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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
6f2750fe | 2 | Copyright (C) 1993-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
352 | ((ABI) == N32_ABI \ | |
353 | || (ABI) == N64_ABI \ | |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
252b5132 | 946 | \f |
4d7206a2 RS |
947 | /* The expansion of many macros depends on the type of symbol that |
948 | they refer to. For example, when generating position-dependent code, | |
949 | a macro that refers to a symbol may have two different expansions, | |
950 | one which uses GP-relative addresses and one which uses absolute | |
951 | addresses. When generating SVR4-style PIC, a macro may have | |
952 | different expansions for local and global symbols. | |
953 | ||
954 | We handle these situations by generating both sequences and putting | |
955 | them in variant frags. In position-dependent code, the first sequence | |
956 | will be the GP-relative one and the second sequence will be the | |
957 | absolute one. In SVR4 PIC, the first sequence will be for global | |
958 | symbols and the second will be for local symbols. | |
959 | ||
584892a6 RS |
960 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
961 | SECOND are the lengths of the two sequences in bytes. These fields | |
962 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
963 | the subtype has the following flags: | |
4d7206a2 | 964 | |
584892a6 RS |
965 | RELAX_USE_SECOND |
966 | Set if it has been decided that we should use the second | |
967 | sequence instead of the first. | |
968 | ||
969 | RELAX_SECOND_LONGER | |
970 | Set in the first variant frag if the macro's second implementation | |
971 | is longer than its first. This refers to the macro as a whole, | |
972 | not an individual relaxation. | |
973 | ||
974 | RELAX_NOMACRO | |
975 | Set in the first variant frag if the macro appeared in a .set nomacro | |
976 | block and if one alternative requires a warning but the other does not. | |
977 | ||
978 | RELAX_DELAY_SLOT | |
979 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
980 | delay slot. | |
4d7206a2 | 981 | |
df58fc94 RS |
982 | RELAX_DELAY_SLOT_16BIT |
983 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
984 | 16-bit instruction. | |
985 | ||
986 | RELAX_DELAY_SLOT_SIZE_FIRST | |
987 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
988 | the macro is of the wrong size for the branch delay slot. | |
989 | ||
990 | RELAX_DELAY_SLOT_SIZE_SECOND | |
991 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
992 | the macro is of the wrong size for the branch delay slot. | |
993 | ||
4d7206a2 RS |
994 | The frag's "opcode" points to the first fixup for relaxable code. |
995 | ||
996 | Relaxable macros are generated using a sequence such as: | |
997 | ||
998 | relax_start (SYMBOL); | |
999 | ... generate first expansion ... | |
1000 | relax_switch (); | |
1001 | ... generate second expansion ... | |
1002 | relax_end (); | |
1003 | ||
1004 | The code and fixups for the unwanted alternative are discarded | |
1005 | by md_convert_frag. */ | |
584892a6 | 1006 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1007 | |
584892a6 RS |
1008 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1009 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1010 | #define RELAX_USE_SECOND 0x10000 | |
1011 | #define RELAX_SECOND_LONGER 0x20000 | |
1012 | #define RELAX_NOMACRO 0x40000 | |
1013 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1014 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1015 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1016 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1017 | |
4a6a3df4 AO |
1018 | /* Branch without likely bit. If label is out of range, we turn: |
1019 | ||
1020 | beq reg1, reg2, label | |
1021 | delay slot | |
1022 | ||
1023 | into | |
1024 | ||
1025 | bne reg1, reg2, 0f | |
1026 | nop | |
1027 | j label | |
1028 | 0: delay slot | |
1029 | ||
1030 | with the following opcode replacements: | |
1031 | ||
1032 | beq <-> bne | |
1033 | blez <-> bgtz | |
1034 | bltz <-> bgez | |
1035 | bc1f <-> bc1t | |
1036 | ||
1037 | bltzal <-> bgezal (with jal label instead of j label) | |
1038 | ||
1039 | Even though keeping the delay slot instruction in the delay slot of | |
1040 | the branch would be more efficient, it would be very tricky to do | |
1041 | correctly, because we'd have to introduce a variable frag *after* | |
1042 | the delay slot instruction, and expand that instead. Let's do it | |
1043 | the easy way for now, even if the branch-not-taken case now costs | |
1044 | one additional instruction. Out-of-range branches are not supposed | |
1045 | to be common, anyway. | |
1046 | ||
1047 | Branch likely. If label is out of range, we turn: | |
1048 | ||
1049 | beql reg1, reg2, label | |
1050 | delay slot (annulled if branch not taken) | |
1051 | ||
1052 | into | |
1053 | ||
1054 | beql reg1, reg2, 1f | |
1055 | nop | |
1056 | beql $0, $0, 2f | |
1057 | nop | |
1058 | 1: j[al] label | |
1059 | delay slot (executed only if branch taken) | |
1060 | 2: | |
1061 | ||
1062 | It would be possible to generate a shorter sequence by losing the | |
1063 | likely bit, generating something like: | |
b34976b6 | 1064 | |
4a6a3df4 AO |
1065 | bne reg1, reg2, 0f |
1066 | nop | |
1067 | j[al] label | |
1068 | delay slot (executed only if branch taken) | |
1069 | 0: | |
1070 | ||
1071 | beql -> bne | |
1072 | bnel -> beq | |
1073 | blezl -> bgtz | |
1074 | bgtzl -> blez | |
1075 | bltzl -> bgez | |
1076 | bgezl -> bltz | |
1077 | bc1fl -> bc1t | |
1078 | bc1tl -> bc1f | |
1079 | ||
1080 | bltzall -> bgezal (with jal label instead of j label) | |
1081 | bgezall -> bltzal (ditto) | |
1082 | ||
1083 | ||
1084 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1085 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1086 | ((relax_substateT) \ | |
1087 | (0xc0000000 \ | |
1088 | | ((at) & 0x1f) \ | |
1089 | | ((toofar) ? 0x20 : 0) \ | |
1090 | | ((link) ? 0x40 : 0) \ | |
1091 | | ((likely) ? 0x80 : 0) \ | |
1092 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1093 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1094 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1095 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1096 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1097 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1098 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1099 | |
252b5132 RH |
1100 | /* For mips16 code, we use an entirely different form of relaxation. |
1101 | mips16 supports two versions of most instructions which take | |
1102 | immediate values: a small one which takes some small value, and a | |
1103 | larger one which takes a 16 bit value. Since branches also follow | |
1104 | this pattern, relaxing these values is required. | |
1105 | ||
1106 | We can assemble both mips16 and normal MIPS code in a single | |
1107 | object. Therefore, we need to support this type of relaxation at | |
1108 | the same time that we support the relaxation described above. We | |
1109 | use the high bit of the subtype field to distinguish these cases. | |
1110 | ||
1111 | The information we store for this type of relaxation is the | |
1112 | argument code found in the opcode file for this relocation, whether | |
1113 | the user explicitly requested a small or extended form, and whether | |
1114 | the relocation is in a jump or jal delay slot. That tells us the | |
1115 | size of the value, and how it should be stored. We also store | |
1116 | whether the fragment is considered to be extended or not. We also | |
1117 | store whether this is known to be a branch to a different section, | |
1118 | whether we have tried to relax this frag yet, and whether we have | |
1119 | ever extended a PC relative fragment because of a shift count. */ | |
1120 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1121 | (0x80000000 \ | |
1122 | | ((type) & 0xff) \ | |
1123 | | ((small) ? 0x100 : 0) \ | |
1124 | | ((ext) ? 0x200 : 0) \ | |
1125 | | ((dslot) ? 0x400 : 0) \ | |
1126 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1127 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1128 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1129 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1130 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1131 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1132 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1133 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1134 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1135 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1136 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1137 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1138 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1139 | |
df58fc94 RS |
1140 | /* For microMIPS code, we use relaxation similar to one we use for |
1141 | MIPS16 code. Some instructions that take immediate values support | |
1142 | two encodings: a small one which takes some small value, and a | |
1143 | larger one which takes a 16 bit value. As some branches also follow | |
1144 | this pattern, relaxing these values is required. | |
1145 | ||
1146 | We can assemble both microMIPS and normal MIPS code in a single | |
1147 | object. Therefore, we need to support this type of relaxation at | |
1148 | the same time that we support the relaxation described above. We | |
1149 | use one of the high bits of the subtype field to distinguish these | |
1150 | cases. | |
1151 | ||
1152 | The information we store for this type of relaxation is the argument | |
1153 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1154 | selected as the assembler temporary, whether the branch is |
1155 | unconditional, whether it is compact, whether it stores the link | |
1156 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1157 | branches to a sequence of instructions is enabled, and whether the | |
1158 | displacement of a branch is too large to fit as an immediate argument | |
1159 | of a 16-bit and a 32-bit branch, respectively. */ | |
1160 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1161 | relax32, toofar16, toofar32) \ | |
1162 | (0x40000000 \ | |
1163 | | ((type) & 0xff) \ | |
1164 | | (((at) & 0x1f) << 8) \ | |
1165 | | ((uncond) ? 0x2000 : 0) \ | |
1166 | | ((compact) ? 0x4000 : 0) \ | |
1167 | | ((link) ? 0x8000 : 0) \ | |
1168 | | ((relax32) ? 0x10000 : 0) \ | |
1169 | | ((toofar16) ? 0x20000 : 0) \ | |
1170 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1171 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1172 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1173 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1174 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1175 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1176 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1177 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1178 | ||
1179 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1180 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1181 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1182 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1183 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1184 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1185 | |
43c0598f RS |
1186 | /* Sign-extend 16-bit value X. */ |
1187 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1188 | ||
885add95 CD |
1189 | /* Is the given value a sign-extended 32-bit value? */ |
1190 | #define IS_SEXT_32BIT_NUM(x) \ | |
1191 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1192 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1193 | ||
1194 | /* Is the given value a sign-extended 16-bit value? */ | |
1195 | #define IS_SEXT_16BIT_NUM(x) \ | |
1196 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1197 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1198 | ||
df58fc94 RS |
1199 | /* Is the given value a sign-extended 12-bit value? */ |
1200 | #define IS_SEXT_12BIT_NUM(x) \ | |
1201 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1202 | ||
7f3c4072 CM |
1203 | /* Is the given value a sign-extended 9-bit value? */ |
1204 | #define IS_SEXT_9BIT_NUM(x) \ | |
1205 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1206 | ||
2051e8c4 MR |
1207 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1208 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1209 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1210 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1211 | ||
bf12938e RS |
1212 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1213 | SHIFT places. */ | |
1214 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1215 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1216 | ||
bf12938e | 1217 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1218 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1219 | (!(MICROMIPS) \ | |
1220 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1221 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1222 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1223 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1224 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1225 | MIPS16OP_MASK_##FIELD, \ | |
1226 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1227 | |
1228 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1229 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1230 | \f |
df58fc94 RS |
1231 | /* Whether or not we are emitting a branch-likely macro. */ |
1232 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1233 | ||
4d7206a2 RS |
1234 | /* Global variables used when generating relaxable macros. See the |
1235 | comment above RELAX_ENCODE for more details about how relaxation | |
1236 | is used. */ | |
1237 | static struct { | |
1238 | /* 0 if we're not emitting a relaxable macro. | |
1239 | 1 if we're emitting the first of the two relaxation alternatives. | |
1240 | 2 if we're emitting the second alternative. */ | |
1241 | int sequence; | |
1242 | ||
1243 | /* The first relaxable fixup in the current frag. (In other words, | |
1244 | the first fixup that refers to relaxable code.) */ | |
1245 | fixS *first_fixup; | |
1246 | ||
1247 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1248 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1249 | unsigned int sizes[2]; | |
1250 | ||
1251 | /* The symbol on which the choice of sequence depends. */ | |
1252 | symbolS *symbol; | |
1253 | } mips_relax; | |
252b5132 | 1254 | \f |
584892a6 RS |
1255 | /* Global variables used to decide whether a macro needs a warning. */ |
1256 | static struct { | |
1257 | /* True if the macro is in a branch delay slot. */ | |
1258 | bfd_boolean delay_slot_p; | |
1259 | ||
df58fc94 RS |
1260 | /* Set to the length in bytes required if the macro is in a delay slot |
1261 | that requires a specific length of instruction, otherwise zero. */ | |
1262 | unsigned int delay_slot_length; | |
1263 | ||
584892a6 RS |
1264 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1265 | in bytes and sizes[1] is the length of the second alternative. | |
1266 | For non-relaxable macros, both elements give the length of the | |
1267 | macro in bytes. */ | |
1268 | unsigned int sizes[2]; | |
1269 | ||
df58fc94 RS |
1270 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1271 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1272 | is the length of the first instruction of the second alternative. | |
1273 | For non-relaxable macros, both elements give the length of the first | |
1274 | instruction in bytes. | |
1275 | ||
1276 | Set to zero if we haven't yet seen the first instruction. */ | |
1277 | unsigned int first_insn_sizes[2]; | |
1278 | ||
1279 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1280 | first alternative and insns[1] is the number of instructions for the | |
1281 | second alternative. | |
1282 | ||
1283 | For non-relaxable macros, both elements give the number of | |
1284 | instructions for the macro. */ | |
1285 | unsigned int insns[2]; | |
1286 | ||
584892a6 RS |
1287 | /* The first variant frag for this macro. */ |
1288 | fragS *first_frag; | |
1289 | } mips_macro_warning; | |
1290 | \f | |
252b5132 RH |
1291 | /* Prototypes for static functions. */ |
1292 | ||
252b5132 RH |
1293 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1294 | ||
b34976b6 | 1295 | static void append_insn |
df58fc94 RS |
1296 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1297 | bfd_boolean expansionp); | |
7d10b47d | 1298 | static void mips_no_prev_insn (void); |
c67a084a | 1299 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1300 | static void mips16_macro_build |
03ea81db | 1301 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1302 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1303 | static void macro_start (void); |
1304 | static void macro_end (void); | |
833794fc | 1305 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1306 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1307 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1308 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1309 | static void mips16_immed |
43c0598f RS |
1310 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1311 | unsigned int, unsigned long *); | |
5e0116d5 | 1312 | static size_t my_getSmallExpression |
17a2f251 TS |
1313 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1314 | static void my_getExpression (expressionS *, char *); | |
1315 | static void s_align (int); | |
1316 | static void s_change_sec (int); | |
1317 | static void s_change_section (int); | |
1318 | static void s_cons (int); | |
1319 | static void s_float_cons (int); | |
1320 | static void s_mips_globl (int); | |
1321 | static void s_option (int); | |
1322 | static void s_mipsset (int); | |
1323 | static void s_abicalls (int); | |
1324 | static void s_cpload (int); | |
1325 | static void s_cpsetup (int); | |
1326 | static void s_cplocal (int); | |
1327 | static void s_cprestore (int); | |
1328 | static void s_cpreturn (int); | |
741d6ea8 JM |
1329 | static void s_dtprelword (int); |
1330 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1331 | static void s_tprelword (int); |
1332 | static void s_tpreldword (int); | |
17a2f251 TS |
1333 | static void s_gpvalue (int); |
1334 | static void s_gpword (int); | |
1335 | static void s_gpdword (int); | |
a3f278e2 | 1336 | static void s_ehword (int); |
17a2f251 TS |
1337 | static void s_cpadd (int); |
1338 | static void s_insn (int); | |
ba92f887 | 1339 | static void s_nan (int); |
919731af | 1340 | static void s_module (int); |
17a2f251 TS |
1341 | static void s_mips_ent (int); |
1342 | static void s_mips_end (int); | |
1343 | static void s_mips_frame (int); | |
1344 | static void s_mips_mask (int reg_type); | |
1345 | static void s_mips_stab (int); | |
1346 | static void s_mips_weakext (int); | |
1347 | static void s_mips_file (int); | |
1348 | static void s_mips_loc (int); | |
1349 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1350 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1351 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1352 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1353 | static void file_mips_check_options (void); |
e7af610e NC |
1354 | |
1355 | /* Table and functions used to map between CPU/ISA names, and | |
1356 | ISA levels, and CPU numbers. */ | |
1357 | ||
e972090a NC |
1358 | struct mips_cpu_info |
1359 | { | |
e7af610e | 1360 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1361 | int flags; /* MIPS_CPU_* flags. */ |
1362 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1363 | int isa; /* ISA level. */ |
1364 | int cpu; /* CPU number (default CPU if ISA). */ | |
1365 | }; | |
1366 | ||
ad3fea08 | 1367 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1368 | |
17a2f251 TS |
1369 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1370 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1371 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1372 | \f |
c31f3936 RS |
1373 | /* Command-line options. */ |
1374 | const char *md_shortopts = "O::g::G:"; | |
1375 | ||
1376 | enum options | |
1377 | { | |
1378 | OPTION_MARCH = OPTION_MD_BASE, | |
1379 | OPTION_MTUNE, | |
1380 | OPTION_MIPS1, | |
1381 | OPTION_MIPS2, | |
1382 | OPTION_MIPS3, | |
1383 | OPTION_MIPS4, | |
1384 | OPTION_MIPS5, | |
1385 | OPTION_MIPS32, | |
1386 | OPTION_MIPS64, | |
1387 | OPTION_MIPS32R2, | |
ae52f483 AB |
1388 | OPTION_MIPS32R3, |
1389 | OPTION_MIPS32R5, | |
7361da2c | 1390 | OPTION_MIPS32R6, |
c31f3936 | 1391 | OPTION_MIPS64R2, |
ae52f483 AB |
1392 | OPTION_MIPS64R3, |
1393 | OPTION_MIPS64R5, | |
7361da2c | 1394 | OPTION_MIPS64R6, |
c31f3936 RS |
1395 | OPTION_MIPS16, |
1396 | OPTION_NO_MIPS16, | |
1397 | OPTION_MIPS3D, | |
1398 | OPTION_NO_MIPS3D, | |
1399 | OPTION_MDMX, | |
1400 | OPTION_NO_MDMX, | |
1401 | OPTION_DSP, | |
1402 | OPTION_NO_DSP, | |
1403 | OPTION_MT, | |
1404 | OPTION_NO_MT, | |
1405 | OPTION_VIRT, | |
1406 | OPTION_NO_VIRT, | |
56d438b1 CF |
1407 | OPTION_MSA, |
1408 | OPTION_NO_MSA, | |
c31f3936 RS |
1409 | OPTION_SMARTMIPS, |
1410 | OPTION_NO_SMARTMIPS, | |
1411 | OPTION_DSPR2, | |
1412 | OPTION_NO_DSPR2, | |
1413 | OPTION_EVA, | |
1414 | OPTION_NO_EVA, | |
7d64c587 AB |
1415 | OPTION_XPA, |
1416 | OPTION_NO_XPA, | |
c31f3936 RS |
1417 | OPTION_MICROMIPS, |
1418 | OPTION_NO_MICROMIPS, | |
1419 | OPTION_MCU, | |
1420 | OPTION_NO_MCU, | |
1421 | OPTION_COMPAT_ARCH_BASE, | |
1422 | OPTION_M4650, | |
1423 | OPTION_NO_M4650, | |
1424 | OPTION_M4010, | |
1425 | OPTION_NO_M4010, | |
1426 | OPTION_M4100, | |
1427 | OPTION_NO_M4100, | |
1428 | OPTION_M3900, | |
1429 | OPTION_NO_M3900, | |
1430 | OPTION_M7000_HILO_FIX, | |
1431 | OPTION_MNO_7000_HILO_FIX, | |
1432 | OPTION_FIX_24K, | |
1433 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1434 | OPTION_FIX_RM7000, |
1435 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1436 | OPTION_FIX_LOONGSON2F_JUMP, |
1437 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1438 | OPTION_FIX_LOONGSON2F_NOP, | |
1439 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1440 | OPTION_FIX_VR4120, | |
1441 | OPTION_NO_FIX_VR4120, | |
1442 | OPTION_FIX_VR4130, | |
1443 | OPTION_NO_FIX_VR4130, | |
1444 | OPTION_FIX_CN63XXP1, | |
1445 | OPTION_NO_FIX_CN63XXP1, | |
1446 | OPTION_TRAP, | |
1447 | OPTION_BREAK, | |
1448 | OPTION_EB, | |
1449 | OPTION_EL, | |
1450 | OPTION_FP32, | |
1451 | OPTION_GP32, | |
1452 | OPTION_CONSTRUCT_FLOATS, | |
1453 | OPTION_NO_CONSTRUCT_FLOATS, | |
1454 | OPTION_FP64, | |
351cdf24 | 1455 | OPTION_FPXX, |
c31f3936 RS |
1456 | OPTION_GP64, |
1457 | OPTION_RELAX_BRANCH, | |
1458 | OPTION_NO_RELAX_BRANCH, | |
833794fc MR |
1459 | OPTION_INSN32, |
1460 | OPTION_NO_INSN32, | |
c31f3936 RS |
1461 | OPTION_MSHARED, |
1462 | OPTION_MNO_SHARED, | |
1463 | OPTION_MSYM32, | |
1464 | OPTION_MNO_SYM32, | |
1465 | OPTION_SOFT_FLOAT, | |
1466 | OPTION_HARD_FLOAT, | |
1467 | OPTION_SINGLE_FLOAT, | |
1468 | OPTION_DOUBLE_FLOAT, | |
1469 | OPTION_32, | |
c31f3936 RS |
1470 | OPTION_CALL_SHARED, |
1471 | OPTION_CALL_NONPIC, | |
1472 | OPTION_NON_SHARED, | |
1473 | OPTION_XGOT, | |
1474 | OPTION_MABI, | |
1475 | OPTION_N32, | |
1476 | OPTION_64, | |
1477 | OPTION_MDEBUG, | |
1478 | OPTION_NO_MDEBUG, | |
1479 | OPTION_PDR, | |
1480 | OPTION_NO_PDR, | |
1481 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1482 | OPTION_NAN, |
351cdf24 MF |
1483 | OPTION_ODD_SPREG, |
1484 | OPTION_NO_ODD_SPREG, | |
c31f3936 RS |
1485 | OPTION_END_OF_ENUM |
1486 | }; | |
1487 | ||
1488 | struct option md_longopts[] = | |
1489 | { | |
1490 | /* Options which specify architecture. */ | |
1491 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1492 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1493 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1494 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1495 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1496 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1497 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1498 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1499 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1500 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1501 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1502 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1503 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1504 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1505 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1506 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1507 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1508 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1509 | |
1510 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1511 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1512 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1513 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1514 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1515 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1516 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1517 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1518 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1519 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1520 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1521 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1522 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1523 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1524 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1525 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1526 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1527 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1528 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1529 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1530 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1531 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1532 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1533 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1534 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1535 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1536 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
c31f3936 RS |
1537 | |
1538 | /* Old-style architecture options. Don't add more of these. */ | |
1539 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1540 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1541 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1542 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1543 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1544 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1545 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1546 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1547 | ||
1548 | /* Options which enable bug fixes. */ | |
1549 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1550 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1551 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1552 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1553 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1554 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1555 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1556 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1557 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1558 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1559 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1560 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1561 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1562 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1563 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1564 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1565 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1566 | ||
1567 | /* Miscellaneous options. */ | |
1568 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1569 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1570 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1571 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1572 | {"EB", no_argument, NULL, OPTION_EB}, | |
1573 | {"EL", no_argument, NULL, OPTION_EL}, | |
1574 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1575 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1576 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1577 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1578 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1579 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1580 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1581 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1582 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
833794fc MR |
1583 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1584 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1585 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1586 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1587 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1588 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1589 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1590 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1591 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1592 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1593 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1594 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1595 | |
1596 | /* Strictly speaking this next option is ELF specific, | |
1597 | but we allow it for other ports as well in order to | |
1598 | make testing easier. */ | |
1599 | {"32", no_argument, NULL, OPTION_32}, | |
1600 | ||
1601 | /* ELF-specific options. */ | |
c31f3936 RS |
1602 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1603 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1604 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1605 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1606 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1607 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1608 | {"n32", no_argument, NULL, OPTION_N32}, | |
1609 | {"64", no_argument, NULL, OPTION_64}, | |
1610 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1611 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1612 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1613 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1614 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1615 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1616 | |
1617 | {NULL, no_argument, NULL, 0} | |
1618 | }; | |
1619 | size_t md_longopts_size = sizeof (md_longopts); | |
1620 | \f | |
c6278170 RS |
1621 | /* Information about either an Application Specific Extension or an |
1622 | optional architecture feature that, for simplicity, we treat in the | |
1623 | same way as an ASE. */ | |
1624 | struct mips_ase | |
1625 | { | |
1626 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1627 | const char *name; | |
1628 | ||
1629 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1630 | and 64-bit architectures, the flags here refer to the subset that | |
1631 | is available on both. */ | |
1632 | unsigned int flags; | |
1633 | ||
1634 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1635 | architectures but that are not included in FLAGS. */ | |
1636 | unsigned int flags64; | |
1637 | ||
1638 | /* The command-line options that turn the ASE on and off. */ | |
1639 | int option_on; | |
1640 | int option_off; | |
1641 | ||
1642 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1643 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1644 | int mips32_rev; | |
1645 | int mips64_rev; | |
1646 | int micromips32_rev; | |
1647 | int micromips64_rev; | |
7361da2c AB |
1648 | |
1649 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1650 | been removed. */ | |
1651 | int rem_rev; | |
c6278170 RS |
1652 | }; |
1653 | ||
1654 | /* A table of all supported ASEs. */ | |
1655 | static const struct mips_ase mips_ases[] = { | |
1656 | { "dsp", ASE_DSP, ASE_DSP64, | |
1657 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1658 | 2, 2, 2, 2, |
1659 | -1 }, | |
c6278170 RS |
1660 | |
1661 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1662 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1663 | 2, 2, 2, 2, |
1664 | -1 }, | |
c6278170 RS |
1665 | |
1666 | { "eva", ASE_EVA, 0, | |
1667 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1668 | 2, 2, 2, 2, |
1669 | -1 }, | |
c6278170 RS |
1670 | |
1671 | { "mcu", ASE_MCU, 0, | |
1672 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1673 | 2, 2, 2, 2, |
1674 | -1 }, | |
c6278170 RS |
1675 | |
1676 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1677 | { "mdmx", ASE_MDMX, 0, | |
1678 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1679 | -1, 1, -1, -1, |
1680 | 6 }, | |
c6278170 RS |
1681 | |
1682 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1683 | { "mips3d", ASE_MIPS3D, 0, | |
1684 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1685 | 2, 1, -1, -1, |
1686 | 6 }, | |
c6278170 RS |
1687 | |
1688 | { "mt", ASE_MT, 0, | |
1689 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1690 | 2, 2, -1, -1, |
1691 | -1 }, | |
c6278170 RS |
1692 | |
1693 | { "smartmips", ASE_SMARTMIPS, 0, | |
1694 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1695 | 1, -1, -1, -1, |
1696 | 6 }, | |
c6278170 RS |
1697 | |
1698 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1699 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1700 | 2, 2, 2, 2, |
1701 | -1 }, | |
56d438b1 CF |
1702 | |
1703 | { "msa", ASE_MSA, ASE_MSA64, | |
1704 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1705 | 2, 2, 2, 2, |
1706 | -1 }, | |
7d64c587 AB |
1707 | |
1708 | { "xpa", ASE_XPA, 0, | |
1709 | OPTION_XPA, OPTION_NO_XPA, | |
7361da2c AB |
1710 | 2, 2, -1, -1, |
1711 | -1 }, | |
c6278170 RS |
1712 | }; |
1713 | ||
1714 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1715 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1716 | |
1717 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1718 | static const unsigned int mips_ase_groups[] = { | |
1719 | ASE_DSP | ASE_DSPR2 | |
1720 | }; | |
1721 | \f | |
252b5132 RH |
1722 | /* Pseudo-op table. |
1723 | ||
1724 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1725 | should be defined here, but are currently unsupported: .alias, | |
1726 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1727 | ||
1728 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1729 | specific to the type of debugging information being generated, and | |
1730 | should be defined by the object format: .aent, .begin, .bend, | |
1731 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1732 | .vreg. | |
1733 | ||
1734 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1735 | not MIPS CPU specific, but are also not specific to the object file | |
1736 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1737 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1738 | |
e972090a NC |
1739 | static const pseudo_typeS mips_pseudo_table[] = |
1740 | { | |
beae10d5 | 1741 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1742 | {"option", s_option, 0}, |
1743 | {"set", s_mipsset, 0}, | |
1744 | {"rdata", s_change_sec, 'r'}, | |
1745 | {"sdata", s_change_sec, 's'}, | |
1746 | {"livereg", s_ignore, 0}, | |
1747 | {"abicalls", s_abicalls, 0}, | |
1748 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1749 | {"cpsetup", s_cpsetup, 0}, |
1750 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1751 | {"cprestore", s_cprestore, 0}, |
6478892d | 1752 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1753 | {"dtprelword", s_dtprelword, 0}, |
1754 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1755 | {"tprelword", s_tprelword, 0}, |
1756 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1757 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1758 | {"gpword", s_gpword, 0}, |
10181a0d | 1759 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1760 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1761 | {"cpadd", s_cpadd, 0}, |
1762 | {"insn", s_insn, 0}, | |
ba92f887 | 1763 | {"nan", s_nan, 0}, |
919731af | 1764 | {"module", s_module, 0}, |
252b5132 | 1765 | |
beae10d5 | 1766 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1767 | chips. */ |
38a57ae7 | 1768 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1769 | {"bss", s_change_sec, 'b'}, |
1770 | {"err", s_err, 0}, | |
1771 | {"half", s_cons, 1}, | |
1772 | {"dword", s_cons, 3}, | |
1773 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1774 | {"origin", s_org, 0}, |
1775 | {"repeat", s_rept, 0}, | |
252b5132 | 1776 | |
998b3c36 MR |
1777 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1778 | {"sbss", s_change_sec, 'B'}, | |
1779 | ||
beae10d5 | 1780 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1781 | here for one reason or another. */ |
1782 | {"align", s_align, 0}, | |
1783 | {"byte", s_cons, 0}, | |
1784 | {"data", s_change_sec, 'd'}, | |
1785 | {"double", s_float_cons, 'd'}, | |
1786 | {"float", s_float_cons, 'f'}, | |
1787 | {"globl", s_mips_globl, 0}, | |
1788 | {"global", s_mips_globl, 0}, | |
1789 | {"hword", s_cons, 1}, | |
1790 | {"int", s_cons, 2}, | |
1791 | {"long", s_cons, 2}, | |
1792 | {"octa", s_cons, 4}, | |
1793 | {"quad", s_cons, 3}, | |
cca86cc8 | 1794 | {"section", s_change_section, 0}, |
252b5132 RH |
1795 | {"short", s_cons, 1}, |
1796 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1797 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1798 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1799 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1800 | {"text", s_change_sec, 't'}, |
1801 | {"word", s_cons, 2}, | |
add56521 | 1802 | |
add56521 | 1803 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1804 | |
43841e91 | 1805 | { NULL, NULL, 0 }, |
252b5132 RH |
1806 | }; |
1807 | ||
e972090a NC |
1808 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1809 | { | |
beae10d5 KH |
1810 | /* These pseudo-ops should be defined by the object file format. |
1811 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1812 | {"aent", s_mips_ent, 1}, |
1813 | {"bgnb", s_ignore, 0}, | |
1814 | {"end", s_mips_end, 0}, | |
1815 | {"endb", s_ignore, 0}, | |
1816 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1817 | {"file", s_mips_file, 0}, |
252b5132 RH |
1818 | {"fmask", s_mips_mask, 'F'}, |
1819 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1820 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1821 | {"mask", s_mips_mask, 'R'}, |
1822 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1823 | { NULL, NULL, 0 }, |
252b5132 RH |
1824 | }; |
1825 | ||
3ae8dd8d MR |
1826 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1827 | purpose of the `.dc.a' internal pseudo-op. */ | |
1828 | ||
1829 | int | |
1830 | mips_address_bytes (void) | |
1831 | { | |
919731af | 1832 | file_mips_check_options (); |
3ae8dd8d MR |
1833 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1834 | } | |
1835 | ||
17a2f251 | 1836 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1837 | |
1838 | void | |
17a2f251 | 1839 | mips_pop_insert (void) |
252b5132 RH |
1840 | { |
1841 | pop_insert (mips_pseudo_table); | |
1842 | if (! ECOFF_DEBUGGING) | |
1843 | pop_insert (mips_nonecoff_pseudo_table); | |
1844 | } | |
1845 | \f | |
1846 | /* Symbols labelling the current insn. */ | |
1847 | ||
e972090a NC |
1848 | struct insn_label_list |
1849 | { | |
252b5132 RH |
1850 | struct insn_label_list *next; |
1851 | symbolS *label; | |
1852 | }; | |
1853 | ||
252b5132 | 1854 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1855 | #define label_list tc_segment_info_data.labels |
252b5132 | 1856 | |
17a2f251 | 1857 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1858 | static void mips_mark_labels (void); |
1859 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1860 | |
1861 | static inline void | |
17a2f251 | 1862 | mips_clear_insn_labels (void) |
252b5132 | 1863 | { |
ed9e98c2 | 1864 | struct insn_label_list **pl; |
a8dbcb85 | 1865 | segment_info_type *si; |
252b5132 | 1866 | |
a8dbcb85 TS |
1867 | if (now_seg) |
1868 | { | |
1869 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1870 | ; | |
3739860c | 1871 | |
a8dbcb85 TS |
1872 | si = seg_info (now_seg); |
1873 | *pl = si->label_list; | |
1874 | si->label_list = NULL; | |
1875 | } | |
252b5132 | 1876 | } |
a8dbcb85 | 1877 | |
df58fc94 RS |
1878 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1879 | ||
1880 | static inline void | |
1881 | mips_mark_labels (void) | |
1882 | { | |
1883 | if (HAVE_CODE_COMPRESSION) | |
1884 | mips_compressed_mark_labels (); | |
1885 | } | |
252b5132 RH |
1886 | \f |
1887 | static char *expr_end; | |
1888 | ||
e423441d | 1889 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1890 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1891 | |
1892 | static expressionS imm_expr; | |
252b5132 | 1893 | |
77bd4346 RS |
1894 | /* The relocatable field in an instruction and the relocs associated |
1895 | with it. These variables are used for instructions like LUI and | |
1896 | JAL as well as true offsets. They are also used for address | |
1897 | operands in macros. */ | |
252b5132 | 1898 | |
77bd4346 | 1899 | static expressionS offset_expr; |
f6688943 TS |
1900 | static bfd_reloc_code_real_type offset_reloc[3] |
1901 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1902 | |
df58fc94 RS |
1903 | /* This is set to the resulting size of the instruction to be produced |
1904 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1905 | explicit size is supplied. */ | |
252b5132 | 1906 | |
df58fc94 | 1907 | static unsigned int forced_insn_length; |
252b5132 | 1908 | |
e1b47bd5 RS |
1909 | /* True if we are assembling an instruction. All dot symbols defined during |
1910 | this time should be treated as code labels. */ | |
1911 | ||
1912 | static bfd_boolean mips_assembling_insn; | |
1913 | ||
ecb4347a DJ |
1914 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1915 | ECOFF debugging. */ | |
252b5132 RH |
1916 | |
1917 | static segT pdr_seg; | |
252b5132 | 1918 | |
e013f690 TS |
1919 | /* The default target format to use. */ |
1920 | ||
aeffff67 RS |
1921 | #if defined (TE_FreeBSD) |
1922 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1923 | #elif defined (TE_TMIPS) | |
1924 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1925 | #else | |
1926 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1927 | #endif | |
1928 | ||
e013f690 | 1929 | const char * |
17a2f251 | 1930 | mips_target_format (void) |
e013f690 TS |
1931 | { |
1932 | switch (OUTPUT_FLAVOR) | |
1933 | { | |
e013f690 | 1934 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1935 | #ifdef TE_VXWORKS |
1936 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1937 | return (target_big_endian | |
1938 | ? "elf32-bigmips-vxworks" | |
1939 | : "elf32-littlemips-vxworks"); | |
1940 | #endif | |
e013f690 | 1941 | return (target_big_endian |
cfe86eaa | 1942 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1943 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1944 | : (HAVE_NEWABI |
aeffff67 RS |
1945 | ? ELF_TARGET ("elf32-n", "big") |
1946 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1947 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1948 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1949 | : (HAVE_NEWABI |
aeffff67 RS |
1950 | ? ELF_TARGET ("elf32-n", "little") |
1951 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1952 | default: |
1953 | abort (); | |
1954 | return NULL; | |
1955 | } | |
1956 | } | |
1957 | ||
c6278170 RS |
1958 | /* Return the ISA revision that is currently in use, or 0 if we are |
1959 | generating code for MIPS V or below. */ | |
1960 | ||
1961 | static int | |
1962 | mips_isa_rev (void) | |
1963 | { | |
1964 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1965 | return 2; | |
1966 | ||
ae52f483 AB |
1967 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
1968 | return 3; | |
1969 | ||
1970 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
1971 | return 5; | |
1972 | ||
7361da2c AB |
1973 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
1974 | return 6; | |
1975 | ||
c6278170 RS |
1976 | /* microMIPS implies revision 2 or above. */ |
1977 | if (mips_opts.micromips) | |
1978 | return 2; | |
1979 | ||
1980 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1981 | return 1; | |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
1986 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1987 | ||
1988 | static unsigned int | |
1989 | mips_ase_mask (unsigned int flags) | |
1990 | { | |
1991 | unsigned int i; | |
1992 | ||
1993 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1994 | if (flags & mips_ase_groups[i]) | |
1995 | flags |= mips_ase_groups[i]; | |
1996 | return flags; | |
1997 | } | |
1998 | ||
1999 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2000 | appropriate. */ | |
2001 | ||
2002 | static void | |
2003 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2004 | { | |
2005 | const char *base; | |
2006 | int min_rev, size; | |
2007 | static unsigned int warned_isa; | |
2008 | static unsigned int warned_fp32; | |
2009 | ||
2010 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2011 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2012 | else | |
2013 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2014 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2015 | && (warned_isa & ase->flags) != ase->flags) | |
2016 | { | |
2017 | warned_isa |= ase->flags; | |
2018 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2019 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2020 | if (min_rev < 0) | |
1661c76c | 2021 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2022 | " `%s' extension"), size, base, ase->name); |
2023 | else | |
1661c76c | 2024 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2025 | ase->name, base, size, min_rev); |
2026 | } | |
7361da2c AB |
2027 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2028 | && (warned_isa & ase->flags) != ase->flags) | |
2029 | { | |
2030 | warned_isa |= ase->flags; | |
2031 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2032 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2033 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2034 | ase->name, base, size, ase->rem_rev); | |
2035 | } | |
2036 | ||
c6278170 | 2037 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2038 | && mips_opts.fp != 64 |
c6278170 RS |
2039 | && (warned_fp32 & ase->flags) != ase->flags) |
2040 | { | |
2041 | warned_fp32 |= ase->flags; | |
1661c76c | 2042 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2043 | } |
2044 | } | |
2045 | ||
2046 | /* Check all enabled ASEs to see whether they are supported by the | |
2047 | chosen architecture. */ | |
2048 | ||
2049 | static void | |
2050 | mips_check_isa_supports_ases (void) | |
2051 | { | |
2052 | unsigned int i, mask; | |
2053 | ||
2054 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2055 | { | |
2056 | mask = mips_ase_mask (mips_ases[i].flags); | |
2057 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2058 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2059 | } | |
2060 | } | |
2061 | ||
2062 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2063 | that were affected. */ | |
2064 | ||
2065 | static unsigned int | |
919731af | 2066 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2067 | bfd_boolean enabled_p) | |
c6278170 RS |
2068 | { |
2069 | unsigned int mask; | |
2070 | ||
2071 | mask = mips_ase_mask (ase->flags); | |
919731af | 2072 | opts->ase &= ~mask; |
c6278170 | 2073 | if (enabled_p) |
919731af | 2074 | opts->ase |= ase->flags; |
c6278170 RS |
2075 | return mask; |
2076 | } | |
2077 | ||
2078 | /* Return the ASE called NAME, or null if none. */ | |
2079 | ||
2080 | static const struct mips_ase * | |
2081 | mips_lookup_ase (const char *name) | |
2082 | { | |
2083 | unsigned int i; | |
2084 | ||
2085 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2086 | if (strcmp (name, mips_ases[i].name) == 0) | |
2087 | return &mips_ases[i]; | |
2088 | return NULL; | |
2089 | } | |
2090 | ||
df58fc94 | 2091 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2092 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2093 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2094 | |
2095 | static inline unsigned int | |
2096 | micromips_insn_length (const struct mips_opcode *mo) | |
2097 | { | |
2098 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
2099 | } | |
2100 | ||
5c04167a RS |
2101 | /* Return the length of MIPS16 instruction OPCODE. */ |
2102 | ||
2103 | static inline unsigned int | |
2104 | mips16_opcode_length (unsigned long opcode) | |
2105 | { | |
2106 | return (opcode >> 16) == 0 ? 2 : 4; | |
2107 | } | |
2108 | ||
1e915849 RS |
2109 | /* Return the length of instruction INSN. */ |
2110 | ||
2111 | static inline unsigned int | |
2112 | insn_length (const struct mips_cl_insn *insn) | |
2113 | { | |
df58fc94 RS |
2114 | if (mips_opts.micromips) |
2115 | return micromips_insn_length (insn->insn_mo); | |
2116 | else if (mips_opts.mips16) | |
5c04167a | 2117 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2118 | else |
1e915849 | 2119 | return 4; |
1e915849 RS |
2120 | } |
2121 | ||
2122 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2123 | ||
2124 | static void | |
2125 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2126 | { | |
2127 | size_t i; | |
2128 | ||
2129 | insn->insn_mo = mo; | |
1e915849 RS |
2130 | insn->insn_opcode = mo->match; |
2131 | insn->frag = NULL; | |
2132 | insn->where = 0; | |
2133 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2134 | insn->fixp[i] = NULL; | |
2135 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2136 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2137 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2138 | insn->complete_p = 0; |
e407c74b | 2139 | insn->cleared_p = 0; |
1e915849 RS |
2140 | } |
2141 | ||
fc76e730 RS |
2142 | /* Get a list of all the operands in INSN. */ |
2143 | ||
2144 | static const struct mips_operand_array * | |
2145 | insn_operands (const struct mips_cl_insn *insn) | |
2146 | { | |
2147 | if (insn->insn_mo >= &mips_opcodes[0] | |
2148 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2149 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2150 | ||
2151 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2152 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2153 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2154 | ||
2155 | if (insn->insn_mo >= µmips_opcodes[0] | |
2156 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2157 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2158 | ||
2159 | abort (); | |
2160 | } | |
2161 | ||
2162 | /* Get a description of operand OPNO of INSN. */ | |
2163 | ||
2164 | static const struct mips_operand * | |
2165 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2166 | { | |
2167 | const struct mips_operand_array *operands; | |
2168 | ||
2169 | operands = insn_operands (insn); | |
2170 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2171 | abort (); | |
2172 | return operands->operand[opno]; | |
2173 | } | |
2174 | ||
e077a1c8 RS |
2175 | /* Install UVAL as the value of OPERAND in INSN. */ |
2176 | ||
2177 | static inline void | |
2178 | insn_insert_operand (struct mips_cl_insn *insn, | |
2179 | const struct mips_operand *operand, unsigned int uval) | |
2180 | { | |
2181 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
2182 | } | |
2183 | ||
fc76e730 RS |
2184 | /* Extract the value of OPERAND from INSN. */ |
2185 | ||
2186 | static inline unsigned | |
2187 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2188 | const struct mips_operand *operand) | |
2189 | { | |
2190 | return mips_extract_operand (operand, insn->insn_opcode); | |
2191 | } | |
2192 | ||
df58fc94 | 2193 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2194 | |
2195 | static void | |
df58fc94 | 2196 | mips_record_compressed_mode (void) |
742a56fe RS |
2197 | { |
2198 | segment_info_type *si; | |
2199 | ||
2200 | si = seg_info (now_seg); | |
2201 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2202 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2203 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2204 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2205 | } |
2206 | ||
4d68580a RS |
2207 | /* Read a standard MIPS instruction from BUF. */ |
2208 | ||
2209 | static unsigned long | |
2210 | read_insn (char *buf) | |
2211 | { | |
2212 | if (target_big_endian) | |
2213 | return bfd_getb32 ((bfd_byte *) buf); | |
2214 | else | |
2215 | return bfd_getl32 ((bfd_byte *) buf); | |
2216 | } | |
2217 | ||
2218 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2219 | the next byte. */ | |
2220 | ||
2221 | static char * | |
2222 | write_insn (char *buf, unsigned int insn) | |
2223 | { | |
2224 | md_number_to_chars (buf, insn, 4); | |
2225 | return buf + 4; | |
2226 | } | |
2227 | ||
2228 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2229 | has length LENGTH. */ | |
2230 | ||
2231 | static unsigned long | |
2232 | read_compressed_insn (char *buf, unsigned int length) | |
2233 | { | |
2234 | unsigned long insn; | |
2235 | unsigned int i; | |
2236 | ||
2237 | insn = 0; | |
2238 | for (i = 0; i < length; i += 2) | |
2239 | { | |
2240 | insn <<= 16; | |
2241 | if (target_big_endian) | |
2242 | insn |= bfd_getb16 ((char *) buf); | |
2243 | else | |
2244 | insn |= bfd_getl16 ((char *) buf); | |
2245 | buf += 2; | |
2246 | } | |
2247 | return insn; | |
2248 | } | |
2249 | ||
5c04167a RS |
2250 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2251 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2252 | ||
2253 | static char * | |
2254 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2255 | { | |
2256 | unsigned int i; | |
2257 | ||
2258 | for (i = 0; i < length; i += 2) | |
2259 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2260 | return buf + length; | |
2261 | } | |
2262 | ||
1e915849 RS |
2263 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2264 | ||
2265 | static void | |
2266 | install_insn (const struct mips_cl_insn *insn) | |
2267 | { | |
2268 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2269 | if (HAVE_CODE_COMPRESSION) |
2270 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2271 | else |
4d68580a | 2272 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2273 | mips_record_compressed_mode (); |
1e915849 RS |
2274 | } |
2275 | ||
2276 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2277 | and install the opcode in the new location. */ | |
2278 | ||
2279 | static void | |
2280 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2281 | { | |
2282 | size_t i; | |
2283 | ||
2284 | insn->frag = frag; | |
2285 | insn->where = where; | |
2286 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2287 | if (insn->fixp[i] != NULL) | |
2288 | { | |
2289 | insn->fixp[i]->fx_frag = frag; | |
2290 | insn->fixp[i]->fx_where = where; | |
2291 | } | |
2292 | install_insn (insn); | |
2293 | } | |
2294 | ||
2295 | /* Add INSN to the end of the output. */ | |
2296 | ||
2297 | static void | |
2298 | add_fixed_insn (struct mips_cl_insn *insn) | |
2299 | { | |
2300 | char *f = frag_more (insn_length (insn)); | |
2301 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2302 | } | |
2303 | ||
2304 | /* Start a variant frag and move INSN to the start of the variant part, | |
2305 | marking it as fixed. The other arguments are as for frag_var. */ | |
2306 | ||
2307 | static void | |
2308 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2309 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2310 | { | |
2311 | frag_grow (max_chars); | |
2312 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2313 | insn->fixed_p = 1; | |
2314 | frag_var (rs_machine_dependent, max_chars, var, | |
2315 | subtype, symbol, offset, NULL); | |
2316 | } | |
2317 | ||
2318 | /* Insert N copies of INSN into the history buffer, starting at | |
2319 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2320 | ||
2321 | static void | |
2322 | insert_into_history (unsigned int first, unsigned int n, | |
2323 | const struct mips_cl_insn *insn) | |
2324 | { | |
2325 | if (mips_relax.sequence != 2) | |
2326 | { | |
2327 | unsigned int i; | |
2328 | ||
2329 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2330 | if (i >= first + n) | |
2331 | history[i] = history[i - n]; | |
2332 | else | |
2333 | history[i] = *insn; | |
2334 | } | |
2335 | } | |
2336 | ||
e3de51ce RS |
2337 | /* Clear the error in insn_error. */ |
2338 | ||
2339 | static void | |
2340 | clear_insn_error (void) | |
2341 | { | |
2342 | memset (&insn_error, 0, sizeof (insn_error)); | |
2343 | } | |
2344 | ||
2345 | /* Possibly record error message MSG for the current instruction. | |
2346 | If the error is about a particular argument, ARGNUM is the 1-based | |
2347 | number of that argument, otherwise it is 0. FORMAT is the format | |
2348 | of MSG. Return true if MSG was used, false if the current message | |
2349 | was kept. */ | |
2350 | ||
2351 | static bfd_boolean | |
2352 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2353 | const char *msg) | |
2354 | { | |
2355 | if (argnum == 0) | |
2356 | { | |
2357 | /* Give priority to errors against specific arguments, and to | |
2358 | the first whole-instruction message. */ | |
2359 | if (insn_error.msg) | |
2360 | return FALSE; | |
2361 | } | |
2362 | else | |
2363 | { | |
2364 | /* Keep insn_error if it is against a later argument. */ | |
2365 | if (argnum < insn_error.min_argnum) | |
2366 | return FALSE; | |
2367 | ||
2368 | /* If both errors are against the same argument but are different, | |
2369 | give up on reporting a specific error for this argument. | |
2370 | See the comment about mips_insn_error for details. */ | |
2371 | if (argnum == insn_error.min_argnum | |
2372 | && insn_error.msg | |
2373 | && strcmp (insn_error.msg, msg) != 0) | |
2374 | { | |
2375 | insn_error.msg = 0; | |
2376 | insn_error.min_argnum += 1; | |
2377 | return FALSE; | |
2378 | } | |
2379 | } | |
2380 | insn_error.min_argnum = argnum; | |
2381 | insn_error.format = format; | |
2382 | insn_error.msg = msg; | |
2383 | return TRUE; | |
2384 | } | |
2385 | ||
2386 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2387 | as for set_insn_error_format. */ | |
2388 | ||
2389 | static void | |
2390 | set_insn_error (int argnum, const char *msg) | |
2391 | { | |
2392 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2393 | } | |
2394 | ||
2395 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2396 | as for set_insn_error_format. */ | |
2397 | ||
2398 | static void | |
2399 | set_insn_error_i (int argnum, const char *msg, int i) | |
2400 | { | |
2401 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2402 | insn_error.u.i = i; | |
2403 | } | |
2404 | ||
2405 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2406 | are as for set_insn_error_format. */ | |
2407 | ||
2408 | static void | |
2409 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2410 | { | |
2411 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2412 | { | |
2413 | insn_error.u.ss[0] = s1; | |
2414 | insn_error.u.ss[1] = s2; | |
2415 | } | |
2416 | } | |
2417 | ||
2418 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2419 | ||
2420 | static void | |
2421 | report_insn_error (const char *str) | |
2422 | { | |
2423 | const char *msg; | |
2424 | ||
2425 | msg = ACONCAT ((insn_error.msg, " `%s'", NULL)); | |
2426 | switch (insn_error.format) | |
2427 | { | |
2428 | case ERR_FMT_PLAIN: | |
2429 | as_bad (msg, str); | |
2430 | break; | |
2431 | ||
2432 | case ERR_FMT_I: | |
2433 | as_bad (msg, insn_error.u.i, str); | |
2434 | break; | |
2435 | ||
2436 | case ERR_FMT_SS: | |
2437 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2438 | break; | |
2439 | } | |
2440 | } | |
2441 | ||
71400594 RS |
2442 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2443 | the idea is to make it obvious at a glance that each errata is | |
2444 | included. */ | |
2445 | ||
2446 | static void | |
2447 | init_vr4120_conflicts (void) | |
2448 | { | |
2449 | #define CONFLICT(FIRST, SECOND) \ | |
2450 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2451 | ||
2452 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2453 | CONFLICT (MACC, DIV); | |
2454 | CONFLICT (DMACC, DIV); | |
2455 | ||
2456 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2457 | CONFLICT (DMULT, DMULT); | |
2458 | CONFLICT (DMULT, DMACC); | |
2459 | CONFLICT (DMACC, DMULT); | |
2460 | CONFLICT (DMACC, DMACC); | |
2461 | ||
2462 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2463 | CONFLICT (MACC, MTHILO); | |
2464 | CONFLICT (DMACC, MTHILO); | |
2465 | ||
2466 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2467 | instruction is executed immediately after a MACC or DMACC | |
2468 | instruction, the result of [either instruction] is incorrect." */ | |
2469 | CONFLICT (MACC, MULT); | |
2470 | CONFLICT (MACC, DMULT); | |
2471 | CONFLICT (DMACC, MULT); | |
2472 | CONFLICT (DMACC, DMULT); | |
2473 | ||
2474 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2475 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2476 | DDIV or DDIVU instruction, the result of the MACC or | |
2477 | DMACC instruction is incorrect.". */ | |
2478 | CONFLICT (DMULT, MACC); | |
2479 | CONFLICT (DMULT, DMACC); | |
2480 | CONFLICT (DIV, MACC); | |
2481 | CONFLICT (DIV, DMACC); | |
2482 | ||
2483 | #undef CONFLICT | |
2484 | } | |
2485 | ||
707bfff6 TS |
2486 | struct regname { |
2487 | const char *name; | |
2488 | unsigned int num; | |
2489 | }; | |
2490 | ||
14daeee3 | 2491 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2492 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2493 | #define RTYPE_NUM 0x0000100 |
2494 | #define RTYPE_FPU 0x0000200 | |
2495 | #define RTYPE_FCC 0x0000400 | |
2496 | #define RTYPE_VEC 0x0000800 | |
2497 | #define RTYPE_GP 0x0001000 | |
2498 | #define RTYPE_CP0 0x0002000 | |
2499 | #define RTYPE_PC 0x0004000 | |
2500 | #define RTYPE_ACC 0x0008000 | |
2501 | #define RTYPE_CCC 0x0010000 | |
2502 | #define RTYPE_VI 0x0020000 | |
2503 | #define RTYPE_VF 0x0040000 | |
2504 | #define RTYPE_R5900_I 0x0080000 | |
2505 | #define RTYPE_R5900_Q 0x0100000 | |
2506 | #define RTYPE_R5900_R 0x0200000 | |
2507 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2508 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2509 | #define RWARN 0x8000000 |
707bfff6 TS |
2510 | |
2511 | #define GENERIC_REGISTER_NUMBERS \ | |
2512 | {"$0", RTYPE_NUM | 0}, \ | |
2513 | {"$1", RTYPE_NUM | 1}, \ | |
2514 | {"$2", RTYPE_NUM | 2}, \ | |
2515 | {"$3", RTYPE_NUM | 3}, \ | |
2516 | {"$4", RTYPE_NUM | 4}, \ | |
2517 | {"$5", RTYPE_NUM | 5}, \ | |
2518 | {"$6", RTYPE_NUM | 6}, \ | |
2519 | {"$7", RTYPE_NUM | 7}, \ | |
2520 | {"$8", RTYPE_NUM | 8}, \ | |
2521 | {"$9", RTYPE_NUM | 9}, \ | |
2522 | {"$10", RTYPE_NUM | 10}, \ | |
2523 | {"$11", RTYPE_NUM | 11}, \ | |
2524 | {"$12", RTYPE_NUM | 12}, \ | |
2525 | {"$13", RTYPE_NUM | 13}, \ | |
2526 | {"$14", RTYPE_NUM | 14}, \ | |
2527 | {"$15", RTYPE_NUM | 15}, \ | |
2528 | {"$16", RTYPE_NUM | 16}, \ | |
2529 | {"$17", RTYPE_NUM | 17}, \ | |
2530 | {"$18", RTYPE_NUM | 18}, \ | |
2531 | {"$19", RTYPE_NUM | 19}, \ | |
2532 | {"$20", RTYPE_NUM | 20}, \ | |
2533 | {"$21", RTYPE_NUM | 21}, \ | |
2534 | {"$22", RTYPE_NUM | 22}, \ | |
2535 | {"$23", RTYPE_NUM | 23}, \ | |
2536 | {"$24", RTYPE_NUM | 24}, \ | |
2537 | {"$25", RTYPE_NUM | 25}, \ | |
2538 | {"$26", RTYPE_NUM | 26}, \ | |
2539 | {"$27", RTYPE_NUM | 27}, \ | |
2540 | {"$28", RTYPE_NUM | 28}, \ | |
2541 | {"$29", RTYPE_NUM | 29}, \ | |
2542 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2543 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2544 | |
2545 | #define FPU_REGISTER_NAMES \ | |
2546 | {"$f0", RTYPE_FPU | 0}, \ | |
2547 | {"$f1", RTYPE_FPU | 1}, \ | |
2548 | {"$f2", RTYPE_FPU | 2}, \ | |
2549 | {"$f3", RTYPE_FPU | 3}, \ | |
2550 | {"$f4", RTYPE_FPU | 4}, \ | |
2551 | {"$f5", RTYPE_FPU | 5}, \ | |
2552 | {"$f6", RTYPE_FPU | 6}, \ | |
2553 | {"$f7", RTYPE_FPU | 7}, \ | |
2554 | {"$f8", RTYPE_FPU | 8}, \ | |
2555 | {"$f9", RTYPE_FPU | 9}, \ | |
2556 | {"$f10", RTYPE_FPU | 10}, \ | |
2557 | {"$f11", RTYPE_FPU | 11}, \ | |
2558 | {"$f12", RTYPE_FPU | 12}, \ | |
2559 | {"$f13", RTYPE_FPU | 13}, \ | |
2560 | {"$f14", RTYPE_FPU | 14}, \ | |
2561 | {"$f15", RTYPE_FPU | 15}, \ | |
2562 | {"$f16", RTYPE_FPU | 16}, \ | |
2563 | {"$f17", RTYPE_FPU | 17}, \ | |
2564 | {"$f18", RTYPE_FPU | 18}, \ | |
2565 | {"$f19", RTYPE_FPU | 19}, \ | |
2566 | {"$f20", RTYPE_FPU | 20}, \ | |
2567 | {"$f21", RTYPE_FPU | 21}, \ | |
2568 | {"$f22", RTYPE_FPU | 22}, \ | |
2569 | {"$f23", RTYPE_FPU | 23}, \ | |
2570 | {"$f24", RTYPE_FPU | 24}, \ | |
2571 | {"$f25", RTYPE_FPU | 25}, \ | |
2572 | {"$f26", RTYPE_FPU | 26}, \ | |
2573 | {"$f27", RTYPE_FPU | 27}, \ | |
2574 | {"$f28", RTYPE_FPU | 28}, \ | |
2575 | {"$f29", RTYPE_FPU | 29}, \ | |
2576 | {"$f30", RTYPE_FPU | 30}, \ | |
2577 | {"$f31", RTYPE_FPU | 31} | |
2578 | ||
2579 | #define FPU_CONDITION_CODE_NAMES \ | |
2580 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2581 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2582 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2583 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2584 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2585 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2586 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2587 | {"$fcc7", RTYPE_FCC | 7} | |
2588 | ||
2589 | #define COPROC_CONDITION_CODE_NAMES \ | |
2590 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2591 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2592 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2593 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2594 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2595 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2596 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2597 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2598 | ||
2599 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2600 | {"$a4", RTYPE_GP | 8}, \ | |
2601 | {"$a5", RTYPE_GP | 9}, \ | |
2602 | {"$a6", RTYPE_GP | 10}, \ | |
2603 | {"$a7", RTYPE_GP | 11}, \ | |
2604 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2605 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2606 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2607 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2608 | {"$t0", RTYPE_GP | 12}, \ | |
2609 | {"$t1", RTYPE_GP | 13}, \ | |
2610 | {"$t2", RTYPE_GP | 14}, \ | |
2611 | {"$t3", RTYPE_GP | 15} | |
2612 | ||
2613 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2614 | {"$t0", RTYPE_GP | 8}, \ | |
2615 | {"$t1", RTYPE_GP | 9}, \ | |
2616 | {"$t2", RTYPE_GP | 10}, \ | |
2617 | {"$t3", RTYPE_GP | 11}, \ | |
2618 | {"$t4", RTYPE_GP | 12}, \ | |
2619 | {"$t5", RTYPE_GP | 13}, \ | |
2620 | {"$t6", RTYPE_GP | 14}, \ | |
2621 | {"$t7", RTYPE_GP | 15}, \ | |
2622 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2623 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2624 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2625 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2626 | |
2627 | /* Remaining symbolic register names */ | |
2628 | #define SYMBOLIC_REGISTER_NAMES \ | |
2629 | {"$zero", RTYPE_GP | 0}, \ | |
2630 | {"$at", RTYPE_GP | 1}, \ | |
2631 | {"$AT", RTYPE_GP | 1}, \ | |
2632 | {"$v0", RTYPE_GP | 2}, \ | |
2633 | {"$v1", RTYPE_GP | 3}, \ | |
2634 | {"$a0", RTYPE_GP | 4}, \ | |
2635 | {"$a1", RTYPE_GP | 5}, \ | |
2636 | {"$a2", RTYPE_GP | 6}, \ | |
2637 | {"$a3", RTYPE_GP | 7}, \ | |
2638 | {"$s0", RTYPE_GP | 16}, \ | |
2639 | {"$s1", RTYPE_GP | 17}, \ | |
2640 | {"$s2", RTYPE_GP | 18}, \ | |
2641 | {"$s3", RTYPE_GP | 19}, \ | |
2642 | {"$s4", RTYPE_GP | 20}, \ | |
2643 | {"$s5", RTYPE_GP | 21}, \ | |
2644 | {"$s6", RTYPE_GP | 22}, \ | |
2645 | {"$s7", RTYPE_GP | 23}, \ | |
2646 | {"$t8", RTYPE_GP | 24}, \ | |
2647 | {"$t9", RTYPE_GP | 25}, \ | |
2648 | {"$k0", RTYPE_GP | 26}, \ | |
2649 | {"$kt0", RTYPE_GP | 26}, \ | |
2650 | {"$k1", RTYPE_GP | 27}, \ | |
2651 | {"$kt1", RTYPE_GP | 27}, \ | |
2652 | {"$gp", RTYPE_GP | 28}, \ | |
2653 | {"$sp", RTYPE_GP | 29}, \ | |
2654 | {"$s8", RTYPE_GP | 30}, \ | |
2655 | {"$fp", RTYPE_GP | 30}, \ | |
2656 | {"$ra", RTYPE_GP | 31} | |
2657 | ||
2658 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2659 | {"$pc", RTYPE_PC | 0} | |
2660 | ||
2661 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2662 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2663 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2664 | {"$v2", RTYPE_VEC | 2}, \ | |
2665 | {"$v3", RTYPE_VEC | 3}, \ | |
2666 | {"$v4", RTYPE_VEC | 4}, \ | |
2667 | {"$v5", RTYPE_VEC | 5}, \ | |
2668 | {"$v6", RTYPE_VEC | 6}, \ | |
2669 | {"$v7", RTYPE_VEC | 7}, \ | |
2670 | {"$v8", RTYPE_VEC | 8}, \ | |
2671 | {"$v9", RTYPE_VEC | 9}, \ | |
2672 | {"$v10", RTYPE_VEC | 10}, \ | |
2673 | {"$v11", RTYPE_VEC | 11}, \ | |
2674 | {"$v12", RTYPE_VEC | 12}, \ | |
2675 | {"$v13", RTYPE_VEC | 13}, \ | |
2676 | {"$v14", RTYPE_VEC | 14}, \ | |
2677 | {"$v15", RTYPE_VEC | 15}, \ | |
2678 | {"$v16", RTYPE_VEC | 16}, \ | |
2679 | {"$v17", RTYPE_VEC | 17}, \ | |
2680 | {"$v18", RTYPE_VEC | 18}, \ | |
2681 | {"$v19", RTYPE_VEC | 19}, \ | |
2682 | {"$v20", RTYPE_VEC | 20}, \ | |
2683 | {"$v21", RTYPE_VEC | 21}, \ | |
2684 | {"$v22", RTYPE_VEC | 22}, \ | |
2685 | {"$v23", RTYPE_VEC | 23}, \ | |
2686 | {"$v24", RTYPE_VEC | 24}, \ | |
2687 | {"$v25", RTYPE_VEC | 25}, \ | |
2688 | {"$v26", RTYPE_VEC | 26}, \ | |
2689 | {"$v27", RTYPE_VEC | 27}, \ | |
2690 | {"$v28", RTYPE_VEC | 28}, \ | |
2691 | {"$v29", RTYPE_VEC | 29}, \ | |
2692 | {"$v30", RTYPE_VEC | 30}, \ | |
2693 | {"$v31", RTYPE_VEC | 31} | |
2694 | ||
14daeee3 RS |
2695 | #define R5900_I_NAMES \ |
2696 | {"$I", RTYPE_R5900_I | 0} | |
2697 | ||
2698 | #define R5900_Q_NAMES \ | |
2699 | {"$Q", RTYPE_R5900_Q | 0} | |
2700 | ||
2701 | #define R5900_R_NAMES \ | |
2702 | {"$R", RTYPE_R5900_R | 0} | |
2703 | ||
2704 | #define R5900_ACC_NAMES \ | |
2705 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2706 | ||
707bfff6 TS |
2707 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2708 | {"$ac0", RTYPE_ACC | 0}, \ | |
2709 | {"$ac1", RTYPE_ACC | 1}, \ | |
2710 | {"$ac2", RTYPE_ACC | 2}, \ | |
2711 | {"$ac3", RTYPE_ACC | 3} | |
2712 | ||
2713 | static const struct regname reg_names[] = { | |
2714 | GENERIC_REGISTER_NUMBERS, | |
2715 | FPU_REGISTER_NAMES, | |
2716 | FPU_CONDITION_CODE_NAMES, | |
2717 | COPROC_CONDITION_CODE_NAMES, | |
2718 | ||
2719 | /* The $txx registers depends on the abi, | |
2720 | these will be added later into the symbol table from | |
3739860c | 2721 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2722 | parsing of arguments from the command line. */ |
2723 | SYMBOLIC_REGISTER_NAMES, | |
2724 | ||
2725 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2726 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2727 | R5900_I_NAMES, |
2728 | R5900_Q_NAMES, | |
2729 | R5900_R_NAMES, | |
2730 | R5900_ACC_NAMES, | |
707bfff6 TS |
2731 | MIPS_DSP_ACCUMULATOR_NAMES, |
2732 | {0, 0} | |
2733 | }; | |
2734 | ||
2735 | static const struct regname reg_names_o32[] = { | |
2736 | O32_SYMBOLIC_REGISTER_NAMES, | |
2737 | {0, 0} | |
2738 | }; | |
2739 | ||
2740 | static const struct regname reg_names_n32n64[] = { | |
2741 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2742 | {0, 0} | |
2743 | }; | |
2744 | ||
a92713e6 RS |
2745 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2746 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2747 | of these register symbols, return the associated vector register, | |
2748 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2749 | |
a92713e6 RS |
2750 | static unsigned int |
2751 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2752 | { |
a92713e6 RS |
2753 | if ((symval & -2) == (RTYPE_GP | 2)) |
2754 | return RTYPE_VEC | (symval & 1); | |
2755 | return symval; | |
2756 | } | |
2757 | ||
14daeee3 RS |
2758 | /* Return true if string [S, E) is a valid register name, storing its |
2759 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2760 | |
2761 | static bfd_boolean | |
14daeee3 | 2762 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2763 | { |
707bfff6 | 2764 | char save_c; |
14daeee3 | 2765 | symbolS *symbol; |
707bfff6 TS |
2766 | |
2767 | /* Terminate name. */ | |
2768 | save_c = *e; | |
2769 | *e = '\0'; | |
2770 | ||
a92713e6 RS |
2771 | /* Look up the name. */ |
2772 | symbol = symbol_find (s); | |
2773 | *e = save_c; | |
2774 | ||
2775 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2776 | return FALSE; | |
2777 | ||
14daeee3 RS |
2778 | *symval_ptr = S_GET_VALUE (symbol); |
2779 | return TRUE; | |
2780 | } | |
2781 | ||
2782 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2783 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2784 | is nonnull. | |
2785 | ||
2786 | When returning true, move *SPTR past the register, store the | |
2787 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2788 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2789 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2790 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2791 | ||
2792 | static bfd_boolean | |
2793 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2794 | unsigned int *channels_ptr) | |
2795 | { | |
2796 | char *s, *e, *m; | |
2797 | const char *q; | |
2798 | unsigned int channels, symval, bit; | |
2799 | ||
2800 | /* Find end of name. */ | |
2801 | s = e = *sptr; | |
2802 | if (is_name_beginner (*e)) | |
2803 | ++e; | |
2804 | while (is_part_of_name (*e)) | |
2805 | ++e; | |
2806 | ||
2807 | channels = 0; | |
2808 | if (!mips_parse_register_1 (s, e, &symval)) | |
2809 | { | |
2810 | if (!channels_ptr) | |
2811 | return FALSE; | |
2812 | ||
2813 | /* Eat characters from the end of the string that are valid | |
2814 | channel suffixes. The preceding register must be $ACC or | |
2815 | end with a digit, so there is no ambiguity. */ | |
2816 | bit = 1; | |
2817 | m = e; | |
2818 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2819 | if (m > s && m[-1] == *q) | |
2820 | { | |
2821 | --m; | |
2822 | channels |= bit; | |
2823 | } | |
2824 | ||
2825 | if (channels == 0 | |
2826 | || !mips_parse_register_1 (s, m, &symval) | |
2827 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2828 | return FALSE; | |
2829 | } | |
2830 | ||
a92713e6 | 2831 | *sptr = e; |
14daeee3 RS |
2832 | *symval_ptr = symval; |
2833 | if (channels_ptr) | |
2834 | *channels_ptr = channels; | |
a92713e6 RS |
2835 | return TRUE; |
2836 | } | |
2837 | ||
2838 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2839 | If so, then return 1, advance S to consume the specifier and store | |
2840 | the register's number in REGNOP, otherwise return 0. */ | |
2841 | ||
2842 | static int | |
2843 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2844 | { | |
2845 | unsigned int regno; | |
2846 | ||
14daeee3 | 2847 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2848 | { |
a92713e6 RS |
2849 | if (types & RTYPE_VEC) |
2850 | regno = mips_prefer_vec_regno (regno); | |
2851 | if (regno & types) | |
2852 | regno &= RNUM_MASK; | |
2853 | else | |
2854 | regno = ~0; | |
707bfff6 | 2855 | } |
a92713e6 | 2856 | else |
707bfff6 | 2857 | { |
a92713e6 | 2858 | if (types & RWARN) |
1661c76c | 2859 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2860 | regno = ~0; |
707bfff6 | 2861 | } |
707bfff6 | 2862 | if (regnop) |
a92713e6 RS |
2863 | *regnop = regno; |
2864 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2865 | } |
2866 | ||
14daeee3 RS |
2867 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2868 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2869 | ||
2870 | static char * | |
2871 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2872 | { | |
2873 | unsigned int i; | |
2874 | ||
2875 | *channels = 0; | |
2876 | for (i = 0; i < 4; i++) | |
2877 | if (*s == "xyzw"[i]) | |
2878 | { | |
2879 | *channels |= 1 << (3 - i); | |
2880 | ++s; | |
2881 | } | |
2882 | return s; | |
2883 | } | |
2884 | ||
a92713e6 RS |
2885 | /* Token types for parsed operand lists. */ |
2886 | enum mips_operand_token_type { | |
2887 | /* A plain register, e.g. $f2. */ | |
2888 | OT_REG, | |
df58fc94 | 2889 | |
14daeee3 RS |
2890 | /* A 4-bit XYZW channel mask. */ |
2891 | OT_CHANNELS, | |
2892 | ||
56d438b1 CF |
2893 | /* A constant vector index, e.g. [1]. */ |
2894 | OT_INTEGER_INDEX, | |
2895 | ||
2896 | /* A register vector index, e.g. [$2]. */ | |
2897 | OT_REG_INDEX, | |
df58fc94 | 2898 | |
a92713e6 RS |
2899 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2900 | OT_REG_RANGE, | |
2901 | ||
2902 | /* A (possibly relocated) expression. */ | |
2903 | OT_INTEGER, | |
2904 | ||
2905 | /* A floating-point value. */ | |
2906 | OT_FLOAT, | |
2907 | ||
2908 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
2909 | before OT_REGs. */ | |
2910 | OT_CHAR, | |
2911 | ||
14daeee3 RS |
2912 | /* A doubled character, either "--" or "++". */ |
2913 | OT_DOUBLE_CHAR, | |
2914 | ||
a92713e6 RS |
2915 | /* The end of the operand list. */ |
2916 | OT_END | |
2917 | }; | |
2918 | ||
2919 | /* A parsed operand token. */ | |
2920 | struct mips_operand_token | |
2921 | { | |
2922 | /* The type of token. */ | |
2923 | enum mips_operand_token_type type; | |
2924 | union | |
2925 | { | |
56d438b1 | 2926 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
2927 | unsigned int regno; |
2928 | ||
14daeee3 RS |
2929 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
2930 | unsigned int channels; | |
2931 | ||
56d438b1 CF |
2932 | /* The integer value of an OT_INTEGER_INDEX. */ |
2933 | addressT index; | |
a92713e6 RS |
2934 | |
2935 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
2936 | struct { | |
2937 | unsigned int regno1; | |
2938 | unsigned int regno2; | |
2939 | } reg_range; | |
2940 | ||
2941 | /* The value of an OT_INTEGER. The value is represented as an | |
2942 | expression and the relocation operators that were applied to | |
2943 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
2944 | relocation operators were used. */ | |
2945 | struct { | |
2946 | expressionS value; | |
2947 | bfd_reloc_code_real_type relocs[3]; | |
2948 | } integer; | |
2949 | ||
2950 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
2951 | in the constant. */ | |
2952 | struct { | |
2953 | unsigned char data[8]; | |
2954 | int length; | |
2955 | } flt; | |
2956 | ||
14daeee3 | 2957 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
2958 | char ch; |
2959 | } u; | |
2960 | }; | |
2961 | ||
2962 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
2963 | static struct obstack mips_operand_tokens; | |
2964 | ||
2965 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
2966 | ||
2967 | static void | |
2968 | mips_add_token (struct mips_operand_token *token, | |
2969 | enum mips_operand_token_type type) | |
2970 | { | |
2971 | token->type = type; | |
2972 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
2973 | } | |
2974 | ||
2975 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
2976 | and OT_REG tokens for them if so, and return a pointer to the first | |
2977 | unconsumed character. Return null otherwise. */ | |
2978 | ||
2979 | static char * | |
2980 | mips_parse_base_start (char *s) | |
2981 | { | |
2982 | struct mips_operand_token token; | |
14daeee3 RS |
2983 | unsigned int regno, channels; |
2984 | bfd_boolean decrement_p; | |
df58fc94 | 2985 | |
a92713e6 RS |
2986 | if (*s != '(') |
2987 | return 0; | |
2988 | ||
2989 | ++s; | |
2990 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
2991 | |
2992 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
2993 | is a double negative. */ | |
2994 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
2995 | if (decrement_p) | |
2996 | { | |
2997 | s += 2; | |
2998 | SKIP_SPACE_TABS (s); | |
2999 | } | |
3000 | ||
3001 | /* Allow a channel specifier because that leads to better error messages | |
3002 | than treating something like "$vf0x++" as an expression. */ | |
3003 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3004 | return 0; |
3005 | ||
3006 | token.u.ch = '('; | |
3007 | mips_add_token (&token, OT_CHAR); | |
3008 | ||
14daeee3 RS |
3009 | if (decrement_p) |
3010 | { | |
3011 | token.u.ch = '-'; | |
3012 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3013 | } | |
3014 | ||
a92713e6 RS |
3015 | token.u.regno = regno; |
3016 | mips_add_token (&token, OT_REG); | |
3017 | ||
14daeee3 RS |
3018 | if (channels) |
3019 | { | |
3020 | token.u.channels = channels; | |
3021 | mips_add_token (&token, OT_CHANNELS); | |
3022 | } | |
3023 | ||
3024 | /* For consistency, only match "++" as part of base expressions too. */ | |
3025 | SKIP_SPACE_TABS (s); | |
3026 | if (s[0] == '+' && s[1] == '+') | |
3027 | { | |
3028 | s += 2; | |
3029 | token.u.ch = '+'; | |
3030 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3031 | } | |
3032 | ||
a92713e6 RS |
3033 | return s; |
3034 | } | |
3035 | ||
3036 | /* Parse one or more tokens from S. Return a pointer to the first | |
3037 | unconsumed character on success. Return null if an error was found | |
3038 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3039 | mips_parse_arguments. */ | |
3040 | ||
3041 | static char * | |
3042 | mips_parse_argument_token (char *s, char float_format) | |
3043 | { | |
3044 | char *end, *save_in, *err; | |
14daeee3 | 3045 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3046 | struct mips_operand_token token; |
3047 | ||
3048 | /* First look for "($reg", since we want to treat that as an | |
3049 | OT_CHAR and OT_REG rather than an expression. */ | |
3050 | end = mips_parse_base_start (s); | |
3051 | if (end) | |
3052 | return end; | |
3053 | ||
3054 | /* Handle other characters that end up as OT_CHARs. */ | |
3055 | if (*s == ')' || *s == ',') | |
3056 | { | |
3057 | token.u.ch = *s; | |
3058 | mips_add_token (&token, OT_CHAR); | |
3059 | ++s; | |
3060 | return s; | |
3061 | } | |
3062 | ||
3063 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3064 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3065 | { |
14daeee3 RS |
3066 | if (channels) |
3067 | { | |
3068 | /* A register and a VU0 channel suffix. */ | |
3069 | token.u.regno = regno1; | |
3070 | mips_add_token (&token, OT_REG); | |
3071 | ||
3072 | token.u.channels = channels; | |
3073 | mips_add_token (&token, OT_CHANNELS); | |
3074 | return s; | |
3075 | } | |
3076 | ||
a92713e6 RS |
3077 | SKIP_SPACE_TABS (s); |
3078 | if (*s == '-') | |
df58fc94 | 3079 | { |
a92713e6 RS |
3080 | /* A register range. */ |
3081 | ++s; | |
3082 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3083 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3084 | { |
1661c76c | 3085 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3086 | return 0; |
3087 | } | |
df58fc94 | 3088 | |
a92713e6 RS |
3089 | token.u.reg_range.regno1 = regno1; |
3090 | token.u.reg_range.regno2 = regno2; | |
3091 | mips_add_token (&token, OT_REG_RANGE); | |
3092 | return s; | |
3093 | } | |
a92713e6 | 3094 | |
56d438b1 CF |
3095 | /* Add the register itself. */ |
3096 | token.u.regno = regno1; | |
3097 | mips_add_token (&token, OT_REG); | |
3098 | ||
3099 | /* Check for a vector index. */ | |
3100 | if (*s == '[') | |
3101 | { | |
a92713e6 RS |
3102 | ++s; |
3103 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3104 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3105 | mips_add_token (&token, OT_REG_INDEX); | |
3106 | else | |
a92713e6 | 3107 | { |
56d438b1 CF |
3108 | expressionS element; |
3109 | ||
3110 | my_getExpression (&element, s); | |
3111 | if (element.X_op != O_constant) | |
3112 | { | |
3113 | set_insn_error (0, _("vector element must be constant")); | |
3114 | return 0; | |
3115 | } | |
3116 | s = expr_end; | |
3117 | token.u.index = element.X_add_number; | |
3118 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3119 | } |
a92713e6 RS |
3120 | SKIP_SPACE_TABS (s); |
3121 | if (*s != ']') | |
3122 | { | |
1661c76c | 3123 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3124 | return 0; |
3125 | } | |
3126 | ++s; | |
df58fc94 | 3127 | } |
a92713e6 | 3128 | return s; |
df58fc94 RS |
3129 | } |
3130 | ||
a92713e6 RS |
3131 | if (float_format) |
3132 | { | |
3133 | /* First try to treat expressions as floats. */ | |
3134 | save_in = input_line_pointer; | |
3135 | input_line_pointer = s; | |
3136 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3137 | &token.u.flt.length); | |
3138 | end = input_line_pointer; | |
3139 | input_line_pointer = save_in; | |
3140 | if (err && *err) | |
3141 | { | |
e3de51ce | 3142 | set_insn_error (0, err); |
a92713e6 RS |
3143 | return 0; |
3144 | } | |
3145 | if (s != end) | |
3146 | { | |
3147 | mips_add_token (&token, OT_FLOAT); | |
3148 | return end; | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | /* Treat everything else as an integer expression. */ | |
3153 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3154 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3155 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3156 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3157 | s = expr_end; | |
3158 | mips_add_token (&token, OT_INTEGER); | |
3159 | return s; | |
3160 | } | |
3161 | ||
3162 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3163 | if expressions should be treated as 32-bit floating-point constants, | |
3164 | 'd' if they should be treated as 64-bit floating-point constants, | |
3165 | or 0 if they should be treated as integer expressions (the usual case). | |
3166 | ||
3167 | Return a list of tokens on success, otherwise return 0. The caller | |
3168 | must obstack_free the list after use. */ | |
3169 | ||
3170 | static struct mips_operand_token * | |
3171 | mips_parse_arguments (char *s, char float_format) | |
3172 | { | |
3173 | struct mips_operand_token token; | |
3174 | ||
3175 | SKIP_SPACE_TABS (s); | |
3176 | while (*s) | |
3177 | { | |
3178 | s = mips_parse_argument_token (s, float_format); | |
3179 | if (!s) | |
3180 | { | |
3181 | obstack_free (&mips_operand_tokens, | |
3182 | obstack_finish (&mips_operand_tokens)); | |
3183 | return 0; | |
3184 | } | |
3185 | SKIP_SPACE_TABS (s); | |
3186 | } | |
3187 | mips_add_token (&token, OT_END); | |
3188 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3189 | } |
3190 | ||
d301a56b RS |
3191 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3192 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3193 | |
3194 | static bfd_boolean | |
f79e2745 | 3195 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3196 | { |
3197 | int isa = mips_opts.isa; | |
846ef2d0 | 3198 | int ase = mips_opts.ase; |
037b32b9 | 3199 | int fp_s, fp_d; |
c6278170 | 3200 | unsigned int i; |
037b32b9 | 3201 | |
c6278170 RS |
3202 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
3203 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3204 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3205 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3206 | |
d301a56b | 3207 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3208 | return FALSE; |
3209 | ||
3210 | /* Check whether the instruction or macro requires single-precision or | |
3211 | double-precision floating-point support. Note that this information is | |
3212 | stored differently in the opcode table for insns and macros. */ | |
3213 | if (mo->pinfo == INSN_MACRO) | |
3214 | { | |
3215 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3216 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3217 | } | |
3218 | else | |
3219 | { | |
3220 | fp_s = mo->pinfo & FP_S; | |
3221 | fp_d = mo->pinfo & FP_D; | |
3222 | } | |
3223 | ||
3224 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3225 | return FALSE; | |
3226 | ||
3227 | if (fp_s && mips_opts.soft_float) | |
3228 | return FALSE; | |
3229 | ||
3230 | return TRUE; | |
3231 | } | |
3232 | ||
3233 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3234 | selected ISA and architecture. */ | |
3235 | ||
3236 | static bfd_boolean | |
3237 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3238 | { | |
d301a56b | 3239 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
3240 | } |
3241 | ||
df58fc94 RS |
3242 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
3243 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
3244 | ||
3245 | static bfd_boolean | |
3246 | is_size_valid (const struct mips_opcode *mo) | |
3247 | { | |
3248 | if (!mips_opts.micromips) | |
3249 | return TRUE; | |
3250 | ||
833794fc MR |
3251 | if (mips_opts.insn32) |
3252 | { | |
3253 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3254 | return FALSE; | |
3255 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3256 | return FALSE; | |
3257 | } | |
df58fc94 RS |
3258 | if (!forced_insn_length) |
3259 | return TRUE; | |
3260 | if (mo->pinfo == INSN_MACRO) | |
3261 | return FALSE; | |
3262 | return forced_insn_length == micromips_insn_length (mo); | |
3263 | } | |
3264 | ||
3265 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
3266 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3267 | ||
3268 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3269 | a macro expansion fails because it relies on a preceding 32-bit real | |
3270 | instruction to have matched and does not handle the operands correctly. | |
3271 | The only macros that may expand to 16-bit instructions are JAL that | |
3272 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3273 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3274 | a NOP. In all these cases the macros precede any corresponding real | |
3275 | instruction definitions in the opcode table, so they will match in the | |
3276 | second pass where the size of the delay slot is ignored and therefore | |
3277 | produce correct code. */ | |
df58fc94 RS |
3278 | |
3279 | static bfd_boolean | |
3280 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3281 | { | |
3282 | if (!mips_opts.micromips) | |
3283 | return TRUE; | |
3284 | ||
3285 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3286 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3287 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3288 | && micromips_insn_length (mo) != 4) | |
3289 | return FALSE; | |
3290 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3291 | && micromips_insn_length (mo) != 2) | |
3292 | return FALSE; | |
3293 | ||
3294 | return TRUE; | |
3295 | } | |
3296 | ||
fc76e730 RS |
3297 | /* For consistency checking, verify that all bits of OPCODE are specified |
3298 | either by the match/mask part of the instruction definition, or by the | |
3299 | operand list. Also build up a list of operands in OPERANDS. | |
3300 | ||
3301 | INSN_BITS says which bits of the instruction are significant. | |
3302 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3303 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3304 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3305 | |
3306 | static int | |
3307 | validate_mips_insn (const struct mips_opcode *opcode, | |
3308 | unsigned long insn_bits, | |
fc76e730 RS |
3309 | const struct mips_operand *(*decode_operand) (const char *), |
3310 | struct mips_operand_array *operands) | |
ab902481 RS |
3311 | { |
3312 | const char *s; | |
fc76e730 | 3313 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3314 | const struct mips_operand *operand; |
3315 | ||
fc76e730 RS |
3316 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3317 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3318 | { |
3319 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3320 | opcode->name, opcode->args); | |
3321 | return 0; | |
3322 | } | |
3323 | used_bits = 0; | |
fc76e730 | 3324 | opno = 0; |
14daeee3 RS |
3325 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3326 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3327 | for (s = opcode->args; *s; ++s) |
3328 | switch (*s) | |
3329 | { | |
3330 | case ',': | |
3331 | case '(': | |
3332 | case ')': | |
3333 | break; | |
3334 | ||
14daeee3 RS |
3335 | case '#': |
3336 | s++; | |
3337 | break; | |
3338 | ||
ab902481 | 3339 | default: |
fc76e730 RS |
3340 | if (!decode_operand) |
3341 | operand = decode_mips16_operand (*s, FALSE); | |
3342 | else | |
3343 | operand = decode_operand (s); | |
3344 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3345 | { |
3346 | as_bad (_("internal: unknown operand type: %s %s"), | |
3347 | opcode->name, opcode->args); | |
3348 | return 0; | |
3349 | } | |
fc76e730 RS |
3350 | gas_assert (opno < MAX_OPERANDS); |
3351 | operands->operand[opno] = operand; | |
14daeee3 | 3352 | if (operand && operand->type != OP_VU0_MATCH_SUFFIX) |
fc76e730 | 3353 | { |
14daeee3 | 3354 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3355 | if (operand->type == OP_MDMX_IMM_REG) |
3356 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3357 | has separate entries for each format. */ | |
3358 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3359 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3360 | used_bits &= ~(mask & 0x700); | |
3361 | } | |
ab902481 | 3362 | /* Skip prefix characters. */ |
7361da2c | 3363 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3364 | ++s; |
fc76e730 | 3365 | opno += 1; |
ab902481 RS |
3366 | break; |
3367 | } | |
fc76e730 | 3368 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3369 | if (doubled) |
3370 | { | |
3371 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3372 | " %s %s"), doubled, opcode->name, opcode->args); | |
3373 | return 0; | |
3374 | } | |
fc76e730 | 3375 | used_bits |= mask; |
ab902481 | 3376 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3377 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3378 | { |
3379 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3380 | undefined, opcode->name, opcode->args); | |
3381 | return 0; | |
3382 | } | |
3383 | used_bits &= ~insn_bits; | |
3384 | if (used_bits) | |
3385 | { | |
3386 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3387 | used_bits, opcode->name, opcode->args); | |
3388 | return 0; | |
3389 | } | |
3390 | return 1; | |
3391 | } | |
3392 | ||
fc76e730 RS |
3393 | /* The MIPS16 version of validate_mips_insn. */ |
3394 | ||
3395 | static int | |
3396 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3397 | struct mips_operand_array *operands) | |
3398 | { | |
3399 | if (opcode->args[0] == 'a' || opcode->args[0] == 'i') | |
3400 | { | |
3401 | /* In this case OPCODE defines the first 16 bits in a 32-bit jump | |
3402 | instruction. Use TMP to describe the full instruction. */ | |
3403 | struct mips_opcode tmp; | |
3404 | ||
3405 | tmp = *opcode; | |
3406 | tmp.match <<= 16; | |
3407 | tmp.mask <<= 16; | |
3408 | return validate_mips_insn (&tmp, 0xffffffff, 0, operands); | |
3409 | } | |
3410 | return validate_mips_insn (opcode, 0xffff, 0, operands); | |
3411 | } | |
3412 | ||
ab902481 RS |
3413 | /* The microMIPS version of validate_mips_insn. */ |
3414 | ||
3415 | static int | |
fc76e730 RS |
3416 | validate_micromips_insn (const struct mips_opcode *opc, |
3417 | struct mips_operand_array *operands) | |
ab902481 RS |
3418 | { |
3419 | unsigned long insn_bits; | |
3420 | unsigned long major; | |
3421 | unsigned int length; | |
3422 | ||
fc76e730 RS |
3423 | if (opc->pinfo == INSN_MACRO) |
3424 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3425 | operands); | |
3426 | ||
ab902481 RS |
3427 | length = micromips_insn_length (opc); |
3428 | if (length != 2 && length != 4) | |
3429 | { | |
1661c76c | 3430 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3431 | "%s %s"), length, opc->name, opc->args); |
3432 | return 0; | |
3433 | } | |
3434 | major = opc->match >> (10 + 8 * (length - 2)); | |
3435 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3436 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3437 | { | |
1661c76c | 3438 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3439 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3440 | return 0; | |
3441 | } | |
3442 | ||
3443 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3444 | insn_bits = 1 << 4 * length; | |
3445 | insn_bits <<= 4 * length; | |
3446 | insn_bits -= 1; | |
fc76e730 RS |
3447 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3448 | operands); | |
ab902481 RS |
3449 | } |
3450 | ||
707bfff6 TS |
3451 | /* This function is called once, at assembler startup time. It should set up |
3452 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3453 | |
252b5132 | 3454 | void |
17a2f251 | 3455 | md_begin (void) |
252b5132 | 3456 | { |
3994f87e | 3457 | const char *retval = NULL; |
156c2f8b | 3458 | int i = 0; |
252b5132 | 3459 | int broken = 0; |
1f25f5d3 | 3460 | |
0a44bf69 RS |
3461 | if (mips_pic != NO_PIC) |
3462 | { | |
3463 | if (g_switch_seen && g_switch_value != 0) | |
3464 | as_bad (_("-G may not be used in position-independent code")); | |
3465 | g_switch_value = 0; | |
3466 | } | |
3467 | ||
0b35dfee | 3468 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3469 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3470 | |
252b5132 RH |
3471 | op_hash = hash_new (); |
3472 | ||
fc76e730 | 3473 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3474 | for (i = 0; i < NUMOPCODES;) |
3475 | { | |
3476 | const char *name = mips_opcodes[i].name; | |
3477 | ||
17a2f251 | 3478 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3479 | if (retval != NULL) |
3480 | { | |
3481 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3482 | mips_opcodes[i].name, retval); | |
3483 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3484 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3485 | } |
3486 | do | |
3487 | { | |
fc76e730 RS |
3488 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3489 | decode_mips_operand, &mips_operands[i])) | |
3490 | broken = 1; | |
3491 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3492 | { |
fc76e730 RS |
3493 | create_insn (&nop_insn, mips_opcodes + i); |
3494 | if (mips_fix_loongson2f_nop) | |
3495 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3496 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3497 | } |
3498 | ++i; | |
3499 | } | |
3500 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3501 | } | |
3502 | ||
3503 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3504 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3505 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3506 | |
3507 | i = 0; | |
3508 | while (i < bfd_mips16_num_opcodes) | |
3509 | { | |
3510 | const char *name = mips16_opcodes[i].name; | |
3511 | ||
17a2f251 | 3512 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3513 | if (retval != NULL) |
3514 | as_fatal (_("internal: can't hash `%s': %s"), | |
3515 | mips16_opcodes[i].name, retval); | |
3516 | do | |
3517 | { | |
fc76e730 RS |
3518 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3519 | broken = 1; | |
1e915849 RS |
3520 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3521 | { | |
3522 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3523 | mips16_nop_insn.fixed_p = 1; | |
3524 | } | |
252b5132 RH |
3525 | ++i; |
3526 | } | |
3527 | while (i < bfd_mips16_num_opcodes | |
3528 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3529 | } | |
3530 | ||
df58fc94 | 3531 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3532 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3533 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3534 | |
3535 | i = 0; | |
3536 | while (i < bfd_micromips_num_opcodes) | |
3537 | { | |
3538 | const char *name = micromips_opcodes[i].name; | |
3539 | ||
3540 | retval = hash_insert (micromips_op_hash, name, | |
3541 | (void *) µmips_opcodes[i]); | |
3542 | if (retval != NULL) | |
3543 | as_fatal (_("internal: can't hash `%s': %s"), | |
3544 | micromips_opcodes[i].name, retval); | |
3545 | do | |
fc76e730 RS |
3546 | { |
3547 | struct mips_cl_insn *micromips_nop_insn; | |
3548 | ||
3549 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3550 | µmips_operands[i])) | |
3551 | broken = 1; | |
3552 | ||
3553 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3554 | { | |
3555 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3556 | micromips_nop_insn = µmips_nop16_insn; | |
3557 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3558 | micromips_nop_insn = µmips_nop32_insn; | |
3559 | else | |
3560 | continue; | |
3561 | ||
3562 | if (micromips_nop_insn->insn_mo == NULL | |
3563 | && strcmp (name, "nop") == 0) | |
3564 | { | |
3565 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3566 | micromips_nop_insn->fixed_p = 1; | |
3567 | } | |
3568 | } | |
3569 | } | |
df58fc94 RS |
3570 | while (++i < bfd_micromips_num_opcodes |
3571 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3572 | } | |
3573 | ||
252b5132 | 3574 | if (broken) |
1661c76c | 3575 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3576 | |
3577 | /* We add all the general register names to the symbol table. This | |
3578 | helps us detect invalid uses of them. */ | |
3739860c | 3579 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3580 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3581 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3582 | &zero_address_frag)); |
3583 | if (HAVE_NEWABI) | |
3739860c | 3584 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3585 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3586 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3587 | &zero_address_frag)); |
707bfff6 | 3588 | else |
3739860c | 3589 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3590 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3591 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3592 | &zero_address_frag)); |
6047c971 | 3593 | |
14daeee3 RS |
3594 | for (i = 0; i < 32; i++) |
3595 | { | |
3596 | char regname[7]; | |
3597 | ||
3598 | /* R5900 VU0 floating-point register. */ | |
3599 | regname[sizeof (rename) - 1] = 0; | |
3600 | snprintf (regname, sizeof (regname) - 1, "$vf%d", i); | |
3601 | symbol_table_insert (symbol_new (regname, reg_section, | |
3602 | RTYPE_VF | i, &zero_address_frag)); | |
3603 | ||
3604 | /* R5900 VU0 integer register. */ | |
3605 | snprintf (regname, sizeof (regname) - 1, "$vi%d", i); | |
3606 | symbol_table_insert (symbol_new (regname, reg_section, | |
3607 | RTYPE_VI | i, &zero_address_frag)); | |
3608 | ||
56d438b1 CF |
3609 | /* MSA register. */ |
3610 | snprintf (regname, sizeof (regname) - 1, "$w%d", i); | |
3611 | symbol_table_insert (symbol_new (regname, reg_section, | |
3612 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3613 | } |
3614 | ||
a92713e6 RS |
3615 | obstack_init (&mips_operand_tokens); |
3616 | ||
7d10b47d | 3617 | mips_no_prev_insn (); |
252b5132 RH |
3618 | |
3619 | mips_gprmask = 0; | |
3620 | mips_cprmask[0] = 0; | |
3621 | mips_cprmask[1] = 0; | |
3622 | mips_cprmask[2] = 0; | |
3623 | mips_cprmask[3] = 0; | |
3624 | ||
3625 | /* set the default alignment for the text section (2**2) */ | |
3626 | record_alignment (text_section, 2); | |
3627 | ||
4d0d148d | 3628 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3629 | |
f3ded42a RS |
3630 | /* On a native system other than VxWorks, sections must be aligned |
3631 | to 16 byte boundaries. When configured for an embedded ELF | |
3632 | target, we don't bother. */ | |
3633 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3634 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3635 | { |
f3ded42a RS |
3636 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3637 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3638 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3639 | } | |
252b5132 | 3640 | |
f3ded42a RS |
3641 | /* Create a .reginfo section for register masks and a .mdebug |
3642 | section for debugging information. */ | |
3643 | { | |
3644 | segT seg; | |
3645 | subsegT subseg; | |
3646 | flagword flags; | |
3647 | segT sec; | |
3648 | ||
3649 | seg = now_seg; | |
3650 | subseg = now_subseg; | |
3651 | ||
3652 | /* The ABI says this section should be loaded so that the | |
3653 | running program can access it. However, we don't load it | |
3654 | if we are configured for an embedded target */ | |
3655 | flags = SEC_READONLY | SEC_DATA; | |
3656 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3657 | flags |= SEC_ALLOC | SEC_LOAD; | |
3658 | ||
3659 | if (mips_abi != N64_ABI) | |
252b5132 | 3660 | { |
f3ded42a | 3661 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3662 | |
f3ded42a RS |
3663 | bfd_set_section_flags (stdoutput, sec, flags); |
3664 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3665 | |
f3ded42a RS |
3666 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3667 | } | |
3668 | else | |
3669 | { | |
3670 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3671 | .reginfo section. */ | |
3672 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3673 | bfd_set_section_flags (stdoutput, sec, flags); | |
3674 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3675 | |
f3ded42a RS |
3676 | /* Set up the option header. */ |
3677 | { | |
3678 | Elf_Internal_Options opthdr; | |
3679 | char *f; | |
3680 | ||
3681 | opthdr.kind = ODK_REGINFO; | |
3682 | opthdr.size = (sizeof (Elf_External_Options) | |
3683 | + sizeof (Elf64_External_RegInfo)); | |
3684 | opthdr.section = 0; | |
3685 | opthdr.info = 0; | |
3686 | f = frag_more (sizeof (Elf_External_Options)); | |
3687 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3688 | (Elf_External_Options *) f); | |
3689 | ||
3690 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3691 | } | |
3692 | } | |
252b5132 | 3693 | |
351cdf24 MF |
3694 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3695 | bfd_set_section_flags (stdoutput, sec, | |
3696 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3697 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3698 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3699 | ||
f3ded42a RS |
3700 | if (ECOFF_DEBUGGING) |
3701 | { | |
3702 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3703 | (void) bfd_set_section_flags (stdoutput, sec, | |
3704 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3705 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3706 | } |
f3ded42a RS |
3707 | else if (mips_flag_pdr) |
3708 | { | |
3709 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3710 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3711 | SEC_READONLY | SEC_RELOC | |
3712 | | SEC_DEBUGGING); | |
3713 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3714 | } | |
3715 | ||
3716 | subseg_set (seg, subseg); | |
3717 | } | |
252b5132 | 3718 | |
71400594 RS |
3719 | if (mips_fix_vr4120) |
3720 | init_vr4120_conflicts (); | |
252b5132 RH |
3721 | } |
3722 | ||
351cdf24 MF |
3723 | static inline void |
3724 | fpabi_incompatible_with (int fpabi, const char *what) | |
3725 | { | |
3726 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3727 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3728 | } | |
3729 | ||
3730 | static inline void | |
3731 | fpabi_requires (int fpabi, const char *what) | |
3732 | { | |
3733 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3734 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3735 | } | |
3736 | ||
3737 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3738 | static void | |
3739 | check_fpabi (int fpabi) | |
3740 | { | |
351cdf24 MF |
3741 | switch (fpabi) |
3742 | { | |
3743 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3744 | if (file_mips_opts.soft_float) |
3745 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3746 | else if (file_mips_opts.single_float) | |
3747 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3748 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3749 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3750 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3751 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3752 | break; |
3753 | ||
3754 | case Val_GNU_MIPS_ABI_FP_XX: | |
3755 | if (mips_abi != O32_ABI) | |
3756 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3757 | else if (file_mips_opts.soft_float) |
3758 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3759 | else if (file_mips_opts.single_float) | |
3760 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3761 | else if (file_mips_opts.fp != 0) |
3762 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3763 | break; |
3764 | ||
3765 | case Val_GNU_MIPS_ABI_FP_64A: | |
3766 | case Val_GNU_MIPS_ABI_FP_64: | |
3767 | if (mips_abi != O32_ABI) | |
3768 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3769 | else if (file_mips_opts.soft_float) |
3770 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3771 | else if (file_mips_opts.single_float) | |
3772 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3773 | else if (file_mips_opts.fp != 64) |
3774 | fpabi_requires (fpabi, "fp=64"); | |
3775 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3776 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3777 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3778 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3779 | break; |
3780 | ||
3781 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3782 | if (file_mips_opts.soft_float) | |
3783 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3784 | else if (!file_mips_opts.single_float) | |
3785 | fpabi_requires (fpabi, "singlefloat"); | |
3786 | break; | |
3787 | ||
3788 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3789 | if (!file_mips_opts.soft_float) | |
3790 | fpabi_requires (fpabi, "softfloat"); | |
3791 | break; | |
3792 | ||
3793 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3794 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3795 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3796 | break; | |
3797 | ||
3350cc01 CM |
3798 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3799 | /* Silently ignore compatibility value. */ | |
3800 | break; | |
3801 | ||
351cdf24 MF |
3802 | default: |
3803 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3804 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3805 | break; | |
3806 | } | |
351cdf24 MF |
3807 | } |
3808 | ||
919731af | 3809 | /* Perform consistency checks on the current options. */ |
3810 | ||
3811 | static void | |
3812 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3813 | { | |
3814 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3815 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3816 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3817 | else if (abi_checks | |
3818 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3819 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3820 | else if (abi_checks | |
3821 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3822 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3823 | ||
3824 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3825 | switch (opts->fp) | |
3826 | { | |
351cdf24 MF |
3827 | case 0: |
3828 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3829 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3830 | else if (opts->single_float == 1) | |
3831 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3832 | break; | |
919731af | 3833 | case 64: |
3834 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3835 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3836 | else if (abi_checks | |
3837 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3838 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3839 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3840 | break; | |
3841 | case 32: | |
3842 | if (abi_checks | |
3843 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3844 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
7361da2c AB |
3845 | if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0) |
3846 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); | |
919731af | 3847 | break; |
3848 | default: | |
3849 | as_bad (_("Unknown size of floating point registers")); | |
3850 | break; | |
3851 | } | |
3852 | ||
351cdf24 MF |
3853 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
3854 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
3855 | ||
919731af | 3856 | if (opts->micromips == 1 && opts->mips16 == 1) |
3857 | as_bad (_("`mips16' cannot be used with `micromips'")); | |
7361da2c AB |
3858 | else if (ISA_IS_R6 (mips_opts.isa) |
3859 | && (opts->micromips == 1 | |
3860 | || opts->mips16 == 1)) | |
3861 | as_fatal (_("`%s' can not be used with `%s'"), | |
3862 | opts->micromips ? "micromips" : "mips16", | |
3863 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
3864 | ||
3865 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
3866 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
3867 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 3868 | } |
3869 | ||
3870 | /* Perform consistency checks on the module level options exactly once. | |
3871 | This is a deferred check that happens: | |
3872 | at the first .set directive | |
3873 | or, at the first pseudo op that generates code (inc .dc.a) | |
3874 | or, at the first instruction | |
3875 | or, at the end. */ | |
3876 | ||
3877 | static void | |
3878 | file_mips_check_options (void) | |
3879 | { | |
3880 | const struct mips_cpu_info *arch_info = 0; | |
3881 | ||
3882 | if (file_mips_opts_checked) | |
3883 | return; | |
3884 | ||
3885 | /* The following code determines the register size. | |
3886 | Similar code was added to GCC 3.3 (see override_options() in | |
3887 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
3888 | as much as possible. */ | |
3889 | ||
3890 | if (file_mips_opts.gp < 0) | |
3891 | { | |
3892 | /* Infer the integer register size from the ABI and processor. | |
3893 | Restrict ourselves to 32-bit registers if that's all the | |
3894 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
3895 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
3896 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
3897 | ? 32 : 64; | |
3898 | } | |
3899 | ||
3900 | if (file_mips_opts.fp < 0) | |
3901 | { | |
3902 | /* No user specified float register size. | |
3903 | ??? GAS treats single-float processors as though they had 64-bit | |
3904 | float registers (although it complains when double-precision | |
3905 | instructions are used). As things stand, saying they have 32-bit | |
3906 | registers would lead to spurious "register must be even" messages. | |
3907 | So here we assume float registers are never smaller than the | |
3908 | integer ones. */ | |
3909 | if (file_mips_opts.gp == 64) | |
3910 | /* 64-bit integer registers implies 64-bit float registers. */ | |
3911 | file_mips_opts.fp = 64; | |
3912 | else if ((file_mips_opts.ase & FP64_ASES) | |
3913 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
3914 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
3915 | file_mips_opts.fp = 64; | |
7361da2c AB |
3916 | else if (ISA_IS_R6 (mips_opts.isa)) |
3917 | /* R6 implies 64-bit float registers. */ | |
3918 | file_mips_opts.fp = 64; | |
919731af | 3919 | else |
3920 | /* 32-bit float registers. */ | |
3921 | file_mips_opts.fp = 32; | |
3922 | } | |
3923 | ||
3924 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
3925 | ||
351cdf24 MF |
3926 | /* Disable operations on odd-numbered floating-point registers by default |
3927 | when using the FPXX ABI. */ | |
3928 | if (file_mips_opts.oddspreg < 0) | |
3929 | { | |
3930 | if (file_mips_opts.fp == 0) | |
3931 | file_mips_opts.oddspreg = 0; | |
3932 | else | |
3933 | file_mips_opts.oddspreg = 1; | |
3934 | } | |
3935 | ||
919731af | 3936 | /* End of GCC-shared inference code. */ |
3937 | ||
3938 | /* This flag is set when we have a 64-bit capable CPU but use only | |
3939 | 32-bit wide registers. Note that EABI does not use it. */ | |
3940 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
3941 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
3942 | || mips_abi == O32_ABI)) | |
3943 | mips_32bitmode = 1; | |
3944 | ||
3945 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
3946 | as_bad (_("trap exception not supported at ISA 1")); | |
3947 | ||
3948 | /* If the selected architecture includes support for ASEs, enable | |
3949 | generation of code for them. */ | |
3950 | if (file_mips_opts.mips16 == -1) | |
3951 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
3952 | if (file_mips_opts.micromips == -1) | |
3953 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
3954 | ? 1 : 0; | |
3955 | ||
7361da2c AB |
3956 | if (mips_nan2008 == -1) |
3957 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
3958 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
3959 | as_fatal (_("`%s' does not support legacy NaN"), | |
3960 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
3961 | ||
919731af | 3962 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
3963 | being selected implicitly. */ | |
3964 | if (file_mips_opts.fp != 64) | |
3965 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
3966 | ||
3967 | /* If the user didn't explicitly select or deselect a particular ASE, | |
3968 | use the default setting for the CPU. */ | |
3969 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
3970 | ||
3971 | /* Set up the current options. These may change throughout assembly. */ | |
3972 | mips_opts = file_mips_opts; | |
3973 | ||
3974 | mips_check_isa_supports_ases (); | |
3975 | mips_check_options (&file_mips_opts, TRUE); | |
3976 | file_mips_opts_checked = TRUE; | |
3977 | ||
3978 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
3979 | as_warn (_("could not set architecture and machine")); | |
3980 | } | |
3981 | ||
252b5132 | 3982 | void |
17a2f251 | 3983 | md_assemble (char *str) |
252b5132 RH |
3984 | { |
3985 | struct mips_cl_insn insn; | |
f6688943 TS |
3986 | bfd_reloc_code_real_type unused_reloc[3] |
3987 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3988 | |
919731af | 3989 | file_mips_check_options (); |
3990 | ||
252b5132 | 3991 | imm_expr.X_op = O_absent; |
252b5132 | 3992 | offset_expr.X_op = O_absent; |
f6688943 TS |
3993 | offset_reloc[0] = BFD_RELOC_UNUSED; |
3994 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
3995 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 3996 | |
e1b47bd5 RS |
3997 | mips_mark_labels (); |
3998 | mips_assembling_insn = TRUE; | |
e3de51ce | 3999 | clear_insn_error (); |
e1b47bd5 | 4000 | |
252b5132 RH |
4001 | if (mips_opts.mips16) |
4002 | mips16_ip (str, &insn); | |
4003 | else | |
4004 | { | |
4005 | mips_ip (str, &insn); | |
beae10d5 KH |
4006 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4007 | str, insn.insn_opcode)); | |
252b5132 RH |
4008 | } |
4009 | ||
e3de51ce RS |
4010 | if (insn_error.msg) |
4011 | report_insn_error (str); | |
e1b47bd5 | 4012 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4013 | { |
584892a6 | 4014 | macro_start (); |
252b5132 RH |
4015 | if (mips_opts.mips16) |
4016 | mips16_macro (&insn); | |
4017 | else | |
833794fc | 4018 | macro (&insn, str); |
584892a6 | 4019 | macro_end (); |
252b5132 RH |
4020 | } |
4021 | else | |
4022 | { | |
77bd4346 | 4023 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4024 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4025 | else |
df58fc94 | 4026 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4027 | } |
e1b47bd5 RS |
4028 | |
4029 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4030 | } |
4031 | ||
738e5348 RS |
4032 | /* Convenience functions for abstracting away the differences between |
4033 | MIPS16 and non-MIPS16 relocations. */ | |
4034 | ||
4035 | static inline bfd_boolean | |
4036 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4037 | { | |
4038 | switch (reloc) | |
4039 | { | |
4040 | case BFD_RELOC_MIPS16_JMP: | |
4041 | case BFD_RELOC_MIPS16_GPREL: | |
4042 | case BFD_RELOC_MIPS16_GOT16: | |
4043 | case BFD_RELOC_MIPS16_CALL16: | |
4044 | case BFD_RELOC_MIPS16_HI16_S: | |
4045 | case BFD_RELOC_MIPS16_HI16: | |
4046 | case BFD_RELOC_MIPS16_LO16: | |
4047 | return TRUE; | |
4048 | ||
4049 | default: | |
4050 | return FALSE; | |
4051 | } | |
4052 | } | |
4053 | ||
df58fc94 RS |
4054 | static inline bfd_boolean |
4055 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4056 | { | |
4057 | switch (reloc) | |
4058 | { | |
4059 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4060 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4061 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4062 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4063 | case BFD_RELOC_MICROMIPS_JMP: | |
4064 | case BFD_RELOC_MICROMIPS_HI16: | |
4065 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4066 | case BFD_RELOC_MICROMIPS_LO16: | |
4067 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4068 | case BFD_RELOC_MICROMIPS_GOT16: | |
4069 | case BFD_RELOC_MICROMIPS_CALL16: | |
4070 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4071 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4072 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4073 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4074 | case BFD_RELOC_MICROMIPS_SUB: | |
4075 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4076 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4077 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4078 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4079 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4080 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4081 | case BFD_RELOC_MICROMIPS_JALR: | |
4082 | return TRUE; | |
4083 | ||
4084 | default: | |
4085 | return FALSE; | |
4086 | } | |
4087 | } | |
4088 | ||
2309ddf2 MR |
4089 | static inline bfd_boolean |
4090 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4091 | { | |
4092 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4093 | } | |
4094 | ||
738e5348 RS |
4095 | static inline bfd_boolean |
4096 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4097 | { | |
2309ddf2 | 4098 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4099 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4100 | } |
4101 | ||
4102 | static inline bfd_boolean | |
4103 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4104 | { | |
2309ddf2 | 4105 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4106 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4107 | } |
4108 | ||
4109 | static inline bfd_boolean | |
4110 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4111 | { | |
2309ddf2 | 4112 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4113 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4114 | } | |
4115 | ||
df58fc94 RS |
4116 | static inline bfd_boolean |
4117 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4118 | { | |
2309ddf2 | 4119 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4120 | } |
4121 | ||
f2ae14a1 RS |
4122 | static inline bfd_boolean |
4123 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4124 | { | |
4125 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4126 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4127 | } | |
4128 | ||
2de39019 CM |
4129 | /* Return true if RELOC is a PC-relative relocation that does not have |
4130 | full address range. */ | |
4131 | ||
4132 | static inline bfd_boolean | |
4133 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4134 | { | |
4135 | switch (reloc) | |
4136 | { | |
4137 | case BFD_RELOC_16_PCREL_S2: | |
4138 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4139 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4140 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4141 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4142 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4143 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4144 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4145 | return TRUE; |
4146 | ||
b47468a6 | 4147 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4148 | case BFD_RELOC_HI16_S_PCREL: |
4149 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4150 | return HAVE_64BIT_ADDRESSES; |
4151 | ||
2de39019 CM |
4152 | default: |
4153 | return FALSE; | |
4154 | } | |
4155 | } | |
b47468a6 | 4156 | |
5919d012 | 4157 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4158 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4159 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4160 | |
4161 | static inline bfd_boolean | |
17a2f251 | 4162 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4163 | { |
3b91255e | 4164 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4165 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4166 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4167 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4168 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4169 | } | |
4170 | ||
4171 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4172 | reloc_needs_lo_p. */ | |
4173 | ||
4174 | static inline bfd_reloc_code_real_type | |
4175 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4176 | { | |
df58fc94 RS |
4177 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4178 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4179 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4180 | } |
4181 | ||
4182 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4183 | relocation. */ | |
4184 | ||
4185 | static inline bfd_boolean | |
17a2f251 | 4186 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4187 | { |
4188 | return (fixp->fx_next != NULL | |
738e5348 | 4189 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4190 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4191 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4192 | } | |
4193 | ||
462427c4 RS |
4194 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4195 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4196 | |
4197 | static void | |
462427c4 | 4198 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4199 | { |
4200 | struct insn_label_list *l; | |
4201 | valueT val; | |
4202 | ||
462427c4 | 4203 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4204 | { |
9c2799c2 | 4205 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4206 | symbol_set_frag (l->label, frag_now); |
4207 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4208 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4209 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4210 | ++val; |
4211 | S_SET_VALUE (l->label, val); | |
4212 | } | |
4213 | } | |
4214 | ||
462427c4 RS |
4215 | /* Move all labels in insn_labels to the current insertion point |
4216 | and treat them as text labels. */ | |
4217 | ||
4218 | static void | |
4219 | mips_move_text_labels (void) | |
4220 | { | |
4221 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4222 | } | |
4223 | ||
5f0fe04b TS |
4224 | static bfd_boolean |
4225 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4226 | { | |
4227 | bfd_boolean linkonce = FALSE; | |
4228 | segT symseg = S_GET_SEGMENT (sym); | |
4229 | ||
4230 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4231 | { | |
4232 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4233 | linkonce = TRUE; | |
5f0fe04b TS |
4234 | /* The GNU toolchain uses an extension for ELF: a section |
4235 | beginning with the magic string .gnu.linkonce is a | |
4236 | linkonce section. */ | |
4237 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4238 | sizeof ".gnu.linkonce" - 1) == 0) | |
4239 | linkonce = TRUE; | |
5f0fe04b TS |
4240 | } |
4241 | return linkonce; | |
4242 | } | |
4243 | ||
e1b47bd5 | 4244 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4245 | linker to handle them specially, such as generating jalx instructions |
4246 | when needed. We also make them odd for the duration of the assembly, | |
4247 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4248 | in the adjust_symtab routine, while leaving them marked. This is |
4249 | convenient for the debugger and the disassembler. The linker knows | |
4250 | to make them odd again. */ | |
4251 | ||
4252 | static void | |
e1b47bd5 | 4253 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4254 | { |
df58fc94 | 4255 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4256 | |
f3ded42a RS |
4257 | if (mips_opts.mips16) |
4258 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4259 | else | |
4260 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4261 | if ((S_GET_VALUE (label) & 1) == 0 |
4262 | /* Don't adjust the address if the label is global or weak, or | |
4263 | in a link-once section, since we'll be emitting symbol reloc | |
4264 | references to it which will be patched up by the linker, and | |
4265 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4266 | && !S_IS_WEAK (label) | |
4267 | && !S_IS_EXTERNAL (label) | |
4268 | && !s_is_linkonce (label, now_seg)) | |
4269 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4270 | } | |
4271 | ||
4272 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4273 | ||
4274 | static void | |
4275 | mips_compressed_mark_labels (void) | |
4276 | { | |
4277 | struct insn_label_list *l; | |
4278 | ||
4279 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4280 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4281 | } |
4282 | ||
4d7206a2 RS |
4283 | /* End the current frag. Make it a variant frag and record the |
4284 | relaxation info. */ | |
4285 | ||
4286 | static void | |
4287 | relax_close_frag (void) | |
4288 | { | |
584892a6 | 4289 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4290 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 4291 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
4292 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4293 | ||
4294 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4295 | mips_relax.first_fixup = 0; | |
4296 | } | |
4297 | ||
4298 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4299 | See the comment above RELAX_ENCODE for more details. */ | |
4300 | ||
4301 | static void | |
4302 | relax_start (symbolS *symbol) | |
4303 | { | |
9c2799c2 | 4304 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4305 | mips_relax.sequence = 1; |
4306 | mips_relax.symbol = symbol; | |
4307 | } | |
4308 | ||
4309 | /* Start generating the second version of a relaxable sequence. | |
4310 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4311 | |
4312 | static void | |
4d7206a2 RS |
4313 | relax_switch (void) |
4314 | { | |
9c2799c2 | 4315 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4316 | mips_relax.sequence = 2; |
4317 | } | |
4318 | ||
4319 | /* End the current relaxable sequence. */ | |
4320 | ||
4321 | static void | |
4322 | relax_end (void) | |
4323 | { | |
9c2799c2 | 4324 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4325 | relax_close_frag (); |
4326 | mips_relax.sequence = 0; | |
4327 | } | |
4328 | ||
11625dd8 RS |
4329 | /* Return true if IP is a delayed branch or jump. */ |
4330 | ||
4331 | static inline bfd_boolean | |
4332 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4333 | { | |
4334 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4335 | | INSN_COND_BRANCH_DELAY | |
4336 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4337 | } | |
4338 | ||
4339 | /* Return true if IP is a compact branch or jump. */ | |
4340 | ||
4341 | static inline bfd_boolean | |
4342 | compact_branch_p (const struct mips_cl_insn *ip) | |
4343 | { | |
26545944 RS |
4344 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4345 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4346 | } |
4347 | ||
4348 | /* Return true if IP is an unconditional branch or jump. */ | |
4349 | ||
4350 | static inline bfd_boolean | |
4351 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4352 | { | |
4353 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4354 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4355 | } |
4356 | ||
4357 | /* Return true if IP is a branch-likely instruction. */ | |
4358 | ||
4359 | static inline bfd_boolean | |
4360 | branch_likely_p (const struct mips_cl_insn *ip) | |
4361 | { | |
4362 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4363 | } | |
4364 | ||
14fe068b RS |
4365 | /* Return the type of nop that should be used to fill the delay slot |
4366 | of delayed branch IP. */ | |
4367 | ||
4368 | static struct mips_cl_insn * | |
4369 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4370 | { | |
4371 | if (mips_opts.micromips | |
4372 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4373 | return µmips_nop32_insn; | |
4374 | return NOP_INSN; | |
4375 | } | |
4376 | ||
fc76e730 RS |
4377 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4378 | in operand N. */ | |
df58fc94 RS |
4379 | |
4380 | static unsigned int | |
fc76e730 | 4381 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4382 | { |
fc76e730 RS |
4383 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4384 | } | |
df58fc94 | 4385 | |
fc76e730 RS |
4386 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4387 | in operand N. */ | |
4388 | ||
4389 | static unsigned int | |
4390 | insn_write_mask (const struct mips_opcode *opcode) | |
4391 | { | |
4392 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4393 | } | |
4394 | ||
4395 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4396 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4397 | is set. */ | |
4398 | ||
4399 | static unsigned int | |
4400 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4401 | const struct mips_operand *operand, | |
4402 | unsigned int type_mask) | |
4403 | { | |
4404 | unsigned int uval, vsel; | |
4405 | ||
4406 | switch (operand->type) | |
df58fc94 | 4407 | { |
fc76e730 RS |
4408 | case OP_INT: |
4409 | case OP_MAPPED_INT: | |
4410 | case OP_MSB: | |
4411 | case OP_PCREL: | |
4412 | case OP_PERF_REG: | |
4413 | case OP_ADDIUSP_INT: | |
4414 | case OP_ENTRY_EXIT_LIST: | |
4415 | case OP_REPEAT_DEST_REG: | |
4416 | case OP_REPEAT_PREV_REG: | |
4417 | case OP_PC: | |
14daeee3 RS |
4418 | case OP_VU0_SUFFIX: |
4419 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4420 | case OP_IMM_INDEX: |
fc76e730 RS |
4421 | abort (); |
4422 | ||
4423 | case OP_REG: | |
0f35dbc4 | 4424 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4425 | { |
4426 | const struct mips_reg_operand *reg_op; | |
4427 | ||
4428 | reg_op = (const struct mips_reg_operand *) operand; | |
4429 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4430 | return 0; | |
4431 | uval = insn_extract_operand (insn, operand); | |
4432 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4433 | } | |
4434 | ||
4435 | case OP_REG_PAIR: | |
4436 | { | |
4437 | const struct mips_reg_pair_operand *pair_op; | |
4438 | ||
4439 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4440 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4441 | return 0; | |
4442 | uval = insn_extract_operand (insn, operand); | |
4443 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4444 | } | |
4445 | ||
4446 | case OP_CLO_CLZ_DEST: | |
4447 | if (!(type_mask & (1 << OP_REG_GP))) | |
4448 | return 0; | |
4449 | uval = insn_extract_operand (insn, operand); | |
4450 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4451 | ||
7361da2c AB |
4452 | case OP_SAME_RS_RT: |
4453 | if (!(type_mask & (1 << OP_REG_GP))) | |
4454 | return 0; | |
4455 | uval = insn_extract_operand (insn, operand); | |
4456 | gas_assert ((uval & 31) == (uval >> 5)); | |
4457 | return 1 << (uval & 31); | |
4458 | ||
4459 | case OP_CHECK_PREV: | |
4460 | case OP_NON_ZERO_REG: | |
4461 | if (!(type_mask & (1 << OP_REG_GP))) | |
4462 | return 0; | |
4463 | uval = insn_extract_operand (insn, operand); | |
4464 | return 1 << (uval & 31); | |
4465 | ||
fc76e730 RS |
4466 | case OP_LWM_SWM_LIST: |
4467 | abort (); | |
4468 | ||
4469 | case OP_SAVE_RESTORE_LIST: | |
4470 | abort (); | |
4471 | ||
4472 | case OP_MDMX_IMM_REG: | |
4473 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4474 | return 0; | |
4475 | uval = insn_extract_operand (insn, operand); | |
4476 | vsel = uval >> 5; | |
4477 | if ((vsel & 0x18) == 0x18) | |
4478 | return 0; | |
4479 | return 1 << (uval & 31); | |
56d438b1 CF |
4480 | |
4481 | case OP_REG_INDEX: | |
4482 | if (!(type_mask & (1 << OP_REG_GP))) | |
4483 | return 0; | |
4484 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4485 | } |
fc76e730 RS |
4486 | abort (); |
4487 | } | |
4488 | ||
4489 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4490 | where bit N of OPNO_MASK is set if operand N should be included. | |
4491 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4492 | is set. */ | |
4493 | ||
4494 | static unsigned int | |
4495 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4496 | unsigned int type_mask, unsigned int opno_mask) | |
4497 | { | |
4498 | unsigned int opno, reg_mask; | |
4499 | ||
4500 | opno = 0; | |
4501 | reg_mask = 0; | |
4502 | while (opno_mask != 0) | |
4503 | { | |
4504 | if (opno_mask & 1) | |
4505 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4506 | opno_mask >>= 1; | |
4507 | opno += 1; | |
4508 | } | |
4509 | return reg_mask; | |
df58fc94 RS |
4510 | } |
4511 | ||
4c260379 RS |
4512 | /* Return the mask of core registers that IP reads. */ |
4513 | ||
4514 | static unsigned int | |
4515 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4516 | { | |
4517 | unsigned long pinfo, pinfo2; | |
4518 | unsigned int mask; | |
4519 | ||
fc76e730 | 4520 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4521 | pinfo = ip->insn_mo->pinfo; |
4522 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4523 | if (pinfo & INSN_UDI) |
4c260379 | 4524 | { |
fc76e730 RS |
4525 | /* UDI instructions have traditionally been assumed to read RS |
4526 | and RT. */ | |
4527 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4528 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4529 | } |
fc76e730 RS |
4530 | if (pinfo & INSN_READ_GPR_24) |
4531 | mask |= 1 << 24; | |
4532 | if (pinfo2 & INSN2_READ_GPR_16) | |
4533 | mask |= 1 << 16; | |
4534 | if (pinfo2 & INSN2_READ_SP) | |
4535 | mask |= 1 << SP; | |
26545944 | 4536 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4537 | mask |= 1 << 31; |
fe35f09f RS |
4538 | /* Don't include register 0. */ |
4539 | return mask & ~1; | |
4c260379 RS |
4540 | } |
4541 | ||
4542 | /* Return the mask of core registers that IP writes. */ | |
4543 | ||
4544 | static unsigned int | |
4545 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4546 | { | |
4547 | unsigned long pinfo, pinfo2; | |
4548 | unsigned int mask; | |
4549 | ||
fc76e730 | 4550 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4551 | pinfo = ip->insn_mo->pinfo; |
4552 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4553 | if (pinfo & INSN_WRITE_GPR_24) |
4554 | mask |= 1 << 24; | |
4555 | if (pinfo & INSN_WRITE_GPR_31) | |
4556 | mask |= 1 << 31; | |
4557 | if (pinfo & INSN_UDI) | |
4558 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4559 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4560 | if (pinfo2 & INSN2_WRITE_SP) | |
4561 | mask |= 1 << SP; | |
fe35f09f RS |
4562 | /* Don't include register 0. */ |
4563 | return mask & ~1; | |
4c260379 RS |
4564 | } |
4565 | ||
4566 | /* Return the mask of floating-point registers that IP reads. */ | |
4567 | ||
4568 | static unsigned int | |
4569 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4570 | { | |
fc76e730 | 4571 | unsigned long pinfo; |
4c260379 RS |
4572 | unsigned int mask; |
4573 | ||
9d5de888 CF |
4574 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4575 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4576 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4577 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4578 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4579 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4580 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4581 | mask |= mask << 1; |
4582 | return mask; | |
4583 | } | |
4584 | ||
4585 | /* Return the mask of floating-point registers that IP writes. */ | |
4586 | ||
4587 | static unsigned int | |
4588 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4589 | { | |
fc76e730 | 4590 | unsigned long pinfo; |
4c260379 RS |
4591 | unsigned int mask; |
4592 | ||
9d5de888 CF |
4593 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4594 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4595 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4596 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4597 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4598 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4599 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4600 | mask |= mask << 1; |
4601 | return mask; | |
4602 | } | |
4603 | ||
a1d78564 RS |
4604 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4605 | Check whether that is allowed. */ | |
4606 | ||
4607 | static bfd_boolean | |
4608 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4609 | { | |
4610 | const char *s = insn->name; | |
351cdf24 MF |
4611 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4612 | || FPR_SIZE == 64) | |
4613 | && mips_opts.oddspreg; | |
a1d78564 RS |
4614 | |
4615 | if (insn->pinfo == INSN_MACRO) | |
4616 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4617 | return TRUE; | |
4618 | ||
351cdf24 MF |
4619 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4620 | otherwise it depends on oddspreg. */ | |
4621 | if ((insn->pinfo & FP_S) | |
4622 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4623 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4624 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4625 | |
351cdf24 MF |
4626 | /* Allow odd registers for single-precision ops and double-precision if the |
4627 | floating-point registers are 64-bit wide. */ | |
4628 | switch (insn->pinfo & (FP_S | FP_D)) | |
4629 | { | |
4630 | case FP_S: | |
4631 | case 0: | |
4632 | return oddspreg; | |
4633 | case FP_D: | |
4634 | return FPR_SIZE == 64; | |
4635 | default: | |
4636 | break; | |
a1d78564 RS |
4637 | } |
4638 | ||
351cdf24 MF |
4639 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4640 | s = strchr (insn->name, '.'); | |
4641 | if (s != NULL && opnum == 2) | |
4642 | s = strchr (s + 1, '.'); | |
4643 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4644 | return oddspreg; | |
a1d78564 | 4645 | |
351cdf24 | 4646 | return FPR_SIZE == 64; |
a1d78564 RS |
4647 | } |
4648 | ||
a1d78564 RS |
4649 | /* Information about an instruction argument that we're trying to match. */ |
4650 | struct mips_arg_info | |
4651 | { | |
4652 | /* The instruction so far. */ | |
4653 | struct mips_cl_insn *insn; | |
4654 | ||
a92713e6 RS |
4655 | /* The first unconsumed operand token. */ |
4656 | struct mips_operand_token *token; | |
4657 | ||
a1d78564 RS |
4658 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4659 | int opnum; | |
4660 | ||
4661 | /* The 1-based argument number, for error reporting. This does not | |
4662 | count elided optional registers, etc.. */ | |
4663 | int argnum; | |
4664 | ||
4665 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4666 | unsigned int last_regno; | |
4667 | ||
4668 | /* If the first operand was an OP_REG, this is the register that it | |
4669 | specified, otherwise it is ILLEGAL_REG. */ | |
4670 | unsigned int dest_regno; | |
4671 | ||
4672 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4673 | where it gives the lsb position. */ | |
4674 | unsigned int last_op_int; | |
4675 | ||
60f20e8b RS |
4676 | /* If true, match routines should assume that no later instruction |
4677 | alternative matches and should therefore be as accomodating as | |
4678 | possible. Match routines should not report errors if something | |
4679 | is only invalid for !LAX_MATCH. */ | |
4680 | bfd_boolean lax_match; | |
a1d78564 | 4681 | |
a1d78564 RS |
4682 | /* True if a reference to the current AT register was seen. */ |
4683 | bfd_boolean seen_at; | |
4684 | }; | |
4685 | ||
1a00e612 RS |
4686 | /* Record that the argument is out of range. */ |
4687 | ||
4688 | static void | |
4689 | match_out_of_range (struct mips_arg_info *arg) | |
4690 | { | |
4691 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4692 | } | |
4693 | ||
4694 | /* Record that the argument isn't constant but needs to be. */ | |
4695 | ||
4696 | static void | |
4697 | match_not_constant (struct mips_arg_info *arg) | |
4698 | { | |
4699 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4700 | arg->argnum); | |
4701 | } | |
4702 | ||
a92713e6 RS |
4703 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4704 | and return true on success, otherwise return false. */ | |
a1d78564 | 4705 | |
a92713e6 RS |
4706 | static bfd_boolean |
4707 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4708 | { |
a92713e6 RS |
4709 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4710 | { | |
4711 | ++arg->token; | |
4712 | if (ch == ',') | |
4713 | arg->argnum += 1; | |
4714 | return TRUE; | |
4715 | } | |
4716 | return FALSE; | |
4717 | } | |
a1d78564 | 4718 | |
a92713e6 RS |
4719 | /* Try to get an expression from the next tokens in ARG. Consume the |
4720 | tokens and return true on success, storing the expression value in | |
4721 | VALUE and relocation types in R. */ | |
4722 | ||
4723 | static bfd_boolean | |
4724 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4725 | bfd_reloc_code_real_type *r) | |
4726 | { | |
d436c1c2 RS |
4727 | /* If the next token is a '(' that was parsed as being part of a base |
4728 | expression, assume we have an elided offset. The later match will fail | |
4729 | if this turns out to be wrong. */ | |
4730 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4731 | { |
d436c1c2 RS |
4732 | value->X_op = O_constant; |
4733 | value->X_add_number = 0; | |
4734 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4735 | return TRUE; |
4736 | } | |
4737 | ||
d436c1c2 RS |
4738 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4739 | For plain registers the default error seems more appropriate. */ | |
4740 | if (arg->token->type == OT_INTEGER | |
4741 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4742 | { |
d436c1c2 RS |
4743 | set_insn_error (arg->argnum, _("register value used as expression")); |
4744 | return FALSE; | |
a1d78564 | 4745 | } |
d436c1c2 RS |
4746 | |
4747 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4748 | { |
d436c1c2 RS |
4749 | *value = arg->token->u.integer.value; |
4750 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4751 | ++arg->token; | |
4752 | return TRUE; | |
a92713e6 | 4753 | } |
a92713e6 | 4754 | |
d436c1c2 RS |
4755 | set_insn_error_i |
4756 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4757 | arg->argnum); | |
4758 | return FALSE; | |
a92713e6 RS |
4759 | } |
4760 | ||
4761 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
4762 | the tokens and return return true on success, storing the constant value | |
4763 | in *VALUE. Use FALLBACK as the value if the match succeeded with an | |
4764 | error. */ | |
4765 | ||
4766 | static bfd_boolean | |
1a00e612 | 4767 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4768 | { |
4769 | expressionS ex; | |
4770 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4771 | |
a92713e6 RS |
4772 | if (!match_expression (arg, &ex, r)) |
4773 | return FALSE; | |
4774 | ||
4775 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4776 | *value = ex.X_add_number; |
4777 | else | |
4778 | { | |
1a00e612 RS |
4779 | match_not_constant (arg); |
4780 | return FALSE; | |
a1d78564 | 4781 | } |
a92713e6 | 4782 | return TRUE; |
a1d78564 RS |
4783 | } |
4784 | ||
4785 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4786 | appears in instruction OPCODE. */ | |
4787 | ||
4788 | static unsigned int | |
4789 | convert_reg_type (const struct mips_opcode *opcode, | |
4790 | enum mips_reg_operand_type type) | |
4791 | { | |
4792 | switch (type) | |
4793 | { | |
4794 | case OP_REG_GP: | |
4795 | return RTYPE_NUM | RTYPE_GP; | |
4796 | ||
4797 | case OP_REG_FP: | |
4798 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4799 | FPR load, store or move (including moves to and from GPRs). */ | |
4800 | if ((mips_opts.ase & ASE_MDMX) | |
4801 | && (opcode->pinfo & FP_D) | |
43885403 | 4802 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4803 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4804 | | INSN_LOAD_COPROC |
67dc82bc | 4805 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4806 | | INSN_STORE_MEMORY))) |
4807 | return RTYPE_FPU | RTYPE_VEC; | |
4808 | return RTYPE_FPU; | |
4809 | ||
4810 | case OP_REG_CCC: | |
4811 | if (opcode->pinfo & (FP_D | FP_S)) | |
4812 | return RTYPE_CCC | RTYPE_FCC; | |
4813 | return RTYPE_CCC; | |
4814 | ||
4815 | case OP_REG_VEC: | |
4816 | if (opcode->membership & INSN_5400) | |
4817 | return RTYPE_FPU; | |
4818 | return RTYPE_FPU | RTYPE_VEC; | |
4819 | ||
4820 | case OP_REG_ACC: | |
4821 | return RTYPE_ACC; | |
4822 | ||
4823 | case OP_REG_COPRO: | |
4824 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4825 | return RTYPE_NUM | RTYPE_CP0; | |
4826 | return RTYPE_NUM; | |
4827 | ||
4828 | case OP_REG_HW: | |
4829 | return RTYPE_NUM; | |
14daeee3 RS |
4830 | |
4831 | case OP_REG_VI: | |
4832 | return RTYPE_NUM | RTYPE_VI; | |
4833 | ||
4834 | case OP_REG_VF: | |
4835 | return RTYPE_NUM | RTYPE_VF; | |
4836 | ||
4837 | case OP_REG_R5900_I: | |
4838 | return RTYPE_R5900_I; | |
4839 | ||
4840 | case OP_REG_R5900_Q: | |
4841 | return RTYPE_R5900_Q; | |
4842 | ||
4843 | case OP_REG_R5900_R: | |
4844 | return RTYPE_R5900_R; | |
4845 | ||
4846 | case OP_REG_R5900_ACC: | |
4847 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4848 | |
4849 | case OP_REG_MSA: | |
4850 | return RTYPE_MSA; | |
4851 | ||
4852 | case OP_REG_MSA_CTRL: | |
4853 | return RTYPE_NUM; | |
a1d78564 RS |
4854 | } |
4855 | abort (); | |
4856 | } | |
4857 | ||
4858 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
4859 | ||
4860 | static void | |
4861 | check_regno (struct mips_arg_info *arg, | |
4862 | enum mips_reg_operand_type type, unsigned int regno) | |
4863 | { | |
4864 | if (AT && type == OP_REG_GP && regno == AT) | |
4865 | arg->seen_at = TRUE; | |
4866 | ||
4867 | if (type == OP_REG_FP | |
4868 | && (regno & 1) != 0 | |
a1d78564 | 4869 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
4870 | { |
4871 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
4872 | so maintain a warning for FP32 but raise an error for the new | |
4873 | cases. */ | |
4874 | if (FPR_SIZE == 32) | |
4875 | as_warn (_("float register should be even, was %d"), regno); | |
4876 | else | |
4877 | as_bad (_("float register should be even, was %d"), regno); | |
4878 | } | |
a1d78564 RS |
4879 | |
4880 | if (type == OP_REG_CCC) | |
4881 | { | |
4882 | const char *name; | |
4883 | size_t length; | |
4884 | ||
4885 | name = arg->insn->insn_mo->name; | |
4886 | length = strlen (name); | |
4887 | if ((regno & 1) != 0 | |
4888 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
4889 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 4890 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
4891 | name, regno); |
4892 | ||
4893 | if ((regno & 3) != 0 | |
4894 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 4895 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
4896 | name, regno); |
4897 | } | |
4898 | } | |
4899 | ||
a92713e6 RS |
4900 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
4901 | a register of type TYPE. Return true on success, storing the register | |
4902 | number in *REGNO and warning about any dubious uses. */ | |
4903 | ||
4904 | static bfd_boolean | |
4905 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4906 | unsigned int symval, unsigned int *regno) | |
4907 | { | |
4908 | if (type == OP_REG_VEC) | |
4909 | symval = mips_prefer_vec_regno (symval); | |
4910 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
4911 | return FALSE; | |
4912 | ||
4913 | *regno = symval & RNUM_MASK; | |
4914 | check_regno (arg, type, *regno); | |
4915 | return TRUE; | |
4916 | } | |
4917 | ||
4918 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
4919 | Consume the token and return true on success, storing the register | |
4920 | number in *REGNO. Return false on failure. */ | |
4921 | ||
4922 | static bfd_boolean | |
4923 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4924 | unsigned int *regno) | |
4925 | { | |
4926 | if (arg->token->type == OT_REG | |
4927 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
4928 | { | |
4929 | ++arg->token; | |
4930 | return TRUE; | |
4931 | } | |
4932 | return FALSE; | |
4933 | } | |
4934 | ||
4935 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
4936 | Consume the token and return true on success, storing the register numbers | |
4937 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
4938 | ||
4939 | static bfd_boolean | |
4940 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4941 | unsigned int *regno1, unsigned int *regno2) | |
4942 | { | |
4943 | if (match_reg (arg, type, regno1)) | |
4944 | { | |
4945 | *regno2 = *regno1; | |
4946 | return TRUE; | |
4947 | } | |
4948 | if (arg->token->type == OT_REG_RANGE | |
4949 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
4950 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
4951 | && *regno1 <= *regno2) | |
4952 | { | |
4953 | ++arg->token; | |
4954 | return TRUE; | |
4955 | } | |
4956 | return FALSE; | |
4957 | } | |
4958 | ||
a1d78564 RS |
4959 | /* OP_INT matcher. */ |
4960 | ||
a92713e6 | 4961 | static bfd_boolean |
a1d78564 | 4962 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 4963 | const struct mips_operand *operand_base) |
a1d78564 RS |
4964 | { |
4965 | const struct mips_int_operand *operand; | |
3ccad066 | 4966 | unsigned int uval; |
a1d78564 RS |
4967 | int min_val, max_val, factor; |
4968 | offsetT sval; | |
a1d78564 RS |
4969 | |
4970 | operand = (const struct mips_int_operand *) operand_base; | |
4971 | factor = 1 << operand->shift; | |
3ccad066 RS |
4972 | min_val = mips_int_operand_min (operand); |
4973 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 4974 | |
d436c1c2 RS |
4975 | if (operand_base->lsb == 0 |
4976 | && operand_base->size == 16 | |
4977 | && operand->shift == 0 | |
4978 | && operand->bias == 0 | |
4979 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
4980 | { |
4981 | /* The operand can be relocated. */ | |
a92713e6 RS |
4982 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
4983 | return FALSE; | |
4984 | ||
4985 | if (offset_reloc[0] != BFD_RELOC_UNUSED) | |
a1d78564 RS |
4986 | /* Relocation operators were used. Accept the arguent and |
4987 | leave the relocation value in offset_expr and offset_relocs | |
4988 | for the caller to process. */ | |
a92713e6 RS |
4989 | return TRUE; |
4990 | ||
4991 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 4992 | { |
60f20e8b RS |
4993 | /* Accept non-constant operands if no later alternative matches, |
4994 | leaving it for the caller to process. */ | |
4995 | if (!arg->lax_match) | |
4996 | return FALSE; | |
a92713e6 RS |
4997 | offset_reloc[0] = BFD_RELOC_LO16; |
4998 | return TRUE; | |
a1d78564 | 4999 | } |
a92713e6 | 5000 | |
a1d78564 RS |
5001 | /* Clear the global state; we're going to install the operand |
5002 | ourselves. */ | |
a92713e6 | 5003 | sval = offset_expr.X_add_number; |
a1d78564 | 5004 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5005 | |
5006 | /* For compatibility with older assemblers, we accept | |
5007 | 0x8000-0xffff as signed 16-bit numbers when only | |
5008 | signed numbers are allowed. */ | |
5009 | if (sval > max_val) | |
5010 | { | |
5011 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5012 | if (!arg->lax_match && sval <= max_val) | |
5013 | return FALSE; | |
5014 | } | |
a1d78564 RS |
5015 | } |
5016 | else | |
5017 | { | |
1a00e612 | 5018 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5019 | return FALSE; |
a1d78564 RS |
5020 | } |
5021 | ||
5022 | arg->last_op_int = sval; | |
5023 | ||
1a00e612 | 5024 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5025 | { |
1a00e612 RS |
5026 | match_out_of_range (arg); |
5027 | return FALSE; | |
a1d78564 RS |
5028 | } |
5029 | ||
5030 | uval = (unsigned int) sval >> operand->shift; | |
5031 | uval -= operand->bias; | |
5032 | ||
5033 | /* Handle -mfix-cn63xxp1. */ | |
5034 | if (arg->opnum == 1 | |
5035 | && mips_fix_cn63xxp1 | |
5036 | && !mips_opts.micromips | |
5037 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5038 | switch (uval) | |
5039 | { | |
5040 | case 5: | |
5041 | case 25: | |
5042 | case 26: | |
5043 | case 27: | |
5044 | case 28: | |
5045 | case 29: | |
5046 | case 30: | |
5047 | case 31: | |
5048 | /* These are ok. */ | |
5049 | break; | |
5050 | ||
5051 | default: | |
5052 | /* The rest must be changed to 28. */ | |
5053 | uval = 28; | |
5054 | break; | |
5055 | } | |
5056 | ||
5057 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5058 | return TRUE; |
a1d78564 RS |
5059 | } |
5060 | ||
5061 | /* OP_MAPPED_INT matcher. */ | |
5062 | ||
a92713e6 | 5063 | static bfd_boolean |
a1d78564 | 5064 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5065 | const struct mips_operand *operand_base) |
a1d78564 RS |
5066 | { |
5067 | const struct mips_mapped_int_operand *operand; | |
5068 | unsigned int uval, num_vals; | |
5069 | offsetT sval; | |
5070 | ||
5071 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5072 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5073 | return FALSE; |
a1d78564 RS |
5074 | |
5075 | num_vals = 1 << operand_base->size; | |
5076 | for (uval = 0; uval < num_vals; uval++) | |
5077 | if (operand->int_map[uval] == sval) | |
5078 | break; | |
5079 | if (uval == num_vals) | |
1a00e612 RS |
5080 | { |
5081 | match_out_of_range (arg); | |
5082 | return FALSE; | |
5083 | } | |
a1d78564 RS |
5084 | |
5085 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5086 | return TRUE; |
a1d78564 RS |
5087 | } |
5088 | ||
5089 | /* OP_MSB matcher. */ | |
5090 | ||
a92713e6 | 5091 | static bfd_boolean |
a1d78564 | 5092 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5093 | const struct mips_operand *operand_base) |
a1d78564 RS |
5094 | { |
5095 | const struct mips_msb_operand *operand; | |
5096 | int min_val, max_val, max_high; | |
5097 | offsetT size, sval, high; | |
5098 | ||
5099 | operand = (const struct mips_msb_operand *) operand_base; | |
5100 | min_val = operand->bias; | |
5101 | max_val = min_val + (1 << operand_base->size) - 1; | |
5102 | max_high = operand->opsize; | |
5103 | ||
1a00e612 | 5104 | if (!match_const_int (arg, &size)) |
a92713e6 | 5105 | return FALSE; |
a1d78564 RS |
5106 | |
5107 | high = size + arg->last_op_int; | |
5108 | sval = operand->add_lsb ? high : size; | |
5109 | ||
5110 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5111 | { | |
1a00e612 RS |
5112 | match_out_of_range (arg); |
5113 | return FALSE; | |
a1d78564 RS |
5114 | } |
5115 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5116 | return TRUE; |
a1d78564 RS |
5117 | } |
5118 | ||
5119 | /* OP_REG matcher. */ | |
5120 | ||
a92713e6 | 5121 | static bfd_boolean |
a1d78564 | 5122 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5123 | const struct mips_operand *operand_base) |
a1d78564 RS |
5124 | { |
5125 | const struct mips_reg_operand *operand; | |
a92713e6 | 5126 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5127 | |
5128 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5129 | if (!match_reg (arg, operand->reg_type, ®no)) |
5130 | return FALSE; | |
a1d78564 RS |
5131 | |
5132 | if (operand->reg_map) | |
5133 | { | |
5134 | num_vals = 1 << operand->root.size; | |
5135 | for (uval = 0; uval < num_vals; uval++) | |
5136 | if (operand->reg_map[uval] == regno) | |
5137 | break; | |
5138 | if (num_vals == uval) | |
a92713e6 | 5139 | return FALSE; |
a1d78564 RS |
5140 | } |
5141 | else | |
5142 | uval = regno; | |
5143 | ||
a1d78564 RS |
5144 | arg->last_regno = regno; |
5145 | if (arg->opnum == 1) | |
5146 | arg->dest_regno = regno; | |
5147 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5148 | return TRUE; |
a1d78564 RS |
5149 | } |
5150 | ||
5151 | /* OP_REG_PAIR matcher. */ | |
5152 | ||
a92713e6 | 5153 | static bfd_boolean |
a1d78564 | 5154 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5155 | const struct mips_operand *operand_base) |
a1d78564 RS |
5156 | { |
5157 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5158 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5159 | |
5160 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5161 | if (!match_reg (arg, operand->reg_type, ®no1) |
5162 | || !match_char (arg, ',') | |
5163 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5164 | return FALSE; | |
a1d78564 RS |
5165 | |
5166 | num_vals = 1 << operand_base->size; | |
5167 | for (uval = 0; uval < num_vals; uval++) | |
5168 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5169 | break; | |
5170 | if (uval == num_vals) | |
a92713e6 | 5171 | return FALSE; |
a1d78564 | 5172 | |
a1d78564 | 5173 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5174 | return TRUE; |
a1d78564 RS |
5175 | } |
5176 | ||
5177 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5178 | ||
a92713e6 RS |
5179 | static bfd_boolean |
5180 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5181 | { |
a92713e6 RS |
5182 | bfd_reloc_code_real_type r[3]; |
5183 | ||
5184 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5185 | } |
5186 | ||
5187 | /* OP_PERF_REG matcher. */ | |
5188 | ||
a92713e6 | 5189 | static bfd_boolean |
a1d78564 | 5190 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5191 | const struct mips_operand *operand) |
a1d78564 RS |
5192 | { |
5193 | offsetT sval; | |
5194 | ||
1a00e612 | 5195 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5196 | return FALSE; |
a1d78564 RS |
5197 | |
5198 | if (sval != 0 | |
5199 | && (sval != 1 | |
5200 | || (mips_opts.arch == CPU_R5900 | |
5201 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5202 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5203 | { | |
1a00e612 RS |
5204 | set_insn_error (arg->argnum, _("invalid performance register")); |
5205 | return FALSE; | |
a1d78564 RS |
5206 | } |
5207 | ||
5208 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5209 | return TRUE; |
a1d78564 RS |
5210 | } |
5211 | ||
5212 | /* OP_ADDIUSP matcher. */ | |
5213 | ||
a92713e6 | 5214 | static bfd_boolean |
a1d78564 | 5215 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5216 | const struct mips_operand *operand) |
a1d78564 RS |
5217 | { |
5218 | offsetT sval; | |
5219 | unsigned int uval; | |
5220 | ||
1a00e612 | 5221 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5222 | return FALSE; |
a1d78564 RS |
5223 | |
5224 | if (sval % 4) | |
1a00e612 RS |
5225 | { |
5226 | match_out_of_range (arg); | |
5227 | return FALSE; | |
5228 | } | |
a1d78564 RS |
5229 | |
5230 | sval /= 4; | |
5231 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5232 | { |
5233 | match_out_of_range (arg); | |
5234 | return FALSE; | |
5235 | } | |
a1d78564 RS |
5236 | |
5237 | uval = (unsigned int) sval; | |
5238 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5239 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5240 | return TRUE; |
a1d78564 RS |
5241 | } |
5242 | ||
5243 | /* OP_CLO_CLZ_DEST matcher. */ | |
5244 | ||
a92713e6 | 5245 | static bfd_boolean |
a1d78564 | 5246 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5247 | const struct mips_operand *operand) |
a1d78564 RS |
5248 | { |
5249 | unsigned int regno; | |
5250 | ||
a92713e6 RS |
5251 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5252 | return FALSE; | |
a1d78564 | 5253 | |
a1d78564 | 5254 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5255 | return TRUE; |
a1d78564 RS |
5256 | } |
5257 | ||
7361da2c AB |
5258 | /* OP_CHECK_PREV matcher. */ |
5259 | ||
5260 | static bfd_boolean | |
5261 | match_check_prev_operand (struct mips_arg_info *arg, | |
5262 | const struct mips_operand *operand_base) | |
5263 | { | |
5264 | const struct mips_check_prev_operand *operand; | |
5265 | unsigned int regno; | |
5266 | ||
5267 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5268 | ||
5269 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5270 | return FALSE; | |
5271 | ||
5272 | if (!operand->zero_ok && regno == 0) | |
5273 | return FALSE; | |
5274 | ||
5275 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5276 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5277 | || (operand->equal_ok && regno == arg->last_regno)) | |
5278 | { | |
5279 | arg->last_regno = regno; | |
5280 | insn_insert_operand (arg->insn, operand_base, regno); | |
5281 | return TRUE; | |
5282 | } | |
5283 | ||
5284 | return FALSE; | |
5285 | } | |
5286 | ||
5287 | /* OP_SAME_RS_RT matcher. */ | |
5288 | ||
5289 | static bfd_boolean | |
5290 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5291 | const struct mips_operand *operand) | |
5292 | { | |
5293 | unsigned int regno; | |
5294 | ||
5295 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5296 | return FALSE; | |
5297 | ||
5298 | if (regno == 0) | |
5299 | { | |
5300 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5301 | return FALSE; | |
5302 | } | |
5303 | ||
5304 | arg->last_regno = regno; | |
5305 | ||
5306 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5307 | return TRUE; | |
5308 | } | |
5309 | ||
a1d78564 RS |
5310 | /* OP_LWM_SWM_LIST matcher. */ |
5311 | ||
a92713e6 | 5312 | static bfd_boolean |
a1d78564 | 5313 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5314 | const struct mips_operand *operand) |
a1d78564 | 5315 | { |
a92713e6 RS |
5316 | unsigned int reglist, sregs, ra, regno1, regno2; |
5317 | struct mips_arg_info reset; | |
a1d78564 | 5318 | |
a92713e6 RS |
5319 | reglist = 0; |
5320 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5321 | return FALSE; | |
5322 | do | |
5323 | { | |
5324 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5325 | { | |
5326 | reglist |= 1 << FP; | |
5327 | regno2 = S7; | |
5328 | } | |
5329 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5330 | reset = *arg; | |
5331 | } | |
5332 | while (match_char (arg, ',') | |
5333 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5334 | *arg = reset; | |
a1d78564 RS |
5335 | |
5336 | if (operand->size == 2) | |
5337 | { | |
5338 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5339 | ||
5340 | s0, ra | |
5341 | s0, s1, ra, s2, s3 | |
5342 | s0-s2, ra | |
5343 | ||
5344 | and any permutations of these. */ | |
5345 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5346 | return FALSE; |
a1d78564 RS |
5347 | |
5348 | sregs = (reglist >> 17) & 7; | |
5349 | ra = 0; | |
5350 | } | |
5351 | else | |
5352 | { | |
5353 | /* The list must include at least one of ra and s0-sN, | |
5354 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5355 | which are $23 and $30 respectively.) E.g.: | |
5356 | ||
5357 | ra | |
5358 | s0 | |
5359 | ra, s0, s1, s2 | |
5360 | s0-s8 | |
5361 | s0-s5, ra | |
5362 | ||
5363 | and any permutations of these. */ | |
5364 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5365 | return FALSE; |
a1d78564 RS |
5366 | |
5367 | ra = (reglist >> 27) & 0x10; | |
5368 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5369 | } | |
5370 | sregs += 1; | |
5371 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5372 | return FALSE; |
a1d78564 RS |
5373 | |
5374 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5375 | return TRUE; |
a1d78564 RS |
5376 | } |
5377 | ||
364215c8 RS |
5378 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5379 | ||
a92713e6 | 5380 | static unsigned int |
364215c8 | 5381 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5382 | const struct mips_operand *operand) |
364215c8 RS |
5383 | { |
5384 | unsigned int mask; | |
5385 | bfd_boolean is_exit; | |
5386 | ||
5387 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5388 | are different. */ | |
5389 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5390 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5391 | do |
364215c8 RS |
5392 | { |
5393 | unsigned int regno1, regno2; | |
5394 | bfd_boolean is_freg; | |
5395 | ||
a92713e6 | 5396 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5397 | is_freg = FALSE; |
a92713e6 | 5398 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5399 | is_freg = TRUE; |
5400 | else | |
a92713e6 | 5401 | return FALSE; |
364215c8 RS |
5402 | |
5403 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5404 | { | |
5405 | mask &= ~(7 << 3); | |
5406 | mask |= (5 + regno2) << 3; | |
5407 | } | |
5408 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5409 | mask |= (regno2 - 3) << 3; | |
5410 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5411 | mask |= (regno2 - 15) << 1; | |
5412 | else if (regno1 == RA && regno2 == RA) | |
5413 | mask |= 1; | |
5414 | else | |
a92713e6 | 5415 | return FALSE; |
364215c8 | 5416 | } |
a92713e6 RS |
5417 | while (match_char (arg, ',')); |
5418 | ||
364215c8 | 5419 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5420 | return TRUE; |
364215c8 RS |
5421 | } |
5422 | ||
5423 | /* OP_SAVE_RESTORE_LIST matcher. */ | |
5424 | ||
a92713e6 RS |
5425 | static bfd_boolean |
5426 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5427 | { |
5428 | unsigned int opcode, args, statics, sregs; | |
5429 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
364215c8 | 5430 | offsetT frame_size; |
364215c8 | 5431 | |
364215c8 RS |
5432 | opcode = arg->insn->insn_opcode; |
5433 | frame_size = 0; | |
5434 | num_frame_sizes = 0; | |
5435 | args = 0; | |
5436 | statics = 0; | |
5437 | sregs = 0; | |
a92713e6 | 5438 | do |
364215c8 RS |
5439 | { |
5440 | unsigned int regno1, regno2; | |
5441 | ||
a92713e6 | 5442 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5443 | { |
5444 | /* Handle the frame size. */ | |
1a00e612 | 5445 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5446 | return FALSE; |
364215c8 | 5447 | num_frame_sizes += 1; |
364215c8 RS |
5448 | } |
5449 | else | |
5450 | { | |
a92713e6 RS |
5451 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5452 | return FALSE; | |
364215c8 RS |
5453 | |
5454 | while (regno1 <= regno2) | |
5455 | { | |
5456 | if (regno1 >= 4 && regno1 <= 7) | |
5457 | { | |
5458 | if (num_frame_sizes == 0) | |
5459 | /* args $a0-$a3 */ | |
5460 | args |= 1 << (regno1 - 4); | |
5461 | else | |
5462 | /* statics $a0-$a3 */ | |
5463 | statics |= 1 << (regno1 - 4); | |
5464 | } | |
5465 | else if (regno1 >= 16 && regno1 <= 23) | |
5466 | /* $s0-$s7 */ | |
5467 | sregs |= 1 << (regno1 - 16); | |
5468 | else if (regno1 == 30) | |
5469 | /* $s8 */ | |
5470 | sregs |= 1 << 8; | |
5471 | else if (regno1 == 31) | |
5472 | /* Add $ra to insn. */ | |
5473 | opcode |= 0x40; | |
5474 | else | |
a92713e6 | 5475 | return FALSE; |
364215c8 RS |
5476 | regno1 += 1; |
5477 | if (regno1 == 24) | |
5478 | regno1 = 30; | |
5479 | } | |
5480 | } | |
364215c8 | 5481 | } |
a92713e6 | 5482 | while (match_char (arg, ',')); |
364215c8 RS |
5483 | |
5484 | /* Encode args/statics combination. */ | |
5485 | if (args & statics) | |
a92713e6 | 5486 | return FALSE; |
364215c8 RS |
5487 | else if (args == 0xf) |
5488 | /* All $a0-$a3 are args. */ | |
5489 | opcode |= MIPS16_ALL_ARGS << 16; | |
5490 | else if (statics == 0xf) | |
5491 | /* All $a0-$a3 are statics. */ | |
5492 | opcode |= MIPS16_ALL_STATICS << 16; | |
5493 | else | |
5494 | { | |
5495 | /* Count arg registers. */ | |
5496 | num_args = 0; | |
5497 | while (args & 0x1) | |
5498 | { | |
5499 | args >>= 1; | |
5500 | num_args += 1; | |
5501 | } | |
5502 | if (args != 0) | |
a92713e6 | 5503 | return FALSE; |
364215c8 RS |
5504 | |
5505 | /* Count static registers. */ | |
5506 | num_statics = 0; | |
5507 | while (statics & 0x8) | |
5508 | { | |
5509 | statics = (statics << 1) & 0xf; | |
5510 | num_statics += 1; | |
5511 | } | |
5512 | if (statics != 0) | |
a92713e6 | 5513 | return FALSE; |
364215c8 RS |
5514 | |
5515 | /* Encode args/statics. */ | |
5516 | opcode |= ((num_args << 2) | num_statics) << 16; | |
5517 | } | |
5518 | ||
5519 | /* Encode $s0/$s1. */ | |
5520 | if (sregs & (1 << 0)) /* $s0 */ | |
5521 | opcode |= 0x20; | |
5522 | if (sregs & (1 << 1)) /* $s1 */ | |
5523 | opcode |= 0x10; | |
5524 | sregs >>= 2; | |
5525 | ||
5526 | /* Encode $s2-$s8. */ | |
5527 | num_sregs = 0; | |
5528 | while (sregs & 1) | |
5529 | { | |
5530 | sregs >>= 1; | |
5531 | num_sregs += 1; | |
5532 | } | |
5533 | if (sregs != 0) | |
a92713e6 | 5534 | return FALSE; |
364215c8 RS |
5535 | opcode |= num_sregs << 24; |
5536 | ||
5537 | /* Encode frame size. */ | |
5538 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5539 | { |
5540 | set_insn_error (arg->argnum, _("missing frame size")); | |
5541 | return FALSE; | |
5542 | } | |
5543 | if (num_frame_sizes > 1) | |
5544 | { | |
5545 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5546 | return FALSE; | |
5547 | } | |
5548 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5549 | { | |
5550 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5551 | return FALSE; | |
5552 | } | |
5553 | if (frame_size != 128 || (opcode >> 16) != 0) | |
364215c8 RS |
5554 | { |
5555 | frame_size /= 8; | |
5556 | opcode |= (((frame_size & 0xf0) << 16) | |
5557 | | (frame_size & 0x0f)); | |
5558 | } | |
5559 | ||
364215c8 RS |
5560 | /* Finally build the instruction. */ |
5561 | if ((opcode >> 16) != 0 || frame_size == 0) | |
5562 | opcode |= MIPS16_EXTEND; | |
5563 | arg->insn->insn_opcode = opcode; | |
a92713e6 | 5564 | return TRUE; |
364215c8 RS |
5565 | } |
5566 | ||
a1d78564 RS |
5567 | /* OP_MDMX_IMM_REG matcher. */ |
5568 | ||
a92713e6 | 5569 | static bfd_boolean |
a1d78564 | 5570 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5571 | const struct mips_operand *operand) |
a1d78564 | 5572 | { |
a92713e6 | 5573 | unsigned int regno, uval; |
a1d78564 RS |
5574 | bfd_boolean is_qh; |
5575 | const struct mips_opcode *opcode; | |
5576 | ||
5577 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5578 | instruction. Start out with that bit in place. */ | |
5579 | opcode = arg->insn->insn_mo; | |
5580 | uval = mips_extract_operand (operand, opcode->match); | |
5581 | is_qh = (uval != 0); | |
5582 | ||
56d438b1 | 5583 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5584 | { |
5585 | if ((opcode->membership & INSN_5400) | |
5586 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5587 | { | |
1a00e612 RS |
5588 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5589 | arg->argnum); | |
5590 | return FALSE; | |
a1d78564 RS |
5591 | } |
5592 | ||
56d438b1 CF |
5593 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5594 | return FALSE; | |
5595 | ++arg->token; | |
5596 | ||
a1d78564 RS |
5597 | /* Check whether this is a vector register or a broadcast of |
5598 | a single element. */ | |
56d438b1 | 5599 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5600 | { |
56d438b1 | 5601 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5602 | { |
1a00e612 RS |
5603 | set_insn_error (arg->argnum, _("invalid element selector")); |
5604 | return FALSE; | |
a1d78564 | 5605 | } |
56d438b1 CF |
5606 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5607 | ++arg->token; | |
a1d78564 RS |
5608 | } |
5609 | else | |
5610 | { | |
5611 | /* A full vector. */ | |
5612 | if ((opcode->membership & INSN_5400) | |
5613 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5614 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5615 | { | |
1a00e612 RS |
5616 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5617 | arg->argnum); | |
5618 | return FALSE; | |
a1d78564 RS |
5619 | } |
5620 | ||
5621 | if (is_qh) | |
5622 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5623 | else | |
5624 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5625 | } | |
a1d78564 RS |
5626 | uval |= regno; |
5627 | } | |
5628 | else | |
5629 | { | |
5630 | offsetT sval; | |
5631 | ||
1a00e612 | 5632 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5633 | return FALSE; |
a1d78564 RS |
5634 | if (sval < 0 || sval > 31) |
5635 | { | |
1a00e612 RS |
5636 | match_out_of_range (arg); |
5637 | return FALSE; | |
a1d78564 RS |
5638 | } |
5639 | uval |= (sval & 31); | |
5640 | if (is_qh) | |
5641 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5642 | else | |
5643 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5644 | } | |
5645 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5646 | return TRUE; |
a1d78564 RS |
5647 | } |
5648 | ||
56d438b1 CF |
5649 | /* OP_IMM_INDEX matcher. */ |
5650 | ||
5651 | static bfd_boolean | |
5652 | match_imm_index_operand (struct mips_arg_info *arg, | |
5653 | const struct mips_operand *operand) | |
5654 | { | |
5655 | unsigned int max_val; | |
5656 | ||
5657 | if (arg->token->type != OT_INTEGER_INDEX) | |
5658 | return FALSE; | |
5659 | ||
5660 | max_val = (1 << operand->size) - 1; | |
5661 | if (arg->token->u.index > max_val) | |
5662 | { | |
5663 | match_out_of_range (arg); | |
5664 | return FALSE; | |
5665 | } | |
5666 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5667 | ++arg->token; | |
5668 | return TRUE; | |
5669 | } | |
5670 | ||
5671 | /* OP_REG_INDEX matcher. */ | |
5672 | ||
5673 | static bfd_boolean | |
5674 | match_reg_index_operand (struct mips_arg_info *arg, | |
5675 | const struct mips_operand *operand) | |
5676 | { | |
5677 | unsigned int regno; | |
5678 | ||
5679 | if (arg->token->type != OT_REG_INDEX) | |
5680 | return FALSE; | |
5681 | ||
5682 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5683 | return FALSE; | |
5684 | ||
5685 | insn_insert_operand (arg->insn, operand, regno); | |
5686 | ++arg->token; | |
5687 | return TRUE; | |
5688 | } | |
5689 | ||
a1d78564 RS |
5690 | /* OP_PC matcher. */ |
5691 | ||
a92713e6 RS |
5692 | static bfd_boolean |
5693 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5694 | { |
a92713e6 RS |
5695 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5696 | { | |
5697 | ++arg->token; | |
5698 | return TRUE; | |
5699 | } | |
5700 | return FALSE; | |
a1d78564 RS |
5701 | } |
5702 | ||
7361da2c AB |
5703 | /* OP_NON_ZERO_REG matcher. */ |
5704 | ||
5705 | static bfd_boolean | |
5706 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5707 | const struct mips_operand *operand) | |
5708 | { | |
5709 | unsigned int regno; | |
5710 | ||
5711 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5712 | return FALSE; | |
5713 | ||
5714 | if (regno == 0) | |
5715 | return FALSE; | |
5716 | ||
5717 | arg->last_regno = regno; | |
5718 | insn_insert_operand (arg->insn, operand, regno); | |
5719 | return TRUE; | |
5720 | } | |
5721 | ||
a1d78564 RS |
5722 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5723 | register that we need to match. */ | |
5724 | ||
a92713e6 RS |
5725 | static bfd_boolean |
5726 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5727 | { |
5728 | unsigned int regno; | |
5729 | ||
a92713e6 | 5730 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5731 | } |
5732 | ||
89565f1b RS |
5733 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
5734 | the length of the value in bytes (4 for float, 8 for double) and | |
5735 | USING_GPRS says whether the destination is a GPR rather than an FPR. | |
5736 | ||
5737 | Return the constant in IMM and OFFSET as follows: | |
5738 | ||
5739 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5740 | OFFSET to the memory address. | |
5741 | ||
5742 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5743 | set IMM to the O_constant to load into the high register and OFFSET | |
5744 | to the corresponding value for the low register. | |
5745 | ||
5746 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5747 | ||
5748 | These constants only appear as the last operand in an instruction, | |
5749 | and every instruction that accepts them in any variant accepts them | |
5750 | in all variants. This means we don't have to worry about backing out | |
5751 | any changes if the instruction does not match. We just match | |
5752 | unconditionally and report an error if the constant is invalid. */ | |
5753 | ||
a92713e6 RS |
5754 | static bfd_boolean |
5755 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5756 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5757 | { |
a92713e6 | 5758 | char *p; |
89565f1b RS |
5759 | segT seg, new_seg; |
5760 | subsegT subseg; | |
5761 | const char *newname; | |
a92713e6 | 5762 | unsigned char *data; |
89565f1b RS |
5763 | |
5764 | /* Where the constant is placed is based on how the MIPS assembler | |
5765 | does things: | |
5766 | ||
5767 | length == 4 && using_gprs -- immediate value only | |
5768 | length == 8 && using_gprs -- .rdata or immediate value | |
5769 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5770 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5771 | ||
5772 | The .lit4 and .lit8 sections are only used if permitted by the | |
5773 | -G argument. */ | |
a92713e6 | 5774 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5775 | { |
5776 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5777 | return FALSE; | |
5778 | } | |
a92713e6 RS |
5779 | |
5780 | gas_assert (arg->token->u.flt.length == length); | |
5781 | data = arg->token->u.flt.data; | |
5782 | ++arg->token; | |
89565f1b RS |
5783 | |
5784 | /* Handle 32-bit constants for which an immediate value is best. */ | |
5785 | if (length == 4 | |
5786 | && (using_gprs | |
5787 | || g_switch_value < 4 | |
5788 | || (data[0] == 0 && data[1] == 0) | |
5789 | || (data[2] == 0 && data[3] == 0))) | |
5790 | { | |
5791 | imm->X_op = O_constant; | |
5792 | if (!target_big_endian) | |
5793 | imm->X_add_number = bfd_getl32 (data); | |
5794 | else | |
5795 | imm->X_add_number = bfd_getb32 (data); | |
5796 | offset->X_op = O_absent; | |
a92713e6 | 5797 | return TRUE; |
89565f1b RS |
5798 | } |
5799 | ||
5800 | /* Handle 64-bit constants for which an immediate value is best. */ | |
5801 | if (length == 8 | |
5802 | && !mips_disable_float_construction | |
351cdf24 MF |
5803 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
5804 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
5805 | Unlike most tests for 32-bit floating-point registers this check | |
5806 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
5807 | permit 64-bit moves without MXHC1. | |
5808 | Force the constant into memory otherwise. */ | |
5809 | && (using_gprs | |
5810 | || GPR_SIZE == 64 | |
5811 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
5812 | || FPR_SIZE == 32) | |
89565f1b RS |
5813 | && ((data[0] == 0 && data[1] == 0) |
5814 | || (data[2] == 0 && data[3] == 0)) | |
5815 | && ((data[4] == 0 && data[5] == 0) | |
5816 | || (data[6] == 0 && data[7] == 0))) | |
5817 | { | |
5818 | /* The value is simple enough to load with a couple of instructions. | |
5819 | If using 32-bit registers, set IMM to the high order 32 bits and | |
5820 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
5821 | 64 bit constant. */ | |
351cdf24 | 5822 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
5823 | { |
5824 | imm->X_op = O_constant; | |
5825 | offset->X_op = O_constant; | |
5826 | if (!target_big_endian) | |
5827 | { | |
5828 | imm->X_add_number = bfd_getl32 (data + 4); | |
5829 | offset->X_add_number = bfd_getl32 (data); | |
5830 | } | |
5831 | else | |
5832 | { | |
5833 | imm->X_add_number = bfd_getb32 (data); | |
5834 | offset->X_add_number = bfd_getb32 (data + 4); | |
5835 | } | |
5836 | if (offset->X_add_number == 0) | |
5837 | offset->X_op = O_absent; | |
5838 | } | |
5839 | else | |
5840 | { | |
5841 | imm->X_op = O_constant; | |
5842 | if (!target_big_endian) | |
5843 | imm->X_add_number = bfd_getl64 (data); | |
5844 | else | |
5845 | imm->X_add_number = bfd_getb64 (data); | |
5846 | offset->X_op = O_absent; | |
5847 | } | |
a92713e6 | 5848 | return TRUE; |
89565f1b RS |
5849 | } |
5850 | ||
5851 | /* Switch to the right section. */ | |
5852 | seg = now_seg; | |
5853 | subseg = now_subseg; | |
5854 | if (length == 4) | |
5855 | { | |
5856 | gas_assert (!using_gprs && g_switch_value >= 4); | |
5857 | newname = ".lit4"; | |
5858 | } | |
5859 | else | |
5860 | { | |
5861 | if (using_gprs || g_switch_value < 8) | |
5862 | newname = RDATA_SECTION_NAME; | |
5863 | else | |
5864 | newname = ".lit8"; | |
5865 | } | |
5866 | ||
5867 | new_seg = subseg_new (newname, (subsegT) 0); | |
5868 | bfd_set_section_flags (stdoutput, new_seg, | |
5869 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
5870 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
5871 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
5872 | record_alignment (new_seg, 4); | |
5873 | else | |
5874 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
5875 | if (seg == now_seg) | |
1661c76c | 5876 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
5877 | |
5878 | /* Set the argument to the current address in the section. */ | |
5879 | imm->X_op = O_absent; | |
5880 | offset->X_op = O_symbol; | |
5881 | offset->X_add_symbol = symbol_temp_new_now (); | |
5882 | offset->X_add_number = 0; | |
5883 | ||
5884 | /* Put the floating point number into the section. */ | |
5885 | p = frag_more (length); | |
5886 | memcpy (p, data, length); | |
5887 | ||
5888 | /* Switch back to the original section. */ | |
5889 | subseg_set (seg, subseg); | |
a92713e6 | 5890 | return TRUE; |
89565f1b RS |
5891 | } |
5892 | ||
14daeee3 RS |
5893 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
5894 | them. */ | |
5895 | ||
5896 | static bfd_boolean | |
5897 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
5898 | const struct mips_operand *operand, | |
5899 | bfd_boolean match_p) | |
5900 | { | |
5901 | unsigned int uval; | |
5902 | ||
5903 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
5904 | (with X being 0). */ | |
5905 | gas_assert (operand->size == 2 || operand->size == 4); | |
5906 | ||
ee5734f0 | 5907 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 5908 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 5909 | return match_p; |
14daeee3 RS |
5910 | |
5911 | uval = arg->token->u.channels; | |
5912 | if (operand->size == 2) | |
5913 | { | |
5914 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
5915 | if ((uval & -uval) != uval) | |
5916 | return FALSE; | |
5917 | uval = 4 - ffs (uval); | |
5918 | } | |
5919 | ||
5920 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
5921 | return FALSE; | |
5922 | ||
5923 | ++arg->token; | |
5924 | if (!match_p) | |
5925 | insn_insert_operand (arg->insn, operand, uval); | |
5926 | return TRUE; | |
5927 | } | |
5928 | ||
a1d78564 RS |
5929 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
5930 | of the argument text if the match is successful, otherwise return null. */ | |
5931 | ||
a92713e6 | 5932 | static bfd_boolean |
a1d78564 | 5933 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 5934 | const struct mips_operand *operand) |
a1d78564 RS |
5935 | { |
5936 | switch (operand->type) | |
5937 | { | |
5938 | case OP_INT: | |
a92713e6 | 5939 | return match_int_operand (arg, operand); |
a1d78564 RS |
5940 | |
5941 | case OP_MAPPED_INT: | |
a92713e6 | 5942 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
5943 | |
5944 | case OP_MSB: | |
a92713e6 | 5945 | return match_msb_operand (arg, operand); |
a1d78564 RS |
5946 | |
5947 | case OP_REG: | |
0f35dbc4 | 5948 | case OP_OPTIONAL_REG: |
a92713e6 | 5949 | return match_reg_operand (arg, operand); |
a1d78564 RS |
5950 | |
5951 | case OP_REG_PAIR: | |
a92713e6 | 5952 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
5953 | |
5954 | case OP_PCREL: | |
a92713e6 | 5955 | return match_pcrel_operand (arg); |
a1d78564 RS |
5956 | |
5957 | case OP_PERF_REG: | |
a92713e6 | 5958 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
5959 | |
5960 | case OP_ADDIUSP_INT: | |
a92713e6 | 5961 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
5962 | |
5963 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 5964 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
5965 | |
5966 | case OP_LWM_SWM_LIST: | |
a92713e6 | 5967 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
5968 | |
5969 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 5970 | return match_entry_exit_operand (arg, operand); |
364215c8 | 5971 | |
a1d78564 | 5972 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 5973 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
5974 | |
5975 | case OP_MDMX_IMM_REG: | |
a92713e6 | 5976 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
5977 | |
5978 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 5979 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
5980 | |
5981 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 5982 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
5983 | |
5984 | case OP_PC: | |
a92713e6 | 5985 | return match_pc_operand (arg); |
14daeee3 RS |
5986 | |
5987 | case OP_VU0_SUFFIX: | |
5988 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
5989 | ||
5990 | case OP_VU0_MATCH_SUFFIX: | |
5991 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
5992 | |
5993 | case OP_IMM_INDEX: | |
5994 | return match_imm_index_operand (arg, operand); | |
5995 | ||
5996 | case OP_REG_INDEX: | |
5997 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
5998 | |
5999 | case OP_SAME_RS_RT: | |
6000 | return match_same_rs_rt_operand (arg, operand); | |
6001 | ||
6002 | case OP_CHECK_PREV: | |
6003 | return match_check_prev_operand (arg, operand); | |
6004 | ||
6005 | case OP_NON_ZERO_REG: | |
6006 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6007 | } |
6008 | abort (); | |
6009 | } | |
6010 | ||
6011 | /* ARG is the state after successfully matching an instruction. | |
6012 | Issue any queued-up warnings. */ | |
6013 | ||
6014 | static void | |
6015 | check_completed_insn (struct mips_arg_info *arg) | |
6016 | { | |
6017 | if (arg->seen_at) | |
6018 | { | |
6019 | if (AT == ATREG) | |
1661c76c | 6020 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6021 | else |
1661c76c | 6022 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6023 | } |
6024 | } | |
a1d78564 | 6025 | |
85fcb30f RS |
6026 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6027 | ||
6028 | static bfd_boolean | |
6029 | reg_needs_delay (unsigned int reg) | |
6030 | { | |
6031 | unsigned long prev_pinfo; | |
6032 | ||
6033 | prev_pinfo = history[0].insn_mo->pinfo; | |
6034 | if (!mips_opts.noreorder | |
67dc82bc | 6035 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6036 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6037 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6038 | return TRUE; | |
6039 | ||
6040 | return FALSE; | |
6041 | } | |
6042 | ||
71400594 RS |
6043 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6044 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6045 | by VR4120 errata. */ | |
4d7206a2 | 6046 | |
71400594 RS |
6047 | static unsigned int |
6048 | classify_vr4120_insn (const char *name) | |
252b5132 | 6049 | { |
71400594 RS |
6050 | if (strncmp (name, "macc", 4) == 0) |
6051 | return FIX_VR4120_MACC; | |
6052 | if (strncmp (name, "dmacc", 5) == 0) | |
6053 | return FIX_VR4120_DMACC; | |
6054 | if (strncmp (name, "mult", 4) == 0) | |
6055 | return FIX_VR4120_MULT; | |
6056 | if (strncmp (name, "dmult", 5) == 0) | |
6057 | return FIX_VR4120_DMULT; | |
6058 | if (strstr (name, "div")) | |
6059 | return FIX_VR4120_DIV; | |
6060 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6061 | return FIX_VR4120_MTHILO; | |
6062 | return NUM_FIX_VR4120_CLASSES; | |
6063 | } | |
252b5132 | 6064 | |
a8d14a88 CM |
6065 | #define INSN_ERET 0x42000018 |
6066 | #define INSN_DERET 0x4200001f | |
6067 | #define INSN_DMULT 0x1c | |
6068 | #define INSN_DMULTU 0x1d | |
ff239038 | 6069 | |
71400594 RS |
6070 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6071 | where INSN1 is the earlier instruction. Return the worst-case value | |
6072 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6073 | |
71400594 RS |
6074 | static unsigned int |
6075 | insns_between (const struct mips_cl_insn *insn1, | |
6076 | const struct mips_cl_insn *insn2) | |
6077 | { | |
6078 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6079 | unsigned int mask; |
71400594 | 6080 | |
85fcb30f RS |
6081 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6082 | the second instruction. */ | |
71400594 RS |
6083 | pinfo1 = insn1->insn_mo->pinfo; |
6084 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6085 | |
71400594 RS |
6086 | /* For most targets, write-after-read dependencies on the HI and LO |
6087 | registers must be separated by at least two instructions. */ | |
6088 | if (!hilo_interlocks) | |
252b5132 | 6089 | { |
71400594 RS |
6090 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6091 | return 2; | |
6092 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6093 | return 2; | |
6094 | } | |
6095 | ||
6096 | /* If we're working around r7000 errata, there must be two instructions | |
6097 | between an mfhi or mflo and any instruction that uses the result. */ | |
6098 | if (mips_7000_hilo_fix | |
df58fc94 | 6099 | && !mips_opts.micromips |
71400594 | 6100 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6101 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6102 | return 2; |
6103 | ||
ff239038 CM |
6104 | /* If we're working around 24K errata, one instruction is required |
6105 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6106 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6107 | { |
6108 | if (insn1->insn_opcode == INSN_ERET | |
6109 | || insn1->insn_opcode == INSN_DERET) | |
6110 | { | |
6111 | if (insn2 == NULL | |
6112 | || insn2->insn_opcode == INSN_ERET | |
6113 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6114 | || delayed_branch_p (insn2)) |
ff239038 CM |
6115 | return 1; |
6116 | } | |
6117 | } | |
6118 | ||
a8d14a88 CM |
6119 | /* If we're working around PMC RM7000 errata, there must be three |
6120 | nops between a dmult and a load instruction. */ | |
6121 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6122 | { | |
6123 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6124 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6125 | { | |
6126 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6127 | return 3; | |
6128 | } | |
6129 | } | |
6130 | ||
71400594 RS |
6131 | /* If working around VR4120 errata, check for combinations that need |
6132 | a single intervening instruction. */ | |
df58fc94 | 6133 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6134 | { |
6135 | unsigned int class1, class2; | |
252b5132 | 6136 | |
71400594 RS |
6137 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6138 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6139 | { |
71400594 RS |
6140 | if (insn2 == NULL) |
6141 | return 1; | |
6142 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6143 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6144 | return 1; | |
252b5132 | 6145 | } |
71400594 RS |
6146 | } |
6147 | ||
df58fc94 | 6148 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6149 | { |
6150 | /* Check for GPR or coprocessor load delays. All such delays | |
6151 | are on the RT register. */ | |
6152 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6153 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6154 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6155 | { |
85fcb30f | 6156 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6157 | return 1; |
6158 | } | |
6159 | ||
6160 | /* Check for generic coprocessor hazards. | |
6161 | ||
6162 | This case is not handled very well. There is no special | |
6163 | knowledge of CP0 handling, and the coprocessors other than | |
6164 | the floating point unit are not distinguished at all. */ | |
6165 | /* Itbl support may require additional care here. FIXME! | |
6166 | Need to modify this to include knowledge about | |
6167 | user specified delays! */ | |
43885403 | 6168 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6169 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6170 | { | |
6171 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6172 | register. There must be a one instruction delay before INSN2 | |
6173 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6174 | mask = fpr_write_mask (insn1); |
6175 | if (mask != 0) | |
252b5132 | 6176 | { |
4c260379 | 6177 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6178 | return 1; |
252b5132 RH |
6179 | } |
6180 | else | |
6181 | { | |
71400594 RS |
6182 | /* Read-after-write dependencies on the control registers |
6183 | require a two-instruction gap. */ | |
6184 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6185 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6186 | return 2; | |
6187 | ||
6188 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6189 | also a coprocessor instruction, assume there must be | |
6190 | a one instruction gap. */ | |
6191 | if (pinfo2 & INSN_COP) | |
6192 | return 1; | |
252b5132 RH |
6193 | } |
6194 | } | |
6b76fefe | 6195 | |
71400594 RS |
6196 | /* Check for read-after-write dependencies on the coprocessor |
6197 | control registers in cases where INSN1 does not need a general | |
6198 | coprocessor delay. This means that INSN1 is a floating point | |
6199 | comparison instruction. */ | |
6200 | /* Itbl support may require additional care here. */ | |
6201 | else if (!cop_interlocks | |
6202 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6203 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6204 | return 1; | |
6205 | } | |
6b76fefe | 6206 | |
7361da2c AB |
6207 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6208 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6209 | and pause. */ | |
6210 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6211 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6212 | || (insn2 && delayed_branch_p (insn2)))) | |
6213 | return 1; | |
6214 | ||
71400594 RS |
6215 | return 0; |
6216 | } | |
6b76fefe | 6217 | |
7d8e00cf RS |
6218 | /* Return the number of nops that would be needed to work around the |
6219 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6220 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6221 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6222 | |
6223 | static int | |
932d1a1b | 6224 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6225 | const struct mips_cl_insn *insn) |
6226 | { | |
4c260379 RS |
6227 | int i, j; |
6228 | unsigned int mask; | |
7d8e00cf RS |
6229 | |
6230 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6231 | are not affected by the errata. */ | |
6232 | if (insn != 0 | |
6233 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6234 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6235 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6236 | return 0; | |
6237 | ||
6238 | /* Search for the first MFLO or MFHI. */ | |
6239 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6240 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6241 | { |
6242 | /* Extract the destination register. */ | |
4c260379 | 6243 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6244 | |
6245 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6246 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6247 | return 0; |
6248 | ||
6249 | /* ...or if any of the intervening instructions do. */ | |
6250 | for (j = 0; j < i; j++) | |
4c260379 | 6251 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6252 | return 0; |
6253 | ||
932d1a1b RS |
6254 | if (i >= ignore) |
6255 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6256 | } |
6257 | return 0; | |
6258 | } | |
6259 | ||
15be625d CM |
6260 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6261 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
6262 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
6263 | ||
6264 | /* Return the minimum alignment for this store instruction. */ | |
6265 | ||
6266 | static int | |
6267 | fix_24k_align_to (const struct mips_opcode *mo) | |
6268 | { | |
6269 | if (strcmp (mo->name, "sh") == 0) | |
6270 | return 2; | |
6271 | ||
6272 | if (strcmp (mo->name, "swc1") == 0 | |
6273 | || strcmp (mo->name, "swc2") == 0 | |
6274 | || strcmp (mo->name, "sw") == 0 | |
6275 | || strcmp (mo->name, "sc") == 0 | |
6276 | || strcmp (mo->name, "s.s") == 0) | |
6277 | return 4; | |
6278 | ||
6279 | if (strcmp (mo->name, "sdc1") == 0 | |
6280 | || strcmp (mo->name, "sdc2") == 0 | |
6281 | || strcmp (mo->name, "s.d") == 0) | |
6282 | return 8; | |
6283 | ||
6284 | /* sb, swl, swr */ | |
6285 | return 1; | |
6286 | } | |
6287 | ||
6288 | struct fix_24k_store_info | |
6289 | { | |
6290 | /* Immediate offset, if any, for this store instruction. */ | |
6291 | short off; | |
6292 | /* Alignment required by this store instruction. */ | |
6293 | int align_to; | |
6294 | /* True for register offsets. */ | |
6295 | int register_offset; | |
6296 | }; | |
6297 | ||
6298 | /* Comparison function used by qsort. */ | |
6299 | ||
6300 | static int | |
6301 | fix_24k_sort (const void *a, const void *b) | |
6302 | { | |
6303 | const struct fix_24k_store_info *pos1 = a; | |
6304 | const struct fix_24k_store_info *pos2 = b; | |
6305 | ||
6306 | return (pos1->off - pos2->off); | |
6307 | } | |
6308 | ||
6309 | /* INSN is a store instruction. Try to record the store information | |
6310 | in STINFO. Return false if the information isn't known. */ | |
6311 | ||
6312 | static bfd_boolean | |
6313 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6314 | const struct mips_cl_insn *insn) |
15be625d CM |
6315 | { |
6316 | /* The instruction must have a known offset. */ | |
6317 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6318 | return FALSE; | |
6319 | ||
6320 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6321 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6322 | return TRUE; | |
6323 | } | |
6324 | ||
932d1a1b RS |
6325 | /* Return the number of nops that would be needed to work around the 24k |
6326 | "lost data on stores during refill" errata if instruction INSN | |
6327 | immediately followed the 2 instructions described by HIST. | |
6328 | Ignore hazards that are contained within the first IGNORE | |
6329 | instructions of HIST. | |
6330 | ||
6331 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6332 | for the data cache refills and store data. The following describes | |
6333 | the scenario where the store data could be lost. | |
6334 | ||
6335 | * A data cache miss, due to either a load or a store, causing fill | |
6336 | data to be supplied by the memory subsystem | |
6337 | * The first three doublewords of fill data are returned and written | |
6338 | into the cache | |
6339 | * A sequence of four stores occurs in consecutive cycles around the | |
6340 | final doubleword of the fill: | |
6341 | * Store A | |
6342 | * Store B | |
6343 | * Store C | |
6344 | * Zero, One or more instructions | |
6345 | * Store D | |
6346 | ||
6347 | The four stores A-D must be to different doublewords of the line that | |
6348 | is being filled. The fourth instruction in the sequence above permits | |
6349 | the fill of the final doubleword to be transferred from the FSB into | |
6350 | the cache. In the sequence above, the stores may be either integer | |
6351 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6352 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6353 | different doublewords on the line. If the floating point unit is | |
6354 | running in 1:2 mode, it is not possible to create the sequence above | |
6355 | using only floating point store instructions. | |
15be625d CM |
6356 | |
6357 | In this case, the cache line being filled is incorrectly marked | |
6358 | invalid, thereby losing the data from any store to the line that | |
6359 | occurs between the original miss and the completion of the five | |
6360 | cycle sequence shown above. | |
6361 | ||
932d1a1b | 6362 | The workarounds are: |
15be625d | 6363 | |
932d1a1b RS |
6364 | * Run the data cache in write-through mode. |
6365 | * Insert a non-store instruction between | |
6366 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6367 | |
15be625d | 6368 | static int |
932d1a1b | 6369 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6370 | const struct mips_cl_insn *insn) |
6371 | { | |
6372 | struct fix_24k_store_info pos[3]; | |
6373 | int align, i, base_offset; | |
6374 | ||
932d1a1b RS |
6375 | if (ignore >= 2) |
6376 | return 0; | |
6377 | ||
ab9794cf RS |
6378 | /* If the previous instruction wasn't a store, there's nothing to |
6379 | worry about. */ | |
15be625d CM |
6380 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6381 | return 0; | |
6382 | ||
ab9794cf RS |
6383 | /* If the instructions after the previous one are unknown, we have |
6384 | to assume the worst. */ | |
6385 | if (!insn) | |
15be625d CM |
6386 | return 1; |
6387 | ||
ab9794cf RS |
6388 | /* Check whether we are dealing with three consecutive stores. */ |
6389 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6390 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6391 | return 0; |
6392 | ||
6393 | /* If we don't know the relationship between the store addresses, | |
6394 | assume the worst. */ | |
ab9794cf | 6395 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6396 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6397 | return 1; | |
6398 | ||
6399 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6400 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6401 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6402 | return 1; | |
6403 | ||
6404 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6405 | ||
6406 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6407 | X bytes and such that the base register + X is known to be aligned | |
6408 | to align bytes. */ | |
6409 | ||
6410 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6411 | align = 8; | |
6412 | else | |
6413 | { | |
6414 | align = pos[0].align_to; | |
6415 | base_offset = pos[0].off; | |
6416 | for (i = 1; i < 3; i++) | |
6417 | if (align < pos[i].align_to) | |
6418 | { | |
6419 | align = pos[i].align_to; | |
6420 | base_offset = pos[i].off; | |
6421 | } | |
6422 | for (i = 0; i < 3; i++) | |
6423 | pos[i].off -= base_offset; | |
6424 | } | |
6425 | ||
6426 | pos[0].off &= ~align + 1; | |
6427 | pos[1].off &= ~align + 1; | |
6428 | pos[2].off &= ~align + 1; | |
6429 | ||
6430 | /* If any two stores write to the same chunk, they also write to the | |
6431 | same doubleword. The offsets are still sorted at this point. */ | |
6432 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6433 | return 0; | |
6434 | ||
6435 | /* A range of at least 9 bytes is needed for the stores to be in | |
6436 | non-overlapping doublewords. */ | |
6437 | if (pos[2].off - pos[0].off <= 8) | |
6438 | return 0; | |
6439 | ||
6440 | if (pos[2].off - pos[1].off >= 24 | |
6441 | || pos[1].off - pos[0].off >= 24 | |
6442 | || pos[2].off - pos[0].off >= 32) | |
6443 | return 0; | |
6444 | ||
6445 | return 1; | |
6446 | } | |
6447 | ||
71400594 | 6448 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6449 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6450 | where HIST[0] is the most recent instruction. Ignore hazards |
6451 | between INSN and the first IGNORE instructions in HIST. | |
6452 | ||
6453 | If INSN is null, return the worse-case number of nops for any | |
6454 | instruction. */ | |
bdaaa2e1 | 6455 | |
71400594 | 6456 | static int |
932d1a1b | 6457 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6458 | const struct mips_cl_insn *insn) |
6459 | { | |
6460 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6461 | |
71400594 | 6462 | nops = 0; |
932d1a1b | 6463 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6464 | { |
91d6fa6a | 6465 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6466 | if (tmp_nops > nops) |
6467 | nops = tmp_nops; | |
6468 | } | |
7d8e00cf | 6469 | |
df58fc94 | 6470 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6471 | { |
932d1a1b | 6472 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6473 | if (tmp_nops > nops) |
6474 | nops = tmp_nops; | |
6475 | } | |
6476 | ||
df58fc94 | 6477 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6478 | { |
932d1a1b | 6479 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6480 | if (tmp_nops > nops) |
6481 | nops = tmp_nops; | |
6482 | } | |
6483 | ||
71400594 RS |
6484 | return nops; |
6485 | } | |
252b5132 | 6486 | |
71400594 | 6487 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6488 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6489 | would be needed after the extended sequence, ignoring hazards |
6490 | in the first IGNORE instructions. */ | |
252b5132 | 6491 | |
71400594 | 6492 | static int |
932d1a1b RS |
6493 | nops_for_sequence (int num_insns, int ignore, |
6494 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6495 | { |
6496 | va_list args; | |
6497 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6498 | struct mips_cl_insn *cursor; | |
6499 | int nops; | |
6500 | ||
91d6fa6a | 6501 | va_start (args, hist); |
71400594 | 6502 | cursor = buffer + num_insns; |
91d6fa6a | 6503 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6504 | while (cursor > buffer) |
6505 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6506 | ||
932d1a1b | 6507 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6508 | va_end (args); |
6509 | return nops; | |
6510 | } | |
252b5132 | 6511 | |
71400594 RS |
6512 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6513 | worst-case delay for the branch target. */ | |
252b5132 | 6514 | |
71400594 | 6515 | static int |
932d1a1b | 6516 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6517 | const struct mips_cl_insn *insn) |
6518 | { | |
6519 | int nops, tmp_nops; | |
60b63b72 | 6520 | |
932d1a1b | 6521 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6522 | if (delayed_branch_p (insn)) |
71400594 | 6523 | { |
932d1a1b | 6524 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6525 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6526 | if (tmp_nops > nops) |
6527 | nops = tmp_nops; | |
6528 | } | |
11625dd8 | 6529 | else if (compact_branch_p (insn)) |
71400594 | 6530 | { |
932d1a1b | 6531 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6532 | if (tmp_nops > nops) |
6533 | nops = tmp_nops; | |
6534 | } | |
6535 | return nops; | |
6536 | } | |
6537 | ||
c67a084a NC |
6538 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6539 | ||
6540 | static void | |
6541 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6542 | { | |
df58fc94 | 6543 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6544 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6545 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6546 | } | |
6547 | ||
6548 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6549 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6550 | ||
6551 | static void | |
6552 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6553 | { | |
df58fc94 | 6554 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6555 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6556 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6557 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6558 | { | |
6559 | int sreg; | |
6560 | expressionS ep; | |
6561 | ||
6562 | if (! mips_opts.at) | |
6563 | return; | |
6564 | ||
df58fc94 | 6565 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6566 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6567 | return; | |
6568 | ||
6569 | ep.X_op = O_constant; | |
6570 | ep.X_add_number = 0xcfff0000; | |
6571 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6572 | ep.X_add_number = 0xffff; | |
6573 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6574 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6575 | } | |
6576 | } | |
6577 | ||
6578 | static void | |
6579 | fix_loongson2f (struct mips_cl_insn * ip) | |
6580 | { | |
6581 | if (mips_fix_loongson2f_nop) | |
6582 | fix_loongson2f_nop (ip); | |
6583 | ||
6584 | if (mips_fix_loongson2f_jump) | |
6585 | fix_loongson2f_jump (ip); | |
6586 | } | |
6587 | ||
a4e06468 RS |
6588 | /* IP is a branch that has a delay slot, and we need to fill it |
6589 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6590 | with the previous instruction. |
6591 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6592 | RELOC_TYPE. */ | |
a4e06468 RS |
6593 | |
6594 | static bfd_boolean | |
e407c74b | 6595 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6596 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6597 | { |
2b0c8b40 | 6598 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6599 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6600 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6601 | |
6602 | /* -O2 and above is required for this optimization. */ | |
6603 | if (mips_optimize < 2) | |
6604 | return FALSE; | |
6605 | ||
6606 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6607 | if (mips_opts.nomove) | |
6608 | return FALSE; | |
6609 | ||
6610 | /* We can't swap if the previous instruction's position is fixed. */ | |
6611 | if (history[0].fixed_p) | |
6612 | return FALSE; | |
6613 | ||
6614 | /* If the previous previous insn was in a .set noreorder, we can't | |
6615 | swap. Actually, the MIPS assembler will swap in this situation. | |
6616 | However, gcc configured -with-gnu-as will generate code like | |
6617 | ||
6618 | .set noreorder | |
6619 | lw $4,XXX | |
6620 | .set reorder | |
6621 | INSN | |
6622 | bne $4,$0,foo | |
6623 | ||
6624 | in which we can not swap the bne and INSN. If gcc is not configured | |
6625 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6626 | if (history[1].noreorder_p) | |
6627 | return FALSE; | |
6628 | ||
87333bb7 MR |
6629 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6630 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6631 | if (mips_opts.mips16 && history[0].fixp[0]) |
6632 | return FALSE; | |
6633 | ||
6634 | /* If the branch is itself the target of a branch, we can not swap. | |
6635 | We cheat on this; all we check for is whether there is a label on | |
6636 | this instruction. If there are any branches to anything other than | |
6637 | a label, users must use .set noreorder. */ | |
6638 | if (seg_info (now_seg)->label_list) | |
6639 | return FALSE; | |
6640 | ||
6641 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6642 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6643 | MIPS16 code, which uses variant frags for different purposes. */ |
6644 | if (!mips_opts.mips16 | |
a4e06468 RS |
6645 | && history[0].frag |
6646 | && history[0].frag->fr_type == rs_machine_dependent) | |
6647 | return FALSE; | |
6648 | ||
bcd530a7 RS |
6649 | /* We do not swap with instructions that cannot architecturally |
6650 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6651 | also refrain from swapping with a trap instruction, since it | |
6652 | complicates trap handlers to have the trap instruction be in | |
6653 | a delay slot. */ | |
a4e06468 | 6654 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6655 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6656 | return FALSE; |
6657 | ||
6658 | /* Check for conflicts between the branch and the instructions | |
6659 | before the candidate delay slot. */ | |
6660 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6661 | return FALSE; | |
6662 | ||
6663 | /* Check for conflicts between the swapped sequence and the | |
6664 | target of the branch. */ | |
6665 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6666 | return FALSE; | |
6667 | ||
6668 | /* If the branch reads a register that the previous | |
6669 | instruction sets, we can not swap. */ | |
6670 | gpr_read = gpr_read_mask (ip); | |
6671 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6672 | if (gpr_read & prev_gpr_write) | |
6673 | return FALSE; | |
6674 | ||
9d5de888 CF |
6675 | fpr_read = fpr_read_mask (ip); |
6676 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6677 | if (fpr_read & prev_fpr_write) | |
6678 | return FALSE; | |
6679 | ||
a4e06468 RS |
6680 | /* If the branch writes a register that the previous |
6681 | instruction sets, we can not swap. */ | |
6682 | gpr_write = gpr_write_mask (ip); | |
6683 | if (gpr_write & prev_gpr_write) | |
6684 | return FALSE; | |
6685 | ||
6686 | /* If the branch writes a register that the previous | |
6687 | instruction reads, we can not swap. */ | |
6688 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6689 | if (gpr_write & prev_gpr_read) | |
6690 | return FALSE; | |
6691 | ||
6692 | /* If one instruction sets a condition code and the | |
6693 | other one uses a condition code, we can not swap. */ | |
6694 | pinfo = ip->insn_mo->pinfo; | |
6695 | if ((pinfo & INSN_READ_COND_CODE) | |
6696 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6697 | return FALSE; | |
6698 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6699 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6700 | return FALSE; | |
6701 | ||
6702 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6703 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6704 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6705 | return FALSE; |
a4e06468 | 6706 | |
df58fc94 RS |
6707 | /* If the previous instruction has an incorrect size for a fixed |
6708 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6709 | pinfo2 = ip->insn_mo->pinfo2; |
6710 | if (mips_opts.micromips | |
6711 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6712 | && insn_length (history) != 2) | |
6713 | return FALSE; | |
6714 | if (mips_opts.micromips | |
6715 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6716 | && insn_length (history) != 4) | |
6717 | return FALSE; | |
6718 | ||
e407c74b NC |
6719 | /* On R5900 short loops need to be fixed by inserting a nop in |
6720 | the branch delay slots. | |
6721 | A short loop can be terminated too early. */ | |
6722 | if (mips_opts.arch == CPU_R5900 | |
6723 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6724 | && (address_expr != NULL) | |
6725 | /* Parameter must be 16 bit. */ | |
6726 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6727 | /* Branch to same segment. */ | |
6728 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
6729 | /* Branch to same code fragment. */ | |
6730 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
6731 | /* Can only calculate branch offset if value is known. */ | |
6732 | && symbol_constant_p(address_expr->X_add_symbol) | |
6733 | /* Check if branch is really conditional. */ | |
6734 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6735 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6736 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6737 | { | |
6738 | int distance; | |
6739 | /* Check if loop is shorter than 6 instructions including | |
6740 | branch and delay slot. */ | |
6741 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
6742 | if (distance <= 20) | |
6743 | { | |
6744 | int i; | |
6745 | int rv; | |
6746 | ||
6747 | rv = FALSE; | |
6748 | /* When the loop includes branches or jumps, | |
6749 | it is not a short loop. */ | |
6750 | for (i = 0; i < (distance / 4); i++) | |
6751 | { | |
6752 | if ((history[i].cleared_p) | |
6753 | || delayed_branch_p(&history[i])) | |
6754 | { | |
6755 | rv = TRUE; | |
6756 | break; | |
6757 | } | |
6758 | } | |
6759 | if (rv == FALSE) | |
6760 | { | |
6761 | /* Insert nop after branch to fix short loop. */ | |
6762 | return FALSE; | |
6763 | } | |
6764 | } | |
6765 | } | |
6766 | ||
a4e06468 RS |
6767 | return TRUE; |
6768 | } | |
6769 | ||
e407c74b NC |
6770 | /* Decide how we should add IP to the instruction stream. |
6771 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6772 | RELOC_TYPE. */ | |
a4e06468 RS |
6773 | |
6774 | static enum append_method | |
e407c74b | 6775 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6776 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6777 | { |
a4e06468 RS |
6778 | /* The relaxed version of a macro sequence must be inherently |
6779 | hazard-free. */ | |
6780 | if (mips_relax.sequence == 2) | |
6781 | return APPEND_ADD; | |
6782 | ||
6783 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
6784 | if (mips_opts.noreorder) | |
6785 | return APPEND_ADD; | |
6786 | ||
6787 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 6788 | if (delayed_branch_p (ip)) |
a4e06468 | 6789 | { |
e407c74b NC |
6790 | if (!branch_likely_p (ip) |
6791 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
6792 | return APPEND_SWAP; |
6793 | ||
6794 | if (mips_opts.mips16 | |
6795 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 6796 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
6797 | return APPEND_ADD_COMPACT; |
6798 | ||
6799 | return APPEND_ADD_WITH_NOP; | |
6800 | } | |
6801 | ||
a4e06468 RS |
6802 | return APPEND_ADD; |
6803 | } | |
6804 | ||
ceb94aa5 RS |
6805 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
6806 | Point IP->insn_mo to the new opcode's definition. */ | |
6807 | ||
6808 | static void | |
6809 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
6810 | { | |
6811 | const struct mips_opcode *mo, *end; | |
6812 | ||
6813 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
6814 | for (mo = ip->insn_mo; mo < end; mo++) | |
6815 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
6816 | { | |
6817 | ip->insn_mo = mo; | |
6818 | return; | |
6819 | } | |
6820 | abort (); | |
6821 | } | |
6822 | ||
df58fc94 RS |
6823 | /* For microMIPS macros, we need to generate a local number label |
6824 | as the target of branches. */ | |
6825 | #define MICROMIPS_LABEL_CHAR '\037' | |
6826 | static unsigned long micromips_target_label; | |
6827 | static char micromips_target_name[32]; | |
6828 | ||
6829 | static char * | |
6830 | micromips_label_name (void) | |
6831 | { | |
6832 | char *p = micromips_target_name; | |
6833 | char symbol_name_temporary[24]; | |
6834 | unsigned long l; | |
6835 | int i; | |
6836 | ||
6837 | if (*p) | |
6838 | return p; | |
6839 | ||
6840 | i = 0; | |
6841 | l = micromips_target_label; | |
6842 | #ifdef LOCAL_LABEL_PREFIX | |
6843 | *p++ = LOCAL_LABEL_PREFIX; | |
6844 | #endif | |
6845 | *p++ = 'L'; | |
6846 | *p++ = MICROMIPS_LABEL_CHAR; | |
6847 | do | |
6848 | { | |
6849 | symbol_name_temporary[i++] = l % 10 + '0'; | |
6850 | l /= 10; | |
6851 | } | |
6852 | while (l != 0); | |
6853 | while (i > 0) | |
6854 | *p++ = symbol_name_temporary[--i]; | |
6855 | *p = '\0'; | |
6856 | ||
6857 | return micromips_target_name; | |
6858 | } | |
6859 | ||
6860 | static void | |
6861 | micromips_label_expr (expressionS *label_expr) | |
6862 | { | |
6863 | label_expr->X_op = O_symbol; | |
6864 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
6865 | label_expr->X_add_number = 0; | |
6866 | } | |
6867 | ||
6868 | static void | |
6869 | micromips_label_inc (void) | |
6870 | { | |
6871 | micromips_target_label++; | |
6872 | *micromips_target_name = '\0'; | |
6873 | } | |
6874 | ||
6875 | static void | |
6876 | micromips_add_label (void) | |
6877 | { | |
6878 | symbolS *s; | |
6879 | ||
6880 | s = colon (micromips_label_name ()); | |
6881 | micromips_label_inc (); | |
f3ded42a | 6882 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
6883 | } |
6884 | ||
6885 | /* If assembling microMIPS code, then return the microMIPS reloc | |
6886 | corresponding to the requested one if any. Otherwise return | |
6887 | the reloc unchanged. */ | |
6888 | ||
6889 | static bfd_reloc_code_real_type | |
6890 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
6891 | { | |
6892 | static const bfd_reloc_code_real_type relocs[][2] = | |
6893 | { | |
6894 | /* Keep sorted incrementally by the left-hand key. */ | |
6895 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
6896 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
6897 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
6898 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
6899 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
6900 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
6901 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
6902 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
6903 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
6904 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
6905 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
6906 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
6907 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
6908 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
6909 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
6910 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
6911 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
6912 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
6913 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
6914 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
6915 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
6916 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
6917 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
6918 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
6919 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
6920 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
6921 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
6922 | }; | |
6923 | bfd_reloc_code_real_type r; | |
6924 | size_t i; | |
6925 | ||
6926 | if (!mips_opts.micromips) | |
6927 | return reloc; | |
6928 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
6929 | { | |
6930 | r = relocs[i][0]; | |
6931 | if (r > reloc) | |
6932 | return reloc; | |
6933 | if (r == reloc) | |
6934 | return relocs[i][1]; | |
6935 | } | |
6936 | return reloc; | |
6937 | } | |
6938 | ||
b886a2ab RS |
6939 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
6940 | Return true on success, storing the resolved value in RESULT. */ | |
6941 | ||
6942 | static bfd_boolean | |
6943 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
6944 | offsetT *result) | |
6945 | { | |
6946 | switch (reloc) | |
6947 | { | |
6948 | case BFD_RELOC_MIPS_HIGHEST: | |
6949 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
6950 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
6951 | return TRUE; | |
6952 | ||
6953 | case BFD_RELOC_MIPS_HIGHER: | |
6954 | case BFD_RELOC_MICROMIPS_HIGHER: | |
6955 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
6956 | return TRUE; | |
6957 | ||
6958 | case BFD_RELOC_HI16_S: | |
6959 | case BFD_RELOC_MICROMIPS_HI16_S: | |
6960 | case BFD_RELOC_MIPS16_HI16_S: | |
6961 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
6962 | return TRUE; | |
6963 | ||
6964 | case BFD_RELOC_HI16: | |
6965 | case BFD_RELOC_MICROMIPS_HI16: | |
6966 | case BFD_RELOC_MIPS16_HI16: | |
6967 | *result = (operand >> 16) & 0xffff; | |
6968 | return TRUE; | |
6969 | ||
6970 | case BFD_RELOC_LO16: | |
6971 | case BFD_RELOC_MICROMIPS_LO16: | |
6972 | case BFD_RELOC_MIPS16_LO16: | |
6973 | *result = operand & 0xffff; | |
6974 | return TRUE; | |
6975 | ||
6976 | case BFD_RELOC_UNUSED: | |
6977 | *result = operand; | |
6978 | return TRUE; | |
6979 | ||
6980 | default: | |
6981 | return FALSE; | |
6982 | } | |
6983 | } | |
6984 | ||
71400594 RS |
6985 | /* Output an instruction. IP is the instruction information. |
6986 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
6987 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
6988 | a macro expansion. */ | |
71400594 RS |
6989 | |
6990 | static void | |
6991 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 6992 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 6993 | { |
14fe068b | 6994 | unsigned long prev_pinfo2, pinfo; |
71400594 | 6995 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 6996 | enum append_method method; |
2309ddf2 | 6997 | bfd_boolean relax32; |
2b0c8b40 | 6998 | int branch_disp; |
71400594 | 6999 | |
2309ddf2 | 7000 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7001 | fix_loongson2f (ip); |
7002 | ||
738f4d98 | 7003 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7004 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7005 | |
df58fc94 | 7006 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7007 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
7008 | |
7009 | if (mips_opts.micromips | |
7010 | && !expansionp | |
7011 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
7012 | && micromips_insn_length (ip->insn_mo) != 2) | |
7013 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7014 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7015 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7016 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7017 | |
15be625d CM |
7018 | if (address_expr == NULL) |
7019 | ip->complete_p = 1; | |
b886a2ab RS |
7020 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7021 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7022 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7023 | && address_expr->X_op == O_constant) |
7024 | { | |
15be625d CM |
7025 | switch (*reloc_type) |
7026 | { | |
15be625d | 7027 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7028 | { |
7029 | int shift; | |
7030 | ||
7031 | shift = mips_opts.micromips ? 1 : 2; | |
7032 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7033 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7034 | (unsigned long) address_expr->X_add_number); | |
7035 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7036 | & 0x3ffffff); | |
335574df | 7037 | ip->complete_p = 1; |
df58fc94 | 7038 | } |
15be625d CM |
7039 | break; |
7040 | ||
7041 | case BFD_RELOC_MIPS16_JMP: | |
7042 | if ((address_expr->X_add_number & 3) != 0) | |
7043 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7044 | (unsigned long) address_expr->X_add_number); | |
7045 | ip->insn_opcode |= | |
7046 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7047 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7048 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7049 | ip->complete_p = 1; |
15be625d CM |
7050 | break; |
7051 | ||
7052 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7053 | { |
7054 | int shift; | |
7055 | ||
7056 | shift = mips_opts.micromips ? 1 : 2; | |
7057 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7058 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7059 | (unsigned long) address_expr->X_add_number); | |
7060 | if (!mips_relax_branch) | |
7061 | { | |
7062 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7063 | & ~((1 << (shift + 16)) - 1)) | |
7064 | as_bad (_("branch address range overflow (0x%lx)"), | |
7065 | (unsigned long) address_expr->X_add_number); | |
7066 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7067 | & 0xffff); | |
7068 | } | |
df58fc94 | 7069 | } |
15be625d CM |
7070 | break; |
7071 | ||
7361da2c AB |
7072 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7073 | { | |
7074 | int shift; | |
7075 | ||
7076 | shift = 2; | |
7077 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7078 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7079 | (unsigned long) address_expr->X_add_number); | |
7080 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7081 | & ~((1 << (shift + 21)) - 1)) | |
7082 | as_bad (_("branch address range overflow (0x%lx)"), | |
7083 | (unsigned long) address_expr->X_add_number); | |
7084 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7085 | & 0x1fffff); | |
7086 | } | |
7087 | break; | |
7088 | ||
7089 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7090 | { | |
7091 | int shift; | |
7092 | ||
7093 | shift = 2; | |
7094 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7095 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7096 | (unsigned long) address_expr->X_add_number); | |
7097 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7098 | & ~((1 << (shift + 26)) - 1)) | |
7099 | as_bad (_("branch address range overflow (0x%lx)"), | |
7100 | (unsigned long) address_expr->X_add_number); | |
7101 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7102 | & 0x3ffffff); | |
7103 | } | |
7104 | break; | |
7105 | ||
15be625d | 7106 | default: |
b886a2ab RS |
7107 | { |
7108 | offsetT value; | |
7109 | ||
7110 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7111 | &value)) | |
7112 | { | |
7113 | ip->insn_opcode |= value & 0xffff; | |
7114 | ip->complete_p = 1; | |
7115 | } | |
7116 | } | |
7117 | break; | |
7118 | } | |
15be625d CM |
7119 | } |
7120 | ||
71400594 RS |
7121 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7122 | { | |
7123 | /* There are a lot of optimizations we could do that we don't. | |
7124 | In particular, we do not, in general, reorder instructions. | |
7125 | If you use gcc with optimization, it will reorder | |
7126 | instructions and generally do much more optimization then we | |
7127 | do here; repeating all that work in the assembler would only | |
7128 | benefit hand written assembly code, and does not seem worth | |
7129 | it. */ | |
7130 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7131 | ? nops_for_insn (0, history, NULL) |
7132 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7133 | if (nops > 0) |
252b5132 RH |
7134 | { |
7135 | fragS *old_frag; | |
7136 | unsigned long old_frag_offset; | |
7137 | int i; | |
252b5132 RH |
7138 | |
7139 | old_frag = frag_now; | |
7140 | old_frag_offset = frag_now_fix (); | |
7141 | ||
7142 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7143 | add_fixed_insn (NOP_INSN); |
7144 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7145 | |
7146 | if (listing) | |
7147 | { | |
7148 | listing_prev_line (); | |
7149 | /* We may be at the start of a variant frag. In case we | |
7150 | are, make sure there is enough space for the frag | |
7151 | after the frags created by listing_prev_line. The | |
7152 | argument to frag_grow here must be at least as large | |
7153 | as the argument to all other calls to frag_grow in | |
7154 | this file. We don't have to worry about being in the | |
7155 | middle of a variant frag, because the variants insert | |
7156 | all needed nop instructions themselves. */ | |
7157 | frag_grow (40); | |
7158 | } | |
7159 | ||
462427c4 | 7160 | mips_move_text_labels (); |
252b5132 RH |
7161 | |
7162 | #ifndef NO_ECOFF_DEBUGGING | |
7163 | if (ECOFF_DEBUGGING) | |
7164 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7165 | #endif | |
7166 | } | |
71400594 RS |
7167 | } |
7168 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7169 | { | |
932d1a1b RS |
7170 | int nops; |
7171 | ||
7172 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7173 | ignoring hazards generated by the first prev_nop_frag_since | |
7174 | instructions. */ | |
7175 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7176 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7177 | |
71400594 RS |
7178 | /* Enforce NOPS as a minimum. */ |
7179 | if (nops > prev_nop_frag_required) | |
7180 | prev_nop_frag_required = nops; | |
252b5132 | 7181 | |
71400594 RS |
7182 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7183 | { | |
7184 | /* Settle for the current number of nops. Update the history | |
7185 | accordingly (for the benefit of any future .set reorder code). */ | |
7186 | prev_nop_frag = NULL; | |
7187 | insert_into_history (prev_nop_frag_since, | |
7188 | prev_nop_frag_holds, NOP_INSN); | |
7189 | } | |
7190 | else | |
7191 | { | |
7192 | /* Allow this instruction to replace one of the nops that was | |
7193 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7194 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7195 | prev_nop_frag_holds--; |
7196 | prev_nop_frag_since++; | |
252b5132 RH |
7197 | } |
7198 | } | |
7199 | ||
e407c74b | 7200 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7201 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7202 | |
e410add4 RS |
7203 | dwarf2_emit_insn (0); |
7204 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7205 | so "move" the instruction address accordingly. | |
7206 | ||
7207 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7208 | entries. If this instruction is a branch that we are going to swap | |
7209 | with the previous instruction, the two instructions should be | |
7210 | treated as a unit, and the debug information for both instructions | |
7211 | should refer to the start of the branch sequence. Using the | |
7212 | current position is certainly wrong when swapping a 32-bit branch | |
7213 | and a 16-bit delay slot, since the current position would then be | |
7214 | in the middle of a branch. */ | |
7215 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7216 | |
df58fc94 RS |
7217 | relax32 = (mips_relax_branch |
7218 | /* Don't try branch relaxation within .set nomacro, or within | |
7219 | .set noat if we use $at for PIC computations. If it turns | |
7220 | out that the branch was out-of-range, we'll get an error. */ | |
7221 | && !mips_opts.warn_about_macros | |
7222 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7223 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7224 | as they have no complementing branches. */ | |
7225 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7226 | |
7227 | if (!HAVE_CODE_COMPRESSION | |
7228 | && address_expr | |
7229 | && relax32 | |
0b25d3e6 | 7230 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7231 | && delayed_branch_p (ip)) |
4a6a3df4 | 7232 | { |
895921c9 | 7233 | relaxed_branch = TRUE; |
1e915849 RS |
7234 | add_relaxed_insn (ip, (relaxed_branch_length |
7235 | (NULL, NULL, | |
11625dd8 RS |
7236 | uncond_branch_p (ip) ? -1 |
7237 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7238 | : 0)), 4, |
7239 | RELAX_BRANCH_ENCODE | |
66b3e8da | 7240 | (AT, |
11625dd8 RS |
7241 | uncond_branch_p (ip), |
7242 | branch_likely_p (ip), | |
1e915849 RS |
7243 | pinfo & INSN_WRITE_GPR_31, |
7244 | 0), | |
7245 | address_expr->X_add_symbol, | |
7246 | address_expr->X_add_number); | |
4a6a3df4 AO |
7247 | *reloc_type = BFD_RELOC_UNUSED; |
7248 | } | |
df58fc94 RS |
7249 | else if (mips_opts.micromips |
7250 | && address_expr | |
7251 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7252 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7253 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7254 | /* Don't try branch relaxation when users specify | |
7255 | 16-bit/32-bit instructions. */ | |
7256 | && !forced_insn_length) | |
df58fc94 RS |
7257 | { |
7258 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
7259 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
7260 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7261 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
7262 | int al = pinfo & INSN_WRITE_GPR_31; |
7263 | int length32; | |
7264 | ||
7265 | gas_assert (address_expr != NULL); | |
7266 | gas_assert (!mips_relax.sequence); | |
7267 | ||
2b0c8b40 | 7268 | relaxed_branch = TRUE; |
df58fc94 RS |
7269 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
7270 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
7271 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
7272 | relax32, 0, 0), | |
df58fc94 RS |
7273 | address_expr->X_add_symbol, |
7274 | address_expr->X_add_number); | |
7275 | *reloc_type = BFD_RELOC_UNUSED; | |
7276 | } | |
7277 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
7278 | { |
7279 | /* We need to set up a variant frag. */ | |
df58fc94 | 7280 | gas_assert (address_expr != NULL); |
1e915849 RS |
7281 | add_relaxed_insn (ip, 4, 0, |
7282 | RELAX_MIPS16_ENCODE | |
7283 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 7284 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 7285 | delayed_branch_p (&history[0]), |
1e915849 RS |
7286 | history[0].mips16_absolute_jump_p), |
7287 | make_expr_symbol (address_expr), 0); | |
252b5132 | 7288 | } |
5c04167a | 7289 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7290 | { |
11625dd8 | 7291 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7292 | /* Make sure there is enough room to swap this instruction with |
7293 | a following jump instruction. */ | |
7294 | frag_grow (6); | |
1e915849 | 7295 | add_fixed_insn (ip); |
252b5132 RH |
7296 | } |
7297 | else | |
7298 | { | |
7299 | if (mips_opts.mips16 | |
7300 | && mips_opts.noreorder | |
11625dd8 | 7301 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7302 | as_warn (_("extended instruction in delay slot")); |
7303 | ||
4d7206a2 RS |
7304 | if (mips_relax.sequence) |
7305 | { | |
7306 | /* If we've reached the end of this frag, turn it into a variant | |
7307 | frag and record the information for the instructions we've | |
7308 | written so far. */ | |
7309 | if (frag_room () < 4) | |
7310 | relax_close_frag (); | |
df58fc94 | 7311 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7312 | } |
7313 | ||
584892a6 | 7314 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7315 | { |
7316 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7317 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7318 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7319 | mips_macro_warning.insns[0]++; | |
7320 | } | |
584892a6 | 7321 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7322 | { |
7323 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7324 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7325 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7326 | mips_macro_warning.insns[1]++; | |
7327 | } | |
584892a6 | 7328 | |
1e915849 RS |
7329 | if (mips_opts.mips16) |
7330 | { | |
7331 | ip->fixed_p = 1; | |
7332 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7333 | } | |
7334 | add_fixed_insn (ip); | |
252b5132 RH |
7335 | } |
7336 | ||
9fe77896 | 7337 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7338 | { |
df58fc94 | 7339 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7340 | reloc_howto_type *howto0; |
9fe77896 RS |
7341 | reloc_howto_type *howto; |
7342 | int i; | |
34ce925e | 7343 | |
df58fc94 RS |
7344 | /* Perform any necessary conversion to microMIPS relocations |
7345 | and find out how many relocations there actually are. */ | |
7346 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7347 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7348 | ||
9fe77896 RS |
7349 | /* In a compound relocation, it is the final (outermost) |
7350 | operator that determines the relocated field. */ | |
2309ddf2 | 7351 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7352 | if (!howto) |
7353 | abort (); | |
2309ddf2 MR |
7354 | |
7355 | if (i > 1) | |
7356 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7357 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7358 | bfd_get_reloc_size (howto), | |
7359 | address_expr, | |
2309ddf2 MR |
7360 | howto0 && howto0->pc_relative, |
7361 | final_type[0]); | |
9fe77896 RS |
7362 | |
7363 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7364 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7365 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7366 | ||
7367 | /* These relocations can have an addend that won't fit in | |
7368 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7369 | if (GPR_SIZE == 64 |
9fe77896 RS |
7370 | && ! howto->partial_inplace |
7371 | && (reloc_type[0] == BFD_RELOC_16 | |
7372 | || reloc_type[0] == BFD_RELOC_32 | |
7373 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7374 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7375 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7376 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7377 | || reloc_type[0] == BFD_RELOC_64 | |
7378 | || reloc_type[0] == BFD_RELOC_CTOR | |
7379 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7380 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7381 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7382 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7383 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7384 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7385 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7386 | || hi16_reloc_p (reloc_type[0]) | |
7387 | || lo16_reloc_p (reloc_type[0]))) | |
7388 | ip->fixp[0]->fx_no_overflow = 1; | |
7389 | ||
ddaf2c41 MR |
7390 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7391 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7392 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7393 | ip->fixp[0]->fx_no_overflow = 1; | |
7394 | ||
9fe77896 RS |
7395 | if (mips_relax.sequence) |
7396 | { | |
7397 | if (mips_relax.first_fixup == 0) | |
7398 | mips_relax.first_fixup = ip->fixp[0]; | |
7399 | } | |
7400 | else if (reloc_needs_lo_p (*reloc_type)) | |
7401 | { | |
7402 | struct mips_hi_fixup *hi_fixup; | |
7403 | ||
7404 | /* Reuse the last entry if it already has a matching %lo. */ | |
7405 | hi_fixup = mips_hi_fixup_list; | |
7406 | if (hi_fixup == 0 | |
7407 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7408 | { |
9fe77896 RS |
7409 | hi_fixup = ((struct mips_hi_fixup *) |
7410 | xmalloc (sizeof (struct mips_hi_fixup))); | |
7411 | hi_fixup->next = mips_hi_fixup_list; | |
7412 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7413 | } |
9fe77896 RS |
7414 | hi_fixup->fixp = ip->fixp[0]; |
7415 | hi_fixup->seg = now_seg; | |
7416 | } | |
252b5132 | 7417 | |
9fe77896 RS |
7418 | /* Add fixups for the second and third relocations, if given. |
7419 | Note that the ABI allows the second relocation to be | |
7420 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7421 | moment we only use RSS_UNDEF, but we could add support | |
7422 | for the others if it ever becomes necessary. */ | |
7423 | for (i = 1; i < 3; i++) | |
7424 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7425 | { | |
7426 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7427 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7428 | FALSE, final_type[i]); |
f6688943 | 7429 | |
9fe77896 RS |
7430 | /* Use fx_tcbit to mark compound relocs. */ |
7431 | ip->fixp[0]->fx_tcbit = 1; | |
7432 | ip->fixp[i]->fx_tcbit = 1; | |
7433 | } | |
252b5132 | 7434 | } |
1e915849 | 7435 | install_insn (ip); |
252b5132 RH |
7436 | |
7437 | /* Update the register mask information. */ | |
4c260379 RS |
7438 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7439 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7440 | |
a4e06468 | 7441 | switch (method) |
252b5132 | 7442 | { |
a4e06468 RS |
7443 | case APPEND_ADD: |
7444 | insert_into_history (0, 1, ip); | |
7445 | break; | |
7446 | ||
7447 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7448 | { |
7449 | struct mips_cl_insn *nop; | |
7450 | ||
7451 | insert_into_history (0, 1, ip); | |
7452 | nop = get_delay_slot_nop (ip); | |
7453 | add_fixed_insn (nop); | |
7454 | insert_into_history (0, 1, nop); | |
7455 | if (mips_relax.sequence) | |
7456 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7457 | } | |
a4e06468 RS |
7458 | break; |
7459 | ||
7460 | case APPEND_ADD_COMPACT: | |
7461 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7462 | gas_assert (mips_opts.mips16); | |
7463 | ip->insn_opcode |= 0x0080; | |
7464 | find_altered_mips16_opcode (ip); | |
7465 | install_insn (ip); | |
7466 | insert_into_history (0, 1, ip); | |
7467 | break; | |
7468 | ||
7469 | case APPEND_SWAP: | |
7470 | { | |
7471 | struct mips_cl_insn delay = history[0]; | |
7472 | if (mips_opts.mips16) | |
7473 | { | |
7474 | know (delay.frag == ip->frag); | |
7475 | move_insn (ip, delay.frag, delay.where); | |
7476 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
7477 | } | |
464ab0e5 | 7478 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
7479 | { |
7480 | /* Add the delay slot instruction to the end of the | |
7481 | current frag and shrink the fixed part of the | |
7482 | original frag. If the branch occupies the tail of | |
7483 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7484 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7485 | if (delay.frag == ip->frag) |
2b0c8b40 | 7486 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7487 | add_fixed_insn (&delay); |
7488 | } | |
7489 | else | |
7490 | { | |
2b0c8b40 MR |
7491 | move_insn (&delay, ip->frag, |
7492 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
7493 | move_insn (ip, history[0].frag, history[0].where); |
7494 | } | |
7495 | history[0] = *ip; | |
7496 | delay.fixed_p = 1; | |
7497 | insert_into_history (0, 1, &delay); | |
7498 | } | |
7499 | break; | |
252b5132 RH |
7500 | } |
7501 | ||
13408f1e | 7502 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7503 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7504 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7505 | { |
7506 | unsigned int i; | |
7507 | ||
79850f26 | 7508 | mips_no_prev_insn (); |
13408f1e | 7509 | |
e407c74b | 7510 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7511 | history[i].cleared_p = 1; |
e407c74b NC |
7512 | } |
7513 | ||
df58fc94 RS |
7514 | /* We need to emit a label at the end of branch-likely macros. */ |
7515 | if (emit_branch_likely_macro) | |
7516 | { | |
7517 | emit_branch_likely_macro = FALSE; | |
7518 | micromips_add_label (); | |
7519 | } | |
7520 | ||
252b5132 RH |
7521 | /* We just output an insn, so the next one doesn't have a label. */ |
7522 | mips_clear_insn_labels (); | |
252b5132 RH |
7523 | } |
7524 | ||
e407c74b NC |
7525 | /* Forget that there was any previous instruction or label. |
7526 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7527 | |
7528 | static void | |
7d10b47d | 7529 | mips_no_prev_insn (void) |
252b5132 | 7530 | { |
7d10b47d RS |
7531 | prev_nop_frag = NULL; |
7532 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7533 | mips_clear_insn_labels (); |
7534 | } | |
7535 | ||
7d10b47d RS |
7536 | /* This function must be called before we emit something other than |
7537 | instructions. It is like mips_no_prev_insn except that it inserts | |
7538 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7539 | |
7d10b47d RS |
7540 | void |
7541 | mips_emit_delays (void) | |
252b5132 RH |
7542 | { |
7543 | if (! mips_opts.noreorder) | |
7544 | { | |
932d1a1b | 7545 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7546 | if (nops > 0) |
7547 | { | |
7d10b47d RS |
7548 | while (nops-- > 0) |
7549 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7550 | mips_move_text_labels (); |
7d10b47d RS |
7551 | } |
7552 | } | |
7553 | mips_no_prev_insn (); | |
7554 | } | |
7555 | ||
7556 | /* Start a (possibly nested) noreorder block. */ | |
7557 | ||
7558 | static void | |
7559 | start_noreorder (void) | |
7560 | { | |
7561 | if (mips_opts.noreorder == 0) | |
7562 | { | |
7563 | unsigned int i; | |
7564 | int nops; | |
7565 | ||
7566 | /* None of the instructions before the .set noreorder can be moved. */ | |
7567 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7568 | history[i].fixed_p = 1; | |
7569 | ||
7570 | /* Insert any nops that might be needed between the .set noreorder | |
7571 | block and the previous instructions. We will later remove any | |
7572 | nops that turn out not to be needed. */ | |
932d1a1b | 7573 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7574 | if (nops > 0) |
7575 | { | |
7576 | if (mips_optimize != 0) | |
252b5132 RH |
7577 | { |
7578 | /* Record the frag which holds the nop instructions, so | |
7579 | that we can remove them if we don't need them. */ | |
df58fc94 | 7580 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7581 | prev_nop_frag = frag_now; |
7582 | prev_nop_frag_holds = nops; | |
7583 | prev_nop_frag_required = 0; | |
7584 | prev_nop_frag_since = 0; | |
7585 | } | |
7586 | ||
7587 | for (; nops > 0; --nops) | |
1e915849 | 7588 | add_fixed_insn (NOP_INSN); |
252b5132 | 7589 | |
7d10b47d RS |
7590 | /* Move on to a new frag, so that it is safe to simply |
7591 | decrease the size of prev_nop_frag. */ | |
7592 | frag_wane (frag_now); | |
7593 | frag_new (0); | |
462427c4 | 7594 | mips_move_text_labels (); |
252b5132 | 7595 | } |
df58fc94 | 7596 | mips_mark_labels (); |
7d10b47d | 7597 | mips_clear_insn_labels (); |
252b5132 | 7598 | } |
7d10b47d RS |
7599 | mips_opts.noreorder++; |
7600 | mips_any_noreorder = 1; | |
7601 | } | |
252b5132 | 7602 | |
7d10b47d | 7603 | /* End a nested noreorder block. */ |
252b5132 | 7604 | |
7d10b47d RS |
7605 | static void |
7606 | end_noreorder (void) | |
7607 | { | |
7608 | mips_opts.noreorder--; | |
7609 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7610 | { | |
7611 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7612 | handling nop insertion the .set reorder way. */ | |
7613 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7614 | * NOP_INSN_SIZE); |
7d10b47d RS |
7615 | insert_into_history (prev_nop_frag_since, |
7616 | prev_nop_frag_required, NOP_INSN); | |
7617 | prev_nop_frag = NULL; | |
7618 | } | |
252b5132 RH |
7619 | } |
7620 | ||
97d87491 RS |
7621 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7622 | higher bits unset. */ | |
7623 | ||
7624 | static void | |
7625 | normalize_constant_expr (expressionS *ex) | |
7626 | { | |
7627 | if (ex->X_op == O_constant | |
7628 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7629 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7630 | - 0x80000000); | |
7631 | } | |
7632 | ||
7633 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7634 | all higher bits unset. */ | |
7635 | ||
7636 | static void | |
7637 | normalize_address_expr (expressionS *ex) | |
7638 | { | |
7639 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7640 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7641 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7642 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7643 | - 0x80000000); | |
7644 | } | |
7645 | ||
7646 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7647 | Return true if the match was successful. | |
7648 | ||
7649 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7650 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7651 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7652 | as for mips_arg_info. */ | |
7653 | ||
7654 | static bfd_boolean | |
7655 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7656 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7657 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7658 | { |
7659 | const char *args; | |
7660 | struct mips_arg_info arg; | |
7661 | const struct mips_operand *operand; | |
7662 | char c; | |
7663 | ||
7664 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7665 | offset_expr.X_op = O_absent; |
7666 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7667 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7668 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7669 | ||
7670 | create_insn (insn, opcode); | |
60f20e8b RS |
7671 | /* When no opcode suffix is specified, assume ".xyzw". */ |
7672 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
7673 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
7674 | else | |
7675 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
7676 | memset (&arg, 0, sizeof (arg)); |
7677 | arg.insn = insn; | |
7678 | arg.token = tokens; | |
7679 | arg.argnum = 1; | |
7680 | arg.last_regno = ILLEGAL_REG; | |
7681 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 7682 | arg.lax_match = lax_match; |
97d87491 RS |
7683 | for (args = opcode->args;; ++args) |
7684 | { | |
7685 | if (arg.token->type == OT_END) | |
7686 | { | |
7687 | /* Handle unary instructions in which only one operand is given. | |
7688 | The source is then the same as the destination. */ | |
7689 | if (arg.opnum == 1 && *args == ',') | |
7690 | { | |
7691 | operand = (mips_opts.micromips | |
7692 | ? decode_micromips_operand (args + 1) | |
7693 | : decode_mips_operand (args + 1)); | |
7694 | if (operand && mips_optional_operand_p (operand)) | |
7695 | { | |
7696 | arg.token = tokens; | |
7697 | arg.argnum = 1; | |
7698 | continue; | |
7699 | } | |
7700 | } | |
7701 | ||
7702 | /* Treat elided base registers as $0. */ | |
7703 | if (strcmp (args, "(b)") == 0) | |
7704 | args += 3; | |
7705 | ||
7706 | if (args[0] == '+') | |
7707 | switch (args[1]) | |
7708 | { | |
7709 | case 'K': | |
7710 | case 'N': | |
7711 | /* The register suffix is optional. */ | |
7712 | args += 2; | |
7713 | break; | |
7714 | } | |
7715 | ||
7716 | /* Fail the match if there were too few operands. */ | |
7717 | if (*args) | |
7718 | return FALSE; | |
7719 | ||
7720 | /* Successful match. */ | |
60f20e8b RS |
7721 | if (!complete_p) |
7722 | return TRUE; | |
e3de51ce | 7723 | clear_insn_error (); |
97d87491 RS |
7724 | if (arg.dest_regno == arg.last_regno |
7725 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
7726 | { | |
7727 | if (arg.opnum == 2) | |
e3de51ce | 7728 | set_insn_error |
1661c76c | 7729 | (0, _("source and destination must be different")); |
97d87491 | 7730 | else if (arg.last_regno == 31) |
e3de51ce | 7731 | set_insn_error |
1661c76c | 7732 | (0, _("a destination register must be supplied")); |
97d87491 | 7733 | } |
173d3447 CF |
7734 | else if (arg.last_regno == 31 |
7735 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
7736 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
7737 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
7738 | check_completed_insn (&arg); |
7739 | return TRUE; | |
7740 | } | |
7741 | ||
7742 | /* Fail the match if the line has too many operands. */ | |
7743 | if (*args == 0) | |
7744 | return FALSE; | |
7745 | ||
7746 | /* Handle characters that need to match exactly. */ | |
7747 | if (*args == '(' || *args == ')' || *args == ',') | |
7748 | { | |
7749 | if (match_char (&arg, *args)) | |
7750 | continue; | |
7751 | return FALSE; | |
7752 | } | |
7753 | if (*args == '#') | |
7754 | { | |
7755 | ++args; | |
7756 | if (arg.token->type == OT_DOUBLE_CHAR | |
7757 | && arg.token->u.ch == *args) | |
7758 | { | |
7759 | ++arg.token; | |
7760 | continue; | |
7761 | } | |
7762 | return FALSE; | |
7763 | } | |
7764 | ||
7765 | /* Handle special macro operands. Work out the properties of | |
7766 | other operands. */ | |
7767 | arg.opnum += 1; | |
97d87491 RS |
7768 | switch (*args) |
7769 | { | |
7361da2c AB |
7770 | case '-': |
7771 | switch (args[1]) | |
7772 | { | |
7773 | case 'A': | |
7774 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
7775 | break; | |
7776 | ||
7777 | case 'B': | |
7778 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
7779 | break; | |
7780 | } | |
7781 | break; | |
7782 | ||
97d87491 RS |
7783 | case '+': |
7784 | switch (args[1]) | |
7785 | { | |
97d87491 RS |
7786 | case 'i': |
7787 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7788 | break; | |
7361da2c AB |
7789 | |
7790 | case '\'': | |
7791 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
7792 | break; | |
7793 | ||
7794 | case '\"': | |
7795 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
7796 | break; | |
97d87491 RS |
7797 | } |
7798 | break; | |
7799 | ||
97d87491 | 7800 | case 'I': |
1a00e612 RS |
7801 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
7802 | return FALSE; | |
7803 | imm_expr.X_op = O_constant; | |
bad1aba3 | 7804 | if (GPR_SIZE == 32) |
97d87491 RS |
7805 | normalize_constant_expr (&imm_expr); |
7806 | continue; | |
7807 | ||
7808 | case 'A': | |
7809 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
7810 | { | |
7811 | /* Assume that the offset has been elided and that what | |
7812 | we saw was a base register. The match will fail later | |
7813 | if that assumption turns out to be wrong. */ | |
7814 | offset_expr.X_op = O_constant; | |
7815 | offset_expr.X_add_number = 0; | |
7816 | } | |
97d87491 | 7817 | else |
1a00e612 RS |
7818 | { |
7819 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
7820 | return FALSE; | |
7821 | normalize_address_expr (&offset_expr); | |
7822 | } | |
97d87491 RS |
7823 | continue; |
7824 | ||
7825 | case 'F': | |
7826 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7827 | 8, TRUE)) | |
1a00e612 | 7828 | return FALSE; |
97d87491 RS |
7829 | continue; |
7830 | ||
7831 | case 'L': | |
7832 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7833 | 8, FALSE)) | |
1a00e612 | 7834 | return FALSE; |
97d87491 RS |
7835 | continue; |
7836 | ||
7837 | case 'f': | |
7838 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7839 | 4, TRUE)) | |
1a00e612 | 7840 | return FALSE; |
97d87491 RS |
7841 | continue; |
7842 | ||
7843 | case 'l': | |
7844 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
7845 | 4, FALSE)) | |
1a00e612 | 7846 | return FALSE; |
97d87491 RS |
7847 | continue; |
7848 | ||
97d87491 RS |
7849 | case 'p': |
7850 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7851 | break; | |
7852 | ||
7853 | case 'a': | |
7854 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7855 | break; | |
7856 | ||
7857 | case 'm': | |
7858 | gas_assert (mips_opts.micromips); | |
7859 | c = args[1]; | |
7860 | switch (c) | |
7861 | { | |
7862 | case 'D': | |
7863 | case 'E': | |
7864 | if (!forced_insn_length) | |
7865 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
7866 | else if (c == 'D') | |
7867 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
7868 | else | |
7869 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
7870 | break; | |
7871 | } | |
7872 | break; | |
7873 | } | |
7874 | ||
7875 | operand = (mips_opts.micromips | |
7876 | ? decode_micromips_operand (args) | |
7877 | : decode_mips_operand (args)); | |
7878 | if (!operand) | |
7879 | abort (); | |
7880 | ||
7881 | /* Skip prefixes. */ | |
7361da2c | 7882 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
7883 | args++; |
7884 | ||
7885 | if (mips_optional_operand_p (operand) | |
7886 | && args[1] == ',' | |
7887 | && (arg.token[0].type != OT_REG | |
7888 | || arg.token[1].type == OT_END)) | |
7889 | { | |
7890 | /* Assume that the register has been elided and is the | |
7891 | same as the first operand. */ | |
7892 | arg.token = tokens; | |
7893 | arg.argnum = 1; | |
7894 | } | |
7895 | ||
7896 | if (!match_operand (&arg, operand)) | |
7897 | return FALSE; | |
7898 | } | |
7899 | } | |
7900 | ||
7901 | /* Like match_insn, but for MIPS16. */ | |
7902 | ||
7903 | static bfd_boolean | |
7904 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 7905 | struct mips_operand_token *tokens) |
97d87491 RS |
7906 | { |
7907 | const char *args; | |
7908 | const struct mips_operand *operand; | |
7909 | const struct mips_operand *ext_operand; | |
7910 | struct mips_arg_info arg; | |
7911 | int relax_char; | |
7912 | ||
7913 | create_insn (insn, opcode); | |
7914 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7915 | offset_expr.X_op = O_absent; |
7916 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7917 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7918 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7919 | relax_char = 0; | |
7920 | ||
7921 | memset (&arg, 0, sizeof (arg)); | |
7922 | arg.insn = insn; | |
7923 | arg.token = tokens; | |
7924 | arg.argnum = 1; | |
7925 | arg.last_regno = ILLEGAL_REG; | |
7926 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
7927 | relax_char = 0; |
7928 | for (args = opcode->args;; ++args) | |
7929 | { | |
7930 | int c; | |
7931 | ||
7932 | if (arg.token->type == OT_END) | |
7933 | { | |
7934 | offsetT value; | |
7935 | ||
7936 | /* Handle unary instructions in which only one operand is given. | |
7937 | The source is then the same as the destination. */ | |
7938 | if (arg.opnum == 1 && *args == ',') | |
7939 | { | |
7940 | operand = decode_mips16_operand (args[1], FALSE); | |
7941 | if (operand && mips_optional_operand_p (operand)) | |
7942 | { | |
7943 | arg.token = tokens; | |
7944 | arg.argnum = 1; | |
7945 | continue; | |
7946 | } | |
7947 | } | |
7948 | ||
7949 | /* Fail the match if there were too few operands. */ | |
7950 | if (*args) | |
7951 | return FALSE; | |
7952 | ||
7953 | /* Successful match. Stuff the immediate value in now, if | |
7954 | we can. */ | |
e3de51ce | 7955 | clear_insn_error (); |
97d87491 RS |
7956 | if (opcode->pinfo == INSN_MACRO) |
7957 | { | |
7958 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
7959 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
7960 | } | |
7961 | else if (relax_char | |
7962 | && offset_expr.X_op == O_constant | |
7963 | && calculate_reloc (*offset_reloc, | |
7964 | offset_expr.X_add_number, | |
7965 | &value)) | |
7966 | { | |
7967 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7968 | forced_insn_length, &insn->insn_opcode); | |
7969 | offset_expr.X_op = O_absent; | |
7970 | *offset_reloc = BFD_RELOC_UNUSED; | |
7971 | } | |
7972 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
7973 | { | |
7974 | if (forced_insn_length == 2) | |
e3de51ce | 7975 | set_insn_error (0, _("invalid unextended operand value")); |
97d87491 RS |
7976 | forced_insn_length = 4; |
7977 | insn->insn_opcode |= MIPS16_EXTEND; | |
7978 | } | |
7979 | else if (relax_char) | |
7980 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
7981 | ||
7982 | check_completed_insn (&arg); | |
7983 | return TRUE; | |
7984 | } | |
7985 | ||
7986 | /* Fail the match if the line has too many operands. */ | |
7987 | if (*args == 0) | |
7988 | return FALSE; | |
7989 | ||
7990 | /* Handle characters that need to match exactly. */ | |
7991 | if (*args == '(' || *args == ')' || *args == ',') | |
7992 | { | |
7993 | if (match_char (&arg, *args)) | |
7994 | continue; | |
7995 | return FALSE; | |
7996 | } | |
7997 | ||
7998 | arg.opnum += 1; | |
7999 | c = *args; | |
8000 | switch (c) | |
8001 | { | |
8002 | case 'p': | |
8003 | case 'q': | |
8004 | case 'A': | |
8005 | case 'B': | |
8006 | case 'E': | |
8007 | relax_char = c; | |
8008 | break; | |
8009 | ||
8010 | case 'I': | |
1a00e612 RS |
8011 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8012 | return FALSE; | |
8013 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8014 | if (GPR_SIZE == 32) |
97d87491 RS |
8015 | normalize_constant_expr (&imm_expr); |
8016 | continue; | |
8017 | ||
8018 | case 'a': | |
8019 | case 'i': | |
8020 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8021 | insn->insn_opcode <<= 16; | |
8022 | break; | |
8023 | } | |
8024 | ||
8025 | operand = decode_mips16_operand (c, FALSE); | |
8026 | if (!operand) | |
8027 | abort (); | |
8028 | ||
8029 | /* '6' is a special case. It is used for BREAK and SDBBP, | |
8030 | whose operands are only meaningful to the software that decodes | |
8031 | them. This means that there is no architectural reason why | |
8032 | they cannot be prefixed by EXTEND, but in practice, | |
8033 | exception handlers will only look at the instruction | |
8034 | itself. We therefore allow '6' to be extended when | |
8035 | disassembling but not when assembling. */ | |
8036 | if (operand->type != OP_PCREL && c != '6') | |
8037 | { | |
8038 | ext_operand = decode_mips16_operand (c, TRUE); | |
8039 | if (operand != ext_operand) | |
8040 | { | |
8041 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8042 | { | |
8043 | offset_expr.X_op = O_constant; | |
8044 | offset_expr.X_add_number = 0; | |
8045 | relax_char = c; | |
8046 | continue; | |
8047 | } | |
8048 | ||
8049 | /* We need the OT_INTEGER check because some MIPS16 | |
8050 | immediate variants are listed before the register ones. */ | |
8051 | if (arg.token->type != OT_INTEGER | |
8052 | || !match_expression (&arg, &offset_expr, offset_reloc)) | |
8053 | return FALSE; | |
8054 | ||
8055 | /* '8' is used for SLTI(U) and has traditionally not | |
8056 | been allowed to take relocation operators. */ | |
8057 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8058 | && (ext_operand->size != 16 || c == '8')) | |
8059 | return FALSE; | |
8060 | ||
8061 | relax_char = c; | |
8062 | continue; | |
8063 | } | |
8064 | } | |
8065 | ||
8066 | if (mips_optional_operand_p (operand) | |
8067 | && args[1] == ',' | |
8068 | && (arg.token[0].type != OT_REG | |
8069 | || arg.token[1].type == OT_END)) | |
8070 | { | |
8071 | /* Assume that the register has been elided and is the | |
8072 | same as the first operand. */ | |
8073 | arg.token = tokens; | |
8074 | arg.argnum = 1; | |
8075 | } | |
8076 | ||
8077 | if (!match_operand (&arg, operand)) | |
8078 | return FALSE; | |
8079 | } | |
8080 | } | |
8081 | ||
60f20e8b RS |
8082 | /* Record that the current instruction is invalid for the current ISA. */ |
8083 | ||
8084 | static void | |
8085 | match_invalid_for_isa (void) | |
8086 | { | |
8087 | set_insn_error_ss | |
1661c76c | 8088 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8089 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8090 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8091 | } | |
8092 | ||
8093 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8094 | Return true if a definite match or failure was found, storing any match | |
8095 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8096 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8097 | tried and failed to match under normal conditions and now want to try a | |
8098 | more relaxed match. */ | |
8099 | ||
8100 | static bfd_boolean | |
8101 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8102 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8103 | int opcode_extra, bfd_boolean lax_match) | |
8104 | { | |
8105 | const struct mips_opcode *opcode; | |
8106 | const struct mips_opcode *invalid_delay_slot; | |
8107 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8108 | ||
8109 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8110 | current ISA or forced_length. */ | |
8111 | invalid_delay_slot = 0; | |
8112 | seen_valid_for_isa = FALSE; | |
8113 | seen_valid_for_size = FALSE; | |
8114 | opcode = first; | |
8115 | do | |
8116 | { | |
8117 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8118 | if (is_opcode_valid (opcode)) | |
8119 | { | |
8120 | seen_valid_for_isa = TRUE; | |
8121 | if (is_size_valid (opcode)) | |
8122 | { | |
8123 | bfd_boolean delay_slot_ok; | |
8124 | ||
8125 | seen_valid_for_size = TRUE; | |
8126 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8127 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8128 | lax_match, delay_slot_ok)) | |
8129 | { | |
8130 | if (!delay_slot_ok) | |
8131 | { | |
8132 | if (!invalid_delay_slot) | |
8133 | invalid_delay_slot = opcode; | |
8134 | } | |
8135 | else | |
8136 | return TRUE; | |
8137 | } | |
8138 | } | |
8139 | } | |
8140 | ++opcode; | |
8141 | } | |
8142 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8143 | ||
8144 | /* If the only matches we found had the wrong length for the delay slot, | |
8145 | pick the first such match. We'll issue an appropriate warning later. */ | |
8146 | if (invalid_delay_slot) | |
8147 | { | |
8148 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8149 | lax_match, TRUE)) | |
8150 | return TRUE; | |
8151 | abort (); | |
8152 | } | |
8153 | ||
8154 | /* Handle the case where we didn't try to match an instruction because | |
8155 | all the alternatives were incompatible with the current ISA. */ | |
8156 | if (!seen_valid_for_isa) | |
8157 | { | |
8158 | match_invalid_for_isa (); | |
8159 | return TRUE; | |
8160 | } | |
8161 | ||
8162 | /* Handle the case where we didn't try to match an instruction because | |
8163 | all the alternatives were of the wrong size. */ | |
8164 | if (!seen_valid_for_size) | |
8165 | { | |
8166 | if (mips_opts.insn32) | |
1661c76c | 8167 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8168 | else |
8169 | set_insn_error_i | |
1661c76c | 8170 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8171 | 8 * forced_insn_length); |
8172 | return TRUE; | |
8173 | } | |
8174 | ||
8175 | return FALSE; | |
8176 | } | |
8177 | ||
8178 | /* Like match_insns, but for MIPS16. */ | |
8179 | ||
8180 | static bfd_boolean | |
8181 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8182 | struct mips_operand_token *tokens) | |
8183 | { | |
8184 | const struct mips_opcode *opcode; | |
8185 | bfd_boolean seen_valid_for_isa; | |
8186 | ||
8187 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8188 | current ISA. There are no separate entries for extended forms so | |
8189 | we deal with forced_length later. */ | |
8190 | seen_valid_for_isa = FALSE; | |
8191 | opcode = first; | |
8192 | do | |
8193 | { | |
8194 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8195 | if (is_opcode_valid_16 (opcode)) | |
8196 | { | |
8197 | seen_valid_for_isa = TRUE; | |
8198 | if (match_mips16_insn (insn, opcode, tokens)) | |
8199 | return TRUE; | |
8200 | } | |
8201 | ++opcode; | |
8202 | } | |
8203 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8204 | && strcmp (opcode->name, first->name) == 0); | |
8205 | ||
8206 | /* Handle the case where we didn't try to match an instruction because | |
8207 | all the alternatives were incompatible with the current ISA. */ | |
8208 | if (!seen_valid_for_isa) | |
8209 | { | |
8210 | match_invalid_for_isa (); | |
8211 | return TRUE; | |
8212 | } | |
8213 | ||
8214 | return FALSE; | |
8215 | } | |
8216 | ||
584892a6 RS |
8217 | /* Set up global variables for the start of a new macro. */ |
8218 | ||
8219 | static void | |
8220 | macro_start (void) | |
8221 | { | |
8222 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8223 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8224 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8225 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8226 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8227 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
8228 | switch (history[0].insn_mo->pinfo2 |
8229 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8230 | { | |
8231 | case INSN2_BRANCH_DELAY_32BIT: | |
8232 | mips_macro_warning.delay_slot_length = 4; | |
8233 | break; | |
8234 | case INSN2_BRANCH_DELAY_16BIT: | |
8235 | mips_macro_warning.delay_slot_length = 2; | |
8236 | break; | |
8237 | default: | |
8238 | mips_macro_warning.delay_slot_length = 0; | |
8239 | break; | |
8240 | } | |
8241 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
8242 | } |
8243 | ||
df58fc94 RS |
8244 | /* Given that a macro is longer than one instruction or of the wrong size, |
8245 | return the appropriate warning for it. Return null if no warning is | |
8246 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8247 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8248 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8249 | |
8250 | static const char * | |
8251 | macro_warning (relax_substateT subtype) | |
8252 | { | |
8253 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8254 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8255 | " in a branch delay slot"); |
8256 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8257 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8258 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8259 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8260 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8261 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8262 | " in a 16-bit branch delay slot") |
1661c76c | 8263 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8264 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8265 | else |
8266 | return 0; | |
8267 | } | |
8268 | ||
8269 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8270 | ||
8271 | static void | |
8272 | macro_end (void) | |
8273 | { | |
df58fc94 RS |
8274 | /* Relaxation warning flags. */ |
8275 | relax_substateT subtype = 0; | |
8276 | ||
8277 | /* Check delay slot size requirements. */ | |
8278 | if (mips_macro_warning.delay_slot_length == 2) | |
8279 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8280 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8281 | { |
df58fc94 RS |
8282 | if (mips_macro_warning.delay_slot_length |
8283 | != mips_macro_warning.first_insn_sizes[0]) | |
8284 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8285 | if (mips_macro_warning.delay_slot_length | |
8286 | != mips_macro_warning.first_insn_sizes[1]) | |
8287 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8288 | } | |
584892a6 | 8289 | |
df58fc94 RS |
8290 | /* Check instruction count requirements. */ |
8291 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8292 | { | |
8293 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8294 | subtype |= RELAX_SECOND_LONGER; |
8295 | if (mips_opts.warn_about_macros) | |
8296 | subtype |= RELAX_NOMACRO; | |
8297 | if (mips_macro_warning.delay_slot_p) | |
8298 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8299 | } |
584892a6 | 8300 | |
df58fc94 RS |
8301 | /* If both alternatives fail to fill a delay slot correctly, |
8302 | emit the warning now. */ | |
8303 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8304 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8305 | { | |
8306 | relax_substateT s; | |
8307 | const char *msg; | |
8308 | ||
8309 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8310 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8311 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8312 | msg = macro_warning (s); | |
8313 | if (msg != NULL) | |
8314 | as_warn ("%s", msg); | |
8315 | subtype &= ~s; | |
8316 | } | |
8317 | ||
8318 | /* If both implementations are longer than 1 instruction, then emit the | |
8319 | warning now. */ | |
8320 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8321 | { | |
8322 | relax_substateT s; | |
8323 | const char *msg; | |
8324 | ||
8325 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8326 | msg = macro_warning (s); | |
8327 | if (msg != NULL) | |
8328 | as_warn ("%s", msg); | |
8329 | subtype &= ~s; | |
584892a6 | 8330 | } |
df58fc94 RS |
8331 | |
8332 | /* If any flags still set, then one implementation might need a warning | |
8333 | and the other either will need one of a different kind or none at all. | |
8334 | Pass any remaining flags over to relaxation. */ | |
8335 | if (mips_macro_warning.first_frag != NULL) | |
8336 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8337 | } |
8338 | ||
df58fc94 RS |
8339 | /* Instruction operand formats used in macros that vary between |
8340 | standard MIPS and microMIPS code. */ | |
8341 | ||
833794fc | 8342 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8343 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8344 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8345 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8346 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8347 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8348 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8349 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8350 | ||
833794fc | 8351 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8352 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8353 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8354 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8355 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8356 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8357 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8358 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8359 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8360 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8361 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8362 | ||
6e1304d8 RS |
8363 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8364 | The first argument in *ARGS will be either the code for a single | |
8365 | relocation or -1 followed by the three codes that make up a | |
8366 | composite relocation. */ | |
8367 | ||
8368 | static void | |
8369 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8370 | { | |
8371 | int i, next; | |
8372 | ||
8373 | next = va_arg (*args, int); | |
8374 | if (next >= 0) | |
8375 | r[0] = (bfd_reloc_code_real_type) next; | |
8376 | else | |
f2ae14a1 RS |
8377 | { |
8378 | for (i = 0; i < 3; i++) | |
8379 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8380 | /* This function is only used for 16-bit relocation fields. | |
8381 | To make the macro code simpler, treat an unrelocated value | |
8382 | in the same way as BFD_RELOC_LO16. */ | |
8383 | if (r[0] == BFD_RELOC_UNUSED) | |
8384 | r[0] = BFD_RELOC_LO16; | |
8385 | } | |
6e1304d8 RS |
8386 | } |
8387 | ||
252b5132 RH |
8388 | /* Build an instruction created by a macro expansion. This is passed |
8389 | a pointer to the count of instructions created so far, an | |
8390 | expression, the name of the instruction to build, an operand format | |
8391 | string, and corresponding arguments. */ | |
8392 | ||
252b5132 | 8393 | static void |
67c0d1eb | 8394 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8395 | { |
df58fc94 | 8396 | const struct mips_opcode *mo = NULL; |
f6688943 | 8397 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8398 | const struct mips_opcode *amo; |
e077a1c8 | 8399 | const struct mips_operand *operand; |
df58fc94 RS |
8400 | struct hash_control *hash; |
8401 | struct mips_cl_insn insn; | |
252b5132 | 8402 | va_list args; |
e077a1c8 | 8403 | unsigned int uval; |
252b5132 | 8404 | |
252b5132 | 8405 | va_start (args, fmt); |
252b5132 | 8406 | |
252b5132 RH |
8407 | if (mips_opts.mips16) |
8408 | { | |
03ea81db | 8409 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8410 | va_end (args); |
8411 | return; | |
8412 | } | |
8413 | ||
f6688943 TS |
8414 | r[0] = BFD_RELOC_UNUSED; |
8415 | r[1] = BFD_RELOC_UNUSED; | |
8416 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8417 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8418 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8419 | gas_assert (amo); | |
8420 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8421 | |
df58fc94 | 8422 | do |
8b082fb1 TS |
8423 | { |
8424 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
8425 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
8426 | We try to match an instruction that fulfils the branch delay | |
8427 | slot instruction length requirement (if any) of the previous | |
8428 | instruction. While doing this we record the first instruction | |
8429 | seen that matches all the other conditions and use it anyway | |
8430 | if the requirement cannot be met; we will issue an appropriate | |
8431 | warning later on. */ | |
8432 | if (strcmp (fmt, amo->args) == 0 | |
8433 | && amo->pinfo != INSN_MACRO | |
8434 | && is_opcode_valid (amo) | |
8435 | && is_size_valid (amo)) | |
8436 | { | |
8437 | if (is_delay_slot_valid (amo)) | |
8438 | { | |
8439 | mo = amo; | |
8440 | break; | |
8441 | } | |
8442 | else if (!mo) | |
8443 | mo = amo; | |
8444 | } | |
8b082fb1 | 8445 | |
df58fc94 RS |
8446 | ++amo; |
8447 | gas_assert (amo->name); | |
252b5132 | 8448 | } |
df58fc94 | 8449 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8450 | |
df58fc94 | 8451 | gas_assert (mo); |
1e915849 | 8452 | create_insn (&insn, mo); |
e077a1c8 | 8453 | for (; *fmt; ++fmt) |
252b5132 | 8454 | { |
e077a1c8 | 8455 | switch (*fmt) |
252b5132 | 8456 | { |
252b5132 RH |
8457 | case ',': |
8458 | case '(': | |
8459 | case ')': | |
252b5132 | 8460 | case 'z': |
e077a1c8 | 8461 | break; |
252b5132 RH |
8462 | |
8463 | case 'i': | |
8464 | case 'j': | |
6e1304d8 | 8465 | macro_read_relocs (&args, r); |
9c2799c2 | 8466 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8467 | || *r == BFD_RELOC_MIPS_HIGHER |
8468 | || *r == BFD_RELOC_HI16_S | |
8469 | || *r == BFD_RELOC_LO16 | |
8470 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 8471 | break; |
e391c024 RS |
8472 | |
8473 | case 'o': | |
8474 | macro_read_relocs (&args, r); | |
e077a1c8 | 8475 | break; |
252b5132 RH |
8476 | |
8477 | case 'u': | |
6e1304d8 | 8478 | macro_read_relocs (&args, r); |
9c2799c2 | 8479 | gas_assert (ep != NULL |
90ecf173 MR |
8480 | && (ep->X_op == O_constant |
8481 | || (ep->X_op == O_symbol | |
8482 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8483 | || *r == BFD_RELOC_HI16_S | |
8484 | || *r == BFD_RELOC_HI16 | |
8485 | || *r == BFD_RELOC_GPREL16 | |
8486 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8487 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8488 | break; |
252b5132 RH |
8489 | |
8490 | case 'p': | |
9c2799c2 | 8491 | gas_assert (ep != NULL); |
bad36eac | 8492 | |
252b5132 RH |
8493 | /* |
8494 | * This allows macro() to pass an immediate expression for | |
8495 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8496 | * |
8497 | * We don't allow branch relaxation for these branches, as | |
8498 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8499 | */ |
8500 | if (ep->X_op == O_constant) | |
8501 | { | |
df58fc94 RS |
8502 | /* For microMIPS we always use relocations for branches. |
8503 | So we should not resolve immediate values. */ | |
8504 | gas_assert (!mips_opts.micromips); | |
8505 | ||
bad36eac DJ |
8506 | if ((ep->X_add_number & 3) != 0) |
8507 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8508 | (unsigned long) ep->X_add_number); | |
8509 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8510 | as_bad (_("branch address range overflow (0x%lx)"), | |
8511 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8512 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8513 | ep = NULL; | |
8514 | } | |
8515 | else | |
0b25d3e6 | 8516 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8517 | break; |
252b5132 RH |
8518 | |
8519 | case 'a': | |
9c2799c2 | 8520 | gas_assert (ep != NULL); |
f6688943 | 8521 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8522 | break; |
d43b4baf | 8523 | |
252b5132 | 8524 | default: |
e077a1c8 RS |
8525 | operand = (mips_opts.micromips |
8526 | ? decode_micromips_operand (fmt) | |
8527 | : decode_mips_operand (fmt)); | |
8528 | if (!operand) | |
8529 | abort (); | |
8530 | ||
8531 | uval = va_arg (args, int); | |
8532 | if (operand->type == OP_CLO_CLZ_DEST) | |
8533 | uval |= (uval << 5); | |
8534 | insn_insert_operand (&insn, operand, uval); | |
8535 | ||
7361da2c | 8536 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8537 | ++fmt; |
8538 | break; | |
252b5132 | 8539 | } |
252b5132 RH |
8540 | } |
8541 | va_end (args); | |
9c2799c2 | 8542 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8543 | |
df58fc94 | 8544 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8545 | } |
8546 | ||
8547 | static void | |
67c0d1eb | 8548 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8549 | va_list *args) |
252b5132 | 8550 | { |
1e915849 | 8551 | struct mips_opcode *mo; |
252b5132 | 8552 | struct mips_cl_insn insn; |
e077a1c8 | 8553 | const struct mips_operand *operand; |
f6688943 TS |
8554 | bfd_reloc_code_real_type r[3] |
8555 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8556 | |
1e915849 | 8557 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8558 | gas_assert (mo); |
8559 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8560 | |
1e915849 | 8561 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8562 | { |
1e915849 | 8563 | ++mo; |
9c2799c2 NC |
8564 | gas_assert (mo->name); |
8565 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8566 | } |
8567 | ||
1e915849 | 8568 | create_insn (&insn, mo); |
e077a1c8 | 8569 | for (; *fmt; ++fmt) |
252b5132 RH |
8570 | { |
8571 | int c; | |
8572 | ||
e077a1c8 | 8573 | c = *fmt; |
252b5132 RH |
8574 | switch (c) |
8575 | { | |
252b5132 RH |
8576 | case ',': |
8577 | case '(': | |
8578 | case ')': | |
e077a1c8 | 8579 | break; |
252b5132 RH |
8580 | |
8581 | case '0': | |
8582 | case 'S': | |
8583 | case 'P': | |
8584 | case 'R': | |
e077a1c8 | 8585 | break; |
252b5132 RH |
8586 | |
8587 | case '<': | |
8588 | case '>': | |
8589 | case '4': | |
8590 | case '5': | |
8591 | case 'H': | |
8592 | case 'W': | |
8593 | case 'D': | |
8594 | case 'j': | |
8595 | case '8': | |
8596 | case 'V': | |
8597 | case 'C': | |
8598 | case 'U': | |
8599 | case 'k': | |
8600 | case 'K': | |
8601 | case 'p': | |
8602 | case 'q': | |
8603 | { | |
b886a2ab RS |
8604 | offsetT value; |
8605 | ||
9c2799c2 | 8606 | gas_assert (ep != NULL); |
252b5132 RH |
8607 | |
8608 | if (ep->X_op != O_constant) | |
874e8986 | 8609 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8610 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8611 | { |
b886a2ab | 8612 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8613 | ep = NULL; |
f6688943 | 8614 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8615 | } |
8616 | } | |
e077a1c8 | 8617 | break; |
252b5132 | 8618 | |
e077a1c8 RS |
8619 | default: |
8620 | operand = decode_mips16_operand (c, FALSE); | |
8621 | if (!operand) | |
8622 | abort (); | |
252b5132 | 8623 | |
4a06e5a2 | 8624 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8625 | break; |
8626 | } | |
252b5132 RH |
8627 | } |
8628 | ||
9c2799c2 | 8629 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8630 | |
df58fc94 | 8631 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8632 | } |
8633 | ||
438c16b8 TS |
8634 | /* |
8635 | * Generate a "jalr" instruction with a relocation hint to the called | |
8636 | * function. This occurs in NewABI PIC code. | |
8637 | */ | |
8638 | static void | |
df58fc94 | 8639 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 8640 | { |
df58fc94 RS |
8641 | static const bfd_reloc_code_real_type jalr_relocs[2] |
8642 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
8643 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
8644 | const char *jalr; | |
685736be | 8645 | char *f = NULL; |
b34976b6 | 8646 | |
1180b5a4 | 8647 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 8648 | { |
cc3d92a5 | 8649 | frag_grow (8); |
f21f8242 AO |
8650 | f = frag_more (0); |
8651 | } | |
2906b037 | 8652 | if (mips_opts.micromips) |
df58fc94 | 8653 | { |
833794fc MR |
8654 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
8655 | ? "jalr" : "jalrs"); | |
e64af278 | 8656 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 8657 | || mips_opts.insn32 |
e64af278 | 8658 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
8659 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
8660 | else | |
8661 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
8662 | } | |
2906b037 MR |
8663 | else |
8664 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 8665 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 8666 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
8667 | } |
8668 | ||
252b5132 RH |
8669 | /* |
8670 | * Generate a "lui" instruction. | |
8671 | */ | |
8672 | static void | |
67c0d1eb | 8673 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 8674 | { |
9c2799c2 | 8675 | gas_assert (! mips_opts.mips16); |
252b5132 | 8676 | |
df58fc94 | 8677 | if (ep->X_op != O_constant) |
252b5132 | 8678 | { |
9c2799c2 | 8679 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
8680 | /* _gp_disp is a special case, used from s_cpload. |
8681 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 8682 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 8683 | || (! HAVE_NEWABI |
aa6975fb ILT |
8684 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
8685 | || (! mips_in_shared | |
bbe506e8 TS |
8686 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
8687 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
8688 | } |
8689 | ||
df58fc94 | 8690 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
8691 | } |
8692 | ||
885add95 CD |
8693 | /* Generate a sequence of instructions to do a load or store from a constant |
8694 | offset off of a base register (breg) into/from a target register (treg), | |
8695 | using AT if necessary. */ | |
8696 | static void | |
67c0d1eb RS |
8697 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
8698 | int treg, int breg, int dbl) | |
885add95 | 8699 | { |
9c2799c2 | 8700 | gas_assert (ep->X_op == O_constant); |
885add95 | 8701 | |
256ab948 | 8702 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
8703 | if (!dbl) |
8704 | normalize_constant_expr (ep); | |
256ab948 | 8705 | |
67c1ffbe | 8706 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 8707 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
8708 | as_warn (_("operand overflow")); |
8709 | ||
8710 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
8711 | { | |
8712 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 8713 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
8714 | } |
8715 | else | |
8716 | { | |
8717 | /* 32-bit offset, need multiple instructions and AT, like: | |
8718 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
8719 | addu $tempreg,$tempreg,$breg | |
8720 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
8721 | to handle the complete offset. */ | |
67c0d1eb RS |
8722 | macro_build_lui (ep, AT); |
8723 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
8724 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 8725 | |
741fe287 | 8726 | if (!mips_opts.at) |
1661c76c | 8727 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
8728 | } |
8729 | } | |
8730 | ||
252b5132 RH |
8731 | /* set_at() |
8732 | * Generates code to set the $at register to true (one) | |
8733 | * if reg is less than the immediate expression. | |
8734 | */ | |
8735 | static void | |
67c0d1eb | 8736 | set_at (int reg, int unsignedp) |
252b5132 | 8737 | { |
b0e6f033 | 8738 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 8739 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
8740 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
8741 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
8742 | else |
8743 | { | |
bad1aba3 | 8744 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 8745 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
8746 | } |
8747 | } | |
8748 | ||
252b5132 RH |
8749 | /* Count the leading zeroes by performing a binary chop. This is a |
8750 | bulky bit of source, but performance is a LOT better for the | |
8751 | majority of values than a simple loop to count the bits: | |
8752 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
8753 | if ((v) & (1 << (31 - lcnt))) | |
8754 | break; | |
8755 | However it is not code size friendly, and the gain will drop a bit | |
8756 | on certain cached systems. | |
8757 | */ | |
8758 | #define COUNT_TOP_ZEROES(v) \ | |
8759 | (((v) & ~0xffff) == 0 \ | |
8760 | ? ((v) & ~0xff) == 0 \ | |
8761 | ? ((v) & ~0xf) == 0 \ | |
8762 | ? ((v) & ~0x3) == 0 \ | |
8763 | ? ((v) & ~0x1) == 0 \ | |
8764 | ? !(v) \ | |
8765 | ? 32 \ | |
8766 | : 31 \ | |
8767 | : 30 \ | |
8768 | : ((v) & ~0x7) == 0 \ | |
8769 | ? 29 \ | |
8770 | : 28 \ | |
8771 | : ((v) & ~0x3f) == 0 \ | |
8772 | ? ((v) & ~0x1f) == 0 \ | |
8773 | ? 27 \ | |
8774 | : 26 \ | |
8775 | : ((v) & ~0x7f) == 0 \ | |
8776 | ? 25 \ | |
8777 | : 24 \ | |
8778 | : ((v) & ~0xfff) == 0 \ | |
8779 | ? ((v) & ~0x3ff) == 0 \ | |
8780 | ? ((v) & ~0x1ff) == 0 \ | |
8781 | ? 23 \ | |
8782 | : 22 \ | |
8783 | : ((v) & ~0x7ff) == 0 \ | |
8784 | ? 21 \ | |
8785 | : 20 \ | |
8786 | : ((v) & ~0x3fff) == 0 \ | |
8787 | ? ((v) & ~0x1fff) == 0 \ | |
8788 | ? 19 \ | |
8789 | : 18 \ | |
8790 | : ((v) & ~0x7fff) == 0 \ | |
8791 | ? 17 \ | |
8792 | : 16 \ | |
8793 | : ((v) & ~0xffffff) == 0 \ | |
8794 | ? ((v) & ~0xfffff) == 0 \ | |
8795 | ? ((v) & ~0x3ffff) == 0 \ | |
8796 | ? ((v) & ~0x1ffff) == 0 \ | |
8797 | ? 15 \ | |
8798 | : 14 \ | |
8799 | : ((v) & ~0x7ffff) == 0 \ | |
8800 | ? 13 \ | |
8801 | : 12 \ | |
8802 | : ((v) & ~0x3fffff) == 0 \ | |
8803 | ? ((v) & ~0x1fffff) == 0 \ | |
8804 | ? 11 \ | |
8805 | : 10 \ | |
8806 | : ((v) & ~0x7fffff) == 0 \ | |
8807 | ? 9 \ | |
8808 | : 8 \ | |
8809 | : ((v) & ~0xfffffff) == 0 \ | |
8810 | ? ((v) & ~0x3ffffff) == 0 \ | |
8811 | ? ((v) & ~0x1ffffff) == 0 \ | |
8812 | ? 7 \ | |
8813 | : 6 \ | |
8814 | : ((v) & ~0x7ffffff) == 0 \ | |
8815 | ? 5 \ | |
8816 | : 4 \ | |
8817 | : ((v) & ~0x3fffffff) == 0 \ | |
8818 | ? ((v) & ~0x1fffffff) == 0 \ | |
8819 | ? 3 \ | |
8820 | : 2 \ | |
8821 | : ((v) & ~0x7fffffff) == 0 \ | |
8822 | ? 1 \ | |
8823 | : 0) | |
8824 | ||
8825 | /* load_register() | |
67c1ffbe | 8826 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
8827 | * an absolute expression value into a register. |
8828 | */ | |
8829 | static void | |
67c0d1eb | 8830 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
8831 | { |
8832 | int freg; | |
8833 | expressionS hi32, lo32; | |
8834 | ||
8835 | if (ep->X_op != O_big) | |
8836 | { | |
9c2799c2 | 8837 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
8838 | |
8839 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
8840 | if (!dbl) |
8841 | normalize_constant_expr (ep); | |
256ab948 TS |
8842 | |
8843 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
8844 | { |
8845 | /* We can handle 16 bit signed values with an addiu to | |
8846 | $zero. No need to ever use daddiu here, since $zero and | |
8847 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 8848 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8849 | return; |
8850 | } | |
8851 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
8852 | { | |
8853 | /* We can handle 16 bit unsigned values with an ori to | |
8854 | $zero. */ | |
67c0d1eb | 8855 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8856 | return; |
8857 | } | |
256ab948 | 8858 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
8859 | { |
8860 | /* 32 bit values require an lui. */ | |
df58fc94 | 8861 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 8862 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 8863 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
8864 | return; |
8865 | } | |
8866 | } | |
8867 | ||
8868 | /* The value is larger than 32 bits. */ | |
8869 | ||
bad1aba3 | 8870 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 8871 | { |
55e08f71 NC |
8872 | char value[32]; |
8873 | ||
8874 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 8875 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 8876 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
8877 | return; |
8878 | } | |
8879 | ||
8880 | if (ep->X_op != O_big) | |
8881 | { | |
8882 | hi32 = *ep; | |
8883 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
8884 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
8885 | hi32.X_add_number &= 0xffffffff; | |
8886 | lo32 = *ep; | |
8887 | lo32.X_add_number &= 0xffffffff; | |
8888 | } | |
8889 | else | |
8890 | { | |
9c2799c2 | 8891 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
8892 | if (ep->X_add_number == 3) |
8893 | generic_bignum[3] = 0; | |
8894 | else if (ep->X_add_number > 4) | |
1661c76c | 8895 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
8896 | lo32.X_op = O_constant; |
8897 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
8898 | hi32.X_op = O_constant; | |
8899 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
8900 | } | |
8901 | ||
8902 | if (hi32.X_add_number == 0) | |
8903 | freg = 0; | |
8904 | else | |
8905 | { | |
8906 | int shift, bit; | |
8907 | unsigned long hi, lo; | |
8908 | ||
956cd1d6 | 8909 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
8910 | { |
8911 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
8912 | { | |
67c0d1eb | 8913 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
8914 | return; |
8915 | } | |
8916 | if (lo32.X_add_number & 0x80000000) | |
8917 | { | |
df58fc94 | 8918 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 8919 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 8920 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
8921 | return; |
8922 | } | |
8923 | } | |
252b5132 RH |
8924 | |
8925 | /* Check for 16bit shifted constant. We know that hi32 is | |
8926 | non-zero, so start the mask on the first bit of the hi32 | |
8927 | value. */ | |
8928 | shift = 17; | |
8929 | do | |
beae10d5 KH |
8930 | { |
8931 | unsigned long himask, lomask; | |
8932 | ||
8933 | if (shift < 32) | |
8934 | { | |
8935 | himask = 0xffff >> (32 - shift); | |
8936 | lomask = (0xffff << shift) & 0xffffffff; | |
8937 | } | |
8938 | else | |
8939 | { | |
8940 | himask = 0xffff << (shift - 32); | |
8941 | lomask = 0; | |
8942 | } | |
8943 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
8944 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
8945 | { | |
8946 | expressionS tmp; | |
8947 | ||
8948 | tmp.X_op = O_constant; | |
8949 | if (shift < 32) | |
8950 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
8951 | | (lo32.X_add_number >> shift)); | |
8952 | else | |
8953 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 8954 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 8955 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 8956 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
8957 | return; |
8958 | } | |
f9419b05 | 8959 | ++shift; |
beae10d5 KH |
8960 | } |
8961 | while (shift <= (64 - 16)); | |
252b5132 RH |
8962 | |
8963 | /* Find the bit number of the lowest one bit, and store the | |
8964 | shifted value in hi/lo. */ | |
8965 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
8966 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
8967 | if (lo != 0) | |
8968 | { | |
8969 | bit = 0; | |
8970 | while ((lo & 1) == 0) | |
8971 | { | |
8972 | lo >>= 1; | |
8973 | ++bit; | |
8974 | } | |
8975 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
8976 | hi >>= bit; | |
8977 | } | |
8978 | else | |
8979 | { | |
8980 | bit = 32; | |
8981 | while ((hi & 1) == 0) | |
8982 | { | |
8983 | hi >>= 1; | |
8984 | ++bit; | |
8985 | } | |
8986 | lo = hi; | |
8987 | hi = 0; | |
8988 | } | |
8989 | ||
8990 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
8991 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
8992 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
8993 | { |
8994 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 8995 | if (shift != 0) |
beae10d5 | 8996 | { |
252b5132 RH |
8997 | expressionS tmp; |
8998 | ||
8999 | /* This instruction will set the register to be all | |
9000 | ones. */ | |
beae10d5 KH |
9001 | tmp.X_op = O_constant; |
9002 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9003 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9004 | if (bit != 0) |
9005 | { | |
9006 | bit += shift; | |
df58fc94 | 9007 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9008 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9009 | } |
df58fc94 | 9010 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9011 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9012 | return; |
9013 | } | |
9014 | } | |
252b5132 RH |
9015 | |
9016 | /* Sign extend hi32 before calling load_register, because we can | |
9017 | generally get better code when we load a sign extended value. */ | |
9018 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9019 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9020 | load_register (reg, &hi32, 0); |
252b5132 RH |
9021 | freg = reg; |
9022 | } | |
9023 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9024 | { | |
9025 | if (freg != 0) | |
9026 | { | |
df58fc94 | 9027 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9028 | freg = reg; |
9029 | } | |
9030 | } | |
9031 | else | |
9032 | { | |
9033 | expressionS mid16; | |
9034 | ||
956cd1d6 | 9035 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9036 | { |
df58fc94 RS |
9037 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9038 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9039 | return; |
9040 | } | |
252b5132 RH |
9041 | |
9042 | if (freg != 0) | |
9043 | { | |
df58fc94 | 9044 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9045 | freg = reg; |
9046 | } | |
9047 | mid16 = lo32; | |
9048 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9049 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9050 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9051 | freg = reg; |
9052 | } | |
9053 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9054 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9055 | } |
9056 | ||
269137b2 TS |
9057 | static inline void |
9058 | load_delay_nop (void) | |
9059 | { | |
9060 | if (!gpr_interlocks) | |
9061 | macro_build (NULL, "nop", ""); | |
9062 | } | |
9063 | ||
252b5132 RH |
9064 | /* Load an address into a register. */ |
9065 | ||
9066 | static void | |
67c0d1eb | 9067 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9068 | { |
252b5132 RH |
9069 | if (ep->X_op != O_constant |
9070 | && ep->X_op != O_symbol) | |
9071 | { | |
9072 | as_bad (_("expression too complex")); | |
9073 | ep->X_op = O_constant; | |
9074 | } | |
9075 | ||
9076 | if (ep->X_op == O_constant) | |
9077 | { | |
67c0d1eb | 9078 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9079 | return; |
9080 | } | |
9081 | ||
9082 | if (mips_pic == NO_PIC) | |
9083 | { | |
9084 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9085 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9086 | Otherwise we want |
9087 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9088 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9089 | If we have an addend, we always use the latter form. |
76b3015f | 9090 | |
d6bc6245 TS |
9091 | With 64bit address space and a usable $at we want |
9092 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9093 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9094 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9095 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9096 | dsll32 $reg,0 | |
3a482fd5 | 9097 | daddu $reg,$reg,$at |
76b3015f | 9098 | |
c03099e6 | 9099 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9100 | on superscalar processors. |
9101 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9102 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9103 | dsll $reg,16 | |
9104 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9105 | dsll $reg,16 | |
9106 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9107 | |
9108 | For GP relative symbols in 64bit address space we can use | |
9109 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9110 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9111 | { |
6caf9ef4 TS |
9112 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9113 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9114 | { | |
9115 | relax_start (ep->X_add_symbol); | |
9116 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9117 | mips_gp_register, BFD_RELOC_GPREL16); | |
9118 | relax_switch (); | |
9119 | } | |
d6bc6245 | 9120 | |
741fe287 | 9121 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9122 | { |
df58fc94 RS |
9123 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9124 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9125 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9126 | BFD_RELOC_MIPS_HIGHER); | |
9127 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9128 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9129 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9130 | *used_at = 1; |
9131 | } | |
9132 | else | |
9133 | { | |
df58fc94 | 9134 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9135 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9136 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9137 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9138 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9139 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9140 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9141 | } |
6caf9ef4 TS |
9142 | |
9143 | if (mips_relax.sequence) | |
9144 | relax_end (); | |
d6bc6245 | 9145 | } |
252b5132 RH |
9146 | else |
9147 | { | |
d6bc6245 | 9148 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9149 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9150 | { |
4d7206a2 | 9151 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9152 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9153 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9154 | relax_switch (); |
d6bc6245 | 9155 | } |
67c0d1eb RS |
9156 | macro_build_lui (ep, reg); |
9157 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9158 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9159 | if (mips_relax.sequence) |
9160 | relax_end (); | |
d6bc6245 | 9161 | } |
252b5132 | 9162 | } |
0a44bf69 | 9163 | else if (!mips_big_got) |
252b5132 RH |
9164 | { |
9165 | expressionS ex; | |
9166 | ||
9167 | /* If this is a reference to an external symbol, we want | |
9168 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9169 | Otherwise we want | |
9170 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9171 | nop | |
9172 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9173 | If there is a constant, it must be added in after. |
9174 | ||
ed6fb7bd | 9175 | If we have NewABI, we want |
f5040a92 AO |
9176 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9177 | unless we're referencing a global symbol with a non-zero | |
9178 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9179 | if (HAVE_NEWABI) |
9180 | { | |
f5040a92 AO |
9181 | if (ep->X_add_number) |
9182 | { | |
4d7206a2 | 9183 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9184 | ep->X_add_number = 0; |
4d7206a2 | 9185 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9186 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9187 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9188 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9189 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9190 | ex.X_op = O_constant; | |
67c0d1eb | 9191 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9192 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9193 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9194 | relax_switch (); |
f5040a92 | 9195 | } |
67c0d1eb | 9196 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9197 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9198 | if (mips_relax.sequence) |
9199 | relax_end (); | |
ed6fb7bd SC |
9200 | } |
9201 | else | |
9202 | { | |
f5040a92 AO |
9203 | ex.X_add_number = ep->X_add_number; |
9204 | ep->X_add_number = 0; | |
67c0d1eb RS |
9205 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9206 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9207 | load_delay_nop (); |
4d7206a2 RS |
9208 | relax_start (ep->X_add_symbol); |
9209 | relax_switch (); | |
67c0d1eb | 9210 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9211 | BFD_RELOC_LO16); |
4d7206a2 | 9212 | relax_end (); |
ed6fb7bd | 9213 | |
f5040a92 AO |
9214 | if (ex.X_add_number != 0) |
9215 | { | |
9216 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9217 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9218 | ex.X_op = O_constant; | |
67c0d1eb | 9219 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9220 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9221 | } |
252b5132 RH |
9222 | } |
9223 | } | |
0a44bf69 | 9224 | else if (mips_big_got) |
252b5132 RH |
9225 | { |
9226 | expressionS ex; | |
252b5132 RH |
9227 | |
9228 | /* This is the large GOT case. If this is a reference to an | |
9229 | external symbol, we want | |
9230 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9231 | addu $reg,$reg,$gp | |
9232 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9233 | |
9234 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9235 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9236 | nop | |
9237 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9238 | If there is a constant, it must be added in after. |
f5040a92 AO |
9239 | |
9240 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9241 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9242 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9243 | */ |
438c16b8 TS |
9244 | if (HAVE_NEWABI) |
9245 | { | |
4d7206a2 | 9246 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9247 | ep->X_add_number = 0; |
4d7206a2 | 9248 | relax_start (ep->X_add_symbol); |
df58fc94 | 9249 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9251 | reg, reg, mips_gp_register); | |
9252 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9253 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9254 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9255 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9256 | else if (ex.X_add_number) | |
9257 | { | |
9258 | ex.X_op = O_constant; | |
67c0d1eb RS |
9259 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9260 | BFD_RELOC_LO16); | |
f5040a92 AO |
9261 | } |
9262 | ||
9263 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9264 | relax_switch (); |
67c0d1eb | 9265 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9266 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9267 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9268 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9269 | relax_end (); |
438c16b8 | 9270 | } |
252b5132 | 9271 | else |
438c16b8 | 9272 | { |
f5040a92 AO |
9273 | ex.X_add_number = ep->X_add_number; |
9274 | ep->X_add_number = 0; | |
4d7206a2 | 9275 | relax_start (ep->X_add_symbol); |
df58fc94 | 9276 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9277 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9278 | reg, reg, mips_gp_register); | |
9279 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9280 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9281 | relax_switch (); |
9282 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9283 | { |
9284 | /* We need a nop before loading from $gp. This special | |
9285 | check is required because the lui which starts the main | |
9286 | instruction stream does not refer to $gp, and so will not | |
9287 | insert the nop which may be required. */ | |
67c0d1eb | 9288 | macro_build (NULL, "nop", ""); |
438c16b8 | 9289 | } |
67c0d1eb | 9290 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9291 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9292 | load_delay_nop (); |
67c0d1eb | 9293 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9294 | BFD_RELOC_LO16); |
4d7206a2 | 9295 | relax_end (); |
438c16b8 | 9296 | |
f5040a92 AO |
9297 | if (ex.X_add_number != 0) |
9298 | { | |
9299 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9300 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9301 | ex.X_op = O_constant; | |
67c0d1eb RS |
9302 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9303 | BFD_RELOC_LO16); | |
f5040a92 | 9304 | } |
252b5132 RH |
9305 | } |
9306 | } | |
252b5132 RH |
9307 | else |
9308 | abort (); | |
8fc2e39e | 9309 | |
741fe287 | 9310 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9311 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9312 | } |
9313 | ||
ea1fb5dc RS |
9314 | /* Move the contents of register SOURCE into register DEST. */ |
9315 | ||
9316 | static void | |
67c0d1eb | 9317 | move_register (int dest, int source) |
ea1fb5dc | 9318 | { |
df58fc94 RS |
9319 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9320 | instruction specifically requires a 32-bit one. */ | |
9321 | if (mips_opts.micromips | |
833794fc | 9322 | && !mips_opts.insn32 |
df58fc94 | 9323 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9324 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9325 | else |
40fc1451 | 9326 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9327 | } |
9328 | ||
4d7206a2 | 9329 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9330 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9331 | The two alternatives are: | |
4d7206a2 RS |
9332 | |
9333 | Global symbol Local sybmol | |
9334 | ------------- ------------ | |
9335 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9336 | ... ... | |
9337 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9338 | ||
9339 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9340 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9341 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9342 | |
9343 | static void | |
67c0d1eb | 9344 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9345 | { |
9346 | expressionS global; | |
9347 | ||
9348 | global = *local; | |
9349 | global.X_add_number = 0; | |
9350 | ||
9351 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9352 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9353 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9354 | relax_switch (); |
67c0d1eb RS |
9355 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9356 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9357 | relax_end (); |
9358 | } | |
9359 | ||
9360 | static void | |
67c0d1eb | 9361 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9362 | { |
9363 | expressionS global; | |
9364 | ||
9365 | global.X_op = O_constant; | |
9366 | global.X_op_symbol = NULL; | |
9367 | global.X_add_symbol = NULL; | |
9368 | global.X_add_number = local->X_add_number; | |
9369 | ||
9370 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9371 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9372 | dest, dest, BFD_RELOC_LO16); |
9373 | relax_switch (); | |
67c0d1eb | 9374 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9375 | relax_end (); |
9376 | } | |
9377 | ||
f6a22291 MR |
9378 | static void |
9379 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9380 | { | |
9381 | expressionS global; | |
9382 | int hold_mips_optimize; | |
9383 | ||
9384 | global.X_op = O_constant; | |
9385 | global.X_op_symbol = NULL; | |
9386 | global.X_add_symbol = NULL; | |
9387 | global.X_add_number = local->X_add_number; | |
9388 | ||
9389 | relax_start (local->X_add_symbol); | |
9390 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9391 | relax_switch (); | |
9392 | /* Set mips_optimize around the lui instruction to avoid | |
9393 | inserting an unnecessary nop after the lw. */ | |
9394 | hold_mips_optimize = mips_optimize; | |
9395 | mips_optimize = 2; | |
9396 | macro_build_lui (&global, tmp); | |
9397 | mips_optimize = hold_mips_optimize; | |
9398 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9399 | relax_end (); | |
9400 | ||
9401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9402 | } | |
9403 | ||
df58fc94 RS |
9404 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9405 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9406 | is its complementing branch with the original condition negated. | |
9407 | CALL is set if the original branch specified the link operation. | |
9408 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9409 | ||
9410 | Code like this is produced in the noreorder mode: | |
9411 | ||
9412 | BRNEG <args>, 1f | |
9413 | nop | |
9414 | b <sym> | |
9415 | delay slot (executed only if branch taken) | |
9416 | 1: | |
9417 | ||
9418 | or, if CALL is set: | |
9419 | ||
9420 | BRNEG <args>, 1f | |
9421 | nop | |
9422 | bal <sym> | |
9423 | delay slot (executed only if branch taken) | |
9424 | 1: | |
9425 | ||
9426 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9427 | so code produced is simply: | |
9428 | ||
9429 | BR <args>, <sym> | |
9430 | nop | |
9431 | ||
9432 | This function is used when producing code for the microMIPS ASE that | |
9433 | does not implement branch likely instructions in hardware. */ | |
9434 | ||
9435 | static void | |
9436 | macro_build_branch_likely (const char *br, const char *brneg, | |
9437 | int call, expressionS *ep, const char *fmt, | |
9438 | unsigned int sreg, unsigned int treg) | |
9439 | { | |
9440 | int noreorder = mips_opts.noreorder; | |
9441 | expressionS expr1; | |
9442 | ||
9443 | gas_assert (mips_opts.micromips); | |
9444 | start_noreorder (); | |
9445 | if (noreorder) | |
9446 | { | |
9447 | micromips_label_expr (&expr1); | |
9448 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9449 | macro_build (NULL, "nop", ""); | |
9450 | macro_build (ep, call ? "bal" : "b", "p"); | |
9451 | ||
9452 | /* Set to true so that append_insn adds a label. */ | |
9453 | emit_branch_likely_macro = TRUE; | |
9454 | } | |
9455 | else | |
9456 | { | |
9457 | macro_build (ep, br, fmt, sreg, treg); | |
9458 | macro_build (NULL, "nop", ""); | |
9459 | } | |
9460 | end_noreorder (); | |
9461 | } | |
9462 | ||
9463 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9464 | the condition code tested. EP specifies the branch target. */ | |
9465 | ||
9466 | static void | |
9467 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9468 | { | |
9469 | const int call = 0; | |
9470 | const char *brneg; | |
9471 | const char *br; | |
9472 | ||
9473 | switch (type) | |
9474 | { | |
9475 | case M_BC1FL: | |
9476 | br = "bc1f"; | |
9477 | brneg = "bc1t"; | |
9478 | break; | |
9479 | case M_BC1TL: | |
9480 | br = "bc1t"; | |
9481 | brneg = "bc1f"; | |
9482 | break; | |
9483 | case M_BC2FL: | |
9484 | br = "bc2f"; | |
9485 | brneg = "bc2t"; | |
9486 | break; | |
9487 | case M_BC2TL: | |
9488 | br = "bc2t"; | |
9489 | brneg = "bc2f"; | |
9490 | break; | |
9491 | default: | |
9492 | abort (); | |
9493 | } | |
9494 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9495 | } | |
9496 | ||
9497 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9498 | the register tested. EP specifies the branch target. */ | |
9499 | ||
9500 | static void | |
9501 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9502 | { | |
9503 | const char *brneg = NULL; | |
9504 | const char *br; | |
9505 | int call = 0; | |
9506 | ||
9507 | switch (type) | |
9508 | { | |
9509 | case M_BGEZ: | |
9510 | br = "bgez"; | |
9511 | break; | |
9512 | case M_BGEZL: | |
9513 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9514 | brneg = "bltz"; | |
9515 | break; | |
9516 | case M_BGEZALL: | |
9517 | gas_assert (mips_opts.micromips); | |
833794fc | 9518 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9519 | brneg = "bltz"; |
9520 | call = 1; | |
9521 | break; | |
9522 | case M_BGTZ: | |
9523 | br = "bgtz"; | |
9524 | break; | |
9525 | case M_BGTZL: | |
9526 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9527 | brneg = "blez"; | |
9528 | break; | |
9529 | case M_BLEZ: | |
9530 | br = "blez"; | |
9531 | break; | |
9532 | case M_BLEZL: | |
9533 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9534 | brneg = "bgtz"; | |
9535 | break; | |
9536 | case M_BLTZ: | |
9537 | br = "bltz"; | |
9538 | break; | |
9539 | case M_BLTZL: | |
9540 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9541 | brneg = "bgez"; | |
9542 | break; | |
9543 | case M_BLTZALL: | |
9544 | gas_assert (mips_opts.micromips); | |
833794fc | 9545 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9546 | brneg = "bgez"; |
9547 | call = 1; | |
9548 | break; | |
9549 | default: | |
9550 | abort (); | |
9551 | } | |
9552 | if (mips_opts.micromips && brneg) | |
9553 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9554 | else | |
9555 | macro_build (ep, br, "s,p", sreg); | |
9556 | } | |
9557 | ||
9558 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9559 | TREG as the registers tested. EP specifies the branch target. */ | |
9560 | ||
9561 | static void | |
9562 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9563 | unsigned int sreg, unsigned int treg) | |
9564 | { | |
9565 | const char *brneg = NULL; | |
9566 | const int call = 0; | |
9567 | const char *br; | |
9568 | ||
9569 | switch (type) | |
9570 | { | |
9571 | case M_BEQ: | |
9572 | case M_BEQ_I: | |
9573 | br = "beq"; | |
9574 | break; | |
9575 | case M_BEQL: | |
9576 | case M_BEQL_I: | |
9577 | br = mips_opts.micromips ? "beq" : "beql"; | |
9578 | brneg = "bne"; | |
9579 | break; | |
9580 | case M_BNE: | |
9581 | case M_BNE_I: | |
9582 | br = "bne"; | |
9583 | break; | |
9584 | case M_BNEL: | |
9585 | case M_BNEL_I: | |
9586 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9587 | brneg = "beq"; | |
9588 | break; | |
9589 | default: | |
9590 | abort (); | |
9591 | } | |
9592 | if (mips_opts.micromips && brneg) | |
9593 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9594 | else | |
9595 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9596 | } | |
9597 | ||
f2ae14a1 RS |
9598 | /* Return the high part that should be loaded in order to make the low |
9599 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9600 | ||
9601 | static offsetT | |
9602 | offset_high_part (offsetT value, unsigned int offbits) | |
9603 | { | |
9604 | offsetT bias; | |
9605 | addressT low_mask; | |
9606 | ||
9607 | if (offbits == 0) | |
9608 | return value; | |
9609 | bias = 1 << (offbits - 1); | |
9610 | low_mask = bias * 2 - 1; | |
9611 | return (value + bias) & ~low_mask; | |
9612 | } | |
9613 | ||
9614 | /* Return true if the value stored in offset_expr and offset_reloc | |
9615 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9616 | amount that the caller wants to add without inducing overflow | |
9617 | and ALIGN is the known alignment of the value in bytes. */ | |
9618 | ||
9619 | static bfd_boolean | |
9620 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9621 | { | |
9622 | if (offbits == 16) | |
9623 | { | |
9624 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9625 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
9626 | return TRUE; | |
9627 | ||
9628 | /* These relocations are guaranteed not to overflow in correct links. */ | |
9629 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
9630 | || gprel16_reloc_p (*offset_reloc)) | |
9631 | return TRUE; | |
9632 | } | |
9633 | if (offset_expr.X_op == O_constant | |
9634 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
9635 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
9636 | return TRUE; | |
9637 | return FALSE; | |
9638 | } | |
9639 | ||
252b5132 RH |
9640 | /* |
9641 | * Build macros | |
9642 | * This routine implements the seemingly endless macro or synthesized | |
9643 | * instructions and addressing modes in the mips assembly language. Many | |
9644 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 9645 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
9646 | * this verbose method. Others are not simple macros but are more like |
9647 | * optimizing code generation. | |
9648 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 9649 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
9650 | * The ensuing load upper instructions are ommited. This implies some kind |
9651 | * of global optimization. We currently only optimize within a single macro. | |
9652 | * For many of the load and store macros if the address is specified as a | |
9653 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
9654 | * first load register 'at' with zero and use it as the base register. The | |
9655 | * mips assembler simply uses register $zero. Just one tiny optimization | |
9656 | * we're missing. | |
9657 | */ | |
9658 | static void | |
833794fc | 9659 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 9660 | { |
c0ebe874 RS |
9661 | const struct mips_operand_array *operands; |
9662 | unsigned int breg, i; | |
741fe287 | 9663 | unsigned int tempreg; |
252b5132 | 9664 | int mask; |
43841e91 | 9665 | int used_at = 0; |
df58fc94 | 9666 | expressionS label_expr; |
252b5132 | 9667 | expressionS expr1; |
df58fc94 | 9668 | expressionS *ep; |
252b5132 RH |
9669 | const char *s; |
9670 | const char *s2; | |
9671 | const char *fmt; | |
9672 | int likely = 0; | |
252b5132 | 9673 | int coproc = 0; |
7f3c4072 | 9674 | int offbits = 16; |
1abe91b1 | 9675 | int call = 0; |
df58fc94 RS |
9676 | int jals = 0; |
9677 | int dbl = 0; | |
9678 | int imm = 0; | |
9679 | int ust = 0; | |
9680 | int lp = 0; | |
f2ae14a1 | 9681 | bfd_boolean large_offset; |
252b5132 | 9682 | int off; |
252b5132 | 9683 | int hold_mips_optimize; |
f2ae14a1 | 9684 | unsigned int align; |
c0ebe874 | 9685 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 9686 | |
9c2799c2 | 9687 | gas_assert (! mips_opts.mips16); |
252b5132 | 9688 | |
c0ebe874 RS |
9689 | operands = insn_operands (ip); |
9690 | for (i = 0; i < MAX_OPERANDS; i++) | |
9691 | if (operands->operand[i]) | |
9692 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
9693 | else | |
9694 | op[i] = -1; | |
9695 | ||
252b5132 RH |
9696 | mask = ip->insn_mo->mask; |
9697 | ||
df58fc94 RS |
9698 | label_expr.X_op = O_constant; |
9699 | label_expr.X_op_symbol = NULL; | |
9700 | label_expr.X_add_symbol = NULL; | |
9701 | label_expr.X_add_number = 0; | |
9702 | ||
252b5132 RH |
9703 | expr1.X_op = O_constant; |
9704 | expr1.X_op_symbol = NULL; | |
9705 | expr1.X_add_symbol = NULL; | |
9706 | expr1.X_add_number = 1; | |
f2ae14a1 | 9707 | align = 1; |
252b5132 RH |
9708 | |
9709 | switch (mask) | |
9710 | { | |
9711 | case M_DABS: | |
9712 | dbl = 1; | |
9713 | case M_ABS: | |
df58fc94 RS |
9714 | /* bgez $a0,1f |
9715 | move v0,$a0 | |
9716 | sub v0,$zero,$a0 | |
9717 | 1: | |
9718 | */ | |
252b5132 | 9719 | |
7d10b47d | 9720 | start_noreorder (); |
252b5132 | 9721 | |
df58fc94 RS |
9722 | if (mips_opts.micromips) |
9723 | micromips_label_expr (&label_expr); | |
9724 | else | |
9725 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9726 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
9727 | if (op[0] == op[1]) | |
a605d2b3 | 9728 | macro_build (NULL, "nop", ""); |
252b5132 | 9729 | else |
c0ebe874 RS |
9730 | move_register (op[0], op[1]); |
9731 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
9732 | if (mips_opts.micromips) |
9733 | micromips_add_label (); | |
252b5132 | 9734 | |
7d10b47d | 9735 | end_noreorder (); |
8fc2e39e | 9736 | break; |
252b5132 RH |
9737 | |
9738 | case M_ADD_I: | |
9739 | s = "addi"; | |
9740 | s2 = "add"; | |
9741 | goto do_addi; | |
9742 | case M_ADDU_I: | |
9743 | s = "addiu"; | |
9744 | s2 = "addu"; | |
9745 | goto do_addi; | |
9746 | case M_DADD_I: | |
9747 | dbl = 1; | |
9748 | s = "daddi"; | |
9749 | s2 = "dadd"; | |
df58fc94 RS |
9750 | if (!mips_opts.micromips) |
9751 | goto do_addi; | |
b0e6f033 | 9752 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
9753 | && imm_expr.X_add_number < 0x200) |
9754 | { | |
b0e6f033 RS |
9755 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
9756 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
9757 | break; |
9758 | } | |
9759 | goto do_addi_i; | |
252b5132 RH |
9760 | case M_DADDU_I: |
9761 | dbl = 1; | |
9762 | s = "daddiu"; | |
9763 | s2 = "daddu"; | |
9764 | do_addi: | |
b0e6f033 | 9765 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
9766 | && imm_expr.X_add_number < 0x8000) |
9767 | { | |
c0ebe874 | 9768 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 9769 | break; |
252b5132 | 9770 | } |
df58fc94 | 9771 | do_addi_i: |
8fc2e39e | 9772 | used_at = 1; |
67c0d1eb | 9773 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 9774 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
9775 | break; |
9776 | ||
9777 | case M_AND_I: | |
9778 | s = "andi"; | |
9779 | s2 = "and"; | |
9780 | goto do_bit; | |
9781 | case M_OR_I: | |
9782 | s = "ori"; | |
9783 | s2 = "or"; | |
9784 | goto do_bit; | |
9785 | case M_NOR_I: | |
9786 | s = ""; | |
9787 | s2 = "nor"; | |
9788 | goto do_bit; | |
9789 | case M_XOR_I: | |
9790 | s = "xori"; | |
9791 | s2 = "xor"; | |
9792 | do_bit: | |
b0e6f033 | 9793 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
9794 | && imm_expr.X_add_number < 0x10000) |
9795 | { | |
9796 | if (mask != M_NOR_I) | |
c0ebe874 | 9797 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
9798 | else |
9799 | { | |
67c0d1eb | 9800 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
9801 | op[0], op[1], BFD_RELOC_LO16); |
9802 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 9803 | } |
8fc2e39e | 9804 | break; |
252b5132 RH |
9805 | } |
9806 | ||
8fc2e39e | 9807 | used_at = 1; |
bad1aba3 | 9808 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 9809 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
9810 | break; |
9811 | ||
8b082fb1 TS |
9812 | case M_BALIGN: |
9813 | switch (imm_expr.X_add_number) | |
9814 | { | |
9815 | case 0: | |
9816 | macro_build (NULL, "nop", ""); | |
9817 | break; | |
9818 | case 2: | |
c0ebe874 | 9819 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 9820 | break; |
03f66e8a MR |
9821 | case 1: |
9822 | case 3: | |
c0ebe874 | 9823 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 9824 | (int) imm_expr.X_add_number); |
8b082fb1 | 9825 | break; |
03f66e8a MR |
9826 | default: |
9827 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
9828 | (unsigned long) imm_expr.X_add_number); | |
9829 | break; | |
8b082fb1 TS |
9830 | } |
9831 | break; | |
9832 | ||
df58fc94 RS |
9833 | case M_BC1FL: |
9834 | case M_BC1TL: | |
9835 | case M_BC2FL: | |
9836 | case M_BC2TL: | |
9837 | gas_assert (mips_opts.micromips); | |
9838 | macro_build_branch_ccl (mask, &offset_expr, | |
9839 | EXTRACT_OPERAND (1, BCC, *ip)); | |
9840 | break; | |
9841 | ||
252b5132 | 9842 | case M_BEQ_I: |
252b5132 | 9843 | case M_BEQL_I: |
252b5132 | 9844 | case M_BNE_I: |
252b5132 | 9845 | case M_BNEL_I: |
b0e6f033 | 9846 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 9847 | op[1] = 0; |
df58fc94 | 9848 | else |
252b5132 | 9849 | { |
c0ebe874 | 9850 | op[1] = AT; |
df58fc94 | 9851 | used_at = 1; |
bad1aba3 | 9852 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 9853 | } |
df58fc94 RS |
9854 | /* Fall through. */ |
9855 | case M_BEQL: | |
9856 | case M_BNEL: | |
c0ebe874 | 9857 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
9858 | break; |
9859 | ||
9860 | case M_BGEL: | |
9861 | likely = 1; | |
9862 | case M_BGE: | |
c0ebe874 RS |
9863 | if (op[1] == 0) |
9864 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
9865 | else if (op[0] == 0) | |
9866 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 9867 | else |
252b5132 | 9868 | { |
df58fc94 | 9869 | used_at = 1; |
c0ebe874 | 9870 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9871 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9872 | &offset_expr, AT, ZERO); | |
252b5132 | 9873 | } |
df58fc94 RS |
9874 | break; |
9875 | ||
9876 | case M_BGEZL: | |
9877 | case M_BGEZALL: | |
9878 | case M_BGTZL: | |
9879 | case M_BLEZL: | |
9880 | case M_BLTZL: | |
9881 | case M_BLTZALL: | |
c0ebe874 | 9882 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
9883 | break; |
9884 | ||
9885 | case M_BGTL_I: | |
9886 | likely = 1; | |
9887 | case M_BGT_I: | |
90ecf173 | 9888 | /* Check for > max integer. */ |
b0e6f033 | 9889 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
9890 | { |
9891 | do_false: | |
90ecf173 | 9892 | /* Result is always false. */ |
252b5132 | 9893 | if (! likely) |
a605d2b3 | 9894 | macro_build (NULL, "nop", ""); |
252b5132 | 9895 | else |
df58fc94 | 9896 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 9897 | break; |
252b5132 | 9898 | } |
f9419b05 | 9899 | ++imm_expr.X_add_number; |
252b5132 RH |
9900 | /* FALLTHROUGH */ |
9901 | case M_BGE_I: | |
9902 | case M_BGEL_I: | |
9903 | if (mask == M_BGEL_I) | |
9904 | likely = 1; | |
b0e6f033 | 9905 | if (imm_expr.X_add_number == 0) |
252b5132 | 9906 | { |
df58fc94 | 9907 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 9908 | &offset_expr, op[0]); |
8fc2e39e | 9909 | break; |
252b5132 | 9910 | } |
b0e6f033 | 9911 | if (imm_expr.X_add_number == 1) |
252b5132 | 9912 | { |
df58fc94 | 9913 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 9914 | &offset_expr, op[0]); |
8fc2e39e | 9915 | break; |
252b5132 | 9916 | } |
b0e6f033 | 9917 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
9918 | { |
9919 | do_true: | |
9920 | /* result is always true */ | |
1661c76c | 9921 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 9922 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 9923 | break; |
252b5132 | 9924 | } |
8fc2e39e | 9925 | used_at = 1; |
c0ebe874 | 9926 | set_at (op[0], 0); |
df58fc94 RS |
9927 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9928 | &offset_expr, AT, ZERO); | |
252b5132 RH |
9929 | break; |
9930 | ||
9931 | case M_BGEUL: | |
9932 | likely = 1; | |
9933 | case M_BGEU: | |
c0ebe874 | 9934 | if (op[1] == 0) |
252b5132 | 9935 | goto do_true; |
c0ebe874 | 9936 | else if (op[0] == 0) |
df58fc94 | 9937 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 9938 | &offset_expr, ZERO, op[1]); |
df58fc94 | 9939 | else |
252b5132 | 9940 | { |
df58fc94 | 9941 | used_at = 1; |
c0ebe874 | 9942 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
9943 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9944 | &offset_expr, AT, ZERO); | |
252b5132 | 9945 | } |
252b5132 RH |
9946 | break; |
9947 | ||
9948 | case M_BGTUL_I: | |
9949 | likely = 1; | |
9950 | case M_BGTU_I: | |
c0ebe874 | 9951 | if (op[0] == 0 |
bad1aba3 | 9952 | || (GPR_SIZE == 32 |
f01dc953 | 9953 | && imm_expr.X_add_number == -1)) |
252b5132 | 9954 | goto do_false; |
f9419b05 | 9955 | ++imm_expr.X_add_number; |
252b5132 RH |
9956 | /* FALLTHROUGH */ |
9957 | case M_BGEU_I: | |
9958 | case M_BGEUL_I: | |
9959 | if (mask == M_BGEUL_I) | |
9960 | likely = 1; | |
b0e6f033 | 9961 | if (imm_expr.X_add_number == 0) |
252b5132 | 9962 | goto do_true; |
b0e6f033 | 9963 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 9964 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 9965 | &offset_expr, op[0], ZERO); |
df58fc94 | 9966 | else |
252b5132 | 9967 | { |
df58fc94 | 9968 | used_at = 1; |
c0ebe874 | 9969 | set_at (op[0], 1); |
df58fc94 RS |
9970 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
9971 | &offset_expr, AT, ZERO); | |
252b5132 | 9972 | } |
252b5132 RH |
9973 | break; |
9974 | ||
9975 | case M_BGTL: | |
9976 | likely = 1; | |
9977 | case M_BGT: | |
c0ebe874 RS |
9978 | if (op[1] == 0) |
9979 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
9980 | else if (op[0] == 0) | |
9981 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 9982 | else |
252b5132 | 9983 | { |
df58fc94 | 9984 | used_at = 1; |
c0ebe874 | 9985 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
9986 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
9987 | &offset_expr, AT, ZERO); | |
252b5132 | 9988 | } |
252b5132 RH |
9989 | break; |
9990 | ||
9991 | case M_BGTUL: | |
9992 | likely = 1; | |
9993 | case M_BGTU: | |
c0ebe874 | 9994 | if (op[1] == 0) |
df58fc94 | 9995 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
9996 | &offset_expr, op[0], ZERO); |
9997 | else if (op[0] == 0) | |
df58fc94 RS |
9998 | goto do_false; |
9999 | else | |
252b5132 | 10000 | { |
df58fc94 | 10001 | used_at = 1; |
c0ebe874 | 10002 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10003 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10004 | &offset_expr, AT, ZERO); | |
252b5132 | 10005 | } |
252b5132 RH |
10006 | break; |
10007 | ||
10008 | case M_BLEL: | |
10009 | likely = 1; | |
10010 | case M_BLE: | |
c0ebe874 RS |
10011 | if (op[1] == 0) |
10012 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10013 | else if (op[0] == 0) | |
10014 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10015 | else |
252b5132 | 10016 | { |
df58fc94 | 10017 | used_at = 1; |
c0ebe874 | 10018 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10019 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10020 | &offset_expr, AT, ZERO); | |
252b5132 | 10021 | } |
252b5132 RH |
10022 | break; |
10023 | ||
10024 | case M_BLEL_I: | |
10025 | likely = 1; | |
10026 | case M_BLE_I: | |
b0e6f033 | 10027 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10028 | goto do_true; |
f9419b05 | 10029 | ++imm_expr.X_add_number; |
252b5132 RH |
10030 | /* FALLTHROUGH */ |
10031 | case M_BLT_I: | |
10032 | case M_BLTL_I: | |
10033 | if (mask == M_BLTL_I) | |
10034 | likely = 1; | |
b0e6f033 | 10035 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10036 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10037 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10038 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10039 | else |
252b5132 | 10040 | { |
df58fc94 | 10041 | used_at = 1; |
c0ebe874 | 10042 | set_at (op[0], 0); |
df58fc94 RS |
10043 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10044 | &offset_expr, AT, ZERO); | |
252b5132 | 10045 | } |
252b5132 RH |
10046 | break; |
10047 | ||
10048 | case M_BLEUL: | |
10049 | likely = 1; | |
10050 | case M_BLEU: | |
c0ebe874 | 10051 | if (op[1] == 0) |
df58fc94 | 10052 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10053 | &offset_expr, op[0], ZERO); |
10054 | else if (op[0] == 0) | |
df58fc94 RS |
10055 | goto do_true; |
10056 | else | |
252b5132 | 10057 | { |
df58fc94 | 10058 | used_at = 1; |
c0ebe874 | 10059 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10060 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10061 | &offset_expr, AT, ZERO); | |
252b5132 | 10062 | } |
252b5132 RH |
10063 | break; |
10064 | ||
10065 | case M_BLEUL_I: | |
10066 | likely = 1; | |
10067 | case M_BLEU_I: | |
c0ebe874 | 10068 | if (op[0] == 0 |
bad1aba3 | 10069 | || (GPR_SIZE == 32 |
f01dc953 | 10070 | && imm_expr.X_add_number == -1)) |
252b5132 | 10071 | goto do_true; |
f9419b05 | 10072 | ++imm_expr.X_add_number; |
252b5132 RH |
10073 | /* FALLTHROUGH */ |
10074 | case M_BLTU_I: | |
10075 | case M_BLTUL_I: | |
10076 | if (mask == M_BLTUL_I) | |
10077 | likely = 1; | |
b0e6f033 | 10078 | if (imm_expr.X_add_number == 0) |
252b5132 | 10079 | goto do_false; |
b0e6f033 | 10080 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10081 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10082 | &offset_expr, op[0], ZERO); |
df58fc94 | 10083 | else |
252b5132 | 10084 | { |
df58fc94 | 10085 | used_at = 1; |
c0ebe874 | 10086 | set_at (op[0], 1); |
df58fc94 RS |
10087 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10088 | &offset_expr, AT, ZERO); | |
252b5132 | 10089 | } |
252b5132 RH |
10090 | break; |
10091 | ||
10092 | case M_BLTL: | |
10093 | likely = 1; | |
10094 | case M_BLT: | |
c0ebe874 RS |
10095 | if (op[1] == 0) |
10096 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10097 | else if (op[0] == 0) | |
10098 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10099 | else |
252b5132 | 10100 | { |
df58fc94 | 10101 | used_at = 1; |
c0ebe874 | 10102 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10103 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10104 | &offset_expr, AT, ZERO); | |
252b5132 | 10105 | } |
252b5132 RH |
10106 | break; |
10107 | ||
10108 | case M_BLTUL: | |
10109 | likely = 1; | |
10110 | case M_BLTU: | |
c0ebe874 | 10111 | if (op[1] == 0) |
252b5132 | 10112 | goto do_false; |
c0ebe874 | 10113 | else if (op[0] == 0) |
df58fc94 | 10114 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10115 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10116 | else |
252b5132 | 10117 | { |
df58fc94 | 10118 | used_at = 1; |
c0ebe874 | 10119 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10120 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10121 | &offset_expr, AT, ZERO); | |
252b5132 | 10122 | } |
252b5132 RH |
10123 | break; |
10124 | ||
10125 | case M_DDIV_3: | |
10126 | dbl = 1; | |
10127 | case M_DIV_3: | |
10128 | s = "mflo"; | |
10129 | goto do_div3; | |
10130 | case M_DREM_3: | |
10131 | dbl = 1; | |
10132 | case M_REM_3: | |
10133 | s = "mfhi"; | |
10134 | do_div3: | |
c0ebe874 | 10135 | if (op[2] == 0) |
252b5132 | 10136 | { |
1661c76c | 10137 | as_warn (_("divide by zero")); |
252b5132 | 10138 | if (mips_trap) |
df58fc94 | 10139 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10140 | else |
df58fc94 | 10141 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10142 | break; |
252b5132 RH |
10143 | } |
10144 | ||
7d10b47d | 10145 | start_noreorder (); |
252b5132 RH |
10146 | if (mips_trap) |
10147 | { | |
c0ebe874 RS |
10148 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10149 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10150 | } |
10151 | else | |
10152 | { | |
df58fc94 RS |
10153 | if (mips_opts.micromips) |
10154 | micromips_label_expr (&label_expr); | |
10155 | else | |
10156 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10157 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10158 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10159 | macro_build (NULL, "break", BRK_FMT, 7); |
10160 | if (mips_opts.micromips) | |
10161 | micromips_add_label (); | |
252b5132 RH |
10162 | } |
10163 | expr1.X_add_number = -1; | |
8fc2e39e | 10164 | used_at = 1; |
f6a22291 | 10165 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10166 | if (mips_opts.micromips) |
10167 | micromips_label_expr (&label_expr); | |
10168 | else | |
10169 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10170 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10171 | if (dbl) |
10172 | { | |
10173 | expr1.X_add_number = 1; | |
f6a22291 | 10174 | load_register (AT, &expr1, dbl); |
df58fc94 | 10175 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10176 | } |
10177 | else | |
10178 | { | |
10179 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10180 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10181 | } |
10182 | if (mips_trap) | |
10183 | { | |
c0ebe874 | 10184 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10185 | /* We want to close the noreorder block as soon as possible, so |
10186 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10187 | end_noreorder (); |
252b5132 RH |
10188 | } |
10189 | else | |
10190 | { | |
df58fc94 RS |
10191 | if (mips_opts.micromips) |
10192 | micromips_label_expr (&label_expr); | |
10193 | else | |
10194 | label_expr.X_add_number = 8; | |
c0ebe874 | 10195 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10196 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10197 | |
10198 | /* We want to close the noreorder block as soon as possible, so | |
10199 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10200 | end_noreorder (); |
252b5132 | 10201 | |
df58fc94 | 10202 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10203 | } |
df58fc94 RS |
10204 | if (mips_opts.micromips) |
10205 | micromips_add_label (); | |
c0ebe874 | 10206 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10207 | break; |
10208 | ||
10209 | case M_DIV_3I: | |
10210 | s = "div"; | |
10211 | s2 = "mflo"; | |
10212 | goto do_divi; | |
10213 | case M_DIVU_3I: | |
10214 | s = "divu"; | |
10215 | s2 = "mflo"; | |
10216 | goto do_divi; | |
10217 | case M_REM_3I: | |
10218 | s = "div"; | |
10219 | s2 = "mfhi"; | |
10220 | goto do_divi; | |
10221 | case M_REMU_3I: | |
10222 | s = "divu"; | |
10223 | s2 = "mfhi"; | |
10224 | goto do_divi; | |
10225 | case M_DDIV_3I: | |
10226 | dbl = 1; | |
10227 | s = "ddiv"; | |
10228 | s2 = "mflo"; | |
10229 | goto do_divi; | |
10230 | case M_DDIVU_3I: | |
10231 | dbl = 1; | |
10232 | s = "ddivu"; | |
10233 | s2 = "mflo"; | |
10234 | goto do_divi; | |
10235 | case M_DREM_3I: | |
10236 | dbl = 1; | |
10237 | s = "ddiv"; | |
10238 | s2 = "mfhi"; | |
10239 | goto do_divi; | |
10240 | case M_DREMU_3I: | |
10241 | dbl = 1; | |
10242 | s = "ddivu"; | |
10243 | s2 = "mfhi"; | |
10244 | do_divi: | |
b0e6f033 | 10245 | if (imm_expr.X_add_number == 0) |
252b5132 | 10246 | { |
1661c76c | 10247 | as_warn (_("divide by zero")); |
252b5132 | 10248 | if (mips_trap) |
df58fc94 | 10249 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10250 | else |
df58fc94 | 10251 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10252 | break; |
252b5132 | 10253 | } |
b0e6f033 | 10254 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10255 | { |
10256 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10257 | move_register (op[0], op[1]); |
252b5132 | 10258 | else |
c0ebe874 | 10259 | move_register (op[0], ZERO); |
8fc2e39e | 10260 | break; |
252b5132 | 10261 | } |
b0e6f033 | 10262 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10263 | { |
10264 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10265 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10266 | else |
c0ebe874 | 10267 | move_register (op[0], ZERO); |
8fc2e39e | 10268 | break; |
252b5132 RH |
10269 | } |
10270 | ||
8fc2e39e | 10271 | used_at = 1; |
67c0d1eb | 10272 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10273 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10274 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10275 | break; |
10276 | ||
10277 | case M_DIVU_3: | |
10278 | s = "divu"; | |
10279 | s2 = "mflo"; | |
10280 | goto do_divu3; | |
10281 | case M_REMU_3: | |
10282 | s = "divu"; | |
10283 | s2 = "mfhi"; | |
10284 | goto do_divu3; | |
10285 | case M_DDIVU_3: | |
10286 | s = "ddivu"; | |
10287 | s2 = "mflo"; | |
10288 | goto do_divu3; | |
10289 | case M_DREMU_3: | |
10290 | s = "ddivu"; | |
10291 | s2 = "mfhi"; | |
10292 | do_divu3: | |
7d10b47d | 10293 | start_noreorder (); |
252b5132 RH |
10294 | if (mips_trap) |
10295 | { | |
c0ebe874 RS |
10296 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10297 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10298 | /* We want to close the noreorder block as soon as possible, so |
10299 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10300 | end_noreorder (); |
252b5132 RH |
10301 | } |
10302 | else | |
10303 | { | |
df58fc94 RS |
10304 | if (mips_opts.micromips) |
10305 | micromips_label_expr (&label_expr); | |
10306 | else | |
10307 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10308 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10309 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10310 | |
10311 | /* We want to close the noreorder block as soon as possible, so | |
10312 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10313 | end_noreorder (); |
df58fc94 RS |
10314 | macro_build (NULL, "break", BRK_FMT, 7); |
10315 | if (mips_opts.micromips) | |
10316 | micromips_add_label (); | |
252b5132 | 10317 | } |
c0ebe874 | 10318 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10319 | break; |
252b5132 | 10320 | |
1abe91b1 MR |
10321 | case M_DLCA_AB: |
10322 | dbl = 1; | |
10323 | case M_LCA_AB: | |
10324 | call = 1; | |
10325 | goto do_la; | |
252b5132 RH |
10326 | case M_DLA_AB: |
10327 | dbl = 1; | |
10328 | case M_LA_AB: | |
1abe91b1 | 10329 | do_la: |
252b5132 RH |
10330 | /* Load the address of a symbol into a register. If breg is not |
10331 | zero, we then add a base register to it. */ | |
10332 | ||
c0ebe874 | 10333 | breg = op[2]; |
bad1aba3 | 10334 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10335 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10336 | "instead")); | |
3bec30a8 | 10337 | |
90ecf173 | 10338 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10339 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10340 | "instead")); | |
3bec30a8 | 10341 | |
f2ae14a1 | 10342 | if (small_offset_p (0, align, 16)) |
0c11417f | 10343 | { |
c0ebe874 | 10344 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10345 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10346 | break; |
0c11417f MR |
10347 | } |
10348 | ||
c0ebe874 | 10349 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10350 | { |
10351 | tempreg = AT; | |
10352 | used_at = 1; | |
10353 | } | |
10354 | else | |
c0ebe874 | 10355 | tempreg = op[0]; |
afdbd6d0 | 10356 | |
252b5132 RH |
10357 | if (offset_expr.X_op != O_symbol |
10358 | && offset_expr.X_op != O_constant) | |
10359 | { | |
1661c76c | 10360 | as_bad (_("expression too complex")); |
252b5132 RH |
10361 | offset_expr.X_op = O_constant; |
10362 | } | |
10363 | ||
252b5132 | 10364 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10365 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10366 | else if (mips_pic == NO_PIC) |
10367 | { | |
d6bc6245 | 10368 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10369 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10370 | Otherwise we want |
10371 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10372 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10373 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10374 | so we may as well always use the latter form. |
76b3015f | 10375 | |
6caf9ef4 TS |
10376 | With 64bit address space and a usable $at we want |
10377 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10378 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10379 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10380 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10381 | dsll32 $tempreg,0 | |
10382 | daddu $tempreg,$tempreg,$at | |
10383 | ||
10384 | If $at is already in use, we use a path which is suboptimal | |
10385 | on superscalar processors. | |
10386 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10387 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10388 | dsll $tempreg,16 | |
10389 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10390 | dsll $tempreg,16 | |
10391 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10392 | ||
10393 | For GP relative symbols in 64bit address space we can use | |
10394 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10395 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10396 | { |
6caf9ef4 TS |
10397 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10398 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10399 | { | |
10400 | relax_start (offset_expr.X_add_symbol); | |
10401 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10402 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10403 | relax_switch (); | |
10404 | } | |
d6bc6245 | 10405 | |
741fe287 | 10406 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10407 | { |
df58fc94 | 10408 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10409 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10410 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10411 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10412 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10413 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10414 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10415 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10416 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10417 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10418 | used_at = 1; |
10419 | } | |
10420 | else | |
10421 | { | |
df58fc94 | 10422 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10423 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10424 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10425 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10426 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10427 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10428 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10429 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10430 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10431 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10432 | } |
6caf9ef4 TS |
10433 | |
10434 | if (mips_relax.sequence) | |
10435 | relax_end (); | |
98d3f06f KH |
10436 | } |
10437 | else | |
10438 | { | |
10439 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10440 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10441 | { |
4d7206a2 | 10442 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10443 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10444 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10445 | relax_switch (); |
98d3f06f | 10446 | } |
6943caf0 | 10447 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10448 | as_bad (_("offset too large")); |
67c0d1eb RS |
10449 | macro_build_lui (&offset_expr, tempreg); |
10450 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10451 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10452 | if (mips_relax.sequence) |
10453 | relax_end (); | |
98d3f06f | 10454 | } |
252b5132 | 10455 | } |
0a44bf69 | 10456 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10457 | { |
9117d219 NC |
10458 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10459 | ||
252b5132 RH |
10460 | /* If this is a reference to an external symbol, and there |
10461 | is no constant, we want | |
10462 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10463 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10464 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10465 | For a local symbol, we want |
10466 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10467 | nop | |
10468 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10469 | ||
10470 | If we have a small constant, and this is a reference to | |
10471 | an external symbol, we want | |
10472 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10473 | nop | |
10474 | addiu $tempreg,$tempreg,<constant> | |
10475 | For a local symbol, we want the same instruction | |
10476 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10477 | addiu instruction. | |
10478 | ||
10479 | If we have a large constant, and this is a reference to | |
10480 | an external symbol, we want | |
10481 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10482 | lui $at,<hiconstant> | |
10483 | addiu $at,$at,<loconstant> | |
10484 | addu $tempreg,$tempreg,$at | |
10485 | For a local symbol, we want the same instruction | |
10486 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10487 | addiu instruction. |
ed6fb7bd SC |
10488 | */ |
10489 | ||
4d7206a2 | 10490 | if (offset_expr.X_add_number == 0) |
252b5132 | 10491 | { |
0a44bf69 RS |
10492 | if (mips_pic == SVR4_PIC |
10493 | && breg == 0 | |
10494 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10495 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10496 | ||
10497 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10498 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10499 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10500 | if (breg != 0) |
252b5132 RH |
10501 | { |
10502 | /* We're going to put in an addu instruction using | |
10503 | tempreg, so we may as well insert the nop right | |
10504 | now. */ | |
269137b2 | 10505 | load_delay_nop (); |
252b5132 | 10506 | } |
4d7206a2 | 10507 | relax_switch (); |
67c0d1eb RS |
10508 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10509 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10510 | load_delay_nop (); |
67c0d1eb RS |
10511 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10512 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10513 | relax_end (); |
252b5132 RH |
10514 | /* FIXME: If breg == 0, and the next instruction uses |
10515 | $tempreg, then if this variant case is used an extra | |
10516 | nop will be generated. */ | |
10517 | } | |
4d7206a2 RS |
10518 | else if (offset_expr.X_add_number >= -0x8000 |
10519 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10520 | { |
67c0d1eb | 10521 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10522 | load_delay_nop (); |
67c0d1eb | 10523 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10524 | } |
10525 | else | |
10526 | { | |
4d7206a2 RS |
10527 | expr1.X_add_number = offset_expr.X_add_number; |
10528 | offset_expr.X_add_number = | |
43c0598f | 10529 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10530 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10531 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10532 | /* If we are going to add in a base register, and the |
10533 | target register and the base register are the same, | |
10534 | then we are using AT as a temporary register. Since | |
10535 | we want to load the constant into AT, we add our | |
10536 | current AT (from the global offset table) and the | |
10537 | register into the register now, and pretend we were | |
10538 | not using a base register. */ | |
c0ebe874 | 10539 | if (breg == op[0]) |
252b5132 | 10540 | { |
269137b2 | 10541 | load_delay_nop (); |
67c0d1eb | 10542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10543 | op[0], AT, breg); |
252b5132 | 10544 | breg = 0; |
c0ebe874 | 10545 | tempreg = op[0]; |
252b5132 | 10546 | } |
f6a22291 | 10547 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10548 | used_at = 1; |
10549 | } | |
10550 | } | |
0a44bf69 | 10551 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10552 | { |
67c0d1eb | 10553 | int add_breg_early = 0; |
f5040a92 AO |
10554 | |
10555 | /* If this is a reference to an external, and there is no | |
10556 | constant, or local symbol (*), with or without a | |
10557 | constant, we want | |
10558 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10559 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10560 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10561 | ||
10562 | If we have a small constant, and this is a reference to | |
10563 | an external symbol, we want | |
10564 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10565 | addiu $tempreg,$tempreg,<constant> | |
10566 | ||
10567 | If we have a large constant, and this is a reference to | |
10568 | an external symbol, we want | |
10569 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10570 | lui $at,<hiconstant> | |
10571 | addiu $at,$at,<loconstant> | |
10572 | addu $tempreg,$tempreg,$at | |
10573 | ||
10574 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10575 | local symbols, even though it introduces an additional | |
10576 | instruction. */ | |
10577 | ||
f5040a92 AO |
10578 | if (offset_expr.X_add_number) |
10579 | { | |
4d7206a2 | 10580 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10581 | offset_expr.X_add_number = 0; |
10582 | ||
4d7206a2 | 10583 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10584 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10585 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10586 | |
10587 | if (expr1.X_add_number >= -0x8000 | |
10588 | && expr1.X_add_number < 0x8000) | |
10589 | { | |
67c0d1eb RS |
10590 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10591 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10592 | } |
ecd13cd3 | 10593 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10594 | { |
c0ebe874 RS |
10595 | unsigned int dreg; |
10596 | ||
f5040a92 AO |
10597 | /* If we are going to add in a base register, and the |
10598 | target register and the base register are the same, | |
10599 | then we are using AT as a temporary register. Since | |
10600 | we want to load the constant into AT, we add our | |
10601 | current AT (from the global offset table) and the | |
10602 | register into the register now, and pretend we were | |
10603 | not using a base register. */ | |
c0ebe874 | 10604 | if (breg != op[0]) |
f5040a92 AO |
10605 | dreg = tempreg; |
10606 | else | |
10607 | { | |
9c2799c2 | 10608 | gas_assert (tempreg == AT); |
67c0d1eb | 10609 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10610 | op[0], AT, breg); |
10611 | dreg = op[0]; | |
67c0d1eb | 10612 | add_breg_early = 1; |
f5040a92 AO |
10613 | } |
10614 | ||
f6a22291 | 10615 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10616 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10617 | dreg, dreg, AT); |
f5040a92 | 10618 | |
f5040a92 AO |
10619 | used_at = 1; |
10620 | } | |
10621 | else | |
10622 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10623 | ||
4d7206a2 | 10624 | relax_switch (); |
f5040a92 AO |
10625 | offset_expr.X_add_number = expr1.X_add_number; |
10626 | ||
67c0d1eb RS |
10627 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10628 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
10629 | if (add_breg_early) | |
f5040a92 | 10630 | { |
67c0d1eb | 10631 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10632 | op[0], tempreg, breg); |
f5040a92 | 10633 | breg = 0; |
c0ebe874 | 10634 | tempreg = op[0]; |
f5040a92 | 10635 | } |
4d7206a2 | 10636 | relax_end (); |
f5040a92 | 10637 | } |
4d7206a2 | 10638 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 10639 | { |
4d7206a2 | 10640 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10641 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10642 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 10643 | relax_switch (); |
67c0d1eb RS |
10644 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10645 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 10646 | relax_end (); |
f5040a92 | 10647 | } |
4d7206a2 | 10648 | else |
f5040a92 | 10649 | { |
67c0d1eb RS |
10650 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10651 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10652 | } |
10653 | } | |
0a44bf69 | 10654 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 10655 | { |
67c0d1eb | 10656 | int gpdelay; |
9117d219 NC |
10657 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10658 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 10659 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
10660 | |
10661 | /* This is the large GOT case. If this is a reference to an | |
10662 | external symbol, and there is no constant, we want | |
10663 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10664 | addu $tempreg,$tempreg,$gp | |
10665 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10666 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
10667 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10668 | addu $tempreg,$tempreg,$gp | |
10669 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
10670 | For a local symbol, we want |
10671 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10672 | nop | |
10673 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10674 | ||
10675 | If we have a small constant, and this is a reference to | |
10676 | an external symbol, we want | |
10677 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10678 | addu $tempreg,$tempreg,$gp | |
10679 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10680 | nop | |
10681 | addiu $tempreg,$tempreg,<constant> | |
10682 | For a local symbol, we want | |
10683 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10684 | nop | |
10685 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
10686 | ||
10687 | If we have a large constant, and this is a reference to | |
10688 | an external symbol, we want | |
10689 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10690 | addu $tempreg,$tempreg,$gp | |
10691 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10692 | lui $at,<hiconstant> | |
10693 | addiu $at,$at,<loconstant> | |
10694 | addu $tempreg,$tempreg,$at | |
10695 | For a local symbol, we want | |
10696 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10697 | lui $at,<hiconstant> | |
10698 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
10699 | addu $tempreg,$tempreg,$at | |
f5040a92 | 10700 | */ |
438c16b8 | 10701 | |
252b5132 RH |
10702 | expr1.X_add_number = offset_expr.X_add_number; |
10703 | offset_expr.X_add_number = 0; | |
4d7206a2 | 10704 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 10705 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
10706 | if (expr1.X_add_number == 0 && breg == 0 |
10707 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
10708 | { |
10709 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10710 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10711 | } | |
df58fc94 | 10712 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10713 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10714 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 10715 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 10716 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
10717 | if (expr1.X_add_number == 0) |
10718 | { | |
67c0d1eb | 10719 | if (breg != 0) |
252b5132 RH |
10720 | { |
10721 | /* We're going to put in an addu instruction using | |
10722 | tempreg, so we may as well insert the nop right | |
10723 | now. */ | |
269137b2 | 10724 | load_delay_nop (); |
252b5132 | 10725 | } |
252b5132 RH |
10726 | } |
10727 | else if (expr1.X_add_number >= -0x8000 | |
10728 | && expr1.X_add_number < 0x8000) | |
10729 | { | |
269137b2 | 10730 | load_delay_nop (); |
67c0d1eb | 10731 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10732 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
10733 | } |
10734 | else | |
10735 | { | |
c0ebe874 RS |
10736 | unsigned int dreg; |
10737 | ||
252b5132 RH |
10738 | /* If we are going to add in a base register, and the |
10739 | target register and the base register are the same, | |
10740 | then we are using AT as a temporary register. Since | |
10741 | we want to load the constant into AT, we add our | |
10742 | current AT (from the global offset table) and the | |
10743 | register into the register now, and pretend we were | |
10744 | not using a base register. */ | |
c0ebe874 | 10745 | if (breg != op[0]) |
67c0d1eb | 10746 | dreg = tempreg; |
252b5132 RH |
10747 | else |
10748 | { | |
9c2799c2 | 10749 | gas_assert (tempreg == AT); |
269137b2 | 10750 | load_delay_nop (); |
67c0d1eb | 10751 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10752 | op[0], AT, breg); |
10753 | dreg = op[0]; | |
252b5132 RH |
10754 | } |
10755 | ||
f6a22291 | 10756 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10757 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 10758 | |
252b5132 RH |
10759 | used_at = 1; |
10760 | } | |
43c0598f | 10761 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 10762 | relax_switch (); |
252b5132 | 10763 | |
67c0d1eb | 10764 | if (gpdelay) |
252b5132 RH |
10765 | { |
10766 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 10767 | the first instruction on the main stream does not. */ |
67c0d1eb | 10768 | macro_build (NULL, "nop", ""); |
252b5132 | 10769 | } |
ed6fb7bd | 10770 | |
67c0d1eb RS |
10771 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10772 | local_reloc_type, mips_gp_register); | |
f5040a92 | 10773 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
10774 | && expr1.X_add_number < 0x8000) |
10775 | { | |
269137b2 | 10776 | load_delay_nop (); |
67c0d1eb RS |
10777 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10778 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 10779 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
10780 | register, the external symbol case ended with a load, |
10781 | so if the symbol turns out to not be external, and | |
10782 | the next instruction uses tempreg, an unnecessary nop | |
10783 | will be inserted. */ | |
252b5132 RH |
10784 | } |
10785 | else | |
10786 | { | |
c0ebe874 | 10787 | if (breg == op[0]) |
252b5132 RH |
10788 | { |
10789 | /* We must add in the base register now, as in the | |
f5040a92 | 10790 | external symbol case. */ |
9c2799c2 | 10791 | gas_assert (tempreg == AT); |
269137b2 | 10792 | load_delay_nop (); |
67c0d1eb | 10793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10794 | op[0], AT, breg); |
10795 | tempreg = op[0]; | |
252b5132 | 10796 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 10797 | it in in both cases. */ |
252b5132 RH |
10798 | breg = 0; |
10799 | } | |
10800 | ||
67c0d1eb RS |
10801 | macro_build_lui (&expr1, AT); |
10802 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 10803 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 10804 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10805 | tempreg, tempreg, AT); |
8fc2e39e | 10806 | used_at = 1; |
252b5132 | 10807 | } |
4d7206a2 | 10808 | relax_end (); |
252b5132 | 10809 | } |
0a44bf69 | 10810 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 10811 | { |
f5040a92 AO |
10812 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10813 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 10814 | int add_breg_early = 0; |
f5040a92 AO |
10815 | |
10816 | /* This is the large GOT case. If this is a reference to an | |
10817 | external symbol, and there is no constant, we want | |
10818 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10819 | add $tempreg,$tempreg,$gp | |
10820 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10821 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10822 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10823 | add $tempreg,$tempreg,$gp | |
10824 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
10825 | ||
10826 | If we have a small constant, and this is a reference to | |
10827 | an external symbol, we want | |
10828 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10829 | add $tempreg,$tempreg,$gp | |
10830 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10831 | addi $tempreg,$tempreg,<constant> | |
10832 | ||
10833 | If we have a large constant, and this is a reference to | |
10834 | an external symbol, we want | |
10835 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10836 | addu $tempreg,$tempreg,$gp | |
10837 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10838 | lui $at,<hiconstant> | |
10839 | addi $at,$at,<loconstant> | |
10840 | add $tempreg,$tempreg,$at | |
10841 | ||
10842 | If we have NewABI, and we know it's a local symbol, we want | |
10843 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
10844 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
10845 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
10846 | ||
4d7206a2 | 10847 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 10848 | |
4d7206a2 | 10849 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10850 | offset_expr.X_add_number = 0; |
10851 | ||
1abe91b1 MR |
10852 | if (expr1.X_add_number == 0 && breg == 0 |
10853 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
10854 | { |
10855 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10856 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10857 | } | |
df58fc94 | 10858 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10860 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
10861 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10862 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
10863 | |
10864 | if (expr1.X_add_number == 0) | |
4d7206a2 | 10865 | ; |
f5040a92 AO |
10866 | else if (expr1.X_add_number >= -0x8000 |
10867 | && expr1.X_add_number < 0x8000) | |
10868 | { | |
67c0d1eb | 10869 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10870 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 10871 | } |
ecd13cd3 | 10872 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10873 | { |
c0ebe874 RS |
10874 | unsigned int dreg; |
10875 | ||
f5040a92 AO |
10876 | /* If we are going to add in a base register, and the |
10877 | target register and the base register are the same, | |
10878 | then we are using AT as a temporary register. Since | |
10879 | we want to load the constant into AT, we add our | |
10880 | current AT (from the global offset table) and the | |
10881 | register into the register now, and pretend we were | |
10882 | not using a base register. */ | |
c0ebe874 | 10883 | if (breg != op[0]) |
f5040a92 AO |
10884 | dreg = tempreg; |
10885 | else | |
10886 | { | |
9c2799c2 | 10887 | gas_assert (tempreg == AT); |
67c0d1eb | 10888 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10889 | op[0], AT, breg); |
10890 | dreg = op[0]; | |
67c0d1eb | 10891 | add_breg_early = 1; |
f5040a92 AO |
10892 | } |
10893 | ||
f6a22291 | 10894 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10895 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 10896 | |
f5040a92 AO |
10897 | used_at = 1; |
10898 | } | |
10899 | else | |
10900 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10901 | ||
4d7206a2 | 10902 | relax_switch (); |
f5040a92 | 10903 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
10904 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10905 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
10906 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
10907 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
10908 | if (add_breg_early) | |
f5040a92 | 10909 | { |
67c0d1eb | 10910 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10911 | op[0], tempreg, breg); |
f5040a92 | 10912 | breg = 0; |
c0ebe874 | 10913 | tempreg = op[0]; |
f5040a92 | 10914 | } |
4d7206a2 | 10915 | relax_end (); |
f5040a92 | 10916 | } |
252b5132 RH |
10917 | else |
10918 | abort (); | |
10919 | ||
10920 | if (breg != 0) | |
c0ebe874 | 10921 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
10922 | break; |
10923 | ||
52b6b6b9 | 10924 | case M_MSGSND: |
df58fc94 | 10925 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10926 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 10927 | break; |
52b6b6b9 JM |
10928 | |
10929 | case M_MSGLD: | |
df58fc94 | 10930 | gas_assert (!mips_opts.micromips); |
c8276761 | 10931 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 10932 | break; |
52b6b6b9 JM |
10933 | |
10934 | case M_MSGLD_T: | |
df58fc94 | 10935 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10936 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 10937 | break; |
52b6b6b9 JM |
10938 | |
10939 | case M_MSGWAIT: | |
df58fc94 | 10940 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 10941 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 10942 | break; |
52b6b6b9 JM |
10943 | |
10944 | case M_MSGWAIT_T: | |
df58fc94 | 10945 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 10946 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 10947 | break; |
52b6b6b9 | 10948 | |
252b5132 RH |
10949 | case M_J_A: |
10950 | /* The j instruction may not be used in PIC code, since it | |
10951 | requires an absolute address. We convert it to a b | |
10952 | instruction. */ | |
10953 | if (mips_pic == NO_PIC) | |
67c0d1eb | 10954 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 10955 | else |
67c0d1eb | 10956 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10957 | break; |
252b5132 RH |
10958 | |
10959 | /* The jal instructions must be handled as macros because when | |
10960 | generating PIC code they expand to multi-instruction | |
10961 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 10962 | case M_JALS_1: |
c0ebe874 RS |
10963 | op[1] = op[0]; |
10964 | op[0] = RA; | |
df58fc94 RS |
10965 | /* Fall through. */ |
10966 | case M_JALS_2: | |
10967 | gas_assert (mips_opts.micromips); | |
833794fc MR |
10968 | if (mips_opts.insn32) |
10969 | { | |
1661c76c | 10970 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
10971 | break; |
10972 | } | |
df58fc94 RS |
10973 | jals = 1; |
10974 | goto jal; | |
252b5132 | 10975 | case M_JAL_1: |
c0ebe874 RS |
10976 | op[1] = op[0]; |
10977 | op[0] = RA; | |
252b5132 RH |
10978 | /* Fall through. */ |
10979 | case M_JAL_2: | |
df58fc94 | 10980 | jal: |
3e722fb5 | 10981 | if (mips_pic == NO_PIC) |
df58fc94 RS |
10982 | { |
10983 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 10984 | if (mips_opts.micromips |
833794fc | 10985 | && !mips_opts.insn32 |
c0ebe874 | 10986 | && op[0] == RA |
e64af278 | 10987 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 10988 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 10989 | else |
c0ebe874 | 10990 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 10991 | } |
0a44bf69 | 10992 | else |
252b5132 | 10993 | { |
df58fc94 RS |
10994 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
10995 | && mips_cprestore_offset >= 0); | |
10996 | ||
c0ebe874 | 10997 | if (op[1] != PIC_CALL_REG) |
252b5132 | 10998 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 10999 | |
833794fc MR |
11000 | s = ((mips_opts.micromips |
11001 | && !mips_opts.insn32 | |
11002 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11003 | ? "jalrs" : "jalr"); |
e64af278 | 11004 | if (mips_opts.micromips |
833794fc | 11005 | && !mips_opts.insn32 |
c0ebe874 | 11006 | && op[0] == RA |
e64af278 | 11007 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11008 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11009 | else |
c0ebe874 | 11010 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11011 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11012 | { |
6478892d | 11013 | if (mips_cprestore_offset < 0) |
1661c76c | 11014 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11015 | else |
11016 | { | |
90ecf173 | 11017 | if (!mips_frame_reg_valid) |
7a621144 | 11018 | { |
1661c76c | 11019 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11020 | /* Quiet this warning. */ |
11021 | mips_frame_reg_valid = 1; | |
11022 | } | |
90ecf173 | 11023 | if (!mips_cprestore_valid) |
7a621144 | 11024 | { |
1661c76c | 11025 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11026 | /* Quiet this warning. */ |
11027 | mips_cprestore_valid = 1; | |
11028 | } | |
d3fca0b5 MR |
11029 | if (mips_opts.noreorder) |
11030 | macro_build (NULL, "nop", ""); | |
6478892d | 11031 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 11032 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11033 | mips_gp_register, |
256ab948 TS |
11034 | mips_frame_reg, |
11035 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11036 | } |
252b5132 RH |
11037 | } |
11038 | } | |
252b5132 | 11039 | |
8fc2e39e | 11040 | break; |
252b5132 | 11041 | |
df58fc94 RS |
11042 | case M_JALS_A: |
11043 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11044 | if (mips_opts.insn32) |
11045 | { | |
1661c76c | 11046 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11047 | break; |
11048 | } | |
df58fc94 RS |
11049 | jals = 1; |
11050 | /* Fall through. */ | |
252b5132 RH |
11051 | case M_JAL_A: |
11052 | if (mips_pic == NO_PIC) | |
df58fc94 | 11053 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11054 | else if (mips_pic == SVR4_PIC) |
11055 | { | |
11056 | /* If this is a reference to an external symbol, and we are | |
11057 | using a small GOT, we want | |
11058 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11059 | nop | |
f9419b05 | 11060 | jalr $ra,$25 |
252b5132 RH |
11061 | nop |
11062 | lw $gp,cprestore($sp) | |
11063 | The cprestore value is set using the .cprestore | |
11064 | pseudo-op. If we are using a big GOT, we want | |
11065 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11066 | addu $25,$25,$gp | |
11067 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11068 | nop | |
f9419b05 | 11069 | jalr $ra,$25 |
252b5132 RH |
11070 | nop |
11071 | lw $gp,cprestore($sp) | |
11072 | If the symbol is not external, we want | |
11073 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11074 | nop | |
11075 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11076 | jalr $ra,$25 |
252b5132 | 11077 | nop |
438c16b8 | 11078 | lw $gp,cprestore($sp) |
f5040a92 AO |
11079 | |
11080 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11081 | sequences above, minus nops, unless the symbol is local, | |
11082 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11083 | GOT_DISP. */ | |
438c16b8 | 11084 | if (HAVE_NEWABI) |
252b5132 | 11085 | { |
90ecf173 | 11086 | if (!mips_big_got) |
f5040a92 | 11087 | { |
4d7206a2 | 11088 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11089 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11090 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11091 | mips_gp_register); |
4d7206a2 | 11092 | relax_switch (); |
67c0d1eb RS |
11093 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11094 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11095 | mips_gp_register); |
11096 | relax_end (); | |
f5040a92 AO |
11097 | } |
11098 | else | |
11099 | { | |
4d7206a2 | 11100 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11101 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11102 | BFD_RELOC_MIPS_CALL_HI16); |
11103 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11104 | PIC_CALL_REG, mips_gp_register); | |
11105 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11106 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11107 | PIC_CALL_REG); | |
4d7206a2 | 11108 | relax_switch (); |
67c0d1eb RS |
11109 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11110 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11111 | mips_gp_register); | |
11112 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11113 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11114 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11115 | relax_end (); |
f5040a92 | 11116 | } |
684022ea | 11117 | |
df58fc94 | 11118 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11119 | } |
11120 | else | |
11121 | { | |
4d7206a2 | 11122 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11123 | if (!mips_big_got) |
438c16b8 | 11124 | { |
67c0d1eb RS |
11125 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11126 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11127 | mips_gp_register); |
269137b2 | 11128 | load_delay_nop (); |
4d7206a2 | 11129 | relax_switch (); |
438c16b8 | 11130 | } |
252b5132 | 11131 | else |
252b5132 | 11132 | { |
67c0d1eb RS |
11133 | int gpdelay; |
11134 | ||
11135 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11136 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11137 | BFD_RELOC_MIPS_CALL_HI16); |
11138 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11139 | PIC_CALL_REG, mips_gp_register); | |
11140 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11141 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11142 | PIC_CALL_REG); | |
269137b2 | 11143 | load_delay_nop (); |
4d7206a2 | 11144 | relax_switch (); |
67c0d1eb RS |
11145 | if (gpdelay) |
11146 | macro_build (NULL, "nop", ""); | |
252b5132 | 11147 | } |
67c0d1eb RS |
11148 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11149 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11150 | mips_gp_register); |
269137b2 | 11151 | load_delay_nop (); |
67c0d1eb RS |
11152 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11153 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11154 | relax_end (); |
df58fc94 | 11155 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11156 | |
6478892d | 11157 | if (mips_cprestore_offset < 0) |
1661c76c | 11158 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11159 | else |
11160 | { | |
90ecf173 | 11161 | if (!mips_frame_reg_valid) |
7a621144 | 11162 | { |
1661c76c | 11163 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11164 | /* Quiet this warning. */ |
11165 | mips_frame_reg_valid = 1; | |
11166 | } | |
90ecf173 | 11167 | if (!mips_cprestore_valid) |
7a621144 | 11168 | { |
1661c76c | 11169 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11170 | /* Quiet this warning. */ |
11171 | mips_cprestore_valid = 1; | |
11172 | } | |
6478892d | 11173 | if (mips_opts.noreorder) |
67c0d1eb | 11174 | macro_build (NULL, "nop", ""); |
6478892d | 11175 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 11176 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11177 | mips_gp_register, |
256ab948 TS |
11178 | mips_frame_reg, |
11179 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11180 | } |
252b5132 RH |
11181 | } |
11182 | } | |
0a44bf69 | 11183 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11184 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11185 | else |
11186 | abort (); | |
11187 | ||
8fc2e39e | 11188 | break; |
252b5132 | 11189 | |
7f3c4072 | 11190 | case M_LBUE_AB: |
7f3c4072 CM |
11191 | s = "lbue"; |
11192 | fmt = "t,+j(b)"; | |
11193 | offbits = 9; | |
11194 | goto ld_st; | |
11195 | case M_LHUE_AB: | |
7f3c4072 CM |
11196 | s = "lhue"; |
11197 | fmt = "t,+j(b)"; | |
11198 | offbits = 9; | |
11199 | goto ld_st; | |
11200 | case M_LBE_AB: | |
7f3c4072 CM |
11201 | s = "lbe"; |
11202 | fmt = "t,+j(b)"; | |
11203 | offbits = 9; | |
11204 | goto ld_st; | |
11205 | case M_LHE_AB: | |
7f3c4072 CM |
11206 | s = "lhe"; |
11207 | fmt = "t,+j(b)"; | |
11208 | offbits = 9; | |
11209 | goto ld_st; | |
11210 | case M_LLE_AB: | |
7f3c4072 CM |
11211 | s = "lle"; |
11212 | fmt = "t,+j(b)"; | |
11213 | offbits = 9; | |
11214 | goto ld_st; | |
11215 | case M_LWE_AB: | |
7f3c4072 CM |
11216 | s = "lwe"; |
11217 | fmt = "t,+j(b)"; | |
11218 | offbits = 9; | |
11219 | goto ld_st; | |
11220 | case M_LWLE_AB: | |
7f3c4072 CM |
11221 | s = "lwle"; |
11222 | fmt = "t,+j(b)"; | |
11223 | offbits = 9; | |
11224 | goto ld_st; | |
11225 | case M_LWRE_AB: | |
7f3c4072 CM |
11226 | s = "lwre"; |
11227 | fmt = "t,+j(b)"; | |
11228 | offbits = 9; | |
11229 | goto ld_st; | |
11230 | case M_SBE_AB: | |
7f3c4072 CM |
11231 | s = "sbe"; |
11232 | fmt = "t,+j(b)"; | |
11233 | offbits = 9; | |
11234 | goto ld_st; | |
11235 | case M_SCE_AB: | |
7f3c4072 CM |
11236 | s = "sce"; |
11237 | fmt = "t,+j(b)"; | |
11238 | offbits = 9; | |
11239 | goto ld_st; | |
11240 | case M_SHE_AB: | |
7f3c4072 CM |
11241 | s = "she"; |
11242 | fmt = "t,+j(b)"; | |
11243 | offbits = 9; | |
11244 | goto ld_st; | |
11245 | case M_SWE_AB: | |
7f3c4072 CM |
11246 | s = "swe"; |
11247 | fmt = "t,+j(b)"; | |
11248 | offbits = 9; | |
11249 | goto ld_st; | |
11250 | case M_SWLE_AB: | |
7f3c4072 CM |
11251 | s = "swle"; |
11252 | fmt = "t,+j(b)"; | |
11253 | offbits = 9; | |
11254 | goto ld_st; | |
11255 | case M_SWRE_AB: | |
7f3c4072 CM |
11256 | s = "swre"; |
11257 | fmt = "t,+j(b)"; | |
11258 | offbits = 9; | |
11259 | goto ld_st; | |
dec0624d | 11260 | case M_ACLR_AB: |
dec0624d | 11261 | s = "aclr"; |
dec0624d | 11262 | fmt = "\\,~(b)"; |
7f3c4072 | 11263 | offbits = 12; |
dec0624d MR |
11264 | goto ld_st; |
11265 | case M_ASET_AB: | |
dec0624d | 11266 | s = "aset"; |
dec0624d | 11267 | fmt = "\\,~(b)"; |
7f3c4072 | 11268 | offbits = 12; |
dec0624d | 11269 | goto ld_st; |
252b5132 RH |
11270 | case M_LB_AB: |
11271 | s = "lb"; | |
df58fc94 | 11272 | fmt = "t,o(b)"; |
252b5132 RH |
11273 | goto ld; |
11274 | case M_LBU_AB: | |
11275 | s = "lbu"; | |
df58fc94 | 11276 | fmt = "t,o(b)"; |
252b5132 RH |
11277 | goto ld; |
11278 | case M_LH_AB: | |
11279 | s = "lh"; | |
df58fc94 | 11280 | fmt = "t,o(b)"; |
252b5132 RH |
11281 | goto ld; |
11282 | case M_LHU_AB: | |
11283 | s = "lhu"; | |
df58fc94 | 11284 | fmt = "t,o(b)"; |
252b5132 RH |
11285 | goto ld; |
11286 | case M_LW_AB: | |
11287 | s = "lw"; | |
df58fc94 | 11288 | fmt = "t,o(b)"; |
252b5132 RH |
11289 | goto ld; |
11290 | case M_LWC0_AB: | |
df58fc94 | 11291 | gas_assert (!mips_opts.micromips); |
252b5132 | 11292 | s = "lwc0"; |
df58fc94 | 11293 | fmt = "E,o(b)"; |
bdaaa2e1 | 11294 | /* Itbl support may require additional care here. */ |
252b5132 | 11295 | coproc = 1; |
df58fc94 | 11296 | goto ld_st; |
252b5132 RH |
11297 | case M_LWC1_AB: |
11298 | s = "lwc1"; | |
df58fc94 | 11299 | fmt = "T,o(b)"; |
bdaaa2e1 | 11300 | /* Itbl support may require additional care here. */ |
252b5132 | 11301 | coproc = 1; |
df58fc94 | 11302 | goto ld_st; |
252b5132 RH |
11303 | case M_LWC2_AB: |
11304 | s = "lwc2"; | |
df58fc94 | 11305 | fmt = COP12_FMT; |
7361da2c AB |
11306 | offbits = (mips_opts.micromips ? 12 |
11307 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11308 | : 16); | |
bdaaa2e1 | 11309 | /* Itbl support may require additional care here. */ |
252b5132 | 11310 | coproc = 1; |
df58fc94 | 11311 | goto ld_st; |
252b5132 | 11312 | case M_LWC3_AB: |
df58fc94 | 11313 | gas_assert (!mips_opts.micromips); |
252b5132 | 11314 | s = "lwc3"; |
df58fc94 | 11315 | fmt = "E,o(b)"; |
bdaaa2e1 | 11316 | /* Itbl support may require additional care here. */ |
252b5132 | 11317 | coproc = 1; |
df58fc94 | 11318 | goto ld_st; |
252b5132 RH |
11319 | case M_LWL_AB: |
11320 | s = "lwl"; | |
df58fc94 | 11321 | fmt = MEM12_FMT; |
7f3c4072 | 11322 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11323 | goto ld_st; |
252b5132 RH |
11324 | case M_LWR_AB: |
11325 | s = "lwr"; | |
df58fc94 | 11326 | fmt = MEM12_FMT; |
7f3c4072 | 11327 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11328 | goto ld_st; |
252b5132 | 11329 | case M_LDC1_AB: |
252b5132 | 11330 | s = "ldc1"; |
df58fc94 | 11331 | fmt = "T,o(b)"; |
bdaaa2e1 | 11332 | /* Itbl support may require additional care here. */ |
252b5132 | 11333 | coproc = 1; |
df58fc94 | 11334 | goto ld_st; |
252b5132 RH |
11335 | case M_LDC2_AB: |
11336 | s = "ldc2"; | |
df58fc94 | 11337 | fmt = COP12_FMT; |
7361da2c AB |
11338 | offbits = (mips_opts.micromips ? 12 |
11339 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11340 | : 16); | |
bdaaa2e1 | 11341 | /* Itbl support may require additional care here. */ |
252b5132 | 11342 | coproc = 1; |
df58fc94 | 11343 | goto ld_st; |
c77c0862 | 11344 | case M_LQC2_AB: |
c77c0862 | 11345 | s = "lqc2"; |
14daeee3 | 11346 | fmt = "+7,o(b)"; |
c77c0862 RS |
11347 | /* Itbl support may require additional care here. */ |
11348 | coproc = 1; | |
11349 | goto ld_st; | |
252b5132 RH |
11350 | case M_LDC3_AB: |
11351 | s = "ldc3"; | |
df58fc94 | 11352 | fmt = "E,o(b)"; |
bdaaa2e1 | 11353 | /* Itbl support may require additional care here. */ |
252b5132 | 11354 | coproc = 1; |
df58fc94 | 11355 | goto ld_st; |
252b5132 RH |
11356 | case M_LDL_AB: |
11357 | s = "ldl"; | |
df58fc94 | 11358 | fmt = MEM12_FMT; |
7f3c4072 | 11359 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11360 | goto ld_st; |
252b5132 RH |
11361 | case M_LDR_AB: |
11362 | s = "ldr"; | |
df58fc94 | 11363 | fmt = MEM12_FMT; |
7f3c4072 | 11364 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11365 | goto ld_st; |
252b5132 RH |
11366 | case M_LL_AB: |
11367 | s = "ll"; | |
7361da2c AB |
11368 | fmt = LL_SC_FMT; |
11369 | offbits = (mips_opts.micromips ? 12 | |
11370 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11371 | : 16); | |
252b5132 RH |
11372 | goto ld; |
11373 | case M_LLD_AB: | |
11374 | s = "lld"; | |
7361da2c AB |
11375 | fmt = LL_SC_FMT; |
11376 | offbits = (mips_opts.micromips ? 12 | |
11377 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11378 | : 16); | |
252b5132 RH |
11379 | goto ld; |
11380 | case M_LWU_AB: | |
11381 | s = "lwu"; | |
df58fc94 | 11382 | fmt = MEM12_FMT; |
7f3c4072 | 11383 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11384 | goto ld; |
11385 | case M_LWP_AB: | |
df58fc94 RS |
11386 | gas_assert (mips_opts.micromips); |
11387 | s = "lwp"; | |
11388 | fmt = "t,~(b)"; | |
7f3c4072 | 11389 | offbits = 12; |
df58fc94 RS |
11390 | lp = 1; |
11391 | goto ld; | |
11392 | case M_LDP_AB: | |
df58fc94 RS |
11393 | gas_assert (mips_opts.micromips); |
11394 | s = "ldp"; | |
11395 | fmt = "t,~(b)"; | |
7f3c4072 | 11396 | offbits = 12; |
df58fc94 RS |
11397 | lp = 1; |
11398 | goto ld; | |
11399 | case M_LWM_AB: | |
df58fc94 RS |
11400 | gas_assert (mips_opts.micromips); |
11401 | s = "lwm"; | |
11402 | fmt = "n,~(b)"; | |
7f3c4072 | 11403 | offbits = 12; |
df58fc94 RS |
11404 | goto ld_st; |
11405 | case M_LDM_AB: | |
df58fc94 RS |
11406 | gas_assert (mips_opts.micromips); |
11407 | s = "ldm"; | |
11408 | fmt = "n,~(b)"; | |
7f3c4072 | 11409 | offbits = 12; |
df58fc94 RS |
11410 | goto ld_st; |
11411 | ||
252b5132 | 11412 | ld: |
f19ccbda | 11413 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11414 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11415 | goto ld_st; |
252b5132 | 11416 | else |
c0ebe874 | 11417 | tempreg = op[0] + lp; |
df58fc94 RS |
11418 | goto ld_noat; |
11419 | ||
252b5132 RH |
11420 | case M_SB_AB: |
11421 | s = "sb"; | |
df58fc94 RS |
11422 | fmt = "t,o(b)"; |
11423 | goto ld_st; | |
252b5132 RH |
11424 | case M_SH_AB: |
11425 | s = "sh"; | |
df58fc94 RS |
11426 | fmt = "t,o(b)"; |
11427 | goto ld_st; | |
252b5132 RH |
11428 | case M_SW_AB: |
11429 | s = "sw"; | |
df58fc94 RS |
11430 | fmt = "t,o(b)"; |
11431 | goto ld_st; | |
252b5132 | 11432 | case M_SWC0_AB: |
df58fc94 | 11433 | gas_assert (!mips_opts.micromips); |
252b5132 | 11434 | s = "swc0"; |
df58fc94 | 11435 | fmt = "E,o(b)"; |
bdaaa2e1 | 11436 | /* Itbl support may require additional care here. */ |
252b5132 | 11437 | coproc = 1; |
df58fc94 | 11438 | goto ld_st; |
252b5132 RH |
11439 | case M_SWC1_AB: |
11440 | s = "swc1"; | |
df58fc94 | 11441 | fmt = "T,o(b)"; |
bdaaa2e1 | 11442 | /* Itbl support may require additional care here. */ |
252b5132 | 11443 | coproc = 1; |
df58fc94 | 11444 | goto ld_st; |
252b5132 RH |
11445 | case M_SWC2_AB: |
11446 | s = "swc2"; | |
df58fc94 | 11447 | fmt = COP12_FMT; |
7361da2c AB |
11448 | offbits = (mips_opts.micromips ? 12 |
11449 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11450 | : 16); | |
bdaaa2e1 | 11451 | /* Itbl support may require additional care here. */ |
252b5132 | 11452 | coproc = 1; |
df58fc94 | 11453 | goto ld_st; |
252b5132 | 11454 | case M_SWC3_AB: |
df58fc94 | 11455 | gas_assert (!mips_opts.micromips); |
252b5132 | 11456 | s = "swc3"; |
df58fc94 | 11457 | fmt = "E,o(b)"; |
bdaaa2e1 | 11458 | /* Itbl support may require additional care here. */ |
252b5132 | 11459 | coproc = 1; |
df58fc94 | 11460 | goto ld_st; |
252b5132 RH |
11461 | case M_SWL_AB: |
11462 | s = "swl"; | |
df58fc94 | 11463 | fmt = MEM12_FMT; |
7f3c4072 | 11464 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11465 | goto ld_st; |
252b5132 RH |
11466 | case M_SWR_AB: |
11467 | s = "swr"; | |
df58fc94 | 11468 | fmt = MEM12_FMT; |
7f3c4072 | 11469 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11470 | goto ld_st; |
252b5132 RH |
11471 | case M_SC_AB: |
11472 | s = "sc"; | |
7361da2c AB |
11473 | fmt = LL_SC_FMT; |
11474 | offbits = (mips_opts.micromips ? 12 | |
11475 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11476 | : 16); | |
df58fc94 | 11477 | goto ld_st; |
252b5132 RH |
11478 | case M_SCD_AB: |
11479 | s = "scd"; | |
7361da2c AB |
11480 | fmt = LL_SC_FMT; |
11481 | offbits = (mips_opts.micromips ? 12 | |
11482 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11483 | : 16); | |
df58fc94 | 11484 | goto ld_st; |
d43b4baf TS |
11485 | case M_CACHE_AB: |
11486 | s = "cache"; | |
7361da2c AB |
11487 | fmt = (mips_opts.micromips ? "k,~(b)" |
11488 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11489 | : "k,o(b)"); | |
11490 | offbits = (mips_opts.micromips ? 12 | |
11491 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11492 | : 16); | |
7f3c4072 CM |
11493 | goto ld_st; |
11494 | case M_CACHEE_AB: | |
7f3c4072 CM |
11495 | s = "cachee"; |
11496 | fmt = "k,+j(b)"; | |
11497 | offbits = 9; | |
df58fc94 | 11498 | goto ld_st; |
3eebd5eb MR |
11499 | case M_PREF_AB: |
11500 | s = "pref"; | |
7361da2c AB |
11501 | fmt = (mips_opts.micromips ? "k,~(b)" |
11502 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11503 | : "k,o(b)"); | |
11504 | offbits = (mips_opts.micromips ? 12 | |
11505 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11506 | : 16); | |
7f3c4072 CM |
11507 | goto ld_st; |
11508 | case M_PREFE_AB: | |
7f3c4072 CM |
11509 | s = "prefe"; |
11510 | fmt = "k,+j(b)"; | |
11511 | offbits = 9; | |
df58fc94 | 11512 | goto ld_st; |
252b5132 | 11513 | case M_SDC1_AB: |
252b5132 | 11514 | s = "sdc1"; |
df58fc94 | 11515 | fmt = "T,o(b)"; |
252b5132 | 11516 | coproc = 1; |
bdaaa2e1 | 11517 | /* Itbl support may require additional care here. */ |
df58fc94 | 11518 | goto ld_st; |
252b5132 RH |
11519 | case M_SDC2_AB: |
11520 | s = "sdc2"; | |
df58fc94 | 11521 | fmt = COP12_FMT; |
7361da2c AB |
11522 | offbits = (mips_opts.micromips ? 12 |
11523 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11524 | : 16); | |
c77c0862 RS |
11525 | /* Itbl support may require additional care here. */ |
11526 | coproc = 1; | |
11527 | goto ld_st; | |
11528 | case M_SQC2_AB: | |
c77c0862 | 11529 | s = "sqc2"; |
14daeee3 | 11530 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11531 | /* Itbl support may require additional care here. */ |
252b5132 | 11532 | coproc = 1; |
df58fc94 | 11533 | goto ld_st; |
252b5132 | 11534 | case M_SDC3_AB: |
df58fc94 | 11535 | gas_assert (!mips_opts.micromips); |
252b5132 | 11536 | s = "sdc3"; |
df58fc94 | 11537 | fmt = "E,o(b)"; |
bdaaa2e1 | 11538 | /* Itbl support may require additional care here. */ |
252b5132 | 11539 | coproc = 1; |
df58fc94 | 11540 | goto ld_st; |
252b5132 RH |
11541 | case M_SDL_AB: |
11542 | s = "sdl"; | |
df58fc94 | 11543 | fmt = MEM12_FMT; |
7f3c4072 | 11544 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11545 | goto ld_st; |
252b5132 RH |
11546 | case M_SDR_AB: |
11547 | s = "sdr"; | |
df58fc94 | 11548 | fmt = MEM12_FMT; |
7f3c4072 | 11549 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11550 | goto ld_st; |
11551 | case M_SWP_AB: | |
df58fc94 RS |
11552 | gas_assert (mips_opts.micromips); |
11553 | s = "swp"; | |
11554 | fmt = "t,~(b)"; | |
7f3c4072 | 11555 | offbits = 12; |
df58fc94 RS |
11556 | goto ld_st; |
11557 | case M_SDP_AB: | |
df58fc94 RS |
11558 | gas_assert (mips_opts.micromips); |
11559 | s = "sdp"; | |
11560 | fmt = "t,~(b)"; | |
7f3c4072 | 11561 | offbits = 12; |
df58fc94 RS |
11562 | goto ld_st; |
11563 | case M_SWM_AB: | |
df58fc94 RS |
11564 | gas_assert (mips_opts.micromips); |
11565 | s = "swm"; | |
11566 | fmt = "n,~(b)"; | |
7f3c4072 | 11567 | offbits = 12; |
df58fc94 RS |
11568 | goto ld_st; |
11569 | case M_SDM_AB: | |
df58fc94 RS |
11570 | gas_assert (mips_opts.micromips); |
11571 | s = "sdm"; | |
11572 | fmt = "n,~(b)"; | |
7f3c4072 | 11573 | offbits = 12; |
df58fc94 RS |
11574 | |
11575 | ld_st: | |
8fc2e39e | 11576 | tempreg = AT; |
df58fc94 | 11577 | ld_noat: |
c0ebe874 | 11578 | breg = op[2]; |
f2ae14a1 RS |
11579 | if (small_offset_p (0, align, 16)) |
11580 | { | |
11581 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11582 | macros for o32 but which should act like normal instructions | |
11583 | otherwise. */ | |
11584 | if (offbits == 16) | |
c0ebe874 | 11585 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11586 | offset_reloc[1], offset_reloc[2], breg); |
11587 | else if (small_offset_p (0, align, offbits)) | |
11588 | { | |
11589 | if (offbits == 0) | |
c0ebe874 | 11590 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11591 | else |
c0ebe874 | 11592 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11593 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11594 | } |
11595 | else | |
11596 | { | |
11597 | if (tempreg == AT) | |
11598 | used_at = 1; | |
11599 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11600 | tempreg, breg, -1, offset_reloc[0], | |
11601 | offset_reloc[1], offset_reloc[2]); | |
11602 | if (offbits == 0) | |
c0ebe874 | 11603 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11604 | else |
c0ebe874 | 11605 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11606 | } |
11607 | break; | |
11608 | } | |
11609 | ||
11610 | if (tempreg == AT) | |
11611 | used_at = 1; | |
11612 | ||
252b5132 RH |
11613 | if (offset_expr.X_op != O_constant |
11614 | && offset_expr.X_op != O_symbol) | |
11615 | { | |
1661c76c | 11616 | as_bad (_("expression too complex")); |
252b5132 RH |
11617 | offset_expr.X_op = O_constant; |
11618 | } | |
11619 | ||
2051e8c4 MR |
11620 | if (HAVE_32BIT_ADDRESSES |
11621 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11622 | { |
11623 | char value [32]; | |
11624 | ||
11625 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11626 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11627 | } |
2051e8c4 | 11628 | |
252b5132 RH |
11629 | /* A constant expression in PIC code can be handled just as it |
11630 | is in non PIC code. */ | |
aed1a261 RS |
11631 | if (offset_expr.X_op == O_constant) |
11632 | { | |
f2ae14a1 RS |
11633 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
11634 | offbits == 0 ? 16 : offbits); | |
11635 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 11636 | |
f2ae14a1 RS |
11637 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
11638 | if (breg != 0) | |
11639 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11640 | tempreg, tempreg, breg); | |
7f3c4072 | 11641 | if (offbits == 0) |
dd6a37e7 | 11642 | { |
f2ae14a1 | 11643 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 11644 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 11645 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 11646 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11647 | } |
7f3c4072 | 11648 | else if (offbits == 16) |
c0ebe874 | 11649 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 11650 | else |
c0ebe874 | 11651 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11652 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 11653 | } |
7f3c4072 | 11654 | else if (offbits != 16) |
df58fc94 | 11655 | { |
7f3c4072 CM |
11656 | /* The offset field is too narrow to be used for a low-part |
11657 | relocation, so load the whole address into the auxillary | |
f2ae14a1 RS |
11658 | register. */ |
11659 | load_address (tempreg, &offset_expr, &used_at); | |
11660 | if (breg != 0) | |
11661 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11662 | tempreg, tempreg, breg); | |
7f3c4072 | 11663 | if (offbits == 0) |
c0ebe874 | 11664 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11665 | else |
c0ebe874 | 11666 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
11667 | } |
11668 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
11669 | { |
11670 | /* If this is a reference to a GP relative symbol, and there | |
11671 | is no base register, we want | |
c0ebe874 | 11672 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
11673 | Otherwise, if there is no base register, we want |
11674 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 11675 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
11676 | If we have a constant, we need two instructions anyhow, |
11677 | so we always use the latter form. | |
11678 | ||
11679 | If we have a base register, and this is a reference to a | |
11680 | GP relative symbol, we want | |
11681 | addu $tempreg,$breg,$gp | |
c0ebe874 | 11682 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
11683 | Otherwise we want |
11684 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11685 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 11686 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 11687 | With a constant we always use the latter case. |
76b3015f | 11688 | |
d6bc6245 TS |
11689 | With 64bit address space and no base register and $at usable, |
11690 | we want | |
11691 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11692 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11693 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11694 | dsll32 $tempreg,0 | |
11695 | daddu $tempreg,$at | |
c0ebe874 | 11696 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11697 | If we have a base register, we want |
11698 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11699 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11700 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11701 | daddu $at,$breg | |
11702 | dsll32 $tempreg,0 | |
11703 | daddu $tempreg,$at | |
c0ebe874 | 11704 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11705 | |
11706 | Without $at we can't generate the optimal path for superscalar | |
11707 | processors here since this would require two temporary registers. | |
11708 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11709 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11710 | dsll $tempreg,16 | |
11711 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11712 | dsll $tempreg,16 | |
c0ebe874 | 11713 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11714 | If we have a base register, we want |
11715 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11716 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11717 | dsll $tempreg,16 | |
11718 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11719 | dsll $tempreg,16 | |
11720 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 11721 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 11722 | |
6caf9ef4 | 11723 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
11724 | the same sequence as in 32bit address space. */ |
11725 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 11726 | { |
aed1a261 | 11727 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
11728 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
11729 | { | |
11730 | relax_start (offset_expr.X_add_symbol); | |
11731 | if (breg == 0) | |
11732 | { | |
c0ebe874 | 11733 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11734 | BFD_RELOC_GPREL16, mips_gp_register); |
11735 | } | |
11736 | else | |
11737 | { | |
11738 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11739 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 11740 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11741 | BFD_RELOC_GPREL16, tempreg); |
11742 | } | |
11743 | relax_switch (); | |
11744 | } | |
d6bc6245 | 11745 | |
741fe287 | 11746 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 11747 | { |
df58fc94 | 11748 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 11749 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11750 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
11751 | BFD_RELOC_HI16_S); |
11752 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
11753 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 11754 | if (breg != 0) |
67c0d1eb | 11755 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 11756 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11757 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 11758 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 11759 | tempreg); |
d6bc6245 TS |
11760 | used_at = 1; |
11761 | } | |
11762 | else | |
11763 | { | |
df58fc94 | 11764 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
11765 | BFD_RELOC_MIPS_HIGHEST); |
11766 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
11767 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 11768 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
11769 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
11770 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 11771 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 11772 | if (breg != 0) |
67c0d1eb | 11773 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 11774 | tempreg, tempreg, breg); |
c0ebe874 | 11775 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11776 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 11777 | } |
6caf9ef4 TS |
11778 | |
11779 | if (mips_relax.sequence) | |
11780 | relax_end (); | |
8fc2e39e | 11781 | break; |
d6bc6245 | 11782 | } |
256ab948 | 11783 | |
252b5132 RH |
11784 | if (breg == 0) |
11785 | { | |
67c0d1eb | 11786 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 11787 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 11788 | { |
4d7206a2 | 11789 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 11790 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 11791 | mips_gp_register); |
4d7206a2 | 11792 | relax_switch (); |
252b5132 | 11793 | } |
67c0d1eb | 11794 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 11795 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11796 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
11797 | if (mips_relax.sequence) |
11798 | relax_end (); | |
252b5132 RH |
11799 | } |
11800 | else | |
11801 | { | |
67c0d1eb | 11802 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 11803 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 11804 | { |
4d7206a2 | 11805 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11806 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11807 | tempreg, breg, mips_gp_register); |
c0ebe874 | 11808 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11809 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 11810 | relax_switch (); |
252b5132 | 11811 | } |
67c0d1eb RS |
11812 | macro_build_lui (&offset_expr, tempreg); |
11813 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 11814 | tempreg, tempreg, breg); |
c0ebe874 | 11815 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11816 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
11817 | if (mips_relax.sequence) |
11818 | relax_end (); | |
252b5132 RH |
11819 | } |
11820 | } | |
0a44bf69 | 11821 | else if (!mips_big_got) |
252b5132 | 11822 | { |
ed6fb7bd | 11823 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 11824 | |
252b5132 RH |
11825 | /* If this is a reference to an external symbol, we want |
11826 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11827 | nop | |
c0ebe874 | 11828 | <op> op[0],0($tempreg) |
252b5132 RH |
11829 | Otherwise we want |
11830 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11831 | nop | |
11832 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 11833 | <op> op[0],0($tempreg) |
f5040a92 AO |
11834 | |
11835 | For NewABI, we want | |
11836 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 11837 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 11838 | |
252b5132 RH |
11839 | If there is a base register, we add it to $tempreg before |
11840 | the <op>. If there is a constant, we stick it in the | |
11841 | <op> instruction. We don't handle constants larger than | |
11842 | 16 bits, because we have no way to load the upper 16 bits | |
11843 | (actually, we could handle them for the subset of cases | |
11844 | in which we are not using $at). */ | |
9c2799c2 | 11845 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
11846 | if (HAVE_NEWABI) |
11847 | { | |
67c0d1eb RS |
11848 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11849 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 11850 | if (breg != 0) |
67c0d1eb | 11851 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11852 | tempreg, tempreg, breg); |
c0ebe874 | 11853 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11854 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
11855 | break; |
11856 | } | |
252b5132 RH |
11857 | expr1.X_add_number = offset_expr.X_add_number; |
11858 | offset_expr.X_add_number = 0; | |
11859 | if (expr1.X_add_number < -0x8000 | |
11860 | || expr1.X_add_number >= 0x8000) | |
11861 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
11862 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11863 | lw_reloc_type, mips_gp_register); | |
269137b2 | 11864 | load_delay_nop (); |
4d7206a2 RS |
11865 | relax_start (offset_expr.X_add_symbol); |
11866 | relax_switch (); | |
67c0d1eb RS |
11867 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
11868 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11869 | relax_end (); |
252b5132 | 11870 | if (breg != 0) |
67c0d1eb | 11871 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11872 | tempreg, tempreg, breg); |
c0ebe874 | 11873 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 11874 | } |
0a44bf69 | 11875 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11876 | { |
67c0d1eb | 11877 | int gpdelay; |
252b5132 RH |
11878 | |
11879 | /* If this is a reference to an external symbol, we want | |
11880 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11881 | addu $tempreg,$tempreg,$gp | |
11882 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 11883 | <op> op[0],0($tempreg) |
252b5132 RH |
11884 | Otherwise we want |
11885 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11886 | nop | |
11887 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 11888 | <op> op[0],0($tempreg) |
252b5132 RH |
11889 | If there is a base register, we add it to $tempreg before |
11890 | the <op>. If there is a constant, we stick it in the | |
11891 | <op> instruction. We don't handle constants larger than | |
11892 | 16 bits, because we have no way to load the upper 16 bits | |
11893 | (actually, we could handle them for the subset of cases | |
f5040a92 | 11894 | in which we are not using $at). */ |
9c2799c2 | 11895 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
11896 | expr1.X_add_number = offset_expr.X_add_number; |
11897 | offset_expr.X_add_number = 0; | |
11898 | if (expr1.X_add_number < -0x8000 | |
11899 | || expr1.X_add_number >= 0x8000) | |
11900 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 11901 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 11902 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11903 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 11904 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
11905 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
11906 | mips_gp_register); | |
11907 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11908 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 11909 | relax_switch (); |
67c0d1eb RS |
11910 | if (gpdelay) |
11911 | macro_build (NULL, "nop", ""); | |
11912 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11913 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11914 | load_delay_nop (); |
67c0d1eb RS |
11915 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
11916 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11917 | relax_end (); |
11918 | ||
252b5132 | 11919 | if (breg != 0) |
67c0d1eb | 11920 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11921 | tempreg, tempreg, breg); |
c0ebe874 | 11922 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 11923 | } |
0a44bf69 | 11924 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11925 | { |
f5040a92 AO |
11926 | /* If this is a reference to an external symbol, we want |
11927 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11928 | add $tempreg,$tempreg,$gp | |
11929 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 11930 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
11931 | Otherwise, for local symbols, we want: |
11932 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 11933 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 11934 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 11935 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11936 | offset_expr.X_add_number = 0; |
11937 | if (expr1.X_add_number < -0x8000 | |
11938 | || expr1.X_add_number >= 0x8000) | |
11939 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 11940 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11941 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 11942 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
11943 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
11944 | mips_gp_register); | |
11945 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
11946 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 11947 | if (breg != 0) |
67c0d1eb | 11948 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11949 | tempreg, tempreg, breg); |
c0ebe874 | 11950 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 11951 | |
4d7206a2 | 11952 | relax_switch (); |
f5040a92 | 11953 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11954 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11955 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 11956 | if (breg != 0) |
67c0d1eb | 11957 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11958 | tempreg, tempreg, breg); |
c0ebe874 | 11959 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 11960 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 11961 | relax_end (); |
f5040a92 | 11962 | } |
252b5132 RH |
11963 | else |
11964 | abort (); | |
11965 | ||
252b5132 RH |
11966 | break; |
11967 | ||
833794fc MR |
11968 | case M_JRADDIUSP: |
11969 | gas_assert (mips_opts.micromips); | |
11970 | gas_assert (mips_opts.insn32); | |
11971 | start_noreorder (); | |
11972 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 11973 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
11974 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
11975 | end_noreorder (); | |
11976 | break; | |
11977 | ||
11978 | case M_JRC: | |
11979 | gas_assert (mips_opts.micromips); | |
11980 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 11981 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
11982 | if (mips_opts.noreorder) |
11983 | macro_build (NULL, "nop", ""); | |
11984 | break; | |
11985 | ||
252b5132 RH |
11986 | case M_LI: |
11987 | case M_LI_S: | |
c0ebe874 | 11988 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 11989 | break; |
252b5132 RH |
11990 | |
11991 | case M_DLI: | |
c0ebe874 | 11992 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 11993 | break; |
252b5132 RH |
11994 | |
11995 | case M_LI_SS: | |
11996 | if (imm_expr.X_op == O_constant) | |
11997 | { | |
8fc2e39e | 11998 | used_at = 1; |
67c0d1eb | 11999 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12000 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12001 | break; |
12002 | } | |
12003 | else | |
12004 | { | |
b0e6f033 RS |
12005 | gas_assert (imm_expr.X_op == O_absent |
12006 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12007 | && strcmp (segment_name (S_GET_SEGMENT |
12008 | (offset_expr.X_add_symbol)), | |
12009 | ".lit4") == 0 | |
12010 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12011 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12012 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12013 | break; |
252b5132 RH |
12014 | } |
12015 | ||
12016 | case M_LI_D: | |
ca4e0257 RS |
12017 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12018 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12019 | order 32 bits of the value and the low order 32 bits are either | |
12020 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12021 | if (imm_expr.X_op == O_constant) |
252b5132 | 12022 | { |
bad1aba3 | 12023 | if (GPR_SIZE == 64) |
c0ebe874 | 12024 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12025 | else |
12026 | { | |
12027 | int hreg, lreg; | |
12028 | ||
12029 | if (target_big_endian) | |
12030 | { | |
c0ebe874 RS |
12031 | hreg = op[0]; |
12032 | lreg = op[0] + 1; | |
252b5132 RH |
12033 | } |
12034 | else | |
12035 | { | |
c0ebe874 RS |
12036 | hreg = op[0] + 1; |
12037 | lreg = op[0]; | |
252b5132 RH |
12038 | } |
12039 | ||
12040 | if (hreg <= 31) | |
67c0d1eb | 12041 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12042 | if (lreg <= 31) |
12043 | { | |
12044 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12045 | move_register (lreg, 0); |
252b5132 RH |
12046 | else |
12047 | { | |
9c2799c2 | 12048 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12049 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12050 | } |
12051 | } | |
12052 | } | |
8fc2e39e | 12053 | break; |
252b5132 | 12054 | } |
b0e6f033 | 12055 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12056 | |
12057 | /* We know that sym is in the .rdata section. First we get the | |
12058 | upper 16 bits of the address. */ | |
12059 | if (mips_pic == NO_PIC) | |
12060 | { | |
67c0d1eb | 12061 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12062 | used_at = 1; |
252b5132 | 12063 | } |
0a44bf69 | 12064 | else |
252b5132 | 12065 | { |
67c0d1eb RS |
12066 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12067 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12068 | used_at = 1; |
252b5132 | 12069 | } |
bdaaa2e1 | 12070 | |
252b5132 | 12071 | /* Now we load the register(s). */ |
bad1aba3 | 12072 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12073 | { |
12074 | used_at = 1; | |
c0ebe874 RS |
12075 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12076 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12077 | } |
252b5132 RH |
12078 | else |
12079 | { | |
8fc2e39e | 12080 | used_at = 1; |
c0ebe874 RS |
12081 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12082 | BFD_RELOC_LO16, AT); | |
12083 | if (op[0] != RA) | |
252b5132 RH |
12084 | { |
12085 | /* FIXME: How in the world do we deal with the possible | |
12086 | overflow here? */ | |
12087 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12088 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12089 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12090 | } |
12091 | } | |
252b5132 RH |
12092 | break; |
12093 | ||
12094 | case M_LI_DD: | |
ca4e0257 RS |
12095 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12096 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12097 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12098 | the value and the low order 32 bits are either zero or in | |
12099 | OFFSET_EXPR. */ | |
b0e6f033 | 12100 | if (imm_expr.X_op == O_constant) |
252b5132 | 12101 | { |
8fc2e39e | 12102 | used_at = 1; |
bad1aba3 | 12103 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12104 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12105 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12106 | else |
12107 | { | |
351cdf24 MF |
12108 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12109 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12110 | else if (FPR_SIZE != 32) | |
12111 | as_bad (_("Unable to generate `%s' compliant code " | |
12112 | "without mthc1"), | |
12113 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12114 | else | |
12115 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12116 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12117 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12118 | else |
12119 | { | |
9c2799c2 | 12120 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12121 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12122 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12123 | } |
12124 | } | |
12125 | break; | |
12126 | } | |
12127 | ||
b0e6f033 RS |
12128 | gas_assert (imm_expr.X_op == O_absent |
12129 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12130 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12131 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12132 | if (strcmp (s, ".lit8") == 0) | |
f2ae14a1 | 12133 | { |
c0ebe874 | 12134 | op[2] = mips_gp_register; |
f2ae14a1 RS |
12135 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12136 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12137 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12138 | } |
12139 | else | |
12140 | { | |
9c2799c2 | 12141 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12142 | used_at = 1; |
0a44bf69 | 12143 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12144 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12145 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12146 | else |
12147 | { | |
12148 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12149 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12150 | } |
bdaaa2e1 | 12151 | |
c0ebe874 | 12152 | op[2] = AT; |
f2ae14a1 RS |
12153 | offset_reloc[0] = BFD_RELOC_LO16; |
12154 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12155 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12156 | } | |
12157 | align = 8; | |
12158 | /* Fall through */ | |
c4a68bea | 12159 | |
252b5132 RH |
12160 | case M_L_DAB: |
12161 | /* | |
12162 | * The MIPS assembler seems to check for X_add_number not | |
12163 | * being double aligned and generating: | |
12164 | * lui at,%hi(foo+1) | |
12165 | * addu at,at,v1 | |
12166 | * addiu at,at,%lo(foo+1) | |
12167 | * lwc1 f2,0(at) | |
12168 | * lwc1 f3,4(at) | |
12169 | * But, the resulting address is the same after relocation so why | |
12170 | * generate the extra instruction? | |
12171 | */ | |
bdaaa2e1 | 12172 | /* Itbl support may require additional care here. */ |
252b5132 | 12173 | coproc = 1; |
df58fc94 | 12174 | fmt = "T,o(b)"; |
0aa27725 | 12175 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12176 | { |
12177 | s = "ldc1"; | |
df58fc94 | 12178 | goto ld_st; |
252b5132 | 12179 | } |
252b5132 | 12180 | s = "lwc1"; |
252b5132 RH |
12181 | goto ldd_std; |
12182 | ||
12183 | case M_S_DAB: | |
df58fc94 RS |
12184 | gas_assert (!mips_opts.micromips); |
12185 | /* Itbl support may require additional care here. */ | |
12186 | coproc = 1; | |
12187 | fmt = "T,o(b)"; | |
0aa27725 | 12188 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12189 | { |
12190 | s = "sdc1"; | |
df58fc94 | 12191 | goto ld_st; |
252b5132 | 12192 | } |
252b5132 | 12193 | s = "swc1"; |
252b5132 RH |
12194 | goto ldd_std; |
12195 | ||
e407c74b NC |
12196 | case M_LQ_AB: |
12197 | fmt = "t,o(b)"; | |
12198 | s = "lq"; | |
12199 | goto ld; | |
12200 | ||
12201 | case M_SQ_AB: | |
12202 | fmt = "t,o(b)"; | |
12203 | s = "sq"; | |
12204 | goto ld_st; | |
12205 | ||
252b5132 | 12206 | case M_LD_AB: |
df58fc94 | 12207 | fmt = "t,o(b)"; |
bad1aba3 | 12208 | if (GPR_SIZE == 64) |
252b5132 RH |
12209 | { |
12210 | s = "ld"; | |
12211 | goto ld; | |
12212 | } | |
252b5132 | 12213 | s = "lw"; |
252b5132 RH |
12214 | goto ldd_std; |
12215 | ||
12216 | case M_SD_AB: | |
df58fc94 | 12217 | fmt = "t,o(b)"; |
bad1aba3 | 12218 | if (GPR_SIZE == 64) |
252b5132 RH |
12219 | { |
12220 | s = "sd"; | |
df58fc94 | 12221 | goto ld_st; |
252b5132 | 12222 | } |
252b5132 | 12223 | s = "sw"; |
252b5132 RH |
12224 | |
12225 | ldd_std: | |
f2ae14a1 RS |
12226 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12227 | to adjust when loading from memory. We set coproc if we must | |
12228 | load $fn+1 first. */ | |
12229 | /* Itbl support may require additional care here. */ | |
12230 | if (!target_big_endian) | |
12231 | coproc = 0; | |
12232 | ||
c0ebe874 | 12233 | breg = op[2]; |
f2ae14a1 RS |
12234 | if (small_offset_p (0, align, 16)) |
12235 | { | |
12236 | ep = &offset_expr; | |
12237 | if (!small_offset_p (4, align, 16)) | |
12238 | { | |
12239 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12240 | -1, offset_reloc[0], offset_reloc[1], | |
12241 | offset_reloc[2]); | |
12242 | expr1.X_add_number = 0; | |
12243 | ep = &expr1; | |
12244 | breg = AT; | |
12245 | used_at = 1; | |
12246 | offset_reloc[0] = BFD_RELOC_LO16; | |
12247 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12248 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12249 | } | |
c0ebe874 | 12250 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12251 | { |
12252 | ep->X_add_number += 4; | |
c0ebe874 | 12253 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12254 | offset_reloc[1], offset_reloc[2], breg); |
12255 | ep->X_add_number -= 4; | |
c0ebe874 | 12256 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12257 | offset_reloc[1], offset_reloc[2], breg); |
12258 | } | |
12259 | else | |
12260 | { | |
c0ebe874 | 12261 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12262 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12263 | breg); | |
12264 | ep->X_add_number += 4; | |
c0ebe874 | 12265 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12266 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12267 | breg); | |
12268 | } | |
12269 | break; | |
12270 | } | |
12271 | ||
252b5132 RH |
12272 | if (offset_expr.X_op != O_symbol |
12273 | && offset_expr.X_op != O_constant) | |
12274 | { | |
1661c76c | 12275 | as_bad (_("expression too complex")); |
252b5132 RH |
12276 | offset_expr.X_op = O_constant; |
12277 | } | |
12278 | ||
2051e8c4 MR |
12279 | if (HAVE_32BIT_ADDRESSES |
12280 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12281 | { |
12282 | char value [32]; | |
12283 | ||
12284 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12285 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12286 | } |
2051e8c4 | 12287 | |
90ecf173 | 12288 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12289 | { |
12290 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12291 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12292 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12293 | If we have a base register, we use this |
12294 | addu $at,$breg,$gp | |
c0ebe874 RS |
12295 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12296 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12297 | If this is not a GP relative symbol, we want |
12298 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12299 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12300 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12301 | If there is a base register, we add it to $at after the |
12302 | lui instruction. If there is a constant, we always use | |
12303 | the last case. */ | |
39a59cf8 MR |
12304 | if (offset_expr.X_op == O_symbol |
12305 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12306 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12307 | { |
4d7206a2 | 12308 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12309 | if (breg == 0) |
12310 | { | |
c9914766 | 12311 | tempreg = mips_gp_register; |
252b5132 RH |
12312 | } |
12313 | else | |
12314 | { | |
67c0d1eb | 12315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12316 | AT, breg, mips_gp_register); |
252b5132 | 12317 | tempreg = AT; |
252b5132 RH |
12318 | used_at = 1; |
12319 | } | |
12320 | ||
beae10d5 | 12321 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12322 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12323 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12324 | offset_expr.X_add_number += 4; |
12325 | ||
12326 | /* Set mips_optimize to 2 to avoid inserting an | |
12327 | undesired nop. */ | |
12328 | hold_mips_optimize = mips_optimize; | |
12329 | mips_optimize = 2; | |
beae10d5 | 12330 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12331 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12332 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12333 | mips_optimize = hold_mips_optimize; |
12334 | ||
4d7206a2 | 12335 | relax_switch (); |
252b5132 | 12336 | |
0970e49e | 12337 | offset_expr.X_add_number -= 4; |
252b5132 | 12338 | } |
8fc2e39e | 12339 | used_at = 1; |
f2ae14a1 RS |
12340 | if (offset_high_part (offset_expr.X_add_number, 16) |
12341 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12342 | { | |
12343 | load_address (AT, &offset_expr, &used_at); | |
12344 | offset_expr.X_op = O_constant; | |
12345 | offset_expr.X_add_number = 0; | |
12346 | } | |
12347 | else | |
12348 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12349 | if (breg != 0) |
67c0d1eb | 12350 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12351 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12352 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12353 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12354 | /* FIXME: How do we handle overflow here? */ |
12355 | offset_expr.X_add_number += 4; | |
beae10d5 | 12356 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12357 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12358 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12359 | if (mips_relax.sequence) |
12360 | relax_end (); | |
bdaaa2e1 | 12361 | } |
0a44bf69 | 12362 | else if (!mips_big_got) |
252b5132 | 12363 | { |
252b5132 RH |
12364 | /* If this is a reference to an external symbol, we want |
12365 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12366 | nop | |
c0ebe874 RS |
12367 | <op> op[0],0($at) |
12368 | <op> op[0]+1,4($at) | |
252b5132 RH |
12369 | Otherwise we want |
12370 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12371 | nop | |
c0ebe874 RS |
12372 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12373 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12374 | If there is a base register we add it to $at before the |
12375 | lwc1 instructions. If there is a constant we include it | |
12376 | in the lwc1 instructions. */ | |
12377 | used_at = 1; | |
12378 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12379 | if (expr1.X_add_number < -0x8000 |
12380 | || expr1.X_add_number >= 0x8000 - 4) | |
12381 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12382 | load_got_offset (AT, &offset_expr); |
269137b2 | 12383 | load_delay_nop (); |
252b5132 | 12384 | if (breg != 0) |
67c0d1eb | 12385 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12386 | |
12387 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12388 | nop. */ | |
12389 | hold_mips_optimize = mips_optimize; | |
12390 | mips_optimize = 2; | |
4d7206a2 | 12391 | |
beae10d5 | 12392 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12393 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12394 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12395 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12396 | expr1.X_add_number += 4; |
c0ebe874 | 12397 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12398 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12399 | relax_switch (); |
c0ebe874 | 12400 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12401 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12402 | offset_expr.X_add_number += 4; |
c0ebe874 | 12403 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12404 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12405 | relax_end (); |
252b5132 | 12406 | |
4d7206a2 | 12407 | mips_optimize = hold_mips_optimize; |
252b5132 | 12408 | } |
0a44bf69 | 12409 | else if (mips_big_got) |
252b5132 | 12410 | { |
67c0d1eb | 12411 | int gpdelay; |
252b5132 RH |
12412 | |
12413 | /* If this is a reference to an external symbol, we want | |
12414 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12415 | addu $at,$at,$gp | |
12416 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12417 | nop | |
c0ebe874 RS |
12418 | <op> op[0],0($at) |
12419 | <op> op[0]+1,4($at) | |
252b5132 RH |
12420 | Otherwise we want |
12421 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12422 | nop | |
c0ebe874 RS |
12423 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12424 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12425 | If there is a base register we add it to $at before the |
12426 | lwc1 instructions. If there is a constant we include it | |
12427 | in the lwc1 instructions. */ | |
12428 | used_at = 1; | |
12429 | expr1.X_add_number = offset_expr.X_add_number; | |
12430 | offset_expr.X_add_number = 0; | |
12431 | if (expr1.X_add_number < -0x8000 | |
12432 | || expr1.X_add_number >= 0x8000 - 4) | |
12433 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12434 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12435 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12436 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12437 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12439 | AT, AT, mips_gp_register); |
67c0d1eb | 12440 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12441 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12442 | load_delay_nop (); |
252b5132 | 12443 | if (breg != 0) |
67c0d1eb | 12444 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12445 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12446 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12447 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12448 | expr1.X_add_number += 4; |
12449 | ||
12450 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12451 | nop. */ | |
12452 | hold_mips_optimize = mips_optimize; | |
12453 | mips_optimize = 2; | |
beae10d5 | 12454 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12455 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12456 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12457 | mips_optimize = hold_mips_optimize; |
12458 | expr1.X_add_number -= 4; | |
12459 | ||
4d7206a2 RS |
12460 | relax_switch (); |
12461 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12462 | if (gpdelay) |
12463 | macro_build (NULL, "nop", ""); | |
12464 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12465 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12466 | load_delay_nop (); |
252b5132 | 12467 | if (breg != 0) |
67c0d1eb | 12468 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12469 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12470 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12471 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12472 | offset_expr.X_add_number += 4; |
252b5132 RH |
12473 | |
12474 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12475 | nop. */ | |
12476 | hold_mips_optimize = mips_optimize; | |
12477 | mips_optimize = 2; | |
beae10d5 | 12478 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12479 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12480 | BFD_RELOC_LO16, AT); |
252b5132 | 12481 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12482 | relax_end (); |
252b5132 | 12483 | } |
252b5132 RH |
12484 | else |
12485 | abort (); | |
12486 | ||
252b5132 | 12487 | break; |
3739860c | 12488 | |
dd6a37e7 | 12489 | case M_SAA_AB: |
dd6a37e7 | 12490 | s = "saa"; |
0db377d0 | 12491 | goto saa_saad; |
dd6a37e7 | 12492 | case M_SAAD_AB: |
dd6a37e7 | 12493 | s = "saad"; |
0db377d0 MR |
12494 | saa_saad: |
12495 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12496 | offbits = 0; |
dd6a37e7 AP |
12497 | fmt = "t,(b)"; |
12498 | goto ld_st; | |
12499 | ||
252b5132 RH |
12500 | /* New code added to support COPZ instructions. |
12501 | This code builds table entries out of the macros in mip_opcodes. | |
12502 | R4000 uses interlocks to handle coproc delays. | |
12503 | Other chips (like the R3000) require nops to be inserted for delays. | |
12504 | ||
f72c8c98 | 12505 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12506 | In order to fill delay slots for non-interlocked chips, |
12507 | we must have a way to specify delays based on the coprocessor. | |
12508 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12509 | What are the side-effects of the cop instruction? | |
12510 | What cache support might we have and what are its effects? | |
12511 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12512 | What registers are read/set/modified? |
252b5132 RH |
12513 | |
12514 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12515 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12516 | |
12517 | case M_COP0: | |
12518 | s = "c0"; | |
12519 | goto copz; | |
12520 | case M_COP1: | |
12521 | s = "c1"; | |
12522 | goto copz; | |
12523 | case M_COP2: | |
12524 | s = "c2"; | |
12525 | goto copz; | |
12526 | case M_COP3: | |
12527 | s = "c3"; | |
12528 | copz: | |
df58fc94 | 12529 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12530 | /* For now we just do C (same as Cz). The parameter will be |
12531 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12532 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12533 | break; |
252b5132 | 12534 | |
ea1fb5dc | 12535 | case M_MOVE: |
c0ebe874 | 12536 | move_register (op[0], op[1]); |
8fc2e39e | 12537 | break; |
ea1fb5dc | 12538 | |
833794fc MR |
12539 | case M_MOVEP: |
12540 | gas_assert (mips_opts.micromips); | |
12541 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12542 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12543 | micromips_to_32_reg_m_map[op[1]]); | |
12544 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12545 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12546 | break; |
12547 | ||
252b5132 RH |
12548 | case M_DMUL: |
12549 | dbl = 1; | |
12550 | case M_MUL: | |
e407c74b | 12551 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12552 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12553 | op[2]); | |
e407c74b NC |
12554 | else |
12555 | { | |
c0ebe874 RS |
12556 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12557 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12558 | } |
8fc2e39e | 12559 | break; |
252b5132 RH |
12560 | |
12561 | case M_DMUL_I: | |
12562 | dbl = 1; | |
12563 | case M_MUL_I: | |
12564 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12565 | not trying to be that fancy. GCC should do this for us | |
12566 | anyway. */ | |
8fc2e39e | 12567 | used_at = 1; |
67c0d1eb | 12568 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12569 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12570 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12571 | break; |
12572 | ||
12573 | case M_DMULO_I: | |
12574 | dbl = 1; | |
12575 | case M_MULO_I: | |
12576 | imm = 1; | |
12577 | goto do_mulo; | |
12578 | ||
12579 | case M_DMULO: | |
12580 | dbl = 1; | |
12581 | case M_MULO: | |
12582 | do_mulo: | |
7d10b47d | 12583 | start_noreorder (); |
8fc2e39e | 12584 | used_at = 1; |
252b5132 | 12585 | if (imm) |
67c0d1eb | 12586 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12587 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12588 | op[1], imm ? AT : op[2]); | |
12589 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12590 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12591 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12592 | if (mips_trap) |
c0ebe874 | 12593 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12594 | else |
12595 | { | |
df58fc94 RS |
12596 | if (mips_opts.micromips) |
12597 | micromips_label_expr (&label_expr); | |
12598 | else | |
12599 | label_expr.X_add_number = 8; | |
c0ebe874 | 12600 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12601 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12602 | macro_build (NULL, "break", BRK_FMT, 6); |
12603 | if (mips_opts.micromips) | |
12604 | micromips_add_label (); | |
252b5132 | 12605 | } |
7d10b47d | 12606 | end_noreorder (); |
c0ebe874 | 12607 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
12608 | break; |
12609 | ||
12610 | case M_DMULOU_I: | |
12611 | dbl = 1; | |
12612 | case M_MULOU_I: | |
12613 | imm = 1; | |
12614 | goto do_mulou; | |
12615 | ||
12616 | case M_DMULOU: | |
12617 | dbl = 1; | |
12618 | case M_MULOU: | |
12619 | do_mulou: | |
7d10b47d | 12620 | start_noreorder (); |
8fc2e39e | 12621 | used_at = 1; |
252b5132 | 12622 | if (imm) |
67c0d1eb RS |
12623 | load_register (AT, &imm_expr, dbl); |
12624 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 12625 | op[1], imm ? AT : op[2]); |
df58fc94 | 12626 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 12627 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 12628 | if (mips_trap) |
df58fc94 | 12629 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
12630 | else |
12631 | { | |
df58fc94 RS |
12632 | if (mips_opts.micromips) |
12633 | micromips_label_expr (&label_expr); | |
12634 | else | |
12635 | label_expr.X_add_number = 8; | |
12636 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 12637 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12638 | macro_build (NULL, "break", BRK_FMT, 6); |
12639 | if (mips_opts.micromips) | |
12640 | micromips_add_label (); | |
252b5132 | 12641 | } |
7d10b47d | 12642 | end_noreorder (); |
252b5132 RH |
12643 | break; |
12644 | ||
771c7ce4 | 12645 | case M_DROL: |
fef14a42 | 12646 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12647 | { |
c0ebe874 | 12648 | if (op[0] == op[1]) |
82dd0097 CD |
12649 | { |
12650 | tempreg = AT; | |
12651 | used_at = 1; | |
12652 | } | |
12653 | else | |
c0ebe874 RS |
12654 | tempreg = op[0]; |
12655 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
12656 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12657 | break; |
82dd0097 | 12658 | } |
8fc2e39e | 12659 | used_at = 1; |
c0ebe874 RS |
12660 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12661 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
12662 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
12663 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12664 | break; |
12665 | ||
252b5132 | 12666 | case M_ROL: |
fef14a42 | 12667 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12668 | { |
c0ebe874 | 12669 | if (op[0] == op[1]) |
82dd0097 CD |
12670 | { |
12671 | tempreg = AT; | |
12672 | used_at = 1; | |
12673 | } | |
12674 | else | |
c0ebe874 RS |
12675 | tempreg = op[0]; |
12676 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
12677 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12678 | break; |
82dd0097 | 12679 | } |
8fc2e39e | 12680 | used_at = 1; |
c0ebe874 RS |
12681 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12682 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
12683 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
12684 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12685 | break; |
12686 | ||
771c7ce4 TS |
12687 | case M_DROL_I: |
12688 | { | |
12689 | unsigned int rot; | |
91d6fa6a NC |
12690 | char *l; |
12691 | char *rr; | |
771c7ce4 | 12692 | |
771c7ce4 | 12693 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12694 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
12695 | { |
12696 | rot = (64 - rot) & 0x3f; | |
12697 | if (rot >= 32) | |
c0ebe874 | 12698 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 12699 | else |
c0ebe874 | 12700 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12701 | break; |
60b63b72 | 12702 | } |
483fc7cd | 12703 | if (rot == 0) |
483fc7cd | 12704 | { |
c0ebe874 | 12705 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12706 | break; |
483fc7cd | 12707 | } |
82dd0097 | 12708 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 12709 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 12710 | rot &= 0x1f; |
8fc2e39e | 12711 | used_at = 1; |
c0ebe874 RS |
12712 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
12713 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12714 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12715 | } |
12716 | break; | |
12717 | ||
252b5132 | 12718 | case M_ROL_I: |
771c7ce4 TS |
12719 | { |
12720 | unsigned int rot; | |
12721 | ||
771c7ce4 | 12722 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12723 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 12724 | { |
c0ebe874 RS |
12725 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
12726 | (32 - rot) & 0x1f); | |
8fc2e39e | 12727 | break; |
60b63b72 | 12728 | } |
483fc7cd | 12729 | if (rot == 0) |
483fc7cd | 12730 | { |
c0ebe874 | 12731 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12732 | break; |
483fc7cd | 12733 | } |
8fc2e39e | 12734 | used_at = 1; |
c0ebe874 RS |
12735 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
12736 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12737 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12738 | } |
12739 | break; | |
12740 | ||
12741 | case M_DROR: | |
fef14a42 | 12742 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12743 | { |
c0ebe874 | 12744 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 12745 | break; |
82dd0097 | 12746 | } |
8fc2e39e | 12747 | used_at = 1; |
c0ebe874 RS |
12748 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12749 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
12750 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
12751 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12752 | break; |
12753 | ||
12754 | case M_ROR: | |
fef14a42 | 12755 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12756 | { |
c0ebe874 | 12757 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 12758 | break; |
82dd0097 | 12759 | } |
8fc2e39e | 12760 | used_at = 1; |
c0ebe874 RS |
12761 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12762 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
12763 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
12764 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12765 | break; |
12766 | ||
771c7ce4 TS |
12767 | case M_DROR_I: |
12768 | { | |
12769 | unsigned int rot; | |
91d6fa6a NC |
12770 | char *l; |
12771 | char *rr; | |
771c7ce4 | 12772 | |
771c7ce4 | 12773 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12774 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
12775 | { |
12776 | if (rot >= 32) | |
c0ebe874 | 12777 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 12778 | else |
c0ebe874 | 12779 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12780 | break; |
82dd0097 | 12781 | } |
483fc7cd | 12782 | if (rot == 0) |
483fc7cd | 12783 | { |
c0ebe874 | 12784 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12785 | break; |
483fc7cd | 12786 | } |
91d6fa6a | 12787 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
12788 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
12789 | rot &= 0x1f; | |
8fc2e39e | 12790 | used_at = 1; |
c0ebe874 RS |
12791 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
12792 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12793 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12794 | } |
12795 | break; | |
12796 | ||
252b5132 | 12797 | case M_ROR_I: |
771c7ce4 TS |
12798 | { |
12799 | unsigned int rot; | |
12800 | ||
771c7ce4 | 12801 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12802 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12803 | { |
c0ebe874 | 12804 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12805 | break; |
82dd0097 | 12806 | } |
483fc7cd | 12807 | if (rot == 0) |
483fc7cd | 12808 | { |
c0ebe874 | 12809 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12810 | break; |
483fc7cd | 12811 | } |
8fc2e39e | 12812 | used_at = 1; |
c0ebe874 RS |
12813 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
12814 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12815 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 12816 | } |
252b5132 RH |
12817 | break; |
12818 | ||
252b5132 | 12819 | case M_SEQ: |
c0ebe874 RS |
12820 | if (op[1] == 0) |
12821 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
12822 | else if (op[2] == 0) | |
12823 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
12824 | else |
12825 | { | |
c0ebe874 RS |
12826 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
12827 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 12828 | } |
8fc2e39e | 12829 | break; |
252b5132 RH |
12830 | |
12831 | case M_SEQ_I: | |
b0e6f033 | 12832 | if (imm_expr.X_add_number == 0) |
252b5132 | 12833 | { |
c0ebe874 | 12834 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 12835 | break; |
252b5132 | 12836 | } |
c0ebe874 | 12837 | if (op[1] == 0) |
252b5132 | 12838 | { |
1661c76c | 12839 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 12840 | ip->insn_mo->name); |
c0ebe874 | 12841 | move_register (op[0], 0); |
8fc2e39e | 12842 | break; |
252b5132 | 12843 | } |
dd3cbb7e NC |
12844 | if (CPU_HAS_SEQ (mips_opts.arch) |
12845 | && -512 <= imm_expr.X_add_number | |
12846 | && imm_expr.X_add_number < 512) | |
12847 | { | |
c0ebe874 | 12848 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 12849 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
12850 | break; |
12851 | } | |
b0e6f033 | 12852 | if (imm_expr.X_add_number >= 0 |
252b5132 | 12853 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 12854 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 12855 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
12856 | && imm_expr.X_add_number < 0) |
12857 | { | |
12858 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 12859 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 12860 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 12861 | } |
dd3cbb7e NC |
12862 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
12863 | { | |
12864 | used_at = 1; | |
bad1aba3 | 12865 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12866 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
12867 | break; |
12868 | } | |
252b5132 RH |
12869 | else |
12870 | { | |
bad1aba3 | 12871 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12872 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12873 | used_at = 1; |
12874 | } | |
c0ebe874 | 12875 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 12876 | break; |
252b5132 | 12877 | |
c0ebe874 | 12878 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
12879 | s = "slt"; |
12880 | goto sge; | |
12881 | case M_SGEU: | |
12882 | s = "sltu"; | |
12883 | sge: | |
c0ebe874 RS |
12884 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
12885 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 12886 | break; |
252b5132 | 12887 | |
c0ebe874 | 12888 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 12889 | case M_SGEU_I: |
b0e6f033 | 12890 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 12891 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
12892 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
12893 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
12894 | else |
12895 | { | |
bad1aba3 | 12896 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 12897 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 12898 | op[0], op[1], AT); |
252b5132 RH |
12899 | used_at = 1; |
12900 | } | |
c0ebe874 | 12901 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 12902 | break; |
252b5132 | 12903 | |
c0ebe874 | 12904 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
12905 | s = "slt"; |
12906 | goto sgt; | |
12907 | case M_SGTU: | |
12908 | s = "sltu"; | |
12909 | sgt: | |
c0ebe874 | 12910 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 12911 | break; |
252b5132 | 12912 | |
c0ebe874 | 12913 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
12914 | s = "slt"; |
12915 | goto sgti; | |
12916 | case M_SGTU_I: | |
12917 | s = "sltu"; | |
12918 | sgti: | |
8fc2e39e | 12919 | used_at = 1; |
bad1aba3 | 12920 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12921 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
12922 | break; |
12923 | ||
c0ebe874 | 12924 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
12925 | s = "slt"; |
12926 | goto sle; | |
12927 | case M_SLEU: | |
12928 | s = "sltu"; | |
12929 | sle: | |
c0ebe874 RS |
12930 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
12931 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 12932 | break; |
252b5132 | 12933 | |
c0ebe874 | 12934 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
12935 | s = "slt"; |
12936 | goto slei; | |
12937 | case M_SLEU_I: | |
12938 | s = "sltu"; | |
12939 | slei: | |
8fc2e39e | 12940 | used_at = 1; |
bad1aba3 | 12941 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
12942 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
12943 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
12944 | break; |
12945 | ||
12946 | case M_SLT_I: | |
b0e6f033 | 12947 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
12948 | && imm_expr.X_add_number < 0x8000) |
12949 | { | |
c0ebe874 RS |
12950 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
12951 | BFD_RELOC_LO16); | |
8fc2e39e | 12952 | break; |
252b5132 | 12953 | } |
8fc2e39e | 12954 | used_at = 1; |
bad1aba3 | 12955 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12956 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12957 | break; |
12958 | ||
12959 | case M_SLTU_I: | |
b0e6f033 | 12960 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
12961 | && imm_expr.X_add_number < 0x8000) |
12962 | { | |
c0ebe874 | 12963 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 12964 | BFD_RELOC_LO16); |
8fc2e39e | 12965 | break; |
252b5132 | 12966 | } |
8fc2e39e | 12967 | used_at = 1; |
bad1aba3 | 12968 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 12969 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
12970 | break; |
12971 | ||
12972 | case M_SNE: | |
c0ebe874 RS |
12973 | if (op[1] == 0) |
12974 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
12975 | else if (op[2] == 0) | |
12976 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
12977 | else |
12978 | { | |
c0ebe874 RS |
12979 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
12980 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 12981 | } |
8fc2e39e | 12982 | break; |
252b5132 RH |
12983 | |
12984 | case M_SNE_I: | |
b0e6f033 | 12985 | if (imm_expr.X_add_number == 0) |
252b5132 | 12986 | { |
c0ebe874 | 12987 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 12988 | break; |
252b5132 | 12989 | } |
c0ebe874 | 12990 | if (op[1] == 0) |
252b5132 | 12991 | { |
1661c76c | 12992 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 12993 | ip->insn_mo->name); |
bad1aba3 | 12994 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 12995 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 12996 | break; |
252b5132 | 12997 | } |
dd3cbb7e NC |
12998 | if (CPU_HAS_SEQ (mips_opts.arch) |
12999 | && -512 <= imm_expr.X_add_number | |
13000 | && imm_expr.X_add_number < 512) | |
13001 | { | |
c0ebe874 | 13002 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13003 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13004 | break; |
13005 | } | |
b0e6f033 | 13006 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13007 | && imm_expr.X_add_number < 0x10000) |
13008 | { | |
c0ebe874 RS |
13009 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13010 | BFD_RELOC_LO16); | |
252b5132 | 13011 | } |
b0e6f033 | 13012 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13013 | && imm_expr.X_add_number < 0) |
13014 | { | |
13015 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13016 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13017 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13018 | } |
dd3cbb7e NC |
13019 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13020 | { | |
13021 | used_at = 1; | |
bad1aba3 | 13022 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13023 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13024 | break; |
13025 | } | |
252b5132 RH |
13026 | else |
13027 | { | |
bad1aba3 | 13028 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13029 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13030 | used_at = 1; |
13031 | } | |
c0ebe874 | 13032 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13033 | break; |
252b5132 | 13034 | |
df58fc94 RS |
13035 | case M_SUB_I: |
13036 | s = "addi"; | |
13037 | s2 = "sub"; | |
13038 | goto do_subi; | |
13039 | case M_SUBU_I: | |
13040 | s = "addiu"; | |
13041 | s2 = "subu"; | |
13042 | goto do_subi; | |
252b5132 RH |
13043 | case M_DSUB_I: |
13044 | dbl = 1; | |
df58fc94 RS |
13045 | s = "daddi"; |
13046 | s2 = "dsub"; | |
13047 | if (!mips_opts.micromips) | |
13048 | goto do_subi; | |
b0e6f033 | 13049 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13050 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13051 | { |
b0e6f033 RS |
13052 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13053 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13054 | break; |
252b5132 | 13055 | } |
df58fc94 | 13056 | goto do_subi_i; |
252b5132 RH |
13057 | case M_DSUBU_I: |
13058 | dbl = 1; | |
df58fc94 RS |
13059 | s = "daddiu"; |
13060 | s2 = "dsubu"; | |
13061 | do_subi: | |
b0e6f033 | 13062 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13063 | && imm_expr.X_add_number <= 0x8000) |
13064 | { | |
13065 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13066 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13067 | break; |
252b5132 | 13068 | } |
df58fc94 | 13069 | do_subi_i: |
8fc2e39e | 13070 | used_at = 1; |
67c0d1eb | 13071 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13072 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13073 | break; |
13074 | ||
13075 | case M_TEQ_I: | |
13076 | s = "teq"; | |
13077 | goto trap; | |
13078 | case M_TGE_I: | |
13079 | s = "tge"; | |
13080 | goto trap; | |
13081 | case M_TGEU_I: | |
13082 | s = "tgeu"; | |
13083 | goto trap; | |
13084 | case M_TLT_I: | |
13085 | s = "tlt"; | |
13086 | goto trap; | |
13087 | case M_TLTU_I: | |
13088 | s = "tltu"; | |
13089 | goto trap; | |
13090 | case M_TNE_I: | |
13091 | s = "tne"; | |
13092 | trap: | |
8fc2e39e | 13093 | used_at = 1; |
bad1aba3 | 13094 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13095 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13096 | break; |
13097 | ||
252b5132 | 13098 | case M_TRUNCWS: |
43841e91 | 13099 | case M_TRUNCWD: |
df58fc94 | 13100 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13101 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13102 | used_at = 1; |
252b5132 RH |
13103 | |
13104 | /* | |
13105 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13106 | * or is there a reason for it? | |
13107 | */ | |
7d10b47d | 13108 | start_noreorder (); |
c0ebe874 RS |
13109 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13110 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13111 | macro_build (NULL, "nop", ""); |
252b5132 | 13112 | expr1.X_add_number = 3; |
c0ebe874 | 13113 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13114 | expr1.X_add_number = 2; |
67c0d1eb RS |
13115 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13116 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13117 | macro_build (NULL, "nop", ""); | |
13118 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13119 | op[0], op[1]); |
13120 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13121 | macro_build (NULL, "nop", ""); |
7d10b47d | 13122 | end_noreorder (); |
252b5132 RH |
13123 | break; |
13124 | ||
f2ae14a1 | 13125 | case M_ULH_AB: |
252b5132 | 13126 | s = "lb"; |
df58fc94 RS |
13127 | s2 = "lbu"; |
13128 | off = 1; | |
13129 | goto uld_st; | |
f2ae14a1 | 13130 | case M_ULHU_AB: |
252b5132 | 13131 | s = "lbu"; |
df58fc94 RS |
13132 | s2 = "lbu"; |
13133 | off = 1; | |
13134 | goto uld_st; | |
f2ae14a1 | 13135 | case M_ULW_AB: |
df58fc94 RS |
13136 | s = "lwl"; |
13137 | s2 = "lwr"; | |
7f3c4072 | 13138 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13139 | off = 3; |
13140 | goto uld_st; | |
f2ae14a1 | 13141 | case M_ULD_AB: |
252b5132 RH |
13142 | s = "ldl"; |
13143 | s2 = "ldr"; | |
7f3c4072 | 13144 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13145 | off = 7; |
df58fc94 | 13146 | goto uld_st; |
f2ae14a1 | 13147 | case M_USH_AB: |
df58fc94 RS |
13148 | s = "sb"; |
13149 | s2 = "sb"; | |
13150 | off = 1; | |
13151 | ust = 1; | |
13152 | goto uld_st; | |
f2ae14a1 | 13153 | case M_USW_AB: |
df58fc94 RS |
13154 | s = "swl"; |
13155 | s2 = "swr"; | |
7f3c4072 | 13156 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13157 | off = 3; |
df58fc94 RS |
13158 | ust = 1; |
13159 | goto uld_st; | |
f2ae14a1 | 13160 | case M_USD_AB: |
df58fc94 RS |
13161 | s = "sdl"; |
13162 | s2 = "sdr"; | |
7f3c4072 | 13163 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13164 | off = 7; |
13165 | ust = 1; | |
13166 | ||
13167 | uld_st: | |
c0ebe874 | 13168 | breg = op[2]; |
f2ae14a1 | 13169 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13170 | ep = &offset_expr; |
13171 | expr1.X_add_number = 0; | |
f2ae14a1 | 13172 | if (large_offset) |
df58fc94 RS |
13173 | { |
13174 | used_at = 1; | |
13175 | tempreg = AT; | |
f2ae14a1 RS |
13176 | if (small_offset_p (0, align, 16)) |
13177 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13178 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13179 | else | |
13180 | { | |
13181 | load_address (tempreg, ep, &used_at); | |
13182 | if (breg != 0) | |
13183 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13184 | tempreg, tempreg, breg); | |
13185 | } | |
13186 | offset_reloc[0] = BFD_RELOC_LO16; | |
13187 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13188 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13189 | breg = tempreg; |
c0ebe874 | 13190 | tempreg = op[0]; |
df58fc94 RS |
13191 | ep = &expr1; |
13192 | } | |
c0ebe874 | 13193 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13194 | { |
13195 | used_at = 1; | |
13196 | tempreg = AT; | |
13197 | } | |
252b5132 | 13198 | else |
c0ebe874 | 13199 | tempreg = op[0]; |
af22f5b2 | 13200 | |
df58fc94 RS |
13201 | if (off == 1) |
13202 | goto ulh_sh; | |
252b5132 | 13203 | |
90ecf173 | 13204 | if (!target_big_endian) |
df58fc94 | 13205 | ep->X_add_number += off; |
f2ae14a1 | 13206 | if (offbits == 12) |
c8276761 | 13207 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13208 | else |
13209 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13210 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13211 | |
90ecf173 | 13212 | if (!target_big_endian) |
df58fc94 | 13213 | ep->X_add_number -= off; |
252b5132 | 13214 | else |
df58fc94 | 13215 | ep->X_add_number += off; |
f2ae14a1 | 13216 | if (offbits == 12) |
df58fc94 | 13217 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13218 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13219 | else |
13220 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13221 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13222 | |
df58fc94 | 13223 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13224 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13225 | { |
13226 | /* Protect second load's delay slot. */ | |
13227 | load_delay_nop (); | |
c0ebe874 | 13228 | move_register (op[0], tempreg); |
df58fc94 | 13229 | } |
8fc2e39e | 13230 | break; |
252b5132 | 13231 | |
df58fc94 | 13232 | ulh_sh: |
d6bc6245 | 13233 | used_at = 1; |
df58fc94 RS |
13234 | if (target_big_endian == ust) |
13235 | ep->X_add_number += off; | |
c0ebe874 | 13236 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13237 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13238 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13239 | |
13240 | /* For halfword transfers we need a temporary register to shuffle | |
13241 | bytes. Unfortunately for M_USH_A we have none available before | |
13242 | the next store as AT holds the base address. We deal with this | |
13243 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13244 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13245 | if (ust) |
c0ebe874 | 13246 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13247 | |
13248 | if (target_big_endian == ust) | |
13249 | ep->X_add_number -= off; | |
252b5132 | 13250 | else |
df58fc94 | 13251 | ep->X_add_number += off; |
f2ae14a1 RS |
13252 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13253 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13254 | |
df58fc94 | 13255 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13256 | if (ust && large_offset) |
df58fc94 RS |
13257 | { |
13258 | if (target_big_endian) | |
13259 | ep->X_add_number += off; | |
13260 | else | |
13261 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13262 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13263 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13264 | } |
13265 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13266 | if (!ust || large_offset) |
df58fc94 | 13267 | { |
c0ebe874 | 13268 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13269 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13270 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13271 | } |
252b5132 RH |
13272 | break; |
13273 | ||
13274 | default: | |
13275 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13276 | are added dynamically. */ |
1661c76c | 13277 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13278 | break; |
13279 | } | |
741fe287 | 13280 | if (!mips_opts.at && used_at) |
1661c76c | 13281 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13282 | } |
13283 | ||
13284 | /* Implement macros in mips16 mode. */ | |
13285 | ||
13286 | static void | |
17a2f251 | 13287 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13288 | { |
c0ebe874 | 13289 | const struct mips_operand_array *operands; |
252b5132 | 13290 | int mask; |
c0ebe874 | 13291 | int tmp; |
252b5132 RH |
13292 | expressionS expr1; |
13293 | int dbl; | |
13294 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13295 | unsigned int op[MAX_OPERANDS]; |
13296 | unsigned int i; | |
252b5132 RH |
13297 | |
13298 | mask = ip->insn_mo->mask; | |
13299 | ||
c0ebe874 RS |
13300 | operands = insn_operands (ip); |
13301 | for (i = 0; i < MAX_OPERANDS; i++) | |
13302 | if (operands->operand[i]) | |
13303 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13304 | else | |
13305 | op[i] = -1; | |
252b5132 | 13306 | |
252b5132 RH |
13307 | expr1.X_op = O_constant; |
13308 | expr1.X_op_symbol = NULL; | |
13309 | expr1.X_add_symbol = NULL; | |
13310 | expr1.X_add_number = 1; | |
13311 | ||
13312 | dbl = 0; | |
13313 | ||
13314 | switch (mask) | |
13315 | { | |
13316 | default: | |
b37df7c4 | 13317 | abort (); |
252b5132 RH |
13318 | |
13319 | case M_DDIV_3: | |
13320 | dbl = 1; | |
13321 | case M_DIV_3: | |
13322 | s = "mflo"; | |
13323 | goto do_div3; | |
13324 | case M_DREM_3: | |
13325 | dbl = 1; | |
13326 | case M_REM_3: | |
13327 | s = "mfhi"; | |
13328 | do_div3: | |
7d10b47d | 13329 | start_noreorder (); |
c0ebe874 | 13330 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]); |
252b5132 | 13331 | expr1.X_add_number = 2; |
c0ebe874 | 13332 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13333 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13334 | |
252b5132 RH |
13335 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13336 | since that causes an overflow. We should do that as well, | |
13337 | but I don't see how to do the comparisons without a temporary | |
13338 | register. */ | |
7d10b47d | 13339 | end_noreorder (); |
c0ebe874 | 13340 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13341 | break; |
13342 | ||
13343 | case M_DIVU_3: | |
13344 | s = "divu"; | |
13345 | s2 = "mflo"; | |
13346 | goto do_divu3; | |
13347 | case M_REMU_3: | |
13348 | s = "divu"; | |
13349 | s2 = "mfhi"; | |
13350 | goto do_divu3; | |
13351 | case M_DDIVU_3: | |
13352 | s = "ddivu"; | |
13353 | s2 = "mflo"; | |
13354 | goto do_divu3; | |
13355 | case M_DREMU_3: | |
13356 | s = "ddivu"; | |
13357 | s2 = "mfhi"; | |
13358 | do_divu3: | |
7d10b47d | 13359 | start_noreorder (); |
c0ebe874 | 13360 | macro_build (NULL, s, "0,x,y", op[1], op[2]); |
252b5132 | 13361 | expr1.X_add_number = 2; |
c0ebe874 | 13362 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13363 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13364 | end_noreorder (); |
c0ebe874 | 13365 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13366 | break; |
13367 | ||
13368 | case M_DMUL: | |
13369 | dbl = 1; | |
13370 | case M_MUL: | |
c0ebe874 RS |
13371 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13372 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13373 | break; |
252b5132 RH |
13374 | |
13375 | case M_DSUBU_I: | |
13376 | dbl = 1; | |
13377 | goto do_subu; | |
13378 | case M_SUBU_I: | |
13379 | do_subu: | |
252b5132 | 13380 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13381 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]); |
252b5132 RH |
13382 | break; |
13383 | ||
13384 | case M_SUBU_I_2: | |
252b5132 | 13385 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13386 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13387 | break; |
13388 | ||
13389 | case M_DSUBU_I_2: | |
252b5132 | 13390 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13391 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13392 | break; |
13393 | ||
13394 | case M_BEQ: | |
13395 | s = "cmp"; | |
13396 | s2 = "bteqz"; | |
13397 | goto do_branch; | |
13398 | case M_BNE: | |
13399 | s = "cmp"; | |
13400 | s2 = "btnez"; | |
13401 | goto do_branch; | |
13402 | case M_BLT: | |
13403 | s = "slt"; | |
13404 | s2 = "btnez"; | |
13405 | goto do_branch; | |
13406 | case M_BLTU: | |
13407 | s = "sltu"; | |
13408 | s2 = "btnez"; | |
13409 | goto do_branch; | |
13410 | case M_BLE: | |
13411 | s = "slt"; | |
13412 | s2 = "bteqz"; | |
13413 | goto do_reverse_branch; | |
13414 | case M_BLEU: | |
13415 | s = "sltu"; | |
13416 | s2 = "bteqz"; | |
13417 | goto do_reverse_branch; | |
13418 | case M_BGE: | |
13419 | s = "slt"; | |
13420 | s2 = "bteqz"; | |
13421 | goto do_branch; | |
13422 | case M_BGEU: | |
13423 | s = "sltu"; | |
13424 | s2 = "bteqz"; | |
13425 | goto do_branch; | |
13426 | case M_BGT: | |
13427 | s = "slt"; | |
13428 | s2 = "btnez"; | |
13429 | goto do_reverse_branch; | |
13430 | case M_BGTU: | |
13431 | s = "sltu"; | |
13432 | s2 = "btnez"; | |
13433 | ||
13434 | do_reverse_branch: | |
c0ebe874 RS |
13435 | tmp = op[1]; |
13436 | op[1] = op[0]; | |
13437 | op[0] = tmp; | |
252b5132 RH |
13438 | |
13439 | do_branch: | |
c0ebe874 | 13440 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13441 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13442 | break; |
13443 | ||
13444 | case M_BEQ_I: | |
13445 | s = "cmpi"; | |
13446 | s2 = "bteqz"; | |
13447 | s3 = "x,U"; | |
13448 | goto do_branch_i; | |
13449 | case M_BNE_I: | |
13450 | s = "cmpi"; | |
13451 | s2 = "btnez"; | |
13452 | s3 = "x,U"; | |
13453 | goto do_branch_i; | |
13454 | case M_BLT_I: | |
13455 | s = "slti"; | |
13456 | s2 = "btnez"; | |
13457 | s3 = "x,8"; | |
13458 | goto do_branch_i; | |
13459 | case M_BLTU_I: | |
13460 | s = "sltiu"; | |
13461 | s2 = "btnez"; | |
13462 | s3 = "x,8"; | |
13463 | goto do_branch_i; | |
13464 | case M_BLE_I: | |
13465 | s = "slti"; | |
13466 | s2 = "btnez"; | |
13467 | s3 = "x,8"; | |
13468 | goto do_addone_branch_i; | |
13469 | case M_BLEU_I: | |
13470 | s = "sltiu"; | |
13471 | s2 = "btnez"; | |
13472 | s3 = "x,8"; | |
13473 | goto do_addone_branch_i; | |
13474 | case M_BGE_I: | |
13475 | s = "slti"; | |
13476 | s2 = "bteqz"; | |
13477 | s3 = "x,8"; | |
13478 | goto do_branch_i; | |
13479 | case M_BGEU_I: | |
13480 | s = "sltiu"; | |
13481 | s2 = "bteqz"; | |
13482 | s3 = "x,8"; | |
13483 | goto do_branch_i; | |
13484 | case M_BGT_I: | |
13485 | s = "slti"; | |
13486 | s2 = "bteqz"; | |
13487 | s3 = "x,8"; | |
13488 | goto do_addone_branch_i; | |
13489 | case M_BGTU_I: | |
13490 | s = "sltiu"; | |
13491 | s2 = "bteqz"; | |
13492 | s3 = "x,8"; | |
13493 | ||
13494 | do_addone_branch_i: | |
252b5132 RH |
13495 | ++imm_expr.X_add_number; |
13496 | ||
13497 | do_branch_i: | |
c0ebe874 | 13498 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13499 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13500 | break; |
13501 | ||
13502 | case M_ABS: | |
13503 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13504 | macro_build (&expr1, "slti", "x,8", op[1]); |
13505 | if (op[0] != op[1]) | |
13506 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13507 | expr1.X_add_number = 2; |
67c0d1eb | 13508 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13509 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13510 | break; |
252b5132 RH |
13511 | } |
13512 | } | |
13513 | ||
14daeee3 RS |
13514 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13515 | opcode bits in *OPCODE_EXTRA. */ | |
13516 | ||
13517 | static struct mips_opcode * | |
13518 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13519 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13520 | { |
13521 | char *name, *dot, *p; | |
13522 | unsigned int mask, suffix; | |
da8bca91 | 13523 | ssize_t opend; |
14daeee3 RS |
13524 | struct mips_opcode *insn; |
13525 | ||
13526 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
13527 | name = alloca (length + 1); | |
13528 | memcpy (name, start, length); | |
13529 | name[length] = '\0'; | |
13530 | ||
13531 | /* Look up the instruction as-is. */ | |
13532 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13533 | if (insn) |
14daeee3 RS |
13534 | return insn; |
13535 | ||
13536 | dot = strchr (name, '.'); | |
13537 | if (dot && dot[1]) | |
13538 | { | |
13539 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13540 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13541 | if (*p == 0 && mask != 0) | |
13542 | { | |
13543 | *dot = 0; | |
13544 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13545 | *dot = '.'; | |
13546 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13547 | { | |
13548 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
13549 | return insn; | |
13550 | } | |
13551 | } | |
13552 | } | |
13553 | ||
13554 | if (mips_opts.micromips) | |
13555 | { | |
13556 | /* See if there's an instruction size override suffix, | |
13557 | either `16' or `32', at the end of the mnemonic proper, | |
13558 | that defines the operation, i.e. before the first `.' | |
13559 | character if any. Strip it and retry. */ | |
13560 | opend = dot != NULL ? dot - name : length; | |
13561 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13562 | suffix = 2; | |
13563 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13564 | suffix = 4; | |
13565 | else | |
13566 | suffix = 0; | |
13567 | if (suffix) | |
13568 | { | |
13569 | memcpy (name + opend - 2, name + opend, length - opend + 1); | |
13570 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13571 | if (insn) |
14daeee3 RS |
13572 | { |
13573 | forced_insn_length = suffix; | |
13574 | return insn; | |
13575 | } | |
13576 | } | |
13577 | } | |
13578 | ||
13579 | return NULL; | |
13580 | } | |
13581 | ||
77bd4346 | 13582 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13583 | is a macro, set imm_expr and offset_expr to the values associated |
13584 | with "I" and "A" operands respectively. Otherwise store the value | |
13585 | of the relocatable field (if any) in offset_expr. In both cases | |
13586 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13587 | |
13588 | static void | |
60f20e8b | 13589 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13590 | { |
60f20e8b | 13591 | const struct mips_opcode *first, *past; |
df58fc94 | 13592 | struct hash_control *hash; |
a92713e6 | 13593 | char format; |
14daeee3 | 13594 | size_t end; |
a92713e6 | 13595 | struct mips_operand_token *tokens; |
14daeee3 | 13596 | unsigned int opcode_extra; |
252b5132 | 13597 | |
df58fc94 RS |
13598 | if (mips_opts.micromips) |
13599 | { | |
13600 | hash = micromips_op_hash; | |
13601 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
13602 | } | |
13603 | else | |
13604 | { | |
13605 | hash = op_hash; | |
13606 | past = &mips_opcodes[NUMOPCODES]; | |
13607 | } | |
13608 | forced_insn_length = 0; | |
14daeee3 | 13609 | opcode_extra = 0; |
252b5132 | 13610 | |
df58fc94 | 13611 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
13612 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
13613 | continue; | |
bdaaa2e1 | 13614 | |
60f20e8b RS |
13615 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
13616 | if (first == NULL) | |
252b5132 | 13617 | { |
1661c76c | 13618 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 13619 | return; |
252b5132 RH |
13620 | } |
13621 | ||
60f20e8b | 13622 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 13623 | format = 'f'; |
60f20e8b | 13624 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
13625 | format = 'd'; |
13626 | else | |
13627 | format = 0; | |
13628 | tokens = mips_parse_arguments (str + end, format); | |
13629 | if (!tokens) | |
13630 | return; | |
13631 | ||
60f20e8b RS |
13632 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
13633 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 13634 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 13635 | |
e3de51ce | 13636 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13637 | } |
13638 | ||
77bd4346 RS |
13639 | /* As for mips_ip, but used when assembling MIPS16 code. |
13640 | Also set forced_insn_length to the resulting instruction size in | |
13641 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13642 | |
13643 | static void | |
60f20e8b | 13644 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13645 | { |
1a00e612 | 13646 | char *end, *s, c; |
60f20e8b | 13647 | struct mips_opcode *first; |
a92713e6 | 13648 | struct mips_operand_token *tokens; |
252b5132 | 13649 | |
df58fc94 | 13650 | forced_insn_length = 0; |
252b5132 | 13651 | |
3882b010 | 13652 | for (s = str; ISLOWER (*s); ++s) |
252b5132 | 13653 | ; |
1a00e612 RS |
13654 | end = s; |
13655 | c = *end; | |
13656 | switch (c) | |
252b5132 RH |
13657 | { |
13658 | case '\0': | |
13659 | break; | |
13660 | ||
13661 | case ' ': | |
1a00e612 | 13662 | s++; |
252b5132 RH |
13663 | break; |
13664 | ||
13665 | case '.': | |
13666 | if (s[1] == 't' && s[2] == ' ') | |
13667 | { | |
df58fc94 | 13668 | forced_insn_length = 2; |
252b5132 RH |
13669 | s += 3; |
13670 | break; | |
13671 | } | |
13672 | else if (s[1] == 'e' && s[2] == ' ') | |
13673 | { | |
df58fc94 | 13674 | forced_insn_length = 4; |
252b5132 RH |
13675 | s += 3; |
13676 | break; | |
13677 | } | |
13678 | /* Fall through. */ | |
13679 | default: | |
1661c76c | 13680 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13681 | return; |
13682 | } | |
13683 | ||
df58fc94 RS |
13684 | if (mips_opts.noautoextend && !forced_insn_length) |
13685 | forced_insn_length = 2; | |
252b5132 | 13686 | |
1a00e612 | 13687 | *end = 0; |
60f20e8b | 13688 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
13689 | *end = c; |
13690 | ||
60f20e8b | 13691 | if (!first) |
252b5132 | 13692 | { |
1661c76c | 13693 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13694 | return; |
13695 | } | |
13696 | ||
a92713e6 RS |
13697 | tokens = mips_parse_arguments (s, 0); |
13698 | if (!tokens) | |
13699 | return; | |
13700 | ||
60f20e8b | 13701 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 13702 | set_insn_error (0, _("invalid operands")); |
252b5132 | 13703 | |
e3de51ce | 13704 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13705 | } |
13706 | ||
b886a2ab RS |
13707 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
13708 | NBITS is the number of significant bits in VAL. */ | |
13709 | ||
13710 | static unsigned long | |
13711 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
13712 | { | |
13713 | int extval; | |
13714 | if (nbits == 16) | |
13715 | { | |
13716 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13717 | val &= 0x1f; | |
13718 | } | |
13719 | else if (nbits == 15) | |
13720 | { | |
13721 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13722 | val &= 0xf; | |
13723 | } | |
13724 | else | |
13725 | { | |
13726 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13727 | val = 0; | |
13728 | } | |
13729 | return (extval << 16) | val; | |
13730 | } | |
13731 | ||
3ccad066 RS |
13732 | /* Like decode_mips16_operand, but require the operand to be defined and |
13733 | require it to be an integer. */ | |
13734 | ||
13735 | static const struct mips_int_operand * | |
13736 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
13737 | { | |
13738 | const struct mips_operand *operand; | |
13739 | ||
13740 | operand = decode_mips16_operand (type, extended_p); | |
13741 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
13742 | abort (); | |
13743 | return (const struct mips_int_operand *) operand; | |
13744 | } | |
13745 | ||
13746 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
13747 | ||
13748 | static bfd_boolean | |
13749 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
13750 | bfd_reloc_code_real_type reloc, offsetT sval) | |
13751 | { | |
13752 | int min_val, max_val; | |
13753 | ||
13754 | min_val = mips_int_operand_min (operand); | |
13755 | max_val = mips_int_operand_max (operand); | |
13756 | if (reloc != BFD_RELOC_UNUSED) | |
13757 | { | |
13758 | if (min_val < 0) | |
13759 | sval = SEXT_16BIT (sval); | |
13760 | else | |
13761 | sval &= 0xffff; | |
13762 | } | |
13763 | ||
13764 | return (sval >= min_val | |
13765 | && sval <= max_val | |
13766 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
13767 | } | |
13768 | ||
5c04167a RS |
13769 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
13770 | extending it if necessary. The instruction in *INSN may | |
13771 | already be extended. | |
13772 | ||
43c0598f RS |
13773 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
13774 | if none. In the former case, VAL is a 16-bit number with no | |
13775 | defined signedness. | |
13776 | ||
13777 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
13778 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
13779 | |
13780 | static void | |
43c0598f RS |
13781 | mips16_immed (char *file, unsigned int line, int type, |
13782 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 13783 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 13784 | { |
3ccad066 RS |
13785 | const struct mips_int_operand *operand; |
13786 | unsigned int uval, length; | |
252b5132 | 13787 | |
3ccad066 RS |
13788 | operand = mips16_immed_operand (type, FALSE); |
13789 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
13790 | { |
13791 | /* We need an extended instruction. */ | |
13792 | if (user_insn_length == 2) | |
13793 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13794 | else | |
13795 | *insn |= MIPS16_EXTEND; | |
13796 | } | |
13797 | else if (user_insn_length == 4) | |
13798 | { | |
13799 | /* The operand doesn't force an unextended instruction to be extended. | |
13800 | Warn if the user wanted an extended instruction anyway. */ | |
13801 | *insn |= MIPS16_EXTEND; | |
13802 | as_warn_where (file, line, | |
13803 | _("extended operand requested but not required")); | |
13804 | } | |
252b5132 | 13805 | |
3ccad066 RS |
13806 | length = mips16_opcode_length (*insn); |
13807 | if (length == 4) | |
252b5132 | 13808 | { |
3ccad066 RS |
13809 | operand = mips16_immed_operand (type, TRUE); |
13810 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
13811 | as_bad_where (file, line, | |
13812 | _("operand value out of range for instruction")); | |
252b5132 | 13813 | } |
3ccad066 RS |
13814 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
13815 | if (length == 2) | |
13816 | *insn = mips_insert_operand (&operand->root, *insn, uval); | |
252b5132 | 13817 | else |
3ccad066 | 13818 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
13819 | } |
13820 | \f | |
d6f16593 | 13821 | struct percent_op_match |
ad8d3bb3 | 13822 | { |
5e0116d5 RS |
13823 | const char *str; |
13824 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
13825 | }; |
13826 | ||
13827 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 13828 | { |
5e0116d5 | 13829 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
13830 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
13831 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
13832 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
13833 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
13834 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
13835 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
13836 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
13837 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
13838 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
13839 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
13840 | {"%half", BFD_RELOC_16}, | |
13841 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
13842 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
13843 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
13844 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
13845 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
13846 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
13847 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
13848 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
13849 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
13850 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
13851 | {"%hi", BFD_RELOC_HI16_S}, |
13852 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
13853 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
13854 | }; |
13855 | ||
d6f16593 MR |
13856 | static const struct percent_op_match mips16_percent_op[] = |
13857 | { | |
13858 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
13859 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
13860 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
13861 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
13862 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
13863 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
13864 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
13865 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
13866 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
13867 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
13868 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
13869 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
13870 | }; |
13871 | ||
252b5132 | 13872 | |
5e0116d5 RS |
13873 | /* Return true if *STR points to a relocation operator. When returning true, |
13874 | move *STR over the operator and store its relocation code in *RELOC. | |
13875 | Leave both *STR and *RELOC alone when returning false. */ | |
13876 | ||
13877 | static bfd_boolean | |
17a2f251 | 13878 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 13879 | { |
d6f16593 MR |
13880 | const struct percent_op_match *percent_op; |
13881 | size_t limit, i; | |
13882 | ||
13883 | if (mips_opts.mips16) | |
13884 | { | |
13885 | percent_op = mips16_percent_op; | |
13886 | limit = ARRAY_SIZE (mips16_percent_op); | |
13887 | } | |
13888 | else | |
13889 | { | |
13890 | percent_op = mips_percent_op; | |
13891 | limit = ARRAY_SIZE (mips_percent_op); | |
13892 | } | |
76b3015f | 13893 | |
d6f16593 | 13894 | for (i = 0; i < limit; i++) |
5e0116d5 | 13895 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 13896 | { |
3f98094e DJ |
13897 | int len = strlen (percent_op[i].str); |
13898 | ||
13899 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
13900 | continue; | |
13901 | ||
5e0116d5 RS |
13902 | *str += strlen (percent_op[i].str); |
13903 | *reloc = percent_op[i].reloc; | |
394f9b3a | 13904 | |
5e0116d5 RS |
13905 | /* Check whether the output BFD supports this relocation. |
13906 | If not, issue an error and fall back on something safe. */ | |
13907 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 13908 | { |
20203fb9 | 13909 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 13910 | percent_op[i].str); |
01a3f561 | 13911 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 13912 | } |
5e0116d5 | 13913 | return TRUE; |
394f9b3a | 13914 | } |
5e0116d5 | 13915 | return FALSE; |
394f9b3a | 13916 | } |
ad8d3bb3 | 13917 | |
ad8d3bb3 | 13918 | |
5e0116d5 RS |
13919 | /* Parse string STR as a 16-bit relocatable operand. Store the |
13920 | expression in *EP and the relocations in the array starting | |
13921 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 13922 | |
01a3f561 | 13923 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 13924 | |
5e0116d5 | 13925 | static size_t |
17a2f251 TS |
13926 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
13927 | char *str) | |
ad8d3bb3 | 13928 | { |
5e0116d5 RS |
13929 | bfd_reloc_code_real_type reversed_reloc[3]; |
13930 | size_t reloc_index, i; | |
09b8f35a RS |
13931 | int crux_depth, str_depth; |
13932 | char *crux; | |
5e0116d5 RS |
13933 | |
13934 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
13935 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
13936 | of the main expression and with CRUX_DEPTH containing the number | |
13937 | of open brackets at that point. */ | |
13938 | reloc_index = -1; | |
13939 | str_depth = 0; | |
13940 | do | |
fb1b3232 | 13941 | { |
09b8f35a RS |
13942 | reloc_index++; |
13943 | crux = str; | |
13944 | crux_depth = str_depth; | |
13945 | ||
13946 | /* Skip over whitespace and brackets, keeping count of the number | |
13947 | of brackets. */ | |
13948 | while (*str == ' ' || *str == '\t' || *str == '(') | |
13949 | if (*str++ == '(') | |
13950 | str_depth++; | |
5e0116d5 | 13951 | } |
09b8f35a RS |
13952 | while (*str == '%' |
13953 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
13954 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 13955 | |
09b8f35a | 13956 | my_getExpression (ep, crux); |
5e0116d5 | 13957 | str = expr_end; |
394f9b3a | 13958 | |
5e0116d5 | 13959 | /* Match every open bracket. */ |
09b8f35a | 13960 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 13961 | if (*str++ == ')') |
09b8f35a | 13962 | crux_depth--; |
394f9b3a | 13963 | |
09b8f35a | 13964 | if (crux_depth > 0) |
20203fb9 | 13965 | as_bad (_("unclosed '('")); |
394f9b3a | 13966 | |
5e0116d5 | 13967 | expr_end = str; |
252b5132 | 13968 | |
01a3f561 | 13969 | if (reloc_index != 0) |
64bdfcaf RS |
13970 | { |
13971 | prev_reloc_op_frag = frag_now; | |
13972 | for (i = 0; i < reloc_index; i++) | |
13973 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
13974 | } | |
fb1b3232 | 13975 | |
5e0116d5 | 13976 | return reloc_index; |
252b5132 RH |
13977 | } |
13978 | ||
13979 | static void | |
17a2f251 | 13980 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
13981 | { |
13982 | char *save_in; | |
13983 | ||
13984 | save_in = input_line_pointer; | |
13985 | input_line_pointer = str; | |
13986 | expression (ep); | |
13987 | expr_end = input_line_pointer; | |
13988 | input_line_pointer = save_in; | |
252b5132 RH |
13989 | } |
13990 | ||
252b5132 | 13991 | char * |
17a2f251 | 13992 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 13993 | { |
499ac353 | 13994 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
13995 | } |
13996 | ||
13997 | void | |
17a2f251 | 13998 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
13999 | { |
14000 | if (target_big_endian) | |
14001 | number_to_chars_bigendian (buf, val, n); | |
14002 | else | |
14003 | number_to_chars_littleendian (buf, val, n); | |
14004 | } | |
14005 | \f | |
e013f690 TS |
14006 | static int support_64bit_objects(void) |
14007 | { | |
14008 | const char **list, **l; | |
aa3d8fdf | 14009 | int yes; |
e013f690 TS |
14010 | |
14011 | list = bfd_target_list (); | |
14012 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14013 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14014 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14015 | break; |
aa3d8fdf | 14016 | yes = (*l != NULL); |
e013f690 | 14017 | free (list); |
aa3d8fdf | 14018 | return yes; |
e013f690 TS |
14019 | } |
14020 | ||
316f5878 RS |
14021 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14022 | NEW_VALUE. Warn if another value was already specified. Note: | |
14023 | we have to defer parsing the -march and -mtune arguments in order | |
14024 | to handle 'from-abi' correctly, since the ABI might be specified | |
14025 | in a later argument. */ | |
14026 | ||
14027 | static void | |
17a2f251 | 14028 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14029 | { |
14030 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14031 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14032 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14033 | new_value); | |
14034 | ||
14035 | *string_ptr = new_value; | |
14036 | } | |
14037 | ||
252b5132 | 14038 | int |
17a2f251 | 14039 | md_parse_option (int c, char *arg) |
252b5132 | 14040 | { |
c6278170 RS |
14041 | unsigned int i; |
14042 | ||
14043 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14044 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14045 | { | |
919731af | 14046 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14047 | c == mips_ases[i].option_on); |
14048 | return 1; | |
14049 | } | |
14050 | ||
252b5132 RH |
14051 | switch (c) |
14052 | { | |
119d663a NC |
14053 | case OPTION_CONSTRUCT_FLOATS: |
14054 | mips_disable_float_construction = 0; | |
14055 | break; | |
bdaaa2e1 | 14056 | |
119d663a NC |
14057 | case OPTION_NO_CONSTRUCT_FLOATS: |
14058 | mips_disable_float_construction = 1; | |
14059 | break; | |
bdaaa2e1 | 14060 | |
252b5132 RH |
14061 | case OPTION_TRAP: |
14062 | mips_trap = 1; | |
14063 | break; | |
14064 | ||
14065 | case OPTION_BREAK: | |
14066 | mips_trap = 0; | |
14067 | break; | |
14068 | ||
14069 | case OPTION_EB: | |
14070 | target_big_endian = 1; | |
14071 | break; | |
14072 | ||
14073 | case OPTION_EL: | |
14074 | target_big_endian = 0; | |
14075 | break; | |
14076 | ||
14077 | case 'O': | |
4ffff32f TS |
14078 | if (arg == NULL) |
14079 | mips_optimize = 1; | |
14080 | else if (arg[0] == '0') | |
14081 | mips_optimize = 0; | |
14082 | else if (arg[0] == '1') | |
252b5132 RH |
14083 | mips_optimize = 1; |
14084 | else | |
14085 | mips_optimize = 2; | |
14086 | break; | |
14087 | ||
14088 | case 'g': | |
14089 | if (arg == NULL) | |
14090 | mips_debug = 2; | |
14091 | else | |
14092 | mips_debug = atoi (arg); | |
252b5132 RH |
14093 | break; |
14094 | ||
14095 | case OPTION_MIPS1: | |
0b35dfee | 14096 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14097 | break; |
14098 | ||
14099 | case OPTION_MIPS2: | |
0b35dfee | 14100 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14101 | break; |
14102 | ||
14103 | case OPTION_MIPS3: | |
0b35dfee | 14104 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14105 | break; |
14106 | ||
14107 | case OPTION_MIPS4: | |
0b35dfee | 14108 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14109 | break; |
14110 | ||
84ea6cf2 | 14111 | case OPTION_MIPS5: |
0b35dfee | 14112 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14113 | break; |
14114 | ||
e7af610e | 14115 | case OPTION_MIPS32: |
0b35dfee | 14116 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14117 | break; |
14118 | ||
af7ee8bf | 14119 | case OPTION_MIPS32R2: |
0b35dfee | 14120 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14121 | break; |
14122 | ||
ae52f483 | 14123 | case OPTION_MIPS32R3: |
0ae19f05 | 14124 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14125 | break; |
14126 | ||
14127 | case OPTION_MIPS32R5: | |
0ae19f05 | 14128 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14129 | break; |
14130 | ||
7361da2c AB |
14131 | case OPTION_MIPS32R6: |
14132 | file_mips_opts.isa = ISA_MIPS32R6; | |
14133 | break; | |
14134 | ||
5f74bc13 | 14135 | case OPTION_MIPS64R2: |
0b35dfee | 14136 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14137 | break; |
14138 | ||
ae52f483 | 14139 | case OPTION_MIPS64R3: |
0ae19f05 | 14140 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14141 | break; |
14142 | ||
14143 | case OPTION_MIPS64R5: | |
0ae19f05 | 14144 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14145 | break; |
14146 | ||
7361da2c AB |
14147 | case OPTION_MIPS64R6: |
14148 | file_mips_opts.isa = ISA_MIPS64R6; | |
14149 | break; | |
14150 | ||
84ea6cf2 | 14151 | case OPTION_MIPS64: |
0b35dfee | 14152 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14153 | break; |
14154 | ||
ec68c924 | 14155 | case OPTION_MTUNE: |
316f5878 RS |
14156 | mips_set_option_string (&mips_tune_string, arg); |
14157 | break; | |
ec68c924 | 14158 | |
316f5878 RS |
14159 | case OPTION_MARCH: |
14160 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14161 | break; |
14162 | ||
14163 | case OPTION_M4650: | |
316f5878 RS |
14164 | mips_set_option_string (&mips_arch_string, "4650"); |
14165 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14166 | break; |
14167 | ||
14168 | case OPTION_NO_M4650: | |
14169 | break; | |
14170 | ||
14171 | case OPTION_M4010: | |
316f5878 RS |
14172 | mips_set_option_string (&mips_arch_string, "4010"); |
14173 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14174 | break; |
14175 | ||
14176 | case OPTION_NO_M4010: | |
14177 | break; | |
14178 | ||
14179 | case OPTION_M4100: | |
316f5878 RS |
14180 | mips_set_option_string (&mips_arch_string, "4100"); |
14181 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14182 | break; |
14183 | ||
14184 | case OPTION_NO_M4100: | |
14185 | break; | |
14186 | ||
252b5132 | 14187 | case OPTION_M3900: |
316f5878 RS |
14188 | mips_set_option_string (&mips_arch_string, "3900"); |
14189 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14190 | break; |
bdaaa2e1 | 14191 | |
252b5132 RH |
14192 | case OPTION_NO_M3900: |
14193 | break; | |
14194 | ||
df58fc94 | 14195 | case OPTION_MICROMIPS: |
919731af | 14196 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14197 | { |
14198 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14199 | return 0; | |
14200 | } | |
919731af | 14201 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14202 | mips_no_prev_insn (); |
14203 | break; | |
14204 | ||
14205 | case OPTION_NO_MICROMIPS: | |
919731af | 14206 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14207 | mips_no_prev_insn (); |
14208 | break; | |
14209 | ||
252b5132 | 14210 | case OPTION_MIPS16: |
919731af | 14211 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14212 | { |
14213 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14214 | return 0; | |
14215 | } | |
919731af | 14216 | file_mips_opts.mips16 = 1; |
7d10b47d | 14217 | mips_no_prev_insn (); |
252b5132 RH |
14218 | break; |
14219 | ||
14220 | case OPTION_NO_MIPS16: | |
919731af | 14221 | file_mips_opts.mips16 = 0; |
7d10b47d | 14222 | mips_no_prev_insn (); |
252b5132 RH |
14223 | break; |
14224 | ||
6a32d874 CM |
14225 | case OPTION_FIX_24K: |
14226 | mips_fix_24k = 1; | |
14227 | break; | |
14228 | ||
14229 | case OPTION_NO_FIX_24K: | |
14230 | mips_fix_24k = 0; | |
14231 | break; | |
14232 | ||
a8d14a88 CM |
14233 | case OPTION_FIX_RM7000: |
14234 | mips_fix_rm7000 = 1; | |
14235 | break; | |
14236 | ||
14237 | case OPTION_NO_FIX_RM7000: | |
14238 | mips_fix_rm7000 = 0; | |
14239 | break; | |
14240 | ||
c67a084a NC |
14241 | case OPTION_FIX_LOONGSON2F_JUMP: |
14242 | mips_fix_loongson2f_jump = TRUE; | |
14243 | break; | |
14244 | ||
14245 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14246 | mips_fix_loongson2f_jump = FALSE; | |
14247 | break; | |
14248 | ||
14249 | case OPTION_FIX_LOONGSON2F_NOP: | |
14250 | mips_fix_loongson2f_nop = TRUE; | |
14251 | break; | |
14252 | ||
14253 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14254 | mips_fix_loongson2f_nop = FALSE; | |
14255 | break; | |
14256 | ||
d766e8ec RS |
14257 | case OPTION_FIX_VR4120: |
14258 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14259 | break; |
14260 | ||
d766e8ec RS |
14261 | case OPTION_NO_FIX_VR4120: |
14262 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14263 | break; |
14264 | ||
7d8e00cf RS |
14265 | case OPTION_FIX_VR4130: |
14266 | mips_fix_vr4130 = 1; | |
14267 | break; | |
14268 | ||
14269 | case OPTION_NO_FIX_VR4130: | |
14270 | mips_fix_vr4130 = 0; | |
14271 | break; | |
14272 | ||
d954098f DD |
14273 | case OPTION_FIX_CN63XXP1: |
14274 | mips_fix_cn63xxp1 = TRUE; | |
14275 | break; | |
14276 | ||
14277 | case OPTION_NO_FIX_CN63XXP1: | |
14278 | mips_fix_cn63xxp1 = FALSE; | |
14279 | break; | |
14280 | ||
4a6a3df4 AO |
14281 | case OPTION_RELAX_BRANCH: |
14282 | mips_relax_branch = 1; | |
14283 | break; | |
14284 | ||
14285 | case OPTION_NO_RELAX_BRANCH: | |
14286 | mips_relax_branch = 0; | |
14287 | break; | |
14288 | ||
833794fc | 14289 | case OPTION_INSN32: |
919731af | 14290 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14291 | break; |
14292 | ||
14293 | case OPTION_NO_INSN32: | |
919731af | 14294 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14295 | break; |
14296 | ||
aa6975fb ILT |
14297 | case OPTION_MSHARED: |
14298 | mips_in_shared = TRUE; | |
14299 | break; | |
14300 | ||
14301 | case OPTION_MNO_SHARED: | |
14302 | mips_in_shared = FALSE; | |
14303 | break; | |
14304 | ||
aed1a261 | 14305 | case OPTION_MSYM32: |
919731af | 14306 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14307 | break; |
14308 | ||
14309 | case OPTION_MNO_SYM32: | |
919731af | 14310 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14311 | break; |
14312 | ||
252b5132 RH |
14313 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14314 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14315 | intended to be compatible with Irix 5. */ | |
14316 | case OPTION_CALL_SHARED: | |
252b5132 | 14317 | mips_pic = SVR4_PIC; |
143d77c5 | 14318 | mips_abicalls = TRUE; |
252b5132 RH |
14319 | break; |
14320 | ||
861fb55a | 14321 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14322 | mips_pic = NO_PIC; |
14323 | mips_abicalls = TRUE; | |
14324 | break; | |
14325 | ||
252b5132 | 14326 | case OPTION_NON_SHARED: |
252b5132 | 14327 | mips_pic = NO_PIC; |
143d77c5 | 14328 | mips_abicalls = FALSE; |
252b5132 RH |
14329 | break; |
14330 | ||
44075ae2 TS |
14331 | /* The -xgot option tells the assembler to use 32 bit offsets |
14332 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14333 | compatibility. */ |
14334 | case OPTION_XGOT: | |
14335 | mips_big_got = 1; | |
14336 | break; | |
14337 | ||
14338 | case 'G': | |
6caf9ef4 TS |
14339 | g_switch_value = atoi (arg); |
14340 | g_switch_seen = 1; | |
252b5132 RH |
14341 | break; |
14342 | ||
34ba82a8 TS |
14343 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14344 | and -mabi=64. */ | |
252b5132 | 14345 | case OPTION_32: |
f3ded42a | 14346 | mips_abi = O32_ABI; |
252b5132 RH |
14347 | break; |
14348 | ||
e013f690 | 14349 | case OPTION_N32: |
316f5878 | 14350 | mips_abi = N32_ABI; |
e013f690 | 14351 | break; |
252b5132 | 14352 | |
e013f690 | 14353 | case OPTION_64: |
316f5878 | 14354 | mips_abi = N64_ABI; |
f43abd2b | 14355 | if (!support_64bit_objects()) |
1661c76c | 14356 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14357 | break; |
14358 | ||
c97ef257 | 14359 | case OPTION_GP32: |
bad1aba3 | 14360 | file_mips_opts.gp = 32; |
c97ef257 AH |
14361 | break; |
14362 | ||
14363 | case OPTION_GP64: | |
bad1aba3 | 14364 | file_mips_opts.gp = 64; |
c97ef257 | 14365 | break; |
252b5132 | 14366 | |
ca4e0257 | 14367 | case OPTION_FP32: |
0b35dfee | 14368 | file_mips_opts.fp = 32; |
316f5878 RS |
14369 | break; |
14370 | ||
351cdf24 MF |
14371 | case OPTION_FPXX: |
14372 | file_mips_opts.fp = 0; | |
14373 | break; | |
14374 | ||
316f5878 | 14375 | case OPTION_FP64: |
0b35dfee | 14376 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14377 | break; |
14378 | ||
351cdf24 MF |
14379 | case OPTION_ODD_SPREG: |
14380 | file_mips_opts.oddspreg = 1; | |
14381 | break; | |
14382 | ||
14383 | case OPTION_NO_ODD_SPREG: | |
14384 | file_mips_opts.oddspreg = 0; | |
14385 | break; | |
14386 | ||
037b32b9 | 14387 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14388 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14389 | break; |
14390 | ||
14391 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14392 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14393 | break; |
14394 | ||
14395 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14396 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14397 | break; |
14398 | ||
14399 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14400 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14401 | break; |
14402 | ||
252b5132 | 14403 | case OPTION_MABI: |
e013f690 | 14404 | if (strcmp (arg, "32") == 0) |
316f5878 | 14405 | mips_abi = O32_ABI; |
e013f690 | 14406 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14407 | mips_abi = O64_ABI; |
e013f690 | 14408 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14409 | mips_abi = N32_ABI; |
e013f690 TS |
14410 | else if (strcmp (arg, "64") == 0) |
14411 | { | |
316f5878 | 14412 | mips_abi = N64_ABI; |
e013f690 | 14413 | if (! support_64bit_objects()) |
1661c76c | 14414 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14415 | "format")); |
14416 | } | |
14417 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14418 | mips_abi = EABI_ABI; |
e013f690 | 14419 | else |
da0e507f TS |
14420 | { |
14421 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14422 | return 0; | |
14423 | } | |
252b5132 RH |
14424 | break; |
14425 | ||
6b76fefe | 14426 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14427 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14428 | break; |
14429 | ||
9ee72ff1 | 14430 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14431 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14432 | break; |
14433 | ||
ecb4347a | 14434 | case OPTION_MDEBUG: |
b34976b6 | 14435 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14436 | break; |
14437 | ||
14438 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14439 | mips_flag_mdebug = FALSE; |
ecb4347a | 14440 | break; |
dcd410fe RO |
14441 | |
14442 | case OPTION_PDR: | |
14443 | mips_flag_pdr = TRUE; | |
14444 | break; | |
14445 | ||
14446 | case OPTION_NO_PDR: | |
14447 | mips_flag_pdr = FALSE; | |
14448 | break; | |
0a44bf69 RS |
14449 | |
14450 | case OPTION_MVXWORKS_PIC: | |
14451 | mips_pic = VXWORKS_PIC; | |
14452 | break; | |
ecb4347a | 14453 | |
ba92f887 MR |
14454 | case OPTION_NAN: |
14455 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14456 | mips_nan2008 = 1; |
ba92f887 | 14457 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14458 | mips_nan2008 = 0; |
ba92f887 MR |
14459 | else |
14460 | { | |
1661c76c | 14461 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14462 | return 0; |
14463 | } | |
14464 | break; | |
14465 | ||
252b5132 RH |
14466 | default: |
14467 | return 0; | |
14468 | } | |
14469 | ||
c67a084a NC |
14470 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14471 | ||
252b5132 RH |
14472 | return 1; |
14473 | } | |
316f5878 | 14474 | \f |
919731af | 14475 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14476 | |
316f5878 | 14477 | static void |
17a2f251 | 14478 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14479 | { |
14480 | if (info != 0) | |
fef14a42 | 14481 | mips_tune = info->cpu; |
316f5878 | 14482 | } |
80cc45a5 | 14483 | |
34ba82a8 | 14484 | |
252b5132 | 14485 | void |
17a2f251 | 14486 | mips_after_parse_args (void) |
e9670677 | 14487 | { |
fef14a42 TS |
14488 | const struct mips_cpu_info *arch_info = 0; |
14489 | const struct mips_cpu_info *tune_info = 0; | |
14490 | ||
e9670677 | 14491 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14492 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14493 | { |
6caf9ef4 | 14494 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14495 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14496 | g_switch_value = 0; |
14497 | } | |
14498 | ||
cac012d6 AO |
14499 | if (mips_abi == NO_ABI) |
14500 | mips_abi = MIPS_DEFAULT_ABI; | |
14501 | ||
919731af | 14502 | /* The following code determines the architecture. |
22923709 RS |
14503 | Similar code was added to GCC 3.3 (see override_options() in |
14504 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14505 | as much as possible. */ | |
e9670677 | 14506 | |
316f5878 | 14507 | if (mips_arch_string != 0) |
fef14a42 | 14508 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14509 | |
0b35dfee | 14510 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14511 | { |
0b35dfee | 14512 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14513 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14514 | the -march selection (if any). */ |
fef14a42 | 14515 | if (arch_info != 0) |
e9670677 | 14516 | { |
316f5878 RS |
14517 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14518 | There's no harm in specifying both as long as the ISA levels | |
14519 | are the same. */ | |
0b35dfee | 14520 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14521 | as_bad (_("-%s conflicts with the other architecture options," |
14522 | " which imply -%s"), | |
0b35dfee | 14523 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14524 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14525 | } |
316f5878 | 14526 | else |
0b35dfee | 14527 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14528 | } |
14529 | ||
fef14a42 | 14530 | if (arch_info == 0) |
95bfe26e MF |
14531 | { |
14532 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14533 | gas_assert (arch_info); | |
14534 | } | |
e9670677 | 14535 | |
fef14a42 | 14536 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14537 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14538 | arch_info->name); |
14539 | ||
919731af | 14540 | file_mips_opts.arch = arch_info->cpu; |
14541 | file_mips_opts.isa = arch_info->isa; | |
14542 | ||
14543 | /* Set up initial mips_opts state. */ | |
14544 | mips_opts = file_mips_opts; | |
14545 | ||
14546 | /* The register size inference code is now placed in | |
14547 | file_mips_check_options. */ | |
fef14a42 | 14548 | |
0b35dfee | 14549 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
14550 | processor. */ | |
fef14a42 TS |
14551 | if (mips_tune_string != 0) |
14552 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14553 | |
fef14a42 TS |
14554 | if (tune_info == 0) |
14555 | mips_set_tune (arch_info); | |
14556 | else | |
14557 | mips_set_tune (tune_info); | |
e9670677 | 14558 | |
ecb4347a | 14559 | if (mips_flag_mdebug < 0) |
e8044f35 | 14560 | mips_flag_mdebug = 0; |
e9670677 MR |
14561 | } |
14562 | \f | |
14563 | void | |
17a2f251 | 14564 | mips_init_after_args (void) |
252b5132 RH |
14565 | { |
14566 | /* initialize opcodes */ | |
14567 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14568 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14569 | } |
14570 | ||
14571 | long | |
17a2f251 | 14572 | md_pcrel_from (fixS *fixP) |
252b5132 | 14573 | { |
a7ebbfdf TS |
14574 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14575 | switch (fixP->fx_r_type) | |
14576 | { | |
df58fc94 RS |
14577 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14578 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14579 | /* Return the address of the delay slot. */ | |
14580 | return addr + 2; | |
14581 | ||
14582 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14583 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf | 14584 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
14585 | case BFD_RELOC_MIPS_21_PCREL_S2: |
14586 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
14587 | case BFD_RELOC_MIPS_JMP: |
14588 | /* Return the address of the delay slot. */ | |
14589 | return addr + 4; | |
df58fc94 | 14590 | |
a7ebbfdf TS |
14591 | default: |
14592 | return addr; | |
14593 | } | |
252b5132 RH |
14594 | } |
14595 | ||
252b5132 RH |
14596 | /* This is called before the symbol table is processed. In order to |
14597 | work with gcc when using mips-tfile, we must keep all local labels. | |
14598 | However, in other cases, we want to discard them. If we were | |
14599 | called with -g, but we didn't see any debugging information, it may | |
14600 | mean that gcc is smuggling debugging information through to | |
14601 | mips-tfile, in which case we must generate all local labels. */ | |
14602 | ||
14603 | void | |
17a2f251 | 14604 | mips_frob_file_before_adjust (void) |
252b5132 RH |
14605 | { |
14606 | #ifndef NO_ECOFF_DEBUGGING | |
14607 | if (ECOFF_DEBUGGING | |
14608 | && mips_debug != 0 | |
14609 | && ! ecoff_debugging_seen) | |
14610 | flag_keep_locals = 1; | |
14611 | #endif | |
14612 | } | |
14613 | ||
3b91255e | 14614 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 14615 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
14616 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
14617 | relocation operators. | |
14618 | ||
14619 | For our purposes, a %lo() expression matches a %got() or %hi() | |
14620 | expression if: | |
14621 | ||
14622 | (a) it refers to the same symbol; and | |
14623 | (b) the offset applied in the %lo() expression is no lower than | |
14624 | the offset applied in the %got() or %hi(). | |
14625 | ||
14626 | (b) allows us to cope with code like: | |
14627 | ||
14628 | lui $4,%hi(foo) | |
14629 | lh $4,%lo(foo+2)($4) | |
14630 | ||
14631 | ...which is legal on RELA targets, and has a well-defined behaviour | |
14632 | if the user knows that adding 2 to "foo" will not induce a carry to | |
14633 | the high 16 bits. | |
14634 | ||
14635 | When several %lo()s match a particular %got() or %hi(), we use the | |
14636 | following rules to distinguish them: | |
14637 | ||
14638 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
14639 | higher offsets. | |
14640 | ||
14641 | (2) %lo()s with no matching %got() or %hi() are better than those | |
14642 | that already have a matching %got() or %hi(). | |
14643 | ||
14644 | (3) later %lo()s are better than earlier %lo()s. | |
14645 | ||
14646 | These rules are applied in order. | |
14647 | ||
14648 | (1) means, among other things, that %lo()s with identical offsets are | |
14649 | chosen if they exist. | |
14650 | ||
14651 | (2) means that we won't associate several high-part relocations with | |
14652 | the same low-part relocation unless there's no alternative. Having | |
14653 | several high parts for the same low part is a GNU extension; this rule | |
14654 | allows careful users to avoid it. | |
14655 | ||
14656 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
14657 | with the last high-part relocation being at the front of the list. | |
14658 | It therefore makes sense to choose the last matching low-part | |
14659 | relocation, all other things being equal. It's also easier | |
14660 | to code that way. */ | |
252b5132 RH |
14661 | |
14662 | void | |
17a2f251 | 14663 | mips_frob_file (void) |
252b5132 RH |
14664 | { |
14665 | struct mips_hi_fixup *l; | |
35903be0 | 14666 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
14667 | |
14668 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
14669 | { | |
14670 | segment_info_type *seginfo; | |
3b91255e RS |
14671 | bfd_boolean matched_lo_p; |
14672 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 14673 | |
9c2799c2 | 14674 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 14675 | |
5919d012 | 14676 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
14677 | there isn't supposed to be a matching LO. Ignore %gots against |
14678 | constants; we'll report an error for those later. */ | |
738e5348 | 14679 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
14680 | && !(l->fixp->fx_addsy |
14681 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
14682 | continue; |
14683 | ||
14684 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
14685 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
14686 | continue; |
14687 | ||
252b5132 | 14688 | seginfo = seg_info (l->seg); |
252b5132 | 14689 | |
3b91255e RS |
14690 | /* Set HI_POS to the position of this relocation in the chain. |
14691 | Set LO_POS to the position of the chosen low-part relocation. | |
14692 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
14693 | relocation that matches an immediately-preceding high-part | |
14694 | relocation. */ | |
14695 | hi_pos = NULL; | |
14696 | lo_pos = NULL; | |
14697 | matched_lo_p = FALSE; | |
738e5348 | 14698 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 14699 | |
3b91255e RS |
14700 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
14701 | { | |
14702 | if (*pos == l->fixp) | |
14703 | hi_pos = pos; | |
14704 | ||
35903be0 | 14705 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 14706 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
14707 | && (*pos)->fx_offset >= l->fixp->fx_offset |
14708 | && (lo_pos == NULL | |
14709 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
14710 | || (!matched_lo_p | |
14711 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
14712 | lo_pos = pos; | |
14713 | ||
14714 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
14715 | && fixup_has_matching_lo_p (*pos)); | |
14716 | } | |
14717 | ||
14718 | /* If we found a match, remove the high-part relocation from its | |
14719 | current position and insert it before the low-part relocation. | |
14720 | Make the offsets match so that fixup_has_matching_lo_p() | |
14721 | will return true. | |
14722 | ||
14723 | We don't warn about unmatched high-part relocations since some | |
14724 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
14725 | instructions. */ | |
14726 | if (lo_pos != NULL) | |
14727 | { | |
14728 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
14729 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 14730 | { |
3b91255e RS |
14731 | *hi_pos = l->fixp->fx_next; |
14732 | l->fixp->fx_next = *lo_pos; | |
14733 | *lo_pos = l->fixp; | |
252b5132 | 14734 | } |
252b5132 RH |
14735 | } |
14736 | } | |
14737 | } | |
14738 | ||
252b5132 | 14739 | int |
17a2f251 | 14740 | mips_force_relocation (fixS *fixp) |
252b5132 | 14741 | { |
ae6063d4 | 14742 | if (generic_force_reloc (fixp)) |
252b5132 RH |
14743 | return 1; |
14744 | ||
df58fc94 RS |
14745 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
14746 | so that the linker relaxation can update targets. */ | |
14747 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
14748 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
14749 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
14750 | return 1; | |
14751 | ||
7361da2c AB |
14752 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
14753 | if (ISA_IS_R6 (mips_opts.isa) | |
14754 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
14755 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
14756 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
14757 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
14758 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
14759 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
14760 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
14761 | return 1; | |
14762 | ||
3e722fb5 | 14763 | return 0; |
252b5132 RH |
14764 | } |
14765 | ||
b886a2ab RS |
14766 | /* Read the instruction associated with RELOC from BUF. */ |
14767 | ||
14768 | static unsigned int | |
14769 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
14770 | { | |
14771 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
14772 | return read_compressed_insn (buf, 4); | |
14773 | else | |
14774 | return read_insn (buf); | |
14775 | } | |
14776 | ||
14777 | /* Write instruction INSN to BUF, given that it has been relocated | |
14778 | by RELOC. */ | |
14779 | ||
14780 | static void | |
14781 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
14782 | unsigned long insn) | |
14783 | { | |
14784 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
14785 | write_compressed_insn (buf, insn, 4); | |
14786 | else | |
14787 | write_insn (buf, insn); | |
14788 | } | |
14789 | ||
252b5132 RH |
14790 | /* Apply a fixup to the object file. */ |
14791 | ||
94f592af | 14792 | void |
55cf6793 | 14793 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 14794 | { |
4d68580a | 14795 | char *buf; |
b886a2ab | 14796 | unsigned long insn; |
a7ebbfdf | 14797 | reloc_howto_type *howto; |
252b5132 | 14798 | |
d56a8dda RS |
14799 | if (fixP->fx_pcrel) |
14800 | switch (fixP->fx_r_type) | |
14801 | { | |
14802 | case BFD_RELOC_16_PCREL_S2: | |
14803 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
14804 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14805 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14806 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
14807 | case BFD_RELOC_MIPS_21_PCREL_S2: |
14808 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
14809 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
14810 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
14811 | case BFD_RELOC_HI16_S_PCREL: | |
14812 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
14813 | break; |
14814 | ||
14815 | case BFD_RELOC_32: | |
14816 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
14817 | break; | |
14818 | ||
14819 | default: | |
14820 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
14821 | _("PC-relative reference to a different section")); | |
14822 | break; | |
14823 | } | |
14824 | ||
14825 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
14826 | that have no MIPS ELF equivalent. */ | |
14827 | if (fixP->fx_r_type != BFD_RELOC_8) | |
14828 | { | |
14829 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
14830 | if (!howto) | |
14831 | return; | |
14832 | } | |
65551fa4 | 14833 | |
df58fc94 RS |
14834 | gas_assert (fixP->fx_size == 2 |
14835 | || fixP->fx_size == 4 | |
d56a8dda | 14836 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
14837 | || fixP->fx_r_type == BFD_RELOC_16 |
14838 | || fixP->fx_r_type == BFD_RELOC_64 | |
14839 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
14840 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 14841 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
14842 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14843 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
14844 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
14845 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 14846 | |
4d68580a | 14847 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 14848 | |
b1dca8ee RS |
14849 | /* Don't treat parts of a composite relocation as done. There are two |
14850 | reasons for this: | |
14851 | ||
14852 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
14853 | should nevertheless be emitted if the first part is. | |
14854 | ||
14855 | (2) In normal usage, composite relocations are never assembly-time | |
14856 | constants. The easiest way of dealing with the pathological | |
14857 | exceptions is to generate a relocation against STN_UNDEF and | |
14858 | leave everything up to the linker. */ | |
3994f87e | 14859 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
14860 | fixP->fx_done = 1; |
14861 | ||
14862 | switch (fixP->fx_r_type) | |
14863 | { | |
3f98094e DJ |
14864 | case BFD_RELOC_MIPS_TLS_GD: |
14865 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
14866 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
14867 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
14868 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
14869 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
14870 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
14871 | case BFD_RELOC_MIPS_TLS_TPREL32: |
14872 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
14873 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
14874 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
14875 | case BFD_RELOC_MICROMIPS_TLS_GD: |
14876 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
14877 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
14878 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
14879 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
14880 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
14881 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
14882 | case BFD_RELOC_MIPS16_TLS_GD: |
14883 | case BFD_RELOC_MIPS16_TLS_LDM: | |
14884 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
14885 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
14886 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
14887 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
14888 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
14889 | if (!fixP->fx_addsy) |
14890 | { | |
14891 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
14892 | _("TLS relocation against a constant")); | |
14893 | break; | |
14894 | } | |
3f98094e DJ |
14895 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
14896 | /* fall through */ | |
14897 | ||
252b5132 | 14898 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
14899 | case BFD_RELOC_MIPS_SHIFT5: |
14900 | case BFD_RELOC_MIPS_SHIFT6: | |
14901 | case BFD_RELOC_MIPS_GOT_DISP: | |
14902 | case BFD_RELOC_MIPS_GOT_PAGE: | |
14903 | case BFD_RELOC_MIPS_GOT_OFST: | |
14904 | case BFD_RELOC_MIPS_SUB: | |
14905 | case BFD_RELOC_MIPS_INSERT_A: | |
14906 | case BFD_RELOC_MIPS_INSERT_B: | |
14907 | case BFD_RELOC_MIPS_DELETE: | |
14908 | case BFD_RELOC_MIPS_HIGHEST: | |
14909 | case BFD_RELOC_MIPS_HIGHER: | |
14910 | case BFD_RELOC_MIPS_SCN_DISP: | |
14911 | case BFD_RELOC_MIPS_REL16: | |
14912 | case BFD_RELOC_MIPS_RELGOT: | |
14913 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
14914 | case BFD_RELOC_HI16: |
14915 | case BFD_RELOC_HI16_S: | |
b886a2ab | 14916 | case BFD_RELOC_LO16: |
cdf6fd85 | 14917 | case BFD_RELOC_GPREL16: |
252b5132 RH |
14918 | case BFD_RELOC_MIPS_LITERAL: |
14919 | case BFD_RELOC_MIPS_CALL16: | |
14920 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 14921 | case BFD_RELOC_GPREL32: |
252b5132 RH |
14922 | case BFD_RELOC_MIPS_GOT_HI16: |
14923 | case BFD_RELOC_MIPS_GOT_LO16: | |
14924 | case BFD_RELOC_MIPS_CALL_HI16: | |
14925 | case BFD_RELOC_MIPS_CALL_LO16: | |
14926 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
14927 | case BFD_RELOC_MIPS16_GOT16: |
14928 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
14929 | case BFD_RELOC_MIPS16_HI16: |
14930 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 14931 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 14932 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
14933 | case BFD_RELOC_MICROMIPS_JMP: |
14934 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
14935 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
14936 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
14937 | case BFD_RELOC_MICROMIPS_SUB: | |
14938 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
14939 | case BFD_RELOC_MICROMIPS_HIGHER: | |
14940 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
14941 | case BFD_RELOC_MICROMIPS_JALR: | |
14942 | case BFD_RELOC_MICROMIPS_HI16: | |
14943 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 14944 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
14945 | case BFD_RELOC_MICROMIPS_GPREL16: |
14946 | case BFD_RELOC_MICROMIPS_LITERAL: | |
14947 | case BFD_RELOC_MICROMIPS_CALL16: | |
14948 | case BFD_RELOC_MICROMIPS_GOT16: | |
14949 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
14950 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
14951 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
14952 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 14953 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
14954 | if (fixP->fx_done) |
14955 | { | |
14956 | offsetT value; | |
14957 | ||
14958 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
14959 | { | |
14960 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
14961 | if (mips16_reloc_p (fixP->fx_r_type)) | |
14962 | insn |= mips16_immed_extend (value, 16); | |
14963 | else | |
14964 | insn |= (value & 0xffff); | |
14965 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
14966 | } | |
14967 | else | |
14968 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 14969 | _("unsupported constant in relocation")); |
b886a2ab | 14970 | } |
252b5132 RH |
14971 | break; |
14972 | ||
252b5132 RH |
14973 | case BFD_RELOC_64: |
14974 | /* This is handled like BFD_RELOC_32, but we output a sign | |
14975 | extended value if we are only 32 bits. */ | |
3e722fb5 | 14976 | if (fixP->fx_done) |
252b5132 RH |
14977 | { |
14978 | if (8 <= sizeof (valueT)) | |
4d68580a | 14979 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
14980 | else |
14981 | { | |
a7ebbfdf | 14982 | valueT hiv; |
252b5132 | 14983 | |
a7ebbfdf | 14984 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
14985 | hiv = 0xffffffff; |
14986 | else | |
14987 | hiv = 0; | |
4d68580a RS |
14988 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
14989 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
14990 | } |
14991 | } | |
14992 | break; | |
14993 | ||
056350c6 | 14994 | case BFD_RELOC_RVA: |
252b5132 | 14995 | case BFD_RELOC_32: |
b47468a6 | 14996 | case BFD_RELOC_32_PCREL: |
252b5132 | 14997 | case BFD_RELOC_16: |
d56a8dda | 14998 | case BFD_RELOC_8: |
252b5132 | 14999 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15000 | value now. This can happen if we have a .word which is not |
15001 | resolved when it appears but is later defined. */ | |
252b5132 | 15002 | if (fixP->fx_done) |
4d68580a | 15003 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15004 | break; |
15005 | ||
7361da2c AB |
15006 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15007 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15008 | if ((*valP & 0x3) != 0) | |
15009 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15010 | _("branch to misaligned address (%lx)"), (long) *valP); | |
15011 | ||
15012 | gas_assert (!fixP->fx_done); | |
15013 | break; | |
15014 | ||
15015 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
0866e94c | 15016 | if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15017 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15018 | _("PC-relative access using misaligned symbol (%lx)"), |
15019 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15020 | if ((fixP->fx_offset & 0x7) != 0) | |
15021 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15022 | _("PC-relative access using misaligned offset (%lx)"), | |
15023 | (long) fixP->fx_offset); | |
7361da2c AB |
15024 | |
15025 | gas_assert (!fixP->fx_done); | |
15026 | break; | |
15027 | ||
15028 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15029 | if ((*valP & 0x3) != 0) | |
15030 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15031 | _("PC-relative access to misaligned address (%lx)"), | |
0866e94c | 15032 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); |
7361da2c AB |
15033 | |
15034 | gas_assert (!fixP->fx_done); | |
15035 | break; | |
15036 | ||
15037 | case BFD_RELOC_HI16_S_PCREL: | |
15038 | case BFD_RELOC_LO16_PCREL: | |
15039 | gas_assert (!fixP->fx_done); | |
15040 | break; | |
15041 | ||
252b5132 | 15042 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15043 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15044 | as_bad_where (fixP->fx_file, fixP->fx_line, |
1661c76c | 15045 | _("branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15046 | |
54f4ddb3 TS |
15047 | /* We need to save the bits in the instruction since fixup_segment() |
15048 | might be deleting the relocation entry (i.e., a branch within | |
15049 | the current segment). */ | |
a7ebbfdf | 15050 | if (! fixP->fx_done) |
bb2d6cd7 | 15051 | break; |
252b5132 | 15052 | |
54f4ddb3 | 15053 | /* Update old instruction data. */ |
4d68580a | 15054 | insn = read_insn (buf); |
252b5132 | 15055 | |
a7ebbfdf TS |
15056 | if (*valP + 0x20000 <= 0x3ffff) |
15057 | { | |
15058 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15059 | write_insn (buf, insn); |
a7ebbfdf TS |
15060 | } |
15061 | else if (mips_pic == NO_PIC | |
15062 | && fixP->fx_done | |
15063 | && fixP->fx_frag->fr_address >= text_section->vma | |
15064 | && (fixP->fx_frag->fr_address | |
587aac4e | 15065 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15066 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15067 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15068 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15069 | { |
15070 | /* The branch offset is too large. If this is an | |
15071 | unconditional branch, and we are not generating PIC code, | |
15072 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15073 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15074 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15075 | else |
a7ebbfdf TS |
15076 | insn = 0x08000000; /* j */ |
15077 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15078 | fixP->fx_done = 0; | |
15079 | fixP->fx_addsy = section_symbol (text_section); | |
15080 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15081 | write_insn (buf, insn); |
a7ebbfdf TS |
15082 | } |
15083 | else | |
15084 | { | |
15085 | /* If we got here, we have branch-relaxation disabled, | |
15086 | and there's nothing we can do to fix this instruction | |
15087 | without turning it into a longer sequence. */ | |
15088 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15089 | _("branch out of range")); |
252b5132 | 15090 | } |
252b5132 RH |
15091 | break; |
15092 | ||
df58fc94 RS |
15093 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15094 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15095 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15096 | /* We adjust the offset back to even. */ | |
15097 | if ((*valP & 0x1) != 0) | |
15098 | --(*valP); | |
15099 | ||
15100 | if (! fixP->fx_done) | |
15101 | break; | |
15102 | ||
15103 | /* Should never visit here, because we keep the relocation. */ | |
15104 | abort (); | |
15105 | break; | |
15106 | ||
252b5132 RH |
15107 | case BFD_RELOC_VTABLE_INHERIT: |
15108 | fixP->fx_done = 0; | |
15109 | if (fixP->fx_addsy | |
15110 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15111 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15112 | S_SET_WEAK (fixP->fx_addsy); | |
15113 | break; | |
15114 | ||
2f0c68f2 | 15115 | case BFD_RELOC_NONE: |
252b5132 RH |
15116 | case BFD_RELOC_VTABLE_ENTRY: |
15117 | fixP->fx_done = 0; | |
15118 | break; | |
15119 | ||
15120 | default: | |
b37df7c4 | 15121 | abort (); |
252b5132 | 15122 | } |
a7ebbfdf TS |
15123 | |
15124 | /* Remember value for tc_gen_reloc. */ | |
15125 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15126 | } |
15127 | ||
252b5132 | 15128 | static symbolS * |
17a2f251 | 15129 | get_symbol (void) |
252b5132 RH |
15130 | { |
15131 | int c; | |
15132 | char *name; | |
15133 | symbolS *p; | |
15134 | ||
d02603dc | 15135 | c = get_symbol_name (&name); |
252b5132 | 15136 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15137 | (void) restore_line_pointer (c); |
252b5132 RH |
15138 | return p; |
15139 | } | |
15140 | ||
742a56fe RS |
15141 | /* Align the current frag to a given power of two. If a particular |
15142 | fill byte should be used, FILL points to an integer that contains | |
15143 | that byte, otherwise FILL is null. | |
15144 | ||
462427c4 RS |
15145 | This function used to have the comment: |
15146 | ||
15147 | The MIPS assembler also automatically adjusts any preceding label. | |
15148 | ||
15149 | The implementation therefore applied the adjustment to a maximum of | |
15150 | one label. However, other label adjustments are applied to batches | |
15151 | of labels, and adjusting just one caused problems when new labels | |
15152 | were added for the sake of debugging or unwind information. | |
15153 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15154 | |
15155 | static void | |
462427c4 | 15156 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15157 | { |
7d10b47d | 15158 | mips_emit_delays (); |
df58fc94 | 15159 | mips_record_compressed_mode (); |
742a56fe RS |
15160 | if (fill == NULL && subseg_text_p (now_seg)) |
15161 | frag_align_code (to, 0); | |
15162 | else | |
15163 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15164 | record_alignment (now_seg, to); |
462427c4 | 15165 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15166 | } |
15167 | ||
15168 | /* Align to a given power of two. .align 0 turns off the automatic | |
15169 | alignment used by the data creating pseudo-ops. */ | |
15170 | ||
15171 | static void | |
17a2f251 | 15172 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15173 | { |
742a56fe | 15174 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15175 | long max_alignment = 28; |
252b5132 | 15176 | |
54f4ddb3 | 15177 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15178 | to the aligned address. |
54f4ddb3 | 15179 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15180 | a .align pseudo instruction. |
54f4ddb3 | 15181 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15182 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15183 | We don't. */ |
252b5132 RH |
15184 | |
15185 | temp = get_absolute_expression (); | |
15186 | if (temp > max_alignment) | |
1661c76c | 15187 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15188 | else if (temp < 0) |
15189 | { | |
1661c76c | 15190 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15191 | temp = 0; |
15192 | } | |
15193 | if (*input_line_pointer == ',') | |
15194 | { | |
f9419b05 | 15195 | ++input_line_pointer; |
742a56fe RS |
15196 | fill_value = get_absolute_expression (); |
15197 | fill_ptr = &fill_value; | |
252b5132 RH |
15198 | } |
15199 | else | |
742a56fe | 15200 | fill_ptr = 0; |
252b5132 RH |
15201 | if (temp) |
15202 | { | |
a8dbcb85 TS |
15203 | segment_info_type *si = seg_info (now_seg); |
15204 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15205 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15206 | auto_align = 1; |
462427c4 | 15207 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15208 | } |
15209 | else | |
15210 | { | |
15211 | auto_align = 0; | |
15212 | } | |
15213 | ||
15214 | demand_empty_rest_of_line (); | |
15215 | } | |
15216 | ||
252b5132 | 15217 | static void |
17a2f251 | 15218 | s_change_sec (int sec) |
252b5132 RH |
15219 | { |
15220 | segT seg; | |
15221 | ||
252b5132 RH |
15222 | /* The ELF backend needs to know that we are changing sections, so |
15223 | that .previous works correctly. We could do something like check | |
b6ff326e | 15224 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15225 | as it would not be appropriate to use it in the section changing |
15226 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15227 | This should be cleaner, somehow. */ | |
f3ded42a | 15228 | obj_elf_section_change_hook (); |
252b5132 | 15229 | |
7d10b47d | 15230 | mips_emit_delays (); |
6a32d874 | 15231 | |
252b5132 RH |
15232 | switch (sec) |
15233 | { | |
15234 | case 't': | |
15235 | s_text (0); | |
15236 | break; | |
15237 | case 'd': | |
15238 | s_data (0); | |
15239 | break; | |
15240 | case 'b': | |
15241 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15242 | demand_empty_rest_of_line (); | |
15243 | break; | |
15244 | ||
15245 | case 'r': | |
4d0d148d TS |
15246 | seg = subseg_new (RDATA_SECTION_NAME, |
15247 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15248 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15249 | | SEC_READONLY | SEC_RELOC | |
15250 | | SEC_DATA)); | |
15251 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15252 | record_alignment (seg, 4); | |
4d0d148d | 15253 | demand_empty_rest_of_line (); |
252b5132 RH |
15254 | break; |
15255 | ||
15256 | case 's': | |
4d0d148d | 15257 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
15258 | bfd_set_section_flags (stdoutput, seg, |
15259 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
15260 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15261 | record_alignment (seg, 4); | |
4d0d148d TS |
15262 | demand_empty_rest_of_line (); |
15263 | break; | |
998b3c36 MR |
15264 | |
15265 | case 'B': | |
15266 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15267 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
15268 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15269 | record_alignment (seg, 4); | |
998b3c36 MR |
15270 | demand_empty_rest_of_line (); |
15271 | break; | |
252b5132 RH |
15272 | } |
15273 | ||
15274 | auto_align = 1; | |
15275 | } | |
b34976b6 | 15276 | |
cca86cc8 | 15277 | void |
17a2f251 | 15278 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15279 | { |
d02603dc | 15280 | char *saved_ilp; |
cca86cc8 | 15281 | char *section_name; |
d02603dc | 15282 | char c, endc; |
684022ea | 15283 | char next_c = 0; |
cca86cc8 SC |
15284 | int section_type; |
15285 | int section_flag; | |
15286 | int section_entry_size; | |
15287 | int section_alignment; | |
b34976b6 | 15288 | |
d02603dc NC |
15289 | saved_ilp = input_line_pointer; |
15290 | endc = get_symbol_name (§ion_name); | |
15291 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 15292 | if (c) |
d02603dc | 15293 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 15294 | |
4cf0dd0d TS |
15295 | /* Do we have .section Name<,"flags">? */ |
15296 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15297 | { |
d02603dc NC |
15298 | /* Just after name is now '\0'. */ |
15299 | (void) restore_line_pointer (endc); | |
15300 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
15301 | obj_elf_section (ignore); |
15302 | return; | |
15303 | } | |
d02603dc NC |
15304 | |
15305 | section_name = xstrdup (section_name); | |
15306 | c = restore_line_pointer (endc); | |
15307 | ||
cca86cc8 SC |
15308 | input_line_pointer++; |
15309 | ||
15310 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15311 | if (c == ',') | |
15312 | section_type = get_absolute_expression (); | |
15313 | else | |
15314 | section_type = 0; | |
d02603dc | 15315 | |
cca86cc8 SC |
15316 | if (*input_line_pointer++ == ',') |
15317 | section_flag = get_absolute_expression (); | |
15318 | else | |
15319 | section_flag = 0; | |
d02603dc | 15320 | |
cca86cc8 SC |
15321 | if (*input_line_pointer++ == ',') |
15322 | section_entry_size = get_absolute_expression (); | |
15323 | else | |
15324 | section_entry_size = 0; | |
d02603dc | 15325 | |
cca86cc8 SC |
15326 | if (*input_line_pointer++ == ',') |
15327 | section_alignment = get_absolute_expression (); | |
15328 | else | |
15329 | section_alignment = 0; | |
d02603dc | 15330 | |
87975d2a AM |
15331 | /* FIXME: really ignore? */ |
15332 | (void) section_alignment; | |
cca86cc8 | 15333 | |
8ab8a5c8 RS |
15334 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15335 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15336 | traditionally had to fall back on the more common @progbits instead. | |
15337 | ||
15338 | There's nothing really harmful in this, since bfd will correct | |
15339 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15340 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15341 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15342 | ||
15343 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15344 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15345 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15346 | generic type-checking code. */ | |
15347 | if (section_type == SHT_MIPS_DWARF) | |
15348 | section_type = SHT_PROGBITS; | |
15349 | ||
cca86cc8 SC |
15350 | obj_elf_change_section (section_name, section_type, section_flag, |
15351 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15352 | |
15353 | if (now_seg->name != section_name) | |
15354 | free (section_name); | |
cca86cc8 | 15355 | } |
252b5132 RH |
15356 | |
15357 | void | |
17a2f251 | 15358 | mips_enable_auto_align (void) |
252b5132 RH |
15359 | { |
15360 | auto_align = 1; | |
15361 | } | |
15362 | ||
15363 | static void | |
17a2f251 | 15364 | s_cons (int log_size) |
252b5132 | 15365 | { |
a8dbcb85 TS |
15366 | segment_info_type *si = seg_info (now_seg); |
15367 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15368 | |
7d10b47d | 15369 | mips_emit_delays (); |
252b5132 | 15370 | if (log_size > 0 && auto_align) |
462427c4 | 15371 | mips_align (log_size, 0, l); |
252b5132 | 15372 | cons (1 << log_size); |
a1facbec | 15373 | mips_clear_insn_labels (); |
252b5132 RH |
15374 | } |
15375 | ||
15376 | static void | |
17a2f251 | 15377 | s_float_cons (int type) |
252b5132 | 15378 | { |
a8dbcb85 TS |
15379 | segment_info_type *si = seg_info (now_seg); |
15380 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15381 | |
7d10b47d | 15382 | mips_emit_delays (); |
252b5132 RH |
15383 | |
15384 | if (auto_align) | |
49309057 ILT |
15385 | { |
15386 | if (type == 'd') | |
462427c4 | 15387 | mips_align (3, 0, l); |
49309057 | 15388 | else |
462427c4 | 15389 | mips_align (2, 0, l); |
49309057 | 15390 | } |
252b5132 | 15391 | |
252b5132 | 15392 | float_cons (type); |
a1facbec | 15393 | mips_clear_insn_labels (); |
252b5132 RH |
15394 | } |
15395 | ||
15396 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15397 | permitted to say | |
15398 | .globl foo .text | |
15399 | where foo is an undefined symbol, to mean that foo should be | |
15400 | considered to be the address of a function. */ | |
15401 | ||
15402 | static void | |
17a2f251 | 15403 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15404 | { |
15405 | char *name; | |
15406 | int c; | |
15407 | symbolS *symbolP; | |
15408 | flagword flag; | |
15409 | ||
8a06b769 | 15410 | do |
252b5132 | 15411 | { |
d02603dc | 15412 | c = get_symbol_name (&name); |
8a06b769 TS |
15413 | symbolP = symbol_find_or_make (name); |
15414 | S_SET_EXTERNAL (symbolP); | |
15415 | ||
252b5132 | 15416 | *input_line_pointer = c; |
d02603dc | 15417 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 15418 | |
8a06b769 TS |
15419 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15420 | being a function is apparently labelled as being an object. */ | |
15421 | flag = BSF_OBJECT; | |
252b5132 | 15422 | |
8a06b769 TS |
15423 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15424 | && (*input_line_pointer != ',')) | |
15425 | { | |
15426 | char *secname; | |
15427 | asection *sec; | |
15428 | ||
d02603dc | 15429 | c = get_symbol_name (&secname); |
8a06b769 TS |
15430 | sec = bfd_get_section_by_name (stdoutput, secname); |
15431 | if (sec == NULL) | |
15432 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 15433 | (void) restore_line_pointer (c); |
8a06b769 TS |
15434 | |
15435 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15436 | flag = BSF_FUNCTION; | |
15437 | } | |
15438 | ||
15439 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15440 | ||
15441 | c = *input_line_pointer; | |
15442 | if (c == ',') | |
15443 | { | |
15444 | input_line_pointer++; | |
15445 | SKIP_WHITESPACE (); | |
15446 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15447 | c = '\n'; | |
15448 | } | |
15449 | } | |
15450 | while (c == ','); | |
252b5132 | 15451 | |
252b5132 RH |
15452 | demand_empty_rest_of_line (); |
15453 | } | |
15454 | ||
15455 | static void | |
17a2f251 | 15456 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15457 | { |
15458 | char *opt; | |
15459 | char c; | |
15460 | ||
d02603dc | 15461 | c = get_symbol_name (&opt); |
252b5132 RH |
15462 | |
15463 | if (*opt == 'O') | |
15464 | { | |
15465 | /* FIXME: What does this mean? */ | |
15466 | } | |
15467 | else if (strncmp (opt, "pic", 3) == 0) | |
15468 | { | |
15469 | int i; | |
15470 | ||
15471 | i = atoi (opt + 3); | |
15472 | if (i == 0) | |
15473 | mips_pic = NO_PIC; | |
15474 | else if (i == 2) | |
143d77c5 | 15475 | { |
8b828383 | 15476 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15477 | mips_abicalls = TRUE; |
15478 | } | |
252b5132 RH |
15479 | else |
15480 | as_bad (_(".option pic%d not supported"), i); | |
15481 | ||
4d0d148d | 15482 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
15483 | { |
15484 | if (g_switch_seen && g_switch_value != 0) | |
15485 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15486 | g_switch_value = 0; | |
15487 | bfd_set_gp_size (stdoutput, 0); | |
15488 | } | |
15489 | } | |
15490 | else | |
1661c76c | 15491 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 15492 | |
d02603dc | 15493 | (void) restore_line_pointer (c); |
252b5132 RH |
15494 | demand_empty_rest_of_line (); |
15495 | } | |
15496 | ||
15497 | /* This structure is used to hold a stack of .set values. */ | |
15498 | ||
e972090a NC |
15499 | struct mips_option_stack |
15500 | { | |
252b5132 RH |
15501 | struct mips_option_stack *next; |
15502 | struct mips_set_options options; | |
15503 | }; | |
15504 | ||
15505 | static struct mips_option_stack *mips_opts_stack; | |
15506 | ||
919731af | 15507 | static bfd_boolean |
15508 | parse_code_option (char * name) | |
252b5132 | 15509 | { |
c6278170 | 15510 | const struct mips_ase *ase; |
919731af | 15511 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
15512 | { |
15513 | char *s = name + 3; | |
15514 | ||
15515 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 15516 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 15517 | } |
252b5132 | 15518 | else if (strcmp (name, "at") == 0) |
919731af | 15519 | mips_opts.at = ATREG; |
252b5132 | 15520 | else if (strcmp (name, "noat") == 0) |
919731af | 15521 | mips_opts.at = ZERO; |
252b5132 | 15522 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 15523 | mips_opts.nomove = 0; |
252b5132 | 15524 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 15525 | mips_opts.nomove = 1; |
252b5132 | 15526 | else if (strcmp (name, "bopt") == 0) |
919731af | 15527 | mips_opts.nobopt = 0; |
252b5132 | 15528 | else if (strcmp (name, "nobopt") == 0) |
919731af | 15529 | mips_opts.nobopt = 1; |
ad3fea08 | 15530 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 15531 | mips_opts.gp = 32; |
ad3fea08 | 15532 | else if (strcmp (name, "gp=64") == 0) |
919731af | 15533 | mips_opts.gp = 64; |
ad3fea08 | 15534 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 15535 | mips_opts.fp = 32; |
351cdf24 MF |
15536 | else if (strcmp (name, "fp=xx") == 0) |
15537 | mips_opts.fp = 0; | |
ad3fea08 | 15538 | else if (strcmp (name, "fp=64") == 0) |
919731af | 15539 | mips_opts.fp = 64; |
037b32b9 AN |
15540 | else if (strcmp (name, "softfloat") == 0) |
15541 | mips_opts.soft_float = 1; | |
15542 | else if (strcmp (name, "hardfloat") == 0) | |
15543 | mips_opts.soft_float = 0; | |
15544 | else if (strcmp (name, "singlefloat") == 0) | |
15545 | mips_opts.single_float = 1; | |
15546 | else if (strcmp (name, "doublefloat") == 0) | |
15547 | mips_opts.single_float = 0; | |
351cdf24 MF |
15548 | else if (strcmp (name, "nooddspreg") == 0) |
15549 | mips_opts.oddspreg = 0; | |
15550 | else if (strcmp (name, "oddspreg") == 0) | |
15551 | mips_opts.oddspreg = 1; | |
252b5132 RH |
15552 | else if (strcmp (name, "mips16") == 0 |
15553 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 15554 | mips_opts.mips16 = 1; |
252b5132 RH |
15555 | else if (strcmp (name, "nomips16") == 0 |
15556 | || strcmp (name, "noMIPS-16") == 0) | |
15557 | mips_opts.mips16 = 0; | |
df58fc94 | 15558 | else if (strcmp (name, "micromips") == 0) |
919731af | 15559 | mips_opts.micromips = 1; |
df58fc94 RS |
15560 | else if (strcmp (name, "nomicromips") == 0) |
15561 | mips_opts.micromips = 0; | |
c6278170 RS |
15562 | else if (name[0] == 'n' |
15563 | && name[1] == 'o' | |
15564 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 15565 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 15566 | else if ((ase = mips_lookup_ase (name))) |
919731af | 15567 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 15568 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 15569 | { |
1a2c1fad CD |
15570 | /* Permit the user to change the ISA and architecture on the fly. |
15571 | Needless to say, misuse can cause serious problems. */ | |
919731af | 15572 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
15573 | { |
15574 | const struct mips_cpu_info *p; | |
15575 | ||
919731af | 15576 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
15577 | if (!p) |
15578 | as_bad (_("unknown architecture %s"), name + 5); | |
15579 | else | |
15580 | { | |
15581 | mips_opts.arch = p->cpu; | |
15582 | mips_opts.isa = p->isa; | |
15583 | } | |
15584 | } | |
81a21e38 TS |
15585 | else if (strncmp (name, "mips", 4) == 0) |
15586 | { | |
15587 | const struct mips_cpu_info *p; | |
15588 | ||
919731af | 15589 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
15590 | if (!p) |
15591 | as_bad (_("unknown ISA level %s"), name + 4); | |
15592 | else | |
15593 | { | |
15594 | mips_opts.arch = p->cpu; | |
15595 | mips_opts.isa = p->isa; | |
15596 | } | |
15597 | } | |
af7ee8bf | 15598 | else |
81a21e38 | 15599 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
15600 | } |
15601 | else if (strcmp (name, "autoextend") == 0) | |
15602 | mips_opts.noautoextend = 0; | |
15603 | else if (strcmp (name, "noautoextend") == 0) | |
15604 | mips_opts.noautoextend = 1; | |
833794fc MR |
15605 | else if (strcmp (name, "insn32") == 0) |
15606 | mips_opts.insn32 = TRUE; | |
15607 | else if (strcmp (name, "noinsn32") == 0) | |
15608 | mips_opts.insn32 = FALSE; | |
919731af | 15609 | else if (strcmp (name, "sym32") == 0) |
15610 | mips_opts.sym32 = TRUE; | |
15611 | else if (strcmp (name, "nosym32") == 0) | |
15612 | mips_opts.sym32 = FALSE; | |
15613 | else | |
15614 | return FALSE; | |
15615 | return TRUE; | |
15616 | } | |
15617 | ||
15618 | /* Handle the .set pseudo-op. */ | |
15619 | ||
15620 | static void | |
15621 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
15622 | { | |
15623 | char *name = input_line_pointer, ch; | |
15624 | int prev_isa = mips_opts.isa; | |
15625 | ||
15626 | file_mips_check_options (); | |
15627 | ||
15628 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
15629 | ++input_line_pointer; | |
15630 | ch = *input_line_pointer; | |
15631 | *input_line_pointer = '\0'; | |
15632 | ||
15633 | if (strchr (name, ',')) | |
15634 | { | |
15635 | /* Generic ".set" directive; use the generic handler. */ | |
15636 | *input_line_pointer = ch; | |
15637 | input_line_pointer = name; | |
15638 | s_set (0); | |
15639 | return; | |
15640 | } | |
15641 | ||
15642 | if (strcmp (name, "reorder") == 0) | |
15643 | { | |
15644 | if (mips_opts.noreorder) | |
15645 | end_noreorder (); | |
15646 | } | |
15647 | else if (strcmp (name, "noreorder") == 0) | |
15648 | { | |
15649 | if (!mips_opts.noreorder) | |
15650 | start_noreorder (); | |
15651 | } | |
15652 | else if (strcmp (name, "macro") == 0) | |
15653 | mips_opts.warn_about_macros = 0; | |
15654 | else if (strcmp (name, "nomacro") == 0) | |
15655 | { | |
15656 | if (mips_opts.noreorder == 0) | |
15657 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
15658 | mips_opts.warn_about_macros = 1; | |
15659 | } | |
15660 | else if (strcmp (name, "gp=default") == 0) | |
15661 | mips_opts.gp = file_mips_opts.gp; | |
15662 | else if (strcmp (name, "fp=default") == 0) | |
15663 | mips_opts.fp = file_mips_opts.fp; | |
15664 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
15665 | { | |
15666 | mips_opts.isa = file_mips_opts.isa; | |
15667 | mips_opts.arch = file_mips_opts.arch; | |
15668 | mips_opts.gp = file_mips_opts.gp; | |
15669 | mips_opts.fp = file_mips_opts.fp; | |
15670 | } | |
252b5132 RH |
15671 | else if (strcmp (name, "push") == 0) |
15672 | { | |
15673 | struct mips_option_stack *s; | |
15674 | ||
15675 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
15676 | s->next = mips_opts_stack; | |
15677 | s->options = mips_opts; | |
15678 | mips_opts_stack = s; | |
15679 | } | |
15680 | else if (strcmp (name, "pop") == 0) | |
15681 | { | |
15682 | struct mips_option_stack *s; | |
15683 | ||
15684 | s = mips_opts_stack; | |
15685 | if (s == NULL) | |
15686 | as_bad (_(".set pop with no .set push")); | |
15687 | else | |
15688 | { | |
15689 | /* If we're changing the reorder mode we need to handle | |
15690 | delay slots correctly. */ | |
15691 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 15692 | start_noreorder (); |
252b5132 | 15693 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 15694 | end_noreorder (); |
252b5132 RH |
15695 | |
15696 | mips_opts = s->options; | |
15697 | mips_opts_stack = s->next; | |
15698 | free (s); | |
15699 | } | |
15700 | } | |
919731af | 15701 | else if (!parse_code_option (name)) |
15702 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
15703 | ||
15704 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
15705 | registers based on what is supported by the arch/cpu. */ | |
15706 | if (mips_opts.isa != prev_isa) | |
e6559e01 | 15707 | { |
919731af | 15708 | switch (mips_opts.isa) |
15709 | { | |
15710 | case 0: | |
15711 | break; | |
15712 | case ISA_MIPS1: | |
351cdf24 MF |
15713 | /* MIPS I cannot support FPXX. */ |
15714 | mips_opts.fp = 32; | |
15715 | /* fall-through. */ | |
919731af | 15716 | case ISA_MIPS2: |
15717 | case ISA_MIPS32: | |
15718 | case ISA_MIPS32R2: | |
15719 | case ISA_MIPS32R3: | |
15720 | case ISA_MIPS32R5: | |
15721 | mips_opts.gp = 32; | |
351cdf24 MF |
15722 | if (mips_opts.fp != 0) |
15723 | mips_opts.fp = 32; | |
919731af | 15724 | break; |
7361da2c AB |
15725 | case ISA_MIPS32R6: |
15726 | mips_opts.gp = 32; | |
15727 | mips_opts.fp = 64; | |
15728 | break; | |
919731af | 15729 | case ISA_MIPS3: |
15730 | case ISA_MIPS4: | |
15731 | case ISA_MIPS5: | |
15732 | case ISA_MIPS64: | |
15733 | case ISA_MIPS64R2: | |
15734 | case ISA_MIPS64R3: | |
15735 | case ISA_MIPS64R5: | |
7361da2c | 15736 | case ISA_MIPS64R6: |
919731af | 15737 | mips_opts.gp = 64; |
351cdf24 MF |
15738 | if (mips_opts.fp != 0) |
15739 | { | |
15740 | if (mips_opts.arch == CPU_R5900) | |
15741 | mips_opts.fp = 32; | |
15742 | else | |
15743 | mips_opts.fp = 64; | |
15744 | } | |
919731af | 15745 | break; |
15746 | default: | |
15747 | as_bad (_("unknown ISA level %s"), name + 4); | |
15748 | break; | |
15749 | } | |
e6559e01 | 15750 | } |
919731af | 15751 | |
15752 | mips_check_options (&mips_opts, FALSE); | |
15753 | ||
15754 | mips_check_isa_supports_ases (); | |
15755 | *input_line_pointer = ch; | |
15756 | demand_empty_rest_of_line (); | |
15757 | } | |
15758 | ||
15759 | /* Handle the .module pseudo-op. */ | |
15760 | ||
15761 | static void | |
15762 | s_module (int ignore ATTRIBUTE_UNUSED) | |
15763 | { | |
15764 | char *name = input_line_pointer, ch; | |
15765 | ||
15766 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
15767 | ++input_line_pointer; | |
15768 | ch = *input_line_pointer; | |
15769 | *input_line_pointer = '\0'; | |
15770 | ||
15771 | if (!file_mips_opts_checked) | |
252b5132 | 15772 | { |
919731af | 15773 | if (!parse_code_option (name)) |
15774 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); | |
15775 | ||
15776 | /* Update module level settings from mips_opts. */ | |
15777 | file_mips_opts = mips_opts; | |
252b5132 | 15778 | } |
919731af | 15779 | else |
15780 | as_bad (_(".module is not permitted after generating code")); | |
15781 | ||
252b5132 RH |
15782 | *input_line_pointer = ch; |
15783 | demand_empty_rest_of_line (); | |
15784 | } | |
15785 | ||
15786 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
15787 | .option pic2. It means to generate SVR4 PIC calls. */ | |
15788 | ||
15789 | static void | |
17a2f251 | 15790 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15791 | { |
15792 | mips_pic = SVR4_PIC; | |
143d77c5 | 15793 | mips_abicalls = TRUE; |
4d0d148d TS |
15794 | |
15795 | if (g_switch_seen && g_switch_value != 0) | |
15796 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15797 | g_switch_value = 0; | |
15798 | ||
252b5132 RH |
15799 | bfd_set_gp_size (stdoutput, 0); |
15800 | demand_empty_rest_of_line (); | |
15801 | } | |
15802 | ||
15803 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
15804 | PIC code. It sets the $gp register for the function based on the | |
15805 | function address, which is in the register named in the argument. | |
15806 | This uses a relocation against _gp_disp, which is handled specially | |
15807 | by the linker. The result is: | |
15808 | lui $gp,%hi(_gp_disp) | |
15809 | addiu $gp,$gp,%lo(_gp_disp) | |
15810 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
15811 | The .cpload argument is normally $25 == $t9. |
15812 | ||
15813 | The -mno-shared option changes this to: | |
bbe506e8 TS |
15814 | lui $gp,%hi(__gnu_local_gp) |
15815 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
15816 | and the argument is ignored. This saves an instruction, but the |
15817 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
15818 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
15819 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
15820 | |
15821 | static void | |
17a2f251 | 15822 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
15823 | { |
15824 | expressionS ex; | |
aa6975fb ILT |
15825 | int reg; |
15826 | int in_shared; | |
252b5132 | 15827 | |
919731af | 15828 | file_mips_check_options (); |
15829 | ||
6478892d TS |
15830 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
15831 | .cpload is ignored. */ | |
15832 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
15833 | { |
15834 | s_ignore (0); | |
15835 | return; | |
15836 | } | |
15837 | ||
a276b80c MR |
15838 | if (mips_opts.mips16) |
15839 | { | |
15840 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
15841 | ignore_rest_of_line (); | |
15842 | return; | |
15843 | } | |
15844 | ||
d3ecfc59 | 15845 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
15846 | if (mips_opts.noreorder == 0) |
15847 | as_warn (_(".cpload not in noreorder section")); | |
15848 | ||
aa6975fb ILT |
15849 | reg = tc_get_register (0); |
15850 | ||
15851 | /* If we need to produce a 64-bit address, we are better off using | |
15852 | the default instruction sequence. */ | |
aed1a261 | 15853 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 15854 | |
252b5132 | 15855 | ex.X_op = O_symbol; |
bbe506e8 TS |
15856 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
15857 | "__gnu_local_gp"); | |
252b5132 RH |
15858 | ex.X_op_symbol = NULL; |
15859 | ex.X_add_number = 0; | |
15860 | ||
15861 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 15862 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 15863 | |
8a75745d MR |
15864 | mips_mark_labels (); |
15865 | mips_assembling_insn = TRUE; | |
15866 | ||
584892a6 | 15867 | macro_start (); |
67c0d1eb RS |
15868 | macro_build_lui (&ex, mips_gp_register); |
15869 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 15870 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
15871 | if (in_shared) |
15872 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
15873 | mips_gp_register, reg); | |
584892a6 | 15874 | macro_end (); |
252b5132 | 15875 | |
8a75745d | 15876 | mips_assembling_insn = FALSE; |
252b5132 RH |
15877 | demand_empty_rest_of_line (); |
15878 | } | |
15879 | ||
6478892d TS |
15880 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
15881 | .cpsetup $reg1, offset|$reg2, label | |
15882 | ||
15883 | If offset is given, this results in: | |
15884 | sd $gp, offset($sp) | |
956cd1d6 | 15885 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
15886 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
15887 | daddu $gp, $gp, $reg1 | |
6478892d TS |
15888 | |
15889 | If $reg2 is given, this results in: | |
40fc1451 | 15890 | or $reg2, $gp, $0 |
956cd1d6 | 15891 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
15892 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
15893 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
15894 | $reg1 is normally $25 == $t9. |
15895 | ||
15896 | The -mno-shared option replaces the last three instructions with | |
15897 | lui $gp,%hi(_gp) | |
54f4ddb3 | 15898 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 15899 | |
6478892d | 15900 | static void |
17a2f251 | 15901 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
15902 | { |
15903 | expressionS ex_off; | |
15904 | expressionS ex_sym; | |
15905 | int reg1; | |
6478892d | 15906 | |
919731af | 15907 | file_mips_check_options (); |
15908 | ||
8586fc66 | 15909 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
15910 | We also need NewABI support. */ |
15911 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
15912 | { | |
15913 | s_ignore (0); | |
15914 | return; | |
15915 | } | |
15916 | ||
a276b80c MR |
15917 | if (mips_opts.mips16) |
15918 | { | |
15919 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
15920 | ignore_rest_of_line (); | |
15921 | return; | |
15922 | } | |
15923 | ||
6478892d TS |
15924 | reg1 = tc_get_register (0); |
15925 | SKIP_WHITESPACE (); | |
15926 | if (*input_line_pointer != ',') | |
15927 | { | |
15928 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
15929 | return; | |
15930 | } | |
15931 | else | |
80245285 | 15932 | ++input_line_pointer; |
6478892d TS |
15933 | SKIP_WHITESPACE (); |
15934 | if (*input_line_pointer == '$') | |
80245285 TS |
15935 | { |
15936 | mips_cpreturn_register = tc_get_register (0); | |
15937 | mips_cpreturn_offset = -1; | |
15938 | } | |
6478892d | 15939 | else |
80245285 TS |
15940 | { |
15941 | mips_cpreturn_offset = get_absolute_expression (); | |
15942 | mips_cpreturn_register = -1; | |
15943 | } | |
6478892d TS |
15944 | SKIP_WHITESPACE (); |
15945 | if (*input_line_pointer != ',') | |
15946 | { | |
15947 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
15948 | return; | |
15949 | } | |
15950 | else | |
f9419b05 | 15951 | ++input_line_pointer; |
6478892d | 15952 | SKIP_WHITESPACE (); |
f21f8242 | 15953 | expression (&ex_sym); |
6478892d | 15954 | |
8a75745d MR |
15955 | mips_mark_labels (); |
15956 | mips_assembling_insn = TRUE; | |
15957 | ||
584892a6 | 15958 | macro_start (); |
6478892d TS |
15959 | if (mips_cpreturn_register == -1) |
15960 | { | |
15961 | ex_off.X_op = O_constant; | |
15962 | ex_off.X_add_symbol = NULL; | |
15963 | ex_off.X_op_symbol = NULL; | |
15964 | ex_off.X_add_number = mips_cpreturn_offset; | |
15965 | ||
67c0d1eb | 15966 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 15967 | BFD_RELOC_LO16, SP); |
6478892d TS |
15968 | } |
15969 | else | |
40fc1451 | 15970 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 15971 | |
aed1a261 | 15972 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 15973 | { |
df58fc94 | 15974 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
15975 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
15976 | BFD_RELOC_HI16_S); | |
15977 | ||
15978 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
15979 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
15980 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
15981 | ||
15982 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
15983 | mips_gp_register, reg1); | |
15984 | } | |
15985 | else | |
15986 | { | |
15987 | expressionS ex; | |
15988 | ||
15989 | ex.X_op = O_symbol; | |
4184909a | 15990 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
15991 | ex.X_op_symbol = NULL; |
15992 | ex.X_add_number = 0; | |
6e1304d8 | 15993 | |
aa6975fb ILT |
15994 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
15995 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
15996 | ||
15997 | macro_build_lui (&ex, mips_gp_register); | |
15998 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
15999 | mips_gp_register, BFD_RELOC_LO16); | |
16000 | } | |
f21f8242 | 16001 | |
584892a6 | 16002 | macro_end (); |
6478892d | 16003 | |
8a75745d | 16004 | mips_assembling_insn = FALSE; |
6478892d TS |
16005 | demand_empty_rest_of_line (); |
16006 | } | |
16007 | ||
16008 | static void | |
17a2f251 | 16009 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16010 | { |
919731af | 16011 | file_mips_check_options (); |
16012 | ||
6478892d | 16013 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16014 | .cplocal is ignored. */ |
6478892d TS |
16015 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16016 | { | |
16017 | s_ignore (0); | |
16018 | return; | |
16019 | } | |
16020 | ||
a276b80c MR |
16021 | if (mips_opts.mips16) |
16022 | { | |
16023 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16024 | ignore_rest_of_line (); | |
16025 | return; | |
16026 | } | |
16027 | ||
6478892d | 16028 | mips_gp_register = tc_get_register (0); |
85b51719 | 16029 | demand_empty_rest_of_line (); |
6478892d TS |
16030 | } |
16031 | ||
252b5132 RH |
16032 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16033 | offset from $sp. The offset is remembered, and after making a PIC | |
16034 | call $gp is restored from that location. */ | |
16035 | ||
16036 | static void | |
17a2f251 | 16037 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16038 | { |
16039 | expressionS ex; | |
252b5132 | 16040 | |
919731af | 16041 | file_mips_check_options (); |
16042 | ||
6478892d | 16043 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16044 | .cprestore is ignored. */ |
6478892d | 16045 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16046 | { |
16047 | s_ignore (0); | |
16048 | return; | |
16049 | } | |
16050 | ||
a276b80c MR |
16051 | if (mips_opts.mips16) |
16052 | { | |
16053 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16054 | ignore_rest_of_line (); | |
16055 | return; | |
16056 | } | |
16057 | ||
252b5132 | 16058 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16059 | mips_cprestore_valid = 1; |
252b5132 RH |
16060 | |
16061 | ex.X_op = O_constant; | |
16062 | ex.X_add_symbol = NULL; | |
16063 | ex.X_op_symbol = NULL; | |
16064 | ex.X_add_number = mips_cprestore_offset; | |
16065 | ||
8a75745d MR |
16066 | mips_mark_labels (); |
16067 | mips_assembling_insn = TRUE; | |
16068 | ||
584892a6 | 16069 | macro_start (); |
67c0d1eb RS |
16070 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16071 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16072 | macro_end (); |
252b5132 | 16073 | |
8a75745d | 16074 | mips_assembling_insn = FALSE; |
252b5132 RH |
16075 | demand_empty_rest_of_line (); |
16076 | } | |
16077 | ||
6478892d | 16078 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16079 | was given in the preceding .cpsetup, it results in: |
6478892d | 16080 | ld $gp, offset($sp) |
76b3015f | 16081 | |
6478892d | 16082 | If a register $reg2 was given there, it results in: |
40fc1451 | 16083 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16084 | |
6478892d | 16085 | static void |
17a2f251 | 16086 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16087 | { |
16088 | expressionS ex; | |
6478892d | 16089 | |
919731af | 16090 | file_mips_check_options (); |
16091 | ||
6478892d TS |
16092 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16093 | We also need NewABI support. */ | |
16094 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16095 | { | |
16096 | s_ignore (0); | |
16097 | return; | |
16098 | } | |
16099 | ||
a276b80c MR |
16100 | if (mips_opts.mips16) |
16101 | { | |
16102 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16103 | ignore_rest_of_line (); | |
16104 | return; | |
16105 | } | |
16106 | ||
8a75745d MR |
16107 | mips_mark_labels (); |
16108 | mips_assembling_insn = TRUE; | |
16109 | ||
584892a6 | 16110 | macro_start (); |
6478892d TS |
16111 | if (mips_cpreturn_register == -1) |
16112 | { | |
16113 | ex.X_op = O_constant; | |
16114 | ex.X_add_symbol = NULL; | |
16115 | ex.X_op_symbol = NULL; | |
16116 | ex.X_add_number = mips_cpreturn_offset; | |
16117 | ||
67c0d1eb | 16118 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16119 | } |
16120 | else | |
40fc1451 SD |
16121 | move_register (mips_gp_register, mips_cpreturn_register); |
16122 | ||
584892a6 | 16123 | macro_end (); |
6478892d | 16124 | |
8a75745d | 16125 | mips_assembling_insn = FALSE; |
6478892d TS |
16126 | demand_empty_rest_of_line (); |
16127 | } | |
16128 | ||
d0f13682 CLT |
16129 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16130 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16131 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16132 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16133 | |
16134 | static void | |
d0f13682 CLT |
16135 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16136 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16137 | { |
16138 | expressionS ex; | |
16139 | char *p; | |
16140 | ||
16141 | expression (&ex); | |
16142 | ||
16143 | if (ex.X_op != O_symbol) | |
16144 | { | |
1661c76c | 16145 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16146 | ignore_rest_of_line (); |
16147 | } | |
16148 | ||
16149 | p = frag_more (bytes); | |
16150 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16151 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16152 | demand_empty_rest_of_line (); |
de64cffd | 16153 | mips_clear_insn_labels (); |
741d6ea8 JM |
16154 | } |
16155 | ||
16156 | /* Handle .dtprelword. */ | |
16157 | ||
16158 | static void | |
16159 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16160 | { | |
d0f13682 | 16161 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16162 | } |
16163 | ||
16164 | /* Handle .dtpreldword. */ | |
16165 | ||
16166 | static void | |
16167 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16168 | { | |
d0f13682 CLT |
16169 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16170 | } | |
16171 | ||
16172 | /* Handle .tprelword. */ | |
16173 | ||
16174 | static void | |
16175 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16176 | { | |
16177 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16178 | } | |
16179 | ||
16180 | /* Handle .tpreldword. */ | |
16181 | ||
16182 | static void | |
16183 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16184 | { | |
16185 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16186 | } |
16187 | ||
6478892d TS |
16188 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16189 | code. It sets the offset to use in gp_rel relocations. */ | |
16190 | ||
16191 | static void | |
17a2f251 | 16192 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16193 | { |
16194 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16195 | We also need NewABI support. */ | |
16196 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16197 | { | |
16198 | s_ignore (0); | |
16199 | return; | |
16200 | } | |
16201 | ||
def2e0dd | 16202 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16203 | |
16204 | demand_empty_rest_of_line (); | |
16205 | } | |
16206 | ||
252b5132 RH |
16207 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16208 | code. It generates a 32 bit GP relative reloc. */ | |
16209 | ||
16210 | static void | |
17a2f251 | 16211 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16212 | { |
a8dbcb85 TS |
16213 | segment_info_type *si; |
16214 | struct insn_label_list *l; | |
252b5132 RH |
16215 | expressionS ex; |
16216 | char *p; | |
16217 | ||
16218 | /* When not generating PIC code, this is treated as .word. */ | |
16219 | if (mips_pic != SVR4_PIC) | |
16220 | { | |
16221 | s_cons (2); | |
16222 | return; | |
16223 | } | |
16224 | ||
a8dbcb85 TS |
16225 | si = seg_info (now_seg); |
16226 | l = si->label_list; | |
7d10b47d | 16227 | mips_emit_delays (); |
252b5132 | 16228 | if (auto_align) |
462427c4 | 16229 | mips_align (2, 0, l); |
252b5132 RH |
16230 | |
16231 | expression (&ex); | |
a1facbec | 16232 | mips_clear_insn_labels (); |
252b5132 RH |
16233 | |
16234 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16235 | { | |
1661c76c | 16236 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
16237 | ignore_rest_of_line (); |
16238 | } | |
16239 | ||
16240 | p = frag_more (4); | |
17a2f251 | 16241 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16242 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16243 | BFD_RELOC_GPREL32); |
252b5132 RH |
16244 | |
16245 | demand_empty_rest_of_line (); | |
16246 | } | |
16247 | ||
10181a0d | 16248 | static void |
17a2f251 | 16249 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16250 | { |
a8dbcb85 TS |
16251 | segment_info_type *si; |
16252 | struct insn_label_list *l; | |
10181a0d AO |
16253 | expressionS ex; |
16254 | char *p; | |
16255 | ||
16256 | /* When not generating PIC code, this is treated as .dword. */ | |
16257 | if (mips_pic != SVR4_PIC) | |
16258 | { | |
16259 | s_cons (3); | |
16260 | return; | |
16261 | } | |
16262 | ||
a8dbcb85 TS |
16263 | si = seg_info (now_seg); |
16264 | l = si->label_list; | |
7d10b47d | 16265 | mips_emit_delays (); |
10181a0d | 16266 | if (auto_align) |
462427c4 | 16267 | mips_align (3, 0, l); |
10181a0d AO |
16268 | |
16269 | expression (&ex); | |
a1facbec | 16270 | mips_clear_insn_labels (); |
10181a0d AO |
16271 | |
16272 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16273 | { | |
1661c76c | 16274 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
16275 | ignore_rest_of_line (); |
16276 | } | |
16277 | ||
16278 | p = frag_more (8); | |
17a2f251 | 16279 | md_number_to_chars (p, 0, 8); |
a105a300 | 16280 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16281 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16282 | |
16283 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16284 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16285 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16286 | |
16287 | demand_empty_rest_of_line (); | |
16288 | } | |
16289 | ||
a3f278e2 CM |
16290 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
16291 | tables. It generates a R_MIPS_EH reloc. */ | |
16292 | ||
16293 | static void | |
16294 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
16295 | { | |
16296 | expressionS ex; | |
16297 | char *p; | |
16298 | ||
16299 | mips_emit_delays (); | |
16300 | ||
16301 | expression (&ex); | |
16302 | mips_clear_insn_labels (); | |
16303 | ||
16304 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16305 | { | |
1661c76c | 16306 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
16307 | ignore_rest_of_line (); |
16308 | } | |
16309 | ||
16310 | p = frag_more (4); | |
16311 | md_number_to_chars (p, 0, 4); | |
16312 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 16313 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
16314 | |
16315 | demand_empty_rest_of_line (); | |
16316 | } | |
16317 | ||
252b5132 RH |
16318 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16319 | tables in SVR4 PIC code. */ | |
16320 | ||
16321 | static void | |
17a2f251 | 16322 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16323 | { |
252b5132 RH |
16324 | int reg; |
16325 | ||
919731af | 16326 | file_mips_check_options (); |
16327 | ||
10181a0d AO |
16328 | /* This is ignored when not generating SVR4 PIC code. */ |
16329 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16330 | { |
16331 | s_ignore (0); | |
16332 | return; | |
16333 | } | |
16334 | ||
8a75745d MR |
16335 | mips_mark_labels (); |
16336 | mips_assembling_insn = TRUE; | |
16337 | ||
252b5132 | 16338 | /* Add $gp to the register named as an argument. */ |
584892a6 | 16339 | macro_start (); |
252b5132 | 16340 | reg = tc_get_register (0); |
67c0d1eb | 16341 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16342 | macro_end (); |
252b5132 | 16343 | |
8a75745d | 16344 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 16345 | demand_empty_rest_of_line (); |
252b5132 RH |
16346 | } |
16347 | ||
16348 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16349 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16350 | such as generating jalx instructions when needed. We also make |
16351 | them odd for the duration of the assembly, in order to generate the | |
16352 | right sort of code. We will make them even in the adjust_symtab | |
16353 | routine, while leaving them marked. This is convenient for the | |
16354 | debugger and the disassembler. The linker knows to make them odd | |
16355 | again. */ | |
16356 | ||
16357 | static void | |
17a2f251 | 16358 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16359 | { |
7bb01e2d MR |
16360 | file_mips_check_options (); |
16361 | file_ase_mips16 |= mips_opts.mips16; | |
16362 | file_ase_micromips |= mips_opts.micromips; | |
16363 | ||
df58fc94 | 16364 | mips_mark_labels (); |
252b5132 RH |
16365 | |
16366 | demand_empty_rest_of_line (); | |
16367 | } | |
16368 | ||
ba92f887 MR |
16369 | /* Handle the .nan pseudo-op. */ |
16370 | ||
16371 | static void | |
16372 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
16373 | { | |
16374 | static const char str_legacy[] = "legacy"; | |
16375 | static const char str_2008[] = "2008"; | |
16376 | size_t i; | |
16377 | ||
16378 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
16379 | ||
16380 | if (i == sizeof (str_2008) - 1 | |
16381 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 16382 | mips_nan2008 = 1; |
ba92f887 MR |
16383 | else if (i == sizeof (str_legacy) - 1 |
16384 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
16385 | { |
16386 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
16387 | mips_nan2008 = 0; | |
16388 | else | |
16389 | as_bad (_("`%s' does not support legacy NaN"), | |
16390 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
16391 | } | |
ba92f887 | 16392 | else |
1661c76c | 16393 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
16394 | |
16395 | input_line_pointer += i; | |
16396 | demand_empty_rest_of_line (); | |
16397 | } | |
16398 | ||
754e2bb9 RS |
16399 | /* Handle a .stab[snd] directive. Ideally these directives would be |
16400 | implemented in a transparent way, so that removing them would not | |
16401 | have any effect on the generated instructions. However, s_stab | |
16402 | internally changes the section, so in practice we need to decide | |
16403 | now whether the preceding label marks compressed code. We do not | |
16404 | support changing the compression mode of a label after a .stab* | |
16405 | directive, such as in: | |
16406 | ||
16407 | foo: | |
16408 | .stabs ... | |
16409 | .set mips16 | |
16410 | ||
16411 | so the current mode wins. */ | |
252b5132 RH |
16412 | |
16413 | static void | |
17a2f251 | 16414 | s_mips_stab (int type) |
252b5132 | 16415 | { |
754e2bb9 | 16416 | mips_mark_labels (); |
252b5132 RH |
16417 | s_stab (type); |
16418 | } | |
16419 | ||
54f4ddb3 | 16420 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16421 | |
16422 | static void | |
17a2f251 | 16423 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16424 | { |
16425 | char *name; | |
16426 | int c; | |
16427 | symbolS *symbolP; | |
16428 | expressionS exp; | |
16429 | ||
d02603dc | 16430 | c = get_symbol_name (&name); |
252b5132 RH |
16431 | symbolP = symbol_find_or_make (name); |
16432 | S_SET_WEAK (symbolP); | |
16433 | *input_line_pointer = c; | |
16434 | ||
d02603dc | 16435 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
16436 | |
16437 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16438 | { | |
16439 | if (S_IS_DEFINED (symbolP)) | |
16440 | { | |
20203fb9 | 16441 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16442 | S_GET_NAME (symbolP)); |
16443 | ignore_rest_of_line (); | |
16444 | return; | |
16445 | } | |
bdaaa2e1 | 16446 | |
252b5132 RH |
16447 | if (*input_line_pointer == ',') |
16448 | { | |
16449 | ++input_line_pointer; | |
16450 | SKIP_WHITESPACE (); | |
16451 | } | |
bdaaa2e1 | 16452 | |
252b5132 RH |
16453 | expression (&exp); |
16454 | if (exp.X_op != O_symbol) | |
16455 | { | |
20203fb9 | 16456 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16457 | ignore_rest_of_line (); |
252b5132 RH |
16458 | return; |
16459 | } | |
49309057 | 16460 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16461 | } |
16462 | ||
16463 | demand_empty_rest_of_line (); | |
16464 | } | |
16465 | ||
16466 | /* Parse a register string into a number. Called from the ECOFF code | |
16467 | to parse .frame. The argument is non-zero if this is the frame | |
16468 | register, so that we can record it in mips_frame_reg. */ | |
16469 | ||
16470 | int | |
17a2f251 | 16471 | tc_get_register (int frame) |
252b5132 | 16472 | { |
707bfff6 | 16473 | unsigned int reg; |
252b5132 RH |
16474 | |
16475 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16476 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16477 | reg = 0; | |
252b5132 | 16478 | if (frame) |
7a621144 DJ |
16479 | { |
16480 | mips_frame_reg = reg != 0 ? reg : SP; | |
16481 | mips_frame_reg_valid = 1; | |
16482 | mips_cprestore_valid = 0; | |
16483 | } | |
252b5132 RH |
16484 | return reg; |
16485 | } | |
16486 | ||
16487 | valueT | |
17a2f251 | 16488 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16489 | { |
16490 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16491 | ||
f3ded42a RS |
16492 | /* We don't need to align ELF sections to the full alignment. |
16493 | However, Irix 5 may prefer that we align them at least to a 16 | |
16494 | byte boundary. We don't bother to align the sections if we | |
16495 | are targeted for an embedded system. */ | |
16496 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
16497 | return addr; | |
16498 | if (align > 4) | |
16499 | align = 4; | |
252b5132 | 16500 | |
8d3842cd | 16501 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
16502 | } |
16503 | ||
16504 | /* Utility routine, called from above as well. If called while the | |
16505 | input file is still being read, it's only an approximation. (For | |
16506 | example, a symbol may later become defined which appeared to be | |
16507 | undefined earlier.) */ | |
16508 | ||
16509 | static int | |
17a2f251 | 16510 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16511 | { |
16512 | if (sym == 0) | |
16513 | return 0; | |
16514 | ||
4d0d148d | 16515 | if (g_switch_value > 0) |
252b5132 RH |
16516 | { |
16517 | const char *symname; | |
16518 | int change; | |
16519 | ||
c9914766 | 16520 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16521 | register. It can be if it is smaller than the -G size or if |
16522 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16523 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16524 | they can. */ |
16525 | symname = S_GET_NAME (sym); | |
16526 | if (symname != (const char *) NULL | |
16527 | && (strcmp (symname, "eprol") == 0 | |
16528 | || strcmp (symname, "etext") == 0 | |
16529 | || strcmp (symname, "_gp") == 0 | |
16530 | || strcmp (symname, "edata") == 0 | |
16531 | || strcmp (symname, "_fbss") == 0 | |
16532 | || strcmp (symname, "_fdata") == 0 | |
16533 | || strcmp (symname, "_ftext") == 0 | |
16534 | || strcmp (symname, "end") == 0 | |
16535 | || strcmp (symname, "_gp_disp") == 0)) | |
16536 | change = 1; | |
16537 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16538 | && (0 | |
16539 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16540 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16541 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16542 | <= g_switch_value)) | |
252b5132 RH |
16543 | #endif |
16544 | /* We must defer this decision until after the whole | |
16545 | file has been read, since there might be a .extern | |
16546 | after the first use of this symbol. */ | |
16547 | || (before_relaxing | |
16548 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16549 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16550 | #endif |
16551 | && S_GET_VALUE (sym) == 0) | |
16552 | || (S_GET_VALUE (sym) != 0 | |
16553 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16554 | change = 0; | |
16555 | else | |
16556 | { | |
16557 | const char *segname; | |
16558 | ||
16559 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16560 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16561 | && strcmp (segname, ".lit4") != 0); |
16562 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16563 | && strcmp (segname, ".sbss") != 0 |
16564 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16565 | && strncmp (segname, ".sbss.", 6) != 0 |
16566 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16567 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16568 | } |
16569 | return change; | |
16570 | } | |
16571 | else | |
c9914766 | 16572 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16573 | return 1; |
16574 | } | |
16575 | ||
5919d012 RS |
16576 | |
16577 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16578 | ||
16579 | static bfd_boolean | |
17a2f251 | 16580 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16581 | { |
16582 | asection *symsec; | |
5919d012 RS |
16583 | |
16584 | /* Handle the case of a symbol equated to another symbol. */ | |
16585 | while (symbol_equated_reloc_p (sym)) | |
16586 | { | |
16587 | symbolS *n; | |
16588 | ||
5f0fe04b | 16589 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16590 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16591 | if (n == sym) | |
16592 | break; | |
16593 | sym = n; | |
16594 | } | |
16595 | ||
df1f3cda DD |
16596 | if (symbol_section_p (sym)) |
16597 | return TRUE; | |
16598 | ||
5919d012 RS |
16599 | symsec = S_GET_SEGMENT (sym); |
16600 | ||
5919d012 | 16601 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
16602 | return (!bfd_is_und_section (symsec) |
16603 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
16604 | && !bfd_is_com_section (symsec) |
16605 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 16606 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 16607 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
16608 | } |
16609 | ||
16610 | ||
252b5132 RH |
16611 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16612 | extended opcode. SEC is the section the frag is in. */ | |
16613 | ||
16614 | static int | |
17a2f251 | 16615 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16616 | { |
16617 | int type; | |
3ccad066 | 16618 | const struct mips_int_operand *operand; |
252b5132 | 16619 | offsetT val; |
252b5132 | 16620 | segT symsec; |
98aa84af | 16621 | fragS *sym_frag; |
252b5132 RH |
16622 | |
16623 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16624 | return 0; | |
16625 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16626 | return 1; | |
16627 | ||
16628 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 16629 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 16630 | |
98aa84af | 16631 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 16632 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 16633 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 16634 | |
3ccad066 | 16635 | if (operand->root.type == OP_PCREL) |
252b5132 | 16636 | { |
3ccad066 | 16637 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 16638 | addressT addr; |
3ccad066 | 16639 | offsetT maxtiny; |
252b5132 RH |
16640 | |
16641 | /* We won't have the section when we are called from | |
16642 | mips_relax_frag. However, we will always have been called | |
16643 | from md_estimate_size_before_relax first. If this is a | |
16644 | branch to a different section, we mark it as such. If SEC is | |
16645 | NULL, and the frag is not marked, then it must be a branch to | |
16646 | the same section. */ | |
3ccad066 | 16647 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 RH |
16648 | if (sec == NULL) |
16649 | { | |
16650 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
16651 | return 1; | |
16652 | } | |
16653 | else | |
16654 | { | |
98aa84af | 16655 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
16656 | if (symsec != sec) |
16657 | { | |
16658 | fragp->fr_subtype = | |
16659 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16660 | ||
16661 | /* FIXME: We should support this, and let the linker | |
16662 | catch branches and loads that are out of range. */ | |
16663 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
16664 | _("unsupported PC relative reference to different section")); | |
16665 | ||
16666 | return 1; | |
16667 | } | |
98aa84af AM |
16668 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
16669 | /* Assume non-extended on the first relaxation pass. | |
16670 | The address we have calculated will be bogus if this is | |
16671 | a forward branch to another frag, as the forward frag | |
16672 | will have fr_address == 0. */ | |
16673 | return 0; | |
252b5132 RH |
16674 | } |
16675 | ||
16676 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
16677 | the same section. If the relax_marker of the symbol fragment |
16678 | differs from the relax_marker of this fragment, we have not | |
16679 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
16680 | in STRETCH in order to get a better estimate of the address. |
16681 | This particularly matters because of the shift bits. */ | |
16682 | if (stretch != 0 | |
98aa84af | 16683 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
16684 | { |
16685 | fragS *f; | |
16686 | ||
16687 | /* Adjust stretch for any alignment frag. Note that if have | |
16688 | been expanding the earlier code, the symbol may be | |
16689 | defined in what appears to be an earlier frag. FIXME: | |
16690 | This doesn't handle the fr_subtype field, which specifies | |
16691 | a maximum number of bytes to skip when doing an | |
16692 | alignment. */ | |
98aa84af | 16693 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
16694 | { |
16695 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
16696 | { | |
16697 | if (stretch < 0) | |
16698 | stretch = - ((- stretch) | |
16699 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
16700 | else | |
16701 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
16702 | if (stretch == 0) | |
16703 | break; | |
16704 | } | |
16705 | } | |
16706 | if (f != NULL) | |
16707 | val += stretch; | |
16708 | } | |
16709 | ||
16710 | addr = fragp->fr_address + fragp->fr_fix; | |
16711 | ||
16712 | /* The base address rules are complicated. The base address of | |
16713 | a branch is the following instruction. The base address of a | |
16714 | PC relative load or add is the instruction itself, but if it | |
16715 | is in a delay slot (in which case it can not be extended) use | |
16716 | the address of the instruction whose delay slot it is in. */ | |
3ccad066 | 16717 | if (pcrel_op->include_isa_bit) |
252b5132 RH |
16718 | { |
16719 | addr += 2; | |
16720 | ||
16721 | /* If we are currently assuming that this frag should be | |
16722 | extended, then, the current address is two bytes | |
bdaaa2e1 | 16723 | higher. */ |
252b5132 RH |
16724 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
16725 | addr += 2; | |
16726 | ||
16727 | /* Ignore the low bit in the target, since it will be set | |
16728 | for a text label. */ | |
3ccad066 | 16729 | val &= -2; |
252b5132 RH |
16730 | } |
16731 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
16732 | addr -= 4; | |
16733 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
16734 | addr -= 2; | |
16735 | ||
3ccad066 | 16736 | val -= addr & -(1 << pcrel_op->align_log2); |
252b5132 RH |
16737 | |
16738 | /* If any of the shifted bits are set, we must use an extended | |
16739 | opcode. If the address depends on the size of this | |
16740 | instruction, this can lead to a loop, so we arrange to always | |
16741 | use an extended opcode. We only check this when we are in | |
16742 | the main relaxation loop, when SEC is NULL. */ | |
3ccad066 | 16743 | if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL) |
252b5132 RH |
16744 | { |
16745 | fragp->fr_subtype = | |
16746 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16747 | return 1; | |
16748 | } | |
16749 | ||
16750 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
16751 | is precisely the next value above maxtiny, then there is a |
16752 | chance of an infinite loop as in the following code: | |
252b5132 RH |
16753 | la $4,foo |
16754 | .skip 1020 | |
16755 | .align 2 | |
16756 | foo: | |
16757 | In this case when the la is extended, foo is 0x3fc bytes | |
16758 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
16759 | the la must be extended. To avoid this loop, we mark the | |
16760 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
16761 | extended with the next value above maxtiny. */ |
16762 | maxtiny = mips_int_operand_max (operand); | |
16763 | if (val == maxtiny + (1 << operand->shift) | |
252b5132 RH |
16764 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) |
16765 | && sec == NULL) | |
16766 | { | |
16767 | fragp->fr_subtype = | |
16768 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16769 | return 1; | |
16770 | } | |
16771 | } | |
16772 | else if (symsec != absolute_section && sec != NULL) | |
16773 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
16774 | ||
3ccad066 | 16775 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
16776 | } |
16777 | ||
4a6a3df4 AO |
16778 | /* Compute the length of a branch sequence, and adjust the |
16779 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
16780 | worst-case length is computed, with UPDATE being used to indicate | |
16781 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
16782 | branch is to be computed. */ | |
16783 | static int | |
17a2f251 | 16784 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 16785 | { |
b34976b6 | 16786 | bfd_boolean toofar; |
4a6a3df4 AO |
16787 | int length; |
16788 | ||
16789 | if (fragp | |
16790 | && S_IS_DEFINED (fragp->fr_symbol) | |
16791 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16792 | { | |
16793 | addressT addr; | |
16794 | offsetT val; | |
16795 | ||
16796 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16797 | ||
16798 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
16799 | ||
16800 | val -= addr; | |
16801 | ||
16802 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
16803 | } | |
16804 | else if (fragp) | |
16805 | /* If the symbol is not defined or it's in a different segment, | |
16806 | assume the user knows what's going on and emit a short | |
16807 | branch. */ | |
b34976b6 | 16808 | toofar = FALSE; |
4a6a3df4 | 16809 | else |
b34976b6 | 16810 | toofar = TRUE; |
4a6a3df4 AO |
16811 | |
16812 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
16813 | fragp->fr_subtype | |
66b3e8da MR |
16814 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
16815 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
16816 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
16817 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
16818 | toofar); | |
16819 | ||
16820 | length = 4; | |
16821 | if (toofar) | |
16822 | { | |
16823 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
16824 | length += 8; | |
16825 | ||
16826 | if (mips_pic != NO_PIC) | |
16827 | { | |
16828 | /* Additional space for PIC loading of target address. */ | |
16829 | length += 8; | |
16830 | if (mips_opts.isa == ISA_MIPS1) | |
16831 | /* Additional space for $at-stabilizing nop. */ | |
16832 | length += 4; | |
16833 | } | |
16834 | ||
16835 | /* If branch is conditional. */ | |
16836 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
16837 | length += 8; | |
16838 | } | |
b34976b6 | 16839 | |
4a6a3df4 AO |
16840 | return length; |
16841 | } | |
16842 | ||
df58fc94 RS |
16843 | /* Compute the length of a branch sequence, and adjust the |
16844 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
16845 | worst-case length is computed, with UPDATE being used to indicate | |
16846 | whether an unconditional (-1), or regular (0) branch is to be | |
16847 | computed. */ | |
16848 | ||
16849 | static int | |
16850 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
16851 | { | |
16852 | bfd_boolean toofar; | |
16853 | int length; | |
16854 | ||
16855 | if (fragp | |
16856 | && S_IS_DEFINED (fragp->fr_symbol) | |
16857 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16858 | { | |
16859 | addressT addr; | |
16860 | offsetT val; | |
16861 | ||
16862 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16863 | /* Ignore the low bit in the target, since it will be set | |
16864 | for a text label. */ | |
16865 | if ((val & 1) != 0) | |
16866 | --val; | |
16867 | ||
16868 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
16869 | ||
16870 | val -= addr; | |
16871 | ||
16872 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
16873 | } | |
16874 | else if (fragp) | |
16875 | /* If the symbol is not defined or it's in a different segment, | |
16876 | assume the user knows what's going on and emit a short | |
16877 | branch. */ | |
16878 | toofar = FALSE; | |
16879 | else | |
16880 | toofar = TRUE; | |
16881 | ||
16882 | if (fragp && update | |
16883 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
16884 | fragp->fr_subtype = (toofar | |
16885 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
16886 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
16887 | ||
16888 | length = 4; | |
16889 | if (toofar) | |
16890 | { | |
16891 | bfd_boolean compact_known = fragp != NULL; | |
16892 | bfd_boolean compact = FALSE; | |
16893 | bfd_boolean uncond; | |
16894 | ||
16895 | if (compact_known) | |
16896 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
16897 | if (fragp) | |
16898 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
16899 | else | |
16900 | uncond = update < 0; | |
16901 | ||
16902 | /* If label is out of range, we turn branch <br>: | |
16903 | ||
16904 | <br> label # 4 bytes | |
16905 | 0: | |
16906 | ||
16907 | into: | |
16908 | ||
16909 | j label # 4 bytes | |
16910 | nop # 2 bytes if compact && !PIC | |
16911 | 0: | |
16912 | */ | |
16913 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
16914 | length += 2; | |
16915 | ||
16916 | /* If assembling PIC code, we further turn: | |
16917 | ||
16918 | j label # 4 bytes | |
16919 | ||
16920 | into: | |
16921 | ||
16922 | lw/ld at, %got(label)(gp) # 4 bytes | |
16923 | d/addiu at, %lo(label) # 4 bytes | |
16924 | jr/c at # 2 bytes | |
16925 | */ | |
16926 | if (mips_pic != NO_PIC) | |
16927 | length += 6; | |
16928 | ||
16929 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
16930 | ||
16931 | <brneg> 0f # 4 bytes | |
16932 | nop # 2 bytes if !compact | |
16933 | */ | |
16934 | if (!uncond) | |
16935 | length += (compact_known && compact) ? 4 : 6; | |
16936 | } | |
16937 | ||
16938 | return length; | |
16939 | } | |
16940 | ||
16941 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
16942 | bit accordingly. */ | |
16943 | ||
16944 | static int | |
16945 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
16946 | { | |
16947 | bfd_boolean toofar; | |
16948 | ||
df58fc94 RS |
16949 | if (fragp |
16950 | && S_IS_DEFINED (fragp->fr_symbol) | |
16951 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
16952 | { | |
16953 | addressT addr; | |
16954 | offsetT val; | |
16955 | int type; | |
16956 | ||
16957 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
16958 | /* Ignore the low bit in the target, since it will be set | |
16959 | for a text label. */ | |
16960 | if ((val & 1) != 0) | |
16961 | --val; | |
16962 | ||
16963 | /* Assume this is a 2-byte branch. */ | |
16964 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
16965 | ||
16966 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
16967 | long branches. */ | |
16968 | ||
16969 | val -= addr; | |
16970 | ||
16971 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
16972 | if (type == 'D') | |
16973 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
16974 | else if (type == 'E') | |
16975 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
16976 | else | |
16977 | abort (); | |
16978 | } | |
16979 | else | |
16980 | /* If the symbol is not defined or it's in a different segment, | |
16981 | we emit a normal 32-bit branch. */ | |
16982 | toofar = TRUE; | |
16983 | ||
16984 | if (fragp && update | |
16985 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
16986 | fragp->fr_subtype | |
16987 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
16988 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
16989 | ||
16990 | if (toofar) | |
16991 | return 4; | |
16992 | ||
16993 | return 2; | |
16994 | } | |
16995 | ||
252b5132 RH |
16996 | /* Estimate the size of a frag before relaxing. Unless this is the |
16997 | mips16, we are not really relaxing here, and the final size is | |
16998 | encoded in the subtype information. For the mips16, we have to | |
16999 | decide whether we are using an extended opcode or not. */ | |
17000 | ||
252b5132 | 17001 | int |
17a2f251 | 17002 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17003 | { |
5919d012 | 17004 | int change; |
252b5132 | 17005 | |
4a6a3df4 AO |
17006 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17007 | { | |
17008 | ||
b34976b6 AM |
17009 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17010 | ||
4a6a3df4 AO |
17011 | return fragp->fr_var; |
17012 | } | |
17013 | ||
252b5132 | 17014 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17015 | /* We don't want to modify the EXTENDED bit here; it might get us |
17016 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17017 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17018 | |
df58fc94 RS |
17019 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17020 | { | |
17021 | int length = 4; | |
17022 | ||
17023 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17024 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17025 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17026 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17027 | fragp->fr_var = length; | |
17028 | ||
17029 | return length; | |
17030 | } | |
17031 | ||
252b5132 | 17032 | if (mips_pic == NO_PIC) |
5919d012 | 17033 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17034 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17035 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17036 | else if (mips_pic == VXWORKS_PIC) |
17037 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17038 | change = 0; | |
252b5132 RH |
17039 | else |
17040 | abort (); | |
17041 | ||
17042 | if (change) | |
17043 | { | |
4d7206a2 | 17044 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17045 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17046 | } |
4d7206a2 RS |
17047 | else |
17048 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17049 | } |
17050 | ||
17051 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17052 | should be converted into a reloc against a section. */ |
252b5132 RH |
17053 | |
17054 | int | |
17a2f251 | 17055 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17056 | { |
252b5132 RH |
17057 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17058 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17059 | return 0; | |
a161fe53 | 17060 | |
252b5132 RH |
17061 | if (fixp->fx_addsy == NULL) |
17062 | return 1; | |
a161fe53 | 17063 | |
2f0c68f2 CM |
17064 | /* Allow relocs used for EH tables. */ |
17065 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17066 | return 1; | |
17067 | ||
de7e6852 RS |
17068 | /* If symbol SYM is in a mergeable section, relocations of the form |
17069 | SYM + 0 can usually be made section-relative. The mergeable data | |
17070 | is then identified by the section offset rather than by the symbol. | |
17071 | ||
17072 | However, if we're generating REL LO16 relocations, the offset is split | |
17073 | between the LO16 and parterning high part relocation. The linker will | |
17074 | need to recalculate the complete offset in order to correctly identify | |
17075 | the merge data. | |
17076 | ||
17077 | The linker has traditionally not looked for the parterning high part | |
17078 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17079 | placed anywhere. Rather than break backwards compatibility by changing | |
17080 | this, it seems better not to force the issue, and instead keep the | |
17081 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17082 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17083 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17084 | && HAVE_IN_PLACE_ADDENDS |
17085 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17086 | return 0; | |
17087 | ||
ce70d90a | 17088 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17089 | Likewise an in-range offset of limited PC-relative relocations may |
17090 | overflow the in-place relocatable field if recalculated against the | |
7361da2c AB |
17091 | start address of the symbol's containing section. |
17092 | ||
17093 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17094 | section relative to allow linker relaxations to be performed later on. */ | |
17095 | if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa)) | |
2de39019 CM |
17096 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17097 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17098 | return 0; |
17099 | ||
b314ec0e RS |
17100 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17101 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17102 | relocations against MIPS16 functions; in this case, the stub becomes | |
17103 | the function's canonical address. | |
17104 | ||
17105 | Floating-point stubs are stored in unique .mips16.call.* or | |
17106 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17107 | the first relocation in section S must be against F; this is how the | |
17108 | linker determines the target function. All relocations that might | |
17109 | resolve to T must also be against F. We therefore have the following | |
17110 | restrictions, which are given in an intentionally-redundant way: | |
17111 | ||
17112 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17113 | symbols. | |
17114 | ||
17115 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17116 | if that stub might be used. | |
17117 | ||
17118 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17119 | symbols. | |
17120 | ||
17121 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17122 | that stub might be used. | |
17123 | ||
17124 | There is a further restriction: | |
17125 | ||
df58fc94 RS |
17126 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17127 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17128 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17129 | encode the low bit. |
17130 | ||
df58fc94 RS |
17131 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17132 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17133 | such relocations on REL targets. | |
b314ec0e RS |
17134 | |
17135 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17136 | relocation against some symbol R, no relocation against R may be | |
17137 | reduced. (Note that this deals with (2) as well as (1) because | |
17138 | relocations against global symbols will never be reduced on ELF | |
17139 | targets.) This approach is a little simpler than trying to detect | |
17140 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17141 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17142 | if (fixp->fx_subsy == NULL |
30c09090 | 17143 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17144 | || *symbol_get_tc (fixp->fx_addsy) |
17145 | || (HAVE_IN_PLACE_ADDENDS | |
17146 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17147 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 17148 | return 0; |
a161fe53 | 17149 | |
252b5132 RH |
17150 | return 1; |
17151 | } | |
17152 | ||
17153 | /* Translate internal representation of relocation info to BFD target | |
17154 | format. */ | |
17155 | ||
17156 | arelent ** | |
17a2f251 | 17157 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17158 | { |
17159 | static arelent *retval[4]; | |
17160 | arelent *reloc; | |
17161 | bfd_reloc_code_real_type code; | |
17162 | ||
4b0cff4e TS |
17163 | memset (retval, 0, sizeof(retval)); |
17164 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17165 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17166 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17167 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17168 | ||
bad36eac DJ |
17169 | if (fixp->fx_pcrel) |
17170 | { | |
df58fc94 RS |
17171 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17172 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17173 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 17174 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
17175 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
17176 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
17177 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
17178 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
17179 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
17180 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
17181 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
17182 | |
17183 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17184 | Relocations want only the symbol offset. */ | |
17185 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
17186 | } |
17187 | else | |
17188 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17189 | |
438c16b8 TS |
17190 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17191 | entry to be used in the relocation's section offset. */ | |
17192 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17193 | { |
17194 | reloc->address = reloc->addend; | |
17195 | reloc->addend = 0; | |
17196 | } | |
17197 | ||
252b5132 | 17198 | code = fixp->fx_r_type; |
252b5132 | 17199 | |
bad36eac | 17200 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17201 | if (reloc->howto == NULL) |
17202 | { | |
17203 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
17204 | _("cannot represent %s relocation in this object file" |
17205 | " format"), | |
252b5132 RH |
17206 | bfd_get_reloc_code_name (code)); |
17207 | retval[0] = NULL; | |
17208 | } | |
17209 | ||
17210 | return retval; | |
17211 | } | |
17212 | ||
17213 | /* Relax a machine dependent frag. This returns the amount by which | |
17214 | the current size of the frag should change. */ | |
17215 | ||
17216 | int | |
17a2f251 | 17217 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17218 | { |
4a6a3df4 AO |
17219 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17220 | { | |
17221 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17222 | |
17223 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17224 | |
17225 | return fragp->fr_var - old_var; | |
17226 | } | |
17227 | ||
df58fc94 RS |
17228 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17229 | { | |
17230 | offsetT old_var = fragp->fr_var; | |
17231 | offsetT new_var = 4; | |
17232 | ||
17233 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17234 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17235 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17236 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17237 | fragp->fr_var = new_var; | |
17238 | ||
17239 | return new_var - old_var; | |
17240 | } | |
17241 | ||
252b5132 RH |
17242 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17243 | return 0; | |
17244 | ||
c4e7957c | 17245 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17246 | { |
17247 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17248 | return 0; | |
17249 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17250 | return 2; | |
17251 | } | |
17252 | else | |
17253 | { | |
17254 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17255 | return 0; | |
17256 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17257 | return -2; | |
17258 | } | |
17259 | ||
17260 | return 0; | |
17261 | } | |
17262 | ||
17263 | /* Convert a machine dependent frag. */ | |
17264 | ||
17265 | void | |
17a2f251 | 17266 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17267 | { |
4a6a3df4 AO |
17268 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17269 | { | |
4d68580a | 17270 | char *buf; |
4a6a3df4 AO |
17271 | unsigned long insn; |
17272 | expressionS exp; | |
17273 | fixS *fixp; | |
b34976b6 | 17274 | |
4d68580a RS |
17275 | buf = fragp->fr_literal + fragp->fr_fix; |
17276 | insn = read_insn (buf); | |
b34976b6 | 17277 | |
4a6a3df4 AO |
17278 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17279 | { | |
17280 | /* We generate a fixup instead of applying it right now | |
17281 | because, if there are linker relaxations, we're going to | |
17282 | need the relocations. */ | |
17283 | exp.X_op = O_symbol; | |
17284 | exp.X_add_symbol = fragp->fr_symbol; | |
17285 | exp.X_add_number = fragp->fr_offset; | |
17286 | ||
4d68580a RS |
17287 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
17288 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
17289 | fixp->fx_file = fragp->fr_file; |
17290 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17291 | |
4d68580a | 17292 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17293 | } |
17294 | else | |
17295 | { | |
17296 | int i; | |
17297 | ||
17298 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 17299 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17300 | |
17301 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17302 | goto uncond; | |
17303 | ||
17304 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17305 | { | |
17306 | /* Reverse the branch. */ | |
17307 | switch ((insn >> 28) & 0xf) | |
17308 | { | |
17309 | case 4: | |
56d438b1 CF |
17310 | if ((insn & 0xff000000) == 0x47000000 |
17311 | || (insn & 0xff600000) == 0x45600000) | |
17312 | { | |
17313 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
17314 | reversed by tweaking bit 23. */ | |
17315 | insn ^= 0x00800000; | |
17316 | } | |
17317 | else | |
17318 | { | |
17319 | /* bc[0-3][tf]l? instructions can have the condition | |
17320 | reversed by tweaking a single TF bit, and their | |
17321 | opcodes all have 0x4???????. */ | |
17322 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
17323 | insn ^= 0x00010000; | |
17324 | } | |
4a6a3df4 AO |
17325 | break; |
17326 | ||
17327 | case 0: | |
17328 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17329 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17330 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17331 | insn ^= 0x00010000; |
17332 | break; | |
b34976b6 | 17333 | |
4a6a3df4 AO |
17334 | case 1: |
17335 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17336 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17337 | insn ^= 0x04000000; |
17338 | break; | |
17339 | ||
17340 | default: | |
17341 | abort (); | |
17342 | } | |
17343 | } | |
17344 | ||
17345 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17346 | { | |
17347 | /* Clear the and-link bit. */ | |
9c2799c2 | 17348 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17349 | |
54f4ddb3 TS |
17350 | /* bltzal 0x04100000 bgezal 0x04110000 |
17351 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17352 | insn &= ~0x00100000; |
17353 | } | |
17354 | ||
17355 | /* Branch over the branch (if the branch was likely) or the | |
17356 | full jump (not likely case). Compute the offset from the | |
17357 | current instruction to branch to. */ | |
17358 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17359 | i = 16; | |
17360 | else | |
17361 | { | |
17362 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17363 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17364 | /* How many bytes in instructions from here to the end? */ |
17365 | i = fragp->fr_var - i; | |
17366 | } | |
17367 | /* Convert to instruction count. */ | |
17368 | i >>= 2; | |
17369 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17370 | i--; |
4a6a3df4 AO |
17371 | insn |= i; |
17372 | /* Branch over the jump. */ | |
4d68580a | 17373 | buf = write_insn (buf, insn); |
4a6a3df4 | 17374 | |
54f4ddb3 | 17375 | /* nop */ |
4d68580a | 17376 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
17377 | |
17378 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17379 | { | |
17380 | /* beql $0, $0, 2f */ | |
17381 | insn = 0x50000000; | |
17382 | /* Compute the PC offset from the current instruction to | |
17383 | the end of the variable frag. */ | |
17384 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17385 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17386 | /* How many bytes in instructions from here to the end? */ |
17387 | i = fragp->fr_var - i; | |
17388 | /* Convert to instruction count. */ | |
17389 | i >>= 2; | |
17390 | /* Don't decrement i, because we want to branch over the | |
17391 | delay slot. */ | |
4a6a3df4 | 17392 | insn |= i; |
4a6a3df4 | 17393 | |
4d68580a RS |
17394 | buf = write_insn (buf, insn); |
17395 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
17396 | } |
17397 | ||
17398 | uncond: | |
17399 | if (mips_pic == NO_PIC) | |
17400 | { | |
17401 | /* j or jal. */ | |
17402 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17403 | ? 0x0c000000 : 0x08000000); | |
17404 | exp.X_op = O_symbol; | |
17405 | exp.X_add_symbol = fragp->fr_symbol; | |
17406 | exp.X_add_number = fragp->fr_offset; | |
17407 | ||
4d68580a RS |
17408 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17409 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
17410 | fixp->fx_file = fragp->fr_file; |
17411 | fixp->fx_line = fragp->fr_line; | |
17412 | ||
4d68580a | 17413 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17414 | } |
17415 | else | |
17416 | { | |
66b3e8da MR |
17417 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17418 | ||
4a6a3df4 | 17419 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17420 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17421 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17422 | exp.X_op = O_symbol; |
17423 | exp.X_add_symbol = fragp->fr_symbol; | |
17424 | exp.X_add_number = fragp->fr_offset; | |
17425 | ||
17426 | if (fragp->fr_offset) | |
17427 | { | |
17428 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17429 | exp.X_add_number = 0; | |
17430 | } | |
17431 | ||
4d68580a RS |
17432 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17433 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
17434 | fixp->fx_file = fragp->fr_file; |
17435 | fixp->fx_line = fragp->fr_line; | |
17436 | ||
4d68580a | 17437 | buf = write_insn (buf, insn); |
b34976b6 | 17438 | |
4a6a3df4 | 17439 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
17440 | /* nop */ |
17441 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
17442 | |
17443 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17444 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17445 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 17446 | |
4d68580a RS |
17447 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17448 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
17449 | fixp->fx_file = fragp->fr_file; |
17450 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17451 | |
4d68580a | 17452 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17453 | |
17454 | /* j(al)r $at. */ | |
17455 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17456 | insn = 0x0000f809; |
4a6a3df4 | 17457 | else |
66b3e8da MR |
17458 | insn = 0x00000008; |
17459 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17460 | |
4d68580a | 17461 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17462 | } |
17463 | } | |
17464 | ||
4a6a3df4 | 17465 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 17466 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
17467 | return; |
17468 | } | |
17469 | ||
df58fc94 RS |
17470 | /* Relax microMIPS branches. */ |
17471 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17472 | { | |
4d68580a | 17473 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
17474 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
17475 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17476 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17477 | bfd_boolean short_ds; |
df58fc94 RS |
17478 | unsigned long insn; |
17479 | expressionS exp; | |
17480 | fixS *fixp; | |
17481 | ||
17482 | exp.X_op = O_symbol; | |
17483 | exp.X_add_symbol = fragp->fr_symbol; | |
17484 | exp.X_add_number = fragp->fr_offset; | |
17485 | ||
17486 | fragp->fr_fix += fragp->fr_var; | |
17487 | ||
17488 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17489 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17490 | { | |
17491 | /* We generate a fixup instead of applying it right now, | |
17492 | because if there is linker relaxation, we're going to | |
17493 | need the relocations. */ | |
17494 | if (type == 'D') | |
4d68580a | 17495 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
17496 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
17497 | else if (type == 'E') | |
4d68580a | 17498 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
17499 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
17500 | else | |
17501 | abort (); | |
17502 | ||
17503 | fixp->fx_file = fragp->fr_file; | |
17504 | fixp->fx_line = fragp->fr_line; | |
17505 | ||
17506 | /* These relocations can have an addend that won't fit in | |
17507 | 2 octets. */ | |
17508 | fixp->fx_no_overflow = 1; | |
17509 | ||
17510 | return; | |
17511 | } | |
17512 | ||
2309ddf2 | 17513 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17514 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17515 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17516 | { | |
17517 | /* We generate a fixup instead of applying it right now, | |
17518 | because if there is linker relaxation, we're going to | |
17519 | need the relocations. */ | |
4d68580a RS |
17520 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
17521 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
17522 | fixp->fx_file = fragp->fr_file; |
17523 | fixp->fx_line = fragp->fr_line; | |
17524 | ||
17525 | if (type == 0) | |
17526 | return; | |
17527 | } | |
17528 | ||
17529 | /* Relax 16-bit branches to 32-bit branches. */ | |
17530 | if (type != 0) | |
17531 | { | |
4d68580a | 17532 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
17533 | |
17534 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17535 | insn = 0x94000000; /* beq */ | |
17536 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17537 | { | |
17538 | unsigned long regno; | |
17539 | ||
17540 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17541 | regno = micromips_to_32_reg_d_map [regno]; | |
17542 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17543 | insn |= regno << MICROMIPSOP_SH_RS; | |
17544 | } | |
17545 | else | |
17546 | abort (); | |
17547 | ||
17548 | /* Nothing else to do, just write it out. */ | |
17549 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
17550 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17551 | { | |
4d68580a RS |
17552 | buf = write_compressed_insn (buf, insn, 4); |
17553 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
17554 | return; |
17555 | } | |
17556 | } | |
17557 | else | |
4d68580a | 17558 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
17559 | |
17560 | /* Relax 32-bit branches to a sequence of instructions. */ | |
17561 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 17562 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 17563 | |
2309ddf2 MR |
17564 | /* Set the short-delay-slot bit. */ |
17565 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
17566 | |
17567 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
17568 | { | |
17569 | symbolS *l; | |
17570 | ||
17571 | /* Reverse the branch. */ | |
17572 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
17573 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
17574 | insn ^= 0x20000000; | |
17575 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
17576 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
17577 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
17578 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
17579 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
17580 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
17581 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
17582 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
17583 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
17584 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
17585 | insn ^= 0x00400000; | |
17586 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
17587 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
17588 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
17589 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
17590 | insn ^= 0x00200000; | |
56d438b1 CF |
17591 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
17592 | BNZ.df */ | |
17593 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
17594 | BNZ.V */ | |
17595 | insn ^= 0x00800000; | |
df58fc94 RS |
17596 | else |
17597 | abort (); | |
17598 | ||
17599 | if (al) | |
17600 | { | |
17601 | /* Clear the and-link and short-delay-slot bits. */ | |
17602 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
17603 | ||
17604 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
17605 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
17606 | insn &= ~0x02200000; | |
17607 | } | |
17608 | ||
17609 | /* Make a label at the end for use with the branch. */ | |
17610 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
17611 | micromips_label_inc (); | |
f3ded42a | 17612 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
17613 | |
17614 | /* Refer to it. */ | |
4d68580a RS |
17615 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
17616 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
17617 | fixp->fx_file = fragp->fr_file; |
17618 | fixp->fx_line = fragp->fr_line; | |
17619 | ||
17620 | /* Branch over the jump. */ | |
4d68580a | 17621 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 17622 | if (!compact) |
4d68580a RS |
17623 | /* nop */ |
17624 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
17625 | } |
17626 | ||
17627 | if (mips_pic == NO_PIC) | |
17628 | { | |
2309ddf2 MR |
17629 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
17630 | ||
df58fc94 RS |
17631 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
17632 | insn = al ? jal : 0xd4000000; | |
17633 | ||
4d68580a RS |
17634 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17635 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
17636 | fixp->fx_file = fragp->fr_file; |
17637 | fixp->fx_line = fragp->fr_line; | |
17638 | ||
4d68580a | 17639 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 17640 | if (compact) |
4d68580a RS |
17641 | /* nop */ |
17642 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
17643 | } |
17644 | else | |
17645 | { | |
17646 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
17647 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
17648 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
17649 | |
17650 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
17651 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
17652 | insn |= at << MICROMIPSOP_SH_RT; | |
17653 | ||
17654 | if (exp.X_add_number) | |
17655 | { | |
17656 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17657 | exp.X_add_number = 0; | |
17658 | } | |
17659 | ||
4d68580a RS |
17660 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17661 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
17662 | fixp->fx_file = fragp->fr_file; |
17663 | fixp->fx_line = fragp->fr_line; | |
17664 | ||
4d68580a | 17665 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
17666 | |
17667 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
17668 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
17669 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
17670 | ||
4d68580a RS |
17671 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
17672 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
17673 | fixp->fx_file = fragp->fr_file; |
17674 | fixp->fx_line = fragp->fr_line; | |
17675 | ||
4d68580a | 17676 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
17677 | |
17678 | /* jr/jrc/jalr/jalrs $at */ | |
17679 | insn = al ? jalr : jr; | |
17680 | insn |= at << MICROMIPSOP_SH_MJ; | |
17681 | ||
4d68580a | 17682 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
17683 | } |
17684 | ||
4d68580a | 17685 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
17686 | return; |
17687 | } | |
17688 | ||
252b5132 RH |
17689 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
17690 | { | |
17691 | int type; | |
3ccad066 | 17692 | const struct mips_int_operand *operand; |
252b5132 | 17693 | offsetT val; |
5c04167a RS |
17694 | char *buf; |
17695 | unsigned int user_length, length; | |
252b5132 | 17696 | unsigned long insn; |
5c04167a | 17697 | bfd_boolean ext; |
252b5132 RH |
17698 | |
17699 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 17700 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 17701 | |
5c04167a | 17702 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 17703 | val = resolve_symbol_value (fragp->fr_symbol); |
3ccad066 | 17704 | if (operand->root.type == OP_PCREL) |
252b5132 | 17705 | { |
3ccad066 | 17706 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 RH |
17707 | addressT addr; |
17708 | ||
3ccad066 | 17709 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 RH |
17710 | addr = fragp->fr_address + fragp->fr_fix; |
17711 | ||
17712 | /* The rules for the base address of a PC relative reloc are | |
17713 | complicated; see mips16_extended_frag. */ | |
3ccad066 | 17714 | if (pcrel_op->include_isa_bit) |
252b5132 RH |
17715 | { |
17716 | addr += 2; | |
17717 | if (ext) | |
17718 | addr += 2; | |
17719 | /* Ignore the low bit in the target, since it will be | |
17720 | set for a text label. */ | |
3ccad066 | 17721 | val &= -2; |
252b5132 RH |
17722 | } |
17723 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17724 | addr -= 4; | |
17725 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17726 | addr -= 2; | |
17727 | ||
3ccad066 | 17728 | addr &= -(1 << pcrel_op->align_log2); |
252b5132 RH |
17729 | val -= addr; |
17730 | ||
17731 | /* Make sure the section winds up with the alignment we have | |
17732 | assumed. */ | |
3ccad066 RS |
17733 | if (operand->shift > 0) |
17734 | record_alignment (asec, operand->shift); | |
252b5132 RH |
17735 | } |
17736 | ||
17737 | if (ext | |
17738 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
17739 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
17740 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17741 | _("extended instruction in delay slot")); | |
17742 | ||
5c04167a | 17743 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 17744 | |
4d68580a | 17745 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
17746 | if (ext) |
17747 | insn |= MIPS16_EXTEND; | |
252b5132 | 17748 | |
5c04167a RS |
17749 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
17750 | user_length = 4; | |
17751 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17752 | user_length = 2; | |
17753 | else | |
17754 | user_length = 0; | |
17755 | ||
43c0598f | 17756 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 17757 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 17758 | |
5c04167a RS |
17759 | length = (ext ? 4 : 2); |
17760 | gas_assert (mips16_opcode_length (insn) == length); | |
17761 | write_compressed_insn (buf, insn, length); | |
17762 | fragp->fr_fix += length; | |
252b5132 RH |
17763 | } |
17764 | else | |
17765 | { | |
df58fc94 RS |
17766 | relax_substateT subtype = fragp->fr_subtype; |
17767 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
17768 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
17769 | int first, second; |
17770 | fixS *fixp; | |
252b5132 | 17771 | |
df58fc94 RS |
17772 | first = RELAX_FIRST (subtype); |
17773 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 17774 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 17775 | |
df58fc94 RS |
17776 | /* If the delay slot chosen does not match the size of the instruction, |
17777 | then emit a warning. */ | |
17778 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
17779 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
17780 | { | |
17781 | relax_substateT s; | |
17782 | const char *msg; | |
17783 | ||
17784 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
17785 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
17786 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
17787 | msg = macro_warning (s); | |
17788 | if (msg != NULL) | |
db9b2be4 | 17789 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
17790 | subtype &= ~s; |
17791 | } | |
17792 | ||
584892a6 | 17793 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 17794 | if (use_second == second_longer) |
584892a6 | 17795 | { |
df58fc94 RS |
17796 | relax_substateT s; |
17797 | const char *msg; | |
17798 | ||
17799 | s = (subtype | |
17800 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
17801 | msg = macro_warning (s); | |
17802 | if (msg != NULL) | |
db9b2be4 | 17803 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 17804 | subtype &= ~s; |
584892a6 RS |
17805 | } |
17806 | ||
4d7206a2 RS |
17807 | /* Go through all the fixups for the first sequence. Disable them |
17808 | (by marking them as done) if we're going to use the second | |
17809 | sequence instead. */ | |
17810 | while (fixp | |
17811 | && fixp->fx_frag == fragp | |
17812 | && fixp->fx_where < fragp->fr_fix - second) | |
17813 | { | |
df58fc94 | 17814 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17815 | fixp->fx_done = 1; |
17816 | fixp = fixp->fx_next; | |
17817 | } | |
252b5132 | 17818 | |
4d7206a2 RS |
17819 | /* Go through the fixups for the second sequence. Disable them if |
17820 | we're going to use the first sequence, otherwise adjust their | |
17821 | addresses to account for the relaxation. */ | |
17822 | while (fixp && fixp->fx_frag == fragp) | |
17823 | { | |
df58fc94 | 17824 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17825 | fixp->fx_where -= first; |
17826 | else | |
17827 | fixp->fx_done = 1; | |
17828 | fixp = fixp->fx_next; | |
17829 | } | |
17830 | ||
17831 | /* Now modify the frag contents. */ | |
df58fc94 | 17832 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
17833 | { |
17834 | char *start; | |
17835 | ||
17836 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
17837 | memmove (start, start + first, second); | |
17838 | fragp->fr_fix -= first; | |
17839 | } | |
17840 | else | |
17841 | fragp->fr_fix -= second; | |
252b5132 RH |
17842 | } |
17843 | } | |
17844 | ||
252b5132 RH |
17845 | /* This function is called after the relocs have been generated. |
17846 | We've been storing mips16 text labels as odd. Here we convert them | |
17847 | back to even for the convenience of the debugger. */ | |
17848 | ||
17849 | void | |
17a2f251 | 17850 | mips_frob_file_after_relocs (void) |
252b5132 RH |
17851 | { |
17852 | asymbol **syms; | |
17853 | unsigned int count, i; | |
17854 | ||
252b5132 RH |
17855 | syms = bfd_get_outsymbols (stdoutput); |
17856 | count = bfd_get_symcount (stdoutput); | |
17857 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
17858 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
17859 | && ((*syms)->value & 1) != 0) | |
17860 | { | |
17861 | (*syms)->value &= ~1; | |
17862 | /* If the symbol has an odd size, it was probably computed | |
17863 | incorrectly, so adjust that as well. */ | |
17864 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
17865 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
17866 | } | |
252b5132 RH |
17867 | } |
17868 | ||
a1facbec MR |
17869 | /* This function is called whenever a label is defined, including fake |
17870 | labels instantiated off the dot special symbol. It is used when | |
17871 | handling branch delays; if a branch has a label, we assume we cannot | |
17872 | move it. This also bumps the value of the symbol by 1 in compressed | |
17873 | code. */ | |
252b5132 | 17874 | |
e1b47bd5 | 17875 | static void |
a1facbec | 17876 | mips_record_label (symbolS *sym) |
252b5132 | 17877 | { |
a8dbcb85 | 17878 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
17879 | struct insn_label_list *l; |
17880 | ||
17881 | if (free_insn_labels == NULL) | |
17882 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
17883 | else | |
17884 | { | |
17885 | l = free_insn_labels; | |
17886 | free_insn_labels = l->next; | |
17887 | } | |
17888 | ||
17889 | l->label = sym; | |
a8dbcb85 TS |
17890 | l->next = si->label_list; |
17891 | si->label_list = l; | |
a1facbec | 17892 | } |
07a53e5c | 17893 | |
a1facbec MR |
17894 | /* This function is called as tc_frob_label() whenever a label is defined |
17895 | and adds a DWARF-2 record we only want for true labels. */ | |
17896 | ||
17897 | void | |
17898 | mips_define_label (symbolS *sym) | |
17899 | { | |
17900 | mips_record_label (sym); | |
07a53e5c | 17901 | dwarf2_emit_label (sym); |
252b5132 | 17902 | } |
e1b47bd5 RS |
17903 | |
17904 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
17905 | is defined. */ | |
17906 | ||
17907 | void | |
17908 | mips_add_dot_label (symbolS *sym) | |
17909 | { | |
17910 | mips_record_label (sym); | |
17911 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
17912 | mips_compressed_mark_label (sym); | |
17913 | } | |
252b5132 | 17914 | \f |
351cdf24 MF |
17915 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
17916 | static unsigned int | |
17917 | mips_convert_ase_flags (int ase) | |
17918 | { | |
17919 | unsigned int ext_ases = 0; | |
17920 | ||
17921 | if (ase & ASE_DSP) | |
17922 | ext_ases |= AFL_ASE_DSP; | |
17923 | if (ase & ASE_DSPR2) | |
17924 | ext_ases |= AFL_ASE_DSPR2; | |
17925 | if (ase & ASE_EVA) | |
17926 | ext_ases |= AFL_ASE_EVA; | |
17927 | if (ase & ASE_MCU) | |
17928 | ext_ases |= AFL_ASE_MCU; | |
17929 | if (ase & ASE_MDMX) | |
17930 | ext_ases |= AFL_ASE_MDMX; | |
17931 | if (ase & ASE_MIPS3D) | |
17932 | ext_ases |= AFL_ASE_MIPS3D; | |
17933 | if (ase & ASE_MT) | |
17934 | ext_ases |= AFL_ASE_MT; | |
17935 | if (ase & ASE_SMARTMIPS) | |
17936 | ext_ases |= AFL_ASE_SMARTMIPS; | |
17937 | if (ase & ASE_VIRT) | |
17938 | ext_ases |= AFL_ASE_VIRT; | |
17939 | if (ase & ASE_MSA) | |
17940 | ext_ases |= AFL_ASE_MSA; | |
17941 | if (ase & ASE_XPA) | |
17942 | ext_ases |= AFL_ASE_XPA; | |
17943 | ||
17944 | return ext_ases; | |
17945 | } | |
252b5132 RH |
17946 | /* Some special processing for a MIPS ELF file. */ |
17947 | ||
17948 | void | |
17a2f251 | 17949 | mips_elf_final_processing (void) |
252b5132 | 17950 | { |
351cdf24 MF |
17951 | int fpabi; |
17952 | Elf_Internal_ABIFlags_v0 flags; | |
17953 | ||
17954 | flags.version = 0; | |
17955 | flags.isa_rev = 0; | |
17956 | switch (file_mips_opts.isa) | |
17957 | { | |
17958 | case INSN_ISA1: | |
17959 | flags.isa_level = 1; | |
17960 | break; | |
17961 | case INSN_ISA2: | |
17962 | flags.isa_level = 2; | |
17963 | break; | |
17964 | case INSN_ISA3: | |
17965 | flags.isa_level = 3; | |
17966 | break; | |
17967 | case INSN_ISA4: | |
17968 | flags.isa_level = 4; | |
17969 | break; | |
17970 | case INSN_ISA5: | |
17971 | flags.isa_level = 5; | |
17972 | break; | |
17973 | case INSN_ISA32: | |
17974 | flags.isa_level = 32; | |
17975 | flags.isa_rev = 1; | |
17976 | break; | |
17977 | case INSN_ISA32R2: | |
17978 | flags.isa_level = 32; | |
17979 | flags.isa_rev = 2; | |
17980 | break; | |
17981 | case INSN_ISA32R3: | |
17982 | flags.isa_level = 32; | |
17983 | flags.isa_rev = 3; | |
17984 | break; | |
17985 | case INSN_ISA32R5: | |
17986 | flags.isa_level = 32; | |
17987 | flags.isa_rev = 5; | |
17988 | break; | |
09c14161 MF |
17989 | case INSN_ISA32R6: |
17990 | flags.isa_level = 32; | |
17991 | flags.isa_rev = 6; | |
17992 | break; | |
351cdf24 MF |
17993 | case INSN_ISA64: |
17994 | flags.isa_level = 64; | |
17995 | flags.isa_rev = 1; | |
17996 | break; | |
17997 | case INSN_ISA64R2: | |
17998 | flags.isa_level = 64; | |
17999 | flags.isa_rev = 2; | |
18000 | break; | |
18001 | case INSN_ISA64R3: | |
18002 | flags.isa_level = 64; | |
18003 | flags.isa_rev = 3; | |
18004 | break; | |
18005 | case INSN_ISA64R5: | |
18006 | flags.isa_level = 64; | |
18007 | flags.isa_rev = 5; | |
18008 | break; | |
09c14161 MF |
18009 | case INSN_ISA64R6: |
18010 | flags.isa_level = 64; | |
18011 | flags.isa_rev = 6; | |
18012 | break; | |
351cdf24 MF |
18013 | } |
18014 | ||
18015 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
18016 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
18017 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
18018 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
18019 | : AFL_REG_32; | |
18020 | flags.cpr2_size = AFL_REG_NONE; | |
18021 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
18022 | Tag_GNU_MIPS_ABI_FP); | |
18023 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
18024 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
18025 | if (file_ase_mips16) | |
18026 | flags.ases |= AFL_ASE_MIPS16; | |
18027 | if (file_ase_micromips) | |
18028 | flags.ases |= AFL_ASE_MICROMIPS; | |
18029 | flags.flags1 = 0; | |
18030 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
18031 | || file_mips_opts.fp == 64) | |
18032 | && file_mips_opts.oddspreg) | |
18033 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
18034 | flags.flags2 = 0; | |
18035 | ||
18036 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
18037 | ((Elf_External_ABIFlags_v0 *) | |
18038 | mips_flags_frag)); | |
18039 | ||
252b5132 | 18040 | /* Write out the register information. */ |
316f5878 | 18041 | if (mips_abi != N64_ABI) |
252b5132 RH |
18042 | { |
18043 | Elf32_RegInfo s; | |
18044 | ||
18045 | s.ri_gprmask = mips_gprmask; | |
18046 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18047 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18048 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18049 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18050 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18051 | ||
18052 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18053 | ((Elf32_External_RegInfo *) | |
18054 | mips_regmask_frag)); | |
18055 | } | |
18056 | else | |
18057 | { | |
18058 | Elf64_Internal_RegInfo s; | |
18059 | ||
18060 | s.ri_gprmask = mips_gprmask; | |
18061 | s.ri_pad = 0; | |
18062 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18063 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18064 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18065 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18066 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18067 | ||
18068 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18069 | ((Elf64_External_RegInfo *) | |
18070 | mips_regmask_frag)); | |
18071 | } | |
18072 | ||
18073 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18074 | sort of BFD interface for this. */ | |
18075 | if (mips_any_noreorder) | |
18076 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18077 | if (mips_pic != NO_PIC) | |
143d77c5 | 18078 | { |
8b828383 | 18079 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18080 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18081 | } | |
18082 | if (mips_abicalls) | |
18083 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18084 | |
b015e599 AP |
18085 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18086 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18087 | if (file_ase_mips16) |
18088 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18089 | if (file_ase_micromips) |
18090 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 18091 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 18092 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18093 | |
bdaaa2e1 | 18094 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18095 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18096 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18097 | else if (mips_abi == O64_ABI) |
252b5132 | 18098 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18099 | else if (mips_abi == EABI_ABI) |
252b5132 | 18100 | { |
bad1aba3 | 18101 | if (file_mips_opts.gp == 64) |
252b5132 RH |
18102 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18103 | else | |
18104 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18105 | } | |
316f5878 | 18106 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18107 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18108 | ||
c9914766 | 18109 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18110 | |
18111 | if (mips_32bitmode) | |
18112 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 18113 | |
7361da2c | 18114 | if (mips_nan2008 == 1) |
ba92f887 MR |
18115 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
18116 | ||
ad3fea08 | 18117 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
18118 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
18119 | Tag_GNU_MIPS_ABI_FP); | |
18120 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 18121 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 18122 | } |
252b5132 | 18123 | \f |
beae10d5 | 18124 | typedef struct proc { |
9b2f1d35 EC |
18125 | symbolS *func_sym; |
18126 | symbolS *func_end_sym; | |
beae10d5 KH |
18127 | unsigned long reg_mask; |
18128 | unsigned long reg_offset; | |
18129 | unsigned long fpreg_mask; | |
18130 | unsigned long fpreg_offset; | |
18131 | unsigned long frame_offset; | |
18132 | unsigned long frame_reg; | |
18133 | unsigned long pc_reg; | |
18134 | } procS; | |
252b5132 RH |
18135 | |
18136 | static procS cur_proc; | |
18137 | static procS *cur_proc_ptr; | |
18138 | static int numprocs; | |
18139 | ||
df58fc94 RS |
18140 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18141 | as "2", and a normal nop as "0". */ | |
18142 | ||
18143 | #define NOP_OPCODE_MIPS 0 | |
18144 | #define NOP_OPCODE_MIPS16 1 | |
18145 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18146 | |
18147 | char | |
18148 | mips_nop_opcode (void) | |
18149 | { | |
df58fc94 RS |
18150 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18151 | return NOP_OPCODE_MICROMIPS; | |
18152 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18153 | return NOP_OPCODE_MIPS16; | |
18154 | else | |
18155 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18156 | } |
18157 | ||
df58fc94 RS |
18158 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18159 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18160 | |
0a9ef439 | 18161 | void |
17a2f251 | 18162 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18163 | { |
df58fc94 | 18164 | char nop_opcode; |
742a56fe | 18165 | char *p; |
c67a084a NC |
18166 | int bytes, size, excess; |
18167 | valueT opcode; | |
742a56fe | 18168 | |
0a9ef439 RH |
18169 | if (fragp->fr_type != rs_align_code) |
18170 | return; | |
18171 | ||
742a56fe | 18172 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18173 | nop_opcode = *p; |
18174 | switch (nop_opcode) | |
a19d8eb0 | 18175 | { |
df58fc94 RS |
18176 | case NOP_OPCODE_MICROMIPS: |
18177 | opcode = micromips_nop32_insn.insn_opcode; | |
18178 | size = 4; | |
18179 | break; | |
18180 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18181 | opcode = mips16_nop_insn.insn_opcode; |
18182 | size = 2; | |
df58fc94 RS |
18183 | break; |
18184 | case NOP_OPCODE_MIPS: | |
18185 | default: | |
c67a084a NC |
18186 | opcode = nop_insn.insn_opcode; |
18187 | size = 4; | |
df58fc94 | 18188 | break; |
c67a084a | 18189 | } |
a19d8eb0 | 18190 | |
c67a084a NC |
18191 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18192 | excess = bytes % size; | |
df58fc94 RS |
18193 | |
18194 | /* Handle the leading part if we're not inserting a whole number of | |
18195 | instructions, and make it the end of the fixed part of the frag. | |
18196 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18197 | and use zeroes otherwise. */ | |
18198 | gas_assert (excess < 4); | |
18199 | fragp->fr_fix += excess; | |
18200 | switch (excess) | |
c67a084a | 18201 | { |
df58fc94 RS |
18202 | case 3: |
18203 | *p++ = '\0'; | |
18204 | /* Fall through. */ | |
18205 | case 2: | |
833794fc | 18206 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 18207 | { |
4d68580a | 18208 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18209 | break; |
18210 | } | |
18211 | *p++ = '\0'; | |
18212 | /* Fall through. */ | |
18213 | case 1: | |
18214 | *p++ = '\0'; | |
18215 | /* Fall through. */ | |
18216 | case 0: | |
18217 | break; | |
a19d8eb0 | 18218 | } |
c67a084a NC |
18219 | |
18220 | md_number_to_chars (p, opcode, size); | |
18221 | fragp->fr_var = size; | |
a19d8eb0 CP |
18222 | } |
18223 | ||
252b5132 | 18224 | static long |
17a2f251 | 18225 | get_number (void) |
252b5132 RH |
18226 | { |
18227 | int negative = 0; | |
18228 | long val = 0; | |
18229 | ||
18230 | if (*input_line_pointer == '-') | |
18231 | { | |
18232 | ++input_line_pointer; | |
18233 | negative = 1; | |
18234 | } | |
3882b010 | 18235 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18236 | as_bad (_("expected simple number")); |
252b5132 RH |
18237 | if (input_line_pointer[0] == '0') |
18238 | { | |
18239 | if (input_line_pointer[1] == 'x') | |
18240 | { | |
18241 | input_line_pointer += 2; | |
3882b010 | 18242 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18243 | { |
18244 | val <<= 4; | |
18245 | val |= hex_value (*input_line_pointer++); | |
18246 | } | |
18247 | return negative ? -val : val; | |
18248 | } | |
18249 | else | |
18250 | { | |
18251 | ++input_line_pointer; | |
3882b010 | 18252 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18253 | { |
18254 | val <<= 3; | |
18255 | val |= *input_line_pointer++ - '0'; | |
18256 | } | |
18257 | return negative ? -val : val; | |
18258 | } | |
18259 | } | |
3882b010 | 18260 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18261 | { |
18262 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18263 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18264 | as_warn (_("invalid number")); |
252b5132 RH |
18265 | return -1; |
18266 | } | |
3882b010 | 18267 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18268 | { |
18269 | val *= 10; | |
18270 | val += *input_line_pointer++ - '0'; | |
18271 | } | |
18272 | return negative ? -val : val; | |
18273 | } | |
18274 | ||
18275 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18276 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18277 | case .file implies DWARF-2. */ | |
18278 | ||
18279 | static void | |
17a2f251 | 18280 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18281 | { |
ecb4347a DJ |
18282 | static int first_file_directive = 0; |
18283 | ||
c5dd6aab DJ |
18284 | if (ECOFF_DEBUGGING) |
18285 | { | |
18286 | get_number (); | |
18287 | s_app_file (0); | |
18288 | } | |
18289 | else | |
ecb4347a DJ |
18290 | { |
18291 | char *filename; | |
18292 | ||
18293 | filename = dwarf2_directive_file (0); | |
18294 | ||
18295 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18296 | directive even for stabs output. Make sure that this | |
18297 | ".file" is handled. Note that you need a version of GCC | |
18298 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18299 | if (filename != NULL && ! first_file_directive) | |
18300 | { | |
18301 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18302 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18303 | } |
18304 | first_file_directive = 1; | |
18305 | } | |
c5dd6aab DJ |
18306 | } |
18307 | ||
18308 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18309 | |
18310 | static void | |
17a2f251 | 18311 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18312 | { |
c5dd6aab DJ |
18313 | if (!ECOFF_DEBUGGING) |
18314 | dwarf2_directive_loc (0); | |
252b5132 RH |
18315 | } |
18316 | ||
252b5132 RH |
18317 | /* The .end directive. */ |
18318 | ||
18319 | static void | |
17a2f251 | 18320 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18321 | { |
18322 | symbolS *p; | |
252b5132 | 18323 | |
7a621144 DJ |
18324 | /* Following functions need their own .frame and .cprestore directives. */ |
18325 | mips_frame_reg_valid = 0; | |
18326 | mips_cprestore_valid = 0; | |
18327 | ||
252b5132 RH |
18328 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18329 | { | |
18330 | p = get_symbol (); | |
18331 | demand_empty_rest_of_line (); | |
18332 | } | |
18333 | else | |
18334 | p = NULL; | |
18335 | ||
14949570 | 18336 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18337 | as_warn (_(".end not in text section")); |
18338 | ||
18339 | if (!cur_proc_ptr) | |
18340 | { | |
1661c76c | 18341 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
18342 | demand_empty_rest_of_line (); |
18343 | return; | |
18344 | } | |
18345 | ||
18346 | if (p != NULL) | |
18347 | { | |
9c2799c2 | 18348 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18349 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 18350 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
18351 | |
18352 | if (debug_type == DEBUG_STABS) | |
18353 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18354 | S_GET_NAME (p)); | |
252b5132 RH |
18355 | } |
18356 | else | |
18357 | as_warn (_(".end directive missing or unknown symbol")); | |
18358 | ||
9b2f1d35 EC |
18359 | /* Create an expression to calculate the size of the function. */ |
18360 | if (p && cur_proc_ptr) | |
18361 | { | |
18362 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18363 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18364 | ||
18365 | obj->size = exp; | |
18366 | exp->X_op = O_subtract; | |
18367 | exp->X_add_symbol = symbol_temp_new_now (); | |
18368 | exp->X_op_symbol = p; | |
18369 | exp->X_add_number = 0; | |
18370 | ||
18371 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18372 | } | |
18373 | ||
ecb4347a | 18374 | /* Generate a .pdr section. */ |
f3ded42a | 18375 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18376 | { |
18377 | segT saved_seg = now_seg; | |
18378 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18379 | expressionS exp; |
18380 | char *fragp; | |
252b5132 | 18381 | |
252b5132 | 18382 | #ifdef md_flush_pending_output |
ecb4347a | 18383 | md_flush_pending_output (); |
252b5132 RH |
18384 | #endif |
18385 | ||
9c2799c2 | 18386 | gas_assert (pdr_seg); |
ecb4347a | 18387 | subseg_set (pdr_seg, 0); |
252b5132 | 18388 | |
ecb4347a DJ |
18389 | /* Write the symbol. */ |
18390 | exp.X_op = O_symbol; | |
18391 | exp.X_add_symbol = p; | |
18392 | exp.X_add_number = 0; | |
18393 | emit_expr (&exp, 4); | |
252b5132 | 18394 | |
ecb4347a | 18395 | fragp = frag_more (7 * 4); |
252b5132 | 18396 | |
17a2f251 TS |
18397 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18398 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18399 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18400 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18401 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18402 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18403 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18404 | |
ecb4347a DJ |
18405 | subseg_set (saved_seg, saved_subseg); |
18406 | } | |
252b5132 RH |
18407 | |
18408 | cur_proc_ptr = NULL; | |
18409 | } | |
18410 | ||
18411 | /* The .aent and .ent directives. */ | |
18412 | ||
18413 | static void | |
17a2f251 | 18414 | s_mips_ent (int aent) |
252b5132 | 18415 | { |
252b5132 | 18416 | symbolS *symbolP; |
252b5132 RH |
18417 | |
18418 | symbolP = get_symbol (); | |
18419 | if (*input_line_pointer == ',') | |
f9419b05 | 18420 | ++input_line_pointer; |
252b5132 | 18421 | SKIP_WHITESPACE (); |
3882b010 | 18422 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18423 | || *input_line_pointer == '-') |
874e8986 | 18424 | get_number (); |
252b5132 | 18425 | |
14949570 | 18426 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 18427 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
18428 | |
18429 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18430 | as_warn (_("missing .end")); |
252b5132 RH |
18431 | |
18432 | if (!aent) | |
18433 | { | |
7a621144 DJ |
18434 | /* This function needs its own .frame and .cprestore directives. */ |
18435 | mips_frame_reg_valid = 0; | |
18436 | mips_cprestore_valid = 0; | |
18437 | ||
252b5132 RH |
18438 | cur_proc_ptr = &cur_proc; |
18439 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18440 | ||
9b2f1d35 | 18441 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18442 | |
f9419b05 | 18443 | ++numprocs; |
ecb4347a DJ |
18444 | |
18445 | if (debug_type == DEBUG_STABS) | |
18446 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18447 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18448 | } |
18449 | ||
7c0fc524 MR |
18450 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18451 | ||
252b5132 RH |
18452 | demand_empty_rest_of_line (); |
18453 | } | |
18454 | ||
18455 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18456 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18457 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18458 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18459 | symbol table (in the mdebug section). */ |
18460 | ||
18461 | static void | |
17a2f251 | 18462 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18463 | { |
f3ded42a RS |
18464 | if (ECOFF_DEBUGGING) |
18465 | s_ignore (ignore); | |
18466 | else | |
ecb4347a DJ |
18467 | { |
18468 | long val; | |
252b5132 | 18469 | |
ecb4347a DJ |
18470 | if (cur_proc_ptr == (procS *) NULL) |
18471 | { | |
18472 | as_warn (_(".frame outside of .ent")); | |
18473 | demand_empty_rest_of_line (); | |
18474 | return; | |
18475 | } | |
252b5132 | 18476 | |
ecb4347a DJ |
18477 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18478 | ||
18479 | SKIP_WHITESPACE (); | |
18480 | if (*input_line_pointer++ != ',' | |
18481 | || get_absolute_expression_and_terminator (&val) != ',') | |
18482 | { | |
1661c76c | 18483 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
18484 | --input_line_pointer; |
18485 | demand_empty_rest_of_line (); | |
18486 | return; | |
18487 | } | |
252b5132 | 18488 | |
ecb4347a DJ |
18489 | cur_proc_ptr->frame_offset = val; |
18490 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18491 | |
252b5132 | 18492 | demand_empty_rest_of_line (); |
252b5132 | 18493 | } |
252b5132 RH |
18494 | } |
18495 | ||
bdaaa2e1 KH |
18496 | /* The .fmask and .mask directives. If the mdebug section is present |
18497 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18498 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18499 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18500 | make reference to the ecoff symbol table (in the mdebug section). */ |
18501 | ||
18502 | static void | |
17a2f251 | 18503 | s_mips_mask (int reg_type) |
252b5132 | 18504 | { |
f3ded42a RS |
18505 | if (ECOFF_DEBUGGING) |
18506 | s_ignore (reg_type); | |
18507 | else | |
252b5132 | 18508 | { |
ecb4347a | 18509 | long mask, off; |
252b5132 | 18510 | |
ecb4347a DJ |
18511 | if (cur_proc_ptr == (procS *) NULL) |
18512 | { | |
18513 | as_warn (_(".mask/.fmask outside of .ent")); | |
18514 | demand_empty_rest_of_line (); | |
18515 | return; | |
18516 | } | |
252b5132 | 18517 | |
ecb4347a DJ |
18518 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18519 | { | |
1661c76c | 18520 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
18521 | --input_line_pointer; |
18522 | demand_empty_rest_of_line (); | |
18523 | return; | |
18524 | } | |
252b5132 | 18525 | |
ecb4347a DJ |
18526 | off = get_absolute_expression (); |
18527 | ||
18528 | if (reg_type == 'F') | |
18529 | { | |
18530 | cur_proc_ptr->fpreg_mask = mask; | |
18531 | cur_proc_ptr->fpreg_offset = off; | |
18532 | } | |
18533 | else | |
18534 | { | |
18535 | cur_proc_ptr->reg_mask = mask; | |
18536 | cur_proc_ptr->reg_offset = off; | |
18537 | } | |
18538 | ||
18539 | demand_empty_rest_of_line (); | |
252b5132 | 18540 | } |
252b5132 RH |
18541 | } |
18542 | ||
316f5878 RS |
18543 | /* A table describing all the processors gas knows about. Names are |
18544 | matched in the order listed. | |
e7af610e | 18545 | |
316f5878 RS |
18546 | To ease comparison, please keep this table in the same order as |
18547 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18548 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18549 | { | |
316f5878 | 18550 | /* Entries for generic ISAs */ |
d16afab6 RS |
18551 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
18552 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
18553 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
18554 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
18555 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
18556 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
18557 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
18558 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
18559 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 18560 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
18561 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
18562 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
18563 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
18564 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 18565 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
18566 | |
18567 | /* MIPS I */ | |
d16afab6 RS |
18568 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
18569 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
18570 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18571 | |
18572 | /* MIPS II */ | |
d16afab6 | 18573 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18574 | |
18575 | /* MIPS III */ | |
d16afab6 RS |
18576 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
18577 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
18578 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
18579 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
18580 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
18581 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
18582 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
18583 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
18584 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
18585 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
18586 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
18587 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
18588 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 18589 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
18590 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
18591 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18592 | |
18593 | /* MIPS IV */ | |
d16afab6 RS |
18594 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
18595 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
18596 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
18597 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
18598 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
18599 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18600 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
18601 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
18602 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18603 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18604 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18605 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18606 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
18607 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
18608 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
18609 | |
18610 | /* MIPS 32 */ | |
d16afab6 RS |
18611 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
18612 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
18613 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
18614 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
18615 | |
18616 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
18617 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18618 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18619 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18620 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18621 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18622 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18623 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18624 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18625 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
18626 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18627 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
18628 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18629 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18630 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18631 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18632 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 18633 | /* Deprecated forms of the above. */ |
d16afab6 RS |
18634 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18635 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 18636 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
18637 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18638 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18639 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18640 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 18641 | /* Deprecated forms of the above. */ |
d16afab6 RS |
18642 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18643 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 18644 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
18645 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18646 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18647 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18648 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 18649 | /* Deprecated forms of the above. */ |
d16afab6 RS |
18650 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18651 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 18652 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 18653 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18654 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
18655 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18656 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18657 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18658 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18659 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 18660 | /* Deprecated forms of the above. */ |
d16afab6 RS |
18661 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18662 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 18663 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
18664 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18665 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18666 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18667 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
18668 | /* interaptiv is the new name for 1004kf */ |
18669 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
c6e5c03a RS |
18670 | /* M5100 family */ |
18671 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
18672 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 18673 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
ae52f483 | 18674 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 18675 | |
316f5878 | 18676 | /* MIPS 64 */ |
d16afab6 RS |
18677 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
18678 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
18679 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
18680 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 18681 | |
c7a23324 | 18682 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 18683 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 18684 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 18685 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 18686 | |
4ba154f5 | 18687 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 18688 | |
ed163775 MR |
18689 | /* MIPS 64 Release 2 */ |
18690 | ||
967344c6 | 18691 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
18692 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
18693 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
18694 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 18695 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 18696 | |
52b6b6b9 | 18697 | /* RMI Xlr */ |
d16afab6 | 18698 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 18699 | |
55a36193 MK |
18700 | /* Broadcom XLP. |
18701 | XLP is mostly like XLR, with the prominent exception that it is | |
18702 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 18703 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 18704 | |
7ef0d297 AB |
18705 | /* i6400. */ |
18706 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, | |
18707 | ||
316f5878 | 18708 | /* End marker */ |
d16afab6 | 18709 | { NULL, 0, 0, 0, 0 } |
316f5878 | 18710 | }; |
e7af610e | 18711 | |
84ea6cf2 | 18712 | |
316f5878 RS |
18713 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
18714 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 18715 | |
316f5878 | 18716 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 18717 | |
b34976b6 | 18718 | static bfd_boolean |
17a2f251 | 18719 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18720 | { |
18721 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
18722 | given++, canonical++; | |
18723 | ||
18724 | return ((*given == 0 && *canonical == 0) | |
18725 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
18726 | } | |
18727 | ||
18728 | ||
18729 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
18730 | CPU name. We've traditionally allowed a lot of variation here. | |
18731 | ||
18732 | Note: this function is shared between GCC and GAS. */ | |
18733 | ||
b34976b6 | 18734 | static bfd_boolean |
17a2f251 | 18735 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18736 | { |
18737 | /* First see if the name matches exactly, or with a final "000" | |
18738 | turned into "k". */ | |
18739 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 18740 | return TRUE; |
316f5878 RS |
18741 | |
18742 | /* If not, try comparing based on numerical designation alone. | |
18743 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
18744 | if (TOLOWER (*given) == 'r') | |
18745 | given++; | |
18746 | if (!ISDIGIT (*given)) | |
b34976b6 | 18747 | return FALSE; |
316f5878 RS |
18748 | |
18749 | /* Skip over some well-known prefixes in the canonical name, | |
18750 | hoping to find a number there too. */ | |
18751 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
18752 | canonical += 2; | |
18753 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
18754 | canonical += 2; | |
18755 | else if (TOLOWER (canonical[0]) == 'r') | |
18756 | canonical += 1; | |
18757 | ||
18758 | return mips_strict_matching_cpu_name_p (canonical, given); | |
18759 | } | |
18760 | ||
18761 | ||
18762 | /* Parse an option that takes the name of a processor as its argument. | |
18763 | OPTION is the name of the option and CPU_STRING is the argument. | |
18764 | Return the corresponding processor enumeration if the CPU_STRING is | |
18765 | recognized, otherwise report an error and return null. | |
18766 | ||
18767 | A similar function exists in GCC. */ | |
e7af610e NC |
18768 | |
18769 | static const struct mips_cpu_info * | |
17a2f251 | 18770 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 18771 | { |
316f5878 | 18772 | const struct mips_cpu_info *p; |
e7af610e | 18773 | |
316f5878 RS |
18774 | /* 'from-abi' selects the most compatible architecture for the given |
18775 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
18776 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
18777 | version. Look first at the -mgp options, if given, otherwise base | |
18778 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 18779 | |
316f5878 RS |
18780 | Treat NO_ABI like the EABIs. One reason to do this is that the |
18781 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
18782 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
18783 | 'mips64', just as we did in the days before 'from-abi'. */ | |
18784 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
18785 | { | |
18786 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18787 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
18788 | ||
18789 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
18790 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
18791 | ||
bad1aba3 | 18792 | if (file_mips_opts.gp >= 0) |
18793 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 18794 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
18795 | |
18796 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
18797 | ? ISA_MIPS3 | |
18798 | : ISA_MIPS1); | |
18799 | } | |
18800 | ||
18801 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
18802 | if (strcasecmp (cpu_string, "default") == 0) | |
18803 | return 0; | |
18804 | ||
18805 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
18806 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
18807 | return p; | |
18808 | ||
1661c76c | 18809 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 18810 | return 0; |
e7af610e NC |
18811 | } |
18812 | ||
316f5878 RS |
18813 | /* Return the canonical processor information for ISA (a member of the |
18814 | ISA_MIPS* enumeration). */ | |
18815 | ||
e7af610e | 18816 | static const struct mips_cpu_info * |
17a2f251 | 18817 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
18818 | { |
18819 | int i; | |
18820 | ||
18821 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 18822 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 18823 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
18824 | return (&mips_cpu_info_table[i]); |
18825 | ||
e972090a | 18826 | return NULL; |
e7af610e | 18827 | } |
fef14a42 TS |
18828 | |
18829 | static const struct mips_cpu_info * | |
17a2f251 | 18830 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
18831 | { |
18832 | int i; | |
18833 | ||
18834 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
18835 | if (arch == mips_cpu_info_table[i].cpu) | |
18836 | return (&mips_cpu_info_table[i]); | |
18837 | ||
18838 | return NULL; | |
18839 | } | |
316f5878 RS |
18840 | \f |
18841 | static void | |
17a2f251 | 18842 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
18843 | { |
18844 | if (*first_p) | |
18845 | { | |
18846 | fprintf (stream, "%24s", ""); | |
18847 | *col_p = 24; | |
18848 | } | |
18849 | else | |
18850 | { | |
18851 | fprintf (stream, ", "); | |
18852 | *col_p += 2; | |
18853 | } | |
e7af610e | 18854 | |
316f5878 RS |
18855 | if (*col_p + strlen (string) > 72) |
18856 | { | |
18857 | fprintf (stream, "\n%24s", ""); | |
18858 | *col_p = 24; | |
18859 | } | |
18860 | ||
18861 | fprintf (stream, "%s", string); | |
18862 | *col_p += strlen (string); | |
18863 | ||
18864 | *first_p = 0; | |
18865 | } | |
18866 | ||
18867 | void | |
17a2f251 | 18868 | md_show_usage (FILE *stream) |
e7af610e | 18869 | { |
316f5878 RS |
18870 | int column, first; |
18871 | size_t i; | |
18872 | ||
18873 | fprintf (stream, _("\ | |
18874 | MIPS options:\n\ | |
316f5878 RS |
18875 | -EB generate big endian output\n\ |
18876 | -EL generate little endian output\n\ | |
18877 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
18878 | -G NUM allow referencing objects up to NUM bytes\n\ | |
18879 | implicitly with the gp register [default 8]\n")); | |
18880 | fprintf (stream, _("\ | |
18881 | -mips1 generate MIPS ISA I instructions\n\ | |
18882 | -mips2 generate MIPS ISA II instructions\n\ | |
18883 | -mips3 generate MIPS ISA III instructions\n\ | |
18884 | -mips4 generate MIPS ISA IV instructions\n\ | |
18885 | -mips5 generate MIPS ISA V instructions\n\ | |
18886 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 18887 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
18888 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
18889 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 18890 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 18891 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 18892 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
18893 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
18894 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 18895 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
18896 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
18897 | ||
18898 | first = 1; | |
e7af610e NC |
18899 | |
18900 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
18901 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
18902 | show (stream, "from-abi", &column, &first); | |
18903 | fputc ('\n', stream); | |
e7af610e | 18904 | |
316f5878 RS |
18905 | fprintf (stream, _("\ |
18906 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
18907 | -no-mCPU don't generate code specific to CPU.\n\ | |
18908 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
18909 | ||
18910 | first = 1; | |
18911 | ||
18912 | show (stream, "3900", &column, &first); | |
18913 | show (stream, "4010", &column, &first); | |
18914 | show (stream, "4100", &column, &first); | |
18915 | show (stream, "4650", &column, &first); | |
18916 | fputc ('\n', stream); | |
18917 | ||
18918 | fprintf (stream, _("\ | |
18919 | -mips16 generate mips16 instructions\n\ | |
18920 | -no-mips16 do not generate mips16 instructions\n")); | |
18921 | fprintf (stream, _("\ | |
df58fc94 RS |
18922 | -mmicromips generate microMIPS instructions\n\ |
18923 | -mno-micromips do not generate microMIPS instructions\n")); | |
18924 | fprintf (stream, _("\ | |
e16bfa71 | 18925 | -msmartmips generate smartmips instructions\n\ |
3739860c | 18926 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 18927 | fprintf (stream, _("\ |
74cd071d CF |
18928 | -mdsp generate DSP instructions\n\ |
18929 | -mno-dsp do not generate DSP instructions\n")); | |
18930 | fprintf (stream, _("\ | |
8b082fb1 TS |
18931 | -mdspr2 generate DSP R2 instructions\n\ |
18932 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
18933 | fprintf (stream, _("\ | |
ef2e4d86 CF |
18934 | -mmt generate MT instructions\n\ |
18935 | -mno-mt do not generate MT instructions\n")); | |
18936 | fprintf (stream, _("\ | |
dec0624d MR |
18937 | -mmcu generate MCU instructions\n\ |
18938 | -mno-mcu do not generate MCU instructions\n")); | |
18939 | fprintf (stream, _("\ | |
56d438b1 CF |
18940 | -mmsa generate MSA instructions\n\ |
18941 | -mno-msa do not generate MSA instructions\n")); | |
18942 | fprintf (stream, _("\ | |
7d64c587 AB |
18943 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
18944 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
18945 | fprintf (stream, _("\ | |
b015e599 AP |
18946 | -mvirt generate Virtualization instructions\n\ |
18947 | -mno-virt do not generate Virtualization instructions\n")); | |
18948 | fprintf (stream, _("\ | |
833794fc MR |
18949 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
18950 | -mno-insn32 generate all microMIPS instructions\n")); | |
18951 | fprintf (stream, _("\ | |
c67a084a NC |
18952 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
18953 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 18954 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 18955 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 18956 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 18957 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
18958 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
18959 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 18960 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
18961 | -O0 remove unneeded NOPs, do not swap branches\n\ |
18962 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
18963 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
18964 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
18965 | fprintf (stream, _("\ |
18966 | -mhard-float allow floating-point instructions\n\ | |
18967 | -msoft-float do not allow floating-point instructions\n\ | |
18968 | -msingle-float only allow 32-bit floating-point operations\n\ | |
18969 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 18970 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 MR |
18971 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
18972 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); | |
18973 | ||
18974 | first = 1; | |
18975 | ||
18976 | show (stream, "legacy", &column, &first); | |
18977 | show (stream, "2008", &column, &first); | |
18978 | ||
18979 | fputc ('\n', stream); | |
18980 | ||
316f5878 RS |
18981 | fprintf (stream, _("\ |
18982 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 18983 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 18984 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 18985 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 18986 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 18987 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 18988 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 18989 | position dependent (non shared) code\n\ |
316f5878 RS |
18990 | -mabi=ABI create ABI conformant object file for:\n")); |
18991 | ||
18992 | first = 1; | |
18993 | ||
18994 | show (stream, "32", &column, &first); | |
18995 | show (stream, "o64", &column, &first); | |
18996 | show (stream, "n32", &column, &first); | |
18997 | show (stream, "64", &column, &first); | |
18998 | show (stream, "eabi", &column, &first); | |
18999 | ||
19000 | fputc ('\n', stream); | |
19001 | ||
19002 | fprintf (stream, _("\ | |
19003 | -32 create o32 ABI object file (default)\n\ | |
19004 | -n32 create n32 ABI object file\n\ | |
19005 | -64 create 64 ABI object file\n")); | |
e7af610e | 19006 | } |
14e777e0 | 19007 | |
1575952e | 19008 | #ifdef TE_IRIX |
14e777e0 | 19009 | enum dwarf2_format |
413a266c | 19010 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19011 | { |
369943fe | 19012 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19013 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19014 | else |
19015 | return dwarf2_format_32bit; | |
19016 | } | |
1575952e | 19017 | #endif |
73369e65 EC |
19018 | |
19019 | int | |
19020 | mips_dwarf2_addr_size (void) | |
19021 | { | |
6b6b3450 | 19022 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19023 | return 8; |
73369e65 EC |
19024 | else |
19025 | return 4; | |
19026 | } | |
5862107c EC |
19027 | |
19028 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19029 | void | |
19030 | mips_cfi_frame_initial_instructions (void) | |
19031 | { | |
19032 | cfi_add_CFA_def_cfa_register (SP); | |
19033 | } | |
19034 | ||
707bfff6 TS |
19035 | int |
19036 | tc_mips_regname_to_dw2regnum (char *regname) | |
19037 | { | |
19038 | unsigned int regnum = -1; | |
19039 | unsigned int reg; | |
19040 | ||
19041 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19042 | regnum = reg; | |
19043 | ||
19044 | return regnum; | |
19045 | } | |
263b2574 | 19046 | |
19047 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
19048 | Given a symbolic attribute NAME, return the proper integer value. | |
19049 | Returns -1 if the attribute is not known. */ | |
19050 | ||
19051 | int | |
19052 | mips_convert_symbolic_attribute (const char *name) | |
19053 | { | |
19054 | static const struct | |
19055 | { | |
19056 | const char * name; | |
19057 | const int tag; | |
19058 | } | |
19059 | attribute_table[] = | |
19060 | { | |
19061 | #define T(tag) {#tag, tag} | |
19062 | T (Tag_GNU_MIPS_ABI_FP), | |
19063 | T (Tag_GNU_MIPS_ABI_MSA), | |
19064 | #undef T | |
19065 | }; | |
19066 | unsigned int i; | |
19067 | ||
19068 | if (name == NULL) | |
19069 | return -1; | |
19070 | ||
19071 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
19072 | if (streq (name, attribute_table[i].name)) | |
19073 | return attribute_table[i].tag; | |
19074 | ||
19075 | return -1; | |
19076 | } | |
fd5c94ab RS |
19077 | |
19078 | void | |
19079 | md_mips_end (void) | |
19080 | { | |
351cdf24 MF |
19081 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
19082 | ||
fd5c94ab RS |
19083 | mips_emit_delays (); |
19084 | if (cur_proc_ptr) | |
19085 | as_warn (_("missing .end at end of assembly")); | |
919731af | 19086 | |
19087 | /* Just in case no code was emitted, do the consistency check. */ | |
19088 | file_mips_check_options (); | |
351cdf24 MF |
19089 | |
19090 | /* Set a floating-point ABI if the user did not. */ | |
19091 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
19092 | { | |
19093 | /* Perform consistency checks on the floating-point ABI. */ | |
19094 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19095 | Tag_GNU_MIPS_ABI_FP); | |
19096 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
19097 | check_fpabi (fpabi); | |
19098 | } | |
19099 | else | |
19100 | { | |
19101 | /* Soft-float gets precedence over single-float, the two options should | |
19102 | not be used together so this should not matter. */ | |
19103 | if (file_mips_opts.soft_float == 1) | |
19104 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
19105 | /* Single-float gets precedence over all double_float cases. */ | |
19106 | else if (file_mips_opts.single_float == 1) | |
19107 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
19108 | else | |
19109 | { | |
19110 | switch (file_mips_opts.fp) | |
19111 | { | |
19112 | case 32: | |
19113 | if (file_mips_opts.gp == 32) | |
19114 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
19115 | break; | |
19116 | case 0: | |
19117 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
19118 | break; | |
19119 | case 64: | |
19120 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
19121 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
19122 | else if (file_mips_opts.gp == 32) | |
19123 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
19124 | else | |
19125 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
19126 | break; | |
19127 | } | |
19128 | } | |
19129 | ||
19130 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19131 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
19132 | } | |
fd5c94ab | 19133 | } |
2f0c68f2 CM |
19134 | |
19135 | /* Returns the relocation type required for a particular CFI encoding. */ | |
19136 | ||
19137 | bfd_reloc_code_real_type | |
19138 | mips_cfi_reloc_for_encoding (int encoding) | |
19139 | { | |
19140 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
19141 | return BFD_RELOC_32_PCREL; | |
19142 | else return BFD_RELOC_NONE; | |
19143 | } |