]>
Commit | Line | Data |
---|---|---|
3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
145 | struct mips_set_options | |
146 | { | |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
151 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
152 | not, 1 if we are, and -1 if the value has not been initialized. | |
153 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
154 | -nomips16 command line options, and the default CPU. */ | |
155 | int mips16; | |
156 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
157 | reorder' and `.set noreorder'. */ | |
158 | int noreorder; | |
159 | /* Non-zero if we should not permit the $at ($1) register to be used | |
160 | in instructions. Changed by `.set at' and `.set noat'. */ | |
161 | int noat; | |
162 | /* Non-zero if we should warn when a macro instruction expands into | |
163 | more than one machine instruction. Changed by `.set nomacro' and | |
164 | `.set macro'. */ | |
165 | int warn_about_macros; | |
166 | /* Non-zero if we should not move instructions. Changed by `.set | |
167 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
168 | int nomove; | |
169 | /* Non-zero if we should not optimize branches by moving the target | |
170 | of the branch into the delay slot. Actually, we don't perform | |
171 | this optimization anyhow. Changed by `.set bopt' and `.set | |
172 | nobopt'. */ | |
173 | int nobopt; | |
174 | /* Non-zero if we should not autoextend mips16 instructions. | |
175 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
176 | int noautoextend; | |
177 | }; | |
178 | ||
179 | /* This is the struct we use to hold the current set of options. Note | |
180 | that we must set the isa and mips16 fields to -1 to indicate that | |
181 | they have not been initialized. */ | |
182 | ||
183 | static struct mips_set_options mips_opts = { -1, -1 }; | |
184 | ||
1aa6938e ILT |
185 | /* These variables are filled in with the masks of registers used. |
186 | The object format code reads them and puts them in the appropriate | |
187 | place. */ | |
188 | unsigned long mips_gprmask; | |
189 | unsigned long mips_cprmask[4]; | |
190 | ||
1051c97f ILT |
191 | /* MIPS ISA we are using for this output file. */ |
192 | static int file_mips_isa; | |
193 | ||
8c63448a | 194 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 195 | static int mips_cpu = -1; |
8c63448a | 196 | |
b2b8c24e ILT |
197 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
198 | static int mips_4650 = -1; | |
199 | ||
e532b44c ILT |
200 | /* Whether the 4010 instructions are permitted. */ |
201 | static int mips_4010 = -1; | |
202 | ||
c625fc23 JSC |
203 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
204 | static int mips_4100 = -1; | |
205 | ||
2d035a50 GRK |
206 | /* start-sanitize-vr4320 */ |
207 | /* Whether NEC vr4320 instructions are permitted. */ | |
208 | static int mips_4320 = -1; | |
209 | ||
210 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
211 | /* start-sanitize-vr5400 */ |
212 | /* Whether NEC vr5400 instructions are permitted. */ | |
213 | static int mips_5400 = -1; | |
214 | ||
215 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
216 | /* start-sanitize-r5900 */ |
217 | /* Whether Toshiba r5900 instructions are permitted. */ | |
218 | static int mips_5900 = -1; | |
276c2d7d | 219 | |
aa2e0460 | 220 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
221 | /* Whether Toshiba r3900 instructions are permitted. */ |
222 | static int mips_3900 = -1; | |
223 | ||
42444087 GRK |
224 | /* start-sanitize-tx49 */ |
225 | /* Whether Toshiba r4900 instructions are permitted. */ | |
226 | static int mips_4900 = -1; | |
227 | ||
228 | /* end-sanitize-tx49 */ | |
4e96260f JL |
229 | /* start-sanitize-tx19 */ |
230 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
231 | The tx19 related options and configuration bits are handled by | |
232 | the tx39 flags. */ | |
233 | /* end-sanitize-tx19 */ | |
234 | ||
5c6f5923 GRK |
235 | /* Whether the processor uses hardware interlocks to protect |
236 | reads from the HI and LO registers, and thus does not | |
237 | require nops to be inserted. */ | |
2cf51495 | 238 | #define hilo_interlocks (mips_4010 || mips_3900 \ |
4ebda395 | 239 | /* start-sanitize-tx49 */ \ |
42444087 | 240 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 241 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
242 | /* start-sanitize-vr4320 */ \ |
243 | || mips_cpu == 4320 \ | |
244 | /* end-sanitize-vr4320 */ \ | |
4ebda395 | 245 | ) |
5c6f5923 | 246 | |
a3e8c5b7 ILT |
247 | /* Whether the processor uses hardware interlocks to protect reads |
248 | from the GPRs, and thus does not require nops to be inserted. */ | |
249 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
1c6f3441 ILT |
250 | /* start-sanitize-vr5400 */ |
251 | #undef gpr_interlocks | |
252 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
253 | /* end-sanitize-vr5400 */ | |
254 | ||
e532b44c | 255 | |
5c6f5923 | 256 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 257 | (co-processor) interlocks. */ |
efec4a28 | 258 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
259 | #define cop_interlocks (mips_cpu == 4300 \ |
260 | /* start-sanitize-vr4320 */ \ | |
261 | || mips_cpu == 4320 \ | |
262 | /* end-sanitize-vr4320 */ \ | |
263 | /* start-sanitize-vr5400 */ \ | |
264 | || mips_cpu == 5400 \ | |
265 | /* end-sanitize-vr5400 */ \ | |
266 | ) | |
344a8d61 | 267 | |
d9aba805 ILT |
268 | /* MIPS PIC level. */ |
269 | ||
270 | enum mips_pic_level | |
271 | { | |
272 | /* Do not generate PIC code. */ | |
273 | NO_PIC, | |
274 | ||
275 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
276 | not sure what it is supposed to do. */ | |
277 | IRIX4_PIC, | |
278 | ||
279 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
280 | SVR4_PIC, | |
281 | ||
282 | /* Generate PIC code without using a global offset table: the data | |
283 | segment has a maximum size of 64K, all data references are off | |
284 | the $gp register, and all text references are PC relative. This | |
285 | is used on some embedded systems. */ | |
286 | EMBEDDED_PIC | |
287 | }; | |
288 | ||
289 | static enum mips_pic_level mips_pic; | |
9226253a | 290 | |
fb251650 ILT |
291 | /* 1 if we should generate 32 bit offsets from the GP register in |
292 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
293 | static int mips_big_got; | |
294 | ||
8ea7f4e8 ILT |
295 | /* 1 if trap instructions should used for overflow rather than break |
296 | instructions. */ | |
297 | static int mips_trap; | |
298 | ||
3c83da8a | 299 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 300 | |
0dd2d296 | 301 | static int mips_any_noreorder; |
3d3c5039 | 302 | |
670a50eb ILT |
303 | /* The size of the small data section. */ |
304 | static int g_switch_value = 8; | |
42562568 ILT |
305 | /* Whether the -G option was used. */ |
306 | static int g_switch_seen = 0; | |
670a50eb | 307 | |
3d3c5039 ILT |
308 | #define N_RMASK 0xc4 |
309 | #define N_VFP 0xd4 | |
310 | ||
d8a1c247 KR |
311 | /* If we can determine in advance that GP optimization won't be |
312 | possible, we can skip the relaxation stuff that tries to produce | |
313 | GP-relative references. This makes delay slot optimization work | |
314 | better. | |
315 | ||
316 | This function can only provide a guess, but it seems to work for | |
317 | gcc output. If it guesses wrong, the only loss should be in | |
318 | efficiency; it shouldn't introduce any bugs. | |
319 | ||
320 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
321 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 322 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 323 | |
3d3c5039 ILT |
324 | /* handle of the OPCODE hash table */ |
325 | static struct hash_control *op_hash = NULL; | |
326 | ||
cc5703cd ILT |
327 | /* The opcode hash table we use for the mips16. */ |
328 | static struct hash_control *mips16_op_hash = NULL; | |
329 | ||
3d3c5039 ILT |
330 | /* This array holds the chars that always start a comment. If the |
331 | pre-processor is disabled, these aren't very useful */ | |
332 | const char comment_chars[] = "#"; | |
333 | ||
334 | /* This array holds the chars that only start a comment at the beginning of | |
335 | a line. If the line seems to have the form '# 123 filename' | |
336 | .line and .file directives will appear in the pre-processed output */ | |
337 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
338 | first line of the input file. This is because the compiler outputs | |
339 | #NO_APP at the beginning of its output. */ | |
340 | /* Also note that C style comments are always supported. */ | |
341 | const char line_comment_chars[] = "#"; | |
342 | ||
343 | /* This array holds machine specific line separator characters. */ | |
344 | const char line_separator_chars[] = ""; | |
345 | ||
346 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
347 | const char EXP_CHARS[] = "eE"; | |
348 | ||
349 | /* Chars that mean this number is a floating point constant */ | |
350 | /* As in 0f12.456 */ | |
351 | /* or 0d1.2345e12 */ | |
352 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
353 | ||
354 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
355 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
356 | but nothing is ideal around here. | |
357 | */ | |
358 | ||
670a50eb | 359 | static char *insn_error; |
3d3c5039 | 360 | |
3d3c5039 | 361 | static int auto_align = 1; |
becfe05e | 362 | |
9226253a ILT |
363 | /* When outputting SVR4 PIC code, the assembler needs to know the |
364 | offset in the stack frame from which to restore the $gp register. | |
365 | This is set by the .cprestore pseudo-op, and saved in this | |
366 | variable. */ | |
0dd2d296 ILT |
367 | static offsetT mips_cprestore_offset = -1; |
368 | ||
369 | /* This is the register which holds the stack frame, as set by the | |
370 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
371 | static int mips_frame_reg = SP; | |
9226253a | 372 | |
becfe05e ILT |
373 | /* To output NOP instructions correctly, we need to keep information |
374 | about the previous two instructions. */ | |
375 | ||
0aa07269 ILT |
376 | /* Whether we are optimizing. The default value of 2 means to remove |
377 | unneeded NOPs and swap branch instructions when possible. A value | |
378 | of 1 means to not swap branches. A value of 0 means to always | |
379 | insert NOPs. */ | |
380 | static int mips_optimize = 2; | |
4e95866e | 381 | |
22ba90ce ILT |
382 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
383 | equivalent to seeing no -g option at all. */ | |
384 | static int mips_debug = 0; | |
385 | ||
becfe05e ILT |
386 | /* The previous instruction. */ |
387 | static struct mips_cl_insn prev_insn; | |
388 | ||
389 | /* The instruction before prev_insn. */ | |
390 | static struct mips_cl_insn prev_prev_insn; | |
391 | ||
392 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
393 | point the insn_mo field at this dummy integer. */ | |
394 | static const struct mips_opcode dummy_opcode = { 0 }; | |
395 | ||
396 | /* Non-zero if prev_insn is valid. */ | |
397 | static int prev_insn_valid; | |
398 | ||
399 | /* The frag for the previous instruction. */ | |
400 | static struct frag *prev_insn_frag; | |
401 | ||
402 | /* The offset into prev_insn_frag for the previous instruction. */ | |
403 | static long prev_insn_where; | |
404 | ||
a677feeb ILT |
405 | /* The reloc type for the previous instruction, if any. */ |
406 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
407 | ||
becfe05e ILT |
408 | /* The reloc for the previous instruction, if any. */ |
409 | static fixS *prev_insn_fixp; | |
410 | ||
411 | /* Non-zero if the previous instruction was in a delay slot. */ | |
412 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
413 | |
414 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
415 | static int prev_insn_unreordered; | |
416 | ||
cc5703cd ILT |
417 | /* Non-zero if the previous instruction uses an extend opcode (if |
418 | mips16). */ | |
419 | static int prev_insn_extended; | |
420 | ||
4e95866e ILT |
421 | /* Non-zero if the previous previous instruction was in a .set |
422 | noreorder. */ | |
423 | static int prev_prev_insn_unreordered; | |
867a58b3 | 424 | |
4a1cb507 ILT |
425 | /* If this is set, it points to a frag holding nop instructions which |
426 | were inserted before the start of a noreorder section. If those | |
427 | nops turn out to be unnecessary, the size of the frag can be | |
428 | decreased. */ | |
429 | static fragS *prev_nop_frag; | |
430 | ||
431 | /* The number of nop instructions we created in prev_nop_frag. */ | |
432 | static int prev_nop_frag_holds; | |
433 | ||
434 | /* The number of nop instructions that we know we need in | |
435 | prev_nop_frag. */ | |
436 | static int prev_nop_frag_required; | |
437 | ||
438 | /* The number of instructions we've seen since prev_nop_frag. */ | |
439 | static int prev_nop_frag_since; | |
440 | ||
867a58b3 ILT |
441 | /* For ECOFF and ELF, relocations against symbols are done in two |
442 | parts, with a HI relocation and a LO relocation. Each relocation | |
443 | has only 16 bits of space to store an addend. This means that in | |
444 | order for the linker to handle carries correctly, it must be able | |
445 | to locate both the HI and the LO relocation. This means that the | |
446 | relocations must appear in order in the relocation table. | |
447 | ||
448 | In order to implement this, we keep track of each unmatched HI | |
449 | relocation. We then sort them so that they immediately precede the | |
450 | corresponding LO relocation. */ | |
451 | ||
452 | struct mips_hi_fixup | |
453 | { | |
454 | /* Next HI fixup. */ | |
455 | struct mips_hi_fixup *next; | |
456 | /* This fixup. */ | |
457 | fixS *fixp; | |
458 | /* The section this fixup is in. */ | |
459 | segT seg; | |
460 | }; | |
461 | ||
462 | /* The list of unmatched HI relocs. */ | |
463 | ||
464 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
465 | |
466 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
467 | ||
468 | #define X ILLEGAL_REG | |
469 | static const int mips32_to_16_reg_map[] = | |
470 | { | |
471 | X, X, 2, 3, 4, 5, 6, 7, | |
472 | X, X, X, X, X, X, X, X, | |
473 | 0, 1, X, X, X, X, X, X, | |
474 | X, X, X, X, X, X, X, X | |
475 | }; | |
476 | #undef X | |
477 | ||
478 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
479 | ||
480 | static const int mips16_to_32_reg_map[] = | |
481 | { | |
482 | 16, 17, 2, 3, 4, 5, 6, 7 | |
483 | }; | |
3d3c5039 | 484 | \f |
0dd2d296 ILT |
485 | /* Since the MIPS does not have multiple forms of PC relative |
486 | instructions, we do not have to do relaxing as is done on other | |
487 | platforms. However, we do have to handle GP relative addressing | |
488 | correctly, which turns out to be a similar problem. | |
489 | ||
490 | Every macro that refers to a symbol can occur in (at least) two | |
491 | forms, one with GP relative addressing and one without. For | |
492 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 493 | a macro instruction like this: |
0dd2d296 ILT |
494 | lw $4,i |
495 | If i can be addressed off the GP register (this is true if it is in | |
496 | the .sbss or .sdata section, or if it is known to be smaller than | |
497 | the -G argument) this will generate the following instruction: | |
498 | lw $4,i($gp) | |
499 | This instruction will use a GPREL reloc. If i can not be addressed | |
500 | off the GP register, the following instruction sequence will be used: | |
501 | lui $at,i | |
502 | lw $4,i($at) | |
503 | In this case the first instruction will have a HI16 reloc, and the | |
504 | second reloc will have a LO16 reloc. Both relocs will be against | |
505 | the symbol i. | |
506 | ||
507 | The issue here is that we may not know whether i is GP addressable | |
508 | until after we see the instruction that uses it. Therefore, we | |
509 | want to be able to choose the final instruction sequence only at | |
510 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 511 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
512 | end of assembly. |
513 | ||
514 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
515 | addressing in quite the same way, but the issue still arises as |
516 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
517 | |
518 | We handle these issues by actually generating both possible | |
519 | instruction sequences. The longer one is put in a frag_var with | |
520 | type rs_machine_dependent. We encode what to do with the frag in | |
521 | the subtype field. We encode (1) the number of existing bytes to | |
522 | replace, (2) the number of new bytes to use, (3) the offset from | |
523 | the start of the existing bytes to the first reloc we must generate | |
524 | (that is, the offset is applied from the start of the existing | |
525 | bytes after they are replaced by the new bytes, if any), (4) the | |
526 | offset from the start of the existing bytes to the second reloc, | |
527 | (5) whether a third reloc is needed (the third reloc is always four | |
528 | bytes after the second reloc), and (6) whether to warn if this | |
529 | variant is used (this is sometimes needed if .set nomacro or .set | |
530 | noat is in effect). All these numbers are reasonably small. | |
531 | ||
532 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
533 | ensure that delay slots are handled correctly. Fortunately, there |
534 | are a limited number of cases. When the second instruction | |
535 | sequence is generated, append_insn is directed to maintain the | |
536 | existing delay slot information, so it continues to apply to any | |
537 | code after the second instruction sequence. This means that the | |
538 | second instruction sequence must not impose any requirements not | |
539 | required by the first instruction sequence. | |
0dd2d296 ILT |
540 | |
541 | These variant frags are then handled in functions called by the | |
542 | machine independent code. md_estimate_size_before_relax returns | |
543 | the final size of the frag. md_convert_frag sets up the final form | |
544 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
545 | one if needed. */ | |
546 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
547 | ((relax_substateT) \ | |
cc5703cd | 548 | (((old) << 23) \ |
0dd2d296 ILT |
549 | | ((new) << 16) \ |
550 | | (((reloc1) + 64) << 9) \ | |
551 | | (((reloc2) + 64) << 2) \ | |
552 | | ((reloc3) ? (1 << 1) : 0) \ | |
553 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
554 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
555 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
556 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
557 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
558 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
559 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
560 | |
561 | /* For mips16 code, we use an entirely different form of relaxation. | |
562 | mips16 supports two versions of most instructions which take | |
563 | immediate values: a small one which takes some small value, and a | |
564 | larger one which takes a 16 bit value. Since branches also follow | |
565 | this pattern, relaxing these values is required. | |
566 | ||
567 | We can assemble both mips16 and normal MIPS code in a single | |
568 | object. Therefore, we need to support this type of relaxation at | |
569 | the same time that we support the relaxation described above. We | |
570 | use the high bit of the subtype field to distinguish these cases. | |
571 | ||
a677feeb ILT |
572 | The information we store for this type of relaxation is the |
573 | argument code found in the opcode file for this relocation, whether | |
574 | the user explicitly requested a small or extended form, and whether | |
575 | the relocation is in a jump or jal delay slot. That tells us the | |
576 | size of the value, and how it should be stored. We also store | |
577 | whether the fragment is considered to be extended or not. We also | |
578 | store whether this is known to be a branch to a different section, | |
579 | whether we have tried to relax this frag yet, and whether we have | |
580 | ever extended a PC relative fragment because of a shift count. */ | |
581 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
582 | (0x80000000 \ | |
583 | | ((type) & 0xff) \ | |
584 | | ((small) ? 0x100 : 0) \ | |
585 | | ((ext) ? 0x200 : 0) \ | |
586 | | ((dslot) ? 0x400 : 0) \ | |
587 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
588 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
589 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
590 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
591 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
592 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
593 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
594 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
595 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
596 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
597 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
598 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
599 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 600 | \f |
3d3c5039 ILT |
601 | /* Prototypes for static functions. */ |
602 | ||
603 | #ifdef __STDC__ | |
604 | #define internalError() \ | |
48401fcf | 605 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
3d3c5039 | 606 | #else |
48401fcf | 607 | #define internalError() as_fatal (_("MIPS internal Error")); |
3d3c5039 ILT |
608 | #endif |
609 | ||
cc5703cd ILT |
610 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
611 | ||
becfe05e | 612 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 613 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 614 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 615 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
616 | static void append_insn PARAMS ((char *place, |
617 | struct mips_cl_insn * ip, | |
670a50eb | 618 | expressionS * p, |
867a58b3 ILT |
619 | bfd_reloc_code_real_type r, |
620 | boolean)); | |
4a1cb507 | 621 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 622 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 623 | #ifdef USE_STDARG |
0dd2d296 | 624 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
625 | const char *name, const char *fmt, |
626 | ...)); | |
c625fc23 JSC |
627 | #else |
628 | static void macro_build (); | |
629 | #endif | |
cc5703cd ILT |
630 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
631 | const char *, const char *, | |
632 | va_list)); | |
0dd2d296 ILT |
633 | static void macro_build_lui PARAMS ((char *place, int *counter, |
634 | expressionS * ep, int regnum)); | |
6e8dda9c | 635 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 636 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 637 | expressionS *)); |
d8a1c247 | 638 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 639 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 640 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 641 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
642 | #ifdef LOSING_COMPILER |
643 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
644 | #endif | |
670a50eb | 645 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 646 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
647 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
648 | boolean, boolean, unsigned long *, | |
649 | boolean *, unsigned short *)); | |
670a50eb ILT |
650 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
651 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 652 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 653 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
654 | static void s_align PARAMS ((int)); |
655 | static void s_change_sec PARAMS ((int)); | |
656 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 657 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 658 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
659 | static void s_option PARAMS ((int)); |
660 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
661 | static void s_abicalls PARAMS ((int)); |
662 | static void s_cpload PARAMS ((int)); | |
663 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
664 | static void s_gpword PARAMS ((int)); |
665 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 666 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
667 | static void md_obj_begin PARAMS ((void)); |
668 | static void md_obj_end PARAMS ((void)); | |
669 | static long get_number PARAMS ((void)); | |
670 | static void s_ent PARAMS ((int)); | |
671 | static void s_mipsend PARAMS ((int)); | |
672 | static void s_file PARAMS ((int)); | |
3c83da8a | 673 | static void s_mips_stab PARAMS ((int)); |
3c69baf9 | 674 | static void s_mips_weakext PARAMS ((int)); |
cc5703cd | 675 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 | 676 | |
3c69baf9 | 677 | |
aa2e0460 | 678 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
3d3c5039 ILT |
679 | \f |
680 | /* Pseudo-op table. | |
681 | ||
682 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
683 | should be defined here, but are currently unsupported: .alias, | |
684 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
685 | ||
686 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
687 | specific to the type of debugging information being generated, and | |
688 | should be defined by the object format: .aent, .begin, .bend, | |
689 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
690 | .vreg. | |
691 | ||
692 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
693 | not MIPS CPU specific, but are also not specific to the object file | |
694 | format. This file is probably the best place to define them, but | |
695 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
3c69baf9 | 696 | .struct. */ |
3d3c5039 | 697 | |
739708fa | 698 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 699 | { |
670a50eb ILT |
700 | /* MIPS specific pseudo-ops. */ |
701 | {"option", s_option, 0}, | |
702 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
703 | {"rdata", s_change_sec, 'r'}, |
704 | {"sdata", s_change_sec, 's'}, | |
705 | {"livereg", s_ignore, 0}, | |
739708fa KR |
706 | {"abicalls", s_abicalls, 0}, |
707 | {"cpload", s_cpload, 0}, | |
708 | {"cprestore", s_cprestore, 0}, | |
709 | {"gpword", s_gpword, 0}, | |
710 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 711 | {"insn", s_insn, 0}, |
3d3c5039 | 712 | |
670a50eb | 713 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 714 | chips. */ |
739708fa | 715 | {"asciiz", stringer, 1}, |
670a50eb ILT |
716 | {"bss", s_change_sec, 'b'}, |
717 | {"err", s_err, 0}, | |
718 | {"half", s_cons, 1}, | |
52aa70b5 | 719 | {"dword", s_cons, 3}, |
3c69baf9 | 720 | {"weakext", s_mips_weakext, 0}, |
3d3c5039 | 721 | |
670a50eb | 722 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 723 | here for one reason or another. */ |
670a50eb ILT |
724 | {"align", s_align, 0}, |
725 | {"byte", s_cons, 0}, | |
726 | {"data", s_change_sec, 'd'}, | |
becfe05e | 727 | {"double", s_float_cons, 'd'}, |
becfe05e | 728 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
729 | {"globl", s_mips_globl, 0}, |
730 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
731 | {"hword", s_cons, 1}, |
732 | {"int", s_cons, 2}, | |
733 | {"long", s_cons, 2}, | |
734 | {"octa", s_cons, 4}, | |
735 | {"quad", s_cons, 3}, | |
736 | {"short", s_cons, 1}, | |
737 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 738 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
739 | {"text", s_change_sec, 't'}, |
740 | {"word", s_cons, 2}, | |
739708fa KR |
741 | { 0 }, |
742 | }; | |
3d3c5039 | 743 | |
739708fa | 744 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 745 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 746 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 747 | {"aent", s_ent, 1}, |
9226253a | 748 | {"bgnb", s_ignore, 0}, |
670a50eb | 749 | {"end", s_mipsend, 0}, |
9226253a | 750 | {"endb", s_ignore, 0}, |
670a50eb ILT |
751 | {"ent", s_ent, 0}, |
752 | {"file", s_file, 0}, | |
753 | {"fmask", s_ignore, 'F'}, | |
754 | {"frame", s_ignore, 0}, | |
755 | {"loc", s_ignore, 0}, | |
756 | {"mask", s_ignore, 'R'}, | |
757 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
758 | { 0 }, |
759 | }; | |
61420a20 | 760 | |
739708fa KR |
761 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
762 | ||
763 | void | |
764 | mips_pop_insert () | |
765 | { | |
766 | pop_insert (mips_pseudo_table); | |
767 | if (! ECOFF_DEBUGGING) | |
768 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 769 | } |
3d3c5039 | 770 | \f |
fbcfacb7 ILT |
771 | /* Symbols labelling the current insn. */ |
772 | ||
773 | struct insn_label_list | |
774 | { | |
775 | struct insn_label_list *next; | |
776 | symbolS *label; | |
777 | }; | |
778 | ||
779 | static struct insn_label_list *insn_labels; | |
780 | static struct insn_label_list *free_insn_labels; | |
781 | ||
782 | static void mips_clear_insn_labels PARAMS ((void)); | |
783 | ||
784 | static inline void | |
785 | mips_clear_insn_labels () | |
786 | { | |
787 | register struct insn_label_list **pl; | |
788 | ||
789 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
790 | ; | |
791 | *pl = insn_labels; | |
792 | insn_labels = NULL; | |
793 | } | |
794 | \f | |
3d3c5039 ILT |
795 | static char *expr_end; |
796 | ||
867a58b3 ILT |
797 | /* Expressions which appear in instructions. These are set by |
798 | mips_ip. */ | |
799 | ||
3d3c5039 ILT |
800 | static expressionS imm_expr; |
801 | static expressionS offset_expr; | |
867a58b3 ILT |
802 | |
803 | /* Relocs associated with imm_expr and offset_expr. */ | |
804 | ||
3d3c5039 ILT |
805 | static bfd_reloc_code_real_type imm_reloc; |
806 | static bfd_reloc_code_real_type offset_reloc; | |
807 | ||
867a58b3 ILT |
808 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
809 | ||
810 | static boolean imm_unmatched_hi; | |
811 | ||
8728fa92 ILT |
812 | /* These are set by mips16_ip if an explicit extension is used. */ |
813 | ||
814 | static boolean mips16_small, mips16_ext; | |
815 | ||
3d3c5039 ILT |
816 | /* |
817 | * This function is called once, at assembler startup time. It should | |
818 | * set up all the tables, etc. that the MD part of the assembler will need. | |
819 | */ | |
820 | void | |
670a50eb | 821 | md_begin () |
3d3c5039 | 822 | { |
0dd2d296 | 823 | boolean ok = false; |
604633ae | 824 | register const char *retval = NULL; |
670a50eb | 825 | register unsigned int i = 0; |
1724c79e GRK |
826 | const char *cpu; |
827 | char *a = NULL; | |
aa2e0460 | 828 | int broken = 0; |
3d3c5039 | 829 | |
1724c79e GRK |
830 | cpu = TARGET_CPU; |
831 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 832 | { |
1724c79e GRK |
833 | a = xmalloc (sizeof TARGET_CPU); |
834 | strcpy (a, TARGET_CPU); | |
835 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
836 | cpu = a; | |
837 | } | |
8c63448a | 838 | |
1724c79e GRK |
839 | if (mips_cpu < 0) |
840 | { | |
841 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
842 | just the generic 'mips', in which case set mips_cpu based | |
843 | on the given ISA, if any. */ | |
8c63448a ILT |
844 | |
845 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
846 | { |
847 | if (mips_opts.isa < 0) | |
848 | mips_cpu = 3000; | |
849 | ||
850 | else if (mips_opts.isa == 2) | |
851 | mips_cpu = 6000; | |
852 | ||
853 | else if (mips_opts.isa == 3) | |
854 | mips_cpu = 4000; | |
855 | ||
856 | else if (mips_opts.isa == 4) | |
857 | mips_cpu = 8000; | |
858 | ||
859 | else | |
860 | mips_cpu = 3000; | |
861 | } | |
862 | ||
5c6f5923 | 863 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 864 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
865 | /* start-sanitize-tx19 */ |
866 | || strcmp (cpu, "r1900") == 0 | |
867 | || strcmp (cpu, "mipstx19") == 0 | |
868 | /* end-sanitize-tx19 */ | |
869 | ) | |
1724c79e GRK |
870 | mips_cpu = 3900; |
871 | ||
8c63448a ILT |
872 | else if (strcmp (cpu, "r6000") == 0 |
873 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
874 | mips_cpu = 6000; |
875 | ||
8c63448a ILT |
876 | else if (strcmp (cpu, "mips64") == 0 |
877 | || strcmp (cpu, "r4000") == 0 | |
878 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
879 | mips_cpu = 4000; |
880 | ||
8c63448a | 881 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
882 | mips_cpu = 4400; |
883 | ||
8c63448a ILT |
884 | else if (strcmp (cpu, "mips64orion") == 0 |
885 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
886 | mips_cpu = 4600; |
887 | ||
b2b8c24e | 888 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
889 | mips_cpu = 4650; |
890 | ||
c625fc23 | 891 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
892 | mips_cpu = 4300; |
893 | ||
2d035a50 GRK |
894 | /* start-sanitize-vr4320 */ |
895 | else if (strcmp (cpu, "r4320") == 0 | |
896 | || strcmp (cpu, "mips64vr4320") == 0) | |
897 | mips_cpu = 4320; | |
898 | ||
899 | /* end-sanitize-vr4320 */ | |
e599ab16 | 900 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
901 | mips_cpu = 4100; |
902 | ||
e532b44c | 903 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
904 | mips_cpu = 4010; |
905 | ||
4ebda395 GRK |
906 | /* start-sanitize-tx49 */ |
907 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 908 | mips_cpu = 4900; |
4ebda395 | 909 | /* end-sanitize-tx49 */ |
1724c79e | 910 | |
517078c1 ILT |
911 | else if (strcmp (cpu, "r5000") == 0 |
912 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
913 | mips_cpu = 5000; |
914 | ||
aa2e0460 KR |
915 | /* start-sanitize-vr5400 */ |
916 | else if (strcmp (cpu, "r5400") == 0 | |
b3ed1af3 KR |
917 | || strcmp (cpu, "mips64vr5400") == 0) |
918 | mips_cpu = 5400; | |
aa2e0460 | 919 | /* end-sanitize-vr5400 */ |
1724c79e | 920 | |
276c2d7d GRK |
921 | /* start-sanitize-r5900 */ |
922 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
923 | || strcmp (cpu, "mips64r5900") == 0) |
924 | mips_cpu = 5900; | |
276c2d7d | 925 | /* end-sanitize-r5900 */ |
1724c79e | 926 | |
d8a1c247 KR |
927 | else if (strcmp (cpu, "r8000") == 0 |
928 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
929 | mips_cpu = 8000; |
930 | ||
d8a1c247 | 931 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
932 | mips_cpu = 10000; |
933 | ||
cc5703cd | 934 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
935 | mips_cpu = 0; /* FIXME */ |
936 | ||
8358c818 | 937 | else |
1724c79e GRK |
938 | mips_cpu = 3000; |
939 | } | |
8c63448a | 940 | |
1724c79e GRK |
941 | if (mips_opts.isa == -1) |
942 | { | |
943 | if (mips_cpu == 3000 | |
944 | || mips_cpu == 3900) | |
945 | mips_opts.isa = 1; | |
946 | ||
947 | else if (mips_cpu == 6000 | |
948 | || mips_cpu == 4010) | |
949 | mips_opts.isa = 2; | |
950 | ||
951 | else if (mips_cpu == 4000 | |
952 | || mips_cpu == 4100 | |
953 | || mips_cpu == 4400 | |
954 | || mips_cpu == 4300 | |
2d035a50 GRK |
955 | /* start-sanitize-vr4320 */ |
956 | || mips_cpu == 4320 | |
059a6388 | 957 | /* end-sanitize-vr4320 */ |
1724c79e GRK |
958 | || mips_cpu == 4600 |
959 | /* start-sanitize-tx49 */ | |
960 | || mips_cpu == 4900 | |
961 | /* end-sanitize-tx49 */ | |
962 | /* start-sanitize-r5900 */ | |
963 | || mips_cpu == 5900 | |
964 | /* end-sanitize-r5900 */ | |
965 | || mips_cpu == 4650) | |
966 | mips_opts.isa = 3; | |
967 | ||
968 | else if (mips_cpu == 5000 | |
969 | /* start-sanitize-vr5400 */ | |
970 | || mips_cpu == 5400 | |
971 | /* end-sanitize-vr5400 */ | |
972 | || mips_cpu == 8000 | |
973 | || mips_cpu == 10000) | |
974 | mips_opts.isa = 4; | |
975 | ||
976 | else | |
977 | mips_opts.isa = 1; | |
8358c818 ILT |
978 | } |
979 | ||
3c83da8a | 980 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
981 | { |
982 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 983 | mips_opts.mips16 = 1; |
cc5703cd | 984 | else |
3c83da8a | 985 | mips_opts.mips16 = 0; |
cc5703cd ILT |
986 | } |
987 | ||
b2b8c24e | 988 | if (mips_4650 < 0) |
1724c79e | 989 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 990 | |
e532b44c | 991 | if (mips_4010 < 0) |
1724c79e | 992 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 993 | |
c625fc23 | 994 | if (mips_4100 < 0) |
1724c79e | 995 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 996 | |
2d035a50 GRK |
997 | /* start-sanitize-vr4320 */ |
998 | if (mips_4320 < 0) | |
999 | mips_4320 = (mips_cpu == 4320); | |
1000 | ||
1001 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
1002 | /* start-sanitize-vr5400 */ |
1003 | if (mips_5400 < 0) | |
1724c79e | 1004 | mips_5400 = (mips_cpu == 5400); |
aa2e0460 | 1005 | /* end-sanitize-vr5400 */ |
1724c79e | 1006 | |
276c2d7d GRK |
1007 | /* start-sanitize-r5900 */ |
1008 | if (mips_5900 < 0) | |
1724c79e | 1009 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 1010 | /* end-sanitize-r5900 */ |
1724c79e | 1011 | |
5c6f5923 | 1012 | if (mips_3900 < 0) |
1724c79e GRK |
1013 | mips_3900 = (mips_cpu == 3900); |
1014 | ||
42444087 GRK |
1015 | /* start-sanitize-tx49 */ |
1016 | if (mips_4900 < 0) | |
1017 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 1018 | |
42444087 | 1019 | /* end-sanitize-tx49 */ |
1724c79e GRK |
1020 | |
1021 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1022 | if necessary. */ | |
1023 | cpu = NULL; | |
1024 | if (a != NULL) | |
1025 | { | |
1026 | free (a); | |
1027 | a = NULL; | |
1028 | } | |
1029 | ||
3c83da8a | 1030 | if (mips_opts.isa < 2 && mips_trap) |
48401fcf | 1031 | as_bad (_("trap exception not supported at ISA 1")); |
8ea7f4e8 | 1032 | |
9a1f3160 | 1033 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1034 | { |
9a1f3160 JL |
1035 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1036 | } | |
1037 | else | |
1038 | { | |
1039 | switch (mips_opts.isa) | |
1040 | { | |
1041 | case 1: | |
1042 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1043 | break; | |
1044 | case 2: | |
1045 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1046 | break; | |
1047 | case 3: | |
1048 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1049 | break; | |
1050 | case 4: | |
1051 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1052 | break; | |
1053 | } | |
97f99d11 | 1054 | } |
9a1f3160 | 1055 | |
97f99d11 | 1056 | if (! ok) |
48401fcf | 1057 | as_warn (_("Could not set architecture and machine")); |
97f99d11 | 1058 | |
3c83da8a | 1059 | file_mips_isa = mips_opts.isa; |
1051c97f | 1060 | |
13fe1379 ILT |
1061 | op_hash = hash_new (); |
1062 | ||
670a50eb ILT |
1063 | for (i = 0; i < NUMOPCODES;) |
1064 | { | |
1065 | const char *name = mips_opcodes[i].name; | |
1066 | ||
604633ae | 1067 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1068 | if (retval != NULL) |
670a50eb | 1069 | { |
48401fcf | 1070 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
670a50eb | 1071 | mips_opcodes[i].name, retval); |
aa2e0460 | 1072 | /* Probably a memory allocation problem? Give up now. */ |
48401fcf | 1073 | as_fatal (_("Broken assembler. No assembly attempted.")); |
670a50eb ILT |
1074 | } |
1075 | do | |
1076 | { | |
aa2e0460 | 1077 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1078 | { |
aa2e0460 KR |
1079 | if (!validate_mips_insn (&mips_opcodes[i])) |
1080 | broken = 1; | |
3d3c5039 | 1081 | } |
670a50eb ILT |
1082 | ++i; |
1083 | } | |
1084 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1085 | } |
1086 | ||
cc5703cd ILT |
1087 | mips16_op_hash = hash_new (); |
1088 | ||
1089 | i = 0; | |
1090 | while (i < bfd_mips16_num_opcodes) | |
1091 | { | |
1092 | const char *name = mips16_opcodes[i].name; | |
1093 | ||
1094 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1095 | if (retval != NULL) | |
48401fcf | 1096 | as_fatal (_("internal: can't hash `%s': %s"), |
cc5703cd ILT |
1097 | mips16_opcodes[i].name, retval); |
1098 | do | |
1099 | { | |
1100 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1101 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1102 | != mips16_opcodes[i].match)) | |
aa2e0460 | 1103 | { |
48401fcf | 1104 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
aa2e0460 KR |
1105 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
1106 | broken = 1; | |
1107 | } | |
cc5703cd ILT |
1108 | ++i; |
1109 | } | |
1110 | while (i < bfd_mips16_num_opcodes | |
1111 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1112 | } | |
1113 | ||
aa2e0460 | 1114 | if (broken) |
48401fcf | 1115 | as_fatal (_("Broken assembler. No assembly attempted.")); |
aa2e0460 | 1116 | |
ebf28372 ILT |
1117 | /* We add all the general register names to the symbol table. This |
1118 | helps us detect invalid uses of them. */ | |
1119 | for (i = 0; i < 32; i++) | |
1120 | { | |
1121 | char buf[5]; | |
1122 | ||
1123 | sprintf (buf, "$%d", i); | |
1124 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1125 | &zero_address_frag)); | |
1126 | } | |
1127 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1128 | &zero_address_frag)); | |
1129 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1130 | &zero_address_frag)); | |
1131 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1132 | &zero_address_frag)); | |
1133 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1134 | &zero_address_frag)); | |
1135 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1136 | &zero_address_frag)); | |
1137 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1138 | &zero_address_frag)); | |
1139 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1140 | &zero_address_frag)); | |
1141 | ||
4a1cb507 | 1142 | mips_no_prev_insn (false); |
becfe05e | 1143 | |
1aa6938e ILT |
1144 | mips_gprmask = 0; |
1145 | mips_cprmask[0] = 0; | |
1146 | mips_cprmask[1] = 0; | |
1147 | mips_cprmask[2] = 0; | |
1148 | mips_cprmask[3] = 0; | |
1149 | ||
8358c818 | 1150 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1151 | record_alignment (text_section, 2); |
8358c818 | 1152 | |
1dc1e798 KR |
1153 | if (USE_GLOBAL_POINTER_OPT) |
1154 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1155 | |
1dc1e798 KR |
1156 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1157 | { | |
08e17202 ILT |
1158 | /* On a native system, sections must be aligned to 16 byte |
1159 | boundaries. When configured for an embedded ELF target, we | |
1160 | don't bother. */ | |
1161 | if (strcmp (TARGET_OS, "elf") != 0) | |
1162 | { | |
1163 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1164 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1165 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1166 | } | |
1dc1e798 KR |
1167 | |
1168 | /* Create a .reginfo section for register masks and a .mdebug | |
1169 | section for debugging information. */ | |
1170 | { | |
1171 | segT seg; | |
1172 | subsegT subseg; | |
b3a64736 | 1173 | flagword flags; |
1dc1e798 KR |
1174 | segT sec; |
1175 | ||
1176 | seg = now_seg; | |
1177 | subseg = now_subseg; | |
1dc1e798 | 1178 | |
b3a64736 ILT |
1179 | /* The ABI says this section should be loaded so that the |
1180 | running program can access it. However, we don't load it | |
1181 | if we are configured for an embedded target */ | |
1182 | flags = SEC_READONLY | SEC_DATA; | |
1183 | if (strcmp (TARGET_OS, "elf") != 0) | |
1184 | flags |= SEC_ALLOC | SEC_LOAD; | |
1185 | ||
87178180 ILT |
1186 | if (! mips_64) |
1187 | { | |
1188 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1189 | |
b3a64736 ILT |
1190 | |
1191 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1192 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1193 | ||
f2a663d3 | 1194 | #ifdef OBJ_ELF |
87178180 | 1195 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1196 | #endif |
87178180 ILT |
1197 | } |
1198 | else | |
1199 | { | |
1200 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1201 | .reginfo section. */ | |
1202 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1203 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1204 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1205 | ||
1206 | #ifdef OBJ_ELF | |
1207 | /* Set up the option header. */ | |
1208 | { | |
1209 | Elf_Internal_Options opthdr; | |
1210 | char *f; | |
1211 | ||
1212 | opthdr.kind = ODK_REGINFO; | |
1213 | opthdr.size = (sizeof (Elf_External_Options) | |
1214 | + sizeof (Elf64_External_RegInfo)); | |
1215 | opthdr.section = 0; | |
1216 | opthdr.info = 0; | |
1217 | f = frag_more (sizeof (Elf_External_Options)); | |
1218 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1219 | (Elf_External_Options *) f); | |
1220 | ||
1221 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1222 | } | |
1223 | #endif | |
1224 | } | |
f2a663d3 | 1225 | |
739708fa KR |
1226 | if (ECOFF_DEBUGGING) |
1227 | { | |
1228 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1229 | (void) bfd_set_section_flags (stdoutput, sec, | |
1230 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1231 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1232 | } | |
0dd2d296 | 1233 | |
1dc1e798 KR |
1234 | subseg_set (seg, subseg); |
1235 | } | |
1236 | } | |
f2a663d3 | 1237 | |
739708fa KR |
1238 | if (! ECOFF_DEBUGGING) |
1239 | md_obj_begin (); | |
3d3c5039 ILT |
1240 | } |
1241 | ||
1242 | void | |
13fe1379 | 1243 | md_mips_end () |
3d3c5039 | 1244 | { |
739708fa KR |
1245 | if (! ECOFF_DEBUGGING) |
1246 | md_obj_end (); | |
3d3c5039 ILT |
1247 | } |
1248 | ||
1249 | void | |
670a50eb ILT |
1250 | md_assemble (str) |
1251 | char *str; | |
3d3c5039 | 1252 | { |
670a50eb | 1253 | struct mips_cl_insn insn; |
3d3c5039 | 1254 | |
5ac34ac3 | 1255 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1256 | imm_reloc = BFD_RELOC_UNUSED; |
1257 | imm_unmatched_hi = false; | |
5ac34ac3 | 1258 | offset_expr.X_op = O_absent; |
867a58b3 | 1259 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1260 | |
3c83da8a | 1261 | if (mips_opts.mips16) |
cc5703cd ILT |
1262 | mips16_ip (str, &insn); |
1263 | else | |
efec4a28 | 1264 | { |
9218cee0 | 1265 | mips_ip (str, &insn); |
48401fcf | 1266 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
efec4a28 DP |
1267 | str, insn.insn_opcode)); |
1268 | } | |
cc5703cd | 1269 | |
670a50eb ILT |
1270 | if (insn_error) |
1271 | { | |
1272 | as_bad ("%s `%s'", insn_error, str); | |
1273 | return; | |
1274 | } | |
cc5703cd | 1275 | |
670a50eb ILT |
1276 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1277 | { | |
3c83da8a | 1278 | if (mips_opts.mips16) |
cc5703cd ILT |
1279 | mips16_macro (&insn); |
1280 | else | |
1281 | macro (&insn); | |
3d3c5039 | 1282 | } |
670a50eb ILT |
1283 | else |
1284 | { | |
5ac34ac3 | 1285 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1286 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1287 | imm_unmatched_hi); | |
5ac34ac3 | 1288 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1289 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1290 | else |
867a58b3 | 1291 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1292 | } |
1293 | } | |
1294 | ||
cc5703cd ILT |
1295 | /* See whether instruction IP reads register REG. CLASS is the type |
1296 | of register. */ | |
becfe05e ILT |
1297 | |
1298 | static int | |
cc5703cd | 1299 | insn_uses_reg (ip, reg, class) |
becfe05e | 1300 | struct mips_cl_insn *ip; |
604633ae | 1301 | unsigned int reg; |
cc5703cd | 1302 | enum mips_regclass class; |
becfe05e | 1303 | { |
cc5703cd ILT |
1304 | if (class == MIPS16_REG) |
1305 | { | |
3c83da8a | 1306 | assert (mips_opts.mips16); |
cc5703cd ILT |
1307 | reg = mips16_to_32_reg_map[reg]; |
1308 | class = MIPS_GR_REG; | |
1309 | } | |
1310 | ||
becfe05e | 1311 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1312 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1313 | return 0; |
1314 | ||
cc5703cd | 1315 | if (class == MIPS_FP_REG) |
becfe05e | 1316 | { |
3c83da8a | 1317 | assert (! mips_opts.mips16); |
becfe05e ILT |
1318 | /* If we are called with either $f0 or $f1, we must check $f0. |
1319 | This is not optimal, because it will introduce an unnecessary | |
1320 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1321 | need to distinguish reading both $f0 and $f1 or just one of | |
1322 | them. Note that we don't have to check the other way, | |
1323 | because there is no instruction that sets both $f0 and $f1 | |
1324 | and requires a delay. */ | |
1325 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1326 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1327 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1328 | return 1; |
1329 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1330 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1331 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1332 | return 1; |
1333 | } | |
3c83da8a | 1334 | else if (! mips_opts.mips16) |
becfe05e ILT |
1335 | { |
1336 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1337 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1338 | return 1; | |
1339 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1340 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1341 | return 1; | |
1342 | } | |
cc5703cd ILT |
1343 | else |
1344 | { | |
1345 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1346 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1347 | & MIPS16OP_MASK_RX)] | |
1348 | == reg)) | |
cc5703cd ILT |
1349 | return 1; |
1350 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1351 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1352 | & MIPS16OP_MASK_RY)] | |
1353 | == reg)) | |
cc5703cd ILT |
1354 | return 1; |
1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1356 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1357 | & MIPS16OP_MASK_MOVE32Z)] | |
1358 | == reg)) | |
cc5703cd ILT |
1359 | return 1; |
1360 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1361 | return 1; | |
1362 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1363 | return 1; | |
1364 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1365 | return 1; | |
1366 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1367 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1368 | & MIPS16OP_MASK_REGR32) == reg) | |
1369 | return 1; | |
1370 | } | |
becfe05e ILT |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | ||
fb251650 ILT |
1375 | /* This function returns true if modifying a register requires a |
1376 | delay. */ | |
1377 | ||
1378 | static int | |
1379 | reg_needs_delay (reg) | |
1380 | int reg; | |
1381 | { | |
1382 | unsigned long prev_pinfo; | |
1383 | ||
1384 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1385 | if (! mips_opts.noreorder |
1386 | && mips_opts.isa < 4 | |
fb251650 | 1387 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1388 | || (! gpr_interlocks |
fb251650 ILT |
1389 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1390 | { | |
1391 | /* A load from a coprocessor or from memory. All load | |
1392 | delays delay the use of general register rt for one | |
1393 | instruction on the r3000. The r6000 and r4000 use | |
1394 | interlocks. */ | |
efec4a28 | 1395 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1396 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1397 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1398 | return 1; | |
1399 | } | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
3c83da8a JW |
1404 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1405 | handle them specially, such as generating jalx instructions when | |
1406 | needed. We also make them odd for the duration of the assembly, in | |
1407 | order to generate the right sort of code. We will make them even | |
1408 | in the adjust_symtab routine, while leaving them marked. This is | |
1409 | convenient for the debugger and the disassembler. The linker knows | |
1410 | to make them odd again. */ | |
1411 | ||
1412 | static void | |
1413 | mips16_mark_labels () | |
1414 | { | |
1415 | if (mips_opts.mips16) | |
1416 | { | |
1417 | struct insn_label_list *l; | |
1418 | ||
1419 | for (l = insn_labels; l != NULL; l = l->next) | |
1420 | { | |
68952421 | 1421 | #ifdef OBJ_ELF |
3c83da8a JW |
1422 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1423 | S_SET_OTHER (l->label, STO_MIPS16); | |
1424 | #endif | |
1425 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1426 | ++l->label->sy_value.X_add_number; | |
1427 | } | |
1428 | } | |
1429 | } | |
1430 | ||
0dd2d296 ILT |
1431 | /* Output an instruction. PLACE is where to put the instruction; if |
1432 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1433 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1434 | used with RELOC_TYPE. */ | |
3d3c5039 | 1435 | |
3d3c5039 | 1436 | static void |
867a58b3 | 1437 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1438 | char *place; |
670a50eb ILT |
1439 | struct mips_cl_insn *ip; |
1440 | expressionS *address_expr; | |
1441 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1442 | boolean unmatched_hi; |
3d3c5039 | 1443 | { |
1aa6938e | 1444 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1445 | char *f; |
becfe05e ILT |
1446 | fixS *fixp; |
1447 | int nops = 0; | |
3d3c5039 | 1448 | |
3c83da8a JW |
1449 | /* Mark instruction labels in mips16 mode. */ |
1450 | if (mips_opts.mips16) | |
1451 | mips16_mark_labels (); | |
fbcfacb7 | 1452 | |
1aa6938e ILT |
1453 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1454 | pinfo = ip->insn_mo->pinfo; | |
1455 | ||
3c83da8a | 1456 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1457 | { |
4a1cb507 ILT |
1458 | int prev_prev_nop; |
1459 | ||
becfe05e | 1460 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1461 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1462 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1463 | (1) a load from memory delay |
1464 | (2) a load from a coprocessor delay | |
1465 | (3) an unconditional branch delay | |
1466 | (4) a conditional branch delay | |
1467 | (5) a move to coprocessor register delay | |
1468 | (6) a load coprocessor register from memory delay | |
1469 | (7) a coprocessor condition code delay | |
1470 | (8) a HI/LO special register delay | |
becfe05e ILT |
1471 | |
1472 | There are a lot of optimizations we could do that we don't. | |
1473 | In particular, we do not, in general, reorder instructions. | |
1474 | If you use gcc with optimization, it will reorder | |
1475 | instructions and generally do much more optimization then we | |
1476 | do here; repeating all that work in the assembler would only | |
1477 | benefit hand written assembly code, and does not seem worth | |
1478 | it. */ | |
1479 | ||
1480 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1481 | #define emit_nop() \ |
3c83da8a | 1482 | (mips_opts.mips16 \ |
cc5703cd ILT |
1483 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1484 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1485 | |
1486 | /* The previous insn might require a delay slot, depending upon | |
1487 | the contents of the current insn. */ | |
3c83da8a JW |
1488 | if (! mips_opts.mips16 |
1489 | && mips_opts.isa < 4 | |
5af96dce ILT |
1490 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1491 | && ! cop_interlocks) | |
5c6f5923 | 1492 | || (! gpr_interlocks |
d8a1c247 | 1493 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1494 | { |
1495 | /* A load from a coprocessor or from memory. All load | |
1496 | delays delay the use of general register rt for one | |
1497 | instruction on the r3000. The r6000 and r4000 use | |
1498 | interlocks. */ | |
efec4a28 | 1499 | /* Itbl support may require additional care here. */ |
1aa6938e | 1500 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1501 | if (mips_optimize == 0 |
1502 | || insn_uses_reg (ip, | |
1503 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1504 | & OP_MASK_RT), | |
cc5703cd | 1505 | MIPS_GR_REG)) |
becfe05e ILT |
1506 | ++nops; |
1507 | } | |
3c83da8a JW |
1508 | else if (! mips_opts.mips16 |
1509 | && mips_opts.isa < 4 | |
5af96dce ILT |
1510 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1511 | && ! cop_interlocks) | |
3c83da8a | 1512 | || (mips_opts.isa < 2 |
d8a1c247 | 1513 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1514 | { |
1515 | /* A generic coprocessor delay. The previous instruction | |
1516 | modified a coprocessor general or control register. If | |
1517 | it modified a control register, we need to avoid any | |
1518 | coprocessor instruction (this is probably not always | |
1519 | required, but it sometimes is). If it modified a general | |
1520 | register, we avoid using that register. | |
1521 | ||
8358c818 ILT |
1522 | On the r6000 and r4000 loading a coprocessor register |
1523 | from memory is interlocked, and does not require a delay. | |
1524 | ||
becfe05e ILT |
1525 | This case is not handled very well. There is no special |
1526 | knowledge of CP0 handling, and the coprocessors other | |
1527 | than the floating point unit are not distinguished at | |
1528 | all. */ | |
efec4a28 DP |
1529 | /* Itbl support may require additional care here. FIXME! |
1530 | Need to modify this to include knowledge about | |
1531 | user specified delays! */ | |
1aa6938e | 1532 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1533 | { |
0aa07269 ILT |
1534 | if (mips_optimize == 0 |
1535 | || insn_uses_reg (ip, | |
8358c818 ILT |
1536 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1537 | & OP_MASK_FT), | |
cc5703cd | 1538 | MIPS_FP_REG)) |
becfe05e ILT |
1539 | ++nops; |
1540 | } | |
1aa6938e | 1541 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1542 | { |
0aa07269 ILT |
1543 | if (mips_optimize == 0 |
1544 | || insn_uses_reg (ip, | |
8358c818 ILT |
1545 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1546 | & OP_MASK_FS), | |
cc5703cd | 1547 | MIPS_FP_REG)) |
becfe05e ILT |
1548 | ++nops; |
1549 | } | |
1550 | else | |
1551 | { | |
1552 | /* We don't know exactly what the previous instruction | |
1553 | does. If the current instruction uses a coprocessor | |
1554 | register, we must insert a NOP. If previous | |
1555 | instruction may set the condition codes, and the | |
1556 | current instruction uses them, we must insert two | |
1557 | NOPS. */ | |
efec4a28 | 1558 | /* Itbl support may require additional care here. */ |
0aa07269 | 1559 | if (mips_optimize == 0 |
1aa6938e ILT |
1560 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1561 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1562 | nops += 2; |
1aa6938e | 1563 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1564 | ++nops; |
1565 | } | |
1566 | } | |
3c83da8a JW |
1567 | else if (! mips_opts.mips16 |
1568 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1569 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1570 | && ! cop_interlocks) | |
becfe05e ILT |
1571 | { |
1572 | /* The previous instruction sets the coprocessor condition | |
1573 | codes, but does not require a general coprocessor delay | |
1574 | (this means it is a floating point comparison | |
1575 | instruction). If this instruction uses the condition | |
1576 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1577 | /* Itbl support may require additional care here. */ |
0aa07269 | 1578 | if (mips_optimize == 0 |
1aa6938e | 1579 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1580 | ++nops; |
1581 | } | |
1aa6938e | 1582 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1583 | { |
1584 | /* The previous instruction reads the LO register; if the | |
1585 | current instruction writes to the LO register, we must | |
517078c1 | 1586 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1587 | if (! hilo_interlocks |
b2b8c24e ILT |
1588 | && (mips_optimize == 0 |
1589 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1590 | nops += 2; |
1591 | } | |
1592 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1593 | { | |
1594 | /* The previous instruction reads the HI register; if the | |
1595 | current instruction writes to the HI register, we must | |
517078c1 | 1596 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1597 | if (! hilo_interlocks |
b2b8c24e ILT |
1598 | && (mips_optimize == 0 |
1599 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1600 | nops += 2; |
1601 | } | |
1602 | ||
4a1cb507 ILT |
1603 | /* If the previous instruction was in a noreorder section, then |
1604 | we don't want to insert the nop after all. */ | |
efec4a28 | 1605 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1606 | if (prev_insn_unreordered) |
1607 | nops = 0; | |
1608 | ||
becfe05e ILT |
1609 | /* There are two cases which require two intervening |
1610 | instructions: 1) setting the condition codes using a move to | |
1611 | coprocessor instruction which requires a general coprocessor | |
1612 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1613 | or LO register and then writing to it (except on processors |
1614 | which have interlocks). If we are not already emitting a NOP | |
1615 | instruction, we must check for these cases compared to the | |
1616 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1617 | if ((! mips_opts.mips16 |
1618 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1619 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1620 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1621 | && (pinfo & INSN_READ_COND_CODE) | |
1622 | && ! cop_interlocks) | |
1623 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1624 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1625 | && ! hilo_interlocks) |
4a1cb507 ILT |
1626 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1627 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1628 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1629 | prev_prev_nop = 1; |
1630 | else | |
1631 | prev_prev_nop = 0; | |
1632 | ||
1633 | if (prev_prev_insn_unreordered) | |
1634 | prev_prev_nop = 0; | |
1635 | ||
1636 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1637 | ++nops; |
1638 | ||
0dd2d296 ILT |
1639 | /* If we are being given a nop instruction, don't bother with |
1640 | one of the nops we would otherwise output. This will only | |
1641 | happen when a nop instruction is used with mips_optimize set | |
1642 | to 0. */ | |
4a1cb507 | 1643 | if (nops > 0 |
3c83da8a JW |
1644 | && ! mips_opts.noreorder |
1645 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1646 | --nops; |
1647 | ||
becfe05e | 1648 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1649 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1650 | { |
5af96dce ILT |
1651 | fragS *old_frag; |
1652 | unsigned long old_frag_offset; | |
8c63448a | 1653 | int i; |
fbcfacb7 | 1654 | struct insn_label_list *l; |
8c63448a | 1655 | |
5af96dce ILT |
1656 | old_frag = frag_now; |
1657 | old_frag_offset = frag_now_fix (); | |
1658 | ||
8c63448a | 1659 | for (i = 0; i < nops; i++) |
becfe05e | 1660 | emit_nop (); |
5af96dce | 1661 | |
af255ca0 | 1662 | if (listing) |
546f5536 ILT |
1663 | { |
1664 | listing_prev_line (); | |
1665 | /* We may be at the start of a variant frag. In case we | |
1666 | are, make sure there is enough space for the frag | |
1667 | after the frags created by listing_prev_line. The | |
1668 | argument to frag_grow here must be at least as large | |
1669 | as the argument to all other calls to frag_grow in | |
1670 | this file. We don't have to worry about being in the | |
1671 | middle of a variant frag, because the variants insert | |
1672 | all needed nop instructions themselves. */ | |
1673 | frag_grow (40); | |
1674 | } | |
5af96dce | 1675 | |
fbcfacb7 | 1676 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1677 | { |
fbcfacb7 ILT |
1678 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1679 | l->label->sy_frag = frag_now; | |
1680 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1681 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1682 | if (mips_opts.mips16) |
fbcfacb7 | 1683 | ++l->label->sy_value.X_add_number; |
becfe05e | 1684 | } |
5af96dce ILT |
1685 | |
1686 | #ifndef NO_ECOFF_DEBUGGING | |
1687 | if (ECOFF_DEBUGGING) | |
1688 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1689 | #endif | |
becfe05e | 1690 | } |
4a1cb507 ILT |
1691 | else if (prev_nop_frag != NULL) |
1692 | { | |
1693 | /* We have a frag holding nops we may be able to remove. If | |
1694 | we don't need any nops, we can decrease the size of | |
1695 | prev_nop_frag by the size of one instruction. If we do | |
1696 | need some nops, we count them in prev_nops_required. */ | |
1697 | if (prev_nop_frag_since == 0) | |
1698 | { | |
1699 | if (nops == 0) | |
1700 | { | |
3c83da8a | 1701 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1702 | --prev_nop_frag_holds; |
1703 | } | |
1704 | else | |
1705 | prev_nop_frag_required += nops; | |
1706 | } | |
1707 | else | |
1708 | { | |
1709 | if (prev_prev_nop == 0) | |
1710 | { | |
3c83da8a | 1711 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1712 | --prev_nop_frag_holds; |
1713 | } | |
1714 | else | |
1715 | ++prev_nop_frag_required; | |
1716 | } | |
1717 | ||
1718 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1719 | prev_nop_frag = NULL; | |
1720 | ||
1721 | ++prev_nop_frag_since; | |
1722 | ||
1723 | /* Sanity check: by the time we reach the second instruction | |
1724 | after prev_nop_frag, we should have used up all the nops | |
1725 | one way or another. */ | |
1726 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1727 | } | |
becfe05e | 1728 | } |
4a1cb507 | 1729 | |
cc5703cd ILT |
1730 | if (reloc_type > BFD_RELOC_UNUSED) |
1731 | { | |
1732 | /* We need to set up a variant frag. */ | |
3c83da8a | 1733 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1734 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1735 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1736 | mips16_small, mips16_ext, |
1737 | (prev_pinfo | |
1738 | & INSN_UNCOND_BRANCH_DELAY), | |
1739 | (prev_insn_reloc_type | |
1740 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1741 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1742 | (char *) NULL); |
1743 | } | |
1744 | else if (place != NULL) | |
0dd2d296 | 1745 | f = place; |
3c83da8a JW |
1746 | else if (mips_opts.mips16 |
1747 | && ! ip->use_extend | |
1748 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1749 | { |
1750 | /* Make sure there is enough room to swap this instruction with | |
1751 | a following jump instruction. */ | |
1752 | frag_grow (6); | |
1753 | f = frag_more (2); | |
1754 | } | |
cc5703cd | 1755 | else |
035936da | 1756 | { |
3c83da8a JW |
1757 | if (mips_opts.mips16 |
1758 | && mips_opts.noreorder | |
035936da | 1759 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
48401fcf | 1760 | as_warn (_("extended instruction in delay slot")); |
035936da ILT |
1761 | |
1762 | f = frag_more (4); | |
1763 | } | |
1764 | ||
becfe05e | 1765 | fixp = NULL; |
cc5703cd | 1766 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1767 | { |
5ac34ac3 | 1768 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1769 | { |
1770 | switch (reloc_type) | |
1771 | { | |
3d3c5039 | 1772 | case BFD_RELOC_32: |
670a50eb ILT |
1773 | ip->insn_opcode |= address_expr->X_add_number; |
1774 | break; | |
3d3c5039 ILT |
1775 | |
1776 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1777 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1778 | break; | |
3d3c5039 ILT |
1779 | |
1780 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 | 1781 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1782 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1783 | (unsigned long) address_expr->X_add_number); |
5e1e8f23 ILT |
1784 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1785 | break; | |
1786 | ||
cc5703cd | 1787 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 | 1788 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1789 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1790 | (unsigned long) address_expr->X_add_number); |
cc5703cd ILT |
1791 | ip->insn_opcode |= |
1792 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1793 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1794 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1795 | break; | |
1796 | ||
3c69baf9 | 1797 | /* start-sanitize-r5900 */ |
0bc0e337 JL |
1798 | case BFD_RELOC_MIPS15_S3: |
1799 | ip->insn_opcode |= ((imm_expr.X_add_number & 0x7fff) >> 3) << 6; | |
1800 | break; | |
3c69baf9 | 1801 | /* end-sanitize-r5900 */ |
0bc0e337 | 1802 | |
3d3c5039 | 1803 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1804 | goto need_reloc; |
3d3c5039 ILT |
1805 | |
1806 | default: | |
670a50eb | 1807 | internalError (); |
3d3c5039 | 1808 | } |
670a50eb ILT |
1809 | } |
1810 | else | |
1811 | { | |
3d3c5039 | 1812 | need_reloc: |
0dd2d296 ILT |
1813 | /* Don't generate a reloc if we are writing into a variant |
1814 | frag. */ | |
1815 | if (place == NULL) | |
867a58b3 ILT |
1816 | { |
1817 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1818 | address_expr, | |
1819 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1820 | reloc_type); | |
1821 | if (unmatched_hi) | |
1822 | { | |
1823 | struct mips_hi_fixup *hi_fixup; | |
1824 | ||
1825 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1826 | hi_fixup = ((struct mips_hi_fixup *) | |
1827 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1828 | hi_fixup->fixp = fixp; | |
1829 | hi_fixup->seg = now_seg; | |
1830 | hi_fixup->next = mips_hi_fixup_list; | |
1831 | mips_hi_fixup_list = hi_fixup; | |
1832 | } | |
1833 | } | |
3d3c5039 ILT |
1834 | } |
1835 | } | |
becfe05e | 1836 | |
3c83da8a | 1837 | if (! mips_opts.mips16) |
cc5703cd | 1838 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1839 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1840 | { | |
1841 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1842 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1843 | } | |
cc5703cd ILT |
1844 | else |
1845 | { | |
1846 | if (ip->use_extend) | |
1847 | { | |
1848 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1849 | f += 2; | |
1850 | } | |
1851 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1852 | } | |
670a50eb | 1853 | |
1aa6938e | 1854 | /* Update the register mask information. */ |
3c83da8a | 1855 | if (! mips_opts.mips16) |
cc5703cd ILT |
1856 | { |
1857 | if (pinfo & INSN_WRITE_GPR_D) | |
1858 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1859 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1860 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1861 | if (pinfo & INSN_READ_GPR_S) | |
1862 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1863 | if (pinfo & INSN_WRITE_GPR_31) | |
1864 | mips_gprmask |= 1 << 31; | |
1865 | if (pinfo & INSN_WRITE_FPR_D) | |
1866 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1867 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1868 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1869 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1870 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1871 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1872 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1873 | if (pinfo & INSN_COP) | |
1874 | { | |
efec4a28 DP |
1875 | /* We don't keep enough information to sort these cases out. |
1876 | The itbl support does keep this information however, although | |
1877 | we currently don't support itbl fprmats as part of the cop | |
1878 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1879 | } |
1880 | /* Never set the bit for $0, which is always zero. */ | |
1881 | mips_gprmask &=~ 1 << 0; | |
1882 | } | |
1883 | else | |
1aa6938e | 1884 | { |
cc5703cd ILT |
1885 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1886 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1887 | & MIPS16OP_MASK_RX); | |
1888 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1889 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1890 | & MIPS16OP_MASK_RY); | |
1891 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1892 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1893 | & MIPS16OP_MASK_RZ); | |
1894 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1895 | mips_gprmask |= 1 << TREG; | |
1896 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1897 | mips_gprmask |= 1 << SP; | |
1898 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1899 | mips_gprmask |= 1 << RA; | |
1900 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1901 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1902 | if (pinfo & MIPS16_INSN_READ_Z) | |
1903 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1904 | & MIPS16OP_MASK_MOVE32Z); | |
1905 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1906 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1907 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1908 | } |
1aa6938e | 1909 | |
3c83da8a | 1910 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1911 | { |
becfe05e ILT |
1912 | /* Filling the branch delay slot is more complex. We try to |
1913 | switch the branch with the previous instruction, which we can | |
1914 | do if the previous instruction does not set up a condition | |
1915 | that the branch tests and if the branch is not itself the | |
1916 | target of any branch. */ | |
1aa6938e ILT |
1917 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1918 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1919 | { |
0aa07269 | 1920 | if (mips_optimize < 2 |
19ed8960 ILT |
1921 | /* If we have seen .set volatile or .set nomove, don't |
1922 | optimize. */ | |
3c83da8a | 1923 | || mips_opts.nomove != 0 |
4e95866e ILT |
1924 | /* If we had to emit any NOP instructions, then we |
1925 | already know we can not swap. */ | |
1926 | || nops != 0 | |
becfe05e ILT |
1927 | /* If we don't even know the previous insn, we can not |
1928 | swap. */ | |
1929 | || ! prev_insn_valid | |
1930 | /* If the previous insn is already in a branch delay | |
1931 | slot, then we can not swap. */ | |
1932 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1933 | /* If the previous previous insn was in a .set |
1934 | noreorder, we can't swap. Actually, the MIPS | |
1935 | assembler will swap in this situation. However, gcc | |
1936 | configured -with-gnu-as will generate code like | |
1937 | .set noreorder | |
1938 | lw $4,XXX | |
1939 | .set reorder | |
1940 | INSN | |
1941 | bne $4,$0,foo | |
1942 | in which we can not swap the bne and INSN. If gcc is | |
1943 | not configured -with-gnu-as, it does not output the | |
1944 | .set pseudo-ops. We don't have to check | |
1945 | prev_insn_unreordered, because prev_insn_valid will | |
1946 | be 0 in that case. We don't want to use | |
1947 | prev_prev_insn_valid, because we do want to be able | |
1948 | to swap at the start of a function. */ | |
1949 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1950 | /* If the branch is itself the target of a branch, we |
1951 | can not swap. We cheat on this; all we check for is | |
1952 | whether there is a label on this instruction. If | |
1953 | there are any branches to anything other than a | |
1954 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1955 | || insn_labels != NULL |
777ad64d | 1956 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1957 | can not do the swap. This does not apply to the |
1958 | mips16, which uses variant frags for different | |
1959 | purposes. */ | |
3c83da8a | 1960 | || (! mips_opts.mips16 |
cc5703cd | 1961 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1962 | /* If the branch reads the condition codes, we don't |
1963 | even try to swap, because in the sequence | |
1964 | ctc1 $X,$31 | |
1965 | INSN | |
1966 | INSN | |
1967 | bc1t LABEL | |
1968 | we can not swap, and I don't feel like handling that | |
1969 | case. */ | |
3c83da8a JW |
1970 | || (! mips_opts.mips16 |
1971 | && mips_opts.isa < 4 | |
d8a1c247 | 1972 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1973 | /* We can not swap with an instruction that requires a |
1974 | delay slot, becase the target of the branch might | |
1975 | interfere with that instruction. */ | |
3c83da8a JW |
1976 | || (! mips_opts.mips16 |
1977 | && mips_opts.isa < 4 | |
d8a1c247 | 1978 | && (prev_pinfo |
efec4a28 | 1979 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1980 | & (INSN_LOAD_COPROC_DELAY |
1981 | | INSN_COPROC_MOVE_DELAY | |
1982 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1983 | || (! hilo_interlocks |
b2b8c24e ILT |
1984 | && (prev_pinfo |
1985 | & (INSN_READ_LO | |
1986 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1987 | || (! mips_opts.mips16 |
1988 | && ! gpr_interlocks | |
1989 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1990 | || (! mips_opts.mips16 |
1991 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1992 | /* Itbl support may require additional care here. */ |
1993 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1994 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1995 | || (prev_pinfo |
6e8dda9c ILT |
1996 | & (INSN_UNCOND_BRANCH_DELAY |
1997 | | INSN_COND_BRANCH_DELAY | |
1998 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1999 | /* We do not swap with a trap instruction, since it |
2000 | complicates trap handlers to have the trap | |
2001 | instruction be in a delay slot. */ | |
1aa6938e | 2002 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
2003 | /* If the branch reads a register that the previous |
2004 | instruction sets, we can not swap. */ | |
3c83da8a | 2005 | || (! mips_opts.mips16 |
cc5703cd | 2006 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2007 | && insn_uses_reg (ip, |
2008 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2009 | & OP_MASK_RT), | |
cc5703cd | 2010 | MIPS_GR_REG)) |
3c83da8a | 2011 | || (! mips_opts.mips16 |
cc5703cd | 2012 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2013 | && insn_uses_reg (ip, |
2014 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2015 | & OP_MASK_RD), | |
cc5703cd | 2016 | MIPS_GR_REG)) |
3c83da8a | 2017 | || (mips_opts.mips16 |
cc5703cd ILT |
2018 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2019 | && insn_uses_reg (ip, | |
2020 | ((prev_insn.insn_opcode | |
2021 | >> MIPS16OP_SH_RX) | |
2022 | & MIPS16OP_MASK_RX), | |
2023 | MIPS16_REG)) | |
2024 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2025 | && insn_uses_reg (ip, | |
2026 | ((prev_insn.insn_opcode | |
2027 | >> MIPS16OP_SH_RY) | |
2028 | & MIPS16OP_MASK_RY), | |
2029 | MIPS16_REG)) | |
2030 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2031 | && insn_uses_reg (ip, | |
2032 | ((prev_insn.insn_opcode | |
2033 | >> MIPS16OP_SH_RZ) | |
2034 | & MIPS16OP_MASK_RZ), | |
2035 | MIPS16_REG)) | |
2036 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2037 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2038 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2039 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2040 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2041 | && insn_uses_reg (ip, | |
2042 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2043 | insn_opcode), | |
2044 | MIPS_GR_REG)))) | |
1849d646 ILT |
2045 | /* If the branch writes a register that the previous |
2046 | instruction sets, we can not swap (we know that | |
2047 | branches write only to RD or to $31). */ | |
3c83da8a | 2048 | || (! mips_opts.mips16 |
cc5703cd | 2049 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2050 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2051 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2052 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2053 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2054 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2055 | & OP_MASK_RT) | |
2056 | == 31)))) | |
3c83da8a | 2057 | || (! mips_opts.mips16 |
cc5703cd | 2058 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2059 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2060 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2061 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2062 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2063 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2064 | & OP_MASK_RD) | |
2065 | == 31)))) | |
3c83da8a | 2066 | || (mips_opts.mips16 |
cc5703cd ILT |
2067 | && (pinfo & MIPS16_INSN_WRITE_31) |
2068 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2069 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2070 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2071 | == RA)))) | |
becfe05e ILT |
2072 | /* If the branch writes a register that the previous |
2073 | instruction reads, we can not swap (we know that | |
2074 | branches only write to RD or to $31). */ | |
3c83da8a | 2075 | || (! mips_opts.mips16 |
cc5703cd | 2076 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2077 | && insn_uses_reg (&prev_insn, |
2078 | ((ip->insn_opcode >> OP_SH_RD) | |
2079 | & OP_MASK_RD), | |
cc5703cd | 2080 | MIPS_GR_REG)) |
3c83da8a | 2081 | || (! mips_opts.mips16 |
cc5703cd ILT |
2082 | && (pinfo & INSN_WRITE_GPR_31) |
2083 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2084 | || (mips_opts.mips16 |
cc5703cd ILT |
2085 | && (pinfo & MIPS16_INSN_WRITE_31) |
2086 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2087 | /* If we are generating embedded PIC code, the branch |
2088 | might be expanded into a sequence which uses $at, so | |
2089 | we can't swap with an instruction which reads it. */ | |
2090 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2091 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2092 | /* If the previous previous instruction has a load |
2093 | delay, and sets a register that the branch reads, we | |
2094 | can not swap. */ | |
3c83da8a JW |
2095 | || (! mips_opts.mips16 |
2096 | && mips_opts.isa < 4 | |
efec4a28 | 2097 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2098 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2099 | || (! gpr_interlocks |
d8a1c247 KR |
2100 | && (prev_prev_insn.insn_mo->pinfo |
2101 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2102 | && insn_uses_reg (ip, |
2103 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2104 | & OP_MASK_RT), | |
cc5703cd | 2105 | MIPS_GR_REG)) |
d31a3f5e ILT |
2106 | /* If one instruction sets a condition code and the |
2107 | other one uses a condition code, we can not swap. */ | |
2108 | || ((pinfo & INSN_READ_COND_CODE) | |
2109 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2110 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2111 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2112 | /* If the previous instruction uses the PC, we can not | |
2113 | swap. */ | |
3c83da8a | 2114 | || (mips_opts.mips16 |
cc5703cd ILT |
2115 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2116 | /* If the previous instruction was extended, we can not | |
2117 | swap. */ | |
3c83da8a | 2118 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2119 | /* If the previous instruction had a fixup in mips16 |
2120 | mode, we can not swap. This normally means that the | |
2121 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2122 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2123 | { |
2124 | /* We could do even better for unconditional branches to | |
2125 | portions of this object file; we could pick up the | |
2126 | instruction at the destination, put it in the delay | |
2127 | slot, and bump the destination address. */ | |
2128 | emit_nop (); | |
2129 | /* Update the previous insn information. */ | |
2130 | prev_prev_insn = *ip; | |
2131 | prev_insn.insn_mo = &dummy_opcode; | |
2132 | } | |
2133 | else | |
2134 | { | |
becfe05e | 2135 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2136 | if (! mips_opts.mips16) |
cc5703cd ILT |
2137 | { |
2138 | char *prev_f; | |
2139 | char temp[4]; | |
2140 | ||
2141 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2142 | memcpy (temp, prev_f, 4); | |
2143 | memcpy (prev_f, f, 4); | |
2144 | memcpy (f, temp, 4); | |
2145 | if (prev_insn_fixp) | |
2146 | { | |
2147 | prev_insn_fixp->fx_frag = frag_now; | |
2148 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2149 | } | |
2150 | if (fixp) | |
2151 | { | |
2152 | fixp->fx_frag = prev_insn_frag; | |
2153 | fixp->fx_where = prev_insn_where; | |
2154 | } | |
2155 | } | |
cc5703cd | 2156 | else |
becfe05e | 2157 | { |
cc5703cd ILT |
2158 | char *prev_f; |
2159 | char temp[2]; | |
2160 | ||
2161 | assert (prev_insn_fixp == NULL); | |
2162 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2163 | memcpy (temp, prev_f, 2); | |
2164 | memcpy (prev_f, f, 2); | |
2165 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2166 | { |
2167 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2168 | memcpy (f, temp, 2); | |
2169 | } | |
cc5703cd ILT |
2170 | else |
2171 | { | |
2172 | memcpy (f, f + 2, 2); | |
2173 | memcpy (f + 2, temp, 2); | |
2174 | } | |
2175 | if (fixp) | |
2176 | { | |
2177 | fixp->fx_frag = prev_insn_frag; | |
2178 | fixp->fx_where = prev_insn_where; | |
2179 | } | |
becfe05e | 2180 | } |
cc5703cd | 2181 | |
becfe05e ILT |
2182 | /* Update the previous insn information; leave prev_insn |
2183 | unchanged. */ | |
2184 | prev_prev_insn = *ip; | |
2185 | } | |
2186 | prev_insn_is_delay_slot = 1; | |
2187 | ||
2188 | /* If that was an unconditional branch, forget the previous | |
2189 | insn information. */ | |
1aa6938e | 2190 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2191 | { |
2192 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2193 | prev_insn.insn_mo = &dummy_opcode; | |
2194 | } | |
a677feeb ILT |
2195 | |
2196 | prev_insn_fixp = NULL; | |
2197 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2198 | prev_insn_extended = 0; | |
becfe05e | 2199 | } |
1aa6938e | 2200 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2201 | { |
2202 | /* We don't yet optimize a branch likely. What we should do | |
2203 | is look at the target, copy the instruction found there | |
2204 | into the delay slot, and increment the branch to jump to | |
2205 | the next instruction. */ | |
2206 | emit_nop (); | |
2207 | /* Update the previous insn information. */ | |
2208 | prev_prev_insn = *ip; | |
2209 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2210 | prev_insn_fixp = NULL; |
2211 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2212 | prev_insn_extended = 0; | |
8358c818 | 2213 | } |
becfe05e | 2214 | else |
670a50eb | 2215 | { |
becfe05e ILT |
2216 | /* Update the previous insn information. */ |
2217 | if (nops > 0) | |
2218 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2219 | else | |
2220 | prev_prev_insn = prev_insn; | |
2221 | prev_insn = *ip; | |
2222 | ||
2223 | /* Any time we see a branch, we always fill the delay slot | |
2224 | immediately; since this insn is not a branch, we know it | |
2225 | is not in a delay slot. */ | |
2226 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2227 | |
2228 | prev_insn_fixp = fixp; | |
2229 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2230 | if (mips_opts.mips16) |
a677feeb ILT |
2231 | prev_insn_extended = (ip->use_extend |
2232 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2233 | } |
2234 | ||
4e95866e ILT |
2235 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2236 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2237 | prev_insn_frag = frag_now; |
2238 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2239 | prev_insn_valid = 1; |
2240 | } | |
fbcfacb7 | 2241 | else if (place == NULL) |
a677feeb | 2242 | { |
fbcfacb7 | 2243 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2244 | reordering, in order to determine the base address for mips16 |
2245 | PC relative relocs. */ | |
4a1cb507 | 2246 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2247 | prev_insn = *ip; |
2248 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2249 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2250 | prev_insn_unreordered = 1; | |
a677feeb | 2251 | } |
3d3c5039 | 2252 | |
becfe05e | 2253 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2254 | mips_clear_insn_labels (); |
b073d428 ILT |
2255 | |
2256 | /* We must ensure that a fixup associated with an unmatched %hi | |
2257 | reloc does not become a variant frag. Otherwise, the | |
2258 | rearrangement of %hi relocs in frob_file may confuse | |
2259 | tc_gen_reloc. */ | |
2260 | if (unmatched_hi) | |
2261 | { | |
2262 | frag_wane (frag_now); | |
2263 | frag_new (0); | |
2264 | } | |
becfe05e ILT |
2265 | } |
2266 | ||
2267 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2268 | label. If PRESERVE is non-zero, it remembers enough information to |
2269 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2270 | |
2271 | static void | |
4a1cb507 ILT |
2272 | mips_no_prev_insn (preserve) |
2273 | int preserve; | |
becfe05e | 2274 | { |
4a1cb507 ILT |
2275 | if (! preserve) |
2276 | { | |
2277 | prev_insn.insn_mo = &dummy_opcode; | |
2278 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2279 | prev_nop_frag = NULL; | |
2280 | prev_nop_frag_holds = 0; | |
2281 | prev_nop_frag_required = 0; | |
2282 | prev_nop_frag_since = 0; | |
2283 | } | |
becfe05e ILT |
2284 | prev_insn_valid = 0; |
2285 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2286 | prev_insn_unreordered = 0; |
cc5703cd | 2287 | prev_insn_extended = 0; |
a677feeb | 2288 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2289 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2290 | mips_clear_insn_labels (); |
becfe05e ILT |
2291 | } |
2292 | ||
2293 | /* This function must be called whenever we turn on noreorder or emit | |
2294 | something other than instructions. It inserts any NOPS which might | |
2295 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2296 | kept for the previous instructions. The INSNS parameter is true if |
2297 | instructions are to follow. */ | |
becfe05e ILT |
2298 | |
2299 | static void | |
fbcfacb7 ILT |
2300 | mips_emit_delays (insns) |
2301 | boolean insns; | |
becfe05e | 2302 | { |
3c83da8a | 2303 | if (! mips_opts.noreorder) |
becfe05e | 2304 | { |
4a1cb507 | 2305 | int nops; |
becfe05e | 2306 | |
4a1cb507 | 2307 | nops = 0; |
3c83da8a JW |
2308 | if ((! mips_opts.mips16 |
2309 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2310 | && (! cop_interlocks |
2311 | && (prev_insn.insn_mo->pinfo | |
2312 | & (INSN_LOAD_COPROC_DELAY | |
2313 | | INSN_COPROC_MOVE_DELAY | |
2314 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2315 | || (! hilo_interlocks |
b2b8c24e ILT |
2316 | && (prev_insn.insn_mo->pinfo |
2317 | & (INSN_READ_LO | |
2318 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2319 | || (! mips_opts.mips16 |
2320 | && ! gpr_interlocks | |
2321 | && (prev_insn.insn_mo->pinfo | |
2322 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2323 | || (! mips_opts.mips16 |
2324 | && mips_opts.isa < 2 | |
8358c818 | 2325 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2326 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2327 | { |
efec4a28 | 2328 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2329 | ++nops; |
3c83da8a JW |
2330 | if ((! mips_opts.mips16 |
2331 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2332 | && (! cop_interlocks |
2333 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2334 | || (! hilo_interlocks |
b2b8c24e ILT |
2335 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2336 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2337 | ++nops; |
2338 | ||
2339 | if (prev_insn_unreordered) | |
2340 | nops = 0; | |
becfe05e | 2341 | } |
3c83da8a JW |
2342 | else if ((! mips_opts.mips16 |
2343 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2344 | && (! cop_interlocks |
2345 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2346 | || (! hilo_interlocks |
b2b8c24e ILT |
2347 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2348 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2349 | { |
efec4a28 | 2350 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2351 | if (! prev_prev_insn_unreordered) |
2352 | ++nops; | |
2353 | } | |
2354 | ||
2355 | if (nops > 0) | |
670a50eb | 2356 | { |
fbcfacb7 ILT |
2357 | struct insn_label_list *l; |
2358 | ||
4a1cb507 ILT |
2359 | if (insns) |
2360 | { | |
2361 | /* Record the frag which holds the nop instructions, so | |
2362 | that we can remove them if we don't need them. */ | |
3c83da8a | 2363 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2364 | prev_nop_frag = frag_now; |
2365 | prev_nop_frag_holds = nops; | |
2366 | prev_nop_frag_required = 0; | |
2367 | prev_nop_frag_since = 0; | |
2368 | } | |
2369 | ||
2370 | for (; nops > 0; --nops) | |
2371 | emit_nop (); | |
2372 | ||
2373 | if (insns) | |
2374 | { | |
2375 | /* Move on to a new frag, so that it is safe to simply | |
2376 | decrease the size of prev_nop_frag. */ | |
2377 | frag_wane (frag_now); | |
2378 | frag_new (0); | |
2379 | } | |
2380 | ||
fbcfacb7 | 2381 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2382 | { |
fbcfacb7 ILT |
2383 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2384 | l->label->sy_frag = frag_now; | |
2385 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2386 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2387 | if (mips_opts.mips16) |
fbcfacb7 | 2388 | ++l->label->sy_value.X_add_number; |
becfe05e | 2389 | } |
3d3c5039 ILT |
2390 | } |
2391 | } | |
0221ddf7 | 2392 | |
3c83da8a JW |
2393 | /* Mark instruction labels in mips16 mode. */ |
2394 | if (mips_opts.mips16 && insns) | |
2395 | mips16_mark_labels (); | |
fbcfacb7 | 2396 | |
4a1cb507 | 2397 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2398 | } |
2399 | ||
670a50eb ILT |
2400 | /* Build an instruction created by a macro expansion. This is passed |
2401 | a pointer to the count of instructions created so far, an | |
2402 | expression, the name of the instruction to build, an operand format | |
2403 | string, and corresponding arguments. */ | |
2404 | ||
1dc1e798 | 2405 | #ifdef USE_STDARG |
3d3c5039 | 2406 | static void |
0dd2d296 ILT |
2407 | macro_build (char *place, |
2408 | int *counter, | |
670a50eb | 2409 | expressionS * ep, |
3d3c5039 ILT |
2410 | const char *name, |
2411 | const char *fmt, | |
2412 | ...) | |
1dc1e798 | 2413 | #else |
3d3c5039 | 2414 | static void |
0dd2d296 ILT |
2415 | macro_build (place, counter, ep, name, fmt, va_alist) |
2416 | char *place; | |
3d3c5039 ILT |
2417 | int *counter; |
2418 | expressionS *ep; | |
2419 | const char *name; | |
2420 | const char *fmt; | |
2421 | va_dcl | |
1dc1e798 | 2422 | #endif |
3d3c5039 | 2423 | { |
670a50eb ILT |
2424 | struct mips_cl_insn insn; |
2425 | bfd_reloc_code_real_type r; | |
2426 | va_list args; | |
931a1858 | 2427 | int insn_isa; |
3d3c5039 | 2428 | |
1dc1e798 | 2429 | #ifdef USE_STDARG |
670a50eb | 2430 | va_start (args, fmt); |
3d3c5039 | 2431 | #else |
670a50eb | 2432 | va_start (args); |
3d3c5039 ILT |
2433 | #endif |
2434 | ||
670a50eb ILT |
2435 | /* |
2436 | * If the macro is about to expand into a second instruction, | |
2437 | * print a warning if needed. We need to pass ip as a parameter | |
2438 | * to generate a better warning message here... | |
2439 | */ | |
3c83da8a | 2440 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2441 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2442 | |
0dd2d296 ILT |
2443 | if (place == NULL) |
2444 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2445 | |
3c83da8a | 2446 | if (mips_opts.mips16) |
cc5703cd ILT |
2447 | { |
2448 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2449 | va_end (args); | |
2450 | return; | |
2451 | } | |
2452 | ||
670a50eb ILT |
2453 | r = BFD_RELOC_UNUSED; |
2454 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2455 | assert (insn.insn_mo); | |
2456 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2457 | ||
931a1858 JL |
2458 | /* Search until we get a match for NAME. */ |
2459 | while (1) | |
670a50eb | 2460 | { |
1c6f3441 | 2461 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2462 | insn_isa = 1; |
2463 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2464 | insn_isa = 2; | |
2465 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2466 | insn_isa = 3; | |
2467 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2468 | insn_isa = 4; | |
2469 | else | |
2470 | insn_isa = 15; | |
2471 | ||
a652f74c ILT |
2472 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2473 | && insn.insn_mo->pinfo != INSN_MACRO | |
2474 | && (insn_isa <= mips_opts.isa | |
2475 | || (mips_4650 | |
2476 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2477 | || (mips_4010 | |
2478 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2479 | || (mips_4100 | |
2480 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
2d035a50 GRK |
2481 | /* start-sanitize-vr4320 */ |
2482 | || (mips_4320 | |
2483 | && (insn.insn_mo->membership & INSN_4320) != 0) | |
2484 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
2485 | /* start-sanitize-tx49 */ |
2486 | || (mips_4900 | |
2487 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2488 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2489 | /* start-sanitize-r5900 */ |
2490 | || (mips_5900 | |
2491 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2492 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
2493 | /* start-sanitize-vr5400 */ |
2494 | || (mips_5400 | |
2495 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
2496 | /* end-sanitize-vr5400 */ | |
a652f74c ILT |
2497 | || (mips_3900 |
2498 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2499 | /* start-sanitize-r5900 */ | |
2500 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2501 | /* end-sanitize-r5900 */ | |
2502 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2503 | break; | |
931a1858 | 2504 | |
a652f74c ILT |
2505 | ++insn.insn_mo; |
2506 | assert (insn.insn_mo->name); | |
2507 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2508 | } |
931a1858 | 2509 | |
670a50eb ILT |
2510 | insn.insn_opcode = insn.insn_mo->match; |
2511 | for (;;) | |
2512 | { | |
2513 | switch (*fmt++) | |
2514 | { | |
3d3c5039 | 2515 | case '\0': |
670a50eb | 2516 | break; |
3d3c5039 ILT |
2517 | |
2518 | case ',': | |
2519 | case '(': | |
2520 | case ')': | |
670a50eb | 2521 | continue; |
3d3c5039 ILT |
2522 | |
2523 | case 't': | |
2524 | case 'w': | |
918692a5 | 2525 | case 'E': |
670a50eb ILT |
2526 | insn.insn_opcode |= va_arg (args, int) << 16; |
2527 | continue; | |
3d3c5039 ILT |
2528 | |
2529 | case 'c': | |
2530 | case 'T': | |
2531 | case 'W': | |
670a50eb ILT |
2532 | insn.insn_opcode |= va_arg (args, int) << 16; |
2533 | continue; | |
3d3c5039 ILT |
2534 | |
2535 | case 'd': | |
918692a5 | 2536 | case 'G': |
670a50eb ILT |
2537 | insn.insn_opcode |= va_arg (args, int) << 11; |
2538 | continue; | |
3d3c5039 ILT |
2539 | |
2540 | case 'V': | |
2541 | case 'S': | |
670a50eb ILT |
2542 | insn.insn_opcode |= va_arg (args, int) << 11; |
2543 | continue; | |
3d3c5039 | 2544 | |
ff3a5c18 ILT |
2545 | case 'z': |
2546 | continue; | |
2547 | ||
3d3c5039 | 2548 | case '<': |
670a50eb ILT |
2549 | insn.insn_opcode |= va_arg (args, int) << 6; |
2550 | continue; | |
3d3c5039 ILT |
2551 | |
2552 | case 'D': | |
670a50eb ILT |
2553 | insn.insn_opcode |= va_arg (args, int) << 6; |
2554 | continue; | |
3d3c5039 | 2555 | |
918692a5 ILT |
2556 | case 'B': |
2557 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2558 | continue; | |
2559 | ||
40f0c904 FCE |
2560 | case 'q': |
2561 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2562 | continue; | |
2563 | ||
3d3c5039 ILT |
2564 | case 'b': |
2565 | case 's': | |
2566 | case 'r': | |
2567 | case 'v': | |
670a50eb ILT |
2568 | insn.insn_opcode |= va_arg (args, int) << 21; |
2569 | continue; | |
3d3c5039 ILT |
2570 | |
2571 | case 'i': | |
2572 | case 'j': | |
2573 | case 'o': | |
9226253a | 2574 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2575 | assert (r == BFD_RELOC_MIPS_GPREL |
2576 | || r == BFD_RELOC_MIPS_LITERAL | |
2577 | || r == BFD_RELOC_LO16 | |
2578 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2579 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2580 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2581 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2582 | || (ep->X_op == O_subtract |
2583 | && now_seg == text_section | |
ecd4ca1c | 2584 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2585 | continue; |
3d3c5039 | 2586 | |
6e8dda9c | 2587 | case 'u': |
ecd4ca1c ILT |
2588 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2589 | assert (ep != NULL | |
2590 | && (ep->X_op == O_constant | |
2591 | || (ep->X_op == O_symbol | |
2592 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2593 | || r == BFD_RELOC_HI16 |
2594 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2595 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2596 | || (ep->X_op == O_subtract |
2597 | && now_seg == text_section | |
ecd4ca1c ILT |
2598 | && r == BFD_RELOC_PCREL_HI16_S))); |
2599 | if (ep->X_op == O_constant) | |
2600 | { | |
2601 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2602 | ep = NULL; | |
2603 | r = BFD_RELOC_UNUSED; | |
2604 | } | |
6e8dda9c ILT |
2605 | continue; |
2606 | ||
3d3c5039 | 2607 | case 'p': |
670a50eb ILT |
2608 | assert (ep != NULL); |
2609 | /* | |
2610 | * This allows macro() to pass an immediate expression for | |
2611 | * creating short branches without creating a symbol. | |
2612 | * Note that the expression still might come from the assembly | |
2613 | * input, in which case the value is not checked for range nor | |
2614 | * is a relocation entry generated (yuck). | |
2615 | */ | |
5ac34ac3 | 2616 | if (ep->X_op == O_constant) |
670a50eb ILT |
2617 | { |
2618 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2619 | ep = NULL; | |
2620 | } | |
2621 | else | |
2622 | r = BFD_RELOC_16_PCREL_S2; | |
2623 | continue; | |
3d3c5039 | 2624 | |
9226253a ILT |
2625 | case 'a': |
2626 | assert (ep != NULL); | |
2627 | r = BFD_RELOC_MIPS_JMP; | |
2628 | continue; | |
2629 | ||
65d2c7d3 JL |
2630 | case 'C': |
2631 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2632 | continue; | |
2633 | ||
3d3c5039 | 2634 | default: |
670a50eb | 2635 | internalError (); |
3d3c5039 | 2636 | } |
670a50eb | 2637 | break; |
3d3c5039 | 2638 | } |
670a50eb ILT |
2639 | va_end (args); |
2640 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2641 | ||
867a58b3 | 2642 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2643 | } |
2644 | ||
cc5703cd ILT |
2645 | static void |
2646 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2647 | char *place; | |
2648 | int *counter; | |
2649 | expressionS *ep; | |
2650 | const char *name; | |
2651 | const char *fmt; | |
2652 | va_list args; | |
2653 | { | |
2654 | struct mips_cl_insn insn; | |
2655 | bfd_reloc_code_real_type r; | |
2656 | ||
2657 | r = BFD_RELOC_UNUSED; | |
2658 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2659 | assert (insn.insn_mo); | |
2660 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2661 | ||
2662 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2663 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2664 | { | |
2665 | ++insn.insn_mo; | |
2666 | assert (insn.insn_mo->name); | |
2667 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2668 | } | |
2669 | ||
2670 | insn.insn_opcode = insn.insn_mo->match; | |
2671 | insn.use_extend = false; | |
2672 | ||
2673 | for (;;) | |
2674 | { | |
2675 | int c; | |
2676 | ||
2677 | c = *fmt++; | |
2678 | switch (c) | |
2679 | { | |
2680 | case '\0': | |
2681 | break; | |
2682 | ||
2683 | case ',': | |
2684 | case '(': | |
2685 | case ')': | |
2686 | continue; | |
2687 | ||
2688 | case 'y': | |
2689 | case 'w': | |
2690 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2691 | continue; | |
2692 | ||
2693 | case 'x': | |
2694 | case 'v': | |
2695 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2696 | continue; | |
2697 | ||
2698 | case 'z': | |
2699 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2700 | continue; | |
2701 | ||
2702 | case 'Z': | |
2703 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2704 | continue; | |
2705 | ||
2706 | case '0': | |
2707 | case 'S': | |
2708 | case 'P': | |
2709 | case 'R': | |
2710 | continue; | |
2711 | ||
2712 | case 'X': | |
2713 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2714 | continue; | |
2715 | ||
2716 | case 'Y': | |
2717 | { | |
2718 | int regno; | |
2719 | ||
2720 | regno = va_arg (args, int); | |
2721 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2722 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2723 | } | |
2724 | continue; | |
2725 | ||
2726 | case '<': | |
2727 | case '>': | |
2728 | case '4': | |
2729 | case '5': | |
2730 | case 'H': | |
2731 | case 'W': | |
2732 | case 'D': | |
2733 | case 'j': | |
2734 | case '8': | |
2735 | case 'V': | |
2736 | case 'C': | |
2737 | case 'U': | |
2738 | case 'k': | |
2739 | case 'K': | |
2740 | case 'p': | |
2741 | case 'q': | |
2742 | { | |
2743 | assert (ep != NULL); | |
2744 | ||
2745 | if (ep->X_op != O_constant) | |
2746 | r = BFD_RELOC_UNUSED + c; | |
2747 | else | |
2748 | { | |
15e69f98 ILT |
2749 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2750 | false, false, &insn.insn_opcode, | |
2751 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2752 | ep = NULL; |
2753 | r = BFD_RELOC_UNUSED; | |
2754 | } | |
2755 | } | |
2756 | continue; | |
2757 | ||
2758 | case '6': | |
2759 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2760 | continue; | |
2761 | } | |
2762 | ||
2763 | break; | |
2764 | } | |
2765 | ||
2766 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2767 | ||
2768 | append_insn (place, &insn, ep, r, false); | |
2769 | } | |
2770 | ||
3d3c5039 ILT |
2771 | /* |
2772 | * Generate a "lui" instruction. | |
2773 | */ | |
2774 | static void | |
0dd2d296 ILT |
2775 | macro_build_lui (place, counter, ep, regnum) |
2776 | char *place; | |
3d3c5039 ILT |
2777 | int *counter; |
2778 | expressionS *ep; | |
2779 | int regnum; | |
2780 | { | |
670a50eb ILT |
2781 | expressionS high_expr; |
2782 | struct mips_cl_insn insn; | |
2783 | bfd_reloc_code_real_type r; | |
2784 | CONST char *name = "lui"; | |
2785 | CONST char *fmt = "t,u"; | |
2786 | ||
3c83da8a | 2787 | assert (! mips_opts.mips16); |
cc5703cd | 2788 | |
0dd2d296 ILT |
2789 | if (place == NULL) |
2790 | high_expr = *ep; | |
2791 | else | |
2792 | { | |
2793 | high_expr.X_op = O_constant; | |
fb251650 | 2794 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2795 | } |
670a50eb | 2796 | |
5ac34ac3 | 2797 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2798 | { |
2799 | /* we can compute the instruction now without a relocation entry */ | |
2800 | if (high_expr.X_add_number & 0x8000) | |
2801 | high_expr.X_add_number += 0x10000; | |
2802 | high_expr.X_add_number = | |
2803 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2804 | r = BFD_RELOC_UNUSED; | |
2805 | } | |
2806 | else | |
0dd2d296 ILT |
2807 | { |
2808 | assert (ep->X_op == O_symbol); | |
2809 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2810 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2811 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2812 | r = BFD_RELOC_HI16_S; | |
2813 | } | |
670a50eb ILT |
2814 | |
2815 | /* | |
2816 | * If the macro is about to expand into a second instruction, | |
2817 | * print a warning if needed. We need to pass ip as a parameter | |
2818 | * to generate a better warning message here... | |
2819 | */ | |
3c83da8a | 2820 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2821 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2822 | |
0dd2d296 ILT |
2823 | if (place == NULL) |
2824 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2825 | |
2826 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2827 | assert (insn.insn_mo); | |
2828 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2829 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2830 | ||
0dd2d296 | 2831 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2832 | if (r == BFD_RELOC_UNUSED) |
2833 | { | |
2834 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2835 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2836 | } |
2837 | else | |
867a58b3 | 2838 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2839 | } |
2840 | ||
2841 | /* set_at() | |
2842 | * Generates code to set the $at register to true (one) | |
2843 | * if reg is less than the immediate expression. | |
2844 | */ | |
2845 | static void | |
6e8dda9c | 2846 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2847 | int *counter; |
2848 | int reg; | |
6e8dda9c | 2849 | int unsignedp; |
3d3c5039 | 2850 | { |
5c6f5923 GRK |
2851 | if (imm_expr.X_op == O_constant |
2852 | && imm_expr.X_add_number >= -0x8000 | |
2853 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2854 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2855 | unsignedp ? "sltiu" : "slti", |
9226253a | 2856 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2857 | else |
670a50eb | 2858 | { |
d8a1c247 | 2859 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2860 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2861 | unsignedp ? "sltu" : "slt", |
2862 | "d,v,t", AT, reg, AT); | |
670a50eb | 2863 | } |
3d3c5039 ILT |
2864 | } |
2865 | ||
6e8dda9c | 2866 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2867 | |
2868 | static void | |
19ed8960 | 2869 | check_absolute_expr (ip, ex) |
3d3c5039 | 2870 | struct mips_cl_insn *ip; |
19ed8960 | 2871 | expressionS *ex; |
3d3c5039 | 2872 | { |
5c6f5923 | 2873 | if (ex->X_op == O_big) |
48401fcf | 2874 | as_bad (_("unsupported large constant")); |
5c6f5923 | 2875 | else if (ex->X_op != O_constant) |
48401fcf | 2876 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
3d3c5039 ILT |
2877 | } |
2878 | ||
ff8716f5 JSC |
2879 | /* Count the leading zeroes by performing a binary chop. This is a |
2880 | bulky bit of source, but performance is a LOT better for the | |
2881 | majority of values than a simple loop to count the bits: | |
2882 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2883 | if ((v) & (1 << (31 - lcnt))) | |
2884 | break; | |
2885 | However it is not code size friendly, and the gain will drop a bit | |
2886 | on certain cached systems. | |
2887 | */ | |
2888 | #define COUNT_TOP_ZEROES(v) \ | |
2889 | (((v) & ~0xffff) == 0 \ | |
2890 | ? ((v) & ~0xff) == 0 \ | |
2891 | ? ((v) & ~0xf) == 0 \ | |
2892 | ? ((v) & ~0x3) == 0 \ | |
2893 | ? ((v) & ~0x1) == 0 \ | |
2894 | ? !(v) \ | |
2895 | ? 32 \ | |
2896 | : 31 \ | |
2897 | : 30 \ | |
2898 | : ((v) & ~0x7) == 0 \ | |
2899 | ? 29 \ | |
2900 | : 28 \ | |
2901 | : ((v) & ~0x3f) == 0 \ | |
2902 | ? ((v) & ~0x1f) == 0 \ | |
2903 | ? 27 \ | |
2904 | : 26 \ | |
2905 | : ((v) & ~0x7f) == 0 \ | |
2906 | ? 25 \ | |
2907 | : 24 \ | |
2908 | : ((v) & ~0xfff) == 0 \ | |
2909 | ? ((v) & ~0x3ff) == 0 \ | |
2910 | ? ((v) & ~0x1ff) == 0 \ | |
2911 | ? 23 \ | |
2912 | : 22 \ | |
2913 | : ((v) & ~0x7ff) == 0 \ | |
2914 | ? 21 \ | |
2915 | : 20 \ | |
2916 | : ((v) & ~0x3fff) == 0 \ | |
2917 | ? ((v) & ~0x1fff) == 0 \ | |
2918 | ? 19 \ | |
2919 | : 18 \ | |
2920 | : ((v) & ~0x7fff) == 0 \ | |
2921 | ? 17 \ | |
2922 | : 16 \ | |
2923 | : ((v) & ~0xffffff) == 0 \ | |
2924 | ? ((v) & ~0xfffff) == 0 \ | |
2925 | ? ((v) & ~0x3ffff) == 0 \ | |
2926 | ? ((v) & ~0x1ffff) == 0 \ | |
2927 | ? 15 \ | |
2928 | : 14 \ | |
2929 | : ((v) & ~0x7ffff) == 0 \ | |
2930 | ? 13 \ | |
2931 | : 12 \ | |
2932 | : ((v) & ~0x3fffff) == 0 \ | |
2933 | ? ((v) & ~0x1fffff) == 0 \ | |
2934 | ? 11 \ | |
2935 | : 10 \ | |
2936 | : ((v) & ~0x7fffff) == 0 \ | |
2937 | ? 9 \ | |
2938 | : 8 \ | |
2939 | : ((v) & ~0xfffffff) == 0 \ | |
2940 | ? ((v) & ~0x3ffffff) == 0 \ | |
2941 | ? ((v) & ~0x1ffffff) == 0 \ | |
2942 | ? 7 \ | |
2943 | : 6 \ | |
2944 | : ((v) & ~0x7ffffff) == 0 \ | |
2945 | ? 5 \ | |
2946 | : 4 \ | |
2947 | : ((v) & ~0x3fffffff) == 0 \ | |
2948 | ? ((v) & ~0x1fffffff) == 0 \ | |
2949 | ? 3 \ | |
2950 | : 2 \ | |
2951 | : ((v) & ~0x7fffffff) == 0 \ | |
2952 | ? 1 \ | |
2953 | : 0) | |
2954 | ||
3d3c5039 ILT |
2955 | /* load_register() |
2956 | * This routine generates the least number of instructions neccessary to load | |
2957 | * an absolute expression value into a register. | |
2958 | */ | |
2959 | static void | |
d8a1c247 | 2960 | load_register (counter, reg, ep, dbl) |
670a50eb | 2961 | int *counter; |
670a50eb ILT |
2962 | int reg; |
2963 | expressionS *ep; | |
d8a1c247 | 2964 | int dbl; |
3d3c5039 | 2965 | { |
c36a90ef ILT |
2966 | int freg; |
2967 | expressionS hi32, lo32; | |
847a01cd ILT |
2968 | |
2969 | if (ep->X_op != O_big) | |
6e8dda9c | 2970 | { |
847a01cd | 2971 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2972 | if (ep->X_add_number < 0x8000 |
2973 | && (ep->X_add_number >= 0 | |
2974 | || (ep->X_add_number >= -0x8000 | |
2975 | && (! dbl | |
2976 | || ! ep->X_unsigned | |
2977 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2978 | { |
2979 | /* We can handle 16 bit signed values with an addiu to | |
2980 | $zero. No need to ever use daddiu here, since $zero and | |
2981 | the result are always correct in 32 bit mode. */ | |
2982 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2983 | (int) BFD_RELOC_LO16); | |
2984 | return; | |
2985 | } | |
2986 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2987 | { | |
2988 | /* We can handle 16 bit unsigned values with an ori to | |
2989 | $zero. */ | |
2990 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2991 | (int) BFD_RELOC_LO16); | |
2992 | return; | |
2993 | } | |
98bfd087 ILT |
2994 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2995 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2996 | == ~ (offsetT) 0x7fffffff)) | |
2997 | && (! dbl | |
2998 | || ! ep->X_unsigned | |
2999 | || sizeof (ep->X_add_number) > 4 | |
3000 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 3001 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 3002 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 3003 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
3004 | && ! dbl |
3005 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3006 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
3007 | { |
3008 | /* 32 bit values require an lui. */ | |
3009 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3010 | (int) BFD_RELOC_HI16); | |
3011 | if ((ep->X_add_number & 0xffff) != 0) | |
3012 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3013 | (int) BFD_RELOC_LO16); | |
3014 | return; | |
3015 | } | |
6e8dda9c | 3016 | } |
847a01cd ILT |
3017 | |
3018 | /* The value is larger than 32 bits. */ | |
3019 | ||
3c83da8a | 3020 | if (mips_opts.isa < 3) |
670a50eb | 3021 | { |
48401fcf | 3022 | as_bad (_("Number larger than 32 bits")); |
0dd2d296 | 3023 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3024 | (int) BFD_RELOC_LO16); |
847a01cd | 3025 | return; |
6e8dda9c | 3026 | } |
6e8dda9c | 3027 | |
847a01cd ILT |
3028 | if (ep->X_op != O_big) |
3029 | { | |
6e8dda9c | 3030 | hi32 = *ep; |
c36a90ef ILT |
3031 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3032 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3033 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3034 | lo32 = *ep; |
3035 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3036 | } |
847a01cd ILT |
3037 | else |
3038 | { | |
3039 | assert (ep->X_add_number > 2); | |
3040 | if (ep->X_add_number == 3) | |
3041 | generic_bignum[3] = 0; | |
3042 | else if (ep->X_add_number > 4) | |
48401fcf | 3043 | as_bad (_("Number larger than 64 bits")); |
847a01cd ILT |
3044 | lo32.X_op = O_constant; |
3045 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3046 | hi32.X_op = O_constant; | |
3047 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3048 | } | |
3049 | ||
d8a1c247 KR |
3050 | if (hi32.X_add_number == 0) |
3051 | freg = 0; | |
3052 | else | |
3053 | { | |
c36a90ef ILT |
3054 | int shift, bit; |
3055 | unsigned long hi, lo; | |
3056 | ||
fb251650 ILT |
3057 | if (hi32.X_add_number == 0xffffffff) |
3058 | { | |
3059 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3060 | { | |
c36a90ef ILT |
3061 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3062 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3063 | return; |
3064 | } | |
3065 | if (lo32.X_add_number & 0x80000000) | |
3066 | { | |
3067 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3068 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3069 | if (lo32.X_add_number & 0xffff) |
3070 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3071 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3072 | return; |
3073 | } | |
3074 | } | |
ff8716f5 | 3075 | |
c36a90ef ILT |
3076 | /* Check for 16bit shifted constant. We know that hi32 is |
3077 | non-zero, so start the mask on the first bit of the hi32 | |
3078 | value. */ | |
ff8716f5 JSC |
3079 | shift = 17; |
3080 | do | |
3081 | { | |
c36a90ef ILT |
3082 | unsigned long himask, lomask; |
3083 | ||
3084 | if (shift < 32) | |
3085 | { | |
3086 | himask = 0xffff >> (32 - shift); | |
3087 | lomask = (0xffff << shift) & 0xffffffff; | |
3088 | } | |
3089 | else | |
3090 | { | |
3091 | himask = 0xffff << (shift - 32); | |
3092 | lomask = 0; | |
3093 | } | |
3094 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3095 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3096 | { | |
3097 | expressionS tmp; | |
3098 | ||
3099 | tmp.X_op = O_constant; | |
3100 | if (shift < 32) | |
3101 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3102 | | (lo32.X_add_number >> shift)); | |
3103 | else | |
3104 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3105 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3106 | (int) BFD_RELOC_LO16); | |
3107 | macro_build ((char *) NULL, counter, NULL, | |
3108 | (shift >= 32) ? "dsll32" : "dsll", | |
3109 | "d,w,<", reg, reg, | |
3110 | (shift >= 32) ? shift - 32 : shift); | |
3111 | return; | |
3112 | } | |
ff8716f5 JSC |
3113 | shift++; |
3114 | } while (shift <= (64 - 16)); | |
3115 | ||
c36a90ef ILT |
3116 | /* Find the bit number of the lowest one bit, and store the |
3117 | shifted value in hi/lo. */ | |
3118 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3119 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3120 | if (lo != 0) | |
3121 | { | |
3122 | bit = 0; | |
3123 | while ((lo & 1) == 0) | |
3124 | { | |
3125 | lo >>= 1; | |
3126 | ++bit; | |
3127 | } | |
3128 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3129 | hi >>= bit; | |
3130 | } | |
3131 | else | |
3132 | { | |
3133 | bit = 32; | |
3134 | while ((hi & 1) == 0) | |
3135 | { | |
3136 | hi >>= 1; | |
3137 | ++bit; | |
3138 | } | |
3139 | lo = hi; | |
3140 | hi = 0; | |
3141 | } | |
3142 | ||
3143 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3144 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3145 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3146 | { |
c36a90ef | 3147 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3148 | if (shift != 0) |
3149 | { | |
c36a90ef ILT |
3150 | expressionS tmp; |
3151 | ||
3152 | /* This instruction will set the register to be all | |
3153 | ones. */ | |
ff8716f5 | 3154 | tmp.X_op = O_constant; |
c36a90ef ILT |
3155 | tmp.X_add_number = (offsetT) -1; |
3156 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3157 | reg, 0, (int) BFD_RELOC_LO16); | |
3158 | if (bit != 0) | |
ff8716f5 | 3159 | { |
c36a90ef | 3160 | bit += shift; |
ff8716f5 | 3161 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3162 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3163 | "d,w,<", reg, reg, |
c36a90ef | 3164 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3165 | } |
c36a90ef ILT |
3166 | macro_build ((char *) NULL, counter, NULL, |
3167 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3168 | "d,w,<", reg, reg, | |
3169 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3170 | return; |
3171 | } | |
3172 | } | |
c36a90ef ILT |
3173 | |
3174 | /* Sign extend hi32 before calling load_register, because we can | |
3175 | generally get better code when we load a sign extended value. */ | |
3176 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3177 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3178 | load_register (counter, reg, &hi32, 0); |
3179 | freg = reg; | |
3180 | } | |
847a01cd | 3181 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3182 | { |
3183 | if (freg != 0) | |
3184 | { | |
3185 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3186 | freg, 0); | |
3187 | freg = reg; | |
3188 | } | |
3189 | } | |
847a01cd ILT |
3190 | else |
3191 | { | |
3192 | expressionS mid16; | |
3193 | ||
fb251650 ILT |
3194 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3195 | { | |
3196 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3197 | (int) BFD_RELOC_HI16); | |
3198 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3199 | reg, 0); |
fb251650 ILT |
3200 | return; |
3201 | } | |
3202 | ||
d8a1c247 KR |
3203 | if (freg != 0) |
3204 | { | |
3205 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3206 | freg, 16); | |
3207 | freg = reg; | |
3208 | } | |
847a01cd ILT |
3209 | mid16 = lo32; |
3210 | mid16.X_add_number >>= 16; | |
3211 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3212 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3213 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3214 | reg, 16); | |
d8a1c247 | 3215 | freg = reg; |
847a01cd ILT |
3216 | } |
3217 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3218 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3219 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3220 | } |
3221 | ||
0dd2d296 ILT |
3222 | /* Load an address into a register. */ |
3223 | ||
3224 | static void | |
3225 | load_address (counter, reg, ep) | |
3226 | int *counter; | |
3227 | int reg; | |
3228 | expressionS *ep; | |
3229 | { | |
3230 | char *p; | |
3231 | ||
3232 | if (ep->X_op != O_constant | |
3233 | && ep->X_op != O_symbol) | |
3234 | { | |
48401fcf | 3235 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
3236 | ep->X_op = O_constant; |
3237 | } | |
3238 | ||
3239 | if (ep->X_op == O_constant) | |
d9aba805 | 3240 | { |
d8a1c247 | 3241 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3242 | return; |
3243 | } | |
3244 | ||
3245 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3246 | { |
3247 | /* If this is a reference to a GP relative symbol, we want | |
3248 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3249 | Otherwise we want | |
04cb3372 | 3250 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3251 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3252 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3253 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3254 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3255 | p = NULL; |
3256 | else | |
3257 | { | |
8ea7f4e8 | 3258 | frag_grow (20); |
0dd2d296 | 3259 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3260 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3261 | || mips_opts.isa < 3) | |
3262 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3263 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3264 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3265 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3266 | mips_opts.warn_about_macros), | |
f59fb6ca | 3267 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3268 | } |
3269 | macro_build_lui (p, counter, ep, reg); | |
3270 | if (p != NULL) | |
3271 | p += 4; | |
3272 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3273 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3274 | || mips_opts.isa < 3) | |
3275 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3276 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3277 | } | |
fb251650 | 3278 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3279 | { |
3280 | expressionS ex; | |
3281 | ||
3282 | /* If this is a reference to an external symbol, we want | |
3283 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3284 | Otherwise we want | |
3285 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3286 | nop | |
3287 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3288 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3289 | ex.X_add_number = ep->X_add_number; |
3290 | ep->X_add_number = 0; | |
8ea7f4e8 | 3291 | frag_grow (20); |
0dd2d296 | 3292 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3293 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3294 | || mips_opts.isa < 3) | |
3295 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3296 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3297 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3298 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3299 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3300 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3301 | macro_build (p, counter, ep, |
9a1f3160 JL |
3302 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3303 | || mips_opts.isa < 3) | |
3304 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3305 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3306 | if (ex.X_add_number != 0) | |
3307 | { | |
3308 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3309 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 | 3310 | ex.X_op = O_constant; |
fb251650 | 3311 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3312 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3313 | || mips_opts.isa < 3) | |
3314 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3315 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3316 | } | |
3317 | } | |
3318 | else if (mips_pic == SVR4_PIC) | |
3319 | { | |
3320 | expressionS ex; | |
3321 | int off; | |
3322 | ||
3323 | /* This is the large GOT case. If this is a reference to an | |
3324 | external symbol, we want | |
3325 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3326 | addu $reg,$reg,$gp | |
3327 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3328 | Otherwise, for a reference to a local symbol, we want | |
3329 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3330 | nop | |
3331 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3332 | If there is a constant, it must be added in after. */ | |
3333 | ex.X_add_number = ep->X_add_number; | |
3334 | ep->X_add_number = 0; | |
3335 | if (reg_needs_delay (GP)) | |
3336 | off = 4; | |
3337 | else | |
3338 | off = 0; | |
3339 | frag_grow (32); | |
3340 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3341 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3342 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3343 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3344 | || mips_opts.isa < 3) | |
3345 | ? "addu" : "daddu"), | |
fb251650 ILT |
3346 | "d,v,t", reg, reg, GP); |
3347 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3348 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3349 | || mips_opts.isa < 3) | |
3350 | ? "lw" : "ld"), | |
fb251650 ILT |
3351 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3352 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3353 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3354 | mips_opts.warn_about_macros), |
f59fb6ca | 3355 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3356 | if (off > 0) |
3357 | { | |
3358 | /* We need a nop before loading from $gp. This special | |
3359 | check is required because the lui which starts the main | |
3360 | instruction stream does not refer to $gp, and so will not | |
3361 | insert the nop which may be required. */ | |
3362 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3363 | p += 4; | |
3364 | } | |
3365 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3366 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3367 | || mips_opts.isa < 3) | |
3368 | ? "lw" : "ld"), | |
fb251650 ILT |
3369 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3370 | p += 4; | |
3371 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3372 | p += 4; | |
3373 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3374 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3375 | || mips_opts.isa < 3) | |
3376 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3377 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3378 | if (ex.X_add_number != 0) | |
3379 | { | |
3380 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3381 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
3382 | ex.X_op = O_constant; |
3383 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3384 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3385 | || mips_opts.isa < 3) | |
3386 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3387 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3388 | } | |
d9aba805 ILT |
3389 | } |
3390 | else if (mips_pic == EMBEDDED_PIC) | |
3391 | { | |
3392 | /* We always do | |
3393 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3394 | */ | |
3395 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3396 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3397 | || mips_opts.isa < 3) | |
3398 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3399 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3400 | } | |
3401 | else | |
3402 | abort (); | |
0dd2d296 ILT |
3403 | } |
3404 | ||
3d3c5039 ILT |
3405 | /* |
3406 | * Build macros | |
3407 | * This routine implements the seemingly endless macro or synthesized | |
3408 | * instructions and addressing modes in the mips assembly language. Many | |
3409 | * of these macros are simple and are similar to each other. These could | |
3410 | * probably be handled by some kind of table or grammer aproach instead of | |
3411 | * this verbose method. Others are not simple macros but are more like | |
3412 | * optimizing code generation. | |
3413 | * One interesting optimization is when several store macros appear | |
3414 | * consecutivly that would load AT with the upper half of the same address. | |
3415 | * The ensuing load upper instructions are ommited. This implies some kind | |
3416 | * of global optimization. We currently only optimize within a single macro. | |
3417 | * For many of the load and store macros if the address is specified as a | |
3418 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3419 | * first load register 'at' with zero and use it as the base register. The | |
3420 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3421 | * we're missing. | |
3422 | */ | |
3423 | static void | |
3424 | macro (ip) | |
3425 | struct mips_cl_insn *ip; | |
3426 | { | |
670a50eb ILT |
3427 | register int treg, sreg, dreg, breg; |
3428 | int tempreg; | |
3429 | int mask; | |
3430 | int icnt = 0; | |
3431 | int used_at; | |
670a50eb ILT |
3432 | expressionS expr1; |
3433 | const char *s; | |
8358c818 | 3434 | const char *s2; |
670a50eb | 3435 | const char *fmt; |
8358c818 ILT |
3436 | int likely = 0; |
3437 | int dbl = 0; | |
3438 | int coproc = 0; | |
b2b8c24e | 3439 | int lr = 0; |
40f0c904 | 3440 | int imm = 0; |
6e8dda9c | 3441 | offsetT maxnum; |
adcf2b9d | 3442 | int off; |
9226253a | 3443 | bfd_reloc_code_real_type r; |
0dd2d296 | 3444 | char *p; |
55933a58 | 3445 | int hold_mips_optimize; |
670a50eb | 3446 | |
3c83da8a | 3447 | assert (! mips_opts.mips16); |
cc5703cd | 3448 | |
670a50eb ILT |
3449 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3450 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3451 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3452 | mask = ip->insn_mo->mask; | |
3453 | ||
5ac34ac3 ILT |
3454 | expr1.X_op = O_constant; |
3455 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3456 | expr1.X_add_symbol = NULL; |
3457 | expr1.X_add_number = 1; | |
3458 | ||
3459 | switch (mask) | |
3460 | { | |
6e8dda9c ILT |
3461 | case M_DABS: |
3462 | dbl = 1; | |
3d3c5039 | 3463 | case M_ABS: |
6e8dda9c ILT |
3464 | /* bgez $a0,.+12 |
3465 | move v0,$a0 | |
3466 | sub v0,$zero,$a0 | |
3467 | */ | |
3d3c5039 | 3468 | |
fbcfacb7 | 3469 | mips_emit_delays (true); |
3c83da8a | 3470 | ++mips_opts.noreorder; |
0dd2d296 | 3471 | mips_any_noreorder = 1; |
3d3c5039 | 3472 | |
670a50eb | 3473 | expr1.X_add_number = 8; |
0dd2d296 | 3474 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3475 | if (dreg == sreg) |
0dd2d296 | 3476 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3477 | else |
0dd2d296 ILT |
3478 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3479 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3480 | dbl ? "dsub" : "sub", |
3481 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3482 | |
3c83da8a | 3483 | --mips_opts.noreorder; |
670a50eb | 3484 | return; |
3d3c5039 ILT |
3485 | |
3486 | case M_ADD_I: | |
8358c818 ILT |
3487 | s = "addi"; |
3488 | s2 = "add"; | |
3489 | goto do_addi; | |
3d3c5039 | 3490 | case M_ADDU_I: |
8358c818 ILT |
3491 | s = "addiu"; |
3492 | s2 = "addu"; | |
3493 | goto do_addi; | |
3494 | case M_DADD_I: | |
6e8dda9c | 3495 | dbl = 1; |
8358c818 ILT |
3496 | s = "daddi"; |
3497 | s2 = "dadd"; | |
3498 | goto do_addi; | |
3499 | case M_DADDU_I: | |
6e8dda9c | 3500 | dbl = 1; |
8358c818 ILT |
3501 | s = "daddiu"; |
3502 | s2 = "daddu"; | |
3503 | do_addi: | |
5c6f5923 GRK |
3504 | if (imm_expr.X_op == O_constant |
3505 | && imm_expr.X_add_number >= -0x8000 | |
3506 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3507 | { |
0dd2d296 | 3508 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3509 | (int) BFD_RELOC_LO16); |
670a50eb | 3510 | return; |
3d3c5039 | 3511 | } |
d8a1c247 | 3512 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3513 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3514 | break; |
3d3c5039 ILT |
3515 | |
3516 | case M_AND_I: | |
6e8dda9c ILT |
3517 | s = "andi"; |
3518 | s2 = "and"; | |
3519 | goto do_bit; | |
3d3c5039 | 3520 | case M_OR_I: |
6e8dda9c ILT |
3521 | s = "ori"; |
3522 | s2 = "or"; | |
3523 | goto do_bit; | |
3d3c5039 | 3524 | case M_NOR_I: |
6e8dda9c ILT |
3525 | s = ""; |
3526 | s2 = "nor"; | |
3527 | goto do_bit; | |
3d3c5039 | 3528 | case M_XOR_I: |
6e8dda9c ILT |
3529 | s = "xori"; |
3530 | s2 = "xor"; | |
3531 | do_bit: | |
5c6f5923 GRK |
3532 | if (imm_expr.X_op == O_constant |
3533 | && imm_expr.X_add_number >= 0 | |
3534 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3535 | { |
6e8dda9c | 3536 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3537 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3538 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3539 | else |
670a50eb | 3540 | { |
0dd2d296 ILT |
3541 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3542 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3543 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3544 | treg, treg, 0); |
3d3c5039 | 3545 | } |
6e8dda9c | 3546 | return; |
3d3c5039 | 3547 | } |
6e8dda9c | 3548 | |
d8a1c247 | 3549 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3550 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3551 | break; |
3d3c5039 ILT |
3552 | |
3553 | case M_BEQ_I: | |
8358c818 ILT |
3554 | s = "beq"; |
3555 | goto beq_i; | |
3556 | case M_BEQL_I: | |
3557 | s = "beql"; | |
3558 | likely = 1; | |
3559 | goto beq_i; | |
3d3c5039 | 3560 | case M_BNE_I: |
8358c818 ILT |
3561 | s = "bne"; |
3562 | goto beq_i; | |
3563 | case M_BNEL_I: | |
3564 | s = "bnel"; | |
3565 | likely = 1; | |
3566 | beq_i: | |
5c6f5923 | 3567 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3568 | { |
0dd2d296 ILT |
3569 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3570 | 0); | |
670a50eb ILT |
3571 | return; |
3572 | } | |
d8a1c247 | 3573 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3574 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3575 | break; |
3d3c5039 | 3576 | |
8358c818 ILT |
3577 | case M_BGEL: |
3578 | likely = 1; | |
3d3c5039 | 3579 | case M_BGE: |
670a50eb ILT |
3580 | if (treg == 0) |
3581 | { | |
0dd2d296 | 3582 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3583 | likely ? "bgezl" : "bgez", |
3584 | "s,p", sreg); | |
670a50eb | 3585 | return; |
3d3c5039 | 3586 | } |
9a7d824a ILT |
3587 | if (sreg == 0) |
3588 | { | |
0dd2d296 | 3589 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3590 | likely ? "blezl" : "blez", |
3591 | "s,p", treg); | |
9a7d824a ILT |
3592 | return; |
3593 | } | |
0dd2d296 ILT |
3594 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3595 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3596 | likely ? "beql" : "beq", |
3597 | "s,t,p", AT, 0); | |
670a50eb | 3598 | break; |
3d3c5039 | 3599 | |
8358c818 ILT |
3600 | case M_BGTL_I: |
3601 | likely = 1; | |
3d3c5039 | 3602 | case M_BGT_I: |
9a7d824a | 3603 | /* check for > max integer */ |
6e8dda9c | 3604 | maxnum = 0x7fffffff; |
5c6f5923 | 3605 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3606 | { |
3607 | maxnum <<= 16; | |
3608 | maxnum |= 0xffff; | |
3609 | maxnum <<= 16; | |
3610 | maxnum |= 0xffff; | |
3611 | } | |
5c6f5923 GRK |
3612 | if (imm_expr.X_op == O_constant |
3613 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3614 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3615 | { |
3616 | do_false: | |
3617 | /* result is always false */ | |
8358c818 ILT |
3618 | if (! likely) |
3619 | { | |
48401fcf | 3620 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); |
0dd2d296 | 3621 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3622 | } |
3623 | else | |
3624 | { | |
48401fcf | 3625 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); |
0dd2d296 ILT |
3626 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3627 | "s,t,p", 0, 0); | |
8358c818 | 3628 | } |
9a7d824a ILT |
3629 | return; |
3630 | } | |
5c6f5923 | 3631 | if (imm_expr.X_op != O_constant) |
48401fcf | 3632 | as_bad (_("Unsupported large constant")); |
670a50eb ILT |
3633 | imm_expr.X_add_number++; |
3634 | /* FALLTHROUGH */ | |
3d3c5039 | 3635 | case M_BGE_I: |
8358c818 ILT |
3636 | case M_BGEL_I: |
3637 | if (mask == M_BGEL_I) | |
3638 | likely = 1; | |
5c6f5923 | 3639 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3640 | { |
0dd2d296 | 3641 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3642 | likely ? "bgezl" : "bgez", |
3643 | "s,p", sreg); | |
670a50eb | 3644 | return; |
3d3c5039 | 3645 | } |
5c6f5923 | 3646 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3647 | { |
0dd2d296 | 3648 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3649 | likely ? "bgtzl" : "bgtz", |
3650 | "s,p", sreg); | |
670a50eb | 3651 | return; |
3d3c5039 | 3652 | } |
6e8dda9c | 3653 | maxnum = 0x7fffffff; |
5c6f5923 | 3654 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3655 | { |
3656 | maxnum <<= 16; | |
3657 | maxnum |= 0xffff; | |
3658 | maxnum <<= 16; | |
3659 | maxnum |= 0xffff; | |
3660 | } | |
3661 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3662 | if (imm_expr.X_op == O_constant |
3663 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3664 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3665 | { |
3666 | do_true: | |
3667 | /* result is always true */ | |
48401fcf | 3668 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
0dd2d296 | 3669 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3670 | return; |
3671 | } | |
6e8dda9c | 3672 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3673 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3674 | likely ? "beql" : "beq", |
3675 | "s,t,p", AT, 0); | |
670a50eb | 3676 | break; |
3d3c5039 | 3677 | |
8358c818 ILT |
3678 | case M_BGEUL: |
3679 | likely = 1; | |
3d3c5039 | 3680 | case M_BGEU: |
670a50eb | 3681 | if (treg == 0) |
9a7d824a ILT |
3682 | goto do_true; |
3683 | if (sreg == 0) | |
670a50eb | 3684 | { |
0dd2d296 | 3685 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3686 | likely ? "beql" : "beq", |
3687 | "s,t,p", 0, treg); | |
670a50eb | 3688 | return; |
3d3c5039 | 3689 | } |
0dd2d296 ILT |
3690 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3691 | treg); | |
3692 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3693 | likely ? "beql" : "beq", |
3694 | "s,t,p", AT, 0); | |
670a50eb | 3695 | break; |
3d3c5039 | 3696 | |
8358c818 ILT |
3697 | case M_BGTUL_I: |
3698 | likely = 1; | |
9a7d824a | 3699 | case M_BGTU_I: |
5c6f5923 GRK |
3700 | if (sreg == 0 |
3701 | || (mips_opts.isa < 3 | |
3702 | && imm_expr.X_op == O_constant | |
3703 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3704 | goto do_false; |
5c6f5923 | 3705 | if (imm_expr.X_op != O_constant) |
48401fcf | 3706 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3707 | imm_expr.X_add_number++; |
3708 | /* FALLTHROUGH */ | |
3d3c5039 | 3709 | case M_BGEU_I: |
8358c818 ILT |
3710 | case M_BGEUL_I: |
3711 | if (mask == M_BGEUL_I) | |
3712 | likely = 1; | |
5c6f5923 | 3713 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3714 | goto do_true; |
5c6f5923 | 3715 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3716 | { |
0dd2d296 | 3717 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3718 | likely ? "bnel" : "bne", |
3719 | "s,t,p", sreg, 0); | |
670a50eb | 3720 | return; |
3d3c5039 | 3721 | } |
6e8dda9c | 3722 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3723 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3724 | likely ? "beql" : "beq", |
3725 | "s,t,p", AT, 0); | |
670a50eb | 3726 | break; |
3d3c5039 | 3727 | |
8358c818 ILT |
3728 | case M_BGTL: |
3729 | likely = 1; | |
3d3c5039 | 3730 | case M_BGT: |
670a50eb ILT |
3731 | if (treg == 0) |
3732 | { | |
0dd2d296 | 3733 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3734 | likely ? "bgtzl" : "bgtz", |
3735 | "s,p", sreg); | |
670a50eb | 3736 | return; |
3d3c5039 | 3737 | } |
9a7d824a ILT |
3738 | if (sreg == 0) |
3739 | { | |
0dd2d296 | 3740 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3741 | likely ? "bltzl" : "bltz", |
3742 | "s,p", treg); | |
9a7d824a ILT |
3743 | return; |
3744 | } | |
0dd2d296 ILT |
3745 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3746 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3747 | likely ? "bnel" : "bne", |
3748 | "s,t,p", AT, 0); | |
670a50eb | 3749 | break; |
3d3c5039 | 3750 | |
8358c818 ILT |
3751 | case M_BGTUL: |
3752 | likely = 1; | |
3d3c5039 | 3753 | case M_BGTU: |
670a50eb ILT |
3754 | if (treg == 0) |
3755 | { | |
0dd2d296 | 3756 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3757 | likely ? "bnel" : "bne", |
3758 | "s,t,p", sreg, 0); | |
670a50eb | 3759 | return; |
3d3c5039 | 3760 | } |
9a7d824a ILT |
3761 | if (sreg == 0) |
3762 | goto do_false; | |
0dd2d296 ILT |
3763 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3764 | sreg); | |
3765 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3766 | likely ? "bnel" : "bne", |
3767 | "s,t,p", AT, 0); | |
670a50eb | 3768 | break; |
3d3c5039 | 3769 | |
8358c818 ILT |
3770 | case M_BLEL: |
3771 | likely = 1; | |
3d3c5039 | 3772 | case M_BLE: |
670a50eb ILT |
3773 | if (treg == 0) |
3774 | { | |
0dd2d296 | 3775 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3776 | likely ? "blezl" : "blez", |
3777 | "s,p", sreg); | |
670a50eb ILT |
3778 | return; |
3779 | } | |
9a7d824a ILT |
3780 | if (sreg == 0) |
3781 | { | |
0dd2d296 | 3782 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3783 | likely ? "bgezl" : "bgez", |
3784 | "s,p", treg); | |
9a7d824a ILT |
3785 | return; |
3786 | } | |
0dd2d296 ILT |
3787 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3788 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3789 | likely ? "beql" : "beq", |
3790 | "s,t,p", AT, 0); | |
670a50eb | 3791 | break; |
3d3c5039 | 3792 | |
8358c818 ILT |
3793 | case M_BLEL_I: |
3794 | likely = 1; | |
3d3c5039 | 3795 | case M_BLE_I: |
6e8dda9c | 3796 | maxnum = 0x7fffffff; |
5c6f5923 | 3797 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3798 | { |
3799 | maxnum <<= 16; | |
3800 | maxnum |= 0xffff; | |
3801 | maxnum <<= 16; | |
3802 | maxnum |= 0xffff; | |
3803 | } | |
5c6f5923 GRK |
3804 | if (imm_expr.X_op == O_constant |
3805 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3806 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3807 | goto do_true; |
5c6f5923 | 3808 | if (imm_expr.X_op != O_constant) |
48401fcf | 3809 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3810 | imm_expr.X_add_number++; |
3811 | /* FALLTHROUGH */ | |
9a7d824a | 3812 | case M_BLT_I: |
8358c818 ILT |
3813 | case M_BLTL_I: |
3814 | if (mask == M_BLTL_I) | |
3815 | likely = 1; | |
5c6f5923 | 3816 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3817 | { |
0dd2d296 | 3818 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3819 | likely ? "bltzl" : "bltz", |
3820 | "s,p", sreg); | |
670a50eb ILT |
3821 | return; |
3822 | } | |
5c6f5923 | 3823 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3824 | { |
0dd2d296 | 3825 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3826 | likely ? "blezl" : "blez", |
3827 | "s,p", sreg); | |
670a50eb ILT |
3828 | return; |
3829 | } | |
6e8dda9c | 3830 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3831 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3832 | likely ? "bnel" : "bne", |
3833 | "s,t,p", AT, 0); | |
670a50eb | 3834 | break; |
3d3c5039 | 3835 | |
8358c818 ILT |
3836 | case M_BLEUL: |
3837 | likely = 1; | |
3d3c5039 | 3838 | case M_BLEU: |
670a50eb ILT |
3839 | if (treg == 0) |
3840 | { | |
0dd2d296 | 3841 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3842 | likely ? "beql" : "beq", |
3843 | "s,t,p", sreg, 0); | |
670a50eb | 3844 | return; |
3d3c5039 | 3845 | } |
9a7d824a ILT |
3846 | if (sreg == 0) |
3847 | goto do_true; | |
0dd2d296 ILT |
3848 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3849 | sreg); | |
3850 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3851 | likely ? "beql" : "beq", |
3852 | "s,t,p", AT, 0); | |
670a50eb | 3853 | break; |
3d3c5039 | 3854 | |
8358c818 ILT |
3855 | case M_BLEUL_I: |
3856 | likely = 1; | |
3d3c5039 | 3857 | case M_BLEU_I: |
5c6f5923 GRK |
3858 | if (sreg == 0 |
3859 | || (mips_opts.isa < 3 | |
3860 | && imm_expr.X_op == O_constant | |
3861 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3862 | goto do_true; |
5c6f5923 | 3863 | if (imm_expr.X_op != O_constant) |
48401fcf | 3864 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3865 | imm_expr.X_add_number++; |
3866 | /* FALLTHROUGH */ | |
9a7d824a | 3867 | case M_BLTU_I: |
8358c818 ILT |
3868 | case M_BLTUL_I: |
3869 | if (mask == M_BLTUL_I) | |
3870 | likely = 1; | |
5c6f5923 | 3871 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3872 | goto do_false; |
5c6f5923 | 3873 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3874 | { |
0dd2d296 | 3875 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3876 | likely ? "beql" : "beq", |
3877 | "s,t,p", sreg, 0); | |
670a50eb | 3878 | return; |
3d3c5039 | 3879 | } |
6e8dda9c | 3880 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3881 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3882 | likely ? "bnel" : "bne", |
3883 | "s,t,p", AT, 0); | |
670a50eb | 3884 | break; |
3d3c5039 | 3885 | |
8358c818 ILT |
3886 | case M_BLTL: |
3887 | likely = 1; | |
3d3c5039 | 3888 | case M_BLT: |
670a50eb ILT |
3889 | if (treg == 0) |
3890 | { | |
0dd2d296 | 3891 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3892 | likely ? "bltzl" : "bltz", |
3893 | "s,p", sreg); | |
670a50eb | 3894 | return; |
3d3c5039 | 3895 | } |
9a7d824a | 3896 | if (sreg == 0) |
670a50eb | 3897 | { |
0dd2d296 | 3898 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3899 | likely ? "bgtzl" : "bgtz", |
3900 | "s,p", treg); | |
670a50eb | 3901 | return; |
3d3c5039 | 3902 | } |
0dd2d296 ILT |
3903 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3904 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3905 | likely ? "bnel" : "bne", |
3906 | "s,t,p", AT, 0); | |
670a50eb | 3907 | break; |
3d3c5039 | 3908 | |
8358c818 ILT |
3909 | case M_BLTUL: |
3910 | likely = 1; | |
3d3c5039 | 3911 | case M_BLTU: |
670a50eb | 3912 | if (treg == 0) |
9a7d824a ILT |
3913 | goto do_false; |
3914 | if (sreg == 0) | |
670a50eb | 3915 | { |
0dd2d296 | 3916 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3917 | likely ? "bnel" : "bne", |
3918 | "s,t,p", 0, treg); | |
670a50eb ILT |
3919 | return; |
3920 | } | |
0dd2d296 ILT |
3921 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3922 | treg); | |
3923 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3924 | likely ? "bnel" : "bne", |
3925 | "s,t,p", AT, 0); | |
670a50eb | 3926 | break; |
3d3c5039 | 3927 | |
8358c818 ILT |
3928 | case M_DDIV_3: |
3929 | dbl = 1; | |
3d3c5039 | 3930 | case M_DIV_3: |
8358c818 ILT |
3931 | s = "mflo"; |
3932 | goto do_div3; | |
3933 | case M_DREM_3: | |
3934 | dbl = 1; | |
3d3c5039 | 3935 | case M_REM_3: |
8358c818 ILT |
3936 | s = "mfhi"; |
3937 | do_div3: | |
670a50eb ILT |
3938 | if (treg == 0) |
3939 | { | |
48401fcf | 3940 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
3941 | if (mips_trap) |
3942 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3943 | else | |
d9c2c0c5 FCE |
3944 | /* start-sanitize-r5900 */ |
3945 | if (mips_5900) | |
3946 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
3947 | else | |
3948 | /* end-sanitize-r5900 */ | |
3949 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3950 | return; |
3951 | } | |
3952 | ||
fbcfacb7 | 3953 | mips_emit_delays (true); |
3c83da8a | 3954 | ++mips_opts.noreorder; |
0dd2d296 | 3955 | mips_any_noreorder = 1; |
8ea7f4e8 | 3956 | if (mips_trap) |
6c4b811d JL |
3957 | { |
3958 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3959 | macro_build ((char *) NULL, &icnt, NULL, | |
3960 | dbl ? "ddiv" : "div", | |
3961 | "z,s,t", sreg, treg); | |
3962 | } | |
8ea7f4e8 ILT |
3963 | else |
3964 | { | |
3965 | expr1.X_add_number = 8; | |
3966 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
3967 | macro_build ((char *) NULL, &icnt, NULL, |
3968 | dbl ? "ddiv" : "div", | |
3969 | "z,s,t", sreg, treg); | |
d9c2c0c5 FCE |
3970 | /* start-sanitize-r5900 */ |
3971 | if (mips_5900) | |
3972 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
3973 | else | |
3974 | /* end-sanitize-r5900 */ | |
3975 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 3976 | } |
670a50eb | 3977 | expr1.X_add_number = -1; |
0dd2d296 | 3978 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3979 | dbl ? "daddiu" : "addiu", |
9226253a | 3980 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3981 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3982 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3983 | if (dbl) |
3984 | { | |
3985 | expr1.X_add_number = 1; | |
0dd2d296 | 3986 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3987 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3988 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3989 | 31); | |
8358c818 ILT |
3990 | } |
3991 | else | |
3992 | { | |
3993 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3994 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3995 | (int) BFD_RELOC_HI16); | |
8358c818 | 3996 | } |
8ea7f4e8 ILT |
3997 | if (mips_trap) |
3998 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3999 | else | |
4000 | { | |
4001 | expr1.X_add_number = 8; | |
4002 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4003 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
4004 | |
4005 | /* start-sanitize-r5900 */ | |
4006 | if (mips_5900) | |
4007 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
4008 | else | |
4009 | /* end-sanitize-r5900 */ | |
4010 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 4011 | } |
3c83da8a | 4012 | --mips_opts.noreorder; |
0dd2d296 | 4013 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 4014 | break; |
3d3c5039 ILT |
4015 | |
4016 | case M_DIV_3I: | |
8358c818 ILT |
4017 | s = "div"; |
4018 | s2 = "mflo"; | |
4019 | goto do_divi; | |
3d3c5039 | 4020 | case M_DIVU_3I: |
8358c818 ILT |
4021 | s = "divu"; |
4022 | s2 = "mflo"; | |
4023 | goto do_divi; | |
3d3c5039 | 4024 | case M_REM_3I: |
8358c818 ILT |
4025 | s = "div"; |
4026 | s2 = "mfhi"; | |
4027 | goto do_divi; | |
3d3c5039 | 4028 | case M_REMU_3I: |
8358c818 ILT |
4029 | s = "divu"; |
4030 | s2 = "mfhi"; | |
4031 | goto do_divi; | |
4032 | case M_DDIV_3I: | |
4033 | dbl = 1; | |
4034 | s = "ddiv"; | |
4035 | s2 = "mflo"; | |
4036 | goto do_divi; | |
4037 | case M_DDIVU_3I: | |
4038 | dbl = 1; | |
4039 | s = "ddivu"; | |
4040 | s2 = "mflo"; | |
4041 | goto do_divi; | |
4042 | case M_DREM_3I: | |
4043 | dbl = 1; | |
4044 | s = "ddiv"; | |
4045 | s2 = "mfhi"; | |
4046 | goto do_divi; | |
4047 | case M_DREMU_3I: | |
4048 | dbl = 1; | |
4049 | s = "ddivu"; | |
4050 | s2 = "mfhi"; | |
4051 | do_divi: | |
5c6f5923 | 4052 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 4053 | { |
48401fcf | 4054 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4055 | if (mips_trap) |
4056 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4057 | else | |
d9c2c0c5 FCE |
4058 | /* start-sanitize-r5900 */ |
4059 | if (mips_5900) | |
4060 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4061 | else | |
4062 | /* end-sanitize-r5900 */ | |
4063 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4064 | return; |
4065 | } | |
5c6f5923 | 4066 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4067 | { |
8358c818 | 4068 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4069 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4070 | sreg); | |
3d3c5039 | 4071 | else |
0dd2d296 | 4072 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4073 | return; |
4074 | } | |
5c6f5923 GRK |
4075 | if (imm_expr.X_op == O_constant |
4076 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4077 | && s[strlen (s) - 1] != 'u') |
4078 | { | |
4079 | if (strcmp (s2, "mflo") == 0) | |
4080 | { | |
4081 | if (dbl) | |
0dd2d296 ILT |
4082 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4083 | sreg); | |
8358c818 | 4084 | else |
0dd2d296 ILT |
4085 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4086 | sreg); | |
8358c818 ILT |
4087 | } |
4088 | else | |
0dd2d296 | 4089 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4090 | return; |
4091 | } | |
3d3c5039 | 4092 | |
d8a1c247 | 4093 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4094 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4095 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4096 | break; |
4097 | ||
4098 | case M_DIVU_3: | |
8358c818 ILT |
4099 | s = "divu"; |
4100 | s2 = "mflo"; | |
4101 | goto do_divu3; | |
670a50eb | 4102 | case M_REMU_3: |
8358c818 ILT |
4103 | s = "divu"; |
4104 | s2 = "mfhi"; | |
4105 | goto do_divu3; | |
4106 | case M_DDIVU_3: | |
4107 | s = "ddivu"; | |
4108 | s2 = "mflo"; | |
4109 | goto do_divu3; | |
4110 | case M_DREMU_3: | |
4111 | s = "ddivu"; | |
4112 | s2 = "mfhi"; | |
4113 | do_divu3: | |
fbcfacb7 | 4114 | mips_emit_delays (true); |
3c83da8a | 4115 | ++mips_opts.noreorder; |
0dd2d296 | 4116 | mips_any_noreorder = 1; |
8ea7f4e8 | 4117 | if (mips_trap) |
6c4b811d JL |
4118 | { |
4119 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4120 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4121 | } | |
8ea7f4e8 ILT |
4122 | else |
4123 | { | |
4124 | expr1.X_add_number = 8; | |
4125 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4126 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
d9c2c0c5 FCE |
4127 | /* start-sanitize-r5900 */ |
4128 | if (mips_5900) | |
4129 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
4130 | else | |
4131 | /* end-sanitize-r5900 */ | |
4132 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4133 | } |
3c83da8a | 4134 | --mips_opts.noreorder; |
0dd2d296 | 4135 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4136 | return; |
3d3c5039 | 4137 | |
d8a1c247 KR |
4138 | case M_DLA_AB: |
4139 | dbl = 1; | |
0dd2d296 | 4140 | case M_LA_AB: |
d9aba805 ILT |
4141 | /* Load the address of a symbol into a register. If breg is not |
4142 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4143 | |
4144 | /* When generating embedded PIC code, we permit expressions of | |
4145 | the form | |
4146 | la $4,foo-bar | |
4147 | where bar is an address in the .text section. These are used | |
4148 | when getting the addresses of functions. We don't permit | |
4149 | X_add_number to be non-zero, because if the symbol is | |
4150 | external the relaxing code needs to know that any addend is | |
4151 | purely the offset to X_op_symbol. */ | |
4152 | if (mips_pic == EMBEDDED_PIC | |
4153 | && offset_expr.X_op == O_subtract | |
4154 | && now_seg == text_section | |
847a01cd ILT |
4155 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4156 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4157 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4158 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4159 | ->sy_value.X_add_symbol) | |
4160 | == text_section))) | |
ecd4ca1c ILT |
4161 | && breg == 0 |
4162 | && offset_expr.X_add_number == 0) | |
4163 | { | |
4164 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4165 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4166 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4167 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4168 | || mips_opts.isa < 3) | |
4169 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4170 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4171 | return; | |
4172 | } | |
4173 | ||
0dd2d296 ILT |
4174 | if (offset_expr.X_op != O_symbol |
4175 | && offset_expr.X_op != O_constant) | |
670a50eb | 4176 | { |
48401fcf | 4177 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
4178 | offset_expr.X_op = O_constant; |
4179 | } | |
4180 | ||
4181 | if (treg == breg) | |
4182 | { | |
4183 | tempreg = AT; | |
4184 | used_at = 1; | |
3d3c5039 | 4185 | } |
670a50eb ILT |
4186 | else |
4187 | { | |
0dd2d296 ILT |
4188 | tempreg = treg; |
4189 | used_at = 0; | |
670a50eb | 4190 | } |
3d3c5039 | 4191 | |
5ac34ac3 | 4192 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4193 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4194 | else if (mips_pic == NO_PIC) |
670a50eb | 4195 | { |
0dd2d296 ILT |
4196 | /* If this is a reference to an GP relative symbol, we want |
4197 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4198 | Otherwise we want | |
4199 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4200 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4201 | If we have a constant, we need two instructions anyhow, | |
4202 | so we may as well always use the latter form. */ | |
7a15a226 | 4203 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4204 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4205 | p = NULL; |
4206 | else | |
4207 | { | |
8ea7f4e8 | 4208 | frag_grow (20); |
0dd2d296 | 4209 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4210 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4211 | || mips_opts.isa < 3) | |
4212 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4213 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4214 | p = frag_var (rs_machine_dependent, 8, 0, | |
4215 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4216 | mips_opts.warn_about_macros), |
f59fb6ca | 4217 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4218 | (char *) NULL); |
4219 | } | |
4220 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4221 | if (p != NULL) | |
4222 | p += 4; | |
4223 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4224 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4225 | || mips_opts.isa < 3) | |
4226 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4227 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4228 | } | |
fb251650 | 4229 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4230 | { |
4231 | /* If this is a reference to an external symbol, and there | |
4232 | is no constant, we want | |
4233 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4234 | For a local symbol, we want | |
4235 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4236 | nop | |
4237 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4238 | ||
4239 | If we have a small constant, and this is a reference to | |
4240 | an external symbol, we want | |
4241 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4242 | nop | |
4243 | addiu $tempreg,$tempreg,<constant> | |
4244 | For a local symbol, we want the same instruction | |
4245 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4246 | addiu instruction. | |
4247 | ||
4248 | If we have a large constant, and this is a reference to | |
4249 | an external symbol, we want | |
4250 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4251 | lui $at,<hiconstant> | |
4252 | addiu $at,$at,<loconstant> | |
4253 | addu $tempreg,$tempreg,$at | |
4254 | For a local symbol, we want the same instruction | |
4255 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4256 | addiu instruction. */ | |
4257 | expr1.X_add_number = offset_expr.X_add_number; | |
4258 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4259 | frag_grow (32); |
0dd2d296 | 4260 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4261 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4262 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4263 | if (expr1.X_add_number == 0) | |
4264 | { | |
4265 | int off; | |
4266 | ||
4267 | if (breg == 0) | |
4268 | off = 0; | |
4269 | else | |
4270 | { | |
4271 | /* We're going to put in an addu instruction using | |
4272 | tempreg, so we may as well insert the nop right | |
4273 | now. */ | |
4274 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4275 | "nop", ""); | |
4276 | off = 4; | |
4277 | } | |
4278 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4279 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4280 | (breg == 0 | |
3c83da8a | 4281 | ? mips_opts.warn_about_macros |
0dd2d296 | 4282 | : 0)), |
f59fb6ca | 4283 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4284 | (char *) NULL); |
4285 | if (breg == 0) | |
4286 | { | |
4287 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4288 | p += 4; | |
4289 | } | |
4290 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4291 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4292 | || mips_opts.isa < 3) | |
4293 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4294 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4295 | /* FIXME: If breg == 0, and the next instruction uses | |
4296 | $tempreg, then if this variant case is used an extra | |
4297 | nop will be generated. */ | |
4298 | } | |
4299 | else if (expr1.X_add_number >= -0x8000 | |
4300 | && expr1.X_add_number < 0x8000) | |
4301 | { | |
4302 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4303 | "nop", ""); | |
4304 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4305 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4306 | || mips_opts.isa < 3) | |
4307 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4308 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4309 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4310 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4311 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4312 | (char *) NULL); |
4313 | } | |
4314 | else | |
4315 | { | |
4316 | int off1; | |
4317 | ||
4318 | /* If we are going to add in a base register, and the | |
4319 | target register and the base register are the same, | |
4320 | then we are using AT as a temporary register. Since | |
4321 | we want to load the constant into AT, we add our | |
4322 | current AT (from the global offset table) and the | |
4323 | register into the register now, and pretend we were | |
4324 | not using a base register. */ | |
4325 | if (breg != treg) | |
4326 | off1 = 0; | |
4327 | else | |
4328 | { | |
4329 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4330 | "nop", ""); | |
4331 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4332 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4333 | || mips_opts.isa < 3) | |
4334 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4335 | "d,v,t", treg, AT, breg); |
4336 | breg = 0; | |
4337 | tempreg = treg; | |
4338 | off1 = -8; | |
4339 | } | |
4340 | ||
55933a58 ILT |
4341 | /* Set mips_optimize around the lui instruction to avoid |
4342 | inserting an unnecessary nop after the lw. */ | |
4343 | hold_mips_optimize = mips_optimize; | |
4344 | mips_optimize = 2; | |
0dd2d296 | 4345 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4346 | mips_optimize = hold_mips_optimize; |
4347 | ||
0dd2d296 | 4348 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4349 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4350 | || mips_opts.isa < 3) | |
4351 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4352 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4353 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4354 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4355 | || mips_opts.isa < 3) | |
4356 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4357 | "d,v,t", tempreg, tempreg, AT); |
4358 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4359 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4360 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4361 | (char *) NULL); |
4362 | used_at = 1; | |
4363 | } | |
670a50eb | 4364 | } |
fb251650 ILT |
4365 | else if (mips_pic == SVR4_PIC) |
4366 | { | |
4367 | int gpdel; | |
4368 | ||
4369 | /* This is the large GOT case. If this is a reference to an | |
4370 | external symbol, and there is no constant, we want | |
4371 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4372 | addu $tempreg,$tempreg,$gp | |
4373 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4374 | For a local symbol, we want | |
4375 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4376 | nop | |
4377 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4378 | ||
4379 | If we have a small constant, and this is a reference to | |
4380 | an external symbol, we want | |
4381 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4382 | addu $tempreg,$tempreg,$gp | |
4383 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4384 | nop | |
4385 | addiu $tempreg,$tempreg,<constant> | |
4386 | For a local symbol, we want | |
4387 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4388 | nop | |
4389 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4390 | ||
4391 | If we have a large constant, and this is a reference to | |
4392 | an external symbol, we want | |
4393 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4394 | addu $tempreg,$tempreg,$gp | |
4395 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4396 | lui $at,<hiconstant> | |
4397 | addiu $at,$at,<loconstant> | |
4398 | addu $tempreg,$tempreg,$at | |
4399 | For a local symbol, we want | |
4400 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4401 | lui $at,<hiconstant> | |
4402 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4403 | addu $tempreg,$tempreg,$at | |
4404 | */ | |
4405 | expr1.X_add_number = offset_expr.X_add_number; | |
4406 | offset_expr.X_add_number = 0; | |
4407 | frag_grow (52); | |
4408 | if (reg_needs_delay (GP)) | |
4409 | gpdel = 4; | |
4410 | else | |
4411 | gpdel = 0; | |
4412 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4413 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4414 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4415 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4416 | || mips_opts.isa < 3) | |
4417 | ? "addu" : "daddu"), | |
fb251650 ILT |
4418 | "d,v,t", tempreg, tempreg, GP); |
4419 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4420 | dbl ? "ld" : "lw", | |
4421 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4422 | tempreg); | |
4423 | if (expr1.X_add_number == 0) | |
4424 | { | |
4425 | int off; | |
4426 | ||
4427 | if (breg == 0) | |
4428 | off = 0; | |
4429 | else | |
4430 | { | |
4431 | /* We're going to put in an addu instruction using | |
4432 | tempreg, so we may as well insert the nop right | |
4433 | now. */ | |
4434 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4435 | "nop", ""); | |
4436 | off = 4; | |
4437 | } | |
4438 | ||
4439 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4440 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4441 | 8 + gpdel, 0, | |
4442 | (breg == 0 | |
3c83da8a | 4443 | ? mips_opts.warn_about_macros |
fb251650 | 4444 | : 0)), |
f59fb6ca | 4445 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4446 | (char *) NULL); |
4447 | } | |
4448 | else if (expr1.X_add_number >= -0x8000 | |
4449 | && expr1.X_add_number < 0x8000) | |
4450 | { | |
4451 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4452 | "nop", ""); | |
4453 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4454 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4455 | || mips_opts.isa < 3) | |
4456 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4457 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4458 | ||
4459 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4460 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4461 | (breg == 0 | |
3c83da8a | 4462 | ? mips_opts.warn_about_macros |
fb251650 | 4463 | : 0)), |
f59fb6ca | 4464 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4465 | (char *) NULL); |
4466 | } | |
4467 | else | |
4468 | { | |
4469 | int adj, dreg; | |
4470 | ||
4471 | /* If we are going to add in a base register, and the | |
4472 | target register and the base register are the same, | |
4473 | then we are using AT as a temporary register. Since | |
4474 | we want to load the constant into AT, we add our | |
4475 | current AT (from the global offset table) and the | |
4476 | register into the register now, and pretend we were | |
4477 | not using a base register. */ | |
4478 | if (breg != treg) | |
4479 | { | |
4480 | adj = 0; | |
4481 | dreg = tempreg; | |
4482 | } | |
4483 | else | |
4484 | { | |
4485 | assert (tempreg == AT); | |
4486 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4487 | "nop", ""); | |
4488 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4489 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4490 | || mips_opts.isa < 3) | |
4491 | ? "addu" : "daddu"), | |
fb251650 ILT |
4492 | "d,v,t", treg, AT, breg); |
4493 | dreg = treg; | |
4494 | adj = 8; | |
4495 | } | |
4496 | ||
4497 | /* Set mips_optimize around the lui instruction to avoid | |
4498 | inserting an unnecessary nop after the lw. */ | |
4499 | hold_mips_optimize = mips_optimize; | |
4500 | mips_optimize = 2; | |
4501 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4502 | mips_optimize = hold_mips_optimize; | |
4503 | ||
4504 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4505 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4506 | || mips_opts.isa < 3) | |
4507 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4508 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4509 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4510 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4511 | || mips_opts.isa < 3) | |
4512 | ? "addu" : "daddu"), | |
fb251650 ILT |
4513 | "d,v,t", dreg, dreg, AT); |
4514 | ||
4515 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4516 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4517 | 8 + gpdel, 0, | |
4518 | (breg == 0 | |
3c83da8a | 4519 | ? mips_opts.warn_about_macros |
fb251650 | 4520 | : 0)), |
f59fb6ca | 4521 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4522 | (char *) NULL); |
4523 | ||
4524 | used_at = 1; | |
4525 | } | |
4526 | ||
4527 | if (gpdel > 0) | |
4528 | { | |
4529 | /* This is needed because this instruction uses $gp, but | |
4530 | the first instruction on the main stream does not. */ | |
4531 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4532 | p += 4; | |
4533 | } | |
4534 | macro_build (p, &icnt, &offset_expr, | |
4535 | dbl ? "ld" : "lw", | |
4536 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4537 | p += 4; | |
4538 | if (expr1.X_add_number >= -0x8000 | |
4539 | && expr1.X_add_number < 0x8000) | |
4540 | { | |
4541 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4542 | p += 4; | |
4543 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4544 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4545 | || mips_opts.isa < 3) | |
4546 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4547 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4548 | /* FIXME: If add_number is 0, and there was no base | |
4549 | register, the external symbol case ended with a load, | |
4550 | so if the symbol turns out to not be external, and | |
4551 | the next instruction uses tempreg, an unnecessary nop | |
4552 | will be inserted. */ | |
4553 | } | |
4554 | else | |
4555 | { | |
4556 | if (breg == treg) | |
4557 | { | |
4558 | /* We must add in the base register now, as in the | |
4559 | external symbol case. */ | |
4560 | assert (tempreg == AT); | |
4561 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4562 | p += 4; | |
4563 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4564 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4565 | || mips_opts.isa < 3) | |
4566 | ? "addu" : "daddu"), | |
fb251650 ILT |
4567 | "d,v,t", treg, AT, breg); |
4568 | p += 4; | |
4569 | tempreg = treg; | |
4570 | /* We set breg to 0 because we have arranged to add | |
4571 | it in in both cases. */ | |
4572 | breg = 0; | |
4573 | } | |
4574 | ||
4575 | macro_build_lui (p, &icnt, &expr1, AT); | |
4576 | p += 4; | |
4577 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4578 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4579 | || mips_opts.isa < 3) | |
4580 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4581 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4582 | p += 4; | |
4583 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4584 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4585 | || mips_opts.isa < 3) | |
4586 | ? "addu" : "daddu"), | |
fb251650 ILT |
4587 | "d,v,t", tempreg, tempreg, AT); |
4588 | p += 4; | |
4589 | } | |
4590 | } | |
d9aba805 ILT |
4591 | else if (mips_pic == EMBEDDED_PIC) |
4592 | { | |
4593 | /* We use | |
4594 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4595 | */ | |
4596 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4597 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4598 | || mips_opts.isa < 3) | |
4599 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4600 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4601 | } | |
4602 | else | |
4603 | abort (); | |
0dd2d296 | 4604 | |
670a50eb | 4605 | if (breg != 0) |
0dd2d296 | 4606 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4607 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4608 | || mips_opts.isa < 3) | |
4609 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4610 | "d,v,t", treg, tempreg, breg); |
4611 | ||
4612 | if (! used_at) | |
4613 | return; | |
4614 | ||
4615 | break; | |
4616 | ||
4617 | case M_J_A: | |
4618 | /* The j instruction may not be used in PIC code, since it | |
4619 | requires an absolute address. We convert it to a b | |
4620 | instruction. */ | |
d9aba805 | 4621 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4622 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4623 | else | |
4624 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4625 | return; |
3d3c5039 | 4626 | |
9226253a ILT |
4627 | /* The jal instructions must be handled as macros because when |
4628 | generating PIC code they expand to multi-instruction | |
4629 | sequences. Normally they are simple instructions. */ | |
4630 | case M_JAL_1: | |
4631 | dreg = RA; | |
4632 | /* Fall through. */ | |
4633 | case M_JAL_2: | |
d9aba805 ILT |
4634 | if (mips_pic == NO_PIC |
4635 | || mips_pic == EMBEDDED_PIC) | |
4636 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4637 | "d,s", dreg, sreg); | |
4638 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4639 | { |
d9aba805 | 4640 | if (sreg != PIC_CALL_REG) |
48401fcf | 4641 | as_warn (_("MIPS PIC call to register other than $25")); |
d9aba805 | 4642 | |
0dd2d296 ILT |
4643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4644 | "d,s", dreg, sreg); | |
d9aba805 | 4645 | if (mips_cprestore_offset < 0) |
48401fcf | 4646 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4647 | else |
4648 | { | |
4649 | expr1.X_add_number = mips_cprestore_offset; | |
4650 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4651 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4652 | || mips_opts.isa < 3) | |
4653 | ? "lw" : "ld"), | |
d9aba805 ILT |
4654 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4655 | } | |
9226253a | 4656 | } |
0dd2d296 | 4657 | else |
d9aba805 ILT |
4658 | abort (); |
4659 | ||
9226253a ILT |
4660 | return; |
4661 | ||
4662 | case M_JAL_A: | |
d9aba805 ILT |
4663 | if (mips_pic == NO_PIC) |
4664 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4665 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4666 | { |
fb251650 ILT |
4667 | /* If this is a reference to an external symbol, and we are |
4668 | using a small GOT, we want | |
d9aba805 ILT |
4669 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4670 | nop | |
4671 | jalr $25 | |
4672 | nop | |
4673 | lw $gp,cprestore($sp) | |
4674 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4675 | pseudo-op. If we are using a big GOT, we want |
4676 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4677 | addu $25,$25,$gp | |
4678 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4679 | nop | |
4680 | jalr $25 | |
4681 | nop | |
4682 | lw $gp,cprestore($sp) | |
4683 | If the symbol is not external, we want | |
d9aba805 ILT |
4684 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4685 | nop | |
4686 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4687 | jalr $25 | |
4688 | nop | |
fb251650 ILT |
4689 | lw $gp,cprestore($sp) */ |
4690 | frag_grow (40); | |
4691 | if (! mips_big_got) | |
4692 | { | |
4693 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4694 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4695 | || mips_opts.isa < 3) | |
4696 | ? "lw" : "ld"), | |
fb251650 ILT |
4697 | "t,o(b)", PIC_CALL_REG, |
4698 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4699 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4700 | "nop", ""); | |
4701 | p = frag_var (rs_machine_dependent, 4, 0, | |
4702 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4703 | offset_expr.X_add_symbol, (offsetT) 0, |
4704 | (char *) NULL); | |
fb251650 ILT |
4705 | } |
4706 | else | |
4707 | { | |
4708 | int gpdel; | |
4709 | ||
4710 | if (reg_needs_delay (GP)) | |
4711 | gpdel = 4; | |
4712 | else | |
4713 | gpdel = 0; | |
4714 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4715 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4716 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4717 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4718 | || mips_opts.isa < 3) | |
4719 | ? "addu" : "daddu"), | |
fb251650 ILT |
4720 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4721 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4722 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4723 | || mips_opts.isa < 3) | |
4724 | ? "lw" : "ld"), | |
fb251650 ILT |
4725 | "t,o(b)", PIC_CALL_REG, |
4726 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4727 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4728 | "nop", ""); | |
4729 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4730 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4731 | 0, 0), | |
f59fb6ca ILT |
4732 | offset_expr.X_add_symbol, (offsetT) 0, |
4733 | (char *) NULL); | |
fb251650 ILT |
4734 | if (gpdel > 0) |
4735 | { | |
4736 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4737 | p += 4; | |
4738 | } | |
4739 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4740 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4741 | || mips_opts.isa < 3) | |
4742 | ? "lw" : "ld"), | |
fb251650 ILT |
4743 | "t,o(b)", PIC_CALL_REG, |
4744 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4745 | p += 4; | |
4746 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4747 | p += 4; | |
4748 | } | |
d9aba805 | 4749 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4750 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4751 | || mips_opts.isa < 3) | |
4752 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4753 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4754 | (int) BFD_RELOC_LO16); | |
4755 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4756 | "jalr", "s", PIC_CALL_REG); | |
4757 | if (mips_cprestore_offset < 0) | |
48401fcf | 4758 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4759 | else |
4760 | { | |
3c83da8a | 4761 | if (mips_opts.noreorder) |
d9aba805 ILT |
4762 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4763 | "nop", ""); | |
4764 | expr1.X_add_number = mips_cprestore_offset; | |
4765 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4766 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4767 | || mips_opts.isa < 3) | |
4768 | ? "lw" : "ld"), | |
d9aba805 ILT |
4769 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4770 | mips_frame_reg); | |
4771 | } | |
0dd2d296 | 4772 | } |
d9aba805 | 4773 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4774 | { |
4775 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4776 | /* The linker may expand the call to a longer sequence which | |
4777 | uses $at, so we must break rather than return. */ | |
4778 | break; | |
4779 | } | |
d9aba805 ILT |
4780 | else |
4781 | abort (); | |
4782 | ||
9226253a ILT |
4783 | return; |
4784 | ||
3d3c5039 | 4785 | case M_LB_AB: |
670a50eb ILT |
4786 | s = "lb"; |
4787 | goto ld; | |
3d3c5039 | 4788 | case M_LBU_AB: |
670a50eb ILT |
4789 | s = "lbu"; |
4790 | goto ld; | |
3d3c5039 | 4791 | case M_LH_AB: |
670a50eb ILT |
4792 | s = "lh"; |
4793 | goto ld; | |
3d3c5039 | 4794 | case M_LHU_AB: |
670a50eb ILT |
4795 | s = "lhu"; |
4796 | goto ld; | |
3d3c5039 | 4797 | case M_LW_AB: |
670a50eb ILT |
4798 | s = "lw"; |
4799 | goto ld; | |
3d3c5039 | 4800 | case M_LWC0_AB: |
670a50eb | 4801 | s = "lwc0"; |
efec4a28 | 4802 | /* Itbl support may require additional care here. */ |
8358c818 | 4803 | coproc = 1; |
670a50eb | 4804 | goto ld; |
3d3c5039 | 4805 | case M_LWC1_AB: |
670a50eb | 4806 | s = "lwc1"; |
efec4a28 | 4807 | /* Itbl support may require additional care here. */ |
8358c818 | 4808 | coproc = 1; |
670a50eb | 4809 | goto ld; |
3d3c5039 | 4810 | case M_LWC2_AB: |
670a50eb | 4811 | s = "lwc2"; |
efec4a28 | 4812 | /* Itbl support may require additional care here. */ |
8358c818 | 4813 | coproc = 1; |
670a50eb | 4814 | goto ld; |
3d3c5039 | 4815 | case M_LWC3_AB: |
670a50eb | 4816 | s = "lwc3"; |
efec4a28 | 4817 | /* Itbl support may require additional care here. */ |
8358c818 | 4818 | coproc = 1; |
670a50eb | 4819 | goto ld; |
3d3c5039 | 4820 | case M_LWL_AB: |
670a50eb | 4821 | s = "lwl"; |
b2b8c24e | 4822 | lr = 1; |
670a50eb | 4823 | goto ld; |
3d3c5039 | 4824 | case M_LWR_AB: |
670a50eb | 4825 | s = "lwr"; |
b2b8c24e | 4826 | lr = 1; |
8358c818 ILT |
4827 | goto ld; |
4828 | case M_LDC1_AB: | |
1c6f3441 ILT |
4829 | if (mips_4650) |
4830 | { | |
48401fcf | 4831 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
4832 | return; |
4833 | } | |
8358c818 | 4834 | s = "ldc1"; |
efec4a28 | 4835 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4836 | coproc = 1; |
4837 | goto ld; | |
4838 | case M_LDC2_AB: | |
4839 | s = "ldc2"; | |
efec4a28 | 4840 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4841 | coproc = 1; |
4842 | goto ld; | |
4843 | case M_LDC3_AB: | |
4844 | s = "ldc3"; | |
efec4a28 | 4845 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4846 | coproc = 1; |
4847 | goto ld; | |
4848 | case M_LDL_AB: | |
4849 | s = "ldl"; | |
b2b8c24e | 4850 | lr = 1; |
8358c818 ILT |
4851 | goto ld; |
4852 | case M_LDR_AB: | |
4853 | s = "ldr"; | |
b2b8c24e | 4854 | lr = 1; |
8358c818 ILT |
4855 | goto ld; |
4856 | case M_LL_AB: | |
4857 | s = "ll"; | |
4858 | goto ld; | |
4859 | case M_LLD_AB: | |
4860 | s = "lld"; | |
4861 | goto ld; | |
4862 | case M_LWU_AB: | |
4863 | s = "lwu"; | |
3d3c5039 | 4864 | ld: |
b2b8c24e | 4865 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4866 | { |
4867 | tempreg = AT; | |
4868 | used_at = 1; | |
4869 | } | |
4870 | else | |
4871 | { | |
4872 | tempreg = treg; | |
4873 | used_at = 0; | |
4874 | } | |
4875 | goto ld_st; | |
3d3c5039 | 4876 | case M_SB_AB: |
670a50eb ILT |
4877 | s = "sb"; |
4878 | goto st; | |
3d3c5039 | 4879 | case M_SH_AB: |
670a50eb ILT |
4880 | s = "sh"; |
4881 | goto st; | |
3d3c5039 | 4882 | case M_SW_AB: |
670a50eb ILT |
4883 | s = "sw"; |
4884 | goto st; | |
3d3c5039 | 4885 | case M_SWC0_AB: |
670a50eb | 4886 | s = "swc0"; |
efec4a28 | 4887 | /* Itbl support may require additional care here. */ |
8358c818 | 4888 | coproc = 1; |
670a50eb | 4889 | goto st; |
3d3c5039 | 4890 | case M_SWC1_AB: |
670a50eb | 4891 | s = "swc1"; |
efec4a28 | 4892 | /* Itbl support may require additional care here. */ |
8358c818 | 4893 | coproc = 1; |
670a50eb | 4894 | goto st; |
3d3c5039 | 4895 | case M_SWC2_AB: |
670a50eb | 4896 | s = "swc2"; |
efec4a28 | 4897 | /* Itbl support may require additional care here. */ |
8358c818 | 4898 | coproc = 1; |
670a50eb | 4899 | goto st; |
3d3c5039 | 4900 | case M_SWC3_AB: |
670a50eb | 4901 | s = "swc3"; |
efec4a28 | 4902 | /* Itbl support may require additional care here. */ |
8358c818 | 4903 | coproc = 1; |
670a50eb | 4904 | goto st; |
3d3c5039 | 4905 | case M_SWL_AB: |
670a50eb ILT |
4906 | s = "swl"; |
4907 | goto st; | |
3d3c5039 | 4908 | case M_SWR_AB: |
670a50eb | 4909 | s = "swr"; |
8358c818 ILT |
4910 | goto st; |
4911 | case M_SC_AB: | |
4912 | s = "sc"; | |
4913 | goto st; | |
4914 | case M_SCD_AB: | |
4915 | s = "scd"; | |
4916 | goto st; | |
4917 | case M_SDC1_AB: | |
1c6f3441 ILT |
4918 | if (mips_4650) |
4919 | { | |
48401fcf | 4920 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
4921 | return; |
4922 | } | |
8358c818 ILT |
4923 | s = "sdc1"; |
4924 | coproc = 1; | |
efec4a28 | 4925 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4926 | goto st; |
4927 | case M_SDC2_AB: | |
4928 | s = "sdc2"; | |
efec4a28 | 4929 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4930 | coproc = 1; |
4931 | goto st; | |
4932 | case M_SDC3_AB: | |
4933 | s = "sdc3"; | |
efec4a28 | 4934 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4935 | coproc = 1; |
4936 | goto st; | |
4937 | case M_SDL_AB: | |
4938 | s = "sdl"; | |
4939 | goto st; | |
4940 | case M_SDR_AB: | |
4941 | s = "sdr"; | |
3d3c5039 | 4942 | st: |
670a50eb ILT |
4943 | tempreg = AT; |
4944 | used_at = 1; | |
3d3c5039 | 4945 | ld_st: |
efec4a28 | 4946 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4947 | if (mask == M_LWC1_AB |
4948 | || mask == M_SWC1_AB | |
8358c818 | 4949 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4950 | || mask == M_SDC1_AB |
4951 | || mask == M_L_DAB | |
4952 | || mask == M_S_DAB) | |
670a50eb | 4953 | fmt = "T,o(b)"; |
8358c818 | 4954 | else if (coproc) |
19ed8960 | 4955 | fmt = "E,o(b)"; |
670a50eb ILT |
4956 | else |
4957 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4958 | |
4959 | if (offset_expr.X_op != O_constant | |
4960 | && offset_expr.X_op != O_symbol) | |
4961 | { | |
48401fcf | 4962 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
4963 | offset_expr.X_op = O_constant; |
4964 | } | |
4965 | ||
4966 | /* A constant expression in PIC code can be handled just as it | |
4967 | is in non PIC code. */ | |
d9aba805 | 4968 | if (mips_pic == NO_PIC |
0dd2d296 | 4969 | || offset_expr.X_op == O_constant) |
670a50eb | 4970 | { |
0dd2d296 ILT |
4971 | /* If this is a reference to a GP relative symbol, and there |
4972 | is no base register, we want | |
4973 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4974 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4975 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4976 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4977 | If we have a constant, we need two instructions anyhow, | |
4978 | so we always use the latter form. | |
4979 | ||
4980 | If we have a base register, and this is a reference to a | |
4981 | GP relative symbol, we want | |
4982 | addu $tempreg,$breg,$gp | |
4983 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4984 | Otherwise we want | |
4985 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4986 | addu $tempreg,$tempreg,$breg | |
4987 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4988 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4989 | if (breg == 0) |
4990 | { | |
7a15a226 | 4991 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4992 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4993 | p = NULL; |
4994 | else | |
4995 | { | |
8ea7f4e8 | 4996 | frag_grow (20); |
0dd2d296 ILT |
4997 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4998 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4999 | p = frag_var (rs_machine_dependent, 8, 0, | |
5000 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
5001 | (mips_opts.warn_about_macros |
5002 | || (used_at | |
5003 | && mips_opts.noat))), | |
f59fb6ca | 5004 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5005 | (char *) NULL); |
8197b589 | 5006 | used_at = 0; |
0dd2d296 ILT |
5007 | } |
5008 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5009 | if (p != NULL) | |
5010 | p += 4; | |
5011 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5012 | (int) BFD_RELOC_LO16, tempreg); | |
5013 | } | |
5014 | else | |
5015 | { | |
7a15a226 | 5016 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5017 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5018 | p = NULL; |
5019 | else | |
5020 | { | |
8ea7f4e8 | 5021 | frag_grow (28); |
0dd2d296 | 5022 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5023 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5024 | || mips_opts.isa < 3) | |
5025 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5026 | "d,v,t", tempreg, breg, GP); |
5027 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5028 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5029 | p = frag_var (rs_machine_dependent, 12, 0, | |
5030 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 5031 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5032 | (char *) NULL); |
5033 | } | |
5034 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5035 | if (p != NULL) | |
5036 | p += 4; | |
5037 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5038 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5039 | || mips_opts.isa < 3) | |
5040 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5041 | "d,v,t", tempreg, tempreg, breg); |
5042 | if (p != NULL) | |
5043 | p += 4; | |
5044 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5045 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5046 | } |
670a50eb | 5047 | } |
fb251650 | 5048 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5049 | { |
0dd2d296 ILT |
5050 | /* If this is a reference to an external symbol, we want |
5051 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5052 | nop | |
5053 | <op> $treg,0($tempreg) | |
5054 | Otherwise we want | |
5055 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5056 | nop | |
5057 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5058 | <op> $treg,0($tempreg) | |
5059 | If there is a base register, we add it to $tempreg before | |
5060 | the <op>. If there is a constant, we stick it in the | |
5061 | <op> instruction. We don't handle constants larger than | |
5062 | 16 bits, because we have no way to load the upper 16 bits | |
5063 | (actually, we could handle them for the subset of cases | |
5064 | in which we are not using $at). */ | |
5065 | assert (offset_expr.X_op == O_symbol); | |
5066 | expr1.X_add_number = offset_expr.X_add_number; | |
5067 | offset_expr.X_add_number = 0; | |
5068 | if (expr1.X_add_number < -0x8000 | |
5069 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5070 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
8ea7f4e8 | 5071 | frag_grow (20); |
0dd2d296 | 5072 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5073 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5074 | || mips_opts.isa < 3) | |
5075 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5076 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5077 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5078 | p = frag_var (rs_machine_dependent, 4, 0, | |
5079 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5080 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5081 | (char *) NULL); |
5082 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5083 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5084 | || mips_opts.isa < 3) | |
5085 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5086 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5087 | if (breg != 0) |
0dd2d296 | 5088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5089 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5090 | || mips_opts.isa < 3) | |
5091 | ? "addu" : "daddu"), | |
6e8dda9c | 5092 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5093 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5094 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5095 | } |
fb251650 ILT |
5096 | else if (mips_pic == SVR4_PIC) |
5097 | { | |
5098 | int gpdel; | |
5099 | ||
5100 | /* If this is a reference to an external symbol, we want | |
5101 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5102 | addu $tempreg,$tempreg,$gp | |
5103 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5104 | <op> $treg,0($tempreg) | |
5105 | Otherwise we want | |
5106 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5107 | nop | |
5108 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5109 | <op> $treg,0($tempreg) | |
5110 | If there is a base register, we add it to $tempreg before | |
5111 | the <op>. If there is a constant, we stick it in the | |
5112 | <op> instruction. We don't handle constants larger than | |
5113 | 16 bits, because we have no way to load the upper 16 bits | |
5114 | (actually, we could handle them for the subset of cases | |
5115 | in which we are not using $at). */ | |
5116 | assert (offset_expr.X_op == O_symbol); | |
5117 | expr1.X_add_number = offset_expr.X_add_number; | |
5118 | offset_expr.X_add_number = 0; | |
5119 | if (expr1.X_add_number < -0x8000 | |
5120 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5121 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5122 | if (reg_needs_delay (GP)) |
5123 | gpdel = 4; | |
5124 | else | |
5125 | gpdel = 0; | |
5126 | frag_grow (36); | |
5127 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5128 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5129 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5130 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5131 | || mips_opts.isa < 3) | |
5132 | ? "addu" : "daddu"), | |
fb251650 ILT |
5133 | "d,v,t", tempreg, tempreg, GP); |
5134 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5135 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5136 | || mips_opts.isa < 3) | |
5137 | ? "lw" : "ld"), | |
867a58b3 ILT |
5138 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5139 | tempreg); | |
fb251650 ILT |
5140 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5141 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5142 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5143 | if (gpdel > 0) |
5144 | { | |
5145 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5146 | p += 4; | |
5147 | } | |
5148 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5149 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5150 | || mips_opts.isa < 3) | |
5151 | ? "lw" : "ld"), | |
867a58b3 | 5152 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5153 | p += 4; |
5154 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5155 | p += 4; | |
5156 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5157 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5158 | || mips_opts.isa < 3) | |
5159 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5160 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5161 | if (breg != 0) | |
5162 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5163 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5164 | || mips_opts.isa < 3) | |
5165 | ? "addu" : "daddu"), | |
fb251650 ILT |
5166 | "d,v,t", tempreg, tempreg, breg); |
5167 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5168 | (int) BFD_RELOC_LO16, tempreg); | |
5169 | } | |
d9aba805 ILT |
5170 | else if (mips_pic == EMBEDDED_PIC) |
5171 | { | |
5172 | /* If there is no base register, we want | |
5173 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5174 | If there is a base register, we want | |
5175 | addu $tempreg,$breg,$gp | |
5176 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5177 | */ | |
5178 | assert (offset_expr.X_op == O_symbol); | |
5179 | if (breg == 0) | |
5180 | { | |
5181 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5182 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5183 | used_at = 0; | |
5184 | } | |
5185 | else | |
5186 | { | |
5187 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5188 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5189 | || mips_opts.isa < 3) | |
5190 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5191 | "d,v,t", tempreg, breg, GP); |
5192 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5193 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5194 | } | |
5195 | } | |
5196 | else | |
5197 | abort (); | |
0dd2d296 ILT |
5198 | |
5199 | if (! used_at) | |
5200 | return; | |
5201 | ||
5202 | break; | |
3d3c5039 ILT |
5203 | |
5204 | case M_LI: | |
19ed8960 | 5205 | case M_LI_S: |
d8a1c247 KR |
5206 | load_register (&icnt, treg, &imm_expr, 0); |
5207 | return; | |
5208 | ||
5209 | case M_DLI: | |
5210 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5211 | return; |
3d3c5039 | 5212 | |
0dd2d296 | 5213 | case M_LI_SS: |
55933a58 | 5214 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5215 | { |
d8a1c247 | 5216 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5218 | "mtc1", "t,G", AT, treg); | |
5219 | break; | |
0dd2d296 | 5220 | } |
d9aba805 | 5221 | else |
d2c71068 | 5222 | { |
55933a58 ILT |
5223 | assert (offset_expr.X_op == O_symbol |
5224 | && strcmp (segment_name (S_GET_SEGMENT | |
5225 | (offset_expr.X_add_symbol)), | |
5226 | ".lit4") == 0 | |
5227 | && offset_expr.X_add_number == 0); | |
5228 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5229 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5230 | return; |
5231 | } | |
0dd2d296 | 5232 | |
3d3c5039 | 5233 | case M_LI_D: |
a5586bdc ILT |
5234 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5235 | the entire value, and in mips1 mode it is the high order 32 | |
5236 | bits of the value and the low order 32 bits are either zero | |
5237 | or in offset_expr. */ | |
5238 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5239 | { | |
517640d9 ILT |
5240 | if (mips_opts.isa >= 3) |
5241 | load_register (&icnt, treg, &imm_expr, 1); | |
5242 | else | |
a5586bdc | 5243 | { |
517640d9 ILT |
5244 | int hreg, lreg; |
5245 | ||
5246 | if (target_big_endian) | |
5247 | { | |
5248 | hreg = treg; | |
5249 | lreg = treg + 1; | |
5250 | } | |
a5586bdc ILT |
5251 | else |
5252 | { | |
517640d9 ILT |
5253 | hreg = treg + 1; |
5254 | lreg = treg; | |
5255 | } | |
5256 | ||
5257 | if (hreg <= 31) | |
5258 | load_register (&icnt, hreg, &imm_expr, 0); | |
5259 | if (lreg <= 31) | |
5260 | { | |
5261 | if (offset_expr.X_op == O_absent) | |
5262 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5263 | lreg, 0); | |
5264 | else | |
5265 | { | |
5266 | assert (offset_expr.X_op == O_constant); | |
5267 | load_register (&icnt, lreg, &offset_expr, 0); | |
5268 | } | |
a5586bdc ILT |
5269 | } |
5270 | } | |
5271 | return; | |
5272 | } | |
5273 | ||
d9aba805 ILT |
5274 | /* We know that sym is in the .rdata section. First we get the |
5275 | upper 16 bits of the address. */ | |
5276 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5277 | { |
5278 | /* FIXME: This won't work for a 64 bit address. */ | |
5279 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5280 | } | |
d9aba805 | 5281 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5282 | { |
5283 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5284 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5285 | || mips_opts.isa < 3) | |
5286 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5287 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5288 | } | |
d9aba805 ILT |
5289 | else if (mips_pic == EMBEDDED_PIC) |
5290 | { | |
5291 | /* For embedded PIC we pick up the entire address off $gp in | |
5292 | a single instruction. */ | |
5293 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5294 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5295 | || mips_opts.isa < 3) | |
5296 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5297 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5298 | offset_expr.X_op = O_constant; | |
5299 | offset_expr.X_add_number = 0; | |
5300 | } | |
5301 | else | |
5302 | abort (); | |
5303 | ||
0dd2d296 | 5304 | /* Now we load the register(s). */ |
3c83da8a | 5305 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5306 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5307 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5308 | else |
5309 | { | |
0dd2d296 ILT |
5310 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5311 | treg, (int) BFD_RELOC_LO16, AT); | |
5312 | if (treg != 31) | |
5313 | { | |
5314 | /* FIXME: How in the world do we deal with the possible | |
5315 | overflow here? */ | |
5316 | offset_expr.X_add_number += 4; | |
5317 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5318 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5319 | } | |
8358c818 | 5320 | } |
d2c71068 ILT |
5321 | |
5322 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5323 | does not become a variant frag. */ | |
5324 | frag_wane (frag_now); | |
5325 | frag_new (0); | |
5326 | ||
670a50eb | 5327 | break; |
3d3c5039 ILT |
5328 | |
5329 | case M_LI_DD: | |
a5586bdc ILT |
5330 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5331 | the entire value, and in mips1 mode it is the high order 32 | |
5332 | bits of the value and the low order 32 bits are either zero | |
5333 | or in offset_expr. */ | |
5334 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5335 | { | |
5336 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5337 | if (mips_opts.isa >= 3) | |
5338 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5339 | "dmtc1", "t,S", AT, treg); | |
5340 | else | |
5341 | { | |
5342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5343 | "mtc1", "t,G", AT, treg + 1); | |
5344 | if (offset_expr.X_op == O_absent) | |
5345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5346 | "mtc1", "t,G", 0, treg); | |
5347 | else | |
5348 | { | |
5349 | assert (offset_expr.X_op == O_constant); | |
5350 | load_register (&icnt, AT, &offset_expr, 0); | |
5351 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5352 | "mtc1", "t,G", AT, treg); | |
5353 | } | |
5354 | } | |
5355 | break; | |
5356 | } | |
5357 | ||
55933a58 ILT |
5358 | assert (offset_expr.X_op == O_symbol |
5359 | && offset_expr.X_add_number == 0); | |
5360 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5361 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5362 | { |
3c83da8a | 5363 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5364 | { |
5365 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5366 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5367 | return; | |
5368 | } | |
5369 | breg = GP; | |
5370 | r = BFD_RELOC_MIPS_LITERAL; | |
5371 | goto dob; | |
5372 | } | |
55933a58 | 5373 | else |
0dd2d296 | 5374 | { |
55933a58 ILT |
5375 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5376 | if (mips_pic == SVR4_PIC) | |
5377 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5378 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5379 | || mips_opts.isa < 3) | |
5380 | ? "lw" : "ld"), | |
55933a58 ILT |
5381 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5382 | else | |
5383 | { | |
5384 | /* FIXME: This won't work for a 64 bit address. */ | |
5385 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5386 | } | |
5387 | ||
3c83da8a | 5388 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5389 | { |
5390 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5391 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5392 | |
5393 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5394 | that this does not become a variant frag. */ | |
5395 | frag_wane (frag_now); | |
5396 | frag_new (0); | |
5397 | ||
0dd2d296 ILT |
5398 | break; |
5399 | } | |
5400 | breg = AT; | |
5401 | r = BFD_RELOC_LO16; | |
5402 | goto dob; | |
8358c818 | 5403 | } |
9226253a | 5404 | |
3d3c5039 | 5405 | case M_L_DOB: |
1c6f3441 ILT |
5406 | if (mips_4650) |
5407 | { | |
48401fcf | 5408 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5409 | return; |
5410 | } | |
9a7d824a ILT |
5411 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5412 | to adjust when loading from memory. */ | |
9226253a ILT |
5413 | r = BFD_RELOC_LO16; |
5414 | dob: | |
3c83da8a | 5415 | assert (mips_opts.isa < 2); |
0dd2d296 | 5416 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5417 | target_big_endian ? treg + 1 : treg, |
9226253a | 5418 | (int) r, breg); |
0dd2d296 ILT |
5419 | /* FIXME: A possible overflow which I don't know how to deal |
5420 | with. */ | |
670a50eb | 5421 | offset_expr.X_add_number += 4; |
0dd2d296 | 5422 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5423 | target_big_endian ? treg : treg + 1, |
9226253a | 5424 | (int) r, breg); |
d2c71068 ILT |
5425 | |
5426 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5427 | does not become a variant frag. */ | |
5428 | frag_wane (frag_now); | |
5429 | frag_new (0); | |
5430 | ||
0dd2d296 ILT |
5431 | if (breg != AT) |
5432 | return; | |
5433 | break; | |
3d3c5039 ILT |
5434 | |
5435 | case M_L_DAB: | |
670a50eb ILT |
5436 | /* |
5437 | * The MIPS assembler seems to check for X_add_number not | |
5438 | * being double aligned and generating: | |
5439 | * lui at,%hi(foo+1) | |
5440 | * addu at,at,v1 | |
5441 | * addiu at,at,%lo(foo+1) | |
5442 | * lwc1 f2,0(at) | |
5443 | * lwc1 f3,4(at) | |
5444 | * But, the resulting address is the same after relocation so why | |
5445 | * generate the extra instruction? | |
5446 | */ | |
1c6f3441 ILT |
5447 | if (mips_4650) |
5448 | { | |
48401fcf | 5449 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5450 | return; |
5451 | } | |
efec4a28 | 5452 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5453 | coproc = 1; |
3c83da8a | 5454 | if (mips_opts.isa >= 2) |
670a50eb | 5455 | { |
0dd2d296 ILT |
5456 | s = "ldc1"; |
5457 | goto ld; | |
670a50eb | 5458 | } |
0dd2d296 ILT |
5459 | |
5460 | s = "lwc1"; | |
5461 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5462 | goto ldd_std; |
5463 | ||
5464 | case M_S_DAB: | |
1c6f3441 ILT |
5465 | if (mips_4650) |
5466 | { | |
48401fcf | 5467 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5468 | return; |
5469 | } | |
5470 | ||
3c83da8a | 5471 | if (mips_opts.isa >= 2) |
8358c818 | 5472 | { |
0dd2d296 ILT |
5473 | s = "sdc1"; |
5474 | goto st; | |
8358c818 | 5475 | } |
3d3c5039 | 5476 | |
0dd2d296 ILT |
5477 | s = "swc1"; |
5478 | fmt = "T,o(b)"; | |
efec4a28 | 5479 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5480 | coproc = 1; |
5481 | goto ldd_std; | |
3d3c5039 ILT |
5482 | |
5483 | case M_LD_AB: | |
3c83da8a | 5484 | if (mips_opts.isa >= 3) |
670a50eb | 5485 | { |
0dd2d296 ILT |
5486 | s = "ld"; |
5487 | goto ld; | |
670a50eb | 5488 | } |
0dd2d296 ILT |
5489 | |
5490 | s = "lw"; | |
5491 | fmt = "t,o(b)"; | |
5492 | goto ldd_std; | |
5493 | ||
5494 | case M_SD_AB: | |
3c83da8a | 5495 | if (mips_opts.isa >= 3) |
670a50eb | 5496 | { |
0dd2d296 ILT |
5497 | s = "sd"; |
5498 | goto st; | |
670a50eb | 5499 | } |
0dd2d296 | 5500 | |
670a50eb | 5501 | s = "sw"; |
0dd2d296 ILT |
5502 | fmt = "t,o(b)"; |
5503 | ||
5504 | ldd_std: | |
5505 | if (offset_expr.X_op != O_symbol | |
5506 | && offset_expr.X_op != O_constant) | |
670a50eb | 5507 | { |
48401fcf | 5508 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5509 | offset_expr.X_op = O_constant; |
5510 | } | |
5511 | ||
5512 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5513 | to adjust when loading from memory. We set coproc if we must | |
5514 | load $fn+1 first. */ | |
efec4a28 | 5515 | /* Itbl support may require additional care here. */ |
b9129c6f | 5516 | if (! target_big_endian) |
0dd2d296 ILT |
5517 | coproc = 0; |
5518 | ||
d9aba805 | 5519 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5520 | || offset_expr.X_op == O_constant) |
5521 | { | |
5522 | /* If this is a reference to a GP relative symbol, we want | |
5523 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5524 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5525 | If we have a base register, we use this | |
5526 | addu $at,$breg,$gp | |
5527 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5528 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5529 | If this is not a GP relative symbol, we want | |
5530 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5531 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5532 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5533 | If there is a base register, we add it to $at after the | |
5534 | lui instruction. If there is a constant, we always use | |
5535 | the last case. */ | |
7a15a226 | 5536 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5537 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5538 | { |
0dd2d296 ILT |
5539 | p = NULL; |
5540 | used_at = 1; | |
670a50eb ILT |
5541 | } |
5542 | else | |
0dd2d296 ILT |
5543 | { |
5544 | int off; | |
5545 | ||
5546 | if (breg == 0) | |
5547 | { | |
8ea7f4e8 | 5548 | frag_grow (28); |
0dd2d296 ILT |
5549 | tempreg = GP; |
5550 | off = 0; | |
5551 | used_at = 0; | |
5552 | } | |
5553 | else | |
5554 | { | |
8ea7f4e8 | 5555 | frag_grow (36); |
0dd2d296 | 5556 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5557 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5558 | || mips_opts.isa < 3) | |
5559 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5560 | "d,v,t", AT, breg, GP); |
5561 | tempreg = AT; | |
5562 | off = 4; | |
5563 | used_at = 1; | |
5564 | } | |
5565 | ||
efec4a28 | 5566 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5567 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5568 | coproc ? treg + 1 : treg, | |
5569 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5570 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5571 | |
5572 | /* Set mips_optimize to 2 to avoid inserting an | |
5573 | undesired nop. */ | |
5574 | hold_mips_optimize = mips_optimize; | |
5575 | mips_optimize = 2; | |
efec4a28 | 5576 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5577 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5578 | coproc ? treg : treg + 1, | |
5579 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5580 | mips_optimize = hold_mips_optimize; |
5581 | ||
0dd2d296 ILT |
5582 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5583 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5584 | used_at && mips_opts.noat), |
f59fb6ca | 5585 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5586 | (char *) NULL); |
777ad64d ILT |
5587 | |
5588 | /* We just generated two relocs. When tc_gen_reloc | |
5589 | handles this case, it will skip the first reloc and | |
5590 | handle the second. The second reloc already has an | |
5591 | extra addend of 4, which we added above. We must | |
5592 | subtract it out, and then subtract another 4 to make | |
5593 | the first reloc come out right. The second reloc | |
5594 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5595 | offset_expr when we build its instruction below. |
5596 | ||
5597 | If we have a symbol, then we don't want to include | |
5598 | the offset, because it will wind up being included | |
5599 | when we generate the reloc. */ | |
5600 | ||
5601 | if (offset_expr.X_op == O_constant) | |
5602 | offset_expr.X_add_number -= 8; | |
5603 | else | |
5604 | { | |
5605 | offset_expr.X_add_number = -4; | |
5606 | offset_expr.X_op = O_constant; | |
5607 | } | |
0dd2d296 ILT |
5608 | } |
5609 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5610 | if (p != NULL) | |
5611 | p += 4; | |
5612 | if (breg != 0) | |
5613 | { | |
5614 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5615 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5616 | || mips_opts.isa < 3) | |
5617 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5618 | "d,v,t", AT, breg, AT); |
5619 | if (p != NULL) | |
5620 | p += 4; | |
5621 | } | |
efec4a28 | 5622 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5623 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5624 | coproc ? treg + 1 : treg, | |
5625 | (int) BFD_RELOC_LO16, AT); | |
5626 | if (p != NULL) | |
5627 | p += 4; | |
5628 | /* FIXME: How do we handle overflow here? */ | |
5629 | offset_expr.X_add_number += 4; | |
efec4a28 | 5630 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5631 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5632 | coproc ? treg : treg + 1, | |
5633 | (int) BFD_RELOC_LO16, AT); | |
5634 | } | |
fb251650 | 5635 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5636 | { |
0dd2d296 ILT |
5637 | int off; |
5638 | ||
5639 | /* If this is a reference to an external symbol, we want | |
5640 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5641 | nop | |
5642 | <op> $treg,0($at) | |
5643 | <op> $treg+1,4($at) | |
5644 | Otherwise we want | |
5645 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5646 | nop | |
5647 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5648 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5649 | If there is a base register we add it to $at before the | |
5650 | lwc1 instructions. If there is a constant we include it | |
5651 | in the lwc1 instructions. */ | |
5652 | used_at = 1; | |
5653 | expr1.X_add_number = offset_expr.X_add_number; | |
5654 | offset_expr.X_add_number = 0; | |
5655 | if (expr1.X_add_number < -0x8000 | |
5656 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5657 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 ILT |
5658 | if (breg == 0) |
5659 | off = 0; | |
5660 | else | |
5661 | off = 4; | |
8ea7f4e8 | 5662 | frag_grow (24 + off); |
0dd2d296 | 5663 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5664 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5665 | || mips_opts.isa < 3) | |
5666 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5667 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5668 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5669 | if (breg != 0) |
0dd2d296 | 5670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5671 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5672 | || mips_opts.isa < 3) | |
5673 | ? "addu" : "daddu"), | |
0dd2d296 | 5674 | "d,v,t", AT, breg, AT); |
efec4a28 | 5675 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5676 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5677 | coproc ? treg + 1 : treg, | |
5678 | (int) BFD_RELOC_LO16, AT); | |
5679 | expr1.X_add_number += 4; | |
55933a58 ILT |
5680 | |
5681 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5682 | nop. */ | |
5683 | hold_mips_optimize = mips_optimize; | |
5684 | mips_optimize = 2; | |
efec4a28 | 5685 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5686 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5687 | coproc ? treg : treg + 1, | |
5688 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5689 | mips_optimize = hold_mips_optimize; |
5690 | ||
0dd2d296 ILT |
5691 | (void) frag_var (rs_machine_dependent, 0, 0, |
5692 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5693 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5694 | (char *) NULL); |
8358c818 | 5695 | } |
fb251650 ILT |
5696 | else if (mips_pic == SVR4_PIC) |
5697 | { | |
5698 | int gpdel, off; | |
5699 | ||
5700 | /* If this is a reference to an external symbol, we want | |
5701 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5702 | addu $at,$at,$gp | |
5703 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5704 | nop | |
5705 | <op> $treg,0($at) | |
5706 | <op> $treg+1,4($at) | |
5707 | Otherwise we want | |
5708 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5709 | nop | |
5710 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5711 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5712 | If there is a base register we add it to $at before the | |
5713 | lwc1 instructions. If there is a constant we include it | |
5714 | in the lwc1 instructions. */ | |
5715 | used_at = 1; | |
5716 | expr1.X_add_number = offset_expr.X_add_number; | |
5717 | offset_expr.X_add_number = 0; | |
5718 | if (expr1.X_add_number < -0x8000 | |
5719 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5720 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5721 | if (reg_needs_delay (GP)) |
5722 | gpdel = 4; | |
5723 | else | |
5724 | gpdel = 0; | |
5725 | if (breg == 0) | |
5726 | off = 0; | |
5727 | else | |
5728 | off = 4; | |
5729 | frag_grow (56); | |
5730 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5731 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5732 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5733 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5734 | || mips_opts.isa < 3) | |
5735 | ? "addu" : "daddu"), | |
fb251650 ILT |
5736 | "d,v,t", AT, AT, GP); |
5737 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5738 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5739 | || mips_opts.isa < 3) | |
5740 | ? "lw" : "ld"), | |
fb251650 ILT |
5741 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5742 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5743 | if (breg != 0) | |
5744 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5745 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5746 | || mips_opts.isa < 3) | |
5747 | ? "addu" : "daddu"), | |
fb251650 | 5748 | "d,v,t", AT, breg, AT); |
efec4a28 | 5749 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5750 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5751 | coproc ? treg + 1 : treg, | |
5752 | (int) BFD_RELOC_LO16, AT); | |
5753 | expr1.X_add_number += 4; | |
5754 | ||
5755 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5756 | nop. */ | |
5757 | hold_mips_optimize = mips_optimize; | |
5758 | mips_optimize = 2; | |
efec4a28 | 5759 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5760 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5761 | coproc ? treg : treg + 1, | |
5762 | (int) BFD_RELOC_LO16, AT); | |
5763 | mips_optimize = hold_mips_optimize; | |
5764 | expr1.X_add_number -= 4; | |
5765 | ||
5766 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5767 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5768 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5769 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5770 | (char *) NULL); |
5771 | if (gpdel > 0) | |
5772 | { | |
5773 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5774 | p += 4; | |
5775 | } | |
5776 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5777 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5778 | || mips_opts.isa < 3) | |
5779 | ? "lw" : "ld"), | |
fb251650 ILT |
5780 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5781 | p += 4; | |
5782 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5783 | p += 4; | |
5784 | if (breg != 0) | |
5785 | { | |
5786 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5787 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5788 | || mips_opts.isa < 3) | |
5789 | ? "addu" : "daddu"), | |
fb251650 ILT |
5790 | "d,v,t", AT, breg, AT); |
5791 | p += 4; | |
5792 | } | |
efec4a28 | 5793 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5794 | macro_build (p, &icnt, &expr1, s, fmt, |
5795 | coproc ? treg + 1 : treg, | |
5796 | (int) BFD_RELOC_LO16, AT); | |
5797 | p += 4; | |
5798 | expr1.X_add_number += 4; | |
5799 | ||
5800 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5801 | nop. */ | |
5802 | hold_mips_optimize = mips_optimize; | |
5803 | mips_optimize = 2; | |
efec4a28 | 5804 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5805 | macro_build (p, &icnt, &expr1, s, fmt, |
5806 | coproc ? treg : treg + 1, | |
5807 | (int) BFD_RELOC_LO16, AT); | |
5808 | mips_optimize = hold_mips_optimize; | |
5809 | } | |
d9aba805 ILT |
5810 | else if (mips_pic == EMBEDDED_PIC) |
5811 | { | |
5812 | /* If there is no base register, we use | |
5813 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5814 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5815 | If we have a base register, we use | |
5816 | addu $at,$breg,$gp | |
5817 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5818 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5819 | */ | |
5820 | if (breg == 0) | |
5821 | { | |
5822 | tempreg = GP; | |
5823 | used_at = 0; | |
5824 | } | |
5825 | else | |
5826 | { | |
5827 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5828 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5829 | || mips_opts.isa < 3) | |
5830 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5831 | "d,v,t", AT, breg, GP); |
5832 | tempreg = AT; | |
5833 | used_at = 1; | |
5834 | } | |
5835 | ||
efec4a28 | 5836 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5837 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5838 | coproc ? treg + 1 : treg, | |
5839 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5840 | offset_expr.X_add_number += 4; | |
efec4a28 | 5841 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5842 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5843 | coproc ? treg : treg + 1, | |
5844 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5845 | } | |
5846 | else | |
5847 | abort (); | |
0dd2d296 ILT |
5848 | |
5849 | if (! used_at) | |
5850 | return; | |
5851 | ||
5852 | break; | |
5853 | ||
5854 | case M_LD_OB: | |
5855 | s = "lw"; | |
5856 | goto sd_ob; | |
5857 | case M_SD_OB: | |
5858 | s = "sw"; | |
5859 | sd_ob: | |
9a1f3160 | 5860 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5861 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5862 | (int) BFD_RELOC_LO16, breg); | |
5863 | offset_expr.X_add_number += 4; | |
5864 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5865 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5866 | return; |
efec4a28 DP |
5867 | |
5868 | /* New code added to support COPZ instructions. | |
5869 | This code builds table entries out of the macros in mip_opcodes. | |
5870 | R4000 uses interlocks to handle coproc delays. | |
5871 | Other chips (like the R3000) require nops to be inserted for delays. | |
5872 | ||
5873 | FIXME: Currently, we require that the user handle delays. | |
5874 | In order to fill delay slots for non-interlocked chips, | |
5875 | we must have a way to specify delays based on the coprocessor. | |
5876 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5877 | What are the side-effects of the cop instruction? | |
5878 | What cache support might we have and what are its effects? | |
5879 | Both coprocessor & memory require delays. how long??? | |
5880 | What registers are read/set/modified? | |
5881 | ||
5882 | If an itbl is provided to interpret cop instructions, | |
5883 | this knowledge can be encoded in the itbl spec. */ | |
5884 | ||
5885 | case M_COP0: | |
65d2c7d3 | 5886 | s = "c0"; |
efec4a28 DP |
5887 | goto copz; |
5888 | case M_COP1: | |
65d2c7d3 | 5889 | s = "c1"; |
efec4a28 DP |
5890 | goto copz; |
5891 | case M_COP2: | |
65d2c7d3 | 5892 | s = "c2"; |
efec4a28 DP |
5893 | goto copz; |
5894 | case M_COP3: | |
65d2c7d3 | 5895 | s = "c3"; |
efec4a28 | 5896 | copz: |
65d2c7d3 JL |
5897 | /* For now we just do C (same as Cz). The parameter will be |
5898 | stored in insn_opcode by mips_ip. */ | |
5899 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5900 | ip->insn_opcode); | |
efec4a28 DP |
5901 | return; |
5902 | ||
917fae09 SS |
5903 | #ifdef LOSING_COMPILER |
5904 | default: | |
efec4a28 DP |
5905 | /* Try and see if this is a new itbl instruction. |
5906 | This code builds table entries out of the macros in mip_opcodes. | |
5907 | FIXME: For now we just assemble the expression and pass it's | |
5908 | value along as a 32-bit immediate. | |
5909 | We may want to have the assembler assemble this value, | |
5910 | so that we gain the assembler's knowledge of delay slots, | |
5911 | symbols, etc. | |
5912 | Would it be more efficient to use mask (id) here? */ | |
5913 | if (itbl_have_entries | |
9218cee0 | 5914 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5915 | { |
5916 | s = ip->insn_mo->name; | |
5917 | s2 = "cop3"; | |
9218cee0 | 5918 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5919 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5920 | return; | |
5921 | } | |
917fae09 SS |
5922 | macro2 (ip); |
5923 | return; | |
5924 | } | |
3c83da8a | 5925 | if (mips_opts.noat) |
48401fcf | 5926 | as_warn (_("Macro used $at after \".set noat\"")); |
917fae09 SS |
5927 | } |
5928 | ||
5929 | static void | |
5930 | macro2 (ip) | |
5931 | struct mips_cl_insn *ip; | |
5932 | { | |
5933 | register int treg, sreg, dreg, breg; | |
5934 | int tempreg; | |
5935 | int mask; | |
5936 | int icnt = 0; | |
5937 | int used_at; | |
5938 | expressionS expr1; | |
5939 | const char *s; | |
5940 | const char *s2; | |
5941 | const char *fmt; | |
5942 | int likely = 0; | |
5943 | int dbl = 0; | |
5944 | int coproc = 0; | |
adcf2b9d | 5945 | int lr = 0; |
40f0c904 | 5946 | int imm = 0; |
adcf2b9d | 5947 | int off; |
917fae09 SS |
5948 | offsetT maxnum; |
5949 | bfd_reloc_code_real_type r; | |
5950 | char *p; | |
5951 | ||
5952 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5953 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5954 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5955 | mask = ip->insn_mo->mask; | |
5956 | ||
5957 | expr1.X_op = O_constant; | |
5958 | expr1.X_op_symbol = NULL; | |
5959 | expr1.X_add_symbol = NULL; | |
5960 | expr1.X_add_number = 1; | |
5961 | ||
5962 | switch (mask) | |
5963 | { | |
5964 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5965 | |
8358c818 ILT |
5966 | case M_DMUL: |
5967 | dbl = 1; | |
3d3c5039 | 5968 | case M_MUL: |
0dd2d296 | 5969 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5970 | dbl ? "dmultu" : "multu", |
5971 | "s,t", sreg, treg); | |
0dd2d296 | 5972 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5973 | return; |
3d3c5039 | 5974 | |
8358c818 ILT |
5975 | case M_DMUL_I: |
5976 | dbl = 1; | |
3d3c5039 | 5977 | case M_MUL_I: |
8358c818 ILT |
5978 | /* The MIPS assembler some times generates shifts and adds. I'm |
5979 | not trying to be that fancy. GCC should do this for us | |
5980 | anyway. */ | |
d8a1c247 | 5981 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5982 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5983 | dbl ? "dmult" : "mult", |
5984 | "s,t", sreg, AT); | |
0dd2d296 | 5985 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5986 | break; |
3d3c5039 | 5987 | |
40f0c904 FCE |
5988 | case M_DMULO_I: |
5989 | dbl = 1; | |
5990 | case M_MULO_I: | |
5991 | imm = 1; | |
5992 | goto do_mulo; | |
5993 | ||
8358c818 ILT |
5994 | case M_DMULO: |
5995 | dbl = 1; | |
5996 | case M_MULO: | |
40f0c904 | 5997 | do_mulo: |
fbcfacb7 | 5998 | mips_emit_delays (true); |
3c83da8a | 5999 | ++mips_opts.noreorder; |
0dd2d296 | 6000 | mips_any_noreorder = 1; |
40f0c904 FCE |
6001 | if (imm) |
6002 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6003 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6004 | dbl ? "dmult" : "mult", |
40f0c904 | 6005 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6006 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6007 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
6008 | dbl ? "dsra32" : "sra", |
6009 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 6010 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
6011 | if (mips_trap) |
6012 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6013 | else | |
6014 | { | |
6015 | expr1.X_add_number = 8; | |
6016 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6017 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6018 | /* start-sanitize-r5900 */ |
6019 | if (mips_5900) | |
6020 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6021 | else | |
6022 | /* end-sanitize-r5900 */ | |
6023 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6024 | } |
3c83da8a | 6025 | --mips_opts.noreorder; |
0dd2d296 | 6026 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
6027 | break; |
6028 | ||
40f0c904 FCE |
6029 | case M_DMULOU_I: |
6030 | dbl = 1; | |
6031 | case M_MULOU_I: | |
6032 | imm = 1; | |
6033 | goto do_mulou; | |
6034 | ||
8358c818 ILT |
6035 | case M_DMULOU: |
6036 | dbl = 1; | |
6037 | case M_MULOU: | |
40f0c904 | 6038 | do_mulou: |
fbcfacb7 | 6039 | mips_emit_delays (true); |
3c83da8a | 6040 | ++mips_opts.noreorder; |
0dd2d296 | 6041 | mips_any_noreorder = 1; |
40f0c904 FCE |
6042 | if (imm) |
6043 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6044 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6045 | dbl ? "dmultu" : "multu", |
40f0c904 | 6046 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6047 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
6048 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
6049 | if (mips_trap) |
6050 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6051 | else | |
6052 | { | |
6053 | expr1.X_add_number = 8; | |
6054 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6055 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 FCE |
6056 | /* start-sanitize-r5900 */ |
6057 | if (mips_5900) | |
6058 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); | |
6059 | else | |
6060 | /* end-sanitize-r5900 */ | |
6061 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6062 | } |
3c83da8a | 6063 | --mips_opts.noreorder; |
8358c818 ILT |
6064 | break; |
6065 | ||
3d3c5039 | 6066 | case M_ROL: |
0dd2d296 ILT |
6067 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6068 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6069 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6070 | treg); | |
6071 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6072 | break; |
3d3c5039 ILT |
6073 | |
6074 | case M_ROL_I: | |
5c6f5923 | 6075 | if (imm_expr.X_op != O_constant) |
48401fcf | 6076 | as_bad (_("rotate count too large")); |
0dd2d296 | 6077 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6078 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6079 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6080 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6081 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6082 | break; |
3d3c5039 ILT |
6083 | |
6084 | case M_ROR: | |
0dd2d296 ILT |
6085 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6086 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6087 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6088 | treg); | |
6089 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6090 | break; |
3d3c5039 ILT |
6091 | |
6092 | case M_ROR_I: | |
5c6f5923 | 6093 | if (imm_expr.X_op != O_constant) |
48401fcf | 6094 | as_bad (_("rotate count too large")); |
0dd2d296 | 6095 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6096 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6097 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6098 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6099 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6100 | break; |
3d3c5039 ILT |
6101 | |
6102 | case M_S_DOB: | |
1c6f3441 ILT |
6103 | if (mips_4650) |
6104 | { | |
48401fcf | 6105 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
6106 | return; |
6107 | } | |
3c83da8a | 6108 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6109 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6110 | to adjust when storing to memory. */ | |
0dd2d296 | 6111 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6112 | target_big_endian ? treg + 1 : treg, |
9226253a | 6113 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6114 | offset_expr.X_add_number += 4; |
0dd2d296 | 6115 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6116 | target_big_endian ? treg : treg + 1, |
9226253a | 6117 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6118 | return; |
3d3c5039 | 6119 | |
3d3c5039 | 6120 | case M_SEQ: |
670a50eb | 6121 | if (sreg == 0) |
0dd2d296 ILT |
6122 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6123 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6124 | else if (treg == 0) |
0dd2d296 ILT |
6125 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6126 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6127 | else |
6128 | { | |
0dd2d296 ILT |
6129 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6130 | sreg, treg); | |
6131 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6132 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6133 | } |
670a50eb | 6134 | return; |
3d3c5039 ILT |
6135 | |
6136 | case M_SEQ_I: | |
5c6f5923 | 6137 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6138 | { |
0dd2d296 ILT |
6139 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6140 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6141 | return; |
3d3c5039 | 6142 | } |
670a50eb ILT |
6143 | if (sreg == 0) |
6144 | { | |
48401fcf | 6145 | as_warn (_("Instruction %s: result is always false"), |
6e8dda9c | 6146 | ip->insn_mo->name); |
0dd2d296 | 6147 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6148 | return; |
3d3c5039 | 6149 | } |
5c6f5923 GRK |
6150 | if (imm_expr.X_op == O_constant |
6151 | && imm_expr.X_add_number >= 0 | |
6152 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6153 | { |
0dd2d296 ILT |
6154 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6155 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6156 | used_at = 0; |
6e8dda9c | 6157 | } |
5c6f5923 GRK |
6158 | else if (imm_expr.X_op == O_constant |
6159 | && imm_expr.X_add_number > -0x8000 | |
6160 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6161 | { |
6162 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6163 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6164 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6165 | || mips_opts.isa < 3) | |
6166 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6167 | "t,r,j", dreg, sreg, |
6168 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6169 | used_at = 0; |
6170 | } | |
6171 | else | |
6172 | { | |
d8a1c247 | 6173 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6174 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6175 | sreg, AT); | |
670a50eb ILT |
6176 | used_at = 1; |
6177 | } | |
0dd2d296 | 6178 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6179 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6180 | if (used_at) |
6181 | break; | |
6182 | return; | |
3d3c5039 ILT |
6183 | |
6184 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6185 | s = "slt"; |
6186 | goto sge; | |
3d3c5039 | 6187 | case M_SGEU: |
670a50eb | 6188 | s = "sltu"; |
3d3c5039 | 6189 | sge: |
0dd2d296 ILT |
6190 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6191 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6192 | (int) BFD_RELOC_LO16); |
670a50eb | 6193 | return; |
3d3c5039 | 6194 | |
670a50eb | 6195 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6196 | case M_SGEU_I: |
5c6f5923 GRK |
6197 | if (imm_expr.X_op == O_constant |
6198 | && imm_expr.X_add_number >= -0x8000 | |
6199 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6200 | { |
0dd2d296 | 6201 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 6202 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6203 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6204 | used_at = 0; |
6205 | } | |
6206 | else | |
6207 | { | |
d8a1c247 | 6208 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6209 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6210 | mask == M_SGE_I ? "slt" : "sltu", |
6211 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6212 | used_at = 1; |
6213 | } | |
0dd2d296 | 6214 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6215 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6216 | if (used_at) |
6217 | break; | |
6218 | return; | |
3d3c5039 ILT |
6219 | |
6220 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6221 | s = "slt"; |
6222 | goto sgt; | |
3d3c5039 | 6223 | case M_SGTU: |
670a50eb | 6224 | s = "sltu"; |
3d3c5039 | 6225 | sgt: |
0dd2d296 | 6226 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6227 | return; |
3d3c5039 | 6228 | |
670a50eb ILT |
6229 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6230 | s = "slt"; | |
6231 | goto sgti; | |
3d3c5039 | 6232 | case M_SGTU_I: |
670a50eb | 6233 | s = "sltu"; |
3d3c5039 | 6234 | sgti: |
d8a1c247 | 6235 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6236 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6237 | break; |
3d3c5039 | 6238 | |
670a50eb ILT |
6239 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6240 | s = "slt"; | |
6241 | goto sle; | |
3d3c5039 | 6242 | case M_SLEU: |
670a50eb | 6243 | s = "sltu"; |
3d3c5039 | 6244 | sle: |
0dd2d296 ILT |
6245 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6246 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6247 | (int) BFD_RELOC_LO16); |
670a50eb | 6248 | return; |
3d3c5039 | 6249 | |
670a50eb ILT |
6250 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6251 | s = "slt"; | |
6252 | goto slei; | |
3d3c5039 | 6253 | case M_SLEU_I: |
670a50eb | 6254 | s = "sltu"; |
3d3c5039 | 6255 | slei: |
d8a1c247 | 6256 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6257 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6258 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6259 | (int) BFD_RELOC_LO16); |
670a50eb | 6260 | break; |
3d3c5039 ILT |
6261 | |
6262 | case M_SLT_I: | |
5c6f5923 GRK |
6263 | if (imm_expr.X_op == O_constant |
6264 | && imm_expr.X_add_number >= -0x8000 | |
6265 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6266 | { |
0dd2d296 ILT |
6267 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6268 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6269 | return; |
3d3c5039 | 6270 | } |
d8a1c247 | 6271 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6272 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6273 | break; |
3d3c5039 ILT |
6274 | |
6275 | case M_SLTU_I: | |
5c6f5923 GRK |
6276 | if (imm_expr.X_op == O_constant |
6277 | && imm_expr.X_add_number >= -0x8000 | |
6278 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6279 | { |
0dd2d296 ILT |
6280 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6281 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6282 | return; |
3d3c5039 | 6283 | } |
d8a1c247 | 6284 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6285 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6286 | AT); | |
670a50eb | 6287 | break; |
3d3c5039 ILT |
6288 | |
6289 | case M_SNE: | |
670a50eb | 6290 | if (sreg == 0) |
0dd2d296 ILT |
6291 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6292 | treg); | |
670a50eb | 6293 | else if (treg == 0) |
0dd2d296 ILT |
6294 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6295 | sreg); | |
670a50eb ILT |
6296 | else |
6297 | { | |
0dd2d296 ILT |
6298 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6299 | sreg, treg); | |
6300 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6301 | dreg); | |
3d3c5039 | 6302 | } |
670a50eb | 6303 | return; |
3d3c5039 ILT |
6304 | |
6305 | case M_SNE_I: | |
5c6f5923 | 6306 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6307 | { |
0dd2d296 ILT |
6308 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6309 | sreg); | |
670a50eb | 6310 | return; |
3d3c5039 | 6311 | } |
670a50eb ILT |
6312 | if (sreg == 0) |
6313 | { | |
48401fcf | 6314 | as_warn (_("Instruction %s: result is always true"), |
6e8dda9c | 6315 | ip->insn_mo->name); |
0dd2d296 | 6316 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6317 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6318 | || mips_opts.isa < 3) | |
6319 | ? "addiu" : "daddiu"), | |
9226253a | 6320 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6321 | return; |
3d3c5039 | 6322 | } |
5c6f5923 GRK |
6323 | if (imm_expr.X_op == O_constant |
6324 | && imm_expr.X_add_number >= 0 | |
6325 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6326 | { |
0dd2d296 ILT |
6327 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6328 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6329 | used_at = 0; |
6e8dda9c | 6330 | } |
5c6f5923 GRK |
6331 | else if (imm_expr.X_op == O_constant |
6332 | && imm_expr.X_add_number > -0x8000 | |
6333 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6334 | { |
6335 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6336 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6337 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6338 | || mips_opts.isa < 3) | |
6339 | ? "addiu" : "daddiu"), | |
9226253a | 6340 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6341 | used_at = 0; |
6342 | } | |
6343 | else | |
6344 | { | |
d8a1c247 | 6345 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6346 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6347 | sreg, AT); | |
670a50eb ILT |
6348 | used_at = 1; |
6349 | } | |
0dd2d296 | 6350 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6351 | if (used_at) |
6352 | break; | |
6353 | return; | |
3d3c5039 | 6354 | |
8358c818 ILT |
6355 | case M_DSUB_I: |
6356 | dbl = 1; | |
3d3c5039 | 6357 | case M_SUB_I: |
5c6f5923 GRK |
6358 | if (imm_expr.X_op == O_constant |
6359 | && imm_expr.X_add_number > -0x8000 | |
6360 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6361 | { |
6362 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6363 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6364 | dbl ? "daddi" : "addi", |
9226253a | 6365 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6366 | return; |
3d3c5039 | 6367 | } |
d8a1c247 | 6368 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6369 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6370 | dbl ? "dsub" : "sub", |
6371 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6372 | break; |
3d3c5039 | 6373 | |
8358c818 ILT |
6374 | case M_DSUBU_I: |
6375 | dbl = 1; | |
3d3c5039 | 6376 | case M_SUBU_I: |
5c6f5923 GRK |
6377 | if (imm_expr.X_op == O_constant |
6378 | && imm_expr.X_add_number > -0x8000 | |
6379 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6380 | { |
6381 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6382 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6383 | dbl ? "daddiu" : "addiu", |
9226253a | 6384 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6385 | return; |
3d3c5039 | 6386 | } |
d8a1c247 | 6387 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6388 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6389 | dbl ? "dsubu" : "subu", |
6390 | "d,v,t", dreg, sreg, AT); | |
6391 | break; | |
6392 | ||
6393 | case M_TEQ_I: | |
6394 | s = "teq"; | |
6395 | goto trap; | |
6396 | case M_TGE_I: | |
6397 | s = "tge"; | |
6398 | goto trap; | |
6399 | case M_TGEU_I: | |
6400 | s = "tgeu"; | |
6401 | goto trap; | |
6402 | case M_TLT_I: | |
6403 | s = "tlt"; | |
6404 | goto trap; | |
6405 | case M_TLTU_I: | |
6406 | s = "tltu"; | |
6407 | goto trap; | |
6408 | case M_TNE_I: | |
6409 | s = "tne"; | |
6410 | trap: | |
d8a1c247 | 6411 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6412 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6413 | break; |
3d3c5039 ILT |
6414 | |
6415 | case M_TRUNCWD: | |
6416 | case M_TRUNCWS: | |
3c83da8a | 6417 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6418 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6419 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6420 | ||
6421 | /* | |
6422 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6423 | * or is there a reason for it? | |
6424 | */ | |
fbcfacb7 | 6425 | mips_emit_delays (true); |
3c83da8a | 6426 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6427 | mips_any_noreorder = 1; |
6428 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6429 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6430 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6431 | expr1.X_add_number = 3; |
0dd2d296 | 6432 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6433 | (int) BFD_RELOC_LO16); |
670a50eb | 6434 | expr1.X_add_number = 2; |
0dd2d296 | 6435 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6436 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6437 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6438 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6439 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6440 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6441 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6442 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6443 | --mips_opts.noreorder; |
670a50eb | 6444 | break; |
3d3c5039 ILT |
6445 | |
6446 | case M_ULH: | |
670a50eb ILT |
6447 | s = "lb"; |
6448 | goto ulh; | |
3d3c5039 | 6449 | case M_ULHU: |
670a50eb | 6450 | s = "lbu"; |
3d3c5039 | 6451 | ulh: |
8ea7f4e8 | 6452 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6453 | as_bad (_("operand overflow")); |
670a50eb | 6454 | /* avoid load delay */ |
b9129c6f | 6455 | if (! target_big_endian) |
8ea7f4e8 | 6456 | offset_expr.X_add_number += 1; |
0dd2d296 | 6457 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6458 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6459 | if (! target_big_endian) |
8ea7f4e8 ILT |
6460 | offset_expr.X_add_number -= 1; |
6461 | else | |
6462 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6463 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6464 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6465 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6466 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6467 | break; |
3d3c5039 | 6468 | |
adcf2b9d ILT |
6469 | case M_ULD: |
6470 | s = "ldl"; | |
6471 | s2 = "ldr"; | |
6472 | off = 7; | |
6473 | goto ulw; | |
3d3c5039 | 6474 | case M_ULW: |
adcf2b9d ILT |
6475 | s = "lwl"; |
6476 | s2 = "lwr"; | |
6477 | off = 3; | |
6478 | ulw: | |
6479 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6480 | as_bad (_("operand overflow")); |
b9129c6f | 6481 | if (! target_big_endian) |
adcf2b9d ILT |
6482 | offset_expr.X_add_number += off; |
6483 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6484 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6485 | if (! target_big_endian) |
adcf2b9d | 6486 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6487 | else |
adcf2b9d ILT |
6488 | offset_expr.X_add_number += off; |
6489 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6490 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6491 | return; |
3d3c5039 | 6492 | |
adcf2b9d ILT |
6493 | case M_ULD_A: |
6494 | s = "ldl"; | |
6495 | s2 = "ldr"; | |
6496 | off = 7; | |
6497 | goto ulwa; | |
6498 | case M_ULW_A: | |
6499 | s = "lwl"; | |
6500 | s2 = "lwr"; | |
6501 | off = 3; | |
6502 | ulwa: | |
6503 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6504 | if (breg != 0) |
6505 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6506 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6507 | || mips_opts.isa < 3) | |
6508 | ? "addu" : "daddu"), | |
c625fc23 | 6509 | "d,v,t", AT, AT, breg); |
b9129c6f | 6510 | if (! target_big_endian) |
adcf2b9d ILT |
6511 | expr1.X_add_number = off; |
6512 | else | |
6513 | expr1.X_add_number = 0; | |
6514 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6515 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6516 | if (! target_big_endian) |
adcf2b9d ILT |
6517 | expr1.X_add_number = 0; |
6518 | else | |
6519 | expr1.X_add_number = off; | |
6520 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6521 | (int) BFD_RELOC_LO16, AT); | |
6522 | break; | |
6523 | ||
3d3c5039 ILT |
6524 | case M_ULH_A: |
6525 | case M_ULHU_A: | |
0dd2d296 | 6526 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6527 | if (breg != 0) |
6528 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6529 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6530 | || mips_opts.isa < 3) | |
6531 | ? "addu" : "daddu"), | |
c625fc23 | 6532 | "d,v,t", AT, AT, breg); |
b9129c6f | 6533 | if (target_big_endian) |
adcf2b9d ILT |
6534 | expr1.X_add_number = 0; |
6535 | macro_build ((char *) NULL, &icnt, &expr1, | |
6536 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6537 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6538 | if (target_big_endian) |
adcf2b9d | 6539 | expr1.X_add_number = 1; |
670a50eb | 6540 | else |
adcf2b9d ILT |
6541 | expr1.X_add_number = 0; |
6542 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6543 | (int) BFD_RELOC_LO16, AT); | |
6544 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6545 | treg, 8); | |
6546 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6547 | treg, AT); | |
670a50eb | 6548 | break; |
3d3c5039 ILT |
6549 | |
6550 | case M_USH: | |
8ea7f4e8 | 6551 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6552 | as_bad (_("operand overflow")); |
b9129c6f | 6553 | if (target_big_endian) |
8ea7f4e8 | 6554 | offset_expr.X_add_number += 1; |
0dd2d296 | 6555 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6556 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6557 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6558 | if (target_big_endian) |
8ea7f4e8 ILT |
6559 | offset_expr.X_add_number -= 1; |
6560 | else | |
6561 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6562 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6563 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6564 | break; |
3d3c5039 | 6565 | |
adcf2b9d ILT |
6566 | case M_USD: |
6567 | s = "sdl"; | |
6568 | s2 = "sdr"; | |
6569 | off = 7; | |
6570 | goto usw; | |
3d3c5039 | 6571 | case M_USW: |
adcf2b9d ILT |
6572 | s = "swl"; |
6573 | s2 = "swr"; | |
6574 | off = 3; | |
6575 | usw: | |
6576 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6577 | as_bad (_("operand overflow")); |
b9129c6f | 6578 | if (! target_big_endian) |
adcf2b9d ILT |
6579 | offset_expr.X_add_number += off; |
6580 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6581 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6582 | if (! target_big_endian) |
adcf2b9d | 6583 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6584 | else |
adcf2b9d ILT |
6585 | offset_expr.X_add_number += off; |
6586 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6587 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6588 | return; |
3d3c5039 | 6589 | |
adcf2b9d ILT |
6590 | case M_USD_A: |
6591 | s = "sdl"; | |
6592 | s2 = "sdr"; | |
6593 | off = 7; | |
6594 | goto uswa; | |
3d3c5039 | 6595 | case M_USW_A: |
adcf2b9d ILT |
6596 | s = "swl"; |
6597 | s2 = "swr"; | |
6598 | off = 3; | |
6599 | uswa: | |
0dd2d296 | 6600 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6601 | if (breg != 0) |
6602 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6603 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6604 | || mips_opts.isa < 3) | |
6605 | ? "addu" : "daddu"), | |
c625fc23 | 6606 | "d,v,t", AT, AT, breg); |
b9129c6f | 6607 | if (! target_big_endian) |
adcf2b9d | 6608 | expr1.X_add_number = off; |
670a50eb | 6609 | else |
adcf2b9d ILT |
6610 | expr1.X_add_number = 0; |
6611 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6612 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6613 | if (! target_big_endian) |
adcf2b9d ILT |
6614 | expr1.X_add_number = 0; |
6615 | else | |
6616 | expr1.X_add_number = off; | |
6617 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6618 | (int) BFD_RELOC_LO16, AT); | |
6619 | break; | |
6620 | ||
6621 | case M_USH_A: | |
6622 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6623 | if (breg != 0) |
6624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6625 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6626 | || mips_opts.isa < 3) | |
6627 | ? "addu" : "daddu"), | |
c625fc23 | 6628 | "d,v,t", AT, AT, breg); |
b9129c6f | 6629 | if (! target_big_endian) |
adcf2b9d ILT |
6630 | expr1.X_add_number = 0; |
6631 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6632 | (int) BFD_RELOC_LO16, AT); | |
6633 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6634 | treg, 8); | |
b9129c6f | 6635 | if (! target_big_endian) |
adcf2b9d ILT |
6636 | expr1.X_add_number = 1; |
6637 | else | |
6638 | expr1.X_add_number = 0; | |
6639 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6640 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6641 | if (! target_big_endian) |
adcf2b9d ILT |
6642 | expr1.X_add_number = 0; |
6643 | else | |
6644 | expr1.X_add_number = 1; | |
6645 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6646 | (int) BFD_RELOC_LO16, AT); | |
6647 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6648 | treg, 8); | |
6649 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6650 | treg, AT); | |
670a50eb | 6651 | break; |
3d3c5039 ILT |
6652 | |
6653 | default: | |
9218cee0 ILT |
6654 | /* FIXME: Check if this is one of the itbl macros, since they |
6655 | are added dynamically. */ | |
48401fcf | 6656 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8358c818 | 6657 | break; |
3d3c5039 | 6658 | } |
3c83da8a | 6659 | if (mips_opts.noat) |
48401fcf | 6660 | as_warn (_("Macro used $at after \".set noat\"")); |
3d3c5039 ILT |
6661 | } |
6662 | ||
cc5703cd | 6663 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6664 | |
3d3c5039 | 6665 | static void |
cc5703cd | 6666 | mips16_macro (ip) |
3d3c5039 ILT |
6667 | struct mips_cl_insn *ip; |
6668 | { | |
cc5703cd ILT |
6669 | int mask; |
6670 | int xreg, yreg, zreg, tmp; | |
6671 | int icnt; | |
6672 | expressionS expr1; | |
6673 | int dbl; | |
6674 | const char *s, *s2, *s3; | |
3d3c5039 | 6675 | |
cc5703cd | 6676 | mask = ip->insn_mo->mask; |
3d3c5039 | 6677 | |
cc5703cd ILT |
6678 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6679 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6680 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6681 | |
cc5703cd | 6682 | icnt = 0; |
8358c818 | 6683 | |
cc5703cd ILT |
6684 | expr1.X_op = O_constant; |
6685 | expr1.X_op_symbol = NULL; | |
6686 | expr1.X_add_symbol = NULL; | |
6687 | expr1.X_add_number = 1; | |
8358c818 | 6688 | |
cc5703cd | 6689 | dbl = 0; |
517078c1 | 6690 | |
cc5703cd ILT |
6691 | switch (mask) |
6692 | { | |
6693 | default: | |
6694 | internalError (); | |
6695 | ||
6696 | case M_DDIV_3: | |
6697 | dbl = 1; | |
6698 | case M_DIV_3: | |
6699 | s = "mflo"; | |
6700 | goto do_div3; | |
6701 | case M_DREM_3: | |
6702 | dbl = 1; | |
6703 | case M_REM_3: | |
6704 | s = "mfhi"; | |
6705 | do_div3: | |
fbcfacb7 | 6706 | mips_emit_delays (true); |
3c83da8a | 6707 | ++mips_opts.noreorder; |
cc5703cd ILT |
6708 | mips_any_noreorder = 1; |
6709 | macro_build ((char *) NULL, &icnt, NULL, | |
6710 | dbl ? "ddiv" : "div", | |
6711 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6712 | expr1.X_add_number = 2; |
cc5703cd | 6713 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6714 | /* start-sanitize-r5900 */ |
6715 | if (mips_5900) | |
6716 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6717 | else | |
6718 | /* end-sanitize-r5900 */ | |
6719 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6720 | ||
cc5703cd ILT |
6721 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6722 | since that causes an overflow. We should do that as well, | |
6723 | but I don't see how to do the comparisons without a temporary | |
6724 | register. */ | |
3c83da8a | 6725 | --mips_opts.noreorder; |
cc5703cd ILT |
6726 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6727 | break; | |
6728 | ||
6729 | case M_DIVU_3: | |
6730 | s = "divu"; | |
6731 | s2 = "mflo"; | |
6732 | goto do_divu3; | |
6733 | case M_REMU_3: | |
6734 | s = "divu"; | |
6735 | s2 = "mfhi"; | |
6736 | goto do_divu3; | |
6737 | case M_DDIVU_3: | |
6738 | s = "ddivu"; | |
6739 | s2 = "mflo"; | |
6740 | goto do_divu3; | |
6741 | case M_DREMU_3: | |
6742 | s = "ddivu"; | |
6743 | s2 = "mfhi"; | |
6744 | do_divu3: | |
fbcfacb7 | 6745 | mips_emit_delays (true); |
3c83da8a | 6746 | ++mips_opts.noreorder; |
cc5703cd ILT |
6747 | mips_any_noreorder = 1; |
6748 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6749 | expr1.X_add_number = 2; |
cc5703cd | 6750 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 FCE |
6751 | /* start-sanitize-r5900 */ |
6752 | if (mips_5900) | |
6753 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); | |
6754 | else | |
6755 | /* end-sanitize-r5900 */ | |
6756 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
3c83da8a | 6757 | --mips_opts.noreorder; |
cc5703cd ILT |
6758 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6759 | break; | |
6760 | ||
08438bef ILT |
6761 | case M_DMUL: |
6762 | dbl = 1; | |
6763 | case M_MUL: | |
6764 | macro_build ((char *) NULL, &icnt, NULL, | |
6765 | dbl ? "dmultu" : "multu", | |
6766 | "x,y", xreg, yreg); | |
6767 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6768 | return; | |
6769 | ||
cc5703cd ILT |
6770 | case M_DSUBU_I: |
6771 | dbl = 1; | |
6772 | goto do_subu; | |
6773 | case M_SUBU_I: | |
6774 | do_subu: | |
5c6f5923 | 6775 | if (imm_expr.X_op != O_constant) |
48401fcf | 6776 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6777 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6778 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6779 | dbl ? "daddiu" : "addiu", | |
6780 | "y,x,4", yreg, xreg); | |
6781 | break; | |
6782 | ||
6783 | case M_SUBU_I_2: | |
5c6f5923 | 6784 | if (imm_expr.X_op != O_constant) |
48401fcf | 6785 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6786 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6787 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6788 | "x,k", xreg); | |
6789 | break; | |
6790 | ||
6791 | case M_DSUBU_I_2: | |
5c6f5923 | 6792 | if (imm_expr.X_op != O_constant) |
48401fcf | 6793 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6794 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6795 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6796 | "y,j", yreg); | |
6797 | break; | |
6798 | ||
6799 | case M_BEQ: | |
6800 | s = "cmp"; | |
6801 | s2 = "bteqz"; | |
6802 | goto do_branch; | |
6803 | case M_BNE: | |
6804 | s = "cmp"; | |
6805 | s2 = "btnez"; | |
6806 | goto do_branch; | |
6807 | case M_BLT: | |
6808 | s = "slt"; | |
6809 | s2 = "btnez"; | |
6810 | goto do_branch; | |
6811 | case M_BLTU: | |
6812 | s = "sltu"; | |
6813 | s2 = "btnez"; | |
6814 | goto do_branch; | |
6815 | case M_BLE: | |
6816 | s = "slt"; | |
6817 | s2 = "bteqz"; | |
6818 | goto do_reverse_branch; | |
6819 | case M_BLEU: | |
6820 | s = "sltu"; | |
6821 | s2 = "bteqz"; | |
6822 | goto do_reverse_branch; | |
6823 | case M_BGE: | |
6824 | s = "slt"; | |
6825 | s2 = "bteqz"; | |
6826 | goto do_branch; | |
6827 | case M_BGEU: | |
6828 | s = "sltu"; | |
6829 | s2 = "bteqz"; | |
6830 | goto do_branch; | |
6831 | case M_BGT: | |
6832 | s = "slt"; | |
6833 | s2 = "btnez"; | |
6834 | goto do_reverse_branch; | |
6835 | case M_BGTU: | |
6836 | s = "sltu"; | |
6837 | s2 = "btnez"; | |
6838 | ||
6839 | do_reverse_branch: | |
6840 | tmp = xreg; | |
6841 | xreg = yreg; | |
6842 | yreg = tmp; | |
6843 | ||
6844 | do_branch: | |
6845 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6846 | xreg, yreg); | |
6847 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6848 | break; | |
6849 | ||
6850 | case M_BEQ_I: | |
6851 | s = "cmpi"; | |
6852 | s2 = "bteqz"; | |
6853 | s3 = "x,U"; | |
6854 | goto do_branch_i; | |
6855 | case M_BNE_I: | |
6856 | s = "cmpi"; | |
6857 | s2 = "btnez"; | |
6858 | s3 = "x,U"; | |
6859 | goto do_branch_i; | |
6860 | case M_BLT_I: | |
6861 | s = "slti"; | |
6862 | s2 = "btnez"; | |
6863 | s3 = "x,8"; | |
6864 | goto do_branch_i; | |
6865 | case M_BLTU_I: | |
6866 | s = "sltiu"; | |
6867 | s2 = "btnez"; | |
6868 | s3 = "x,8"; | |
6869 | goto do_branch_i; | |
6870 | case M_BLE_I: | |
6871 | s = "slti"; | |
6872 | s2 = "btnez"; | |
6873 | s3 = "x,8"; | |
6874 | goto do_addone_branch_i; | |
6875 | case M_BLEU_I: | |
6876 | s = "sltiu"; | |
6877 | s2 = "btnez"; | |
6878 | s3 = "x,8"; | |
6879 | goto do_addone_branch_i; | |
6880 | case M_BGE_I: | |
6881 | s = "slti"; | |
6882 | s2 = "bteqz"; | |
6883 | s3 = "x,8"; | |
6884 | goto do_branch_i; | |
6885 | case M_BGEU_I: | |
6886 | s = "sltiu"; | |
6887 | s2 = "bteqz"; | |
6888 | s3 = "x,8"; | |
6889 | goto do_branch_i; | |
6890 | case M_BGT_I: | |
6891 | s = "slti"; | |
6892 | s2 = "bteqz"; | |
6893 | s3 = "x,8"; | |
6894 | goto do_addone_branch_i; | |
6895 | case M_BGTU_I: | |
6896 | s = "sltiu"; | |
6897 | s2 = "bteqz"; | |
6898 | s3 = "x,8"; | |
6899 | ||
6900 | do_addone_branch_i: | |
5c6f5923 | 6901 | if (imm_expr.X_op != O_constant) |
48401fcf | 6902 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6903 | ++imm_expr.X_add_number; |
6904 | ||
6905 | do_branch_i: | |
6906 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6907 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6908 | break; | |
18e0764d ILT |
6909 | |
6910 | case M_ABS: | |
6911 | expr1.X_add_number = 0; | |
6912 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6913 | if (xreg != yreg) | |
6914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6915 | "move", "y,X", xreg, yreg); | |
6916 | expr1.X_add_number = 2; | |
6917 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6918 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6919 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6920 | } |
6921 | } | |
6922 | ||
aa2e0460 KR |
6923 | /* For consistency checking, verify that all bits are specified either |
6924 | by the match/mask part of the instruction definition, or by the | |
6925 | operand list. */ | |
6926 | static int | |
6927 | validate_mips_insn (opc) | |
6928 | const struct mips_opcode *opc; | |
6929 | { | |
6930 | const char *p = opc->args; | |
6931 | char c; | |
6932 | unsigned long used_bits = opc->mask; | |
6933 | ||
6934 | if ((used_bits & opc->match) != opc->match) | |
6935 | { | |
48401fcf | 6936 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
aa2e0460 KR |
6937 | opc->name, opc->args); |
6938 | return 0; | |
6939 | } | |
6940 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6941 | while (*p) | |
6942 | switch (c = *p++) | |
6943 | { | |
6944 | case ',': break; | |
6945 | case '(': break; | |
6946 | case ')': break; | |
6947 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6948 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6949 | case 'A': break; | |
6950 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6951 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6952 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6953 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6954 | case 'F': break; | |
6955 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6956 | case 'I': break; | |
6957 | case 'L': break; | |
6958 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6959 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6960 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6961 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6962 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6963 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6964 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6965 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6966 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6967 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6968 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6969 | case 'f': break; | |
6970 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6971 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6972 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6973 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6974 | case 'l': break; | |
6975 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6976 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
40f0c904 | 6977 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
aa2e0460 KR |
6978 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
6979 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6980 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6981 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6982 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6983 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6984 | case 'x': break; | |
6985 | case 'z': break; | |
aa2e0460 | 6986 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
3c69baf9 GRK |
6987 | /* start-sanitize-r5900 */ |
6988 | case '0': USE_BITS (OP_MASK_VADDI, OP_SH_VADDI); break; | |
6989 | case '1': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
6990 | case '2': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
6991 | case '3': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
6992 | case '4': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
6993 | case '5': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
6994 | case '6': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
6995 | case '7': | |
6996 | USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); | |
6997 | USE_BITS (OP_MASK_VUFTF, OP_SH_VUFTF); | |
6998 | break; | |
6999 | case '8': | |
7000 | USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); | |
7001 | USE_BITS (OP_MASK_VUFSF, OP_SH_VUFSF); | |
7002 | break; | |
7003 | case '9': break; | |
7004 | case 'K': break; | |
7005 | case 'X': break; | |
7006 | case 'U': break; | |
7007 | case 'Q': break; | |
7008 | case 'J': break; | |
7009 | case 'O': USE_BITS (OP_MASK_VUCALLMS, OP_SH_VUCALLMS);break; | |
7010 | case '&': USE_BITS (OP_MASK_VUDEST, OP_SH_VUDEST); break; | |
7011 | case '#': | |
7012 | p++; | |
7013 | break; | |
7014 | case '-': break; | |
7015 | case '+': break; | |
7016 | /* end-sanitize-r5900 */ | |
1c6f3441 | 7017 | /* start-sanitize-vr5400 */ |
aa2e0460 KR |
7018 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7019 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7020 | case '[': break; | |
7021 | case ']': break; | |
7022 | /* end-sanitize-vr5400 */ | |
7023 | default: | |
48401fcf | 7024 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
aa2e0460 KR |
7025 | c, opc->name, opc->args); |
7026 | return 0; | |
7027 | } | |
7028 | #undef USE_BITS | |
aa2e0460 KR |
7029 | if (used_bits != 0xffffffff) |
7030 | { | |
48401fcf | 7031 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
aa2e0460 KR |
7032 | ~used_bits & 0xffffffff, opc->name, opc->args); |
7033 | return 0; | |
7034 | } | |
7035 | return 1; | |
7036 | } | |
7037 | ||
cc5703cd ILT |
7038 | /* This routine assembles an instruction into its binary format. As a |
7039 | side effect, it sets one of the global variables imm_reloc or | |
7040 | offset_reloc to the type of relocation to do if one of the operands | |
7041 | is an address expression. */ | |
7042 | ||
7043 | static void | |
7044 | mips_ip (str, ip) | |
7045 | char *str; | |
7046 | struct mips_cl_insn *ip; | |
7047 | { | |
7048 | char *s; | |
7049 | const char *args; | |
7050 | char c; | |
7051 | struct mips_opcode *insn; | |
7052 | char *argsStart; | |
7053 | unsigned int regno; | |
7054 | unsigned int lastregno = 0; | |
7055 | char *s_reset; | |
059a6388 | 7056 | char save_c = 0; |
48401fcf | 7057 | int full_opcode_match = 1; |
cc5703cd ILT |
7058 | |
7059 | insn_error = NULL; | |
7060 | ||
059a6388 JL |
7061 | /* If the instruction contains a '.', we first try to match an instruction |
7062 | including the '.'. Then we try again without the '.'. */ | |
7063 | insn = NULL; | |
e2e5acfa | 7064 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 7065 | continue; |
059a6388 JL |
7066 | |
7067 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7068 | the call to hash_find. Save the character we replaced just in case we | |
7069 | have to re-parse the instruction. */ | |
1857d1e6 | 7070 | if (isspace (*s)) |
059a6388 JL |
7071 | { |
7072 | save_c = *s; | |
7073 | *s++ = '\0'; | |
7074 | } | |
7075 | ||
7076 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
1857d1e6 | 7077 | |
059a6388 JL |
7078 | /* If we didn't find the instruction in the opcode table, try again, but |
7079 | this time with just the instruction up to, but not including the | |
7080 | first '.'. */ | |
7081 | if (insn == NULL) | |
cc5703cd | 7082 | { |
059a6388 JL |
7083 | /* Restore the character we overwrite above (if any). */ |
7084 | if (save_c) | |
7085 | *(--s) = save_c; | |
7086 | ||
7087 | /* Scan up to the first '.' or whitespace. */ | |
7088 | for (s = str; *s != '\0' && *s != '.' && !isspace (*s); ++s) | |
7089 | continue; | |
7090 | ||
7091 | /* If we did not find a '.', then we can quit now. */ | |
7092 | if (*s != '.') | |
7093 | { | |
7094 | insn_error = "unrecognized opcode"; | |
7095 | return; | |
7096 | } | |
7097 | ||
7098 | /* Lookup the instruction in the hash table. */ | |
7099 | *s++ = '\0'; | |
7100 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7101 | { | |
7102 | insn_error = "unrecognized opcode"; | |
7103 | return; | |
7104 | } | |
48401fcf TT |
7105 | |
7106 | full_opcode_match = 0; | |
cc5703cd | 7107 | } |
059a6388 | 7108 | |
cc5703cd ILT |
7109 | argsStart = s; |
7110 | for (;;) | |
7111 | { | |
7112 | int insn_isa; | |
a652f74c | 7113 | boolean ok; |
cc5703cd ILT |
7114 | |
7115 | assert (strcmp (insn->name, str) == 0); | |
7116 | ||
1c6f3441 | 7117 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 7118 | insn_isa = 1; |
5c6f5923 | 7119 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 7120 | insn_isa = 2; |
5c6f5923 | 7121 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 7122 | insn_isa = 3; |
5c6f5923 | 7123 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
7124 | insn_isa = 4; |
7125 | else | |
931a1858 | 7126 | insn_isa = 15; |
cc5703cd | 7127 | |
a652f74c ILT |
7128 | if (insn_isa <= mips_opts.isa) |
7129 | ok = true; | |
7130 | else if (insn->pinfo == INSN_MACRO) | |
7131 | ok = false; | |
7132 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
7133 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
7134 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
2d035a50 GRK |
7135 | /* start-sanitize-vr4320 */ |
7136 | || (mips_4320 && (insn->membership & INSN_4320) != 0) | |
7137 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
7138 | /* start-sanitize-tx49 */ |
7139 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
7140 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
7141 | /* start-sanitize-r5900 */ |
7142 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
7143 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
7144 | /* start-sanitize-vr5400 */ |
7145 | || (mips_5400 && (insn->membership & INSN_5400) != 0) | |
7146 | /* end-sanitize-vr5400 */ | |
a652f74c | 7147 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7148 | ok = true; |
a652f74c ILT |
7149 | else |
7150 | ok = false; | |
7151 | ||
b2cf4548 DE |
7152 | if (insn->pinfo != INSN_MACRO) |
7153 | { | |
7154 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
7155 | ok = false; | |
7156 | /* start-sanitize-r5900 */ | |
7157 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
7158 | ok = false; | |
7159 | /* end-sanitize-r5900 */ | |
7160 | } | |
1c6f3441 | 7161 | |
a652f74c | 7162 | if (! ok) |
cc5703cd ILT |
7163 | { |
7164 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7165 | && strcmp (insn->name, insn[1].name) == 0) | |
7166 | { | |
7167 | ++insn; | |
7168 | continue; | |
7169 | } | |
6fd819cf GRK |
7170 | if (insn_isa == 15 |
7171 | || insn_isa <= mips_opts.isa) | |
48401fcf | 7172 | insn_error = _("opcode not supported on this processor"); |
cc5703cd ILT |
7173 | else |
7174 | { | |
7175 | static char buf[100]; | |
7176 | ||
48401fcf | 7177 | sprintf (buf, _("opcode requires -mips%d or greater"), insn_isa); |
cc5703cd ILT |
7178 | insn_error = buf; |
7179 | } | |
7180 | return; | |
7181 | } | |
8358c818 | 7182 | |
670a50eb ILT |
7183 | ip->insn_mo = insn; |
7184 | ip->insn_opcode = insn->match; | |
7185 | for (args = insn->args;; ++args) | |
7186 | { | |
7187 | if (*s == ' ') | |
7188 | ++s; | |
7189 | switch (*args) | |
7190 | { | |
7191 | case '\0': /* end of args */ | |
7192 | if (*s == '\0') | |
7193 | return; | |
7194 | break; | |
3d3c5039 ILT |
7195 | |
7196 | case ',': | |
670a50eb ILT |
7197 | if (*s++ == *args) |
7198 | continue; | |
7199 | s--; | |
7200 | switch (*++args) | |
7201 | { | |
3d3c5039 ILT |
7202 | case 'r': |
7203 | case 'v': | |
670a50eb ILT |
7204 | ip->insn_opcode |= lastregno << 21; |
7205 | continue; | |
3d3c5039 ILT |
7206 | |
7207 | case 'w': | |
7208 | case 'W': | |
670a50eb ILT |
7209 | ip->insn_opcode |= lastregno << 16; |
7210 | continue; | |
3d3c5039 ILT |
7211 | |
7212 | case 'V': | |
670a50eb ILT |
7213 | ip->insn_opcode |= lastregno << 11; |
7214 | continue; | |
3d3c5039 | 7215 | } |
670a50eb | 7216 | break; |
3d3c5039 ILT |
7217 | |
7218 | case '(': | |
059a6388 | 7219 | /* Handle optional base register. |
670a50eb ILT |
7220 | Either the base register is omitted or |
7221 | we must have a left paren. */ | |
059a6388 JL |
7222 | /* This is dependent on the next operand specifier |
7223 | is a base register specification. */ | |
7224 | assert (args[1] == 'b' || args[1] == '5' | |
7225 | || args[1] == '-' || args[1] == '4'); | |
670a50eb ILT |
7226 | if (*s == '\0') |
7227 | return; | |
3d3c5039 | 7228 | |
670a50eb | 7229 | case ')': /* these must match exactly */ |
aa2e0460 KR |
7230 | /* start-sanitize-vr5400 */ |
7231 | case '[': | |
7232 | case ']': | |
7233 | /* end-sanitize-vr5400 */ | |
059a6388 JL |
7234 | /* start-sanitize-r5900 */ |
7235 | case '-': | |
7236 | case '+': | |
7237 | /* end-sanitize-r5900 */ | |
670a50eb | 7238 | if (*s++ == *args) |
3d3c5039 | 7239 | continue; |
670a50eb ILT |
7240 | break; |
7241 | ||
7242 | case '<': /* must be at least one digit */ | |
7243 | /* | |
7244 | * According to the manual, if the shift amount is greater | |
7245 | * than 31 or less than 0 the the shift amount should be | |
7246 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7247 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7248 | */ |
7249 | my_getExpression (&imm_expr, s); | |
7250 | check_absolute_expr (ip, &imm_expr); | |
7251 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7252 | { | |
48401fcf | 7253 | as_warn (_("Improper shift amount (%ld)"), |
58d4951d | 7254 | (long) imm_expr.X_add_number); |
9226253a | 7255 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7256 | } |
7257 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7258 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7259 | s = expr_end; |
7260 | continue; | |
7261 | ||
56c96faa ILT |
7262 | case '>': /* shift amount minus 32 */ |
7263 | my_getExpression (&imm_expr, s); | |
7264 | check_absolute_expr (ip, &imm_expr); | |
7265 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7266 | || (unsigned long) imm_expr.X_add_number > 63) | |
7267 | break; | |
7268 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7269 | imm_expr.X_op = O_absent; | |
7270 | s = expr_end; | |
7271 | continue; | |
7272 | ||
059a6388 JL |
7273 | /* start-sanitize-r5900 */ |
7274 | case '0': /* 5 bit signed immediate at 6 */ | |
7275 | my_getExpression (&imm_expr, s); | |
7276 | check_absolute_expr (ip, &imm_expr); | |
7277 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7278 | || ((imm_expr.X_add_number < -16 | |
7279 | || imm_expr.X_add_number >= 16) | |
7280 | && imm_expr.X_op == O_constant)) | |
7281 | { | |
7282 | if (imm_expr.X_op != O_constant | |
7283 | && imm_expr.X_op != O_big) | |
7284 | insn_error = "absolute expression required"; | |
7285 | else | |
48401fcf | 7286 | as_bad (_("5 bit expression not in range -16..15")); |
059a6388 JL |
7287 | } |
7288 | ip->insn_opcode |= (imm_expr.X_add_number) << 6; | |
7289 | imm_expr.X_op = O_absent; | |
7290 | s = expr_end; | |
7291 | continue; | |
7292 | ||
65a17223 FCE |
7293 | case '9': /* vi27 for vcallmsr */ |
7294 | if (strncmp (s, "vi27", 4) == 0) | |
059a6388 JL |
7295 | s += 4; |
7296 | else | |
48401fcf | 7297 | as_bad (_("expected vi27")); |
059a6388 JL |
7298 | continue; |
7299 | ||
981ce186 JL |
7300 | case '#': /* escape character */ |
7301 | /* '#' specifies that we've got an optional suffix to this | |
059a6388 JL |
7302 | operand that must match exactly (if it exists). */ |
7303 | if (*s != '\0' && *s != ',' | |
7304 | && *s != ' ' && *s != '\t' && *s != '\n') | |
7305 | { | |
7306 | if (*s == *(args + 1)) | |
7307 | { | |
7308 | s++; | |
7309 | args++; | |
7310 | continue; | |
7311 | } | |
7312 | break; | |
7313 | } | |
7314 | args++; | |
7315 | continue; | |
7316 | ||
7317 | case 'K': /* DEST operand completer (optional), must | |
7318 | match previous dest if specified. */ | |
7319 | case '&': /* DEST instruction completer */ | |
7320 | { | |
7321 | int w,x,y,z; | |
7322 | static int last_h; | |
7323 | ||
7324 | w = x = y = z = 0; | |
7325 | ||
7326 | /* Parse the completer. */ | |
7327 | s_reset = s; | |
48401fcf TT |
7328 | while ((!full_opcode_match || *args == 'K') |
7329 | && *s != '\0' && *s != ' ' && *s != ',') | |
059a6388 JL |
7330 | { |
7331 | if (*s == 'w') | |
7332 | w++; | |
7333 | else if (*s == 'x') | |
7334 | x++; | |
7335 | else if (*s == 'y') | |
7336 | y++; | |
7337 | else if (*s == 'z') | |
7338 | z++; | |
7339 | else | |
7340 | { | |
7341 | insn_error = "Invalid dest specification"; | |
48401fcf | 7342 | break; |
059a6388 JL |
7343 | } |
7344 | s++; | |
7345 | } | |
7346 | ||
48401fcf TT |
7347 | if (insn_error) |
7348 | continue; | |
7349 | ||
059a6388 JL |
7350 | /* Each completer can only appear once. */ |
7351 | if (w > 1 || x > 1 || y > 1 || z > 1) | |
7352 | { | |
7353 | insn_error = "Invalid dest specification"; | |
7354 | continue; | |
7355 | } | |
7356 | ||
7357 | /* If this is the opcode completer, then we must insert | |
7358 | the appropriate value into the insn. */ | |
7359 | if (*args == '&') | |
7360 | { | |
48401fcf TT |
7361 | /* Not strictly in the specs, but requested by users. */ |
7362 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7363 | w = x = y = z = 1; | |
7364 | ||
059a6388 JL |
7365 | ip->insn_opcode |= ((w << 21) | (x << 24) |
7366 | | (y << 23) | (z << 22)); | |
7367 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7368 | } | |
7369 | else | |
7370 | { | |
7371 | int temp; | |
7372 | ||
7373 | /* This is the operand completer, make sure it matches | |
7374 | the previous opcode completer. */ | |
7375 | temp = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7376 | if (temp && temp != last_h) | |
7377 | { | |
7378 | insn_error = "DEST field in operand does not match DEST field in instruction"; | |
7379 | continue; | |
7380 | } | |
7381 | ||
7382 | } | |
7383 | ||
7384 | continue; | |
7385 | } | |
7386 | ||
7387 | case 'J': /* vu0 I register */ | |
7388 | if (s[0] == 'I') | |
7389 | s += 1; | |
7390 | else | |
7391 | insn_error = "operand `I' expected"; | |
7392 | continue; | |
7393 | ||
7394 | case 'Q': /* vu0 Q register */ | |
7395 | if (s[0] == 'Q') | |
7396 | s += 1; | |
7397 | else | |
7398 | insn_error = "operand `Q' expected"; | |
7399 | continue; | |
7400 | ||
7401 | case 'X': /* vu0 R register */ | |
7402 | if (s[0] == 'R') | |
7403 | s += 1; | |
7404 | else | |
7405 | insn_error = "operand `R' expected"; | |
7406 | continue; | |
7407 | ||
7408 | case 'U': /* vu0 ACC register */ | |
7409 | if (s[0] == 'A' && s[1] == 'C' && s[2] == 'C') | |
7410 | s += 3; | |
7411 | else | |
7412 | insn_error = "operand `ACC' expected"; | |
7413 | continue; | |
0bc0e337 JL |
7414 | |
7415 | case 'O': | |
7416 | my_getSmallExpression (&imm_expr, s); | |
7417 | imm_reloc = BFD_RELOC_MIPS15_S3; | |
7418 | s = expr_end; | |
7419 | continue; | |
059a6388 JL |
7420 | /* end-sanitize-r5900 */ |
7421 | ||
9226253a | 7422 | case 'k': /* cache code */ |
d8a1c247 | 7423 | case 'h': /* prefx code */ |
9226253a ILT |
7424 | my_getExpression (&imm_expr, s); |
7425 | check_absolute_expr (ip, &imm_expr); | |
7426 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7427 | { | |
48401fcf | 7428 | as_warn (_("Invalid value for `%s' (%lu)"), |
d8a1c247 | 7429 | ip->insn_mo->name, |
9226253a ILT |
7430 | (unsigned long) imm_expr.X_add_number); |
7431 | imm_expr.X_add_number &= 0x1f; | |
7432 | } | |
d8a1c247 KR |
7433 | if (*args == 'k') |
7434 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7435 | else | |
7436 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7437 | imm_expr.X_op = O_absent; |
7438 | s = expr_end; | |
7439 | continue; | |
7440 | ||
670a50eb ILT |
7441 | case 'c': /* break code */ |
7442 | my_getExpression (&imm_expr, s); | |
7443 | check_absolute_expr (ip, &imm_expr); | |
7444 | if ((unsigned) imm_expr.X_add_number > 1023) | |
40f0c904 FCE |
7445 | { |
7446 | as_warn (_("Illegal break code (%ld)"), | |
7447 | (long) imm_expr.X_add_number); | |
7448 | imm_expr.X_add_number &= 0x3ff; | |
7449 | } | |
670a50eb | 7450 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7451 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7452 | s = expr_end; |
7453 | continue; | |
7454 | ||
40f0c904 FCE |
7455 | case 'q': /* lower break code */ |
7456 | my_getExpression (&imm_expr, s); | |
7457 | check_absolute_expr (ip, &imm_expr); | |
7458 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7459 | { | |
7460 | as_warn (_("Illegal lower break code (%ld)"), | |
7461 | (long) imm_expr.X_add_number); | |
7462 | imm_expr.X_add_number &= 0x3ff; | |
7463 | } | |
7464 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7465 | imm_expr.X_op = O_absent; | |
7466 | s = expr_end; | |
7467 | continue; | |
7468 | ||
918692a5 ILT |
7469 | case 'B': /* syscall code */ |
7470 | my_getExpression (&imm_expr, s); | |
7471 | check_absolute_expr (ip, &imm_expr); | |
7472 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
48401fcf | 7473 | as_warn (_("Illegal syscall code (%ld)"), |
58d4951d | 7474 | (long) imm_expr.X_add_number); |
918692a5 | 7475 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7476 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7477 | s = expr_end; |
7478 | continue; | |
7479 | ||
0aa07269 ILT |
7480 | case 'C': /* Coprocessor code */ |
7481 | my_getExpression (&imm_expr, s); | |
7482 | check_absolute_expr (ip, &imm_expr); | |
7483 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7484 | { | |
48401fcf | 7485 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
58d4951d | 7486 | (long) imm_expr.X_add_number); |
0aa07269 ILT |
7487 | imm_expr.X_add_number &= ((1<<25) - 1); |
7488 | } | |
7489 | ip->insn_opcode |= imm_expr.X_add_number; | |
7490 | imm_expr.X_op = O_absent; | |
7491 | s = expr_end; | |
7492 | continue; | |
7493 | ||
65d2c7d3 JL |
7494 | case 'P': /* Performance register */ |
7495 | my_getExpression (&imm_expr, s); | |
7496 | check_absolute_expr (ip, &imm_expr); | |
7497 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7498 | { | |
48401fcf | 7499 | as_warn (_("Invalidate performance regster (%ld)"), |
65d2c7d3 JL |
7500 | (long) imm_expr.X_add_number); |
7501 | imm_expr.X_add_number &= 1; | |
7502 | } | |
7503 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7504 | imm_expr.X_op = O_absent; | |
7505 | s = expr_end; | |
7506 | continue; | |
7507 | ||
670a50eb ILT |
7508 | case 'b': /* base register */ |
7509 | case 'd': /* destination register */ | |
7510 | case 's': /* source register */ | |
7511 | case 't': /* target register */ | |
7512 | case 'r': /* both target and source */ | |
7513 | case 'v': /* both dest and source */ | |
7514 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7515 | case 'E': /* coprocessor target register */ |
7516 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7517 | case 'x': /* ignore register name */ |
ff3a5c18 | 7518 | case 'z': /* must be zero register */ |
670a50eb ILT |
7519 | s_reset = s; |
7520 | if (s[0] == '$') | |
7521 | { | |
7522 | if (isdigit (s[1])) | |
7523 | { | |
7524 | ++s; | |
7525 | regno = 0; | |
7526 | do | |
7527 | { | |
7528 | regno *= 10; | |
7529 | regno += *s - '0'; | |
7530 | ++s; | |
7531 | } | |
7532 | while (isdigit (*s)); | |
0aa07269 | 7533 | if (regno > 31) |
48401fcf | 7534 | as_bad (_("Invalid register number (%d)"), regno); |
670a50eb | 7535 | } |
0dd2d296 ILT |
7536 | else if (*args == 'E' || *args == 'G') |
7537 | goto notreg; | |
7538 | else | |
670a50eb | 7539 | { |
0aa07269 ILT |
7540 | if (s[1] == 'f' && s[2] == 'p') |
7541 | { | |
7542 | s += 3; | |
9226253a | 7543 | regno = FP; |
0aa07269 ILT |
7544 | } |
7545 | else if (s[1] == 's' && s[2] == 'p') | |
7546 | { | |
7547 | s += 3; | |
9226253a | 7548 | regno = SP; |
0aa07269 ILT |
7549 | } |
7550 | else if (s[1] == 'g' && s[2] == 'p') | |
7551 | { | |
7552 | s += 3; | |
9226253a | 7553 | regno = GP; |
0aa07269 ILT |
7554 | } |
7555 | else if (s[1] == 'a' && s[2] == 't') | |
7556 | { | |
7557 | s += 3; | |
9226253a | 7558 | regno = AT; |
0aa07269 | 7559 | } |
b2b8c24e ILT |
7560 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7561 | { | |
7562 | s += 4; | |
7563 | regno = KT0; | |
7564 | } | |
7565 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7566 | { | |
7567 | s += 4; | |
7568 | regno = KT1; | |
7569 | } | |
efec4a28 DP |
7570 | else if (itbl_have_entries) |
7571 | { | |
7572 | char *p, *n; | |
7573 | int r; | |
7574 | ||
7575 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7576 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7577 | |
7578 | /* See if this is a register defined in an | |
7579 | itbl entry */ | |
9218cee0 ILT |
7580 | r = itbl_get_reg_val (n); |
7581 | if (r) | |
efec4a28 | 7582 | { |
9218cee0 ILT |
7583 | /* Get_field advances to the start of |
7584 | the next field, so we need to back | |
7585 | rack to the end of the last field. */ | |
efec4a28 | 7586 | if (p) |
9218cee0 | 7587 | s = p - 1; |
efec4a28 | 7588 | else |
9218cee0 | 7589 | s = strchr (s,'\0'); |
efec4a28 DP |
7590 | regno = r; |
7591 | } | |
7592 | else | |
7593 | goto notreg; | |
7594 | } | |
0aa07269 ILT |
7595 | else |
7596 | goto notreg; | |
670a50eb | 7597 | } |
9753202d | 7598 | if (regno == AT |
3c83da8a | 7599 | && ! mips_opts.noat |
9753202d ILT |
7600 | && *args != 'E' |
7601 | && *args != 'G') | |
48401fcf | 7602 | as_warn (_("Used $at without \".set noat\"")); |
670a50eb ILT |
7603 | c = *args; |
7604 | if (*s == ' ') | |
7605 | s++; | |
7606 | if (args[1] != *s) | |
7607 | { | |
7608 | if (c == 'r' || c == 'v' || c == 'w') | |
7609 | { | |
7610 | regno = lastregno; | |
7611 | s = s_reset; | |
7612 | args++; | |
7613 | } | |
7614 | } | |
ff3a5c18 ILT |
7615 | /* 'z' only matches $0. */ |
7616 | if (c == 'z' && regno != 0) | |
7617 | break; | |
efec4a28 DP |
7618 | |
7619 | /* Now that we have assembled one operand, we use the args string | |
7620 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7621 | switch (c) |
7622 | { | |
3d3c5039 ILT |
7623 | case 'r': |
7624 | case 's': | |
7625 | case 'v': | |
7626 | case 'b': | |
670a50eb ILT |
7627 | ip->insn_opcode |= regno << 21; |
7628 | break; | |
3d3c5039 | 7629 | case 'd': |
918692a5 | 7630 | case 'G': |
670a50eb ILT |
7631 | ip->insn_opcode |= regno << 11; |
7632 | break; | |
3d3c5039 ILT |
7633 | case 'w': |
7634 | case 't': | |
918692a5 | 7635 | case 'E': |
670a50eb | 7636 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7637 | break; |
7638 | case 'x': | |
7639 | /* This case exists because on the r3000 trunc | |
7640 | expands into a macro which requires a gp | |
7641 | register. On the r6000 or r4000 it is | |
7642 | assembled into a single instruction which | |
7643 | ignores the register. Thus the insn version | |
7644 | is MIPS_ISA2 and uses 'x', and the macro | |
7645 | version is MIPS_ISA1 and uses 't'. */ | |
7646 | break; | |
ff3a5c18 ILT |
7647 | case 'z': |
7648 | /* This case is for the div instruction, which | |
7649 | acts differently if the destination argument | |
7650 | is $0. This only matches $0, and is checked | |
7651 | outside the switch. */ | |
7652 | break; | |
efec4a28 DP |
7653 | case 'D': |
7654 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7655 | break; | |
9218cee0 ILT |
7656 | /* What about all other operands like 'i', which |
7657 | can be specified in the opcode table? */ | |
3d3c5039 | 7658 | } |
670a50eb ILT |
7659 | lastregno = regno; |
7660 | continue; | |
3d3c5039 ILT |
7661 | } |
7662 | notreg: | |
670a50eb ILT |
7663 | switch (*args++) |
7664 | { | |
3d3c5039 ILT |
7665 | case 'r': |
7666 | case 'v': | |
670a50eb ILT |
7667 | ip->insn_opcode |= lastregno << 21; |
7668 | continue; | |
3d3c5039 | 7669 | case 'w': |
670a50eb ILT |
7670 | ip->insn_opcode |= lastregno << 16; |
7671 | continue; | |
3d3c5039 | 7672 | } |
670a50eb | 7673 | break; |
3d3c5039 | 7674 | |
670a50eb ILT |
7675 | case 'D': /* floating point destination register */ |
7676 | case 'S': /* floating point source register */ | |
7677 | case 'T': /* floating point target register */ | |
d8a1c247 | 7678 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7679 | case 'V': |
7680 | case 'W': | |
059a6388 JL |
7681 | /* start-sanitize-r5900 */ |
7682 | case '1': /* vu0 fp reg position 1 */ | |
7683 | case '2': /* vu0 fp reg position 2 */ | |
7684 | case '3': /* vu0 fp reg position 3 */ | |
7685 | case '4': /* vu0 int reg position 1 */ | |
7686 | case '5': /* vu0 int reg position 2 */ | |
7687 | case '6': /* vu0 int reg position 3 */ | |
7688 | case '7': /* vu0 fp reg with ftf modifier */ | |
7689 | case '8': /* vu0 fp reg with fsf modifier */ | |
7690 | /* end-sanitize-r5900 */ | |
670a50eb ILT |
7691 | s_reset = s; |
7692 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7693 | { | |
7694 | s += 2; | |
7695 | regno = 0; | |
7696 | do | |
7697 | { | |
7698 | regno *= 10; | |
7699 | regno += *s - '0'; | |
7700 | ++s; | |
7701 | } | |
7702 | while (isdigit (*s)); | |
7703 | ||
7704 | if (regno > 31) | |
48401fcf | 7705 | as_bad (_("Invalid float register number (%d)"), regno); |
670a50eb | 7706 | |
9226253a | 7707 | if ((regno & 1) != 0 |
3c83da8a | 7708 | && mips_opts.isa < 3 |
538034cf ILT |
7709 | && ! (strcmp (str, "mtc1") == 0 |
7710 | || strcmp (str, "mfc1") == 0 | |
7711 | || strcmp (str, "lwc1") == 0 | |
7712 | || strcmp (str, "swc1") == 0 | |
7713 | || strcmp (str, "l.s") == 0 | |
7714 | || strcmp (str, "s.s") == 0)) | |
48401fcf | 7715 | as_warn (_("Float register should be even, was %d"), |
670a50eb ILT |
7716 | regno); |
7717 | ||
7718 | c = *args; | |
7719 | if (*s == ' ') | |
7720 | s++; | |
7721 | if (args[1] != *s) | |
7722 | { | |
7723 | if (c == 'V' || c == 'W') | |
7724 | { | |
7725 | regno = lastregno; | |
7726 | s = s_reset; | |
7727 | args++; | |
3d3c5039 ILT |
7728 | } |
7729 | } | |
670a50eb ILT |
7730 | switch (c) |
7731 | { | |
3d3c5039 | 7732 | case 'D': |
670a50eb ILT |
7733 | ip->insn_opcode |= regno << 6; |
7734 | break; | |
3d3c5039 ILT |
7735 | case 'V': |
7736 | case 'S': | |
670a50eb ILT |
7737 | ip->insn_opcode |= regno << 11; |
7738 | break; | |
3d3c5039 ILT |
7739 | case 'W': |
7740 | case 'T': | |
670a50eb | 7741 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7742 | break; |
7743 | case 'R': | |
7744 | ip->insn_opcode |= regno << 21; | |
7745 | break; | |
3d3c5039 | 7746 | } |
670a50eb ILT |
7747 | lastregno = regno; |
7748 | continue; | |
3d3c5039 | 7749 | } |
059a6388 JL |
7750 | |
7751 | /* start-sanitize-r5900 */ | |
7752 | /* Handle vf and vi regsiters for vu0. */ | |
7753 | if (s[0] == 'v' | |
7754 | && (s[1] == 'f' || s[1] == 'i') | |
7755 | && isdigit (s[2])) | |
7756 | { | |
7757 | s += 2; | |
7758 | regno = 0; | |
7759 | do | |
7760 | { | |
7761 | regno *= 10; | |
7762 | regno += *s - '0'; | |
7763 | ++s; | |
7764 | } | |
7765 | while (isdigit (*s)); | |
7766 | ||
7767 | if (regno > 31) | |
48401fcf | 7768 | as_bad (_("Invalid vu0 register number (%d)"), regno); |
059a6388 JL |
7769 | |
7770 | c = *args; | |
7771 | ||
7772 | if (c == '7' || c == '8') | |
7773 | { | |
7774 | int value; | |
7775 | ||
7776 | switch (*s) | |
7777 | { | |
7778 | case 'w': | |
7779 | value = 3; | |
7780 | s++; | |
7781 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7782 | break; | |
7783 | case 'x': | |
7784 | value = 0; | |
7785 | s++; | |
7786 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7787 | break; | |
7788 | case 'y': | |
7789 | value = 1; | |
7790 | s++; | |
7791 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7792 | break; | |
7793 | case 'z': | |
7794 | value = 2; | |
7795 | s++; | |
7796 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7797 | break; | |
7798 | default: | |
48401fcf | 7799 | as_bad (_("Invalid FSF/FTF specification")); |
059a6388 JL |
7800 | } |
7801 | } | |
7802 | ||
7803 | if (*s == ' ') | |
7804 | s++; | |
7805 | if (args[1] != *s) | |
7806 | { | |
7807 | if (c == 'V' || c == 'W') | |
7808 | { | |
7809 | regno = lastregno; | |
7810 | s = s_reset; | |
7811 | args++; | |
7812 | } | |
7813 | } | |
7814 | switch (c) | |
7815 | { | |
7816 | case '1': | |
7817 | case '4': | |
7818 | case '7': | |
7819 | ip->insn_opcode |= regno << 16; | |
7820 | break; | |
7821 | case '2': | |
7822 | case '5': | |
7823 | case '8': | |
7824 | ip->insn_opcode |= regno << 11; | |
7825 | break; | |
7826 | case '3': | |
7827 | case '6': | |
7828 | ip->insn_opcode |= regno << 6; | |
7829 | break; | |
7830 | } | |
7831 | lastregno = regno; | |
7832 | continue; | |
7833 | } | |
7834 | /* end-sanitize-r5900 */ | |
7835 | ||
670a50eb ILT |
7836 | switch (*args++) |
7837 | { | |
3d3c5039 | 7838 | case 'V': |
670a50eb ILT |
7839 | ip->insn_opcode |= lastregno << 11; |
7840 | continue; | |
3d3c5039 | 7841 | case 'W': |
670a50eb ILT |
7842 | ip->insn_opcode |= lastregno << 16; |
7843 | continue; | |
3d3c5039 | 7844 | } |
670a50eb | 7845 | break; |
3d3c5039 ILT |
7846 | |
7847 | case 'I': | |
670a50eb | 7848 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7849 | if (imm_expr.X_op != O_big |
7850 | && imm_expr.X_op != O_constant) | |
48401fcf | 7851 | insn_error = _("absolute expression required"); |
670a50eb ILT |
7852 | s = expr_end; |
7853 | continue; | |
3d3c5039 ILT |
7854 | |
7855 | case 'A': | |
670a50eb ILT |
7856 | my_getExpression (&offset_expr, s); |
7857 | imm_reloc = BFD_RELOC_32; | |
7858 | s = expr_end; | |
7859 | continue; | |
3d3c5039 ILT |
7860 | |
7861 | case 'F': | |
19ed8960 ILT |
7862 | case 'L': |
7863 | case 'f': | |
7864 | case 'l': | |
7865 | { | |
7866 | int f64; | |
7867 | char *save_in; | |
7868 | char *err; | |
7869 | unsigned char temp[8]; | |
604633ae ILT |
7870 | int len; |
7871 | unsigned int length; | |
19ed8960 ILT |
7872 | segT seg; |
7873 | subsegT subseg; | |
7874 | char *p; | |
7875 | ||
7876 | /* These only appear as the last operand in an | |
7877 | instruction, and every instruction that accepts | |
7878 | them in any variant accepts them in all variants. | |
7879 | This means we don't have to worry about backing out | |
7880 | any changes if the instruction does not match. | |
7881 | ||
7882 | The difference between them is the size of the | |
7883 | floating point constant and where it goes. For 'F' | |
7884 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7885 | is 32 bits. Where the constant is placed is based | |
7886 | on how the MIPS assembler does things: | |
7887 | F -- .rdata | |
7888 | L -- .lit8 | |
7889 | f -- immediate value | |
7890 | l -- .lit4 | |
0dd2d296 | 7891 | |
55933a58 ILT |
7892 | The .lit4 and .lit8 sections are only used if |
7893 | permitted by the -G argument. | |
7894 | ||
7895 | When generating embedded PIC code, we use the | |
7896 | .lit8 section but not the .lit4 section (we can do | |
7897 | .lit4 inline easily; we need to put .lit8 | |
7898 | somewhere in the data segment, and using .lit8 | |
7899 | permits the linker to eventually combine identical | |
7900 | .lit8 entries). */ | |
19ed8960 ILT |
7901 | |
7902 | f64 = *args == 'F' || *args == 'L'; | |
7903 | ||
7904 | save_in = input_line_pointer; | |
7905 | input_line_pointer = s; | |
604633ae ILT |
7906 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7907 | length = len; | |
19ed8960 ILT |
7908 | s = input_line_pointer; |
7909 | input_line_pointer = save_in; | |
7910 | if (err != NULL && *err != '\0') | |
7911 | { | |
48401fcf | 7912 | as_bad (_("Bad floating point constant: %s"), err); |
19ed8960 ILT |
7913 | memset (temp, '\0', sizeof temp); |
7914 | length = f64 ? 8 : 4; | |
7915 | } | |
7916 | ||
7917 | assert (length == (f64 ? 8 : 4)); | |
7918 | ||
0dd2d296 | 7919 | if (*args == 'f' |
55933a58 | 7920 | || (*args == 'l' |
1dc1e798 KR |
7921 | && (! USE_GLOBAL_POINTER_OPT |
7922 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7923 | || g_switch_value < 4 |
7924 | || (temp[0] == 0 && temp[1] == 0) | |
7925 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7926 | { |
7927 | imm_expr.X_op = O_constant; | |
b9129c6f | 7928 | if (! target_big_endian) |
a5586bdc | 7929 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7930 | else |
a5586bdc ILT |
7931 | imm_expr.X_add_number = bfd_getb32 (temp); |
7932 | } | |
7933 | else if (length > 4 | |
7934 | && ((temp[0] == 0 && temp[1] == 0) | |
7935 | || (temp[2] == 0 && temp[3] == 0)) | |
7936 | && ((temp[4] == 0 && temp[5] == 0) | |
7937 | || (temp[6] == 0 && temp[7] == 0))) | |
7938 | { | |
7939 | /* The value is simple enough to load with a | |
7940 | couple of instructions. In mips1 mode, set | |
7941 | imm_expr to the high order 32 bits and | |
7942 | offset_expr to the low order 32 bits. | |
7943 | Otherwise, set imm_expr to the entire 64 bit | |
7944 | constant. */ | |
7945 | if (mips_opts.isa < 3) | |
7946 | { | |
7947 | imm_expr.X_op = O_constant; | |
7948 | offset_expr.X_op = O_constant; | |
7949 | if (! target_big_endian) | |
7950 | { | |
7951 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7952 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7953 | } | |
7954 | else | |
7955 | { | |
7956 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7957 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7958 | } | |
7959 | if (offset_expr.X_add_number == 0) | |
7960 | offset_expr.X_op = O_absent; | |
7961 | } | |
7962 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7963 | { | |
7964 | imm_expr.X_op = O_constant; | |
7965 | if (! target_big_endian) | |
7966 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7967 | else | |
7968 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7969 | } | |
7970 | else | |
7971 | { | |
7972 | imm_expr.X_op = O_big; | |
7973 | imm_expr.X_add_number = 4; | |
7974 | if (! target_big_endian) | |
7975 | { | |
7976 | generic_bignum[0] = bfd_getl16 (temp); | |
7977 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7978 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7979 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7980 | } | |
7981 | else | |
7982 | { | |
7983 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7984 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7985 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7986 | generic_bignum[3] = bfd_getb16 (temp); | |
7987 | } | |
7988 | } | |
19ed8960 ILT |
7989 | } |
7990 | else | |
7991 | { | |
0dd2d296 ILT |
7992 | const char *newname; |
7993 | segT new_seg; | |
7994 | ||
19ed8960 ILT |
7995 | /* Switch to the right section. */ |
7996 | seg = now_seg; | |
7997 | subseg = now_subseg; | |
7998 | switch (*args) | |
7999 | { | |
0dd2d296 | 8000 | default: /* unused default case avoids warnings. */ |
19ed8960 | 8001 | case 'L': |
1113140a | 8002 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 8003 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 8004 | newname = ".lit8"; |
0dd2d296 ILT |
8005 | break; |
8006 | case 'F': | |
d2c71068 | 8007 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
8008 | break; |
8009 | case 'l': | |
1dc1e798 KR |
8010 | assert (!USE_GLOBAL_POINTER_OPT |
8011 | || g_switch_value >= 4); | |
0dd2d296 | 8012 | newname = ".lit4"; |
19ed8960 ILT |
8013 | break; |
8014 | } | |
0dd2d296 | 8015 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
8016 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
8017 | bfd_set_section_flags (stdoutput, new_seg, | |
8018 | (SEC_ALLOC | |
8019 | | SEC_LOAD | |
8020 | | SEC_READONLY | |
8021 | | SEC_DATA)); | |
e2e5acfa JW |
8022 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
8023 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8024 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
8025 | record_alignment (new_seg, 4); |
8026 | else | |
8027 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 | 8028 | if (seg == now_seg) |
48401fcf | 8029 | as_bad (_("Can't use floating point insn in this section")); |
19ed8960 ILT |
8030 | |
8031 | /* Set the argument to the current address in the | |
6e8dda9c | 8032 | section. */ |
19ed8960 ILT |
8033 | offset_expr.X_op = O_symbol; |
8034 | offset_expr.X_add_symbol = | |
8035 | symbol_new ("L0\001", now_seg, | |
8036 | (valueT) frag_now_fix (), frag_now); | |
8037 | offset_expr.X_add_number = 0; | |
8038 | ||
8039 | /* Put the floating point number into the section. */ | |
604633ae | 8040 | p = frag_more ((int) length); |
19ed8960 ILT |
8041 | memcpy (p, temp, length); |
8042 | ||
8043 | /* Switch back to the original section. */ | |
8044 | subseg_set (seg, subseg); | |
8045 | } | |
8046 | } | |
670a50eb ILT |
8047 | continue; |
8048 | ||
8049 | case 'i': /* 16 bit unsigned immediate */ | |
8050 | case 'j': /* 16 bit signed immediate */ | |
8051 | imm_reloc = BFD_RELOC_LO16; | |
8052 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 8053 | if (c != '\0') |
670a50eb ILT |
8054 | { |
8055 | if (c != 'l') | |
8056 | { | |
5ac34ac3 | 8057 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
8058 | imm_expr.X_add_number = |
8059 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8060 | else if (c == 'h') | |
867a58b3 ILT |
8061 | { |
8062 | imm_reloc = BFD_RELOC_HI16_S; | |
8063 | imm_unmatched_hi = true; | |
8064 | } | |
670a50eb ILT |
8065 | else |
8066 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 8067 | } |
670a50eb | 8068 | } |
670a50eb ILT |
8069 | if (*args == 'i') |
8070 | { | |
344a8d61 | 8071 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8072 | || ((imm_expr.X_add_number < 0 |
8073 | || imm_expr.X_add_number >= 0x10000) | |
8074 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
8075 | { |
8076 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8077 | !strcmp (insn->name, insn[1].name)) | |
8078 | break; | |
9753202d ILT |
8079 | if (imm_expr.X_op != O_constant |
8080 | && imm_expr.X_op != O_big) | |
48401fcf | 8081 | insn_error = _("absolute expression required"); |
9753202d | 8082 | else |
48401fcf | 8083 | as_bad (_("16 bit expression not in range 0..65535")); |
99c24539 | 8084 | } |
670a50eb ILT |
8085 | } |
8086 | else | |
8087 | { | |
d9aba805 ILT |
8088 | int more; |
8089 | offsetT max; | |
8090 | ||
be22008b ILT |
8091 | /* The upper bound should be 0x8000, but |
8092 | unfortunately the MIPS assembler accepts numbers | |
8093 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
8094 | we want to be compatible. We only permit this |
8095 | extended range for an instruction which does not | |
8096 | provide any further alternates, since those | |
8097 | alternates may handle other cases. People should | |
8098 | use the numbers they mean, rather than relying on | |
8099 | a mysterious sign extension. */ | |
8100 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8101 | strcmp (insn->name, insn[1].name) == 0); | |
8102 | if (more) | |
8103 | max = 0x8000; | |
8104 | else | |
8105 | max = 0x10000; | |
344a8d61 | 8106 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8107 | || ((imm_expr.X_add_number < -0x8000 |
8108 | || imm_expr.X_add_number >= max) | |
8109 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
8110 | || (more |
8111 | && imm_expr.X_add_number < 0 | |
3c83da8a | 8112 | && mips_opts.isa >= 3 |
d8a1c247 KR |
8113 | && imm_expr.X_unsigned |
8114 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 8115 | { |
d9aba805 | 8116 | if (more) |
99c24539 | 8117 | break; |
9753202d ILT |
8118 | if (imm_expr.X_op != O_constant |
8119 | && imm_expr.X_op != O_big) | |
48401fcf | 8120 | insn_error = _("absolute expression required"); |
9753202d | 8121 | else |
48401fcf | 8122 | as_bad (_("16 bit expression not in range -32768..32767")); |
99c24539 | 8123 | } |
3d3c5039 | 8124 | } |
670a50eb ILT |
8125 | s = expr_end; |
8126 | continue; | |
8127 | ||
8128 | case 'o': /* 16 bit offset */ | |
8129 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
8130 | |
8131 | /* If this value won't fit into a 16 bit offset, then go | |
8132 | find a macro that will generate the 32 bit offset | |
8133 | code pattern. As a special hack, we accept the | |
8134 | difference of two local symbols as a constant. This | |
8135 | is required to suppose embedded PIC switches, which | |
8136 | use an instruction which looks like | |
8137 | lw $4,$L12-$LS12($4) | |
8138 | The problem with handling this in a more general | |
8139 | fashion is that the macro function doesn't expect to | |
8140 | see anything which can be handled in a single | |
8141 | constant instruction. */ | |
6f0b87c3 SS |
8142 | if (c == 0 |
8143 | && (offset_expr.X_op != O_constant | |
8144 | || offset_expr.X_add_number >= 0x8000 | |
8145 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
8146 | && (mips_pic != EMBEDDED_PIC |
8147 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
8148 | || now_seg != text_section |
8149 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
8150 | != text_section))) | |
670a50eb | 8151 | break; |
3d3c5039 | 8152 | |
670a50eb ILT |
8153 | offset_reloc = BFD_RELOC_LO16; |
8154 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
8155 | { |
8156 | assert (offset_expr.X_op == O_constant); | |
8157 | offset_expr.X_add_number = | |
8158 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8159 | } | |
cc5703cd ILT |
8160 | s = expr_end; |
8161 | continue; | |
8162 | ||
8163 | case 'p': /* pc relative offset */ | |
8164 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8165 | my_getExpression (&offset_expr, s); | |
8166 | s = expr_end; | |
8167 | continue; | |
8168 | ||
8169 | case 'u': /* upper 16 bits */ | |
8170 | c = my_getSmallExpression (&imm_expr, s); | |
8171 | if (imm_expr.X_op == O_constant | |
8172 | && (imm_expr.X_add_number < 0 | |
8173 | || imm_expr.X_add_number >= 0x10000)) | |
48401fcf | 8174 | as_bad (_("lui expression not in range 0..65535")); |
cc5703cd ILT |
8175 | imm_reloc = BFD_RELOC_LO16; |
8176 | if (c) | |
8177 | { | |
8178 | if (c != 'l') | |
8179 | { | |
8180 | if (imm_expr.X_op == O_constant) | |
8181 | imm_expr.X_add_number = | |
8182 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8183 | else if (c == 'h') | |
8184 | { | |
8185 | imm_reloc = BFD_RELOC_HI16_S; | |
8186 | imm_unmatched_hi = true; | |
8187 | } | |
8188 | else | |
8189 | imm_reloc = BFD_RELOC_HI16; | |
8190 | } | |
8191 | } | |
8192 | s = expr_end; | |
8193 | continue; | |
8194 | ||
8195 | case 'a': /* 26 bit address */ | |
8196 | my_getExpression (&offset_expr, s); | |
8197 | s = expr_end; | |
8198 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
8199 | continue; | |
8200 | ||
8201 | case 'N': /* 3 bit branch condition code */ | |
8202 | case 'M': /* 3 bit compare condition code */ | |
8203 | if (strncmp (s, "$fcc", 4) != 0) | |
8204 | break; | |
8205 | s += 4; | |
8206 | regno = 0; | |
8207 | do | |
8208 | { | |
8209 | regno *= 10; | |
8210 | regno += *s - '0'; | |
8211 | ++s; | |
8212 | } | |
8213 | while (isdigit (*s)); | |
8214 | if (regno > 7) | |
48401fcf | 8215 | as_bad (_("invalid condition code register $fcc%d"), regno); |
cc5703cd ILT |
8216 | if (*args == 'N') |
8217 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8218 | else | |
8219 | ip->insn_opcode |= regno << OP_SH_CCC; | |
8220 | continue; | |
8221 | ||
b3ed1af3 KR |
8222 | /* start-sanitize-vr5400 */ |
8223 | case 'e': /* must be at least one digit */ | |
8224 | my_getExpression (&imm_expr, s); | |
8225 | check_absolute_expr (ip, &imm_expr); | |
8226 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
8227 | { | |
48401fcf | 8228 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8229 | (long) imm_expr.X_add_number); |
8230 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8231 | } | |
8232 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
8233 | imm_expr.X_op = O_absent; | |
8234 | s = expr_end; | |
8235 | continue; | |
8236 | ||
8237 | case '%': | |
8238 | my_getExpression (&imm_expr, s); | |
8239 | check_absolute_expr (ip, &imm_expr); | |
8240 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
8241 | { | |
48401fcf | 8242 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8243 | (long) imm_expr.X_add_number); |
8244 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8245 | } | |
8246 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
8247 | imm_expr.X_op = O_absent; | |
8248 | s = expr_end; | |
8249 | continue; | |
8250 | ||
8251 | /* end-sanitize-vr5400 */ | |
cc5703cd | 8252 | default: |
48401fcf | 8253 | as_bad (_("bad char = '%c'\n"), *args); |
cc5703cd ILT |
8254 | internalError (); |
8255 | } | |
8256 | break; | |
8257 | } | |
8258 | /* Args don't match. */ | |
8259 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8260 | !strcmp (insn->name, insn[1].name)) | |
8261 | { | |
8262 | ++insn; | |
8263 | s = argsStart; | |
8264 | continue; | |
8265 | } | |
48401fcf | 8266 | insn_error = _("illegal operands"); |
cc5703cd ILT |
8267 | return; |
8268 | } | |
8269 | } | |
8270 | ||
8271 | /* This routine assembles an instruction into its binary format when | |
8272 | assembling for the mips16. As a side effect, it sets one of the | |
8273 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
8274 | relocation to do if one of the operands is an address expression. |
8275 | It also sets mips16_small and mips16_ext if the user explicitly | |
8276 | requested a small or extended instruction. */ | |
cc5703cd ILT |
8277 | |
8278 | static void | |
8279 | mips16_ip (str, ip) | |
8280 | char *str; | |
8281 | struct mips_cl_insn *ip; | |
8282 | { | |
8283 | char *s; | |
cc5703cd ILT |
8284 | const char *args; |
8285 | struct mips_opcode *insn; | |
8286 | char *argsstart; | |
8287 | unsigned int regno; | |
8288 | unsigned int lastregno = 0; | |
8289 | char *s_reset; | |
8290 | ||
8291 | insn_error = NULL; | |
8292 | ||
8728fa92 ILT |
8293 | mips16_small = false; |
8294 | mips16_ext = false; | |
cc5703cd ILT |
8295 | |
8296 | for (s = str; islower (*s); ++s) | |
8297 | ; | |
8298 | switch (*s) | |
8299 | { | |
8300 | case '\0': | |
8301 | break; | |
8302 | ||
8303 | case ' ': | |
8304 | *s++ = '\0'; | |
8305 | break; | |
8306 | ||
8307 | case '.': | |
8308 | if (s[1] == 't' && s[2] == ' ') | |
8309 | { | |
8310 | *s = '\0'; | |
8728fa92 | 8311 | mips16_small = true; |
cc5703cd ILT |
8312 | s += 3; |
8313 | break; | |
8314 | } | |
8315 | else if (s[1] == 'e' && s[2] == ' ') | |
8316 | { | |
8317 | *s = '\0'; | |
8728fa92 | 8318 | mips16_ext = true; |
cc5703cd ILT |
8319 | s += 3; |
8320 | break; | |
8321 | } | |
8322 | /* Fall through. */ | |
8323 | default: | |
48401fcf | 8324 | insn_error = _("unknown opcode"); |
cc5703cd ILT |
8325 | return; |
8326 | } | |
8327 | ||
3c83da8a | 8328 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
8329 | mips16_small = true; |
8330 | ||
cc5703cd ILT |
8331 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
8332 | { | |
48401fcf | 8333 | insn_error = _("unrecognized opcode"); |
cc5703cd ILT |
8334 | return; |
8335 | } | |
8336 | ||
8337 | argsstart = s; | |
8338 | for (;;) | |
8339 | { | |
8340 | assert (strcmp (insn->name, str) == 0); | |
8341 | ||
8342 | ip->insn_mo = insn; | |
8343 | ip->insn_opcode = insn->match; | |
8344 | ip->use_extend = false; | |
8345 | imm_expr.X_op = O_absent; | |
8346 | imm_reloc = BFD_RELOC_UNUSED; | |
8347 | offset_expr.X_op = O_absent; | |
8348 | offset_reloc = BFD_RELOC_UNUSED; | |
8349 | for (args = insn->args; 1; ++args) | |
8350 | { | |
8351 | int c; | |
8352 | ||
8353 | if (*s == ' ') | |
8354 | ++s; | |
8355 | ||
8356 | /* In this switch statement we call break if we did not find | |
8357 | a match, continue if we did find a match, or return if we | |
8358 | are done. */ | |
8359 | ||
8360 | c = *args; | |
8361 | switch (c) | |
8362 | { | |
8363 | case '\0': | |
8364 | if (*s == '\0') | |
8365 | { | |
8366 | /* Stuff the immediate value in now, if we can. */ | |
8367 | if (imm_expr.X_op == O_constant | |
8368 | && imm_reloc > BFD_RELOC_UNUSED | |
8369 | && insn->pinfo != INSN_MACRO) | |
8370 | { | |
15e69f98 ILT |
8371 | mips16_immed ((char *) NULL, 0, |
8372 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
8373 | imm_expr.X_add_number, true, mips16_small, |
8374 | mips16_ext, &ip->insn_opcode, | |
8375 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
8376 | imm_expr.X_op = O_absent; |
8377 | imm_reloc = BFD_RELOC_UNUSED; | |
8378 | } | |
8379 | ||
8380 | return; | |
8381 | } | |
8382 | break; | |
8383 | ||
8384 | case ',': | |
8385 | if (*s++ == c) | |
8386 | continue; | |
8387 | s--; | |
8388 | switch (*++args) | |
8389 | { | |
8390 | case 'v': | |
8391 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8392 | continue; | |
8393 | case 'w': | |
8394 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8395 | continue; | |
8396 | } | |
8397 | break; | |
8398 | ||
8399 | case '(': | |
8400 | case ')': | |
8401 | if (*s++ == c) | |
8402 | continue; | |
8403 | break; | |
8404 | ||
8405 | case 'v': | |
8406 | case 'w': | |
8407 | if (s[0] != '$') | |
8408 | { | |
8409 | if (c == 'v') | |
8410 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8411 | else | |
8412 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8413 | ++args; | |
8414 | continue; | |
8415 | } | |
8416 | /* Fall through. */ | |
8417 | case 'x': | |
8418 | case 'y': | |
8419 | case 'z': | |
8420 | case 'Z': | |
8421 | case '0': | |
8422 | case 'S': | |
8423 | case 'R': | |
8424 | case 'X': | |
8425 | case 'Y': | |
8426 | if (s[0] != '$') | |
8427 | break; | |
8428 | s_reset = s; | |
8429 | if (isdigit (s[1])) | |
8430 | { | |
8431 | ++s; | |
8432 | regno = 0; | |
8433 | do | |
8434 | { | |
8435 | regno *= 10; | |
8436 | regno += *s - '0'; | |
8437 | ++s; | |
8438 | } | |
8439 | while (isdigit (*s)); | |
8440 | if (regno > 31) | |
8441 | { | |
48401fcf | 8442 | as_bad (_("invalid register number (%d)"), regno); |
cc5703cd ILT |
8443 | regno = 2; |
8444 | } | |
8445 | } | |
8446 | else | |
8447 | { | |
8448 | if (s[1] == 'f' && s[2] == 'p') | |
8449 | { | |
8450 | s += 3; | |
8451 | regno = FP; | |
8452 | } | |
8453 | else if (s[1] == 's' && s[2] == 'p') | |
8454 | { | |
8455 | s += 3; | |
8456 | regno = SP; | |
8457 | } | |
8458 | else if (s[1] == 'g' && s[2] == 'p') | |
8459 | { | |
8460 | s += 3; | |
8461 | regno = GP; | |
8462 | } | |
8463 | else if (s[1] == 'a' && s[2] == 't') | |
8464 | { | |
8465 | s += 3; | |
8466 | regno = AT; | |
8467 | } | |
8468 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8469 | { | |
8470 | s += 4; | |
8471 | regno = KT0; | |
8472 | } | |
8473 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8474 | { | |
8475 | s += 4; | |
8476 | regno = KT1; | |
8477 | } | |
8478 | else | |
8479 | break; | |
8480 | } | |
8481 | ||
8482 | if (*s == ' ') | |
8483 | ++s; | |
8484 | if (args[1] != *s) | |
8485 | { | |
8486 | if (c == 'v' || c == 'w') | |
8487 | { | |
8488 | regno = mips16_to_32_reg_map[lastregno]; | |
8489 | s = s_reset; | |
8490 | args++; | |
8491 | } | |
8492 | } | |
8493 | ||
8494 | switch (c) | |
8495 | { | |
8496 | case 'x': | |
8497 | case 'y': | |
8498 | case 'z': | |
8499 | case 'v': | |
8500 | case 'w': | |
8501 | case 'Z': | |
8502 | regno = mips32_to_16_reg_map[regno]; | |
8503 | break; | |
8504 | ||
8505 | case '0': | |
8506 | if (regno != 0) | |
8507 | regno = ILLEGAL_REG; | |
8508 | break; | |
8509 | ||
8510 | case 'S': | |
8511 | if (regno != SP) | |
8512 | regno = ILLEGAL_REG; | |
8513 | break; | |
8514 | ||
8515 | case 'R': | |
8516 | if (regno != RA) | |
8517 | regno = ILLEGAL_REG; | |
8518 | break; | |
8519 | ||
8520 | case 'X': | |
8521 | case 'Y': | |
3c83da8a | 8522 | if (regno == AT && ! mips_opts.noat) |
48401fcf | 8523 | as_warn (_("used $at without \".set noat\"")); |
cc5703cd ILT |
8524 | break; |
8525 | ||
8526 | default: | |
8527 | internalError (); | |
8528 | } | |
8529 | ||
8530 | if (regno == ILLEGAL_REG) | |
8531 | break; | |
8532 | ||
8533 | switch (c) | |
8534 | { | |
8535 | case 'x': | |
8536 | case 'v': | |
8537 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8538 | break; | |
8539 | case 'y': | |
8540 | case 'w': | |
8541 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8542 | break; | |
8543 | case 'z': | |
8544 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8545 | break; | |
8546 | case 'Z': | |
8547 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8548 | case '0': | |
8549 | case 'S': | |
8550 | case 'R': | |
8551 | break; | |
8552 | case 'X': | |
8553 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8554 | break; | |
8555 | case 'Y': | |
8556 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8557 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8558 | break; | |
8559 | default: | |
8560 | internalError (); | |
8561 | } | |
8562 | ||
8563 | lastregno = regno; | |
8564 | continue; | |
8565 | ||
8566 | case 'P': | |
8567 | if (strncmp (s, "$pc", 3) == 0) | |
8568 | { | |
8569 | s += 3; | |
8570 | continue; | |
8571 | } | |
8572 | break; | |
8573 | ||
8574 | case '<': | |
8575 | case '>': | |
8576 | case '[': | |
8577 | case ']': | |
8578 | case '4': | |
8579 | case '5': | |
8580 | case 'H': | |
8581 | case 'W': | |
8582 | case 'D': | |
8583 | case 'j': | |
8584 | case '8': | |
8585 | case 'V': | |
8586 | case 'C': | |
8587 | case 'U': | |
8588 | case 'k': | |
8589 | case 'K': | |
16262668 ILT |
8590 | if (s[0] == '%' |
8591 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8592 | { | |
8593 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8594 | and generate the appropriate reloc. If the text | |
8595 | inside %gprel is not a symbol name with an | |
8596 | optional offset, then we generate a normal reloc | |
8597 | and will probably fail later. */ | |
8598 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8599 | if (imm_expr.X_op == O_symbol) | |
8600 | { | |
8601 | mips16_ext = true; | |
8602 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8603 | s = expr_end; | |
8604 | ip->use_extend = true; | |
8605 | ip->extend = 0; | |
8606 | continue; | |
8607 | } | |
8608 | } | |
8609 | else | |
8610 | { | |
8611 | /* Just pick up a normal expression. */ | |
8612 | my_getExpression (&imm_expr, s); | |
8613 | } | |
8614 | ||
ebf28372 ILT |
8615 | if (imm_expr.X_op == O_register) |
8616 | { | |
8617 | /* What we thought was an expression turned out to | |
8618 | be a register. */ | |
8619 | ||
8620 | if (s[0] == '(' && args[1] == '(') | |
8621 | { | |
8622 | /* It looks like the expression was omitted | |
8623 | before a register indirection, which means | |
8624 | that the expression is implicitly zero. We | |
8625 | still set up imm_expr, so that we handle | |
8626 | explicit extensions correctly. */ | |
8627 | imm_expr.X_op = O_constant; | |
8628 | imm_expr.X_add_number = 0; | |
8629 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8630 | continue; | |
8631 | } | |
8632 | ||
8633 | break; | |
8634 | } | |
8635 | ||
cc5703cd ILT |
8636 | /* We need to relax this instruction. */ |
8637 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8638 | s = expr_end; | |
8639 | continue; | |
8640 | ||
8641 | case 'p': | |
8642 | case 'q': | |
8643 | case 'A': | |
8644 | case 'B': | |
8645 | case 'E': | |
8646 | /* We use offset_reloc rather than imm_reloc for the PC | |
8647 | relative operands. This lets macros with both | |
8648 | immediate and address operands work correctly. */ | |
670a50eb | 8649 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8650 | |
8651 | if (offset_expr.X_op == O_register) | |
8652 | break; | |
8653 | ||
cc5703cd ILT |
8654 | /* We need to relax this instruction. */ |
8655 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8656 | s = expr_end; |
8657 | continue; | |
8658 | ||
cc5703cd ILT |
8659 | case '6': /* break code */ |
8660 | my_getExpression (&imm_expr, s); | |
8661 | check_absolute_expr (ip, &imm_expr); | |
8662 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8663 | { |
48401fcf | 8664 | as_warn (_("Invalid value for `%s' (%lu)"), |
cc5703cd ILT |
8665 | ip->insn_mo->name, |
8666 | (unsigned long) imm_expr.X_add_number); | |
8667 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8668 | } |
cc5703cd ILT |
8669 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8670 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8671 | s = expr_end; |
8672 | continue; | |
3d3c5039 | 8673 | |
670a50eb ILT |
8674 | case 'a': /* 26 bit address */ |
8675 | my_getExpression (&offset_expr, s); | |
8676 | s = expr_end; | |
cc5703cd ILT |
8677 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8678 | ip->insn_opcode <<= 16; | |
670a50eb | 8679 | continue; |
3d3c5039 | 8680 | |
cc5703cd ILT |
8681 | case 'l': /* register list for entry macro */ |
8682 | case 'L': /* register list for exit macro */ | |
8683 | { | |
8684 | int mask; | |
8685 | ||
8686 | if (c == 'l') | |
8687 | mask = 0; | |
8688 | else | |
8689 | mask = 7 << 3; | |
8690 | while (*s != '\0') | |
8691 | { | |
c9167640 | 8692 | int freg, reg1, reg2; |
cc5703cd ILT |
8693 | |
8694 | while (*s == ' ' || *s == ',') | |
8695 | ++s; | |
8696 | if (*s != '$') | |
8697 | { | |
48401fcf | 8698 | as_bad (_("can't parse register list")); |
cc5703cd ILT |
8699 | break; |
8700 | } | |
8701 | ++s; | |
c9167640 ILT |
8702 | if (*s != 'f') |
8703 | freg = 0; | |
8704 | else | |
8705 | { | |
8706 | freg = 1; | |
8707 | ++s; | |
8708 | } | |
cc5703cd ILT |
8709 | reg1 = 0; |
8710 | while (isdigit (*s)) | |
8711 | { | |
8712 | reg1 *= 10; | |
8713 | reg1 += *s - '0'; | |
8714 | ++s; | |
8715 | } | |
8716 | if (*s == ' ') | |
8717 | ++s; | |
8718 | if (*s != '-') | |
8719 | reg2 = reg1; | |
8720 | else | |
8721 | { | |
8722 | ++s; | |
8723 | if (*s != '$') | |
8724 | break; | |
8725 | ++s; | |
c9167640 ILT |
8726 | if (freg) |
8727 | { | |
8728 | if (*s == 'f') | |
8729 | ++s; | |
8730 | else | |
8731 | { | |
48401fcf | 8732 | as_bad (_("invalid register list")); |
c9167640 ILT |
8733 | break; |
8734 | } | |
8735 | } | |
cc5703cd ILT |
8736 | reg2 = 0; |
8737 | while (isdigit (*s)) | |
8738 | { | |
8739 | reg2 *= 10; | |
8740 | reg2 += *s - '0'; | |
8741 | ++s; | |
8742 | } | |
8743 | } | |
c9167640 ILT |
8744 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8745 | { | |
8746 | mask &= ~ (7 << 3); | |
8747 | mask |= 5 << 3; | |
8748 | } | |
8749 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8750 | { | |
8751 | mask &= ~ (7 << 3); | |
8752 | mask |= 6 << 3; | |
8753 | } | |
8754 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8755 | mask |= (reg2 - 3) << 3; |
8756 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8757 | mask |= (reg2 - 15) << 1; | |
8758 | else if (reg1 == 31 && reg2 == 31) | |
8759 | mask |= 1; | |
8760 | else | |
c9167640 | 8761 | { |
48401fcf | 8762 | as_bad (_("invalid register list")); |
c9167640 ILT |
8763 | break; |
8764 | } | |
cc5703cd | 8765 | } |
c9167640 ILT |
8766 | /* The mask is filled in in the opcode table for the |
8767 | benefit of the disassembler. We remove it before | |
8768 | applying the actual mask. */ | |
8769 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8770 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8771 | } | |
8772 | continue; | |
d8a1c247 | 8773 | |
56bb6eee ILT |
8774 | case 'e': /* extend code */ |
8775 | my_getExpression (&imm_expr, s); | |
8776 | check_absolute_expr (ip, &imm_expr); | |
8777 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8778 | { | |
48401fcf | 8779 | as_warn (_("Invalid value for `%s' (%lu)"), |
56bb6eee ILT |
8780 | ip->insn_mo->name, |
8781 | (unsigned long) imm_expr.X_add_number); | |
8782 | imm_expr.X_add_number &= 0x7ff; | |
8783 | } | |
8784 | ip->insn_opcode |= imm_expr.X_add_number; | |
8785 | imm_expr.X_op = O_absent; | |
8786 | s = expr_end; | |
8787 | continue; | |
8788 | ||
3d3c5039 | 8789 | default: |
670a50eb | 8790 | internalError (); |
3d3c5039 | 8791 | } |
670a50eb | 8792 | break; |
3d3c5039 | 8793 | } |
cc5703cd | 8794 | |
670a50eb | 8795 | /* Args don't match. */ |
cc5703cd ILT |
8796 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8797 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8798 | { |
8799 | ++insn; | |
cc5703cd | 8800 | s = argsstart; |
670a50eb | 8801 | continue; |
3d3c5039 | 8802 | } |
cc5703cd | 8803 | |
48401fcf | 8804 | insn_error = _("illegal operands"); |
cc5703cd | 8805 | |
670a50eb | 8806 | return; |
3d3c5039 ILT |
8807 | } |
8808 | } | |
8809 | ||
cc5703cd ILT |
8810 | /* This structure holds information we know about a mips16 immediate |
8811 | argument type. */ | |
8812 | ||
8813 | struct mips16_immed_operand | |
8814 | { | |
8815 | /* The type code used in the argument string in the opcode table. */ | |
8816 | int type; | |
8817 | /* The number of bits in the short form of the opcode. */ | |
8818 | int nbits; | |
8819 | /* The number of bits in the extended form of the opcode. */ | |
8820 | int extbits; | |
8821 | /* The amount by which the short form is shifted when it is used; | |
8822 | for example, the sw instruction has a shift count of 2. */ | |
8823 | int shift; | |
8824 | /* The amount by which the short form is shifted when it is stored | |
8825 | into the instruction code. */ | |
8826 | int op_shift; | |
8827 | /* Non-zero if the short form is unsigned. */ | |
8828 | int unsp; | |
8829 | /* Non-zero if the extended form is unsigned. */ | |
8830 | int extu; | |
8831 | /* Non-zero if the value is PC relative. */ | |
8832 | int pcrel; | |
8833 | }; | |
8834 | ||
8835 | /* The mips16 immediate operand types. */ | |
8836 | ||
8837 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8838 | { | |
8839 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8840 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8841 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8842 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8843 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8844 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8845 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8846 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8847 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8848 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8849 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8850 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8851 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8852 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8853 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8854 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8855 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8856 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8857 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8858 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8859 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8860 | }; | |
8861 | ||
8862 | #define MIPS16_NUM_IMMED \ | |
8863 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8864 | ||
8865 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8866 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8867 | whether an extended value is needed; if one is needed, it sets | |
8868 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8869 | If SMALL is true, an unextended opcode was explicitly requested. | |
8870 | If EXT is true, an extended opcode was explicitly requested. If | |
8871 | WARN is true, warn if EXT does not match reality. */ | |
8872 | ||
8873 | static void | |
15e69f98 ILT |
8874 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
8875 | extend) | |
8876 | char *file; | |
8877 | unsigned int line; | |
cc5703cd ILT |
8878 | int type; |
8879 | offsetT val; | |
8880 | boolean warn; | |
8881 | boolean small; | |
8882 | boolean ext; | |
8883 | unsigned long *insn; | |
8884 | boolean *use_extend; | |
8885 | unsigned short *extend; | |
8886 | { | |
8887 | register const struct mips16_immed_operand *op; | |
8888 | int mintiny, maxtiny; | |
8889 | boolean needext; | |
8890 | ||
8891 | op = mips16_immed_operands; | |
8892 | while (op->type != type) | |
8893 | { | |
8894 | ++op; | |
8895 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8896 | } | |
8897 | ||
8898 | if (op->unsp) | |
8899 | { | |
8900 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8901 | { | |
8902 | mintiny = 1; | |
8903 | maxtiny = 1 << op->nbits; | |
8904 | } | |
8905 | else | |
8906 | { | |
8907 | mintiny = 0; | |
8908 | maxtiny = (1 << op->nbits) - 1; | |
8909 | } | |
8910 | } | |
8911 | else | |
8912 | { | |
8913 | mintiny = - (1 << (op->nbits - 1)); | |
8914 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8915 | } | |
8916 | ||
8917 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8918 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8919 | val /= 2; |
cc5703cd ILT |
8920 | |
8921 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8922 | || val < (mintiny << op->shift) | |
8923 | || val > (maxtiny << op->shift)) | |
8924 | needext = true; | |
8925 | else | |
8926 | needext = false; | |
8927 | ||
8928 | if (warn && ext && ! needext) | |
48401fcf | 8929 | as_warn_where (file, line, _("extended operand requested but not required")); |
8728fa92 | 8930 | if (small && needext) |
48401fcf | 8931 | as_bad_where (file, line, _("invalid unextended operand value")); |
cc5703cd ILT |
8932 | |
8933 | if (small || (! ext && ! needext)) | |
8934 | { | |
8935 | int insnval; | |
8936 | ||
8937 | *use_extend = false; | |
8938 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8939 | insnval <<= op->op_shift; | |
8940 | *insn |= insnval; | |
8941 | } | |
8942 | else | |
8943 | { | |
8944 | long minext, maxext; | |
8945 | int extval; | |
8946 | ||
8947 | if (op->extu) | |
8948 | { | |
8949 | minext = 0; | |
8950 | maxext = (1 << op->extbits) - 1; | |
8951 | } | |
8952 | else | |
8953 | { | |
8954 | minext = - (1 << (op->extbits - 1)); | |
8955 | maxext = (1 << (op->extbits - 1)) - 1; | |
8956 | } | |
8957 | if (val < minext || val > maxext) | |
15e69f98 | 8958 | as_bad_where (file, line, |
48401fcf | 8959 | _("operand value out of range for instruction")); |
cc5703cd ILT |
8960 | |
8961 | *use_extend = true; | |
8962 | if (op->extbits == 16) | |
8963 | { | |
8964 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8965 | val &= 0x1f; | |
8966 | } | |
8967 | else if (op->extbits == 15) | |
8968 | { | |
8969 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8970 | val &= 0xf; | |
8971 | } | |
8972 | else | |
8973 | { | |
8974 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8975 | val = 0; | |
8976 | } | |
8977 | ||
8978 | *extend = (unsigned short) extval; | |
8979 | *insn |= val; | |
8980 | } | |
8981 | } | |
8982 | \f | |
3d3c5039 ILT |
8983 | #define LP '(' |
8984 | #define RP ')' | |
8985 | ||
8986 | static int | |
8987 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8988 | expressionS *ep; |
8989 | char *str; | |
3d3c5039 | 8990 | { |
670a50eb ILT |
8991 | char *sp; |
8992 | int c = 0; | |
8993 | ||
8994 | if (*str == ' ') | |
8995 | str++; | |
8996 | if (*str == LP | |
8997 | || (*str == '%' && | |
8998 | ((str[1] == 'h' && str[2] == 'i') | |
8999 | || (str[1] == 'H' && str[2] == 'I') | |
9000 | || (str[1] == 'l' && str[2] == 'o')) | |
9001 | && str[3] == LP)) | |
9002 | { | |
9003 | if (*str == LP) | |
9004 | c = 0; | |
9005 | else | |
9006 | { | |
9007 | c = str[1]; | |
9008 | str += 3; | |
9009 | } | |
9010 | ||
9011 | /* | |
9012 | * A small expression may be followed by a base register. | |
9013 | * Scan to the end of this operand, and then back over a possible | |
9014 | * base register. Then scan the small expression up to that | |
9015 | * point. (Based on code in sparc.c...) | |
9016 | */ | |
9017 | for (sp = str; *sp && *sp != ','; sp++) | |
9018 | ; | |
9019 | if (sp - 4 >= str && sp[-1] == RP) | |
9020 | { | |
9021 | if (isdigit (sp[-2])) | |
9022 | { | |
9023 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
9024 | ; | |
9025 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
9026 | { | |
9027 | sp--; | |
9028 | goto do_it; | |
3d3c5039 | 9029 | } |
670a50eb ILT |
9030 | } |
9031 | else if (sp - 5 >= str | |
9032 | && sp[-5] == LP | |
9033 | && sp[-4] == '$' | |
9034 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
9035 | || (sp[-3] == 's' && sp[-2] == 'p') | |
9036 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
9037 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
9038 | { | |
9039 | sp -= 5; | |
3d3c5039 | 9040 | do_it: |
670a50eb ILT |
9041 | if (sp == str) |
9042 | { | |
9043 | /* no expression means zero offset */ | |
9044 | if (c) | |
9045 | { | |
9046 | /* %xx(reg) is an error */ | |
5ac34ac3 | 9047 | ep->X_op = O_absent; |
670a50eb | 9048 | expr_end = str - 3; |
3d3c5039 | 9049 | } |
670a50eb ILT |
9050 | else |
9051 | { | |
52aa70b5 | 9052 | ep->X_op = O_constant; |
670a50eb ILT |
9053 | expr_end = sp; |
9054 | } | |
9055 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 9056 | ep->X_op_symbol = NULL; |
670a50eb ILT |
9057 | ep->X_add_number = 0; |
9058 | } | |
9059 | else | |
9060 | { | |
9061 | *sp = '\0'; | |
9062 | my_getExpression (ep, str); | |
9063 | *sp = LP; | |
3d3c5039 | 9064 | } |
670a50eb | 9065 | return c; |
3d3c5039 ILT |
9066 | } |
9067 | } | |
9068 | } | |
670a50eb ILT |
9069 | my_getExpression (ep, str); |
9070 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
9071 | } |
9072 | ||
9073 | static void | |
9074 | my_getExpression (ep, str) | |
670a50eb ILT |
9075 | expressionS *ep; |
9076 | char *str; | |
3d3c5039 | 9077 | { |
670a50eb | 9078 | char *save_in; |
670a50eb ILT |
9079 | |
9080 | save_in = input_line_pointer; | |
9081 | input_line_pointer = str; | |
5ac34ac3 | 9082 | expression (ep); |
670a50eb ILT |
9083 | expr_end = input_line_pointer; |
9084 | input_line_pointer = save_in; | |
eb17f56c ILT |
9085 | |
9086 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9087 | then we bump the value of the symbol by 1 since that is how other | |
9088 | text symbols are handled. We don't bother to handle complex | |
9089 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 9090 | if (mips_opts.mips16 |
eb17f56c ILT |
9091 | && ep->X_op == O_symbol |
9092 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9093 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
9094 | && ep->X_add_symbol->sy_frag == frag_now | |
9095 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
9096 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
9097 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
9098 | } |
9099 | ||
becfe05e ILT |
9100 | /* Turn a string in input_line_pointer into a floating point constant |
9101 | of type type, and store the appropriate bytes in *litP. The number | |
9102 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
9103 | returned, or NULL on OK. */ | |
9104 | ||
3d3c5039 | 9105 | char * |
670a50eb | 9106 | md_atof (type, litP, sizeP) |
becfe05e | 9107 | int type; |
3d3c5039 ILT |
9108 | char *litP; |
9109 | int *sizeP; | |
9110 | { | |
becfe05e ILT |
9111 | int prec; |
9112 | LITTLENUM_TYPE words[4]; | |
9113 | char *t; | |
9114 | int i; | |
9115 | ||
9116 | switch (type) | |
9117 | { | |
9118 | case 'f': | |
9119 | prec = 2; | |
9120 | break; | |
9121 | ||
9122 | case 'd': | |
9123 | prec = 4; | |
9124 | break; | |
9125 | ||
9126 | default: | |
9127 | *sizeP = 0; | |
48401fcf | 9128 | return _("bad call to md_atof"); |
becfe05e ILT |
9129 | } |
9130 | ||
9131 | t = atof_ieee (input_line_pointer, type, words); | |
9132 | if (t) | |
9133 | input_line_pointer = t; | |
9134 | ||
9135 | *sizeP = prec * 2; | |
9136 | ||
b9129c6f | 9137 | if (! target_big_endian) |
becfe05e ILT |
9138 | { |
9139 | for (i = prec - 1; i >= 0; i--) | |
9140 | { | |
9141 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9142 | litP += 2; | |
9143 | } | |
9144 | } | |
9145 | else | |
9146 | { | |
9147 | for (i = 0; i < prec; i++) | |
9148 | { | |
9149 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9150 | litP += 2; | |
9151 | } | |
9152 | } | |
9153 | ||
670a50eb | 9154 | return NULL; |
3d3c5039 ILT |
9155 | } |
9156 | ||
9157 | void | |
9158 | md_number_to_chars (buf, val, n) | |
9159 | char *buf; | |
918692a5 | 9160 | valueT val; |
3d3c5039 ILT |
9161 | int n; |
9162 | { | |
b9129c6f ILT |
9163 | if (target_big_endian) |
9164 | number_to_chars_bigendian (buf, val, n); | |
9165 | else | |
9166 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 9167 | } |
f3d817d8 | 9168 | \f |
e8d4d475 | 9169 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 9170 | |
f3d817d8 DM |
9171 | struct option md_longopts[] = { |
9172 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
9173 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9174 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9175 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9176 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9177 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9178 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
9179 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
9180 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
9181 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 9182 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 9183 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 9184 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 9185 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
9186 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9187 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 9188 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
9189 | {"break", no_argument, NULL, OPTION_BREAK}, |
9190 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 9191 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 9192 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 9193 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 9194 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 9195 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 9196 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 9197 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 9198 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
9199 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
9200 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9201 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
9202 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
9203 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
9204 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9205 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
9206 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 9207 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 9208 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 9209 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 9210 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 9211 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
9212 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
9213 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
9214 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
9215 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 9216 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
9217 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
9218 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9219 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
9220 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
9221 | |
9222 | /* start-sanitize-tx19 */ | |
9223 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
9224 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
9225 | /* end-sanitize-tx19 */ | |
f3d817d8 | 9226 | |
aa2e0460 KR |
9227 | /* start-sanitize-vr5400 */ |
9228 | #define OPTION_M5400 (OPTION_MD_BASE + 28) | |
9229 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
9230 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
9231 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
9232 | ||
9233 | /* end-sanitize-vr5400 */ | |
42444087 GRK |
9234 | /* start-sanitize-tx49 */ |
9235 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
9236 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
9237 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
9238 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
9239 | ||
9240 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
9241 | /* start-sanitize-vr4320 */ |
9242 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
9243 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
9244 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
9245 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
9246 | ||
9247 | /* end-sanitize-vr4320 */ | |
d8a1c247 | 9248 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 9249 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 9250 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
9251 | #define OPTION_32 (OPTION_MD_BASE + 20) |
9252 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 9253 | #ifdef OBJ_ELF |
f3d817d8 | 9254 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 9255 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 9256 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 9257 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
9258 | {"32", no_argument, NULL, OPTION_32}, |
9259 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
9260 | #endif |
9261 | ||
9262 | {NULL, no_argument, NULL, 0} | |
9263 | }; | |
9264 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
9265 | |
9266 | int | |
f3d817d8 DM |
9267 | md_parse_option (c, arg) |
9268 | int c; | |
9269 | char *arg; | |
3d3c5039 | 9270 | { |
f3d817d8 | 9271 | switch (c) |
670a50eb | 9272 | { |
f3d817d8 DM |
9273 | case OPTION_TRAP: |
9274 | mips_trap = 1; | |
9275 | break; | |
670a50eb | 9276 | |
f3d817d8 DM |
9277 | case OPTION_BREAK: |
9278 | mips_trap = 0; | |
9279 | break; | |
9280 | ||
e8d4d475 | 9281 | case OPTION_EB: |
1dc1e798 | 9282 | target_big_endian = 1; |
e8d4d475 | 9283 | break; |
04cb3372 | 9284 | |
e8d4d475 | 9285 | case OPTION_EL: |
1dc1e798 | 9286 | target_big_endian = 0; |
f3d817d8 | 9287 | break; |
670a50eb | 9288 | |
f3d817d8 DM |
9289 | case 'O': |
9290 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
9291 | mips_optimize = 1; |
9292 | else | |
9293 | mips_optimize = 2; | |
f3d817d8 | 9294 | break; |
0aa07269 | 9295 | |
f3d817d8 | 9296 | case 'g': |
22ba90ce ILT |
9297 | if (arg == NULL) |
9298 | mips_debug = 2; | |
9299 | else | |
9300 | mips_debug = atoi (arg); | |
9301 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9302 | optimizations which limit full symbolic debugging. We take | |
9303 | that to be equivalent to -O0. */ | |
9304 | if (mips_debug == 2) | |
05874c2e | 9305 | mips_optimize = 1; |
f3d817d8 | 9306 | break; |
4e95866e | 9307 | |
f3d817d8 | 9308 | case OPTION_MIPS1: |
3c83da8a | 9309 | mips_opts.isa = 1; |
f3d817d8 | 9310 | break; |
8358c818 | 9311 | |
f3d817d8 | 9312 | case OPTION_MIPS2: |
3c83da8a | 9313 | mips_opts.isa = 2; |
f3d817d8 | 9314 | break; |
8358c818 | 9315 | |
f3d817d8 | 9316 | case OPTION_MIPS3: |
3c83da8a | 9317 | mips_opts.isa = 3; |
f3d817d8 | 9318 | break; |
8358c818 | 9319 | |
d8a1c247 | 9320 | case OPTION_MIPS4: |
3c83da8a | 9321 | mips_opts.isa = 4; |
d8a1c247 KR |
9322 | break; |
9323 | ||
f3d817d8 DM |
9324 | case OPTION_MCPU: |
9325 | { | |
9326 | char *p; | |
9327 | ||
9328 | /* Identify the processor type */ | |
9329 | p = arg; | |
9330 | if (strcmp (p, "default") == 0 | |
9331 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 9332 | mips_cpu = -1; |
f3d817d8 DM |
9333 | else |
9334 | { | |
c625fc23 JSC |
9335 | int sv = 0; |
9336 | ||
9337 | /* We need to cope with the various "vr" prefixes for the 4300 | |
9338 | processor. */ | |
9339 | if (*p == 'v' || *p == 'V') | |
9340 | { | |
9341 | sv = 1; | |
9342 | p++; | |
9343 | } | |
9344 | ||
f3d817d8 DM |
9345 | if (*p == 'r' || *p == 'R') |
9346 | p++; | |
8358c818 | 9347 | |
4bb0cc41 | 9348 | mips_cpu = -1; |
f3d817d8 DM |
9349 | switch (*p) |
9350 | { | |
d8a1c247 KR |
9351 | case '1': |
9352 | if (strcmp (p, "10000") == 0 | |
9353 | || strcmp (p, "10k") == 0 | |
9354 | || strcmp (p, "10K") == 0) | |
9355 | mips_cpu = 10000; | |
4e96260f JL |
9356 | /* start-sanitize-tx19 */ |
9357 | else if (strcmp (p, "1900") == 0) | |
9358 | mips_cpu = 3900; | |
9359 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
9360 | break; |
9361 | ||
f3d817d8 DM |
9362 | case '2': |
9363 | if (strcmp (p, "2000") == 0 | |
9364 | || strcmp (p, "2k") == 0 | |
9365 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 9366 | mips_cpu = 2000; |
f3d817d8 | 9367 | break; |
8358c818 | 9368 | |
f3d817d8 DM |
9369 | case '3': |
9370 | if (strcmp (p, "3000") == 0 | |
9371 | || strcmp (p, "3k") == 0 | |
9372 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 9373 | mips_cpu = 3000; |
5c6f5923 GRK |
9374 | else if (strcmp (p, "3900") == 0) |
9375 | mips_cpu = 3900; | |
f3d817d8 | 9376 | break; |
8358c818 | 9377 | |
f3d817d8 DM |
9378 | case '4': |
9379 | if (strcmp (p, "4000") == 0 | |
9380 | || strcmp (p, "4k") == 0 | |
8c63448a | 9381 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 9382 | mips_cpu = 4000; |
c625fc23 | 9383 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 9384 | mips_cpu = 4100; |
c625fc23 JSC |
9385 | else if (strcmp (p, "4300") == 0) |
9386 | mips_cpu = 4300; | |
2d035a50 GRK |
9387 | /* start-sanitize-vr4320 */ |
9388 | else if (strcmp (p, "4320") == 0) | |
9389 | mips_cpu = 4320; | |
9390 | /* end-sanitize-vr4320 */ | |
8c63448a | 9391 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 9392 | mips_cpu = 4400; |
8c63448a | 9393 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 9394 | mips_cpu = 4600; |
b2b8c24e | 9395 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 9396 | mips_cpu = 4650; |
4ebda395 GRK |
9397 | /* start-sanitize-tx49 */ |
9398 | else if (strcmp (p, "4900") == 0) | |
9399 | mips_cpu = 4900; | |
9400 | /* end-sanitize-tx49 */ | |
e532b44c | 9401 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9402 | mips_cpu = 4010; |
f3d817d8 | 9403 | break; |
8358c818 | 9404 | |
517078c1 ILT |
9405 | case '5': |
9406 | if (strcmp (p, "5000") == 0 | |
9407 | || strcmp (p, "5k") == 0 | |
9408 | || strcmp (p, "5K") == 0) | |
9409 | mips_cpu = 5000; | |
aa2e0460 KR |
9410 | /* start-sanitize-vr5400 */ |
9411 | else if (strcmp (p, "5400") == 0) | |
9412 | mips_cpu = 5400; | |
9413 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
9414 | /* start-sanitize-r5900 */ |
9415 | else if (strcmp (p, "5900") == 0) | |
9416 | mips_cpu = 5900; | |
9417 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9418 | break; |
9419 | ||
f3d817d8 DM |
9420 | case '6': |
9421 | if (strcmp (p, "6000") == 0 | |
9422 | || strcmp (p, "6k") == 0 | |
9423 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9424 | mips_cpu = 6000; |
f3d817d8 | 9425 | break; |
55933a58 | 9426 | |
d8a1c247 KR |
9427 | case '8': |
9428 | if (strcmp (p, "8000") == 0 | |
9429 | || strcmp (p, "8k") == 0 | |
9430 | || strcmp (p, "8K") == 0) | |
9431 | mips_cpu = 8000; | |
9432 | break; | |
9433 | ||
55933a58 ILT |
9434 | case 'o': |
9435 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9436 | mips_cpu = 4600; |
55933a58 | 9437 | break; |
f3d817d8 | 9438 | } |
8358c818 | 9439 | |
b3ed1af3 KR |
9440 | if (sv |
9441 | && (mips_cpu != 4300 | |
9442 | && mips_cpu != 4100 | |
2d035a50 GRK |
9443 | /* start-sanitize-vr4320 */ |
9444 | && mips_cpu != 4320 | |
9445 | /* end-sanitize-vr4320 */ | |
b3ed1af3 KR |
9446 | /* start-sanitize-vr5400 */ |
9447 | && mips_cpu != 5400 | |
9448 | /* end-sanitize-vr5400 */ | |
9449 | && mips_cpu != 5000)) | |
c625fc23 | 9450 | { |
48401fcf | 9451 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); |
c625fc23 JSC |
9452 | return 0; |
9453 | } | |
9454 | ||
4bb0cc41 | 9455 | if (mips_cpu == -1) |
f3d817d8 | 9456 | { |
48401fcf | 9457 | as_bad (_("invalid architecture -mcpu=%s"), arg); |
f3d817d8 DM |
9458 | return 0; |
9459 | } | |
9460 | } | |
9461 | } | |
9462 | break; | |
8358c818 | 9463 | |
b2b8c24e ILT |
9464 | case OPTION_M4650: |
9465 | mips_4650 = 1; | |
9466 | break; | |
9467 | ||
9468 | case OPTION_NO_M4650: | |
9469 | mips_4650 = 0; | |
9470 | break; | |
9471 | ||
e532b44c ILT |
9472 | case OPTION_M4010: |
9473 | mips_4010 = 1; | |
9474 | break; | |
9475 | ||
9476 | case OPTION_NO_M4010: | |
9477 | mips_4010 = 0; | |
9478 | break; | |
9479 | ||
c625fc23 JSC |
9480 | case OPTION_M4100: |
9481 | mips_4100 = 1; | |
9482 | break; | |
9483 | ||
9484 | case OPTION_NO_M4100: | |
9485 | mips_4100 = 0; | |
9486 | break; | |
9487 | ||
276c2d7d GRK |
9488 | /* start-sanitize-r5900 */ |
9489 | case OPTION_M5900: | |
9490 | mips_5900 = 1; | |
9491 | break; | |
9492 | ||
9493 | case OPTION_NO_M5900: | |
9494 | mips_5900 = 0; | |
9495 | break; | |
9496 | /* end-sanitize-r5900 */ | |
9497 | ||
2d035a50 GRK |
9498 | /* start-sanitize-vr4320 */ |
9499 | case OPTION_M4320: | |
9500 | mips_4320 = 1; | |
9501 | break; | |
9502 | ||
9503 | case OPTION_NO_M4320: | |
9504 | mips_4320 = 0; | |
9505 | break; | |
9506 | ||
9507 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
9508 | /* start-sanitize-vr5400 */ |
9509 | case OPTION_M5400: | |
9510 | mips_5400 = 1; | |
9511 | break; | |
9512 | ||
9513 | case OPTION_NO_M5400: | |
9514 | mips_5400 = 0; | |
9515 | break; | |
9516 | ||
9517 | /* end-sanitize-vr5400 */ | |
5c6f5923 GRK |
9518 | case OPTION_M3900: |
9519 | mips_3900 = 1; | |
9520 | break; | |
9521 | ||
9522 | case OPTION_NO_M3900: | |
9523 | mips_3900 = 0; | |
9524 | break; | |
9525 | ||
42444087 GRK |
9526 | /* start-sanitize-tx49 */ |
9527 | case OPTION_M4900: | |
9528 | mips_4900 = 1; | |
9529 | break; | |
9530 | ||
9531 | case OPTION_NO_M4900: | |
9532 | mips_4900 = 0; | |
9533 | break; | |
9534 | ||
9535 | /* end-sanitize-tx49 */ | |
cc5703cd | 9536 | case OPTION_MIPS16: |
3c83da8a | 9537 | mips_opts.mips16 = 1; |
4a1cb507 | 9538 | mips_no_prev_insn (false); |
cc5703cd ILT |
9539 | break; |
9540 | ||
9541 | case OPTION_NO_MIPS16: | |
3c83da8a | 9542 | mips_opts.mips16 = 0; |
4a1cb507 | 9543 | mips_no_prev_insn (false); |
cc5703cd ILT |
9544 | break; |
9545 | ||
f3d817d8 | 9546 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9547 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9548 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 | 9549 | { |
48401fcf | 9550 | as_bad (_("-G may not be used with embedded PIC code")); |
f3d817d8 DM |
9551 | return 0; |
9552 | } | |
5b63f465 | 9553 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9554 | break; |
d9aba805 | 9555 | |
fb251650 ILT |
9556 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9557 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9558 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9559 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9560 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9561 | { | |
48401fcf | 9562 | as_bad (_("-call_shared is supported only for ELF format")); |
1dc1e798 KR |
9563 | return 0; |
9564 | } | |
d9aba805 ILT |
9565 | mips_pic = SVR4_PIC; |
9566 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 | 9567 | { |
48401fcf | 9568 | as_bad (_("-G may not be used with SVR4 PIC code")); |
f3d817d8 DM |
9569 | return 0; |
9570 | } | |
d9aba805 | 9571 | g_switch_value = 0; |
f3d817d8 DM |
9572 | break; |
9573 | ||
9574 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9575 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9576 | { | |
48401fcf | 9577 | as_bad (_("-non_shared is supported only for ELF format")); |
1dc1e798 KR |
9578 | return 0; |
9579 | } | |
d9aba805 | 9580 | mips_pic = NO_PIC; |
f3d817d8 | 9581 | break; |
8358c818 | 9582 | |
fb251650 ILT |
9583 | /* The -xgot option tells the assembler to use 32 offsets when |
9584 | accessing the got in SVR4_PIC mode. It is for Irix | |
9585 | compatibility. */ | |
9586 | case OPTION_XGOT: | |
9587 | mips_big_got = 1; | |
9588 | break; | |
9589 | ||
f3d817d8 | 9590 | case 'G': |
1dc1e798 KR |
9591 | if (! USE_GLOBAL_POINTER_OPT) |
9592 | { | |
48401fcf | 9593 | as_bad (_("-G is not supported for this configuration")); |
1dc1e798 KR |
9594 | return 0; |
9595 | } | |
9596 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9597 | { |
48401fcf | 9598 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
f3d817d8 | 9599 | return 0; |
670a50eb ILT |
9600 | } |
9601 | else | |
f3d817d8 | 9602 | g_switch_value = atoi (arg); |
42562568 | 9603 | g_switch_seen = 1; |
f3d817d8 | 9604 | break; |
4e95866e | 9605 | |
7f9880e5 ILT |
9606 | /* The -32 and -64 options tell the assembler to output the 32 |
9607 | bit or the 64 bit MIPS ELF format. */ | |
9608 | case OPTION_32: | |
9609 | mips_64 = 0; | |
9610 | break; | |
9611 | ||
9612 | case OPTION_64: | |
9c44af60 ILT |
9613 | { |
9614 | const char **list, **l; | |
9615 | ||
9616 | list = bfd_target_list (); | |
9617 | for (l = list; *l != NULL; l++) | |
9618 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9619 | || strcmp (*l, "elf64-littlemips") == 0) | |
9620 | break; | |
9621 | if (*l == NULL) | |
48401fcf | 9622 | as_fatal (_("No compiled in support for 64 bit object file format")); |
9c44af60 ILT |
9623 | free (list); |
9624 | mips_64 = 1; | |
9625 | } | |
7f9880e5 ILT |
9626 | break; |
9627 | ||
f3d817d8 DM |
9628 | default: |
9629 | return 0; | |
8ea7f4e8 ILT |
9630 | } |
9631 | ||
f3d817d8 | 9632 | return 1; |
8ea7f4e8 ILT |
9633 | } |
9634 | ||
f3d817d8 DM |
9635 | void |
9636 | md_show_usage (stream) | |
9637 | FILE *stream; | |
9638 | { | |
48401fcf | 9639 | fprintf(stream, _("\ |
f3d817d8 DM |
9640 | MIPS options:\n\ |
9641 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9642 | -EB generate big endian output\n\ |
9643 | -EL generate little endian output\n\ | |
9644 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9645 | -G NUM allow referencing objects up to NUM bytes\n\ | |
48401fcf TT |
9646 | implicitly with the gp register [default 8]\n")); |
9647 | fprintf(stream, _("\ | |
f3d817d8 DM |
9648 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
9649 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
9650 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 9651 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 9652 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9653 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9654 | -m4650 permit R4650 instructions\n\ |
9655 | -no-m4650 do not permit R4650 instructions\n\ | |
9656 | -m4010 permit R4010 instructions\n\ | |
9657 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 | 9658 | -m4100 permit VR4100 instructions\n\ |
48401fcf TT |
9659 | -no-m4100 do not permit VR4100 instructions\n")); |
9660 | fprintf(stream, _("\ | |
cc5703cd | 9661 | -mips16 generate mips16 instructions\n\ |
48401fcf TT |
9662 | -no-mips16 do not generate mips16 instructions\n")); |
9663 | fprintf(stream, _("\ | |
f3d817d8 DM |
9664 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9665 | -O remove unneeded NOPs and swap branches\n\ | |
9666 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
48401fcf | 9667 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
f3d817d8 | 9668 | #ifdef OBJ_ELF |
48401fcf | 9669 | fprintf(stream, _("\ |
f3d817d8 | 9670 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
fb251650 | 9671 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9672 | -xgot assume a 32 bit GOT\n\ |
9673 | -32 create 32 bit object file (default)\n\ | |
48401fcf | 9674 | -64 create 64 bit object file\n")); |
f3d817d8 DM |
9675 | #endif |
9676 | } | |
9677 | \f | |
efec4a28 DP |
9678 | void |
9679 | mips_init_after_args () | |
9680 | { | |
af942793 SS |
9681 | /* initialize opcodes */ |
9682 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9683 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9684 | } |
9685 | ||
3d3c5039 ILT |
9686 | long |
9687 | md_pcrel_from (fixP) | |
9688 | fixS *fixP; | |
9689 | { | |
1dc1e798 KR |
9690 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9691 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9692 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9693 | { | |
9694 | /* This makes a branch to an undefined symbol be a branch to the | |
9695 | current location. */ | |
9696 | return 4; | |
9697 | } | |
5b63f465 | 9698 | |
670a50eb ILT |
9699 | /* return the address of the delay slot */ |
9700 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9701 | } |
9702 | ||
abdad6bc ILT |
9703 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9704 | reloc for a cons. We could use the definition there, except that | |
9705 | we want to handle 64 bit relocs specially. */ | |
9706 | ||
9707 | void | |
9708 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9709 | fragS *frag; | |
9710 | int where; | |
9711 | unsigned int nbytes; | |
9712 | expressionS *exp; | |
9713 | { | |
bf39474f | 9714 | #ifndef OBJ_ELF |
abdad6bc | 9715 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9716 | 4 byte reloc. */ |
9717 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9718 | { |
b9129c6f | 9719 | if (target_big_endian) |
abdad6bc ILT |
9720 | where += 4; |
9721 | nbytes = 4; | |
9722 | } | |
bf39474f | 9723 | #endif |
abdad6bc | 9724 | |
7f9880e5 | 9725 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
48401fcf | 9726 | as_bad (_("Unsupported reloc size %d"), nbytes); |
abdad6bc ILT |
9727 | |
9728 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9729 | (nbytes == 2 |
9730 | ? BFD_RELOC_16 | |
9731 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9732 | } |
9733 | ||
23604921 ILT |
9734 | /* This is called before the symbol table is processed. In order to |
9735 | work with gcc when using mips-tfile, we must keep all local labels. | |
9736 | However, in other cases, we want to discard them. If we were | |
9737 | called with -g, but we didn't see any debugging information, it may | |
9738 | mean that gcc is smuggling debugging information through to | |
9739 | mips-tfile, in which case we must generate all local labels. */ | |
9740 | ||
9741 | void | |
9742 | mips_frob_file_before_adjust () | |
9743 | { | |
9744 | #ifndef NO_ECOFF_DEBUGGING | |
9745 | if (ECOFF_DEBUGGING | |
9746 | && mips_debug != 0 | |
9747 | && ! ecoff_debugging_seen) | |
9748 | flag_keep_locals = 1; | |
9749 | #endif | |
9750 | } | |
9751 | ||
867a58b3 ILT |
9752 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9753 | the corresponding LO reloc. This is called before md_apply_fix and | |
9754 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9755 | explicit use of the %hi modifier. */ | |
9756 | ||
9757 | void | |
9758 | mips_frob_file () | |
9759 | { | |
9760 | struct mips_hi_fixup *l; | |
9761 | ||
9762 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9763 | { | |
9764 | segment_info_type *seginfo; | |
9b61d62b | 9765 | int pass; |
867a58b3 ILT |
9766 | |
9767 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9768 | ||
9769 | /* Check quickly whether the next fixup happens to be a matching | |
9770 | %lo. */ | |
9771 | if (l->fixp->fx_next != NULL | |
9772 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9773 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9774 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9775 | continue; | |
9776 | ||
9777 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9778 | When we find one, move the %hi just in front of it. We do |
9779 | this in two passes. In the first pass, we try to find a | |
9780 | unique %lo. In the second pass, we permit multiple %hi | |
9781 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9782 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9783 | for (pass = 0; pass < 2; pass++) |
9784 | { | |
9785 | fixS *f, *prev; | |
9786 | ||
9787 | prev = NULL; | |
9788 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9789 | { |
9b61d62b ILT |
9790 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9791 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9792 | && f->fx_addsy == l->fixp->fx_addsy | |
9793 | && f->fx_offset == l->fixp->fx_offset | |
9794 | && (pass == 1 | |
9795 | || prev == NULL | |
9796 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9797 | || prev->fx_addsy != f->fx_addsy | |
9798 | || prev->fx_offset != f->fx_offset)) | |
9799 | { | |
9800 | fixS **pf; | |
867a58b3 | 9801 | |
9b61d62b ILT |
9802 | /* Move l->fixp before f. */ |
9803 | for (pf = &seginfo->fix_root; | |
9804 | *pf != l->fixp; | |
9805 | pf = &(*pf)->fx_next) | |
9806 | assert (*pf != NULL); | |
867a58b3 | 9807 | |
9b61d62b | 9808 | *pf = l->fixp->fx_next; |
867a58b3 | 9809 | |
9b61d62b ILT |
9810 | l->fixp->fx_next = f; |
9811 | if (prev == NULL) | |
9812 | seginfo->fix_root = l->fixp; | |
9813 | else | |
9814 | prev->fx_next = l->fixp; | |
867a58b3 | 9815 | |
9b61d62b ILT |
9816 | break; |
9817 | } | |
9818 | ||
9819 | prev = f; | |
867a58b3 ILT |
9820 | } |
9821 | ||
9b61d62b ILT |
9822 | if (f != NULL) |
9823 | break; | |
867a58b3 | 9824 | |
9b61d62b ILT |
9825 | if (pass == 1) |
9826 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
48401fcf | 9827 | _("Unmatched %%hi reloc")); |
9b61d62b | 9828 | } |
867a58b3 ILT |
9829 | } |
9830 | } | |
9831 | ||
1c803e52 ILT |
9832 | /* When generating embedded PIC code we need to use a special |
9833 | relocation to represent the difference of two symbols in the .text | |
9834 | section (switch tables use a difference of this sort). See | |
9835 | include/coff/mips.h for details. This macro checks whether this | |
9836 | fixup requires the special reloc. */ | |
9837 | #define SWITCH_TABLE(fixp) \ | |
9838 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9839 | && (fixp)->fx_addsy != NULL \ | |
9840 | && (fixp)->fx_subsy != NULL \ | |
9841 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9842 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9843 | ||
5b63f465 | 9844 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
9845 | relocations, in case the linker has to relax a call. We also need |
9846 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
9847 | |
9848 | /*ARGSUSED*/ | |
9849 | int | |
9850 | mips_force_relocation (fixp) | |
9851 | fixS *fixp; | |
9852 | { | |
1c803e52 | 9853 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
9854 | && (fixp->fx_pcrel |
9855 | || SWITCH_TABLE (fixp) | |
9856 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9857 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
9858 | } |
9859 | ||
9860 | /* Apply a fixup to the object file. */ | |
9861 | ||
3d3c5039 ILT |
9862 | int |
9863 | md_apply_fix (fixP, valueP) | |
9864 | fixS *fixP; | |
918692a5 | 9865 | valueT *valueP; |
3d3c5039 | 9866 | { |
670a50eb ILT |
9867 | unsigned char *buf; |
9868 | long insn, value; | |
3d3c5039 | 9869 | |
bf39474f ILT |
9870 | assert (fixP->fx_size == 4 |
9871 | || fixP->fx_r_type == BFD_RELOC_16 | |
9872 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 9873 | |
670a50eb | 9874 | value = *valueP; |
1748b9d8 ILT |
9875 | |
9876 | /* If we aren't adjusting this fixup to be against the section | |
9877 | symbol, we need to adjust the value. */ | |
68952421 | 9878 | #ifdef OBJ_ELF |
1748b9d8 | 9879 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
9880 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
9881 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
9882 | { | |
9883 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9884 | if (value != 0 && ! fixP->fx_pcrel) | |
9885 | { | |
9886 | /* In this case, the bfd_install_relocation routine will | |
9887 | incorrectly add the symbol value back in. We just want | |
9888 | the addend to appear in the object file. */ | |
9889 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9890 | } | |
9891 | } | |
9892 | #endif | |
9893 | ||
670a50eb | 9894 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 9895 | |
5b63f465 ILT |
9896 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
9897 | fixP->fx_done = 1; | |
9898 | ||
670a50eb ILT |
9899 | switch (fixP->fx_r_type) |
9900 | { | |
3d3c5039 ILT |
9901 | case BFD_RELOC_MIPS_JMP: |
9902 | case BFD_RELOC_HI16: | |
9903 | case BFD_RELOC_HI16_S: | |
670a50eb | 9904 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
9905 | case BFD_RELOC_MIPS_LITERAL: |
9906 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
9907 | case BFD_RELOC_MIPS_GOT16: |
9908 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
9909 | case BFD_RELOC_MIPS_GOT_HI16: |
9910 | case BFD_RELOC_MIPS_GOT_LO16: | |
9911 | case BFD_RELOC_MIPS_CALL_HI16: | |
9912 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 9913 | case BFD_RELOC_MIPS16_GPREL: |
0bc0e337 JL |
9914 | /* start-sanitize-r5900 */ |
9915 | case BFD_RELOC_MIPS15_S3: | |
9916 | /* end-sanitize-r5900 */ | |
ecd4ca1c | 9917 | if (fixP->fx_pcrel) |
7b777690 | 9918 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 9919 | _("Invalid PC relative reloc")); |
670a50eb | 9920 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 9921 | break; |
3d3c5039 | 9922 | |
cc5703cd ILT |
9923 | case BFD_RELOC_MIPS16_JMP: |
9924 | /* We currently always generate a reloc against a symbol, which | |
9925 | means that we don't want an addend even if the symbol is | |
9926 | defined. */ | |
9927 | fixP->fx_addnumber = 0; | |
9928 | break; | |
9929 | ||
ecd4ca1c ILT |
9930 | case BFD_RELOC_PCREL_HI16_S: |
9931 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9932 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9933 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9934 | { | |
9935 | /* For an external symbol adjust by the address to make it | |
9936 | pcrel_offset. We use the address of the RELLO reloc | |
9937 | which follows this one. */ | |
9938 | value += (fixP->fx_next->fx_frag->fr_address | |
9939 | + fixP->fx_next->fx_where); | |
9940 | } | |
9941 | if (value & 0x8000) | |
9942 | value += 0x10000; | |
9943 | value >>= 16; | |
0221ddf7 | 9944 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9945 | if (target_big_endian) |
ecd4ca1c ILT |
9946 | buf += 2; |
9947 | md_number_to_chars (buf, value, 2); | |
9948 | break; | |
9949 | ||
9950 | case BFD_RELOC_PCREL_LO16: | |
9951 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9952 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9953 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9954 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 9955 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9956 | if (target_big_endian) |
ecd4ca1c ILT |
9957 | buf += 2; |
9958 | md_number_to_chars (buf, value, 2); | |
9959 | break; | |
9960 | ||
bf39474f ILT |
9961 | case BFD_RELOC_64: |
9962 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9963 | extended value if we are only 32 bits. */ | |
9964 | if (fixP->fx_done | |
9965 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9966 | { | |
9967 | if (8 <= sizeof (valueT)) | |
9968 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9969 | value, 8); | |
9970 | else | |
9971 | { | |
9972 | long w1, w2; | |
9973 | long hiv; | |
9974 | ||
9975 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9976 | if (target_big_endian) |
bf39474f ILT |
9977 | w1 += 4; |
9978 | else | |
9979 | w2 += 4; | |
9980 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9981 | if ((value & 0x80000000) != 0) | |
9982 | hiv = 0xffffffff; | |
9983 | else | |
9984 | hiv = 0; | |
9985 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9986 | } | |
9987 | } | |
9988 | break; | |
9989 | ||
f3645945 ILT |
9990 | case BFD_RELOC_32: |
9991 | /* If we are deleting this reloc entry, we must fill in the | |
9992 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9993 | resolved when it appears but is later defined. We also need |
9994 | to fill in the value if this is an embedded PIC switch table | |
9995 | entry. */ | |
9996 | if (fixP->fx_done | |
9997 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9998 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9999 | value, 4); | |
10000 | break; | |
10001 | ||
49ad0c4c ILT |
10002 | case BFD_RELOC_16: |
10003 | /* If we are deleting this reloc entry, we must fill in the | |
10004 | value now. */ | |
10005 | assert (fixP->fx_size == 2); | |
10006 | if (fixP->fx_done) | |
10007 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10008 | value, 2); | |
10009 | break; | |
10010 | ||
f3645945 ILT |
10011 | case BFD_RELOC_LO16: |
10012 | /* When handling an embedded PIC switch statement, we can wind | |
10013 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10014 | if (fixP->fx_done) | |
10015 | { | |
10016 | if (value < -0x8000 || value > 0x7fff) | |
10017 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10018 | _("relocation overflow")); |
0221ddf7 | 10019 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10020 | if (target_big_endian) |
f3645945 ILT |
10021 | buf += 2; |
10022 | md_number_to_chars (buf, value, 2); | |
10023 | } | |
10024 | break; | |
10025 | ||
3d3c5039 | 10026 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
10027 | /* |
10028 | * We need to save the bits in the instruction since fixup_segment() | |
10029 | * might be deleting the relocation entry (i.e., a branch within | |
10030 | * the current segment). | |
10031 | */ | |
fbcfacb7 | 10032 | if ((value & 0x3) != 0) |
3b320c48 | 10033 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10034 | _("Branch to odd address (%lx)"), value); |
670a50eb | 10035 | value >>= 2; |
670a50eb ILT |
10036 | |
10037 | /* update old instruction data */ | |
10038 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
10039 | if (target_big_endian) |
10040 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10041 | else | |
10042 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
10043 | |
10044 | if (value >= -0x8000 && value < 0x8000) | |
10045 | insn |= value & 0xffff; | |
10046 | else | |
10047 | { | |
10048 | /* The branch offset is too large. If this is an | |
10049 | unconditional branch, and we are not generating PIC code, | |
10050 | we can convert it to an absolute jump instruction. */ | |
10051 | if (mips_pic == NO_PIC | |
10052 | && fixP->fx_done | |
10053 | && fixP->fx_frag->fr_address >= text_section->vma | |
10054 | && (fixP->fx_frag->fr_address | |
10055 | < text_section->vma + text_section->_raw_size) | |
10056 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10057 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10058 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10059 | { | |
10060 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10061 | insn = 0x0c000000; /* jal */ | |
10062 | else | |
10063 | insn = 0x08000000; /* j */ | |
10064 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10065 | fixP->fx_done = 0; | |
10066 | fixP->fx_addsy = section_symbol (text_section); | |
10067 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10068 | } | |
10069 | else | |
10070 | { | |
10071 | /* FIXME. It would be possible in principle to handle | |
10072 | conditional branches which overflow. They could be | |
10073 | transformed into a branch around a jump. This would | |
10074 | require setting up variant frags for each different | |
10075 | branch type. The native MIPS assembler attempts to | |
10076 | handle these cases, but it appears to do it | |
10077 | incorrectly. */ | |
10078 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10079 | _("Branch out of range")); |
9da4c5d1 ILT |
10080 | } |
10081 | } | |
10082 | ||
604633ae | 10083 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 10084 | break; |
3d3c5039 ILT |
10085 | |
10086 | default: | |
670a50eb | 10087 | internalError (); |
3d3c5039 | 10088 | } |
5b63f465 | 10089 | |
670a50eb | 10090 | return 1; |
3d3c5039 ILT |
10091 | } |
10092 | ||
10093 | #if 0 | |
10094 | void | |
670a50eb ILT |
10095 | printInsn (oc) |
10096 | unsigned long oc; | |
3d3c5039 | 10097 | { |
670a50eb ILT |
10098 | const struct mips_opcode *p; |
10099 | int treg, sreg, dreg, shamt; | |
10100 | short imm; | |
10101 | const char *args; | |
10102 | int i; | |
3d3c5039 | 10103 | |
670a50eb ILT |
10104 | for (i = 0; i < NUMOPCODES; ++i) |
10105 | { | |
10106 | p = &mips_opcodes[i]; | |
10107 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10108 | { | |
10109 | printf ("%08lx %s\t", oc, p->name); | |
10110 | treg = (oc >> 16) & 0x1f; | |
10111 | sreg = (oc >> 21) & 0x1f; | |
10112 | dreg = (oc >> 11) & 0x1f; | |
10113 | shamt = (oc >> 6) & 0x1f; | |
10114 | imm = oc; | |
10115 | for (args = p->args;; ++args) | |
10116 | { | |
10117 | switch (*args) | |
10118 | { | |
3d3c5039 | 10119 | case '\0': |
670a50eb ILT |
10120 | printf ("\n"); |
10121 | break; | |
3d3c5039 ILT |
10122 | |
10123 | case ',': | |
10124 | case '(': | |
10125 | case ')': | |
670a50eb ILT |
10126 | printf ("%c", *args); |
10127 | continue; | |
3d3c5039 ILT |
10128 | |
10129 | case 'r': | |
670a50eb ILT |
10130 | assert (treg == sreg); |
10131 | printf ("$%d,$%d", treg, sreg); | |
10132 | continue; | |
3d3c5039 ILT |
10133 | |
10134 | case 'd': | |
918692a5 | 10135 | case 'G': |
670a50eb ILT |
10136 | printf ("$%d", dreg); |
10137 | continue; | |
3d3c5039 ILT |
10138 | |
10139 | case 't': | |
918692a5 | 10140 | case 'E': |
670a50eb ILT |
10141 | printf ("$%d", treg); |
10142 | continue; | |
3d3c5039 | 10143 | |
9226253a ILT |
10144 | case 'k': |
10145 | printf ("0x%x", treg); | |
10146 | continue; | |
10147 | ||
3d3c5039 ILT |
10148 | case 'b': |
10149 | case 's': | |
670a50eb ILT |
10150 | printf ("$%d", sreg); |
10151 | continue; | |
3d3c5039 ILT |
10152 | |
10153 | case 'a': | |
670a50eb ILT |
10154 | printf ("0x%08lx", oc & 0x1ffffff); |
10155 | continue; | |
3d3c5039 ILT |
10156 | |
10157 | case 'i': | |
10158 | case 'j': | |
10159 | case 'o': | |
10160 | case 'u': | |
670a50eb ILT |
10161 | printf ("%d", imm); |
10162 | continue; | |
3d3c5039 ILT |
10163 | |
10164 | case '<': | |
56c96faa | 10165 | case '>': |
670a50eb ILT |
10166 | printf ("$%d", shamt); |
10167 | continue; | |
3d3c5039 ILT |
10168 | |
10169 | default: | |
670a50eb | 10170 | internalError (); |
3d3c5039 | 10171 | } |
670a50eb | 10172 | break; |
3d3c5039 | 10173 | } |
670a50eb | 10174 | return; |
3d3c5039 ILT |
10175 | } |
10176 | } | |
48401fcf | 10177 | printf (_("%08lx UNDEFINED\n"), oc); |
3d3c5039 ILT |
10178 | } |
10179 | #endif | |
10180 | ||
10181 | static symbolS * | |
10182 | get_symbol () | |
10183 | { | |
670a50eb ILT |
10184 | int c; |
10185 | char *name; | |
10186 | symbolS *p; | |
10187 | ||
10188 | name = input_line_pointer; | |
10189 | c = get_symbol_end (); | |
10190 | p = (symbolS *) symbol_find_or_make (name); | |
10191 | *input_line_pointer = c; | |
10192 | return p; | |
3d3c5039 ILT |
10193 | } |
10194 | ||
becfe05e ILT |
10195 | /* Align the current frag to a given power of two. The MIPS assembler |
10196 | also automatically adjusts any preceding label. */ | |
10197 | ||
10198 | static void | |
23dc1ae3 | 10199 | mips_align (to, fill, label) |
becfe05e ILT |
10200 | int to; |
10201 | int fill; | |
23dc1ae3 | 10202 | symbolS *label; |
becfe05e | 10203 | { |
fbcfacb7 | 10204 | mips_emit_delays (false); |
e2e5acfa | 10205 | frag_align (to, fill, 0); |
becfe05e | 10206 | record_alignment (now_seg, to); |
23dc1ae3 | 10207 | if (label != NULL) |
becfe05e | 10208 | { |
23dc1ae3 ILT |
10209 | assert (S_GET_SEGMENT (label) == now_seg); |
10210 | label->sy_frag = frag_now; | |
10211 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
10212 | } |
10213 | } | |
10214 | ||
10215 | /* Align to a given power of two. .align 0 turns off the automatic | |
10216 | alignment used by the data creating pseudo-ops. */ | |
10217 | ||
3d3c5039 ILT |
10218 | static void |
10219 | s_align (x) | |
10220 | int x; | |
10221 | { | |
670a50eb ILT |
10222 | register int temp; |
10223 | register long temp_fill; | |
10224 | long max_alignment = 15; | |
3d3c5039 | 10225 | |
670a50eb | 10226 | /* |
3d3c5039 ILT |
10227 | |
10228 | o Note that the assembler pulls down any immediately preceeding label | |
10229 | to the aligned address. | |
10230 | o It's not documented but auto alignment is reinstated by | |
10231 | a .align pseudo instruction. | |
10232 | o Note also that after auto alignment is turned off the mips assembler | |
10233 | issues an error on attempt to assemble an improperly aligned data item. | |
10234 | We don't. | |
10235 | ||
10236 | */ | |
10237 | ||
670a50eb ILT |
10238 | temp = get_absolute_expression (); |
10239 | if (temp > max_alignment) | |
48401fcf | 10240 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
670a50eb ILT |
10241 | else if (temp < 0) |
10242 | { | |
48401fcf | 10243 | as_warn (_("Alignment negative: 0 assumed.")); |
670a50eb ILT |
10244 | temp = 0; |
10245 | } | |
10246 | if (*input_line_pointer == ',') | |
10247 | { | |
10248 | input_line_pointer++; | |
10249 | temp_fill = get_absolute_expression (); | |
10250 | } | |
10251 | else | |
10252 | temp_fill = 0; | |
10253 | if (temp) | |
10254 | { | |
10255 | auto_align = 1; | |
fbcfacb7 ILT |
10256 | mips_align (temp, (int) temp_fill, |
10257 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 10258 | } |
670a50eb ILT |
10259 | else |
10260 | { | |
10261 | auto_align = 0; | |
3d3c5039 ILT |
10262 | } |
10263 | ||
670a50eb | 10264 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10265 | } |
10266 | ||
739708fa KR |
10267 | void |
10268 | mips_flush_pending_output () | |
becfe05e | 10269 | { |
fbcfacb7 ILT |
10270 | mips_emit_delays (false); |
10271 | mips_clear_insn_labels (); | |
becfe05e ILT |
10272 | } |
10273 | ||
3d3c5039 ILT |
10274 | static void |
10275 | s_change_sec (sec) | |
10276 | int sec; | |
10277 | { | |
88225433 | 10278 | segT seg; |
becfe05e | 10279 | |
5b63f465 ILT |
10280 | /* When generating embedded PIC code, we only use the .text, .lit8, |
10281 | .sdata and .sbss sections. We change the .data and .rdata | |
10282 | pseudo-ops to use .sdata. */ | |
10283 | if (mips_pic == EMBEDDED_PIC | |
10284 | && (sec == 'd' || sec == 'r')) | |
10285 | sec = 's'; | |
10286 | ||
acdc7ce3 ILT |
10287 | #ifdef OBJ_ELF |
10288 | /* The ELF backend needs to know that we are changing sections, so | |
10289 | that .previous works correctly. We could do something like check | |
10290 | for a obj_section_change_hook macro, but that might be confusing | |
10291 | as it would not be appropriate to use it in the section changing | |
10292 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10293 | This should be cleaner, somehow. */ | |
10294 | obj_elf_section_change_hook (); | |
10295 | #endif | |
10296 | ||
fbcfacb7 | 10297 | mips_emit_delays (false); |
670a50eb ILT |
10298 | switch (sec) |
10299 | { | |
3d3c5039 | 10300 | case 't': |
604633ae | 10301 | s_text (0); |
670a50eb | 10302 | break; |
3d3c5039 | 10303 | case 'd': |
604633ae | 10304 | s_data (0); |
670a50eb | 10305 | break; |
3d3c5039 | 10306 | case 'b': |
670a50eb | 10307 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
10308 | demand_empty_rest_of_line (); |
10309 | break; | |
88225433 ILT |
10310 | |
10311 | case 'r': | |
1dc1e798 KR |
10312 | if (USE_GLOBAL_POINTER_OPT) |
10313 | { | |
10314 | seg = subseg_new (RDATA_SECTION_NAME, | |
10315 | (subsegT) get_absolute_expression ()); | |
10316 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10317 | { | |
10318 | bfd_set_section_flags (stdoutput, seg, | |
10319 | (SEC_ALLOC | |
10320 | | SEC_LOAD | |
10321 | | SEC_READONLY | |
10322 | | SEC_RELOC | |
10323 | | SEC_DATA)); | |
08e17202 ILT |
10324 | if (strcmp (TARGET_OS, "elf") != 0) |
10325 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10326 | } |
10327 | demand_empty_rest_of_line (); | |
10328 | } | |
10329 | else | |
10330 | { | |
48401fcf | 10331 | as_bad (_("No read only data section in this object file format")); |
1dc1e798 KR |
10332 | demand_empty_rest_of_line (); |
10333 | return; | |
10334 | } | |
88225433 | 10335 | break; |
88225433 ILT |
10336 | |
10337 | case 's': | |
1dc1e798 KR |
10338 | if (USE_GLOBAL_POINTER_OPT) |
10339 | { | |
10340 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10341 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10342 | { | |
10343 | bfd_set_section_flags (stdoutput, seg, | |
10344 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10345 | | SEC_DATA); | |
08e17202 ILT |
10346 | if (strcmp (TARGET_OS, "elf") != 0) |
10347 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10348 | } |
10349 | demand_empty_rest_of_line (); | |
10350 | break; | |
10351 | } | |
10352 | else | |
10353 | { | |
48401fcf | 10354 | as_bad (_("Global pointers not supported; recompile -G 0")); |
1dc1e798 KR |
10355 | demand_empty_rest_of_line (); |
10356 | return; | |
10357 | } | |
3d3c5039 | 10358 | } |
88225433 | 10359 | |
670a50eb | 10360 | auto_align = 1; |
3d3c5039 ILT |
10361 | } |
10362 | ||
739708fa KR |
10363 | void |
10364 | mips_enable_auto_align () | |
9da4c5d1 | 10365 | { |
9da4c5d1 ILT |
10366 | auto_align = 1; |
10367 | } | |
10368 | ||
3d3c5039 ILT |
10369 | static void |
10370 | s_cons (log_size) | |
10371 | int log_size; | |
10372 | { | |
23dc1ae3 ILT |
10373 | symbolS *label; |
10374 | ||
fbcfacb7 ILT |
10375 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10376 | mips_emit_delays (false); | |
670a50eb | 10377 | if (log_size > 0 && auto_align) |
23dc1ae3 | 10378 | mips_align (log_size, 0, label); |
fbcfacb7 | 10379 | mips_clear_insn_labels (); |
670a50eb | 10380 | cons (1 << log_size); |
3d3c5039 ILT |
10381 | } |
10382 | ||
3d3c5039 | 10383 | static void |
becfe05e ILT |
10384 | s_float_cons (type) |
10385 | int type; | |
3d3c5039 | 10386 | { |
23dc1ae3 ILT |
10387 | symbolS *label; |
10388 | ||
fbcfacb7 | 10389 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 10390 | |
fbcfacb7 | 10391 | mips_emit_delays (false); |
670a50eb ILT |
10392 | |
10393 | if (auto_align) | |
becfe05e | 10394 | if (type == 'd') |
23dc1ae3 | 10395 | mips_align (3, 0, label); |
670a50eb | 10396 | else |
23dc1ae3 | 10397 | mips_align (2, 0, label); |
670a50eb | 10398 | |
fbcfacb7 | 10399 | mips_clear_insn_labels (); |
1849d646 | 10400 | |
becfe05e | 10401 | float_cons (type); |
3d3c5039 ILT |
10402 | } |
10403 | ||
c1444ec4 ILT |
10404 | /* Handle .globl. We need to override it because on Irix 5 you are |
10405 | permitted to say | |
10406 | .globl foo .text | |
10407 | where foo is an undefined symbol, to mean that foo should be | |
10408 | considered to be the address of a function. */ | |
10409 | ||
10410 | static void | |
10411 | s_mips_globl (x) | |
10412 | int x; | |
10413 | { | |
10414 | char *name; | |
10415 | int c; | |
10416 | symbolS *symbolP; | |
fb251650 | 10417 | flagword flag; |
c1444ec4 ILT |
10418 | |
10419 | name = input_line_pointer; | |
10420 | c = get_symbol_end (); | |
10421 | symbolP = symbol_find_or_make (name); | |
10422 | *input_line_pointer = c; | |
10423 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10424 | |
10425 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10426 | being a function is apparently labelled as being an object. */ | |
10427 | flag = BSF_OBJECT; | |
10428 | ||
c1444ec4 ILT |
10429 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10430 | { | |
10431 | char *secname; | |
10432 | asection *sec; | |
10433 | ||
10434 | secname = input_line_pointer; | |
10435 | c = get_symbol_end (); | |
10436 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10437 | if (sec == NULL) | |
48401fcf | 10438 | as_bad (_("%s: no such section"), secname); |
c1444ec4 ILT |
10439 | *input_line_pointer = c; |
10440 | ||
10441 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10442 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10443 | } |
10444 | ||
fb251650 ILT |
10445 | symbolP->bsym->flags |= flag; |
10446 | ||
c1444ec4 ILT |
10447 | S_SET_EXTERNAL (symbolP); |
10448 | demand_empty_rest_of_line (); | |
10449 | } | |
10450 | ||
3d3c5039 ILT |
10451 | static void |
10452 | s_option (x) | |
10453 | int x; | |
10454 | { | |
dd3f1f76 ILT |
10455 | char *opt; |
10456 | char c; | |
10457 | ||
10458 | opt = input_line_pointer; | |
10459 | c = get_symbol_end (); | |
10460 | ||
dd3f1f76 | 10461 | if (*opt == 'O') |
9226253a ILT |
10462 | { |
10463 | /* FIXME: What does this mean? */ | |
10464 | } | |
dd3f1f76 | 10465 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10466 | { |
d9aba805 | 10467 | int i; |
42562568 | 10468 | |
d9aba805 ILT |
10469 | i = atoi (opt + 3); |
10470 | if (i == 0) | |
10471 | mips_pic = NO_PIC; | |
10472 | else if (i == 2) | |
10473 | mips_pic = SVR4_PIC; | |
10474 | else | |
48401fcf | 10475 | as_bad (_(".option pic%d not supported"), i); |
d9aba805 | 10476 | |
1dc1e798 | 10477 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10478 | { |
10479 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10480 | as_warn (_("-G may not be used with SVR4 PIC code")); |
42562568 ILT |
10481 | g_switch_value = 0; |
10482 | bfd_set_gp_size (stdoutput, 0); | |
10483 | } | |
9226253a | 10484 | } |
dd3f1f76 | 10485 | else |
48401fcf | 10486 | as_warn (_("Unrecognized option \"%s\""), opt); |
dd3f1f76 ILT |
10487 | |
10488 | *input_line_pointer = c; | |
670a50eb | 10489 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10490 | } |
10491 | ||
3c83da8a JW |
10492 | /* This structure is used to hold a stack of .set values. */ |
10493 | ||
10494 | struct mips_option_stack | |
10495 | { | |
10496 | struct mips_option_stack *next; | |
10497 | struct mips_set_options options; | |
10498 | }; | |
10499 | ||
10500 | static struct mips_option_stack *mips_opts_stack; | |
10501 | ||
10502 | /* Handle the .set pseudo-op. */ | |
10503 | ||
3d3c5039 ILT |
10504 | static void |
10505 | s_mipsset (x) | |
10506 | int x; | |
10507 | { | |
670a50eb ILT |
10508 | char *name = input_line_pointer, ch; |
10509 | ||
10510 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10511 | input_line_pointer++; | |
10512 | ch = *input_line_pointer; | |
10513 | *input_line_pointer = '\0'; | |
10514 | ||
10515 | if (strcmp (name, "reorder") == 0) | |
10516 | { | |
3c83da8a | 10517 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10518 | { |
4a1cb507 ILT |
10519 | /* If we still have pending nops, we can discard them. The |
10520 | usual nop handling will insert any that are still | |
10521 | needed. */ | |
3c83da8a JW |
10522 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10523 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10524 | prev_nop_frag = NULL; |
4e95866e | 10525 | } |
3c83da8a | 10526 | mips_opts.noreorder = 0; |
670a50eb ILT |
10527 | } |
10528 | else if (strcmp (name, "noreorder") == 0) | |
10529 | { | |
fbcfacb7 | 10530 | mips_emit_delays (true); |
3c83da8a | 10531 | mips_opts.noreorder = 1; |
0dd2d296 | 10532 | mips_any_noreorder = 1; |
670a50eb ILT |
10533 | } |
10534 | else if (strcmp (name, "at") == 0) | |
10535 | { | |
3c83da8a | 10536 | mips_opts.noat = 0; |
670a50eb ILT |
10537 | } |
10538 | else if (strcmp (name, "noat") == 0) | |
10539 | { | |
3c83da8a | 10540 | mips_opts.noat = 1; |
3d3c5039 | 10541 | } |
670a50eb ILT |
10542 | else if (strcmp (name, "macro") == 0) |
10543 | { | |
3c83da8a | 10544 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10545 | } |
10546 | else if (strcmp (name, "nomacro") == 0) | |
10547 | { | |
3c83da8a | 10548 | if (mips_opts.noreorder == 0) |
48401fcf | 10549 | as_bad (_("`noreorder' must be set before `nomacro'")); |
3c83da8a | 10550 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10551 | } |
10552 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10553 | { | |
3c83da8a | 10554 | mips_opts.nomove = 0; |
670a50eb ILT |
10555 | } |
10556 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10557 | { | |
3c83da8a | 10558 | mips_opts.nomove = 1; |
670a50eb ILT |
10559 | } |
10560 | else if (strcmp (name, "bopt") == 0) | |
10561 | { | |
3c83da8a | 10562 | mips_opts.nobopt = 0; |
670a50eb ILT |
10563 | } |
10564 | else if (strcmp (name, "nobopt") == 0) | |
10565 | { | |
3c83da8a | 10566 | mips_opts.nobopt = 1; |
670a50eb | 10567 | } |
943321c0 ILT |
10568 | else if (strcmp (name, "mips16") == 0 |
10569 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10570 | mips_opts.mips16 = 1; |
943321c0 ILT |
10571 | else if (strcmp (name, "nomips16") == 0 |
10572 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10573 | mips_opts.mips16 = 0; |
1051c97f ILT |
10574 | else if (strncmp (name, "mips", 4) == 0) |
10575 | { | |
10576 | int isa; | |
10577 | ||
10578 | /* Permit the user to change the ISA on the fly. Needless to | |
10579 | say, misuse can cause serious problems. */ | |
10580 | isa = atoi (name + 4); | |
10581 | if (isa == 0) | |
3c83da8a | 10582 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10583 | else if (isa < 1 || isa > 4) |
48401fcf | 10584 | as_bad (_("unknown ISA level")); |
1051c97f | 10585 | else |
3c83da8a | 10586 | mips_opts.isa = isa; |
1051c97f | 10587 | } |
cc5703cd | 10588 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10589 | mips_opts.noautoextend = 0; |
cc5703cd | 10590 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10591 | mips_opts.noautoextend = 1; |
10592 | else if (strcmp (name, "push") == 0) | |
10593 | { | |
10594 | struct mips_option_stack *s; | |
10595 | ||
10596 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10597 | s->next = mips_opts_stack; | |
10598 | s->options = mips_opts; | |
10599 | mips_opts_stack = s; | |
10600 | } | |
10601 | else if (strcmp (name, "pop") == 0) | |
10602 | { | |
10603 | struct mips_option_stack *s; | |
10604 | ||
10605 | s = mips_opts_stack; | |
10606 | if (s == NULL) | |
48401fcf | 10607 | as_bad (_(".set pop with no .set push")); |
3c83da8a JW |
10608 | else |
10609 | { | |
10610 | /* If we're changing the reorder mode we need to handle | |
10611 | delay slots correctly. */ | |
10612 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10613 | mips_emit_delays (true); | |
10614 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10615 | { | |
10616 | if (prev_nop_frag != NULL) | |
10617 | { | |
10618 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10619 | * (mips_opts.mips16 ? 2 : 4)); | |
10620 | prev_nop_frag = NULL; | |
10621 | } | |
10622 | } | |
10623 | ||
10624 | mips_opts = s->options; | |
10625 | mips_opts_stack = s->next; | |
10626 | free (s); | |
10627 | } | |
10628 | } | |
670a50eb ILT |
10629 | else |
10630 | { | |
48401fcf | 10631 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
670a50eb ILT |
10632 | } |
10633 | *input_line_pointer = ch; | |
10634 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10635 | } |
10636 | ||
9226253a ILT |
10637 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10638 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10639 | ||
10640 | static void | |
10641 | s_abicalls (ignore) | |
10642 | int ignore; | |
10643 | { | |
d9aba805 | 10644 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10645 | if (USE_GLOBAL_POINTER_OPT) |
10646 | { | |
10647 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10648 | as_warn (_("-G may not be used with SVR4 PIC code")); |
1dc1e798 KR |
10649 | g_switch_value = 0; |
10650 | } | |
d9aba805 | 10651 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10652 | demand_empty_rest_of_line (); |
10653 | } | |
10654 | ||
10655 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10656 | PIC code. It sets the $gp register for the function based on the | |
10657 | function address, which is in the register named in the argument. | |
10658 | This uses a relocation against _gp_disp, which is handled specially | |
10659 | by the linker. The result is: | |
10660 | lui $gp,%hi(_gp_disp) | |
10661 | addiu $gp,$gp,%lo(_gp_disp) | |
10662 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10663 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10664 | |
10665 | static void | |
10666 | s_cpload (ignore) | |
10667 | int ignore; | |
10668 | { | |
10669 | expressionS ex; | |
10670 | int icnt = 0; | |
10671 | ||
d9aba805 ILT |
10672 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10673 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10674 | { |
10675 | s_ignore (0); | |
10676 | return; | |
10677 | } | |
10678 | ||
10679 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10680 | if (mips_opts.noreorder == 0) |
48401fcf | 10681 | as_warn (_(".cpload not in noreorder section")); |
0dd2d296 | 10682 | |
9226253a ILT |
10683 | ex.X_op = O_symbol; |
10684 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10685 | ex.X_op_symbol = NULL; | |
10686 | ex.X_add_number = 0; | |
10687 | ||
fb251650 ILT |
10688 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10689 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10690 | ||
0dd2d296 ILT |
10691 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10692 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10693 | (int) BFD_RELOC_LO16); |
10694 | ||
0dd2d296 ILT |
10695 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10696 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10697 | |
10698 | demand_empty_rest_of_line (); | |
10699 | } | |
10700 | ||
10701 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10702 | offset from $sp. The offset is remembered, and after making a PIC | |
10703 | call $gp is restored from that location. */ | |
10704 | ||
10705 | static void | |
10706 | s_cprestore (ignore) | |
10707 | int ignore; | |
10708 | { | |
10709 | expressionS ex; | |
10710 | int icnt = 0; | |
10711 | ||
d9aba805 ILT |
10712 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10713 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10714 | { |
10715 | s_ignore (0); | |
10716 | return; | |
10717 | } | |
10718 | ||
9226253a ILT |
10719 | mips_cprestore_offset = get_absolute_expression (); |
10720 | ||
10721 | ex.X_op = O_constant; | |
10722 | ex.X_add_symbol = NULL; | |
10723 | ex.X_op_symbol = NULL; | |
10724 | ex.X_add_number = mips_cprestore_offset; | |
10725 | ||
0dd2d296 | 10726 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
10727 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10728 | || mips_opts.isa < 3) | |
10729 | ? "sw" : "sd"), | |
9226253a ILT |
10730 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10731 | ||
10732 | demand_empty_rest_of_line (); | |
10733 | } | |
10734 | ||
0dd2d296 ILT |
10735 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10736 | code. It generates a 32 bit GP relative reloc. */ | |
10737 | ||
10738 | static void | |
10739 | s_gpword (ignore) | |
10740 | int ignore; | |
10741 | { | |
23dc1ae3 | 10742 | symbolS *label; |
0dd2d296 ILT |
10743 | expressionS ex; |
10744 | char *p; | |
10745 | ||
10746 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10747 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10748 | { |
10749 | s_cons (2); | |
10750 | return; | |
10751 | } | |
10752 | ||
fbcfacb7 ILT |
10753 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10754 | mips_emit_delays (true); | |
0dd2d296 | 10755 | if (auto_align) |
23dc1ae3 | 10756 | mips_align (2, 0, label); |
fbcfacb7 | 10757 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10758 | |
10759 | expression (&ex); | |
10760 | ||
10761 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10762 | { | |
48401fcf | 10763 | as_bad (_("Unsupported use of .gpword")); |
0dd2d296 ILT |
10764 | ignore_rest_of_line (); |
10765 | } | |
10766 | ||
10767 | p = frag_more (4); | |
10768 | md_number_to_chars (p, (valueT) 0, 4); | |
10769 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10770 | BFD_RELOC_MIPS_GPREL32); | |
10771 | ||
10772 | demand_empty_rest_of_line (); | |
10773 | } | |
10774 | ||
10775 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10776 | tables in SVR4 PIC code. */ | |
10777 | ||
10778 | static void | |
10779 | s_cpadd (ignore) | |
10780 | int ignore; | |
10781 | { | |
10782 | int icnt = 0; | |
10783 | int reg; | |
10784 | ||
10785 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10786 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10787 | { |
10788 | s_ignore (0); | |
10789 | return; | |
10790 | } | |
10791 | ||
10792 | /* Add $gp to the register named as an argument. */ | |
10793 | reg = tc_get_register (0); | |
10794 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
10795 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10796 | || mips_opts.isa < 3) | |
10797 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
10798 | "d,v,t", reg, reg, GP); |
10799 | ||
10800 | demand_empty_rest_of_line (); | |
10801 | } | |
10802 | ||
ed3eb786 ILT |
10803 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10804 | mips16 mode. This permits the linker to handle them specially, | |
10805 | such as generating jalx instructions when needed. We also make | |
10806 | them odd for the duration of the assembly, in order to generate the | |
10807 | right sort of code. We will make them even in the adjust_symtab | |
10808 | routine, while leaving them marked. This is convenient for the | |
10809 | debugger and the disassembler. The linker knows to make them odd | |
10810 | again. */ | |
10811 | ||
10812 | static void | |
10813 | s_insn (ignore) | |
10814 | int ignore; | |
10815 | { | |
3c83da8a JW |
10816 | if (mips_opts.mips16) |
10817 | mips16_mark_labels (); | |
ed3eb786 | 10818 | |
3c83da8a JW |
10819 | demand_empty_rest_of_line (); |
10820 | } | |
ed3eb786 | 10821 | |
3c83da8a JW |
10822 | /* Handle a .stabn directive. We need these in order to mark a label |
10823 | as being a mips16 text label correctly. Sometimes the compiler | |
10824 | will emit a label, followed by a .stabn, and then switch sections. | |
10825 | If the label and .stabn are in mips16 mode, then the label is | |
10826 | really a mips16 text label. */ | |
ed3eb786 | 10827 | |
3c83da8a JW |
10828 | static void |
10829 | s_mips_stab (type) | |
10830 | int type; | |
10831 | { | |
10832 | if (type == 'n' && mips_opts.mips16) | |
10833 | mips16_mark_labels (); | |
10834 | ||
10835 | s_stab (type); | |
ed3eb786 ILT |
10836 | } |
10837 | ||
3c69baf9 GRK |
10838 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
10839 | */ | |
10840 | ||
10841 | static void | |
10842 | s_mips_weakext (ignore) | |
10843 | int ignore; | |
10844 | { | |
10845 | char *name; | |
10846 | int c; | |
10847 | symbolS *symbolP; | |
10848 | expressionS exp; | |
10849 | ||
10850 | name = input_line_pointer; | |
10851 | c = get_symbol_end (); | |
10852 | symbolP = symbol_find_or_make (name); | |
10853 | S_SET_WEAK (symbolP); | |
10854 | *input_line_pointer = c; | |
10855 | ||
10856 | SKIP_WHITESPACE (); | |
10857 | ||
10858 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10859 | { | |
10860 | if (S_IS_DEFINED (symbolP)) | |
10861 | { | |
10862 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10863 | S_GET_NAME (symbolP)); | |
10864 | ignore_rest_of_line (); | |
10865 | return; | |
10866 | } | |
10867 | ||
10868 | if (*input_line_pointer == ',') | |
10869 | { | |
10870 | ++input_line_pointer; | |
10871 | SKIP_WHITESPACE (); | |
10872 | } | |
10873 | ||
10874 | expression (&exp); | |
10875 | if (exp.X_op != O_symbol) | |
10876 | { | |
10877 | as_bad ("bad .weakext directive"); | |
10878 | ignore_rest_of_line(); | |
10879 | return; | |
10880 | } | |
10881 | symbolP->sy_value = exp; | |
10882 | } | |
10883 | ||
10884 | demand_empty_rest_of_line (); | |
10885 | } | |
10886 | ||
9226253a | 10887 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
10888 | to parse .frame. The argument is non-zero if this is the frame |
10889 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 10890 | |
3d3c5039 | 10891 | int |
0dd2d296 ILT |
10892 | tc_get_register (frame) |
10893 | int frame; | |
3d3c5039 ILT |
10894 | { |
10895 | int reg; | |
10896 | ||
10897 | SKIP_WHITESPACE (); | |
10898 | if (*input_line_pointer++ != '$') | |
10899 | { | |
48401fcf | 10900 | as_warn (_("expected `$'")); |
0dd2d296 | 10901 | reg = 0; |
3d3c5039 | 10902 | } |
0dd2d296 | 10903 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
10904 | { |
10905 | reg = get_absolute_expression (); | |
10906 | if (reg < 0 || reg >= 32) | |
10907 | { | |
48401fcf | 10908 | as_warn (_("Bad register number")); |
3d3c5039 ILT |
10909 | reg = 0; |
10910 | } | |
10911 | } | |
10912 | else | |
10913 | { | |
10914 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 10915 | reg = FP; |
3d3c5039 | 10916 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 10917 | reg = SP; |
3d3c5039 | 10918 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 10919 | reg = GP; |
3d3c5039 | 10920 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 10921 | reg = AT; |
3d3c5039 ILT |
10922 | else |
10923 | { | |
48401fcf | 10924 | as_warn (_("Unrecognized register name")); |
0dd2d296 | 10925 | reg = 0; |
3d3c5039 ILT |
10926 | } |
10927 | input_line_pointer += 2; | |
10928 | } | |
0dd2d296 ILT |
10929 | if (frame) |
10930 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
10931 | return reg; |
10932 | } | |
10933 | ||
0dd2d296 ILT |
10934 | valueT |
10935 | md_section_align (seg, addr) | |
10936 | asection *seg; | |
10937 | valueT addr; | |
10938 | { | |
10939 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10940 | ||
cf32394d ILT |
10941 | #ifdef OBJ_ELF |
10942 | /* We don't need to align ELF sections to the full alignment. | |
10943 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
10944 | byte boundary. We don't bother to align the sections if we are |
10945 | targeted for an embedded system. */ | |
10946 | if (strcmp (TARGET_OS, "elf") == 0) | |
10947 | return addr; | |
943321c0 ILT |
10948 | if (align > 4) |
10949 | align = 4; | |
10a14e36 | 10950 | #endif |
cf32394d ILT |
10951 | |
10952 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
10953 | } |
10954 | ||
d8a1c247 KR |
10955 | /* Utility routine, called from above as well. If called while the |
10956 | input file is still being read, it's only an approximation. (For | |
10957 | example, a symbol may later become defined which appeared to be | |
10958 | undefined earlier.) */ | |
22ba90ce ILT |
10959 | |
10960 | static int | |
85ce5635 | 10961 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 10962 | symbolS *sym; |
85ce5635 | 10963 | int before_relaxing; |
d8a1c247 KR |
10964 | { |
10965 | if (sym == 0) | |
10966 | return 0; | |
10967 | ||
1dc1e798 KR |
10968 | if (USE_GLOBAL_POINTER_OPT) |
10969 | { | |
10970 | const char *symname; | |
10971 | int change; | |
10972 | ||
10973 | /* Find out whether this symbol can be referenced off the GP | |
10974 | register. It can be if it is smaller than the -G size or if | |
10975 | it is in the .sdata or .sbss section. Certain symbols can | |
10976 | not be referenced off the GP, although it appears as though | |
10977 | they can. */ | |
10978 | symname = S_GET_NAME (sym); | |
10979 | if (symname != (const char *) NULL | |
10980 | && (strcmp (symname, "eprol") == 0 | |
10981 | || strcmp (symname, "etext") == 0 | |
10982 | || strcmp (symname, "_gp") == 0 | |
10983 | || strcmp (symname, "edata") == 0 | |
10984 | || strcmp (symname, "_fbss") == 0 | |
10985 | || strcmp (symname, "_fdata") == 0 | |
10986 | || strcmp (symname, "_ftext") == 0 | |
10987 | || strcmp (symname, "end") == 0 | |
10988 | || strcmp (symname, "_gp_disp") == 0)) | |
10989 | change = 1; | |
23ac3ca1 | 10990 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
10991 | && (0 |
10992 | #ifndef NO_ECOFF_DEBUGGING | |
10993 | || (sym->ecoff_extern_size != 0 | |
10994 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 10995 | #endif |
85ce5635 ILT |
10996 | /* We must defer this decision until after the whole |
10997 | file has been read, since there might be a .extern | |
10998 | after the first use of this symbol. */ | |
a5586bdc ILT |
10999 | || (before_relaxing |
11000 | #ifndef NO_ECOFF_DEBUGGING | |
11001 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 11002 | #endif |
a5586bdc | 11003 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
11004 | || (S_GET_VALUE (sym) != 0 |
11005 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11006 | change = 0; | |
11007 | else | |
11008 | { | |
11009 | const char *segname; | |
d8a1c247 | 11010 | |
1dc1e798 KR |
11011 | segname = segment_name (S_GET_SEGMENT (sym)); |
11012 | assert (strcmp (segname, ".lit8") != 0 | |
11013 | && strcmp (segname, ".lit4") != 0); | |
11014 | change = (strcmp (segname, ".sdata") != 0 | |
11015 | && strcmp (segname, ".sbss") != 0); | |
11016 | } | |
11017 | return change; | |
11018 | } | |
11019 | else | |
11020 | /* We are not optimizing for the GP register. */ | |
11021 | return 1; | |
d8a1c247 KR |
11022 | } |
11023 | ||
cc5703cd ILT |
11024 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
11025 | extended opcode. SEC is the section the frag is in. */ | |
11026 | ||
11027 | static int | |
11028 | mips16_extended_frag (fragp, sec, stretch) | |
11029 | fragS *fragp; | |
11030 | asection *sec; | |
11031 | long stretch; | |
11032 | { | |
11033 | int type; | |
11034 | register const struct mips16_immed_operand *op; | |
11035 | offsetT val; | |
11036 | int mintiny, maxtiny; | |
f74ba7a3 | 11037 | segT symsec; |
cc5703cd | 11038 | |
8728fa92 ILT |
11039 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
11040 | return 0; | |
11041 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11042 | return 1; | |
11043 | ||
cc5703cd ILT |
11044 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
11045 | op = mips16_immed_operands; | |
11046 | while (op->type != type) | |
11047 | { | |
11048 | ++op; | |
11049 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11050 | } | |
11051 | ||
11052 | if (op->unsp) | |
11053 | { | |
11054 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11055 | { | |
11056 | mintiny = 1; | |
11057 | maxtiny = 1 << op->nbits; | |
11058 | } | |
11059 | else | |
11060 | { | |
11061 | mintiny = 0; | |
11062 | maxtiny = (1 << op->nbits) - 1; | |
11063 | } | |
11064 | } | |
11065 | else | |
11066 | { | |
11067 | mintiny = - (1 << (op->nbits - 1)); | |
11068 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11069 | } | |
11070 | ||
f74ba7a3 ILT |
11071 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
11072 | a particular frag address. */ | |
11073 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
11074 | { | |
11075 | val = (fragp->fr_symbol->sy_value.X_add_number | |
11076 | + fragp->fr_symbol->sy_frag->fr_address); | |
11077 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
11078 | } | |
11079 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
11080 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
11081 | == O_constant)) | |
11082 | { | |
11083 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
11084 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
11085 | + fragp->fr_symbol->sy_value.X_add_number | |
11086 | + fragp->fr_symbol->sy_frag->fr_address); | |
11087 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
11088 | } | |
11089 | else | |
11090 | return 1; | |
cc5703cd ILT |
11091 | |
11092 | if (op->pcrel) | |
11093 | { | |
11094 | addressT addr; | |
11095 | ||
11096 | /* We won't have the section when we are called from | |
11097 | mips_relax_frag. However, we will always have been called | |
11098 | from md_estimate_size_before_relax first. If this is a | |
11099 | branch to a different section, we mark it as such. If SEC is | |
11100 | NULL, and the frag is not marked, then it must be a branch to | |
11101 | the same section. */ | |
11102 | if (sec == NULL) | |
11103 | { | |
11104 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11105 | return 1; | |
11106 | } | |
11107 | else | |
11108 | { | |
f74ba7a3 | 11109 | if (symsec != sec) |
cc5703cd ILT |
11110 | { |
11111 | fragp->fr_subtype = | |
11112 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11113 | ||
11114 | /* FIXME: We should support this, and let the linker | |
11115 | catch branches and loads that are out of range. */ | |
11116 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11117 | _("unsupported PC relative reference to different section")); |
cc5703cd ILT |
11118 | |
11119 | return 1; | |
11120 | } | |
11121 | } | |
11122 | ||
11123 | /* In this case, we know for sure that the symbol fragment is in | |
11124 | the same section. If the fr_address of the symbol fragment | |
11125 | is greater then the address of this fragment we want to add | |
11126 | in STRETCH in order to get a better estimate of the address. | |
11127 | This particularly matters because of the shift bits. */ | |
11128 | if (stretch != 0 | |
11129 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
11130 | { | |
11131 | fragS *f; | |
11132 | ||
a941619c ILT |
11133 | /* Adjust stretch for any alignment frag. Note that if have |
11134 | been expanding the earlier code, the symbol may be | |
11135 | defined in what appears to be an earlier frag. FIXME: | |
11136 | This doesn't handle the fr_subtype field, which specifies | |
11137 | a maximum number of bytes to skip when doing an | |
11138 | alignment. */ | |
11139 | for (f = fragp; | |
11140 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
11141 | f = f->fr_next) | |
cc5703cd | 11142 | { |
cc5703cd ILT |
11143 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
11144 | { | |
11145 | if (stretch < 0) | |
11146 | stretch = - ((- stretch) | |
11147 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11148 | else | |
11149 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11150 | if (stretch == 0) | |
11151 | break; | |
11152 | } | |
11153 | } | |
a941619c ILT |
11154 | if (f != NULL) |
11155 | val += stretch; | |
cc5703cd ILT |
11156 | } |
11157 | ||
a677feeb ILT |
11158 | addr = fragp->fr_address + fragp->fr_fix; |
11159 | ||
11160 | /* The base address rules are complicated. The base address of | |
11161 | a branch is the following instruction. The base address of a | |
11162 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
11163 | is in a delay slot (in which case it can not be extended) use |
11164 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 11165 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
11166 | { |
11167 | addr += 2; | |
319305a7 ILT |
11168 | |
11169 | /* If we are currently assuming that this frag should be | |
11170 | extended, then, the current address is two bytes | |
11171 | higher. */ | |
11172 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11173 | addr += 2; | |
11174 | ||
fbcfacb7 ILT |
11175 | /* Ignore the low bit in the target, since it will be set |
11176 | for a text label. */ | |
11177 | if ((val & 1) != 0) | |
11178 | --val; | |
11179 | } | |
a677feeb ILT |
11180 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11181 | addr -= 4; | |
11182 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11183 | addr -= 2; | |
cc5703cd | 11184 | |
cc5703cd ILT |
11185 | val -= addr & ~ ((1 << op->shift) - 1); |
11186 | ||
11187 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11188 | if (type == 'p' || type == 'q') | |
11189 | val /= 2; | |
11190 | ||
11191 | /* If any of the shifted bits are set, we must use an extended | |
11192 | opcode. If the address depends on the size of this | |
11193 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
11194 | use an extended opcode. We only check this when we are in |
11195 | the main relaxation loop, when SEC is NULL. */ | |
11196 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11197 | { | |
11198 | fragp->fr_subtype = | |
11199 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11200 | return 1; | |
11201 | } | |
11202 | ||
11203 | /* If we are about to mark a frag as extended because the value | |
11204 | is precisely maxtiny + 1, then there is a chance of an | |
11205 | infinite loop as in the following code: | |
11206 | la $4,foo | |
11207 | .skip 1020 | |
11208 | .align 2 | |
11209 | foo: | |
11210 | In this case when the la is extended, foo is 0x3fc bytes | |
11211 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11212 | the la must be extended. To avoid this loop, we mark the | |
11213 | frag as extended if it was small, and is about to become | |
11214 | extended with a value of maxtiny + 1. */ | |
11215 | if (val == ((maxtiny + 1) << op->shift) | |
11216 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11217 | && sec == NULL) | |
cc5703cd ILT |
11218 | { |
11219 | fragp->fr_subtype = | |
11220 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11221 | return 1; | |
11222 | } | |
11223 | } | |
41a0ed22 | 11224 | else if (symsec != absolute_section && sec != NULL) |
48401fcf | 11225 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
cc5703cd ILT |
11226 | |
11227 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11228 | || val < (mintiny << op->shift) | |
11229 | || val > (maxtiny << op->shift)) | |
11230 | return 1; | |
11231 | else | |
11232 | return 0; | |
11233 | } | |
11234 | ||
11235 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11236 | mips16, we are not really relaxing here, and the final size is | |
11237 | encoded in the subtype information. For the mips16, we have to | |
11238 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 11239 | |
0dd2d296 ILT |
11240 | /*ARGSUSED*/ |
11241 | int | |
11242 | md_estimate_size_before_relax (fragp, segtype) | |
11243 | fragS *fragp; | |
11244 | asection *segtype; | |
11245 | { | |
11246 | int change; | |
11247 | ||
cc5703cd ILT |
11248 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11249 | { | |
11250 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11251 | { | |
11252 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11253 | return 4; | |
11254 | } | |
11255 | else | |
11256 | { | |
11257 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11258 | return 2; | |
11259 | } | |
11260 | } | |
11261 | ||
d9aba805 | 11262 | if (mips_pic == NO_PIC) |
0dd2d296 | 11263 | { |
85ce5635 | 11264 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 11265 | } |
d9aba805 | 11266 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11267 | { |
46a92fde ILT |
11268 | symbolS *sym; |
11269 | asection *symsec; | |
11270 | ||
11271 | sym = fragp->fr_symbol; | |
11272 | ||
11273 | /* Handle the case of a symbol equated to another symbol. */ | |
11274 | while (sym->sy_value.X_op == O_symbol | |
11275 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
11276 | { | |
11277 | symbolS *n; | |
11278 | ||
11279 | /* It's possible to get a loop here in a badly written | |
11280 | program. */ | |
11281 | n = sym->sy_value.X_add_symbol; | |
11282 | if (n == sym) | |
11283 | break; | |
11284 | sym = n; | |
11285 | } | |
11286 | ||
11287 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
11288 | |
11289 | /* This must duplicate the test in adjust_reloc_syms. */ | |
11290 | change = (symsec != &bfd_und_section | |
11291 | && symsec != &bfd_abs_section | |
11292 | && ! bfd_is_com_section (symsec)); | |
11293 | } | |
d9aba805 ILT |
11294 | else |
11295 | abort (); | |
0dd2d296 ILT |
11296 | |
11297 | if (change) | |
11298 | { | |
11299 | /* Record the offset to the first reloc in the fr_opcode field. | |
11300 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11301 | must be expanded. */ | |
11302 | fragp->fr_opcode = (fragp->fr_literal | |
11303 | + fragp->fr_fix | |
11304 | - RELAX_OLD (fragp->fr_subtype) | |
11305 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11306 | /* FIXME: This really needs as_warn_where. */ | |
11307 | if (RELAX_WARN (fragp->fr_subtype)) | |
48401fcf | 11308 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); |
0dd2d296 ILT |
11309 | } |
11310 | ||
11311 | if (! change) | |
11312 | return 0; | |
11313 | else | |
11314 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11315 | } | |
11316 | ||
0d7f9025 ILT |
11317 | /* This is called to see whether a reloc against a defined symbol |
11318 | should be converted into a reloc against a section. Don't adjust | |
11319 | MIPS16 jump relocations, so we don't have to worry about the format | |
11320 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
11321 | mips16 symbols, so that the linker can find them if it needs to set |
11322 | up a stub. */ | |
0d7f9025 ILT |
11323 | |
11324 | int | |
11325 | mips_fix_adjustable (fixp) | |
11326 | fixS *fixp; | |
11327 | { | |
11328 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11329 | return 0; | |
11330 | if (fixp->fx_addsy == NULL) | |
11331 | return 1; | |
68952421 | 11332 | #ifdef OBJ_ELF |
0d7f9025 | 11333 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
11334 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
11335 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
11336 | return 0; |
11337 | #endif | |
11338 | return 1; | |
11339 | } | |
11340 | ||
0dd2d296 ILT |
11341 | /* Translate internal representation of relocation info to BFD target |
11342 | format. */ | |
11343 | ||
11344 | arelent ** | |
3d3c5039 ILT |
11345 | tc_gen_reloc (section, fixp) |
11346 | asection *section; | |
11347 | fixS *fixp; | |
11348 | { | |
0dd2d296 | 11349 | static arelent *retval[4]; |
3d3c5039 | 11350 | arelent *reloc; |
a8aed9dd | 11351 | bfd_reloc_code_real_type code; |
3d3c5039 | 11352 | |
0dd2d296 ILT |
11353 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
11354 | retval[1] = NULL; | |
3d3c5039 ILT |
11355 | |
11356 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11357 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
11358 | |
11359 | if (mips_pic == EMBEDDED_PIC | |
11360 | && SWITCH_TABLE (fixp)) | |
11361 | { | |
11362 | /* For a switch table entry we use a special reloc. The addend | |
11363 | is actually the difference between the reloc address and the | |
11364 | subtrahend. */ | |
11365 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 | 11366 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
48401fcf | 11367 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
1c803e52 ILT |
11368 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
11369 | } | |
ecd4ca1c ILT |
11370 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11371 | { | |
11372 | /* We use a special addend for an internal RELLO reloc. */ | |
11373 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11374 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11375 | else | |
11376 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11377 | } | |
11378 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11379 | { | |
11380 | assert (fixp->fx_next != NULL | |
11381 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11382 | /* We use a special addend for an internal RELHI reloc. The | |
11383 | reloc is relative to the RELLO; adjust the addend | |
11384 | accordingly. */ | |
11385 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11386 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
11387 | + fixp->fx_next->fx_where | |
11388 | - S_GET_VALUE (fixp->fx_subsy)); | |
11389 | else | |
11390 | reloc->addend = (fixp->fx_addnumber | |
11391 | + fixp->fx_next->fx_frag->fr_address | |
11392 | + fixp->fx_next->fx_where); | |
11393 | } | |
1c803e52 | 11394 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
11395 | reloc->addend = fixp->fx_addnumber; |
11396 | else | |
5b63f465 | 11397 | { |
1dc1e798 KR |
11398 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
11399 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11400 | handling. */ | |
11401 | reloc->addend = reloc->address; | |
11402 | else | |
11403 | reloc->addend = -reloc->address; | |
5b63f465 | 11404 | } |
0dd2d296 ILT |
11405 | |
11406 | /* If this is a variant frag, we may need to adjust the existing | |
11407 | reloc and generate a new one. */ | |
11408 | if (fixp->fx_frag->fr_opcode != NULL | |
11409 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11410 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
11411 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
11412 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11413 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11414 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11415 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
11416 | { |
11417 | arelent *reloc2; | |
11418 | ||
cc5703cd ILT |
11419 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
11420 | ||
0dd2d296 | 11421 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
11422 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
11423 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11424 | the second one handle all of them. */ | |
0dd2d296 ILT |
11425 | if (fixp->fx_next != NULL |
11426 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11427 | { | |
fb251650 ILT |
11428 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
11429 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11430 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11431 | && (fixp->fx_next->fx_r_type | |
11432 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11433 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11434 | && (fixp->fx_next->fx_r_type | |
11435 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
11436 | retval[0] = NULL; |
11437 | return retval; | |
11438 | } | |
11439 | ||
11440 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11441 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11442 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11443 | retval[2] = NULL; | |
11444 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11445 | reloc2->address = (reloc->address | |
11446 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11447 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11448 | reloc2->addend = fixp->fx_addnumber; | |
11449 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11450 | assert (reloc2->howto != NULL); | |
11451 | ||
11452 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11453 | { | |
11454 | arelent *reloc3; | |
11455 | ||
11456 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11457 | retval[3] = NULL; | |
11458 | *reloc3 = *reloc2; | |
11459 | reloc3->address += 4; | |
11460 | } | |
11461 | ||
d9aba805 | 11462 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11463 | { |
11464 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11465 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11466 | } | |
d9aba805 | 11467 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11468 | { |
fb251650 | 11469 | switch (fixp->fx_r_type) |
0dd2d296 | 11470 | { |
fb251650 ILT |
11471 | default: |
11472 | abort (); | |
11473 | case BFD_RELOC_MIPS_GOT16: | |
11474 | break; | |
11475 | case BFD_RELOC_MIPS_CALL16: | |
11476 | case BFD_RELOC_MIPS_GOT_LO16: | |
11477 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11478 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11479 | break; |
0dd2d296 ILT |
11480 | } |
11481 | } | |
d9aba805 ILT |
11482 | else |
11483 | abort (); | |
0dd2d296 ILT |
11484 | } |
11485 | ||
a8aed9dd ILT |
11486 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11487 | fixup_segment converted a non-PC relative reloc into a PC | |
11488 | relative reloc. In such a case, we need to convert the reloc | |
11489 | code. */ | |
11490 | code = fixp->fx_r_type; | |
11491 | if (fixp->fx_pcrel) | |
11492 | { | |
11493 | switch (code) | |
11494 | { | |
11495 | case BFD_RELOC_8: | |
11496 | code = BFD_RELOC_8_PCREL; | |
11497 | break; | |
11498 | case BFD_RELOC_16: | |
11499 | code = BFD_RELOC_16_PCREL; | |
11500 | break; | |
11501 | case BFD_RELOC_32: | |
11502 | code = BFD_RELOC_32_PCREL; | |
11503 | break; | |
bf39474f ILT |
11504 | case BFD_RELOC_64: |
11505 | code = BFD_RELOC_64_PCREL; | |
11506 | break; | |
a8aed9dd ILT |
11507 | case BFD_RELOC_8_PCREL: |
11508 | case BFD_RELOC_16_PCREL: | |
11509 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11510 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11511 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11512 | case BFD_RELOC_PCREL_HI16_S: |
11513 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11514 | break; |
11515 | default: | |
11516 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11517 | _("Cannot make %s relocation PC relative"), |
a8aed9dd ILT |
11518 | bfd_get_reloc_code_name (code)); |
11519 | } | |
11520 | } | |
11521 | ||
d9aba805 ILT |
11522 | /* To support a PC relative reloc when generating embedded PIC code |
11523 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11524 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11525 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11526 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11527 | && mips_pic != EMBEDDED_PIC) |
11528 | reloc->howto = NULL; | |
11529 | else | |
a8aed9dd | 11530 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11531 | |
52aa70b5 JW |
11532 | if (reloc->howto == NULL) |
11533 | { | |
11534 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11535 | _("Can not represent %s relocation in this object file format"), |
a8aed9dd | 11536 | bfd_get_reloc_code_name (code)); |
0dd2d296 | 11537 | retval[0] = NULL; |
52aa70b5 | 11538 | } |
3d3c5039 | 11539 | |
0dd2d296 | 11540 | return retval; |
3d3c5039 ILT |
11541 | } |
11542 | ||
cc5703cd ILT |
11543 | /* Relax a machine dependent frag. This returns the amount by which |
11544 | the current size of the frag should change. */ | |
11545 | ||
11546 | int | |
11547 | mips_relax_frag (fragp, stretch) | |
11548 | fragS *fragp; | |
11549 | long stretch; | |
11550 | { | |
11551 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11552 | return 0; | |
11553 | ||
11554 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11555 | { | |
11556 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11557 | return 0; | |
11558 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11559 | return 2; | |
11560 | } | |
11561 | else | |
11562 | { | |
11563 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11564 | return 0; | |
11565 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11566 | return -2; | |
11567 | } | |
11568 | ||
11569 | return 0; | |
11570 | } | |
11571 | ||
0dd2d296 ILT |
11572 | /* Convert a machine dependent frag. */ |
11573 | ||
11574 | void | |
11575 | md_convert_frag (abfd, asec, fragp) | |
11576 | bfd *abfd; | |
11577 | segT asec; | |
11578 | fragS *fragp; | |
3d3c5039 | 11579 | { |
0dd2d296 ILT |
11580 | int old, new; |
11581 | char *fixptr; | |
3d3c5039 | 11582 | |
cc5703cd ILT |
11583 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11584 | { | |
11585 | int type; | |
11586 | register const struct mips16_immed_operand *op; | |
11587 | boolean small, ext; | |
11588 | offsetT val; | |
11589 | bfd_byte *buf; | |
11590 | unsigned long insn; | |
11591 | boolean use_extend; | |
11592 | unsigned short extend; | |
11593 | ||
11594 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11595 | op = mips16_immed_operands; | |
11596 | while (op->type != type) | |
11597 | ++op; | |
11598 | ||
11599 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11600 | { | |
11601 | small = false; | |
11602 | ext = true; | |
11603 | } | |
11604 | else | |
11605 | { | |
11606 | small = true; | |
11607 | ext = false; | |
11608 | } | |
11609 | ||
b637f306 | 11610 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11611 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11612 | if (op->pcrel) |
11613 | { | |
11614 | addressT addr; | |
11615 | ||
a677feeb ILT |
11616 | addr = fragp->fr_address + fragp->fr_fix; |
11617 | ||
11618 | /* The rules for the base address of a PC relative reloc are | |
11619 | complicated; see mips16_extended_frag. */ | |
11620 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11621 | { |
11622 | addr += 2; | |
319305a7 ILT |
11623 | if (ext) |
11624 | addr += 2; | |
fbcfacb7 ILT |
11625 | /* Ignore the low bit in the target, since it will be |
11626 | set for a text label. */ | |
11627 | if ((val & 1) != 0) | |
11628 | --val; | |
11629 | } | |
a677feeb ILT |
11630 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11631 | addr -= 4; | |
11632 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11633 | addr -= 2; | |
11634 | ||
cc5703cd ILT |
11635 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11636 | val -= addr; | |
a677feeb ILT |
11637 | |
11638 | /* Make sure the section winds up with the alignment we have | |
11639 | assumed. */ | |
11640 | if (op->shift > 0) | |
11641 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11642 | } |
11643 | ||
035936da ILT |
11644 | if (ext |
11645 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11646 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11647 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11648 | _("extended instruction in delay slot")); |
035936da | 11649 | |
cc5703cd ILT |
11650 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
11651 | ||
b9129c6f ILT |
11652 | if (target_big_endian) |
11653 | insn = bfd_getb16 (buf); | |
11654 | else | |
11655 | insn = bfd_getl16 (buf); | |
cc5703cd | 11656 | |
31a2c6ff ILT |
11657 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
11658 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11659 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
11660 | |
11661 | if (use_extend) | |
11662 | { | |
11663 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11664 | fragp->fr_fix += 2; | |
11665 | buf += 2; | |
11666 | } | |
3d3c5039 | 11667 | |
cc5703cd ILT |
11668 | md_number_to_chars (buf, insn, 2); |
11669 | fragp->fr_fix += 2; | |
11670 | buf += 2; | |
11671 | } | |
11672 | else | |
11673 | { | |
11674 | if (fragp->fr_opcode == NULL) | |
11675 | return; | |
0dd2d296 | 11676 | |
cc5703cd ILT |
11677 | old = RELAX_OLD (fragp->fr_subtype); |
11678 | new = RELAX_NEW (fragp->fr_subtype); | |
11679 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 11680 | |
cc5703cd ILT |
11681 | if (new > 0) |
11682 | memcpy (fixptr - old, fixptr, new); | |
11683 | ||
11684 | fragp->fr_fix += new - old; | |
11685 | } | |
0dd2d296 | 11686 | } |
becfe05e | 11687 | |
fbcfacb7 ILT |
11688 | #ifdef OBJ_ELF |
11689 | ||
11690 | /* This function is called after the relocs have been generated. | |
11691 | We've been storing mips16 text labels as odd. Here we convert them | |
11692 | back to even for the convenience of the debugger. */ | |
11693 | ||
11694 | void | |
11695 | mips_frob_file_after_relocs () | |
11696 | { | |
11697 | asymbol **syms; | |
11698 | unsigned int count, i; | |
11699 | ||
11700 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11701 | return; | |
11702 | ||
11703 | syms = bfd_get_outsymbols (stdoutput); | |
11704 | count = bfd_get_symcount (stdoutput); | |
11705 | for (i = 0; i < count; i++, syms++) | |
11706 | { | |
11707 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11708 | && ((*syms)->value & 1) != 0) | |
11709 | { | |
11710 | (*syms)->value &= ~1; | |
11711 | /* If the symbol has an odd size, it was probably computed | |
11712 | incorrectly, so adjust that as well. */ | |
11713 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11714 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11715 | } | |
11716 | } | |
11717 | } | |
11718 | ||
11719 | #endif | |
11720 | ||
becfe05e ILT |
11721 | /* This function is called whenever a label is defined. It is used |
11722 | when handling branch delays; if a branch has a label, we assume we | |
11723 | can not move it. */ | |
11724 | ||
11725 | void | |
11726 | mips_define_label (sym) | |
11727 | symbolS *sym; | |
11728 | { | |
fbcfacb7 ILT |
11729 | struct insn_label_list *l; |
11730 | ||
11731 | if (free_insn_labels == NULL) | |
11732 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11733 | else | |
11734 | { | |
11735 | l = free_insn_labels; | |
11736 | free_insn_labels = l->next; | |
11737 | } | |
11738 | ||
11739 | l->label = sym; | |
11740 | l->next = insn_labels; | |
11741 | insn_labels = l; | |
becfe05e | 11742 | } |
3d3c5039 | 11743 | \f |
739708fa | 11744 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11745 | |
0dd2d296 | 11746 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11747 | |
11748 | void | |
11749 | mips_elf_final_processing () | |
11750 | { | |
87178180 ILT |
11751 | /* Write out the register information. */ |
11752 | if (! mips_64) | |
11753 | { | |
11754 | Elf32_RegInfo s; | |
11755 | ||
11756 | s.ri_gprmask = mips_gprmask; | |
11757 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11758 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11759 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11760 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11761 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11762 | ||
11763 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11764 | ((Elf32_External_RegInfo *) | |
11765 | mips_regmask_frag)); | |
11766 | } | |
11767 | else | |
11768 | { | |
11769 | Elf64_Internal_RegInfo s; | |
11770 | ||
11771 | s.ri_gprmask = mips_gprmask; | |
11772 | s.ri_pad = 0; | |
11773 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11774 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11775 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11776 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11777 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11778 | ||
11779 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11780 | ((Elf64_External_RegInfo *) | |
11781 | mips_regmask_frag)); | |
11782 | } | |
0dd2d296 ILT |
11783 | |
11784 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11785 | sort of BFD interface for this. */ | |
11786 | if (mips_any_noreorder) | |
11787 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11788 | if (mips_pic != NO_PIC) |
0dd2d296 | 11789 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11790 | } |
11791 | ||
739708fa | 11792 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11793 | \f |
3d3c5039 ILT |
11794 | /* These functions should really be defined by the object file format, |
11795 | since they are related to debugging information. However, this | |
11796 | code has to work for the a.out format, which does not define them, | |
11797 | so we provide simple versions here. These don't actually generate | |
11798 | any debugging information, but they do simple checking and someday | |
11799 | somebody may make them useful. */ | |
11800 | ||
670a50eb ILT |
11801 | typedef struct loc |
11802 | { | |
11803 | struct loc *loc_next; | |
11804 | unsigned long loc_fileno; | |
11805 | unsigned long loc_lineno; | |
11806 | unsigned long loc_offset; | |
11807 | unsigned short loc_delta; | |
11808 | unsigned short loc_count; | |
3d3c5039 | 11809 | #if 0 |
670a50eb | 11810 | fragS *loc_frag; |
3d3c5039 | 11811 | #endif |
670a50eb ILT |
11812 | } |
11813 | locS; | |
3d3c5039 | 11814 | |
670a50eb ILT |
11815 | typedef struct proc |
11816 | { | |
3d3c5039 ILT |
11817 | struct proc *proc_next; |
11818 | struct symbol *proc_isym; | |
11819 | struct symbol *proc_end; | |
11820 | unsigned long proc_reg_mask; | |
11821 | unsigned long proc_reg_offset; | |
11822 | unsigned long proc_fpreg_mask; | |
11823 | unsigned long proc_fpreg_offset; | |
11824 | unsigned long proc_frameoffset; | |
11825 | unsigned long proc_framereg; | |
11826 | unsigned long proc_pcreg; | |
11827 | locS *proc_iline; | |
11828 | struct file *proc_file; | |
11829 | int proc_index; | |
670a50eb ILT |
11830 | } |
11831 | procS; | |
3d3c5039 | 11832 | |
670a50eb ILT |
11833 | typedef struct file |
11834 | { | |
3d3c5039 ILT |
11835 | struct file *file_next; |
11836 | unsigned long file_fileno; | |
11837 | struct symbol *file_symbol; | |
11838 | struct symbol *file_end; | |
11839 | struct proc *file_proc; | |
11840 | int file_numprocs; | |
670a50eb ILT |
11841 | } |
11842 | fileS; | |
3d3c5039 ILT |
11843 | |
11844 | static struct obstack proc_frags; | |
11845 | static procS *proc_lastP; | |
11846 | static procS *proc_rootP; | |
11847 | static int numprocs; | |
11848 | ||
11849 | static void | |
11850 | md_obj_begin () | |
11851 | { | |
670a50eb | 11852 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
11853 | } |
11854 | ||
11855 | static void | |
11856 | md_obj_end () | |
11857 | { | |
11858 | /* check for premature end, nesting errors, etc */ | |
11859 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
48401fcf | 11860 | as_warn (_("missing `.end' at end of assembly")); |
3d3c5039 ILT |
11861 | } |
11862 | ||
3d3c5039 ILT |
11863 | static long |
11864 | get_number () | |
11865 | { | |
670a50eb ILT |
11866 | int negative = 0; |
11867 | long val = 0; | |
3d3c5039 | 11868 | |
670a50eb ILT |
11869 | if (*input_line_pointer == '-') |
11870 | { | |
11871 | ++input_line_pointer; | |
11872 | negative = 1; | |
3d3c5039 | 11873 | } |
670a50eb | 11874 | if (!isdigit (*input_line_pointer)) |
48401fcf | 11875 | as_bad (_("Expected simple number.")); |
670a50eb ILT |
11876 | if (input_line_pointer[0] == '0') |
11877 | { | |
11878 | if (input_line_pointer[1] == 'x') | |
11879 | { | |
11880 | input_line_pointer += 2; | |
11881 | while (isxdigit (*input_line_pointer)) | |
11882 | { | |
11883 | val <<= 4; | |
3a762a0b | 11884 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 11885 | } |
670a50eb ILT |
11886 | return negative ? -val : val; |
11887 | } | |
11888 | else | |
11889 | { | |
11890 | ++input_line_pointer; | |
11891 | while (isdigit (*input_line_pointer)) | |
11892 | { | |
11893 | val <<= 3; | |
11894 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 11895 | } |
670a50eb | 11896 | return negative ? -val : val; |
3d3c5039 ILT |
11897 | } |
11898 | } | |
670a50eb ILT |
11899 | if (!isdigit (*input_line_pointer)) |
11900 | { | |
48401fcf | 11901 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
670a50eb | 11902 | *input_line_pointer, *input_line_pointer); |
48401fcf | 11903 | as_warn (_("Invalid number")); |
670a50eb | 11904 | return -1; |
3d3c5039 | 11905 | } |
670a50eb ILT |
11906 | while (isdigit (*input_line_pointer)) |
11907 | { | |
11908 | val *= 10; | |
11909 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 11910 | } |
670a50eb | 11911 | return negative ? -val : val; |
3d3c5039 ILT |
11912 | } |
11913 | ||
11914 | /* The .file directive; just like the usual .file directive, but there | |
11915 | is an initial number which is the ECOFF file index. */ | |
11916 | ||
11917 | static void | |
11918 | s_file (x) | |
11919 | int x; | |
11920 | { | |
670a50eb | 11921 | int line; |
3d3c5039 | 11922 | |
670a50eb | 11923 | line = get_number (); |
9a7d824a | 11924 | s_app_file (0); |
3d3c5039 ILT |
11925 | } |
11926 | ||
11927 | ||
11928 | /* The .end directive. */ | |
11929 | ||
11930 | static void | |
11931 | s_mipsend (x) | |
11932 | int x; | |
11933 | { | |
670a50eb ILT |
11934 | symbolS *p; |
11935 | ||
11936 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11937 | { | |
11938 | p = get_symbol (); | |
11939 | demand_empty_rest_of_line (); | |
11940 | } | |
11941 | else | |
11942 | p = NULL; | |
11943 | if (now_seg != text_section) | |
48401fcf | 11944 | as_warn (_(".end not in text section")); |
670a50eb ILT |
11945 | if (!proc_lastP) |
11946 | { | |
48401fcf | 11947 | as_warn (_(".end and no .ent seen yet.")); |
670a50eb | 11948 | return; |
3d3c5039 ILT |
11949 | } |
11950 | ||
670a50eb ILT |
11951 | if (p != NULL) |
11952 | { | |
11953 | assert (S_GET_NAME (p)); | |
11954 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
48401fcf | 11955 | as_warn (_(".end symbol does not match .ent symbol.")); |
3d3c5039 ILT |
11956 | } |
11957 | ||
670a50eb | 11958 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
11959 | } |
11960 | ||
11961 | /* The .aent and .ent directives. */ | |
11962 | ||
11963 | static void | |
11964 | s_ent (aent) | |
11965 | int aent; | |
11966 | { | |
670a50eb ILT |
11967 | int number = 0; |
11968 | procS *procP; | |
11969 | symbolS *symbolP; | |
11970 | ||
11971 | symbolP = get_symbol (); | |
11972 | if (*input_line_pointer == ',') | |
11973 | input_line_pointer++; | |
dd3f1f76 | 11974 | SKIP_WHITESPACE (); |
670a50eb ILT |
11975 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
11976 | number = get_number (); | |
11977 | if (now_seg != text_section) | |
48401fcf | 11978 | as_warn (_(".ent or .aent not in text section.")); |
670a50eb ILT |
11979 | |
11980 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
48401fcf | 11981 | as_warn (_("missing `.end'")); |
670a50eb ILT |
11982 | |
11983 | if (!aent) | |
11984 | { | |
11985 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
11986 | procP->proc_isym = symbolP; | |
11987 | procP->proc_reg_mask = 0; | |
11988 | procP->proc_reg_offset = 0; | |
11989 | procP->proc_fpreg_mask = 0; | |
11990 | procP->proc_fpreg_offset = 0; | |
11991 | procP->proc_frameoffset = 0; | |
11992 | procP->proc_framereg = 0; | |
11993 | procP->proc_pcreg = 0; | |
11994 | procP->proc_end = NULL; | |
11995 | procP->proc_next = NULL; | |
11996 | if (proc_lastP) | |
11997 | proc_lastP->proc_next = procP; | |
11998 | else | |
11999 | proc_rootP = procP; | |
12000 | proc_lastP = procP; | |
12001 | numprocs++; | |
3d3c5039 | 12002 | } |
670a50eb | 12003 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
12004 | } |
12005 | ||
12006 | /* The .frame directive. */ | |
12007 | ||
88225433 | 12008 | #if 0 |
3d3c5039 ILT |
12009 | static void |
12010 | s_frame (x) | |
670a50eb | 12011 | int x; |
3d3c5039 | 12012 | { |
670a50eb ILT |
12013 | char str[100]; |
12014 | symbolS *symP; | |
12015 | int frame_reg; | |
12016 | int frame_off; | |
12017 | int pcreg; | |
12018 | ||
0dd2d296 | 12019 | frame_reg = tc_get_register (1); |
670a50eb ILT |
12020 | if (*input_line_pointer == ',') |
12021 | input_line_pointer++; | |
5ac34ac3 | 12022 | frame_off = get_absolute_expression (); |
670a50eb ILT |
12023 | if (*input_line_pointer == ',') |
12024 | input_line_pointer++; | |
0dd2d296 | 12025 | pcreg = tc_get_register (0); |
670a50eb ILT |
12026 | |
12027 | /* bob third eye */ | |
12028 | assert (proc_rootP); | |
12029 | proc_rootP->proc_framereg = frame_reg; | |
12030 | proc_rootP->proc_frameoffset = frame_off; | |
12031 | proc_rootP->proc_pcreg = pcreg; | |
12032 | /* bob macho .frame */ | |
12033 | ||
12034 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 12035 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
12036 | { |
12037 | if (!proc_lastP) | |
48401fcf | 12038 | as_warn (_("No .ent for .frame to use.")); |
670a50eb ILT |
12039 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); |
12040 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
12041 | S_SET_TYPE (symP, N_RMASK); | |
12042 | S_SET_OTHER (symP, 0); | |
12043 | S_SET_DESC (symP, 0); | |
12044 | symP->sy_forward = proc_lastP->proc_isym; | |
12045 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 12046 | } |
670a50eb | 12047 | demand_empty_rest_of_line (); |
3d3c5039 | 12048 | } |
88225433 | 12049 | #endif |
3d3c5039 ILT |
12050 | |
12051 | /* The .fmask and .mask directives. */ | |
12052 | ||
88225433 | 12053 | #if 0 |
3d3c5039 ILT |
12054 | static void |
12055 | s_mask (reg_type) | |
12056 | char reg_type; | |
12057 | { | |
670a50eb ILT |
12058 | char str[100], *strP; |
12059 | symbolS *symP; | |
12060 | int i; | |
12061 | unsigned int mask; | |
12062 | int off; | |
12063 | ||
12064 | mask = get_number (); | |
12065 | if (*input_line_pointer == ',') | |
12066 | input_line_pointer++; | |
12067 | off = get_absolute_expression (); | |
12068 | ||
12069 | /* bob only for coff */ | |
12070 | assert (proc_rootP); | |
12071 | if (reg_type == 'F') | |
12072 | { | |
12073 | proc_rootP->proc_fpreg_mask = mask; | |
12074 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 12075 | } |
670a50eb ILT |
12076 | else |
12077 | { | |
12078 | proc_rootP->proc_reg_mask = mask; | |
12079 | proc_rootP->proc_reg_offset = off; | |
12080 | } | |
12081 | ||
12082 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 12083 | |
670a50eb ILT |
12084 | /* We don't have to write out a mask stab if no saved regs. */ |
12085 | if (!(mask == 0)) | |
12086 | { | |
12087 | if (!proc_lastP) | |
48401fcf | 12088 | as_warn (_("No .ent for .mask to use.")); |
670a50eb ILT |
12089 | strP = str; |
12090 | for (i = 0; i < 32; i++) | |
12091 | { | |
12092 | if (mask % 2) | |
12093 | { | |
12094 | sprintf (strP, "%c%d,", reg_type, i); | |
12095 | strP += strlen (strP); | |
12096 | } | |
3d3c5039 | 12097 | mask /= 2; |
670a50eb ILT |
12098 | } |
12099 | sprintf (strP, ";%d,", off); | |
12100 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
12101 | S_SET_TYPE (symP, N_RMASK); | |
12102 | S_SET_OTHER (symP, 0); | |
12103 | S_SET_DESC (symP, 0); | |
12104 | symP->sy_forward = proc_lastP->proc_isym; | |
12105 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 12106 | } |
3d3c5039 | 12107 | } |
88225433 | 12108 | #endif |
3d3c5039 ILT |
12109 | |
12110 | /* The .loc directive. */ | |
12111 | ||
88225433 | 12112 | #if 0 |
3d3c5039 ILT |
12113 | static void |
12114 | s_loc (x) | |
12115 | int x; | |
12116 | { | |
670a50eb ILT |
12117 | symbolS *symbolP; |
12118 | int lineno; | |
12119 | int addroff; | |
3d3c5039 | 12120 | |
670a50eb | 12121 | assert (now_seg == text_section); |
3d3c5039 | 12122 | |
670a50eb | 12123 | lineno = get_number (); |
87e48495 | 12124 | addroff = frag_now_fix (); |
3d3c5039 | 12125 | |
670a50eb ILT |
12126 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
12127 | S_SET_TYPE (symbolP, N_SLINE); | |
12128 | S_SET_OTHER (symbolP, 0); | |
12129 | S_SET_DESC (symbolP, lineno); | |
12130 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 12131 | } |
88225433 | 12132 | #endif |