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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
145 | struct mips_set_options | |
146 | { | |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
151 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
152 | not, 1 if we are, and -1 if the value has not been initialized. | |
153 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
154 | -nomips16 command line options, and the default CPU. */ | |
155 | int mips16; | |
156 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
157 | reorder' and `.set noreorder'. */ | |
158 | int noreorder; | |
159 | /* Non-zero if we should not permit the $at ($1) register to be used | |
160 | in instructions. Changed by `.set at' and `.set noat'. */ | |
161 | int noat; | |
162 | /* Non-zero if we should warn when a macro instruction expands into | |
163 | more than one machine instruction. Changed by `.set nomacro' and | |
164 | `.set macro'. */ | |
165 | int warn_about_macros; | |
166 | /* Non-zero if we should not move instructions. Changed by `.set | |
167 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
168 | int nomove; | |
169 | /* Non-zero if we should not optimize branches by moving the target | |
170 | of the branch into the delay slot. Actually, we don't perform | |
171 | this optimization anyhow. Changed by `.set bopt' and `.set | |
172 | nobopt'. */ | |
173 | int nobopt; | |
174 | /* Non-zero if we should not autoextend mips16 instructions. | |
175 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
176 | int noautoextend; | |
177 | }; | |
178 | ||
179 | /* This is the struct we use to hold the current set of options. Note | |
180 | that we must set the isa and mips16 fields to -1 to indicate that | |
181 | they have not been initialized. */ | |
182 | ||
183 | static struct mips_set_options mips_opts = { -1, -1 }; | |
184 | ||
1aa6938e ILT |
185 | /* These variables are filled in with the masks of registers used. |
186 | The object format code reads them and puts them in the appropriate | |
187 | place. */ | |
188 | unsigned long mips_gprmask; | |
189 | unsigned long mips_cprmask[4]; | |
190 | ||
1051c97f ILT |
191 | /* MIPS ISA we are using for this output file. */ |
192 | static int file_mips_isa; | |
193 | ||
8c63448a | 194 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 195 | static int mips_cpu = -1; |
8c63448a | 196 | |
b2b8c24e ILT |
197 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
198 | static int mips_4650 = -1; | |
199 | ||
e532b44c ILT |
200 | /* Whether the 4010 instructions are permitted. */ |
201 | static int mips_4010 = -1; | |
202 | ||
c625fc23 JSC |
203 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
204 | static int mips_4100 = -1; | |
205 | ||
2d035a50 GRK |
206 | /* start-sanitize-vr4320 */ |
207 | /* Whether NEC vr4320 instructions are permitted. */ | |
208 | static int mips_4320 = -1; | |
209 | ||
210 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
211 | /* start-sanitize-vr5400 */ |
212 | /* Whether NEC vr5400 instructions are permitted. */ | |
213 | static int mips_5400 = -1; | |
214 | ||
215 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
216 | /* start-sanitize-r5900 */ |
217 | /* Whether Toshiba r5900 instructions are permitted. */ | |
218 | static int mips_5900 = -1; | |
276c2d7d | 219 | |
aa2e0460 | 220 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
221 | /* Whether Toshiba r3900 instructions are permitted. */ |
222 | static int mips_3900 = -1; | |
223 | ||
42444087 GRK |
224 | /* start-sanitize-tx49 */ |
225 | /* Whether Toshiba r4900 instructions are permitted. */ | |
226 | static int mips_4900 = -1; | |
227 | ||
228 | /* end-sanitize-tx49 */ | |
4e96260f JL |
229 | /* start-sanitize-tx19 */ |
230 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
231 | The tx19 related options and configuration bits are handled by | |
232 | the tx39 flags. */ | |
233 | /* end-sanitize-tx19 */ | |
234 | ||
5c6f5923 GRK |
235 | /* Whether the processor uses hardware interlocks to protect |
236 | reads from the HI and LO registers, and thus does not | |
237 | require nops to be inserted. */ | |
4ebda395 GRK |
238 | #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \ |
239 | /* start-sanitize-tx49 */ \ | |
42444087 | 240 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 241 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
242 | /* start-sanitize-vr4320 */ \ |
243 | || mips_cpu == 4320 \ | |
244 | /* end-sanitize-vr4320 */ \ | |
b3ed1af3 KR |
245 | /* start-sanitize-vr5400 */ \ |
246 | || mips_cpu == 5400 \ | |
247 | /* end-sanitize-vr5400 */ \ | |
4ebda395 | 248 | ) |
5c6f5923 | 249 | |
a3e8c5b7 ILT |
250 | /* Whether the processor uses hardware interlocks to protect reads |
251 | from the GPRs, and thus does not require nops to be inserted. */ | |
252 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
1c6f3441 ILT |
253 | /* start-sanitize-vr5400 */ |
254 | #undef gpr_interlocks | |
255 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
256 | /* end-sanitize-vr5400 */ | |
257 | ||
e532b44c | 258 | |
5c6f5923 | 259 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 260 | (co-processor) interlocks. */ |
efec4a28 | 261 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
262 | #define cop_interlocks (mips_cpu == 4300 \ |
263 | /* start-sanitize-vr4320 */ \ | |
264 | || mips_cpu == 4320 \ | |
265 | /* end-sanitize-vr4320 */ \ | |
266 | /* start-sanitize-vr5400 */ \ | |
267 | || mips_cpu == 5400 \ | |
268 | /* end-sanitize-vr5400 */ \ | |
269 | ) | |
344a8d61 | 270 | |
d9aba805 ILT |
271 | /* MIPS PIC level. */ |
272 | ||
273 | enum mips_pic_level | |
274 | { | |
275 | /* Do not generate PIC code. */ | |
276 | NO_PIC, | |
277 | ||
278 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
279 | not sure what it is supposed to do. */ | |
280 | IRIX4_PIC, | |
281 | ||
282 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
283 | SVR4_PIC, | |
284 | ||
285 | /* Generate PIC code without using a global offset table: the data | |
286 | segment has a maximum size of 64K, all data references are off | |
287 | the $gp register, and all text references are PC relative. This | |
288 | is used on some embedded systems. */ | |
289 | EMBEDDED_PIC | |
290 | }; | |
291 | ||
292 | static enum mips_pic_level mips_pic; | |
9226253a | 293 | |
fb251650 ILT |
294 | /* 1 if we should generate 32 bit offsets from the GP register in |
295 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
296 | static int mips_big_got; | |
297 | ||
8ea7f4e8 ILT |
298 | /* 1 if trap instructions should used for overflow rather than break |
299 | instructions. */ | |
300 | static int mips_trap; | |
301 | ||
3c83da8a | 302 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 303 | |
0dd2d296 | 304 | static int mips_any_noreorder; |
3d3c5039 | 305 | |
670a50eb ILT |
306 | /* The size of the small data section. */ |
307 | static int g_switch_value = 8; | |
42562568 ILT |
308 | /* Whether the -G option was used. */ |
309 | static int g_switch_seen = 0; | |
670a50eb | 310 | |
3d3c5039 ILT |
311 | #define N_RMASK 0xc4 |
312 | #define N_VFP 0xd4 | |
313 | ||
d8a1c247 KR |
314 | /* If we can determine in advance that GP optimization won't be |
315 | possible, we can skip the relaxation stuff that tries to produce | |
316 | GP-relative references. This makes delay slot optimization work | |
317 | better. | |
318 | ||
319 | This function can only provide a guess, but it seems to work for | |
320 | gcc output. If it guesses wrong, the only loss should be in | |
321 | efficiency; it shouldn't introduce any bugs. | |
322 | ||
323 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
324 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 325 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 326 | |
3d3c5039 ILT |
327 | /* handle of the OPCODE hash table */ |
328 | static struct hash_control *op_hash = NULL; | |
329 | ||
cc5703cd ILT |
330 | /* The opcode hash table we use for the mips16. */ |
331 | static struct hash_control *mips16_op_hash = NULL; | |
332 | ||
3d3c5039 ILT |
333 | /* This array holds the chars that always start a comment. If the |
334 | pre-processor is disabled, these aren't very useful */ | |
335 | const char comment_chars[] = "#"; | |
336 | ||
337 | /* This array holds the chars that only start a comment at the beginning of | |
338 | a line. If the line seems to have the form '# 123 filename' | |
339 | .line and .file directives will appear in the pre-processed output */ | |
340 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
341 | first line of the input file. This is because the compiler outputs | |
342 | #NO_APP at the beginning of its output. */ | |
343 | /* Also note that C style comments are always supported. */ | |
344 | const char line_comment_chars[] = "#"; | |
345 | ||
346 | /* This array holds machine specific line separator characters. */ | |
347 | const char line_separator_chars[] = ""; | |
348 | ||
349 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
350 | const char EXP_CHARS[] = "eE"; | |
351 | ||
352 | /* Chars that mean this number is a floating point constant */ | |
353 | /* As in 0f12.456 */ | |
354 | /* or 0d1.2345e12 */ | |
355 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
356 | ||
357 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
358 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
359 | but nothing is ideal around here. | |
360 | */ | |
361 | ||
670a50eb | 362 | static char *insn_error; |
3d3c5039 | 363 | |
3d3c5039 | 364 | static int auto_align = 1; |
becfe05e | 365 | |
9226253a ILT |
366 | /* When outputting SVR4 PIC code, the assembler needs to know the |
367 | offset in the stack frame from which to restore the $gp register. | |
368 | This is set by the .cprestore pseudo-op, and saved in this | |
369 | variable. */ | |
0dd2d296 ILT |
370 | static offsetT mips_cprestore_offset = -1; |
371 | ||
372 | /* This is the register which holds the stack frame, as set by the | |
373 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
374 | static int mips_frame_reg = SP; | |
9226253a | 375 | |
becfe05e ILT |
376 | /* To output NOP instructions correctly, we need to keep information |
377 | about the previous two instructions. */ | |
378 | ||
0aa07269 ILT |
379 | /* Whether we are optimizing. The default value of 2 means to remove |
380 | unneeded NOPs and swap branch instructions when possible. A value | |
381 | of 1 means to not swap branches. A value of 0 means to always | |
382 | insert NOPs. */ | |
383 | static int mips_optimize = 2; | |
4e95866e | 384 | |
22ba90ce ILT |
385 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
386 | equivalent to seeing no -g option at all. */ | |
387 | static int mips_debug = 0; | |
388 | ||
becfe05e ILT |
389 | /* The previous instruction. */ |
390 | static struct mips_cl_insn prev_insn; | |
391 | ||
392 | /* The instruction before prev_insn. */ | |
393 | static struct mips_cl_insn prev_prev_insn; | |
394 | ||
395 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
396 | point the insn_mo field at this dummy integer. */ | |
397 | static const struct mips_opcode dummy_opcode = { 0 }; | |
398 | ||
399 | /* Non-zero if prev_insn is valid. */ | |
400 | static int prev_insn_valid; | |
401 | ||
402 | /* The frag for the previous instruction. */ | |
403 | static struct frag *prev_insn_frag; | |
404 | ||
405 | /* The offset into prev_insn_frag for the previous instruction. */ | |
406 | static long prev_insn_where; | |
407 | ||
a677feeb ILT |
408 | /* The reloc type for the previous instruction, if any. */ |
409 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
410 | ||
becfe05e ILT |
411 | /* The reloc for the previous instruction, if any. */ |
412 | static fixS *prev_insn_fixp; | |
413 | ||
414 | /* Non-zero if the previous instruction was in a delay slot. */ | |
415 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
416 | |
417 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
418 | static int prev_insn_unreordered; | |
419 | ||
cc5703cd ILT |
420 | /* Non-zero if the previous instruction uses an extend opcode (if |
421 | mips16). */ | |
422 | static int prev_insn_extended; | |
423 | ||
4e95866e ILT |
424 | /* Non-zero if the previous previous instruction was in a .set |
425 | noreorder. */ | |
426 | static int prev_prev_insn_unreordered; | |
867a58b3 | 427 | |
4a1cb507 ILT |
428 | /* If this is set, it points to a frag holding nop instructions which |
429 | were inserted before the start of a noreorder section. If those | |
430 | nops turn out to be unnecessary, the size of the frag can be | |
431 | decreased. */ | |
432 | static fragS *prev_nop_frag; | |
433 | ||
434 | /* The number of nop instructions we created in prev_nop_frag. */ | |
435 | static int prev_nop_frag_holds; | |
436 | ||
437 | /* The number of nop instructions that we know we need in | |
438 | prev_nop_frag. */ | |
439 | static int prev_nop_frag_required; | |
440 | ||
441 | /* The number of instructions we've seen since prev_nop_frag. */ | |
442 | static int prev_nop_frag_since; | |
443 | ||
867a58b3 ILT |
444 | /* For ECOFF and ELF, relocations against symbols are done in two |
445 | parts, with a HI relocation and a LO relocation. Each relocation | |
446 | has only 16 bits of space to store an addend. This means that in | |
447 | order for the linker to handle carries correctly, it must be able | |
448 | to locate both the HI and the LO relocation. This means that the | |
449 | relocations must appear in order in the relocation table. | |
450 | ||
451 | In order to implement this, we keep track of each unmatched HI | |
452 | relocation. We then sort them so that they immediately precede the | |
453 | corresponding LO relocation. */ | |
454 | ||
455 | struct mips_hi_fixup | |
456 | { | |
457 | /* Next HI fixup. */ | |
458 | struct mips_hi_fixup *next; | |
459 | /* This fixup. */ | |
460 | fixS *fixp; | |
461 | /* The section this fixup is in. */ | |
462 | segT seg; | |
463 | }; | |
464 | ||
465 | /* The list of unmatched HI relocs. */ | |
466 | ||
467 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
468 | |
469 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
470 | ||
471 | #define X ILLEGAL_REG | |
472 | static const int mips32_to_16_reg_map[] = | |
473 | { | |
474 | X, X, 2, 3, 4, 5, 6, 7, | |
475 | X, X, X, X, X, X, X, X, | |
476 | 0, 1, X, X, X, X, X, X, | |
477 | X, X, X, X, X, X, X, X | |
478 | }; | |
479 | #undef X | |
480 | ||
481 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
482 | ||
483 | static const int mips16_to_32_reg_map[] = | |
484 | { | |
485 | 16, 17, 2, 3, 4, 5, 6, 7 | |
486 | }; | |
3d3c5039 | 487 | \f |
0dd2d296 ILT |
488 | /* Since the MIPS does not have multiple forms of PC relative |
489 | instructions, we do not have to do relaxing as is done on other | |
490 | platforms. However, we do have to handle GP relative addressing | |
491 | correctly, which turns out to be a similar problem. | |
492 | ||
493 | Every macro that refers to a symbol can occur in (at least) two | |
494 | forms, one with GP relative addressing and one without. For | |
495 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 496 | a macro instruction like this: |
0dd2d296 ILT |
497 | lw $4,i |
498 | If i can be addressed off the GP register (this is true if it is in | |
499 | the .sbss or .sdata section, or if it is known to be smaller than | |
500 | the -G argument) this will generate the following instruction: | |
501 | lw $4,i($gp) | |
502 | This instruction will use a GPREL reloc. If i can not be addressed | |
503 | off the GP register, the following instruction sequence will be used: | |
504 | lui $at,i | |
505 | lw $4,i($at) | |
506 | In this case the first instruction will have a HI16 reloc, and the | |
507 | second reloc will have a LO16 reloc. Both relocs will be against | |
508 | the symbol i. | |
509 | ||
510 | The issue here is that we may not know whether i is GP addressable | |
511 | until after we see the instruction that uses it. Therefore, we | |
512 | want to be able to choose the final instruction sequence only at | |
513 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 514 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
515 | end of assembly. |
516 | ||
517 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
518 | addressing in quite the same way, but the issue still arises as |
519 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
520 | |
521 | We handle these issues by actually generating both possible | |
522 | instruction sequences. The longer one is put in a frag_var with | |
523 | type rs_machine_dependent. We encode what to do with the frag in | |
524 | the subtype field. We encode (1) the number of existing bytes to | |
525 | replace, (2) the number of new bytes to use, (3) the offset from | |
526 | the start of the existing bytes to the first reloc we must generate | |
527 | (that is, the offset is applied from the start of the existing | |
528 | bytes after they are replaced by the new bytes, if any), (4) the | |
529 | offset from the start of the existing bytes to the second reloc, | |
530 | (5) whether a third reloc is needed (the third reloc is always four | |
531 | bytes after the second reloc), and (6) whether to warn if this | |
532 | variant is used (this is sometimes needed if .set nomacro or .set | |
533 | noat is in effect). All these numbers are reasonably small. | |
534 | ||
535 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
536 | ensure that delay slots are handled correctly. Fortunately, there |
537 | are a limited number of cases. When the second instruction | |
538 | sequence is generated, append_insn is directed to maintain the | |
539 | existing delay slot information, so it continues to apply to any | |
540 | code after the second instruction sequence. This means that the | |
541 | second instruction sequence must not impose any requirements not | |
542 | required by the first instruction sequence. | |
0dd2d296 ILT |
543 | |
544 | These variant frags are then handled in functions called by the | |
545 | machine independent code. md_estimate_size_before_relax returns | |
546 | the final size of the frag. md_convert_frag sets up the final form | |
547 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
548 | one if needed. */ | |
549 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
550 | ((relax_substateT) \ | |
cc5703cd | 551 | (((old) << 23) \ |
0dd2d296 ILT |
552 | | ((new) << 16) \ |
553 | | (((reloc1) + 64) << 9) \ | |
554 | | (((reloc2) + 64) << 2) \ | |
555 | | ((reloc3) ? (1 << 1) : 0) \ | |
556 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
557 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
558 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
559 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
560 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
561 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
562 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
563 | |
564 | /* For mips16 code, we use an entirely different form of relaxation. | |
565 | mips16 supports two versions of most instructions which take | |
566 | immediate values: a small one which takes some small value, and a | |
567 | larger one which takes a 16 bit value. Since branches also follow | |
568 | this pattern, relaxing these values is required. | |
569 | ||
570 | We can assemble both mips16 and normal MIPS code in a single | |
571 | object. Therefore, we need to support this type of relaxation at | |
572 | the same time that we support the relaxation described above. We | |
573 | use the high bit of the subtype field to distinguish these cases. | |
574 | ||
a677feeb ILT |
575 | The information we store for this type of relaxation is the |
576 | argument code found in the opcode file for this relocation, whether | |
577 | the user explicitly requested a small or extended form, and whether | |
578 | the relocation is in a jump or jal delay slot. That tells us the | |
579 | size of the value, and how it should be stored. We also store | |
580 | whether the fragment is considered to be extended or not. We also | |
581 | store whether this is known to be a branch to a different section, | |
582 | whether we have tried to relax this frag yet, and whether we have | |
583 | ever extended a PC relative fragment because of a shift count. */ | |
584 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
585 | (0x80000000 \ | |
586 | | ((type) & 0xff) \ | |
587 | | ((small) ? 0x100 : 0) \ | |
588 | | ((ext) ? 0x200 : 0) \ | |
589 | | ((dslot) ? 0x400 : 0) \ | |
590 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
591 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
592 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
593 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
594 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
595 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
596 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
597 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
598 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
599 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
600 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
601 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
602 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 603 | \f |
3d3c5039 ILT |
604 | /* Prototypes for static functions. */ |
605 | ||
606 | #ifdef __STDC__ | |
607 | #define internalError() \ | |
608 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
609 | #else | |
610 | #define internalError() as_fatal ("MIPS internal Error"); | |
611 | #endif | |
612 | ||
cc5703cd ILT |
613 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
614 | ||
becfe05e | 615 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 616 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 617 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 618 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
619 | static void append_insn PARAMS ((char *place, |
620 | struct mips_cl_insn * ip, | |
670a50eb | 621 | expressionS * p, |
867a58b3 ILT |
622 | bfd_reloc_code_real_type r, |
623 | boolean)); | |
4a1cb507 | 624 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 625 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 626 | #ifdef USE_STDARG |
0dd2d296 | 627 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
628 | const char *name, const char *fmt, |
629 | ...)); | |
c625fc23 JSC |
630 | #else |
631 | static void macro_build (); | |
632 | #endif | |
cc5703cd ILT |
633 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
634 | const char *, const char *, | |
635 | va_list)); | |
0dd2d296 ILT |
636 | static void macro_build_lui PARAMS ((char *place, int *counter, |
637 | expressionS * ep, int regnum)); | |
6e8dda9c | 638 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 639 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 640 | expressionS *)); |
d8a1c247 | 641 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 642 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 643 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 644 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
645 | #ifdef LOSING_COMPILER |
646 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
647 | #endif | |
670a50eb | 648 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 649 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
650 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
651 | boolean, boolean, unsigned long *, | |
652 | boolean *, unsigned short *)); | |
670a50eb ILT |
653 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
654 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 655 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 656 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
657 | static void s_align PARAMS ((int)); |
658 | static void s_change_sec PARAMS ((int)); | |
659 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 660 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 661 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
662 | static void s_option PARAMS ((int)); |
663 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
664 | static void s_abicalls PARAMS ((int)); |
665 | static void s_cpload PARAMS ((int)); | |
666 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
667 | static void s_gpword PARAMS ((int)); |
668 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 669 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
670 | static void md_obj_begin PARAMS ((void)); |
671 | static void md_obj_end PARAMS ((void)); | |
672 | static long get_number PARAMS ((void)); | |
673 | static void s_ent PARAMS ((int)); | |
674 | static void s_mipsend PARAMS ((int)); | |
675 | static void s_file PARAMS ((int)); | |
3c83da8a | 676 | static void s_mips_stab PARAMS ((int)); |
cc5703cd | 677 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 KR |
678 | |
679 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); | |
3d3c5039 ILT |
680 | \f |
681 | /* Pseudo-op table. | |
682 | ||
683 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
684 | should be defined here, but are currently unsupported: .alias, | |
685 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
686 | ||
687 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
688 | specific to the type of debugging information being generated, and | |
689 | should be defined by the object format: .aent, .begin, .bend, | |
690 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
691 | .vreg. | |
692 | ||
693 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
694 | not MIPS CPU specific, but are also not specific to the object file | |
695 | format. This file is probably the best place to define them, but | |
696 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
697 | .struct, .weakext. */ | |
698 | ||
739708fa | 699 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 700 | { |
670a50eb ILT |
701 | /* MIPS specific pseudo-ops. */ |
702 | {"option", s_option, 0}, | |
703 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
704 | {"rdata", s_change_sec, 'r'}, |
705 | {"sdata", s_change_sec, 's'}, | |
706 | {"livereg", s_ignore, 0}, | |
739708fa KR |
707 | {"abicalls", s_abicalls, 0}, |
708 | {"cpload", s_cpload, 0}, | |
709 | {"cprestore", s_cprestore, 0}, | |
710 | {"gpword", s_gpword, 0}, | |
711 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 712 | {"insn", s_insn, 0}, |
3d3c5039 | 713 | |
670a50eb | 714 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 715 | chips. */ |
739708fa | 716 | {"asciiz", stringer, 1}, |
670a50eb ILT |
717 | {"bss", s_change_sec, 'b'}, |
718 | {"err", s_err, 0}, | |
719 | {"half", s_cons, 1}, | |
52aa70b5 | 720 | {"dword", s_cons, 3}, |
3d3c5039 | 721 | |
670a50eb | 722 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 723 | here for one reason or another. */ |
670a50eb ILT |
724 | {"align", s_align, 0}, |
725 | {"byte", s_cons, 0}, | |
726 | {"data", s_change_sec, 'd'}, | |
becfe05e | 727 | {"double", s_float_cons, 'd'}, |
becfe05e | 728 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
729 | {"globl", s_mips_globl, 0}, |
730 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
731 | {"hword", s_cons, 1}, |
732 | {"int", s_cons, 2}, | |
733 | {"long", s_cons, 2}, | |
734 | {"octa", s_cons, 4}, | |
735 | {"quad", s_cons, 3}, | |
736 | {"short", s_cons, 1}, | |
737 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 738 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
739 | {"text", s_change_sec, 't'}, |
740 | {"word", s_cons, 2}, | |
739708fa KR |
741 | { 0 }, |
742 | }; | |
3d3c5039 | 743 | |
739708fa | 744 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 745 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 746 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 747 | {"aent", s_ent, 1}, |
9226253a | 748 | {"bgnb", s_ignore, 0}, |
670a50eb | 749 | {"end", s_mipsend, 0}, |
9226253a | 750 | {"endb", s_ignore, 0}, |
670a50eb ILT |
751 | {"ent", s_ent, 0}, |
752 | {"file", s_file, 0}, | |
753 | {"fmask", s_ignore, 'F'}, | |
754 | {"frame", s_ignore, 0}, | |
755 | {"loc", s_ignore, 0}, | |
756 | {"mask", s_ignore, 'R'}, | |
757 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
758 | { 0 }, |
759 | }; | |
61420a20 | 760 | |
739708fa KR |
761 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
762 | ||
763 | void | |
764 | mips_pop_insert () | |
765 | { | |
766 | pop_insert (mips_pseudo_table); | |
767 | if (! ECOFF_DEBUGGING) | |
768 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 769 | } |
3d3c5039 | 770 | \f |
fbcfacb7 ILT |
771 | /* Symbols labelling the current insn. */ |
772 | ||
773 | struct insn_label_list | |
774 | { | |
775 | struct insn_label_list *next; | |
776 | symbolS *label; | |
777 | }; | |
778 | ||
779 | static struct insn_label_list *insn_labels; | |
780 | static struct insn_label_list *free_insn_labels; | |
781 | ||
782 | static void mips_clear_insn_labels PARAMS ((void)); | |
783 | ||
784 | static inline void | |
785 | mips_clear_insn_labels () | |
786 | { | |
787 | register struct insn_label_list **pl; | |
788 | ||
789 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
790 | ; | |
791 | *pl = insn_labels; | |
792 | insn_labels = NULL; | |
793 | } | |
794 | \f | |
3d3c5039 ILT |
795 | static char *expr_end; |
796 | ||
867a58b3 ILT |
797 | /* Expressions which appear in instructions. These are set by |
798 | mips_ip. */ | |
799 | ||
3d3c5039 ILT |
800 | static expressionS imm_expr; |
801 | static expressionS offset_expr; | |
867a58b3 ILT |
802 | |
803 | /* Relocs associated with imm_expr and offset_expr. */ | |
804 | ||
3d3c5039 ILT |
805 | static bfd_reloc_code_real_type imm_reloc; |
806 | static bfd_reloc_code_real_type offset_reloc; | |
807 | ||
867a58b3 ILT |
808 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
809 | ||
810 | static boolean imm_unmatched_hi; | |
811 | ||
8728fa92 ILT |
812 | /* These are set by mips16_ip if an explicit extension is used. */ |
813 | ||
814 | static boolean mips16_small, mips16_ext; | |
815 | ||
3d3c5039 ILT |
816 | /* |
817 | * This function is called once, at assembler startup time. It should | |
818 | * set up all the tables, etc. that the MD part of the assembler will need. | |
819 | */ | |
820 | void | |
670a50eb | 821 | md_begin () |
3d3c5039 | 822 | { |
0dd2d296 | 823 | boolean ok = false; |
604633ae | 824 | register const char *retval = NULL; |
670a50eb | 825 | register unsigned int i = 0; |
1724c79e GRK |
826 | const char *cpu; |
827 | char *a = NULL; | |
aa2e0460 | 828 | int broken = 0; |
3d3c5039 | 829 | |
1724c79e GRK |
830 | cpu = TARGET_CPU; |
831 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 832 | { |
1724c79e GRK |
833 | a = xmalloc (sizeof TARGET_CPU); |
834 | strcpy (a, TARGET_CPU); | |
835 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
836 | cpu = a; | |
837 | } | |
8c63448a | 838 | |
1724c79e GRK |
839 | if (mips_cpu < 0) |
840 | { | |
841 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
842 | just the generic 'mips', in which case set mips_cpu based | |
843 | on the given ISA, if any. */ | |
8c63448a ILT |
844 | |
845 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
846 | { |
847 | if (mips_opts.isa < 0) | |
848 | mips_cpu = 3000; | |
849 | ||
850 | else if (mips_opts.isa == 2) | |
851 | mips_cpu = 6000; | |
852 | ||
853 | else if (mips_opts.isa == 3) | |
854 | mips_cpu = 4000; | |
855 | ||
856 | else if (mips_opts.isa == 4) | |
857 | mips_cpu = 8000; | |
858 | ||
859 | else | |
860 | mips_cpu = 3000; | |
861 | } | |
862 | ||
5c6f5923 | 863 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 864 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
865 | /* start-sanitize-tx19 */ |
866 | || strcmp (cpu, "r1900") == 0 | |
867 | || strcmp (cpu, "mipstx19") == 0 | |
868 | /* end-sanitize-tx19 */ | |
869 | ) | |
1724c79e GRK |
870 | mips_cpu = 3900; |
871 | ||
8c63448a ILT |
872 | else if (strcmp (cpu, "r6000") == 0 |
873 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
874 | mips_cpu = 6000; |
875 | ||
8c63448a ILT |
876 | else if (strcmp (cpu, "mips64") == 0 |
877 | || strcmp (cpu, "r4000") == 0 | |
878 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
879 | mips_cpu = 4000; |
880 | ||
8c63448a | 881 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
882 | mips_cpu = 4400; |
883 | ||
8c63448a ILT |
884 | else if (strcmp (cpu, "mips64orion") == 0 |
885 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
886 | mips_cpu = 4600; |
887 | ||
b2b8c24e | 888 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
889 | mips_cpu = 4650; |
890 | ||
c625fc23 | 891 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
892 | mips_cpu = 4300; |
893 | ||
2d035a50 GRK |
894 | /* start-sanitize-vr4320 */ |
895 | else if (strcmp (cpu, "r4320") == 0 | |
896 | || strcmp (cpu, "mips64vr4320") == 0) | |
897 | mips_cpu = 4320; | |
898 | ||
899 | /* end-sanitize-vr4320 */ | |
e599ab16 | 900 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
901 | mips_cpu = 4100; |
902 | ||
e532b44c | 903 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
904 | mips_cpu = 4010; |
905 | ||
4ebda395 GRK |
906 | /* start-sanitize-tx49 */ |
907 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 908 | mips_cpu = 4900; |
4ebda395 | 909 | /* end-sanitize-tx49 */ |
1724c79e | 910 | |
517078c1 ILT |
911 | else if (strcmp (cpu, "r5000") == 0 |
912 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
913 | mips_cpu = 5000; |
914 | ||
aa2e0460 KR |
915 | /* start-sanitize-vr5400 */ |
916 | else if (strcmp (cpu, "r5400") == 0 | |
b3ed1af3 KR |
917 | || strcmp (cpu, "mips64vr5400") == 0) |
918 | mips_cpu = 5400; | |
aa2e0460 | 919 | /* end-sanitize-vr5400 */ |
1724c79e | 920 | |
276c2d7d GRK |
921 | /* start-sanitize-r5900 */ |
922 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
923 | || strcmp (cpu, "mips64r5900") == 0) |
924 | mips_cpu = 5900; | |
276c2d7d | 925 | /* end-sanitize-r5900 */ |
1724c79e | 926 | |
d8a1c247 KR |
927 | else if (strcmp (cpu, "r8000") == 0 |
928 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
929 | mips_cpu = 8000; |
930 | ||
d8a1c247 | 931 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
932 | mips_cpu = 10000; |
933 | ||
cc5703cd | 934 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
935 | mips_cpu = 0; /* FIXME */ |
936 | ||
8358c818 | 937 | else |
1724c79e GRK |
938 | mips_cpu = 3000; |
939 | } | |
8c63448a | 940 | |
1724c79e GRK |
941 | if (mips_opts.isa == -1) |
942 | { | |
943 | if (mips_cpu == 3000 | |
944 | || mips_cpu == 3900) | |
945 | mips_opts.isa = 1; | |
946 | ||
947 | else if (mips_cpu == 6000 | |
948 | || mips_cpu == 4010) | |
949 | mips_opts.isa = 2; | |
950 | ||
951 | else if (mips_cpu == 4000 | |
952 | || mips_cpu == 4100 | |
953 | || mips_cpu == 4400 | |
954 | || mips_cpu == 4300 | |
2d035a50 GRK |
955 | /* start-sanitize-vr4320 */ |
956 | || mips_cpu == 4320 | |
957 | /* end-sanitize-4320 */ | |
1724c79e GRK |
958 | || mips_cpu == 4600 |
959 | /* start-sanitize-tx49 */ | |
960 | || mips_cpu == 4900 | |
961 | /* end-sanitize-tx49 */ | |
962 | /* start-sanitize-r5900 */ | |
963 | || mips_cpu == 5900 | |
964 | /* end-sanitize-r5900 */ | |
965 | || mips_cpu == 4650) | |
966 | mips_opts.isa = 3; | |
967 | ||
968 | else if (mips_cpu == 5000 | |
969 | /* start-sanitize-vr5400 */ | |
970 | || mips_cpu == 5400 | |
971 | /* end-sanitize-vr5400 */ | |
972 | || mips_cpu == 8000 | |
973 | || mips_cpu == 10000) | |
974 | mips_opts.isa = 4; | |
975 | ||
976 | else | |
977 | mips_opts.isa = 1; | |
8358c818 ILT |
978 | } |
979 | ||
3c83da8a | 980 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
981 | { |
982 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 983 | mips_opts.mips16 = 1; |
cc5703cd | 984 | else |
3c83da8a | 985 | mips_opts.mips16 = 0; |
cc5703cd ILT |
986 | } |
987 | ||
b2b8c24e | 988 | if (mips_4650 < 0) |
1724c79e | 989 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 990 | |
e532b44c | 991 | if (mips_4010 < 0) |
1724c79e | 992 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 993 | |
c625fc23 | 994 | if (mips_4100 < 0) |
1724c79e | 995 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 996 | |
2d035a50 GRK |
997 | /* start-sanitize-vr4320 */ |
998 | if (mips_4320 < 0) | |
999 | mips_4320 = (mips_cpu == 4320); | |
1000 | ||
1001 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
1002 | /* start-sanitize-vr5400 */ |
1003 | if (mips_5400 < 0) | |
1724c79e | 1004 | mips_5400 = (mips_cpu == 5400); |
aa2e0460 | 1005 | /* end-sanitize-vr5400 */ |
1724c79e | 1006 | |
276c2d7d GRK |
1007 | /* start-sanitize-r5900 */ |
1008 | if (mips_5900 < 0) | |
1724c79e | 1009 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 1010 | /* end-sanitize-r5900 */ |
1724c79e | 1011 | |
5c6f5923 | 1012 | if (mips_3900 < 0) |
1724c79e GRK |
1013 | mips_3900 = (mips_cpu == 3900); |
1014 | ||
42444087 GRK |
1015 | /* start-sanitize-tx49 */ |
1016 | if (mips_4900 < 0) | |
1017 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 1018 | |
42444087 | 1019 | /* end-sanitize-tx49 */ |
1724c79e GRK |
1020 | |
1021 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1022 | if necessary. */ | |
1023 | cpu = NULL; | |
1024 | if (a != NULL) | |
1025 | { | |
1026 | free (a); | |
1027 | a = NULL; | |
1028 | } | |
1029 | ||
3c83da8a | 1030 | if (mips_opts.isa < 2 && mips_trap) |
8ea7f4e8 ILT |
1031 | as_bad ("trap exception not supported at ISA 1"); |
1032 | ||
9a1f3160 | 1033 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1034 | { |
9a1f3160 JL |
1035 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1036 | } | |
1037 | else | |
1038 | { | |
1039 | switch (mips_opts.isa) | |
1040 | { | |
1041 | case 1: | |
1042 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1043 | break; | |
1044 | case 2: | |
1045 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1046 | break; | |
1047 | case 3: | |
1048 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1049 | break; | |
1050 | case 4: | |
1051 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1052 | break; | |
1053 | } | |
97f99d11 | 1054 | } |
9a1f3160 | 1055 | |
97f99d11 ILT |
1056 | if (! ok) |
1057 | as_warn ("Could not set architecture and machine"); | |
1058 | ||
3c83da8a | 1059 | file_mips_isa = mips_opts.isa; |
1051c97f | 1060 | |
13fe1379 ILT |
1061 | op_hash = hash_new (); |
1062 | ||
670a50eb ILT |
1063 | for (i = 0; i < NUMOPCODES;) |
1064 | { | |
1065 | const char *name = mips_opcodes[i].name; | |
1066 | ||
604633ae | 1067 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1068 | if (retval != NULL) |
670a50eb ILT |
1069 | { |
1070 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
1071 | mips_opcodes[i].name, retval); | |
aa2e0460 | 1072 | /* Probably a memory allocation problem? Give up now. */ |
670a50eb ILT |
1073 | as_fatal ("Broken assembler. No assembly attempted."); |
1074 | } | |
1075 | do | |
1076 | { | |
aa2e0460 | 1077 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1078 | { |
aa2e0460 KR |
1079 | if (!validate_mips_insn (&mips_opcodes[i])) |
1080 | broken = 1; | |
3d3c5039 | 1081 | } |
670a50eb ILT |
1082 | ++i; |
1083 | } | |
1084 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1085 | } |
1086 | ||
cc5703cd ILT |
1087 | mips16_op_hash = hash_new (); |
1088 | ||
1089 | i = 0; | |
1090 | while (i < bfd_mips16_num_opcodes) | |
1091 | { | |
1092 | const char *name = mips16_opcodes[i].name; | |
1093 | ||
1094 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1095 | if (retval != NULL) | |
aa2e0460 | 1096 | as_fatal ("internal: can't hash `%s': %s", |
cc5703cd ILT |
1097 | mips16_opcodes[i].name, retval); |
1098 | do | |
1099 | { | |
1100 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1101 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1102 | != mips16_opcodes[i].match)) | |
aa2e0460 KR |
1103 | { |
1104 | fprintf (stderr, "internal error: bad mips16 opcode: %s %s\n", | |
1105 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1106 | broken = 1; | |
1107 | } | |
cc5703cd ILT |
1108 | ++i; |
1109 | } | |
1110 | while (i < bfd_mips16_num_opcodes | |
1111 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1112 | } | |
1113 | ||
aa2e0460 KR |
1114 | if (broken) |
1115 | as_fatal ("Broken assembler. No assembly attempted."); | |
1116 | ||
ebf28372 ILT |
1117 | /* We add all the general register names to the symbol table. This |
1118 | helps us detect invalid uses of them. */ | |
1119 | for (i = 0; i < 32; i++) | |
1120 | { | |
1121 | char buf[5]; | |
1122 | ||
1123 | sprintf (buf, "$%d", i); | |
1124 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1125 | &zero_address_frag)); | |
1126 | } | |
1127 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1128 | &zero_address_frag)); | |
1129 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1130 | &zero_address_frag)); | |
1131 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1132 | &zero_address_frag)); | |
1133 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1134 | &zero_address_frag)); | |
1135 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1136 | &zero_address_frag)); | |
1137 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1138 | &zero_address_frag)); | |
1139 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1140 | &zero_address_frag)); | |
1141 | ||
4a1cb507 | 1142 | mips_no_prev_insn (false); |
becfe05e | 1143 | |
1aa6938e ILT |
1144 | mips_gprmask = 0; |
1145 | mips_cprmask[0] = 0; | |
1146 | mips_cprmask[1] = 0; | |
1147 | mips_cprmask[2] = 0; | |
1148 | mips_cprmask[3] = 0; | |
1149 | ||
8358c818 | 1150 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1151 | record_alignment (text_section, 2); |
8358c818 | 1152 | |
1dc1e798 KR |
1153 | if (USE_GLOBAL_POINTER_OPT) |
1154 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1155 | |
1dc1e798 KR |
1156 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1157 | { | |
08e17202 ILT |
1158 | /* On a native system, sections must be aligned to 16 byte |
1159 | boundaries. When configured for an embedded ELF target, we | |
1160 | don't bother. */ | |
1161 | if (strcmp (TARGET_OS, "elf") != 0) | |
1162 | { | |
1163 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1164 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1165 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1166 | } | |
1dc1e798 KR |
1167 | |
1168 | /* Create a .reginfo section for register masks and a .mdebug | |
1169 | section for debugging information. */ | |
1170 | { | |
1171 | segT seg; | |
1172 | subsegT subseg; | |
b3a64736 | 1173 | flagword flags; |
1dc1e798 KR |
1174 | segT sec; |
1175 | ||
1176 | seg = now_seg; | |
1177 | subseg = now_subseg; | |
1dc1e798 | 1178 | |
b3a64736 ILT |
1179 | /* The ABI says this section should be loaded so that the |
1180 | running program can access it. However, we don't load it | |
1181 | if we are configured for an embedded target */ | |
1182 | flags = SEC_READONLY | SEC_DATA; | |
1183 | if (strcmp (TARGET_OS, "elf") != 0) | |
1184 | flags |= SEC_ALLOC | SEC_LOAD; | |
1185 | ||
87178180 ILT |
1186 | if (! mips_64) |
1187 | { | |
1188 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1189 | |
b3a64736 ILT |
1190 | |
1191 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1192 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1193 | ||
f2a663d3 | 1194 | #ifdef OBJ_ELF |
87178180 | 1195 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1196 | #endif |
87178180 ILT |
1197 | } |
1198 | else | |
1199 | { | |
1200 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1201 | .reginfo section. */ | |
1202 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1203 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1204 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1205 | ||
1206 | #ifdef OBJ_ELF | |
1207 | /* Set up the option header. */ | |
1208 | { | |
1209 | Elf_Internal_Options opthdr; | |
1210 | char *f; | |
1211 | ||
1212 | opthdr.kind = ODK_REGINFO; | |
1213 | opthdr.size = (sizeof (Elf_External_Options) | |
1214 | + sizeof (Elf64_External_RegInfo)); | |
1215 | opthdr.section = 0; | |
1216 | opthdr.info = 0; | |
1217 | f = frag_more (sizeof (Elf_External_Options)); | |
1218 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1219 | (Elf_External_Options *) f); | |
1220 | ||
1221 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1222 | } | |
1223 | #endif | |
1224 | } | |
f2a663d3 | 1225 | |
739708fa KR |
1226 | if (ECOFF_DEBUGGING) |
1227 | { | |
1228 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1229 | (void) bfd_set_section_flags (stdoutput, sec, | |
1230 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1231 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1232 | } | |
0dd2d296 | 1233 | |
1dc1e798 KR |
1234 | subseg_set (seg, subseg); |
1235 | } | |
1236 | } | |
f2a663d3 | 1237 | |
739708fa KR |
1238 | if (! ECOFF_DEBUGGING) |
1239 | md_obj_begin (); | |
3d3c5039 ILT |
1240 | } |
1241 | ||
1242 | void | |
13fe1379 | 1243 | md_mips_end () |
3d3c5039 | 1244 | { |
739708fa KR |
1245 | if (! ECOFF_DEBUGGING) |
1246 | md_obj_end (); | |
3d3c5039 ILT |
1247 | } |
1248 | ||
1249 | void | |
670a50eb ILT |
1250 | md_assemble (str) |
1251 | char *str; | |
3d3c5039 | 1252 | { |
670a50eb | 1253 | struct mips_cl_insn insn; |
3d3c5039 | 1254 | |
5ac34ac3 | 1255 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1256 | imm_reloc = BFD_RELOC_UNUSED; |
1257 | imm_unmatched_hi = false; | |
5ac34ac3 | 1258 | offset_expr.X_op = O_absent; |
867a58b3 | 1259 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1260 | |
3c83da8a | 1261 | if (mips_opts.mips16) |
cc5703cd ILT |
1262 | mips16_ip (str, &insn); |
1263 | else | |
efec4a28 | 1264 | { |
9218cee0 | 1265 | mips_ip (str, &insn); |
efec4a28 DP |
1266 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1267 | str, insn.insn_opcode)); | |
1268 | } | |
cc5703cd | 1269 | |
670a50eb ILT |
1270 | if (insn_error) |
1271 | { | |
1272 | as_bad ("%s `%s'", insn_error, str); | |
1273 | return; | |
1274 | } | |
cc5703cd | 1275 | |
670a50eb ILT |
1276 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1277 | { | |
3c83da8a | 1278 | if (mips_opts.mips16) |
cc5703cd ILT |
1279 | mips16_macro (&insn); |
1280 | else | |
1281 | macro (&insn); | |
3d3c5039 | 1282 | } |
670a50eb ILT |
1283 | else |
1284 | { | |
5ac34ac3 | 1285 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1286 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1287 | imm_unmatched_hi); | |
5ac34ac3 | 1288 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1289 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1290 | else |
867a58b3 | 1291 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1292 | } |
1293 | } | |
1294 | ||
cc5703cd ILT |
1295 | /* See whether instruction IP reads register REG. CLASS is the type |
1296 | of register. */ | |
becfe05e ILT |
1297 | |
1298 | static int | |
cc5703cd | 1299 | insn_uses_reg (ip, reg, class) |
becfe05e | 1300 | struct mips_cl_insn *ip; |
604633ae | 1301 | unsigned int reg; |
cc5703cd | 1302 | enum mips_regclass class; |
becfe05e | 1303 | { |
cc5703cd ILT |
1304 | if (class == MIPS16_REG) |
1305 | { | |
3c83da8a | 1306 | assert (mips_opts.mips16); |
cc5703cd ILT |
1307 | reg = mips16_to_32_reg_map[reg]; |
1308 | class = MIPS_GR_REG; | |
1309 | } | |
1310 | ||
becfe05e | 1311 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1312 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1313 | return 0; |
1314 | ||
cc5703cd | 1315 | if (class == MIPS_FP_REG) |
becfe05e | 1316 | { |
3c83da8a | 1317 | assert (! mips_opts.mips16); |
becfe05e ILT |
1318 | /* If we are called with either $f0 or $f1, we must check $f0. |
1319 | This is not optimal, because it will introduce an unnecessary | |
1320 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1321 | need to distinguish reading both $f0 and $f1 or just one of | |
1322 | them. Note that we don't have to check the other way, | |
1323 | because there is no instruction that sets both $f0 and $f1 | |
1324 | and requires a delay. */ | |
1325 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1326 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1327 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1328 | return 1; |
1329 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1330 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1331 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1332 | return 1; |
1333 | } | |
3c83da8a | 1334 | else if (! mips_opts.mips16) |
becfe05e ILT |
1335 | { |
1336 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1337 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1338 | return 1; | |
1339 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1340 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1341 | return 1; | |
1342 | } | |
cc5703cd ILT |
1343 | else |
1344 | { | |
1345 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1346 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1347 | & MIPS16OP_MASK_RX)] | |
1348 | == reg)) | |
cc5703cd ILT |
1349 | return 1; |
1350 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1351 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1352 | & MIPS16OP_MASK_RY)] | |
1353 | == reg)) | |
cc5703cd ILT |
1354 | return 1; |
1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1356 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1357 | & MIPS16OP_MASK_MOVE32Z)] | |
1358 | == reg)) | |
cc5703cd ILT |
1359 | return 1; |
1360 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1361 | return 1; | |
1362 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1363 | return 1; | |
1364 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1365 | return 1; | |
1366 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1367 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1368 | & MIPS16OP_MASK_REGR32) == reg) | |
1369 | return 1; | |
1370 | } | |
becfe05e ILT |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | ||
fb251650 ILT |
1375 | /* This function returns true if modifying a register requires a |
1376 | delay. */ | |
1377 | ||
1378 | static int | |
1379 | reg_needs_delay (reg) | |
1380 | int reg; | |
1381 | { | |
1382 | unsigned long prev_pinfo; | |
1383 | ||
1384 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1385 | if (! mips_opts.noreorder |
1386 | && mips_opts.isa < 4 | |
fb251650 | 1387 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1388 | || (! gpr_interlocks |
fb251650 ILT |
1389 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1390 | { | |
1391 | /* A load from a coprocessor or from memory. All load | |
1392 | delays delay the use of general register rt for one | |
1393 | instruction on the r3000. The r6000 and r4000 use | |
1394 | interlocks. */ | |
efec4a28 | 1395 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1396 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1397 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1398 | return 1; | |
1399 | } | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
3c83da8a JW |
1404 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1405 | handle them specially, such as generating jalx instructions when | |
1406 | needed. We also make them odd for the duration of the assembly, in | |
1407 | order to generate the right sort of code. We will make them even | |
1408 | in the adjust_symtab routine, while leaving them marked. This is | |
1409 | convenient for the debugger and the disassembler. The linker knows | |
1410 | to make them odd again. */ | |
1411 | ||
1412 | static void | |
1413 | mips16_mark_labels () | |
1414 | { | |
1415 | if (mips_opts.mips16) | |
1416 | { | |
1417 | struct insn_label_list *l; | |
1418 | ||
1419 | for (l = insn_labels; l != NULL; l = l->next) | |
1420 | { | |
68952421 | 1421 | #ifdef OBJ_ELF |
3c83da8a JW |
1422 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1423 | S_SET_OTHER (l->label, STO_MIPS16); | |
1424 | #endif | |
1425 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1426 | ++l->label->sy_value.X_add_number; | |
1427 | } | |
1428 | } | |
1429 | } | |
1430 | ||
0dd2d296 ILT |
1431 | /* Output an instruction. PLACE is where to put the instruction; if |
1432 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1433 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1434 | used with RELOC_TYPE. */ | |
3d3c5039 | 1435 | |
3d3c5039 | 1436 | static void |
867a58b3 | 1437 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1438 | char *place; |
670a50eb ILT |
1439 | struct mips_cl_insn *ip; |
1440 | expressionS *address_expr; | |
1441 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1442 | boolean unmatched_hi; |
3d3c5039 | 1443 | { |
1aa6938e | 1444 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1445 | char *f; |
becfe05e ILT |
1446 | fixS *fixp; |
1447 | int nops = 0; | |
3d3c5039 | 1448 | |
3c83da8a JW |
1449 | /* Mark instruction labels in mips16 mode. */ |
1450 | if (mips_opts.mips16) | |
1451 | mips16_mark_labels (); | |
fbcfacb7 | 1452 | |
1aa6938e ILT |
1453 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1454 | pinfo = ip->insn_mo->pinfo; | |
1455 | ||
3c83da8a | 1456 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1457 | { |
4a1cb507 ILT |
1458 | int prev_prev_nop; |
1459 | ||
becfe05e | 1460 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1461 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1462 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1463 | (1) a load from memory delay |
1464 | (2) a load from a coprocessor delay | |
1465 | (3) an unconditional branch delay | |
1466 | (4) a conditional branch delay | |
1467 | (5) a move to coprocessor register delay | |
1468 | (6) a load coprocessor register from memory delay | |
1469 | (7) a coprocessor condition code delay | |
1470 | (8) a HI/LO special register delay | |
becfe05e ILT |
1471 | |
1472 | There are a lot of optimizations we could do that we don't. | |
1473 | In particular, we do not, in general, reorder instructions. | |
1474 | If you use gcc with optimization, it will reorder | |
1475 | instructions and generally do much more optimization then we | |
1476 | do here; repeating all that work in the assembler would only | |
1477 | benefit hand written assembly code, and does not seem worth | |
1478 | it. */ | |
1479 | ||
1480 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1481 | #define emit_nop() \ |
3c83da8a | 1482 | (mips_opts.mips16 \ |
cc5703cd ILT |
1483 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1484 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1485 | |
1486 | /* The previous insn might require a delay slot, depending upon | |
1487 | the contents of the current insn. */ | |
3c83da8a JW |
1488 | if (! mips_opts.mips16 |
1489 | && mips_opts.isa < 4 | |
5af96dce ILT |
1490 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1491 | && ! cop_interlocks) | |
5c6f5923 | 1492 | || (! gpr_interlocks |
d8a1c247 | 1493 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1494 | { |
1495 | /* A load from a coprocessor or from memory. All load | |
1496 | delays delay the use of general register rt for one | |
1497 | instruction on the r3000. The r6000 and r4000 use | |
1498 | interlocks. */ | |
efec4a28 | 1499 | /* Itbl support may require additional care here. */ |
1aa6938e | 1500 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1501 | if (mips_optimize == 0 |
1502 | || insn_uses_reg (ip, | |
1503 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1504 | & OP_MASK_RT), | |
cc5703cd | 1505 | MIPS_GR_REG)) |
becfe05e ILT |
1506 | ++nops; |
1507 | } | |
3c83da8a JW |
1508 | else if (! mips_opts.mips16 |
1509 | && mips_opts.isa < 4 | |
5af96dce ILT |
1510 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1511 | && ! cop_interlocks) | |
3c83da8a | 1512 | || (mips_opts.isa < 2 |
d8a1c247 | 1513 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1514 | { |
1515 | /* A generic coprocessor delay. The previous instruction | |
1516 | modified a coprocessor general or control register. If | |
1517 | it modified a control register, we need to avoid any | |
1518 | coprocessor instruction (this is probably not always | |
1519 | required, but it sometimes is). If it modified a general | |
1520 | register, we avoid using that register. | |
1521 | ||
8358c818 ILT |
1522 | On the r6000 and r4000 loading a coprocessor register |
1523 | from memory is interlocked, and does not require a delay. | |
1524 | ||
becfe05e ILT |
1525 | This case is not handled very well. There is no special |
1526 | knowledge of CP0 handling, and the coprocessors other | |
1527 | than the floating point unit are not distinguished at | |
1528 | all. */ | |
efec4a28 DP |
1529 | /* Itbl support may require additional care here. FIXME! |
1530 | Need to modify this to include knowledge about | |
1531 | user specified delays! */ | |
1aa6938e | 1532 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1533 | { |
0aa07269 ILT |
1534 | if (mips_optimize == 0 |
1535 | || insn_uses_reg (ip, | |
8358c818 ILT |
1536 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1537 | & OP_MASK_FT), | |
cc5703cd | 1538 | MIPS_FP_REG)) |
becfe05e ILT |
1539 | ++nops; |
1540 | } | |
1aa6938e | 1541 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1542 | { |
0aa07269 ILT |
1543 | if (mips_optimize == 0 |
1544 | || insn_uses_reg (ip, | |
8358c818 ILT |
1545 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1546 | & OP_MASK_FS), | |
cc5703cd | 1547 | MIPS_FP_REG)) |
becfe05e ILT |
1548 | ++nops; |
1549 | } | |
1550 | else | |
1551 | { | |
1552 | /* We don't know exactly what the previous instruction | |
1553 | does. If the current instruction uses a coprocessor | |
1554 | register, we must insert a NOP. If previous | |
1555 | instruction may set the condition codes, and the | |
1556 | current instruction uses them, we must insert two | |
1557 | NOPS. */ | |
efec4a28 | 1558 | /* Itbl support may require additional care here. */ |
0aa07269 | 1559 | if (mips_optimize == 0 |
1aa6938e ILT |
1560 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1561 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1562 | nops += 2; |
1aa6938e | 1563 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1564 | ++nops; |
1565 | } | |
1566 | } | |
3c83da8a JW |
1567 | else if (! mips_opts.mips16 |
1568 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1569 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1570 | && ! cop_interlocks) | |
becfe05e ILT |
1571 | { |
1572 | /* The previous instruction sets the coprocessor condition | |
1573 | codes, but does not require a general coprocessor delay | |
1574 | (this means it is a floating point comparison | |
1575 | instruction). If this instruction uses the condition | |
1576 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1577 | /* Itbl support may require additional care here. */ |
0aa07269 | 1578 | if (mips_optimize == 0 |
1aa6938e | 1579 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1580 | ++nops; |
1581 | } | |
1aa6938e | 1582 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1583 | { |
1584 | /* The previous instruction reads the LO register; if the | |
1585 | current instruction writes to the LO register, we must | |
517078c1 | 1586 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1587 | if (! hilo_interlocks |
b2b8c24e ILT |
1588 | && (mips_optimize == 0 |
1589 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1590 | nops += 2; |
1591 | } | |
1592 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1593 | { | |
1594 | /* The previous instruction reads the HI register; if the | |
1595 | current instruction writes to the HI register, we must | |
517078c1 | 1596 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1597 | if (! hilo_interlocks |
b2b8c24e ILT |
1598 | && (mips_optimize == 0 |
1599 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1600 | nops += 2; |
1601 | } | |
1602 | ||
4a1cb507 ILT |
1603 | /* If the previous instruction was in a noreorder section, then |
1604 | we don't want to insert the nop after all. */ | |
efec4a28 | 1605 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1606 | if (prev_insn_unreordered) |
1607 | nops = 0; | |
1608 | ||
becfe05e ILT |
1609 | /* There are two cases which require two intervening |
1610 | instructions: 1) setting the condition codes using a move to | |
1611 | coprocessor instruction which requires a general coprocessor | |
1612 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1613 | or LO register and then writing to it (except on processors |
1614 | which have interlocks). If we are not already emitting a NOP | |
1615 | instruction, we must check for these cases compared to the | |
1616 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1617 | if ((! mips_opts.mips16 |
1618 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1619 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1620 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1621 | && (pinfo & INSN_READ_COND_CODE) | |
1622 | && ! cop_interlocks) | |
1623 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1624 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1625 | && ! hilo_interlocks) |
4a1cb507 ILT |
1626 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1627 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1628 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1629 | prev_prev_nop = 1; |
1630 | else | |
1631 | prev_prev_nop = 0; | |
1632 | ||
1633 | if (prev_prev_insn_unreordered) | |
1634 | prev_prev_nop = 0; | |
1635 | ||
1636 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1637 | ++nops; |
1638 | ||
0dd2d296 ILT |
1639 | /* If we are being given a nop instruction, don't bother with |
1640 | one of the nops we would otherwise output. This will only | |
1641 | happen when a nop instruction is used with mips_optimize set | |
1642 | to 0. */ | |
4a1cb507 | 1643 | if (nops > 0 |
3c83da8a JW |
1644 | && ! mips_opts.noreorder |
1645 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1646 | --nops; |
1647 | ||
becfe05e | 1648 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1649 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1650 | { |
5af96dce ILT |
1651 | fragS *old_frag; |
1652 | unsigned long old_frag_offset; | |
8c63448a | 1653 | int i; |
fbcfacb7 | 1654 | struct insn_label_list *l; |
8c63448a | 1655 | |
5af96dce ILT |
1656 | old_frag = frag_now; |
1657 | old_frag_offset = frag_now_fix (); | |
1658 | ||
8c63448a | 1659 | for (i = 0; i < nops; i++) |
becfe05e | 1660 | emit_nop (); |
5af96dce | 1661 | |
af255ca0 | 1662 | if (listing) |
546f5536 ILT |
1663 | { |
1664 | listing_prev_line (); | |
1665 | /* We may be at the start of a variant frag. In case we | |
1666 | are, make sure there is enough space for the frag | |
1667 | after the frags created by listing_prev_line. The | |
1668 | argument to frag_grow here must be at least as large | |
1669 | as the argument to all other calls to frag_grow in | |
1670 | this file. We don't have to worry about being in the | |
1671 | middle of a variant frag, because the variants insert | |
1672 | all needed nop instructions themselves. */ | |
1673 | frag_grow (40); | |
1674 | } | |
5af96dce | 1675 | |
fbcfacb7 | 1676 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1677 | { |
fbcfacb7 ILT |
1678 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1679 | l->label->sy_frag = frag_now; | |
1680 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1681 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1682 | if (mips_opts.mips16) |
fbcfacb7 | 1683 | ++l->label->sy_value.X_add_number; |
becfe05e | 1684 | } |
5af96dce ILT |
1685 | |
1686 | #ifndef NO_ECOFF_DEBUGGING | |
1687 | if (ECOFF_DEBUGGING) | |
1688 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1689 | #endif | |
becfe05e | 1690 | } |
4a1cb507 ILT |
1691 | else if (prev_nop_frag != NULL) |
1692 | { | |
1693 | /* We have a frag holding nops we may be able to remove. If | |
1694 | we don't need any nops, we can decrease the size of | |
1695 | prev_nop_frag by the size of one instruction. If we do | |
1696 | need some nops, we count them in prev_nops_required. */ | |
1697 | if (prev_nop_frag_since == 0) | |
1698 | { | |
1699 | if (nops == 0) | |
1700 | { | |
3c83da8a | 1701 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1702 | --prev_nop_frag_holds; |
1703 | } | |
1704 | else | |
1705 | prev_nop_frag_required += nops; | |
1706 | } | |
1707 | else | |
1708 | { | |
1709 | if (prev_prev_nop == 0) | |
1710 | { | |
3c83da8a | 1711 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1712 | --prev_nop_frag_holds; |
1713 | } | |
1714 | else | |
1715 | ++prev_nop_frag_required; | |
1716 | } | |
1717 | ||
1718 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1719 | prev_nop_frag = NULL; | |
1720 | ||
1721 | ++prev_nop_frag_since; | |
1722 | ||
1723 | /* Sanity check: by the time we reach the second instruction | |
1724 | after prev_nop_frag, we should have used up all the nops | |
1725 | one way or another. */ | |
1726 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1727 | } | |
becfe05e | 1728 | } |
4a1cb507 | 1729 | |
cc5703cd ILT |
1730 | if (reloc_type > BFD_RELOC_UNUSED) |
1731 | { | |
1732 | /* We need to set up a variant frag. */ | |
3c83da8a | 1733 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1734 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1735 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1736 | mips16_small, mips16_ext, |
1737 | (prev_pinfo | |
1738 | & INSN_UNCOND_BRANCH_DELAY), | |
1739 | (prev_insn_reloc_type | |
1740 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1741 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1742 | (char *) NULL); |
1743 | } | |
1744 | else if (place != NULL) | |
0dd2d296 | 1745 | f = place; |
3c83da8a JW |
1746 | else if (mips_opts.mips16 |
1747 | && ! ip->use_extend | |
1748 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1749 | { |
1750 | /* Make sure there is enough room to swap this instruction with | |
1751 | a following jump instruction. */ | |
1752 | frag_grow (6); | |
1753 | f = frag_more (2); | |
1754 | } | |
cc5703cd | 1755 | else |
035936da | 1756 | { |
3c83da8a JW |
1757 | if (mips_opts.mips16 |
1758 | && mips_opts.noreorder | |
035936da ILT |
1759 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
1760 | as_warn ("extended instruction in delay slot"); | |
1761 | ||
1762 | f = frag_more (4); | |
1763 | } | |
1764 | ||
becfe05e | 1765 | fixp = NULL; |
cc5703cd | 1766 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1767 | { |
5ac34ac3 | 1768 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1769 | { |
1770 | switch (reloc_type) | |
1771 | { | |
3d3c5039 | 1772 | case BFD_RELOC_32: |
670a50eb ILT |
1773 | ip->insn_opcode |= address_expr->X_add_number; |
1774 | break; | |
3d3c5039 ILT |
1775 | |
1776 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1777 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1778 | break; | |
3d3c5039 ILT |
1779 | |
1780 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1781 | if ((address_expr->X_add_number & 3) != 0) |
1782 | as_bad ("jump to misaligned address (0x%lx)", | |
1783 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1784 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1785 | break; | |
1786 | ||
cc5703cd | 1787 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1788 | if ((address_expr->X_add_number & 3) != 0) |
1789 | as_bad ("jump to misaligned address (0x%lx)", | |
1790 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1791 | ip->insn_opcode |= |
1792 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1793 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1794 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1795 | break; | |
1796 | ||
3d3c5039 | 1797 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1798 | goto need_reloc; |
3d3c5039 ILT |
1799 | |
1800 | default: | |
670a50eb | 1801 | internalError (); |
3d3c5039 | 1802 | } |
670a50eb ILT |
1803 | } |
1804 | else | |
1805 | { | |
3d3c5039 | 1806 | need_reloc: |
0dd2d296 ILT |
1807 | /* Don't generate a reloc if we are writing into a variant |
1808 | frag. */ | |
1809 | if (place == NULL) | |
867a58b3 ILT |
1810 | { |
1811 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1812 | address_expr, | |
1813 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1814 | reloc_type); | |
1815 | if (unmatched_hi) | |
1816 | { | |
1817 | struct mips_hi_fixup *hi_fixup; | |
1818 | ||
1819 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1820 | hi_fixup = ((struct mips_hi_fixup *) | |
1821 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1822 | hi_fixup->fixp = fixp; | |
1823 | hi_fixup->seg = now_seg; | |
1824 | hi_fixup->next = mips_hi_fixup_list; | |
1825 | mips_hi_fixup_list = hi_fixup; | |
1826 | } | |
1827 | } | |
3d3c5039 ILT |
1828 | } |
1829 | } | |
becfe05e | 1830 | |
3c83da8a | 1831 | if (! mips_opts.mips16) |
cc5703cd | 1832 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1833 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1834 | { | |
1835 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1836 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1837 | } | |
cc5703cd ILT |
1838 | else |
1839 | { | |
1840 | if (ip->use_extend) | |
1841 | { | |
1842 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1843 | f += 2; | |
1844 | } | |
1845 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1846 | } | |
670a50eb | 1847 | |
1aa6938e | 1848 | /* Update the register mask information. */ |
3c83da8a | 1849 | if (! mips_opts.mips16) |
cc5703cd ILT |
1850 | { |
1851 | if (pinfo & INSN_WRITE_GPR_D) | |
1852 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1853 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1854 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1855 | if (pinfo & INSN_READ_GPR_S) | |
1856 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1857 | if (pinfo & INSN_WRITE_GPR_31) | |
1858 | mips_gprmask |= 1 << 31; | |
1859 | if (pinfo & INSN_WRITE_FPR_D) | |
1860 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1861 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1862 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1863 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1864 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1865 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1866 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1867 | if (pinfo & INSN_COP) | |
1868 | { | |
efec4a28 DP |
1869 | /* We don't keep enough information to sort these cases out. |
1870 | The itbl support does keep this information however, although | |
1871 | we currently don't support itbl fprmats as part of the cop | |
1872 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1873 | } |
1874 | /* Never set the bit for $0, which is always zero. */ | |
1875 | mips_gprmask &=~ 1 << 0; | |
1876 | } | |
1877 | else | |
1aa6938e | 1878 | { |
cc5703cd ILT |
1879 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1880 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1881 | & MIPS16OP_MASK_RX); | |
1882 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1883 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1884 | & MIPS16OP_MASK_RY); | |
1885 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1886 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1887 | & MIPS16OP_MASK_RZ); | |
1888 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1889 | mips_gprmask |= 1 << TREG; | |
1890 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1891 | mips_gprmask |= 1 << SP; | |
1892 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1893 | mips_gprmask |= 1 << RA; | |
1894 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1895 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1896 | if (pinfo & MIPS16_INSN_READ_Z) | |
1897 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1898 | & MIPS16OP_MASK_MOVE32Z); | |
1899 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1900 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1901 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1902 | } |
1aa6938e | 1903 | |
3c83da8a | 1904 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1905 | { |
becfe05e ILT |
1906 | /* Filling the branch delay slot is more complex. We try to |
1907 | switch the branch with the previous instruction, which we can | |
1908 | do if the previous instruction does not set up a condition | |
1909 | that the branch tests and if the branch is not itself the | |
1910 | target of any branch. */ | |
1aa6938e ILT |
1911 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1912 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1913 | { |
0aa07269 | 1914 | if (mips_optimize < 2 |
19ed8960 ILT |
1915 | /* If we have seen .set volatile or .set nomove, don't |
1916 | optimize. */ | |
3c83da8a | 1917 | || mips_opts.nomove != 0 |
4e95866e ILT |
1918 | /* If we had to emit any NOP instructions, then we |
1919 | already know we can not swap. */ | |
1920 | || nops != 0 | |
becfe05e ILT |
1921 | /* If we don't even know the previous insn, we can not |
1922 | swap. */ | |
1923 | || ! prev_insn_valid | |
1924 | /* If the previous insn is already in a branch delay | |
1925 | slot, then we can not swap. */ | |
1926 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1927 | /* If the previous previous insn was in a .set |
1928 | noreorder, we can't swap. Actually, the MIPS | |
1929 | assembler will swap in this situation. However, gcc | |
1930 | configured -with-gnu-as will generate code like | |
1931 | .set noreorder | |
1932 | lw $4,XXX | |
1933 | .set reorder | |
1934 | INSN | |
1935 | bne $4,$0,foo | |
1936 | in which we can not swap the bne and INSN. If gcc is | |
1937 | not configured -with-gnu-as, it does not output the | |
1938 | .set pseudo-ops. We don't have to check | |
1939 | prev_insn_unreordered, because prev_insn_valid will | |
1940 | be 0 in that case. We don't want to use | |
1941 | prev_prev_insn_valid, because we do want to be able | |
1942 | to swap at the start of a function. */ | |
1943 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1944 | /* If the branch is itself the target of a branch, we |
1945 | can not swap. We cheat on this; all we check for is | |
1946 | whether there is a label on this instruction. If | |
1947 | there are any branches to anything other than a | |
1948 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1949 | || insn_labels != NULL |
777ad64d | 1950 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1951 | can not do the swap. This does not apply to the |
1952 | mips16, which uses variant frags for different | |
1953 | purposes. */ | |
3c83da8a | 1954 | || (! mips_opts.mips16 |
cc5703cd | 1955 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1956 | /* If the branch reads the condition codes, we don't |
1957 | even try to swap, because in the sequence | |
1958 | ctc1 $X,$31 | |
1959 | INSN | |
1960 | INSN | |
1961 | bc1t LABEL | |
1962 | we can not swap, and I don't feel like handling that | |
1963 | case. */ | |
3c83da8a JW |
1964 | || (! mips_opts.mips16 |
1965 | && mips_opts.isa < 4 | |
d8a1c247 | 1966 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1967 | /* We can not swap with an instruction that requires a |
1968 | delay slot, becase the target of the branch might | |
1969 | interfere with that instruction. */ | |
3c83da8a JW |
1970 | || (! mips_opts.mips16 |
1971 | && mips_opts.isa < 4 | |
d8a1c247 | 1972 | && (prev_pinfo |
efec4a28 | 1973 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1974 | & (INSN_LOAD_COPROC_DELAY |
1975 | | INSN_COPROC_MOVE_DELAY | |
1976 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1977 | || (! hilo_interlocks |
b2b8c24e ILT |
1978 | && (prev_pinfo |
1979 | & (INSN_READ_LO | |
1980 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1981 | || (! mips_opts.mips16 |
1982 | && ! gpr_interlocks | |
1983 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1984 | || (! mips_opts.mips16 |
1985 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1986 | /* Itbl support may require additional care here. */ |
1987 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1988 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1989 | || (prev_pinfo |
6e8dda9c ILT |
1990 | & (INSN_UNCOND_BRANCH_DELAY |
1991 | | INSN_COND_BRANCH_DELAY | |
1992 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1993 | /* We do not swap with a trap instruction, since it |
1994 | complicates trap handlers to have the trap | |
1995 | instruction be in a delay slot. */ | |
1aa6938e | 1996 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1997 | /* If the branch reads a register that the previous |
1998 | instruction sets, we can not swap. */ | |
3c83da8a | 1999 | || (! mips_opts.mips16 |
cc5703cd | 2000 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2001 | && insn_uses_reg (ip, |
2002 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2003 | & OP_MASK_RT), | |
cc5703cd | 2004 | MIPS_GR_REG)) |
3c83da8a | 2005 | || (! mips_opts.mips16 |
cc5703cd | 2006 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2007 | && insn_uses_reg (ip, |
2008 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2009 | & OP_MASK_RD), | |
cc5703cd | 2010 | MIPS_GR_REG)) |
3c83da8a | 2011 | || (mips_opts.mips16 |
cc5703cd ILT |
2012 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2013 | && insn_uses_reg (ip, | |
2014 | ((prev_insn.insn_opcode | |
2015 | >> MIPS16OP_SH_RX) | |
2016 | & MIPS16OP_MASK_RX), | |
2017 | MIPS16_REG)) | |
2018 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2019 | && insn_uses_reg (ip, | |
2020 | ((prev_insn.insn_opcode | |
2021 | >> MIPS16OP_SH_RY) | |
2022 | & MIPS16OP_MASK_RY), | |
2023 | MIPS16_REG)) | |
2024 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2025 | && insn_uses_reg (ip, | |
2026 | ((prev_insn.insn_opcode | |
2027 | >> MIPS16OP_SH_RZ) | |
2028 | & MIPS16OP_MASK_RZ), | |
2029 | MIPS16_REG)) | |
2030 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2031 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2032 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2033 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2034 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2035 | && insn_uses_reg (ip, | |
2036 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2037 | insn_opcode), | |
2038 | MIPS_GR_REG)))) | |
1849d646 ILT |
2039 | /* If the branch writes a register that the previous |
2040 | instruction sets, we can not swap (we know that | |
2041 | branches write only to RD or to $31). */ | |
3c83da8a | 2042 | || (! mips_opts.mips16 |
cc5703cd | 2043 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2044 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2045 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2046 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2047 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2048 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2049 | & OP_MASK_RT) | |
2050 | == 31)))) | |
3c83da8a | 2051 | || (! mips_opts.mips16 |
cc5703cd | 2052 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2053 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2054 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2055 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2056 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2057 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2058 | & OP_MASK_RD) | |
2059 | == 31)))) | |
3c83da8a | 2060 | || (mips_opts.mips16 |
cc5703cd ILT |
2061 | && (pinfo & MIPS16_INSN_WRITE_31) |
2062 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2063 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2064 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2065 | == RA)))) | |
becfe05e ILT |
2066 | /* If the branch writes a register that the previous |
2067 | instruction reads, we can not swap (we know that | |
2068 | branches only write to RD or to $31). */ | |
3c83da8a | 2069 | || (! mips_opts.mips16 |
cc5703cd | 2070 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2071 | && insn_uses_reg (&prev_insn, |
2072 | ((ip->insn_opcode >> OP_SH_RD) | |
2073 | & OP_MASK_RD), | |
cc5703cd | 2074 | MIPS_GR_REG)) |
3c83da8a | 2075 | || (! mips_opts.mips16 |
cc5703cd ILT |
2076 | && (pinfo & INSN_WRITE_GPR_31) |
2077 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2078 | || (mips_opts.mips16 |
cc5703cd ILT |
2079 | && (pinfo & MIPS16_INSN_WRITE_31) |
2080 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2081 | /* If we are generating embedded PIC code, the branch |
2082 | might be expanded into a sequence which uses $at, so | |
2083 | we can't swap with an instruction which reads it. */ | |
2084 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2085 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2086 | /* If the previous previous instruction has a load |
2087 | delay, and sets a register that the branch reads, we | |
2088 | can not swap. */ | |
3c83da8a JW |
2089 | || (! mips_opts.mips16 |
2090 | && mips_opts.isa < 4 | |
efec4a28 | 2091 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2092 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2093 | || (! gpr_interlocks |
d8a1c247 KR |
2094 | && (prev_prev_insn.insn_mo->pinfo |
2095 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2096 | && insn_uses_reg (ip, |
2097 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2098 | & OP_MASK_RT), | |
cc5703cd | 2099 | MIPS_GR_REG)) |
d31a3f5e ILT |
2100 | /* If one instruction sets a condition code and the |
2101 | other one uses a condition code, we can not swap. */ | |
2102 | || ((pinfo & INSN_READ_COND_CODE) | |
2103 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2104 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2105 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2106 | /* If the previous instruction uses the PC, we can not | |
2107 | swap. */ | |
3c83da8a | 2108 | || (mips_opts.mips16 |
cc5703cd ILT |
2109 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2110 | /* If the previous instruction was extended, we can not | |
2111 | swap. */ | |
3c83da8a | 2112 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2113 | /* If the previous instruction had a fixup in mips16 |
2114 | mode, we can not swap. This normally means that the | |
2115 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2116 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2117 | { |
2118 | /* We could do even better for unconditional branches to | |
2119 | portions of this object file; we could pick up the | |
2120 | instruction at the destination, put it in the delay | |
2121 | slot, and bump the destination address. */ | |
2122 | emit_nop (); | |
2123 | /* Update the previous insn information. */ | |
2124 | prev_prev_insn = *ip; | |
2125 | prev_insn.insn_mo = &dummy_opcode; | |
2126 | } | |
2127 | else | |
2128 | { | |
becfe05e | 2129 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2130 | if (! mips_opts.mips16) |
cc5703cd ILT |
2131 | { |
2132 | char *prev_f; | |
2133 | char temp[4]; | |
2134 | ||
2135 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2136 | memcpy (temp, prev_f, 4); | |
2137 | memcpy (prev_f, f, 4); | |
2138 | memcpy (f, temp, 4); | |
2139 | if (prev_insn_fixp) | |
2140 | { | |
2141 | prev_insn_fixp->fx_frag = frag_now; | |
2142 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2143 | } | |
2144 | if (fixp) | |
2145 | { | |
2146 | fixp->fx_frag = prev_insn_frag; | |
2147 | fixp->fx_where = prev_insn_where; | |
2148 | } | |
2149 | } | |
cc5703cd | 2150 | else |
becfe05e | 2151 | { |
cc5703cd ILT |
2152 | char *prev_f; |
2153 | char temp[2]; | |
2154 | ||
2155 | assert (prev_insn_fixp == NULL); | |
2156 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2157 | memcpy (temp, prev_f, 2); | |
2158 | memcpy (prev_f, f, 2); | |
2159 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2160 | { |
2161 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2162 | memcpy (f, temp, 2); | |
2163 | } | |
cc5703cd ILT |
2164 | else |
2165 | { | |
2166 | memcpy (f, f + 2, 2); | |
2167 | memcpy (f + 2, temp, 2); | |
2168 | } | |
2169 | if (fixp) | |
2170 | { | |
2171 | fixp->fx_frag = prev_insn_frag; | |
2172 | fixp->fx_where = prev_insn_where; | |
2173 | } | |
becfe05e | 2174 | } |
cc5703cd | 2175 | |
becfe05e ILT |
2176 | /* Update the previous insn information; leave prev_insn |
2177 | unchanged. */ | |
2178 | prev_prev_insn = *ip; | |
2179 | } | |
2180 | prev_insn_is_delay_slot = 1; | |
2181 | ||
2182 | /* If that was an unconditional branch, forget the previous | |
2183 | insn information. */ | |
1aa6938e | 2184 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2185 | { |
2186 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2187 | prev_insn.insn_mo = &dummy_opcode; | |
2188 | } | |
a677feeb ILT |
2189 | |
2190 | prev_insn_fixp = NULL; | |
2191 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2192 | prev_insn_extended = 0; | |
becfe05e | 2193 | } |
1aa6938e | 2194 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2195 | { |
2196 | /* We don't yet optimize a branch likely. What we should do | |
2197 | is look at the target, copy the instruction found there | |
2198 | into the delay slot, and increment the branch to jump to | |
2199 | the next instruction. */ | |
2200 | emit_nop (); | |
2201 | /* Update the previous insn information. */ | |
2202 | prev_prev_insn = *ip; | |
2203 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2204 | prev_insn_fixp = NULL; |
2205 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2206 | prev_insn_extended = 0; | |
8358c818 | 2207 | } |
becfe05e | 2208 | else |
670a50eb | 2209 | { |
becfe05e ILT |
2210 | /* Update the previous insn information. */ |
2211 | if (nops > 0) | |
2212 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2213 | else | |
2214 | prev_prev_insn = prev_insn; | |
2215 | prev_insn = *ip; | |
2216 | ||
2217 | /* Any time we see a branch, we always fill the delay slot | |
2218 | immediately; since this insn is not a branch, we know it | |
2219 | is not in a delay slot. */ | |
2220 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2221 | |
2222 | prev_insn_fixp = fixp; | |
2223 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2224 | if (mips_opts.mips16) |
a677feeb ILT |
2225 | prev_insn_extended = (ip->use_extend |
2226 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2227 | } |
2228 | ||
4e95866e ILT |
2229 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2230 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2231 | prev_insn_frag = frag_now; |
2232 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2233 | prev_insn_valid = 1; |
2234 | } | |
fbcfacb7 | 2235 | else if (place == NULL) |
a677feeb | 2236 | { |
fbcfacb7 | 2237 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2238 | reordering, in order to determine the base address for mips16 |
2239 | PC relative relocs. */ | |
4a1cb507 | 2240 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2241 | prev_insn = *ip; |
2242 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2243 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2244 | prev_insn_unreordered = 1; | |
a677feeb | 2245 | } |
3d3c5039 | 2246 | |
becfe05e | 2247 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2248 | mips_clear_insn_labels (); |
b073d428 ILT |
2249 | |
2250 | /* We must ensure that a fixup associated with an unmatched %hi | |
2251 | reloc does not become a variant frag. Otherwise, the | |
2252 | rearrangement of %hi relocs in frob_file may confuse | |
2253 | tc_gen_reloc. */ | |
2254 | if (unmatched_hi) | |
2255 | { | |
2256 | frag_wane (frag_now); | |
2257 | frag_new (0); | |
2258 | } | |
becfe05e ILT |
2259 | } |
2260 | ||
2261 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2262 | label. If PRESERVE is non-zero, it remembers enough information to |
2263 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2264 | |
2265 | static void | |
4a1cb507 ILT |
2266 | mips_no_prev_insn (preserve) |
2267 | int preserve; | |
becfe05e | 2268 | { |
4a1cb507 ILT |
2269 | if (! preserve) |
2270 | { | |
2271 | prev_insn.insn_mo = &dummy_opcode; | |
2272 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2273 | prev_nop_frag = NULL; | |
2274 | prev_nop_frag_holds = 0; | |
2275 | prev_nop_frag_required = 0; | |
2276 | prev_nop_frag_since = 0; | |
2277 | } | |
becfe05e ILT |
2278 | prev_insn_valid = 0; |
2279 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2280 | prev_insn_unreordered = 0; |
cc5703cd | 2281 | prev_insn_extended = 0; |
a677feeb | 2282 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2283 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2284 | mips_clear_insn_labels (); |
becfe05e ILT |
2285 | } |
2286 | ||
2287 | /* This function must be called whenever we turn on noreorder or emit | |
2288 | something other than instructions. It inserts any NOPS which might | |
2289 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2290 | kept for the previous instructions. The INSNS parameter is true if |
2291 | instructions are to follow. */ | |
becfe05e ILT |
2292 | |
2293 | static void | |
fbcfacb7 ILT |
2294 | mips_emit_delays (insns) |
2295 | boolean insns; | |
becfe05e | 2296 | { |
3c83da8a | 2297 | if (! mips_opts.noreorder) |
becfe05e | 2298 | { |
4a1cb507 | 2299 | int nops; |
becfe05e | 2300 | |
4a1cb507 | 2301 | nops = 0; |
3c83da8a JW |
2302 | if ((! mips_opts.mips16 |
2303 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2304 | && (! cop_interlocks |
2305 | && (prev_insn.insn_mo->pinfo | |
2306 | & (INSN_LOAD_COPROC_DELAY | |
2307 | | INSN_COPROC_MOVE_DELAY | |
2308 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2309 | || (! hilo_interlocks |
b2b8c24e ILT |
2310 | && (prev_insn.insn_mo->pinfo |
2311 | & (INSN_READ_LO | |
2312 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2313 | || (! mips_opts.mips16 |
2314 | && ! gpr_interlocks | |
2315 | && (prev_insn.insn_mo->pinfo | |
2316 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2317 | || (! mips_opts.mips16 |
2318 | && mips_opts.isa < 2 | |
8358c818 | 2319 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2320 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2321 | { |
efec4a28 | 2322 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2323 | ++nops; |
3c83da8a JW |
2324 | if ((! mips_opts.mips16 |
2325 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2326 | && (! cop_interlocks |
2327 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2328 | || (! hilo_interlocks |
b2b8c24e ILT |
2329 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2330 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2331 | ++nops; |
2332 | ||
2333 | if (prev_insn_unreordered) | |
2334 | nops = 0; | |
becfe05e | 2335 | } |
3c83da8a JW |
2336 | else if ((! mips_opts.mips16 |
2337 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2338 | && (! cop_interlocks |
2339 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2340 | || (! hilo_interlocks |
b2b8c24e ILT |
2341 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2342 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2343 | { |
efec4a28 | 2344 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2345 | if (! prev_prev_insn_unreordered) |
2346 | ++nops; | |
2347 | } | |
2348 | ||
2349 | if (nops > 0) | |
670a50eb | 2350 | { |
fbcfacb7 ILT |
2351 | struct insn_label_list *l; |
2352 | ||
4a1cb507 ILT |
2353 | if (insns) |
2354 | { | |
2355 | /* Record the frag which holds the nop instructions, so | |
2356 | that we can remove them if we don't need them. */ | |
3c83da8a | 2357 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2358 | prev_nop_frag = frag_now; |
2359 | prev_nop_frag_holds = nops; | |
2360 | prev_nop_frag_required = 0; | |
2361 | prev_nop_frag_since = 0; | |
2362 | } | |
2363 | ||
2364 | for (; nops > 0; --nops) | |
2365 | emit_nop (); | |
2366 | ||
2367 | if (insns) | |
2368 | { | |
2369 | /* Move on to a new frag, so that it is safe to simply | |
2370 | decrease the size of prev_nop_frag. */ | |
2371 | frag_wane (frag_now); | |
2372 | frag_new (0); | |
2373 | } | |
2374 | ||
fbcfacb7 | 2375 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2376 | { |
fbcfacb7 ILT |
2377 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2378 | l->label->sy_frag = frag_now; | |
2379 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2380 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2381 | if (mips_opts.mips16) |
fbcfacb7 | 2382 | ++l->label->sy_value.X_add_number; |
becfe05e | 2383 | } |
3d3c5039 ILT |
2384 | } |
2385 | } | |
0221ddf7 | 2386 | |
3c83da8a JW |
2387 | /* Mark instruction labels in mips16 mode. */ |
2388 | if (mips_opts.mips16 && insns) | |
2389 | mips16_mark_labels (); | |
fbcfacb7 | 2390 | |
4a1cb507 | 2391 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2392 | } |
2393 | ||
670a50eb ILT |
2394 | /* Build an instruction created by a macro expansion. This is passed |
2395 | a pointer to the count of instructions created so far, an | |
2396 | expression, the name of the instruction to build, an operand format | |
2397 | string, and corresponding arguments. */ | |
2398 | ||
1dc1e798 | 2399 | #ifdef USE_STDARG |
3d3c5039 | 2400 | static void |
0dd2d296 ILT |
2401 | macro_build (char *place, |
2402 | int *counter, | |
670a50eb | 2403 | expressionS * ep, |
3d3c5039 ILT |
2404 | const char *name, |
2405 | const char *fmt, | |
2406 | ...) | |
1dc1e798 | 2407 | #else |
3d3c5039 | 2408 | static void |
0dd2d296 ILT |
2409 | macro_build (place, counter, ep, name, fmt, va_alist) |
2410 | char *place; | |
3d3c5039 ILT |
2411 | int *counter; |
2412 | expressionS *ep; | |
2413 | const char *name; | |
2414 | const char *fmt; | |
2415 | va_dcl | |
1dc1e798 | 2416 | #endif |
3d3c5039 | 2417 | { |
670a50eb ILT |
2418 | struct mips_cl_insn insn; |
2419 | bfd_reloc_code_real_type r; | |
2420 | va_list args; | |
931a1858 | 2421 | int insn_isa; |
3d3c5039 | 2422 | |
1dc1e798 | 2423 | #ifdef USE_STDARG |
670a50eb | 2424 | va_start (args, fmt); |
3d3c5039 | 2425 | #else |
670a50eb | 2426 | va_start (args); |
3d3c5039 ILT |
2427 | #endif |
2428 | ||
670a50eb ILT |
2429 | /* |
2430 | * If the macro is about to expand into a second instruction, | |
2431 | * print a warning if needed. We need to pass ip as a parameter | |
2432 | * to generate a better warning message here... | |
2433 | */ | |
3c83da8a | 2434 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2435 | as_warn ("Macro instruction expanded into multiple instructions"); |
2436 | ||
0dd2d296 ILT |
2437 | if (place == NULL) |
2438 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2439 | |
3c83da8a | 2440 | if (mips_opts.mips16) |
cc5703cd ILT |
2441 | { |
2442 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2443 | va_end (args); | |
2444 | return; | |
2445 | } | |
2446 | ||
670a50eb ILT |
2447 | r = BFD_RELOC_UNUSED; |
2448 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2449 | assert (insn.insn_mo); | |
2450 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2451 | ||
931a1858 JL |
2452 | /* Search until we get a match for NAME. */ |
2453 | while (1) | |
670a50eb | 2454 | { |
1c6f3441 | 2455 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2456 | insn_isa = 1; |
2457 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2458 | insn_isa = 2; | |
2459 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2460 | insn_isa = 3; | |
2461 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2462 | insn_isa = 4; | |
2463 | else | |
2464 | insn_isa = 15; | |
2465 | ||
a652f74c ILT |
2466 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2467 | && insn.insn_mo->pinfo != INSN_MACRO | |
2468 | && (insn_isa <= mips_opts.isa | |
2469 | || (mips_4650 | |
2470 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2471 | || (mips_4010 | |
2472 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2473 | || (mips_4100 | |
2474 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
2d035a50 GRK |
2475 | /* start-sanitize-vr4320 */ |
2476 | || (mips_4320 | |
2477 | && (insn.insn_mo->membership & INSN_4320) != 0) | |
2478 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
2479 | /* start-sanitize-tx49 */ |
2480 | || (mips_4900 | |
2481 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2482 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2483 | /* start-sanitize-r5900 */ |
2484 | || (mips_5900 | |
2485 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2486 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
2487 | /* start-sanitize-vr5400 */ |
2488 | || (mips_5400 | |
2489 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
2490 | /* end-sanitize-vr5400 */ | |
a652f74c ILT |
2491 | || (mips_3900 |
2492 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2493 | /* start-sanitize-r5900 */ | |
2494 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2495 | /* end-sanitize-r5900 */ | |
2496 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2497 | break; | |
931a1858 | 2498 | |
a652f74c ILT |
2499 | ++insn.insn_mo; |
2500 | assert (insn.insn_mo->name); | |
2501 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2502 | } |
931a1858 | 2503 | |
670a50eb ILT |
2504 | insn.insn_opcode = insn.insn_mo->match; |
2505 | for (;;) | |
2506 | { | |
2507 | switch (*fmt++) | |
2508 | { | |
3d3c5039 | 2509 | case '\0': |
670a50eb | 2510 | break; |
3d3c5039 ILT |
2511 | |
2512 | case ',': | |
2513 | case '(': | |
2514 | case ')': | |
670a50eb | 2515 | continue; |
3d3c5039 ILT |
2516 | |
2517 | case 't': | |
2518 | case 'w': | |
918692a5 | 2519 | case 'E': |
670a50eb ILT |
2520 | insn.insn_opcode |= va_arg (args, int) << 16; |
2521 | continue; | |
3d3c5039 ILT |
2522 | |
2523 | case 'c': | |
2524 | case 'T': | |
2525 | case 'W': | |
670a50eb ILT |
2526 | insn.insn_opcode |= va_arg (args, int) << 16; |
2527 | continue; | |
3d3c5039 ILT |
2528 | |
2529 | case 'd': | |
918692a5 | 2530 | case 'G': |
670a50eb ILT |
2531 | insn.insn_opcode |= va_arg (args, int) << 11; |
2532 | continue; | |
3d3c5039 ILT |
2533 | |
2534 | case 'V': | |
2535 | case 'S': | |
670a50eb ILT |
2536 | insn.insn_opcode |= va_arg (args, int) << 11; |
2537 | continue; | |
3d3c5039 | 2538 | |
ff3a5c18 ILT |
2539 | case 'z': |
2540 | continue; | |
2541 | ||
3d3c5039 | 2542 | case '<': |
670a50eb ILT |
2543 | insn.insn_opcode |= va_arg (args, int) << 6; |
2544 | continue; | |
3d3c5039 ILT |
2545 | |
2546 | case 'D': | |
670a50eb ILT |
2547 | insn.insn_opcode |= va_arg (args, int) << 6; |
2548 | continue; | |
3d3c5039 | 2549 | |
918692a5 ILT |
2550 | case 'B': |
2551 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2552 | continue; | |
2553 | ||
3d3c5039 ILT |
2554 | case 'b': |
2555 | case 's': | |
2556 | case 'r': | |
2557 | case 'v': | |
670a50eb ILT |
2558 | insn.insn_opcode |= va_arg (args, int) << 21; |
2559 | continue; | |
3d3c5039 ILT |
2560 | |
2561 | case 'i': | |
2562 | case 'j': | |
2563 | case 'o': | |
9226253a | 2564 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2565 | assert (r == BFD_RELOC_MIPS_GPREL |
2566 | || r == BFD_RELOC_MIPS_LITERAL | |
2567 | || r == BFD_RELOC_LO16 | |
2568 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2569 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2570 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2571 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2572 | || (ep->X_op == O_subtract |
2573 | && now_seg == text_section | |
ecd4ca1c | 2574 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2575 | continue; |
3d3c5039 | 2576 | |
6e8dda9c | 2577 | case 'u': |
ecd4ca1c ILT |
2578 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2579 | assert (ep != NULL | |
2580 | && (ep->X_op == O_constant | |
2581 | || (ep->X_op == O_symbol | |
2582 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2583 | || r == BFD_RELOC_HI16 |
2584 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2585 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2586 | || (ep->X_op == O_subtract |
2587 | && now_seg == text_section | |
ecd4ca1c ILT |
2588 | && r == BFD_RELOC_PCREL_HI16_S))); |
2589 | if (ep->X_op == O_constant) | |
2590 | { | |
2591 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2592 | ep = NULL; | |
2593 | r = BFD_RELOC_UNUSED; | |
2594 | } | |
6e8dda9c ILT |
2595 | continue; |
2596 | ||
3d3c5039 | 2597 | case 'p': |
670a50eb ILT |
2598 | assert (ep != NULL); |
2599 | /* | |
2600 | * This allows macro() to pass an immediate expression for | |
2601 | * creating short branches without creating a symbol. | |
2602 | * Note that the expression still might come from the assembly | |
2603 | * input, in which case the value is not checked for range nor | |
2604 | * is a relocation entry generated (yuck). | |
2605 | */ | |
5ac34ac3 | 2606 | if (ep->X_op == O_constant) |
670a50eb ILT |
2607 | { |
2608 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2609 | ep = NULL; | |
2610 | } | |
2611 | else | |
2612 | r = BFD_RELOC_16_PCREL_S2; | |
2613 | continue; | |
3d3c5039 | 2614 | |
9226253a ILT |
2615 | case 'a': |
2616 | assert (ep != NULL); | |
2617 | r = BFD_RELOC_MIPS_JMP; | |
2618 | continue; | |
2619 | ||
65d2c7d3 JL |
2620 | case 'C': |
2621 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2622 | continue; | |
2623 | ||
3d3c5039 | 2624 | default: |
670a50eb | 2625 | internalError (); |
3d3c5039 | 2626 | } |
670a50eb | 2627 | break; |
3d3c5039 | 2628 | } |
670a50eb ILT |
2629 | va_end (args); |
2630 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2631 | ||
867a58b3 | 2632 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2633 | } |
2634 | ||
cc5703cd ILT |
2635 | static void |
2636 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2637 | char *place; | |
2638 | int *counter; | |
2639 | expressionS *ep; | |
2640 | const char *name; | |
2641 | const char *fmt; | |
2642 | va_list args; | |
2643 | { | |
2644 | struct mips_cl_insn insn; | |
2645 | bfd_reloc_code_real_type r; | |
2646 | ||
2647 | r = BFD_RELOC_UNUSED; | |
2648 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2649 | assert (insn.insn_mo); | |
2650 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2651 | ||
2652 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2653 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2654 | { | |
2655 | ++insn.insn_mo; | |
2656 | assert (insn.insn_mo->name); | |
2657 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2658 | } | |
2659 | ||
2660 | insn.insn_opcode = insn.insn_mo->match; | |
2661 | insn.use_extend = false; | |
2662 | ||
2663 | for (;;) | |
2664 | { | |
2665 | int c; | |
2666 | ||
2667 | c = *fmt++; | |
2668 | switch (c) | |
2669 | { | |
2670 | case '\0': | |
2671 | break; | |
2672 | ||
2673 | case ',': | |
2674 | case '(': | |
2675 | case ')': | |
2676 | continue; | |
2677 | ||
2678 | case 'y': | |
2679 | case 'w': | |
2680 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2681 | continue; | |
2682 | ||
2683 | case 'x': | |
2684 | case 'v': | |
2685 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2686 | continue; | |
2687 | ||
2688 | case 'z': | |
2689 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2690 | continue; | |
2691 | ||
2692 | case 'Z': | |
2693 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2694 | continue; | |
2695 | ||
2696 | case '0': | |
2697 | case 'S': | |
2698 | case 'P': | |
2699 | case 'R': | |
2700 | continue; | |
2701 | ||
2702 | case 'X': | |
2703 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2704 | continue; | |
2705 | ||
2706 | case 'Y': | |
2707 | { | |
2708 | int regno; | |
2709 | ||
2710 | regno = va_arg (args, int); | |
2711 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2712 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2713 | } | |
2714 | continue; | |
2715 | ||
2716 | case '<': | |
2717 | case '>': | |
2718 | case '4': | |
2719 | case '5': | |
2720 | case 'H': | |
2721 | case 'W': | |
2722 | case 'D': | |
2723 | case 'j': | |
2724 | case '8': | |
2725 | case 'V': | |
2726 | case 'C': | |
2727 | case 'U': | |
2728 | case 'k': | |
2729 | case 'K': | |
2730 | case 'p': | |
2731 | case 'q': | |
2732 | { | |
2733 | assert (ep != NULL); | |
2734 | ||
2735 | if (ep->X_op != O_constant) | |
2736 | r = BFD_RELOC_UNUSED + c; | |
2737 | else | |
2738 | { | |
15e69f98 ILT |
2739 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2740 | false, false, &insn.insn_opcode, | |
2741 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2742 | ep = NULL; |
2743 | r = BFD_RELOC_UNUSED; | |
2744 | } | |
2745 | } | |
2746 | continue; | |
2747 | ||
2748 | case '6': | |
2749 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2750 | continue; | |
2751 | } | |
2752 | ||
2753 | break; | |
2754 | } | |
2755 | ||
2756 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2757 | ||
2758 | append_insn (place, &insn, ep, r, false); | |
2759 | } | |
2760 | ||
3d3c5039 ILT |
2761 | /* |
2762 | * Generate a "lui" instruction. | |
2763 | */ | |
2764 | static void | |
0dd2d296 ILT |
2765 | macro_build_lui (place, counter, ep, regnum) |
2766 | char *place; | |
3d3c5039 ILT |
2767 | int *counter; |
2768 | expressionS *ep; | |
2769 | int regnum; | |
2770 | { | |
670a50eb ILT |
2771 | expressionS high_expr; |
2772 | struct mips_cl_insn insn; | |
2773 | bfd_reloc_code_real_type r; | |
2774 | CONST char *name = "lui"; | |
2775 | CONST char *fmt = "t,u"; | |
2776 | ||
3c83da8a | 2777 | assert (! mips_opts.mips16); |
cc5703cd | 2778 | |
0dd2d296 ILT |
2779 | if (place == NULL) |
2780 | high_expr = *ep; | |
2781 | else | |
2782 | { | |
2783 | high_expr.X_op = O_constant; | |
fb251650 | 2784 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2785 | } |
670a50eb | 2786 | |
5ac34ac3 | 2787 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2788 | { |
2789 | /* we can compute the instruction now without a relocation entry */ | |
2790 | if (high_expr.X_add_number & 0x8000) | |
2791 | high_expr.X_add_number += 0x10000; | |
2792 | high_expr.X_add_number = | |
2793 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2794 | r = BFD_RELOC_UNUSED; | |
2795 | } | |
2796 | else | |
0dd2d296 ILT |
2797 | { |
2798 | assert (ep->X_op == O_symbol); | |
2799 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2800 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2801 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2802 | r = BFD_RELOC_HI16_S; | |
2803 | } | |
670a50eb ILT |
2804 | |
2805 | /* | |
2806 | * If the macro is about to expand into a second instruction, | |
2807 | * print a warning if needed. We need to pass ip as a parameter | |
2808 | * to generate a better warning message here... | |
2809 | */ | |
3c83da8a | 2810 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2811 | as_warn ("Macro instruction expanded into multiple instructions"); |
2812 | ||
0dd2d296 ILT |
2813 | if (place == NULL) |
2814 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2815 | |
2816 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2817 | assert (insn.insn_mo); | |
2818 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2819 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2820 | ||
0dd2d296 | 2821 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2822 | if (r == BFD_RELOC_UNUSED) |
2823 | { | |
2824 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2825 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2826 | } |
2827 | else | |
867a58b3 | 2828 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2829 | } |
2830 | ||
2831 | /* set_at() | |
2832 | * Generates code to set the $at register to true (one) | |
2833 | * if reg is less than the immediate expression. | |
2834 | */ | |
2835 | static void | |
6e8dda9c | 2836 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2837 | int *counter; |
2838 | int reg; | |
6e8dda9c | 2839 | int unsignedp; |
3d3c5039 | 2840 | { |
5c6f5923 GRK |
2841 | if (imm_expr.X_op == O_constant |
2842 | && imm_expr.X_add_number >= -0x8000 | |
2843 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2844 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2845 | unsignedp ? "sltiu" : "slti", |
9226253a | 2846 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2847 | else |
670a50eb | 2848 | { |
d8a1c247 | 2849 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2850 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2851 | unsignedp ? "sltu" : "slt", |
2852 | "d,v,t", AT, reg, AT); | |
670a50eb | 2853 | } |
3d3c5039 ILT |
2854 | } |
2855 | ||
6e8dda9c | 2856 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2857 | |
2858 | static void | |
19ed8960 | 2859 | check_absolute_expr (ip, ex) |
3d3c5039 | 2860 | struct mips_cl_insn *ip; |
19ed8960 | 2861 | expressionS *ex; |
3d3c5039 | 2862 | { |
5c6f5923 GRK |
2863 | if (ex->X_op == O_big) |
2864 | as_bad ("unsupported large constant"); | |
2865 | else if (ex->X_op != O_constant) | |
4dc85508 | 2866 | as_bad ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2867 | } |
2868 | ||
ff8716f5 JSC |
2869 | /* Count the leading zeroes by performing a binary chop. This is a |
2870 | bulky bit of source, but performance is a LOT better for the | |
2871 | majority of values than a simple loop to count the bits: | |
2872 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2873 | if ((v) & (1 << (31 - lcnt))) | |
2874 | break; | |
2875 | However it is not code size friendly, and the gain will drop a bit | |
2876 | on certain cached systems. | |
2877 | */ | |
2878 | #define COUNT_TOP_ZEROES(v) \ | |
2879 | (((v) & ~0xffff) == 0 \ | |
2880 | ? ((v) & ~0xff) == 0 \ | |
2881 | ? ((v) & ~0xf) == 0 \ | |
2882 | ? ((v) & ~0x3) == 0 \ | |
2883 | ? ((v) & ~0x1) == 0 \ | |
2884 | ? !(v) \ | |
2885 | ? 32 \ | |
2886 | : 31 \ | |
2887 | : 30 \ | |
2888 | : ((v) & ~0x7) == 0 \ | |
2889 | ? 29 \ | |
2890 | : 28 \ | |
2891 | : ((v) & ~0x3f) == 0 \ | |
2892 | ? ((v) & ~0x1f) == 0 \ | |
2893 | ? 27 \ | |
2894 | : 26 \ | |
2895 | : ((v) & ~0x7f) == 0 \ | |
2896 | ? 25 \ | |
2897 | : 24 \ | |
2898 | : ((v) & ~0xfff) == 0 \ | |
2899 | ? ((v) & ~0x3ff) == 0 \ | |
2900 | ? ((v) & ~0x1ff) == 0 \ | |
2901 | ? 23 \ | |
2902 | : 22 \ | |
2903 | : ((v) & ~0x7ff) == 0 \ | |
2904 | ? 21 \ | |
2905 | : 20 \ | |
2906 | : ((v) & ~0x3fff) == 0 \ | |
2907 | ? ((v) & ~0x1fff) == 0 \ | |
2908 | ? 19 \ | |
2909 | : 18 \ | |
2910 | : ((v) & ~0x7fff) == 0 \ | |
2911 | ? 17 \ | |
2912 | : 16 \ | |
2913 | : ((v) & ~0xffffff) == 0 \ | |
2914 | ? ((v) & ~0xfffff) == 0 \ | |
2915 | ? ((v) & ~0x3ffff) == 0 \ | |
2916 | ? ((v) & ~0x1ffff) == 0 \ | |
2917 | ? 15 \ | |
2918 | : 14 \ | |
2919 | : ((v) & ~0x7ffff) == 0 \ | |
2920 | ? 13 \ | |
2921 | : 12 \ | |
2922 | : ((v) & ~0x3fffff) == 0 \ | |
2923 | ? ((v) & ~0x1fffff) == 0 \ | |
2924 | ? 11 \ | |
2925 | : 10 \ | |
2926 | : ((v) & ~0x7fffff) == 0 \ | |
2927 | ? 9 \ | |
2928 | : 8 \ | |
2929 | : ((v) & ~0xfffffff) == 0 \ | |
2930 | ? ((v) & ~0x3ffffff) == 0 \ | |
2931 | ? ((v) & ~0x1ffffff) == 0 \ | |
2932 | ? 7 \ | |
2933 | : 6 \ | |
2934 | : ((v) & ~0x7ffffff) == 0 \ | |
2935 | ? 5 \ | |
2936 | : 4 \ | |
2937 | : ((v) & ~0x3fffffff) == 0 \ | |
2938 | ? ((v) & ~0x1fffffff) == 0 \ | |
2939 | ? 3 \ | |
2940 | : 2 \ | |
2941 | : ((v) & ~0x7fffffff) == 0 \ | |
2942 | ? 1 \ | |
2943 | : 0) | |
2944 | ||
3d3c5039 ILT |
2945 | /* load_register() |
2946 | * This routine generates the least number of instructions neccessary to load | |
2947 | * an absolute expression value into a register. | |
2948 | */ | |
2949 | static void | |
d8a1c247 | 2950 | load_register (counter, reg, ep, dbl) |
670a50eb | 2951 | int *counter; |
670a50eb ILT |
2952 | int reg; |
2953 | expressionS *ep; | |
d8a1c247 | 2954 | int dbl; |
3d3c5039 | 2955 | { |
c36a90ef ILT |
2956 | int freg; |
2957 | expressionS hi32, lo32; | |
847a01cd ILT |
2958 | |
2959 | if (ep->X_op != O_big) | |
6e8dda9c | 2960 | { |
847a01cd | 2961 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2962 | if (ep->X_add_number < 0x8000 |
2963 | && (ep->X_add_number >= 0 | |
2964 | || (ep->X_add_number >= -0x8000 | |
2965 | && (! dbl | |
2966 | || ! ep->X_unsigned | |
2967 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2968 | { |
2969 | /* We can handle 16 bit signed values with an addiu to | |
2970 | $zero. No need to ever use daddiu here, since $zero and | |
2971 | the result are always correct in 32 bit mode. */ | |
2972 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2973 | (int) BFD_RELOC_LO16); | |
2974 | return; | |
2975 | } | |
2976 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2977 | { | |
2978 | /* We can handle 16 bit unsigned values with an ori to | |
2979 | $zero. */ | |
2980 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2981 | (int) BFD_RELOC_LO16); | |
2982 | return; | |
2983 | } | |
98bfd087 ILT |
2984 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2985 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2986 | == ~ (offsetT) 0x7fffffff)) | |
2987 | && (! dbl | |
2988 | || ! ep->X_unsigned | |
2989 | || sizeof (ep->X_add_number) > 4 | |
2990 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 2991 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 2992 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 2993 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
2994 | && ! dbl |
2995 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
2996 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
2997 | { |
2998 | /* 32 bit values require an lui. */ | |
2999 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3000 | (int) BFD_RELOC_HI16); | |
3001 | if ((ep->X_add_number & 0xffff) != 0) | |
3002 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3003 | (int) BFD_RELOC_LO16); | |
3004 | return; | |
3005 | } | |
6e8dda9c | 3006 | } |
847a01cd ILT |
3007 | |
3008 | /* The value is larger than 32 bits. */ | |
3009 | ||
3c83da8a | 3010 | if (mips_opts.isa < 3) |
670a50eb | 3011 | { |
6e8dda9c | 3012 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 3013 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3014 | (int) BFD_RELOC_LO16); |
847a01cd | 3015 | return; |
6e8dda9c | 3016 | } |
6e8dda9c | 3017 | |
847a01cd ILT |
3018 | if (ep->X_op != O_big) |
3019 | { | |
6e8dda9c | 3020 | hi32 = *ep; |
c36a90ef ILT |
3021 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3022 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3023 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3024 | lo32 = *ep; |
3025 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3026 | } |
847a01cd ILT |
3027 | else |
3028 | { | |
3029 | assert (ep->X_add_number > 2); | |
3030 | if (ep->X_add_number == 3) | |
3031 | generic_bignum[3] = 0; | |
3032 | else if (ep->X_add_number > 4) | |
3033 | as_bad ("Number larger than 64 bits"); | |
3034 | lo32.X_op = O_constant; | |
3035 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3036 | hi32.X_op = O_constant; | |
3037 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3038 | } | |
3039 | ||
d8a1c247 KR |
3040 | if (hi32.X_add_number == 0) |
3041 | freg = 0; | |
3042 | else | |
3043 | { | |
c36a90ef ILT |
3044 | int shift, bit; |
3045 | unsigned long hi, lo; | |
3046 | ||
fb251650 ILT |
3047 | if (hi32.X_add_number == 0xffffffff) |
3048 | { | |
3049 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3050 | { | |
c36a90ef ILT |
3051 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3052 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3053 | return; |
3054 | } | |
3055 | if (lo32.X_add_number & 0x80000000) | |
3056 | { | |
3057 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3058 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3059 | if (lo32.X_add_number & 0xffff) |
3060 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3061 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3062 | return; |
3063 | } | |
3064 | } | |
ff8716f5 | 3065 | |
c36a90ef ILT |
3066 | /* Check for 16bit shifted constant. We know that hi32 is |
3067 | non-zero, so start the mask on the first bit of the hi32 | |
3068 | value. */ | |
ff8716f5 JSC |
3069 | shift = 17; |
3070 | do | |
3071 | { | |
c36a90ef ILT |
3072 | unsigned long himask, lomask; |
3073 | ||
3074 | if (shift < 32) | |
3075 | { | |
3076 | himask = 0xffff >> (32 - shift); | |
3077 | lomask = (0xffff << shift) & 0xffffffff; | |
3078 | } | |
3079 | else | |
3080 | { | |
3081 | himask = 0xffff << (shift - 32); | |
3082 | lomask = 0; | |
3083 | } | |
3084 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3085 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3086 | { | |
3087 | expressionS tmp; | |
3088 | ||
3089 | tmp.X_op = O_constant; | |
3090 | if (shift < 32) | |
3091 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3092 | | (lo32.X_add_number >> shift)); | |
3093 | else | |
3094 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3095 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3096 | (int) BFD_RELOC_LO16); | |
3097 | macro_build ((char *) NULL, counter, NULL, | |
3098 | (shift >= 32) ? "dsll32" : "dsll", | |
3099 | "d,w,<", reg, reg, | |
3100 | (shift >= 32) ? shift - 32 : shift); | |
3101 | return; | |
3102 | } | |
ff8716f5 JSC |
3103 | shift++; |
3104 | } while (shift <= (64 - 16)); | |
3105 | ||
c36a90ef ILT |
3106 | /* Find the bit number of the lowest one bit, and store the |
3107 | shifted value in hi/lo. */ | |
3108 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3109 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3110 | if (lo != 0) | |
3111 | { | |
3112 | bit = 0; | |
3113 | while ((lo & 1) == 0) | |
3114 | { | |
3115 | lo >>= 1; | |
3116 | ++bit; | |
3117 | } | |
3118 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3119 | hi >>= bit; | |
3120 | } | |
3121 | else | |
3122 | { | |
3123 | bit = 32; | |
3124 | while ((hi & 1) == 0) | |
3125 | { | |
3126 | hi >>= 1; | |
3127 | ++bit; | |
3128 | } | |
3129 | lo = hi; | |
3130 | hi = 0; | |
3131 | } | |
3132 | ||
3133 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3134 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3135 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3136 | { |
c36a90ef | 3137 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3138 | if (shift != 0) |
3139 | { | |
c36a90ef ILT |
3140 | expressionS tmp; |
3141 | ||
3142 | /* This instruction will set the register to be all | |
3143 | ones. */ | |
ff8716f5 | 3144 | tmp.X_op = O_constant; |
c36a90ef ILT |
3145 | tmp.X_add_number = (offsetT) -1; |
3146 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3147 | reg, 0, (int) BFD_RELOC_LO16); | |
3148 | if (bit != 0) | |
ff8716f5 | 3149 | { |
c36a90ef | 3150 | bit += shift; |
ff8716f5 | 3151 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3152 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3153 | "d,w,<", reg, reg, |
c36a90ef | 3154 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3155 | } |
c36a90ef ILT |
3156 | macro_build ((char *) NULL, counter, NULL, |
3157 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3158 | "d,w,<", reg, reg, | |
3159 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3160 | return; |
3161 | } | |
3162 | } | |
c36a90ef ILT |
3163 | |
3164 | /* Sign extend hi32 before calling load_register, because we can | |
3165 | generally get better code when we load a sign extended value. */ | |
3166 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3167 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3168 | load_register (counter, reg, &hi32, 0); |
3169 | freg = reg; | |
3170 | } | |
847a01cd | 3171 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3172 | { |
3173 | if (freg != 0) | |
3174 | { | |
3175 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3176 | freg, 0); | |
3177 | freg = reg; | |
3178 | } | |
3179 | } | |
847a01cd ILT |
3180 | else |
3181 | { | |
3182 | expressionS mid16; | |
3183 | ||
fb251650 ILT |
3184 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3185 | { | |
3186 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3187 | (int) BFD_RELOC_HI16); | |
3188 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3189 | reg, 0); |
fb251650 ILT |
3190 | return; |
3191 | } | |
3192 | ||
d8a1c247 KR |
3193 | if (freg != 0) |
3194 | { | |
3195 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3196 | freg, 16); | |
3197 | freg = reg; | |
3198 | } | |
847a01cd ILT |
3199 | mid16 = lo32; |
3200 | mid16.X_add_number >>= 16; | |
3201 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3202 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3203 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3204 | reg, 16); | |
d8a1c247 | 3205 | freg = reg; |
847a01cd ILT |
3206 | } |
3207 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3208 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3209 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3210 | } |
3211 | ||
0dd2d296 ILT |
3212 | /* Load an address into a register. */ |
3213 | ||
3214 | static void | |
3215 | load_address (counter, reg, ep) | |
3216 | int *counter; | |
3217 | int reg; | |
3218 | expressionS *ep; | |
3219 | { | |
3220 | char *p; | |
3221 | ||
3222 | if (ep->X_op != O_constant | |
3223 | && ep->X_op != O_symbol) | |
3224 | { | |
3225 | as_bad ("expression too complex"); | |
3226 | ep->X_op = O_constant; | |
3227 | } | |
3228 | ||
3229 | if (ep->X_op == O_constant) | |
d9aba805 | 3230 | { |
d8a1c247 | 3231 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3232 | return; |
3233 | } | |
3234 | ||
3235 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3236 | { |
3237 | /* If this is a reference to a GP relative symbol, we want | |
3238 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3239 | Otherwise we want | |
04cb3372 | 3240 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3241 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3242 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3243 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3244 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3245 | p = NULL; |
3246 | else | |
3247 | { | |
8ea7f4e8 | 3248 | frag_grow (20); |
0dd2d296 | 3249 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3250 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3251 | || mips_opts.isa < 3) | |
3252 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3253 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3254 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3255 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3256 | mips_opts.warn_about_macros), | |
f59fb6ca | 3257 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3258 | } |
3259 | macro_build_lui (p, counter, ep, reg); | |
3260 | if (p != NULL) | |
3261 | p += 4; | |
3262 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3263 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3264 | || mips_opts.isa < 3) | |
3265 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3266 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3267 | } | |
fb251650 | 3268 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3269 | { |
3270 | expressionS ex; | |
3271 | ||
3272 | /* If this is a reference to an external symbol, we want | |
3273 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3274 | Otherwise we want | |
3275 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3276 | nop | |
3277 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3278 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3279 | ex.X_add_number = ep->X_add_number; |
3280 | ep->X_add_number = 0; | |
8ea7f4e8 | 3281 | frag_grow (20); |
0dd2d296 | 3282 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3283 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3284 | || mips_opts.isa < 3) | |
3285 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3286 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3287 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3288 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3289 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3290 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3291 | macro_build (p, counter, ep, |
9a1f3160 JL |
3292 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3293 | || mips_opts.isa < 3) | |
3294 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3295 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3296 | if (ex.X_add_number != 0) | |
3297 | { | |
3298 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3299 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3300 | ex.X_op = O_constant; | |
fb251650 | 3301 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3302 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3303 | || mips_opts.isa < 3) | |
3304 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3305 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3306 | } | |
3307 | } | |
3308 | else if (mips_pic == SVR4_PIC) | |
3309 | { | |
3310 | expressionS ex; | |
3311 | int off; | |
3312 | ||
3313 | /* This is the large GOT case. If this is a reference to an | |
3314 | external symbol, we want | |
3315 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3316 | addu $reg,$reg,$gp | |
3317 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3318 | Otherwise, for a reference to a local symbol, we want | |
3319 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3320 | nop | |
3321 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3322 | If there is a constant, it must be added in after. */ | |
3323 | ex.X_add_number = ep->X_add_number; | |
3324 | ep->X_add_number = 0; | |
3325 | if (reg_needs_delay (GP)) | |
3326 | off = 4; | |
3327 | else | |
3328 | off = 0; | |
3329 | frag_grow (32); | |
3330 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3331 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3332 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3333 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3334 | || mips_opts.isa < 3) | |
3335 | ? "addu" : "daddu"), | |
fb251650 ILT |
3336 | "d,v,t", reg, reg, GP); |
3337 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3338 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3339 | || mips_opts.isa < 3) | |
3340 | ? "lw" : "ld"), | |
fb251650 ILT |
3341 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3342 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3343 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3344 | mips_opts.warn_about_macros), |
f59fb6ca | 3345 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3346 | if (off > 0) |
3347 | { | |
3348 | /* We need a nop before loading from $gp. This special | |
3349 | check is required because the lui which starts the main | |
3350 | instruction stream does not refer to $gp, and so will not | |
3351 | insert the nop which may be required. */ | |
3352 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3353 | p += 4; | |
3354 | } | |
3355 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3356 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3357 | || mips_opts.isa < 3) | |
3358 | ? "lw" : "ld"), | |
fb251650 ILT |
3359 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3360 | p += 4; | |
3361 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3362 | p += 4; | |
3363 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3364 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3365 | || mips_opts.isa < 3) | |
3366 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3367 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3368 | if (ex.X_add_number != 0) | |
3369 | { | |
3370 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3371 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3372 | ex.X_op = O_constant; | |
3373 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3374 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3375 | || mips_opts.isa < 3) | |
3376 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3377 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3378 | } | |
d9aba805 ILT |
3379 | } |
3380 | else if (mips_pic == EMBEDDED_PIC) | |
3381 | { | |
3382 | /* We always do | |
3383 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3384 | */ | |
3385 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3386 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3387 | || mips_opts.isa < 3) | |
3388 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3389 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3390 | } | |
3391 | else | |
3392 | abort (); | |
0dd2d296 ILT |
3393 | } |
3394 | ||
3d3c5039 ILT |
3395 | /* |
3396 | * Build macros | |
3397 | * This routine implements the seemingly endless macro or synthesized | |
3398 | * instructions and addressing modes in the mips assembly language. Many | |
3399 | * of these macros are simple and are similar to each other. These could | |
3400 | * probably be handled by some kind of table or grammer aproach instead of | |
3401 | * this verbose method. Others are not simple macros but are more like | |
3402 | * optimizing code generation. | |
3403 | * One interesting optimization is when several store macros appear | |
3404 | * consecutivly that would load AT with the upper half of the same address. | |
3405 | * The ensuing load upper instructions are ommited. This implies some kind | |
3406 | * of global optimization. We currently only optimize within a single macro. | |
3407 | * For many of the load and store macros if the address is specified as a | |
3408 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3409 | * first load register 'at' with zero and use it as the base register. The | |
3410 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3411 | * we're missing. | |
3412 | */ | |
3413 | static void | |
3414 | macro (ip) | |
3415 | struct mips_cl_insn *ip; | |
3416 | { | |
670a50eb ILT |
3417 | register int treg, sreg, dreg, breg; |
3418 | int tempreg; | |
3419 | int mask; | |
3420 | int icnt = 0; | |
3421 | int used_at; | |
670a50eb ILT |
3422 | expressionS expr1; |
3423 | const char *s; | |
8358c818 | 3424 | const char *s2; |
670a50eb | 3425 | const char *fmt; |
8358c818 ILT |
3426 | int likely = 0; |
3427 | int dbl = 0; | |
3428 | int coproc = 0; | |
b2b8c24e | 3429 | int lr = 0; |
6e8dda9c | 3430 | offsetT maxnum; |
adcf2b9d | 3431 | int off; |
9226253a | 3432 | bfd_reloc_code_real_type r; |
0dd2d296 | 3433 | char *p; |
55933a58 | 3434 | int hold_mips_optimize; |
670a50eb | 3435 | |
3c83da8a | 3436 | assert (! mips_opts.mips16); |
cc5703cd | 3437 | |
670a50eb ILT |
3438 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3439 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3440 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3441 | mask = ip->insn_mo->mask; | |
3442 | ||
5ac34ac3 ILT |
3443 | expr1.X_op = O_constant; |
3444 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3445 | expr1.X_add_symbol = NULL; |
3446 | expr1.X_add_number = 1; | |
3447 | ||
3448 | switch (mask) | |
3449 | { | |
6e8dda9c ILT |
3450 | case M_DABS: |
3451 | dbl = 1; | |
3d3c5039 | 3452 | case M_ABS: |
6e8dda9c ILT |
3453 | /* bgez $a0,.+12 |
3454 | move v0,$a0 | |
3455 | sub v0,$zero,$a0 | |
3456 | */ | |
3d3c5039 | 3457 | |
fbcfacb7 | 3458 | mips_emit_delays (true); |
3c83da8a | 3459 | ++mips_opts.noreorder; |
0dd2d296 | 3460 | mips_any_noreorder = 1; |
3d3c5039 | 3461 | |
670a50eb | 3462 | expr1.X_add_number = 8; |
0dd2d296 | 3463 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3464 | if (dreg == sreg) |
0dd2d296 | 3465 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3466 | else |
0dd2d296 ILT |
3467 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3468 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3469 | dbl ? "dsub" : "sub", |
3470 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3471 | |
3c83da8a | 3472 | --mips_opts.noreorder; |
670a50eb | 3473 | return; |
3d3c5039 ILT |
3474 | |
3475 | case M_ADD_I: | |
8358c818 ILT |
3476 | s = "addi"; |
3477 | s2 = "add"; | |
3478 | goto do_addi; | |
3d3c5039 | 3479 | case M_ADDU_I: |
8358c818 ILT |
3480 | s = "addiu"; |
3481 | s2 = "addu"; | |
3482 | goto do_addi; | |
3483 | case M_DADD_I: | |
6e8dda9c | 3484 | dbl = 1; |
8358c818 ILT |
3485 | s = "daddi"; |
3486 | s2 = "dadd"; | |
3487 | goto do_addi; | |
3488 | case M_DADDU_I: | |
6e8dda9c | 3489 | dbl = 1; |
8358c818 ILT |
3490 | s = "daddiu"; |
3491 | s2 = "daddu"; | |
3492 | do_addi: | |
5c6f5923 GRK |
3493 | if (imm_expr.X_op == O_constant |
3494 | && imm_expr.X_add_number >= -0x8000 | |
3495 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3496 | { |
0dd2d296 | 3497 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3498 | (int) BFD_RELOC_LO16); |
670a50eb | 3499 | return; |
3d3c5039 | 3500 | } |
d8a1c247 | 3501 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3502 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3503 | break; |
3d3c5039 ILT |
3504 | |
3505 | case M_AND_I: | |
6e8dda9c ILT |
3506 | s = "andi"; |
3507 | s2 = "and"; | |
3508 | goto do_bit; | |
3d3c5039 | 3509 | case M_OR_I: |
6e8dda9c ILT |
3510 | s = "ori"; |
3511 | s2 = "or"; | |
3512 | goto do_bit; | |
3d3c5039 | 3513 | case M_NOR_I: |
6e8dda9c ILT |
3514 | s = ""; |
3515 | s2 = "nor"; | |
3516 | goto do_bit; | |
3d3c5039 | 3517 | case M_XOR_I: |
6e8dda9c ILT |
3518 | s = "xori"; |
3519 | s2 = "xor"; | |
3520 | do_bit: | |
5c6f5923 GRK |
3521 | if (imm_expr.X_op == O_constant |
3522 | && imm_expr.X_add_number >= 0 | |
3523 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3524 | { |
6e8dda9c | 3525 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3526 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3527 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3528 | else |
670a50eb | 3529 | { |
0dd2d296 ILT |
3530 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3531 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3532 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3533 | treg, treg, 0); |
3d3c5039 | 3534 | } |
6e8dda9c | 3535 | return; |
3d3c5039 | 3536 | } |
6e8dda9c | 3537 | |
d8a1c247 | 3538 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3539 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3540 | break; |
3d3c5039 ILT |
3541 | |
3542 | case M_BEQ_I: | |
8358c818 ILT |
3543 | s = "beq"; |
3544 | goto beq_i; | |
3545 | case M_BEQL_I: | |
3546 | s = "beql"; | |
3547 | likely = 1; | |
3548 | goto beq_i; | |
3d3c5039 | 3549 | case M_BNE_I: |
8358c818 ILT |
3550 | s = "bne"; |
3551 | goto beq_i; | |
3552 | case M_BNEL_I: | |
3553 | s = "bnel"; | |
3554 | likely = 1; | |
3555 | beq_i: | |
5c6f5923 | 3556 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3557 | { |
0dd2d296 ILT |
3558 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3559 | 0); | |
670a50eb ILT |
3560 | return; |
3561 | } | |
d8a1c247 | 3562 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3563 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3564 | break; |
3d3c5039 | 3565 | |
8358c818 ILT |
3566 | case M_BGEL: |
3567 | likely = 1; | |
3d3c5039 | 3568 | case M_BGE: |
670a50eb ILT |
3569 | if (treg == 0) |
3570 | { | |
0dd2d296 | 3571 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3572 | likely ? "bgezl" : "bgez", |
3573 | "s,p", sreg); | |
670a50eb | 3574 | return; |
3d3c5039 | 3575 | } |
9a7d824a ILT |
3576 | if (sreg == 0) |
3577 | { | |
0dd2d296 | 3578 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3579 | likely ? "blezl" : "blez", |
3580 | "s,p", treg); | |
9a7d824a ILT |
3581 | return; |
3582 | } | |
0dd2d296 ILT |
3583 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3584 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3585 | likely ? "beql" : "beq", |
3586 | "s,t,p", AT, 0); | |
670a50eb | 3587 | break; |
3d3c5039 | 3588 | |
8358c818 ILT |
3589 | case M_BGTL_I: |
3590 | likely = 1; | |
3d3c5039 | 3591 | case M_BGT_I: |
9a7d824a | 3592 | /* check for > max integer */ |
6e8dda9c | 3593 | maxnum = 0x7fffffff; |
5c6f5923 | 3594 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3595 | { |
3596 | maxnum <<= 16; | |
3597 | maxnum |= 0xffff; | |
3598 | maxnum <<= 16; | |
3599 | maxnum |= 0xffff; | |
3600 | } | |
5c6f5923 GRK |
3601 | if (imm_expr.X_op == O_constant |
3602 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3603 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3604 | { |
3605 | do_false: | |
3606 | /* result is always false */ | |
8358c818 ILT |
3607 | if (! likely) |
3608 | { | |
3609 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3610 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3611 | } |
3612 | else | |
3613 | { | |
3614 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3615 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3616 | "s,t,p", 0, 0); | |
8358c818 | 3617 | } |
9a7d824a ILT |
3618 | return; |
3619 | } | |
5c6f5923 GRK |
3620 | if (imm_expr.X_op != O_constant) |
3621 | as_bad ("Unsupported large constant"); | |
670a50eb ILT |
3622 | imm_expr.X_add_number++; |
3623 | /* FALLTHROUGH */ | |
3d3c5039 | 3624 | case M_BGE_I: |
8358c818 ILT |
3625 | case M_BGEL_I: |
3626 | if (mask == M_BGEL_I) | |
3627 | likely = 1; | |
5c6f5923 | 3628 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3629 | { |
0dd2d296 | 3630 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3631 | likely ? "bgezl" : "bgez", |
3632 | "s,p", sreg); | |
670a50eb | 3633 | return; |
3d3c5039 | 3634 | } |
5c6f5923 | 3635 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3636 | { |
0dd2d296 | 3637 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3638 | likely ? "bgtzl" : "bgtz", |
3639 | "s,p", sreg); | |
670a50eb | 3640 | return; |
3d3c5039 | 3641 | } |
6e8dda9c | 3642 | maxnum = 0x7fffffff; |
5c6f5923 | 3643 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3644 | { |
3645 | maxnum <<= 16; | |
3646 | maxnum |= 0xffff; | |
3647 | maxnum <<= 16; | |
3648 | maxnum |= 0xffff; | |
3649 | } | |
3650 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3651 | if (imm_expr.X_op == O_constant |
3652 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3653 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3654 | { |
3655 | do_true: | |
3656 | /* result is always true */ | |
3657 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3658 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3659 | return; |
3660 | } | |
6e8dda9c | 3661 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3662 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3663 | likely ? "beql" : "beq", |
3664 | "s,t,p", AT, 0); | |
670a50eb | 3665 | break; |
3d3c5039 | 3666 | |
8358c818 ILT |
3667 | case M_BGEUL: |
3668 | likely = 1; | |
3d3c5039 | 3669 | case M_BGEU: |
670a50eb | 3670 | if (treg == 0) |
9a7d824a ILT |
3671 | goto do_true; |
3672 | if (sreg == 0) | |
670a50eb | 3673 | { |
0dd2d296 | 3674 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3675 | likely ? "beql" : "beq", |
3676 | "s,t,p", 0, treg); | |
670a50eb | 3677 | return; |
3d3c5039 | 3678 | } |
0dd2d296 ILT |
3679 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3680 | treg); | |
3681 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3682 | likely ? "beql" : "beq", |
3683 | "s,t,p", AT, 0); | |
670a50eb | 3684 | break; |
3d3c5039 | 3685 | |
8358c818 ILT |
3686 | case M_BGTUL_I: |
3687 | likely = 1; | |
9a7d824a | 3688 | case M_BGTU_I: |
5c6f5923 GRK |
3689 | if (sreg == 0 |
3690 | || (mips_opts.isa < 3 | |
3691 | && imm_expr.X_op == O_constant | |
3692 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3693 | goto do_false; |
5c6f5923 GRK |
3694 | if (imm_expr.X_op != O_constant) |
3695 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3696 | imm_expr.X_add_number++; |
3697 | /* FALLTHROUGH */ | |
3d3c5039 | 3698 | case M_BGEU_I: |
8358c818 ILT |
3699 | case M_BGEUL_I: |
3700 | if (mask == M_BGEUL_I) | |
3701 | likely = 1; | |
5c6f5923 | 3702 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3703 | goto do_true; |
5c6f5923 | 3704 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3705 | { |
0dd2d296 | 3706 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3707 | likely ? "bnel" : "bne", |
3708 | "s,t,p", sreg, 0); | |
670a50eb | 3709 | return; |
3d3c5039 | 3710 | } |
6e8dda9c | 3711 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3712 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3713 | likely ? "beql" : "beq", |
3714 | "s,t,p", AT, 0); | |
670a50eb | 3715 | break; |
3d3c5039 | 3716 | |
8358c818 ILT |
3717 | case M_BGTL: |
3718 | likely = 1; | |
3d3c5039 | 3719 | case M_BGT: |
670a50eb ILT |
3720 | if (treg == 0) |
3721 | { | |
0dd2d296 | 3722 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3723 | likely ? "bgtzl" : "bgtz", |
3724 | "s,p", sreg); | |
670a50eb | 3725 | return; |
3d3c5039 | 3726 | } |
9a7d824a ILT |
3727 | if (sreg == 0) |
3728 | { | |
0dd2d296 | 3729 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3730 | likely ? "bltzl" : "bltz", |
3731 | "s,p", treg); | |
9a7d824a ILT |
3732 | return; |
3733 | } | |
0dd2d296 ILT |
3734 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3735 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3736 | likely ? "bnel" : "bne", |
3737 | "s,t,p", AT, 0); | |
670a50eb | 3738 | break; |
3d3c5039 | 3739 | |
8358c818 ILT |
3740 | case M_BGTUL: |
3741 | likely = 1; | |
3d3c5039 | 3742 | case M_BGTU: |
670a50eb ILT |
3743 | if (treg == 0) |
3744 | { | |
0dd2d296 | 3745 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3746 | likely ? "bnel" : "bne", |
3747 | "s,t,p", sreg, 0); | |
670a50eb | 3748 | return; |
3d3c5039 | 3749 | } |
9a7d824a ILT |
3750 | if (sreg == 0) |
3751 | goto do_false; | |
0dd2d296 ILT |
3752 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3753 | sreg); | |
3754 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3755 | likely ? "bnel" : "bne", |
3756 | "s,t,p", AT, 0); | |
670a50eb | 3757 | break; |
3d3c5039 | 3758 | |
8358c818 ILT |
3759 | case M_BLEL: |
3760 | likely = 1; | |
3d3c5039 | 3761 | case M_BLE: |
670a50eb ILT |
3762 | if (treg == 0) |
3763 | { | |
0dd2d296 | 3764 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3765 | likely ? "blezl" : "blez", |
3766 | "s,p", sreg); | |
670a50eb ILT |
3767 | return; |
3768 | } | |
9a7d824a ILT |
3769 | if (sreg == 0) |
3770 | { | |
0dd2d296 | 3771 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3772 | likely ? "bgezl" : "bgez", |
3773 | "s,p", treg); | |
9a7d824a ILT |
3774 | return; |
3775 | } | |
0dd2d296 ILT |
3776 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3777 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3778 | likely ? "beql" : "beq", |
3779 | "s,t,p", AT, 0); | |
670a50eb | 3780 | break; |
3d3c5039 | 3781 | |
8358c818 ILT |
3782 | case M_BLEL_I: |
3783 | likely = 1; | |
3d3c5039 | 3784 | case M_BLE_I: |
6e8dda9c | 3785 | maxnum = 0x7fffffff; |
5c6f5923 | 3786 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3787 | { |
3788 | maxnum <<= 16; | |
3789 | maxnum |= 0xffff; | |
3790 | maxnum <<= 16; | |
3791 | maxnum |= 0xffff; | |
3792 | } | |
5c6f5923 GRK |
3793 | if (imm_expr.X_op == O_constant |
3794 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3795 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3796 | goto do_true; |
5c6f5923 GRK |
3797 | if (imm_expr.X_op != O_constant) |
3798 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3799 | imm_expr.X_add_number++; |
3800 | /* FALLTHROUGH */ | |
9a7d824a | 3801 | case M_BLT_I: |
8358c818 ILT |
3802 | case M_BLTL_I: |
3803 | if (mask == M_BLTL_I) | |
3804 | likely = 1; | |
5c6f5923 | 3805 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3806 | { |
0dd2d296 | 3807 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3808 | likely ? "bltzl" : "bltz", |
3809 | "s,p", sreg); | |
670a50eb ILT |
3810 | return; |
3811 | } | |
5c6f5923 | 3812 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3813 | { |
0dd2d296 | 3814 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3815 | likely ? "blezl" : "blez", |
3816 | "s,p", sreg); | |
670a50eb ILT |
3817 | return; |
3818 | } | |
6e8dda9c | 3819 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3820 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3821 | likely ? "bnel" : "bne", |
3822 | "s,t,p", AT, 0); | |
670a50eb | 3823 | break; |
3d3c5039 | 3824 | |
8358c818 ILT |
3825 | case M_BLEUL: |
3826 | likely = 1; | |
3d3c5039 | 3827 | case M_BLEU: |
670a50eb ILT |
3828 | if (treg == 0) |
3829 | { | |
0dd2d296 | 3830 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3831 | likely ? "beql" : "beq", |
3832 | "s,t,p", sreg, 0); | |
670a50eb | 3833 | return; |
3d3c5039 | 3834 | } |
9a7d824a ILT |
3835 | if (sreg == 0) |
3836 | goto do_true; | |
0dd2d296 ILT |
3837 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3838 | sreg); | |
3839 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3840 | likely ? "beql" : "beq", |
3841 | "s,t,p", AT, 0); | |
670a50eb | 3842 | break; |
3d3c5039 | 3843 | |
8358c818 ILT |
3844 | case M_BLEUL_I: |
3845 | likely = 1; | |
3d3c5039 | 3846 | case M_BLEU_I: |
5c6f5923 GRK |
3847 | if (sreg == 0 |
3848 | || (mips_opts.isa < 3 | |
3849 | && imm_expr.X_op == O_constant | |
3850 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3851 | goto do_true; |
5c6f5923 GRK |
3852 | if (imm_expr.X_op != O_constant) |
3853 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3854 | imm_expr.X_add_number++; |
3855 | /* FALLTHROUGH */ | |
9a7d824a | 3856 | case M_BLTU_I: |
8358c818 ILT |
3857 | case M_BLTUL_I: |
3858 | if (mask == M_BLTUL_I) | |
3859 | likely = 1; | |
5c6f5923 | 3860 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3861 | goto do_false; |
5c6f5923 | 3862 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3863 | { |
0dd2d296 | 3864 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3865 | likely ? "beql" : "beq", |
3866 | "s,t,p", sreg, 0); | |
670a50eb | 3867 | return; |
3d3c5039 | 3868 | } |
6e8dda9c | 3869 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3870 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3871 | likely ? "bnel" : "bne", |
3872 | "s,t,p", AT, 0); | |
670a50eb | 3873 | break; |
3d3c5039 | 3874 | |
8358c818 ILT |
3875 | case M_BLTL: |
3876 | likely = 1; | |
3d3c5039 | 3877 | case M_BLT: |
670a50eb ILT |
3878 | if (treg == 0) |
3879 | { | |
0dd2d296 | 3880 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3881 | likely ? "bltzl" : "bltz", |
3882 | "s,p", sreg); | |
670a50eb | 3883 | return; |
3d3c5039 | 3884 | } |
9a7d824a | 3885 | if (sreg == 0) |
670a50eb | 3886 | { |
0dd2d296 | 3887 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3888 | likely ? "bgtzl" : "bgtz", |
3889 | "s,p", treg); | |
670a50eb | 3890 | return; |
3d3c5039 | 3891 | } |
0dd2d296 ILT |
3892 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3893 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3894 | likely ? "bnel" : "bne", |
3895 | "s,t,p", AT, 0); | |
670a50eb | 3896 | break; |
3d3c5039 | 3897 | |
8358c818 ILT |
3898 | case M_BLTUL: |
3899 | likely = 1; | |
3d3c5039 | 3900 | case M_BLTU: |
670a50eb | 3901 | if (treg == 0) |
9a7d824a ILT |
3902 | goto do_false; |
3903 | if (sreg == 0) | |
670a50eb | 3904 | { |
0dd2d296 | 3905 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3906 | likely ? "bnel" : "bne", |
3907 | "s,t,p", 0, treg); | |
670a50eb ILT |
3908 | return; |
3909 | } | |
0dd2d296 ILT |
3910 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3911 | treg); | |
3912 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3913 | likely ? "bnel" : "bne", |
3914 | "s,t,p", AT, 0); | |
670a50eb | 3915 | break; |
3d3c5039 | 3916 | |
8358c818 ILT |
3917 | case M_DDIV_3: |
3918 | dbl = 1; | |
3d3c5039 | 3919 | case M_DIV_3: |
8358c818 ILT |
3920 | s = "mflo"; |
3921 | goto do_div3; | |
3922 | case M_DREM_3: | |
3923 | dbl = 1; | |
3d3c5039 | 3924 | case M_REM_3: |
8358c818 ILT |
3925 | s = "mfhi"; |
3926 | do_div3: | |
670a50eb ILT |
3927 | if (treg == 0) |
3928 | { | |
3929 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3930 | if (mips_trap) |
3931 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3932 | else | |
3933 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3934 | return; |
3935 | } | |
3936 | ||
fbcfacb7 | 3937 | mips_emit_delays (true); |
3c83da8a | 3938 | ++mips_opts.noreorder; |
0dd2d296 | 3939 | mips_any_noreorder = 1; |
8ea7f4e8 | 3940 | if (mips_trap) |
6c4b811d JL |
3941 | { |
3942 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3943 | macro_build ((char *) NULL, &icnt, NULL, | |
3944 | dbl ? "ddiv" : "div", | |
3945 | "z,s,t", sreg, treg); | |
3946 | } | |
8ea7f4e8 ILT |
3947 | else |
3948 | { | |
3949 | expr1.X_add_number = 8; | |
3950 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
3951 | macro_build ((char *) NULL, &icnt, NULL, |
3952 | dbl ? "ddiv" : "div", | |
3953 | "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3954 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
3955 | } | |
670a50eb | 3956 | expr1.X_add_number = -1; |
0dd2d296 | 3957 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3958 | dbl ? "daddiu" : "addiu", |
9226253a | 3959 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3960 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3961 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3962 | if (dbl) |
3963 | { | |
3964 | expr1.X_add_number = 1; | |
0dd2d296 | 3965 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3966 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3967 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3968 | 31); | |
8358c818 ILT |
3969 | } |
3970 | else | |
3971 | { | |
3972 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3973 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3974 | (int) BFD_RELOC_HI16); | |
8358c818 | 3975 | } |
8ea7f4e8 ILT |
3976 | if (mips_trap) |
3977 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3978 | else | |
3979 | { | |
3980 | expr1.X_add_number = 8; | |
3981 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3982 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3983 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3984 | } | |
3c83da8a | 3985 | --mips_opts.noreorder; |
0dd2d296 | 3986 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3987 | break; |
3d3c5039 ILT |
3988 | |
3989 | case M_DIV_3I: | |
8358c818 ILT |
3990 | s = "div"; |
3991 | s2 = "mflo"; | |
3992 | goto do_divi; | |
3d3c5039 | 3993 | case M_DIVU_3I: |
8358c818 ILT |
3994 | s = "divu"; |
3995 | s2 = "mflo"; | |
3996 | goto do_divi; | |
3d3c5039 | 3997 | case M_REM_3I: |
8358c818 ILT |
3998 | s = "div"; |
3999 | s2 = "mfhi"; | |
4000 | goto do_divi; | |
3d3c5039 | 4001 | case M_REMU_3I: |
8358c818 ILT |
4002 | s = "divu"; |
4003 | s2 = "mfhi"; | |
4004 | goto do_divi; | |
4005 | case M_DDIV_3I: | |
4006 | dbl = 1; | |
4007 | s = "ddiv"; | |
4008 | s2 = "mflo"; | |
4009 | goto do_divi; | |
4010 | case M_DDIVU_3I: | |
4011 | dbl = 1; | |
4012 | s = "ddivu"; | |
4013 | s2 = "mflo"; | |
4014 | goto do_divi; | |
4015 | case M_DREM_3I: | |
4016 | dbl = 1; | |
4017 | s = "ddiv"; | |
4018 | s2 = "mfhi"; | |
4019 | goto do_divi; | |
4020 | case M_DREMU_3I: | |
4021 | dbl = 1; | |
4022 | s = "ddivu"; | |
4023 | s2 = "mfhi"; | |
4024 | do_divi: | |
5c6f5923 | 4025 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb ILT |
4026 | { |
4027 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
4028 | if (mips_trap) |
4029 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4030 | else | |
4031 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4032 | return; |
4033 | } | |
5c6f5923 | 4034 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4035 | { |
8358c818 | 4036 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4037 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4038 | sreg); | |
3d3c5039 | 4039 | else |
0dd2d296 | 4040 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4041 | return; |
4042 | } | |
5c6f5923 GRK |
4043 | if (imm_expr.X_op == O_constant |
4044 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4045 | && s[strlen (s) - 1] != 'u') |
4046 | { | |
4047 | if (strcmp (s2, "mflo") == 0) | |
4048 | { | |
4049 | if (dbl) | |
0dd2d296 ILT |
4050 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4051 | sreg); | |
8358c818 | 4052 | else |
0dd2d296 ILT |
4053 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4054 | sreg); | |
8358c818 ILT |
4055 | } |
4056 | else | |
0dd2d296 | 4057 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4058 | return; |
4059 | } | |
3d3c5039 | 4060 | |
d8a1c247 | 4061 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4062 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4063 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4064 | break; |
4065 | ||
4066 | case M_DIVU_3: | |
8358c818 ILT |
4067 | s = "divu"; |
4068 | s2 = "mflo"; | |
4069 | goto do_divu3; | |
670a50eb | 4070 | case M_REMU_3: |
8358c818 ILT |
4071 | s = "divu"; |
4072 | s2 = "mfhi"; | |
4073 | goto do_divu3; | |
4074 | case M_DDIVU_3: | |
4075 | s = "ddivu"; | |
4076 | s2 = "mflo"; | |
4077 | goto do_divu3; | |
4078 | case M_DREMU_3: | |
4079 | s = "ddivu"; | |
4080 | s2 = "mfhi"; | |
4081 | do_divu3: | |
fbcfacb7 | 4082 | mips_emit_delays (true); |
3c83da8a | 4083 | ++mips_opts.noreorder; |
0dd2d296 | 4084 | mips_any_noreorder = 1; |
8ea7f4e8 | 4085 | if (mips_trap) |
6c4b811d JL |
4086 | { |
4087 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4088 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4089 | } | |
8ea7f4e8 ILT |
4090 | else |
4091 | { | |
4092 | expr1.X_add_number = 8; | |
4093 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4094 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
4095 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
4096 | } | |
3c83da8a | 4097 | --mips_opts.noreorder; |
0dd2d296 | 4098 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4099 | return; |
3d3c5039 | 4100 | |
d8a1c247 KR |
4101 | case M_DLA_AB: |
4102 | dbl = 1; | |
0dd2d296 | 4103 | case M_LA_AB: |
d9aba805 ILT |
4104 | /* Load the address of a symbol into a register. If breg is not |
4105 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4106 | |
4107 | /* When generating embedded PIC code, we permit expressions of | |
4108 | the form | |
4109 | la $4,foo-bar | |
4110 | where bar is an address in the .text section. These are used | |
4111 | when getting the addresses of functions. We don't permit | |
4112 | X_add_number to be non-zero, because if the symbol is | |
4113 | external the relaxing code needs to know that any addend is | |
4114 | purely the offset to X_op_symbol. */ | |
4115 | if (mips_pic == EMBEDDED_PIC | |
4116 | && offset_expr.X_op == O_subtract | |
4117 | && now_seg == text_section | |
847a01cd ILT |
4118 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4119 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4120 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4121 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4122 | ->sy_value.X_add_symbol) | |
4123 | == text_section))) | |
ecd4ca1c ILT |
4124 | && breg == 0 |
4125 | && offset_expr.X_add_number == 0) | |
4126 | { | |
4127 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4128 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4129 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4130 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4131 | || mips_opts.isa < 3) | |
4132 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4133 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4134 | return; | |
4135 | } | |
4136 | ||
0dd2d296 ILT |
4137 | if (offset_expr.X_op != O_symbol |
4138 | && offset_expr.X_op != O_constant) | |
670a50eb | 4139 | { |
0dd2d296 ILT |
4140 | as_bad ("expression too complex"); |
4141 | offset_expr.X_op = O_constant; | |
4142 | } | |
4143 | ||
4144 | if (treg == breg) | |
4145 | { | |
4146 | tempreg = AT; | |
4147 | used_at = 1; | |
3d3c5039 | 4148 | } |
670a50eb ILT |
4149 | else |
4150 | { | |
0dd2d296 ILT |
4151 | tempreg = treg; |
4152 | used_at = 0; | |
670a50eb | 4153 | } |
3d3c5039 | 4154 | |
5ac34ac3 | 4155 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4156 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4157 | else if (mips_pic == NO_PIC) |
670a50eb | 4158 | { |
0dd2d296 ILT |
4159 | /* If this is a reference to an GP relative symbol, we want |
4160 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4161 | Otherwise we want | |
4162 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4163 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4164 | If we have a constant, we need two instructions anyhow, | |
4165 | so we may as well always use the latter form. */ | |
7a15a226 | 4166 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4167 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4168 | p = NULL; |
4169 | else | |
4170 | { | |
8ea7f4e8 | 4171 | frag_grow (20); |
0dd2d296 | 4172 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4173 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4174 | || mips_opts.isa < 3) | |
4175 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4176 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4177 | p = frag_var (rs_machine_dependent, 8, 0, | |
4178 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4179 | mips_opts.warn_about_macros), |
f59fb6ca | 4180 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4181 | (char *) NULL); |
4182 | } | |
4183 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4184 | if (p != NULL) | |
4185 | p += 4; | |
4186 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4187 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4188 | || mips_opts.isa < 3) | |
4189 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4190 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4191 | } | |
fb251650 | 4192 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4193 | { |
4194 | /* If this is a reference to an external symbol, and there | |
4195 | is no constant, we want | |
4196 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4197 | For a local symbol, we want | |
4198 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4199 | nop | |
4200 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4201 | ||
4202 | If we have a small constant, and this is a reference to | |
4203 | an external symbol, we want | |
4204 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4205 | nop | |
4206 | addiu $tempreg,$tempreg,<constant> | |
4207 | For a local symbol, we want the same instruction | |
4208 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4209 | addiu instruction. | |
4210 | ||
4211 | If we have a large constant, and this is a reference to | |
4212 | an external symbol, we want | |
4213 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4214 | lui $at,<hiconstant> | |
4215 | addiu $at,$at,<loconstant> | |
4216 | addu $tempreg,$tempreg,$at | |
4217 | For a local symbol, we want the same instruction | |
4218 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4219 | addiu instruction. */ | |
4220 | expr1.X_add_number = offset_expr.X_add_number; | |
4221 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4222 | frag_grow (32); |
0dd2d296 | 4223 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4224 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4225 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4226 | if (expr1.X_add_number == 0) | |
4227 | { | |
4228 | int off; | |
4229 | ||
4230 | if (breg == 0) | |
4231 | off = 0; | |
4232 | else | |
4233 | { | |
4234 | /* We're going to put in an addu instruction using | |
4235 | tempreg, so we may as well insert the nop right | |
4236 | now. */ | |
4237 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4238 | "nop", ""); | |
4239 | off = 4; | |
4240 | } | |
4241 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4242 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4243 | (breg == 0 | |
3c83da8a | 4244 | ? mips_opts.warn_about_macros |
0dd2d296 | 4245 | : 0)), |
f59fb6ca | 4246 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4247 | (char *) NULL); |
4248 | if (breg == 0) | |
4249 | { | |
4250 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4251 | p += 4; | |
4252 | } | |
4253 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4254 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4255 | || mips_opts.isa < 3) | |
4256 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4257 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4258 | /* FIXME: If breg == 0, and the next instruction uses | |
4259 | $tempreg, then if this variant case is used an extra | |
4260 | nop will be generated. */ | |
4261 | } | |
4262 | else if (expr1.X_add_number >= -0x8000 | |
4263 | && expr1.X_add_number < 0x8000) | |
4264 | { | |
4265 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4266 | "nop", ""); | |
4267 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4268 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4269 | || mips_opts.isa < 3) | |
4270 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4271 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4272 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4273 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4274 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4275 | (char *) NULL); |
4276 | } | |
4277 | else | |
4278 | { | |
4279 | int off1; | |
4280 | ||
4281 | /* If we are going to add in a base register, and the | |
4282 | target register and the base register are the same, | |
4283 | then we are using AT as a temporary register. Since | |
4284 | we want to load the constant into AT, we add our | |
4285 | current AT (from the global offset table) and the | |
4286 | register into the register now, and pretend we were | |
4287 | not using a base register. */ | |
4288 | if (breg != treg) | |
4289 | off1 = 0; | |
4290 | else | |
4291 | { | |
4292 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4293 | "nop", ""); | |
4294 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4295 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4296 | || mips_opts.isa < 3) | |
4297 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4298 | "d,v,t", treg, AT, breg); |
4299 | breg = 0; | |
4300 | tempreg = treg; | |
4301 | off1 = -8; | |
4302 | } | |
4303 | ||
55933a58 ILT |
4304 | /* Set mips_optimize around the lui instruction to avoid |
4305 | inserting an unnecessary nop after the lw. */ | |
4306 | hold_mips_optimize = mips_optimize; | |
4307 | mips_optimize = 2; | |
0dd2d296 | 4308 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4309 | mips_optimize = hold_mips_optimize; |
4310 | ||
0dd2d296 | 4311 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4312 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4313 | || mips_opts.isa < 3) | |
4314 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4315 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4316 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4317 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4318 | || mips_opts.isa < 3) | |
4319 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4320 | "d,v,t", tempreg, tempreg, AT); |
4321 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4322 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4323 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4324 | (char *) NULL); |
4325 | used_at = 1; | |
4326 | } | |
670a50eb | 4327 | } |
fb251650 ILT |
4328 | else if (mips_pic == SVR4_PIC) |
4329 | { | |
4330 | int gpdel; | |
4331 | ||
4332 | /* This is the large GOT case. If this is a reference to an | |
4333 | external symbol, and there is no constant, we want | |
4334 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4335 | addu $tempreg,$tempreg,$gp | |
4336 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4337 | For a local symbol, we want | |
4338 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4339 | nop | |
4340 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4341 | ||
4342 | If we have a small constant, and this is a reference to | |
4343 | an external symbol, we want | |
4344 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4345 | addu $tempreg,$tempreg,$gp | |
4346 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4347 | nop | |
4348 | addiu $tempreg,$tempreg,<constant> | |
4349 | For a local symbol, we want | |
4350 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4351 | nop | |
4352 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4353 | ||
4354 | If we have a large constant, and this is a reference to | |
4355 | an external symbol, we want | |
4356 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4357 | addu $tempreg,$tempreg,$gp | |
4358 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4359 | lui $at,<hiconstant> | |
4360 | addiu $at,$at,<loconstant> | |
4361 | addu $tempreg,$tempreg,$at | |
4362 | For a local symbol, we want | |
4363 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4364 | lui $at,<hiconstant> | |
4365 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4366 | addu $tempreg,$tempreg,$at | |
4367 | */ | |
4368 | expr1.X_add_number = offset_expr.X_add_number; | |
4369 | offset_expr.X_add_number = 0; | |
4370 | frag_grow (52); | |
4371 | if (reg_needs_delay (GP)) | |
4372 | gpdel = 4; | |
4373 | else | |
4374 | gpdel = 0; | |
4375 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4376 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4377 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4378 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4379 | || mips_opts.isa < 3) | |
4380 | ? "addu" : "daddu"), | |
fb251650 ILT |
4381 | "d,v,t", tempreg, tempreg, GP); |
4382 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4383 | dbl ? "ld" : "lw", | |
4384 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4385 | tempreg); | |
4386 | if (expr1.X_add_number == 0) | |
4387 | { | |
4388 | int off; | |
4389 | ||
4390 | if (breg == 0) | |
4391 | off = 0; | |
4392 | else | |
4393 | { | |
4394 | /* We're going to put in an addu instruction using | |
4395 | tempreg, so we may as well insert the nop right | |
4396 | now. */ | |
4397 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4398 | "nop", ""); | |
4399 | off = 4; | |
4400 | } | |
4401 | ||
4402 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4403 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4404 | 8 + gpdel, 0, | |
4405 | (breg == 0 | |
3c83da8a | 4406 | ? mips_opts.warn_about_macros |
fb251650 | 4407 | : 0)), |
f59fb6ca | 4408 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4409 | (char *) NULL); |
4410 | } | |
4411 | else if (expr1.X_add_number >= -0x8000 | |
4412 | && expr1.X_add_number < 0x8000) | |
4413 | { | |
4414 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4415 | "nop", ""); | |
4416 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4417 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4418 | || mips_opts.isa < 3) | |
4419 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4420 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4421 | ||
4422 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4423 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4424 | (breg == 0 | |
3c83da8a | 4425 | ? mips_opts.warn_about_macros |
fb251650 | 4426 | : 0)), |
f59fb6ca | 4427 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4428 | (char *) NULL); |
4429 | } | |
4430 | else | |
4431 | { | |
4432 | int adj, dreg; | |
4433 | ||
4434 | /* If we are going to add in a base register, and the | |
4435 | target register and the base register are the same, | |
4436 | then we are using AT as a temporary register. Since | |
4437 | we want to load the constant into AT, we add our | |
4438 | current AT (from the global offset table) and the | |
4439 | register into the register now, and pretend we were | |
4440 | not using a base register. */ | |
4441 | if (breg != treg) | |
4442 | { | |
4443 | adj = 0; | |
4444 | dreg = tempreg; | |
4445 | } | |
4446 | else | |
4447 | { | |
4448 | assert (tempreg == AT); | |
4449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4450 | "nop", ""); | |
4451 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4452 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4453 | || mips_opts.isa < 3) | |
4454 | ? "addu" : "daddu"), | |
fb251650 ILT |
4455 | "d,v,t", treg, AT, breg); |
4456 | dreg = treg; | |
4457 | adj = 8; | |
4458 | } | |
4459 | ||
4460 | /* Set mips_optimize around the lui instruction to avoid | |
4461 | inserting an unnecessary nop after the lw. */ | |
4462 | hold_mips_optimize = mips_optimize; | |
4463 | mips_optimize = 2; | |
4464 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4465 | mips_optimize = hold_mips_optimize; | |
4466 | ||
4467 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4468 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4469 | || mips_opts.isa < 3) | |
4470 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4471 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4472 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4473 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4474 | || mips_opts.isa < 3) | |
4475 | ? "addu" : "daddu"), | |
fb251650 ILT |
4476 | "d,v,t", dreg, dreg, AT); |
4477 | ||
4478 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4479 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4480 | 8 + gpdel, 0, | |
4481 | (breg == 0 | |
3c83da8a | 4482 | ? mips_opts.warn_about_macros |
fb251650 | 4483 | : 0)), |
f59fb6ca | 4484 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4485 | (char *) NULL); |
4486 | ||
4487 | used_at = 1; | |
4488 | } | |
4489 | ||
4490 | if (gpdel > 0) | |
4491 | { | |
4492 | /* This is needed because this instruction uses $gp, but | |
4493 | the first instruction on the main stream does not. */ | |
4494 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4495 | p += 4; | |
4496 | } | |
4497 | macro_build (p, &icnt, &offset_expr, | |
4498 | dbl ? "ld" : "lw", | |
4499 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4500 | p += 4; | |
4501 | if (expr1.X_add_number >= -0x8000 | |
4502 | && expr1.X_add_number < 0x8000) | |
4503 | { | |
4504 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4505 | p += 4; | |
4506 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4507 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4508 | || mips_opts.isa < 3) | |
4509 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4510 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4511 | /* FIXME: If add_number is 0, and there was no base | |
4512 | register, the external symbol case ended with a load, | |
4513 | so if the symbol turns out to not be external, and | |
4514 | the next instruction uses tempreg, an unnecessary nop | |
4515 | will be inserted. */ | |
4516 | } | |
4517 | else | |
4518 | { | |
4519 | if (breg == treg) | |
4520 | { | |
4521 | /* We must add in the base register now, as in the | |
4522 | external symbol case. */ | |
4523 | assert (tempreg == AT); | |
4524 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4525 | p += 4; | |
4526 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4527 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4528 | || mips_opts.isa < 3) | |
4529 | ? "addu" : "daddu"), | |
fb251650 ILT |
4530 | "d,v,t", treg, AT, breg); |
4531 | p += 4; | |
4532 | tempreg = treg; | |
4533 | /* We set breg to 0 because we have arranged to add | |
4534 | it in in both cases. */ | |
4535 | breg = 0; | |
4536 | } | |
4537 | ||
4538 | macro_build_lui (p, &icnt, &expr1, AT); | |
4539 | p += 4; | |
4540 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4541 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4542 | || mips_opts.isa < 3) | |
4543 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4544 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4545 | p += 4; | |
4546 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4547 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4548 | || mips_opts.isa < 3) | |
4549 | ? "addu" : "daddu"), | |
fb251650 ILT |
4550 | "d,v,t", tempreg, tempreg, AT); |
4551 | p += 4; | |
4552 | } | |
4553 | } | |
d9aba805 ILT |
4554 | else if (mips_pic == EMBEDDED_PIC) |
4555 | { | |
4556 | /* We use | |
4557 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4558 | */ | |
4559 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4560 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4561 | || mips_opts.isa < 3) | |
4562 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4563 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4564 | } | |
4565 | else | |
4566 | abort (); | |
0dd2d296 | 4567 | |
670a50eb | 4568 | if (breg != 0) |
0dd2d296 | 4569 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4570 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4571 | || mips_opts.isa < 3) | |
4572 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4573 | "d,v,t", treg, tempreg, breg); |
4574 | ||
4575 | if (! used_at) | |
4576 | return; | |
4577 | ||
4578 | break; | |
4579 | ||
4580 | case M_J_A: | |
4581 | /* The j instruction may not be used in PIC code, since it | |
4582 | requires an absolute address. We convert it to a b | |
4583 | instruction. */ | |
d9aba805 | 4584 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4585 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4586 | else | |
4587 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4588 | return; |
3d3c5039 | 4589 | |
9226253a ILT |
4590 | /* The jal instructions must be handled as macros because when |
4591 | generating PIC code they expand to multi-instruction | |
4592 | sequences. Normally they are simple instructions. */ | |
4593 | case M_JAL_1: | |
4594 | dreg = RA; | |
4595 | /* Fall through. */ | |
4596 | case M_JAL_2: | |
d9aba805 ILT |
4597 | if (mips_pic == NO_PIC |
4598 | || mips_pic == EMBEDDED_PIC) | |
4599 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4600 | "d,s", dreg, sreg); | |
4601 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4602 | { |
d9aba805 ILT |
4603 | if (sreg != PIC_CALL_REG) |
4604 | as_warn ("MIPS PIC call to register other than $25"); | |
4605 | ||
0dd2d296 ILT |
4606 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4607 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4608 | if (mips_cprestore_offset < 0) |
4609 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4610 | else | |
4611 | { | |
4612 | expr1.X_add_number = mips_cprestore_offset; | |
4613 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4614 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4615 | || mips_opts.isa < 3) | |
4616 | ? "lw" : "ld"), | |
d9aba805 ILT |
4617 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4618 | } | |
9226253a | 4619 | } |
0dd2d296 | 4620 | else |
d9aba805 ILT |
4621 | abort (); |
4622 | ||
9226253a ILT |
4623 | return; |
4624 | ||
4625 | case M_JAL_A: | |
d9aba805 ILT |
4626 | if (mips_pic == NO_PIC) |
4627 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4628 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4629 | { |
fb251650 ILT |
4630 | /* If this is a reference to an external symbol, and we are |
4631 | using a small GOT, we want | |
d9aba805 ILT |
4632 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4633 | nop | |
4634 | jalr $25 | |
4635 | nop | |
4636 | lw $gp,cprestore($sp) | |
4637 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4638 | pseudo-op. If we are using a big GOT, we want |
4639 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4640 | addu $25,$25,$gp | |
4641 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4642 | nop | |
4643 | jalr $25 | |
4644 | nop | |
4645 | lw $gp,cprestore($sp) | |
4646 | If the symbol is not external, we want | |
d9aba805 ILT |
4647 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4648 | nop | |
4649 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4650 | jalr $25 | |
4651 | nop | |
fb251650 ILT |
4652 | lw $gp,cprestore($sp) */ |
4653 | frag_grow (40); | |
4654 | if (! mips_big_got) | |
4655 | { | |
4656 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4657 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4658 | || mips_opts.isa < 3) | |
4659 | ? "lw" : "ld"), | |
fb251650 ILT |
4660 | "t,o(b)", PIC_CALL_REG, |
4661 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4662 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4663 | "nop", ""); | |
4664 | p = frag_var (rs_machine_dependent, 4, 0, | |
4665 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4666 | offset_expr.X_add_symbol, (offsetT) 0, |
4667 | (char *) NULL); | |
fb251650 ILT |
4668 | } |
4669 | else | |
4670 | { | |
4671 | int gpdel; | |
4672 | ||
4673 | if (reg_needs_delay (GP)) | |
4674 | gpdel = 4; | |
4675 | else | |
4676 | gpdel = 0; | |
4677 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4678 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4679 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4680 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4681 | || mips_opts.isa < 3) | |
4682 | ? "addu" : "daddu"), | |
fb251650 ILT |
4683 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4684 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4685 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4686 | || mips_opts.isa < 3) | |
4687 | ? "lw" : "ld"), | |
fb251650 ILT |
4688 | "t,o(b)", PIC_CALL_REG, |
4689 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4690 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4691 | "nop", ""); | |
4692 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4693 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4694 | 0, 0), | |
f59fb6ca ILT |
4695 | offset_expr.X_add_symbol, (offsetT) 0, |
4696 | (char *) NULL); | |
fb251650 ILT |
4697 | if (gpdel > 0) |
4698 | { | |
4699 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4700 | p += 4; | |
4701 | } | |
4702 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4703 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4704 | || mips_opts.isa < 3) | |
4705 | ? "lw" : "ld"), | |
fb251650 ILT |
4706 | "t,o(b)", PIC_CALL_REG, |
4707 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4708 | p += 4; | |
4709 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4710 | p += 4; | |
4711 | } | |
d9aba805 | 4712 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4713 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4714 | || mips_opts.isa < 3) | |
4715 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4716 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4717 | (int) BFD_RELOC_LO16); | |
4718 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4719 | "jalr", "s", PIC_CALL_REG); | |
4720 | if (mips_cprestore_offset < 0) | |
4721 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4722 | else | |
4723 | { | |
3c83da8a | 4724 | if (mips_opts.noreorder) |
d9aba805 ILT |
4725 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4726 | "nop", ""); | |
4727 | expr1.X_add_number = mips_cprestore_offset; | |
4728 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4729 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4730 | || mips_opts.isa < 3) | |
4731 | ? "lw" : "ld"), | |
d9aba805 ILT |
4732 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4733 | mips_frame_reg); | |
4734 | } | |
0dd2d296 | 4735 | } |
d9aba805 | 4736 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4737 | { |
4738 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4739 | /* The linker may expand the call to a longer sequence which | |
4740 | uses $at, so we must break rather than return. */ | |
4741 | break; | |
4742 | } | |
d9aba805 ILT |
4743 | else |
4744 | abort (); | |
4745 | ||
9226253a ILT |
4746 | return; |
4747 | ||
3d3c5039 | 4748 | case M_LB_AB: |
670a50eb ILT |
4749 | s = "lb"; |
4750 | goto ld; | |
3d3c5039 | 4751 | case M_LBU_AB: |
670a50eb ILT |
4752 | s = "lbu"; |
4753 | goto ld; | |
3d3c5039 | 4754 | case M_LH_AB: |
670a50eb ILT |
4755 | s = "lh"; |
4756 | goto ld; | |
3d3c5039 | 4757 | case M_LHU_AB: |
670a50eb ILT |
4758 | s = "lhu"; |
4759 | goto ld; | |
3d3c5039 | 4760 | case M_LW_AB: |
670a50eb ILT |
4761 | s = "lw"; |
4762 | goto ld; | |
3d3c5039 | 4763 | case M_LWC0_AB: |
670a50eb | 4764 | s = "lwc0"; |
efec4a28 | 4765 | /* Itbl support may require additional care here. */ |
8358c818 | 4766 | coproc = 1; |
670a50eb | 4767 | goto ld; |
3d3c5039 | 4768 | case M_LWC1_AB: |
670a50eb | 4769 | s = "lwc1"; |
efec4a28 | 4770 | /* Itbl support may require additional care here. */ |
8358c818 | 4771 | coproc = 1; |
670a50eb | 4772 | goto ld; |
3d3c5039 | 4773 | case M_LWC2_AB: |
670a50eb | 4774 | s = "lwc2"; |
efec4a28 | 4775 | /* Itbl support may require additional care here. */ |
8358c818 | 4776 | coproc = 1; |
670a50eb | 4777 | goto ld; |
3d3c5039 | 4778 | case M_LWC3_AB: |
670a50eb | 4779 | s = "lwc3"; |
efec4a28 | 4780 | /* Itbl support may require additional care here. */ |
8358c818 | 4781 | coproc = 1; |
670a50eb | 4782 | goto ld; |
3d3c5039 | 4783 | case M_LWL_AB: |
670a50eb | 4784 | s = "lwl"; |
b2b8c24e | 4785 | lr = 1; |
670a50eb | 4786 | goto ld; |
3d3c5039 | 4787 | case M_LWR_AB: |
670a50eb | 4788 | s = "lwr"; |
b2b8c24e | 4789 | lr = 1; |
8358c818 ILT |
4790 | goto ld; |
4791 | case M_LDC1_AB: | |
1c6f3441 ILT |
4792 | if (mips_4650) |
4793 | { | |
4794 | as_bad ("opcode not supported on this processor"); | |
4795 | return; | |
4796 | } | |
8358c818 | 4797 | s = "ldc1"; |
efec4a28 | 4798 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4799 | coproc = 1; |
4800 | goto ld; | |
4801 | case M_LDC2_AB: | |
4802 | s = "ldc2"; | |
efec4a28 | 4803 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4804 | coproc = 1; |
4805 | goto ld; | |
4806 | case M_LDC3_AB: | |
4807 | s = "ldc3"; | |
efec4a28 | 4808 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4809 | coproc = 1; |
4810 | goto ld; | |
4811 | case M_LDL_AB: | |
4812 | s = "ldl"; | |
b2b8c24e | 4813 | lr = 1; |
8358c818 ILT |
4814 | goto ld; |
4815 | case M_LDR_AB: | |
4816 | s = "ldr"; | |
b2b8c24e | 4817 | lr = 1; |
8358c818 ILT |
4818 | goto ld; |
4819 | case M_LL_AB: | |
4820 | s = "ll"; | |
4821 | goto ld; | |
4822 | case M_LLD_AB: | |
4823 | s = "lld"; | |
4824 | goto ld; | |
4825 | case M_LWU_AB: | |
4826 | s = "lwu"; | |
3d3c5039 | 4827 | ld: |
b2b8c24e | 4828 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4829 | { |
4830 | tempreg = AT; | |
4831 | used_at = 1; | |
4832 | } | |
4833 | else | |
4834 | { | |
4835 | tempreg = treg; | |
4836 | used_at = 0; | |
4837 | } | |
4838 | goto ld_st; | |
3d3c5039 | 4839 | case M_SB_AB: |
670a50eb ILT |
4840 | s = "sb"; |
4841 | goto st; | |
3d3c5039 | 4842 | case M_SH_AB: |
670a50eb ILT |
4843 | s = "sh"; |
4844 | goto st; | |
3d3c5039 | 4845 | case M_SW_AB: |
670a50eb ILT |
4846 | s = "sw"; |
4847 | goto st; | |
3d3c5039 | 4848 | case M_SWC0_AB: |
670a50eb | 4849 | s = "swc0"; |
efec4a28 | 4850 | /* Itbl support may require additional care here. */ |
8358c818 | 4851 | coproc = 1; |
670a50eb | 4852 | goto st; |
3d3c5039 | 4853 | case M_SWC1_AB: |
670a50eb | 4854 | s = "swc1"; |
efec4a28 | 4855 | /* Itbl support may require additional care here. */ |
8358c818 | 4856 | coproc = 1; |
670a50eb | 4857 | goto st; |
3d3c5039 | 4858 | case M_SWC2_AB: |
670a50eb | 4859 | s = "swc2"; |
efec4a28 | 4860 | /* Itbl support may require additional care here. */ |
8358c818 | 4861 | coproc = 1; |
670a50eb | 4862 | goto st; |
3d3c5039 | 4863 | case M_SWC3_AB: |
670a50eb | 4864 | s = "swc3"; |
efec4a28 | 4865 | /* Itbl support may require additional care here. */ |
8358c818 | 4866 | coproc = 1; |
670a50eb | 4867 | goto st; |
3d3c5039 | 4868 | case M_SWL_AB: |
670a50eb ILT |
4869 | s = "swl"; |
4870 | goto st; | |
3d3c5039 | 4871 | case M_SWR_AB: |
670a50eb | 4872 | s = "swr"; |
8358c818 ILT |
4873 | goto st; |
4874 | case M_SC_AB: | |
4875 | s = "sc"; | |
4876 | goto st; | |
4877 | case M_SCD_AB: | |
4878 | s = "scd"; | |
4879 | goto st; | |
4880 | case M_SDC1_AB: | |
1c6f3441 ILT |
4881 | if (mips_4650) |
4882 | { | |
4883 | as_bad ("opcode not supported on this processor"); | |
4884 | return; | |
4885 | } | |
8358c818 ILT |
4886 | s = "sdc1"; |
4887 | coproc = 1; | |
efec4a28 | 4888 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4889 | goto st; |
4890 | case M_SDC2_AB: | |
4891 | s = "sdc2"; | |
efec4a28 | 4892 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4893 | coproc = 1; |
4894 | goto st; | |
4895 | case M_SDC3_AB: | |
4896 | s = "sdc3"; | |
efec4a28 | 4897 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4898 | coproc = 1; |
4899 | goto st; | |
4900 | case M_SDL_AB: | |
4901 | s = "sdl"; | |
4902 | goto st; | |
4903 | case M_SDR_AB: | |
4904 | s = "sdr"; | |
3d3c5039 | 4905 | st: |
670a50eb ILT |
4906 | tempreg = AT; |
4907 | used_at = 1; | |
3d3c5039 | 4908 | ld_st: |
efec4a28 | 4909 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4910 | if (mask == M_LWC1_AB |
4911 | || mask == M_SWC1_AB | |
8358c818 | 4912 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4913 | || mask == M_SDC1_AB |
4914 | || mask == M_L_DAB | |
4915 | || mask == M_S_DAB) | |
670a50eb | 4916 | fmt = "T,o(b)"; |
8358c818 | 4917 | else if (coproc) |
19ed8960 | 4918 | fmt = "E,o(b)"; |
670a50eb ILT |
4919 | else |
4920 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4921 | |
4922 | if (offset_expr.X_op != O_constant | |
4923 | && offset_expr.X_op != O_symbol) | |
4924 | { | |
4925 | as_bad ("expression too complex"); | |
4926 | offset_expr.X_op = O_constant; | |
4927 | } | |
4928 | ||
4929 | /* A constant expression in PIC code can be handled just as it | |
4930 | is in non PIC code. */ | |
d9aba805 | 4931 | if (mips_pic == NO_PIC |
0dd2d296 | 4932 | || offset_expr.X_op == O_constant) |
670a50eb | 4933 | { |
0dd2d296 ILT |
4934 | /* If this is a reference to a GP relative symbol, and there |
4935 | is no base register, we want | |
4936 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4937 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4938 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4939 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4940 | If we have a constant, we need two instructions anyhow, | |
4941 | so we always use the latter form. | |
4942 | ||
4943 | If we have a base register, and this is a reference to a | |
4944 | GP relative symbol, we want | |
4945 | addu $tempreg,$breg,$gp | |
4946 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4947 | Otherwise we want | |
4948 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4949 | addu $tempreg,$tempreg,$breg | |
4950 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4951 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4952 | if (breg == 0) |
4953 | { | |
7a15a226 | 4954 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4955 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4956 | p = NULL; |
4957 | else | |
4958 | { | |
8ea7f4e8 | 4959 | frag_grow (20); |
0dd2d296 ILT |
4960 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4961 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4962 | p = frag_var (rs_machine_dependent, 8, 0, | |
4963 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
4964 | (mips_opts.warn_about_macros |
4965 | || (used_at | |
4966 | && mips_opts.noat))), | |
f59fb6ca | 4967 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4968 | (char *) NULL); |
8197b589 | 4969 | used_at = 0; |
0dd2d296 ILT |
4970 | } |
4971 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4972 | if (p != NULL) | |
4973 | p += 4; | |
4974 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4975 | (int) BFD_RELOC_LO16, tempreg); | |
4976 | } | |
4977 | else | |
4978 | { | |
7a15a226 | 4979 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4980 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4981 | p = NULL; |
4982 | else | |
4983 | { | |
8ea7f4e8 | 4984 | frag_grow (28); |
0dd2d296 | 4985 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4986 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4987 | || mips_opts.isa < 3) | |
4988 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4989 | "d,v,t", tempreg, breg, GP); |
4990 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4991 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4992 | p = frag_var (rs_machine_dependent, 12, 0, | |
4993 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4994 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4995 | (char *) NULL); |
4996 | } | |
4997 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4998 | if (p != NULL) | |
4999 | p += 4; | |
5000 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5001 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5002 | || mips_opts.isa < 3) | |
5003 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5004 | "d,v,t", tempreg, tempreg, breg); |
5005 | if (p != NULL) | |
5006 | p += 4; | |
5007 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5008 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5009 | } |
670a50eb | 5010 | } |
fb251650 | 5011 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5012 | { |
0dd2d296 ILT |
5013 | /* If this is a reference to an external symbol, we want |
5014 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5015 | nop | |
5016 | <op> $treg,0($tempreg) | |
5017 | Otherwise we want | |
5018 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5019 | nop | |
5020 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5021 | <op> $treg,0($tempreg) | |
5022 | If there is a base register, we add it to $tempreg before | |
5023 | the <op>. If there is a constant, we stick it in the | |
5024 | <op> instruction. We don't handle constants larger than | |
5025 | 16 bits, because we have no way to load the upper 16 bits | |
5026 | (actually, we could handle them for the subset of cases | |
5027 | in which we are not using $at). */ | |
5028 | assert (offset_expr.X_op == O_symbol); | |
5029 | expr1.X_add_number = offset_expr.X_add_number; | |
5030 | offset_expr.X_add_number = 0; | |
5031 | if (expr1.X_add_number < -0x8000 | |
5032 | || expr1.X_add_number >= 0x8000) | |
5033 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 5034 | frag_grow (20); |
0dd2d296 | 5035 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5036 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5037 | || mips_opts.isa < 3) | |
5038 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5039 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5040 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5041 | p = frag_var (rs_machine_dependent, 4, 0, | |
5042 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5043 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5044 | (char *) NULL); |
5045 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5046 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5047 | || mips_opts.isa < 3) | |
5048 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5049 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5050 | if (breg != 0) |
0dd2d296 | 5051 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5052 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5053 | || mips_opts.isa < 3) | |
5054 | ? "addu" : "daddu"), | |
6e8dda9c | 5055 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5056 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5057 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5058 | } |
fb251650 ILT |
5059 | else if (mips_pic == SVR4_PIC) |
5060 | { | |
5061 | int gpdel; | |
5062 | ||
5063 | /* If this is a reference to an external symbol, we want | |
5064 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5065 | addu $tempreg,$tempreg,$gp | |
5066 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5067 | <op> $treg,0($tempreg) | |
5068 | Otherwise we want | |
5069 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5070 | nop | |
5071 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5072 | <op> $treg,0($tempreg) | |
5073 | If there is a base register, we add it to $tempreg before | |
5074 | the <op>. If there is a constant, we stick it in the | |
5075 | <op> instruction. We don't handle constants larger than | |
5076 | 16 bits, because we have no way to load the upper 16 bits | |
5077 | (actually, we could handle them for the subset of cases | |
5078 | in which we are not using $at). */ | |
5079 | assert (offset_expr.X_op == O_symbol); | |
5080 | expr1.X_add_number = offset_expr.X_add_number; | |
5081 | offset_expr.X_add_number = 0; | |
5082 | if (expr1.X_add_number < -0x8000 | |
5083 | || expr1.X_add_number >= 0x8000) | |
5084 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5085 | if (reg_needs_delay (GP)) | |
5086 | gpdel = 4; | |
5087 | else | |
5088 | gpdel = 0; | |
5089 | frag_grow (36); | |
5090 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5091 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5092 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5093 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5094 | || mips_opts.isa < 3) | |
5095 | ? "addu" : "daddu"), | |
fb251650 ILT |
5096 | "d,v,t", tempreg, tempreg, GP); |
5097 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5098 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5099 | || mips_opts.isa < 3) | |
5100 | ? "lw" : "ld"), | |
867a58b3 ILT |
5101 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5102 | tempreg); | |
fb251650 ILT |
5103 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5104 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5105 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5106 | if (gpdel > 0) |
5107 | { | |
5108 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5109 | p += 4; | |
5110 | } | |
5111 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5112 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5113 | || mips_opts.isa < 3) | |
5114 | ? "lw" : "ld"), | |
867a58b3 | 5115 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5116 | p += 4; |
5117 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5118 | p += 4; | |
5119 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5120 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5121 | || mips_opts.isa < 3) | |
5122 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5123 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5124 | if (breg != 0) | |
5125 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5126 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5127 | || mips_opts.isa < 3) | |
5128 | ? "addu" : "daddu"), | |
fb251650 ILT |
5129 | "d,v,t", tempreg, tempreg, breg); |
5130 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5131 | (int) BFD_RELOC_LO16, tempreg); | |
5132 | } | |
d9aba805 ILT |
5133 | else if (mips_pic == EMBEDDED_PIC) |
5134 | { | |
5135 | /* If there is no base register, we want | |
5136 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5137 | If there is a base register, we want | |
5138 | addu $tempreg,$breg,$gp | |
5139 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5140 | */ | |
5141 | assert (offset_expr.X_op == O_symbol); | |
5142 | if (breg == 0) | |
5143 | { | |
5144 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5145 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5146 | used_at = 0; | |
5147 | } | |
5148 | else | |
5149 | { | |
5150 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5151 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5152 | || mips_opts.isa < 3) | |
5153 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5154 | "d,v,t", tempreg, breg, GP); |
5155 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5156 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5157 | } | |
5158 | } | |
5159 | else | |
5160 | abort (); | |
0dd2d296 ILT |
5161 | |
5162 | if (! used_at) | |
5163 | return; | |
5164 | ||
5165 | break; | |
3d3c5039 ILT |
5166 | |
5167 | case M_LI: | |
19ed8960 | 5168 | case M_LI_S: |
d8a1c247 KR |
5169 | load_register (&icnt, treg, &imm_expr, 0); |
5170 | return; | |
5171 | ||
5172 | case M_DLI: | |
5173 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5174 | return; |
3d3c5039 | 5175 | |
0dd2d296 | 5176 | case M_LI_SS: |
55933a58 | 5177 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5178 | { |
d8a1c247 | 5179 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5180 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5181 | "mtc1", "t,G", AT, treg); | |
5182 | break; | |
0dd2d296 | 5183 | } |
d9aba805 | 5184 | else |
d2c71068 | 5185 | { |
55933a58 ILT |
5186 | assert (offset_expr.X_op == O_symbol |
5187 | && strcmp (segment_name (S_GET_SEGMENT | |
5188 | (offset_expr.X_add_symbol)), | |
5189 | ".lit4") == 0 | |
5190 | && offset_expr.X_add_number == 0); | |
5191 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5192 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5193 | return; |
5194 | } | |
0dd2d296 | 5195 | |
3d3c5039 | 5196 | case M_LI_D: |
a5586bdc ILT |
5197 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5198 | the entire value, and in mips1 mode it is the high order 32 | |
5199 | bits of the value and the low order 32 bits are either zero | |
5200 | or in offset_expr. */ | |
5201 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5202 | { | |
517640d9 ILT |
5203 | if (mips_opts.isa >= 3) |
5204 | load_register (&icnt, treg, &imm_expr, 1); | |
5205 | else | |
a5586bdc | 5206 | { |
517640d9 ILT |
5207 | int hreg, lreg; |
5208 | ||
5209 | if (target_big_endian) | |
5210 | { | |
5211 | hreg = treg; | |
5212 | lreg = treg + 1; | |
5213 | } | |
a5586bdc ILT |
5214 | else |
5215 | { | |
517640d9 ILT |
5216 | hreg = treg + 1; |
5217 | lreg = treg; | |
5218 | } | |
5219 | ||
5220 | if (hreg <= 31) | |
5221 | load_register (&icnt, hreg, &imm_expr, 0); | |
5222 | if (lreg <= 31) | |
5223 | { | |
5224 | if (offset_expr.X_op == O_absent) | |
5225 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5226 | lreg, 0); | |
5227 | else | |
5228 | { | |
5229 | assert (offset_expr.X_op == O_constant); | |
5230 | load_register (&icnt, lreg, &offset_expr, 0); | |
5231 | } | |
a5586bdc ILT |
5232 | } |
5233 | } | |
5234 | return; | |
5235 | } | |
5236 | ||
d9aba805 ILT |
5237 | /* We know that sym is in the .rdata section. First we get the |
5238 | upper 16 bits of the address. */ | |
5239 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5240 | { |
5241 | /* FIXME: This won't work for a 64 bit address. */ | |
5242 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5243 | } | |
d9aba805 | 5244 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5245 | { |
5246 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5247 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5248 | || mips_opts.isa < 3) | |
5249 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5250 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5251 | } | |
d9aba805 ILT |
5252 | else if (mips_pic == EMBEDDED_PIC) |
5253 | { | |
5254 | /* For embedded PIC we pick up the entire address off $gp in | |
5255 | a single instruction. */ | |
5256 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5257 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5258 | || mips_opts.isa < 3) | |
5259 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5260 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5261 | offset_expr.X_op = O_constant; | |
5262 | offset_expr.X_add_number = 0; | |
5263 | } | |
5264 | else | |
5265 | abort (); | |
5266 | ||
0dd2d296 | 5267 | /* Now we load the register(s). */ |
3c83da8a | 5268 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5269 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5270 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5271 | else |
5272 | { | |
0dd2d296 ILT |
5273 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5274 | treg, (int) BFD_RELOC_LO16, AT); | |
5275 | if (treg != 31) | |
5276 | { | |
5277 | /* FIXME: How in the world do we deal with the possible | |
5278 | overflow here? */ | |
5279 | offset_expr.X_add_number += 4; | |
5280 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5281 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5282 | } | |
8358c818 | 5283 | } |
d2c71068 ILT |
5284 | |
5285 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5286 | does not become a variant frag. */ | |
5287 | frag_wane (frag_now); | |
5288 | frag_new (0); | |
5289 | ||
670a50eb | 5290 | break; |
3d3c5039 ILT |
5291 | |
5292 | case M_LI_DD: | |
a5586bdc ILT |
5293 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5294 | the entire value, and in mips1 mode it is the high order 32 | |
5295 | bits of the value and the low order 32 bits are either zero | |
5296 | or in offset_expr. */ | |
5297 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5298 | { | |
5299 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5300 | if (mips_opts.isa >= 3) | |
5301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5302 | "dmtc1", "t,S", AT, treg); | |
5303 | else | |
5304 | { | |
5305 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5306 | "mtc1", "t,G", AT, treg + 1); | |
5307 | if (offset_expr.X_op == O_absent) | |
5308 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5309 | "mtc1", "t,G", 0, treg); | |
5310 | else | |
5311 | { | |
5312 | assert (offset_expr.X_op == O_constant); | |
5313 | load_register (&icnt, AT, &offset_expr, 0); | |
5314 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5315 | "mtc1", "t,G", AT, treg); | |
5316 | } | |
5317 | } | |
5318 | break; | |
5319 | } | |
5320 | ||
55933a58 ILT |
5321 | assert (offset_expr.X_op == O_symbol |
5322 | && offset_expr.X_add_number == 0); | |
5323 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5324 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5325 | { |
3c83da8a | 5326 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5327 | { |
5328 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5329 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5330 | return; | |
5331 | } | |
5332 | breg = GP; | |
5333 | r = BFD_RELOC_MIPS_LITERAL; | |
5334 | goto dob; | |
5335 | } | |
55933a58 | 5336 | else |
0dd2d296 | 5337 | { |
55933a58 ILT |
5338 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5339 | if (mips_pic == SVR4_PIC) | |
5340 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5341 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5342 | || mips_opts.isa < 3) | |
5343 | ? "lw" : "ld"), | |
55933a58 ILT |
5344 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5345 | else | |
5346 | { | |
5347 | /* FIXME: This won't work for a 64 bit address. */ | |
5348 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5349 | } | |
5350 | ||
3c83da8a | 5351 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5352 | { |
5353 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5354 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5355 | |
5356 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5357 | that this does not become a variant frag. */ | |
5358 | frag_wane (frag_now); | |
5359 | frag_new (0); | |
5360 | ||
0dd2d296 ILT |
5361 | break; |
5362 | } | |
5363 | breg = AT; | |
5364 | r = BFD_RELOC_LO16; | |
5365 | goto dob; | |
8358c818 | 5366 | } |
9226253a | 5367 | |
3d3c5039 | 5368 | case M_L_DOB: |
1c6f3441 ILT |
5369 | if (mips_4650) |
5370 | { | |
5371 | as_bad ("opcode not supported on this processor"); | |
5372 | return; | |
5373 | } | |
9a7d824a ILT |
5374 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5375 | to adjust when loading from memory. */ | |
9226253a ILT |
5376 | r = BFD_RELOC_LO16; |
5377 | dob: | |
3c83da8a | 5378 | assert (mips_opts.isa < 2); |
0dd2d296 | 5379 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5380 | target_big_endian ? treg + 1 : treg, |
9226253a | 5381 | (int) r, breg); |
0dd2d296 ILT |
5382 | /* FIXME: A possible overflow which I don't know how to deal |
5383 | with. */ | |
670a50eb | 5384 | offset_expr.X_add_number += 4; |
0dd2d296 | 5385 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5386 | target_big_endian ? treg : treg + 1, |
9226253a | 5387 | (int) r, breg); |
d2c71068 ILT |
5388 | |
5389 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5390 | does not become a variant frag. */ | |
5391 | frag_wane (frag_now); | |
5392 | frag_new (0); | |
5393 | ||
0dd2d296 ILT |
5394 | if (breg != AT) |
5395 | return; | |
5396 | break; | |
3d3c5039 ILT |
5397 | |
5398 | case M_L_DAB: | |
670a50eb ILT |
5399 | /* |
5400 | * The MIPS assembler seems to check for X_add_number not | |
5401 | * being double aligned and generating: | |
5402 | * lui at,%hi(foo+1) | |
5403 | * addu at,at,v1 | |
5404 | * addiu at,at,%lo(foo+1) | |
5405 | * lwc1 f2,0(at) | |
5406 | * lwc1 f3,4(at) | |
5407 | * But, the resulting address is the same after relocation so why | |
5408 | * generate the extra instruction? | |
5409 | */ | |
1c6f3441 ILT |
5410 | if (mips_4650) |
5411 | { | |
5412 | as_bad ("opcode not supported on this processor"); | |
5413 | return; | |
5414 | } | |
efec4a28 | 5415 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5416 | coproc = 1; |
3c83da8a | 5417 | if (mips_opts.isa >= 2) |
670a50eb | 5418 | { |
0dd2d296 ILT |
5419 | s = "ldc1"; |
5420 | goto ld; | |
670a50eb | 5421 | } |
0dd2d296 ILT |
5422 | |
5423 | s = "lwc1"; | |
5424 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5425 | goto ldd_std; |
5426 | ||
5427 | case M_S_DAB: | |
1c6f3441 ILT |
5428 | if (mips_4650) |
5429 | { | |
5430 | as_bad ("opcode not supported on this processor"); | |
5431 | return; | |
5432 | } | |
5433 | ||
3c83da8a | 5434 | if (mips_opts.isa >= 2) |
8358c818 | 5435 | { |
0dd2d296 ILT |
5436 | s = "sdc1"; |
5437 | goto st; | |
8358c818 | 5438 | } |
3d3c5039 | 5439 | |
0dd2d296 ILT |
5440 | s = "swc1"; |
5441 | fmt = "T,o(b)"; | |
efec4a28 | 5442 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5443 | coproc = 1; |
5444 | goto ldd_std; | |
3d3c5039 ILT |
5445 | |
5446 | case M_LD_AB: | |
3c83da8a | 5447 | if (mips_opts.isa >= 3) |
670a50eb | 5448 | { |
0dd2d296 ILT |
5449 | s = "ld"; |
5450 | goto ld; | |
670a50eb | 5451 | } |
0dd2d296 ILT |
5452 | |
5453 | s = "lw"; | |
5454 | fmt = "t,o(b)"; | |
5455 | goto ldd_std; | |
5456 | ||
5457 | case M_SD_AB: | |
3c83da8a | 5458 | if (mips_opts.isa >= 3) |
670a50eb | 5459 | { |
0dd2d296 ILT |
5460 | s = "sd"; |
5461 | goto st; | |
670a50eb | 5462 | } |
0dd2d296 | 5463 | |
670a50eb | 5464 | s = "sw"; |
0dd2d296 ILT |
5465 | fmt = "t,o(b)"; |
5466 | ||
5467 | ldd_std: | |
5468 | if (offset_expr.X_op != O_symbol | |
5469 | && offset_expr.X_op != O_constant) | |
670a50eb | 5470 | { |
0dd2d296 ILT |
5471 | as_bad ("expression too complex"); |
5472 | offset_expr.X_op = O_constant; | |
5473 | } | |
5474 | ||
5475 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5476 | to adjust when loading from memory. We set coproc if we must | |
5477 | load $fn+1 first. */ | |
efec4a28 | 5478 | /* Itbl support may require additional care here. */ |
b9129c6f | 5479 | if (! target_big_endian) |
0dd2d296 ILT |
5480 | coproc = 0; |
5481 | ||
d9aba805 | 5482 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5483 | || offset_expr.X_op == O_constant) |
5484 | { | |
5485 | /* If this is a reference to a GP relative symbol, we want | |
5486 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5487 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5488 | If we have a base register, we use this | |
5489 | addu $at,$breg,$gp | |
5490 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5491 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5492 | If this is not a GP relative symbol, we want | |
5493 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5494 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5495 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5496 | If there is a base register, we add it to $at after the | |
5497 | lui instruction. If there is a constant, we always use | |
5498 | the last case. */ | |
7a15a226 | 5499 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5500 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5501 | { |
0dd2d296 ILT |
5502 | p = NULL; |
5503 | used_at = 1; | |
670a50eb ILT |
5504 | } |
5505 | else | |
0dd2d296 ILT |
5506 | { |
5507 | int off; | |
5508 | ||
5509 | if (breg == 0) | |
5510 | { | |
8ea7f4e8 | 5511 | frag_grow (28); |
0dd2d296 ILT |
5512 | tempreg = GP; |
5513 | off = 0; | |
5514 | used_at = 0; | |
5515 | } | |
5516 | else | |
5517 | { | |
8ea7f4e8 | 5518 | frag_grow (36); |
0dd2d296 | 5519 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5520 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5521 | || mips_opts.isa < 3) | |
5522 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5523 | "d,v,t", AT, breg, GP); |
5524 | tempreg = AT; | |
5525 | off = 4; | |
5526 | used_at = 1; | |
5527 | } | |
5528 | ||
efec4a28 | 5529 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5530 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5531 | coproc ? treg + 1 : treg, | |
5532 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5533 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5534 | |
5535 | /* Set mips_optimize to 2 to avoid inserting an | |
5536 | undesired nop. */ | |
5537 | hold_mips_optimize = mips_optimize; | |
5538 | mips_optimize = 2; | |
efec4a28 | 5539 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5540 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5541 | coproc ? treg : treg + 1, | |
5542 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5543 | mips_optimize = hold_mips_optimize; |
5544 | ||
0dd2d296 ILT |
5545 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5546 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5547 | used_at && mips_opts.noat), |
f59fb6ca | 5548 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5549 | (char *) NULL); |
777ad64d ILT |
5550 | |
5551 | /* We just generated two relocs. When tc_gen_reloc | |
5552 | handles this case, it will skip the first reloc and | |
5553 | handle the second. The second reloc already has an | |
5554 | extra addend of 4, which we added above. We must | |
5555 | subtract it out, and then subtract another 4 to make | |
5556 | the first reloc come out right. The second reloc | |
5557 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5558 | offset_expr when we build its instruction below. |
5559 | ||
5560 | If we have a symbol, then we don't want to include | |
5561 | the offset, because it will wind up being included | |
5562 | when we generate the reloc. */ | |
5563 | ||
5564 | if (offset_expr.X_op == O_constant) | |
5565 | offset_expr.X_add_number -= 8; | |
5566 | else | |
5567 | { | |
5568 | offset_expr.X_add_number = -4; | |
5569 | offset_expr.X_op = O_constant; | |
5570 | } | |
0dd2d296 ILT |
5571 | } |
5572 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5573 | if (p != NULL) | |
5574 | p += 4; | |
5575 | if (breg != 0) | |
5576 | { | |
5577 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5578 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5579 | || mips_opts.isa < 3) | |
5580 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5581 | "d,v,t", AT, breg, AT); |
5582 | if (p != NULL) | |
5583 | p += 4; | |
5584 | } | |
efec4a28 | 5585 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5586 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5587 | coproc ? treg + 1 : treg, | |
5588 | (int) BFD_RELOC_LO16, AT); | |
5589 | if (p != NULL) | |
5590 | p += 4; | |
5591 | /* FIXME: How do we handle overflow here? */ | |
5592 | offset_expr.X_add_number += 4; | |
efec4a28 | 5593 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5594 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5595 | coproc ? treg : treg + 1, | |
5596 | (int) BFD_RELOC_LO16, AT); | |
5597 | } | |
fb251650 | 5598 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5599 | { |
0dd2d296 ILT |
5600 | int off; |
5601 | ||
5602 | /* If this is a reference to an external symbol, we want | |
5603 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5604 | nop | |
5605 | <op> $treg,0($at) | |
5606 | <op> $treg+1,4($at) | |
5607 | Otherwise we want | |
5608 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5609 | nop | |
5610 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5611 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5612 | If there is a base register we add it to $at before the | |
5613 | lwc1 instructions. If there is a constant we include it | |
5614 | in the lwc1 instructions. */ | |
5615 | used_at = 1; | |
5616 | expr1.X_add_number = offset_expr.X_add_number; | |
5617 | offset_expr.X_add_number = 0; | |
5618 | if (expr1.X_add_number < -0x8000 | |
5619 | || expr1.X_add_number >= 0x8000 - 4) | |
5620 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5621 | if (breg == 0) | |
5622 | off = 0; | |
5623 | else | |
5624 | off = 4; | |
8ea7f4e8 | 5625 | frag_grow (24 + off); |
0dd2d296 | 5626 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5627 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5628 | || mips_opts.isa < 3) | |
5629 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5630 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5632 | if (breg != 0) |
0dd2d296 | 5633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5634 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5635 | || mips_opts.isa < 3) | |
5636 | ? "addu" : "daddu"), | |
0dd2d296 | 5637 | "d,v,t", AT, breg, AT); |
efec4a28 | 5638 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5639 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5640 | coproc ? treg + 1 : treg, | |
5641 | (int) BFD_RELOC_LO16, AT); | |
5642 | expr1.X_add_number += 4; | |
55933a58 ILT |
5643 | |
5644 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5645 | nop. */ | |
5646 | hold_mips_optimize = mips_optimize; | |
5647 | mips_optimize = 2; | |
efec4a28 | 5648 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5649 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5650 | coproc ? treg : treg + 1, | |
5651 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5652 | mips_optimize = hold_mips_optimize; |
5653 | ||
0dd2d296 ILT |
5654 | (void) frag_var (rs_machine_dependent, 0, 0, |
5655 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5656 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5657 | (char *) NULL); |
8358c818 | 5658 | } |
fb251650 ILT |
5659 | else if (mips_pic == SVR4_PIC) |
5660 | { | |
5661 | int gpdel, off; | |
5662 | ||
5663 | /* If this is a reference to an external symbol, we want | |
5664 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5665 | addu $at,$at,$gp | |
5666 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5667 | nop | |
5668 | <op> $treg,0($at) | |
5669 | <op> $treg+1,4($at) | |
5670 | Otherwise we want | |
5671 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5672 | nop | |
5673 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5674 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5675 | If there is a base register we add it to $at before the | |
5676 | lwc1 instructions. If there is a constant we include it | |
5677 | in the lwc1 instructions. */ | |
5678 | used_at = 1; | |
5679 | expr1.X_add_number = offset_expr.X_add_number; | |
5680 | offset_expr.X_add_number = 0; | |
5681 | if (expr1.X_add_number < -0x8000 | |
5682 | || expr1.X_add_number >= 0x8000 - 4) | |
5683 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5684 | if (reg_needs_delay (GP)) | |
5685 | gpdel = 4; | |
5686 | else | |
5687 | gpdel = 0; | |
5688 | if (breg == 0) | |
5689 | off = 0; | |
5690 | else | |
5691 | off = 4; | |
5692 | frag_grow (56); | |
5693 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5694 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5695 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5696 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5697 | || mips_opts.isa < 3) | |
5698 | ? "addu" : "daddu"), | |
fb251650 ILT |
5699 | "d,v,t", AT, AT, GP); |
5700 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5701 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5702 | || mips_opts.isa < 3) | |
5703 | ? "lw" : "ld"), | |
fb251650 ILT |
5704 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5705 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5706 | if (breg != 0) | |
5707 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5708 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5709 | || mips_opts.isa < 3) | |
5710 | ? "addu" : "daddu"), | |
fb251650 | 5711 | "d,v,t", AT, breg, AT); |
efec4a28 | 5712 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5713 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5714 | coproc ? treg + 1 : treg, | |
5715 | (int) BFD_RELOC_LO16, AT); | |
5716 | expr1.X_add_number += 4; | |
5717 | ||
5718 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5719 | nop. */ | |
5720 | hold_mips_optimize = mips_optimize; | |
5721 | mips_optimize = 2; | |
efec4a28 | 5722 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5723 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5724 | coproc ? treg : treg + 1, | |
5725 | (int) BFD_RELOC_LO16, AT); | |
5726 | mips_optimize = hold_mips_optimize; | |
5727 | expr1.X_add_number -= 4; | |
5728 | ||
5729 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5730 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5731 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5732 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5733 | (char *) NULL); |
5734 | if (gpdel > 0) | |
5735 | { | |
5736 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5737 | p += 4; | |
5738 | } | |
5739 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5740 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5741 | || mips_opts.isa < 3) | |
5742 | ? "lw" : "ld"), | |
fb251650 ILT |
5743 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5744 | p += 4; | |
5745 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5746 | p += 4; | |
5747 | if (breg != 0) | |
5748 | { | |
5749 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5750 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5751 | || mips_opts.isa < 3) | |
5752 | ? "addu" : "daddu"), | |
fb251650 ILT |
5753 | "d,v,t", AT, breg, AT); |
5754 | p += 4; | |
5755 | } | |
efec4a28 | 5756 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5757 | macro_build (p, &icnt, &expr1, s, fmt, |
5758 | coproc ? treg + 1 : treg, | |
5759 | (int) BFD_RELOC_LO16, AT); | |
5760 | p += 4; | |
5761 | expr1.X_add_number += 4; | |
5762 | ||
5763 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5764 | nop. */ | |
5765 | hold_mips_optimize = mips_optimize; | |
5766 | mips_optimize = 2; | |
efec4a28 | 5767 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5768 | macro_build (p, &icnt, &expr1, s, fmt, |
5769 | coproc ? treg : treg + 1, | |
5770 | (int) BFD_RELOC_LO16, AT); | |
5771 | mips_optimize = hold_mips_optimize; | |
5772 | } | |
d9aba805 ILT |
5773 | else if (mips_pic == EMBEDDED_PIC) |
5774 | { | |
5775 | /* If there is no base register, we use | |
5776 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5777 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5778 | If we have a base register, we use | |
5779 | addu $at,$breg,$gp | |
5780 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5781 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5782 | */ | |
5783 | if (breg == 0) | |
5784 | { | |
5785 | tempreg = GP; | |
5786 | used_at = 0; | |
5787 | } | |
5788 | else | |
5789 | { | |
5790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5791 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5792 | || mips_opts.isa < 3) | |
5793 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5794 | "d,v,t", AT, breg, GP); |
5795 | tempreg = AT; | |
5796 | used_at = 1; | |
5797 | } | |
5798 | ||
efec4a28 | 5799 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5800 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5801 | coproc ? treg + 1 : treg, | |
5802 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5803 | offset_expr.X_add_number += 4; | |
efec4a28 | 5804 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5805 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5806 | coproc ? treg : treg + 1, | |
5807 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5808 | } | |
5809 | else | |
5810 | abort (); | |
0dd2d296 ILT |
5811 | |
5812 | if (! used_at) | |
5813 | return; | |
5814 | ||
5815 | break; | |
5816 | ||
5817 | case M_LD_OB: | |
5818 | s = "lw"; | |
5819 | goto sd_ob; | |
5820 | case M_SD_OB: | |
5821 | s = "sw"; | |
5822 | sd_ob: | |
9a1f3160 | 5823 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5824 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5825 | (int) BFD_RELOC_LO16, breg); | |
5826 | offset_expr.X_add_number += 4; | |
5827 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5828 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5829 | return; |
efec4a28 DP |
5830 | |
5831 | /* New code added to support COPZ instructions. | |
5832 | This code builds table entries out of the macros in mip_opcodes. | |
5833 | R4000 uses interlocks to handle coproc delays. | |
5834 | Other chips (like the R3000) require nops to be inserted for delays. | |
5835 | ||
5836 | FIXME: Currently, we require that the user handle delays. | |
5837 | In order to fill delay slots for non-interlocked chips, | |
5838 | we must have a way to specify delays based on the coprocessor. | |
5839 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5840 | What are the side-effects of the cop instruction? | |
5841 | What cache support might we have and what are its effects? | |
5842 | Both coprocessor & memory require delays. how long??? | |
5843 | What registers are read/set/modified? | |
5844 | ||
5845 | If an itbl is provided to interpret cop instructions, | |
5846 | this knowledge can be encoded in the itbl spec. */ | |
5847 | ||
5848 | case M_COP0: | |
65d2c7d3 | 5849 | s = "c0"; |
efec4a28 DP |
5850 | goto copz; |
5851 | case M_COP1: | |
65d2c7d3 | 5852 | s = "c1"; |
efec4a28 DP |
5853 | goto copz; |
5854 | case M_COP2: | |
65d2c7d3 | 5855 | s = "c2"; |
efec4a28 DP |
5856 | goto copz; |
5857 | case M_COP3: | |
65d2c7d3 | 5858 | s = "c3"; |
efec4a28 | 5859 | copz: |
65d2c7d3 JL |
5860 | /* For now we just do C (same as Cz). The parameter will be |
5861 | stored in insn_opcode by mips_ip. */ | |
5862 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5863 | ip->insn_opcode); | |
efec4a28 DP |
5864 | return; |
5865 | ||
917fae09 SS |
5866 | #ifdef LOSING_COMPILER |
5867 | default: | |
efec4a28 DP |
5868 | /* Try and see if this is a new itbl instruction. |
5869 | This code builds table entries out of the macros in mip_opcodes. | |
5870 | FIXME: For now we just assemble the expression and pass it's | |
5871 | value along as a 32-bit immediate. | |
5872 | We may want to have the assembler assemble this value, | |
5873 | so that we gain the assembler's knowledge of delay slots, | |
5874 | symbols, etc. | |
5875 | Would it be more efficient to use mask (id) here? */ | |
5876 | if (itbl_have_entries | |
9218cee0 | 5877 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5878 | { |
5879 | s = ip->insn_mo->name; | |
5880 | s2 = "cop3"; | |
9218cee0 | 5881 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5882 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5883 | return; | |
5884 | } | |
917fae09 SS |
5885 | macro2 (ip); |
5886 | return; | |
5887 | } | |
3c83da8a | 5888 | if (mips_opts.noat) |
917fae09 SS |
5889 | as_warn ("Macro used $at after \".set noat\""); |
5890 | } | |
5891 | ||
5892 | static void | |
5893 | macro2 (ip) | |
5894 | struct mips_cl_insn *ip; | |
5895 | { | |
5896 | register int treg, sreg, dreg, breg; | |
5897 | int tempreg; | |
5898 | int mask; | |
5899 | int icnt = 0; | |
5900 | int used_at; | |
5901 | expressionS expr1; | |
5902 | const char *s; | |
5903 | const char *s2; | |
5904 | const char *fmt; | |
5905 | int likely = 0; | |
5906 | int dbl = 0; | |
5907 | int coproc = 0; | |
adcf2b9d ILT |
5908 | int lr = 0; |
5909 | int off; | |
917fae09 SS |
5910 | offsetT maxnum; |
5911 | bfd_reloc_code_real_type r; | |
5912 | char *p; | |
5913 | ||
5914 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5915 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5916 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5917 | mask = ip->insn_mo->mask; | |
5918 | ||
5919 | expr1.X_op = O_constant; | |
5920 | expr1.X_op_symbol = NULL; | |
5921 | expr1.X_add_symbol = NULL; | |
5922 | expr1.X_add_number = 1; | |
5923 | ||
5924 | switch (mask) | |
5925 | { | |
5926 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5927 | |
8358c818 ILT |
5928 | case M_DMUL: |
5929 | dbl = 1; | |
3d3c5039 | 5930 | case M_MUL: |
0dd2d296 | 5931 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5932 | dbl ? "dmultu" : "multu", |
5933 | "s,t", sreg, treg); | |
0dd2d296 | 5934 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5935 | return; |
3d3c5039 | 5936 | |
8358c818 ILT |
5937 | case M_DMUL_I: |
5938 | dbl = 1; | |
3d3c5039 | 5939 | case M_MUL_I: |
8358c818 ILT |
5940 | /* The MIPS assembler some times generates shifts and adds. I'm |
5941 | not trying to be that fancy. GCC should do this for us | |
5942 | anyway. */ | |
d8a1c247 | 5943 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5944 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5945 | dbl ? "dmult" : "mult", |
5946 | "s,t", sreg, AT); | |
0dd2d296 | 5947 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5948 | break; |
3d3c5039 | 5949 | |
8358c818 ILT |
5950 | case M_DMULO: |
5951 | dbl = 1; | |
5952 | case M_MULO: | |
fbcfacb7 | 5953 | mips_emit_delays (true); |
3c83da8a | 5954 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5955 | mips_any_noreorder = 1; |
5956 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5957 | dbl ? "dmult" : "mult", |
5958 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5959 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5960 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5961 | dbl ? "dsra32" : "sra", |
5962 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5963 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5964 | if (mips_trap) |
5965 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5966 | else | |
5967 | { | |
5968 | expr1.X_add_number = 8; | |
5969 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5970 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5971 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5972 | } | |
3c83da8a | 5973 | --mips_opts.noreorder; |
0dd2d296 | 5974 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5975 | break; |
5976 | ||
5977 | case M_DMULOU: | |
5978 | dbl = 1; | |
5979 | case M_MULOU: | |
fbcfacb7 | 5980 | mips_emit_delays (true); |
3c83da8a | 5981 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5982 | mips_any_noreorder = 1; |
5983 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5984 | dbl ? "dmultu" : "multu", |
5985 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5986 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5987 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5988 | if (mips_trap) |
5989 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5990 | else | |
5991 | { | |
5992 | expr1.X_add_number = 8; | |
5993 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5994 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5995 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5996 | } | |
3c83da8a | 5997 | --mips_opts.noreorder; |
8358c818 ILT |
5998 | break; |
5999 | ||
3d3c5039 | 6000 | case M_ROL: |
0dd2d296 ILT |
6001 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6002 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6003 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6004 | treg); | |
6005 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6006 | break; |
3d3c5039 ILT |
6007 | |
6008 | case M_ROL_I: | |
5c6f5923 GRK |
6009 | if (imm_expr.X_op != O_constant) |
6010 | as_bad ("rotate count too large"); | |
0dd2d296 | 6011 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6012 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6013 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6014 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6015 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6016 | break; |
3d3c5039 ILT |
6017 | |
6018 | case M_ROR: | |
0dd2d296 ILT |
6019 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6020 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6021 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6022 | treg); | |
6023 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6024 | break; |
3d3c5039 ILT |
6025 | |
6026 | case M_ROR_I: | |
5c6f5923 GRK |
6027 | if (imm_expr.X_op != O_constant) |
6028 | as_bad ("rotate count too large"); | |
0dd2d296 | 6029 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6030 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6031 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6032 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6033 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6034 | break; |
3d3c5039 ILT |
6035 | |
6036 | case M_S_DOB: | |
1c6f3441 ILT |
6037 | if (mips_4650) |
6038 | { | |
6039 | as_bad ("opcode not supported on this processor"); | |
6040 | return; | |
6041 | } | |
3c83da8a | 6042 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6043 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6044 | to adjust when storing to memory. */ | |
0dd2d296 | 6045 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6046 | target_big_endian ? treg + 1 : treg, |
9226253a | 6047 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6048 | offset_expr.X_add_number += 4; |
0dd2d296 | 6049 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6050 | target_big_endian ? treg : treg + 1, |
9226253a | 6051 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6052 | return; |
3d3c5039 | 6053 | |
3d3c5039 | 6054 | case M_SEQ: |
670a50eb | 6055 | if (sreg == 0) |
0dd2d296 ILT |
6056 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6057 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6058 | else if (treg == 0) |
0dd2d296 ILT |
6059 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6060 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6061 | else |
6062 | { | |
0dd2d296 ILT |
6063 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6064 | sreg, treg); | |
6065 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6066 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6067 | } |
670a50eb | 6068 | return; |
3d3c5039 ILT |
6069 | |
6070 | case M_SEQ_I: | |
5c6f5923 | 6071 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6072 | { |
0dd2d296 ILT |
6073 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6074 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6075 | return; |
3d3c5039 | 6076 | } |
670a50eb ILT |
6077 | if (sreg == 0) |
6078 | { | |
9a7d824a | 6079 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 6080 | ip->insn_mo->name); |
0dd2d296 | 6081 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6082 | return; |
3d3c5039 | 6083 | } |
5c6f5923 GRK |
6084 | if (imm_expr.X_op == O_constant |
6085 | && imm_expr.X_add_number >= 0 | |
6086 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6087 | { |
0dd2d296 ILT |
6088 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6089 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6090 | used_at = 0; |
6e8dda9c | 6091 | } |
5c6f5923 GRK |
6092 | else if (imm_expr.X_op == O_constant |
6093 | && imm_expr.X_add_number > -0x8000 | |
6094 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6095 | { |
6096 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6097 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6098 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6099 | || mips_opts.isa < 3) | |
6100 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6101 | "t,r,j", dreg, sreg, |
6102 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6103 | used_at = 0; |
6104 | } | |
6105 | else | |
6106 | { | |
d8a1c247 | 6107 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6108 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6109 | sreg, AT); | |
670a50eb ILT |
6110 | used_at = 1; |
6111 | } | |
0dd2d296 | 6112 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6113 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6114 | if (used_at) |
6115 | break; | |
6116 | return; | |
3d3c5039 ILT |
6117 | |
6118 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6119 | s = "slt"; |
6120 | goto sge; | |
3d3c5039 | 6121 | case M_SGEU: |
670a50eb | 6122 | s = "sltu"; |
3d3c5039 | 6123 | sge: |
0dd2d296 ILT |
6124 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6125 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6126 | (int) BFD_RELOC_LO16); |
670a50eb | 6127 | return; |
3d3c5039 | 6128 | |
670a50eb | 6129 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6130 | case M_SGEU_I: |
5c6f5923 GRK |
6131 | if (imm_expr.X_op == O_constant |
6132 | && imm_expr.X_add_number >= -0x8000 | |
6133 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6134 | { |
0dd2d296 | 6135 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 6136 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6137 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6138 | used_at = 0; |
6139 | } | |
6140 | else | |
6141 | { | |
d8a1c247 | 6142 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6143 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6144 | mask == M_SGE_I ? "slt" : "sltu", |
6145 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6146 | used_at = 1; |
6147 | } | |
0dd2d296 | 6148 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6149 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6150 | if (used_at) |
6151 | break; | |
6152 | return; | |
3d3c5039 ILT |
6153 | |
6154 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6155 | s = "slt"; |
6156 | goto sgt; | |
3d3c5039 | 6157 | case M_SGTU: |
670a50eb | 6158 | s = "sltu"; |
3d3c5039 | 6159 | sgt: |
0dd2d296 | 6160 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6161 | return; |
3d3c5039 | 6162 | |
670a50eb ILT |
6163 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6164 | s = "slt"; | |
6165 | goto sgti; | |
3d3c5039 | 6166 | case M_SGTU_I: |
670a50eb | 6167 | s = "sltu"; |
3d3c5039 | 6168 | sgti: |
d8a1c247 | 6169 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6170 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6171 | break; |
3d3c5039 | 6172 | |
670a50eb ILT |
6173 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6174 | s = "slt"; | |
6175 | goto sle; | |
3d3c5039 | 6176 | case M_SLEU: |
670a50eb | 6177 | s = "sltu"; |
3d3c5039 | 6178 | sle: |
0dd2d296 ILT |
6179 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6180 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6181 | (int) BFD_RELOC_LO16); |
670a50eb | 6182 | return; |
3d3c5039 | 6183 | |
670a50eb ILT |
6184 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6185 | s = "slt"; | |
6186 | goto slei; | |
3d3c5039 | 6187 | case M_SLEU_I: |
670a50eb | 6188 | s = "sltu"; |
3d3c5039 | 6189 | slei: |
d8a1c247 | 6190 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6191 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6192 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6193 | (int) BFD_RELOC_LO16); |
670a50eb | 6194 | break; |
3d3c5039 ILT |
6195 | |
6196 | case M_SLT_I: | |
5c6f5923 GRK |
6197 | if (imm_expr.X_op == O_constant |
6198 | && imm_expr.X_add_number >= -0x8000 | |
6199 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6200 | { |
0dd2d296 ILT |
6201 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6202 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6203 | return; |
3d3c5039 | 6204 | } |
d8a1c247 | 6205 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6206 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6207 | break; |
3d3c5039 ILT |
6208 | |
6209 | case M_SLTU_I: | |
5c6f5923 GRK |
6210 | if (imm_expr.X_op == O_constant |
6211 | && imm_expr.X_add_number >= -0x8000 | |
6212 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6213 | { |
0dd2d296 ILT |
6214 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6215 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6216 | return; |
3d3c5039 | 6217 | } |
d8a1c247 | 6218 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6219 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6220 | AT); | |
670a50eb | 6221 | break; |
3d3c5039 ILT |
6222 | |
6223 | case M_SNE: | |
670a50eb | 6224 | if (sreg == 0) |
0dd2d296 ILT |
6225 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6226 | treg); | |
670a50eb | 6227 | else if (treg == 0) |
0dd2d296 ILT |
6228 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6229 | sreg); | |
670a50eb ILT |
6230 | else |
6231 | { | |
0dd2d296 ILT |
6232 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6233 | sreg, treg); | |
6234 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6235 | dreg); | |
3d3c5039 | 6236 | } |
670a50eb | 6237 | return; |
3d3c5039 ILT |
6238 | |
6239 | case M_SNE_I: | |
5c6f5923 | 6240 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6241 | { |
0dd2d296 ILT |
6242 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6243 | sreg); | |
670a50eb | 6244 | return; |
3d3c5039 | 6245 | } |
670a50eb ILT |
6246 | if (sreg == 0) |
6247 | { | |
9a7d824a | 6248 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 6249 | ip->insn_mo->name); |
0dd2d296 | 6250 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6251 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6252 | || mips_opts.isa < 3) | |
6253 | ? "addiu" : "daddiu"), | |
9226253a | 6254 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6255 | return; |
3d3c5039 | 6256 | } |
5c6f5923 GRK |
6257 | if (imm_expr.X_op == O_constant |
6258 | && imm_expr.X_add_number >= 0 | |
6259 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6260 | { |
0dd2d296 ILT |
6261 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6262 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6263 | used_at = 0; |
6e8dda9c | 6264 | } |
5c6f5923 GRK |
6265 | else if (imm_expr.X_op == O_constant |
6266 | && imm_expr.X_add_number > -0x8000 | |
6267 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6268 | { |
6269 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6270 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6271 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6272 | || mips_opts.isa < 3) | |
6273 | ? "addiu" : "daddiu"), | |
9226253a | 6274 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6275 | used_at = 0; |
6276 | } | |
6277 | else | |
6278 | { | |
d8a1c247 | 6279 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6280 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6281 | sreg, AT); | |
670a50eb ILT |
6282 | used_at = 1; |
6283 | } | |
0dd2d296 | 6284 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6285 | if (used_at) |
6286 | break; | |
6287 | return; | |
3d3c5039 | 6288 | |
8358c818 ILT |
6289 | case M_DSUB_I: |
6290 | dbl = 1; | |
3d3c5039 | 6291 | case M_SUB_I: |
5c6f5923 GRK |
6292 | if (imm_expr.X_op == O_constant |
6293 | && imm_expr.X_add_number > -0x8000 | |
6294 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6295 | { |
6296 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6297 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6298 | dbl ? "daddi" : "addi", |
9226253a | 6299 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6300 | return; |
3d3c5039 | 6301 | } |
d8a1c247 | 6302 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6303 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6304 | dbl ? "dsub" : "sub", |
6305 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6306 | break; |
3d3c5039 | 6307 | |
8358c818 ILT |
6308 | case M_DSUBU_I: |
6309 | dbl = 1; | |
3d3c5039 | 6310 | case M_SUBU_I: |
5c6f5923 GRK |
6311 | if (imm_expr.X_op == O_constant |
6312 | && imm_expr.X_add_number > -0x8000 | |
6313 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6314 | { |
6315 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6316 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6317 | dbl ? "daddiu" : "addiu", |
9226253a | 6318 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6319 | return; |
3d3c5039 | 6320 | } |
d8a1c247 | 6321 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6322 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6323 | dbl ? "dsubu" : "subu", |
6324 | "d,v,t", dreg, sreg, AT); | |
6325 | break; | |
6326 | ||
6327 | case M_TEQ_I: | |
6328 | s = "teq"; | |
6329 | goto trap; | |
6330 | case M_TGE_I: | |
6331 | s = "tge"; | |
6332 | goto trap; | |
6333 | case M_TGEU_I: | |
6334 | s = "tgeu"; | |
6335 | goto trap; | |
6336 | case M_TLT_I: | |
6337 | s = "tlt"; | |
6338 | goto trap; | |
6339 | case M_TLTU_I: | |
6340 | s = "tltu"; | |
6341 | goto trap; | |
6342 | case M_TNE_I: | |
6343 | s = "tne"; | |
6344 | trap: | |
d8a1c247 | 6345 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6346 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6347 | break; |
3d3c5039 ILT |
6348 | |
6349 | case M_TRUNCWD: | |
6350 | case M_TRUNCWS: | |
3c83da8a | 6351 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6352 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6353 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6354 | ||
6355 | /* | |
6356 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6357 | * or is there a reason for it? | |
6358 | */ | |
fbcfacb7 | 6359 | mips_emit_delays (true); |
3c83da8a | 6360 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6361 | mips_any_noreorder = 1; |
6362 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6363 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6364 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6365 | expr1.X_add_number = 3; |
0dd2d296 | 6366 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6367 | (int) BFD_RELOC_LO16); |
670a50eb | 6368 | expr1.X_add_number = 2; |
0dd2d296 | 6369 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6370 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6371 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6372 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6373 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6374 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6375 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6376 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6377 | --mips_opts.noreorder; |
670a50eb | 6378 | break; |
3d3c5039 ILT |
6379 | |
6380 | case M_ULH: | |
670a50eb ILT |
6381 | s = "lb"; |
6382 | goto ulh; | |
3d3c5039 | 6383 | case M_ULHU: |
670a50eb | 6384 | s = "lbu"; |
3d3c5039 | 6385 | ulh: |
8ea7f4e8 ILT |
6386 | if (offset_expr.X_add_number >= 0x7fff) |
6387 | as_bad ("operand overflow"); | |
670a50eb | 6388 | /* avoid load delay */ |
b9129c6f | 6389 | if (! target_big_endian) |
8ea7f4e8 | 6390 | offset_expr.X_add_number += 1; |
0dd2d296 | 6391 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6392 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6393 | if (! target_big_endian) |
8ea7f4e8 ILT |
6394 | offset_expr.X_add_number -= 1; |
6395 | else | |
6396 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6397 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6398 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6399 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6400 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6401 | break; |
3d3c5039 | 6402 | |
adcf2b9d ILT |
6403 | case M_ULD: |
6404 | s = "ldl"; | |
6405 | s2 = "ldr"; | |
6406 | off = 7; | |
6407 | goto ulw; | |
3d3c5039 | 6408 | case M_ULW: |
adcf2b9d ILT |
6409 | s = "lwl"; |
6410 | s2 = "lwr"; | |
6411 | off = 3; | |
6412 | ulw: | |
6413 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6414 | as_bad ("operand overflow"); |
b9129c6f | 6415 | if (! target_big_endian) |
adcf2b9d ILT |
6416 | offset_expr.X_add_number += off; |
6417 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6418 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6419 | if (! target_big_endian) |
adcf2b9d | 6420 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6421 | else |
adcf2b9d ILT |
6422 | offset_expr.X_add_number += off; |
6423 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6424 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6425 | return; |
3d3c5039 | 6426 | |
adcf2b9d ILT |
6427 | case M_ULD_A: |
6428 | s = "ldl"; | |
6429 | s2 = "ldr"; | |
6430 | off = 7; | |
6431 | goto ulwa; | |
6432 | case M_ULW_A: | |
6433 | s = "lwl"; | |
6434 | s2 = "lwr"; | |
6435 | off = 3; | |
6436 | ulwa: | |
6437 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6438 | if (breg != 0) |
6439 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6440 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6441 | || mips_opts.isa < 3) | |
6442 | ? "addu" : "daddu"), | |
c625fc23 | 6443 | "d,v,t", AT, AT, breg); |
b9129c6f | 6444 | if (! target_big_endian) |
adcf2b9d ILT |
6445 | expr1.X_add_number = off; |
6446 | else | |
6447 | expr1.X_add_number = 0; | |
6448 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6449 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6450 | if (! target_big_endian) |
adcf2b9d ILT |
6451 | expr1.X_add_number = 0; |
6452 | else | |
6453 | expr1.X_add_number = off; | |
6454 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6455 | (int) BFD_RELOC_LO16, AT); | |
6456 | break; | |
6457 | ||
3d3c5039 ILT |
6458 | case M_ULH_A: |
6459 | case M_ULHU_A: | |
0dd2d296 | 6460 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6461 | if (breg != 0) |
6462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6463 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6464 | || mips_opts.isa < 3) | |
6465 | ? "addu" : "daddu"), | |
c625fc23 | 6466 | "d,v,t", AT, AT, breg); |
b9129c6f | 6467 | if (target_big_endian) |
adcf2b9d ILT |
6468 | expr1.X_add_number = 0; |
6469 | macro_build ((char *) NULL, &icnt, &expr1, | |
6470 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6471 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6472 | if (target_big_endian) |
adcf2b9d | 6473 | expr1.X_add_number = 1; |
670a50eb | 6474 | else |
adcf2b9d ILT |
6475 | expr1.X_add_number = 0; |
6476 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6477 | (int) BFD_RELOC_LO16, AT); | |
6478 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6479 | treg, 8); | |
6480 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6481 | treg, AT); | |
670a50eb | 6482 | break; |
3d3c5039 ILT |
6483 | |
6484 | case M_USH: | |
8ea7f4e8 ILT |
6485 | if (offset_expr.X_add_number >= 0x7fff) |
6486 | as_bad ("operand overflow"); | |
b9129c6f | 6487 | if (target_big_endian) |
8ea7f4e8 | 6488 | offset_expr.X_add_number += 1; |
0dd2d296 | 6489 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6490 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6491 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6492 | if (target_big_endian) |
8ea7f4e8 ILT |
6493 | offset_expr.X_add_number -= 1; |
6494 | else | |
6495 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6496 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6497 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6498 | break; |
3d3c5039 | 6499 | |
adcf2b9d ILT |
6500 | case M_USD: |
6501 | s = "sdl"; | |
6502 | s2 = "sdr"; | |
6503 | off = 7; | |
6504 | goto usw; | |
3d3c5039 | 6505 | case M_USW: |
adcf2b9d ILT |
6506 | s = "swl"; |
6507 | s2 = "swr"; | |
6508 | off = 3; | |
6509 | usw: | |
6510 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6511 | as_bad ("operand overflow"); |
b9129c6f | 6512 | if (! target_big_endian) |
adcf2b9d ILT |
6513 | offset_expr.X_add_number += off; |
6514 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6515 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6516 | if (! target_big_endian) |
adcf2b9d | 6517 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6518 | else |
adcf2b9d ILT |
6519 | offset_expr.X_add_number += off; |
6520 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6521 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6522 | return; |
3d3c5039 | 6523 | |
adcf2b9d ILT |
6524 | case M_USD_A: |
6525 | s = "sdl"; | |
6526 | s2 = "sdr"; | |
6527 | off = 7; | |
6528 | goto uswa; | |
3d3c5039 | 6529 | case M_USW_A: |
adcf2b9d ILT |
6530 | s = "swl"; |
6531 | s2 = "swr"; | |
6532 | off = 3; | |
6533 | uswa: | |
0dd2d296 | 6534 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6535 | if (breg != 0) |
6536 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6537 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6538 | || mips_opts.isa < 3) | |
6539 | ? "addu" : "daddu"), | |
c625fc23 | 6540 | "d,v,t", AT, AT, breg); |
b9129c6f | 6541 | if (! target_big_endian) |
adcf2b9d | 6542 | expr1.X_add_number = off; |
670a50eb | 6543 | else |
adcf2b9d ILT |
6544 | expr1.X_add_number = 0; |
6545 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6546 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6547 | if (! target_big_endian) |
adcf2b9d ILT |
6548 | expr1.X_add_number = 0; |
6549 | else | |
6550 | expr1.X_add_number = off; | |
6551 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6552 | (int) BFD_RELOC_LO16, AT); | |
6553 | break; | |
6554 | ||
6555 | case M_USH_A: | |
6556 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6557 | if (breg != 0) |
6558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6559 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6560 | || mips_opts.isa < 3) | |
6561 | ? "addu" : "daddu"), | |
c625fc23 | 6562 | "d,v,t", AT, AT, breg); |
b9129c6f | 6563 | if (! target_big_endian) |
adcf2b9d ILT |
6564 | expr1.X_add_number = 0; |
6565 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6566 | (int) BFD_RELOC_LO16, AT); | |
6567 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6568 | treg, 8); | |
b9129c6f | 6569 | if (! target_big_endian) |
adcf2b9d ILT |
6570 | expr1.X_add_number = 1; |
6571 | else | |
6572 | expr1.X_add_number = 0; | |
6573 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6574 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6575 | if (! target_big_endian) |
adcf2b9d ILT |
6576 | expr1.X_add_number = 0; |
6577 | else | |
6578 | expr1.X_add_number = 1; | |
6579 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6580 | (int) BFD_RELOC_LO16, AT); | |
6581 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6582 | treg, 8); | |
6583 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6584 | treg, AT); | |
670a50eb | 6585 | break; |
3d3c5039 ILT |
6586 | |
6587 | default: | |
9218cee0 ILT |
6588 | /* FIXME: Check if this is one of the itbl macros, since they |
6589 | are added dynamically. */ | |
670a50eb | 6590 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6591 | break; |
3d3c5039 | 6592 | } |
3c83da8a | 6593 | if (mips_opts.noat) |
670a50eb | 6594 | as_warn ("Macro used $at after \".set noat\""); |
3d3c5039 ILT |
6595 | } |
6596 | ||
cc5703cd | 6597 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6598 | |
3d3c5039 | 6599 | static void |
cc5703cd | 6600 | mips16_macro (ip) |
3d3c5039 ILT |
6601 | struct mips_cl_insn *ip; |
6602 | { | |
cc5703cd ILT |
6603 | int mask; |
6604 | int xreg, yreg, zreg, tmp; | |
6605 | int icnt; | |
6606 | expressionS expr1; | |
6607 | int dbl; | |
6608 | const char *s, *s2, *s3; | |
3d3c5039 | 6609 | |
cc5703cd | 6610 | mask = ip->insn_mo->mask; |
3d3c5039 | 6611 | |
cc5703cd ILT |
6612 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6613 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6614 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6615 | |
cc5703cd | 6616 | icnt = 0; |
8358c818 | 6617 | |
cc5703cd ILT |
6618 | expr1.X_op = O_constant; |
6619 | expr1.X_op_symbol = NULL; | |
6620 | expr1.X_add_symbol = NULL; | |
6621 | expr1.X_add_number = 1; | |
8358c818 | 6622 | |
cc5703cd | 6623 | dbl = 0; |
517078c1 | 6624 | |
cc5703cd ILT |
6625 | switch (mask) |
6626 | { | |
6627 | default: | |
6628 | internalError (); | |
6629 | ||
6630 | case M_DDIV_3: | |
6631 | dbl = 1; | |
6632 | case M_DIV_3: | |
6633 | s = "mflo"; | |
6634 | goto do_div3; | |
6635 | case M_DREM_3: | |
6636 | dbl = 1; | |
6637 | case M_REM_3: | |
6638 | s = "mfhi"; | |
6639 | do_div3: | |
fbcfacb7 | 6640 | mips_emit_delays (true); |
3c83da8a | 6641 | ++mips_opts.noreorder; |
cc5703cd ILT |
6642 | mips_any_noreorder = 1; |
6643 | macro_build ((char *) NULL, &icnt, NULL, | |
6644 | dbl ? "ddiv" : "div", | |
6645 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6646 | expr1.X_add_number = 2; |
cc5703cd | 6647 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6648 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6649 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6650 | since that causes an overflow. We should do that as well, | |
6651 | but I don't see how to do the comparisons without a temporary | |
6652 | register. */ | |
3c83da8a | 6653 | --mips_opts.noreorder; |
cc5703cd ILT |
6654 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6655 | break; | |
6656 | ||
6657 | case M_DIVU_3: | |
6658 | s = "divu"; | |
6659 | s2 = "mflo"; | |
6660 | goto do_divu3; | |
6661 | case M_REMU_3: | |
6662 | s = "divu"; | |
6663 | s2 = "mfhi"; | |
6664 | goto do_divu3; | |
6665 | case M_DDIVU_3: | |
6666 | s = "ddivu"; | |
6667 | s2 = "mflo"; | |
6668 | goto do_divu3; | |
6669 | case M_DREMU_3: | |
6670 | s = "ddivu"; | |
6671 | s2 = "mfhi"; | |
6672 | do_divu3: | |
fbcfacb7 | 6673 | mips_emit_delays (true); |
3c83da8a | 6674 | ++mips_opts.noreorder; |
cc5703cd ILT |
6675 | mips_any_noreorder = 1; |
6676 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6677 | expr1.X_add_number = 2; |
cc5703cd | 6678 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd | 6679 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
3c83da8a | 6680 | --mips_opts.noreorder; |
cc5703cd ILT |
6681 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6682 | break; | |
6683 | ||
08438bef ILT |
6684 | case M_DMUL: |
6685 | dbl = 1; | |
6686 | case M_MUL: | |
6687 | macro_build ((char *) NULL, &icnt, NULL, | |
6688 | dbl ? "dmultu" : "multu", | |
6689 | "x,y", xreg, yreg); | |
6690 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6691 | return; | |
6692 | ||
cc5703cd ILT |
6693 | case M_DSUBU_I: |
6694 | dbl = 1; | |
6695 | goto do_subu; | |
6696 | case M_SUBU_I: | |
6697 | do_subu: | |
5c6f5923 GRK |
6698 | if (imm_expr.X_op != O_constant) |
6699 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6700 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6701 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6702 | dbl ? "daddiu" : "addiu", | |
6703 | "y,x,4", yreg, xreg); | |
6704 | break; | |
6705 | ||
6706 | case M_SUBU_I_2: | |
5c6f5923 GRK |
6707 | if (imm_expr.X_op != O_constant) |
6708 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6709 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6710 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6711 | "x,k", xreg); | |
6712 | break; | |
6713 | ||
6714 | case M_DSUBU_I_2: | |
5c6f5923 GRK |
6715 | if (imm_expr.X_op != O_constant) |
6716 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6717 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6718 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6719 | "y,j", yreg); | |
6720 | break; | |
6721 | ||
6722 | case M_BEQ: | |
6723 | s = "cmp"; | |
6724 | s2 = "bteqz"; | |
6725 | goto do_branch; | |
6726 | case M_BNE: | |
6727 | s = "cmp"; | |
6728 | s2 = "btnez"; | |
6729 | goto do_branch; | |
6730 | case M_BLT: | |
6731 | s = "slt"; | |
6732 | s2 = "btnez"; | |
6733 | goto do_branch; | |
6734 | case M_BLTU: | |
6735 | s = "sltu"; | |
6736 | s2 = "btnez"; | |
6737 | goto do_branch; | |
6738 | case M_BLE: | |
6739 | s = "slt"; | |
6740 | s2 = "bteqz"; | |
6741 | goto do_reverse_branch; | |
6742 | case M_BLEU: | |
6743 | s = "sltu"; | |
6744 | s2 = "bteqz"; | |
6745 | goto do_reverse_branch; | |
6746 | case M_BGE: | |
6747 | s = "slt"; | |
6748 | s2 = "bteqz"; | |
6749 | goto do_branch; | |
6750 | case M_BGEU: | |
6751 | s = "sltu"; | |
6752 | s2 = "bteqz"; | |
6753 | goto do_branch; | |
6754 | case M_BGT: | |
6755 | s = "slt"; | |
6756 | s2 = "btnez"; | |
6757 | goto do_reverse_branch; | |
6758 | case M_BGTU: | |
6759 | s = "sltu"; | |
6760 | s2 = "btnez"; | |
6761 | ||
6762 | do_reverse_branch: | |
6763 | tmp = xreg; | |
6764 | xreg = yreg; | |
6765 | yreg = tmp; | |
6766 | ||
6767 | do_branch: | |
6768 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6769 | xreg, yreg); | |
6770 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6771 | break; | |
6772 | ||
6773 | case M_BEQ_I: | |
6774 | s = "cmpi"; | |
6775 | s2 = "bteqz"; | |
6776 | s3 = "x,U"; | |
6777 | goto do_branch_i; | |
6778 | case M_BNE_I: | |
6779 | s = "cmpi"; | |
6780 | s2 = "btnez"; | |
6781 | s3 = "x,U"; | |
6782 | goto do_branch_i; | |
6783 | case M_BLT_I: | |
6784 | s = "slti"; | |
6785 | s2 = "btnez"; | |
6786 | s3 = "x,8"; | |
6787 | goto do_branch_i; | |
6788 | case M_BLTU_I: | |
6789 | s = "sltiu"; | |
6790 | s2 = "btnez"; | |
6791 | s3 = "x,8"; | |
6792 | goto do_branch_i; | |
6793 | case M_BLE_I: | |
6794 | s = "slti"; | |
6795 | s2 = "btnez"; | |
6796 | s3 = "x,8"; | |
6797 | goto do_addone_branch_i; | |
6798 | case M_BLEU_I: | |
6799 | s = "sltiu"; | |
6800 | s2 = "btnez"; | |
6801 | s3 = "x,8"; | |
6802 | goto do_addone_branch_i; | |
6803 | case M_BGE_I: | |
6804 | s = "slti"; | |
6805 | s2 = "bteqz"; | |
6806 | s3 = "x,8"; | |
6807 | goto do_branch_i; | |
6808 | case M_BGEU_I: | |
6809 | s = "sltiu"; | |
6810 | s2 = "bteqz"; | |
6811 | s3 = "x,8"; | |
6812 | goto do_branch_i; | |
6813 | case M_BGT_I: | |
6814 | s = "slti"; | |
6815 | s2 = "bteqz"; | |
6816 | s3 = "x,8"; | |
6817 | goto do_addone_branch_i; | |
6818 | case M_BGTU_I: | |
6819 | s = "sltiu"; | |
6820 | s2 = "bteqz"; | |
6821 | s3 = "x,8"; | |
6822 | ||
6823 | do_addone_branch_i: | |
5c6f5923 GRK |
6824 | if (imm_expr.X_op != O_constant) |
6825 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6826 | ++imm_expr.X_add_number; |
6827 | ||
6828 | do_branch_i: | |
6829 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6830 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6831 | break; | |
18e0764d ILT |
6832 | |
6833 | case M_ABS: | |
6834 | expr1.X_add_number = 0; | |
6835 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6836 | if (xreg != yreg) | |
6837 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6838 | "move", "y,X", xreg, yreg); | |
6839 | expr1.X_add_number = 2; | |
6840 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6842 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6843 | } |
6844 | } | |
6845 | ||
aa2e0460 KR |
6846 | /* For consistency checking, verify that all bits are specified either |
6847 | by the match/mask part of the instruction definition, or by the | |
6848 | operand list. */ | |
6849 | static int | |
6850 | validate_mips_insn (opc) | |
6851 | const struct mips_opcode *opc; | |
6852 | { | |
6853 | const char *p = opc->args; | |
6854 | char c; | |
6855 | unsigned long used_bits = opc->mask; | |
6856 | ||
6857 | if ((used_bits & opc->match) != opc->match) | |
6858 | { | |
6859 | as_bad ("internal: bad mips opcode (mask error): %s %s", | |
6860 | opc->name, opc->args); | |
6861 | return 0; | |
6862 | } | |
6863 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6864 | while (*p) | |
6865 | switch (c = *p++) | |
6866 | { | |
6867 | case ',': break; | |
6868 | case '(': break; | |
6869 | case ')': break; | |
6870 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6871 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6872 | case 'A': break; | |
6873 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6874 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6875 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6876 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6877 | case 'F': break; | |
6878 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6879 | case 'I': break; | |
6880 | case 'L': break; | |
6881 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6882 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6883 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6884 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6885 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6886 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6887 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6888 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6889 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6890 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6891 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6892 | case 'f': break; | |
6893 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6894 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6895 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6896 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6897 | case 'l': break; | |
6898 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6899 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6900 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6901 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6902 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6903 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6904 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6905 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6906 | case 'x': break; | |
6907 | case 'z': break; | |
aa2e0460 | 6908 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
1c6f3441 | 6909 | /* start-sanitize-vr5400 */ |
aa2e0460 KR |
6910 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
6911 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
6912 | case '[': break; | |
6913 | case ']': break; | |
6914 | /* end-sanitize-vr5400 */ | |
6915 | default: | |
6916 | as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s", | |
6917 | c, opc->name, opc->args); | |
6918 | return 0; | |
6919 | } | |
6920 | #undef USE_BITS | |
6921 | /* Some of the trapping instructions (break, t*, sdbbp) have "code" | |
6922 | fields that cannot currently be set by assembly code. Ignore them | |
6923 | for now. */ | |
6924 | if (opc->pinfo & INSN_TRAP) | |
6925 | { | |
6926 | static const char *const trap_insns[] = { | |
6927 | "break", "sdbbp", | |
6928 | "teq", "tge", "tgeu", "tlt", "tltu", "tne", | |
6929 | }; | |
6930 | int i; | |
6931 | for (i = sizeof(trap_insns)/sizeof(trap_insns[0]) - 1; i >= 0; i--) | |
6932 | if (!strcmp (trap_insns[i], opc->name)) | |
6933 | { | |
6934 | used_bits |= 0xffc0; | |
6935 | break; | |
6936 | } | |
6937 | } | |
6938 | if (used_bits != 0xffffffff) | |
6939 | { | |
6940 | as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s", | |
6941 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6942 | return 0; | |
6943 | } | |
6944 | return 1; | |
6945 | } | |
6946 | ||
cc5703cd ILT |
6947 | /* This routine assembles an instruction into its binary format. As a |
6948 | side effect, it sets one of the global variables imm_reloc or | |
6949 | offset_reloc to the type of relocation to do if one of the operands | |
6950 | is an address expression. */ | |
6951 | ||
6952 | static void | |
6953 | mips_ip (str, ip) | |
6954 | char *str; | |
6955 | struct mips_cl_insn *ip; | |
6956 | { | |
6957 | char *s; | |
6958 | const char *args; | |
6959 | char c; | |
6960 | struct mips_opcode *insn; | |
6961 | char *argsStart; | |
6962 | unsigned int regno; | |
6963 | unsigned int lastregno = 0; | |
6964 | char *s_reset; | |
6965 | ||
6966 | insn_error = NULL; | |
6967 | ||
e2e5acfa | 6968 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6969 | continue; |
1857d1e6 | 6970 | if (isspace (*s)) |
e2e5acfa | 6971 | *s++ = '\0'; |
1857d1e6 | 6972 | |
cc5703cd ILT |
6973 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6974 | { | |
6975 | insn_error = "unrecognized opcode"; | |
6976 | return; | |
6977 | } | |
6978 | argsStart = s; | |
6979 | for (;;) | |
6980 | { | |
6981 | int insn_isa; | |
a652f74c | 6982 | boolean ok; |
cc5703cd ILT |
6983 | |
6984 | assert (strcmp (insn->name, str) == 0); | |
6985 | ||
1c6f3441 | 6986 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 6987 | insn_isa = 1; |
5c6f5923 | 6988 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 6989 | insn_isa = 2; |
5c6f5923 | 6990 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 6991 | insn_isa = 3; |
5c6f5923 | 6992 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
6993 | insn_isa = 4; |
6994 | else | |
931a1858 | 6995 | insn_isa = 15; |
cc5703cd | 6996 | |
a652f74c ILT |
6997 | if (insn_isa <= mips_opts.isa) |
6998 | ok = true; | |
6999 | else if (insn->pinfo == INSN_MACRO) | |
7000 | ok = false; | |
7001 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
7002 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
7003 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
2d035a50 GRK |
7004 | /* start-sanitize-vr4320 */ |
7005 | || (mips_4320 && (insn->membership & INSN_4320) != 0) | |
7006 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
7007 | /* start-sanitize-tx49 */ |
7008 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
7009 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
7010 | /* start-sanitize-r5900 */ |
7011 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
7012 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
7013 | /* start-sanitize-vr5400 */ |
7014 | || (mips_5400 && (insn->membership & INSN_5400) != 0) | |
7015 | /* end-sanitize-vr5400 */ | |
a652f74c | 7016 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7017 | ok = true; |
a652f74c ILT |
7018 | else |
7019 | ok = false; | |
7020 | ||
b2cf4548 DE |
7021 | if (insn->pinfo != INSN_MACRO) |
7022 | { | |
7023 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
7024 | ok = false; | |
7025 | /* start-sanitize-r5900 */ | |
7026 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
7027 | ok = false; | |
7028 | /* end-sanitize-r5900 */ | |
7029 | } | |
1c6f3441 | 7030 | |
a652f74c | 7031 | if (! ok) |
cc5703cd ILT |
7032 | { |
7033 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7034 | && strcmp (insn->name, insn[1].name) == 0) | |
7035 | { | |
7036 | ++insn; | |
7037 | continue; | |
7038 | } | |
6fd819cf GRK |
7039 | if (insn_isa == 15 |
7040 | || insn_isa <= mips_opts.isa) | |
cc5703cd ILT |
7041 | insn_error = "opcode not supported on this processor"; |
7042 | else | |
7043 | { | |
7044 | static char buf[100]; | |
7045 | ||
7046 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
7047 | insn_error = buf; | |
7048 | } | |
7049 | return; | |
7050 | } | |
8358c818 | 7051 | |
670a50eb ILT |
7052 | ip->insn_mo = insn; |
7053 | ip->insn_opcode = insn->match; | |
7054 | for (args = insn->args;; ++args) | |
7055 | { | |
7056 | if (*s == ' ') | |
7057 | ++s; | |
7058 | switch (*args) | |
7059 | { | |
7060 | case '\0': /* end of args */ | |
7061 | if (*s == '\0') | |
7062 | return; | |
7063 | break; | |
3d3c5039 ILT |
7064 | |
7065 | case ',': | |
670a50eb ILT |
7066 | if (*s++ == *args) |
7067 | continue; | |
7068 | s--; | |
7069 | switch (*++args) | |
7070 | { | |
3d3c5039 ILT |
7071 | case 'r': |
7072 | case 'v': | |
670a50eb ILT |
7073 | ip->insn_opcode |= lastregno << 21; |
7074 | continue; | |
3d3c5039 ILT |
7075 | |
7076 | case 'w': | |
7077 | case 'W': | |
670a50eb ILT |
7078 | ip->insn_opcode |= lastregno << 16; |
7079 | continue; | |
3d3c5039 ILT |
7080 | |
7081 | case 'V': | |
670a50eb ILT |
7082 | ip->insn_opcode |= lastregno << 11; |
7083 | continue; | |
3d3c5039 | 7084 | } |
670a50eb | 7085 | break; |
3d3c5039 ILT |
7086 | |
7087 | case '(': | |
670a50eb ILT |
7088 | /* handle optional base register. |
7089 | Either the base register is omitted or | |
7090 | we must have a left paren. */ | |
7091 | /* this is dependent on the next operand specifier | |
7092 | is a 'b' for base register */ | |
7093 | assert (args[1] == 'b'); | |
7094 | if (*s == '\0') | |
7095 | return; | |
3d3c5039 | 7096 | |
670a50eb | 7097 | case ')': /* these must match exactly */ |
aa2e0460 KR |
7098 | /* start-sanitize-vr5400 */ |
7099 | case '[': | |
7100 | case ']': | |
7101 | /* end-sanitize-vr5400 */ | |
670a50eb | 7102 | if (*s++ == *args) |
3d3c5039 | 7103 | continue; |
670a50eb ILT |
7104 | break; |
7105 | ||
7106 | case '<': /* must be at least one digit */ | |
7107 | /* | |
7108 | * According to the manual, if the shift amount is greater | |
7109 | * than 31 or less than 0 the the shift amount should be | |
7110 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7111 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7112 | */ |
7113 | my_getExpression (&imm_expr, s); | |
7114 | check_absolute_expr (ip, &imm_expr); | |
7115 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7116 | { | |
58d4951d ILT |
7117 | as_warn ("Improper shift amount (%ld)", |
7118 | (long) imm_expr.X_add_number); | |
9226253a | 7119 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7120 | } |
7121 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7122 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7123 | s = expr_end; |
7124 | continue; | |
7125 | ||
56c96faa ILT |
7126 | case '>': /* shift amount minus 32 */ |
7127 | my_getExpression (&imm_expr, s); | |
7128 | check_absolute_expr (ip, &imm_expr); | |
7129 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7130 | || (unsigned long) imm_expr.X_add_number > 63) | |
7131 | break; | |
7132 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7133 | imm_expr.X_op = O_absent; | |
7134 | s = expr_end; | |
7135 | continue; | |
7136 | ||
9226253a | 7137 | case 'k': /* cache code */ |
d8a1c247 | 7138 | case 'h': /* prefx code */ |
9226253a ILT |
7139 | my_getExpression (&imm_expr, s); |
7140 | check_absolute_expr (ip, &imm_expr); | |
7141 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7142 | { | |
d8a1c247 KR |
7143 | as_warn ("Invalid value for `%s' (%lu)", |
7144 | ip->insn_mo->name, | |
9226253a ILT |
7145 | (unsigned long) imm_expr.X_add_number); |
7146 | imm_expr.X_add_number &= 0x1f; | |
7147 | } | |
d8a1c247 KR |
7148 | if (*args == 'k') |
7149 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7150 | else | |
7151 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7152 | imm_expr.X_op = O_absent; |
7153 | s = expr_end; | |
7154 | continue; | |
7155 | ||
670a50eb ILT |
7156 | case 'c': /* break code */ |
7157 | my_getExpression (&imm_expr, s); | |
7158 | check_absolute_expr (ip, &imm_expr); | |
7159 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
7160 | as_warn ("Illegal break code (%ld)", |
7161 | (long) imm_expr.X_add_number); | |
670a50eb | 7162 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7163 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7164 | s = expr_end; |
7165 | continue; | |
7166 | ||
918692a5 ILT |
7167 | case 'B': /* syscall code */ |
7168 | my_getExpression (&imm_expr, s); | |
7169 | check_absolute_expr (ip, &imm_expr); | |
7170 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
7171 | as_warn ("Illegal syscall code (%ld)", |
7172 | (long) imm_expr.X_add_number); | |
918692a5 | 7173 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7174 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7175 | s = expr_end; |
7176 | continue; | |
7177 | ||
0aa07269 ILT |
7178 | case 'C': /* Coprocessor code */ |
7179 | my_getExpression (&imm_expr, s); | |
7180 | check_absolute_expr (ip, &imm_expr); | |
7181 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7182 | { | |
58d4951d ILT |
7183 | as_warn ("Coproccesor code > 25 bits (%ld)", |
7184 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
7185 | imm_expr.X_add_number &= ((1<<25) - 1); |
7186 | } | |
7187 | ip->insn_opcode |= imm_expr.X_add_number; | |
7188 | imm_expr.X_op = O_absent; | |
7189 | s = expr_end; | |
7190 | continue; | |
7191 | ||
65d2c7d3 JL |
7192 | case 'P': /* Performance register */ |
7193 | my_getExpression (&imm_expr, s); | |
7194 | check_absolute_expr (ip, &imm_expr); | |
7195 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7196 | { | |
7197 | as_warn ("Invalidate performance regster (%ld)", | |
7198 | (long) imm_expr.X_add_number); | |
7199 | imm_expr.X_add_number &= 1; | |
7200 | } | |
7201 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7202 | imm_expr.X_op = O_absent; | |
7203 | s = expr_end; | |
7204 | continue; | |
7205 | ||
670a50eb ILT |
7206 | case 'b': /* base register */ |
7207 | case 'd': /* destination register */ | |
7208 | case 's': /* source register */ | |
7209 | case 't': /* target register */ | |
7210 | case 'r': /* both target and source */ | |
7211 | case 'v': /* both dest and source */ | |
7212 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7213 | case 'E': /* coprocessor target register */ |
7214 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7215 | case 'x': /* ignore register name */ |
ff3a5c18 | 7216 | case 'z': /* must be zero register */ |
670a50eb ILT |
7217 | s_reset = s; |
7218 | if (s[0] == '$') | |
7219 | { | |
7220 | if (isdigit (s[1])) | |
7221 | { | |
7222 | ++s; | |
7223 | regno = 0; | |
7224 | do | |
7225 | { | |
7226 | regno *= 10; | |
7227 | regno += *s - '0'; | |
7228 | ++s; | |
7229 | } | |
7230 | while (isdigit (*s)); | |
0aa07269 ILT |
7231 | if (regno > 31) |
7232 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 7233 | } |
0dd2d296 ILT |
7234 | else if (*args == 'E' || *args == 'G') |
7235 | goto notreg; | |
7236 | else | |
670a50eb | 7237 | { |
0aa07269 ILT |
7238 | if (s[1] == 'f' && s[2] == 'p') |
7239 | { | |
7240 | s += 3; | |
9226253a | 7241 | regno = FP; |
0aa07269 ILT |
7242 | } |
7243 | else if (s[1] == 's' && s[2] == 'p') | |
7244 | { | |
7245 | s += 3; | |
9226253a | 7246 | regno = SP; |
0aa07269 ILT |
7247 | } |
7248 | else if (s[1] == 'g' && s[2] == 'p') | |
7249 | { | |
7250 | s += 3; | |
9226253a | 7251 | regno = GP; |
0aa07269 ILT |
7252 | } |
7253 | else if (s[1] == 'a' && s[2] == 't') | |
7254 | { | |
7255 | s += 3; | |
9226253a | 7256 | regno = AT; |
0aa07269 | 7257 | } |
b2b8c24e ILT |
7258 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7259 | { | |
7260 | s += 4; | |
7261 | regno = KT0; | |
7262 | } | |
7263 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7264 | { | |
7265 | s += 4; | |
7266 | regno = KT1; | |
7267 | } | |
efec4a28 DP |
7268 | else if (itbl_have_entries) |
7269 | { | |
7270 | char *p, *n; | |
7271 | int r; | |
7272 | ||
7273 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7274 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7275 | |
7276 | /* See if this is a register defined in an | |
7277 | itbl entry */ | |
9218cee0 ILT |
7278 | r = itbl_get_reg_val (n); |
7279 | if (r) | |
efec4a28 | 7280 | { |
9218cee0 ILT |
7281 | /* Get_field advances to the start of |
7282 | the next field, so we need to back | |
7283 | rack to the end of the last field. */ | |
efec4a28 | 7284 | if (p) |
9218cee0 | 7285 | s = p - 1; |
efec4a28 | 7286 | else |
9218cee0 | 7287 | s = strchr (s,'\0'); |
efec4a28 DP |
7288 | regno = r; |
7289 | } | |
7290 | else | |
7291 | goto notreg; | |
7292 | } | |
0aa07269 ILT |
7293 | else |
7294 | goto notreg; | |
670a50eb | 7295 | } |
9753202d | 7296 | if (regno == AT |
3c83da8a | 7297 | && ! mips_opts.noat |
9753202d ILT |
7298 | && *args != 'E' |
7299 | && *args != 'G') | |
13fe1379 | 7300 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
7301 | c = *args; |
7302 | if (*s == ' ') | |
7303 | s++; | |
7304 | if (args[1] != *s) | |
7305 | { | |
7306 | if (c == 'r' || c == 'v' || c == 'w') | |
7307 | { | |
7308 | regno = lastregno; | |
7309 | s = s_reset; | |
7310 | args++; | |
7311 | } | |
7312 | } | |
ff3a5c18 ILT |
7313 | /* 'z' only matches $0. */ |
7314 | if (c == 'z' && regno != 0) | |
7315 | break; | |
efec4a28 DP |
7316 | |
7317 | /* Now that we have assembled one operand, we use the args string | |
7318 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7319 | switch (c) |
7320 | { | |
3d3c5039 ILT |
7321 | case 'r': |
7322 | case 's': | |
7323 | case 'v': | |
7324 | case 'b': | |
670a50eb ILT |
7325 | ip->insn_opcode |= regno << 21; |
7326 | break; | |
3d3c5039 | 7327 | case 'd': |
918692a5 | 7328 | case 'G': |
670a50eb ILT |
7329 | ip->insn_opcode |= regno << 11; |
7330 | break; | |
3d3c5039 ILT |
7331 | case 'w': |
7332 | case 't': | |
918692a5 | 7333 | case 'E': |
670a50eb | 7334 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7335 | break; |
7336 | case 'x': | |
7337 | /* This case exists because on the r3000 trunc | |
7338 | expands into a macro which requires a gp | |
7339 | register. On the r6000 or r4000 it is | |
7340 | assembled into a single instruction which | |
7341 | ignores the register. Thus the insn version | |
7342 | is MIPS_ISA2 and uses 'x', and the macro | |
7343 | version is MIPS_ISA1 and uses 't'. */ | |
7344 | break; | |
ff3a5c18 ILT |
7345 | case 'z': |
7346 | /* This case is for the div instruction, which | |
7347 | acts differently if the destination argument | |
7348 | is $0. This only matches $0, and is checked | |
7349 | outside the switch. */ | |
7350 | break; | |
efec4a28 DP |
7351 | case 'D': |
7352 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7353 | break; | |
9218cee0 ILT |
7354 | /* What about all other operands like 'i', which |
7355 | can be specified in the opcode table? */ | |
3d3c5039 | 7356 | } |
670a50eb ILT |
7357 | lastregno = regno; |
7358 | continue; | |
3d3c5039 ILT |
7359 | } |
7360 | notreg: | |
670a50eb ILT |
7361 | switch (*args++) |
7362 | { | |
3d3c5039 ILT |
7363 | case 'r': |
7364 | case 'v': | |
670a50eb ILT |
7365 | ip->insn_opcode |= lastregno << 21; |
7366 | continue; | |
3d3c5039 | 7367 | case 'w': |
670a50eb ILT |
7368 | ip->insn_opcode |= lastregno << 16; |
7369 | continue; | |
3d3c5039 | 7370 | } |
670a50eb | 7371 | break; |
3d3c5039 | 7372 | |
670a50eb ILT |
7373 | case 'D': /* floating point destination register */ |
7374 | case 'S': /* floating point source register */ | |
7375 | case 'T': /* floating point target register */ | |
d8a1c247 | 7376 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7377 | case 'V': |
7378 | case 'W': | |
670a50eb ILT |
7379 | s_reset = s; |
7380 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7381 | { | |
7382 | s += 2; | |
7383 | regno = 0; | |
7384 | do | |
7385 | { | |
7386 | regno *= 10; | |
7387 | regno += *s - '0'; | |
7388 | ++s; | |
7389 | } | |
7390 | while (isdigit (*s)); | |
7391 | ||
7392 | if (regno > 31) | |
7393 | as_bad ("Invalid float register number (%d)", regno); | |
7394 | ||
9226253a | 7395 | if ((regno & 1) != 0 |
3c83da8a | 7396 | && mips_opts.isa < 3 |
538034cf ILT |
7397 | && ! (strcmp (str, "mtc1") == 0 |
7398 | || strcmp (str, "mfc1") == 0 | |
7399 | || strcmp (str, "lwc1") == 0 | |
7400 | || strcmp (str, "swc1") == 0 | |
7401 | || strcmp (str, "l.s") == 0 | |
7402 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
7403 | as_warn ("Float register should be even, was %d", |
7404 | regno); | |
7405 | ||
7406 | c = *args; | |
7407 | if (*s == ' ') | |
7408 | s++; | |
7409 | if (args[1] != *s) | |
7410 | { | |
7411 | if (c == 'V' || c == 'W') | |
7412 | { | |
7413 | regno = lastregno; | |
7414 | s = s_reset; | |
7415 | args++; | |
3d3c5039 ILT |
7416 | } |
7417 | } | |
670a50eb ILT |
7418 | switch (c) |
7419 | { | |
3d3c5039 | 7420 | case 'D': |
670a50eb ILT |
7421 | ip->insn_opcode |= regno << 6; |
7422 | break; | |
3d3c5039 ILT |
7423 | case 'V': |
7424 | case 'S': | |
670a50eb ILT |
7425 | ip->insn_opcode |= regno << 11; |
7426 | break; | |
3d3c5039 ILT |
7427 | case 'W': |
7428 | case 'T': | |
670a50eb | 7429 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7430 | break; |
7431 | case 'R': | |
7432 | ip->insn_opcode |= regno << 21; | |
7433 | break; | |
3d3c5039 | 7434 | } |
670a50eb ILT |
7435 | lastregno = regno; |
7436 | continue; | |
3d3c5039 | 7437 | } |
670a50eb ILT |
7438 | switch (*args++) |
7439 | { | |
3d3c5039 | 7440 | case 'V': |
670a50eb ILT |
7441 | ip->insn_opcode |= lastregno << 11; |
7442 | continue; | |
3d3c5039 | 7443 | case 'W': |
670a50eb ILT |
7444 | ip->insn_opcode |= lastregno << 16; |
7445 | continue; | |
3d3c5039 | 7446 | } |
670a50eb | 7447 | break; |
3d3c5039 ILT |
7448 | |
7449 | case 'I': | |
670a50eb | 7450 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7451 | if (imm_expr.X_op != O_big |
7452 | && imm_expr.X_op != O_constant) | |
7453 | insn_error = "absolute expression required"; | |
670a50eb ILT |
7454 | s = expr_end; |
7455 | continue; | |
3d3c5039 ILT |
7456 | |
7457 | case 'A': | |
670a50eb ILT |
7458 | my_getExpression (&offset_expr, s); |
7459 | imm_reloc = BFD_RELOC_32; | |
7460 | s = expr_end; | |
7461 | continue; | |
3d3c5039 ILT |
7462 | |
7463 | case 'F': | |
19ed8960 ILT |
7464 | case 'L': |
7465 | case 'f': | |
7466 | case 'l': | |
7467 | { | |
7468 | int f64; | |
7469 | char *save_in; | |
7470 | char *err; | |
7471 | unsigned char temp[8]; | |
604633ae ILT |
7472 | int len; |
7473 | unsigned int length; | |
19ed8960 ILT |
7474 | segT seg; |
7475 | subsegT subseg; | |
7476 | char *p; | |
7477 | ||
7478 | /* These only appear as the last operand in an | |
7479 | instruction, and every instruction that accepts | |
7480 | them in any variant accepts them in all variants. | |
7481 | This means we don't have to worry about backing out | |
7482 | any changes if the instruction does not match. | |
7483 | ||
7484 | The difference between them is the size of the | |
7485 | floating point constant and where it goes. For 'F' | |
7486 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7487 | is 32 bits. Where the constant is placed is based | |
7488 | on how the MIPS assembler does things: | |
7489 | F -- .rdata | |
7490 | L -- .lit8 | |
7491 | f -- immediate value | |
7492 | l -- .lit4 | |
0dd2d296 | 7493 | |
55933a58 ILT |
7494 | The .lit4 and .lit8 sections are only used if |
7495 | permitted by the -G argument. | |
7496 | ||
7497 | When generating embedded PIC code, we use the | |
7498 | .lit8 section but not the .lit4 section (we can do | |
7499 | .lit4 inline easily; we need to put .lit8 | |
7500 | somewhere in the data segment, and using .lit8 | |
7501 | permits the linker to eventually combine identical | |
7502 | .lit8 entries). */ | |
19ed8960 ILT |
7503 | |
7504 | f64 = *args == 'F' || *args == 'L'; | |
7505 | ||
7506 | save_in = input_line_pointer; | |
7507 | input_line_pointer = s; | |
604633ae ILT |
7508 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7509 | length = len; | |
19ed8960 ILT |
7510 | s = input_line_pointer; |
7511 | input_line_pointer = save_in; | |
7512 | if (err != NULL && *err != '\0') | |
7513 | { | |
7514 | as_bad ("Bad floating point constant: %s", err); | |
7515 | memset (temp, '\0', sizeof temp); | |
7516 | length = f64 ? 8 : 4; | |
7517 | } | |
7518 | ||
7519 | assert (length == (f64 ? 8 : 4)); | |
7520 | ||
0dd2d296 | 7521 | if (*args == 'f' |
55933a58 | 7522 | || (*args == 'l' |
1dc1e798 KR |
7523 | && (! USE_GLOBAL_POINTER_OPT |
7524 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7525 | || g_switch_value < 4 |
7526 | || (temp[0] == 0 && temp[1] == 0) | |
7527 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7528 | { |
7529 | imm_expr.X_op = O_constant; | |
b9129c6f | 7530 | if (! target_big_endian) |
a5586bdc | 7531 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7532 | else |
a5586bdc ILT |
7533 | imm_expr.X_add_number = bfd_getb32 (temp); |
7534 | } | |
7535 | else if (length > 4 | |
7536 | && ((temp[0] == 0 && temp[1] == 0) | |
7537 | || (temp[2] == 0 && temp[3] == 0)) | |
7538 | && ((temp[4] == 0 && temp[5] == 0) | |
7539 | || (temp[6] == 0 && temp[7] == 0))) | |
7540 | { | |
7541 | /* The value is simple enough to load with a | |
7542 | couple of instructions. In mips1 mode, set | |
7543 | imm_expr to the high order 32 bits and | |
7544 | offset_expr to the low order 32 bits. | |
7545 | Otherwise, set imm_expr to the entire 64 bit | |
7546 | constant. */ | |
7547 | if (mips_opts.isa < 3) | |
7548 | { | |
7549 | imm_expr.X_op = O_constant; | |
7550 | offset_expr.X_op = O_constant; | |
7551 | if (! target_big_endian) | |
7552 | { | |
7553 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7554 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7555 | } | |
7556 | else | |
7557 | { | |
7558 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7559 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7560 | } | |
7561 | if (offset_expr.X_add_number == 0) | |
7562 | offset_expr.X_op = O_absent; | |
7563 | } | |
7564 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7565 | { | |
7566 | imm_expr.X_op = O_constant; | |
7567 | if (! target_big_endian) | |
7568 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7569 | else | |
7570 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7571 | } | |
7572 | else | |
7573 | { | |
7574 | imm_expr.X_op = O_big; | |
7575 | imm_expr.X_add_number = 4; | |
7576 | if (! target_big_endian) | |
7577 | { | |
7578 | generic_bignum[0] = bfd_getl16 (temp); | |
7579 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7580 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7581 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7582 | } | |
7583 | else | |
7584 | { | |
7585 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7586 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7587 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7588 | generic_bignum[3] = bfd_getb16 (temp); | |
7589 | } | |
7590 | } | |
19ed8960 ILT |
7591 | } |
7592 | else | |
7593 | { | |
0dd2d296 ILT |
7594 | const char *newname; |
7595 | segT new_seg; | |
7596 | ||
19ed8960 ILT |
7597 | /* Switch to the right section. */ |
7598 | seg = now_seg; | |
7599 | subseg = now_subseg; | |
7600 | switch (*args) | |
7601 | { | |
0dd2d296 | 7602 | default: /* unused default case avoids warnings. */ |
19ed8960 | 7603 | case 'L': |
1113140a | 7604 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 7605 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 7606 | newname = ".lit8"; |
0dd2d296 ILT |
7607 | break; |
7608 | case 'F': | |
d2c71068 | 7609 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
7610 | break; |
7611 | case 'l': | |
1dc1e798 KR |
7612 | assert (!USE_GLOBAL_POINTER_OPT |
7613 | || g_switch_value >= 4); | |
0dd2d296 | 7614 | newname = ".lit4"; |
19ed8960 ILT |
7615 | break; |
7616 | } | |
0dd2d296 | 7617 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
7618 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
7619 | bfd_set_section_flags (stdoutput, new_seg, | |
7620 | (SEC_ALLOC | |
7621 | | SEC_LOAD | |
7622 | | SEC_READONLY | |
7623 | | SEC_DATA)); | |
e2e5acfa JW |
7624 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
7625 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7626 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
7627 | record_alignment (new_seg, 4); |
7628 | else | |
7629 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
7630 | if (seg == now_seg) |
7631 | as_bad ("Can't use floating point insn in this section"); | |
7632 | ||
7633 | /* Set the argument to the current address in the | |
6e8dda9c | 7634 | section. */ |
19ed8960 ILT |
7635 | offset_expr.X_op = O_symbol; |
7636 | offset_expr.X_add_symbol = | |
7637 | symbol_new ("L0\001", now_seg, | |
7638 | (valueT) frag_now_fix (), frag_now); | |
7639 | offset_expr.X_add_number = 0; | |
7640 | ||
7641 | /* Put the floating point number into the section. */ | |
604633ae | 7642 | p = frag_more ((int) length); |
19ed8960 ILT |
7643 | memcpy (p, temp, length); |
7644 | ||
7645 | /* Switch back to the original section. */ | |
7646 | subseg_set (seg, subseg); | |
7647 | } | |
7648 | } | |
670a50eb ILT |
7649 | continue; |
7650 | ||
7651 | case 'i': /* 16 bit unsigned immediate */ | |
7652 | case 'j': /* 16 bit signed immediate */ | |
7653 | imm_reloc = BFD_RELOC_LO16; | |
7654 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 7655 | if (c != '\0') |
670a50eb ILT |
7656 | { |
7657 | if (c != 'l') | |
7658 | { | |
5ac34ac3 | 7659 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
7660 | imm_expr.X_add_number = |
7661 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7662 | else if (c == 'h') | |
867a58b3 ILT |
7663 | { |
7664 | imm_reloc = BFD_RELOC_HI16_S; | |
7665 | imm_unmatched_hi = true; | |
7666 | } | |
670a50eb ILT |
7667 | else |
7668 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 7669 | } |
670a50eb | 7670 | } |
670a50eb ILT |
7671 | if (*args == 'i') |
7672 | { | |
344a8d61 | 7673 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7674 | || ((imm_expr.X_add_number < 0 |
7675 | || imm_expr.X_add_number >= 0x10000) | |
7676 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
7677 | { |
7678 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7679 | !strcmp (insn->name, insn[1].name)) | |
7680 | break; | |
9753202d ILT |
7681 | if (imm_expr.X_op != O_constant |
7682 | && imm_expr.X_op != O_big) | |
7683 | insn_error = "absolute expression required"; | |
7684 | else | |
7685 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 7686 | } |
670a50eb ILT |
7687 | } |
7688 | else | |
7689 | { | |
d9aba805 ILT |
7690 | int more; |
7691 | offsetT max; | |
7692 | ||
be22008b ILT |
7693 | /* The upper bound should be 0x8000, but |
7694 | unfortunately the MIPS assembler accepts numbers | |
7695 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
7696 | we want to be compatible. We only permit this |
7697 | extended range for an instruction which does not | |
7698 | provide any further alternates, since those | |
7699 | alternates may handle other cases. People should | |
7700 | use the numbers they mean, rather than relying on | |
7701 | a mysterious sign extension. */ | |
7702 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7703 | strcmp (insn->name, insn[1].name) == 0); | |
7704 | if (more) | |
7705 | max = 0x8000; | |
7706 | else | |
7707 | max = 0x10000; | |
344a8d61 | 7708 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7709 | || ((imm_expr.X_add_number < -0x8000 |
7710 | || imm_expr.X_add_number >= max) | |
7711 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7712 | || (more |
7713 | && imm_expr.X_add_number < 0 | |
3c83da8a | 7714 | && mips_opts.isa >= 3 |
d8a1c247 KR |
7715 | && imm_expr.X_unsigned |
7716 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7717 | { |
d9aba805 | 7718 | if (more) |
99c24539 | 7719 | break; |
9753202d ILT |
7720 | if (imm_expr.X_op != O_constant |
7721 | && imm_expr.X_op != O_big) | |
7722 | insn_error = "absolute expression required"; | |
7723 | else | |
7724 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7725 | } |
3d3c5039 | 7726 | } |
670a50eb ILT |
7727 | s = expr_end; |
7728 | continue; | |
7729 | ||
7730 | case 'o': /* 16 bit offset */ | |
7731 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7732 | |
7733 | /* If this value won't fit into a 16 bit offset, then go | |
7734 | find a macro that will generate the 32 bit offset | |
7735 | code pattern. As a special hack, we accept the | |
7736 | difference of two local symbols as a constant. This | |
7737 | is required to suppose embedded PIC switches, which | |
7738 | use an instruction which looks like | |
7739 | lw $4,$L12-$LS12($4) | |
7740 | The problem with handling this in a more general | |
7741 | fashion is that the macro function doesn't expect to | |
7742 | see anything which can be handled in a single | |
7743 | constant instruction. */ | |
6f0b87c3 SS |
7744 | if (c == 0 |
7745 | && (offset_expr.X_op != O_constant | |
7746 | || offset_expr.X_add_number >= 0x8000 | |
7747 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7748 | && (mips_pic != EMBEDDED_PIC |
7749 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7750 | || now_seg != text_section |
7751 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7752 | != text_section))) | |
670a50eb | 7753 | break; |
3d3c5039 | 7754 | |
670a50eb ILT |
7755 | offset_reloc = BFD_RELOC_LO16; |
7756 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7757 | { |
7758 | assert (offset_expr.X_op == O_constant); | |
7759 | offset_expr.X_add_number = | |
7760 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7761 | } | |
cc5703cd ILT |
7762 | s = expr_end; |
7763 | continue; | |
7764 | ||
7765 | case 'p': /* pc relative offset */ | |
7766 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7767 | my_getExpression (&offset_expr, s); | |
7768 | s = expr_end; | |
7769 | continue; | |
7770 | ||
7771 | case 'u': /* upper 16 bits */ | |
7772 | c = my_getSmallExpression (&imm_expr, s); | |
7773 | if (imm_expr.X_op == O_constant | |
7774 | && (imm_expr.X_add_number < 0 | |
7775 | || imm_expr.X_add_number >= 0x10000)) | |
7776 | as_bad ("lui expression not in range 0..65535"); | |
7777 | imm_reloc = BFD_RELOC_LO16; | |
7778 | if (c) | |
7779 | { | |
7780 | if (c != 'l') | |
7781 | { | |
7782 | if (imm_expr.X_op == O_constant) | |
7783 | imm_expr.X_add_number = | |
7784 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7785 | else if (c == 'h') | |
7786 | { | |
7787 | imm_reloc = BFD_RELOC_HI16_S; | |
7788 | imm_unmatched_hi = true; | |
7789 | } | |
7790 | else | |
7791 | imm_reloc = BFD_RELOC_HI16; | |
7792 | } | |
7793 | } | |
7794 | s = expr_end; | |
7795 | continue; | |
7796 | ||
7797 | case 'a': /* 26 bit address */ | |
7798 | my_getExpression (&offset_expr, s); | |
7799 | s = expr_end; | |
7800 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7801 | continue; | |
7802 | ||
7803 | case 'N': /* 3 bit branch condition code */ | |
7804 | case 'M': /* 3 bit compare condition code */ | |
7805 | if (strncmp (s, "$fcc", 4) != 0) | |
7806 | break; | |
7807 | s += 4; | |
7808 | regno = 0; | |
7809 | do | |
7810 | { | |
7811 | regno *= 10; | |
7812 | regno += *s - '0'; | |
7813 | ++s; | |
7814 | } | |
7815 | while (isdigit (*s)); | |
7816 | if (regno > 7) | |
7817 | as_bad ("invalid condition code register $fcc%d", regno); | |
7818 | if (*args == 'N') | |
7819 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7820 | else | |
7821 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7822 | continue; | |
7823 | ||
b3ed1af3 KR |
7824 | /* start-sanitize-vr5400 */ |
7825 | case 'e': /* must be at least one digit */ | |
7826 | my_getExpression (&imm_expr, s); | |
7827 | check_absolute_expr (ip, &imm_expr); | |
7828 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
7829 | { | |
7830 | as_bad ("bad byte vector index (%ld)", | |
7831 | (long) imm_expr.X_add_number); | |
7832 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7833 | } | |
7834 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
7835 | imm_expr.X_op = O_absent; | |
7836 | s = expr_end; | |
7837 | continue; | |
7838 | ||
7839 | case '%': | |
7840 | my_getExpression (&imm_expr, s); | |
7841 | check_absolute_expr (ip, &imm_expr); | |
7842 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
7843 | { | |
7844 | as_bad ("bad byte vector index (%ld)", | |
7845 | (long) imm_expr.X_add_number); | |
7846 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7847 | } | |
7848 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
7849 | imm_expr.X_op = O_absent; | |
7850 | s = expr_end; | |
7851 | continue; | |
7852 | ||
7853 | /* end-sanitize-vr5400 */ | |
cc5703cd | 7854 | default: |
b3ed1af3 | 7855 | as_bad ("bad char = '%c'\n", *args); |
cc5703cd ILT |
7856 | internalError (); |
7857 | } | |
7858 | break; | |
7859 | } | |
7860 | /* Args don't match. */ | |
7861 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7862 | !strcmp (insn->name, insn[1].name)) | |
7863 | { | |
7864 | ++insn; | |
7865 | s = argsStart; | |
7866 | continue; | |
7867 | } | |
7868 | insn_error = "illegal operands"; | |
7869 | return; | |
7870 | } | |
7871 | } | |
7872 | ||
7873 | /* This routine assembles an instruction into its binary format when | |
7874 | assembling for the mips16. As a side effect, it sets one of the | |
7875 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7876 | relocation to do if one of the operands is an address expression. |
7877 | It also sets mips16_small and mips16_ext if the user explicitly | |
7878 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7879 | |
7880 | static void | |
7881 | mips16_ip (str, ip) | |
7882 | char *str; | |
7883 | struct mips_cl_insn *ip; | |
7884 | { | |
7885 | char *s; | |
cc5703cd ILT |
7886 | const char *args; |
7887 | struct mips_opcode *insn; | |
7888 | char *argsstart; | |
7889 | unsigned int regno; | |
7890 | unsigned int lastregno = 0; | |
7891 | char *s_reset; | |
7892 | ||
7893 | insn_error = NULL; | |
7894 | ||
8728fa92 ILT |
7895 | mips16_small = false; |
7896 | mips16_ext = false; | |
cc5703cd ILT |
7897 | |
7898 | for (s = str; islower (*s); ++s) | |
7899 | ; | |
7900 | switch (*s) | |
7901 | { | |
7902 | case '\0': | |
7903 | break; | |
7904 | ||
7905 | case ' ': | |
7906 | *s++ = '\0'; | |
7907 | break; | |
7908 | ||
7909 | case '.': | |
7910 | if (s[1] == 't' && s[2] == ' ') | |
7911 | { | |
7912 | *s = '\0'; | |
8728fa92 | 7913 | mips16_small = true; |
cc5703cd ILT |
7914 | s += 3; |
7915 | break; | |
7916 | } | |
7917 | else if (s[1] == 'e' && s[2] == ' ') | |
7918 | { | |
7919 | *s = '\0'; | |
8728fa92 | 7920 | mips16_ext = true; |
cc5703cd ILT |
7921 | s += 3; |
7922 | break; | |
7923 | } | |
7924 | /* Fall through. */ | |
7925 | default: | |
7926 | insn_error = "unknown opcode"; | |
7927 | return; | |
7928 | } | |
7929 | ||
3c83da8a | 7930 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
7931 | mips16_small = true; |
7932 | ||
cc5703cd ILT |
7933 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7934 | { | |
7935 | insn_error = "unrecognized opcode"; | |
7936 | return; | |
7937 | } | |
7938 | ||
7939 | argsstart = s; | |
7940 | for (;;) | |
7941 | { | |
7942 | assert (strcmp (insn->name, str) == 0); | |
7943 | ||
7944 | ip->insn_mo = insn; | |
7945 | ip->insn_opcode = insn->match; | |
7946 | ip->use_extend = false; | |
7947 | imm_expr.X_op = O_absent; | |
7948 | imm_reloc = BFD_RELOC_UNUSED; | |
7949 | offset_expr.X_op = O_absent; | |
7950 | offset_reloc = BFD_RELOC_UNUSED; | |
7951 | for (args = insn->args; 1; ++args) | |
7952 | { | |
7953 | int c; | |
7954 | ||
7955 | if (*s == ' ') | |
7956 | ++s; | |
7957 | ||
7958 | /* In this switch statement we call break if we did not find | |
7959 | a match, continue if we did find a match, or return if we | |
7960 | are done. */ | |
7961 | ||
7962 | c = *args; | |
7963 | switch (c) | |
7964 | { | |
7965 | case '\0': | |
7966 | if (*s == '\0') | |
7967 | { | |
7968 | /* Stuff the immediate value in now, if we can. */ | |
7969 | if (imm_expr.X_op == O_constant | |
7970 | && imm_reloc > BFD_RELOC_UNUSED | |
7971 | && insn->pinfo != INSN_MACRO) | |
7972 | { | |
15e69f98 ILT |
7973 | mips16_immed ((char *) NULL, 0, |
7974 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7975 | imm_expr.X_add_number, true, mips16_small, |
7976 | mips16_ext, &ip->insn_opcode, | |
7977 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7978 | imm_expr.X_op = O_absent; |
7979 | imm_reloc = BFD_RELOC_UNUSED; | |
7980 | } | |
7981 | ||
7982 | return; | |
7983 | } | |
7984 | break; | |
7985 | ||
7986 | case ',': | |
7987 | if (*s++ == c) | |
7988 | continue; | |
7989 | s--; | |
7990 | switch (*++args) | |
7991 | { | |
7992 | case 'v': | |
7993 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7994 | continue; | |
7995 | case 'w': | |
7996 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7997 | continue; | |
7998 | } | |
7999 | break; | |
8000 | ||
8001 | case '(': | |
8002 | case ')': | |
8003 | if (*s++ == c) | |
8004 | continue; | |
8005 | break; | |
8006 | ||
8007 | case 'v': | |
8008 | case 'w': | |
8009 | if (s[0] != '$') | |
8010 | { | |
8011 | if (c == 'v') | |
8012 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8013 | else | |
8014 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8015 | ++args; | |
8016 | continue; | |
8017 | } | |
8018 | /* Fall through. */ | |
8019 | case 'x': | |
8020 | case 'y': | |
8021 | case 'z': | |
8022 | case 'Z': | |
8023 | case '0': | |
8024 | case 'S': | |
8025 | case 'R': | |
8026 | case 'X': | |
8027 | case 'Y': | |
8028 | if (s[0] != '$') | |
8029 | break; | |
8030 | s_reset = s; | |
8031 | if (isdigit (s[1])) | |
8032 | { | |
8033 | ++s; | |
8034 | regno = 0; | |
8035 | do | |
8036 | { | |
8037 | regno *= 10; | |
8038 | regno += *s - '0'; | |
8039 | ++s; | |
8040 | } | |
8041 | while (isdigit (*s)); | |
8042 | if (regno > 31) | |
8043 | { | |
8044 | as_bad ("invalid register number (%d)", regno); | |
8045 | regno = 2; | |
8046 | } | |
8047 | } | |
8048 | else | |
8049 | { | |
8050 | if (s[1] == 'f' && s[2] == 'p') | |
8051 | { | |
8052 | s += 3; | |
8053 | regno = FP; | |
8054 | } | |
8055 | else if (s[1] == 's' && s[2] == 'p') | |
8056 | { | |
8057 | s += 3; | |
8058 | regno = SP; | |
8059 | } | |
8060 | else if (s[1] == 'g' && s[2] == 'p') | |
8061 | { | |
8062 | s += 3; | |
8063 | regno = GP; | |
8064 | } | |
8065 | else if (s[1] == 'a' && s[2] == 't') | |
8066 | { | |
8067 | s += 3; | |
8068 | regno = AT; | |
8069 | } | |
8070 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8071 | { | |
8072 | s += 4; | |
8073 | regno = KT0; | |
8074 | } | |
8075 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8076 | { | |
8077 | s += 4; | |
8078 | regno = KT1; | |
8079 | } | |
8080 | else | |
8081 | break; | |
8082 | } | |
8083 | ||
8084 | if (*s == ' ') | |
8085 | ++s; | |
8086 | if (args[1] != *s) | |
8087 | { | |
8088 | if (c == 'v' || c == 'w') | |
8089 | { | |
8090 | regno = mips16_to_32_reg_map[lastregno]; | |
8091 | s = s_reset; | |
8092 | args++; | |
8093 | } | |
8094 | } | |
8095 | ||
8096 | switch (c) | |
8097 | { | |
8098 | case 'x': | |
8099 | case 'y': | |
8100 | case 'z': | |
8101 | case 'v': | |
8102 | case 'w': | |
8103 | case 'Z': | |
8104 | regno = mips32_to_16_reg_map[regno]; | |
8105 | break; | |
8106 | ||
8107 | case '0': | |
8108 | if (regno != 0) | |
8109 | regno = ILLEGAL_REG; | |
8110 | break; | |
8111 | ||
8112 | case 'S': | |
8113 | if (regno != SP) | |
8114 | regno = ILLEGAL_REG; | |
8115 | break; | |
8116 | ||
8117 | case 'R': | |
8118 | if (regno != RA) | |
8119 | regno = ILLEGAL_REG; | |
8120 | break; | |
8121 | ||
8122 | case 'X': | |
8123 | case 'Y': | |
3c83da8a | 8124 | if (regno == AT && ! mips_opts.noat) |
cc5703cd ILT |
8125 | as_warn ("used $at without \".set noat\""); |
8126 | break; | |
8127 | ||
8128 | default: | |
8129 | internalError (); | |
8130 | } | |
8131 | ||
8132 | if (regno == ILLEGAL_REG) | |
8133 | break; | |
8134 | ||
8135 | switch (c) | |
8136 | { | |
8137 | case 'x': | |
8138 | case 'v': | |
8139 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8140 | break; | |
8141 | case 'y': | |
8142 | case 'w': | |
8143 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8144 | break; | |
8145 | case 'z': | |
8146 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8147 | break; | |
8148 | case 'Z': | |
8149 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8150 | case '0': | |
8151 | case 'S': | |
8152 | case 'R': | |
8153 | break; | |
8154 | case 'X': | |
8155 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8156 | break; | |
8157 | case 'Y': | |
8158 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8159 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8160 | break; | |
8161 | default: | |
8162 | internalError (); | |
8163 | } | |
8164 | ||
8165 | lastregno = regno; | |
8166 | continue; | |
8167 | ||
8168 | case 'P': | |
8169 | if (strncmp (s, "$pc", 3) == 0) | |
8170 | { | |
8171 | s += 3; | |
8172 | continue; | |
8173 | } | |
8174 | break; | |
8175 | ||
8176 | case '<': | |
8177 | case '>': | |
8178 | case '[': | |
8179 | case ']': | |
8180 | case '4': | |
8181 | case '5': | |
8182 | case 'H': | |
8183 | case 'W': | |
8184 | case 'D': | |
8185 | case 'j': | |
8186 | case '8': | |
8187 | case 'V': | |
8188 | case 'C': | |
8189 | case 'U': | |
8190 | case 'k': | |
8191 | case 'K': | |
16262668 ILT |
8192 | if (s[0] == '%' |
8193 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8194 | { | |
8195 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8196 | and generate the appropriate reloc. If the text | |
8197 | inside %gprel is not a symbol name with an | |
8198 | optional offset, then we generate a normal reloc | |
8199 | and will probably fail later. */ | |
8200 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8201 | if (imm_expr.X_op == O_symbol) | |
8202 | { | |
8203 | mips16_ext = true; | |
8204 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8205 | s = expr_end; | |
8206 | ip->use_extend = true; | |
8207 | ip->extend = 0; | |
8208 | continue; | |
8209 | } | |
8210 | } | |
8211 | else | |
8212 | { | |
8213 | /* Just pick up a normal expression. */ | |
8214 | my_getExpression (&imm_expr, s); | |
8215 | } | |
8216 | ||
ebf28372 ILT |
8217 | if (imm_expr.X_op == O_register) |
8218 | { | |
8219 | /* What we thought was an expression turned out to | |
8220 | be a register. */ | |
8221 | ||
8222 | if (s[0] == '(' && args[1] == '(') | |
8223 | { | |
8224 | /* It looks like the expression was omitted | |
8225 | before a register indirection, which means | |
8226 | that the expression is implicitly zero. We | |
8227 | still set up imm_expr, so that we handle | |
8228 | explicit extensions correctly. */ | |
8229 | imm_expr.X_op = O_constant; | |
8230 | imm_expr.X_add_number = 0; | |
8231 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8232 | continue; | |
8233 | } | |
8234 | ||
8235 | break; | |
8236 | } | |
8237 | ||
cc5703cd ILT |
8238 | /* We need to relax this instruction. */ |
8239 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8240 | s = expr_end; | |
8241 | continue; | |
8242 | ||
8243 | case 'p': | |
8244 | case 'q': | |
8245 | case 'A': | |
8246 | case 'B': | |
8247 | case 'E': | |
8248 | /* We use offset_reloc rather than imm_reloc for the PC | |
8249 | relative operands. This lets macros with both | |
8250 | immediate and address operands work correctly. */ | |
670a50eb | 8251 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8252 | |
8253 | if (offset_expr.X_op == O_register) | |
8254 | break; | |
8255 | ||
cc5703cd ILT |
8256 | /* We need to relax this instruction. */ |
8257 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8258 | s = expr_end; |
8259 | continue; | |
8260 | ||
cc5703cd ILT |
8261 | case '6': /* break code */ |
8262 | my_getExpression (&imm_expr, s); | |
8263 | check_absolute_expr (ip, &imm_expr); | |
8264 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8265 | { |
cc5703cd ILT |
8266 | as_warn ("Invalid value for `%s' (%lu)", |
8267 | ip->insn_mo->name, | |
8268 | (unsigned long) imm_expr.X_add_number); | |
8269 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8270 | } |
cc5703cd ILT |
8271 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8272 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8273 | s = expr_end; |
8274 | continue; | |
3d3c5039 | 8275 | |
670a50eb ILT |
8276 | case 'a': /* 26 bit address */ |
8277 | my_getExpression (&offset_expr, s); | |
8278 | s = expr_end; | |
cc5703cd ILT |
8279 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8280 | ip->insn_opcode <<= 16; | |
670a50eb | 8281 | continue; |
3d3c5039 | 8282 | |
cc5703cd ILT |
8283 | case 'l': /* register list for entry macro */ |
8284 | case 'L': /* register list for exit macro */ | |
8285 | { | |
8286 | int mask; | |
8287 | ||
8288 | if (c == 'l') | |
8289 | mask = 0; | |
8290 | else | |
8291 | mask = 7 << 3; | |
8292 | while (*s != '\0') | |
8293 | { | |
c9167640 | 8294 | int freg, reg1, reg2; |
cc5703cd ILT |
8295 | |
8296 | while (*s == ' ' || *s == ',') | |
8297 | ++s; | |
8298 | if (*s != '$') | |
8299 | { | |
8300 | as_bad ("can't parse register list"); | |
8301 | break; | |
8302 | } | |
8303 | ++s; | |
c9167640 ILT |
8304 | if (*s != 'f') |
8305 | freg = 0; | |
8306 | else | |
8307 | { | |
8308 | freg = 1; | |
8309 | ++s; | |
8310 | } | |
cc5703cd ILT |
8311 | reg1 = 0; |
8312 | while (isdigit (*s)) | |
8313 | { | |
8314 | reg1 *= 10; | |
8315 | reg1 += *s - '0'; | |
8316 | ++s; | |
8317 | } | |
8318 | if (*s == ' ') | |
8319 | ++s; | |
8320 | if (*s != '-') | |
8321 | reg2 = reg1; | |
8322 | else | |
8323 | { | |
8324 | ++s; | |
8325 | if (*s != '$') | |
8326 | break; | |
8327 | ++s; | |
c9167640 ILT |
8328 | if (freg) |
8329 | { | |
8330 | if (*s == 'f') | |
8331 | ++s; | |
8332 | else | |
8333 | { | |
8334 | as_bad ("invalid register list"); | |
8335 | break; | |
8336 | } | |
8337 | } | |
cc5703cd ILT |
8338 | reg2 = 0; |
8339 | while (isdigit (*s)) | |
8340 | { | |
8341 | reg2 *= 10; | |
8342 | reg2 += *s - '0'; | |
8343 | ++s; | |
8344 | } | |
8345 | } | |
c9167640 ILT |
8346 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8347 | { | |
8348 | mask &= ~ (7 << 3); | |
8349 | mask |= 5 << 3; | |
8350 | } | |
8351 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8352 | { | |
8353 | mask &= ~ (7 << 3); | |
8354 | mask |= 6 << 3; | |
8355 | } | |
8356 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8357 | mask |= (reg2 - 3) << 3; |
8358 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8359 | mask |= (reg2 - 15) << 1; | |
8360 | else if (reg1 == 31 && reg2 == 31) | |
8361 | mask |= 1; | |
8362 | else | |
c9167640 ILT |
8363 | { |
8364 | as_bad ("invalid register list"); | |
8365 | break; | |
8366 | } | |
cc5703cd | 8367 | } |
c9167640 ILT |
8368 | /* The mask is filled in in the opcode table for the |
8369 | benefit of the disassembler. We remove it before | |
8370 | applying the actual mask. */ | |
8371 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8372 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8373 | } | |
8374 | continue; | |
d8a1c247 | 8375 | |
56bb6eee ILT |
8376 | case 'e': /* extend code */ |
8377 | my_getExpression (&imm_expr, s); | |
8378 | check_absolute_expr (ip, &imm_expr); | |
8379 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8380 | { | |
8381 | as_warn ("Invalid value for `%s' (%lu)", | |
8382 | ip->insn_mo->name, | |
8383 | (unsigned long) imm_expr.X_add_number); | |
8384 | imm_expr.X_add_number &= 0x7ff; | |
8385 | } | |
8386 | ip->insn_opcode |= imm_expr.X_add_number; | |
8387 | imm_expr.X_op = O_absent; | |
8388 | s = expr_end; | |
8389 | continue; | |
8390 | ||
3d3c5039 | 8391 | default: |
670a50eb | 8392 | internalError (); |
3d3c5039 | 8393 | } |
670a50eb | 8394 | break; |
3d3c5039 | 8395 | } |
cc5703cd | 8396 | |
670a50eb | 8397 | /* Args don't match. */ |
cc5703cd ILT |
8398 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8399 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8400 | { |
8401 | ++insn; | |
cc5703cd | 8402 | s = argsstart; |
670a50eb | 8403 | continue; |
3d3c5039 | 8404 | } |
cc5703cd | 8405 | |
9753202d | 8406 | insn_error = "illegal operands"; |
cc5703cd | 8407 | |
670a50eb | 8408 | return; |
3d3c5039 ILT |
8409 | } |
8410 | } | |
8411 | ||
cc5703cd ILT |
8412 | /* This structure holds information we know about a mips16 immediate |
8413 | argument type. */ | |
8414 | ||
8415 | struct mips16_immed_operand | |
8416 | { | |
8417 | /* The type code used in the argument string in the opcode table. */ | |
8418 | int type; | |
8419 | /* The number of bits in the short form of the opcode. */ | |
8420 | int nbits; | |
8421 | /* The number of bits in the extended form of the opcode. */ | |
8422 | int extbits; | |
8423 | /* The amount by which the short form is shifted when it is used; | |
8424 | for example, the sw instruction has a shift count of 2. */ | |
8425 | int shift; | |
8426 | /* The amount by which the short form is shifted when it is stored | |
8427 | into the instruction code. */ | |
8428 | int op_shift; | |
8429 | /* Non-zero if the short form is unsigned. */ | |
8430 | int unsp; | |
8431 | /* Non-zero if the extended form is unsigned. */ | |
8432 | int extu; | |
8433 | /* Non-zero if the value is PC relative. */ | |
8434 | int pcrel; | |
8435 | }; | |
8436 | ||
8437 | /* The mips16 immediate operand types. */ | |
8438 | ||
8439 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8440 | { | |
8441 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8442 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8443 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8444 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8445 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8446 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8447 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8448 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8449 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8450 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8451 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8452 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8453 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8454 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8455 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8456 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8457 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8458 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8459 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8460 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8461 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8462 | }; | |
8463 | ||
8464 | #define MIPS16_NUM_IMMED \ | |
8465 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8466 | ||
8467 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8468 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8469 | whether an extended value is needed; if one is needed, it sets | |
8470 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8471 | If SMALL is true, an unextended opcode was explicitly requested. | |
8472 | If EXT is true, an extended opcode was explicitly requested. If | |
8473 | WARN is true, warn if EXT does not match reality. */ | |
8474 | ||
8475 | static void | |
15e69f98 ILT |
8476 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
8477 | extend) | |
8478 | char *file; | |
8479 | unsigned int line; | |
cc5703cd ILT |
8480 | int type; |
8481 | offsetT val; | |
8482 | boolean warn; | |
8483 | boolean small; | |
8484 | boolean ext; | |
8485 | unsigned long *insn; | |
8486 | boolean *use_extend; | |
8487 | unsigned short *extend; | |
8488 | { | |
8489 | register const struct mips16_immed_operand *op; | |
8490 | int mintiny, maxtiny; | |
8491 | boolean needext; | |
8492 | ||
8493 | op = mips16_immed_operands; | |
8494 | while (op->type != type) | |
8495 | { | |
8496 | ++op; | |
8497 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8498 | } | |
8499 | ||
8500 | if (op->unsp) | |
8501 | { | |
8502 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8503 | { | |
8504 | mintiny = 1; | |
8505 | maxtiny = 1 << op->nbits; | |
8506 | } | |
8507 | else | |
8508 | { | |
8509 | mintiny = 0; | |
8510 | maxtiny = (1 << op->nbits) - 1; | |
8511 | } | |
8512 | } | |
8513 | else | |
8514 | { | |
8515 | mintiny = - (1 << (op->nbits - 1)); | |
8516 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8517 | } | |
8518 | ||
8519 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8520 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8521 | val /= 2; |
cc5703cd ILT |
8522 | |
8523 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8524 | || val < (mintiny << op->shift) | |
8525 | || val > (maxtiny << op->shift)) | |
8526 | needext = true; | |
8527 | else | |
8528 | needext = false; | |
8529 | ||
8530 | if (warn && ext && ! needext) | |
15e69f98 | 8531 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 8532 | if (small && needext) |
15e69f98 | 8533 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
8534 | |
8535 | if (small || (! ext && ! needext)) | |
8536 | { | |
8537 | int insnval; | |
8538 | ||
8539 | *use_extend = false; | |
8540 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8541 | insnval <<= op->op_shift; | |
8542 | *insn |= insnval; | |
8543 | } | |
8544 | else | |
8545 | { | |
8546 | long minext, maxext; | |
8547 | int extval; | |
8548 | ||
8549 | if (op->extu) | |
8550 | { | |
8551 | minext = 0; | |
8552 | maxext = (1 << op->extbits) - 1; | |
8553 | } | |
8554 | else | |
8555 | { | |
8556 | minext = - (1 << (op->extbits - 1)); | |
8557 | maxext = (1 << (op->extbits - 1)) - 1; | |
8558 | } | |
8559 | if (val < minext || val > maxext) | |
15e69f98 ILT |
8560 | as_bad_where (file, line, |
8561 | "operand value out of range for instruction"); | |
cc5703cd ILT |
8562 | |
8563 | *use_extend = true; | |
8564 | if (op->extbits == 16) | |
8565 | { | |
8566 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8567 | val &= 0x1f; | |
8568 | } | |
8569 | else if (op->extbits == 15) | |
8570 | { | |
8571 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8572 | val &= 0xf; | |
8573 | } | |
8574 | else | |
8575 | { | |
8576 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8577 | val = 0; | |
8578 | } | |
8579 | ||
8580 | *extend = (unsigned short) extval; | |
8581 | *insn |= val; | |
8582 | } | |
8583 | } | |
8584 | \f | |
3d3c5039 ILT |
8585 | #define LP '(' |
8586 | #define RP ')' | |
8587 | ||
8588 | static int | |
8589 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8590 | expressionS *ep; |
8591 | char *str; | |
3d3c5039 | 8592 | { |
670a50eb ILT |
8593 | char *sp; |
8594 | int c = 0; | |
8595 | ||
8596 | if (*str == ' ') | |
8597 | str++; | |
8598 | if (*str == LP | |
8599 | || (*str == '%' && | |
8600 | ((str[1] == 'h' && str[2] == 'i') | |
8601 | || (str[1] == 'H' && str[2] == 'I') | |
8602 | || (str[1] == 'l' && str[2] == 'o')) | |
8603 | && str[3] == LP)) | |
8604 | { | |
8605 | if (*str == LP) | |
8606 | c = 0; | |
8607 | else | |
8608 | { | |
8609 | c = str[1]; | |
8610 | str += 3; | |
8611 | } | |
8612 | ||
8613 | /* | |
8614 | * A small expression may be followed by a base register. | |
8615 | * Scan to the end of this operand, and then back over a possible | |
8616 | * base register. Then scan the small expression up to that | |
8617 | * point. (Based on code in sparc.c...) | |
8618 | */ | |
8619 | for (sp = str; *sp && *sp != ','; sp++) | |
8620 | ; | |
8621 | if (sp - 4 >= str && sp[-1] == RP) | |
8622 | { | |
8623 | if (isdigit (sp[-2])) | |
8624 | { | |
8625 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
8626 | ; | |
8627 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8628 | { | |
8629 | sp--; | |
8630 | goto do_it; | |
3d3c5039 | 8631 | } |
670a50eb ILT |
8632 | } |
8633 | else if (sp - 5 >= str | |
8634 | && sp[-5] == LP | |
8635 | && sp[-4] == '$' | |
8636 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8637 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8638 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8639 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8640 | { | |
8641 | sp -= 5; | |
3d3c5039 | 8642 | do_it: |
670a50eb ILT |
8643 | if (sp == str) |
8644 | { | |
8645 | /* no expression means zero offset */ | |
8646 | if (c) | |
8647 | { | |
8648 | /* %xx(reg) is an error */ | |
5ac34ac3 | 8649 | ep->X_op = O_absent; |
670a50eb | 8650 | expr_end = str - 3; |
3d3c5039 | 8651 | } |
670a50eb ILT |
8652 | else |
8653 | { | |
52aa70b5 | 8654 | ep->X_op = O_constant; |
670a50eb ILT |
8655 | expr_end = sp; |
8656 | } | |
8657 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 8658 | ep->X_op_symbol = NULL; |
670a50eb ILT |
8659 | ep->X_add_number = 0; |
8660 | } | |
8661 | else | |
8662 | { | |
8663 | *sp = '\0'; | |
8664 | my_getExpression (ep, str); | |
8665 | *sp = LP; | |
3d3c5039 | 8666 | } |
670a50eb | 8667 | return c; |
3d3c5039 ILT |
8668 | } |
8669 | } | |
8670 | } | |
670a50eb ILT |
8671 | my_getExpression (ep, str); |
8672 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
8673 | } |
8674 | ||
8675 | static void | |
8676 | my_getExpression (ep, str) | |
670a50eb ILT |
8677 | expressionS *ep; |
8678 | char *str; | |
3d3c5039 | 8679 | { |
670a50eb | 8680 | char *save_in; |
670a50eb ILT |
8681 | |
8682 | save_in = input_line_pointer; | |
8683 | input_line_pointer = str; | |
5ac34ac3 | 8684 | expression (ep); |
670a50eb ILT |
8685 | expr_end = input_line_pointer; |
8686 | input_line_pointer = save_in; | |
eb17f56c ILT |
8687 | |
8688 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8689 | then we bump the value of the symbol by 1 since that is how other | |
8690 | text symbols are handled. We don't bother to handle complex | |
8691 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 8692 | if (mips_opts.mips16 |
eb17f56c ILT |
8693 | && ep->X_op == O_symbol |
8694 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8695 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
8696 | && ep->X_add_symbol->sy_frag == frag_now | |
8697 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
8698 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
8699 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
8700 | } |
8701 | ||
becfe05e ILT |
8702 | /* Turn a string in input_line_pointer into a floating point constant |
8703 | of type type, and store the appropriate bytes in *litP. The number | |
8704 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8705 | returned, or NULL on OK. */ | |
8706 | ||
3d3c5039 | 8707 | char * |
670a50eb | 8708 | md_atof (type, litP, sizeP) |
becfe05e | 8709 | int type; |
3d3c5039 ILT |
8710 | char *litP; |
8711 | int *sizeP; | |
8712 | { | |
becfe05e ILT |
8713 | int prec; |
8714 | LITTLENUM_TYPE words[4]; | |
8715 | char *t; | |
8716 | int i; | |
8717 | ||
8718 | switch (type) | |
8719 | { | |
8720 | case 'f': | |
8721 | prec = 2; | |
8722 | break; | |
8723 | ||
8724 | case 'd': | |
8725 | prec = 4; | |
8726 | break; | |
8727 | ||
8728 | default: | |
8729 | *sizeP = 0; | |
8730 | return "bad call to md_atof"; | |
8731 | } | |
8732 | ||
8733 | t = atof_ieee (input_line_pointer, type, words); | |
8734 | if (t) | |
8735 | input_line_pointer = t; | |
8736 | ||
8737 | *sizeP = prec * 2; | |
8738 | ||
b9129c6f | 8739 | if (! target_big_endian) |
becfe05e ILT |
8740 | { |
8741 | for (i = prec - 1; i >= 0; i--) | |
8742 | { | |
8743 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8744 | litP += 2; | |
8745 | } | |
8746 | } | |
8747 | else | |
8748 | { | |
8749 | for (i = 0; i < prec; i++) | |
8750 | { | |
8751 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8752 | litP += 2; | |
8753 | } | |
8754 | } | |
8755 | ||
670a50eb | 8756 | return NULL; |
3d3c5039 ILT |
8757 | } |
8758 | ||
8759 | void | |
8760 | md_number_to_chars (buf, val, n) | |
8761 | char *buf; | |
918692a5 | 8762 | valueT val; |
3d3c5039 ILT |
8763 | int n; |
8764 | { | |
b9129c6f ILT |
8765 | if (target_big_endian) |
8766 | number_to_chars_bigendian (buf, val, n); | |
8767 | else | |
8768 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8769 | } |
f3d817d8 | 8770 | \f |
e8d4d475 | 8771 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8772 | |
f3d817d8 DM |
8773 | struct option md_longopts[] = { |
8774 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8775 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8776 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8777 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8778 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8779 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8780 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8781 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8782 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8783 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8784 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8785 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8786 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8787 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8788 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8789 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8790 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8791 | {"break", no_argument, NULL, OPTION_BREAK}, |
8792 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8793 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8794 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8795 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8796 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8797 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8798 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8799 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8800 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8801 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8802 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8803 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8804 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8805 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8806 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8807 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8808 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8809 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8810 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8811 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8812 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8813 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8814 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8815 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8816 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8817 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8818 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
8819 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8820 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8821 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8822 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
8823 | |
8824 | /* start-sanitize-tx19 */ | |
8825 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
8826 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
8827 | /* end-sanitize-tx19 */ | |
f3d817d8 | 8828 | |
aa2e0460 KR |
8829 | /* start-sanitize-vr5400 */ |
8830 | #define OPTION_M5400 (OPTION_MD_BASE + 28) | |
8831 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
8832 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
8833 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
8834 | ||
8835 | /* end-sanitize-vr5400 */ | |
42444087 GRK |
8836 | /* start-sanitize-tx49 */ |
8837 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
8838 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
8839 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
8840 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
8841 | ||
8842 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
8843 | /* start-sanitize-vr4320 */ |
8844 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
8845 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
8846 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
8847 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
8848 | ||
8849 | /* end-sanitize-vr4320 */ | |
d8a1c247 | 8850 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8851 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8852 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8853 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8854 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8855 | #ifdef OBJ_ELF |
f3d817d8 | 8856 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8857 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8858 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8859 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8860 | {"32", no_argument, NULL, OPTION_32}, |
8861 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8862 | #endif |
8863 | ||
8864 | {NULL, no_argument, NULL, 0} | |
8865 | }; | |
8866 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8867 | |
8868 | int | |
f3d817d8 DM |
8869 | md_parse_option (c, arg) |
8870 | int c; | |
8871 | char *arg; | |
3d3c5039 | 8872 | { |
f3d817d8 | 8873 | switch (c) |
670a50eb | 8874 | { |
f3d817d8 DM |
8875 | case OPTION_TRAP: |
8876 | mips_trap = 1; | |
8877 | break; | |
670a50eb | 8878 | |
f3d817d8 DM |
8879 | case OPTION_BREAK: |
8880 | mips_trap = 0; | |
8881 | break; | |
8882 | ||
e8d4d475 | 8883 | case OPTION_EB: |
1dc1e798 | 8884 | target_big_endian = 1; |
e8d4d475 | 8885 | break; |
04cb3372 | 8886 | |
e8d4d475 | 8887 | case OPTION_EL: |
1dc1e798 | 8888 | target_big_endian = 0; |
f3d817d8 | 8889 | break; |
670a50eb | 8890 | |
f3d817d8 DM |
8891 | case 'O': |
8892 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8893 | mips_optimize = 1; |
8894 | else | |
8895 | mips_optimize = 2; | |
f3d817d8 | 8896 | break; |
0aa07269 | 8897 | |
f3d817d8 | 8898 | case 'g': |
22ba90ce ILT |
8899 | if (arg == NULL) |
8900 | mips_debug = 2; | |
8901 | else | |
8902 | mips_debug = atoi (arg); | |
8903 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8904 | optimizations which limit full symbolic debugging. We take | |
8905 | that to be equivalent to -O0. */ | |
8906 | if (mips_debug == 2) | |
05874c2e | 8907 | mips_optimize = 1; |
f3d817d8 | 8908 | break; |
4e95866e | 8909 | |
f3d817d8 | 8910 | case OPTION_MIPS1: |
3c83da8a | 8911 | mips_opts.isa = 1; |
f3d817d8 | 8912 | break; |
8358c818 | 8913 | |
f3d817d8 | 8914 | case OPTION_MIPS2: |
3c83da8a | 8915 | mips_opts.isa = 2; |
f3d817d8 | 8916 | break; |
8358c818 | 8917 | |
f3d817d8 | 8918 | case OPTION_MIPS3: |
3c83da8a | 8919 | mips_opts.isa = 3; |
f3d817d8 | 8920 | break; |
8358c818 | 8921 | |
d8a1c247 | 8922 | case OPTION_MIPS4: |
3c83da8a | 8923 | mips_opts.isa = 4; |
d8a1c247 KR |
8924 | break; |
8925 | ||
f3d817d8 DM |
8926 | case OPTION_MCPU: |
8927 | { | |
8928 | char *p; | |
8929 | ||
8930 | /* Identify the processor type */ | |
8931 | p = arg; | |
8932 | if (strcmp (p, "default") == 0 | |
8933 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8934 | mips_cpu = -1; |
f3d817d8 DM |
8935 | else |
8936 | { | |
c625fc23 JSC |
8937 | int sv = 0; |
8938 | ||
8939 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8940 | processor. */ | |
8941 | if (*p == 'v' || *p == 'V') | |
8942 | { | |
8943 | sv = 1; | |
8944 | p++; | |
8945 | } | |
8946 | ||
f3d817d8 DM |
8947 | if (*p == 'r' || *p == 'R') |
8948 | p++; | |
8358c818 | 8949 | |
4bb0cc41 | 8950 | mips_cpu = -1; |
f3d817d8 DM |
8951 | switch (*p) |
8952 | { | |
d8a1c247 KR |
8953 | case '1': |
8954 | if (strcmp (p, "10000") == 0 | |
8955 | || strcmp (p, "10k") == 0 | |
8956 | || strcmp (p, "10K") == 0) | |
8957 | mips_cpu = 10000; | |
4e96260f JL |
8958 | /* start-sanitize-tx19 */ |
8959 | else if (strcmp (p, "1900") == 0) | |
8960 | mips_cpu = 3900; | |
8961 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
8962 | break; |
8963 | ||
f3d817d8 DM |
8964 | case '2': |
8965 | if (strcmp (p, "2000") == 0 | |
8966 | || strcmp (p, "2k") == 0 | |
8967 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8968 | mips_cpu = 2000; |
f3d817d8 | 8969 | break; |
8358c818 | 8970 | |
f3d817d8 DM |
8971 | case '3': |
8972 | if (strcmp (p, "3000") == 0 | |
8973 | || strcmp (p, "3k") == 0 | |
8974 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8975 | mips_cpu = 3000; |
5c6f5923 GRK |
8976 | else if (strcmp (p, "3900") == 0) |
8977 | mips_cpu = 3900; | |
f3d817d8 | 8978 | break; |
8358c818 | 8979 | |
f3d817d8 DM |
8980 | case '4': |
8981 | if (strcmp (p, "4000") == 0 | |
8982 | || strcmp (p, "4k") == 0 | |
8c63448a | 8983 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8984 | mips_cpu = 4000; |
c625fc23 | 8985 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 8986 | mips_cpu = 4100; |
c625fc23 JSC |
8987 | else if (strcmp (p, "4300") == 0) |
8988 | mips_cpu = 4300; | |
2d035a50 GRK |
8989 | /* start-sanitize-vr4320 */ |
8990 | else if (strcmp (p, "4320") == 0) | |
8991 | mips_cpu = 4320; | |
8992 | /* end-sanitize-vr4320 */ | |
8c63448a | 8993 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8994 | mips_cpu = 4400; |
8c63448a | 8995 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8996 | mips_cpu = 4600; |
b2b8c24e | 8997 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 8998 | mips_cpu = 4650; |
4ebda395 GRK |
8999 | /* start-sanitize-tx49 */ |
9000 | else if (strcmp (p, "4900") == 0) | |
9001 | mips_cpu = 4900; | |
9002 | /* end-sanitize-tx49 */ | |
e532b44c | 9003 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9004 | mips_cpu = 4010; |
f3d817d8 | 9005 | break; |
8358c818 | 9006 | |
517078c1 ILT |
9007 | case '5': |
9008 | if (strcmp (p, "5000") == 0 | |
9009 | || strcmp (p, "5k") == 0 | |
9010 | || strcmp (p, "5K") == 0) | |
9011 | mips_cpu = 5000; | |
aa2e0460 KR |
9012 | /* start-sanitize-vr5400 */ |
9013 | else if (strcmp (p, "5400") == 0) | |
9014 | mips_cpu = 5400; | |
9015 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
9016 | /* start-sanitize-r5900 */ |
9017 | else if (strcmp (p, "5900") == 0) | |
9018 | mips_cpu = 5900; | |
9019 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9020 | break; |
9021 | ||
f3d817d8 DM |
9022 | case '6': |
9023 | if (strcmp (p, "6000") == 0 | |
9024 | || strcmp (p, "6k") == 0 | |
9025 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9026 | mips_cpu = 6000; |
f3d817d8 | 9027 | break; |
55933a58 | 9028 | |
d8a1c247 KR |
9029 | case '8': |
9030 | if (strcmp (p, "8000") == 0 | |
9031 | || strcmp (p, "8k") == 0 | |
9032 | || strcmp (p, "8K") == 0) | |
9033 | mips_cpu = 8000; | |
9034 | break; | |
9035 | ||
55933a58 ILT |
9036 | case 'o': |
9037 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9038 | mips_cpu = 4600; |
55933a58 | 9039 | break; |
f3d817d8 | 9040 | } |
8358c818 | 9041 | |
b3ed1af3 KR |
9042 | if (sv |
9043 | && (mips_cpu != 4300 | |
9044 | && mips_cpu != 4100 | |
2d035a50 GRK |
9045 | /* start-sanitize-vr4320 */ |
9046 | && mips_cpu != 4320 | |
9047 | /* end-sanitize-vr4320 */ | |
b3ed1af3 KR |
9048 | /* start-sanitize-vr5400 */ |
9049 | && mips_cpu != 5400 | |
9050 | /* end-sanitize-vr5400 */ | |
9051 | && mips_cpu != 5000)) | |
c625fc23 JSC |
9052 | { |
9053 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
9054 | return 0; | |
9055 | } | |
9056 | ||
4bb0cc41 | 9057 | if (mips_cpu == -1) |
f3d817d8 DM |
9058 | { |
9059 | as_bad ("invalid architecture -mcpu=%s", arg); | |
9060 | return 0; | |
9061 | } | |
9062 | } | |
9063 | } | |
9064 | break; | |
8358c818 | 9065 | |
b2b8c24e ILT |
9066 | case OPTION_M4650: |
9067 | mips_4650 = 1; | |
9068 | break; | |
9069 | ||
9070 | case OPTION_NO_M4650: | |
9071 | mips_4650 = 0; | |
9072 | break; | |
9073 | ||
e532b44c ILT |
9074 | case OPTION_M4010: |
9075 | mips_4010 = 1; | |
9076 | break; | |
9077 | ||
9078 | case OPTION_NO_M4010: | |
9079 | mips_4010 = 0; | |
9080 | break; | |
9081 | ||
c625fc23 JSC |
9082 | case OPTION_M4100: |
9083 | mips_4100 = 1; | |
9084 | break; | |
9085 | ||
9086 | case OPTION_NO_M4100: | |
9087 | mips_4100 = 0; | |
9088 | break; | |
9089 | ||
276c2d7d GRK |
9090 | /* start-sanitize-r5900 */ |
9091 | case OPTION_M5900: | |
9092 | mips_5900 = 1; | |
9093 | break; | |
9094 | ||
9095 | case OPTION_NO_M5900: | |
9096 | mips_5900 = 0; | |
9097 | break; | |
9098 | /* end-sanitize-r5900 */ | |
9099 | ||
2d035a50 GRK |
9100 | /* start-sanitize-vr4320 */ |
9101 | case OPTION_M4320: | |
9102 | mips_4320 = 1; | |
9103 | break; | |
9104 | ||
9105 | case OPTION_NO_M4320: | |
9106 | mips_4320 = 0; | |
9107 | break; | |
9108 | ||
9109 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
9110 | /* start-sanitize-vr5400 */ |
9111 | case OPTION_M5400: | |
9112 | mips_5400 = 1; | |
9113 | break; | |
9114 | ||
9115 | case OPTION_NO_M5400: | |
9116 | mips_5400 = 0; | |
9117 | break; | |
9118 | ||
9119 | /* end-sanitize-vr5400 */ | |
5c6f5923 GRK |
9120 | case OPTION_M3900: |
9121 | mips_3900 = 1; | |
9122 | break; | |
9123 | ||
9124 | case OPTION_NO_M3900: | |
9125 | mips_3900 = 0; | |
9126 | break; | |
9127 | ||
42444087 GRK |
9128 | /* start-sanitize-tx49 */ |
9129 | case OPTION_M4900: | |
9130 | mips_4900 = 1; | |
9131 | break; | |
9132 | ||
9133 | case OPTION_NO_M4900: | |
9134 | mips_4900 = 0; | |
9135 | break; | |
9136 | ||
9137 | /* end-sanitize-tx49 */ | |
cc5703cd | 9138 | case OPTION_MIPS16: |
3c83da8a | 9139 | mips_opts.mips16 = 1; |
4a1cb507 | 9140 | mips_no_prev_insn (false); |
cc5703cd ILT |
9141 | break; |
9142 | ||
9143 | case OPTION_NO_MIPS16: | |
3c83da8a | 9144 | mips_opts.mips16 = 0; |
4a1cb507 | 9145 | mips_no_prev_insn (false); |
cc5703cd ILT |
9146 | break; |
9147 | ||
f3d817d8 | 9148 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9149 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9150 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
9151 | { |
9152 | as_bad ("-G may not be used with embedded PIC code"); | |
9153 | return 0; | |
9154 | } | |
5b63f465 | 9155 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9156 | break; |
d9aba805 | 9157 | |
fb251650 ILT |
9158 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9159 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9160 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9161 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9162 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9163 | { | |
9164 | as_bad ("-call_shared is supported only for ELF format"); | |
9165 | return 0; | |
9166 | } | |
d9aba805 ILT |
9167 | mips_pic = SVR4_PIC; |
9168 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
9169 | { |
9170 | as_bad ("-G may not be used with SVR4 PIC code"); | |
9171 | return 0; | |
9172 | } | |
d9aba805 | 9173 | g_switch_value = 0; |
f3d817d8 DM |
9174 | break; |
9175 | ||
9176 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9177 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9178 | { | |
9179 | as_bad ("-non_shared is supported only for ELF format"); | |
9180 | return 0; | |
9181 | } | |
d9aba805 | 9182 | mips_pic = NO_PIC; |
f3d817d8 | 9183 | break; |
8358c818 | 9184 | |
fb251650 ILT |
9185 | /* The -xgot option tells the assembler to use 32 offsets when |
9186 | accessing the got in SVR4_PIC mode. It is for Irix | |
9187 | compatibility. */ | |
9188 | case OPTION_XGOT: | |
9189 | mips_big_got = 1; | |
9190 | break; | |
9191 | ||
f3d817d8 | 9192 | case 'G': |
1dc1e798 KR |
9193 | if (! USE_GLOBAL_POINTER_OPT) |
9194 | { | |
9195 | as_bad ("-G is not supported for this configuration"); | |
9196 | return 0; | |
9197 | } | |
9198 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9199 | { |
f3d817d8 DM |
9200 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
9201 | return 0; | |
670a50eb ILT |
9202 | } |
9203 | else | |
f3d817d8 | 9204 | g_switch_value = atoi (arg); |
42562568 | 9205 | g_switch_seen = 1; |
f3d817d8 | 9206 | break; |
4e95866e | 9207 | |
7f9880e5 ILT |
9208 | /* The -32 and -64 options tell the assembler to output the 32 |
9209 | bit or the 64 bit MIPS ELF format. */ | |
9210 | case OPTION_32: | |
9211 | mips_64 = 0; | |
9212 | break; | |
9213 | ||
9214 | case OPTION_64: | |
9c44af60 ILT |
9215 | { |
9216 | const char **list, **l; | |
9217 | ||
9218 | list = bfd_target_list (); | |
9219 | for (l = list; *l != NULL; l++) | |
9220 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9221 | || strcmp (*l, "elf64-littlemips") == 0) | |
9222 | break; | |
9223 | if (*l == NULL) | |
9224 | as_fatal ("No compiled in support for 64 bit object file format"); | |
9225 | free (list); | |
9226 | mips_64 = 1; | |
9227 | } | |
7f9880e5 ILT |
9228 | break; |
9229 | ||
f3d817d8 DM |
9230 | default: |
9231 | return 0; | |
8ea7f4e8 ILT |
9232 | } |
9233 | ||
f3d817d8 | 9234 | return 1; |
8ea7f4e8 ILT |
9235 | } |
9236 | ||
f3d817d8 DM |
9237 | void |
9238 | md_show_usage (stream) | |
9239 | FILE *stream; | |
9240 | { | |
9241 | fprintf(stream, "\ | |
9242 | MIPS options:\n\ | |
9243 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9244 | -EB generate big endian output\n\ |
9245 | -EL generate little endian output\n\ | |
9246 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9247 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
9248 | implicitly with the gp register [default 8]\n"); |
9249 | fprintf(stream, "\ | |
f3d817d8 DM |
9250 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
9251 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
9252 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 9253 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 9254 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9255 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9256 | -m4650 permit R4650 instructions\n\ |
9257 | -no-m4650 do not permit R4650 instructions\n\ | |
9258 | -m4010 permit R4010 instructions\n\ | |
9259 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
9260 | -m4100 permit VR4100 instructions\n\ |
9261 | -no-m4100 do not permit VR4100 instructions\n"); | |
9262 | fprintf(stream, "\ | |
cc5703cd ILT |
9263 | -mips16 generate mips16 instructions\n\ |
9264 | -no-mips16 do not generate mips16 instructions\n"); | |
9265 | fprintf(stream, "\ | |
f3d817d8 DM |
9266 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9267 | -O remove unneeded NOPs and swap branches\n\ | |
9268 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
9269 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
9270 | #ifdef OBJ_ELF | |
9271 | fprintf(stream, "\ | |
9272 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 9273 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9274 | -xgot assume a 32 bit GOT\n\ |
9275 | -32 create 32 bit object file (default)\n\ | |
9276 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
9277 | #endif |
9278 | } | |
9279 | \f | |
efec4a28 DP |
9280 | void |
9281 | mips_init_after_args () | |
9282 | { | |
af942793 SS |
9283 | /* initialize opcodes */ |
9284 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9285 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9286 | } |
9287 | ||
3d3c5039 ILT |
9288 | long |
9289 | md_pcrel_from (fixP) | |
9290 | fixS *fixP; | |
9291 | { | |
1dc1e798 KR |
9292 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9293 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9294 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9295 | { | |
9296 | /* This makes a branch to an undefined symbol be a branch to the | |
9297 | current location. */ | |
9298 | return 4; | |
9299 | } | |
5b63f465 | 9300 | |
670a50eb ILT |
9301 | /* return the address of the delay slot */ |
9302 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9303 | } |
9304 | ||
abdad6bc ILT |
9305 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9306 | reloc for a cons. We could use the definition there, except that | |
9307 | we want to handle 64 bit relocs specially. */ | |
9308 | ||
9309 | void | |
9310 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9311 | fragS *frag; | |
9312 | int where; | |
9313 | unsigned int nbytes; | |
9314 | expressionS *exp; | |
9315 | { | |
bf39474f | 9316 | #ifndef OBJ_ELF |
abdad6bc | 9317 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9318 | 4 byte reloc. */ |
9319 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9320 | { |
b9129c6f | 9321 | if (target_big_endian) |
abdad6bc ILT |
9322 | where += 4; |
9323 | nbytes = 4; | |
9324 | } | |
bf39474f | 9325 | #endif |
abdad6bc | 9326 | |
7f9880e5 | 9327 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
9328 | as_bad ("Unsupported reloc size %d", nbytes); |
9329 | ||
9330 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9331 | (nbytes == 2 |
9332 | ? BFD_RELOC_16 | |
9333 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9334 | } |
9335 | ||
23604921 ILT |
9336 | /* This is called before the symbol table is processed. In order to |
9337 | work with gcc when using mips-tfile, we must keep all local labels. | |
9338 | However, in other cases, we want to discard them. If we were | |
9339 | called with -g, but we didn't see any debugging information, it may | |
9340 | mean that gcc is smuggling debugging information through to | |
9341 | mips-tfile, in which case we must generate all local labels. */ | |
9342 | ||
9343 | void | |
9344 | mips_frob_file_before_adjust () | |
9345 | { | |
9346 | #ifndef NO_ECOFF_DEBUGGING | |
9347 | if (ECOFF_DEBUGGING | |
9348 | && mips_debug != 0 | |
9349 | && ! ecoff_debugging_seen) | |
9350 | flag_keep_locals = 1; | |
9351 | #endif | |
9352 | } | |
9353 | ||
867a58b3 ILT |
9354 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9355 | the corresponding LO reloc. This is called before md_apply_fix and | |
9356 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9357 | explicit use of the %hi modifier. */ | |
9358 | ||
9359 | void | |
9360 | mips_frob_file () | |
9361 | { | |
9362 | struct mips_hi_fixup *l; | |
9363 | ||
9364 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9365 | { | |
9366 | segment_info_type *seginfo; | |
9b61d62b | 9367 | int pass; |
867a58b3 ILT |
9368 | |
9369 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9370 | ||
9371 | /* Check quickly whether the next fixup happens to be a matching | |
9372 | %lo. */ | |
9373 | if (l->fixp->fx_next != NULL | |
9374 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9375 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9376 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9377 | continue; | |
9378 | ||
9379 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9380 | When we find one, move the %hi just in front of it. We do |
9381 | this in two passes. In the first pass, we try to find a | |
9382 | unique %lo. In the second pass, we permit multiple %hi | |
9383 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9384 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9385 | for (pass = 0; pass < 2; pass++) |
9386 | { | |
9387 | fixS *f, *prev; | |
9388 | ||
9389 | prev = NULL; | |
9390 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9391 | { |
9b61d62b ILT |
9392 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9393 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9394 | && f->fx_addsy == l->fixp->fx_addsy | |
9395 | && f->fx_offset == l->fixp->fx_offset | |
9396 | && (pass == 1 | |
9397 | || prev == NULL | |
9398 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9399 | || prev->fx_addsy != f->fx_addsy | |
9400 | || prev->fx_offset != f->fx_offset)) | |
9401 | { | |
9402 | fixS **pf; | |
867a58b3 | 9403 | |
9b61d62b ILT |
9404 | /* Move l->fixp before f. */ |
9405 | for (pf = &seginfo->fix_root; | |
9406 | *pf != l->fixp; | |
9407 | pf = &(*pf)->fx_next) | |
9408 | assert (*pf != NULL); | |
867a58b3 | 9409 | |
9b61d62b | 9410 | *pf = l->fixp->fx_next; |
867a58b3 | 9411 | |
9b61d62b ILT |
9412 | l->fixp->fx_next = f; |
9413 | if (prev == NULL) | |
9414 | seginfo->fix_root = l->fixp; | |
9415 | else | |
9416 | prev->fx_next = l->fixp; | |
867a58b3 | 9417 | |
9b61d62b ILT |
9418 | break; |
9419 | } | |
9420 | ||
9421 | prev = f; | |
867a58b3 ILT |
9422 | } |
9423 | ||
9b61d62b ILT |
9424 | if (f != NULL) |
9425 | break; | |
867a58b3 | 9426 | |
9b61d62b ILT |
9427 | if (pass == 1) |
9428 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9429 | "Unmatched %%hi reloc"); | |
9430 | } | |
867a58b3 ILT |
9431 | } |
9432 | } | |
9433 | ||
1c803e52 ILT |
9434 | /* When generating embedded PIC code we need to use a special |
9435 | relocation to represent the difference of two symbols in the .text | |
9436 | section (switch tables use a difference of this sort). See | |
9437 | include/coff/mips.h for details. This macro checks whether this | |
9438 | fixup requires the special reloc. */ | |
9439 | #define SWITCH_TABLE(fixp) \ | |
9440 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9441 | && (fixp)->fx_addsy != NULL \ | |
9442 | && (fixp)->fx_subsy != NULL \ | |
9443 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9444 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9445 | ||
5b63f465 | 9446 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
9447 | relocations, in case the linker has to relax a call. We also need |
9448 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
9449 | |
9450 | /*ARGSUSED*/ | |
9451 | int | |
9452 | mips_force_relocation (fixp) | |
9453 | fixS *fixp; | |
9454 | { | |
1c803e52 | 9455 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
9456 | && (fixp->fx_pcrel |
9457 | || SWITCH_TABLE (fixp) | |
9458 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9459 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
9460 | } |
9461 | ||
9462 | /* Apply a fixup to the object file. */ | |
9463 | ||
3d3c5039 ILT |
9464 | int |
9465 | md_apply_fix (fixP, valueP) | |
9466 | fixS *fixP; | |
918692a5 | 9467 | valueT *valueP; |
3d3c5039 | 9468 | { |
670a50eb ILT |
9469 | unsigned char *buf; |
9470 | long insn, value; | |
3d3c5039 | 9471 | |
bf39474f ILT |
9472 | assert (fixP->fx_size == 4 |
9473 | || fixP->fx_r_type == BFD_RELOC_16 | |
9474 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 9475 | |
670a50eb | 9476 | value = *valueP; |
1748b9d8 ILT |
9477 | |
9478 | /* If we aren't adjusting this fixup to be against the section | |
9479 | symbol, we need to adjust the value. */ | |
68952421 | 9480 | #ifdef OBJ_ELF |
1748b9d8 | 9481 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
9482 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
9483 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
9484 | { | |
9485 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9486 | if (value != 0 && ! fixP->fx_pcrel) | |
9487 | { | |
9488 | /* In this case, the bfd_install_relocation routine will | |
9489 | incorrectly add the symbol value back in. We just want | |
9490 | the addend to appear in the object file. */ | |
9491 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9492 | } | |
9493 | } | |
9494 | #endif | |
9495 | ||
670a50eb | 9496 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 9497 | |
5b63f465 ILT |
9498 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
9499 | fixP->fx_done = 1; | |
9500 | ||
670a50eb ILT |
9501 | switch (fixP->fx_r_type) |
9502 | { | |
3d3c5039 ILT |
9503 | case BFD_RELOC_MIPS_JMP: |
9504 | case BFD_RELOC_HI16: | |
9505 | case BFD_RELOC_HI16_S: | |
670a50eb | 9506 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
9507 | case BFD_RELOC_MIPS_LITERAL: |
9508 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
9509 | case BFD_RELOC_MIPS_GOT16: |
9510 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
9511 | case BFD_RELOC_MIPS_GOT_HI16: |
9512 | case BFD_RELOC_MIPS_GOT_LO16: | |
9513 | case BFD_RELOC_MIPS_CALL_HI16: | |
9514 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 9515 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 9516 | if (fixP->fx_pcrel) |
7b777690 ILT |
9517 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9518 | "Invalid PC relative reloc"); | |
670a50eb | 9519 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 9520 | break; |
3d3c5039 | 9521 | |
cc5703cd ILT |
9522 | case BFD_RELOC_MIPS16_JMP: |
9523 | /* We currently always generate a reloc against a symbol, which | |
9524 | means that we don't want an addend even if the symbol is | |
9525 | defined. */ | |
9526 | fixP->fx_addnumber = 0; | |
9527 | break; | |
9528 | ||
ecd4ca1c ILT |
9529 | case BFD_RELOC_PCREL_HI16_S: |
9530 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9531 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9532 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9533 | { | |
9534 | /* For an external symbol adjust by the address to make it | |
9535 | pcrel_offset. We use the address of the RELLO reloc | |
9536 | which follows this one. */ | |
9537 | value += (fixP->fx_next->fx_frag->fr_address | |
9538 | + fixP->fx_next->fx_where); | |
9539 | } | |
9540 | if (value & 0x8000) | |
9541 | value += 0x10000; | |
9542 | value >>= 16; | |
0221ddf7 | 9543 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9544 | if (target_big_endian) |
ecd4ca1c ILT |
9545 | buf += 2; |
9546 | md_number_to_chars (buf, value, 2); | |
9547 | break; | |
9548 | ||
9549 | case BFD_RELOC_PCREL_LO16: | |
9550 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9551 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9552 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9553 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 9554 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9555 | if (target_big_endian) |
ecd4ca1c ILT |
9556 | buf += 2; |
9557 | md_number_to_chars (buf, value, 2); | |
9558 | break; | |
9559 | ||
bf39474f ILT |
9560 | case BFD_RELOC_64: |
9561 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9562 | extended value if we are only 32 bits. */ | |
9563 | if (fixP->fx_done | |
9564 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9565 | { | |
9566 | if (8 <= sizeof (valueT)) | |
9567 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9568 | value, 8); | |
9569 | else | |
9570 | { | |
9571 | long w1, w2; | |
9572 | long hiv; | |
9573 | ||
9574 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9575 | if (target_big_endian) |
bf39474f ILT |
9576 | w1 += 4; |
9577 | else | |
9578 | w2 += 4; | |
9579 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9580 | if ((value & 0x80000000) != 0) | |
9581 | hiv = 0xffffffff; | |
9582 | else | |
9583 | hiv = 0; | |
9584 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9585 | } | |
9586 | } | |
9587 | break; | |
9588 | ||
f3645945 ILT |
9589 | case BFD_RELOC_32: |
9590 | /* If we are deleting this reloc entry, we must fill in the | |
9591 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9592 | resolved when it appears but is later defined. We also need |
9593 | to fill in the value if this is an embedded PIC switch table | |
9594 | entry. */ | |
9595 | if (fixP->fx_done | |
9596 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9597 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9598 | value, 4); | |
9599 | break; | |
9600 | ||
49ad0c4c ILT |
9601 | case BFD_RELOC_16: |
9602 | /* If we are deleting this reloc entry, we must fill in the | |
9603 | value now. */ | |
9604 | assert (fixP->fx_size == 2); | |
9605 | if (fixP->fx_done) | |
9606 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9607 | value, 2); | |
9608 | break; | |
9609 | ||
f3645945 ILT |
9610 | case BFD_RELOC_LO16: |
9611 | /* When handling an embedded PIC switch statement, we can wind | |
9612 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9613 | if (fixP->fx_done) | |
9614 | { | |
9615 | if (value < -0x8000 || value > 0x7fff) | |
9616 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9617 | "relocation overflow"); | |
0221ddf7 | 9618 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9619 | if (target_big_endian) |
f3645945 ILT |
9620 | buf += 2; |
9621 | md_number_to_chars (buf, value, 2); | |
9622 | } | |
9623 | break; | |
9624 | ||
3d3c5039 | 9625 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
9626 | /* |
9627 | * We need to save the bits in the instruction since fixup_segment() | |
9628 | * might be deleting the relocation entry (i.e., a branch within | |
9629 | * the current segment). | |
9630 | */ | |
fbcfacb7 | 9631 | if ((value & 0x3) != 0) |
3b320c48 ILT |
9632 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9633 | "Branch to odd address (%lx)", value); | |
670a50eb | 9634 | value >>= 2; |
670a50eb ILT |
9635 | |
9636 | /* update old instruction data */ | |
9637 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
9638 | if (target_big_endian) |
9639 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9640 | else | |
9641 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
9642 | |
9643 | if (value >= -0x8000 && value < 0x8000) | |
9644 | insn |= value & 0xffff; | |
9645 | else | |
9646 | { | |
9647 | /* The branch offset is too large. If this is an | |
9648 | unconditional branch, and we are not generating PIC code, | |
9649 | we can convert it to an absolute jump instruction. */ | |
9650 | if (mips_pic == NO_PIC | |
9651 | && fixP->fx_done | |
9652 | && fixP->fx_frag->fr_address >= text_section->vma | |
9653 | && (fixP->fx_frag->fr_address | |
9654 | < text_section->vma + text_section->_raw_size) | |
9655 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9656 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9657 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9658 | { | |
9659 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9660 | insn = 0x0c000000; /* jal */ | |
9661 | else | |
9662 | insn = 0x08000000; /* j */ | |
9663 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9664 | fixP->fx_done = 0; | |
9665 | fixP->fx_addsy = section_symbol (text_section); | |
9666 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9667 | } | |
9668 | else | |
9669 | { | |
9670 | /* FIXME. It would be possible in principle to handle | |
9671 | conditional branches which overflow. They could be | |
9672 | transformed into a branch around a jump. This would | |
9673 | require setting up variant frags for each different | |
9674 | branch type. The native MIPS assembler attempts to | |
9675 | handle these cases, but it appears to do it | |
9676 | incorrectly. */ | |
9677 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 9678 | "Branch out of range"); |
9da4c5d1 ILT |
9679 | } |
9680 | } | |
9681 | ||
604633ae | 9682 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 9683 | break; |
3d3c5039 ILT |
9684 | |
9685 | default: | |
670a50eb | 9686 | internalError (); |
3d3c5039 | 9687 | } |
5b63f465 | 9688 | |
670a50eb | 9689 | return 1; |
3d3c5039 ILT |
9690 | } |
9691 | ||
9692 | #if 0 | |
9693 | void | |
670a50eb ILT |
9694 | printInsn (oc) |
9695 | unsigned long oc; | |
3d3c5039 | 9696 | { |
670a50eb ILT |
9697 | const struct mips_opcode *p; |
9698 | int treg, sreg, dreg, shamt; | |
9699 | short imm; | |
9700 | const char *args; | |
9701 | int i; | |
3d3c5039 | 9702 | |
670a50eb ILT |
9703 | for (i = 0; i < NUMOPCODES; ++i) |
9704 | { | |
9705 | p = &mips_opcodes[i]; | |
9706 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9707 | { | |
9708 | printf ("%08lx %s\t", oc, p->name); | |
9709 | treg = (oc >> 16) & 0x1f; | |
9710 | sreg = (oc >> 21) & 0x1f; | |
9711 | dreg = (oc >> 11) & 0x1f; | |
9712 | shamt = (oc >> 6) & 0x1f; | |
9713 | imm = oc; | |
9714 | for (args = p->args;; ++args) | |
9715 | { | |
9716 | switch (*args) | |
9717 | { | |
3d3c5039 | 9718 | case '\0': |
670a50eb ILT |
9719 | printf ("\n"); |
9720 | break; | |
3d3c5039 ILT |
9721 | |
9722 | case ',': | |
9723 | case '(': | |
9724 | case ')': | |
670a50eb ILT |
9725 | printf ("%c", *args); |
9726 | continue; | |
3d3c5039 ILT |
9727 | |
9728 | case 'r': | |
670a50eb ILT |
9729 | assert (treg == sreg); |
9730 | printf ("$%d,$%d", treg, sreg); | |
9731 | continue; | |
3d3c5039 ILT |
9732 | |
9733 | case 'd': | |
918692a5 | 9734 | case 'G': |
670a50eb ILT |
9735 | printf ("$%d", dreg); |
9736 | continue; | |
3d3c5039 ILT |
9737 | |
9738 | case 't': | |
918692a5 | 9739 | case 'E': |
670a50eb ILT |
9740 | printf ("$%d", treg); |
9741 | continue; | |
3d3c5039 | 9742 | |
9226253a ILT |
9743 | case 'k': |
9744 | printf ("0x%x", treg); | |
9745 | continue; | |
9746 | ||
3d3c5039 ILT |
9747 | case 'b': |
9748 | case 's': | |
670a50eb ILT |
9749 | printf ("$%d", sreg); |
9750 | continue; | |
3d3c5039 ILT |
9751 | |
9752 | case 'a': | |
670a50eb ILT |
9753 | printf ("0x%08lx", oc & 0x1ffffff); |
9754 | continue; | |
3d3c5039 ILT |
9755 | |
9756 | case 'i': | |
9757 | case 'j': | |
9758 | case 'o': | |
9759 | case 'u': | |
670a50eb ILT |
9760 | printf ("%d", imm); |
9761 | continue; | |
3d3c5039 ILT |
9762 | |
9763 | case '<': | |
56c96faa | 9764 | case '>': |
670a50eb ILT |
9765 | printf ("$%d", shamt); |
9766 | continue; | |
3d3c5039 ILT |
9767 | |
9768 | default: | |
670a50eb | 9769 | internalError (); |
3d3c5039 | 9770 | } |
670a50eb | 9771 | break; |
3d3c5039 | 9772 | } |
670a50eb | 9773 | return; |
3d3c5039 ILT |
9774 | } |
9775 | } | |
670a50eb | 9776 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
9777 | } |
9778 | #endif | |
9779 | ||
9780 | static symbolS * | |
9781 | get_symbol () | |
9782 | { | |
670a50eb ILT |
9783 | int c; |
9784 | char *name; | |
9785 | symbolS *p; | |
9786 | ||
9787 | name = input_line_pointer; | |
9788 | c = get_symbol_end (); | |
9789 | p = (symbolS *) symbol_find_or_make (name); | |
9790 | *input_line_pointer = c; | |
9791 | return p; | |
3d3c5039 ILT |
9792 | } |
9793 | ||
becfe05e ILT |
9794 | /* Align the current frag to a given power of two. The MIPS assembler |
9795 | also automatically adjusts any preceding label. */ | |
9796 | ||
9797 | static void | |
23dc1ae3 | 9798 | mips_align (to, fill, label) |
becfe05e ILT |
9799 | int to; |
9800 | int fill; | |
23dc1ae3 | 9801 | symbolS *label; |
becfe05e | 9802 | { |
fbcfacb7 | 9803 | mips_emit_delays (false); |
e2e5acfa | 9804 | frag_align (to, fill, 0); |
becfe05e | 9805 | record_alignment (now_seg, to); |
23dc1ae3 | 9806 | if (label != NULL) |
becfe05e | 9807 | { |
23dc1ae3 ILT |
9808 | assert (S_GET_SEGMENT (label) == now_seg); |
9809 | label->sy_frag = frag_now; | |
9810 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9811 | } |
9812 | } | |
9813 | ||
9814 | /* Align to a given power of two. .align 0 turns off the automatic | |
9815 | alignment used by the data creating pseudo-ops. */ | |
9816 | ||
3d3c5039 ILT |
9817 | static void |
9818 | s_align (x) | |
9819 | int x; | |
9820 | { | |
670a50eb ILT |
9821 | register int temp; |
9822 | register long temp_fill; | |
9823 | long max_alignment = 15; | |
3d3c5039 | 9824 | |
670a50eb | 9825 | /* |
3d3c5039 ILT |
9826 | |
9827 | o Note that the assembler pulls down any immediately preceeding label | |
9828 | to the aligned address. | |
9829 | o It's not documented but auto alignment is reinstated by | |
9830 | a .align pseudo instruction. | |
9831 | o Note also that after auto alignment is turned off the mips assembler | |
9832 | issues an error on attempt to assemble an improperly aligned data item. | |
9833 | We don't. | |
9834 | ||
9835 | */ | |
9836 | ||
670a50eb ILT |
9837 | temp = get_absolute_expression (); |
9838 | if (temp > max_alignment) | |
9839 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9840 | else if (temp < 0) | |
9841 | { | |
9842 | as_warn ("Alignment negative: 0 assumed."); | |
9843 | temp = 0; | |
9844 | } | |
9845 | if (*input_line_pointer == ',') | |
9846 | { | |
9847 | input_line_pointer++; | |
9848 | temp_fill = get_absolute_expression (); | |
9849 | } | |
9850 | else | |
9851 | temp_fill = 0; | |
9852 | if (temp) | |
9853 | { | |
9854 | auto_align = 1; | |
fbcfacb7 ILT |
9855 | mips_align (temp, (int) temp_fill, |
9856 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9857 | } |
670a50eb ILT |
9858 | else |
9859 | { | |
9860 | auto_align = 0; | |
3d3c5039 ILT |
9861 | } |
9862 | ||
670a50eb | 9863 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9864 | } |
9865 | ||
739708fa KR |
9866 | void |
9867 | mips_flush_pending_output () | |
becfe05e | 9868 | { |
fbcfacb7 ILT |
9869 | mips_emit_delays (false); |
9870 | mips_clear_insn_labels (); | |
becfe05e ILT |
9871 | } |
9872 | ||
3d3c5039 ILT |
9873 | static void |
9874 | s_change_sec (sec) | |
9875 | int sec; | |
9876 | { | |
88225433 | 9877 | segT seg; |
becfe05e | 9878 | |
5b63f465 ILT |
9879 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9880 | .sdata and .sbss sections. We change the .data and .rdata | |
9881 | pseudo-ops to use .sdata. */ | |
9882 | if (mips_pic == EMBEDDED_PIC | |
9883 | && (sec == 'd' || sec == 'r')) | |
9884 | sec = 's'; | |
9885 | ||
acdc7ce3 ILT |
9886 | #ifdef OBJ_ELF |
9887 | /* The ELF backend needs to know that we are changing sections, so | |
9888 | that .previous works correctly. We could do something like check | |
9889 | for a obj_section_change_hook macro, but that might be confusing | |
9890 | as it would not be appropriate to use it in the section changing | |
9891 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9892 | This should be cleaner, somehow. */ | |
9893 | obj_elf_section_change_hook (); | |
9894 | #endif | |
9895 | ||
fbcfacb7 | 9896 | mips_emit_delays (false); |
670a50eb ILT |
9897 | switch (sec) |
9898 | { | |
3d3c5039 | 9899 | case 't': |
604633ae | 9900 | s_text (0); |
670a50eb | 9901 | break; |
3d3c5039 | 9902 | case 'd': |
604633ae | 9903 | s_data (0); |
670a50eb | 9904 | break; |
3d3c5039 | 9905 | case 'b': |
670a50eb | 9906 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9907 | demand_empty_rest_of_line (); |
9908 | break; | |
88225433 ILT |
9909 | |
9910 | case 'r': | |
1dc1e798 KR |
9911 | if (USE_GLOBAL_POINTER_OPT) |
9912 | { | |
9913 | seg = subseg_new (RDATA_SECTION_NAME, | |
9914 | (subsegT) get_absolute_expression ()); | |
9915 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9916 | { | |
9917 | bfd_set_section_flags (stdoutput, seg, | |
9918 | (SEC_ALLOC | |
9919 | | SEC_LOAD | |
9920 | | SEC_READONLY | |
9921 | | SEC_RELOC | |
9922 | | SEC_DATA)); | |
08e17202 ILT |
9923 | if (strcmp (TARGET_OS, "elf") != 0) |
9924 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9925 | } |
9926 | demand_empty_rest_of_line (); | |
9927 | } | |
9928 | else | |
9929 | { | |
9930 | as_bad ("No read only data section in this object file format"); | |
9931 | demand_empty_rest_of_line (); | |
9932 | return; | |
9933 | } | |
88225433 | 9934 | break; |
88225433 ILT |
9935 | |
9936 | case 's': | |
1dc1e798 KR |
9937 | if (USE_GLOBAL_POINTER_OPT) |
9938 | { | |
9939 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9940 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9941 | { | |
9942 | bfd_set_section_flags (stdoutput, seg, | |
9943 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9944 | | SEC_DATA); | |
08e17202 ILT |
9945 | if (strcmp (TARGET_OS, "elf") != 0) |
9946 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9947 | } |
9948 | demand_empty_rest_of_line (); | |
9949 | break; | |
9950 | } | |
9951 | else | |
9952 | { | |
9953 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9954 | demand_empty_rest_of_line (); | |
9955 | return; | |
9956 | } | |
3d3c5039 | 9957 | } |
88225433 | 9958 | |
670a50eb | 9959 | auto_align = 1; |
3d3c5039 ILT |
9960 | } |
9961 | ||
739708fa KR |
9962 | void |
9963 | mips_enable_auto_align () | |
9da4c5d1 | 9964 | { |
9da4c5d1 ILT |
9965 | auto_align = 1; |
9966 | } | |
9967 | ||
3d3c5039 ILT |
9968 | static void |
9969 | s_cons (log_size) | |
9970 | int log_size; | |
9971 | { | |
23dc1ae3 ILT |
9972 | symbolS *label; |
9973 | ||
fbcfacb7 ILT |
9974 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9975 | mips_emit_delays (false); | |
670a50eb | 9976 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9977 | mips_align (log_size, 0, label); |
fbcfacb7 | 9978 | mips_clear_insn_labels (); |
670a50eb | 9979 | cons (1 << log_size); |
3d3c5039 ILT |
9980 | } |
9981 | ||
3d3c5039 | 9982 | static void |
becfe05e ILT |
9983 | s_float_cons (type) |
9984 | int type; | |
3d3c5039 | 9985 | { |
23dc1ae3 ILT |
9986 | symbolS *label; |
9987 | ||
fbcfacb7 | 9988 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9989 | |
fbcfacb7 | 9990 | mips_emit_delays (false); |
670a50eb ILT |
9991 | |
9992 | if (auto_align) | |
becfe05e | 9993 | if (type == 'd') |
23dc1ae3 | 9994 | mips_align (3, 0, label); |
670a50eb | 9995 | else |
23dc1ae3 | 9996 | mips_align (2, 0, label); |
670a50eb | 9997 | |
fbcfacb7 | 9998 | mips_clear_insn_labels (); |
1849d646 | 9999 | |
becfe05e | 10000 | float_cons (type); |
3d3c5039 ILT |
10001 | } |
10002 | ||
c1444ec4 ILT |
10003 | /* Handle .globl. We need to override it because on Irix 5 you are |
10004 | permitted to say | |
10005 | .globl foo .text | |
10006 | where foo is an undefined symbol, to mean that foo should be | |
10007 | considered to be the address of a function. */ | |
10008 | ||
10009 | static void | |
10010 | s_mips_globl (x) | |
10011 | int x; | |
10012 | { | |
10013 | char *name; | |
10014 | int c; | |
10015 | symbolS *symbolP; | |
fb251650 | 10016 | flagword flag; |
c1444ec4 ILT |
10017 | |
10018 | name = input_line_pointer; | |
10019 | c = get_symbol_end (); | |
10020 | symbolP = symbol_find_or_make (name); | |
10021 | *input_line_pointer = c; | |
10022 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10023 | |
10024 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10025 | being a function is apparently labelled as being an object. */ | |
10026 | flag = BSF_OBJECT; | |
10027 | ||
c1444ec4 ILT |
10028 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10029 | { | |
10030 | char *secname; | |
10031 | asection *sec; | |
10032 | ||
10033 | secname = input_line_pointer; | |
10034 | c = get_symbol_end (); | |
10035 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10036 | if (sec == NULL) | |
10037 | as_bad ("%s: no such section", secname); | |
10038 | *input_line_pointer = c; | |
10039 | ||
10040 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10041 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10042 | } |
10043 | ||
fb251650 ILT |
10044 | symbolP->bsym->flags |= flag; |
10045 | ||
c1444ec4 ILT |
10046 | S_SET_EXTERNAL (symbolP); |
10047 | demand_empty_rest_of_line (); | |
10048 | } | |
10049 | ||
3d3c5039 ILT |
10050 | static void |
10051 | s_option (x) | |
10052 | int x; | |
10053 | { | |
dd3f1f76 ILT |
10054 | char *opt; |
10055 | char c; | |
10056 | ||
10057 | opt = input_line_pointer; | |
10058 | c = get_symbol_end (); | |
10059 | ||
dd3f1f76 | 10060 | if (*opt == 'O') |
9226253a ILT |
10061 | { |
10062 | /* FIXME: What does this mean? */ | |
10063 | } | |
dd3f1f76 | 10064 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10065 | { |
d9aba805 | 10066 | int i; |
42562568 | 10067 | |
d9aba805 ILT |
10068 | i = atoi (opt + 3); |
10069 | if (i == 0) | |
10070 | mips_pic = NO_PIC; | |
10071 | else if (i == 2) | |
10072 | mips_pic = SVR4_PIC; | |
10073 | else | |
10074 | as_bad (".option pic%d not supported", i); | |
10075 | ||
1dc1e798 | 10076 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10077 | { |
10078 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 10079 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
10080 | g_switch_value = 0; |
10081 | bfd_set_gp_size (stdoutput, 0); | |
10082 | } | |
9226253a | 10083 | } |
dd3f1f76 ILT |
10084 | else |
10085 | as_warn ("Unrecognized option \"%s\"", opt); | |
10086 | ||
10087 | *input_line_pointer = c; | |
670a50eb | 10088 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10089 | } |
10090 | ||
3c83da8a JW |
10091 | /* This structure is used to hold a stack of .set values. */ |
10092 | ||
10093 | struct mips_option_stack | |
10094 | { | |
10095 | struct mips_option_stack *next; | |
10096 | struct mips_set_options options; | |
10097 | }; | |
10098 | ||
10099 | static struct mips_option_stack *mips_opts_stack; | |
10100 | ||
10101 | /* Handle the .set pseudo-op. */ | |
10102 | ||
3d3c5039 ILT |
10103 | static void |
10104 | s_mipsset (x) | |
10105 | int x; | |
10106 | { | |
670a50eb ILT |
10107 | char *name = input_line_pointer, ch; |
10108 | ||
10109 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10110 | input_line_pointer++; | |
10111 | ch = *input_line_pointer; | |
10112 | *input_line_pointer = '\0'; | |
10113 | ||
10114 | if (strcmp (name, "reorder") == 0) | |
10115 | { | |
3c83da8a | 10116 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10117 | { |
4a1cb507 ILT |
10118 | /* If we still have pending nops, we can discard them. The |
10119 | usual nop handling will insert any that are still | |
10120 | needed. */ | |
3c83da8a JW |
10121 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10122 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10123 | prev_nop_frag = NULL; |
4e95866e | 10124 | } |
3c83da8a | 10125 | mips_opts.noreorder = 0; |
670a50eb ILT |
10126 | } |
10127 | else if (strcmp (name, "noreorder") == 0) | |
10128 | { | |
fbcfacb7 | 10129 | mips_emit_delays (true); |
3c83da8a | 10130 | mips_opts.noreorder = 1; |
0dd2d296 | 10131 | mips_any_noreorder = 1; |
670a50eb ILT |
10132 | } |
10133 | else if (strcmp (name, "at") == 0) | |
10134 | { | |
3c83da8a | 10135 | mips_opts.noat = 0; |
670a50eb ILT |
10136 | } |
10137 | else if (strcmp (name, "noat") == 0) | |
10138 | { | |
3c83da8a | 10139 | mips_opts.noat = 1; |
3d3c5039 | 10140 | } |
670a50eb ILT |
10141 | else if (strcmp (name, "macro") == 0) |
10142 | { | |
3c83da8a | 10143 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10144 | } |
10145 | else if (strcmp (name, "nomacro") == 0) | |
10146 | { | |
3c83da8a | 10147 | if (mips_opts.noreorder == 0) |
670a50eb | 10148 | as_bad ("`noreorder' must be set before `nomacro'"); |
3c83da8a | 10149 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10150 | } |
10151 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10152 | { | |
3c83da8a | 10153 | mips_opts.nomove = 0; |
670a50eb ILT |
10154 | } |
10155 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10156 | { | |
3c83da8a | 10157 | mips_opts.nomove = 1; |
670a50eb ILT |
10158 | } |
10159 | else if (strcmp (name, "bopt") == 0) | |
10160 | { | |
3c83da8a | 10161 | mips_opts.nobopt = 0; |
670a50eb ILT |
10162 | } |
10163 | else if (strcmp (name, "nobopt") == 0) | |
10164 | { | |
3c83da8a | 10165 | mips_opts.nobopt = 1; |
670a50eb | 10166 | } |
943321c0 ILT |
10167 | else if (strcmp (name, "mips16") == 0 |
10168 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10169 | mips_opts.mips16 = 1; |
943321c0 ILT |
10170 | else if (strcmp (name, "nomips16") == 0 |
10171 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10172 | mips_opts.mips16 = 0; |
1051c97f ILT |
10173 | else if (strncmp (name, "mips", 4) == 0) |
10174 | { | |
10175 | int isa; | |
10176 | ||
10177 | /* Permit the user to change the ISA on the fly. Needless to | |
10178 | say, misuse can cause serious problems. */ | |
10179 | isa = atoi (name + 4); | |
10180 | if (isa == 0) | |
3c83da8a | 10181 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10182 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
10183 | as_bad ("unknown ISA level"); |
10184 | else | |
3c83da8a | 10185 | mips_opts.isa = isa; |
1051c97f | 10186 | } |
cc5703cd | 10187 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10188 | mips_opts.noautoextend = 0; |
cc5703cd | 10189 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10190 | mips_opts.noautoextend = 1; |
10191 | else if (strcmp (name, "push") == 0) | |
10192 | { | |
10193 | struct mips_option_stack *s; | |
10194 | ||
10195 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10196 | s->next = mips_opts_stack; | |
10197 | s->options = mips_opts; | |
10198 | mips_opts_stack = s; | |
10199 | } | |
10200 | else if (strcmp (name, "pop") == 0) | |
10201 | { | |
10202 | struct mips_option_stack *s; | |
10203 | ||
10204 | s = mips_opts_stack; | |
10205 | if (s == NULL) | |
10206 | as_bad (".set pop with no .set push"); | |
10207 | else | |
10208 | { | |
10209 | /* If we're changing the reorder mode we need to handle | |
10210 | delay slots correctly. */ | |
10211 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10212 | mips_emit_delays (true); | |
10213 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10214 | { | |
10215 | if (prev_nop_frag != NULL) | |
10216 | { | |
10217 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10218 | * (mips_opts.mips16 ? 2 : 4)); | |
10219 | prev_nop_frag = NULL; | |
10220 | } | |
10221 | } | |
10222 | ||
10223 | mips_opts = s->options; | |
10224 | mips_opts_stack = s->next; | |
10225 | free (s); | |
10226 | } | |
10227 | } | |
670a50eb ILT |
10228 | else |
10229 | { | |
10230 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
10231 | } | |
10232 | *input_line_pointer = ch; | |
10233 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10234 | } |
10235 | ||
9226253a ILT |
10236 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10237 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10238 | ||
10239 | static void | |
10240 | s_abicalls (ignore) | |
10241 | int ignore; | |
10242 | { | |
d9aba805 | 10243 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10244 | if (USE_GLOBAL_POINTER_OPT) |
10245 | { | |
10246 | if (g_switch_seen && g_switch_value != 0) | |
10247 | as_warn ("-G may not be used with SVR4 PIC code"); | |
10248 | g_switch_value = 0; | |
10249 | } | |
d9aba805 | 10250 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10251 | demand_empty_rest_of_line (); |
10252 | } | |
10253 | ||
10254 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10255 | PIC code. It sets the $gp register for the function based on the | |
10256 | function address, which is in the register named in the argument. | |
10257 | This uses a relocation against _gp_disp, which is handled specially | |
10258 | by the linker. The result is: | |
10259 | lui $gp,%hi(_gp_disp) | |
10260 | addiu $gp,$gp,%lo(_gp_disp) | |
10261 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10262 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10263 | |
10264 | static void | |
10265 | s_cpload (ignore) | |
10266 | int ignore; | |
10267 | { | |
10268 | expressionS ex; | |
10269 | int icnt = 0; | |
10270 | ||
d9aba805 ILT |
10271 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10272 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10273 | { |
10274 | s_ignore (0); | |
10275 | return; | |
10276 | } | |
10277 | ||
10278 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10279 | if (mips_opts.noreorder == 0) |
0dd2d296 ILT |
10280 | as_warn (".cpload not in noreorder section"); |
10281 | ||
9226253a ILT |
10282 | ex.X_op = O_symbol; |
10283 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10284 | ex.X_op_symbol = NULL; | |
10285 | ex.X_add_number = 0; | |
10286 | ||
fb251650 ILT |
10287 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10288 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10289 | ||
0dd2d296 ILT |
10290 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10291 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10292 | (int) BFD_RELOC_LO16); |
10293 | ||
0dd2d296 ILT |
10294 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10295 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10296 | |
10297 | demand_empty_rest_of_line (); | |
10298 | } | |
10299 | ||
10300 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10301 | offset from $sp. The offset is remembered, and after making a PIC | |
10302 | call $gp is restored from that location. */ | |
10303 | ||
10304 | static void | |
10305 | s_cprestore (ignore) | |
10306 | int ignore; | |
10307 | { | |
10308 | expressionS ex; | |
10309 | int icnt = 0; | |
10310 | ||
d9aba805 ILT |
10311 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10312 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10313 | { |
10314 | s_ignore (0); | |
10315 | return; | |
10316 | } | |
10317 | ||
9226253a ILT |
10318 | mips_cprestore_offset = get_absolute_expression (); |
10319 | ||
10320 | ex.X_op = O_constant; | |
10321 | ex.X_add_symbol = NULL; | |
10322 | ex.X_op_symbol = NULL; | |
10323 | ex.X_add_number = mips_cprestore_offset; | |
10324 | ||
0dd2d296 | 10325 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
10326 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10327 | || mips_opts.isa < 3) | |
10328 | ? "sw" : "sd"), | |
9226253a ILT |
10329 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10330 | ||
10331 | demand_empty_rest_of_line (); | |
10332 | } | |
10333 | ||
0dd2d296 ILT |
10334 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10335 | code. It generates a 32 bit GP relative reloc. */ | |
10336 | ||
10337 | static void | |
10338 | s_gpword (ignore) | |
10339 | int ignore; | |
10340 | { | |
23dc1ae3 | 10341 | symbolS *label; |
0dd2d296 ILT |
10342 | expressionS ex; |
10343 | char *p; | |
10344 | ||
10345 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10346 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10347 | { |
10348 | s_cons (2); | |
10349 | return; | |
10350 | } | |
10351 | ||
fbcfacb7 ILT |
10352 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10353 | mips_emit_delays (true); | |
0dd2d296 | 10354 | if (auto_align) |
23dc1ae3 | 10355 | mips_align (2, 0, label); |
fbcfacb7 | 10356 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10357 | |
10358 | expression (&ex); | |
10359 | ||
10360 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10361 | { | |
10362 | as_bad ("Unsupported use of .gpword"); | |
10363 | ignore_rest_of_line (); | |
10364 | } | |
10365 | ||
10366 | p = frag_more (4); | |
10367 | md_number_to_chars (p, (valueT) 0, 4); | |
10368 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10369 | BFD_RELOC_MIPS_GPREL32); | |
10370 | ||
10371 | demand_empty_rest_of_line (); | |
10372 | } | |
10373 | ||
10374 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10375 | tables in SVR4 PIC code. */ | |
10376 | ||
10377 | static void | |
10378 | s_cpadd (ignore) | |
10379 | int ignore; | |
10380 | { | |
10381 | int icnt = 0; | |
10382 | int reg; | |
10383 | ||
10384 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10385 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10386 | { |
10387 | s_ignore (0); | |
10388 | return; | |
10389 | } | |
10390 | ||
10391 | /* Add $gp to the register named as an argument. */ | |
10392 | reg = tc_get_register (0); | |
10393 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
10394 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10395 | || mips_opts.isa < 3) | |
10396 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
10397 | "d,v,t", reg, reg, GP); |
10398 | ||
10399 | demand_empty_rest_of_line (); | |
10400 | } | |
10401 | ||
ed3eb786 ILT |
10402 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10403 | mips16 mode. This permits the linker to handle them specially, | |
10404 | such as generating jalx instructions when needed. We also make | |
10405 | them odd for the duration of the assembly, in order to generate the | |
10406 | right sort of code. We will make them even in the adjust_symtab | |
10407 | routine, while leaving them marked. This is convenient for the | |
10408 | debugger and the disassembler. The linker knows to make them odd | |
10409 | again. */ | |
10410 | ||
10411 | static void | |
10412 | s_insn (ignore) | |
10413 | int ignore; | |
10414 | { | |
3c83da8a JW |
10415 | if (mips_opts.mips16) |
10416 | mips16_mark_labels (); | |
ed3eb786 | 10417 | |
3c83da8a JW |
10418 | demand_empty_rest_of_line (); |
10419 | } | |
ed3eb786 | 10420 | |
3c83da8a JW |
10421 | /* Handle a .stabn directive. We need these in order to mark a label |
10422 | as being a mips16 text label correctly. Sometimes the compiler | |
10423 | will emit a label, followed by a .stabn, and then switch sections. | |
10424 | If the label and .stabn are in mips16 mode, then the label is | |
10425 | really a mips16 text label. */ | |
ed3eb786 | 10426 | |
3c83da8a JW |
10427 | static void |
10428 | s_mips_stab (type) | |
10429 | int type; | |
10430 | { | |
10431 | if (type == 'n' && mips_opts.mips16) | |
10432 | mips16_mark_labels (); | |
10433 | ||
10434 | s_stab (type); | |
ed3eb786 ILT |
10435 | } |
10436 | ||
9226253a | 10437 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
10438 | to parse .frame. The argument is non-zero if this is the frame |
10439 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 10440 | |
3d3c5039 | 10441 | int |
0dd2d296 ILT |
10442 | tc_get_register (frame) |
10443 | int frame; | |
3d3c5039 ILT |
10444 | { |
10445 | int reg; | |
10446 | ||
10447 | SKIP_WHITESPACE (); | |
10448 | if (*input_line_pointer++ != '$') | |
10449 | { | |
10450 | as_warn ("expected `$'"); | |
0dd2d296 | 10451 | reg = 0; |
3d3c5039 | 10452 | } |
0dd2d296 | 10453 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
10454 | { |
10455 | reg = get_absolute_expression (); | |
10456 | if (reg < 0 || reg >= 32) | |
10457 | { | |
10458 | as_warn ("Bad register number"); | |
10459 | reg = 0; | |
10460 | } | |
10461 | } | |
10462 | else | |
10463 | { | |
10464 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 10465 | reg = FP; |
3d3c5039 | 10466 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 10467 | reg = SP; |
3d3c5039 | 10468 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 10469 | reg = GP; |
3d3c5039 | 10470 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 10471 | reg = AT; |
3d3c5039 ILT |
10472 | else |
10473 | { | |
10474 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 10475 | reg = 0; |
3d3c5039 ILT |
10476 | } |
10477 | input_line_pointer += 2; | |
10478 | } | |
0dd2d296 ILT |
10479 | if (frame) |
10480 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
10481 | return reg; |
10482 | } | |
10483 | ||
0dd2d296 ILT |
10484 | valueT |
10485 | md_section_align (seg, addr) | |
10486 | asection *seg; | |
10487 | valueT addr; | |
10488 | { | |
10489 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10490 | ||
cf32394d ILT |
10491 | #ifdef OBJ_ELF |
10492 | /* We don't need to align ELF sections to the full alignment. | |
10493 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
10494 | byte boundary. We don't bother to align the sections if we are |
10495 | targeted for an embedded system. */ | |
10496 | if (strcmp (TARGET_OS, "elf") == 0) | |
10497 | return addr; | |
943321c0 ILT |
10498 | if (align > 4) |
10499 | align = 4; | |
10a14e36 | 10500 | #endif |
cf32394d ILT |
10501 | |
10502 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
10503 | } |
10504 | ||
d8a1c247 KR |
10505 | /* Utility routine, called from above as well. If called while the |
10506 | input file is still being read, it's only an approximation. (For | |
10507 | example, a symbol may later become defined which appeared to be | |
10508 | undefined earlier.) */ | |
22ba90ce ILT |
10509 | |
10510 | static int | |
85ce5635 | 10511 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 10512 | symbolS *sym; |
85ce5635 | 10513 | int before_relaxing; |
d8a1c247 KR |
10514 | { |
10515 | if (sym == 0) | |
10516 | return 0; | |
10517 | ||
1dc1e798 KR |
10518 | if (USE_GLOBAL_POINTER_OPT) |
10519 | { | |
10520 | const char *symname; | |
10521 | int change; | |
10522 | ||
10523 | /* Find out whether this symbol can be referenced off the GP | |
10524 | register. It can be if it is smaller than the -G size or if | |
10525 | it is in the .sdata or .sbss section. Certain symbols can | |
10526 | not be referenced off the GP, although it appears as though | |
10527 | they can. */ | |
10528 | symname = S_GET_NAME (sym); | |
10529 | if (symname != (const char *) NULL | |
10530 | && (strcmp (symname, "eprol") == 0 | |
10531 | || strcmp (symname, "etext") == 0 | |
10532 | || strcmp (symname, "_gp") == 0 | |
10533 | || strcmp (symname, "edata") == 0 | |
10534 | || strcmp (symname, "_fbss") == 0 | |
10535 | || strcmp (symname, "_fdata") == 0 | |
10536 | || strcmp (symname, "_ftext") == 0 | |
10537 | || strcmp (symname, "end") == 0 | |
10538 | || strcmp (symname, "_gp_disp") == 0)) | |
10539 | change = 1; | |
23ac3ca1 | 10540 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
10541 | && (0 |
10542 | #ifndef NO_ECOFF_DEBUGGING | |
10543 | || (sym->ecoff_extern_size != 0 | |
10544 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 10545 | #endif |
85ce5635 ILT |
10546 | /* We must defer this decision until after the whole |
10547 | file has been read, since there might be a .extern | |
10548 | after the first use of this symbol. */ | |
a5586bdc ILT |
10549 | || (before_relaxing |
10550 | #ifndef NO_ECOFF_DEBUGGING | |
10551 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 10552 | #endif |
a5586bdc | 10553 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
10554 | || (S_GET_VALUE (sym) != 0 |
10555 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10556 | change = 0; | |
10557 | else | |
10558 | { | |
10559 | const char *segname; | |
d8a1c247 | 10560 | |
1dc1e798 KR |
10561 | segname = segment_name (S_GET_SEGMENT (sym)); |
10562 | assert (strcmp (segname, ".lit8") != 0 | |
10563 | && strcmp (segname, ".lit4") != 0); | |
10564 | change = (strcmp (segname, ".sdata") != 0 | |
10565 | && strcmp (segname, ".sbss") != 0); | |
10566 | } | |
10567 | return change; | |
10568 | } | |
10569 | else | |
10570 | /* We are not optimizing for the GP register. */ | |
10571 | return 1; | |
d8a1c247 KR |
10572 | } |
10573 | ||
cc5703cd ILT |
10574 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
10575 | extended opcode. SEC is the section the frag is in. */ | |
10576 | ||
10577 | static int | |
10578 | mips16_extended_frag (fragp, sec, stretch) | |
10579 | fragS *fragp; | |
10580 | asection *sec; | |
10581 | long stretch; | |
10582 | { | |
10583 | int type; | |
10584 | register const struct mips16_immed_operand *op; | |
10585 | offsetT val; | |
10586 | int mintiny, maxtiny; | |
f74ba7a3 | 10587 | segT symsec; |
cc5703cd | 10588 | |
8728fa92 ILT |
10589 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
10590 | return 0; | |
10591 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10592 | return 1; | |
10593 | ||
cc5703cd ILT |
10594 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
10595 | op = mips16_immed_operands; | |
10596 | while (op->type != type) | |
10597 | { | |
10598 | ++op; | |
10599 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10600 | } | |
10601 | ||
10602 | if (op->unsp) | |
10603 | { | |
10604 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10605 | { | |
10606 | mintiny = 1; | |
10607 | maxtiny = 1 << op->nbits; | |
10608 | } | |
10609 | else | |
10610 | { | |
10611 | mintiny = 0; | |
10612 | maxtiny = (1 << op->nbits) - 1; | |
10613 | } | |
10614 | } | |
10615 | else | |
10616 | { | |
10617 | mintiny = - (1 << (op->nbits - 1)); | |
10618 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10619 | } | |
10620 | ||
f74ba7a3 ILT |
10621 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
10622 | a particular frag address. */ | |
10623 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
10624 | { | |
10625 | val = (fragp->fr_symbol->sy_value.X_add_number | |
10626 | + fragp->fr_symbol->sy_frag->fr_address); | |
10627 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
10628 | } | |
10629 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
10630 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
10631 | == O_constant)) | |
10632 | { | |
10633 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
10634 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
10635 | + fragp->fr_symbol->sy_value.X_add_number | |
10636 | + fragp->fr_symbol->sy_frag->fr_address); | |
10637 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
10638 | } | |
10639 | else | |
10640 | return 1; | |
cc5703cd ILT |
10641 | |
10642 | if (op->pcrel) | |
10643 | { | |
10644 | addressT addr; | |
10645 | ||
10646 | /* We won't have the section when we are called from | |
10647 | mips_relax_frag. However, we will always have been called | |
10648 | from md_estimate_size_before_relax first. If this is a | |
10649 | branch to a different section, we mark it as such. If SEC is | |
10650 | NULL, and the frag is not marked, then it must be a branch to | |
10651 | the same section. */ | |
10652 | if (sec == NULL) | |
10653 | { | |
10654 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10655 | return 1; | |
10656 | } | |
10657 | else | |
10658 | { | |
f74ba7a3 | 10659 | if (symsec != sec) |
cc5703cd ILT |
10660 | { |
10661 | fragp->fr_subtype = | |
10662 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10663 | ||
10664 | /* FIXME: We should support this, and let the linker | |
10665 | catch branches and loads that are out of range. */ | |
10666 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10667 | "unsupported PC relative reference to different section"); | |
10668 | ||
10669 | return 1; | |
10670 | } | |
10671 | } | |
10672 | ||
10673 | /* In this case, we know for sure that the symbol fragment is in | |
10674 | the same section. If the fr_address of the symbol fragment | |
10675 | is greater then the address of this fragment we want to add | |
10676 | in STRETCH in order to get a better estimate of the address. | |
10677 | This particularly matters because of the shift bits. */ | |
10678 | if (stretch != 0 | |
10679 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
10680 | { | |
10681 | fragS *f; | |
10682 | ||
a941619c ILT |
10683 | /* Adjust stretch for any alignment frag. Note that if have |
10684 | been expanding the earlier code, the symbol may be | |
10685 | defined in what appears to be an earlier frag. FIXME: | |
10686 | This doesn't handle the fr_subtype field, which specifies | |
10687 | a maximum number of bytes to skip when doing an | |
10688 | alignment. */ | |
10689 | for (f = fragp; | |
10690 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
10691 | f = f->fr_next) | |
cc5703cd | 10692 | { |
cc5703cd ILT |
10693 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
10694 | { | |
10695 | if (stretch < 0) | |
10696 | stretch = - ((- stretch) | |
10697 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10698 | else | |
10699 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10700 | if (stretch == 0) | |
10701 | break; | |
10702 | } | |
10703 | } | |
a941619c ILT |
10704 | if (f != NULL) |
10705 | val += stretch; | |
cc5703cd ILT |
10706 | } |
10707 | ||
a677feeb ILT |
10708 | addr = fragp->fr_address + fragp->fr_fix; |
10709 | ||
10710 | /* The base address rules are complicated. The base address of | |
10711 | a branch is the following instruction. The base address of a | |
10712 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
10713 | is in a delay slot (in which case it can not be extended) use |
10714 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 10715 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
10716 | { |
10717 | addr += 2; | |
319305a7 ILT |
10718 | |
10719 | /* If we are currently assuming that this frag should be | |
10720 | extended, then, the current address is two bytes | |
10721 | higher. */ | |
10722 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10723 | addr += 2; | |
10724 | ||
fbcfacb7 ILT |
10725 | /* Ignore the low bit in the target, since it will be set |
10726 | for a text label. */ | |
10727 | if ((val & 1) != 0) | |
10728 | --val; | |
10729 | } | |
a677feeb ILT |
10730 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10731 | addr -= 4; | |
10732 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10733 | addr -= 2; | |
cc5703cd | 10734 | |
cc5703cd ILT |
10735 | val -= addr & ~ ((1 << op->shift) - 1); |
10736 | ||
10737 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10738 | if (type == 'p' || type == 'q') | |
10739 | val /= 2; | |
10740 | ||
10741 | /* If any of the shifted bits are set, we must use an extended | |
10742 | opcode. If the address depends on the size of this | |
10743 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
10744 | use an extended opcode. We only check this when we are in |
10745 | the main relaxation loop, when SEC is NULL. */ | |
10746 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10747 | { | |
10748 | fragp->fr_subtype = | |
10749 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10750 | return 1; | |
10751 | } | |
10752 | ||
10753 | /* If we are about to mark a frag as extended because the value | |
10754 | is precisely maxtiny + 1, then there is a chance of an | |
10755 | infinite loop as in the following code: | |
10756 | la $4,foo | |
10757 | .skip 1020 | |
10758 | .align 2 | |
10759 | foo: | |
10760 | In this case when the la is extended, foo is 0x3fc bytes | |
10761 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10762 | the la must be extended. To avoid this loop, we mark the | |
10763 | frag as extended if it was small, and is about to become | |
10764 | extended with a value of maxtiny + 1. */ | |
10765 | if (val == ((maxtiny + 1) << op->shift) | |
10766 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10767 | && sec == NULL) | |
cc5703cd ILT |
10768 | { |
10769 | fragp->fr_subtype = | |
10770 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10771 | return 1; | |
10772 | } | |
10773 | } | |
41a0ed22 ILT |
10774 | else if (symsec != absolute_section && sec != NULL) |
10775 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
10776 | |
10777 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10778 | || val < (mintiny << op->shift) | |
10779 | || val > (maxtiny << op->shift)) | |
10780 | return 1; | |
10781 | else | |
10782 | return 0; | |
10783 | } | |
10784 | ||
10785 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10786 | mips16, we are not really relaxing here, and the final size is | |
10787 | encoded in the subtype information. For the mips16, we have to | |
10788 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 10789 | |
0dd2d296 ILT |
10790 | /*ARGSUSED*/ |
10791 | int | |
10792 | md_estimate_size_before_relax (fragp, segtype) | |
10793 | fragS *fragp; | |
10794 | asection *segtype; | |
10795 | { | |
10796 | int change; | |
10797 | ||
cc5703cd ILT |
10798 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10799 | { | |
10800 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10801 | { | |
10802 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10803 | return 4; | |
10804 | } | |
10805 | else | |
10806 | { | |
10807 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10808 | return 2; | |
10809 | } | |
10810 | } | |
10811 | ||
d9aba805 | 10812 | if (mips_pic == NO_PIC) |
0dd2d296 | 10813 | { |
85ce5635 | 10814 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 10815 | } |
d9aba805 | 10816 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10817 | { |
46a92fde ILT |
10818 | symbolS *sym; |
10819 | asection *symsec; | |
10820 | ||
10821 | sym = fragp->fr_symbol; | |
10822 | ||
10823 | /* Handle the case of a symbol equated to another symbol. */ | |
10824 | while (sym->sy_value.X_op == O_symbol | |
10825 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
10826 | { | |
10827 | symbolS *n; | |
10828 | ||
10829 | /* It's possible to get a loop here in a badly written | |
10830 | program. */ | |
10831 | n = sym->sy_value.X_add_symbol; | |
10832 | if (n == sym) | |
10833 | break; | |
10834 | sym = n; | |
10835 | } | |
10836 | ||
10837 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
10838 | |
10839 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10840 | change = (symsec != &bfd_und_section | |
10841 | && symsec != &bfd_abs_section | |
10842 | && ! bfd_is_com_section (symsec)); | |
10843 | } | |
d9aba805 ILT |
10844 | else |
10845 | abort (); | |
0dd2d296 ILT |
10846 | |
10847 | if (change) | |
10848 | { | |
10849 | /* Record the offset to the first reloc in the fr_opcode field. | |
10850 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10851 | must be expanded. */ | |
10852 | fragp->fr_opcode = (fragp->fr_literal | |
10853 | + fragp->fr_fix | |
10854 | - RELAX_OLD (fragp->fr_subtype) | |
10855 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10856 | /* FIXME: This really needs as_warn_where. */ | |
10857 | if (RELAX_WARN (fragp->fr_subtype)) | |
10858 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
10859 | } | |
10860 | ||
10861 | if (! change) | |
10862 | return 0; | |
10863 | else | |
10864 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10865 | } | |
10866 | ||
0d7f9025 ILT |
10867 | /* This is called to see whether a reloc against a defined symbol |
10868 | should be converted into a reloc against a section. Don't adjust | |
10869 | MIPS16 jump relocations, so we don't have to worry about the format | |
10870 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10871 | mips16 symbols, so that the linker can find them if it needs to set |
10872 | up a stub. */ | |
0d7f9025 ILT |
10873 | |
10874 | int | |
10875 | mips_fix_adjustable (fixp) | |
10876 | fixS *fixp; | |
10877 | { | |
10878 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10879 | return 0; | |
10880 | if (fixp->fx_addsy == NULL) | |
10881 | return 1; | |
68952421 | 10882 | #ifdef OBJ_ELF |
0d7f9025 | 10883 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
10884 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10885 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10886 | return 0; |
10887 | #endif | |
10888 | return 1; | |
10889 | } | |
10890 | ||
0dd2d296 ILT |
10891 | /* Translate internal representation of relocation info to BFD target |
10892 | format. */ | |
10893 | ||
10894 | arelent ** | |
3d3c5039 ILT |
10895 | tc_gen_reloc (section, fixp) |
10896 | asection *section; | |
10897 | fixS *fixp; | |
10898 | { | |
0dd2d296 | 10899 | static arelent *retval[4]; |
3d3c5039 | 10900 | arelent *reloc; |
a8aed9dd | 10901 | bfd_reloc_code_real_type code; |
3d3c5039 | 10902 | |
0dd2d296 ILT |
10903 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10904 | retval[1] = NULL; | |
3d3c5039 ILT |
10905 | |
10906 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10907 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10908 | |
10909 | if (mips_pic == EMBEDDED_PIC | |
10910 | && SWITCH_TABLE (fixp)) | |
10911 | { | |
10912 | /* For a switch table entry we use a special reloc. The addend | |
10913 | is actually the difference between the reloc address and the | |
10914 | subtrahend. */ | |
10915 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10916 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10917 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10918 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10919 | } | |
ecd4ca1c ILT |
10920 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10921 | { | |
10922 | /* We use a special addend for an internal RELLO reloc. */ | |
10923 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10924 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10925 | else | |
10926 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10927 | } | |
10928 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10929 | { | |
10930 | assert (fixp->fx_next != NULL | |
10931 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10932 | /* We use a special addend for an internal RELHI reloc. The | |
10933 | reloc is relative to the RELLO; adjust the addend | |
10934 | accordingly. */ | |
10935 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10936 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10937 | + fixp->fx_next->fx_where | |
10938 | - S_GET_VALUE (fixp->fx_subsy)); | |
10939 | else | |
10940 | reloc->addend = (fixp->fx_addnumber | |
10941 | + fixp->fx_next->fx_frag->fr_address | |
10942 | + fixp->fx_next->fx_where); | |
10943 | } | |
1c803e52 | 10944 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10945 | reloc->addend = fixp->fx_addnumber; |
10946 | else | |
5b63f465 | 10947 | { |
1dc1e798 KR |
10948 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10949 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10950 | handling. */ | |
10951 | reloc->addend = reloc->address; | |
10952 | else | |
10953 | reloc->addend = -reloc->address; | |
5b63f465 | 10954 | } |
0dd2d296 ILT |
10955 | |
10956 | /* If this is a variant frag, we may need to adjust the existing | |
10957 | reloc and generate a new one. */ | |
10958 | if (fixp->fx_frag->fr_opcode != NULL | |
10959 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10960 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10961 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10962 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10963 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10964 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10965 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10966 | { |
10967 | arelent *reloc2; | |
10968 | ||
cc5703cd ILT |
10969 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10970 | ||
0dd2d296 | 10971 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10972 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10973 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10974 | the second one handle all of them. */ | |
0dd2d296 ILT |
10975 | if (fixp->fx_next != NULL |
10976 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10977 | { | |
fb251650 ILT |
10978 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10979 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10980 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10981 | && (fixp->fx_next->fx_r_type | |
10982 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10983 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10984 | && (fixp->fx_next->fx_r_type | |
10985 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10986 | retval[0] = NULL; |
10987 | return retval; | |
10988 | } | |
10989 | ||
10990 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10991 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10992 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10993 | retval[2] = NULL; | |
10994 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10995 | reloc2->address = (reloc->address | |
10996 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10997 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10998 | reloc2->addend = fixp->fx_addnumber; | |
10999 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11000 | assert (reloc2->howto != NULL); | |
11001 | ||
11002 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11003 | { | |
11004 | arelent *reloc3; | |
11005 | ||
11006 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11007 | retval[3] = NULL; | |
11008 | *reloc3 = *reloc2; | |
11009 | reloc3->address += 4; | |
11010 | } | |
11011 | ||
d9aba805 | 11012 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11013 | { |
11014 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11015 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11016 | } | |
d9aba805 | 11017 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11018 | { |
fb251650 | 11019 | switch (fixp->fx_r_type) |
0dd2d296 | 11020 | { |
fb251650 ILT |
11021 | default: |
11022 | abort (); | |
11023 | case BFD_RELOC_MIPS_GOT16: | |
11024 | break; | |
11025 | case BFD_RELOC_MIPS_CALL16: | |
11026 | case BFD_RELOC_MIPS_GOT_LO16: | |
11027 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11028 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11029 | break; |
0dd2d296 ILT |
11030 | } |
11031 | } | |
d9aba805 ILT |
11032 | else |
11033 | abort (); | |
0dd2d296 ILT |
11034 | } |
11035 | ||
a8aed9dd ILT |
11036 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11037 | fixup_segment converted a non-PC relative reloc into a PC | |
11038 | relative reloc. In such a case, we need to convert the reloc | |
11039 | code. */ | |
11040 | code = fixp->fx_r_type; | |
11041 | if (fixp->fx_pcrel) | |
11042 | { | |
11043 | switch (code) | |
11044 | { | |
11045 | case BFD_RELOC_8: | |
11046 | code = BFD_RELOC_8_PCREL; | |
11047 | break; | |
11048 | case BFD_RELOC_16: | |
11049 | code = BFD_RELOC_16_PCREL; | |
11050 | break; | |
11051 | case BFD_RELOC_32: | |
11052 | code = BFD_RELOC_32_PCREL; | |
11053 | break; | |
bf39474f ILT |
11054 | case BFD_RELOC_64: |
11055 | code = BFD_RELOC_64_PCREL; | |
11056 | break; | |
a8aed9dd ILT |
11057 | case BFD_RELOC_8_PCREL: |
11058 | case BFD_RELOC_16_PCREL: | |
11059 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11060 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11061 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11062 | case BFD_RELOC_PCREL_HI16_S: |
11063 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11064 | break; |
11065 | default: | |
11066 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11067 | "Cannot make %s relocation PC relative", | |
11068 | bfd_get_reloc_code_name (code)); | |
11069 | } | |
11070 | } | |
11071 | ||
d9aba805 ILT |
11072 | /* To support a PC relative reloc when generating embedded PIC code |
11073 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11074 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11075 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11076 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11077 | && mips_pic != EMBEDDED_PIC) |
11078 | reloc->howto = NULL; | |
11079 | else | |
a8aed9dd | 11080 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11081 | |
52aa70b5 JW |
11082 | if (reloc->howto == NULL) |
11083 | { | |
11084 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
11085 | "Can not represent %s relocation in this object file format", |
11086 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 11087 | retval[0] = NULL; |
52aa70b5 | 11088 | } |
3d3c5039 | 11089 | |
0dd2d296 | 11090 | return retval; |
3d3c5039 ILT |
11091 | } |
11092 | ||
cc5703cd ILT |
11093 | /* Relax a machine dependent frag. This returns the amount by which |
11094 | the current size of the frag should change. */ | |
11095 | ||
11096 | int | |
11097 | mips_relax_frag (fragp, stretch) | |
11098 | fragS *fragp; | |
11099 | long stretch; | |
11100 | { | |
11101 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11102 | return 0; | |
11103 | ||
11104 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11105 | { | |
11106 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11107 | return 0; | |
11108 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11109 | return 2; | |
11110 | } | |
11111 | else | |
11112 | { | |
11113 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11114 | return 0; | |
11115 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11116 | return -2; | |
11117 | } | |
11118 | ||
11119 | return 0; | |
11120 | } | |
11121 | ||
0dd2d296 ILT |
11122 | /* Convert a machine dependent frag. */ |
11123 | ||
11124 | void | |
11125 | md_convert_frag (abfd, asec, fragp) | |
11126 | bfd *abfd; | |
11127 | segT asec; | |
11128 | fragS *fragp; | |
3d3c5039 | 11129 | { |
0dd2d296 ILT |
11130 | int old, new; |
11131 | char *fixptr; | |
3d3c5039 | 11132 | |
cc5703cd ILT |
11133 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11134 | { | |
11135 | int type; | |
11136 | register const struct mips16_immed_operand *op; | |
11137 | boolean small, ext; | |
11138 | offsetT val; | |
11139 | bfd_byte *buf; | |
11140 | unsigned long insn; | |
11141 | boolean use_extend; | |
11142 | unsigned short extend; | |
11143 | ||
11144 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11145 | op = mips16_immed_operands; | |
11146 | while (op->type != type) | |
11147 | ++op; | |
11148 | ||
11149 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11150 | { | |
11151 | small = false; | |
11152 | ext = true; | |
11153 | } | |
11154 | else | |
11155 | { | |
11156 | small = true; | |
11157 | ext = false; | |
11158 | } | |
11159 | ||
b637f306 | 11160 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11161 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11162 | if (op->pcrel) |
11163 | { | |
11164 | addressT addr; | |
11165 | ||
a677feeb ILT |
11166 | addr = fragp->fr_address + fragp->fr_fix; |
11167 | ||
11168 | /* The rules for the base address of a PC relative reloc are | |
11169 | complicated; see mips16_extended_frag. */ | |
11170 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11171 | { |
11172 | addr += 2; | |
319305a7 ILT |
11173 | if (ext) |
11174 | addr += 2; | |
fbcfacb7 ILT |
11175 | /* Ignore the low bit in the target, since it will be |
11176 | set for a text label. */ | |
11177 | if ((val & 1) != 0) | |
11178 | --val; | |
11179 | } | |
a677feeb ILT |
11180 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11181 | addr -= 4; | |
11182 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11183 | addr -= 2; | |
11184 | ||
cc5703cd ILT |
11185 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11186 | val -= addr; | |
a677feeb ILT |
11187 | |
11188 | /* Make sure the section winds up with the alignment we have | |
11189 | assumed. */ | |
11190 | if (op->shift > 0) | |
11191 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11192 | } |
11193 | ||
035936da ILT |
11194 | if (ext |
11195 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11196 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11197 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11198 | "extended instruction in delay slot"); | |
11199 | ||
cc5703cd ILT |
11200 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
11201 | ||
b9129c6f ILT |
11202 | if (target_big_endian) |
11203 | insn = bfd_getb16 (buf); | |
11204 | else | |
11205 | insn = bfd_getl16 (buf); | |
cc5703cd | 11206 | |
31a2c6ff ILT |
11207 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
11208 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11209 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
11210 | |
11211 | if (use_extend) | |
11212 | { | |
11213 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11214 | fragp->fr_fix += 2; | |
11215 | buf += 2; | |
11216 | } | |
3d3c5039 | 11217 | |
cc5703cd ILT |
11218 | md_number_to_chars (buf, insn, 2); |
11219 | fragp->fr_fix += 2; | |
11220 | buf += 2; | |
11221 | } | |
11222 | else | |
11223 | { | |
11224 | if (fragp->fr_opcode == NULL) | |
11225 | return; | |
0dd2d296 | 11226 | |
cc5703cd ILT |
11227 | old = RELAX_OLD (fragp->fr_subtype); |
11228 | new = RELAX_NEW (fragp->fr_subtype); | |
11229 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 11230 | |
cc5703cd ILT |
11231 | if (new > 0) |
11232 | memcpy (fixptr - old, fixptr, new); | |
11233 | ||
11234 | fragp->fr_fix += new - old; | |
11235 | } | |
0dd2d296 | 11236 | } |
becfe05e | 11237 | |
fbcfacb7 ILT |
11238 | #ifdef OBJ_ELF |
11239 | ||
11240 | /* This function is called after the relocs have been generated. | |
11241 | We've been storing mips16 text labels as odd. Here we convert them | |
11242 | back to even for the convenience of the debugger. */ | |
11243 | ||
11244 | void | |
11245 | mips_frob_file_after_relocs () | |
11246 | { | |
11247 | asymbol **syms; | |
11248 | unsigned int count, i; | |
11249 | ||
11250 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11251 | return; | |
11252 | ||
11253 | syms = bfd_get_outsymbols (stdoutput); | |
11254 | count = bfd_get_symcount (stdoutput); | |
11255 | for (i = 0; i < count; i++, syms++) | |
11256 | { | |
11257 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11258 | && ((*syms)->value & 1) != 0) | |
11259 | { | |
11260 | (*syms)->value &= ~1; | |
11261 | /* If the symbol has an odd size, it was probably computed | |
11262 | incorrectly, so adjust that as well. */ | |
11263 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11264 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11265 | } | |
11266 | } | |
11267 | } | |
11268 | ||
11269 | #endif | |
11270 | ||
becfe05e ILT |
11271 | /* This function is called whenever a label is defined. It is used |
11272 | when handling branch delays; if a branch has a label, we assume we | |
11273 | can not move it. */ | |
11274 | ||
11275 | void | |
11276 | mips_define_label (sym) | |
11277 | symbolS *sym; | |
11278 | { | |
fbcfacb7 ILT |
11279 | struct insn_label_list *l; |
11280 | ||
11281 | if (free_insn_labels == NULL) | |
11282 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11283 | else | |
11284 | { | |
11285 | l = free_insn_labels; | |
11286 | free_insn_labels = l->next; | |
11287 | } | |
11288 | ||
11289 | l->label = sym; | |
11290 | l->next = insn_labels; | |
11291 | insn_labels = l; | |
becfe05e | 11292 | } |
3d3c5039 | 11293 | \f |
739708fa | 11294 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11295 | |
0dd2d296 | 11296 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11297 | |
11298 | void | |
11299 | mips_elf_final_processing () | |
11300 | { | |
87178180 ILT |
11301 | /* Write out the register information. */ |
11302 | if (! mips_64) | |
11303 | { | |
11304 | Elf32_RegInfo s; | |
11305 | ||
11306 | s.ri_gprmask = mips_gprmask; | |
11307 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11308 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11309 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11310 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11311 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11312 | ||
11313 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11314 | ((Elf32_External_RegInfo *) | |
11315 | mips_regmask_frag)); | |
11316 | } | |
11317 | else | |
11318 | { | |
11319 | Elf64_Internal_RegInfo s; | |
11320 | ||
11321 | s.ri_gprmask = mips_gprmask; | |
11322 | s.ri_pad = 0; | |
11323 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11324 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11325 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11326 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11327 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11328 | ||
11329 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11330 | ((Elf64_External_RegInfo *) | |
11331 | mips_regmask_frag)); | |
11332 | } | |
0dd2d296 ILT |
11333 | |
11334 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11335 | sort of BFD interface for this. */ | |
11336 | if (mips_any_noreorder) | |
11337 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11338 | if (mips_pic != NO_PIC) |
0dd2d296 | 11339 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11340 | } |
11341 | ||
739708fa | 11342 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11343 | \f |
3d3c5039 ILT |
11344 | /* These functions should really be defined by the object file format, |
11345 | since they are related to debugging information. However, this | |
11346 | code has to work for the a.out format, which does not define them, | |
11347 | so we provide simple versions here. These don't actually generate | |
11348 | any debugging information, but they do simple checking and someday | |
11349 | somebody may make them useful. */ | |
11350 | ||
670a50eb ILT |
11351 | typedef struct loc |
11352 | { | |
11353 | struct loc *loc_next; | |
11354 | unsigned long loc_fileno; | |
11355 | unsigned long loc_lineno; | |
11356 | unsigned long loc_offset; | |
11357 | unsigned short loc_delta; | |
11358 | unsigned short loc_count; | |
3d3c5039 | 11359 | #if 0 |
670a50eb | 11360 | fragS *loc_frag; |
3d3c5039 | 11361 | #endif |
670a50eb ILT |
11362 | } |
11363 | locS; | |
3d3c5039 | 11364 | |
670a50eb ILT |
11365 | typedef struct proc |
11366 | { | |
3d3c5039 ILT |
11367 | struct proc *proc_next; |
11368 | struct symbol *proc_isym; | |
11369 | struct symbol *proc_end; | |
11370 | unsigned long proc_reg_mask; | |
11371 | unsigned long proc_reg_offset; | |
11372 | unsigned long proc_fpreg_mask; | |
11373 | unsigned long proc_fpreg_offset; | |
11374 | unsigned long proc_frameoffset; | |
11375 | unsigned long proc_framereg; | |
11376 | unsigned long proc_pcreg; | |
11377 | locS *proc_iline; | |
11378 | struct file *proc_file; | |
11379 | int proc_index; | |
670a50eb ILT |
11380 | } |
11381 | procS; | |
3d3c5039 | 11382 | |
670a50eb ILT |
11383 | typedef struct file |
11384 | { | |
3d3c5039 ILT |
11385 | struct file *file_next; |
11386 | unsigned long file_fileno; | |
11387 | struct symbol *file_symbol; | |
11388 | struct symbol *file_end; | |
11389 | struct proc *file_proc; | |
11390 | int file_numprocs; | |
670a50eb ILT |
11391 | } |
11392 | fileS; | |
3d3c5039 ILT |
11393 | |
11394 | static struct obstack proc_frags; | |
11395 | static procS *proc_lastP; | |
11396 | static procS *proc_rootP; | |
11397 | static int numprocs; | |
11398 | ||
11399 | static void | |
11400 | md_obj_begin () | |
11401 | { | |
670a50eb | 11402 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
11403 | } |
11404 | ||
11405 | static void | |
11406 | md_obj_end () | |
11407 | { | |
11408 | /* check for premature end, nesting errors, etc */ | |
11409 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 11410 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
11411 | } |
11412 | ||
3d3c5039 ILT |
11413 | static long |
11414 | get_number () | |
11415 | { | |
670a50eb ILT |
11416 | int negative = 0; |
11417 | long val = 0; | |
3d3c5039 | 11418 | |
670a50eb ILT |
11419 | if (*input_line_pointer == '-') |
11420 | { | |
11421 | ++input_line_pointer; | |
11422 | negative = 1; | |
3d3c5039 | 11423 | } |
670a50eb ILT |
11424 | if (!isdigit (*input_line_pointer)) |
11425 | as_bad ("Expected simple number."); | |
11426 | if (input_line_pointer[0] == '0') | |
11427 | { | |
11428 | if (input_line_pointer[1] == 'x') | |
11429 | { | |
11430 | input_line_pointer += 2; | |
11431 | while (isxdigit (*input_line_pointer)) | |
11432 | { | |
11433 | val <<= 4; | |
3a762a0b | 11434 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 11435 | } |
670a50eb ILT |
11436 | return negative ? -val : val; |
11437 | } | |
11438 | else | |
11439 | { | |
11440 | ++input_line_pointer; | |
11441 | while (isdigit (*input_line_pointer)) | |
11442 | { | |
11443 | val <<= 3; | |
11444 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 11445 | } |
670a50eb | 11446 | return negative ? -val : val; |
3d3c5039 ILT |
11447 | } |
11448 | } | |
670a50eb ILT |
11449 | if (!isdigit (*input_line_pointer)) |
11450 | { | |
11451 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
11452 | *input_line_pointer, *input_line_pointer); | |
11453 | as_warn ("Invalid number"); | |
11454 | return -1; | |
3d3c5039 | 11455 | } |
670a50eb ILT |
11456 | while (isdigit (*input_line_pointer)) |
11457 | { | |
11458 | val *= 10; | |
11459 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 11460 | } |
670a50eb | 11461 | return negative ? -val : val; |
3d3c5039 ILT |
11462 | } |
11463 | ||
11464 | /* The .file directive; just like the usual .file directive, but there | |
11465 | is an initial number which is the ECOFF file index. */ | |
11466 | ||
11467 | static void | |
11468 | s_file (x) | |
11469 | int x; | |
11470 | { | |
670a50eb | 11471 | int line; |
3d3c5039 | 11472 | |
670a50eb | 11473 | line = get_number (); |
9a7d824a | 11474 | s_app_file (0); |
3d3c5039 ILT |
11475 | } |
11476 | ||
11477 | ||
11478 | /* The .end directive. */ | |
11479 | ||
11480 | static void | |
11481 | s_mipsend (x) | |
11482 | int x; | |
11483 | { | |
670a50eb ILT |
11484 | symbolS *p; |
11485 | ||
11486 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11487 | { | |
11488 | p = get_symbol (); | |
11489 | demand_empty_rest_of_line (); | |
11490 | } | |
11491 | else | |
11492 | p = NULL; | |
11493 | if (now_seg != text_section) | |
11494 | as_warn (".end not in text section"); | |
11495 | if (!proc_lastP) | |
11496 | { | |
11497 | as_warn (".end and no .ent seen yet."); | |
11498 | return; | |
3d3c5039 ILT |
11499 | } |
11500 | ||
670a50eb ILT |
11501 | if (p != NULL) |
11502 | { | |
11503 | assert (S_GET_NAME (p)); | |
11504 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
11505 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
11506 | } |
11507 | ||
670a50eb | 11508 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
11509 | } |
11510 | ||
11511 | /* The .aent and .ent directives. */ | |
11512 | ||
11513 | static void | |
11514 | s_ent (aent) | |
11515 | int aent; | |
11516 | { | |
670a50eb ILT |
11517 | int number = 0; |
11518 | procS *procP; | |
11519 | symbolS *symbolP; | |
11520 | ||
11521 | symbolP = get_symbol (); | |
11522 | if (*input_line_pointer == ',') | |
11523 | input_line_pointer++; | |
dd3f1f76 | 11524 | SKIP_WHITESPACE (); |
670a50eb ILT |
11525 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
11526 | number = get_number (); | |
11527 | if (now_seg != text_section) | |
11528 | as_warn (".ent or .aent not in text section."); | |
11529 | ||
11530 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
11531 | as_warn ("missing `.end'"); | |
11532 | ||
11533 | if (!aent) | |
11534 | { | |
11535 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
11536 | procP->proc_isym = symbolP; | |
11537 | procP->proc_reg_mask = 0; | |
11538 | procP->proc_reg_offset = 0; | |
11539 | procP->proc_fpreg_mask = 0; | |
11540 | procP->proc_fpreg_offset = 0; | |
11541 | procP->proc_frameoffset = 0; | |
11542 | procP->proc_framereg = 0; | |
11543 | procP->proc_pcreg = 0; | |
11544 | procP->proc_end = NULL; | |
11545 | procP->proc_next = NULL; | |
11546 | if (proc_lastP) | |
11547 | proc_lastP->proc_next = procP; | |
11548 | else | |
11549 | proc_rootP = procP; | |
11550 | proc_lastP = procP; | |
11551 | numprocs++; | |
3d3c5039 | 11552 | } |
670a50eb | 11553 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
11554 | } |
11555 | ||
11556 | /* The .frame directive. */ | |
11557 | ||
88225433 | 11558 | #if 0 |
3d3c5039 ILT |
11559 | static void |
11560 | s_frame (x) | |
670a50eb | 11561 | int x; |
3d3c5039 | 11562 | { |
670a50eb ILT |
11563 | char str[100]; |
11564 | symbolS *symP; | |
11565 | int frame_reg; | |
11566 | int frame_off; | |
11567 | int pcreg; | |
11568 | ||
0dd2d296 | 11569 | frame_reg = tc_get_register (1); |
670a50eb ILT |
11570 | if (*input_line_pointer == ',') |
11571 | input_line_pointer++; | |
5ac34ac3 | 11572 | frame_off = get_absolute_expression (); |
670a50eb ILT |
11573 | if (*input_line_pointer == ',') |
11574 | input_line_pointer++; | |
0dd2d296 | 11575 | pcreg = tc_get_register (0); |
670a50eb ILT |
11576 | |
11577 | /* bob third eye */ | |
11578 | assert (proc_rootP); | |
11579 | proc_rootP->proc_framereg = frame_reg; | |
11580 | proc_rootP->proc_frameoffset = frame_off; | |
11581 | proc_rootP->proc_pcreg = pcreg; | |
11582 | /* bob macho .frame */ | |
11583 | ||
11584 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 11585 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
11586 | { |
11587 | if (!proc_lastP) | |
11588 | as_warn ("No .ent for .frame to use."); | |
11589 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
11590 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
11591 | S_SET_TYPE (symP, N_RMASK); | |
11592 | S_SET_OTHER (symP, 0); | |
11593 | S_SET_DESC (symP, 0); | |
11594 | symP->sy_forward = proc_lastP->proc_isym; | |
11595 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11596 | } |
670a50eb | 11597 | demand_empty_rest_of_line (); |
3d3c5039 | 11598 | } |
88225433 | 11599 | #endif |
3d3c5039 ILT |
11600 | |
11601 | /* The .fmask and .mask directives. */ | |
11602 | ||
88225433 | 11603 | #if 0 |
3d3c5039 ILT |
11604 | static void |
11605 | s_mask (reg_type) | |
11606 | char reg_type; | |
11607 | { | |
670a50eb ILT |
11608 | char str[100], *strP; |
11609 | symbolS *symP; | |
11610 | int i; | |
11611 | unsigned int mask; | |
11612 | int off; | |
11613 | ||
11614 | mask = get_number (); | |
11615 | if (*input_line_pointer == ',') | |
11616 | input_line_pointer++; | |
11617 | off = get_absolute_expression (); | |
11618 | ||
11619 | /* bob only for coff */ | |
11620 | assert (proc_rootP); | |
11621 | if (reg_type == 'F') | |
11622 | { | |
11623 | proc_rootP->proc_fpreg_mask = mask; | |
11624 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 11625 | } |
670a50eb ILT |
11626 | else |
11627 | { | |
11628 | proc_rootP->proc_reg_mask = mask; | |
11629 | proc_rootP->proc_reg_offset = off; | |
11630 | } | |
11631 | ||
11632 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 11633 | |
670a50eb ILT |
11634 | /* We don't have to write out a mask stab if no saved regs. */ |
11635 | if (!(mask == 0)) | |
11636 | { | |
11637 | if (!proc_lastP) | |
11638 | as_warn ("No .ent for .mask to use."); | |
11639 | strP = str; | |
11640 | for (i = 0; i < 32; i++) | |
11641 | { | |
11642 | if (mask % 2) | |
11643 | { | |
11644 | sprintf (strP, "%c%d,", reg_type, i); | |
11645 | strP += strlen (strP); | |
11646 | } | |
3d3c5039 | 11647 | mask /= 2; |
670a50eb ILT |
11648 | } |
11649 | sprintf (strP, ";%d,", off); | |
11650 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
11651 | S_SET_TYPE (symP, N_RMASK); | |
11652 | S_SET_OTHER (symP, 0); | |
11653 | S_SET_DESC (symP, 0); | |
11654 | symP->sy_forward = proc_lastP->proc_isym; | |
11655 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11656 | } |
3d3c5039 | 11657 | } |
88225433 | 11658 | #endif |
3d3c5039 ILT |
11659 | |
11660 | /* The .loc directive. */ | |
11661 | ||
88225433 | 11662 | #if 0 |
3d3c5039 ILT |
11663 | static void |
11664 | s_loc (x) | |
11665 | int x; | |
11666 | { | |
670a50eb ILT |
11667 | symbolS *symbolP; |
11668 | int lineno; | |
11669 | int addroff; | |
3d3c5039 | 11670 | |
670a50eb | 11671 | assert (now_seg == text_section); |
3d3c5039 | 11672 | |
670a50eb | 11673 | lineno = get_number (); |
87e48495 | 11674 | addroff = frag_now_fix (); |
3d3c5039 | 11675 | |
670a50eb ILT |
11676 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
11677 | S_SET_TYPE (symbolP, N_SLINE); | |
11678 | S_SET_OTHER (symbolP, 0); | |
11679 | S_SET_DESC (symbolP, lineno); | |
11680 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 11681 | } |
88225433 | 11682 | #endif |