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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
e407c74b NC |
174 | |
175 | /* True if this instruction is cleared from history by unconditional | |
176 | branch. */ | |
177 | unsigned int cleared_p : 1; | |
47e39b9d RS |
178 | }; |
179 | ||
a325df1d TS |
180 | /* The ABI to use. */ |
181 | enum mips_abi_level | |
182 | { | |
183 | NO_ABI = 0, | |
184 | O32_ABI, | |
185 | O64_ABI, | |
186 | N32_ABI, | |
187 | N64_ABI, | |
188 | EABI_ABI | |
189 | }; | |
190 | ||
191 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 192 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 193 | |
143d77c5 EC |
194 | /* Whether or not we have code that can call pic code. */ |
195 | int mips_abicalls = FALSE; | |
196 | ||
aa6975fb ILT |
197 | /* Whether or not we have code which can be put into a shared |
198 | library. */ | |
199 | static bfd_boolean mips_in_shared = TRUE; | |
200 | ||
252b5132 RH |
201 | /* This is the set of options which may be modified by the .set |
202 | pseudo-op. We use a struct so that .set push and .set pop are more | |
203 | reliable. */ | |
204 | ||
e972090a NC |
205 | struct mips_set_options |
206 | { | |
252b5132 RH |
207 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
208 | if it has not been initialized. Changed by `.set mipsN', and the | |
209 | -mipsN command line option, and the default CPU. */ | |
210 | int isa; | |
846ef2d0 RS |
211 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
212 | <asename>', by command line options, and based on the default | |
213 | architecture. */ | |
214 | int ase; | |
252b5132 RH |
215 | /* Whether we are assembling for the mips16 processor. 0 if we are |
216 | not, 1 if we are, and -1 if the value has not been initialized. | |
217 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
218 | -nomips16 command line options, and the default CPU. */ | |
219 | int mips16; | |
df58fc94 RS |
220 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
221 | 1 if we are, and -1 if the value has not been initialized. Changed | |
222 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
223 | and -mno-micromips command line options, and the default CPU. */ | |
224 | int micromips; | |
252b5132 RH |
225 | /* Non-zero if we should not reorder instructions. Changed by `.set |
226 | reorder' and `.set noreorder'. */ | |
227 | int noreorder; | |
741fe287 MR |
228 | /* Non-zero if we should not permit the register designated "assembler |
229 | temporary" to be used in instructions. The value is the register | |
230 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
231 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
232 | unsigned int at; | |
252b5132 RH |
233 | /* Non-zero if we should warn when a macro instruction expands into |
234 | more than one machine instruction. Changed by `.set nomacro' and | |
235 | `.set macro'. */ | |
236 | int warn_about_macros; | |
237 | /* Non-zero if we should not move instructions. Changed by `.set | |
238 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
239 | int nomove; | |
240 | /* Non-zero if we should not optimize branches by moving the target | |
241 | of the branch into the delay slot. Actually, we don't perform | |
242 | this optimization anyhow. Changed by `.set bopt' and `.set | |
243 | nobopt'. */ | |
244 | int nobopt; | |
245 | /* Non-zero if we should not autoextend mips16 instructions. | |
246 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
247 | int noautoextend; | |
a325df1d TS |
248 | /* Restrict general purpose registers and floating point registers |
249 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
250 | is passed but can changed if the assembler code uses .set mipsN. */ | |
251 | int gp32; | |
252 | int fp32; | |
fef14a42 TS |
253 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
254 | command line option, and the default CPU. */ | |
255 | int arch; | |
aed1a261 RS |
256 | /* True if ".set sym32" is in effect. */ |
257 | bfd_boolean sym32; | |
037b32b9 AN |
258 | /* True if floating-point operations are not allowed. Changed by .set |
259 | softfloat or .set hardfloat, by command line options -msoft-float or | |
260 | -mhard-float. The default is false. */ | |
261 | bfd_boolean soft_float; | |
262 | ||
263 | /* True if only single-precision floating-point operations are allowed. | |
264 | Changed by .set singlefloat or .set doublefloat, command-line options | |
265 | -msingle-float or -mdouble-float. The default is false. */ | |
266 | bfd_boolean single_float; | |
252b5132 RH |
267 | }; |
268 | ||
037b32b9 AN |
269 | /* This is the struct we use to hold the current set of options. Note |
270 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
271 | -1 to indicate that they have not been initialized. */ | |
272 | ||
a325df1d | 273 | /* True if -mgp32 was passed. */ |
a8e8e863 | 274 | static int file_mips_gp32 = -1; |
a325df1d TS |
275 | |
276 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 277 | static int file_mips_fp32 = -1; |
a325df1d | 278 | |
037b32b9 AN |
279 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
280 | static int file_mips_soft_float = 0; | |
281 | ||
282 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
283 | static int file_mips_single_float = 0; | |
252b5132 | 284 | |
e972090a NC |
285 | static struct mips_set_options mips_opts = |
286 | { | |
846ef2d0 | 287 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 AP |
288 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
289 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0, | |
290 | /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
291 | /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 292 | }; |
252b5132 | 293 | |
846ef2d0 RS |
294 | /* The set of ASEs that were selected on the command line, either |
295 | explicitly via ASE options or implicitly through things like -march. */ | |
296 | static unsigned int file_ase; | |
297 | ||
298 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
299 | static unsigned int file_ase_explicit; | |
300 | ||
252b5132 RH |
301 | /* These variables are filled in with the masks of registers used. |
302 | The object format code reads them and puts them in the appropriate | |
303 | place. */ | |
304 | unsigned long mips_gprmask; | |
305 | unsigned long mips_cprmask[4]; | |
306 | ||
307 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 308 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 309 | |
738f4d98 | 310 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
311 | static int file_ase_mips16; |
312 | ||
3994f87e TS |
313 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2 \ | |
315 | || mips_opts.isa == ISA_MIPS64 \ | |
316 | || mips_opts.isa == ISA_MIPS64R2) | |
317 | ||
df58fc94 RS |
318 | /* True if any microMIPS code was produced. */ |
319 | static int file_ase_micromips; | |
320 | ||
b12dd2e4 CF |
321 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
322 | #ifdef TE_IRIX | |
1180b5a4 | 323 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 324 | #else |
1180b5a4 RS |
325 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
326 | because there's no place for any addend, the only acceptable | |
327 | expression is a bare symbol. */ | |
328 | #define MIPS_JALR_HINT_P(EXPR) \ | |
329 | (!HAVE_IN_PLACE_ADDENDS \ | |
330 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
331 | #endif |
332 | ||
ad3fea08 TS |
333 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
334 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 335 | |
ad3fea08 | 336 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
337 | || mips_opts.isa == ISA_MIPS64R2 \ |
338 | || mips_opts.micromips) | |
ad3fea08 | 339 | |
65263ce3 TS |
340 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
341 | ||
8b082fb1 | 342 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
343 | || mips_opts.isa == ISA_MIPS64R2 \ |
344 | || mips_opts.micromips) | |
8b082fb1 | 345 | |
7f3c4072 CM |
346 | #define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
347 | || mips_opts.isa == ISA_MIPS64R2 \ | |
348 | || mips_opts.micromips) | |
349 | ||
ad3fea08 TS |
350 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
351 | || mips_opts.isa == ISA_MIPS64R2) | |
352 | ||
dec0624d | 353 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
354 | || mips_opts.isa == ISA_MIPS64R2 \ |
355 | || mips_opts.micromips) | |
dec0624d | 356 | |
b015e599 | 357 | #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
f122319e CF |
358 | || mips_opts.isa == ISA_MIPS64R2 \ |
359 | || mips_opts.micromips) | |
b015e599 | 360 | |
f122319e CF |
361 | #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \ |
362 | || (mips_opts.micromips \ | |
363 | && ISA_HAS_64BIT_REGS (mips_opts.isa))) | |
b015e599 | 364 | |
ec68c924 | 365 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 366 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 367 | static const char *mips_arch_string; |
ec68c924 EC |
368 | |
369 | /* The argument of the -mtune= flag. The architecture for which we | |
370 | are optimizing. */ | |
371 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 372 | static const char *mips_tune_string; |
ec68c924 | 373 | |
316f5878 | 374 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
375 | static int mips_32bitmode = 0; |
376 | ||
316f5878 RS |
377 | /* True if the given ABI requires 32-bit registers. */ |
378 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
379 | ||
380 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
381 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
382 | ((ABI) == N32_ABI \ | |
383 | || (ABI) == N64_ABI \ | |
316f5878 RS |
384 | || (ABI) == O64_ABI) |
385 | ||
ad3fea08 | 386 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
387 | #define ISA_HAS_64BIT_REGS(ISA) \ |
388 | ((ISA) == ISA_MIPS3 \ | |
389 | || (ISA) == ISA_MIPS4 \ | |
390 | || (ISA) == ISA_MIPS5 \ | |
391 | || (ISA) == ISA_MIPS64 \ | |
392 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 393 | |
ad3fea08 TS |
394 | /* Return true if ISA supports 64 bit wide float registers. */ |
395 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
396 | ((ISA) == ISA_MIPS3 \ | |
397 | || (ISA) == ISA_MIPS4 \ | |
398 | || (ISA) == ISA_MIPS5 \ | |
399 | || (ISA) == ISA_MIPS32R2 \ | |
400 | || (ISA) == ISA_MIPS64 \ | |
401 | || (ISA) == ISA_MIPS64R2) | |
402 | ||
af7ee8bf CD |
403 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
404 | instructions. */ | |
707bfff6 | 405 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
406 | ((ISA) == ISA_MIPS64R2 \ |
407 | || (mips_opts.micromips \ | |
408 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
409 | ) | |
af7ee8bf CD |
410 | |
411 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
412 | instructions. */ | |
707bfff6 TS |
413 | #define ISA_HAS_ROR(ISA) \ |
414 | ((ISA) == ISA_MIPS32R2 \ | |
415 | || (ISA) == ISA_MIPS64R2 \ | |
846ef2d0 | 416 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
417 | || mips_opts.micromips \ |
418 | ) | |
707bfff6 | 419 | |
7455baf8 TS |
420 | /* Return true if ISA supports single-precision floats in odd registers. */ |
421 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
422 | ((ISA) == ISA_MIPS32 \ | |
423 | || (ISA) == ISA_MIPS32R2 \ | |
424 | || (ISA) == ISA_MIPS64 \ | |
425 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
431 | || (ISA) == ISA_MIPS64R2) | |
432 | ||
e013f690 | 433 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 434 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 435 | |
e013f690 | 436 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 437 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 438 | |
ad3fea08 TS |
439 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
440 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 441 | |
316f5878 | 442 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 443 | |
316f5878 | 444 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 445 | |
3b91255e RS |
446 | /* True if relocations are stored in-place. */ |
447 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
448 | ||
aed1a261 RS |
449 | /* The ABI-derived address size. */ |
450 | #define HAVE_64BIT_ADDRESSES \ | |
451 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
452 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 453 | |
aed1a261 RS |
454 | /* The size of symbolic constants (i.e., expressions of the form |
455 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
456 | #define HAVE_32BIT_SYMBOLS \ | |
457 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
458 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 459 | |
b7c7d6c1 TS |
460 | /* Addresses are loaded in different ways, depending on the address size |
461 | in use. The n32 ABI Documentation also mandates the use of additions | |
462 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 463 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 464 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
465 | |
466 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 467 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
468 | |
469 | #define ADDRESS_LOAD_INSN \ | |
470 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
471 | ||
472 | #define ADDRESS_STORE_INSN \ | |
473 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
474 | ||
a4672219 | 475 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
476 | #define CPU_HAS_MIPS16(cpu) \ |
477 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
478 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 479 | |
2309ddf2 | 480 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
481 | #define CPU_HAS_MICROMIPS(cpu) 0 |
482 | ||
60b63b72 RS |
483 | /* True if CPU has a dror instruction. */ |
484 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
485 | ||
486 | /* True if CPU has a ror instruction. */ | |
487 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
488 | ||
dd6a37e7 | 489 | /* True if CPU is in the Octeon family */ |
432233b3 | 490 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 491 | |
dd3cbb7e | 492 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 493 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 494 | |
0aa27725 RS |
495 | /* True, if CPU has support for ldc1 and sdc1. */ |
496 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
497 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
498 | ||
c8978940 CD |
499 | /* True if mflo and mfhi can be immediately followed by instructions |
500 | which write to the HI and LO registers. | |
501 | ||
502 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
503 | (at least) two instructions between the reads of HI/LO and | |
504 | instructions which write them, and later ISAs do not. Contradicting | |
505 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
506 | the UM for the NEC Vr5000) document needing the instructions between | |
507 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
508 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
509 | earlier-ISA CPUs for which CPU documentation declares that the | |
510 | instructions are really interlocked. */ | |
511 | #define hilo_interlocks \ | |
512 | (mips_opts.isa == ISA_MIPS32 \ | |
513 | || mips_opts.isa == ISA_MIPS32R2 \ | |
514 | || mips_opts.isa == ISA_MIPS64 \ | |
515 | || mips_opts.isa == ISA_MIPS64R2 \ | |
516 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 517 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
518 | || mips_opts.arch == CPU_R10000 \ |
519 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
520 | || mips_opts.arch == CPU_R14000 \ |
521 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 522 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 523 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 524 | || mips_opts.micromips \ |
c8978940 | 525 | ) |
252b5132 RH |
526 | |
527 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
528 | from the GPRs after they are loaded from memory, and thus does not |
529 | require nops to be inserted. This applies to instructions marked | |
530 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
531 | level I and microMIPS mode instructions are always interlocked. */ |
532 | #define gpr_interlocks \ | |
533 | (mips_opts.isa != ISA_MIPS1 \ | |
534 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 535 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
536 | || mips_opts.micromips \ |
537 | ) | |
252b5132 | 538 | |
81912461 ILT |
539 | /* Whether the processor uses hardware interlocks to avoid delays |
540 | required by coprocessor instructions, and thus does not require | |
541 | nops to be inserted. This applies to instructions marked | |
542 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
543 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
544 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
545 | levels I, II, and III and microMIPS mode instructions are always |
546 | interlocked. */ | |
bdaaa2e1 | 547 | /* Itbl support may require additional care here. */ |
81912461 ILT |
548 | #define cop_interlocks \ |
549 | ((mips_opts.isa != ISA_MIPS1 \ | |
550 | && mips_opts.isa != ISA_MIPS2 \ | |
551 | && mips_opts.isa != ISA_MIPS3) \ | |
552 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 553 | || mips_opts.micromips \ |
81912461 ILT |
554 | ) |
555 | ||
556 | /* Whether the processor uses hardware interlocks to protect reads | |
557 | from coprocessor registers after they are loaded from memory, and | |
558 | thus does not require nops to be inserted. This applies to | |
559 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
560 | requires at MIPS ISA level I and microMIPS mode instructions are |
561 | always interlocked. */ | |
562 | #define cop_mem_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.micromips \ | |
565 | ) | |
252b5132 | 566 | |
6b76fefe CM |
567 | /* Is this a mfhi or mflo instruction? */ |
568 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
569 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
570 | ||
df58fc94 RS |
571 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
572 | has been selected. This implies, in particular, that addresses of text | |
573 | labels have their LSB set. */ | |
574 | #define HAVE_CODE_COMPRESSION \ | |
575 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
576 | ||
252b5132 RH |
577 | /* MIPS PIC level. */ |
578 | ||
a161fe53 | 579 | enum mips_pic_level mips_pic; |
252b5132 | 580 | |
c9914766 | 581 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 582 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 583 | static int mips_big_got = 0; |
252b5132 RH |
584 | |
585 | /* 1 if trap instructions should used for overflow rather than break | |
586 | instructions. */ | |
c9914766 | 587 | static int mips_trap = 0; |
252b5132 | 588 | |
119d663a | 589 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 590 | by assembling two single width halves into two single width floating |
119d663a NC |
591 | point registers which just happen to alias the double width destination |
592 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 593 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
594 | automatically at assemble time. */ |
595 | static int mips_disable_float_construction; | |
596 | ||
252b5132 RH |
597 | /* Non-zero if any .set noreorder directives were used. */ |
598 | ||
599 | static int mips_any_noreorder; | |
600 | ||
6b76fefe CM |
601 | /* Non-zero if nops should be inserted when the register referenced in |
602 | an mfhi/mflo instruction is read in the next two instructions. */ | |
603 | static int mips_7000_hilo_fix; | |
604 | ||
02ffd3e4 | 605 | /* The size of objects in the small data section. */ |
156c2f8b | 606 | static unsigned int g_switch_value = 8; |
252b5132 RH |
607 | /* Whether the -G option was used. */ |
608 | static int g_switch_seen = 0; | |
609 | ||
610 | #define N_RMASK 0xc4 | |
611 | #define N_VFP 0xd4 | |
612 | ||
613 | /* If we can determine in advance that GP optimization won't be | |
614 | possible, we can skip the relaxation stuff that tries to produce | |
615 | GP-relative references. This makes delay slot optimization work | |
616 | better. | |
617 | ||
618 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
619 | gcc output. It needs to guess right for gcc, otherwise gcc |
620 | will put what it thinks is a GP-relative instruction in a branch | |
621 | delay slot. | |
252b5132 RH |
622 | |
623 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
624 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 625 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
626 | |
627 | /* handle of the OPCODE hash table */ | |
628 | static struct hash_control *op_hash = NULL; | |
629 | ||
630 | /* The opcode hash table we use for the mips16. */ | |
631 | static struct hash_control *mips16_op_hash = NULL; | |
632 | ||
df58fc94 RS |
633 | /* The opcode hash table we use for the microMIPS ASE. */ |
634 | static struct hash_control *micromips_op_hash = NULL; | |
635 | ||
252b5132 RH |
636 | /* This array holds the chars that always start a comment. If the |
637 | pre-processor is disabled, these aren't very useful */ | |
638 | const char comment_chars[] = "#"; | |
639 | ||
640 | /* This array holds the chars that only start a comment at the beginning of | |
641 | a line. If the line seems to have the form '# 123 filename' | |
642 | .line and .file directives will appear in the pre-processed output */ | |
643 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
644 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 645 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
646 | /* Also note that C style comments are always supported. */ |
647 | const char line_comment_chars[] = "#"; | |
648 | ||
bdaaa2e1 | 649 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 650 | const char line_separator_chars[] = ";"; |
252b5132 RH |
651 | |
652 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
653 | const char EXP_CHARS[] = "eE"; | |
654 | ||
655 | /* Chars that mean this number is a floating point constant */ | |
656 | /* As in 0f12.456 */ | |
657 | /* or 0d1.2345e12 */ | |
658 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
659 | ||
660 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
661 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
662 | but nothing is ideal around here. | |
663 | */ | |
664 | ||
665 | static char *insn_error; | |
666 | ||
667 | static int auto_align = 1; | |
668 | ||
669 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
670 | offset in the stack frame from which to restore the $gp register. | |
671 | This is set by the .cprestore pseudo-op, and saved in this | |
672 | variable. */ | |
673 | static offsetT mips_cprestore_offset = -1; | |
674 | ||
67c1ffbe | 675 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 676 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 677 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
678 | static offsetT mips_cpreturn_offset = -1; |
679 | static int mips_cpreturn_register = -1; | |
680 | static int mips_gp_register = GP; | |
def2e0dd | 681 | static int mips_gprel_offset = 0; |
6478892d | 682 | |
7a621144 DJ |
683 | /* Whether mips_cprestore_offset has been set in the current function |
684 | (or whether it has already been warned about, if not). */ | |
685 | static int mips_cprestore_valid = 0; | |
686 | ||
252b5132 RH |
687 | /* This is the register which holds the stack frame, as set by the |
688 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
689 | static int mips_frame_reg = SP; | |
690 | ||
7a621144 DJ |
691 | /* Whether mips_frame_reg has been set in the current function |
692 | (or whether it has already been warned about, if not). */ | |
693 | static int mips_frame_reg_valid = 0; | |
694 | ||
252b5132 RH |
695 | /* To output NOP instructions correctly, we need to keep information |
696 | about the previous two instructions. */ | |
697 | ||
698 | /* Whether we are optimizing. The default value of 2 means to remove | |
699 | unneeded NOPs and swap branch instructions when possible. A value | |
700 | of 1 means to not swap branches. A value of 0 means to always | |
701 | insert NOPs. */ | |
702 | static int mips_optimize = 2; | |
703 | ||
704 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
705 | equivalent to seeing no -g option at all. */ | |
706 | static int mips_debug = 0; | |
707 | ||
7d8e00cf RS |
708 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
709 | #define MAX_VR4130_NOPS 4 | |
710 | ||
711 | /* The maximum number of NOPs needed to fill delay slots. */ | |
712 | #define MAX_DELAY_NOPS 2 | |
713 | ||
714 | /* The maximum number of NOPs needed for any purpose. */ | |
715 | #define MAX_NOPS 4 | |
71400594 RS |
716 | |
717 | /* A list of previous instructions, with index 0 being the most recent. | |
718 | We need to look back MAX_NOPS instructions when filling delay slots | |
719 | or working around processor errata. We need to look back one | |
720 | instruction further if we're thinking about using history[0] to | |
721 | fill a branch delay slot. */ | |
722 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 723 | |
1e915849 | 724 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
725 | static struct mips_cl_insn nop_insn; |
726 | static struct mips_cl_insn mips16_nop_insn; | |
727 | static struct mips_cl_insn micromips_nop16_insn; | |
728 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
729 | |
730 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
731 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
732 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
733 | ||
734 | /* The size of NOP_INSN in bytes. */ | |
735 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 736 | |
252b5132 RH |
737 | /* If this is set, it points to a frag holding nop instructions which |
738 | were inserted before the start of a noreorder section. If those | |
739 | nops turn out to be unnecessary, the size of the frag can be | |
740 | decreased. */ | |
741 | static fragS *prev_nop_frag; | |
742 | ||
743 | /* The number of nop instructions we created in prev_nop_frag. */ | |
744 | static int prev_nop_frag_holds; | |
745 | ||
746 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 747 | prev_nop_frag. */ |
252b5132 RH |
748 | static int prev_nop_frag_required; |
749 | ||
750 | /* The number of instructions we've seen since prev_nop_frag. */ | |
751 | static int prev_nop_frag_since; | |
752 | ||
753 | /* For ECOFF and ELF, relocations against symbols are done in two | |
754 | parts, with a HI relocation and a LO relocation. Each relocation | |
755 | has only 16 bits of space to store an addend. This means that in | |
756 | order for the linker to handle carries correctly, it must be able | |
757 | to locate both the HI and the LO relocation. This means that the | |
758 | relocations must appear in order in the relocation table. | |
759 | ||
760 | In order to implement this, we keep track of each unmatched HI | |
761 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 762 | corresponding LO relocation. */ |
252b5132 | 763 | |
e972090a NC |
764 | struct mips_hi_fixup |
765 | { | |
252b5132 RH |
766 | /* Next HI fixup. */ |
767 | struct mips_hi_fixup *next; | |
768 | /* This fixup. */ | |
769 | fixS *fixp; | |
770 | /* The section this fixup is in. */ | |
771 | segT seg; | |
772 | }; | |
773 | ||
774 | /* The list of unmatched HI relocs. */ | |
775 | ||
776 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
777 | ||
64bdfcaf RS |
778 | /* The frag containing the last explicit relocation operator. |
779 | Null if explicit relocations have not been used. */ | |
780 | ||
781 | static fragS *prev_reloc_op_frag; | |
782 | ||
252b5132 RH |
783 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
784 | ||
785 | #define X ILLEGAL_REG | |
e972090a NC |
786 | static const int mips32_to_16_reg_map[] = |
787 | { | |
252b5132 RH |
788 | X, X, 2, 3, 4, 5, 6, 7, |
789 | X, X, X, X, X, X, X, X, | |
790 | 0, 1, X, X, X, X, X, X, | |
791 | X, X, X, X, X, X, X, X | |
792 | }; | |
793 | #undef X | |
794 | ||
795 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
796 | ||
e972090a NC |
797 | static const unsigned int mips16_to_32_reg_map[] = |
798 | { | |
252b5132 RH |
799 | 16, 17, 2, 3, 4, 5, 6, 7 |
800 | }; | |
60b63b72 | 801 | |
df58fc94 RS |
802 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
803 | ||
804 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
805 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
806 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
807 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
808 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
809 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
810 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
811 | ||
812 | #define X ILLEGAL_REG | |
813 | /* reg type h: 4, 5, 6. */ | |
814 | static const int mips32_to_micromips_reg_h_map[] = | |
815 | { | |
816 | X, X, X, X, 4, 5, 6, X, | |
817 | X, X, X, X, X, X, X, X, | |
818 | X, X, X, X, X, X, X, X, | |
819 | X, X, X, X, X, X, X, X | |
820 | }; | |
821 | ||
822 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
823 | static const int mips32_to_micromips_reg_m_map[] = | |
824 | { | |
825 | 0, X, 2, 3, X, X, X, X, | |
826 | X, X, X, X, X, X, X, X, | |
827 | 4, 1, 5, 6, 7, X, X, X, | |
828 | X, X, X, X, X, X, X, X | |
829 | }; | |
830 | ||
831 | /* reg type q: 0, 2-7. 17. */ | |
832 | static const int mips32_to_micromips_reg_q_map[] = | |
833 | { | |
834 | 0, X, 2, 3, 4, 5, 6, 7, | |
835 | X, X, X, X, X, X, X, X, | |
836 | X, 1, X, X, X, X, X, X, | |
837 | X, X, X, X, X, X, X, X | |
838 | }; | |
839 | ||
840 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
841 | #undef X | |
842 | ||
843 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
844 | ||
845 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
846 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
847 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
848 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
849 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
850 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
851 | ||
852 | /* The microMIPS registers with type h. */ | |
853 | static const unsigned int micromips_to_32_reg_h_map[] = | |
854 | { | |
855 | 5, 5, 6, 4, 4, 4, 4, 4 | |
856 | }; | |
857 | ||
858 | /* The microMIPS registers with type i. */ | |
859 | static const unsigned int micromips_to_32_reg_i_map[] = | |
860 | { | |
861 | 6, 7, 7, 21, 22, 5, 6, 7 | |
862 | }; | |
863 | ||
864 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
865 | ||
866 | /* The microMIPS registers with type m. */ | |
867 | static const unsigned int micromips_to_32_reg_m_map[] = | |
868 | { | |
869 | 0, 17, 2, 3, 16, 18, 19, 20 | |
870 | }; | |
871 | ||
872 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
873 | ||
874 | /* The microMIPS registers with type q. */ | |
875 | static const unsigned int micromips_to_32_reg_q_map[] = | |
876 | { | |
877 | 0, 17, 2, 3, 4, 5, 6, 7 | |
878 | }; | |
879 | ||
880 | /* microMIPS imm type B. */ | |
881 | static const int micromips_imm_b_map[] = | |
882 | { | |
883 | 1, 4, 8, 12, 16, 20, 24, -1 | |
884 | }; | |
885 | ||
886 | /* microMIPS imm type C. */ | |
887 | static const int micromips_imm_c_map[] = | |
888 | { | |
889 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
890 | }; | |
891 | ||
71400594 RS |
892 | /* Classifies the kind of instructions we're interested in when |
893 | implementing -mfix-vr4120. */ | |
c67a084a NC |
894 | enum fix_vr4120_class |
895 | { | |
71400594 RS |
896 | FIX_VR4120_MACC, |
897 | FIX_VR4120_DMACC, | |
898 | FIX_VR4120_MULT, | |
899 | FIX_VR4120_DMULT, | |
900 | FIX_VR4120_DIV, | |
901 | FIX_VR4120_MTHILO, | |
902 | NUM_FIX_VR4120_CLASSES | |
903 | }; | |
904 | ||
c67a084a NC |
905 | /* ...likewise -mfix-loongson2f-jump. */ |
906 | static bfd_boolean mips_fix_loongson2f_jump; | |
907 | ||
908 | /* ...likewise -mfix-loongson2f-nop. */ | |
909 | static bfd_boolean mips_fix_loongson2f_nop; | |
910 | ||
911 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
912 | static bfd_boolean mips_fix_loongson2f; | |
913 | ||
71400594 RS |
914 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
915 | there must be at least one other instruction between an instruction | |
916 | of type X and an instruction of type Y. */ | |
917 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
918 | ||
919 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 920 | static int mips_fix_vr4120; |
4a6a3df4 | 921 | |
7d8e00cf RS |
922 | /* ...likewise -mfix-vr4130. */ |
923 | static int mips_fix_vr4130; | |
924 | ||
6a32d874 CM |
925 | /* ...likewise -mfix-24k. */ |
926 | static int mips_fix_24k; | |
927 | ||
d954098f DD |
928 | /* ...likewise -mfix-cn63xxp1 */ |
929 | static bfd_boolean mips_fix_cn63xxp1; | |
930 | ||
4a6a3df4 AO |
931 | /* We don't relax branches by default, since this causes us to expand |
932 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
933 | fail to compute the offset before expanding the macro to the most | |
934 | efficient expansion. */ | |
935 | ||
936 | static int mips_relax_branch; | |
252b5132 | 937 | \f |
4d7206a2 RS |
938 | /* The expansion of many macros depends on the type of symbol that |
939 | they refer to. For example, when generating position-dependent code, | |
940 | a macro that refers to a symbol may have two different expansions, | |
941 | one which uses GP-relative addresses and one which uses absolute | |
942 | addresses. When generating SVR4-style PIC, a macro may have | |
943 | different expansions for local and global symbols. | |
944 | ||
945 | We handle these situations by generating both sequences and putting | |
946 | them in variant frags. In position-dependent code, the first sequence | |
947 | will be the GP-relative one and the second sequence will be the | |
948 | absolute one. In SVR4 PIC, the first sequence will be for global | |
949 | symbols and the second will be for local symbols. | |
950 | ||
584892a6 RS |
951 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
952 | SECOND are the lengths of the two sequences in bytes. These fields | |
953 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
954 | the subtype has the following flags: | |
4d7206a2 | 955 | |
584892a6 RS |
956 | RELAX_USE_SECOND |
957 | Set if it has been decided that we should use the second | |
958 | sequence instead of the first. | |
959 | ||
960 | RELAX_SECOND_LONGER | |
961 | Set in the first variant frag if the macro's second implementation | |
962 | is longer than its first. This refers to the macro as a whole, | |
963 | not an individual relaxation. | |
964 | ||
965 | RELAX_NOMACRO | |
966 | Set in the first variant frag if the macro appeared in a .set nomacro | |
967 | block and if one alternative requires a warning but the other does not. | |
968 | ||
969 | RELAX_DELAY_SLOT | |
970 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
971 | delay slot. | |
4d7206a2 | 972 | |
df58fc94 RS |
973 | RELAX_DELAY_SLOT_16BIT |
974 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
975 | 16-bit instruction. | |
976 | ||
977 | RELAX_DELAY_SLOT_SIZE_FIRST | |
978 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
979 | the macro is of the wrong size for the branch delay slot. | |
980 | ||
981 | RELAX_DELAY_SLOT_SIZE_SECOND | |
982 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
983 | the macro is of the wrong size for the branch delay slot. | |
984 | ||
4d7206a2 RS |
985 | The frag's "opcode" points to the first fixup for relaxable code. |
986 | ||
987 | Relaxable macros are generated using a sequence such as: | |
988 | ||
989 | relax_start (SYMBOL); | |
990 | ... generate first expansion ... | |
991 | relax_switch (); | |
992 | ... generate second expansion ... | |
993 | relax_end (); | |
994 | ||
995 | The code and fixups for the unwanted alternative are discarded | |
996 | by md_convert_frag. */ | |
584892a6 | 997 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 998 | |
584892a6 RS |
999 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1000 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1001 | #define RELAX_USE_SECOND 0x10000 | |
1002 | #define RELAX_SECOND_LONGER 0x20000 | |
1003 | #define RELAX_NOMACRO 0x40000 | |
1004 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1005 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1006 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1007 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1008 | |
4a6a3df4 AO |
1009 | /* Branch without likely bit. If label is out of range, we turn: |
1010 | ||
1011 | beq reg1, reg2, label | |
1012 | delay slot | |
1013 | ||
1014 | into | |
1015 | ||
1016 | bne reg1, reg2, 0f | |
1017 | nop | |
1018 | j label | |
1019 | 0: delay slot | |
1020 | ||
1021 | with the following opcode replacements: | |
1022 | ||
1023 | beq <-> bne | |
1024 | blez <-> bgtz | |
1025 | bltz <-> bgez | |
1026 | bc1f <-> bc1t | |
1027 | ||
1028 | bltzal <-> bgezal (with jal label instead of j label) | |
1029 | ||
1030 | Even though keeping the delay slot instruction in the delay slot of | |
1031 | the branch would be more efficient, it would be very tricky to do | |
1032 | correctly, because we'd have to introduce a variable frag *after* | |
1033 | the delay slot instruction, and expand that instead. Let's do it | |
1034 | the easy way for now, even if the branch-not-taken case now costs | |
1035 | one additional instruction. Out-of-range branches are not supposed | |
1036 | to be common, anyway. | |
1037 | ||
1038 | Branch likely. If label is out of range, we turn: | |
1039 | ||
1040 | beql reg1, reg2, label | |
1041 | delay slot (annulled if branch not taken) | |
1042 | ||
1043 | into | |
1044 | ||
1045 | beql reg1, reg2, 1f | |
1046 | nop | |
1047 | beql $0, $0, 2f | |
1048 | nop | |
1049 | 1: j[al] label | |
1050 | delay slot (executed only if branch taken) | |
1051 | 2: | |
1052 | ||
1053 | It would be possible to generate a shorter sequence by losing the | |
1054 | likely bit, generating something like: | |
b34976b6 | 1055 | |
4a6a3df4 AO |
1056 | bne reg1, reg2, 0f |
1057 | nop | |
1058 | j[al] label | |
1059 | delay slot (executed only if branch taken) | |
1060 | 0: | |
1061 | ||
1062 | beql -> bne | |
1063 | bnel -> beq | |
1064 | blezl -> bgtz | |
1065 | bgtzl -> blez | |
1066 | bltzl -> bgez | |
1067 | bgezl -> bltz | |
1068 | bc1fl -> bc1t | |
1069 | bc1tl -> bc1f | |
1070 | ||
1071 | bltzall -> bgezal (with jal label instead of j label) | |
1072 | bgezall -> bltzal (ditto) | |
1073 | ||
1074 | ||
1075 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1076 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1077 | ((relax_substateT) \ | |
1078 | (0xc0000000 \ | |
1079 | | ((at) & 0x1f) \ | |
1080 | | ((toofar) ? 0x20 : 0) \ | |
1081 | | ((link) ? 0x40 : 0) \ | |
1082 | | ((likely) ? 0x80 : 0) \ | |
1083 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1084 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1085 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1086 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1087 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1088 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1089 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1090 | |
252b5132 RH |
1091 | /* For mips16 code, we use an entirely different form of relaxation. |
1092 | mips16 supports two versions of most instructions which take | |
1093 | immediate values: a small one which takes some small value, and a | |
1094 | larger one which takes a 16 bit value. Since branches also follow | |
1095 | this pattern, relaxing these values is required. | |
1096 | ||
1097 | We can assemble both mips16 and normal MIPS code in a single | |
1098 | object. Therefore, we need to support this type of relaxation at | |
1099 | the same time that we support the relaxation described above. We | |
1100 | use the high bit of the subtype field to distinguish these cases. | |
1101 | ||
1102 | The information we store for this type of relaxation is the | |
1103 | argument code found in the opcode file for this relocation, whether | |
1104 | the user explicitly requested a small or extended form, and whether | |
1105 | the relocation is in a jump or jal delay slot. That tells us the | |
1106 | size of the value, and how it should be stored. We also store | |
1107 | whether the fragment is considered to be extended or not. We also | |
1108 | store whether this is known to be a branch to a different section, | |
1109 | whether we have tried to relax this frag yet, and whether we have | |
1110 | ever extended a PC relative fragment because of a shift count. */ | |
1111 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1112 | (0x80000000 \ | |
1113 | | ((type) & 0xff) \ | |
1114 | | ((small) ? 0x100 : 0) \ | |
1115 | | ((ext) ? 0x200 : 0) \ | |
1116 | | ((dslot) ? 0x400 : 0) \ | |
1117 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1118 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1119 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1120 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1121 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1122 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1123 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1124 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1125 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1126 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1127 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1128 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1129 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1130 | |
df58fc94 RS |
1131 | /* For microMIPS code, we use relaxation similar to one we use for |
1132 | MIPS16 code. Some instructions that take immediate values support | |
1133 | two encodings: a small one which takes some small value, and a | |
1134 | larger one which takes a 16 bit value. As some branches also follow | |
1135 | this pattern, relaxing these values is required. | |
1136 | ||
1137 | We can assemble both microMIPS and normal MIPS code in a single | |
1138 | object. Therefore, we need to support this type of relaxation at | |
1139 | the same time that we support the relaxation described above. We | |
1140 | use one of the high bits of the subtype field to distinguish these | |
1141 | cases. | |
1142 | ||
1143 | The information we store for this type of relaxation is the argument | |
1144 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1145 | selected as the assembler temporary, whether the branch is |
1146 | unconditional, whether it is compact, whether it stores the link | |
1147 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1148 | branches to a sequence of instructions is enabled, and whether the | |
1149 | displacement of a branch is too large to fit as an immediate argument | |
1150 | of a 16-bit and a 32-bit branch, respectively. */ | |
1151 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1152 | relax32, toofar16, toofar32) \ | |
1153 | (0x40000000 \ | |
1154 | | ((type) & 0xff) \ | |
1155 | | (((at) & 0x1f) << 8) \ | |
1156 | | ((uncond) ? 0x2000 : 0) \ | |
1157 | | ((compact) ? 0x4000 : 0) \ | |
1158 | | ((link) ? 0x8000 : 0) \ | |
1159 | | ((relax32) ? 0x10000 : 0) \ | |
1160 | | ((toofar16) ? 0x20000 : 0) \ | |
1161 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1162 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1163 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1164 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1165 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1166 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1167 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1168 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1169 | ||
1170 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1171 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1172 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1173 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1174 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1175 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1176 | |
43c0598f RS |
1177 | /* Sign-extend 16-bit value X. */ |
1178 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1179 | ||
885add95 CD |
1180 | /* Is the given value a sign-extended 32-bit value? */ |
1181 | #define IS_SEXT_32BIT_NUM(x) \ | |
1182 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1183 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1184 | ||
1185 | /* Is the given value a sign-extended 16-bit value? */ | |
1186 | #define IS_SEXT_16BIT_NUM(x) \ | |
1187 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1188 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1189 | ||
df58fc94 RS |
1190 | /* Is the given value a sign-extended 12-bit value? */ |
1191 | #define IS_SEXT_12BIT_NUM(x) \ | |
1192 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1193 | ||
7f3c4072 CM |
1194 | /* Is the given value a sign-extended 9-bit value? */ |
1195 | #define IS_SEXT_9BIT_NUM(x) \ | |
1196 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1197 | ||
2051e8c4 MR |
1198 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1199 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1200 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1201 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1202 | ||
bf12938e RS |
1203 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1204 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1205 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1206 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1207 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1208 | ||
1209 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1210 | SHIFT places. */ | |
1211 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1212 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1213 | ||
1214 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1215 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1216 | ||
1217 | include/opcode/mips.h specifies operand fields using the macros | |
1218 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1219 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1220 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1221 | do \ | |
1222 | if (!(MICROMIPS)) \ | |
1223 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1224 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1225 | else \ | |
1226 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1227 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1228 | while (0) | |
bf12938e RS |
1229 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1230 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1231 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1232 | ||
1233 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1234 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1235 | (!(MICROMIPS) \ | |
1236 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1237 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1238 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1239 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1240 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1241 | MIPS16OP_MASK_##FIELD, \ | |
1242 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1243 | |
1244 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1245 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1246 | \f |
df58fc94 RS |
1247 | /* Whether or not we are emitting a branch-likely macro. */ |
1248 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1249 | ||
4d7206a2 RS |
1250 | /* Global variables used when generating relaxable macros. See the |
1251 | comment above RELAX_ENCODE for more details about how relaxation | |
1252 | is used. */ | |
1253 | static struct { | |
1254 | /* 0 if we're not emitting a relaxable macro. | |
1255 | 1 if we're emitting the first of the two relaxation alternatives. | |
1256 | 2 if we're emitting the second alternative. */ | |
1257 | int sequence; | |
1258 | ||
1259 | /* The first relaxable fixup in the current frag. (In other words, | |
1260 | the first fixup that refers to relaxable code.) */ | |
1261 | fixS *first_fixup; | |
1262 | ||
1263 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1264 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1265 | unsigned int sizes[2]; | |
1266 | ||
1267 | /* The symbol on which the choice of sequence depends. */ | |
1268 | symbolS *symbol; | |
1269 | } mips_relax; | |
252b5132 | 1270 | \f |
584892a6 RS |
1271 | /* Global variables used to decide whether a macro needs a warning. */ |
1272 | static struct { | |
1273 | /* True if the macro is in a branch delay slot. */ | |
1274 | bfd_boolean delay_slot_p; | |
1275 | ||
df58fc94 RS |
1276 | /* Set to the length in bytes required if the macro is in a delay slot |
1277 | that requires a specific length of instruction, otherwise zero. */ | |
1278 | unsigned int delay_slot_length; | |
1279 | ||
584892a6 RS |
1280 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1281 | in bytes and sizes[1] is the length of the second alternative. | |
1282 | For non-relaxable macros, both elements give the length of the | |
1283 | macro in bytes. */ | |
1284 | unsigned int sizes[2]; | |
1285 | ||
df58fc94 RS |
1286 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1287 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1288 | is the length of the first instruction of the second alternative. | |
1289 | For non-relaxable macros, both elements give the length of the first | |
1290 | instruction in bytes. | |
1291 | ||
1292 | Set to zero if we haven't yet seen the first instruction. */ | |
1293 | unsigned int first_insn_sizes[2]; | |
1294 | ||
1295 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1296 | first alternative and insns[1] is the number of instructions for the | |
1297 | second alternative. | |
1298 | ||
1299 | For non-relaxable macros, both elements give the number of | |
1300 | instructions for the macro. */ | |
1301 | unsigned int insns[2]; | |
1302 | ||
584892a6 RS |
1303 | /* The first variant frag for this macro. */ |
1304 | fragS *first_frag; | |
1305 | } mips_macro_warning; | |
1306 | \f | |
252b5132 RH |
1307 | /* Prototypes for static functions. */ |
1308 | ||
252b5132 RH |
1309 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1310 | ||
b34976b6 | 1311 | static void append_insn |
df58fc94 RS |
1312 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1313 | bfd_boolean expansionp); | |
7d10b47d | 1314 | static void mips_no_prev_insn (void); |
c67a084a | 1315 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1316 | static void mips16_macro_build |
03ea81db | 1317 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1318 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1319 | static void macro_start (void); |
1320 | static void macro_end (void); | |
17a2f251 TS |
1321 | static void macro (struct mips_cl_insn * ip); |
1322 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1323 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1324 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1325 | static void mips16_immed |
43c0598f RS |
1326 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1327 | unsigned int, unsigned long *); | |
5e0116d5 | 1328 | static size_t my_getSmallExpression |
17a2f251 TS |
1329 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1330 | static void my_getExpression (expressionS *, char *); | |
1331 | static void s_align (int); | |
1332 | static void s_change_sec (int); | |
1333 | static void s_change_section (int); | |
1334 | static void s_cons (int); | |
1335 | static void s_float_cons (int); | |
1336 | static void s_mips_globl (int); | |
1337 | static void s_option (int); | |
1338 | static void s_mipsset (int); | |
1339 | static void s_abicalls (int); | |
1340 | static void s_cpload (int); | |
1341 | static void s_cpsetup (int); | |
1342 | static void s_cplocal (int); | |
1343 | static void s_cprestore (int); | |
1344 | static void s_cpreturn (int); | |
741d6ea8 JM |
1345 | static void s_dtprelword (int); |
1346 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1347 | static void s_tprelword (int); |
1348 | static void s_tpreldword (int); | |
17a2f251 TS |
1349 | static void s_gpvalue (int); |
1350 | static void s_gpword (int); | |
1351 | static void s_gpdword (int); | |
a3f278e2 | 1352 | static void s_ehword (int); |
17a2f251 TS |
1353 | static void s_cpadd (int); |
1354 | static void s_insn (int); | |
1355 | static void md_obj_begin (void); | |
1356 | static void md_obj_end (void); | |
1357 | static void s_mips_ent (int); | |
1358 | static void s_mips_end (int); | |
1359 | static void s_mips_frame (int); | |
1360 | static void s_mips_mask (int reg_type); | |
1361 | static void s_mips_stab (int); | |
1362 | static void s_mips_weakext (int); | |
1363 | static void s_mips_file (int); | |
1364 | static void s_mips_loc (int); | |
1365 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1366 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1367 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1368 | static int validate_micromips_insn (const struct mips_opcode *); |
1369 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1370 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1371 | |
1372 | /* Table and functions used to map between CPU/ISA names, and | |
1373 | ISA levels, and CPU numbers. */ | |
1374 | ||
e972090a NC |
1375 | struct mips_cpu_info |
1376 | { | |
e7af610e | 1377 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1378 | int flags; /* MIPS_CPU_* flags. */ |
1379 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1380 | int isa; /* ISA level. */ |
1381 | int cpu; /* CPU number (default CPU if ISA). */ | |
1382 | }; | |
1383 | ||
ad3fea08 | 1384 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1385 | |
17a2f251 TS |
1386 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1387 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1388 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1389 | \f |
c31f3936 RS |
1390 | /* Command-line options. */ |
1391 | const char *md_shortopts = "O::g::G:"; | |
1392 | ||
1393 | enum options | |
1394 | { | |
1395 | OPTION_MARCH = OPTION_MD_BASE, | |
1396 | OPTION_MTUNE, | |
1397 | OPTION_MIPS1, | |
1398 | OPTION_MIPS2, | |
1399 | OPTION_MIPS3, | |
1400 | OPTION_MIPS4, | |
1401 | OPTION_MIPS5, | |
1402 | OPTION_MIPS32, | |
1403 | OPTION_MIPS64, | |
1404 | OPTION_MIPS32R2, | |
1405 | OPTION_MIPS64R2, | |
1406 | OPTION_MIPS16, | |
1407 | OPTION_NO_MIPS16, | |
1408 | OPTION_MIPS3D, | |
1409 | OPTION_NO_MIPS3D, | |
1410 | OPTION_MDMX, | |
1411 | OPTION_NO_MDMX, | |
1412 | OPTION_DSP, | |
1413 | OPTION_NO_DSP, | |
1414 | OPTION_MT, | |
1415 | OPTION_NO_MT, | |
1416 | OPTION_VIRT, | |
1417 | OPTION_NO_VIRT, | |
1418 | OPTION_SMARTMIPS, | |
1419 | OPTION_NO_SMARTMIPS, | |
1420 | OPTION_DSPR2, | |
1421 | OPTION_NO_DSPR2, | |
1422 | OPTION_EVA, | |
1423 | OPTION_NO_EVA, | |
1424 | OPTION_MICROMIPS, | |
1425 | OPTION_NO_MICROMIPS, | |
1426 | OPTION_MCU, | |
1427 | OPTION_NO_MCU, | |
1428 | OPTION_COMPAT_ARCH_BASE, | |
1429 | OPTION_M4650, | |
1430 | OPTION_NO_M4650, | |
1431 | OPTION_M4010, | |
1432 | OPTION_NO_M4010, | |
1433 | OPTION_M4100, | |
1434 | OPTION_NO_M4100, | |
1435 | OPTION_M3900, | |
1436 | OPTION_NO_M3900, | |
1437 | OPTION_M7000_HILO_FIX, | |
1438 | OPTION_MNO_7000_HILO_FIX, | |
1439 | OPTION_FIX_24K, | |
1440 | OPTION_NO_FIX_24K, | |
1441 | OPTION_FIX_LOONGSON2F_JUMP, | |
1442 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1443 | OPTION_FIX_LOONGSON2F_NOP, | |
1444 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1445 | OPTION_FIX_VR4120, | |
1446 | OPTION_NO_FIX_VR4120, | |
1447 | OPTION_FIX_VR4130, | |
1448 | OPTION_NO_FIX_VR4130, | |
1449 | OPTION_FIX_CN63XXP1, | |
1450 | OPTION_NO_FIX_CN63XXP1, | |
1451 | OPTION_TRAP, | |
1452 | OPTION_BREAK, | |
1453 | OPTION_EB, | |
1454 | OPTION_EL, | |
1455 | OPTION_FP32, | |
1456 | OPTION_GP32, | |
1457 | OPTION_CONSTRUCT_FLOATS, | |
1458 | OPTION_NO_CONSTRUCT_FLOATS, | |
1459 | OPTION_FP64, | |
1460 | OPTION_GP64, | |
1461 | OPTION_RELAX_BRANCH, | |
1462 | OPTION_NO_RELAX_BRANCH, | |
1463 | OPTION_MSHARED, | |
1464 | OPTION_MNO_SHARED, | |
1465 | OPTION_MSYM32, | |
1466 | OPTION_MNO_SYM32, | |
1467 | OPTION_SOFT_FLOAT, | |
1468 | OPTION_HARD_FLOAT, | |
1469 | OPTION_SINGLE_FLOAT, | |
1470 | OPTION_DOUBLE_FLOAT, | |
1471 | OPTION_32, | |
1472 | #ifdef OBJ_ELF | |
1473 | OPTION_CALL_SHARED, | |
1474 | OPTION_CALL_NONPIC, | |
1475 | OPTION_NON_SHARED, | |
1476 | OPTION_XGOT, | |
1477 | OPTION_MABI, | |
1478 | OPTION_N32, | |
1479 | OPTION_64, | |
1480 | OPTION_MDEBUG, | |
1481 | OPTION_NO_MDEBUG, | |
1482 | OPTION_PDR, | |
1483 | OPTION_NO_PDR, | |
1484 | OPTION_MVXWORKS_PIC, | |
1485 | #endif /* OBJ_ELF */ | |
1486 | OPTION_END_OF_ENUM | |
1487 | }; | |
1488 | ||
1489 | struct option md_longopts[] = | |
1490 | { | |
1491 | /* Options which specify architecture. */ | |
1492 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1493 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1494 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1495 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1496 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1497 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1498 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1499 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1500 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1501 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1502 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
1503 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
1504 | ||
1505 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1506 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1507 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1508 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1509 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1510 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1511 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1512 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1513 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1514 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1515 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1516 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1517 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1518 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1519 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1520 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1521 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1522 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1523 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1524 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1525 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1526 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1527 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
1528 | ||
1529 | /* Old-style architecture options. Don't add more of these. */ | |
1530 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1531 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1532 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1533 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1534 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1535 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1536 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1537 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1538 | ||
1539 | /* Options which enable bug fixes. */ | |
1540 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1541 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1542 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1543 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1544 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1545 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1546 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1547 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1548 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1549 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1550 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1551 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1552 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
1553 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, | |
1554 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1555 | ||
1556 | /* Miscellaneous options. */ | |
1557 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1558 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1559 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1560 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1561 | {"EB", no_argument, NULL, OPTION_EB}, | |
1562 | {"EL", no_argument, NULL, OPTION_EL}, | |
1563 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1564 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1565 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1566 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1567 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1568 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1569 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1570 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
1571 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
1572 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1573 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1574 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1575 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1576 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1577 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1578 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1579 | ||
1580 | /* Strictly speaking this next option is ELF specific, | |
1581 | but we allow it for other ports as well in order to | |
1582 | make testing easier. */ | |
1583 | {"32", no_argument, NULL, OPTION_32}, | |
1584 | ||
1585 | /* ELF-specific options. */ | |
1586 | #ifdef OBJ_ELF | |
1587 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
1588 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1589 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1590 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1591 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1592 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1593 | {"n32", no_argument, NULL, OPTION_N32}, | |
1594 | {"64", no_argument, NULL, OPTION_64}, | |
1595 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1596 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1597 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1598 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1599 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
1600 | #endif /* OBJ_ELF */ | |
1601 | ||
1602 | {NULL, no_argument, NULL, 0} | |
1603 | }; | |
1604 | size_t md_longopts_size = sizeof (md_longopts); | |
1605 | \f | |
252b5132 RH |
1606 | /* Pseudo-op table. |
1607 | ||
1608 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1609 | should be defined here, but are currently unsupported: .alias, | |
1610 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1611 | ||
1612 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1613 | specific to the type of debugging information being generated, and | |
1614 | should be defined by the object format: .aent, .begin, .bend, | |
1615 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1616 | .vreg. | |
1617 | ||
1618 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1619 | not MIPS CPU specific, but are also not specific to the object file | |
1620 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1621 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1622 | |
e972090a NC |
1623 | static const pseudo_typeS mips_pseudo_table[] = |
1624 | { | |
beae10d5 | 1625 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1626 | {"option", s_option, 0}, |
1627 | {"set", s_mipsset, 0}, | |
1628 | {"rdata", s_change_sec, 'r'}, | |
1629 | {"sdata", s_change_sec, 's'}, | |
1630 | {"livereg", s_ignore, 0}, | |
1631 | {"abicalls", s_abicalls, 0}, | |
1632 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1633 | {"cpsetup", s_cpsetup, 0}, |
1634 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1635 | {"cprestore", s_cprestore, 0}, |
6478892d | 1636 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1637 | {"dtprelword", s_dtprelword, 0}, |
1638 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1639 | {"tprelword", s_tprelword, 0}, |
1640 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1641 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1642 | {"gpword", s_gpword, 0}, |
10181a0d | 1643 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1644 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1645 | {"cpadd", s_cpadd, 0}, |
1646 | {"insn", s_insn, 0}, | |
1647 | ||
beae10d5 | 1648 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1649 | chips. */ |
38a57ae7 | 1650 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1651 | {"bss", s_change_sec, 'b'}, |
1652 | {"err", s_err, 0}, | |
1653 | {"half", s_cons, 1}, | |
1654 | {"dword", s_cons, 3}, | |
1655 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1656 | {"origin", s_org, 0}, |
1657 | {"repeat", s_rept, 0}, | |
252b5132 | 1658 | |
998b3c36 MR |
1659 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1660 | {"sbss", s_change_sec, 'B'}, | |
1661 | ||
beae10d5 | 1662 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1663 | here for one reason or another. */ |
1664 | {"align", s_align, 0}, | |
1665 | {"byte", s_cons, 0}, | |
1666 | {"data", s_change_sec, 'd'}, | |
1667 | {"double", s_float_cons, 'd'}, | |
1668 | {"float", s_float_cons, 'f'}, | |
1669 | {"globl", s_mips_globl, 0}, | |
1670 | {"global", s_mips_globl, 0}, | |
1671 | {"hword", s_cons, 1}, | |
1672 | {"int", s_cons, 2}, | |
1673 | {"long", s_cons, 2}, | |
1674 | {"octa", s_cons, 4}, | |
1675 | {"quad", s_cons, 3}, | |
cca86cc8 | 1676 | {"section", s_change_section, 0}, |
252b5132 RH |
1677 | {"short", s_cons, 1}, |
1678 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1679 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1680 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1681 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1682 | {"text", s_change_sec, 't'}, |
1683 | {"word", s_cons, 2}, | |
add56521 | 1684 | |
add56521 | 1685 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1686 | |
43841e91 | 1687 | { NULL, NULL, 0 }, |
252b5132 RH |
1688 | }; |
1689 | ||
e972090a NC |
1690 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1691 | { | |
beae10d5 KH |
1692 | /* These pseudo-ops should be defined by the object file format. |
1693 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1694 | {"aent", s_mips_ent, 1}, |
1695 | {"bgnb", s_ignore, 0}, | |
1696 | {"end", s_mips_end, 0}, | |
1697 | {"endb", s_ignore, 0}, | |
1698 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1699 | {"file", s_mips_file, 0}, |
252b5132 RH |
1700 | {"fmask", s_mips_mask, 'F'}, |
1701 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1702 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1703 | {"mask", s_mips_mask, 'R'}, |
1704 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1705 | { NULL, NULL, 0 }, |
252b5132 RH |
1706 | }; |
1707 | ||
3ae8dd8d MR |
1708 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1709 | purpose of the `.dc.a' internal pseudo-op. */ | |
1710 | ||
1711 | int | |
1712 | mips_address_bytes (void) | |
1713 | { | |
1714 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1715 | } | |
1716 | ||
17a2f251 | 1717 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1718 | |
1719 | void | |
17a2f251 | 1720 | mips_pop_insert (void) |
252b5132 RH |
1721 | { |
1722 | pop_insert (mips_pseudo_table); | |
1723 | if (! ECOFF_DEBUGGING) | |
1724 | pop_insert (mips_nonecoff_pseudo_table); | |
1725 | } | |
1726 | \f | |
1727 | /* Symbols labelling the current insn. */ | |
1728 | ||
e972090a NC |
1729 | struct insn_label_list |
1730 | { | |
252b5132 RH |
1731 | struct insn_label_list *next; |
1732 | symbolS *label; | |
1733 | }; | |
1734 | ||
252b5132 | 1735 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1736 | #define label_list tc_segment_info_data.labels |
252b5132 | 1737 | |
17a2f251 | 1738 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1739 | static void mips_mark_labels (void); |
1740 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1741 | |
1742 | static inline void | |
17a2f251 | 1743 | mips_clear_insn_labels (void) |
252b5132 RH |
1744 | { |
1745 | register struct insn_label_list **pl; | |
a8dbcb85 | 1746 | segment_info_type *si; |
252b5132 | 1747 | |
a8dbcb85 TS |
1748 | if (now_seg) |
1749 | { | |
1750 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1751 | ; | |
1752 | ||
1753 | si = seg_info (now_seg); | |
1754 | *pl = si->label_list; | |
1755 | si->label_list = NULL; | |
1756 | } | |
252b5132 | 1757 | } |
a8dbcb85 | 1758 | |
df58fc94 RS |
1759 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1760 | ||
1761 | static inline void | |
1762 | mips_mark_labels (void) | |
1763 | { | |
1764 | if (HAVE_CODE_COMPRESSION) | |
1765 | mips_compressed_mark_labels (); | |
1766 | } | |
252b5132 RH |
1767 | \f |
1768 | static char *expr_end; | |
1769 | ||
1770 | /* Expressions which appear in instructions. These are set by | |
1771 | mips_ip. */ | |
1772 | ||
1773 | static expressionS imm_expr; | |
5f74bc13 | 1774 | static expressionS imm2_expr; |
252b5132 RH |
1775 | static expressionS offset_expr; |
1776 | ||
1777 | /* Relocs associated with imm_expr and offset_expr. */ | |
1778 | ||
f6688943 TS |
1779 | static bfd_reloc_code_real_type imm_reloc[3] |
1780 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1781 | static bfd_reloc_code_real_type offset_reloc[3] | |
1782 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1783 | |
df58fc94 RS |
1784 | /* This is set to the resulting size of the instruction to be produced |
1785 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1786 | explicit size is supplied. */ | |
252b5132 | 1787 | |
df58fc94 | 1788 | static unsigned int forced_insn_length; |
252b5132 | 1789 | |
e1b47bd5 RS |
1790 | /* True if we are assembling an instruction. All dot symbols defined during |
1791 | this time should be treated as code labels. */ | |
1792 | ||
1793 | static bfd_boolean mips_assembling_insn; | |
1794 | ||
7ed4a06a | 1795 | #ifdef OBJ_ELF |
ecb4347a DJ |
1796 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1797 | ECOFF debugging. */ | |
252b5132 RH |
1798 | |
1799 | static segT pdr_seg; | |
7ed4a06a | 1800 | #endif |
252b5132 | 1801 | |
e013f690 TS |
1802 | /* The default target format to use. */ |
1803 | ||
aeffff67 RS |
1804 | #if defined (TE_FreeBSD) |
1805 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1806 | #elif defined (TE_TMIPS) | |
1807 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1808 | #else | |
1809 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1810 | #endif | |
1811 | ||
e013f690 | 1812 | const char * |
17a2f251 | 1813 | mips_target_format (void) |
e013f690 TS |
1814 | { |
1815 | switch (OUTPUT_FLAVOR) | |
1816 | { | |
e013f690 TS |
1817 | case bfd_target_ecoff_flavour: |
1818 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1819 | case bfd_target_coff_flavour: | |
1820 | return "pe-mips"; | |
1821 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1822 | #ifdef TE_VXWORKS |
1823 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1824 | return (target_big_endian | |
1825 | ? "elf32-bigmips-vxworks" | |
1826 | : "elf32-littlemips-vxworks"); | |
1827 | #endif | |
e013f690 | 1828 | return (target_big_endian |
cfe86eaa | 1829 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1830 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1831 | : (HAVE_NEWABI |
aeffff67 RS |
1832 | ? ELF_TARGET ("elf32-n", "big") |
1833 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1834 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1835 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1836 | : (HAVE_NEWABI |
aeffff67 RS |
1837 | ? ELF_TARGET ("elf32-n", "little") |
1838 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1839 | default: |
1840 | abort (); | |
1841 | return NULL; | |
1842 | } | |
1843 | } | |
1844 | ||
df58fc94 RS |
1845 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1846 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1847 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1848 | major opcode) will require further modifications to the opcode | |
1849 | table. */ | |
1850 | ||
1851 | static inline unsigned int | |
1852 | micromips_insn_length (const struct mips_opcode *mo) | |
1853 | { | |
1854 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1855 | } | |
1856 | ||
5c04167a RS |
1857 | /* Return the length of MIPS16 instruction OPCODE. */ |
1858 | ||
1859 | static inline unsigned int | |
1860 | mips16_opcode_length (unsigned long opcode) | |
1861 | { | |
1862 | return (opcode >> 16) == 0 ? 2 : 4; | |
1863 | } | |
1864 | ||
1e915849 RS |
1865 | /* Return the length of instruction INSN. */ |
1866 | ||
1867 | static inline unsigned int | |
1868 | insn_length (const struct mips_cl_insn *insn) | |
1869 | { | |
df58fc94 RS |
1870 | if (mips_opts.micromips) |
1871 | return micromips_insn_length (insn->insn_mo); | |
1872 | else if (mips_opts.mips16) | |
5c04167a | 1873 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1874 | else |
1e915849 | 1875 | return 4; |
1e915849 RS |
1876 | } |
1877 | ||
1878 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1879 | ||
1880 | static void | |
1881 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1882 | { | |
1883 | size_t i; | |
1884 | ||
1885 | insn->insn_mo = mo; | |
1e915849 RS |
1886 | insn->insn_opcode = mo->match; |
1887 | insn->frag = NULL; | |
1888 | insn->where = 0; | |
1889 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1890 | insn->fixp[i] = NULL; | |
1891 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1892 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1893 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1894 | insn->complete_p = 0; |
e407c74b | 1895 | insn->cleared_p = 0; |
1e915849 RS |
1896 | } |
1897 | ||
df58fc94 | 1898 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1899 | |
1900 | static void | |
df58fc94 | 1901 | mips_record_compressed_mode (void) |
742a56fe RS |
1902 | { |
1903 | segment_info_type *si; | |
1904 | ||
1905 | si = seg_info (now_seg); | |
1906 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1907 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1908 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1909 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1910 | } |
1911 | ||
4d68580a RS |
1912 | /* Read a standard MIPS instruction from BUF. */ |
1913 | ||
1914 | static unsigned long | |
1915 | read_insn (char *buf) | |
1916 | { | |
1917 | if (target_big_endian) | |
1918 | return bfd_getb32 ((bfd_byte *) buf); | |
1919 | else | |
1920 | return bfd_getl32 ((bfd_byte *) buf); | |
1921 | } | |
1922 | ||
1923 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1924 | the next byte. */ | |
1925 | ||
1926 | static char * | |
1927 | write_insn (char *buf, unsigned int insn) | |
1928 | { | |
1929 | md_number_to_chars (buf, insn, 4); | |
1930 | return buf + 4; | |
1931 | } | |
1932 | ||
1933 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1934 | has length LENGTH. */ | |
1935 | ||
1936 | static unsigned long | |
1937 | read_compressed_insn (char *buf, unsigned int length) | |
1938 | { | |
1939 | unsigned long insn; | |
1940 | unsigned int i; | |
1941 | ||
1942 | insn = 0; | |
1943 | for (i = 0; i < length; i += 2) | |
1944 | { | |
1945 | insn <<= 16; | |
1946 | if (target_big_endian) | |
1947 | insn |= bfd_getb16 ((char *) buf); | |
1948 | else | |
1949 | insn |= bfd_getl16 ((char *) buf); | |
1950 | buf += 2; | |
1951 | } | |
1952 | return insn; | |
1953 | } | |
1954 | ||
5c04167a RS |
1955 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1956 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1957 | ||
1958 | static char * | |
1959 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1960 | { | |
1961 | unsigned int i; | |
1962 | ||
1963 | for (i = 0; i < length; i += 2) | |
1964 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1965 | return buf + length; | |
1966 | } | |
1967 | ||
1e915849 RS |
1968 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1969 | ||
1970 | static void | |
1971 | install_insn (const struct mips_cl_insn *insn) | |
1972 | { | |
1973 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1974 | if (HAVE_CODE_COMPRESSION) |
1975 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1976 | else |
4d68580a | 1977 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1978 | mips_record_compressed_mode (); |
1e915849 RS |
1979 | } |
1980 | ||
1981 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1982 | and install the opcode in the new location. */ | |
1983 | ||
1984 | static void | |
1985 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1986 | { | |
1987 | size_t i; | |
1988 | ||
1989 | insn->frag = frag; | |
1990 | insn->where = where; | |
1991 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1992 | if (insn->fixp[i] != NULL) | |
1993 | { | |
1994 | insn->fixp[i]->fx_frag = frag; | |
1995 | insn->fixp[i]->fx_where = where; | |
1996 | } | |
1997 | install_insn (insn); | |
1998 | } | |
1999 | ||
2000 | /* Add INSN to the end of the output. */ | |
2001 | ||
2002 | static void | |
2003 | add_fixed_insn (struct mips_cl_insn *insn) | |
2004 | { | |
2005 | char *f = frag_more (insn_length (insn)); | |
2006 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2007 | } | |
2008 | ||
2009 | /* Start a variant frag and move INSN to the start of the variant part, | |
2010 | marking it as fixed. The other arguments are as for frag_var. */ | |
2011 | ||
2012 | static void | |
2013 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2014 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2015 | { | |
2016 | frag_grow (max_chars); | |
2017 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2018 | insn->fixed_p = 1; | |
2019 | frag_var (rs_machine_dependent, max_chars, var, | |
2020 | subtype, symbol, offset, NULL); | |
2021 | } | |
2022 | ||
2023 | /* Insert N copies of INSN into the history buffer, starting at | |
2024 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2025 | ||
2026 | static void | |
2027 | insert_into_history (unsigned int first, unsigned int n, | |
2028 | const struct mips_cl_insn *insn) | |
2029 | { | |
2030 | if (mips_relax.sequence != 2) | |
2031 | { | |
2032 | unsigned int i; | |
2033 | ||
2034 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2035 | if (i >= first + n) | |
2036 | history[i] = history[i - n]; | |
2037 | else | |
2038 | history[i] = *insn; | |
2039 | } | |
2040 | } | |
2041 | ||
71400594 RS |
2042 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2043 | the idea is to make it obvious at a glance that each errata is | |
2044 | included. */ | |
2045 | ||
2046 | static void | |
2047 | init_vr4120_conflicts (void) | |
2048 | { | |
2049 | #define CONFLICT(FIRST, SECOND) \ | |
2050 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2051 | ||
2052 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2053 | CONFLICT (MACC, DIV); | |
2054 | CONFLICT (DMACC, DIV); | |
2055 | ||
2056 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2057 | CONFLICT (DMULT, DMULT); | |
2058 | CONFLICT (DMULT, DMACC); | |
2059 | CONFLICT (DMACC, DMULT); | |
2060 | CONFLICT (DMACC, DMACC); | |
2061 | ||
2062 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2063 | CONFLICT (MACC, MTHILO); | |
2064 | CONFLICT (DMACC, MTHILO); | |
2065 | ||
2066 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2067 | instruction is executed immediately after a MACC or DMACC | |
2068 | instruction, the result of [either instruction] is incorrect." */ | |
2069 | CONFLICT (MACC, MULT); | |
2070 | CONFLICT (MACC, DMULT); | |
2071 | CONFLICT (DMACC, MULT); | |
2072 | CONFLICT (DMACC, DMULT); | |
2073 | ||
2074 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2075 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2076 | DDIV or DDIVU instruction, the result of the MACC or | |
2077 | DMACC instruction is incorrect.". */ | |
2078 | CONFLICT (DMULT, MACC); | |
2079 | CONFLICT (DMULT, DMACC); | |
2080 | CONFLICT (DIV, MACC); | |
2081 | CONFLICT (DIV, DMACC); | |
2082 | ||
2083 | #undef CONFLICT | |
2084 | } | |
2085 | ||
707bfff6 TS |
2086 | struct regname { |
2087 | const char *name; | |
2088 | unsigned int num; | |
2089 | }; | |
2090 | ||
2091 | #define RTYPE_MASK 0x1ff00 | |
2092 | #define RTYPE_NUM 0x00100 | |
2093 | #define RTYPE_FPU 0x00200 | |
2094 | #define RTYPE_FCC 0x00400 | |
2095 | #define RTYPE_VEC 0x00800 | |
2096 | #define RTYPE_GP 0x01000 | |
2097 | #define RTYPE_CP0 0x02000 | |
2098 | #define RTYPE_PC 0x04000 | |
2099 | #define RTYPE_ACC 0x08000 | |
2100 | #define RTYPE_CCC 0x10000 | |
2101 | #define RNUM_MASK 0x000ff | |
2102 | #define RWARN 0x80000 | |
2103 | ||
2104 | #define GENERIC_REGISTER_NUMBERS \ | |
2105 | {"$0", RTYPE_NUM | 0}, \ | |
2106 | {"$1", RTYPE_NUM | 1}, \ | |
2107 | {"$2", RTYPE_NUM | 2}, \ | |
2108 | {"$3", RTYPE_NUM | 3}, \ | |
2109 | {"$4", RTYPE_NUM | 4}, \ | |
2110 | {"$5", RTYPE_NUM | 5}, \ | |
2111 | {"$6", RTYPE_NUM | 6}, \ | |
2112 | {"$7", RTYPE_NUM | 7}, \ | |
2113 | {"$8", RTYPE_NUM | 8}, \ | |
2114 | {"$9", RTYPE_NUM | 9}, \ | |
2115 | {"$10", RTYPE_NUM | 10}, \ | |
2116 | {"$11", RTYPE_NUM | 11}, \ | |
2117 | {"$12", RTYPE_NUM | 12}, \ | |
2118 | {"$13", RTYPE_NUM | 13}, \ | |
2119 | {"$14", RTYPE_NUM | 14}, \ | |
2120 | {"$15", RTYPE_NUM | 15}, \ | |
2121 | {"$16", RTYPE_NUM | 16}, \ | |
2122 | {"$17", RTYPE_NUM | 17}, \ | |
2123 | {"$18", RTYPE_NUM | 18}, \ | |
2124 | {"$19", RTYPE_NUM | 19}, \ | |
2125 | {"$20", RTYPE_NUM | 20}, \ | |
2126 | {"$21", RTYPE_NUM | 21}, \ | |
2127 | {"$22", RTYPE_NUM | 22}, \ | |
2128 | {"$23", RTYPE_NUM | 23}, \ | |
2129 | {"$24", RTYPE_NUM | 24}, \ | |
2130 | {"$25", RTYPE_NUM | 25}, \ | |
2131 | {"$26", RTYPE_NUM | 26}, \ | |
2132 | {"$27", RTYPE_NUM | 27}, \ | |
2133 | {"$28", RTYPE_NUM | 28}, \ | |
2134 | {"$29", RTYPE_NUM | 29}, \ | |
2135 | {"$30", RTYPE_NUM | 30}, \ | |
2136 | {"$31", RTYPE_NUM | 31} | |
2137 | ||
2138 | #define FPU_REGISTER_NAMES \ | |
2139 | {"$f0", RTYPE_FPU | 0}, \ | |
2140 | {"$f1", RTYPE_FPU | 1}, \ | |
2141 | {"$f2", RTYPE_FPU | 2}, \ | |
2142 | {"$f3", RTYPE_FPU | 3}, \ | |
2143 | {"$f4", RTYPE_FPU | 4}, \ | |
2144 | {"$f5", RTYPE_FPU | 5}, \ | |
2145 | {"$f6", RTYPE_FPU | 6}, \ | |
2146 | {"$f7", RTYPE_FPU | 7}, \ | |
2147 | {"$f8", RTYPE_FPU | 8}, \ | |
2148 | {"$f9", RTYPE_FPU | 9}, \ | |
2149 | {"$f10", RTYPE_FPU | 10}, \ | |
2150 | {"$f11", RTYPE_FPU | 11}, \ | |
2151 | {"$f12", RTYPE_FPU | 12}, \ | |
2152 | {"$f13", RTYPE_FPU | 13}, \ | |
2153 | {"$f14", RTYPE_FPU | 14}, \ | |
2154 | {"$f15", RTYPE_FPU | 15}, \ | |
2155 | {"$f16", RTYPE_FPU | 16}, \ | |
2156 | {"$f17", RTYPE_FPU | 17}, \ | |
2157 | {"$f18", RTYPE_FPU | 18}, \ | |
2158 | {"$f19", RTYPE_FPU | 19}, \ | |
2159 | {"$f20", RTYPE_FPU | 20}, \ | |
2160 | {"$f21", RTYPE_FPU | 21}, \ | |
2161 | {"$f22", RTYPE_FPU | 22}, \ | |
2162 | {"$f23", RTYPE_FPU | 23}, \ | |
2163 | {"$f24", RTYPE_FPU | 24}, \ | |
2164 | {"$f25", RTYPE_FPU | 25}, \ | |
2165 | {"$f26", RTYPE_FPU | 26}, \ | |
2166 | {"$f27", RTYPE_FPU | 27}, \ | |
2167 | {"$f28", RTYPE_FPU | 28}, \ | |
2168 | {"$f29", RTYPE_FPU | 29}, \ | |
2169 | {"$f30", RTYPE_FPU | 30}, \ | |
2170 | {"$f31", RTYPE_FPU | 31} | |
2171 | ||
2172 | #define FPU_CONDITION_CODE_NAMES \ | |
2173 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2174 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2175 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2176 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2177 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2178 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2179 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2180 | {"$fcc7", RTYPE_FCC | 7} | |
2181 | ||
2182 | #define COPROC_CONDITION_CODE_NAMES \ | |
2183 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2184 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2185 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2186 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2187 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2188 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2189 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2190 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2191 | ||
2192 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2193 | {"$a4", RTYPE_GP | 8}, \ | |
2194 | {"$a5", RTYPE_GP | 9}, \ | |
2195 | {"$a6", RTYPE_GP | 10}, \ | |
2196 | {"$a7", RTYPE_GP | 11}, \ | |
2197 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2198 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2199 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2200 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2201 | {"$t0", RTYPE_GP | 12}, \ | |
2202 | {"$t1", RTYPE_GP | 13}, \ | |
2203 | {"$t2", RTYPE_GP | 14}, \ | |
2204 | {"$t3", RTYPE_GP | 15} | |
2205 | ||
2206 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2207 | {"$t0", RTYPE_GP | 8}, \ | |
2208 | {"$t1", RTYPE_GP | 9}, \ | |
2209 | {"$t2", RTYPE_GP | 10}, \ | |
2210 | {"$t3", RTYPE_GP | 11}, \ | |
2211 | {"$t4", RTYPE_GP | 12}, \ | |
2212 | {"$t5", RTYPE_GP | 13}, \ | |
2213 | {"$t6", RTYPE_GP | 14}, \ | |
2214 | {"$t7", RTYPE_GP | 15}, \ | |
2215 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2216 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2217 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2218 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2219 | ||
2220 | /* Remaining symbolic register names */ | |
2221 | #define SYMBOLIC_REGISTER_NAMES \ | |
2222 | {"$zero", RTYPE_GP | 0}, \ | |
2223 | {"$at", RTYPE_GP | 1}, \ | |
2224 | {"$AT", RTYPE_GP | 1}, \ | |
2225 | {"$v0", RTYPE_GP | 2}, \ | |
2226 | {"$v1", RTYPE_GP | 3}, \ | |
2227 | {"$a0", RTYPE_GP | 4}, \ | |
2228 | {"$a1", RTYPE_GP | 5}, \ | |
2229 | {"$a2", RTYPE_GP | 6}, \ | |
2230 | {"$a3", RTYPE_GP | 7}, \ | |
2231 | {"$s0", RTYPE_GP | 16}, \ | |
2232 | {"$s1", RTYPE_GP | 17}, \ | |
2233 | {"$s2", RTYPE_GP | 18}, \ | |
2234 | {"$s3", RTYPE_GP | 19}, \ | |
2235 | {"$s4", RTYPE_GP | 20}, \ | |
2236 | {"$s5", RTYPE_GP | 21}, \ | |
2237 | {"$s6", RTYPE_GP | 22}, \ | |
2238 | {"$s7", RTYPE_GP | 23}, \ | |
2239 | {"$t8", RTYPE_GP | 24}, \ | |
2240 | {"$t9", RTYPE_GP | 25}, \ | |
2241 | {"$k0", RTYPE_GP | 26}, \ | |
2242 | {"$kt0", RTYPE_GP | 26}, \ | |
2243 | {"$k1", RTYPE_GP | 27}, \ | |
2244 | {"$kt1", RTYPE_GP | 27}, \ | |
2245 | {"$gp", RTYPE_GP | 28}, \ | |
2246 | {"$sp", RTYPE_GP | 29}, \ | |
2247 | {"$s8", RTYPE_GP | 30}, \ | |
2248 | {"$fp", RTYPE_GP | 30}, \ | |
2249 | {"$ra", RTYPE_GP | 31} | |
2250 | ||
2251 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2252 | {"$pc", RTYPE_PC | 0} | |
2253 | ||
2254 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2255 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2256 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2257 | {"$v2", RTYPE_VEC | 2}, \ | |
2258 | {"$v3", RTYPE_VEC | 3}, \ | |
2259 | {"$v4", RTYPE_VEC | 4}, \ | |
2260 | {"$v5", RTYPE_VEC | 5}, \ | |
2261 | {"$v6", RTYPE_VEC | 6}, \ | |
2262 | {"$v7", RTYPE_VEC | 7}, \ | |
2263 | {"$v8", RTYPE_VEC | 8}, \ | |
2264 | {"$v9", RTYPE_VEC | 9}, \ | |
2265 | {"$v10", RTYPE_VEC | 10}, \ | |
2266 | {"$v11", RTYPE_VEC | 11}, \ | |
2267 | {"$v12", RTYPE_VEC | 12}, \ | |
2268 | {"$v13", RTYPE_VEC | 13}, \ | |
2269 | {"$v14", RTYPE_VEC | 14}, \ | |
2270 | {"$v15", RTYPE_VEC | 15}, \ | |
2271 | {"$v16", RTYPE_VEC | 16}, \ | |
2272 | {"$v17", RTYPE_VEC | 17}, \ | |
2273 | {"$v18", RTYPE_VEC | 18}, \ | |
2274 | {"$v19", RTYPE_VEC | 19}, \ | |
2275 | {"$v20", RTYPE_VEC | 20}, \ | |
2276 | {"$v21", RTYPE_VEC | 21}, \ | |
2277 | {"$v22", RTYPE_VEC | 22}, \ | |
2278 | {"$v23", RTYPE_VEC | 23}, \ | |
2279 | {"$v24", RTYPE_VEC | 24}, \ | |
2280 | {"$v25", RTYPE_VEC | 25}, \ | |
2281 | {"$v26", RTYPE_VEC | 26}, \ | |
2282 | {"$v27", RTYPE_VEC | 27}, \ | |
2283 | {"$v28", RTYPE_VEC | 28}, \ | |
2284 | {"$v29", RTYPE_VEC | 29}, \ | |
2285 | {"$v30", RTYPE_VEC | 30}, \ | |
2286 | {"$v31", RTYPE_VEC | 31} | |
2287 | ||
2288 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2289 | {"$ac0", RTYPE_ACC | 0}, \ | |
2290 | {"$ac1", RTYPE_ACC | 1}, \ | |
2291 | {"$ac2", RTYPE_ACC | 2}, \ | |
2292 | {"$ac3", RTYPE_ACC | 3} | |
2293 | ||
2294 | static const struct regname reg_names[] = { | |
2295 | GENERIC_REGISTER_NUMBERS, | |
2296 | FPU_REGISTER_NAMES, | |
2297 | FPU_CONDITION_CODE_NAMES, | |
2298 | COPROC_CONDITION_CODE_NAMES, | |
2299 | ||
2300 | /* The $txx registers depends on the abi, | |
2301 | these will be added later into the symbol table from | |
2302 | one of the tables below once mips_abi is set after | |
2303 | parsing of arguments from the command line. */ | |
2304 | SYMBOLIC_REGISTER_NAMES, | |
2305 | ||
2306 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2307 | MDMX_VECTOR_REGISTER_NAMES, | |
2308 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2309 | {0, 0} | |
2310 | }; | |
2311 | ||
2312 | static const struct regname reg_names_o32[] = { | |
2313 | O32_SYMBOLIC_REGISTER_NAMES, | |
2314 | {0, 0} | |
2315 | }; | |
2316 | ||
2317 | static const struct regname reg_names_n32n64[] = { | |
2318 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2319 | {0, 0} | |
2320 | }; | |
2321 | ||
df58fc94 RS |
2322 | /* Check if S points at a valid register specifier according to TYPES. |
2323 | If so, then return 1, advance S to consume the specifier and store | |
2324 | the register's number in REGNOP, otherwise return 0. */ | |
2325 | ||
707bfff6 TS |
2326 | static int |
2327 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2328 | { | |
2329 | symbolS *symbolP; | |
2330 | char *e; | |
2331 | char save_c; | |
2332 | int reg = -1; | |
2333 | ||
2334 | /* Find end of name. */ | |
2335 | e = *s; | |
2336 | if (is_name_beginner (*e)) | |
2337 | ++e; | |
2338 | while (is_part_of_name (*e)) | |
2339 | ++e; | |
2340 | ||
2341 | /* Terminate name. */ | |
2342 | save_c = *e; | |
2343 | *e = '\0'; | |
2344 | ||
2345 | /* Look for a register symbol. */ | |
2346 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2347 | { | |
2348 | int r = S_GET_VALUE (symbolP); | |
2349 | if (r & types) | |
2350 | reg = r & RNUM_MASK; | |
2351 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2352 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2353 | reg = (r & RNUM_MASK) - 2; | |
2354 | } | |
2355 | /* Else see if this is a register defined in an itbl entry. */ | |
2356 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2357 | { | |
2358 | char *n = *s; | |
2359 | unsigned long r; | |
2360 | ||
2361 | if (*n == '$') | |
2362 | ++n; | |
2363 | if (itbl_get_reg_val (n, &r)) | |
2364 | reg = r & RNUM_MASK; | |
2365 | } | |
2366 | ||
2367 | /* Advance to next token if a register was recognised. */ | |
2368 | if (reg >= 0) | |
2369 | *s = e; | |
2370 | else if (types & RWARN) | |
20203fb9 | 2371 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2372 | |
2373 | *e = save_c; | |
2374 | if (regnop) | |
2375 | *regnop = reg; | |
2376 | return reg >= 0; | |
2377 | } | |
2378 | ||
df58fc94 RS |
2379 | /* Check if S points at a valid register list according to TYPES. |
2380 | If so, then return 1, advance S to consume the list and store | |
2381 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2382 | otherwise return 0. A valid list comprises a comma-separated | |
2383 | enumeration of valid single registers and/or dash-separated | |
2384 | contiguous register ranges as determined by their numbers. | |
2385 | ||
2386 | As a special exception if one of s0-s7 registers is specified as | |
2387 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2388 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2389 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2390 | |
2391 | static int | |
2392 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2393 | { | |
2394 | unsigned int reglist = 0; | |
2395 | unsigned int lastregno; | |
2396 | bfd_boolean ok = TRUE; | |
2397 | unsigned int regmask; | |
2309ddf2 | 2398 | char *s_endlist = *s; |
df58fc94 | 2399 | char *s_reset = *s; |
2309ddf2 | 2400 | unsigned int regno; |
df58fc94 RS |
2401 | |
2402 | while (reg_lookup (s, types, ®no)) | |
2403 | { | |
2404 | lastregno = regno; | |
2405 | if (**s == '-') | |
2406 | { | |
2407 | (*s)++; | |
2408 | ok = reg_lookup (s, types, &lastregno); | |
2409 | if (ok && lastregno < regno) | |
2410 | ok = FALSE; | |
2411 | if (!ok) | |
2412 | break; | |
2413 | } | |
2414 | ||
2415 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2416 | { | |
2417 | lastregno = S7; | |
2418 | reglist |= 1 << FP; | |
2419 | } | |
2420 | regmask = 1 << lastregno; | |
2421 | regmask = (regmask << 1) - 1; | |
2422 | regmask ^= (1 << regno) - 1; | |
2423 | reglist |= regmask; | |
2424 | ||
2309ddf2 | 2425 | s_endlist = *s; |
df58fc94 RS |
2426 | if (**s != ',') |
2427 | break; | |
2428 | (*s)++; | |
2429 | } | |
2430 | ||
2431 | if (ok) | |
2309ddf2 | 2432 | *s = s_endlist; |
df58fc94 RS |
2433 | else |
2434 | *s = s_reset; | |
2435 | if (reglistp) | |
2436 | *reglistp = reglist; | |
2437 | return ok && reglist != 0; | |
2438 | } | |
2439 | ||
d301a56b RS |
2440 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2441 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2442 | |
2443 | static bfd_boolean | |
f79e2745 | 2444 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2445 | { |
2446 | int isa = mips_opts.isa; | |
846ef2d0 | 2447 | int ase = mips_opts.ase; |
037b32b9 AN |
2448 | int fp_s, fp_d; |
2449 | ||
846ef2d0 | 2450 | if ((ase & ASE_DSP) && ISA_SUPPORTS_DSP64_ASE) |
d301a56b | 2451 | ase |= ASE_DSP64; |
846ef2d0 | 2452 | if ((ase & ASE_VIRT) && ISA_SUPPORTS_VIRT64_ASE) |
d301a56b | 2453 | ase |= ASE_VIRT64; |
037b32b9 | 2454 | |
d301a56b | 2455 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2456 | return FALSE; |
2457 | ||
2458 | /* Check whether the instruction or macro requires single-precision or | |
2459 | double-precision floating-point support. Note that this information is | |
2460 | stored differently in the opcode table for insns and macros. */ | |
2461 | if (mo->pinfo == INSN_MACRO) | |
2462 | { | |
2463 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2464 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2465 | } | |
2466 | else | |
2467 | { | |
2468 | fp_s = mo->pinfo & FP_S; | |
2469 | fp_d = mo->pinfo & FP_D; | |
2470 | } | |
2471 | ||
2472 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2473 | return FALSE; | |
2474 | ||
2475 | if (fp_s && mips_opts.soft_float) | |
2476 | return FALSE; | |
2477 | ||
2478 | return TRUE; | |
2479 | } | |
2480 | ||
2481 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2482 | selected ISA and architecture. */ | |
2483 | ||
2484 | static bfd_boolean | |
2485 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2486 | { | |
d301a56b | 2487 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2488 | } |
2489 | ||
df58fc94 RS |
2490 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2491 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2492 | ||
2493 | static bfd_boolean | |
2494 | is_size_valid (const struct mips_opcode *mo) | |
2495 | { | |
2496 | if (!mips_opts.micromips) | |
2497 | return TRUE; | |
2498 | ||
2499 | if (!forced_insn_length) | |
2500 | return TRUE; | |
2501 | if (mo->pinfo == INSN_MACRO) | |
2502 | return FALSE; | |
2503 | return forced_insn_length == micromips_insn_length (mo); | |
2504 | } | |
2505 | ||
2506 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2507 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2508 | ||
2509 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2510 | a macro expansion fails because it relies on a preceding 32-bit real | |
2511 | instruction to have matched and does not handle the operands correctly. | |
2512 | The only macros that may expand to 16-bit instructions are JAL that | |
2513 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2514 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2515 | a NOP. In all these cases the macros precede any corresponding real | |
2516 | instruction definitions in the opcode table, so they will match in the | |
2517 | second pass where the size of the delay slot is ignored and therefore | |
2518 | produce correct code. */ | |
df58fc94 RS |
2519 | |
2520 | static bfd_boolean | |
2521 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2522 | { | |
2523 | if (!mips_opts.micromips) | |
2524 | return TRUE; | |
2525 | ||
2526 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2527 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2528 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2529 | && micromips_insn_length (mo) != 4) | |
2530 | return FALSE; | |
2531 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2532 | && micromips_insn_length (mo) != 2) | |
2533 | return FALSE; | |
2534 | ||
2535 | return TRUE; | |
2536 | } | |
2537 | ||
707bfff6 TS |
2538 | /* This function is called once, at assembler startup time. It should set up |
2539 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2540 | |
252b5132 | 2541 | void |
17a2f251 | 2542 | md_begin (void) |
252b5132 | 2543 | { |
3994f87e | 2544 | const char *retval = NULL; |
156c2f8b | 2545 | int i = 0; |
252b5132 | 2546 | int broken = 0; |
1f25f5d3 | 2547 | |
0a44bf69 RS |
2548 | if (mips_pic != NO_PIC) |
2549 | { | |
2550 | if (g_switch_seen && g_switch_value != 0) | |
2551 | as_bad (_("-G may not be used in position-independent code")); | |
2552 | g_switch_value = 0; | |
2553 | } | |
2554 | ||
fef14a42 | 2555 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2556 | as_warn (_("Could not set architecture and machine")); |
2557 | ||
252b5132 RH |
2558 | op_hash = hash_new (); |
2559 | ||
2560 | for (i = 0; i < NUMOPCODES;) | |
2561 | { | |
2562 | const char *name = mips_opcodes[i].name; | |
2563 | ||
17a2f251 | 2564 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2565 | if (retval != NULL) |
2566 | { | |
2567 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2568 | mips_opcodes[i].name, retval); | |
2569 | /* Probably a memory allocation problem? Give up now. */ | |
2570 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2571 | } | |
2572 | do | |
2573 | { | |
2574 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2575 | { | |
2576 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2577 | broken = 1; | |
1e915849 RS |
2578 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2579 | { | |
2580 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2581 | if (mips_fix_loongson2f_nop) |
2582 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2583 | nop_insn.fixed_p = 1; |
2584 | } | |
252b5132 RH |
2585 | } |
2586 | ++i; | |
2587 | } | |
2588 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2589 | } | |
2590 | ||
2591 | mips16_op_hash = hash_new (); | |
2592 | ||
2593 | i = 0; | |
2594 | while (i < bfd_mips16_num_opcodes) | |
2595 | { | |
2596 | const char *name = mips16_opcodes[i].name; | |
2597 | ||
17a2f251 | 2598 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2599 | if (retval != NULL) |
2600 | as_fatal (_("internal: can't hash `%s': %s"), | |
2601 | mips16_opcodes[i].name, retval); | |
2602 | do | |
2603 | { | |
2604 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2605 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2606 | != mips16_opcodes[i].match)) | |
2607 | { | |
2608 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2609 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2610 | broken = 1; | |
2611 | } | |
1e915849 RS |
2612 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2613 | { | |
2614 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2615 | mips16_nop_insn.fixed_p = 1; | |
2616 | } | |
252b5132 RH |
2617 | ++i; |
2618 | } | |
2619 | while (i < bfd_mips16_num_opcodes | |
2620 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2621 | } | |
2622 | ||
df58fc94 RS |
2623 | micromips_op_hash = hash_new (); |
2624 | ||
2625 | i = 0; | |
2626 | while (i < bfd_micromips_num_opcodes) | |
2627 | { | |
2628 | const char *name = micromips_opcodes[i].name; | |
2629 | ||
2630 | retval = hash_insert (micromips_op_hash, name, | |
2631 | (void *) µmips_opcodes[i]); | |
2632 | if (retval != NULL) | |
2633 | as_fatal (_("internal: can't hash `%s': %s"), | |
2634 | micromips_opcodes[i].name, retval); | |
2635 | do | |
2636 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2637 | { | |
2638 | struct mips_cl_insn *micromips_nop_insn; | |
2639 | ||
2640 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2641 | broken = 1; | |
2642 | ||
2643 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2644 | micromips_nop_insn = µmips_nop16_insn; | |
2645 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2646 | micromips_nop_insn = µmips_nop32_insn; | |
2647 | else | |
2648 | continue; | |
2649 | ||
2650 | if (micromips_nop_insn->insn_mo == NULL | |
2651 | && strcmp (name, "nop") == 0) | |
2652 | { | |
2653 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2654 | micromips_nop_insn->fixed_p = 1; | |
2655 | } | |
2656 | } | |
2657 | while (++i < bfd_micromips_num_opcodes | |
2658 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2659 | } | |
2660 | ||
252b5132 RH |
2661 | if (broken) |
2662 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2663 | ||
2664 | /* We add all the general register names to the symbol table. This | |
2665 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2666 | for (i = 0; reg_names[i].name; i++) |
2667 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2668 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2669 | &zero_address_frag)); |
2670 | if (HAVE_NEWABI) | |
2671 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2672 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2673 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2674 | &zero_address_frag)); |
707bfff6 TS |
2675 | else |
2676 | for (i = 0; reg_names_o32[i].name; i++) | |
2677 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2678 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2679 | &zero_address_frag)); |
6047c971 | 2680 | |
7d10b47d | 2681 | mips_no_prev_insn (); |
252b5132 RH |
2682 | |
2683 | mips_gprmask = 0; | |
2684 | mips_cprmask[0] = 0; | |
2685 | mips_cprmask[1] = 0; | |
2686 | mips_cprmask[2] = 0; | |
2687 | mips_cprmask[3] = 0; | |
2688 | ||
2689 | /* set the default alignment for the text section (2**2) */ | |
2690 | record_alignment (text_section, 2); | |
2691 | ||
4d0d148d | 2692 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2693 | |
707bfff6 | 2694 | #ifdef OBJ_ELF |
f43abd2b | 2695 | if (IS_ELF) |
252b5132 | 2696 | { |
0a44bf69 RS |
2697 | /* On a native system other than VxWorks, sections must be aligned |
2698 | to 16 byte boundaries. When configured for an embedded ELF | |
2699 | target, we don't bother. */ | |
c41e87e3 CF |
2700 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2701 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2702 | { |
2703 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2704 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2705 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2706 | } | |
2707 | ||
2708 | /* Create a .reginfo section for register masks and a .mdebug | |
2709 | section for debugging information. */ | |
2710 | { | |
2711 | segT seg; | |
2712 | subsegT subseg; | |
2713 | flagword flags; | |
2714 | segT sec; | |
2715 | ||
2716 | seg = now_seg; | |
2717 | subseg = now_subseg; | |
2718 | ||
2719 | /* The ABI says this section should be loaded so that the | |
2720 | running program can access it. However, we don't load it | |
2721 | if we are configured for an embedded target */ | |
2722 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2723 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2724 | flags |= SEC_ALLOC | SEC_LOAD; |
2725 | ||
316f5878 | 2726 | if (mips_abi != N64_ABI) |
252b5132 RH |
2727 | { |
2728 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2729 | ||
195325d2 TS |
2730 | bfd_set_section_flags (stdoutput, sec, flags); |
2731 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2732 | |
252b5132 | 2733 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2734 | } |
2735 | else | |
2736 | { | |
2737 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2738 | .reginfo section. */ | |
2739 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2740 | bfd_set_section_flags (stdoutput, sec, flags); |
2741 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2742 | |
252b5132 RH |
2743 | /* Set up the option header. */ |
2744 | { | |
2745 | Elf_Internal_Options opthdr; | |
2746 | char *f; | |
2747 | ||
2748 | opthdr.kind = ODK_REGINFO; | |
2749 | opthdr.size = (sizeof (Elf_External_Options) | |
2750 | + sizeof (Elf64_External_RegInfo)); | |
2751 | opthdr.section = 0; | |
2752 | opthdr.info = 0; | |
2753 | f = frag_more (sizeof (Elf_External_Options)); | |
2754 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2755 | (Elf_External_Options *) f); | |
2756 | ||
2757 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2758 | } | |
252b5132 RH |
2759 | } |
2760 | ||
2761 | if (ECOFF_DEBUGGING) | |
2762 | { | |
2763 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2764 | (void) bfd_set_section_flags (stdoutput, sec, | |
2765 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2766 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2767 | } | |
f43abd2b | 2768 | else if (mips_flag_pdr) |
ecb4347a DJ |
2769 | { |
2770 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2771 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2772 | SEC_READONLY | SEC_RELOC | |
2773 | | SEC_DEBUGGING); | |
2774 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2775 | } | |
252b5132 RH |
2776 | |
2777 | subseg_set (seg, subseg); | |
2778 | } | |
2779 | } | |
707bfff6 | 2780 | #endif /* OBJ_ELF */ |
252b5132 RH |
2781 | |
2782 | if (! ECOFF_DEBUGGING) | |
2783 | md_obj_begin (); | |
71400594 RS |
2784 | |
2785 | if (mips_fix_vr4120) | |
2786 | init_vr4120_conflicts (); | |
252b5132 RH |
2787 | } |
2788 | ||
2789 | void | |
17a2f251 | 2790 | md_mips_end (void) |
252b5132 | 2791 | { |
02b1ab82 | 2792 | mips_emit_delays (); |
252b5132 RH |
2793 | if (! ECOFF_DEBUGGING) |
2794 | md_obj_end (); | |
2795 | } | |
2796 | ||
2797 | void | |
17a2f251 | 2798 | md_assemble (char *str) |
252b5132 RH |
2799 | { |
2800 | struct mips_cl_insn insn; | |
f6688943 TS |
2801 | bfd_reloc_code_real_type unused_reloc[3] |
2802 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2803 | |
2804 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2805 | imm2_expr.X_op = O_absent; |
252b5132 | 2806 | offset_expr.X_op = O_absent; |
f6688943 TS |
2807 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2808 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2809 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2810 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2811 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2812 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2813 | |
e1b47bd5 RS |
2814 | mips_mark_labels (); |
2815 | mips_assembling_insn = TRUE; | |
2816 | ||
252b5132 RH |
2817 | if (mips_opts.mips16) |
2818 | mips16_ip (str, &insn); | |
2819 | else | |
2820 | { | |
2821 | mips_ip (str, &insn); | |
beae10d5 KH |
2822 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2823 | str, insn.insn_opcode)); | |
252b5132 RH |
2824 | } |
2825 | ||
2826 | if (insn_error) | |
e1b47bd5 RS |
2827 | as_bad ("%s `%s'", insn_error, str); |
2828 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2829 | { |
584892a6 | 2830 | macro_start (); |
252b5132 RH |
2831 | if (mips_opts.mips16) |
2832 | mips16_macro (&insn); | |
2833 | else | |
2834 | macro (&insn); | |
584892a6 | 2835 | macro_end (); |
252b5132 RH |
2836 | } |
2837 | else | |
2838 | { | |
2839 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2840 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2841 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2842 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2843 | else |
df58fc94 | 2844 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 2845 | } |
e1b47bd5 RS |
2846 | |
2847 | mips_assembling_insn = FALSE; | |
252b5132 RH |
2848 | } |
2849 | ||
738e5348 RS |
2850 | /* Convenience functions for abstracting away the differences between |
2851 | MIPS16 and non-MIPS16 relocations. */ | |
2852 | ||
2853 | static inline bfd_boolean | |
2854 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2855 | { | |
2856 | switch (reloc) | |
2857 | { | |
2858 | case BFD_RELOC_MIPS16_JMP: | |
2859 | case BFD_RELOC_MIPS16_GPREL: | |
2860 | case BFD_RELOC_MIPS16_GOT16: | |
2861 | case BFD_RELOC_MIPS16_CALL16: | |
2862 | case BFD_RELOC_MIPS16_HI16_S: | |
2863 | case BFD_RELOC_MIPS16_HI16: | |
2864 | case BFD_RELOC_MIPS16_LO16: | |
2865 | return TRUE; | |
2866 | ||
2867 | default: | |
2868 | return FALSE; | |
2869 | } | |
2870 | } | |
2871 | ||
df58fc94 RS |
2872 | static inline bfd_boolean |
2873 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2874 | { | |
2875 | switch (reloc) | |
2876 | { | |
2877 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2878 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2879 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2880 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2881 | case BFD_RELOC_MICROMIPS_JMP: | |
2882 | case BFD_RELOC_MICROMIPS_HI16: | |
2883 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2884 | case BFD_RELOC_MICROMIPS_LO16: | |
2885 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2886 | case BFD_RELOC_MICROMIPS_GOT16: | |
2887 | case BFD_RELOC_MICROMIPS_CALL16: | |
2888 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2889 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2890 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2891 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2892 | case BFD_RELOC_MICROMIPS_SUB: | |
2893 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2894 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2895 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2896 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2897 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2898 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2899 | case BFD_RELOC_MICROMIPS_JALR: | |
2900 | return TRUE; | |
2901 | ||
2902 | default: | |
2903 | return FALSE; | |
2904 | } | |
2905 | } | |
2906 | ||
2309ddf2 MR |
2907 | static inline bfd_boolean |
2908 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2909 | { | |
2910 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2911 | } | |
2912 | ||
738e5348 RS |
2913 | static inline bfd_boolean |
2914 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2915 | { | |
2309ddf2 | 2916 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2917 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2918 | } |
2919 | ||
2920 | static inline bfd_boolean | |
2921 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2922 | { | |
2309ddf2 | 2923 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2924 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2925 | } |
2926 | ||
2927 | static inline bfd_boolean | |
2928 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2929 | { | |
2309ddf2 | 2930 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2931 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2932 | } | |
2933 | ||
df58fc94 RS |
2934 | static inline bfd_boolean |
2935 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2936 | { | |
2309ddf2 | 2937 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2938 | } |
2939 | ||
2de39019 CM |
2940 | /* Return true if RELOC is a PC-relative relocation that does not have |
2941 | full address range. */ | |
2942 | ||
2943 | static inline bfd_boolean | |
2944 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
2945 | { | |
2946 | switch (reloc) | |
2947 | { | |
2948 | case BFD_RELOC_16_PCREL_S2: | |
2949 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2950 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2951 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2952 | return TRUE; | |
2953 | ||
b47468a6 CM |
2954 | case BFD_RELOC_32_PCREL: |
2955 | return HAVE_64BIT_ADDRESSES; | |
2956 | ||
2de39019 CM |
2957 | default: |
2958 | return FALSE; | |
2959 | } | |
2960 | } | |
b47468a6 | 2961 | |
5919d012 | 2962 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2963 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2964 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2965 | |
2966 | static inline bfd_boolean | |
17a2f251 | 2967 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2968 | { |
3b91255e | 2969 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2970 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2971 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2972 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2973 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2974 | } | |
2975 | ||
2976 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2977 | reloc_needs_lo_p. */ | |
2978 | ||
2979 | static inline bfd_reloc_code_real_type | |
2980 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2981 | { | |
df58fc94 RS |
2982 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2983 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2984 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2985 | } |
2986 | ||
2987 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2988 | relocation. */ | |
2989 | ||
2990 | static inline bfd_boolean | |
17a2f251 | 2991 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2992 | { |
2993 | return (fixp->fx_next != NULL | |
738e5348 | 2994 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2995 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2996 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2997 | } | |
2998 | ||
252b5132 RH |
2999 | /* This function returns true if modifying a register requires a |
3000 | delay. */ | |
3001 | ||
3002 | static int | |
17a2f251 | 3003 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
3004 | { |
3005 | unsigned long prev_pinfo; | |
3006 | ||
47e39b9d | 3007 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 3008 | if (! mips_opts.noreorder |
81912461 ILT |
3009 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
3010 | && ! gpr_interlocks) | |
3011 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
3012 | && ! cop_interlocks))) | |
252b5132 | 3013 | { |
81912461 ILT |
3014 | /* A load from a coprocessor or from memory. All load delays |
3015 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 3016 | /* Itbl support may require additional care here. */ |
252b5132 | 3017 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 3018 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
3019 | return 1; |
3020 | } | |
3021 | ||
3022 | return 0; | |
3023 | } | |
3024 | ||
462427c4 RS |
3025 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3026 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3027 | |
3028 | static void | |
462427c4 | 3029 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3030 | { |
3031 | struct insn_label_list *l; | |
3032 | valueT val; | |
3033 | ||
462427c4 | 3034 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3035 | { |
9c2799c2 | 3036 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3037 | symbol_set_frag (l->label, frag_now); |
3038 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3039 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3040 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3041 | ++val; |
3042 | S_SET_VALUE (l->label, val); | |
3043 | } | |
3044 | } | |
3045 | ||
462427c4 RS |
3046 | /* Move all labels in insn_labels to the current insertion point |
3047 | and treat them as text labels. */ | |
3048 | ||
3049 | static void | |
3050 | mips_move_text_labels (void) | |
3051 | { | |
3052 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3053 | } | |
3054 | ||
5f0fe04b TS |
3055 | static bfd_boolean |
3056 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3057 | { | |
3058 | bfd_boolean linkonce = FALSE; | |
3059 | segT symseg = S_GET_SEGMENT (sym); | |
3060 | ||
3061 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3062 | { | |
3063 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3064 | linkonce = TRUE; | |
3065 | #ifdef OBJ_ELF | |
3066 | /* The GNU toolchain uses an extension for ELF: a section | |
3067 | beginning with the magic string .gnu.linkonce is a | |
3068 | linkonce section. */ | |
3069 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3070 | sizeof ".gnu.linkonce" - 1) == 0) | |
3071 | linkonce = TRUE; | |
3072 | #endif | |
3073 | } | |
3074 | return linkonce; | |
3075 | } | |
3076 | ||
e1b47bd5 | 3077 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3078 | linker to handle them specially, such as generating jalx instructions |
3079 | when needed. We also make them odd for the duration of the assembly, | |
3080 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3081 | in the adjust_symtab routine, while leaving them marked. This is |
3082 | convenient for the debugger and the disassembler. The linker knows | |
3083 | to make them odd again. */ | |
3084 | ||
3085 | static void | |
e1b47bd5 | 3086 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3087 | { |
df58fc94 | 3088 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3089 | |
a8dbcb85 | 3090 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) |
e1b47bd5 RS |
3091 | if (IS_ELF) |
3092 | { | |
3093 | if (mips_opts.mips16) | |
3094 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3095 | else | |
3096 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
252b5132 | 3097 | } |
e1b47bd5 RS |
3098 | #endif |
3099 | if ((S_GET_VALUE (label) & 1) == 0 | |
3100 | /* Don't adjust the address if the label is global or weak, or | |
3101 | in a link-once section, since we'll be emitting symbol reloc | |
3102 | references to it which will be patched up by the linker, and | |
3103 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3104 | && !S_IS_WEAK (label) | |
3105 | && !S_IS_EXTERNAL (label) | |
3106 | && !s_is_linkonce (label, now_seg)) | |
3107 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3108 | } | |
3109 | ||
3110 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3111 | ||
3112 | static void | |
3113 | mips_compressed_mark_labels (void) | |
3114 | { | |
3115 | struct insn_label_list *l; | |
3116 | ||
3117 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3118 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3119 | } |
3120 | ||
4d7206a2 RS |
3121 | /* End the current frag. Make it a variant frag and record the |
3122 | relaxation info. */ | |
3123 | ||
3124 | static void | |
3125 | relax_close_frag (void) | |
3126 | { | |
584892a6 | 3127 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3128 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3129 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3130 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3131 | ||
3132 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3133 | mips_relax.first_fixup = 0; | |
3134 | } | |
3135 | ||
3136 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3137 | See the comment above RELAX_ENCODE for more details. */ | |
3138 | ||
3139 | static void | |
3140 | relax_start (symbolS *symbol) | |
3141 | { | |
9c2799c2 | 3142 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3143 | mips_relax.sequence = 1; |
3144 | mips_relax.symbol = symbol; | |
3145 | } | |
3146 | ||
3147 | /* Start generating the second version of a relaxable sequence. | |
3148 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3149 | |
3150 | static void | |
4d7206a2 RS |
3151 | relax_switch (void) |
3152 | { | |
9c2799c2 | 3153 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3154 | mips_relax.sequence = 2; |
3155 | } | |
3156 | ||
3157 | /* End the current relaxable sequence. */ | |
3158 | ||
3159 | static void | |
3160 | relax_end (void) | |
3161 | { | |
9c2799c2 | 3162 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3163 | relax_close_frag (); |
3164 | mips_relax.sequence = 0; | |
3165 | } | |
3166 | ||
11625dd8 RS |
3167 | /* Return true if IP is a delayed branch or jump. */ |
3168 | ||
3169 | static inline bfd_boolean | |
3170 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3171 | { | |
3172 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3173 | | INSN_COND_BRANCH_DELAY | |
3174 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3175 | } | |
3176 | ||
3177 | /* Return true if IP is a compact branch or jump. */ | |
3178 | ||
3179 | static inline bfd_boolean | |
3180 | compact_branch_p (const struct mips_cl_insn *ip) | |
3181 | { | |
3182 | if (mips_opts.mips16) | |
3183 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3184 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3185 | else | |
3186 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3187 | | INSN2_COND_BRANCH)) != 0; | |
3188 | } | |
3189 | ||
3190 | /* Return true if IP is an unconditional branch or jump. */ | |
3191 | ||
3192 | static inline bfd_boolean | |
3193 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3194 | { | |
3195 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3196 | || (mips_opts.mips16 | |
3197 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3198 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3199 | } | |
3200 | ||
3201 | /* Return true if IP is a branch-likely instruction. */ | |
3202 | ||
3203 | static inline bfd_boolean | |
3204 | branch_likely_p (const struct mips_cl_insn *ip) | |
3205 | { | |
3206 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3207 | } | |
3208 | ||
14fe068b RS |
3209 | /* Return the type of nop that should be used to fill the delay slot |
3210 | of delayed branch IP. */ | |
3211 | ||
3212 | static struct mips_cl_insn * | |
3213 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3214 | { | |
3215 | if (mips_opts.micromips | |
3216 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3217 | return µmips_nop32_insn; | |
3218 | return NOP_INSN; | |
3219 | } | |
3220 | ||
2309ddf2 | 3221 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3222 | |
3223 | static unsigned int | |
3224 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3225 | { | |
2309ddf2 | 3226 | unsigned long pinfo2; |
df58fc94 RS |
3227 | unsigned int mask; |
3228 | ||
3229 | mask = 0; | |
df58fc94 RS |
3230 | pinfo2 = ip->insn_mo->pinfo2; |
3231 | if (mips_opts.micromips) | |
3232 | { | |
df58fc94 RS |
3233 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3234 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3235 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3236 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3237 | if (pinfo2 & INSN2_MOD_SP) |
3238 | mask |= 1 << SP; | |
3239 | } | |
3240 | return mask; | |
3241 | } | |
3242 | ||
4c260379 RS |
3243 | /* Return the mask of core registers that IP reads. */ |
3244 | ||
3245 | static unsigned int | |
3246 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3247 | { | |
3248 | unsigned long pinfo, pinfo2; | |
3249 | unsigned int mask; | |
3250 | ||
df58fc94 | 3251 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3252 | pinfo = ip->insn_mo->pinfo; |
3253 | pinfo2 = ip->insn_mo->pinfo2; | |
3254 | if (mips_opts.mips16) | |
3255 | { | |
3256 | if (pinfo & MIPS16_INSN_READ_X) | |
3257 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3258 | if (pinfo & MIPS16_INSN_READ_Y) | |
3259 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3260 | if (pinfo & MIPS16_INSN_READ_T) | |
3261 | mask |= 1 << TREG; | |
3262 | if (pinfo & MIPS16_INSN_READ_SP) | |
3263 | mask |= 1 << SP; | |
3264 | if (pinfo & MIPS16_INSN_READ_31) | |
3265 | mask |= 1 << RA; | |
3266 | if (pinfo & MIPS16_INSN_READ_Z) | |
3267 | mask |= 1 << (mips16_to_32_reg_map | |
3268 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3269 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3270 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3275 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3276 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3277 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3278 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3279 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3280 | if (pinfo2 & INSN2_READ_GP) | |
3281 | mask |= 1 << GP; | |
3282 | if (pinfo2 & INSN2_READ_GPR_31) | |
3283 | mask |= 1 << RA; | |
4c260379 | 3284 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3285 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3286 | } |
2b0c8b40 MR |
3287 | if (mips_opts.micromips) |
3288 | { | |
3289 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3290 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3291 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3292 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3293 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3294 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3295 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3296 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3297 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3298 | { | |
3299 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3300 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3301 | } | |
3302 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3303 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3304 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3305 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3306 | } | |
fe35f09f RS |
3307 | /* Don't include register 0. */ |
3308 | return mask & ~1; | |
4c260379 RS |
3309 | } |
3310 | ||
3311 | /* Return the mask of core registers that IP writes. */ | |
3312 | ||
3313 | static unsigned int | |
3314 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3315 | { | |
3316 | unsigned long pinfo, pinfo2; | |
3317 | unsigned int mask; | |
3318 | ||
df58fc94 | 3319 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3320 | pinfo = ip->insn_mo->pinfo; |
3321 | pinfo2 = ip->insn_mo->pinfo2; | |
3322 | if (mips_opts.mips16) | |
3323 | { | |
3324 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3325 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3326 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3327 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3328 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3329 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3330 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3331 | mask |= 1 << TREG; | |
3332 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3333 | mask |= 1 << SP; | |
3334 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3335 | mask |= 1 << RA; | |
3336 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3337 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3338 | } | |
3339 | else | |
3340 | { | |
3341 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3342 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3343 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3344 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3345 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3346 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3347 | if (pinfo & INSN_WRITE_GPR_31) |
3348 | mask |= 1 << RA; | |
3349 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3350 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3351 | } |
2b0c8b40 MR |
3352 | if (mips_opts.micromips) |
3353 | { | |
3354 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3355 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3356 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3357 | { | |
3358 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3359 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3360 | } | |
3361 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3362 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3363 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3364 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3365 | } | |
fe35f09f RS |
3366 | /* Don't include register 0. */ |
3367 | return mask & ~1; | |
4c260379 RS |
3368 | } |
3369 | ||
3370 | /* Return the mask of floating-point registers that IP reads. */ | |
3371 | ||
3372 | static unsigned int | |
3373 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3374 | { | |
3375 | unsigned long pinfo, pinfo2; | |
3376 | unsigned int mask; | |
3377 | ||
3378 | mask = 0; | |
3379 | pinfo = ip->insn_mo->pinfo; | |
3380 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3381 | if (!mips_opts.mips16) |
df58fc94 RS |
3382 | { |
3383 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3384 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3385 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3386 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3387 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3388 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3389 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3390 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3391 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3392 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3393 | } |
3394 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3395 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3396 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3397 | mask |= mask << 1; | |
3398 | return mask; | |
3399 | } | |
3400 | ||
3401 | /* Return the mask of floating-point registers that IP writes. */ | |
3402 | ||
3403 | static unsigned int | |
3404 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3405 | { | |
3406 | unsigned long pinfo, pinfo2; | |
3407 | unsigned int mask; | |
3408 | ||
3409 | mask = 0; | |
3410 | pinfo = ip->insn_mo->pinfo; | |
3411 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3412 | if (!mips_opts.mips16) |
4c260379 RS |
3413 | { |
3414 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3415 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3416 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3417 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3418 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3419 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3420 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3421 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3422 | } |
3423 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3424 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3425 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3426 | mask |= mask << 1; | |
3427 | return mask; | |
3428 | } | |
3429 | ||
71400594 RS |
3430 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3431 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3432 | by VR4120 errata. */ | |
4d7206a2 | 3433 | |
71400594 RS |
3434 | static unsigned int |
3435 | classify_vr4120_insn (const char *name) | |
252b5132 | 3436 | { |
71400594 RS |
3437 | if (strncmp (name, "macc", 4) == 0) |
3438 | return FIX_VR4120_MACC; | |
3439 | if (strncmp (name, "dmacc", 5) == 0) | |
3440 | return FIX_VR4120_DMACC; | |
3441 | if (strncmp (name, "mult", 4) == 0) | |
3442 | return FIX_VR4120_MULT; | |
3443 | if (strncmp (name, "dmult", 5) == 0) | |
3444 | return FIX_VR4120_DMULT; | |
3445 | if (strstr (name, "div")) | |
3446 | return FIX_VR4120_DIV; | |
3447 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3448 | return FIX_VR4120_MTHILO; | |
3449 | return NUM_FIX_VR4120_CLASSES; | |
3450 | } | |
252b5132 | 3451 | |
ff239038 CM |
3452 | #define INSN_ERET 0x42000018 |
3453 | #define INSN_DERET 0x4200001f | |
3454 | ||
71400594 RS |
3455 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3456 | where INSN1 is the earlier instruction. Return the worst-case value | |
3457 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3458 | |
71400594 RS |
3459 | static unsigned int |
3460 | insns_between (const struct mips_cl_insn *insn1, | |
3461 | const struct mips_cl_insn *insn2) | |
3462 | { | |
3463 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3464 | unsigned int mask; |
71400594 RS |
3465 | |
3466 | /* This function needs to know which pinfo flags are set for INSN2 | |
3467 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3468 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3469 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3470 | pinfo1 = insn1->insn_mo->pinfo; |
3471 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3472 | |
4c260379 RS |
3473 | #define INSN2_USES_GPR(REG) \ |
3474 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3475 | |
3476 | /* For most targets, write-after-read dependencies on the HI and LO | |
3477 | registers must be separated by at least two instructions. */ | |
3478 | if (!hilo_interlocks) | |
252b5132 | 3479 | { |
71400594 RS |
3480 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3481 | return 2; | |
3482 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3483 | return 2; | |
3484 | } | |
3485 | ||
3486 | /* If we're working around r7000 errata, there must be two instructions | |
3487 | between an mfhi or mflo and any instruction that uses the result. */ | |
3488 | if (mips_7000_hilo_fix | |
df58fc94 | 3489 | && !mips_opts.micromips |
71400594 | 3490 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3491 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3492 | return 2; |
3493 | ||
ff239038 CM |
3494 | /* If we're working around 24K errata, one instruction is required |
3495 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3496 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3497 | { |
3498 | if (insn1->insn_opcode == INSN_ERET | |
3499 | || insn1->insn_opcode == INSN_DERET) | |
3500 | { | |
3501 | if (insn2 == NULL | |
3502 | || insn2->insn_opcode == INSN_ERET | |
3503 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3504 | || delayed_branch_p (insn2)) |
ff239038 CM |
3505 | return 1; |
3506 | } | |
3507 | } | |
3508 | ||
71400594 RS |
3509 | /* If working around VR4120 errata, check for combinations that need |
3510 | a single intervening instruction. */ | |
df58fc94 | 3511 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3512 | { |
3513 | unsigned int class1, class2; | |
252b5132 | 3514 | |
71400594 RS |
3515 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3516 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3517 | { |
71400594 RS |
3518 | if (insn2 == NULL) |
3519 | return 1; | |
3520 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3521 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3522 | return 1; | |
252b5132 | 3523 | } |
71400594 RS |
3524 | } |
3525 | ||
df58fc94 | 3526 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3527 | { |
3528 | /* Check for GPR or coprocessor load delays. All such delays | |
3529 | are on the RT register. */ | |
3530 | /* Itbl support may require additional care here. */ | |
3531 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3532 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3533 | { |
71400594 | 3534 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3535 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3536 | return 1; |
3537 | } | |
3538 | ||
3539 | /* Check for generic coprocessor hazards. | |
3540 | ||
3541 | This case is not handled very well. There is no special | |
3542 | knowledge of CP0 handling, and the coprocessors other than | |
3543 | the floating point unit are not distinguished at all. */ | |
3544 | /* Itbl support may require additional care here. FIXME! | |
3545 | Need to modify this to include knowledge about | |
3546 | user specified delays! */ | |
3547 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3548 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3549 | { | |
3550 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3551 | register. There must be a one instruction delay before INSN2 | |
3552 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3553 | mask = fpr_write_mask (insn1); |
3554 | if (mask != 0) | |
252b5132 | 3555 | { |
4c260379 | 3556 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3557 | return 1; |
252b5132 RH |
3558 | } |
3559 | else | |
3560 | { | |
71400594 RS |
3561 | /* Read-after-write dependencies on the control registers |
3562 | require a two-instruction gap. */ | |
3563 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3564 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3565 | return 2; | |
3566 | ||
3567 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3568 | also a coprocessor instruction, assume there must be | |
3569 | a one instruction gap. */ | |
3570 | if (pinfo2 & INSN_COP) | |
3571 | return 1; | |
252b5132 RH |
3572 | } |
3573 | } | |
6b76fefe | 3574 | |
71400594 RS |
3575 | /* Check for read-after-write dependencies on the coprocessor |
3576 | control registers in cases where INSN1 does not need a general | |
3577 | coprocessor delay. This means that INSN1 is a floating point | |
3578 | comparison instruction. */ | |
3579 | /* Itbl support may require additional care here. */ | |
3580 | else if (!cop_interlocks | |
3581 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3582 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3583 | return 1; | |
3584 | } | |
6b76fefe | 3585 | |
4c260379 | 3586 | #undef INSN2_USES_GPR |
6b76fefe | 3587 | |
71400594 RS |
3588 | return 0; |
3589 | } | |
6b76fefe | 3590 | |
7d8e00cf RS |
3591 | /* Return the number of nops that would be needed to work around the |
3592 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3593 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3594 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3595 | |
3596 | static int | |
932d1a1b | 3597 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3598 | const struct mips_cl_insn *insn) |
3599 | { | |
4c260379 RS |
3600 | int i, j; |
3601 | unsigned int mask; | |
7d8e00cf RS |
3602 | |
3603 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3604 | are not affected by the errata. */ | |
3605 | if (insn != 0 | |
3606 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3607 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3608 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3609 | return 0; | |
3610 | ||
3611 | /* Search for the first MFLO or MFHI. */ | |
3612 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3613 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3614 | { |
3615 | /* Extract the destination register. */ | |
4c260379 | 3616 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3617 | |
3618 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3619 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3620 | return 0; |
3621 | ||
3622 | /* ...or if any of the intervening instructions do. */ | |
3623 | for (j = 0; j < i; j++) | |
4c260379 | 3624 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3625 | return 0; |
3626 | ||
932d1a1b RS |
3627 | if (i >= ignore) |
3628 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3629 | } |
3630 | return 0; | |
3631 | } | |
3632 | ||
15be625d CM |
3633 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3634 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3635 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3636 | ||
3637 | /* Return the minimum alignment for this store instruction. */ | |
3638 | ||
3639 | static int | |
3640 | fix_24k_align_to (const struct mips_opcode *mo) | |
3641 | { | |
3642 | if (strcmp (mo->name, "sh") == 0) | |
3643 | return 2; | |
3644 | ||
3645 | if (strcmp (mo->name, "swc1") == 0 | |
3646 | || strcmp (mo->name, "swc2") == 0 | |
3647 | || strcmp (mo->name, "sw") == 0 | |
3648 | || strcmp (mo->name, "sc") == 0 | |
3649 | || strcmp (mo->name, "s.s") == 0) | |
3650 | return 4; | |
3651 | ||
3652 | if (strcmp (mo->name, "sdc1") == 0 | |
3653 | || strcmp (mo->name, "sdc2") == 0 | |
3654 | || strcmp (mo->name, "s.d") == 0) | |
3655 | return 8; | |
3656 | ||
3657 | /* sb, swl, swr */ | |
3658 | return 1; | |
3659 | } | |
3660 | ||
3661 | struct fix_24k_store_info | |
3662 | { | |
3663 | /* Immediate offset, if any, for this store instruction. */ | |
3664 | short off; | |
3665 | /* Alignment required by this store instruction. */ | |
3666 | int align_to; | |
3667 | /* True for register offsets. */ | |
3668 | int register_offset; | |
3669 | }; | |
3670 | ||
3671 | /* Comparison function used by qsort. */ | |
3672 | ||
3673 | static int | |
3674 | fix_24k_sort (const void *a, const void *b) | |
3675 | { | |
3676 | const struct fix_24k_store_info *pos1 = a; | |
3677 | const struct fix_24k_store_info *pos2 = b; | |
3678 | ||
3679 | return (pos1->off - pos2->off); | |
3680 | } | |
3681 | ||
3682 | /* INSN is a store instruction. Try to record the store information | |
3683 | in STINFO. Return false if the information isn't known. */ | |
3684 | ||
3685 | static bfd_boolean | |
3686 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3687 | const struct mips_cl_insn *insn) |
15be625d CM |
3688 | { |
3689 | /* The instruction must have a known offset. */ | |
3690 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3691 | return FALSE; | |
3692 | ||
3693 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3694 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3695 | return TRUE; | |
3696 | } | |
3697 | ||
932d1a1b RS |
3698 | /* Return the number of nops that would be needed to work around the 24k |
3699 | "lost data on stores during refill" errata if instruction INSN | |
3700 | immediately followed the 2 instructions described by HIST. | |
3701 | Ignore hazards that are contained within the first IGNORE | |
3702 | instructions of HIST. | |
3703 | ||
3704 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3705 | for the data cache refills and store data. The following describes | |
3706 | the scenario where the store data could be lost. | |
3707 | ||
3708 | * A data cache miss, due to either a load or a store, causing fill | |
3709 | data to be supplied by the memory subsystem | |
3710 | * The first three doublewords of fill data are returned and written | |
3711 | into the cache | |
3712 | * A sequence of four stores occurs in consecutive cycles around the | |
3713 | final doubleword of the fill: | |
3714 | * Store A | |
3715 | * Store B | |
3716 | * Store C | |
3717 | * Zero, One or more instructions | |
3718 | * Store D | |
3719 | ||
3720 | The four stores A-D must be to different doublewords of the line that | |
3721 | is being filled. The fourth instruction in the sequence above permits | |
3722 | the fill of the final doubleword to be transferred from the FSB into | |
3723 | the cache. In the sequence above, the stores may be either integer | |
3724 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3725 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3726 | different doublewords on the line. If the floating point unit is | |
3727 | running in 1:2 mode, it is not possible to create the sequence above | |
3728 | using only floating point store instructions. | |
15be625d CM |
3729 | |
3730 | In this case, the cache line being filled is incorrectly marked | |
3731 | invalid, thereby losing the data from any store to the line that | |
3732 | occurs between the original miss and the completion of the five | |
3733 | cycle sequence shown above. | |
3734 | ||
932d1a1b | 3735 | The workarounds are: |
15be625d | 3736 | |
932d1a1b RS |
3737 | * Run the data cache in write-through mode. |
3738 | * Insert a non-store instruction between | |
3739 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3740 | |
3741 | static int | |
932d1a1b | 3742 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3743 | const struct mips_cl_insn *insn) |
3744 | { | |
3745 | struct fix_24k_store_info pos[3]; | |
3746 | int align, i, base_offset; | |
3747 | ||
932d1a1b RS |
3748 | if (ignore >= 2) |
3749 | return 0; | |
3750 | ||
ab9794cf RS |
3751 | /* If the previous instruction wasn't a store, there's nothing to |
3752 | worry about. */ | |
15be625d CM |
3753 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3754 | return 0; | |
3755 | ||
ab9794cf RS |
3756 | /* If the instructions after the previous one are unknown, we have |
3757 | to assume the worst. */ | |
3758 | if (!insn) | |
15be625d CM |
3759 | return 1; |
3760 | ||
ab9794cf RS |
3761 | /* Check whether we are dealing with three consecutive stores. */ |
3762 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3763 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3764 | return 0; |
3765 | ||
3766 | /* If we don't know the relationship between the store addresses, | |
3767 | assume the worst. */ | |
ab9794cf | 3768 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3769 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3770 | return 1; | |
3771 | ||
3772 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3773 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3774 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3775 | return 1; | |
3776 | ||
3777 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3778 | ||
3779 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3780 | X bytes and such that the base register + X is known to be aligned | |
3781 | to align bytes. */ | |
3782 | ||
3783 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3784 | align = 8; | |
3785 | else | |
3786 | { | |
3787 | align = pos[0].align_to; | |
3788 | base_offset = pos[0].off; | |
3789 | for (i = 1; i < 3; i++) | |
3790 | if (align < pos[i].align_to) | |
3791 | { | |
3792 | align = pos[i].align_to; | |
3793 | base_offset = pos[i].off; | |
3794 | } | |
3795 | for (i = 0; i < 3; i++) | |
3796 | pos[i].off -= base_offset; | |
3797 | } | |
3798 | ||
3799 | pos[0].off &= ~align + 1; | |
3800 | pos[1].off &= ~align + 1; | |
3801 | pos[2].off &= ~align + 1; | |
3802 | ||
3803 | /* If any two stores write to the same chunk, they also write to the | |
3804 | same doubleword. The offsets are still sorted at this point. */ | |
3805 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3806 | return 0; | |
3807 | ||
3808 | /* A range of at least 9 bytes is needed for the stores to be in | |
3809 | non-overlapping doublewords. */ | |
3810 | if (pos[2].off - pos[0].off <= 8) | |
3811 | return 0; | |
3812 | ||
3813 | if (pos[2].off - pos[1].off >= 24 | |
3814 | || pos[1].off - pos[0].off >= 24 | |
3815 | || pos[2].off - pos[0].off >= 32) | |
3816 | return 0; | |
3817 | ||
3818 | return 1; | |
3819 | } | |
3820 | ||
71400594 | 3821 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3822 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3823 | where HIST[0] is the most recent instruction. Ignore hazards |
3824 | between INSN and the first IGNORE instructions in HIST. | |
3825 | ||
3826 | If INSN is null, return the worse-case number of nops for any | |
3827 | instruction. */ | |
bdaaa2e1 | 3828 | |
71400594 | 3829 | static int |
932d1a1b | 3830 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3831 | const struct mips_cl_insn *insn) |
3832 | { | |
3833 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3834 | |
71400594 | 3835 | nops = 0; |
932d1a1b | 3836 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3837 | { |
91d6fa6a | 3838 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3839 | if (tmp_nops > nops) |
3840 | nops = tmp_nops; | |
3841 | } | |
7d8e00cf | 3842 | |
df58fc94 | 3843 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3844 | { |
932d1a1b | 3845 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3846 | if (tmp_nops > nops) |
3847 | nops = tmp_nops; | |
3848 | } | |
3849 | ||
df58fc94 | 3850 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3851 | { |
932d1a1b | 3852 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3853 | if (tmp_nops > nops) |
3854 | nops = tmp_nops; | |
3855 | } | |
3856 | ||
71400594 RS |
3857 | return nops; |
3858 | } | |
252b5132 | 3859 | |
71400594 | 3860 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3861 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3862 | would be needed after the extended sequence, ignoring hazards |
3863 | in the first IGNORE instructions. */ | |
252b5132 | 3864 | |
71400594 | 3865 | static int |
932d1a1b RS |
3866 | nops_for_sequence (int num_insns, int ignore, |
3867 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3868 | { |
3869 | va_list args; | |
3870 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3871 | struct mips_cl_insn *cursor; | |
3872 | int nops; | |
3873 | ||
91d6fa6a | 3874 | va_start (args, hist); |
71400594 | 3875 | cursor = buffer + num_insns; |
91d6fa6a | 3876 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3877 | while (cursor > buffer) |
3878 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3879 | ||
932d1a1b | 3880 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3881 | va_end (args); |
3882 | return nops; | |
3883 | } | |
252b5132 | 3884 | |
71400594 RS |
3885 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3886 | worst-case delay for the branch target. */ | |
252b5132 | 3887 | |
71400594 | 3888 | static int |
932d1a1b | 3889 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3890 | const struct mips_cl_insn *insn) |
3891 | { | |
3892 | int nops, tmp_nops; | |
60b63b72 | 3893 | |
932d1a1b | 3894 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3895 | if (delayed_branch_p (insn)) |
71400594 | 3896 | { |
932d1a1b | 3897 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3898 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3899 | if (tmp_nops > nops) |
3900 | nops = tmp_nops; | |
3901 | } | |
11625dd8 | 3902 | else if (compact_branch_p (insn)) |
71400594 | 3903 | { |
932d1a1b | 3904 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3905 | if (tmp_nops > nops) |
3906 | nops = tmp_nops; | |
3907 | } | |
3908 | return nops; | |
3909 | } | |
3910 | ||
c67a084a NC |
3911 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3912 | ||
3913 | static void | |
3914 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3915 | { | |
df58fc94 | 3916 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3917 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3918 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3919 | } | |
3920 | ||
3921 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3922 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3923 | ||
3924 | static void | |
3925 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3926 | { | |
df58fc94 | 3927 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3928 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3929 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3930 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3931 | { | |
3932 | int sreg; | |
3933 | expressionS ep; | |
3934 | ||
3935 | if (! mips_opts.at) | |
3936 | return; | |
3937 | ||
df58fc94 | 3938 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3939 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3940 | return; | |
3941 | ||
3942 | ep.X_op = O_constant; | |
3943 | ep.X_add_number = 0xcfff0000; | |
3944 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3945 | ep.X_add_number = 0xffff; | |
3946 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3947 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3948 | } | |
3949 | } | |
3950 | ||
3951 | static void | |
3952 | fix_loongson2f (struct mips_cl_insn * ip) | |
3953 | { | |
3954 | if (mips_fix_loongson2f_nop) | |
3955 | fix_loongson2f_nop (ip); | |
3956 | ||
3957 | if (mips_fix_loongson2f_jump) | |
3958 | fix_loongson2f_jump (ip); | |
3959 | } | |
3960 | ||
a4e06468 RS |
3961 | /* IP is a branch that has a delay slot, and we need to fill it |
3962 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
3963 | with the previous instruction. |
3964 | ADDRESS_EXPR is an operand of the instruction to be used with | |
3965 | RELOC_TYPE. */ | |
a4e06468 RS |
3966 | |
3967 | static bfd_boolean | |
e407c74b NC |
3968 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
3969 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 3970 | { |
2b0c8b40 | 3971 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3972 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3973 | ||
3974 | /* -O2 and above is required for this optimization. */ | |
3975 | if (mips_optimize < 2) | |
3976 | return FALSE; | |
3977 | ||
3978 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3979 | if (mips_opts.nomove) | |
3980 | return FALSE; | |
3981 | ||
3982 | /* We can't swap if the previous instruction's position is fixed. */ | |
3983 | if (history[0].fixed_p) | |
3984 | return FALSE; | |
3985 | ||
3986 | /* If the previous previous insn was in a .set noreorder, we can't | |
3987 | swap. Actually, the MIPS assembler will swap in this situation. | |
3988 | However, gcc configured -with-gnu-as will generate code like | |
3989 | ||
3990 | .set noreorder | |
3991 | lw $4,XXX | |
3992 | .set reorder | |
3993 | INSN | |
3994 | bne $4,$0,foo | |
3995 | ||
3996 | in which we can not swap the bne and INSN. If gcc is not configured | |
3997 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3998 | if (history[1].noreorder_p) | |
3999 | return FALSE; | |
4000 | ||
87333bb7 MR |
4001 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
4002 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
4003 | if (mips_opts.mips16 && history[0].fixp[0]) |
4004 | return FALSE; | |
4005 | ||
4006 | /* If the branch is itself the target of a branch, we can not swap. | |
4007 | We cheat on this; all we check for is whether there is a label on | |
4008 | this instruction. If there are any branches to anything other than | |
4009 | a label, users must use .set noreorder. */ | |
4010 | if (seg_info (now_seg)->label_list) | |
4011 | return FALSE; | |
4012 | ||
4013 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 4014 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
4015 | MIPS16 code, which uses variant frags for different purposes. */ |
4016 | if (!mips_opts.mips16 | |
a4e06468 RS |
4017 | && history[0].frag |
4018 | && history[0].frag->fr_type == rs_machine_dependent) | |
4019 | return FALSE; | |
4020 | ||
bcd530a7 RS |
4021 | /* We do not swap with instructions that cannot architecturally |
4022 | be placed in a branch delay slot, such as SYNC or ERET. We | |
4023 | also refrain from swapping with a trap instruction, since it | |
4024 | complicates trap handlers to have the trap instruction be in | |
4025 | a delay slot. */ | |
a4e06468 | 4026 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 4027 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
4028 | return FALSE; |
4029 | ||
4030 | /* Check for conflicts between the branch and the instructions | |
4031 | before the candidate delay slot. */ | |
4032 | if (nops_for_insn (0, history + 1, ip) > 0) | |
4033 | return FALSE; | |
4034 | ||
4035 | /* Check for conflicts between the swapped sequence and the | |
4036 | target of the branch. */ | |
4037 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
4038 | return FALSE; | |
4039 | ||
4040 | /* If the branch reads a register that the previous | |
4041 | instruction sets, we can not swap. */ | |
4042 | gpr_read = gpr_read_mask (ip); | |
4043 | prev_gpr_write = gpr_write_mask (&history[0]); | |
4044 | if (gpr_read & prev_gpr_write) | |
4045 | return FALSE; | |
4046 | ||
4047 | /* If the branch writes a register that the previous | |
4048 | instruction sets, we can not swap. */ | |
4049 | gpr_write = gpr_write_mask (ip); | |
4050 | if (gpr_write & prev_gpr_write) | |
4051 | return FALSE; | |
4052 | ||
4053 | /* If the branch writes a register that the previous | |
4054 | instruction reads, we can not swap. */ | |
4055 | prev_gpr_read = gpr_read_mask (&history[0]); | |
4056 | if (gpr_write & prev_gpr_read) | |
4057 | return FALSE; | |
4058 | ||
4059 | /* If one instruction sets a condition code and the | |
4060 | other one uses a condition code, we can not swap. */ | |
4061 | pinfo = ip->insn_mo->pinfo; | |
4062 | if ((pinfo & INSN_READ_COND_CODE) | |
4063 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
4064 | return FALSE; | |
4065 | if ((pinfo & INSN_WRITE_COND_CODE) | |
4066 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
4067 | return FALSE; | |
4068 | ||
4069 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 4070 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
4071 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
4072 | return FALSE; | |
2b0c8b40 MR |
4073 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
4074 | return FALSE; | |
a4e06468 | 4075 | |
df58fc94 RS |
4076 | /* If the previous instruction has an incorrect size for a fixed |
4077 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
4078 | pinfo2 = ip->insn_mo->pinfo2; |
4079 | if (mips_opts.micromips | |
4080 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
4081 | && insn_length (history) != 2) | |
4082 | return FALSE; | |
4083 | if (mips_opts.micromips | |
4084 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
4085 | && insn_length (history) != 4) | |
4086 | return FALSE; | |
4087 | ||
e407c74b NC |
4088 | /* On R5900 short loops need to be fixed by inserting a nop in |
4089 | the branch delay slots. | |
4090 | A short loop can be terminated too early. */ | |
4091 | if (mips_opts.arch == CPU_R5900 | |
4092 | /* Check if instruction has a parameter, ignore "j $31". */ | |
4093 | && (address_expr != NULL) | |
4094 | /* Parameter must be 16 bit. */ | |
4095 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
4096 | /* Branch to same segment. */ | |
4097 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
4098 | /* Branch to same code fragment. */ | |
4099 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
4100 | /* Can only calculate branch offset if value is known. */ | |
4101 | && symbol_constant_p(address_expr->X_add_symbol) | |
4102 | /* Check if branch is really conditional. */ | |
4103 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
4104 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
4105 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
4106 | { | |
4107 | int distance; | |
4108 | /* Check if loop is shorter than 6 instructions including | |
4109 | branch and delay slot. */ | |
4110 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
4111 | if (distance <= 20) | |
4112 | { | |
4113 | int i; | |
4114 | int rv; | |
4115 | ||
4116 | rv = FALSE; | |
4117 | /* When the loop includes branches or jumps, | |
4118 | it is not a short loop. */ | |
4119 | for (i = 0; i < (distance / 4); i++) | |
4120 | { | |
4121 | if ((history[i].cleared_p) | |
4122 | || delayed_branch_p(&history[i])) | |
4123 | { | |
4124 | rv = TRUE; | |
4125 | break; | |
4126 | } | |
4127 | } | |
4128 | if (rv == FALSE) | |
4129 | { | |
4130 | /* Insert nop after branch to fix short loop. */ | |
4131 | return FALSE; | |
4132 | } | |
4133 | } | |
4134 | } | |
4135 | ||
a4e06468 RS |
4136 | return TRUE; |
4137 | } | |
4138 | ||
e407c74b NC |
4139 | /* Decide how we should add IP to the instruction stream. |
4140 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4141 | RELOC_TYPE. */ | |
a4e06468 RS |
4142 | |
4143 | static enum append_method | |
e407c74b NC |
4144 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
4145 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
4146 | { |
4147 | unsigned long pinfo; | |
4148 | ||
4149 | /* The relaxed version of a macro sequence must be inherently | |
4150 | hazard-free. */ | |
4151 | if (mips_relax.sequence == 2) | |
4152 | return APPEND_ADD; | |
4153 | ||
4154 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4155 | if (mips_opts.noreorder) | |
4156 | return APPEND_ADD; | |
4157 | ||
4158 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4159 | if (delayed_branch_p (ip)) |
a4e06468 | 4160 | { |
e407c74b NC |
4161 | if (!branch_likely_p (ip) |
4162 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4163 | return APPEND_SWAP; |
4164 | ||
11625dd8 | 4165 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4166 | if (mips_opts.mips16 |
4167 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4168 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4169 | return APPEND_ADD_COMPACT; | |
4170 | ||
4171 | return APPEND_ADD_WITH_NOP; | |
4172 | } | |
4173 | ||
a4e06468 RS |
4174 | return APPEND_ADD; |
4175 | } | |
4176 | ||
ceb94aa5 RS |
4177 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4178 | Point IP->insn_mo to the new opcode's definition. */ | |
4179 | ||
4180 | static void | |
4181 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4182 | { | |
4183 | const struct mips_opcode *mo, *end; | |
4184 | ||
4185 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4186 | for (mo = ip->insn_mo; mo < end; mo++) | |
4187 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4188 | { | |
4189 | ip->insn_mo = mo; | |
4190 | return; | |
4191 | } | |
4192 | abort (); | |
4193 | } | |
4194 | ||
df58fc94 RS |
4195 | /* For microMIPS macros, we need to generate a local number label |
4196 | as the target of branches. */ | |
4197 | #define MICROMIPS_LABEL_CHAR '\037' | |
4198 | static unsigned long micromips_target_label; | |
4199 | static char micromips_target_name[32]; | |
4200 | ||
4201 | static char * | |
4202 | micromips_label_name (void) | |
4203 | { | |
4204 | char *p = micromips_target_name; | |
4205 | char symbol_name_temporary[24]; | |
4206 | unsigned long l; | |
4207 | int i; | |
4208 | ||
4209 | if (*p) | |
4210 | return p; | |
4211 | ||
4212 | i = 0; | |
4213 | l = micromips_target_label; | |
4214 | #ifdef LOCAL_LABEL_PREFIX | |
4215 | *p++ = LOCAL_LABEL_PREFIX; | |
4216 | #endif | |
4217 | *p++ = 'L'; | |
4218 | *p++ = MICROMIPS_LABEL_CHAR; | |
4219 | do | |
4220 | { | |
4221 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4222 | l /= 10; | |
4223 | } | |
4224 | while (l != 0); | |
4225 | while (i > 0) | |
4226 | *p++ = symbol_name_temporary[--i]; | |
4227 | *p = '\0'; | |
4228 | ||
4229 | return micromips_target_name; | |
4230 | } | |
4231 | ||
4232 | static void | |
4233 | micromips_label_expr (expressionS *label_expr) | |
4234 | { | |
4235 | label_expr->X_op = O_symbol; | |
4236 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4237 | label_expr->X_add_number = 0; | |
4238 | } | |
4239 | ||
4240 | static void | |
4241 | micromips_label_inc (void) | |
4242 | { | |
4243 | micromips_target_label++; | |
4244 | *micromips_target_name = '\0'; | |
4245 | } | |
4246 | ||
4247 | static void | |
4248 | micromips_add_label (void) | |
4249 | { | |
4250 | symbolS *s; | |
4251 | ||
4252 | s = colon (micromips_label_name ()); | |
4253 | micromips_label_inc (); | |
4254 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
4255 | if (IS_ELF) | |
4256 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
4257 | #else |
4258 | (void) s; | |
df58fc94 RS |
4259 | #endif |
4260 | } | |
4261 | ||
4262 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4263 | corresponding to the requested one if any. Otherwise return | |
4264 | the reloc unchanged. */ | |
4265 | ||
4266 | static bfd_reloc_code_real_type | |
4267 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4268 | { | |
4269 | static const bfd_reloc_code_real_type relocs[][2] = | |
4270 | { | |
4271 | /* Keep sorted incrementally by the left-hand key. */ | |
4272 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4273 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4274 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4275 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4276 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4277 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4278 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4279 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4280 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4281 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4282 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4283 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4284 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4285 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4286 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4287 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4288 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4289 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4290 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4291 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4292 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4293 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4294 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4295 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4296 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4297 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4298 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4299 | }; | |
4300 | bfd_reloc_code_real_type r; | |
4301 | size_t i; | |
4302 | ||
4303 | if (!mips_opts.micromips) | |
4304 | return reloc; | |
4305 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4306 | { | |
4307 | r = relocs[i][0]; | |
4308 | if (r > reloc) | |
4309 | return reloc; | |
4310 | if (r == reloc) | |
4311 | return relocs[i][1]; | |
4312 | } | |
4313 | return reloc; | |
4314 | } | |
4315 | ||
b886a2ab RS |
4316 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4317 | Return true on success, storing the resolved value in RESULT. */ | |
4318 | ||
4319 | static bfd_boolean | |
4320 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4321 | offsetT *result) | |
4322 | { | |
4323 | switch (reloc) | |
4324 | { | |
4325 | case BFD_RELOC_MIPS_HIGHEST: | |
4326 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4327 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4328 | return TRUE; | |
4329 | ||
4330 | case BFD_RELOC_MIPS_HIGHER: | |
4331 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4332 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4333 | return TRUE; | |
4334 | ||
4335 | case BFD_RELOC_HI16_S: | |
4336 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4337 | case BFD_RELOC_MIPS16_HI16_S: | |
4338 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4339 | return TRUE; | |
4340 | ||
4341 | case BFD_RELOC_HI16: | |
4342 | case BFD_RELOC_MICROMIPS_HI16: | |
4343 | case BFD_RELOC_MIPS16_HI16: | |
4344 | *result = (operand >> 16) & 0xffff; | |
4345 | return TRUE; | |
4346 | ||
4347 | case BFD_RELOC_LO16: | |
4348 | case BFD_RELOC_MICROMIPS_LO16: | |
4349 | case BFD_RELOC_MIPS16_LO16: | |
4350 | *result = operand & 0xffff; | |
4351 | return TRUE; | |
4352 | ||
4353 | case BFD_RELOC_UNUSED: | |
4354 | *result = operand; | |
4355 | return TRUE; | |
4356 | ||
4357 | default: | |
4358 | return FALSE; | |
4359 | } | |
4360 | } | |
4361 | ||
71400594 RS |
4362 | /* Output an instruction. IP is the instruction information. |
4363 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4364 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4365 | a macro expansion. */ | |
71400594 RS |
4366 | |
4367 | static void | |
4368 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4369 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4370 | { |
14fe068b | 4371 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4372 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4373 | enum append_method method; |
2309ddf2 | 4374 | bfd_boolean relax32; |
2b0c8b40 | 4375 | int branch_disp; |
71400594 | 4376 | |
2309ddf2 | 4377 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4378 | fix_loongson2f (ip); |
4379 | ||
738f4d98 | 4380 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4381 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4382 | |
df58fc94 | 4383 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4384 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4385 | |
4386 | if (mips_opts.micromips | |
4387 | && !expansionp | |
4388 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4389 | && micromips_insn_length (ip->insn_mo) != 2) | |
4390 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4391 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4392 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4393 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4394 | |
15be625d CM |
4395 | if (address_expr == NULL) |
4396 | ip->complete_p = 1; | |
b886a2ab RS |
4397 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4398 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4399 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4400 | && address_expr->X_op == O_constant) |
4401 | { | |
15be625d CM |
4402 | switch (*reloc_type) |
4403 | { | |
15be625d | 4404 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4405 | { |
4406 | int shift; | |
4407 | ||
4408 | shift = mips_opts.micromips ? 1 : 2; | |
4409 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4410 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4411 | (unsigned long) address_expr->X_add_number); | |
4412 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4413 | & 0x3ffffff); | |
335574df | 4414 | ip->complete_p = 1; |
df58fc94 | 4415 | } |
15be625d CM |
4416 | break; |
4417 | ||
4418 | case BFD_RELOC_MIPS16_JMP: | |
4419 | if ((address_expr->X_add_number & 3) != 0) | |
4420 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4421 | (unsigned long) address_expr->X_add_number); | |
4422 | ip->insn_opcode |= | |
4423 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4424 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4425 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4426 | ip->complete_p = 1; |
15be625d CM |
4427 | break; |
4428 | ||
4429 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4430 | { |
4431 | int shift; | |
4432 | ||
4433 | shift = mips_opts.micromips ? 1 : 2; | |
4434 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4435 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4436 | (unsigned long) address_expr->X_add_number); | |
4437 | if (!mips_relax_branch) | |
4438 | { | |
4439 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4440 | & ~((1 << (shift + 16)) - 1)) | |
4441 | as_bad (_("branch address range overflow (0x%lx)"), | |
4442 | (unsigned long) address_expr->X_add_number); | |
4443 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4444 | & 0xffff); | |
4445 | } | |
df58fc94 | 4446 | } |
15be625d CM |
4447 | break; |
4448 | ||
4449 | default: | |
b886a2ab RS |
4450 | { |
4451 | offsetT value; | |
4452 | ||
4453 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4454 | &value)) | |
4455 | { | |
4456 | ip->insn_opcode |= value & 0xffff; | |
4457 | ip->complete_p = 1; | |
4458 | } | |
4459 | } | |
4460 | break; | |
4461 | } | |
15be625d CM |
4462 | } |
4463 | ||
71400594 RS |
4464 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4465 | { | |
4466 | /* There are a lot of optimizations we could do that we don't. | |
4467 | In particular, we do not, in general, reorder instructions. | |
4468 | If you use gcc with optimization, it will reorder | |
4469 | instructions and generally do much more optimization then we | |
4470 | do here; repeating all that work in the assembler would only | |
4471 | benefit hand written assembly code, and does not seem worth | |
4472 | it. */ | |
4473 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4474 | ? nops_for_insn (0, history, NULL) |
4475 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4476 | if (nops > 0) |
252b5132 RH |
4477 | { |
4478 | fragS *old_frag; | |
4479 | unsigned long old_frag_offset; | |
4480 | int i; | |
252b5132 RH |
4481 | |
4482 | old_frag = frag_now; | |
4483 | old_frag_offset = frag_now_fix (); | |
4484 | ||
4485 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4486 | add_fixed_insn (NOP_INSN); |
4487 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4488 | |
4489 | if (listing) | |
4490 | { | |
4491 | listing_prev_line (); | |
4492 | /* We may be at the start of a variant frag. In case we | |
4493 | are, make sure there is enough space for the frag | |
4494 | after the frags created by listing_prev_line. The | |
4495 | argument to frag_grow here must be at least as large | |
4496 | as the argument to all other calls to frag_grow in | |
4497 | this file. We don't have to worry about being in the | |
4498 | middle of a variant frag, because the variants insert | |
4499 | all needed nop instructions themselves. */ | |
4500 | frag_grow (40); | |
4501 | } | |
4502 | ||
462427c4 | 4503 | mips_move_text_labels (); |
252b5132 RH |
4504 | |
4505 | #ifndef NO_ECOFF_DEBUGGING | |
4506 | if (ECOFF_DEBUGGING) | |
4507 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4508 | #endif | |
4509 | } | |
71400594 RS |
4510 | } |
4511 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4512 | { | |
932d1a1b RS |
4513 | int nops; |
4514 | ||
4515 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4516 | ignoring hazards generated by the first prev_nop_frag_since | |
4517 | instructions. */ | |
4518 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4519 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4520 | |
71400594 RS |
4521 | /* Enforce NOPS as a minimum. */ |
4522 | if (nops > prev_nop_frag_required) | |
4523 | prev_nop_frag_required = nops; | |
252b5132 | 4524 | |
71400594 RS |
4525 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4526 | { | |
4527 | /* Settle for the current number of nops. Update the history | |
4528 | accordingly (for the benefit of any future .set reorder code). */ | |
4529 | prev_nop_frag = NULL; | |
4530 | insert_into_history (prev_nop_frag_since, | |
4531 | prev_nop_frag_holds, NOP_INSN); | |
4532 | } | |
4533 | else | |
4534 | { | |
4535 | /* Allow this instruction to replace one of the nops that was | |
4536 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4537 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4538 | prev_nop_frag_holds--; |
4539 | prev_nop_frag_since++; | |
252b5132 RH |
4540 | } |
4541 | } | |
4542 | ||
e407c74b | 4543 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4544 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4545 | |
58e2ea4d | 4546 | #ifdef OBJ_ELF |
e410add4 RS |
4547 | dwarf2_emit_insn (0); |
4548 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4549 | so "move" the instruction address accordingly. | |
4550 | ||
4551 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4552 | entries. If this instruction is a branch that we are going to swap | |
4553 | with the previous instruction, the two instructions should be | |
4554 | treated as a unit, and the debug information for both instructions | |
4555 | should refer to the start of the branch sequence. Using the | |
4556 | current position is certainly wrong when swapping a 32-bit branch | |
4557 | and a 16-bit delay slot, since the current position would then be | |
4558 | in the middle of a branch. */ | |
4559 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d MR |
4560 | #endif |
4561 | ||
df58fc94 RS |
4562 | relax32 = (mips_relax_branch |
4563 | /* Don't try branch relaxation within .set nomacro, or within | |
4564 | .set noat if we use $at for PIC computations. If it turns | |
4565 | out that the branch was out-of-range, we'll get an error. */ | |
4566 | && !mips_opts.warn_about_macros | |
4567 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4568 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4569 | as they have no complementing branches. */ | |
4570 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4571 | |
4572 | if (!HAVE_CODE_COMPRESSION | |
4573 | && address_expr | |
4574 | && relax32 | |
0b25d3e6 | 4575 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4576 | && delayed_branch_p (ip)) |
4a6a3df4 | 4577 | { |
895921c9 | 4578 | relaxed_branch = TRUE; |
1e915849 RS |
4579 | add_relaxed_insn (ip, (relaxed_branch_length |
4580 | (NULL, NULL, | |
11625dd8 RS |
4581 | uncond_branch_p (ip) ? -1 |
4582 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4583 | : 0)), 4, |
4584 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4585 | (AT, |
11625dd8 RS |
4586 | uncond_branch_p (ip), |
4587 | branch_likely_p (ip), | |
1e915849 RS |
4588 | pinfo & INSN_WRITE_GPR_31, |
4589 | 0), | |
4590 | address_expr->X_add_symbol, | |
4591 | address_expr->X_add_number); | |
4a6a3df4 AO |
4592 | *reloc_type = BFD_RELOC_UNUSED; |
4593 | } | |
df58fc94 RS |
4594 | else if (mips_opts.micromips |
4595 | && address_expr | |
4596 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4597 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4598 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4599 | /* Don't try branch relaxation when users specify | |
4600 | 16-bit/32-bit instructions. */ | |
4601 | && !forced_insn_length) | |
df58fc94 RS |
4602 | { |
4603 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4604 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4605 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4606 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4607 | int al = pinfo & INSN_WRITE_GPR_31; |
4608 | int length32; | |
4609 | ||
4610 | gas_assert (address_expr != NULL); | |
4611 | gas_assert (!mips_relax.sequence); | |
4612 | ||
2b0c8b40 | 4613 | relaxed_branch = TRUE; |
df58fc94 RS |
4614 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4615 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4616 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4617 | relax32, 0, 0), | |
df58fc94 RS |
4618 | address_expr->X_add_symbol, |
4619 | address_expr->X_add_number); | |
4620 | *reloc_type = BFD_RELOC_UNUSED; | |
4621 | } | |
4622 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4623 | { |
4624 | /* We need to set up a variant frag. */ | |
df58fc94 | 4625 | gas_assert (address_expr != NULL); |
1e915849 RS |
4626 | add_relaxed_insn (ip, 4, 0, |
4627 | RELAX_MIPS16_ENCODE | |
4628 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4629 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4630 | delayed_branch_p (&history[0]), |
1e915849 RS |
4631 | history[0].mips16_absolute_jump_p), |
4632 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4633 | } |
5c04167a | 4634 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4635 | { |
11625dd8 | 4636 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4637 | /* Make sure there is enough room to swap this instruction with |
4638 | a following jump instruction. */ | |
4639 | frag_grow (6); | |
1e915849 | 4640 | add_fixed_insn (ip); |
252b5132 RH |
4641 | } |
4642 | else | |
4643 | { | |
4644 | if (mips_opts.mips16 | |
4645 | && mips_opts.noreorder | |
11625dd8 | 4646 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4647 | as_warn (_("extended instruction in delay slot")); |
4648 | ||
4d7206a2 RS |
4649 | if (mips_relax.sequence) |
4650 | { | |
4651 | /* If we've reached the end of this frag, turn it into a variant | |
4652 | frag and record the information for the instructions we've | |
4653 | written so far. */ | |
4654 | if (frag_room () < 4) | |
4655 | relax_close_frag (); | |
df58fc94 | 4656 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4657 | } |
4658 | ||
584892a6 | 4659 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4660 | { |
4661 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4662 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4663 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4664 | mips_macro_warning.insns[0]++; | |
4665 | } | |
584892a6 | 4666 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4667 | { |
4668 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4669 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4670 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4671 | mips_macro_warning.insns[1]++; | |
4672 | } | |
584892a6 | 4673 | |
1e915849 RS |
4674 | if (mips_opts.mips16) |
4675 | { | |
4676 | ip->fixed_p = 1; | |
4677 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4678 | } | |
4679 | add_fixed_insn (ip); | |
252b5132 RH |
4680 | } |
4681 | ||
9fe77896 | 4682 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4683 | { |
df58fc94 | 4684 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4685 | reloc_howto_type *howto0; |
9fe77896 RS |
4686 | reloc_howto_type *howto; |
4687 | int i; | |
34ce925e | 4688 | |
df58fc94 RS |
4689 | /* Perform any necessary conversion to microMIPS relocations |
4690 | and find out how many relocations there actually are. */ | |
4691 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4692 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4693 | ||
9fe77896 RS |
4694 | /* In a compound relocation, it is the final (outermost) |
4695 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4696 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4697 | ||
9fe77896 RS |
4698 | if (howto == NULL) |
4699 | { | |
4700 | /* To reproduce this failure try assembling gas/testsuites/ | |
4701 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4702 | assembler. */ | |
df58fc94 RS |
4703 | as_bad (_("Unsupported MIPS relocation number %d"), |
4704 | final_type[i - 1]); | |
9fe77896 RS |
4705 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4706 | } | |
2309ddf2 MR |
4707 | |
4708 | if (i > 1) | |
4709 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4710 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4711 | bfd_get_reloc_size (howto), | |
4712 | address_expr, | |
2309ddf2 MR |
4713 | howto0 && howto0->pc_relative, |
4714 | final_type[0]); | |
9fe77896 RS |
4715 | |
4716 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4717 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4718 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4719 | ||
4720 | /* These relocations can have an addend that won't fit in | |
4721 | 4 octets for 64bit assembly. */ | |
4722 | if (HAVE_64BIT_GPRS | |
4723 | && ! howto->partial_inplace | |
4724 | && (reloc_type[0] == BFD_RELOC_16 | |
4725 | || reloc_type[0] == BFD_RELOC_32 | |
4726 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4727 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4728 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4729 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4730 | || reloc_type[0] == BFD_RELOC_64 | |
4731 | || reloc_type[0] == BFD_RELOC_CTOR | |
4732 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4733 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4734 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4735 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4736 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4737 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4738 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4739 | || hi16_reloc_p (reloc_type[0]) | |
4740 | || lo16_reloc_p (reloc_type[0]))) | |
4741 | ip->fixp[0]->fx_no_overflow = 1; | |
4742 | ||
ddaf2c41 MR |
4743 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4744 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4745 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4746 | ip->fixp[0]->fx_no_overflow = 1; | |
4747 | ||
9fe77896 RS |
4748 | if (mips_relax.sequence) |
4749 | { | |
4750 | if (mips_relax.first_fixup == 0) | |
4751 | mips_relax.first_fixup = ip->fixp[0]; | |
4752 | } | |
4753 | else if (reloc_needs_lo_p (*reloc_type)) | |
4754 | { | |
4755 | struct mips_hi_fixup *hi_fixup; | |
4756 | ||
4757 | /* Reuse the last entry if it already has a matching %lo. */ | |
4758 | hi_fixup = mips_hi_fixup_list; | |
4759 | if (hi_fixup == 0 | |
4760 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4761 | { |
9fe77896 RS |
4762 | hi_fixup = ((struct mips_hi_fixup *) |
4763 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4764 | hi_fixup->next = mips_hi_fixup_list; | |
4765 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4766 | } |
9fe77896 RS |
4767 | hi_fixup->fixp = ip->fixp[0]; |
4768 | hi_fixup->seg = now_seg; | |
4769 | } | |
252b5132 | 4770 | |
9fe77896 RS |
4771 | /* Add fixups for the second and third relocations, if given. |
4772 | Note that the ABI allows the second relocation to be | |
4773 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4774 | moment we only use RSS_UNDEF, but we could add support | |
4775 | for the others if it ever becomes necessary. */ | |
4776 | for (i = 1; i < 3; i++) | |
4777 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4778 | { | |
4779 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4780 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4781 | FALSE, final_type[i]); |
f6688943 | 4782 | |
9fe77896 RS |
4783 | /* Use fx_tcbit to mark compound relocs. */ |
4784 | ip->fixp[0]->fx_tcbit = 1; | |
4785 | ip->fixp[i]->fx_tcbit = 1; | |
4786 | } | |
252b5132 | 4787 | } |
1e915849 | 4788 | install_insn (ip); |
252b5132 RH |
4789 | |
4790 | /* Update the register mask information. */ | |
4c260379 RS |
4791 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4792 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4793 | |
a4e06468 | 4794 | switch (method) |
252b5132 | 4795 | { |
a4e06468 RS |
4796 | case APPEND_ADD: |
4797 | insert_into_history (0, 1, ip); | |
4798 | break; | |
4799 | ||
4800 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4801 | { |
4802 | struct mips_cl_insn *nop; | |
4803 | ||
4804 | insert_into_history (0, 1, ip); | |
4805 | nop = get_delay_slot_nop (ip); | |
4806 | add_fixed_insn (nop); | |
4807 | insert_into_history (0, 1, nop); | |
4808 | if (mips_relax.sequence) | |
4809 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4810 | } | |
a4e06468 RS |
4811 | break; |
4812 | ||
4813 | case APPEND_ADD_COMPACT: | |
4814 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4815 | gas_assert (mips_opts.mips16); | |
4816 | ip->insn_opcode |= 0x0080; | |
4817 | find_altered_mips16_opcode (ip); | |
4818 | install_insn (ip); | |
4819 | insert_into_history (0, 1, ip); | |
4820 | break; | |
4821 | ||
4822 | case APPEND_SWAP: | |
4823 | { | |
4824 | struct mips_cl_insn delay = history[0]; | |
4825 | if (mips_opts.mips16) | |
4826 | { | |
4827 | know (delay.frag == ip->frag); | |
4828 | move_insn (ip, delay.frag, delay.where); | |
4829 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4830 | } | |
464ab0e5 | 4831 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4832 | { |
4833 | /* Add the delay slot instruction to the end of the | |
4834 | current frag and shrink the fixed part of the | |
4835 | original frag. If the branch occupies the tail of | |
4836 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4837 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4838 | if (delay.frag == ip->frag) |
2b0c8b40 | 4839 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4840 | add_fixed_insn (&delay); |
4841 | } | |
4842 | else | |
4843 | { | |
2b0c8b40 MR |
4844 | move_insn (&delay, ip->frag, |
4845 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4846 | move_insn (ip, history[0].frag, history[0].where); |
4847 | } | |
4848 | history[0] = *ip; | |
4849 | delay.fixed_p = 1; | |
4850 | insert_into_history (0, 1, &delay); | |
4851 | } | |
4852 | break; | |
252b5132 RH |
4853 | } |
4854 | ||
13408f1e | 4855 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4856 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4857 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
4858 | { |
4859 | unsigned int i; | |
4860 | ||
79850f26 | 4861 | mips_no_prev_insn (); |
13408f1e | 4862 | |
e407c74b | 4863 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 4864 | history[i].cleared_p = 1; |
e407c74b NC |
4865 | } |
4866 | ||
df58fc94 RS |
4867 | /* We need to emit a label at the end of branch-likely macros. */ |
4868 | if (emit_branch_likely_macro) | |
4869 | { | |
4870 | emit_branch_likely_macro = FALSE; | |
4871 | micromips_add_label (); | |
4872 | } | |
4873 | ||
252b5132 RH |
4874 | /* We just output an insn, so the next one doesn't have a label. */ |
4875 | mips_clear_insn_labels (); | |
252b5132 RH |
4876 | } |
4877 | ||
e407c74b NC |
4878 | /* Forget that there was any previous instruction or label. |
4879 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
4880 | |
4881 | static void | |
7d10b47d | 4882 | mips_no_prev_insn (void) |
252b5132 | 4883 | { |
7d10b47d RS |
4884 | prev_nop_frag = NULL; |
4885 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4886 | mips_clear_insn_labels (); |
4887 | } | |
4888 | ||
7d10b47d RS |
4889 | /* This function must be called before we emit something other than |
4890 | instructions. It is like mips_no_prev_insn except that it inserts | |
4891 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4892 | |
7d10b47d RS |
4893 | void |
4894 | mips_emit_delays (void) | |
252b5132 RH |
4895 | { |
4896 | if (! mips_opts.noreorder) | |
4897 | { | |
932d1a1b | 4898 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4899 | if (nops > 0) |
4900 | { | |
7d10b47d RS |
4901 | while (nops-- > 0) |
4902 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4903 | mips_move_text_labels (); |
7d10b47d RS |
4904 | } |
4905 | } | |
4906 | mips_no_prev_insn (); | |
4907 | } | |
4908 | ||
4909 | /* Start a (possibly nested) noreorder block. */ | |
4910 | ||
4911 | static void | |
4912 | start_noreorder (void) | |
4913 | { | |
4914 | if (mips_opts.noreorder == 0) | |
4915 | { | |
4916 | unsigned int i; | |
4917 | int nops; | |
4918 | ||
4919 | /* None of the instructions before the .set noreorder can be moved. */ | |
4920 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4921 | history[i].fixed_p = 1; | |
4922 | ||
4923 | /* Insert any nops that might be needed between the .set noreorder | |
4924 | block and the previous instructions. We will later remove any | |
4925 | nops that turn out not to be needed. */ | |
932d1a1b | 4926 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4927 | if (nops > 0) |
4928 | { | |
4929 | if (mips_optimize != 0) | |
252b5132 RH |
4930 | { |
4931 | /* Record the frag which holds the nop instructions, so | |
4932 | that we can remove them if we don't need them. */ | |
df58fc94 | 4933 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4934 | prev_nop_frag = frag_now; |
4935 | prev_nop_frag_holds = nops; | |
4936 | prev_nop_frag_required = 0; | |
4937 | prev_nop_frag_since = 0; | |
4938 | } | |
4939 | ||
4940 | for (; nops > 0; --nops) | |
1e915849 | 4941 | add_fixed_insn (NOP_INSN); |
252b5132 | 4942 | |
7d10b47d RS |
4943 | /* Move on to a new frag, so that it is safe to simply |
4944 | decrease the size of prev_nop_frag. */ | |
4945 | frag_wane (frag_now); | |
4946 | frag_new (0); | |
462427c4 | 4947 | mips_move_text_labels (); |
252b5132 | 4948 | } |
df58fc94 | 4949 | mips_mark_labels (); |
7d10b47d | 4950 | mips_clear_insn_labels (); |
252b5132 | 4951 | } |
7d10b47d RS |
4952 | mips_opts.noreorder++; |
4953 | mips_any_noreorder = 1; | |
4954 | } | |
252b5132 | 4955 | |
7d10b47d | 4956 | /* End a nested noreorder block. */ |
252b5132 | 4957 | |
7d10b47d RS |
4958 | static void |
4959 | end_noreorder (void) | |
4960 | { | |
4961 | mips_opts.noreorder--; | |
4962 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4963 | { | |
4964 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4965 | handling nop insertion the .set reorder way. */ | |
4966 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4967 | * NOP_INSN_SIZE); |
7d10b47d RS |
4968 | insert_into_history (prev_nop_frag_since, |
4969 | prev_nop_frag_required, NOP_INSN); | |
4970 | prev_nop_frag = NULL; | |
4971 | } | |
252b5132 RH |
4972 | } |
4973 | ||
584892a6 RS |
4974 | /* Set up global variables for the start of a new macro. */ |
4975 | ||
4976 | static void | |
4977 | macro_start (void) | |
4978 | { | |
4979 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4980 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4981 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4982 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4983 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4984 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4985 | switch (history[0].insn_mo->pinfo2 |
4986 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4987 | { | |
4988 | case INSN2_BRANCH_DELAY_32BIT: | |
4989 | mips_macro_warning.delay_slot_length = 4; | |
4990 | break; | |
4991 | case INSN2_BRANCH_DELAY_16BIT: | |
4992 | mips_macro_warning.delay_slot_length = 2; | |
4993 | break; | |
4994 | default: | |
4995 | mips_macro_warning.delay_slot_length = 0; | |
4996 | break; | |
4997 | } | |
4998 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4999 | } |
5000 | ||
df58fc94 RS |
5001 | /* Given that a macro is longer than one instruction or of the wrong size, |
5002 | return the appropriate warning for it. Return null if no warning is | |
5003 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
5004 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
5005 | and RELAX_NOMACRO. */ | |
584892a6 RS |
5006 | |
5007 | static const char * | |
5008 | macro_warning (relax_substateT subtype) | |
5009 | { | |
5010 | if (subtype & RELAX_DELAY_SLOT) | |
5011 | return _("Macro instruction expanded into multiple instructions" | |
5012 | " in a branch delay slot"); | |
5013 | else if (subtype & RELAX_NOMACRO) | |
5014 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
5015 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
5016 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
5017 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
5018 | ? _("Macro instruction expanded into a wrong size instruction" | |
5019 | " in a 16-bit branch delay slot") | |
5020 | : _("Macro instruction expanded into a wrong size instruction" | |
5021 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
5022 | else |
5023 | return 0; | |
5024 | } | |
5025 | ||
5026 | /* Finish up a macro. Emit warnings as appropriate. */ | |
5027 | ||
5028 | static void | |
5029 | macro_end (void) | |
5030 | { | |
df58fc94 RS |
5031 | /* Relaxation warning flags. */ |
5032 | relax_substateT subtype = 0; | |
5033 | ||
5034 | /* Check delay slot size requirements. */ | |
5035 | if (mips_macro_warning.delay_slot_length == 2) | |
5036 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
5037 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 5038 | { |
df58fc94 RS |
5039 | if (mips_macro_warning.delay_slot_length |
5040 | != mips_macro_warning.first_insn_sizes[0]) | |
5041 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
5042 | if (mips_macro_warning.delay_slot_length | |
5043 | != mips_macro_warning.first_insn_sizes[1]) | |
5044 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
5045 | } | |
584892a6 | 5046 | |
df58fc94 RS |
5047 | /* Check instruction count requirements. */ |
5048 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
5049 | { | |
5050 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
5051 | subtype |= RELAX_SECOND_LONGER; |
5052 | if (mips_opts.warn_about_macros) | |
5053 | subtype |= RELAX_NOMACRO; | |
5054 | if (mips_macro_warning.delay_slot_p) | |
5055 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 5056 | } |
584892a6 | 5057 | |
df58fc94 RS |
5058 | /* If both alternatives fail to fill a delay slot correctly, |
5059 | emit the warning now. */ | |
5060 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
5061 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
5062 | { | |
5063 | relax_substateT s; | |
5064 | const char *msg; | |
5065 | ||
5066 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
5067 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
5068 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
5069 | msg = macro_warning (s); | |
5070 | if (msg != NULL) | |
5071 | as_warn ("%s", msg); | |
5072 | subtype &= ~s; | |
5073 | } | |
5074 | ||
5075 | /* If both implementations are longer than 1 instruction, then emit the | |
5076 | warning now. */ | |
5077 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
5078 | { | |
5079 | relax_substateT s; | |
5080 | const char *msg; | |
5081 | ||
5082 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
5083 | msg = macro_warning (s); | |
5084 | if (msg != NULL) | |
5085 | as_warn ("%s", msg); | |
5086 | subtype &= ~s; | |
584892a6 | 5087 | } |
df58fc94 RS |
5088 | |
5089 | /* If any flags still set, then one implementation might need a warning | |
5090 | and the other either will need one of a different kind or none at all. | |
5091 | Pass any remaining flags over to relaxation. */ | |
5092 | if (mips_macro_warning.first_frag != NULL) | |
5093 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
5094 | } |
5095 | ||
df58fc94 RS |
5096 | /* Instruction operand formats used in macros that vary between |
5097 | standard MIPS and microMIPS code. */ | |
5098 | ||
5099 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
5100 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
5101 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
5102 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
5103 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
5104 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
5105 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
5106 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
5107 | ||
5108 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
5109 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
5110 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
5111 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
5112 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
5113 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
5114 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
5115 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
5116 | ||
6e1304d8 RS |
5117 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
5118 | The first argument in *ARGS will be either the code for a single | |
5119 | relocation or -1 followed by the three codes that make up a | |
5120 | composite relocation. */ | |
5121 | ||
5122 | static void | |
5123 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
5124 | { | |
5125 | int i, next; | |
5126 | ||
5127 | next = va_arg (*args, int); | |
5128 | if (next >= 0) | |
5129 | r[0] = (bfd_reloc_code_real_type) next; | |
5130 | else | |
5131 | for (i = 0; i < 3; i++) | |
5132 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
5133 | } | |
5134 | ||
252b5132 RH |
5135 | /* Build an instruction created by a macro expansion. This is passed |
5136 | a pointer to the count of instructions created so far, an | |
5137 | expression, the name of the instruction to build, an operand format | |
5138 | string, and corresponding arguments. */ | |
5139 | ||
252b5132 | 5140 | static void |
67c0d1eb | 5141 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 5142 | { |
df58fc94 | 5143 | const struct mips_opcode *mo = NULL; |
f6688943 | 5144 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
5145 | const struct mips_opcode *amo; |
5146 | struct hash_control *hash; | |
5147 | struct mips_cl_insn insn; | |
252b5132 | 5148 | va_list args; |
252b5132 | 5149 | |
252b5132 | 5150 | va_start (args, fmt); |
252b5132 | 5151 | |
252b5132 RH |
5152 | if (mips_opts.mips16) |
5153 | { | |
03ea81db | 5154 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5155 | va_end (args); |
5156 | return; | |
5157 | } | |
5158 | ||
f6688943 TS |
5159 | r[0] = BFD_RELOC_UNUSED; |
5160 | r[1] = BFD_RELOC_UNUSED; | |
5161 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5162 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5163 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5164 | gas_assert (amo); | |
5165 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5166 | |
df58fc94 | 5167 | do |
8b082fb1 TS |
5168 | { |
5169 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5170 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5171 | We try to match an instruction that fulfils the branch delay | |
5172 | slot instruction length requirement (if any) of the previous | |
5173 | instruction. While doing this we record the first instruction | |
5174 | seen that matches all the other conditions and use it anyway | |
5175 | if the requirement cannot be met; we will issue an appropriate | |
5176 | warning later on. */ | |
5177 | if (strcmp (fmt, amo->args) == 0 | |
5178 | && amo->pinfo != INSN_MACRO | |
5179 | && is_opcode_valid (amo) | |
5180 | && is_size_valid (amo)) | |
5181 | { | |
5182 | if (is_delay_slot_valid (amo)) | |
5183 | { | |
5184 | mo = amo; | |
5185 | break; | |
5186 | } | |
5187 | else if (!mo) | |
5188 | mo = amo; | |
5189 | } | |
8b082fb1 | 5190 | |
df58fc94 RS |
5191 | ++amo; |
5192 | gas_assert (amo->name); | |
252b5132 | 5193 | } |
df58fc94 | 5194 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5195 | |
df58fc94 | 5196 | gas_assert (mo); |
1e915849 | 5197 | create_insn (&insn, mo); |
252b5132 RH |
5198 | for (;;) |
5199 | { | |
5200 | switch (*fmt++) | |
5201 | { | |
5202 | case '\0': | |
5203 | break; | |
5204 | ||
5205 | case ',': | |
5206 | case '(': | |
5207 | case ')': | |
5208 | continue; | |
5209 | ||
5f74bc13 CD |
5210 | case '+': |
5211 | switch (*fmt++) | |
5212 | { | |
5213 | case 'A': | |
5214 | case 'E': | |
df58fc94 RS |
5215 | INSERT_OPERAND (mips_opts.micromips, |
5216 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5217 | continue; |
5218 | ||
5219 | case 'B': | |
5220 | case 'F': | |
5221 | /* Note that in the macro case, these arguments are already | |
5222 | in MSB form. (When handling the instruction in the | |
5223 | non-macro case, these arguments are sizes from which | |
5224 | MSB values must be calculated.) */ | |
df58fc94 RS |
5225 | INSERT_OPERAND (mips_opts.micromips, |
5226 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5227 | continue; |
5228 | ||
b015e599 AP |
5229 | case 'J': |
5230 | gas_assert (!mips_opts.micromips); | |
5231 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5232 | continue; | |
5233 | ||
5f74bc13 CD |
5234 | case 'C': |
5235 | case 'G': | |
5236 | case 'H': | |
5237 | /* Note that in the macro case, these arguments are already | |
5238 | in MSBD form. (When handling the instruction in the | |
5239 | non-macro case, these arguments are sizes from which | |
5240 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5241 | INSERT_OPERAND (mips_opts.micromips, |
5242 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5243 | continue; |
5244 | ||
dd3cbb7e | 5245 | case 'Q': |
df58fc94 RS |
5246 | gas_assert (!mips_opts.micromips); |
5247 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5248 | continue; |
5249 | ||
7f3c4072 CM |
5250 | case 'j': |
5251 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5252 | continue; | |
5253 | ||
5f74bc13 | 5254 | default: |
b37df7c4 | 5255 | abort (); |
5f74bc13 CD |
5256 | } |
5257 | continue; | |
5258 | ||
8b082fb1 | 5259 | case '2': |
03f66e8a | 5260 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5261 | continue; |
5262 | ||
df58fc94 RS |
5263 | case 'n': |
5264 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5265 | case 't': |
5266 | case 'w': | |
5267 | case 'E': | |
df58fc94 | 5268 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5269 | continue; |
5270 | ||
5271 | case 'c': | |
df58fc94 RS |
5272 | gas_assert (!mips_opts.micromips); |
5273 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
5274 | continue; |
5275 | ||
252b5132 | 5276 | case 'W': |
df58fc94 RS |
5277 | gas_assert (!mips_opts.micromips); |
5278 | case 'T': | |
5279 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5280 | continue; |
5281 | ||
252b5132 | 5282 | case 'G': |
df58fc94 RS |
5283 | if (mips_opts.micromips) |
5284 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5285 | else | |
5286 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5287 | continue; | |
5288 | ||
af7ee8bf | 5289 | case 'K': |
df58fc94 RS |
5290 | gas_assert (!mips_opts.micromips); |
5291 | case 'd': | |
5292 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5293 | continue; |
5294 | ||
4372b673 | 5295 | case 'U': |
df58fc94 | 5296 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5297 | { |
5298 | int tmp = va_arg (args, int); | |
5299 | ||
df58fc94 RS |
5300 | INSERT_OPERAND (0, RT, insn, tmp); |
5301 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5302 | } |
df58fc94 | 5303 | continue; |
4372b673 | 5304 | |
252b5132 RH |
5305 | case 'V': |
5306 | case 'S': | |
df58fc94 RS |
5307 | gas_assert (!mips_opts.micromips); |
5308 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5309 | continue; |
5310 | ||
5311 | case 'z': | |
5312 | continue; | |
5313 | ||
5314 | case '<': | |
df58fc94 RS |
5315 | INSERT_OPERAND (mips_opts.micromips, |
5316 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5317 | continue; |
5318 | ||
5319 | case 'D': | |
df58fc94 RS |
5320 | gas_assert (!mips_opts.micromips); |
5321 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5322 | continue; |
5323 | ||
5324 | case 'B': | |
df58fc94 RS |
5325 | gas_assert (!mips_opts.micromips); |
5326 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5327 | continue; |
5328 | ||
4372b673 | 5329 | case 'J': |
df58fc94 RS |
5330 | gas_assert (!mips_opts.micromips); |
5331 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5332 | continue; |
5333 | ||
252b5132 | 5334 | case 'q': |
df58fc94 RS |
5335 | gas_assert (!mips_opts.micromips); |
5336 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5337 | continue; |
5338 | ||
5339 | case 'b': | |
5340 | case 's': | |
5341 | case 'r': | |
5342 | case 'v': | |
df58fc94 | 5343 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5344 | continue; |
5345 | ||
5346 | case 'i': | |
5347 | case 'j': | |
6e1304d8 | 5348 | macro_read_relocs (&args, r); |
9c2799c2 | 5349 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5350 | || *r == BFD_RELOC_MIPS_HIGHER |
5351 | || *r == BFD_RELOC_HI16_S | |
5352 | || *r == BFD_RELOC_LO16 | |
5353 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5354 | continue; | |
5355 | ||
5356 | case 'o': | |
5357 | macro_read_relocs (&args, r); | |
252b5132 RH |
5358 | continue; |
5359 | ||
5360 | case 'u': | |
6e1304d8 | 5361 | macro_read_relocs (&args, r); |
9c2799c2 | 5362 | gas_assert (ep != NULL |
90ecf173 MR |
5363 | && (ep->X_op == O_constant |
5364 | || (ep->X_op == O_symbol | |
5365 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5366 | || *r == BFD_RELOC_HI16_S | |
5367 | || *r == BFD_RELOC_HI16 | |
5368 | || *r == BFD_RELOC_GPREL16 | |
5369 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5370 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5371 | continue; |
5372 | ||
5373 | case 'p': | |
9c2799c2 | 5374 | gas_assert (ep != NULL); |
bad36eac | 5375 | |
252b5132 RH |
5376 | /* |
5377 | * This allows macro() to pass an immediate expression for | |
5378 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5379 | * |
5380 | * We don't allow branch relaxation for these branches, as | |
5381 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5382 | */ |
5383 | if (ep->X_op == O_constant) | |
5384 | { | |
df58fc94 RS |
5385 | /* For microMIPS we always use relocations for branches. |
5386 | So we should not resolve immediate values. */ | |
5387 | gas_assert (!mips_opts.micromips); | |
5388 | ||
bad36eac DJ |
5389 | if ((ep->X_add_number & 3) != 0) |
5390 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5391 | (unsigned long) ep->X_add_number); | |
5392 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5393 | as_bad (_("branch address range overflow (0x%lx)"), | |
5394 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5395 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5396 | ep = NULL; | |
5397 | } | |
5398 | else | |
0b25d3e6 | 5399 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5400 | continue; |
5401 | ||
5402 | case 'a': | |
9c2799c2 | 5403 | gas_assert (ep != NULL); |
f6688943 | 5404 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5405 | continue; |
5406 | ||
5407 | case 'C': | |
df58fc94 RS |
5408 | gas_assert (!mips_opts.micromips); |
5409 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5410 | continue; |
5411 | ||
d43b4baf | 5412 | case 'k': |
df58fc94 RS |
5413 | INSERT_OPERAND (mips_opts.micromips, |
5414 | CACHE, insn, va_arg (args, unsigned long)); | |
5415 | continue; | |
5416 | ||
5417 | case '|': | |
5418 | gas_assert (mips_opts.micromips); | |
5419 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5420 | continue; | |
5421 | ||
5422 | case '.': | |
5423 | gas_assert (mips_opts.micromips); | |
5424 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5425 | continue; | |
5426 | ||
dec0624d MR |
5427 | case '\\': |
5428 | INSERT_OPERAND (mips_opts.micromips, | |
5429 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5430 | continue; | |
5431 | ||
df58fc94 | 5432 | case '~': |
dec0624d MR |
5433 | INSERT_OPERAND (mips_opts.micromips, |
5434 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5435 | continue; |
5436 | ||
5437 | case 'N': | |
5438 | gas_assert (mips_opts.micromips); | |
5439 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5440 | continue; | |
5441 | ||
5442 | case 'm': /* Opcode extension character. */ | |
5443 | gas_assert (mips_opts.micromips); | |
5444 | switch (*fmt++) | |
5445 | { | |
5446 | case 'j': | |
5447 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5448 | break; | |
5449 | ||
5450 | case 'p': | |
5451 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5452 | break; | |
5453 | ||
5454 | case 'F': | |
5455 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5456 | break; | |
5457 | ||
5458 | default: | |
b37df7c4 | 5459 | abort (); |
df58fc94 | 5460 | } |
d43b4baf TS |
5461 | continue; |
5462 | ||
252b5132 | 5463 | default: |
b37df7c4 | 5464 | abort (); |
252b5132 RH |
5465 | } |
5466 | break; | |
5467 | } | |
5468 | va_end (args); | |
9c2799c2 | 5469 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5470 | |
df58fc94 | 5471 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5472 | } |
5473 | ||
5474 | static void | |
67c0d1eb | 5475 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5476 | va_list *args) |
252b5132 | 5477 | { |
1e915849 | 5478 | struct mips_opcode *mo; |
252b5132 | 5479 | struct mips_cl_insn insn; |
f6688943 TS |
5480 | bfd_reloc_code_real_type r[3] |
5481 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5482 | |
1e915849 | 5483 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5484 | gas_assert (mo); |
5485 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5486 | |
1e915849 | 5487 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5488 | { |
1e915849 | 5489 | ++mo; |
9c2799c2 NC |
5490 | gas_assert (mo->name); |
5491 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5492 | } |
5493 | ||
1e915849 | 5494 | create_insn (&insn, mo); |
252b5132 RH |
5495 | for (;;) |
5496 | { | |
5497 | int c; | |
5498 | ||
5499 | c = *fmt++; | |
5500 | switch (c) | |
5501 | { | |
5502 | case '\0': | |
5503 | break; | |
5504 | ||
5505 | case ',': | |
5506 | case '(': | |
5507 | case ')': | |
5508 | continue; | |
5509 | ||
5510 | case 'y': | |
5511 | case 'w': | |
03ea81db | 5512 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5513 | continue; |
5514 | ||
5515 | case 'x': | |
5516 | case 'v': | |
03ea81db | 5517 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5518 | continue; |
5519 | ||
5520 | case 'z': | |
03ea81db | 5521 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5522 | continue; |
5523 | ||
5524 | case 'Z': | |
03ea81db | 5525 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5526 | continue; |
5527 | ||
5528 | case '0': | |
5529 | case 'S': | |
5530 | case 'P': | |
5531 | case 'R': | |
5532 | continue; | |
5533 | ||
5534 | case 'X': | |
03ea81db | 5535 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5536 | continue; |
5537 | ||
5538 | case 'Y': | |
5539 | { | |
5540 | int regno; | |
5541 | ||
03ea81db | 5542 | regno = va_arg (*args, int); |
252b5132 | 5543 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5544 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5545 | } |
5546 | continue; | |
5547 | ||
5548 | case '<': | |
5549 | case '>': | |
5550 | case '4': | |
5551 | case '5': | |
5552 | case 'H': | |
5553 | case 'W': | |
5554 | case 'D': | |
5555 | case 'j': | |
5556 | case '8': | |
5557 | case 'V': | |
5558 | case 'C': | |
5559 | case 'U': | |
5560 | case 'k': | |
5561 | case 'K': | |
5562 | case 'p': | |
5563 | case 'q': | |
5564 | { | |
b886a2ab RS |
5565 | offsetT value; |
5566 | ||
9c2799c2 | 5567 | gas_assert (ep != NULL); |
252b5132 RH |
5568 | |
5569 | if (ep->X_op != O_constant) | |
874e8986 | 5570 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5571 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5572 | { |
b886a2ab | 5573 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5574 | ep = NULL; |
f6688943 | 5575 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5576 | } |
5577 | } | |
5578 | continue; | |
5579 | ||
5580 | case '6': | |
03ea81db | 5581 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5582 | continue; |
5583 | } | |
5584 | ||
5585 | break; | |
5586 | } | |
5587 | ||
9c2799c2 | 5588 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5589 | |
df58fc94 | 5590 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5591 | } |
5592 | ||
2051e8c4 MR |
5593 | /* |
5594 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5595 | * higher bits unset. | |
5596 | */ | |
9f872bbe | 5597 | static void |
2051e8c4 MR |
5598 | normalize_constant_expr (expressionS *ex) |
5599 | { | |
9ee2a2d4 | 5600 | if (ex->X_op == O_constant |
2051e8c4 MR |
5601 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5602 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5603 | - 0x80000000); | |
5604 | } | |
5605 | ||
5606 | /* | |
5607 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5608 | * all higher bits unset. | |
5609 | */ | |
5610 | static void | |
5611 | normalize_address_expr (expressionS *ex) | |
5612 | { | |
5613 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5614 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5615 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5616 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5617 | - 0x80000000); | |
5618 | } | |
5619 | ||
438c16b8 TS |
5620 | /* |
5621 | * Generate a "jalr" instruction with a relocation hint to the called | |
5622 | * function. This occurs in NewABI PIC code. | |
5623 | */ | |
5624 | static void | |
df58fc94 | 5625 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5626 | { |
df58fc94 RS |
5627 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5628 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5629 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5630 | const char *jalr; | |
685736be | 5631 | char *f = NULL; |
b34976b6 | 5632 | |
1180b5a4 | 5633 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5634 | { |
cc3d92a5 | 5635 | frag_grow (8); |
f21f8242 AO |
5636 | f = frag_more (0); |
5637 | } | |
2906b037 | 5638 | if (mips_opts.micromips) |
df58fc94 RS |
5639 | { |
5640 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
e64af278 MR |
5641 | if (MIPS_JALR_HINT_P (ep) |
5642 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
5643 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5644 | else | |
5645 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5646 | } | |
2906b037 MR |
5647 | else |
5648 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5649 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5650 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5651 | } |
5652 | ||
252b5132 RH |
5653 | /* |
5654 | * Generate a "lui" instruction. | |
5655 | */ | |
5656 | static void | |
67c0d1eb | 5657 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5658 | { |
9c2799c2 | 5659 | gas_assert (! mips_opts.mips16); |
252b5132 | 5660 | |
df58fc94 | 5661 | if (ep->X_op != O_constant) |
252b5132 | 5662 | { |
9c2799c2 | 5663 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5664 | /* _gp_disp is a special case, used from s_cpload. |
5665 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5666 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5667 | || (! HAVE_NEWABI |
aa6975fb ILT |
5668 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5669 | || (! mips_in_shared | |
bbe506e8 TS |
5670 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5671 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5672 | } |
5673 | ||
df58fc94 | 5674 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5675 | } |
5676 | ||
885add95 CD |
5677 | /* Generate a sequence of instructions to do a load or store from a constant |
5678 | offset off of a base register (breg) into/from a target register (treg), | |
5679 | using AT if necessary. */ | |
5680 | static void | |
67c0d1eb RS |
5681 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5682 | int treg, int breg, int dbl) | |
885add95 | 5683 | { |
9c2799c2 | 5684 | gas_assert (ep->X_op == O_constant); |
885add95 | 5685 | |
256ab948 | 5686 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5687 | if (!dbl) |
5688 | normalize_constant_expr (ep); | |
256ab948 | 5689 | |
67c1ffbe | 5690 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5691 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5692 | as_warn (_("operand overflow")); |
5693 | ||
5694 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5695 | { | |
5696 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5697 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5698 | } |
5699 | else | |
5700 | { | |
5701 | /* 32-bit offset, need multiple instructions and AT, like: | |
5702 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5703 | addu $tempreg,$tempreg,$breg | |
5704 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5705 | to handle the complete offset. */ | |
67c0d1eb RS |
5706 | macro_build_lui (ep, AT); |
5707 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5708 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5709 | |
741fe287 | 5710 | if (!mips_opts.at) |
8fc2e39e | 5711 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5712 | } |
5713 | } | |
5714 | ||
252b5132 RH |
5715 | /* set_at() |
5716 | * Generates code to set the $at register to true (one) | |
5717 | * if reg is less than the immediate expression. | |
5718 | */ | |
5719 | static void | |
67c0d1eb | 5720 | set_at (int reg, int unsignedp) |
252b5132 RH |
5721 | { |
5722 | if (imm_expr.X_op == O_constant | |
5723 | && imm_expr.X_add_number >= -0x8000 | |
5724 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5725 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5726 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5727 | else |
5728 | { | |
67c0d1eb RS |
5729 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5730 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5731 | } |
5732 | } | |
5733 | ||
5734 | /* Warn if an expression is not a constant. */ | |
5735 | ||
5736 | static void | |
17a2f251 | 5737 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5738 | { |
5739 | if (ex->X_op == O_big) | |
5740 | as_bad (_("unsupported large constant")); | |
5741 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5742 | as_bad (_("Instruction %s requires absolute expression"), |
5743 | ip->insn_mo->name); | |
13757d0c | 5744 | |
9ee2a2d4 MR |
5745 | if (HAVE_32BIT_GPRS) |
5746 | normalize_constant_expr (ex); | |
252b5132 RH |
5747 | } |
5748 | ||
5749 | /* Count the leading zeroes by performing a binary chop. This is a | |
5750 | bulky bit of source, but performance is a LOT better for the | |
5751 | majority of values than a simple loop to count the bits: | |
5752 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5753 | if ((v) & (1 << (31 - lcnt))) | |
5754 | break; | |
5755 | However it is not code size friendly, and the gain will drop a bit | |
5756 | on certain cached systems. | |
5757 | */ | |
5758 | #define COUNT_TOP_ZEROES(v) \ | |
5759 | (((v) & ~0xffff) == 0 \ | |
5760 | ? ((v) & ~0xff) == 0 \ | |
5761 | ? ((v) & ~0xf) == 0 \ | |
5762 | ? ((v) & ~0x3) == 0 \ | |
5763 | ? ((v) & ~0x1) == 0 \ | |
5764 | ? !(v) \ | |
5765 | ? 32 \ | |
5766 | : 31 \ | |
5767 | : 30 \ | |
5768 | : ((v) & ~0x7) == 0 \ | |
5769 | ? 29 \ | |
5770 | : 28 \ | |
5771 | : ((v) & ~0x3f) == 0 \ | |
5772 | ? ((v) & ~0x1f) == 0 \ | |
5773 | ? 27 \ | |
5774 | : 26 \ | |
5775 | : ((v) & ~0x7f) == 0 \ | |
5776 | ? 25 \ | |
5777 | : 24 \ | |
5778 | : ((v) & ~0xfff) == 0 \ | |
5779 | ? ((v) & ~0x3ff) == 0 \ | |
5780 | ? ((v) & ~0x1ff) == 0 \ | |
5781 | ? 23 \ | |
5782 | : 22 \ | |
5783 | : ((v) & ~0x7ff) == 0 \ | |
5784 | ? 21 \ | |
5785 | : 20 \ | |
5786 | : ((v) & ~0x3fff) == 0 \ | |
5787 | ? ((v) & ~0x1fff) == 0 \ | |
5788 | ? 19 \ | |
5789 | : 18 \ | |
5790 | : ((v) & ~0x7fff) == 0 \ | |
5791 | ? 17 \ | |
5792 | : 16 \ | |
5793 | : ((v) & ~0xffffff) == 0 \ | |
5794 | ? ((v) & ~0xfffff) == 0 \ | |
5795 | ? ((v) & ~0x3ffff) == 0 \ | |
5796 | ? ((v) & ~0x1ffff) == 0 \ | |
5797 | ? 15 \ | |
5798 | : 14 \ | |
5799 | : ((v) & ~0x7ffff) == 0 \ | |
5800 | ? 13 \ | |
5801 | : 12 \ | |
5802 | : ((v) & ~0x3fffff) == 0 \ | |
5803 | ? ((v) & ~0x1fffff) == 0 \ | |
5804 | ? 11 \ | |
5805 | : 10 \ | |
5806 | : ((v) & ~0x7fffff) == 0 \ | |
5807 | ? 9 \ | |
5808 | : 8 \ | |
5809 | : ((v) & ~0xfffffff) == 0 \ | |
5810 | ? ((v) & ~0x3ffffff) == 0 \ | |
5811 | ? ((v) & ~0x1ffffff) == 0 \ | |
5812 | ? 7 \ | |
5813 | : 6 \ | |
5814 | : ((v) & ~0x7ffffff) == 0 \ | |
5815 | ? 5 \ | |
5816 | : 4 \ | |
5817 | : ((v) & ~0x3fffffff) == 0 \ | |
5818 | ? ((v) & ~0x1fffffff) == 0 \ | |
5819 | ? 3 \ | |
5820 | : 2 \ | |
5821 | : ((v) & ~0x7fffffff) == 0 \ | |
5822 | ? 1 \ | |
5823 | : 0) | |
5824 | ||
5825 | /* load_register() | |
67c1ffbe | 5826 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5827 | * an absolute expression value into a register. |
5828 | */ | |
5829 | static void | |
67c0d1eb | 5830 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5831 | { |
5832 | int freg; | |
5833 | expressionS hi32, lo32; | |
5834 | ||
5835 | if (ep->X_op != O_big) | |
5836 | { | |
9c2799c2 | 5837 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5838 | |
5839 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5840 | if (!dbl) |
5841 | normalize_constant_expr (ep); | |
256ab948 TS |
5842 | |
5843 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5844 | { |
5845 | /* We can handle 16 bit signed values with an addiu to | |
5846 | $zero. No need to ever use daddiu here, since $zero and | |
5847 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5848 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5849 | return; |
5850 | } | |
5851 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5852 | { | |
5853 | /* We can handle 16 bit unsigned values with an ori to | |
5854 | $zero. */ | |
67c0d1eb | 5855 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5856 | return; |
5857 | } | |
256ab948 | 5858 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5859 | { |
5860 | /* 32 bit values require an lui. */ | |
df58fc94 | 5861 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5862 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5863 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5864 | return; |
5865 | } | |
5866 | } | |
5867 | ||
5868 | /* The value is larger than 32 bits. */ | |
5869 | ||
2051e8c4 | 5870 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5871 | { |
55e08f71 NC |
5872 | char value[32]; |
5873 | ||
5874 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5875 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5876 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5877 | return; |
5878 | } | |
5879 | ||
5880 | if (ep->X_op != O_big) | |
5881 | { | |
5882 | hi32 = *ep; | |
5883 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5884 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5885 | hi32.X_add_number &= 0xffffffff; | |
5886 | lo32 = *ep; | |
5887 | lo32.X_add_number &= 0xffffffff; | |
5888 | } | |
5889 | else | |
5890 | { | |
9c2799c2 | 5891 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5892 | if (ep->X_add_number == 3) |
5893 | generic_bignum[3] = 0; | |
5894 | else if (ep->X_add_number > 4) | |
5895 | as_bad (_("Number larger than 64 bits")); | |
5896 | lo32.X_op = O_constant; | |
5897 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5898 | hi32.X_op = O_constant; | |
5899 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5900 | } | |
5901 | ||
5902 | if (hi32.X_add_number == 0) | |
5903 | freg = 0; | |
5904 | else | |
5905 | { | |
5906 | int shift, bit; | |
5907 | unsigned long hi, lo; | |
5908 | ||
956cd1d6 | 5909 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5910 | { |
5911 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5912 | { | |
67c0d1eb | 5913 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5914 | return; |
5915 | } | |
5916 | if (lo32.X_add_number & 0x80000000) | |
5917 | { | |
df58fc94 | 5918 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5919 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5920 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5921 | return; |
5922 | } | |
5923 | } | |
252b5132 RH |
5924 | |
5925 | /* Check for 16bit shifted constant. We know that hi32 is | |
5926 | non-zero, so start the mask on the first bit of the hi32 | |
5927 | value. */ | |
5928 | shift = 17; | |
5929 | do | |
beae10d5 KH |
5930 | { |
5931 | unsigned long himask, lomask; | |
5932 | ||
5933 | if (shift < 32) | |
5934 | { | |
5935 | himask = 0xffff >> (32 - shift); | |
5936 | lomask = (0xffff << shift) & 0xffffffff; | |
5937 | } | |
5938 | else | |
5939 | { | |
5940 | himask = 0xffff << (shift - 32); | |
5941 | lomask = 0; | |
5942 | } | |
5943 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5944 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5945 | { | |
5946 | expressionS tmp; | |
5947 | ||
5948 | tmp.X_op = O_constant; | |
5949 | if (shift < 32) | |
5950 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5951 | | (lo32.X_add_number >> shift)); | |
5952 | else | |
5953 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5954 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5955 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5956 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5957 | return; |
5958 | } | |
f9419b05 | 5959 | ++shift; |
beae10d5 KH |
5960 | } |
5961 | while (shift <= (64 - 16)); | |
252b5132 RH |
5962 | |
5963 | /* Find the bit number of the lowest one bit, and store the | |
5964 | shifted value in hi/lo. */ | |
5965 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5966 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5967 | if (lo != 0) | |
5968 | { | |
5969 | bit = 0; | |
5970 | while ((lo & 1) == 0) | |
5971 | { | |
5972 | lo >>= 1; | |
5973 | ++bit; | |
5974 | } | |
5975 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5976 | hi >>= bit; | |
5977 | } | |
5978 | else | |
5979 | { | |
5980 | bit = 32; | |
5981 | while ((hi & 1) == 0) | |
5982 | { | |
5983 | hi >>= 1; | |
5984 | ++bit; | |
5985 | } | |
5986 | lo = hi; | |
5987 | hi = 0; | |
5988 | } | |
5989 | ||
5990 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5991 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5992 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5993 | { |
5994 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5995 | if (shift != 0) |
beae10d5 | 5996 | { |
252b5132 RH |
5997 | expressionS tmp; |
5998 | ||
5999 | /* This instruction will set the register to be all | |
6000 | ones. */ | |
beae10d5 KH |
6001 | tmp.X_op = O_constant; |
6002 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 6003 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6004 | if (bit != 0) |
6005 | { | |
6006 | bit += shift; | |
df58fc94 | 6007 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6008 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 6009 | } |
df58fc94 | 6010 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 6011 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6012 | return; |
6013 | } | |
6014 | } | |
252b5132 RH |
6015 | |
6016 | /* Sign extend hi32 before calling load_register, because we can | |
6017 | generally get better code when we load a sign extended value. */ | |
6018 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 6019 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 6020 | load_register (reg, &hi32, 0); |
252b5132 RH |
6021 | freg = reg; |
6022 | } | |
6023 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
6024 | { | |
6025 | if (freg != 0) | |
6026 | { | |
df58fc94 | 6027 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
6028 | freg = reg; |
6029 | } | |
6030 | } | |
6031 | else | |
6032 | { | |
6033 | expressionS mid16; | |
6034 | ||
956cd1d6 | 6035 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 6036 | { |
df58fc94 RS |
6037 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
6038 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
6039 | return; |
6040 | } | |
252b5132 RH |
6041 | |
6042 | if (freg != 0) | |
6043 | { | |
df58fc94 | 6044 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
6045 | freg = reg; |
6046 | } | |
6047 | mid16 = lo32; | |
6048 | mid16.X_add_number >>= 16; | |
67c0d1eb | 6049 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 6050 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
6051 | freg = reg; |
6052 | } | |
6053 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 6054 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
6055 | } |
6056 | ||
269137b2 TS |
6057 | static inline void |
6058 | load_delay_nop (void) | |
6059 | { | |
6060 | if (!gpr_interlocks) | |
6061 | macro_build (NULL, "nop", ""); | |
6062 | } | |
6063 | ||
252b5132 RH |
6064 | /* Load an address into a register. */ |
6065 | ||
6066 | static void | |
67c0d1eb | 6067 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 6068 | { |
252b5132 RH |
6069 | if (ep->X_op != O_constant |
6070 | && ep->X_op != O_symbol) | |
6071 | { | |
6072 | as_bad (_("expression too complex")); | |
6073 | ep->X_op = O_constant; | |
6074 | } | |
6075 | ||
6076 | if (ep->X_op == O_constant) | |
6077 | { | |
67c0d1eb | 6078 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
6079 | return; |
6080 | } | |
6081 | ||
6082 | if (mips_pic == NO_PIC) | |
6083 | { | |
6084 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 6085 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
6086 | Otherwise we want |
6087 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
6088 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 6089 | If we have an addend, we always use the latter form. |
76b3015f | 6090 | |
d6bc6245 TS |
6091 | With 64bit address space and a usable $at we want |
6092 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6093 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6094 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6095 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
6096 | dsll32 $reg,0 | |
3a482fd5 | 6097 | daddu $reg,$reg,$at |
76b3015f | 6098 | |
c03099e6 | 6099 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
6100 | on superscalar processors. |
6101 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6102 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6103 | dsll $reg,16 | |
6104 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
6105 | dsll $reg,16 | |
6106 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
6107 | |
6108 | For GP relative symbols in 64bit address space we can use | |
6109 | the same sequence as in 32bit address space. */ | |
aed1a261 | 6110 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 6111 | { |
6caf9ef4 TS |
6112 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6113 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
6114 | { | |
6115 | relax_start (ep->X_add_symbol); | |
6116 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
6117 | mips_gp_register, BFD_RELOC_GPREL16); | |
6118 | relax_switch (); | |
6119 | } | |
d6bc6245 | 6120 | |
741fe287 | 6121 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 6122 | { |
df58fc94 RS |
6123 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
6124 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
6125 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6126 | BFD_RELOC_MIPS_HIGHER); | |
6127 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 6128 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 6129 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
6130 | *used_at = 1; |
6131 | } | |
6132 | else | |
6133 | { | |
df58fc94 | 6134 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
6135 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6136 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 6137 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6138 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 6139 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6140 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 6141 | } |
6caf9ef4 TS |
6142 | |
6143 | if (mips_relax.sequence) | |
6144 | relax_end (); | |
d6bc6245 | 6145 | } |
252b5132 RH |
6146 | else |
6147 | { | |
d6bc6245 | 6148 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6149 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 6150 | { |
4d7206a2 | 6151 | relax_start (ep->X_add_symbol); |
67c0d1eb | 6152 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 6153 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6154 | relax_switch (); |
d6bc6245 | 6155 | } |
67c0d1eb RS |
6156 | macro_build_lui (ep, reg); |
6157 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6158 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6159 | if (mips_relax.sequence) |
6160 | relax_end (); | |
d6bc6245 | 6161 | } |
252b5132 | 6162 | } |
0a44bf69 | 6163 | else if (!mips_big_got) |
252b5132 RH |
6164 | { |
6165 | expressionS ex; | |
6166 | ||
6167 | /* If this is a reference to an external symbol, we want | |
6168 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6169 | Otherwise we want | |
6170 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6171 | nop | |
6172 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6173 | If there is a constant, it must be added in after. |
6174 | ||
ed6fb7bd | 6175 | If we have NewABI, we want |
f5040a92 AO |
6176 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6177 | unless we're referencing a global symbol with a non-zero | |
6178 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6179 | if (HAVE_NEWABI) |
6180 | { | |
f5040a92 AO |
6181 | if (ep->X_add_number) |
6182 | { | |
4d7206a2 | 6183 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6184 | ep->X_add_number = 0; |
4d7206a2 | 6185 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6186 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6187 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6188 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6189 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6190 | ex.X_op = O_constant; | |
67c0d1eb | 6191 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6192 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6193 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6194 | relax_switch (); |
f5040a92 | 6195 | } |
67c0d1eb | 6196 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6197 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6198 | if (mips_relax.sequence) |
6199 | relax_end (); | |
ed6fb7bd SC |
6200 | } |
6201 | else | |
6202 | { | |
f5040a92 AO |
6203 | ex.X_add_number = ep->X_add_number; |
6204 | ep->X_add_number = 0; | |
67c0d1eb RS |
6205 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6206 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6207 | load_delay_nop (); |
4d7206a2 RS |
6208 | relax_start (ep->X_add_symbol); |
6209 | relax_switch (); | |
67c0d1eb | 6210 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6211 | BFD_RELOC_LO16); |
4d7206a2 | 6212 | relax_end (); |
ed6fb7bd | 6213 | |
f5040a92 AO |
6214 | if (ex.X_add_number != 0) |
6215 | { | |
6216 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6217 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6218 | ex.X_op = O_constant; | |
67c0d1eb | 6219 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6220 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6221 | } |
252b5132 RH |
6222 | } |
6223 | } | |
0a44bf69 | 6224 | else if (mips_big_got) |
252b5132 RH |
6225 | { |
6226 | expressionS ex; | |
252b5132 RH |
6227 | |
6228 | /* This is the large GOT case. If this is a reference to an | |
6229 | external symbol, we want | |
6230 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6231 | addu $reg,$reg,$gp | |
6232 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6233 | |
6234 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6235 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6236 | nop | |
6237 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6238 | If there is a constant, it must be added in after. |
f5040a92 AO |
6239 | |
6240 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6241 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6242 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6243 | */ |
438c16b8 TS |
6244 | if (HAVE_NEWABI) |
6245 | { | |
4d7206a2 | 6246 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6247 | ep->X_add_number = 0; |
4d7206a2 | 6248 | relax_start (ep->X_add_symbol); |
df58fc94 | 6249 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6251 | reg, reg, mips_gp_register); | |
6252 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6253 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6254 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6255 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6256 | else if (ex.X_add_number) | |
6257 | { | |
6258 | ex.X_op = O_constant; | |
67c0d1eb RS |
6259 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6260 | BFD_RELOC_LO16); | |
f5040a92 AO |
6261 | } |
6262 | ||
6263 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6264 | relax_switch (); |
67c0d1eb | 6265 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6266 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6267 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6268 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6269 | relax_end (); |
438c16b8 | 6270 | } |
252b5132 | 6271 | else |
438c16b8 | 6272 | { |
f5040a92 AO |
6273 | ex.X_add_number = ep->X_add_number; |
6274 | ep->X_add_number = 0; | |
4d7206a2 | 6275 | relax_start (ep->X_add_symbol); |
df58fc94 | 6276 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6277 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6278 | reg, reg, mips_gp_register); | |
6279 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6280 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6281 | relax_switch (); |
6282 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6283 | { |
6284 | /* We need a nop before loading from $gp. This special | |
6285 | check is required because the lui which starts the main | |
6286 | instruction stream does not refer to $gp, and so will not | |
6287 | insert the nop which may be required. */ | |
67c0d1eb | 6288 | macro_build (NULL, "nop", ""); |
438c16b8 | 6289 | } |
67c0d1eb | 6290 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6291 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6292 | load_delay_nop (); |
67c0d1eb | 6293 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6294 | BFD_RELOC_LO16); |
4d7206a2 | 6295 | relax_end (); |
438c16b8 | 6296 | |
f5040a92 AO |
6297 | if (ex.X_add_number != 0) |
6298 | { | |
6299 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6300 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6301 | ex.X_op = O_constant; | |
67c0d1eb RS |
6302 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6303 | BFD_RELOC_LO16); | |
f5040a92 | 6304 | } |
252b5132 RH |
6305 | } |
6306 | } | |
252b5132 RH |
6307 | else |
6308 | abort (); | |
8fc2e39e | 6309 | |
741fe287 | 6310 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6311 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6312 | } |
6313 | ||
ea1fb5dc RS |
6314 | /* Move the contents of register SOURCE into register DEST. */ |
6315 | ||
6316 | static void | |
67c0d1eb | 6317 | move_register (int dest, int source) |
ea1fb5dc | 6318 | { |
df58fc94 RS |
6319 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6320 | instruction specifically requires a 32-bit one. */ | |
6321 | if (mips_opts.micromips | |
6322 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 6323 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6324 | else |
6325 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6326 | dest, source, 0); | |
ea1fb5dc RS |
6327 | } |
6328 | ||
4d7206a2 | 6329 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6330 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6331 | The two alternatives are: | |
4d7206a2 RS |
6332 | |
6333 | Global symbol Local sybmol | |
6334 | ------------- ------------ | |
6335 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6336 | ... ... | |
6337 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6338 | ||
6339 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6340 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6341 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6342 | |
6343 | static void | |
67c0d1eb | 6344 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6345 | { |
6346 | expressionS global; | |
6347 | ||
6348 | global = *local; | |
6349 | global.X_add_number = 0; | |
6350 | ||
6351 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6352 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6353 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6354 | relax_switch (); |
67c0d1eb RS |
6355 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6356 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6357 | relax_end (); |
6358 | } | |
6359 | ||
6360 | static void | |
67c0d1eb | 6361 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6362 | { |
6363 | expressionS global; | |
6364 | ||
6365 | global.X_op = O_constant; | |
6366 | global.X_op_symbol = NULL; | |
6367 | global.X_add_symbol = NULL; | |
6368 | global.X_add_number = local->X_add_number; | |
6369 | ||
6370 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6371 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6372 | dest, dest, BFD_RELOC_LO16); |
6373 | relax_switch (); | |
67c0d1eb | 6374 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6375 | relax_end (); |
6376 | } | |
6377 | ||
f6a22291 MR |
6378 | static void |
6379 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6380 | { | |
6381 | expressionS global; | |
6382 | int hold_mips_optimize; | |
6383 | ||
6384 | global.X_op = O_constant; | |
6385 | global.X_op_symbol = NULL; | |
6386 | global.X_add_symbol = NULL; | |
6387 | global.X_add_number = local->X_add_number; | |
6388 | ||
6389 | relax_start (local->X_add_symbol); | |
6390 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6391 | relax_switch (); | |
6392 | /* Set mips_optimize around the lui instruction to avoid | |
6393 | inserting an unnecessary nop after the lw. */ | |
6394 | hold_mips_optimize = mips_optimize; | |
6395 | mips_optimize = 2; | |
6396 | macro_build_lui (&global, tmp); | |
6397 | mips_optimize = hold_mips_optimize; | |
6398 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6399 | relax_end (); | |
6400 | ||
6401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6402 | } | |
6403 | ||
df58fc94 RS |
6404 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6405 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6406 | is its complementing branch with the original condition negated. | |
6407 | CALL is set if the original branch specified the link operation. | |
6408 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6409 | ||
6410 | Code like this is produced in the noreorder mode: | |
6411 | ||
6412 | BRNEG <args>, 1f | |
6413 | nop | |
6414 | b <sym> | |
6415 | delay slot (executed only if branch taken) | |
6416 | 1: | |
6417 | ||
6418 | or, if CALL is set: | |
6419 | ||
6420 | BRNEG <args>, 1f | |
6421 | nop | |
6422 | bal <sym> | |
6423 | delay slot (executed only if branch taken) | |
6424 | 1: | |
6425 | ||
6426 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6427 | so code produced is simply: | |
6428 | ||
6429 | BR <args>, <sym> | |
6430 | nop | |
6431 | ||
6432 | This function is used when producing code for the microMIPS ASE that | |
6433 | does not implement branch likely instructions in hardware. */ | |
6434 | ||
6435 | static void | |
6436 | macro_build_branch_likely (const char *br, const char *brneg, | |
6437 | int call, expressionS *ep, const char *fmt, | |
6438 | unsigned int sreg, unsigned int treg) | |
6439 | { | |
6440 | int noreorder = mips_opts.noreorder; | |
6441 | expressionS expr1; | |
6442 | ||
6443 | gas_assert (mips_opts.micromips); | |
6444 | start_noreorder (); | |
6445 | if (noreorder) | |
6446 | { | |
6447 | micromips_label_expr (&expr1); | |
6448 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6449 | macro_build (NULL, "nop", ""); | |
6450 | macro_build (ep, call ? "bal" : "b", "p"); | |
6451 | ||
6452 | /* Set to true so that append_insn adds a label. */ | |
6453 | emit_branch_likely_macro = TRUE; | |
6454 | } | |
6455 | else | |
6456 | { | |
6457 | macro_build (ep, br, fmt, sreg, treg); | |
6458 | macro_build (NULL, "nop", ""); | |
6459 | } | |
6460 | end_noreorder (); | |
6461 | } | |
6462 | ||
6463 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6464 | the condition code tested. EP specifies the branch target. */ | |
6465 | ||
6466 | static void | |
6467 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6468 | { | |
6469 | const int call = 0; | |
6470 | const char *brneg; | |
6471 | const char *br; | |
6472 | ||
6473 | switch (type) | |
6474 | { | |
6475 | case M_BC1FL: | |
6476 | br = "bc1f"; | |
6477 | brneg = "bc1t"; | |
6478 | break; | |
6479 | case M_BC1TL: | |
6480 | br = "bc1t"; | |
6481 | brneg = "bc1f"; | |
6482 | break; | |
6483 | case M_BC2FL: | |
6484 | br = "bc2f"; | |
6485 | brneg = "bc2t"; | |
6486 | break; | |
6487 | case M_BC2TL: | |
6488 | br = "bc2t"; | |
6489 | brneg = "bc2f"; | |
6490 | break; | |
6491 | default: | |
6492 | abort (); | |
6493 | } | |
6494 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6495 | } | |
6496 | ||
6497 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6498 | the register tested. EP specifies the branch target. */ | |
6499 | ||
6500 | static void | |
6501 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6502 | { | |
6503 | const char *brneg = NULL; | |
6504 | const char *br; | |
6505 | int call = 0; | |
6506 | ||
6507 | switch (type) | |
6508 | { | |
6509 | case M_BGEZ: | |
6510 | br = "bgez"; | |
6511 | break; | |
6512 | case M_BGEZL: | |
6513 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6514 | brneg = "bltz"; | |
6515 | break; | |
6516 | case M_BGEZALL: | |
6517 | gas_assert (mips_opts.micromips); | |
6518 | br = "bgezals"; | |
6519 | brneg = "bltz"; | |
6520 | call = 1; | |
6521 | break; | |
6522 | case M_BGTZ: | |
6523 | br = "bgtz"; | |
6524 | break; | |
6525 | case M_BGTZL: | |
6526 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6527 | brneg = "blez"; | |
6528 | break; | |
6529 | case M_BLEZ: | |
6530 | br = "blez"; | |
6531 | break; | |
6532 | case M_BLEZL: | |
6533 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6534 | brneg = "bgtz"; | |
6535 | break; | |
6536 | case M_BLTZ: | |
6537 | br = "bltz"; | |
6538 | break; | |
6539 | case M_BLTZL: | |
6540 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6541 | brneg = "bgez"; | |
6542 | break; | |
6543 | case M_BLTZALL: | |
6544 | gas_assert (mips_opts.micromips); | |
6545 | br = "bltzals"; | |
6546 | brneg = "bgez"; | |
6547 | call = 1; | |
6548 | break; | |
6549 | default: | |
6550 | abort (); | |
6551 | } | |
6552 | if (mips_opts.micromips && brneg) | |
6553 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6554 | else | |
6555 | macro_build (ep, br, "s,p", sreg); | |
6556 | } | |
6557 | ||
6558 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6559 | TREG as the registers tested. EP specifies the branch target. */ | |
6560 | ||
6561 | static void | |
6562 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6563 | unsigned int sreg, unsigned int treg) | |
6564 | { | |
6565 | const char *brneg = NULL; | |
6566 | const int call = 0; | |
6567 | const char *br; | |
6568 | ||
6569 | switch (type) | |
6570 | { | |
6571 | case M_BEQ: | |
6572 | case M_BEQ_I: | |
6573 | br = "beq"; | |
6574 | break; | |
6575 | case M_BEQL: | |
6576 | case M_BEQL_I: | |
6577 | br = mips_opts.micromips ? "beq" : "beql"; | |
6578 | brneg = "bne"; | |
6579 | break; | |
6580 | case M_BNE: | |
6581 | case M_BNE_I: | |
6582 | br = "bne"; | |
6583 | break; | |
6584 | case M_BNEL: | |
6585 | case M_BNEL_I: | |
6586 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6587 | brneg = "beq"; | |
6588 | break; | |
6589 | default: | |
6590 | abort (); | |
6591 | } | |
6592 | if (mips_opts.micromips && brneg) | |
6593 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6594 | else | |
6595 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6596 | } | |
6597 | ||
252b5132 RH |
6598 | /* |
6599 | * Build macros | |
6600 | * This routine implements the seemingly endless macro or synthesized | |
6601 | * instructions and addressing modes in the mips assembly language. Many | |
6602 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6603 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6604 | * this verbose method. Others are not simple macros but are more like |
6605 | * optimizing code generation. | |
6606 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6607 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6608 | * The ensuing load upper instructions are ommited. This implies some kind |
6609 | * of global optimization. We currently only optimize within a single macro. | |
6610 | * For many of the load and store macros if the address is specified as a | |
6611 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6612 | * first load register 'at' with zero and use it as the base register. The | |
6613 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6614 | * we're missing. | |
6615 | */ | |
6616 | static void | |
17a2f251 | 6617 | macro (struct mips_cl_insn *ip) |
252b5132 | 6618 | { |
741fe287 MR |
6619 | unsigned int treg, sreg, dreg, breg; |
6620 | unsigned int tempreg; | |
252b5132 | 6621 | int mask; |
43841e91 | 6622 | int used_at = 0; |
df58fc94 | 6623 | expressionS label_expr; |
252b5132 | 6624 | expressionS expr1; |
df58fc94 | 6625 | expressionS *ep; |
252b5132 RH |
6626 | const char *s; |
6627 | const char *s2; | |
6628 | const char *fmt; | |
6629 | int likely = 0; | |
252b5132 | 6630 | int coproc = 0; |
7f3c4072 | 6631 | int offbits = 16; |
1abe91b1 | 6632 | int call = 0; |
df58fc94 RS |
6633 | int jals = 0; |
6634 | int dbl = 0; | |
6635 | int imm = 0; | |
6636 | int ust = 0; | |
6637 | int lp = 0; | |
6638 | int ab = 0; | |
252b5132 | 6639 | int off; |
67c0d1eb | 6640 | offsetT maxnum; |
252b5132 | 6641 | bfd_reloc_code_real_type r; |
252b5132 RH |
6642 | int hold_mips_optimize; |
6643 | ||
9c2799c2 | 6644 | gas_assert (! mips_opts.mips16); |
252b5132 | 6645 | |
df58fc94 RS |
6646 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6647 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6648 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6649 | mask = ip->insn_mo->mask; |
6650 | ||
df58fc94 RS |
6651 | label_expr.X_op = O_constant; |
6652 | label_expr.X_op_symbol = NULL; | |
6653 | label_expr.X_add_symbol = NULL; | |
6654 | label_expr.X_add_number = 0; | |
6655 | ||
252b5132 RH |
6656 | expr1.X_op = O_constant; |
6657 | expr1.X_op_symbol = NULL; | |
6658 | expr1.X_add_symbol = NULL; | |
6659 | expr1.X_add_number = 1; | |
6660 | ||
6661 | switch (mask) | |
6662 | { | |
6663 | case M_DABS: | |
6664 | dbl = 1; | |
6665 | case M_ABS: | |
df58fc94 RS |
6666 | /* bgez $a0,1f |
6667 | move v0,$a0 | |
6668 | sub v0,$zero,$a0 | |
6669 | 1: | |
6670 | */ | |
252b5132 | 6671 | |
7d10b47d | 6672 | start_noreorder (); |
252b5132 | 6673 | |
df58fc94 RS |
6674 | if (mips_opts.micromips) |
6675 | micromips_label_expr (&label_expr); | |
6676 | else | |
6677 | label_expr.X_add_number = 8; | |
6678 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6679 | if (dreg == sreg) |
a605d2b3 | 6680 | macro_build (NULL, "nop", ""); |
252b5132 | 6681 | else |
67c0d1eb RS |
6682 | move_register (dreg, sreg); |
6683 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6684 | if (mips_opts.micromips) |
6685 | micromips_add_label (); | |
252b5132 | 6686 | |
7d10b47d | 6687 | end_noreorder (); |
8fc2e39e | 6688 | break; |
252b5132 RH |
6689 | |
6690 | case M_ADD_I: | |
6691 | s = "addi"; | |
6692 | s2 = "add"; | |
6693 | goto do_addi; | |
6694 | case M_ADDU_I: | |
6695 | s = "addiu"; | |
6696 | s2 = "addu"; | |
6697 | goto do_addi; | |
6698 | case M_DADD_I: | |
6699 | dbl = 1; | |
6700 | s = "daddi"; | |
6701 | s2 = "dadd"; | |
df58fc94 RS |
6702 | if (!mips_opts.micromips) |
6703 | goto do_addi; | |
6704 | if (imm_expr.X_op == O_constant | |
6705 | && imm_expr.X_add_number >= -0x200 | |
6706 | && imm_expr.X_add_number < 0x200) | |
6707 | { | |
6708 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6709 | break; | |
6710 | } | |
6711 | goto do_addi_i; | |
252b5132 RH |
6712 | case M_DADDU_I: |
6713 | dbl = 1; | |
6714 | s = "daddiu"; | |
6715 | s2 = "daddu"; | |
6716 | do_addi: | |
6717 | if (imm_expr.X_op == O_constant | |
6718 | && imm_expr.X_add_number >= -0x8000 | |
6719 | && imm_expr.X_add_number < 0x8000) | |
6720 | { | |
67c0d1eb | 6721 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6722 | break; |
252b5132 | 6723 | } |
df58fc94 | 6724 | do_addi_i: |
8fc2e39e | 6725 | used_at = 1; |
67c0d1eb RS |
6726 | load_register (AT, &imm_expr, dbl); |
6727 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6728 | break; |
6729 | ||
6730 | case M_AND_I: | |
6731 | s = "andi"; | |
6732 | s2 = "and"; | |
6733 | goto do_bit; | |
6734 | case M_OR_I: | |
6735 | s = "ori"; | |
6736 | s2 = "or"; | |
6737 | goto do_bit; | |
6738 | case M_NOR_I: | |
6739 | s = ""; | |
6740 | s2 = "nor"; | |
6741 | goto do_bit; | |
6742 | case M_XOR_I: | |
6743 | s = "xori"; | |
6744 | s2 = "xor"; | |
6745 | do_bit: | |
6746 | if (imm_expr.X_op == O_constant | |
6747 | && imm_expr.X_add_number >= 0 | |
6748 | && imm_expr.X_add_number < 0x10000) | |
6749 | { | |
6750 | if (mask != M_NOR_I) | |
67c0d1eb | 6751 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6752 | else |
6753 | { | |
67c0d1eb RS |
6754 | macro_build (&imm_expr, "ori", "t,r,i", |
6755 | treg, sreg, BFD_RELOC_LO16); | |
6756 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6757 | } |
8fc2e39e | 6758 | break; |
252b5132 RH |
6759 | } |
6760 | ||
8fc2e39e | 6761 | used_at = 1; |
67c0d1eb RS |
6762 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6763 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6764 | break; |
6765 | ||
8b082fb1 TS |
6766 | case M_BALIGN: |
6767 | switch (imm_expr.X_add_number) | |
6768 | { | |
6769 | case 0: | |
6770 | macro_build (NULL, "nop", ""); | |
6771 | break; | |
6772 | case 2: | |
6773 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6774 | break; | |
03f66e8a MR |
6775 | case 1: |
6776 | case 3: | |
8b082fb1 | 6777 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6778 | (int) imm_expr.X_add_number); |
8b082fb1 | 6779 | break; |
03f66e8a MR |
6780 | default: |
6781 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6782 | (unsigned long) imm_expr.X_add_number); | |
6783 | break; | |
8b082fb1 TS |
6784 | } |
6785 | break; | |
6786 | ||
df58fc94 RS |
6787 | case M_BC1FL: |
6788 | case M_BC1TL: | |
6789 | case M_BC2FL: | |
6790 | case M_BC2TL: | |
6791 | gas_assert (mips_opts.micromips); | |
6792 | macro_build_branch_ccl (mask, &offset_expr, | |
6793 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6794 | break; | |
6795 | ||
252b5132 | 6796 | case M_BEQ_I: |
252b5132 | 6797 | case M_BEQL_I: |
252b5132 | 6798 | case M_BNE_I: |
252b5132 | 6799 | case M_BNEL_I: |
252b5132 | 6800 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6801 | treg = 0; |
6802 | else | |
252b5132 | 6803 | { |
df58fc94 RS |
6804 | treg = AT; |
6805 | used_at = 1; | |
6806 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6807 | } |
df58fc94 RS |
6808 | /* Fall through. */ |
6809 | case M_BEQL: | |
6810 | case M_BNEL: | |
6811 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6812 | break; |
6813 | ||
6814 | case M_BGEL: | |
6815 | likely = 1; | |
6816 | case M_BGE: | |
6817 | if (treg == 0) | |
df58fc94 RS |
6818 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6819 | else if (sreg == 0) | |
6820 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6821 | else | |
252b5132 | 6822 | { |
df58fc94 RS |
6823 | used_at = 1; |
6824 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6825 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6826 | &offset_expr, AT, ZERO); | |
252b5132 | 6827 | } |
df58fc94 RS |
6828 | break; |
6829 | ||
6830 | case M_BGEZL: | |
6831 | case M_BGEZALL: | |
6832 | case M_BGTZL: | |
6833 | case M_BLEZL: | |
6834 | case M_BLTZL: | |
6835 | case M_BLTZALL: | |
6836 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6837 | break; |
6838 | ||
6839 | case M_BGTL_I: | |
6840 | likely = 1; | |
6841 | case M_BGT_I: | |
90ecf173 | 6842 | /* Check for > max integer. */ |
252b5132 | 6843 | maxnum = 0x7fffffff; |
ca4e0257 | 6844 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6845 | { |
6846 | maxnum <<= 16; | |
6847 | maxnum |= 0xffff; | |
6848 | maxnum <<= 16; | |
6849 | maxnum |= 0xffff; | |
6850 | } | |
6851 | if (imm_expr.X_op == O_constant | |
6852 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6853 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6854 | { |
6855 | do_false: | |
90ecf173 | 6856 | /* Result is always false. */ |
252b5132 | 6857 | if (! likely) |
a605d2b3 | 6858 | macro_build (NULL, "nop", ""); |
252b5132 | 6859 | else |
df58fc94 | 6860 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6861 | break; |
252b5132 RH |
6862 | } |
6863 | if (imm_expr.X_op != O_constant) | |
6864 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6865 | ++imm_expr.X_add_number; |
252b5132 RH |
6866 | /* FALLTHROUGH */ |
6867 | case M_BGE_I: | |
6868 | case M_BGEL_I: | |
6869 | if (mask == M_BGEL_I) | |
6870 | likely = 1; | |
6871 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6872 | { | |
df58fc94 RS |
6873 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6874 | &offset_expr, sreg); | |
8fc2e39e | 6875 | break; |
252b5132 RH |
6876 | } |
6877 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6878 | { | |
df58fc94 RS |
6879 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6880 | &offset_expr, sreg); | |
8fc2e39e | 6881 | break; |
252b5132 RH |
6882 | } |
6883 | maxnum = 0x7fffffff; | |
ca4e0257 | 6884 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6885 | { |
6886 | maxnum <<= 16; | |
6887 | maxnum |= 0xffff; | |
6888 | maxnum <<= 16; | |
6889 | maxnum |= 0xffff; | |
6890 | } | |
6891 | maxnum = - maxnum - 1; | |
6892 | if (imm_expr.X_op == O_constant | |
6893 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6894 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6895 | { |
6896 | do_true: | |
6897 | /* result is always true */ | |
6898 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6899 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6900 | break; |
252b5132 | 6901 | } |
8fc2e39e | 6902 | used_at = 1; |
67c0d1eb | 6903 | set_at (sreg, 0); |
df58fc94 RS |
6904 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6905 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6906 | break; |
6907 | ||
6908 | case M_BGEUL: | |
6909 | likely = 1; | |
6910 | case M_BGEU: | |
6911 | if (treg == 0) | |
6912 | goto do_true; | |
df58fc94 RS |
6913 | else if (sreg == 0) |
6914 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6915 | &offset_expr, ZERO, treg); | |
6916 | else | |
252b5132 | 6917 | { |
df58fc94 RS |
6918 | used_at = 1; |
6919 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6920 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6921 | &offset_expr, AT, ZERO); | |
252b5132 | 6922 | } |
252b5132 RH |
6923 | break; |
6924 | ||
6925 | case M_BGTUL_I: | |
6926 | likely = 1; | |
6927 | case M_BGTU_I: | |
6928 | if (sreg == 0 | |
ca4e0257 | 6929 | || (HAVE_32BIT_GPRS |
252b5132 | 6930 | && imm_expr.X_op == O_constant |
f01dc953 | 6931 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6932 | goto do_false; |
6933 | if (imm_expr.X_op != O_constant) | |
6934 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6935 | ++imm_expr.X_add_number; |
252b5132 RH |
6936 | /* FALLTHROUGH */ |
6937 | case M_BGEU_I: | |
6938 | case M_BGEUL_I: | |
6939 | if (mask == M_BGEUL_I) | |
6940 | likely = 1; | |
6941 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6942 | goto do_true; | |
df58fc94 RS |
6943 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6944 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6945 | &offset_expr, sreg, ZERO); | |
6946 | else | |
252b5132 | 6947 | { |
df58fc94 RS |
6948 | used_at = 1; |
6949 | set_at (sreg, 1); | |
6950 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6951 | &offset_expr, AT, ZERO); | |
252b5132 | 6952 | } |
252b5132 RH |
6953 | break; |
6954 | ||
6955 | case M_BGTL: | |
6956 | likely = 1; | |
6957 | case M_BGT: | |
6958 | if (treg == 0) | |
df58fc94 RS |
6959 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6960 | else if (sreg == 0) | |
6961 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6962 | else | |
252b5132 | 6963 | { |
df58fc94 RS |
6964 | used_at = 1; |
6965 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6966 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6967 | &offset_expr, AT, ZERO); | |
252b5132 | 6968 | } |
252b5132 RH |
6969 | break; |
6970 | ||
6971 | case M_BGTUL: | |
6972 | likely = 1; | |
6973 | case M_BGTU: | |
6974 | if (treg == 0) | |
df58fc94 RS |
6975 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6976 | &offset_expr, sreg, ZERO); | |
6977 | else if (sreg == 0) | |
6978 | goto do_false; | |
6979 | else | |
252b5132 | 6980 | { |
df58fc94 RS |
6981 | used_at = 1; |
6982 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6983 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6984 | &offset_expr, AT, ZERO); | |
252b5132 | 6985 | } |
252b5132 RH |
6986 | break; |
6987 | ||
6988 | case M_BLEL: | |
6989 | likely = 1; | |
6990 | case M_BLE: | |
6991 | if (treg == 0) | |
df58fc94 RS |
6992 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6993 | else if (sreg == 0) | |
6994 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6995 | else | |
252b5132 | 6996 | { |
df58fc94 RS |
6997 | used_at = 1; |
6998 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6999 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7000 | &offset_expr, AT, ZERO); | |
252b5132 | 7001 | } |
252b5132 RH |
7002 | break; |
7003 | ||
7004 | case M_BLEL_I: | |
7005 | likely = 1; | |
7006 | case M_BLE_I: | |
7007 | maxnum = 0x7fffffff; | |
ca4e0257 | 7008 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
7009 | { |
7010 | maxnum <<= 16; | |
7011 | maxnum |= 0xffff; | |
7012 | maxnum <<= 16; | |
7013 | maxnum |= 0xffff; | |
7014 | } | |
7015 | if (imm_expr.X_op == O_constant | |
7016 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 7017 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
7018 | goto do_true; |
7019 | if (imm_expr.X_op != O_constant) | |
7020 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7021 | ++imm_expr.X_add_number; |
252b5132 RH |
7022 | /* FALLTHROUGH */ |
7023 | case M_BLT_I: | |
7024 | case M_BLTL_I: | |
7025 | if (mask == M_BLTL_I) | |
7026 | likely = 1; | |
7027 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
7028 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7029 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7030 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
7031 | else | |
252b5132 | 7032 | { |
df58fc94 RS |
7033 | used_at = 1; |
7034 | set_at (sreg, 0); | |
7035 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7036 | &offset_expr, AT, ZERO); | |
252b5132 | 7037 | } |
252b5132 RH |
7038 | break; |
7039 | ||
7040 | case M_BLEUL: | |
7041 | likely = 1; | |
7042 | case M_BLEU: | |
7043 | if (treg == 0) | |
df58fc94 RS |
7044 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7045 | &offset_expr, sreg, ZERO); | |
7046 | else if (sreg == 0) | |
7047 | goto do_true; | |
7048 | else | |
252b5132 | 7049 | { |
df58fc94 RS |
7050 | used_at = 1; |
7051 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7052 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7053 | &offset_expr, AT, ZERO); | |
252b5132 | 7054 | } |
252b5132 RH |
7055 | break; |
7056 | ||
7057 | case M_BLEUL_I: | |
7058 | likely = 1; | |
7059 | case M_BLEU_I: | |
7060 | if (sreg == 0 | |
ca4e0257 | 7061 | || (HAVE_32BIT_GPRS |
252b5132 | 7062 | && imm_expr.X_op == O_constant |
f01dc953 | 7063 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7064 | goto do_true; |
7065 | if (imm_expr.X_op != O_constant) | |
7066 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7067 | ++imm_expr.X_add_number; |
252b5132 RH |
7068 | /* FALLTHROUGH */ |
7069 | case M_BLTU_I: | |
7070 | case M_BLTUL_I: | |
7071 | if (mask == M_BLTUL_I) | |
7072 | likely = 1; | |
7073 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7074 | goto do_false; | |
df58fc94 RS |
7075 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7076 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7077 | &offset_expr, sreg, ZERO); | |
7078 | else | |
252b5132 | 7079 | { |
df58fc94 RS |
7080 | used_at = 1; |
7081 | set_at (sreg, 1); | |
7082 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7083 | &offset_expr, AT, ZERO); | |
252b5132 | 7084 | } |
252b5132 RH |
7085 | break; |
7086 | ||
7087 | case M_BLTL: | |
7088 | likely = 1; | |
7089 | case M_BLT: | |
7090 | if (treg == 0) | |
df58fc94 RS |
7091 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7092 | else if (sreg == 0) | |
7093 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
7094 | else | |
252b5132 | 7095 | { |
df58fc94 RS |
7096 | used_at = 1; |
7097 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7098 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7099 | &offset_expr, AT, ZERO); | |
252b5132 | 7100 | } |
252b5132 RH |
7101 | break; |
7102 | ||
7103 | case M_BLTUL: | |
7104 | likely = 1; | |
7105 | case M_BLTU: | |
7106 | if (treg == 0) | |
7107 | goto do_false; | |
df58fc94 RS |
7108 | else if (sreg == 0) |
7109 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7110 | &offset_expr, ZERO, treg); | |
7111 | else | |
252b5132 | 7112 | { |
df58fc94 RS |
7113 | used_at = 1; |
7114 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7115 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7116 | &offset_expr, AT, ZERO); | |
252b5132 | 7117 | } |
252b5132 RH |
7118 | break; |
7119 | ||
5f74bc13 CD |
7120 | case M_DEXT: |
7121 | { | |
d5818fca MR |
7122 | /* Use unsigned arithmetic. */ |
7123 | addressT pos; | |
7124 | addressT size; | |
5f74bc13 | 7125 | |
90ecf173 | 7126 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7127 | { |
7128 | as_bad (_("Unsupported large constant")); | |
7129 | pos = size = 1; | |
7130 | } | |
7131 | else | |
7132 | { | |
d5818fca MR |
7133 | pos = imm_expr.X_add_number; |
7134 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7135 | } |
7136 | ||
7137 | if (pos > 63) | |
7138 | { | |
d5818fca | 7139 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7140 | pos = 1; |
7141 | } | |
90ecf173 | 7142 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7143 | { |
7144 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 7145 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7146 | size = 1; |
7147 | } | |
7148 | ||
7149 | if (size <= 32 && pos < 32) | |
7150 | { | |
7151 | s = "dext"; | |
7152 | fmt = "t,r,+A,+C"; | |
7153 | } | |
7154 | else if (size <= 32) | |
7155 | { | |
7156 | s = "dextu"; | |
7157 | fmt = "t,r,+E,+H"; | |
7158 | } | |
7159 | else | |
7160 | { | |
7161 | s = "dextm"; | |
7162 | fmt = "t,r,+A,+G"; | |
7163 | } | |
d5818fca MR |
7164 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7165 | (int) (size - 1)); | |
5f74bc13 | 7166 | } |
8fc2e39e | 7167 | break; |
5f74bc13 CD |
7168 | |
7169 | case M_DINS: | |
7170 | { | |
d5818fca MR |
7171 | /* Use unsigned arithmetic. */ |
7172 | addressT pos; | |
7173 | addressT size; | |
5f74bc13 | 7174 | |
90ecf173 | 7175 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7176 | { |
7177 | as_bad (_("Unsupported large constant")); | |
7178 | pos = size = 1; | |
7179 | } | |
7180 | else | |
7181 | { | |
d5818fca MR |
7182 | pos = imm_expr.X_add_number; |
7183 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7184 | } |
7185 | ||
7186 | if (pos > 63) | |
7187 | { | |
d5818fca | 7188 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7189 | pos = 1; |
7190 | } | |
90ecf173 | 7191 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7192 | { |
7193 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7194 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7195 | size = 1; |
7196 | } | |
7197 | ||
7198 | if (pos < 32 && (pos + size - 1) < 32) | |
7199 | { | |
7200 | s = "dins"; | |
7201 | fmt = "t,r,+A,+B"; | |
7202 | } | |
7203 | else if (pos >= 32) | |
7204 | { | |
7205 | s = "dinsu"; | |
7206 | fmt = "t,r,+E,+F"; | |
7207 | } | |
7208 | else | |
7209 | { | |
7210 | s = "dinsm"; | |
7211 | fmt = "t,r,+A,+F"; | |
7212 | } | |
750bdd57 AS |
7213 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7214 | (int) (pos + size - 1)); | |
5f74bc13 | 7215 | } |
8fc2e39e | 7216 | break; |
5f74bc13 | 7217 | |
252b5132 RH |
7218 | case M_DDIV_3: |
7219 | dbl = 1; | |
7220 | case M_DIV_3: | |
7221 | s = "mflo"; | |
7222 | goto do_div3; | |
7223 | case M_DREM_3: | |
7224 | dbl = 1; | |
7225 | case M_REM_3: | |
7226 | s = "mfhi"; | |
7227 | do_div3: | |
7228 | if (treg == 0) | |
7229 | { | |
7230 | as_warn (_("Divide by zero.")); | |
7231 | if (mips_trap) | |
df58fc94 | 7232 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7233 | else |
df58fc94 | 7234 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7235 | break; |
252b5132 RH |
7236 | } |
7237 | ||
7d10b47d | 7238 | start_noreorder (); |
252b5132 RH |
7239 | if (mips_trap) |
7240 | { | |
df58fc94 | 7241 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7242 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7243 | } |
7244 | else | |
7245 | { | |
df58fc94 RS |
7246 | if (mips_opts.micromips) |
7247 | micromips_label_expr (&label_expr); | |
7248 | else | |
7249 | label_expr.X_add_number = 8; | |
7250 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7251 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7252 | macro_build (NULL, "break", BRK_FMT, 7); |
7253 | if (mips_opts.micromips) | |
7254 | micromips_add_label (); | |
252b5132 RH |
7255 | } |
7256 | expr1.X_add_number = -1; | |
8fc2e39e | 7257 | used_at = 1; |
f6a22291 | 7258 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7259 | if (mips_opts.micromips) |
7260 | micromips_label_expr (&label_expr); | |
7261 | else | |
7262 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7263 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7264 | if (dbl) |
7265 | { | |
7266 | expr1.X_add_number = 1; | |
f6a22291 | 7267 | load_register (AT, &expr1, dbl); |
df58fc94 | 7268 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7269 | } |
7270 | else | |
7271 | { | |
7272 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7273 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7274 | } |
7275 | if (mips_trap) | |
7276 | { | |
df58fc94 | 7277 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7278 | /* We want to close the noreorder block as soon as possible, so |
7279 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7280 | end_noreorder (); |
252b5132 RH |
7281 | } |
7282 | else | |
7283 | { | |
df58fc94 RS |
7284 | if (mips_opts.micromips) |
7285 | micromips_label_expr (&label_expr); | |
7286 | else | |
7287 | label_expr.X_add_number = 8; | |
7288 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7289 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7290 | |
7291 | /* We want to close the noreorder block as soon as possible, so | |
7292 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7293 | end_noreorder (); |
252b5132 | 7294 | |
df58fc94 | 7295 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7296 | } |
df58fc94 RS |
7297 | if (mips_opts.micromips) |
7298 | micromips_add_label (); | |
7299 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7300 | break; |
7301 | ||
7302 | case M_DIV_3I: | |
7303 | s = "div"; | |
7304 | s2 = "mflo"; | |
7305 | goto do_divi; | |
7306 | case M_DIVU_3I: | |
7307 | s = "divu"; | |
7308 | s2 = "mflo"; | |
7309 | goto do_divi; | |
7310 | case M_REM_3I: | |
7311 | s = "div"; | |
7312 | s2 = "mfhi"; | |
7313 | goto do_divi; | |
7314 | case M_REMU_3I: | |
7315 | s = "divu"; | |
7316 | s2 = "mfhi"; | |
7317 | goto do_divi; | |
7318 | case M_DDIV_3I: | |
7319 | dbl = 1; | |
7320 | s = "ddiv"; | |
7321 | s2 = "mflo"; | |
7322 | goto do_divi; | |
7323 | case M_DDIVU_3I: | |
7324 | dbl = 1; | |
7325 | s = "ddivu"; | |
7326 | s2 = "mflo"; | |
7327 | goto do_divi; | |
7328 | case M_DREM_3I: | |
7329 | dbl = 1; | |
7330 | s = "ddiv"; | |
7331 | s2 = "mfhi"; | |
7332 | goto do_divi; | |
7333 | case M_DREMU_3I: | |
7334 | dbl = 1; | |
7335 | s = "ddivu"; | |
7336 | s2 = "mfhi"; | |
7337 | do_divi: | |
7338 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7339 | { | |
7340 | as_warn (_("Divide by zero.")); | |
7341 | if (mips_trap) | |
df58fc94 | 7342 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7343 | else |
df58fc94 | 7344 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7345 | break; |
252b5132 RH |
7346 | } |
7347 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7348 | { | |
7349 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7350 | move_register (dreg, sreg); |
252b5132 | 7351 | else |
c80c840e | 7352 | move_register (dreg, ZERO); |
8fc2e39e | 7353 | break; |
252b5132 RH |
7354 | } |
7355 | if (imm_expr.X_op == O_constant | |
7356 | && imm_expr.X_add_number == -1 | |
7357 | && s[strlen (s) - 1] != 'u') | |
7358 | { | |
7359 | if (strcmp (s2, "mflo") == 0) | |
7360 | { | |
67c0d1eb | 7361 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7362 | } |
7363 | else | |
c80c840e | 7364 | move_register (dreg, ZERO); |
8fc2e39e | 7365 | break; |
252b5132 RH |
7366 | } |
7367 | ||
8fc2e39e | 7368 | used_at = 1; |
67c0d1eb RS |
7369 | load_register (AT, &imm_expr, dbl); |
7370 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7371 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7372 | break; |
7373 | ||
7374 | case M_DIVU_3: | |
7375 | s = "divu"; | |
7376 | s2 = "mflo"; | |
7377 | goto do_divu3; | |
7378 | case M_REMU_3: | |
7379 | s = "divu"; | |
7380 | s2 = "mfhi"; | |
7381 | goto do_divu3; | |
7382 | case M_DDIVU_3: | |
7383 | s = "ddivu"; | |
7384 | s2 = "mflo"; | |
7385 | goto do_divu3; | |
7386 | case M_DREMU_3: | |
7387 | s = "ddivu"; | |
7388 | s2 = "mfhi"; | |
7389 | do_divu3: | |
7d10b47d | 7390 | start_noreorder (); |
252b5132 RH |
7391 | if (mips_trap) |
7392 | { | |
df58fc94 | 7393 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7394 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7395 | /* We want to close the noreorder block as soon as possible, so |
7396 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7397 | end_noreorder (); |
252b5132 RH |
7398 | } |
7399 | else | |
7400 | { | |
df58fc94 RS |
7401 | if (mips_opts.micromips) |
7402 | micromips_label_expr (&label_expr); | |
7403 | else | |
7404 | label_expr.X_add_number = 8; | |
7405 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7406 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7407 | |
7408 | /* We want to close the noreorder block as soon as possible, so | |
7409 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7410 | end_noreorder (); |
df58fc94 RS |
7411 | macro_build (NULL, "break", BRK_FMT, 7); |
7412 | if (mips_opts.micromips) | |
7413 | micromips_add_label (); | |
252b5132 | 7414 | } |
df58fc94 | 7415 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7416 | break; |
252b5132 | 7417 | |
1abe91b1 MR |
7418 | case M_DLCA_AB: |
7419 | dbl = 1; | |
7420 | case M_LCA_AB: | |
7421 | call = 1; | |
7422 | goto do_la; | |
252b5132 RH |
7423 | case M_DLA_AB: |
7424 | dbl = 1; | |
7425 | case M_LA_AB: | |
1abe91b1 | 7426 | do_la: |
252b5132 RH |
7427 | /* Load the address of a symbol into a register. If breg is not |
7428 | zero, we then add a base register to it. */ | |
7429 | ||
3bec30a8 TS |
7430 | if (dbl && HAVE_32BIT_GPRS) |
7431 | as_warn (_("dla used to load 32-bit register")); | |
7432 | ||
90ecf173 | 7433 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7434 | as_warn (_("la used to load 64-bit address")); |
7435 | ||
0c11417f MR |
7436 | if (offset_expr.X_op == O_constant |
7437 | && offset_expr.X_add_number >= -0x8000 | |
7438 | && offset_expr.X_add_number < 0x8000) | |
7439 | { | |
aed1a261 | 7440 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7441 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7442 | break; |
0c11417f MR |
7443 | } |
7444 | ||
741fe287 | 7445 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7446 | { |
7447 | tempreg = AT; | |
7448 | used_at = 1; | |
7449 | } | |
7450 | else | |
7451 | { | |
7452 | tempreg = treg; | |
afdbd6d0 CD |
7453 | } |
7454 | ||
252b5132 RH |
7455 | if (offset_expr.X_op != O_symbol |
7456 | && offset_expr.X_op != O_constant) | |
7457 | { | |
f71d0d44 | 7458 | as_bad (_("Expression too complex")); |
252b5132 RH |
7459 | offset_expr.X_op = O_constant; |
7460 | } | |
7461 | ||
252b5132 | 7462 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7463 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7464 | else if (mips_pic == NO_PIC) |
7465 | { | |
d6bc6245 | 7466 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7467 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7468 | Otherwise we want |
7469 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7470 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7471 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7472 | so we may as well always use the latter form. |
76b3015f | 7473 | |
6caf9ef4 TS |
7474 | With 64bit address space and a usable $at we want |
7475 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7476 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7477 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7478 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7479 | dsll32 $tempreg,0 | |
7480 | daddu $tempreg,$tempreg,$at | |
7481 | ||
7482 | If $at is already in use, we use a path which is suboptimal | |
7483 | on superscalar processors. | |
7484 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7485 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7486 | dsll $tempreg,16 | |
7487 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7488 | dsll $tempreg,16 | |
7489 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7490 | ||
7491 | For GP relative symbols in 64bit address space we can use | |
7492 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7493 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7494 | { |
6caf9ef4 TS |
7495 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7496 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7497 | { | |
7498 | relax_start (offset_expr.X_add_symbol); | |
7499 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7500 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7501 | relax_switch (); | |
7502 | } | |
d6bc6245 | 7503 | |
741fe287 | 7504 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7505 | { |
df58fc94 | 7506 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7507 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7508 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7509 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7510 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7511 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7512 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7513 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7514 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7515 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7516 | used_at = 1; |
7517 | } | |
7518 | else | |
7519 | { | |
df58fc94 | 7520 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7521 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7522 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7523 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7524 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7525 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7526 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7527 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7528 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7529 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7530 | } |
6caf9ef4 TS |
7531 | |
7532 | if (mips_relax.sequence) | |
7533 | relax_end (); | |
98d3f06f KH |
7534 | } |
7535 | else | |
7536 | { | |
7537 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7538 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7539 | { |
4d7206a2 | 7540 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7541 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7542 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7543 | relax_switch (); |
98d3f06f | 7544 | } |
6943caf0 | 7545 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7546 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7547 | macro_build_lui (&offset_expr, tempreg); |
7548 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7549 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7550 | if (mips_relax.sequence) |
7551 | relax_end (); | |
98d3f06f | 7552 | } |
252b5132 | 7553 | } |
0a44bf69 | 7554 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7555 | { |
9117d219 NC |
7556 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7557 | ||
252b5132 RH |
7558 | /* If this is a reference to an external symbol, and there |
7559 | is no constant, we want | |
7560 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7561 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7562 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7563 | For a local symbol, we want |
7564 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7565 | nop | |
7566 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7567 | ||
7568 | If we have a small constant, and this is a reference to | |
7569 | an external symbol, we want | |
7570 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7571 | nop | |
7572 | addiu $tempreg,$tempreg,<constant> | |
7573 | For a local symbol, we want the same instruction | |
7574 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7575 | addiu instruction. | |
7576 | ||
7577 | If we have a large constant, and this is a reference to | |
7578 | an external symbol, we want | |
7579 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7580 | lui $at,<hiconstant> | |
7581 | addiu $at,$at,<loconstant> | |
7582 | addu $tempreg,$tempreg,$at | |
7583 | For a local symbol, we want the same instruction | |
7584 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7585 | addiu instruction. |
ed6fb7bd SC |
7586 | */ |
7587 | ||
4d7206a2 | 7588 | if (offset_expr.X_add_number == 0) |
252b5132 | 7589 | { |
0a44bf69 RS |
7590 | if (mips_pic == SVR4_PIC |
7591 | && breg == 0 | |
7592 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7593 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7594 | ||
7595 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7596 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7597 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7598 | if (breg != 0) |
252b5132 RH |
7599 | { |
7600 | /* We're going to put in an addu instruction using | |
7601 | tempreg, so we may as well insert the nop right | |
7602 | now. */ | |
269137b2 | 7603 | load_delay_nop (); |
252b5132 | 7604 | } |
4d7206a2 | 7605 | relax_switch (); |
67c0d1eb RS |
7606 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7607 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7608 | load_delay_nop (); |
67c0d1eb RS |
7609 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7610 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7611 | relax_end (); |
252b5132 RH |
7612 | /* FIXME: If breg == 0, and the next instruction uses |
7613 | $tempreg, then if this variant case is used an extra | |
7614 | nop will be generated. */ | |
7615 | } | |
4d7206a2 RS |
7616 | else if (offset_expr.X_add_number >= -0x8000 |
7617 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7618 | { |
67c0d1eb | 7619 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7620 | load_delay_nop (); |
67c0d1eb | 7621 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7622 | } |
7623 | else | |
7624 | { | |
4d7206a2 RS |
7625 | expr1.X_add_number = offset_expr.X_add_number; |
7626 | offset_expr.X_add_number = | |
43c0598f | 7627 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7628 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7629 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7630 | /* If we are going to add in a base register, and the |
7631 | target register and the base register are the same, | |
7632 | then we are using AT as a temporary register. Since | |
7633 | we want to load the constant into AT, we add our | |
7634 | current AT (from the global offset table) and the | |
7635 | register into the register now, and pretend we were | |
7636 | not using a base register. */ | |
67c0d1eb | 7637 | if (breg == treg) |
252b5132 | 7638 | { |
269137b2 | 7639 | load_delay_nop (); |
67c0d1eb | 7640 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7641 | treg, AT, breg); |
252b5132 RH |
7642 | breg = 0; |
7643 | tempreg = treg; | |
252b5132 | 7644 | } |
f6a22291 | 7645 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7646 | used_at = 1; |
7647 | } | |
7648 | } | |
0a44bf69 | 7649 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7650 | { |
67c0d1eb | 7651 | int add_breg_early = 0; |
f5040a92 AO |
7652 | |
7653 | /* If this is a reference to an external, and there is no | |
7654 | constant, or local symbol (*), with or without a | |
7655 | constant, we want | |
7656 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7657 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7658 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7659 | ||
7660 | If we have a small constant, and this is a reference to | |
7661 | an external symbol, we want | |
7662 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7663 | addiu $tempreg,$tempreg,<constant> | |
7664 | ||
7665 | If we have a large constant, and this is a reference to | |
7666 | an external symbol, we want | |
7667 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7668 | lui $at,<hiconstant> | |
7669 | addiu $at,$at,<loconstant> | |
7670 | addu $tempreg,$tempreg,$at | |
7671 | ||
7672 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7673 | local symbols, even though it introduces an additional | |
7674 | instruction. */ | |
7675 | ||
f5040a92 AO |
7676 | if (offset_expr.X_add_number) |
7677 | { | |
4d7206a2 | 7678 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7679 | offset_expr.X_add_number = 0; |
7680 | ||
4d7206a2 | 7681 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7682 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7683 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7684 | |
7685 | if (expr1.X_add_number >= -0x8000 | |
7686 | && expr1.X_add_number < 0x8000) | |
7687 | { | |
67c0d1eb RS |
7688 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7689 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7690 | } |
ecd13cd3 | 7691 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7692 | { |
f5040a92 AO |
7693 | /* If we are going to add in a base register, and the |
7694 | target register and the base register are the same, | |
7695 | then we are using AT as a temporary register. Since | |
7696 | we want to load the constant into AT, we add our | |
7697 | current AT (from the global offset table) and the | |
7698 | register into the register now, and pretend we were | |
7699 | not using a base register. */ | |
7700 | if (breg != treg) | |
7701 | dreg = tempreg; | |
7702 | else | |
7703 | { | |
9c2799c2 | 7704 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7705 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7706 | treg, AT, breg); | |
f5040a92 | 7707 | dreg = treg; |
67c0d1eb | 7708 | add_breg_early = 1; |
f5040a92 AO |
7709 | } |
7710 | ||
f6a22291 | 7711 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7712 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7713 | dreg, dreg, AT); |
f5040a92 | 7714 | |
f5040a92 AO |
7715 | used_at = 1; |
7716 | } | |
7717 | else | |
7718 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7719 | ||
4d7206a2 | 7720 | relax_switch (); |
f5040a92 AO |
7721 | offset_expr.X_add_number = expr1.X_add_number; |
7722 | ||
67c0d1eb RS |
7723 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7724 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7725 | if (add_breg_early) | |
f5040a92 | 7726 | { |
67c0d1eb | 7727 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7728 | treg, tempreg, breg); |
f5040a92 AO |
7729 | breg = 0; |
7730 | tempreg = treg; | |
7731 | } | |
4d7206a2 | 7732 | relax_end (); |
f5040a92 | 7733 | } |
4d7206a2 | 7734 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7735 | { |
4d7206a2 | 7736 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7737 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7738 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7739 | relax_switch (); |
67c0d1eb RS |
7740 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7741 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7742 | relax_end (); |
f5040a92 | 7743 | } |
4d7206a2 | 7744 | else |
f5040a92 | 7745 | { |
67c0d1eb RS |
7746 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7747 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7748 | } |
7749 | } | |
0a44bf69 | 7750 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7751 | { |
67c0d1eb | 7752 | int gpdelay; |
9117d219 NC |
7753 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7754 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7755 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7756 | |
7757 | /* This is the large GOT case. If this is a reference to an | |
7758 | external symbol, and there is no constant, we want | |
7759 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7760 | addu $tempreg,$tempreg,$gp | |
7761 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7762 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7763 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7764 | addu $tempreg,$tempreg,$gp | |
7765 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7766 | For a local symbol, we want |
7767 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7768 | nop | |
7769 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7770 | ||
7771 | If we have a small constant, and this is a reference to | |
7772 | an external symbol, we want | |
7773 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7774 | addu $tempreg,$tempreg,$gp | |
7775 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7776 | nop | |
7777 | addiu $tempreg,$tempreg,<constant> | |
7778 | For a local symbol, we want | |
7779 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7780 | nop | |
7781 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7782 | ||
7783 | If we have a large constant, and this is a reference to | |
7784 | an external symbol, we want | |
7785 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7786 | addu $tempreg,$tempreg,$gp | |
7787 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7788 | lui $at,<hiconstant> | |
7789 | addiu $at,$at,<loconstant> | |
7790 | addu $tempreg,$tempreg,$at | |
7791 | For a local symbol, we want | |
7792 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7793 | lui $at,<hiconstant> | |
7794 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7795 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7796 | */ |
438c16b8 | 7797 | |
252b5132 RH |
7798 | expr1.X_add_number = offset_expr.X_add_number; |
7799 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7800 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7801 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7802 | if (expr1.X_add_number == 0 && breg == 0 |
7803 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7804 | { |
7805 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7806 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7807 | } | |
df58fc94 | 7808 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7809 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7810 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7811 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7812 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7813 | if (expr1.X_add_number == 0) |
7814 | { | |
67c0d1eb | 7815 | if (breg != 0) |
252b5132 RH |
7816 | { |
7817 | /* We're going to put in an addu instruction using | |
7818 | tempreg, so we may as well insert the nop right | |
7819 | now. */ | |
269137b2 | 7820 | load_delay_nop (); |
252b5132 | 7821 | } |
252b5132 RH |
7822 | } |
7823 | else if (expr1.X_add_number >= -0x8000 | |
7824 | && expr1.X_add_number < 0x8000) | |
7825 | { | |
269137b2 | 7826 | load_delay_nop (); |
67c0d1eb | 7827 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7828 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7829 | } |
7830 | else | |
7831 | { | |
252b5132 RH |
7832 | /* If we are going to add in a base register, and the |
7833 | target register and the base register are the same, | |
7834 | then we are using AT as a temporary register. Since | |
7835 | we want to load the constant into AT, we add our | |
7836 | current AT (from the global offset table) and the | |
7837 | register into the register now, and pretend we were | |
7838 | not using a base register. */ | |
7839 | if (breg != treg) | |
67c0d1eb | 7840 | dreg = tempreg; |
252b5132 RH |
7841 | else |
7842 | { | |
9c2799c2 | 7843 | gas_assert (tempreg == AT); |
269137b2 | 7844 | load_delay_nop (); |
67c0d1eb | 7845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7846 | treg, AT, breg); |
252b5132 | 7847 | dreg = treg; |
252b5132 RH |
7848 | } |
7849 | ||
f6a22291 | 7850 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7851 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7852 | |
252b5132 RH |
7853 | used_at = 1; |
7854 | } | |
43c0598f | 7855 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7856 | relax_switch (); |
252b5132 | 7857 | |
67c0d1eb | 7858 | if (gpdelay) |
252b5132 RH |
7859 | { |
7860 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7861 | the first instruction on the main stream does not. */ |
67c0d1eb | 7862 | macro_build (NULL, "nop", ""); |
252b5132 | 7863 | } |
ed6fb7bd | 7864 | |
67c0d1eb RS |
7865 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7866 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7867 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7868 | && expr1.X_add_number < 0x8000) |
7869 | { | |
269137b2 | 7870 | load_delay_nop (); |
67c0d1eb RS |
7871 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7872 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7873 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7874 | register, the external symbol case ended with a load, |
7875 | so if the symbol turns out to not be external, and | |
7876 | the next instruction uses tempreg, an unnecessary nop | |
7877 | will be inserted. */ | |
252b5132 RH |
7878 | } |
7879 | else | |
7880 | { | |
7881 | if (breg == treg) | |
7882 | { | |
7883 | /* We must add in the base register now, as in the | |
f5040a92 | 7884 | external symbol case. */ |
9c2799c2 | 7885 | gas_assert (tempreg == AT); |
269137b2 | 7886 | load_delay_nop (); |
67c0d1eb | 7887 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7888 | treg, AT, breg); |
252b5132 RH |
7889 | tempreg = treg; |
7890 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7891 | it in in both cases. */ |
252b5132 RH |
7892 | breg = 0; |
7893 | } | |
7894 | ||
67c0d1eb RS |
7895 | macro_build_lui (&expr1, AT); |
7896 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7897 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7898 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7899 | tempreg, tempreg, AT); |
8fc2e39e | 7900 | used_at = 1; |
252b5132 | 7901 | } |
4d7206a2 | 7902 | relax_end (); |
252b5132 | 7903 | } |
0a44bf69 | 7904 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7905 | { |
f5040a92 AO |
7906 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7907 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7908 | int add_breg_early = 0; |
f5040a92 AO |
7909 | |
7910 | /* This is the large GOT case. If this is a reference to an | |
7911 | external symbol, and there is no constant, we want | |
7912 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7913 | add $tempreg,$tempreg,$gp | |
7914 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7915 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7916 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7917 | add $tempreg,$tempreg,$gp | |
7918 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7919 | ||
7920 | If we have a small constant, and this is a reference to | |
7921 | an external symbol, we want | |
7922 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7923 | add $tempreg,$tempreg,$gp | |
7924 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7925 | addi $tempreg,$tempreg,<constant> | |
7926 | ||
7927 | If we have a large constant, and this is a reference to | |
7928 | an external symbol, we want | |
7929 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7930 | addu $tempreg,$tempreg,$gp | |
7931 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7932 | lui $at,<hiconstant> | |
7933 | addi $at,$at,<loconstant> | |
7934 | add $tempreg,$tempreg,$at | |
7935 | ||
7936 | If we have NewABI, and we know it's a local symbol, we want | |
7937 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7938 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7939 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7940 | ||
4d7206a2 | 7941 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7942 | |
4d7206a2 | 7943 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7944 | offset_expr.X_add_number = 0; |
7945 | ||
1abe91b1 MR |
7946 | if (expr1.X_add_number == 0 && breg == 0 |
7947 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7948 | { |
7949 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7950 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7951 | } | |
df58fc94 | 7952 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7953 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7954 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7955 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7956 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7957 | |
7958 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7959 | ; |
f5040a92 AO |
7960 | else if (expr1.X_add_number >= -0x8000 |
7961 | && expr1.X_add_number < 0x8000) | |
7962 | { | |
67c0d1eb | 7963 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7964 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7965 | } |
ecd13cd3 | 7966 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7967 | { |
f5040a92 AO |
7968 | /* If we are going to add in a base register, and the |
7969 | target register and the base register are the same, | |
7970 | then we are using AT as a temporary register. Since | |
7971 | we want to load the constant into AT, we add our | |
7972 | current AT (from the global offset table) and the | |
7973 | register into the register now, and pretend we were | |
7974 | not using a base register. */ | |
7975 | if (breg != treg) | |
7976 | dreg = tempreg; | |
7977 | else | |
7978 | { | |
9c2799c2 | 7979 | gas_assert (tempreg == AT); |
67c0d1eb | 7980 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7981 | treg, AT, breg); |
f5040a92 | 7982 | dreg = treg; |
67c0d1eb | 7983 | add_breg_early = 1; |
f5040a92 AO |
7984 | } |
7985 | ||
f6a22291 | 7986 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7987 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7988 | |
f5040a92 AO |
7989 | used_at = 1; |
7990 | } | |
7991 | else | |
7992 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7993 | ||
4d7206a2 | 7994 | relax_switch (); |
f5040a92 | 7995 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7996 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7997 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7998 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7999 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
8000 | if (add_breg_early) | |
f5040a92 | 8001 | { |
67c0d1eb | 8002 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8003 | treg, tempreg, breg); |
f5040a92 AO |
8004 | breg = 0; |
8005 | tempreg = treg; | |
8006 | } | |
4d7206a2 | 8007 | relax_end (); |
f5040a92 | 8008 | } |
252b5132 RH |
8009 | else |
8010 | abort (); | |
8011 | ||
8012 | if (breg != 0) | |
aed1a261 | 8013 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
8014 | break; |
8015 | ||
52b6b6b9 | 8016 | case M_MSGSND: |
df58fc94 | 8017 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8018 | { |
8019 | unsigned long temp = (treg << 16) | (0x01); | |
8020 | macro_build (NULL, "c2", "C", temp); | |
8021 | } | |
c7af4273 | 8022 | break; |
52b6b6b9 JM |
8023 | |
8024 | case M_MSGLD: | |
df58fc94 | 8025 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8026 | { |
8027 | unsigned long temp = (0x02); | |
8028 | macro_build (NULL, "c2", "C", temp); | |
8029 | } | |
c7af4273 | 8030 | break; |
52b6b6b9 JM |
8031 | |
8032 | case M_MSGLD_T: | |
df58fc94 | 8033 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8034 | { |
8035 | unsigned long temp = (treg << 16) | (0x02); | |
8036 | macro_build (NULL, "c2", "C", temp); | |
8037 | } | |
c7af4273 | 8038 | break; |
52b6b6b9 JM |
8039 | |
8040 | case M_MSGWAIT: | |
df58fc94 | 8041 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 8042 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 8043 | break; |
52b6b6b9 JM |
8044 | |
8045 | case M_MSGWAIT_T: | |
df58fc94 | 8046 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8047 | { |
8048 | unsigned long temp = (treg << 16) | 0x03; | |
8049 | macro_build (NULL, "c2", "C", temp); | |
8050 | } | |
c7af4273 | 8051 | break; |
52b6b6b9 | 8052 | |
252b5132 RH |
8053 | case M_J_A: |
8054 | /* The j instruction may not be used in PIC code, since it | |
8055 | requires an absolute address. We convert it to a b | |
8056 | instruction. */ | |
8057 | if (mips_pic == NO_PIC) | |
67c0d1eb | 8058 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 8059 | else |
67c0d1eb | 8060 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 8061 | break; |
252b5132 RH |
8062 | |
8063 | /* The jal instructions must be handled as macros because when | |
8064 | generating PIC code they expand to multi-instruction | |
8065 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
8066 | case M_JALS_1: |
8067 | dreg = RA; | |
8068 | /* Fall through. */ | |
8069 | case M_JALS_2: | |
8070 | gas_assert (mips_opts.micromips); | |
8071 | jals = 1; | |
8072 | goto jal; | |
252b5132 RH |
8073 | case M_JAL_1: |
8074 | dreg = RA; | |
8075 | /* Fall through. */ | |
8076 | case M_JAL_2: | |
df58fc94 | 8077 | jal: |
3e722fb5 | 8078 | if (mips_pic == NO_PIC) |
df58fc94 RS |
8079 | { |
8080 | s = jals ? "jalrs" : "jalr"; | |
e64af278 MR |
8081 | if (mips_opts.micromips |
8082 | && dreg == RA | |
8083 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8084 | macro_build (NULL, s, "mj", sreg); |
8085 | else | |
8086 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
8087 | } | |
0a44bf69 | 8088 | else |
252b5132 | 8089 | { |
df58fc94 RS |
8090 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
8091 | && mips_cprestore_offset >= 0); | |
8092 | ||
252b5132 RH |
8093 | if (sreg != PIC_CALL_REG) |
8094 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 8095 | |
df58fc94 RS |
8096 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
8097 | ? "jalrs" : "jalr"); | |
e64af278 MR |
8098 | if (mips_opts.micromips |
8099 | && dreg == RA | |
8100 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8101 | macro_build (NULL, s, "mj", sreg); |
8102 | else | |
8103 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 8104 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 8105 | { |
6478892d TS |
8106 | if (mips_cprestore_offset < 0) |
8107 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8108 | else | |
8109 | { | |
90ecf173 | 8110 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8111 | { |
8112 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8113 | /* Quiet this warning. */ | |
8114 | mips_frame_reg_valid = 1; | |
8115 | } | |
90ecf173 | 8116 | if (!mips_cprestore_valid) |
7a621144 DJ |
8117 | { |
8118 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8119 | /* Quiet this warning. */ | |
8120 | mips_cprestore_valid = 1; | |
8121 | } | |
d3fca0b5 MR |
8122 | if (mips_opts.noreorder) |
8123 | macro_build (NULL, "nop", ""); | |
6478892d | 8124 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8125 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8126 | mips_gp_register, |
256ab948 TS |
8127 | mips_frame_reg, |
8128 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8129 | } |
252b5132 RH |
8130 | } |
8131 | } | |
252b5132 | 8132 | |
8fc2e39e | 8133 | break; |
252b5132 | 8134 | |
df58fc94 RS |
8135 | case M_JALS_A: |
8136 | gas_assert (mips_opts.micromips); | |
8137 | jals = 1; | |
8138 | /* Fall through. */ | |
252b5132 RH |
8139 | case M_JAL_A: |
8140 | if (mips_pic == NO_PIC) | |
df58fc94 | 8141 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
8142 | else if (mips_pic == SVR4_PIC) |
8143 | { | |
8144 | /* If this is a reference to an external symbol, and we are | |
8145 | using a small GOT, we want | |
8146 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
8147 | nop | |
f9419b05 | 8148 | jalr $ra,$25 |
252b5132 RH |
8149 | nop |
8150 | lw $gp,cprestore($sp) | |
8151 | The cprestore value is set using the .cprestore | |
8152 | pseudo-op. If we are using a big GOT, we want | |
8153 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8154 | addu $25,$25,$gp | |
8155 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8156 | nop | |
f9419b05 | 8157 | jalr $ra,$25 |
252b5132 RH |
8158 | nop |
8159 | lw $gp,cprestore($sp) | |
8160 | If the symbol is not external, we want | |
8161 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8162 | nop | |
8163 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8164 | jalr $ra,$25 |
252b5132 | 8165 | nop |
438c16b8 | 8166 | lw $gp,cprestore($sp) |
f5040a92 AO |
8167 | |
8168 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8169 | sequences above, minus nops, unless the symbol is local, | |
8170 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8171 | GOT_DISP. */ | |
438c16b8 | 8172 | if (HAVE_NEWABI) |
252b5132 | 8173 | { |
90ecf173 | 8174 | if (!mips_big_got) |
f5040a92 | 8175 | { |
4d7206a2 | 8176 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8177 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8178 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8179 | mips_gp_register); |
4d7206a2 | 8180 | relax_switch (); |
67c0d1eb RS |
8181 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8182 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8183 | mips_gp_register); |
8184 | relax_end (); | |
f5040a92 AO |
8185 | } |
8186 | else | |
8187 | { | |
4d7206a2 | 8188 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8189 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8190 | BFD_RELOC_MIPS_CALL_HI16); |
8191 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8192 | PIC_CALL_REG, mips_gp_register); | |
8193 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8194 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8195 | PIC_CALL_REG); | |
4d7206a2 | 8196 | relax_switch (); |
67c0d1eb RS |
8197 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8198 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8199 | mips_gp_register); | |
8200 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8201 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8202 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8203 | relax_end (); |
f5040a92 | 8204 | } |
684022ea | 8205 | |
df58fc94 | 8206 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8207 | } |
8208 | else | |
8209 | { | |
4d7206a2 | 8210 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8211 | if (!mips_big_got) |
438c16b8 | 8212 | { |
67c0d1eb RS |
8213 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8214 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8215 | mips_gp_register); |
269137b2 | 8216 | load_delay_nop (); |
4d7206a2 | 8217 | relax_switch (); |
438c16b8 | 8218 | } |
252b5132 | 8219 | else |
252b5132 | 8220 | { |
67c0d1eb RS |
8221 | int gpdelay; |
8222 | ||
8223 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8224 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8225 | BFD_RELOC_MIPS_CALL_HI16); |
8226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8227 | PIC_CALL_REG, mips_gp_register); | |
8228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8229 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8230 | PIC_CALL_REG); | |
269137b2 | 8231 | load_delay_nop (); |
4d7206a2 | 8232 | relax_switch (); |
67c0d1eb RS |
8233 | if (gpdelay) |
8234 | macro_build (NULL, "nop", ""); | |
252b5132 | 8235 | } |
67c0d1eb RS |
8236 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8237 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8238 | mips_gp_register); |
269137b2 | 8239 | load_delay_nop (); |
67c0d1eb RS |
8240 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8241 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8242 | relax_end (); |
df58fc94 | 8243 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8244 | |
6478892d TS |
8245 | if (mips_cprestore_offset < 0) |
8246 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8247 | else | |
8248 | { | |
90ecf173 | 8249 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8250 | { |
8251 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8252 | /* Quiet this warning. */ | |
8253 | mips_frame_reg_valid = 1; | |
8254 | } | |
90ecf173 | 8255 | if (!mips_cprestore_valid) |
7a621144 DJ |
8256 | { |
8257 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8258 | /* Quiet this warning. */ | |
8259 | mips_cprestore_valid = 1; | |
8260 | } | |
6478892d | 8261 | if (mips_opts.noreorder) |
67c0d1eb | 8262 | macro_build (NULL, "nop", ""); |
6478892d | 8263 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8264 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8265 | mips_gp_register, |
256ab948 TS |
8266 | mips_frame_reg, |
8267 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8268 | } |
252b5132 RH |
8269 | } |
8270 | } | |
0a44bf69 RS |
8271 | else if (mips_pic == VXWORKS_PIC) |
8272 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8273 | else |
8274 | abort (); | |
8275 | ||
8fc2e39e | 8276 | break; |
252b5132 | 8277 | |
7f3c4072 CM |
8278 | case M_LBUE_AB: |
8279 | ab = 1; | |
8280 | case M_LBUE_OB: | |
8281 | s = "lbue"; | |
8282 | fmt = "t,+j(b)"; | |
8283 | offbits = 9; | |
8284 | goto ld_st; | |
8285 | case M_LHUE_AB: | |
8286 | ab = 1; | |
8287 | case M_LHUE_OB: | |
8288 | s = "lhue"; | |
8289 | fmt = "t,+j(b)"; | |
8290 | offbits = 9; | |
8291 | goto ld_st; | |
8292 | case M_LBE_AB: | |
8293 | ab = 1; | |
8294 | case M_LBE_OB: | |
8295 | s = "lbe"; | |
8296 | fmt = "t,+j(b)"; | |
8297 | offbits = 9; | |
8298 | goto ld_st; | |
8299 | case M_LHE_AB: | |
8300 | ab = 1; | |
8301 | case M_LHE_OB: | |
8302 | s = "lhe"; | |
8303 | fmt = "t,+j(b)"; | |
8304 | offbits = 9; | |
8305 | goto ld_st; | |
8306 | case M_LLE_AB: | |
8307 | ab = 1; | |
8308 | case M_LLE_OB: | |
8309 | s = "lle"; | |
8310 | fmt = "t,+j(b)"; | |
8311 | offbits = 9; | |
8312 | goto ld_st; | |
8313 | case M_LWE_AB: | |
8314 | ab = 1; | |
8315 | case M_LWE_OB: | |
8316 | s = "lwe"; | |
8317 | fmt = "t,+j(b)"; | |
8318 | offbits = 9; | |
8319 | goto ld_st; | |
8320 | case M_LWLE_AB: | |
8321 | ab = 1; | |
8322 | case M_LWLE_OB: | |
8323 | s = "lwle"; | |
8324 | fmt = "t,+j(b)"; | |
8325 | offbits = 9; | |
8326 | goto ld_st; | |
8327 | case M_LWRE_AB: | |
8328 | ab = 1; | |
8329 | case M_LWRE_OB: | |
8330 | s = "lwre"; | |
8331 | fmt = "t,+j(b)"; | |
8332 | offbits = 9; | |
8333 | goto ld_st; | |
8334 | case M_SBE_AB: | |
8335 | ab = 1; | |
8336 | case M_SBE_OB: | |
8337 | s = "sbe"; | |
8338 | fmt = "t,+j(b)"; | |
8339 | offbits = 9; | |
8340 | goto ld_st; | |
8341 | case M_SCE_AB: | |
8342 | ab = 1; | |
8343 | case M_SCE_OB: | |
8344 | s = "sce"; | |
8345 | fmt = "t,+j(b)"; | |
8346 | offbits = 9; | |
8347 | goto ld_st; | |
8348 | case M_SHE_AB: | |
8349 | ab = 1; | |
8350 | case M_SHE_OB: | |
8351 | s = "she"; | |
8352 | fmt = "t,+j(b)"; | |
8353 | offbits = 9; | |
8354 | goto ld_st; | |
8355 | case M_SWE_AB: | |
8356 | ab = 1; | |
8357 | case M_SWE_OB: | |
8358 | s = "swe"; | |
8359 | fmt = "t,+j(b)"; | |
8360 | offbits = 9; | |
8361 | goto ld_st; | |
8362 | case M_SWLE_AB: | |
8363 | ab = 1; | |
8364 | case M_SWLE_OB: | |
8365 | s = "swle"; | |
8366 | fmt = "t,+j(b)"; | |
8367 | offbits = 9; | |
8368 | goto ld_st; | |
8369 | case M_SWRE_AB: | |
8370 | ab = 1; | |
8371 | case M_SWRE_OB: | |
8372 | s = "swre"; | |
8373 | fmt = "t,+j(b)"; | |
8374 | offbits = 9; | |
8375 | goto ld_st; | |
dec0624d MR |
8376 | case M_ACLR_AB: |
8377 | ab = 1; | |
8378 | case M_ACLR_OB: | |
8379 | s = "aclr"; | |
8380 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8381 | fmt = "\\,~(b)"; | |
7f3c4072 | 8382 | offbits = 12; |
dec0624d MR |
8383 | goto ld_st; |
8384 | case M_ASET_AB: | |
8385 | ab = 1; | |
8386 | case M_ASET_OB: | |
8387 | s = "aset"; | |
8388 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8389 | fmt = "\\,~(b)"; | |
7f3c4072 | 8390 | offbits = 12; |
dec0624d | 8391 | goto ld_st; |
252b5132 | 8392 | case M_LB_AB: |
df58fc94 | 8393 | ab = 1; |
252b5132 | 8394 | s = "lb"; |
df58fc94 | 8395 | fmt = "t,o(b)"; |
252b5132 RH |
8396 | goto ld; |
8397 | case M_LBU_AB: | |
df58fc94 | 8398 | ab = 1; |
252b5132 | 8399 | s = "lbu"; |
df58fc94 | 8400 | fmt = "t,o(b)"; |
252b5132 RH |
8401 | goto ld; |
8402 | case M_LH_AB: | |
df58fc94 | 8403 | ab = 1; |
252b5132 | 8404 | s = "lh"; |
df58fc94 | 8405 | fmt = "t,o(b)"; |
252b5132 RH |
8406 | goto ld; |
8407 | case M_LHU_AB: | |
df58fc94 | 8408 | ab = 1; |
252b5132 | 8409 | s = "lhu"; |
df58fc94 | 8410 | fmt = "t,o(b)"; |
252b5132 RH |
8411 | goto ld; |
8412 | case M_LW_AB: | |
df58fc94 | 8413 | ab = 1; |
252b5132 | 8414 | s = "lw"; |
df58fc94 | 8415 | fmt = "t,o(b)"; |
252b5132 RH |
8416 | goto ld; |
8417 | case M_LWC0_AB: | |
df58fc94 RS |
8418 | ab = 1; |
8419 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8420 | s = "lwc0"; |
df58fc94 | 8421 | fmt = "E,o(b)"; |
bdaaa2e1 | 8422 | /* Itbl support may require additional care here. */ |
252b5132 | 8423 | coproc = 1; |
df58fc94 | 8424 | goto ld_st; |
252b5132 | 8425 | case M_LWC1_AB: |
df58fc94 | 8426 | ab = 1; |
252b5132 | 8427 | s = "lwc1"; |
df58fc94 | 8428 | fmt = "T,o(b)"; |
bdaaa2e1 | 8429 | /* Itbl support may require additional care here. */ |
252b5132 | 8430 | coproc = 1; |
df58fc94 | 8431 | goto ld_st; |
252b5132 | 8432 | case M_LWC2_AB: |
df58fc94 RS |
8433 | ab = 1; |
8434 | case M_LWC2_OB: | |
252b5132 | 8435 | s = "lwc2"; |
df58fc94 | 8436 | fmt = COP12_FMT; |
7f3c4072 | 8437 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8438 | /* Itbl support may require additional care here. */ |
252b5132 | 8439 | coproc = 1; |
df58fc94 | 8440 | goto ld_st; |
252b5132 | 8441 | case M_LWC3_AB: |
df58fc94 RS |
8442 | ab = 1; |
8443 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8444 | s = "lwc3"; |
df58fc94 | 8445 | fmt = "E,o(b)"; |
bdaaa2e1 | 8446 | /* Itbl support may require additional care here. */ |
252b5132 | 8447 | coproc = 1; |
df58fc94 | 8448 | goto ld_st; |
252b5132 | 8449 | case M_LWL_AB: |
df58fc94 RS |
8450 | ab = 1; |
8451 | case M_LWL_OB: | |
252b5132 | 8452 | s = "lwl"; |
df58fc94 | 8453 | fmt = MEM12_FMT; |
7f3c4072 | 8454 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8455 | goto ld_st; |
252b5132 | 8456 | case M_LWR_AB: |
df58fc94 RS |
8457 | ab = 1; |
8458 | case M_LWR_OB: | |
252b5132 | 8459 | s = "lwr"; |
df58fc94 | 8460 | fmt = MEM12_FMT; |
7f3c4072 | 8461 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8462 | goto ld_st; |
252b5132 | 8463 | case M_LDC1_AB: |
df58fc94 | 8464 | ab = 1; |
252b5132 | 8465 | s = "ldc1"; |
df58fc94 | 8466 | fmt = "T,o(b)"; |
bdaaa2e1 | 8467 | /* Itbl support may require additional care here. */ |
252b5132 | 8468 | coproc = 1; |
df58fc94 | 8469 | goto ld_st; |
252b5132 | 8470 | case M_LDC2_AB: |
df58fc94 RS |
8471 | ab = 1; |
8472 | case M_LDC2_OB: | |
252b5132 | 8473 | s = "ldc2"; |
df58fc94 | 8474 | fmt = COP12_FMT; |
7f3c4072 | 8475 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8476 | /* Itbl support may require additional care here. */ |
252b5132 | 8477 | coproc = 1; |
df58fc94 | 8478 | goto ld_st; |
c77c0862 RS |
8479 | case M_LQC2_AB: |
8480 | ab = 1; | |
8481 | s = "lqc2"; | |
8482 | fmt = "E,o(b)"; | |
8483 | /* Itbl support may require additional care here. */ | |
8484 | coproc = 1; | |
8485 | goto ld_st; | |
252b5132 | 8486 | case M_LDC3_AB: |
df58fc94 | 8487 | ab = 1; |
252b5132 | 8488 | s = "ldc3"; |
df58fc94 | 8489 | fmt = "E,o(b)"; |
bdaaa2e1 | 8490 | /* Itbl support may require additional care here. */ |
252b5132 | 8491 | coproc = 1; |
df58fc94 | 8492 | goto ld_st; |
252b5132 | 8493 | case M_LDL_AB: |
df58fc94 RS |
8494 | ab = 1; |
8495 | case M_LDL_OB: | |
252b5132 | 8496 | s = "ldl"; |
df58fc94 | 8497 | fmt = MEM12_FMT; |
7f3c4072 | 8498 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8499 | goto ld_st; |
252b5132 | 8500 | case M_LDR_AB: |
df58fc94 RS |
8501 | ab = 1; |
8502 | case M_LDR_OB: | |
252b5132 | 8503 | s = "ldr"; |
df58fc94 | 8504 | fmt = MEM12_FMT; |
7f3c4072 | 8505 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8506 | goto ld_st; |
252b5132 | 8507 | case M_LL_AB: |
df58fc94 RS |
8508 | ab = 1; |
8509 | case M_LL_OB: | |
252b5132 | 8510 | s = "ll"; |
df58fc94 | 8511 | fmt = MEM12_FMT; |
7f3c4072 | 8512 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8513 | goto ld; |
8514 | case M_LLD_AB: | |
df58fc94 RS |
8515 | ab = 1; |
8516 | case M_LLD_OB: | |
252b5132 | 8517 | s = "lld"; |
df58fc94 | 8518 | fmt = MEM12_FMT; |
7f3c4072 | 8519 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8520 | goto ld; |
8521 | case M_LWU_AB: | |
df58fc94 RS |
8522 | ab = 1; |
8523 | case M_LWU_OB: | |
252b5132 | 8524 | s = "lwu"; |
df58fc94 | 8525 | fmt = MEM12_FMT; |
7f3c4072 | 8526 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8527 | goto ld; |
8528 | case M_LWP_AB: | |
8529 | ab = 1; | |
8530 | case M_LWP_OB: | |
8531 | gas_assert (mips_opts.micromips); | |
8532 | s = "lwp"; | |
8533 | fmt = "t,~(b)"; | |
7f3c4072 | 8534 | offbits = 12; |
df58fc94 RS |
8535 | lp = 1; |
8536 | goto ld; | |
8537 | case M_LDP_AB: | |
8538 | ab = 1; | |
8539 | case M_LDP_OB: | |
8540 | gas_assert (mips_opts.micromips); | |
8541 | s = "ldp"; | |
8542 | fmt = "t,~(b)"; | |
7f3c4072 | 8543 | offbits = 12; |
df58fc94 RS |
8544 | lp = 1; |
8545 | goto ld; | |
8546 | case M_LWM_AB: | |
8547 | ab = 1; | |
8548 | case M_LWM_OB: | |
8549 | gas_assert (mips_opts.micromips); | |
8550 | s = "lwm"; | |
8551 | fmt = "n,~(b)"; | |
7f3c4072 | 8552 | offbits = 12; |
df58fc94 RS |
8553 | goto ld_st; |
8554 | case M_LDM_AB: | |
8555 | ab = 1; | |
8556 | case M_LDM_OB: | |
8557 | gas_assert (mips_opts.micromips); | |
8558 | s = "ldm"; | |
8559 | fmt = "n,~(b)"; | |
7f3c4072 | 8560 | offbits = 12; |
df58fc94 RS |
8561 | goto ld_st; |
8562 | ||
252b5132 | 8563 | ld: |
f19ccbda MR |
8564 | /* We don't want to use $0 as tempreg. */ |
8565 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8566 | goto ld_st; |
252b5132 | 8567 | else |
df58fc94 RS |
8568 | tempreg = treg + lp; |
8569 | goto ld_noat; | |
8570 | ||
252b5132 | 8571 | case M_SB_AB: |
df58fc94 | 8572 | ab = 1; |
252b5132 | 8573 | s = "sb"; |
df58fc94 RS |
8574 | fmt = "t,o(b)"; |
8575 | goto ld_st; | |
252b5132 | 8576 | case M_SH_AB: |
df58fc94 | 8577 | ab = 1; |
252b5132 | 8578 | s = "sh"; |
df58fc94 RS |
8579 | fmt = "t,o(b)"; |
8580 | goto ld_st; | |
252b5132 | 8581 | case M_SW_AB: |
df58fc94 | 8582 | ab = 1; |
252b5132 | 8583 | s = "sw"; |
df58fc94 RS |
8584 | fmt = "t,o(b)"; |
8585 | goto ld_st; | |
252b5132 | 8586 | case M_SWC0_AB: |
df58fc94 RS |
8587 | ab = 1; |
8588 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8589 | s = "swc0"; |
df58fc94 | 8590 | fmt = "E,o(b)"; |
bdaaa2e1 | 8591 | /* Itbl support may require additional care here. */ |
252b5132 | 8592 | coproc = 1; |
df58fc94 | 8593 | goto ld_st; |
252b5132 | 8594 | case M_SWC1_AB: |
df58fc94 | 8595 | ab = 1; |
252b5132 | 8596 | s = "swc1"; |
df58fc94 | 8597 | fmt = "T,o(b)"; |
bdaaa2e1 | 8598 | /* Itbl support may require additional care here. */ |
252b5132 | 8599 | coproc = 1; |
df58fc94 | 8600 | goto ld_st; |
252b5132 | 8601 | case M_SWC2_AB: |
df58fc94 RS |
8602 | ab = 1; |
8603 | case M_SWC2_OB: | |
252b5132 | 8604 | s = "swc2"; |
df58fc94 | 8605 | fmt = COP12_FMT; |
7f3c4072 | 8606 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8607 | /* Itbl support may require additional care here. */ |
252b5132 | 8608 | coproc = 1; |
df58fc94 | 8609 | goto ld_st; |
252b5132 | 8610 | case M_SWC3_AB: |
df58fc94 RS |
8611 | ab = 1; |
8612 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8613 | s = "swc3"; |
df58fc94 | 8614 | fmt = "E,o(b)"; |
bdaaa2e1 | 8615 | /* Itbl support may require additional care here. */ |
252b5132 | 8616 | coproc = 1; |
df58fc94 | 8617 | goto ld_st; |
252b5132 | 8618 | case M_SWL_AB: |
df58fc94 RS |
8619 | ab = 1; |
8620 | case M_SWL_OB: | |
252b5132 | 8621 | s = "swl"; |
df58fc94 | 8622 | fmt = MEM12_FMT; |
7f3c4072 | 8623 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8624 | goto ld_st; |
252b5132 | 8625 | case M_SWR_AB: |
df58fc94 RS |
8626 | ab = 1; |
8627 | case M_SWR_OB: | |
252b5132 | 8628 | s = "swr"; |
df58fc94 | 8629 | fmt = MEM12_FMT; |
7f3c4072 | 8630 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8631 | goto ld_st; |
252b5132 | 8632 | case M_SC_AB: |
df58fc94 RS |
8633 | ab = 1; |
8634 | case M_SC_OB: | |
252b5132 | 8635 | s = "sc"; |
df58fc94 | 8636 | fmt = MEM12_FMT; |
7f3c4072 | 8637 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8638 | goto ld_st; |
252b5132 | 8639 | case M_SCD_AB: |
df58fc94 RS |
8640 | ab = 1; |
8641 | case M_SCD_OB: | |
252b5132 | 8642 | s = "scd"; |
df58fc94 | 8643 | fmt = MEM12_FMT; |
7f3c4072 | 8644 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8645 | goto ld_st; |
d43b4baf | 8646 | case M_CACHE_AB: |
df58fc94 RS |
8647 | ab = 1; |
8648 | case M_CACHE_OB: | |
d43b4baf | 8649 | s = "cache"; |
df58fc94 | 8650 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8651 | offbits = (mips_opts.micromips ? 12 : 16); |
8652 | goto ld_st; | |
8653 | case M_CACHEE_AB: | |
8654 | ab = 1; | |
8655 | case M_CACHEE_OB: | |
8656 | s = "cachee"; | |
8657 | fmt = "k,+j(b)"; | |
8658 | offbits = 9; | |
df58fc94 | 8659 | goto ld_st; |
3eebd5eb | 8660 | case M_PREF_AB: |
df58fc94 RS |
8661 | ab = 1; |
8662 | case M_PREF_OB: | |
3eebd5eb | 8663 | s = "pref"; |
df58fc94 | 8664 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8665 | offbits = (mips_opts.micromips ? 12 : 16); |
8666 | goto ld_st; | |
8667 | case M_PREFE_AB: | |
8668 | ab = 1; | |
8669 | case M_PREFE_OB: | |
8670 | s = "prefe"; | |
8671 | fmt = "k,+j(b)"; | |
8672 | offbits = 9; | |
df58fc94 | 8673 | goto ld_st; |
252b5132 | 8674 | case M_SDC1_AB: |
df58fc94 | 8675 | ab = 1; |
252b5132 | 8676 | s = "sdc1"; |
df58fc94 | 8677 | fmt = "T,o(b)"; |
252b5132 | 8678 | coproc = 1; |
bdaaa2e1 | 8679 | /* Itbl support may require additional care here. */ |
df58fc94 | 8680 | goto ld_st; |
252b5132 | 8681 | case M_SDC2_AB: |
df58fc94 RS |
8682 | ab = 1; |
8683 | case M_SDC2_OB: | |
252b5132 | 8684 | s = "sdc2"; |
df58fc94 | 8685 | fmt = COP12_FMT; |
7f3c4072 | 8686 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8687 | /* Itbl support may require additional care here. */ |
8688 | coproc = 1; | |
8689 | goto ld_st; | |
8690 | case M_SQC2_AB: | |
8691 | ab = 1; | |
8692 | s = "sqc2"; | |
8693 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8694 | /* Itbl support may require additional care here. */ |
252b5132 | 8695 | coproc = 1; |
df58fc94 | 8696 | goto ld_st; |
252b5132 | 8697 | case M_SDC3_AB: |
df58fc94 RS |
8698 | ab = 1; |
8699 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8700 | s = "sdc3"; |
df58fc94 | 8701 | fmt = "E,o(b)"; |
bdaaa2e1 | 8702 | /* Itbl support may require additional care here. */ |
252b5132 | 8703 | coproc = 1; |
df58fc94 | 8704 | goto ld_st; |
252b5132 | 8705 | case M_SDL_AB: |
df58fc94 RS |
8706 | ab = 1; |
8707 | case M_SDL_OB: | |
252b5132 | 8708 | s = "sdl"; |
df58fc94 | 8709 | fmt = MEM12_FMT; |
7f3c4072 | 8710 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8711 | goto ld_st; |
252b5132 | 8712 | case M_SDR_AB: |
df58fc94 RS |
8713 | ab = 1; |
8714 | case M_SDR_OB: | |
252b5132 | 8715 | s = "sdr"; |
df58fc94 | 8716 | fmt = MEM12_FMT; |
7f3c4072 | 8717 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8718 | goto ld_st; |
8719 | case M_SWP_AB: | |
8720 | ab = 1; | |
8721 | case M_SWP_OB: | |
8722 | gas_assert (mips_opts.micromips); | |
8723 | s = "swp"; | |
8724 | fmt = "t,~(b)"; | |
7f3c4072 | 8725 | offbits = 12; |
df58fc94 RS |
8726 | goto ld_st; |
8727 | case M_SDP_AB: | |
8728 | ab = 1; | |
8729 | case M_SDP_OB: | |
8730 | gas_assert (mips_opts.micromips); | |
8731 | s = "sdp"; | |
8732 | fmt = "t,~(b)"; | |
7f3c4072 | 8733 | offbits = 12; |
df58fc94 RS |
8734 | goto ld_st; |
8735 | case M_SWM_AB: | |
8736 | ab = 1; | |
8737 | case M_SWM_OB: | |
8738 | gas_assert (mips_opts.micromips); | |
8739 | s = "swm"; | |
8740 | fmt = "n,~(b)"; | |
7f3c4072 | 8741 | offbits = 12; |
df58fc94 RS |
8742 | goto ld_st; |
8743 | case M_SDM_AB: | |
8744 | ab = 1; | |
8745 | case M_SDM_OB: | |
8746 | gas_assert (mips_opts.micromips); | |
8747 | s = "sdm"; | |
8748 | fmt = "n,~(b)"; | |
7f3c4072 | 8749 | offbits = 12; |
df58fc94 RS |
8750 | |
8751 | ld_st: | |
8fc2e39e TS |
8752 | tempreg = AT; |
8753 | used_at = 1; | |
df58fc94 | 8754 | ld_noat: |
252b5132 RH |
8755 | if (offset_expr.X_op != O_constant |
8756 | && offset_expr.X_op != O_symbol) | |
8757 | { | |
f71d0d44 | 8758 | as_bad (_("Expression too complex")); |
252b5132 RH |
8759 | offset_expr.X_op = O_constant; |
8760 | } | |
8761 | ||
2051e8c4 MR |
8762 | if (HAVE_32BIT_ADDRESSES |
8763 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8764 | { |
8765 | char value [32]; | |
8766 | ||
8767 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8768 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8769 | } |
2051e8c4 | 8770 | |
252b5132 RH |
8771 | /* A constant expression in PIC code can be handled just as it |
8772 | is in non PIC code. */ | |
aed1a261 RS |
8773 | if (offset_expr.X_op == O_constant) |
8774 | { | |
df58fc94 RS |
8775 | int hipart = 0; |
8776 | ||
842f8b2a | 8777 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8778 | normalize_address_expr (&expr1); |
7f3c4072 CM |
8779 | if ((offbits == 0 || offbits == 16) |
8780 | && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) | |
842f8b2a MR |
8781 | { |
8782 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8783 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8784 | hipart = 1; |
8785 | } | |
7f3c4072 | 8786 | else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) |
df58fc94 RS |
8787 | { |
8788 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8789 | & ~(bfd_vma) 0xfff); | |
8790 | hipart = 1; | |
8791 | } | |
7f3c4072 CM |
8792 | else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number)) |
8793 | { | |
8794 | expr1.X_add_number = ((expr1.X_add_number + 0x100) | |
8795 | & ~(bfd_vma) 0x1ff); | |
8796 | hipart = 1; | |
8797 | } | |
df58fc94 RS |
8798 | if (hipart) |
8799 | { | |
842f8b2a MR |
8800 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8801 | if (breg != 0) | |
8802 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8803 | tempreg, tempreg, breg); | |
8804 | breg = tempreg; | |
8805 | } | |
7f3c4072 | 8806 | if (offbits == 0) |
dd6a37e7 AP |
8807 | { |
8808 | if (offset_expr.X_add_number == 0) | |
8809 | tempreg = breg; | |
8810 | else | |
8811 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8812 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8813 | macro_build (NULL, s, fmt, treg, tempreg); | |
8814 | } | |
7f3c4072 | 8815 | else if (offbits == 16) |
df58fc94 RS |
8816 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8817 | else | |
8818 | macro_build (NULL, s, fmt, | |
8819 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8820 | } | |
7f3c4072 | 8821 | else if (offbits != 16) |
df58fc94 | 8822 | { |
7f3c4072 CM |
8823 | /* The offset field is too narrow to be used for a low-part |
8824 | relocation, so load the whole address into the auxillary | |
8825 | register. In the case of "A(b)" addresses, we first load | |
8826 | absolute address "A" into the register and then add base | |
8827 | register "b". In the case of "o(b)" addresses, we simply | |
8828 | need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8829 | offset_reloc already contains the relocations associated |
8830 | with "o". */ | |
8831 | if (ab) | |
8832 | { | |
8833 | load_address (tempreg, &offset_expr, &used_at); | |
8834 | if (breg != 0) | |
8835 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8836 | tempreg, tempreg, breg); | |
8837 | } | |
8838 | else | |
8839 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8840 | tempreg, breg, -1, | |
8841 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8842 | expr1.X_add_number = 0; | |
7f3c4072 | 8843 | if (offbits == 0) |
dd6a37e7 AP |
8844 | macro_build (NULL, s, fmt, treg, tempreg); |
8845 | else | |
8846 | macro_build (NULL, s, fmt, | |
8847 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8848 | } |
8849 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8850 | { |
8851 | /* If this is a reference to a GP relative symbol, and there | |
8852 | is no base register, we want | |
cdf6fd85 | 8853 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8854 | Otherwise, if there is no base register, we want |
8855 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8856 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8857 | If we have a constant, we need two instructions anyhow, | |
8858 | so we always use the latter form. | |
8859 | ||
8860 | If we have a base register, and this is a reference to a | |
8861 | GP relative symbol, we want | |
8862 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8863 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8864 | Otherwise we want |
8865 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8866 | addu $tempreg,$tempreg,$breg | |
8867 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8868 | With a constant we always use the latter case. |
76b3015f | 8869 | |
d6bc6245 TS |
8870 | With 64bit address space and no base register and $at usable, |
8871 | we want | |
8872 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8873 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8874 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8875 | dsll32 $tempreg,0 | |
8876 | daddu $tempreg,$at | |
8877 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8878 | If we have a base register, we want | |
8879 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8880 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8881 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8882 | daddu $at,$breg | |
8883 | dsll32 $tempreg,0 | |
8884 | daddu $tempreg,$at | |
8885 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8886 | ||
8887 | Without $at we can't generate the optimal path for superscalar | |
8888 | processors here since this would require two temporary registers. | |
8889 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8890 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8891 | dsll $tempreg,16 | |
8892 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8893 | dsll $tempreg,16 | |
8894 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8895 | If we have a base register, we want | |
8896 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8897 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8898 | dsll $tempreg,16 | |
8899 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8900 | dsll $tempreg,16 | |
8901 | daddu $tempreg,$tempreg,$breg | |
8902 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8903 | |
6caf9ef4 | 8904 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8905 | the same sequence as in 32bit address space. */ |
8906 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8907 | { |
aed1a261 | 8908 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8909 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8910 | { | |
8911 | relax_start (offset_expr.X_add_symbol); | |
8912 | if (breg == 0) | |
8913 | { | |
8914 | macro_build (&offset_expr, s, fmt, treg, | |
8915 | BFD_RELOC_GPREL16, mips_gp_register); | |
8916 | } | |
8917 | else | |
8918 | { | |
8919 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8920 | tempreg, breg, mips_gp_register); | |
8921 | macro_build (&offset_expr, s, fmt, treg, | |
8922 | BFD_RELOC_GPREL16, tempreg); | |
8923 | } | |
8924 | relax_switch (); | |
8925 | } | |
d6bc6245 | 8926 | |
741fe287 | 8927 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8928 | { |
df58fc94 | 8929 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8930 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8931 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8932 | BFD_RELOC_HI16_S); |
8933 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8934 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8935 | if (breg != 0) |
67c0d1eb | 8936 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8937 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8938 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8939 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8940 | tempreg); | |
d6bc6245 TS |
8941 | used_at = 1; |
8942 | } | |
8943 | else | |
8944 | { | |
df58fc94 | 8945 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8946 | BFD_RELOC_MIPS_HIGHEST); |
8947 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8948 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8949 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8950 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8951 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8952 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8953 | if (breg != 0) |
67c0d1eb | 8954 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8955 | tempreg, tempreg, breg); |
67c0d1eb | 8956 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8957 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8958 | } |
6caf9ef4 TS |
8959 | |
8960 | if (mips_relax.sequence) | |
8961 | relax_end (); | |
8fc2e39e | 8962 | break; |
d6bc6245 | 8963 | } |
256ab948 | 8964 | |
252b5132 RH |
8965 | if (breg == 0) |
8966 | { | |
67c0d1eb | 8967 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8968 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8969 | { |
4d7206a2 | 8970 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8971 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8972 | mips_gp_register); | |
4d7206a2 | 8973 | relax_switch (); |
252b5132 | 8974 | } |
67c0d1eb RS |
8975 | macro_build_lui (&offset_expr, tempreg); |
8976 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8977 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8978 | if (mips_relax.sequence) |
8979 | relax_end (); | |
252b5132 RH |
8980 | } |
8981 | else | |
8982 | { | |
67c0d1eb | 8983 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8984 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8985 | { |
4d7206a2 | 8986 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8987 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8988 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8989 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8990 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8991 | relax_switch (); |
252b5132 | 8992 | } |
67c0d1eb RS |
8993 | macro_build_lui (&offset_expr, tempreg); |
8994 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8995 | tempreg, tempreg, breg); |
67c0d1eb | 8996 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8997 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8998 | if (mips_relax.sequence) |
8999 | relax_end (); | |
252b5132 RH |
9000 | } |
9001 | } | |
0a44bf69 | 9002 | else if (!mips_big_got) |
252b5132 | 9003 | { |
ed6fb7bd | 9004 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 9005 | |
252b5132 RH |
9006 | /* If this is a reference to an external symbol, we want |
9007 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9008 | nop | |
9009 | <op> $treg,0($tempreg) | |
9010 | Otherwise we want | |
9011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9012 | nop | |
9013 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9014 | <op> $treg,0($tempreg) | |
f5040a92 AO |
9015 | |
9016 | For NewABI, we want | |
9017 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9018 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
9019 | ||
252b5132 RH |
9020 | If there is a base register, we add it to $tempreg before |
9021 | the <op>. If there is a constant, we stick it in the | |
9022 | <op> instruction. We don't handle constants larger than | |
9023 | 16 bits, because we have no way to load the upper 16 bits | |
9024 | (actually, we could handle them for the subset of cases | |
9025 | in which we are not using $at). */ | |
9c2799c2 | 9026 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
9027 | if (HAVE_NEWABI) |
9028 | { | |
67c0d1eb RS |
9029 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9030 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9031 | if (breg != 0) |
67c0d1eb | 9032 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9033 | tempreg, tempreg, breg); |
67c0d1eb | 9034 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9035 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
9036 | break; |
9037 | } | |
252b5132 RH |
9038 | expr1.X_add_number = offset_expr.X_add_number; |
9039 | offset_expr.X_add_number = 0; | |
9040 | if (expr1.X_add_number < -0x8000 | |
9041 | || expr1.X_add_number >= 0x8000) | |
9042 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
9043 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9044 | lw_reloc_type, mips_gp_register); | |
269137b2 | 9045 | load_delay_nop (); |
4d7206a2 RS |
9046 | relax_start (offset_expr.X_add_symbol); |
9047 | relax_switch (); | |
67c0d1eb RS |
9048 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9049 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9050 | relax_end (); |
252b5132 | 9051 | if (breg != 0) |
67c0d1eb | 9052 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9053 | tempreg, tempreg, breg); |
67c0d1eb | 9054 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9055 | } |
0a44bf69 | 9056 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 9057 | { |
67c0d1eb | 9058 | int gpdelay; |
252b5132 RH |
9059 | |
9060 | /* If this is a reference to an external symbol, we want | |
9061 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9062 | addu $tempreg,$tempreg,$gp | |
9063 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9064 | <op> $treg,0($tempreg) | |
9065 | Otherwise we want | |
9066 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9067 | nop | |
9068 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9069 | <op> $treg,0($tempreg) | |
9070 | If there is a base register, we add it to $tempreg before | |
9071 | the <op>. If there is a constant, we stick it in the | |
9072 | <op> instruction. We don't handle constants larger than | |
9073 | 16 bits, because we have no way to load the upper 16 bits | |
9074 | (actually, we could handle them for the subset of cases | |
f5040a92 | 9075 | in which we are not using $at). */ |
9c2799c2 | 9076 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
9077 | expr1.X_add_number = offset_expr.X_add_number; |
9078 | offset_expr.X_add_number = 0; | |
9079 | if (expr1.X_add_number < -0x8000 | |
9080 | || expr1.X_add_number >= 0x8000) | |
9081 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9082 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9083 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9084 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9085 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9086 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9087 | mips_gp_register); | |
9088 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9089 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 9090 | relax_switch (); |
67c0d1eb RS |
9091 | if (gpdelay) |
9092 | macro_build (NULL, "nop", ""); | |
9093 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9094 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9095 | load_delay_nop (); |
67c0d1eb RS |
9096 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9097 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9098 | relax_end (); |
9099 | ||
252b5132 | 9100 | if (breg != 0) |
67c0d1eb | 9101 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9102 | tempreg, tempreg, breg); |
67c0d1eb | 9103 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9104 | } |
0a44bf69 | 9105 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 9106 | { |
f5040a92 AO |
9107 | /* If this is a reference to an external symbol, we want |
9108 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9109 | add $tempreg,$tempreg,$gp | |
9110 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9111 | <op> $treg,<ofst>($tempreg) | |
9112 | Otherwise, for local symbols, we want: | |
9113 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9114 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 9115 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 9116 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
9117 | offset_expr.X_add_number = 0; |
9118 | if (expr1.X_add_number < -0x8000 | |
9119 | || expr1.X_add_number >= 0x8000) | |
9120 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 9121 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9122 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9123 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9124 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9125 | mips_gp_register); | |
9126 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9127 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 9128 | if (breg != 0) |
67c0d1eb | 9129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9130 | tempreg, tempreg, breg); |
67c0d1eb | 9131 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 9132 | |
4d7206a2 | 9133 | relax_switch (); |
f5040a92 | 9134 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
9135 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9136 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9137 | if (breg != 0) |
67c0d1eb | 9138 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9139 | tempreg, tempreg, breg); |
67c0d1eb | 9140 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9141 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 9142 | relax_end (); |
f5040a92 | 9143 | } |
252b5132 RH |
9144 | else |
9145 | abort (); | |
9146 | ||
252b5132 RH |
9147 | break; |
9148 | ||
9149 | case M_LI: | |
9150 | case M_LI_S: | |
67c0d1eb | 9151 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 9152 | break; |
252b5132 RH |
9153 | |
9154 | case M_DLI: | |
67c0d1eb | 9155 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9156 | break; |
252b5132 RH |
9157 | |
9158 | case M_LI_SS: | |
9159 | if (imm_expr.X_op == O_constant) | |
9160 | { | |
8fc2e39e | 9161 | used_at = 1; |
67c0d1eb RS |
9162 | load_register (AT, &imm_expr, 0); |
9163 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9164 | break; |
9165 | } | |
9166 | else | |
9167 | { | |
9c2799c2 | 9168 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9169 | && strcmp (segment_name (S_GET_SEGMENT |
9170 | (offset_expr.X_add_symbol)), | |
9171 | ".lit4") == 0 | |
9172 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9173 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9174 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9175 | break; |
252b5132 RH |
9176 | } |
9177 | ||
9178 | case M_LI_D: | |
ca4e0257 RS |
9179 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9180 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9181 | order 32 bits of the value and the low order 32 bits are either | |
9182 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9183 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9184 | { | |
ca4e0257 | 9185 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9186 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9187 | else |
9188 | { | |
9189 | int hreg, lreg; | |
9190 | ||
9191 | if (target_big_endian) | |
9192 | { | |
9193 | hreg = treg; | |
9194 | lreg = treg + 1; | |
9195 | } | |
9196 | else | |
9197 | { | |
9198 | hreg = treg + 1; | |
9199 | lreg = treg; | |
9200 | } | |
9201 | ||
9202 | if (hreg <= 31) | |
67c0d1eb | 9203 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9204 | if (lreg <= 31) |
9205 | { | |
9206 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9207 | move_register (lreg, 0); |
252b5132 RH |
9208 | else |
9209 | { | |
9c2799c2 | 9210 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9211 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9212 | } |
9213 | } | |
9214 | } | |
8fc2e39e | 9215 | break; |
252b5132 RH |
9216 | } |
9217 | ||
9218 | /* We know that sym is in the .rdata section. First we get the | |
9219 | upper 16 bits of the address. */ | |
9220 | if (mips_pic == NO_PIC) | |
9221 | { | |
67c0d1eb | 9222 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9223 | used_at = 1; |
252b5132 | 9224 | } |
0a44bf69 | 9225 | else |
252b5132 | 9226 | { |
67c0d1eb RS |
9227 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9228 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9229 | used_at = 1; |
252b5132 | 9230 | } |
bdaaa2e1 | 9231 | |
252b5132 | 9232 | /* Now we load the register(s). */ |
ca4e0257 | 9233 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9234 | { |
9235 | used_at = 1; | |
9236 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9237 | } | |
252b5132 RH |
9238 | else |
9239 | { | |
8fc2e39e | 9240 | used_at = 1; |
67c0d1eb | 9241 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9242 | if (treg != RA) |
252b5132 RH |
9243 | { |
9244 | /* FIXME: How in the world do we deal with the possible | |
9245 | overflow here? */ | |
9246 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9247 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9248 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9249 | } |
9250 | } | |
252b5132 RH |
9251 | break; |
9252 | ||
9253 | case M_LI_DD: | |
ca4e0257 RS |
9254 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9255 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9256 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9257 | the value and the low order 32 bits are either zero or in | |
9258 | OFFSET_EXPR. */ | |
252b5132 RH |
9259 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9260 | { | |
8fc2e39e | 9261 | used_at = 1; |
67c0d1eb | 9262 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9263 | if (HAVE_64BIT_FPRS) |
9264 | { | |
9c2799c2 | 9265 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9266 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9267 | } |
252b5132 RH |
9268 | else |
9269 | { | |
67c0d1eb | 9270 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9271 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9272 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9273 | else |
9274 | { | |
9c2799c2 | 9275 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9276 | load_register (AT, &offset_expr, 0); |
9277 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9278 | } |
9279 | } | |
9280 | break; | |
9281 | } | |
9282 | ||
9c2799c2 | 9283 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9284 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9285 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9286 | if (strcmp (s, ".lit8") == 0) | |
9287 | { | |
0aa27725 | 9288 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9289 | { |
67c0d1eb | 9290 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 9291 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9292 | break; |
252b5132 | 9293 | } |
c9914766 | 9294 | breg = mips_gp_register; |
252b5132 RH |
9295 | r = BFD_RELOC_MIPS_LITERAL; |
9296 | goto dob; | |
9297 | } | |
9298 | else | |
9299 | { | |
9c2799c2 | 9300 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9301 | used_at = 1; |
0a44bf69 | 9302 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9304 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9305 | else |
9306 | { | |
9307 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9308 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9309 | } |
bdaaa2e1 | 9310 | |
0aa27725 | 9311 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) |
252b5132 | 9312 | { |
67c0d1eb RS |
9313 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
9314 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
9315 | break; |
9316 | } | |
9317 | breg = AT; | |
9318 | r = BFD_RELOC_LO16; | |
9319 | goto dob; | |
9320 | } | |
9321 | ||
9322 | case M_L_DOB: | |
252b5132 RH |
9323 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9324 | to adjust when loading from memory. */ | |
9325 | r = BFD_RELOC_LO16; | |
9326 | dob: | |
df58fc94 | 9327 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9328 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
67c0d1eb | 9329 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9330 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
9331 | /* FIXME: A possible overflow which I don't know how to deal |
9332 | with. */ | |
9333 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9334 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 9335 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
9336 | break; |
9337 | ||
c4a68bea | 9338 | case M_S_DOB: |
df58fc94 | 9339 | gas_assert (!mips_opts.micromips); |
0aa27725 | 9340 | gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); |
c4a68bea MR |
9341 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9342 | to adjust when storing to memory. */ | |
9343 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9344 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
9345 | offset_expr.X_add_number += 4; | |
9346 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
9347 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
9348 | break; | |
9349 | ||
252b5132 | 9350 | case M_L_DAB: |
df58fc94 | 9351 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9352 | /* |
9353 | * The MIPS assembler seems to check for X_add_number not | |
9354 | * being double aligned and generating: | |
9355 | * lui at,%hi(foo+1) | |
9356 | * addu at,at,v1 | |
9357 | * addiu at,at,%lo(foo+1) | |
9358 | * lwc1 f2,0(at) | |
9359 | * lwc1 f3,4(at) | |
9360 | * But, the resulting address is the same after relocation so why | |
9361 | * generate the extra instruction? | |
9362 | */ | |
bdaaa2e1 | 9363 | /* Itbl support may require additional care here. */ |
252b5132 | 9364 | coproc = 1; |
df58fc94 | 9365 | fmt = "T,o(b)"; |
0aa27725 | 9366 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9367 | { |
9368 | s = "ldc1"; | |
df58fc94 | 9369 | goto ld_st; |
252b5132 | 9370 | } |
252b5132 | 9371 | s = "lwc1"; |
252b5132 RH |
9372 | goto ldd_std; |
9373 | ||
9374 | case M_S_DAB: | |
df58fc94 RS |
9375 | gas_assert (!mips_opts.micromips); |
9376 | /* Itbl support may require additional care here. */ | |
9377 | coproc = 1; | |
9378 | fmt = "T,o(b)"; | |
0aa27725 | 9379 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9380 | { |
9381 | s = "sdc1"; | |
df58fc94 | 9382 | goto ld_st; |
252b5132 | 9383 | } |
252b5132 | 9384 | s = "swc1"; |
252b5132 RH |
9385 | goto ldd_std; |
9386 | ||
e407c74b NC |
9387 | case M_LQ_AB: |
9388 | fmt = "t,o(b)"; | |
9389 | s = "lq"; | |
9390 | goto ld; | |
9391 | ||
9392 | case M_SQ_AB: | |
9393 | fmt = "t,o(b)"; | |
9394 | s = "sq"; | |
9395 | goto ld_st; | |
9396 | ||
252b5132 | 9397 | case M_LD_AB: |
df58fc94 | 9398 | fmt = "t,o(b)"; |
ca4e0257 | 9399 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9400 | { |
9401 | s = "ld"; | |
9402 | goto ld; | |
9403 | } | |
252b5132 | 9404 | s = "lw"; |
252b5132 RH |
9405 | goto ldd_std; |
9406 | ||
9407 | case M_SD_AB: | |
df58fc94 | 9408 | fmt = "t,o(b)"; |
ca4e0257 | 9409 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9410 | { |
9411 | s = "sd"; | |
df58fc94 | 9412 | goto ld_st; |
252b5132 | 9413 | } |
252b5132 | 9414 | s = "sw"; |
252b5132 RH |
9415 | |
9416 | ldd_std: | |
9417 | if (offset_expr.X_op != O_symbol | |
9418 | && offset_expr.X_op != O_constant) | |
9419 | { | |
f71d0d44 | 9420 | as_bad (_("Expression too complex")); |
252b5132 RH |
9421 | offset_expr.X_op = O_constant; |
9422 | } | |
9423 | ||
2051e8c4 MR |
9424 | if (HAVE_32BIT_ADDRESSES |
9425 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9426 | { |
9427 | char value [32]; | |
9428 | ||
9429 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9430 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9431 | } |
2051e8c4 | 9432 | |
252b5132 RH |
9433 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9434 | to adjust when loading from memory. We set coproc if we must | |
9435 | load $fn+1 first. */ | |
bdaaa2e1 | 9436 | /* Itbl support may require additional care here. */ |
90ecf173 | 9437 | if (!target_big_endian) |
252b5132 RH |
9438 | coproc = 0; |
9439 | ||
90ecf173 | 9440 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9441 | { |
9442 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9443 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9444 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9445 | If we have a base register, we use this |
9446 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9447 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9448 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9449 | If this is not a GP relative symbol, we want |
9450 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9451 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9452 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9453 | If there is a base register, we add it to $at after the | |
9454 | lui instruction. If there is a constant, we always use | |
9455 | the last case. */ | |
39a59cf8 MR |
9456 | if (offset_expr.X_op == O_symbol |
9457 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9458 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9459 | { |
4d7206a2 | 9460 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9461 | if (breg == 0) |
9462 | { | |
c9914766 | 9463 | tempreg = mips_gp_register; |
252b5132 RH |
9464 | } |
9465 | else | |
9466 | { | |
67c0d1eb | 9467 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9468 | AT, breg, mips_gp_register); |
252b5132 | 9469 | tempreg = AT; |
252b5132 RH |
9470 | used_at = 1; |
9471 | } | |
9472 | ||
beae10d5 | 9473 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9474 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9475 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9476 | offset_expr.X_add_number += 4; |
9477 | ||
9478 | /* Set mips_optimize to 2 to avoid inserting an | |
9479 | undesired nop. */ | |
9480 | hold_mips_optimize = mips_optimize; | |
9481 | mips_optimize = 2; | |
beae10d5 | 9482 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9483 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9484 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9485 | mips_optimize = hold_mips_optimize; |
9486 | ||
4d7206a2 | 9487 | relax_switch (); |
252b5132 | 9488 | |
0970e49e | 9489 | offset_expr.X_add_number -= 4; |
252b5132 | 9490 | } |
8fc2e39e | 9491 | used_at = 1; |
67c0d1eb | 9492 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9493 | if (breg != 0) |
67c0d1eb | 9494 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9495 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9496 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9497 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9498 | /* FIXME: How do we handle overflow here? */ |
9499 | offset_expr.X_add_number += 4; | |
beae10d5 | 9500 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9501 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9502 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9503 | if (mips_relax.sequence) |
9504 | relax_end (); | |
bdaaa2e1 | 9505 | } |
0a44bf69 | 9506 | else if (!mips_big_got) |
252b5132 | 9507 | { |
252b5132 RH |
9508 | /* If this is a reference to an external symbol, we want |
9509 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9510 | nop | |
9511 | <op> $treg,0($at) | |
9512 | <op> $treg+1,4($at) | |
9513 | Otherwise we want | |
9514 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9515 | nop | |
9516 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9517 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9518 | If there is a base register we add it to $at before the | |
9519 | lwc1 instructions. If there is a constant we include it | |
9520 | in the lwc1 instructions. */ | |
9521 | used_at = 1; | |
9522 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9523 | if (expr1.X_add_number < -0x8000 |
9524 | || expr1.X_add_number >= 0x8000 - 4) | |
9525 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9526 | load_got_offset (AT, &offset_expr); |
269137b2 | 9527 | load_delay_nop (); |
252b5132 | 9528 | if (breg != 0) |
67c0d1eb | 9529 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9530 | |
9531 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9532 | nop. */ | |
9533 | hold_mips_optimize = mips_optimize; | |
9534 | mips_optimize = 2; | |
4d7206a2 | 9535 | |
beae10d5 | 9536 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9537 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9538 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9539 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9540 | expr1.X_add_number += 4; |
67c0d1eb RS |
9541 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9542 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9543 | relax_switch (); |
67c0d1eb RS |
9544 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9545 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9546 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9547 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9548 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9549 | relax_end (); |
252b5132 | 9550 | |
4d7206a2 | 9551 | mips_optimize = hold_mips_optimize; |
252b5132 | 9552 | } |
0a44bf69 | 9553 | else if (mips_big_got) |
252b5132 | 9554 | { |
67c0d1eb | 9555 | int gpdelay; |
252b5132 RH |
9556 | |
9557 | /* If this is a reference to an external symbol, we want | |
9558 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9559 | addu $at,$at,$gp | |
9560 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9561 | nop | |
9562 | <op> $treg,0($at) | |
9563 | <op> $treg+1,4($at) | |
9564 | Otherwise we want | |
9565 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9566 | nop | |
9567 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9568 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9569 | If there is a base register we add it to $at before the | |
9570 | lwc1 instructions. If there is a constant we include it | |
9571 | in the lwc1 instructions. */ | |
9572 | used_at = 1; | |
9573 | expr1.X_add_number = offset_expr.X_add_number; | |
9574 | offset_expr.X_add_number = 0; | |
9575 | if (expr1.X_add_number < -0x8000 | |
9576 | || expr1.X_add_number >= 0x8000 - 4) | |
9577 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9578 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9579 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9580 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9581 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9582 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9583 | AT, AT, mips_gp_register); |
67c0d1eb | 9584 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9585 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9586 | load_delay_nop (); |
252b5132 | 9587 | if (breg != 0) |
67c0d1eb | 9588 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9589 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9590 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9591 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9592 | expr1.X_add_number += 4; |
9593 | ||
9594 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9595 | nop. */ | |
9596 | hold_mips_optimize = mips_optimize; | |
9597 | mips_optimize = 2; | |
beae10d5 | 9598 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9599 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9600 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9601 | mips_optimize = hold_mips_optimize; |
9602 | expr1.X_add_number -= 4; | |
9603 | ||
4d7206a2 RS |
9604 | relax_switch (); |
9605 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9606 | if (gpdelay) |
9607 | macro_build (NULL, "nop", ""); | |
9608 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9609 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9610 | load_delay_nop (); |
252b5132 | 9611 | if (breg != 0) |
67c0d1eb | 9612 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9613 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9614 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9615 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9616 | offset_expr.X_add_number += 4; |
252b5132 RH |
9617 | |
9618 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9619 | nop. */ | |
9620 | hold_mips_optimize = mips_optimize; | |
9621 | mips_optimize = 2; | |
beae10d5 | 9622 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9623 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9624 | BFD_RELOC_LO16, AT); | |
252b5132 | 9625 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9626 | relax_end (); |
252b5132 | 9627 | } |
252b5132 RH |
9628 | else |
9629 | abort (); | |
9630 | ||
252b5132 RH |
9631 | break; |
9632 | ||
9633 | case M_LD_OB: | |
704897fb | 9634 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9635 | goto sd_ob; |
9636 | case M_SD_OB: | |
704897fb | 9637 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9638 | sd_ob: |
4614d845 MR |
9639 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9640 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9641 | breg); | |
704897fb MR |
9642 | if (!HAVE_64BIT_GPRS) |
9643 | { | |
9644 | offset_expr.X_add_number += 4; | |
9645 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9646 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9647 | breg); | |
704897fb | 9648 | } |
8fc2e39e | 9649 | break; |
252b5132 | 9650 | |
dd6a37e7 AP |
9651 | |
9652 | case M_SAA_AB: | |
9653 | ab = 1; | |
9654 | case M_SAA_OB: | |
9655 | s = "saa"; | |
7f3c4072 | 9656 | offbits = 0; |
dd6a37e7 AP |
9657 | fmt = "t,(b)"; |
9658 | goto ld_st; | |
9659 | case M_SAAD_AB: | |
9660 | ab = 1; | |
9661 | case M_SAAD_OB: | |
9662 | s = "saad"; | |
7f3c4072 | 9663 | offbits = 0; |
dd6a37e7 AP |
9664 | fmt = "t,(b)"; |
9665 | goto ld_st; | |
9666 | ||
252b5132 RH |
9667 | /* New code added to support COPZ instructions. |
9668 | This code builds table entries out of the macros in mip_opcodes. | |
9669 | R4000 uses interlocks to handle coproc delays. | |
9670 | Other chips (like the R3000) require nops to be inserted for delays. | |
9671 | ||
f72c8c98 | 9672 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9673 | In order to fill delay slots for non-interlocked chips, |
9674 | we must have a way to specify delays based on the coprocessor. | |
9675 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9676 | What are the side-effects of the cop instruction? | |
9677 | What cache support might we have and what are its effects? | |
9678 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9679 | What registers are read/set/modified? |
252b5132 RH |
9680 | |
9681 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9682 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9683 | |
9684 | case M_COP0: | |
9685 | s = "c0"; | |
9686 | goto copz; | |
9687 | case M_COP1: | |
9688 | s = "c1"; | |
9689 | goto copz; | |
9690 | case M_COP2: | |
9691 | s = "c2"; | |
9692 | goto copz; | |
9693 | case M_COP3: | |
9694 | s = "c3"; | |
9695 | copz: | |
df58fc94 | 9696 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9697 | /* For now we just do C (same as Cz). The parameter will be |
9698 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9699 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9700 | break; |
252b5132 | 9701 | |
ea1fb5dc | 9702 | case M_MOVE: |
67c0d1eb | 9703 | move_register (dreg, sreg); |
8fc2e39e | 9704 | break; |
ea1fb5dc | 9705 | |
252b5132 RH |
9706 | case M_DMUL: |
9707 | dbl = 1; | |
9708 | case M_MUL: | |
e407c74b NC |
9709 | if (mips_opts.arch == CPU_R5900) |
9710 | { | |
9711 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9712 | } | |
9713 | else | |
9714 | { | |
67c0d1eb | 9715 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9716 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9717 | } |
8fc2e39e | 9718 | break; |
252b5132 RH |
9719 | |
9720 | case M_DMUL_I: | |
9721 | dbl = 1; | |
9722 | case M_MUL_I: | |
9723 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9724 | not trying to be that fancy. GCC should do this for us | |
9725 | anyway. */ | |
8fc2e39e | 9726 | used_at = 1; |
67c0d1eb RS |
9727 | load_register (AT, &imm_expr, dbl); |
9728 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9729 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9730 | break; |
9731 | ||
9732 | case M_DMULO_I: | |
9733 | dbl = 1; | |
9734 | case M_MULO_I: | |
9735 | imm = 1; | |
9736 | goto do_mulo; | |
9737 | ||
9738 | case M_DMULO: | |
9739 | dbl = 1; | |
9740 | case M_MULO: | |
9741 | do_mulo: | |
7d10b47d | 9742 | start_noreorder (); |
8fc2e39e | 9743 | used_at = 1; |
252b5132 | 9744 | if (imm) |
67c0d1eb RS |
9745 | load_register (AT, &imm_expr, dbl); |
9746 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9747 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9748 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9749 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9750 | if (mips_trap) |
df58fc94 | 9751 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9752 | else |
9753 | { | |
df58fc94 RS |
9754 | if (mips_opts.micromips) |
9755 | micromips_label_expr (&label_expr); | |
9756 | else | |
9757 | label_expr.X_add_number = 8; | |
9758 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9759 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9760 | macro_build (NULL, "break", BRK_FMT, 6); |
9761 | if (mips_opts.micromips) | |
9762 | micromips_add_label (); | |
252b5132 | 9763 | } |
7d10b47d | 9764 | end_noreorder (); |
df58fc94 | 9765 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9766 | break; |
9767 | ||
9768 | case M_DMULOU_I: | |
9769 | dbl = 1; | |
9770 | case M_MULOU_I: | |
9771 | imm = 1; | |
9772 | goto do_mulou; | |
9773 | ||
9774 | case M_DMULOU: | |
9775 | dbl = 1; | |
9776 | case M_MULOU: | |
9777 | do_mulou: | |
7d10b47d | 9778 | start_noreorder (); |
8fc2e39e | 9779 | used_at = 1; |
252b5132 | 9780 | if (imm) |
67c0d1eb RS |
9781 | load_register (AT, &imm_expr, dbl); |
9782 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9783 | sreg, imm ? AT : treg); |
df58fc94 RS |
9784 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9785 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9786 | if (mips_trap) |
df58fc94 | 9787 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9788 | else |
9789 | { | |
df58fc94 RS |
9790 | if (mips_opts.micromips) |
9791 | micromips_label_expr (&label_expr); | |
9792 | else | |
9793 | label_expr.X_add_number = 8; | |
9794 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9795 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9796 | macro_build (NULL, "break", BRK_FMT, 6); |
9797 | if (mips_opts.micromips) | |
9798 | micromips_add_label (); | |
252b5132 | 9799 | } |
7d10b47d | 9800 | end_noreorder (); |
252b5132 RH |
9801 | break; |
9802 | ||
771c7ce4 | 9803 | case M_DROL: |
fef14a42 | 9804 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9805 | { |
9806 | if (dreg == sreg) | |
9807 | { | |
9808 | tempreg = AT; | |
9809 | used_at = 1; | |
9810 | } | |
9811 | else | |
9812 | { | |
9813 | tempreg = dreg; | |
82dd0097 | 9814 | } |
67c0d1eb RS |
9815 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9816 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9817 | break; |
82dd0097 | 9818 | } |
8fc2e39e | 9819 | used_at = 1; |
c80c840e | 9820 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9821 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9822 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9823 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9824 | break; |
9825 | ||
252b5132 | 9826 | case M_ROL: |
fef14a42 | 9827 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9828 | { |
9829 | if (dreg == sreg) | |
9830 | { | |
9831 | tempreg = AT; | |
9832 | used_at = 1; | |
9833 | } | |
9834 | else | |
9835 | { | |
9836 | tempreg = dreg; | |
82dd0097 | 9837 | } |
67c0d1eb RS |
9838 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9839 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9840 | break; |
82dd0097 | 9841 | } |
8fc2e39e | 9842 | used_at = 1; |
c80c840e | 9843 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9844 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9845 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9846 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9847 | break; |
9848 | ||
771c7ce4 TS |
9849 | case M_DROL_I: |
9850 | { | |
9851 | unsigned int rot; | |
91d6fa6a NC |
9852 | char *l; |
9853 | char *rr; | |
771c7ce4 TS |
9854 | |
9855 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9856 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9857 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9858 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9859 | { |
9860 | rot = (64 - rot) & 0x3f; | |
9861 | if (rot >= 32) | |
df58fc94 | 9862 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9863 | else |
df58fc94 | 9864 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9865 | break; |
60b63b72 | 9866 | } |
483fc7cd | 9867 | if (rot == 0) |
483fc7cd | 9868 | { |
df58fc94 | 9869 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9870 | break; |
483fc7cd | 9871 | } |
82dd0097 | 9872 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9873 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9874 | rot &= 0x1f; |
8fc2e39e | 9875 | used_at = 1; |
df58fc94 RS |
9876 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9877 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9878 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9879 | } |
9880 | break; | |
9881 | ||
252b5132 | 9882 | case M_ROL_I: |
771c7ce4 TS |
9883 | { |
9884 | unsigned int rot; | |
9885 | ||
9886 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9887 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9888 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9889 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9890 | { |
df58fc94 | 9891 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9892 | break; |
60b63b72 | 9893 | } |
483fc7cd | 9894 | if (rot == 0) |
483fc7cd | 9895 | { |
df58fc94 | 9896 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9897 | break; |
483fc7cd | 9898 | } |
8fc2e39e | 9899 | used_at = 1; |
df58fc94 RS |
9900 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9901 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9902 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9903 | } |
9904 | break; | |
9905 | ||
9906 | case M_DROR: | |
fef14a42 | 9907 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9908 | { |
67c0d1eb | 9909 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9910 | break; |
82dd0097 | 9911 | } |
8fc2e39e | 9912 | used_at = 1; |
c80c840e | 9913 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9914 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9915 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9916 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9917 | break; |
9918 | ||
9919 | case M_ROR: | |
fef14a42 | 9920 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9921 | { |
67c0d1eb | 9922 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9923 | break; |
82dd0097 | 9924 | } |
8fc2e39e | 9925 | used_at = 1; |
c80c840e | 9926 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9927 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9928 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9929 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9930 | break; |
9931 | ||
771c7ce4 TS |
9932 | case M_DROR_I: |
9933 | { | |
9934 | unsigned int rot; | |
91d6fa6a NC |
9935 | char *l; |
9936 | char *rr; | |
771c7ce4 TS |
9937 | |
9938 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9939 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9940 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9941 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9942 | { |
9943 | if (rot >= 32) | |
df58fc94 | 9944 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9945 | else |
df58fc94 | 9946 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9947 | break; |
82dd0097 | 9948 | } |
483fc7cd | 9949 | if (rot == 0) |
483fc7cd | 9950 | { |
df58fc94 | 9951 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9952 | break; |
483fc7cd | 9953 | } |
91d6fa6a | 9954 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9955 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9956 | rot &= 0x1f; | |
8fc2e39e | 9957 | used_at = 1; |
df58fc94 RS |
9958 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9959 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9960 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9961 | } |
9962 | break; | |
9963 | ||
252b5132 | 9964 | case M_ROR_I: |
771c7ce4 TS |
9965 | { |
9966 | unsigned int rot; | |
9967 | ||
9968 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9969 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9970 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9971 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9972 | { |
df58fc94 | 9973 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9974 | break; |
82dd0097 | 9975 | } |
483fc7cd | 9976 | if (rot == 0) |
483fc7cd | 9977 | { |
df58fc94 | 9978 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9979 | break; |
483fc7cd | 9980 | } |
8fc2e39e | 9981 | used_at = 1; |
df58fc94 RS |
9982 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9983 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9984 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9985 | } |
252b5132 RH |
9986 | break; |
9987 | ||
252b5132 RH |
9988 | case M_SEQ: |
9989 | if (sreg == 0) | |
67c0d1eb | 9990 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9991 | else if (treg == 0) |
67c0d1eb | 9992 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9993 | else |
9994 | { | |
67c0d1eb RS |
9995 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9996 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9997 | } |
8fc2e39e | 9998 | break; |
252b5132 RH |
9999 | |
10000 | case M_SEQ_I: | |
10001 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10002 | { | |
67c0d1eb | 10003 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10004 | break; |
252b5132 RH |
10005 | } |
10006 | if (sreg == 0) | |
10007 | { | |
10008 | as_warn (_("Instruction %s: result is always false"), | |
10009 | ip->insn_mo->name); | |
67c0d1eb | 10010 | move_register (dreg, 0); |
8fc2e39e | 10011 | break; |
252b5132 | 10012 | } |
dd3cbb7e NC |
10013 | if (CPU_HAS_SEQ (mips_opts.arch) |
10014 | && -512 <= imm_expr.X_add_number | |
10015 | && imm_expr.X_add_number < 512) | |
10016 | { | |
10017 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10018 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10019 | break; |
10020 | } | |
252b5132 RH |
10021 | if (imm_expr.X_op == O_constant |
10022 | && imm_expr.X_add_number >= 0 | |
10023 | && imm_expr.X_add_number < 0x10000) | |
10024 | { | |
67c0d1eb | 10025 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10026 | } |
10027 | else if (imm_expr.X_op == O_constant | |
10028 | && imm_expr.X_add_number > -0x8000 | |
10029 | && imm_expr.X_add_number < 0) | |
10030 | { | |
10031 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10032 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10033 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10034 | } |
dd3cbb7e NC |
10035 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10036 | { | |
10037 | used_at = 1; | |
10038 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10039 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
10040 | break; | |
10041 | } | |
252b5132 RH |
10042 | else |
10043 | { | |
67c0d1eb RS |
10044 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10045 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10046 | used_at = 1; |
10047 | } | |
67c0d1eb | 10048 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10049 | break; |
252b5132 RH |
10050 | |
10051 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
10052 | s = "slt"; | |
10053 | goto sge; | |
10054 | case M_SGEU: | |
10055 | s = "sltu"; | |
10056 | sge: | |
67c0d1eb RS |
10057 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
10058 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10059 | break; |
252b5132 RH |
10060 | |
10061 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
10062 | case M_SGEU_I: | |
10063 | if (imm_expr.X_op == O_constant | |
10064 | && imm_expr.X_add_number >= -0x8000 | |
10065 | && imm_expr.X_add_number < 0x8000) | |
10066 | { | |
67c0d1eb RS |
10067 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
10068 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
10069 | } |
10070 | else | |
10071 | { | |
67c0d1eb RS |
10072 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10073 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
10074 | dreg, sreg, AT); | |
252b5132 RH |
10075 | used_at = 1; |
10076 | } | |
67c0d1eb | 10077 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10078 | break; |
252b5132 RH |
10079 | |
10080 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
10081 | s = "slt"; | |
10082 | goto sgt; | |
10083 | case M_SGTU: | |
10084 | s = "sltu"; | |
10085 | sgt: | |
67c0d1eb | 10086 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 10087 | break; |
252b5132 RH |
10088 | |
10089 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
10090 | s = "slt"; | |
10091 | goto sgti; | |
10092 | case M_SGTU_I: | |
10093 | s = "sltu"; | |
10094 | sgti: | |
8fc2e39e | 10095 | used_at = 1; |
67c0d1eb RS |
10096 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10097 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
10098 | break; |
10099 | ||
2396cfb9 | 10100 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
10101 | s = "slt"; |
10102 | goto sle; | |
10103 | case M_SLEU: | |
10104 | s = "sltu"; | |
10105 | sle: | |
67c0d1eb RS |
10106 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
10107 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10108 | break; |
252b5132 | 10109 | |
2396cfb9 | 10110 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
10111 | s = "slt"; |
10112 | goto slei; | |
10113 | case M_SLEU_I: | |
10114 | s = "sltu"; | |
10115 | slei: | |
8fc2e39e | 10116 | used_at = 1; |
67c0d1eb RS |
10117 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10118 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
10119 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
10120 | break; |
10121 | ||
10122 | case M_SLT_I: | |
10123 | if (imm_expr.X_op == O_constant | |
10124 | && imm_expr.X_add_number >= -0x8000 | |
10125 | && imm_expr.X_add_number < 0x8000) | |
10126 | { | |
67c0d1eb | 10127 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10128 | break; |
252b5132 | 10129 | } |
8fc2e39e | 10130 | used_at = 1; |
67c0d1eb RS |
10131 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10132 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10133 | break; |
10134 | ||
10135 | case M_SLTU_I: | |
10136 | if (imm_expr.X_op == O_constant | |
10137 | && imm_expr.X_add_number >= -0x8000 | |
10138 | && imm_expr.X_add_number < 0x8000) | |
10139 | { | |
67c0d1eb | 10140 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 10141 | BFD_RELOC_LO16); |
8fc2e39e | 10142 | break; |
252b5132 | 10143 | } |
8fc2e39e | 10144 | used_at = 1; |
67c0d1eb RS |
10145 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10146 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10147 | break; |
10148 | ||
10149 | case M_SNE: | |
10150 | if (sreg == 0) | |
67c0d1eb | 10151 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 10152 | else if (treg == 0) |
67c0d1eb | 10153 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10154 | else |
10155 | { | |
67c0d1eb RS |
10156 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10157 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10158 | } |
8fc2e39e | 10159 | break; |
252b5132 RH |
10160 | |
10161 | case M_SNE_I: | |
10162 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10163 | { | |
67c0d1eb | 10164 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10165 | break; |
252b5132 RH |
10166 | } |
10167 | if (sreg == 0) | |
10168 | { | |
10169 | as_warn (_("Instruction %s: result is always true"), | |
10170 | ip->insn_mo->name); | |
67c0d1eb RS |
10171 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10172 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10173 | break; |
252b5132 | 10174 | } |
dd3cbb7e NC |
10175 | if (CPU_HAS_SEQ (mips_opts.arch) |
10176 | && -512 <= imm_expr.X_add_number | |
10177 | && imm_expr.X_add_number < 512) | |
10178 | { | |
10179 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10180 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10181 | break; |
10182 | } | |
252b5132 RH |
10183 | if (imm_expr.X_op == O_constant |
10184 | && imm_expr.X_add_number >= 0 | |
10185 | && imm_expr.X_add_number < 0x10000) | |
10186 | { | |
67c0d1eb | 10187 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10188 | } |
10189 | else if (imm_expr.X_op == O_constant | |
10190 | && imm_expr.X_add_number > -0x8000 | |
10191 | && imm_expr.X_add_number < 0) | |
10192 | { | |
10193 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10194 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10195 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10196 | } |
dd3cbb7e NC |
10197 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10198 | { | |
10199 | used_at = 1; | |
10200 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10201 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10202 | break; | |
10203 | } | |
252b5132 RH |
10204 | else |
10205 | { | |
67c0d1eb RS |
10206 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10207 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10208 | used_at = 1; |
10209 | } | |
67c0d1eb | 10210 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10211 | break; |
252b5132 | 10212 | |
df58fc94 RS |
10213 | case M_SUB_I: |
10214 | s = "addi"; | |
10215 | s2 = "sub"; | |
10216 | goto do_subi; | |
10217 | case M_SUBU_I: | |
10218 | s = "addiu"; | |
10219 | s2 = "subu"; | |
10220 | goto do_subi; | |
252b5132 RH |
10221 | case M_DSUB_I: |
10222 | dbl = 1; | |
df58fc94 RS |
10223 | s = "daddi"; |
10224 | s2 = "dsub"; | |
10225 | if (!mips_opts.micromips) | |
10226 | goto do_subi; | |
252b5132 | 10227 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10228 | && imm_expr.X_add_number > -0x200 |
10229 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10230 | { |
df58fc94 | 10231 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10232 | break; |
252b5132 | 10233 | } |
df58fc94 | 10234 | goto do_subi_i; |
252b5132 RH |
10235 | case M_DSUBU_I: |
10236 | dbl = 1; | |
df58fc94 RS |
10237 | s = "daddiu"; |
10238 | s2 = "dsubu"; | |
10239 | do_subi: | |
252b5132 RH |
10240 | if (imm_expr.X_op == O_constant |
10241 | && imm_expr.X_add_number > -0x8000 | |
10242 | && imm_expr.X_add_number <= 0x8000) | |
10243 | { | |
10244 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10245 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10246 | break; |
252b5132 | 10247 | } |
df58fc94 | 10248 | do_subi_i: |
8fc2e39e | 10249 | used_at = 1; |
67c0d1eb | 10250 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10251 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10252 | break; |
10253 | ||
10254 | case M_TEQ_I: | |
10255 | s = "teq"; | |
10256 | goto trap; | |
10257 | case M_TGE_I: | |
10258 | s = "tge"; | |
10259 | goto trap; | |
10260 | case M_TGEU_I: | |
10261 | s = "tgeu"; | |
10262 | goto trap; | |
10263 | case M_TLT_I: | |
10264 | s = "tlt"; | |
10265 | goto trap; | |
10266 | case M_TLTU_I: | |
10267 | s = "tltu"; | |
10268 | goto trap; | |
10269 | case M_TNE_I: | |
10270 | s = "tne"; | |
10271 | trap: | |
8fc2e39e | 10272 | used_at = 1; |
67c0d1eb RS |
10273 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10274 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10275 | break; |
10276 | ||
252b5132 | 10277 | case M_TRUNCWS: |
43841e91 | 10278 | case M_TRUNCWD: |
df58fc94 | 10279 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10280 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10281 | used_at = 1; |
252b5132 RH |
10282 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10283 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10284 | ||
10285 | /* | |
10286 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10287 | * or is there a reason for it? | |
10288 | */ | |
7d10b47d | 10289 | start_noreorder (); |
67c0d1eb RS |
10290 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10291 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10292 | macro_build (NULL, "nop", ""); | |
252b5132 | 10293 | expr1.X_add_number = 3; |
67c0d1eb | 10294 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10295 | expr1.X_add_number = 2; |
67c0d1eb RS |
10296 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10297 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10298 | macro_build (NULL, "nop", ""); | |
10299 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10300 | dreg, sreg); | |
10301 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10302 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10303 | end_noreorder (); |
252b5132 RH |
10304 | break; |
10305 | ||
df58fc94 RS |
10306 | case M_ULH_A: |
10307 | ab = 1; | |
252b5132 RH |
10308 | case M_ULH: |
10309 | s = "lb"; | |
df58fc94 RS |
10310 | s2 = "lbu"; |
10311 | off = 1; | |
10312 | goto uld_st; | |
10313 | case M_ULHU_A: | |
10314 | ab = 1; | |
252b5132 RH |
10315 | case M_ULHU: |
10316 | s = "lbu"; | |
df58fc94 RS |
10317 | s2 = "lbu"; |
10318 | off = 1; | |
10319 | goto uld_st; | |
10320 | case M_ULW_A: | |
10321 | ab = 1; | |
10322 | case M_ULW: | |
10323 | s = "lwl"; | |
10324 | s2 = "lwr"; | |
7f3c4072 | 10325 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10326 | off = 3; |
10327 | goto uld_st; | |
10328 | case M_ULD_A: | |
10329 | ab = 1; | |
252b5132 RH |
10330 | case M_ULD: |
10331 | s = "ldl"; | |
10332 | s2 = "ldr"; | |
7f3c4072 | 10333 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10334 | off = 7; |
df58fc94 RS |
10335 | goto uld_st; |
10336 | case M_USH_A: | |
10337 | ab = 1; | |
10338 | case M_USH: | |
10339 | s = "sb"; | |
10340 | s2 = "sb"; | |
10341 | off = 1; | |
10342 | ust = 1; | |
10343 | goto uld_st; | |
10344 | case M_USW_A: | |
10345 | ab = 1; | |
10346 | case M_USW: | |
10347 | s = "swl"; | |
10348 | s2 = "swr"; | |
7f3c4072 | 10349 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10350 | off = 3; |
df58fc94 RS |
10351 | ust = 1; |
10352 | goto uld_st; | |
10353 | case M_USD_A: | |
10354 | ab = 1; | |
10355 | case M_USD: | |
10356 | s = "sdl"; | |
10357 | s2 = "sdr"; | |
7f3c4072 | 10358 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10359 | off = 7; |
10360 | ust = 1; | |
10361 | ||
10362 | uld_st: | |
10363 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 10364 | as_bad (_("Operand overflow")); |
df58fc94 RS |
10365 | |
10366 | ep = &offset_expr; | |
10367 | expr1.X_add_number = 0; | |
10368 | if (ab) | |
10369 | { | |
10370 | used_at = 1; | |
10371 | tempreg = AT; | |
10372 | load_address (tempreg, ep, &used_at); | |
10373 | if (breg != 0) | |
10374 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10375 | tempreg, tempreg, breg); | |
10376 | breg = tempreg; | |
10377 | tempreg = treg; | |
10378 | ep = &expr1; | |
10379 | } | |
7f3c4072 | 10380 | else if (offbits == 12 |
df58fc94 RS |
10381 | && (offset_expr.X_op != O_constant |
10382 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
10383 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
10384 | { | |
10385 | used_at = 1; | |
10386 | tempreg = AT; | |
10387 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
10388 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10389 | breg = tempreg; | |
10390 | tempreg = treg; | |
10391 | ep = &expr1; | |
10392 | } | |
10393 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10394 | { |
10395 | used_at = 1; | |
10396 | tempreg = AT; | |
10397 | } | |
252b5132 | 10398 | else |
df58fc94 | 10399 | tempreg = treg; |
af22f5b2 | 10400 | |
df58fc94 RS |
10401 | if (off == 1) |
10402 | goto ulh_sh; | |
252b5132 | 10403 | |
90ecf173 | 10404 | if (!target_big_endian) |
df58fc94 | 10405 | ep->X_add_number += off; |
7f3c4072 | 10406 | if (offbits != 12) |
df58fc94 | 10407 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 | 10408 | else |
df58fc94 RS |
10409 | macro_build (NULL, s, "t,~(b)", |
10410 | tempreg, (unsigned long) ep->X_add_number, breg); | |
10411 | ||
90ecf173 | 10412 | if (!target_big_endian) |
df58fc94 | 10413 | ep->X_add_number -= off; |
252b5132 | 10414 | else |
df58fc94 | 10415 | ep->X_add_number += off; |
7f3c4072 | 10416 | if (offbits != 12) |
df58fc94 RS |
10417 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
10418 | else | |
10419 | macro_build (NULL, s2, "t,~(b)", | |
10420 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 10421 | |
df58fc94 RS |
10422 | /* If necessary, move the result in tempreg to the final destination. */ |
10423 | if (!ust && treg != tempreg) | |
10424 | { | |
10425 | /* Protect second load's delay slot. */ | |
10426 | load_delay_nop (); | |
10427 | move_register (treg, tempreg); | |
10428 | } | |
8fc2e39e | 10429 | break; |
252b5132 | 10430 | |
df58fc94 | 10431 | ulh_sh: |
d6bc6245 | 10432 | used_at = 1; |
df58fc94 RS |
10433 | if (target_big_endian == ust) |
10434 | ep->X_add_number += off; | |
10435 | tempreg = ust || ab ? treg : AT; | |
10436 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
10437 | ||
10438 | /* For halfword transfers we need a temporary register to shuffle | |
10439 | bytes. Unfortunately for M_USH_A we have none available before | |
10440 | the next store as AT holds the base address. We deal with this | |
10441 | case by clobbering TREG and then restoring it as with ULH. */ | |
10442 | tempreg = ust == ab ? treg : AT; | |
10443 | if (ust) | |
10444 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10445 | ||
10446 | if (target_big_endian == ust) | |
10447 | ep->X_add_number -= off; | |
252b5132 | 10448 | else |
df58fc94 RS |
10449 | ep->X_add_number += off; |
10450 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 10451 | |
df58fc94 RS |
10452 | /* For M_USH_A re-retrieve the LSB. */ |
10453 | if (ust && ab) | |
10454 | { | |
10455 | if (target_big_endian) | |
10456 | ep->X_add_number += off; | |
10457 | else | |
10458 | ep->X_add_number -= off; | |
10459 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
10460 | } | |
10461 | /* For ULH and M_USH_A OR the LSB in. */ | |
10462 | if (!ust || ab) | |
10463 | { | |
10464 | tempreg = !ab ? AT : treg; | |
10465 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
10466 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10467 | } | |
252b5132 RH |
10468 | break; |
10469 | ||
10470 | default: | |
10471 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10472 | are added dynamically. */ |
252b5132 RH |
10473 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10474 | break; | |
10475 | } | |
741fe287 | 10476 | if (!mips_opts.at && used_at) |
8fc2e39e | 10477 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10478 | } |
10479 | ||
10480 | /* Implement macros in mips16 mode. */ | |
10481 | ||
10482 | static void | |
17a2f251 | 10483 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10484 | { |
10485 | int mask; | |
10486 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10487 | expressionS expr1; |
10488 | int dbl; | |
10489 | const char *s, *s2, *s3; | |
10490 | ||
10491 | mask = ip->insn_mo->mask; | |
10492 | ||
bf12938e RS |
10493 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10494 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10495 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10496 | |
252b5132 RH |
10497 | expr1.X_op = O_constant; |
10498 | expr1.X_op_symbol = NULL; | |
10499 | expr1.X_add_symbol = NULL; | |
10500 | expr1.X_add_number = 1; | |
10501 | ||
10502 | dbl = 0; | |
10503 | ||
10504 | switch (mask) | |
10505 | { | |
10506 | default: | |
b37df7c4 | 10507 | abort (); |
252b5132 RH |
10508 | |
10509 | case M_DDIV_3: | |
10510 | dbl = 1; | |
10511 | case M_DIV_3: | |
10512 | s = "mflo"; | |
10513 | goto do_div3; | |
10514 | case M_DREM_3: | |
10515 | dbl = 1; | |
10516 | case M_REM_3: | |
10517 | s = "mfhi"; | |
10518 | do_div3: | |
7d10b47d | 10519 | start_noreorder (); |
67c0d1eb | 10520 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10521 | expr1.X_add_number = 2; |
67c0d1eb RS |
10522 | macro_build (&expr1, "bnez", "x,p", yreg); |
10523 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10524 | |
252b5132 RH |
10525 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10526 | since that causes an overflow. We should do that as well, | |
10527 | but I don't see how to do the comparisons without a temporary | |
10528 | register. */ | |
7d10b47d | 10529 | end_noreorder (); |
67c0d1eb | 10530 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10531 | break; |
10532 | ||
10533 | case M_DIVU_3: | |
10534 | s = "divu"; | |
10535 | s2 = "mflo"; | |
10536 | goto do_divu3; | |
10537 | case M_REMU_3: | |
10538 | s = "divu"; | |
10539 | s2 = "mfhi"; | |
10540 | goto do_divu3; | |
10541 | case M_DDIVU_3: | |
10542 | s = "ddivu"; | |
10543 | s2 = "mflo"; | |
10544 | goto do_divu3; | |
10545 | case M_DREMU_3: | |
10546 | s = "ddivu"; | |
10547 | s2 = "mfhi"; | |
10548 | do_divu3: | |
7d10b47d | 10549 | start_noreorder (); |
67c0d1eb | 10550 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10551 | expr1.X_add_number = 2; |
67c0d1eb RS |
10552 | macro_build (&expr1, "bnez", "x,p", yreg); |
10553 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10554 | end_noreorder (); |
67c0d1eb | 10555 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10556 | break; |
10557 | ||
10558 | case M_DMUL: | |
10559 | dbl = 1; | |
10560 | case M_MUL: | |
67c0d1eb RS |
10561 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10562 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10563 | break; |
252b5132 RH |
10564 | |
10565 | case M_DSUBU_I: | |
10566 | dbl = 1; | |
10567 | goto do_subu; | |
10568 | case M_SUBU_I: | |
10569 | do_subu: | |
10570 | if (imm_expr.X_op != O_constant) | |
10571 | as_bad (_("Unsupported large constant")); | |
10572 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10573 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10574 | break; |
10575 | ||
10576 | case M_SUBU_I_2: | |
10577 | if (imm_expr.X_op != O_constant) | |
10578 | as_bad (_("Unsupported large constant")); | |
10579 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10580 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10581 | break; |
10582 | ||
10583 | case M_DSUBU_I_2: | |
10584 | if (imm_expr.X_op != O_constant) | |
10585 | as_bad (_("Unsupported large constant")); | |
10586 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10587 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10588 | break; |
10589 | ||
10590 | case M_BEQ: | |
10591 | s = "cmp"; | |
10592 | s2 = "bteqz"; | |
10593 | goto do_branch; | |
10594 | case M_BNE: | |
10595 | s = "cmp"; | |
10596 | s2 = "btnez"; | |
10597 | goto do_branch; | |
10598 | case M_BLT: | |
10599 | s = "slt"; | |
10600 | s2 = "btnez"; | |
10601 | goto do_branch; | |
10602 | case M_BLTU: | |
10603 | s = "sltu"; | |
10604 | s2 = "btnez"; | |
10605 | goto do_branch; | |
10606 | case M_BLE: | |
10607 | s = "slt"; | |
10608 | s2 = "bteqz"; | |
10609 | goto do_reverse_branch; | |
10610 | case M_BLEU: | |
10611 | s = "sltu"; | |
10612 | s2 = "bteqz"; | |
10613 | goto do_reverse_branch; | |
10614 | case M_BGE: | |
10615 | s = "slt"; | |
10616 | s2 = "bteqz"; | |
10617 | goto do_branch; | |
10618 | case M_BGEU: | |
10619 | s = "sltu"; | |
10620 | s2 = "bteqz"; | |
10621 | goto do_branch; | |
10622 | case M_BGT: | |
10623 | s = "slt"; | |
10624 | s2 = "btnez"; | |
10625 | goto do_reverse_branch; | |
10626 | case M_BGTU: | |
10627 | s = "sltu"; | |
10628 | s2 = "btnez"; | |
10629 | ||
10630 | do_reverse_branch: | |
10631 | tmp = xreg; | |
10632 | xreg = yreg; | |
10633 | yreg = tmp; | |
10634 | ||
10635 | do_branch: | |
67c0d1eb RS |
10636 | macro_build (NULL, s, "x,y", xreg, yreg); |
10637 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10638 | break; |
10639 | ||
10640 | case M_BEQ_I: | |
10641 | s = "cmpi"; | |
10642 | s2 = "bteqz"; | |
10643 | s3 = "x,U"; | |
10644 | goto do_branch_i; | |
10645 | case M_BNE_I: | |
10646 | s = "cmpi"; | |
10647 | s2 = "btnez"; | |
10648 | s3 = "x,U"; | |
10649 | goto do_branch_i; | |
10650 | case M_BLT_I: | |
10651 | s = "slti"; | |
10652 | s2 = "btnez"; | |
10653 | s3 = "x,8"; | |
10654 | goto do_branch_i; | |
10655 | case M_BLTU_I: | |
10656 | s = "sltiu"; | |
10657 | s2 = "btnez"; | |
10658 | s3 = "x,8"; | |
10659 | goto do_branch_i; | |
10660 | case M_BLE_I: | |
10661 | s = "slti"; | |
10662 | s2 = "btnez"; | |
10663 | s3 = "x,8"; | |
10664 | goto do_addone_branch_i; | |
10665 | case M_BLEU_I: | |
10666 | s = "sltiu"; | |
10667 | s2 = "btnez"; | |
10668 | s3 = "x,8"; | |
10669 | goto do_addone_branch_i; | |
10670 | case M_BGE_I: | |
10671 | s = "slti"; | |
10672 | s2 = "bteqz"; | |
10673 | s3 = "x,8"; | |
10674 | goto do_branch_i; | |
10675 | case M_BGEU_I: | |
10676 | s = "sltiu"; | |
10677 | s2 = "bteqz"; | |
10678 | s3 = "x,8"; | |
10679 | goto do_branch_i; | |
10680 | case M_BGT_I: | |
10681 | s = "slti"; | |
10682 | s2 = "bteqz"; | |
10683 | s3 = "x,8"; | |
10684 | goto do_addone_branch_i; | |
10685 | case M_BGTU_I: | |
10686 | s = "sltiu"; | |
10687 | s2 = "bteqz"; | |
10688 | s3 = "x,8"; | |
10689 | ||
10690 | do_addone_branch_i: | |
10691 | if (imm_expr.X_op != O_constant) | |
10692 | as_bad (_("Unsupported large constant")); | |
10693 | ++imm_expr.X_add_number; | |
10694 | ||
10695 | do_branch_i: | |
67c0d1eb RS |
10696 | macro_build (&imm_expr, s, s3, xreg); |
10697 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10698 | break; |
10699 | ||
10700 | case M_ABS: | |
10701 | expr1.X_add_number = 0; | |
67c0d1eb | 10702 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10703 | if (xreg != yreg) |
67c0d1eb | 10704 | move_register (xreg, yreg); |
252b5132 | 10705 | expr1.X_add_number = 2; |
67c0d1eb RS |
10706 | macro_build (&expr1, "bteqz", "p"); |
10707 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10708 | } |
10709 | } | |
10710 | ||
10711 | /* For consistency checking, verify that all bits are specified either | |
10712 | by the match/mask part of the instruction definition, or by the | |
10713 | operand list. */ | |
10714 | static int | |
17a2f251 | 10715 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10716 | { |
10717 | const char *p = opc->args; | |
10718 | char c; | |
10719 | unsigned long used_bits = opc->mask; | |
10720 | ||
10721 | if ((used_bits & opc->match) != opc->match) | |
10722 | { | |
10723 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10724 | opc->name, opc->args); | |
10725 | return 0; | |
10726 | } | |
10727 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10728 | while (*p) | |
10729 | switch (c = *p++) | |
10730 | { | |
10731 | case ',': break; | |
10732 | case '(': break; | |
10733 | case ')': break; | |
af7ee8bf CD |
10734 | case '+': |
10735 | switch (c = *p++) | |
10736 | { | |
9bcd4f99 TS |
10737 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10738 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10739 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10740 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10741 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10742 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10743 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10744 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10745 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10746 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10747 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10748 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10749 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10750 | case 'I': break; | |
b015e599 | 10751 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 CF |
10752 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10753 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10754 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10755 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10756 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10757 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10758 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10759 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10760 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10761 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10762 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10763 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10764 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10765 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10766 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
7f3c4072 | 10767 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10768 | |
af7ee8bf CD |
10769 | default: |
10770 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10771 | c, opc->name, opc->args); | |
10772 | return 0; | |
10773 | } | |
10774 | break; | |
252b5132 RH |
10775 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10776 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10777 | case 'A': break; | |
4372b673 | 10778 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10779 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10780 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10781 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10782 | case 'F': break; | |
10783 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10784 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10785 | case 'I': break; |
e972090a | 10786 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10787 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10788 | case 'L': break; |
10789 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10790 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10791 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10792 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10793 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10794 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10795 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10796 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10797 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10798 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10799 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10800 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10801 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10802 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10803 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10804 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10805 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10806 | case 'f': break; | |
10807 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10808 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10809 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10810 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10811 | case 'l': break; | |
10812 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10813 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10814 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10815 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10816 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10817 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10818 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10819 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10820 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10821 | case 'x': break; | |
10822 | case 'z': break; | |
10823 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10824 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10825 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10826 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10827 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10828 | case '[': break; | |
10829 | case ']': break; | |
620edafd | 10830 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10831 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10832 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10833 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10834 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10835 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10836 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10837 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10838 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10839 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10840 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10841 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10842 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10843 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10844 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10845 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10846 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10847 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10848 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10849 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10850 | default: |
10851 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10852 | c, opc->name, opc->args); | |
10853 | return 0; | |
10854 | } | |
10855 | #undef USE_BITS | |
10856 | if (used_bits != 0xffffffff) | |
10857 | { | |
10858 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10859 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10860 | return 0; | |
10861 | } | |
10862 | return 1; | |
10863 | } | |
10864 | ||
df58fc94 RS |
10865 | /* For consistency checking, verify that the length implied matches the |
10866 | major opcode and that all bits are specified either by the match/mask | |
10867 | part of the instruction definition, or by the operand list. */ | |
10868 | ||
10869 | static int | |
10870 | validate_micromips_insn (const struct mips_opcode *opc) | |
10871 | { | |
10872 | unsigned long match = opc->match; | |
10873 | unsigned long mask = opc->mask; | |
10874 | const char *p = opc->args; | |
10875 | unsigned long insn_bits; | |
10876 | unsigned long used_bits; | |
10877 | unsigned long major; | |
10878 | unsigned int length; | |
10879 | char e; | |
10880 | char c; | |
10881 | ||
10882 | if ((mask & match) != match) | |
10883 | { | |
10884 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10885 | opc->name, opc->args); | |
10886 | return 0; | |
10887 | } | |
10888 | length = micromips_insn_length (opc); | |
10889 | if (length != 2 && length != 4) | |
10890 | { | |
10891 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10892 | "%s %s"), length, opc->name, opc->args); | |
10893 | return 0; | |
10894 | } | |
10895 | major = match >> (10 + 8 * (length - 2)); | |
10896 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10897 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10898 | { | |
10899 | as_bad (_("Internal error: bad microMIPS opcode " | |
10900 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10901 | return 0; | |
10902 | } | |
10903 | ||
10904 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10905 | insn_bits = 1 << 4 * length; | |
10906 | insn_bits <<= 4 * length; | |
10907 | insn_bits -= 1; | |
10908 | used_bits = mask; | |
10909 | #define USE_BITS(field) \ | |
10910 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10911 | while (*p) | |
10912 | switch (c = *p++) | |
10913 | { | |
10914 | case ',': break; | |
10915 | case '(': break; | |
10916 | case ')': break; | |
10917 | case '+': | |
10918 | e = c; | |
10919 | switch (c = *p++) | |
10920 | { | |
10921 | case 'A': USE_BITS (EXTLSB); break; | |
10922 | case 'B': USE_BITS (INSMSB); break; | |
10923 | case 'C': USE_BITS (EXTMSBD); break; | |
10924 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10925 | case 'E': USE_BITS (EXTLSB); break; | |
10926 | case 'F': USE_BITS (INSMSB); break; | |
10927 | case 'G': USE_BITS (EXTMSBD); break; | |
10928 | case 'H': USE_BITS (EXTMSBD); break; | |
7f3c4072 | 10929 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
10930 | default: |
10931 | as_bad (_("Internal error: bad mips opcode " | |
10932 | "(unknown extension operand type `%c%c'): %s %s"), | |
10933 | e, c, opc->name, opc->args); | |
10934 | return 0; | |
10935 | } | |
10936 | break; | |
10937 | case 'm': | |
10938 | e = c; | |
10939 | switch (c = *p++) | |
10940 | { | |
10941 | case 'A': USE_BITS (IMMA); break; | |
10942 | case 'B': USE_BITS (IMMB); break; | |
10943 | case 'C': USE_BITS (IMMC); break; | |
10944 | case 'D': USE_BITS (IMMD); break; | |
10945 | case 'E': USE_BITS (IMME); break; | |
10946 | case 'F': USE_BITS (IMMF); break; | |
10947 | case 'G': USE_BITS (IMMG); break; | |
10948 | case 'H': USE_BITS (IMMH); break; | |
10949 | case 'I': USE_BITS (IMMI); break; | |
10950 | case 'J': USE_BITS (IMMJ); break; | |
10951 | case 'L': USE_BITS (IMML); break; | |
10952 | case 'M': USE_BITS (IMMM); break; | |
10953 | case 'N': USE_BITS (IMMN); break; | |
10954 | case 'O': USE_BITS (IMMO); break; | |
10955 | case 'P': USE_BITS (IMMP); break; | |
10956 | case 'Q': USE_BITS (IMMQ); break; | |
10957 | case 'U': USE_BITS (IMMU); break; | |
10958 | case 'W': USE_BITS (IMMW); break; | |
10959 | case 'X': USE_BITS (IMMX); break; | |
10960 | case 'Y': USE_BITS (IMMY); break; | |
10961 | case 'Z': break; | |
10962 | case 'a': break; | |
10963 | case 'b': USE_BITS (MB); break; | |
10964 | case 'c': USE_BITS (MC); break; | |
10965 | case 'd': USE_BITS (MD); break; | |
10966 | case 'e': USE_BITS (ME); break; | |
10967 | case 'f': USE_BITS (MF); break; | |
10968 | case 'g': USE_BITS (MG); break; | |
10969 | case 'h': USE_BITS (MH); break; | |
10970 | case 'i': USE_BITS (MI); break; | |
10971 | case 'j': USE_BITS (MJ); break; | |
10972 | case 'l': USE_BITS (ML); break; | |
10973 | case 'm': USE_BITS (MM); break; | |
10974 | case 'n': USE_BITS (MN); break; | |
10975 | case 'p': USE_BITS (MP); break; | |
10976 | case 'q': USE_BITS (MQ); break; | |
10977 | case 'r': break; | |
10978 | case 's': break; | |
10979 | case 't': break; | |
10980 | case 'x': break; | |
10981 | case 'y': break; | |
10982 | case 'z': break; | |
10983 | default: | |
10984 | as_bad (_("Internal error: bad mips opcode " | |
10985 | "(unknown extension operand type `%c%c'): %s %s"), | |
10986 | e, c, opc->name, opc->args); | |
10987 | return 0; | |
10988 | } | |
10989 | break; | |
10990 | case '.': USE_BITS (OFFSET10); break; | |
10991 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10992 | case '2': USE_BITS (BP); break; |
10993 | case '3': USE_BITS (SA3); break; | |
10994 | case '4': USE_BITS (SA4); break; | |
10995 | case '5': USE_BITS (IMM8); break; | |
10996 | case '6': USE_BITS (RS); break; | |
10997 | case '7': USE_BITS (DSPACC); break; | |
10998 | case '8': USE_BITS (WRDSP); break; | |
10999 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
11000 | case '<': USE_BITS (SHAMT); break; |
11001 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 11002 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
11003 | case 'B': USE_BITS (CODE10); break; |
11004 | case 'C': USE_BITS (COPZ); break; | |
11005 | case 'D': USE_BITS (FD); break; | |
11006 | case 'E': USE_BITS (RT); break; | |
11007 | case 'G': USE_BITS (RS); break; | |
444d75be | 11008 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
11009 | case 'K': USE_BITS (RS); break; |
11010 | case 'M': USE_BITS (CCC); break; | |
11011 | case 'N': USE_BITS (BCC); break; | |
11012 | case 'R': USE_BITS (FR); break; | |
11013 | case 'S': USE_BITS (FS); break; | |
11014 | case 'T': USE_BITS (FT); break; | |
11015 | case 'V': USE_BITS (FS); break; | |
dec0624d | 11016 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 11017 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
11018 | case 'a': USE_BITS (TARGET); break; |
11019 | case 'b': USE_BITS (RS); break; | |
11020 | case 'c': USE_BITS (CODE); break; | |
11021 | case 'd': USE_BITS (RD); break; | |
11022 | case 'h': USE_BITS (PREFX); break; | |
11023 | case 'i': USE_BITS (IMMEDIATE); break; | |
11024 | case 'j': USE_BITS (DELTA); break; | |
11025 | case 'k': USE_BITS (CACHE); break; | |
11026 | case 'n': USE_BITS (RT); break; | |
11027 | case 'o': USE_BITS (DELTA); break; | |
11028 | case 'p': USE_BITS (DELTA); break; | |
11029 | case 'q': USE_BITS (CODE2); break; | |
11030 | case 'r': USE_BITS (RS); break; | |
11031 | case 's': USE_BITS (RS); break; | |
11032 | case 't': USE_BITS (RT); break; | |
11033 | case 'u': USE_BITS (IMMEDIATE); break; | |
11034 | case 'v': USE_BITS (RS); break; | |
11035 | case 'w': USE_BITS (RT); break; | |
11036 | case 'y': USE_BITS (RS3); break; | |
11037 | case 'z': break; | |
11038 | case '|': USE_BITS (TRAP); break; | |
11039 | case '~': USE_BITS (OFFSET12); break; | |
11040 | default: | |
11041 | as_bad (_("Internal error: bad microMIPS opcode " | |
11042 | "(unknown operand type `%c'): %s %s"), | |
11043 | c, opc->name, opc->args); | |
11044 | return 0; | |
11045 | } | |
11046 | #undef USE_BITS | |
11047 | if (used_bits != insn_bits) | |
11048 | { | |
11049 | if (~used_bits & insn_bits) | |
11050 | as_bad (_("Internal error: bad microMIPS opcode " | |
11051 | "(bits 0x%lx undefined): %s %s"), | |
11052 | ~used_bits & insn_bits, opc->name, opc->args); | |
11053 | if (used_bits & ~insn_bits) | |
11054 | as_bad (_("Internal error: bad microMIPS opcode " | |
11055 | "(bits 0x%lx defined): %s %s"), | |
11056 | used_bits & ~insn_bits, opc->name, opc->args); | |
11057 | return 0; | |
11058 | } | |
11059 | return 1; | |
11060 | } | |
11061 | ||
9bcd4f99 TS |
11062 | /* UDI immediates. */ |
11063 | struct mips_immed { | |
11064 | char type; | |
11065 | unsigned int shift; | |
11066 | unsigned long mask; | |
11067 | const char * desc; | |
11068 | }; | |
11069 | ||
11070 | static const struct mips_immed mips_immed[] = { | |
11071 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
11072 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
11073 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
11074 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
11075 | { 0,0,0,0 } | |
11076 | }; | |
11077 | ||
7455baf8 TS |
11078 | /* Check whether an odd floating-point register is allowed. */ |
11079 | static int | |
11080 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
11081 | { | |
11082 | const char *s = insn->name; | |
11083 | ||
11084 | if (insn->pinfo == INSN_MACRO) | |
11085 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
11086 | return 1; | |
11087 | ||
e407c74b | 11088 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
11089 | { |
11090 | /* Allow odd registers for single-precision ops. */ | |
11091 | switch (insn->pinfo & (FP_S | FP_D)) | |
11092 | { | |
11093 | case FP_S: | |
11094 | case 0: | |
11095 | return 1; /* both single precision - ok */ | |
11096 | case FP_D: | |
11097 | return 0; /* both double precision - fail */ | |
11098 | default: | |
11099 | break; | |
11100 | } | |
11101 | ||
11102 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
11103 | s = strchr (insn->name, '.'); | |
11104 | if (argnum == 2) | |
11105 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
11106 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
11107 | } | |
11108 | ||
11109 | /* Single-precision coprocessor loads and moves are OK too. */ | |
11110 | if ((insn->pinfo & FP_S) | |
11111 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
11112 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
11113 | return 1; | |
11114 | ||
11115 | return 0; | |
11116 | } | |
11117 | ||
df58fc94 RS |
11118 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
11119 | taking bits from BIT up. */ | |
11120 | static int | |
11121 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
11122 | { | |
11123 | return (ep->X_op == O_constant | |
11124 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
11125 | && ep->X_add_number >= min << bit | |
11126 | && ep->X_add_number < max << bit); | |
11127 | } | |
11128 | ||
252b5132 RH |
11129 | /* This routine assembles an instruction into its binary format. As a |
11130 | side effect, it sets one of the global variables imm_reloc or | |
11131 | offset_reloc to the type of relocation to do if one of the operands | |
11132 | is an address expression. */ | |
11133 | ||
11134 | static void | |
17a2f251 | 11135 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 11136 | { |
df58fc94 RS |
11137 | bfd_boolean wrong_delay_slot_insns = FALSE; |
11138 | bfd_boolean need_delay_slot_ok = TRUE; | |
11139 | struct mips_opcode *firstinsn = NULL; | |
11140 | const struct mips_opcode *past; | |
11141 | struct hash_control *hash; | |
252b5132 RH |
11142 | char *s; |
11143 | const char *args; | |
43841e91 | 11144 | char c = 0; |
252b5132 RH |
11145 | struct mips_opcode *insn; |
11146 | char *argsStart; | |
11147 | unsigned int regno; | |
34224acf | 11148 | unsigned int lastregno; |
df58fc94 | 11149 | unsigned int destregno = 0; |
af7ee8bf | 11150 | unsigned int lastpos = 0; |
071742cf | 11151 | unsigned int limlo, limhi; |
f02d8318 | 11152 | int sizelo; |
252b5132 | 11153 | char *s_reset; |
74cd071d | 11154 | offsetT min_range, max_range; |
df58fc94 | 11155 | long opend; |
a40bc9dd | 11156 | char *name; |
707bfff6 TS |
11157 | int argnum; |
11158 | unsigned int rtype; | |
df58fc94 | 11159 | char *dot; |
a40bc9dd | 11160 | long end; |
252b5132 RH |
11161 | |
11162 | insn_error = NULL; | |
11163 | ||
df58fc94 RS |
11164 | if (mips_opts.micromips) |
11165 | { | |
11166 | hash = micromips_op_hash; | |
11167 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11168 | } | |
11169 | else | |
11170 | { | |
11171 | hash = op_hash; | |
11172 | past = &mips_opcodes[NUMOPCODES]; | |
11173 | } | |
11174 | forced_insn_length = 0; | |
252b5132 | 11175 | insn = NULL; |
252b5132 | 11176 | |
df58fc94 | 11177 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11178 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11179 | continue; | |
bdaaa2e1 | 11180 | |
a40bc9dd RS |
11181 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11182 | name = alloca (end + 1); | |
11183 | memcpy (name, str, end); | |
11184 | name[end] = '\0'; | |
252b5132 | 11185 | |
df58fc94 RS |
11186 | for (;;) |
11187 | { | |
11188 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11189 | ||
11190 | if (insn != NULL || !mips_opts.micromips) | |
11191 | break; | |
11192 | if (forced_insn_length) | |
11193 | break; | |
11194 | ||
11195 | /* See if there's an instruction size override suffix, | |
11196 | either `16' or `32', at the end of the mnemonic proper, | |
11197 | that defines the operation, i.e. before the first `.' | |
11198 | character if any. Strip it and retry. */ | |
11199 | dot = strchr (name, '.'); | |
11200 | opend = dot != NULL ? dot - name : end; | |
11201 | if (opend < 3) | |
11202 | break; | |
11203 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11204 | forced_insn_length = 2; | |
11205 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11206 | forced_insn_length = 4; | |
11207 | else | |
11208 | break; | |
11209 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11210 | } | |
252b5132 RH |
11211 | if (insn == NULL) |
11212 | { | |
a40bc9dd RS |
11213 | insn_error = _("Unrecognized opcode"); |
11214 | return; | |
252b5132 RH |
11215 | } |
11216 | ||
df58fc94 RS |
11217 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11218 | we make up to two passes over the relevant fragment of the opcode | |
11219 | table. First we try instructions that meet the delay slot's length | |
11220 | requirement. If none matched, then we retry with the remaining ones | |
11221 | and if one matches, then we use it and then issue an appropriate | |
11222 | warning later on. */ | |
a40bc9dd | 11223 | argsStart = s = str + end; |
252b5132 RH |
11224 | for (;;) |
11225 | { | |
df58fc94 RS |
11226 | bfd_boolean delay_slot_ok; |
11227 | bfd_boolean size_ok; | |
b34976b6 | 11228 | bfd_boolean ok; |
252b5132 | 11229 | |
a40bc9dd | 11230 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11231 | |
f79e2745 | 11232 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11233 | size_ok = is_size_valid (insn); |
11234 | delay_slot_ok = is_delay_slot_valid (insn); | |
11235 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11236 | { |
df58fc94 RS |
11237 | firstinsn = insn; |
11238 | wrong_delay_slot_insns = TRUE; | |
11239 | } | |
11240 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11241 | { | |
11242 | static char buf[256]; | |
11243 | ||
11244 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11245 | { |
11246 | ++insn; | |
11247 | continue; | |
11248 | } | |
df58fc94 | 11249 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11250 | { |
df58fc94 RS |
11251 | gas_assert (firstinsn); |
11252 | need_delay_slot_ok = FALSE; | |
11253 | past = insn + 1; | |
11254 | insn = firstinsn; | |
11255 | continue; | |
252b5132 | 11256 | } |
df58fc94 RS |
11257 | |
11258 | if (insn_error) | |
11259 | return; | |
11260 | ||
11261 | if (!ok) | |
7bd942df | 11262 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11263 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11264 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11265 | else | |
11266 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11267 | 8 * forced_insn_length); | |
11268 | insn_error = buf; | |
11269 | ||
11270 | return; | |
252b5132 RH |
11271 | } |
11272 | ||
1e915849 | 11273 | create_insn (ip, insn); |
268f6bed | 11274 | insn_error = NULL; |
707bfff6 | 11275 | argnum = 1; |
24864476 | 11276 | lastregno = 0xffffffff; |
252b5132 RH |
11277 | for (args = insn->args;; ++args) |
11278 | { | |
deec1734 CD |
11279 | int is_mdmx; |
11280 | ||
ad8d3bb3 | 11281 | s += strspn (s, " \t"); |
deec1734 | 11282 | is_mdmx = 0; |
252b5132 RH |
11283 | switch (*args) |
11284 | { | |
11285 | case '\0': /* end of args */ | |
11286 | if (*s == '\0') | |
11287 | return; | |
11288 | break; | |
11289 | ||
03f66e8a MR |
11290 | case '2': |
11291 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11292 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11293 | my_getExpression (&imm_expr, s); |
11294 | check_absolute_expr (ip, &imm_expr); | |
11295 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11296 | && (unsigned long) imm_expr.X_add_number != 3) | |
11297 | { | |
11298 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11299 | (unsigned long) imm_expr.X_add_number); | |
11300 | } | |
03f66e8a MR |
11301 | INSERT_OPERAND (mips_opts.micromips, |
11302 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11303 | imm_expr.X_op = O_absent; |
11304 | s = expr_end; | |
11305 | continue; | |
11306 | ||
03f66e8a MR |
11307 | case '3': |
11308 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
11309 | code) or 21 (for microMIPS code). */ | |
11310 | { | |
11311 | unsigned long mask = (mips_opts.micromips | |
11312 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11313 | ||
11314 | my_getExpression (&imm_expr, s); | |
11315 | check_absolute_expr (ip, &imm_expr); | |
11316 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11317 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11318 | mask, (unsigned long) imm_expr.X_add_number); | |
11319 | INSERT_OPERAND (mips_opts.micromips, | |
11320 | SA3, *ip, imm_expr.X_add_number); | |
11321 | imm_expr.X_op = O_absent; | |
11322 | s = expr_end; | |
11323 | } | |
74cd071d CF |
11324 | continue; |
11325 | ||
03f66e8a MR |
11326 | case '4': |
11327 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
11328 | code) or 21 (for microMIPS code). */ | |
11329 | { | |
11330 | unsigned long mask = (mips_opts.micromips | |
11331 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11332 | ||
11333 | my_getExpression (&imm_expr, s); | |
11334 | check_absolute_expr (ip, &imm_expr); | |
11335 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11336 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11337 | mask, (unsigned long) imm_expr.X_add_number); | |
11338 | INSERT_OPERAND (mips_opts.micromips, | |
11339 | SA4, *ip, imm_expr.X_add_number); | |
11340 | imm_expr.X_op = O_absent; | |
11341 | s = expr_end; | |
11342 | } | |
74cd071d CF |
11343 | continue; |
11344 | ||
03f66e8a MR |
11345 | case '5': |
11346 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
11347 | code) or 16 (for microMIPS code). */ | |
11348 | { | |
11349 | unsigned long mask = (mips_opts.micromips | |
11350 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11351 | ||
11352 | my_getExpression (&imm_expr, s); | |
11353 | check_absolute_expr (ip, &imm_expr); | |
11354 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11355 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11356 | mask, (unsigned long) imm_expr.X_add_number); | |
11357 | INSERT_OPERAND (mips_opts.micromips, | |
11358 | IMM8, *ip, imm_expr.X_add_number); | |
11359 | imm_expr.X_op = O_absent; | |
11360 | s = expr_end; | |
11361 | } | |
74cd071d CF |
11362 | continue; |
11363 | ||
03f66e8a MR |
11364 | case '6': |
11365 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
11366 | code) or 21 (for microMIPS code). */ | |
11367 | { | |
11368 | unsigned long mask = (mips_opts.micromips | |
11369 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11370 | ||
11371 | my_getExpression (&imm_expr, s); | |
11372 | check_absolute_expr (ip, &imm_expr); | |
11373 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11374 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11375 | mask, (unsigned long) imm_expr.X_add_number); | |
11376 | INSERT_OPERAND (mips_opts.micromips, | |
11377 | RS, *ip, imm_expr.X_add_number); | |
11378 | imm_expr.X_op = O_absent; | |
11379 | s = expr_end; | |
11380 | } | |
74cd071d CF |
11381 | continue; |
11382 | ||
90ecf173 | 11383 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
11384 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11385 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11386 | { |
11387 | regno = s[3] - '0'; | |
11388 | s += 4; | |
03f66e8a | 11389 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11390 | continue; |
11391 | } | |
11392 | else | |
11393 | as_bad (_("Invalid dsp acc register")); | |
11394 | break; | |
11395 | ||
03f66e8a MR |
11396 | case '8': |
11397 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11398 | code) or 14 (for microMIPS code). */ | |
11399 | { | |
11400 | unsigned long mask = (mips_opts.micromips | |
11401 | ? MICROMIPSOP_MASK_WRDSP | |
11402 | : OP_MASK_WRDSP); | |
11403 | ||
11404 | my_getExpression (&imm_expr, s); | |
11405 | check_absolute_expr (ip, &imm_expr); | |
11406 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11407 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11408 | mask, (unsigned long) imm_expr.X_add_number); | |
11409 | INSERT_OPERAND (mips_opts.micromips, | |
11410 | WRDSP, *ip, imm_expr.X_add_number); | |
11411 | imm_expr.X_op = O_absent; | |
11412 | s = expr_end; | |
11413 | } | |
74cd071d CF |
11414 | continue; |
11415 | ||
90ecf173 | 11416 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11417 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11418 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11419 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11420 | { |
11421 | regno = s[3] - '0'; | |
11422 | s += 4; | |
df58fc94 | 11423 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11424 | continue; |
11425 | } | |
11426 | else | |
11427 | as_bad (_("Invalid dsp acc register")); | |
11428 | break; | |
11429 | ||
03f66e8a MR |
11430 | case '0': |
11431 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
11432 | code) or 20 (for microMIPS code). */ | |
11433 | { | |
11434 | long mask = (mips_opts.micromips | |
11435 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11436 | ||
11437 | my_getExpression (&imm_expr, s); | |
11438 | check_absolute_expr (ip, &imm_expr); | |
11439 | min_range = -((mask + 1) >> 1); | |
11440 | max_range = ((mask + 1) >> 1) - 1; | |
11441 | if (imm_expr.X_add_number < min_range | |
11442 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11443 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11444 | (long) min_range, (long) max_range, | |
11445 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11446 | INSERT_OPERAND (mips_opts.micromips, |
11447 | DSPSFT, *ip, imm_expr.X_add_number); | |
11448 | imm_expr.X_op = O_absent; | |
11449 | s = expr_end; | |
11450 | } | |
74cd071d CF |
11451 | continue; |
11452 | ||
90ecf173 | 11453 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11454 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11455 | my_getExpression (&imm_expr, s); |
11456 | check_absolute_expr (ip, &imm_expr); | |
11457 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11458 | { | |
a9e24354 TS |
11459 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11460 | OP_MASK_RDDSP, | |
11461 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11462 | } |
df58fc94 | 11463 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11464 | imm_expr.X_op = O_absent; |
11465 | s = expr_end; | |
11466 | continue; | |
11467 | ||
90ecf173 | 11468 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11469 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11470 | my_getExpression (&imm_expr, s); |
11471 | check_absolute_expr (ip, &imm_expr); | |
11472 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11473 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11474 | if (imm_expr.X_add_number < min_range || | |
11475 | imm_expr.X_add_number > max_range) | |
11476 | { | |
a9e24354 TS |
11477 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11478 | (long) min_range, (long) max_range, | |
11479 | (long) imm_expr.X_add_number); | |
74cd071d | 11480 | } |
df58fc94 | 11481 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11482 | imm_expr.X_op = O_absent; |
11483 | s = expr_end; | |
11484 | continue; | |
11485 | ||
90ecf173 | 11486 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11487 | { |
11488 | long mask = (mips_opts.micromips | |
11489 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11490 | ||
11491 | my_getExpression (&imm_expr, s); | |
11492 | check_absolute_expr (ip, &imm_expr); | |
11493 | min_range = -((mask + 1) >> 1); | |
11494 | max_range = ((mask + 1) >> 1) - 1; | |
11495 | if (imm_expr.X_add_number < min_range | |
11496 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11497 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11498 | (long) min_range, (long) max_range, | |
11499 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11500 | INSERT_OPERAND (mips_opts.micromips, |
11501 | IMM10, *ip, imm_expr.X_add_number); | |
11502 | imm_expr.X_op = O_absent; | |
11503 | s = expr_end; | |
11504 | } | |
11505 | continue; | |
11506 | ||
11507 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11508 | gas_assert (mips_opts.micromips); | |
11509 | my_getExpression (&imm_expr, s); | |
11510 | check_absolute_expr (ip, &imm_expr); | |
11511 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11512 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11513 | MICROMIPSOP_MASK_RD, | |
11514 | (unsigned long) imm_expr.X_add_number); | |
11515 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11516 | imm_expr.X_op = O_absent; |
11517 | s = expr_end; | |
11518 | continue; | |
11519 | ||
a9e24354 | 11520 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11521 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11522 | my_getExpression (&imm_expr, s); |
11523 | check_absolute_expr (ip, &imm_expr); | |
11524 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11525 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11526 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11527 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11528 | imm_expr.X_op = O_absent; |
11529 | s = expr_end; | |
11530 | continue; | |
11531 | ||
a9e24354 | 11532 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11533 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11534 | my_getExpression (&imm_expr, s); |
11535 | check_absolute_expr (ip, &imm_expr); | |
11536 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11537 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11538 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11539 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11540 | imm_expr.X_op = O_absent; |
11541 | s = expr_end; | |
11542 | continue; | |
11543 | ||
90ecf173 | 11544 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11545 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11546 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11547 | s[3] >= '0' && s[3] <= '3') | |
11548 | { | |
11549 | regno = s[3] - '0'; | |
11550 | s += 4; | |
df58fc94 | 11551 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11552 | continue; |
11553 | } | |
11554 | else | |
11555 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11556 | break; | |
11557 | ||
90ecf173 | 11558 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11559 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11560 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11561 | s[3] >= '0' && s[3] <= '3') | |
11562 | { | |
11563 | regno = s[3] - '0'; | |
11564 | s += 4; | |
df58fc94 | 11565 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11566 | continue; |
11567 | } | |
11568 | else | |
11569 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11570 | break; | |
11571 | ||
dec0624d MR |
11572 | case '\\': /* 3-bit bit position. */ |
11573 | { | |
2906b037 MR |
11574 | unsigned long mask = (mips_opts.micromips |
11575 | ? MICROMIPSOP_MASK_3BITPOS | |
11576 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11577 | |
11578 | my_getExpression (&imm_expr, s); | |
11579 | check_absolute_expr (ip, &imm_expr); | |
11580 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11581 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11582 | ip->insn_mo->name, | |
11583 | mask, (unsigned long) imm_expr.X_add_number); | |
11584 | INSERT_OPERAND (mips_opts.micromips, | |
11585 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11586 | imm_expr.X_op = O_absent; | |
11587 | s = expr_end; | |
11588 | } | |
11589 | continue; | |
11590 | ||
252b5132 | 11591 | case ',': |
a339155f | 11592 | ++argnum; |
252b5132 RH |
11593 | if (*s++ == *args) |
11594 | continue; | |
11595 | s--; | |
11596 | switch (*++args) | |
11597 | { | |
11598 | case 'r': | |
11599 | case 'v': | |
df58fc94 | 11600 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11601 | continue; |
11602 | ||
11603 | case 'w': | |
df58fc94 | 11604 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11605 | continue; |
11606 | ||
252b5132 | 11607 | case 'W': |
df58fc94 RS |
11608 | gas_assert (!mips_opts.micromips); |
11609 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11610 | continue; |
11611 | ||
11612 | case 'V': | |
df58fc94 | 11613 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11614 | continue; |
11615 | } | |
11616 | break; | |
11617 | ||
11618 | case '(': | |
11619 | /* Handle optional base register. | |
11620 | Either the base register is omitted or | |
bdaaa2e1 | 11621 | we must have a left paren. */ |
252b5132 RH |
11622 | /* This is dependent on the next operand specifier |
11623 | is a base register specification. */ | |
df58fc94 RS |
11624 | gas_assert (args[1] == 'b' |
11625 | || (mips_opts.micromips | |
11626 | && args[1] == 'm' | |
11627 | && (args[2] == 'l' || args[2] == 'n' | |
11628 | || args[2] == 's' || args[2] == 'a'))); | |
11629 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11630 | return; |
df58fc94 | 11631 | /* Fall through. */ |
252b5132 | 11632 | |
90ecf173 | 11633 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11634 | if (*s++ == *args) |
11635 | continue; | |
11636 | break; | |
11637 | ||
11638 | case '[': /* These must match exactly. */ | |
60b63b72 | 11639 | case ']': |
df58fc94 | 11640 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11641 | if (*s++ == *args) |
11642 | continue; | |
11643 | break; | |
11644 | ||
af7ee8bf CD |
11645 | case '+': /* Opcode extension character. */ |
11646 | switch (*++args) | |
11647 | { | |
9bcd4f99 TS |
11648 | case '1': /* UDI immediates. */ |
11649 | case '2': | |
11650 | case '3': | |
11651 | case '4': | |
df58fc94 | 11652 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11653 | { |
11654 | const struct mips_immed *imm = mips_immed; | |
11655 | ||
11656 | while (imm->type && imm->type != *args) | |
11657 | ++imm; | |
11658 | if (! imm->type) | |
b37df7c4 | 11659 | abort (); |
9bcd4f99 TS |
11660 | my_getExpression (&imm_expr, s); |
11661 | check_absolute_expr (ip, &imm_expr); | |
11662 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11663 | { | |
11664 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11665 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11666 | (unsigned long) imm_expr.X_add_number, | |
11667 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11668 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11669 | } |
11670 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11671 | << imm->shift); | |
11672 | imm_expr.X_op = O_absent; | |
11673 | s = expr_end; | |
11674 | } | |
11675 | continue; | |
90ecf173 | 11676 | |
b015e599 AP |
11677 | case 'J': /* 10-bit hypcall code. */ |
11678 | gas_assert (!mips_opts.micromips); | |
11679 | { | |
11680 | unsigned long mask = OP_MASK_CODE10; | |
11681 | ||
11682 | my_getExpression (&imm_expr, s); | |
11683 | check_absolute_expr (ip, &imm_expr); | |
11684 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11685 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11686 | ip->insn_mo->name, | |
11687 | mask, (unsigned long) imm_expr.X_add_number); | |
11688 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11689 | imm_expr.X_op = O_absent; | |
11690 | s = expr_end; | |
11691 | } | |
11692 | continue; | |
11693 | ||
071742cf CD |
11694 | case 'A': /* ins/ext position, becomes LSB. */ |
11695 | limlo = 0; | |
11696 | limhi = 31; | |
5f74bc13 CD |
11697 | goto do_lsb; |
11698 | case 'E': | |
11699 | limlo = 32; | |
11700 | limhi = 63; | |
11701 | goto do_lsb; | |
90ecf173 | 11702 | do_lsb: |
071742cf CD |
11703 | my_getExpression (&imm_expr, s); |
11704 | check_absolute_expr (ip, &imm_expr); | |
11705 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11706 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11707 | { | |
11708 | as_bad (_("Improper position (%lu)"), | |
11709 | (unsigned long) imm_expr.X_add_number); | |
11710 | imm_expr.X_add_number = limlo; | |
11711 | } | |
11712 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11713 | INSERT_OPERAND (mips_opts.micromips, |
11714 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11715 | imm_expr.X_op = O_absent; |
11716 | s = expr_end; | |
11717 | continue; | |
11718 | ||
11719 | case 'B': /* ins size, becomes MSB. */ | |
11720 | limlo = 1; | |
11721 | limhi = 32; | |
5f74bc13 CD |
11722 | goto do_msb; |
11723 | case 'F': | |
11724 | limlo = 33; | |
11725 | limhi = 64; | |
11726 | goto do_msb; | |
90ecf173 | 11727 | do_msb: |
071742cf CD |
11728 | my_getExpression (&imm_expr, s); |
11729 | check_absolute_expr (ip, &imm_expr); | |
11730 | /* Check for negative input so that small negative numbers | |
11731 | will not succeed incorrectly. The checks against | |
11732 | (pos+size) transitively check "size" itself, | |
11733 | assuming that "pos" is reasonable. */ | |
11734 | if ((long) imm_expr.X_add_number < 0 | |
11735 | || ((unsigned long) imm_expr.X_add_number | |
11736 | + lastpos) < limlo | |
11737 | || ((unsigned long) imm_expr.X_add_number | |
11738 | + lastpos) > limhi) | |
11739 | { | |
11740 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11741 | (unsigned long) imm_expr.X_add_number, | |
11742 | (unsigned long) lastpos); | |
11743 | imm_expr.X_add_number = limlo - lastpos; | |
11744 | } | |
df58fc94 RS |
11745 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11746 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11747 | imm_expr.X_op = O_absent; |
11748 | s = expr_end; | |
11749 | continue; | |
11750 | ||
11751 | case 'C': /* ext size, becomes MSBD. */ | |
11752 | limlo = 1; | |
11753 | limhi = 32; | |
f02d8318 | 11754 | sizelo = 1; |
5f74bc13 CD |
11755 | goto do_msbd; |
11756 | case 'G': | |
11757 | limlo = 33; | |
11758 | limhi = 64; | |
f02d8318 | 11759 | sizelo = 33; |
5f74bc13 CD |
11760 | goto do_msbd; |
11761 | case 'H': | |
11762 | limlo = 33; | |
11763 | limhi = 64; | |
f02d8318 | 11764 | sizelo = 1; |
5f74bc13 | 11765 | goto do_msbd; |
90ecf173 | 11766 | do_msbd: |
071742cf CD |
11767 | my_getExpression (&imm_expr, s); |
11768 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11769 | /* The checks against (pos+size) don't transitively check |
11770 | "size" itself, assuming that "pos" is reasonable. | |
11771 | We also need to check the lower bound of "size". */ | |
11772 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11773 | || ((unsigned long) imm_expr.X_add_number |
11774 | + lastpos) < limlo | |
11775 | || ((unsigned long) imm_expr.X_add_number | |
11776 | + lastpos) > limhi) | |
11777 | { | |
11778 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11779 | (unsigned long) imm_expr.X_add_number, | |
11780 | (unsigned long) lastpos); | |
11781 | imm_expr.X_add_number = limlo - lastpos; | |
11782 | } | |
df58fc94 RS |
11783 | INSERT_OPERAND (mips_opts.micromips, |
11784 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11785 | imm_expr.X_op = O_absent; |
11786 | s = expr_end; | |
11787 | continue; | |
af7ee8bf | 11788 | |
bbcc0807 CD |
11789 | case 'D': |
11790 | /* +D is for disassembly only; never match. */ | |
11791 | break; | |
11792 | ||
5f74bc13 CD |
11793 | case 'I': |
11794 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11795 | my_getExpression (&imm2_expr, s); | |
11796 | if (imm2_expr.X_op != O_big | |
11797 | && imm2_expr.X_op != O_constant) | |
11798 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11799 | if (HAVE_32BIT_GPRS) |
11800 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11801 | s = expr_end; |
11802 | continue; | |
11803 | ||
707bfff6 | 11804 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11805 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11806 | /* +T is for disassembly only; never match. */ |
11807 | break; | |
11808 | ||
707bfff6 | 11809 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11810 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11811 | if (s[0] == '$' && ISDIGIT (s[1])) |
11812 | { | |
11813 | ++s; | |
11814 | regno = 0; | |
11815 | do | |
11816 | { | |
11817 | regno *= 10; | |
11818 | regno += *s - '0'; | |
11819 | ++s; | |
11820 | } | |
11821 | while (ISDIGIT (*s)); | |
11822 | if (regno > 31) | |
11823 | as_bad (_("Invalid register number (%d)"), regno); | |
11824 | else | |
11825 | { | |
df58fc94 | 11826 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11827 | continue; |
11828 | } | |
11829 | } | |
11830 | else | |
11831 | as_bad (_("Invalid coprocessor 0 register number")); | |
11832 | break; | |
11833 | ||
bb35fb24 NC |
11834 | case 'x': |
11835 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11836 | is not in the valid range. */ | |
df58fc94 | 11837 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11838 | my_getExpression (&imm_expr, s); |
11839 | check_absolute_expr (ip, &imm_expr); | |
11840 | if ((unsigned) imm_expr.X_add_number > 31) | |
11841 | { | |
11842 | as_bad (_("Improper bit index (%lu)"), | |
11843 | (unsigned long) imm_expr.X_add_number); | |
11844 | imm_expr.X_add_number = 0; | |
11845 | } | |
df58fc94 | 11846 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11847 | imm_expr.X_op = O_absent; |
11848 | s = expr_end; | |
11849 | continue; | |
11850 | ||
11851 | case 'X': | |
11852 | /* bbit[01] bit index when bbit is used but we generate | |
11853 | bbit[01]32 because the index is over 32. Move to the | |
11854 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11855 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11856 | my_getExpression (&imm_expr, s); |
11857 | check_absolute_expr (ip, &imm_expr); | |
11858 | if ((unsigned) imm_expr.X_add_number < 32 | |
11859 | || (unsigned) imm_expr.X_add_number > 63) | |
11860 | break; | |
df58fc94 | 11861 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11862 | imm_expr.X_op = O_absent; |
11863 | s = expr_end; | |
11864 | continue; | |
11865 | ||
11866 | case 'p': | |
11867 | /* cins, cins32, exts and exts32 position field. Give error | |
11868 | if it's not in the valid range. */ | |
df58fc94 | 11869 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11870 | my_getExpression (&imm_expr, s); |
11871 | check_absolute_expr (ip, &imm_expr); | |
11872 | if ((unsigned) imm_expr.X_add_number > 31) | |
11873 | { | |
11874 | as_bad (_("Improper position (%lu)"), | |
11875 | (unsigned long) imm_expr.X_add_number); | |
11876 | imm_expr.X_add_number = 0; | |
11877 | } | |
11878 | /* Make the pos explicit to simplify +S. */ | |
11879 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11880 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11881 | imm_expr.X_op = O_absent; |
11882 | s = expr_end; | |
11883 | continue; | |
11884 | ||
11885 | case 'P': | |
11886 | /* cins, cins32, exts and exts32 position field. Move to | |
11887 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11888 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11889 | my_getExpression (&imm_expr, s); |
11890 | check_absolute_expr (ip, &imm_expr); | |
11891 | if ((unsigned) imm_expr.X_add_number < 32 | |
11892 | || (unsigned) imm_expr.X_add_number > 63) | |
11893 | break; | |
11894 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11895 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11896 | imm_expr.X_op = O_absent; |
11897 | s = expr_end; | |
11898 | continue; | |
11899 | ||
11900 | case 's': | |
11901 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11902 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11903 | my_getExpression (&imm_expr, s); |
11904 | check_absolute_expr (ip, &imm_expr); | |
11905 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11906 | { | |
11907 | as_bad (_("Improper size (%lu)"), | |
11908 | (unsigned long) imm_expr.X_add_number); | |
11909 | imm_expr.X_add_number = 0; | |
11910 | } | |
df58fc94 | 11911 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11912 | imm_expr.X_op = O_absent; |
11913 | s = expr_end; | |
11914 | continue; | |
11915 | ||
11916 | case 'S': | |
11917 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11918 | length-minus-one field. */ | |
df58fc94 | 11919 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11920 | my_getExpression (&imm_expr, s); |
11921 | check_absolute_expr (ip, &imm_expr); | |
11922 | if ((long) imm_expr.X_add_number < 0 | |
11923 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11924 | { | |
11925 | as_bad (_("Improper size (%lu)"), | |
11926 | (unsigned long) imm_expr.X_add_number); | |
11927 | imm_expr.X_add_number = 0; | |
11928 | } | |
df58fc94 | 11929 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11930 | imm_expr.X_op = O_absent; |
11931 | s = expr_end; | |
11932 | continue; | |
11933 | ||
dd3cbb7e NC |
11934 | case 'Q': |
11935 | /* seqi/snei immediate field. */ | |
df58fc94 | 11936 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11937 | my_getExpression (&imm_expr, s); |
11938 | check_absolute_expr (ip, &imm_expr); | |
11939 | if ((long) imm_expr.X_add_number < -512 | |
11940 | || (long) imm_expr.X_add_number >= 512) | |
11941 | { | |
11942 | as_bad (_("Improper immediate (%ld)"), | |
11943 | (long) imm_expr.X_add_number); | |
11944 | imm_expr.X_add_number = 0; | |
11945 | } | |
df58fc94 | 11946 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11947 | imm_expr.X_op = O_absent; |
11948 | s = expr_end; | |
11949 | continue; | |
11950 | ||
98675402 | 11951 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11952 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11953 | my_getExpression (&imm_expr, s); |
11954 | check_absolute_expr (ip, &imm_expr); | |
11955 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11956 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11957 | if (imm_expr.X_add_number < min_range | |
11958 | || imm_expr.X_add_number > max_range) | |
11959 | { | |
c95354ed | 11960 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11961 | (long) min_range, (long) max_range, |
11962 | (long) imm_expr.X_add_number); | |
11963 | } | |
df58fc94 | 11964 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11965 | imm_expr.X_op = O_absent; |
11966 | s = expr_end; | |
11967 | continue; | |
11968 | ||
11969 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11970 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11971 | my_getExpression (&imm_expr, s); |
11972 | check_absolute_expr (ip, &imm_expr); | |
11973 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11974 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11975 | if (imm_expr.X_add_number < min_range | |
11976 | || imm_expr.X_add_number > max_range) | |
11977 | { | |
c95354ed | 11978 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11979 | (long) min_range, (long) max_range, |
11980 | (long) imm_expr.X_add_number); | |
11981 | } | |
df58fc94 | 11982 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11983 | imm_expr.X_op = O_absent; |
11984 | s = expr_end; | |
11985 | continue; | |
11986 | ||
11987 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11988 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11989 | my_getExpression (&imm_expr, s); |
11990 | check_absolute_expr (ip, &imm_expr); | |
11991 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11992 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11993 | /* We check the offset range before adjusted. */ |
11994 | min_range <<= 4; | |
11995 | max_range <<= 4; | |
98675402 RS |
11996 | if (imm_expr.X_add_number < min_range |
11997 | || imm_expr.X_add_number > max_range) | |
11998 | { | |
c95354ed | 11999 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12000 | (long) min_range, (long) max_range, |
12001 | (long) imm_expr.X_add_number); | |
12002 | } | |
c95354ed MX |
12003 | if (imm_expr.X_add_number & 0xf) |
12004 | { | |
12005 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
12006 | (long) imm_expr.X_add_number); | |
12007 | } | |
12008 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
12009 | INSERT_OPERAND (0, OFFSET_C, *ip, |
12010 | imm_expr.X_add_number >> 4); | |
98675402 RS |
12011 | imm_expr.X_op = O_absent; |
12012 | s = expr_end; | |
12013 | continue; | |
12014 | ||
12015 | case 'z': | |
df58fc94 | 12016 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12017 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
12018 | break; | |
12019 | if (regno == AT && mips_opts.at) | |
12020 | { | |
12021 | if (mips_opts.at == ATREG) | |
12022 | as_warn (_("used $at without \".set noat\"")); | |
12023 | else | |
12024 | as_warn (_("used $%u with \".set at=$%u\""), | |
12025 | regno, mips_opts.at); | |
12026 | } | |
df58fc94 | 12027 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
12028 | continue; |
12029 | ||
12030 | case 'Z': | |
df58fc94 | 12031 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12032 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
12033 | break; | |
df58fc94 | 12034 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
12035 | continue; |
12036 | ||
7f3c4072 CM |
12037 | case 'j': |
12038 | { | |
12039 | int shift = 8; | |
12040 | size_t i; | |
12041 | /* Check whether there is only a single bracketed expression | |
12042 | left. If so, it must be the base register and the | |
12043 | constant must be zero. */ | |
12044 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12045 | continue; | |
12046 | ||
12047 | /* If this value won't fit into the offset, then go find | |
12048 | a macro that will generate a 16- or 32-bit offset code | |
12049 | pattern. */ | |
12050 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12051 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12052 | || imm_expr.X_add_number >= 1 << shift | |
12053 | || imm_expr.X_add_number < -1 << shift)) | |
12054 | || i > 0) | |
12055 | { | |
12056 | imm_expr.X_op = O_absent; | |
12057 | break; | |
12058 | } | |
12059 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
12060 | imm_expr.X_add_number); | |
12061 | imm_expr.X_op = O_absent; | |
12062 | s = expr_end; | |
12063 | } | |
12064 | continue; | |
12065 | ||
af7ee8bf | 12066 | default: |
df58fc94 | 12067 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 12068 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 12069 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 12070 | *args, insn->name, insn->args); |
af7ee8bf CD |
12071 | /* Further processing is fruitless. */ |
12072 | return; | |
12073 | } | |
12074 | break; | |
12075 | ||
df58fc94 | 12076 | case '.': /* 10-bit offset. */ |
df58fc94 | 12077 | gas_assert (mips_opts.micromips); |
dec0624d | 12078 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
12079 | { |
12080 | int shift = *args == '.' ? 9 : 11; | |
12081 | size_t i; | |
12082 | ||
12083 | /* Check whether there is only a single bracketed expression | |
12084 | left. If so, it must be the base register and the | |
12085 | constant must be zero. */ | |
12086 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12087 | continue; | |
12088 | ||
12089 | /* If this value won't fit into the offset, then go find | |
12090 | a macro that will generate a 16- or 32-bit offset code | |
12091 | pattern. */ | |
12092 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
12093 | if ((i == 0 && (imm_expr.X_op != O_constant | |
12094 | || imm_expr.X_add_number >= 1 << shift | |
12095 | || imm_expr.X_add_number < -1 << shift)) | |
12096 | || i > 0) | |
12097 | { | |
12098 | imm_expr.X_op = O_absent; | |
12099 | break; | |
12100 | } | |
12101 | if (shift == 9) | |
12102 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
12103 | else | |
dec0624d MR |
12104 | INSERT_OPERAND (mips_opts.micromips, |
12105 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
12106 | imm_expr.X_op = O_absent; |
12107 | s = expr_end; | |
12108 | } | |
12109 | continue; | |
12110 | ||
252b5132 RH |
12111 | case '<': /* must be at least one digit */ |
12112 | /* | |
12113 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
12114 | * than 31 or less than 0, then the shift amount should be |
12115 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
12116 | * We issue a warning and mask out all but the low 5 bits. |
12117 | */ | |
12118 | my_getExpression (&imm_expr, s); | |
12119 | check_absolute_expr (ip, &imm_expr); | |
12120 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12121 | as_warn (_("Improper shift amount (%lu)"), |
12122 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
12123 | INSERT_OPERAND (mips_opts.micromips, |
12124 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
12125 | imm_expr.X_op = O_absent; |
12126 | s = expr_end; | |
12127 | continue; | |
12128 | ||
12129 | case '>': /* shift amount minus 32 */ | |
12130 | my_getExpression (&imm_expr, s); | |
12131 | check_absolute_expr (ip, &imm_expr); | |
12132 | if ((unsigned long) imm_expr.X_add_number < 32 | |
12133 | || (unsigned long) imm_expr.X_add_number > 63) | |
12134 | break; | |
df58fc94 RS |
12135 | INSERT_OPERAND (mips_opts.micromips, |
12136 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
12137 | imm_expr.X_op = O_absent; |
12138 | s = expr_end; | |
12139 | continue; | |
12140 | ||
90ecf173 MR |
12141 | case 'k': /* CACHE code. */ |
12142 | case 'h': /* PREFX code. */ | |
12143 | case '1': /* SYNC type. */ | |
252b5132 RH |
12144 | my_getExpression (&imm_expr, s); |
12145 | check_absolute_expr (ip, &imm_expr); | |
12146 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12147 | as_warn (_("Invalid value for `%s' (%lu)"), |
12148 | ip->insn_mo->name, | |
12149 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12150 | switch (*args) |
d954098f | 12151 | { |
df58fc94 RS |
12152 | case 'k': |
12153 | if (mips_fix_cn63xxp1 | |
12154 | && !mips_opts.micromips | |
12155 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12156 | switch (imm_expr.X_add_number) |
12157 | { | |
12158 | case 5: | |
12159 | case 25: | |
12160 | case 26: | |
12161 | case 27: | |
12162 | case 28: | |
12163 | case 29: | |
12164 | case 30: | |
12165 | case 31: /* These are ok. */ | |
12166 | break; | |
12167 | ||
12168 | default: /* The rest must be changed to 28. */ | |
12169 | imm_expr.X_add_number = 28; | |
12170 | break; | |
12171 | } | |
df58fc94 RS |
12172 | INSERT_OPERAND (mips_opts.micromips, |
12173 | CACHE, *ip, imm_expr.X_add_number); | |
12174 | break; | |
12175 | case 'h': | |
12176 | INSERT_OPERAND (mips_opts.micromips, | |
12177 | PREFX, *ip, imm_expr.X_add_number); | |
12178 | break; | |
12179 | case '1': | |
12180 | INSERT_OPERAND (mips_opts.micromips, | |
12181 | STYPE, *ip, imm_expr.X_add_number); | |
12182 | break; | |
d954098f | 12183 | } |
252b5132 RH |
12184 | imm_expr.X_op = O_absent; |
12185 | s = expr_end; | |
12186 | continue; | |
12187 | ||
90ecf173 | 12188 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12189 | { |
12190 | unsigned long mask = (mips_opts.micromips | |
12191 | ? MICROMIPSOP_MASK_CODE | |
12192 | : OP_MASK_CODE); | |
12193 | ||
12194 | my_getExpression (&imm_expr, s); | |
12195 | check_absolute_expr (ip, &imm_expr); | |
12196 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12197 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12198 | ip->insn_mo->name, | |
12199 | mask, (unsigned long) imm_expr.X_add_number); | |
12200 | INSERT_OPERAND (mips_opts.micromips, | |
12201 | CODE, *ip, imm_expr.X_add_number); | |
12202 | imm_expr.X_op = O_absent; | |
12203 | s = expr_end; | |
12204 | } | |
252b5132 RH |
12205 | continue; |
12206 | ||
90ecf173 | 12207 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12208 | { |
12209 | unsigned long mask = (mips_opts.micromips | |
12210 | ? MICROMIPSOP_MASK_CODE2 | |
12211 | : OP_MASK_CODE2); | |
12212 | ||
12213 | my_getExpression (&imm_expr, s); | |
12214 | check_absolute_expr (ip, &imm_expr); | |
12215 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12216 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12217 | ip->insn_mo->name, | |
12218 | mask, (unsigned long) imm_expr.X_add_number); | |
12219 | INSERT_OPERAND (mips_opts.micromips, | |
12220 | CODE2, *ip, imm_expr.X_add_number); | |
12221 | imm_expr.X_op = O_absent; | |
12222 | s = expr_end; | |
12223 | } | |
252b5132 RH |
12224 | continue; |
12225 | ||
df58fc94 RS |
12226 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12227 | { | |
12228 | unsigned long mask = (mips_opts.micromips | |
12229 | ? MICROMIPSOP_MASK_CODE10 | |
12230 | : OP_MASK_CODE20); | |
12231 | ||
12232 | my_getExpression (&imm_expr, s); | |
12233 | check_absolute_expr (ip, &imm_expr); | |
12234 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12235 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12236 | ip->insn_mo->name, | |
12237 | mask, (unsigned long) imm_expr.X_add_number); | |
12238 | if (mips_opts.micromips) | |
12239 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12240 | else | |
12241 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12242 | imm_expr.X_op = O_absent; | |
12243 | s = expr_end; | |
12244 | } | |
252b5132 RH |
12245 | continue; |
12246 | ||
df58fc94 RS |
12247 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12248 | { | |
12249 | unsigned long mask = (mips_opts.micromips | |
12250 | ? MICROMIPSOP_MASK_COPZ | |
12251 | : OP_MASK_COPZ); | |
12252 | ||
12253 | my_getExpression (&imm_expr, s); | |
12254 | check_absolute_expr (ip, &imm_expr); | |
12255 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12256 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12257 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12258 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12259 | INSERT_OPERAND (mips_opts.micromips, |
12260 | COPZ, *ip, imm_expr.X_add_number); | |
12261 | imm_expr.X_op = O_absent; | |
12262 | s = expr_end; | |
12263 | } | |
beae10d5 | 12264 | continue; |
252b5132 | 12265 | |
df58fc94 RS |
12266 | case 'J': /* 19-bit WAIT code. */ |
12267 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12268 | my_getExpression (&imm_expr, s); |
12269 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12270 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12271 | { |
12272 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12273 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12274 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12275 | } | |
12276 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12277 | imm_expr.X_op = O_absent; |
12278 | s = expr_end; | |
12279 | continue; | |
12280 | ||
707bfff6 | 12281 | case 'P': /* Performance register. */ |
df58fc94 | 12282 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12283 | my_getExpression (&imm_expr, s); |
252b5132 | 12284 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12285 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12286 | as_warn (_("Invalid performance register (%lu)"), |
12287 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12288 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12289 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12290 | as_warn (_("Invalid performance register (%lu)"), | |
12291 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12292 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12293 | imm_expr.X_op = O_absent; |
12294 | s = expr_end; | |
12295 | continue; | |
252b5132 | 12296 | |
707bfff6 | 12297 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12298 | { |
12299 | unsigned long opcode = ip->insn_opcode; | |
12300 | unsigned long mask; | |
12301 | unsigned int types; | |
12302 | int cop0; | |
12303 | ||
12304 | if (mips_opts.micromips) | |
12305 | { | |
12306 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12307 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12308 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12309 | opcode &= mask; | |
12310 | switch (opcode) | |
12311 | { | |
12312 | case 0x000000fc: /* mfc0 */ | |
12313 | case 0x000002fc: /* mtc0 */ | |
12314 | case 0x580000fc: /* dmfc0 */ | |
12315 | case 0x580002fc: /* dmtc0 */ | |
12316 | cop0 = 1; | |
12317 | break; | |
12318 | default: | |
12319 | cop0 = 0; | |
12320 | break; | |
12321 | } | |
12322 | } | |
12323 | else | |
12324 | { | |
12325 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12326 | cop0 = opcode == OP_OP_COP0; | |
12327 | } | |
12328 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12329 | ok = reg_lookup (&s, types, ®no); | |
12330 | if (mips_opts.micromips) | |
12331 | INSERT_OPERAND (1, RS, *ip, regno); | |
12332 | else | |
12333 | INSERT_OPERAND (0, RD, *ip, regno); | |
12334 | if (ok) | |
12335 | { | |
12336 | lastregno = regno; | |
12337 | continue; | |
12338 | } | |
12339 | } | |
12340 | break; | |
707bfff6 | 12341 | |
df58fc94 RS |
12342 | case 'y': /* ALNV.PS source register. */ |
12343 | gas_assert (mips_opts.micromips); | |
12344 | goto do_reg; | |
12345 | case 'x': /* Ignore register name. */ | |
12346 | case 'U': /* Destination register (CLO/CLZ). */ | |
12347 | case 'g': /* Coprocessor destination register. */ | |
12348 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12349 | case 'b': /* Base register. */ |
12350 | case 'd': /* Destination register. */ | |
12351 | case 's': /* Source register. */ | |
12352 | case 't': /* Target register. */ | |
12353 | case 'r': /* Both target and source. */ | |
12354 | case 'v': /* Both dest and source. */ | |
12355 | case 'w': /* Both dest and target. */ | |
12356 | case 'E': /* Coprocessor target register. */ | |
12357 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12358 | case 'z': /* Must be zero register. */ |
df58fc94 | 12359 | do_reg: |
90ecf173 | 12360 | s_reset = s; |
707bfff6 TS |
12361 | if (*args == 'E' || *args == 'K') |
12362 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12363 | else | |
12364 | { | |
12365 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12366 | if (regno == AT && mips_opts.at) |
12367 | { | |
12368 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12369 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12370 | else |
f71d0d44 | 12371 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12372 | regno, mips_opts.at); |
12373 | } | |
707bfff6 TS |
12374 | } |
12375 | if (ok) | |
252b5132 | 12376 | { |
252b5132 RH |
12377 | c = *args; |
12378 | if (*s == ' ') | |
f9419b05 | 12379 | ++s; |
252b5132 RH |
12380 | if (args[1] != *s) |
12381 | { | |
12382 | if (c == 'r' || c == 'v' || c == 'w') | |
12383 | { | |
12384 | regno = lastregno; | |
12385 | s = s_reset; | |
f9419b05 | 12386 | ++args; |
252b5132 RH |
12387 | } |
12388 | } | |
12389 | /* 'z' only matches $0. */ | |
12390 | if (c == 'z' && regno != 0) | |
12391 | break; | |
12392 | ||
24864476 | 12393 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12394 | { |
12395 | if (regno == lastregno) | |
90ecf173 MR |
12396 | { |
12397 | insn_error | |
f71d0d44 | 12398 | = _("Source and destination must be different"); |
e7c604dd | 12399 | continue; |
90ecf173 | 12400 | } |
24864476 | 12401 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12402 | { |
12403 | insn_error | |
f71d0d44 | 12404 | = _("A destination register must be supplied"); |
e7c604dd | 12405 | continue; |
90ecf173 | 12406 | } |
e7c604dd | 12407 | } |
90ecf173 MR |
12408 | /* Now that we have assembled one operand, we use the args |
12409 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12410 | switch (c) |
12411 | { | |
12412 | case 'r': | |
12413 | case 's': | |
12414 | case 'v': | |
12415 | case 'b': | |
df58fc94 | 12416 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12417 | break; |
df58fc94 | 12418 | |
af7ee8bf | 12419 | case 'K': |
df58fc94 RS |
12420 | if (mips_opts.micromips) |
12421 | INSERT_OPERAND (1, RS, *ip, regno); | |
12422 | else | |
12423 | INSERT_OPERAND (0, RD, *ip, regno); | |
12424 | break; | |
12425 | ||
12426 | case 'd': | |
ef2e4d86 | 12427 | case 'g': |
df58fc94 | 12428 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12429 | break; |
df58fc94 | 12430 | |
4372b673 | 12431 | case 'U': |
df58fc94 RS |
12432 | gas_assert (!mips_opts.micromips); |
12433 | INSERT_OPERAND (0, RD, *ip, regno); | |
12434 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12435 | break; |
df58fc94 | 12436 | |
252b5132 RH |
12437 | case 'w': |
12438 | case 't': | |
12439 | case 'E': | |
df58fc94 RS |
12440 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12441 | break; | |
12442 | ||
12443 | case 'y': | |
12444 | gas_assert (mips_opts.micromips); | |
12445 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12446 | break; |
df58fc94 | 12447 | |
252b5132 RH |
12448 | case 'x': |
12449 | /* This case exists because on the r3000 trunc | |
12450 | expands into a macro which requires a gp | |
12451 | register. On the r6000 or r4000 it is | |
12452 | assembled into a single instruction which | |
12453 | ignores the register. Thus the insn version | |
12454 | is MIPS_ISA2 and uses 'x', and the macro | |
12455 | version is MIPS_ISA1 and uses 't'. */ | |
12456 | break; | |
df58fc94 | 12457 | |
252b5132 RH |
12458 | case 'z': |
12459 | /* This case is for the div instruction, which | |
12460 | acts differently if the destination argument | |
12461 | is $0. This only matches $0, and is checked | |
12462 | outside the switch. */ | |
12463 | break; | |
252b5132 RH |
12464 | } |
12465 | lastregno = regno; | |
12466 | continue; | |
12467 | } | |
252b5132 RH |
12468 | switch (*args++) |
12469 | { | |
12470 | case 'r': | |
12471 | case 'v': | |
df58fc94 | 12472 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12473 | continue; |
df58fc94 | 12474 | |
252b5132 | 12475 | case 'w': |
df58fc94 | 12476 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12477 | continue; |
12478 | } | |
12479 | break; | |
12480 | ||
deec1734 | 12481 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12482 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12483 | my_getExpression (&imm_expr, s); |
12484 | check_absolute_expr (ip, &imm_expr); | |
12485 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12486 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12487 | (long) imm_expr.X_add_number); |
df58fc94 | 12488 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12489 | imm_expr.X_op = O_absent; |
12490 | s = expr_end; | |
12491 | continue; | |
12492 | ||
12493 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12494 | if (s[0] != '$') | |
12495 | { | |
12496 | /* MDMX Immediate. */ | |
df58fc94 | 12497 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12498 | my_getExpression (&imm_expr, s); |
12499 | check_absolute_expr (ip, &imm_expr); | |
12500 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12501 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12502 | (long) imm_expr.X_add_number); | |
df58fc94 | 12503 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12504 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12505 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12506 | else | |
12507 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12508 | imm_expr.X_op = O_absent; |
12509 | s = expr_end; | |
12510 | continue; | |
12511 | } | |
12512 | /* Not MDMX Immediate. Fall through. */ | |
12513 | case 'X': /* MDMX destination register. */ | |
12514 | case 'Y': /* MDMX source register. */ | |
12515 | case 'Z': /* MDMX target register. */ | |
12516 | is_mdmx = 1; | |
df58fc94 RS |
12517 | case 'W': |
12518 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12519 | case 'D': /* Floating point destination register. */ |
12520 | case 'S': /* Floating point source register. */ | |
12521 | case 'T': /* Floating point target register. */ | |
12522 | case 'R': /* Floating point source register. */ | |
252b5132 | 12523 | case 'V': |
707bfff6 TS |
12524 | rtype = RTYPE_FPU; |
12525 | if (is_mdmx | |
846ef2d0 | 12526 | || ((mips_opts.ase & ASE_MDMX) |
707bfff6 TS |
12527 | && (ip->insn_mo->pinfo & FP_D) |
12528 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12529 | | INSN_COPROC_MEMORY_DELAY | |
12530 | | INSN_LOAD_COPROC_DELAY | |
12531 | | INSN_LOAD_MEMORY_DELAY | |
12532 | | INSN_STORE_MEMORY)))) | |
12533 | rtype |= RTYPE_VEC; | |
252b5132 | 12534 | s_reset = s; |
707bfff6 | 12535 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12536 | { |
252b5132 | 12537 | if ((regno & 1) != 0 |
ca4e0257 | 12538 | && HAVE_32BIT_FPRS |
90ecf173 | 12539 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12540 | as_warn (_("Float register should be even, was %d"), |
12541 | regno); | |
12542 | ||
12543 | c = *args; | |
12544 | if (*s == ' ') | |
f9419b05 | 12545 | ++s; |
252b5132 RH |
12546 | if (args[1] != *s) |
12547 | { | |
12548 | if (c == 'V' || c == 'W') | |
12549 | { | |
12550 | regno = lastregno; | |
12551 | s = s_reset; | |
f9419b05 | 12552 | ++args; |
252b5132 RH |
12553 | } |
12554 | } | |
12555 | switch (c) | |
12556 | { | |
12557 | case 'D': | |
deec1734 | 12558 | case 'X': |
df58fc94 | 12559 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12560 | break; |
df58fc94 | 12561 | |
252b5132 RH |
12562 | case 'V': |
12563 | case 'S': | |
deec1734 | 12564 | case 'Y': |
df58fc94 | 12565 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12566 | break; |
df58fc94 | 12567 | |
deec1734 CD |
12568 | case 'Q': |
12569 | /* This is like 'Z', but also needs to fix the MDMX | |
12570 | vector/scalar select bits. Note that the | |
12571 | scalar immediate case is handled above. */ | |
12572 | if (*s == '[') | |
12573 | { | |
12574 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12575 | int max_el = (is_qh ? 3 : 7); | |
12576 | s++; | |
12577 | my_getExpression(&imm_expr, s); | |
12578 | check_absolute_expr (ip, &imm_expr); | |
12579 | s = expr_end; | |
12580 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12581 | as_bad (_("Bad element selector %ld"), |
12582 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12583 | imm_expr.X_add_number &= max_el; |
12584 | ip->insn_opcode |= (imm_expr.X_add_number | |
12585 | << (OP_SH_VSEL + | |
12586 | (is_qh ? 2 : 1))); | |
01a3f561 | 12587 | imm_expr.X_op = O_absent; |
deec1734 | 12588 | if (*s != ']') |
20203fb9 | 12589 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12590 | else |
12591 | s++; | |
12592 | } | |
12593 | else | |
12594 | { | |
12595 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12596 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12597 | << OP_SH_VSEL); | |
12598 | else | |
12599 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12600 | OP_SH_VSEL); | |
12601 | } | |
90ecf173 | 12602 | /* Fall through. */ |
252b5132 RH |
12603 | case 'W': |
12604 | case 'T': | |
deec1734 | 12605 | case 'Z': |
df58fc94 | 12606 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12607 | break; |
df58fc94 | 12608 | |
252b5132 | 12609 | case 'R': |
df58fc94 | 12610 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12611 | break; |
12612 | } | |
12613 | lastregno = regno; | |
12614 | continue; | |
12615 | } | |
12616 | ||
252b5132 RH |
12617 | switch (*args++) |
12618 | { | |
12619 | case 'V': | |
df58fc94 | 12620 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12621 | continue; |
df58fc94 | 12622 | |
252b5132 | 12623 | case 'W': |
df58fc94 | 12624 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12625 | continue; |
12626 | } | |
12627 | break; | |
12628 | ||
12629 | case 'I': | |
12630 | my_getExpression (&imm_expr, s); | |
12631 | if (imm_expr.X_op != O_big | |
12632 | && imm_expr.X_op != O_constant) | |
12633 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12634 | if (HAVE_32BIT_GPRS) |
12635 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12636 | s = expr_end; |
12637 | continue; | |
12638 | ||
12639 | case 'A': | |
12640 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12641 | normalize_address_expr (&offset_expr); |
f6688943 | 12642 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12643 | s = expr_end; |
12644 | continue; | |
12645 | ||
12646 | case 'F': | |
12647 | case 'L': | |
12648 | case 'f': | |
12649 | case 'l': | |
12650 | { | |
12651 | int f64; | |
ca4e0257 | 12652 | int using_gprs; |
252b5132 RH |
12653 | char *save_in; |
12654 | char *err; | |
12655 | unsigned char temp[8]; | |
12656 | int len; | |
12657 | unsigned int length; | |
12658 | segT seg; | |
12659 | subsegT subseg; | |
12660 | char *p; | |
12661 | ||
12662 | /* These only appear as the last operand in an | |
12663 | instruction, and every instruction that accepts | |
12664 | them in any variant accepts them in all variants. | |
12665 | This means we don't have to worry about backing out | |
12666 | any changes if the instruction does not match. | |
12667 | ||
12668 | The difference between them is the size of the | |
12669 | floating point constant and where it goes. For 'F' | |
12670 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12671 | is 32 bits. Where the constant is placed is based | |
12672 | on how the MIPS assembler does things: | |
12673 | F -- .rdata | |
12674 | L -- .lit8 | |
12675 | f -- immediate value | |
12676 | l -- .lit4 | |
12677 | ||
12678 | The .lit4 and .lit8 sections are only used if | |
12679 | permitted by the -G argument. | |
12680 | ||
ca4e0257 RS |
12681 | The code below needs to know whether the target register |
12682 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12683 | 'F' are used with GPR-based instructions and 'l' and | |
12684 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12685 | |
12686 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12687 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12688 | |
12689 | save_in = input_line_pointer; | |
12690 | input_line_pointer = s; | |
12691 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12692 | length = len; | |
12693 | s = input_line_pointer; | |
12694 | input_line_pointer = save_in; | |
12695 | if (err != NULL && *err != '\0') | |
12696 | { | |
12697 | as_bad (_("Bad floating point constant: %s"), err); | |
12698 | memset (temp, '\0', sizeof temp); | |
12699 | length = f64 ? 8 : 4; | |
12700 | } | |
12701 | ||
9c2799c2 | 12702 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12703 | |
12704 | if (*args == 'f' | |
12705 | || (*args == 'l' | |
3e722fb5 | 12706 | && (g_switch_value < 4 |
252b5132 RH |
12707 | || (temp[0] == 0 && temp[1] == 0) |
12708 | || (temp[2] == 0 && temp[3] == 0)))) | |
12709 | { | |
12710 | imm_expr.X_op = O_constant; | |
90ecf173 | 12711 | if (!target_big_endian) |
252b5132 RH |
12712 | imm_expr.X_add_number = bfd_getl32 (temp); |
12713 | else | |
12714 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12715 | } | |
12716 | else if (length > 4 | |
90ecf173 | 12717 | && !mips_disable_float_construction |
ca4e0257 RS |
12718 | /* Constants can only be constructed in GPRs and |
12719 | copied to FPRs if the GPRs are at least as wide | |
12720 | as the FPRs. Force the constant into memory if | |
12721 | we are using 64-bit FPRs but the GPRs are only | |
12722 | 32 bits wide. */ | |
12723 | && (using_gprs | |
90ecf173 | 12724 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12725 | && ((temp[0] == 0 && temp[1] == 0) |
12726 | || (temp[2] == 0 && temp[3] == 0)) | |
12727 | && ((temp[4] == 0 && temp[5] == 0) | |
12728 | || (temp[6] == 0 && temp[7] == 0))) | |
12729 | { | |
ca4e0257 | 12730 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12731 | instructions. If using 32-bit registers, set |
12732 | imm_expr to the high order 32 bits and offset_expr to | |
12733 | the low order 32 bits. Otherwise, set imm_expr to | |
12734 | the entire 64 bit constant. */ | |
ca4e0257 | 12735 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12736 | { |
12737 | imm_expr.X_op = O_constant; | |
12738 | offset_expr.X_op = O_constant; | |
90ecf173 | 12739 | if (!target_big_endian) |
252b5132 RH |
12740 | { |
12741 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12742 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12743 | } | |
12744 | else | |
12745 | { | |
12746 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12747 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12748 | } | |
12749 | if (offset_expr.X_add_number == 0) | |
12750 | offset_expr.X_op = O_absent; | |
12751 | } | |
12752 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12753 | { | |
12754 | imm_expr.X_op = O_constant; | |
90ecf173 | 12755 | if (!target_big_endian) |
252b5132 RH |
12756 | imm_expr.X_add_number = bfd_getl64 (temp); |
12757 | else | |
12758 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12759 | } | |
12760 | else | |
12761 | { | |
12762 | imm_expr.X_op = O_big; | |
12763 | imm_expr.X_add_number = 4; | |
90ecf173 | 12764 | if (!target_big_endian) |
252b5132 RH |
12765 | { |
12766 | generic_bignum[0] = bfd_getl16 (temp); | |
12767 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12768 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12769 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12770 | } | |
12771 | else | |
12772 | { | |
12773 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12774 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12775 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12776 | generic_bignum[3] = bfd_getb16 (temp); | |
12777 | } | |
12778 | } | |
12779 | } | |
12780 | else | |
12781 | { | |
12782 | const char *newname; | |
12783 | segT new_seg; | |
12784 | ||
12785 | /* Switch to the right section. */ | |
12786 | seg = now_seg; | |
12787 | subseg = now_subseg; | |
12788 | switch (*args) | |
12789 | { | |
12790 | default: /* unused default case avoids warnings. */ | |
12791 | case 'L': | |
12792 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12793 | if (g_switch_value >= 8) |
252b5132 RH |
12794 | newname = ".lit8"; |
12795 | break; | |
12796 | case 'F': | |
3e722fb5 | 12797 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12798 | break; |
12799 | case 'l': | |
9c2799c2 | 12800 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12801 | newname = ".lit4"; |
12802 | break; | |
12803 | } | |
12804 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12805 | if (IS_ELF) |
252b5132 RH |
12806 | bfd_set_section_flags (stdoutput, new_seg, |
12807 | (SEC_ALLOC | |
12808 | | SEC_LOAD | |
12809 | | SEC_READONLY | |
12810 | | SEC_DATA)); | |
12811 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12812 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12813 | record_alignment (new_seg, 4); |
12814 | else | |
12815 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12816 | if (seg == now_seg) | |
12817 | as_bad (_("Can't use floating point insn in this section")); | |
12818 | ||
df58fc94 RS |
12819 | /* Set the argument to the current address in the |
12820 | section. */ | |
12821 | offset_expr.X_op = O_symbol; | |
12822 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12823 | offset_expr.X_add_number = 0; | |
12824 | ||
12825 | /* Put the floating point number into the section. */ | |
12826 | p = frag_more ((int) length); | |
12827 | memcpy (p, temp, length); | |
12828 | ||
12829 | /* Switch back to the original section. */ | |
12830 | subseg_set (seg, subseg); | |
12831 | } | |
12832 | } | |
12833 | continue; | |
12834 | ||
12835 | case 'i': /* 16-bit unsigned immediate. */ | |
12836 | case 'j': /* 16-bit signed immediate. */ | |
12837 | *imm_reloc = BFD_RELOC_LO16; | |
12838 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12839 | { | |
12840 | int more; | |
12841 | offsetT minval, maxval; | |
12842 | ||
12843 | more = (insn + 1 < past | |
12844 | && strcmp (insn->name, insn[1].name) == 0); | |
12845 | ||
12846 | /* If the expression was written as an unsigned number, | |
12847 | only treat it as signed if there are no more | |
12848 | alternatives. */ | |
12849 | if (more | |
12850 | && *args == 'j' | |
12851 | && sizeof (imm_expr.X_add_number) <= 4 | |
12852 | && imm_expr.X_op == O_constant | |
12853 | && imm_expr.X_add_number < 0 | |
12854 | && imm_expr.X_unsigned | |
12855 | && HAVE_64BIT_GPRS) | |
12856 | break; | |
12857 | ||
12858 | /* For compatibility with older assemblers, we accept | |
12859 | 0x8000-0xffff as signed 16-bit numbers when only | |
12860 | signed numbers are allowed. */ | |
12861 | if (*args == 'i') | |
12862 | minval = 0, maxval = 0xffff; | |
12863 | else if (more) | |
12864 | minval = -0x8000, maxval = 0x7fff; | |
12865 | else | |
12866 | minval = -0x8000, maxval = 0xffff; | |
12867 | ||
12868 | if (imm_expr.X_op != O_constant | |
12869 | || imm_expr.X_add_number < minval | |
12870 | || imm_expr.X_add_number > maxval) | |
12871 | { | |
12872 | if (more) | |
12873 | break; | |
12874 | if (imm_expr.X_op == O_constant | |
12875 | || imm_expr.X_op == O_big) | |
12876 | as_bad (_("Expression out of range")); | |
12877 | } | |
12878 | } | |
12879 | s = expr_end; | |
12880 | continue; | |
12881 | ||
12882 | case 'o': /* 16-bit offset. */ | |
12883 | offset_reloc[0] = BFD_RELOC_LO16; | |
12884 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12885 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12886 | ||
12887 | /* Check whether there is only a single bracketed expression | |
12888 | left. If so, it must be the base register and the | |
12889 | constant must be zero. */ | |
12890 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12891 | { | |
12892 | offset_expr.X_op = O_constant; | |
12893 | offset_expr.X_add_number = 0; | |
12894 | continue; | |
12895 | } | |
12896 | ||
12897 | /* If this value won't fit into a 16 bit offset, then go | |
12898 | find a macro that will generate the 32 bit offset | |
12899 | code pattern. */ | |
12900 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12901 | && (offset_expr.X_op != O_constant | |
12902 | || offset_expr.X_add_number >= 0x8000 | |
12903 | || offset_expr.X_add_number < -0x8000)) | |
12904 | break; | |
12905 | ||
12906 | s = expr_end; | |
12907 | continue; | |
12908 | ||
12909 | case 'p': /* PC-relative offset. */ | |
12910 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12911 | my_getExpression (&offset_expr, s); | |
12912 | s = expr_end; | |
12913 | continue; | |
12914 | ||
12915 | case 'u': /* Upper 16 bits. */ | |
5821951c | 12916 | *imm_reloc = BFD_RELOC_LO16; |
df58fc94 RS |
12917 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
12918 | && imm_expr.X_op == O_constant | |
12919 | && (imm_expr.X_add_number < 0 | |
12920 | || imm_expr.X_add_number >= 0x10000)) | |
12921 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12922 | (unsigned long) imm_expr.X_add_number); | |
12923 | s = expr_end; | |
12924 | continue; | |
12925 | ||
12926 | case 'a': /* 26-bit address. */ | |
12927 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12928 | my_getExpression (&offset_expr, s); | |
12929 | s = expr_end; | |
12930 | continue; | |
12931 | ||
12932 | case 'N': /* 3-bit branch condition code. */ | |
12933 | case 'M': /* 3-bit compare condition code. */ | |
12934 | rtype = RTYPE_CCC; | |
12935 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12936 | rtype |= RTYPE_FCC; | |
12937 | if (!reg_lookup (&s, rtype, ®no)) | |
12938 | break; | |
12939 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12940 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12941 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12942 | && (regno & 1) != 0) | |
12943 | as_warn (_("Condition code register should be even for %s, " | |
12944 | "was %d"), | |
12945 | str, regno); | |
12946 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12947 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12948 | && (regno & 3) != 0) | |
12949 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12950 | "was %d"), | |
12951 | str, regno); | |
12952 | if (*args == 'N') | |
12953 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12954 | else | |
12955 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12956 | continue; | |
12957 | ||
12958 | case 'H': | |
12959 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12960 | s += 2; | |
12961 | if (ISDIGIT (*s)) | |
12962 | { | |
12963 | c = 0; | |
12964 | do | |
12965 | { | |
12966 | c *= 10; | |
12967 | c += *s - '0'; | |
12968 | ++s; | |
12969 | } | |
12970 | while (ISDIGIT (*s)); | |
12971 | } | |
12972 | else | |
12973 | c = 8; /* Invalid sel value. */ | |
12974 | ||
12975 | if (c > 7) | |
12976 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12977 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12978 | continue; | |
12979 | ||
12980 | case 'e': | |
12981 | gas_assert (!mips_opts.micromips); | |
12982 | /* Must be at least one digit. */ | |
12983 | my_getExpression (&imm_expr, s); | |
12984 | check_absolute_expr (ip, &imm_expr); | |
12985 | ||
12986 | if ((unsigned long) imm_expr.X_add_number | |
12987 | > (unsigned long) OP_MASK_VECBYTE) | |
12988 | { | |
12989 | as_bad (_("bad byte vector index (%ld)"), | |
12990 | (long) imm_expr.X_add_number); | |
12991 | imm_expr.X_add_number = 0; | |
12992 | } | |
12993 | ||
12994 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12995 | imm_expr.X_op = O_absent; | |
12996 | s = expr_end; | |
12997 | continue; | |
12998 | ||
12999 | case '%': | |
13000 | gas_assert (!mips_opts.micromips); | |
13001 | my_getExpression (&imm_expr, s); | |
13002 | check_absolute_expr (ip, &imm_expr); | |
13003 | ||
13004 | if ((unsigned long) imm_expr.X_add_number | |
13005 | > (unsigned long) OP_MASK_VECALIGN) | |
13006 | { | |
13007 | as_bad (_("bad byte vector index (%ld)"), | |
13008 | (long) imm_expr.X_add_number); | |
13009 | imm_expr.X_add_number = 0; | |
13010 | } | |
13011 | ||
13012 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
13013 | imm_expr.X_op = O_absent; | |
13014 | s = expr_end; | |
13015 | continue; | |
13016 | ||
13017 | case 'm': /* Opcode extension character. */ | |
13018 | gas_assert (mips_opts.micromips); | |
13019 | c = *++args; | |
13020 | switch (c) | |
13021 | { | |
13022 | case 'r': | |
13023 | if (strncmp (s, "$pc", 3) == 0) | |
13024 | { | |
13025 | s += 3; | |
13026 | continue; | |
13027 | } | |
13028 | break; | |
13029 | ||
13030 | case 'a': | |
13031 | case 'b': | |
13032 | case 'c': | |
13033 | case 'd': | |
13034 | case 'e': | |
13035 | case 'f': | |
13036 | case 'g': | |
13037 | case 'h': | |
13038 | case 'i': | |
13039 | case 'j': | |
13040 | case 'l': | |
13041 | case 'm': | |
13042 | case 'n': | |
13043 | case 'p': | |
13044 | case 'q': | |
13045 | case 's': | |
13046 | case 't': | |
13047 | case 'x': | |
13048 | case 'y': | |
13049 | case 'z': | |
13050 | s_reset = s; | |
13051 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
13052 | if (regno == AT && mips_opts.at) | |
13053 | { | |
13054 | if (mips_opts.at == ATREG) | |
13055 | as_warn (_("Used $at without \".set noat\"")); | |
13056 | else | |
13057 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13058 | regno, mips_opts.at); | |
13059 | } | |
13060 | if (!ok) | |
13061 | { | |
13062 | if (c == 'c') | |
13063 | { | |
13064 | gas_assert (args[1] == ','); | |
13065 | regno = lastregno; | |
13066 | ++args; | |
13067 | } | |
13068 | else if (c == 't') | |
13069 | { | |
13070 | gas_assert (args[1] == ','); | |
13071 | ++args; | |
13072 | continue; /* Nothing to do. */ | |
13073 | } | |
13074 | else | |
13075 | break; | |
13076 | } | |
13077 | ||
13078 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
13079 | { | |
13080 | if (regno == lastregno) | |
13081 | { | |
13082 | insn_error | |
13083 | = _("Source and destination must be different"); | |
13084 | continue; | |
13085 | } | |
13086 | if (regno == 31 && lastregno == 0xffffffff) | |
13087 | { | |
13088 | insn_error | |
13089 | = _("A destination register must be supplied"); | |
13090 | continue; | |
13091 | } | |
13092 | } | |
13093 | ||
13094 | if (*s == ' ') | |
13095 | ++s; | |
13096 | if (args[1] != *s) | |
13097 | { | |
13098 | if (c == 'e') | |
13099 | { | |
13100 | gas_assert (args[1] == ','); | |
13101 | regno = lastregno; | |
13102 | s = s_reset; | |
13103 | ++args; | |
13104 | } | |
13105 | else if (c == 't') | |
13106 | { | |
13107 | gas_assert (args[1] == ','); | |
13108 | s = s_reset; | |
13109 | ++args; | |
13110 | continue; /* Nothing to do. */ | |
13111 | } | |
13112 | } | |
13113 | ||
13114 | /* Make sure regno is the same as lastregno. */ | |
13115 | if (c == 't' && regno != lastregno) | |
13116 | break; | |
13117 | ||
13118 | /* Make sure regno is the same as destregno. */ | |
13119 | if (c == 'x' && regno != destregno) | |
13120 | break; | |
13121 | ||
13122 | /* We need to save regno, before regno maps to the | |
13123 | microMIPS register encoding. */ | |
13124 | lastregno = regno; | |
13125 | ||
13126 | if (c == 'f') | |
13127 | destregno = regno; | |
13128 | ||
13129 | switch (c) | |
13130 | { | |
13131 | case 'a': | |
13132 | if (regno != GP) | |
13133 | regno = ILLEGAL_REG; | |
13134 | break; | |
13135 | ||
13136 | case 'b': | |
13137 | regno = mips32_to_micromips_reg_b_map[regno]; | |
13138 | break; | |
13139 | ||
13140 | case 'c': | |
13141 | regno = mips32_to_micromips_reg_c_map[regno]; | |
13142 | break; | |
13143 | ||
13144 | case 'd': | |
13145 | regno = mips32_to_micromips_reg_d_map[regno]; | |
13146 | break; | |
13147 | ||
13148 | case 'e': | |
13149 | regno = mips32_to_micromips_reg_e_map[regno]; | |
13150 | break; | |
13151 | ||
13152 | case 'f': | |
13153 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13154 | break; | |
13155 | ||
13156 | case 'g': | |
13157 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13158 | break; | |
13159 | ||
13160 | case 'h': | |
13161 | regno = mips32_to_micromips_reg_h_map[regno]; | |
13162 | break; | |
13163 | ||
13164 | case 'i': | |
13165 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
13166 | { | |
13167 | case 4: | |
13168 | if (regno == 21) | |
13169 | regno = 3; | |
13170 | else if (regno == 22) | |
13171 | regno = 4; | |
13172 | else if (regno == 5) | |
13173 | regno = 5; | |
13174 | else if (regno == 6) | |
13175 | regno = 6; | |
13176 | else if (regno == 7) | |
13177 | regno = 7; | |
13178 | else | |
13179 | regno = ILLEGAL_REG; | |
13180 | break; | |
13181 | ||
13182 | case 5: | |
13183 | if (regno == 6) | |
13184 | regno = 0; | |
13185 | else if (regno == 7) | |
13186 | regno = 1; | |
13187 | else | |
13188 | regno = ILLEGAL_REG; | |
13189 | break; | |
13190 | ||
13191 | case 6: | |
13192 | if (regno == 7) | |
13193 | regno = 2; | |
13194 | else | |
13195 | regno = ILLEGAL_REG; | |
13196 | break; | |
13197 | ||
13198 | default: | |
13199 | regno = ILLEGAL_REG; | |
13200 | break; | |
13201 | } | |
13202 | break; | |
13203 | ||
13204 | case 'l': | |
13205 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13206 | break; | |
13207 | ||
13208 | case 'm': | |
13209 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13210 | break; | |
13211 | ||
13212 | case 'n': | |
13213 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13214 | break; | |
13215 | ||
13216 | case 'q': | |
13217 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13218 | break; | |
13219 | ||
13220 | case 's': | |
13221 | if (regno != SP) | |
13222 | regno = ILLEGAL_REG; | |
13223 | break; | |
13224 | ||
13225 | case 'y': | |
13226 | if (regno != 31) | |
13227 | regno = ILLEGAL_REG; | |
13228 | break; | |
13229 | ||
13230 | case 'z': | |
13231 | if (regno != ZERO) | |
13232 | regno = ILLEGAL_REG; | |
13233 | break; | |
13234 | ||
13235 | case 'j': /* Do nothing. */ | |
13236 | case 'p': | |
13237 | case 't': | |
13238 | case 'x': | |
13239 | break; | |
13240 | ||
13241 | default: | |
b37df7c4 | 13242 | abort (); |
df58fc94 RS |
13243 | } |
13244 | ||
13245 | if (regno == ILLEGAL_REG) | |
13246 | break; | |
13247 | ||
13248 | switch (c) | |
13249 | { | |
13250 | case 'b': | |
13251 | INSERT_OPERAND (1, MB, *ip, regno); | |
13252 | break; | |
13253 | ||
13254 | case 'c': | |
13255 | INSERT_OPERAND (1, MC, *ip, regno); | |
13256 | break; | |
13257 | ||
13258 | case 'd': | |
13259 | INSERT_OPERAND (1, MD, *ip, regno); | |
13260 | break; | |
13261 | ||
13262 | case 'e': | |
13263 | INSERT_OPERAND (1, ME, *ip, regno); | |
13264 | break; | |
13265 | ||
13266 | case 'f': | |
13267 | INSERT_OPERAND (1, MF, *ip, regno); | |
13268 | break; | |
13269 | ||
13270 | case 'g': | |
13271 | INSERT_OPERAND (1, MG, *ip, regno); | |
13272 | break; | |
13273 | ||
13274 | case 'h': | |
13275 | INSERT_OPERAND (1, MH, *ip, regno); | |
13276 | break; | |
13277 | ||
13278 | case 'i': | |
13279 | INSERT_OPERAND (1, MI, *ip, regno); | |
13280 | break; | |
13281 | ||
13282 | case 'j': | |
13283 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13284 | break; | |
13285 | ||
13286 | case 'l': | |
13287 | INSERT_OPERAND (1, ML, *ip, regno); | |
13288 | break; | |
13289 | ||
13290 | case 'm': | |
13291 | INSERT_OPERAND (1, MM, *ip, regno); | |
13292 | break; | |
13293 | ||
13294 | case 'n': | |
13295 | INSERT_OPERAND (1, MN, *ip, regno); | |
13296 | break; | |
13297 | ||
13298 | case 'p': | |
13299 | INSERT_OPERAND (1, MP, *ip, regno); | |
13300 | break; | |
13301 | ||
13302 | case 'q': | |
13303 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13304 | break; | |
13305 | ||
13306 | case 'a': /* Do nothing. */ | |
13307 | case 's': /* Do nothing. */ | |
13308 | case 't': /* Do nothing. */ | |
13309 | case 'x': /* Do nothing. */ | |
13310 | case 'y': /* Do nothing. */ | |
13311 | case 'z': /* Do nothing. */ | |
13312 | break; | |
13313 | ||
13314 | default: | |
b37df7c4 | 13315 | abort (); |
df58fc94 RS |
13316 | } |
13317 | continue; | |
13318 | ||
13319 | case 'A': | |
13320 | { | |
13321 | bfd_reloc_code_real_type r[3]; | |
13322 | expressionS ep; | |
13323 | int imm; | |
13324 | ||
13325 | /* Check whether there is only a single bracketed | |
13326 | expression left. If so, it must be the base register | |
13327 | and the constant must be zero. */ | |
13328 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13329 | { | |
13330 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13331 | continue; | |
13332 | } | |
13333 | ||
13334 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13335 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13336 | break; | |
13337 | ||
13338 | imm = ep.X_add_number >> 2; | |
13339 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13340 | } | |
13341 | s = expr_end; | |
13342 | continue; | |
13343 | ||
13344 | case 'B': | |
13345 | { | |
13346 | bfd_reloc_code_real_type r[3]; | |
13347 | expressionS ep; | |
13348 | int imm; | |
13349 | ||
13350 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13351 | || ep.X_op != O_constant) | |
13352 | break; | |
13353 | ||
13354 | for (imm = 0; imm < 8; imm++) | |
13355 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13356 | break; | |
13357 | if (imm >= 8) | |
13358 | break; | |
13359 | ||
13360 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13361 | } | |
13362 | s = expr_end; | |
13363 | continue; | |
13364 | ||
13365 | case 'C': | |
13366 | { | |
13367 | bfd_reloc_code_real_type r[3]; | |
13368 | expressionS ep; | |
13369 | int imm; | |
13370 | ||
13371 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13372 | || ep.X_op != O_constant) | |
13373 | break; | |
13374 | ||
13375 | for (imm = 0; imm < 16; imm++) | |
13376 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13377 | break; | |
13378 | if (imm >= 16) | |
13379 | break; | |
13380 | ||
13381 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13382 | } | |
13383 | s = expr_end; | |
13384 | continue; | |
13385 | ||
13386 | case 'D': /* pc relative offset */ | |
13387 | case 'E': /* pc relative offset */ | |
13388 | my_getExpression (&offset_expr, s); | |
13389 | if (offset_expr.X_op == O_register) | |
13390 | break; | |
13391 | ||
40209cad MR |
13392 | if (!forced_insn_length) |
13393 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13394 | else if (c == 'D') | |
13395 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13396 | else | |
13397 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13398 | s = expr_end; |
13399 | continue; | |
13400 | ||
13401 | case 'F': | |
13402 | { | |
13403 | bfd_reloc_code_real_type r[3]; | |
13404 | expressionS ep; | |
13405 | int imm; | |
13406 | ||
13407 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13408 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13409 | break; | |
13410 | ||
13411 | imm = ep.X_add_number; | |
13412 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13413 | } | |
13414 | s = expr_end; | |
13415 | continue; | |
13416 | ||
13417 | case 'G': | |
13418 | { | |
13419 | bfd_reloc_code_real_type r[3]; | |
13420 | expressionS ep; | |
13421 | int imm; | |
13422 | ||
13423 | /* Check whether there is only a single bracketed | |
13424 | expression left. If so, it must be the base register | |
13425 | and the constant must be zero. */ | |
13426 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13427 | { | |
13428 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13429 | continue; | |
13430 | } | |
13431 | ||
13432 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13433 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13434 | break; | |
13435 | ||
13436 | imm = ep.X_add_number & 15; | |
13437 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13438 | } | |
13439 | s = expr_end; | |
13440 | continue; | |
13441 | ||
13442 | case 'H': | |
13443 | { | |
13444 | bfd_reloc_code_real_type r[3]; | |
13445 | expressionS ep; | |
13446 | int imm; | |
13447 | ||
13448 | /* Check whether there is only a single bracketed | |
13449 | expression left. If so, it must be the base register | |
13450 | and the constant must be zero. */ | |
13451 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13452 | { | |
13453 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13454 | continue; | |
13455 | } | |
13456 | ||
13457 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13458 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13459 | break; | |
13460 | ||
13461 | imm = ep.X_add_number >> 1; | |
13462 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13463 | } | |
13464 | s = expr_end; | |
13465 | continue; | |
13466 | ||
13467 | case 'I': | |
13468 | { | |
13469 | bfd_reloc_code_real_type r[3]; | |
13470 | expressionS ep; | |
13471 | int imm; | |
13472 | ||
13473 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13474 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13475 | break; | |
13476 | ||
13477 | imm = ep.X_add_number & 127; | |
13478 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13479 | } | |
13480 | s = expr_end; | |
13481 | continue; | |
13482 | ||
13483 | case 'J': | |
13484 | { | |
13485 | bfd_reloc_code_real_type r[3]; | |
13486 | expressionS ep; | |
13487 | int imm; | |
13488 | ||
13489 | /* Check whether there is only a single bracketed | |
13490 | expression left. If so, it must be the base register | |
13491 | and the constant must be zero. */ | |
13492 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13493 | { | |
13494 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13495 | continue; | |
13496 | } | |
13497 | ||
13498 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13499 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13500 | break; | |
13501 | ||
13502 | imm = ep.X_add_number >> 2; | |
13503 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13504 | } | |
13505 | s = expr_end; | |
13506 | continue; | |
13507 | ||
13508 | case 'L': | |
13509 | { | |
13510 | bfd_reloc_code_real_type r[3]; | |
13511 | expressionS ep; | |
13512 | int imm; | |
13513 | ||
13514 | /* Check whether there is only a single bracketed | |
13515 | expression left. If so, it must be the base register | |
13516 | and the constant must be zero. */ | |
13517 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13518 | { | |
13519 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13520 | continue; | |
13521 | } | |
13522 | ||
13523 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13524 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13525 | break; | |
13526 | ||
13527 | imm = ep.X_add_number; | |
13528 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13529 | } | |
13530 | s = expr_end; | |
13531 | continue; | |
13532 | ||
13533 | case 'M': | |
13534 | { | |
13535 | bfd_reloc_code_real_type r[3]; | |
13536 | expressionS ep; | |
13537 | int imm; | |
13538 | ||
13539 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13540 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13541 | break; | |
13542 | ||
13543 | imm = ep.X_add_number & 7; | |
13544 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13545 | } | |
13546 | s = expr_end; | |
13547 | continue; | |
13548 | ||
13549 | case 'N': /* Register list for lwm and swm. */ | |
13550 | { | |
13551 | /* A comma-separated list of registers and/or | |
13552 | dash-separated contiguous ranges including | |
13553 | both ra and a set of one or more registers | |
13554 | starting at s0 up to s3 which have to be | |
13555 | consecutive, e.g.: | |
13556 | ||
13557 | s0, ra | |
13558 | s0, s1, ra, s2, s3 | |
13559 | s0-s2, ra | |
13560 | ||
13561 | and any permutations of these. */ | |
13562 | unsigned int reglist; | |
13563 | int imm; | |
13564 | ||
13565 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13566 | break; | |
13567 | ||
13568 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13569 | break; | |
13570 | ||
13571 | reglist = (reglist >> 17) & 7; | |
13572 | reglist += 1; | |
13573 | if ((reglist & -reglist) != reglist) | |
13574 | break; | |
252b5132 | 13575 | |
df58fc94 RS |
13576 | imm = ffs (reglist) - 1; |
13577 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13578 | } | |
13579 | continue; | |
252b5132 | 13580 | |
df58fc94 RS |
13581 | case 'O': /* sdbbp 4-bit code. */ |
13582 | { | |
13583 | bfd_reloc_code_real_type r[3]; | |
13584 | expressionS ep; | |
13585 | int imm; | |
13586 | ||
13587 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13588 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13589 | break; | |
13590 | ||
13591 | imm = ep.X_add_number; | |
13592 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13593 | } |
df58fc94 RS |
13594 | s = expr_end; |
13595 | continue; | |
252b5132 | 13596 | |
df58fc94 RS |
13597 | case 'P': |
13598 | { | |
13599 | bfd_reloc_code_real_type r[3]; | |
13600 | expressionS ep; | |
13601 | int imm; | |
5e0116d5 | 13602 | |
df58fc94 RS |
13603 | if (my_getSmallExpression (&ep, r, s) > 0 |
13604 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13605 | break; | |
5e0116d5 | 13606 | |
df58fc94 RS |
13607 | imm = ep.X_add_number >> 2; |
13608 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13609 | } | |
13610 | s = expr_end; | |
13611 | continue; | |
5e0116d5 | 13612 | |
df58fc94 RS |
13613 | case 'Q': |
13614 | { | |
13615 | bfd_reloc_code_real_type r[3]; | |
13616 | expressionS ep; | |
13617 | int imm; | |
5e0116d5 | 13618 | |
df58fc94 RS |
13619 | if (my_getSmallExpression (&ep, r, s) > 0 |
13620 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13621 | break; | |
252b5132 | 13622 | |
df58fc94 RS |
13623 | imm = ep.X_add_number >> 2; |
13624 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13625 | } | |
13626 | s = expr_end; | |
13627 | continue; | |
4614d845 | 13628 | |
df58fc94 RS |
13629 | case 'U': |
13630 | { | |
13631 | bfd_reloc_code_real_type r[3]; | |
13632 | expressionS ep; | |
13633 | int imm; | |
13634 | ||
13635 | /* Check whether there is only a single bracketed | |
13636 | expression left. If so, it must be the base register | |
13637 | and the constant must be zero. */ | |
13638 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13639 | { | |
13640 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13641 | continue; | |
13642 | } | |
13643 | ||
13644 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13645 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13646 | break; | |
13647 | ||
13648 | imm = ep.X_add_number >> 2; | |
13649 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13650 | } | |
13651 | s = expr_end; | |
5e0116d5 | 13652 | continue; |
252b5132 | 13653 | |
df58fc94 RS |
13654 | case 'W': |
13655 | { | |
13656 | bfd_reloc_code_real_type r[3]; | |
13657 | expressionS ep; | |
13658 | int imm; | |
252b5132 | 13659 | |
df58fc94 RS |
13660 | if (my_getSmallExpression (&ep, r, s) > 0 |
13661 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13662 | break; | |
252b5132 | 13663 | |
df58fc94 RS |
13664 | imm = ep.X_add_number >> 2; |
13665 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13666 | } | |
13667 | s = expr_end; | |
13668 | continue; | |
252b5132 | 13669 | |
df58fc94 RS |
13670 | case 'X': |
13671 | { | |
13672 | bfd_reloc_code_real_type r[3]; | |
13673 | expressionS ep; | |
13674 | int imm; | |
252b5132 | 13675 | |
df58fc94 RS |
13676 | if (my_getSmallExpression (&ep, r, s) > 0 |
13677 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13678 | break; | |
252b5132 | 13679 | |
df58fc94 RS |
13680 | imm = ep.X_add_number; |
13681 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13682 | } | |
13683 | s = expr_end; | |
13684 | continue; | |
252b5132 | 13685 | |
df58fc94 RS |
13686 | case 'Y': |
13687 | { | |
13688 | bfd_reloc_code_real_type r[3]; | |
13689 | expressionS ep; | |
13690 | int imm; | |
156c2f8b | 13691 | |
df58fc94 RS |
13692 | if (my_getSmallExpression (&ep, r, s) > 0 |
13693 | || expr_const_in_range (&ep, -2, 2, 2) | |
13694 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13695 | break; | |
156c2f8b | 13696 | |
df58fc94 RS |
13697 | imm = ep.X_add_number >> 2; |
13698 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13699 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13700 | } | |
13701 | s = expr_end; | |
13702 | continue; | |
60b63b72 | 13703 | |
df58fc94 RS |
13704 | case 'Z': |
13705 | { | |
13706 | bfd_reloc_code_real_type r[3]; | |
13707 | expressionS ep; | |
13708 | ||
13709 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13710 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13711 | break; | |
13712 | } | |
13713 | s = expr_end; | |
13714 | continue; | |
13715 | ||
13716 | default: | |
13717 | as_bad (_("Internal error: bad microMIPS opcode " | |
13718 | "(unknown extension operand type `m%c'): %s %s"), | |
13719 | *args, insn->name, insn->args); | |
13720 | /* Further processing is fruitless. */ | |
13721 | return; | |
60b63b72 | 13722 | } |
df58fc94 | 13723 | break; |
60b63b72 | 13724 | |
df58fc94 RS |
13725 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13726 | gas_assert (mips_opts.micromips); | |
13727 | { | |
13728 | /* A comma-separated list of registers and/or | |
13729 | dash-separated contiguous ranges including | |
13730 | at least one of ra and a set of one or more | |
13731 | registers starting at s0 up to s7 and then | |
13732 | s8 which have to be consecutive, e.g.: | |
13733 | ||
13734 | ra | |
13735 | s0 | |
13736 | ra, s0, s1, s2 | |
13737 | s0-s8 | |
13738 | s0-s5, ra | |
13739 | ||
13740 | and any permutations of these. */ | |
13741 | unsigned int reglist; | |
13742 | int imm; | |
13743 | int ra; | |
13744 | ||
13745 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13746 | break; | |
13747 | ||
13748 | if ((reglist & 0x3f00ffff) != 0) | |
13749 | break; | |
13750 | ||
13751 | ra = (reglist >> 27) & 0x10; | |
13752 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13753 | reglist += 1; | |
13754 | if ((reglist & -reglist) != reglist) | |
13755 | break; | |
13756 | ||
13757 | imm = (ffs (reglist) - 1) | ra; | |
13758 | INSERT_OPERAND (1, RT, *ip, imm); | |
13759 | imm_expr.X_op = O_absent; | |
13760 | } | |
60b63b72 RS |
13761 | continue; |
13762 | ||
df58fc94 RS |
13763 | case '|': /* 4-bit trap code. */ |
13764 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13765 | my_getExpression (&imm_expr, s); |
13766 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13767 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13768 | > MICROMIPSOP_MASK_TRAP) |
13769 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13770 | (unsigned long) imm_expr.X_add_number, | |
13771 | ip->insn_mo->name); | |
13772 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13773 | imm_expr.X_op = O_absent; |
13774 | s = expr_end; | |
13775 | continue; | |
13776 | ||
252b5132 | 13777 | default: |
f71d0d44 | 13778 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13779 | abort (); |
252b5132 RH |
13780 | } |
13781 | break; | |
13782 | } | |
13783 | /* Args don't match. */ | |
df58fc94 RS |
13784 | s = argsStart; |
13785 | insn_error = _("Illegal operands"); | |
13786 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13787 | { |
13788 | ++insn; | |
252b5132 RH |
13789 | continue; |
13790 | } | |
df58fc94 RS |
13791 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13792 | { | |
13793 | gas_assert (firstinsn); | |
13794 | need_delay_slot_ok = FALSE; | |
13795 | past = insn + 1; | |
13796 | insn = firstinsn; | |
13797 | continue; | |
13798 | } | |
252b5132 RH |
13799 | return; |
13800 | } | |
13801 | } | |
13802 | ||
0499d65b TS |
13803 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13804 | ||
252b5132 RH |
13805 | /* This routine assembles an instruction into its binary format when |
13806 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13807 | global variables imm_reloc or offset_reloc to the type of relocation |
13808 | to do if one of the operands is an address expression. It also sets | |
13809 | forced_insn_length to the resulting instruction size in bytes if the | |
13810 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13811 | |
13812 | static void | |
17a2f251 | 13813 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13814 | { |
13815 | char *s; | |
13816 | const char *args; | |
13817 | struct mips_opcode *insn; | |
13818 | char *argsstart; | |
13819 | unsigned int regno; | |
13820 | unsigned int lastregno = 0; | |
13821 | char *s_reset; | |
d6f16593 | 13822 | size_t i; |
252b5132 RH |
13823 | |
13824 | insn_error = NULL; | |
13825 | ||
df58fc94 | 13826 | forced_insn_length = 0; |
252b5132 | 13827 | |
3882b010 | 13828 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13829 | ; |
13830 | switch (*s) | |
13831 | { | |
13832 | case '\0': | |
13833 | break; | |
13834 | ||
13835 | case ' ': | |
13836 | *s++ = '\0'; | |
13837 | break; | |
13838 | ||
13839 | case '.': | |
13840 | if (s[1] == 't' && s[2] == ' ') | |
13841 | { | |
13842 | *s = '\0'; | |
df58fc94 | 13843 | forced_insn_length = 2; |
252b5132 RH |
13844 | s += 3; |
13845 | break; | |
13846 | } | |
13847 | else if (s[1] == 'e' && s[2] == ' ') | |
13848 | { | |
13849 | *s = '\0'; | |
df58fc94 | 13850 | forced_insn_length = 4; |
252b5132 RH |
13851 | s += 3; |
13852 | break; | |
13853 | } | |
13854 | /* Fall through. */ | |
13855 | default: | |
13856 | insn_error = _("unknown opcode"); | |
13857 | return; | |
13858 | } | |
13859 | ||
df58fc94 RS |
13860 | if (mips_opts.noautoextend && !forced_insn_length) |
13861 | forced_insn_length = 2; | |
252b5132 RH |
13862 | |
13863 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13864 | { | |
13865 | insn_error = _("unrecognized opcode"); | |
13866 | return; | |
13867 | } | |
13868 | ||
13869 | argsstart = s; | |
13870 | for (;;) | |
13871 | { | |
9b3f89ee TS |
13872 | bfd_boolean ok; |
13873 | ||
9c2799c2 | 13874 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13875 | |
037b32b9 | 13876 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13877 | if (! ok) |
13878 | { | |
13879 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13880 | && strcmp (insn->name, insn[1].name) == 0) | |
13881 | { | |
13882 | ++insn; | |
13883 | continue; | |
13884 | } | |
13885 | else | |
13886 | { | |
13887 | if (!insn_error) | |
13888 | { | |
13889 | static char buf[100]; | |
13890 | sprintf (buf, | |
7bd942df | 13891 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13892 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13893 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13894 | insn_error = buf; | |
13895 | } | |
13896 | return; | |
13897 | } | |
13898 | } | |
13899 | ||
1e915849 | 13900 | create_insn (ip, insn); |
252b5132 | 13901 | imm_expr.X_op = O_absent; |
f6688943 TS |
13902 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13903 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13904 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13905 | imm2_expr.X_op = O_absent; |
252b5132 | 13906 | offset_expr.X_op = O_absent; |
f6688943 TS |
13907 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13908 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13909 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13910 | for (args = insn->args; 1; ++args) |
13911 | { | |
13912 | int c; | |
13913 | ||
13914 | if (*s == ' ') | |
13915 | ++s; | |
13916 | ||
13917 | /* In this switch statement we call break if we did not find | |
13918 | a match, continue if we did find a match, or return if we | |
13919 | are done. */ | |
13920 | ||
13921 | c = *args; | |
13922 | switch (c) | |
13923 | { | |
13924 | case '\0': | |
13925 | if (*s == '\0') | |
13926 | { | |
b886a2ab RS |
13927 | offsetT value; |
13928 | ||
252b5132 RH |
13929 | /* Stuff the immediate value in now, if we can. */ |
13930 | if (imm_expr.X_op == O_constant | |
f6688943 | 13931 | && *imm_reloc > BFD_RELOC_UNUSED |
b886a2ab RS |
13932 | && insn->pinfo != INSN_MACRO |
13933 | && calculate_reloc (*offset_reloc, | |
13934 | imm_expr.X_add_number, &value)) | |
252b5132 | 13935 | { |
c4e7957c | 13936 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b886a2ab | 13937 | *offset_reloc, value, forced_insn_length, |
43c0598f | 13938 | &ip->insn_opcode); |
252b5132 | 13939 | imm_expr.X_op = O_absent; |
f6688943 | 13940 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13941 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13942 | } |
13943 | ||
13944 | return; | |
13945 | } | |
13946 | break; | |
13947 | ||
13948 | case ',': | |
13949 | if (*s++ == c) | |
13950 | continue; | |
13951 | s--; | |
13952 | switch (*++args) | |
13953 | { | |
13954 | case 'v': | |
bf12938e | 13955 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13956 | continue; |
13957 | case 'w': | |
bf12938e | 13958 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13959 | continue; |
13960 | } | |
13961 | break; | |
13962 | ||
13963 | case '(': | |
13964 | case ')': | |
13965 | if (*s++ == c) | |
13966 | continue; | |
13967 | break; | |
13968 | ||
13969 | case 'v': | |
13970 | case 'w': | |
13971 | if (s[0] != '$') | |
13972 | { | |
13973 | if (c == 'v') | |
bf12938e | 13974 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13975 | else |
bf12938e | 13976 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13977 | ++args; |
13978 | continue; | |
13979 | } | |
13980 | /* Fall through. */ | |
13981 | case 'x': | |
13982 | case 'y': | |
13983 | case 'z': | |
13984 | case 'Z': | |
13985 | case '0': | |
13986 | case 'S': | |
13987 | case 'R': | |
13988 | case 'X': | |
13989 | case 'Y': | |
707bfff6 TS |
13990 | s_reset = s; |
13991 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13992 | { |
707bfff6 | 13993 | if (c == 'v' || c == 'w') |
85b51719 | 13994 | { |
707bfff6 | 13995 | if (c == 'v') |
a9e24354 | 13996 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13997 | else |
a9e24354 | 13998 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13999 | ++args; |
14000 | continue; | |
85b51719 | 14001 | } |
707bfff6 | 14002 | break; |
252b5132 RH |
14003 | } |
14004 | ||
14005 | if (*s == ' ') | |
14006 | ++s; | |
14007 | if (args[1] != *s) | |
14008 | { | |
14009 | if (c == 'v' || c == 'w') | |
14010 | { | |
14011 | regno = mips16_to_32_reg_map[lastregno]; | |
14012 | s = s_reset; | |
f9419b05 | 14013 | ++args; |
252b5132 RH |
14014 | } |
14015 | } | |
14016 | ||
14017 | switch (c) | |
14018 | { | |
14019 | case 'x': | |
14020 | case 'y': | |
14021 | case 'z': | |
14022 | case 'v': | |
14023 | case 'w': | |
14024 | case 'Z': | |
14025 | regno = mips32_to_16_reg_map[regno]; | |
14026 | break; | |
14027 | ||
14028 | case '0': | |
14029 | if (regno != 0) | |
14030 | regno = ILLEGAL_REG; | |
14031 | break; | |
14032 | ||
14033 | case 'S': | |
14034 | if (regno != SP) | |
14035 | regno = ILLEGAL_REG; | |
14036 | break; | |
14037 | ||
14038 | case 'R': | |
14039 | if (regno != RA) | |
14040 | regno = ILLEGAL_REG; | |
14041 | break; | |
14042 | ||
14043 | case 'X': | |
14044 | case 'Y': | |
741fe287 MR |
14045 | if (regno == AT && mips_opts.at) |
14046 | { | |
14047 | if (mips_opts.at == ATREG) | |
14048 | as_warn (_("used $at without \".set noat\"")); | |
14049 | else | |
14050 | as_warn (_("used $%u with \".set at=$%u\""), | |
14051 | regno, mips_opts.at); | |
14052 | } | |
252b5132 RH |
14053 | break; |
14054 | ||
14055 | default: | |
b37df7c4 | 14056 | abort (); |
252b5132 RH |
14057 | } |
14058 | ||
14059 | if (regno == ILLEGAL_REG) | |
14060 | break; | |
14061 | ||
14062 | switch (c) | |
14063 | { | |
14064 | case 'x': | |
14065 | case 'v': | |
bf12938e | 14066 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
14067 | break; |
14068 | case 'y': | |
14069 | case 'w': | |
bf12938e | 14070 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
14071 | break; |
14072 | case 'z': | |
bf12938e | 14073 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
14074 | break; |
14075 | case 'Z': | |
bf12938e | 14076 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
14077 | case '0': |
14078 | case 'S': | |
14079 | case 'R': | |
14080 | break; | |
14081 | case 'X': | |
bf12938e | 14082 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
14083 | break; |
14084 | case 'Y': | |
14085 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 14086 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
14087 | break; |
14088 | default: | |
b37df7c4 | 14089 | abort (); |
252b5132 RH |
14090 | } |
14091 | ||
14092 | lastregno = regno; | |
14093 | continue; | |
14094 | ||
14095 | case 'P': | |
14096 | if (strncmp (s, "$pc", 3) == 0) | |
14097 | { | |
14098 | s += 3; | |
14099 | continue; | |
14100 | } | |
14101 | break; | |
14102 | ||
252b5132 RH |
14103 | case '5': |
14104 | case 'H': | |
14105 | case 'W': | |
14106 | case 'D': | |
14107 | case 'j': | |
252b5132 RH |
14108 | case 'V': |
14109 | case 'C': | |
14110 | case 'U': | |
14111 | case 'k': | |
14112 | case 'K': | |
d6f16593 MR |
14113 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
14114 | if (i > 0) | |
252b5132 | 14115 | { |
d6f16593 | 14116 | if (imm_expr.X_op != O_constant) |
252b5132 | 14117 | { |
df58fc94 | 14118 | forced_insn_length = 4; |
5c04167a | 14119 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 14120 | } |
d6f16593 MR |
14121 | else |
14122 | { | |
14123 | /* We need to relax this instruction. */ | |
14124 | *offset_reloc = *imm_reloc; | |
14125 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
14126 | } | |
14127 | s = expr_end; | |
14128 | continue; | |
252b5132 | 14129 | } |
d6f16593 MR |
14130 | *imm_reloc = BFD_RELOC_UNUSED; |
14131 | /* Fall through. */ | |
14132 | case '<': | |
14133 | case '>': | |
14134 | case '[': | |
14135 | case ']': | |
14136 | case '4': | |
14137 | case '8': | |
14138 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
14139 | if (imm_expr.X_op == O_register) |
14140 | { | |
14141 | /* What we thought was an expression turned out to | |
14142 | be a register. */ | |
14143 | ||
14144 | if (s[0] == '(' && args[1] == '(') | |
14145 | { | |
14146 | /* It looks like the expression was omitted | |
14147 | before a register indirection, which means | |
14148 | that the expression is implicitly zero. We | |
14149 | still set up imm_expr, so that we handle | |
14150 | explicit extensions correctly. */ | |
14151 | imm_expr.X_op = O_constant; | |
14152 | imm_expr.X_add_number = 0; | |
f6688943 | 14153 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14154 | continue; |
14155 | } | |
14156 | ||
14157 | break; | |
14158 | } | |
14159 | ||
14160 | /* We need to relax this instruction. */ | |
f6688943 | 14161 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14162 | s = expr_end; |
14163 | continue; | |
14164 | ||
14165 | case 'p': | |
14166 | case 'q': | |
14167 | case 'A': | |
14168 | case 'B': | |
14169 | case 'E': | |
14170 | /* We use offset_reloc rather than imm_reloc for the PC | |
14171 | relative operands. This lets macros with both | |
14172 | immediate and address operands work correctly. */ | |
14173 | my_getExpression (&offset_expr, s); | |
14174 | ||
14175 | if (offset_expr.X_op == O_register) | |
14176 | break; | |
14177 | ||
14178 | /* We need to relax this instruction. */ | |
f6688943 | 14179 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
14180 | s = expr_end; |
14181 | continue; | |
14182 | ||
14183 | case '6': /* break code */ | |
14184 | my_getExpression (&imm_expr, s); | |
14185 | check_absolute_expr (ip, &imm_expr); | |
14186 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14187 | as_warn (_("Invalid value for `%s' (%lu)"), |
14188 | ip->insn_mo->name, | |
14189 | (unsigned long) imm_expr.X_add_number); | |
14190 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14191 | imm_expr.X_op = O_absent; |
14192 | s = expr_end; | |
14193 | continue; | |
14194 | ||
14195 | case 'a': /* 26 bit address */ | |
14196 | my_getExpression (&offset_expr, s); | |
14197 | s = expr_end; | |
f6688943 | 14198 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14199 | ip->insn_opcode <<= 16; |
14200 | continue; | |
14201 | ||
14202 | case 'l': /* register list for entry macro */ | |
14203 | case 'L': /* register list for exit macro */ | |
14204 | { | |
14205 | int mask; | |
14206 | ||
14207 | if (c == 'l') | |
14208 | mask = 0; | |
14209 | else | |
14210 | mask = 7 << 3; | |
14211 | while (*s != '\0') | |
14212 | { | |
707bfff6 | 14213 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14214 | |
14215 | while (*s == ' ' || *s == ',') | |
14216 | ++s; | |
707bfff6 | 14217 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14218 | freg = 0; |
707bfff6 TS |
14219 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14220 | freg = 1; | |
252b5132 RH |
14221 | else |
14222 | { | |
707bfff6 TS |
14223 | as_bad (_("can't parse register list")); |
14224 | break; | |
252b5132 RH |
14225 | } |
14226 | if (*s == ' ') | |
14227 | ++s; | |
14228 | if (*s != '-') | |
14229 | reg2 = reg1; | |
14230 | else | |
14231 | { | |
14232 | ++s; | |
707bfff6 TS |
14233 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14234 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14235 | { |
707bfff6 TS |
14236 | as_bad (_("invalid register list")); |
14237 | break; | |
252b5132 RH |
14238 | } |
14239 | } | |
14240 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14241 | { | |
14242 | mask &= ~ (7 << 3); | |
14243 | mask |= 5 << 3; | |
14244 | } | |
14245 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14246 | { | |
14247 | mask &= ~ (7 << 3); | |
14248 | mask |= 6 << 3; | |
14249 | } | |
14250 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14251 | mask |= (reg2 - 3) << 3; | |
14252 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14253 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14254 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14255 | mask |= 1; |
14256 | else | |
14257 | { | |
14258 | as_bad (_("invalid register list")); | |
14259 | break; | |
14260 | } | |
14261 | } | |
14262 | /* The mask is filled in in the opcode table for the | |
14263 | benefit of the disassembler. We remove it before | |
14264 | applying the actual mask. */ | |
14265 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14266 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14267 | } | |
14268 | continue; | |
14269 | ||
0499d65b TS |
14270 | case 'm': /* Register list for save insn. */ |
14271 | case 'M': /* Register list for restore insn. */ | |
14272 | { | |
5c04167a | 14273 | int opcode = ip->insn_opcode; |
0499d65b | 14274 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14275 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14276 | |
14277 | while (*s != '\0') | |
14278 | { | |
14279 | unsigned int reg1, reg2; | |
14280 | ||
14281 | SKIP_SPACE_TABS (s); | |
14282 | while (*s == ',') | |
14283 | ++s; | |
14284 | SKIP_SPACE_TABS (s); | |
14285 | ||
14286 | my_getExpression (&imm_expr, s); | |
14287 | if (imm_expr.X_op == O_constant) | |
14288 | { | |
14289 | /* Handle the frame size. */ | |
14290 | if (seen_framesz) | |
14291 | { | |
14292 | as_bad (_("more than one frame size in list")); | |
14293 | break; | |
14294 | } | |
14295 | seen_framesz = 1; | |
14296 | framesz = imm_expr.X_add_number; | |
14297 | imm_expr.X_op = O_absent; | |
14298 | s = expr_end; | |
14299 | continue; | |
14300 | } | |
14301 | ||
707bfff6 | 14302 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14303 | { |
14304 | as_bad (_("can't parse register list")); | |
14305 | break; | |
14306 | } | |
0499d65b | 14307 | |
707bfff6 TS |
14308 | while (*s == ' ') |
14309 | ++s; | |
14310 | ||
0499d65b TS |
14311 | if (*s != '-') |
14312 | reg2 = reg1; | |
14313 | else | |
14314 | { | |
14315 | ++s; | |
707bfff6 TS |
14316 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14317 | || reg2 < reg1) | |
0499d65b TS |
14318 | { |
14319 | as_bad (_("can't parse register list")); | |
14320 | break; | |
14321 | } | |
0499d65b TS |
14322 | } |
14323 | ||
14324 | while (reg1 <= reg2) | |
14325 | { | |
14326 | if (reg1 >= 4 && reg1 <= 7) | |
14327 | { | |
3a93f742 | 14328 | if (!seen_framesz) |
0499d65b | 14329 | /* args $a0-$a3 */ |
91d6fa6a | 14330 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14331 | else |
14332 | /* statics $a0-$a3 */ | |
14333 | statics |= 1 << (reg1 - 4); | |
14334 | } | |
14335 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14336 | { | |
14337 | /* $s0-$s8 */ | |
14338 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14339 | } | |
14340 | else if (reg1 == 31) | |
14341 | { | |
14342 | /* Add $ra to insn. */ | |
14343 | opcode |= 0x40; | |
14344 | } | |
14345 | else | |
14346 | { | |
14347 | as_bad (_("unexpected register in list")); | |
14348 | break; | |
14349 | } | |
14350 | if (++reg1 == 24) | |
14351 | reg1 = 30; | |
14352 | } | |
14353 | } | |
14354 | ||
14355 | /* Encode args/statics combination. */ | |
91d6fa6a | 14356 | if (nargs & statics) |
0499d65b | 14357 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14358 | else if (nargs == 0xf) |
0499d65b TS |
14359 | /* All $a0-$a3 are args. */ |
14360 | opcode |= MIPS16_ALL_ARGS << 16; | |
14361 | else if (statics == 0xf) | |
14362 | /* All $a0-$a3 are statics. */ | |
14363 | opcode |= MIPS16_ALL_STATICS << 16; | |
14364 | else | |
14365 | { | |
14366 | int narg = 0, nstat = 0; | |
14367 | ||
14368 | /* Count arg registers. */ | |
91d6fa6a | 14369 | while (nargs & 0x1) |
0499d65b | 14370 | { |
91d6fa6a | 14371 | nargs >>= 1; |
0499d65b TS |
14372 | narg++; |
14373 | } | |
91d6fa6a | 14374 | if (nargs != 0) |
0499d65b TS |
14375 | as_bad (_("invalid arg register list")); |
14376 | ||
14377 | /* Count static registers. */ | |
14378 | while (statics & 0x8) | |
14379 | { | |
14380 | statics = (statics << 1) & 0xf; | |
14381 | nstat++; | |
14382 | } | |
14383 | if (statics != 0) | |
14384 | as_bad (_("invalid static register list")); | |
14385 | ||
14386 | /* Encode args/statics. */ | |
14387 | opcode |= ((narg << 2) | nstat) << 16; | |
14388 | } | |
14389 | ||
14390 | /* Encode $s0/$s1. */ | |
14391 | if (sregs & (1 << 0)) /* $s0 */ | |
14392 | opcode |= 0x20; | |
14393 | if (sregs & (1 << 1)) /* $s1 */ | |
14394 | opcode |= 0x10; | |
14395 | sregs >>= 2; | |
14396 | ||
14397 | if (sregs != 0) | |
14398 | { | |
14399 | /* Count regs $s2-$s8. */ | |
14400 | int nsreg = 0; | |
14401 | while (sregs & 1) | |
14402 | { | |
14403 | sregs >>= 1; | |
14404 | nsreg++; | |
14405 | } | |
14406 | if (sregs != 0) | |
14407 | as_bad (_("invalid static register list")); | |
14408 | /* Encode $s2-$s8. */ | |
14409 | opcode |= nsreg << 24; | |
14410 | } | |
14411 | ||
14412 | /* Encode frame size. */ | |
14413 | if (!seen_framesz) | |
14414 | as_bad (_("missing frame size")); | |
14415 | else if ((framesz & 7) != 0 || framesz < 0 | |
14416 | || framesz > 0xff * 8) | |
14417 | as_bad (_("invalid frame size")); | |
14418 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14419 | { | |
14420 | framesz /= 8; | |
14421 | opcode |= (((framesz & 0xf0) << 16) | |
14422 | | (framesz & 0x0f)); | |
14423 | } | |
14424 | ||
14425 | /* Finally build the instruction. */ | |
14426 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14427 | opcode |= MIPS16_EXTEND; |
14428 | ip->insn_opcode = opcode; | |
0499d65b TS |
14429 | } |
14430 | continue; | |
14431 | ||
252b5132 RH |
14432 | case 'e': /* extend code */ |
14433 | my_getExpression (&imm_expr, s); | |
14434 | check_absolute_expr (ip, &imm_expr); | |
14435 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14436 | { | |
14437 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14438 | ip->insn_mo->name, | |
14439 | (unsigned long) imm_expr.X_add_number); | |
14440 | imm_expr.X_add_number &= 0x7ff; | |
14441 | } | |
14442 | ip->insn_opcode |= imm_expr.X_add_number; | |
14443 | imm_expr.X_op = O_absent; | |
14444 | s = expr_end; | |
14445 | continue; | |
14446 | ||
14447 | default: | |
b37df7c4 | 14448 | abort (); |
252b5132 RH |
14449 | } |
14450 | break; | |
14451 | } | |
14452 | ||
14453 | /* Args don't match. */ | |
14454 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14455 | strcmp (insn->name, insn[1].name) == 0) | |
14456 | { | |
14457 | ++insn; | |
14458 | s = argsstart; | |
14459 | continue; | |
14460 | } | |
14461 | ||
14462 | insn_error = _("illegal operands"); | |
14463 | ||
14464 | return; | |
14465 | } | |
14466 | } | |
14467 | ||
14468 | /* This structure holds information we know about a mips16 immediate | |
14469 | argument type. */ | |
14470 | ||
e972090a NC |
14471 | struct mips16_immed_operand |
14472 | { | |
252b5132 RH |
14473 | /* The type code used in the argument string in the opcode table. */ |
14474 | int type; | |
14475 | /* The number of bits in the short form of the opcode. */ | |
14476 | int nbits; | |
14477 | /* The number of bits in the extended form of the opcode. */ | |
14478 | int extbits; | |
14479 | /* The amount by which the short form is shifted when it is used; | |
14480 | for example, the sw instruction has a shift count of 2. */ | |
14481 | int shift; | |
14482 | /* The amount by which the short form is shifted when it is stored | |
14483 | into the instruction code. */ | |
14484 | int op_shift; | |
14485 | /* Non-zero if the short form is unsigned. */ | |
14486 | int unsp; | |
14487 | /* Non-zero if the extended form is unsigned. */ | |
14488 | int extu; | |
14489 | /* Non-zero if the value is PC relative. */ | |
14490 | int pcrel; | |
14491 | }; | |
14492 | ||
14493 | /* The mips16 immediate operand types. */ | |
14494 | ||
14495 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14496 | { | |
14497 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14498 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14499 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14500 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14501 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14502 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14503 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14504 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14505 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14506 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14507 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14508 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14509 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14510 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14511 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14512 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14513 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14514 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14515 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14516 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14517 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14518 | }; | |
14519 | ||
14520 | #define MIPS16_NUM_IMMED \ | |
14521 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14522 | ||
b886a2ab RS |
14523 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14524 | NBITS is the number of significant bits in VAL. */ | |
14525 | ||
14526 | static unsigned long | |
14527 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14528 | { | |
14529 | int extval; | |
14530 | if (nbits == 16) | |
14531 | { | |
14532 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14533 | val &= 0x1f; | |
14534 | } | |
14535 | else if (nbits == 15) | |
14536 | { | |
14537 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14538 | val &= 0xf; | |
14539 | } | |
14540 | else | |
14541 | { | |
14542 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14543 | val = 0; | |
14544 | } | |
14545 | return (extval << 16) | val; | |
14546 | } | |
14547 | ||
5c04167a RS |
14548 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14549 | extending it if necessary. The instruction in *INSN may | |
14550 | already be extended. | |
14551 | ||
43c0598f RS |
14552 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14553 | if none. In the former case, VAL is a 16-bit number with no | |
14554 | defined signedness. | |
14555 | ||
14556 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14557 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14558 | |
14559 | static void | |
43c0598f RS |
14560 | mips16_immed (char *file, unsigned int line, int type, |
14561 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14562 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14563 | { |
3994f87e | 14564 | const struct mips16_immed_operand *op; |
252b5132 | 14565 | int mintiny, maxtiny; |
252b5132 RH |
14566 | |
14567 | op = mips16_immed_operands; | |
14568 | while (op->type != type) | |
14569 | { | |
14570 | ++op; | |
9c2799c2 | 14571 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14572 | } |
14573 | ||
14574 | if (op->unsp) | |
14575 | { | |
14576 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14577 | { | |
14578 | mintiny = 1; | |
14579 | maxtiny = 1 << op->nbits; | |
14580 | } | |
14581 | else | |
14582 | { | |
14583 | mintiny = 0; | |
14584 | maxtiny = (1 << op->nbits) - 1; | |
14585 | } | |
43c0598f RS |
14586 | if (reloc != BFD_RELOC_UNUSED) |
14587 | val &= 0xffff; | |
252b5132 RH |
14588 | } |
14589 | else | |
14590 | { | |
14591 | mintiny = - (1 << (op->nbits - 1)); | |
14592 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14593 | if (reloc != BFD_RELOC_UNUSED) |
14594 | val = SEXT_16BIT (val); | |
252b5132 RH |
14595 | } |
14596 | ||
14597 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14598 | if (type == 'p' || type == 'q') | |
14599 | val /= 2; | |
14600 | ||
14601 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14602 | || val < (mintiny << op->shift) | |
14603 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14604 | { |
14605 | /* We need an extended instruction. */ | |
14606 | if (user_insn_length == 2) | |
14607 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14608 | else | |
14609 | *insn |= MIPS16_EXTEND; | |
14610 | } | |
14611 | else if (user_insn_length == 4) | |
14612 | { | |
14613 | /* The operand doesn't force an unextended instruction to be extended. | |
14614 | Warn if the user wanted an extended instruction anyway. */ | |
14615 | *insn |= MIPS16_EXTEND; | |
14616 | as_warn_where (file, line, | |
14617 | _("extended operand requested but not required")); | |
14618 | } | |
252b5132 | 14619 | |
5c04167a | 14620 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14621 | { |
14622 | int insnval; | |
14623 | ||
252b5132 RH |
14624 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14625 | insnval <<= op->op_shift; | |
14626 | *insn |= insnval; | |
14627 | } | |
14628 | else | |
14629 | { | |
14630 | long minext, maxext; | |
252b5132 | 14631 | |
43c0598f | 14632 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14633 | { |
43c0598f RS |
14634 | if (op->extu) |
14635 | { | |
14636 | minext = 0; | |
14637 | maxext = (1 << op->extbits) - 1; | |
14638 | } | |
14639 | else | |
14640 | { | |
14641 | minext = - (1 << (op->extbits - 1)); | |
14642 | maxext = (1 << (op->extbits - 1)) - 1; | |
14643 | } | |
14644 | if (val < minext || val > maxext) | |
14645 | as_bad_where (file, line, | |
14646 | _("operand value out of range for instruction")); | |
252b5132 | 14647 | } |
252b5132 | 14648 | |
b886a2ab | 14649 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14650 | } |
14651 | } | |
14652 | \f | |
d6f16593 | 14653 | struct percent_op_match |
ad8d3bb3 | 14654 | { |
5e0116d5 RS |
14655 | const char *str; |
14656 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14657 | }; |
14658 | ||
14659 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14660 | { |
5e0116d5 | 14661 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14662 | #ifdef OBJ_ELF |
5e0116d5 RS |
14663 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14664 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14665 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14666 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14667 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14668 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14669 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14670 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14671 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14672 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14673 | {"%half", BFD_RELOC_16}, | |
14674 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14675 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14676 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14677 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14678 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14679 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14680 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14681 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14682 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14683 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14684 | #endif |
5e0116d5 | 14685 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14686 | }; |
14687 | ||
d6f16593 MR |
14688 | static const struct percent_op_match mips16_percent_op[] = |
14689 | { | |
14690 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14691 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14692 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14693 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14694 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14695 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14696 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14697 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14698 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14699 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14700 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14701 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14702 | }; |
14703 | ||
252b5132 | 14704 | |
5e0116d5 RS |
14705 | /* Return true if *STR points to a relocation operator. When returning true, |
14706 | move *STR over the operator and store its relocation code in *RELOC. | |
14707 | Leave both *STR and *RELOC alone when returning false. */ | |
14708 | ||
14709 | static bfd_boolean | |
17a2f251 | 14710 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14711 | { |
d6f16593 MR |
14712 | const struct percent_op_match *percent_op; |
14713 | size_t limit, i; | |
14714 | ||
14715 | if (mips_opts.mips16) | |
14716 | { | |
14717 | percent_op = mips16_percent_op; | |
14718 | limit = ARRAY_SIZE (mips16_percent_op); | |
14719 | } | |
14720 | else | |
14721 | { | |
14722 | percent_op = mips_percent_op; | |
14723 | limit = ARRAY_SIZE (mips_percent_op); | |
14724 | } | |
76b3015f | 14725 | |
d6f16593 | 14726 | for (i = 0; i < limit; i++) |
5e0116d5 | 14727 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14728 | { |
3f98094e DJ |
14729 | int len = strlen (percent_op[i].str); |
14730 | ||
14731 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14732 | continue; | |
14733 | ||
5e0116d5 RS |
14734 | *str += strlen (percent_op[i].str); |
14735 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14736 | |
5e0116d5 RS |
14737 | /* Check whether the output BFD supports this relocation. |
14738 | If not, issue an error and fall back on something safe. */ | |
14739 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14740 | { |
20203fb9 | 14741 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14742 | percent_op[i].str); |
01a3f561 | 14743 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14744 | } |
5e0116d5 | 14745 | return TRUE; |
394f9b3a | 14746 | } |
5e0116d5 | 14747 | return FALSE; |
394f9b3a | 14748 | } |
ad8d3bb3 | 14749 | |
ad8d3bb3 | 14750 | |
5e0116d5 RS |
14751 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14752 | expression in *EP and the relocations in the array starting | |
14753 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14754 | |
01a3f561 | 14755 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14756 | |
5e0116d5 | 14757 | static size_t |
17a2f251 TS |
14758 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14759 | char *str) | |
ad8d3bb3 | 14760 | { |
5e0116d5 RS |
14761 | bfd_reloc_code_real_type reversed_reloc[3]; |
14762 | size_t reloc_index, i; | |
09b8f35a RS |
14763 | int crux_depth, str_depth; |
14764 | char *crux; | |
5e0116d5 RS |
14765 | |
14766 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14767 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14768 | of the main expression and with CRUX_DEPTH containing the number | |
14769 | of open brackets at that point. */ | |
14770 | reloc_index = -1; | |
14771 | str_depth = 0; | |
14772 | do | |
fb1b3232 | 14773 | { |
09b8f35a RS |
14774 | reloc_index++; |
14775 | crux = str; | |
14776 | crux_depth = str_depth; | |
14777 | ||
14778 | /* Skip over whitespace and brackets, keeping count of the number | |
14779 | of brackets. */ | |
14780 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14781 | if (*str++ == '(') | |
14782 | str_depth++; | |
5e0116d5 | 14783 | } |
09b8f35a RS |
14784 | while (*str == '%' |
14785 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14786 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14787 | |
09b8f35a | 14788 | my_getExpression (ep, crux); |
5e0116d5 | 14789 | str = expr_end; |
394f9b3a | 14790 | |
5e0116d5 | 14791 | /* Match every open bracket. */ |
09b8f35a | 14792 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14793 | if (*str++ == ')') |
09b8f35a | 14794 | crux_depth--; |
394f9b3a | 14795 | |
09b8f35a | 14796 | if (crux_depth > 0) |
20203fb9 | 14797 | as_bad (_("unclosed '('")); |
394f9b3a | 14798 | |
5e0116d5 | 14799 | expr_end = str; |
252b5132 | 14800 | |
01a3f561 | 14801 | if (reloc_index != 0) |
64bdfcaf RS |
14802 | { |
14803 | prev_reloc_op_frag = frag_now; | |
14804 | for (i = 0; i < reloc_index; i++) | |
14805 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14806 | } | |
fb1b3232 | 14807 | |
5e0116d5 | 14808 | return reloc_index; |
252b5132 RH |
14809 | } |
14810 | ||
14811 | static void | |
17a2f251 | 14812 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14813 | { |
14814 | char *save_in; | |
14815 | ||
14816 | save_in = input_line_pointer; | |
14817 | input_line_pointer = str; | |
14818 | expression (ep); | |
14819 | expr_end = input_line_pointer; | |
14820 | input_line_pointer = save_in; | |
252b5132 RH |
14821 | } |
14822 | ||
252b5132 | 14823 | char * |
17a2f251 | 14824 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14825 | { |
499ac353 | 14826 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14827 | } |
14828 | ||
14829 | void | |
17a2f251 | 14830 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14831 | { |
14832 | if (target_big_endian) | |
14833 | number_to_chars_bigendian (buf, val, n); | |
14834 | else | |
14835 | number_to_chars_littleendian (buf, val, n); | |
14836 | } | |
14837 | \f | |
ae948b86 | 14838 | #ifdef OBJ_ELF |
e013f690 TS |
14839 | static int support_64bit_objects(void) |
14840 | { | |
14841 | const char **list, **l; | |
aa3d8fdf | 14842 | int yes; |
e013f690 TS |
14843 | |
14844 | list = bfd_target_list (); | |
14845 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14846 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14847 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14848 | break; |
aa3d8fdf | 14849 | yes = (*l != NULL); |
e013f690 | 14850 | free (list); |
aa3d8fdf | 14851 | return yes; |
e013f690 | 14852 | } |
ae948b86 | 14853 | #endif /* OBJ_ELF */ |
e013f690 | 14854 | |
316f5878 RS |
14855 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14856 | NEW_VALUE. Warn if another value was already specified. Note: | |
14857 | we have to defer parsing the -march and -mtune arguments in order | |
14858 | to handle 'from-abi' correctly, since the ABI might be specified | |
14859 | in a later argument. */ | |
14860 | ||
14861 | static void | |
17a2f251 | 14862 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14863 | { |
14864 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14865 | as_warn (_("A different %s was already specified, is now %s"), | |
14866 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14867 | new_value); | |
14868 | ||
14869 | *string_ptr = new_value; | |
14870 | } | |
14871 | ||
252b5132 | 14872 | int |
17a2f251 | 14873 | md_parse_option (int c, char *arg) |
252b5132 RH |
14874 | { |
14875 | switch (c) | |
14876 | { | |
119d663a NC |
14877 | case OPTION_CONSTRUCT_FLOATS: |
14878 | mips_disable_float_construction = 0; | |
14879 | break; | |
bdaaa2e1 | 14880 | |
119d663a NC |
14881 | case OPTION_NO_CONSTRUCT_FLOATS: |
14882 | mips_disable_float_construction = 1; | |
14883 | break; | |
bdaaa2e1 | 14884 | |
252b5132 RH |
14885 | case OPTION_TRAP: |
14886 | mips_trap = 1; | |
14887 | break; | |
14888 | ||
14889 | case OPTION_BREAK: | |
14890 | mips_trap = 0; | |
14891 | break; | |
14892 | ||
14893 | case OPTION_EB: | |
14894 | target_big_endian = 1; | |
14895 | break; | |
14896 | ||
14897 | case OPTION_EL: | |
14898 | target_big_endian = 0; | |
14899 | break; | |
14900 | ||
14901 | case 'O': | |
4ffff32f TS |
14902 | if (arg == NULL) |
14903 | mips_optimize = 1; | |
14904 | else if (arg[0] == '0') | |
14905 | mips_optimize = 0; | |
14906 | else if (arg[0] == '1') | |
252b5132 RH |
14907 | mips_optimize = 1; |
14908 | else | |
14909 | mips_optimize = 2; | |
14910 | break; | |
14911 | ||
14912 | case 'g': | |
14913 | if (arg == NULL) | |
14914 | mips_debug = 2; | |
14915 | else | |
14916 | mips_debug = atoi (arg); | |
252b5132 RH |
14917 | break; |
14918 | ||
14919 | case OPTION_MIPS1: | |
316f5878 | 14920 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14921 | break; |
14922 | ||
14923 | case OPTION_MIPS2: | |
316f5878 | 14924 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14925 | break; |
14926 | ||
14927 | case OPTION_MIPS3: | |
316f5878 | 14928 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14929 | break; |
14930 | ||
14931 | case OPTION_MIPS4: | |
316f5878 | 14932 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14933 | break; |
14934 | ||
84ea6cf2 | 14935 | case OPTION_MIPS5: |
316f5878 | 14936 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14937 | break; |
14938 | ||
e7af610e | 14939 | case OPTION_MIPS32: |
316f5878 | 14940 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14941 | break; |
14942 | ||
af7ee8bf CD |
14943 | case OPTION_MIPS32R2: |
14944 | file_mips_isa = ISA_MIPS32R2; | |
14945 | break; | |
14946 | ||
5f74bc13 CD |
14947 | case OPTION_MIPS64R2: |
14948 | file_mips_isa = ISA_MIPS64R2; | |
14949 | break; | |
14950 | ||
84ea6cf2 | 14951 | case OPTION_MIPS64: |
316f5878 | 14952 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14953 | break; |
14954 | ||
ec68c924 | 14955 | case OPTION_MTUNE: |
316f5878 RS |
14956 | mips_set_option_string (&mips_tune_string, arg); |
14957 | break; | |
ec68c924 | 14958 | |
316f5878 RS |
14959 | case OPTION_MARCH: |
14960 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14961 | break; |
14962 | ||
14963 | case OPTION_M4650: | |
316f5878 RS |
14964 | mips_set_option_string (&mips_arch_string, "4650"); |
14965 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14966 | break; |
14967 | ||
14968 | case OPTION_NO_M4650: | |
14969 | break; | |
14970 | ||
14971 | case OPTION_M4010: | |
316f5878 RS |
14972 | mips_set_option_string (&mips_arch_string, "4010"); |
14973 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14974 | break; |
14975 | ||
14976 | case OPTION_NO_M4010: | |
14977 | break; | |
14978 | ||
14979 | case OPTION_M4100: | |
316f5878 RS |
14980 | mips_set_option_string (&mips_arch_string, "4100"); |
14981 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14982 | break; |
14983 | ||
14984 | case OPTION_NO_M4100: | |
14985 | break; | |
14986 | ||
252b5132 | 14987 | case OPTION_M3900: |
316f5878 RS |
14988 | mips_set_option_string (&mips_arch_string, "3900"); |
14989 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14990 | break; |
bdaaa2e1 | 14991 | |
252b5132 RH |
14992 | case OPTION_NO_M3900: |
14993 | break; | |
14994 | ||
deec1734 | 14995 | case OPTION_MDMX: |
846ef2d0 RS |
14996 | mips_opts.ase |= ASE_MDMX; |
14997 | file_ase_explicit |= ASE_MDMX; | |
deec1734 CD |
14998 | break; |
14999 | ||
15000 | case OPTION_NO_MDMX: | |
846ef2d0 RS |
15001 | mips_opts.ase &= ~ASE_MDMX; |
15002 | file_ase_explicit |= ASE_MDMX; | |
deec1734 CD |
15003 | break; |
15004 | ||
74cd071d | 15005 | case OPTION_DSP: |
846ef2d0 RS |
15006 | mips_opts.ase |= ASE_DSP; |
15007 | mips_opts.ase &= ~ASE_DSPR2; | |
15008 | file_ase_explicit |= ASE_DSP | ASE_DSPR2; | |
8b082fb1 TS |
15009 | break; |
15010 | ||
15011 | case OPTION_DSPR2: | |
846ef2d0 RS |
15012 | mips_opts.ase |= ASE_DSP | ASE_DSPR2; |
15013 | file_ase_explicit |= ASE_DSP | ASE_DSPR2; | |
8b082fb1 TS |
15014 | break; |
15015 | ||
846ef2d0 | 15016 | case OPTION_NO_DSP: |
8b082fb1 | 15017 | case OPTION_NO_DSPR2: |
846ef2d0 RS |
15018 | mips_opts.ase &= ~(ASE_DSP | ASE_DSPR2); |
15019 | file_ase_explicit |= ASE_DSP | ASE_DSPR2; | |
74cd071d CF |
15020 | break; |
15021 | ||
7f3c4072 | 15022 | case OPTION_EVA: |
846ef2d0 RS |
15023 | mips_opts.ase |= ASE_EVA; |
15024 | file_ase_explicit |= ASE_EVA; | |
7f3c4072 CM |
15025 | break; |
15026 | ||
15027 | case OPTION_NO_EVA: | |
846ef2d0 RS |
15028 | mips_opts.ase &= ~ASE_EVA; |
15029 | file_ase_explicit |= ASE_EVA; | |
7f3c4072 CM |
15030 | break; |
15031 | ||
ef2e4d86 | 15032 | case OPTION_MT: |
846ef2d0 RS |
15033 | mips_opts.ase |= ASE_MT; |
15034 | file_ase_explicit |= ASE_MT; | |
ef2e4d86 CF |
15035 | break; |
15036 | ||
15037 | case OPTION_NO_MT: | |
846ef2d0 RS |
15038 | mips_opts.ase &= ~ASE_MT; |
15039 | file_ase_explicit |= ASE_MT; | |
ef2e4d86 CF |
15040 | break; |
15041 | ||
dec0624d | 15042 | case OPTION_MCU: |
846ef2d0 RS |
15043 | mips_opts.ase |= ASE_MCU; |
15044 | file_ase_explicit |= ASE_MCU; | |
dec0624d MR |
15045 | break; |
15046 | ||
15047 | case OPTION_NO_MCU: | |
846ef2d0 RS |
15048 | mips_opts.ase &= ~ASE_MCU; |
15049 | file_ase_explicit |= ASE_MCU; | |
dec0624d MR |
15050 | break; |
15051 | ||
df58fc94 RS |
15052 | case OPTION_MICROMIPS: |
15053 | if (mips_opts.mips16 == 1) | |
15054 | { | |
15055 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15056 | return 0; | |
15057 | } | |
15058 | mips_opts.micromips = 1; | |
15059 | mips_no_prev_insn (); | |
15060 | break; | |
15061 | ||
15062 | case OPTION_NO_MICROMIPS: | |
15063 | mips_opts.micromips = 0; | |
15064 | mips_no_prev_insn (); | |
15065 | break; | |
15066 | ||
b015e599 | 15067 | case OPTION_VIRT: |
846ef2d0 RS |
15068 | mips_opts.ase |= ASE_VIRT; |
15069 | file_ase_explicit |= ASE_VIRT; | |
b015e599 AP |
15070 | break; |
15071 | ||
15072 | case OPTION_NO_VIRT: | |
846ef2d0 RS |
15073 | mips_opts.ase &= ~ASE_VIRT; |
15074 | file_ase_explicit |= ASE_VIRT; | |
b015e599 AP |
15075 | break; |
15076 | ||
252b5132 | 15077 | case OPTION_MIPS16: |
df58fc94 RS |
15078 | if (mips_opts.micromips == 1) |
15079 | { | |
15080 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15081 | return 0; | |
15082 | } | |
252b5132 | 15083 | mips_opts.mips16 = 1; |
7d10b47d | 15084 | mips_no_prev_insn (); |
252b5132 RH |
15085 | break; |
15086 | ||
15087 | case OPTION_NO_MIPS16: | |
15088 | mips_opts.mips16 = 0; | |
7d10b47d | 15089 | mips_no_prev_insn (); |
252b5132 RH |
15090 | break; |
15091 | ||
1f25f5d3 | 15092 | case OPTION_MIPS3D: |
846ef2d0 RS |
15093 | mips_opts.ase |= ASE_MIPS3D; |
15094 | file_ase_explicit |= ASE_MIPS3D; | |
1f25f5d3 CD |
15095 | break; |
15096 | ||
15097 | case OPTION_NO_MIPS3D: | |
846ef2d0 RS |
15098 | mips_opts.ase &= ~ASE_MIPS3D; |
15099 | file_ase_explicit |= ASE_MIPS3D; | |
1f25f5d3 CD |
15100 | break; |
15101 | ||
e16bfa71 | 15102 | case OPTION_SMARTMIPS: |
846ef2d0 RS |
15103 | mips_opts.ase |= ASE_SMARTMIPS; |
15104 | file_ase_explicit |= ASE_SMARTMIPS; | |
e16bfa71 TS |
15105 | break; |
15106 | ||
15107 | case OPTION_NO_SMARTMIPS: | |
846ef2d0 RS |
15108 | mips_opts.ase &= ~ASE_SMARTMIPS; |
15109 | file_ase_explicit |= ASE_SMARTMIPS; | |
e16bfa71 TS |
15110 | break; |
15111 | ||
6a32d874 CM |
15112 | case OPTION_FIX_24K: |
15113 | mips_fix_24k = 1; | |
15114 | break; | |
15115 | ||
15116 | case OPTION_NO_FIX_24K: | |
15117 | mips_fix_24k = 0; | |
15118 | break; | |
15119 | ||
c67a084a NC |
15120 | case OPTION_FIX_LOONGSON2F_JUMP: |
15121 | mips_fix_loongson2f_jump = TRUE; | |
15122 | break; | |
15123 | ||
15124 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15125 | mips_fix_loongson2f_jump = FALSE; | |
15126 | break; | |
15127 | ||
15128 | case OPTION_FIX_LOONGSON2F_NOP: | |
15129 | mips_fix_loongson2f_nop = TRUE; | |
15130 | break; | |
15131 | ||
15132 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15133 | mips_fix_loongson2f_nop = FALSE; | |
15134 | break; | |
15135 | ||
d766e8ec RS |
15136 | case OPTION_FIX_VR4120: |
15137 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15138 | break; |
15139 | ||
d766e8ec RS |
15140 | case OPTION_NO_FIX_VR4120: |
15141 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15142 | break; |
15143 | ||
7d8e00cf RS |
15144 | case OPTION_FIX_VR4130: |
15145 | mips_fix_vr4130 = 1; | |
15146 | break; | |
15147 | ||
15148 | case OPTION_NO_FIX_VR4130: | |
15149 | mips_fix_vr4130 = 0; | |
15150 | break; | |
15151 | ||
d954098f DD |
15152 | case OPTION_FIX_CN63XXP1: |
15153 | mips_fix_cn63xxp1 = TRUE; | |
15154 | break; | |
15155 | ||
15156 | case OPTION_NO_FIX_CN63XXP1: | |
15157 | mips_fix_cn63xxp1 = FALSE; | |
15158 | break; | |
15159 | ||
4a6a3df4 AO |
15160 | case OPTION_RELAX_BRANCH: |
15161 | mips_relax_branch = 1; | |
15162 | break; | |
15163 | ||
15164 | case OPTION_NO_RELAX_BRANCH: | |
15165 | mips_relax_branch = 0; | |
15166 | break; | |
15167 | ||
aa6975fb ILT |
15168 | case OPTION_MSHARED: |
15169 | mips_in_shared = TRUE; | |
15170 | break; | |
15171 | ||
15172 | case OPTION_MNO_SHARED: | |
15173 | mips_in_shared = FALSE; | |
15174 | break; | |
15175 | ||
aed1a261 RS |
15176 | case OPTION_MSYM32: |
15177 | mips_opts.sym32 = TRUE; | |
15178 | break; | |
15179 | ||
15180 | case OPTION_MNO_SYM32: | |
15181 | mips_opts.sym32 = FALSE; | |
15182 | break; | |
15183 | ||
0f074f60 | 15184 | #ifdef OBJ_ELF |
252b5132 RH |
15185 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15186 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15187 | intended to be compatible with Irix 5. */ | |
15188 | case OPTION_CALL_SHARED: | |
f43abd2b | 15189 | if (!IS_ELF) |
252b5132 RH |
15190 | { |
15191 | as_bad (_("-call_shared is supported only for ELF format")); | |
15192 | return 0; | |
15193 | } | |
15194 | mips_pic = SVR4_PIC; | |
143d77c5 | 15195 | mips_abicalls = TRUE; |
252b5132 RH |
15196 | break; |
15197 | ||
861fb55a DJ |
15198 | case OPTION_CALL_NONPIC: |
15199 | if (!IS_ELF) | |
15200 | { | |
15201 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
15202 | return 0; | |
15203 | } | |
15204 | mips_pic = NO_PIC; | |
15205 | mips_abicalls = TRUE; | |
15206 | break; | |
15207 | ||
252b5132 | 15208 | case OPTION_NON_SHARED: |
f43abd2b | 15209 | if (!IS_ELF) |
252b5132 RH |
15210 | { |
15211 | as_bad (_("-non_shared is supported only for ELF format")); | |
15212 | return 0; | |
15213 | } | |
15214 | mips_pic = NO_PIC; | |
143d77c5 | 15215 | mips_abicalls = FALSE; |
252b5132 RH |
15216 | break; |
15217 | ||
44075ae2 TS |
15218 | /* The -xgot option tells the assembler to use 32 bit offsets |
15219 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15220 | compatibility. */ |
15221 | case OPTION_XGOT: | |
15222 | mips_big_got = 1; | |
15223 | break; | |
0f074f60 | 15224 | #endif /* OBJ_ELF */ |
252b5132 RH |
15225 | |
15226 | case 'G': | |
6caf9ef4 TS |
15227 | g_switch_value = atoi (arg); |
15228 | g_switch_seen = 1; | |
252b5132 RH |
15229 | break; |
15230 | ||
34ba82a8 TS |
15231 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15232 | and -mabi=64. */ | |
252b5132 | 15233 | case OPTION_32: |
23fce1e3 NC |
15234 | if (IS_ELF) |
15235 | mips_abi = O32_ABI; | |
15236 | /* We silently ignore -32 for non-ELF targets. This greatly | |
15237 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
15238 | break; |
15239 | ||
23fce1e3 | 15240 | #ifdef OBJ_ELF |
e013f690 | 15241 | case OPTION_N32: |
f43abd2b | 15242 | if (!IS_ELF) |
34ba82a8 TS |
15243 | { |
15244 | as_bad (_("-n32 is supported for ELF format only")); | |
15245 | return 0; | |
15246 | } | |
316f5878 | 15247 | mips_abi = N32_ABI; |
e013f690 | 15248 | break; |
252b5132 | 15249 | |
e013f690 | 15250 | case OPTION_64: |
f43abd2b | 15251 | if (!IS_ELF) |
34ba82a8 TS |
15252 | { |
15253 | as_bad (_("-64 is supported for ELF format only")); | |
15254 | return 0; | |
15255 | } | |
316f5878 | 15256 | mips_abi = N64_ABI; |
f43abd2b | 15257 | if (!support_64bit_objects()) |
e013f690 | 15258 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 15259 | break; |
ae948b86 | 15260 | #endif /* OBJ_ELF */ |
252b5132 | 15261 | |
c97ef257 | 15262 | case OPTION_GP32: |
a325df1d | 15263 | file_mips_gp32 = 1; |
c97ef257 AH |
15264 | break; |
15265 | ||
15266 | case OPTION_GP64: | |
a325df1d | 15267 | file_mips_gp32 = 0; |
c97ef257 | 15268 | break; |
252b5132 | 15269 | |
ca4e0257 | 15270 | case OPTION_FP32: |
a325df1d | 15271 | file_mips_fp32 = 1; |
316f5878 RS |
15272 | break; |
15273 | ||
15274 | case OPTION_FP64: | |
15275 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15276 | break; |
15277 | ||
037b32b9 AN |
15278 | case OPTION_SINGLE_FLOAT: |
15279 | file_mips_single_float = 1; | |
15280 | break; | |
15281 | ||
15282 | case OPTION_DOUBLE_FLOAT: | |
15283 | file_mips_single_float = 0; | |
15284 | break; | |
15285 | ||
15286 | case OPTION_SOFT_FLOAT: | |
15287 | file_mips_soft_float = 1; | |
15288 | break; | |
15289 | ||
15290 | case OPTION_HARD_FLOAT: | |
15291 | file_mips_soft_float = 0; | |
15292 | break; | |
15293 | ||
ae948b86 | 15294 | #ifdef OBJ_ELF |
252b5132 | 15295 | case OPTION_MABI: |
f43abd2b | 15296 | if (!IS_ELF) |
34ba82a8 TS |
15297 | { |
15298 | as_bad (_("-mabi is supported for ELF format only")); | |
15299 | return 0; | |
15300 | } | |
e013f690 | 15301 | if (strcmp (arg, "32") == 0) |
316f5878 | 15302 | mips_abi = O32_ABI; |
e013f690 | 15303 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15304 | mips_abi = O64_ABI; |
e013f690 | 15305 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15306 | mips_abi = N32_ABI; |
e013f690 TS |
15307 | else if (strcmp (arg, "64") == 0) |
15308 | { | |
316f5878 | 15309 | mips_abi = N64_ABI; |
e013f690 TS |
15310 | if (! support_64bit_objects()) |
15311 | as_fatal (_("No compiled in support for 64 bit object file " | |
15312 | "format")); | |
15313 | } | |
15314 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15315 | mips_abi = EABI_ABI; |
e013f690 | 15316 | else |
da0e507f TS |
15317 | { |
15318 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15319 | return 0; | |
15320 | } | |
252b5132 | 15321 | break; |
e013f690 | 15322 | #endif /* OBJ_ELF */ |
252b5132 | 15323 | |
6b76fefe | 15324 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15325 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15326 | break; |
15327 | ||
9ee72ff1 | 15328 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15329 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15330 | break; |
15331 | ||
ecb4347a DJ |
15332 | #ifdef OBJ_ELF |
15333 | case OPTION_MDEBUG: | |
b34976b6 | 15334 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15335 | break; |
15336 | ||
15337 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15338 | mips_flag_mdebug = FALSE; |
ecb4347a | 15339 | break; |
dcd410fe RO |
15340 | |
15341 | case OPTION_PDR: | |
15342 | mips_flag_pdr = TRUE; | |
15343 | break; | |
15344 | ||
15345 | case OPTION_NO_PDR: | |
15346 | mips_flag_pdr = FALSE; | |
15347 | break; | |
0a44bf69 RS |
15348 | |
15349 | case OPTION_MVXWORKS_PIC: | |
15350 | mips_pic = VXWORKS_PIC; | |
15351 | break; | |
ecb4347a DJ |
15352 | #endif /* OBJ_ELF */ |
15353 | ||
252b5132 RH |
15354 | default: |
15355 | return 0; | |
15356 | } | |
15357 | ||
c67a084a NC |
15358 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15359 | ||
252b5132 RH |
15360 | return 1; |
15361 | } | |
316f5878 RS |
15362 | \f |
15363 | /* Set up globals to generate code for the ISA or processor | |
15364 | described by INFO. */ | |
252b5132 | 15365 | |
252b5132 | 15366 | static void |
17a2f251 | 15367 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15368 | { |
316f5878 | 15369 | if (info != 0) |
252b5132 | 15370 | { |
fef14a42 TS |
15371 | file_mips_arch = info->cpu; |
15372 | mips_opts.arch = info->cpu; | |
316f5878 | 15373 | mips_opts.isa = info->isa; |
252b5132 | 15374 | } |
252b5132 RH |
15375 | } |
15376 | ||
252b5132 | 15377 | |
316f5878 | 15378 | /* Likewise for tuning. */ |
252b5132 | 15379 | |
316f5878 | 15380 | static void |
17a2f251 | 15381 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15382 | { |
15383 | if (info != 0) | |
fef14a42 | 15384 | mips_tune = info->cpu; |
316f5878 | 15385 | } |
80cc45a5 | 15386 | |
34ba82a8 | 15387 | |
252b5132 | 15388 | void |
17a2f251 | 15389 | mips_after_parse_args (void) |
e9670677 | 15390 | { |
fef14a42 TS |
15391 | const struct mips_cpu_info *arch_info = 0; |
15392 | const struct mips_cpu_info *tune_info = 0; | |
15393 | ||
e9670677 | 15394 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15395 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15396 | { |
6caf9ef4 | 15397 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15398 | as_bad (_("-G not supported in this configuration.")); |
15399 | g_switch_value = 0; | |
15400 | } | |
15401 | ||
cac012d6 AO |
15402 | if (mips_abi == NO_ABI) |
15403 | mips_abi = MIPS_DEFAULT_ABI; | |
15404 | ||
22923709 RS |
15405 | /* The following code determines the architecture and register size. |
15406 | Similar code was added to GCC 3.3 (see override_options() in | |
15407 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15408 | as much as possible. */ | |
e9670677 | 15409 | |
316f5878 | 15410 | if (mips_arch_string != 0) |
fef14a42 | 15411 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15412 | |
316f5878 | 15413 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15414 | { |
316f5878 | 15415 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15416 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15417 | the -march selection (if any). */ |
fef14a42 | 15418 | if (arch_info != 0) |
e9670677 | 15419 | { |
316f5878 RS |
15420 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15421 | There's no harm in specifying both as long as the ISA levels | |
15422 | are the same. */ | |
fef14a42 | 15423 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15424 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15425 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15426 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15427 | } |
316f5878 | 15428 | else |
fef14a42 | 15429 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15430 | } |
15431 | ||
fef14a42 | 15432 | if (arch_info == 0) |
95bfe26e MF |
15433 | { |
15434 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15435 | gas_assert (arch_info); | |
15436 | } | |
e9670677 | 15437 | |
fef14a42 | 15438 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15439 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15440 | arch_info->name); |
15441 | ||
15442 | mips_set_architecture (arch_info); | |
15443 | ||
15444 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15445 | if (mips_tune_string != 0) | |
15446 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15447 | |
fef14a42 TS |
15448 | if (tune_info == 0) |
15449 | mips_set_tune (arch_info); | |
15450 | else | |
15451 | mips_set_tune (tune_info); | |
e9670677 | 15452 | |
316f5878 | 15453 | if (file_mips_gp32 >= 0) |
e9670677 | 15454 | { |
316f5878 RS |
15455 | /* The user specified the size of the integer registers. Make sure |
15456 | it agrees with the ABI and ISA. */ | |
15457 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15458 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15459 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15460 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15461 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15462 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15463 | } |
15464 | else | |
15465 | { | |
316f5878 RS |
15466 | /* Infer the integer register size from the ABI and processor. |
15467 | Restrict ourselves to 32-bit registers if that's all the | |
15468 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15469 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15470 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15471 | } |
15472 | ||
ad3fea08 TS |
15473 | switch (file_mips_fp32) |
15474 | { | |
15475 | default: | |
15476 | case -1: | |
15477 | /* No user specified float register size. | |
15478 | ??? GAS treats single-float processors as though they had 64-bit | |
15479 | float registers (although it complains when double-precision | |
15480 | instructions are used). As things stand, saying they have 32-bit | |
15481 | registers would lead to spurious "register must be even" messages. | |
15482 | So here we assume float registers are never smaller than the | |
15483 | integer ones. */ | |
15484 | if (file_mips_gp32 == 0) | |
15485 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15486 | file_mips_fp32 = 0; | |
846ef2d0 | 15487 | else if ((mips_opts.ase & (ASE_MIPS3D | ASE_MDMX)) |
ad3fea08 TS |
15488 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
15489 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15490 | file_mips_fp32 = 0; | |
15491 | else | |
15492 | /* 32-bit float registers. */ | |
15493 | file_mips_fp32 = 1; | |
15494 | break; | |
15495 | ||
15496 | /* The user specified the size of the float registers. Check if it | |
15497 | agrees with the ABI and ISA. */ | |
15498 | case 0: | |
15499 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15500 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15501 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15502 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15503 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15504 | break; | |
15505 | case 1: | |
15506 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15507 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15508 | break; | |
15509 | } | |
e9670677 | 15510 | |
316f5878 | 15511 | /* End of GCC-shared inference code. */ |
e9670677 | 15512 | |
17a2f251 TS |
15513 | /* This flag is set when we have a 64-bit capable CPU but use only |
15514 | 32-bit wide registers. Note that EABI does not use it. */ | |
15515 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15516 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15517 | || mips_abi == O32_ABI)) | |
316f5878 | 15518 | mips_32bitmode = 1; |
e9670677 MR |
15519 | |
15520 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15521 | as_bad (_("trap exception not supported at ISA 1")); | |
15522 | ||
e9670677 MR |
15523 | /* If the selected architecture includes support for ASEs, enable |
15524 | generation of code for them. */ | |
a4672219 | 15525 | if (mips_opts.mips16 == -1) |
fef14a42 | 15526 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15527 | if (mips_opts.micromips == -1) |
15528 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
846ef2d0 RS |
15529 | |
15530 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
15531 | ASEs from being selected implicitly. */ | |
15532 | if (file_mips_fp32 == 1) | |
15533 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; | |
15534 | ||
15535 | /* If the user didn't explicitly select or deselect a particular ASE, | |
15536 | use the default setting for the CPU. */ | |
15537 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
15538 | ||
15539 | if ((mips_opts.ase & ASE_MIPS3D) && file_mips_fp32 == 1) | |
ad3fea08 TS |
15540 | as_bad (_("-mfp32 used with -mips3d")); |
15541 | ||
846ef2d0 | 15542 | if ((mips_opts.ase & ASE_MDMX) && file_mips_fp32 == 1) |
ad3fea08 TS |
15543 | as_bad (_("-mfp32 used with -mdmx")); |
15544 | ||
846ef2d0 | 15545 | if ((mips_opts.ase & ASE_SMARTMIPS) && !ISA_SUPPORTS_SMARTMIPS) |
20203fb9 NC |
15546 | as_warn (_("%s ISA does not support SmartMIPS"), |
15547 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15548 | |
846ef2d0 | 15549 | if ((mips_opts.ase & ASE_DSP) && !ISA_SUPPORTS_DSP_ASE) |
20203fb9 NC |
15550 | as_warn (_("%s ISA does not support DSP ASE"), |
15551 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15552 | |
846ef2d0 | 15553 | if ((mips_opts.ase & ASE_DSPR2) && !ISA_SUPPORTS_DSPR2_ASE) |
20203fb9 NC |
15554 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15555 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15556 | |
846ef2d0 | 15557 | if ((mips_opts.ase & ASE_EVA) && !ISA_SUPPORTS_EVA_ASE) |
7f3c4072 CM |
15558 | as_warn (_("%s ISA does not support EVA ASE"), |
15559 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15560 | ||
846ef2d0 | 15561 | if ((mips_opts.ase & ASE_MT) && !ISA_SUPPORTS_MT_ASE) |
20203fb9 NC |
15562 | as_warn (_("%s ISA does not support MT ASE"), |
15563 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15564 | |
846ef2d0 RS |
15565 | if ((mips_opts.ase & ASE_MCU) && !ISA_SUPPORTS_MCU_ASE) |
15566 | as_warn (_("%s ISA does not support MCU ASE"), | |
15567 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
dec0624d | 15568 | |
846ef2d0 | 15569 | if ((mips_opts.ase & ASE_VIRT) && !ISA_SUPPORTS_VIRT_ASE) |
b015e599 AP |
15570 | as_warn (_("%s ISA does not support Virtualization ASE"), |
15571 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15572 | ||
e9670677 | 15573 | file_mips_isa = mips_opts.isa; |
846ef2d0 | 15574 | file_ase = mips_opts.ase; |
e9670677 MR |
15575 | mips_opts.gp32 = file_mips_gp32; |
15576 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15577 | mips_opts.soft_float = file_mips_soft_float; |
15578 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15579 | |
ecb4347a DJ |
15580 | if (mips_flag_mdebug < 0) |
15581 | { | |
15582 | #ifdef OBJ_MAYBE_ECOFF | |
15583 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15584 | mips_flag_mdebug = 1; | |
15585 | else | |
15586 | #endif /* OBJ_MAYBE_ECOFF */ | |
15587 | mips_flag_mdebug = 0; | |
15588 | } | |
e9670677 MR |
15589 | } |
15590 | \f | |
15591 | void | |
17a2f251 | 15592 | mips_init_after_args (void) |
252b5132 RH |
15593 | { |
15594 | /* initialize opcodes */ | |
15595 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15596 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15597 | } |
15598 | ||
15599 | long | |
17a2f251 | 15600 | md_pcrel_from (fixS *fixP) |
252b5132 | 15601 | { |
a7ebbfdf TS |
15602 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15603 | switch (fixP->fx_r_type) | |
15604 | { | |
df58fc94 RS |
15605 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15606 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15607 | /* Return the address of the delay slot. */ | |
15608 | return addr + 2; | |
15609 | ||
15610 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15611 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15612 | case BFD_RELOC_16_PCREL_S2: |
15613 | case BFD_RELOC_MIPS_JMP: | |
15614 | /* Return the address of the delay slot. */ | |
15615 | return addr + 4; | |
df58fc94 | 15616 | |
b47468a6 CM |
15617 | case BFD_RELOC_32_PCREL: |
15618 | return addr; | |
15619 | ||
a7ebbfdf | 15620 | default: |
58ea3d6a | 15621 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15622 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15623 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15624 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15625 | return addr; |
15626 | } | |
252b5132 RH |
15627 | } |
15628 | ||
252b5132 RH |
15629 | /* This is called before the symbol table is processed. In order to |
15630 | work with gcc when using mips-tfile, we must keep all local labels. | |
15631 | However, in other cases, we want to discard them. If we were | |
15632 | called with -g, but we didn't see any debugging information, it may | |
15633 | mean that gcc is smuggling debugging information through to | |
15634 | mips-tfile, in which case we must generate all local labels. */ | |
15635 | ||
15636 | void | |
17a2f251 | 15637 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15638 | { |
15639 | #ifndef NO_ECOFF_DEBUGGING | |
15640 | if (ECOFF_DEBUGGING | |
15641 | && mips_debug != 0 | |
15642 | && ! ecoff_debugging_seen) | |
15643 | flag_keep_locals = 1; | |
15644 | #endif | |
15645 | } | |
15646 | ||
3b91255e | 15647 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15648 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15649 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15650 | relocation operators. | |
15651 | ||
15652 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15653 | expression if: | |
15654 | ||
15655 | (a) it refers to the same symbol; and | |
15656 | (b) the offset applied in the %lo() expression is no lower than | |
15657 | the offset applied in the %got() or %hi(). | |
15658 | ||
15659 | (b) allows us to cope with code like: | |
15660 | ||
15661 | lui $4,%hi(foo) | |
15662 | lh $4,%lo(foo+2)($4) | |
15663 | ||
15664 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15665 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15666 | the high 16 bits. | |
15667 | ||
15668 | When several %lo()s match a particular %got() or %hi(), we use the | |
15669 | following rules to distinguish them: | |
15670 | ||
15671 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15672 | higher offsets. | |
15673 | ||
15674 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15675 | that already have a matching %got() or %hi(). | |
15676 | ||
15677 | (3) later %lo()s are better than earlier %lo()s. | |
15678 | ||
15679 | These rules are applied in order. | |
15680 | ||
15681 | (1) means, among other things, that %lo()s with identical offsets are | |
15682 | chosen if they exist. | |
15683 | ||
15684 | (2) means that we won't associate several high-part relocations with | |
15685 | the same low-part relocation unless there's no alternative. Having | |
15686 | several high parts for the same low part is a GNU extension; this rule | |
15687 | allows careful users to avoid it. | |
15688 | ||
15689 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15690 | with the last high-part relocation being at the front of the list. | |
15691 | It therefore makes sense to choose the last matching low-part | |
15692 | relocation, all other things being equal. It's also easier | |
15693 | to code that way. */ | |
252b5132 RH |
15694 | |
15695 | void | |
17a2f251 | 15696 | mips_frob_file (void) |
252b5132 RH |
15697 | { |
15698 | struct mips_hi_fixup *l; | |
35903be0 | 15699 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15700 | |
15701 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15702 | { | |
15703 | segment_info_type *seginfo; | |
3b91255e RS |
15704 | bfd_boolean matched_lo_p; |
15705 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15706 | |
9c2799c2 | 15707 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15708 | |
5919d012 | 15709 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15710 | there isn't supposed to be a matching LO. Ignore %gots against |
15711 | constants; we'll report an error for those later. */ | |
738e5348 | 15712 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15713 | && !(l->fixp->fx_addsy |
15714 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15715 | continue; |
15716 | ||
15717 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15718 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15719 | continue; |
15720 | ||
252b5132 | 15721 | seginfo = seg_info (l->seg); |
252b5132 | 15722 | |
3b91255e RS |
15723 | /* Set HI_POS to the position of this relocation in the chain. |
15724 | Set LO_POS to the position of the chosen low-part relocation. | |
15725 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15726 | relocation that matches an immediately-preceding high-part | |
15727 | relocation. */ | |
15728 | hi_pos = NULL; | |
15729 | lo_pos = NULL; | |
15730 | matched_lo_p = FALSE; | |
738e5348 | 15731 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15732 | |
3b91255e RS |
15733 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15734 | { | |
15735 | if (*pos == l->fixp) | |
15736 | hi_pos = pos; | |
15737 | ||
35903be0 | 15738 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15739 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15740 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15741 | && (lo_pos == NULL | |
15742 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15743 | || (!matched_lo_p | |
15744 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15745 | lo_pos = pos; | |
15746 | ||
15747 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15748 | && fixup_has_matching_lo_p (*pos)); | |
15749 | } | |
15750 | ||
15751 | /* If we found a match, remove the high-part relocation from its | |
15752 | current position and insert it before the low-part relocation. | |
15753 | Make the offsets match so that fixup_has_matching_lo_p() | |
15754 | will return true. | |
15755 | ||
15756 | We don't warn about unmatched high-part relocations since some | |
15757 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15758 | instructions. */ | |
15759 | if (lo_pos != NULL) | |
15760 | { | |
15761 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15762 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15763 | { |
3b91255e RS |
15764 | *hi_pos = l->fixp->fx_next; |
15765 | l->fixp->fx_next = *lo_pos; | |
15766 | *lo_pos = l->fixp; | |
252b5132 | 15767 | } |
252b5132 RH |
15768 | } |
15769 | } | |
15770 | } | |
15771 | ||
252b5132 | 15772 | int |
17a2f251 | 15773 | mips_force_relocation (fixS *fixp) |
252b5132 | 15774 | { |
ae6063d4 | 15775 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15776 | return 1; |
15777 | ||
df58fc94 RS |
15778 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15779 | so that the linker relaxation can update targets. */ | |
15780 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15781 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15782 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15783 | return 1; | |
15784 | ||
3e722fb5 | 15785 | return 0; |
252b5132 RH |
15786 | } |
15787 | ||
b886a2ab RS |
15788 | /* Read the instruction associated with RELOC from BUF. */ |
15789 | ||
15790 | static unsigned int | |
15791 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15792 | { | |
15793 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15794 | return read_compressed_insn (buf, 4); | |
15795 | else | |
15796 | return read_insn (buf); | |
15797 | } | |
15798 | ||
15799 | /* Write instruction INSN to BUF, given that it has been relocated | |
15800 | by RELOC. */ | |
15801 | ||
15802 | static void | |
15803 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15804 | unsigned long insn) | |
15805 | { | |
15806 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15807 | write_compressed_insn (buf, insn, 4); | |
15808 | else | |
15809 | write_insn (buf, insn); | |
15810 | } | |
15811 | ||
252b5132 RH |
15812 | /* Apply a fixup to the object file. */ |
15813 | ||
94f592af | 15814 | void |
55cf6793 | 15815 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15816 | { |
4d68580a | 15817 | char *buf; |
b886a2ab | 15818 | unsigned long insn; |
a7ebbfdf | 15819 | reloc_howto_type *howto; |
252b5132 | 15820 | |
a7ebbfdf TS |
15821 | /* We ignore generic BFD relocations we don't know about. */ |
15822 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15823 | if (! howto) | |
15824 | return; | |
65551fa4 | 15825 | |
df58fc94 RS |
15826 | gas_assert (fixP->fx_size == 2 |
15827 | || fixP->fx_size == 4 | |
90ecf173 MR |
15828 | || fixP->fx_r_type == BFD_RELOC_16 |
15829 | || fixP->fx_r_type == BFD_RELOC_64 | |
15830 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15831 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15832 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15833 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15834 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15835 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15836 | |
4d68580a | 15837 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15838 | |
df58fc94 RS |
15839 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15840 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15841 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15842 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15843 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15844 | |
15845 | /* Don't treat parts of a composite relocation as done. There are two | |
15846 | reasons for this: | |
15847 | ||
15848 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15849 | should nevertheless be emitted if the first part is. | |
15850 | ||
15851 | (2) In normal usage, composite relocations are never assembly-time | |
15852 | constants. The easiest way of dealing with the pathological | |
15853 | exceptions is to generate a relocation against STN_UNDEF and | |
15854 | leave everything up to the linker. */ | |
3994f87e | 15855 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15856 | fixP->fx_done = 1; |
15857 | ||
15858 | switch (fixP->fx_r_type) | |
15859 | { | |
3f98094e DJ |
15860 | case BFD_RELOC_MIPS_TLS_GD: |
15861 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15862 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15863 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15864 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15865 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15866 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15867 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15868 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15869 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15870 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15871 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15872 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15873 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15874 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15875 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15876 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15877 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15878 | case BFD_RELOC_MIPS16_TLS_GD: |
15879 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15880 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15881 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15882 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15883 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15884 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15885 | if (!fixP->fx_addsy) |
15886 | { | |
15887 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15888 | _("TLS relocation against a constant")); | |
15889 | break; | |
15890 | } | |
3f98094e DJ |
15891 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15892 | /* fall through */ | |
15893 | ||
252b5132 | 15894 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15895 | case BFD_RELOC_MIPS_SHIFT5: |
15896 | case BFD_RELOC_MIPS_SHIFT6: | |
15897 | case BFD_RELOC_MIPS_GOT_DISP: | |
15898 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15899 | case BFD_RELOC_MIPS_GOT_OFST: | |
15900 | case BFD_RELOC_MIPS_SUB: | |
15901 | case BFD_RELOC_MIPS_INSERT_A: | |
15902 | case BFD_RELOC_MIPS_INSERT_B: | |
15903 | case BFD_RELOC_MIPS_DELETE: | |
15904 | case BFD_RELOC_MIPS_HIGHEST: | |
15905 | case BFD_RELOC_MIPS_HIGHER: | |
15906 | case BFD_RELOC_MIPS_SCN_DISP: | |
15907 | case BFD_RELOC_MIPS_REL16: | |
15908 | case BFD_RELOC_MIPS_RELGOT: | |
15909 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15910 | case BFD_RELOC_HI16: |
15911 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15912 | case BFD_RELOC_LO16: |
cdf6fd85 | 15913 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15914 | case BFD_RELOC_MIPS_LITERAL: |
15915 | case BFD_RELOC_MIPS_CALL16: | |
15916 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15917 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15918 | case BFD_RELOC_MIPS_GOT_HI16: |
15919 | case BFD_RELOC_MIPS_GOT_LO16: | |
15920 | case BFD_RELOC_MIPS_CALL_HI16: | |
15921 | case BFD_RELOC_MIPS_CALL_LO16: | |
15922 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15923 | case BFD_RELOC_MIPS16_GOT16: |
15924 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15925 | case BFD_RELOC_MIPS16_HI16: |
15926 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15927 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15928 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15929 | case BFD_RELOC_MICROMIPS_JMP: |
15930 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15931 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15932 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15933 | case BFD_RELOC_MICROMIPS_SUB: | |
15934 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15935 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15936 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15937 | case BFD_RELOC_MICROMIPS_JALR: | |
15938 | case BFD_RELOC_MICROMIPS_HI16: | |
15939 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15940 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15941 | case BFD_RELOC_MICROMIPS_GPREL16: |
15942 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15943 | case BFD_RELOC_MICROMIPS_CALL16: | |
15944 | case BFD_RELOC_MICROMIPS_GOT16: | |
15945 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15946 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15947 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15948 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15949 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15950 | if (fixP->fx_done) |
15951 | { | |
15952 | offsetT value; | |
15953 | ||
15954 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15955 | { | |
15956 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15957 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15958 | insn |= mips16_immed_extend (value, 16); | |
15959 | else | |
15960 | insn |= (value & 0xffff); | |
15961 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15962 | } | |
15963 | else | |
15964 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15965 | _("Unsupported constant in relocation")); | |
15966 | } | |
252b5132 RH |
15967 | break; |
15968 | ||
252b5132 RH |
15969 | case BFD_RELOC_64: |
15970 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15971 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15972 | if (fixP->fx_done) |
252b5132 RH |
15973 | { |
15974 | if (8 <= sizeof (valueT)) | |
4d68580a | 15975 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15976 | else |
15977 | { | |
a7ebbfdf | 15978 | valueT hiv; |
252b5132 | 15979 | |
a7ebbfdf | 15980 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15981 | hiv = 0xffffffff; |
15982 | else | |
15983 | hiv = 0; | |
4d68580a RS |
15984 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15985 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15986 | } |
15987 | } | |
15988 | break; | |
15989 | ||
056350c6 | 15990 | case BFD_RELOC_RVA: |
252b5132 | 15991 | case BFD_RELOC_32: |
b47468a6 | 15992 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15993 | case BFD_RELOC_16: |
15994 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15995 | value now. This can happen if we have a .word which is not |
15996 | resolved when it appears but is later defined. */ | |
252b5132 | 15997 | if (fixP->fx_done) |
4d68580a | 15998 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15999 | break; |
16000 | ||
252b5132 | 16001 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 16002 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 16003 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 16004 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 16005 | |
54f4ddb3 TS |
16006 | /* We need to save the bits in the instruction since fixup_segment() |
16007 | might be deleting the relocation entry (i.e., a branch within | |
16008 | the current segment). */ | |
a7ebbfdf | 16009 | if (! fixP->fx_done) |
bb2d6cd7 | 16010 | break; |
252b5132 | 16011 | |
54f4ddb3 | 16012 | /* Update old instruction data. */ |
4d68580a | 16013 | insn = read_insn (buf); |
252b5132 | 16014 | |
a7ebbfdf TS |
16015 | if (*valP + 0x20000 <= 0x3ffff) |
16016 | { | |
16017 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16018 | write_insn (buf, insn); |
a7ebbfdf TS |
16019 | } |
16020 | else if (mips_pic == NO_PIC | |
16021 | && fixP->fx_done | |
16022 | && fixP->fx_frag->fr_address >= text_section->vma | |
16023 | && (fixP->fx_frag->fr_address | |
587aac4e | 16024 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
16025 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16026 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16027 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16028 | { |
16029 | /* The branch offset is too large. If this is an | |
16030 | unconditional branch, and we are not generating PIC code, | |
16031 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16032 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16033 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16034 | else |
a7ebbfdf TS |
16035 | insn = 0x08000000; /* j */ |
16036 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16037 | fixP->fx_done = 0; | |
16038 | fixP->fx_addsy = section_symbol (text_section); | |
16039 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16040 | write_insn (buf, insn); |
a7ebbfdf TS |
16041 | } |
16042 | else | |
16043 | { | |
16044 | /* If we got here, we have branch-relaxation disabled, | |
16045 | and there's nothing we can do to fix this instruction | |
16046 | without turning it into a longer sequence. */ | |
16047 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16048 | _("Branch out of range")); | |
252b5132 | 16049 | } |
252b5132 RH |
16050 | break; |
16051 | ||
df58fc94 RS |
16052 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16053 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16054 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
16055 | /* We adjust the offset back to even. */ | |
16056 | if ((*valP & 0x1) != 0) | |
16057 | --(*valP); | |
16058 | ||
16059 | if (! fixP->fx_done) | |
16060 | break; | |
16061 | ||
16062 | /* Should never visit here, because we keep the relocation. */ | |
16063 | abort (); | |
16064 | break; | |
16065 | ||
252b5132 RH |
16066 | case BFD_RELOC_VTABLE_INHERIT: |
16067 | fixP->fx_done = 0; | |
16068 | if (fixP->fx_addsy | |
16069 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16070 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16071 | S_SET_WEAK (fixP->fx_addsy); | |
16072 | break; | |
16073 | ||
16074 | case BFD_RELOC_VTABLE_ENTRY: | |
16075 | fixP->fx_done = 0; | |
16076 | break; | |
16077 | ||
16078 | default: | |
b37df7c4 | 16079 | abort (); |
252b5132 | 16080 | } |
a7ebbfdf TS |
16081 | |
16082 | /* Remember value for tc_gen_reloc. */ | |
16083 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16084 | } |
16085 | ||
252b5132 | 16086 | static symbolS * |
17a2f251 | 16087 | get_symbol (void) |
252b5132 RH |
16088 | { |
16089 | int c; | |
16090 | char *name; | |
16091 | symbolS *p; | |
16092 | ||
16093 | name = input_line_pointer; | |
16094 | c = get_symbol_end (); | |
16095 | p = (symbolS *) symbol_find_or_make (name); | |
16096 | *input_line_pointer = c; | |
16097 | return p; | |
16098 | } | |
16099 | ||
742a56fe RS |
16100 | /* Align the current frag to a given power of two. If a particular |
16101 | fill byte should be used, FILL points to an integer that contains | |
16102 | that byte, otherwise FILL is null. | |
16103 | ||
462427c4 RS |
16104 | This function used to have the comment: |
16105 | ||
16106 | The MIPS assembler also automatically adjusts any preceding label. | |
16107 | ||
16108 | The implementation therefore applied the adjustment to a maximum of | |
16109 | one label. However, other label adjustments are applied to batches | |
16110 | of labels, and adjusting just one caused problems when new labels | |
16111 | were added for the sake of debugging or unwind information. | |
16112 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16113 | |
16114 | static void | |
462427c4 | 16115 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16116 | { |
7d10b47d | 16117 | mips_emit_delays (); |
df58fc94 | 16118 | mips_record_compressed_mode (); |
742a56fe RS |
16119 | if (fill == NULL && subseg_text_p (now_seg)) |
16120 | frag_align_code (to, 0); | |
16121 | else | |
16122 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16123 | record_alignment (now_seg, to); |
462427c4 | 16124 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16125 | } |
16126 | ||
16127 | /* Align to a given power of two. .align 0 turns off the automatic | |
16128 | alignment used by the data creating pseudo-ops. */ | |
16129 | ||
16130 | static void | |
17a2f251 | 16131 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16132 | { |
742a56fe | 16133 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16134 | long max_alignment = 28; |
252b5132 | 16135 | |
54f4ddb3 | 16136 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16137 | to the aligned address. |
54f4ddb3 | 16138 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16139 | a .align pseudo instruction. |
54f4ddb3 | 16140 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16141 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16142 | We don't. */ |
252b5132 RH |
16143 | |
16144 | temp = get_absolute_expression (); | |
16145 | if (temp > max_alignment) | |
16146 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16147 | else if (temp < 0) | |
16148 | { | |
16149 | as_warn (_("Alignment negative: 0 assumed.")); | |
16150 | temp = 0; | |
16151 | } | |
16152 | if (*input_line_pointer == ',') | |
16153 | { | |
f9419b05 | 16154 | ++input_line_pointer; |
742a56fe RS |
16155 | fill_value = get_absolute_expression (); |
16156 | fill_ptr = &fill_value; | |
252b5132 RH |
16157 | } |
16158 | else | |
742a56fe | 16159 | fill_ptr = 0; |
252b5132 RH |
16160 | if (temp) |
16161 | { | |
a8dbcb85 TS |
16162 | segment_info_type *si = seg_info (now_seg); |
16163 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16164 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16165 | auto_align = 1; |
462427c4 | 16166 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16167 | } |
16168 | else | |
16169 | { | |
16170 | auto_align = 0; | |
16171 | } | |
16172 | ||
16173 | demand_empty_rest_of_line (); | |
16174 | } | |
16175 | ||
252b5132 | 16176 | static void |
17a2f251 | 16177 | s_change_sec (int sec) |
252b5132 RH |
16178 | { |
16179 | segT seg; | |
16180 | ||
252b5132 RH |
16181 | #ifdef OBJ_ELF |
16182 | /* The ELF backend needs to know that we are changing sections, so | |
16183 | that .previous works correctly. We could do something like check | |
b6ff326e | 16184 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16185 | as it would not be appropriate to use it in the section changing |
16186 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16187 | This should be cleaner, somehow. */ | |
f43abd2b TS |
16188 | if (IS_ELF) |
16189 | obj_elf_section_change_hook (); | |
252b5132 RH |
16190 | #endif |
16191 | ||
7d10b47d | 16192 | mips_emit_delays (); |
6a32d874 | 16193 | |
252b5132 RH |
16194 | switch (sec) |
16195 | { | |
16196 | case 't': | |
16197 | s_text (0); | |
16198 | break; | |
16199 | case 'd': | |
16200 | s_data (0); | |
16201 | break; | |
16202 | case 'b': | |
16203 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16204 | demand_empty_rest_of_line (); | |
16205 | break; | |
16206 | ||
16207 | case 'r': | |
4d0d148d TS |
16208 | seg = subseg_new (RDATA_SECTION_NAME, |
16209 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 16210 | if (IS_ELF) |
252b5132 | 16211 | { |
4d0d148d TS |
16212 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16213 | | SEC_READONLY | SEC_RELOC | |
16214 | | SEC_DATA)); | |
c41e87e3 | 16215 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16216 | record_alignment (seg, 4); |
252b5132 | 16217 | } |
4d0d148d | 16218 | demand_empty_rest_of_line (); |
252b5132 RH |
16219 | break; |
16220 | ||
16221 | case 's': | |
4d0d148d | 16222 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 16223 | if (IS_ELF) |
252b5132 | 16224 | { |
4d0d148d TS |
16225 | bfd_set_section_flags (stdoutput, seg, |
16226 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 16227 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 16228 | record_alignment (seg, 4); |
252b5132 | 16229 | } |
4d0d148d TS |
16230 | demand_empty_rest_of_line (); |
16231 | break; | |
998b3c36 MR |
16232 | |
16233 | case 'B': | |
16234 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
16235 | if (IS_ELF) | |
16236 | { | |
16237 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
16238 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16239 | record_alignment (seg, 4); | |
16240 | } | |
16241 | demand_empty_rest_of_line (); | |
16242 | break; | |
252b5132 RH |
16243 | } |
16244 | ||
16245 | auto_align = 1; | |
16246 | } | |
b34976b6 | 16247 | |
cca86cc8 | 16248 | void |
17a2f251 | 16249 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16250 | { |
7ed4a06a | 16251 | #ifdef OBJ_ELF |
cca86cc8 SC |
16252 | char *section_name; |
16253 | char c; | |
684022ea | 16254 | char next_c = 0; |
cca86cc8 SC |
16255 | int section_type; |
16256 | int section_flag; | |
16257 | int section_entry_size; | |
16258 | int section_alignment; | |
b34976b6 | 16259 | |
f43abd2b | 16260 | if (!IS_ELF) |
7ed4a06a TS |
16261 | return; |
16262 | ||
cca86cc8 SC |
16263 | section_name = input_line_pointer; |
16264 | c = get_symbol_end (); | |
a816d1ed AO |
16265 | if (c) |
16266 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16267 | |
4cf0dd0d TS |
16268 | /* Do we have .section Name<,"flags">? */ |
16269 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16270 | { |
4cf0dd0d TS |
16271 | /* just after name is now '\0'. */ |
16272 | *input_line_pointer = c; | |
cca86cc8 SC |
16273 | input_line_pointer = section_name; |
16274 | obj_elf_section (ignore); | |
16275 | return; | |
16276 | } | |
16277 | input_line_pointer++; | |
16278 | ||
16279 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16280 | if (c == ',') | |
16281 | section_type = get_absolute_expression (); | |
16282 | else | |
16283 | section_type = 0; | |
16284 | if (*input_line_pointer++ == ',') | |
16285 | section_flag = get_absolute_expression (); | |
16286 | else | |
16287 | section_flag = 0; | |
16288 | if (*input_line_pointer++ == ',') | |
16289 | section_entry_size = get_absolute_expression (); | |
16290 | else | |
16291 | section_entry_size = 0; | |
16292 | if (*input_line_pointer++ == ',') | |
16293 | section_alignment = get_absolute_expression (); | |
16294 | else | |
16295 | section_alignment = 0; | |
87975d2a AM |
16296 | /* FIXME: really ignore? */ |
16297 | (void) section_alignment; | |
cca86cc8 | 16298 | |
a816d1ed AO |
16299 | section_name = xstrdup (section_name); |
16300 | ||
8ab8a5c8 RS |
16301 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16302 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16303 | traditionally had to fall back on the more common @progbits instead. | |
16304 | ||
16305 | There's nothing really harmful in this, since bfd will correct | |
16306 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16307 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16308 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16309 | ||
16310 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16311 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16312 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16313 | generic type-checking code. */ | |
16314 | if (section_type == SHT_MIPS_DWARF) | |
16315 | section_type = SHT_PROGBITS; | |
16316 | ||
cca86cc8 SC |
16317 | obj_elf_change_section (section_name, section_type, section_flag, |
16318 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16319 | |
16320 | if (now_seg->name != section_name) | |
16321 | free (section_name); | |
7ed4a06a | 16322 | #endif /* OBJ_ELF */ |
cca86cc8 | 16323 | } |
252b5132 RH |
16324 | |
16325 | void | |
17a2f251 | 16326 | mips_enable_auto_align (void) |
252b5132 RH |
16327 | { |
16328 | auto_align = 1; | |
16329 | } | |
16330 | ||
16331 | static void | |
17a2f251 | 16332 | s_cons (int log_size) |
252b5132 | 16333 | { |
a8dbcb85 TS |
16334 | segment_info_type *si = seg_info (now_seg); |
16335 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16336 | |
7d10b47d | 16337 | mips_emit_delays (); |
252b5132 | 16338 | if (log_size > 0 && auto_align) |
462427c4 | 16339 | mips_align (log_size, 0, l); |
252b5132 | 16340 | cons (1 << log_size); |
a1facbec | 16341 | mips_clear_insn_labels (); |
252b5132 RH |
16342 | } |
16343 | ||
16344 | static void | |
17a2f251 | 16345 | s_float_cons (int type) |
252b5132 | 16346 | { |
a8dbcb85 TS |
16347 | segment_info_type *si = seg_info (now_seg); |
16348 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16349 | |
7d10b47d | 16350 | mips_emit_delays (); |
252b5132 RH |
16351 | |
16352 | if (auto_align) | |
49309057 ILT |
16353 | { |
16354 | if (type == 'd') | |
462427c4 | 16355 | mips_align (3, 0, l); |
49309057 | 16356 | else |
462427c4 | 16357 | mips_align (2, 0, l); |
49309057 | 16358 | } |
252b5132 | 16359 | |
252b5132 | 16360 | float_cons (type); |
a1facbec | 16361 | mips_clear_insn_labels (); |
252b5132 RH |
16362 | } |
16363 | ||
16364 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16365 | permitted to say | |
16366 | .globl foo .text | |
16367 | where foo is an undefined symbol, to mean that foo should be | |
16368 | considered to be the address of a function. */ | |
16369 | ||
16370 | static void | |
17a2f251 | 16371 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16372 | { |
16373 | char *name; | |
16374 | int c; | |
16375 | symbolS *symbolP; | |
16376 | flagword flag; | |
16377 | ||
8a06b769 | 16378 | do |
252b5132 | 16379 | { |
8a06b769 | 16380 | name = input_line_pointer; |
252b5132 | 16381 | c = get_symbol_end (); |
8a06b769 TS |
16382 | symbolP = symbol_find_or_make (name); |
16383 | S_SET_EXTERNAL (symbolP); | |
16384 | ||
252b5132 | 16385 | *input_line_pointer = c; |
8a06b769 | 16386 | SKIP_WHITESPACE (); |
252b5132 | 16387 | |
8a06b769 TS |
16388 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16389 | being a function is apparently labelled as being an object. */ | |
16390 | flag = BSF_OBJECT; | |
252b5132 | 16391 | |
8a06b769 TS |
16392 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16393 | && (*input_line_pointer != ',')) | |
16394 | { | |
16395 | char *secname; | |
16396 | asection *sec; | |
16397 | ||
16398 | secname = input_line_pointer; | |
16399 | c = get_symbol_end (); | |
16400 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16401 | if (sec == NULL) | |
16402 | as_bad (_("%s: no such section"), secname); | |
16403 | *input_line_pointer = c; | |
16404 | ||
16405 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16406 | flag = BSF_FUNCTION; | |
16407 | } | |
16408 | ||
16409 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16410 | ||
16411 | c = *input_line_pointer; | |
16412 | if (c == ',') | |
16413 | { | |
16414 | input_line_pointer++; | |
16415 | SKIP_WHITESPACE (); | |
16416 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16417 | c = '\n'; | |
16418 | } | |
16419 | } | |
16420 | while (c == ','); | |
252b5132 | 16421 | |
252b5132 RH |
16422 | demand_empty_rest_of_line (); |
16423 | } | |
16424 | ||
16425 | static void | |
17a2f251 | 16426 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16427 | { |
16428 | char *opt; | |
16429 | char c; | |
16430 | ||
16431 | opt = input_line_pointer; | |
16432 | c = get_symbol_end (); | |
16433 | ||
16434 | if (*opt == 'O') | |
16435 | { | |
16436 | /* FIXME: What does this mean? */ | |
16437 | } | |
16438 | else if (strncmp (opt, "pic", 3) == 0) | |
16439 | { | |
16440 | int i; | |
16441 | ||
16442 | i = atoi (opt + 3); | |
16443 | if (i == 0) | |
16444 | mips_pic = NO_PIC; | |
16445 | else if (i == 2) | |
143d77c5 | 16446 | { |
8b828383 | 16447 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16448 | mips_abicalls = TRUE; |
16449 | } | |
252b5132 RH |
16450 | else |
16451 | as_bad (_(".option pic%d not supported"), i); | |
16452 | ||
4d0d148d | 16453 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16454 | { |
16455 | if (g_switch_seen && g_switch_value != 0) | |
16456 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16457 | g_switch_value = 0; | |
16458 | bfd_set_gp_size (stdoutput, 0); | |
16459 | } | |
16460 | } | |
16461 | else | |
16462 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16463 | ||
16464 | *input_line_pointer = c; | |
16465 | demand_empty_rest_of_line (); | |
16466 | } | |
16467 | ||
16468 | /* This structure is used to hold a stack of .set values. */ | |
16469 | ||
e972090a NC |
16470 | struct mips_option_stack |
16471 | { | |
252b5132 RH |
16472 | struct mips_option_stack *next; |
16473 | struct mips_set_options options; | |
16474 | }; | |
16475 | ||
16476 | static struct mips_option_stack *mips_opts_stack; | |
16477 | ||
16478 | /* Handle the .set pseudo-op. */ | |
16479 | ||
16480 | static void | |
17a2f251 | 16481 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16482 | { |
16483 | char *name = input_line_pointer, ch; | |
16484 | ||
16485 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16486 | ++input_line_pointer; |
252b5132 RH |
16487 | ch = *input_line_pointer; |
16488 | *input_line_pointer = '\0'; | |
16489 | ||
16490 | if (strcmp (name, "reorder") == 0) | |
16491 | { | |
7d10b47d RS |
16492 | if (mips_opts.noreorder) |
16493 | end_noreorder (); | |
252b5132 RH |
16494 | } |
16495 | else if (strcmp (name, "noreorder") == 0) | |
16496 | { | |
7d10b47d RS |
16497 | if (!mips_opts.noreorder) |
16498 | start_noreorder (); | |
252b5132 | 16499 | } |
741fe287 MR |
16500 | else if (strncmp (name, "at=", 3) == 0) |
16501 | { | |
16502 | char *s = name + 3; | |
16503 | ||
16504 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16505 | as_bad (_("Unrecognized register name `%s'"), s); | |
16506 | } | |
252b5132 RH |
16507 | else if (strcmp (name, "at") == 0) |
16508 | { | |
741fe287 | 16509 | mips_opts.at = ATREG; |
252b5132 RH |
16510 | } |
16511 | else if (strcmp (name, "noat") == 0) | |
16512 | { | |
741fe287 | 16513 | mips_opts.at = ZERO; |
252b5132 RH |
16514 | } |
16515 | else if (strcmp (name, "macro") == 0) | |
16516 | { | |
16517 | mips_opts.warn_about_macros = 0; | |
16518 | } | |
16519 | else if (strcmp (name, "nomacro") == 0) | |
16520 | { | |
16521 | if (mips_opts.noreorder == 0) | |
16522 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16523 | mips_opts.warn_about_macros = 1; | |
16524 | } | |
16525 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16526 | { | |
16527 | mips_opts.nomove = 0; | |
16528 | } | |
16529 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16530 | { | |
16531 | mips_opts.nomove = 1; | |
16532 | } | |
16533 | else if (strcmp (name, "bopt") == 0) | |
16534 | { | |
16535 | mips_opts.nobopt = 0; | |
16536 | } | |
16537 | else if (strcmp (name, "nobopt") == 0) | |
16538 | { | |
16539 | mips_opts.nobopt = 1; | |
16540 | } | |
ad3fea08 TS |
16541 | else if (strcmp (name, "gp=default") == 0) |
16542 | mips_opts.gp32 = file_mips_gp32; | |
16543 | else if (strcmp (name, "gp=32") == 0) | |
16544 | mips_opts.gp32 = 1; | |
16545 | else if (strcmp (name, "gp=64") == 0) | |
16546 | { | |
16547 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16548 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16549 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16550 | mips_opts.gp32 = 0; | |
16551 | } | |
16552 | else if (strcmp (name, "fp=default") == 0) | |
16553 | mips_opts.fp32 = file_mips_fp32; | |
16554 | else if (strcmp (name, "fp=32") == 0) | |
16555 | mips_opts.fp32 = 1; | |
16556 | else if (strcmp (name, "fp=64") == 0) | |
16557 | { | |
16558 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16559 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16560 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16561 | mips_opts.fp32 = 0; | |
16562 | } | |
037b32b9 AN |
16563 | else if (strcmp (name, "softfloat") == 0) |
16564 | mips_opts.soft_float = 1; | |
16565 | else if (strcmp (name, "hardfloat") == 0) | |
16566 | mips_opts.soft_float = 0; | |
16567 | else if (strcmp (name, "singlefloat") == 0) | |
16568 | mips_opts.single_float = 1; | |
16569 | else if (strcmp (name, "doublefloat") == 0) | |
16570 | mips_opts.single_float = 0; | |
252b5132 RH |
16571 | else if (strcmp (name, "mips16") == 0 |
16572 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16573 | { |
16574 | if (mips_opts.micromips == 1) | |
16575 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16576 | mips_opts.mips16 = 1; | |
16577 | } | |
252b5132 RH |
16578 | else if (strcmp (name, "nomips16") == 0 |
16579 | || strcmp (name, "noMIPS-16") == 0) | |
16580 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16581 | else if (strcmp (name, "micromips") == 0) |
16582 | { | |
16583 | if (mips_opts.mips16 == 1) | |
16584 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16585 | mips_opts.micromips = 1; | |
16586 | } | |
16587 | else if (strcmp (name, "nomicromips") == 0) | |
16588 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16589 | else if (strcmp (name, "smartmips") == 0) |
16590 | { | |
ad3fea08 | 16591 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16592 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 | 16593 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
846ef2d0 | 16594 | mips_opts.ase |= ASE_SMARTMIPS; |
e16bfa71 TS |
16595 | } |
16596 | else if (strcmp (name, "nosmartmips") == 0) | |
846ef2d0 | 16597 | mips_opts.ase &= ~ASE_SMARTMIPS; |
1f25f5d3 | 16598 | else if (strcmp (name, "mips3d") == 0) |
846ef2d0 | 16599 | mips_opts.ase |= ASE_MIPS3D; |
1f25f5d3 | 16600 | else if (strcmp (name, "nomips3d") == 0) |
846ef2d0 | 16601 | mips_opts.ase &= ~ASE_MIPS3D; |
a4672219 | 16602 | else if (strcmp (name, "mdmx") == 0) |
846ef2d0 | 16603 | mips_opts.ase |= ASE_MDMX; |
a4672219 | 16604 | else if (strcmp (name, "nomdmx") == 0) |
846ef2d0 | 16605 | mips_opts.ase &= ~ASE_MDMX; |
74cd071d | 16606 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16607 | { |
16608 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16609 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 | 16610 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
846ef2d0 RS |
16611 | mips_opts.ase |= ASE_DSP; |
16612 | mips_opts.ase &= ~ASE_DSPR2; | |
8b082fb1 TS |
16613 | } |
16614 | else if (strcmp (name, "dspr2") == 0) | |
16615 | { | |
16616 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16617 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 | 16618 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
846ef2d0 | 16619 | mips_opts.ase |= ASE_DSP | ASE_DSPR2; |
8b082fb1 | 16620 | } |
846ef2d0 RS |
16621 | else if (strcmp (name, "nodsp") == 0 |
16622 | || strcmp (name, "nodspr2") == 0) | |
16623 | mips_opts.ase &= ~(ASE_DSP | ASE_DSPR2); | |
7f3c4072 CM |
16624 | else if (strcmp (name, "eva") == 0) |
16625 | { | |
16626 | if (!ISA_SUPPORTS_EVA_ASE) | |
16627 | as_warn (_("%s ISA does not support EVA ASE"), | |
16628 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
846ef2d0 | 16629 | mips_opts.ase |= ASE_EVA; |
7f3c4072 CM |
16630 | } |
16631 | else if (strcmp (name, "noeva") == 0) | |
846ef2d0 | 16632 | mips_opts.ase &= ~ASE_EVA; |
ef2e4d86 | 16633 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16634 | { |
16635 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16636 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 | 16637 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
846ef2d0 | 16638 | mips_opts.ase |= ASE_MT; |
ad3fea08 | 16639 | } |
ef2e4d86 | 16640 | else if (strcmp (name, "nomt") == 0) |
846ef2d0 | 16641 | mips_opts.ase &= ~ASE_MT; |
dec0624d | 16642 | else if (strcmp (name, "mcu") == 0) |
846ef2d0 | 16643 | mips_opts.ase |= ASE_MCU; |
dec0624d | 16644 | else if (strcmp (name, "nomcu") == 0) |
846ef2d0 | 16645 | mips_opts.ase &= ~ASE_MCU; |
b015e599 AP |
16646 | else if (strcmp (name, "virt") == 0) |
16647 | { | |
16648 | if (!ISA_SUPPORTS_VIRT_ASE) | |
16649 | as_warn (_("%s ISA does not support Virtualization ASE"), | |
16650 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
846ef2d0 | 16651 | mips_opts.ase |= ASE_VIRT; |
b015e599 AP |
16652 | } |
16653 | else if (strcmp (name, "novirt") == 0) | |
846ef2d0 | 16654 | mips_opts.ase &= ~ASE_VIRT; |
1a2c1fad | 16655 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16656 | { |
af7ee8bf | 16657 | int reset = 0; |
252b5132 | 16658 | |
1a2c1fad CD |
16659 | /* Permit the user to change the ISA and architecture on the fly. |
16660 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16661 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16662 | { |
16663 | reset = 1; | |
16664 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16665 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16666 | } |
16667 | else if (strncmp (name, "arch=", 5) == 0) | |
16668 | { | |
16669 | const struct mips_cpu_info *p; | |
16670 | ||
16671 | p = mips_parse_cpu("internal use", name + 5); | |
16672 | if (!p) | |
16673 | as_bad (_("unknown architecture %s"), name + 5); | |
16674 | else | |
16675 | { | |
16676 | mips_opts.arch = p->cpu; | |
16677 | mips_opts.isa = p->isa; | |
16678 | } | |
16679 | } | |
81a21e38 TS |
16680 | else if (strncmp (name, "mips", 4) == 0) |
16681 | { | |
16682 | const struct mips_cpu_info *p; | |
16683 | ||
16684 | p = mips_parse_cpu("internal use", name); | |
16685 | if (!p) | |
16686 | as_bad (_("unknown ISA level %s"), name + 4); | |
16687 | else | |
16688 | { | |
16689 | mips_opts.arch = p->cpu; | |
16690 | mips_opts.isa = p->isa; | |
16691 | } | |
16692 | } | |
af7ee8bf | 16693 | else |
81a21e38 | 16694 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16695 | |
16696 | switch (mips_opts.isa) | |
98d3f06f KH |
16697 | { |
16698 | case 0: | |
98d3f06f | 16699 | break; |
af7ee8bf CD |
16700 | case ISA_MIPS1: |
16701 | case ISA_MIPS2: | |
16702 | case ISA_MIPS32: | |
16703 | case ISA_MIPS32R2: | |
98d3f06f KH |
16704 | mips_opts.gp32 = 1; |
16705 | mips_opts.fp32 = 1; | |
16706 | break; | |
af7ee8bf CD |
16707 | case ISA_MIPS3: |
16708 | case ISA_MIPS4: | |
16709 | case ISA_MIPS5: | |
16710 | case ISA_MIPS64: | |
5f74bc13 | 16711 | case ISA_MIPS64R2: |
98d3f06f | 16712 | mips_opts.gp32 = 0; |
e407c74b NC |
16713 | if (mips_opts.arch == CPU_R5900) |
16714 | { | |
16715 | mips_opts.fp32 = 1; | |
16716 | } | |
16717 | else | |
16718 | { | |
98d3f06f | 16719 | mips_opts.fp32 = 0; |
e407c74b | 16720 | } |
98d3f06f KH |
16721 | break; |
16722 | default: | |
16723 | as_bad (_("unknown ISA level %s"), name + 4); | |
16724 | break; | |
16725 | } | |
af7ee8bf | 16726 | if (reset) |
98d3f06f | 16727 | { |
af7ee8bf CD |
16728 | mips_opts.gp32 = file_mips_gp32; |
16729 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16730 | } |
252b5132 RH |
16731 | } |
16732 | else if (strcmp (name, "autoextend") == 0) | |
16733 | mips_opts.noautoextend = 0; | |
16734 | else if (strcmp (name, "noautoextend") == 0) | |
16735 | mips_opts.noautoextend = 1; | |
16736 | else if (strcmp (name, "push") == 0) | |
16737 | { | |
16738 | struct mips_option_stack *s; | |
16739 | ||
16740 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16741 | s->next = mips_opts_stack; | |
16742 | s->options = mips_opts; | |
16743 | mips_opts_stack = s; | |
16744 | } | |
16745 | else if (strcmp (name, "pop") == 0) | |
16746 | { | |
16747 | struct mips_option_stack *s; | |
16748 | ||
16749 | s = mips_opts_stack; | |
16750 | if (s == NULL) | |
16751 | as_bad (_(".set pop with no .set push")); | |
16752 | else | |
16753 | { | |
16754 | /* If we're changing the reorder mode we need to handle | |
16755 | delay slots correctly. */ | |
16756 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16757 | start_noreorder (); |
252b5132 | 16758 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16759 | end_noreorder (); |
252b5132 RH |
16760 | |
16761 | mips_opts = s->options; | |
16762 | mips_opts_stack = s->next; | |
16763 | free (s); | |
16764 | } | |
16765 | } | |
aed1a261 RS |
16766 | else if (strcmp (name, "sym32") == 0) |
16767 | mips_opts.sym32 = TRUE; | |
16768 | else if (strcmp (name, "nosym32") == 0) | |
16769 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16770 | else if (strchr (name, ',')) |
16771 | { | |
16772 | /* Generic ".set" directive; use the generic handler. */ | |
16773 | *input_line_pointer = ch; | |
16774 | input_line_pointer = name; | |
16775 | s_set (0); | |
16776 | return; | |
16777 | } | |
252b5132 RH |
16778 | else |
16779 | { | |
16780 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16781 | } | |
16782 | *input_line_pointer = ch; | |
16783 | demand_empty_rest_of_line (); | |
16784 | } | |
16785 | ||
16786 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16787 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16788 | ||
16789 | static void | |
17a2f251 | 16790 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16791 | { |
16792 | mips_pic = SVR4_PIC; | |
143d77c5 | 16793 | mips_abicalls = TRUE; |
4d0d148d TS |
16794 | |
16795 | if (g_switch_seen && g_switch_value != 0) | |
16796 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16797 | g_switch_value = 0; | |
16798 | ||
252b5132 RH |
16799 | bfd_set_gp_size (stdoutput, 0); |
16800 | demand_empty_rest_of_line (); | |
16801 | } | |
16802 | ||
16803 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16804 | PIC code. It sets the $gp register for the function based on the | |
16805 | function address, which is in the register named in the argument. | |
16806 | This uses a relocation against _gp_disp, which is handled specially | |
16807 | by the linker. The result is: | |
16808 | lui $gp,%hi(_gp_disp) | |
16809 | addiu $gp,$gp,%lo(_gp_disp) | |
16810 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16811 | The .cpload argument is normally $25 == $t9. |
16812 | ||
16813 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16814 | lui $gp,%hi(__gnu_local_gp) |
16815 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16816 | and the argument is ignored. This saves an instruction, but the |
16817 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16818 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16819 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16820 | |
16821 | static void | |
17a2f251 | 16822 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16823 | { |
16824 | expressionS ex; | |
aa6975fb ILT |
16825 | int reg; |
16826 | int in_shared; | |
252b5132 | 16827 | |
6478892d TS |
16828 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16829 | .cpload is ignored. */ | |
16830 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16831 | { |
16832 | s_ignore (0); | |
16833 | return; | |
16834 | } | |
16835 | ||
a276b80c MR |
16836 | if (mips_opts.mips16) |
16837 | { | |
16838 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16839 | ignore_rest_of_line (); | |
16840 | return; | |
16841 | } | |
16842 | ||
d3ecfc59 | 16843 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16844 | if (mips_opts.noreorder == 0) |
16845 | as_warn (_(".cpload not in noreorder section")); | |
16846 | ||
aa6975fb ILT |
16847 | reg = tc_get_register (0); |
16848 | ||
16849 | /* If we need to produce a 64-bit address, we are better off using | |
16850 | the default instruction sequence. */ | |
aed1a261 | 16851 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16852 | |
252b5132 | 16853 | ex.X_op = O_symbol; |
bbe506e8 TS |
16854 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16855 | "__gnu_local_gp"); | |
252b5132 RH |
16856 | ex.X_op_symbol = NULL; |
16857 | ex.X_add_number = 0; | |
16858 | ||
16859 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16860 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16861 | |
8a75745d MR |
16862 | mips_mark_labels (); |
16863 | mips_assembling_insn = TRUE; | |
16864 | ||
584892a6 | 16865 | macro_start (); |
67c0d1eb RS |
16866 | macro_build_lui (&ex, mips_gp_register); |
16867 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16868 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16869 | if (in_shared) |
16870 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16871 | mips_gp_register, reg); | |
584892a6 | 16872 | macro_end (); |
252b5132 | 16873 | |
8a75745d | 16874 | mips_assembling_insn = FALSE; |
252b5132 RH |
16875 | demand_empty_rest_of_line (); |
16876 | } | |
16877 | ||
6478892d TS |
16878 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16879 | .cpsetup $reg1, offset|$reg2, label | |
16880 | ||
16881 | If offset is given, this results in: | |
16882 | sd $gp, offset($sp) | |
956cd1d6 | 16883 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16884 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16885 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16886 | |
16887 | If $reg2 is given, this results in: | |
16888 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16889 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16890 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16891 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16892 | $reg1 is normally $25 == $t9. |
16893 | ||
16894 | The -mno-shared option replaces the last three instructions with | |
16895 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16896 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16897 | |
6478892d | 16898 | static void |
17a2f251 | 16899 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16900 | { |
16901 | expressionS ex_off; | |
16902 | expressionS ex_sym; | |
16903 | int reg1; | |
6478892d | 16904 | |
8586fc66 | 16905 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16906 | We also need NewABI support. */ |
16907 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16908 | { | |
16909 | s_ignore (0); | |
16910 | return; | |
16911 | } | |
16912 | ||
a276b80c MR |
16913 | if (mips_opts.mips16) |
16914 | { | |
16915 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16916 | ignore_rest_of_line (); | |
16917 | return; | |
16918 | } | |
16919 | ||
6478892d TS |
16920 | reg1 = tc_get_register (0); |
16921 | SKIP_WHITESPACE (); | |
16922 | if (*input_line_pointer != ',') | |
16923 | { | |
16924 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16925 | return; | |
16926 | } | |
16927 | else | |
80245285 | 16928 | ++input_line_pointer; |
6478892d TS |
16929 | SKIP_WHITESPACE (); |
16930 | if (*input_line_pointer == '$') | |
80245285 TS |
16931 | { |
16932 | mips_cpreturn_register = tc_get_register (0); | |
16933 | mips_cpreturn_offset = -1; | |
16934 | } | |
6478892d | 16935 | else |
80245285 TS |
16936 | { |
16937 | mips_cpreturn_offset = get_absolute_expression (); | |
16938 | mips_cpreturn_register = -1; | |
16939 | } | |
6478892d TS |
16940 | SKIP_WHITESPACE (); |
16941 | if (*input_line_pointer != ',') | |
16942 | { | |
16943 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16944 | return; | |
16945 | } | |
16946 | else | |
f9419b05 | 16947 | ++input_line_pointer; |
6478892d | 16948 | SKIP_WHITESPACE (); |
f21f8242 | 16949 | expression (&ex_sym); |
6478892d | 16950 | |
8a75745d MR |
16951 | mips_mark_labels (); |
16952 | mips_assembling_insn = TRUE; | |
16953 | ||
584892a6 | 16954 | macro_start (); |
6478892d TS |
16955 | if (mips_cpreturn_register == -1) |
16956 | { | |
16957 | ex_off.X_op = O_constant; | |
16958 | ex_off.X_add_symbol = NULL; | |
16959 | ex_off.X_op_symbol = NULL; | |
16960 | ex_off.X_add_number = mips_cpreturn_offset; | |
16961 | ||
67c0d1eb | 16962 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16963 | BFD_RELOC_LO16, SP); |
6478892d TS |
16964 | } |
16965 | else | |
67c0d1eb | 16966 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16967 | mips_gp_register, 0); |
6478892d | 16968 | |
aed1a261 | 16969 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16970 | { |
df58fc94 | 16971 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16972 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16973 | BFD_RELOC_HI16_S); | |
16974 | ||
16975 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16976 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16977 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16978 | ||
16979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16980 | mips_gp_register, reg1); | |
16981 | } | |
16982 | else | |
16983 | { | |
16984 | expressionS ex; | |
16985 | ||
16986 | ex.X_op = O_symbol; | |
4184909a | 16987 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16988 | ex.X_op_symbol = NULL; |
16989 | ex.X_add_number = 0; | |
6e1304d8 | 16990 | |
aa6975fb ILT |
16991 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16992 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16993 | ||
16994 | macro_build_lui (&ex, mips_gp_register); | |
16995 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16996 | mips_gp_register, BFD_RELOC_LO16); | |
16997 | } | |
f21f8242 | 16998 | |
584892a6 | 16999 | macro_end (); |
6478892d | 17000 | |
8a75745d | 17001 | mips_assembling_insn = FALSE; |
6478892d TS |
17002 | demand_empty_rest_of_line (); |
17003 | } | |
17004 | ||
17005 | static void | |
17a2f251 | 17006 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17007 | { |
17008 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 17009 | .cplocal is ignored. */ |
6478892d TS |
17010 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17011 | { | |
17012 | s_ignore (0); | |
17013 | return; | |
17014 | } | |
17015 | ||
a276b80c MR |
17016 | if (mips_opts.mips16) |
17017 | { | |
17018 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17019 | ignore_rest_of_line (); | |
17020 | return; | |
17021 | } | |
17022 | ||
6478892d | 17023 | mips_gp_register = tc_get_register (0); |
85b51719 | 17024 | demand_empty_rest_of_line (); |
6478892d TS |
17025 | } |
17026 | ||
252b5132 RH |
17027 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17028 | offset from $sp. The offset is remembered, and after making a PIC | |
17029 | call $gp is restored from that location. */ | |
17030 | ||
17031 | static void | |
17a2f251 | 17032 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17033 | { |
17034 | expressionS ex; | |
252b5132 | 17035 | |
6478892d | 17036 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17037 | .cprestore is ignored. */ |
6478892d | 17038 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17039 | { |
17040 | s_ignore (0); | |
17041 | return; | |
17042 | } | |
17043 | ||
a276b80c MR |
17044 | if (mips_opts.mips16) |
17045 | { | |
17046 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17047 | ignore_rest_of_line (); | |
17048 | return; | |
17049 | } | |
17050 | ||
252b5132 | 17051 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17052 | mips_cprestore_valid = 1; |
252b5132 RH |
17053 | |
17054 | ex.X_op = O_constant; | |
17055 | ex.X_add_symbol = NULL; | |
17056 | ex.X_op_symbol = NULL; | |
17057 | ex.X_add_number = mips_cprestore_offset; | |
17058 | ||
8a75745d MR |
17059 | mips_mark_labels (); |
17060 | mips_assembling_insn = TRUE; | |
17061 | ||
584892a6 | 17062 | macro_start (); |
67c0d1eb RS |
17063 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17064 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17065 | macro_end (); |
252b5132 | 17066 | |
8a75745d | 17067 | mips_assembling_insn = FALSE; |
252b5132 RH |
17068 | demand_empty_rest_of_line (); |
17069 | } | |
17070 | ||
6478892d | 17071 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17072 | was given in the preceding .cpsetup, it results in: |
6478892d | 17073 | ld $gp, offset($sp) |
76b3015f | 17074 | |
6478892d | 17075 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
17076 | daddu $gp, $reg2, $0 */ |
17077 | ||
6478892d | 17078 | static void |
17a2f251 | 17079 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17080 | { |
17081 | expressionS ex; | |
6478892d TS |
17082 | |
17083 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
17084 | We also need NewABI support. */ | |
17085 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17086 | { | |
17087 | s_ignore (0); | |
17088 | return; | |
17089 | } | |
17090 | ||
a276b80c MR |
17091 | if (mips_opts.mips16) |
17092 | { | |
17093 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17094 | ignore_rest_of_line (); | |
17095 | return; | |
17096 | } | |
17097 | ||
8a75745d MR |
17098 | mips_mark_labels (); |
17099 | mips_assembling_insn = TRUE; | |
17100 | ||
584892a6 | 17101 | macro_start (); |
6478892d TS |
17102 | if (mips_cpreturn_register == -1) |
17103 | { | |
17104 | ex.X_op = O_constant; | |
17105 | ex.X_add_symbol = NULL; | |
17106 | ex.X_op_symbol = NULL; | |
17107 | ex.X_add_number = mips_cpreturn_offset; | |
17108 | ||
67c0d1eb | 17109 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17110 | } |
17111 | else | |
67c0d1eb | 17112 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 17113 | mips_cpreturn_register, 0); |
584892a6 | 17114 | macro_end (); |
6478892d | 17115 | |
8a75745d | 17116 | mips_assembling_insn = FALSE; |
6478892d TS |
17117 | demand_empty_rest_of_line (); |
17118 | } | |
17119 | ||
d0f13682 CLT |
17120 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17121 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17122 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17123 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17124 | |
17125 | static void | |
d0f13682 CLT |
17126 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17127 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17128 | { |
17129 | expressionS ex; | |
17130 | char *p; | |
17131 | ||
17132 | expression (&ex); | |
17133 | ||
17134 | if (ex.X_op != O_symbol) | |
17135 | { | |
d0f13682 | 17136 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
17137 | ignore_rest_of_line (); |
17138 | } | |
17139 | ||
17140 | p = frag_more (bytes); | |
17141 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17142 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17143 | demand_empty_rest_of_line (); |
de64cffd | 17144 | mips_clear_insn_labels (); |
741d6ea8 JM |
17145 | } |
17146 | ||
17147 | /* Handle .dtprelword. */ | |
17148 | ||
17149 | static void | |
17150 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17151 | { | |
d0f13682 | 17152 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17153 | } |
17154 | ||
17155 | /* Handle .dtpreldword. */ | |
17156 | ||
17157 | static void | |
17158 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17159 | { | |
d0f13682 CLT |
17160 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17161 | } | |
17162 | ||
17163 | /* Handle .tprelword. */ | |
17164 | ||
17165 | static void | |
17166 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17167 | { | |
17168 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17169 | } | |
17170 | ||
17171 | /* Handle .tpreldword. */ | |
17172 | ||
17173 | static void | |
17174 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17175 | { | |
17176 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17177 | } |
17178 | ||
6478892d TS |
17179 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17180 | code. It sets the offset to use in gp_rel relocations. */ | |
17181 | ||
17182 | static void | |
17a2f251 | 17183 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17184 | { |
17185 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17186 | We also need NewABI support. */ | |
17187 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17188 | { | |
17189 | s_ignore (0); | |
17190 | return; | |
17191 | } | |
17192 | ||
def2e0dd | 17193 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17194 | |
17195 | demand_empty_rest_of_line (); | |
17196 | } | |
17197 | ||
252b5132 RH |
17198 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17199 | code. It generates a 32 bit GP relative reloc. */ | |
17200 | ||
17201 | static void | |
17a2f251 | 17202 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17203 | { |
a8dbcb85 TS |
17204 | segment_info_type *si; |
17205 | struct insn_label_list *l; | |
252b5132 RH |
17206 | expressionS ex; |
17207 | char *p; | |
17208 | ||
17209 | /* When not generating PIC code, this is treated as .word. */ | |
17210 | if (mips_pic != SVR4_PIC) | |
17211 | { | |
17212 | s_cons (2); | |
17213 | return; | |
17214 | } | |
17215 | ||
a8dbcb85 TS |
17216 | si = seg_info (now_seg); |
17217 | l = si->label_list; | |
7d10b47d | 17218 | mips_emit_delays (); |
252b5132 | 17219 | if (auto_align) |
462427c4 | 17220 | mips_align (2, 0, l); |
252b5132 RH |
17221 | |
17222 | expression (&ex); | |
a1facbec | 17223 | mips_clear_insn_labels (); |
252b5132 RH |
17224 | |
17225 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17226 | { | |
17227 | as_bad (_("Unsupported use of .gpword")); | |
17228 | ignore_rest_of_line (); | |
17229 | } | |
17230 | ||
17231 | p = frag_more (4); | |
17a2f251 | 17232 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17233 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17234 | BFD_RELOC_GPREL32); |
252b5132 RH |
17235 | |
17236 | demand_empty_rest_of_line (); | |
17237 | } | |
17238 | ||
10181a0d | 17239 | static void |
17a2f251 | 17240 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17241 | { |
a8dbcb85 TS |
17242 | segment_info_type *si; |
17243 | struct insn_label_list *l; | |
10181a0d AO |
17244 | expressionS ex; |
17245 | char *p; | |
17246 | ||
17247 | /* When not generating PIC code, this is treated as .dword. */ | |
17248 | if (mips_pic != SVR4_PIC) | |
17249 | { | |
17250 | s_cons (3); | |
17251 | return; | |
17252 | } | |
17253 | ||
a8dbcb85 TS |
17254 | si = seg_info (now_seg); |
17255 | l = si->label_list; | |
7d10b47d | 17256 | mips_emit_delays (); |
10181a0d | 17257 | if (auto_align) |
462427c4 | 17258 | mips_align (3, 0, l); |
10181a0d AO |
17259 | |
17260 | expression (&ex); | |
a1facbec | 17261 | mips_clear_insn_labels (); |
10181a0d AO |
17262 | |
17263 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17264 | { | |
17265 | as_bad (_("Unsupported use of .gpdword")); | |
17266 | ignore_rest_of_line (); | |
17267 | } | |
17268 | ||
17269 | p = frag_more (8); | |
17a2f251 | 17270 | md_number_to_chars (p, 0, 8); |
a105a300 | 17271 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17272 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17273 | |
17274 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17275 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17276 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17277 | |
17278 | demand_empty_rest_of_line (); | |
17279 | } | |
17280 | ||
a3f278e2 CM |
17281 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17282 | tables. It generates a R_MIPS_EH reloc. */ | |
17283 | ||
17284 | static void | |
17285 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17286 | { | |
17287 | expressionS ex; | |
17288 | char *p; | |
17289 | ||
17290 | mips_emit_delays (); | |
17291 | ||
17292 | expression (&ex); | |
17293 | mips_clear_insn_labels (); | |
17294 | ||
17295 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17296 | { | |
17297 | as_bad (_("Unsupported use of .ehword")); | |
17298 | ignore_rest_of_line (); | |
17299 | } | |
17300 | ||
17301 | p = frag_more (4); | |
17302 | md_number_to_chars (p, 0, 4); | |
17303 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17304 | BFD_RELOC_MIPS_EH); | |
17305 | ||
17306 | demand_empty_rest_of_line (); | |
17307 | } | |
17308 | ||
252b5132 RH |
17309 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17310 | tables in SVR4 PIC code. */ | |
17311 | ||
17312 | static void | |
17a2f251 | 17313 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17314 | { |
252b5132 RH |
17315 | int reg; |
17316 | ||
10181a0d AO |
17317 | /* This is ignored when not generating SVR4 PIC code. */ |
17318 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17319 | { |
17320 | s_ignore (0); | |
17321 | return; | |
17322 | } | |
17323 | ||
8a75745d MR |
17324 | mips_mark_labels (); |
17325 | mips_assembling_insn = TRUE; | |
17326 | ||
252b5132 | 17327 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17328 | macro_start (); |
252b5132 | 17329 | reg = tc_get_register (0); |
67c0d1eb | 17330 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17331 | macro_end (); |
252b5132 | 17332 | |
8a75745d | 17333 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17334 | demand_empty_rest_of_line (); |
252b5132 RH |
17335 | } |
17336 | ||
17337 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17338 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17339 | such as generating jalx instructions when needed. We also make |
17340 | them odd for the duration of the assembly, in order to generate the | |
17341 | right sort of code. We will make them even in the adjust_symtab | |
17342 | routine, while leaving them marked. This is convenient for the | |
17343 | debugger and the disassembler. The linker knows to make them odd | |
17344 | again. */ | |
17345 | ||
17346 | static void | |
17a2f251 | 17347 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17348 | { |
df58fc94 | 17349 | mips_mark_labels (); |
252b5132 RH |
17350 | |
17351 | demand_empty_rest_of_line (); | |
17352 | } | |
17353 | ||
754e2bb9 RS |
17354 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17355 | implemented in a transparent way, so that removing them would not | |
17356 | have any effect on the generated instructions. However, s_stab | |
17357 | internally changes the section, so in practice we need to decide | |
17358 | now whether the preceding label marks compressed code. We do not | |
17359 | support changing the compression mode of a label after a .stab* | |
17360 | directive, such as in: | |
17361 | ||
17362 | foo: | |
17363 | .stabs ... | |
17364 | .set mips16 | |
17365 | ||
17366 | so the current mode wins. */ | |
252b5132 RH |
17367 | |
17368 | static void | |
17a2f251 | 17369 | s_mips_stab (int type) |
252b5132 | 17370 | { |
754e2bb9 | 17371 | mips_mark_labels (); |
252b5132 RH |
17372 | s_stab (type); |
17373 | } | |
17374 | ||
54f4ddb3 | 17375 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17376 | |
17377 | static void | |
17a2f251 | 17378 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17379 | { |
17380 | char *name; | |
17381 | int c; | |
17382 | symbolS *symbolP; | |
17383 | expressionS exp; | |
17384 | ||
17385 | name = input_line_pointer; | |
17386 | c = get_symbol_end (); | |
17387 | symbolP = symbol_find_or_make (name); | |
17388 | S_SET_WEAK (symbolP); | |
17389 | *input_line_pointer = c; | |
17390 | ||
17391 | SKIP_WHITESPACE (); | |
17392 | ||
17393 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17394 | { | |
17395 | if (S_IS_DEFINED (symbolP)) | |
17396 | { | |
20203fb9 | 17397 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17398 | S_GET_NAME (symbolP)); |
17399 | ignore_rest_of_line (); | |
17400 | return; | |
17401 | } | |
bdaaa2e1 | 17402 | |
252b5132 RH |
17403 | if (*input_line_pointer == ',') |
17404 | { | |
17405 | ++input_line_pointer; | |
17406 | SKIP_WHITESPACE (); | |
17407 | } | |
bdaaa2e1 | 17408 | |
252b5132 RH |
17409 | expression (&exp); |
17410 | if (exp.X_op != O_symbol) | |
17411 | { | |
20203fb9 | 17412 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17413 | ignore_rest_of_line (); |
252b5132 RH |
17414 | return; |
17415 | } | |
49309057 | 17416 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17417 | } |
17418 | ||
17419 | demand_empty_rest_of_line (); | |
17420 | } | |
17421 | ||
17422 | /* Parse a register string into a number. Called from the ECOFF code | |
17423 | to parse .frame. The argument is non-zero if this is the frame | |
17424 | register, so that we can record it in mips_frame_reg. */ | |
17425 | ||
17426 | int | |
17a2f251 | 17427 | tc_get_register (int frame) |
252b5132 | 17428 | { |
707bfff6 | 17429 | unsigned int reg; |
252b5132 RH |
17430 | |
17431 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17432 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17433 | reg = 0; | |
252b5132 | 17434 | if (frame) |
7a621144 DJ |
17435 | { |
17436 | mips_frame_reg = reg != 0 ? reg : SP; | |
17437 | mips_frame_reg_valid = 1; | |
17438 | mips_cprestore_valid = 0; | |
17439 | } | |
252b5132 RH |
17440 | return reg; |
17441 | } | |
17442 | ||
17443 | valueT | |
17a2f251 | 17444 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17445 | { |
17446 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17447 | ||
b4c71f56 TS |
17448 | if (IS_ELF) |
17449 | { | |
17450 | /* We don't need to align ELF sections to the full alignment. | |
17451 | However, Irix 5 may prefer that we align them at least to a 16 | |
17452 | byte boundary. We don't bother to align the sections if we | |
17453 | are targeted for an embedded system. */ | |
c41e87e3 | 17454 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17455 | return addr; |
17456 | if (align > 4) | |
17457 | align = 4; | |
17458 | } | |
252b5132 RH |
17459 | |
17460 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17461 | } | |
17462 | ||
17463 | /* Utility routine, called from above as well. If called while the | |
17464 | input file is still being read, it's only an approximation. (For | |
17465 | example, a symbol may later become defined which appeared to be | |
17466 | undefined earlier.) */ | |
17467 | ||
17468 | static int | |
17a2f251 | 17469 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17470 | { |
17471 | if (sym == 0) | |
17472 | return 0; | |
17473 | ||
4d0d148d | 17474 | if (g_switch_value > 0) |
252b5132 RH |
17475 | { |
17476 | const char *symname; | |
17477 | int change; | |
17478 | ||
c9914766 | 17479 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17480 | register. It can be if it is smaller than the -G size or if |
17481 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17482 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17483 | they can. */ |
17484 | symname = S_GET_NAME (sym); | |
17485 | if (symname != (const char *) NULL | |
17486 | && (strcmp (symname, "eprol") == 0 | |
17487 | || strcmp (symname, "etext") == 0 | |
17488 | || strcmp (symname, "_gp") == 0 | |
17489 | || strcmp (symname, "edata") == 0 | |
17490 | || strcmp (symname, "_fbss") == 0 | |
17491 | || strcmp (symname, "_fdata") == 0 | |
17492 | || strcmp (symname, "_ftext") == 0 | |
17493 | || strcmp (symname, "end") == 0 | |
17494 | || strcmp (symname, "_gp_disp") == 0)) | |
17495 | change = 1; | |
17496 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17497 | && (0 | |
17498 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17499 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17500 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17501 | <= g_switch_value)) | |
252b5132 RH |
17502 | #endif |
17503 | /* We must defer this decision until after the whole | |
17504 | file has been read, since there might be a .extern | |
17505 | after the first use of this symbol. */ | |
17506 | || (before_relaxing | |
17507 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17508 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17509 | #endif |
17510 | && S_GET_VALUE (sym) == 0) | |
17511 | || (S_GET_VALUE (sym) != 0 | |
17512 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17513 | change = 0; | |
17514 | else | |
17515 | { | |
17516 | const char *segname; | |
17517 | ||
17518 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17519 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17520 | && strcmp (segname, ".lit4") != 0); |
17521 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17522 | && strcmp (segname, ".sbss") != 0 |
17523 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17524 | && strncmp (segname, ".sbss.", 6) != 0 |
17525 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17526 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17527 | } |
17528 | return change; | |
17529 | } | |
17530 | else | |
c9914766 | 17531 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17532 | return 1; |
17533 | } | |
17534 | ||
5919d012 RS |
17535 | |
17536 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17537 | ||
17538 | static bfd_boolean | |
17a2f251 | 17539 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17540 | { |
17541 | asection *symsec; | |
5919d012 RS |
17542 | |
17543 | /* Handle the case of a symbol equated to another symbol. */ | |
17544 | while (symbol_equated_reloc_p (sym)) | |
17545 | { | |
17546 | symbolS *n; | |
17547 | ||
5f0fe04b | 17548 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17549 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17550 | if (n == sym) | |
17551 | break; | |
17552 | sym = n; | |
17553 | } | |
17554 | ||
df1f3cda DD |
17555 | if (symbol_section_p (sym)) |
17556 | return TRUE; | |
17557 | ||
5919d012 RS |
17558 | symsec = S_GET_SEGMENT (sym); |
17559 | ||
5919d012 | 17560 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17561 | return (!bfd_is_und_section (symsec) |
17562 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17563 | && !bfd_is_com_section (symsec) |
17564 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17565 | #ifdef OBJ_ELF |
17566 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17567 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17568 | #endif |
17569 | ); | |
17570 | } | |
17571 | ||
17572 | ||
252b5132 RH |
17573 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17574 | extended opcode. SEC is the section the frag is in. */ | |
17575 | ||
17576 | static int | |
17a2f251 | 17577 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17578 | { |
17579 | int type; | |
3994f87e | 17580 | const struct mips16_immed_operand *op; |
252b5132 RH |
17581 | offsetT val; |
17582 | int mintiny, maxtiny; | |
17583 | segT symsec; | |
98aa84af | 17584 | fragS *sym_frag; |
252b5132 RH |
17585 | |
17586 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17587 | return 0; | |
17588 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17589 | return 1; | |
17590 | ||
17591 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17592 | op = mips16_immed_operands; | |
17593 | while (op->type != type) | |
17594 | { | |
17595 | ++op; | |
9c2799c2 | 17596 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17597 | } |
17598 | ||
17599 | if (op->unsp) | |
17600 | { | |
17601 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17602 | { | |
17603 | mintiny = 1; | |
17604 | maxtiny = 1 << op->nbits; | |
17605 | } | |
17606 | else | |
17607 | { | |
17608 | mintiny = 0; | |
17609 | maxtiny = (1 << op->nbits) - 1; | |
17610 | } | |
17611 | } | |
17612 | else | |
17613 | { | |
17614 | mintiny = - (1 << (op->nbits - 1)); | |
17615 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17616 | } | |
17617 | ||
98aa84af | 17618 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17619 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17620 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17621 | |
17622 | if (op->pcrel) | |
17623 | { | |
17624 | addressT addr; | |
17625 | ||
17626 | /* We won't have the section when we are called from | |
17627 | mips_relax_frag. However, we will always have been called | |
17628 | from md_estimate_size_before_relax first. If this is a | |
17629 | branch to a different section, we mark it as such. If SEC is | |
17630 | NULL, and the frag is not marked, then it must be a branch to | |
17631 | the same section. */ | |
17632 | if (sec == NULL) | |
17633 | { | |
17634 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17635 | return 1; | |
17636 | } | |
17637 | else | |
17638 | { | |
98aa84af | 17639 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17640 | if (symsec != sec) |
17641 | { | |
17642 | fragp->fr_subtype = | |
17643 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17644 | ||
17645 | /* FIXME: We should support this, and let the linker | |
17646 | catch branches and loads that are out of range. */ | |
17647 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17648 | _("unsupported PC relative reference to different section")); | |
17649 | ||
17650 | return 1; | |
17651 | } | |
98aa84af AM |
17652 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17653 | /* Assume non-extended on the first relaxation pass. | |
17654 | The address we have calculated will be bogus if this is | |
17655 | a forward branch to another frag, as the forward frag | |
17656 | will have fr_address == 0. */ | |
17657 | return 0; | |
252b5132 RH |
17658 | } |
17659 | ||
17660 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17661 | the same section. If the relax_marker of the symbol fragment |
17662 | differs from the relax_marker of this fragment, we have not | |
17663 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17664 | in STRETCH in order to get a better estimate of the address. |
17665 | This particularly matters because of the shift bits. */ | |
17666 | if (stretch != 0 | |
98aa84af | 17667 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17668 | { |
17669 | fragS *f; | |
17670 | ||
17671 | /* Adjust stretch for any alignment frag. Note that if have | |
17672 | been expanding the earlier code, the symbol may be | |
17673 | defined in what appears to be an earlier frag. FIXME: | |
17674 | This doesn't handle the fr_subtype field, which specifies | |
17675 | a maximum number of bytes to skip when doing an | |
17676 | alignment. */ | |
98aa84af | 17677 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17678 | { |
17679 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17680 | { | |
17681 | if (stretch < 0) | |
17682 | stretch = - ((- stretch) | |
17683 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17684 | else | |
17685 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17686 | if (stretch == 0) | |
17687 | break; | |
17688 | } | |
17689 | } | |
17690 | if (f != NULL) | |
17691 | val += stretch; | |
17692 | } | |
17693 | ||
17694 | addr = fragp->fr_address + fragp->fr_fix; | |
17695 | ||
17696 | /* The base address rules are complicated. The base address of | |
17697 | a branch is the following instruction. The base address of a | |
17698 | PC relative load or add is the instruction itself, but if it | |
17699 | is in a delay slot (in which case it can not be extended) use | |
17700 | the address of the instruction whose delay slot it is in. */ | |
17701 | if (type == 'p' || type == 'q') | |
17702 | { | |
17703 | addr += 2; | |
17704 | ||
17705 | /* If we are currently assuming that this frag should be | |
17706 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17707 | higher. */ |
252b5132 RH |
17708 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17709 | addr += 2; | |
17710 | ||
17711 | /* Ignore the low bit in the target, since it will be set | |
17712 | for a text label. */ | |
17713 | if ((val & 1) != 0) | |
17714 | --val; | |
17715 | } | |
17716 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17717 | addr -= 4; | |
17718 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17719 | addr -= 2; | |
17720 | ||
17721 | val -= addr & ~ ((1 << op->shift) - 1); | |
17722 | ||
17723 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17724 | if (type == 'p' || type == 'q') | |
17725 | val /= 2; | |
17726 | ||
17727 | /* If any of the shifted bits are set, we must use an extended | |
17728 | opcode. If the address depends on the size of this | |
17729 | instruction, this can lead to a loop, so we arrange to always | |
17730 | use an extended opcode. We only check this when we are in | |
17731 | the main relaxation loop, when SEC is NULL. */ | |
17732 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17733 | { | |
17734 | fragp->fr_subtype = | |
17735 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17736 | return 1; | |
17737 | } | |
17738 | ||
17739 | /* If we are about to mark a frag as extended because the value | |
17740 | is precisely maxtiny + 1, then there is a chance of an | |
17741 | infinite loop as in the following code: | |
17742 | la $4,foo | |
17743 | .skip 1020 | |
17744 | .align 2 | |
17745 | foo: | |
17746 | In this case when the la is extended, foo is 0x3fc bytes | |
17747 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17748 | the la must be extended. To avoid this loop, we mark the | |
17749 | frag as extended if it was small, and is about to become | |
17750 | extended with a value of maxtiny + 1. */ | |
17751 | if (val == ((maxtiny + 1) << op->shift) | |
17752 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17753 | && sec == NULL) | |
17754 | { | |
17755 | fragp->fr_subtype = | |
17756 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17757 | return 1; | |
17758 | } | |
17759 | } | |
17760 | else if (symsec != absolute_section && sec != NULL) | |
17761 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17762 | ||
17763 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17764 | || val < (mintiny << op->shift) | |
17765 | || val > (maxtiny << op->shift)) | |
17766 | return 1; | |
17767 | else | |
17768 | return 0; | |
17769 | } | |
17770 | ||
4a6a3df4 AO |
17771 | /* Compute the length of a branch sequence, and adjust the |
17772 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17773 | worst-case length is computed, with UPDATE being used to indicate | |
17774 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17775 | branch is to be computed. */ | |
17776 | static int | |
17a2f251 | 17777 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17778 | { |
b34976b6 | 17779 | bfd_boolean toofar; |
4a6a3df4 AO |
17780 | int length; |
17781 | ||
17782 | if (fragp | |
17783 | && S_IS_DEFINED (fragp->fr_symbol) | |
17784 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17785 | { | |
17786 | addressT addr; | |
17787 | offsetT val; | |
17788 | ||
17789 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17790 | ||
17791 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17792 | ||
17793 | val -= addr; | |
17794 | ||
17795 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17796 | } | |
17797 | else if (fragp) | |
17798 | /* If the symbol is not defined or it's in a different segment, | |
17799 | assume the user knows what's going on and emit a short | |
17800 | branch. */ | |
b34976b6 | 17801 | toofar = FALSE; |
4a6a3df4 | 17802 | else |
b34976b6 | 17803 | toofar = TRUE; |
4a6a3df4 AO |
17804 | |
17805 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17806 | fragp->fr_subtype | |
66b3e8da MR |
17807 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17808 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17809 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17810 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17811 | toofar); | |
17812 | ||
17813 | length = 4; | |
17814 | if (toofar) | |
17815 | { | |
17816 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17817 | length += 8; | |
17818 | ||
17819 | if (mips_pic != NO_PIC) | |
17820 | { | |
17821 | /* Additional space for PIC loading of target address. */ | |
17822 | length += 8; | |
17823 | if (mips_opts.isa == ISA_MIPS1) | |
17824 | /* Additional space for $at-stabilizing nop. */ | |
17825 | length += 4; | |
17826 | } | |
17827 | ||
17828 | /* If branch is conditional. */ | |
17829 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17830 | length += 8; | |
17831 | } | |
b34976b6 | 17832 | |
4a6a3df4 AO |
17833 | return length; |
17834 | } | |
17835 | ||
df58fc94 RS |
17836 | /* Compute the length of a branch sequence, and adjust the |
17837 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17838 | worst-case length is computed, with UPDATE being used to indicate | |
17839 | whether an unconditional (-1), or regular (0) branch is to be | |
17840 | computed. */ | |
17841 | ||
17842 | static int | |
17843 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17844 | { | |
17845 | bfd_boolean toofar; | |
17846 | int length; | |
17847 | ||
17848 | if (fragp | |
17849 | && S_IS_DEFINED (fragp->fr_symbol) | |
17850 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17851 | { | |
17852 | addressT addr; | |
17853 | offsetT val; | |
17854 | ||
17855 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17856 | /* Ignore the low bit in the target, since it will be set | |
17857 | for a text label. */ | |
17858 | if ((val & 1) != 0) | |
17859 | --val; | |
17860 | ||
17861 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17862 | ||
17863 | val -= addr; | |
17864 | ||
17865 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17866 | } | |
17867 | else if (fragp) | |
17868 | /* If the symbol is not defined or it's in a different segment, | |
17869 | assume the user knows what's going on and emit a short | |
17870 | branch. */ | |
17871 | toofar = FALSE; | |
17872 | else | |
17873 | toofar = TRUE; | |
17874 | ||
17875 | if (fragp && update | |
17876 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17877 | fragp->fr_subtype = (toofar | |
17878 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17879 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17880 | ||
17881 | length = 4; | |
17882 | if (toofar) | |
17883 | { | |
17884 | bfd_boolean compact_known = fragp != NULL; | |
17885 | bfd_boolean compact = FALSE; | |
17886 | bfd_boolean uncond; | |
17887 | ||
17888 | if (compact_known) | |
17889 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17890 | if (fragp) | |
17891 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17892 | else | |
17893 | uncond = update < 0; | |
17894 | ||
17895 | /* If label is out of range, we turn branch <br>: | |
17896 | ||
17897 | <br> label # 4 bytes | |
17898 | 0: | |
17899 | ||
17900 | into: | |
17901 | ||
17902 | j label # 4 bytes | |
17903 | nop # 2 bytes if compact && !PIC | |
17904 | 0: | |
17905 | */ | |
17906 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17907 | length += 2; | |
17908 | ||
17909 | /* If assembling PIC code, we further turn: | |
17910 | ||
17911 | j label # 4 bytes | |
17912 | ||
17913 | into: | |
17914 | ||
17915 | lw/ld at, %got(label)(gp) # 4 bytes | |
17916 | d/addiu at, %lo(label) # 4 bytes | |
17917 | jr/c at # 2 bytes | |
17918 | */ | |
17919 | if (mips_pic != NO_PIC) | |
17920 | length += 6; | |
17921 | ||
17922 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17923 | ||
17924 | <brneg> 0f # 4 bytes | |
17925 | nop # 2 bytes if !compact | |
17926 | */ | |
17927 | if (!uncond) | |
17928 | length += (compact_known && compact) ? 4 : 6; | |
17929 | } | |
17930 | ||
17931 | return length; | |
17932 | } | |
17933 | ||
17934 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17935 | bit accordingly. */ | |
17936 | ||
17937 | static int | |
17938 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17939 | { | |
17940 | bfd_boolean toofar; | |
17941 | ||
df58fc94 RS |
17942 | if (fragp |
17943 | && S_IS_DEFINED (fragp->fr_symbol) | |
17944 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17945 | { | |
17946 | addressT addr; | |
17947 | offsetT val; | |
17948 | int type; | |
17949 | ||
17950 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17951 | /* Ignore the low bit in the target, since it will be set | |
17952 | for a text label. */ | |
17953 | if ((val & 1) != 0) | |
17954 | --val; | |
17955 | ||
17956 | /* Assume this is a 2-byte branch. */ | |
17957 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17958 | ||
17959 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17960 | long branches. */ | |
17961 | ||
17962 | val -= addr; | |
17963 | ||
17964 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17965 | if (type == 'D') | |
17966 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17967 | else if (type == 'E') | |
17968 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17969 | else | |
17970 | abort (); | |
17971 | } | |
17972 | else | |
17973 | /* If the symbol is not defined or it's in a different segment, | |
17974 | we emit a normal 32-bit branch. */ | |
17975 | toofar = TRUE; | |
17976 | ||
17977 | if (fragp && update | |
17978 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17979 | fragp->fr_subtype | |
17980 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17981 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17982 | ||
17983 | if (toofar) | |
17984 | return 4; | |
17985 | ||
17986 | return 2; | |
17987 | } | |
17988 | ||
252b5132 RH |
17989 | /* Estimate the size of a frag before relaxing. Unless this is the |
17990 | mips16, we are not really relaxing here, and the final size is | |
17991 | encoded in the subtype information. For the mips16, we have to | |
17992 | decide whether we are using an extended opcode or not. */ | |
17993 | ||
252b5132 | 17994 | int |
17a2f251 | 17995 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17996 | { |
5919d012 | 17997 | int change; |
252b5132 | 17998 | |
4a6a3df4 AO |
17999 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18000 | { | |
18001 | ||
b34976b6 AM |
18002 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18003 | ||
4a6a3df4 AO |
18004 | return fragp->fr_var; |
18005 | } | |
18006 | ||
252b5132 | 18007 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
18008 | /* We don't want to modify the EXTENDED bit here; it might get us |
18009 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18010 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 18011 | |
df58fc94 RS |
18012 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18013 | { | |
18014 | int length = 4; | |
18015 | ||
18016 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18017 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18018 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18019 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18020 | fragp->fr_var = length; | |
18021 | ||
18022 | return length; | |
18023 | } | |
18024 | ||
252b5132 | 18025 | if (mips_pic == NO_PIC) |
5919d012 | 18026 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 18027 | else if (mips_pic == SVR4_PIC) |
5919d012 | 18028 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
18029 | else if (mips_pic == VXWORKS_PIC) |
18030 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
18031 | change = 0; | |
252b5132 RH |
18032 | else |
18033 | abort (); | |
18034 | ||
18035 | if (change) | |
18036 | { | |
4d7206a2 | 18037 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18038 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18039 | } |
4d7206a2 RS |
18040 | else |
18041 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18042 | } |
18043 | ||
18044 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18045 | should be converted into a reloc against a section. */ |
252b5132 RH |
18046 | |
18047 | int | |
17a2f251 | 18048 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18049 | { |
252b5132 RH |
18050 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18051 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18052 | return 0; | |
a161fe53 | 18053 | |
252b5132 RH |
18054 | if (fixp->fx_addsy == NULL) |
18055 | return 1; | |
a161fe53 | 18056 | |
de7e6852 RS |
18057 | /* If symbol SYM is in a mergeable section, relocations of the form |
18058 | SYM + 0 can usually be made section-relative. The mergeable data | |
18059 | is then identified by the section offset rather than by the symbol. | |
18060 | ||
18061 | However, if we're generating REL LO16 relocations, the offset is split | |
18062 | between the LO16 and parterning high part relocation. The linker will | |
18063 | need to recalculate the complete offset in order to correctly identify | |
18064 | the merge data. | |
18065 | ||
18066 | The linker has traditionally not looked for the parterning high part | |
18067 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
18068 | placed anywhere. Rather than break backwards compatibility by changing | |
18069 | this, it seems better not to force the issue, and instead keep the | |
18070 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18071 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18072 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18073 | && HAVE_IN_PLACE_ADDENDS |
18074 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18075 | return 0; | |
18076 | ||
ce70d90a | 18077 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
18078 | Likewise an in-range offset of limited PC-relative relocations may |
18079 | overflow the in-place relocatable field if recalculated against the | |
18080 | start address of the symbol's containing section. */ | |
ce70d90a | 18081 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
18082 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
18083 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
18084 | return 0; |
18085 | ||
252b5132 | 18086 | #ifdef OBJ_ELF |
b314ec0e RS |
18087 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18088 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18089 | relocations against MIPS16 functions; in this case, the stub becomes | |
18090 | the function's canonical address. | |
18091 | ||
18092 | Floating-point stubs are stored in unique .mips16.call.* or | |
18093 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18094 | the first relocation in section S must be against F; this is how the | |
18095 | linker determines the target function. All relocations that might | |
18096 | resolve to T must also be against F. We therefore have the following | |
18097 | restrictions, which are given in an intentionally-redundant way: | |
18098 | ||
18099 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18100 | symbols. | |
18101 | ||
18102 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18103 | if that stub might be used. | |
18104 | ||
18105 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18106 | symbols. | |
18107 | ||
18108 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18109 | that stub might be used. | |
18110 | ||
18111 | There is a further restriction: | |
18112 | ||
df58fc94 RS |
18113 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
18114 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
18115 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
18116 | encode the low bit. |
18117 | ||
df58fc94 RS |
18118 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
18119 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
18120 | such relocations on REL targets. | |
b314ec0e RS |
18121 | |
18122 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18123 | relocation against some symbol R, no relocation against R may be | |
18124 | reduced. (Note that this deals with (2) as well as (1) because | |
18125 | relocations against global symbols will never be reduced on ELF | |
18126 | targets.) This approach is a little simpler than trying to detect | |
18127 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18128 | that we have for MIPS16 symbols. */ | |
f43abd2b | 18129 | if (IS_ELF |
b314ec0e | 18130 | && fixp->fx_subsy == NULL |
30c09090 | 18131 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
18132 | || *symbol_get_tc (fixp->fx_addsy) |
18133 | || (HAVE_IN_PLACE_ADDENDS | |
18134 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
18135 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
18136 | return 0; |
18137 | #endif | |
a161fe53 | 18138 | |
252b5132 RH |
18139 | return 1; |
18140 | } | |
18141 | ||
18142 | /* Translate internal representation of relocation info to BFD target | |
18143 | format. */ | |
18144 | ||
18145 | arelent ** | |
17a2f251 | 18146 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18147 | { |
18148 | static arelent *retval[4]; | |
18149 | arelent *reloc; | |
18150 | bfd_reloc_code_real_type code; | |
18151 | ||
4b0cff4e TS |
18152 | memset (retval, 0, sizeof(retval)); |
18153 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
18154 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
18155 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
18156 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18157 | ||
bad36eac DJ |
18158 | if (fixp->fx_pcrel) |
18159 | { | |
df58fc94 RS |
18160 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18161 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18162 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18163 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18164 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18165 | |
18166 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18167 | Relocations want only the symbol offset. */ | |
18168 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 18169 | if (!IS_ELF) |
bad36eac DJ |
18170 | { |
18171 | /* A gruesome hack which is a result of the gruesome gas | |
18172 | reloc handling. What's worse, for COFF (as opposed to | |
18173 | ECOFF), we might need yet another copy of reloc->address. | |
18174 | See bfd_install_relocation. */ | |
18175 | reloc->addend += reloc->address; | |
18176 | } | |
18177 | } | |
18178 | else | |
18179 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18180 | |
438c16b8 TS |
18181 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18182 | entry to be used in the relocation's section offset. */ | |
18183 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18184 | { |
18185 | reloc->address = reloc->addend; | |
18186 | reloc->addend = 0; | |
18187 | } | |
18188 | ||
252b5132 | 18189 | code = fixp->fx_r_type; |
252b5132 | 18190 | |
bad36eac | 18191 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18192 | if (reloc->howto == NULL) |
18193 | { | |
18194 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18195 | _("Can not represent %s relocation in this object file format"), | |
18196 | bfd_get_reloc_code_name (code)); | |
18197 | retval[0] = NULL; | |
18198 | } | |
18199 | ||
18200 | return retval; | |
18201 | } | |
18202 | ||
18203 | /* Relax a machine dependent frag. This returns the amount by which | |
18204 | the current size of the frag should change. */ | |
18205 | ||
18206 | int | |
17a2f251 | 18207 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18208 | { |
4a6a3df4 AO |
18209 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18210 | { | |
18211 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18212 | |
18213 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18214 | |
18215 | return fragp->fr_var - old_var; | |
18216 | } | |
18217 | ||
df58fc94 RS |
18218 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18219 | { | |
18220 | offsetT old_var = fragp->fr_var; | |
18221 | offsetT new_var = 4; | |
18222 | ||
18223 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18224 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18225 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18226 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18227 | fragp->fr_var = new_var; | |
18228 | ||
18229 | return new_var - old_var; | |
18230 | } | |
18231 | ||
252b5132 RH |
18232 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18233 | return 0; | |
18234 | ||
c4e7957c | 18235 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18236 | { |
18237 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18238 | return 0; | |
18239 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18240 | return 2; | |
18241 | } | |
18242 | else | |
18243 | { | |
18244 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18245 | return 0; | |
18246 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18247 | return -2; | |
18248 | } | |
18249 | ||
18250 | return 0; | |
18251 | } | |
18252 | ||
18253 | /* Convert a machine dependent frag. */ | |
18254 | ||
18255 | void | |
17a2f251 | 18256 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18257 | { |
4a6a3df4 AO |
18258 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18259 | { | |
4d68580a | 18260 | char *buf; |
4a6a3df4 AO |
18261 | unsigned long insn; |
18262 | expressionS exp; | |
18263 | fixS *fixp; | |
b34976b6 | 18264 | |
4d68580a RS |
18265 | buf = fragp->fr_literal + fragp->fr_fix; |
18266 | insn = read_insn (buf); | |
b34976b6 | 18267 | |
4a6a3df4 AO |
18268 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18269 | { | |
18270 | /* We generate a fixup instead of applying it right now | |
18271 | because, if there are linker relaxations, we're going to | |
18272 | need the relocations. */ | |
18273 | exp.X_op = O_symbol; | |
18274 | exp.X_add_symbol = fragp->fr_symbol; | |
18275 | exp.X_add_number = fragp->fr_offset; | |
18276 | ||
4d68580a RS |
18277 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18278 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18279 | fixp->fx_file = fragp->fr_file; |
18280 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18281 | |
4d68580a | 18282 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18283 | } |
18284 | else | |
18285 | { | |
18286 | int i; | |
18287 | ||
18288 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18289 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18290 | |
18291 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18292 | goto uncond; | |
18293 | ||
18294 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18295 | { | |
18296 | /* Reverse the branch. */ | |
18297 | switch ((insn >> 28) & 0xf) | |
18298 | { | |
18299 | case 4: | |
3bf0dbfb MR |
18300 | /* bc[0-3][tf]l? instructions can have the condition |
18301 | reversed by tweaking a single TF bit, and their | |
18302 | opcodes all have 0x4???????. */ | |
18303 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18304 | insn ^= 0x00010000; |
18305 | break; | |
18306 | ||
18307 | case 0: | |
18308 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18309 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18310 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18311 | insn ^= 0x00010000; |
18312 | break; | |
b34976b6 | 18313 | |
4a6a3df4 AO |
18314 | case 1: |
18315 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18316 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18317 | insn ^= 0x04000000; |
18318 | break; | |
18319 | ||
18320 | default: | |
18321 | abort (); | |
18322 | } | |
18323 | } | |
18324 | ||
18325 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18326 | { | |
18327 | /* Clear the and-link bit. */ | |
9c2799c2 | 18328 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18329 | |
54f4ddb3 TS |
18330 | /* bltzal 0x04100000 bgezal 0x04110000 |
18331 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18332 | insn &= ~0x00100000; |
18333 | } | |
18334 | ||
18335 | /* Branch over the branch (if the branch was likely) or the | |
18336 | full jump (not likely case). Compute the offset from the | |
18337 | current instruction to branch to. */ | |
18338 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18339 | i = 16; | |
18340 | else | |
18341 | { | |
18342 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18343 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18344 | /* How many bytes in instructions from here to the end? */ |
18345 | i = fragp->fr_var - i; | |
18346 | } | |
18347 | /* Convert to instruction count. */ | |
18348 | i >>= 2; | |
18349 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18350 | i--; |
4a6a3df4 AO |
18351 | insn |= i; |
18352 | /* Branch over the jump. */ | |
4d68580a | 18353 | buf = write_insn (buf, insn); |
4a6a3df4 | 18354 | |
54f4ddb3 | 18355 | /* nop */ |
4d68580a | 18356 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18357 | |
18358 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18359 | { | |
18360 | /* beql $0, $0, 2f */ | |
18361 | insn = 0x50000000; | |
18362 | /* Compute the PC offset from the current instruction to | |
18363 | the end of the variable frag. */ | |
18364 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18365 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18366 | /* How many bytes in instructions from here to the end? */ |
18367 | i = fragp->fr_var - i; | |
18368 | /* Convert to instruction count. */ | |
18369 | i >>= 2; | |
18370 | /* Don't decrement i, because we want to branch over the | |
18371 | delay slot. */ | |
4a6a3df4 | 18372 | insn |= i; |
4a6a3df4 | 18373 | |
4d68580a RS |
18374 | buf = write_insn (buf, insn); |
18375 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18376 | } |
18377 | ||
18378 | uncond: | |
18379 | if (mips_pic == NO_PIC) | |
18380 | { | |
18381 | /* j or jal. */ | |
18382 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18383 | ? 0x0c000000 : 0x08000000); | |
18384 | exp.X_op = O_symbol; | |
18385 | exp.X_add_symbol = fragp->fr_symbol; | |
18386 | exp.X_add_number = fragp->fr_offset; | |
18387 | ||
4d68580a RS |
18388 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18389 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18390 | fixp->fx_file = fragp->fr_file; |
18391 | fixp->fx_line = fragp->fr_line; | |
18392 | ||
4d68580a | 18393 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18394 | } |
18395 | else | |
18396 | { | |
66b3e8da MR |
18397 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18398 | ||
4a6a3df4 | 18399 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18400 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18401 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18402 | exp.X_op = O_symbol; |
18403 | exp.X_add_symbol = fragp->fr_symbol; | |
18404 | exp.X_add_number = fragp->fr_offset; | |
18405 | ||
18406 | if (fragp->fr_offset) | |
18407 | { | |
18408 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18409 | exp.X_add_number = 0; | |
18410 | } | |
18411 | ||
4d68580a RS |
18412 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18413 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18414 | fixp->fx_file = fragp->fr_file; |
18415 | fixp->fx_line = fragp->fr_line; | |
18416 | ||
4d68580a | 18417 | buf = write_insn (buf, insn); |
b34976b6 | 18418 | |
4a6a3df4 | 18419 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18420 | /* nop */ |
18421 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18422 | |
18423 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18424 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18425 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18426 | |
4d68580a RS |
18427 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18428 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18429 | fixp->fx_file = fragp->fr_file; |
18430 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18431 | |
4d68580a | 18432 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18433 | |
18434 | /* j(al)r $at. */ | |
18435 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18436 | insn = 0x0000f809; |
4a6a3df4 | 18437 | else |
66b3e8da MR |
18438 | insn = 0x00000008; |
18439 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18440 | |
4d68580a | 18441 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18442 | } |
18443 | } | |
18444 | ||
4a6a3df4 | 18445 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18446 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18447 | return; |
18448 | } | |
18449 | ||
df58fc94 RS |
18450 | /* Relax microMIPS branches. */ |
18451 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18452 | { | |
4d68580a | 18453 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18454 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18455 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18456 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18457 | bfd_boolean short_ds; |
df58fc94 RS |
18458 | unsigned long insn; |
18459 | expressionS exp; | |
18460 | fixS *fixp; | |
18461 | ||
18462 | exp.X_op = O_symbol; | |
18463 | exp.X_add_symbol = fragp->fr_symbol; | |
18464 | exp.X_add_number = fragp->fr_offset; | |
18465 | ||
18466 | fragp->fr_fix += fragp->fr_var; | |
18467 | ||
18468 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18469 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18470 | { | |
18471 | /* We generate a fixup instead of applying it right now, | |
18472 | because if there is linker relaxation, we're going to | |
18473 | need the relocations. */ | |
18474 | if (type == 'D') | |
4d68580a | 18475 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18476 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18477 | else if (type == 'E') | |
4d68580a | 18478 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18479 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18480 | else | |
18481 | abort (); | |
18482 | ||
18483 | fixp->fx_file = fragp->fr_file; | |
18484 | fixp->fx_line = fragp->fr_line; | |
18485 | ||
18486 | /* These relocations can have an addend that won't fit in | |
18487 | 2 octets. */ | |
18488 | fixp->fx_no_overflow = 1; | |
18489 | ||
18490 | return; | |
18491 | } | |
18492 | ||
2309ddf2 | 18493 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18494 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18495 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18496 | { | |
18497 | /* We generate a fixup instead of applying it right now, | |
18498 | because if there is linker relaxation, we're going to | |
18499 | need the relocations. */ | |
4d68580a RS |
18500 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18501 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18502 | fixp->fx_file = fragp->fr_file; |
18503 | fixp->fx_line = fragp->fr_line; | |
18504 | ||
18505 | if (type == 0) | |
18506 | return; | |
18507 | } | |
18508 | ||
18509 | /* Relax 16-bit branches to 32-bit branches. */ | |
18510 | if (type != 0) | |
18511 | { | |
4d68580a | 18512 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18513 | |
18514 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18515 | insn = 0x94000000; /* beq */ | |
18516 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18517 | { | |
18518 | unsigned long regno; | |
18519 | ||
18520 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18521 | regno = micromips_to_32_reg_d_map [regno]; | |
18522 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18523 | insn |= regno << MICROMIPSOP_SH_RS; | |
18524 | } | |
18525 | else | |
18526 | abort (); | |
18527 | ||
18528 | /* Nothing else to do, just write it out. */ | |
18529 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18530 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18531 | { | |
4d68580a RS |
18532 | buf = write_compressed_insn (buf, insn, 4); |
18533 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18534 | return; |
18535 | } | |
18536 | } | |
18537 | else | |
4d68580a | 18538 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18539 | |
18540 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18541 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18542 | _("Relaxed out-of-range branch into a jump")); | |
18543 | ||
2309ddf2 MR |
18544 | /* Set the short-delay-slot bit. */ |
18545 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18546 | |
18547 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18548 | { | |
18549 | symbolS *l; | |
18550 | ||
18551 | /* Reverse the branch. */ | |
18552 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18553 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18554 | insn ^= 0x20000000; | |
18555 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18556 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18557 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18558 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18559 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18560 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18561 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18562 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18563 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18564 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18565 | insn ^= 0x00400000; | |
18566 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18567 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18568 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18569 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18570 | insn ^= 0x00200000; | |
18571 | else | |
18572 | abort (); | |
18573 | ||
18574 | if (al) | |
18575 | { | |
18576 | /* Clear the and-link and short-delay-slot bits. */ | |
18577 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18578 | ||
18579 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18580 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18581 | insn &= ~0x02200000; | |
18582 | } | |
18583 | ||
18584 | /* Make a label at the end for use with the branch. */ | |
18585 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18586 | micromips_label_inc (); | |
18587 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18588 | if (IS_ELF) | |
18589 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18590 | #endif | |
18591 | ||
18592 | /* Refer to it. */ | |
4d68580a RS |
18593 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18594 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18595 | fixp->fx_file = fragp->fr_file; |
18596 | fixp->fx_line = fragp->fr_line; | |
18597 | ||
18598 | /* Branch over the jump. */ | |
4d68580a | 18599 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18600 | if (!compact) |
4d68580a RS |
18601 | /* nop */ |
18602 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18603 | } |
18604 | ||
18605 | if (mips_pic == NO_PIC) | |
18606 | { | |
2309ddf2 MR |
18607 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18608 | ||
df58fc94 RS |
18609 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18610 | insn = al ? jal : 0xd4000000; | |
18611 | ||
4d68580a RS |
18612 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18613 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18614 | fixp->fx_file = fragp->fr_file; |
18615 | fixp->fx_line = fragp->fr_line; | |
18616 | ||
4d68580a | 18617 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18618 | if (compact) |
4d68580a RS |
18619 | /* nop */ |
18620 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18621 | } |
18622 | else | |
18623 | { | |
18624 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18625 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18626 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18627 | |
18628 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18629 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18630 | insn |= at << MICROMIPSOP_SH_RT; | |
18631 | ||
18632 | if (exp.X_add_number) | |
18633 | { | |
18634 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18635 | exp.X_add_number = 0; | |
18636 | } | |
18637 | ||
4d68580a RS |
18638 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18639 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18640 | fixp->fx_file = fragp->fr_file; |
18641 | fixp->fx_line = fragp->fr_line; | |
18642 | ||
4d68580a | 18643 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18644 | |
18645 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18646 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18647 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18648 | ||
4d68580a RS |
18649 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18650 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18651 | fixp->fx_file = fragp->fr_file; |
18652 | fixp->fx_line = fragp->fr_line; | |
18653 | ||
4d68580a | 18654 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18655 | |
18656 | /* jr/jrc/jalr/jalrs $at */ | |
18657 | insn = al ? jalr : jr; | |
18658 | insn |= at << MICROMIPSOP_SH_MJ; | |
18659 | ||
4d68580a | 18660 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18661 | } |
18662 | ||
4d68580a | 18663 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18664 | return; |
18665 | } | |
18666 | ||
252b5132 RH |
18667 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18668 | { | |
18669 | int type; | |
3994f87e | 18670 | const struct mips16_immed_operand *op; |
252b5132 | 18671 | offsetT val; |
5c04167a RS |
18672 | char *buf; |
18673 | unsigned int user_length, length; | |
252b5132 | 18674 | unsigned long insn; |
5c04167a | 18675 | bfd_boolean ext; |
252b5132 RH |
18676 | |
18677 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18678 | op = mips16_immed_operands; | |
18679 | while (op->type != type) | |
18680 | ++op; | |
18681 | ||
5c04167a | 18682 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18683 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18684 | if (op->pcrel) |
18685 | { | |
18686 | addressT addr; | |
18687 | ||
18688 | addr = fragp->fr_address + fragp->fr_fix; | |
18689 | ||
18690 | /* The rules for the base address of a PC relative reloc are | |
18691 | complicated; see mips16_extended_frag. */ | |
18692 | if (type == 'p' || type == 'q') | |
18693 | { | |
18694 | addr += 2; | |
18695 | if (ext) | |
18696 | addr += 2; | |
18697 | /* Ignore the low bit in the target, since it will be | |
18698 | set for a text label. */ | |
18699 | if ((val & 1) != 0) | |
18700 | --val; | |
18701 | } | |
18702 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18703 | addr -= 4; | |
18704 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18705 | addr -= 2; | |
18706 | ||
18707 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18708 | val -= addr; | |
18709 | ||
18710 | /* Make sure the section winds up with the alignment we have | |
18711 | assumed. */ | |
18712 | if (op->shift > 0) | |
18713 | record_alignment (asec, op->shift); | |
18714 | } | |
18715 | ||
18716 | if (ext | |
18717 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18718 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18719 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18720 | _("extended instruction in delay slot")); | |
18721 | ||
5c04167a | 18722 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18723 | |
4d68580a | 18724 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18725 | if (ext) |
18726 | insn |= MIPS16_EXTEND; | |
252b5132 | 18727 | |
5c04167a RS |
18728 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18729 | user_length = 4; | |
18730 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18731 | user_length = 2; | |
18732 | else | |
18733 | user_length = 0; | |
18734 | ||
43c0598f | 18735 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18736 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18737 | |
5c04167a RS |
18738 | length = (ext ? 4 : 2); |
18739 | gas_assert (mips16_opcode_length (insn) == length); | |
18740 | write_compressed_insn (buf, insn, length); | |
18741 | fragp->fr_fix += length; | |
252b5132 RH |
18742 | } |
18743 | else | |
18744 | { | |
df58fc94 RS |
18745 | relax_substateT subtype = fragp->fr_subtype; |
18746 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18747 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18748 | int first, second; |
18749 | fixS *fixp; | |
252b5132 | 18750 | |
df58fc94 RS |
18751 | first = RELAX_FIRST (subtype); |
18752 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18753 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18754 | |
df58fc94 RS |
18755 | /* If the delay slot chosen does not match the size of the instruction, |
18756 | then emit a warning. */ | |
18757 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18758 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18759 | { | |
18760 | relax_substateT s; | |
18761 | const char *msg; | |
18762 | ||
18763 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18764 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18765 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18766 | msg = macro_warning (s); | |
18767 | if (msg != NULL) | |
db9b2be4 | 18768 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18769 | subtype &= ~s; |
18770 | } | |
18771 | ||
584892a6 | 18772 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18773 | if (use_second == second_longer) |
584892a6 | 18774 | { |
df58fc94 RS |
18775 | relax_substateT s; |
18776 | const char *msg; | |
18777 | ||
18778 | s = (subtype | |
18779 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18780 | msg = macro_warning (s); | |
18781 | if (msg != NULL) | |
db9b2be4 | 18782 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18783 | subtype &= ~s; |
584892a6 RS |
18784 | } |
18785 | ||
4d7206a2 RS |
18786 | /* Go through all the fixups for the first sequence. Disable them |
18787 | (by marking them as done) if we're going to use the second | |
18788 | sequence instead. */ | |
18789 | while (fixp | |
18790 | && fixp->fx_frag == fragp | |
18791 | && fixp->fx_where < fragp->fr_fix - second) | |
18792 | { | |
df58fc94 | 18793 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18794 | fixp->fx_done = 1; |
18795 | fixp = fixp->fx_next; | |
18796 | } | |
252b5132 | 18797 | |
4d7206a2 RS |
18798 | /* Go through the fixups for the second sequence. Disable them if |
18799 | we're going to use the first sequence, otherwise adjust their | |
18800 | addresses to account for the relaxation. */ | |
18801 | while (fixp && fixp->fx_frag == fragp) | |
18802 | { | |
df58fc94 | 18803 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18804 | fixp->fx_where -= first; |
18805 | else | |
18806 | fixp->fx_done = 1; | |
18807 | fixp = fixp->fx_next; | |
18808 | } | |
18809 | ||
18810 | /* Now modify the frag contents. */ | |
df58fc94 | 18811 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18812 | { |
18813 | char *start; | |
18814 | ||
18815 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18816 | memmove (start, start + first, second); | |
18817 | fragp->fr_fix -= first; | |
18818 | } | |
18819 | else | |
18820 | fragp->fr_fix -= second; | |
252b5132 RH |
18821 | } |
18822 | } | |
18823 | ||
18824 | #ifdef OBJ_ELF | |
18825 | ||
18826 | /* This function is called after the relocs have been generated. | |
18827 | We've been storing mips16 text labels as odd. Here we convert them | |
18828 | back to even for the convenience of the debugger. */ | |
18829 | ||
18830 | void | |
17a2f251 | 18831 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18832 | { |
18833 | asymbol **syms; | |
18834 | unsigned int count, i; | |
18835 | ||
f43abd2b | 18836 | if (!IS_ELF) |
252b5132 RH |
18837 | return; |
18838 | ||
18839 | syms = bfd_get_outsymbols (stdoutput); | |
18840 | count = bfd_get_symcount (stdoutput); | |
18841 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18842 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18843 | && ((*syms)->value & 1) != 0) | |
18844 | { | |
18845 | (*syms)->value &= ~1; | |
18846 | /* If the symbol has an odd size, it was probably computed | |
18847 | incorrectly, so adjust that as well. */ | |
18848 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18849 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18850 | } | |
252b5132 RH |
18851 | } |
18852 | ||
18853 | #endif | |
18854 | ||
a1facbec MR |
18855 | /* This function is called whenever a label is defined, including fake |
18856 | labels instantiated off the dot special symbol. It is used when | |
18857 | handling branch delays; if a branch has a label, we assume we cannot | |
18858 | move it. This also bumps the value of the symbol by 1 in compressed | |
18859 | code. */ | |
252b5132 | 18860 | |
e1b47bd5 | 18861 | static void |
a1facbec | 18862 | mips_record_label (symbolS *sym) |
252b5132 | 18863 | { |
a8dbcb85 | 18864 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18865 | struct insn_label_list *l; |
18866 | ||
18867 | if (free_insn_labels == NULL) | |
18868 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18869 | else | |
18870 | { | |
18871 | l = free_insn_labels; | |
18872 | free_insn_labels = l->next; | |
18873 | } | |
18874 | ||
18875 | l->label = sym; | |
a8dbcb85 TS |
18876 | l->next = si->label_list; |
18877 | si->label_list = l; | |
a1facbec | 18878 | } |
07a53e5c | 18879 | |
a1facbec MR |
18880 | /* This function is called as tc_frob_label() whenever a label is defined |
18881 | and adds a DWARF-2 record we only want for true labels. */ | |
18882 | ||
18883 | void | |
18884 | mips_define_label (symbolS *sym) | |
18885 | { | |
18886 | mips_record_label (sym); | |
07a53e5c RH |
18887 | #ifdef OBJ_ELF |
18888 | dwarf2_emit_label (sym); | |
18889 | #endif | |
252b5132 | 18890 | } |
e1b47bd5 RS |
18891 | |
18892 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18893 | is defined. */ | |
18894 | ||
18895 | void | |
18896 | mips_add_dot_label (symbolS *sym) | |
18897 | { | |
18898 | mips_record_label (sym); | |
18899 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18900 | mips_compressed_mark_label (sym); | |
18901 | } | |
252b5132 RH |
18902 | \f |
18903 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18904 | ||
18905 | /* Some special processing for a MIPS ELF file. */ | |
18906 | ||
18907 | void | |
17a2f251 | 18908 | mips_elf_final_processing (void) |
252b5132 RH |
18909 | { |
18910 | /* Write out the register information. */ | |
316f5878 | 18911 | if (mips_abi != N64_ABI) |
252b5132 RH |
18912 | { |
18913 | Elf32_RegInfo s; | |
18914 | ||
18915 | s.ri_gprmask = mips_gprmask; | |
18916 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18917 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18918 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18919 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18920 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18921 | ||
18922 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18923 | ((Elf32_External_RegInfo *) | |
18924 | mips_regmask_frag)); | |
18925 | } | |
18926 | else | |
18927 | { | |
18928 | Elf64_Internal_RegInfo s; | |
18929 | ||
18930 | s.ri_gprmask = mips_gprmask; | |
18931 | s.ri_pad = 0; | |
18932 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18933 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18934 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18935 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18936 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18937 | ||
18938 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18939 | ((Elf64_External_RegInfo *) | |
18940 | mips_regmask_frag)); | |
18941 | } | |
18942 | ||
18943 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18944 | sort of BFD interface for this. */ | |
18945 | if (mips_any_noreorder) | |
18946 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18947 | if (mips_pic != NO_PIC) | |
143d77c5 | 18948 | { |
8b828383 | 18949 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18950 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18951 | } | |
18952 | if (mips_abicalls) | |
18953 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18954 | |
b015e599 AP |
18955 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18956 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18957 | if (file_ase_mips16) |
18958 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18959 | if (file_ase_micromips) |
18960 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 18961 | if (file_ase & ASE_MDMX) |
deec1734 | 18962 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18963 | |
bdaaa2e1 | 18964 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18965 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18966 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18967 | else if (mips_abi == O64_ABI) |
252b5132 | 18968 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18969 | else if (mips_abi == EABI_ABI) |
252b5132 | 18970 | { |
316f5878 | 18971 | if (!file_mips_gp32) |
252b5132 RH |
18972 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18973 | else | |
18974 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18975 | } | |
316f5878 | 18976 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18977 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18978 | ||
c9914766 | 18979 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18980 | |
18981 | if (mips_32bitmode) | |
18982 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18983 | |
18984 | #if 0 /* XXX FIXME */ | |
18985 | /* 32 bit code with 64 bit FP registers. */ | |
18986 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18987 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18988 | #endif | |
252b5132 RH |
18989 | } |
18990 | ||
18991 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18992 | \f | |
beae10d5 | 18993 | typedef struct proc { |
9b2f1d35 EC |
18994 | symbolS *func_sym; |
18995 | symbolS *func_end_sym; | |
beae10d5 KH |
18996 | unsigned long reg_mask; |
18997 | unsigned long reg_offset; | |
18998 | unsigned long fpreg_mask; | |
18999 | unsigned long fpreg_offset; | |
19000 | unsigned long frame_offset; | |
19001 | unsigned long frame_reg; | |
19002 | unsigned long pc_reg; | |
19003 | } procS; | |
252b5132 RH |
19004 | |
19005 | static procS cur_proc; | |
19006 | static procS *cur_proc_ptr; | |
19007 | static int numprocs; | |
19008 | ||
df58fc94 RS |
19009 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19010 | as "2", and a normal nop as "0". */ | |
19011 | ||
19012 | #define NOP_OPCODE_MIPS 0 | |
19013 | #define NOP_OPCODE_MIPS16 1 | |
19014 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19015 | |
19016 | char | |
19017 | mips_nop_opcode (void) | |
19018 | { | |
df58fc94 RS |
19019 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19020 | return NOP_OPCODE_MICROMIPS; | |
19021 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19022 | return NOP_OPCODE_MIPS16; | |
19023 | else | |
19024 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19025 | } |
19026 | ||
df58fc94 RS |
19027 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19028 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19029 | |
0a9ef439 | 19030 | void |
17a2f251 | 19031 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19032 | { |
df58fc94 | 19033 | char nop_opcode; |
742a56fe | 19034 | char *p; |
c67a084a NC |
19035 | int bytes, size, excess; |
19036 | valueT opcode; | |
742a56fe | 19037 | |
0a9ef439 RH |
19038 | if (fragp->fr_type != rs_align_code) |
19039 | return; | |
19040 | ||
742a56fe | 19041 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19042 | nop_opcode = *p; |
19043 | switch (nop_opcode) | |
a19d8eb0 | 19044 | { |
df58fc94 RS |
19045 | case NOP_OPCODE_MICROMIPS: |
19046 | opcode = micromips_nop32_insn.insn_opcode; | |
19047 | size = 4; | |
19048 | break; | |
19049 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19050 | opcode = mips16_nop_insn.insn_opcode; |
19051 | size = 2; | |
df58fc94 RS |
19052 | break; |
19053 | case NOP_OPCODE_MIPS: | |
19054 | default: | |
c67a084a NC |
19055 | opcode = nop_insn.insn_opcode; |
19056 | size = 4; | |
df58fc94 | 19057 | break; |
c67a084a | 19058 | } |
a19d8eb0 | 19059 | |
c67a084a NC |
19060 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19061 | excess = bytes % size; | |
df58fc94 RS |
19062 | |
19063 | /* Handle the leading part if we're not inserting a whole number of | |
19064 | instructions, and make it the end of the fixed part of the frag. | |
19065 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19066 | and use zeroes otherwise. */ | |
19067 | gas_assert (excess < 4); | |
19068 | fragp->fr_fix += excess; | |
19069 | switch (excess) | |
c67a084a | 19070 | { |
df58fc94 RS |
19071 | case 3: |
19072 | *p++ = '\0'; | |
19073 | /* Fall through. */ | |
19074 | case 2: | |
19075 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
19076 | { | |
4d68580a | 19077 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19078 | break; |
19079 | } | |
19080 | *p++ = '\0'; | |
19081 | /* Fall through. */ | |
19082 | case 1: | |
19083 | *p++ = '\0'; | |
19084 | /* Fall through. */ | |
19085 | case 0: | |
19086 | break; | |
a19d8eb0 | 19087 | } |
c67a084a NC |
19088 | |
19089 | md_number_to_chars (p, opcode, size); | |
19090 | fragp->fr_var = size; | |
a19d8eb0 CP |
19091 | } |
19092 | ||
252b5132 | 19093 | static void |
17a2f251 | 19094 | md_obj_begin (void) |
252b5132 RH |
19095 | { |
19096 | } | |
19097 | ||
19098 | static void | |
17a2f251 | 19099 | md_obj_end (void) |
252b5132 | 19100 | { |
54f4ddb3 | 19101 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 19102 | if (cur_proc_ptr) |
9a41af64 | 19103 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
19104 | } |
19105 | ||
19106 | static long | |
17a2f251 | 19107 | get_number (void) |
252b5132 RH |
19108 | { |
19109 | int negative = 0; | |
19110 | long val = 0; | |
19111 | ||
19112 | if (*input_line_pointer == '-') | |
19113 | { | |
19114 | ++input_line_pointer; | |
19115 | negative = 1; | |
19116 | } | |
3882b010 | 19117 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19118 | as_bad (_("expected simple number")); |
252b5132 RH |
19119 | if (input_line_pointer[0] == '0') |
19120 | { | |
19121 | if (input_line_pointer[1] == 'x') | |
19122 | { | |
19123 | input_line_pointer += 2; | |
3882b010 | 19124 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19125 | { |
19126 | val <<= 4; | |
19127 | val |= hex_value (*input_line_pointer++); | |
19128 | } | |
19129 | return negative ? -val : val; | |
19130 | } | |
19131 | else | |
19132 | { | |
19133 | ++input_line_pointer; | |
3882b010 | 19134 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19135 | { |
19136 | val <<= 3; | |
19137 | val |= *input_line_pointer++ - '0'; | |
19138 | } | |
19139 | return negative ? -val : val; | |
19140 | } | |
19141 | } | |
3882b010 | 19142 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19143 | { |
19144 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19145 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19146 | as_warn (_("invalid number")); |
252b5132 RH |
19147 | return -1; |
19148 | } | |
3882b010 | 19149 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19150 | { |
19151 | val *= 10; | |
19152 | val += *input_line_pointer++ - '0'; | |
19153 | } | |
19154 | return negative ? -val : val; | |
19155 | } | |
19156 | ||
19157 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19158 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19159 | case .file implies DWARF-2. */ | |
19160 | ||
19161 | static void | |
17a2f251 | 19162 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19163 | { |
ecb4347a DJ |
19164 | static int first_file_directive = 0; |
19165 | ||
c5dd6aab DJ |
19166 | if (ECOFF_DEBUGGING) |
19167 | { | |
19168 | get_number (); | |
19169 | s_app_file (0); | |
19170 | } | |
19171 | else | |
ecb4347a DJ |
19172 | { |
19173 | char *filename; | |
19174 | ||
19175 | filename = dwarf2_directive_file (0); | |
19176 | ||
19177 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19178 | directive even for stabs output. Make sure that this | |
19179 | ".file" is handled. Note that you need a version of GCC | |
19180 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19181 | if (filename != NULL && ! first_file_directive) | |
19182 | { | |
19183 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19184 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19185 | } |
19186 | first_file_directive = 1; | |
19187 | } | |
c5dd6aab DJ |
19188 | } |
19189 | ||
19190 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19191 | |
19192 | static void | |
17a2f251 | 19193 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19194 | { |
c5dd6aab DJ |
19195 | if (!ECOFF_DEBUGGING) |
19196 | dwarf2_directive_loc (0); | |
252b5132 RH |
19197 | } |
19198 | ||
252b5132 RH |
19199 | /* The .end directive. */ |
19200 | ||
19201 | static void | |
17a2f251 | 19202 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19203 | { |
19204 | symbolS *p; | |
252b5132 | 19205 | |
7a621144 DJ |
19206 | /* Following functions need their own .frame and .cprestore directives. */ |
19207 | mips_frame_reg_valid = 0; | |
19208 | mips_cprestore_valid = 0; | |
19209 | ||
252b5132 RH |
19210 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19211 | { | |
19212 | p = get_symbol (); | |
19213 | demand_empty_rest_of_line (); | |
19214 | } | |
19215 | else | |
19216 | p = NULL; | |
19217 | ||
14949570 | 19218 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19219 | as_warn (_(".end not in text section")); |
19220 | ||
19221 | if (!cur_proc_ptr) | |
19222 | { | |
19223 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19224 | demand_empty_rest_of_line (); | |
19225 | return; | |
19226 | } | |
19227 | ||
19228 | if (p != NULL) | |
19229 | { | |
9c2799c2 | 19230 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19231 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19232 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19233 | |
19234 | if (debug_type == DEBUG_STABS) | |
19235 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19236 | S_GET_NAME (p)); | |
252b5132 RH |
19237 | } |
19238 | else | |
19239 | as_warn (_(".end directive missing or unknown symbol")); | |
19240 | ||
2132e3a3 | 19241 | #ifdef OBJ_ELF |
9b2f1d35 EC |
19242 | /* Create an expression to calculate the size of the function. */ |
19243 | if (p && cur_proc_ptr) | |
19244 | { | |
19245 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19246 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19247 | ||
19248 | obj->size = exp; | |
19249 | exp->X_op = O_subtract; | |
19250 | exp->X_add_symbol = symbol_temp_new_now (); | |
19251 | exp->X_op_symbol = p; | |
19252 | exp->X_add_number = 0; | |
19253 | ||
19254 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19255 | } | |
19256 | ||
ecb4347a | 19257 | /* Generate a .pdr section. */ |
f43abd2b | 19258 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19259 | { |
19260 | segT saved_seg = now_seg; | |
19261 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19262 | expressionS exp; |
19263 | char *fragp; | |
252b5132 | 19264 | |
252b5132 | 19265 | #ifdef md_flush_pending_output |
ecb4347a | 19266 | md_flush_pending_output (); |
252b5132 RH |
19267 | #endif |
19268 | ||
9c2799c2 | 19269 | gas_assert (pdr_seg); |
ecb4347a | 19270 | subseg_set (pdr_seg, 0); |
252b5132 | 19271 | |
ecb4347a DJ |
19272 | /* Write the symbol. */ |
19273 | exp.X_op = O_symbol; | |
19274 | exp.X_add_symbol = p; | |
19275 | exp.X_add_number = 0; | |
19276 | emit_expr (&exp, 4); | |
252b5132 | 19277 | |
ecb4347a | 19278 | fragp = frag_more (7 * 4); |
252b5132 | 19279 | |
17a2f251 TS |
19280 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19281 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19282 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19283 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19284 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19285 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19286 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19287 | |
ecb4347a DJ |
19288 | subseg_set (saved_seg, saved_subseg); |
19289 | } | |
19290 | #endif /* OBJ_ELF */ | |
252b5132 RH |
19291 | |
19292 | cur_proc_ptr = NULL; | |
19293 | } | |
19294 | ||
19295 | /* The .aent and .ent directives. */ | |
19296 | ||
19297 | static void | |
17a2f251 | 19298 | s_mips_ent (int aent) |
252b5132 | 19299 | { |
252b5132 | 19300 | symbolS *symbolP; |
252b5132 RH |
19301 | |
19302 | symbolP = get_symbol (); | |
19303 | if (*input_line_pointer == ',') | |
f9419b05 | 19304 | ++input_line_pointer; |
252b5132 | 19305 | SKIP_WHITESPACE (); |
3882b010 | 19306 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19307 | || *input_line_pointer == '-') |
874e8986 | 19308 | get_number (); |
252b5132 | 19309 | |
14949570 | 19310 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19311 | as_warn (_(".ent or .aent not in text section.")); |
19312 | ||
19313 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19314 | as_warn (_("missing .end")); |
252b5132 RH |
19315 | |
19316 | if (!aent) | |
19317 | { | |
7a621144 DJ |
19318 | /* This function needs its own .frame and .cprestore directives. */ |
19319 | mips_frame_reg_valid = 0; | |
19320 | mips_cprestore_valid = 0; | |
19321 | ||
252b5132 RH |
19322 | cur_proc_ptr = &cur_proc; |
19323 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19324 | ||
9b2f1d35 | 19325 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19326 | |
f9419b05 | 19327 | ++numprocs; |
ecb4347a DJ |
19328 | |
19329 | if (debug_type == DEBUG_STABS) | |
19330 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19331 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19332 | } |
19333 | ||
7c0fc524 MR |
19334 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19335 | ||
252b5132 RH |
19336 | demand_empty_rest_of_line (); |
19337 | } | |
19338 | ||
19339 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19340 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19341 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19342 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19343 | symbol table (in the mdebug section). */ |
19344 | ||
19345 | static void | |
17a2f251 | 19346 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19347 | { |
ecb4347a | 19348 | #ifdef OBJ_ELF |
f43abd2b | 19349 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
19350 | { |
19351 | long val; | |
252b5132 | 19352 | |
ecb4347a DJ |
19353 | if (cur_proc_ptr == (procS *) NULL) |
19354 | { | |
19355 | as_warn (_(".frame outside of .ent")); | |
19356 | demand_empty_rest_of_line (); | |
19357 | return; | |
19358 | } | |
252b5132 | 19359 | |
ecb4347a DJ |
19360 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19361 | ||
19362 | SKIP_WHITESPACE (); | |
19363 | if (*input_line_pointer++ != ',' | |
19364 | || get_absolute_expression_and_terminator (&val) != ',') | |
19365 | { | |
19366 | as_warn (_("Bad .frame directive")); | |
19367 | --input_line_pointer; | |
19368 | demand_empty_rest_of_line (); | |
19369 | return; | |
19370 | } | |
252b5132 | 19371 | |
ecb4347a DJ |
19372 | cur_proc_ptr->frame_offset = val; |
19373 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19374 | |
252b5132 | 19375 | demand_empty_rest_of_line (); |
252b5132 | 19376 | } |
ecb4347a DJ |
19377 | else |
19378 | #endif /* OBJ_ELF */ | |
19379 | s_ignore (ignore); | |
252b5132 RH |
19380 | } |
19381 | ||
bdaaa2e1 KH |
19382 | /* The .fmask and .mask directives. If the mdebug section is present |
19383 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19384 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19385 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19386 | make reference to the ecoff symbol table (in the mdebug section). */ |
19387 | ||
19388 | static void | |
17a2f251 | 19389 | s_mips_mask (int reg_type) |
252b5132 | 19390 | { |
ecb4347a | 19391 | #ifdef OBJ_ELF |
f43abd2b | 19392 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 19393 | { |
ecb4347a | 19394 | long mask, off; |
252b5132 | 19395 | |
ecb4347a DJ |
19396 | if (cur_proc_ptr == (procS *) NULL) |
19397 | { | |
19398 | as_warn (_(".mask/.fmask outside of .ent")); | |
19399 | demand_empty_rest_of_line (); | |
19400 | return; | |
19401 | } | |
252b5132 | 19402 | |
ecb4347a DJ |
19403 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19404 | { | |
19405 | as_warn (_("Bad .mask/.fmask directive")); | |
19406 | --input_line_pointer; | |
19407 | demand_empty_rest_of_line (); | |
19408 | return; | |
19409 | } | |
252b5132 | 19410 | |
ecb4347a DJ |
19411 | off = get_absolute_expression (); |
19412 | ||
19413 | if (reg_type == 'F') | |
19414 | { | |
19415 | cur_proc_ptr->fpreg_mask = mask; | |
19416 | cur_proc_ptr->fpreg_offset = off; | |
19417 | } | |
19418 | else | |
19419 | { | |
19420 | cur_proc_ptr->reg_mask = mask; | |
19421 | cur_proc_ptr->reg_offset = off; | |
19422 | } | |
19423 | ||
19424 | demand_empty_rest_of_line (); | |
252b5132 RH |
19425 | } |
19426 | else | |
ecb4347a DJ |
19427 | #endif /* OBJ_ELF */ |
19428 | s_ignore (reg_type); | |
252b5132 RH |
19429 | } |
19430 | ||
316f5878 RS |
19431 | /* A table describing all the processors gas knows about. Names are |
19432 | matched in the order listed. | |
e7af610e | 19433 | |
316f5878 RS |
19434 | To ease comparison, please keep this table in the same order as |
19435 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19436 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19437 | { | |
316f5878 | 19438 | /* Entries for generic ISAs */ |
d16afab6 RS |
19439 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19440 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19441 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19442 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19443 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19444 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19445 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19446 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19447 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19448 | |
19449 | /* MIPS I */ | |
d16afab6 RS |
19450 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19451 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19452 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19453 | |
19454 | /* MIPS II */ | |
d16afab6 | 19455 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19456 | |
19457 | /* MIPS III */ | |
d16afab6 RS |
19458 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19459 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19460 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19461 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19462 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19463 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19464 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19465 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19466 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19467 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19468 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19469 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19470 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19471 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19472 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19473 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19474 | |
19475 | /* MIPS IV */ | |
d16afab6 RS |
19476 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19477 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19478 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19479 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19480 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19481 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19482 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19483 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19484 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19485 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19486 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19487 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19488 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19489 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19490 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19491 | |
19492 | /* MIPS 32 */ | |
d16afab6 RS |
19493 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19494 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19495 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19496 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19497 | |
19498 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19499 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19500 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19501 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19502 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19503 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19504 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19505 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19506 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19507 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19508 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19509 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19510 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19511 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19512 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19513 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19514 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19515 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19516 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19517 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19518 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19519 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19520 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19521 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19522 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19523 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19524 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19525 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19526 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19527 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19528 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19529 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19530 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19531 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19532 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19533 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19534 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19535 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19536 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19537 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19538 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19539 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19540 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19541 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19542 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19543 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19544 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19545 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19546 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19547 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19548 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19549 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19550 | |
316f5878 | 19551 | /* MIPS 64 */ |
d16afab6 RS |
19552 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19553 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19554 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19555 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19556 | |
c7a23324 | 19557 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19558 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19559 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19560 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 19561 | |
d16afab6 | 19562 | { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, |
e7af610e | 19563 | |
ed163775 MR |
19564 | /* MIPS 64 Release 2 */ |
19565 | ||
967344c6 | 19566 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19567 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19568 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19569 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 19570 | |
52b6b6b9 | 19571 | /* RMI Xlr */ |
d16afab6 | 19572 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19573 | |
55a36193 MK |
19574 | /* Broadcom XLP. |
19575 | XLP is mostly like XLR, with the prominent exception that it is | |
19576 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19577 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19578 | |
316f5878 | 19579 | /* End marker */ |
d16afab6 | 19580 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19581 | }; |
e7af610e | 19582 | |
84ea6cf2 | 19583 | |
316f5878 RS |
19584 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19585 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19586 | |
316f5878 | 19587 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19588 | |
b34976b6 | 19589 | static bfd_boolean |
17a2f251 | 19590 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19591 | { |
19592 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19593 | given++, canonical++; | |
19594 | ||
19595 | return ((*given == 0 && *canonical == 0) | |
19596 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19597 | } | |
19598 | ||
19599 | ||
19600 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19601 | CPU name. We've traditionally allowed a lot of variation here. | |
19602 | ||
19603 | Note: this function is shared between GCC and GAS. */ | |
19604 | ||
b34976b6 | 19605 | static bfd_boolean |
17a2f251 | 19606 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19607 | { |
19608 | /* First see if the name matches exactly, or with a final "000" | |
19609 | turned into "k". */ | |
19610 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19611 | return TRUE; |
316f5878 RS |
19612 | |
19613 | /* If not, try comparing based on numerical designation alone. | |
19614 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19615 | if (TOLOWER (*given) == 'r') | |
19616 | given++; | |
19617 | if (!ISDIGIT (*given)) | |
b34976b6 | 19618 | return FALSE; |
316f5878 RS |
19619 | |
19620 | /* Skip over some well-known prefixes in the canonical name, | |
19621 | hoping to find a number there too. */ | |
19622 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19623 | canonical += 2; | |
19624 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19625 | canonical += 2; | |
19626 | else if (TOLOWER (canonical[0]) == 'r') | |
19627 | canonical += 1; | |
19628 | ||
19629 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19630 | } | |
19631 | ||
19632 | ||
19633 | /* Parse an option that takes the name of a processor as its argument. | |
19634 | OPTION is the name of the option and CPU_STRING is the argument. | |
19635 | Return the corresponding processor enumeration if the CPU_STRING is | |
19636 | recognized, otherwise report an error and return null. | |
19637 | ||
19638 | A similar function exists in GCC. */ | |
e7af610e NC |
19639 | |
19640 | static const struct mips_cpu_info * | |
17a2f251 | 19641 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19642 | { |
316f5878 | 19643 | const struct mips_cpu_info *p; |
e7af610e | 19644 | |
316f5878 RS |
19645 | /* 'from-abi' selects the most compatible architecture for the given |
19646 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19647 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19648 | version. Look first at the -mgp options, if given, otherwise base | |
19649 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19650 | |
316f5878 RS |
19651 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19652 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19653 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19654 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19655 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19656 | { | |
19657 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19658 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19659 | ||
19660 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19661 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19662 | ||
19663 | if (file_mips_gp32 >= 0) | |
19664 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19665 | ||
19666 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19667 | ? ISA_MIPS3 | |
19668 | : ISA_MIPS1); | |
19669 | } | |
19670 | ||
19671 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19672 | if (strcasecmp (cpu_string, "default") == 0) | |
19673 | return 0; | |
19674 | ||
19675 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19676 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19677 | return p; | |
19678 | ||
20203fb9 | 19679 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19680 | return 0; |
e7af610e NC |
19681 | } |
19682 | ||
316f5878 RS |
19683 | /* Return the canonical processor information for ISA (a member of the |
19684 | ISA_MIPS* enumeration). */ | |
19685 | ||
e7af610e | 19686 | static const struct mips_cpu_info * |
17a2f251 | 19687 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19688 | { |
19689 | int i; | |
19690 | ||
19691 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19692 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19693 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19694 | return (&mips_cpu_info_table[i]); |
19695 | ||
e972090a | 19696 | return NULL; |
e7af610e | 19697 | } |
fef14a42 TS |
19698 | |
19699 | static const struct mips_cpu_info * | |
17a2f251 | 19700 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19701 | { |
19702 | int i; | |
19703 | ||
19704 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19705 | if (arch == mips_cpu_info_table[i].cpu) | |
19706 | return (&mips_cpu_info_table[i]); | |
19707 | ||
19708 | return NULL; | |
19709 | } | |
316f5878 RS |
19710 | \f |
19711 | static void | |
17a2f251 | 19712 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19713 | { |
19714 | if (*first_p) | |
19715 | { | |
19716 | fprintf (stream, "%24s", ""); | |
19717 | *col_p = 24; | |
19718 | } | |
19719 | else | |
19720 | { | |
19721 | fprintf (stream, ", "); | |
19722 | *col_p += 2; | |
19723 | } | |
e7af610e | 19724 | |
316f5878 RS |
19725 | if (*col_p + strlen (string) > 72) |
19726 | { | |
19727 | fprintf (stream, "\n%24s", ""); | |
19728 | *col_p = 24; | |
19729 | } | |
19730 | ||
19731 | fprintf (stream, "%s", string); | |
19732 | *col_p += strlen (string); | |
19733 | ||
19734 | *first_p = 0; | |
19735 | } | |
19736 | ||
19737 | void | |
17a2f251 | 19738 | md_show_usage (FILE *stream) |
e7af610e | 19739 | { |
316f5878 RS |
19740 | int column, first; |
19741 | size_t i; | |
19742 | ||
19743 | fprintf (stream, _("\ | |
19744 | MIPS options:\n\ | |
316f5878 RS |
19745 | -EB generate big endian output\n\ |
19746 | -EL generate little endian output\n\ | |
19747 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19748 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19749 | implicitly with the gp register [default 8]\n")); | |
19750 | fprintf (stream, _("\ | |
19751 | -mips1 generate MIPS ISA I instructions\n\ | |
19752 | -mips2 generate MIPS ISA II instructions\n\ | |
19753 | -mips3 generate MIPS ISA III instructions\n\ | |
19754 | -mips4 generate MIPS ISA IV instructions\n\ | |
19755 | -mips5 generate MIPS ISA V instructions\n\ | |
19756 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19757 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19758 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19759 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19760 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19761 | ||
19762 | first = 1; | |
e7af610e NC |
19763 | |
19764 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19765 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19766 | show (stream, "from-abi", &column, &first); | |
19767 | fputc ('\n', stream); | |
e7af610e | 19768 | |
316f5878 RS |
19769 | fprintf (stream, _("\ |
19770 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19771 | -no-mCPU don't generate code specific to CPU.\n\ | |
19772 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19773 | ||
19774 | first = 1; | |
19775 | ||
19776 | show (stream, "3900", &column, &first); | |
19777 | show (stream, "4010", &column, &first); | |
19778 | show (stream, "4100", &column, &first); | |
19779 | show (stream, "4650", &column, &first); | |
19780 | fputc ('\n', stream); | |
19781 | ||
19782 | fprintf (stream, _("\ | |
19783 | -mips16 generate mips16 instructions\n\ | |
19784 | -no-mips16 do not generate mips16 instructions\n")); | |
19785 | fprintf (stream, _("\ | |
df58fc94 RS |
19786 | -mmicromips generate microMIPS instructions\n\ |
19787 | -mno-micromips do not generate microMIPS instructions\n")); | |
19788 | fprintf (stream, _("\ | |
e16bfa71 TS |
19789 | -msmartmips generate smartmips instructions\n\ |
19790 | -mno-smartmips do not generate smartmips instructions\n")); | |
19791 | fprintf (stream, _("\ | |
74cd071d CF |
19792 | -mdsp generate DSP instructions\n\ |
19793 | -mno-dsp do not generate DSP instructions\n")); | |
19794 | fprintf (stream, _("\ | |
8b082fb1 TS |
19795 | -mdspr2 generate DSP R2 instructions\n\ |
19796 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19797 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19798 | -mmt generate MT instructions\n\ |
19799 | -mno-mt do not generate MT instructions\n")); | |
19800 | fprintf (stream, _("\ | |
dec0624d MR |
19801 | -mmcu generate MCU instructions\n\ |
19802 | -mno-mcu do not generate MCU instructions\n")); | |
19803 | fprintf (stream, _("\ | |
b015e599 AP |
19804 | -mvirt generate Virtualization instructions\n\ |
19805 | -mno-virt do not generate Virtualization instructions\n")); | |
19806 | fprintf (stream, _("\ | |
c67a084a NC |
19807 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19808 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19809 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19810 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19811 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19812 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19813 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19814 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19815 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19816 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19817 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19818 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19819 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19820 | fprintf (stream, _("\ |
19821 | -mhard-float allow floating-point instructions\n\ | |
19822 | -msoft-float do not allow floating-point instructions\n\ | |
19823 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19824 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb MR |
19825 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
19826 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n" | |
037b32b9 | 19827 | )); |
316f5878 RS |
19828 | #ifdef OBJ_ELF |
19829 | fprintf (stream, _("\ | |
19830 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19831 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19832 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19833 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19834 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19835 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19836 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19837 | position dependent (non shared) code\n\ |
316f5878 RS |
19838 | -mabi=ABI create ABI conformant object file for:\n")); |
19839 | ||
19840 | first = 1; | |
19841 | ||
19842 | show (stream, "32", &column, &first); | |
19843 | show (stream, "o64", &column, &first); | |
19844 | show (stream, "n32", &column, &first); | |
19845 | show (stream, "64", &column, &first); | |
19846 | show (stream, "eabi", &column, &first); | |
19847 | ||
19848 | fputc ('\n', stream); | |
19849 | ||
19850 | fprintf (stream, _("\ | |
19851 | -32 create o32 ABI object file (default)\n\ | |
19852 | -n32 create n32 ABI object file\n\ | |
19853 | -64 create 64 ABI object file\n")); | |
19854 | #endif | |
e7af610e | 19855 | } |
14e777e0 | 19856 | |
1575952e | 19857 | #ifdef TE_IRIX |
14e777e0 | 19858 | enum dwarf2_format |
413a266c | 19859 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19860 | { |
369943fe | 19861 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19862 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19863 | else |
19864 | return dwarf2_format_32bit; | |
19865 | } | |
1575952e | 19866 | #endif |
73369e65 EC |
19867 | |
19868 | int | |
19869 | mips_dwarf2_addr_size (void) | |
19870 | { | |
6b6b3450 | 19871 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19872 | return 8; |
73369e65 EC |
19873 | else |
19874 | return 4; | |
19875 | } | |
5862107c EC |
19876 | |
19877 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19878 | void | |
19879 | mips_cfi_frame_initial_instructions (void) | |
19880 | { | |
19881 | cfi_add_CFA_def_cfa_register (SP); | |
19882 | } | |
19883 | ||
707bfff6 TS |
19884 | int |
19885 | tc_mips_regname_to_dw2regnum (char *regname) | |
19886 | { | |
19887 | unsigned int regnum = -1; | |
19888 | unsigned int reg; | |
19889 | ||
19890 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19891 | regnum = reg; | |
19892 | ||
19893 | return regnum; | |
19894 | } |