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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
47e39b9d RS |
122 | /* Information about an instruction, including its format, operands |
123 | and fixups. */ | |
124 | struct mips_cl_insn | |
125 | { | |
126 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
127 | const struct mips_opcode *insn_mo; | |
128 | ||
129 | /* True if this is a mips16 instruction and if we want the extended | |
130 | form of INSN_MO. */ | |
131 | bfd_boolean use_extend; | |
132 | ||
133 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
134 | unsigned short extend; | |
135 | ||
136 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
137 | a copy of INSN_MO->match with the operands filled in. */ | |
138 | unsigned long insn_opcode; | |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d RS |
151 | |
152 | /* True if this instruction occured in a .set noreorder block. */ | |
153 | unsigned int noreorder_p : 1; | |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
157 | }; |
158 | ||
a325df1d TS |
159 | /* The ABI to use. */ |
160 | enum mips_abi_level | |
161 | { | |
162 | NO_ABI = 0, | |
163 | O32_ABI, | |
164 | O64_ABI, | |
165 | N32_ABI, | |
166 | N64_ABI, | |
167 | EABI_ABI | |
168 | }; | |
169 | ||
170 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 171 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 172 | |
143d77c5 EC |
173 | /* Whether or not we have code that can call pic code. */ |
174 | int mips_abicalls = FALSE; | |
175 | ||
aa6975fb ILT |
176 | /* Whether or not we have code which can be put into a shared |
177 | library. */ | |
178 | static bfd_boolean mips_in_shared = TRUE; | |
179 | ||
252b5132 RH |
180 | /* This is the set of options which may be modified by the .set |
181 | pseudo-op. We use a struct so that .set push and .set pop are more | |
182 | reliable. */ | |
183 | ||
e972090a NC |
184 | struct mips_set_options |
185 | { | |
252b5132 RH |
186 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
187 | if it has not been initialized. Changed by `.set mipsN', and the | |
188 | -mipsN command line option, and the default CPU. */ | |
189 | int isa; | |
1f25f5d3 CD |
190 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
191 | if they have not been initialized. Changed by `.set <asename>', by | |
192 | command line options, and based on the default architecture. */ | |
193 | int ase_mips3d; | |
deec1734 | 194 | int ase_mdmx; |
252b5132 RH |
195 | /* Whether we are assembling for the mips16 processor. 0 if we are |
196 | not, 1 if we are, and -1 if the value has not been initialized. | |
197 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
198 | -nomips16 command line options, and the default CPU. */ | |
199 | int mips16; | |
200 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
201 | reorder' and `.set noreorder'. */ | |
202 | int noreorder; | |
203 | /* Non-zero if we should not permit the $at ($1) register to be used | |
204 | in instructions. Changed by `.set at' and `.set noat'. */ | |
205 | int noat; | |
206 | /* Non-zero if we should warn when a macro instruction expands into | |
207 | more than one machine instruction. Changed by `.set nomacro' and | |
208 | `.set macro'. */ | |
209 | int warn_about_macros; | |
210 | /* Non-zero if we should not move instructions. Changed by `.set | |
211 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
212 | int nomove; | |
213 | /* Non-zero if we should not optimize branches by moving the target | |
214 | of the branch into the delay slot. Actually, we don't perform | |
215 | this optimization anyhow. Changed by `.set bopt' and `.set | |
216 | nobopt'. */ | |
217 | int nobopt; | |
218 | /* Non-zero if we should not autoextend mips16 instructions. | |
219 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
220 | int noautoextend; | |
a325df1d TS |
221 | /* Restrict general purpose registers and floating point registers |
222 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
223 | is passed but can changed if the assembler code uses .set mipsN. */ | |
224 | int gp32; | |
225 | int fp32; | |
fef14a42 TS |
226 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
227 | command line option, and the default CPU. */ | |
228 | int arch; | |
aed1a261 RS |
229 | /* True if ".set sym32" is in effect. */ |
230 | bfd_boolean sym32; | |
252b5132 RH |
231 | }; |
232 | ||
a325df1d | 233 | /* True if -mgp32 was passed. */ |
a8e8e863 | 234 | static int file_mips_gp32 = -1; |
a325df1d TS |
235 | |
236 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 237 | static int file_mips_fp32 = -1; |
a325df1d | 238 | |
252b5132 | 239 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 240 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 241 | -1 to indicate that they have not been initialized. */ |
252b5132 | 242 | |
e972090a NC |
243 | static struct mips_set_options mips_opts = |
244 | { | |
aed1a261 | 245 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 246 | }; |
252b5132 RH |
247 | |
248 | /* These variables are filled in with the masks of registers used. | |
249 | The object format code reads them and puts them in the appropriate | |
250 | place. */ | |
251 | unsigned long mips_gprmask; | |
252 | unsigned long mips_cprmask[4]; | |
253 | ||
254 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 255 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 256 | |
a4672219 TS |
257 | /* True if -mips16 was passed or implied by arguments passed on the |
258 | command line (e.g., by -march). */ | |
259 | static int file_ase_mips16; | |
260 | ||
1f25f5d3 CD |
261 | /* True if -mips3d was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips3d; | |
264 | ||
deec1734 CD |
265 | /* True if -mdmx was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mdmx; | |
268 | ||
ec68c924 | 269 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 270 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 271 | static const char *mips_arch_string; |
ec68c924 EC |
272 | |
273 | /* The argument of the -mtune= flag. The architecture for which we | |
274 | are optimizing. */ | |
275 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 276 | static const char *mips_tune_string; |
ec68c924 | 277 | |
316f5878 | 278 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
279 | static int mips_32bitmode = 0; |
280 | ||
316f5878 RS |
281 | /* True if the given ABI requires 32-bit registers. */ |
282 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
283 | ||
284 | /* Likewise 64-bit registers. */ | |
285 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
286 | ((ABI) == N32_ABI \ | |
287 | || (ABI) == N64_ABI \ | |
288 | || (ABI) == O64_ABI) | |
289 | ||
bdaaa2e1 | 290 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 291 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
292 | (ISA) == ISA_MIPS3 \ |
293 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 294 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 295 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 296 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
297 | ) |
298 | ||
af7ee8bf CD |
299 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
300 | instructions. */ | |
301 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 302 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
303 | ) |
304 | ||
305 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
306 | instructions. */ | |
307 | #define ISA_HAS_ROR(ISA) ( \ | |
308 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 309 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
310 | ) |
311 | ||
e013f690 | 312 | #define HAVE_32BIT_GPRS \ |
316f5878 | 313 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 314 | |
e013f690 | 315 | #define HAVE_32BIT_FPRS \ |
316f5878 | 316 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
317 | |
318 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
319 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
320 | ||
316f5878 | 321 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 322 | |
316f5878 | 323 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 324 | |
3b91255e RS |
325 | /* True if relocations are stored in-place. */ |
326 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
327 | ||
aed1a261 RS |
328 | /* The ABI-derived address size. */ |
329 | #define HAVE_64BIT_ADDRESSES \ | |
330 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
331 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 332 | |
aed1a261 RS |
333 | /* The size of symbolic constants (i.e., expressions of the form |
334 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
335 | #define HAVE_32BIT_SYMBOLS \ | |
336 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
337 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 338 | |
b7c7d6c1 TS |
339 | /* Addresses are loaded in different ways, depending on the address size |
340 | in use. The n32 ABI Documentation also mandates the use of additions | |
341 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 342 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 343 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
344 | |
345 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 346 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
347 | |
348 | #define ADDRESS_LOAD_INSN \ | |
349 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
350 | ||
351 | #define ADDRESS_STORE_INSN \ | |
352 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
353 | ||
a4672219 | 354 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
355 | #define CPU_HAS_MIPS16(cpu) \ |
356 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
357 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 358 | |
1f25f5d3 CD |
359 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
360 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
361 | ) | |
362 | ||
deec1734 | 363 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 364 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
365 | ) |
366 | ||
60b63b72 RS |
367 | /* True if CPU has a dror instruction. */ |
368 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
369 | ||
370 | /* True if CPU has a ror instruction. */ | |
371 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
372 | ||
c8978940 CD |
373 | /* True if mflo and mfhi can be immediately followed by instructions |
374 | which write to the HI and LO registers. | |
375 | ||
376 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
377 | (at least) two instructions between the reads of HI/LO and | |
378 | instructions which write them, and later ISAs do not. Contradicting | |
379 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
380 | the UM for the NEC Vr5000) document needing the instructions between | |
381 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
382 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
383 | earlier-ISA CPUs for which CPU documentation declares that the | |
384 | instructions are really interlocked. */ | |
385 | #define hilo_interlocks \ | |
386 | (mips_opts.isa == ISA_MIPS32 \ | |
387 | || mips_opts.isa == ISA_MIPS32R2 \ | |
388 | || mips_opts.isa == ISA_MIPS64 \ | |
389 | || mips_opts.isa == ISA_MIPS64R2 \ | |
390 | || mips_opts.arch == CPU_R4010 \ | |
391 | || mips_opts.arch == CPU_R10000 \ | |
392 | || mips_opts.arch == CPU_R12000 \ | |
393 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
394 | || mips_opts.arch == CPU_VR5500 \ |
395 | ) | |
252b5132 RH |
396 | |
397 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
398 | from the GPRs after they are loaded from memory, and thus does not |
399 | require nops to be inserted. This applies to instructions marked | |
400 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
401 | level I. */ | |
252b5132 | 402 | #define gpr_interlocks \ |
e7af610e | 403 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 404 | || mips_opts.arch == CPU_R3900) |
252b5132 | 405 | |
81912461 ILT |
406 | /* Whether the processor uses hardware interlocks to avoid delays |
407 | required by coprocessor instructions, and thus does not require | |
408 | nops to be inserted. This applies to instructions marked | |
409 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
410 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
411 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
412 | levels I, II, and III. */ | |
bdaaa2e1 | 413 | /* Itbl support may require additional care here. */ |
81912461 ILT |
414 | #define cop_interlocks \ |
415 | ((mips_opts.isa != ISA_MIPS1 \ | |
416 | && mips_opts.isa != ISA_MIPS2 \ | |
417 | && mips_opts.isa != ISA_MIPS3) \ | |
418 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
419 | ) |
420 | ||
421 | /* Whether the processor uses hardware interlocks to protect reads | |
422 | from coprocessor registers after they are loaded from memory, and | |
423 | thus does not require nops to be inserted. This applies to | |
424 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
425 | requires at MIPS ISA level I. */ | |
426 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 427 | |
6b76fefe CM |
428 | /* Is this a mfhi or mflo instruction? */ |
429 | #define MF_HILO_INSN(PINFO) \ | |
430 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
431 | ||
252b5132 RH |
432 | /* MIPS PIC level. */ |
433 | ||
a161fe53 | 434 | enum mips_pic_level mips_pic; |
252b5132 | 435 | |
c9914766 | 436 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 437 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 438 | static int mips_big_got = 0; |
252b5132 RH |
439 | |
440 | /* 1 if trap instructions should used for overflow rather than break | |
441 | instructions. */ | |
c9914766 | 442 | static int mips_trap = 0; |
252b5132 | 443 | |
119d663a | 444 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 445 | by assembling two single width halves into two single width floating |
119d663a NC |
446 | point registers which just happen to alias the double width destination |
447 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 448 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
449 | automatically at assemble time. */ |
450 | static int mips_disable_float_construction; | |
451 | ||
252b5132 RH |
452 | /* Non-zero if any .set noreorder directives were used. */ |
453 | ||
454 | static int mips_any_noreorder; | |
455 | ||
6b76fefe CM |
456 | /* Non-zero if nops should be inserted when the register referenced in |
457 | an mfhi/mflo instruction is read in the next two instructions. */ | |
458 | static int mips_7000_hilo_fix; | |
459 | ||
252b5132 | 460 | /* The size of the small data section. */ |
156c2f8b | 461 | static unsigned int g_switch_value = 8; |
252b5132 RH |
462 | /* Whether the -G option was used. */ |
463 | static int g_switch_seen = 0; | |
464 | ||
465 | #define N_RMASK 0xc4 | |
466 | #define N_VFP 0xd4 | |
467 | ||
468 | /* If we can determine in advance that GP optimization won't be | |
469 | possible, we can skip the relaxation stuff that tries to produce | |
470 | GP-relative references. This makes delay slot optimization work | |
471 | better. | |
472 | ||
473 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
474 | gcc output. It needs to guess right for gcc, otherwise gcc |
475 | will put what it thinks is a GP-relative instruction in a branch | |
476 | delay slot. | |
252b5132 RH |
477 | |
478 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
479 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 480 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
481 | |
482 | /* handle of the OPCODE hash table */ | |
483 | static struct hash_control *op_hash = NULL; | |
484 | ||
485 | /* The opcode hash table we use for the mips16. */ | |
486 | static struct hash_control *mips16_op_hash = NULL; | |
487 | ||
488 | /* This array holds the chars that always start a comment. If the | |
489 | pre-processor is disabled, these aren't very useful */ | |
490 | const char comment_chars[] = "#"; | |
491 | ||
492 | /* This array holds the chars that only start a comment at the beginning of | |
493 | a line. If the line seems to have the form '# 123 filename' | |
494 | .line and .file directives will appear in the pre-processed output */ | |
495 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
496 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 497 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
498 | /* Also note that C style comments are always supported. */ |
499 | const char line_comment_chars[] = "#"; | |
500 | ||
bdaaa2e1 | 501 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 502 | const char line_separator_chars[] = ";"; |
252b5132 RH |
503 | |
504 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
505 | const char EXP_CHARS[] = "eE"; | |
506 | ||
507 | /* Chars that mean this number is a floating point constant */ | |
508 | /* As in 0f12.456 */ | |
509 | /* or 0d1.2345e12 */ | |
510 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
511 | ||
512 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
513 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
514 | but nothing is ideal around here. | |
515 | */ | |
516 | ||
517 | static char *insn_error; | |
518 | ||
519 | static int auto_align = 1; | |
520 | ||
521 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
522 | offset in the stack frame from which to restore the $gp register. | |
523 | This is set by the .cprestore pseudo-op, and saved in this | |
524 | variable. */ | |
525 | static offsetT mips_cprestore_offset = -1; | |
526 | ||
67c1ffbe | 527 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 528 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 529 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
530 | static offsetT mips_cpreturn_offset = -1; |
531 | static int mips_cpreturn_register = -1; | |
532 | static int mips_gp_register = GP; | |
def2e0dd | 533 | static int mips_gprel_offset = 0; |
6478892d | 534 | |
7a621144 DJ |
535 | /* Whether mips_cprestore_offset has been set in the current function |
536 | (or whether it has already been warned about, if not). */ | |
537 | static int mips_cprestore_valid = 0; | |
538 | ||
252b5132 RH |
539 | /* This is the register which holds the stack frame, as set by the |
540 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
541 | static int mips_frame_reg = SP; | |
542 | ||
7a621144 DJ |
543 | /* Whether mips_frame_reg has been set in the current function |
544 | (or whether it has already been warned about, if not). */ | |
545 | static int mips_frame_reg_valid = 0; | |
546 | ||
252b5132 RH |
547 | /* To output NOP instructions correctly, we need to keep information |
548 | about the previous two instructions. */ | |
549 | ||
550 | /* Whether we are optimizing. The default value of 2 means to remove | |
551 | unneeded NOPs and swap branch instructions when possible. A value | |
552 | of 1 means to not swap branches. A value of 0 means to always | |
553 | insert NOPs. */ | |
554 | static int mips_optimize = 2; | |
555 | ||
556 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
557 | equivalent to seeing no -g option at all. */ | |
558 | static int mips_debug = 0; | |
559 | ||
47e39b9d RS |
560 | /* A list of previous instructions, with index 0 being the most recent. */ |
561 | static struct mips_cl_insn history[2]; | |
252b5132 | 562 | |
47e39b9d | 563 | /* If we don't want information for a history[] entry, we |
252b5132 | 564 | point the insn_mo field at this dummy integer. */ |
9c6ed8e6 | 565 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 }; |
252b5132 | 566 | |
252b5132 RH |
567 | /* If this is set, it points to a frag holding nop instructions which |
568 | were inserted before the start of a noreorder section. If those | |
569 | nops turn out to be unnecessary, the size of the frag can be | |
570 | decreased. */ | |
571 | static fragS *prev_nop_frag; | |
572 | ||
573 | /* The number of nop instructions we created in prev_nop_frag. */ | |
574 | static int prev_nop_frag_holds; | |
575 | ||
576 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 577 | prev_nop_frag. */ |
252b5132 RH |
578 | static int prev_nop_frag_required; |
579 | ||
580 | /* The number of instructions we've seen since prev_nop_frag. */ | |
581 | static int prev_nop_frag_since; | |
582 | ||
583 | /* For ECOFF and ELF, relocations against symbols are done in two | |
584 | parts, with a HI relocation and a LO relocation. Each relocation | |
585 | has only 16 bits of space to store an addend. This means that in | |
586 | order for the linker to handle carries correctly, it must be able | |
587 | to locate both the HI and the LO relocation. This means that the | |
588 | relocations must appear in order in the relocation table. | |
589 | ||
590 | In order to implement this, we keep track of each unmatched HI | |
591 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 592 | corresponding LO relocation. */ |
252b5132 | 593 | |
e972090a NC |
594 | struct mips_hi_fixup |
595 | { | |
252b5132 RH |
596 | /* Next HI fixup. */ |
597 | struct mips_hi_fixup *next; | |
598 | /* This fixup. */ | |
599 | fixS *fixp; | |
600 | /* The section this fixup is in. */ | |
601 | segT seg; | |
602 | }; | |
603 | ||
604 | /* The list of unmatched HI relocs. */ | |
605 | ||
606 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
607 | ||
64bdfcaf RS |
608 | /* The frag containing the last explicit relocation operator. |
609 | Null if explicit relocations have not been used. */ | |
610 | ||
611 | static fragS *prev_reloc_op_frag; | |
612 | ||
252b5132 RH |
613 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
614 | ||
615 | #define X ILLEGAL_REG | |
e972090a NC |
616 | static const int mips32_to_16_reg_map[] = |
617 | { | |
252b5132 RH |
618 | X, X, 2, 3, 4, 5, 6, 7, |
619 | X, X, X, X, X, X, X, X, | |
620 | 0, 1, X, X, X, X, X, X, | |
621 | X, X, X, X, X, X, X, X | |
622 | }; | |
623 | #undef X | |
624 | ||
625 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
626 | ||
e972090a NC |
627 | static const unsigned int mips16_to_32_reg_map[] = |
628 | { | |
252b5132 RH |
629 | 16, 17, 2, 3, 4, 5, 6, 7 |
630 | }; | |
60b63b72 | 631 | |
d766e8ec | 632 | static int mips_fix_vr4120; |
4a6a3df4 AO |
633 | |
634 | /* We don't relax branches by default, since this causes us to expand | |
635 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
636 | fail to compute the offset before expanding the macro to the most | |
637 | efficient expansion. */ | |
638 | ||
639 | static int mips_relax_branch; | |
252b5132 | 640 | \f |
4d7206a2 RS |
641 | /* The expansion of many macros depends on the type of symbol that |
642 | they refer to. For example, when generating position-dependent code, | |
643 | a macro that refers to a symbol may have two different expansions, | |
644 | one which uses GP-relative addresses and one which uses absolute | |
645 | addresses. When generating SVR4-style PIC, a macro may have | |
646 | different expansions for local and global symbols. | |
647 | ||
648 | We handle these situations by generating both sequences and putting | |
649 | them in variant frags. In position-dependent code, the first sequence | |
650 | will be the GP-relative one and the second sequence will be the | |
651 | absolute one. In SVR4 PIC, the first sequence will be for global | |
652 | symbols and the second will be for local symbols. | |
653 | ||
584892a6 RS |
654 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
655 | SECOND are the lengths of the two sequences in bytes. These fields | |
656 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
657 | the subtype has the following flags: | |
4d7206a2 | 658 | |
584892a6 RS |
659 | RELAX_USE_SECOND |
660 | Set if it has been decided that we should use the second | |
661 | sequence instead of the first. | |
662 | ||
663 | RELAX_SECOND_LONGER | |
664 | Set in the first variant frag if the macro's second implementation | |
665 | is longer than its first. This refers to the macro as a whole, | |
666 | not an individual relaxation. | |
667 | ||
668 | RELAX_NOMACRO | |
669 | Set in the first variant frag if the macro appeared in a .set nomacro | |
670 | block and if one alternative requires a warning but the other does not. | |
671 | ||
672 | RELAX_DELAY_SLOT | |
673 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
674 | delay slot. | |
4d7206a2 RS |
675 | |
676 | The frag's "opcode" points to the first fixup for relaxable code. | |
677 | ||
678 | Relaxable macros are generated using a sequence such as: | |
679 | ||
680 | relax_start (SYMBOL); | |
681 | ... generate first expansion ... | |
682 | relax_switch (); | |
683 | ... generate second expansion ... | |
684 | relax_end (); | |
685 | ||
686 | The code and fixups for the unwanted alternative are discarded | |
687 | by md_convert_frag. */ | |
584892a6 | 688 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 689 | |
584892a6 RS |
690 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
691 | #define RELAX_SECOND(X) ((X) & 0xff) | |
692 | #define RELAX_USE_SECOND 0x10000 | |
693 | #define RELAX_SECOND_LONGER 0x20000 | |
694 | #define RELAX_NOMACRO 0x40000 | |
695 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 696 | |
4a6a3df4 AO |
697 | /* Branch without likely bit. If label is out of range, we turn: |
698 | ||
699 | beq reg1, reg2, label | |
700 | delay slot | |
701 | ||
702 | into | |
703 | ||
704 | bne reg1, reg2, 0f | |
705 | nop | |
706 | j label | |
707 | 0: delay slot | |
708 | ||
709 | with the following opcode replacements: | |
710 | ||
711 | beq <-> bne | |
712 | blez <-> bgtz | |
713 | bltz <-> bgez | |
714 | bc1f <-> bc1t | |
715 | ||
716 | bltzal <-> bgezal (with jal label instead of j label) | |
717 | ||
718 | Even though keeping the delay slot instruction in the delay slot of | |
719 | the branch would be more efficient, it would be very tricky to do | |
720 | correctly, because we'd have to introduce a variable frag *after* | |
721 | the delay slot instruction, and expand that instead. Let's do it | |
722 | the easy way for now, even if the branch-not-taken case now costs | |
723 | one additional instruction. Out-of-range branches are not supposed | |
724 | to be common, anyway. | |
725 | ||
726 | Branch likely. If label is out of range, we turn: | |
727 | ||
728 | beql reg1, reg2, label | |
729 | delay slot (annulled if branch not taken) | |
730 | ||
731 | into | |
732 | ||
733 | beql reg1, reg2, 1f | |
734 | nop | |
735 | beql $0, $0, 2f | |
736 | nop | |
737 | 1: j[al] label | |
738 | delay slot (executed only if branch taken) | |
739 | 2: | |
740 | ||
741 | It would be possible to generate a shorter sequence by losing the | |
742 | likely bit, generating something like: | |
b34976b6 | 743 | |
4a6a3df4 AO |
744 | bne reg1, reg2, 0f |
745 | nop | |
746 | j[al] label | |
747 | delay slot (executed only if branch taken) | |
748 | 0: | |
749 | ||
750 | beql -> bne | |
751 | bnel -> beq | |
752 | blezl -> bgtz | |
753 | bgtzl -> blez | |
754 | bltzl -> bgez | |
755 | bgezl -> bltz | |
756 | bc1fl -> bc1t | |
757 | bc1tl -> bc1f | |
758 | ||
759 | bltzall -> bgezal (with jal label instead of j label) | |
760 | bgezall -> bltzal (ditto) | |
761 | ||
762 | ||
763 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 764 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
765 | ((relax_substateT) \ |
766 | (0xc0000000 \ | |
767 | | ((toofar) ? 1 : 0) \ | |
768 | | ((link) ? 2 : 0) \ | |
769 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 770 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 771 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
772 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
773 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
774 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 775 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 776 | |
252b5132 RH |
777 | /* For mips16 code, we use an entirely different form of relaxation. |
778 | mips16 supports two versions of most instructions which take | |
779 | immediate values: a small one which takes some small value, and a | |
780 | larger one which takes a 16 bit value. Since branches also follow | |
781 | this pattern, relaxing these values is required. | |
782 | ||
783 | We can assemble both mips16 and normal MIPS code in a single | |
784 | object. Therefore, we need to support this type of relaxation at | |
785 | the same time that we support the relaxation described above. We | |
786 | use the high bit of the subtype field to distinguish these cases. | |
787 | ||
788 | The information we store for this type of relaxation is the | |
789 | argument code found in the opcode file for this relocation, whether | |
790 | the user explicitly requested a small or extended form, and whether | |
791 | the relocation is in a jump or jal delay slot. That tells us the | |
792 | size of the value, and how it should be stored. We also store | |
793 | whether the fragment is considered to be extended or not. We also | |
794 | store whether this is known to be a branch to a different section, | |
795 | whether we have tried to relax this frag yet, and whether we have | |
796 | ever extended a PC relative fragment because of a shift count. */ | |
797 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
798 | (0x80000000 \ | |
799 | | ((type) & 0xff) \ | |
800 | | ((small) ? 0x100 : 0) \ | |
801 | | ((ext) ? 0x200 : 0) \ | |
802 | | ((dslot) ? 0x400 : 0) \ | |
803 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 804 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
805 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
806 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
807 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
808 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
809 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
810 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
811 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
812 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
813 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
814 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
815 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
816 | |
817 | /* Is the given value a sign-extended 32-bit value? */ | |
818 | #define IS_SEXT_32BIT_NUM(x) \ | |
819 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
820 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
821 | ||
822 | /* Is the given value a sign-extended 16-bit value? */ | |
823 | #define IS_SEXT_16BIT_NUM(x) \ | |
824 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
825 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
826 | ||
bf12938e RS |
827 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
828 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
829 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
830 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
831 | | (((VALUE) & (MASK)) << (SHIFT))) | |
832 | ||
833 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
834 | SHIFT places. */ | |
835 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
836 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
837 | ||
838 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
839 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
840 | ||
841 | include/opcode/mips.h specifies operand fields using the macros | |
842 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
843 | with "MIPS16OP" instead of "OP". */ | |
844 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
845 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
846 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
847 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
848 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
849 | ||
850 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
851 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
852 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
853 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
854 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
855 | MIPS16OP_MASK_##FIELD, \ | |
856 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
857 | \f |
858 | /* Global variables used when generating relaxable macros. See the | |
859 | comment above RELAX_ENCODE for more details about how relaxation | |
860 | is used. */ | |
861 | static struct { | |
862 | /* 0 if we're not emitting a relaxable macro. | |
863 | 1 if we're emitting the first of the two relaxation alternatives. | |
864 | 2 if we're emitting the second alternative. */ | |
865 | int sequence; | |
866 | ||
867 | /* The first relaxable fixup in the current frag. (In other words, | |
868 | the first fixup that refers to relaxable code.) */ | |
869 | fixS *first_fixup; | |
870 | ||
871 | /* sizes[0] says how many bytes of the first alternative are stored in | |
872 | the current frag. Likewise sizes[1] for the second alternative. */ | |
873 | unsigned int sizes[2]; | |
874 | ||
875 | /* The symbol on which the choice of sequence depends. */ | |
876 | symbolS *symbol; | |
877 | } mips_relax; | |
252b5132 | 878 | \f |
584892a6 RS |
879 | /* Global variables used to decide whether a macro needs a warning. */ |
880 | static struct { | |
881 | /* True if the macro is in a branch delay slot. */ | |
882 | bfd_boolean delay_slot_p; | |
883 | ||
884 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
885 | in bytes and sizes[1] is the length of the second alternative. | |
886 | For non-relaxable macros, both elements give the length of the | |
887 | macro in bytes. */ | |
888 | unsigned int sizes[2]; | |
889 | ||
890 | /* The first variant frag for this macro. */ | |
891 | fragS *first_frag; | |
892 | } mips_macro_warning; | |
893 | \f | |
252b5132 RH |
894 | /* Prototypes for static functions. */ |
895 | ||
17a2f251 | 896 | #define internalError() \ |
252b5132 | 897 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
898 | |
899 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
900 | ||
b34976b6 | 901 | static void append_insn |
4d7206a2 | 902 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 903 | static void mips_no_prev_insn (int); |
b34976b6 | 904 | static void mips16_macro_build |
67c0d1eb RS |
905 | (expressionS *, const char *, const char *, va_list); |
906 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
907 | static void macro_start (void); |
908 | static void macro_end (void); | |
17a2f251 TS |
909 | static void macro (struct mips_cl_insn * ip); |
910 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 911 | #ifdef LOSING_COMPILER |
17a2f251 | 912 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 913 | #endif |
17a2f251 TS |
914 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
915 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 916 | static void mips16_immed |
17a2f251 TS |
917 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
918 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 919 | static size_t my_getSmallExpression |
17a2f251 TS |
920 | (expressionS *, bfd_reloc_code_real_type *, char *); |
921 | static void my_getExpression (expressionS *, char *); | |
922 | static void s_align (int); | |
923 | static void s_change_sec (int); | |
924 | static void s_change_section (int); | |
925 | static void s_cons (int); | |
926 | static void s_float_cons (int); | |
927 | static void s_mips_globl (int); | |
928 | static void s_option (int); | |
929 | static void s_mipsset (int); | |
930 | static void s_abicalls (int); | |
931 | static void s_cpload (int); | |
932 | static void s_cpsetup (int); | |
933 | static void s_cplocal (int); | |
934 | static void s_cprestore (int); | |
935 | static void s_cpreturn (int); | |
936 | static void s_gpvalue (int); | |
937 | static void s_gpword (int); | |
938 | static void s_gpdword (int); | |
939 | static void s_cpadd (int); | |
940 | static void s_insn (int); | |
941 | static void md_obj_begin (void); | |
942 | static void md_obj_end (void); | |
943 | static void s_mips_ent (int); | |
944 | static void s_mips_end (int); | |
945 | static void s_mips_frame (int); | |
946 | static void s_mips_mask (int reg_type); | |
947 | static void s_mips_stab (int); | |
948 | static void s_mips_weakext (int); | |
949 | static void s_mips_file (int); | |
950 | static void s_mips_loc (int); | |
951 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 952 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 953 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
954 | |
955 | /* Table and functions used to map between CPU/ISA names, and | |
956 | ISA levels, and CPU numbers. */ | |
957 | ||
e972090a NC |
958 | struct mips_cpu_info |
959 | { | |
e7af610e NC |
960 | const char *name; /* CPU or ISA name. */ |
961 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
962 | int isa; /* ISA level. */ | |
963 | int cpu; /* CPU number (default CPU if ISA). */ | |
964 | }; | |
965 | ||
17a2f251 TS |
966 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
967 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
968 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
969 | \f |
970 | /* Pseudo-op table. | |
971 | ||
972 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
973 | should be defined here, but are currently unsupported: .alias, | |
974 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
975 | ||
976 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
977 | specific to the type of debugging information being generated, and | |
978 | should be defined by the object format: .aent, .begin, .bend, | |
979 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
980 | .vreg. | |
981 | ||
982 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
983 | not MIPS CPU specific, but are also not specific to the object file | |
984 | format. This file is probably the best place to define them, but | |
985 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
986 | .struct. */ | |
987 | ||
e972090a NC |
988 | static const pseudo_typeS mips_pseudo_table[] = |
989 | { | |
beae10d5 | 990 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
991 | {"option", s_option, 0}, |
992 | {"set", s_mipsset, 0}, | |
993 | {"rdata", s_change_sec, 'r'}, | |
994 | {"sdata", s_change_sec, 's'}, | |
995 | {"livereg", s_ignore, 0}, | |
996 | {"abicalls", s_abicalls, 0}, | |
997 | {"cpload", s_cpload, 0}, | |
6478892d TS |
998 | {"cpsetup", s_cpsetup, 0}, |
999 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1000 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1001 | {"cpreturn", s_cpreturn, 0}, |
1002 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1003 | {"gpword", s_gpword, 0}, |
10181a0d | 1004 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1005 | {"cpadd", s_cpadd, 0}, |
1006 | {"insn", s_insn, 0}, | |
1007 | ||
beae10d5 | 1008 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1009 | chips. */ |
1010 | {"asciiz", stringer, 1}, | |
1011 | {"bss", s_change_sec, 'b'}, | |
1012 | {"err", s_err, 0}, | |
1013 | {"half", s_cons, 1}, | |
1014 | {"dword", s_cons, 3}, | |
1015 | {"weakext", s_mips_weakext, 0}, | |
1016 | ||
beae10d5 | 1017 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1018 | here for one reason or another. */ |
1019 | {"align", s_align, 0}, | |
1020 | {"byte", s_cons, 0}, | |
1021 | {"data", s_change_sec, 'd'}, | |
1022 | {"double", s_float_cons, 'd'}, | |
1023 | {"float", s_float_cons, 'f'}, | |
1024 | {"globl", s_mips_globl, 0}, | |
1025 | {"global", s_mips_globl, 0}, | |
1026 | {"hword", s_cons, 1}, | |
1027 | {"int", s_cons, 2}, | |
1028 | {"long", s_cons, 2}, | |
1029 | {"octa", s_cons, 4}, | |
1030 | {"quad", s_cons, 3}, | |
cca86cc8 | 1031 | {"section", s_change_section, 0}, |
252b5132 RH |
1032 | {"short", s_cons, 1}, |
1033 | {"single", s_float_cons, 'f'}, | |
1034 | {"stabn", s_mips_stab, 'n'}, | |
1035 | {"text", s_change_sec, 't'}, | |
1036 | {"word", s_cons, 2}, | |
add56521 | 1037 | |
add56521 | 1038 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1039 | |
43841e91 | 1040 | { NULL, NULL, 0 }, |
252b5132 RH |
1041 | }; |
1042 | ||
e972090a NC |
1043 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1044 | { | |
beae10d5 KH |
1045 | /* These pseudo-ops should be defined by the object file format. |
1046 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1047 | {"aent", s_mips_ent, 1}, |
1048 | {"bgnb", s_ignore, 0}, | |
1049 | {"end", s_mips_end, 0}, | |
1050 | {"endb", s_ignore, 0}, | |
1051 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1052 | {"file", s_mips_file, 0}, |
252b5132 RH |
1053 | {"fmask", s_mips_mask, 'F'}, |
1054 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1055 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1056 | {"mask", s_mips_mask, 'R'}, |
1057 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1058 | { NULL, NULL, 0 }, |
252b5132 RH |
1059 | }; |
1060 | ||
17a2f251 | 1061 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1062 | |
1063 | void | |
17a2f251 | 1064 | mips_pop_insert (void) |
252b5132 RH |
1065 | { |
1066 | pop_insert (mips_pseudo_table); | |
1067 | if (! ECOFF_DEBUGGING) | |
1068 | pop_insert (mips_nonecoff_pseudo_table); | |
1069 | } | |
1070 | \f | |
1071 | /* Symbols labelling the current insn. */ | |
1072 | ||
e972090a NC |
1073 | struct insn_label_list |
1074 | { | |
252b5132 RH |
1075 | struct insn_label_list *next; |
1076 | symbolS *label; | |
1077 | }; | |
1078 | ||
1079 | static struct insn_label_list *insn_labels; | |
1080 | static struct insn_label_list *free_insn_labels; | |
1081 | ||
17a2f251 | 1082 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1083 | |
1084 | static inline void | |
17a2f251 | 1085 | mips_clear_insn_labels (void) |
252b5132 RH |
1086 | { |
1087 | register struct insn_label_list **pl; | |
1088 | ||
1089 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1090 | ; | |
1091 | *pl = insn_labels; | |
1092 | insn_labels = NULL; | |
1093 | } | |
1094 | \f | |
1095 | static char *expr_end; | |
1096 | ||
1097 | /* Expressions which appear in instructions. These are set by | |
1098 | mips_ip. */ | |
1099 | ||
1100 | static expressionS imm_expr; | |
5f74bc13 | 1101 | static expressionS imm2_expr; |
252b5132 RH |
1102 | static expressionS offset_expr; |
1103 | ||
1104 | /* Relocs associated with imm_expr and offset_expr. */ | |
1105 | ||
f6688943 TS |
1106 | static bfd_reloc_code_real_type imm_reloc[3] |
1107 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1108 | static bfd_reloc_code_real_type offset_reloc[3] | |
1109 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1110 | |
252b5132 RH |
1111 | /* These are set by mips16_ip if an explicit extension is used. */ |
1112 | ||
b34976b6 | 1113 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1114 | |
7ed4a06a | 1115 | #ifdef OBJ_ELF |
ecb4347a DJ |
1116 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1117 | ECOFF debugging. */ | |
252b5132 RH |
1118 | |
1119 | static segT pdr_seg; | |
7ed4a06a | 1120 | #endif |
252b5132 | 1121 | |
e013f690 TS |
1122 | /* The default target format to use. */ |
1123 | ||
1124 | const char * | |
17a2f251 | 1125 | mips_target_format (void) |
e013f690 TS |
1126 | { |
1127 | switch (OUTPUT_FLAVOR) | |
1128 | { | |
e013f690 TS |
1129 | case bfd_target_ecoff_flavour: |
1130 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1131 | case bfd_target_coff_flavour: | |
1132 | return "pe-mips"; | |
1133 | case bfd_target_elf_flavour: | |
1134 | #ifdef TE_TMIPS | |
cfe86eaa | 1135 | /* This is traditional mips. */ |
e013f690 | 1136 | return (target_big_endian |
cfe86eaa TS |
1137 | ? (HAVE_64BIT_OBJECTS |
1138 | ? "elf64-tradbigmips" | |
1139 | : (HAVE_NEWABI | |
1140 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1141 | : (HAVE_64BIT_OBJECTS | |
1142 | ? "elf64-tradlittlemips" | |
1143 | : (HAVE_NEWABI | |
1144 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1145 | #else |
1146 | return (target_big_endian | |
cfe86eaa TS |
1147 | ? (HAVE_64BIT_OBJECTS |
1148 | ? "elf64-bigmips" | |
1149 | : (HAVE_NEWABI | |
1150 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1151 | : (HAVE_64BIT_OBJECTS | |
1152 | ? "elf64-littlemips" | |
1153 | : (HAVE_NEWABI | |
1154 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1155 | #endif |
1156 | default: | |
1157 | abort (); | |
1158 | return NULL; | |
1159 | } | |
1160 | } | |
1161 | ||
156c2f8b NC |
1162 | /* This function is called once, at assembler startup time. It should |
1163 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1164 | ||
252b5132 | 1165 | void |
17a2f251 | 1166 | md_begin (void) |
252b5132 | 1167 | { |
252b5132 | 1168 | register const char *retval = NULL; |
156c2f8b | 1169 | int i = 0; |
252b5132 | 1170 | int broken = 0; |
1f25f5d3 | 1171 | |
fef14a42 | 1172 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1173 | as_warn (_("Could not set architecture and machine")); |
1174 | ||
252b5132 RH |
1175 | op_hash = hash_new (); |
1176 | ||
1177 | for (i = 0; i < NUMOPCODES;) | |
1178 | { | |
1179 | const char *name = mips_opcodes[i].name; | |
1180 | ||
17a2f251 | 1181 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1182 | if (retval != NULL) |
1183 | { | |
1184 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1185 | mips_opcodes[i].name, retval); | |
1186 | /* Probably a memory allocation problem? Give up now. */ | |
1187 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1188 | } | |
1189 | do | |
1190 | { | |
1191 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1192 | { | |
1193 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1194 | broken = 1; | |
1195 | } | |
1196 | ++i; | |
1197 | } | |
1198 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1199 | } | |
1200 | ||
1201 | mips16_op_hash = hash_new (); | |
1202 | ||
1203 | i = 0; | |
1204 | while (i < bfd_mips16_num_opcodes) | |
1205 | { | |
1206 | const char *name = mips16_opcodes[i].name; | |
1207 | ||
17a2f251 | 1208 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1209 | if (retval != NULL) |
1210 | as_fatal (_("internal: can't hash `%s': %s"), | |
1211 | mips16_opcodes[i].name, retval); | |
1212 | do | |
1213 | { | |
1214 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1215 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1216 | != mips16_opcodes[i].match)) | |
1217 | { | |
1218 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1219 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1220 | broken = 1; | |
1221 | } | |
1222 | ++i; | |
1223 | } | |
1224 | while (i < bfd_mips16_num_opcodes | |
1225 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1226 | } | |
1227 | ||
1228 | if (broken) | |
1229 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1230 | ||
1231 | /* We add all the general register names to the symbol table. This | |
1232 | helps us detect invalid uses of them. */ | |
1233 | for (i = 0; i < 32; i++) | |
1234 | { | |
1235 | char buf[5]; | |
1236 | ||
1237 | sprintf (buf, "$%d", i); | |
1238 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1239 | &zero_address_frag)); | |
1240 | } | |
76db943d TS |
1241 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1242 | &zero_address_frag)); | |
252b5132 RH |
1243 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1244 | &zero_address_frag)); | |
1245 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1246 | &zero_address_frag)); | |
1247 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1248 | &zero_address_frag)); | |
1249 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1250 | &zero_address_frag)); | |
1251 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1252 | &zero_address_frag)); | |
1253 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1254 | &zero_address_frag)); | |
85b51719 TS |
1255 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1256 | &zero_address_frag)); | |
252b5132 RH |
1257 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1258 | &zero_address_frag)); | |
1259 | ||
6047c971 AO |
1260 | /* If we don't add these register names to the symbol table, they |
1261 | may end up being added as regular symbols by operand(), and then | |
1262 | make it to the object file as undefined in case they're not | |
1263 | regarded as local symbols. They're local in o32, since `$' is a | |
1264 | local symbol prefix, but not in n32 or n64. */ | |
1265 | for (i = 0; i < 8; i++) | |
1266 | { | |
1267 | char buf[6]; | |
1268 | ||
1269 | sprintf (buf, "$fcc%i", i); | |
1270 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1271 | &zero_address_frag)); | |
1272 | } | |
1273 | ||
b34976b6 | 1274 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1275 | |
1276 | mips_gprmask = 0; | |
1277 | mips_cprmask[0] = 0; | |
1278 | mips_cprmask[1] = 0; | |
1279 | mips_cprmask[2] = 0; | |
1280 | mips_cprmask[3] = 0; | |
1281 | ||
1282 | /* set the default alignment for the text section (2**2) */ | |
1283 | record_alignment (text_section, 2); | |
1284 | ||
4d0d148d | 1285 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1286 | |
1287 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1288 | { | |
1289 | /* On a native system, sections must be aligned to 16 byte | |
1290 | boundaries. When configured for an embedded ELF target, we | |
1291 | don't bother. */ | |
1292 | if (strcmp (TARGET_OS, "elf") != 0) | |
1293 | { | |
1294 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1295 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1296 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1297 | } | |
1298 | ||
1299 | /* Create a .reginfo section for register masks and a .mdebug | |
1300 | section for debugging information. */ | |
1301 | { | |
1302 | segT seg; | |
1303 | subsegT subseg; | |
1304 | flagword flags; | |
1305 | segT sec; | |
1306 | ||
1307 | seg = now_seg; | |
1308 | subseg = now_subseg; | |
1309 | ||
1310 | /* The ABI says this section should be loaded so that the | |
1311 | running program can access it. However, we don't load it | |
1312 | if we are configured for an embedded target */ | |
1313 | flags = SEC_READONLY | SEC_DATA; | |
1314 | if (strcmp (TARGET_OS, "elf") != 0) | |
1315 | flags |= SEC_ALLOC | SEC_LOAD; | |
1316 | ||
316f5878 | 1317 | if (mips_abi != N64_ABI) |
252b5132 RH |
1318 | { |
1319 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1320 | ||
195325d2 TS |
1321 | bfd_set_section_flags (stdoutput, sec, flags); |
1322 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1323 | |
252b5132 RH |
1324 | #ifdef OBJ_ELF |
1325 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1326 | #endif | |
1327 | } | |
1328 | else | |
1329 | { | |
1330 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1331 | .reginfo section. */ | |
1332 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1333 | bfd_set_section_flags (stdoutput, sec, flags); |
1334 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1335 | |
1336 | #ifdef OBJ_ELF | |
1337 | /* Set up the option header. */ | |
1338 | { | |
1339 | Elf_Internal_Options opthdr; | |
1340 | char *f; | |
1341 | ||
1342 | opthdr.kind = ODK_REGINFO; | |
1343 | opthdr.size = (sizeof (Elf_External_Options) | |
1344 | + sizeof (Elf64_External_RegInfo)); | |
1345 | opthdr.section = 0; | |
1346 | opthdr.info = 0; | |
1347 | f = frag_more (sizeof (Elf_External_Options)); | |
1348 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1349 | (Elf_External_Options *) f); | |
1350 | ||
1351 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1352 | } | |
1353 | #endif | |
1354 | } | |
1355 | ||
1356 | if (ECOFF_DEBUGGING) | |
1357 | { | |
1358 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1359 | (void) bfd_set_section_flags (stdoutput, sec, | |
1360 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1361 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1362 | } | |
ecb4347a | 1363 | #ifdef OBJ_ELF |
dcd410fe | 1364 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1365 | { |
1366 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1367 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1368 | SEC_READONLY | SEC_RELOC | |
1369 | | SEC_DEBUGGING); | |
1370 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1371 | } | |
252b5132 RH |
1372 | #endif |
1373 | ||
1374 | subseg_set (seg, subseg); | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | if (! ECOFF_DEBUGGING) | |
1379 | md_obj_begin (); | |
1380 | } | |
1381 | ||
1382 | void | |
17a2f251 | 1383 | md_mips_end (void) |
252b5132 RH |
1384 | { |
1385 | if (! ECOFF_DEBUGGING) | |
1386 | md_obj_end (); | |
1387 | } | |
1388 | ||
1389 | void | |
17a2f251 | 1390 | md_assemble (char *str) |
252b5132 RH |
1391 | { |
1392 | struct mips_cl_insn insn; | |
f6688943 TS |
1393 | bfd_reloc_code_real_type unused_reloc[3] |
1394 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1395 | |
1396 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1397 | imm2_expr.X_op = O_absent; |
252b5132 | 1398 | offset_expr.X_op = O_absent; |
f6688943 TS |
1399 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1400 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1401 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1402 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1403 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1404 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1405 | |
1406 | if (mips_opts.mips16) | |
1407 | mips16_ip (str, &insn); | |
1408 | else | |
1409 | { | |
1410 | mips_ip (str, &insn); | |
beae10d5 KH |
1411 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1412 | str, insn.insn_opcode)); | |
252b5132 RH |
1413 | } |
1414 | ||
1415 | if (insn_error) | |
1416 | { | |
1417 | as_bad ("%s `%s'", insn_error, str); | |
1418 | return; | |
1419 | } | |
1420 | ||
1421 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1422 | { | |
584892a6 | 1423 | macro_start (); |
252b5132 RH |
1424 | if (mips_opts.mips16) |
1425 | mips16_macro (&insn); | |
1426 | else | |
1427 | macro (&insn); | |
584892a6 | 1428 | macro_end (); |
252b5132 RH |
1429 | } |
1430 | else | |
1431 | { | |
1432 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1433 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1434 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1435 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1436 | else |
4d7206a2 | 1437 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1438 | } |
1439 | } | |
1440 | ||
5919d012 RS |
1441 | /* Return true if the given relocation might need a matching %lo(). |
1442 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1443 | applied to local symbols. */ | |
1444 | ||
1445 | static inline bfd_boolean | |
17a2f251 | 1446 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1447 | { |
3b91255e RS |
1448 | return (HAVE_IN_PLACE_ADDENDS |
1449 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1450 | || reloc == BFD_RELOC_MIPS_GOT16 |
1451 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1452 | } |
1453 | ||
1454 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1455 | relocation. */ | |
1456 | ||
1457 | static inline bfd_boolean | |
17a2f251 | 1458 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1459 | { |
1460 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1461 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1462 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1463 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1464 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1465 | } | |
1466 | ||
252b5132 RH |
1467 | /* See whether instruction IP reads register REG. CLASS is the type |
1468 | of register. */ | |
1469 | ||
1470 | static int | |
17a2f251 TS |
1471 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1472 | enum mips_regclass class) | |
252b5132 RH |
1473 | { |
1474 | if (class == MIPS16_REG) | |
1475 | { | |
1476 | assert (mips_opts.mips16); | |
1477 | reg = mips16_to_32_reg_map[reg]; | |
1478 | class = MIPS_GR_REG; | |
1479 | } | |
1480 | ||
85b51719 TS |
1481 | /* Don't report on general register ZERO, since it never changes. */ |
1482 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1483 | return 0; |
1484 | ||
1485 | if (class == MIPS_FP_REG) | |
1486 | { | |
1487 | assert (! mips_opts.mips16); | |
1488 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1489 | This is not optimal, because it will introduce an unnecessary | |
1490 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1491 | need to distinguish reading both $f0 and $f1 or just one of | |
1492 | them. Note that we don't have to check the other way, | |
1493 | because there is no instruction that sets both $f0 and $f1 | |
1494 | and requires a delay. */ | |
1495 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1496 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1497 | == (reg &~ (unsigned) 1))) |
1498 | return 1; | |
1499 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1500 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1501 | == (reg &~ (unsigned) 1))) |
1502 | return 1; | |
1503 | } | |
1504 | else if (! mips_opts.mips16) | |
1505 | { | |
1506 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1507 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1508 | return 1; |
1509 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1510 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1511 | return 1; |
1512 | } | |
1513 | else | |
1514 | { | |
1515 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1516 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1517 | return 1; |
1518 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1519 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1520 | return 1; |
1521 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1522 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1523 | == reg)) |
1524 | return 1; | |
1525 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1526 | return 1; | |
1527 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1528 | return 1; | |
1529 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1530 | return 1; | |
1531 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1532 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1533 | return 1; |
1534 | } | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | /* This function returns true if modifying a register requires a | |
1540 | delay. */ | |
1541 | ||
1542 | static int | |
17a2f251 | 1543 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1544 | { |
1545 | unsigned long prev_pinfo; | |
1546 | ||
47e39b9d | 1547 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1548 | if (! mips_opts.noreorder |
81912461 ILT |
1549 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1550 | && ! gpr_interlocks) | |
1551 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1552 | && ! cop_interlocks))) | |
252b5132 | 1553 | { |
81912461 ILT |
1554 | /* A load from a coprocessor or from memory. All load delays |
1555 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1556 | /* Itbl support may require additional care here. */ |
252b5132 | 1557 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1558 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1559 | return 1; |
1560 | } | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1566 | handle them specially, such as generating jalx instructions when | |
1567 | needed. We also make them odd for the duration of the assembly, in | |
1568 | order to generate the right sort of code. We will make them even | |
1569 | in the adjust_symtab routine, while leaving them marked. This is | |
1570 | convenient for the debugger and the disassembler. The linker knows | |
1571 | to make them odd again. */ | |
1572 | ||
1573 | static void | |
17a2f251 | 1574 | mips16_mark_labels (void) |
252b5132 RH |
1575 | { |
1576 | if (mips_opts.mips16) | |
1577 | { | |
1578 | struct insn_label_list *l; | |
98aa84af | 1579 | valueT val; |
252b5132 RH |
1580 | |
1581 | for (l = insn_labels; l != NULL; l = l->next) | |
1582 | { | |
1583 | #ifdef OBJ_ELF | |
1584 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1585 | S_SET_OTHER (l->label, STO_MIPS16); | |
1586 | #endif | |
98aa84af AM |
1587 | val = S_GET_VALUE (l->label); |
1588 | if ((val & 1) == 0) | |
1589 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1590 | } |
1591 | } | |
1592 | } | |
1593 | ||
4d7206a2 RS |
1594 | /* End the current frag. Make it a variant frag and record the |
1595 | relaxation info. */ | |
1596 | ||
1597 | static void | |
1598 | relax_close_frag (void) | |
1599 | { | |
584892a6 | 1600 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1601 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1602 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1603 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1604 | ||
1605 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1606 | mips_relax.first_fixup = 0; | |
1607 | } | |
1608 | ||
1609 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1610 | See the comment above RELAX_ENCODE for more details. */ | |
1611 | ||
1612 | static void | |
1613 | relax_start (symbolS *symbol) | |
1614 | { | |
1615 | assert (mips_relax.sequence == 0); | |
1616 | mips_relax.sequence = 1; | |
1617 | mips_relax.symbol = symbol; | |
1618 | } | |
1619 | ||
1620 | /* Start generating the second version of a relaxable sequence. | |
1621 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1622 | |
1623 | static void | |
4d7206a2 RS |
1624 | relax_switch (void) |
1625 | { | |
1626 | assert (mips_relax.sequence == 1); | |
1627 | mips_relax.sequence = 2; | |
1628 | } | |
1629 | ||
1630 | /* End the current relaxable sequence. */ | |
1631 | ||
1632 | static void | |
1633 | relax_end (void) | |
1634 | { | |
1635 | assert (mips_relax.sequence == 2); | |
1636 | relax_close_frag (); | |
1637 | mips_relax.sequence = 0; | |
1638 | } | |
1639 | ||
1640 | /* Output an instruction. IP is the instruction information. | |
1641 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1642 | RELOC_TYPE. */ | |
1643 | ||
1644 | static void | |
1645 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1646 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1647 | { |
1648 | register unsigned long prev_pinfo, pinfo; | |
1649 | char *f; | |
f6688943 | 1650 | fixS *fixp[3]; |
252b5132 | 1651 | int nops = 0; |
895921c9 MR |
1652 | relax_stateT prev_insn_frag_type = 0; |
1653 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1654 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1655 | |
1656 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1657 | mips16_mark_labels (); |
252b5132 | 1658 | |
47e39b9d | 1659 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 RH |
1660 | pinfo = ip->insn_mo->pinfo; |
1661 | ||
4d7206a2 RS |
1662 | if (mips_relax.sequence != 2 |
1663 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1664 | { |
1665 | int prev_prev_nop; | |
1666 | ||
1667 | /* If the previous insn required any delay slots, see if we need | |
1668 | to insert a NOP or two. There are eight kinds of possible | |
1669 | hazards, of which an instruction can have at most one type. | |
1670 | (1) a load from memory delay | |
1671 | (2) a load from a coprocessor delay | |
1672 | (3) an unconditional branch delay | |
1673 | (4) a conditional branch delay | |
1674 | (5) a move to coprocessor register delay | |
1675 | (6) a load coprocessor register from memory delay | |
1676 | (7) a coprocessor condition code delay | |
1677 | (8) a HI/LO special register delay | |
1678 | ||
1679 | There are a lot of optimizations we could do that we don't. | |
1680 | In particular, we do not, in general, reorder instructions. | |
1681 | If you use gcc with optimization, it will reorder | |
1682 | instructions and generally do much more optimization then we | |
1683 | do here; repeating all that work in the assembler would only | |
1684 | benefit hand written assembly code, and does not seem worth | |
1685 | it. */ | |
1686 | ||
1687 | /* This is how a NOP is emitted. */ | |
1688 | #define emit_nop() \ | |
1689 | (mips_opts.mips16 \ | |
1690 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1691 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1692 | ||
1693 | /* The previous insn might require a delay slot, depending upon | |
1694 | the contents of the current insn. */ | |
1695 | if (! mips_opts.mips16 | |
81912461 ILT |
1696 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1697 | && ! gpr_interlocks) | |
1698 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1699 | && ! cop_interlocks))) | |
252b5132 RH |
1700 | { |
1701 | /* A load from a coprocessor or from memory. All load | |
1702 | delays delay the use of general register rt for one | |
81912461 | 1703 | instruction. */ |
beae10d5 | 1704 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1705 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1706 | if (mips_optimize == 0 | |
bf12938e | 1707 | || insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
1708 | MIPS_GR_REG)) |
1709 | ++nops; | |
1710 | } | |
1711 | else if (! mips_opts.mips16 | |
252b5132 | 1712 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1713 | && ! cop_interlocks) |
81912461 ILT |
1714 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1715 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1716 | { |
1717 | /* A generic coprocessor delay. The previous instruction | |
1718 | modified a coprocessor general or control register. If | |
1719 | it modified a control register, we need to avoid any | |
1720 | coprocessor instruction (this is probably not always | |
1721 | required, but it sometimes is). If it modified a general | |
1722 | register, we avoid using that register. | |
1723 | ||
252b5132 RH |
1724 | This case is not handled very well. There is no special |
1725 | knowledge of CP0 handling, and the coprocessors other | |
1726 | than the floating point unit are not distinguished at | |
1727 | all. */ | |
1728 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1729 | Need to modify this to include knowledge about |
252b5132 RH |
1730 | user specified delays! */ |
1731 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1732 | { | |
1733 | if (mips_optimize == 0 | |
bf12938e | 1734 | || insn_uses_reg (ip, EXTRACT_OPERAND (FT, history[0]), |
252b5132 RH |
1735 | MIPS_FP_REG)) |
1736 | ++nops; | |
1737 | } | |
1738 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1739 | { | |
1740 | if (mips_optimize == 0 | |
bf12938e | 1741 | || insn_uses_reg (ip, EXTRACT_OPERAND (FS, history[0]), |
252b5132 RH |
1742 | MIPS_FP_REG)) |
1743 | ++nops; | |
1744 | } | |
1745 | else | |
1746 | { | |
1747 | /* We don't know exactly what the previous instruction | |
1748 | does. If the current instruction uses a coprocessor | |
1749 | register, we must insert a NOP. If previous | |
1750 | instruction may set the condition codes, and the | |
1751 | current instruction uses them, we must insert two | |
1752 | NOPS. */ | |
bdaaa2e1 | 1753 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1754 | if (mips_optimize == 0 |
1755 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1756 | && (pinfo & INSN_READ_COND_CODE))) | |
1757 | nops += 2; | |
1758 | else if (pinfo & INSN_COP) | |
1759 | ++nops; | |
1760 | } | |
1761 | } | |
1762 | else if (! mips_opts.mips16 | |
252b5132 RH |
1763 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1764 | && ! cop_interlocks) | |
1765 | { | |
1766 | /* The previous instruction sets the coprocessor condition | |
1767 | codes, but does not require a general coprocessor delay | |
1768 | (this means it is a floating point comparison | |
1769 | instruction). If this instruction uses the condition | |
1770 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1771 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1772 | if (mips_optimize == 0 |
1773 | || (pinfo & INSN_READ_COND_CODE)) | |
1774 | ++nops; | |
1775 | } | |
6b76fefe CM |
1776 | |
1777 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1778 | previous insn was an mfhi/mflo and the current insn | |
1779 | reads the register that the mfhi/mflo wrote to, then | |
1780 | insert two nops. */ | |
1781 | ||
1782 | else if (mips_7000_hilo_fix | |
1783 | && MF_HILO_INSN (prev_pinfo) | |
bf12938e | 1784 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
beae10d5 | 1785 | MIPS_GR_REG)) |
6b76fefe CM |
1786 | { |
1787 | nops += 2; | |
1788 | } | |
1789 | ||
1790 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1791 | 2nd previous insn was an mfhi/mflo and the current insn | |
1792 | reads the register that the mfhi/mflo wrote to, then | |
1793 | insert one nop. */ | |
1794 | ||
1795 | else if (mips_7000_hilo_fix | |
47e39b9d | 1796 | && MF_HILO_INSN (history[1].insn_opcode) |
bf12938e RS |
1797 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[1]), |
1798 | MIPS_GR_REG)) | |
bdaaa2e1 | 1799 | |
6b76fefe | 1800 | { |
f9419b05 | 1801 | ++nops; |
6b76fefe | 1802 | } |
bdaaa2e1 | 1803 | |
252b5132 RH |
1804 | else if (prev_pinfo & INSN_READ_LO) |
1805 | { | |
1806 | /* The previous instruction reads the LO register; if the | |
1807 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1808 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1809 | Also the tx39's multiply instructions can be executed |
1810 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1811 | though the tx39's divide insns still do require the |
1812 | delay. */ | |
252b5132 | 1813 | if (! (hilo_interlocks |
048cdf86 | 1814 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1815 | && (mips_optimize == 0 |
1816 | || (pinfo & INSN_WRITE_LO))) | |
1817 | nops += 2; | |
1818 | /* Most mips16 branch insns don't have a delay slot. | |
1819 | If a read from LO is immediately followed by a branch | |
1820 | to a write to LO we have a read followed by a write | |
1821 | less than 2 insns away. We assume the target of | |
1822 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1823 | between a read and an immediately following branch. */ |
252b5132 RH |
1824 | else if (mips_opts.mips16 |
1825 | && (mips_optimize == 0 | |
1826 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1827 | ++nops; |
252b5132 | 1828 | } |
47e39b9d | 1829 | else if (history[0].insn_mo->pinfo & INSN_READ_HI) |
252b5132 RH |
1830 | { |
1831 | /* The previous instruction reads the HI register; if the | |
1832 | current instruction writes to the HI register, we must | |
1833 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1834 | Also the note tx39's multiply above. */ |
252b5132 | 1835 | if (! (hilo_interlocks |
048cdf86 | 1836 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1837 | && (mips_optimize == 0 |
1838 | || (pinfo & INSN_WRITE_HI))) | |
1839 | nops += 2; | |
1840 | /* Most mips16 branch insns don't have a delay slot. | |
1841 | If a read from HI is immediately followed by a branch | |
1842 | to a write to HI we have a read followed by a write | |
1843 | less than 2 insns away. We assume the target of | |
1844 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1845 | between a read and an immediately following branch. */ |
252b5132 RH |
1846 | else if (mips_opts.mips16 |
1847 | && (mips_optimize == 0 | |
1848 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1849 | ++nops; |
252b5132 RH |
1850 | } |
1851 | ||
1852 | /* If the previous instruction was in a noreorder section, then | |
1853 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1854 | /* Itbl support may require additional care here. */ |
47e39b9d | 1855 | if (history[0].noreorder_p) |
252b5132 RH |
1856 | nops = 0; |
1857 | ||
1858 | /* There are two cases which require two intervening | |
1859 | instructions: 1) setting the condition codes using a move to | |
1860 | coprocessor instruction which requires a general coprocessor | |
1861 | delay and then reading the condition codes 2) reading the HI | |
1862 | or LO register and then writing to it (except on processors | |
1863 | which have interlocks). If we are not already emitting a NOP | |
1864 | instruction, we must check for these cases compared to the | |
1865 | instruction previous to the previous instruction. */ | |
1866 | if ((! mips_opts.mips16 | |
47e39b9d RS |
1867 | && (history[1].insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1868 | && (history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
252b5132 RH |
1869 | && (pinfo & INSN_READ_COND_CODE) |
1870 | && ! cop_interlocks) | |
47e39b9d | 1871 | || ((history[1].insn_mo->pinfo & INSN_READ_LO) |
252b5132 RH |
1872 | && (pinfo & INSN_WRITE_LO) |
1873 | && ! (hilo_interlocks | |
048cdf86 | 1874 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
47e39b9d | 1875 | || ((history[1].insn_mo->pinfo & INSN_READ_HI) |
252b5132 RH |
1876 | && (pinfo & INSN_WRITE_HI) |
1877 | && ! (hilo_interlocks | |
048cdf86 | 1878 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1879 | prev_prev_nop = 1; |
1880 | else | |
1881 | prev_prev_nop = 0; | |
1882 | ||
47e39b9d | 1883 | if (history[1].noreorder_p) |
252b5132 RH |
1884 | prev_prev_nop = 0; |
1885 | ||
1886 | if (prev_prev_nop && nops == 0) | |
1887 | ++nops; | |
1888 | ||
47e39b9d | 1889 | if (mips_fix_vr4120 && history[0].insn_mo->name) |
60b63b72 RS |
1890 | { |
1891 | /* We're out of bits in pinfo, so we must resort to string | |
1892 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1893 | limited to the VR4120 instruction set. */ |
60b63b72 | 1894 | int min_nops = 0; |
47e39b9d | 1895 | const char *pn = history[0].insn_mo->name; |
60b63b72 | 1896 | const char *tn = ip->insn_mo->name; |
532c738a RS |
1897 | if (strncmp (pn, "macc", 4) == 0 |
1898 | || strncmp (pn, "dmacc", 5) == 0) | |
60b63b72 RS |
1899 | { |
1900 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1901 | if (strstr (tn, "div")) | |
532c738a | 1902 | min_nops = 1; |
60b63b72 | 1903 | |
532c738a RS |
1904 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
1905 | instruction is executed immediately after a MACC or | |
1906 | DMACC instruction, the result of [either instruction] | |
1907 | is incorrect." */ | |
1908 | if (strncmp (tn, "mult", 4) == 0 | |
1909 | || strncmp (tn, "dmult", 5) == 0) | |
1910 | min_nops = 1; | |
1911 | ||
1912 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. | |
1913 | Applies on top of VR4181A MD(1) errata. */ | |
1914 | if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0) | |
1915 | min_nops = 1; | |
60b63b72 RS |
1916 | |
1917 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1918 | if (strcmp (tn, "mtlo") == 0 | |
1919 | || strcmp (tn, "mthi") == 0) | |
532c738a | 1920 | min_nops = 1; |
60b63b72 | 1921 | } |
532c738a RS |
1922 | else if (strncmp (pn, "dmult", 5) == 0 |
1923 | && (strncmp (tn, "dmult", 5) == 0 | |
1924 | || strncmp (tn, "dmacc", 5) == 0)) | |
60b63b72 RS |
1925 | { |
1926 | /* Here is the rest of errata 23. */ | |
1927 | min_nops = 1; | |
1928 | } | |
532c738a RS |
1929 | else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div")) |
1930 | && (strncmp (tn, "macc", 4) == 0 | |
1931 | || strncmp (tn, "dmacc", 5) == 0)) | |
1932 | { | |
1933 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1934 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1935 | DDIV or DDIVU instruction, the result of the MACC or | |
1936 | DMACC instruction is incorrect.". This partly overlaps | |
1937 | the workaround for errata 23. */ | |
1938 | min_nops = 1; | |
1939 | } | |
60b63b72 RS |
1940 | if (nops < min_nops) |
1941 | nops = min_nops; | |
1942 | } | |
1943 | ||
252b5132 RH |
1944 | /* If we are being given a nop instruction, don't bother with |
1945 | one of the nops we would otherwise output. This will only | |
1946 | happen when a nop instruction is used with mips_optimize set | |
1947 | to 0. */ | |
1948 | if (nops > 0 | |
1949 | && ! mips_opts.noreorder | |
156c2f8b | 1950 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1951 | --nops; |
1952 | ||
1953 | /* Now emit the right number of NOP instructions. */ | |
1954 | if (nops > 0 && ! mips_opts.noreorder) | |
1955 | { | |
1956 | fragS *old_frag; | |
1957 | unsigned long old_frag_offset; | |
1958 | int i; | |
1959 | struct insn_label_list *l; | |
1960 | ||
1961 | old_frag = frag_now; | |
1962 | old_frag_offset = frag_now_fix (); | |
1963 | ||
1964 | for (i = 0; i < nops; i++) | |
1965 | emit_nop (); | |
1966 | ||
1967 | if (listing) | |
1968 | { | |
1969 | listing_prev_line (); | |
1970 | /* We may be at the start of a variant frag. In case we | |
1971 | are, make sure there is enough space for the frag | |
1972 | after the frags created by listing_prev_line. The | |
1973 | argument to frag_grow here must be at least as large | |
1974 | as the argument to all other calls to frag_grow in | |
1975 | this file. We don't have to worry about being in the | |
1976 | middle of a variant frag, because the variants insert | |
1977 | all needed nop instructions themselves. */ | |
1978 | frag_grow (40); | |
1979 | } | |
1980 | ||
1981 | for (l = insn_labels; l != NULL; l = l->next) | |
1982 | { | |
98aa84af AM |
1983 | valueT val; |
1984 | ||
252b5132 | 1985 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1986 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1987 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1988 | /* mips16 text labels are stored as odd. */ |
1989 | if (mips_opts.mips16) | |
f9419b05 | 1990 | ++val; |
98aa84af | 1991 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1992 | } |
1993 | ||
1994 | #ifndef NO_ECOFF_DEBUGGING | |
1995 | if (ECOFF_DEBUGGING) | |
1996 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1997 | #endif | |
1998 | } | |
1999 | else if (prev_nop_frag != NULL) | |
2000 | { | |
2001 | /* We have a frag holding nops we may be able to remove. If | |
2002 | we don't need any nops, we can decrease the size of | |
2003 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 2004 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
2005 | if (prev_nop_frag_since == 0) |
2006 | { | |
2007 | if (nops == 0) | |
2008 | { | |
2009 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2010 | --prev_nop_frag_holds; | |
2011 | } | |
2012 | else | |
2013 | prev_nop_frag_required += nops; | |
2014 | } | |
2015 | else | |
2016 | { | |
2017 | if (prev_prev_nop == 0) | |
2018 | { | |
2019 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2020 | --prev_nop_frag_holds; | |
2021 | } | |
2022 | else | |
2023 | ++prev_nop_frag_required; | |
2024 | } | |
2025 | ||
2026 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2027 | prev_nop_frag = NULL; | |
2028 | ||
2029 | ++prev_nop_frag_since; | |
2030 | ||
2031 | /* Sanity check: by the time we reach the second instruction | |
2032 | after prev_nop_frag, we should have used up all the nops | |
2033 | one way or another. */ | |
2034 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2035 | } | |
2036 | } | |
2037 | ||
58e2ea4d MR |
2038 | #ifdef OBJ_ELF |
2039 | /* The value passed to dwarf2_emit_insn is the distance between | |
2040 | the beginning of the current instruction and the address that | |
2041 | should be recorded in the debug tables. For MIPS16 debug info | |
2042 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2043 | address higher by one than the current. */ | |
2044 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2045 | #endif | |
2046 | ||
895921c9 | 2047 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2048 | if (history[0].frag) |
2049 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2050 | |
4d7206a2 | 2051 | if (address_expr |
0b25d3e6 | 2052 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2053 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2054 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2055 | && mips_relax_branch | |
2056 | /* Don't try branch relaxation within .set nomacro, or within | |
2057 | .set noat if we use $at for PIC computations. If it turns | |
2058 | out that the branch was out-of-range, we'll get an error. */ | |
2059 | && !mips_opts.warn_about_macros | |
2060 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2061 | && !mips_opts.mips16) | |
2062 | { | |
895921c9 | 2063 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2064 | f = frag_var (rs_machine_dependent, |
2065 | relaxed_branch_length | |
2066 | (NULL, NULL, | |
2067 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2068 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2069 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2070 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2071 | pinfo & INSN_COND_BRANCH_LIKELY, |
2072 | pinfo & INSN_WRITE_GPR_31, | |
2073 | 0), | |
2074 | address_expr->X_add_symbol, | |
2075 | address_expr->X_add_number, | |
2076 | 0); | |
2077 | *reloc_type = BFD_RELOC_UNUSED; | |
2078 | } | |
2079 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2080 | { |
2081 | /* We need to set up a variant frag. */ | |
2082 | assert (mips_opts.mips16 && address_expr != NULL); | |
2083 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2084 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2085 | mips16_small, mips16_ext, |
2086 | (prev_pinfo | |
2087 | & INSN_UNCOND_BRANCH_DELAY), | |
2fa15973 | 2088 | history[0].mips16_absolute_jump_p), |
c4e7957c | 2089 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2090 | } |
252b5132 RH |
2091 | else if (mips_opts.mips16 |
2092 | && ! ip->use_extend | |
f6688943 | 2093 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2094 | { |
2095 | /* Make sure there is enough room to swap this instruction with | |
2096 | a following jump instruction. */ | |
2097 | frag_grow (6); | |
2098 | f = frag_more (2); | |
2099 | } | |
2100 | else | |
2101 | { | |
2102 | if (mips_opts.mips16 | |
2103 | && mips_opts.noreorder | |
2104 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2105 | as_warn (_("extended instruction in delay slot")); | |
2106 | ||
4d7206a2 RS |
2107 | if (mips_relax.sequence) |
2108 | { | |
2109 | /* If we've reached the end of this frag, turn it into a variant | |
2110 | frag and record the information for the instructions we've | |
2111 | written so far. */ | |
2112 | if (frag_room () < 4) | |
2113 | relax_close_frag (); | |
2114 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2115 | } | |
2116 | ||
584892a6 RS |
2117 | if (mips_relax.sequence != 2) |
2118 | mips_macro_warning.sizes[0] += 4; | |
2119 | if (mips_relax.sequence != 1) | |
2120 | mips_macro_warning.sizes[1] += 4; | |
2121 | ||
252b5132 RH |
2122 | f = frag_more (4); |
2123 | } | |
2124 | ||
f6688943 | 2125 | fixp[0] = fixp[1] = fixp[2] = NULL; |
01a3f561 | 2126 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2127 | { |
2128 | if (address_expr->X_op == O_constant) | |
2129 | { | |
f17c130b | 2130 | unsigned int tmp; |
f6688943 TS |
2131 | |
2132 | switch (*reloc_type) | |
252b5132 RH |
2133 | { |
2134 | case BFD_RELOC_32: | |
2135 | ip->insn_opcode |= address_expr->X_add_number; | |
2136 | break; | |
2137 | ||
f6688943 | 2138 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2139 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2140 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2141 | break; |
2142 | ||
2143 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2144 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2145 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2146 | break; |
2147 | ||
2148 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2149 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2150 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2151 | break; |
2152 | ||
2153 | case BFD_RELOC_HI16: | |
2154 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2155 | break; | |
2156 | ||
01a3f561 | 2157 | case BFD_RELOC_UNUSED: |
252b5132 | 2158 | case BFD_RELOC_LO16: |
ed6fb7bd | 2159 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2160 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2161 | break; | |
2162 | ||
2163 | case BFD_RELOC_MIPS_JMP: | |
2164 | if ((address_expr->X_add_number & 3) != 0) | |
2165 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2166 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2167 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2168 | as_bad (_("jump address range overflow (0x%lx)"), |
2169 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2170 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2171 | break; | |
2172 | ||
2173 | case BFD_RELOC_MIPS16_JMP: | |
2174 | if ((address_expr->X_add_number & 3) != 0) | |
2175 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2176 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2177 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2178 | as_bad (_("jump address range overflow (0x%lx)"), |
2179 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2180 | ip->insn_opcode |= |
2181 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2182 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2183 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2184 | break; | |
2185 | ||
252b5132 RH |
2186 | case BFD_RELOC_16_PCREL_S2: |
2187 | goto need_reloc; | |
2188 | ||
2189 | default: | |
2190 | internalError (); | |
2191 | } | |
2192 | } | |
01a3f561 | 2193 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2194 | need_reloc: |
4d7206a2 RS |
2195 | { |
2196 | reloc_howto_type *howto; | |
2197 | int i; | |
34ce925e | 2198 | |
4d7206a2 RS |
2199 | /* In a compound relocation, it is the final (outermost) |
2200 | operator that determines the relocated field. */ | |
2201 | for (i = 1; i < 3; i++) | |
2202 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2203 | break; | |
34ce925e | 2204 | |
4d7206a2 RS |
2205 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2206 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2207 | bfd_get_reloc_size(howto), | |
2208 | address_expr, | |
2209 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2210 | reloc_type[0]); | |
2211 | ||
2212 | /* These relocations can have an addend that won't fit in | |
2213 | 4 octets for 64bit assembly. */ | |
2214 | if (HAVE_64BIT_GPRS | |
2215 | && ! howto->partial_inplace | |
2216 | && (reloc_type[0] == BFD_RELOC_16 | |
2217 | || reloc_type[0] == BFD_RELOC_32 | |
2218 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2219 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2220 | || reloc_type[0] == BFD_RELOC_LO16 | |
2221 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2222 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2223 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2224 | || reloc_type[0] == BFD_RELOC_64 | |
2225 | || reloc_type[0] == BFD_RELOC_CTOR | |
2226 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2227 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2228 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2229 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2230 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2231 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2232 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2233 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2234 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
4d7206a2 RS |
2235 | fixp[0]->fx_no_overflow = 1; |
2236 | ||
2237 | if (mips_relax.sequence) | |
2238 | { | |
2239 | if (mips_relax.first_fixup == 0) | |
2240 | mips_relax.first_fixup = fixp[0]; | |
2241 | } | |
2242 | else if (reloc_needs_lo_p (*reloc_type)) | |
2243 | { | |
2244 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2245 | |
4d7206a2 RS |
2246 | /* Reuse the last entry if it already has a matching %lo. */ |
2247 | hi_fixup = mips_hi_fixup_list; | |
2248 | if (hi_fixup == 0 | |
2249 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2250 | { | |
2251 | hi_fixup = ((struct mips_hi_fixup *) | |
2252 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2253 | hi_fixup->next = mips_hi_fixup_list; | |
2254 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2255 | } |
4d7206a2 RS |
2256 | hi_fixup->fixp = fixp[0]; |
2257 | hi_fixup->seg = now_seg; | |
2258 | } | |
f6688943 | 2259 | |
4d7206a2 RS |
2260 | /* Add fixups for the second and third relocations, if given. |
2261 | Note that the ABI allows the second relocation to be | |
2262 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2263 | moment we only use RSS_UNDEF, but we could add support | |
2264 | for the others if it ever becomes necessary. */ | |
2265 | for (i = 1; i < 3; i++) | |
2266 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2267 | { | |
6e1304d8 RS |
2268 | fixp[i] = fix_new (frag_now, fixp[0]->fx_where, |
2269 | fixp[0]->fx_size, NULL, 0, | |
2270 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2271 | |
2272 | /* Use fx_tcbit to mark compound relocs. */ | |
2273 | fixp[0]->fx_tcbit = 1; | |
2274 | fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2275 | } |
252b5132 RH |
2276 | } |
2277 | } | |
2278 | ||
2279 | if (! mips_opts.mips16) | |
58e2ea4d | 2280 | md_number_to_chars (f, ip->insn_opcode, 4); |
f6688943 | 2281 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2282 | { |
2283 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2284 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2285 | } | |
2286 | else | |
2287 | { | |
2288 | if (ip->use_extend) | |
2289 | { | |
2290 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2291 | f += 2; | |
2292 | } | |
2293 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2294 | } | |
2295 | ||
2296 | /* Update the register mask information. */ | |
2297 | if (! mips_opts.mips16) | |
2298 | { | |
2299 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2300 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2301 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2302 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2303 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2304 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2305 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2306 | mips_gprmask |= 1 << RA; |
252b5132 | 2307 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2308 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2309 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2310 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2311 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2312 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2313 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2314 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2315 | if (pinfo & INSN_COP) |
2316 | { | |
bdaaa2e1 KH |
2317 | /* We don't keep enough information to sort these cases out. |
2318 | The itbl support does keep this information however, although | |
2319 | we currently don't support itbl fprmats as part of the cop | |
2320 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2321 | } |
2322 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2323 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2324 | } |
2325 | else | |
2326 | { | |
2327 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2328 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2329 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2330 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2331 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2332 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2333 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2334 | mips_gprmask |= 1 << TREG; | |
2335 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2336 | mips_gprmask |= 1 << SP; | |
2337 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2338 | mips_gprmask |= 1 << RA; | |
2339 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2340 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2341 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2342 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2343 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2344 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2345 | } |
2346 | ||
4d7206a2 | 2347 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2348 | { |
2349 | /* Filling the branch delay slot is more complex. We try to | |
2350 | switch the branch with the previous instruction, which we can | |
2351 | do if the previous instruction does not set up a condition | |
2352 | that the branch tests and if the branch is not itself the | |
2353 | target of any branch. */ | |
2354 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2355 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2356 | { | |
2357 | if (mips_optimize < 2 | |
2358 | /* If we have seen .set volatile or .set nomove, don't | |
2359 | optimize. */ | |
2360 | || mips_opts.nomove != 0 | |
2361 | /* If we had to emit any NOP instructions, then we | |
2362 | already know we can not swap. */ | |
2363 | || nops != 0 | |
a38419a5 RS |
2364 | /* We can't swap if the previous instruction's position |
2365 | is fixed. */ | |
2366 | || history[0].fixed_p | |
252b5132 RH |
2367 | /* If the previous previous insn was in a .set |
2368 | noreorder, we can't swap. Actually, the MIPS | |
2369 | assembler will swap in this situation. However, gcc | |
2370 | configured -with-gnu-as will generate code like | |
2371 | .set noreorder | |
2372 | lw $4,XXX | |
2373 | .set reorder | |
2374 | INSN | |
2375 | bne $4,$0,foo | |
2376 | in which we can not swap the bne and INSN. If gcc is | |
2377 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2378 | .set pseudo-ops. */ |
47e39b9d | 2379 | || history[1].noreorder_p |
252b5132 RH |
2380 | /* If the branch is itself the target of a branch, we |
2381 | can not swap. We cheat on this; all we check for is | |
2382 | whether there is a label on this instruction. If | |
2383 | there are any branches to anything other than a | |
2384 | label, users must use .set noreorder. */ | |
2385 | || insn_labels != NULL | |
895921c9 MR |
2386 | /* If the previous instruction is in a variant frag |
2387 | other than this branch's one, we cannot do the swap. | |
2388 | This does not apply to the mips16, which uses variant | |
2389 | frags for different purposes. */ | |
252b5132 | 2390 | || (! mips_opts.mips16 |
895921c9 | 2391 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2392 | /* If the branch reads the condition codes, we don't |
2393 | even try to swap, because in the sequence | |
2394 | ctc1 $X,$31 | |
2395 | INSN | |
2396 | INSN | |
2397 | bc1t LABEL | |
2398 | we can not swap, and I don't feel like handling that | |
2399 | case. */ | |
2400 | || (! mips_opts.mips16 | |
81912461 ILT |
2401 | && (pinfo & INSN_READ_COND_CODE) |
2402 | && ! cop_interlocks) | |
252b5132 | 2403 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2404 | delay slot, because the target of the branch might |
252b5132 RH |
2405 | interfere with that instruction. */ |
2406 | || (! mips_opts.mips16 | |
252b5132 | 2407 | && (prev_pinfo |
bdaaa2e1 | 2408 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2409 | & (INSN_LOAD_COPROC_DELAY |
2410 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2411 | | INSN_WRITE_COND_CODE)) |
2412 | && ! cop_interlocks) | |
252b5132 | 2413 | || (! (hilo_interlocks |
048cdf86 | 2414 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2415 | && (prev_pinfo |
2416 | & (INSN_READ_LO | |
2417 | | INSN_READ_HI))) | |
2418 | || (! mips_opts.mips16 | |
81912461 ILT |
2419 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2420 | && ! gpr_interlocks) | |
252b5132 | 2421 | || (! mips_opts.mips16 |
bdaaa2e1 | 2422 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2423 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2424 | && ! cop_mem_interlocks) | |
252b5132 RH |
2425 | /* We can not swap with a branch instruction. */ |
2426 | || (prev_pinfo | |
2427 | & (INSN_UNCOND_BRANCH_DELAY | |
2428 | | INSN_COND_BRANCH_DELAY | |
2429 | | INSN_COND_BRANCH_LIKELY)) | |
2430 | /* We do not swap with a trap instruction, since it | |
2431 | complicates trap handlers to have the trap | |
2432 | instruction be in a delay slot. */ | |
2433 | || (prev_pinfo & INSN_TRAP) | |
2434 | /* If the branch reads a register that the previous | |
2435 | instruction sets, we can not swap. */ | |
2436 | || (! mips_opts.mips16 | |
2437 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2438 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2439 | MIPS_GR_REG)) |
2440 | || (! mips_opts.mips16 | |
2441 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2442 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2443 | MIPS_GR_REG)) |
2444 | || (mips_opts.mips16 | |
2445 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2446 | && (insn_uses_reg |
2447 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2448 | MIPS16_REG))) | |
252b5132 | 2449 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2450 | && (insn_uses_reg |
2451 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2452 | MIPS16_REG))) | |
252b5132 | 2453 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2454 | && (insn_uses_reg |
2455 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2456 | MIPS16_REG))) | |
252b5132 RH |
2457 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2458 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2459 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2460 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2461 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2462 | && insn_uses_reg (ip, | |
47e39b9d RS |
2463 | MIPS16OP_EXTRACT_REG32R |
2464 | (history[0].insn_opcode), | |
252b5132 RH |
2465 | MIPS_GR_REG)))) |
2466 | /* If the branch writes a register that the previous | |
2467 | instruction sets, we can not swap (we know that | |
2468 | branches write only to RD or to $31). */ | |
2469 | || (! mips_opts.mips16 | |
2470 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2471 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2472 | && (EXTRACT_OPERAND (RT, history[0]) |
2473 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2474 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2475 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2476 | || (! mips_opts.mips16 |
2477 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2478 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2479 | && (EXTRACT_OPERAND (RD, history[0]) |
2480 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2481 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2482 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2483 | || (mips_opts.mips16 |
2484 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2485 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2486 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2487 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2488 | == RA)))) |
2489 | /* If the branch writes a register that the previous | |
2490 | instruction reads, we can not swap (we know that | |
2491 | branches only write to RD or to $31). */ | |
2492 | || (! mips_opts.mips16 | |
2493 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2494 | && insn_uses_reg (&history[0], |
bf12938e | 2495 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2496 | MIPS_GR_REG)) |
2497 | || (! mips_opts.mips16 | |
2498 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2499 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2500 | || (mips_opts.mips16 |
2501 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2502 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2503 | /* If the previous previous instruction has a load |
2504 | delay, and sets a register that the branch reads, we | |
2505 | can not swap. */ | |
2506 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2507 | /* Itbl support may require additional care here. */ |
47e39b9d | 2508 | && (((history[1].insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
81912461 | 2509 | && ! cop_interlocks) |
47e39b9d | 2510 | || ((history[1].insn_mo->pinfo |
81912461 ILT |
2511 | & INSN_LOAD_MEMORY_DELAY) |
2512 | && ! gpr_interlocks)) | |
bf12938e | 2513 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[1]), |
252b5132 RH |
2514 | MIPS_GR_REG)) |
2515 | /* If one instruction sets a condition code and the | |
2516 | other one uses a condition code, we can not swap. */ | |
2517 | || ((pinfo & INSN_READ_COND_CODE) | |
2518 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2519 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2520 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2521 | /* If the previous instruction uses the PC, we can not | |
2522 | swap. */ | |
2523 | || (mips_opts.mips16 | |
2524 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2525 | /* If the previous instruction had a fixup in mips16 |
2526 | mode, we can not swap. This normally means that the | |
2527 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2528 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2529 | /* If the previous instruction is a sync, sync.l, or |
2530 | sync.p, we can not swap. */ | |
f173e82e | 2531 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2532 | { |
2533 | /* We could do even better for unconditional branches to | |
2534 | portions of this object file; we could pick up the | |
2535 | instruction at the destination, put it in the delay | |
2536 | slot, and bump the destination address. */ | |
2537 | emit_nop (); | |
dd22970f ILT |
2538 | if (mips_relax.sequence) |
2539 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 | 2540 | /* Update the previous insn information. */ |
47e39b9d RS |
2541 | history[1].insn_mo = ip->insn_mo; |
2542 | history[1].use_extend = ip->use_extend; | |
2543 | history[1].extend = ip->extend; | |
2544 | history[1].insn_opcode = ip->insn_opcode; | |
2545 | history[0].insn_mo = &dummy_opcode; | |
252b5132 RH |
2546 | } |
2547 | else | |
2548 | { | |
2549 | /* It looks like we can actually do the swap. */ | |
2550 | if (! mips_opts.mips16) | |
2551 | { | |
2552 | char *prev_f; | |
2553 | char temp[4]; | |
2554 | ||
47e39b9d | 2555 | prev_f = history[0].frag->fr_literal + history[0].where; |
895921c9 MR |
2556 | if (!relaxed_branch) |
2557 | { | |
2558 | /* If this is not a relaxed branch, then just | |
2559 | swap the instructions. */ | |
2560 | memcpy (temp, prev_f, 4); | |
2561 | memcpy (prev_f, f, 4); | |
2562 | memcpy (f, temp, 4); | |
2563 | } | |
2564 | else | |
2565 | { | |
2566 | /* If this is a relaxed branch, then we move the | |
2567 | instruction to be placed in the delay slot to | |
2568 | the current frag, shrinking the fixed part of | |
2569 | the originating frag. If the branch occupies | |
2570 | the tail of the latter, we move it backwards, | |
2571 | into the space freed by the moved instruction. */ | |
2572 | f = frag_more (4); | |
2573 | memcpy (f, prev_f, 4); | |
47e39b9d RS |
2574 | history[0].frag->fr_fix -= 4; |
2575 | if (history[0].frag->fr_type == rs_machine_dependent) | |
2576 | memmove (prev_f, prev_f + 4, history[0].frag->fr_var); | |
895921c9 MR |
2577 | } |
2578 | ||
47e39b9d | 2579 | if (history[0].fixp[0]) |
f6688943 | 2580 | { |
47e39b9d RS |
2581 | history[0].fixp[0]->fx_frag = frag_now; |
2582 | history[0].fixp[0]->fx_where = f - frag_now->fr_literal; | |
f6688943 | 2583 | } |
47e39b9d | 2584 | if (history[0].fixp[1]) |
f6688943 | 2585 | { |
47e39b9d RS |
2586 | history[0].fixp[1]->fx_frag = frag_now; |
2587 | history[0].fixp[1]->fx_where = f - frag_now->fr_literal; | |
f6688943 | 2588 | } |
47e39b9d | 2589 | if (history[0].fixp[2]) |
252b5132 | 2590 | { |
47e39b9d RS |
2591 | history[0].fixp[2]->fx_frag = frag_now; |
2592 | history[0].fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2593 | } |
47e39b9d RS |
2594 | if (history[0].fixp[0] && HAVE_NEWABI |
2595 | && history[0].frag != frag_now | |
2596 | && (history[0].fixp[0]->fx_r_type | |
f5040a92 | 2597 | == BFD_RELOC_MIPS_GOT_DISP |
47e39b9d | 2598 | || (history[0].fixp[0]->fx_r_type |
f5040a92 AO |
2599 | == BFD_RELOC_MIPS_CALL16))) |
2600 | { | |
2601 | /* To avoid confusion in tc_gen_reloc, we must | |
2602 | ensure that this does not become a variant | |
2603 | frag. */ | |
2604 | force_new_frag = TRUE; | |
2605 | } | |
895921c9 MR |
2606 | |
2607 | if (!relaxed_branch) | |
f6688943 | 2608 | { |
895921c9 MR |
2609 | if (fixp[0]) |
2610 | { | |
47e39b9d RS |
2611 | fixp[0]->fx_frag = history[0].frag; |
2612 | fixp[0]->fx_where = history[0].where; | |
895921c9 MR |
2613 | } |
2614 | if (fixp[1]) | |
2615 | { | |
47e39b9d RS |
2616 | fixp[1]->fx_frag = history[0].frag; |
2617 | fixp[1]->fx_where = history[0].where; | |
895921c9 MR |
2618 | } |
2619 | if (fixp[2]) | |
2620 | { | |
47e39b9d RS |
2621 | fixp[2]->fx_frag = history[0].frag; |
2622 | fixp[2]->fx_where = history[0].where; | |
895921c9 | 2623 | } |
f6688943 | 2624 | } |
47e39b9d | 2625 | else if (history[0].frag->fr_type == rs_machine_dependent) |
f6688943 | 2626 | { |
895921c9 MR |
2627 | if (fixp[0]) |
2628 | fixp[0]->fx_where -= 4; | |
2629 | if (fixp[1]) | |
2630 | fixp[1]->fx_where -= 4; | |
2631 | if (fixp[2]) | |
2632 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2633 | } |
2634 | } | |
2635 | else | |
2636 | { | |
2637 | char *prev_f; | |
2638 | char temp[2]; | |
2639 | ||
47e39b9d RS |
2640 | assert (history[0].fixp[0] == NULL); |
2641 | assert (history[0].fixp[1] == NULL); | |
2642 | assert (history[0].fixp[2] == NULL); | |
2643 | prev_f = history[0].frag->fr_literal + history[0].where; | |
252b5132 RH |
2644 | memcpy (temp, prev_f, 2); |
2645 | memcpy (prev_f, f, 2); | |
f6688943 | 2646 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2647 | { |
f6688943 | 2648 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2649 | memcpy (f, temp, 2); |
2650 | } | |
2651 | else | |
2652 | { | |
2653 | memcpy (f, f + 2, 2); | |
2654 | memcpy (f + 2, temp, 2); | |
2655 | } | |
f6688943 TS |
2656 | if (fixp[0]) |
2657 | { | |
47e39b9d RS |
2658 | fixp[0]->fx_frag = history[0].frag; |
2659 | fixp[0]->fx_where = history[0].where; | |
f6688943 TS |
2660 | } |
2661 | if (fixp[1]) | |
2662 | { | |
47e39b9d RS |
2663 | fixp[1]->fx_frag = history[0].frag; |
2664 | fixp[1]->fx_where = history[0].where; | |
f6688943 TS |
2665 | } |
2666 | if (fixp[2]) | |
252b5132 | 2667 | { |
47e39b9d RS |
2668 | fixp[2]->fx_frag = history[0].frag; |
2669 | fixp[2]->fx_where = history[0].where; | |
252b5132 RH |
2670 | } |
2671 | } | |
2672 | ||
47e39b9d | 2673 | /* Update the previous insn information; leave history[0] |
252b5132 | 2674 | unchanged. */ |
47e39b9d RS |
2675 | history[1].insn_mo = ip->insn_mo; |
2676 | history[1].use_extend = ip->use_extend; | |
2677 | history[1].extend = ip->extend; | |
2678 | history[1].insn_opcode = ip->insn_opcode; | |
252b5132 | 2679 | } |
a38419a5 | 2680 | history[0].fixed_p = 1; |
252b5132 RH |
2681 | |
2682 | /* If that was an unconditional branch, forget the previous | |
2683 | insn information. */ | |
2684 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2685 | { | |
47e39b9d RS |
2686 | history[1].insn_mo = &dummy_opcode; |
2687 | history[0].insn_mo = &dummy_opcode; | |
252b5132 RH |
2688 | } |
2689 | ||
47e39b9d RS |
2690 | history[0].fixp[0] = NULL; |
2691 | history[0].fixp[1] = NULL; | |
2692 | history[0].fixp[2] = NULL; | |
2fa15973 | 2693 | history[0].mips16_absolute_jump_p = 0; |
252b5132 RH |
2694 | } |
2695 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2696 | { | |
2697 | /* We don't yet optimize a branch likely. What we should do | |
2698 | is look at the target, copy the instruction found there | |
2699 | into the delay slot, and increment the branch to jump to | |
2700 | the next instruction. */ | |
2701 | emit_nop (); | |
2702 | /* Update the previous insn information. */ | |
47e39b9d RS |
2703 | history[1].insn_mo = ip->insn_mo; |
2704 | history[1].use_extend = ip->use_extend; | |
2705 | history[1].extend = ip->extend; | |
2706 | history[1].insn_opcode = ip->insn_opcode; | |
2707 | history[0].insn_mo = &dummy_opcode; | |
2708 | history[0].fixp[0] = NULL; | |
2709 | history[0].fixp[1] = NULL; | |
2710 | history[0].fixp[2] = NULL; | |
2fa15973 | 2711 | history[0].mips16_absolute_jump_p = 0; |
a38419a5 | 2712 | history[0].fixed_p = 1; |
252b5132 RH |
2713 | } |
2714 | else | |
2715 | { | |
2716 | /* Update the previous insn information. */ | |
2717 | if (nops > 0) | |
47e39b9d | 2718 | history[1].insn_mo = &dummy_opcode; |
252b5132 | 2719 | else |
47e39b9d RS |
2720 | { |
2721 | history[1].insn_mo = history[0].insn_mo; | |
2722 | history[1].use_extend = history[0].use_extend; | |
2723 | history[1].extend = history[0].extend; | |
2724 | history[1].insn_opcode = history[0].insn_opcode; | |
2725 | } | |
2726 | history[0].insn_mo = ip->insn_mo; | |
2727 | history[0].use_extend = ip->use_extend; | |
2728 | history[0].extend = ip->extend; | |
2729 | history[0].insn_opcode = ip->insn_opcode; | |
a38419a5 RS |
2730 | history[0].fixed_p = (mips_opts.mips16 |
2731 | && (ip->use_extend | |
2732 | || *reloc_type > BFD_RELOC_UNUSED)); | |
47e39b9d RS |
2733 | history[0].fixp[0] = fixp[0]; |
2734 | history[0].fixp[1] = fixp[1]; | |
2735 | history[0].fixp[2] = fixp[2]; | |
2fa15973 RS |
2736 | history[0].mips16_absolute_jump_p = (reloc_type[0] |
2737 | == BFD_RELOC_MIPS16_JMP); | |
252b5132 RH |
2738 | } |
2739 | ||
47e39b9d RS |
2740 | history[1].noreorder_p = history[0].noreorder_p; |
2741 | history[0].noreorder_p = 0; | |
2742 | history[0].frag = frag_now; | |
2743 | history[0].where = f - frag_now->fr_literal; | |
252b5132 | 2744 | } |
4d7206a2 | 2745 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2746 | { |
2747 | /* We need to record a bit of information even when we are not | |
2748 | reordering, in order to determine the base address for mips16 | |
2749 | PC relative relocs. */ | |
47e39b9d RS |
2750 | history[1].insn_mo = history[0].insn_mo; |
2751 | history[1].use_extend = history[0].use_extend; | |
2752 | history[1].extend = history[0].extend; | |
2753 | history[1].insn_opcode = history[0].insn_opcode; | |
2754 | history[0].insn_mo = ip->insn_mo; | |
2755 | history[0].use_extend = ip->use_extend; | |
2756 | history[0].extend = ip->extend; | |
2757 | history[0].insn_opcode = ip->insn_opcode; | |
2fa15973 RS |
2758 | history[0].mips16_absolute_jump_p = (reloc_type[0] |
2759 | == BFD_RELOC_MIPS16_JMP); | |
47e39b9d RS |
2760 | history[1].noreorder_p = history[0].noreorder_p; |
2761 | history[0].noreorder_p = 1; | |
a38419a5 | 2762 | history[0].fixed_p = 1; |
252b5132 RH |
2763 | } |
2764 | ||
2765 | /* We just output an insn, so the next one doesn't have a label. */ | |
2766 | mips_clear_insn_labels (); | |
252b5132 RH |
2767 | } |
2768 | ||
2769 | /* This function forgets that there was any previous instruction or | |
2770 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2771 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2772 | |
2773 | static void | |
17a2f251 | 2774 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2775 | { |
2776 | if (! preserve) | |
2777 | { | |
47e39b9d RS |
2778 | history[0].insn_mo = &dummy_opcode; |
2779 | history[1].insn_mo = &dummy_opcode; | |
252b5132 RH |
2780 | prev_nop_frag = NULL; |
2781 | prev_nop_frag_holds = 0; | |
2782 | prev_nop_frag_required = 0; | |
2783 | prev_nop_frag_since = 0; | |
2784 | } | |
a38419a5 | 2785 | history[0].fixed_p = 1; |
47e39b9d | 2786 | history[0].noreorder_p = 0; |
2fa15973 | 2787 | history[0].mips16_absolute_jump_p = 0; |
47e39b9d | 2788 | history[1].noreorder_p = 0; |
252b5132 RH |
2789 | mips_clear_insn_labels (); |
2790 | } | |
2791 | ||
2792 | /* This function must be called whenever we turn on noreorder or emit | |
2793 | something other than instructions. It inserts any NOPS which might | |
2794 | be needed by the previous instruction, and clears the information | |
2795 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2796 | instructions are to follow. */ |
252b5132 RH |
2797 | |
2798 | static void | |
17a2f251 | 2799 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2800 | { |
2801 | if (! mips_opts.noreorder) | |
2802 | { | |
2803 | int nops; | |
2804 | ||
2805 | nops = 0; | |
2806 | if ((! mips_opts.mips16 | |
47e39b9d | 2807 | && ((history[0].insn_mo->pinfo |
81912461 ILT |
2808 | & (INSN_LOAD_COPROC_DELAY |
2809 | | INSN_COPROC_MOVE_DELAY | |
2810 | | INSN_WRITE_COND_CODE)) | |
2811 | && ! cop_interlocks)) | |
252b5132 | 2812 | || (! hilo_interlocks |
47e39b9d | 2813 | && (history[0].insn_mo->pinfo |
252b5132 RH |
2814 | & (INSN_READ_LO |
2815 | | INSN_READ_HI))) | |
2816 | || (! mips_opts.mips16 | |
47e39b9d | 2817 | && (history[0].insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
81912461 | 2818 | && ! gpr_interlocks) |
252b5132 | 2819 | || (! mips_opts.mips16 |
47e39b9d | 2820 | && (history[0].insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
81912461 | 2821 | && ! cop_mem_interlocks)) |
252b5132 | 2822 | { |
beae10d5 | 2823 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2824 | ++nops; |
2825 | if ((! mips_opts.mips16 | |
47e39b9d | 2826 | && ((history[0].insn_mo->pinfo & INSN_WRITE_COND_CODE) |
81912461 | 2827 | && ! cop_interlocks)) |
252b5132 | 2828 | || (! hilo_interlocks |
47e39b9d RS |
2829 | && ((history[0].insn_mo->pinfo & INSN_READ_HI) |
2830 | || (history[0].insn_mo->pinfo & INSN_READ_LO)))) | |
252b5132 RH |
2831 | ++nops; |
2832 | ||
47e39b9d | 2833 | if (history[0].noreorder_p) |
252b5132 RH |
2834 | nops = 0; |
2835 | } | |
2836 | else if ((! mips_opts.mips16 | |
47e39b9d | 2837 | && ((history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE) |
81912461 | 2838 | && ! cop_interlocks)) |
252b5132 | 2839 | || (! hilo_interlocks |
47e39b9d RS |
2840 | && ((history[1].insn_mo->pinfo & INSN_READ_HI) |
2841 | || (history[1].insn_mo->pinfo & INSN_READ_LO)))) | |
252b5132 | 2842 | { |
beae10d5 | 2843 | /* Itbl support may require additional care here. */ |
47e39b9d | 2844 | if (! history[1].noreorder_p) |
252b5132 RH |
2845 | ++nops; |
2846 | } | |
2847 | ||
47e39b9d | 2848 | if (mips_fix_vr4120 && history[0].insn_mo->name) |
60b63b72 RS |
2849 | { |
2850 | int min_nops = 0; | |
47e39b9d | 2851 | const char *pn = history[0].insn_mo->name; |
532c738a RS |
2852 | if (strncmp (pn, "macc", 4) == 0 |
2853 | || strncmp (pn, "dmacc", 5) == 0 | |
2854 | || strncmp (pn, "dmult", 5) == 0 | |
2855 | || strstr (pn, "div")) | |
2856 | min_nops = 1; | |
60b63b72 RS |
2857 | if (nops < min_nops) |
2858 | nops = min_nops; | |
2859 | } | |
2860 | ||
252b5132 RH |
2861 | if (nops > 0) |
2862 | { | |
2863 | struct insn_label_list *l; | |
2864 | ||
2865 | if (insns) | |
2866 | { | |
2867 | /* Record the frag which holds the nop instructions, so | |
2868 | that we can remove them if we don't need them. */ | |
2869 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2870 | prev_nop_frag = frag_now; | |
2871 | prev_nop_frag_holds = nops; | |
2872 | prev_nop_frag_required = 0; | |
2873 | prev_nop_frag_since = 0; | |
2874 | } | |
2875 | ||
2876 | for (; nops > 0; --nops) | |
2877 | emit_nop (); | |
2878 | ||
2879 | if (insns) | |
2880 | { | |
2881 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2882 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2883 | frag_wane (frag_now); |
2884 | frag_new (0); | |
2885 | } | |
2886 | ||
2887 | for (l = insn_labels; l != NULL; l = l->next) | |
2888 | { | |
98aa84af AM |
2889 | valueT val; |
2890 | ||
252b5132 | 2891 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2892 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2893 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2894 | /* mips16 text labels are stored as odd. */ |
2895 | if (mips_opts.mips16) | |
f9419b05 | 2896 | ++val; |
98aa84af | 2897 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2898 | } |
2899 | } | |
2900 | } | |
2901 | ||
2902 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2903 | if (insns) |
252b5132 RH |
2904 | mips16_mark_labels (); |
2905 | ||
2906 | mips_no_prev_insn (insns); | |
2907 | } | |
2908 | ||
584892a6 RS |
2909 | /* Set up global variables for the start of a new macro. */ |
2910 | ||
2911 | static void | |
2912 | macro_start (void) | |
2913 | { | |
2914 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2915 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2916 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2917 | & (INSN_UNCOND_BRANCH_DELAY |
2918 | | INSN_COND_BRANCH_DELAY | |
2919 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2920 | } | |
2921 | ||
2922 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2923 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2924 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2925 | ||
2926 | static const char * | |
2927 | macro_warning (relax_substateT subtype) | |
2928 | { | |
2929 | if (subtype & RELAX_DELAY_SLOT) | |
2930 | return _("Macro instruction expanded into multiple instructions" | |
2931 | " in a branch delay slot"); | |
2932 | else if (subtype & RELAX_NOMACRO) | |
2933 | return _("Macro instruction expanded into multiple instructions"); | |
2934 | else | |
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2939 | ||
2940 | static void | |
2941 | macro_end (void) | |
2942 | { | |
2943 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2944 | { | |
2945 | relax_substateT subtype; | |
2946 | ||
2947 | /* Set up the relaxation warning flags. */ | |
2948 | subtype = 0; | |
2949 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2950 | subtype |= RELAX_SECOND_LONGER; | |
2951 | if (mips_opts.warn_about_macros) | |
2952 | subtype |= RELAX_NOMACRO; | |
2953 | if (mips_macro_warning.delay_slot_p) | |
2954 | subtype |= RELAX_DELAY_SLOT; | |
2955 | ||
2956 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2957 | { | |
2958 | /* Either the macro has a single implementation or both | |
2959 | implementations are longer than 4 bytes. Emit the | |
2960 | warning now. */ | |
2961 | const char *msg = macro_warning (subtype); | |
2962 | if (msg != 0) | |
2963 | as_warn (msg); | |
2964 | } | |
2965 | else | |
2966 | { | |
2967 | /* One implementation might need a warning but the other | |
2968 | definitely doesn't. */ | |
2969 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2970 | } | |
2971 | } | |
2972 | } | |
2973 | ||
6e1304d8 RS |
2974 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2975 | The first argument in *ARGS will be either the code for a single | |
2976 | relocation or -1 followed by the three codes that make up a | |
2977 | composite relocation. */ | |
2978 | ||
2979 | static void | |
2980 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2981 | { | |
2982 | int i, next; | |
2983 | ||
2984 | next = va_arg (*args, int); | |
2985 | if (next >= 0) | |
2986 | r[0] = (bfd_reloc_code_real_type) next; | |
2987 | else | |
2988 | for (i = 0; i < 3; i++) | |
2989 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2990 | } | |
2991 | ||
252b5132 RH |
2992 | /* Build an instruction created by a macro expansion. This is passed |
2993 | a pointer to the count of instructions created so far, an | |
2994 | expression, the name of the instruction to build, an operand format | |
2995 | string, and corresponding arguments. */ | |
2996 | ||
252b5132 | 2997 | static void |
67c0d1eb | 2998 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
2999 | { |
3000 | struct mips_cl_insn insn; | |
f6688943 | 3001 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3002 | va_list args; |
252b5132 | 3003 | |
252b5132 | 3004 | va_start (args, fmt); |
252b5132 | 3005 | |
252b5132 RH |
3006 | if (mips_opts.mips16) |
3007 | { | |
67c0d1eb | 3008 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3009 | va_end (args); |
3010 | return; | |
3011 | } | |
3012 | ||
f6688943 TS |
3013 | r[0] = BFD_RELOC_UNUSED; |
3014 | r[1] = BFD_RELOC_UNUSED; | |
3015 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
3016 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3017 | assert (insn.insn_mo); | |
3018 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3019 | ||
3020 | /* Search until we get a match for NAME. */ | |
3021 | while (1) | |
3022 | { | |
b34976b6 | 3023 | /* It is assumed here that macros will never generate |
deec1734 | 3024 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
3025 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
3026 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3027 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3028 | (mips_opts.isa | |
3396de36 | 3029 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3030 | mips_opts.arch) |
3031 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3032 | break; |
3033 | ||
3034 | ++insn.insn_mo; | |
3035 | assert (insn.insn_mo->name); | |
3036 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3037 | } | |
3038 | ||
3039 | insn.insn_opcode = insn.insn_mo->match; | |
3040 | for (;;) | |
3041 | { | |
3042 | switch (*fmt++) | |
3043 | { | |
3044 | case '\0': | |
3045 | break; | |
3046 | ||
3047 | case ',': | |
3048 | case '(': | |
3049 | case ')': | |
3050 | continue; | |
3051 | ||
5f74bc13 CD |
3052 | case '+': |
3053 | switch (*fmt++) | |
3054 | { | |
3055 | case 'A': | |
3056 | case 'E': | |
bf12938e | 3057 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3058 | continue; |
3059 | ||
3060 | case 'B': | |
3061 | case 'F': | |
3062 | /* Note that in the macro case, these arguments are already | |
3063 | in MSB form. (When handling the instruction in the | |
3064 | non-macro case, these arguments are sizes from which | |
3065 | MSB values must be calculated.) */ | |
bf12938e | 3066 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3067 | continue; |
3068 | ||
3069 | case 'C': | |
3070 | case 'G': | |
3071 | case 'H': | |
3072 | /* Note that in the macro case, these arguments are already | |
3073 | in MSBD form. (When handling the instruction in the | |
3074 | non-macro case, these arguments are sizes from which | |
3075 | MSBD values must be calculated.) */ | |
bf12938e | 3076 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3077 | continue; |
3078 | ||
3079 | default: | |
3080 | internalError (); | |
3081 | } | |
3082 | continue; | |
3083 | ||
252b5132 RH |
3084 | case 't': |
3085 | case 'w': | |
3086 | case 'E': | |
bf12938e | 3087 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3088 | continue; |
3089 | ||
3090 | case 'c': | |
bf12938e | 3091 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3092 | continue; |
3093 | ||
252b5132 RH |
3094 | case 'T': |
3095 | case 'W': | |
bf12938e | 3096 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3097 | continue; |
3098 | ||
3099 | case 'd': | |
3100 | case 'G': | |
af7ee8bf | 3101 | case 'K': |
bf12938e | 3102 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3103 | continue; |
3104 | ||
4372b673 NC |
3105 | case 'U': |
3106 | { | |
3107 | int tmp = va_arg (args, int); | |
3108 | ||
bf12938e RS |
3109 | INSERT_OPERAND (RT, insn, tmp); |
3110 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3111 | continue; |
4372b673 NC |
3112 | } |
3113 | ||
252b5132 RH |
3114 | case 'V': |
3115 | case 'S': | |
bf12938e | 3116 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3117 | continue; |
3118 | ||
3119 | case 'z': | |
3120 | continue; | |
3121 | ||
3122 | case '<': | |
bf12938e | 3123 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3124 | continue; |
3125 | ||
3126 | case 'D': | |
bf12938e | 3127 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3128 | continue; |
3129 | ||
3130 | case 'B': | |
bf12938e | 3131 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3132 | continue; |
3133 | ||
4372b673 | 3134 | case 'J': |
bf12938e | 3135 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3136 | continue; |
3137 | ||
252b5132 | 3138 | case 'q': |
bf12938e | 3139 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3140 | continue; |
3141 | ||
3142 | case 'b': | |
3143 | case 's': | |
3144 | case 'r': | |
3145 | case 'v': | |
bf12938e | 3146 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3147 | continue; |
3148 | ||
3149 | case 'i': | |
3150 | case 'j': | |
3151 | case 'o': | |
6e1304d8 | 3152 | macro_read_relocs (&args, r); |
cdf6fd85 | 3153 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3154 | || *r == BFD_RELOC_MIPS_LITERAL |
3155 | || *r == BFD_RELOC_MIPS_HIGHER | |
3156 | || *r == BFD_RELOC_HI16_S | |
3157 | || *r == BFD_RELOC_LO16 | |
3158 | || *r == BFD_RELOC_MIPS_GOT16 | |
3159 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3160 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3161 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3162 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3163 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3164 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3165 | continue; |
3166 | ||
3167 | case 'u': | |
6e1304d8 | 3168 | macro_read_relocs (&args, r); |
252b5132 RH |
3169 | assert (ep != NULL |
3170 | && (ep->X_op == O_constant | |
3171 | || (ep->X_op == O_symbol | |
f6688943 TS |
3172 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3173 | || *r == BFD_RELOC_HI16_S | |
3174 | || *r == BFD_RELOC_HI16 | |
3175 | || *r == BFD_RELOC_GPREL16 | |
3176 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3177 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3178 | continue; |
3179 | ||
3180 | case 'p': | |
3181 | assert (ep != NULL); | |
3182 | /* | |
3183 | * This allows macro() to pass an immediate expression for | |
3184 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3185 | * Note that the expression still might come from the assembly |
3186 | * input, in which case the value is not checked for range nor | |
3187 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3188 | */ |
3189 | if (ep->X_op == O_constant) | |
3190 | { | |
3191 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3192 | ep = NULL; | |
3193 | } | |
3194 | else | |
0b25d3e6 | 3195 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3196 | continue; |
3197 | ||
3198 | case 'a': | |
3199 | assert (ep != NULL); | |
f6688943 | 3200 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3201 | continue; |
3202 | ||
3203 | case 'C': | |
3204 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3205 | continue; | |
3206 | ||
3207 | default: | |
3208 | internalError (); | |
3209 | } | |
3210 | break; | |
3211 | } | |
3212 | va_end (args); | |
f6688943 | 3213 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3214 | |
4d7206a2 | 3215 | append_insn (&insn, ep, r); |
252b5132 RH |
3216 | } |
3217 | ||
3218 | static void | |
67c0d1eb | 3219 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3220 | va_list args) |
252b5132 RH |
3221 | { |
3222 | struct mips_cl_insn insn; | |
f6688943 TS |
3223 | bfd_reloc_code_real_type r[3] |
3224 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3225 | |
252b5132 RH |
3226 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3227 | assert (insn.insn_mo); | |
3228 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3229 | ||
3230 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3231 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3232 | { | |
3233 | ++insn.insn_mo; | |
3234 | assert (insn.insn_mo->name); | |
3235 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3236 | } | |
3237 | ||
3238 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3239 | insn.use_extend = FALSE; |
252b5132 RH |
3240 | |
3241 | for (;;) | |
3242 | { | |
3243 | int c; | |
3244 | ||
3245 | c = *fmt++; | |
3246 | switch (c) | |
3247 | { | |
3248 | case '\0': | |
3249 | break; | |
3250 | ||
3251 | case ',': | |
3252 | case '(': | |
3253 | case ')': | |
3254 | continue; | |
3255 | ||
3256 | case 'y': | |
3257 | case 'w': | |
bf12938e | 3258 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3259 | continue; |
3260 | ||
3261 | case 'x': | |
3262 | case 'v': | |
bf12938e | 3263 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3264 | continue; |
3265 | ||
3266 | case 'z': | |
bf12938e | 3267 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3268 | continue; |
3269 | ||
3270 | case 'Z': | |
bf12938e | 3271 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3272 | continue; |
3273 | ||
3274 | case '0': | |
3275 | case 'S': | |
3276 | case 'P': | |
3277 | case 'R': | |
3278 | continue; | |
3279 | ||
3280 | case 'X': | |
bf12938e | 3281 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3282 | continue; |
3283 | ||
3284 | case 'Y': | |
3285 | { | |
3286 | int regno; | |
3287 | ||
3288 | regno = va_arg (args, int); | |
3289 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3290 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3291 | } | |
3292 | continue; | |
3293 | ||
3294 | case '<': | |
3295 | case '>': | |
3296 | case '4': | |
3297 | case '5': | |
3298 | case 'H': | |
3299 | case 'W': | |
3300 | case 'D': | |
3301 | case 'j': | |
3302 | case '8': | |
3303 | case 'V': | |
3304 | case 'C': | |
3305 | case 'U': | |
3306 | case 'k': | |
3307 | case 'K': | |
3308 | case 'p': | |
3309 | case 'q': | |
3310 | { | |
3311 | assert (ep != NULL); | |
3312 | ||
3313 | if (ep->X_op != O_constant) | |
874e8986 | 3314 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3315 | else |
3316 | { | |
b34976b6 AM |
3317 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3318 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3319 | &insn.extend); |
252b5132 | 3320 | ep = NULL; |
f6688943 | 3321 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3322 | } |
3323 | } | |
3324 | continue; | |
3325 | ||
3326 | case '6': | |
bf12938e | 3327 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3328 | continue; |
3329 | } | |
3330 | ||
3331 | break; | |
3332 | } | |
3333 | ||
f6688943 | 3334 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3335 | |
4d7206a2 | 3336 | append_insn (&insn, ep, r); |
252b5132 RH |
3337 | } |
3338 | ||
438c16b8 TS |
3339 | /* |
3340 | * Generate a "jalr" instruction with a relocation hint to the called | |
3341 | * function. This occurs in NewABI PIC code. | |
3342 | */ | |
3343 | static void | |
67c0d1eb | 3344 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3345 | { |
685736be | 3346 | char *f = NULL; |
b34976b6 | 3347 | |
438c16b8 | 3348 | if (HAVE_NEWABI) |
f21f8242 | 3349 | { |
cc3d92a5 | 3350 | frag_grow (8); |
f21f8242 AO |
3351 | f = frag_more (0); |
3352 | } | |
67c0d1eb | 3353 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3354 | if (HAVE_NEWABI) |
f21f8242 | 3355 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3356 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3357 | } |
3358 | ||
252b5132 RH |
3359 | /* |
3360 | * Generate a "lui" instruction. | |
3361 | */ | |
3362 | static void | |
67c0d1eb | 3363 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3364 | { |
3365 | expressionS high_expr; | |
3366 | struct mips_cl_insn insn; | |
f6688943 TS |
3367 | bfd_reloc_code_real_type r[3] |
3368 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3369 | const char *name = "lui"; |
3370 | const char *fmt = "t,u"; | |
252b5132 RH |
3371 | |
3372 | assert (! mips_opts.mips16); | |
3373 | ||
4d7206a2 | 3374 | high_expr = *ep; |
252b5132 RH |
3375 | |
3376 | if (high_expr.X_op == O_constant) | |
3377 | { | |
3378 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3379 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3380 | >> 16) & 0xffff; | |
f6688943 | 3381 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3382 | } |
78e1bb40 | 3383 | else |
252b5132 RH |
3384 | { |
3385 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3386 | /* _gp_disp is a special case, used from s_cpload. |
3387 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3388 | assert (mips_pic == NO_PIC |
78e1bb40 | 3389 | || (! HAVE_NEWABI |
aa6975fb ILT |
3390 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3391 | || (! mips_in_shared | |
bbe506e8 TS |
3392 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3393 | "__gnu_local_gp") == 0)); | |
f6688943 | 3394 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3395 | } |
3396 | ||
252b5132 RH |
3397 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3398 | assert (insn.insn_mo); | |
3399 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3400 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3401 | ||
bf12938e RS |
3402 | insn.insn_opcode = insn.insn_mo->match; |
3403 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3404 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3405 | { |
3406 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3407 | append_insn (&insn, NULL, r); |
252b5132 RH |
3408 | } |
3409 | else | |
4d7206a2 | 3410 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3411 | } |
3412 | ||
885add95 CD |
3413 | /* Generate a sequence of instructions to do a load or store from a constant |
3414 | offset off of a base register (breg) into/from a target register (treg), | |
3415 | using AT if necessary. */ | |
3416 | static void | |
67c0d1eb RS |
3417 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3418 | int treg, int breg, int dbl) | |
885add95 CD |
3419 | { |
3420 | assert (ep->X_op == O_constant); | |
3421 | ||
256ab948 | 3422 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3423 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3424 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3425 | { |
d17e7bce | 3426 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3427 | as_bad (_("constant too large")); |
ae826530 | 3428 | |
1b8e29e5 TS |
3429 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3430 | - 0x80000000); | |
ae826530 | 3431 | } |
256ab948 | 3432 | |
67c1ffbe | 3433 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3434 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3435 | as_warn (_("operand overflow")); |
3436 | ||
3437 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3438 | { | |
3439 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3440 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3441 | } |
3442 | else | |
3443 | { | |
3444 | /* 32-bit offset, need multiple instructions and AT, like: | |
3445 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3446 | addu $tempreg,$tempreg,$breg | |
3447 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3448 | to handle the complete offset. */ | |
67c0d1eb RS |
3449 | macro_build_lui (ep, AT); |
3450 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3451 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3452 | |
3453 | if (mips_opts.noat) | |
8fc2e39e | 3454 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3455 | } |
3456 | } | |
3457 | ||
252b5132 RH |
3458 | /* set_at() |
3459 | * Generates code to set the $at register to true (one) | |
3460 | * if reg is less than the immediate expression. | |
3461 | */ | |
3462 | static void | |
67c0d1eb | 3463 | set_at (int reg, int unsignedp) |
252b5132 RH |
3464 | { |
3465 | if (imm_expr.X_op == O_constant | |
3466 | && imm_expr.X_add_number >= -0x8000 | |
3467 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3468 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3469 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3470 | else |
3471 | { | |
67c0d1eb RS |
3472 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3473 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3474 | } |
3475 | } | |
3476 | ||
13757d0c TS |
3477 | static void |
3478 | normalize_constant_expr (expressionS *ex) | |
3479 | { | |
3480 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3481 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3482 | - 0x80000000); | |
3483 | } | |
3484 | ||
252b5132 RH |
3485 | /* Warn if an expression is not a constant. */ |
3486 | ||
3487 | static void | |
17a2f251 | 3488 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3489 | { |
3490 | if (ex->X_op == O_big) | |
3491 | as_bad (_("unsupported large constant")); | |
3492 | else if (ex->X_op != O_constant) | |
3493 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3494 | |
3495 | normalize_constant_expr (ex); | |
252b5132 RH |
3496 | } |
3497 | ||
3498 | /* Count the leading zeroes by performing a binary chop. This is a | |
3499 | bulky bit of source, but performance is a LOT better for the | |
3500 | majority of values than a simple loop to count the bits: | |
3501 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3502 | if ((v) & (1 << (31 - lcnt))) | |
3503 | break; | |
3504 | However it is not code size friendly, and the gain will drop a bit | |
3505 | on certain cached systems. | |
3506 | */ | |
3507 | #define COUNT_TOP_ZEROES(v) \ | |
3508 | (((v) & ~0xffff) == 0 \ | |
3509 | ? ((v) & ~0xff) == 0 \ | |
3510 | ? ((v) & ~0xf) == 0 \ | |
3511 | ? ((v) & ~0x3) == 0 \ | |
3512 | ? ((v) & ~0x1) == 0 \ | |
3513 | ? !(v) \ | |
3514 | ? 32 \ | |
3515 | : 31 \ | |
3516 | : 30 \ | |
3517 | : ((v) & ~0x7) == 0 \ | |
3518 | ? 29 \ | |
3519 | : 28 \ | |
3520 | : ((v) & ~0x3f) == 0 \ | |
3521 | ? ((v) & ~0x1f) == 0 \ | |
3522 | ? 27 \ | |
3523 | : 26 \ | |
3524 | : ((v) & ~0x7f) == 0 \ | |
3525 | ? 25 \ | |
3526 | : 24 \ | |
3527 | : ((v) & ~0xfff) == 0 \ | |
3528 | ? ((v) & ~0x3ff) == 0 \ | |
3529 | ? ((v) & ~0x1ff) == 0 \ | |
3530 | ? 23 \ | |
3531 | : 22 \ | |
3532 | : ((v) & ~0x7ff) == 0 \ | |
3533 | ? 21 \ | |
3534 | : 20 \ | |
3535 | : ((v) & ~0x3fff) == 0 \ | |
3536 | ? ((v) & ~0x1fff) == 0 \ | |
3537 | ? 19 \ | |
3538 | : 18 \ | |
3539 | : ((v) & ~0x7fff) == 0 \ | |
3540 | ? 17 \ | |
3541 | : 16 \ | |
3542 | : ((v) & ~0xffffff) == 0 \ | |
3543 | ? ((v) & ~0xfffff) == 0 \ | |
3544 | ? ((v) & ~0x3ffff) == 0 \ | |
3545 | ? ((v) & ~0x1ffff) == 0 \ | |
3546 | ? 15 \ | |
3547 | : 14 \ | |
3548 | : ((v) & ~0x7ffff) == 0 \ | |
3549 | ? 13 \ | |
3550 | : 12 \ | |
3551 | : ((v) & ~0x3fffff) == 0 \ | |
3552 | ? ((v) & ~0x1fffff) == 0 \ | |
3553 | ? 11 \ | |
3554 | : 10 \ | |
3555 | : ((v) & ~0x7fffff) == 0 \ | |
3556 | ? 9 \ | |
3557 | : 8 \ | |
3558 | : ((v) & ~0xfffffff) == 0 \ | |
3559 | ? ((v) & ~0x3ffffff) == 0 \ | |
3560 | ? ((v) & ~0x1ffffff) == 0 \ | |
3561 | ? 7 \ | |
3562 | : 6 \ | |
3563 | : ((v) & ~0x7ffffff) == 0 \ | |
3564 | ? 5 \ | |
3565 | : 4 \ | |
3566 | : ((v) & ~0x3fffffff) == 0 \ | |
3567 | ? ((v) & ~0x1fffffff) == 0 \ | |
3568 | ? 3 \ | |
3569 | : 2 \ | |
3570 | : ((v) & ~0x7fffffff) == 0 \ | |
3571 | ? 1 \ | |
3572 | : 0) | |
3573 | ||
3574 | /* load_register() | |
67c1ffbe | 3575 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3576 | * an absolute expression value into a register. |
3577 | */ | |
3578 | static void | |
67c0d1eb | 3579 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3580 | { |
3581 | int freg; | |
3582 | expressionS hi32, lo32; | |
3583 | ||
3584 | if (ep->X_op != O_big) | |
3585 | { | |
3586 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3587 | |
3588 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3589 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3590 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3591 | { |
d17e7bce | 3592 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3593 | as_bad (_("constant too large")); |
ae826530 | 3594 | |
1b8e29e5 TS |
3595 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3596 | - 0x80000000); | |
ae826530 | 3597 | } |
256ab948 TS |
3598 | |
3599 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3600 | { |
3601 | /* We can handle 16 bit signed values with an addiu to | |
3602 | $zero. No need to ever use daddiu here, since $zero and | |
3603 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3604 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3605 | return; |
3606 | } | |
3607 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3608 | { | |
3609 | /* We can handle 16 bit unsigned values with an ori to | |
3610 | $zero. */ | |
67c0d1eb | 3611 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3612 | return; |
3613 | } | |
256ab948 | 3614 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3615 | { |
3616 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3617 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3618 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3619 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3620 | return; |
3621 | } | |
3622 | } | |
3623 | ||
3624 | /* The value is larger than 32 bits. */ | |
3625 | ||
ca4e0257 | 3626 | if (HAVE_32BIT_GPRS) |
252b5132 | 3627 | { |
956cd1d6 TS |
3628 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3629 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3630 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3631 | return; |
3632 | } | |
3633 | ||
3634 | if (ep->X_op != O_big) | |
3635 | { | |
3636 | hi32 = *ep; | |
3637 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3638 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3639 | hi32.X_add_number &= 0xffffffff; | |
3640 | lo32 = *ep; | |
3641 | lo32.X_add_number &= 0xffffffff; | |
3642 | } | |
3643 | else | |
3644 | { | |
3645 | assert (ep->X_add_number > 2); | |
3646 | if (ep->X_add_number == 3) | |
3647 | generic_bignum[3] = 0; | |
3648 | else if (ep->X_add_number > 4) | |
3649 | as_bad (_("Number larger than 64 bits")); | |
3650 | lo32.X_op = O_constant; | |
3651 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3652 | hi32.X_op = O_constant; | |
3653 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3654 | } | |
3655 | ||
3656 | if (hi32.X_add_number == 0) | |
3657 | freg = 0; | |
3658 | else | |
3659 | { | |
3660 | int shift, bit; | |
3661 | unsigned long hi, lo; | |
3662 | ||
956cd1d6 | 3663 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3664 | { |
3665 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3666 | { | |
67c0d1eb | 3667 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3668 | return; |
3669 | } | |
3670 | if (lo32.X_add_number & 0x80000000) | |
3671 | { | |
67c0d1eb | 3672 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3673 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3674 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3675 | return; |
3676 | } | |
3677 | } | |
252b5132 RH |
3678 | |
3679 | /* Check for 16bit shifted constant. We know that hi32 is | |
3680 | non-zero, so start the mask on the first bit of the hi32 | |
3681 | value. */ | |
3682 | shift = 17; | |
3683 | do | |
beae10d5 KH |
3684 | { |
3685 | unsigned long himask, lomask; | |
3686 | ||
3687 | if (shift < 32) | |
3688 | { | |
3689 | himask = 0xffff >> (32 - shift); | |
3690 | lomask = (0xffff << shift) & 0xffffffff; | |
3691 | } | |
3692 | else | |
3693 | { | |
3694 | himask = 0xffff << (shift - 32); | |
3695 | lomask = 0; | |
3696 | } | |
3697 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3698 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3699 | { | |
3700 | expressionS tmp; | |
3701 | ||
3702 | tmp.X_op = O_constant; | |
3703 | if (shift < 32) | |
3704 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3705 | | (lo32.X_add_number >> shift)); | |
3706 | else | |
3707 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3708 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3709 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3710 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3711 | return; |
3712 | } | |
f9419b05 | 3713 | ++shift; |
beae10d5 KH |
3714 | } |
3715 | while (shift <= (64 - 16)); | |
252b5132 RH |
3716 | |
3717 | /* Find the bit number of the lowest one bit, and store the | |
3718 | shifted value in hi/lo. */ | |
3719 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3720 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3721 | if (lo != 0) | |
3722 | { | |
3723 | bit = 0; | |
3724 | while ((lo & 1) == 0) | |
3725 | { | |
3726 | lo >>= 1; | |
3727 | ++bit; | |
3728 | } | |
3729 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3730 | hi >>= bit; | |
3731 | } | |
3732 | else | |
3733 | { | |
3734 | bit = 32; | |
3735 | while ((hi & 1) == 0) | |
3736 | { | |
3737 | hi >>= 1; | |
3738 | ++bit; | |
3739 | } | |
3740 | lo = hi; | |
3741 | hi = 0; | |
3742 | } | |
3743 | ||
3744 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3745 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3746 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3747 | { |
3748 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3749 | if (shift != 0) |
beae10d5 | 3750 | { |
252b5132 RH |
3751 | expressionS tmp; |
3752 | ||
3753 | /* This instruction will set the register to be all | |
3754 | ones. */ | |
beae10d5 KH |
3755 | tmp.X_op = O_constant; |
3756 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3757 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3758 | if (bit != 0) |
3759 | { | |
3760 | bit += shift; | |
67c0d1eb RS |
3761 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3762 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3763 | } |
67c0d1eb RS |
3764 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3765 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3766 | return; |
3767 | } | |
3768 | } | |
252b5132 RH |
3769 | |
3770 | /* Sign extend hi32 before calling load_register, because we can | |
3771 | generally get better code when we load a sign extended value. */ | |
3772 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3773 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3774 | load_register (reg, &hi32, 0); |
252b5132 RH |
3775 | freg = reg; |
3776 | } | |
3777 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3778 | { | |
3779 | if (freg != 0) | |
3780 | { | |
67c0d1eb | 3781 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3782 | freg = reg; |
3783 | } | |
3784 | } | |
3785 | else | |
3786 | { | |
3787 | expressionS mid16; | |
3788 | ||
956cd1d6 | 3789 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3790 | { |
67c0d1eb RS |
3791 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3792 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3793 | return; |
3794 | } | |
252b5132 RH |
3795 | |
3796 | if (freg != 0) | |
3797 | { | |
67c0d1eb | 3798 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3799 | freg = reg; |
3800 | } | |
3801 | mid16 = lo32; | |
3802 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3803 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3804 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3805 | freg = reg; |
3806 | } | |
3807 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3808 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3809 | } |
3810 | ||
269137b2 TS |
3811 | static inline void |
3812 | load_delay_nop (void) | |
3813 | { | |
3814 | if (!gpr_interlocks) | |
3815 | macro_build (NULL, "nop", ""); | |
3816 | } | |
3817 | ||
252b5132 RH |
3818 | /* Load an address into a register. */ |
3819 | ||
3820 | static void | |
67c0d1eb | 3821 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3822 | { |
252b5132 RH |
3823 | if (ep->X_op != O_constant |
3824 | && ep->X_op != O_symbol) | |
3825 | { | |
3826 | as_bad (_("expression too complex")); | |
3827 | ep->X_op = O_constant; | |
3828 | } | |
3829 | ||
3830 | if (ep->X_op == O_constant) | |
3831 | { | |
67c0d1eb | 3832 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3833 | return; |
3834 | } | |
3835 | ||
3836 | if (mips_pic == NO_PIC) | |
3837 | { | |
3838 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3839 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3840 | Otherwise we want |
3841 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3842 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3843 | If we have an addend, we always use the latter form. |
76b3015f | 3844 | |
d6bc6245 TS |
3845 | With 64bit address space and a usable $at we want |
3846 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3847 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3848 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3849 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3850 | dsll32 $reg,0 | |
3a482fd5 | 3851 | daddu $reg,$reg,$at |
76b3015f | 3852 | |
c03099e6 | 3853 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3854 | on superscalar processors. |
3855 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3856 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3857 | dsll $reg,16 | |
3858 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3859 | dsll $reg,16 | |
3860 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3861 | |
3862 | For GP relative symbols in 64bit address space we can use | |
3863 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3864 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3865 | { |
6caf9ef4 TS |
3866 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3867 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3868 | { | |
3869 | relax_start (ep->X_add_symbol); | |
3870 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3871 | mips_gp_register, BFD_RELOC_GPREL16); | |
3872 | relax_switch (); | |
3873 | } | |
d6bc6245 | 3874 | |
b8285c27 | 3875 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3876 | { |
67c0d1eb RS |
3877 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3878 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3879 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3880 | BFD_RELOC_MIPS_HIGHER); | |
3881 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3882 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3883 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3884 | *used_at = 1; |
3885 | } | |
3886 | else | |
3887 | { | |
67c0d1eb RS |
3888 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3889 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3890 | BFD_RELOC_MIPS_HIGHER); | |
3891 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3892 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3893 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3894 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3895 | } |
6caf9ef4 TS |
3896 | |
3897 | if (mips_relax.sequence) | |
3898 | relax_end (); | |
d6bc6245 | 3899 | } |
252b5132 RH |
3900 | else |
3901 | { | |
d6bc6245 | 3902 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3903 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3904 | { |
4d7206a2 | 3905 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3906 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3907 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3908 | relax_switch (); |
d6bc6245 | 3909 | } |
67c0d1eb RS |
3910 | macro_build_lui (ep, reg); |
3911 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3912 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3913 | if (mips_relax.sequence) |
3914 | relax_end (); | |
d6bc6245 | 3915 | } |
252b5132 RH |
3916 | } |
3917 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3918 | { | |
3919 | expressionS ex; | |
3920 | ||
3921 | /* If this is a reference to an external symbol, we want | |
3922 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3923 | Otherwise we want | |
3924 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3925 | nop | |
3926 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3927 | If there is a constant, it must be added in after. |
3928 | ||
ed6fb7bd | 3929 | If we have NewABI, we want |
f5040a92 AO |
3930 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3931 | unless we're referencing a global symbol with a non-zero | |
3932 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3933 | if (HAVE_NEWABI) |
3934 | { | |
f5040a92 AO |
3935 | if (ep->X_add_number) |
3936 | { | |
4d7206a2 | 3937 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3938 | ep->X_add_number = 0; |
4d7206a2 | 3939 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3940 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3941 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3942 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3943 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3944 | ex.X_op = O_constant; | |
67c0d1eb | 3945 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3946 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3947 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3948 | relax_switch (); |
f5040a92 | 3949 | } |
67c0d1eb | 3950 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3951 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3952 | if (mips_relax.sequence) |
3953 | relax_end (); | |
ed6fb7bd SC |
3954 | } |
3955 | else | |
3956 | { | |
f5040a92 AO |
3957 | ex.X_add_number = ep->X_add_number; |
3958 | ep->X_add_number = 0; | |
67c0d1eb RS |
3959 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3960 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3961 | load_delay_nop (); |
4d7206a2 RS |
3962 | relax_start (ep->X_add_symbol); |
3963 | relax_switch (); | |
67c0d1eb | 3964 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3965 | BFD_RELOC_LO16); |
4d7206a2 | 3966 | relax_end (); |
ed6fb7bd | 3967 | |
f5040a92 AO |
3968 | if (ex.X_add_number != 0) |
3969 | { | |
3970 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3971 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3972 | ex.X_op = O_constant; | |
67c0d1eb | 3973 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3974 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3975 | } |
252b5132 RH |
3976 | } |
3977 | } | |
3978 | else if (mips_pic == SVR4_PIC) | |
3979 | { | |
3980 | expressionS ex; | |
252b5132 RH |
3981 | |
3982 | /* This is the large GOT case. If this is a reference to an | |
3983 | external symbol, we want | |
3984 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3985 | addu $reg,$reg,$gp | |
3986 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3987 | |
3988 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3989 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3990 | nop | |
3991 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3992 | If there is a constant, it must be added in after. |
f5040a92 AO |
3993 | |
3994 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3995 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3996 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3997 | */ |
438c16b8 TS |
3998 | if (HAVE_NEWABI) |
3999 | { | |
4d7206a2 | 4000 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4001 | ep->X_add_number = 0; |
4d7206a2 | 4002 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4003 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4004 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4005 | reg, reg, mips_gp_register); | |
4006 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4007 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4008 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4009 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4010 | else if (ex.X_add_number) | |
4011 | { | |
4012 | ex.X_op = O_constant; | |
67c0d1eb RS |
4013 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4014 | BFD_RELOC_LO16); | |
f5040a92 AO |
4015 | } |
4016 | ||
4017 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4018 | relax_switch (); |
67c0d1eb | 4019 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4020 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4021 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4022 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4023 | relax_end (); |
438c16b8 | 4024 | } |
252b5132 | 4025 | else |
438c16b8 | 4026 | { |
f5040a92 AO |
4027 | ex.X_add_number = ep->X_add_number; |
4028 | ep->X_add_number = 0; | |
4d7206a2 | 4029 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4030 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4031 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4032 | reg, reg, mips_gp_register); | |
4033 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4034 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4035 | relax_switch (); |
4036 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4037 | { |
4038 | /* We need a nop before loading from $gp. This special | |
4039 | check is required because the lui which starts the main | |
4040 | instruction stream does not refer to $gp, and so will not | |
4041 | insert the nop which may be required. */ | |
67c0d1eb | 4042 | macro_build (NULL, "nop", ""); |
438c16b8 | 4043 | } |
67c0d1eb | 4044 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4045 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4046 | load_delay_nop (); |
67c0d1eb | 4047 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4048 | BFD_RELOC_LO16); |
4d7206a2 | 4049 | relax_end (); |
438c16b8 | 4050 | |
f5040a92 AO |
4051 | if (ex.X_add_number != 0) |
4052 | { | |
4053 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4054 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4055 | ex.X_op = O_constant; | |
67c0d1eb RS |
4056 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4057 | BFD_RELOC_LO16); | |
f5040a92 | 4058 | } |
252b5132 RH |
4059 | } |
4060 | } | |
252b5132 RH |
4061 | else |
4062 | abort (); | |
8fc2e39e TS |
4063 | |
4064 | if (mips_opts.noat && *used_at == 1) | |
4065 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4066 | } |
4067 | ||
ea1fb5dc RS |
4068 | /* Move the contents of register SOURCE into register DEST. */ |
4069 | ||
4070 | static void | |
67c0d1eb | 4071 | move_register (int dest, int source) |
ea1fb5dc | 4072 | { |
67c0d1eb RS |
4073 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4074 | dest, source, 0); | |
ea1fb5dc RS |
4075 | } |
4076 | ||
4d7206a2 | 4077 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4078 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4079 | The two alternatives are: | |
4d7206a2 RS |
4080 | |
4081 | Global symbol Local sybmol | |
4082 | ------------- ------------ | |
4083 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4084 | ... ... | |
4085 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4086 | ||
4087 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4088 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4089 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4090 | |
4091 | static void | |
67c0d1eb | 4092 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4093 | { |
4094 | expressionS global; | |
4095 | ||
4096 | global = *local; | |
4097 | global.X_add_number = 0; | |
4098 | ||
4099 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4100 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4101 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4102 | relax_switch (); |
67c0d1eb RS |
4103 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4104 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4105 | relax_end (); |
4106 | } | |
4107 | ||
4108 | static void | |
67c0d1eb | 4109 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4110 | { |
4111 | expressionS global; | |
4112 | ||
4113 | global.X_op = O_constant; | |
4114 | global.X_op_symbol = NULL; | |
4115 | global.X_add_symbol = NULL; | |
4116 | global.X_add_number = local->X_add_number; | |
4117 | ||
4118 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4119 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4120 | dest, dest, BFD_RELOC_LO16); |
4121 | relax_switch (); | |
67c0d1eb | 4122 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4123 | relax_end (); |
4124 | } | |
4125 | ||
f6a22291 MR |
4126 | static void |
4127 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4128 | { | |
4129 | expressionS global; | |
4130 | int hold_mips_optimize; | |
4131 | ||
4132 | global.X_op = O_constant; | |
4133 | global.X_op_symbol = NULL; | |
4134 | global.X_add_symbol = NULL; | |
4135 | global.X_add_number = local->X_add_number; | |
4136 | ||
4137 | relax_start (local->X_add_symbol); | |
4138 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4139 | relax_switch (); | |
4140 | /* Set mips_optimize around the lui instruction to avoid | |
4141 | inserting an unnecessary nop after the lw. */ | |
4142 | hold_mips_optimize = mips_optimize; | |
4143 | mips_optimize = 2; | |
4144 | macro_build_lui (&global, tmp); | |
4145 | mips_optimize = hold_mips_optimize; | |
4146 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4147 | relax_end (); | |
4148 | ||
4149 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4150 | } | |
4151 | ||
252b5132 RH |
4152 | /* |
4153 | * Build macros | |
4154 | * This routine implements the seemingly endless macro or synthesized | |
4155 | * instructions and addressing modes in the mips assembly language. Many | |
4156 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4157 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4158 | * this verbose method. Others are not simple macros but are more like |
4159 | * optimizing code generation. | |
4160 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4161 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4162 | * The ensuing load upper instructions are ommited. This implies some kind |
4163 | * of global optimization. We currently only optimize within a single macro. | |
4164 | * For many of the load and store macros if the address is specified as a | |
4165 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4166 | * first load register 'at' with zero and use it as the base register. The | |
4167 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4168 | * we're missing. | |
4169 | */ | |
4170 | static void | |
17a2f251 | 4171 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4172 | { |
4173 | register int treg, sreg, dreg, breg; | |
4174 | int tempreg; | |
4175 | int mask; | |
43841e91 | 4176 | int used_at = 0; |
252b5132 RH |
4177 | expressionS expr1; |
4178 | const char *s; | |
4179 | const char *s2; | |
4180 | const char *fmt; | |
4181 | int likely = 0; | |
4182 | int dbl = 0; | |
4183 | int coproc = 0; | |
4184 | int lr = 0; | |
4185 | int imm = 0; | |
1abe91b1 | 4186 | int call = 0; |
252b5132 | 4187 | int off; |
67c0d1eb | 4188 | offsetT maxnum; |
252b5132 | 4189 | bfd_reloc_code_real_type r; |
252b5132 RH |
4190 | int hold_mips_optimize; |
4191 | ||
4192 | assert (! mips_opts.mips16); | |
4193 | ||
4194 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4195 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4196 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4197 | mask = ip->insn_mo->mask; | |
4198 | ||
4199 | expr1.X_op = O_constant; | |
4200 | expr1.X_op_symbol = NULL; | |
4201 | expr1.X_add_symbol = NULL; | |
4202 | expr1.X_add_number = 1; | |
4203 | ||
4204 | switch (mask) | |
4205 | { | |
4206 | case M_DABS: | |
4207 | dbl = 1; | |
4208 | case M_ABS: | |
4209 | /* bgez $a0,.+12 | |
4210 | move v0,$a0 | |
4211 | sub v0,$zero,$a0 | |
4212 | */ | |
4213 | ||
b34976b6 | 4214 | mips_emit_delays (TRUE); |
252b5132 RH |
4215 | ++mips_opts.noreorder; |
4216 | mips_any_noreorder = 1; | |
4217 | ||
4218 | expr1.X_add_number = 8; | |
67c0d1eb | 4219 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4220 | if (dreg == sreg) |
67c0d1eb | 4221 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4222 | else |
67c0d1eb RS |
4223 | move_register (dreg, sreg); |
4224 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4225 | |
4226 | --mips_opts.noreorder; | |
8fc2e39e | 4227 | break; |
252b5132 RH |
4228 | |
4229 | case M_ADD_I: | |
4230 | s = "addi"; | |
4231 | s2 = "add"; | |
4232 | goto do_addi; | |
4233 | case M_ADDU_I: | |
4234 | s = "addiu"; | |
4235 | s2 = "addu"; | |
4236 | goto do_addi; | |
4237 | case M_DADD_I: | |
4238 | dbl = 1; | |
4239 | s = "daddi"; | |
4240 | s2 = "dadd"; | |
4241 | goto do_addi; | |
4242 | case M_DADDU_I: | |
4243 | dbl = 1; | |
4244 | s = "daddiu"; | |
4245 | s2 = "daddu"; | |
4246 | do_addi: | |
4247 | if (imm_expr.X_op == O_constant | |
4248 | && imm_expr.X_add_number >= -0x8000 | |
4249 | && imm_expr.X_add_number < 0x8000) | |
4250 | { | |
67c0d1eb | 4251 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4252 | break; |
252b5132 | 4253 | } |
8fc2e39e | 4254 | used_at = 1; |
67c0d1eb RS |
4255 | load_register (AT, &imm_expr, dbl); |
4256 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4257 | break; |
4258 | ||
4259 | case M_AND_I: | |
4260 | s = "andi"; | |
4261 | s2 = "and"; | |
4262 | goto do_bit; | |
4263 | case M_OR_I: | |
4264 | s = "ori"; | |
4265 | s2 = "or"; | |
4266 | goto do_bit; | |
4267 | case M_NOR_I: | |
4268 | s = ""; | |
4269 | s2 = "nor"; | |
4270 | goto do_bit; | |
4271 | case M_XOR_I: | |
4272 | s = "xori"; | |
4273 | s2 = "xor"; | |
4274 | do_bit: | |
4275 | if (imm_expr.X_op == O_constant | |
4276 | && imm_expr.X_add_number >= 0 | |
4277 | && imm_expr.X_add_number < 0x10000) | |
4278 | { | |
4279 | if (mask != M_NOR_I) | |
67c0d1eb | 4280 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4281 | else |
4282 | { | |
67c0d1eb RS |
4283 | macro_build (&imm_expr, "ori", "t,r,i", |
4284 | treg, sreg, BFD_RELOC_LO16); | |
4285 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4286 | } |
8fc2e39e | 4287 | break; |
252b5132 RH |
4288 | } |
4289 | ||
8fc2e39e | 4290 | used_at = 1; |
67c0d1eb RS |
4291 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4292 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4293 | break; |
4294 | ||
4295 | case M_BEQ_I: | |
4296 | s = "beq"; | |
4297 | goto beq_i; | |
4298 | case M_BEQL_I: | |
4299 | s = "beql"; | |
4300 | likely = 1; | |
4301 | goto beq_i; | |
4302 | case M_BNE_I: | |
4303 | s = "bne"; | |
4304 | goto beq_i; | |
4305 | case M_BNEL_I: | |
4306 | s = "bnel"; | |
4307 | likely = 1; | |
4308 | beq_i: | |
4309 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4310 | { | |
67c0d1eb | 4311 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4312 | break; |
252b5132 | 4313 | } |
8fc2e39e | 4314 | used_at = 1; |
67c0d1eb RS |
4315 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4316 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4317 | break; |
4318 | ||
4319 | case M_BGEL: | |
4320 | likely = 1; | |
4321 | case M_BGE: | |
4322 | if (treg == 0) | |
4323 | { | |
67c0d1eb | 4324 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4325 | break; |
252b5132 RH |
4326 | } |
4327 | if (sreg == 0) | |
4328 | { | |
67c0d1eb | 4329 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4330 | break; |
252b5132 | 4331 | } |
8fc2e39e | 4332 | used_at = 1; |
67c0d1eb RS |
4333 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4334 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4335 | break; |
4336 | ||
4337 | case M_BGTL_I: | |
4338 | likely = 1; | |
4339 | case M_BGT_I: | |
4340 | /* check for > max integer */ | |
4341 | maxnum = 0x7fffffff; | |
ca4e0257 | 4342 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4343 | { |
4344 | maxnum <<= 16; | |
4345 | maxnum |= 0xffff; | |
4346 | maxnum <<= 16; | |
4347 | maxnum |= 0xffff; | |
4348 | } | |
4349 | if (imm_expr.X_op == O_constant | |
4350 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4351 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4352 | { |
4353 | do_false: | |
4354 | /* result is always false */ | |
4355 | if (! likely) | |
67c0d1eb | 4356 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4357 | else |
67c0d1eb | 4358 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4359 | break; |
252b5132 RH |
4360 | } |
4361 | if (imm_expr.X_op != O_constant) | |
4362 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4363 | ++imm_expr.X_add_number; |
252b5132 RH |
4364 | /* FALLTHROUGH */ |
4365 | case M_BGE_I: | |
4366 | case M_BGEL_I: | |
4367 | if (mask == M_BGEL_I) | |
4368 | likely = 1; | |
4369 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4370 | { | |
67c0d1eb | 4371 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4372 | break; |
252b5132 RH |
4373 | } |
4374 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4375 | { | |
67c0d1eb | 4376 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4377 | break; |
252b5132 RH |
4378 | } |
4379 | maxnum = 0x7fffffff; | |
ca4e0257 | 4380 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4381 | { |
4382 | maxnum <<= 16; | |
4383 | maxnum |= 0xffff; | |
4384 | maxnum <<= 16; | |
4385 | maxnum |= 0xffff; | |
4386 | } | |
4387 | maxnum = - maxnum - 1; | |
4388 | if (imm_expr.X_op == O_constant | |
4389 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4390 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4391 | { |
4392 | do_true: | |
4393 | /* result is always true */ | |
4394 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4395 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4396 | break; |
252b5132 | 4397 | } |
8fc2e39e | 4398 | used_at = 1; |
67c0d1eb RS |
4399 | set_at (sreg, 0); |
4400 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4401 | break; |
4402 | ||
4403 | case M_BGEUL: | |
4404 | likely = 1; | |
4405 | case M_BGEU: | |
4406 | if (treg == 0) | |
4407 | goto do_true; | |
4408 | if (sreg == 0) | |
4409 | { | |
67c0d1eb | 4410 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4411 | "s,t,p", 0, treg); |
8fc2e39e | 4412 | break; |
252b5132 | 4413 | } |
8fc2e39e | 4414 | used_at = 1; |
67c0d1eb RS |
4415 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4416 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4417 | break; |
4418 | ||
4419 | case M_BGTUL_I: | |
4420 | likely = 1; | |
4421 | case M_BGTU_I: | |
4422 | if (sreg == 0 | |
ca4e0257 | 4423 | || (HAVE_32BIT_GPRS |
252b5132 | 4424 | && imm_expr.X_op == O_constant |
956cd1d6 | 4425 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4426 | goto do_false; |
4427 | if (imm_expr.X_op != O_constant) | |
4428 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4429 | ++imm_expr.X_add_number; |
252b5132 RH |
4430 | /* FALLTHROUGH */ |
4431 | case M_BGEU_I: | |
4432 | case M_BGEUL_I: | |
4433 | if (mask == M_BGEUL_I) | |
4434 | likely = 1; | |
4435 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4436 | goto do_true; | |
4437 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4438 | { | |
67c0d1eb | 4439 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4440 | "s,t,p", sreg, 0); |
8fc2e39e | 4441 | break; |
252b5132 | 4442 | } |
8fc2e39e | 4443 | used_at = 1; |
67c0d1eb RS |
4444 | set_at (sreg, 1); |
4445 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4446 | break; |
4447 | ||
4448 | case M_BGTL: | |
4449 | likely = 1; | |
4450 | case M_BGT: | |
4451 | if (treg == 0) | |
4452 | { | |
67c0d1eb | 4453 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4454 | break; |
252b5132 RH |
4455 | } |
4456 | if (sreg == 0) | |
4457 | { | |
67c0d1eb | 4458 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4459 | break; |
252b5132 | 4460 | } |
8fc2e39e | 4461 | used_at = 1; |
67c0d1eb RS |
4462 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4463 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4464 | break; |
4465 | ||
4466 | case M_BGTUL: | |
4467 | likely = 1; | |
4468 | case M_BGTU: | |
4469 | if (treg == 0) | |
4470 | { | |
67c0d1eb | 4471 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4472 | "s,t,p", sreg, 0); |
8fc2e39e | 4473 | break; |
252b5132 RH |
4474 | } |
4475 | if (sreg == 0) | |
4476 | goto do_false; | |
8fc2e39e | 4477 | used_at = 1; |
67c0d1eb RS |
4478 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4479 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4480 | break; |
4481 | ||
4482 | case M_BLEL: | |
4483 | likely = 1; | |
4484 | case M_BLE: | |
4485 | if (treg == 0) | |
4486 | { | |
67c0d1eb | 4487 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4488 | break; |
252b5132 RH |
4489 | } |
4490 | if (sreg == 0) | |
4491 | { | |
67c0d1eb | 4492 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4493 | break; |
252b5132 | 4494 | } |
8fc2e39e | 4495 | used_at = 1; |
67c0d1eb RS |
4496 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4497 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4498 | break; |
4499 | ||
4500 | case M_BLEL_I: | |
4501 | likely = 1; | |
4502 | case M_BLE_I: | |
4503 | maxnum = 0x7fffffff; | |
ca4e0257 | 4504 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4505 | { |
4506 | maxnum <<= 16; | |
4507 | maxnum |= 0xffff; | |
4508 | maxnum <<= 16; | |
4509 | maxnum |= 0xffff; | |
4510 | } | |
4511 | if (imm_expr.X_op == O_constant | |
4512 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4513 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4514 | goto do_true; |
4515 | if (imm_expr.X_op != O_constant) | |
4516 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4517 | ++imm_expr.X_add_number; |
252b5132 RH |
4518 | /* FALLTHROUGH */ |
4519 | case M_BLT_I: | |
4520 | case M_BLTL_I: | |
4521 | if (mask == M_BLTL_I) | |
4522 | likely = 1; | |
4523 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4524 | { | |
67c0d1eb | 4525 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4526 | break; |
252b5132 RH |
4527 | } |
4528 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4529 | { | |
67c0d1eb | 4530 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4531 | break; |
252b5132 | 4532 | } |
8fc2e39e | 4533 | used_at = 1; |
67c0d1eb RS |
4534 | set_at (sreg, 0); |
4535 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4536 | break; |
4537 | ||
4538 | case M_BLEUL: | |
4539 | likely = 1; | |
4540 | case M_BLEU: | |
4541 | if (treg == 0) | |
4542 | { | |
67c0d1eb | 4543 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4544 | "s,t,p", sreg, 0); |
8fc2e39e | 4545 | break; |
252b5132 RH |
4546 | } |
4547 | if (sreg == 0) | |
4548 | goto do_true; | |
8fc2e39e | 4549 | used_at = 1; |
67c0d1eb RS |
4550 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4551 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4552 | break; |
4553 | ||
4554 | case M_BLEUL_I: | |
4555 | likely = 1; | |
4556 | case M_BLEU_I: | |
4557 | if (sreg == 0 | |
ca4e0257 | 4558 | || (HAVE_32BIT_GPRS |
252b5132 | 4559 | && imm_expr.X_op == O_constant |
956cd1d6 | 4560 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4561 | goto do_true; |
4562 | if (imm_expr.X_op != O_constant) | |
4563 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4564 | ++imm_expr.X_add_number; |
252b5132 RH |
4565 | /* FALLTHROUGH */ |
4566 | case M_BLTU_I: | |
4567 | case M_BLTUL_I: | |
4568 | if (mask == M_BLTUL_I) | |
4569 | likely = 1; | |
4570 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4571 | goto do_false; | |
4572 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4573 | { | |
67c0d1eb | 4574 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4575 | "s,t,p", sreg, 0); |
8fc2e39e | 4576 | break; |
252b5132 | 4577 | } |
8fc2e39e | 4578 | used_at = 1; |
67c0d1eb RS |
4579 | set_at (sreg, 1); |
4580 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4581 | break; |
4582 | ||
4583 | case M_BLTL: | |
4584 | likely = 1; | |
4585 | case M_BLT: | |
4586 | if (treg == 0) | |
4587 | { | |
67c0d1eb | 4588 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4589 | break; |
252b5132 RH |
4590 | } |
4591 | if (sreg == 0) | |
4592 | { | |
67c0d1eb | 4593 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4594 | break; |
252b5132 | 4595 | } |
8fc2e39e | 4596 | used_at = 1; |
67c0d1eb RS |
4597 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4598 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4599 | break; |
4600 | ||
4601 | case M_BLTUL: | |
4602 | likely = 1; | |
4603 | case M_BLTU: | |
4604 | if (treg == 0) | |
4605 | goto do_false; | |
4606 | if (sreg == 0) | |
4607 | { | |
67c0d1eb | 4608 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4609 | "s,t,p", 0, treg); |
8fc2e39e | 4610 | break; |
252b5132 | 4611 | } |
8fc2e39e | 4612 | used_at = 1; |
67c0d1eb RS |
4613 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4614 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4615 | break; |
4616 | ||
5f74bc13 CD |
4617 | case M_DEXT: |
4618 | { | |
4619 | unsigned long pos; | |
4620 | unsigned long size; | |
4621 | ||
4622 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4623 | { | |
4624 | as_bad (_("Unsupported large constant")); | |
4625 | pos = size = 1; | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | pos = (unsigned long) imm_expr.X_add_number; | |
4630 | size = (unsigned long) imm2_expr.X_add_number; | |
4631 | } | |
4632 | ||
4633 | if (pos > 63) | |
4634 | { | |
4635 | as_bad (_("Improper position (%lu)"), pos); | |
4636 | pos = 1; | |
4637 | } | |
4638 | if (size == 0 || size > 64 | |
4639 | || (pos + size - 1) > 63) | |
4640 | { | |
4641 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4642 | size, pos); | |
4643 | size = 1; | |
4644 | } | |
4645 | ||
4646 | if (size <= 32 && pos < 32) | |
4647 | { | |
4648 | s = "dext"; | |
4649 | fmt = "t,r,+A,+C"; | |
4650 | } | |
4651 | else if (size <= 32) | |
4652 | { | |
4653 | s = "dextu"; | |
4654 | fmt = "t,r,+E,+H"; | |
4655 | } | |
4656 | else | |
4657 | { | |
4658 | s = "dextm"; | |
4659 | fmt = "t,r,+A,+G"; | |
4660 | } | |
67c0d1eb | 4661 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4662 | } |
8fc2e39e | 4663 | break; |
5f74bc13 CD |
4664 | |
4665 | case M_DINS: | |
4666 | { | |
4667 | unsigned long pos; | |
4668 | unsigned long size; | |
4669 | ||
4670 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4671 | { | |
4672 | as_bad (_("Unsupported large constant")); | |
4673 | pos = size = 1; | |
4674 | } | |
4675 | else | |
4676 | { | |
4677 | pos = (unsigned long) imm_expr.X_add_number; | |
4678 | size = (unsigned long) imm2_expr.X_add_number; | |
4679 | } | |
4680 | ||
4681 | if (pos > 63) | |
4682 | { | |
4683 | as_bad (_("Improper position (%lu)"), pos); | |
4684 | pos = 1; | |
4685 | } | |
4686 | if (size == 0 || size > 64 | |
4687 | || (pos + size - 1) > 63) | |
4688 | { | |
4689 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4690 | size, pos); | |
4691 | size = 1; | |
4692 | } | |
4693 | ||
4694 | if (pos < 32 && (pos + size - 1) < 32) | |
4695 | { | |
4696 | s = "dins"; | |
4697 | fmt = "t,r,+A,+B"; | |
4698 | } | |
4699 | else if (pos >= 32) | |
4700 | { | |
4701 | s = "dinsu"; | |
4702 | fmt = "t,r,+E,+F"; | |
4703 | } | |
4704 | else | |
4705 | { | |
4706 | s = "dinsm"; | |
4707 | fmt = "t,r,+A,+F"; | |
4708 | } | |
67c0d1eb RS |
4709 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4710 | pos + size - 1); | |
5f74bc13 | 4711 | } |
8fc2e39e | 4712 | break; |
5f74bc13 | 4713 | |
252b5132 RH |
4714 | case M_DDIV_3: |
4715 | dbl = 1; | |
4716 | case M_DIV_3: | |
4717 | s = "mflo"; | |
4718 | goto do_div3; | |
4719 | case M_DREM_3: | |
4720 | dbl = 1; | |
4721 | case M_REM_3: | |
4722 | s = "mfhi"; | |
4723 | do_div3: | |
4724 | if (treg == 0) | |
4725 | { | |
4726 | as_warn (_("Divide by zero.")); | |
4727 | if (mips_trap) | |
67c0d1eb | 4728 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4729 | else |
67c0d1eb | 4730 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4731 | break; |
252b5132 RH |
4732 | } |
4733 | ||
b34976b6 | 4734 | mips_emit_delays (TRUE); |
252b5132 RH |
4735 | ++mips_opts.noreorder; |
4736 | mips_any_noreorder = 1; | |
4737 | if (mips_trap) | |
4738 | { | |
67c0d1eb RS |
4739 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4740 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4741 | } |
4742 | else | |
4743 | { | |
4744 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4745 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4746 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4747 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4748 | } |
4749 | expr1.X_add_number = -1; | |
8fc2e39e | 4750 | used_at = 1; |
f6a22291 | 4751 | load_register (AT, &expr1, dbl); |
252b5132 | 4752 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4753 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4754 | if (dbl) |
4755 | { | |
4756 | expr1.X_add_number = 1; | |
f6a22291 | 4757 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4758 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4759 | } |
4760 | else | |
4761 | { | |
4762 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4763 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4764 | } |
4765 | if (mips_trap) | |
4766 | { | |
67c0d1eb | 4767 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4768 | /* We want to close the noreorder block as soon as possible, so |
4769 | that later insns are available for delay slot filling. */ | |
4770 | --mips_opts.noreorder; | |
4771 | } | |
4772 | else | |
4773 | { | |
4774 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4775 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4776 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4777 | |
4778 | /* We want to close the noreorder block as soon as possible, so | |
4779 | that later insns are available for delay slot filling. */ | |
4780 | --mips_opts.noreorder; | |
4781 | ||
67c0d1eb | 4782 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4783 | } |
67c0d1eb | 4784 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4785 | break; |
4786 | ||
4787 | case M_DIV_3I: | |
4788 | s = "div"; | |
4789 | s2 = "mflo"; | |
4790 | goto do_divi; | |
4791 | case M_DIVU_3I: | |
4792 | s = "divu"; | |
4793 | s2 = "mflo"; | |
4794 | goto do_divi; | |
4795 | case M_REM_3I: | |
4796 | s = "div"; | |
4797 | s2 = "mfhi"; | |
4798 | goto do_divi; | |
4799 | case M_REMU_3I: | |
4800 | s = "divu"; | |
4801 | s2 = "mfhi"; | |
4802 | goto do_divi; | |
4803 | case M_DDIV_3I: | |
4804 | dbl = 1; | |
4805 | s = "ddiv"; | |
4806 | s2 = "mflo"; | |
4807 | goto do_divi; | |
4808 | case M_DDIVU_3I: | |
4809 | dbl = 1; | |
4810 | s = "ddivu"; | |
4811 | s2 = "mflo"; | |
4812 | goto do_divi; | |
4813 | case M_DREM_3I: | |
4814 | dbl = 1; | |
4815 | s = "ddiv"; | |
4816 | s2 = "mfhi"; | |
4817 | goto do_divi; | |
4818 | case M_DREMU_3I: | |
4819 | dbl = 1; | |
4820 | s = "ddivu"; | |
4821 | s2 = "mfhi"; | |
4822 | do_divi: | |
4823 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4824 | { | |
4825 | as_warn (_("Divide by zero.")); | |
4826 | if (mips_trap) | |
67c0d1eb | 4827 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4828 | else |
67c0d1eb | 4829 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4830 | break; |
252b5132 RH |
4831 | } |
4832 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4833 | { | |
4834 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4835 | move_register (dreg, sreg); |
252b5132 | 4836 | else |
67c0d1eb | 4837 | move_register (dreg, 0); |
8fc2e39e | 4838 | break; |
252b5132 RH |
4839 | } |
4840 | if (imm_expr.X_op == O_constant | |
4841 | && imm_expr.X_add_number == -1 | |
4842 | && s[strlen (s) - 1] != 'u') | |
4843 | { | |
4844 | if (strcmp (s2, "mflo") == 0) | |
4845 | { | |
67c0d1eb | 4846 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4847 | } |
4848 | else | |
67c0d1eb | 4849 | move_register (dreg, 0); |
8fc2e39e | 4850 | break; |
252b5132 RH |
4851 | } |
4852 | ||
8fc2e39e | 4853 | used_at = 1; |
67c0d1eb RS |
4854 | load_register (AT, &imm_expr, dbl); |
4855 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4856 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4857 | break; |
4858 | ||
4859 | case M_DIVU_3: | |
4860 | s = "divu"; | |
4861 | s2 = "mflo"; | |
4862 | goto do_divu3; | |
4863 | case M_REMU_3: | |
4864 | s = "divu"; | |
4865 | s2 = "mfhi"; | |
4866 | goto do_divu3; | |
4867 | case M_DDIVU_3: | |
4868 | s = "ddivu"; | |
4869 | s2 = "mflo"; | |
4870 | goto do_divu3; | |
4871 | case M_DREMU_3: | |
4872 | s = "ddivu"; | |
4873 | s2 = "mfhi"; | |
4874 | do_divu3: | |
b34976b6 | 4875 | mips_emit_delays (TRUE); |
252b5132 RH |
4876 | ++mips_opts.noreorder; |
4877 | mips_any_noreorder = 1; | |
4878 | if (mips_trap) | |
4879 | { | |
67c0d1eb RS |
4880 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4881 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4882 | /* We want to close the noreorder block as soon as possible, so |
4883 | that later insns are available for delay slot filling. */ | |
4884 | --mips_opts.noreorder; | |
4885 | } | |
4886 | else | |
4887 | { | |
4888 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4889 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4890 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4891 | |
4892 | /* We want to close the noreorder block as soon as possible, so | |
4893 | that later insns are available for delay slot filling. */ | |
4894 | --mips_opts.noreorder; | |
67c0d1eb | 4895 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4896 | } |
67c0d1eb | 4897 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4898 | break; |
252b5132 | 4899 | |
1abe91b1 MR |
4900 | case M_DLCA_AB: |
4901 | dbl = 1; | |
4902 | case M_LCA_AB: | |
4903 | call = 1; | |
4904 | goto do_la; | |
252b5132 RH |
4905 | case M_DLA_AB: |
4906 | dbl = 1; | |
4907 | case M_LA_AB: | |
1abe91b1 | 4908 | do_la: |
252b5132 RH |
4909 | /* Load the address of a symbol into a register. If breg is not |
4910 | zero, we then add a base register to it. */ | |
4911 | ||
3bec30a8 TS |
4912 | if (dbl && HAVE_32BIT_GPRS) |
4913 | as_warn (_("dla used to load 32-bit register")); | |
4914 | ||
c90bbe5b | 4915 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4916 | as_warn (_("la used to load 64-bit address")); |
4917 | ||
0c11417f MR |
4918 | if (offset_expr.X_op == O_constant |
4919 | && offset_expr.X_add_number >= -0x8000 | |
4920 | && offset_expr.X_add_number < 0x8000) | |
4921 | { | |
aed1a261 | 4922 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4923 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4924 | break; |
0c11417f MR |
4925 | } |
4926 | ||
b8285c27 | 4927 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4928 | { |
4929 | tempreg = AT; | |
4930 | used_at = 1; | |
4931 | } | |
4932 | else | |
4933 | { | |
4934 | tempreg = treg; | |
afdbd6d0 CD |
4935 | } |
4936 | ||
252b5132 RH |
4937 | if (offset_expr.X_op != O_symbol |
4938 | && offset_expr.X_op != O_constant) | |
4939 | { | |
4940 | as_bad (_("expression too complex")); | |
4941 | offset_expr.X_op = O_constant; | |
4942 | } | |
4943 | ||
252b5132 | 4944 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4945 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4946 | else if (mips_pic == NO_PIC) |
4947 | { | |
d6bc6245 | 4948 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4949 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4950 | Otherwise we want |
4951 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4952 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4953 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4954 | so we may as well always use the latter form. |
76b3015f | 4955 | |
6caf9ef4 TS |
4956 | With 64bit address space and a usable $at we want |
4957 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4958 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4959 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4960 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4961 | dsll32 $tempreg,0 | |
4962 | daddu $tempreg,$tempreg,$at | |
4963 | ||
4964 | If $at is already in use, we use a path which is suboptimal | |
4965 | on superscalar processors. | |
4966 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4967 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4968 | dsll $tempreg,16 | |
4969 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4970 | dsll $tempreg,16 | |
4971 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4972 | ||
4973 | For GP relative symbols in 64bit address space we can use | |
4974 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4975 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4976 | { |
6caf9ef4 TS |
4977 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4978 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4979 | { | |
4980 | relax_start (offset_expr.X_add_symbol); | |
4981 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4982 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4983 | relax_switch (); | |
4984 | } | |
d6bc6245 | 4985 | |
b8285c27 | 4986 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4987 | { |
67c0d1eb | 4988 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4989 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4990 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4991 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4992 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4993 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4994 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4995 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4996 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4997 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4998 | used_at = 1; |
4999 | } | |
5000 | else | |
5001 | { | |
67c0d1eb | 5002 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5003 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5004 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5005 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5006 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5007 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5008 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5009 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5010 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5011 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5012 | } |
6caf9ef4 TS |
5013 | |
5014 | if (mips_relax.sequence) | |
5015 | relax_end (); | |
98d3f06f KH |
5016 | } |
5017 | else | |
5018 | { | |
5019 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5020 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5021 | { |
4d7206a2 | 5022 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5023 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5024 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5025 | relax_switch (); |
98d3f06f | 5026 | } |
6943caf0 ILT |
5027 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5028 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5029 | macro_build_lui (&offset_expr, tempreg); |
5030 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5031 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5032 | if (mips_relax.sequence) |
5033 | relax_end (); | |
98d3f06f | 5034 | } |
252b5132 | 5035 | } |
f5040a92 | 5036 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5037 | { |
9117d219 NC |
5038 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5039 | ||
252b5132 RH |
5040 | /* If this is a reference to an external symbol, and there |
5041 | is no constant, we want | |
5042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5043 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5044 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5045 | For a local symbol, we want |
5046 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5047 | nop | |
5048 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5049 | ||
5050 | If we have a small constant, and this is a reference to | |
5051 | an external symbol, we want | |
5052 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5053 | nop | |
5054 | addiu $tempreg,$tempreg,<constant> | |
5055 | For a local symbol, we want the same instruction | |
5056 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5057 | addiu instruction. | |
5058 | ||
5059 | If we have a large constant, and this is a reference to | |
5060 | an external symbol, we want | |
5061 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5062 | lui $at,<hiconstant> | |
5063 | addiu $at,$at,<loconstant> | |
5064 | addu $tempreg,$tempreg,$at | |
5065 | For a local symbol, we want the same instruction | |
5066 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5067 | addiu instruction. |
ed6fb7bd SC |
5068 | */ |
5069 | ||
4d7206a2 | 5070 | if (offset_expr.X_add_number == 0) |
252b5132 | 5071 | { |
4d7206a2 RS |
5072 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5073 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5074 | ||
5075 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5076 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5077 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5078 | if (breg != 0) |
252b5132 RH |
5079 | { |
5080 | /* We're going to put in an addu instruction using | |
5081 | tempreg, so we may as well insert the nop right | |
5082 | now. */ | |
269137b2 | 5083 | load_delay_nop (); |
252b5132 | 5084 | } |
4d7206a2 | 5085 | relax_switch (); |
67c0d1eb RS |
5086 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5087 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5088 | load_delay_nop (); |
67c0d1eb RS |
5089 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5090 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5091 | relax_end (); |
252b5132 RH |
5092 | /* FIXME: If breg == 0, and the next instruction uses |
5093 | $tempreg, then if this variant case is used an extra | |
5094 | nop will be generated. */ | |
5095 | } | |
4d7206a2 RS |
5096 | else if (offset_expr.X_add_number >= -0x8000 |
5097 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5098 | { |
67c0d1eb | 5099 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5100 | load_delay_nop (); |
67c0d1eb | 5101 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5102 | } |
5103 | else | |
5104 | { | |
4d7206a2 RS |
5105 | expr1.X_add_number = offset_expr.X_add_number; |
5106 | offset_expr.X_add_number = | |
5107 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5108 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5109 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5110 | /* If we are going to add in a base register, and the |
5111 | target register and the base register are the same, | |
5112 | then we are using AT as a temporary register. Since | |
5113 | we want to load the constant into AT, we add our | |
5114 | current AT (from the global offset table) and the | |
5115 | register into the register now, and pretend we were | |
5116 | not using a base register. */ | |
67c0d1eb | 5117 | if (breg == treg) |
252b5132 | 5118 | { |
269137b2 | 5119 | load_delay_nop (); |
67c0d1eb | 5120 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5121 | treg, AT, breg); |
252b5132 RH |
5122 | breg = 0; |
5123 | tempreg = treg; | |
252b5132 | 5124 | } |
f6a22291 | 5125 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5126 | used_at = 1; |
5127 | } | |
5128 | } | |
f5040a92 AO |
5129 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5130 | { | |
67c0d1eb | 5131 | int add_breg_early = 0; |
f5040a92 AO |
5132 | |
5133 | /* If this is a reference to an external, and there is no | |
5134 | constant, or local symbol (*), with or without a | |
5135 | constant, we want | |
5136 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5137 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5138 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5139 | ||
5140 | If we have a small constant, and this is a reference to | |
5141 | an external symbol, we want | |
5142 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5143 | addiu $tempreg,$tempreg,<constant> | |
5144 | ||
5145 | If we have a large constant, and this is a reference to | |
5146 | an external symbol, we want | |
5147 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5148 | lui $at,<hiconstant> | |
5149 | addiu $at,$at,<loconstant> | |
5150 | addu $tempreg,$tempreg,$at | |
5151 | ||
5152 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5153 | local symbols, even though it introduces an additional | |
5154 | instruction. */ | |
5155 | ||
f5040a92 AO |
5156 | if (offset_expr.X_add_number) |
5157 | { | |
4d7206a2 | 5158 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5159 | offset_expr.X_add_number = 0; |
5160 | ||
4d7206a2 | 5161 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5162 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5163 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5164 | |
5165 | if (expr1.X_add_number >= -0x8000 | |
5166 | && expr1.X_add_number < 0x8000) | |
5167 | { | |
67c0d1eb RS |
5168 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5169 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5170 | } |
ecd13cd3 | 5171 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5172 | { |
5173 | int dreg; | |
5174 | ||
5175 | /* If we are going to add in a base register, and the | |
5176 | target register and the base register are the same, | |
5177 | then we are using AT as a temporary register. Since | |
5178 | we want to load the constant into AT, we add our | |
5179 | current AT (from the global offset table) and the | |
5180 | register into the register now, and pretend we were | |
5181 | not using a base register. */ | |
5182 | if (breg != treg) | |
5183 | dreg = tempreg; | |
5184 | else | |
5185 | { | |
5186 | assert (tempreg == AT); | |
67c0d1eb RS |
5187 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5188 | treg, AT, breg); | |
f5040a92 | 5189 | dreg = treg; |
67c0d1eb | 5190 | add_breg_early = 1; |
f5040a92 AO |
5191 | } |
5192 | ||
f6a22291 | 5193 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5194 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5195 | dreg, dreg, AT); |
f5040a92 | 5196 | |
f5040a92 AO |
5197 | used_at = 1; |
5198 | } | |
5199 | else | |
5200 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5201 | ||
4d7206a2 | 5202 | relax_switch (); |
f5040a92 AO |
5203 | offset_expr.X_add_number = expr1.X_add_number; |
5204 | ||
67c0d1eb RS |
5205 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5206 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5207 | if (add_breg_early) | |
f5040a92 | 5208 | { |
67c0d1eb | 5209 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5210 | treg, tempreg, breg); |
f5040a92 AO |
5211 | breg = 0; |
5212 | tempreg = treg; | |
5213 | } | |
4d7206a2 | 5214 | relax_end (); |
f5040a92 | 5215 | } |
4d7206a2 | 5216 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5217 | { |
4d7206a2 | 5218 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5219 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5220 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5221 | relax_switch (); |
67c0d1eb RS |
5222 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5223 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5224 | relax_end (); |
f5040a92 | 5225 | } |
4d7206a2 | 5226 | else |
f5040a92 | 5227 | { |
67c0d1eb RS |
5228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5229 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5230 | } |
5231 | } | |
5232 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5233 | { |
67c0d1eb | 5234 | int gpdelay; |
9117d219 NC |
5235 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5236 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5237 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5238 | |
5239 | /* This is the large GOT case. If this is a reference to an | |
5240 | external symbol, and there is no constant, we want | |
5241 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5242 | addu $tempreg,$tempreg,$gp | |
5243 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5244 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5245 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5246 | addu $tempreg,$tempreg,$gp | |
5247 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5248 | For a local symbol, we want |
5249 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5250 | nop | |
5251 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5252 | ||
5253 | If we have a small constant, and this is a reference to | |
5254 | an external symbol, we want | |
5255 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5256 | addu $tempreg,$tempreg,$gp | |
5257 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5258 | nop | |
5259 | addiu $tempreg,$tempreg,<constant> | |
5260 | For a local symbol, we want | |
5261 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5262 | nop | |
5263 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5264 | ||
5265 | If we have a large constant, and this is a reference to | |
5266 | an external symbol, we want | |
5267 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5268 | addu $tempreg,$tempreg,$gp | |
5269 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5270 | lui $at,<hiconstant> | |
5271 | addiu $at,$at,<loconstant> | |
5272 | addu $tempreg,$tempreg,$at | |
5273 | For a local symbol, we want | |
5274 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5275 | lui $at,<hiconstant> | |
5276 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5277 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5278 | */ |
438c16b8 | 5279 | |
252b5132 RH |
5280 | expr1.X_add_number = offset_expr.X_add_number; |
5281 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5282 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5283 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5284 | if (expr1.X_add_number == 0 && breg == 0 |
5285 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5286 | { |
5287 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5288 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5289 | } | |
67c0d1eb RS |
5290 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5291 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5292 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5293 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5294 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5295 | if (expr1.X_add_number == 0) |
5296 | { | |
67c0d1eb | 5297 | if (breg != 0) |
252b5132 RH |
5298 | { |
5299 | /* We're going to put in an addu instruction using | |
5300 | tempreg, so we may as well insert the nop right | |
5301 | now. */ | |
269137b2 | 5302 | load_delay_nop (); |
252b5132 | 5303 | } |
252b5132 RH |
5304 | } |
5305 | else if (expr1.X_add_number >= -0x8000 | |
5306 | && expr1.X_add_number < 0x8000) | |
5307 | { | |
269137b2 | 5308 | load_delay_nop (); |
67c0d1eb | 5309 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5310 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5311 | } |
5312 | else | |
5313 | { | |
67c0d1eb | 5314 | int dreg; |
252b5132 RH |
5315 | |
5316 | /* If we are going to add in a base register, and the | |
5317 | target register and the base register are the same, | |
5318 | then we are using AT as a temporary register. Since | |
5319 | we want to load the constant into AT, we add our | |
5320 | current AT (from the global offset table) and the | |
5321 | register into the register now, and pretend we were | |
5322 | not using a base register. */ | |
5323 | if (breg != treg) | |
67c0d1eb | 5324 | dreg = tempreg; |
252b5132 RH |
5325 | else |
5326 | { | |
5327 | assert (tempreg == AT); | |
269137b2 | 5328 | load_delay_nop (); |
67c0d1eb | 5329 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5330 | treg, AT, breg); |
252b5132 | 5331 | dreg = treg; |
252b5132 RH |
5332 | } |
5333 | ||
f6a22291 | 5334 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5335 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5336 | |
252b5132 RH |
5337 | used_at = 1; |
5338 | } | |
4d7206a2 RS |
5339 | offset_expr.X_add_number = |
5340 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5341 | relax_switch (); | |
252b5132 | 5342 | |
67c0d1eb | 5343 | if (gpdelay) |
252b5132 RH |
5344 | { |
5345 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5346 | the first instruction on the main stream does not. */ |
67c0d1eb | 5347 | macro_build (NULL, "nop", ""); |
252b5132 | 5348 | } |
ed6fb7bd | 5349 | |
67c0d1eb RS |
5350 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5351 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5352 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5353 | && expr1.X_add_number < 0x8000) |
5354 | { | |
269137b2 | 5355 | load_delay_nop (); |
67c0d1eb RS |
5356 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5357 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5358 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5359 | register, the external symbol case ended with a load, |
5360 | so if the symbol turns out to not be external, and | |
5361 | the next instruction uses tempreg, an unnecessary nop | |
5362 | will be inserted. */ | |
252b5132 RH |
5363 | } |
5364 | else | |
5365 | { | |
5366 | if (breg == treg) | |
5367 | { | |
5368 | /* We must add in the base register now, as in the | |
f5040a92 | 5369 | external symbol case. */ |
252b5132 | 5370 | assert (tempreg == AT); |
269137b2 | 5371 | load_delay_nop (); |
67c0d1eb | 5372 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5373 | treg, AT, breg); |
252b5132 RH |
5374 | tempreg = treg; |
5375 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5376 | it in in both cases. */ |
252b5132 RH |
5377 | breg = 0; |
5378 | } | |
5379 | ||
67c0d1eb RS |
5380 | macro_build_lui (&expr1, AT); |
5381 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5382 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5384 | tempreg, tempreg, AT); |
8fc2e39e | 5385 | used_at = 1; |
252b5132 | 5386 | } |
4d7206a2 | 5387 | relax_end (); |
252b5132 | 5388 | } |
f5040a92 AO |
5389 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5390 | { | |
f5040a92 AO |
5391 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5392 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5393 | int add_breg_early = 0; |
f5040a92 AO |
5394 | |
5395 | /* This is the large GOT case. If this is a reference to an | |
5396 | external symbol, and there is no constant, we want | |
5397 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5398 | add $tempreg,$tempreg,$gp | |
5399 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5400 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5401 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5402 | add $tempreg,$tempreg,$gp | |
5403 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5404 | ||
5405 | If we have a small constant, and this is a reference to | |
5406 | an external symbol, we want | |
5407 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5408 | add $tempreg,$tempreg,$gp | |
5409 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5410 | addi $tempreg,$tempreg,<constant> | |
5411 | ||
5412 | If we have a large constant, and this is a reference to | |
5413 | an external symbol, we want | |
5414 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5415 | addu $tempreg,$tempreg,$gp | |
5416 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5417 | lui $at,<hiconstant> | |
5418 | addi $at,$at,<loconstant> | |
5419 | add $tempreg,$tempreg,$at | |
5420 | ||
5421 | If we have NewABI, and we know it's a local symbol, we want | |
5422 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5423 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5424 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5425 | ||
4d7206a2 | 5426 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5427 | |
4d7206a2 | 5428 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5429 | offset_expr.X_add_number = 0; |
5430 | ||
1abe91b1 MR |
5431 | if (expr1.X_add_number == 0 && breg == 0 |
5432 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5433 | { |
5434 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5435 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5436 | } | |
67c0d1eb RS |
5437 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5439 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5440 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5441 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5442 | |
5443 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5444 | ; |
f5040a92 AO |
5445 | else if (expr1.X_add_number >= -0x8000 |
5446 | && expr1.X_add_number < 0x8000) | |
5447 | { | |
67c0d1eb | 5448 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5449 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5450 | } |
ecd13cd3 | 5451 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5452 | { |
5453 | int dreg; | |
5454 | ||
5455 | /* If we are going to add in a base register, and the | |
5456 | target register and the base register are the same, | |
5457 | then we are using AT as a temporary register. Since | |
5458 | we want to load the constant into AT, we add our | |
5459 | current AT (from the global offset table) and the | |
5460 | register into the register now, and pretend we were | |
5461 | not using a base register. */ | |
5462 | if (breg != treg) | |
5463 | dreg = tempreg; | |
5464 | else | |
5465 | { | |
5466 | assert (tempreg == AT); | |
67c0d1eb | 5467 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5468 | treg, AT, breg); |
f5040a92 | 5469 | dreg = treg; |
67c0d1eb | 5470 | add_breg_early = 1; |
f5040a92 AO |
5471 | } |
5472 | ||
f6a22291 | 5473 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5474 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5475 | |
f5040a92 AO |
5476 | used_at = 1; |
5477 | } | |
5478 | else | |
5479 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5480 | ||
4d7206a2 | 5481 | relax_switch (); |
f5040a92 | 5482 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5483 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5484 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5485 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5486 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5487 | if (add_breg_early) | |
f5040a92 | 5488 | { |
67c0d1eb | 5489 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5490 | treg, tempreg, breg); |
f5040a92 AO |
5491 | breg = 0; |
5492 | tempreg = treg; | |
5493 | } | |
4d7206a2 | 5494 | relax_end (); |
f5040a92 | 5495 | } |
252b5132 RH |
5496 | else |
5497 | abort (); | |
5498 | ||
5499 | if (breg != 0) | |
aed1a261 | 5500 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5501 | break; |
5502 | ||
5503 | case M_J_A: | |
5504 | /* The j instruction may not be used in PIC code, since it | |
5505 | requires an absolute address. We convert it to a b | |
5506 | instruction. */ | |
5507 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5508 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5509 | else |
67c0d1eb | 5510 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5511 | break; |
252b5132 RH |
5512 | |
5513 | /* The jal instructions must be handled as macros because when | |
5514 | generating PIC code they expand to multi-instruction | |
5515 | sequences. Normally they are simple instructions. */ | |
5516 | case M_JAL_1: | |
5517 | dreg = RA; | |
5518 | /* Fall through. */ | |
5519 | case M_JAL_2: | |
3e722fb5 | 5520 | if (mips_pic == NO_PIC) |
67c0d1eb | 5521 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5522 | else if (mips_pic == SVR4_PIC) |
5523 | { | |
5524 | if (sreg != PIC_CALL_REG) | |
5525 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5526 | |
67c0d1eb | 5527 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5528 | if (! HAVE_NEWABI) |
252b5132 | 5529 | { |
6478892d TS |
5530 | if (mips_cprestore_offset < 0) |
5531 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5532 | else | |
5533 | { | |
7a621144 DJ |
5534 | if (! mips_frame_reg_valid) |
5535 | { | |
5536 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5537 | /* Quiet this warning. */ | |
5538 | mips_frame_reg_valid = 1; | |
5539 | } | |
5540 | if (! mips_cprestore_valid) | |
5541 | { | |
5542 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5543 | /* Quiet this warning. */ | |
5544 | mips_cprestore_valid = 1; | |
5545 | } | |
6478892d | 5546 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5547 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5548 | mips_gp_register, |
256ab948 TS |
5549 | mips_frame_reg, |
5550 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5551 | } |
252b5132 RH |
5552 | } |
5553 | } | |
5554 | else | |
5555 | abort (); | |
5556 | ||
8fc2e39e | 5557 | break; |
252b5132 RH |
5558 | |
5559 | case M_JAL_A: | |
5560 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5561 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5562 | else if (mips_pic == SVR4_PIC) |
5563 | { | |
5564 | /* If this is a reference to an external symbol, and we are | |
5565 | using a small GOT, we want | |
5566 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5567 | nop | |
f9419b05 | 5568 | jalr $ra,$25 |
252b5132 RH |
5569 | nop |
5570 | lw $gp,cprestore($sp) | |
5571 | The cprestore value is set using the .cprestore | |
5572 | pseudo-op. If we are using a big GOT, we want | |
5573 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5574 | addu $25,$25,$gp | |
5575 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5576 | nop | |
f9419b05 | 5577 | jalr $ra,$25 |
252b5132 RH |
5578 | nop |
5579 | lw $gp,cprestore($sp) | |
5580 | If the symbol is not external, we want | |
5581 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5582 | nop | |
5583 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5584 | jalr $ra,$25 |
252b5132 | 5585 | nop |
438c16b8 | 5586 | lw $gp,cprestore($sp) |
f5040a92 AO |
5587 | |
5588 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5589 | sequences above, minus nops, unless the symbol is local, | |
5590 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5591 | GOT_DISP. */ | |
438c16b8 | 5592 | if (HAVE_NEWABI) |
252b5132 | 5593 | { |
f5040a92 AO |
5594 | if (! mips_big_got) |
5595 | { | |
4d7206a2 | 5596 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5597 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5598 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5599 | mips_gp_register); |
4d7206a2 | 5600 | relax_switch (); |
67c0d1eb RS |
5601 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5602 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5603 | mips_gp_register); |
5604 | relax_end (); | |
f5040a92 AO |
5605 | } |
5606 | else | |
5607 | { | |
4d7206a2 | 5608 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5609 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5610 | BFD_RELOC_MIPS_CALL_HI16); | |
5611 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5612 | PIC_CALL_REG, mips_gp_register); | |
5613 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5614 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5615 | PIC_CALL_REG); | |
4d7206a2 | 5616 | relax_switch (); |
67c0d1eb RS |
5617 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5618 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5619 | mips_gp_register); | |
5620 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5621 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5622 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5623 | relax_end (); |
f5040a92 | 5624 | } |
684022ea | 5625 | |
67c0d1eb | 5626 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5627 | } |
5628 | else | |
5629 | { | |
4d7206a2 | 5630 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5631 | if (! mips_big_got) |
5632 | { | |
67c0d1eb RS |
5633 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5634 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5635 | mips_gp_register); |
269137b2 | 5636 | load_delay_nop (); |
4d7206a2 | 5637 | relax_switch (); |
438c16b8 | 5638 | } |
252b5132 | 5639 | else |
252b5132 | 5640 | { |
67c0d1eb RS |
5641 | int gpdelay; |
5642 | ||
5643 | gpdelay = reg_needs_delay (mips_gp_register); | |
5644 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5645 | BFD_RELOC_MIPS_CALL_HI16); | |
5646 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5647 | PIC_CALL_REG, mips_gp_register); | |
5648 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5649 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5650 | PIC_CALL_REG); | |
269137b2 | 5651 | load_delay_nop (); |
4d7206a2 | 5652 | relax_switch (); |
67c0d1eb RS |
5653 | if (gpdelay) |
5654 | macro_build (NULL, "nop", ""); | |
252b5132 | 5655 | } |
67c0d1eb RS |
5656 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5657 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5658 | mips_gp_register); |
269137b2 | 5659 | load_delay_nop (); |
67c0d1eb RS |
5660 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5661 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5662 | relax_end (); |
67c0d1eb | 5663 | macro_build_jalr (&offset_expr); |
438c16b8 | 5664 | |
6478892d TS |
5665 | if (mips_cprestore_offset < 0) |
5666 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5667 | else | |
5668 | { | |
7a621144 DJ |
5669 | if (! mips_frame_reg_valid) |
5670 | { | |
5671 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5672 | /* Quiet this warning. */ | |
5673 | mips_frame_reg_valid = 1; | |
5674 | } | |
5675 | if (! mips_cprestore_valid) | |
5676 | { | |
5677 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5678 | /* Quiet this warning. */ | |
5679 | mips_cprestore_valid = 1; | |
5680 | } | |
6478892d | 5681 | if (mips_opts.noreorder) |
67c0d1eb | 5682 | macro_build (NULL, "nop", ""); |
6478892d | 5683 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5684 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5685 | mips_gp_register, |
256ab948 TS |
5686 | mips_frame_reg, |
5687 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5688 | } |
252b5132 RH |
5689 | } |
5690 | } | |
252b5132 RH |
5691 | else |
5692 | abort (); | |
5693 | ||
8fc2e39e | 5694 | break; |
252b5132 RH |
5695 | |
5696 | case M_LB_AB: | |
5697 | s = "lb"; | |
5698 | goto ld; | |
5699 | case M_LBU_AB: | |
5700 | s = "lbu"; | |
5701 | goto ld; | |
5702 | case M_LH_AB: | |
5703 | s = "lh"; | |
5704 | goto ld; | |
5705 | case M_LHU_AB: | |
5706 | s = "lhu"; | |
5707 | goto ld; | |
5708 | case M_LW_AB: | |
5709 | s = "lw"; | |
5710 | goto ld; | |
5711 | case M_LWC0_AB: | |
5712 | s = "lwc0"; | |
bdaaa2e1 | 5713 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5714 | coproc = 1; |
5715 | goto ld; | |
5716 | case M_LWC1_AB: | |
5717 | s = "lwc1"; | |
bdaaa2e1 | 5718 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5719 | coproc = 1; |
5720 | goto ld; | |
5721 | case M_LWC2_AB: | |
5722 | s = "lwc2"; | |
bdaaa2e1 | 5723 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5724 | coproc = 1; |
5725 | goto ld; | |
5726 | case M_LWC3_AB: | |
5727 | s = "lwc3"; | |
bdaaa2e1 | 5728 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5729 | coproc = 1; |
5730 | goto ld; | |
5731 | case M_LWL_AB: | |
5732 | s = "lwl"; | |
5733 | lr = 1; | |
5734 | goto ld; | |
5735 | case M_LWR_AB: | |
5736 | s = "lwr"; | |
5737 | lr = 1; | |
5738 | goto ld; | |
5739 | case M_LDC1_AB: | |
fef14a42 | 5740 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5741 | { |
5742 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5743 | break; |
252b5132 RH |
5744 | } |
5745 | s = "ldc1"; | |
bdaaa2e1 | 5746 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5747 | coproc = 1; |
5748 | goto ld; | |
5749 | case M_LDC2_AB: | |
5750 | s = "ldc2"; | |
bdaaa2e1 | 5751 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5752 | coproc = 1; |
5753 | goto ld; | |
5754 | case M_LDC3_AB: | |
5755 | s = "ldc3"; | |
bdaaa2e1 | 5756 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5757 | coproc = 1; |
5758 | goto ld; | |
5759 | case M_LDL_AB: | |
5760 | s = "ldl"; | |
5761 | lr = 1; | |
5762 | goto ld; | |
5763 | case M_LDR_AB: | |
5764 | s = "ldr"; | |
5765 | lr = 1; | |
5766 | goto ld; | |
5767 | case M_LL_AB: | |
5768 | s = "ll"; | |
5769 | goto ld; | |
5770 | case M_LLD_AB: | |
5771 | s = "lld"; | |
5772 | goto ld; | |
5773 | case M_LWU_AB: | |
5774 | s = "lwu"; | |
5775 | ld: | |
8fc2e39e | 5776 | if (breg == treg || coproc || lr) |
252b5132 RH |
5777 | { |
5778 | tempreg = AT; | |
5779 | used_at = 1; | |
5780 | } | |
5781 | else | |
5782 | { | |
5783 | tempreg = treg; | |
252b5132 RH |
5784 | } |
5785 | goto ld_st; | |
5786 | case M_SB_AB: | |
5787 | s = "sb"; | |
5788 | goto st; | |
5789 | case M_SH_AB: | |
5790 | s = "sh"; | |
5791 | goto st; | |
5792 | case M_SW_AB: | |
5793 | s = "sw"; | |
5794 | goto st; | |
5795 | case M_SWC0_AB: | |
5796 | s = "swc0"; | |
bdaaa2e1 | 5797 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5798 | coproc = 1; |
5799 | goto st; | |
5800 | case M_SWC1_AB: | |
5801 | s = "swc1"; | |
bdaaa2e1 | 5802 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5803 | coproc = 1; |
5804 | goto st; | |
5805 | case M_SWC2_AB: | |
5806 | s = "swc2"; | |
bdaaa2e1 | 5807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5808 | coproc = 1; |
5809 | goto st; | |
5810 | case M_SWC3_AB: | |
5811 | s = "swc3"; | |
bdaaa2e1 | 5812 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5813 | coproc = 1; |
5814 | goto st; | |
5815 | case M_SWL_AB: | |
5816 | s = "swl"; | |
5817 | goto st; | |
5818 | case M_SWR_AB: | |
5819 | s = "swr"; | |
5820 | goto st; | |
5821 | case M_SC_AB: | |
5822 | s = "sc"; | |
5823 | goto st; | |
5824 | case M_SCD_AB: | |
5825 | s = "scd"; | |
5826 | goto st; | |
5827 | case M_SDC1_AB: | |
fef14a42 | 5828 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5829 | { |
5830 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5831 | break; |
252b5132 RH |
5832 | } |
5833 | s = "sdc1"; | |
5834 | coproc = 1; | |
bdaaa2e1 | 5835 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5836 | goto st; |
5837 | case M_SDC2_AB: | |
5838 | s = "sdc2"; | |
bdaaa2e1 | 5839 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5840 | coproc = 1; |
5841 | goto st; | |
5842 | case M_SDC3_AB: | |
5843 | s = "sdc3"; | |
bdaaa2e1 | 5844 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5845 | coproc = 1; |
5846 | goto st; | |
5847 | case M_SDL_AB: | |
5848 | s = "sdl"; | |
5849 | goto st; | |
5850 | case M_SDR_AB: | |
5851 | s = "sdr"; | |
5852 | st: | |
8fc2e39e TS |
5853 | tempreg = AT; |
5854 | used_at = 1; | |
252b5132 | 5855 | ld_st: |
bdaaa2e1 | 5856 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5857 | if (mask == M_LWC1_AB |
5858 | || mask == M_SWC1_AB | |
5859 | || mask == M_LDC1_AB | |
5860 | || mask == M_SDC1_AB | |
5861 | || mask == M_L_DAB | |
5862 | || mask == M_S_DAB) | |
5863 | fmt = "T,o(b)"; | |
5864 | else if (coproc) | |
5865 | fmt = "E,o(b)"; | |
5866 | else | |
5867 | fmt = "t,o(b)"; | |
5868 | ||
5869 | if (offset_expr.X_op != O_constant | |
5870 | && offset_expr.X_op != O_symbol) | |
5871 | { | |
5872 | as_bad (_("expression too complex")); | |
5873 | offset_expr.X_op = O_constant; | |
5874 | } | |
5875 | ||
5876 | /* A constant expression in PIC code can be handled just as it | |
5877 | is in non PIC code. */ | |
aed1a261 RS |
5878 | if (offset_expr.X_op == O_constant) |
5879 | { | |
5880 | if (HAVE_32BIT_ADDRESSES | |
5881 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5882 | as_bad (_("constant too large")); | |
5883 | ||
5884 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) | |
5885 | & ~(bfd_vma) 0xffff); | |
5886 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
5887 | if (breg != 0) | |
5888 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5889 | tempreg, tempreg, breg); | |
5890 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5891 | } | |
5892 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5893 | { |
5894 | /* If this is a reference to a GP relative symbol, and there | |
5895 | is no base register, we want | |
cdf6fd85 | 5896 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5897 | Otherwise, if there is no base register, we want |
5898 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5899 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5900 | If we have a constant, we need two instructions anyhow, | |
5901 | so we always use the latter form. | |
5902 | ||
5903 | If we have a base register, and this is a reference to a | |
5904 | GP relative symbol, we want | |
5905 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5906 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5907 | Otherwise we want |
5908 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5909 | addu $tempreg,$tempreg,$breg | |
5910 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5911 | With a constant we always use the latter case. |
76b3015f | 5912 | |
d6bc6245 TS |
5913 | With 64bit address space and no base register and $at usable, |
5914 | we want | |
5915 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5916 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5917 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5918 | dsll32 $tempreg,0 | |
5919 | daddu $tempreg,$at | |
5920 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5921 | If we have a base register, we want | |
5922 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5923 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5924 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5925 | daddu $at,$breg | |
5926 | dsll32 $tempreg,0 | |
5927 | daddu $tempreg,$at | |
5928 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5929 | ||
5930 | Without $at we can't generate the optimal path for superscalar | |
5931 | processors here since this would require two temporary registers. | |
5932 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5933 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5934 | dsll $tempreg,16 | |
5935 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5936 | dsll $tempreg,16 | |
5937 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5938 | If we have a base register, we want | |
5939 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5940 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5941 | dsll $tempreg,16 | |
5942 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5943 | dsll $tempreg,16 | |
5944 | daddu $tempreg,$tempreg,$breg | |
5945 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5946 | |
6caf9ef4 | 5947 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5948 | the same sequence as in 32bit address space. */ |
5949 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5950 | { |
aed1a261 | 5951 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5952 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5953 | { | |
5954 | relax_start (offset_expr.X_add_symbol); | |
5955 | if (breg == 0) | |
5956 | { | |
5957 | macro_build (&offset_expr, s, fmt, treg, | |
5958 | BFD_RELOC_GPREL16, mips_gp_register); | |
5959 | } | |
5960 | else | |
5961 | { | |
5962 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5963 | tempreg, breg, mips_gp_register); | |
5964 | macro_build (&offset_expr, s, fmt, treg, | |
5965 | BFD_RELOC_GPREL16, tempreg); | |
5966 | } | |
5967 | relax_switch (); | |
5968 | } | |
d6bc6245 | 5969 | |
b8285c27 | 5970 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5971 | { |
67c0d1eb RS |
5972 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5973 | BFD_RELOC_MIPS_HIGHEST); | |
5974 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5975 | BFD_RELOC_HI16_S); | |
5976 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5977 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5978 | if (breg != 0) |
67c0d1eb RS |
5979 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5980 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5981 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5982 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5983 | tempreg); | |
d6bc6245 TS |
5984 | used_at = 1; |
5985 | } | |
5986 | else | |
5987 | { | |
67c0d1eb RS |
5988 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5989 | BFD_RELOC_MIPS_HIGHEST); | |
5990 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5991 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5992 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5993 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5994 | tempreg, BFD_RELOC_HI16_S); | |
5995 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5996 | if (breg != 0) |
67c0d1eb | 5997 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5998 | tempreg, tempreg, breg); |
67c0d1eb | 5999 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6000 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6001 | } |
6caf9ef4 TS |
6002 | |
6003 | if (mips_relax.sequence) | |
6004 | relax_end (); | |
8fc2e39e | 6005 | break; |
d6bc6245 | 6006 | } |
256ab948 | 6007 | |
252b5132 RH |
6008 | if (breg == 0) |
6009 | { | |
67c0d1eb | 6010 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6011 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6012 | { |
4d7206a2 | 6013 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6014 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6015 | mips_gp_register); | |
4d7206a2 | 6016 | relax_switch (); |
252b5132 | 6017 | } |
67c0d1eb RS |
6018 | macro_build_lui (&offset_expr, tempreg); |
6019 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6020 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6021 | if (mips_relax.sequence) |
6022 | relax_end (); | |
252b5132 RH |
6023 | } |
6024 | else | |
6025 | { | |
67c0d1eb | 6026 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6027 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6028 | { |
4d7206a2 | 6029 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6030 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6031 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6032 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6033 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6034 | relax_switch (); |
252b5132 | 6035 | } |
67c0d1eb RS |
6036 | macro_build_lui (&offset_expr, tempreg); |
6037 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6038 | tempreg, tempreg, breg); |
67c0d1eb | 6039 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6040 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6041 | if (mips_relax.sequence) |
6042 | relax_end (); | |
252b5132 RH |
6043 | } |
6044 | } | |
6045 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6046 | { | |
ed6fb7bd | 6047 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6048 | |
252b5132 RH |
6049 | /* If this is a reference to an external symbol, we want |
6050 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6051 | nop | |
6052 | <op> $treg,0($tempreg) | |
6053 | Otherwise we want | |
6054 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6055 | nop | |
6056 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6057 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6058 | |
6059 | For NewABI, we want | |
6060 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6061 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6062 | ||
252b5132 RH |
6063 | If there is a base register, we add it to $tempreg before |
6064 | the <op>. If there is a constant, we stick it in the | |
6065 | <op> instruction. We don't handle constants larger than | |
6066 | 16 bits, because we have no way to load the upper 16 bits | |
6067 | (actually, we could handle them for the subset of cases | |
6068 | in which we are not using $at). */ | |
6069 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6070 | if (HAVE_NEWABI) |
6071 | { | |
67c0d1eb RS |
6072 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6073 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6074 | if (breg != 0) |
67c0d1eb | 6075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6076 | tempreg, tempreg, breg); |
67c0d1eb | 6077 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6078 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6079 | break; |
6080 | } | |
252b5132 RH |
6081 | expr1.X_add_number = offset_expr.X_add_number; |
6082 | offset_expr.X_add_number = 0; | |
6083 | if (expr1.X_add_number < -0x8000 | |
6084 | || expr1.X_add_number >= 0x8000) | |
6085 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6086 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6087 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6088 | load_delay_nop (); |
4d7206a2 RS |
6089 | relax_start (offset_expr.X_add_symbol); |
6090 | relax_switch (); | |
67c0d1eb RS |
6091 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6092 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6093 | relax_end (); |
252b5132 | 6094 | if (breg != 0) |
67c0d1eb | 6095 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6096 | tempreg, tempreg, breg); |
67c0d1eb | 6097 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6098 | } |
f5040a92 | 6099 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6100 | { |
67c0d1eb | 6101 | int gpdelay; |
252b5132 RH |
6102 | |
6103 | /* If this is a reference to an external symbol, we want | |
6104 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6105 | addu $tempreg,$tempreg,$gp | |
6106 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6107 | <op> $treg,0($tempreg) | |
6108 | Otherwise we want | |
6109 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6110 | nop | |
6111 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6112 | <op> $treg,0($tempreg) | |
6113 | If there is a base register, we add it to $tempreg before | |
6114 | the <op>. If there is a constant, we stick it in the | |
6115 | <op> instruction. We don't handle constants larger than | |
6116 | 16 bits, because we have no way to load the upper 16 bits | |
6117 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6118 | in which we are not using $at). */ |
252b5132 RH |
6119 | assert (offset_expr.X_op == O_symbol); |
6120 | expr1.X_add_number = offset_expr.X_add_number; | |
6121 | offset_expr.X_add_number = 0; | |
6122 | if (expr1.X_add_number < -0x8000 | |
6123 | || expr1.X_add_number >= 0x8000) | |
6124 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6125 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6126 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6127 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6128 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6130 | mips_gp_register); | |
6131 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6132 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6133 | relax_switch (); |
67c0d1eb RS |
6134 | if (gpdelay) |
6135 | macro_build (NULL, "nop", ""); | |
6136 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6137 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6138 | load_delay_nop (); |
67c0d1eb RS |
6139 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6140 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6141 | relax_end (); |
6142 | ||
252b5132 | 6143 | if (breg != 0) |
67c0d1eb | 6144 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6145 | tempreg, tempreg, breg); |
67c0d1eb | 6146 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6147 | } |
f5040a92 AO |
6148 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6149 | { | |
f5040a92 AO |
6150 | /* If this is a reference to an external symbol, we want |
6151 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6152 | add $tempreg,$tempreg,$gp | |
6153 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6154 | <op> $treg,<ofst>($tempreg) | |
6155 | Otherwise, for local symbols, we want: | |
6156 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6157 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6158 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6159 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6160 | offset_expr.X_add_number = 0; |
6161 | if (expr1.X_add_number < -0x8000 | |
6162 | || expr1.X_add_number >= 0x8000) | |
6163 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6164 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6165 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6166 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6167 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6168 | mips_gp_register); | |
6169 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6170 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6171 | if (breg != 0) |
67c0d1eb | 6172 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6173 | tempreg, tempreg, breg); |
67c0d1eb | 6174 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6175 | |
4d7206a2 | 6176 | relax_switch (); |
f5040a92 | 6177 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6178 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6179 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6180 | if (breg != 0) |
67c0d1eb | 6181 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6182 | tempreg, tempreg, breg); |
67c0d1eb | 6183 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6184 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6185 | relax_end (); |
f5040a92 | 6186 | } |
252b5132 RH |
6187 | else |
6188 | abort (); | |
6189 | ||
252b5132 RH |
6190 | break; |
6191 | ||
6192 | case M_LI: | |
6193 | case M_LI_S: | |
67c0d1eb | 6194 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6195 | break; |
252b5132 RH |
6196 | |
6197 | case M_DLI: | |
67c0d1eb | 6198 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6199 | break; |
252b5132 RH |
6200 | |
6201 | case M_LI_SS: | |
6202 | if (imm_expr.X_op == O_constant) | |
6203 | { | |
8fc2e39e | 6204 | used_at = 1; |
67c0d1eb RS |
6205 | load_register (AT, &imm_expr, 0); |
6206 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6207 | break; |
6208 | } | |
6209 | else | |
6210 | { | |
6211 | assert (offset_expr.X_op == O_symbol | |
6212 | && strcmp (segment_name (S_GET_SEGMENT | |
6213 | (offset_expr.X_add_symbol)), | |
6214 | ".lit4") == 0 | |
6215 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6216 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6217 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6218 | break; |
252b5132 RH |
6219 | } |
6220 | ||
6221 | case M_LI_D: | |
ca4e0257 RS |
6222 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6223 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6224 | order 32 bits of the value and the low order 32 bits are either | |
6225 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6226 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6227 | { | |
ca4e0257 | 6228 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6229 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6230 | else |
6231 | { | |
6232 | int hreg, lreg; | |
6233 | ||
6234 | if (target_big_endian) | |
6235 | { | |
6236 | hreg = treg; | |
6237 | lreg = treg + 1; | |
6238 | } | |
6239 | else | |
6240 | { | |
6241 | hreg = treg + 1; | |
6242 | lreg = treg; | |
6243 | } | |
6244 | ||
6245 | if (hreg <= 31) | |
67c0d1eb | 6246 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6247 | if (lreg <= 31) |
6248 | { | |
6249 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6250 | move_register (lreg, 0); |
252b5132 RH |
6251 | else |
6252 | { | |
6253 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6254 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6255 | } |
6256 | } | |
6257 | } | |
8fc2e39e | 6258 | break; |
252b5132 RH |
6259 | } |
6260 | ||
6261 | /* We know that sym is in the .rdata section. First we get the | |
6262 | upper 16 bits of the address. */ | |
6263 | if (mips_pic == NO_PIC) | |
6264 | { | |
67c0d1eb | 6265 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6266 | used_at = 1; |
252b5132 RH |
6267 | } |
6268 | else if (mips_pic == SVR4_PIC) | |
6269 | { | |
67c0d1eb RS |
6270 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6271 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6272 | used_at = 1; |
252b5132 | 6273 | } |
252b5132 RH |
6274 | else |
6275 | abort (); | |
bdaaa2e1 | 6276 | |
252b5132 | 6277 | /* Now we load the register(s). */ |
ca4e0257 | 6278 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6279 | { |
6280 | used_at = 1; | |
6281 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6282 | } | |
252b5132 RH |
6283 | else |
6284 | { | |
8fc2e39e | 6285 | used_at = 1; |
67c0d1eb | 6286 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6287 | if (treg != RA) |
252b5132 RH |
6288 | { |
6289 | /* FIXME: How in the world do we deal with the possible | |
6290 | overflow here? */ | |
6291 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6292 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6293 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6294 | } |
6295 | } | |
252b5132 RH |
6296 | break; |
6297 | ||
6298 | case M_LI_DD: | |
ca4e0257 RS |
6299 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6300 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6301 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6302 | the value and the low order 32 bits are either zero or in | |
6303 | OFFSET_EXPR. */ | |
252b5132 RH |
6304 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6305 | { | |
8fc2e39e | 6306 | used_at = 1; |
67c0d1eb | 6307 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6308 | if (HAVE_64BIT_FPRS) |
6309 | { | |
6310 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6311 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6312 | } |
252b5132 RH |
6313 | else |
6314 | { | |
67c0d1eb | 6315 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6316 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6317 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6318 | else |
6319 | { | |
6320 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6321 | load_register (AT, &offset_expr, 0); |
6322 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6323 | } |
6324 | } | |
6325 | break; | |
6326 | } | |
6327 | ||
6328 | assert (offset_expr.X_op == O_symbol | |
6329 | && offset_expr.X_add_number == 0); | |
6330 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6331 | if (strcmp (s, ".lit8") == 0) | |
6332 | { | |
e7af610e | 6333 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6334 | { |
67c0d1eb | 6335 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6336 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6337 | break; |
252b5132 | 6338 | } |
c9914766 | 6339 | breg = mips_gp_register; |
252b5132 RH |
6340 | r = BFD_RELOC_MIPS_LITERAL; |
6341 | goto dob; | |
6342 | } | |
6343 | else | |
6344 | { | |
6345 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6346 | used_at = 1; |
252b5132 | 6347 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6348 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6349 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6350 | else |
6351 | { | |
6352 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6353 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6354 | } |
bdaaa2e1 | 6355 | |
e7af610e | 6356 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6357 | { |
67c0d1eb RS |
6358 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6359 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6360 | break; |
6361 | } | |
6362 | breg = AT; | |
6363 | r = BFD_RELOC_LO16; | |
6364 | goto dob; | |
6365 | } | |
6366 | ||
6367 | case M_L_DOB: | |
fef14a42 | 6368 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6369 | { |
6370 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6371 | break; |
252b5132 RH |
6372 | } |
6373 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6374 | to adjust when loading from memory. */ | |
6375 | r = BFD_RELOC_LO16; | |
6376 | dob: | |
e7af610e | 6377 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6378 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6379 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6380 | /* FIXME: A possible overflow which I don't know how to deal |
6381 | with. */ | |
6382 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6383 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6384 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6385 | break; |
6386 | ||
6387 | case M_L_DAB: | |
6388 | /* | |
6389 | * The MIPS assembler seems to check for X_add_number not | |
6390 | * being double aligned and generating: | |
6391 | * lui at,%hi(foo+1) | |
6392 | * addu at,at,v1 | |
6393 | * addiu at,at,%lo(foo+1) | |
6394 | * lwc1 f2,0(at) | |
6395 | * lwc1 f3,4(at) | |
6396 | * But, the resulting address is the same after relocation so why | |
6397 | * generate the extra instruction? | |
6398 | */ | |
fef14a42 | 6399 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6400 | { |
6401 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6402 | break; |
252b5132 | 6403 | } |
bdaaa2e1 | 6404 | /* Itbl support may require additional care here. */ |
252b5132 | 6405 | coproc = 1; |
e7af610e | 6406 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6407 | { |
6408 | s = "ldc1"; | |
6409 | goto ld; | |
6410 | } | |
6411 | ||
6412 | s = "lwc1"; | |
6413 | fmt = "T,o(b)"; | |
6414 | goto ldd_std; | |
6415 | ||
6416 | case M_S_DAB: | |
fef14a42 | 6417 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6418 | { |
6419 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6420 | break; |
252b5132 RH |
6421 | } |
6422 | ||
e7af610e | 6423 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6424 | { |
6425 | s = "sdc1"; | |
6426 | goto st; | |
6427 | } | |
6428 | ||
6429 | s = "swc1"; | |
6430 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6431 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6432 | coproc = 1; |
6433 | goto ldd_std; | |
6434 | ||
6435 | case M_LD_AB: | |
ca4e0257 | 6436 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6437 | { |
6438 | s = "ld"; | |
6439 | goto ld; | |
6440 | } | |
6441 | ||
6442 | s = "lw"; | |
6443 | fmt = "t,o(b)"; | |
6444 | goto ldd_std; | |
6445 | ||
6446 | case M_SD_AB: | |
ca4e0257 | 6447 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6448 | { |
6449 | s = "sd"; | |
6450 | goto st; | |
6451 | } | |
6452 | ||
6453 | s = "sw"; | |
6454 | fmt = "t,o(b)"; | |
6455 | ||
6456 | ldd_std: | |
6457 | if (offset_expr.X_op != O_symbol | |
6458 | && offset_expr.X_op != O_constant) | |
6459 | { | |
6460 | as_bad (_("expression too complex")); | |
6461 | offset_expr.X_op = O_constant; | |
6462 | } | |
6463 | ||
6464 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6465 | to adjust when loading from memory. We set coproc if we must | |
6466 | load $fn+1 first. */ | |
bdaaa2e1 | 6467 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6468 | if (! target_big_endian) |
6469 | coproc = 0; | |
6470 | ||
6471 | if (mips_pic == NO_PIC | |
6472 | || offset_expr.X_op == O_constant) | |
6473 | { | |
6474 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6475 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6476 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6477 | If we have a base register, we use this |
6478 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6479 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6480 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6481 | If this is not a GP relative symbol, we want |
6482 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6483 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6484 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6485 | If there is a base register, we add it to $at after the | |
6486 | lui instruction. If there is a constant, we always use | |
6487 | the last case. */ | |
6caf9ef4 TS |
6488 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6489 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6490 | { |
4d7206a2 | 6491 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6492 | if (breg == 0) |
6493 | { | |
c9914766 | 6494 | tempreg = mips_gp_register; |
252b5132 RH |
6495 | } |
6496 | else | |
6497 | { | |
67c0d1eb | 6498 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6499 | AT, breg, mips_gp_register); |
252b5132 | 6500 | tempreg = AT; |
252b5132 RH |
6501 | used_at = 1; |
6502 | } | |
6503 | ||
beae10d5 | 6504 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6505 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6506 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6507 | offset_expr.X_add_number += 4; |
6508 | ||
6509 | /* Set mips_optimize to 2 to avoid inserting an | |
6510 | undesired nop. */ | |
6511 | hold_mips_optimize = mips_optimize; | |
6512 | mips_optimize = 2; | |
beae10d5 | 6513 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6514 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6515 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6516 | mips_optimize = hold_mips_optimize; |
6517 | ||
4d7206a2 | 6518 | relax_switch (); |
252b5132 RH |
6519 | |
6520 | /* We just generated two relocs. When tc_gen_reloc | |
6521 | handles this case, it will skip the first reloc and | |
6522 | handle the second. The second reloc already has an | |
6523 | extra addend of 4, which we added above. We must | |
6524 | subtract it out, and then subtract another 4 to make | |
6525 | the first reloc come out right. The second reloc | |
6526 | will come out right because we are going to add 4 to | |
6527 | offset_expr when we build its instruction below. | |
6528 | ||
6529 | If we have a symbol, then we don't want to include | |
6530 | the offset, because it will wind up being included | |
6531 | when we generate the reloc. */ | |
6532 | ||
6533 | if (offset_expr.X_op == O_constant) | |
6534 | offset_expr.X_add_number -= 8; | |
6535 | else | |
6536 | { | |
6537 | offset_expr.X_add_number = -4; | |
6538 | offset_expr.X_op = O_constant; | |
6539 | } | |
6540 | } | |
8fc2e39e | 6541 | used_at = 1; |
67c0d1eb | 6542 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6543 | if (breg != 0) |
67c0d1eb | 6544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6545 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6546 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6547 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6548 | /* FIXME: How do we handle overflow here? */ |
6549 | offset_expr.X_add_number += 4; | |
beae10d5 | 6550 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6551 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6552 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6553 | if (mips_relax.sequence) |
6554 | relax_end (); | |
bdaaa2e1 | 6555 | } |
252b5132 RH |
6556 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6557 | { | |
252b5132 RH |
6558 | /* If this is a reference to an external symbol, we want |
6559 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6560 | nop | |
6561 | <op> $treg,0($at) | |
6562 | <op> $treg+1,4($at) | |
6563 | Otherwise we want | |
6564 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6565 | nop | |
6566 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6567 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6568 | If there is a base register we add it to $at before the | |
6569 | lwc1 instructions. If there is a constant we include it | |
6570 | in the lwc1 instructions. */ | |
6571 | used_at = 1; | |
6572 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6573 | if (expr1.X_add_number < -0x8000 |
6574 | || expr1.X_add_number >= 0x8000 - 4) | |
6575 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6576 | load_got_offset (AT, &offset_expr); |
269137b2 | 6577 | load_delay_nop (); |
252b5132 | 6578 | if (breg != 0) |
67c0d1eb | 6579 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6580 | |
6581 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6582 | nop. */ | |
6583 | hold_mips_optimize = mips_optimize; | |
6584 | mips_optimize = 2; | |
4d7206a2 | 6585 | |
beae10d5 | 6586 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6587 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6588 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6589 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6590 | expr1.X_add_number += 4; |
67c0d1eb RS |
6591 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6592 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6593 | relax_switch (); |
67c0d1eb RS |
6594 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6595 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6596 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6597 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6598 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6599 | relax_end (); |
252b5132 | 6600 | |
4d7206a2 | 6601 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6602 | } |
6603 | else if (mips_pic == SVR4_PIC) | |
6604 | { | |
67c0d1eb | 6605 | int gpdelay; |
252b5132 RH |
6606 | |
6607 | /* If this is a reference to an external symbol, we want | |
6608 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6609 | addu $at,$at,$gp | |
6610 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6611 | nop | |
6612 | <op> $treg,0($at) | |
6613 | <op> $treg+1,4($at) | |
6614 | Otherwise we want | |
6615 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6616 | nop | |
6617 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6618 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6619 | If there is a base register we add it to $at before the | |
6620 | lwc1 instructions. If there is a constant we include it | |
6621 | in the lwc1 instructions. */ | |
6622 | used_at = 1; | |
6623 | expr1.X_add_number = offset_expr.X_add_number; | |
6624 | offset_expr.X_add_number = 0; | |
6625 | if (expr1.X_add_number < -0x8000 | |
6626 | || expr1.X_add_number >= 0x8000 - 4) | |
6627 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6628 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6629 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6630 | macro_build (&offset_expr, "lui", "t,u", |
6631 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6632 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6633 | AT, AT, mips_gp_register); |
67c0d1eb | 6634 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6635 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6636 | load_delay_nop (); |
252b5132 | 6637 | if (breg != 0) |
67c0d1eb | 6638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6639 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6640 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6641 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6642 | expr1.X_add_number += 4; |
6643 | ||
6644 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6645 | nop. */ | |
6646 | hold_mips_optimize = mips_optimize; | |
6647 | mips_optimize = 2; | |
beae10d5 | 6648 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6649 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6650 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6651 | mips_optimize = hold_mips_optimize; |
6652 | expr1.X_add_number -= 4; | |
6653 | ||
4d7206a2 RS |
6654 | relax_switch (); |
6655 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6656 | if (gpdelay) |
6657 | macro_build (NULL, "nop", ""); | |
6658 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6659 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6660 | load_delay_nop (); |
252b5132 | 6661 | if (breg != 0) |
67c0d1eb | 6662 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6663 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6664 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6665 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6666 | offset_expr.X_add_number += 4; |
252b5132 RH |
6667 | |
6668 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6669 | nop. */ | |
6670 | hold_mips_optimize = mips_optimize; | |
6671 | mips_optimize = 2; | |
beae10d5 | 6672 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6673 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6674 | BFD_RELOC_LO16, AT); | |
252b5132 | 6675 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6676 | relax_end (); |
252b5132 | 6677 | } |
252b5132 RH |
6678 | else |
6679 | abort (); | |
6680 | ||
252b5132 RH |
6681 | break; |
6682 | ||
6683 | case M_LD_OB: | |
6684 | s = "lw"; | |
6685 | goto sd_ob; | |
6686 | case M_SD_OB: | |
6687 | s = "sw"; | |
6688 | sd_ob: | |
ca4e0257 | 6689 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6690 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6691 | offset_expr.X_add_number += 4; |
67c0d1eb | 6692 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6693 | break; |
252b5132 RH |
6694 | |
6695 | /* New code added to support COPZ instructions. | |
6696 | This code builds table entries out of the macros in mip_opcodes. | |
6697 | R4000 uses interlocks to handle coproc delays. | |
6698 | Other chips (like the R3000) require nops to be inserted for delays. | |
6699 | ||
f72c8c98 | 6700 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6701 | In order to fill delay slots for non-interlocked chips, |
6702 | we must have a way to specify delays based on the coprocessor. | |
6703 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6704 | What are the side-effects of the cop instruction? | |
6705 | What cache support might we have and what are its effects? | |
6706 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6707 | What registers are read/set/modified? |
252b5132 RH |
6708 | |
6709 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6710 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6711 | |
6712 | case M_COP0: | |
6713 | s = "c0"; | |
6714 | goto copz; | |
6715 | case M_COP1: | |
6716 | s = "c1"; | |
6717 | goto copz; | |
6718 | case M_COP2: | |
6719 | s = "c2"; | |
6720 | goto copz; | |
6721 | case M_COP3: | |
6722 | s = "c3"; | |
6723 | copz: | |
6724 | /* For now we just do C (same as Cz). The parameter will be | |
6725 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6726 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6727 | break; |
252b5132 | 6728 | |
ea1fb5dc | 6729 | case M_MOVE: |
67c0d1eb | 6730 | move_register (dreg, sreg); |
8fc2e39e | 6731 | break; |
ea1fb5dc | 6732 | |
252b5132 RH |
6733 | #ifdef LOSING_COMPILER |
6734 | default: | |
6735 | /* Try and see if this is a new itbl instruction. | |
6736 | This code builds table entries out of the macros in mip_opcodes. | |
6737 | FIXME: For now we just assemble the expression and pass it's | |
6738 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6739 | We may want to have the assembler assemble this value, |
252b5132 RH |
6740 | so that we gain the assembler's knowledge of delay slots, |
6741 | symbols, etc. | |
6742 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6743 | if (itbl_have_entries |
252b5132 | 6744 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6745 | { |
252b5132 RH |
6746 | s = ip->insn_mo->name; |
6747 | s2 = "cop3"; | |
6748 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6749 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6750 | break; |
beae10d5 | 6751 | } |
252b5132 | 6752 | macro2 (ip); |
8fc2e39e | 6753 | break; |
252b5132 | 6754 | } |
8fc2e39e TS |
6755 | if (mips_opts.noat && used_at) |
6756 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6757 | } |
bdaaa2e1 | 6758 | |
252b5132 | 6759 | static void |
17a2f251 | 6760 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6761 | { |
6762 | register int treg, sreg, dreg, breg; | |
6763 | int tempreg; | |
6764 | int mask; | |
252b5132 RH |
6765 | int used_at; |
6766 | expressionS expr1; | |
6767 | const char *s; | |
6768 | const char *s2; | |
6769 | const char *fmt; | |
6770 | int likely = 0; | |
6771 | int dbl = 0; | |
6772 | int coproc = 0; | |
6773 | int lr = 0; | |
6774 | int imm = 0; | |
6775 | int off; | |
6776 | offsetT maxnum; | |
6777 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6778 | |
252b5132 RH |
6779 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6780 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6781 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6782 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6783 | |
252b5132 RH |
6784 | expr1.X_op = O_constant; |
6785 | expr1.X_op_symbol = NULL; | |
6786 | expr1.X_add_symbol = NULL; | |
6787 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6788 | |
252b5132 RH |
6789 | switch (mask) |
6790 | { | |
6791 | #endif /* LOSING_COMPILER */ | |
6792 | ||
6793 | case M_DMUL: | |
6794 | dbl = 1; | |
6795 | case M_MUL: | |
67c0d1eb RS |
6796 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6797 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6798 | break; |
252b5132 RH |
6799 | |
6800 | case M_DMUL_I: | |
6801 | dbl = 1; | |
6802 | case M_MUL_I: | |
6803 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6804 | not trying to be that fancy. GCC should do this for us | |
6805 | anyway. */ | |
8fc2e39e | 6806 | used_at = 1; |
67c0d1eb RS |
6807 | load_register (AT, &imm_expr, dbl); |
6808 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6809 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6810 | break; |
6811 | ||
6812 | case M_DMULO_I: | |
6813 | dbl = 1; | |
6814 | case M_MULO_I: | |
6815 | imm = 1; | |
6816 | goto do_mulo; | |
6817 | ||
6818 | case M_DMULO: | |
6819 | dbl = 1; | |
6820 | case M_MULO: | |
6821 | do_mulo: | |
b34976b6 | 6822 | mips_emit_delays (TRUE); |
252b5132 RH |
6823 | ++mips_opts.noreorder; |
6824 | mips_any_noreorder = 1; | |
8fc2e39e | 6825 | used_at = 1; |
252b5132 | 6826 | if (imm) |
67c0d1eb RS |
6827 | load_register (AT, &imm_expr, dbl); |
6828 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6829 | macro_build (NULL, "mflo", "d", dreg); | |
6830 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6831 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6832 | if (mips_trap) |
67c0d1eb | 6833 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6834 | else |
6835 | { | |
6836 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6837 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6838 | macro_build (NULL, "nop", "", 0); | |
6839 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6840 | } |
6841 | --mips_opts.noreorder; | |
67c0d1eb | 6842 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6843 | break; |
6844 | ||
6845 | case M_DMULOU_I: | |
6846 | dbl = 1; | |
6847 | case M_MULOU_I: | |
6848 | imm = 1; | |
6849 | goto do_mulou; | |
6850 | ||
6851 | case M_DMULOU: | |
6852 | dbl = 1; | |
6853 | case M_MULOU: | |
6854 | do_mulou: | |
b34976b6 | 6855 | mips_emit_delays (TRUE); |
252b5132 RH |
6856 | ++mips_opts.noreorder; |
6857 | mips_any_noreorder = 1; | |
8fc2e39e | 6858 | used_at = 1; |
252b5132 | 6859 | if (imm) |
67c0d1eb RS |
6860 | load_register (AT, &imm_expr, dbl); |
6861 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6862 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6863 | macro_build (NULL, "mfhi", "d", AT); |
6864 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6865 | if (mips_trap) |
67c0d1eb | 6866 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6867 | else |
6868 | { | |
6869 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6870 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6871 | macro_build (NULL, "nop", "", 0); | |
6872 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6873 | } |
6874 | --mips_opts.noreorder; | |
6875 | break; | |
6876 | ||
771c7ce4 | 6877 | case M_DROL: |
fef14a42 | 6878 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6879 | { |
6880 | if (dreg == sreg) | |
6881 | { | |
6882 | tempreg = AT; | |
6883 | used_at = 1; | |
6884 | } | |
6885 | else | |
6886 | { | |
6887 | tempreg = dreg; | |
82dd0097 | 6888 | } |
67c0d1eb RS |
6889 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6890 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6891 | break; |
82dd0097 | 6892 | } |
8fc2e39e | 6893 | used_at = 1; |
67c0d1eb RS |
6894 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6895 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6896 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6897 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6898 | break; |
6899 | ||
252b5132 | 6900 | case M_ROL: |
fef14a42 | 6901 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6902 | { |
6903 | if (dreg == sreg) | |
6904 | { | |
6905 | tempreg = AT; | |
6906 | used_at = 1; | |
6907 | } | |
6908 | else | |
6909 | { | |
6910 | tempreg = dreg; | |
82dd0097 | 6911 | } |
67c0d1eb RS |
6912 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6913 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6914 | break; |
82dd0097 | 6915 | } |
8fc2e39e | 6916 | used_at = 1; |
67c0d1eb RS |
6917 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6918 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6919 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6920 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6921 | break; |
6922 | ||
771c7ce4 TS |
6923 | case M_DROL_I: |
6924 | { | |
6925 | unsigned int rot; | |
82dd0097 | 6926 | char *l, *r; |
771c7ce4 TS |
6927 | |
6928 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6929 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6930 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6931 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6932 | { |
6933 | rot = (64 - rot) & 0x3f; | |
6934 | if (rot >= 32) | |
67c0d1eb | 6935 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6936 | else |
67c0d1eb | 6937 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6938 | break; |
60b63b72 | 6939 | } |
483fc7cd | 6940 | if (rot == 0) |
483fc7cd | 6941 | { |
67c0d1eb | 6942 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6943 | break; |
483fc7cd | 6944 | } |
82dd0097 CD |
6945 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6946 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6947 | rot &= 0x1f; | |
8fc2e39e | 6948 | used_at = 1; |
67c0d1eb RS |
6949 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6950 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6951 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6952 | } |
6953 | break; | |
6954 | ||
252b5132 | 6955 | case M_ROL_I: |
771c7ce4 TS |
6956 | { |
6957 | unsigned int rot; | |
6958 | ||
6959 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6960 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6961 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6962 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6963 | { |
67c0d1eb | 6964 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6965 | break; |
60b63b72 | 6966 | } |
483fc7cd | 6967 | if (rot == 0) |
483fc7cd | 6968 | { |
67c0d1eb | 6969 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6970 | break; |
483fc7cd | 6971 | } |
8fc2e39e | 6972 | used_at = 1; |
67c0d1eb RS |
6973 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6974 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6975 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6976 | } |
6977 | break; | |
6978 | ||
6979 | case M_DROR: | |
fef14a42 | 6980 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6981 | { |
67c0d1eb | 6982 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6983 | break; |
82dd0097 | 6984 | } |
8fc2e39e | 6985 | used_at = 1; |
67c0d1eb RS |
6986 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6987 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6988 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6989 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6990 | break; |
6991 | ||
6992 | case M_ROR: | |
fef14a42 | 6993 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6994 | { |
67c0d1eb | 6995 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6996 | break; |
82dd0097 | 6997 | } |
8fc2e39e | 6998 | used_at = 1; |
67c0d1eb RS |
6999 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7000 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7001 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7002 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7003 | break; |
7004 | ||
771c7ce4 TS |
7005 | case M_DROR_I: |
7006 | { | |
7007 | unsigned int rot; | |
82dd0097 | 7008 | char *l, *r; |
771c7ce4 TS |
7009 | |
7010 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7011 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7012 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7013 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7014 | { |
7015 | if (rot >= 32) | |
67c0d1eb | 7016 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7017 | else |
67c0d1eb | 7018 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7019 | break; |
82dd0097 | 7020 | } |
483fc7cd | 7021 | if (rot == 0) |
483fc7cd | 7022 | { |
67c0d1eb | 7023 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7024 | break; |
483fc7cd | 7025 | } |
82dd0097 CD |
7026 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7027 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7028 | rot &= 0x1f; | |
8fc2e39e | 7029 | used_at = 1; |
67c0d1eb RS |
7030 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7031 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7032 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7033 | } |
7034 | break; | |
7035 | ||
252b5132 | 7036 | case M_ROR_I: |
771c7ce4 TS |
7037 | { |
7038 | unsigned int rot; | |
7039 | ||
7040 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7041 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7042 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7043 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7044 | { |
67c0d1eb | 7045 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7046 | break; |
82dd0097 | 7047 | } |
483fc7cd | 7048 | if (rot == 0) |
483fc7cd | 7049 | { |
67c0d1eb | 7050 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7051 | break; |
483fc7cd | 7052 | } |
8fc2e39e | 7053 | used_at = 1; |
67c0d1eb RS |
7054 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7055 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7056 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7057 | } |
252b5132 RH |
7058 | break; |
7059 | ||
7060 | case M_S_DOB: | |
fef14a42 | 7061 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7062 | { |
7063 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7064 | break; |
252b5132 | 7065 | } |
e7af610e | 7066 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7067 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7068 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7069 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7070 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7071 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7072 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7073 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7074 | break; |
252b5132 RH |
7075 | |
7076 | case M_SEQ: | |
7077 | if (sreg == 0) | |
67c0d1eb | 7078 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7079 | else if (treg == 0) |
67c0d1eb | 7080 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7081 | else |
7082 | { | |
67c0d1eb RS |
7083 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7084 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7085 | } |
8fc2e39e | 7086 | break; |
252b5132 RH |
7087 | |
7088 | case M_SEQ_I: | |
7089 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7090 | { | |
67c0d1eb | 7091 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7092 | break; |
252b5132 RH |
7093 | } |
7094 | if (sreg == 0) | |
7095 | { | |
7096 | as_warn (_("Instruction %s: result is always false"), | |
7097 | ip->insn_mo->name); | |
67c0d1eb | 7098 | move_register (dreg, 0); |
8fc2e39e | 7099 | break; |
252b5132 RH |
7100 | } |
7101 | if (imm_expr.X_op == O_constant | |
7102 | && imm_expr.X_add_number >= 0 | |
7103 | && imm_expr.X_add_number < 0x10000) | |
7104 | { | |
67c0d1eb | 7105 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7106 | } |
7107 | else if (imm_expr.X_op == O_constant | |
7108 | && imm_expr.X_add_number > -0x8000 | |
7109 | && imm_expr.X_add_number < 0) | |
7110 | { | |
7111 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7112 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7113 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7114 | } |
7115 | else | |
7116 | { | |
67c0d1eb RS |
7117 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7118 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7119 | used_at = 1; |
7120 | } | |
67c0d1eb | 7121 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7122 | break; |
252b5132 RH |
7123 | |
7124 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7125 | s = "slt"; | |
7126 | goto sge; | |
7127 | case M_SGEU: | |
7128 | s = "sltu"; | |
7129 | sge: | |
67c0d1eb RS |
7130 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7131 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7132 | break; |
252b5132 RH |
7133 | |
7134 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7135 | case M_SGEU_I: | |
7136 | if (imm_expr.X_op == O_constant | |
7137 | && imm_expr.X_add_number >= -0x8000 | |
7138 | && imm_expr.X_add_number < 0x8000) | |
7139 | { | |
67c0d1eb RS |
7140 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7141 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7142 | } |
7143 | else | |
7144 | { | |
67c0d1eb RS |
7145 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7146 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7147 | dreg, sreg, AT); | |
252b5132 RH |
7148 | used_at = 1; |
7149 | } | |
67c0d1eb | 7150 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7151 | break; |
252b5132 RH |
7152 | |
7153 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7154 | s = "slt"; | |
7155 | goto sgt; | |
7156 | case M_SGTU: | |
7157 | s = "sltu"; | |
7158 | sgt: | |
67c0d1eb | 7159 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7160 | break; |
252b5132 RH |
7161 | |
7162 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7163 | s = "slt"; | |
7164 | goto sgti; | |
7165 | case M_SGTU_I: | |
7166 | s = "sltu"; | |
7167 | sgti: | |
8fc2e39e | 7168 | used_at = 1; |
67c0d1eb RS |
7169 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7170 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7171 | break; |
7172 | ||
2396cfb9 | 7173 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7174 | s = "slt"; |
7175 | goto sle; | |
7176 | case M_SLEU: | |
7177 | s = "sltu"; | |
7178 | sle: | |
67c0d1eb RS |
7179 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7180 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7181 | break; |
252b5132 | 7182 | |
2396cfb9 | 7183 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7184 | s = "slt"; |
7185 | goto slei; | |
7186 | case M_SLEU_I: | |
7187 | s = "sltu"; | |
7188 | slei: | |
8fc2e39e | 7189 | used_at = 1; |
67c0d1eb RS |
7190 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7191 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7192 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7193 | break; |
7194 | ||
7195 | case M_SLT_I: | |
7196 | if (imm_expr.X_op == O_constant | |
7197 | && imm_expr.X_add_number >= -0x8000 | |
7198 | && imm_expr.X_add_number < 0x8000) | |
7199 | { | |
67c0d1eb | 7200 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7201 | break; |
252b5132 | 7202 | } |
8fc2e39e | 7203 | used_at = 1; |
67c0d1eb RS |
7204 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7205 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7206 | break; |
7207 | ||
7208 | case M_SLTU_I: | |
7209 | if (imm_expr.X_op == O_constant | |
7210 | && imm_expr.X_add_number >= -0x8000 | |
7211 | && imm_expr.X_add_number < 0x8000) | |
7212 | { | |
67c0d1eb | 7213 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7214 | BFD_RELOC_LO16); |
8fc2e39e | 7215 | break; |
252b5132 | 7216 | } |
8fc2e39e | 7217 | used_at = 1; |
67c0d1eb RS |
7218 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7219 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7220 | break; |
7221 | ||
7222 | case M_SNE: | |
7223 | if (sreg == 0) | |
67c0d1eb | 7224 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7225 | else if (treg == 0) |
67c0d1eb | 7226 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7227 | else |
7228 | { | |
67c0d1eb RS |
7229 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7230 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7231 | } |
8fc2e39e | 7232 | break; |
252b5132 RH |
7233 | |
7234 | case M_SNE_I: | |
7235 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7236 | { | |
67c0d1eb | 7237 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7238 | break; |
252b5132 RH |
7239 | } |
7240 | if (sreg == 0) | |
7241 | { | |
7242 | as_warn (_("Instruction %s: result is always true"), | |
7243 | ip->insn_mo->name); | |
67c0d1eb RS |
7244 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7245 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7246 | break; |
252b5132 RH |
7247 | } |
7248 | if (imm_expr.X_op == O_constant | |
7249 | && imm_expr.X_add_number >= 0 | |
7250 | && imm_expr.X_add_number < 0x10000) | |
7251 | { | |
67c0d1eb | 7252 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7253 | } |
7254 | else if (imm_expr.X_op == O_constant | |
7255 | && imm_expr.X_add_number > -0x8000 | |
7256 | && imm_expr.X_add_number < 0) | |
7257 | { | |
7258 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7259 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7260 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7261 | } |
7262 | else | |
7263 | { | |
67c0d1eb RS |
7264 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7265 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7266 | used_at = 1; |
7267 | } | |
67c0d1eb | 7268 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7269 | break; |
252b5132 RH |
7270 | |
7271 | case M_DSUB_I: | |
7272 | dbl = 1; | |
7273 | case M_SUB_I: | |
7274 | if (imm_expr.X_op == O_constant | |
7275 | && imm_expr.X_add_number > -0x8000 | |
7276 | && imm_expr.X_add_number <= 0x8000) | |
7277 | { | |
7278 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7279 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7280 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7281 | break; |
252b5132 | 7282 | } |
8fc2e39e | 7283 | used_at = 1; |
67c0d1eb RS |
7284 | load_register (AT, &imm_expr, dbl); |
7285 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7286 | break; |
7287 | ||
7288 | case M_DSUBU_I: | |
7289 | dbl = 1; | |
7290 | case M_SUBU_I: | |
7291 | if (imm_expr.X_op == O_constant | |
7292 | && imm_expr.X_add_number > -0x8000 | |
7293 | && imm_expr.X_add_number <= 0x8000) | |
7294 | { | |
7295 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7296 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7297 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7298 | break; |
252b5132 | 7299 | } |
8fc2e39e | 7300 | used_at = 1; |
67c0d1eb RS |
7301 | load_register (AT, &imm_expr, dbl); |
7302 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7303 | break; |
7304 | ||
7305 | case M_TEQ_I: | |
7306 | s = "teq"; | |
7307 | goto trap; | |
7308 | case M_TGE_I: | |
7309 | s = "tge"; | |
7310 | goto trap; | |
7311 | case M_TGEU_I: | |
7312 | s = "tgeu"; | |
7313 | goto trap; | |
7314 | case M_TLT_I: | |
7315 | s = "tlt"; | |
7316 | goto trap; | |
7317 | case M_TLTU_I: | |
7318 | s = "tltu"; | |
7319 | goto trap; | |
7320 | case M_TNE_I: | |
7321 | s = "tne"; | |
7322 | trap: | |
8fc2e39e | 7323 | used_at = 1; |
67c0d1eb RS |
7324 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7325 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7326 | break; |
7327 | ||
252b5132 | 7328 | case M_TRUNCWS: |
43841e91 | 7329 | case M_TRUNCWD: |
e7af610e | 7330 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7331 | used_at = 1; |
252b5132 RH |
7332 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7333 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7334 | ||
7335 | /* | |
7336 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7337 | * or is there a reason for it? | |
7338 | */ | |
b34976b6 | 7339 | mips_emit_delays (TRUE); |
252b5132 RH |
7340 | ++mips_opts.noreorder; |
7341 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7342 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7343 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7344 | macro_build (NULL, "nop", ""); | |
252b5132 | 7345 | expr1.X_add_number = 3; |
67c0d1eb | 7346 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7347 | expr1.X_add_number = 2; |
67c0d1eb RS |
7348 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7349 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7350 | macro_build (NULL, "nop", ""); | |
7351 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7352 | dreg, sreg); | |
7353 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7354 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7355 | --mips_opts.noreorder; |
7356 | break; | |
7357 | ||
7358 | case M_ULH: | |
7359 | s = "lb"; | |
7360 | goto ulh; | |
7361 | case M_ULHU: | |
7362 | s = "lbu"; | |
7363 | ulh: | |
8fc2e39e | 7364 | used_at = 1; |
252b5132 RH |
7365 | if (offset_expr.X_add_number >= 0x7fff) |
7366 | as_bad (_("operand overflow")); | |
252b5132 | 7367 | if (! target_big_endian) |
f9419b05 | 7368 | ++offset_expr.X_add_number; |
67c0d1eb | 7369 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7370 | if (! target_big_endian) |
f9419b05 | 7371 | --offset_expr.X_add_number; |
252b5132 | 7372 | else |
f9419b05 | 7373 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7374 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7375 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7376 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7377 | break; |
7378 | ||
7379 | case M_ULD: | |
7380 | s = "ldl"; | |
7381 | s2 = "ldr"; | |
7382 | off = 7; | |
7383 | goto ulw; | |
7384 | case M_ULW: | |
7385 | s = "lwl"; | |
7386 | s2 = "lwr"; | |
7387 | off = 3; | |
7388 | ulw: | |
7389 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7390 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7391 | if (treg != breg) |
7392 | tempreg = treg; | |
7393 | else | |
8fc2e39e TS |
7394 | { |
7395 | used_at = 1; | |
7396 | tempreg = AT; | |
7397 | } | |
252b5132 RH |
7398 | if (! target_big_endian) |
7399 | offset_expr.X_add_number += off; | |
67c0d1eb | 7400 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7401 | if (! target_big_endian) |
7402 | offset_expr.X_add_number -= off; | |
7403 | else | |
7404 | offset_expr.X_add_number += off; | |
67c0d1eb | 7405 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7406 | |
7407 | /* If necessary, move the result in tempreg the final destination. */ | |
7408 | if (treg == tempreg) | |
8fc2e39e | 7409 | break; |
af22f5b2 | 7410 | /* Protect second load's delay slot. */ |
017315e4 | 7411 | load_delay_nop (); |
67c0d1eb | 7412 | move_register (treg, tempreg); |
af22f5b2 | 7413 | break; |
252b5132 RH |
7414 | |
7415 | case M_ULD_A: | |
7416 | s = "ldl"; | |
7417 | s2 = "ldr"; | |
7418 | off = 7; | |
7419 | goto ulwa; | |
7420 | case M_ULW_A: | |
7421 | s = "lwl"; | |
7422 | s2 = "lwr"; | |
7423 | off = 3; | |
7424 | ulwa: | |
d6bc6245 | 7425 | used_at = 1; |
67c0d1eb | 7426 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7427 | if (breg != 0) |
67c0d1eb | 7428 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7429 | if (! target_big_endian) |
7430 | expr1.X_add_number = off; | |
7431 | else | |
7432 | expr1.X_add_number = 0; | |
67c0d1eb | 7433 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7434 | if (! target_big_endian) |
7435 | expr1.X_add_number = 0; | |
7436 | else | |
7437 | expr1.X_add_number = off; | |
67c0d1eb | 7438 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7439 | break; |
7440 | ||
7441 | case M_ULH_A: | |
7442 | case M_ULHU_A: | |
d6bc6245 | 7443 | used_at = 1; |
67c0d1eb | 7444 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7445 | if (breg != 0) |
67c0d1eb | 7446 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7447 | if (target_big_endian) |
7448 | expr1.X_add_number = 0; | |
67c0d1eb | 7449 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7450 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7451 | if (target_big_endian) |
7452 | expr1.X_add_number = 1; | |
7453 | else | |
7454 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7455 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7456 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7457 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7458 | break; |
7459 | ||
7460 | case M_USH: | |
8fc2e39e | 7461 | used_at = 1; |
252b5132 RH |
7462 | if (offset_expr.X_add_number >= 0x7fff) |
7463 | as_bad (_("operand overflow")); | |
7464 | if (target_big_endian) | |
f9419b05 | 7465 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7466 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7467 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7468 | if (target_big_endian) |
f9419b05 | 7469 | --offset_expr.X_add_number; |
252b5132 | 7470 | else |
f9419b05 | 7471 | ++offset_expr.X_add_number; |
67c0d1eb | 7472 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7473 | break; |
7474 | ||
7475 | case M_USD: | |
7476 | s = "sdl"; | |
7477 | s2 = "sdr"; | |
7478 | off = 7; | |
7479 | goto usw; | |
7480 | case M_USW: | |
7481 | s = "swl"; | |
7482 | s2 = "swr"; | |
7483 | off = 3; | |
7484 | usw: | |
7485 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7486 | as_bad (_("operand overflow")); | |
7487 | if (! target_big_endian) | |
7488 | offset_expr.X_add_number += off; | |
67c0d1eb | 7489 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7490 | if (! target_big_endian) |
7491 | offset_expr.X_add_number -= off; | |
7492 | else | |
7493 | offset_expr.X_add_number += off; | |
67c0d1eb | 7494 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7495 | break; |
252b5132 RH |
7496 | |
7497 | case M_USD_A: | |
7498 | s = "sdl"; | |
7499 | s2 = "sdr"; | |
7500 | off = 7; | |
7501 | goto uswa; | |
7502 | case M_USW_A: | |
7503 | s = "swl"; | |
7504 | s2 = "swr"; | |
7505 | off = 3; | |
7506 | uswa: | |
d6bc6245 | 7507 | used_at = 1; |
67c0d1eb | 7508 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7509 | if (breg != 0) |
67c0d1eb | 7510 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7511 | if (! target_big_endian) |
7512 | expr1.X_add_number = off; | |
7513 | else | |
7514 | expr1.X_add_number = 0; | |
67c0d1eb | 7515 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7516 | if (! target_big_endian) |
7517 | expr1.X_add_number = 0; | |
7518 | else | |
7519 | expr1.X_add_number = off; | |
67c0d1eb | 7520 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7521 | break; |
7522 | ||
7523 | case M_USH_A: | |
d6bc6245 | 7524 | used_at = 1; |
67c0d1eb | 7525 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7526 | if (breg != 0) |
67c0d1eb | 7527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7528 | if (! target_big_endian) |
7529 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7530 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7531 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7532 | if (! target_big_endian) |
7533 | expr1.X_add_number = 1; | |
7534 | else | |
7535 | expr1.X_add_number = 0; | |
67c0d1eb | 7536 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7537 | if (! target_big_endian) |
7538 | expr1.X_add_number = 0; | |
7539 | else | |
7540 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7541 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7542 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7543 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7544 | break; |
7545 | ||
7546 | default: | |
7547 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7548 | are added dynamically. */ |
252b5132 RH |
7549 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7550 | break; | |
7551 | } | |
8fc2e39e TS |
7552 | if (mips_opts.noat && used_at) |
7553 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7554 | } |
7555 | ||
7556 | /* Implement macros in mips16 mode. */ | |
7557 | ||
7558 | static void | |
17a2f251 | 7559 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7560 | { |
7561 | int mask; | |
7562 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7563 | expressionS expr1; |
7564 | int dbl; | |
7565 | const char *s, *s2, *s3; | |
7566 | ||
7567 | mask = ip->insn_mo->mask; | |
7568 | ||
bf12938e RS |
7569 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7570 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7571 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7572 | |
252b5132 RH |
7573 | expr1.X_op = O_constant; |
7574 | expr1.X_op_symbol = NULL; | |
7575 | expr1.X_add_symbol = NULL; | |
7576 | expr1.X_add_number = 1; | |
7577 | ||
7578 | dbl = 0; | |
7579 | ||
7580 | switch (mask) | |
7581 | { | |
7582 | default: | |
7583 | internalError (); | |
7584 | ||
7585 | case M_DDIV_3: | |
7586 | dbl = 1; | |
7587 | case M_DIV_3: | |
7588 | s = "mflo"; | |
7589 | goto do_div3; | |
7590 | case M_DREM_3: | |
7591 | dbl = 1; | |
7592 | case M_REM_3: | |
7593 | s = "mfhi"; | |
7594 | do_div3: | |
b34976b6 | 7595 | mips_emit_delays (TRUE); |
252b5132 RH |
7596 | ++mips_opts.noreorder; |
7597 | mips_any_noreorder = 1; | |
67c0d1eb | 7598 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7599 | expr1.X_add_number = 2; |
67c0d1eb RS |
7600 | macro_build (&expr1, "bnez", "x,p", yreg); |
7601 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7602 | |
252b5132 RH |
7603 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7604 | since that causes an overflow. We should do that as well, | |
7605 | but I don't see how to do the comparisons without a temporary | |
7606 | register. */ | |
7607 | --mips_opts.noreorder; | |
67c0d1eb | 7608 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7609 | break; |
7610 | ||
7611 | case M_DIVU_3: | |
7612 | s = "divu"; | |
7613 | s2 = "mflo"; | |
7614 | goto do_divu3; | |
7615 | case M_REMU_3: | |
7616 | s = "divu"; | |
7617 | s2 = "mfhi"; | |
7618 | goto do_divu3; | |
7619 | case M_DDIVU_3: | |
7620 | s = "ddivu"; | |
7621 | s2 = "mflo"; | |
7622 | goto do_divu3; | |
7623 | case M_DREMU_3: | |
7624 | s = "ddivu"; | |
7625 | s2 = "mfhi"; | |
7626 | do_divu3: | |
b34976b6 | 7627 | mips_emit_delays (TRUE); |
252b5132 RH |
7628 | ++mips_opts.noreorder; |
7629 | mips_any_noreorder = 1; | |
67c0d1eb | 7630 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7631 | expr1.X_add_number = 2; |
67c0d1eb RS |
7632 | macro_build (&expr1, "bnez", "x,p", yreg); |
7633 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7634 | --mips_opts.noreorder; |
67c0d1eb | 7635 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7636 | break; |
7637 | ||
7638 | case M_DMUL: | |
7639 | dbl = 1; | |
7640 | case M_MUL: | |
67c0d1eb RS |
7641 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7642 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7643 | break; |
252b5132 RH |
7644 | |
7645 | case M_DSUBU_I: | |
7646 | dbl = 1; | |
7647 | goto do_subu; | |
7648 | case M_SUBU_I: | |
7649 | do_subu: | |
7650 | if (imm_expr.X_op != O_constant) | |
7651 | as_bad (_("Unsupported large constant")); | |
7652 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7653 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7654 | break; |
7655 | ||
7656 | case M_SUBU_I_2: | |
7657 | if (imm_expr.X_op != O_constant) | |
7658 | as_bad (_("Unsupported large constant")); | |
7659 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7660 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7661 | break; |
7662 | ||
7663 | case M_DSUBU_I_2: | |
7664 | if (imm_expr.X_op != O_constant) | |
7665 | as_bad (_("Unsupported large constant")); | |
7666 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7667 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7668 | break; |
7669 | ||
7670 | case M_BEQ: | |
7671 | s = "cmp"; | |
7672 | s2 = "bteqz"; | |
7673 | goto do_branch; | |
7674 | case M_BNE: | |
7675 | s = "cmp"; | |
7676 | s2 = "btnez"; | |
7677 | goto do_branch; | |
7678 | case M_BLT: | |
7679 | s = "slt"; | |
7680 | s2 = "btnez"; | |
7681 | goto do_branch; | |
7682 | case M_BLTU: | |
7683 | s = "sltu"; | |
7684 | s2 = "btnez"; | |
7685 | goto do_branch; | |
7686 | case M_BLE: | |
7687 | s = "slt"; | |
7688 | s2 = "bteqz"; | |
7689 | goto do_reverse_branch; | |
7690 | case M_BLEU: | |
7691 | s = "sltu"; | |
7692 | s2 = "bteqz"; | |
7693 | goto do_reverse_branch; | |
7694 | case M_BGE: | |
7695 | s = "slt"; | |
7696 | s2 = "bteqz"; | |
7697 | goto do_branch; | |
7698 | case M_BGEU: | |
7699 | s = "sltu"; | |
7700 | s2 = "bteqz"; | |
7701 | goto do_branch; | |
7702 | case M_BGT: | |
7703 | s = "slt"; | |
7704 | s2 = "btnez"; | |
7705 | goto do_reverse_branch; | |
7706 | case M_BGTU: | |
7707 | s = "sltu"; | |
7708 | s2 = "btnez"; | |
7709 | ||
7710 | do_reverse_branch: | |
7711 | tmp = xreg; | |
7712 | xreg = yreg; | |
7713 | yreg = tmp; | |
7714 | ||
7715 | do_branch: | |
67c0d1eb RS |
7716 | macro_build (NULL, s, "x,y", xreg, yreg); |
7717 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7718 | break; |
7719 | ||
7720 | case M_BEQ_I: | |
7721 | s = "cmpi"; | |
7722 | s2 = "bteqz"; | |
7723 | s3 = "x,U"; | |
7724 | goto do_branch_i; | |
7725 | case M_BNE_I: | |
7726 | s = "cmpi"; | |
7727 | s2 = "btnez"; | |
7728 | s3 = "x,U"; | |
7729 | goto do_branch_i; | |
7730 | case M_BLT_I: | |
7731 | s = "slti"; | |
7732 | s2 = "btnez"; | |
7733 | s3 = "x,8"; | |
7734 | goto do_branch_i; | |
7735 | case M_BLTU_I: | |
7736 | s = "sltiu"; | |
7737 | s2 = "btnez"; | |
7738 | s3 = "x,8"; | |
7739 | goto do_branch_i; | |
7740 | case M_BLE_I: | |
7741 | s = "slti"; | |
7742 | s2 = "btnez"; | |
7743 | s3 = "x,8"; | |
7744 | goto do_addone_branch_i; | |
7745 | case M_BLEU_I: | |
7746 | s = "sltiu"; | |
7747 | s2 = "btnez"; | |
7748 | s3 = "x,8"; | |
7749 | goto do_addone_branch_i; | |
7750 | case M_BGE_I: | |
7751 | s = "slti"; | |
7752 | s2 = "bteqz"; | |
7753 | s3 = "x,8"; | |
7754 | goto do_branch_i; | |
7755 | case M_BGEU_I: | |
7756 | s = "sltiu"; | |
7757 | s2 = "bteqz"; | |
7758 | s3 = "x,8"; | |
7759 | goto do_branch_i; | |
7760 | case M_BGT_I: | |
7761 | s = "slti"; | |
7762 | s2 = "bteqz"; | |
7763 | s3 = "x,8"; | |
7764 | goto do_addone_branch_i; | |
7765 | case M_BGTU_I: | |
7766 | s = "sltiu"; | |
7767 | s2 = "bteqz"; | |
7768 | s3 = "x,8"; | |
7769 | ||
7770 | do_addone_branch_i: | |
7771 | if (imm_expr.X_op != O_constant) | |
7772 | as_bad (_("Unsupported large constant")); | |
7773 | ++imm_expr.X_add_number; | |
7774 | ||
7775 | do_branch_i: | |
67c0d1eb RS |
7776 | macro_build (&imm_expr, s, s3, xreg); |
7777 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7778 | break; |
7779 | ||
7780 | case M_ABS: | |
7781 | expr1.X_add_number = 0; | |
67c0d1eb | 7782 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7783 | if (xreg != yreg) |
67c0d1eb | 7784 | move_register (xreg, yreg); |
252b5132 | 7785 | expr1.X_add_number = 2; |
67c0d1eb RS |
7786 | macro_build (&expr1, "bteqz", "p"); |
7787 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7788 | } |
7789 | } | |
7790 | ||
7791 | /* For consistency checking, verify that all bits are specified either | |
7792 | by the match/mask part of the instruction definition, or by the | |
7793 | operand list. */ | |
7794 | static int | |
17a2f251 | 7795 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7796 | { |
7797 | const char *p = opc->args; | |
7798 | char c; | |
7799 | unsigned long used_bits = opc->mask; | |
7800 | ||
7801 | if ((used_bits & opc->match) != opc->match) | |
7802 | { | |
7803 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7804 | opc->name, opc->args); | |
7805 | return 0; | |
7806 | } | |
7807 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7808 | while (*p) | |
7809 | switch (c = *p++) | |
7810 | { | |
7811 | case ',': break; | |
7812 | case '(': break; | |
7813 | case ')': break; | |
af7ee8bf CD |
7814 | case '+': |
7815 | switch (c = *p++) | |
7816 | { | |
7817 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7818 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7819 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7820 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7821 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7822 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7823 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7824 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7825 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7826 | case 'I': break; | |
af7ee8bf CD |
7827 | default: |
7828 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7829 | c, opc->name, opc->args); | |
7830 | return 0; | |
7831 | } | |
7832 | break; | |
252b5132 RH |
7833 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7834 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7835 | case 'A': break; | |
4372b673 | 7836 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7837 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7838 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7839 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7840 | case 'F': break; | |
7841 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7842 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7843 | case 'I': break; |
e972090a | 7844 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7845 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7846 | case 'L': break; |
7847 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7848 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7849 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7850 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7851 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7852 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7853 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7854 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7855 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7856 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7857 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7858 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7859 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7860 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7861 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7862 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7863 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7864 | case 'f': break; | |
7865 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7866 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7867 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7868 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7869 | case 'l': break; | |
7870 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7871 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7872 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7873 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7874 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7875 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7876 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7877 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7878 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7879 | case 'x': break; | |
7880 | case 'z': break; | |
7881 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7882 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7883 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7884 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7885 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7886 | case '[': break; | |
7887 | case ']': break; | |
252b5132 RH |
7888 | default: |
7889 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7890 | c, opc->name, opc->args); | |
7891 | return 0; | |
7892 | } | |
7893 | #undef USE_BITS | |
7894 | if (used_bits != 0xffffffff) | |
7895 | { | |
7896 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7897 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7898 | return 0; | |
7899 | } | |
7900 | return 1; | |
7901 | } | |
7902 | ||
7903 | /* This routine assembles an instruction into its binary format. As a | |
7904 | side effect, it sets one of the global variables imm_reloc or | |
7905 | offset_reloc to the type of relocation to do if one of the operands | |
7906 | is an address expression. */ | |
7907 | ||
7908 | static void | |
17a2f251 | 7909 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7910 | { |
7911 | char *s; | |
7912 | const char *args; | |
43841e91 | 7913 | char c = 0; |
252b5132 RH |
7914 | struct mips_opcode *insn; |
7915 | char *argsStart; | |
7916 | unsigned int regno; | |
7917 | unsigned int lastregno = 0; | |
af7ee8bf | 7918 | unsigned int lastpos = 0; |
071742cf | 7919 | unsigned int limlo, limhi; |
252b5132 RH |
7920 | char *s_reset; |
7921 | char save_c = 0; | |
252b5132 RH |
7922 | |
7923 | insn_error = NULL; | |
7924 | ||
7925 | /* If the instruction contains a '.', we first try to match an instruction | |
7926 | including the '.'. Then we try again without the '.'. */ | |
7927 | insn = NULL; | |
3882b010 | 7928 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7929 | continue; |
7930 | ||
7931 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7932 | the call to hash_find. Save the character we replaced just in case we | |
7933 | have to re-parse the instruction. */ | |
3882b010 | 7934 | if (ISSPACE (*s)) |
252b5132 RH |
7935 | { |
7936 | save_c = *s; | |
7937 | *s++ = '\0'; | |
7938 | } | |
bdaaa2e1 | 7939 | |
252b5132 RH |
7940 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7941 | ||
7942 | /* If we didn't find the instruction in the opcode table, try again, but | |
7943 | this time with just the instruction up to, but not including the | |
7944 | first '.'. */ | |
7945 | if (insn == NULL) | |
7946 | { | |
bdaaa2e1 | 7947 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7948 | if (save_c) |
7949 | *(--s) = save_c; | |
7950 | ||
7951 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7952 | for (s = str; |
7953 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7954 | ++s) | |
252b5132 RH |
7955 | continue; |
7956 | ||
7957 | /* If we did not find a '.', then we can quit now. */ | |
7958 | if (*s != '.') | |
7959 | { | |
7960 | insn_error = "unrecognized opcode"; | |
7961 | return; | |
7962 | } | |
7963 | ||
7964 | /* Lookup the instruction in the hash table. */ | |
7965 | *s++ = '\0'; | |
7966 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7967 | { | |
7968 | insn_error = "unrecognized opcode"; | |
7969 | return; | |
7970 | } | |
252b5132 RH |
7971 | } |
7972 | ||
7973 | argsStart = s; | |
7974 | for (;;) | |
7975 | { | |
b34976b6 | 7976 | bfd_boolean ok; |
252b5132 RH |
7977 | |
7978 | assert (strcmp (insn->name, str) == 0); | |
7979 | ||
1f25f5d3 CD |
7980 | if (OPCODE_IS_MEMBER (insn, |
7981 | (mips_opts.isa | |
3396de36 | 7982 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7983 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7984 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7985 | mips_opts.arch)) |
b34976b6 | 7986 | ok = TRUE; |
bdaaa2e1 | 7987 | else |
b34976b6 | 7988 | ok = FALSE; |
bdaaa2e1 | 7989 | |
252b5132 RH |
7990 | if (insn->pinfo != INSN_MACRO) |
7991 | { | |
fef14a42 | 7992 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7993 | ok = FALSE; |
252b5132 RH |
7994 | } |
7995 | ||
7996 | if (! ok) | |
7997 | { | |
7998 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7999 | && strcmp (insn->name, insn[1].name) == 0) | |
8000 | { | |
8001 | ++insn; | |
8002 | continue; | |
8003 | } | |
252b5132 | 8004 | else |
beae10d5 | 8005 | { |
268f6bed L |
8006 | if (!insn_error) |
8007 | { | |
8008 | static char buf[100]; | |
fef14a42 TS |
8009 | sprintf (buf, |
8010 | _("opcode not supported on this processor: %s (%s)"), | |
8011 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8012 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8013 | insn_error = buf; |
8014 | } | |
8015 | if (save_c) | |
8016 | *(--s) = save_c; | |
2bd7f1f3 | 8017 | return; |
252b5132 | 8018 | } |
252b5132 RH |
8019 | } |
8020 | ||
8021 | ip->insn_mo = insn; | |
8022 | ip->insn_opcode = insn->match; | |
268f6bed | 8023 | insn_error = NULL; |
252b5132 RH |
8024 | for (args = insn->args;; ++args) |
8025 | { | |
deec1734 CD |
8026 | int is_mdmx; |
8027 | ||
ad8d3bb3 | 8028 | s += strspn (s, " \t"); |
deec1734 | 8029 | is_mdmx = 0; |
252b5132 RH |
8030 | switch (*args) |
8031 | { | |
8032 | case '\0': /* end of args */ | |
8033 | if (*s == '\0') | |
8034 | return; | |
8035 | break; | |
8036 | ||
8037 | case ',': | |
8038 | if (*s++ == *args) | |
8039 | continue; | |
8040 | s--; | |
8041 | switch (*++args) | |
8042 | { | |
8043 | case 'r': | |
8044 | case 'v': | |
bf12938e | 8045 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8046 | continue; |
8047 | ||
8048 | case 'w': | |
bf12938e | 8049 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8050 | continue; |
8051 | ||
252b5132 | 8052 | case 'W': |
bf12938e | 8053 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8054 | continue; |
8055 | ||
8056 | case 'V': | |
bf12938e | 8057 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8058 | continue; |
8059 | } | |
8060 | break; | |
8061 | ||
8062 | case '(': | |
8063 | /* Handle optional base register. | |
8064 | Either the base register is omitted or | |
bdaaa2e1 | 8065 | we must have a left paren. */ |
252b5132 RH |
8066 | /* This is dependent on the next operand specifier |
8067 | is a base register specification. */ | |
8068 | assert (args[1] == 'b' || args[1] == '5' | |
8069 | || args[1] == '-' || args[1] == '4'); | |
8070 | if (*s == '\0') | |
8071 | return; | |
8072 | ||
8073 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8074 | case '[': |
8075 | case ']': | |
252b5132 RH |
8076 | if (*s++ == *args) |
8077 | continue; | |
8078 | break; | |
8079 | ||
af7ee8bf CD |
8080 | case '+': /* Opcode extension character. */ |
8081 | switch (*++args) | |
8082 | { | |
071742cf CD |
8083 | case 'A': /* ins/ext position, becomes LSB. */ |
8084 | limlo = 0; | |
8085 | limhi = 31; | |
5f74bc13 CD |
8086 | goto do_lsb; |
8087 | case 'E': | |
8088 | limlo = 32; | |
8089 | limhi = 63; | |
8090 | goto do_lsb; | |
8091 | do_lsb: | |
071742cf CD |
8092 | my_getExpression (&imm_expr, s); |
8093 | check_absolute_expr (ip, &imm_expr); | |
8094 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8095 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8096 | { | |
8097 | as_bad (_("Improper position (%lu)"), | |
8098 | (unsigned long) imm_expr.X_add_number); | |
8099 | imm_expr.X_add_number = limlo; | |
8100 | } | |
8101 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8102 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8103 | imm_expr.X_op = O_absent; |
8104 | s = expr_end; | |
8105 | continue; | |
8106 | ||
8107 | case 'B': /* ins size, becomes MSB. */ | |
8108 | limlo = 1; | |
8109 | limhi = 32; | |
5f74bc13 CD |
8110 | goto do_msb; |
8111 | case 'F': | |
8112 | limlo = 33; | |
8113 | limhi = 64; | |
8114 | goto do_msb; | |
8115 | do_msb: | |
071742cf CD |
8116 | my_getExpression (&imm_expr, s); |
8117 | check_absolute_expr (ip, &imm_expr); | |
8118 | /* Check for negative input so that small negative numbers | |
8119 | will not succeed incorrectly. The checks against | |
8120 | (pos+size) transitively check "size" itself, | |
8121 | assuming that "pos" is reasonable. */ | |
8122 | if ((long) imm_expr.X_add_number < 0 | |
8123 | || ((unsigned long) imm_expr.X_add_number | |
8124 | + lastpos) < limlo | |
8125 | || ((unsigned long) imm_expr.X_add_number | |
8126 | + lastpos) > limhi) | |
8127 | { | |
8128 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8129 | (unsigned long) imm_expr.X_add_number, | |
8130 | (unsigned long) lastpos); | |
8131 | imm_expr.X_add_number = limlo - lastpos; | |
8132 | } | |
bf12938e RS |
8133 | INSERT_OPERAND (INSMSB, *ip, |
8134 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8135 | imm_expr.X_op = O_absent; |
8136 | s = expr_end; | |
8137 | continue; | |
8138 | ||
8139 | case 'C': /* ext size, becomes MSBD. */ | |
8140 | limlo = 1; | |
8141 | limhi = 32; | |
5f74bc13 CD |
8142 | goto do_msbd; |
8143 | case 'G': | |
8144 | limlo = 33; | |
8145 | limhi = 64; | |
8146 | goto do_msbd; | |
8147 | case 'H': | |
8148 | limlo = 33; | |
8149 | limhi = 64; | |
8150 | goto do_msbd; | |
8151 | do_msbd: | |
071742cf CD |
8152 | my_getExpression (&imm_expr, s); |
8153 | check_absolute_expr (ip, &imm_expr); | |
8154 | /* Check for negative input so that small negative numbers | |
8155 | will not succeed incorrectly. The checks against | |
8156 | (pos+size) transitively check "size" itself, | |
8157 | assuming that "pos" is reasonable. */ | |
8158 | if ((long) imm_expr.X_add_number < 0 | |
8159 | || ((unsigned long) imm_expr.X_add_number | |
8160 | + lastpos) < limlo | |
8161 | || ((unsigned long) imm_expr.X_add_number | |
8162 | + lastpos) > limhi) | |
8163 | { | |
8164 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8165 | (unsigned long) imm_expr.X_add_number, | |
8166 | (unsigned long) lastpos); | |
8167 | imm_expr.X_add_number = limlo - lastpos; | |
8168 | } | |
bf12938e | 8169 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8170 | imm_expr.X_op = O_absent; |
8171 | s = expr_end; | |
8172 | continue; | |
af7ee8bf | 8173 | |
bbcc0807 CD |
8174 | case 'D': |
8175 | /* +D is for disassembly only; never match. */ | |
8176 | break; | |
8177 | ||
5f74bc13 CD |
8178 | case 'I': |
8179 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8180 | my_getExpression (&imm2_expr, s); | |
8181 | if (imm2_expr.X_op != O_big | |
8182 | && imm2_expr.X_op != O_constant) | |
8183 | insn_error = _("absolute expression required"); | |
13757d0c | 8184 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8185 | s = expr_end; |
8186 | continue; | |
8187 | ||
af7ee8bf CD |
8188 | default: |
8189 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8190 | *args, insn->name, insn->args); | |
8191 | /* Further processing is fruitless. */ | |
8192 | return; | |
8193 | } | |
8194 | break; | |
8195 | ||
252b5132 RH |
8196 | case '<': /* must be at least one digit */ |
8197 | /* | |
8198 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8199 | * than 31 or less than 0, then the shift amount should be |
8200 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8201 | * We issue a warning and mask out all but the low 5 bits. |
8202 | */ | |
8203 | my_getExpression (&imm_expr, s); | |
8204 | check_absolute_expr (ip, &imm_expr); | |
8205 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8206 | as_warn (_("Improper shift amount (%lu)"), |
8207 | (unsigned long) imm_expr.X_add_number); | |
8208 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8209 | imm_expr.X_op = O_absent; |
8210 | s = expr_end; | |
8211 | continue; | |
8212 | ||
8213 | case '>': /* shift amount minus 32 */ | |
8214 | my_getExpression (&imm_expr, s); | |
8215 | check_absolute_expr (ip, &imm_expr); | |
8216 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8217 | || (unsigned long) imm_expr.X_add_number > 63) | |
8218 | break; | |
bf12938e | 8219 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8220 | imm_expr.X_op = O_absent; |
8221 | s = expr_end; | |
8222 | continue; | |
8223 | ||
252b5132 RH |
8224 | case 'k': /* cache code */ |
8225 | case 'h': /* prefx code */ | |
8226 | my_getExpression (&imm_expr, s); | |
8227 | check_absolute_expr (ip, &imm_expr); | |
8228 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8229 | as_warn (_("Invalid value for `%s' (%lu)"), |
8230 | ip->insn_mo->name, | |
8231 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8232 | if (*args == 'k') |
bf12938e | 8233 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8234 | else |
bf12938e | 8235 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8236 | imm_expr.X_op = O_absent; |
8237 | s = expr_end; | |
8238 | continue; | |
8239 | ||
8240 | case 'c': /* break code */ | |
8241 | my_getExpression (&imm_expr, s); | |
8242 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8243 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8244 | as_warn (_("Illegal break code (%lu)"), |
8245 | (unsigned long) imm_expr.X_add_number); | |
8246 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8247 | imm_expr.X_op = O_absent; |
8248 | s = expr_end; | |
8249 | continue; | |
8250 | ||
8251 | case 'q': /* lower break code */ | |
8252 | my_getExpression (&imm_expr, s); | |
8253 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8254 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8255 | as_warn (_("Illegal lower break code (%lu)"), |
8256 | (unsigned long) imm_expr.X_add_number); | |
8257 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8258 | imm_expr.X_op = O_absent; |
8259 | s = expr_end; | |
8260 | continue; | |
8261 | ||
4372b673 | 8262 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8263 | my_getExpression (&imm_expr, s); |
156c2f8b | 8264 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8265 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8266 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8267 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8268 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8269 | imm_expr.X_op = O_absent; |
8270 | s = expr_end; | |
8271 | continue; | |
8272 | ||
98d3f06f | 8273 | case 'C': /* Coprocessor code */ |
beae10d5 | 8274 | my_getExpression (&imm_expr, s); |
252b5132 | 8275 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8276 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8277 | { |
793b27f4 TS |
8278 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8279 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8280 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8281 | } |
beae10d5 KH |
8282 | ip->insn_opcode |= imm_expr.X_add_number; |
8283 | imm_expr.X_op = O_absent; | |
8284 | s = expr_end; | |
8285 | continue; | |
252b5132 | 8286 | |
4372b673 NC |
8287 | case 'J': /* 19-bit wait code. */ |
8288 | my_getExpression (&imm_expr, s); | |
8289 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8290 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8291 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8292 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8293 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8294 | imm_expr.X_op = O_absent; |
8295 | s = expr_end; | |
8296 | continue; | |
8297 | ||
252b5132 | 8298 | case 'P': /* Performance register */ |
beae10d5 | 8299 | my_getExpression (&imm_expr, s); |
252b5132 | 8300 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8301 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8302 | as_warn (_("Invalid performance register (%lu)"), |
8303 | (unsigned long) imm_expr.X_add_number); | |
8304 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8305 | imm_expr.X_op = O_absent; |
8306 | s = expr_end; | |
8307 | continue; | |
252b5132 RH |
8308 | |
8309 | case 'b': /* base register */ | |
8310 | case 'd': /* destination register */ | |
8311 | case 's': /* source register */ | |
8312 | case 't': /* target register */ | |
8313 | case 'r': /* both target and source */ | |
8314 | case 'v': /* both dest and source */ | |
8315 | case 'w': /* both dest and target */ | |
8316 | case 'E': /* coprocessor target register */ | |
8317 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8318 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8319 | case 'x': /* ignore register name */ |
8320 | case 'z': /* must be zero register */ | |
4372b673 | 8321 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8322 | s_reset = s; |
8323 | if (s[0] == '$') | |
8324 | { | |
8325 | ||
3882b010 | 8326 | if (ISDIGIT (s[1])) |
252b5132 RH |
8327 | { |
8328 | ++s; | |
8329 | regno = 0; | |
8330 | do | |
8331 | { | |
8332 | regno *= 10; | |
8333 | regno += *s - '0'; | |
8334 | ++s; | |
8335 | } | |
3882b010 | 8336 | while (ISDIGIT (*s)); |
252b5132 RH |
8337 | if (regno > 31) |
8338 | as_bad (_("Invalid register number (%d)"), regno); | |
8339 | } | |
af7ee8bf | 8340 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8341 | goto notreg; |
8342 | else | |
8343 | { | |
76db943d TS |
8344 | if (s[1] == 'r' && s[2] == 'a') |
8345 | { | |
8346 | s += 3; | |
8347 | regno = RA; | |
8348 | } | |
8349 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8350 | { |
8351 | s += 3; | |
8352 | regno = FP; | |
8353 | } | |
8354 | else if (s[1] == 's' && s[2] == 'p') | |
8355 | { | |
8356 | s += 3; | |
8357 | regno = SP; | |
8358 | } | |
8359 | else if (s[1] == 'g' && s[2] == 'p') | |
8360 | { | |
8361 | s += 3; | |
8362 | regno = GP; | |
8363 | } | |
8364 | else if (s[1] == 'a' && s[2] == 't') | |
8365 | { | |
8366 | s += 3; | |
8367 | regno = AT; | |
8368 | } | |
8369 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8370 | { | |
8371 | s += 4; | |
8372 | regno = KT0; | |
8373 | } | |
8374 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8375 | { | |
8376 | s += 4; | |
8377 | regno = KT1; | |
8378 | } | |
85b51719 TS |
8379 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8380 | { | |
8381 | s += 5; | |
8382 | regno = ZERO; | |
8383 | } | |
252b5132 RH |
8384 | else if (itbl_have_entries) |
8385 | { | |
8386 | char *p, *n; | |
d7ba4a77 | 8387 | unsigned long r; |
252b5132 | 8388 | |
d7ba4a77 | 8389 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8390 | n = itbl_get_field (&p); /* n is name */ |
8391 | ||
d7ba4a77 ILT |
8392 | /* See if this is a register defined in an |
8393 | itbl entry. */ | |
8394 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8395 | { |
8396 | /* Get_field advances to the start of | |
8397 | the next field, so we need to back | |
d7ba4a77 | 8398 | rack to the end of the last field. */ |
bdaaa2e1 | 8399 | if (p) |
252b5132 | 8400 | s = p - 1; |
bdaaa2e1 | 8401 | else |
d7ba4a77 | 8402 | s = strchr (s, '\0'); |
252b5132 RH |
8403 | regno = r; |
8404 | } | |
8405 | else | |
8406 | goto notreg; | |
beae10d5 | 8407 | } |
252b5132 RH |
8408 | else |
8409 | goto notreg; | |
8410 | } | |
8411 | if (regno == AT | |
8412 | && ! mips_opts.noat | |
8413 | && *args != 'E' | |
af7ee8bf CD |
8414 | && *args != 'G' |
8415 | && *args != 'K') | |
252b5132 RH |
8416 | as_warn (_("Used $at without \".set noat\"")); |
8417 | c = *args; | |
8418 | if (*s == ' ') | |
f9419b05 | 8419 | ++s; |
252b5132 RH |
8420 | if (args[1] != *s) |
8421 | { | |
8422 | if (c == 'r' || c == 'v' || c == 'w') | |
8423 | { | |
8424 | regno = lastregno; | |
8425 | s = s_reset; | |
f9419b05 | 8426 | ++args; |
252b5132 RH |
8427 | } |
8428 | } | |
8429 | /* 'z' only matches $0. */ | |
8430 | if (c == 'z' && regno != 0) | |
8431 | break; | |
8432 | ||
bdaaa2e1 KH |
8433 | /* Now that we have assembled one operand, we use the args string |
8434 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8435 | switch (c) |
8436 | { | |
8437 | case 'r': | |
8438 | case 's': | |
8439 | case 'v': | |
8440 | case 'b': | |
bf12938e | 8441 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8442 | break; |
8443 | case 'd': | |
8444 | case 'G': | |
af7ee8bf | 8445 | case 'K': |
bf12938e | 8446 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8447 | break; |
4372b673 | 8448 | case 'U': |
bf12938e RS |
8449 | INSERT_OPERAND (RD, *ip, regno); |
8450 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8451 | break; |
252b5132 RH |
8452 | case 'w': |
8453 | case 't': | |
8454 | case 'E': | |
bf12938e | 8455 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8456 | break; |
8457 | case 'x': | |
8458 | /* This case exists because on the r3000 trunc | |
8459 | expands into a macro which requires a gp | |
8460 | register. On the r6000 or r4000 it is | |
8461 | assembled into a single instruction which | |
8462 | ignores the register. Thus the insn version | |
8463 | is MIPS_ISA2 and uses 'x', and the macro | |
8464 | version is MIPS_ISA1 and uses 't'. */ | |
8465 | break; | |
8466 | case 'z': | |
8467 | /* This case is for the div instruction, which | |
8468 | acts differently if the destination argument | |
8469 | is $0. This only matches $0, and is checked | |
8470 | outside the switch. */ | |
8471 | break; | |
8472 | case 'D': | |
8473 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8474 | break; | |
8475 | /* What about all other operands like 'i', which | |
8476 | can be specified in the opcode table? */ | |
8477 | } | |
8478 | lastregno = regno; | |
8479 | continue; | |
8480 | } | |
8481 | notreg: | |
8482 | switch (*args++) | |
8483 | { | |
8484 | case 'r': | |
8485 | case 'v': | |
bf12938e | 8486 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8487 | continue; |
8488 | case 'w': | |
bf12938e | 8489 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8490 | continue; |
8491 | } | |
8492 | break; | |
8493 | ||
deec1734 CD |
8494 | case 'O': /* MDMX alignment immediate constant. */ |
8495 | my_getExpression (&imm_expr, s); | |
8496 | check_absolute_expr (ip, &imm_expr); | |
8497 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8498 | as_warn ("Improper align amount (%ld), using low bits", |
8499 | (long) imm_expr.X_add_number); | |
8500 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8501 | imm_expr.X_op = O_absent; |
8502 | s = expr_end; | |
8503 | continue; | |
8504 | ||
8505 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8506 | if (s[0] != '$') | |
8507 | { | |
8508 | /* MDMX Immediate. */ | |
8509 | my_getExpression (&imm_expr, s); | |
8510 | check_absolute_expr (ip, &imm_expr); | |
8511 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8512 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8513 | (long) imm_expr.X_add_number); | |
8514 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8515 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8516 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8517 | else | |
8518 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8519 | imm_expr.X_op = O_absent; |
8520 | s = expr_end; | |
8521 | continue; | |
8522 | } | |
8523 | /* Not MDMX Immediate. Fall through. */ | |
8524 | case 'X': /* MDMX destination register. */ | |
8525 | case 'Y': /* MDMX source register. */ | |
8526 | case 'Z': /* MDMX target register. */ | |
8527 | is_mdmx = 1; | |
252b5132 RH |
8528 | case 'D': /* floating point destination register */ |
8529 | case 'S': /* floating point source register */ | |
8530 | case 'T': /* floating point target register */ | |
8531 | case 'R': /* floating point source register */ | |
8532 | case 'V': | |
8533 | case 'W': | |
8534 | s_reset = s; | |
deec1734 CD |
8535 | /* Accept $fN for FP and MDMX register numbers, and in |
8536 | addition accept $vN for MDMX register numbers. */ | |
8537 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8538 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8539 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8540 | { |
8541 | s += 2; | |
8542 | regno = 0; | |
8543 | do | |
8544 | { | |
8545 | regno *= 10; | |
8546 | regno += *s - '0'; | |
8547 | ++s; | |
8548 | } | |
3882b010 | 8549 | while (ISDIGIT (*s)); |
252b5132 RH |
8550 | |
8551 | if (regno > 31) | |
8552 | as_bad (_("Invalid float register number (%d)"), regno); | |
8553 | ||
8554 | if ((regno & 1) != 0 | |
ca4e0257 | 8555 | && HAVE_32BIT_FPRS |
252b5132 RH |
8556 | && ! (strcmp (str, "mtc1") == 0 |
8557 | || strcmp (str, "mfc1") == 0 | |
8558 | || strcmp (str, "lwc1") == 0 | |
8559 | || strcmp (str, "swc1") == 0 | |
8560 | || strcmp (str, "l.s") == 0 | |
8561 | || strcmp (str, "s.s") == 0)) | |
8562 | as_warn (_("Float register should be even, was %d"), | |
8563 | regno); | |
8564 | ||
8565 | c = *args; | |
8566 | if (*s == ' ') | |
f9419b05 | 8567 | ++s; |
252b5132 RH |
8568 | if (args[1] != *s) |
8569 | { | |
8570 | if (c == 'V' || c == 'W') | |
8571 | { | |
8572 | regno = lastregno; | |
8573 | s = s_reset; | |
f9419b05 | 8574 | ++args; |
252b5132 RH |
8575 | } |
8576 | } | |
8577 | switch (c) | |
8578 | { | |
8579 | case 'D': | |
deec1734 | 8580 | case 'X': |
bf12938e | 8581 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8582 | break; |
8583 | case 'V': | |
8584 | case 'S': | |
deec1734 | 8585 | case 'Y': |
bf12938e | 8586 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8587 | break; |
deec1734 CD |
8588 | case 'Q': |
8589 | /* This is like 'Z', but also needs to fix the MDMX | |
8590 | vector/scalar select bits. Note that the | |
8591 | scalar immediate case is handled above. */ | |
8592 | if (*s == '[') | |
8593 | { | |
8594 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8595 | int max_el = (is_qh ? 3 : 7); | |
8596 | s++; | |
8597 | my_getExpression(&imm_expr, s); | |
8598 | check_absolute_expr (ip, &imm_expr); | |
8599 | s = expr_end; | |
8600 | if (imm_expr.X_add_number > max_el) | |
8601 | as_bad(_("Bad element selector %ld"), | |
8602 | (long) imm_expr.X_add_number); | |
8603 | imm_expr.X_add_number &= max_el; | |
8604 | ip->insn_opcode |= (imm_expr.X_add_number | |
8605 | << (OP_SH_VSEL + | |
8606 | (is_qh ? 2 : 1))); | |
01a3f561 | 8607 | imm_expr.X_op = O_absent; |
deec1734 CD |
8608 | if (*s != ']') |
8609 | as_warn(_("Expecting ']' found '%s'"), s); | |
8610 | else | |
8611 | s++; | |
8612 | } | |
8613 | else | |
8614 | { | |
8615 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8616 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8617 | << OP_SH_VSEL); | |
8618 | else | |
8619 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8620 | OP_SH_VSEL); | |
8621 | } | |
8622 | /* Fall through */ | |
252b5132 RH |
8623 | case 'W': |
8624 | case 'T': | |
deec1734 | 8625 | case 'Z': |
bf12938e | 8626 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8627 | break; |
8628 | case 'R': | |
bf12938e | 8629 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8630 | break; |
8631 | } | |
8632 | lastregno = regno; | |
8633 | continue; | |
8634 | } | |
8635 | ||
252b5132 RH |
8636 | switch (*args++) |
8637 | { | |
8638 | case 'V': | |
bf12938e | 8639 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8640 | continue; |
8641 | case 'W': | |
bf12938e | 8642 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8643 | continue; |
8644 | } | |
8645 | break; | |
8646 | ||
8647 | case 'I': | |
8648 | my_getExpression (&imm_expr, s); | |
8649 | if (imm_expr.X_op != O_big | |
8650 | && imm_expr.X_op != O_constant) | |
8651 | insn_error = _("absolute expression required"); | |
13757d0c | 8652 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8653 | s = expr_end; |
8654 | continue; | |
8655 | ||
8656 | case 'A': | |
8657 | my_getExpression (&offset_expr, s); | |
f6688943 | 8658 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8659 | s = expr_end; |
8660 | continue; | |
8661 | ||
8662 | case 'F': | |
8663 | case 'L': | |
8664 | case 'f': | |
8665 | case 'l': | |
8666 | { | |
8667 | int f64; | |
ca4e0257 | 8668 | int using_gprs; |
252b5132 RH |
8669 | char *save_in; |
8670 | char *err; | |
8671 | unsigned char temp[8]; | |
8672 | int len; | |
8673 | unsigned int length; | |
8674 | segT seg; | |
8675 | subsegT subseg; | |
8676 | char *p; | |
8677 | ||
8678 | /* These only appear as the last operand in an | |
8679 | instruction, and every instruction that accepts | |
8680 | them in any variant accepts them in all variants. | |
8681 | This means we don't have to worry about backing out | |
8682 | any changes if the instruction does not match. | |
8683 | ||
8684 | The difference between them is the size of the | |
8685 | floating point constant and where it goes. For 'F' | |
8686 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8687 | is 32 bits. Where the constant is placed is based | |
8688 | on how the MIPS assembler does things: | |
8689 | F -- .rdata | |
8690 | L -- .lit8 | |
8691 | f -- immediate value | |
8692 | l -- .lit4 | |
8693 | ||
8694 | The .lit4 and .lit8 sections are only used if | |
8695 | permitted by the -G argument. | |
8696 | ||
ca4e0257 RS |
8697 | The code below needs to know whether the target register |
8698 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8699 | 'F' are used with GPR-based instructions and 'l' and | |
8700 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8701 | |
8702 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8703 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8704 | |
8705 | save_in = input_line_pointer; | |
8706 | input_line_pointer = s; | |
8707 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8708 | length = len; | |
8709 | s = input_line_pointer; | |
8710 | input_line_pointer = save_in; | |
8711 | if (err != NULL && *err != '\0') | |
8712 | { | |
8713 | as_bad (_("Bad floating point constant: %s"), err); | |
8714 | memset (temp, '\0', sizeof temp); | |
8715 | length = f64 ? 8 : 4; | |
8716 | } | |
8717 | ||
156c2f8b | 8718 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8719 | |
8720 | if (*args == 'f' | |
8721 | || (*args == 'l' | |
3e722fb5 | 8722 | && (g_switch_value < 4 |
252b5132 RH |
8723 | || (temp[0] == 0 && temp[1] == 0) |
8724 | || (temp[2] == 0 && temp[3] == 0)))) | |
8725 | { | |
8726 | imm_expr.X_op = O_constant; | |
8727 | if (! target_big_endian) | |
8728 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8729 | else | |
8730 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8731 | } | |
8732 | else if (length > 4 | |
119d663a | 8733 | && ! mips_disable_float_construction |
ca4e0257 RS |
8734 | /* Constants can only be constructed in GPRs and |
8735 | copied to FPRs if the GPRs are at least as wide | |
8736 | as the FPRs. Force the constant into memory if | |
8737 | we are using 64-bit FPRs but the GPRs are only | |
8738 | 32 bits wide. */ | |
8739 | && (using_gprs | |
8740 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8741 | && ((temp[0] == 0 && temp[1] == 0) |
8742 | || (temp[2] == 0 && temp[3] == 0)) | |
8743 | && ((temp[4] == 0 && temp[5] == 0) | |
8744 | || (temp[6] == 0 && temp[7] == 0))) | |
8745 | { | |
ca4e0257 RS |
8746 | /* The value is simple enough to load with a couple of |
8747 | instructions. If using 32-bit registers, set | |
8748 | imm_expr to the high order 32 bits and offset_expr to | |
8749 | the low order 32 bits. Otherwise, set imm_expr to | |
8750 | the entire 64 bit constant. */ | |
8751 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8752 | { |
8753 | imm_expr.X_op = O_constant; | |
8754 | offset_expr.X_op = O_constant; | |
8755 | if (! target_big_endian) | |
8756 | { | |
8757 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8758 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8759 | } | |
8760 | else | |
8761 | { | |
8762 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8763 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8764 | } | |
8765 | if (offset_expr.X_add_number == 0) | |
8766 | offset_expr.X_op = O_absent; | |
8767 | } | |
8768 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8769 | { | |
8770 | imm_expr.X_op = O_constant; | |
8771 | if (! target_big_endian) | |
8772 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8773 | else | |
8774 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8775 | } | |
8776 | else | |
8777 | { | |
8778 | imm_expr.X_op = O_big; | |
8779 | imm_expr.X_add_number = 4; | |
8780 | if (! target_big_endian) | |
8781 | { | |
8782 | generic_bignum[0] = bfd_getl16 (temp); | |
8783 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8784 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8785 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8786 | } | |
8787 | else | |
8788 | { | |
8789 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8790 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8791 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8792 | generic_bignum[3] = bfd_getb16 (temp); | |
8793 | } | |
8794 | } | |
8795 | } | |
8796 | else | |
8797 | { | |
8798 | const char *newname; | |
8799 | segT new_seg; | |
8800 | ||
8801 | /* Switch to the right section. */ | |
8802 | seg = now_seg; | |
8803 | subseg = now_subseg; | |
8804 | switch (*args) | |
8805 | { | |
8806 | default: /* unused default case avoids warnings. */ | |
8807 | case 'L': | |
8808 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8809 | if (g_switch_value >= 8) |
252b5132 RH |
8810 | newname = ".lit8"; |
8811 | break; | |
8812 | case 'F': | |
3e722fb5 | 8813 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8814 | break; |
8815 | case 'l': | |
4d0d148d | 8816 | assert (g_switch_value >= 4); |
252b5132 RH |
8817 | newname = ".lit4"; |
8818 | break; | |
8819 | } | |
8820 | new_seg = subseg_new (newname, (subsegT) 0); | |
8821 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8822 | bfd_set_section_flags (stdoutput, new_seg, | |
8823 | (SEC_ALLOC | |
8824 | | SEC_LOAD | |
8825 | | SEC_READONLY | |
8826 | | SEC_DATA)); | |
8827 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8828 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8829 | && strcmp (TARGET_OS, "elf") != 0) | |
8830 | record_alignment (new_seg, 4); | |
8831 | else | |
8832 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8833 | if (seg == now_seg) | |
8834 | as_bad (_("Can't use floating point insn in this section")); | |
8835 | ||
8836 | /* Set the argument to the current address in the | |
8837 | section. */ | |
8838 | offset_expr.X_op = O_symbol; | |
8839 | offset_expr.X_add_symbol = | |
8840 | symbol_new ("L0\001", now_seg, | |
8841 | (valueT) frag_now_fix (), frag_now); | |
8842 | offset_expr.X_add_number = 0; | |
8843 | ||
8844 | /* Put the floating point number into the section. */ | |
8845 | p = frag_more ((int) length); | |
8846 | memcpy (p, temp, length); | |
8847 | ||
8848 | /* Switch back to the original section. */ | |
8849 | subseg_set (seg, subseg); | |
8850 | } | |
8851 | } | |
8852 | continue; | |
8853 | ||
8854 | case 'i': /* 16 bit unsigned immediate */ | |
8855 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8856 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8857 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8858 | { |
8859 | int more; | |
5e0116d5 RS |
8860 | offsetT minval, maxval; |
8861 | ||
8862 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8863 | && strcmp (insn->name, insn[1].name) == 0); | |
8864 | ||
8865 | /* If the expression was written as an unsigned number, | |
8866 | only treat it as signed if there are no more | |
8867 | alternatives. */ | |
8868 | if (more | |
8869 | && *args == 'j' | |
8870 | && sizeof (imm_expr.X_add_number) <= 4 | |
8871 | && imm_expr.X_op == O_constant | |
8872 | && imm_expr.X_add_number < 0 | |
8873 | && imm_expr.X_unsigned | |
8874 | && HAVE_64BIT_GPRS) | |
8875 | break; | |
8876 | ||
8877 | /* For compatibility with older assemblers, we accept | |
8878 | 0x8000-0xffff as signed 16-bit numbers when only | |
8879 | signed numbers are allowed. */ | |
8880 | if (*args == 'i') | |
8881 | minval = 0, maxval = 0xffff; | |
8882 | else if (more) | |
8883 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8884 | else |
5e0116d5 RS |
8885 | minval = -0x8000, maxval = 0xffff; |
8886 | ||
8887 | if (imm_expr.X_op != O_constant | |
8888 | || imm_expr.X_add_number < minval | |
8889 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8890 | { |
8891 | if (more) | |
8892 | break; | |
2ae7e77b AH |
8893 | if (imm_expr.X_op == O_constant |
8894 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8895 | as_bad (_("expression out of range")); |
252b5132 RH |
8896 | } |
8897 | } | |
8898 | s = expr_end; | |
8899 | continue; | |
8900 | ||
8901 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8902 | /* Check whether there is only a single bracketed expression |
8903 | left. If so, it must be the base register and the | |
8904 | constant must be zero. */ | |
8905 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8906 | { | |
8907 | offset_expr.X_op = O_constant; | |
8908 | offset_expr.X_add_number = 0; | |
8909 | continue; | |
8910 | } | |
252b5132 RH |
8911 | |
8912 | /* If this value won't fit into a 16 bit offset, then go | |
8913 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8914 | code pattern. */ |
5e0116d5 | 8915 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8916 | && (offset_expr.X_op != O_constant |
8917 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8918 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8919 | break; |
8920 | ||
252b5132 RH |
8921 | s = expr_end; |
8922 | continue; | |
8923 | ||
8924 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8925 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8926 | my_getExpression (&offset_expr, s); |
8927 | s = expr_end; | |
8928 | continue; | |
8929 | ||
8930 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8931 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8932 | && imm_expr.X_op == O_constant | |
8933 | && (imm_expr.X_add_number < 0 | |
8934 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8935 | as_bad (_("lui expression not in range 0..65535")); |
8936 | s = expr_end; | |
8937 | continue; | |
8938 | ||
8939 | case 'a': /* 26 bit address */ | |
8940 | my_getExpression (&offset_expr, s); | |
8941 | s = expr_end; | |
f6688943 | 8942 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8943 | continue; |
8944 | ||
8945 | case 'N': /* 3 bit branch condition code */ | |
8946 | case 'M': /* 3 bit compare condition code */ | |
8947 | if (strncmp (s, "$fcc", 4) != 0) | |
8948 | break; | |
8949 | s += 4; | |
8950 | regno = 0; | |
8951 | do | |
8952 | { | |
8953 | regno *= 10; | |
8954 | regno += *s - '0'; | |
8955 | ++s; | |
8956 | } | |
3882b010 | 8957 | while (ISDIGIT (*s)); |
252b5132 | 8958 | if (regno > 7) |
30c378fd CD |
8959 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8960 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8961 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8962 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8963 | && (regno & 1) != 0) | |
8964 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8965 | str, regno); | |
8966 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8967 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8968 | && (regno & 3) != 0) | |
8969 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8970 | str, regno); | |
252b5132 | 8971 | if (*args == 'N') |
bf12938e | 8972 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 8973 | else |
bf12938e | 8974 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 8975 | continue; |
252b5132 | 8976 | |
156c2f8b NC |
8977 | case 'H': |
8978 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8979 | s += 2; | |
3882b010 | 8980 | if (ISDIGIT (*s)) |
156c2f8b NC |
8981 | { |
8982 | c = 0; | |
8983 | do | |
8984 | { | |
8985 | c *= 10; | |
8986 | c += *s - '0'; | |
8987 | ++s; | |
8988 | } | |
3882b010 | 8989 | while (ISDIGIT (*s)); |
156c2f8b NC |
8990 | } |
8991 | else | |
8992 | c = 8; /* Invalid sel value. */ | |
8993 | ||
8994 | if (c > 7) | |
8995 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8996 | ip->insn_opcode |= c; | |
8997 | continue; | |
8998 | ||
60b63b72 RS |
8999 | case 'e': |
9000 | /* Must be at least one digit. */ | |
9001 | my_getExpression (&imm_expr, s); | |
9002 | check_absolute_expr (ip, &imm_expr); | |
9003 | ||
9004 | if ((unsigned long) imm_expr.X_add_number | |
9005 | > (unsigned long) OP_MASK_VECBYTE) | |
9006 | { | |
9007 | as_bad (_("bad byte vector index (%ld)"), | |
9008 | (long) imm_expr.X_add_number); | |
9009 | imm_expr.X_add_number = 0; | |
9010 | } | |
9011 | ||
bf12938e | 9012 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9013 | imm_expr.X_op = O_absent; |
9014 | s = expr_end; | |
9015 | continue; | |
9016 | ||
9017 | case '%': | |
9018 | my_getExpression (&imm_expr, s); | |
9019 | check_absolute_expr (ip, &imm_expr); | |
9020 | ||
9021 | if ((unsigned long) imm_expr.X_add_number | |
9022 | > (unsigned long) OP_MASK_VECALIGN) | |
9023 | { | |
9024 | as_bad (_("bad byte vector index (%ld)"), | |
9025 | (long) imm_expr.X_add_number); | |
9026 | imm_expr.X_add_number = 0; | |
9027 | } | |
9028 | ||
bf12938e | 9029 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9030 | imm_expr.X_op = O_absent; |
9031 | s = expr_end; | |
9032 | continue; | |
9033 | ||
252b5132 RH |
9034 | default: |
9035 | as_bad (_("bad char = '%c'\n"), *args); | |
9036 | internalError (); | |
9037 | } | |
9038 | break; | |
9039 | } | |
9040 | /* Args don't match. */ | |
9041 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9042 | !strcmp (insn->name, insn[1].name)) | |
9043 | { | |
9044 | ++insn; | |
9045 | s = argsStart; | |
268f6bed | 9046 | insn_error = _("illegal operands"); |
252b5132 RH |
9047 | continue; |
9048 | } | |
268f6bed L |
9049 | if (save_c) |
9050 | *(--s) = save_c; | |
252b5132 RH |
9051 | insn_error = _("illegal operands"); |
9052 | return; | |
9053 | } | |
9054 | } | |
9055 | ||
9056 | /* This routine assembles an instruction into its binary format when | |
9057 | assembling for the mips16. As a side effect, it sets one of the | |
9058 | global variables imm_reloc or offset_reloc to the type of | |
9059 | relocation to do if one of the operands is an address expression. | |
9060 | It also sets mips16_small and mips16_ext if the user explicitly | |
9061 | requested a small or extended instruction. */ | |
9062 | ||
9063 | static void | |
17a2f251 | 9064 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9065 | { |
9066 | char *s; | |
9067 | const char *args; | |
9068 | struct mips_opcode *insn; | |
9069 | char *argsstart; | |
9070 | unsigned int regno; | |
9071 | unsigned int lastregno = 0; | |
9072 | char *s_reset; | |
d6f16593 | 9073 | size_t i; |
252b5132 RH |
9074 | |
9075 | insn_error = NULL; | |
9076 | ||
b34976b6 AM |
9077 | mips16_small = FALSE; |
9078 | mips16_ext = FALSE; | |
252b5132 | 9079 | |
3882b010 | 9080 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9081 | ; |
9082 | switch (*s) | |
9083 | { | |
9084 | case '\0': | |
9085 | break; | |
9086 | ||
9087 | case ' ': | |
9088 | *s++ = '\0'; | |
9089 | break; | |
9090 | ||
9091 | case '.': | |
9092 | if (s[1] == 't' && s[2] == ' ') | |
9093 | { | |
9094 | *s = '\0'; | |
b34976b6 | 9095 | mips16_small = TRUE; |
252b5132 RH |
9096 | s += 3; |
9097 | break; | |
9098 | } | |
9099 | else if (s[1] == 'e' && s[2] == ' ') | |
9100 | { | |
9101 | *s = '\0'; | |
b34976b6 | 9102 | mips16_ext = TRUE; |
252b5132 RH |
9103 | s += 3; |
9104 | break; | |
9105 | } | |
9106 | /* Fall through. */ | |
9107 | default: | |
9108 | insn_error = _("unknown opcode"); | |
9109 | return; | |
9110 | } | |
9111 | ||
9112 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9113 | mips16_small = TRUE; |
252b5132 RH |
9114 | |
9115 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9116 | { | |
9117 | insn_error = _("unrecognized opcode"); | |
9118 | return; | |
9119 | } | |
9120 | ||
9121 | argsstart = s; | |
9122 | for (;;) | |
9123 | { | |
9124 | assert (strcmp (insn->name, str) == 0); | |
9125 | ||
9126 | ip->insn_mo = insn; | |
9127 | ip->insn_opcode = insn->match; | |
b34976b6 | 9128 | ip->use_extend = FALSE; |
252b5132 | 9129 | imm_expr.X_op = O_absent; |
f6688943 TS |
9130 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9131 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9132 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9133 | imm2_expr.X_op = O_absent; |
252b5132 | 9134 | offset_expr.X_op = O_absent; |
f6688943 TS |
9135 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9136 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9137 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9138 | for (args = insn->args; 1; ++args) |
9139 | { | |
9140 | int c; | |
9141 | ||
9142 | if (*s == ' ') | |
9143 | ++s; | |
9144 | ||
9145 | /* In this switch statement we call break if we did not find | |
9146 | a match, continue if we did find a match, or return if we | |
9147 | are done. */ | |
9148 | ||
9149 | c = *args; | |
9150 | switch (c) | |
9151 | { | |
9152 | case '\0': | |
9153 | if (*s == '\0') | |
9154 | { | |
9155 | /* Stuff the immediate value in now, if we can. */ | |
9156 | if (imm_expr.X_op == O_constant | |
f6688943 | 9157 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9158 | && insn->pinfo != INSN_MACRO) |
9159 | { | |
d6f16593 MR |
9160 | valueT tmp; |
9161 | ||
9162 | switch (*offset_reloc) | |
9163 | { | |
9164 | case BFD_RELOC_MIPS16_HI16_S: | |
9165 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9166 | break; | |
9167 | ||
9168 | case BFD_RELOC_MIPS16_HI16: | |
9169 | tmp = imm_expr.X_add_number >> 16; | |
9170 | break; | |
9171 | ||
9172 | case BFD_RELOC_MIPS16_LO16: | |
9173 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9174 | - 0x8000; | |
9175 | break; | |
9176 | ||
9177 | case BFD_RELOC_UNUSED: | |
9178 | tmp = imm_expr.X_add_number; | |
9179 | break; | |
9180 | ||
9181 | default: | |
9182 | internalError (); | |
9183 | } | |
9184 | *offset_reloc = BFD_RELOC_UNUSED; | |
9185 | ||
c4e7957c | 9186 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9187 | tmp, TRUE, mips16_small, |
252b5132 RH |
9188 | mips16_ext, &ip->insn_opcode, |
9189 | &ip->use_extend, &ip->extend); | |
9190 | imm_expr.X_op = O_absent; | |
f6688943 | 9191 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9192 | } |
9193 | ||
9194 | return; | |
9195 | } | |
9196 | break; | |
9197 | ||
9198 | case ',': | |
9199 | if (*s++ == c) | |
9200 | continue; | |
9201 | s--; | |
9202 | switch (*++args) | |
9203 | { | |
9204 | case 'v': | |
bf12938e | 9205 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9206 | continue; |
9207 | case 'w': | |
bf12938e | 9208 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9209 | continue; |
9210 | } | |
9211 | break; | |
9212 | ||
9213 | case '(': | |
9214 | case ')': | |
9215 | if (*s++ == c) | |
9216 | continue; | |
9217 | break; | |
9218 | ||
9219 | case 'v': | |
9220 | case 'w': | |
9221 | if (s[0] != '$') | |
9222 | { | |
9223 | if (c == 'v') | |
bf12938e | 9224 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9225 | else |
bf12938e | 9226 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9227 | ++args; |
9228 | continue; | |
9229 | } | |
9230 | /* Fall through. */ | |
9231 | case 'x': | |
9232 | case 'y': | |
9233 | case 'z': | |
9234 | case 'Z': | |
9235 | case '0': | |
9236 | case 'S': | |
9237 | case 'R': | |
9238 | case 'X': | |
9239 | case 'Y': | |
9240 | if (s[0] != '$') | |
9241 | break; | |
9242 | s_reset = s; | |
3882b010 | 9243 | if (ISDIGIT (s[1])) |
252b5132 RH |
9244 | { |
9245 | ++s; | |
9246 | regno = 0; | |
9247 | do | |
9248 | { | |
9249 | regno *= 10; | |
9250 | regno += *s - '0'; | |
9251 | ++s; | |
9252 | } | |
3882b010 | 9253 | while (ISDIGIT (*s)); |
252b5132 RH |
9254 | if (regno > 31) |
9255 | { | |
9256 | as_bad (_("invalid register number (%d)"), regno); | |
9257 | regno = 2; | |
9258 | } | |
9259 | } | |
9260 | else | |
9261 | { | |
76db943d TS |
9262 | if (s[1] == 'r' && s[2] == 'a') |
9263 | { | |
9264 | s += 3; | |
9265 | regno = RA; | |
9266 | } | |
9267 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9268 | { |
9269 | s += 3; | |
9270 | regno = FP; | |
9271 | } | |
9272 | else if (s[1] == 's' && s[2] == 'p') | |
9273 | { | |
9274 | s += 3; | |
9275 | regno = SP; | |
9276 | } | |
9277 | else if (s[1] == 'g' && s[2] == 'p') | |
9278 | { | |
9279 | s += 3; | |
9280 | regno = GP; | |
9281 | } | |
9282 | else if (s[1] == 'a' && s[2] == 't') | |
9283 | { | |
9284 | s += 3; | |
9285 | regno = AT; | |
9286 | } | |
9287 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9288 | { | |
9289 | s += 4; | |
9290 | regno = KT0; | |
9291 | } | |
9292 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9293 | { | |
9294 | s += 4; | |
9295 | regno = KT1; | |
9296 | } | |
85b51719 TS |
9297 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9298 | { | |
9299 | s += 5; | |
9300 | regno = ZERO; | |
9301 | } | |
252b5132 RH |
9302 | else |
9303 | break; | |
9304 | } | |
9305 | ||
9306 | if (*s == ' ') | |
9307 | ++s; | |
9308 | if (args[1] != *s) | |
9309 | { | |
9310 | if (c == 'v' || c == 'w') | |
9311 | { | |
9312 | regno = mips16_to_32_reg_map[lastregno]; | |
9313 | s = s_reset; | |
f9419b05 | 9314 | ++args; |
252b5132 RH |
9315 | } |
9316 | } | |
9317 | ||
9318 | switch (c) | |
9319 | { | |
9320 | case 'x': | |
9321 | case 'y': | |
9322 | case 'z': | |
9323 | case 'v': | |
9324 | case 'w': | |
9325 | case 'Z': | |
9326 | regno = mips32_to_16_reg_map[regno]; | |
9327 | break; | |
9328 | ||
9329 | case '0': | |
9330 | if (regno != 0) | |
9331 | regno = ILLEGAL_REG; | |
9332 | break; | |
9333 | ||
9334 | case 'S': | |
9335 | if (regno != SP) | |
9336 | regno = ILLEGAL_REG; | |
9337 | break; | |
9338 | ||
9339 | case 'R': | |
9340 | if (regno != RA) | |
9341 | regno = ILLEGAL_REG; | |
9342 | break; | |
9343 | ||
9344 | case 'X': | |
9345 | case 'Y': | |
9346 | if (regno == AT && ! mips_opts.noat) | |
9347 | as_warn (_("used $at without \".set noat\"")); | |
9348 | break; | |
9349 | ||
9350 | default: | |
9351 | internalError (); | |
9352 | } | |
9353 | ||
9354 | if (regno == ILLEGAL_REG) | |
9355 | break; | |
9356 | ||
9357 | switch (c) | |
9358 | { | |
9359 | case 'x': | |
9360 | case 'v': | |
bf12938e | 9361 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9362 | break; |
9363 | case 'y': | |
9364 | case 'w': | |
bf12938e | 9365 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9366 | break; |
9367 | case 'z': | |
bf12938e | 9368 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9369 | break; |
9370 | case 'Z': | |
bf12938e | 9371 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9372 | case '0': |
9373 | case 'S': | |
9374 | case 'R': | |
9375 | break; | |
9376 | case 'X': | |
bf12938e | 9377 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9378 | break; |
9379 | case 'Y': | |
9380 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9381 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9382 | break; |
9383 | default: | |
9384 | internalError (); | |
9385 | } | |
9386 | ||
9387 | lastregno = regno; | |
9388 | continue; | |
9389 | ||
9390 | case 'P': | |
9391 | if (strncmp (s, "$pc", 3) == 0) | |
9392 | { | |
9393 | s += 3; | |
9394 | continue; | |
9395 | } | |
9396 | break; | |
9397 | ||
252b5132 RH |
9398 | case '5': |
9399 | case 'H': | |
9400 | case 'W': | |
9401 | case 'D': | |
9402 | case 'j': | |
252b5132 RH |
9403 | case 'V': |
9404 | case 'C': | |
9405 | case 'U': | |
9406 | case 'k': | |
9407 | case 'K': | |
d6f16593 MR |
9408 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9409 | if (i > 0) | |
252b5132 | 9410 | { |
d6f16593 | 9411 | if (imm_expr.X_op != O_constant) |
252b5132 | 9412 | { |
b34976b6 | 9413 | mips16_ext = TRUE; |
b34976b6 | 9414 | ip->use_extend = TRUE; |
252b5132 | 9415 | ip->extend = 0; |
252b5132 | 9416 | } |
d6f16593 MR |
9417 | else |
9418 | { | |
9419 | /* We need to relax this instruction. */ | |
9420 | *offset_reloc = *imm_reloc; | |
9421 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9422 | } | |
9423 | s = expr_end; | |
9424 | continue; | |
252b5132 | 9425 | } |
d6f16593 MR |
9426 | *imm_reloc = BFD_RELOC_UNUSED; |
9427 | /* Fall through. */ | |
9428 | case '<': | |
9429 | case '>': | |
9430 | case '[': | |
9431 | case ']': | |
9432 | case '4': | |
9433 | case '8': | |
9434 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9435 | if (imm_expr.X_op == O_register) |
9436 | { | |
9437 | /* What we thought was an expression turned out to | |
9438 | be a register. */ | |
9439 | ||
9440 | if (s[0] == '(' && args[1] == '(') | |
9441 | { | |
9442 | /* It looks like the expression was omitted | |
9443 | before a register indirection, which means | |
9444 | that the expression is implicitly zero. We | |
9445 | still set up imm_expr, so that we handle | |
9446 | explicit extensions correctly. */ | |
9447 | imm_expr.X_op = O_constant; | |
9448 | imm_expr.X_add_number = 0; | |
f6688943 | 9449 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9450 | continue; |
9451 | } | |
9452 | ||
9453 | break; | |
9454 | } | |
9455 | ||
9456 | /* We need to relax this instruction. */ | |
f6688943 | 9457 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9458 | s = expr_end; |
9459 | continue; | |
9460 | ||
9461 | case 'p': | |
9462 | case 'q': | |
9463 | case 'A': | |
9464 | case 'B': | |
9465 | case 'E': | |
9466 | /* We use offset_reloc rather than imm_reloc for the PC | |
9467 | relative operands. This lets macros with both | |
9468 | immediate and address operands work correctly. */ | |
9469 | my_getExpression (&offset_expr, s); | |
9470 | ||
9471 | if (offset_expr.X_op == O_register) | |
9472 | break; | |
9473 | ||
9474 | /* We need to relax this instruction. */ | |
f6688943 | 9475 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9476 | s = expr_end; |
9477 | continue; | |
9478 | ||
9479 | case '6': /* break code */ | |
9480 | my_getExpression (&imm_expr, s); | |
9481 | check_absolute_expr (ip, &imm_expr); | |
9482 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9483 | as_warn (_("Invalid value for `%s' (%lu)"), |
9484 | ip->insn_mo->name, | |
9485 | (unsigned long) imm_expr.X_add_number); | |
9486 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9487 | imm_expr.X_op = O_absent; |
9488 | s = expr_end; | |
9489 | continue; | |
9490 | ||
9491 | case 'a': /* 26 bit address */ | |
9492 | my_getExpression (&offset_expr, s); | |
9493 | s = expr_end; | |
f6688943 | 9494 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9495 | ip->insn_opcode <<= 16; |
9496 | continue; | |
9497 | ||
9498 | case 'l': /* register list for entry macro */ | |
9499 | case 'L': /* register list for exit macro */ | |
9500 | { | |
9501 | int mask; | |
9502 | ||
9503 | if (c == 'l') | |
9504 | mask = 0; | |
9505 | else | |
9506 | mask = 7 << 3; | |
9507 | while (*s != '\0') | |
9508 | { | |
9509 | int freg, reg1, reg2; | |
9510 | ||
9511 | while (*s == ' ' || *s == ',') | |
9512 | ++s; | |
9513 | if (*s != '$') | |
9514 | { | |
9515 | as_bad (_("can't parse register list")); | |
9516 | break; | |
9517 | } | |
9518 | ++s; | |
9519 | if (*s != 'f') | |
9520 | freg = 0; | |
9521 | else | |
9522 | { | |
9523 | freg = 1; | |
9524 | ++s; | |
9525 | } | |
9526 | reg1 = 0; | |
3882b010 | 9527 | while (ISDIGIT (*s)) |
252b5132 RH |
9528 | { |
9529 | reg1 *= 10; | |
9530 | reg1 += *s - '0'; | |
9531 | ++s; | |
9532 | } | |
9533 | if (*s == ' ') | |
9534 | ++s; | |
9535 | if (*s != '-') | |
9536 | reg2 = reg1; | |
9537 | else | |
9538 | { | |
9539 | ++s; | |
9540 | if (*s != '$') | |
9541 | break; | |
9542 | ++s; | |
9543 | if (freg) | |
9544 | { | |
9545 | if (*s == 'f') | |
9546 | ++s; | |
9547 | else | |
9548 | { | |
9549 | as_bad (_("invalid register list")); | |
9550 | break; | |
9551 | } | |
9552 | } | |
9553 | reg2 = 0; | |
3882b010 | 9554 | while (ISDIGIT (*s)) |
252b5132 RH |
9555 | { |
9556 | reg2 *= 10; | |
9557 | reg2 += *s - '0'; | |
9558 | ++s; | |
9559 | } | |
9560 | } | |
9561 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9562 | { | |
9563 | mask &= ~ (7 << 3); | |
9564 | mask |= 5 << 3; | |
9565 | } | |
9566 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9567 | { | |
9568 | mask &= ~ (7 << 3); | |
9569 | mask |= 6 << 3; | |
9570 | } | |
9571 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9572 | mask |= (reg2 - 3) << 3; | |
9573 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9574 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9575 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9576 | mask |= 1; |
9577 | else | |
9578 | { | |
9579 | as_bad (_("invalid register list")); | |
9580 | break; | |
9581 | } | |
9582 | } | |
9583 | /* The mask is filled in in the opcode table for the | |
9584 | benefit of the disassembler. We remove it before | |
9585 | applying the actual mask. */ | |
9586 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9587 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9588 | } | |
9589 | continue; | |
9590 | ||
9591 | case 'e': /* extend code */ | |
9592 | my_getExpression (&imm_expr, s); | |
9593 | check_absolute_expr (ip, &imm_expr); | |
9594 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9595 | { | |
9596 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9597 | ip->insn_mo->name, | |
9598 | (unsigned long) imm_expr.X_add_number); | |
9599 | imm_expr.X_add_number &= 0x7ff; | |
9600 | } | |
9601 | ip->insn_opcode |= imm_expr.X_add_number; | |
9602 | imm_expr.X_op = O_absent; | |
9603 | s = expr_end; | |
9604 | continue; | |
9605 | ||
9606 | default: | |
9607 | internalError (); | |
9608 | } | |
9609 | break; | |
9610 | } | |
9611 | ||
9612 | /* Args don't match. */ | |
9613 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9614 | strcmp (insn->name, insn[1].name) == 0) | |
9615 | { | |
9616 | ++insn; | |
9617 | s = argsstart; | |
9618 | continue; | |
9619 | } | |
9620 | ||
9621 | insn_error = _("illegal operands"); | |
9622 | ||
9623 | return; | |
9624 | } | |
9625 | } | |
9626 | ||
9627 | /* This structure holds information we know about a mips16 immediate | |
9628 | argument type. */ | |
9629 | ||
e972090a NC |
9630 | struct mips16_immed_operand |
9631 | { | |
252b5132 RH |
9632 | /* The type code used in the argument string in the opcode table. */ |
9633 | int type; | |
9634 | /* The number of bits in the short form of the opcode. */ | |
9635 | int nbits; | |
9636 | /* The number of bits in the extended form of the opcode. */ | |
9637 | int extbits; | |
9638 | /* The amount by which the short form is shifted when it is used; | |
9639 | for example, the sw instruction has a shift count of 2. */ | |
9640 | int shift; | |
9641 | /* The amount by which the short form is shifted when it is stored | |
9642 | into the instruction code. */ | |
9643 | int op_shift; | |
9644 | /* Non-zero if the short form is unsigned. */ | |
9645 | int unsp; | |
9646 | /* Non-zero if the extended form is unsigned. */ | |
9647 | int extu; | |
9648 | /* Non-zero if the value is PC relative. */ | |
9649 | int pcrel; | |
9650 | }; | |
9651 | ||
9652 | /* The mips16 immediate operand types. */ | |
9653 | ||
9654 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9655 | { | |
9656 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9657 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9658 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9659 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9660 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9661 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9662 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9663 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9664 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9665 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9666 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9667 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9668 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9669 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9670 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9671 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9672 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9673 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9674 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9675 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9676 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9677 | }; | |
9678 | ||
9679 | #define MIPS16_NUM_IMMED \ | |
9680 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9681 | ||
9682 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9683 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9684 | whether an extended value is needed; if one is needed, it sets | |
9685 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9686 | If SMALL is true, an unextended opcode was explicitly requested. | |
9687 | If EXT is true, an extended opcode was explicitly requested. If | |
9688 | WARN is true, warn if EXT does not match reality. */ | |
9689 | ||
9690 | static void | |
17a2f251 TS |
9691 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9692 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9693 | unsigned long *insn, bfd_boolean *use_extend, | |
9694 | unsigned short *extend) | |
252b5132 RH |
9695 | { |
9696 | register const struct mips16_immed_operand *op; | |
9697 | int mintiny, maxtiny; | |
b34976b6 | 9698 | bfd_boolean needext; |
252b5132 RH |
9699 | |
9700 | op = mips16_immed_operands; | |
9701 | while (op->type != type) | |
9702 | { | |
9703 | ++op; | |
9704 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9705 | } | |
9706 | ||
9707 | if (op->unsp) | |
9708 | { | |
9709 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9710 | { | |
9711 | mintiny = 1; | |
9712 | maxtiny = 1 << op->nbits; | |
9713 | } | |
9714 | else | |
9715 | { | |
9716 | mintiny = 0; | |
9717 | maxtiny = (1 << op->nbits) - 1; | |
9718 | } | |
9719 | } | |
9720 | else | |
9721 | { | |
9722 | mintiny = - (1 << (op->nbits - 1)); | |
9723 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9724 | } | |
9725 | ||
9726 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9727 | if (type == 'p' || type == 'q') | |
9728 | val /= 2; | |
9729 | ||
9730 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9731 | || val < (mintiny << op->shift) | |
9732 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9733 | needext = TRUE; |
252b5132 | 9734 | else |
b34976b6 | 9735 | needext = FALSE; |
252b5132 RH |
9736 | |
9737 | if (warn && ext && ! needext) | |
beae10d5 KH |
9738 | as_warn_where (file, line, |
9739 | _("extended operand requested but not required")); | |
252b5132 RH |
9740 | if (small && needext) |
9741 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9742 | ||
9743 | if (small || (! ext && ! needext)) | |
9744 | { | |
9745 | int insnval; | |
9746 | ||
b34976b6 | 9747 | *use_extend = FALSE; |
252b5132 RH |
9748 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9749 | insnval <<= op->op_shift; | |
9750 | *insn |= insnval; | |
9751 | } | |
9752 | else | |
9753 | { | |
9754 | long minext, maxext; | |
9755 | int extval; | |
9756 | ||
9757 | if (op->extu) | |
9758 | { | |
9759 | minext = 0; | |
9760 | maxext = (1 << op->extbits) - 1; | |
9761 | } | |
9762 | else | |
9763 | { | |
9764 | minext = - (1 << (op->extbits - 1)); | |
9765 | maxext = (1 << (op->extbits - 1)) - 1; | |
9766 | } | |
9767 | if (val < minext || val > maxext) | |
9768 | as_bad_where (file, line, | |
9769 | _("operand value out of range for instruction")); | |
9770 | ||
b34976b6 | 9771 | *use_extend = TRUE; |
252b5132 RH |
9772 | if (op->extbits == 16) |
9773 | { | |
9774 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9775 | val &= 0x1f; | |
9776 | } | |
9777 | else if (op->extbits == 15) | |
9778 | { | |
9779 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9780 | val &= 0xf; | |
9781 | } | |
9782 | else | |
9783 | { | |
9784 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9785 | val = 0; | |
9786 | } | |
9787 | ||
9788 | *extend = (unsigned short) extval; | |
9789 | *insn |= val; | |
9790 | } | |
9791 | } | |
9792 | \f | |
d6f16593 | 9793 | struct percent_op_match |
ad8d3bb3 | 9794 | { |
5e0116d5 RS |
9795 | const char *str; |
9796 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9797 | }; |
9798 | ||
9799 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9800 | { |
5e0116d5 | 9801 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9802 | #ifdef OBJ_ELF |
5e0116d5 RS |
9803 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9804 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9805 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9806 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9807 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9808 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9809 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9810 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9811 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9812 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9813 | {"%half", BFD_RELOC_16}, | |
9814 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9815 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9816 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9817 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9818 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9819 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9820 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9821 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9822 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9823 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9824 | #endif |
5e0116d5 | 9825 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9826 | }; |
9827 | ||
d6f16593 MR |
9828 | static const struct percent_op_match mips16_percent_op[] = |
9829 | { | |
9830 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9831 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9832 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9833 | }; | |
9834 | ||
252b5132 | 9835 | |
5e0116d5 RS |
9836 | /* Return true if *STR points to a relocation operator. When returning true, |
9837 | move *STR over the operator and store its relocation code in *RELOC. | |
9838 | Leave both *STR and *RELOC alone when returning false. */ | |
9839 | ||
9840 | static bfd_boolean | |
17a2f251 | 9841 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9842 | { |
d6f16593 MR |
9843 | const struct percent_op_match *percent_op; |
9844 | size_t limit, i; | |
9845 | ||
9846 | if (mips_opts.mips16) | |
9847 | { | |
9848 | percent_op = mips16_percent_op; | |
9849 | limit = ARRAY_SIZE (mips16_percent_op); | |
9850 | } | |
9851 | else | |
9852 | { | |
9853 | percent_op = mips_percent_op; | |
9854 | limit = ARRAY_SIZE (mips_percent_op); | |
9855 | } | |
76b3015f | 9856 | |
d6f16593 | 9857 | for (i = 0; i < limit; i++) |
5e0116d5 | 9858 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9859 | { |
3f98094e DJ |
9860 | int len = strlen (percent_op[i].str); |
9861 | ||
9862 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9863 | continue; | |
9864 | ||
5e0116d5 RS |
9865 | *str += strlen (percent_op[i].str); |
9866 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9867 | |
5e0116d5 RS |
9868 | /* Check whether the output BFD supports this relocation. |
9869 | If not, issue an error and fall back on something safe. */ | |
9870 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9871 | { |
5e0116d5 RS |
9872 | as_bad ("relocation %s isn't supported by the current ABI", |
9873 | percent_op[i].str); | |
01a3f561 | 9874 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9875 | } |
5e0116d5 | 9876 | return TRUE; |
394f9b3a | 9877 | } |
5e0116d5 | 9878 | return FALSE; |
394f9b3a | 9879 | } |
ad8d3bb3 | 9880 | |
ad8d3bb3 | 9881 | |
5e0116d5 RS |
9882 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9883 | expression in *EP and the relocations in the array starting | |
9884 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9885 | |
01a3f561 | 9886 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9887 | |
5e0116d5 | 9888 | static size_t |
17a2f251 TS |
9889 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9890 | char *str) | |
ad8d3bb3 | 9891 | { |
5e0116d5 RS |
9892 | bfd_reloc_code_real_type reversed_reloc[3]; |
9893 | size_t reloc_index, i; | |
09b8f35a RS |
9894 | int crux_depth, str_depth; |
9895 | char *crux; | |
5e0116d5 RS |
9896 | |
9897 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9898 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9899 | of the main expression and with CRUX_DEPTH containing the number | |
9900 | of open brackets at that point. */ | |
9901 | reloc_index = -1; | |
9902 | str_depth = 0; | |
9903 | do | |
fb1b3232 | 9904 | { |
09b8f35a RS |
9905 | reloc_index++; |
9906 | crux = str; | |
9907 | crux_depth = str_depth; | |
9908 | ||
9909 | /* Skip over whitespace and brackets, keeping count of the number | |
9910 | of brackets. */ | |
9911 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9912 | if (*str++ == '(') | |
9913 | str_depth++; | |
5e0116d5 | 9914 | } |
09b8f35a RS |
9915 | while (*str == '%' |
9916 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9917 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9918 | |
09b8f35a | 9919 | my_getExpression (ep, crux); |
5e0116d5 | 9920 | str = expr_end; |
394f9b3a | 9921 | |
5e0116d5 | 9922 | /* Match every open bracket. */ |
09b8f35a | 9923 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9924 | if (*str++ == ')') |
09b8f35a | 9925 | crux_depth--; |
394f9b3a | 9926 | |
09b8f35a | 9927 | if (crux_depth > 0) |
5e0116d5 | 9928 | as_bad ("unclosed '('"); |
394f9b3a | 9929 | |
5e0116d5 | 9930 | expr_end = str; |
252b5132 | 9931 | |
01a3f561 | 9932 | if (reloc_index != 0) |
64bdfcaf RS |
9933 | { |
9934 | prev_reloc_op_frag = frag_now; | |
9935 | for (i = 0; i < reloc_index; i++) | |
9936 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9937 | } | |
fb1b3232 | 9938 | |
5e0116d5 | 9939 | return reloc_index; |
252b5132 RH |
9940 | } |
9941 | ||
9942 | static void | |
17a2f251 | 9943 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9944 | { |
9945 | char *save_in; | |
98aa84af | 9946 | valueT val; |
252b5132 RH |
9947 | |
9948 | save_in = input_line_pointer; | |
9949 | input_line_pointer = str; | |
9950 | expression (ep); | |
9951 | expr_end = input_line_pointer; | |
9952 | input_line_pointer = save_in; | |
9953 | ||
9954 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9955 | then we bump the value of the symbol by 1 since that is how other | |
9956 | text symbols are handled. We don't bother to handle complex | |
9957 | expressions, just `.' plus or minus a constant. */ | |
9958 | if (mips_opts.mips16 | |
9959 | && ep->X_op == O_symbol | |
9960 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9961 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9962 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9963 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9964 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9965 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9966 | } |
9967 | ||
9968 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9969 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9970 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9971 | returned, or NULL on OK. */ |
9972 | ||
9973 | char * | |
17a2f251 | 9974 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9975 | { |
9976 | int prec; | |
9977 | LITTLENUM_TYPE words[4]; | |
9978 | char *t; | |
9979 | int i; | |
9980 | ||
9981 | switch (type) | |
9982 | { | |
9983 | case 'f': | |
9984 | prec = 2; | |
9985 | break; | |
9986 | ||
9987 | case 'd': | |
9988 | prec = 4; | |
9989 | break; | |
9990 | ||
9991 | default: | |
9992 | *sizeP = 0; | |
9993 | return _("bad call to md_atof"); | |
9994 | } | |
9995 | ||
9996 | t = atof_ieee (input_line_pointer, type, words); | |
9997 | if (t) | |
9998 | input_line_pointer = t; | |
9999 | ||
10000 | *sizeP = prec * 2; | |
10001 | ||
10002 | if (! target_big_endian) | |
10003 | { | |
10004 | for (i = prec - 1; i >= 0; i--) | |
10005 | { | |
17a2f251 | 10006 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10007 | litP += 2; |
10008 | } | |
10009 | } | |
10010 | else | |
10011 | { | |
10012 | for (i = 0; i < prec; i++) | |
10013 | { | |
17a2f251 | 10014 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10015 | litP += 2; |
10016 | } | |
10017 | } | |
bdaaa2e1 | 10018 | |
252b5132 RH |
10019 | return NULL; |
10020 | } | |
10021 | ||
10022 | void | |
17a2f251 | 10023 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10024 | { |
10025 | if (target_big_endian) | |
10026 | number_to_chars_bigendian (buf, val, n); | |
10027 | else | |
10028 | number_to_chars_littleendian (buf, val, n); | |
10029 | } | |
10030 | \f | |
ae948b86 | 10031 | #ifdef OBJ_ELF |
e013f690 TS |
10032 | static int support_64bit_objects(void) |
10033 | { | |
10034 | const char **list, **l; | |
aa3d8fdf | 10035 | int yes; |
e013f690 TS |
10036 | |
10037 | list = bfd_target_list (); | |
10038 | for (l = list; *l != NULL; l++) | |
10039 | #ifdef TE_TMIPS | |
10040 | /* This is traditional mips */ | |
10041 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10042 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10043 | #else | |
10044 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10045 | || strcmp (*l, "elf64-littlemips") == 0) | |
10046 | #endif | |
10047 | break; | |
aa3d8fdf | 10048 | yes = (*l != NULL); |
e013f690 | 10049 | free (list); |
aa3d8fdf | 10050 | return yes; |
e013f690 | 10051 | } |
ae948b86 | 10052 | #endif /* OBJ_ELF */ |
e013f690 | 10053 | |
78849248 | 10054 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10055 | |
e972090a NC |
10056 | struct option md_longopts[] = |
10057 | { | |
f9b4148d CD |
10058 | /* Options which specify architecture. */ |
10059 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10060 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10061 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10062 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10063 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10064 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10065 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10066 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10067 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10068 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10069 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10070 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10071 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10072 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10073 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10074 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10075 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10076 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10077 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10078 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10079 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10080 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10081 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10082 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10083 | |
10084 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10085 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10086 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10087 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10088 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10089 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10090 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10091 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10092 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10093 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10094 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10095 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10096 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10097 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10098 | ||
10099 | /* Old-style architecture options. Don't add more of these. */ | |
10100 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10101 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10102 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10103 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10104 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10105 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10106 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10107 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10108 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10109 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10110 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10111 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10112 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10113 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10114 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10115 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10116 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10117 | ||
10118 | /* Options which enable bug fixes. */ | |
10119 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10120 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10121 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10122 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10123 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10124 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10125 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10126 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10127 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10128 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10129 | |
10130 | /* Miscellaneous options. */ | |
10131 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 10132 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10133 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10134 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10135 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10136 | {"break", no_argument, NULL, OPTION_BREAK}, |
10137 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10138 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10139 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10140 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10141 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10142 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10143 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10144 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10145 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10146 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10147 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10148 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10149 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10150 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10151 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10152 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10153 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10154 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10155 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10156 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10157 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10158 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10159 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10160 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10161 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10162 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10163 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10164 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10165 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10166 | |
10167 | /* ELF-specific options. */ | |
156c2f8b | 10168 | #ifdef OBJ_ELF |
aed1a261 | 10169 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10170 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10171 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10172 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10173 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10174 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10175 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10176 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10177 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10178 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10179 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10180 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10181 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10182 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10183 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10184 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10185 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10186 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10187 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10188 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10189 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10190 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10191 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10192 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10193 | #endif /* OBJ_ELF */ |
f9b4148d | 10194 | |
252b5132 RH |
10195 | {NULL, no_argument, NULL, 0} |
10196 | }; | |
156c2f8b | 10197 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10198 | |
316f5878 RS |
10199 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10200 | NEW_VALUE. Warn if another value was already specified. Note: | |
10201 | we have to defer parsing the -march and -mtune arguments in order | |
10202 | to handle 'from-abi' correctly, since the ABI might be specified | |
10203 | in a later argument. */ | |
10204 | ||
10205 | static void | |
17a2f251 | 10206 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10207 | { |
10208 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10209 | as_warn (_("A different %s was already specified, is now %s"), | |
10210 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10211 | new_value); | |
10212 | ||
10213 | *string_ptr = new_value; | |
10214 | } | |
10215 | ||
252b5132 | 10216 | int |
17a2f251 | 10217 | md_parse_option (int c, char *arg) |
252b5132 RH |
10218 | { |
10219 | switch (c) | |
10220 | { | |
119d663a NC |
10221 | case OPTION_CONSTRUCT_FLOATS: |
10222 | mips_disable_float_construction = 0; | |
10223 | break; | |
bdaaa2e1 | 10224 | |
119d663a NC |
10225 | case OPTION_NO_CONSTRUCT_FLOATS: |
10226 | mips_disable_float_construction = 1; | |
10227 | break; | |
bdaaa2e1 | 10228 | |
252b5132 RH |
10229 | case OPTION_TRAP: |
10230 | mips_trap = 1; | |
10231 | break; | |
10232 | ||
10233 | case OPTION_BREAK: | |
10234 | mips_trap = 0; | |
10235 | break; | |
10236 | ||
10237 | case OPTION_EB: | |
10238 | target_big_endian = 1; | |
10239 | break; | |
10240 | ||
10241 | case OPTION_EL: | |
10242 | target_big_endian = 0; | |
10243 | break; | |
10244 | ||
10245 | case 'O': | |
10246 | if (arg && arg[1] == '0') | |
10247 | mips_optimize = 1; | |
10248 | else | |
10249 | mips_optimize = 2; | |
10250 | break; | |
10251 | ||
10252 | case 'g': | |
10253 | if (arg == NULL) | |
10254 | mips_debug = 2; | |
10255 | else | |
10256 | mips_debug = atoi (arg); | |
10257 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10258 | optimizations which limit full symbolic debugging. We take | |
10259 | that to be equivalent to -O0. */ | |
10260 | if (mips_debug == 2) | |
10261 | mips_optimize = 1; | |
10262 | break; | |
10263 | ||
10264 | case OPTION_MIPS1: | |
316f5878 | 10265 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10266 | break; |
10267 | ||
10268 | case OPTION_MIPS2: | |
316f5878 | 10269 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10270 | break; |
10271 | ||
10272 | case OPTION_MIPS3: | |
316f5878 | 10273 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10274 | break; |
10275 | ||
10276 | case OPTION_MIPS4: | |
316f5878 | 10277 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10278 | break; |
10279 | ||
84ea6cf2 | 10280 | case OPTION_MIPS5: |
316f5878 | 10281 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10282 | break; |
10283 | ||
e7af610e | 10284 | case OPTION_MIPS32: |
316f5878 | 10285 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10286 | break; |
10287 | ||
af7ee8bf CD |
10288 | case OPTION_MIPS32R2: |
10289 | file_mips_isa = ISA_MIPS32R2; | |
10290 | break; | |
10291 | ||
5f74bc13 CD |
10292 | case OPTION_MIPS64R2: |
10293 | file_mips_isa = ISA_MIPS64R2; | |
10294 | break; | |
10295 | ||
84ea6cf2 | 10296 | case OPTION_MIPS64: |
316f5878 | 10297 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10298 | break; |
10299 | ||
ec68c924 | 10300 | case OPTION_MTUNE: |
316f5878 RS |
10301 | mips_set_option_string (&mips_tune_string, arg); |
10302 | break; | |
ec68c924 | 10303 | |
316f5878 RS |
10304 | case OPTION_MARCH: |
10305 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10306 | break; |
10307 | ||
10308 | case OPTION_M4650: | |
316f5878 RS |
10309 | mips_set_option_string (&mips_arch_string, "4650"); |
10310 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10311 | break; |
10312 | ||
10313 | case OPTION_NO_M4650: | |
10314 | break; | |
10315 | ||
10316 | case OPTION_M4010: | |
316f5878 RS |
10317 | mips_set_option_string (&mips_arch_string, "4010"); |
10318 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10319 | break; |
10320 | ||
10321 | case OPTION_NO_M4010: | |
10322 | break; | |
10323 | ||
10324 | case OPTION_M4100: | |
316f5878 RS |
10325 | mips_set_option_string (&mips_arch_string, "4100"); |
10326 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10327 | break; |
10328 | ||
10329 | case OPTION_NO_M4100: | |
10330 | break; | |
10331 | ||
252b5132 | 10332 | case OPTION_M3900: |
316f5878 RS |
10333 | mips_set_option_string (&mips_arch_string, "3900"); |
10334 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10335 | break; |
bdaaa2e1 | 10336 | |
252b5132 RH |
10337 | case OPTION_NO_M3900: |
10338 | break; | |
10339 | ||
deec1734 CD |
10340 | case OPTION_MDMX: |
10341 | mips_opts.ase_mdmx = 1; | |
10342 | break; | |
10343 | ||
10344 | case OPTION_NO_MDMX: | |
10345 | mips_opts.ase_mdmx = 0; | |
10346 | break; | |
10347 | ||
252b5132 RH |
10348 | case OPTION_MIPS16: |
10349 | mips_opts.mips16 = 1; | |
b34976b6 | 10350 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10351 | break; |
10352 | ||
10353 | case OPTION_NO_MIPS16: | |
10354 | mips_opts.mips16 = 0; | |
b34976b6 | 10355 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10356 | break; |
10357 | ||
1f25f5d3 CD |
10358 | case OPTION_MIPS3D: |
10359 | mips_opts.ase_mips3d = 1; | |
10360 | break; | |
10361 | ||
10362 | case OPTION_NO_MIPS3D: | |
10363 | mips_opts.ase_mips3d = 0; | |
10364 | break; | |
10365 | ||
d766e8ec RS |
10366 | case OPTION_FIX_VR4120: |
10367 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10368 | break; |
10369 | ||
d766e8ec RS |
10370 | case OPTION_NO_FIX_VR4120: |
10371 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10372 | break; |
10373 | ||
4a6a3df4 AO |
10374 | case OPTION_RELAX_BRANCH: |
10375 | mips_relax_branch = 1; | |
10376 | break; | |
10377 | ||
10378 | case OPTION_NO_RELAX_BRANCH: | |
10379 | mips_relax_branch = 0; | |
10380 | break; | |
10381 | ||
aa6975fb ILT |
10382 | case OPTION_MSHARED: |
10383 | mips_in_shared = TRUE; | |
10384 | break; | |
10385 | ||
10386 | case OPTION_MNO_SHARED: | |
10387 | mips_in_shared = FALSE; | |
10388 | break; | |
10389 | ||
aed1a261 RS |
10390 | case OPTION_MSYM32: |
10391 | mips_opts.sym32 = TRUE; | |
10392 | break; | |
10393 | ||
10394 | case OPTION_MNO_SYM32: | |
10395 | mips_opts.sym32 = FALSE; | |
10396 | break; | |
10397 | ||
0f074f60 | 10398 | #ifdef OBJ_ELF |
252b5132 RH |
10399 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10400 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10401 | intended to be compatible with Irix 5. */ | |
10402 | case OPTION_CALL_SHARED: | |
10403 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10404 | { | |
10405 | as_bad (_("-call_shared is supported only for ELF format")); | |
10406 | return 0; | |
10407 | } | |
10408 | mips_pic = SVR4_PIC; | |
143d77c5 | 10409 | mips_abicalls = TRUE; |
252b5132 RH |
10410 | if (g_switch_seen && g_switch_value != 0) |
10411 | { | |
10412 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10413 | return 0; | |
10414 | } | |
10415 | g_switch_value = 0; | |
10416 | break; | |
10417 | ||
10418 | case OPTION_NON_SHARED: | |
10419 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10420 | { | |
10421 | as_bad (_("-non_shared is supported only for ELF format")); | |
10422 | return 0; | |
10423 | } | |
10424 | mips_pic = NO_PIC; | |
143d77c5 | 10425 | mips_abicalls = FALSE; |
252b5132 RH |
10426 | break; |
10427 | ||
10428 | /* The -xgot option tells the assembler to use 32 offsets when | |
10429 | accessing the got in SVR4_PIC mode. It is for Irix | |
10430 | compatibility. */ | |
10431 | case OPTION_XGOT: | |
10432 | mips_big_got = 1; | |
10433 | break; | |
0f074f60 | 10434 | #endif /* OBJ_ELF */ |
252b5132 RH |
10435 | |
10436 | case 'G': | |
6caf9ef4 TS |
10437 | g_switch_value = atoi (arg); |
10438 | g_switch_seen = 1; | |
10439 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10440 | { |
3e722fb5 | 10441 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10442 | return 0; |
10443 | } | |
252b5132 RH |
10444 | break; |
10445 | ||
0f074f60 | 10446 | #ifdef OBJ_ELF |
34ba82a8 TS |
10447 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10448 | and -mabi=64. */ | |
252b5132 | 10449 | case OPTION_32: |
34ba82a8 TS |
10450 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10451 | { | |
10452 | as_bad (_("-32 is supported for ELF format only")); | |
10453 | return 0; | |
10454 | } | |
316f5878 | 10455 | mips_abi = O32_ABI; |
252b5132 RH |
10456 | break; |
10457 | ||
e013f690 | 10458 | case OPTION_N32: |
34ba82a8 TS |
10459 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10460 | { | |
10461 | as_bad (_("-n32 is supported for ELF format only")); | |
10462 | return 0; | |
10463 | } | |
316f5878 | 10464 | mips_abi = N32_ABI; |
e013f690 | 10465 | break; |
252b5132 | 10466 | |
e013f690 | 10467 | case OPTION_64: |
34ba82a8 TS |
10468 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10469 | { | |
10470 | as_bad (_("-64 is supported for ELF format only")); | |
10471 | return 0; | |
10472 | } | |
316f5878 | 10473 | mips_abi = N64_ABI; |
e013f690 TS |
10474 | if (! support_64bit_objects()) |
10475 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10476 | break; |
ae948b86 | 10477 | #endif /* OBJ_ELF */ |
252b5132 | 10478 | |
c97ef257 | 10479 | case OPTION_GP32: |
a325df1d | 10480 | file_mips_gp32 = 1; |
c97ef257 AH |
10481 | break; |
10482 | ||
10483 | case OPTION_GP64: | |
a325df1d | 10484 | file_mips_gp32 = 0; |
c97ef257 | 10485 | break; |
252b5132 | 10486 | |
ca4e0257 | 10487 | case OPTION_FP32: |
a325df1d | 10488 | file_mips_fp32 = 1; |
316f5878 RS |
10489 | break; |
10490 | ||
10491 | case OPTION_FP64: | |
10492 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10493 | break; |
10494 | ||
ae948b86 | 10495 | #ifdef OBJ_ELF |
252b5132 | 10496 | case OPTION_MABI: |
34ba82a8 TS |
10497 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10498 | { | |
10499 | as_bad (_("-mabi is supported for ELF format only")); | |
10500 | return 0; | |
10501 | } | |
e013f690 | 10502 | if (strcmp (arg, "32") == 0) |
316f5878 | 10503 | mips_abi = O32_ABI; |
e013f690 | 10504 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10505 | mips_abi = O64_ABI; |
e013f690 | 10506 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10507 | mips_abi = N32_ABI; |
e013f690 TS |
10508 | else if (strcmp (arg, "64") == 0) |
10509 | { | |
316f5878 | 10510 | mips_abi = N64_ABI; |
e013f690 TS |
10511 | if (! support_64bit_objects()) |
10512 | as_fatal (_("No compiled in support for 64 bit object file " | |
10513 | "format")); | |
10514 | } | |
10515 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10516 | mips_abi = EABI_ABI; |
e013f690 | 10517 | else |
da0e507f TS |
10518 | { |
10519 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10520 | return 0; | |
10521 | } | |
252b5132 | 10522 | break; |
e013f690 | 10523 | #endif /* OBJ_ELF */ |
252b5132 | 10524 | |
6b76fefe | 10525 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10526 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10527 | break; |
10528 | ||
9ee72ff1 | 10529 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10530 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10531 | break; |
10532 | ||
ecb4347a DJ |
10533 | #ifdef OBJ_ELF |
10534 | case OPTION_MDEBUG: | |
b34976b6 | 10535 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10536 | break; |
10537 | ||
10538 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10539 | mips_flag_mdebug = FALSE; |
ecb4347a | 10540 | break; |
dcd410fe RO |
10541 | |
10542 | case OPTION_PDR: | |
10543 | mips_flag_pdr = TRUE; | |
10544 | break; | |
10545 | ||
10546 | case OPTION_NO_PDR: | |
10547 | mips_flag_pdr = FALSE; | |
10548 | break; | |
ecb4347a DJ |
10549 | #endif /* OBJ_ELF */ |
10550 | ||
252b5132 RH |
10551 | default: |
10552 | return 0; | |
10553 | } | |
10554 | ||
10555 | return 1; | |
10556 | } | |
316f5878 RS |
10557 | \f |
10558 | /* Set up globals to generate code for the ISA or processor | |
10559 | described by INFO. */ | |
252b5132 | 10560 | |
252b5132 | 10561 | static void |
17a2f251 | 10562 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10563 | { |
316f5878 | 10564 | if (info != 0) |
252b5132 | 10565 | { |
fef14a42 TS |
10566 | file_mips_arch = info->cpu; |
10567 | mips_opts.arch = info->cpu; | |
316f5878 | 10568 | mips_opts.isa = info->isa; |
252b5132 | 10569 | } |
252b5132 RH |
10570 | } |
10571 | ||
252b5132 | 10572 | |
316f5878 | 10573 | /* Likewise for tuning. */ |
252b5132 | 10574 | |
316f5878 | 10575 | static void |
17a2f251 | 10576 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10577 | { |
10578 | if (info != 0) | |
fef14a42 | 10579 | mips_tune = info->cpu; |
316f5878 | 10580 | } |
80cc45a5 | 10581 | |
34ba82a8 | 10582 | |
252b5132 | 10583 | void |
17a2f251 | 10584 | mips_after_parse_args (void) |
e9670677 | 10585 | { |
fef14a42 TS |
10586 | const struct mips_cpu_info *arch_info = 0; |
10587 | const struct mips_cpu_info *tune_info = 0; | |
10588 | ||
e9670677 | 10589 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10590 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10591 | { |
6caf9ef4 | 10592 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10593 | as_bad (_("-G not supported in this configuration.")); |
10594 | g_switch_value = 0; | |
10595 | } | |
10596 | ||
cac012d6 AO |
10597 | if (mips_abi == NO_ABI) |
10598 | mips_abi = MIPS_DEFAULT_ABI; | |
10599 | ||
22923709 RS |
10600 | /* The following code determines the architecture and register size. |
10601 | Similar code was added to GCC 3.3 (see override_options() in | |
10602 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10603 | as much as possible. */ | |
e9670677 | 10604 | |
316f5878 | 10605 | if (mips_arch_string != 0) |
fef14a42 | 10606 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10607 | |
316f5878 | 10608 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10609 | { |
316f5878 | 10610 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10611 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10612 | the -march selection (if any). */ |
fef14a42 | 10613 | if (arch_info != 0) |
e9670677 | 10614 | { |
316f5878 RS |
10615 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10616 | There's no harm in specifying both as long as the ISA levels | |
10617 | are the same. */ | |
fef14a42 | 10618 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10619 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10620 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10621 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10622 | } |
316f5878 | 10623 | else |
fef14a42 | 10624 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10625 | } |
10626 | ||
fef14a42 TS |
10627 | if (arch_info == 0) |
10628 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10629 | |
fef14a42 | 10630 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10631 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10632 | arch_info->name); |
10633 | ||
10634 | mips_set_architecture (arch_info); | |
10635 | ||
10636 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10637 | if (mips_tune_string != 0) | |
10638 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10639 | |
fef14a42 TS |
10640 | if (tune_info == 0) |
10641 | mips_set_tune (arch_info); | |
10642 | else | |
10643 | mips_set_tune (tune_info); | |
e9670677 | 10644 | |
316f5878 | 10645 | if (file_mips_gp32 >= 0) |
e9670677 | 10646 | { |
316f5878 RS |
10647 | /* The user specified the size of the integer registers. Make sure |
10648 | it agrees with the ABI and ISA. */ | |
10649 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10650 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10651 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10652 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10653 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10654 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10655 | } |
10656 | else | |
10657 | { | |
316f5878 RS |
10658 | /* Infer the integer register size from the ABI and processor. |
10659 | Restrict ourselves to 32-bit registers if that's all the | |
10660 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10661 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10662 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10663 | } |
10664 | ||
316f5878 RS |
10665 | /* ??? GAS treats single-float processors as though they had 64-bit |
10666 | float registers (although it complains when double-precision | |
10667 | instructions are used). As things stand, saying they have 32-bit | |
10668 | registers would lead to spurious "register must be even" messages. | |
10669 | So here we assume float registers are always the same size as | |
10670 | integer ones, unless the user says otherwise. */ | |
10671 | if (file_mips_fp32 < 0) | |
10672 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10673 | |
316f5878 | 10674 | /* End of GCC-shared inference code. */ |
e9670677 | 10675 | |
17a2f251 TS |
10676 | /* This flag is set when we have a 64-bit capable CPU but use only |
10677 | 32-bit wide registers. Note that EABI does not use it. */ | |
10678 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10679 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10680 | || mips_abi == O32_ABI)) | |
316f5878 | 10681 | mips_32bitmode = 1; |
e9670677 MR |
10682 | |
10683 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10684 | as_bad (_("trap exception not supported at ISA 1")); | |
10685 | ||
e9670677 MR |
10686 | /* If the selected architecture includes support for ASEs, enable |
10687 | generation of code for them. */ | |
a4672219 | 10688 | if (mips_opts.mips16 == -1) |
fef14a42 | 10689 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10690 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10691 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10692 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10693 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10694 | |
e9670677 | 10695 | file_mips_isa = mips_opts.isa; |
a4672219 | 10696 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10697 | file_ase_mips3d = mips_opts.ase_mips3d; |
10698 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10699 | mips_opts.gp32 = file_mips_gp32; | |
10700 | mips_opts.fp32 = file_mips_fp32; | |
10701 | ||
ecb4347a DJ |
10702 | if (mips_flag_mdebug < 0) |
10703 | { | |
10704 | #ifdef OBJ_MAYBE_ECOFF | |
10705 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10706 | mips_flag_mdebug = 1; | |
10707 | else | |
10708 | #endif /* OBJ_MAYBE_ECOFF */ | |
10709 | mips_flag_mdebug = 0; | |
10710 | } | |
e9670677 MR |
10711 | } |
10712 | \f | |
10713 | void | |
17a2f251 | 10714 | mips_init_after_args (void) |
252b5132 RH |
10715 | { |
10716 | /* initialize opcodes */ | |
10717 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10718 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10719 | } |
10720 | ||
10721 | long | |
17a2f251 | 10722 | md_pcrel_from (fixS *fixP) |
252b5132 | 10723 | { |
a7ebbfdf TS |
10724 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10725 | switch (fixP->fx_r_type) | |
10726 | { | |
10727 | case BFD_RELOC_16_PCREL_S2: | |
10728 | case BFD_RELOC_MIPS_JMP: | |
10729 | /* Return the address of the delay slot. */ | |
10730 | return addr + 4; | |
10731 | default: | |
10732 | return addr; | |
10733 | } | |
252b5132 RH |
10734 | } |
10735 | ||
252b5132 RH |
10736 | /* This is called before the symbol table is processed. In order to |
10737 | work with gcc when using mips-tfile, we must keep all local labels. | |
10738 | However, in other cases, we want to discard them. If we were | |
10739 | called with -g, but we didn't see any debugging information, it may | |
10740 | mean that gcc is smuggling debugging information through to | |
10741 | mips-tfile, in which case we must generate all local labels. */ | |
10742 | ||
10743 | void | |
17a2f251 | 10744 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10745 | { |
10746 | #ifndef NO_ECOFF_DEBUGGING | |
10747 | if (ECOFF_DEBUGGING | |
10748 | && mips_debug != 0 | |
10749 | && ! ecoff_debugging_seen) | |
10750 | flag_keep_locals = 1; | |
10751 | #endif | |
10752 | } | |
10753 | ||
3b91255e RS |
10754 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10755 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10756 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10757 | relocation operators. | |
10758 | ||
10759 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10760 | expression if: | |
10761 | ||
10762 | (a) it refers to the same symbol; and | |
10763 | (b) the offset applied in the %lo() expression is no lower than | |
10764 | the offset applied in the %got() or %hi(). | |
10765 | ||
10766 | (b) allows us to cope with code like: | |
10767 | ||
10768 | lui $4,%hi(foo) | |
10769 | lh $4,%lo(foo+2)($4) | |
10770 | ||
10771 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10772 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10773 | the high 16 bits. | |
10774 | ||
10775 | When several %lo()s match a particular %got() or %hi(), we use the | |
10776 | following rules to distinguish them: | |
10777 | ||
10778 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10779 | higher offsets. | |
10780 | ||
10781 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10782 | that already have a matching %got() or %hi(). | |
10783 | ||
10784 | (3) later %lo()s are better than earlier %lo()s. | |
10785 | ||
10786 | These rules are applied in order. | |
10787 | ||
10788 | (1) means, among other things, that %lo()s with identical offsets are | |
10789 | chosen if they exist. | |
10790 | ||
10791 | (2) means that we won't associate several high-part relocations with | |
10792 | the same low-part relocation unless there's no alternative. Having | |
10793 | several high parts for the same low part is a GNU extension; this rule | |
10794 | allows careful users to avoid it. | |
10795 | ||
10796 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10797 | with the last high-part relocation being at the front of the list. | |
10798 | It therefore makes sense to choose the last matching low-part | |
10799 | relocation, all other things being equal. It's also easier | |
10800 | to code that way. */ | |
252b5132 RH |
10801 | |
10802 | void | |
17a2f251 | 10803 | mips_frob_file (void) |
252b5132 RH |
10804 | { |
10805 | struct mips_hi_fixup *l; | |
10806 | ||
10807 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10808 | { | |
10809 | segment_info_type *seginfo; | |
3b91255e RS |
10810 | bfd_boolean matched_lo_p; |
10811 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10812 | |
5919d012 | 10813 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10814 | |
5919d012 RS |
10815 | /* If a GOT16 relocation turns out to be against a global symbol, |
10816 | there isn't supposed to be a matching LO. */ | |
10817 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10818 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10819 | continue; | |
10820 | ||
10821 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10822 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10823 | continue; |
10824 | ||
252b5132 | 10825 | seginfo = seg_info (l->seg); |
252b5132 | 10826 | |
3b91255e RS |
10827 | /* Set HI_POS to the position of this relocation in the chain. |
10828 | Set LO_POS to the position of the chosen low-part relocation. | |
10829 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10830 | relocation that matches an immediately-preceding high-part | |
10831 | relocation. */ | |
10832 | hi_pos = NULL; | |
10833 | lo_pos = NULL; | |
10834 | matched_lo_p = FALSE; | |
10835 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10836 | { | |
10837 | if (*pos == l->fixp) | |
10838 | hi_pos = pos; | |
10839 | ||
10840 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10841 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10842 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10843 | && (lo_pos == NULL | |
10844 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10845 | || (!matched_lo_p | |
10846 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10847 | lo_pos = pos; | |
10848 | ||
10849 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10850 | && fixup_has_matching_lo_p (*pos)); | |
10851 | } | |
10852 | ||
10853 | /* If we found a match, remove the high-part relocation from its | |
10854 | current position and insert it before the low-part relocation. | |
10855 | Make the offsets match so that fixup_has_matching_lo_p() | |
10856 | will return true. | |
10857 | ||
10858 | We don't warn about unmatched high-part relocations since some | |
10859 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10860 | instructions. */ | |
10861 | if (lo_pos != NULL) | |
10862 | { | |
10863 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10864 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10865 | { |
3b91255e RS |
10866 | *hi_pos = l->fixp->fx_next; |
10867 | l->fixp->fx_next = *lo_pos; | |
10868 | *lo_pos = l->fixp; | |
252b5132 | 10869 | } |
252b5132 RH |
10870 | } |
10871 | } | |
10872 | } | |
10873 | ||
3e722fb5 | 10874 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10875 | We have to prevent gas from dropping them. */ |
252b5132 | 10876 | |
252b5132 | 10877 | int |
17a2f251 | 10878 | mips_force_relocation (fixS *fixp) |
252b5132 | 10879 | { |
ae6063d4 | 10880 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10881 | return 1; |
10882 | ||
f6688943 TS |
10883 | if (HAVE_NEWABI |
10884 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10885 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10886 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10887 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10888 | return 1; | |
10889 | ||
3e722fb5 | 10890 | return 0; |
252b5132 RH |
10891 | } |
10892 | ||
45f8dfe8 AO |
10893 | /* This hook is called before a fix is simplified. We don't really |
10894 | decide whether to skip a fix here. Rather, we turn global symbols | |
10895 | used as branch targets into local symbols, such that they undergo | |
10896 | simplification. We can only do this if the symbol is defined and | |
10897 | it is in the same section as the branch. If this doesn't hold, we | |
10898 | emit a better error message than just saying the relocation is not | |
10899 | valid for the selected object format. | |
10900 | ||
10901 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10902 | segment in which the fix up occurs. The return value should be | |
10903 | non-zero to indicate the fix-up is valid for further | |
10904 | simplifications. */ | |
10905 | ||
10906 | int | |
17a2f251 | 10907 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10908 | { |
10909 | /* There's a lot of discussion on whether it should be possible to | |
10910 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10911 | seems to be that it can, but gas/bfd are very broken in creating | |
10912 | RELA relocations for this, so for now we only accept branches to | |
10913 | symbols in the same section. Anything else is of dubious value, | |
10914 | since there's no guarantee that at link time the symbol would be | |
10915 | in range. Even for branches to local symbols this is arguably | |
10916 | wrong, since it we assume the symbol is not going to be | |
10917 | overridden, which should be possible per ELF library semantics, | |
10918 | but then, there isn't a dynamic relocation that could be used to | |
10919 | this effect, and the target would likely be out of range as well. | |
10920 | ||
10921 | Unfortunately, it seems that there is too much code out there | |
10922 | that relies on branches to symbols that are global to be resolved | |
10923 | as if they were local, like the IRIX tools do, so we do it as | |
10924 | well, but with a warning so that people are reminded to fix their | |
10925 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10926 | targets, this entire block should go away (and probably the | |
10927 | whole function). */ | |
10928 | ||
10929 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10930 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10931 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10932 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10933 | && fixP->fx_addsy) | |
10934 | { | |
10935 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10936 | { | |
10937 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10938 | _("Cannot branch to undefined symbol.")); | |
10939 | /* Avoid any further errors about this fixup. */ | |
10940 | fixP->fx_done = 1; | |
10941 | } | |
10942 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10943 | { | |
10944 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10945 | _("Cannot branch to symbol in another section.")); | |
10946 | fixP->fx_done = 1; | |
10947 | } | |
10948 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10949 | { | |
10950 | symbolS *sym = fixP->fx_addsy; | |
10951 | ||
115695a8 CD |
10952 | if (mips_pic == SVR4_PIC) |
10953 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10954 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10955 | |
10956 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10957 | S_GET_SEGMENT (sym), | |
10958 | S_GET_VALUE (sym), | |
10959 | symbol_get_frag (sym)); | |
10960 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10961 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10962 | assert (symbol_resolved_p (sym)); | |
10963 | symbol_mark_resolved (fixP->fx_addsy); | |
10964 | } | |
10965 | } | |
10966 | ||
10967 | return 1; | |
10968 | } | |
10969 | ||
252b5132 RH |
10970 | /* Apply a fixup to the object file. */ |
10971 | ||
94f592af | 10972 | void |
17a2f251 | 10973 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10974 | { |
874e8986 | 10975 | bfd_byte *buf; |
98aa84af | 10976 | long insn; |
a7ebbfdf | 10977 | reloc_howto_type *howto; |
252b5132 | 10978 | |
a7ebbfdf TS |
10979 | /* We ignore generic BFD relocations we don't know about. */ |
10980 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10981 | if (! howto) | |
10982 | return; | |
65551fa4 | 10983 | |
252b5132 RH |
10984 | assert (fixP->fx_size == 4 |
10985 | || fixP->fx_r_type == BFD_RELOC_16 | |
10986 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10987 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10988 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10989 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10990 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10991 | |
a7ebbfdf | 10992 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10993 | |
3e722fb5 | 10994 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10995 | |
10996 | /* Don't treat parts of a composite relocation as done. There are two | |
10997 | reasons for this: | |
10998 | ||
10999 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11000 | should nevertheless be emitted if the first part is. | |
11001 | ||
11002 | (2) In normal usage, composite relocations are never assembly-time | |
11003 | constants. The easiest way of dealing with the pathological | |
11004 | exceptions is to generate a relocation against STN_UNDEF and | |
11005 | leave everything up to the linker. */ | |
11006 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
11007 | fixP->fx_done = 1; |
11008 | ||
11009 | switch (fixP->fx_r_type) | |
11010 | { | |
3f98094e DJ |
11011 | case BFD_RELOC_MIPS_TLS_GD: |
11012 | case BFD_RELOC_MIPS_TLS_LDM: | |
11013 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11014 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11015 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11016 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11017 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11018 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11019 | /* fall through */ | |
11020 | ||
252b5132 | 11021 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11022 | case BFD_RELOC_MIPS_SHIFT5: |
11023 | case BFD_RELOC_MIPS_SHIFT6: | |
11024 | case BFD_RELOC_MIPS_GOT_DISP: | |
11025 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11026 | case BFD_RELOC_MIPS_GOT_OFST: | |
11027 | case BFD_RELOC_MIPS_SUB: | |
11028 | case BFD_RELOC_MIPS_INSERT_A: | |
11029 | case BFD_RELOC_MIPS_INSERT_B: | |
11030 | case BFD_RELOC_MIPS_DELETE: | |
11031 | case BFD_RELOC_MIPS_HIGHEST: | |
11032 | case BFD_RELOC_MIPS_HIGHER: | |
11033 | case BFD_RELOC_MIPS_SCN_DISP: | |
11034 | case BFD_RELOC_MIPS_REL16: | |
11035 | case BFD_RELOC_MIPS_RELGOT: | |
11036 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11037 | case BFD_RELOC_HI16: |
11038 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11039 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11040 | case BFD_RELOC_MIPS_LITERAL: |
11041 | case BFD_RELOC_MIPS_CALL16: | |
11042 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11043 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11044 | case BFD_RELOC_MIPS_GOT_HI16: |
11045 | case BFD_RELOC_MIPS_GOT_LO16: | |
11046 | case BFD_RELOC_MIPS_CALL_HI16: | |
11047 | case BFD_RELOC_MIPS_CALL_LO16: | |
11048 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11049 | case BFD_RELOC_MIPS16_HI16: |
11050 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 11051 | assert (! fixP->fx_pcrel); |
252b5132 RH |
11052 | /* Nothing needed to do. The value comes from the reloc entry */ |
11053 | break; | |
11054 | ||
11055 | case BFD_RELOC_MIPS16_JMP: | |
11056 | /* We currently always generate a reloc against a symbol, which | |
11057 | means that we don't want an addend even if the symbol is | |
11058 | defined. */ | |
a7ebbfdf | 11059 | *valP = 0; |
252b5132 RH |
11060 | break; |
11061 | ||
252b5132 RH |
11062 | case BFD_RELOC_64: |
11063 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11064 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11065 | if (fixP->fx_done) |
252b5132 RH |
11066 | { |
11067 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11068 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11069 | else |
11070 | { | |
a7ebbfdf | 11071 | valueT hiv; |
252b5132 | 11072 | |
a7ebbfdf | 11073 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11074 | hiv = 0xffffffff; |
11075 | else | |
11076 | hiv = 0; | |
a7ebbfdf TS |
11077 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11078 | *valP, 4); | |
11079 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11080 | hiv, 4); | |
252b5132 RH |
11081 | } |
11082 | } | |
11083 | break; | |
11084 | ||
056350c6 | 11085 | case BFD_RELOC_RVA: |
252b5132 RH |
11086 | case BFD_RELOC_32: |
11087 | /* If we are deleting this reloc entry, we must fill in the | |
11088 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11089 | resolved when it appears but is later defined. */ |
11090 | if (fixP->fx_done) | |
2132e3a3 | 11091 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11092 | break; |
11093 | ||
11094 | case BFD_RELOC_16: | |
11095 | /* If we are deleting this reloc entry, we must fill in the | |
11096 | value now. */ | |
252b5132 | 11097 | if (fixP->fx_done) |
2132e3a3 | 11098 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11099 | break; |
11100 | ||
11101 | case BFD_RELOC_LO16: | |
d6f16593 | 11102 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11103 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11104 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11105 | /* When handling an embedded PIC switch statement, we can wind |
11106 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11107 | if (fixP->fx_done) | |
11108 | { | |
a7ebbfdf | 11109 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11110 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11111 | _("relocation overflow")); | |
252b5132 RH |
11112 | if (target_big_endian) |
11113 | buf += 2; | |
2132e3a3 | 11114 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11115 | } |
11116 | break; | |
11117 | ||
11118 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11119 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11120 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11121 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11122 | |
252b5132 RH |
11123 | /* |
11124 | * We need to save the bits in the instruction since fixup_segment() | |
11125 | * might be deleting the relocation entry (i.e., a branch within | |
11126 | * the current segment). | |
11127 | */ | |
a7ebbfdf | 11128 | if (! fixP->fx_done) |
bb2d6cd7 | 11129 | break; |
252b5132 RH |
11130 | |
11131 | /* update old instruction data */ | |
252b5132 RH |
11132 | if (target_big_endian) |
11133 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11134 | else | |
11135 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11136 | ||
a7ebbfdf TS |
11137 | if (*valP + 0x20000 <= 0x3ffff) |
11138 | { | |
11139 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11140 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11141 | } |
11142 | else if (mips_pic == NO_PIC | |
11143 | && fixP->fx_done | |
11144 | && fixP->fx_frag->fr_address >= text_section->vma | |
11145 | && (fixP->fx_frag->fr_address | |
587aac4e | 11146 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11147 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11148 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11149 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11150 | { |
11151 | /* The branch offset is too large. If this is an | |
11152 | unconditional branch, and we are not generating PIC code, | |
11153 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11154 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11155 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11156 | else |
a7ebbfdf TS |
11157 | insn = 0x08000000; /* j */ |
11158 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11159 | fixP->fx_done = 0; | |
11160 | fixP->fx_addsy = section_symbol (text_section); | |
11161 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11162 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11163 | } |
11164 | else | |
11165 | { | |
11166 | /* If we got here, we have branch-relaxation disabled, | |
11167 | and there's nothing we can do to fix this instruction | |
11168 | without turning it into a longer sequence. */ | |
11169 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11170 | _("Branch out of range")); | |
252b5132 | 11171 | } |
252b5132 RH |
11172 | break; |
11173 | ||
11174 | case BFD_RELOC_VTABLE_INHERIT: | |
11175 | fixP->fx_done = 0; | |
11176 | if (fixP->fx_addsy | |
11177 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11178 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11179 | S_SET_WEAK (fixP->fx_addsy); | |
11180 | break; | |
11181 | ||
11182 | case BFD_RELOC_VTABLE_ENTRY: | |
11183 | fixP->fx_done = 0; | |
11184 | break; | |
11185 | ||
11186 | default: | |
11187 | internalError (); | |
11188 | } | |
a7ebbfdf TS |
11189 | |
11190 | /* Remember value for tc_gen_reloc. */ | |
11191 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11192 | } |
11193 | ||
252b5132 | 11194 | static symbolS * |
17a2f251 | 11195 | get_symbol (void) |
252b5132 RH |
11196 | { |
11197 | int c; | |
11198 | char *name; | |
11199 | symbolS *p; | |
11200 | ||
11201 | name = input_line_pointer; | |
11202 | c = get_symbol_end (); | |
11203 | p = (symbolS *) symbol_find_or_make (name); | |
11204 | *input_line_pointer = c; | |
11205 | return p; | |
11206 | } | |
11207 | ||
11208 | /* Align the current frag to a given power of two. The MIPS assembler | |
11209 | also automatically adjusts any preceding label. */ | |
11210 | ||
11211 | static void | |
17a2f251 | 11212 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11213 | { |
b34976b6 | 11214 | mips_emit_delays (FALSE); |
252b5132 RH |
11215 | frag_align (to, fill, 0); |
11216 | record_alignment (now_seg, to); | |
11217 | if (label != NULL) | |
11218 | { | |
11219 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11220 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11221 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11222 | } | |
11223 | } | |
11224 | ||
11225 | /* Align to a given power of two. .align 0 turns off the automatic | |
11226 | alignment used by the data creating pseudo-ops. */ | |
11227 | ||
11228 | static void | |
17a2f251 | 11229 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11230 | { |
11231 | register int temp; | |
11232 | register long temp_fill; | |
11233 | long max_alignment = 15; | |
11234 | ||
11235 | /* | |
11236 | ||
67c1ffbe | 11237 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11238 | to the aligned address. |
11239 | o It's not documented but auto alignment is reinstated by | |
11240 | a .align pseudo instruction. | |
11241 | o Note also that after auto alignment is turned off the mips assembler | |
11242 | issues an error on attempt to assemble an improperly aligned data item. | |
11243 | We don't. | |
11244 | ||
11245 | */ | |
11246 | ||
11247 | temp = get_absolute_expression (); | |
11248 | if (temp > max_alignment) | |
11249 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11250 | else if (temp < 0) | |
11251 | { | |
11252 | as_warn (_("Alignment negative: 0 assumed.")); | |
11253 | temp = 0; | |
11254 | } | |
11255 | if (*input_line_pointer == ',') | |
11256 | { | |
f9419b05 | 11257 | ++input_line_pointer; |
252b5132 RH |
11258 | temp_fill = get_absolute_expression (); |
11259 | } | |
11260 | else | |
11261 | temp_fill = 0; | |
11262 | if (temp) | |
11263 | { | |
11264 | auto_align = 1; | |
11265 | mips_align (temp, (int) temp_fill, | |
11266 | insn_labels != NULL ? insn_labels->label : NULL); | |
11267 | } | |
11268 | else | |
11269 | { | |
11270 | auto_align = 0; | |
11271 | } | |
11272 | ||
11273 | demand_empty_rest_of_line (); | |
11274 | } | |
11275 | ||
11276 | void | |
17a2f251 | 11277 | mips_flush_pending_output (void) |
252b5132 | 11278 | { |
b34976b6 | 11279 | mips_emit_delays (FALSE); |
252b5132 RH |
11280 | mips_clear_insn_labels (); |
11281 | } | |
11282 | ||
11283 | static void | |
17a2f251 | 11284 | s_change_sec (int sec) |
252b5132 RH |
11285 | { |
11286 | segT seg; | |
11287 | ||
252b5132 RH |
11288 | #ifdef OBJ_ELF |
11289 | /* The ELF backend needs to know that we are changing sections, so | |
11290 | that .previous works correctly. We could do something like check | |
b6ff326e | 11291 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11292 | as it would not be appropriate to use it in the section changing |
11293 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11294 | This should be cleaner, somehow. */ | |
11295 | obj_elf_section_change_hook (); | |
11296 | #endif | |
11297 | ||
b34976b6 | 11298 | mips_emit_delays (FALSE); |
252b5132 RH |
11299 | switch (sec) |
11300 | { | |
11301 | case 't': | |
11302 | s_text (0); | |
11303 | break; | |
11304 | case 'd': | |
11305 | s_data (0); | |
11306 | break; | |
11307 | case 'b': | |
11308 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11309 | demand_empty_rest_of_line (); | |
11310 | break; | |
11311 | ||
11312 | case 'r': | |
4d0d148d TS |
11313 | seg = subseg_new (RDATA_SECTION_NAME, |
11314 | (subsegT) get_absolute_expression ()); | |
11315 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11316 | { |
4d0d148d TS |
11317 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11318 | | SEC_READONLY | SEC_RELOC | |
11319 | | SEC_DATA)); | |
11320 | if (strcmp (TARGET_OS, "elf") != 0) | |
11321 | record_alignment (seg, 4); | |
252b5132 | 11322 | } |
4d0d148d | 11323 | demand_empty_rest_of_line (); |
252b5132 RH |
11324 | break; |
11325 | ||
11326 | case 's': | |
4d0d148d TS |
11327 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11328 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11329 | { |
4d0d148d TS |
11330 | bfd_set_section_flags (stdoutput, seg, |
11331 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11332 | if (strcmp (TARGET_OS, "elf") != 0) | |
11333 | record_alignment (seg, 4); | |
252b5132 | 11334 | } |
4d0d148d TS |
11335 | demand_empty_rest_of_line (); |
11336 | break; | |
252b5132 RH |
11337 | } |
11338 | ||
11339 | auto_align = 1; | |
11340 | } | |
b34976b6 | 11341 | |
cca86cc8 | 11342 | void |
17a2f251 | 11343 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11344 | { |
7ed4a06a | 11345 | #ifdef OBJ_ELF |
cca86cc8 SC |
11346 | char *section_name; |
11347 | char c; | |
684022ea | 11348 | char next_c = 0; |
cca86cc8 SC |
11349 | int section_type; |
11350 | int section_flag; | |
11351 | int section_entry_size; | |
11352 | int section_alignment; | |
b34976b6 | 11353 | |
7ed4a06a TS |
11354 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11355 | return; | |
11356 | ||
cca86cc8 SC |
11357 | section_name = input_line_pointer; |
11358 | c = get_symbol_end (); | |
a816d1ed AO |
11359 | if (c) |
11360 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11361 | |
4cf0dd0d TS |
11362 | /* Do we have .section Name<,"flags">? */ |
11363 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11364 | { |
4cf0dd0d TS |
11365 | /* just after name is now '\0'. */ |
11366 | *input_line_pointer = c; | |
cca86cc8 SC |
11367 | input_line_pointer = section_name; |
11368 | obj_elf_section (ignore); | |
11369 | return; | |
11370 | } | |
11371 | input_line_pointer++; | |
11372 | ||
11373 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11374 | if (c == ',') | |
11375 | section_type = get_absolute_expression (); | |
11376 | else | |
11377 | section_type = 0; | |
11378 | if (*input_line_pointer++ == ',') | |
11379 | section_flag = get_absolute_expression (); | |
11380 | else | |
11381 | section_flag = 0; | |
11382 | if (*input_line_pointer++ == ',') | |
11383 | section_entry_size = get_absolute_expression (); | |
11384 | else | |
11385 | section_entry_size = 0; | |
11386 | if (*input_line_pointer++ == ',') | |
11387 | section_alignment = get_absolute_expression (); | |
11388 | else | |
11389 | section_alignment = 0; | |
11390 | ||
a816d1ed AO |
11391 | section_name = xstrdup (section_name); |
11392 | ||
8ab8a5c8 RS |
11393 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11394 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11395 | traditionally had to fall back on the more common @progbits instead. | |
11396 | ||
11397 | There's nothing really harmful in this, since bfd will correct | |
11398 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11399 | means that, for backwards compatibiltiy, the special_section entries | |
11400 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11401 | ||
11402 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11403 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11404 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11405 | generic type-checking code. */ | |
11406 | if (section_type == SHT_MIPS_DWARF) | |
11407 | section_type = SHT_PROGBITS; | |
11408 | ||
cca86cc8 SC |
11409 | obj_elf_change_section (section_name, section_type, section_flag, |
11410 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11411 | |
11412 | if (now_seg->name != section_name) | |
11413 | free (section_name); | |
7ed4a06a | 11414 | #endif /* OBJ_ELF */ |
cca86cc8 | 11415 | } |
252b5132 RH |
11416 | |
11417 | void | |
17a2f251 | 11418 | mips_enable_auto_align (void) |
252b5132 RH |
11419 | { |
11420 | auto_align = 1; | |
11421 | } | |
11422 | ||
11423 | static void | |
17a2f251 | 11424 | s_cons (int log_size) |
252b5132 RH |
11425 | { |
11426 | symbolS *label; | |
11427 | ||
11428 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11429 | mips_emit_delays (FALSE); |
252b5132 RH |
11430 | if (log_size > 0 && auto_align) |
11431 | mips_align (log_size, 0, label); | |
11432 | mips_clear_insn_labels (); | |
11433 | cons (1 << log_size); | |
11434 | } | |
11435 | ||
11436 | static void | |
17a2f251 | 11437 | s_float_cons (int type) |
252b5132 RH |
11438 | { |
11439 | symbolS *label; | |
11440 | ||
11441 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11442 | ||
b34976b6 | 11443 | mips_emit_delays (FALSE); |
252b5132 RH |
11444 | |
11445 | if (auto_align) | |
49309057 ILT |
11446 | { |
11447 | if (type == 'd') | |
11448 | mips_align (3, 0, label); | |
11449 | else | |
11450 | mips_align (2, 0, label); | |
11451 | } | |
252b5132 RH |
11452 | |
11453 | mips_clear_insn_labels (); | |
11454 | ||
11455 | float_cons (type); | |
11456 | } | |
11457 | ||
11458 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11459 | permitted to say | |
11460 | .globl foo .text | |
11461 | where foo is an undefined symbol, to mean that foo should be | |
11462 | considered to be the address of a function. */ | |
11463 | ||
11464 | static void | |
17a2f251 | 11465 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11466 | { |
11467 | char *name; | |
11468 | int c; | |
11469 | symbolS *symbolP; | |
11470 | flagword flag; | |
11471 | ||
11472 | name = input_line_pointer; | |
11473 | c = get_symbol_end (); | |
11474 | symbolP = symbol_find_or_make (name); | |
11475 | *input_line_pointer = c; | |
11476 | SKIP_WHITESPACE (); | |
11477 | ||
11478 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11479 | being a function is apparently labelled as being an object. */ | |
11480 | flag = BSF_OBJECT; | |
11481 | ||
11482 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11483 | { | |
11484 | char *secname; | |
11485 | asection *sec; | |
11486 | ||
11487 | secname = input_line_pointer; | |
11488 | c = get_symbol_end (); | |
11489 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11490 | if (sec == NULL) | |
11491 | as_bad (_("%s: no such section"), secname); | |
11492 | *input_line_pointer = c; | |
11493 | ||
11494 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11495 | flag = BSF_FUNCTION; | |
11496 | } | |
11497 | ||
49309057 | 11498 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11499 | |
11500 | S_SET_EXTERNAL (symbolP); | |
11501 | demand_empty_rest_of_line (); | |
11502 | } | |
11503 | ||
11504 | static void | |
17a2f251 | 11505 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11506 | { |
11507 | char *opt; | |
11508 | char c; | |
11509 | ||
11510 | opt = input_line_pointer; | |
11511 | c = get_symbol_end (); | |
11512 | ||
11513 | if (*opt == 'O') | |
11514 | { | |
11515 | /* FIXME: What does this mean? */ | |
11516 | } | |
11517 | else if (strncmp (opt, "pic", 3) == 0) | |
11518 | { | |
11519 | int i; | |
11520 | ||
11521 | i = atoi (opt + 3); | |
11522 | if (i == 0) | |
11523 | mips_pic = NO_PIC; | |
11524 | else if (i == 2) | |
143d77c5 | 11525 | { |
252b5132 | 11526 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11527 | mips_abicalls = TRUE; |
11528 | } | |
252b5132 RH |
11529 | else |
11530 | as_bad (_(".option pic%d not supported"), i); | |
11531 | ||
4d0d148d | 11532 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11533 | { |
11534 | if (g_switch_seen && g_switch_value != 0) | |
11535 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11536 | g_switch_value = 0; | |
11537 | bfd_set_gp_size (stdoutput, 0); | |
11538 | } | |
11539 | } | |
11540 | else | |
11541 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11542 | ||
11543 | *input_line_pointer = c; | |
11544 | demand_empty_rest_of_line (); | |
11545 | } | |
11546 | ||
11547 | /* This structure is used to hold a stack of .set values. */ | |
11548 | ||
e972090a NC |
11549 | struct mips_option_stack |
11550 | { | |
252b5132 RH |
11551 | struct mips_option_stack *next; |
11552 | struct mips_set_options options; | |
11553 | }; | |
11554 | ||
11555 | static struct mips_option_stack *mips_opts_stack; | |
11556 | ||
11557 | /* Handle the .set pseudo-op. */ | |
11558 | ||
11559 | static void | |
17a2f251 | 11560 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11561 | { |
11562 | char *name = input_line_pointer, ch; | |
11563 | ||
11564 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11565 | ++input_line_pointer; |
252b5132 RH |
11566 | ch = *input_line_pointer; |
11567 | *input_line_pointer = '\0'; | |
11568 | ||
11569 | if (strcmp (name, "reorder") == 0) | |
11570 | { | |
11571 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11572 | { | |
11573 | /* If we still have pending nops, we can discard them. The | |
11574 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11575 | needed. */ |
252b5132 RH |
11576 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11577 | * (mips_opts.mips16 ? 2 : 4)); | |
11578 | prev_nop_frag = NULL; | |
11579 | } | |
11580 | mips_opts.noreorder = 0; | |
11581 | } | |
11582 | else if (strcmp (name, "noreorder") == 0) | |
11583 | { | |
b34976b6 | 11584 | mips_emit_delays (TRUE); |
252b5132 RH |
11585 | mips_opts.noreorder = 1; |
11586 | mips_any_noreorder = 1; | |
11587 | } | |
11588 | else if (strcmp (name, "at") == 0) | |
11589 | { | |
11590 | mips_opts.noat = 0; | |
11591 | } | |
11592 | else if (strcmp (name, "noat") == 0) | |
11593 | { | |
11594 | mips_opts.noat = 1; | |
11595 | } | |
11596 | else if (strcmp (name, "macro") == 0) | |
11597 | { | |
11598 | mips_opts.warn_about_macros = 0; | |
11599 | } | |
11600 | else if (strcmp (name, "nomacro") == 0) | |
11601 | { | |
11602 | if (mips_opts.noreorder == 0) | |
11603 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11604 | mips_opts.warn_about_macros = 1; | |
11605 | } | |
11606 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11607 | { | |
11608 | mips_opts.nomove = 0; | |
11609 | } | |
11610 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11611 | { | |
11612 | mips_opts.nomove = 1; | |
11613 | } | |
11614 | else if (strcmp (name, "bopt") == 0) | |
11615 | { | |
11616 | mips_opts.nobopt = 0; | |
11617 | } | |
11618 | else if (strcmp (name, "nobopt") == 0) | |
11619 | { | |
11620 | mips_opts.nobopt = 1; | |
11621 | } | |
11622 | else if (strcmp (name, "mips16") == 0 | |
11623 | || strcmp (name, "MIPS-16") == 0) | |
11624 | mips_opts.mips16 = 1; | |
11625 | else if (strcmp (name, "nomips16") == 0 | |
11626 | || strcmp (name, "noMIPS-16") == 0) | |
11627 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11628 | else if (strcmp (name, "mips3d") == 0) |
11629 | mips_opts.ase_mips3d = 1; | |
11630 | else if (strcmp (name, "nomips3d") == 0) | |
11631 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11632 | else if (strcmp (name, "mdmx") == 0) |
11633 | mips_opts.ase_mdmx = 1; | |
11634 | else if (strcmp (name, "nomdmx") == 0) | |
11635 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11636 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11637 | { |
af7ee8bf | 11638 | int reset = 0; |
252b5132 | 11639 | |
1a2c1fad CD |
11640 | /* Permit the user to change the ISA and architecture on the fly. |
11641 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11642 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11643 | { |
11644 | reset = 1; | |
11645 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11646 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11647 | } |
11648 | else if (strncmp (name, "arch=", 5) == 0) | |
11649 | { | |
11650 | const struct mips_cpu_info *p; | |
11651 | ||
11652 | p = mips_parse_cpu("internal use", name + 5); | |
11653 | if (!p) | |
11654 | as_bad (_("unknown architecture %s"), name + 5); | |
11655 | else | |
11656 | { | |
11657 | mips_opts.arch = p->cpu; | |
11658 | mips_opts.isa = p->isa; | |
11659 | } | |
11660 | } | |
81a21e38 TS |
11661 | else if (strncmp (name, "mips", 4) == 0) |
11662 | { | |
11663 | const struct mips_cpu_info *p; | |
11664 | ||
11665 | p = mips_parse_cpu("internal use", name); | |
11666 | if (!p) | |
11667 | as_bad (_("unknown ISA level %s"), name + 4); | |
11668 | else | |
11669 | { | |
11670 | mips_opts.arch = p->cpu; | |
11671 | mips_opts.isa = p->isa; | |
11672 | } | |
11673 | } | |
af7ee8bf | 11674 | else |
81a21e38 | 11675 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11676 | |
11677 | switch (mips_opts.isa) | |
98d3f06f KH |
11678 | { |
11679 | case 0: | |
98d3f06f | 11680 | break; |
af7ee8bf CD |
11681 | case ISA_MIPS1: |
11682 | case ISA_MIPS2: | |
11683 | case ISA_MIPS32: | |
11684 | case ISA_MIPS32R2: | |
98d3f06f KH |
11685 | mips_opts.gp32 = 1; |
11686 | mips_opts.fp32 = 1; | |
11687 | break; | |
af7ee8bf CD |
11688 | case ISA_MIPS3: |
11689 | case ISA_MIPS4: | |
11690 | case ISA_MIPS5: | |
11691 | case ISA_MIPS64: | |
5f74bc13 | 11692 | case ISA_MIPS64R2: |
98d3f06f KH |
11693 | mips_opts.gp32 = 0; |
11694 | mips_opts.fp32 = 0; | |
11695 | break; | |
11696 | default: | |
11697 | as_bad (_("unknown ISA level %s"), name + 4); | |
11698 | break; | |
11699 | } | |
af7ee8bf | 11700 | if (reset) |
98d3f06f | 11701 | { |
af7ee8bf CD |
11702 | mips_opts.gp32 = file_mips_gp32; |
11703 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11704 | } |
252b5132 RH |
11705 | } |
11706 | else if (strcmp (name, "autoextend") == 0) | |
11707 | mips_opts.noautoextend = 0; | |
11708 | else if (strcmp (name, "noautoextend") == 0) | |
11709 | mips_opts.noautoextend = 1; | |
11710 | else if (strcmp (name, "push") == 0) | |
11711 | { | |
11712 | struct mips_option_stack *s; | |
11713 | ||
11714 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11715 | s->next = mips_opts_stack; | |
11716 | s->options = mips_opts; | |
11717 | mips_opts_stack = s; | |
11718 | } | |
11719 | else if (strcmp (name, "pop") == 0) | |
11720 | { | |
11721 | struct mips_option_stack *s; | |
11722 | ||
11723 | s = mips_opts_stack; | |
11724 | if (s == NULL) | |
11725 | as_bad (_(".set pop with no .set push")); | |
11726 | else | |
11727 | { | |
11728 | /* If we're changing the reorder mode we need to handle | |
11729 | delay slots correctly. */ | |
11730 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11731 | mips_emit_delays (TRUE); |
252b5132 RH |
11732 | else if (! s->options.noreorder && mips_opts.noreorder) |
11733 | { | |
11734 | if (prev_nop_frag != NULL) | |
11735 | { | |
11736 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11737 | * (mips_opts.mips16 ? 2 : 4)); | |
11738 | prev_nop_frag = NULL; | |
11739 | } | |
11740 | } | |
11741 | ||
11742 | mips_opts = s->options; | |
11743 | mips_opts_stack = s->next; | |
11744 | free (s); | |
11745 | } | |
11746 | } | |
aed1a261 RS |
11747 | else if (strcmp (name, "sym32") == 0) |
11748 | mips_opts.sym32 = TRUE; | |
11749 | else if (strcmp (name, "nosym32") == 0) | |
11750 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11751 | else |
11752 | { | |
11753 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11754 | } | |
11755 | *input_line_pointer = ch; | |
11756 | demand_empty_rest_of_line (); | |
11757 | } | |
11758 | ||
11759 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11760 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11761 | ||
11762 | static void | |
17a2f251 | 11763 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11764 | { |
11765 | mips_pic = SVR4_PIC; | |
143d77c5 | 11766 | mips_abicalls = TRUE; |
4d0d148d TS |
11767 | |
11768 | if (g_switch_seen && g_switch_value != 0) | |
11769 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11770 | g_switch_value = 0; | |
11771 | ||
252b5132 RH |
11772 | bfd_set_gp_size (stdoutput, 0); |
11773 | demand_empty_rest_of_line (); | |
11774 | } | |
11775 | ||
11776 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11777 | PIC code. It sets the $gp register for the function based on the | |
11778 | function address, which is in the register named in the argument. | |
11779 | This uses a relocation against _gp_disp, which is handled specially | |
11780 | by the linker. The result is: | |
11781 | lui $gp,%hi(_gp_disp) | |
11782 | addiu $gp,$gp,%lo(_gp_disp) | |
11783 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11784 | The .cpload argument is normally $25 == $t9. |
11785 | ||
11786 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11787 | lui $gp,%hi(__gnu_local_gp) |
11788 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11789 | and the argument is ignored. This saves an instruction, but the |
11790 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11791 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11792 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11793 | |
11794 | static void | |
17a2f251 | 11795 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11796 | { |
11797 | expressionS ex; | |
aa6975fb ILT |
11798 | int reg; |
11799 | int in_shared; | |
252b5132 | 11800 | |
6478892d TS |
11801 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11802 | .cpload is ignored. */ | |
11803 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11804 | { |
11805 | s_ignore (0); | |
11806 | return; | |
11807 | } | |
11808 | ||
d3ecfc59 | 11809 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11810 | if (mips_opts.noreorder == 0) |
11811 | as_warn (_(".cpload not in noreorder section")); | |
11812 | ||
aa6975fb ILT |
11813 | reg = tc_get_register (0); |
11814 | ||
11815 | /* If we need to produce a 64-bit address, we are better off using | |
11816 | the default instruction sequence. */ | |
aed1a261 | 11817 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11818 | |
252b5132 | 11819 | ex.X_op = O_symbol; |
bbe506e8 TS |
11820 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11821 | "__gnu_local_gp"); | |
252b5132 RH |
11822 | ex.X_op_symbol = NULL; |
11823 | ex.X_add_number = 0; | |
11824 | ||
11825 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11826 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11827 | |
584892a6 | 11828 | macro_start (); |
67c0d1eb RS |
11829 | macro_build_lui (&ex, mips_gp_register); |
11830 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11831 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11832 | if (in_shared) |
11833 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11834 | mips_gp_register, reg); | |
584892a6 | 11835 | macro_end (); |
252b5132 RH |
11836 | |
11837 | demand_empty_rest_of_line (); | |
11838 | } | |
11839 | ||
6478892d TS |
11840 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11841 | .cpsetup $reg1, offset|$reg2, label | |
11842 | ||
11843 | If offset is given, this results in: | |
11844 | sd $gp, offset($sp) | |
956cd1d6 | 11845 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11846 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11847 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11848 | |
11849 | If $reg2 is given, this results in: | |
11850 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11851 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11852 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11853 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11854 | $reg1 is normally $25 == $t9. |
11855 | ||
11856 | The -mno-shared option replaces the last three instructions with | |
11857 | lui $gp,%hi(_gp) | |
11858 | addiu $gp,$gp,%lo(_gp) | |
11859 | */ | |
11860 | ||
6478892d | 11861 | static void |
17a2f251 | 11862 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11863 | { |
11864 | expressionS ex_off; | |
11865 | expressionS ex_sym; | |
11866 | int reg1; | |
6478892d | 11867 | |
8586fc66 | 11868 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11869 | We also need NewABI support. */ |
11870 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11871 | { | |
11872 | s_ignore (0); | |
11873 | return; | |
11874 | } | |
11875 | ||
11876 | reg1 = tc_get_register (0); | |
11877 | SKIP_WHITESPACE (); | |
11878 | if (*input_line_pointer != ',') | |
11879 | { | |
11880 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11881 | return; | |
11882 | } | |
11883 | else | |
80245285 | 11884 | ++input_line_pointer; |
6478892d TS |
11885 | SKIP_WHITESPACE (); |
11886 | if (*input_line_pointer == '$') | |
80245285 TS |
11887 | { |
11888 | mips_cpreturn_register = tc_get_register (0); | |
11889 | mips_cpreturn_offset = -1; | |
11890 | } | |
6478892d | 11891 | else |
80245285 TS |
11892 | { |
11893 | mips_cpreturn_offset = get_absolute_expression (); | |
11894 | mips_cpreturn_register = -1; | |
11895 | } | |
6478892d TS |
11896 | SKIP_WHITESPACE (); |
11897 | if (*input_line_pointer != ',') | |
11898 | { | |
11899 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11900 | return; | |
11901 | } | |
11902 | else | |
f9419b05 | 11903 | ++input_line_pointer; |
6478892d | 11904 | SKIP_WHITESPACE (); |
f21f8242 | 11905 | expression (&ex_sym); |
6478892d | 11906 | |
584892a6 | 11907 | macro_start (); |
6478892d TS |
11908 | if (mips_cpreturn_register == -1) |
11909 | { | |
11910 | ex_off.X_op = O_constant; | |
11911 | ex_off.X_add_symbol = NULL; | |
11912 | ex_off.X_op_symbol = NULL; | |
11913 | ex_off.X_add_number = mips_cpreturn_offset; | |
11914 | ||
67c0d1eb | 11915 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11916 | BFD_RELOC_LO16, SP); |
6478892d TS |
11917 | } |
11918 | else | |
67c0d1eb | 11919 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11920 | mips_gp_register, 0); |
6478892d | 11921 | |
aed1a261 | 11922 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
11923 | { |
11924 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11925 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11926 | BFD_RELOC_HI16_S); | |
11927 | ||
11928 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11929 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11930 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11931 | ||
11932 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11933 | mips_gp_register, reg1); | |
11934 | } | |
11935 | else | |
11936 | { | |
11937 | expressionS ex; | |
11938 | ||
11939 | ex.X_op = O_symbol; | |
11940 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11941 | ex.X_op_symbol = NULL; | |
11942 | ex.X_add_number = 0; | |
6e1304d8 | 11943 | |
aa6975fb ILT |
11944 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11945 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11946 | ||
11947 | macro_build_lui (&ex, mips_gp_register); | |
11948 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11949 | mips_gp_register, BFD_RELOC_LO16); | |
11950 | } | |
f21f8242 | 11951 | |
584892a6 | 11952 | macro_end (); |
6478892d TS |
11953 | |
11954 | demand_empty_rest_of_line (); | |
11955 | } | |
11956 | ||
11957 | static void | |
17a2f251 | 11958 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11959 | { |
11960 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11961 | .cplocal is ignored. */ | |
11962 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11963 | { | |
11964 | s_ignore (0); | |
11965 | return; | |
11966 | } | |
11967 | ||
11968 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11969 | demand_empty_rest_of_line (); |
6478892d TS |
11970 | } |
11971 | ||
252b5132 RH |
11972 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11973 | offset from $sp. The offset is remembered, and after making a PIC | |
11974 | call $gp is restored from that location. */ | |
11975 | ||
11976 | static void | |
17a2f251 | 11977 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11978 | { |
11979 | expressionS ex; | |
252b5132 | 11980 | |
6478892d | 11981 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11982 | .cprestore is ignored. */ |
6478892d | 11983 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11984 | { |
11985 | s_ignore (0); | |
11986 | return; | |
11987 | } | |
11988 | ||
11989 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11990 | mips_cprestore_valid = 1; |
252b5132 RH |
11991 | |
11992 | ex.X_op = O_constant; | |
11993 | ex.X_add_symbol = NULL; | |
11994 | ex.X_op_symbol = NULL; | |
11995 | ex.X_add_number = mips_cprestore_offset; | |
11996 | ||
584892a6 | 11997 | macro_start (); |
67c0d1eb RS |
11998 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11999 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12000 | macro_end (); |
252b5132 RH |
12001 | |
12002 | demand_empty_rest_of_line (); | |
12003 | } | |
12004 | ||
6478892d | 12005 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12006 | was given in the preceding .cpsetup, it results in: |
6478892d | 12007 | ld $gp, offset($sp) |
76b3015f | 12008 | |
6478892d | 12009 | If a register $reg2 was given there, it results in: |
609f23f4 | 12010 | daddu $gp, $reg2, $0 |
6478892d TS |
12011 | */ |
12012 | static void | |
17a2f251 | 12013 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12014 | { |
12015 | expressionS ex; | |
6478892d TS |
12016 | |
12017 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12018 | We also need NewABI support. */ | |
12019 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12020 | { | |
12021 | s_ignore (0); | |
12022 | return; | |
12023 | } | |
12024 | ||
584892a6 | 12025 | macro_start (); |
6478892d TS |
12026 | if (mips_cpreturn_register == -1) |
12027 | { | |
12028 | ex.X_op = O_constant; | |
12029 | ex.X_add_symbol = NULL; | |
12030 | ex.X_op_symbol = NULL; | |
12031 | ex.X_add_number = mips_cpreturn_offset; | |
12032 | ||
67c0d1eb | 12033 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12034 | } |
12035 | else | |
67c0d1eb | 12036 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12037 | mips_cpreturn_register, 0); |
584892a6 | 12038 | macro_end (); |
6478892d TS |
12039 | |
12040 | demand_empty_rest_of_line (); | |
12041 | } | |
12042 | ||
12043 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12044 | code. It sets the offset to use in gp_rel relocations. */ | |
12045 | ||
12046 | static void | |
17a2f251 | 12047 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12048 | { |
12049 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12050 | We also need NewABI support. */ | |
12051 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12052 | { | |
12053 | s_ignore (0); | |
12054 | return; | |
12055 | } | |
12056 | ||
def2e0dd | 12057 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12058 | |
12059 | demand_empty_rest_of_line (); | |
12060 | } | |
12061 | ||
252b5132 RH |
12062 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12063 | code. It generates a 32 bit GP relative reloc. */ | |
12064 | ||
12065 | static void | |
17a2f251 | 12066 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12067 | { |
12068 | symbolS *label; | |
12069 | expressionS ex; | |
12070 | char *p; | |
12071 | ||
12072 | /* When not generating PIC code, this is treated as .word. */ | |
12073 | if (mips_pic != SVR4_PIC) | |
12074 | { | |
12075 | s_cons (2); | |
12076 | return; | |
12077 | } | |
12078 | ||
12079 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12080 | mips_emit_delays (TRUE); |
252b5132 RH |
12081 | if (auto_align) |
12082 | mips_align (2, 0, label); | |
12083 | mips_clear_insn_labels (); | |
12084 | ||
12085 | expression (&ex); | |
12086 | ||
12087 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12088 | { | |
12089 | as_bad (_("Unsupported use of .gpword")); | |
12090 | ignore_rest_of_line (); | |
12091 | } | |
12092 | ||
12093 | p = frag_more (4); | |
17a2f251 | 12094 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12095 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12096 | BFD_RELOC_GPREL32); |
252b5132 RH |
12097 | |
12098 | demand_empty_rest_of_line (); | |
12099 | } | |
12100 | ||
10181a0d | 12101 | static void |
17a2f251 | 12102 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12103 | { |
12104 | symbolS *label; | |
12105 | expressionS ex; | |
12106 | char *p; | |
12107 | ||
12108 | /* When not generating PIC code, this is treated as .dword. */ | |
12109 | if (mips_pic != SVR4_PIC) | |
12110 | { | |
12111 | s_cons (3); | |
12112 | return; | |
12113 | } | |
12114 | ||
12115 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12116 | mips_emit_delays (TRUE); |
10181a0d AO |
12117 | if (auto_align) |
12118 | mips_align (3, 0, label); | |
12119 | mips_clear_insn_labels (); | |
12120 | ||
12121 | expression (&ex); | |
12122 | ||
12123 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12124 | { | |
12125 | as_bad (_("Unsupported use of .gpdword")); | |
12126 | ignore_rest_of_line (); | |
12127 | } | |
12128 | ||
12129 | p = frag_more (8); | |
17a2f251 | 12130 | md_number_to_chars (p, 0, 8); |
a105a300 | 12131 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12132 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12133 | |
12134 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12135 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12136 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12137 | |
12138 | demand_empty_rest_of_line (); | |
12139 | } | |
12140 | ||
252b5132 RH |
12141 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12142 | tables in SVR4 PIC code. */ | |
12143 | ||
12144 | static void | |
17a2f251 | 12145 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12146 | { |
252b5132 RH |
12147 | int reg; |
12148 | ||
10181a0d AO |
12149 | /* This is ignored when not generating SVR4 PIC code. */ |
12150 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12151 | { |
12152 | s_ignore (0); | |
12153 | return; | |
12154 | } | |
12155 | ||
12156 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12157 | macro_start (); |
252b5132 | 12158 | reg = tc_get_register (0); |
67c0d1eb | 12159 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12160 | macro_end (); |
252b5132 | 12161 | |
bdaaa2e1 | 12162 | demand_empty_rest_of_line (); |
252b5132 RH |
12163 | } |
12164 | ||
12165 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12166 | mips16 mode. This permits the linker to handle them specially, | |
12167 | such as generating jalx instructions when needed. We also make | |
12168 | them odd for the duration of the assembly, in order to generate the | |
12169 | right sort of code. We will make them even in the adjust_symtab | |
12170 | routine, while leaving them marked. This is convenient for the | |
12171 | debugger and the disassembler. The linker knows to make them odd | |
12172 | again. */ | |
12173 | ||
12174 | static void | |
17a2f251 | 12175 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12176 | { |
f9419b05 | 12177 | mips16_mark_labels (); |
252b5132 RH |
12178 | |
12179 | demand_empty_rest_of_line (); | |
12180 | } | |
12181 | ||
12182 | /* Handle a .stabn directive. We need these in order to mark a label | |
12183 | as being a mips16 text label correctly. Sometimes the compiler | |
12184 | will emit a label, followed by a .stabn, and then switch sections. | |
12185 | If the label and .stabn are in mips16 mode, then the label is | |
12186 | really a mips16 text label. */ | |
12187 | ||
12188 | static void | |
17a2f251 | 12189 | s_mips_stab (int type) |
252b5132 | 12190 | { |
f9419b05 | 12191 | if (type == 'n') |
252b5132 RH |
12192 | mips16_mark_labels (); |
12193 | ||
12194 | s_stab (type); | |
12195 | } | |
12196 | ||
12197 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12198 | */ | |
12199 | ||
12200 | static void | |
17a2f251 | 12201 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12202 | { |
12203 | char *name; | |
12204 | int c; | |
12205 | symbolS *symbolP; | |
12206 | expressionS exp; | |
12207 | ||
12208 | name = input_line_pointer; | |
12209 | c = get_symbol_end (); | |
12210 | symbolP = symbol_find_or_make (name); | |
12211 | S_SET_WEAK (symbolP); | |
12212 | *input_line_pointer = c; | |
12213 | ||
12214 | SKIP_WHITESPACE (); | |
12215 | ||
12216 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12217 | { | |
12218 | if (S_IS_DEFINED (symbolP)) | |
12219 | { | |
956cd1d6 | 12220 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12221 | S_GET_NAME (symbolP)); |
12222 | ignore_rest_of_line (); | |
12223 | return; | |
12224 | } | |
bdaaa2e1 | 12225 | |
252b5132 RH |
12226 | if (*input_line_pointer == ',') |
12227 | { | |
12228 | ++input_line_pointer; | |
12229 | SKIP_WHITESPACE (); | |
12230 | } | |
bdaaa2e1 | 12231 | |
252b5132 RH |
12232 | expression (&exp); |
12233 | if (exp.X_op != O_symbol) | |
12234 | { | |
12235 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12236 | ignore_rest_of_line (); |
252b5132 RH |
12237 | return; |
12238 | } | |
49309057 | 12239 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12240 | } |
12241 | ||
12242 | demand_empty_rest_of_line (); | |
12243 | } | |
12244 | ||
12245 | /* Parse a register string into a number. Called from the ECOFF code | |
12246 | to parse .frame. The argument is non-zero if this is the frame | |
12247 | register, so that we can record it in mips_frame_reg. */ | |
12248 | ||
12249 | int | |
17a2f251 | 12250 | tc_get_register (int frame) |
252b5132 RH |
12251 | { |
12252 | int reg; | |
12253 | ||
12254 | SKIP_WHITESPACE (); | |
12255 | if (*input_line_pointer++ != '$') | |
12256 | { | |
12257 | as_warn (_("expected `$'")); | |
85b51719 | 12258 | reg = ZERO; |
252b5132 | 12259 | } |
3882b010 | 12260 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12261 | { |
12262 | reg = get_absolute_expression (); | |
12263 | if (reg < 0 || reg >= 32) | |
12264 | { | |
12265 | as_warn (_("Bad register number")); | |
85b51719 | 12266 | reg = ZERO; |
252b5132 RH |
12267 | } |
12268 | } | |
12269 | else | |
12270 | { | |
76db943d | 12271 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12272 | { |
12273 | reg = RA; | |
12274 | input_line_pointer += 2; | |
12275 | } | |
76db943d | 12276 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12277 | { |
12278 | reg = FP; | |
12279 | input_line_pointer += 2; | |
12280 | } | |
252b5132 | 12281 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12282 | { |
12283 | reg = SP; | |
12284 | input_line_pointer += 2; | |
12285 | } | |
252b5132 | 12286 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12287 | { |
12288 | reg = GP; | |
12289 | input_line_pointer += 2; | |
12290 | } | |
252b5132 | 12291 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12292 | { |
12293 | reg = AT; | |
12294 | input_line_pointer += 2; | |
12295 | } | |
12296 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12297 | { | |
12298 | reg = KT0; | |
12299 | input_line_pointer += 3; | |
12300 | } | |
12301 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12302 | { | |
12303 | reg = KT1; | |
12304 | input_line_pointer += 3; | |
12305 | } | |
12306 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12307 | { | |
12308 | reg = ZERO; | |
12309 | input_line_pointer += 4; | |
12310 | } | |
252b5132 RH |
12311 | else |
12312 | { | |
12313 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12314 | reg = ZERO; |
12315 | while (ISALNUM(*input_line_pointer)) | |
12316 | input_line_pointer++; | |
252b5132 | 12317 | } |
252b5132 RH |
12318 | } |
12319 | if (frame) | |
7a621144 DJ |
12320 | { |
12321 | mips_frame_reg = reg != 0 ? reg : SP; | |
12322 | mips_frame_reg_valid = 1; | |
12323 | mips_cprestore_valid = 0; | |
12324 | } | |
252b5132 RH |
12325 | return reg; |
12326 | } | |
12327 | ||
12328 | valueT | |
17a2f251 | 12329 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12330 | { |
12331 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12332 | ||
12333 | #ifdef OBJ_ELF | |
12334 | /* We don't need to align ELF sections to the full alignment. | |
12335 | However, Irix 5 may prefer that we align them at least to a 16 | |
12336 | byte boundary. We don't bother to align the sections if we are | |
12337 | targeted for an embedded system. */ | |
12338 | if (strcmp (TARGET_OS, "elf") == 0) | |
12339 | return addr; | |
12340 | if (align > 4) | |
12341 | align = 4; | |
12342 | #endif | |
12343 | ||
12344 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12345 | } | |
12346 | ||
12347 | /* Utility routine, called from above as well. If called while the | |
12348 | input file is still being read, it's only an approximation. (For | |
12349 | example, a symbol may later become defined which appeared to be | |
12350 | undefined earlier.) */ | |
12351 | ||
12352 | static int | |
17a2f251 | 12353 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12354 | { |
12355 | if (sym == 0) | |
12356 | return 0; | |
12357 | ||
4d0d148d | 12358 | if (g_switch_value > 0) |
252b5132 RH |
12359 | { |
12360 | const char *symname; | |
12361 | int change; | |
12362 | ||
c9914766 | 12363 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12364 | register. It can be if it is smaller than the -G size or if |
12365 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12366 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12367 | they can. */ |
12368 | symname = S_GET_NAME (sym); | |
12369 | if (symname != (const char *) NULL | |
12370 | && (strcmp (symname, "eprol") == 0 | |
12371 | || strcmp (symname, "etext") == 0 | |
12372 | || strcmp (symname, "_gp") == 0 | |
12373 | || strcmp (symname, "edata") == 0 | |
12374 | || strcmp (symname, "_fbss") == 0 | |
12375 | || strcmp (symname, "_fdata") == 0 | |
12376 | || strcmp (symname, "_ftext") == 0 | |
12377 | || strcmp (symname, "end") == 0 | |
12378 | || strcmp (symname, "_gp_disp") == 0)) | |
12379 | change = 1; | |
12380 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12381 | && (0 | |
12382 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12383 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12384 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12385 | <= g_switch_value)) | |
252b5132 RH |
12386 | #endif |
12387 | /* We must defer this decision until after the whole | |
12388 | file has been read, since there might be a .extern | |
12389 | after the first use of this symbol. */ | |
12390 | || (before_relaxing | |
12391 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12392 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12393 | #endif |
12394 | && S_GET_VALUE (sym) == 0) | |
12395 | || (S_GET_VALUE (sym) != 0 | |
12396 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12397 | change = 0; | |
12398 | else | |
12399 | { | |
12400 | const char *segname; | |
12401 | ||
12402 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12403 | assert (strcmp (segname, ".lit8") != 0 | |
12404 | && strcmp (segname, ".lit4") != 0); | |
12405 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12406 | && strcmp (segname, ".sbss") != 0 |
12407 | && strncmp (segname, ".sdata.", 7) != 0 | |
12408 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12409 | } |
12410 | return change; | |
12411 | } | |
12412 | else | |
c9914766 | 12413 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12414 | return 1; |
12415 | } | |
12416 | ||
5919d012 RS |
12417 | |
12418 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12419 | ||
12420 | static bfd_boolean | |
17a2f251 | 12421 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12422 | { |
12423 | asection *symsec; | |
12424 | bfd_boolean linkonce; | |
12425 | ||
12426 | /* Handle the case of a symbol equated to another symbol. */ | |
12427 | while (symbol_equated_reloc_p (sym)) | |
12428 | { | |
12429 | symbolS *n; | |
12430 | ||
12431 | /* It's possible to get a loop here in a badly written | |
12432 | program. */ | |
12433 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12434 | if (n == sym) | |
12435 | break; | |
12436 | sym = n; | |
12437 | } | |
12438 | ||
12439 | symsec = S_GET_SEGMENT (sym); | |
12440 | ||
12441 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12442 | linkonce = FALSE; | |
12443 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12444 | { | |
12445 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12446 | != 0) | |
12447 | linkonce = TRUE; | |
12448 | ||
12449 | /* The GNU toolchain uses an extension for ELF: a section | |
12450 | beginning with the magic string .gnu.linkonce is a linkonce | |
12451 | section. */ | |
12452 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12453 | sizeof ".gnu.linkonce" - 1) == 0) | |
12454 | linkonce = TRUE; | |
12455 | } | |
12456 | ||
12457 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12458 | return (symsec != &bfd_und_section | |
12459 | && symsec != &bfd_abs_section | |
12460 | && ! bfd_is_com_section (symsec) | |
12461 | && !linkonce | |
12462 | #ifdef OBJ_ELF | |
12463 | /* A global or weak symbol is treated as external. */ | |
12464 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12465 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12466 | #endif |
12467 | ); | |
12468 | } | |
12469 | ||
12470 | ||
252b5132 RH |
12471 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12472 | extended opcode. SEC is the section the frag is in. */ | |
12473 | ||
12474 | static int | |
17a2f251 | 12475 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12476 | { |
12477 | int type; | |
12478 | register const struct mips16_immed_operand *op; | |
12479 | offsetT val; | |
12480 | int mintiny, maxtiny; | |
12481 | segT symsec; | |
98aa84af | 12482 | fragS *sym_frag; |
252b5132 RH |
12483 | |
12484 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12485 | return 0; | |
12486 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12487 | return 1; | |
12488 | ||
12489 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12490 | op = mips16_immed_operands; | |
12491 | while (op->type != type) | |
12492 | { | |
12493 | ++op; | |
12494 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12495 | } | |
12496 | ||
12497 | if (op->unsp) | |
12498 | { | |
12499 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12500 | { | |
12501 | mintiny = 1; | |
12502 | maxtiny = 1 << op->nbits; | |
12503 | } | |
12504 | else | |
12505 | { | |
12506 | mintiny = 0; | |
12507 | maxtiny = (1 << op->nbits) - 1; | |
12508 | } | |
12509 | } | |
12510 | else | |
12511 | { | |
12512 | mintiny = - (1 << (op->nbits - 1)); | |
12513 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12514 | } | |
12515 | ||
98aa84af | 12516 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12517 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12518 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12519 | |
12520 | if (op->pcrel) | |
12521 | { | |
12522 | addressT addr; | |
12523 | ||
12524 | /* We won't have the section when we are called from | |
12525 | mips_relax_frag. However, we will always have been called | |
12526 | from md_estimate_size_before_relax first. If this is a | |
12527 | branch to a different section, we mark it as such. If SEC is | |
12528 | NULL, and the frag is not marked, then it must be a branch to | |
12529 | the same section. */ | |
12530 | if (sec == NULL) | |
12531 | { | |
12532 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12533 | return 1; | |
12534 | } | |
12535 | else | |
12536 | { | |
98aa84af | 12537 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12538 | if (symsec != sec) |
12539 | { | |
12540 | fragp->fr_subtype = | |
12541 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12542 | ||
12543 | /* FIXME: We should support this, and let the linker | |
12544 | catch branches and loads that are out of range. */ | |
12545 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12546 | _("unsupported PC relative reference to different section")); | |
12547 | ||
12548 | return 1; | |
12549 | } | |
98aa84af AM |
12550 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12551 | /* Assume non-extended on the first relaxation pass. | |
12552 | The address we have calculated will be bogus if this is | |
12553 | a forward branch to another frag, as the forward frag | |
12554 | will have fr_address == 0. */ | |
12555 | return 0; | |
252b5132 RH |
12556 | } |
12557 | ||
12558 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12559 | the same section. If the relax_marker of the symbol fragment |
12560 | differs from the relax_marker of this fragment, we have not | |
12561 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12562 | in STRETCH in order to get a better estimate of the address. |
12563 | This particularly matters because of the shift bits. */ | |
12564 | if (stretch != 0 | |
98aa84af | 12565 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12566 | { |
12567 | fragS *f; | |
12568 | ||
12569 | /* Adjust stretch for any alignment frag. Note that if have | |
12570 | been expanding the earlier code, the symbol may be | |
12571 | defined in what appears to be an earlier frag. FIXME: | |
12572 | This doesn't handle the fr_subtype field, which specifies | |
12573 | a maximum number of bytes to skip when doing an | |
12574 | alignment. */ | |
98aa84af | 12575 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12576 | { |
12577 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12578 | { | |
12579 | if (stretch < 0) | |
12580 | stretch = - ((- stretch) | |
12581 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12582 | else | |
12583 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12584 | if (stretch == 0) | |
12585 | break; | |
12586 | } | |
12587 | } | |
12588 | if (f != NULL) | |
12589 | val += stretch; | |
12590 | } | |
12591 | ||
12592 | addr = fragp->fr_address + fragp->fr_fix; | |
12593 | ||
12594 | /* The base address rules are complicated. The base address of | |
12595 | a branch is the following instruction. The base address of a | |
12596 | PC relative load or add is the instruction itself, but if it | |
12597 | is in a delay slot (in which case it can not be extended) use | |
12598 | the address of the instruction whose delay slot it is in. */ | |
12599 | if (type == 'p' || type == 'q') | |
12600 | { | |
12601 | addr += 2; | |
12602 | ||
12603 | /* If we are currently assuming that this frag should be | |
12604 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12605 | higher. */ |
252b5132 RH |
12606 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12607 | addr += 2; | |
12608 | ||
12609 | /* Ignore the low bit in the target, since it will be set | |
12610 | for a text label. */ | |
12611 | if ((val & 1) != 0) | |
12612 | --val; | |
12613 | } | |
12614 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12615 | addr -= 4; | |
12616 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12617 | addr -= 2; | |
12618 | ||
12619 | val -= addr & ~ ((1 << op->shift) - 1); | |
12620 | ||
12621 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12622 | if (type == 'p' || type == 'q') | |
12623 | val /= 2; | |
12624 | ||
12625 | /* If any of the shifted bits are set, we must use an extended | |
12626 | opcode. If the address depends on the size of this | |
12627 | instruction, this can lead to a loop, so we arrange to always | |
12628 | use an extended opcode. We only check this when we are in | |
12629 | the main relaxation loop, when SEC is NULL. */ | |
12630 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12631 | { | |
12632 | fragp->fr_subtype = | |
12633 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12634 | return 1; | |
12635 | } | |
12636 | ||
12637 | /* If we are about to mark a frag as extended because the value | |
12638 | is precisely maxtiny + 1, then there is a chance of an | |
12639 | infinite loop as in the following code: | |
12640 | la $4,foo | |
12641 | .skip 1020 | |
12642 | .align 2 | |
12643 | foo: | |
12644 | In this case when the la is extended, foo is 0x3fc bytes | |
12645 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12646 | the la must be extended. To avoid this loop, we mark the | |
12647 | frag as extended if it was small, and is about to become | |
12648 | extended with a value of maxtiny + 1. */ | |
12649 | if (val == ((maxtiny + 1) << op->shift) | |
12650 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12651 | && sec == NULL) | |
12652 | { | |
12653 | fragp->fr_subtype = | |
12654 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12655 | return 1; | |
12656 | } | |
12657 | } | |
12658 | else if (symsec != absolute_section && sec != NULL) | |
12659 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12660 | ||
12661 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12662 | || val < (mintiny << op->shift) | |
12663 | || val > (maxtiny << op->shift)) | |
12664 | return 1; | |
12665 | else | |
12666 | return 0; | |
12667 | } | |
12668 | ||
4a6a3df4 AO |
12669 | /* Compute the length of a branch sequence, and adjust the |
12670 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12671 | worst-case length is computed, with UPDATE being used to indicate | |
12672 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12673 | branch is to be computed. */ | |
12674 | static int | |
17a2f251 | 12675 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12676 | { |
b34976b6 | 12677 | bfd_boolean toofar; |
4a6a3df4 AO |
12678 | int length; |
12679 | ||
12680 | if (fragp | |
12681 | && S_IS_DEFINED (fragp->fr_symbol) | |
12682 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12683 | { | |
12684 | addressT addr; | |
12685 | offsetT val; | |
12686 | ||
12687 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12688 | ||
12689 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12690 | ||
12691 | val -= addr; | |
12692 | ||
12693 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12694 | } | |
12695 | else if (fragp) | |
12696 | /* If the symbol is not defined or it's in a different segment, | |
12697 | assume the user knows what's going on and emit a short | |
12698 | branch. */ | |
b34976b6 | 12699 | toofar = FALSE; |
4a6a3df4 | 12700 | else |
b34976b6 | 12701 | toofar = TRUE; |
4a6a3df4 AO |
12702 | |
12703 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12704 | fragp->fr_subtype | |
af6ae2ad | 12705 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12706 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12707 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12708 | toofar); | |
12709 | ||
12710 | length = 4; | |
12711 | if (toofar) | |
12712 | { | |
12713 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12714 | length += 8; | |
12715 | ||
12716 | if (mips_pic != NO_PIC) | |
12717 | { | |
12718 | /* Additional space for PIC loading of target address. */ | |
12719 | length += 8; | |
12720 | if (mips_opts.isa == ISA_MIPS1) | |
12721 | /* Additional space for $at-stabilizing nop. */ | |
12722 | length += 4; | |
12723 | } | |
12724 | ||
12725 | /* If branch is conditional. */ | |
12726 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12727 | length += 8; | |
12728 | } | |
b34976b6 | 12729 | |
4a6a3df4 AO |
12730 | return length; |
12731 | } | |
12732 | ||
252b5132 RH |
12733 | /* Estimate the size of a frag before relaxing. Unless this is the |
12734 | mips16, we are not really relaxing here, and the final size is | |
12735 | encoded in the subtype information. For the mips16, we have to | |
12736 | decide whether we are using an extended opcode or not. */ | |
12737 | ||
252b5132 | 12738 | int |
17a2f251 | 12739 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12740 | { |
5919d012 | 12741 | int change; |
252b5132 | 12742 | |
4a6a3df4 AO |
12743 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12744 | { | |
12745 | ||
b34976b6 AM |
12746 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12747 | ||
4a6a3df4 AO |
12748 | return fragp->fr_var; |
12749 | } | |
12750 | ||
252b5132 | 12751 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12752 | /* We don't want to modify the EXTENDED bit here; it might get us |
12753 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12754 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12755 | |
12756 | if (mips_pic == NO_PIC) | |
5919d012 | 12757 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12758 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12759 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12760 | else |
12761 | abort (); | |
12762 | ||
12763 | if (change) | |
12764 | { | |
4d7206a2 | 12765 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12766 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12767 | } |
4d7206a2 RS |
12768 | else |
12769 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12770 | } |
12771 | ||
12772 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12773 | should be converted into a reloc against a section. */ |
252b5132 RH |
12774 | |
12775 | int | |
17a2f251 | 12776 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12777 | { |
de7e6852 RS |
12778 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12779 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12780 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12781 | return 0; | |
a161fe53 | 12782 | |
252b5132 RH |
12783 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12784 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12785 | return 0; | |
a161fe53 | 12786 | |
252b5132 RH |
12787 | if (fixp->fx_addsy == NULL) |
12788 | return 1; | |
a161fe53 | 12789 | |
de7e6852 RS |
12790 | /* If symbol SYM is in a mergeable section, relocations of the form |
12791 | SYM + 0 can usually be made section-relative. The mergeable data | |
12792 | is then identified by the section offset rather than by the symbol. | |
12793 | ||
12794 | However, if we're generating REL LO16 relocations, the offset is split | |
12795 | between the LO16 and parterning high part relocation. The linker will | |
12796 | need to recalculate the complete offset in order to correctly identify | |
12797 | the merge data. | |
12798 | ||
12799 | The linker has traditionally not looked for the parterning high part | |
12800 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12801 | placed anywhere. Rather than break backwards compatibility by changing | |
12802 | this, it seems better not to force the issue, and instead keep the | |
12803 | original symbol. This will work with either linker behavior. */ | |
12804 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12805 | && HAVE_IN_PLACE_ADDENDS | |
12806 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12807 | return 0; | |
12808 | ||
252b5132 | 12809 | #ifdef OBJ_ELF |
de7e6852 RS |
12810 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12811 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12812 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12813 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12814 | && fixp->fx_subsy == NULL) | |
12815 | return 0; | |
12816 | #endif | |
a161fe53 | 12817 | |
252b5132 RH |
12818 | return 1; |
12819 | } | |
12820 | ||
12821 | /* Translate internal representation of relocation info to BFD target | |
12822 | format. */ | |
12823 | ||
12824 | arelent ** | |
17a2f251 | 12825 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12826 | { |
12827 | static arelent *retval[4]; | |
12828 | arelent *reloc; | |
12829 | bfd_reloc_code_real_type code; | |
12830 | ||
4b0cff4e TS |
12831 | memset (retval, 0, sizeof(retval)); |
12832 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12833 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12834 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12835 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12836 | ||
3e722fb5 CD |
12837 | assert (! fixp->fx_pcrel); |
12838 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12839 | |
438c16b8 TS |
12840 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12841 | entry to be used in the relocation's section offset. */ | |
12842 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12843 | { |
12844 | reloc->address = reloc->addend; | |
12845 | reloc->addend = 0; | |
12846 | } | |
12847 | ||
252b5132 | 12848 | code = fixp->fx_r_type; |
252b5132 | 12849 | |
3e722fb5 CD |
12850 | /* To support a PC relative reloc, we used a Cygnus extension. |
12851 | We check for that here to make sure that we don't let such a | |
12852 | reloc escape normally. (FIXME: This was formerly used by | |
12853 | embedded-PIC support, but is now used by branch handling in | |
12854 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12855 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12856 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12857 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12858 | reloc->howto = NULL; |
12859 | else | |
12860 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12861 | ||
252b5132 RH |
12862 | if (reloc->howto == NULL) |
12863 | { | |
12864 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12865 | _("Can not represent %s relocation in this object file format"), | |
12866 | bfd_get_reloc_code_name (code)); | |
12867 | retval[0] = NULL; | |
12868 | } | |
12869 | ||
12870 | return retval; | |
12871 | } | |
12872 | ||
12873 | /* Relax a machine dependent frag. This returns the amount by which | |
12874 | the current size of the frag should change. */ | |
12875 | ||
12876 | int | |
17a2f251 | 12877 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12878 | { |
4a6a3df4 AO |
12879 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12880 | { | |
12881 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12882 | |
12883 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12884 | |
12885 | return fragp->fr_var - old_var; | |
12886 | } | |
12887 | ||
252b5132 RH |
12888 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12889 | return 0; | |
12890 | ||
c4e7957c | 12891 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12892 | { |
12893 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12894 | return 0; | |
12895 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12896 | return 2; | |
12897 | } | |
12898 | else | |
12899 | { | |
12900 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12901 | return 0; | |
12902 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12903 | return -2; | |
12904 | } | |
12905 | ||
12906 | return 0; | |
12907 | } | |
12908 | ||
12909 | /* Convert a machine dependent frag. */ | |
12910 | ||
12911 | void | |
17a2f251 | 12912 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12913 | { |
4a6a3df4 AO |
12914 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12915 | { | |
12916 | bfd_byte *buf; | |
12917 | unsigned long insn; | |
12918 | expressionS exp; | |
12919 | fixS *fixp; | |
b34976b6 | 12920 | |
4a6a3df4 AO |
12921 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12922 | ||
12923 | if (target_big_endian) | |
12924 | insn = bfd_getb32 (buf); | |
12925 | else | |
12926 | insn = bfd_getl32 (buf); | |
b34976b6 | 12927 | |
4a6a3df4 AO |
12928 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12929 | { | |
12930 | /* We generate a fixup instead of applying it right now | |
12931 | because, if there are linker relaxations, we're going to | |
12932 | need the relocations. */ | |
12933 | exp.X_op = O_symbol; | |
12934 | exp.X_add_symbol = fragp->fr_symbol; | |
12935 | exp.X_add_number = fragp->fr_offset; | |
12936 | ||
12937 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12938 | 4, &exp, 1, |
12939 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12940 | fixp->fx_file = fragp->fr_file; |
12941 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12942 | |
2132e3a3 | 12943 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12944 | buf += 4; |
12945 | } | |
12946 | else | |
12947 | { | |
12948 | int i; | |
12949 | ||
12950 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12951 | _("relaxed out-of-range branch into a jump")); | |
12952 | ||
12953 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12954 | goto uncond; | |
12955 | ||
12956 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12957 | { | |
12958 | /* Reverse the branch. */ | |
12959 | switch ((insn >> 28) & 0xf) | |
12960 | { | |
12961 | case 4: | |
12962 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12963 | have the condition reversed by tweaking a single | |
12964 | bit, and their opcodes all have 0x4???????. */ | |
12965 | assert ((insn & 0xf1000000) == 0x41000000); | |
12966 | insn ^= 0x00010000; | |
12967 | break; | |
12968 | ||
12969 | case 0: | |
12970 | /* bltz 0x04000000 bgez 0x04010000 | |
12971 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12972 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12973 | insn ^= 0x00010000; | |
12974 | break; | |
b34976b6 | 12975 | |
4a6a3df4 AO |
12976 | case 1: |
12977 | /* beq 0x10000000 bne 0x14000000 | |
12978 | blez 0x18000000 bgtz 0x1c000000 */ | |
12979 | insn ^= 0x04000000; | |
12980 | break; | |
12981 | ||
12982 | default: | |
12983 | abort (); | |
12984 | } | |
12985 | } | |
12986 | ||
12987 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12988 | { | |
12989 | /* Clear the and-link bit. */ | |
12990 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12991 | ||
12992 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12993 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12994 | insn &= ~0x00100000; | |
12995 | } | |
12996 | ||
12997 | /* Branch over the branch (if the branch was likely) or the | |
12998 | full jump (not likely case). Compute the offset from the | |
12999 | current instruction to branch to. */ | |
13000 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13001 | i = 16; | |
13002 | else | |
13003 | { | |
13004 | /* How many bytes in instructions we've already emitted? */ | |
13005 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13006 | /* How many bytes in instructions from here to the end? */ | |
13007 | i = fragp->fr_var - i; | |
13008 | } | |
13009 | /* Convert to instruction count. */ | |
13010 | i >>= 2; | |
13011 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13012 | i--; |
4a6a3df4 AO |
13013 | insn |= i; |
13014 | /* Branch over the jump. */ | |
2132e3a3 | 13015 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13016 | buf += 4; |
13017 | ||
13018 | /* Nop */ | |
2132e3a3 | 13019 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13020 | buf += 4; |
13021 | ||
13022 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13023 | { | |
13024 | /* beql $0, $0, 2f */ | |
13025 | insn = 0x50000000; | |
13026 | /* Compute the PC offset from the current instruction to | |
13027 | the end of the variable frag. */ | |
13028 | /* How many bytes in instructions we've already emitted? */ | |
13029 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13030 | /* How many bytes in instructions from here to the end? */ | |
13031 | i = fragp->fr_var - i; | |
13032 | /* Convert to instruction count. */ | |
13033 | i >>= 2; | |
13034 | /* Don't decrement i, because we want to branch over the | |
13035 | delay slot. */ | |
13036 | ||
13037 | insn |= i; | |
2132e3a3 | 13038 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13039 | buf += 4; |
13040 | ||
2132e3a3 | 13041 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13042 | buf += 4; |
13043 | } | |
13044 | ||
13045 | uncond: | |
13046 | if (mips_pic == NO_PIC) | |
13047 | { | |
13048 | /* j or jal. */ | |
13049 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13050 | ? 0x0c000000 : 0x08000000); | |
13051 | exp.X_op = O_symbol; | |
13052 | exp.X_add_symbol = fragp->fr_symbol; | |
13053 | exp.X_add_number = fragp->fr_offset; | |
13054 | ||
13055 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13056 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13057 | fixp->fx_file = fragp->fr_file; | |
13058 | fixp->fx_line = fragp->fr_line; | |
13059 | ||
2132e3a3 | 13060 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13061 | buf += 4; |
13062 | } | |
13063 | else | |
13064 | { | |
13065 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13066 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13067 | exp.X_op = O_symbol; | |
13068 | exp.X_add_symbol = fragp->fr_symbol; | |
13069 | exp.X_add_number = fragp->fr_offset; | |
13070 | ||
13071 | if (fragp->fr_offset) | |
13072 | { | |
13073 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13074 | exp.X_add_number = 0; | |
13075 | } | |
13076 | ||
13077 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13078 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13079 | fixp->fx_file = fragp->fr_file; | |
13080 | fixp->fx_line = fragp->fr_line; | |
13081 | ||
2132e3a3 | 13082 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13083 | buf += 4; |
b34976b6 | 13084 | |
4a6a3df4 AO |
13085 | if (mips_opts.isa == ISA_MIPS1) |
13086 | { | |
13087 | /* nop */ | |
2132e3a3 | 13088 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13089 | buf += 4; |
13090 | } | |
13091 | ||
13092 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13093 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13094 | ||
13095 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13096 | 4, &exp, 0, BFD_RELOC_LO16); | |
13097 | fixp->fx_file = fragp->fr_file; | |
13098 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13099 | |
2132e3a3 | 13100 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13101 | buf += 4; |
13102 | ||
13103 | /* j(al)r $at. */ | |
13104 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13105 | insn = 0x0020f809; | |
13106 | else | |
13107 | insn = 0x00200008; | |
13108 | ||
2132e3a3 | 13109 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13110 | buf += 4; |
13111 | } | |
13112 | } | |
13113 | ||
13114 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13115 | + fragp->fr_fix + fragp->fr_var); | |
13116 | ||
13117 | fragp->fr_fix += fragp->fr_var; | |
13118 | ||
13119 | return; | |
13120 | } | |
13121 | ||
252b5132 RH |
13122 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13123 | { | |
13124 | int type; | |
13125 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13126 | bfd_boolean small, ext; |
252b5132 RH |
13127 | offsetT val; |
13128 | bfd_byte *buf; | |
13129 | unsigned long insn; | |
b34976b6 | 13130 | bfd_boolean use_extend; |
252b5132 RH |
13131 | unsigned short extend; |
13132 | ||
13133 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13134 | op = mips16_immed_operands; | |
13135 | while (op->type != type) | |
13136 | ++op; | |
13137 | ||
13138 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13139 | { | |
b34976b6 AM |
13140 | small = FALSE; |
13141 | ext = TRUE; | |
252b5132 RH |
13142 | } |
13143 | else | |
13144 | { | |
b34976b6 AM |
13145 | small = TRUE; |
13146 | ext = FALSE; | |
252b5132 RH |
13147 | } |
13148 | ||
6386f3a7 | 13149 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13150 | val = S_GET_VALUE (fragp->fr_symbol); |
13151 | if (op->pcrel) | |
13152 | { | |
13153 | addressT addr; | |
13154 | ||
13155 | addr = fragp->fr_address + fragp->fr_fix; | |
13156 | ||
13157 | /* The rules for the base address of a PC relative reloc are | |
13158 | complicated; see mips16_extended_frag. */ | |
13159 | if (type == 'p' || type == 'q') | |
13160 | { | |
13161 | addr += 2; | |
13162 | if (ext) | |
13163 | addr += 2; | |
13164 | /* Ignore the low bit in the target, since it will be | |
13165 | set for a text label. */ | |
13166 | if ((val & 1) != 0) | |
13167 | --val; | |
13168 | } | |
13169 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13170 | addr -= 4; | |
13171 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13172 | addr -= 2; | |
13173 | ||
13174 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13175 | val -= addr; | |
13176 | ||
13177 | /* Make sure the section winds up with the alignment we have | |
13178 | assumed. */ | |
13179 | if (op->shift > 0) | |
13180 | record_alignment (asec, op->shift); | |
13181 | } | |
13182 | ||
13183 | if (ext | |
13184 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13185 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13186 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13187 | _("extended instruction in delay slot")); | |
13188 | ||
13189 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13190 | ||
13191 | if (target_big_endian) | |
13192 | insn = bfd_getb16 (buf); | |
13193 | else | |
13194 | insn = bfd_getl16 (buf); | |
13195 | ||
13196 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13197 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13198 | small, ext, &insn, &use_extend, &extend); | |
13199 | ||
13200 | if (use_extend) | |
13201 | { | |
2132e3a3 | 13202 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13203 | fragp->fr_fix += 2; |
13204 | buf += 2; | |
13205 | } | |
13206 | ||
2132e3a3 | 13207 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13208 | fragp->fr_fix += 2; |
13209 | buf += 2; | |
13210 | } | |
13211 | else | |
13212 | { | |
4d7206a2 RS |
13213 | int first, second; |
13214 | fixS *fixp; | |
252b5132 | 13215 | |
4d7206a2 RS |
13216 | first = RELAX_FIRST (fragp->fr_subtype); |
13217 | second = RELAX_SECOND (fragp->fr_subtype); | |
13218 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13219 | |
584892a6 RS |
13220 | /* Possibly emit a warning if we've chosen the longer option. */ |
13221 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13222 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13223 | { | |
13224 | const char *msg = macro_warning (fragp->fr_subtype); | |
13225 | if (msg != 0) | |
13226 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13227 | } | |
13228 | ||
4d7206a2 RS |
13229 | /* Go through all the fixups for the first sequence. Disable them |
13230 | (by marking them as done) if we're going to use the second | |
13231 | sequence instead. */ | |
13232 | while (fixp | |
13233 | && fixp->fx_frag == fragp | |
13234 | && fixp->fx_where < fragp->fr_fix - second) | |
13235 | { | |
13236 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13237 | fixp->fx_done = 1; | |
13238 | fixp = fixp->fx_next; | |
13239 | } | |
252b5132 | 13240 | |
4d7206a2 RS |
13241 | /* Go through the fixups for the second sequence. Disable them if |
13242 | we're going to use the first sequence, otherwise adjust their | |
13243 | addresses to account for the relaxation. */ | |
13244 | while (fixp && fixp->fx_frag == fragp) | |
13245 | { | |
13246 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13247 | fixp->fx_where -= first; | |
13248 | else | |
13249 | fixp->fx_done = 1; | |
13250 | fixp = fixp->fx_next; | |
13251 | } | |
13252 | ||
13253 | /* Now modify the frag contents. */ | |
13254 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13255 | { | |
13256 | char *start; | |
13257 | ||
13258 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13259 | memmove (start, start + first, second); | |
13260 | fragp->fr_fix -= first; | |
13261 | } | |
13262 | else | |
13263 | fragp->fr_fix -= second; | |
252b5132 RH |
13264 | } |
13265 | } | |
13266 | ||
13267 | #ifdef OBJ_ELF | |
13268 | ||
13269 | /* This function is called after the relocs have been generated. | |
13270 | We've been storing mips16 text labels as odd. Here we convert them | |
13271 | back to even for the convenience of the debugger. */ | |
13272 | ||
13273 | void | |
17a2f251 | 13274 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13275 | { |
13276 | asymbol **syms; | |
13277 | unsigned int count, i; | |
13278 | ||
13279 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13280 | return; | |
13281 | ||
13282 | syms = bfd_get_outsymbols (stdoutput); | |
13283 | count = bfd_get_symcount (stdoutput); | |
13284 | for (i = 0; i < count; i++, syms++) | |
13285 | { | |
13286 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13287 | && ((*syms)->value & 1) != 0) | |
13288 | { | |
13289 | (*syms)->value &= ~1; | |
13290 | /* If the symbol has an odd size, it was probably computed | |
13291 | incorrectly, so adjust that as well. */ | |
13292 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13293 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13294 | } | |
13295 | } | |
13296 | } | |
13297 | ||
13298 | #endif | |
13299 | ||
13300 | /* This function is called whenever a label is defined. It is used | |
13301 | when handling branch delays; if a branch has a label, we assume we | |
13302 | can not move it. */ | |
13303 | ||
13304 | void | |
17a2f251 | 13305 | mips_define_label (symbolS *sym) |
252b5132 RH |
13306 | { |
13307 | struct insn_label_list *l; | |
13308 | ||
13309 | if (free_insn_labels == NULL) | |
13310 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13311 | else | |
13312 | { | |
13313 | l = free_insn_labels; | |
13314 | free_insn_labels = l->next; | |
13315 | } | |
13316 | ||
13317 | l->label = sym; | |
13318 | l->next = insn_labels; | |
13319 | insn_labels = l; | |
13320 | } | |
13321 | \f | |
13322 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13323 | ||
13324 | /* Some special processing for a MIPS ELF file. */ | |
13325 | ||
13326 | void | |
17a2f251 | 13327 | mips_elf_final_processing (void) |
252b5132 RH |
13328 | { |
13329 | /* Write out the register information. */ | |
316f5878 | 13330 | if (mips_abi != N64_ABI) |
252b5132 RH |
13331 | { |
13332 | Elf32_RegInfo s; | |
13333 | ||
13334 | s.ri_gprmask = mips_gprmask; | |
13335 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13336 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13337 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13338 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13339 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13340 | ||
13341 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13342 | ((Elf32_External_RegInfo *) | |
13343 | mips_regmask_frag)); | |
13344 | } | |
13345 | else | |
13346 | { | |
13347 | Elf64_Internal_RegInfo s; | |
13348 | ||
13349 | s.ri_gprmask = mips_gprmask; | |
13350 | s.ri_pad = 0; | |
13351 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13352 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13353 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13354 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13355 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13356 | ||
13357 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13358 | ((Elf64_External_RegInfo *) | |
13359 | mips_regmask_frag)); | |
13360 | } | |
13361 | ||
13362 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13363 | sort of BFD interface for this. */ | |
13364 | if (mips_any_noreorder) | |
13365 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13366 | if (mips_pic != NO_PIC) | |
143d77c5 | 13367 | { |
252b5132 | 13368 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13369 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13370 | } | |
13371 | if (mips_abicalls) | |
13372 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13373 | |
98d3f06f | 13374 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13375 | if (file_ase_mips16) |
13376 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13377 | #if 0 /* XXX FIXME */ |
13378 | if (file_ase_mips3d) | |
13379 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13380 | #endif | |
deec1734 CD |
13381 | if (file_ase_mdmx) |
13382 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13383 | |
bdaaa2e1 | 13384 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13385 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13386 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13387 | else if (mips_abi == O64_ABI) |
252b5132 | 13388 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13389 | else if (mips_abi == EABI_ABI) |
252b5132 | 13390 | { |
316f5878 | 13391 | if (!file_mips_gp32) |
252b5132 RH |
13392 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13393 | else | |
13394 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13395 | } | |
316f5878 | 13396 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13397 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13398 | ||
c9914766 | 13399 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13400 | |
13401 | if (mips_32bitmode) | |
13402 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13403 | } | |
13404 | ||
13405 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13406 | \f | |
beae10d5 | 13407 | typedef struct proc { |
9b2f1d35 EC |
13408 | symbolS *func_sym; |
13409 | symbolS *func_end_sym; | |
beae10d5 KH |
13410 | unsigned long reg_mask; |
13411 | unsigned long reg_offset; | |
13412 | unsigned long fpreg_mask; | |
13413 | unsigned long fpreg_offset; | |
13414 | unsigned long frame_offset; | |
13415 | unsigned long frame_reg; | |
13416 | unsigned long pc_reg; | |
13417 | } procS; | |
252b5132 RH |
13418 | |
13419 | static procS cur_proc; | |
13420 | static procS *cur_proc_ptr; | |
13421 | static int numprocs; | |
13422 | ||
0a9ef439 | 13423 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13424 | |
0a9ef439 | 13425 | void |
17a2f251 | 13426 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13427 | { |
0a9ef439 RH |
13428 | if (fragp->fr_type != rs_align_code) |
13429 | return; | |
13430 | ||
13431 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13432 | { |
13433 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13434 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13435 | ||
0a9ef439 RH |
13436 | int bytes; |
13437 | char *p; | |
a19d8eb0 | 13438 | |
0a9ef439 RH |
13439 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13440 | p = fragp->fr_literal + fragp->fr_fix; | |
13441 | ||
13442 | if (bytes & 1) | |
13443 | { | |
13444 | *p++ = 0; | |
f9419b05 | 13445 | fragp->fr_fix++; |
0a9ef439 RH |
13446 | } |
13447 | ||
13448 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13449 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13450 | } |
13451 | ||
0a9ef439 | 13452 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13453 | } |
13454 | ||
252b5132 | 13455 | static void |
17a2f251 | 13456 | md_obj_begin (void) |
252b5132 RH |
13457 | { |
13458 | } | |
13459 | ||
13460 | static void | |
17a2f251 | 13461 | md_obj_end (void) |
252b5132 RH |
13462 | { |
13463 | /* check for premature end, nesting errors, etc */ | |
13464 | if (cur_proc_ptr) | |
9a41af64 | 13465 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13466 | } |
13467 | ||
13468 | static long | |
17a2f251 | 13469 | get_number (void) |
252b5132 RH |
13470 | { |
13471 | int negative = 0; | |
13472 | long val = 0; | |
13473 | ||
13474 | if (*input_line_pointer == '-') | |
13475 | { | |
13476 | ++input_line_pointer; | |
13477 | negative = 1; | |
13478 | } | |
3882b010 | 13479 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13480 | as_bad (_("expected simple number")); |
252b5132 RH |
13481 | if (input_line_pointer[0] == '0') |
13482 | { | |
13483 | if (input_line_pointer[1] == 'x') | |
13484 | { | |
13485 | input_line_pointer += 2; | |
3882b010 | 13486 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13487 | { |
13488 | val <<= 4; | |
13489 | val |= hex_value (*input_line_pointer++); | |
13490 | } | |
13491 | return negative ? -val : val; | |
13492 | } | |
13493 | else | |
13494 | { | |
13495 | ++input_line_pointer; | |
3882b010 | 13496 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13497 | { |
13498 | val <<= 3; | |
13499 | val |= *input_line_pointer++ - '0'; | |
13500 | } | |
13501 | return negative ? -val : val; | |
13502 | } | |
13503 | } | |
3882b010 | 13504 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13505 | { |
13506 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13507 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13508 | as_warn (_("invalid number")); |
252b5132 RH |
13509 | return -1; |
13510 | } | |
3882b010 | 13511 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13512 | { |
13513 | val *= 10; | |
13514 | val += *input_line_pointer++ - '0'; | |
13515 | } | |
13516 | return negative ? -val : val; | |
13517 | } | |
13518 | ||
13519 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13520 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13521 | case .file implies DWARF-2. */ | |
13522 | ||
13523 | static void | |
17a2f251 | 13524 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13525 | { |
ecb4347a DJ |
13526 | static int first_file_directive = 0; |
13527 | ||
c5dd6aab DJ |
13528 | if (ECOFF_DEBUGGING) |
13529 | { | |
13530 | get_number (); | |
13531 | s_app_file (0); | |
13532 | } | |
13533 | else | |
ecb4347a DJ |
13534 | { |
13535 | char *filename; | |
13536 | ||
13537 | filename = dwarf2_directive_file (0); | |
13538 | ||
13539 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13540 | directive even for stabs output. Make sure that this | |
13541 | ".file" is handled. Note that you need a version of GCC | |
13542 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13543 | if (filename != NULL && ! first_file_directive) | |
13544 | { | |
13545 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13546 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13547 | } |
13548 | first_file_directive = 1; | |
13549 | } | |
c5dd6aab DJ |
13550 | } |
13551 | ||
13552 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13553 | |
13554 | static void | |
17a2f251 | 13555 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13556 | { |
c5dd6aab DJ |
13557 | if (!ECOFF_DEBUGGING) |
13558 | dwarf2_directive_loc (0); | |
252b5132 RH |
13559 | } |
13560 | ||
252b5132 RH |
13561 | /* The .end directive. */ |
13562 | ||
13563 | static void | |
17a2f251 | 13564 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13565 | { |
13566 | symbolS *p; | |
252b5132 | 13567 | |
7a621144 DJ |
13568 | /* Following functions need their own .frame and .cprestore directives. */ |
13569 | mips_frame_reg_valid = 0; | |
13570 | mips_cprestore_valid = 0; | |
13571 | ||
252b5132 RH |
13572 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13573 | { | |
13574 | p = get_symbol (); | |
13575 | demand_empty_rest_of_line (); | |
13576 | } | |
13577 | else | |
13578 | p = NULL; | |
13579 | ||
14949570 | 13580 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13581 | as_warn (_(".end not in text section")); |
13582 | ||
13583 | if (!cur_proc_ptr) | |
13584 | { | |
13585 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13586 | demand_empty_rest_of_line (); | |
13587 | return; | |
13588 | } | |
13589 | ||
13590 | if (p != NULL) | |
13591 | { | |
13592 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13593 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13594 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13595 | |
13596 | if (debug_type == DEBUG_STABS) | |
13597 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13598 | S_GET_NAME (p)); | |
252b5132 RH |
13599 | } |
13600 | else | |
13601 | as_warn (_(".end directive missing or unknown symbol")); | |
13602 | ||
2132e3a3 | 13603 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13604 | /* Create an expression to calculate the size of the function. */ |
13605 | if (p && cur_proc_ptr) | |
13606 | { | |
13607 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13608 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13609 | ||
13610 | obj->size = exp; | |
13611 | exp->X_op = O_subtract; | |
13612 | exp->X_add_symbol = symbol_temp_new_now (); | |
13613 | exp->X_op_symbol = p; | |
13614 | exp->X_add_number = 0; | |
13615 | ||
13616 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13617 | } | |
13618 | ||
ecb4347a | 13619 | /* Generate a .pdr section. */ |
dcd410fe RO |
13620 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13621 | && mips_flag_pdr) | |
ecb4347a DJ |
13622 | { |
13623 | segT saved_seg = now_seg; | |
13624 | subsegT saved_subseg = now_subseg; | |
13625 | valueT dot; | |
13626 | expressionS exp; | |
13627 | char *fragp; | |
252b5132 | 13628 | |
ecb4347a | 13629 | dot = frag_now_fix (); |
252b5132 RH |
13630 | |
13631 | #ifdef md_flush_pending_output | |
ecb4347a | 13632 | md_flush_pending_output (); |
252b5132 RH |
13633 | #endif |
13634 | ||
ecb4347a DJ |
13635 | assert (pdr_seg); |
13636 | subseg_set (pdr_seg, 0); | |
252b5132 | 13637 | |
ecb4347a DJ |
13638 | /* Write the symbol. */ |
13639 | exp.X_op = O_symbol; | |
13640 | exp.X_add_symbol = p; | |
13641 | exp.X_add_number = 0; | |
13642 | emit_expr (&exp, 4); | |
252b5132 | 13643 | |
ecb4347a | 13644 | fragp = frag_more (7 * 4); |
252b5132 | 13645 | |
17a2f251 TS |
13646 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13647 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13648 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13649 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13650 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13651 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13652 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13653 | |
ecb4347a DJ |
13654 | subseg_set (saved_seg, saved_subseg); |
13655 | } | |
13656 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13657 | |
13658 | cur_proc_ptr = NULL; | |
13659 | } | |
13660 | ||
13661 | /* The .aent and .ent directives. */ | |
13662 | ||
13663 | static void | |
17a2f251 | 13664 | s_mips_ent (int aent) |
252b5132 | 13665 | { |
252b5132 | 13666 | symbolS *symbolP; |
252b5132 RH |
13667 | |
13668 | symbolP = get_symbol (); | |
13669 | if (*input_line_pointer == ',') | |
f9419b05 | 13670 | ++input_line_pointer; |
252b5132 | 13671 | SKIP_WHITESPACE (); |
3882b010 | 13672 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13673 | || *input_line_pointer == '-') |
874e8986 | 13674 | get_number (); |
252b5132 | 13675 | |
14949570 | 13676 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13677 | as_warn (_(".ent or .aent not in text section.")); |
13678 | ||
13679 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13680 | as_warn (_("missing .end")); |
252b5132 RH |
13681 | |
13682 | if (!aent) | |
13683 | { | |
7a621144 DJ |
13684 | /* This function needs its own .frame and .cprestore directives. */ |
13685 | mips_frame_reg_valid = 0; | |
13686 | mips_cprestore_valid = 0; | |
13687 | ||
252b5132 RH |
13688 | cur_proc_ptr = &cur_proc; |
13689 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13690 | ||
9b2f1d35 | 13691 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13692 | |
49309057 | 13693 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13694 | |
f9419b05 | 13695 | ++numprocs; |
ecb4347a DJ |
13696 | |
13697 | if (debug_type == DEBUG_STABS) | |
13698 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13699 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13700 | } |
13701 | ||
13702 | demand_empty_rest_of_line (); | |
13703 | } | |
13704 | ||
13705 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13706 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13707 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13708 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13709 | symbol table (in the mdebug section). */ |
13710 | ||
13711 | static void | |
17a2f251 | 13712 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13713 | { |
ecb4347a DJ |
13714 | #ifdef OBJ_ELF |
13715 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13716 | { | |
13717 | long val; | |
252b5132 | 13718 | |
ecb4347a DJ |
13719 | if (cur_proc_ptr == (procS *) NULL) |
13720 | { | |
13721 | as_warn (_(".frame outside of .ent")); | |
13722 | demand_empty_rest_of_line (); | |
13723 | return; | |
13724 | } | |
252b5132 | 13725 | |
ecb4347a DJ |
13726 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13727 | ||
13728 | SKIP_WHITESPACE (); | |
13729 | if (*input_line_pointer++ != ',' | |
13730 | || get_absolute_expression_and_terminator (&val) != ',') | |
13731 | { | |
13732 | as_warn (_("Bad .frame directive")); | |
13733 | --input_line_pointer; | |
13734 | demand_empty_rest_of_line (); | |
13735 | return; | |
13736 | } | |
252b5132 | 13737 | |
ecb4347a DJ |
13738 | cur_proc_ptr->frame_offset = val; |
13739 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13740 | |
252b5132 | 13741 | demand_empty_rest_of_line (); |
252b5132 | 13742 | } |
ecb4347a DJ |
13743 | else |
13744 | #endif /* OBJ_ELF */ | |
13745 | s_ignore (ignore); | |
252b5132 RH |
13746 | } |
13747 | ||
bdaaa2e1 KH |
13748 | /* The .fmask and .mask directives. If the mdebug section is present |
13749 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13750 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13751 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13752 | make reference to the ecoff symbol table (in the mdebug section). */ |
13753 | ||
13754 | static void | |
17a2f251 | 13755 | s_mips_mask (int reg_type) |
252b5132 | 13756 | { |
ecb4347a DJ |
13757 | #ifdef OBJ_ELF |
13758 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13759 | { |
ecb4347a | 13760 | long mask, off; |
252b5132 | 13761 | |
ecb4347a DJ |
13762 | if (cur_proc_ptr == (procS *) NULL) |
13763 | { | |
13764 | as_warn (_(".mask/.fmask outside of .ent")); | |
13765 | demand_empty_rest_of_line (); | |
13766 | return; | |
13767 | } | |
252b5132 | 13768 | |
ecb4347a DJ |
13769 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13770 | { | |
13771 | as_warn (_("Bad .mask/.fmask directive")); | |
13772 | --input_line_pointer; | |
13773 | demand_empty_rest_of_line (); | |
13774 | return; | |
13775 | } | |
252b5132 | 13776 | |
ecb4347a DJ |
13777 | off = get_absolute_expression (); |
13778 | ||
13779 | if (reg_type == 'F') | |
13780 | { | |
13781 | cur_proc_ptr->fpreg_mask = mask; | |
13782 | cur_proc_ptr->fpreg_offset = off; | |
13783 | } | |
13784 | else | |
13785 | { | |
13786 | cur_proc_ptr->reg_mask = mask; | |
13787 | cur_proc_ptr->reg_offset = off; | |
13788 | } | |
13789 | ||
13790 | demand_empty_rest_of_line (); | |
252b5132 RH |
13791 | } |
13792 | else | |
ecb4347a DJ |
13793 | #endif /* OBJ_ELF */ |
13794 | s_ignore (reg_type); | |
252b5132 RH |
13795 | } |
13796 | ||
316f5878 RS |
13797 | /* A table describing all the processors gas knows about. Names are |
13798 | matched in the order listed. | |
e7af610e | 13799 | |
316f5878 RS |
13800 | To ease comparison, please keep this table in the same order as |
13801 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13802 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13803 | { | |
316f5878 RS |
13804 | /* Entries for generic ISAs */ |
13805 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13806 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13807 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13808 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13809 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13810 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13811 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13812 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13813 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13814 | |
13815 | /* MIPS I */ | |
13816 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13817 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13818 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13819 | ||
13820 | /* MIPS II */ | |
13821 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13822 | ||
13823 | /* MIPS III */ | |
13824 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13825 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13826 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13827 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13828 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13829 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13830 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13831 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13832 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13833 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13834 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13835 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13836 | ||
13837 | /* MIPS IV */ | |
13838 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13839 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13840 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13841 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13842 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13843 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13844 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13845 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13846 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13847 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13848 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13849 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13850 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13851 | |
13852 | /* MIPS 32 */ | |
fef14a42 | 13853 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13854 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13855 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13856 | |
316f5878 RS |
13857 | /* MIPS 64 */ |
13858 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13859 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13860 | |
c7a23324 | 13861 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13862 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13863 | |
316f5878 RS |
13864 | /* End marker */ |
13865 | { NULL, 0, 0, 0 } | |
13866 | }; | |
e7af610e | 13867 | |
84ea6cf2 | 13868 | |
316f5878 RS |
13869 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13870 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13871 | |
316f5878 | 13872 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13873 | |
b34976b6 | 13874 | static bfd_boolean |
17a2f251 | 13875 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13876 | { |
13877 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13878 | given++, canonical++; | |
13879 | ||
13880 | return ((*given == 0 && *canonical == 0) | |
13881 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13882 | } | |
13883 | ||
13884 | ||
13885 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13886 | CPU name. We've traditionally allowed a lot of variation here. | |
13887 | ||
13888 | Note: this function is shared between GCC and GAS. */ | |
13889 | ||
b34976b6 | 13890 | static bfd_boolean |
17a2f251 | 13891 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13892 | { |
13893 | /* First see if the name matches exactly, or with a final "000" | |
13894 | turned into "k". */ | |
13895 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13896 | return TRUE; |
316f5878 RS |
13897 | |
13898 | /* If not, try comparing based on numerical designation alone. | |
13899 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13900 | if (TOLOWER (*given) == 'r') | |
13901 | given++; | |
13902 | if (!ISDIGIT (*given)) | |
b34976b6 | 13903 | return FALSE; |
316f5878 RS |
13904 | |
13905 | /* Skip over some well-known prefixes in the canonical name, | |
13906 | hoping to find a number there too. */ | |
13907 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13908 | canonical += 2; | |
13909 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13910 | canonical += 2; | |
13911 | else if (TOLOWER (canonical[0]) == 'r') | |
13912 | canonical += 1; | |
13913 | ||
13914 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13915 | } | |
13916 | ||
13917 | ||
13918 | /* Parse an option that takes the name of a processor as its argument. | |
13919 | OPTION is the name of the option and CPU_STRING is the argument. | |
13920 | Return the corresponding processor enumeration if the CPU_STRING is | |
13921 | recognized, otherwise report an error and return null. | |
13922 | ||
13923 | A similar function exists in GCC. */ | |
e7af610e NC |
13924 | |
13925 | static const struct mips_cpu_info * | |
17a2f251 | 13926 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13927 | { |
316f5878 | 13928 | const struct mips_cpu_info *p; |
e7af610e | 13929 | |
316f5878 RS |
13930 | /* 'from-abi' selects the most compatible architecture for the given |
13931 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13932 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13933 | version. Look first at the -mgp options, if given, otherwise base | |
13934 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13935 | |
316f5878 RS |
13936 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13937 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13938 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13939 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13940 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13941 | { | |
13942 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13943 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13944 | ||
13945 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13946 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13947 | ||
13948 | if (file_mips_gp32 >= 0) | |
13949 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13950 | ||
13951 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13952 | ? ISA_MIPS3 | |
13953 | : ISA_MIPS1); | |
13954 | } | |
13955 | ||
13956 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13957 | if (strcasecmp (cpu_string, "default") == 0) | |
13958 | return 0; | |
13959 | ||
13960 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13961 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13962 | return p; | |
13963 | ||
13964 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13965 | return 0; | |
e7af610e NC |
13966 | } |
13967 | ||
316f5878 RS |
13968 | /* Return the canonical processor information for ISA (a member of the |
13969 | ISA_MIPS* enumeration). */ | |
13970 | ||
e7af610e | 13971 | static const struct mips_cpu_info * |
17a2f251 | 13972 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13973 | { |
13974 | int i; | |
13975 | ||
13976 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13977 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13978 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13979 | return (&mips_cpu_info_table[i]); |
13980 | ||
e972090a | 13981 | return NULL; |
e7af610e | 13982 | } |
fef14a42 TS |
13983 | |
13984 | static const struct mips_cpu_info * | |
17a2f251 | 13985 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13986 | { |
13987 | int i; | |
13988 | ||
13989 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13990 | if (arch == mips_cpu_info_table[i].cpu) | |
13991 | return (&mips_cpu_info_table[i]); | |
13992 | ||
13993 | return NULL; | |
13994 | } | |
316f5878 RS |
13995 | \f |
13996 | static void | |
17a2f251 | 13997 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13998 | { |
13999 | if (*first_p) | |
14000 | { | |
14001 | fprintf (stream, "%24s", ""); | |
14002 | *col_p = 24; | |
14003 | } | |
14004 | else | |
14005 | { | |
14006 | fprintf (stream, ", "); | |
14007 | *col_p += 2; | |
14008 | } | |
e7af610e | 14009 | |
316f5878 RS |
14010 | if (*col_p + strlen (string) > 72) |
14011 | { | |
14012 | fprintf (stream, "\n%24s", ""); | |
14013 | *col_p = 24; | |
14014 | } | |
14015 | ||
14016 | fprintf (stream, "%s", string); | |
14017 | *col_p += strlen (string); | |
14018 | ||
14019 | *first_p = 0; | |
14020 | } | |
14021 | ||
14022 | void | |
17a2f251 | 14023 | md_show_usage (FILE *stream) |
e7af610e | 14024 | { |
316f5878 RS |
14025 | int column, first; |
14026 | size_t i; | |
14027 | ||
14028 | fprintf (stream, _("\ | |
14029 | MIPS options:\n\ | |
316f5878 RS |
14030 | -EB generate big endian output\n\ |
14031 | -EL generate little endian output\n\ | |
14032 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14033 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14034 | implicitly with the gp register [default 8]\n")); | |
14035 | fprintf (stream, _("\ | |
14036 | -mips1 generate MIPS ISA I instructions\n\ | |
14037 | -mips2 generate MIPS ISA II instructions\n\ | |
14038 | -mips3 generate MIPS ISA III instructions\n\ | |
14039 | -mips4 generate MIPS ISA IV instructions\n\ | |
14040 | -mips5 generate MIPS ISA V instructions\n\ | |
14041 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14042 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14043 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14044 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14045 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14046 | ||
14047 | first = 1; | |
e7af610e NC |
14048 | |
14049 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14050 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14051 | show (stream, "from-abi", &column, &first); | |
14052 | fputc ('\n', stream); | |
e7af610e | 14053 | |
316f5878 RS |
14054 | fprintf (stream, _("\ |
14055 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14056 | -no-mCPU don't generate code specific to CPU.\n\ | |
14057 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14058 | ||
14059 | first = 1; | |
14060 | ||
14061 | show (stream, "3900", &column, &first); | |
14062 | show (stream, "4010", &column, &first); | |
14063 | show (stream, "4100", &column, &first); | |
14064 | show (stream, "4650", &column, &first); | |
14065 | fputc ('\n', stream); | |
14066 | ||
14067 | fprintf (stream, _("\ | |
14068 | -mips16 generate mips16 instructions\n\ | |
14069 | -no-mips16 do not generate mips16 instructions\n")); | |
14070 | fprintf (stream, _("\ | |
d766e8ec | 14071 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14072 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14073 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14074 | -mno-shared optimize output for executables\n\ |
14075 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14076 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14077 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14078 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14079 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14080 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14081 | #ifdef OBJ_ELF | |
14082 | fprintf (stream, _("\ | |
14083 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14084 | -non_shared do not generate position independent code\n\ | |
14085 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14086 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14087 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14088 | non-shared code\n\ | |
316f5878 RS |
14089 | -mabi=ABI create ABI conformant object file for:\n")); |
14090 | ||
14091 | first = 1; | |
14092 | ||
14093 | show (stream, "32", &column, &first); | |
14094 | show (stream, "o64", &column, &first); | |
14095 | show (stream, "n32", &column, &first); | |
14096 | show (stream, "64", &column, &first); | |
14097 | show (stream, "eabi", &column, &first); | |
14098 | ||
14099 | fputc ('\n', stream); | |
14100 | ||
14101 | fprintf (stream, _("\ | |
14102 | -32 create o32 ABI object file (default)\n\ | |
14103 | -n32 create n32 ABI object file\n\ | |
14104 | -64 create 64 ABI object file\n")); | |
14105 | #endif | |
e7af610e | 14106 | } |
14e777e0 KB |
14107 | |
14108 | enum dwarf2_format | |
17a2f251 | 14109 | mips_dwarf2_format (void) |
14e777e0 KB |
14110 | { |
14111 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14112 | { |
14113 | #ifdef TE_IRIX | |
14114 | return dwarf2_format_64bit_irix; | |
14115 | #else | |
14116 | return dwarf2_format_64bit; | |
14117 | #endif | |
14118 | } | |
14e777e0 KB |
14119 | else |
14120 | return dwarf2_format_32bit; | |
14121 | } | |
73369e65 EC |
14122 | |
14123 | int | |
14124 | mips_dwarf2_addr_size (void) | |
14125 | { | |
14126 | if (mips_abi == N64_ABI) | |
14127 | return 8; | |
73369e65 EC |
14128 | else |
14129 | return 4; | |
14130 | } |