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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
45dfa85a | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
47e39b9d | 148 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
149 | a copy of INSN_MO->match with the operands filled in. If we have |
150 | decided to use an extended MIPS16 instruction, this includes the | |
151 | extension. */ | |
47e39b9d RS |
152 | unsigned long insn_opcode; |
153 | ||
154 | /* The frag that contains the instruction. */ | |
155 | struct frag *frag; | |
156 | ||
157 | /* The offset into FRAG of the first instruction byte. */ | |
158 | long where; | |
159 | ||
160 | /* The relocs associated with the instruction, if any. */ | |
161 | fixS *fixp[3]; | |
162 | ||
a38419a5 RS |
163 | /* True if this entry cannot be moved from its current position. */ |
164 | unsigned int fixed_p : 1; | |
47e39b9d | 165 | |
708587a4 | 166 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
167 | unsigned int noreorder_p : 1; |
168 | ||
2fa15973 RS |
169 | /* True for mips16 instructions that jump to an absolute address. */ |
170 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
171 | |
172 | /* True if this instruction is complete. */ | |
173 | unsigned int complete_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
1f25f5d3 CD |
207 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
208 | if they have not been initialized. Changed by `.set <asename>', by | |
209 | command line options, and based on the default architecture. */ | |
210 | int ase_mips3d; | |
deec1734 | 211 | int ase_mdmx; |
e16bfa71 | 212 | int ase_smartmips; |
74cd071d | 213 | int ase_dsp; |
8b082fb1 | 214 | int ase_dspr2; |
ef2e4d86 | 215 | int ase_mt; |
dec0624d | 216 | int ase_mcu; |
252b5132 RH |
217 | /* Whether we are assembling for the mips16 processor. 0 if we are |
218 | not, 1 if we are, and -1 if the value has not been initialized. | |
219 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
220 | -nomips16 command line options, and the default CPU. */ | |
221 | int mips16; | |
df58fc94 RS |
222 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
223 | 1 if we are, and -1 if the value has not been initialized. Changed | |
224 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
225 | and -mno-micromips command line options, and the default CPU. */ | |
226 | int micromips; | |
252b5132 RH |
227 | /* Non-zero if we should not reorder instructions. Changed by `.set |
228 | reorder' and `.set noreorder'. */ | |
229 | int noreorder; | |
741fe287 MR |
230 | /* Non-zero if we should not permit the register designated "assembler |
231 | temporary" to be used in instructions. The value is the register | |
232 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
233 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
234 | unsigned int at; | |
252b5132 RH |
235 | /* Non-zero if we should warn when a macro instruction expands into |
236 | more than one machine instruction. Changed by `.set nomacro' and | |
237 | `.set macro'. */ | |
238 | int warn_about_macros; | |
239 | /* Non-zero if we should not move instructions. Changed by `.set | |
240 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
241 | int nomove; | |
242 | /* Non-zero if we should not optimize branches by moving the target | |
243 | of the branch into the delay slot. Actually, we don't perform | |
244 | this optimization anyhow. Changed by `.set bopt' and `.set | |
245 | nobopt'. */ | |
246 | int nobopt; | |
247 | /* Non-zero if we should not autoextend mips16 instructions. | |
248 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
249 | int noautoextend; | |
a325df1d TS |
250 | /* Restrict general purpose registers and floating point registers |
251 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
252 | is passed but can changed if the assembler code uses .set mipsN. */ | |
253 | int gp32; | |
254 | int fp32; | |
fef14a42 TS |
255 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
256 | command line option, and the default CPU. */ | |
257 | int arch; | |
aed1a261 RS |
258 | /* True if ".set sym32" is in effect. */ |
259 | bfd_boolean sym32; | |
037b32b9 AN |
260 | /* True if floating-point operations are not allowed. Changed by .set |
261 | softfloat or .set hardfloat, by command line options -msoft-float or | |
262 | -mhard-float. The default is false. */ | |
263 | bfd_boolean soft_float; | |
264 | ||
265 | /* True if only single-precision floating-point operations are allowed. | |
266 | Changed by .set singlefloat or .set doublefloat, command-line options | |
267 | -msingle-float or -mdouble-float. The default is false. */ | |
268 | bfd_boolean single_float; | |
252b5132 RH |
269 | }; |
270 | ||
037b32b9 AN |
271 | /* This is the struct we use to hold the current set of options. Note |
272 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
273 | -1 to indicate that they have not been initialized. */ | |
274 | ||
a325df1d | 275 | /* True if -mgp32 was passed. */ |
a8e8e863 | 276 | static int file_mips_gp32 = -1; |
a325df1d TS |
277 | |
278 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 279 | static int file_mips_fp32 = -1; |
a325df1d | 280 | |
037b32b9 AN |
281 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
282 | static int file_mips_soft_float = 0; | |
283 | ||
284 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
285 | static int file_mips_single_float = 0; | |
252b5132 | 286 | |
e972090a NC |
287 | static struct mips_set_options mips_opts = |
288 | { | |
037b32b9 AN |
289 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
290 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
291 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
292 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
293 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
294 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 295 | }; |
252b5132 RH |
296 | |
297 | /* These variables are filled in with the masks of registers used. | |
298 | The object format code reads them and puts them in the appropriate | |
299 | place. */ | |
300 | unsigned long mips_gprmask; | |
301 | unsigned long mips_cprmask[4]; | |
302 | ||
303 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 304 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 305 | |
738f4d98 | 306 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
307 | static int file_ase_mips16; |
308 | ||
3994f87e TS |
309 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
310 | || mips_opts.isa == ISA_MIPS32R2 \ | |
311 | || mips_opts.isa == ISA_MIPS64 \ | |
312 | || mips_opts.isa == ISA_MIPS64R2) | |
313 | ||
df58fc94 RS |
314 | /* True if any microMIPS code was produced. */ |
315 | static int file_ase_micromips; | |
316 | ||
b12dd2e4 CF |
317 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
318 | #ifdef TE_IRIX | |
1180b5a4 | 319 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 320 | #else |
1180b5a4 RS |
321 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
322 | because there's no place for any addend, the only acceptable | |
323 | expression is a bare symbol. */ | |
324 | #define MIPS_JALR_HINT_P(EXPR) \ | |
325 | (!HAVE_IN_PLACE_ADDENDS \ | |
326 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
327 | #endif |
328 | ||
1f25f5d3 CD |
329 | /* True if -mips3d was passed or implied by arguments passed on the |
330 | command line (e.g., by -march). */ | |
331 | static int file_ase_mips3d; | |
332 | ||
deec1734 CD |
333 | /* True if -mdmx was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mdmx; | |
336 | ||
e16bfa71 TS |
337 | /* True if -msmartmips was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_smartmips; | |
340 | ||
ad3fea08 TS |
341 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
342 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 343 | |
74cd071d CF |
344 | /* True if -mdsp was passed or implied by arguments passed on the |
345 | command line (e.g., by -march). */ | |
346 | static int file_ase_dsp; | |
347 | ||
ad3fea08 | 348 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
03f66e8a MR |
349 | || mips_opts.isa == ISA_MIPS64R2 \ |
350 | || mips_opts.micromips) | |
ad3fea08 | 351 | |
65263ce3 TS |
352 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
353 | ||
8b082fb1 TS |
354 | /* True if -mdspr2 was passed or implied by arguments passed on the |
355 | command line (e.g., by -march). */ | |
356 | static int file_ase_dspr2; | |
357 | ||
358 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
03f66e8a MR |
359 | || mips_opts.isa == ISA_MIPS64R2 \ |
360 | || mips_opts.micromips) | |
8b082fb1 | 361 | |
ef2e4d86 CF |
362 | /* True if -mmt was passed or implied by arguments passed on the |
363 | command line (e.g., by -march). */ | |
364 | static int file_ase_mt; | |
365 | ||
ad3fea08 TS |
366 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
367 | || mips_opts.isa == ISA_MIPS64R2) | |
368 | ||
dec0624d | 369 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
370 | || mips_opts.isa == ISA_MIPS64R2 \ |
371 | || mips_opts.micromips) | |
dec0624d | 372 | |
ec68c924 | 373 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 374 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 375 | static const char *mips_arch_string; |
ec68c924 EC |
376 | |
377 | /* The argument of the -mtune= flag. The architecture for which we | |
378 | are optimizing. */ | |
379 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 380 | static const char *mips_tune_string; |
ec68c924 | 381 | |
316f5878 | 382 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
383 | static int mips_32bitmode = 0; |
384 | ||
316f5878 RS |
385 | /* True if the given ABI requires 32-bit registers. */ |
386 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
387 | ||
388 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
389 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
390 | ((ABI) == N32_ABI \ | |
391 | || (ABI) == N64_ABI \ | |
316f5878 RS |
392 | || (ABI) == O64_ABI) |
393 | ||
ad3fea08 | 394 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
395 | #define ISA_HAS_64BIT_REGS(ISA) \ |
396 | ((ISA) == ISA_MIPS3 \ | |
397 | || (ISA) == ISA_MIPS4 \ | |
398 | || (ISA) == ISA_MIPS5 \ | |
399 | || (ISA) == ISA_MIPS64 \ | |
400 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 401 | |
ad3fea08 TS |
402 | /* Return true if ISA supports 64 bit wide float registers. */ |
403 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
404 | ((ISA) == ISA_MIPS3 \ | |
405 | || (ISA) == ISA_MIPS4 \ | |
406 | || (ISA) == ISA_MIPS5 \ | |
407 | || (ISA) == ISA_MIPS32R2 \ | |
408 | || (ISA) == ISA_MIPS64 \ | |
409 | || (ISA) == ISA_MIPS64R2) | |
410 | ||
af7ee8bf CD |
411 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
412 | instructions. */ | |
707bfff6 | 413 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
414 | ((ISA) == ISA_MIPS64R2 \ |
415 | || (mips_opts.micromips \ | |
416 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
417 | ) | |
af7ee8bf CD |
418 | |
419 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
420 | instructions. */ | |
707bfff6 TS |
421 | #define ISA_HAS_ROR(ISA) \ |
422 | ((ISA) == ISA_MIPS32R2 \ | |
423 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
424 | || mips_opts.ase_smartmips \ |
425 | || mips_opts.micromips \ | |
426 | ) | |
707bfff6 | 427 | |
7455baf8 TS |
428 | /* Return true if ISA supports single-precision floats in odd registers. */ |
429 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
430 | ((ISA) == ISA_MIPS32 \ | |
431 | || (ISA) == ISA_MIPS32R2 \ | |
432 | || (ISA) == ISA_MIPS64 \ | |
433 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 434 | |
ad3fea08 TS |
435 | /* Return true if ISA supports move to/from high part of a 64-bit |
436 | floating-point register. */ | |
437 | #define ISA_HAS_MXHC1(ISA) \ | |
438 | ((ISA) == ISA_MIPS32R2 \ | |
439 | || (ISA) == ISA_MIPS64R2) | |
440 | ||
e013f690 | 441 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 442 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 443 | |
e013f690 | 444 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 445 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 446 | |
ad3fea08 TS |
447 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
448 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 449 | |
316f5878 | 450 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 451 | |
316f5878 | 452 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 453 | |
3b91255e RS |
454 | /* True if relocations are stored in-place. */ |
455 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
456 | ||
aed1a261 RS |
457 | /* The ABI-derived address size. */ |
458 | #define HAVE_64BIT_ADDRESSES \ | |
459 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
460 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 461 | |
aed1a261 RS |
462 | /* The size of symbolic constants (i.e., expressions of the form |
463 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
464 | #define HAVE_32BIT_SYMBOLS \ | |
465 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
466 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 467 | |
b7c7d6c1 TS |
468 | /* Addresses are loaded in different ways, depending on the address size |
469 | in use. The n32 ABI Documentation also mandates the use of additions | |
470 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 471 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 472 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
473 | |
474 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 475 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
476 | |
477 | #define ADDRESS_LOAD_INSN \ | |
478 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
479 | ||
480 | #define ADDRESS_STORE_INSN \ | |
481 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
482 | ||
a4672219 | 483 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
484 | #define CPU_HAS_MIPS16(cpu) \ |
485 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
486 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 487 | |
2309ddf2 | 488 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
489 | #define CPU_HAS_MICROMIPS(cpu) 0 |
490 | ||
60b63b72 RS |
491 | /* True if CPU has a dror instruction. */ |
492 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
493 | ||
494 | /* True if CPU has a ror instruction. */ | |
495 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
496 | ||
dd6a37e7 | 497 | /* True if CPU is in the Octeon family */ |
432233b3 | 498 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 499 | |
dd3cbb7e | 500 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 501 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 502 | |
c8978940 CD |
503 | /* True if mflo and mfhi can be immediately followed by instructions |
504 | which write to the HI and LO registers. | |
505 | ||
506 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
507 | (at least) two instructions between the reads of HI/LO and | |
508 | instructions which write them, and later ISAs do not. Contradicting | |
509 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
510 | the UM for the NEC Vr5000) document needing the instructions between | |
511 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
512 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
513 | earlier-ISA CPUs for which CPU documentation declares that the | |
514 | instructions are really interlocked. */ | |
515 | #define hilo_interlocks \ | |
516 | (mips_opts.isa == ISA_MIPS32 \ | |
517 | || mips_opts.isa == ISA_MIPS32R2 \ | |
518 | || mips_opts.isa == ISA_MIPS64 \ | |
519 | || mips_opts.isa == ISA_MIPS64R2 \ | |
520 | || mips_opts.arch == CPU_R4010 \ | |
521 | || mips_opts.arch == CPU_R10000 \ | |
522 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
523 | || mips_opts.arch == CPU_R14000 \ |
524 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 525 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 526 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 527 | || mips_opts.micromips \ |
c8978940 | 528 | ) |
252b5132 RH |
529 | |
530 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
531 | from the GPRs after they are loaded from memory, and thus does not |
532 | require nops to be inserted. This applies to instructions marked | |
533 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
534 | level I and microMIPS mode instructions are always interlocked. */ |
535 | #define gpr_interlocks \ | |
536 | (mips_opts.isa != ISA_MIPS1 \ | |
537 | || mips_opts.arch == CPU_R3900 \ | |
538 | || mips_opts.micromips \ | |
539 | ) | |
252b5132 | 540 | |
81912461 ILT |
541 | /* Whether the processor uses hardware interlocks to avoid delays |
542 | required by coprocessor instructions, and thus does not require | |
543 | nops to be inserted. This applies to instructions marked | |
544 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
545 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
546 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
547 | levels I, II, and III and microMIPS mode instructions are always |
548 | interlocked. */ | |
bdaaa2e1 | 549 | /* Itbl support may require additional care here. */ |
81912461 ILT |
550 | #define cop_interlocks \ |
551 | ((mips_opts.isa != ISA_MIPS1 \ | |
552 | && mips_opts.isa != ISA_MIPS2 \ | |
553 | && mips_opts.isa != ISA_MIPS3) \ | |
554 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 555 | || mips_opts.micromips \ |
81912461 ILT |
556 | ) |
557 | ||
558 | /* Whether the processor uses hardware interlocks to protect reads | |
559 | from coprocessor registers after they are loaded from memory, and | |
560 | thus does not require nops to be inserted. This applies to | |
561 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
562 | requires at MIPS ISA level I and microMIPS mode instructions are |
563 | always interlocked. */ | |
564 | #define cop_mem_interlocks \ | |
565 | (mips_opts.isa != ISA_MIPS1 \ | |
566 | || mips_opts.micromips \ | |
567 | ) | |
252b5132 | 568 | |
6b76fefe CM |
569 | /* Is this a mfhi or mflo instruction? */ |
570 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
571 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
572 | ||
df58fc94 RS |
573 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
574 | has been selected. This implies, in particular, that addresses of text | |
575 | labels have their LSB set. */ | |
576 | #define HAVE_CODE_COMPRESSION \ | |
577 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
578 | ||
252b5132 RH |
579 | /* MIPS PIC level. */ |
580 | ||
a161fe53 | 581 | enum mips_pic_level mips_pic; |
252b5132 | 582 | |
c9914766 | 583 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 584 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 585 | static int mips_big_got = 0; |
252b5132 RH |
586 | |
587 | /* 1 if trap instructions should used for overflow rather than break | |
588 | instructions. */ | |
c9914766 | 589 | static int mips_trap = 0; |
252b5132 | 590 | |
119d663a | 591 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 592 | by assembling two single width halves into two single width floating |
119d663a NC |
593 | point registers which just happen to alias the double width destination |
594 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 595 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
596 | automatically at assemble time. */ |
597 | static int mips_disable_float_construction; | |
598 | ||
252b5132 RH |
599 | /* Non-zero if any .set noreorder directives were used. */ |
600 | ||
601 | static int mips_any_noreorder; | |
602 | ||
6b76fefe CM |
603 | /* Non-zero if nops should be inserted when the register referenced in |
604 | an mfhi/mflo instruction is read in the next two instructions. */ | |
605 | static int mips_7000_hilo_fix; | |
606 | ||
02ffd3e4 | 607 | /* The size of objects in the small data section. */ |
156c2f8b | 608 | static unsigned int g_switch_value = 8; |
252b5132 RH |
609 | /* Whether the -G option was used. */ |
610 | static int g_switch_seen = 0; | |
611 | ||
612 | #define N_RMASK 0xc4 | |
613 | #define N_VFP 0xd4 | |
614 | ||
615 | /* If we can determine in advance that GP optimization won't be | |
616 | possible, we can skip the relaxation stuff that tries to produce | |
617 | GP-relative references. This makes delay slot optimization work | |
618 | better. | |
619 | ||
620 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
621 | gcc output. It needs to guess right for gcc, otherwise gcc |
622 | will put what it thinks is a GP-relative instruction in a branch | |
623 | delay slot. | |
252b5132 RH |
624 | |
625 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
626 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 627 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
628 | |
629 | /* handle of the OPCODE hash table */ | |
630 | static struct hash_control *op_hash = NULL; | |
631 | ||
632 | /* The opcode hash table we use for the mips16. */ | |
633 | static struct hash_control *mips16_op_hash = NULL; | |
634 | ||
df58fc94 RS |
635 | /* The opcode hash table we use for the microMIPS ASE. */ |
636 | static struct hash_control *micromips_op_hash = NULL; | |
637 | ||
252b5132 RH |
638 | /* This array holds the chars that always start a comment. If the |
639 | pre-processor is disabled, these aren't very useful */ | |
640 | const char comment_chars[] = "#"; | |
641 | ||
642 | /* This array holds the chars that only start a comment at the beginning of | |
643 | a line. If the line seems to have the form '# 123 filename' | |
644 | .line and .file directives will appear in the pre-processed output */ | |
645 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
646 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 647 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
648 | /* Also note that C style comments are always supported. */ |
649 | const char line_comment_chars[] = "#"; | |
650 | ||
bdaaa2e1 | 651 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 652 | const char line_separator_chars[] = ";"; |
252b5132 RH |
653 | |
654 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
655 | const char EXP_CHARS[] = "eE"; | |
656 | ||
657 | /* Chars that mean this number is a floating point constant */ | |
658 | /* As in 0f12.456 */ | |
659 | /* or 0d1.2345e12 */ | |
660 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
661 | ||
662 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
663 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
664 | but nothing is ideal around here. | |
665 | */ | |
666 | ||
667 | static char *insn_error; | |
668 | ||
669 | static int auto_align = 1; | |
670 | ||
671 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
672 | offset in the stack frame from which to restore the $gp register. | |
673 | This is set by the .cprestore pseudo-op, and saved in this | |
674 | variable. */ | |
675 | static offsetT mips_cprestore_offset = -1; | |
676 | ||
67c1ffbe | 677 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 678 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 679 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
680 | static offsetT mips_cpreturn_offset = -1; |
681 | static int mips_cpreturn_register = -1; | |
682 | static int mips_gp_register = GP; | |
def2e0dd | 683 | static int mips_gprel_offset = 0; |
6478892d | 684 | |
7a621144 DJ |
685 | /* Whether mips_cprestore_offset has been set in the current function |
686 | (or whether it has already been warned about, if not). */ | |
687 | static int mips_cprestore_valid = 0; | |
688 | ||
252b5132 RH |
689 | /* This is the register which holds the stack frame, as set by the |
690 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
691 | static int mips_frame_reg = SP; | |
692 | ||
7a621144 DJ |
693 | /* Whether mips_frame_reg has been set in the current function |
694 | (or whether it has already been warned about, if not). */ | |
695 | static int mips_frame_reg_valid = 0; | |
696 | ||
252b5132 RH |
697 | /* To output NOP instructions correctly, we need to keep information |
698 | about the previous two instructions. */ | |
699 | ||
700 | /* Whether we are optimizing. The default value of 2 means to remove | |
701 | unneeded NOPs and swap branch instructions when possible. A value | |
702 | of 1 means to not swap branches. A value of 0 means to always | |
703 | insert NOPs. */ | |
704 | static int mips_optimize = 2; | |
705 | ||
706 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
707 | equivalent to seeing no -g option at all. */ | |
708 | static int mips_debug = 0; | |
709 | ||
7d8e00cf RS |
710 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
711 | #define MAX_VR4130_NOPS 4 | |
712 | ||
713 | /* The maximum number of NOPs needed to fill delay slots. */ | |
714 | #define MAX_DELAY_NOPS 2 | |
715 | ||
716 | /* The maximum number of NOPs needed for any purpose. */ | |
717 | #define MAX_NOPS 4 | |
71400594 RS |
718 | |
719 | /* A list of previous instructions, with index 0 being the most recent. | |
720 | We need to look back MAX_NOPS instructions when filling delay slots | |
721 | or working around processor errata. We need to look back one | |
722 | instruction further if we're thinking about using history[0] to | |
723 | fill a branch delay slot. */ | |
724 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 725 | |
1e915849 | 726 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
727 | static struct mips_cl_insn nop_insn; |
728 | static struct mips_cl_insn mips16_nop_insn; | |
729 | static struct mips_cl_insn micromips_nop16_insn; | |
730 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
731 | |
732 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
733 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
734 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
735 | ||
736 | /* The size of NOP_INSN in bytes. */ | |
737 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 738 | |
252b5132 RH |
739 | /* If this is set, it points to a frag holding nop instructions which |
740 | were inserted before the start of a noreorder section. If those | |
741 | nops turn out to be unnecessary, the size of the frag can be | |
742 | decreased. */ | |
743 | static fragS *prev_nop_frag; | |
744 | ||
745 | /* The number of nop instructions we created in prev_nop_frag. */ | |
746 | static int prev_nop_frag_holds; | |
747 | ||
748 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 749 | prev_nop_frag. */ |
252b5132 RH |
750 | static int prev_nop_frag_required; |
751 | ||
752 | /* The number of instructions we've seen since prev_nop_frag. */ | |
753 | static int prev_nop_frag_since; | |
754 | ||
755 | /* For ECOFF and ELF, relocations against symbols are done in two | |
756 | parts, with a HI relocation and a LO relocation. Each relocation | |
757 | has only 16 bits of space to store an addend. This means that in | |
758 | order for the linker to handle carries correctly, it must be able | |
759 | to locate both the HI and the LO relocation. This means that the | |
760 | relocations must appear in order in the relocation table. | |
761 | ||
762 | In order to implement this, we keep track of each unmatched HI | |
763 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 764 | corresponding LO relocation. */ |
252b5132 | 765 | |
e972090a NC |
766 | struct mips_hi_fixup |
767 | { | |
252b5132 RH |
768 | /* Next HI fixup. */ |
769 | struct mips_hi_fixup *next; | |
770 | /* This fixup. */ | |
771 | fixS *fixp; | |
772 | /* The section this fixup is in. */ | |
773 | segT seg; | |
774 | }; | |
775 | ||
776 | /* The list of unmatched HI relocs. */ | |
777 | ||
778 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
779 | ||
64bdfcaf RS |
780 | /* The frag containing the last explicit relocation operator. |
781 | Null if explicit relocations have not been used. */ | |
782 | ||
783 | static fragS *prev_reloc_op_frag; | |
784 | ||
252b5132 RH |
785 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
786 | ||
787 | #define X ILLEGAL_REG | |
e972090a NC |
788 | static const int mips32_to_16_reg_map[] = |
789 | { | |
252b5132 RH |
790 | X, X, 2, 3, 4, 5, 6, 7, |
791 | X, X, X, X, X, X, X, X, | |
792 | 0, 1, X, X, X, X, X, X, | |
793 | X, X, X, X, X, X, X, X | |
794 | }; | |
795 | #undef X | |
796 | ||
797 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
798 | ||
e972090a NC |
799 | static const unsigned int mips16_to_32_reg_map[] = |
800 | { | |
252b5132 RH |
801 | 16, 17, 2, 3, 4, 5, 6, 7 |
802 | }; | |
60b63b72 | 803 | |
df58fc94 RS |
804 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
805 | ||
806 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
807 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
808 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
809 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
810 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
811 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
812 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
813 | ||
814 | #define X ILLEGAL_REG | |
815 | /* reg type h: 4, 5, 6. */ | |
816 | static const int mips32_to_micromips_reg_h_map[] = | |
817 | { | |
818 | X, X, X, X, 4, 5, 6, X, | |
819 | X, X, X, X, X, X, X, X, | |
820 | X, X, X, X, X, X, X, X, | |
821 | X, X, X, X, X, X, X, X | |
822 | }; | |
823 | ||
824 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
825 | static const int mips32_to_micromips_reg_m_map[] = | |
826 | { | |
827 | 0, X, 2, 3, X, X, X, X, | |
828 | X, X, X, X, X, X, X, X, | |
829 | 4, 1, 5, 6, 7, X, X, X, | |
830 | X, X, X, X, X, X, X, X | |
831 | }; | |
832 | ||
833 | /* reg type q: 0, 2-7. 17. */ | |
834 | static const int mips32_to_micromips_reg_q_map[] = | |
835 | { | |
836 | 0, X, 2, 3, 4, 5, 6, 7, | |
837 | X, X, X, X, X, X, X, X, | |
838 | X, 1, X, X, X, X, X, X, | |
839 | X, X, X, X, X, X, X, X | |
840 | }; | |
841 | ||
842 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
843 | #undef X | |
844 | ||
845 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
846 | ||
847 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
848 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
849 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
850 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
851 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
852 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
853 | ||
854 | /* The microMIPS registers with type h. */ | |
855 | static const unsigned int micromips_to_32_reg_h_map[] = | |
856 | { | |
857 | 5, 5, 6, 4, 4, 4, 4, 4 | |
858 | }; | |
859 | ||
860 | /* The microMIPS registers with type i. */ | |
861 | static const unsigned int micromips_to_32_reg_i_map[] = | |
862 | { | |
863 | 6, 7, 7, 21, 22, 5, 6, 7 | |
864 | }; | |
865 | ||
866 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
867 | ||
868 | /* The microMIPS registers with type m. */ | |
869 | static const unsigned int micromips_to_32_reg_m_map[] = | |
870 | { | |
871 | 0, 17, 2, 3, 16, 18, 19, 20 | |
872 | }; | |
873 | ||
874 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
875 | ||
876 | /* The microMIPS registers with type q. */ | |
877 | static const unsigned int micromips_to_32_reg_q_map[] = | |
878 | { | |
879 | 0, 17, 2, 3, 4, 5, 6, 7 | |
880 | }; | |
881 | ||
882 | /* microMIPS imm type B. */ | |
883 | static const int micromips_imm_b_map[] = | |
884 | { | |
885 | 1, 4, 8, 12, 16, 20, 24, -1 | |
886 | }; | |
887 | ||
888 | /* microMIPS imm type C. */ | |
889 | static const int micromips_imm_c_map[] = | |
890 | { | |
891 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
892 | }; | |
893 | ||
71400594 RS |
894 | /* Classifies the kind of instructions we're interested in when |
895 | implementing -mfix-vr4120. */ | |
c67a084a NC |
896 | enum fix_vr4120_class |
897 | { | |
71400594 RS |
898 | FIX_VR4120_MACC, |
899 | FIX_VR4120_DMACC, | |
900 | FIX_VR4120_MULT, | |
901 | FIX_VR4120_DMULT, | |
902 | FIX_VR4120_DIV, | |
903 | FIX_VR4120_MTHILO, | |
904 | NUM_FIX_VR4120_CLASSES | |
905 | }; | |
906 | ||
c67a084a NC |
907 | /* ...likewise -mfix-loongson2f-jump. */ |
908 | static bfd_boolean mips_fix_loongson2f_jump; | |
909 | ||
910 | /* ...likewise -mfix-loongson2f-nop. */ | |
911 | static bfd_boolean mips_fix_loongson2f_nop; | |
912 | ||
913 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
914 | static bfd_boolean mips_fix_loongson2f; | |
915 | ||
71400594 RS |
916 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
917 | there must be at least one other instruction between an instruction | |
918 | of type X and an instruction of type Y. */ | |
919 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
920 | ||
921 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 922 | static int mips_fix_vr4120; |
4a6a3df4 | 923 | |
7d8e00cf RS |
924 | /* ...likewise -mfix-vr4130. */ |
925 | static int mips_fix_vr4130; | |
926 | ||
6a32d874 CM |
927 | /* ...likewise -mfix-24k. */ |
928 | static int mips_fix_24k; | |
929 | ||
d954098f DD |
930 | /* ...likewise -mfix-cn63xxp1 */ |
931 | static bfd_boolean mips_fix_cn63xxp1; | |
932 | ||
4a6a3df4 AO |
933 | /* We don't relax branches by default, since this causes us to expand |
934 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
935 | fail to compute the offset before expanding the macro to the most | |
936 | efficient expansion. */ | |
937 | ||
938 | static int mips_relax_branch; | |
252b5132 | 939 | \f |
4d7206a2 RS |
940 | /* The expansion of many macros depends on the type of symbol that |
941 | they refer to. For example, when generating position-dependent code, | |
942 | a macro that refers to a symbol may have two different expansions, | |
943 | one which uses GP-relative addresses and one which uses absolute | |
944 | addresses. When generating SVR4-style PIC, a macro may have | |
945 | different expansions for local and global symbols. | |
946 | ||
947 | We handle these situations by generating both sequences and putting | |
948 | them in variant frags. In position-dependent code, the first sequence | |
949 | will be the GP-relative one and the second sequence will be the | |
950 | absolute one. In SVR4 PIC, the first sequence will be for global | |
951 | symbols and the second will be for local symbols. | |
952 | ||
584892a6 RS |
953 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
954 | SECOND are the lengths of the two sequences in bytes. These fields | |
955 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
956 | the subtype has the following flags: | |
4d7206a2 | 957 | |
584892a6 RS |
958 | RELAX_USE_SECOND |
959 | Set if it has been decided that we should use the second | |
960 | sequence instead of the first. | |
961 | ||
962 | RELAX_SECOND_LONGER | |
963 | Set in the first variant frag if the macro's second implementation | |
964 | is longer than its first. This refers to the macro as a whole, | |
965 | not an individual relaxation. | |
966 | ||
967 | RELAX_NOMACRO | |
968 | Set in the first variant frag if the macro appeared in a .set nomacro | |
969 | block and if one alternative requires a warning but the other does not. | |
970 | ||
971 | RELAX_DELAY_SLOT | |
972 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
973 | delay slot. | |
4d7206a2 | 974 | |
df58fc94 RS |
975 | RELAX_DELAY_SLOT_16BIT |
976 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
977 | 16-bit instruction. | |
978 | ||
979 | RELAX_DELAY_SLOT_SIZE_FIRST | |
980 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
981 | the macro is of the wrong size for the branch delay slot. | |
982 | ||
983 | RELAX_DELAY_SLOT_SIZE_SECOND | |
984 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
985 | the macro is of the wrong size for the branch delay slot. | |
986 | ||
4d7206a2 RS |
987 | The frag's "opcode" points to the first fixup for relaxable code. |
988 | ||
989 | Relaxable macros are generated using a sequence such as: | |
990 | ||
991 | relax_start (SYMBOL); | |
992 | ... generate first expansion ... | |
993 | relax_switch (); | |
994 | ... generate second expansion ... | |
995 | relax_end (); | |
996 | ||
997 | The code and fixups for the unwanted alternative are discarded | |
998 | by md_convert_frag. */ | |
584892a6 | 999 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1000 | |
584892a6 RS |
1001 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1002 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1003 | #define RELAX_USE_SECOND 0x10000 | |
1004 | #define RELAX_SECOND_LONGER 0x20000 | |
1005 | #define RELAX_NOMACRO 0x40000 | |
1006 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1007 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1008 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1009 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1010 | |
4a6a3df4 AO |
1011 | /* Branch without likely bit. If label is out of range, we turn: |
1012 | ||
1013 | beq reg1, reg2, label | |
1014 | delay slot | |
1015 | ||
1016 | into | |
1017 | ||
1018 | bne reg1, reg2, 0f | |
1019 | nop | |
1020 | j label | |
1021 | 0: delay slot | |
1022 | ||
1023 | with the following opcode replacements: | |
1024 | ||
1025 | beq <-> bne | |
1026 | blez <-> bgtz | |
1027 | bltz <-> bgez | |
1028 | bc1f <-> bc1t | |
1029 | ||
1030 | bltzal <-> bgezal (with jal label instead of j label) | |
1031 | ||
1032 | Even though keeping the delay slot instruction in the delay slot of | |
1033 | the branch would be more efficient, it would be very tricky to do | |
1034 | correctly, because we'd have to introduce a variable frag *after* | |
1035 | the delay slot instruction, and expand that instead. Let's do it | |
1036 | the easy way for now, even if the branch-not-taken case now costs | |
1037 | one additional instruction. Out-of-range branches are not supposed | |
1038 | to be common, anyway. | |
1039 | ||
1040 | Branch likely. If label is out of range, we turn: | |
1041 | ||
1042 | beql reg1, reg2, label | |
1043 | delay slot (annulled if branch not taken) | |
1044 | ||
1045 | into | |
1046 | ||
1047 | beql reg1, reg2, 1f | |
1048 | nop | |
1049 | beql $0, $0, 2f | |
1050 | nop | |
1051 | 1: j[al] label | |
1052 | delay slot (executed only if branch taken) | |
1053 | 2: | |
1054 | ||
1055 | It would be possible to generate a shorter sequence by losing the | |
1056 | likely bit, generating something like: | |
b34976b6 | 1057 | |
4a6a3df4 AO |
1058 | bne reg1, reg2, 0f |
1059 | nop | |
1060 | j[al] label | |
1061 | delay slot (executed only if branch taken) | |
1062 | 0: | |
1063 | ||
1064 | beql -> bne | |
1065 | bnel -> beq | |
1066 | blezl -> bgtz | |
1067 | bgtzl -> blez | |
1068 | bltzl -> bgez | |
1069 | bgezl -> bltz | |
1070 | bc1fl -> bc1t | |
1071 | bc1tl -> bc1f | |
1072 | ||
1073 | bltzall -> bgezal (with jal label instead of j label) | |
1074 | bgezall -> bltzal (ditto) | |
1075 | ||
1076 | ||
1077 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1078 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1079 | ((relax_substateT) \ | |
1080 | (0xc0000000 \ | |
1081 | | ((at) & 0x1f) \ | |
1082 | | ((toofar) ? 0x20 : 0) \ | |
1083 | | ((link) ? 0x40 : 0) \ | |
1084 | | ((likely) ? 0x80 : 0) \ | |
1085 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1086 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1087 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1088 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1089 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1090 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1091 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1092 | |
252b5132 RH |
1093 | /* For mips16 code, we use an entirely different form of relaxation. |
1094 | mips16 supports two versions of most instructions which take | |
1095 | immediate values: a small one which takes some small value, and a | |
1096 | larger one which takes a 16 bit value. Since branches also follow | |
1097 | this pattern, relaxing these values is required. | |
1098 | ||
1099 | We can assemble both mips16 and normal MIPS code in a single | |
1100 | object. Therefore, we need to support this type of relaxation at | |
1101 | the same time that we support the relaxation described above. We | |
1102 | use the high bit of the subtype field to distinguish these cases. | |
1103 | ||
1104 | The information we store for this type of relaxation is the | |
1105 | argument code found in the opcode file for this relocation, whether | |
1106 | the user explicitly requested a small or extended form, and whether | |
1107 | the relocation is in a jump or jal delay slot. That tells us the | |
1108 | size of the value, and how it should be stored. We also store | |
1109 | whether the fragment is considered to be extended or not. We also | |
1110 | store whether this is known to be a branch to a different section, | |
1111 | whether we have tried to relax this frag yet, and whether we have | |
1112 | ever extended a PC relative fragment because of a shift count. */ | |
1113 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1114 | (0x80000000 \ | |
1115 | | ((type) & 0xff) \ | |
1116 | | ((small) ? 0x100 : 0) \ | |
1117 | | ((ext) ? 0x200 : 0) \ | |
1118 | | ((dslot) ? 0x400 : 0) \ | |
1119 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1120 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1121 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1122 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1123 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1124 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1125 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1126 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1127 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1128 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1129 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1130 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1131 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1132 | |
df58fc94 RS |
1133 | /* For microMIPS code, we use relaxation similar to one we use for |
1134 | MIPS16 code. Some instructions that take immediate values support | |
1135 | two encodings: a small one which takes some small value, and a | |
1136 | larger one which takes a 16 bit value. As some branches also follow | |
1137 | this pattern, relaxing these values is required. | |
1138 | ||
1139 | We can assemble both microMIPS and normal MIPS code in a single | |
1140 | object. Therefore, we need to support this type of relaxation at | |
1141 | the same time that we support the relaxation described above. We | |
1142 | use one of the high bits of the subtype field to distinguish these | |
1143 | cases. | |
1144 | ||
1145 | The information we store for this type of relaxation is the argument | |
1146 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1147 | selected as the assembler temporary, whether the branch is |
1148 | unconditional, whether it is compact, whether it stores the link | |
1149 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1150 | branches to a sequence of instructions is enabled, and whether the | |
1151 | displacement of a branch is too large to fit as an immediate argument | |
1152 | of a 16-bit and a 32-bit branch, respectively. */ | |
1153 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1154 | relax32, toofar16, toofar32) \ | |
1155 | (0x40000000 \ | |
1156 | | ((type) & 0xff) \ | |
1157 | | (((at) & 0x1f) << 8) \ | |
1158 | | ((uncond) ? 0x2000 : 0) \ | |
1159 | | ((compact) ? 0x4000 : 0) \ | |
1160 | | ((link) ? 0x8000 : 0) \ | |
1161 | | ((relax32) ? 0x10000 : 0) \ | |
1162 | | ((toofar16) ? 0x20000 : 0) \ | |
1163 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1164 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1165 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1166 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1167 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1168 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1169 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1170 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1171 | ||
1172 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1173 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1174 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1175 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1176 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1177 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1178 | |
43c0598f RS |
1179 | /* Sign-extend 16-bit value X. */ |
1180 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1181 | ||
885add95 CD |
1182 | /* Is the given value a sign-extended 32-bit value? */ |
1183 | #define IS_SEXT_32BIT_NUM(x) \ | |
1184 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1185 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1186 | ||
1187 | /* Is the given value a sign-extended 16-bit value? */ | |
1188 | #define IS_SEXT_16BIT_NUM(x) \ | |
1189 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1190 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1191 | ||
df58fc94 RS |
1192 | /* Is the given value a sign-extended 12-bit value? */ |
1193 | #define IS_SEXT_12BIT_NUM(x) \ | |
1194 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1195 | ||
2051e8c4 MR |
1196 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1197 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1198 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1199 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1200 | ||
bf12938e RS |
1201 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1202 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1203 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1204 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1205 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1206 | ||
1207 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1208 | SHIFT places. */ | |
1209 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1210 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1211 | ||
1212 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1213 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1214 | ||
1215 | include/opcode/mips.h specifies operand fields using the macros | |
1216 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1217 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1218 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1219 | do \ | |
1220 | if (!(MICROMIPS)) \ | |
1221 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1222 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1223 | else \ | |
1224 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1225 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1226 | while (0) | |
bf12938e RS |
1227 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1228 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1229 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1230 | ||
1231 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1232 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1233 | (!(MICROMIPS) \ | |
1234 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1235 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1236 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1237 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1238 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1239 | MIPS16OP_MASK_##FIELD, \ | |
1240 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1241 | |
1242 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1243 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1244 | \f |
df58fc94 RS |
1245 | /* Whether or not we are emitting a branch-likely macro. */ |
1246 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1247 | ||
4d7206a2 RS |
1248 | /* Global variables used when generating relaxable macros. See the |
1249 | comment above RELAX_ENCODE for more details about how relaxation | |
1250 | is used. */ | |
1251 | static struct { | |
1252 | /* 0 if we're not emitting a relaxable macro. | |
1253 | 1 if we're emitting the first of the two relaxation alternatives. | |
1254 | 2 if we're emitting the second alternative. */ | |
1255 | int sequence; | |
1256 | ||
1257 | /* The first relaxable fixup in the current frag. (In other words, | |
1258 | the first fixup that refers to relaxable code.) */ | |
1259 | fixS *first_fixup; | |
1260 | ||
1261 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1262 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1263 | unsigned int sizes[2]; | |
1264 | ||
1265 | /* The symbol on which the choice of sequence depends. */ | |
1266 | symbolS *symbol; | |
1267 | } mips_relax; | |
252b5132 | 1268 | \f |
584892a6 RS |
1269 | /* Global variables used to decide whether a macro needs a warning. */ |
1270 | static struct { | |
1271 | /* True if the macro is in a branch delay slot. */ | |
1272 | bfd_boolean delay_slot_p; | |
1273 | ||
df58fc94 RS |
1274 | /* Set to the length in bytes required if the macro is in a delay slot |
1275 | that requires a specific length of instruction, otherwise zero. */ | |
1276 | unsigned int delay_slot_length; | |
1277 | ||
584892a6 RS |
1278 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1279 | in bytes and sizes[1] is the length of the second alternative. | |
1280 | For non-relaxable macros, both elements give the length of the | |
1281 | macro in bytes. */ | |
1282 | unsigned int sizes[2]; | |
1283 | ||
df58fc94 RS |
1284 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1285 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1286 | is the length of the first instruction of the second alternative. | |
1287 | For non-relaxable macros, both elements give the length of the first | |
1288 | instruction in bytes. | |
1289 | ||
1290 | Set to zero if we haven't yet seen the first instruction. */ | |
1291 | unsigned int first_insn_sizes[2]; | |
1292 | ||
1293 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1294 | first alternative and insns[1] is the number of instructions for the | |
1295 | second alternative. | |
1296 | ||
1297 | For non-relaxable macros, both elements give the number of | |
1298 | instructions for the macro. */ | |
1299 | unsigned int insns[2]; | |
1300 | ||
584892a6 RS |
1301 | /* The first variant frag for this macro. */ |
1302 | fragS *first_frag; | |
1303 | } mips_macro_warning; | |
1304 | \f | |
252b5132 RH |
1305 | /* Prototypes for static functions. */ |
1306 | ||
17a2f251 | 1307 | #define internalError() \ |
252b5132 | 1308 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1309 | |
1310 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1311 | ||
b34976b6 | 1312 | static void append_insn |
df58fc94 RS |
1313 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1314 | bfd_boolean expansionp); | |
7d10b47d | 1315 | static void mips_no_prev_insn (void); |
c67a084a | 1316 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1317 | static void mips16_macro_build |
03ea81db | 1318 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1319 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1320 | static void macro_start (void); |
1321 | static void macro_end (void); | |
17a2f251 TS |
1322 | static void macro (struct mips_cl_insn * ip); |
1323 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1324 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1325 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1326 | static void mips16_immed |
43c0598f RS |
1327 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1328 | unsigned int, unsigned long *); | |
5e0116d5 | 1329 | static size_t my_getSmallExpression |
17a2f251 TS |
1330 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1331 | static void my_getExpression (expressionS *, char *); | |
1332 | static void s_align (int); | |
1333 | static void s_change_sec (int); | |
1334 | static void s_change_section (int); | |
1335 | static void s_cons (int); | |
1336 | static void s_float_cons (int); | |
1337 | static void s_mips_globl (int); | |
1338 | static void s_option (int); | |
1339 | static void s_mipsset (int); | |
1340 | static void s_abicalls (int); | |
1341 | static void s_cpload (int); | |
1342 | static void s_cpsetup (int); | |
1343 | static void s_cplocal (int); | |
1344 | static void s_cprestore (int); | |
1345 | static void s_cpreturn (int); | |
741d6ea8 JM |
1346 | static void s_dtprelword (int); |
1347 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1348 | static void s_tprelword (int); |
1349 | static void s_tpreldword (int); | |
17a2f251 TS |
1350 | static void s_gpvalue (int); |
1351 | static void s_gpword (int); | |
1352 | static void s_gpdword (int); | |
1353 | static void s_cpadd (int); | |
1354 | static void s_insn (int); | |
1355 | static void md_obj_begin (void); | |
1356 | static void md_obj_end (void); | |
1357 | static void s_mips_ent (int); | |
1358 | static void s_mips_end (int); | |
1359 | static void s_mips_frame (int); | |
1360 | static void s_mips_mask (int reg_type); | |
1361 | static void s_mips_stab (int); | |
1362 | static void s_mips_weakext (int); | |
1363 | static void s_mips_file (int); | |
1364 | static void s_mips_loc (int); | |
1365 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1366 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1367 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1368 | static int validate_micromips_insn (const struct mips_opcode *); |
1369 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1370 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1371 | |
1372 | /* Table and functions used to map between CPU/ISA names, and | |
1373 | ISA levels, and CPU numbers. */ | |
1374 | ||
e972090a NC |
1375 | struct mips_cpu_info |
1376 | { | |
e7af610e | 1377 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1378 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1379 | int isa; /* ISA level. */ |
1380 | int cpu; /* CPU number (default CPU if ISA). */ | |
1381 | }; | |
1382 | ||
ad3fea08 TS |
1383 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1384 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1385 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1386 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1387 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1388 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1389 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1390 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1391 | |
17a2f251 TS |
1392 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1393 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1394 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1395 | \f |
1396 | /* Pseudo-op table. | |
1397 | ||
1398 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1399 | should be defined here, but are currently unsupported: .alias, | |
1400 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1401 | ||
1402 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1403 | specific to the type of debugging information being generated, and | |
1404 | should be defined by the object format: .aent, .begin, .bend, | |
1405 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1406 | .vreg. | |
1407 | ||
1408 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1409 | not MIPS CPU specific, but are also not specific to the object file | |
1410 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1411 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1412 | |
e972090a NC |
1413 | static const pseudo_typeS mips_pseudo_table[] = |
1414 | { | |
beae10d5 | 1415 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1416 | {"option", s_option, 0}, |
1417 | {"set", s_mipsset, 0}, | |
1418 | {"rdata", s_change_sec, 'r'}, | |
1419 | {"sdata", s_change_sec, 's'}, | |
1420 | {"livereg", s_ignore, 0}, | |
1421 | {"abicalls", s_abicalls, 0}, | |
1422 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1423 | {"cpsetup", s_cpsetup, 0}, |
1424 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1425 | {"cprestore", s_cprestore, 0}, |
6478892d | 1426 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1427 | {"dtprelword", s_dtprelword, 0}, |
1428 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1429 | {"tprelword", s_tprelword, 0}, |
1430 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1431 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1432 | {"gpword", s_gpword, 0}, |
10181a0d | 1433 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1434 | {"cpadd", s_cpadd, 0}, |
1435 | {"insn", s_insn, 0}, | |
1436 | ||
beae10d5 | 1437 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1438 | chips. */ |
38a57ae7 | 1439 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1440 | {"bss", s_change_sec, 'b'}, |
1441 | {"err", s_err, 0}, | |
1442 | {"half", s_cons, 1}, | |
1443 | {"dword", s_cons, 3}, | |
1444 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1445 | {"origin", s_org, 0}, |
1446 | {"repeat", s_rept, 0}, | |
252b5132 | 1447 | |
998b3c36 MR |
1448 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1449 | {"sbss", s_change_sec, 'B'}, | |
1450 | ||
beae10d5 | 1451 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1452 | here for one reason or another. */ |
1453 | {"align", s_align, 0}, | |
1454 | {"byte", s_cons, 0}, | |
1455 | {"data", s_change_sec, 'd'}, | |
1456 | {"double", s_float_cons, 'd'}, | |
1457 | {"float", s_float_cons, 'f'}, | |
1458 | {"globl", s_mips_globl, 0}, | |
1459 | {"global", s_mips_globl, 0}, | |
1460 | {"hword", s_cons, 1}, | |
1461 | {"int", s_cons, 2}, | |
1462 | {"long", s_cons, 2}, | |
1463 | {"octa", s_cons, 4}, | |
1464 | {"quad", s_cons, 3}, | |
cca86cc8 | 1465 | {"section", s_change_section, 0}, |
252b5132 RH |
1466 | {"short", s_cons, 1}, |
1467 | {"single", s_float_cons, 'f'}, | |
1468 | {"stabn", s_mips_stab, 'n'}, | |
1469 | {"text", s_change_sec, 't'}, | |
1470 | {"word", s_cons, 2}, | |
add56521 | 1471 | |
add56521 | 1472 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1473 | |
43841e91 | 1474 | { NULL, NULL, 0 }, |
252b5132 RH |
1475 | }; |
1476 | ||
e972090a NC |
1477 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1478 | { | |
beae10d5 KH |
1479 | /* These pseudo-ops should be defined by the object file format. |
1480 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1481 | {"aent", s_mips_ent, 1}, |
1482 | {"bgnb", s_ignore, 0}, | |
1483 | {"end", s_mips_end, 0}, | |
1484 | {"endb", s_ignore, 0}, | |
1485 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1486 | {"file", s_mips_file, 0}, |
252b5132 RH |
1487 | {"fmask", s_mips_mask, 'F'}, |
1488 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1489 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1490 | {"mask", s_mips_mask, 'R'}, |
1491 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1492 | { NULL, NULL, 0 }, |
252b5132 RH |
1493 | }; |
1494 | ||
3ae8dd8d MR |
1495 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1496 | purpose of the `.dc.a' internal pseudo-op. */ | |
1497 | ||
1498 | int | |
1499 | mips_address_bytes (void) | |
1500 | { | |
1501 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1502 | } | |
1503 | ||
17a2f251 | 1504 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1505 | |
1506 | void | |
17a2f251 | 1507 | mips_pop_insert (void) |
252b5132 RH |
1508 | { |
1509 | pop_insert (mips_pseudo_table); | |
1510 | if (! ECOFF_DEBUGGING) | |
1511 | pop_insert (mips_nonecoff_pseudo_table); | |
1512 | } | |
1513 | \f | |
1514 | /* Symbols labelling the current insn. */ | |
1515 | ||
e972090a NC |
1516 | struct insn_label_list |
1517 | { | |
252b5132 RH |
1518 | struct insn_label_list *next; |
1519 | symbolS *label; | |
1520 | }; | |
1521 | ||
252b5132 | 1522 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1523 | #define label_list tc_segment_info_data.labels |
252b5132 | 1524 | |
17a2f251 | 1525 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1526 | static void mips_mark_labels (void); |
1527 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1528 | |
1529 | static inline void | |
17a2f251 | 1530 | mips_clear_insn_labels (void) |
252b5132 RH |
1531 | { |
1532 | register struct insn_label_list **pl; | |
a8dbcb85 | 1533 | segment_info_type *si; |
252b5132 | 1534 | |
a8dbcb85 TS |
1535 | if (now_seg) |
1536 | { | |
1537 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1538 | ; | |
1539 | ||
1540 | si = seg_info (now_seg); | |
1541 | *pl = si->label_list; | |
1542 | si->label_list = NULL; | |
1543 | } | |
252b5132 | 1544 | } |
a8dbcb85 | 1545 | |
df58fc94 RS |
1546 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1547 | ||
1548 | static inline void | |
1549 | mips_mark_labels (void) | |
1550 | { | |
1551 | if (HAVE_CODE_COMPRESSION) | |
1552 | mips_compressed_mark_labels (); | |
1553 | } | |
252b5132 RH |
1554 | \f |
1555 | static char *expr_end; | |
1556 | ||
1557 | /* Expressions which appear in instructions. These are set by | |
1558 | mips_ip. */ | |
1559 | ||
1560 | static expressionS imm_expr; | |
5f74bc13 | 1561 | static expressionS imm2_expr; |
252b5132 RH |
1562 | static expressionS offset_expr; |
1563 | ||
1564 | /* Relocs associated with imm_expr and offset_expr. */ | |
1565 | ||
f6688943 TS |
1566 | static bfd_reloc_code_real_type imm_reloc[3] |
1567 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1568 | static bfd_reloc_code_real_type offset_reloc[3] | |
1569 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1570 | |
df58fc94 RS |
1571 | /* This is set to the resulting size of the instruction to be produced |
1572 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1573 | explicit size is supplied. */ | |
252b5132 | 1574 | |
df58fc94 | 1575 | static unsigned int forced_insn_length; |
252b5132 | 1576 | |
7ed4a06a | 1577 | #ifdef OBJ_ELF |
ecb4347a DJ |
1578 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1579 | ECOFF debugging. */ | |
252b5132 RH |
1580 | |
1581 | static segT pdr_seg; | |
7ed4a06a | 1582 | #endif |
252b5132 | 1583 | |
e013f690 TS |
1584 | /* The default target format to use. */ |
1585 | ||
aeffff67 RS |
1586 | #if defined (TE_FreeBSD) |
1587 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1588 | #elif defined (TE_TMIPS) | |
1589 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1590 | #else | |
1591 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1592 | #endif | |
1593 | ||
e013f690 | 1594 | const char * |
17a2f251 | 1595 | mips_target_format (void) |
e013f690 TS |
1596 | { |
1597 | switch (OUTPUT_FLAVOR) | |
1598 | { | |
e013f690 TS |
1599 | case bfd_target_ecoff_flavour: |
1600 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1601 | case bfd_target_coff_flavour: | |
1602 | return "pe-mips"; | |
1603 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1604 | #ifdef TE_VXWORKS |
1605 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1606 | return (target_big_endian | |
1607 | ? "elf32-bigmips-vxworks" | |
1608 | : "elf32-littlemips-vxworks"); | |
1609 | #endif | |
e013f690 | 1610 | return (target_big_endian |
cfe86eaa | 1611 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1612 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1613 | : (HAVE_NEWABI |
aeffff67 RS |
1614 | ? ELF_TARGET ("elf32-n", "big") |
1615 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1616 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1617 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1618 | : (HAVE_NEWABI |
aeffff67 RS |
1619 | ? ELF_TARGET ("elf32-n", "little") |
1620 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1621 | default: |
1622 | abort (); | |
1623 | return NULL; | |
1624 | } | |
1625 | } | |
1626 | ||
df58fc94 RS |
1627 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1628 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1629 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1630 | major opcode) will require further modifications to the opcode | |
1631 | table. */ | |
1632 | ||
1633 | static inline unsigned int | |
1634 | micromips_insn_length (const struct mips_opcode *mo) | |
1635 | { | |
1636 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1637 | } | |
1638 | ||
5c04167a RS |
1639 | /* Return the length of MIPS16 instruction OPCODE. */ |
1640 | ||
1641 | static inline unsigned int | |
1642 | mips16_opcode_length (unsigned long opcode) | |
1643 | { | |
1644 | return (opcode >> 16) == 0 ? 2 : 4; | |
1645 | } | |
1646 | ||
1e915849 RS |
1647 | /* Return the length of instruction INSN. */ |
1648 | ||
1649 | static inline unsigned int | |
1650 | insn_length (const struct mips_cl_insn *insn) | |
1651 | { | |
df58fc94 RS |
1652 | if (mips_opts.micromips) |
1653 | return micromips_insn_length (insn->insn_mo); | |
1654 | else if (mips_opts.mips16) | |
5c04167a | 1655 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 1656 | else |
1e915849 | 1657 | return 4; |
1e915849 RS |
1658 | } |
1659 | ||
1660 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1661 | ||
1662 | static void | |
1663 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1664 | { | |
1665 | size_t i; | |
1666 | ||
1667 | insn->insn_mo = mo; | |
1e915849 RS |
1668 | insn->insn_opcode = mo->match; |
1669 | insn->frag = NULL; | |
1670 | insn->where = 0; | |
1671 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1672 | insn->fixp[i] = NULL; | |
1673 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1674 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1675 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1676 | insn->complete_p = 0; |
1e915849 RS |
1677 | } |
1678 | ||
df58fc94 | 1679 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1680 | |
1681 | static void | |
df58fc94 | 1682 | mips_record_compressed_mode (void) |
742a56fe RS |
1683 | { |
1684 | segment_info_type *si; | |
1685 | ||
1686 | si = seg_info (now_seg); | |
1687 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1688 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1689 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1690 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1691 | } |
1692 | ||
4d68580a RS |
1693 | /* Read a standard MIPS instruction from BUF. */ |
1694 | ||
1695 | static unsigned long | |
1696 | read_insn (char *buf) | |
1697 | { | |
1698 | if (target_big_endian) | |
1699 | return bfd_getb32 ((bfd_byte *) buf); | |
1700 | else | |
1701 | return bfd_getl32 ((bfd_byte *) buf); | |
1702 | } | |
1703 | ||
1704 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
1705 | the next byte. */ | |
1706 | ||
1707 | static char * | |
1708 | write_insn (char *buf, unsigned int insn) | |
1709 | { | |
1710 | md_number_to_chars (buf, insn, 4); | |
1711 | return buf + 4; | |
1712 | } | |
1713 | ||
1714 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
1715 | has length LENGTH. */ | |
1716 | ||
1717 | static unsigned long | |
1718 | read_compressed_insn (char *buf, unsigned int length) | |
1719 | { | |
1720 | unsigned long insn; | |
1721 | unsigned int i; | |
1722 | ||
1723 | insn = 0; | |
1724 | for (i = 0; i < length; i += 2) | |
1725 | { | |
1726 | insn <<= 16; | |
1727 | if (target_big_endian) | |
1728 | insn |= bfd_getb16 ((char *) buf); | |
1729 | else | |
1730 | insn |= bfd_getl16 ((char *) buf); | |
1731 | buf += 2; | |
1732 | } | |
1733 | return insn; | |
1734 | } | |
1735 | ||
5c04167a RS |
1736 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
1737 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
1738 | ||
1739 | static char * | |
1740 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
1741 | { | |
1742 | unsigned int i; | |
1743 | ||
1744 | for (i = 0; i < length; i += 2) | |
1745 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
1746 | return buf + length; | |
1747 | } | |
1748 | ||
1e915849 RS |
1749 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1750 | ||
1751 | static void | |
1752 | install_insn (const struct mips_cl_insn *insn) | |
1753 | { | |
1754 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
1755 | if (HAVE_CODE_COMPRESSION) |
1756 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 1757 | else |
4d68580a | 1758 | write_insn (f, insn->insn_opcode); |
df58fc94 | 1759 | mips_record_compressed_mode (); |
1e915849 RS |
1760 | } |
1761 | ||
1762 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1763 | and install the opcode in the new location. */ | |
1764 | ||
1765 | static void | |
1766 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1767 | { | |
1768 | size_t i; | |
1769 | ||
1770 | insn->frag = frag; | |
1771 | insn->where = where; | |
1772 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1773 | if (insn->fixp[i] != NULL) | |
1774 | { | |
1775 | insn->fixp[i]->fx_frag = frag; | |
1776 | insn->fixp[i]->fx_where = where; | |
1777 | } | |
1778 | install_insn (insn); | |
1779 | } | |
1780 | ||
1781 | /* Add INSN to the end of the output. */ | |
1782 | ||
1783 | static void | |
1784 | add_fixed_insn (struct mips_cl_insn *insn) | |
1785 | { | |
1786 | char *f = frag_more (insn_length (insn)); | |
1787 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1788 | } | |
1789 | ||
1790 | /* Start a variant frag and move INSN to the start of the variant part, | |
1791 | marking it as fixed. The other arguments are as for frag_var. */ | |
1792 | ||
1793 | static void | |
1794 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1795 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1796 | { | |
1797 | frag_grow (max_chars); | |
1798 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1799 | insn->fixed_p = 1; | |
1800 | frag_var (rs_machine_dependent, max_chars, var, | |
1801 | subtype, symbol, offset, NULL); | |
1802 | } | |
1803 | ||
1804 | /* Insert N copies of INSN into the history buffer, starting at | |
1805 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1806 | ||
1807 | static void | |
1808 | insert_into_history (unsigned int first, unsigned int n, | |
1809 | const struct mips_cl_insn *insn) | |
1810 | { | |
1811 | if (mips_relax.sequence != 2) | |
1812 | { | |
1813 | unsigned int i; | |
1814 | ||
1815 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1816 | if (i >= first + n) | |
1817 | history[i] = history[i - n]; | |
1818 | else | |
1819 | history[i] = *insn; | |
1820 | } | |
1821 | } | |
1822 | ||
71400594 RS |
1823 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1824 | the idea is to make it obvious at a glance that each errata is | |
1825 | included. */ | |
1826 | ||
1827 | static void | |
1828 | init_vr4120_conflicts (void) | |
1829 | { | |
1830 | #define CONFLICT(FIRST, SECOND) \ | |
1831 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1832 | ||
1833 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1834 | CONFLICT (MACC, DIV); | |
1835 | CONFLICT (DMACC, DIV); | |
1836 | ||
1837 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1838 | CONFLICT (DMULT, DMULT); | |
1839 | CONFLICT (DMULT, DMACC); | |
1840 | CONFLICT (DMACC, DMULT); | |
1841 | CONFLICT (DMACC, DMACC); | |
1842 | ||
1843 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1844 | CONFLICT (MACC, MTHILO); | |
1845 | CONFLICT (DMACC, MTHILO); | |
1846 | ||
1847 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1848 | instruction is executed immediately after a MACC or DMACC | |
1849 | instruction, the result of [either instruction] is incorrect." */ | |
1850 | CONFLICT (MACC, MULT); | |
1851 | CONFLICT (MACC, DMULT); | |
1852 | CONFLICT (DMACC, MULT); | |
1853 | CONFLICT (DMACC, DMULT); | |
1854 | ||
1855 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1856 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1857 | DDIV or DDIVU instruction, the result of the MACC or | |
1858 | DMACC instruction is incorrect.". */ | |
1859 | CONFLICT (DMULT, MACC); | |
1860 | CONFLICT (DMULT, DMACC); | |
1861 | CONFLICT (DIV, MACC); | |
1862 | CONFLICT (DIV, DMACC); | |
1863 | ||
1864 | #undef CONFLICT | |
1865 | } | |
1866 | ||
707bfff6 TS |
1867 | struct regname { |
1868 | const char *name; | |
1869 | unsigned int num; | |
1870 | }; | |
1871 | ||
1872 | #define RTYPE_MASK 0x1ff00 | |
1873 | #define RTYPE_NUM 0x00100 | |
1874 | #define RTYPE_FPU 0x00200 | |
1875 | #define RTYPE_FCC 0x00400 | |
1876 | #define RTYPE_VEC 0x00800 | |
1877 | #define RTYPE_GP 0x01000 | |
1878 | #define RTYPE_CP0 0x02000 | |
1879 | #define RTYPE_PC 0x04000 | |
1880 | #define RTYPE_ACC 0x08000 | |
1881 | #define RTYPE_CCC 0x10000 | |
1882 | #define RNUM_MASK 0x000ff | |
1883 | #define RWARN 0x80000 | |
1884 | ||
1885 | #define GENERIC_REGISTER_NUMBERS \ | |
1886 | {"$0", RTYPE_NUM | 0}, \ | |
1887 | {"$1", RTYPE_NUM | 1}, \ | |
1888 | {"$2", RTYPE_NUM | 2}, \ | |
1889 | {"$3", RTYPE_NUM | 3}, \ | |
1890 | {"$4", RTYPE_NUM | 4}, \ | |
1891 | {"$5", RTYPE_NUM | 5}, \ | |
1892 | {"$6", RTYPE_NUM | 6}, \ | |
1893 | {"$7", RTYPE_NUM | 7}, \ | |
1894 | {"$8", RTYPE_NUM | 8}, \ | |
1895 | {"$9", RTYPE_NUM | 9}, \ | |
1896 | {"$10", RTYPE_NUM | 10}, \ | |
1897 | {"$11", RTYPE_NUM | 11}, \ | |
1898 | {"$12", RTYPE_NUM | 12}, \ | |
1899 | {"$13", RTYPE_NUM | 13}, \ | |
1900 | {"$14", RTYPE_NUM | 14}, \ | |
1901 | {"$15", RTYPE_NUM | 15}, \ | |
1902 | {"$16", RTYPE_NUM | 16}, \ | |
1903 | {"$17", RTYPE_NUM | 17}, \ | |
1904 | {"$18", RTYPE_NUM | 18}, \ | |
1905 | {"$19", RTYPE_NUM | 19}, \ | |
1906 | {"$20", RTYPE_NUM | 20}, \ | |
1907 | {"$21", RTYPE_NUM | 21}, \ | |
1908 | {"$22", RTYPE_NUM | 22}, \ | |
1909 | {"$23", RTYPE_NUM | 23}, \ | |
1910 | {"$24", RTYPE_NUM | 24}, \ | |
1911 | {"$25", RTYPE_NUM | 25}, \ | |
1912 | {"$26", RTYPE_NUM | 26}, \ | |
1913 | {"$27", RTYPE_NUM | 27}, \ | |
1914 | {"$28", RTYPE_NUM | 28}, \ | |
1915 | {"$29", RTYPE_NUM | 29}, \ | |
1916 | {"$30", RTYPE_NUM | 30}, \ | |
1917 | {"$31", RTYPE_NUM | 31} | |
1918 | ||
1919 | #define FPU_REGISTER_NAMES \ | |
1920 | {"$f0", RTYPE_FPU | 0}, \ | |
1921 | {"$f1", RTYPE_FPU | 1}, \ | |
1922 | {"$f2", RTYPE_FPU | 2}, \ | |
1923 | {"$f3", RTYPE_FPU | 3}, \ | |
1924 | {"$f4", RTYPE_FPU | 4}, \ | |
1925 | {"$f5", RTYPE_FPU | 5}, \ | |
1926 | {"$f6", RTYPE_FPU | 6}, \ | |
1927 | {"$f7", RTYPE_FPU | 7}, \ | |
1928 | {"$f8", RTYPE_FPU | 8}, \ | |
1929 | {"$f9", RTYPE_FPU | 9}, \ | |
1930 | {"$f10", RTYPE_FPU | 10}, \ | |
1931 | {"$f11", RTYPE_FPU | 11}, \ | |
1932 | {"$f12", RTYPE_FPU | 12}, \ | |
1933 | {"$f13", RTYPE_FPU | 13}, \ | |
1934 | {"$f14", RTYPE_FPU | 14}, \ | |
1935 | {"$f15", RTYPE_FPU | 15}, \ | |
1936 | {"$f16", RTYPE_FPU | 16}, \ | |
1937 | {"$f17", RTYPE_FPU | 17}, \ | |
1938 | {"$f18", RTYPE_FPU | 18}, \ | |
1939 | {"$f19", RTYPE_FPU | 19}, \ | |
1940 | {"$f20", RTYPE_FPU | 20}, \ | |
1941 | {"$f21", RTYPE_FPU | 21}, \ | |
1942 | {"$f22", RTYPE_FPU | 22}, \ | |
1943 | {"$f23", RTYPE_FPU | 23}, \ | |
1944 | {"$f24", RTYPE_FPU | 24}, \ | |
1945 | {"$f25", RTYPE_FPU | 25}, \ | |
1946 | {"$f26", RTYPE_FPU | 26}, \ | |
1947 | {"$f27", RTYPE_FPU | 27}, \ | |
1948 | {"$f28", RTYPE_FPU | 28}, \ | |
1949 | {"$f29", RTYPE_FPU | 29}, \ | |
1950 | {"$f30", RTYPE_FPU | 30}, \ | |
1951 | {"$f31", RTYPE_FPU | 31} | |
1952 | ||
1953 | #define FPU_CONDITION_CODE_NAMES \ | |
1954 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1955 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1956 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1957 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1958 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1959 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1960 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1961 | {"$fcc7", RTYPE_FCC | 7} | |
1962 | ||
1963 | #define COPROC_CONDITION_CODE_NAMES \ | |
1964 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1965 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1966 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1967 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1968 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1969 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1970 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1971 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1972 | ||
1973 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1974 | {"$a4", RTYPE_GP | 8}, \ | |
1975 | {"$a5", RTYPE_GP | 9}, \ | |
1976 | {"$a6", RTYPE_GP | 10}, \ | |
1977 | {"$a7", RTYPE_GP | 11}, \ | |
1978 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1979 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1980 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1981 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1982 | {"$t0", RTYPE_GP | 12}, \ | |
1983 | {"$t1", RTYPE_GP | 13}, \ | |
1984 | {"$t2", RTYPE_GP | 14}, \ | |
1985 | {"$t3", RTYPE_GP | 15} | |
1986 | ||
1987 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1988 | {"$t0", RTYPE_GP | 8}, \ | |
1989 | {"$t1", RTYPE_GP | 9}, \ | |
1990 | {"$t2", RTYPE_GP | 10}, \ | |
1991 | {"$t3", RTYPE_GP | 11}, \ | |
1992 | {"$t4", RTYPE_GP | 12}, \ | |
1993 | {"$t5", RTYPE_GP | 13}, \ | |
1994 | {"$t6", RTYPE_GP | 14}, \ | |
1995 | {"$t7", RTYPE_GP | 15}, \ | |
1996 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1997 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1998 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1999 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2000 | ||
2001 | /* Remaining symbolic register names */ | |
2002 | #define SYMBOLIC_REGISTER_NAMES \ | |
2003 | {"$zero", RTYPE_GP | 0}, \ | |
2004 | {"$at", RTYPE_GP | 1}, \ | |
2005 | {"$AT", RTYPE_GP | 1}, \ | |
2006 | {"$v0", RTYPE_GP | 2}, \ | |
2007 | {"$v1", RTYPE_GP | 3}, \ | |
2008 | {"$a0", RTYPE_GP | 4}, \ | |
2009 | {"$a1", RTYPE_GP | 5}, \ | |
2010 | {"$a2", RTYPE_GP | 6}, \ | |
2011 | {"$a3", RTYPE_GP | 7}, \ | |
2012 | {"$s0", RTYPE_GP | 16}, \ | |
2013 | {"$s1", RTYPE_GP | 17}, \ | |
2014 | {"$s2", RTYPE_GP | 18}, \ | |
2015 | {"$s3", RTYPE_GP | 19}, \ | |
2016 | {"$s4", RTYPE_GP | 20}, \ | |
2017 | {"$s5", RTYPE_GP | 21}, \ | |
2018 | {"$s6", RTYPE_GP | 22}, \ | |
2019 | {"$s7", RTYPE_GP | 23}, \ | |
2020 | {"$t8", RTYPE_GP | 24}, \ | |
2021 | {"$t9", RTYPE_GP | 25}, \ | |
2022 | {"$k0", RTYPE_GP | 26}, \ | |
2023 | {"$kt0", RTYPE_GP | 26}, \ | |
2024 | {"$k1", RTYPE_GP | 27}, \ | |
2025 | {"$kt1", RTYPE_GP | 27}, \ | |
2026 | {"$gp", RTYPE_GP | 28}, \ | |
2027 | {"$sp", RTYPE_GP | 29}, \ | |
2028 | {"$s8", RTYPE_GP | 30}, \ | |
2029 | {"$fp", RTYPE_GP | 30}, \ | |
2030 | {"$ra", RTYPE_GP | 31} | |
2031 | ||
2032 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2033 | {"$pc", RTYPE_PC | 0} | |
2034 | ||
2035 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2036 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2037 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2038 | {"$v2", RTYPE_VEC | 2}, \ | |
2039 | {"$v3", RTYPE_VEC | 3}, \ | |
2040 | {"$v4", RTYPE_VEC | 4}, \ | |
2041 | {"$v5", RTYPE_VEC | 5}, \ | |
2042 | {"$v6", RTYPE_VEC | 6}, \ | |
2043 | {"$v7", RTYPE_VEC | 7}, \ | |
2044 | {"$v8", RTYPE_VEC | 8}, \ | |
2045 | {"$v9", RTYPE_VEC | 9}, \ | |
2046 | {"$v10", RTYPE_VEC | 10}, \ | |
2047 | {"$v11", RTYPE_VEC | 11}, \ | |
2048 | {"$v12", RTYPE_VEC | 12}, \ | |
2049 | {"$v13", RTYPE_VEC | 13}, \ | |
2050 | {"$v14", RTYPE_VEC | 14}, \ | |
2051 | {"$v15", RTYPE_VEC | 15}, \ | |
2052 | {"$v16", RTYPE_VEC | 16}, \ | |
2053 | {"$v17", RTYPE_VEC | 17}, \ | |
2054 | {"$v18", RTYPE_VEC | 18}, \ | |
2055 | {"$v19", RTYPE_VEC | 19}, \ | |
2056 | {"$v20", RTYPE_VEC | 20}, \ | |
2057 | {"$v21", RTYPE_VEC | 21}, \ | |
2058 | {"$v22", RTYPE_VEC | 22}, \ | |
2059 | {"$v23", RTYPE_VEC | 23}, \ | |
2060 | {"$v24", RTYPE_VEC | 24}, \ | |
2061 | {"$v25", RTYPE_VEC | 25}, \ | |
2062 | {"$v26", RTYPE_VEC | 26}, \ | |
2063 | {"$v27", RTYPE_VEC | 27}, \ | |
2064 | {"$v28", RTYPE_VEC | 28}, \ | |
2065 | {"$v29", RTYPE_VEC | 29}, \ | |
2066 | {"$v30", RTYPE_VEC | 30}, \ | |
2067 | {"$v31", RTYPE_VEC | 31} | |
2068 | ||
2069 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2070 | {"$ac0", RTYPE_ACC | 0}, \ | |
2071 | {"$ac1", RTYPE_ACC | 1}, \ | |
2072 | {"$ac2", RTYPE_ACC | 2}, \ | |
2073 | {"$ac3", RTYPE_ACC | 3} | |
2074 | ||
2075 | static const struct regname reg_names[] = { | |
2076 | GENERIC_REGISTER_NUMBERS, | |
2077 | FPU_REGISTER_NAMES, | |
2078 | FPU_CONDITION_CODE_NAMES, | |
2079 | COPROC_CONDITION_CODE_NAMES, | |
2080 | ||
2081 | /* The $txx registers depends on the abi, | |
2082 | these will be added later into the symbol table from | |
2083 | one of the tables below once mips_abi is set after | |
2084 | parsing of arguments from the command line. */ | |
2085 | SYMBOLIC_REGISTER_NAMES, | |
2086 | ||
2087 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2088 | MDMX_VECTOR_REGISTER_NAMES, | |
2089 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2090 | {0, 0} | |
2091 | }; | |
2092 | ||
2093 | static const struct regname reg_names_o32[] = { | |
2094 | O32_SYMBOLIC_REGISTER_NAMES, | |
2095 | {0, 0} | |
2096 | }; | |
2097 | ||
2098 | static const struct regname reg_names_n32n64[] = { | |
2099 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2100 | {0, 0} | |
2101 | }; | |
2102 | ||
df58fc94 RS |
2103 | /* Check if S points at a valid register specifier according to TYPES. |
2104 | If so, then return 1, advance S to consume the specifier and store | |
2105 | the register's number in REGNOP, otherwise return 0. */ | |
2106 | ||
707bfff6 TS |
2107 | static int |
2108 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2109 | { | |
2110 | symbolS *symbolP; | |
2111 | char *e; | |
2112 | char save_c; | |
2113 | int reg = -1; | |
2114 | ||
2115 | /* Find end of name. */ | |
2116 | e = *s; | |
2117 | if (is_name_beginner (*e)) | |
2118 | ++e; | |
2119 | while (is_part_of_name (*e)) | |
2120 | ++e; | |
2121 | ||
2122 | /* Terminate name. */ | |
2123 | save_c = *e; | |
2124 | *e = '\0'; | |
2125 | ||
2126 | /* Look for a register symbol. */ | |
2127 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2128 | { | |
2129 | int r = S_GET_VALUE (symbolP); | |
2130 | if (r & types) | |
2131 | reg = r & RNUM_MASK; | |
2132 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2133 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2134 | reg = (r & RNUM_MASK) - 2; | |
2135 | } | |
2136 | /* Else see if this is a register defined in an itbl entry. */ | |
2137 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2138 | { | |
2139 | char *n = *s; | |
2140 | unsigned long r; | |
2141 | ||
2142 | if (*n == '$') | |
2143 | ++n; | |
2144 | if (itbl_get_reg_val (n, &r)) | |
2145 | reg = r & RNUM_MASK; | |
2146 | } | |
2147 | ||
2148 | /* Advance to next token if a register was recognised. */ | |
2149 | if (reg >= 0) | |
2150 | *s = e; | |
2151 | else if (types & RWARN) | |
20203fb9 | 2152 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2153 | |
2154 | *e = save_c; | |
2155 | if (regnop) | |
2156 | *regnop = reg; | |
2157 | return reg >= 0; | |
2158 | } | |
2159 | ||
df58fc94 RS |
2160 | /* Check if S points at a valid register list according to TYPES. |
2161 | If so, then return 1, advance S to consume the list and store | |
2162 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2163 | otherwise return 0. A valid list comprises a comma-separated | |
2164 | enumeration of valid single registers and/or dash-separated | |
2165 | contiguous register ranges as determined by their numbers. | |
2166 | ||
2167 | As a special exception if one of s0-s7 registers is specified as | |
2168 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2169 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2170 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2171 | |
2172 | static int | |
2173 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2174 | { | |
2175 | unsigned int reglist = 0; | |
2176 | unsigned int lastregno; | |
2177 | bfd_boolean ok = TRUE; | |
2178 | unsigned int regmask; | |
2309ddf2 | 2179 | char *s_endlist = *s; |
df58fc94 | 2180 | char *s_reset = *s; |
2309ddf2 | 2181 | unsigned int regno; |
df58fc94 RS |
2182 | |
2183 | while (reg_lookup (s, types, ®no)) | |
2184 | { | |
2185 | lastregno = regno; | |
2186 | if (**s == '-') | |
2187 | { | |
2188 | (*s)++; | |
2189 | ok = reg_lookup (s, types, &lastregno); | |
2190 | if (ok && lastregno < regno) | |
2191 | ok = FALSE; | |
2192 | if (!ok) | |
2193 | break; | |
2194 | } | |
2195 | ||
2196 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2197 | { | |
2198 | lastregno = S7; | |
2199 | reglist |= 1 << FP; | |
2200 | } | |
2201 | regmask = 1 << lastregno; | |
2202 | regmask = (regmask << 1) - 1; | |
2203 | regmask ^= (1 << regno) - 1; | |
2204 | reglist |= regmask; | |
2205 | ||
2309ddf2 | 2206 | s_endlist = *s; |
df58fc94 RS |
2207 | if (**s != ',') |
2208 | break; | |
2209 | (*s)++; | |
2210 | } | |
2211 | ||
2212 | if (ok) | |
2309ddf2 | 2213 | *s = s_endlist; |
df58fc94 RS |
2214 | else |
2215 | *s = s_reset; | |
2216 | if (reglistp) | |
2217 | *reglistp = reglist; | |
2218 | return ok && reglist != 0; | |
2219 | } | |
2220 | ||
037b32b9 | 2221 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2222 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2223 | |
2224 | static bfd_boolean | |
f79e2745 | 2225 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2226 | { |
2227 | int isa = mips_opts.isa; | |
2228 | int fp_s, fp_d; | |
2229 | ||
2230 | if (mips_opts.ase_mdmx) | |
2231 | isa |= INSN_MDMX; | |
2232 | if (mips_opts.ase_dsp) | |
2233 | isa |= INSN_DSP; | |
2234 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2235 | isa |= INSN_DSP64; | |
2236 | if (mips_opts.ase_dspr2) | |
2237 | isa |= INSN_DSPR2; | |
2238 | if (mips_opts.ase_mt) | |
2239 | isa |= INSN_MT; | |
2240 | if (mips_opts.ase_mips3d) | |
2241 | isa |= INSN_MIPS3D; | |
2242 | if (mips_opts.ase_smartmips) | |
2243 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2244 | if (mips_opts.ase_mcu) |
2245 | isa |= INSN_MCU; | |
037b32b9 | 2246 | |
35d0a169 | 2247 | if (!opcode_is_member (mo, isa, mips_opts.arch)) |
037b32b9 AN |
2248 | return FALSE; |
2249 | ||
2250 | /* Check whether the instruction or macro requires single-precision or | |
2251 | double-precision floating-point support. Note that this information is | |
2252 | stored differently in the opcode table for insns and macros. */ | |
2253 | if (mo->pinfo == INSN_MACRO) | |
2254 | { | |
2255 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2256 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2257 | } | |
2258 | else | |
2259 | { | |
2260 | fp_s = mo->pinfo & FP_S; | |
2261 | fp_d = mo->pinfo & FP_D; | |
2262 | } | |
2263 | ||
2264 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2265 | return FALSE; | |
2266 | ||
2267 | if (fp_s && mips_opts.soft_float) | |
2268 | return FALSE; | |
2269 | ||
2270 | return TRUE; | |
2271 | } | |
2272 | ||
2273 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2274 | selected ISA and architecture. */ | |
2275 | ||
2276 | static bfd_boolean | |
2277 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2278 | { | |
35d0a169 | 2279 | return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); |
037b32b9 AN |
2280 | } |
2281 | ||
df58fc94 RS |
2282 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2283 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2284 | ||
2285 | static bfd_boolean | |
2286 | is_size_valid (const struct mips_opcode *mo) | |
2287 | { | |
2288 | if (!mips_opts.micromips) | |
2289 | return TRUE; | |
2290 | ||
2291 | if (!forced_insn_length) | |
2292 | return TRUE; | |
2293 | if (mo->pinfo == INSN_MACRO) | |
2294 | return FALSE; | |
2295 | return forced_insn_length == micromips_insn_length (mo); | |
2296 | } | |
2297 | ||
2298 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2299 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2300 | ||
2301 | static bfd_boolean | |
2302 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2303 | { | |
2304 | if (!mips_opts.micromips) | |
2305 | return TRUE; | |
2306 | ||
2307 | if (mo->pinfo == INSN_MACRO) | |
2308 | return TRUE; | |
2309 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2310 | && micromips_insn_length (mo) != 4) | |
2311 | return FALSE; | |
2312 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2313 | && micromips_insn_length (mo) != 2) | |
2314 | return FALSE; | |
2315 | ||
2316 | return TRUE; | |
2317 | } | |
2318 | ||
707bfff6 TS |
2319 | /* This function is called once, at assembler startup time. It should set up |
2320 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2321 | |
252b5132 | 2322 | void |
17a2f251 | 2323 | md_begin (void) |
252b5132 | 2324 | { |
3994f87e | 2325 | const char *retval = NULL; |
156c2f8b | 2326 | int i = 0; |
252b5132 | 2327 | int broken = 0; |
1f25f5d3 | 2328 | |
0a44bf69 RS |
2329 | if (mips_pic != NO_PIC) |
2330 | { | |
2331 | if (g_switch_seen && g_switch_value != 0) | |
2332 | as_bad (_("-G may not be used in position-independent code")); | |
2333 | g_switch_value = 0; | |
2334 | } | |
2335 | ||
fef14a42 | 2336 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2337 | as_warn (_("Could not set architecture and machine")); |
2338 | ||
252b5132 RH |
2339 | op_hash = hash_new (); |
2340 | ||
2341 | for (i = 0; i < NUMOPCODES;) | |
2342 | { | |
2343 | const char *name = mips_opcodes[i].name; | |
2344 | ||
17a2f251 | 2345 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2346 | if (retval != NULL) |
2347 | { | |
2348 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2349 | mips_opcodes[i].name, retval); | |
2350 | /* Probably a memory allocation problem? Give up now. */ | |
2351 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2352 | } | |
2353 | do | |
2354 | { | |
2355 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2356 | { | |
2357 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2358 | broken = 1; | |
1e915849 RS |
2359 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2360 | { | |
2361 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2362 | if (mips_fix_loongson2f_nop) |
2363 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2364 | nop_insn.fixed_p = 1; |
2365 | } | |
252b5132 RH |
2366 | } |
2367 | ++i; | |
2368 | } | |
2369 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2370 | } | |
2371 | ||
2372 | mips16_op_hash = hash_new (); | |
2373 | ||
2374 | i = 0; | |
2375 | while (i < bfd_mips16_num_opcodes) | |
2376 | { | |
2377 | const char *name = mips16_opcodes[i].name; | |
2378 | ||
17a2f251 | 2379 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2380 | if (retval != NULL) |
2381 | as_fatal (_("internal: can't hash `%s': %s"), | |
2382 | mips16_opcodes[i].name, retval); | |
2383 | do | |
2384 | { | |
2385 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2386 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2387 | != mips16_opcodes[i].match)) | |
2388 | { | |
2389 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2390 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2391 | broken = 1; | |
2392 | } | |
1e915849 RS |
2393 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2394 | { | |
2395 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2396 | mips16_nop_insn.fixed_p = 1; | |
2397 | } | |
252b5132 RH |
2398 | ++i; |
2399 | } | |
2400 | while (i < bfd_mips16_num_opcodes | |
2401 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2402 | } | |
2403 | ||
df58fc94 RS |
2404 | micromips_op_hash = hash_new (); |
2405 | ||
2406 | i = 0; | |
2407 | while (i < bfd_micromips_num_opcodes) | |
2408 | { | |
2409 | const char *name = micromips_opcodes[i].name; | |
2410 | ||
2411 | retval = hash_insert (micromips_op_hash, name, | |
2412 | (void *) µmips_opcodes[i]); | |
2413 | if (retval != NULL) | |
2414 | as_fatal (_("internal: can't hash `%s': %s"), | |
2415 | micromips_opcodes[i].name, retval); | |
2416 | do | |
2417 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2418 | { | |
2419 | struct mips_cl_insn *micromips_nop_insn; | |
2420 | ||
2421 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2422 | broken = 1; | |
2423 | ||
2424 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2425 | micromips_nop_insn = µmips_nop16_insn; | |
2426 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2427 | micromips_nop_insn = µmips_nop32_insn; | |
2428 | else | |
2429 | continue; | |
2430 | ||
2431 | if (micromips_nop_insn->insn_mo == NULL | |
2432 | && strcmp (name, "nop") == 0) | |
2433 | { | |
2434 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2435 | micromips_nop_insn->fixed_p = 1; | |
2436 | } | |
2437 | } | |
2438 | while (++i < bfd_micromips_num_opcodes | |
2439 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2440 | } | |
2441 | ||
252b5132 RH |
2442 | if (broken) |
2443 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2444 | ||
2445 | /* We add all the general register names to the symbol table. This | |
2446 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2447 | for (i = 0; reg_names[i].name; i++) |
2448 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2449 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2450 | &zero_address_frag)); |
2451 | if (HAVE_NEWABI) | |
2452 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2453 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2454 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2455 | &zero_address_frag)); |
707bfff6 TS |
2456 | else |
2457 | for (i = 0; reg_names_o32[i].name; i++) | |
2458 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2459 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2460 | &zero_address_frag)); |
6047c971 | 2461 | |
7d10b47d | 2462 | mips_no_prev_insn (); |
252b5132 RH |
2463 | |
2464 | mips_gprmask = 0; | |
2465 | mips_cprmask[0] = 0; | |
2466 | mips_cprmask[1] = 0; | |
2467 | mips_cprmask[2] = 0; | |
2468 | mips_cprmask[3] = 0; | |
2469 | ||
2470 | /* set the default alignment for the text section (2**2) */ | |
2471 | record_alignment (text_section, 2); | |
2472 | ||
4d0d148d | 2473 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2474 | |
707bfff6 | 2475 | #ifdef OBJ_ELF |
f43abd2b | 2476 | if (IS_ELF) |
252b5132 | 2477 | { |
0a44bf69 RS |
2478 | /* On a native system other than VxWorks, sections must be aligned |
2479 | to 16 byte boundaries. When configured for an embedded ELF | |
2480 | target, we don't bother. */ | |
c41e87e3 CF |
2481 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2482 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2483 | { |
2484 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2485 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2486 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2487 | } | |
2488 | ||
2489 | /* Create a .reginfo section for register masks and a .mdebug | |
2490 | section for debugging information. */ | |
2491 | { | |
2492 | segT seg; | |
2493 | subsegT subseg; | |
2494 | flagword flags; | |
2495 | segT sec; | |
2496 | ||
2497 | seg = now_seg; | |
2498 | subseg = now_subseg; | |
2499 | ||
2500 | /* The ABI says this section should be loaded so that the | |
2501 | running program can access it. However, we don't load it | |
2502 | if we are configured for an embedded target */ | |
2503 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2504 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2505 | flags |= SEC_ALLOC | SEC_LOAD; |
2506 | ||
316f5878 | 2507 | if (mips_abi != N64_ABI) |
252b5132 RH |
2508 | { |
2509 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2510 | ||
195325d2 TS |
2511 | bfd_set_section_flags (stdoutput, sec, flags); |
2512 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2513 | |
252b5132 | 2514 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2515 | } |
2516 | else | |
2517 | { | |
2518 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2519 | .reginfo section. */ | |
2520 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2521 | bfd_set_section_flags (stdoutput, sec, flags); |
2522 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2523 | |
252b5132 RH |
2524 | /* Set up the option header. */ |
2525 | { | |
2526 | Elf_Internal_Options opthdr; | |
2527 | char *f; | |
2528 | ||
2529 | opthdr.kind = ODK_REGINFO; | |
2530 | opthdr.size = (sizeof (Elf_External_Options) | |
2531 | + sizeof (Elf64_External_RegInfo)); | |
2532 | opthdr.section = 0; | |
2533 | opthdr.info = 0; | |
2534 | f = frag_more (sizeof (Elf_External_Options)); | |
2535 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2536 | (Elf_External_Options *) f); | |
2537 | ||
2538 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2539 | } | |
252b5132 RH |
2540 | } |
2541 | ||
2542 | if (ECOFF_DEBUGGING) | |
2543 | { | |
2544 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2545 | (void) bfd_set_section_flags (stdoutput, sec, | |
2546 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2547 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2548 | } | |
f43abd2b | 2549 | else if (mips_flag_pdr) |
ecb4347a DJ |
2550 | { |
2551 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2552 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2553 | SEC_READONLY | SEC_RELOC | |
2554 | | SEC_DEBUGGING); | |
2555 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2556 | } | |
252b5132 RH |
2557 | |
2558 | subseg_set (seg, subseg); | |
2559 | } | |
2560 | } | |
707bfff6 | 2561 | #endif /* OBJ_ELF */ |
252b5132 RH |
2562 | |
2563 | if (! ECOFF_DEBUGGING) | |
2564 | md_obj_begin (); | |
71400594 RS |
2565 | |
2566 | if (mips_fix_vr4120) | |
2567 | init_vr4120_conflicts (); | |
252b5132 RH |
2568 | } |
2569 | ||
2570 | void | |
17a2f251 | 2571 | md_mips_end (void) |
252b5132 | 2572 | { |
02b1ab82 | 2573 | mips_emit_delays (); |
252b5132 RH |
2574 | if (! ECOFF_DEBUGGING) |
2575 | md_obj_end (); | |
2576 | } | |
2577 | ||
2578 | void | |
17a2f251 | 2579 | md_assemble (char *str) |
252b5132 RH |
2580 | { |
2581 | struct mips_cl_insn insn; | |
f6688943 TS |
2582 | bfd_reloc_code_real_type unused_reloc[3] |
2583 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2584 | |
2585 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2586 | imm2_expr.X_op = O_absent; |
252b5132 | 2587 | offset_expr.X_op = O_absent; |
f6688943 TS |
2588 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2589 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2590 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2591 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2592 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2593 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2594 | |
2595 | if (mips_opts.mips16) | |
2596 | mips16_ip (str, &insn); | |
2597 | else | |
2598 | { | |
2599 | mips_ip (str, &insn); | |
beae10d5 KH |
2600 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2601 | str, insn.insn_opcode)); | |
252b5132 RH |
2602 | } |
2603 | ||
2604 | if (insn_error) | |
2605 | { | |
2606 | as_bad ("%s `%s'", insn_error, str); | |
2607 | return; | |
2608 | } | |
2609 | ||
2610 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2611 | { | |
584892a6 | 2612 | macro_start (); |
252b5132 RH |
2613 | if (mips_opts.mips16) |
2614 | mips16_macro (&insn); | |
2615 | else | |
2616 | macro (&insn); | |
584892a6 | 2617 | macro_end (); |
252b5132 RH |
2618 | } |
2619 | else | |
2620 | { | |
2621 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2622 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2623 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2624 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2625 | else |
df58fc94 | 2626 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2627 | } |
2628 | } | |
2629 | ||
738e5348 RS |
2630 | /* Convenience functions for abstracting away the differences between |
2631 | MIPS16 and non-MIPS16 relocations. */ | |
2632 | ||
2633 | static inline bfd_boolean | |
2634 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2635 | { | |
2636 | switch (reloc) | |
2637 | { | |
2638 | case BFD_RELOC_MIPS16_JMP: | |
2639 | case BFD_RELOC_MIPS16_GPREL: | |
2640 | case BFD_RELOC_MIPS16_GOT16: | |
2641 | case BFD_RELOC_MIPS16_CALL16: | |
2642 | case BFD_RELOC_MIPS16_HI16_S: | |
2643 | case BFD_RELOC_MIPS16_HI16: | |
2644 | case BFD_RELOC_MIPS16_LO16: | |
2645 | return TRUE; | |
2646 | ||
2647 | default: | |
2648 | return FALSE; | |
2649 | } | |
2650 | } | |
2651 | ||
df58fc94 RS |
2652 | static inline bfd_boolean |
2653 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2654 | { | |
2655 | switch (reloc) | |
2656 | { | |
2657 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2658 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2659 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2660 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2661 | case BFD_RELOC_MICROMIPS_JMP: | |
2662 | case BFD_RELOC_MICROMIPS_HI16: | |
2663 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2664 | case BFD_RELOC_MICROMIPS_LO16: | |
2665 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2666 | case BFD_RELOC_MICROMIPS_GOT16: | |
2667 | case BFD_RELOC_MICROMIPS_CALL16: | |
2668 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2669 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2670 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2671 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2672 | case BFD_RELOC_MICROMIPS_SUB: | |
2673 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2674 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2675 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2676 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2677 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2678 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2679 | case BFD_RELOC_MICROMIPS_JALR: | |
2680 | return TRUE; | |
2681 | ||
2682 | default: | |
2683 | return FALSE; | |
2684 | } | |
2685 | } | |
2686 | ||
2309ddf2 MR |
2687 | static inline bfd_boolean |
2688 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2689 | { | |
2690 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2691 | } | |
2692 | ||
738e5348 RS |
2693 | static inline bfd_boolean |
2694 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2695 | { | |
2309ddf2 | 2696 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2697 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2698 | } |
2699 | ||
2700 | static inline bfd_boolean | |
2701 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2702 | { | |
2309ddf2 | 2703 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2704 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2705 | } |
2706 | ||
2707 | static inline bfd_boolean | |
2708 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2709 | { | |
2309ddf2 | 2710 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2711 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2712 | } | |
2713 | ||
df58fc94 RS |
2714 | static inline bfd_boolean |
2715 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2716 | { | |
2309ddf2 | 2717 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2718 | } |
2719 | ||
5919d012 | 2720 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2721 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2722 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2723 | |
2724 | static inline bfd_boolean | |
17a2f251 | 2725 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2726 | { |
3b91255e | 2727 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2728 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2729 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2730 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2731 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2732 | } | |
2733 | ||
2734 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2735 | reloc_needs_lo_p. */ | |
2736 | ||
2737 | static inline bfd_reloc_code_real_type | |
2738 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2739 | { | |
df58fc94 RS |
2740 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2741 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2742 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2743 | } |
2744 | ||
2745 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2746 | relocation. */ | |
2747 | ||
2748 | static inline bfd_boolean | |
17a2f251 | 2749 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2750 | { |
2751 | return (fixp->fx_next != NULL | |
738e5348 | 2752 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2753 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2754 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2755 | } | |
2756 | ||
252b5132 RH |
2757 | /* This function returns true if modifying a register requires a |
2758 | delay. */ | |
2759 | ||
2760 | static int | |
17a2f251 | 2761 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2762 | { |
2763 | unsigned long prev_pinfo; | |
2764 | ||
47e39b9d | 2765 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2766 | if (! mips_opts.noreorder |
81912461 ILT |
2767 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2768 | && ! gpr_interlocks) | |
2769 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2770 | && ! cop_interlocks))) | |
252b5132 | 2771 | { |
81912461 ILT |
2772 | /* A load from a coprocessor or from memory. All load delays |
2773 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2774 | /* Itbl support may require additional care here. */ |
252b5132 | 2775 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2776 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2777 | return 1; |
2778 | } | |
2779 | ||
2780 | return 0; | |
2781 | } | |
2782 | ||
462427c4 RS |
2783 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
2784 | says whether the labels refer to text or data. */ | |
404a8071 RS |
2785 | |
2786 | static void | |
462427c4 | 2787 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
2788 | { |
2789 | struct insn_label_list *l; | |
2790 | valueT val; | |
2791 | ||
462427c4 | 2792 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 2793 | { |
9c2799c2 | 2794 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2795 | symbol_set_frag (l->label, frag_now); |
2796 | val = (valueT) frag_now_fix (); | |
df58fc94 | 2797 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 2798 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
2799 | ++val; |
2800 | S_SET_VALUE (l->label, val); | |
2801 | } | |
2802 | } | |
2803 | ||
462427c4 RS |
2804 | /* Move all labels in insn_labels to the current insertion point |
2805 | and treat them as text labels. */ | |
2806 | ||
2807 | static void | |
2808 | mips_move_text_labels (void) | |
2809 | { | |
2810 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
2811 | } | |
2812 | ||
5f0fe04b TS |
2813 | static bfd_boolean |
2814 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2815 | { | |
2816 | bfd_boolean linkonce = FALSE; | |
2817 | segT symseg = S_GET_SEGMENT (sym); | |
2818 | ||
2819 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2820 | { | |
2821 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2822 | linkonce = TRUE; | |
2823 | #ifdef OBJ_ELF | |
2824 | /* The GNU toolchain uses an extension for ELF: a section | |
2825 | beginning with the magic string .gnu.linkonce is a | |
2826 | linkonce section. */ | |
2827 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2828 | sizeof ".gnu.linkonce" - 1) == 0) | |
2829 | linkonce = TRUE; | |
2830 | #endif | |
2831 | } | |
2832 | return linkonce; | |
2833 | } | |
2834 | ||
df58fc94 RS |
2835 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2836 | linker to handle them specially, such as generating jalx instructions | |
2837 | when needed. We also make them odd for the duration of the assembly, | |
2838 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2839 | in the adjust_symtab routine, while leaving them marked. This is |
2840 | convenient for the debugger and the disassembler. The linker knows | |
2841 | to make them odd again. */ | |
2842 | ||
2843 | static void | |
df58fc94 | 2844 | mips_compressed_mark_labels (void) |
252b5132 | 2845 | { |
a8dbcb85 TS |
2846 | segment_info_type *si = seg_info (now_seg); |
2847 | struct insn_label_list *l; | |
252b5132 | 2848 | |
df58fc94 | 2849 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2850 | |
2851 | for (l = si->label_list; l != NULL; l = l->next) | |
2852 | { | |
2853 | symbolS *label = l->label; | |
2854 | ||
2855 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2856 | if (IS_ELF) |
df58fc94 RS |
2857 | { |
2858 | if (mips_opts.mips16) | |
2859 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2860 | else | |
2861 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2862 | } | |
252b5132 | 2863 | #endif |
5f0fe04b TS |
2864 | if ((S_GET_VALUE (label) & 1) == 0 |
2865 | /* Don't adjust the address if the label is global or weak, or | |
2866 | in a link-once section, since we'll be emitting symbol reloc | |
2867 | references to it which will be patched up by the linker, and | |
df58fc94 | 2868 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2869 | && ! S_IS_WEAK (label) |
2870 | && ! S_IS_EXTERNAL (label) | |
2871 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2872 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2873 | } |
2874 | } | |
2875 | ||
4d7206a2 RS |
2876 | /* End the current frag. Make it a variant frag and record the |
2877 | relaxation info. */ | |
2878 | ||
2879 | static void | |
2880 | relax_close_frag (void) | |
2881 | { | |
584892a6 | 2882 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2883 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2884 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2885 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2886 | ||
2887 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2888 | mips_relax.first_fixup = 0; | |
2889 | } | |
2890 | ||
2891 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2892 | See the comment above RELAX_ENCODE for more details. */ | |
2893 | ||
2894 | static void | |
2895 | relax_start (symbolS *symbol) | |
2896 | { | |
9c2799c2 | 2897 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2898 | mips_relax.sequence = 1; |
2899 | mips_relax.symbol = symbol; | |
2900 | } | |
2901 | ||
2902 | /* Start generating the second version of a relaxable sequence. | |
2903 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2904 | |
2905 | static void | |
4d7206a2 RS |
2906 | relax_switch (void) |
2907 | { | |
9c2799c2 | 2908 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2909 | mips_relax.sequence = 2; |
2910 | } | |
2911 | ||
2912 | /* End the current relaxable sequence. */ | |
2913 | ||
2914 | static void | |
2915 | relax_end (void) | |
2916 | { | |
9c2799c2 | 2917 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2918 | relax_close_frag (); |
2919 | mips_relax.sequence = 0; | |
2920 | } | |
2921 | ||
11625dd8 RS |
2922 | /* Return true if IP is a delayed branch or jump. */ |
2923 | ||
2924 | static inline bfd_boolean | |
2925 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2926 | { | |
2927 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2928 | | INSN_COND_BRANCH_DELAY | |
2929 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2930 | } | |
2931 | ||
2932 | /* Return true if IP is a compact branch or jump. */ | |
2933 | ||
2934 | static inline bfd_boolean | |
2935 | compact_branch_p (const struct mips_cl_insn *ip) | |
2936 | { | |
2937 | if (mips_opts.mips16) | |
2938 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2939 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2940 | else | |
2941 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2942 | | INSN2_COND_BRANCH)) != 0; | |
2943 | } | |
2944 | ||
2945 | /* Return true if IP is an unconditional branch or jump. */ | |
2946 | ||
2947 | static inline bfd_boolean | |
2948 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2949 | { | |
2950 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2951 | || (mips_opts.mips16 | |
2952 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2953 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2954 | } | |
2955 | ||
2956 | /* Return true if IP is a branch-likely instruction. */ | |
2957 | ||
2958 | static inline bfd_boolean | |
2959 | branch_likely_p (const struct mips_cl_insn *ip) | |
2960 | { | |
2961 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2962 | } | |
2963 | ||
14fe068b RS |
2964 | /* Return the type of nop that should be used to fill the delay slot |
2965 | of delayed branch IP. */ | |
2966 | ||
2967 | static struct mips_cl_insn * | |
2968 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2969 | { | |
2970 | if (mips_opts.micromips | |
2971 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2972 | return µmips_nop32_insn; | |
2973 | return NOP_INSN; | |
2974 | } | |
2975 | ||
2309ddf2 | 2976 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2977 | |
2978 | static unsigned int | |
2979 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2980 | { | |
2309ddf2 | 2981 | unsigned long pinfo2; |
df58fc94 RS |
2982 | unsigned int mask; |
2983 | ||
2984 | mask = 0; | |
df58fc94 RS |
2985 | pinfo2 = ip->insn_mo->pinfo2; |
2986 | if (mips_opts.micromips) | |
2987 | { | |
df58fc94 RS |
2988 | if (pinfo2 & INSN2_MOD_GPR_MD) |
2989 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
2990 | if (pinfo2 & INSN2_MOD_GPR_MF) |
2991 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
2992 | if (pinfo2 & INSN2_MOD_SP) |
2993 | mask |= 1 << SP; | |
2994 | } | |
2995 | return mask; | |
2996 | } | |
2997 | ||
4c260379 RS |
2998 | /* Return the mask of core registers that IP reads. */ |
2999 | ||
3000 | static unsigned int | |
3001 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3002 | { | |
3003 | unsigned long pinfo, pinfo2; | |
3004 | unsigned int mask; | |
3005 | ||
df58fc94 | 3006 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3007 | pinfo = ip->insn_mo->pinfo; |
3008 | pinfo2 = ip->insn_mo->pinfo2; | |
3009 | if (mips_opts.mips16) | |
3010 | { | |
3011 | if (pinfo & MIPS16_INSN_READ_X) | |
3012 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3013 | if (pinfo & MIPS16_INSN_READ_Y) | |
3014 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3015 | if (pinfo & MIPS16_INSN_READ_T) | |
3016 | mask |= 1 << TREG; | |
3017 | if (pinfo & MIPS16_INSN_READ_SP) | |
3018 | mask |= 1 << SP; | |
3019 | if (pinfo & MIPS16_INSN_READ_31) | |
3020 | mask |= 1 << RA; | |
3021 | if (pinfo & MIPS16_INSN_READ_Z) | |
3022 | mask |= 1 << (mips16_to_32_reg_map | |
3023 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3024 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3025 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3026 | } | |
3027 | else | |
3028 | { | |
3029 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3030 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3031 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3032 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3033 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3034 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3035 | if (pinfo2 & INSN2_READ_GP) | |
3036 | mask |= 1 << GP; | |
3037 | if (pinfo2 & INSN2_READ_GPR_31) | |
3038 | mask |= 1 << RA; | |
4c260379 | 3039 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3040 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3041 | } |
2b0c8b40 MR |
3042 | if (mips_opts.micromips) |
3043 | { | |
3044 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3045 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3046 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3047 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3048 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3049 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3050 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3051 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3052 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3053 | { | |
3054 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3055 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3056 | } | |
3057 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3058 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3059 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3060 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3061 | } | |
fe35f09f RS |
3062 | /* Don't include register 0. */ |
3063 | return mask & ~1; | |
4c260379 RS |
3064 | } |
3065 | ||
3066 | /* Return the mask of core registers that IP writes. */ | |
3067 | ||
3068 | static unsigned int | |
3069 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3070 | { | |
3071 | unsigned long pinfo, pinfo2; | |
3072 | unsigned int mask; | |
3073 | ||
df58fc94 | 3074 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3075 | pinfo = ip->insn_mo->pinfo; |
3076 | pinfo2 = ip->insn_mo->pinfo2; | |
3077 | if (mips_opts.mips16) | |
3078 | { | |
3079 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3080 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3081 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3082 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3083 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3084 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3085 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3086 | mask |= 1 << TREG; | |
3087 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3088 | mask |= 1 << SP; | |
3089 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3090 | mask |= 1 << RA; | |
3091 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3092 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3093 | } | |
3094 | else | |
3095 | { | |
3096 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3097 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3098 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3099 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3100 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3101 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3102 | if (pinfo & INSN_WRITE_GPR_31) |
3103 | mask |= 1 << RA; | |
3104 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3105 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3106 | } |
2b0c8b40 MR |
3107 | if (mips_opts.micromips) |
3108 | { | |
3109 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3110 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3111 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3112 | { | |
3113 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3114 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3115 | } | |
3116 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3117 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3118 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3119 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3120 | } | |
fe35f09f RS |
3121 | /* Don't include register 0. */ |
3122 | return mask & ~1; | |
4c260379 RS |
3123 | } |
3124 | ||
3125 | /* Return the mask of floating-point registers that IP reads. */ | |
3126 | ||
3127 | static unsigned int | |
3128 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3129 | { | |
3130 | unsigned long pinfo, pinfo2; | |
3131 | unsigned int mask; | |
3132 | ||
3133 | mask = 0; | |
3134 | pinfo = ip->insn_mo->pinfo; | |
3135 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3136 | if (!mips_opts.mips16) |
df58fc94 RS |
3137 | { |
3138 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3139 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3140 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3141 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3142 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3143 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3144 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3145 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3146 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3147 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3148 | } |
3149 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3150 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3151 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3152 | mask |= mask << 1; | |
3153 | return mask; | |
3154 | } | |
3155 | ||
3156 | /* Return the mask of floating-point registers that IP writes. */ | |
3157 | ||
3158 | static unsigned int | |
3159 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3160 | { | |
3161 | unsigned long pinfo, pinfo2; | |
3162 | unsigned int mask; | |
3163 | ||
3164 | mask = 0; | |
3165 | pinfo = ip->insn_mo->pinfo; | |
3166 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3167 | if (!mips_opts.mips16) |
4c260379 RS |
3168 | { |
3169 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3170 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3171 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3172 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3173 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3174 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3175 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3176 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3177 | } |
3178 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3179 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3180 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3181 | mask |= mask << 1; | |
3182 | return mask; | |
3183 | } | |
3184 | ||
71400594 RS |
3185 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3186 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3187 | by VR4120 errata. */ | |
4d7206a2 | 3188 | |
71400594 RS |
3189 | static unsigned int |
3190 | classify_vr4120_insn (const char *name) | |
252b5132 | 3191 | { |
71400594 RS |
3192 | if (strncmp (name, "macc", 4) == 0) |
3193 | return FIX_VR4120_MACC; | |
3194 | if (strncmp (name, "dmacc", 5) == 0) | |
3195 | return FIX_VR4120_DMACC; | |
3196 | if (strncmp (name, "mult", 4) == 0) | |
3197 | return FIX_VR4120_MULT; | |
3198 | if (strncmp (name, "dmult", 5) == 0) | |
3199 | return FIX_VR4120_DMULT; | |
3200 | if (strstr (name, "div")) | |
3201 | return FIX_VR4120_DIV; | |
3202 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3203 | return FIX_VR4120_MTHILO; | |
3204 | return NUM_FIX_VR4120_CLASSES; | |
3205 | } | |
252b5132 | 3206 | |
ff239038 CM |
3207 | #define INSN_ERET 0x42000018 |
3208 | #define INSN_DERET 0x4200001f | |
3209 | ||
71400594 RS |
3210 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3211 | where INSN1 is the earlier instruction. Return the worst-case value | |
3212 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3213 | |
71400594 RS |
3214 | static unsigned int |
3215 | insns_between (const struct mips_cl_insn *insn1, | |
3216 | const struct mips_cl_insn *insn2) | |
3217 | { | |
3218 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3219 | unsigned int mask; |
71400594 RS |
3220 | |
3221 | /* This function needs to know which pinfo flags are set for INSN2 | |
3222 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3223 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3224 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3225 | pinfo1 = insn1->insn_mo->pinfo; |
3226 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3227 | |
4c260379 RS |
3228 | #define INSN2_USES_GPR(REG) \ |
3229 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3230 | |
3231 | /* For most targets, write-after-read dependencies on the HI and LO | |
3232 | registers must be separated by at least two instructions. */ | |
3233 | if (!hilo_interlocks) | |
252b5132 | 3234 | { |
71400594 RS |
3235 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3236 | return 2; | |
3237 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3238 | return 2; | |
3239 | } | |
3240 | ||
3241 | /* If we're working around r7000 errata, there must be two instructions | |
3242 | between an mfhi or mflo and any instruction that uses the result. */ | |
3243 | if (mips_7000_hilo_fix | |
df58fc94 | 3244 | && !mips_opts.micromips |
71400594 | 3245 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3246 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3247 | return 2; |
3248 | ||
ff239038 CM |
3249 | /* If we're working around 24K errata, one instruction is required |
3250 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3251 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3252 | { |
3253 | if (insn1->insn_opcode == INSN_ERET | |
3254 | || insn1->insn_opcode == INSN_DERET) | |
3255 | { | |
3256 | if (insn2 == NULL | |
3257 | || insn2->insn_opcode == INSN_ERET | |
3258 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3259 | || delayed_branch_p (insn2)) |
ff239038 CM |
3260 | return 1; |
3261 | } | |
3262 | } | |
3263 | ||
71400594 RS |
3264 | /* If working around VR4120 errata, check for combinations that need |
3265 | a single intervening instruction. */ | |
df58fc94 | 3266 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3267 | { |
3268 | unsigned int class1, class2; | |
252b5132 | 3269 | |
71400594 RS |
3270 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3271 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3272 | { |
71400594 RS |
3273 | if (insn2 == NULL) |
3274 | return 1; | |
3275 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3276 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3277 | return 1; | |
252b5132 | 3278 | } |
71400594 RS |
3279 | } |
3280 | ||
df58fc94 | 3281 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3282 | { |
3283 | /* Check for GPR or coprocessor load delays. All such delays | |
3284 | are on the RT register. */ | |
3285 | /* Itbl support may require additional care here. */ | |
3286 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3287 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3288 | { |
71400594 | 3289 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3290 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3291 | return 1; |
3292 | } | |
3293 | ||
3294 | /* Check for generic coprocessor hazards. | |
3295 | ||
3296 | This case is not handled very well. There is no special | |
3297 | knowledge of CP0 handling, and the coprocessors other than | |
3298 | the floating point unit are not distinguished at all. */ | |
3299 | /* Itbl support may require additional care here. FIXME! | |
3300 | Need to modify this to include knowledge about | |
3301 | user specified delays! */ | |
3302 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3303 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3304 | { | |
3305 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3306 | register. There must be a one instruction delay before INSN2 | |
3307 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3308 | mask = fpr_write_mask (insn1); |
3309 | if (mask != 0) | |
252b5132 | 3310 | { |
4c260379 | 3311 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3312 | return 1; |
252b5132 RH |
3313 | } |
3314 | else | |
3315 | { | |
71400594 RS |
3316 | /* Read-after-write dependencies on the control registers |
3317 | require a two-instruction gap. */ | |
3318 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3319 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3320 | return 2; | |
3321 | ||
3322 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3323 | also a coprocessor instruction, assume there must be | |
3324 | a one instruction gap. */ | |
3325 | if (pinfo2 & INSN_COP) | |
3326 | return 1; | |
252b5132 RH |
3327 | } |
3328 | } | |
6b76fefe | 3329 | |
71400594 RS |
3330 | /* Check for read-after-write dependencies on the coprocessor |
3331 | control registers in cases where INSN1 does not need a general | |
3332 | coprocessor delay. This means that INSN1 is a floating point | |
3333 | comparison instruction. */ | |
3334 | /* Itbl support may require additional care here. */ | |
3335 | else if (!cop_interlocks | |
3336 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3337 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3338 | return 1; | |
3339 | } | |
6b76fefe | 3340 | |
4c260379 | 3341 | #undef INSN2_USES_GPR |
6b76fefe | 3342 | |
71400594 RS |
3343 | return 0; |
3344 | } | |
6b76fefe | 3345 | |
7d8e00cf RS |
3346 | /* Return the number of nops that would be needed to work around the |
3347 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3348 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3349 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3350 | |
3351 | static int | |
932d1a1b | 3352 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3353 | const struct mips_cl_insn *insn) |
3354 | { | |
4c260379 RS |
3355 | int i, j; |
3356 | unsigned int mask; | |
7d8e00cf RS |
3357 | |
3358 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3359 | are not affected by the errata. */ | |
3360 | if (insn != 0 | |
3361 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3362 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3363 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3364 | return 0; | |
3365 | ||
3366 | /* Search for the first MFLO or MFHI. */ | |
3367 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3368 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3369 | { |
3370 | /* Extract the destination register. */ | |
4c260379 | 3371 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3372 | |
3373 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3374 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3375 | return 0; |
3376 | ||
3377 | /* ...or if any of the intervening instructions do. */ | |
3378 | for (j = 0; j < i; j++) | |
4c260379 | 3379 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3380 | return 0; |
3381 | ||
932d1a1b RS |
3382 | if (i >= ignore) |
3383 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3384 | } |
3385 | return 0; | |
3386 | } | |
3387 | ||
15be625d CM |
3388 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3389 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3390 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3391 | ||
3392 | /* Return the minimum alignment for this store instruction. */ | |
3393 | ||
3394 | static int | |
3395 | fix_24k_align_to (const struct mips_opcode *mo) | |
3396 | { | |
3397 | if (strcmp (mo->name, "sh") == 0) | |
3398 | return 2; | |
3399 | ||
3400 | if (strcmp (mo->name, "swc1") == 0 | |
3401 | || strcmp (mo->name, "swc2") == 0 | |
3402 | || strcmp (mo->name, "sw") == 0 | |
3403 | || strcmp (mo->name, "sc") == 0 | |
3404 | || strcmp (mo->name, "s.s") == 0) | |
3405 | return 4; | |
3406 | ||
3407 | if (strcmp (mo->name, "sdc1") == 0 | |
3408 | || strcmp (mo->name, "sdc2") == 0 | |
3409 | || strcmp (mo->name, "s.d") == 0) | |
3410 | return 8; | |
3411 | ||
3412 | /* sb, swl, swr */ | |
3413 | return 1; | |
3414 | } | |
3415 | ||
3416 | struct fix_24k_store_info | |
3417 | { | |
3418 | /* Immediate offset, if any, for this store instruction. */ | |
3419 | short off; | |
3420 | /* Alignment required by this store instruction. */ | |
3421 | int align_to; | |
3422 | /* True for register offsets. */ | |
3423 | int register_offset; | |
3424 | }; | |
3425 | ||
3426 | /* Comparison function used by qsort. */ | |
3427 | ||
3428 | static int | |
3429 | fix_24k_sort (const void *a, const void *b) | |
3430 | { | |
3431 | const struct fix_24k_store_info *pos1 = a; | |
3432 | const struct fix_24k_store_info *pos2 = b; | |
3433 | ||
3434 | return (pos1->off - pos2->off); | |
3435 | } | |
3436 | ||
3437 | /* INSN is a store instruction. Try to record the store information | |
3438 | in STINFO. Return false if the information isn't known. */ | |
3439 | ||
3440 | static bfd_boolean | |
3441 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3442 | const struct mips_cl_insn *insn) |
15be625d CM |
3443 | { |
3444 | /* The instruction must have a known offset. */ | |
3445 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3446 | return FALSE; | |
3447 | ||
3448 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3449 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3450 | return TRUE; | |
3451 | } | |
3452 | ||
932d1a1b RS |
3453 | /* Return the number of nops that would be needed to work around the 24k |
3454 | "lost data on stores during refill" errata if instruction INSN | |
3455 | immediately followed the 2 instructions described by HIST. | |
3456 | Ignore hazards that are contained within the first IGNORE | |
3457 | instructions of HIST. | |
3458 | ||
3459 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3460 | for the data cache refills and store data. The following describes | |
3461 | the scenario where the store data could be lost. | |
3462 | ||
3463 | * A data cache miss, due to either a load or a store, causing fill | |
3464 | data to be supplied by the memory subsystem | |
3465 | * The first three doublewords of fill data are returned and written | |
3466 | into the cache | |
3467 | * A sequence of four stores occurs in consecutive cycles around the | |
3468 | final doubleword of the fill: | |
3469 | * Store A | |
3470 | * Store B | |
3471 | * Store C | |
3472 | * Zero, One or more instructions | |
3473 | * Store D | |
3474 | ||
3475 | The four stores A-D must be to different doublewords of the line that | |
3476 | is being filled. The fourth instruction in the sequence above permits | |
3477 | the fill of the final doubleword to be transferred from the FSB into | |
3478 | the cache. In the sequence above, the stores may be either integer | |
3479 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3480 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3481 | different doublewords on the line. If the floating point unit is | |
3482 | running in 1:2 mode, it is not possible to create the sequence above | |
3483 | using only floating point store instructions. | |
15be625d CM |
3484 | |
3485 | In this case, the cache line being filled is incorrectly marked | |
3486 | invalid, thereby losing the data from any store to the line that | |
3487 | occurs between the original miss and the completion of the five | |
3488 | cycle sequence shown above. | |
3489 | ||
932d1a1b | 3490 | The workarounds are: |
15be625d | 3491 | |
932d1a1b RS |
3492 | * Run the data cache in write-through mode. |
3493 | * Insert a non-store instruction between | |
3494 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3495 | |
3496 | static int | |
932d1a1b | 3497 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3498 | const struct mips_cl_insn *insn) |
3499 | { | |
3500 | struct fix_24k_store_info pos[3]; | |
3501 | int align, i, base_offset; | |
3502 | ||
932d1a1b RS |
3503 | if (ignore >= 2) |
3504 | return 0; | |
3505 | ||
ab9794cf RS |
3506 | /* If the previous instruction wasn't a store, there's nothing to |
3507 | worry about. */ | |
15be625d CM |
3508 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3509 | return 0; | |
3510 | ||
ab9794cf RS |
3511 | /* If the instructions after the previous one are unknown, we have |
3512 | to assume the worst. */ | |
3513 | if (!insn) | |
15be625d CM |
3514 | return 1; |
3515 | ||
ab9794cf RS |
3516 | /* Check whether we are dealing with three consecutive stores. */ |
3517 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3518 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3519 | return 0; |
3520 | ||
3521 | /* If we don't know the relationship between the store addresses, | |
3522 | assume the worst. */ | |
ab9794cf | 3523 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3524 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3525 | return 1; | |
3526 | ||
3527 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3528 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3529 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3530 | return 1; | |
3531 | ||
3532 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3533 | ||
3534 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3535 | X bytes and such that the base register + X is known to be aligned | |
3536 | to align bytes. */ | |
3537 | ||
3538 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3539 | align = 8; | |
3540 | else | |
3541 | { | |
3542 | align = pos[0].align_to; | |
3543 | base_offset = pos[0].off; | |
3544 | for (i = 1; i < 3; i++) | |
3545 | if (align < pos[i].align_to) | |
3546 | { | |
3547 | align = pos[i].align_to; | |
3548 | base_offset = pos[i].off; | |
3549 | } | |
3550 | for (i = 0; i < 3; i++) | |
3551 | pos[i].off -= base_offset; | |
3552 | } | |
3553 | ||
3554 | pos[0].off &= ~align + 1; | |
3555 | pos[1].off &= ~align + 1; | |
3556 | pos[2].off &= ~align + 1; | |
3557 | ||
3558 | /* If any two stores write to the same chunk, they also write to the | |
3559 | same doubleword. The offsets are still sorted at this point. */ | |
3560 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3561 | return 0; | |
3562 | ||
3563 | /* A range of at least 9 bytes is needed for the stores to be in | |
3564 | non-overlapping doublewords. */ | |
3565 | if (pos[2].off - pos[0].off <= 8) | |
3566 | return 0; | |
3567 | ||
3568 | if (pos[2].off - pos[1].off >= 24 | |
3569 | || pos[1].off - pos[0].off >= 24 | |
3570 | || pos[2].off - pos[0].off >= 32) | |
3571 | return 0; | |
3572 | ||
3573 | return 1; | |
3574 | } | |
3575 | ||
71400594 | 3576 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3577 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3578 | where HIST[0] is the most recent instruction. Ignore hazards |
3579 | between INSN and the first IGNORE instructions in HIST. | |
3580 | ||
3581 | If INSN is null, return the worse-case number of nops for any | |
3582 | instruction. */ | |
bdaaa2e1 | 3583 | |
71400594 | 3584 | static int |
932d1a1b | 3585 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3586 | const struct mips_cl_insn *insn) |
3587 | { | |
3588 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3589 | |
71400594 | 3590 | nops = 0; |
932d1a1b | 3591 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3592 | { |
91d6fa6a | 3593 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3594 | if (tmp_nops > nops) |
3595 | nops = tmp_nops; | |
3596 | } | |
7d8e00cf | 3597 | |
df58fc94 | 3598 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3599 | { |
932d1a1b | 3600 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3601 | if (tmp_nops > nops) |
3602 | nops = tmp_nops; | |
3603 | } | |
3604 | ||
df58fc94 | 3605 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3606 | { |
932d1a1b | 3607 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3608 | if (tmp_nops > nops) |
3609 | nops = tmp_nops; | |
3610 | } | |
3611 | ||
71400594 RS |
3612 | return nops; |
3613 | } | |
252b5132 | 3614 | |
71400594 | 3615 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3616 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3617 | would be needed after the extended sequence, ignoring hazards |
3618 | in the first IGNORE instructions. */ | |
252b5132 | 3619 | |
71400594 | 3620 | static int |
932d1a1b RS |
3621 | nops_for_sequence (int num_insns, int ignore, |
3622 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3623 | { |
3624 | va_list args; | |
3625 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3626 | struct mips_cl_insn *cursor; | |
3627 | int nops; | |
3628 | ||
91d6fa6a | 3629 | va_start (args, hist); |
71400594 | 3630 | cursor = buffer + num_insns; |
91d6fa6a | 3631 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3632 | while (cursor > buffer) |
3633 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3634 | ||
932d1a1b | 3635 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3636 | va_end (args); |
3637 | return nops; | |
3638 | } | |
252b5132 | 3639 | |
71400594 RS |
3640 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3641 | worst-case delay for the branch target. */ | |
252b5132 | 3642 | |
71400594 | 3643 | static int |
932d1a1b | 3644 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3645 | const struct mips_cl_insn *insn) |
3646 | { | |
3647 | int nops, tmp_nops; | |
60b63b72 | 3648 | |
932d1a1b | 3649 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3650 | if (delayed_branch_p (insn)) |
71400594 | 3651 | { |
932d1a1b | 3652 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3653 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3654 | if (tmp_nops > nops) |
3655 | nops = tmp_nops; | |
3656 | } | |
11625dd8 | 3657 | else if (compact_branch_p (insn)) |
71400594 | 3658 | { |
932d1a1b | 3659 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3660 | if (tmp_nops > nops) |
3661 | nops = tmp_nops; | |
3662 | } | |
3663 | return nops; | |
3664 | } | |
3665 | ||
c67a084a NC |
3666 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3667 | ||
3668 | static void | |
3669 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3670 | { | |
df58fc94 | 3671 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3672 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3673 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3674 | } | |
3675 | ||
3676 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3677 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3678 | ||
3679 | static void | |
3680 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3681 | { | |
df58fc94 | 3682 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3683 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3684 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3685 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3686 | { | |
3687 | int sreg; | |
3688 | expressionS ep; | |
3689 | ||
3690 | if (! mips_opts.at) | |
3691 | return; | |
3692 | ||
df58fc94 | 3693 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3694 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3695 | return; | |
3696 | ||
3697 | ep.X_op = O_constant; | |
3698 | ep.X_add_number = 0xcfff0000; | |
3699 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3700 | ep.X_add_number = 0xffff; | |
3701 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3702 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3703 | } | |
3704 | } | |
3705 | ||
3706 | static void | |
3707 | fix_loongson2f (struct mips_cl_insn * ip) | |
3708 | { | |
3709 | if (mips_fix_loongson2f_nop) | |
3710 | fix_loongson2f_nop (ip); | |
3711 | ||
3712 | if (mips_fix_loongson2f_jump) | |
3713 | fix_loongson2f_jump (ip); | |
3714 | } | |
3715 | ||
a4e06468 RS |
3716 | /* IP is a branch that has a delay slot, and we need to fill it |
3717 | automatically. Return true if we can do that by swapping IP | |
3718 | with the previous instruction. */ | |
3719 | ||
3720 | static bfd_boolean | |
3721 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3722 | { | |
2b0c8b40 | 3723 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3724 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3725 | ||
3726 | /* -O2 and above is required for this optimization. */ | |
3727 | if (mips_optimize < 2) | |
3728 | return FALSE; | |
3729 | ||
3730 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3731 | if (mips_opts.nomove) | |
3732 | return FALSE; | |
3733 | ||
3734 | /* We can't swap if the previous instruction's position is fixed. */ | |
3735 | if (history[0].fixed_p) | |
3736 | return FALSE; | |
3737 | ||
3738 | /* If the previous previous insn was in a .set noreorder, we can't | |
3739 | swap. Actually, the MIPS assembler will swap in this situation. | |
3740 | However, gcc configured -with-gnu-as will generate code like | |
3741 | ||
3742 | .set noreorder | |
3743 | lw $4,XXX | |
3744 | .set reorder | |
3745 | INSN | |
3746 | bne $4,$0,foo | |
3747 | ||
3748 | in which we can not swap the bne and INSN. If gcc is not configured | |
3749 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3750 | if (history[1].noreorder_p) | |
3751 | return FALSE; | |
3752 | ||
87333bb7 MR |
3753 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3754 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3755 | if (mips_opts.mips16 && history[0].fixp[0]) |
3756 | return FALSE; | |
3757 | ||
3758 | /* If the branch is itself the target of a branch, we can not swap. | |
3759 | We cheat on this; all we check for is whether there is a label on | |
3760 | this instruction. If there are any branches to anything other than | |
3761 | a label, users must use .set noreorder. */ | |
3762 | if (seg_info (now_seg)->label_list) | |
3763 | return FALSE; | |
3764 | ||
3765 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3766 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3767 | MIPS16 code, which uses variant frags for different purposes. */ |
3768 | if (!mips_opts.mips16 | |
a4e06468 RS |
3769 | && history[0].frag |
3770 | && history[0].frag->fr_type == rs_machine_dependent) | |
3771 | return FALSE; | |
3772 | ||
bcd530a7 RS |
3773 | /* We do not swap with instructions that cannot architecturally |
3774 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3775 | also refrain from swapping with a trap instruction, since it | |
3776 | complicates trap handlers to have the trap instruction be in | |
3777 | a delay slot. */ | |
a4e06468 | 3778 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3779 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3780 | return FALSE; |
3781 | ||
3782 | /* Check for conflicts between the branch and the instructions | |
3783 | before the candidate delay slot. */ | |
3784 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3785 | return FALSE; | |
3786 | ||
3787 | /* Check for conflicts between the swapped sequence and the | |
3788 | target of the branch. */ | |
3789 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3790 | return FALSE; | |
3791 | ||
3792 | /* If the branch reads a register that the previous | |
3793 | instruction sets, we can not swap. */ | |
3794 | gpr_read = gpr_read_mask (ip); | |
3795 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3796 | if (gpr_read & prev_gpr_write) | |
3797 | return FALSE; | |
3798 | ||
3799 | /* If the branch writes a register that the previous | |
3800 | instruction sets, we can not swap. */ | |
3801 | gpr_write = gpr_write_mask (ip); | |
3802 | if (gpr_write & prev_gpr_write) | |
3803 | return FALSE; | |
3804 | ||
3805 | /* If the branch writes a register that the previous | |
3806 | instruction reads, we can not swap. */ | |
3807 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3808 | if (gpr_write & prev_gpr_read) | |
3809 | return FALSE; | |
3810 | ||
3811 | /* If one instruction sets a condition code and the | |
3812 | other one uses a condition code, we can not swap. */ | |
3813 | pinfo = ip->insn_mo->pinfo; | |
3814 | if ((pinfo & INSN_READ_COND_CODE) | |
3815 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3816 | return FALSE; | |
3817 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3818 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3819 | return FALSE; | |
3820 | ||
3821 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3822 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3823 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3824 | return FALSE; | |
2b0c8b40 MR |
3825 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3826 | return FALSE; | |
a4e06468 | 3827 | |
df58fc94 RS |
3828 | /* If the previous instruction has an incorrect size for a fixed |
3829 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3830 | pinfo2 = ip->insn_mo->pinfo2; |
3831 | if (mips_opts.micromips | |
3832 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3833 | && insn_length (history) != 2) | |
3834 | return FALSE; | |
3835 | if (mips_opts.micromips | |
3836 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3837 | && insn_length (history) != 4) | |
3838 | return FALSE; | |
3839 | ||
a4e06468 RS |
3840 | return TRUE; |
3841 | } | |
3842 | ||
3843 | /* Decide how we should add IP to the instruction stream. */ | |
3844 | ||
3845 | static enum append_method | |
3846 | get_append_method (struct mips_cl_insn *ip) | |
3847 | { | |
3848 | unsigned long pinfo; | |
3849 | ||
3850 | /* The relaxed version of a macro sequence must be inherently | |
3851 | hazard-free. */ | |
3852 | if (mips_relax.sequence == 2) | |
3853 | return APPEND_ADD; | |
3854 | ||
3855 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3856 | if (mips_opts.noreorder) | |
3857 | return APPEND_ADD; | |
3858 | ||
3859 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3860 | if (delayed_branch_p (ip)) |
a4e06468 | 3861 | { |
11625dd8 | 3862 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3863 | return APPEND_SWAP; |
3864 | ||
11625dd8 | 3865 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3866 | if (mips_opts.mips16 |
3867 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3868 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3869 | return APPEND_ADD_COMPACT; | |
3870 | ||
3871 | return APPEND_ADD_WITH_NOP; | |
3872 | } | |
3873 | ||
a4e06468 RS |
3874 | return APPEND_ADD; |
3875 | } | |
3876 | ||
ceb94aa5 RS |
3877 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3878 | Point IP->insn_mo to the new opcode's definition. */ | |
3879 | ||
3880 | static void | |
3881 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3882 | { | |
3883 | const struct mips_opcode *mo, *end; | |
3884 | ||
3885 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3886 | for (mo = ip->insn_mo; mo < end; mo++) | |
3887 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3888 | { | |
3889 | ip->insn_mo = mo; | |
3890 | return; | |
3891 | } | |
3892 | abort (); | |
3893 | } | |
3894 | ||
df58fc94 RS |
3895 | /* For microMIPS macros, we need to generate a local number label |
3896 | as the target of branches. */ | |
3897 | #define MICROMIPS_LABEL_CHAR '\037' | |
3898 | static unsigned long micromips_target_label; | |
3899 | static char micromips_target_name[32]; | |
3900 | ||
3901 | static char * | |
3902 | micromips_label_name (void) | |
3903 | { | |
3904 | char *p = micromips_target_name; | |
3905 | char symbol_name_temporary[24]; | |
3906 | unsigned long l; | |
3907 | int i; | |
3908 | ||
3909 | if (*p) | |
3910 | return p; | |
3911 | ||
3912 | i = 0; | |
3913 | l = micromips_target_label; | |
3914 | #ifdef LOCAL_LABEL_PREFIX | |
3915 | *p++ = LOCAL_LABEL_PREFIX; | |
3916 | #endif | |
3917 | *p++ = 'L'; | |
3918 | *p++ = MICROMIPS_LABEL_CHAR; | |
3919 | do | |
3920 | { | |
3921 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3922 | l /= 10; | |
3923 | } | |
3924 | while (l != 0); | |
3925 | while (i > 0) | |
3926 | *p++ = symbol_name_temporary[--i]; | |
3927 | *p = '\0'; | |
3928 | ||
3929 | return micromips_target_name; | |
3930 | } | |
3931 | ||
3932 | static void | |
3933 | micromips_label_expr (expressionS *label_expr) | |
3934 | { | |
3935 | label_expr->X_op = O_symbol; | |
3936 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3937 | label_expr->X_add_number = 0; | |
3938 | } | |
3939 | ||
3940 | static void | |
3941 | micromips_label_inc (void) | |
3942 | { | |
3943 | micromips_target_label++; | |
3944 | *micromips_target_name = '\0'; | |
3945 | } | |
3946 | ||
3947 | static void | |
3948 | micromips_add_label (void) | |
3949 | { | |
3950 | symbolS *s; | |
3951 | ||
3952 | s = colon (micromips_label_name ()); | |
3953 | micromips_label_inc (); | |
3954 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3955 | if (IS_ELF) | |
3956 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
3957 | #else |
3958 | (void) s; | |
df58fc94 RS |
3959 | #endif |
3960 | } | |
3961 | ||
3962 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3963 | corresponding to the requested one if any. Otherwise return | |
3964 | the reloc unchanged. */ | |
3965 | ||
3966 | static bfd_reloc_code_real_type | |
3967 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3968 | { | |
3969 | static const bfd_reloc_code_real_type relocs[][2] = | |
3970 | { | |
3971 | /* Keep sorted incrementally by the left-hand key. */ | |
3972 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3973 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3974 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3975 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3976 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3977 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3978 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3979 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3980 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3981 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3982 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3983 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3984 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3985 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3986 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3987 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3988 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3989 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3990 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3991 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3992 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3993 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3994 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3995 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3996 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3997 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3998 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3999 | }; | |
4000 | bfd_reloc_code_real_type r; | |
4001 | size_t i; | |
4002 | ||
4003 | if (!mips_opts.micromips) | |
4004 | return reloc; | |
4005 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4006 | { | |
4007 | r = relocs[i][0]; | |
4008 | if (r > reloc) | |
4009 | return reloc; | |
4010 | if (r == reloc) | |
4011 | return relocs[i][1]; | |
4012 | } | |
4013 | return reloc; | |
4014 | } | |
4015 | ||
71400594 RS |
4016 | /* Output an instruction. IP is the instruction information. |
4017 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4018 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4019 | a macro expansion. */ | |
71400594 RS |
4020 | |
4021 | static void | |
4022 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4023 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4024 | { |
14fe068b | 4025 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4026 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4027 | enum append_method method; |
2309ddf2 | 4028 | bfd_boolean relax32; |
2b0c8b40 | 4029 | int branch_disp; |
71400594 | 4030 | |
2309ddf2 | 4031 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4032 | fix_loongson2f (ip); |
4033 | ||
df58fc94 | 4034 | mips_mark_labels (); |
71400594 | 4035 | |
738f4d98 | 4036 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4037 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4038 | |
df58fc94 | 4039 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4040 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4041 | |
4042 | if (mips_opts.micromips | |
4043 | && !expansionp | |
4044 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4045 | && micromips_insn_length (ip->insn_mo) != 2) | |
4046 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4047 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4048 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4049 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4050 | |
15be625d CM |
4051 | if (address_expr == NULL) |
4052 | ip->complete_p = 1; | |
4053 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
4054 | && address_expr->X_op == O_constant) | |
4055 | { | |
4056 | unsigned int tmp; | |
4057 | ||
4058 | ip->complete_p = 1; | |
4059 | switch (*reloc_type) | |
4060 | { | |
4061 | case BFD_RELOC_32: | |
4062 | ip->insn_opcode |= address_expr->X_add_number; | |
4063 | break; | |
4064 | ||
4065 | case BFD_RELOC_MIPS_HIGHEST: | |
4066 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
4067 | ip->insn_opcode |= tmp & 0xffff; | |
4068 | break; | |
4069 | ||
4070 | case BFD_RELOC_MIPS_HIGHER: | |
4071 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
4072 | ip->insn_opcode |= tmp & 0xffff; | |
4073 | break; | |
4074 | ||
4075 | case BFD_RELOC_HI16_S: | |
4076 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
4077 | ip->insn_opcode |= tmp & 0xffff; | |
4078 | break; | |
4079 | ||
4080 | case BFD_RELOC_HI16: | |
4081 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4082 | break; | |
4083 | ||
4084 | case BFD_RELOC_UNUSED: | |
4085 | case BFD_RELOC_LO16: | |
4086 | case BFD_RELOC_MIPS_GOT_DISP: | |
4087 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4088 | break; | |
4089 | ||
4090 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4091 | { |
4092 | int shift; | |
4093 | ||
4094 | shift = mips_opts.micromips ? 1 : 2; | |
4095 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4096 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4097 | (unsigned long) address_expr->X_add_number); | |
4098 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4099 | & 0x3ffffff); | |
4100 | ip->complete_p = 0; | |
4101 | } | |
15be625d CM |
4102 | break; |
4103 | ||
4104 | case BFD_RELOC_MIPS16_JMP: | |
4105 | if ((address_expr->X_add_number & 3) != 0) | |
4106 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4107 | (unsigned long) address_expr->X_add_number); | |
4108 | ip->insn_opcode |= | |
4109 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4110 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4111 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4112 | ip->complete_p = 0; | |
4113 | break; | |
4114 | ||
4115 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4116 | { |
4117 | int shift; | |
4118 | ||
4119 | shift = mips_opts.micromips ? 1 : 2; | |
4120 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4121 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4122 | (unsigned long) address_expr->X_add_number); | |
4123 | if (!mips_relax_branch) | |
4124 | { | |
4125 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4126 | & ~((1 << (shift + 16)) - 1)) | |
4127 | as_bad (_("branch address range overflow (0x%lx)"), | |
4128 | (unsigned long) address_expr->X_add_number); | |
4129 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4130 | & 0xffff); | |
4131 | } | |
4132 | ip->complete_p = 0; | |
4133 | } | |
15be625d CM |
4134 | break; |
4135 | ||
4136 | default: | |
4137 | internalError (); | |
4138 | } | |
4139 | } | |
4140 | ||
71400594 RS |
4141 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4142 | { | |
4143 | /* There are a lot of optimizations we could do that we don't. | |
4144 | In particular, we do not, in general, reorder instructions. | |
4145 | If you use gcc with optimization, it will reorder | |
4146 | instructions and generally do much more optimization then we | |
4147 | do here; repeating all that work in the assembler would only | |
4148 | benefit hand written assembly code, and does not seem worth | |
4149 | it. */ | |
4150 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4151 | ? nops_for_insn (0, history, NULL) |
4152 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4153 | if (nops > 0) |
252b5132 RH |
4154 | { |
4155 | fragS *old_frag; | |
4156 | unsigned long old_frag_offset; | |
4157 | int i; | |
252b5132 RH |
4158 | |
4159 | old_frag = frag_now; | |
4160 | old_frag_offset = frag_now_fix (); | |
4161 | ||
4162 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4163 | add_fixed_insn (NOP_INSN); |
4164 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4165 | |
4166 | if (listing) | |
4167 | { | |
4168 | listing_prev_line (); | |
4169 | /* We may be at the start of a variant frag. In case we | |
4170 | are, make sure there is enough space for the frag | |
4171 | after the frags created by listing_prev_line. The | |
4172 | argument to frag_grow here must be at least as large | |
4173 | as the argument to all other calls to frag_grow in | |
4174 | this file. We don't have to worry about being in the | |
4175 | middle of a variant frag, because the variants insert | |
4176 | all needed nop instructions themselves. */ | |
4177 | frag_grow (40); | |
4178 | } | |
4179 | ||
462427c4 | 4180 | mips_move_text_labels (); |
252b5132 RH |
4181 | |
4182 | #ifndef NO_ECOFF_DEBUGGING | |
4183 | if (ECOFF_DEBUGGING) | |
4184 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4185 | #endif | |
4186 | } | |
71400594 RS |
4187 | } |
4188 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4189 | { | |
932d1a1b RS |
4190 | int nops; |
4191 | ||
4192 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4193 | ignoring hazards generated by the first prev_nop_frag_since | |
4194 | instructions. */ | |
4195 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4196 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4197 | |
71400594 RS |
4198 | /* Enforce NOPS as a minimum. */ |
4199 | if (nops > prev_nop_frag_required) | |
4200 | prev_nop_frag_required = nops; | |
252b5132 | 4201 | |
71400594 RS |
4202 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4203 | { | |
4204 | /* Settle for the current number of nops. Update the history | |
4205 | accordingly (for the benefit of any future .set reorder code). */ | |
4206 | prev_nop_frag = NULL; | |
4207 | insert_into_history (prev_nop_frag_since, | |
4208 | prev_nop_frag_holds, NOP_INSN); | |
4209 | } | |
4210 | else | |
4211 | { | |
4212 | /* Allow this instruction to replace one of the nops that was | |
4213 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4214 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4215 | prev_nop_frag_holds--; |
4216 | prev_nop_frag_since++; | |
252b5132 RH |
4217 | } |
4218 | } | |
4219 | ||
a4e06468 | 4220 | method = get_append_method (ip); |
2b0c8b40 | 4221 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4222 | |
58e2ea4d MR |
4223 | #ifdef OBJ_ELF |
4224 | /* The value passed to dwarf2_emit_insn is the distance between | |
4225 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4226 | should be recorded in the debug tables. This is normally the |
4227 | current address. | |
4228 | ||
df58fc94 RS |
4229 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4230 | addresses, so we use -1 for an address higher by one than the | |
4231 | current one. | |
e3a82c8e MR |
4232 | |
4233 | If the instruction produced is a branch that we will swap with | |
4234 | the preceding instruction, then we add the displacement by which | |
4235 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4236 | and for MIPS16/microMIPS code also prevents a debugger from |
4237 | placing a breakpoint in the middle of the branch (and corrupting | |
4238 | code if software breakpoints are used). */ | |
2b0c8b40 | 4239 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4240 | #endif |
4241 | ||
df58fc94 RS |
4242 | relax32 = (mips_relax_branch |
4243 | /* Don't try branch relaxation within .set nomacro, or within | |
4244 | .set noat if we use $at for PIC computations. If it turns | |
4245 | out that the branch was out-of-range, we'll get an error. */ | |
4246 | && !mips_opts.warn_about_macros | |
4247 | && (mips_opts.at || mips_pic == NO_PIC) | |
4248 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4249 | branches. */ | |
40209cad | 4250 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4251 | |
4252 | if (!HAVE_CODE_COMPRESSION | |
4253 | && address_expr | |
4254 | && relax32 | |
0b25d3e6 | 4255 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4256 | && delayed_branch_p (ip)) |
4a6a3df4 | 4257 | { |
895921c9 | 4258 | relaxed_branch = TRUE; |
1e915849 RS |
4259 | add_relaxed_insn (ip, (relaxed_branch_length |
4260 | (NULL, NULL, | |
11625dd8 RS |
4261 | uncond_branch_p (ip) ? -1 |
4262 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4263 | : 0)), 4, |
4264 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4265 | (AT, |
11625dd8 RS |
4266 | uncond_branch_p (ip), |
4267 | branch_likely_p (ip), | |
1e915849 RS |
4268 | pinfo & INSN_WRITE_GPR_31, |
4269 | 0), | |
4270 | address_expr->X_add_symbol, | |
4271 | address_expr->X_add_number); | |
4a6a3df4 AO |
4272 | *reloc_type = BFD_RELOC_UNUSED; |
4273 | } | |
df58fc94 RS |
4274 | else if (mips_opts.micromips |
4275 | && address_expr | |
4276 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4277 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4278 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4279 | /* Don't try branch relaxation when users specify | |
4280 | 16-bit/32-bit instructions. */ | |
4281 | && !forced_insn_length) | |
df58fc94 RS |
4282 | { |
4283 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4284 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4285 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4286 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4287 | int al = pinfo & INSN_WRITE_GPR_31; |
4288 | int length32; | |
4289 | ||
4290 | gas_assert (address_expr != NULL); | |
4291 | gas_assert (!mips_relax.sequence); | |
4292 | ||
2b0c8b40 | 4293 | relaxed_branch = TRUE; |
df58fc94 RS |
4294 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4295 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4296 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4297 | relax32, 0, 0), | |
df58fc94 RS |
4298 | address_expr->X_add_symbol, |
4299 | address_expr->X_add_number); | |
4300 | *reloc_type = BFD_RELOC_UNUSED; | |
4301 | } | |
4302 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4303 | { |
4304 | /* We need to set up a variant frag. */ | |
df58fc94 | 4305 | gas_assert (address_expr != NULL); |
1e915849 RS |
4306 | add_relaxed_insn (ip, 4, 0, |
4307 | RELAX_MIPS16_ENCODE | |
4308 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4309 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4310 | delayed_branch_p (&history[0]), |
1e915849 RS |
4311 | history[0].mips16_absolute_jump_p), |
4312 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4313 | } |
5c04167a | 4314 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4315 | { |
11625dd8 | 4316 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4317 | /* Make sure there is enough room to swap this instruction with |
4318 | a following jump instruction. */ | |
4319 | frag_grow (6); | |
1e915849 | 4320 | add_fixed_insn (ip); |
252b5132 RH |
4321 | } |
4322 | else | |
4323 | { | |
4324 | if (mips_opts.mips16 | |
4325 | && mips_opts.noreorder | |
11625dd8 | 4326 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4327 | as_warn (_("extended instruction in delay slot")); |
4328 | ||
4d7206a2 RS |
4329 | if (mips_relax.sequence) |
4330 | { | |
4331 | /* If we've reached the end of this frag, turn it into a variant | |
4332 | frag and record the information for the instructions we've | |
4333 | written so far. */ | |
4334 | if (frag_room () < 4) | |
4335 | relax_close_frag (); | |
df58fc94 | 4336 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4337 | } |
4338 | ||
584892a6 | 4339 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4340 | { |
4341 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4342 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4343 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4344 | mips_macro_warning.insns[0]++; | |
4345 | } | |
584892a6 | 4346 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4347 | { |
4348 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4349 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4350 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4351 | mips_macro_warning.insns[1]++; | |
4352 | } | |
584892a6 | 4353 | |
1e915849 RS |
4354 | if (mips_opts.mips16) |
4355 | { | |
4356 | ip->fixed_p = 1; | |
4357 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4358 | } | |
4359 | add_fixed_insn (ip); | |
252b5132 RH |
4360 | } |
4361 | ||
9fe77896 | 4362 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4363 | { |
df58fc94 | 4364 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4365 | reloc_howto_type *howto0; |
9fe77896 RS |
4366 | reloc_howto_type *howto; |
4367 | int i; | |
34ce925e | 4368 | |
df58fc94 RS |
4369 | /* Perform any necessary conversion to microMIPS relocations |
4370 | and find out how many relocations there actually are. */ | |
4371 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4372 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4373 | ||
9fe77896 RS |
4374 | /* In a compound relocation, it is the final (outermost) |
4375 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4376 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4377 | ||
9fe77896 RS |
4378 | if (howto == NULL) |
4379 | { | |
4380 | /* To reproduce this failure try assembling gas/testsuites/ | |
4381 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4382 | assembler. */ | |
df58fc94 RS |
4383 | as_bad (_("Unsupported MIPS relocation number %d"), |
4384 | final_type[i - 1]); | |
9fe77896 RS |
4385 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4386 | } | |
2309ddf2 MR |
4387 | |
4388 | if (i > 1) | |
4389 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4390 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4391 | bfd_get_reloc_size (howto), | |
4392 | address_expr, | |
2309ddf2 MR |
4393 | howto0 && howto0->pc_relative, |
4394 | final_type[0]); | |
9fe77896 RS |
4395 | |
4396 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4397 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4398 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4399 | ||
4400 | /* These relocations can have an addend that won't fit in | |
4401 | 4 octets for 64bit assembly. */ | |
4402 | if (HAVE_64BIT_GPRS | |
4403 | && ! howto->partial_inplace | |
4404 | && (reloc_type[0] == BFD_RELOC_16 | |
4405 | || reloc_type[0] == BFD_RELOC_32 | |
4406 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4407 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4408 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4409 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4410 | || reloc_type[0] == BFD_RELOC_64 | |
4411 | || reloc_type[0] == BFD_RELOC_CTOR | |
4412 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4413 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4414 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4415 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4416 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4417 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4418 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4419 | || hi16_reloc_p (reloc_type[0]) | |
4420 | || lo16_reloc_p (reloc_type[0]))) | |
4421 | ip->fixp[0]->fx_no_overflow = 1; | |
4422 | ||
4423 | if (mips_relax.sequence) | |
4424 | { | |
4425 | if (mips_relax.first_fixup == 0) | |
4426 | mips_relax.first_fixup = ip->fixp[0]; | |
4427 | } | |
4428 | else if (reloc_needs_lo_p (*reloc_type)) | |
4429 | { | |
4430 | struct mips_hi_fixup *hi_fixup; | |
4431 | ||
4432 | /* Reuse the last entry if it already has a matching %lo. */ | |
4433 | hi_fixup = mips_hi_fixup_list; | |
4434 | if (hi_fixup == 0 | |
4435 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4436 | { |
9fe77896 RS |
4437 | hi_fixup = ((struct mips_hi_fixup *) |
4438 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4439 | hi_fixup->next = mips_hi_fixup_list; | |
4440 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4441 | } |
9fe77896 RS |
4442 | hi_fixup->fixp = ip->fixp[0]; |
4443 | hi_fixup->seg = now_seg; | |
4444 | } | |
252b5132 | 4445 | |
9fe77896 RS |
4446 | /* Add fixups for the second and third relocations, if given. |
4447 | Note that the ABI allows the second relocation to be | |
4448 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4449 | moment we only use RSS_UNDEF, but we could add support | |
4450 | for the others if it ever becomes necessary. */ | |
4451 | for (i = 1; i < 3; i++) | |
4452 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4453 | { | |
4454 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4455 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4456 | FALSE, final_type[i]); |
f6688943 | 4457 | |
9fe77896 RS |
4458 | /* Use fx_tcbit to mark compound relocs. */ |
4459 | ip->fixp[0]->fx_tcbit = 1; | |
4460 | ip->fixp[i]->fx_tcbit = 1; | |
4461 | } | |
252b5132 | 4462 | } |
1e915849 | 4463 | install_insn (ip); |
252b5132 RH |
4464 | |
4465 | /* Update the register mask information. */ | |
4c260379 RS |
4466 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4467 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4468 | |
a4e06468 | 4469 | switch (method) |
252b5132 | 4470 | { |
a4e06468 RS |
4471 | case APPEND_ADD: |
4472 | insert_into_history (0, 1, ip); | |
4473 | break; | |
4474 | ||
4475 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4476 | { |
4477 | struct mips_cl_insn *nop; | |
4478 | ||
4479 | insert_into_history (0, 1, ip); | |
4480 | nop = get_delay_slot_nop (ip); | |
4481 | add_fixed_insn (nop); | |
4482 | insert_into_history (0, 1, nop); | |
4483 | if (mips_relax.sequence) | |
4484 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4485 | } | |
a4e06468 RS |
4486 | break; |
4487 | ||
4488 | case APPEND_ADD_COMPACT: | |
4489 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4490 | gas_assert (mips_opts.mips16); | |
4491 | ip->insn_opcode |= 0x0080; | |
4492 | find_altered_mips16_opcode (ip); | |
4493 | install_insn (ip); | |
4494 | insert_into_history (0, 1, ip); | |
4495 | break; | |
4496 | ||
4497 | case APPEND_SWAP: | |
4498 | { | |
4499 | struct mips_cl_insn delay = history[0]; | |
4500 | if (mips_opts.mips16) | |
4501 | { | |
4502 | know (delay.frag == ip->frag); | |
4503 | move_insn (ip, delay.frag, delay.where); | |
4504 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4505 | } | |
464ab0e5 | 4506 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4507 | { |
4508 | /* Add the delay slot instruction to the end of the | |
4509 | current frag and shrink the fixed part of the | |
4510 | original frag. If the branch occupies the tail of | |
4511 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4512 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4513 | if (delay.frag == ip->frag) |
2b0c8b40 | 4514 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4515 | add_fixed_insn (&delay); |
4516 | } | |
4517 | else | |
4518 | { | |
2b0c8b40 MR |
4519 | move_insn (&delay, ip->frag, |
4520 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4521 | move_insn (ip, history[0].frag, history[0].where); |
4522 | } | |
4523 | history[0] = *ip; | |
4524 | delay.fixed_p = 1; | |
4525 | insert_into_history (0, 1, &delay); | |
4526 | } | |
4527 | break; | |
252b5132 RH |
4528 | } |
4529 | ||
13408f1e | 4530 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4531 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4532 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4533 | mips_no_prev_insn (); |
4534 | ||
df58fc94 RS |
4535 | /* We need to emit a label at the end of branch-likely macros. */ |
4536 | if (emit_branch_likely_macro) | |
4537 | { | |
4538 | emit_branch_likely_macro = FALSE; | |
4539 | micromips_add_label (); | |
4540 | } | |
4541 | ||
252b5132 RH |
4542 | /* We just output an insn, so the next one doesn't have a label. */ |
4543 | mips_clear_insn_labels (); | |
252b5132 RH |
4544 | } |
4545 | ||
7d10b47d | 4546 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4547 | |
4548 | static void | |
7d10b47d | 4549 | mips_no_prev_insn (void) |
252b5132 | 4550 | { |
7d10b47d RS |
4551 | prev_nop_frag = NULL; |
4552 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4553 | mips_clear_insn_labels (); |
4554 | } | |
4555 | ||
7d10b47d RS |
4556 | /* This function must be called before we emit something other than |
4557 | instructions. It is like mips_no_prev_insn except that it inserts | |
4558 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4559 | |
7d10b47d RS |
4560 | void |
4561 | mips_emit_delays (void) | |
252b5132 RH |
4562 | { |
4563 | if (! mips_opts.noreorder) | |
4564 | { | |
932d1a1b | 4565 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4566 | if (nops > 0) |
4567 | { | |
7d10b47d RS |
4568 | while (nops-- > 0) |
4569 | add_fixed_insn (NOP_INSN); | |
462427c4 | 4570 | mips_move_text_labels (); |
7d10b47d RS |
4571 | } |
4572 | } | |
4573 | mips_no_prev_insn (); | |
4574 | } | |
4575 | ||
4576 | /* Start a (possibly nested) noreorder block. */ | |
4577 | ||
4578 | static void | |
4579 | start_noreorder (void) | |
4580 | { | |
4581 | if (mips_opts.noreorder == 0) | |
4582 | { | |
4583 | unsigned int i; | |
4584 | int nops; | |
4585 | ||
4586 | /* None of the instructions before the .set noreorder can be moved. */ | |
4587 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4588 | history[i].fixed_p = 1; | |
4589 | ||
4590 | /* Insert any nops that might be needed between the .set noreorder | |
4591 | block and the previous instructions. We will later remove any | |
4592 | nops that turn out not to be needed. */ | |
932d1a1b | 4593 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4594 | if (nops > 0) |
4595 | { | |
4596 | if (mips_optimize != 0) | |
252b5132 RH |
4597 | { |
4598 | /* Record the frag which holds the nop instructions, so | |
4599 | that we can remove them if we don't need them. */ | |
df58fc94 | 4600 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4601 | prev_nop_frag = frag_now; |
4602 | prev_nop_frag_holds = nops; | |
4603 | prev_nop_frag_required = 0; | |
4604 | prev_nop_frag_since = 0; | |
4605 | } | |
4606 | ||
4607 | for (; nops > 0; --nops) | |
1e915849 | 4608 | add_fixed_insn (NOP_INSN); |
252b5132 | 4609 | |
7d10b47d RS |
4610 | /* Move on to a new frag, so that it is safe to simply |
4611 | decrease the size of prev_nop_frag. */ | |
4612 | frag_wane (frag_now); | |
4613 | frag_new (0); | |
462427c4 | 4614 | mips_move_text_labels (); |
252b5132 | 4615 | } |
df58fc94 | 4616 | mips_mark_labels (); |
7d10b47d | 4617 | mips_clear_insn_labels (); |
252b5132 | 4618 | } |
7d10b47d RS |
4619 | mips_opts.noreorder++; |
4620 | mips_any_noreorder = 1; | |
4621 | } | |
252b5132 | 4622 | |
7d10b47d | 4623 | /* End a nested noreorder block. */ |
252b5132 | 4624 | |
7d10b47d RS |
4625 | static void |
4626 | end_noreorder (void) | |
4627 | { | |
4628 | mips_opts.noreorder--; | |
4629 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4630 | { | |
4631 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4632 | handling nop insertion the .set reorder way. */ | |
4633 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4634 | * NOP_INSN_SIZE); |
7d10b47d RS |
4635 | insert_into_history (prev_nop_frag_since, |
4636 | prev_nop_frag_required, NOP_INSN); | |
4637 | prev_nop_frag = NULL; | |
4638 | } | |
252b5132 RH |
4639 | } |
4640 | ||
584892a6 RS |
4641 | /* Set up global variables for the start of a new macro. */ |
4642 | ||
4643 | static void | |
4644 | macro_start (void) | |
4645 | { | |
4646 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4647 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4648 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4649 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4650 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4651 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4652 | switch (history[0].insn_mo->pinfo2 |
4653 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4654 | { | |
4655 | case INSN2_BRANCH_DELAY_32BIT: | |
4656 | mips_macro_warning.delay_slot_length = 4; | |
4657 | break; | |
4658 | case INSN2_BRANCH_DELAY_16BIT: | |
4659 | mips_macro_warning.delay_slot_length = 2; | |
4660 | break; | |
4661 | default: | |
4662 | mips_macro_warning.delay_slot_length = 0; | |
4663 | break; | |
4664 | } | |
4665 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4666 | } |
4667 | ||
df58fc94 RS |
4668 | /* Given that a macro is longer than one instruction or of the wrong size, |
4669 | return the appropriate warning for it. Return null if no warning is | |
4670 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4671 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4672 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4673 | |
4674 | static const char * | |
4675 | macro_warning (relax_substateT subtype) | |
4676 | { | |
4677 | if (subtype & RELAX_DELAY_SLOT) | |
4678 | return _("Macro instruction expanded into multiple instructions" | |
4679 | " in a branch delay slot"); | |
4680 | else if (subtype & RELAX_NOMACRO) | |
4681 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4682 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4683 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4684 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4685 | ? _("Macro instruction expanded into a wrong size instruction" | |
4686 | " in a 16-bit branch delay slot") | |
4687 | : _("Macro instruction expanded into a wrong size instruction" | |
4688 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4689 | else |
4690 | return 0; | |
4691 | } | |
4692 | ||
4693 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4694 | ||
4695 | static void | |
4696 | macro_end (void) | |
4697 | { | |
df58fc94 RS |
4698 | /* Relaxation warning flags. */ |
4699 | relax_substateT subtype = 0; | |
4700 | ||
4701 | /* Check delay slot size requirements. */ | |
4702 | if (mips_macro_warning.delay_slot_length == 2) | |
4703 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4704 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4705 | { |
df58fc94 RS |
4706 | if (mips_macro_warning.delay_slot_length |
4707 | != mips_macro_warning.first_insn_sizes[0]) | |
4708 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4709 | if (mips_macro_warning.delay_slot_length | |
4710 | != mips_macro_warning.first_insn_sizes[1]) | |
4711 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4712 | } | |
584892a6 | 4713 | |
df58fc94 RS |
4714 | /* Check instruction count requirements. */ |
4715 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4716 | { | |
4717 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4718 | subtype |= RELAX_SECOND_LONGER; |
4719 | if (mips_opts.warn_about_macros) | |
4720 | subtype |= RELAX_NOMACRO; | |
4721 | if (mips_macro_warning.delay_slot_p) | |
4722 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4723 | } |
584892a6 | 4724 | |
df58fc94 RS |
4725 | /* If both alternatives fail to fill a delay slot correctly, |
4726 | emit the warning now. */ | |
4727 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4728 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4729 | { | |
4730 | relax_substateT s; | |
4731 | const char *msg; | |
4732 | ||
4733 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4734 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4735 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4736 | msg = macro_warning (s); | |
4737 | if (msg != NULL) | |
4738 | as_warn ("%s", msg); | |
4739 | subtype &= ~s; | |
4740 | } | |
4741 | ||
4742 | /* If both implementations are longer than 1 instruction, then emit the | |
4743 | warning now. */ | |
4744 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4745 | { | |
4746 | relax_substateT s; | |
4747 | const char *msg; | |
4748 | ||
4749 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4750 | msg = macro_warning (s); | |
4751 | if (msg != NULL) | |
4752 | as_warn ("%s", msg); | |
4753 | subtype &= ~s; | |
584892a6 | 4754 | } |
df58fc94 RS |
4755 | |
4756 | /* If any flags still set, then one implementation might need a warning | |
4757 | and the other either will need one of a different kind or none at all. | |
4758 | Pass any remaining flags over to relaxation. */ | |
4759 | if (mips_macro_warning.first_frag != NULL) | |
4760 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4761 | } |
4762 | ||
df58fc94 RS |
4763 | /* Instruction operand formats used in macros that vary between |
4764 | standard MIPS and microMIPS code. */ | |
4765 | ||
4766 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4767 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4768 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4769 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4770 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4771 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4772 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4773 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4774 | ||
4775 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4776 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4777 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4778 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4779 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4780 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4781 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4782 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4783 | ||
6e1304d8 RS |
4784 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4785 | The first argument in *ARGS will be either the code for a single | |
4786 | relocation or -1 followed by the three codes that make up a | |
4787 | composite relocation. */ | |
4788 | ||
4789 | static void | |
4790 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4791 | { | |
4792 | int i, next; | |
4793 | ||
4794 | next = va_arg (*args, int); | |
4795 | if (next >= 0) | |
4796 | r[0] = (bfd_reloc_code_real_type) next; | |
4797 | else | |
4798 | for (i = 0; i < 3; i++) | |
4799 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4800 | } | |
4801 | ||
252b5132 RH |
4802 | /* Build an instruction created by a macro expansion. This is passed |
4803 | a pointer to the count of instructions created so far, an | |
4804 | expression, the name of the instruction to build, an operand format | |
4805 | string, and corresponding arguments. */ | |
4806 | ||
252b5132 | 4807 | static void |
67c0d1eb | 4808 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4809 | { |
df58fc94 | 4810 | const struct mips_opcode *mo = NULL; |
f6688943 | 4811 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4812 | const struct mips_opcode *amo; |
4813 | struct hash_control *hash; | |
4814 | struct mips_cl_insn insn; | |
252b5132 | 4815 | va_list args; |
252b5132 | 4816 | |
252b5132 | 4817 | va_start (args, fmt); |
252b5132 | 4818 | |
252b5132 RH |
4819 | if (mips_opts.mips16) |
4820 | { | |
03ea81db | 4821 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4822 | va_end (args); |
4823 | return; | |
4824 | } | |
4825 | ||
f6688943 TS |
4826 | r[0] = BFD_RELOC_UNUSED; |
4827 | r[1] = BFD_RELOC_UNUSED; | |
4828 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4829 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4830 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4831 | gas_assert (amo); | |
4832 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4833 | |
df58fc94 | 4834 | do |
8b082fb1 TS |
4835 | { |
4836 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4837 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4838 | We try to match an instruction that fulfils the branch delay | |
4839 | slot instruction length requirement (if any) of the previous | |
4840 | instruction. While doing this we record the first instruction | |
4841 | seen that matches all the other conditions and use it anyway | |
4842 | if the requirement cannot be met; we will issue an appropriate | |
4843 | warning later on. */ | |
4844 | if (strcmp (fmt, amo->args) == 0 | |
4845 | && amo->pinfo != INSN_MACRO | |
4846 | && is_opcode_valid (amo) | |
4847 | && is_size_valid (amo)) | |
4848 | { | |
4849 | if (is_delay_slot_valid (amo)) | |
4850 | { | |
4851 | mo = amo; | |
4852 | break; | |
4853 | } | |
4854 | else if (!mo) | |
4855 | mo = amo; | |
4856 | } | |
8b082fb1 | 4857 | |
df58fc94 RS |
4858 | ++amo; |
4859 | gas_assert (amo->name); | |
252b5132 | 4860 | } |
df58fc94 | 4861 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4862 | |
df58fc94 | 4863 | gas_assert (mo); |
1e915849 | 4864 | create_insn (&insn, mo); |
252b5132 RH |
4865 | for (;;) |
4866 | { | |
4867 | switch (*fmt++) | |
4868 | { | |
4869 | case '\0': | |
4870 | break; | |
4871 | ||
4872 | case ',': | |
4873 | case '(': | |
4874 | case ')': | |
4875 | continue; | |
4876 | ||
5f74bc13 CD |
4877 | case '+': |
4878 | switch (*fmt++) | |
4879 | { | |
4880 | case 'A': | |
4881 | case 'E': | |
df58fc94 RS |
4882 | INSERT_OPERAND (mips_opts.micromips, |
4883 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4884 | continue; |
4885 | ||
4886 | case 'B': | |
4887 | case 'F': | |
4888 | /* Note that in the macro case, these arguments are already | |
4889 | in MSB form. (When handling the instruction in the | |
4890 | non-macro case, these arguments are sizes from which | |
4891 | MSB values must be calculated.) */ | |
df58fc94 RS |
4892 | INSERT_OPERAND (mips_opts.micromips, |
4893 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4894 | continue; |
4895 | ||
4896 | case 'C': | |
4897 | case 'G': | |
4898 | case 'H': | |
4899 | /* Note that in the macro case, these arguments are already | |
4900 | in MSBD form. (When handling the instruction in the | |
4901 | non-macro case, these arguments are sizes from which | |
4902 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4903 | INSERT_OPERAND (mips_opts.micromips, |
4904 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4905 | continue; |
4906 | ||
dd3cbb7e | 4907 | case 'Q': |
df58fc94 RS |
4908 | gas_assert (!mips_opts.micromips); |
4909 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4910 | continue; |
4911 | ||
5f74bc13 CD |
4912 | default: |
4913 | internalError (); | |
4914 | } | |
4915 | continue; | |
4916 | ||
8b082fb1 | 4917 | case '2': |
03f66e8a | 4918 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
4919 | continue; |
4920 | ||
df58fc94 RS |
4921 | case 'n': |
4922 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4923 | case 't': |
4924 | case 'w': | |
4925 | case 'E': | |
df58fc94 | 4926 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4927 | continue; |
4928 | ||
4929 | case 'c': | |
df58fc94 RS |
4930 | gas_assert (!mips_opts.micromips); |
4931 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4932 | continue; |
4933 | ||
252b5132 | 4934 | case 'W': |
df58fc94 RS |
4935 | gas_assert (!mips_opts.micromips); |
4936 | case 'T': | |
4937 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4938 | continue; |
4939 | ||
252b5132 | 4940 | case 'G': |
df58fc94 RS |
4941 | if (mips_opts.micromips) |
4942 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4943 | else | |
4944 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4945 | continue; | |
4946 | ||
af7ee8bf | 4947 | case 'K': |
df58fc94 RS |
4948 | gas_assert (!mips_opts.micromips); |
4949 | case 'd': | |
4950 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4951 | continue; |
4952 | ||
4372b673 | 4953 | case 'U': |
df58fc94 | 4954 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4955 | { |
4956 | int tmp = va_arg (args, int); | |
4957 | ||
df58fc94 RS |
4958 | INSERT_OPERAND (0, RT, insn, tmp); |
4959 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4960 | } |
df58fc94 | 4961 | continue; |
4372b673 | 4962 | |
252b5132 RH |
4963 | case 'V': |
4964 | case 'S': | |
df58fc94 RS |
4965 | gas_assert (!mips_opts.micromips); |
4966 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4967 | continue; |
4968 | ||
4969 | case 'z': | |
4970 | continue; | |
4971 | ||
4972 | case '<': | |
df58fc94 RS |
4973 | INSERT_OPERAND (mips_opts.micromips, |
4974 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4975 | continue; |
4976 | ||
4977 | case 'D': | |
df58fc94 RS |
4978 | gas_assert (!mips_opts.micromips); |
4979 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4980 | continue; |
4981 | ||
4982 | case 'B': | |
df58fc94 RS |
4983 | gas_assert (!mips_opts.micromips); |
4984 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4985 | continue; |
4986 | ||
4372b673 | 4987 | case 'J': |
df58fc94 RS |
4988 | gas_assert (!mips_opts.micromips); |
4989 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4990 | continue; |
4991 | ||
252b5132 | 4992 | case 'q': |
df58fc94 RS |
4993 | gas_assert (!mips_opts.micromips); |
4994 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4995 | continue; |
4996 | ||
4997 | case 'b': | |
4998 | case 's': | |
4999 | case 'r': | |
5000 | case 'v': | |
df58fc94 | 5001 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5002 | continue; |
5003 | ||
5004 | case 'i': | |
5005 | case 'j': | |
6e1304d8 | 5006 | macro_read_relocs (&args, r); |
9c2799c2 | 5007 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5008 | || *r == BFD_RELOC_MIPS_HIGHER |
5009 | || *r == BFD_RELOC_HI16_S | |
5010 | || *r == BFD_RELOC_LO16 | |
5011 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5012 | continue; | |
5013 | ||
5014 | case 'o': | |
5015 | macro_read_relocs (&args, r); | |
252b5132 RH |
5016 | continue; |
5017 | ||
5018 | case 'u': | |
6e1304d8 | 5019 | macro_read_relocs (&args, r); |
9c2799c2 | 5020 | gas_assert (ep != NULL |
90ecf173 MR |
5021 | && (ep->X_op == O_constant |
5022 | || (ep->X_op == O_symbol | |
5023 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5024 | || *r == BFD_RELOC_HI16_S | |
5025 | || *r == BFD_RELOC_HI16 | |
5026 | || *r == BFD_RELOC_GPREL16 | |
5027 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5028 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5029 | continue; |
5030 | ||
5031 | case 'p': | |
9c2799c2 | 5032 | gas_assert (ep != NULL); |
bad36eac | 5033 | |
252b5132 RH |
5034 | /* |
5035 | * This allows macro() to pass an immediate expression for | |
5036 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5037 | * |
5038 | * We don't allow branch relaxation for these branches, as | |
5039 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5040 | */ |
5041 | if (ep->X_op == O_constant) | |
5042 | { | |
df58fc94 RS |
5043 | /* For microMIPS we always use relocations for branches. |
5044 | So we should not resolve immediate values. */ | |
5045 | gas_assert (!mips_opts.micromips); | |
5046 | ||
bad36eac DJ |
5047 | if ((ep->X_add_number & 3) != 0) |
5048 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5049 | (unsigned long) ep->X_add_number); | |
5050 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5051 | as_bad (_("branch address range overflow (0x%lx)"), | |
5052 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5053 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5054 | ep = NULL; | |
5055 | } | |
5056 | else | |
0b25d3e6 | 5057 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5058 | continue; |
5059 | ||
5060 | case 'a': | |
9c2799c2 | 5061 | gas_assert (ep != NULL); |
f6688943 | 5062 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5063 | continue; |
5064 | ||
5065 | case 'C': | |
df58fc94 RS |
5066 | gas_assert (!mips_opts.micromips); |
5067 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5068 | continue; |
5069 | ||
d43b4baf | 5070 | case 'k': |
df58fc94 RS |
5071 | INSERT_OPERAND (mips_opts.micromips, |
5072 | CACHE, insn, va_arg (args, unsigned long)); | |
5073 | continue; | |
5074 | ||
5075 | case '|': | |
5076 | gas_assert (mips_opts.micromips); | |
5077 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5078 | continue; | |
5079 | ||
5080 | case '.': | |
5081 | gas_assert (mips_opts.micromips); | |
5082 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5083 | continue; | |
5084 | ||
dec0624d MR |
5085 | case '\\': |
5086 | INSERT_OPERAND (mips_opts.micromips, | |
5087 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5088 | continue; | |
5089 | ||
df58fc94 | 5090 | case '~': |
dec0624d MR |
5091 | INSERT_OPERAND (mips_opts.micromips, |
5092 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5093 | continue; |
5094 | ||
5095 | case 'N': | |
5096 | gas_assert (mips_opts.micromips); | |
5097 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5098 | continue; | |
5099 | ||
5100 | case 'm': /* Opcode extension character. */ | |
5101 | gas_assert (mips_opts.micromips); | |
5102 | switch (*fmt++) | |
5103 | { | |
5104 | case 'j': | |
5105 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5106 | break; | |
5107 | ||
5108 | case 'p': | |
5109 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5110 | break; | |
5111 | ||
5112 | case 'F': | |
5113 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5114 | break; | |
5115 | ||
5116 | default: | |
5117 | internalError (); | |
5118 | } | |
d43b4baf TS |
5119 | continue; |
5120 | ||
252b5132 RH |
5121 | default: |
5122 | internalError (); | |
5123 | } | |
5124 | break; | |
5125 | } | |
5126 | va_end (args); | |
9c2799c2 | 5127 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5128 | |
df58fc94 | 5129 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5130 | } |
5131 | ||
5132 | static void | |
67c0d1eb | 5133 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5134 | va_list *args) |
252b5132 | 5135 | { |
1e915849 | 5136 | struct mips_opcode *mo; |
252b5132 | 5137 | struct mips_cl_insn insn; |
f6688943 TS |
5138 | bfd_reloc_code_real_type r[3] |
5139 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5140 | |
1e915849 | 5141 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5142 | gas_assert (mo); |
5143 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5144 | |
1e915849 | 5145 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5146 | { |
1e915849 | 5147 | ++mo; |
9c2799c2 NC |
5148 | gas_assert (mo->name); |
5149 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5150 | } |
5151 | ||
1e915849 | 5152 | create_insn (&insn, mo); |
252b5132 RH |
5153 | for (;;) |
5154 | { | |
5155 | int c; | |
5156 | ||
5157 | c = *fmt++; | |
5158 | switch (c) | |
5159 | { | |
5160 | case '\0': | |
5161 | break; | |
5162 | ||
5163 | case ',': | |
5164 | case '(': | |
5165 | case ')': | |
5166 | continue; | |
5167 | ||
5168 | case 'y': | |
5169 | case 'w': | |
03ea81db | 5170 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5171 | continue; |
5172 | ||
5173 | case 'x': | |
5174 | case 'v': | |
03ea81db | 5175 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5176 | continue; |
5177 | ||
5178 | case 'z': | |
03ea81db | 5179 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5180 | continue; |
5181 | ||
5182 | case 'Z': | |
03ea81db | 5183 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5184 | continue; |
5185 | ||
5186 | case '0': | |
5187 | case 'S': | |
5188 | case 'P': | |
5189 | case 'R': | |
5190 | continue; | |
5191 | ||
5192 | case 'X': | |
03ea81db | 5193 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5194 | continue; |
5195 | ||
5196 | case 'Y': | |
5197 | { | |
5198 | int regno; | |
5199 | ||
03ea81db | 5200 | regno = va_arg (*args, int); |
252b5132 | 5201 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5202 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5203 | } |
5204 | continue; | |
5205 | ||
5206 | case '<': | |
5207 | case '>': | |
5208 | case '4': | |
5209 | case '5': | |
5210 | case 'H': | |
5211 | case 'W': | |
5212 | case 'D': | |
5213 | case 'j': | |
5214 | case '8': | |
5215 | case 'V': | |
5216 | case 'C': | |
5217 | case 'U': | |
5218 | case 'k': | |
5219 | case 'K': | |
5220 | case 'p': | |
5221 | case 'q': | |
5222 | { | |
9c2799c2 | 5223 | gas_assert (ep != NULL); |
252b5132 RH |
5224 | |
5225 | if (ep->X_op != O_constant) | |
874e8986 | 5226 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5227 | else |
5228 | { | |
43c0598f | 5229 | mips16_immed (NULL, 0, c, *r, ep->X_add_number, |
5c04167a | 5230 | 0, &insn.insn_opcode); |
252b5132 | 5231 | ep = NULL; |
f6688943 | 5232 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5233 | } |
5234 | } | |
5235 | continue; | |
5236 | ||
5237 | case '6': | |
03ea81db | 5238 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5239 | continue; |
5240 | } | |
5241 | ||
5242 | break; | |
5243 | } | |
5244 | ||
9c2799c2 | 5245 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5246 | |
df58fc94 | 5247 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5248 | } |
5249 | ||
2051e8c4 MR |
5250 | /* |
5251 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5252 | * higher bits unset. | |
5253 | */ | |
9f872bbe | 5254 | static void |
2051e8c4 MR |
5255 | normalize_constant_expr (expressionS *ex) |
5256 | { | |
9ee2a2d4 | 5257 | if (ex->X_op == O_constant |
2051e8c4 MR |
5258 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5259 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5260 | - 0x80000000); | |
5261 | } | |
5262 | ||
5263 | /* | |
5264 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5265 | * all higher bits unset. | |
5266 | */ | |
5267 | static void | |
5268 | normalize_address_expr (expressionS *ex) | |
5269 | { | |
5270 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5271 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5272 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5273 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5274 | - 0x80000000); | |
5275 | } | |
5276 | ||
438c16b8 TS |
5277 | /* |
5278 | * Generate a "jalr" instruction with a relocation hint to the called | |
5279 | * function. This occurs in NewABI PIC code. | |
5280 | */ | |
5281 | static void | |
df58fc94 | 5282 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5283 | { |
df58fc94 RS |
5284 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5285 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5286 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5287 | const char *jalr; | |
685736be | 5288 | char *f = NULL; |
b34976b6 | 5289 | |
1180b5a4 | 5290 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5291 | { |
cc3d92a5 | 5292 | frag_grow (8); |
f21f8242 AO |
5293 | f = frag_more (0); |
5294 | } | |
2906b037 | 5295 | if (mips_opts.micromips) |
df58fc94 RS |
5296 | { |
5297 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5298 | if (MIPS_JALR_HINT_P (ep)) | |
5299 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5300 | else | |
5301 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5302 | } | |
2906b037 MR |
5303 | else |
5304 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5305 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5306 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5307 | } |
5308 | ||
252b5132 RH |
5309 | /* |
5310 | * Generate a "lui" instruction. | |
5311 | */ | |
5312 | static void | |
67c0d1eb | 5313 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5314 | { |
9c2799c2 | 5315 | gas_assert (! mips_opts.mips16); |
252b5132 | 5316 | |
df58fc94 | 5317 | if (ep->X_op != O_constant) |
252b5132 | 5318 | { |
9c2799c2 | 5319 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5320 | /* _gp_disp is a special case, used from s_cpload. |
5321 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5322 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5323 | || (! HAVE_NEWABI |
aa6975fb ILT |
5324 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5325 | || (! mips_in_shared | |
bbe506e8 TS |
5326 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5327 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5328 | } |
5329 | ||
df58fc94 | 5330 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5331 | } |
5332 | ||
885add95 CD |
5333 | /* Generate a sequence of instructions to do a load or store from a constant |
5334 | offset off of a base register (breg) into/from a target register (treg), | |
5335 | using AT if necessary. */ | |
5336 | static void | |
67c0d1eb RS |
5337 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5338 | int treg, int breg, int dbl) | |
885add95 | 5339 | { |
9c2799c2 | 5340 | gas_assert (ep->X_op == O_constant); |
885add95 | 5341 | |
256ab948 | 5342 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5343 | if (!dbl) |
5344 | normalize_constant_expr (ep); | |
256ab948 | 5345 | |
67c1ffbe | 5346 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5347 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5348 | as_warn (_("operand overflow")); |
5349 | ||
5350 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5351 | { | |
5352 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5353 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5354 | } |
5355 | else | |
5356 | { | |
5357 | /* 32-bit offset, need multiple instructions and AT, like: | |
5358 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5359 | addu $tempreg,$tempreg,$breg | |
5360 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5361 | to handle the complete offset. */ | |
67c0d1eb RS |
5362 | macro_build_lui (ep, AT); |
5363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5364 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5365 | |
741fe287 | 5366 | if (!mips_opts.at) |
8fc2e39e | 5367 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5368 | } |
5369 | } | |
5370 | ||
252b5132 RH |
5371 | /* set_at() |
5372 | * Generates code to set the $at register to true (one) | |
5373 | * if reg is less than the immediate expression. | |
5374 | */ | |
5375 | static void | |
67c0d1eb | 5376 | set_at (int reg, int unsignedp) |
252b5132 RH |
5377 | { |
5378 | if (imm_expr.X_op == O_constant | |
5379 | && imm_expr.X_add_number >= -0x8000 | |
5380 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5381 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5382 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5383 | else |
5384 | { | |
67c0d1eb RS |
5385 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5386 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5387 | } |
5388 | } | |
5389 | ||
5390 | /* Warn if an expression is not a constant. */ | |
5391 | ||
5392 | static void | |
17a2f251 | 5393 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5394 | { |
5395 | if (ex->X_op == O_big) | |
5396 | as_bad (_("unsupported large constant")); | |
5397 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5398 | as_bad (_("Instruction %s requires absolute expression"), |
5399 | ip->insn_mo->name); | |
13757d0c | 5400 | |
9ee2a2d4 MR |
5401 | if (HAVE_32BIT_GPRS) |
5402 | normalize_constant_expr (ex); | |
252b5132 RH |
5403 | } |
5404 | ||
5405 | /* Count the leading zeroes by performing a binary chop. This is a | |
5406 | bulky bit of source, but performance is a LOT better for the | |
5407 | majority of values than a simple loop to count the bits: | |
5408 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5409 | if ((v) & (1 << (31 - lcnt))) | |
5410 | break; | |
5411 | However it is not code size friendly, and the gain will drop a bit | |
5412 | on certain cached systems. | |
5413 | */ | |
5414 | #define COUNT_TOP_ZEROES(v) \ | |
5415 | (((v) & ~0xffff) == 0 \ | |
5416 | ? ((v) & ~0xff) == 0 \ | |
5417 | ? ((v) & ~0xf) == 0 \ | |
5418 | ? ((v) & ~0x3) == 0 \ | |
5419 | ? ((v) & ~0x1) == 0 \ | |
5420 | ? !(v) \ | |
5421 | ? 32 \ | |
5422 | : 31 \ | |
5423 | : 30 \ | |
5424 | : ((v) & ~0x7) == 0 \ | |
5425 | ? 29 \ | |
5426 | : 28 \ | |
5427 | : ((v) & ~0x3f) == 0 \ | |
5428 | ? ((v) & ~0x1f) == 0 \ | |
5429 | ? 27 \ | |
5430 | : 26 \ | |
5431 | : ((v) & ~0x7f) == 0 \ | |
5432 | ? 25 \ | |
5433 | : 24 \ | |
5434 | : ((v) & ~0xfff) == 0 \ | |
5435 | ? ((v) & ~0x3ff) == 0 \ | |
5436 | ? ((v) & ~0x1ff) == 0 \ | |
5437 | ? 23 \ | |
5438 | : 22 \ | |
5439 | : ((v) & ~0x7ff) == 0 \ | |
5440 | ? 21 \ | |
5441 | : 20 \ | |
5442 | : ((v) & ~0x3fff) == 0 \ | |
5443 | ? ((v) & ~0x1fff) == 0 \ | |
5444 | ? 19 \ | |
5445 | : 18 \ | |
5446 | : ((v) & ~0x7fff) == 0 \ | |
5447 | ? 17 \ | |
5448 | : 16 \ | |
5449 | : ((v) & ~0xffffff) == 0 \ | |
5450 | ? ((v) & ~0xfffff) == 0 \ | |
5451 | ? ((v) & ~0x3ffff) == 0 \ | |
5452 | ? ((v) & ~0x1ffff) == 0 \ | |
5453 | ? 15 \ | |
5454 | : 14 \ | |
5455 | : ((v) & ~0x7ffff) == 0 \ | |
5456 | ? 13 \ | |
5457 | : 12 \ | |
5458 | : ((v) & ~0x3fffff) == 0 \ | |
5459 | ? ((v) & ~0x1fffff) == 0 \ | |
5460 | ? 11 \ | |
5461 | : 10 \ | |
5462 | : ((v) & ~0x7fffff) == 0 \ | |
5463 | ? 9 \ | |
5464 | : 8 \ | |
5465 | : ((v) & ~0xfffffff) == 0 \ | |
5466 | ? ((v) & ~0x3ffffff) == 0 \ | |
5467 | ? ((v) & ~0x1ffffff) == 0 \ | |
5468 | ? 7 \ | |
5469 | : 6 \ | |
5470 | : ((v) & ~0x7ffffff) == 0 \ | |
5471 | ? 5 \ | |
5472 | : 4 \ | |
5473 | : ((v) & ~0x3fffffff) == 0 \ | |
5474 | ? ((v) & ~0x1fffffff) == 0 \ | |
5475 | ? 3 \ | |
5476 | : 2 \ | |
5477 | : ((v) & ~0x7fffffff) == 0 \ | |
5478 | ? 1 \ | |
5479 | : 0) | |
5480 | ||
5481 | /* load_register() | |
67c1ffbe | 5482 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5483 | * an absolute expression value into a register. |
5484 | */ | |
5485 | static void | |
67c0d1eb | 5486 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5487 | { |
5488 | int freg; | |
5489 | expressionS hi32, lo32; | |
5490 | ||
5491 | if (ep->X_op != O_big) | |
5492 | { | |
9c2799c2 | 5493 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5494 | |
5495 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5496 | if (!dbl) |
5497 | normalize_constant_expr (ep); | |
256ab948 TS |
5498 | |
5499 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5500 | { |
5501 | /* We can handle 16 bit signed values with an addiu to | |
5502 | $zero. No need to ever use daddiu here, since $zero and | |
5503 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5504 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5505 | return; |
5506 | } | |
5507 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5508 | { | |
5509 | /* We can handle 16 bit unsigned values with an ori to | |
5510 | $zero. */ | |
67c0d1eb | 5511 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5512 | return; |
5513 | } | |
256ab948 | 5514 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5515 | { |
5516 | /* 32 bit values require an lui. */ | |
df58fc94 | 5517 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5518 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5519 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5520 | return; |
5521 | } | |
5522 | } | |
5523 | ||
5524 | /* The value is larger than 32 bits. */ | |
5525 | ||
2051e8c4 | 5526 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5527 | { |
55e08f71 NC |
5528 | char value[32]; |
5529 | ||
5530 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5531 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5532 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5533 | return; |
5534 | } | |
5535 | ||
5536 | if (ep->X_op != O_big) | |
5537 | { | |
5538 | hi32 = *ep; | |
5539 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5540 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5541 | hi32.X_add_number &= 0xffffffff; | |
5542 | lo32 = *ep; | |
5543 | lo32.X_add_number &= 0xffffffff; | |
5544 | } | |
5545 | else | |
5546 | { | |
9c2799c2 | 5547 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5548 | if (ep->X_add_number == 3) |
5549 | generic_bignum[3] = 0; | |
5550 | else if (ep->X_add_number > 4) | |
5551 | as_bad (_("Number larger than 64 bits")); | |
5552 | lo32.X_op = O_constant; | |
5553 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5554 | hi32.X_op = O_constant; | |
5555 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5556 | } | |
5557 | ||
5558 | if (hi32.X_add_number == 0) | |
5559 | freg = 0; | |
5560 | else | |
5561 | { | |
5562 | int shift, bit; | |
5563 | unsigned long hi, lo; | |
5564 | ||
956cd1d6 | 5565 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5566 | { |
5567 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5568 | { | |
67c0d1eb | 5569 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5570 | return; |
5571 | } | |
5572 | if (lo32.X_add_number & 0x80000000) | |
5573 | { | |
df58fc94 | 5574 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5575 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5576 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5577 | return; |
5578 | } | |
5579 | } | |
252b5132 RH |
5580 | |
5581 | /* Check for 16bit shifted constant. We know that hi32 is | |
5582 | non-zero, so start the mask on the first bit of the hi32 | |
5583 | value. */ | |
5584 | shift = 17; | |
5585 | do | |
beae10d5 KH |
5586 | { |
5587 | unsigned long himask, lomask; | |
5588 | ||
5589 | if (shift < 32) | |
5590 | { | |
5591 | himask = 0xffff >> (32 - shift); | |
5592 | lomask = (0xffff << shift) & 0xffffffff; | |
5593 | } | |
5594 | else | |
5595 | { | |
5596 | himask = 0xffff << (shift - 32); | |
5597 | lomask = 0; | |
5598 | } | |
5599 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5600 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5601 | { | |
5602 | expressionS tmp; | |
5603 | ||
5604 | tmp.X_op = O_constant; | |
5605 | if (shift < 32) | |
5606 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5607 | | (lo32.X_add_number >> shift)); | |
5608 | else | |
5609 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5610 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5611 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5612 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5613 | return; |
5614 | } | |
f9419b05 | 5615 | ++shift; |
beae10d5 KH |
5616 | } |
5617 | while (shift <= (64 - 16)); | |
252b5132 RH |
5618 | |
5619 | /* Find the bit number of the lowest one bit, and store the | |
5620 | shifted value in hi/lo. */ | |
5621 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5622 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5623 | if (lo != 0) | |
5624 | { | |
5625 | bit = 0; | |
5626 | while ((lo & 1) == 0) | |
5627 | { | |
5628 | lo >>= 1; | |
5629 | ++bit; | |
5630 | } | |
5631 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5632 | hi >>= bit; | |
5633 | } | |
5634 | else | |
5635 | { | |
5636 | bit = 32; | |
5637 | while ((hi & 1) == 0) | |
5638 | { | |
5639 | hi >>= 1; | |
5640 | ++bit; | |
5641 | } | |
5642 | lo = hi; | |
5643 | hi = 0; | |
5644 | } | |
5645 | ||
5646 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5647 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5648 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5649 | { |
5650 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5651 | if (shift != 0) |
beae10d5 | 5652 | { |
252b5132 RH |
5653 | expressionS tmp; |
5654 | ||
5655 | /* This instruction will set the register to be all | |
5656 | ones. */ | |
beae10d5 KH |
5657 | tmp.X_op = O_constant; |
5658 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5659 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5660 | if (bit != 0) |
5661 | { | |
5662 | bit += shift; | |
df58fc94 | 5663 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5664 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5665 | } |
df58fc94 | 5666 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5667 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5668 | return; |
5669 | } | |
5670 | } | |
252b5132 RH |
5671 | |
5672 | /* Sign extend hi32 before calling load_register, because we can | |
5673 | generally get better code when we load a sign extended value. */ | |
5674 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5675 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5676 | load_register (reg, &hi32, 0); |
252b5132 RH |
5677 | freg = reg; |
5678 | } | |
5679 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5680 | { | |
5681 | if (freg != 0) | |
5682 | { | |
df58fc94 | 5683 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5684 | freg = reg; |
5685 | } | |
5686 | } | |
5687 | else | |
5688 | { | |
5689 | expressionS mid16; | |
5690 | ||
956cd1d6 | 5691 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5692 | { |
df58fc94 RS |
5693 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5694 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5695 | return; |
5696 | } | |
252b5132 RH |
5697 | |
5698 | if (freg != 0) | |
5699 | { | |
df58fc94 | 5700 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5701 | freg = reg; |
5702 | } | |
5703 | mid16 = lo32; | |
5704 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5705 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5706 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5707 | freg = reg; |
5708 | } | |
5709 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5710 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5711 | } |
5712 | ||
269137b2 TS |
5713 | static inline void |
5714 | load_delay_nop (void) | |
5715 | { | |
5716 | if (!gpr_interlocks) | |
5717 | macro_build (NULL, "nop", ""); | |
5718 | } | |
5719 | ||
252b5132 RH |
5720 | /* Load an address into a register. */ |
5721 | ||
5722 | static void | |
67c0d1eb | 5723 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5724 | { |
252b5132 RH |
5725 | if (ep->X_op != O_constant |
5726 | && ep->X_op != O_symbol) | |
5727 | { | |
5728 | as_bad (_("expression too complex")); | |
5729 | ep->X_op = O_constant; | |
5730 | } | |
5731 | ||
5732 | if (ep->X_op == O_constant) | |
5733 | { | |
67c0d1eb | 5734 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5735 | return; |
5736 | } | |
5737 | ||
5738 | if (mips_pic == NO_PIC) | |
5739 | { | |
5740 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5741 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5742 | Otherwise we want |
5743 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5744 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5745 | If we have an addend, we always use the latter form. |
76b3015f | 5746 | |
d6bc6245 TS |
5747 | With 64bit address space and a usable $at we want |
5748 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5749 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5750 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5751 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5752 | dsll32 $reg,0 | |
3a482fd5 | 5753 | daddu $reg,$reg,$at |
76b3015f | 5754 | |
c03099e6 | 5755 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5756 | on superscalar processors. |
5757 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5758 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5759 | dsll $reg,16 | |
5760 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5761 | dsll $reg,16 | |
5762 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5763 | |
5764 | For GP relative symbols in 64bit address space we can use | |
5765 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5766 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5767 | { |
6caf9ef4 TS |
5768 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5769 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5770 | { | |
5771 | relax_start (ep->X_add_symbol); | |
5772 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5773 | mips_gp_register, BFD_RELOC_GPREL16); | |
5774 | relax_switch (); | |
5775 | } | |
d6bc6245 | 5776 | |
741fe287 | 5777 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5778 | { |
df58fc94 RS |
5779 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5780 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5781 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5782 | BFD_RELOC_MIPS_HIGHER); | |
5783 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5784 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5785 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5786 | *used_at = 1; |
5787 | } | |
5788 | else | |
5789 | { | |
df58fc94 | 5790 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5791 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5792 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5793 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5794 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5795 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5796 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5797 | } |
6caf9ef4 TS |
5798 | |
5799 | if (mips_relax.sequence) | |
5800 | relax_end (); | |
d6bc6245 | 5801 | } |
252b5132 RH |
5802 | else |
5803 | { | |
d6bc6245 | 5804 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5805 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5806 | { |
4d7206a2 | 5807 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5808 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5809 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5810 | relax_switch (); |
d6bc6245 | 5811 | } |
67c0d1eb RS |
5812 | macro_build_lui (ep, reg); |
5813 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5814 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5815 | if (mips_relax.sequence) |
5816 | relax_end (); | |
d6bc6245 | 5817 | } |
252b5132 | 5818 | } |
0a44bf69 | 5819 | else if (!mips_big_got) |
252b5132 RH |
5820 | { |
5821 | expressionS ex; | |
5822 | ||
5823 | /* If this is a reference to an external symbol, we want | |
5824 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5825 | Otherwise we want | |
5826 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5827 | nop | |
5828 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5829 | If there is a constant, it must be added in after. |
5830 | ||
ed6fb7bd | 5831 | If we have NewABI, we want |
f5040a92 AO |
5832 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5833 | unless we're referencing a global symbol with a non-zero | |
5834 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5835 | if (HAVE_NEWABI) |
5836 | { | |
f5040a92 AO |
5837 | if (ep->X_add_number) |
5838 | { | |
4d7206a2 | 5839 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5840 | ep->X_add_number = 0; |
4d7206a2 | 5841 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5842 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5843 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5844 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5845 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5846 | ex.X_op = O_constant; | |
67c0d1eb | 5847 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5848 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5849 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5850 | relax_switch (); |
f5040a92 | 5851 | } |
67c0d1eb | 5852 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5853 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5854 | if (mips_relax.sequence) |
5855 | relax_end (); | |
ed6fb7bd SC |
5856 | } |
5857 | else | |
5858 | { | |
f5040a92 AO |
5859 | ex.X_add_number = ep->X_add_number; |
5860 | ep->X_add_number = 0; | |
67c0d1eb RS |
5861 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5862 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5863 | load_delay_nop (); |
4d7206a2 RS |
5864 | relax_start (ep->X_add_symbol); |
5865 | relax_switch (); | |
67c0d1eb | 5866 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5867 | BFD_RELOC_LO16); |
4d7206a2 | 5868 | relax_end (); |
ed6fb7bd | 5869 | |
f5040a92 AO |
5870 | if (ex.X_add_number != 0) |
5871 | { | |
5872 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5873 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5874 | ex.X_op = O_constant; | |
67c0d1eb | 5875 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5876 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5877 | } |
252b5132 RH |
5878 | } |
5879 | } | |
0a44bf69 | 5880 | else if (mips_big_got) |
252b5132 RH |
5881 | { |
5882 | expressionS ex; | |
252b5132 RH |
5883 | |
5884 | /* This is the large GOT case. If this is a reference to an | |
5885 | external symbol, we want | |
5886 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5887 | addu $reg,$reg,$gp | |
5888 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5889 | |
5890 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5891 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5892 | nop | |
5893 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5894 | If there is a constant, it must be added in after. |
f5040a92 AO |
5895 | |
5896 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5897 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5898 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5899 | */ |
438c16b8 TS |
5900 | if (HAVE_NEWABI) |
5901 | { | |
4d7206a2 | 5902 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5903 | ep->X_add_number = 0; |
4d7206a2 | 5904 | relax_start (ep->X_add_symbol); |
df58fc94 | 5905 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5906 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5907 | reg, reg, mips_gp_register); | |
5908 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5909 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5910 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5911 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5912 | else if (ex.X_add_number) | |
5913 | { | |
5914 | ex.X_op = O_constant; | |
67c0d1eb RS |
5915 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5916 | BFD_RELOC_LO16); | |
f5040a92 AO |
5917 | } |
5918 | ||
5919 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5920 | relax_switch (); |
67c0d1eb | 5921 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5922 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5923 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5924 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5925 | relax_end (); |
438c16b8 | 5926 | } |
252b5132 | 5927 | else |
438c16b8 | 5928 | { |
f5040a92 AO |
5929 | ex.X_add_number = ep->X_add_number; |
5930 | ep->X_add_number = 0; | |
4d7206a2 | 5931 | relax_start (ep->X_add_symbol); |
df58fc94 | 5932 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5933 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5934 | reg, reg, mips_gp_register); | |
5935 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5936 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5937 | relax_switch (); |
5938 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5939 | { |
5940 | /* We need a nop before loading from $gp. This special | |
5941 | check is required because the lui which starts the main | |
5942 | instruction stream does not refer to $gp, and so will not | |
5943 | insert the nop which may be required. */ | |
67c0d1eb | 5944 | macro_build (NULL, "nop", ""); |
438c16b8 | 5945 | } |
67c0d1eb | 5946 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5947 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5948 | load_delay_nop (); |
67c0d1eb | 5949 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5950 | BFD_RELOC_LO16); |
4d7206a2 | 5951 | relax_end (); |
438c16b8 | 5952 | |
f5040a92 AO |
5953 | if (ex.X_add_number != 0) |
5954 | { | |
5955 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5956 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5957 | ex.X_op = O_constant; | |
67c0d1eb RS |
5958 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5959 | BFD_RELOC_LO16); | |
f5040a92 | 5960 | } |
252b5132 RH |
5961 | } |
5962 | } | |
252b5132 RH |
5963 | else |
5964 | abort (); | |
8fc2e39e | 5965 | |
741fe287 | 5966 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5967 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5968 | } |
5969 | ||
ea1fb5dc RS |
5970 | /* Move the contents of register SOURCE into register DEST. */ |
5971 | ||
5972 | static void | |
67c0d1eb | 5973 | move_register (int dest, int source) |
ea1fb5dc | 5974 | { |
df58fc94 RS |
5975 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5976 | instruction specifically requires a 32-bit one. */ | |
5977 | if (mips_opts.micromips | |
5978 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 5979 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
5980 | else |
5981 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5982 | dest, source, 0); | |
ea1fb5dc RS |
5983 | } |
5984 | ||
4d7206a2 | 5985 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5986 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5987 | The two alternatives are: | |
4d7206a2 RS |
5988 | |
5989 | Global symbol Local sybmol | |
5990 | ------------- ------------ | |
5991 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5992 | ... ... | |
5993 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5994 | ||
5995 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5996 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5997 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5998 | |
5999 | static void | |
67c0d1eb | 6000 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6001 | { |
6002 | expressionS global; | |
6003 | ||
6004 | global = *local; | |
6005 | global.X_add_number = 0; | |
6006 | ||
6007 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6008 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6009 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6010 | relax_switch (); |
67c0d1eb RS |
6011 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6012 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6013 | relax_end (); |
6014 | } | |
6015 | ||
6016 | static void | |
67c0d1eb | 6017 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6018 | { |
6019 | expressionS global; | |
6020 | ||
6021 | global.X_op = O_constant; | |
6022 | global.X_op_symbol = NULL; | |
6023 | global.X_add_symbol = NULL; | |
6024 | global.X_add_number = local->X_add_number; | |
6025 | ||
6026 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6027 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6028 | dest, dest, BFD_RELOC_LO16); |
6029 | relax_switch (); | |
67c0d1eb | 6030 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6031 | relax_end (); |
6032 | } | |
6033 | ||
f6a22291 MR |
6034 | static void |
6035 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6036 | { | |
6037 | expressionS global; | |
6038 | int hold_mips_optimize; | |
6039 | ||
6040 | global.X_op = O_constant; | |
6041 | global.X_op_symbol = NULL; | |
6042 | global.X_add_symbol = NULL; | |
6043 | global.X_add_number = local->X_add_number; | |
6044 | ||
6045 | relax_start (local->X_add_symbol); | |
6046 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6047 | relax_switch (); | |
6048 | /* Set mips_optimize around the lui instruction to avoid | |
6049 | inserting an unnecessary nop after the lw. */ | |
6050 | hold_mips_optimize = mips_optimize; | |
6051 | mips_optimize = 2; | |
6052 | macro_build_lui (&global, tmp); | |
6053 | mips_optimize = hold_mips_optimize; | |
6054 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6055 | relax_end (); | |
6056 | ||
6057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6058 | } | |
6059 | ||
df58fc94 RS |
6060 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6061 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6062 | is its complementing branch with the original condition negated. | |
6063 | CALL is set if the original branch specified the link operation. | |
6064 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6065 | ||
6066 | Code like this is produced in the noreorder mode: | |
6067 | ||
6068 | BRNEG <args>, 1f | |
6069 | nop | |
6070 | b <sym> | |
6071 | delay slot (executed only if branch taken) | |
6072 | 1: | |
6073 | ||
6074 | or, if CALL is set: | |
6075 | ||
6076 | BRNEG <args>, 1f | |
6077 | nop | |
6078 | bal <sym> | |
6079 | delay slot (executed only if branch taken) | |
6080 | 1: | |
6081 | ||
6082 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6083 | so code produced is simply: | |
6084 | ||
6085 | BR <args>, <sym> | |
6086 | nop | |
6087 | ||
6088 | This function is used when producing code for the microMIPS ASE that | |
6089 | does not implement branch likely instructions in hardware. */ | |
6090 | ||
6091 | static void | |
6092 | macro_build_branch_likely (const char *br, const char *brneg, | |
6093 | int call, expressionS *ep, const char *fmt, | |
6094 | unsigned int sreg, unsigned int treg) | |
6095 | { | |
6096 | int noreorder = mips_opts.noreorder; | |
6097 | expressionS expr1; | |
6098 | ||
6099 | gas_assert (mips_opts.micromips); | |
6100 | start_noreorder (); | |
6101 | if (noreorder) | |
6102 | { | |
6103 | micromips_label_expr (&expr1); | |
6104 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6105 | macro_build (NULL, "nop", ""); | |
6106 | macro_build (ep, call ? "bal" : "b", "p"); | |
6107 | ||
6108 | /* Set to true so that append_insn adds a label. */ | |
6109 | emit_branch_likely_macro = TRUE; | |
6110 | } | |
6111 | else | |
6112 | { | |
6113 | macro_build (ep, br, fmt, sreg, treg); | |
6114 | macro_build (NULL, "nop", ""); | |
6115 | } | |
6116 | end_noreorder (); | |
6117 | } | |
6118 | ||
6119 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6120 | the condition code tested. EP specifies the branch target. */ | |
6121 | ||
6122 | static void | |
6123 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6124 | { | |
6125 | const int call = 0; | |
6126 | const char *brneg; | |
6127 | const char *br; | |
6128 | ||
6129 | switch (type) | |
6130 | { | |
6131 | case M_BC1FL: | |
6132 | br = "bc1f"; | |
6133 | brneg = "bc1t"; | |
6134 | break; | |
6135 | case M_BC1TL: | |
6136 | br = "bc1t"; | |
6137 | brneg = "bc1f"; | |
6138 | break; | |
6139 | case M_BC2FL: | |
6140 | br = "bc2f"; | |
6141 | brneg = "bc2t"; | |
6142 | break; | |
6143 | case M_BC2TL: | |
6144 | br = "bc2t"; | |
6145 | brneg = "bc2f"; | |
6146 | break; | |
6147 | default: | |
6148 | abort (); | |
6149 | } | |
6150 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6151 | } | |
6152 | ||
6153 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6154 | the register tested. EP specifies the branch target. */ | |
6155 | ||
6156 | static void | |
6157 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6158 | { | |
6159 | const char *brneg = NULL; | |
6160 | const char *br; | |
6161 | int call = 0; | |
6162 | ||
6163 | switch (type) | |
6164 | { | |
6165 | case M_BGEZ: | |
6166 | br = "bgez"; | |
6167 | break; | |
6168 | case M_BGEZL: | |
6169 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6170 | brneg = "bltz"; | |
6171 | break; | |
6172 | case M_BGEZALL: | |
6173 | gas_assert (mips_opts.micromips); | |
6174 | br = "bgezals"; | |
6175 | brneg = "bltz"; | |
6176 | call = 1; | |
6177 | break; | |
6178 | case M_BGTZ: | |
6179 | br = "bgtz"; | |
6180 | break; | |
6181 | case M_BGTZL: | |
6182 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6183 | brneg = "blez"; | |
6184 | break; | |
6185 | case M_BLEZ: | |
6186 | br = "blez"; | |
6187 | break; | |
6188 | case M_BLEZL: | |
6189 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6190 | brneg = "bgtz"; | |
6191 | break; | |
6192 | case M_BLTZ: | |
6193 | br = "bltz"; | |
6194 | break; | |
6195 | case M_BLTZL: | |
6196 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6197 | brneg = "bgez"; | |
6198 | break; | |
6199 | case M_BLTZALL: | |
6200 | gas_assert (mips_opts.micromips); | |
6201 | br = "bltzals"; | |
6202 | brneg = "bgez"; | |
6203 | call = 1; | |
6204 | break; | |
6205 | default: | |
6206 | abort (); | |
6207 | } | |
6208 | if (mips_opts.micromips && brneg) | |
6209 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6210 | else | |
6211 | macro_build (ep, br, "s,p", sreg); | |
6212 | } | |
6213 | ||
6214 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6215 | TREG as the registers tested. EP specifies the branch target. */ | |
6216 | ||
6217 | static void | |
6218 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6219 | unsigned int sreg, unsigned int treg) | |
6220 | { | |
6221 | const char *brneg = NULL; | |
6222 | const int call = 0; | |
6223 | const char *br; | |
6224 | ||
6225 | switch (type) | |
6226 | { | |
6227 | case M_BEQ: | |
6228 | case M_BEQ_I: | |
6229 | br = "beq"; | |
6230 | break; | |
6231 | case M_BEQL: | |
6232 | case M_BEQL_I: | |
6233 | br = mips_opts.micromips ? "beq" : "beql"; | |
6234 | brneg = "bne"; | |
6235 | break; | |
6236 | case M_BNE: | |
6237 | case M_BNE_I: | |
6238 | br = "bne"; | |
6239 | break; | |
6240 | case M_BNEL: | |
6241 | case M_BNEL_I: | |
6242 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6243 | brneg = "beq"; | |
6244 | break; | |
6245 | default: | |
6246 | abort (); | |
6247 | } | |
6248 | if (mips_opts.micromips && brneg) | |
6249 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6250 | else | |
6251 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6252 | } | |
6253 | ||
252b5132 RH |
6254 | /* |
6255 | * Build macros | |
6256 | * This routine implements the seemingly endless macro or synthesized | |
6257 | * instructions and addressing modes in the mips assembly language. Many | |
6258 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6259 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6260 | * this verbose method. Others are not simple macros but are more like |
6261 | * optimizing code generation. | |
6262 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6263 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6264 | * The ensuing load upper instructions are ommited. This implies some kind |
6265 | * of global optimization. We currently only optimize within a single macro. | |
6266 | * For many of the load and store macros if the address is specified as a | |
6267 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6268 | * first load register 'at' with zero and use it as the base register. The | |
6269 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6270 | * we're missing. | |
6271 | */ | |
6272 | static void | |
17a2f251 | 6273 | macro (struct mips_cl_insn *ip) |
252b5132 | 6274 | { |
741fe287 MR |
6275 | unsigned int treg, sreg, dreg, breg; |
6276 | unsigned int tempreg; | |
252b5132 | 6277 | int mask; |
43841e91 | 6278 | int used_at = 0; |
df58fc94 | 6279 | expressionS label_expr; |
252b5132 | 6280 | expressionS expr1; |
df58fc94 | 6281 | expressionS *ep; |
252b5132 RH |
6282 | const char *s; |
6283 | const char *s2; | |
6284 | const char *fmt; | |
6285 | int likely = 0; | |
252b5132 | 6286 | int coproc = 0; |
df58fc94 | 6287 | int off12 = 0; |
1abe91b1 | 6288 | int call = 0; |
df58fc94 RS |
6289 | int jals = 0; |
6290 | int dbl = 0; | |
6291 | int imm = 0; | |
6292 | int ust = 0; | |
6293 | int lp = 0; | |
6294 | int ab = 0; | |
dd6a37e7 | 6295 | int off0 = 0; |
252b5132 | 6296 | int off; |
67c0d1eb | 6297 | offsetT maxnum; |
252b5132 | 6298 | bfd_reloc_code_real_type r; |
252b5132 RH |
6299 | int hold_mips_optimize; |
6300 | ||
9c2799c2 | 6301 | gas_assert (! mips_opts.mips16); |
252b5132 | 6302 | |
df58fc94 RS |
6303 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6304 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6305 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6306 | mask = ip->insn_mo->mask; |
6307 | ||
df58fc94 RS |
6308 | label_expr.X_op = O_constant; |
6309 | label_expr.X_op_symbol = NULL; | |
6310 | label_expr.X_add_symbol = NULL; | |
6311 | label_expr.X_add_number = 0; | |
6312 | ||
252b5132 RH |
6313 | expr1.X_op = O_constant; |
6314 | expr1.X_op_symbol = NULL; | |
6315 | expr1.X_add_symbol = NULL; | |
6316 | expr1.X_add_number = 1; | |
6317 | ||
6318 | switch (mask) | |
6319 | { | |
6320 | case M_DABS: | |
6321 | dbl = 1; | |
6322 | case M_ABS: | |
df58fc94 RS |
6323 | /* bgez $a0,1f |
6324 | move v0,$a0 | |
6325 | sub v0,$zero,$a0 | |
6326 | 1: | |
6327 | */ | |
252b5132 | 6328 | |
7d10b47d | 6329 | start_noreorder (); |
252b5132 | 6330 | |
df58fc94 RS |
6331 | if (mips_opts.micromips) |
6332 | micromips_label_expr (&label_expr); | |
6333 | else | |
6334 | label_expr.X_add_number = 8; | |
6335 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6336 | if (dreg == sreg) |
a605d2b3 | 6337 | macro_build (NULL, "nop", ""); |
252b5132 | 6338 | else |
67c0d1eb RS |
6339 | move_register (dreg, sreg); |
6340 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6341 | if (mips_opts.micromips) |
6342 | micromips_add_label (); | |
252b5132 | 6343 | |
7d10b47d | 6344 | end_noreorder (); |
8fc2e39e | 6345 | break; |
252b5132 RH |
6346 | |
6347 | case M_ADD_I: | |
6348 | s = "addi"; | |
6349 | s2 = "add"; | |
6350 | goto do_addi; | |
6351 | case M_ADDU_I: | |
6352 | s = "addiu"; | |
6353 | s2 = "addu"; | |
6354 | goto do_addi; | |
6355 | case M_DADD_I: | |
6356 | dbl = 1; | |
6357 | s = "daddi"; | |
6358 | s2 = "dadd"; | |
df58fc94 RS |
6359 | if (!mips_opts.micromips) |
6360 | goto do_addi; | |
6361 | if (imm_expr.X_op == O_constant | |
6362 | && imm_expr.X_add_number >= -0x200 | |
6363 | && imm_expr.X_add_number < 0x200) | |
6364 | { | |
6365 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6366 | break; | |
6367 | } | |
6368 | goto do_addi_i; | |
252b5132 RH |
6369 | case M_DADDU_I: |
6370 | dbl = 1; | |
6371 | s = "daddiu"; | |
6372 | s2 = "daddu"; | |
6373 | do_addi: | |
6374 | if (imm_expr.X_op == O_constant | |
6375 | && imm_expr.X_add_number >= -0x8000 | |
6376 | && imm_expr.X_add_number < 0x8000) | |
6377 | { | |
67c0d1eb | 6378 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6379 | break; |
252b5132 | 6380 | } |
df58fc94 | 6381 | do_addi_i: |
8fc2e39e | 6382 | used_at = 1; |
67c0d1eb RS |
6383 | load_register (AT, &imm_expr, dbl); |
6384 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6385 | break; |
6386 | ||
6387 | case M_AND_I: | |
6388 | s = "andi"; | |
6389 | s2 = "and"; | |
6390 | goto do_bit; | |
6391 | case M_OR_I: | |
6392 | s = "ori"; | |
6393 | s2 = "or"; | |
6394 | goto do_bit; | |
6395 | case M_NOR_I: | |
6396 | s = ""; | |
6397 | s2 = "nor"; | |
6398 | goto do_bit; | |
6399 | case M_XOR_I: | |
6400 | s = "xori"; | |
6401 | s2 = "xor"; | |
6402 | do_bit: | |
6403 | if (imm_expr.X_op == O_constant | |
6404 | && imm_expr.X_add_number >= 0 | |
6405 | && imm_expr.X_add_number < 0x10000) | |
6406 | { | |
6407 | if (mask != M_NOR_I) | |
67c0d1eb | 6408 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6409 | else |
6410 | { | |
67c0d1eb RS |
6411 | macro_build (&imm_expr, "ori", "t,r,i", |
6412 | treg, sreg, BFD_RELOC_LO16); | |
6413 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6414 | } |
8fc2e39e | 6415 | break; |
252b5132 RH |
6416 | } |
6417 | ||
8fc2e39e | 6418 | used_at = 1; |
67c0d1eb RS |
6419 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6420 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6421 | break; |
6422 | ||
8b082fb1 TS |
6423 | case M_BALIGN: |
6424 | switch (imm_expr.X_add_number) | |
6425 | { | |
6426 | case 0: | |
6427 | macro_build (NULL, "nop", ""); | |
6428 | break; | |
6429 | case 2: | |
6430 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6431 | break; | |
03f66e8a MR |
6432 | case 1: |
6433 | case 3: | |
8b082fb1 | 6434 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6435 | (int) imm_expr.X_add_number); |
8b082fb1 | 6436 | break; |
03f66e8a MR |
6437 | default: |
6438 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6439 | (unsigned long) imm_expr.X_add_number); | |
6440 | break; | |
8b082fb1 TS |
6441 | } |
6442 | break; | |
6443 | ||
df58fc94 RS |
6444 | case M_BC1FL: |
6445 | case M_BC1TL: | |
6446 | case M_BC2FL: | |
6447 | case M_BC2TL: | |
6448 | gas_assert (mips_opts.micromips); | |
6449 | macro_build_branch_ccl (mask, &offset_expr, | |
6450 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6451 | break; | |
6452 | ||
252b5132 | 6453 | case M_BEQ_I: |
252b5132 | 6454 | case M_BEQL_I: |
252b5132 | 6455 | case M_BNE_I: |
252b5132 | 6456 | case M_BNEL_I: |
252b5132 | 6457 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6458 | treg = 0; |
6459 | else | |
252b5132 | 6460 | { |
df58fc94 RS |
6461 | treg = AT; |
6462 | used_at = 1; | |
6463 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6464 | } |
df58fc94 RS |
6465 | /* Fall through. */ |
6466 | case M_BEQL: | |
6467 | case M_BNEL: | |
6468 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6469 | break; |
6470 | ||
6471 | case M_BGEL: | |
6472 | likely = 1; | |
6473 | case M_BGE: | |
6474 | if (treg == 0) | |
df58fc94 RS |
6475 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6476 | else if (sreg == 0) | |
6477 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6478 | else | |
252b5132 | 6479 | { |
df58fc94 RS |
6480 | used_at = 1; |
6481 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6482 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6483 | &offset_expr, AT, ZERO); | |
252b5132 | 6484 | } |
df58fc94 RS |
6485 | break; |
6486 | ||
6487 | case M_BGEZL: | |
6488 | case M_BGEZALL: | |
6489 | case M_BGTZL: | |
6490 | case M_BLEZL: | |
6491 | case M_BLTZL: | |
6492 | case M_BLTZALL: | |
6493 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6494 | break; |
6495 | ||
6496 | case M_BGTL_I: | |
6497 | likely = 1; | |
6498 | case M_BGT_I: | |
90ecf173 | 6499 | /* Check for > max integer. */ |
252b5132 | 6500 | maxnum = 0x7fffffff; |
ca4e0257 | 6501 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6502 | { |
6503 | maxnum <<= 16; | |
6504 | maxnum |= 0xffff; | |
6505 | maxnum <<= 16; | |
6506 | maxnum |= 0xffff; | |
6507 | } | |
6508 | if (imm_expr.X_op == O_constant | |
6509 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6510 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6511 | { |
6512 | do_false: | |
90ecf173 | 6513 | /* Result is always false. */ |
252b5132 | 6514 | if (! likely) |
a605d2b3 | 6515 | macro_build (NULL, "nop", ""); |
252b5132 | 6516 | else |
df58fc94 | 6517 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6518 | break; |
252b5132 RH |
6519 | } |
6520 | if (imm_expr.X_op != O_constant) | |
6521 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6522 | ++imm_expr.X_add_number; |
252b5132 RH |
6523 | /* FALLTHROUGH */ |
6524 | case M_BGE_I: | |
6525 | case M_BGEL_I: | |
6526 | if (mask == M_BGEL_I) | |
6527 | likely = 1; | |
6528 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6529 | { | |
df58fc94 RS |
6530 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6531 | &offset_expr, sreg); | |
8fc2e39e | 6532 | break; |
252b5132 RH |
6533 | } |
6534 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6535 | { | |
df58fc94 RS |
6536 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6537 | &offset_expr, sreg); | |
8fc2e39e | 6538 | break; |
252b5132 RH |
6539 | } |
6540 | maxnum = 0x7fffffff; | |
ca4e0257 | 6541 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6542 | { |
6543 | maxnum <<= 16; | |
6544 | maxnum |= 0xffff; | |
6545 | maxnum <<= 16; | |
6546 | maxnum |= 0xffff; | |
6547 | } | |
6548 | maxnum = - maxnum - 1; | |
6549 | if (imm_expr.X_op == O_constant | |
6550 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6551 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6552 | { |
6553 | do_true: | |
6554 | /* result is always true */ | |
6555 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6556 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6557 | break; |
252b5132 | 6558 | } |
8fc2e39e | 6559 | used_at = 1; |
67c0d1eb | 6560 | set_at (sreg, 0); |
df58fc94 RS |
6561 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6562 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6563 | break; |
6564 | ||
6565 | case M_BGEUL: | |
6566 | likely = 1; | |
6567 | case M_BGEU: | |
6568 | if (treg == 0) | |
6569 | goto do_true; | |
df58fc94 RS |
6570 | else if (sreg == 0) |
6571 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6572 | &offset_expr, ZERO, treg); | |
6573 | else | |
252b5132 | 6574 | { |
df58fc94 RS |
6575 | used_at = 1; |
6576 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6577 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6578 | &offset_expr, AT, ZERO); | |
252b5132 | 6579 | } |
252b5132 RH |
6580 | break; |
6581 | ||
6582 | case M_BGTUL_I: | |
6583 | likely = 1; | |
6584 | case M_BGTU_I: | |
6585 | if (sreg == 0 | |
ca4e0257 | 6586 | || (HAVE_32BIT_GPRS |
252b5132 | 6587 | && imm_expr.X_op == O_constant |
f01dc953 | 6588 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6589 | goto do_false; |
6590 | if (imm_expr.X_op != O_constant) | |
6591 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6592 | ++imm_expr.X_add_number; |
252b5132 RH |
6593 | /* FALLTHROUGH */ |
6594 | case M_BGEU_I: | |
6595 | case M_BGEUL_I: | |
6596 | if (mask == M_BGEUL_I) | |
6597 | likely = 1; | |
6598 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6599 | goto do_true; | |
df58fc94 RS |
6600 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6601 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6602 | &offset_expr, sreg, ZERO); | |
6603 | else | |
252b5132 | 6604 | { |
df58fc94 RS |
6605 | used_at = 1; |
6606 | set_at (sreg, 1); | |
6607 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6608 | &offset_expr, AT, ZERO); | |
252b5132 | 6609 | } |
252b5132 RH |
6610 | break; |
6611 | ||
6612 | case M_BGTL: | |
6613 | likely = 1; | |
6614 | case M_BGT: | |
6615 | if (treg == 0) | |
df58fc94 RS |
6616 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6617 | else if (sreg == 0) | |
6618 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6619 | else | |
252b5132 | 6620 | { |
df58fc94 RS |
6621 | used_at = 1; |
6622 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6623 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6624 | &offset_expr, AT, ZERO); | |
252b5132 | 6625 | } |
252b5132 RH |
6626 | break; |
6627 | ||
6628 | case M_BGTUL: | |
6629 | likely = 1; | |
6630 | case M_BGTU: | |
6631 | if (treg == 0) | |
df58fc94 RS |
6632 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6633 | &offset_expr, sreg, ZERO); | |
6634 | else if (sreg == 0) | |
6635 | goto do_false; | |
6636 | else | |
252b5132 | 6637 | { |
df58fc94 RS |
6638 | used_at = 1; |
6639 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6640 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6641 | &offset_expr, AT, ZERO); | |
252b5132 | 6642 | } |
252b5132 RH |
6643 | break; |
6644 | ||
6645 | case M_BLEL: | |
6646 | likely = 1; | |
6647 | case M_BLE: | |
6648 | if (treg == 0) | |
df58fc94 RS |
6649 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6650 | else if (sreg == 0) | |
6651 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6652 | else | |
252b5132 | 6653 | { |
df58fc94 RS |
6654 | used_at = 1; |
6655 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6656 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6657 | &offset_expr, AT, ZERO); | |
252b5132 | 6658 | } |
252b5132 RH |
6659 | break; |
6660 | ||
6661 | case M_BLEL_I: | |
6662 | likely = 1; | |
6663 | case M_BLE_I: | |
6664 | maxnum = 0x7fffffff; | |
ca4e0257 | 6665 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6666 | { |
6667 | maxnum <<= 16; | |
6668 | maxnum |= 0xffff; | |
6669 | maxnum <<= 16; | |
6670 | maxnum |= 0xffff; | |
6671 | } | |
6672 | if (imm_expr.X_op == O_constant | |
6673 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6674 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6675 | goto do_true; |
6676 | if (imm_expr.X_op != O_constant) | |
6677 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6678 | ++imm_expr.X_add_number; |
252b5132 RH |
6679 | /* FALLTHROUGH */ |
6680 | case M_BLT_I: | |
6681 | case M_BLTL_I: | |
6682 | if (mask == M_BLTL_I) | |
6683 | likely = 1; | |
6684 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6685 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6686 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6687 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6688 | else | |
252b5132 | 6689 | { |
df58fc94 RS |
6690 | used_at = 1; |
6691 | set_at (sreg, 0); | |
6692 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6693 | &offset_expr, AT, ZERO); | |
252b5132 | 6694 | } |
252b5132 RH |
6695 | break; |
6696 | ||
6697 | case M_BLEUL: | |
6698 | likely = 1; | |
6699 | case M_BLEU: | |
6700 | if (treg == 0) | |
df58fc94 RS |
6701 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6702 | &offset_expr, sreg, ZERO); | |
6703 | else if (sreg == 0) | |
6704 | goto do_true; | |
6705 | else | |
252b5132 | 6706 | { |
df58fc94 RS |
6707 | used_at = 1; |
6708 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6709 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6710 | &offset_expr, AT, ZERO); | |
252b5132 | 6711 | } |
252b5132 RH |
6712 | break; |
6713 | ||
6714 | case M_BLEUL_I: | |
6715 | likely = 1; | |
6716 | case M_BLEU_I: | |
6717 | if (sreg == 0 | |
ca4e0257 | 6718 | || (HAVE_32BIT_GPRS |
252b5132 | 6719 | && imm_expr.X_op == O_constant |
f01dc953 | 6720 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6721 | goto do_true; |
6722 | if (imm_expr.X_op != O_constant) | |
6723 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6724 | ++imm_expr.X_add_number; |
252b5132 RH |
6725 | /* FALLTHROUGH */ |
6726 | case M_BLTU_I: | |
6727 | case M_BLTUL_I: | |
6728 | if (mask == M_BLTUL_I) | |
6729 | likely = 1; | |
6730 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6731 | goto do_false; | |
df58fc94 RS |
6732 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6733 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6734 | &offset_expr, sreg, ZERO); | |
6735 | else | |
252b5132 | 6736 | { |
df58fc94 RS |
6737 | used_at = 1; |
6738 | set_at (sreg, 1); | |
6739 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6740 | &offset_expr, AT, ZERO); | |
252b5132 | 6741 | } |
252b5132 RH |
6742 | break; |
6743 | ||
6744 | case M_BLTL: | |
6745 | likely = 1; | |
6746 | case M_BLT: | |
6747 | if (treg == 0) | |
df58fc94 RS |
6748 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6749 | else if (sreg == 0) | |
6750 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6751 | else | |
252b5132 | 6752 | { |
df58fc94 RS |
6753 | used_at = 1; |
6754 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6755 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6756 | &offset_expr, AT, ZERO); | |
252b5132 | 6757 | } |
252b5132 RH |
6758 | break; |
6759 | ||
6760 | case M_BLTUL: | |
6761 | likely = 1; | |
6762 | case M_BLTU: | |
6763 | if (treg == 0) | |
6764 | goto do_false; | |
df58fc94 RS |
6765 | else if (sreg == 0) |
6766 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6767 | &offset_expr, ZERO, treg); | |
6768 | else | |
252b5132 | 6769 | { |
df58fc94 RS |
6770 | used_at = 1; |
6771 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6772 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6773 | &offset_expr, AT, ZERO); | |
252b5132 | 6774 | } |
252b5132 RH |
6775 | break; |
6776 | ||
5f74bc13 CD |
6777 | case M_DEXT: |
6778 | { | |
d5818fca MR |
6779 | /* Use unsigned arithmetic. */ |
6780 | addressT pos; | |
6781 | addressT size; | |
5f74bc13 | 6782 | |
90ecf173 | 6783 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6784 | { |
6785 | as_bad (_("Unsupported large constant")); | |
6786 | pos = size = 1; | |
6787 | } | |
6788 | else | |
6789 | { | |
d5818fca MR |
6790 | pos = imm_expr.X_add_number; |
6791 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6792 | } |
6793 | ||
6794 | if (pos > 63) | |
6795 | { | |
d5818fca | 6796 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6797 | pos = 1; |
6798 | } | |
90ecf173 | 6799 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6800 | { |
6801 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6802 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6803 | size = 1; |
6804 | } | |
6805 | ||
6806 | if (size <= 32 && pos < 32) | |
6807 | { | |
6808 | s = "dext"; | |
6809 | fmt = "t,r,+A,+C"; | |
6810 | } | |
6811 | else if (size <= 32) | |
6812 | { | |
6813 | s = "dextu"; | |
6814 | fmt = "t,r,+E,+H"; | |
6815 | } | |
6816 | else | |
6817 | { | |
6818 | s = "dextm"; | |
6819 | fmt = "t,r,+A,+G"; | |
6820 | } | |
d5818fca MR |
6821 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6822 | (int) (size - 1)); | |
5f74bc13 | 6823 | } |
8fc2e39e | 6824 | break; |
5f74bc13 CD |
6825 | |
6826 | case M_DINS: | |
6827 | { | |
d5818fca MR |
6828 | /* Use unsigned arithmetic. */ |
6829 | addressT pos; | |
6830 | addressT size; | |
5f74bc13 | 6831 | |
90ecf173 | 6832 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6833 | { |
6834 | as_bad (_("Unsupported large constant")); | |
6835 | pos = size = 1; | |
6836 | } | |
6837 | else | |
6838 | { | |
d5818fca MR |
6839 | pos = imm_expr.X_add_number; |
6840 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6841 | } |
6842 | ||
6843 | if (pos > 63) | |
6844 | { | |
d5818fca | 6845 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6846 | pos = 1; |
6847 | } | |
90ecf173 | 6848 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6849 | { |
6850 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6851 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6852 | size = 1; |
6853 | } | |
6854 | ||
6855 | if (pos < 32 && (pos + size - 1) < 32) | |
6856 | { | |
6857 | s = "dins"; | |
6858 | fmt = "t,r,+A,+B"; | |
6859 | } | |
6860 | else if (pos >= 32) | |
6861 | { | |
6862 | s = "dinsu"; | |
6863 | fmt = "t,r,+E,+F"; | |
6864 | } | |
6865 | else | |
6866 | { | |
6867 | s = "dinsm"; | |
6868 | fmt = "t,r,+A,+F"; | |
6869 | } | |
750bdd57 AS |
6870 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6871 | (int) (pos + size - 1)); | |
5f74bc13 | 6872 | } |
8fc2e39e | 6873 | break; |
5f74bc13 | 6874 | |
252b5132 RH |
6875 | case M_DDIV_3: |
6876 | dbl = 1; | |
6877 | case M_DIV_3: | |
6878 | s = "mflo"; | |
6879 | goto do_div3; | |
6880 | case M_DREM_3: | |
6881 | dbl = 1; | |
6882 | case M_REM_3: | |
6883 | s = "mfhi"; | |
6884 | do_div3: | |
6885 | if (treg == 0) | |
6886 | { | |
6887 | as_warn (_("Divide by zero.")); | |
6888 | if (mips_trap) | |
df58fc94 | 6889 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6890 | else |
df58fc94 | 6891 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6892 | break; |
252b5132 RH |
6893 | } |
6894 | ||
7d10b47d | 6895 | start_noreorder (); |
252b5132 RH |
6896 | if (mips_trap) |
6897 | { | |
df58fc94 | 6898 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6899 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6900 | } |
6901 | else | |
6902 | { | |
df58fc94 RS |
6903 | if (mips_opts.micromips) |
6904 | micromips_label_expr (&label_expr); | |
6905 | else | |
6906 | label_expr.X_add_number = 8; | |
6907 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6908 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6909 | macro_build (NULL, "break", BRK_FMT, 7); |
6910 | if (mips_opts.micromips) | |
6911 | micromips_add_label (); | |
252b5132 RH |
6912 | } |
6913 | expr1.X_add_number = -1; | |
8fc2e39e | 6914 | used_at = 1; |
f6a22291 | 6915 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6916 | if (mips_opts.micromips) |
6917 | micromips_label_expr (&label_expr); | |
6918 | else | |
6919 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6920 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6921 | if (dbl) |
6922 | { | |
6923 | expr1.X_add_number = 1; | |
f6a22291 | 6924 | load_register (AT, &expr1, dbl); |
df58fc94 | 6925 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6926 | } |
6927 | else | |
6928 | { | |
6929 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6930 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6931 | } |
6932 | if (mips_trap) | |
6933 | { | |
df58fc94 | 6934 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6935 | /* We want to close the noreorder block as soon as possible, so |
6936 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6937 | end_noreorder (); |
252b5132 RH |
6938 | } |
6939 | else | |
6940 | { | |
df58fc94 RS |
6941 | if (mips_opts.micromips) |
6942 | micromips_label_expr (&label_expr); | |
6943 | else | |
6944 | label_expr.X_add_number = 8; | |
6945 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6946 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6947 | |
6948 | /* We want to close the noreorder block as soon as possible, so | |
6949 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6950 | end_noreorder (); |
252b5132 | 6951 | |
df58fc94 | 6952 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6953 | } |
df58fc94 RS |
6954 | if (mips_opts.micromips) |
6955 | micromips_add_label (); | |
6956 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6957 | break; |
6958 | ||
6959 | case M_DIV_3I: | |
6960 | s = "div"; | |
6961 | s2 = "mflo"; | |
6962 | goto do_divi; | |
6963 | case M_DIVU_3I: | |
6964 | s = "divu"; | |
6965 | s2 = "mflo"; | |
6966 | goto do_divi; | |
6967 | case M_REM_3I: | |
6968 | s = "div"; | |
6969 | s2 = "mfhi"; | |
6970 | goto do_divi; | |
6971 | case M_REMU_3I: | |
6972 | s = "divu"; | |
6973 | s2 = "mfhi"; | |
6974 | goto do_divi; | |
6975 | case M_DDIV_3I: | |
6976 | dbl = 1; | |
6977 | s = "ddiv"; | |
6978 | s2 = "mflo"; | |
6979 | goto do_divi; | |
6980 | case M_DDIVU_3I: | |
6981 | dbl = 1; | |
6982 | s = "ddivu"; | |
6983 | s2 = "mflo"; | |
6984 | goto do_divi; | |
6985 | case M_DREM_3I: | |
6986 | dbl = 1; | |
6987 | s = "ddiv"; | |
6988 | s2 = "mfhi"; | |
6989 | goto do_divi; | |
6990 | case M_DREMU_3I: | |
6991 | dbl = 1; | |
6992 | s = "ddivu"; | |
6993 | s2 = "mfhi"; | |
6994 | do_divi: | |
6995 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6996 | { | |
6997 | as_warn (_("Divide by zero.")); | |
6998 | if (mips_trap) | |
df58fc94 | 6999 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7000 | else |
df58fc94 | 7001 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7002 | break; |
252b5132 RH |
7003 | } |
7004 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7005 | { | |
7006 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7007 | move_register (dreg, sreg); |
252b5132 | 7008 | else |
c80c840e | 7009 | move_register (dreg, ZERO); |
8fc2e39e | 7010 | break; |
252b5132 RH |
7011 | } |
7012 | if (imm_expr.X_op == O_constant | |
7013 | && imm_expr.X_add_number == -1 | |
7014 | && s[strlen (s) - 1] != 'u') | |
7015 | { | |
7016 | if (strcmp (s2, "mflo") == 0) | |
7017 | { | |
67c0d1eb | 7018 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7019 | } |
7020 | else | |
c80c840e | 7021 | move_register (dreg, ZERO); |
8fc2e39e | 7022 | break; |
252b5132 RH |
7023 | } |
7024 | ||
8fc2e39e | 7025 | used_at = 1; |
67c0d1eb RS |
7026 | load_register (AT, &imm_expr, dbl); |
7027 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7028 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7029 | break; |
7030 | ||
7031 | case M_DIVU_3: | |
7032 | s = "divu"; | |
7033 | s2 = "mflo"; | |
7034 | goto do_divu3; | |
7035 | case M_REMU_3: | |
7036 | s = "divu"; | |
7037 | s2 = "mfhi"; | |
7038 | goto do_divu3; | |
7039 | case M_DDIVU_3: | |
7040 | s = "ddivu"; | |
7041 | s2 = "mflo"; | |
7042 | goto do_divu3; | |
7043 | case M_DREMU_3: | |
7044 | s = "ddivu"; | |
7045 | s2 = "mfhi"; | |
7046 | do_divu3: | |
7d10b47d | 7047 | start_noreorder (); |
252b5132 RH |
7048 | if (mips_trap) |
7049 | { | |
df58fc94 | 7050 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7051 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7052 | /* We want to close the noreorder block as soon as possible, so |
7053 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7054 | end_noreorder (); |
252b5132 RH |
7055 | } |
7056 | else | |
7057 | { | |
df58fc94 RS |
7058 | if (mips_opts.micromips) |
7059 | micromips_label_expr (&label_expr); | |
7060 | else | |
7061 | label_expr.X_add_number = 8; | |
7062 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7063 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7064 | |
7065 | /* We want to close the noreorder block as soon as possible, so | |
7066 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7067 | end_noreorder (); |
df58fc94 RS |
7068 | macro_build (NULL, "break", BRK_FMT, 7); |
7069 | if (mips_opts.micromips) | |
7070 | micromips_add_label (); | |
252b5132 | 7071 | } |
df58fc94 | 7072 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7073 | break; |
252b5132 | 7074 | |
1abe91b1 MR |
7075 | case M_DLCA_AB: |
7076 | dbl = 1; | |
7077 | case M_LCA_AB: | |
7078 | call = 1; | |
7079 | goto do_la; | |
252b5132 RH |
7080 | case M_DLA_AB: |
7081 | dbl = 1; | |
7082 | case M_LA_AB: | |
1abe91b1 | 7083 | do_la: |
252b5132 RH |
7084 | /* Load the address of a symbol into a register. If breg is not |
7085 | zero, we then add a base register to it. */ | |
7086 | ||
3bec30a8 TS |
7087 | if (dbl && HAVE_32BIT_GPRS) |
7088 | as_warn (_("dla used to load 32-bit register")); | |
7089 | ||
90ecf173 | 7090 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7091 | as_warn (_("la used to load 64-bit address")); |
7092 | ||
0c11417f MR |
7093 | if (offset_expr.X_op == O_constant |
7094 | && offset_expr.X_add_number >= -0x8000 | |
7095 | && offset_expr.X_add_number < 0x8000) | |
7096 | { | |
aed1a261 | 7097 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7098 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7099 | break; |
0c11417f MR |
7100 | } |
7101 | ||
741fe287 | 7102 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7103 | { |
7104 | tempreg = AT; | |
7105 | used_at = 1; | |
7106 | } | |
7107 | else | |
7108 | { | |
7109 | tempreg = treg; | |
afdbd6d0 CD |
7110 | } |
7111 | ||
252b5132 RH |
7112 | if (offset_expr.X_op != O_symbol |
7113 | && offset_expr.X_op != O_constant) | |
7114 | { | |
f71d0d44 | 7115 | as_bad (_("Expression too complex")); |
252b5132 RH |
7116 | offset_expr.X_op = O_constant; |
7117 | } | |
7118 | ||
252b5132 | 7119 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7120 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7121 | else if (mips_pic == NO_PIC) |
7122 | { | |
d6bc6245 | 7123 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7124 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7125 | Otherwise we want |
7126 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7127 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7128 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7129 | so we may as well always use the latter form. |
76b3015f | 7130 | |
6caf9ef4 TS |
7131 | With 64bit address space and a usable $at we want |
7132 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7133 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7134 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7135 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7136 | dsll32 $tempreg,0 | |
7137 | daddu $tempreg,$tempreg,$at | |
7138 | ||
7139 | If $at is already in use, we use a path which is suboptimal | |
7140 | on superscalar processors. | |
7141 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7142 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7143 | dsll $tempreg,16 | |
7144 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7145 | dsll $tempreg,16 | |
7146 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7147 | ||
7148 | For GP relative symbols in 64bit address space we can use | |
7149 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7150 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7151 | { |
6caf9ef4 TS |
7152 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7153 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7154 | { | |
7155 | relax_start (offset_expr.X_add_symbol); | |
7156 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7157 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7158 | relax_switch (); | |
7159 | } | |
d6bc6245 | 7160 | |
741fe287 | 7161 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7162 | { |
df58fc94 | 7163 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7164 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7165 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7166 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7167 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7168 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7169 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7170 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7171 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7172 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7173 | used_at = 1; |
7174 | } | |
7175 | else | |
7176 | { | |
df58fc94 | 7177 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7178 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7179 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7180 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7181 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7182 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7183 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7184 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7185 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7186 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7187 | } |
6caf9ef4 TS |
7188 | |
7189 | if (mips_relax.sequence) | |
7190 | relax_end (); | |
98d3f06f KH |
7191 | } |
7192 | else | |
7193 | { | |
7194 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7195 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7196 | { |
4d7206a2 | 7197 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7198 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7199 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7200 | relax_switch (); |
98d3f06f | 7201 | } |
6943caf0 | 7202 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7203 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7204 | macro_build_lui (&offset_expr, tempreg); |
7205 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7206 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7207 | if (mips_relax.sequence) |
7208 | relax_end (); | |
98d3f06f | 7209 | } |
252b5132 | 7210 | } |
0a44bf69 | 7211 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7212 | { |
9117d219 NC |
7213 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7214 | ||
252b5132 RH |
7215 | /* If this is a reference to an external symbol, and there |
7216 | is no constant, we want | |
7217 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7218 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7219 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7220 | For a local symbol, we want |
7221 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7222 | nop | |
7223 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7224 | ||
7225 | If we have a small constant, and this is a reference to | |
7226 | an external symbol, we want | |
7227 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7228 | nop | |
7229 | addiu $tempreg,$tempreg,<constant> | |
7230 | For a local symbol, we want the same instruction | |
7231 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7232 | addiu instruction. | |
7233 | ||
7234 | If we have a large constant, and this is a reference to | |
7235 | an external symbol, we want | |
7236 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7237 | lui $at,<hiconstant> | |
7238 | addiu $at,$at,<loconstant> | |
7239 | addu $tempreg,$tempreg,$at | |
7240 | For a local symbol, we want the same instruction | |
7241 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7242 | addiu instruction. |
ed6fb7bd SC |
7243 | */ |
7244 | ||
4d7206a2 | 7245 | if (offset_expr.X_add_number == 0) |
252b5132 | 7246 | { |
0a44bf69 RS |
7247 | if (mips_pic == SVR4_PIC |
7248 | && breg == 0 | |
7249 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7250 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7251 | ||
7252 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7253 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7254 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7255 | if (breg != 0) |
252b5132 RH |
7256 | { |
7257 | /* We're going to put in an addu instruction using | |
7258 | tempreg, so we may as well insert the nop right | |
7259 | now. */ | |
269137b2 | 7260 | load_delay_nop (); |
252b5132 | 7261 | } |
4d7206a2 | 7262 | relax_switch (); |
67c0d1eb RS |
7263 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7264 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7265 | load_delay_nop (); |
67c0d1eb RS |
7266 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7267 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7268 | relax_end (); |
252b5132 RH |
7269 | /* FIXME: If breg == 0, and the next instruction uses |
7270 | $tempreg, then if this variant case is used an extra | |
7271 | nop will be generated. */ | |
7272 | } | |
4d7206a2 RS |
7273 | else if (offset_expr.X_add_number >= -0x8000 |
7274 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7275 | { |
67c0d1eb | 7276 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7277 | load_delay_nop (); |
67c0d1eb | 7278 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7279 | } |
7280 | else | |
7281 | { | |
4d7206a2 RS |
7282 | expr1.X_add_number = offset_expr.X_add_number; |
7283 | offset_expr.X_add_number = | |
43c0598f | 7284 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7285 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7286 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7287 | /* If we are going to add in a base register, and the |
7288 | target register and the base register are the same, | |
7289 | then we are using AT as a temporary register. Since | |
7290 | we want to load the constant into AT, we add our | |
7291 | current AT (from the global offset table) and the | |
7292 | register into the register now, and pretend we were | |
7293 | not using a base register. */ | |
67c0d1eb | 7294 | if (breg == treg) |
252b5132 | 7295 | { |
269137b2 | 7296 | load_delay_nop (); |
67c0d1eb | 7297 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7298 | treg, AT, breg); |
252b5132 RH |
7299 | breg = 0; |
7300 | tempreg = treg; | |
252b5132 | 7301 | } |
f6a22291 | 7302 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7303 | used_at = 1; |
7304 | } | |
7305 | } | |
0a44bf69 | 7306 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7307 | { |
67c0d1eb | 7308 | int add_breg_early = 0; |
f5040a92 AO |
7309 | |
7310 | /* If this is a reference to an external, and there is no | |
7311 | constant, or local symbol (*), with or without a | |
7312 | constant, we want | |
7313 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7314 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7315 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7316 | ||
7317 | If we have a small constant, and this is a reference to | |
7318 | an external symbol, we want | |
7319 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7320 | addiu $tempreg,$tempreg,<constant> | |
7321 | ||
7322 | If we have a large constant, and this is a reference to | |
7323 | an external symbol, we want | |
7324 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7325 | lui $at,<hiconstant> | |
7326 | addiu $at,$at,<loconstant> | |
7327 | addu $tempreg,$tempreg,$at | |
7328 | ||
7329 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7330 | local symbols, even though it introduces an additional | |
7331 | instruction. */ | |
7332 | ||
f5040a92 AO |
7333 | if (offset_expr.X_add_number) |
7334 | { | |
4d7206a2 | 7335 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7336 | offset_expr.X_add_number = 0; |
7337 | ||
4d7206a2 | 7338 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7339 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7340 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7341 | |
7342 | if (expr1.X_add_number >= -0x8000 | |
7343 | && expr1.X_add_number < 0x8000) | |
7344 | { | |
67c0d1eb RS |
7345 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7346 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7347 | } |
ecd13cd3 | 7348 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7349 | { |
f5040a92 AO |
7350 | /* If we are going to add in a base register, and the |
7351 | target register and the base register are the same, | |
7352 | then we are using AT as a temporary register. Since | |
7353 | we want to load the constant into AT, we add our | |
7354 | current AT (from the global offset table) and the | |
7355 | register into the register now, and pretend we were | |
7356 | not using a base register. */ | |
7357 | if (breg != treg) | |
7358 | dreg = tempreg; | |
7359 | else | |
7360 | { | |
9c2799c2 | 7361 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7362 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7363 | treg, AT, breg); | |
f5040a92 | 7364 | dreg = treg; |
67c0d1eb | 7365 | add_breg_early = 1; |
f5040a92 AO |
7366 | } |
7367 | ||
f6a22291 | 7368 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7369 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7370 | dreg, dreg, AT); |
f5040a92 | 7371 | |
f5040a92 AO |
7372 | used_at = 1; |
7373 | } | |
7374 | else | |
7375 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7376 | ||
4d7206a2 | 7377 | relax_switch (); |
f5040a92 AO |
7378 | offset_expr.X_add_number = expr1.X_add_number; |
7379 | ||
67c0d1eb RS |
7380 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7381 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7382 | if (add_breg_early) | |
f5040a92 | 7383 | { |
67c0d1eb | 7384 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7385 | treg, tempreg, breg); |
f5040a92 AO |
7386 | breg = 0; |
7387 | tempreg = treg; | |
7388 | } | |
4d7206a2 | 7389 | relax_end (); |
f5040a92 | 7390 | } |
4d7206a2 | 7391 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7392 | { |
4d7206a2 | 7393 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7394 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7395 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7396 | relax_switch (); |
67c0d1eb RS |
7397 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7398 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7399 | relax_end (); |
f5040a92 | 7400 | } |
4d7206a2 | 7401 | else |
f5040a92 | 7402 | { |
67c0d1eb RS |
7403 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7404 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7405 | } |
7406 | } | |
0a44bf69 | 7407 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7408 | { |
67c0d1eb | 7409 | int gpdelay; |
9117d219 NC |
7410 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7411 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7412 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7413 | |
7414 | /* This is the large GOT case. If this is a reference to an | |
7415 | external symbol, and there is no constant, we want | |
7416 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7417 | addu $tempreg,$tempreg,$gp | |
7418 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7419 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7420 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7421 | addu $tempreg,$tempreg,$gp | |
7422 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7423 | For a local symbol, we want |
7424 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7425 | nop | |
7426 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7427 | ||
7428 | If we have a small constant, and this is a reference to | |
7429 | an external symbol, we want | |
7430 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7431 | addu $tempreg,$tempreg,$gp | |
7432 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7433 | nop | |
7434 | addiu $tempreg,$tempreg,<constant> | |
7435 | For a local symbol, we want | |
7436 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7437 | nop | |
7438 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7439 | ||
7440 | If we have a large constant, and this is a reference to | |
7441 | an external symbol, we want | |
7442 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7443 | addu $tempreg,$tempreg,$gp | |
7444 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7445 | lui $at,<hiconstant> | |
7446 | addiu $at,$at,<loconstant> | |
7447 | addu $tempreg,$tempreg,$at | |
7448 | For a local symbol, we want | |
7449 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7450 | lui $at,<hiconstant> | |
7451 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7452 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7453 | */ |
438c16b8 | 7454 | |
252b5132 RH |
7455 | expr1.X_add_number = offset_expr.X_add_number; |
7456 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7457 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7458 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7459 | if (expr1.X_add_number == 0 && breg == 0 |
7460 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7461 | { |
7462 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7463 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7464 | } | |
df58fc94 | 7465 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7467 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7468 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7469 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7470 | if (expr1.X_add_number == 0) |
7471 | { | |
67c0d1eb | 7472 | if (breg != 0) |
252b5132 RH |
7473 | { |
7474 | /* We're going to put in an addu instruction using | |
7475 | tempreg, so we may as well insert the nop right | |
7476 | now. */ | |
269137b2 | 7477 | load_delay_nop (); |
252b5132 | 7478 | } |
252b5132 RH |
7479 | } |
7480 | else if (expr1.X_add_number >= -0x8000 | |
7481 | && expr1.X_add_number < 0x8000) | |
7482 | { | |
269137b2 | 7483 | load_delay_nop (); |
67c0d1eb | 7484 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7485 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7486 | } |
7487 | else | |
7488 | { | |
252b5132 RH |
7489 | /* If we are going to add in a base register, and the |
7490 | target register and the base register are the same, | |
7491 | then we are using AT as a temporary register. Since | |
7492 | we want to load the constant into AT, we add our | |
7493 | current AT (from the global offset table) and the | |
7494 | register into the register now, and pretend we were | |
7495 | not using a base register. */ | |
7496 | if (breg != treg) | |
67c0d1eb | 7497 | dreg = tempreg; |
252b5132 RH |
7498 | else |
7499 | { | |
9c2799c2 | 7500 | gas_assert (tempreg == AT); |
269137b2 | 7501 | load_delay_nop (); |
67c0d1eb | 7502 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7503 | treg, AT, breg); |
252b5132 | 7504 | dreg = treg; |
252b5132 RH |
7505 | } |
7506 | ||
f6a22291 | 7507 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7508 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7509 | |
252b5132 RH |
7510 | used_at = 1; |
7511 | } | |
43c0598f | 7512 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 7513 | relax_switch (); |
252b5132 | 7514 | |
67c0d1eb | 7515 | if (gpdelay) |
252b5132 RH |
7516 | { |
7517 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7518 | the first instruction on the main stream does not. */ |
67c0d1eb | 7519 | macro_build (NULL, "nop", ""); |
252b5132 | 7520 | } |
ed6fb7bd | 7521 | |
67c0d1eb RS |
7522 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7523 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7524 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7525 | && expr1.X_add_number < 0x8000) |
7526 | { | |
269137b2 | 7527 | load_delay_nop (); |
67c0d1eb RS |
7528 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7529 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7530 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7531 | register, the external symbol case ended with a load, |
7532 | so if the symbol turns out to not be external, and | |
7533 | the next instruction uses tempreg, an unnecessary nop | |
7534 | will be inserted. */ | |
252b5132 RH |
7535 | } |
7536 | else | |
7537 | { | |
7538 | if (breg == treg) | |
7539 | { | |
7540 | /* We must add in the base register now, as in the | |
f5040a92 | 7541 | external symbol case. */ |
9c2799c2 | 7542 | gas_assert (tempreg == AT); |
269137b2 | 7543 | load_delay_nop (); |
67c0d1eb | 7544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7545 | treg, AT, breg); |
252b5132 RH |
7546 | tempreg = treg; |
7547 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7548 | it in in both cases. */ |
252b5132 RH |
7549 | breg = 0; |
7550 | } | |
7551 | ||
67c0d1eb RS |
7552 | macro_build_lui (&expr1, AT); |
7553 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7554 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7555 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7556 | tempreg, tempreg, AT); |
8fc2e39e | 7557 | used_at = 1; |
252b5132 | 7558 | } |
4d7206a2 | 7559 | relax_end (); |
252b5132 | 7560 | } |
0a44bf69 | 7561 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7562 | { |
f5040a92 AO |
7563 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7564 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7565 | int add_breg_early = 0; |
f5040a92 AO |
7566 | |
7567 | /* This is the large GOT case. If this is a reference to an | |
7568 | external symbol, and there is no constant, we want | |
7569 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7570 | add $tempreg,$tempreg,$gp | |
7571 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7572 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7573 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7574 | add $tempreg,$tempreg,$gp | |
7575 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7576 | ||
7577 | If we have a small constant, and this is a reference to | |
7578 | an external symbol, we want | |
7579 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7580 | add $tempreg,$tempreg,$gp | |
7581 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7582 | addi $tempreg,$tempreg,<constant> | |
7583 | ||
7584 | If we have a large constant, and this is a reference to | |
7585 | an external symbol, we want | |
7586 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7587 | addu $tempreg,$tempreg,$gp | |
7588 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7589 | lui $at,<hiconstant> | |
7590 | addi $at,$at,<loconstant> | |
7591 | add $tempreg,$tempreg,$at | |
7592 | ||
7593 | If we have NewABI, and we know it's a local symbol, we want | |
7594 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7595 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7596 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7597 | ||
4d7206a2 | 7598 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7599 | |
4d7206a2 | 7600 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7601 | offset_expr.X_add_number = 0; |
7602 | ||
1abe91b1 MR |
7603 | if (expr1.X_add_number == 0 && breg == 0 |
7604 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7605 | { |
7606 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7607 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7608 | } | |
df58fc94 | 7609 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7611 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7612 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7613 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7614 | |
7615 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7616 | ; |
f5040a92 AO |
7617 | else if (expr1.X_add_number >= -0x8000 |
7618 | && expr1.X_add_number < 0x8000) | |
7619 | { | |
67c0d1eb | 7620 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7621 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7622 | } |
ecd13cd3 | 7623 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7624 | { |
f5040a92 AO |
7625 | /* If we are going to add in a base register, and the |
7626 | target register and the base register are the same, | |
7627 | then we are using AT as a temporary register. Since | |
7628 | we want to load the constant into AT, we add our | |
7629 | current AT (from the global offset table) and the | |
7630 | register into the register now, and pretend we were | |
7631 | not using a base register. */ | |
7632 | if (breg != treg) | |
7633 | dreg = tempreg; | |
7634 | else | |
7635 | { | |
9c2799c2 | 7636 | gas_assert (tempreg == AT); |
67c0d1eb | 7637 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7638 | treg, AT, breg); |
f5040a92 | 7639 | dreg = treg; |
67c0d1eb | 7640 | add_breg_early = 1; |
f5040a92 AO |
7641 | } |
7642 | ||
f6a22291 | 7643 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7644 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7645 | |
f5040a92 AO |
7646 | used_at = 1; |
7647 | } | |
7648 | else | |
7649 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7650 | ||
4d7206a2 | 7651 | relax_switch (); |
f5040a92 | 7652 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7653 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7654 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7655 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7656 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7657 | if (add_breg_early) | |
f5040a92 | 7658 | { |
67c0d1eb | 7659 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7660 | treg, tempreg, breg); |
f5040a92 AO |
7661 | breg = 0; |
7662 | tempreg = treg; | |
7663 | } | |
4d7206a2 | 7664 | relax_end (); |
f5040a92 | 7665 | } |
252b5132 RH |
7666 | else |
7667 | abort (); | |
7668 | ||
7669 | if (breg != 0) | |
aed1a261 | 7670 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7671 | break; |
7672 | ||
52b6b6b9 | 7673 | case M_MSGSND: |
df58fc94 | 7674 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7675 | { |
7676 | unsigned long temp = (treg << 16) | (0x01); | |
7677 | macro_build (NULL, "c2", "C", temp); | |
7678 | } | |
c7af4273 | 7679 | break; |
52b6b6b9 JM |
7680 | |
7681 | case M_MSGLD: | |
df58fc94 | 7682 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7683 | { |
7684 | unsigned long temp = (0x02); | |
7685 | macro_build (NULL, "c2", "C", temp); | |
7686 | } | |
c7af4273 | 7687 | break; |
52b6b6b9 JM |
7688 | |
7689 | case M_MSGLD_T: | |
df58fc94 | 7690 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7691 | { |
7692 | unsigned long temp = (treg << 16) | (0x02); | |
7693 | macro_build (NULL, "c2", "C", temp); | |
7694 | } | |
c7af4273 | 7695 | break; |
52b6b6b9 JM |
7696 | |
7697 | case M_MSGWAIT: | |
df58fc94 | 7698 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7699 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7700 | break; |
52b6b6b9 JM |
7701 | |
7702 | case M_MSGWAIT_T: | |
df58fc94 | 7703 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7704 | { |
7705 | unsigned long temp = (treg << 16) | 0x03; | |
7706 | macro_build (NULL, "c2", "C", temp); | |
7707 | } | |
c7af4273 | 7708 | break; |
52b6b6b9 | 7709 | |
252b5132 RH |
7710 | case M_J_A: |
7711 | /* The j instruction may not be used in PIC code, since it | |
7712 | requires an absolute address. We convert it to a b | |
7713 | instruction. */ | |
7714 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7715 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7716 | else |
67c0d1eb | 7717 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7718 | break; |
252b5132 RH |
7719 | |
7720 | /* The jal instructions must be handled as macros because when | |
7721 | generating PIC code they expand to multi-instruction | |
7722 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7723 | case M_JALS_1: |
7724 | dreg = RA; | |
7725 | /* Fall through. */ | |
7726 | case M_JALS_2: | |
7727 | gas_assert (mips_opts.micromips); | |
7728 | jals = 1; | |
7729 | goto jal; | |
252b5132 RH |
7730 | case M_JAL_1: |
7731 | dreg = RA; | |
7732 | /* Fall through. */ | |
7733 | case M_JAL_2: | |
df58fc94 | 7734 | jal: |
3e722fb5 | 7735 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7736 | { |
7737 | s = jals ? "jalrs" : "jalr"; | |
7738 | if (mips_opts.micromips && dreg == RA) | |
7739 | macro_build (NULL, s, "mj", sreg); | |
7740 | else | |
7741 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7742 | } | |
0a44bf69 | 7743 | else |
252b5132 | 7744 | { |
df58fc94 RS |
7745 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7746 | && mips_cprestore_offset >= 0); | |
7747 | ||
252b5132 RH |
7748 | if (sreg != PIC_CALL_REG) |
7749 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7750 | |
df58fc94 RS |
7751 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7752 | ? "jalrs" : "jalr"); | |
7753 | if (mips_opts.micromips && dreg == RA) | |
7754 | macro_build (NULL, s, "mj", sreg); | |
7755 | else | |
7756 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7757 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7758 | { |
6478892d TS |
7759 | if (mips_cprestore_offset < 0) |
7760 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7761 | else | |
7762 | { | |
90ecf173 | 7763 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7764 | { |
7765 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7766 | /* Quiet this warning. */ | |
7767 | mips_frame_reg_valid = 1; | |
7768 | } | |
90ecf173 | 7769 | if (!mips_cprestore_valid) |
7a621144 DJ |
7770 | { |
7771 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7772 | /* Quiet this warning. */ | |
7773 | mips_cprestore_valid = 1; | |
7774 | } | |
d3fca0b5 MR |
7775 | if (mips_opts.noreorder) |
7776 | macro_build (NULL, "nop", ""); | |
6478892d | 7777 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7778 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7779 | mips_gp_register, |
256ab948 TS |
7780 | mips_frame_reg, |
7781 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7782 | } |
252b5132 RH |
7783 | } |
7784 | } | |
252b5132 | 7785 | |
8fc2e39e | 7786 | break; |
252b5132 | 7787 | |
df58fc94 RS |
7788 | case M_JALS_A: |
7789 | gas_assert (mips_opts.micromips); | |
7790 | jals = 1; | |
7791 | /* Fall through. */ | |
252b5132 RH |
7792 | case M_JAL_A: |
7793 | if (mips_pic == NO_PIC) | |
df58fc94 | 7794 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7795 | else if (mips_pic == SVR4_PIC) |
7796 | { | |
7797 | /* If this is a reference to an external symbol, and we are | |
7798 | using a small GOT, we want | |
7799 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7800 | nop | |
f9419b05 | 7801 | jalr $ra,$25 |
252b5132 RH |
7802 | nop |
7803 | lw $gp,cprestore($sp) | |
7804 | The cprestore value is set using the .cprestore | |
7805 | pseudo-op. If we are using a big GOT, we want | |
7806 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7807 | addu $25,$25,$gp | |
7808 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7809 | nop | |
f9419b05 | 7810 | jalr $ra,$25 |
252b5132 RH |
7811 | nop |
7812 | lw $gp,cprestore($sp) | |
7813 | If the symbol is not external, we want | |
7814 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7815 | nop | |
7816 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7817 | jalr $ra,$25 |
252b5132 | 7818 | nop |
438c16b8 | 7819 | lw $gp,cprestore($sp) |
f5040a92 AO |
7820 | |
7821 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7822 | sequences above, minus nops, unless the symbol is local, | |
7823 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7824 | GOT_DISP. */ | |
438c16b8 | 7825 | if (HAVE_NEWABI) |
252b5132 | 7826 | { |
90ecf173 | 7827 | if (!mips_big_got) |
f5040a92 | 7828 | { |
4d7206a2 | 7829 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7830 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7831 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7832 | mips_gp_register); |
4d7206a2 | 7833 | relax_switch (); |
67c0d1eb RS |
7834 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7835 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7836 | mips_gp_register); |
7837 | relax_end (); | |
f5040a92 AO |
7838 | } |
7839 | else | |
7840 | { | |
4d7206a2 | 7841 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7842 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7843 | BFD_RELOC_MIPS_CALL_HI16); |
7844 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7845 | PIC_CALL_REG, mips_gp_register); | |
7846 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7847 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7848 | PIC_CALL_REG); | |
4d7206a2 | 7849 | relax_switch (); |
67c0d1eb RS |
7850 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7851 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7852 | mips_gp_register); | |
7853 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7854 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7855 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7856 | relax_end (); |
f5040a92 | 7857 | } |
684022ea | 7858 | |
df58fc94 | 7859 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7860 | } |
7861 | else | |
7862 | { | |
4d7206a2 | 7863 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7864 | if (!mips_big_got) |
438c16b8 | 7865 | { |
67c0d1eb RS |
7866 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7867 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7868 | mips_gp_register); |
269137b2 | 7869 | load_delay_nop (); |
4d7206a2 | 7870 | relax_switch (); |
438c16b8 | 7871 | } |
252b5132 | 7872 | else |
252b5132 | 7873 | { |
67c0d1eb RS |
7874 | int gpdelay; |
7875 | ||
7876 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7877 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7878 | BFD_RELOC_MIPS_CALL_HI16); |
7879 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7880 | PIC_CALL_REG, mips_gp_register); | |
7881 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7882 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7883 | PIC_CALL_REG); | |
269137b2 | 7884 | load_delay_nop (); |
4d7206a2 | 7885 | relax_switch (); |
67c0d1eb RS |
7886 | if (gpdelay) |
7887 | macro_build (NULL, "nop", ""); | |
252b5132 | 7888 | } |
67c0d1eb RS |
7889 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7890 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7891 | mips_gp_register); |
269137b2 | 7892 | load_delay_nop (); |
67c0d1eb RS |
7893 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7894 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7895 | relax_end (); |
df58fc94 | 7896 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7897 | |
6478892d TS |
7898 | if (mips_cprestore_offset < 0) |
7899 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7900 | else | |
7901 | { | |
90ecf173 | 7902 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7903 | { |
7904 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7905 | /* Quiet this warning. */ | |
7906 | mips_frame_reg_valid = 1; | |
7907 | } | |
90ecf173 | 7908 | if (!mips_cprestore_valid) |
7a621144 DJ |
7909 | { |
7910 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7911 | /* Quiet this warning. */ | |
7912 | mips_cprestore_valid = 1; | |
7913 | } | |
6478892d | 7914 | if (mips_opts.noreorder) |
67c0d1eb | 7915 | macro_build (NULL, "nop", ""); |
6478892d | 7916 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7917 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7918 | mips_gp_register, |
256ab948 TS |
7919 | mips_frame_reg, |
7920 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7921 | } |
252b5132 RH |
7922 | } |
7923 | } | |
0a44bf69 RS |
7924 | else if (mips_pic == VXWORKS_PIC) |
7925 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7926 | else |
7927 | abort (); | |
7928 | ||
8fc2e39e | 7929 | break; |
252b5132 | 7930 | |
dec0624d MR |
7931 | case M_ACLR_AB: |
7932 | ab = 1; | |
7933 | case M_ACLR_OB: | |
7934 | s = "aclr"; | |
7935 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7936 | fmt = "\\,~(b)"; | |
7937 | off12 = 1; | |
7938 | goto ld_st; | |
7939 | case M_ASET_AB: | |
7940 | ab = 1; | |
7941 | case M_ASET_OB: | |
7942 | s = "aset"; | |
7943 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7944 | fmt = "\\,~(b)"; | |
7945 | off12 = 1; | |
7946 | goto ld_st; | |
252b5132 | 7947 | case M_LB_AB: |
df58fc94 | 7948 | ab = 1; |
252b5132 | 7949 | s = "lb"; |
df58fc94 | 7950 | fmt = "t,o(b)"; |
252b5132 RH |
7951 | goto ld; |
7952 | case M_LBU_AB: | |
df58fc94 | 7953 | ab = 1; |
252b5132 | 7954 | s = "lbu"; |
df58fc94 | 7955 | fmt = "t,o(b)"; |
252b5132 RH |
7956 | goto ld; |
7957 | case M_LH_AB: | |
df58fc94 | 7958 | ab = 1; |
252b5132 | 7959 | s = "lh"; |
df58fc94 | 7960 | fmt = "t,o(b)"; |
252b5132 RH |
7961 | goto ld; |
7962 | case M_LHU_AB: | |
df58fc94 | 7963 | ab = 1; |
252b5132 | 7964 | s = "lhu"; |
df58fc94 | 7965 | fmt = "t,o(b)"; |
252b5132 RH |
7966 | goto ld; |
7967 | case M_LW_AB: | |
df58fc94 | 7968 | ab = 1; |
252b5132 | 7969 | s = "lw"; |
df58fc94 | 7970 | fmt = "t,o(b)"; |
252b5132 RH |
7971 | goto ld; |
7972 | case M_LWC0_AB: | |
df58fc94 RS |
7973 | ab = 1; |
7974 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7975 | s = "lwc0"; |
df58fc94 | 7976 | fmt = "E,o(b)"; |
bdaaa2e1 | 7977 | /* Itbl support may require additional care here. */ |
252b5132 | 7978 | coproc = 1; |
df58fc94 | 7979 | goto ld_st; |
252b5132 | 7980 | case M_LWC1_AB: |
df58fc94 | 7981 | ab = 1; |
252b5132 | 7982 | s = "lwc1"; |
df58fc94 | 7983 | fmt = "T,o(b)"; |
bdaaa2e1 | 7984 | /* Itbl support may require additional care here. */ |
252b5132 | 7985 | coproc = 1; |
df58fc94 | 7986 | goto ld_st; |
252b5132 | 7987 | case M_LWC2_AB: |
df58fc94 RS |
7988 | ab = 1; |
7989 | case M_LWC2_OB: | |
252b5132 | 7990 | s = "lwc2"; |
df58fc94 RS |
7991 | fmt = COP12_FMT; |
7992 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7993 | /* Itbl support may require additional care here. */ |
252b5132 | 7994 | coproc = 1; |
df58fc94 | 7995 | goto ld_st; |
252b5132 | 7996 | case M_LWC3_AB: |
df58fc94 RS |
7997 | ab = 1; |
7998 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7999 | s = "lwc3"; |
df58fc94 | 8000 | fmt = "E,o(b)"; |
bdaaa2e1 | 8001 | /* Itbl support may require additional care here. */ |
252b5132 | 8002 | coproc = 1; |
df58fc94 | 8003 | goto ld_st; |
252b5132 | 8004 | case M_LWL_AB: |
df58fc94 RS |
8005 | ab = 1; |
8006 | case M_LWL_OB: | |
252b5132 | 8007 | s = "lwl"; |
df58fc94 RS |
8008 | fmt = MEM12_FMT; |
8009 | off12 = mips_opts.micromips; | |
8010 | goto ld_st; | |
252b5132 | 8011 | case M_LWR_AB: |
df58fc94 RS |
8012 | ab = 1; |
8013 | case M_LWR_OB: | |
252b5132 | 8014 | s = "lwr"; |
df58fc94 RS |
8015 | fmt = MEM12_FMT; |
8016 | off12 = mips_opts.micromips; | |
8017 | goto ld_st; | |
252b5132 | 8018 | case M_LDC1_AB: |
df58fc94 | 8019 | ab = 1; |
252b5132 | 8020 | s = "ldc1"; |
df58fc94 | 8021 | fmt = "T,o(b)"; |
bdaaa2e1 | 8022 | /* Itbl support may require additional care here. */ |
252b5132 | 8023 | coproc = 1; |
df58fc94 | 8024 | goto ld_st; |
252b5132 | 8025 | case M_LDC2_AB: |
df58fc94 RS |
8026 | ab = 1; |
8027 | case M_LDC2_OB: | |
252b5132 | 8028 | s = "ldc2"; |
df58fc94 RS |
8029 | fmt = COP12_FMT; |
8030 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8031 | /* Itbl support may require additional care here. */ |
252b5132 | 8032 | coproc = 1; |
df58fc94 | 8033 | goto ld_st; |
252b5132 | 8034 | case M_LDC3_AB: |
df58fc94 | 8035 | ab = 1; |
252b5132 | 8036 | s = "ldc3"; |
df58fc94 | 8037 | fmt = "E,o(b)"; |
bdaaa2e1 | 8038 | /* Itbl support may require additional care here. */ |
252b5132 | 8039 | coproc = 1; |
df58fc94 | 8040 | goto ld_st; |
252b5132 | 8041 | case M_LDL_AB: |
df58fc94 RS |
8042 | ab = 1; |
8043 | case M_LDL_OB: | |
252b5132 | 8044 | s = "ldl"; |
df58fc94 RS |
8045 | fmt = MEM12_FMT; |
8046 | off12 = mips_opts.micromips; | |
8047 | goto ld_st; | |
252b5132 | 8048 | case M_LDR_AB: |
df58fc94 RS |
8049 | ab = 1; |
8050 | case M_LDR_OB: | |
252b5132 | 8051 | s = "ldr"; |
df58fc94 RS |
8052 | fmt = MEM12_FMT; |
8053 | off12 = mips_opts.micromips; | |
8054 | goto ld_st; | |
252b5132 | 8055 | case M_LL_AB: |
df58fc94 RS |
8056 | ab = 1; |
8057 | case M_LL_OB: | |
252b5132 | 8058 | s = "ll"; |
df58fc94 RS |
8059 | fmt = MEM12_FMT; |
8060 | off12 = mips_opts.micromips; | |
252b5132 RH |
8061 | goto ld; |
8062 | case M_LLD_AB: | |
df58fc94 RS |
8063 | ab = 1; |
8064 | case M_LLD_OB: | |
252b5132 | 8065 | s = "lld"; |
df58fc94 RS |
8066 | fmt = MEM12_FMT; |
8067 | off12 = mips_opts.micromips; | |
252b5132 RH |
8068 | goto ld; |
8069 | case M_LWU_AB: | |
df58fc94 RS |
8070 | ab = 1; |
8071 | case M_LWU_OB: | |
252b5132 | 8072 | s = "lwu"; |
df58fc94 RS |
8073 | fmt = MEM12_FMT; |
8074 | off12 = mips_opts.micromips; | |
8075 | goto ld; | |
8076 | case M_LWP_AB: | |
8077 | ab = 1; | |
8078 | case M_LWP_OB: | |
8079 | gas_assert (mips_opts.micromips); | |
8080 | s = "lwp"; | |
8081 | fmt = "t,~(b)"; | |
8082 | off12 = 1; | |
8083 | lp = 1; | |
8084 | goto ld; | |
8085 | case M_LDP_AB: | |
8086 | ab = 1; | |
8087 | case M_LDP_OB: | |
8088 | gas_assert (mips_opts.micromips); | |
8089 | s = "ldp"; | |
8090 | fmt = "t,~(b)"; | |
8091 | off12 = 1; | |
8092 | lp = 1; | |
8093 | goto ld; | |
8094 | case M_LWM_AB: | |
8095 | ab = 1; | |
8096 | case M_LWM_OB: | |
8097 | gas_assert (mips_opts.micromips); | |
8098 | s = "lwm"; | |
8099 | fmt = "n,~(b)"; | |
8100 | off12 = 1; | |
8101 | goto ld_st; | |
8102 | case M_LDM_AB: | |
8103 | ab = 1; | |
8104 | case M_LDM_OB: | |
8105 | gas_assert (mips_opts.micromips); | |
8106 | s = "ldm"; | |
8107 | fmt = "n,~(b)"; | |
8108 | off12 = 1; | |
8109 | goto ld_st; | |
8110 | ||
252b5132 | 8111 | ld: |
df58fc94 RS |
8112 | if (breg == treg + lp) |
8113 | goto ld_st; | |
252b5132 | 8114 | else |
df58fc94 RS |
8115 | tempreg = treg + lp; |
8116 | goto ld_noat; | |
8117 | ||
252b5132 | 8118 | case M_SB_AB: |
df58fc94 | 8119 | ab = 1; |
252b5132 | 8120 | s = "sb"; |
df58fc94 RS |
8121 | fmt = "t,o(b)"; |
8122 | goto ld_st; | |
252b5132 | 8123 | case M_SH_AB: |
df58fc94 | 8124 | ab = 1; |
252b5132 | 8125 | s = "sh"; |
df58fc94 RS |
8126 | fmt = "t,o(b)"; |
8127 | goto ld_st; | |
252b5132 | 8128 | case M_SW_AB: |
df58fc94 | 8129 | ab = 1; |
252b5132 | 8130 | s = "sw"; |
df58fc94 RS |
8131 | fmt = "t,o(b)"; |
8132 | goto ld_st; | |
252b5132 | 8133 | case M_SWC0_AB: |
df58fc94 RS |
8134 | ab = 1; |
8135 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8136 | s = "swc0"; |
df58fc94 | 8137 | fmt = "E,o(b)"; |
bdaaa2e1 | 8138 | /* Itbl support may require additional care here. */ |
252b5132 | 8139 | coproc = 1; |
df58fc94 | 8140 | goto ld_st; |
252b5132 | 8141 | case M_SWC1_AB: |
df58fc94 | 8142 | ab = 1; |
252b5132 | 8143 | s = "swc1"; |
df58fc94 | 8144 | fmt = "T,o(b)"; |
bdaaa2e1 | 8145 | /* Itbl support may require additional care here. */ |
252b5132 | 8146 | coproc = 1; |
df58fc94 | 8147 | goto ld_st; |
252b5132 | 8148 | case M_SWC2_AB: |
df58fc94 RS |
8149 | ab = 1; |
8150 | case M_SWC2_OB: | |
252b5132 | 8151 | s = "swc2"; |
df58fc94 RS |
8152 | fmt = COP12_FMT; |
8153 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8154 | /* Itbl support may require additional care here. */ |
252b5132 | 8155 | coproc = 1; |
df58fc94 | 8156 | goto ld_st; |
252b5132 | 8157 | case M_SWC3_AB: |
df58fc94 RS |
8158 | ab = 1; |
8159 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8160 | s = "swc3"; |
df58fc94 | 8161 | fmt = "E,o(b)"; |
bdaaa2e1 | 8162 | /* Itbl support may require additional care here. */ |
252b5132 | 8163 | coproc = 1; |
df58fc94 | 8164 | goto ld_st; |
252b5132 | 8165 | case M_SWL_AB: |
df58fc94 RS |
8166 | ab = 1; |
8167 | case M_SWL_OB: | |
252b5132 | 8168 | s = "swl"; |
df58fc94 RS |
8169 | fmt = MEM12_FMT; |
8170 | off12 = mips_opts.micromips; | |
8171 | goto ld_st; | |
252b5132 | 8172 | case M_SWR_AB: |
df58fc94 RS |
8173 | ab = 1; |
8174 | case M_SWR_OB: | |
252b5132 | 8175 | s = "swr"; |
df58fc94 RS |
8176 | fmt = MEM12_FMT; |
8177 | off12 = mips_opts.micromips; | |
8178 | goto ld_st; | |
252b5132 | 8179 | case M_SC_AB: |
df58fc94 RS |
8180 | ab = 1; |
8181 | case M_SC_OB: | |
252b5132 | 8182 | s = "sc"; |
df58fc94 RS |
8183 | fmt = MEM12_FMT; |
8184 | off12 = mips_opts.micromips; | |
8185 | goto ld_st; | |
252b5132 | 8186 | case M_SCD_AB: |
df58fc94 RS |
8187 | ab = 1; |
8188 | case M_SCD_OB: | |
252b5132 | 8189 | s = "scd"; |
df58fc94 RS |
8190 | fmt = MEM12_FMT; |
8191 | off12 = mips_opts.micromips; | |
8192 | goto ld_st; | |
d43b4baf | 8193 | case M_CACHE_AB: |
df58fc94 RS |
8194 | ab = 1; |
8195 | case M_CACHE_OB: | |
d43b4baf | 8196 | s = "cache"; |
df58fc94 RS |
8197 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8198 | off12 = mips_opts.micromips; | |
8199 | goto ld_st; | |
3eebd5eb | 8200 | case M_PREF_AB: |
df58fc94 RS |
8201 | ab = 1; |
8202 | case M_PREF_OB: | |
3eebd5eb | 8203 | s = "pref"; |
df58fc94 RS |
8204 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8205 | off12 = mips_opts.micromips; | |
8206 | goto ld_st; | |
252b5132 | 8207 | case M_SDC1_AB: |
df58fc94 | 8208 | ab = 1; |
252b5132 | 8209 | s = "sdc1"; |
df58fc94 | 8210 | fmt = "T,o(b)"; |
252b5132 | 8211 | coproc = 1; |
bdaaa2e1 | 8212 | /* Itbl support may require additional care here. */ |
df58fc94 | 8213 | goto ld_st; |
252b5132 | 8214 | case M_SDC2_AB: |
df58fc94 RS |
8215 | ab = 1; |
8216 | case M_SDC2_OB: | |
252b5132 | 8217 | s = "sdc2"; |
df58fc94 RS |
8218 | fmt = COP12_FMT; |
8219 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8220 | /* Itbl support may require additional care here. */ |
252b5132 | 8221 | coproc = 1; |
df58fc94 | 8222 | goto ld_st; |
252b5132 | 8223 | case M_SDC3_AB: |
df58fc94 RS |
8224 | ab = 1; |
8225 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8226 | s = "sdc3"; |
df58fc94 | 8227 | fmt = "E,o(b)"; |
bdaaa2e1 | 8228 | /* Itbl support may require additional care here. */ |
252b5132 | 8229 | coproc = 1; |
df58fc94 | 8230 | goto ld_st; |
252b5132 | 8231 | case M_SDL_AB: |
df58fc94 RS |
8232 | ab = 1; |
8233 | case M_SDL_OB: | |
252b5132 | 8234 | s = "sdl"; |
df58fc94 RS |
8235 | fmt = MEM12_FMT; |
8236 | off12 = mips_opts.micromips; | |
8237 | goto ld_st; | |
252b5132 | 8238 | case M_SDR_AB: |
df58fc94 RS |
8239 | ab = 1; |
8240 | case M_SDR_OB: | |
252b5132 | 8241 | s = "sdr"; |
df58fc94 RS |
8242 | fmt = MEM12_FMT; |
8243 | off12 = mips_opts.micromips; | |
8244 | goto ld_st; | |
8245 | case M_SWP_AB: | |
8246 | ab = 1; | |
8247 | case M_SWP_OB: | |
8248 | gas_assert (mips_opts.micromips); | |
8249 | s = "swp"; | |
8250 | fmt = "t,~(b)"; | |
8251 | off12 = 1; | |
8252 | goto ld_st; | |
8253 | case M_SDP_AB: | |
8254 | ab = 1; | |
8255 | case M_SDP_OB: | |
8256 | gas_assert (mips_opts.micromips); | |
8257 | s = "sdp"; | |
8258 | fmt = "t,~(b)"; | |
8259 | off12 = 1; | |
8260 | goto ld_st; | |
8261 | case M_SWM_AB: | |
8262 | ab = 1; | |
8263 | case M_SWM_OB: | |
8264 | gas_assert (mips_opts.micromips); | |
8265 | s = "swm"; | |
8266 | fmt = "n,~(b)"; | |
8267 | off12 = 1; | |
8268 | goto ld_st; | |
8269 | case M_SDM_AB: | |
8270 | ab = 1; | |
8271 | case M_SDM_OB: | |
8272 | gas_assert (mips_opts.micromips); | |
8273 | s = "sdm"; | |
8274 | fmt = "n,~(b)"; | |
8275 | off12 = 1; | |
8276 | ||
8277 | ld_st: | |
8fc2e39e TS |
8278 | tempreg = AT; |
8279 | used_at = 1; | |
df58fc94 | 8280 | ld_noat: |
252b5132 RH |
8281 | if (offset_expr.X_op != O_constant |
8282 | && offset_expr.X_op != O_symbol) | |
8283 | { | |
f71d0d44 | 8284 | as_bad (_("Expression too complex")); |
252b5132 RH |
8285 | offset_expr.X_op = O_constant; |
8286 | } | |
8287 | ||
2051e8c4 MR |
8288 | if (HAVE_32BIT_ADDRESSES |
8289 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8290 | { |
8291 | char value [32]; | |
8292 | ||
8293 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8294 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8295 | } |
2051e8c4 | 8296 | |
252b5132 RH |
8297 | /* A constant expression in PIC code can be handled just as it |
8298 | is in non PIC code. */ | |
aed1a261 RS |
8299 | if (offset_expr.X_op == O_constant) |
8300 | { | |
df58fc94 RS |
8301 | int hipart = 0; |
8302 | ||
842f8b2a | 8303 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8304 | normalize_address_expr (&expr1); |
df58fc94 | 8305 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8306 | { |
8307 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8308 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8309 | hipart = 1; |
8310 | } | |
8311 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8312 | { | |
8313 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8314 | & ~(bfd_vma) 0xfff); | |
8315 | hipart = 1; | |
8316 | } | |
8317 | if (hipart) | |
8318 | { | |
842f8b2a MR |
8319 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8320 | if (breg != 0) | |
8321 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8322 | tempreg, tempreg, breg); | |
8323 | breg = tempreg; | |
8324 | } | |
dd6a37e7 AP |
8325 | if (off0) |
8326 | { | |
8327 | if (offset_expr.X_add_number == 0) | |
8328 | tempreg = breg; | |
8329 | else | |
8330 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8331 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8332 | macro_build (NULL, s, fmt, treg, tempreg); | |
8333 | } | |
8334 | else if (!off12) | |
df58fc94 RS |
8335 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8336 | else | |
8337 | macro_build (NULL, s, fmt, | |
8338 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8339 | } | |
dd6a37e7 | 8340 | else if (off12 || off0) |
df58fc94 | 8341 | { |
dd6a37e7 AP |
8342 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8343 | for a low-part relocation, so load the whole address into | |
8344 | the auxillary register. In the case of "A(b)" addresses, | |
8345 | we first load absolute address "A" into the register and | |
8346 | then add base register "b". In the case of "o(b)" addresses, | |
8347 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8348 | offset_reloc already contains the relocations associated |
8349 | with "o". */ | |
8350 | if (ab) | |
8351 | { | |
8352 | load_address (tempreg, &offset_expr, &used_at); | |
8353 | if (breg != 0) | |
8354 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8355 | tempreg, tempreg, breg); | |
8356 | } | |
8357 | else | |
8358 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8359 | tempreg, breg, -1, | |
8360 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8361 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8362 | if (off0) |
8363 | macro_build (NULL, s, fmt, treg, tempreg); | |
8364 | else | |
8365 | macro_build (NULL, s, fmt, | |
8366 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8367 | } |
8368 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8369 | { |
8370 | /* If this is a reference to a GP relative symbol, and there | |
8371 | is no base register, we want | |
cdf6fd85 | 8372 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8373 | Otherwise, if there is no base register, we want |
8374 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8375 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8376 | If we have a constant, we need two instructions anyhow, | |
8377 | so we always use the latter form. | |
8378 | ||
8379 | If we have a base register, and this is a reference to a | |
8380 | GP relative symbol, we want | |
8381 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8382 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8383 | Otherwise we want |
8384 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8385 | addu $tempreg,$tempreg,$breg | |
8386 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8387 | With a constant we always use the latter case. |
76b3015f | 8388 | |
d6bc6245 TS |
8389 | With 64bit address space and no base register and $at usable, |
8390 | we want | |
8391 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8392 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8393 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8394 | dsll32 $tempreg,0 | |
8395 | daddu $tempreg,$at | |
8396 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8397 | If we have a base register, we want | |
8398 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8399 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8400 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8401 | daddu $at,$breg | |
8402 | dsll32 $tempreg,0 | |
8403 | daddu $tempreg,$at | |
8404 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8405 | ||
8406 | Without $at we can't generate the optimal path for superscalar | |
8407 | processors here since this would require two temporary registers. | |
8408 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8409 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8410 | dsll $tempreg,16 | |
8411 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8412 | dsll $tempreg,16 | |
8413 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8414 | If we have a base register, we want | |
8415 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8416 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8417 | dsll $tempreg,16 | |
8418 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8419 | dsll $tempreg,16 | |
8420 | daddu $tempreg,$tempreg,$breg | |
8421 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8422 | |
6caf9ef4 | 8423 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8424 | the same sequence as in 32bit address space. */ |
8425 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8426 | { |
aed1a261 | 8427 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8428 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8429 | { | |
8430 | relax_start (offset_expr.X_add_symbol); | |
8431 | if (breg == 0) | |
8432 | { | |
8433 | macro_build (&offset_expr, s, fmt, treg, | |
8434 | BFD_RELOC_GPREL16, mips_gp_register); | |
8435 | } | |
8436 | else | |
8437 | { | |
8438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8439 | tempreg, breg, mips_gp_register); | |
8440 | macro_build (&offset_expr, s, fmt, treg, | |
8441 | BFD_RELOC_GPREL16, tempreg); | |
8442 | } | |
8443 | relax_switch (); | |
8444 | } | |
d6bc6245 | 8445 | |
741fe287 | 8446 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8447 | { |
df58fc94 | 8448 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8449 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8450 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8451 | BFD_RELOC_HI16_S); |
8452 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8453 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8454 | if (breg != 0) |
67c0d1eb | 8455 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8456 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8457 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8458 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8459 | tempreg); | |
d6bc6245 TS |
8460 | used_at = 1; |
8461 | } | |
8462 | else | |
8463 | { | |
df58fc94 | 8464 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8465 | BFD_RELOC_MIPS_HIGHEST); |
8466 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8467 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8468 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8469 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8470 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8471 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8472 | if (breg != 0) |
67c0d1eb | 8473 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8474 | tempreg, tempreg, breg); |
67c0d1eb | 8475 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8476 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8477 | } |
6caf9ef4 TS |
8478 | |
8479 | if (mips_relax.sequence) | |
8480 | relax_end (); | |
8fc2e39e | 8481 | break; |
d6bc6245 | 8482 | } |
256ab948 | 8483 | |
252b5132 RH |
8484 | if (breg == 0) |
8485 | { | |
67c0d1eb | 8486 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8487 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8488 | { |
4d7206a2 | 8489 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8490 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8491 | mips_gp_register); | |
4d7206a2 | 8492 | relax_switch (); |
252b5132 | 8493 | } |
67c0d1eb RS |
8494 | macro_build_lui (&offset_expr, tempreg); |
8495 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8496 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8497 | if (mips_relax.sequence) |
8498 | relax_end (); | |
252b5132 RH |
8499 | } |
8500 | else | |
8501 | { | |
67c0d1eb | 8502 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8503 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8504 | { |
4d7206a2 | 8505 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8506 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8507 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8508 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8509 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8510 | relax_switch (); |
252b5132 | 8511 | } |
67c0d1eb RS |
8512 | macro_build_lui (&offset_expr, tempreg); |
8513 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8514 | tempreg, tempreg, breg); |
67c0d1eb | 8515 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8516 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8517 | if (mips_relax.sequence) |
8518 | relax_end (); | |
252b5132 RH |
8519 | } |
8520 | } | |
0a44bf69 | 8521 | else if (!mips_big_got) |
252b5132 | 8522 | { |
ed6fb7bd | 8523 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8524 | |
252b5132 RH |
8525 | /* If this is a reference to an external symbol, we want |
8526 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8527 | nop | |
8528 | <op> $treg,0($tempreg) | |
8529 | Otherwise we want | |
8530 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8531 | nop | |
8532 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8533 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8534 | |
8535 | For NewABI, we want | |
8536 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8537 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8538 | ||
252b5132 RH |
8539 | If there is a base register, we add it to $tempreg before |
8540 | the <op>. If there is a constant, we stick it in the | |
8541 | <op> instruction. We don't handle constants larger than | |
8542 | 16 bits, because we have no way to load the upper 16 bits | |
8543 | (actually, we could handle them for the subset of cases | |
8544 | in which we are not using $at). */ | |
9c2799c2 | 8545 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8546 | if (HAVE_NEWABI) |
8547 | { | |
67c0d1eb RS |
8548 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8549 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8550 | if (breg != 0) |
67c0d1eb | 8551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8552 | tempreg, tempreg, breg); |
67c0d1eb | 8553 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8554 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8555 | break; |
8556 | } | |
252b5132 RH |
8557 | expr1.X_add_number = offset_expr.X_add_number; |
8558 | offset_expr.X_add_number = 0; | |
8559 | if (expr1.X_add_number < -0x8000 | |
8560 | || expr1.X_add_number >= 0x8000) | |
8561 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8563 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8564 | load_delay_nop (); |
4d7206a2 RS |
8565 | relax_start (offset_expr.X_add_symbol); |
8566 | relax_switch (); | |
67c0d1eb RS |
8567 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8568 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8569 | relax_end (); |
252b5132 | 8570 | if (breg != 0) |
67c0d1eb | 8571 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8572 | tempreg, tempreg, breg); |
67c0d1eb | 8573 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8574 | } |
0a44bf69 | 8575 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8576 | { |
67c0d1eb | 8577 | int gpdelay; |
252b5132 RH |
8578 | |
8579 | /* If this is a reference to an external symbol, we want | |
8580 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8581 | addu $tempreg,$tempreg,$gp | |
8582 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8583 | <op> $treg,0($tempreg) | |
8584 | Otherwise we want | |
8585 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8586 | nop | |
8587 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8588 | <op> $treg,0($tempreg) | |
8589 | If there is a base register, we add it to $tempreg before | |
8590 | the <op>. If there is a constant, we stick it in the | |
8591 | <op> instruction. We don't handle constants larger than | |
8592 | 16 bits, because we have no way to load the upper 16 bits | |
8593 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8594 | in which we are not using $at). */ |
9c2799c2 | 8595 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8596 | expr1.X_add_number = offset_expr.X_add_number; |
8597 | offset_expr.X_add_number = 0; | |
8598 | if (expr1.X_add_number < -0x8000 | |
8599 | || expr1.X_add_number >= 0x8000) | |
8600 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8601 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8602 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8603 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8604 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8605 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8606 | mips_gp_register); | |
8607 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8608 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8609 | relax_switch (); |
67c0d1eb RS |
8610 | if (gpdelay) |
8611 | macro_build (NULL, "nop", ""); | |
8612 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8613 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8614 | load_delay_nop (); |
67c0d1eb RS |
8615 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8616 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8617 | relax_end (); |
8618 | ||
252b5132 | 8619 | if (breg != 0) |
67c0d1eb | 8620 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8621 | tempreg, tempreg, breg); |
67c0d1eb | 8622 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8623 | } |
0a44bf69 | 8624 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8625 | { |
f5040a92 AO |
8626 | /* If this is a reference to an external symbol, we want |
8627 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8628 | add $tempreg,$tempreg,$gp | |
8629 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8630 | <op> $treg,<ofst>($tempreg) | |
8631 | Otherwise, for local symbols, we want: | |
8632 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8633 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8634 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8635 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8636 | offset_expr.X_add_number = 0; |
8637 | if (expr1.X_add_number < -0x8000 | |
8638 | || expr1.X_add_number >= 0x8000) | |
8639 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8640 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8641 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8642 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8643 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8644 | mips_gp_register); | |
8645 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8646 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8647 | if (breg != 0) |
67c0d1eb | 8648 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8649 | tempreg, tempreg, breg); |
67c0d1eb | 8650 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8651 | |
4d7206a2 | 8652 | relax_switch (); |
f5040a92 | 8653 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8654 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8655 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8656 | if (breg != 0) |
67c0d1eb | 8657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8658 | tempreg, tempreg, breg); |
67c0d1eb | 8659 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8660 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8661 | relax_end (); |
f5040a92 | 8662 | } |
252b5132 RH |
8663 | else |
8664 | abort (); | |
8665 | ||
252b5132 RH |
8666 | break; |
8667 | ||
8668 | case M_LI: | |
8669 | case M_LI_S: | |
67c0d1eb | 8670 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8671 | break; |
252b5132 RH |
8672 | |
8673 | case M_DLI: | |
67c0d1eb | 8674 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8675 | break; |
252b5132 RH |
8676 | |
8677 | case M_LI_SS: | |
8678 | if (imm_expr.X_op == O_constant) | |
8679 | { | |
8fc2e39e | 8680 | used_at = 1; |
67c0d1eb RS |
8681 | load_register (AT, &imm_expr, 0); |
8682 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8683 | break; |
8684 | } | |
8685 | else | |
8686 | { | |
9c2799c2 | 8687 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8688 | && strcmp (segment_name (S_GET_SEGMENT |
8689 | (offset_expr.X_add_symbol)), | |
8690 | ".lit4") == 0 | |
8691 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8692 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8693 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8694 | break; |
252b5132 RH |
8695 | } |
8696 | ||
8697 | case M_LI_D: | |
ca4e0257 RS |
8698 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8699 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8700 | order 32 bits of the value and the low order 32 bits are either | |
8701 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8702 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8703 | { | |
ca4e0257 | 8704 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8705 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8706 | else |
8707 | { | |
8708 | int hreg, lreg; | |
8709 | ||
8710 | if (target_big_endian) | |
8711 | { | |
8712 | hreg = treg; | |
8713 | lreg = treg + 1; | |
8714 | } | |
8715 | else | |
8716 | { | |
8717 | hreg = treg + 1; | |
8718 | lreg = treg; | |
8719 | } | |
8720 | ||
8721 | if (hreg <= 31) | |
67c0d1eb | 8722 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8723 | if (lreg <= 31) |
8724 | { | |
8725 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8726 | move_register (lreg, 0); |
252b5132 RH |
8727 | else |
8728 | { | |
9c2799c2 | 8729 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8730 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8731 | } |
8732 | } | |
8733 | } | |
8fc2e39e | 8734 | break; |
252b5132 RH |
8735 | } |
8736 | ||
8737 | /* We know that sym is in the .rdata section. First we get the | |
8738 | upper 16 bits of the address. */ | |
8739 | if (mips_pic == NO_PIC) | |
8740 | { | |
67c0d1eb | 8741 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8742 | used_at = 1; |
252b5132 | 8743 | } |
0a44bf69 | 8744 | else |
252b5132 | 8745 | { |
67c0d1eb RS |
8746 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8747 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8748 | used_at = 1; |
252b5132 | 8749 | } |
bdaaa2e1 | 8750 | |
252b5132 | 8751 | /* Now we load the register(s). */ |
ca4e0257 | 8752 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8753 | { |
8754 | used_at = 1; | |
8755 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8756 | } | |
252b5132 RH |
8757 | else |
8758 | { | |
8fc2e39e | 8759 | used_at = 1; |
67c0d1eb | 8760 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8761 | if (treg != RA) |
252b5132 RH |
8762 | { |
8763 | /* FIXME: How in the world do we deal with the possible | |
8764 | overflow here? */ | |
8765 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8766 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8767 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8768 | } |
8769 | } | |
252b5132 RH |
8770 | break; |
8771 | ||
8772 | case M_LI_DD: | |
ca4e0257 RS |
8773 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8774 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8775 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8776 | the value and the low order 32 bits are either zero or in | |
8777 | OFFSET_EXPR. */ | |
252b5132 RH |
8778 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8779 | { | |
8fc2e39e | 8780 | used_at = 1; |
67c0d1eb | 8781 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8782 | if (HAVE_64BIT_FPRS) |
8783 | { | |
9c2799c2 | 8784 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8785 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8786 | } |
252b5132 RH |
8787 | else |
8788 | { | |
67c0d1eb | 8789 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8790 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8791 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8792 | else |
8793 | { | |
9c2799c2 | 8794 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8795 | load_register (AT, &offset_expr, 0); |
8796 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8797 | } |
8798 | } | |
8799 | break; | |
8800 | } | |
8801 | ||
9c2799c2 | 8802 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8803 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8804 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8805 | if (strcmp (s, ".lit8") == 0) | |
8806 | { | |
df58fc94 | 8807 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8808 | { |
67c0d1eb | 8809 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8810 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8811 | break; |
252b5132 | 8812 | } |
c9914766 | 8813 | breg = mips_gp_register; |
252b5132 RH |
8814 | r = BFD_RELOC_MIPS_LITERAL; |
8815 | goto dob; | |
8816 | } | |
8817 | else | |
8818 | { | |
9c2799c2 | 8819 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8820 | used_at = 1; |
0a44bf69 | 8821 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8822 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8823 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8824 | else |
8825 | { | |
8826 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8827 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8828 | } |
bdaaa2e1 | 8829 | |
df58fc94 | 8830 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8831 | { |
67c0d1eb RS |
8832 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8833 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8834 | break; |
8835 | } | |
8836 | breg = AT; | |
8837 | r = BFD_RELOC_LO16; | |
8838 | goto dob; | |
8839 | } | |
8840 | ||
8841 | case M_L_DOB: | |
252b5132 RH |
8842 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8843 | to adjust when loading from memory. */ | |
8844 | r = BFD_RELOC_LO16; | |
8845 | dob: | |
df58fc94 | 8846 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8847 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8848 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8849 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8850 | /* FIXME: A possible overflow which I don't know how to deal |
8851 | with. */ | |
8852 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8853 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8854 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8855 | break; |
8856 | ||
c4a68bea | 8857 | case M_S_DOB: |
df58fc94 | 8858 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8859 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8860 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8861 | to adjust when storing to memory. */ | |
8862 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8863 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8864 | offset_expr.X_add_number += 4; | |
8865 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8866 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8867 | break; | |
8868 | ||
252b5132 | 8869 | case M_L_DAB: |
df58fc94 | 8870 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8871 | /* |
8872 | * The MIPS assembler seems to check for X_add_number not | |
8873 | * being double aligned and generating: | |
8874 | * lui at,%hi(foo+1) | |
8875 | * addu at,at,v1 | |
8876 | * addiu at,at,%lo(foo+1) | |
8877 | * lwc1 f2,0(at) | |
8878 | * lwc1 f3,4(at) | |
8879 | * But, the resulting address is the same after relocation so why | |
8880 | * generate the extra instruction? | |
8881 | */ | |
bdaaa2e1 | 8882 | /* Itbl support may require additional care here. */ |
252b5132 | 8883 | coproc = 1; |
df58fc94 | 8884 | fmt = "T,o(b)"; |
e7af610e | 8885 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8886 | { |
8887 | s = "ldc1"; | |
df58fc94 | 8888 | goto ld_st; |
252b5132 | 8889 | } |
252b5132 | 8890 | s = "lwc1"; |
252b5132 RH |
8891 | goto ldd_std; |
8892 | ||
8893 | case M_S_DAB: | |
df58fc94 RS |
8894 | gas_assert (!mips_opts.micromips); |
8895 | /* Itbl support may require additional care here. */ | |
8896 | coproc = 1; | |
8897 | fmt = "T,o(b)"; | |
e7af610e | 8898 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8899 | { |
8900 | s = "sdc1"; | |
df58fc94 | 8901 | goto ld_st; |
252b5132 | 8902 | } |
252b5132 | 8903 | s = "swc1"; |
252b5132 RH |
8904 | goto ldd_std; |
8905 | ||
8906 | case M_LD_AB: | |
df58fc94 | 8907 | fmt = "t,o(b)"; |
ca4e0257 | 8908 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8909 | { |
8910 | s = "ld"; | |
8911 | goto ld; | |
8912 | } | |
252b5132 | 8913 | s = "lw"; |
252b5132 RH |
8914 | goto ldd_std; |
8915 | ||
8916 | case M_SD_AB: | |
df58fc94 | 8917 | fmt = "t,o(b)"; |
ca4e0257 | 8918 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8919 | { |
8920 | s = "sd"; | |
df58fc94 | 8921 | goto ld_st; |
252b5132 | 8922 | } |
252b5132 | 8923 | s = "sw"; |
252b5132 RH |
8924 | |
8925 | ldd_std: | |
8926 | if (offset_expr.X_op != O_symbol | |
8927 | && offset_expr.X_op != O_constant) | |
8928 | { | |
f71d0d44 | 8929 | as_bad (_("Expression too complex")); |
252b5132 RH |
8930 | offset_expr.X_op = O_constant; |
8931 | } | |
8932 | ||
2051e8c4 MR |
8933 | if (HAVE_32BIT_ADDRESSES |
8934 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8935 | { |
8936 | char value [32]; | |
8937 | ||
8938 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8939 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8940 | } |
2051e8c4 | 8941 | |
252b5132 RH |
8942 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8943 | to adjust when loading from memory. We set coproc if we must | |
8944 | load $fn+1 first. */ | |
bdaaa2e1 | 8945 | /* Itbl support may require additional care here. */ |
90ecf173 | 8946 | if (!target_big_endian) |
252b5132 RH |
8947 | coproc = 0; |
8948 | ||
90ecf173 | 8949 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8950 | { |
8951 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8952 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8953 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8954 | If we have a base register, we use this |
8955 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8956 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8957 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8958 | If this is not a GP relative symbol, we want |
8959 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8960 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8961 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8962 | If there is a base register, we add it to $at after the | |
8963 | lui instruction. If there is a constant, we always use | |
8964 | the last case. */ | |
39a59cf8 MR |
8965 | if (offset_expr.X_op == O_symbol |
8966 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8967 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8968 | { |
4d7206a2 | 8969 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8970 | if (breg == 0) |
8971 | { | |
c9914766 | 8972 | tempreg = mips_gp_register; |
252b5132 RH |
8973 | } |
8974 | else | |
8975 | { | |
67c0d1eb | 8976 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8977 | AT, breg, mips_gp_register); |
252b5132 | 8978 | tempreg = AT; |
252b5132 RH |
8979 | used_at = 1; |
8980 | } | |
8981 | ||
beae10d5 | 8982 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8983 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8984 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8985 | offset_expr.X_add_number += 4; |
8986 | ||
8987 | /* Set mips_optimize to 2 to avoid inserting an | |
8988 | undesired nop. */ | |
8989 | hold_mips_optimize = mips_optimize; | |
8990 | mips_optimize = 2; | |
beae10d5 | 8991 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8992 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8993 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8994 | mips_optimize = hold_mips_optimize; |
8995 | ||
4d7206a2 | 8996 | relax_switch (); |
252b5132 | 8997 | |
0970e49e | 8998 | offset_expr.X_add_number -= 4; |
252b5132 | 8999 | } |
8fc2e39e | 9000 | used_at = 1; |
67c0d1eb | 9001 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9002 | if (breg != 0) |
67c0d1eb | 9003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9004 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9005 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9006 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9007 | /* FIXME: How do we handle overflow here? */ |
9008 | offset_expr.X_add_number += 4; | |
beae10d5 | 9009 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9010 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9011 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9012 | if (mips_relax.sequence) |
9013 | relax_end (); | |
bdaaa2e1 | 9014 | } |
0a44bf69 | 9015 | else if (!mips_big_got) |
252b5132 | 9016 | { |
252b5132 RH |
9017 | /* If this is a reference to an external symbol, we want |
9018 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9019 | nop | |
9020 | <op> $treg,0($at) | |
9021 | <op> $treg+1,4($at) | |
9022 | Otherwise we want | |
9023 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9024 | nop | |
9025 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9026 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9027 | If there is a base register we add it to $at before the | |
9028 | lwc1 instructions. If there is a constant we include it | |
9029 | in the lwc1 instructions. */ | |
9030 | used_at = 1; | |
9031 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9032 | if (expr1.X_add_number < -0x8000 |
9033 | || expr1.X_add_number >= 0x8000 - 4) | |
9034 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9035 | load_got_offset (AT, &offset_expr); |
269137b2 | 9036 | load_delay_nop (); |
252b5132 | 9037 | if (breg != 0) |
67c0d1eb | 9038 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9039 | |
9040 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9041 | nop. */ | |
9042 | hold_mips_optimize = mips_optimize; | |
9043 | mips_optimize = 2; | |
4d7206a2 | 9044 | |
beae10d5 | 9045 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9046 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9047 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9048 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9049 | expr1.X_add_number += 4; |
67c0d1eb RS |
9050 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9051 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9052 | relax_switch (); |
67c0d1eb RS |
9053 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9054 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9055 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9056 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9057 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9058 | relax_end (); |
252b5132 | 9059 | |
4d7206a2 | 9060 | mips_optimize = hold_mips_optimize; |
252b5132 | 9061 | } |
0a44bf69 | 9062 | else if (mips_big_got) |
252b5132 | 9063 | { |
67c0d1eb | 9064 | int gpdelay; |
252b5132 RH |
9065 | |
9066 | /* If this is a reference to an external symbol, we want | |
9067 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9068 | addu $at,$at,$gp | |
9069 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9070 | nop | |
9071 | <op> $treg,0($at) | |
9072 | <op> $treg+1,4($at) | |
9073 | Otherwise we want | |
9074 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9075 | nop | |
9076 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9077 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9078 | If there is a base register we add it to $at before the | |
9079 | lwc1 instructions. If there is a constant we include it | |
9080 | in the lwc1 instructions. */ | |
9081 | used_at = 1; | |
9082 | expr1.X_add_number = offset_expr.X_add_number; | |
9083 | offset_expr.X_add_number = 0; | |
9084 | if (expr1.X_add_number < -0x8000 | |
9085 | || expr1.X_add_number >= 0x8000 - 4) | |
9086 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9087 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9088 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9089 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9090 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9091 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9092 | AT, AT, mips_gp_register); |
67c0d1eb | 9093 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9094 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9095 | load_delay_nop (); |
252b5132 | 9096 | if (breg != 0) |
67c0d1eb | 9097 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9098 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9099 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9100 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9101 | expr1.X_add_number += 4; |
9102 | ||
9103 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9104 | nop. */ | |
9105 | hold_mips_optimize = mips_optimize; | |
9106 | mips_optimize = 2; | |
beae10d5 | 9107 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9108 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9109 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9110 | mips_optimize = hold_mips_optimize; |
9111 | expr1.X_add_number -= 4; | |
9112 | ||
4d7206a2 RS |
9113 | relax_switch (); |
9114 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9115 | if (gpdelay) |
9116 | macro_build (NULL, "nop", ""); | |
9117 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9118 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9119 | load_delay_nop (); |
252b5132 | 9120 | if (breg != 0) |
67c0d1eb | 9121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9122 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9123 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9124 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9125 | offset_expr.X_add_number += 4; |
252b5132 RH |
9126 | |
9127 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9128 | nop. */ | |
9129 | hold_mips_optimize = mips_optimize; | |
9130 | mips_optimize = 2; | |
beae10d5 | 9131 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9132 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9133 | BFD_RELOC_LO16, AT); | |
252b5132 | 9134 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9135 | relax_end (); |
252b5132 | 9136 | } |
252b5132 RH |
9137 | else |
9138 | abort (); | |
9139 | ||
252b5132 RH |
9140 | break; |
9141 | ||
9142 | case M_LD_OB: | |
704897fb | 9143 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9144 | goto sd_ob; |
9145 | case M_SD_OB: | |
704897fb | 9146 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9147 | sd_ob: |
4614d845 MR |
9148 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9149 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9150 | breg); | |
704897fb MR |
9151 | if (!HAVE_64BIT_GPRS) |
9152 | { | |
9153 | offset_expr.X_add_number += 4; | |
9154 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9155 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9156 | breg); | |
704897fb | 9157 | } |
8fc2e39e | 9158 | break; |
252b5132 | 9159 | |
dd6a37e7 AP |
9160 | |
9161 | case M_SAA_AB: | |
9162 | ab = 1; | |
9163 | case M_SAA_OB: | |
9164 | s = "saa"; | |
9165 | off0 = 1; | |
9166 | fmt = "t,(b)"; | |
9167 | goto ld_st; | |
9168 | case M_SAAD_AB: | |
9169 | ab = 1; | |
9170 | case M_SAAD_OB: | |
9171 | s = "saad"; | |
9172 | off0 = 1; | |
9173 | fmt = "t,(b)"; | |
9174 | goto ld_st; | |
9175 | ||
252b5132 RH |
9176 | /* New code added to support COPZ instructions. |
9177 | This code builds table entries out of the macros in mip_opcodes. | |
9178 | R4000 uses interlocks to handle coproc delays. | |
9179 | Other chips (like the R3000) require nops to be inserted for delays. | |
9180 | ||
f72c8c98 | 9181 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9182 | In order to fill delay slots for non-interlocked chips, |
9183 | we must have a way to specify delays based on the coprocessor. | |
9184 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9185 | What are the side-effects of the cop instruction? | |
9186 | What cache support might we have and what are its effects? | |
9187 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9188 | What registers are read/set/modified? |
252b5132 RH |
9189 | |
9190 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9191 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9192 | |
9193 | case M_COP0: | |
9194 | s = "c0"; | |
9195 | goto copz; | |
9196 | case M_COP1: | |
9197 | s = "c1"; | |
9198 | goto copz; | |
9199 | case M_COP2: | |
9200 | s = "c2"; | |
9201 | goto copz; | |
9202 | case M_COP3: | |
9203 | s = "c3"; | |
9204 | copz: | |
df58fc94 | 9205 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9206 | /* For now we just do C (same as Cz). The parameter will be |
9207 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9208 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9209 | break; |
252b5132 | 9210 | |
ea1fb5dc | 9211 | case M_MOVE: |
67c0d1eb | 9212 | move_register (dreg, sreg); |
8fc2e39e | 9213 | break; |
ea1fb5dc | 9214 | |
252b5132 RH |
9215 | case M_DMUL: |
9216 | dbl = 1; | |
9217 | case M_MUL: | |
67c0d1eb | 9218 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9219 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9220 | break; |
252b5132 RH |
9221 | |
9222 | case M_DMUL_I: | |
9223 | dbl = 1; | |
9224 | case M_MUL_I: | |
9225 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9226 | not trying to be that fancy. GCC should do this for us | |
9227 | anyway. */ | |
8fc2e39e | 9228 | used_at = 1; |
67c0d1eb RS |
9229 | load_register (AT, &imm_expr, dbl); |
9230 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9231 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9232 | break; |
9233 | ||
9234 | case M_DMULO_I: | |
9235 | dbl = 1; | |
9236 | case M_MULO_I: | |
9237 | imm = 1; | |
9238 | goto do_mulo; | |
9239 | ||
9240 | case M_DMULO: | |
9241 | dbl = 1; | |
9242 | case M_MULO: | |
9243 | do_mulo: | |
7d10b47d | 9244 | start_noreorder (); |
8fc2e39e | 9245 | used_at = 1; |
252b5132 | 9246 | if (imm) |
67c0d1eb RS |
9247 | load_register (AT, &imm_expr, dbl); |
9248 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9249 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9250 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9251 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9252 | if (mips_trap) |
df58fc94 | 9253 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9254 | else |
9255 | { | |
df58fc94 RS |
9256 | if (mips_opts.micromips) |
9257 | micromips_label_expr (&label_expr); | |
9258 | else | |
9259 | label_expr.X_add_number = 8; | |
9260 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9261 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9262 | macro_build (NULL, "break", BRK_FMT, 6); |
9263 | if (mips_opts.micromips) | |
9264 | micromips_add_label (); | |
252b5132 | 9265 | } |
7d10b47d | 9266 | end_noreorder (); |
df58fc94 | 9267 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9268 | break; |
9269 | ||
9270 | case M_DMULOU_I: | |
9271 | dbl = 1; | |
9272 | case M_MULOU_I: | |
9273 | imm = 1; | |
9274 | goto do_mulou; | |
9275 | ||
9276 | case M_DMULOU: | |
9277 | dbl = 1; | |
9278 | case M_MULOU: | |
9279 | do_mulou: | |
7d10b47d | 9280 | start_noreorder (); |
8fc2e39e | 9281 | used_at = 1; |
252b5132 | 9282 | if (imm) |
67c0d1eb RS |
9283 | load_register (AT, &imm_expr, dbl); |
9284 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9285 | sreg, imm ? AT : treg); |
df58fc94 RS |
9286 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9287 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9288 | if (mips_trap) |
df58fc94 | 9289 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9290 | else |
9291 | { | |
df58fc94 RS |
9292 | if (mips_opts.micromips) |
9293 | micromips_label_expr (&label_expr); | |
9294 | else | |
9295 | label_expr.X_add_number = 8; | |
9296 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9297 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9298 | macro_build (NULL, "break", BRK_FMT, 6); |
9299 | if (mips_opts.micromips) | |
9300 | micromips_add_label (); | |
252b5132 | 9301 | } |
7d10b47d | 9302 | end_noreorder (); |
252b5132 RH |
9303 | break; |
9304 | ||
771c7ce4 | 9305 | case M_DROL: |
fef14a42 | 9306 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9307 | { |
9308 | if (dreg == sreg) | |
9309 | { | |
9310 | tempreg = AT; | |
9311 | used_at = 1; | |
9312 | } | |
9313 | else | |
9314 | { | |
9315 | tempreg = dreg; | |
82dd0097 | 9316 | } |
67c0d1eb RS |
9317 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9318 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9319 | break; |
82dd0097 | 9320 | } |
8fc2e39e | 9321 | used_at = 1; |
c80c840e | 9322 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9323 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9324 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9325 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9326 | break; |
9327 | ||
252b5132 | 9328 | case M_ROL: |
fef14a42 | 9329 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9330 | { |
9331 | if (dreg == sreg) | |
9332 | { | |
9333 | tempreg = AT; | |
9334 | used_at = 1; | |
9335 | } | |
9336 | else | |
9337 | { | |
9338 | tempreg = dreg; | |
82dd0097 | 9339 | } |
67c0d1eb RS |
9340 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9341 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9342 | break; |
82dd0097 | 9343 | } |
8fc2e39e | 9344 | used_at = 1; |
c80c840e | 9345 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9346 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9347 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9348 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9349 | break; |
9350 | ||
771c7ce4 TS |
9351 | case M_DROL_I: |
9352 | { | |
9353 | unsigned int rot; | |
91d6fa6a NC |
9354 | char *l; |
9355 | char *rr; | |
771c7ce4 TS |
9356 | |
9357 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9358 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9359 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9360 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9361 | { |
9362 | rot = (64 - rot) & 0x3f; | |
9363 | if (rot >= 32) | |
df58fc94 | 9364 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9365 | else |
df58fc94 | 9366 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9367 | break; |
60b63b72 | 9368 | } |
483fc7cd | 9369 | if (rot == 0) |
483fc7cd | 9370 | { |
df58fc94 | 9371 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9372 | break; |
483fc7cd | 9373 | } |
82dd0097 | 9374 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9375 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9376 | rot &= 0x1f; |
8fc2e39e | 9377 | used_at = 1; |
df58fc94 RS |
9378 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9379 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9380 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9381 | } |
9382 | break; | |
9383 | ||
252b5132 | 9384 | case M_ROL_I: |
771c7ce4 TS |
9385 | { |
9386 | unsigned int rot; | |
9387 | ||
9388 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9389 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9390 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9391 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9392 | { |
df58fc94 | 9393 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9394 | break; |
60b63b72 | 9395 | } |
483fc7cd | 9396 | if (rot == 0) |
483fc7cd | 9397 | { |
df58fc94 | 9398 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9399 | break; |
483fc7cd | 9400 | } |
8fc2e39e | 9401 | used_at = 1; |
df58fc94 RS |
9402 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9403 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9404 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9405 | } |
9406 | break; | |
9407 | ||
9408 | case M_DROR: | |
fef14a42 | 9409 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9410 | { |
67c0d1eb | 9411 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9412 | break; |
82dd0097 | 9413 | } |
8fc2e39e | 9414 | used_at = 1; |
c80c840e | 9415 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9416 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9417 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9418 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9419 | break; |
9420 | ||
9421 | case M_ROR: | |
fef14a42 | 9422 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9423 | { |
67c0d1eb | 9424 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9425 | break; |
82dd0097 | 9426 | } |
8fc2e39e | 9427 | used_at = 1; |
c80c840e | 9428 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9429 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9430 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9431 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9432 | break; |
9433 | ||
771c7ce4 TS |
9434 | case M_DROR_I: |
9435 | { | |
9436 | unsigned int rot; | |
91d6fa6a NC |
9437 | char *l; |
9438 | char *rr; | |
771c7ce4 TS |
9439 | |
9440 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9441 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9442 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9443 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9444 | { |
9445 | if (rot >= 32) | |
df58fc94 | 9446 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9447 | else |
df58fc94 | 9448 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9449 | break; |
82dd0097 | 9450 | } |
483fc7cd | 9451 | if (rot == 0) |
483fc7cd | 9452 | { |
df58fc94 | 9453 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9454 | break; |
483fc7cd | 9455 | } |
91d6fa6a | 9456 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9457 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9458 | rot &= 0x1f; | |
8fc2e39e | 9459 | used_at = 1; |
df58fc94 RS |
9460 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9461 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9462 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9463 | } |
9464 | break; | |
9465 | ||
252b5132 | 9466 | case M_ROR_I: |
771c7ce4 TS |
9467 | { |
9468 | unsigned int rot; | |
9469 | ||
9470 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9471 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9472 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9473 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9474 | { |
df58fc94 | 9475 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9476 | break; |
82dd0097 | 9477 | } |
483fc7cd | 9478 | if (rot == 0) |
483fc7cd | 9479 | { |
df58fc94 | 9480 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9481 | break; |
483fc7cd | 9482 | } |
8fc2e39e | 9483 | used_at = 1; |
df58fc94 RS |
9484 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9485 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9486 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9487 | } |
252b5132 RH |
9488 | break; |
9489 | ||
252b5132 RH |
9490 | case M_SEQ: |
9491 | if (sreg == 0) | |
67c0d1eb | 9492 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9493 | else if (treg == 0) |
67c0d1eb | 9494 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9495 | else |
9496 | { | |
67c0d1eb RS |
9497 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9498 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9499 | } |
8fc2e39e | 9500 | break; |
252b5132 RH |
9501 | |
9502 | case M_SEQ_I: | |
9503 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9504 | { | |
67c0d1eb | 9505 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9506 | break; |
252b5132 RH |
9507 | } |
9508 | if (sreg == 0) | |
9509 | { | |
9510 | as_warn (_("Instruction %s: result is always false"), | |
9511 | ip->insn_mo->name); | |
67c0d1eb | 9512 | move_register (dreg, 0); |
8fc2e39e | 9513 | break; |
252b5132 | 9514 | } |
dd3cbb7e NC |
9515 | if (CPU_HAS_SEQ (mips_opts.arch) |
9516 | && -512 <= imm_expr.X_add_number | |
9517 | && imm_expr.X_add_number < 512) | |
9518 | { | |
9519 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9520 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9521 | break; |
9522 | } | |
252b5132 RH |
9523 | if (imm_expr.X_op == O_constant |
9524 | && imm_expr.X_add_number >= 0 | |
9525 | && imm_expr.X_add_number < 0x10000) | |
9526 | { | |
67c0d1eb | 9527 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9528 | } |
9529 | else if (imm_expr.X_op == O_constant | |
9530 | && imm_expr.X_add_number > -0x8000 | |
9531 | && imm_expr.X_add_number < 0) | |
9532 | { | |
9533 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9534 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9535 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9536 | } |
dd3cbb7e NC |
9537 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9538 | { | |
9539 | used_at = 1; | |
9540 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9541 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9542 | break; | |
9543 | } | |
252b5132 RH |
9544 | else |
9545 | { | |
67c0d1eb RS |
9546 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9547 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9548 | used_at = 1; |
9549 | } | |
67c0d1eb | 9550 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9551 | break; |
252b5132 RH |
9552 | |
9553 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9554 | s = "slt"; | |
9555 | goto sge; | |
9556 | case M_SGEU: | |
9557 | s = "sltu"; | |
9558 | sge: | |
67c0d1eb RS |
9559 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9560 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9561 | break; |
252b5132 RH |
9562 | |
9563 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9564 | case M_SGEU_I: | |
9565 | if (imm_expr.X_op == O_constant | |
9566 | && imm_expr.X_add_number >= -0x8000 | |
9567 | && imm_expr.X_add_number < 0x8000) | |
9568 | { | |
67c0d1eb RS |
9569 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9570 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9571 | } |
9572 | else | |
9573 | { | |
67c0d1eb RS |
9574 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9575 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9576 | dreg, sreg, AT); | |
252b5132 RH |
9577 | used_at = 1; |
9578 | } | |
67c0d1eb | 9579 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9580 | break; |
252b5132 RH |
9581 | |
9582 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9583 | s = "slt"; | |
9584 | goto sgt; | |
9585 | case M_SGTU: | |
9586 | s = "sltu"; | |
9587 | sgt: | |
67c0d1eb | 9588 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9589 | break; |
252b5132 RH |
9590 | |
9591 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9592 | s = "slt"; | |
9593 | goto sgti; | |
9594 | case M_SGTU_I: | |
9595 | s = "sltu"; | |
9596 | sgti: | |
8fc2e39e | 9597 | used_at = 1; |
67c0d1eb RS |
9598 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9599 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9600 | break; |
9601 | ||
2396cfb9 | 9602 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9603 | s = "slt"; |
9604 | goto sle; | |
9605 | case M_SLEU: | |
9606 | s = "sltu"; | |
9607 | sle: | |
67c0d1eb RS |
9608 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9609 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9610 | break; |
252b5132 | 9611 | |
2396cfb9 | 9612 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9613 | s = "slt"; |
9614 | goto slei; | |
9615 | case M_SLEU_I: | |
9616 | s = "sltu"; | |
9617 | slei: | |
8fc2e39e | 9618 | used_at = 1; |
67c0d1eb RS |
9619 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9620 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9621 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9622 | break; |
9623 | ||
9624 | case M_SLT_I: | |
9625 | if (imm_expr.X_op == O_constant | |
9626 | && imm_expr.X_add_number >= -0x8000 | |
9627 | && imm_expr.X_add_number < 0x8000) | |
9628 | { | |
67c0d1eb | 9629 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9630 | break; |
252b5132 | 9631 | } |
8fc2e39e | 9632 | used_at = 1; |
67c0d1eb RS |
9633 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9634 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9635 | break; |
9636 | ||
9637 | case M_SLTU_I: | |
9638 | if (imm_expr.X_op == O_constant | |
9639 | && imm_expr.X_add_number >= -0x8000 | |
9640 | && imm_expr.X_add_number < 0x8000) | |
9641 | { | |
67c0d1eb | 9642 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9643 | BFD_RELOC_LO16); |
8fc2e39e | 9644 | break; |
252b5132 | 9645 | } |
8fc2e39e | 9646 | used_at = 1; |
67c0d1eb RS |
9647 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9648 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9649 | break; |
9650 | ||
9651 | case M_SNE: | |
9652 | if (sreg == 0) | |
67c0d1eb | 9653 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9654 | else if (treg == 0) |
67c0d1eb | 9655 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9656 | else |
9657 | { | |
67c0d1eb RS |
9658 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9659 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9660 | } |
8fc2e39e | 9661 | break; |
252b5132 RH |
9662 | |
9663 | case M_SNE_I: | |
9664 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9665 | { | |
67c0d1eb | 9666 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9667 | break; |
252b5132 RH |
9668 | } |
9669 | if (sreg == 0) | |
9670 | { | |
9671 | as_warn (_("Instruction %s: result is always true"), | |
9672 | ip->insn_mo->name); | |
67c0d1eb RS |
9673 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9674 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9675 | break; |
252b5132 | 9676 | } |
dd3cbb7e NC |
9677 | if (CPU_HAS_SEQ (mips_opts.arch) |
9678 | && -512 <= imm_expr.X_add_number | |
9679 | && imm_expr.X_add_number < 512) | |
9680 | { | |
9681 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9682 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9683 | break; |
9684 | } | |
252b5132 RH |
9685 | if (imm_expr.X_op == O_constant |
9686 | && imm_expr.X_add_number >= 0 | |
9687 | && imm_expr.X_add_number < 0x10000) | |
9688 | { | |
67c0d1eb | 9689 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9690 | } |
9691 | else if (imm_expr.X_op == O_constant | |
9692 | && imm_expr.X_add_number > -0x8000 | |
9693 | && imm_expr.X_add_number < 0) | |
9694 | { | |
9695 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9696 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9697 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9698 | } |
dd3cbb7e NC |
9699 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9700 | { | |
9701 | used_at = 1; | |
9702 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9703 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9704 | break; | |
9705 | } | |
252b5132 RH |
9706 | else |
9707 | { | |
67c0d1eb RS |
9708 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9709 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9710 | used_at = 1; |
9711 | } | |
67c0d1eb | 9712 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9713 | break; |
252b5132 | 9714 | |
df58fc94 RS |
9715 | case M_SUB_I: |
9716 | s = "addi"; | |
9717 | s2 = "sub"; | |
9718 | goto do_subi; | |
9719 | case M_SUBU_I: | |
9720 | s = "addiu"; | |
9721 | s2 = "subu"; | |
9722 | goto do_subi; | |
252b5132 RH |
9723 | case M_DSUB_I: |
9724 | dbl = 1; | |
df58fc94 RS |
9725 | s = "daddi"; |
9726 | s2 = "dsub"; | |
9727 | if (!mips_opts.micromips) | |
9728 | goto do_subi; | |
252b5132 | 9729 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9730 | && imm_expr.X_add_number > -0x200 |
9731 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9732 | { |
df58fc94 | 9733 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9734 | break; |
252b5132 | 9735 | } |
df58fc94 | 9736 | goto do_subi_i; |
252b5132 RH |
9737 | case M_DSUBU_I: |
9738 | dbl = 1; | |
df58fc94 RS |
9739 | s = "daddiu"; |
9740 | s2 = "dsubu"; | |
9741 | do_subi: | |
252b5132 RH |
9742 | if (imm_expr.X_op == O_constant |
9743 | && imm_expr.X_add_number > -0x8000 | |
9744 | && imm_expr.X_add_number <= 0x8000) | |
9745 | { | |
9746 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9747 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9748 | break; |
252b5132 | 9749 | } |
df58fc94 | 9750 | do_subi_i: |
8fc2e39e | 9751 | used_at = 1; |
67c0d1eb | 9752 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9753 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9754 | break; |
9755 | ||
9756 | case M_TEQ_I: | |
9757 | s = "teq"; | |
9758 | goto trap; | |
9759 | case M_TGE_I: | |
9760 | s = "tge"; | |
9761 | goto trap; | |
9762 | case M_TGEU_I: | |
9763 | s = "tgeu"; | |
9764 | goto trap; | |
9765 | case M_TLT_I: | |
9766 | s = "tlt"; | |
9767 | goto trap; | |
9768 | case M_TLTU_I: | |
9769 | s = "tltu"; | |
9770 | goto trap; | |
9771 | case M_TNE_I: | |
9772 | s = "tne"; | |
9773 | trap: | |
8fc2e39e | 9774 | used_at = 1; |
67c0d1eb RS |
9775 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9776 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9777 | break; |
9778 | ||
252b5132 | 9779 | case M_TRUNCWS: |
43841e91 | 9780 | case M_TRUNCWD: |
df58fc94 | 9781 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9782 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9783 | used_at = 1; |
252b5132 RH |
9784 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9785 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9786 | ||
9787 | /* | |
9788 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9789 | * or is there a reason for it? | |
9790 | */ | |
7d10b47d | 9791 | start_noreorder (); |
67c0d1eb RS |
9792 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9793 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9794 | macro_build (NULL, "nop", ""); | |
252b5132 | 9795 | expr1.X_add_number = 3; |
67c0d1eb | 9796 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9797 | expr1.X_add_number = 2; |
67c0d1eb RS |
9798 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9799 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9800 | macro_build (NULL, "nop", ""); | |
9801 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9802 | dreg, sreg); | |
9803 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9804 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9805 | end_noreorder (); |
252b5132 RH |
9806 | break; |
9807 | ||
df58fc94 RS |
9808 | case M_ULH_A: |
9809 | ab = 1; | |
252b5132 RH |
9810 | case M_ULH: |
9811 | s = "lb"; | |
df58fc94 RS |
9812 | s2 = "lbu"; |
9813 | off = 1; | |
9814 | goto uld_st; | |
9815 | case M_ULHU_A: | |
9816 | ab = 1; | |
252b5132 RH |
9817 | case M_ULHU: |
9818 | s = "lbu"; | |
df58fc94 RS |
9819 | s2 = "lbu"; |
9820 | off = 1; | |
9821 | goto uld_st; | |
9822 | case M_ULW_A: | |
9823 | ab = 1; | |
9824 | case M_ULW: | |
9825 | s = "lwl"; | |
9826 | s2 = "lwr"; | |
9827 | off12 = mips_opts.micromips; | |
9828 | off = 3; | |
9829 | goto uld_st; | |
9830 | case M_ULD_A: | |
9831 | ab = 1; | |
252b5132 RH |
9832 | case M_ULD: |
9833 | s = "ldl"; | |
9834 | s2 = "ldr"; | |
df58fc94 | 9835 | off12 = mips_opts.micromips; |
252b5132 | 9836 | off = 7; |
df58fc94 RS |
9837 | goto uld_st; |
9838 | case M_USH_A: | |
9839 | ab = 1; | |
9840 | case M_USH: | |
9841 | s = "sb"; | |
9842 | s2 = "sb"; | |
9843 | off = 1; | |
9844 | ust = 1; | |
9845 | goto uld_st; | |
9846 | case M_USW_A: | |
9847 | ab = 1; | |
9848 | case M_USW: | |
9849 | s = "swl"; | |
9850 | s2 = "swr"; | |
9851 | off12 = mips_opts.micromips; | |
252b5132 | 9852 | off = 3; |
df58fc94 RS |
9853 | ust = 1; |
9854 | goto uld_st; | |
9855 | case M_USD_A: | |
9856 | ab = 1; | |
9857 | case M_USD: | |
9858 | s = "sdl"; | |
9859 | s2 = "sdr"; | |
9860 | off12 = mips_opts.micromips; | |
9861 | off = 7; | |
9862 | ust = 1; | |
9863 | ||
9864 | uld_st: | |
9865 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9866 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9867 | |
9868 | ep = &offset_expr; | |
9869 | expr1.X_add_number = 0; | |
9870 | if (ab) | |
9871 | { | |
9872 | used_at = 1; | |
9873 | tempreg = AT; | |
9874 | load_address (tempreg, ep, &used_at); | |
9875 | if (breg != 0) | |
9876 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9877 | tempreg, tempreg, breg); | |
9878 | breg = tempreg; | |
9879 | tempreg = treg; | |
9880 | ep = &expr1; | |
9881 | } | |
9882 | else if (off12 | |
9883 | && (offset_expr.X_op != O_constant | |
9884 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9885 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9886 | { | |
9887 | used_at = 1; | |
9888 | tempreg = AT; | |
9889 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9890 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9891 | breg = tempreg; | |
9892 | tempreg = treg; | |
9893 | ep = &expr1; | |
9894 | } | |
9895 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9896 | { |
9897 | used_at = 1; | |
9898 | tempreg = AT; | |
9899 | } | |
252b5132 | 9900 | else |
df58fc94 | 9901 | tempreg = treg; |
af22f5b2 | 9902 | |
df58fc94 RS |
9903 | if (off == 1) |
9904 | goto ulh_sh; | |
252b5132 | 9905 | |
90ecf173 | 9906 | if (!target_big_endian) |
df58fc94 RS |
9907 | ep->X_add_number += off; |
9908 | if (!off12) | |
9909 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9910 | else |
df58fc94 RS |
9911 | macro_build (NULL, s, "t,~(b)", |
9912 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9913 | ||
90ecf173 | 9914 | if (!target_big_endian) |
df58fc94 | 9915 | ep->X_add_number -= off; |
252b5132 | 9916 | else |
df58fc94 RS |
9917 | ep->X_add_number += off; |
9918 | if (!off12) | |
9919 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9920 | else | |
9921 | macro_build (NULL, s2, "t,~(b)", | |
9922 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9923 | |
df58fc94 RS |
9924 | /* If necessary, move the result in tempreg to the final destination. */ |
9925 | if (!ust && treg != tempreg) | |
9926 | { | |
9927 | /* Protect second load's delay slot. */ | |
9928 | load_delay_nop (); | |
9929 | move_register (treg, tempreg); | |
9930 | } | |
8fc2e39e | 9931 | break; |
252b5132 | 9932 | |
df58fc94 | 9933 | ulh_sh: |
d6bc6245 | 9934 | used_at = 1; |
df58fc94 RS |
9935 | if (target_big_endian == ust) |
9936 | ep->X_add_number += off; | |
9937 | tempreg = ust || ab ? treg : AT; | |
9938 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9939 | ||
9940 | /* For halfword transfers we need a temporary register to shuffle | |
9941 | bytes. Unfortunately for M_USH_A we have none available before | |
9942 | the next store as AT holds the base address. We deal with this | |
9943 | case by clobbering TREG and then restoring it as with ULH. */ | |
9944 | tempreg = ust == ab ? treg : AT; | |
9945 | if (ust) | |
9946 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9947 | ||
9948 | if (target_big_endian == ust) | |
9949 | ep->X_add_number -= off; | |
252b5132 | 9950 | else |
df58fc94 RS |
9951 | ep->X_add_number += off; |
9952 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9953 | |
df58fc94 RS |
9954 | /* For M_USH_A re-retrieve the LSB. */ |
9955 | if (ust && ab) | |
9956 | { | |
9957 | if (target_big_endian) | |
9958 | ep->X_add_number += off; | |
9959 | else | |
9960 | ep->X_add_number -= off; | |
9961 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9962 | } | |
9963 | /* For ULH and M_USH_A OR the LSB in. */ | |
9964 | if (!ust || ab) | |
9965 | { | |
9966 | tempreg = !ab ? AT : treg; | |
9967 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9968 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9969 | } | |
252b5132 RH |
9970 | break; |
9971 | ||
9972 | default: | |
9973 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9974 | are added dynamically. */ |
252b5132 RH |
9975 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9976 | break; | |
9977 | } | |
741fe287 | 9978 | if (!mips_opts.at && used_at) |
8fc2e39e | 9979 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9980 | } |
9981 | ||
9982 | /* Implement macros in mips16 mode. */ | |
9983 | ||
9984 | static void | |
17a2f251 | 9985 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9986 | { |
9987 | int mask; | |
9988 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9989 | expressionS expr1; |
9990 | int dbl; | |
9991 | const char *s, *s2, *s3; | |
9992 | ||
9993 | mask = ip->insn_mo->mask; | |
9994 | ||
bf12938e RS |
9995 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9996 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9997 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9998 | |
252b5132 RH |
9999 | expr1.X_op = O_constant; |
10000 | expr1.X_op_symbol = NULL; | |
10001 | expr1.X_add_symbol = NULL; | |
10002 | expr1.X_add_number = 1; | |
10003 | ||
10004 | dbl = 0; | |
10005 | ||
10006 | switch (mask) | |
10007 | { | |
10008 | default: | |
10009 | internalError (); | |
10010 | ||
10011 | case M_DDIV_3: | |
10012 | dbl = 1; | |
10013 | case M_DIV_3: | |
10014 | s = "mflo"; | |
10015 | goto do_div3; | |
10016 | case M_DREM_3: | |
10017 | dbl = 1; | |
10018 | case M_REM_3: | |
10019 | s = "mfhi"; | |
10020 | do_div3: | |
7d10b47d | 10021 | start_noreorder (); |
67c0d1eb | 10022 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10023 | expr1.X_add_number = 2; |
67c0d1eb RS |
10024 | macro_build (&expr1, "bnez", "x,p", yreg); |
10025 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10026 | |
252b5132 RH |
10027 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10028 | since that causes an overflow. We should do that as well, | |
10029 | but I don't see how to do the comparisons without a temporary | |
10030 | register. */ | |
7d10b47d | 10031 | end_noreorder (); |
67c0d1eb | 10032 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10033 | break; |
10034 | ||
10035 | case M_DIVU_3: | |
10036 | s = "divu"; | |
10037 | s2 = "mflo"; | |
10038 | goto do_divu3; | |
10039 | case M_REMU_3: | |
10040 | s = "divu"; | |
10041 | s2 = "mfhi"; | |
10042 | goto do_divu3; | |
10043 | case M_DDIVU_3: | |
10044 | s = "ddivu"; | |
10045 | s2 = "mflo"; | |
10046 | goto do_divu3; | |
10047 | case M_DREMU_3: | |
10048 | s = "ddivu"; | |
10049 | s2 = "mfhi"; | |
10050 | do_divu3: | |
7d10b47d | 10051 | start_noreorder (); |
67c0d1eb | 10052 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10053 | expr1.X_add_number = 2; |
67c0d1eb RS |
10054 | macro_build (&expr1, "bnez", "x,p", yreg); |
10055 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10056 | end_noreorder (); |
67c0d1eb | 10057 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10058 | break; |
10059 | ||
10060 | case M_DMUL: | |
10061 | dbl = 1; | |
10062 | case M_MUL: | |
67c0d1eb RS |
10063 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10064 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10065 | break; |
252b5132 RH |
10066 | |
10067 | case M_DSUBU_I: | |
10068 | dbl = 1; | |
10069 | goto do_subu; | |
10070 | case M_SUBU_I: | |
10071 | do_subu: | |
10072 | if (imm_expr.X_op != O_constant) | |
10073 | as_bad (_("Unsupported large constant")); | |
10074 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10075 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10076 | break; |
10077 | ||
10078 | case M_SUBU_I_2: | |
10079 | if (imm_expr.X_op != O_constant) | |
10080 | as_bad (_("Unsupported large constant")); | |
10081 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10082 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10083 | break; |
10084 | ||
10085 | case M_DSUBU_I_2: | |
10086 | if (imm_expr.X_op != O_constant) | |
10087 | as_bad (_("Unsupported large constant")); | |
10088 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10089 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10090 | break; |
10091 | ||
10092 | case M_BEQ: | |
10093 | s = "cmp"; | |
10094 | s2 = "bteqz"; | |
10095 | goto do_branch; | |
10096 | case M_BNE: | |
10097 | s = "cmp"; | |
10098 | s2 = "btnez"; | |
10099 | goto do_branch; | |
10100 | case M_BLT: | |
10101 | s = "slt"; | |
10102 | s2 = "btnez"; | |
10103 | goto do_branch; | |
10104 | case M_BLTU: | |
10105 | s = "sltu"; | |
10106 | s2 = "btnez"; | |
10107 | goto do_branch; | |
10108 | case M_BLE: | |
10109 | s = "slt"; | |
10110 | s2 = "bteqz"; | |
10111 | goto do_reverse_branch; | |
10112 | case M_BLEU: | |
10113 | s = "sltu"; | |
10114 | s2 = "bteqz"; | |
10115 | goto do_reverse_branch; | |
10116 | case M_BGE: | |
10117 | s = "slt"; | |
10118 | s2 = "bteqz"; | |
10119 | goto do_branch; | |
10120 | case M_BGEU: | |
10121 | s = "sltu"; | |
10122 | s2 = "bteqz"; | |
10123 | goto do_branch; | |
10124 | case M_BGT: | |
10125 | s = "slt"; | |
10126 | s2 = "btnez"; | |
10127 | goto do_reverse_branch; | |
10128 | case M_BGTU: | |
10129 | s = "sltu"; | |
10130 | s2 = "btnez"; | |
10131 | ||
10132 | do_reverse_branch: | |
10133 | tmp = xreg; | |
10134 | xreg = yreg; | |
10135 | yreg = tmp; | |
10136 | ||
10137 | do_branch: | |
67c0d1eb RS |
10138 | macro_build (NULL, s, "x,y", xreg, yreg); |
10139 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10140 | break; |
10141 | ||
10142 | case M_BEQ_I: | |
10143 | s = "cmpi"; | |
10144 | s2 = "bteqz"; | |
10145 | s3 = "x,U"; | |
10146 | goto do_branch_i; | |
10147 | case M_BNE_I: | |
10148 | s = "cmpi"; | |
10149 | s2 = "btnez"; | |
10150 | s3 = "x,U"; | |
10151 | goto do_branch_i; | |
10152 | case M_BLT_I: | |
10153 | s = "slti"; | |
10154 | s2 = "btnez"; | |
10155 | s3 = "x,8"; | |
10156 | goto do_branch_i; | |
10157 | case M_BLTU_I: | |
10158 | s = "sltiu"; | |
10159 | s2 = "btnez"; | |
10160 | s3 = "x,8"; | |
10161 | goto do_branch_i; | |
10162 | case M_BLE_I: | |
10163 | s = "slti"; | |
10164 | s2 = "btnez"; | |
10165 | s3 = "x,8"; | |
10166 | goto do_addone_branch_i; | |
10167 | case M_BLEU_I: | |
10168 | s = "sltiu"; | |
10169 | s2 = "btnez"; | |
10170 | s3 = "x,8"; | |
10171 | goto do_addone_branch_i; | |
10172 | case M_BGE_I: | |
10173 | s = "slti"; | |
10174 | s2 = "bteqz"; | |
10175 | s3 = "x,8"; | |
10176 | goto do_branch_i; | |
10177 | case M_BGEU_I: | |
10178 | s = "sltiu"; | |
10179 | s2 = "bteqz"; | |
10180 | s3 = "x,8"; | |
10181 | goto do_branch_i; | |
10182 | case M_BGT_I: | |
10183 | s = "slti"; | |
10184 | s2 = "bteqz"; | |
10185 | s3 = "x,8"; | |
10186 | goto do_addone_branch_i; | |
10187 | case M_BGTU_I: | |
10188 | s = "sltiu"; | |
10189 | s2 = "bteqz"; | |
10190 | s3 = "x,8"; | |
10191 | ||
10192 | do_addone_branch_i: | |
10193 | if (imm_expr.X_op != O_constant) | |
10194 | as_bad (_("Unsupported large constant")); | |
10195 | ++imm_expr.X_add_number; | |
10196 | ||
10197 | do_branch_i: | |
67c0d1eb RS |
10198 | macro_build (&imm_expr, s, s3, xreg); |
10199 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10200 | break; |
10201 | ||
10202 | case M_ABS: | |
10203 | expr1.X_add_number = 0; | |
67c0d1eb | 10204 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10205 | if (xreg != yreg) |
67c0d1eb | 10206 | move_register (xreg, yreg); |
252b5132 | 10207 | expr1.X_add_number = 2; |
67c0d1eb RS |
10208 | macro_build (&expr1, "bteqz", "p"); |
10209 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10210 | } |
10211 | } | |
10212 | ||
10213 | /* For consistency checking, verify that all bits are specified either | |
10214 | by the match/mask part of the instruction definition, or by the | |
10215 | operand list. */ | |
10216 | static int | |
17a2f251 | 10217 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10218 | { |
10219 | const char *p = opc->args; | |
10220 | char c; | |
10221 | unsigned long used_bits = opc->mask; | |
10222 | ||
10223 | if ((used_bits & opc->match) != opc->match) | |
10224 | { | |
10225 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10226 | opc->name, opc->args); | |
10227 | return 0; | |
10228 | } | |
10229 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10230 | while (*p) | |
10231 | switch (c = *p++) | |
10232 | { | |
10233 | case ',': break; | |
10234 | case '(': break; | |
10235 | case ')': break; | |
af7ee8bf CD |
10236 | case '+': |
10237 | switch (c = *p++) | |
10238 | { | |
9bcd4f99 TS |
10239 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10240 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10241 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10242 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10243 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10244 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10245 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10246 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10247 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10248 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10249 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10250 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10251 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10252 | case 'I': break; | |
ef2e4d86 CF |
10253 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10254 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10255 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10256 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10257 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10258 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10259 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10260 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10261 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10262 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10263 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10264 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10265 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10266 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10267 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10268 | |
af7ee8bf CD |
10269 | default: |
10270 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10271 | c, opc->name, opc->args); | |
10272 | return 0; | |
10273 | } | |
10274 | break; | |
252b5132 RH |
10275 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10276 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10277 | case 'A': break; | |
4372b673 | 10278 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10279 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10280 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10281 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10282 | case 'F': break; | |
10283 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10284 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10285 | case 'I': break; |
e972090a | 10286 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10287 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10288 | case 'L': break; |
10289 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10290 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10291 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10292 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10293 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10294 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10295 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10296 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10297 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10298 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10299 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10300 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10301 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10302 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10303 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10304 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10305 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10306 | case 'f': break; | |
10307 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10308 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10309 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10310 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10311 | case 'l': break; | |
10312 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10313 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10314 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10315 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10316 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10317 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10318 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10319 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10320 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10321 | case 'x': break; | |
10322 | case 'z': break; | |
10323 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10324 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10325 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10326 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10327 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10328 | case '[': break; | |
10329 | case ']': break; | |
620edafd | 10330 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10331 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10332 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10333 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10334 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10335 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10336 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10337 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10338 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10339 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10340 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10341 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10342 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10343 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10344 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10345 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10346 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10347 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10348 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10349 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10350 | default: |
10351 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10352 | c, opc->name, opc->args); | |
10353 | return 0; | |
10354 | } | |
10355 | #undef USE_BITS | |
10356 | if (used_bits != 0xffffffff) | |
10357 | { | |
10358 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10359 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10360 | return 0; | |
10361 | } | |
10362 | return 1; | |
10363 | } | |
10364 | ||
df58fc94 RS |
10365 | /* For consistency checking, verify that the length implied matches the |
10366 | major opcode and that all bits are specified either by the match/mask | |
10367 | part of the instruction definition, or by the operand list. */ | |
10368 | ||
10369 | static int | |
10370 | validate_micromips_insn (const struct mips_opcode *opc) | |
10371 | { | |
10372 | unsigned long match = opc->match; | |
10373 | unsigned long mask = opc->mask; | |
10374 | const char *p = opc->args; | |
10375 | unsigned long insn_bits; | |
10376 | unsigned long used_bits; | |
10377 | unsigned long major; | |
10378 | unsigned int length; | |
10379 | char e; | |
10380 | char c; | |
10381 | ||
10382 | if ((mask & match) != match) | |
10383 | { | |
10384 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10385 | opc->name, opc->args); | |
10386 | return 0; | |
10387 | } | |
10388 | length = micromips_insn_length (opc); | |
10389 | if (length != 2 && length != 4) | |
10390 | { | |
10391 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10392 | "%s %s"), length, opc->name, opc->args); | |
10393 | return 0; | |
10394 | } | |
10395 | major = match >> (10 + 8 * (length - 2)); | |
10396 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10397 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10398 | { | |
10399 | as_bad (_("Internal error: bad microMIPS opcode " | |
10400 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10401 | return 0; | |
10402 | } | |
10403 | ||
10404 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10405 | insn_bits = 1 << 4 * length; | |
10406 | insn_bits <<= 4 * length; | |
10407 | insn_bits -= 1; | |
10408 | used_bits = mask; | |
10409 | #define USE_BITS(field) \ | |
10410 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10411 | while (*p) | |
10412 | switch (c = *p++) | |
10413 | { | |
10414 | case ',': break; | |
10415 | case '(': break; | |
10416 | case ')': break; | |
10417 | case '+': | |
10418 | e = c; | |
10419 | switch (c = *p++) | |
10420 | { | |
10421 | case 'A': USE_BITS (EXTLSB); break; | |
10422 | case 'B': USE_BITS (INSMSB); break; | |
10423 | case 'C': USE_BITS (EXTMSBD); break; | |
10424 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10425 | case 'E': USE_BITS (EXTLSB); break; | |
10426 | case 'F': USE_BITS (INSMSB); break; | |
10427 | case 'G': USE_BITS (EXTMSBD); break; | |
10428 | case 'H': USE_BITS (EXTMSBD); break; | |
10429 | default: | |
10430 | as_bad (_("Internal error: bad mips opcode " | |
10431 | "(unknown extension operand type `%c%c'): %s %s"), | |
10432 | e, c, opc->name, opc->args); | |
10433 | return 0; | |
10434 | } | |
10435 | break; | |
10436 | case 'm': | |
10437 | e = c; | |
10438 | switch (c = *p++) | |
10439 | { | |
10440 | case 'A': USE_BITS (IMMA); break; | |
10441 | case 'B': USE_BITS (IMMB); break; | |
10442 | case 'C': USE_BITS (IMMC); break; | |
10443 | case 'D': USE_BITS (IMMD); break; | |
10444 | case 'E': USE_BITS (IMME); break; | |
10445 | case 'F': USE_BITS (IMMF); break; | |
10446 | case 'G': USE_BITS (IMMG); break; | |
10447 | case 'H': USE_BITS (IMMH); break; | |
10448 | case 'I': USE_BITS (IMMI); break; | |
10449 | case 'J': USE_BITS (IMMJ); break; | |
10450 | case 'L': USE_BITS (IMML); break; | |
10451 | case 'M': USE_BITS (IMMM); break; | |
10452 | case 'N': USE_BITS (IMMN); break; | |
10453 | case 'O': USE_BITS (IMMO); break; | |
10454 | case 'P': USE_BITS (IMMP); break; | |
10455 | case 'Q': USE_BITS (IMMQ); break; | |
10456 | case 'U': USE_BITS (IMMU); break; | |
10457 | case 'W': USE_BITS (IMMW); break; | |
10458 | case 'X': USE_BITS (IMMX); break; | |
10459 | case 'Y': USE_BITS (IMMY); break; | |
10460 | case 'Z': break; | |
10461 | case 'a': break; | |
10462 | case 'b': USE_BITS (MB); break; | |
10463 | case 'c': USE_BITS (MC); break; | |
10464 | case 'd': USE_BITS (MD); break; | |
10465 | case 'e': USE_BITS (ME); break; | |
10466 | case 'f': USE_BITS (MF); break; | |
10467 | case 'g': USE_BITS (MG); break; | |
10468 | case 'h': USE_BITS (MH); break; | |
10469 | case 'i': USE_BITS (MI); break; | |
10470 | case 'j': USE_BITS (MJ); break; | |
10471 | case 'l': USE_BITS (ML); break; | |
10472 | case 'm': USE_BITS (MM); break; | |
10473 | case 'n': USE_BITS (MN); break; | |
10474 | case 'p': USE_BITS (MP); break; | |
10475 | case 'q': USE_BITS (MQ); break; | |
10476 | case 'r': break; | |
10477 | case 's': break; | |
10478 | case 't': break; | |
10479 | case 'x': break; | |
10480 | case 'y': break; | |
10481 | case 'z': break; | |
10482 | default: | |
10483 | as_bad (_("Internal error: bad mips opcode " | |
10484 | "(unknown extension operand type `%c%c'): %s %s"), | |
10485 | e, c, opc->name, opc->args); | |
10486 | return 0; | |
10487 | } | |
10488 | break; | |
10489 | case '.': USE_BITS (OFFSET10); break; | |
10490 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
10491 | case '2': USE_BITS (BP); break; |
10492 | case '3': USE_BITS (SA3); break; | |
10493 | case '4': USE_BITS (SA4); break; | |
10494 | case '5': USE_BITS (IMM8); break; | |
10495 | case '6': USE_BITS (RS); break; | |
10496 | case '7': USE_BITS (DSPACC); break; | |
10497 | case '8': USE_BITS (WRDSP); break; | |
10498 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
10499 | case '<': USE_BITS (SHAMT); break; |
10500 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 10501 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
10502 | case 'B': USE_BITS (CODE10); break; |
10503 | case 'C': USE_BITS (COPZ); break; | |
10504 | case 'D': USE_BITS (FD); break; | |
10505 | case 'E': USE_BITS (RT); break; | |
10506 | case 'G': USE_BITS (RS); break; | |
444d75be | 10507 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10508 | case 'K': USE_BITS (RS); break; |
10509 | case 'M': USE_BITS (CCC); break; | |
10510 | case 'N': USE_BITS (BCC); break; | |
10511 | case 'R': USE_BITS (FR); break; | |
10512 | case 'S': USE_BITS (FS); break; | |
10513 | case 'T': USE_BITS (FT); break; | |
10514 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10515 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 10516 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
10517 | case 'a': USE_BITS (TARGET); break; |
10518 | case 'b': USE_BITS (RS); break; | |
10519 | case 'c': USE_BITS (CODE); break; | |
10520 | case 'd': USE_BITS (RD); break; | |
10521 | case 'h': USE_BITS (PREFX); break; | |
10522 | case 'i': USE_BITS (IMMEDIATE); break; | |
10523 | case 'j': USE_BITS (DELTA); break; | |
10524 | case 'k': USE_BITS (CACHE); break; | |
10525 | case 'n': USE_BITS (RT); break; | |
10526 | case 'o': USE_BITS (DELTA); break; | |
10527 | case 'p': USE_BITS (DELTA); break; | |
10528 | case 'q': USE_BITS (CODE2); break; | |
10529 | case 'r': USE_BITS (RS); break; | |
10530 | case 's': USE_BITS (RS); break; | |
10531 | case 't': USE_BITS (RT); break; | |
10532 | case 'u': USE_BITS (IMMEDIATE); break; | |
10533 | case 'v': USE_BITS (RS); break; | |
10534 | case 'w': USE_BITS (RT); break; | |
10535 | case 'y': USE_BITS (RS3); break; | |
10536 | case 'z': break; | |
10537 | case '|': USE_BITS (TRAP); break; | |
10538 | case '~': USE_BITS (OFFSET12); break; | |
10539 | default: | |
10540 | as_bad (_("Internal error: bad microMIPS opcode " | |
10541 | "(unknown operand type `%c'): %s %s"), | |
10542 | c, opc->name, opc->args); | |
10543 | return 0; | |
10544 | } | |
10545 | #undef USE_BITS | |
10546 | if (used_bits != insn_bits) | |
10547 | { | |
10548 | if (~used_bits & insn_bits) | |
10549 | as_bad (_("Internal error: bad microMIPS opcode " | |
10550 | "(bits 0x%lx undefined): %s %s"), | |
10551 | ~used_bits & insn_bits, opc->name, opc->args); | |
10552 | if (used_bits & ~insn_bits) | |
10553 | as_bad (_("Internal error: bad microMIPS opcode " | |
10554 | "(bits 0x%lx defined): %s %s"), | |
10555 | used_bits & ~insn_bits, opc->name, opc->args); | |
10556 | return 0; | |
10557 | } | |
10558 | return 1; | |
10559 | } | |
10560 | ||
9bcd4f99 TS |
10561 | /* UDI immediates. */ |
10562 | struct mips_immed { | |
10563 | char type; | |
10564 | unsigned int shift; | |
10565 | unsigned long mask; | |
10566 | const char * desc; | |
10567 | }; | |
10568 | ||
10569 | static const struct mips_immed mips_immed[] = { | |
10570 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10571 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10572 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10573 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10574 | { 0,0,0,0 } | |
10575 | }; | |
10576 | ||
7455baf8 TS |
10577 | /* Check whether an odd floating-point register is allowed. */ |
10578 | static int | |
10579 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10580 | { | |
10581 | const char *s = insn->name; | |
10582 | ||
10583 | if (insn->pinfo == INSN_MACRO) | |
10584 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10585 | return 1; | |
10586 | ||
10587 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10588 | { | |
10589 | /* Allow odd registers for single-precision ops. */ | |
10590 | switch (insn->pinfo & (FP_S | FP_D)) | |
10591 | { | |
10592 | case FP_S: | |
10593 | case 0: | |
10594 | return 1; /* both single precision - ok */ | |
10595 | case FP_D: | |
10596 | return 0; /* both double precision - fail */ | |
10597 | default: | |
10598 | break; | |
10599 | } | |
10600 | ||
10601 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10602 | s = strchr (insn->name, '.'); | |
10603 | if (argnum == 2) | |
10604 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10605 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10606 | } | |
10607 | ||
10608 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10609 | if ((insn->pinfo & FP_S) | |
10610 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10611 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10612 | return 1; | |
10613 | ||
10614 | return 0; | |
10615 | } | |
10616 | ||
df58fc94 RS |
10617 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10618 | taking bits from BIT up. */ | |
10619 | static int | |
10620 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10621 | { | |
10622 | return (ep->X_op == O_constant | |
10623 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10624 | && ep->X_add_number >= min << bit | |
10625 | && ep->X_add_number < max << bit); | |
10626 | } | |
10627 | ||
252b5132 RH |
10628 | /* This routine assembles an instruction into its binary format. As a |
10629 | side effect, it sets one of the global variables imm_reloc or | |
10630 | offset_reloc to the type of relocation to do if one of the operands | |
10631 | is an address expression. */ | |
10632 | ||
10633 | static void | |
17a2f251 | 10634 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10635 | { |
df58fc94 RS |
10636 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10637 | bfd_boolean need_delay_slot_ok = TRUE; | |
10638 | struct mips_opcode *firstinsn = NULL; | |
10639 | const struct mips_opcode *past; | |
10640 | struct hash_control *hash; | |
252b5132 RH |
10641 | char *s; |
10642 | const char *args; | |
43841e91 | 10643 | char c = 0; |
252b5132 RH |
10644 | struct mips_opcode *insn; |
10645 | char *argsStart; | |
10646 | unsigned int regno; | |
34224acf | 10647 | unsigned int lastregno; |
df58fc94 | 10648 | unsigned int destregno = 0; |
af7ee8bf | 10649 | unsigned int lastpos = 0; |
071742cf | 10650 | unsigned int limlo, limhi; |
252b5132 | 10651 | char *s_reset; |
74cd071d | 10652 | offsetT min_range, max_range; |
df58fc94 | 10653 | long opend; |
a40bc9dd | 10654 | char *name; |
707bfff6 TS |
10655 | int argnum; |
10656 | unsigned int rtype; | |
df58fc94 | 10657 | char *dot; |
a40bc9dd | 10658 | long end; |
252b5132 RH |
10659 | |
10660 | insn_error = NULL; | |
10661 | ||
df58fc94 RS |
10662 | if (mips_opts.micromips) |
10663 | { | |
10664 | hash = micromips_op_hash; | |
10665 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10666 | } | |
10667 | else | |
10668 | { | |
10669 | hash = op_hash; | |
10670 | past = &mips_opcodes[NUMOPCODES]; | |
10671 | } | |
10672 | forced_insn_length = 0; | |
252b5132 | 10673 | insn = NULL; |
252b5132 | 10674 | |
df58fc94 | 10675 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10676 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10677 | continue; | |
bdaaa2e1 | 10678 | |
a40bc9dd RS |
10679 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10680 | name = alloca (end + 1); | |
10681 | memcpy (name, str, end); | |
10682 | name[end] = '\0'; | |
252b5132 | 10683 | |
df58fc94 RS |
10684 | for (;;) |
10685 | { | |
10686 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10687 | ||
10688 | if (insn != NULL || !mips_opts.micromips) | |
10689 | break; | |
10690 | if (forced_insn_length) | |
10691 | break; | |
10692 | ||
10693 | /* See if there's an instruction size override suffix, | |
10694 | either `16' or `32', at the end of the mnemonic proper, | |
10695 | that defines the operation, i.e. before the first `.' | |
10696 | character if any. Strip it and retry. */ | |
10697 | dot = strchr (name, '.'); | |
10698 | opend = dot != NULL ? dot - name : end; | |
10699 | if (opend < 3) | |
10700 | break; | |
10701 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10702 | forced_insn_length = 2; | |
10703 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10704 | forced_insn_length = 4; | |
10705 | else | |
10706 | break; | |
10707 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10708 | } | |
252b5132 RH |
10709 | if (insn == NULL) |
10710 | { | |
a40bc9dd RS |
10711 | insn_error = _("Unrecognized opcode"); |
10712 | return; | |
252b5132 RH |
10713 | } |
10714 | ||
df58fc94 RS |
10715 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10716 | we make up to two passes over the relevant fragment of the opcode | |
10717 | table. First we try instructions that meet the delay slot's length | |
10718 | requirement. If none matched, then we retry with the remaining ones | |
10719 | and if one matches, then we use it and then issue an appropriate | |
10720 | warning later on. */ | |
a40bc9dd | 10721 | argsStart = s = str + end; |
252b5132 RH |
10722 | for (;;) |
10723 | { | |
df58fc94 RS |
10724 | bfd_boolean delay_slot_ok; |
10725 | bfd_boolean size_ok; | |
b34976b6 | 10726 | bfd_boolean ok; |
252b5132 | 10727 | |
a40bc9dd | 10728 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10729 | |
f79e2745 | 10730 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10731 | size_ok = is_size_valid (insn); |
10732 | delay_slot_ok = is_delay_slot_valid (insn); | |
10733 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10734 | { |
df58fc94 RS |
10735 | firstinsn = insn; |
10736 | wrong_delay_slot_insns = TRUE; | |
10737 | } | |
10738 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10739 | { | |
10740 | static char buf[256]; | |
10741 | ||
10742 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10743 | { |
10744 | ++insn; | |
10745 | continue; | |
10746 | } | |
df58fc94 | 10747 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10748 | { |
df58fc94 RS |
10749 | gas_assert (firstinsn); |
10750 | need_delay_slot_ok = FALSE; | |
10751 | past = insn + 1; | |
10752 | insn = firstinsn; | |
10753 | continue; | |
252b5132 | 10754 | } |
df58fc94 RS |
10755 | |
10756 | if (insn_error) | |
10757 | return; | |
10758 | ||
10759 | if (!ok) | |
7bd942df | 10760 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10761 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10762 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10763 | else | |
10764 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10765 | 8 * forced_insn_length); | |
10766 | insn_error = buf; | |
10767 | ||
10768 | return; | |
252b5132 RH |
10769 | } |
10770 | ||
1e915849 | 10771 | create_insn (ip, insn); |
268f6bed | 10772 | insn_error = NULL; |
707bfff6 | 10773 | argnum = 1; |
24864476 | 10774 | lastregno = 0xffffffff; |
252b5132 RH |
10775 | for (args = insn->args;; ++args) |
10776 | { | |
deec1734 CD |
10777 | int is_mdmx; |
10778 | ||
ad8d3bb3 | 10779 | s += strspn (s, " \t"); |
deec1734 | 10780 | is_mdmx = 0; |
252b5132 RH |
10781 | switch (*args) |
10782 | { | |
10783 | case '\0': /* end of args */ | |
10784 | if (*s == '\0') | |
10785 | return; | |
10786 | break; | |
10787 | ||
03f66e8a MR |
10788 | case '2': |
10789 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
10790 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
10791 | my_getExpression (&imm_expr, s); |
10792 | check_absolute_expr (ip, &imm_expr); | |
10793 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10794 | && (unsigned long) imm_expr.X_add_number != 3) | |
10795 | { | |
10796 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10797 | (unsigned long) imm_expr.X_add_number); | |
10798 | } | |
03f66e8a MR |
10799 | INSERT_OPERAND (mips_opts.micromips, |
10800 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
10801 | imm_expr.X_op = O_absent; |
10802 | s = expr_end; | |
10803 | continue; | |
10804 | ||
03f66e8a MR |
10805 | case '3': |
10806 | /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS | |
10807 | code) or 21 (for microMIPS code). */ | |
10808 | { | |
10809 | unsigned long mask = (mips_opts.micromips | |
10810 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
10811 | ||
10812 | my_getExpression (&imm_expr, s); | |
10813 | check_absolute_expr (ip, &imm_expr); | |
10814 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10815 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10816 | mask, (unsigned long) imm_expr.X_add_number); | |
10817 | INSERT_OPERAND (mips_opts.micromips, | |
10818 | SA3, *ip, imm_expr.X_add_number); | |
10819 | imm_expr.X_op = O_absent; | |
10820 | s = expr_end; | |
10821 | } | |
74cd071d CF |
10822 | continue; |
10823 | ||
03f66e8a MR |
10824 | case '4': |
10825 | /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS | |
10826 | code) or 21 (for microMIPS code). */ | |
10827 | { | |
10828 | unsigned long mask = (mips_opts.micromips | |
10829 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
10830 | ||
10831 | my_getExpression (&imm_expr, s); | |
10832 | check_absolute_expr (ip, &imm_expr); | |
10833 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10834 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10835 | mask, (unsigned long) imm_expr.X_add_number); | |
10836 | INSERT_OPERAND (mips_opts.micromips, | |
10837 | SA4, *ip, imm_expr.X_add_number); | |
10838 | imm_expr.X_op = O_absent; | |
10839 | s = expr_end; | |
10840 | } | |
74cd071d CF |
10841 | continue; |
10842 | ||
03f66e8a MR |
10843 | case '5': |
10844 | /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS | |
10845 | code) or 16 (for microMIPS code). */ | |
10846 | { | |
10847 | unsigned long mask = (mips_opts.micromips | |
10848 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
10849 | ||
10850 | my_getExpression (&imm_expr, s); | |
10851 | check_absolute_expr (ip, &imm_expr); | |
10852 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10853 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10854 | mask, (unsigned long) imm_expr.X_add_number); | |
10855 | INSERT_OPERAND (mips_opts.micromips, | |
10856 | IMM8, *ip, imm_expr.X_add_number); | |
10857 | imm_expr.X_op = O_absent; | |
10858 | s = expr_end; | |
10859 | } | |
74cd071d CF |
10860 | continue; |
10861 | ||
03f66e8a MR |
10862 | case '6': |
10863 | /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS | |
10864 | code) or 21 (for microMIPS code). */ | |
10865 | { | |
10866 | unsigned long mask = (mips_opts.micromips | |
10867 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
10868 | ||
10869 | my_getExpression (&imm_expr, s); | |
10870 | check_absolute_expr (ip, &imm_expr); | |
10871 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10872 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10873 | mask, (unsigned long) imm_expr.X_add_number); | |
10874 | INSERT_OPERAND (mips_opts.micromips, | |
10875 | RS, *ip, imm_expr.X_add_number); | |
10876 | imm_expr.X_op = O_absent; | |
10877 | s = expr_end; | |
10878 | } | |
74cd071d CF |
10879 | continue; |
10880 | ||
90ecf173 | 10881 | case '7': /* Four DSP accumulators in bits 11,12. */ |
03f66e8a MR |
10882 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
10883 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
10884 | { |
10885 | regno = s[3] - '0'; | |
10886 | s += 4; | |
03f66e8a | 10887 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
10888 | continue; |
10889 | } | |
10890 | else | |
10891 | as_bad (_("Invalid dsp acc register")); | |
10892 | break; | |
10893 | ||
03f66e8a MR |
10894 | case '8': |
10895 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
10896 | code) or 14 (for microMIPS code). */ | |
10897 | { | |
10898 | unsigned long mask = (mips_opts.micromips | |
10899 | ? MICROMIPSOP_MASK_WRDSP | |
10900 | : OP_MASK_WRDSP); | |
10901 | ||
10902 | my_getExpression (&imm_expr, s); | |
10903 | check_absolute_expr (ip, &imm_expr); | |
10904 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10905 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
10906 | mask, (unsigned long) imm_expr.X_add_number); | |
10907 | INSERT_OPERAND (mips_opts.micromips, | |
10908 | WRDSP, *ip, imm_expr.X_add_number); | |
10909 | imm_expr.X_op = O_absent; | |
10910 | s = expr_end; | |
10911 | } | |
74cd071d CF |
10912 | continue; |
10913 | ||
90ecf173 | 10914 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10915 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
10916 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
10917 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
10918 | { |
10919 | regno = s[3] - '0'; | |
10920 | s += 4; | |
df58fc94 | 10921 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10922 | continue; |
10923 | } | |
10924 | else | |
10925 | as_bad (_("Invalid dsp acc register")); | |
10926 | break; | |
10927 | ||
03f66e8a MR |
10928 | case '0': |
10929 | /* DSP 6-bit signed immediate in bit 16 (for standard MIPS | |
10930 | code) or 20 (for microMIPS code). */ | |
10931 | { | |
10932 | long mask = (mips_opts.micromips | |
10933 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
10934 | ||
10935 | my_getExpression (&imm_expr, s); | |
10936 | check_absolute_expr (ip, &imm_expr); | |
10937 | min_range = -((mask + 1) >> 1); | |
10938 | max_range = ((mask + 1) >> 1) - 1; | |
10939 | if (imm_expr.X_add_number < min_range | |
10940 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
10941 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10942 | (long) min_range, (long) max_range, | |
10943 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
10944 | INSERT_OPERAND (mips_opts.micromips, |
10945 | DSPSFT, *ip, imm_expr.X_add_number); | |
10946 | imm_expr.X_op = O_absent; | |
10947 | s = expr_end; | |
10948 | } | |
74cd071d CF |
10949 | continue; |
10950 | ||
90ecf173 | 10951 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10952 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10953 | my_getExpression (&imm_expr, s); |
10954 | check_absolute_expr (ip, &imm_expr); | |
10955 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10956 | { | |
a9e24354 TS |
10957 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10958 | OP_MASK_RDDSP, | |
10959 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10960 | } |
df58fc94 | 10961 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10962 | imm_expr.X_op = O_absent; |
10963 | s = expr_end; | |
10964 | continue; | |
10965 | ||
90ecf173 | 10966 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10967 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10968 | my_getExpression (&imm_expr, s); |
10969 | check_absolute_expr (ip, &imm_expr); | |
10970 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10971 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10972 | if (imm_expr.X_add_number < min_range || | |
10973 | imm_expr.X_add_number > max_range) | |
10974 | { | |
a9e24354 TS |
10975 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10976 | (long) min_range, (long) max_range, | |
10977 | (long) imm_expr.X_add_number); | |
74cd071d | 10978 | } |
df58fc94 | 10979 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10980 | imm_expr.X_op = O_absent; |
10981 | s = expr_end; | |
10982 | continue; | |
10983 | ||
90ecf173 | 10984 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
10985 | { |
10986 | long mask = (mips_opts.micromips | |
10987 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
10988 | ||
10989 | my_getExpression (&imm_expr, s); | |
10990 | check_absolute_expr (ip, &imm_expr); | |
10991 | min_range = -((mask + 1) >> 1); | |
10992 | max_range = ((mask + 1) >> 1) - 1; | |
10993 | if (imm_expr.X_add_number < min_range | |
10994 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
10995 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10996 | (long) min_range, (long) max_range, | |
10997 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
10998 | INSERT_OPERAND (mips_opts.micromips, |
10999 | IMM10, *ip, imm_expr.X_add_number); | |
11000 | imm_expr.X_op = O_absent; | |
11001 | s = expr_end; | |
11002 | } | |
11003 | continue; | |
11004 | ||
11005 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11006 | gas_assert (mips_opts.micromips); | |
11007 | my_getExpression (&imm_expr, s); | |
11008 | check_absolute_expr (ip, &imm_expr); | |
11009 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11010 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11011 | MICROMIPSOP_MASK_RD, | |
11012 | (unsigned long) imm_expr.X_add_number); | |
11013 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11014 | imm_expr.X_op = O_absent; |
11015 | s = expr_end; | |
11016 | continue; | |
11017 | ||
a9e24354 | 11018 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11019 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11020 | my_getExpression (&imm_expr, s); |
11021 | check_absolute_expr (ip, &imm_expr); | |
11022 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11023 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11024 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11025 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11026 | imm_expr.X_op = O_absent; |
11027 | s = expr_end; | |
11028 | continue; | |
11029 | ||
a9e24354 | 11030 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11031 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11032 | my_getExpression (&imm_expr, s); |
11033 | check_absolute_expr (ip, &imm_expr); | |
11034 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11035 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11036 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11037 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11038 | imm_expr.X_op = O_absent; |
11039 | s = expr_end; | |
11040 | continue; | |
11041 | ||
90ecf173 | 11042 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11043 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11044 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11045 | s[3] >= '0' && s[3] <= '3') | |
11046 | { | |
11047 | regno = s[3] - '0'; | |
11048 | s += 4; | |
df58fc94 | 11049 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11050 | continue; |
11051 | } | |
11052 | else | |
11053 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11054 | break; | |
11055 | ||
90ecf173 | 11056 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11057 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11058 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11059 | s[3] >= '0' && s[3] <= '3') | |
11060 | { | |
11061 | regno = s[3] - '0'; | |
11062 | s += 4; | |
df58fc94 | 11063 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11064 | continue; |
11065 | } | |
11066 | else | |
11067 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11068 | break; | |
11069 | ||
dec0624d MR |
11070 | case '\\': /* 3-bit bit position. */ |
11071 | { | |
2906b037 MR |
11072 | unsigned long mask = (mips_opts.micromips |
11073 | ? MICROMIPSOP_MASK_3BITPOS | |
11074 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11075 | |
11076 | my_getExpression (&imm_expr, s); | |
11077 | check_absolute_expr (ip, &imm_expr); | |
11078 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11079 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11080 | ip->insn_mo->name, | |
11081 | mask, (unsigned long) imm_expr.X_add_number); | |
11082 | INSERT_OPERAND (mips_opts.micromips, | |
11083 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11084 | imm_expr.X_op = O_absent; | |
11085 | s = expr_end; | |
11086 | } | |
11087 | continue; | |
11088 | ||
252b5132 | 11089 | case ',': |
a339155f | 11090 | ++argnum; |
252b5132 RH |
11091 | if (*s++ == *args) |
11092 | continue; | |
11093 | s--; | |
11094 | switch (*++args) | |
11095 | { | |
11096 | case 'r': | |
11097 | case 'v': | |
df58fc94 | 11098 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11099 | continue; |
11100 | ||
11101 | case 'w': | |
df58fc94 | 11102 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11103 | continue; |
11104 | ||
252b5132 | 11105 | case 'W': |
df58fc94 RS |
11106 | gas_assert (!mips_opts.micromips); |
11107 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11108 | continue; |
11109 | ||
11110 | case 'V': | |
df58fc94 | 11111 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11112 | continue; |
11113 | } | |
11114 | break; | |
11115 | ||
11116 | case '(': | |
11117 | /* Handle optional base register. | |
11118 | Either the base register is omitted or | |
bdaaa2e1 | 11119 | we must have a left paren. */ |
252b5132 RH |
11120 | /* This is dependent on the next operand specifier |
11121 | is a base register specification. */ | |
df58fc94 RS |
11122 | gas_assert (args[1] == 'b' |
11123 | || (mips_opts.micromips | |
11124 | && args[1] == 'm' | |
11125 | && (args[2] == 'l' || args[2] == 'n' | |
11126 | || args[2] == 's' || args[2] == 'a'))); | |
11127 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11128 | return; |
df58fc94 | 11129 | /* Fall through. */ |
252b5132 | 11130 | |
90ecf173 | 11131 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11132 | if (*s++ == *args) |
11133 | continue; | |
11134 | break; | |
11135 | ||
11136 | case '[': /* These must match exactly. */ | |
60b63b72 | 11137 | case ']': |
df58fc94 | 11138 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11139 | if (*s++ == *args) |
11140 | continue; | |
11141 | break; | |
11142 | ||
af7ee8bf CD |
11143 | case '+': /* Opcode extension character. */ |
11144 | switch (*++args) | |
11145 | { | |
9bcd4f99 TS |
11146 | case '1': /* UDI immediates. */ |
11147 | case '2': | |
11148 | case '3': | |
11149 | case '4': | |
df58fc94 | 11150 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11151 | { |
11152 | const struct mips_immed *imm = mips_immed; | |
11153 | ||
11154 | while (imm->type && imm->type != *args) | |
11155 | ++imm; | |
11156 | if (! imm->type) | |
11157 | internalError (); | |
11158 | my_getExpression (&imm_expr, s); | |
11159 | check_absolute_expr (ip, &imm_expr); | |
11160 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11161 | { | |
11162 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11163 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11164 | (unsigned long) imm_expr.X_add_number, | |
11165 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11166 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11167 | } |
11168 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11169 | << imm->shift); | |
11170 | imm_expr.X_op = O_absent; | |
11171 | s = expr_end; | |
11172 | } | |
11173 | continue; | |
90ecf173 | 11174 | |
071742cf CD |
11175 | case 'A': /* ins/ext position, becomes LSB. */ |
11176 | limlo = 0; | |
11177 | limhi = 31; | |
5f74bc13 CD |
11178 | goto do_lsb; |
11179 | case 'E': | |
11180 | limlo = 32; | |
11181 | limhi = 63; | |
11182 | goto do_lsb; | |
90ecf173 | 11183 | do_lsb: |
071742cf CD |
11184 | my_getExpression (&imm_expr, s); |
11185 | check_absolute_expr (ip, &imm_expr); | |
11186 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11187 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11188 | { | |
11189 | as_bad (_("Improper position (%lu)"), | |
11190 | (unsigned long) imm_expr.X_add_number); | |
11191 | imm_expr.X_add_number = limlo; | |
11192 | } | |
11193 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11194 | INSERT_OPERAND (mips_opts.micromips, |
11195 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11196 | imm_expr.X_op = O_absent; |
11197 | s = expr_end; | |
11198 | continue; | |
11199 | ||
11200 | case 'B': /* ins size, becomes MSB. */ | |
11201 | limlo = 1; | |
11202 | limhi = 32; | |
5f74bc13 CD |
11203 | goto do_msb; |
11204 | case 'F': | |
11205 | limlo = 33; | |
11206 | limhi = 64; | |
11207 | goto do_msb; | |
90ecf173 | 11208 | do_msb: |
071742cf CD |
11209 | my_getExpression (&imm_expr, s); |
11210 | check_absolute_expr (ip, &imm_expr); | |
11211 | /* Check for negative input so that small negative numbers | |
11212 | will not succeed incorrectly. The checks against | |
11213 | (pos+size) transitively check "size" itself, | |
11214 | assuming that "pos" is reasonable. */ | |
11215 | if ((long) imm_expr.X_add_number < 0 | |
11216 | || ((unsigned long) imm_expr.X_add_number | |
11217 | + lastpos) < limlo | |
11218 | || ((unsigned long) imm_expr.X_add_number | |
11219 | + lastpos) > limhi) | |
11220 | { | |
11221 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11222 | (unsigned long) imm_expr.X_add_number, | |
11223 | (unsigned long) lastpos); | |
11224 | imm_expr.X_add_number = limlo - lastpos; | |
11225 | } | |
df58fc94 RS |
11226 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11227 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11228 | imm_expr.X_op = O_absent; |
11229 | s = expr_end; | |
11230 | continue; | |
11231 | ||
11232 | case 'C': /* ext size, becomes MSBD. */ | |
11233 | limlo = 1; | |
11234 | limhi = 32; | |
5f74bc13 CD |
11235 | goto do_msbd; |
11236 | case 'G': | |
11237 | limlo = 33; | |
11238 | limhi = 64; | |
11239 | goto do_msbd; | |
11240 | case 'H': | |
11241 | limlo = 33; | |
11242 | limhi = 64; | |
11243 | goto do_msbd; | |
90ecf173 | 11244 | do_msbd: |
071742cf CD |
11245 | my_getExpression (&imm_expr, s); |
11246 | check_absolute_expr (ip, &imm_expr); | |
11247 | /* Check for negative input so that small negative numbers | |
11248 | will not succeed incorrectly. The checks against | |
11249 | (pos+size) transitively check "size" itself, | |
11250 | assuming that "pos" is reasonable. */ | |
11251 | if ((long) imm_expr.X_add_number < 0 | |
11252 | || ((unsigned long) imm_expr.X_add_number | |
11253 | + lastpos) < limlo | |
11254 | || ((unsigned long) imm_expr.X_add_number | |
11255 | + lastpos) > limhi) | |
11256 | { | |
11257 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11258 | (unsigned long) imm_expr.X_add_number, | |
11259 | (unsigned long) lastpos); | |
11260 | imm_expr.X_add_number = limlo - lastpos; | |
11261 | } | |
df58fc94 RS |
11262 | INSERT_OPERAND (mips_opts.micromips, |
11263 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11264 | imm_expr.X_op = O_absent; |
11265 | s = expr_end; | |
11266 | continue; | |
af7ee8bf | 11267 | |
bbcc0807 CD |
11268 | case 'D': |
11269 | /* +D is for disassembly only; never match. */ | |
11270 | break; | |
11271 | ||
5f74bc13 CD |
11272 | case 'I': |
11273 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11274 | my_getExpression (&imm2_expr, s); | |
11275 | if (imm2_expr.X_op != O_big | |
11276 | && imm2_expr.X_op != O_constant) | |
11277 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11278 | if (HAVE_32BIT_GPRS) |
11279 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11280 | s = expr_end; |
11281 | continue; | |
11282 | ||
707bfff6 | 11283 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11284 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11285 | /* +T is for disassembly only; never match. */ |
11286 | break; | |
11287 | ||
707bfff6 | 11288 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11289 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11290 | if (s[0] == '$' && ISDIGIT (s[1])) |
11291 | { | |
11292 | ++s; | |
11293 | regno = 0; | |
11294 | do | |
11295 | { | |
11296 | regno *= 10; | |
11297 | regno += *s - '0'; | |
11298 | ++s; | |
11299 | } | |
11300 | while (ISDIGIT (*s)); | |
11301 | if (regno > 31) | |
11302 | as_bad (_("Invalid register number (%d)"), regno); | |
11303 | else | |
11304 | { | |
df58fc94 | 11305 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11306 | continue; |
11307 | } | |
11308 | } | |
11309 | else | |
11310 | as_bad (_("Invalid coprocessor 0 register number")); | |
11311 | break; | |
11312 | ||
bb35fb24 NC |
11313 | case 'x': |
11314 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11315 | is not in the valid range. */ | |
df58fc94 | 11316 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11317 | my_getExpression (&imm_expr, s); |
11318 | check_absolute_expr (ip, &imm_expr); | |
11319 | if ((unsigned) imm_expr.X_add_number > 31) | |
11320 | { | |
11321 | as_bad (_("Improper bit index (%lu)"), | |
11322 | (unsigned long) imm_expr.X_add_number); | |
11323 | imm_expr.X_add_number = 0; | |
11324 | } | |
df58fc94 | 11325 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11326 | imm_expr.X_op = O_absent; |
11327 | s = expr_end; | |
11328 | continue; | |
11329 | ||
11330 | case 'X': | |
11331 | /* bbit[01] bit index when bbit is used but we generate | |
11332 | bbit[01]32 because the index is over 32. Move to the | |
11333 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11334 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11335 | my_getExpression (&imm_expr, s); |
11336 | check_absolute_expr (ip, &imm_expr); | |
11337 | if ((unsigned) imm_expr.X_add_number < 32 | |
11338 | || (unsigned) imm_expr.X_add_number > 63) | |
11339 | break; | |
df58fc94 | 11340 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11341 | imm_expr.X_op = O_absent; |
11342 | s = expr_end; | |
11343 | continue; | |
11344 | ||
11345 | case 'p': | |
11346 | /* cins, cins32, exts and exts32 position field. Give error | |
11347 | if it's not in the valid range. */ | |
df58fc94 | 11348 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11349 | my_getExpression (&imm_expr, s); |
11350 | check_absolute_expr (ip, &imm_expr); | |
11351 | if ((unsigned) imm_expr.X_add_number > 31) | |
11352 | { | |
11353 | as_bad (_("Improper position (%lu)"), | |
11354 | (unsigned long) imm_expr.X_add_number); | |
11355 | imm_expr.X_add_number = 0; | |
11356 | } | |
11357 | /* Make the pos explicit to simplify +S. */ | |
11358 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11359 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11360 | imm_expr.X_op = O_absent; |
11361 | s = expr_end; | |
11362 | continue; | |
11363 | ||
11364 | case 'P': | |
11365 | /* cins, cins32, exts and exts32 position field. Move to | |
11366 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11367 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11368 | my_getExpression (&imm_expr, s); |
11369 | check_absolute_expr (ip, &imm_expr); | |
11370 | if ((unsigned) imm_expr.X_add_number < 32 | |
11371 | || (unsigned) imm_expr.X_add_number > 63) | |
11372 | break; | |
11373 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11374 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11375 | imm_expr.X_op = O_absent; |
11376 | s = expr_end; | |
11377 | continue; | |
11378 | ||
11379 | case 's': | |
11380 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11381 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11382 | my_getExpression (&imm_expr, s); |
11383 | check_absolute_expr (ip, &imm_expr); | |
11384 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11385 | { | |
11386 | as_bad (_("Improper size (%lu)"), | |
11387 | (unsigned long) imm_expr.X_add_number); | |
11388 | imm_expr.X_add_number = 0; | |
11389 | } | |
df58fc94 | 11390 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11391 | imm_expr.X_op = O_absent; |
11392 | s = expr_end; | |
11393 | continue; | |
11394 | ||
11395 | case 'S': | |
11396 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11397 | length-minus-one field. */ | |
df58fc94 | 11398 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11399 | my_getExpression (&imm_expr, s); |
11400 | check_absolute_expr (ip, &imm_expr); | |
11401 | if ((long) imm_expr.X_add_number < 0 | |
11402 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11403 | { | |
11404 | as_bad (_("Improper size (%lu)"), | |
11405 | (unsigned long) imm_expr.X_add_number); | |
11406 | imm_expr.X_add_number = 0; | |
11407 | } | |
df58fc94 | 11408 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11409 | imm_expr.X_op = O_absent; |
11410 | s = expr_end; | |
11411 | continue; | |
11412 | ||
dd3cbb7e NC |
11413 | case 'Q': |
11414 | /* seqi/snei immediate field. */ | |
df58fc94 | 11415 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11416 | my_getExpression (&imm_expr, s); |
11417 | check_absolute_expr (ip, &imm_expr); | |
11418 | if ((long) imm_expr.X_add_number < -512 | |
11419 | || (long) imm_expr.X_add_number >= 512) | |
11420 | { | |
11421 | as_bad (_("Improper immediate (%ld)"), | |
11422 | (long) imm_expr.X_add_number); | |
11423 | imm_expr.X_add_number = 0; | |
11424 | } | |
df58fc94 | 11425 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11426 | imm_expr.X_op = O_absent; |
11427 | s = expr_end; | |
11428 | continue; | |
11429 | ||
98675402 | 11430 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11431 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11432 | my_getExpression (&imm_expr, s); |
11433 | check_absolute_expr (ip, &imm_expr); | |
11434 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11435 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11436 | if (imm_expr.X_add_number < min_range | |
11437 | || imm_expr.X_add_number > max_range) | |
11438 | { | |
c95354ed | 11439 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11440 | (long) min_range, (long) max_range, |
11441 | (long) imm_expr.X_add_number); | |
11442 | } | |
df58fc94 | 11443 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11444 | imm_expr.X_op = O_absent; |
11445 | s = expr_end; | |
11446 | continue; | |
11447 | ||
11448 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11449 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11450 | my_getExpression (&imm_expr, s); |
11451 | check_absolute_expr (ip, &imm_expr); | |
11452 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11453 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11454 | if (imm_expr.X_add_number < min_range | |
11455 | || imm_expr.X_add_number > max_range) | |
11456 | { | |
c95354ed | 11457 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11458 | (long) min_range, (long) max_range, |
11459 | (long) imm_expr.X_add_number); | |
11460 | } | |
df58fc94 | 11461 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11462 | imm_expr.X_op = O_absent; |
11463 | s = expr_end; | |
11464 | continue; | |
11465 | ||
11466 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11467 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11468 | my_getExpression (&imm_expr, s); |
11469 | check_absolute_expr (ip, &imm_expr); | |
11470 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11471 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11472 | /* We check the offset range before adjusted. */ |
11473 | min_range <<= 4; | |
11474 | max_range <<= 4; | |
98675402 RS |
11475 | if (imm_expr.X_add_number < min_range |
11476 | || imm_expr.X_add_number > max_range) | |
11477 | { | |
c95354ed | 11478 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11479 | (long) min_range, (long) max_range, |
11480 | (long) imm_expr.X_add_number); | |
11481 | } | |
c95354ed MX |
11482 | if (imm_expr.X_add_number & 0xf) |
11483 | { | |
11484 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11485 | (long) imm_expr.X_add_number); | |
11486 | } | |
11487 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11488 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11489 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11490 | imm_expr.X_op = O_absent; |
11491 | s = expr_end; | |
11492 | continue; | |
11493 | ||
11494 | case 'z': | |
df58fc94 | 11495 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11496 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11497 | break; | |
11498 | if (regno == AT && mips_opts.at) | |
11499 | { | |
11500 | if (mips_opts.at == ATREG) | |
11501 | as_warn (_("used $at without \".set noat\"")); | |
11502 | else | |
11503 | as_warn (_("used $%u with \".set at=$%u\""), | |
11504 | regno, mips_opts.at); | |
11505 | } | |
df58fc94 | 11506 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11507 | continue; |
11508 | ||
11509 | case 'Z': | |
df58fc94 | 11510 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11511 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11512 | break; | |
df58fc94 | 11513 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11514 | continue; |
11515 | ||
af7ee8bf | 11516 | default: |
df58fc94 | 11517 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11518 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11519 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11520 | *args, insn->name, insn->args); |
af7ee8bf CD |
11521 | /* Further processing is fruitless. */ |
11522 | return; | |
11523 | } | |
11524 | break; | |
11525 | ||
df58fc94 | 11526 | case '.': /* 10-bit offset. */ |
df58fc94 | 11527 | gas_assert (mips_opts.micromips); |
dec0624d | 11528 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11529 | { |
11530 | int shift = *args == '.' ? 9 : 11; | |
11531 | size_t i; | |
11532 | ||
11533 | /* Check whether there is only a single bracketed expression | |
11534 | left. If so, it must be the base register and the | |
11535 | constant must be zero. */ | |
11536 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11537 | continue; | |
11538 | ||
11539 | /* If this value won't fit into the offset, then go find | |
11540 | a macro that will generate a 16- or 32-bit offset code | |
11541 | pattern. */ | |
11542 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11543 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11544 | || imm_expr.X_add_number >= 1 << shift | |
11545 | || imm_expr.X_add_number < -1 << shift)) | |
11546 | || i > 0) | |
11547 | { | |
11548 | imm_expr.X_op = O_absent; | |
11549 | break; | |
11550 | } | |
11551 | if (shift == 9) | |
11552 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11553 | else | |
dec0624d MR |
11554 | INSERT_OPERAND (mips_opts.micromips, |
11555 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11556 | imm_expr.X_op = O_absent; |
11557 | s = expr_end; | |
11558 | } | |
11559 | continue; | |
11560 | ||
252b5132 RH |
11561 | case '<': /* must be at least one digit */ |
11562 | /* | |
11563 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11564 | * than 31 or less than 0, then the shift amount should be |
11565 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11566 | * We issue a warning and mask out all but the low 5 bits. |
11567 | */ | |
11568 | my_getExpression (&imm_expr, s); | |
11569 | check_absolute_expr (ip, &imm_expr); | |
11570 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11571 | as_warn (_("Improper shift amount (%lu)"), |
11572 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11573 | INSERT_OPERAND (mips_opts.micromips, |
11574 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11575 | imm_expr.X_op = O_absent; |
11576 | s = expr_end; | |
11577 | continue; | |
11578 | ||
11579 | case '>': /* shift amount minus 32 */ | |
11580 | my_getExpression (&imm_expr, s); | |
11581 | check_absolute_expr (ip, &imm_expr); | |
11582 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11583 | || (unsigned long) imm_expr.X_add_number > 63) | |
11584 | break; | |
df58fc94 RS |
11585 | INSERT_OPERAND (mips_opts.micromips, |
11586 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11587 | imm_expr.X_op = O_absent; |
11588 | s = expr_end; | |
11589 | continue; | |
11590 | ||
90ecf173 MR |
11591 | case 'k': /* CACHE code. */ |
11592 | case 'h': /* PREFX code. */ | |
11593 | case '1': /* SYNC type. */ | |
252b5132 RH |
11594 | my_getExpression (&imm_expr, s); |
11595 | check_absolute_expr (ip, &imm_expr); | |
11596 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11597 | as_warn (_("Invalid value for `%s' (%lu)"), |
11598 | ip->insn_mo->name, | |
11599 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11600 | switch (*args) |
d954098f | 11601 | { |
df58fc94 RS |
11602 | case 'k': |
11603 | if (mips_fix_cn63xxp1 | |
11604 | && !mips_opts.micromips | |
11605 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11606 | switch (imm_expr.X_add_number) |
11607 | { | |
11608 | case 5: | |
11609 | case 25: | |
11610 | case 26: | |
11611 | case 27: | |
11612 | case 28: | |
11613 | case 29: | |
11614 | case 30: | |
11615 | case 31: /* These are ok. */ | |
11616 | break; | |
11617 | ||
11618 | default: /* The rest must be changed to 28. */ | |
11619 | imm_expr.X_add_number = 28; | |
11620 | break; | |
11621 | } | |
df58fc94 RS |
11622 | INSERT_OPERAND (mips_opts.micromips, |
11623 | CACHE, *ip, imm_expr.X_add_number); | |
11624 | break; | |
11625 | case 'h': | |
11626 | INSERT_OPERAND (mips_opts.micromips, | |
11627 | PREFX, *ip, imm_expr.X_add_number); | |
11628 | break; | |
11629 | case '1': | |
11630 | INSERT_OPERAND (mips_opts.micromips, | |
11631 | STYPE, *ip, imm_expr.X_add_number); | |
11632 | break; | |
d954098f | 11633 | } |
252b5132 RH |
11634 | imm_expr.X_op = O_absent; |
11635 | s = expr_end; | |
11636 | continue; | |
11637 | ||
90ecf173 | 11638 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11639 | { |
11640 | unsigned long mask = (mips_opts.micromips | |
11641 | ? MICROMIPSOP_MASK_CODE | |
11642 | : OP_MASK_CODE); | |
11643 | ||
11644 | my_getExpression (&imm_expr, s); | |
11645 | check_absolute_expr (ip, &imm_expr); | |
11646 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11647 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11648 | ip->insn_mo->name, | |
11649 | mask, (unsigned long) imm_expr.X_add_number); | |
11650 | INSERT_OPERAND (mips_opts.micromips, | |
11651 | CODE, *ip, imm_expr.X_add_number); | |
11652 | imm_expr.X_op = O_absent; | |
11653 | s = expr_end; | |
11654 | } | |
252b5132 RH |
11655 | continue; |
11656 | ||
90ecf173 | 11657 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11658 | { |
11659 | unsigned long mask = (mips_opts.micromips | |
11660 | ? MICROMIPSOP_MASK_CODE2 | |
11661 | : OP_MASK_CODE2); | |
11662 | ||
11663 | my_getExpression (&imm_expr, s); | |
11664 | check_absolute_expr (ip, &imm_expr); | |
11665 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11666 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11667 | ip->insn_mo->name, | |
11668 | mask, (unsigned long) imm_expr.X_add_number); | |
11669 | INSERT_OPERAND (mips_opts.micromips, | |
11670 | CODE2, *ip, imm_expr.X_add_number); | |
11671 | imm_expr.X_op = O_absent; | |
11672 | s = expr_end; | |
11673 | } | |
252b5132 RH |
11674 | continue; |
11675 | ||
df58fc94 RS |
11676 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11677 | { | |
11678 | unsigned long mask = (mips_opts.micromips | |
11679 | ? MICROMIPSOP_MASK_CODE10 | |
11680 | : OP_MASK_CODE20); | |
11681 | ||
11682 | my_getExpression (&imm_expr, s); | |
11683 | check_absolute_expr (ip, &imm_expr); | |
11684 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11685 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11686 | ip->insn_mo->name, | |
11687 | mask, (unsigned long) imm_expr.X_add_number); | |
11688 | if (mips_opts.micromips) | |
11689 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11690 | else | |
11691 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11692 | imm_expr.X_op = O_absent; | |
11693 | s = expr_end; | |
11694 | } | |
252b5132 RH |
11695 | continue; |
11696 | ||
df58fc94 RS |
11697 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11698 | { | |
11699 | unsigned long mask = (mips_opts.micromips | |
11700 | ? MICROMIPSOP_MASK_COPZ | |
11701 | : OP_MASK_COPZ); | |
11702 | ||
11703 | my_getExpression (&imm_expr, s); | |
11704 | check_absolute_expr (ip, &imm_expr); | |
11705 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11706 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11707 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11708 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11709 | INSERT_OPERAND (mips_opts.micromips, |
11710 | COPZ, *ip, imm_expr.X_add_number); | |
11711 | imm_expr.X_op = O_absent; | |
11712 | s = expr_end; | |
11713 | } | |
beae10d5 | 11714 | continue; |
252b5132 | 11715 | |
df58fc94 RS |
11716 | case 'J': /* 19-bit WAIT code. */ |
11717 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11718 | my_getExpression (&imm_expr, s); |
11719 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11720 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11721 | { |
11722 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11723 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11724 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11725 | } | |
11726 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11727 | imm_expr.X_op = O_absent; |
11728 | s = expr_end; | |
11729 | continue; | |
11730 | ||
707bfff6 | 11731 | case 'P': /* Performance register. */ |
df58fc94 | 11732 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11733 | my_getExpression (&imm_expr, s); |
252b5132 | 11734 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11735 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11736 | as_warn (_("Invalid performance register (%lu)"), |
11737 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11738 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11739 | imm_expr.X_op = O_absent; |
11740 | s = expr_end; | |
11741 | continue; | |
252b5132 | 11742 | |
707bfff6 | 11743 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11744 | { |
11745 | unsigned long opcode = ip->insn_opcode; | |
11746 | unsigned long mask; | |
11747 | unsigned int types; | |
11748 | int cop0; | |
11749 | ||
11750 | if (mips_opts.micromips) | |
11751 | { | |
11752 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11753 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11754 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11755 | opcode &= mask; | |
11756 | switch (opcode) | |
11757 | { | |
11758 | case 0x000000fc: /* mfc0 */ | |
11759 | case 0x000002fc: /* mtc0 */ | |
11760 | case 0x580000fc: /* dmfc0 */ | |
11761 | case 0x580002fc: /* dmtc0 */ | |
11762 | cop0 = 1; | |
11763 | break; | |
11764 | default: | |
11765 | cop0 = 0; | |
11766 | break; | |
11767 | } | |
11768 | } | |
11769 | else | |
11770 | { | |
11771 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11772 | cop0 = opcode == OP_OP_COP0; | |
11773 | } | |
11774 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11775 | ok = reg_lookup (&s, types, ®no); | |
11776 | if (mips_opts.micromips) | |
11777 | INSERT_OPERAND (1, RS, *ip, regno); | |
11778 | else | |
11779 | INSERT_OPERAND (0, RD, *ip, regno); | |
11780 | if (ok) | |
11781 | { | |
11782 | lastregno = regno; | |
11783 | continue; | |
11784 | } | |
11785 | } | |
11786 | break; | |
707bfff6 | 11787 | |
df58fc94 RS |
11788 | case 'y': /* ALNV.PS source register. */ |
11789 | gas_assert (mips_opts.micromips); | |
11790 | goto do_reg; | |
11791 | case 'x': /* Ignore register name. */ | |
11792 | case 'U': /* Destination register (CLO/CLZ). */ | |
11793 | case 'g': /* Coprocessor destination register. */ | |
11794 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11795 | case 'b': /* Base register. */ |
11796 | case 'd': /* Destination register. */ | |
11797 | case 's': /* Source register. */ | |
11798 | case 't': /* Target register. */ | |
11799 | case 'r': /* Both target and source. */ | |
11800 | case 'v': /* Both dest and source. */ | |
11801 | case 'w': /* Both dest and target. */ | |
11802 | case 'E': /* Coprocessor target register. */ | |
11803 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11804 | case 'z': /* Must be zero register. */ |
df58fc94 | 11805 | do_reg: |
90ecf173 | 11806 | s_reset = s; |
707bfff6 TS |
11807 | if (*args == 'E' || *args == 'K') |
11808 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11809 | else | |
11810 | { | |
11811 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11812 | if (regno == AT && mips_opts.at) |
11813 | { | |
11814 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11815 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11816 | else |
f71d0d44 | 11817 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11818 | regno, mips_opts.at); |
11819 | } | |
707bfff6 TS |
11820 | } |
11821 | if (ok) | |
252b5132 | 11822 | { |
252b5132 RH |
11823 | c = *args; |
11824 | if (*s == ' ') | |
f9419b05 | 11825 | ++s; |
252b5132 RH |
11826 | if (args[1] != *s) |
11827 | { | |
11828 | if (c == 'r' || c == 'v' || c == 'w') | |
11829 | { | |
11830 | regno = lastregno; | |
11831 | s = s_reset; | |
f9419b05 | 11832 | ++args; |
252b5132 RH |
11833 | } |
11834 | } | |
11835 | /* 'z' only matches $0. */ | |
11836 | if (c == 'z' && regno != 0) | |
11837 | break; | |
11838 | ||
24864476 | 11839 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11840 | { |
11841 | if (regno == lastregno) | |
90ecf173 MR |
11842 | { |
11843 | insn_error | |
f71d0d44 | 11844 | = _("Source and destination must be different"); |
e7c604dd | 11845 | continue; |
90ecf173 | 11846 | } |
24864476 | 11847 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11848 | { |
11849 | insn_error | |
f71d0d44 | 11850 | = _("A destination register must be supplied"); |
e7c604dd | 11851 | continue; |
90ecf173 | 11852 | } |
e7c604dd | 11853 | } |
90ecf173 MR |
11854 | /* Now that we have assembled one operand, we use the args |
11855 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11856 | switch (c) |
11857 | { | |
11858 | case 'r': | |
11859 | case 's': | |
11860 | case 'v': | |
11861 | case 'b': | |
df58fc94 | 11862 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11863 | break; |
df58fc94 | 11864 | |
af7ee8bf | 11865 | case 'K': |
df58fc94 RS |
11866 | if (mips_opts.micromips) |
11867 | INSERT_OPERAND (1, RS, *ip, regno); | |
11868 | else | |
11869 | INSERT_OPERAND (0, RD, *ip, regno); | |
11870 | break; | |
11871 | ||
11872 | case 'd': | |
ef2e4d86 | 11873 | case 'g': |
df58fc94 | 11874 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11875 | break; |
df58fc94 | 11876 | |
4372b673 | 11877 | case 'U': |
df58fc94 RS |
11878 | gas_assert (!mips_opts.micromips); |
11879 | INSERT_OPERAND (0, RD, *ip, regno); | |
11880 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11881 | break; |
df58fc94 | 11882 | |
252b5132 RH |
11883 | case 'w': |
11884 | case 't': | |
11885 | case 'E': | |
df58fc94 RS |
11886 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11887 | break; | |
11888 | ||
11889 | case 'y': | |
11890 | gas_assert (mips_opts.micromips); | |
11891 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11892 | break; |
df58fc94 | 11893 | |
252b5132 RH |
11894 | case 'x': |
11895 | /* This case exists because on the r3000 trunc | |
11896 | expands into a macro which requires a gp | |
11897 | register. On the r6000 or r4000 it is | |
11898 | assembled into a single instruction which | |
11899 | ignores the register. Thus the insn version | |
11900 | is MIPS_ISA2 and uses 'x', and the macro | |
11901 | version is MIPS_ISA1 and uses 't'. */ | |
11902 | break; | |
df58fc94 | 11903 | |
252b5132 RH |
11904 | case 'z': |
11905 | /* This case is for the div instruction, which | |
11906 | acts differently if the destination argument | |
11907 | is $0. This only matches $0, and is checked | |
11908 | outside the switch. */ | |
11909 | break; | |
252b5132 RH |
11910 | } |
11911 | lastregno = regno; | |
11912 | continue; | |
11913 | } | |
252b5132 RH |
11914 | switch (*args++) |
11915 | { | |
11916 | case 'r': | |
11917 | case 'v': | |
df58fc94 | 11918 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11919 | continue; |
df58fc94 | 11920 | |
252b5132 | 11921 | case 'w': |
df58fc94 | 11922 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11923 | continue; |
11924 | } | |
11925 | break; | |
11926 | ||
deec1734 | 11927 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11928 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11929 | my_getExpression (&imm_expr, s); |
11930 | check_absolute_expr (ip, &imm_expr); | |
11931 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11932 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11933 | (long) imm_expr.X_add_number); |
df58fc94 | 11934 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11935 | imm_expr.X_op = O_absent; |
11936 | s = expr_end; | |
11937 | continue; | |
11938 | ||
11939 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11940 | if (s[0] != '$') | |
11941 | { | |
11942 | /* MDMX Immediate. */ | |
df58fc94 | 11943 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11944 | my_getExpression (&imm_expr, s); |
11945 | check_absolute_expr (ip, &imm_expr); | |
11946 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11947 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11948 | (long) imm_expr.X_add_number); | |
df58fc94 | 11949 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11950 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11951 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11952 | else | |
11953 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11954 | imm_expr.X_op = O_absent; |
11955 | s = expr_end; | |
11956 | continue; | |
11957 | } | |
11958 | /* Not MDMX Immediate. Fall through. */ | |
11959 | case 'X': /* MDMX destination register. */ | |
11960 | case 'Y': /* MDMX source register. */ | |
11961 | case 'Z': /* MDMX target register. */ | |
11962 | is_mdmx = 1; | |
df58fc94 RS |
11963 | case 'W': |
11964 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11965 | case 'D': /* Floating point destination register. */ |
11966 | case 'S': /* Floating point source register. */ | |
11967 | case 'T': /* Floating point target register. */ | |
11968 | case 'R': /* Floating point source register. */ | |
252b5132 | 11969 | case 'V': |
707bfff6 TS |
11970 | rtype = RTYPE_FPU; |
11971 | if (is_mdmx | |
11972 | || (mips_opts.ase_mdmx | |
11973 | && (ip->insn_mo->pinfo & FP_D) | |
11974 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11975 | | INSN_COPROC_MEMORY_DELAY | |
11976 | | INSN_LOAD_COPROC_DELAY | |
11977 | | INSN_LOAD_MEMORY_DELAY | |
11978 | | INSN_STORE_MEMORY)))) | |
11979 | rtype |= RTYPE_VEC; | |
252b5132 | 11980 | s_reset = s; |
707bfff6 | 11981 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11982 | { |
252b5132 | 11983 | if ((regno & 1) != 0 |
ca4e0257 | 11984 | && HAVE_32BIT_FPRS |
90ecf173 | 11985 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11986 | as_warn (_("Float register should be even, was %d"), |
11987 | regno); | |
11988 | ||
11989 | c = *args; | |
11990 | if (*s == ' ') | |
f9419b05 | 11991 | ++s; |
252b5132 RH |
11992 | if (args[1] != *s) |
11993 | { | |
11994 | if (c == 'V' || c == 'W') | |
11995 | { | |
11996 | regno = lastregno; | |
11997 | s = s_reset; | |
f9419b05 | 11998 | ++args; |
252b5132 RH |
11999 | } |
12000 | } | |
12001 | switch (c) | |
12002 | { | |
12003 | case 'D': | |
deec1734 | 12004 | case 'X': |
df58fc94 | 12005 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12006 | break; |
df58fc94 | 12007 | |
252b5132 RH |
12008 | case 'V': |
12009 | case 'S': | |
deec1734 | 12010 | case 'Y': |
df58fc94 | 12011 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12012 | break; |
df58fc94 | 12013 | |
deec1734 CD |
12014 | case 'Q': |
12015 | /* This is like 'Z', but also needs to fix the MDMX | |
12016 | vector/scalar select bits. Note that the | |
12017 | scalar immediate case is handled above. */ | |
12018 | if (*s == '[') | |
12019 | { | |
12020 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12021 | int max_el = (is_qh ? 3 : 7); | |
12022 | s++; | |
12023 | my_getExpression(&imm_expr, s); | |
12024 | check_absolute_expr (ip, &imm_expr); | |
12025 | s = expr_end; | |
12026 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12027 | as_bad (_("Bad element selector %ld"), |
12028 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12029 | imm_expr.X_add_number &= max_el; |
12030 | ip->insn_opcode |= (imm_expr.X_add_number | |
12031 | << (OP_SH_VSEL + | |
12032 | (is_qh ? 2 : 1))); | |
01a3f561 | 12033 | imm_expr.X_op = O_absent; |
deec1734 | 12034 | if (*s != ']') |
20203fb9 | 12035 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12036 | else |
12037 | s++; | |
12038 | } | |
12039 | else | |
12040 | { | |
12041 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
12042 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12043 | << OP_SH_VSEL); | |
12044 | else | |
12045 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12046 | OP_SH_VSEL); | |
12047 | } | |
90ecf173 | 12048 | /* Fall through. */ |
252b5132 RH |
12049 | case 'W': |
12050 | case 'T': | |
deec1734 | 12051 | case 'Z': |
df58fc94 | 12052 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12053 | break; |
df58fc94 | 12054 | |
252b5132 | 12055 | case 'R': |
df58fc94 | 12056 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12057 | break; |
12058 | } | |
12059 | lastregno = regno; | |
12060 | continue; | |
12061 | } | |
12062 | ||
252b5132 RH |
12063 | switch (*args++) |
12064 | { | |
12065 | case 'V': | |
df58fc94 | 12066 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12067 | continue; |
df58fc94 | 12068 | |
252b5132 | 12069 | case 'W': |
df58fc94 | 12070 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12071 | continue; |
12072 | } | |
12073 | break; | |
12074 | ||
12075 | case 'I': | |
12076 | my_getExpression (&imm_expr, s); | |
12077 | if (imm_expr.X_op != O_big | |
12078 | && imm_expr.X_op != O_constant) | |
12079 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12080 | if (HAVE_32BIT_GPRS) |
12081 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12082 | s = expr_end; |
12083 | continue; | |
12084 | ||
12085 | case 'A': | |
12086 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12087 | normalize_address_expr (&offset_expr); |
f6688943 | 12088 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12089 | s = expr_end; |
12090 | continue; | |
12091 | ||
12092 | case 'F': | |
12093 | case 'L': | |
12094 | case 'f': | |
12095 | case 'l': | |
12096 | { | |
12097 | int f64; | |
ca4e0257 | 12098 | int using_gprs; |
252b5132 RH |
12099 | char *save_in; |
12100 | char *err; | |
12101 | unsigned char temp[8]; | |
12102 | int len; | |
12103 | unsigned int length; | |
12104 | segT seg; | |
12105 | subsegT subseg; | |
12106 | char *p; | |
12107 | ||
12108 | /* These only appear as the last operand in an | |
12109 | instruction, and every instruction that accepts | |
12110 | them in any variant accepts them in all variants. | |
12111 | This means we don't have to worry about backing out | |
12112 | any changes if the instruction does not match. | |
12113 | ||
12114 | The difference between them is the size of the | |
12115 | floating point constant and where it goes. For 'F' | |
12116 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12117 | is 32 bits. Where the constant is placed is based | |
12118 | on how the MIPS assembler does things: | |
12119 | F -- .rdata | |
12120 | L -- .lit8 | |
12121 | f -- immediate value | |
12122 | l -- .lit4 | |
12123 | ||
12124 | The .lit4 and .lit8 sections are only used if | |
12125 | permitted by the -G argument. | |
12126 | ||
ca4e0257 RS |
12127 | The code below needs to know whether the target register |
12128 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12129 | 'F' are used with GPR-based instructions and 'l' and | |
12130 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12131 | |
12132 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12133 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12134 | |
12135 | save_in = input_line_pointer; | |
12136 | input_line_pointer = s; | |
12137 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12138 | length = len; | |
12139 | s = input_line_pointer; | |
12140 | input_line_pointer = save_in; | |
12141 | if (err != NULL && *err != '\0') | |
12142 | { | |
12143 | as_bad (_("Bad floating point constant: %s"), err); | |
12144 | memset (temp, '\0', sizeof temp); | |
12145 | length = f64 ? 8 : 4; | |
12146 | } | |
12147 | ||
9c2799c2 | 12148 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12149 | |
12150 | if (*args == 'f' | |
12151 | || (*args == 'l' | |
3e722fb5 | 12152 | && (g_switch_value < 4 |
252b5132 RH |
12153 | || (temp[0] == 0 && temp[1] == 0) |
12154 | || (temp[2] == 0 && temp[3] == 0)))) | |
12155 | { | |
12156 | imm_expr.X_op = O_constant; | |
90ecf173 | 12157 | if (!target_big_endian) |
252b5132 RH |
12158 | imm_expr.X_add_number = bfd_getl32 (temp); |
12159 | else | |
12160 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12161 | } | |
12162 | else if (length > 4 | |
90ecf173 | 12163 | && !mips_disable_float_construction |
ca4e0257 RS |
12164 | /* Constants can only be constructed in GPRs and |
12165 | copied to FPRs if the GPRs are at least as wide | |
12166 | as the FPRs. Force the constant into memory if | |
12167 | we are using 64-bit FPRs but the GPRs are only | |
12168 | 32 bits wide. */ | |
12169 | && (using_gprs | |
90ecf173 | 12170 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12171 | && ((temp[0] == 0 && temp[1] == 0) |
12172 | || (temp[2] == 0 && temp[3] == 0)) | |
12173 | && ((temp[4] == 0 && temp[5] == 0) | |
12174 | || (temp[6] == 0 && temp[7] == 0))) | |
12175 | { | |
ca4e0257 | 12176 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12177 | instructions. If using 32-bit registers, set |
12178 | imm_expr to the high order 32 bits and offset_expr to | |
12179 | the low order 32 bits. Otherwise, set imm_expr to | |
12180 | the entire 64 bit constant. */ | |
ca4e0257 | 12181 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12182 | { |
12183 | imm_expr.X_op = O_constant; | |
12184 | offset_expr.X_op = O_constant; | |
90ecf173 | 12185 | if (!target_big_endian) |
252b5132 RH |
12186 | { |
12187 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12188 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12189 | } | |
12190 | else | |
12191 | { | |
12192 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12193 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12194 | } | |
12195 | if (offset_expr.X_add_number == 0) | |
12196 | offset_expr.X_op = O_absent; | |
12197 | } | |
12198 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12199 | { | |
12200 | imm_expr.X_op = O_constant; | |
90ecf173 | 12201 | if (!target_big_endian) |
252b5132 RH |
12202 | imm_expr.X_add_number = bfd_getl64 (temp); |
12203 | else | |
12204 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12205 | } | |
12206 | else | |
12207 | { | |
12208 | imm_expr.X_op = O_big; | |
12209 | imm_expr.X_add_number = 4; | |
90ecf173 | 12210 | if (!target_big_endian) |
252b5132 RH |
12211 | { |
12212 | generic_bignum[0] = bfd_getl16 (temp); | |
12213 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12214 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12215 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12216 | } | |
12217 | else | |
12218 | { | |
12219 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12220 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12221 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12222 | generic_bignum[3] = bfd_getb16 (temp); | |
12223 | } | |
12224 | } | |
12225 | } | |
12226 | else | |
12227 | { | |
12228 | const char *newname; | |
12229 | segT new_seg; | |
12230 | ||
12231 | /* Switch to the right section. */ | |
12232 | seg = now_seg; | |
12233 | subseg = now_subseg; | |
12234 | switch (*args) | |
12235 | { | |
12236 | default: /* unused default case avoids warnings. */ | |
12237 | case 'L': | |
12238 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12239 | if (g_switch_value >= 8) |
252b5132 RH |
12240 | newname = ".lit8"; |
12241 | break; | |
12242 | case 'F': | |
3e722fb5 | 12243 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12244 | break; |
12245 | case 'l': | |
9c2799c2 | 12246 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12247 | newname = ".lit4"; |
12248 | break; | |
12249 | } | |
12250 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12251 | if (IS_ELF) |
252b5132 RH |
12252 | bfd_set_section_flags (stdoutput, new_seg, |
12253 | (SEC_ALLOC | |
12254 | | SEC_LOAD | |
12255 | | SEC_READONLY | |
12256 | | SEC_DATA)); | |
12257 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12258 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12259 | record_alignment (new_seg, 4); |
12260 | else | |
12261 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12262 | if (seg == now_seg) | |
12263 | as_bad (_("Can't use floating point insn in this section")); | |
12264 | ||
df58fc94 RS |
12265 | /* Set the argument to the current address in the |
12266 | section. */ | |
12267 | offset_expr.X_op = O_symbol; | |
12268 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12269 | offset_expr.X_add_number = 0; | |
12270 | ||
12271 | /* Put the floating point number into the section. */ | |
12272 | p = frag_more ((int) length); | |
12273 | memcpy (p, temp, length); | |
12274 | ||
12275 | /* Switch back to the original section. */ | |
12276 | subseg_set (seg, subseg); | |
12277 | } | |
12278 | } | |
12279 | continue; | |
12280 | ||
12281 | case 'i': /* 16-bit unsigned immediate. */ | |
12282 | case 'j': /* 16-bit signed immediate. */ | |
12283 | *imm_reloc = BFD_RELOC_LO16; | |
12284 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12285 | { | |
12286 | int more; | |
12287 | offsetT minval, maxval; | |
12288 | ||
12289 | more = (insn + 1 < past | |
12290 | && strcmp (insn->name, insn[1].name) == 0); | |
12291 | ||
12292 | /* If the expression was written as an unsigned number, | |
12293 | only treat it as signed if there are no more | |
12294 | alternatives. */ | |
12295 | if (more | |
12296 | && *args == 'j' | |
12297 | && sizeof (imm_expr.X_add_number) <= 4 | |
12298 | && imm_expr.X_op == O_constant | |
12299 | && imm_expr.X_add_number < 0 | |
12300 | && imm_expr.X_unsigned | |
12301 | && HAVE_64BIT_GPRS) | |
12302 | break; | |
12303 | ||
12304 | /* For compatibility with older assemblers, we accept | |
12305 | 0x8000-0xffff as signed 16-bit numbers when only | |
12306 | signed numbers are allowed. */ | |
12307 | if (*args == 'i') | |
12308 | minval = 0, maxval = 0xffff; | |
12309 | else if (more) | |
12310 | minval = -0x8000, maxval = 0x7fff; | |
12311 | else | |
12312 | minval = -0x8000, maxval = 0xffff; | |
12313 | ||
12314 | if (imm_expr.X_op != O_constant | |
12315 | || imm_expr.X_add_number < minval | |
12316 | || imm_expr.X_add_number > maxval) | |
12317 | { | |
12318 | if (more) | |
12319 | break; | |
12320 | if (imm_expr.X_op == O_constant | |
12321 | || imm_expr.X_op == O_big) | |
12322 | as_bad (_("Expression out of range")); | |
12323 | } | |
12324 | } | |
12325 | s = expr_end; | |
12326 | continue; | |
12327 | ||
12328 | case 'o': /* 16-bit offset. */ | |
12329 | offset_reloc[0] = BFD_RELOC_LO16; | |
12330 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12331 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12332 | ||
12333 | /* Check whether there is only a single bracketed expression | |
12334 | left. If so, it must be the base register and the | |
12335 | constant must be zero. */ | |
12336 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12337 | { | |
12338 | offset_expr.X_op = O_constant; | |
12339 | offset_expr.X_add_number = 0; | |
12340 | continue; | |
12341 | } | |
12342 | ||
12343 | /* If this value won't fit into a 16 bit offset, then go | |
12344 | find a macro that will generate the 32 bit offset | |
12345 | code pattern. */ | |
12346 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12347 | && (offset_expr.X_op != O_constant | |
12348 | || offset_expr.X_add_number >= 0x8000 | |
12349 | || offset_expr.X_add_number < -0x8000)) | |
12350 | break; | |
12351 | ||
12352 | s = expr_end; | |
12353 | continue; | |
12354 | ||
12355 | case 'p': /* PC-relative offset. */ | |
12356 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12357 | my_getExpression (&offset_expr, s); | |
12358 | s = expr_end; | |
12359 | continue; | |
12360 | ||
12361 | case 'u': /* Upper 16 bits. */ | |
12362 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12363 | && imm_expr.X_op == O_constant | |
12364 | && (imm_expr.X_add_number < 0 | |
12365 | || imm_expr.X_add_number >= 0x10000)) | |
12366 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12367 | (unsigned long) imm_expr.X_add_number); | |
12368 | s = expr_end; | |
12369 | continue; | |
12370 | ||
12371 | case 'a': /* 26-bit address. */ | |
12372 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12373 | my_getExpression (&offset_expr, s); | |
12374 | s = expr_end; | |
12375 | continue; | |
12376 | ||
12377 | case 'N': /* 3-bit branch condition code. */ | |
12378 | case 'M': /* 3-bit compare condition code. */ | |
12379 | rtype = RTYPE_CCC; | |
12380 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12381 | rtype |= RTYPE_FCC; | |
12382 | if (!reg_lookup (&s, rtype, ®no)) | |
12383 | break; | |
12384 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12385 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12386 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12387 | && (regno & 1) != 0) | |
12388 | as_warn (_("Condition code register should be even for %s, " | |
12389 | "was %d"), | |
12390 | str, regno); | |
12391 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12392 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12393 | && (regno & 3) != 0) | |
12394 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12395 | "was %d"), | |
12396 | str, regno); | |
12397 | if (*args == 'N') | |
12398 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12399 | else | |
12400 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12401 | continue; | |
12402 | ||
12403 | case 'H': | |
12404 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12405 | s += 2; | |
12406 | if (ISDIGIT (*s)) | |
12407 | { | |
12408 | c = 0; | |
12409 | do | |
12410 | { | |
12411 | c *= 10; | |
12412 | c += *s - '0'; | |
12413 | ++s; | |
12414 | } | |
12415 | while (ISDIGIT (*s)); | |
12416 | } | |
12417 | else | |
12418 | c = 8; /* Invalid sel value. */ | |
12419 | ||
12420 | if (c > 7) | |
12421 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12422 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12423 | continue; | |
12424 | ||
12425 | case 'e': | |
12426 | gas_assert (!mips_opts.micromips); | |
12427 | /* Must be at least one digit. */ | |
12428 | my_getExpression (&imm_expr, s); | |
12429 | check_absolute_expr (ip, &imm_expr); | |
12430 | ||
12431 | if ((unsigned long) imm_expr.X_add_number | |
12432 | > (unsigned long) OP_MASK_VECBYTE) | |
12433 | { | |
12434 | as_bad (_("bad byte vector index (%ld)"), | |
12435 | (long) imm_expr.X_add_number); | |
12436 | imm_expr.X_add_number = 0; | |
12437 | } | |
12438 | ||
12439 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12440 | imm_expr.X_op = O_absent; | |
12441 | s = expr_end; | |
12442 | continue; | |
12443 | ||
12444 | case '%': | |
12445 | gas_assert (!mips_opts.micromips); | |
12446 | my_getExpression (&imm_expr, s); | |
12447 | check_absolute_expr (ip, &imm_expr); | |
12448 | ||
12449 | if ((unsigned long) imm_expr.X_add_number | |
12450 | > (unsigned long) OP_MASK_VECALIGN) | |
12451 | { | |
12452 | as_bad (_("bad byte vector index (%ld)"), | |
12453 | (long) imm_expr.X_add_number); | |
12454 | imm_expr.X_add_number = 0; | |
12455 | } | |
12456 | ||
12457 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12458 | imm_expr.X_op = O_absent; | |
12459 | s = expr_end; | |
12460 | continue; | |
12461 | ||
12462 | case 'm': /* Opcode extension character. */ | |
12463 | gas_assert (mips_opts.micromips); | |
12464 | c = *++args; | |
12465 | switch (c) | |
12466 | { | |
12467 | case 'r': | |
12468 | if (strncmp (s, "$pc", 3) == 0) | |
12469 | { | |
12470 | s += 3; | |
12471 | continue; | |
12472 | } | |
12473 | break; | |
12474 | ||
12475 | case 'a': | |
12476 | case 'b': | |
12477 | case 'c': | |
12478 | case 'd': | |
12479 | case 'e': | |
12480 | case 'f': | |
12481 | case 'g': | |
12482 | case 'h': | |
12483 | case 'i': | |
12484 | case 'j': | |
12485 | case 'l': | |
12486 | case 'm': | |
12487 | case 'n': | |
12488 | case 'p': | |
12489 | case 'q': | |
12490 | case 's': | |
12491 | case 't': | |
12492 | case 'x': | |
12493 | case 'y': | |
12494 | case 'z': | |
12495 | s_reset = s; | |
12496 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12497 | if (regno == AT && mips_opts.at) | |
12498 | { | |
12499 | if (mips_opts.at == ATREG) | |
12500 | as_warn (_("Used $at without \".set noat\"")); | |
12501 | else | |
12502 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12503 | regno, mips_opts.at); | |
12504 | } | |
12505 | if (!ok) | |
12506 | { | |
12507 | if (c == 'c') | |
12508 | { | |
12509 | gas_assert (args[1] == ','); | |
12510 | regno = lastregno; | |
12511 | ++args; | |
12512 | } | |
12513 | else if (c == 't') | |
12514 | { | |
12515 | gas_assert (args[1] == ','); | |
12516 | ++args; | |
12517 | continue; /* Nothing to do. */ | |
12518 | } | |
12519 | else | |
12520 | break; | |
12521 | } | |
12522 | ||
12523 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12524 | { | |
12525 | if (regno == lastregno) | |
12526 | { | |
12527 | insn_error | |
12528 | = _("Source and destination must be different"); | |
12529 | continue; | |
12530 | } | |
12531 | if (regno == 31 && lastregno == 0xffffffff) | |
12532 | { | |
12533 | insn_error | |
12534 | = _("A destination register must be supplied"); | |
12535 | continue; | |
12536 | } | |
12537 | } | |
12538 | ||
12539 | if (*s == ' ') | |
12540 | ++s; | |
12541 | if (args[1] != *s) | |
12542 | { | |
12543 | if (c == 'e') | |
12544 | { | |
12545 | gas_assert (args[1] == ','); | |
12546 | regno = lastregno; | |
12547 | s = s_reset; | |
12548 | ++args; | |
12549 | } | |
12550 | else if (c == 't') | |
12551 | { | |
12552 | gas_assert (args[1] == ','); | |
12553 | s = s_reset; | |
12554 | ++args; | |
12555 | continue; /* Nothing to do. */ | |
12556 | } | |
12557 | } | |
12558 | ||
12559 | /* Make sure regno is the same as lastregno. */ | |
12560 | if (c == 't' && regno != lastregno) | |
12561 | break; | |
12562 | ||
12563 | /* Make sure regno is the same as destregno. */ | |
12564 | if (c == 'x' && regno != destregno) | |
12565 | break; | |
12566 | ||
12567 | /* We need to save regno, before regno maps to the | |
12568 | microMIPS register encoding. */ | |
12569 | lastregno = regno; | |
12570 | ||
12571 | if (c == 'f') | |
12572 | destregno = regno; | |
12573 | ||
12574 | switch (c) | |
12575 | { | |
12576 | case 'a': | |
12577 | if (regno != GP) | |
12578 | regno = ILLEGAL_REG; | |
12579 | break; | |
12580 | ||
12581 | case 'b': | |
12582 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12583 | break; | |
12584 | ||
12585 | case 'c': | |
12586 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12587 | break; | |
12588 | ||
12589 | case 'd': | |
12590 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12591 | break; | |
12592 | ||
12593 | case 'e': | |
12594 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12595 | break; | |
12596 | ||
12597 | case 'f': | |
12598 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12599 | break; | |
12600 | ||
12601 | case 'g': | |
12602 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12603 | break; | |
12604 | ||
12605 | case 'h': | |
12606 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12607 | break; | |
12608 | ||
12609 | case 'i': | |
12610 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12611 | { | |
12612 | case 4: | |
12613 | if (regno == 21) | |
12614 | regno = 3; | |
12615 | else if (regno == 22) | |
12616 | regno = 4; | |
12617 | else if (regno == 5) | |
12618 | regno = 5; | |
12619 | else if (regno == 6) | |
12620 | regno = 6; | |
12621 | else if (regno == 7) | |
12622 | regno = 7; | |
12623 | else | |
12624 | regno = ILLEGAL_REG; | |
12625 | break; | |
12626 | ||
12627 | case 5: | |
12628 | if (regno == 6) | |
12629 | regno = 0; | |
12630 | else if (regno == 7) | |
12631 | regno = 1; | |
12632 | else | |
12633 | regno = ILLEGAL_REG; | |
12634 | break; | |
12635 | ||
12636 | case 6: | |
12637 | if (regno == 7) | |
12638 | regno = 2; | |
12639 | else | |
12640 | regno = ILLEGAL_REG; | |
12641 | break; | |
12642 | ||
12643 | default: | |
12644 | regno = ILLEGAL_REG; | |
12645 | break; | |
12646 | } | |
12647 | break; | |
12648 | ||
12649 | case 'l': | |
12650 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12651 | break; | |
12652 | ||
12653 | case 'm': | |
12654 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12655 | break; | |
12656 | ||
12657 | case 'n': | |
12658 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12659 | break; | |
12660 | ||
12661 | case 'q': | |
12662 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12663 | break; | |
12664 | ||
12665 | case 's': | |
12666 | if (regno != SP) | |
12667 | regno = ILLEGAL_REG; | |
12668 | break; | |
12669 | ||
12670 | case 'y': | |
12671 | if (regno != 31) | |
12672 | regno = ILLEGAL_REG; | |
12673 | break; | |
12674 | ||
12675 | case 'z': | |
12676 | if (regno != ZERO) | |
12677 | regno = ILLEGAL_REG; | |
12678 | break; | |
12679 | ||
12680 | case 'j': /* Do nothing. */ | |
12681 | case 'p': | |
12682 | case 't': | |
12683 | case 'x': | |
12684 | break; | |
12685 | ||
12686 | default: | |
12687 | internalError (); | |
12688 | } | |
12689 | ||
12690 | if (regno == ILLEGAL_REG) | |
12691 | break; | |
12692 | ||
12693 | switch (c) | |
12694 | { | |
12695 | case 'b': | |
12696 | INSERT_OPERAND (1, MB, *ip, regno); | |
12697 | break; | |
12698 | ||
12699 | case 'c': | |
12700 | INSERT_OPERAND (1, MC, *ip, regno); | |
12701 | break; | |
12702 | ||
12703 | case 'd': | |
12704 | INSERT_OPERAND (1, MD, *ip, regno); | |
12705 | break; | |
12706 | ||
12707 | case 'e': | |
12708 | INSERT_OPERAND (1, ME, *ip, regno); | |
12709 | break; | |
12710 | ||
12711 | case 'f': | |
12712 | INSERT_OPERAND (1, MF, *ip, regno); | |
12713 | break; | |
12714 | ||
12715 | case 'g': | |
12716 | INSERT_OPERAND (1, MG, *ip, regno); | |
12717 | break; | |
12718 | ||
12719 | case 'h': | |
12720 | INSERT_OPERAND (1, MH, *ip, regno); | |
12721 | break; | |
12722 | ||
12723 | case 'i': | |
12724 | INSERT_OPERAND (1, MI, *ip, regno); | |
12725 | break; | |
12726 | ||
12727 | case 'j': | |
12728 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12729 | break; | |
12730 | ||
12731 | case 'l': | |
12732 | INSERT_OPERAND (1, ML, *ip, regno); | |
12733 | break; | |
12734 | ||
12735 | case 'm': | |
12736 | INSERT_OPERAND (1, MM, *ip, regno); | |
12737 | break; | |
12738 | ||
12739 | case 'n': | |
12740 | INSERT_OPERAND (1, MN, *ip, regno); | |
12741 | break; | |
12742 | ||
12743 | case 'p': | |
12744 | INSERT_OPERAND (1, MP, *ip, regno); | |
12745 | break; | |
12746 | ||
12747 | case 'q': | |
12748 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12749 | break; | |
12750 | ||
12751 | case 'a': /* Do nothing. */ | |
12752 | case 's': /* Do nothing. */ | |
12753 | case 't': /* Do nothing. */ | |
12754 | case 'x': /* Do nothing. */ | |
12755 | case 'y': /* Do nothing. */ | |
12756 | case 'z': /* Do nothing. */ | |
12757 | break; | |
12758 | ||
12759 | default: | |
12760 | internalError (); | |
12761 | } | |
12762 | continue; | |
12763 | ||
12764 | case 'A': | |
12765 | { | |
12766 | bfd_reloc_code_real_type r[3]; | |
12767 | expressionS ep; | |
12768 | int imm; | |
12769 | ||
12770 | /* Check whether there is only a single bracketed | |
12771 | expression left. If so, it must be the base register | |
12772 | and the constant must be zero. */ | |
12773 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12774 | { | |
12775 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12776 | continue; | |
12777 | } | |
12778 | ||
12779 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12780 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12781 | break; | |
12782 | ||
12783 | imm = ep.X_add_number >> 2; | |
12784 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12785 | } | |
12786 | s = expr_end; | |
12787 | continue; | |
12788 | ||
12789 | case 'B': | |
12790 | { | |
12791 | bfd_reloc_code_real_type r[3]; | |
12792 | expressionS ep; | |
12793 | int imm; | |
12794 | ||
12795 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12796 | || ep.X_op != O_constant) | |
12797 | break; | |
12798 | ||
12799 | for (imm = 0; imm < 8; imm++) | |
12800 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12801 | break; | |
12802 | if (imm >= 8) | |
12803 | break; | |
12804 | ||
12805 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12806 | } | |
12807 | s = expr_end; | |
12808 | continue; | |
12809 | ||
12810 | case 'C': | |
12811 | { | |
12812 | bfd_reloc_code_real_type r[3]; | |
12813 | expressionS ep; | |
12814 | int imm; | |
12815 | ||
12816 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12817 | || ep.X_op != O_constant) | |
12818 | break; | |
12819 | ||
12820 | for (imm = 0; imm < 16; imm++) | |
12821 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12822 | break; | |
12823 | if (imm >= 16) | |
12824 | break; | |
12825 | ||
12826 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12827 | } | |
12828 | s = expr_end; | |
12829 | continue; | |
12830 | ||
12831 | case 'D': /* pc relative offset */ | |
12832 | case 'E': /* pc relative offset */ | |
12833 | my_getExpression (&offset_expr, s); | |
12834 | if (offset_expr.X_op == O_register) | |
12835 | break; | |
12836 | ||
40209cad MR |
12837 | if (!forced_insn_length) |
12838 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12839 | else if (c == 'D') | |
12840 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12841 | else | |
12842 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12843 | s = expr_end; |
12844 | continue; | |
12845 | ||
12846 | case 'F': | |
12847 | { | |
12848 | bfd_reloc_code_real_type r[3]; | |
12849 | expressionS ep; | |
12850 | int imm; | |
12851 | ||
12852 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12853 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12854 | break; | |
12855 | ||
12856 | imm = ep.X_add_number; | |
12857 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12858 | } | |
12859 | s = expr_end; | |
12860 | continue; | |
12861 | ||
12862 | case 'G': | |
12863 | { | |
12864 | bfd_reloc_code_real_type r[3]; | |
12865 | expressionS ep; | |
12866 | int imm; | |
12867 | ||
12868 | /* Check whether there is only a single bracketed | |
12869 | expression left. If so, it must be the base register | |
12870 | and the constant must be zero. */ | |
12871 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12872 | { | |
12873 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12874 | continue; | |
12875 | } | |
12876 | ||
12877 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12878 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12879 | break; | |
12880 | ||
12881 | imm = ep.X_add_number & 15; | |
12882 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12883 | } | |
12884 | s = expr_end; | |
12885 | continue; | |
12886 | ||
12887 | case 'H': | |
12888 | { | |
12889 | bfd_reloc_code_real_type r[3]; | |
12890 | expressionS ep; | |
12891 | int imm; | |
12892 | ||
12893 | /* Check whether there is only a single bracketed | |
12894 | expression left. If so, it must be the base register | |
12895 | and the constant must be zero. */ | |
12896 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12897 | { | |
12898 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12899 | continue; | |
12900 | } | |
12901 | ||
12902 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12903 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12904 | break; | |
12905 | ||
12906 | imm = ep.X_add_number >> 1; | |
12907 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12908 | } | |
12909 | s = expr_end; | |
12910 | continue; | |
12911 | ||
12912 | case 'I': | |
12913 | { | |
12914 | bfd_reloc_code_real_type r[3]; | |
12915 | expressionS ep; | |
12916 | int imm; | |
12917 | ||
12918 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12919 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12920 | break; | |
12921 | ||
12922 | imm = ep.X_add_number & 127; | |
12923 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12924 | } | |
12925 | s = expr_end; | |
12926 | continue; | |
12927 | ||
12928 | case 'J': | |
12929 | { | |
12930 | bfd_reloc_code_real_type r[3]; | |
12931 | expressionS ep; | |
12932 | int imm; | |
12933 | ||
12934 | /* Check whether there is only a single bracketed | |
12935 | expression left. If so, it must be the base register | |
12936 | and the constant must be zero. */ | |
12937 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12938 | { | |
12939 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12940 | continue; | |
12941 | } | |
12942 | ||
12943 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12944 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12945 | break; | |
12946 | ||
12947 | imm = ep.X_add_number >> 2; | |
12948 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12949 | } | |
12950 | s = expr_end; | |
12951 | continue; | |
12952 | ||
12953 | case 'L': | |
12954 | { | |
12955 | bfd_reloc_code_real_type r[3]; | |
12956 | expressionS ep; | |
12957 | int imm; | |
12958 | ||
12959 | /* Check whether there is only a single bracketed | |
12960 | expression left. If so, it must be the base register | |
12961 | and the constant must be zero. */ | |
12962 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12963 | { | |
12964 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12965 | continue; | |
12966 | } | |
12967 | ||
12968 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12969 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12970 | break; | |
12971 | ||
12972 | imm = ep.X_add_number; | |
12973 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12974 | } | |
12975 | s = expr_end; | |
12976 | continue; | |
12977 | ||
12978 | case 'M': | |
12979 | { | |
12980 | bfd_reloc_code_real_type r[3]; | |
12981 | expressionS ep; | |
12982 | int imm; | |
12983 | ||
12984 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12985 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12986 | break; | |
12987 | ||
12988 | imm = ep.X_add_number & 7; | |
12989 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12990 | } | |
12991 | s = expr_end; | |
12992 | continue; | |
12993 | ||
12994 | case 'N': /* Register list for lwm and swm. */ | |
12995 | { | |
12996 | /* A comma-separated list of registers and/or | |
12997 | dash-separated contiguous ranges including | |
12998 | both ra and a set of one or more registers | |
12999 | starting at s0 up to s3 which have to be | |
13000 | consecutive, e.g.: | |
13001 | ||
13002 | s0, ra | |
13003 | s0, s1, ra, s2, s3 | |
13004 | s0-s2, ra | |
13005 | ||
13006 | and any permutations of these. */ | |
13007 | unsigned int reglist; | |
13008 | int imm; | |
13009 | ||
13010 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13011 | break; | |
13012 | ||
13013 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13014 | break; | |
13015 | ||
13016 | reglist = (reglist >> 17) & 7; | |
13017 | reglist += 1; | |
13018 | if ((reglist & -reglist) != reglist) | |
13019 | break; | |
252b5132 | 13020 | |
df58fc94 RS |
13021 | imm = ffs (reglist) - 1; |
13022 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13023 | } | |
13024 | continue; | |
252b5132 | 13025 | |
df58fc94 RS |
13026 | case 'O': /* sdbbp 4-bit code. */ |
13027 | { | |
13028 | bfd_reloc_code_real_type r[3]; | |
13029 | expressionS ep; | |
13030 | int imm; | |
13031 | ||
13032 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13033 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13034 | break; | |
13035 | ||
13036 | imm = ep.X_add_number; | |
13037 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13038 | } |
df58fc94 RS |
13039 | s = expr_end; |
13040 | continue; | |
252b5132 | 13041 | |
df58fc94 RS |
13042 | case 'P': |
13043 | { | |
13044 | bfd_reloc_code_real_type r[3]; | |
13045 | expressionS ep; | |
13046 | int imm; | |
5e0116d5 | 13047 | |
df58fc94 RS |
13048 | if (my_getSmallExpression (&ep, r, s) > 0 |
13049 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13050 | break; | |
5e0116d5 | 13051 | |
df58fc94 RS |
13052 | imm = ep.X_add_number >> 2; |
13053 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13054 | } | |
13055 | s = expr_end; | |
13056 | continue; | |
5e0116d5 | 13057 | |
df58fc94 RS |
13058 | case 'Q': |
13059 | { | |
13060 | bfd_reloc_code_real_type r[3]; | |
13061 | expressionS ep; | |
13062 | int imm; | |
5e0116d5 | 13063 | |
df58fc94 RS |
13064 | if (my_getSmallExpression (&ep, r, s) > 0 |
13065 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13066 | break; | |
252b5132 | 13067 | |
df58fc94 RS |
13068 | imm = ep.X_add_number >> 2; |
13069 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13070 | } | |
13071 | s = expr_end; | |
13072 | continue; | |
4614d845 | 13073 | |
df58fc94 RS |
13074 | case 'U': |
13075 | { | |
13076 | bfd_reloc_code_real_type r[3]; | |
13077 | expressionS ep; | |
13078 | int imm; | |
13079 | ||
13080 | /* Check whether there is only a single bracketed | |
13081 | expression left. If so, it must be the base register | |
13082 | and the constant must be zero. */ | |
13083 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13084 | { | |
13085 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13086 | continue; | |
13087 | } | |
13088 | ||
13089 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13090 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13091 | break; | |
13092 | ||
13093 | imm = ep.X_add_number >> 2; | |
13094 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13095 | } | |
13096 | s = expr_end; | |
5e0116d5 | 13097 | continue; |
252b5132 | 13098 | |
df58fc94 RS |
13099 | case 'W': |
13100 | { | |
13101 | bfd_reloc_code_real_type r[3]; | |
13102 | expressionS ep; | |
13103 | int imm; | |
252b5132 | 13104 | |
df58fc94 RS |
13105 | if (my_getSmallExpression (&ep, r, s) > 0 |
13106 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13107 | break; | |
252b5132 | 13108 | |
df58fc94 RS |
13109 | imm = ep.X_add_number >> 2; |
13110 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13111 | } | |
13112 | s = expr_end; | |
13113 | continue; | |
252b5132 | 13114 | |
df58fc94 RS |
13115 | case 'X': |
13116 | { | |
13117 | bfd_reloc_code_real_type r[3]; | |
13118 | expressionS ep; | |
13119 | int imm; | |
252b5132 | 13120 | |
df58fc94 RS |
13121 | if (my_getSmallExpression (&ep, r, s) > 0 |
13122 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13123 | break; | |
252b5132 | 13124 | |
df58fc94 RS |
13125 | imm = ep.X_add_number; |
13126 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13127 | } | |
13128 | s = expr_end; | |
13129 | continue; | |
252b5132 | 13130 | |
df58fc94 RS |
13131 | case 'Y': |
13132 | { | |
13133 | bfd_reloc_code_real_type r[3]; | |
13134 | expressionS ep; | |
13135 | int imm; | |
156c2f8b | 13136 | |
df58fc94 RS |
13137 | if (my_getSmallExpression (&ep, r, s) > 0 |
13138 | || expr_const_in_range (&ep, -2, 2, 2) | |
13139 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13140 | break; | |
156c2f8b | 13141 | |
df58fc94 RS |
13142 | imm = ep.X_add_number >> 2; |
13143 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13144 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13145 | } | |
13146 | s = expr_end; | |
13147 | continue; | |
60b63b72 | 13148 | |
df58fc94 RS |
13149 | case 'Z': |
13150 | { | |
13151 | bfd_reloc_code_real_type r[3]; | |
13152 | expressionS ep; | |
13153 | ||
13154 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13155 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13156 | break; | |
13157 | } | |
13158 | s = expr_end; | |
13159 | continue; | |
13160 | ||
13161 | default: | |
13162 | as_bad (_("Internal error: bad microMIPS opcode " | |
13163 | "(unknown extension operand type `m%c'): %s %s"), | |
13164 | *args, insn->name, insn->args); | |
13165 | /* Further processing is fruitless. */ | |
13166 | return; | |
60b63b72 | 13167 | } |
df58fc94 | 13168 | break; |
60b63b72 | 13169 | |
df58fc94 RS |
13170 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13171 | gas_assert (mips_opts.micromips); | |
13172 | { | |
13173 | /* A comma-separated list of registers and/or | |
13174 | dash-separated contiguous ranges including | |
13175 | at least one of ra and a set of one or more | |
13176 | registers starting at s0 up to s7 and then | |
13177 | s8 which have to be consecutive, e.g.: | |
13178 | ||
13179 | ra | |
13180 | s0 | |
13181 | ra, s0, s1, s2 | |
13182 | s0-s8 | |
13183 | s0-s5, ra | |
13184 | ||
13185 | and any permutations of these. */ | |
13186 | unsigned int reglist; | |
13187 | int imm; | |
13188 | int ra; | |
13189 | ||
13190 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13191 | break; | |
13192 | ||
13193 | if ((reglist & 0x3f00ffff) != 0) | |
13194 | break; | |
13195 | ||
13196 | ra = (reglist >> 27) & 0x10; | |
13197 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13198 | reglist += 1; | |
13199 | if ((reglist & -reglist) != reglist) | |
13200 | break; | |
13201 | ||
13202 | imm = (ffs (reglist) - 1) | ra; | |
13203 | INSERT_OPERAND (1, RT, *ip, imm); | |
13204 | imm_expr.X_op = O_absent; | |
13205 | } | |
60b63b72 RS |
13206 | continue; |
13207 | ||
df58fc94 RS |
13208 | case '|': /* 4-bit trap code. */ |
13209 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13210 | my_getExpression (&imm_expr, s); |
13211 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13212 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13213 | > MICROMIPSOP_MASK_TRAP) |
13214 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13215 | (unsigned long) imm_expr.X_add_number, | |
13216 | ip->insn_mo->name); | |
13217 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13218 | imm_expr.X_op = O_absent; |
13219 | s = expr_end; | |
13220 | continue; | |
13221 | ||
252b5132 | 13222 | default: |
f71d0d44 | 13223 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13224 | internalError (); |
13225 | } | |
13226 | break; | |
13227 | } | |
13228 | /* Args don't match. */ | |
df58fc94 RS |
13229 | s = argsStart; |
13230 | insn_error = _("Illegal operands"); | |
13231 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13232 | { |
13233 | ++insn; | |
252b5132 RH |
13234 | continue; |
13235 | } | |
df58fc94 RS |
13236 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13237 | { | |
13238 | gas_assert (firstinsn); | |
13239 | need_delay_slot_ok = FALSE; | |
13240 | past = insn + 1; | |
13241 | insn = firstinsn; | |
13242 | continue; | |
13243 | } | |
252b5132 RH |
13244 | return; |
13245 | } | |
13246 | } | |
13247 | ||
0499d65b TS |
13248 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13249 | ||
252b5132 RH |
13250 | /* This routine assembles an instruction into its binary format when |
13251 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13252 | global variables imm_reloc or offset_reloc to the type of relocation |
13253 | to do if one of the operands is an address expression. It also sets | |
13254 | forced_insn_length to the resulting instruction size in bytes if the | |
13255 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13256 | |
13257 | static void | |
17a2f251 | 13258 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13259 | { |
13260 | char *s; | |
13261 | const char *args; | |
13262 | struct mips_opcode *insn; | |
13263 | char *argsstart; | |
13264 | unsigned int regno; | |
13265 | unsigned int lastregno = 0; | |
13266 | char *s_reset; | |
d6f16593 | 13267 | size_t i; |
252b5132 RH |
13268 | |
13269 | insn_error = NULL; | |
13270 | ||
df58fc94 | 13271 | forced_insn_length = 0; |
252b5132 | 13272 | |
3882b010 | 13273 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13274 | ; |
13275 | switch (*s) | |
13276 | { | |
13277 | case '\0': | |
13278 | break; | |
13279 | ||
13280 | case ' ': | |
13281 | *s++ = '\0'; | |
13282 | break; | |
13283 | ||
13284 | case '.': | |
13285 | if (s[1] == 't' && s[2] == ' ') | |
13286 | { | |
13287 | *s = '\0'; | |
df58fc94 | 13288 | forced_insn_length = 2; |
252b5132 RH |
13289 | s += 3; |
13290 | break; | |
13291 | } | |
13292 | else if (s[1] == 'e' && s[2] == ' ') | |
13293 | { | |
13294 | *s = '\0'; | |
df58fc94 | 13295 | forced_insn_length = 4; |
252b5132 RH |
13296 | s += 3; |
13297 | break; | |
13298 | } | |
13299 | /* Fall through. */ | |
13300 | default: | |
13301 | insn_error = _("unknown opcode"); | |
13302 | return; | |
13303 | } | |
13304 | ||
df58fc94 RS |
13305 | if (mips_opts.noautoextend && !forced_insn_length) |
13306 | forced_insn_length = 2; | |
252b5132 RH |
13307 | |
13308 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13309 | { | |
13310 | insn_error = _("unrecognized opcode"); | |
13311 | return; | |
13312 | } | |
13313 | ||
13314 | argsstart = s; | |
13315 | for (;;) | |
13316 | { | |
9b3f89ee TS |
13317 | bfd_boolean ok; |
13318 | ||
9c2799c2 | 13319 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13320 | |
037b32b9 | 13321 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13322 | if (! ok) |
13323 | { | |
13324 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13325 | && strcmp (insn->name, insn[1].name) == 0) | |
13326 | { | |
13327 | ++insn; | |
13328 | continue; | |
13329 | } | |
13330 | else | |
13331 | { | |
13332 | if (!insn_error) | |
13333 | { | |
13334 | static char buf[100]; | |
13335 | sprintf (buf, | |
7bd942df | 13336 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13337 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13338 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13339 | insn_error = buf; | |
13340 | } | |
13341 | return; | |
13342 | } | |
13343 | } | |
13344 | ||
1e915849 | 13345 | create_insn (ip, insn); |
252b5132 | 13346 | imm_expr.X_op = O_absent; |
f6688943 TS |
13347 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13348 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13349 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13350 | imm2_expr.X_op = O_absent; |
252b5132 | 13351 | offset_expr.X_op = O_absent; |
f6688943 TS |
13352 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13353 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13354 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13355 | for (args = insn->args; 1; ++args) |
13356 | { | |
13357 | int c; | |
13358 | ||
13359 | if (*s == ' ') | |
13360 | ++s; | |
13361 | ||
13362 | /* In this switch statement we call break if we did not find | |
13363 | a match, continue if we did find a match, or return if we | |
13364 | are done. */ | |
13365 | ||
13366 | c = *args; | |
13367 | switch (c) | |
13368 | { | |
13369 | case '\0': | |
13370 | if (*s == '\0') | |
13371 | { | |
13372 | /* Stuff the immediate value in now, if we can. */ | |
13373 | if (imm_expr.X_op == O_constant | |
f6688943 | 13374 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13375 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13376 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13377 | && insn->pinfo != INSN_MACRO) |
13378 | { | |
d6f16593 MR |
13379 | valueT tmp; |
13380 | ||
13381 | switch (*offset_reloc) | |
13382 | { | |
13383 | case BFD_RELOC_MIPS16_HI16_S: | |
13384 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13385 | break; | |
13386 | ||
13387 | case BFD_RELOC_MIPS16_HI16: | |
13388 | tmp = imm_expr.X_add_number >> 16; | |
13389 | break; | |
13390 | ||
13391 | case BFD_RELOC_MIPS16_LO16: | |
13392 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13393 | - 0x8000; | |
13394 | break; | |
13395 | ||
13396 | case BFD_RELOC_UNUSED: | |
13397 | tmp = imm_expr.X_add_number; | |
13398 | break; | |
13399 | ||
13400 | default: | |
13401 | internalError (); | |
13402 | } | |
d6f16593 | 13403 | |
c4e7957c | 13404 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
43c0598f RS |
13405 | *offset_reloc, tmp, forced_insn_length, |
13406 | &ip->insn_opcode); | |
252b5132 | 13407 | imm_expr.X_op = O_absent; |
f6688943 | 13408 | *imm_reloc = BFD_RELOC_UNUSED; |
43c0598f | 13409 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13410 | } |
13411 | ||
13412 | return; | |
13413 | } | |
13414 | break; | |
13415 | ||
13416 | case ',': | |
13417 | if (*s++ == c) | |
13418 | continue; | |
13419 | s--; | |
13420 | switch (*++args) | |
13421 | { | |
13422 | case 'v': | |
bf12938e | 13423 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13424 | continue; |
13425 | case 'w': | |
bf12938e | 13426 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13427 | continue; |
13428 | } | |
13429 | break; | |
13430 | ||
13431 | case '(': | |
13432 | case ')': | |
13433 | if (*s++ == c) | |
13434 | continue; | |
13435 | break; | |
13436 | ||
13437 | case 'v': | |
13438 | case 'w': | |
13439 | if (s[0] != '$') | |
13440 | { | |
13441 | if (c == 'v') | |
bf12938e | 13442 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13443 | else |
bf12938e | 13444 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13445 | ++args; |
13446 | continue; | |
13447 | } | |
13448 | /* Fall through. */ | |
13449 | case 'x': | |
13450 | case 'y': | |
13451 | case 'z': | |
13452 | case 'Z': | |
13453 | case '0': | |
13454 | case 'S': | |
13455 | case 'R': | |
13456 | case 'X': | |
13457 | case 'Y': | |
707bfff6 TS |
13458 | s_reset = s; |
13459 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13460 | { |
707bfff6 | 13461 | if (c == 'v' || c == 'w') |
85b51719 | 13462 | { |
707bfff6 | 13463 | if (c == 'v') |
a9e24354 | 13464 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13465 | else |
a9e24354 | 13466 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13467 | ++args; |
13468 | continue; | |
85b51719 | 13469 | } |
707bfff6 | 13470 | break; |
252b5132 RH |
13471 | } |
13472 | ||
13473 | if (*s == ' ') | |
13474 | ++s; | |
13475 | if (args[1] != *s) | |
13476 | { | |
13477 | if (c == 'v' || c == 'w') | |
13478 | { | |
13479 | regno = mips16_to_32_reg_map[lastregno]; | |
13480 | s = s_reset; | |
f9419b05 | 13481 | ++args; |
252b5132 RH |
13482 | } |
13483 | } | |
13484 | ||
13485 | switch (c) | |
13486 | { | |
13487 | case 'x': | |
13488 | case 'y': | |
13489 | case 'z': | |
13490 | case 'v': | |
13491 | case 'w': | |
13492 | case 'Z': | |
13493 | regno = mips32_to_16_reg_map[regno]; | |
13494 | break; | |
13495 | ||
13496 | case '0': | |
13497 | if (regno != 0) | |
13498 | regno = ILLEGAL_REG; | |
13499 | break; | |
13500 | ||
13501 | case 'S': | |
13502 | if (regno != SP) | |
13503 | regno = ILLEGAL_REG; | |
13504 | break; | |
13505 | ||
13506 | case 'R': | |
13507 | if (regno != RA) | |
13508 | regno = ILLEGAL_REG; | |
13509 | break; | |
13510 | ||
13511 | case 'X': | |
13512 | case 'Y': | |
741fe287 MR |
13513 | if (regno == AT && mips_opts.at) |
13514 | { | |
13515 | if (mips_opts.at == ATREG) | |
13516 | as_warn (_("used $at without \".set noat\"")); | |
13517 | else | |
13518 | as_warn (_("used $%u with \".set at=$%u\""), | |
13519 | regno, mips_opts.at); | |
13520 | } | |
252b5132 RH |
13521 | break; |
13522 | ||
13523 | default: | |
13524 | internalError (); | |
13525 | } | |
13526 | ||
13527 | if (regno == ILLEGAL_REG) | |
13528 | break; | |
13529 | ||
13530 | switch (c) | |
13531 | { | |
13532 | case 'x': | |
13533 | case 'v': | |
bf12938e | 13534 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13535 | break; |
13536 | case 'y': | |
13537 | case 'w': | |
bf12938e | 13538 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13539 | break; |
13540 | case 'z': | |
bf12938e | 13541 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13542 | break; |
13543 | case 'Z': | |
bf12938e | 13544 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13545 | case '0': |
13546 | case 'S': | |
13547 | case 'R': | |
13548 | break; | |
13549 | case 'X': | |
bf12938e | 13550 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13551 | break; |
13552 | case 'Y': | |
13553 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13554 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13555 | break; |
13556 | default: | |
13557 | internalError (); | |
13558 | } | |
13559 | ||
13560 | lastregno = regno; | |
13561 | continue; | |
13562 | ||
13563 | case 'P': | |
13564 | if (strncmp (s, "$pc", 3) == 0) | |
13565 | { | |
13566 | s += 3; | |
13567 | continue; | |
13568 | } | |
13569 | break; | |
13570 | ||
252b5132 RH |
13571 | case '5': |
13572 | case 'H': | |
13573 | case 'W': | |
13574 | case 'D': | |
13575 | case 'j': | |
252b5132 RH |
13576 | case 'V': |
13577 | case 'C': | |
13578 | case 'U': | |
13579 | case 'k': | |
13580 | case 'K': | |
d6f16593 MR |
13581 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13582 | if (i > 0) | |
252b5132 | 13583 | { |
d6f16593 | 13584 | if (imm_expr.X_op != O_constant) |
252b5132 | 13585 | { |
df58fc94 | 13586 | forced_insn_length = 4; |
5c04167a | 13587 | ip->insn_opcode |= MIPS16_EXTEND; |
252b5132 | 13588 | } |
d6f16593 MR |
13589 | else |
13590 | { | |
13591 | /* We need to relax this instruction. */ | |
13592 | *offset_reloc = *imm_reloc; | |
13593 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13594 | } | |
13595 | s = expr_end; | |
13596 | continue; | |
252b5132 | 13597 | } |
d6f16593 MR |
13598 | *imm_reloc = BFD_RELOC_UNUSED; |
13599 | /* Fall through. */ | |
13600 | case '<': | |
13601 | case '>': | |
13602 | case '[': | |
13603 | case ']': | |
13604 | case '4': | |
13605 | case '8': | |
13606 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13607 | if (imm_expr.X_op == O_register) |
13608 | { | |
13609 | /* What we thought was an expression turned out to | |
13610 | be a register. */ | |
13611 | ||
13612 | if (s[0] == '(' && args[1] == '(') | |
13613 | { | |
13614 | /* It looks like the expression was omitted | |
13615 | before a register indirection, which means | |
13616 | that the expression is implicitly zero. We | |
13617 | still set up imm_expr, so that we handle | |
13618 | explicit extensions correctly. */ | |
13619 | imm_expr.X_op = O_constant; | |
13620 | imm_expr.X_add_number = 0; | |
f6688943 | 13621 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13622 | continue; |
13623 | } | |
13624 | ||
13625 | break; | |
13626 | } | |
13627 | ||
13628 | /* We need to relax this instruction. */ | |
f6688943 | 13629 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13630 | s = expr_end; |
13631 | continue; | |
13632 | ||
13633 | case 'p': | |
13634 | case 'q': | |
13635 | case 'A': | |
13636 | case 'B': | |
13637 | case 'E': | |
13638 | /* We use offset_reloc rather than imm_reloc for the PC | |
13639 | relative operands. This lets macros with both | |
13640 | immediate and address operands work correctly. */ | |
13641 | my_getExpression (&offset_expr, s); | |
13642 | ||
13643 | if (offset_expr.X_op == O_register) | |
13644 | break; | |
13645 | ||
13646 | /* We need to relax this instruction. */ | |
f6688943 | 13647 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13648 | s = expr_end; |
13649 | continue; | |
13650 | ||
13651 | case '6': /* break code */ | |
13652 | my_getExpression (&imm_expr, s); | |
13653 | check_absolute_expr (ip, &imm_expr); | |
13654 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13655 | as_warn (_("Invalid value for `%s' (%lu)"), |
13656 | ip->insn_mo->name, | |
13657 | (unsigned long) imm_expr.X_add_number); | |
13658 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13659 | imm_expr.X_op = O_absent; |
13660 | s = expr_end; | |
13661 | continue; | |
13662 | ||
13663 | case 'a': /* 26 bit address */ | |
13664 | my_getExpression (&offset_expr, s); | |
13665 | s = expr_end; | |
f6688943 | 13666 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13667 | ip->insn_opcode <<= 16; |
13668 | continue; | |
13669 | ||
13670 | case 'l': /* register list for entry macro */ | |
13671 | case 'L': /* register list for exit macro */ | |
13672 | { | |
13673 | int mask; | |
13674 | ||
13675 | if (c == 'l') | |
13676 | mask = 0; | |
13677 | else | |
13678 | mask = 7 << 3; | |
13679 | while (*s != '\0') | |
13680 | { | |
707bfff6 | 13681 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13682 | |
13683 | while (*s == ' ' || *s == ',') | |
13684 | ++s; | |
707bfff6 | 13685 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13686 | freg = 0; |
707bfff6 TS |
13687 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13688 | freg = 1; | |
252b5132 RH |
13689 | else |
13690 | { | |
707bfff6 TS |
13691 | as_bad (_("can't parse register list")); |
13692 | break; | |
252b5132 RH |
13693 | } |
13694 | if (*s == ' ') | |
13695 | ++s; | |
13696 | if (*s != '-') | |
13697 | reg2 = reg1; | |
13698 | else | |
13699 | { | |
13700 | ++s; | |
707bfff6 TS |
13701 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13702 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13703 | { |
707bfff6 TS |
13704 | as_bad (_("invalid register list")); |
13705 | break; | |
252b5132 RH |
13706 | } |
13707 | } | |
13708 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13709 | { | |
13710 | mask &= ~ (7 << 3); | |
13711 | mask |= 5 << 3; | |
13712 | } | |
13713 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13714 | { | |
13715 | mask &= ~ (7 << 3); | |
13716 | mask |= 6 << 3; | |
13717 | } | |
13718 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13719 | mask |= (reg2 - 3) << 3; | |
13720 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13721 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13722 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13723 | mask |= 1; |
13724 | else | |
13725 | { | |
13726 | as_bad (_("invalid register list")); | |
13727 | break; | |
13728 | } | |
13729 | } | |
13730 | /* The mask is filled in in the opcode table for the | |
13731 | benefit of the disassembler. We remove it before | |
13732 | applying the actual mask. */ | |
13733 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13734 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13735 | } | |
13736 | continue; | |
13737 | ||
0499d65b TS |
13738 | case 'm': /* Register list for save insn. */ |
13739 | case 'M': /* Register list for restore insn. */ | |
13740 | { | |
5c04167a | 13741 | int opcode = ip->insn_opcode; |
0499d65b | 13742 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 13743 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13744 | |
13745 | while (*s != '\0') | |
13746 | { | |
13747 | unsigned int reg1, reg2; | |
13748 | ||
13749 | SKIP_SPACE_TABS (s); | |
13750 | while (*s == ',') | |
13751 | ++s; | |
13752 | SKIP_SPACE_TABS (s); | |
13753 | ||
13754 | my_getExpression (&imm_expr, s); | |
13755 | if (imm_expr.X_op == O_constant) | |
13756 | { | |
13757 | /* Handle the frame size. */ | |
13758 | if (seen_framesz) | |
13759 | { | |
13760 | as_bad (_("more than one frame size in list")); | |
13761 | break; | |
13762 | } | |
13763 | seen_framesz = 1; | |
13764 | framesz = imm_expr.X_add_number; | |
13765 | imm_expr.X_op = O_absent; | |
13766 | s = expr_end; | |
13767 | continue; | |
13768 | } | |
13769 | ||
707bfff6 | 13770 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13771 | { |
13772 | as_bad (_("can't parse register list")); | |
13773 | break; | |
13774 | } | |
0499d65b | 13775 | |
707bfff6 TS |
13776 | while (*s == ' ') |
13777 | ++s; | |
13778 | ||
0499d65b TS |
13779 | if (*s != '-') |
13780 | reg2 = reg1; | |
13781 | else | |
13782 | { | |
13783 | ++s; | |
707bfff6 TS |
13784 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13785 | || reg2 < reg1) | |
0499d65b TS |
13786 | { |
13787 | as_bad (_("can't parse register list")); | |
13788 | break; | |
13789 | } | |
0499d65b TS |
13790 | } |
13791 | ||
13792 | while (reg1 <= reg2) | |
13793 | { | |
13794 | if (reg1 >= 4 && reg1 <= 7) | |
13795 | { | |
3a93f742 | 13796 | if (!seen_framesz) |
0499d65b | 13797 | /* args $a0-$a3 */ |
91d6fa6a | 13798 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13799 | else |
13800 | /* statics $a0-$a3 */ | |
13801 | statics |= 1 << (reg1 - 4); | |
13802 | } | |
13803 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13804 | { | |
13805 | /* $s0-$s8 */ | |
13806 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13807 | } | |
13808 | else if (reg1 == 31) | |
13809 | { | |
13810 | /* Add $ra to insn. */ | |
13811 | opcode |= 0x40; | |
13812 | } | |
13813 | else | |
13814 | { | |
13815 | as_bad (_("unexpected register in list")); | |
13816 | break; | |
13817 | } | |
13818 | if (++reg1 == 24) | |
13819 | reg1 = 30; | |
13820 | } | |
13821 | } | |
13822 | ||
13823 | /* Encode args/statics combination. */ | |
91d6fa6a | 13824 | if (nargs & statics) |
0499d65b | 13825 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13826 | else if (nargs == 0xf) |
0499d65b TS |
13827 | /* All $a0-$a3 are args. */ |
13828 | opcode |= MIPS16_ALL_ARGS << 16; | |
13829 | else if (statics == 0xf) | |
13830 | /* All $a0-$a3 are statics. */ | |
13831 | opcode |= MIPS16_ALL_STATICS << 16; | |
13832 | else | |
13833 | { | |
13834 | int narg = 0, nstat = 0; | |
13835 | ||
13836 | /* Count arg registers. */ | |
91d6fa6a | 13837 | while (nargs & 0x1) |
0499d65b | 13838 | { |
91d6fa6a | 13839 | nargs >>= 1; |
0499d65b TS |
13840 | narg++; |
13841 | } | |
91d6fa6a | 13842 | if (nargs != 0) |
0499d65b TS |
13843 | as_bad (_("invalid arg register list")); |
13844 | ||
13845 | /* Count static registers. */ | |
13846 | while (statics & 0x8) | |
13847 | { | |
13848 | statics = (statics << 1) & 0xf; | |
13849 | nstat++; | |
13850 | } | |
13851 | if (statics != 0) | |
13852 | as_bad (_("invalid static register list")); | |
13853 | ||
13854 | /* Encode args/statics. */ | |
13855 | opcode |= ((narg << 2) | nstat) << 16; | |
13856 | } | |
13857 | ||
13858 | /* Encode $s0/$s1. */ | |
13859 | if (sregs & (1 << 0)) /* $s0 */ | |
13860 | opcode |= 0x20; | |
13861 | if (sregs & (1 << 1)) /* $s1 */ | |
13862 | opcode |= 0x10; | |
13863 | sregs >>= 2; | |
13864 | ||
13865 | if (sregs != 0) | |
13866 | { | |
13867 | /* Count regs $s2-$s8. */ | |
13868 | int nsreg = 0; | |
13869 | while (sregs & 1) | |
13870 | { | |
13871 | sregs >>= 1; | |
13872 | nsreg++; | |
13873 | } | |
13874 | if (sregs != 0) | |
13875 | as_bad (_("invalid static register list")); | |
13876 | /* Encode $s2-$s8. */ | |
13877 | opcode |= nsreg << 24; | |
13878 | } | |
13879 | ||
13880 | /* Encode frame size. */ | |
13881 | if (!seen_framesz) | |
13882 | as_bad (_("missing frame size")); | |
13883 | else if ((framesz & 7) != 0 || framesz < 0 | |
13884 | || framesz > 0xff * 8) | |
13885 | as_bad (_("invalid frame size")); | |
13886 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13887 | { | |
13888 | framesz /= 8; | |
13889 | opcode |= (((framesz & 0xf0) << 16) | |
13890 | | (framesz & 0x0f)); | |
13891 | } | |
13892 | ||
13893 | /* Finally build the instruction. */ | |
13894 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
13895 | opcode |= MIPS16_EXTEND; |
13896 | ip->insn_opcode = opcode; | |
0499d65b TS |
13897 | } |
13898 | continue; | |
13899 | ||
252b5132 RH |
13900 | case 'e': /* extend code */ |
13901 | my_getExpression (&imm_expr, s); | |
13902 | check_absolute_expr (ip, &imm_expr); | |
13903 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13904 | { | |
13905 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13906 | ip->insn_mo->name, | |
13907 | (unsigned long) imm_expr.X_add_number); | |
13908 | imm_expr.X_add_number &= 0x7ff; | |
13909 | } | |
13910 | ip->insn_opcode |= imm_expr.X_add_number; | |
13911 | imm_expr.X_op = O_absent; | |
13912 | s = expr_end; | |
13913 | continue; | |
13914 | ||
13915 | default: | |
13916 | internalError (); | |
13917 | } | |
13918 | break; | |
13919 | } | |
13920 | ||
13921 | /* Args don't match. */ | |
13922 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13923 | strcmp (insn->name, insn[1].name) == 0) | |
13924 | { | |
13925 | ++insn; | |
13926 | s = argsstart; | |
13927 | continue; | |
13928 | } | |
13929 | ||
13930 | insn_error = _("illegal operands"); | |
13931 | ||
13932 | return; | |
13933 | } | |
13934 | } | |
13935 | ||
13936 | /* This structure holds information we know about a mips16 immediate | |
13937 | argument type. */ | |
13938 | ||
e972090a NC |
13939 | struct mips16_immed_operand |
13940 | { | |
252b5132 RH |
13941 | /* The type code used in the argument string in the opcode table. */ |
13942 | int type; | |
13943 | /* The number of bits in the short form of the opcode. */ | |
13944 | int nbits; | |
13945 | /* The number of bits in the extended form of the opcode. */ | |
13946 | int extbits; | |
13947 | /* The amount by which the short form is shifted when it is used; | |
13948 | for example, the sw instruction has a shift count of 2. */ | |
13949 | int shift; | |
13950 | /* The amount by which the short form is shifted when it is stored | |
13951 | into the instruction code. */ | |
13952 | int op_shift; | |
13953 | /* Non-zero if the short form is unsigned. */ | |
13954 | int unsp; | |
13955 | /* Non-zero if the extended form is unsigned. */ | |
13956 | int extu; | |
13957 | /* Non-zero if the value is PC relative. */ | |
13958 | int pcrel; | |
13959 | }; | |
13960 | ||
13961 | /* The mips16 immediate operand types. */ | |
13962 | ||
13963 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13964 | { | |
13965 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13966 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13967 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13968 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13969 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13970 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13971 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13972 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13973 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13974 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13975 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13976 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13977 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13978 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13979 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13980 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13981 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13982 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13983 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13984 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13985 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13986 | }; | |
13987 | ||
13988 | #define MIPS16_NUM_IMMED \ | |
13989 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13990 | ||
5c04167a RS |
13991 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
13992 | extending it if necessary. The instruction in *INSN may | |
13993 | already be extended. | |
13994 | ||
43c0598f RS |
13995 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
13996 | if none. In the former case, VAL is a 16-bit number with no | |
13997 | defined signedness. | |
13998 | ||
13999 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14000 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14001 | |
14002 | static void | |
43c0598f RS |
14003 | mips16_immed (char *file, unsigned int line, int type, |
14004 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14005 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14006 | { |
3994f87e | 14007 | const struct mips16_immed_operand *op; |
252b5132 | 14008 | int mintiny, maxtiny; |
252b5132 RH |
14009 | |
14010 | op = mips16_immed_operands; | |
14011 | while (op->type != type) | |
14012 | { | |
14013 | ++op; | |
9c2799c2 | 14014 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14015 | } |
14016 | ||
14017 | if (op->unsp) | |
14018 | { | |
14019 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14020 | { | |
14021 | mintiny = 1; | |
14022 | maxtiny = 1 << op->nbits; | |
14023 | } | |
14024 | else | |
14025 | { | |
14026 | mintiny = 0; | |
14027 | maxtiny = (1 << op->nbits) - 1; | |
14028 | } | |
43c0598f RS |
14029 | if (reloc != BFD_RELOC_UNUSED) |
14030 | val &= 0xffff; | |
252b5132 RH |
14031 | } |
14032 | else | |
14033 | { | |
14034 | mintiny = - (1 << (op->nbits - 1)); | |
14035 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14036 | if (reloc != BFD_RELOC_UNUSED) |
14037 | val = SEXT_16BIT (val); | |
252b5132 RH |
14038 | } |
14039 | ||
14040 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14041 | if (type == 'p' || type == 'q') | |
14042 | val /= 2; | |
14043 | ||
14044 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14045 | || val < (mintiny << op->shift) | |
14046 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14047 | { |
14048 | /* We need an extended instruction. */ | |
14049 | if (user_insn_length == 2) | |
14050 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14051 | else | |
14052 | *insn |= MIPS16_EXTEND; | |
14053 | } | |
14054 | else if (user_insn_length == 4) | |
14055 | { | |
14056 | /* The operand doesn't force an unextended instruction to be extended. | |
14057 | Warn if the user wanted an extended instruction anyway. */ | |
14058 | *insn |= MIPS16_EXTEND; | |
14059 | as_warn_where (file, line, | |
14060 | _("extended operand requested but not required")); | |
14061 | } | |
252b5132 | 14062 | |
5c04167a | 14063 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14064 | { |
14065 | int insnval; | |
14066 | ||
252b5132 RH |
14067 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14068 | insnval <<= op->op_shift; | |
14069 | *insn |= insnval; | |
14070 | } | |
14071 | else | |
14072 | { | |
14073 | long minext, maxext; | |
14074 | int extval; | |
14075 | ||
43c0598f | 14076 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14077 | { |
43c0598f RS |
14078 | if (op->extu) |
14079 | { | |
14080 | minext = 0; | |
14081 | maxext = (1 << op->extbits) - 1; | |
14082 | } | |
14083 | else | |
14084 | { | |
14085 | minext = - (1 << (op->extbits - 1)); | |
14086 | maxext = (1 << (op->extbits - 1)) - 1; | |
14087 | } | |
14088 | if (val < minext || val > maxext) | |
14089 | as_bad_where (file, line, | |
14090 | _("operand value out of range for instruction")); | |
252b5132 | 14091 | } |
252b5132 | 14092 | |
252b5132 RH |
14093 | if (op->extbits == 16) |
14094 | { | |
14095 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14096 | val &= 0x1f; | |
14097 | } | |
14098 | else if (op->extbits == 15) | |
14099 | { | |
14100 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14101 | val &= 0xf; | |
14102 | } | |
14103 | else | |
14104 | { | |
14105 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14106 | val = 0; | |
14107 | } | |
14108 | ||
5c04167a | 14109 | *insn |= (extval << 16) | val; |
252b5132 RH |
14110 | } |
14111 | } | |
14112 | \f | |
d6f16593 | 14113 | struct percent_op_match |
ad8d3bb3 | 14114 | { |
5e0116d5 RS |
14115 | const char *str; |
14116 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14117 | }; |
14118 | ||
14119 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14120 | { |
5e0116d5 | 14121 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14122 | #ifdef OBJ_ELF |
5e0116d5 RS |
14123 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14124 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14125 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14126 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14127 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14128 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14129 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14130 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14131 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14132 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14133 | {"%half", BFD_RELOC_16}, | |
14134 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14135 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14136 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14137 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14138 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14139 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14140 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14141 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14142 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14143 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14144 | #endif |
5e0116d5 | 14145 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14146 | }; |
14147 | ||
d6f16593 MR |
14148 | static const struct percent_op_match mips16_percent_op[] = |
14149 | { | |
14150 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14151 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14152 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14153 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14154 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14155 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14156 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14157 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14158 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14159 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14160 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14161 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14162 | }; |
14163 | ||
252b5132 | 14164 | |
5e0116d5 RS |
14165 | /* Return true if *STR points to a relocation operator. When returning true, |
14166 | move *STR over the operator and store its relocation code in *RELOC. | |
14167 | Leave both *STR and *RELOC alone when returning false. */ | |
14168 | ||
14169 | static bfd_boolean | |
17a2f251 | 14170 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14171 | { |
d6f16593 MR |
14172 | const struct percent_op_match *percent_op; |
14173 | size_t limit, i; | |
14174 | ||
14175 | if (mips_opts.mips16) | |
14176 | { | |
14177 | percent_op = mips16_percent_op; | |
14178 | limit = ARRAY_SIZE (mips16_percent_op); | |
14179 | } | |
14180 | else | |
14181 | { | |
14182 | percent_op = mips_percent_op; | |
14183 | limit = ARRAY_SIZE (mips_percent_op); | |
14184 | } | |
76b3015f | 14185 | |
d6f16593 | 14186 | for (i = 0; i < limit; i++) |
5e0116d5 | 14187 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14188 | { |
3f98094e DJ |
14189 | int len = strlen (percent_op[i].str); |
14190 | ||
14191 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14192 | continue; | |
14193 | ||
5e0116d5 RS |
14194 | *str += strlen (percent_op[i].str); |
14195 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14196 | |
5e0116d5 RS |
14197 | /* Check whether the output BFD supports this relocation. |
14198 | If not, issue an error and fall back on something safe. */ | |
14199 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14200 | { |
20203fb9 | 14201 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14202 | percent_op[i].str); |
01a3f561 | 14203 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14204 | } |
5e0116d5 | 14205 | return TRUE; |
394f9b3a | 14206 | } |
5e0116d5 | 14207 | return FALSE; |
394f9b3a | 14208 | } |
ad8d3bb3 | 14209 | |
ad8d3bb3 | 14210 | |
5e0116d5 RS |
14211 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14212 | expression in *EP and the relocations in the array starting | |
14213 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14214 | |
01a3f561 | 14215 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14216 | |
5e0116d5 | 14217 | static size_t |
17a2f251 TS |
14218 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14219 | char *str) | |
ad8d3bb3 | 14220 | { |
5e0116d5 RS |
14221 | bfd_reloc_code_real_type reversed_reloc[3]; |
14222 | size_t reloc_index, i; | |
09b8f35a RS |
14223 | int crux_depth, str_depth; |
14224 | char *crux; | |
5e0116d5 RS |
14225 | |
14226 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14227 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14228 | of the main expression and with CRUX_DEPTH containing the number | |
14229 | of open brackets at that point. */ | |
14230 | reloc_index = -1; | |
14231 | str_depth = 0; | |
14232 | do | |
fb1b3232 | 14233 | { |
09b8f35a RS |
14234 | reloc_index++; |
14235 | crux = str; | |
14236 | crux_depth = str_depth; | |
14237 | ||
14238 | /* Skip over whitespace and brackets, keeping count of the number | |
14239 | of brackets. */ | |
14240 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14241 | if (*str++ == '(') | |
14242 | str_depth++; | |
5e0116d5 | 14243 | } |
09b8f35a RS |
14244 | while (*str == '%' |
14245 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14246 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14247 | |
09b8f35a | 14248 | my_getExpression (ep, crux); |
5e0116d5 | 14249 | str = expr_end; |
394f9b3a | 14250 | |
5e0116d5 | 14251 | /* Match every open bracket. */ |
09b8f35a | 14252 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14253 | if (*str++ == ')') |
09b8f35a | 14254 | crux_depth--; |
394f9b3a | 14255 | |
09b8f35a | 14256 | if (crux_depth > 0) |
20203fb9 | 14257 | as_bad (_("unclosed '('")); |
394f9b3a | 14258 | |
5e0116d5 | 14259 | expr_end = str; |
252b5132 | 14260 | |
01a3f561 | 14261 | if (reloc_index != 0) |
64bdfcaf RS |
14262 | { |
14263 | prev_reloc_op_frag = frag_now; | |
14264 | for (i = 0; i < reloc_index; i++) | |
14265 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14266 | } | |
fb1b3232 | 14267 | |
5e0116d5 | 14268 | return reloc_index; |
252b5132 RH |
14269 | } |
14270 | ||
14271 | static void | |
17a2f251 | 14272 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14273 | { |
14274 | char *save_in; | |
14275 | ||
14276 | save_in = input_line_pointer; | |
14277 | input_line_pointer = str; | |
14278 | expression (ep); | |
14279 | expr_end = input_line_pointer; | |
14280 | input_line_pointer = save_in; | |
252b5132 RH |
14281 | } |
14282 | ||
252b5132 | 14283 | char * |
17a2f251 | 14284 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14285 | { |
499ac353 | 14286 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14287 | } |
14288 | ||
14289 | void | |
17a2f251 | 14290 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14291 | { |
14292 | if (target_big_endian) | |
14293 | number_to_chars_bigendian (buf, val, n); | |
14294 | else | |
14295 | number_to_chars_littleendian (buf, val, n); | |
14296 | } | |
14297 | \f | |
ae948b86 | 14298 | #ifdef OBJ_ELF |
e013f690 TS |
14299 | static int support_64bit_objects(void) |
14300 | { | |
14301 | const char **list, **l; | |
aa3d8fdf | 14302 | int yes; |
e013f690 TS |
14303 | |
14304 | list = bfd_target_list (); | |
14305 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14306 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14307 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14308 | break; |
aa3d8fdf | 14309 | yes = (*l != NULL); |
e013f690 | 14310 | free (list); |
aa3d8fdf | 14311 | return yes; |
e013f690 | 14312 | } |
ae948b86 | 14313 | #endif /* OBJ_ELF */ |
e013f690 | 14314 | |
78849248 | 14315 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14316 | |
23fce1e3 NC |
14317 | enum options |
14318 | { | |
14319 | OPTION_MARCH = OPTION_MD_BASE, | |
14320 | OPTION_MTUNE, | |
14321 | OPTION_MIPS1, | |
14322 | OPTION_MIPS2, | |
14323 | OPTION_MIPS3, | |
14324 | OPTION_MIPS4, | |
14325 | OPTION_MIPS5, | |
14326 | OPTION_MIPS32, | |
14327 | OPTION_MIPS64, | |
14328 | OPTION_MIPS32R2, | |
14329 | OPTION_MIPS64R2, | |
14330 | OPTION_MIPS16, | |
14331 | OPTION_NO_MIPS16, | |
14332 | OPTION_MIPS3D, | |
14333 | OPTION_NO_MIPS3D, | |
14334 | OPTION_MDMX, | |
14335 | OPTION_NO_MDMX, | |
14336 | OPTION_DSP, | |
14337 | OPTION_NO_DSP, | |
14338 | OPTION_MT, | |
14339 | OPTION_NO_MT, | |
14340 | OPTION_SMARTMIPS, | |
14341 | OPTION_NO_SMARTMIPS, | |
14342 | OPTION_DSPR2, | |
14343 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14344 | OPTION_MICROMIPS, |
14345 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14346 | OPTION_MCU, |
14347 | OPTION_NO_MCU, | |
23fce1e3 NC |
14348 | OPTION_COMPAT_ARCH_BASE, |
14349 | OPTION_M4650, | |
14350 | OPTION_NO_M4650, | |
14351 | OPTION_M4010, | |
14352 | OPTION_NO_M4010, | |
14353 | OPTION_M4100, | |
14354 | OPTION_NO_M4100, | |
14355 | OPTION_M3900, | |
14356 | OPTION_NO_M3900, | |
14357 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14358 | OPTION_MNO_7000_HILO_FIX, |
14359 | OPTION_FIX_24K, | |
14360 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14361 | OPTION_FIX_LOONGSON2F_JUMP, |
14362 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14363 | OPTION_FIX_LOONGSON2F_NOP, | |
14364 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14365 | OPTION_FIX_VR4120, |
14366 | OPTION_NO_FIX_VR4120, | |
14367 | OPTION_FIX_VR4130, | |
14368 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14369 | OPTION_FIX_CN63XXP1, |
14370 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14371 | OPTION_TRAP, |
14372 | OPTION_BREAK, | |
14373 | OPTION_EB, | |
14374 | OPTION_EL, | |
14375 | OPTION_FP32, | |
14376 | OPTION_GP32, | |
14377 | OPTION_CONSTRUCT_FLOATS, | |
14378 | OPTION_NO_CONSTRUCT_FLOATS, | |
14379 | OPTION_FP64, | |
14380 | OPTION_GP64, | |
14381 | OPTION_RELAX_BRANCH, | |
14382 | OPTION_NO_RELAX_BRANCH, | |
14383 | OPTION_MSHARED, | |
14384 | OPTION_MNO_SHARED, | |
14385 | OPTION_MSYM32, | |
14386 | OPTION_MNO_SYM32, | |
14387 | OPTION_SOFT_FLOAT, | |
14388 | OPTION_HARD_FLOAT, | |
14389 | OPTION_SINGLE_FLOAT, | |
14390 | OPTION_DOUBLE_FLOAT, | |
14391 | OPTION_32, | |
14392 | #ifdef OBJ_ELF | |
14393 | OPTION_CALL_SHARED, | |
14394 | OPTION_CALL_NONPIC, | |
14395 | OPTION_NON_SHARED, | |
14396 | OPTION_XGOT, | |
14397 | OPTION_MABI, | |
14398 | OPTION_N32, | |
14399 | OPTION_64, | |
14400 | OPTION_MDEBUG, | |
14401 | OPTION_NO_MDEBUG, | |
14402 | OPTION_PDR, | |
14403 | OPTION_NO_PDR, | |
14404 | OPTION_MVXWORKS_PIC, | |
14405 | #endif /* OBJ_ELF */ | |
14406 | OPTION_END_OF_ENUM | |
14407 | }; | |
14408 | ||
e972090a NC |
14409 | struct option md_longopts[] = |
14410 | { | |
f9b4148d | 14411 | /* Options which specify architecture. */ |
f9b4148d | 14412 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14413 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14414 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14415 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14416 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14417 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14418 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14419 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14420 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14421 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14422 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14423 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14424 | |
14425 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14426 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14427 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14428 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14429 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14430 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14431 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14432 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14433 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14434 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14435 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14436 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14437 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14438 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14439 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14440 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14441 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14442 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14443 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14444 | |
14445 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14446 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14447 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14448 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14449 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14450 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14451 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14452 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14453 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14454 | ||
14455 | /* Options which enable bug fixes. */ | |
f9b4148d | 14456 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14457 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14458 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14459 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14460 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14461 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14462 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14463 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14464 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14465 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14466 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14467 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14468 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14469 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14470 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14471 | |
14472 | /* Miscellaneous options. */ | |
252b5132 RH |
14473 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14474 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14475 | {"break", no_argument, NULL, OPTION_BREAK}, |
14476 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14477 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14478 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14479 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14480 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14481 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14482 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14483 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14484 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14485 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14486 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14487 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14488 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14489 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14490 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14491 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14492 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14493 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14494 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14495 | |
14496 | /* Strictly speaking this next option is ELF specific, | |
14497 | but we allow it for other ports as well in order to | |
14498 | make testing easier. */ | |
14499 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14500 | |
f9b4148d | 14501 | /* ELF-specific options. */ |
156c2f8b | 14502 | #ifdef OBJ_ELF |
156c2f8b NC |
14503 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14504 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14505 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14506 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14507 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14508 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14509 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14510 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14511 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14512 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14513 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14514 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14515 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14516 | #endif /* OBJ_ELF */ |
f9b4148d | 14517 | |
252b5132 RH |
14518 | {NULL, no_argument, NULL, 0} |
14519 | }; | |
156c2f8b | 14520 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14521 | |
316f5878 RS |
14522 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14523 | NEW_VALUE. Warn if another value was already specified. Note: | |
14524 | we have to defer parsing the -march and -mtune arguments in order | |
14525 | to handle 'from-abi' correctly, since the ABI might be specified | |
14526 | in a later argument. */ | |
14527 | ||
14528 | static void | |
17a2f251 | 14529 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14530 | { |
14531 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14532 | as_warn (_("A different %s was already specified, is now %s"), | |
14533 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14534 | new_value); | |
14535 | ||
14536 | *string_ptr = new_value; | |
14537 | } | |
14538 | ||
252b5132 | 14539 | int |
17a2f251 | 14540 | md_parse_option (int c, char *arg) |
252b5132 RH |
14541 | { |
14542 | switch (c) | |
14543 | { | |
119d663a NC |
14544 | case OPTION_CONSTRUCT_FLOATS: |
14545 | mips_disable_float_construction = 0; | |
14546 | break; | |
bdaaa2e1 | 14547 | |
119d663a NC |
14548 | case OPTION_NO_CONSTRUCT_FLOATS: |
14549 | mips_disable_float_construction = 1; | |
14550 | break; | |
bdaaa2e1 | 14551 | |
252b5132 RH |
14552 | case OPTION_TRAP: |
14553 | mips_trap = 1; | |
14554 | break; | |
14555 | ||
14556 | case OPTION_BREAK: | |
14557 | mips_trap = 0; | |
14558 | break; | |
14559 | ||
14560 | case OPTION_EB: | |
14561 | target_big_endian = 1; | |
14562 | break; | |
14563 | ||
14564 | case OPTION_EL: | |
14565 | target_big_endian = 0; | |
14566 | break; | |
14567 | ||
14568 | case 'O': | |
4ffff32f TS |
14569 | if (arg == NULL) |
14570 | mips_optimize = 1; | |
14571 | else if (arg[0] == '0') | |
14572 | mips_optimize = 0; | |
14573 | else if (arg[0] == '1') | |
252b5132 RH |
14574 | mips_optimize = 1; |
14575 | else | |
14576 | mips_optimize = 2; | |
14577 | break; | |
14578 | ||
14579 | case 'g': | |
14580 | if (arg == NULL) | |
14581 | mips_debug = 2; | |
14582 | else | |
14583 | mips_debug = atoi (arg); | |
252b5132 RH |
14584 | break; |
14585 | ||
14586 | case OPTION_MIPS1: | |
316f5878 | 14587 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14588 | break; |
14589 | ||
14590 | case OPTION_MIPS2: | |
316f5878 | 14591 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14592 | break; |
14593 | ||
14594 | case OPTION_MIPS3: | |
316f5878 | 14595 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14596 | break; |
14597 | ||
14598 | case OPTION_MIPS4: | |
316f5878 | 14599 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14600 | break; |
14601 | ||
84ea6cf2 | 14602 | case OPTION_MIPS5: |
316f5878 | 14603 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14604 | break; |
14605 | ||
e7af610e | 14606 | case OPTION_MIPS32: |
316f5878 | 14607 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14608 | break; |
14609 | ||
af7ee8bf CD |
14610 | case OPTION_MIPS32R2: |
14611 | file_mips_isa = ISA_MIPS32R2; | |
14612 | break; | |
14613 | ||
5f74bc13 CD |
14614 | case OPTION_MIPS64R2: |
14615 | file_mips_isa = ISA_MIPS64R2; | |
14616 | break; | |
14617 | ||
84ea6cf2 | 14618 | case OPTION_MIPS64: |
316f5878 | 14619 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14620 | break; |
14621 | ||
ec68c924 | 14622 | case OPTION_MTUNE: |
316f5878 RS |
14623 | mips_set_option_string (&mips_tune_string, arg); |
14624 | break; | |
ec68c924 | 14625 | |
316f5878 RS |
14626 | case OPTION_MARCH: |
14627 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14628 | break; |
14629 | ||
14630 | case OPTION_M4650: | |
316f5878 RS |
14631 | mips_set_option_string (&mips_arch_string, "4650"); |
14632 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14633 | break; |
14634 | ||
14635 | case OPTION_NO_M4650: | |
14636 | break; | |
14637 | ||
14638 | case OPTION_M4010: | |
316f5878 RS |
14639 | mips_set_option_string (&mips_arch_string, "4010"); |
14640 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14641 | break; |
14642 | ||
14643 | case OPTION_NO_M4010: | |
14644 | break; | |
14645 | ||
14646 | case OPTION_M4100: | |
316f5878 RS |
14647 | mips_set_option_string (&mips_arch_string, "4100"); |
14648 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14649 | break; |
14650 | ||
14651 | case OPTION_NO_M4100: | |
14652 | break; | |
14653 | ||
252b5132 | 14654 | case OPTION_M3900: |
316f5878 RS |
14655 | mips_set_option_string (&mips_arch_string, "3900"); |
14656 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14657 | break; |
bdaaa2e1 | 14658 | |
252b5132 RH |
14659 | case OPTION_NO_M3900: |
14660 | break; | |
14661 | ||
deec1734 CD |
14662 | case OPTION_MDMX: |
14663 | mips_opts.ase_mdmx = 1; | |
14664 | break; | |
14665 | ||
14666 | case OPTION_NO_MDMX: | |
14667 | mips_opts.ase_mdmx = 0; | |
14668 | break; | |
14669 | ||
74cd071d CF |
14670 | case OPTION_DSP: |
14671 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14672 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14673 | break; |
14674 | ||
14675 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14676 | mips_opts.ase_dsp = 0; |
14677 | mips_opts.ase_dspr2 = 0; | |
14678 | break; | |
14679 | ||
14680 | case OPTION_DSPR2: | |
14681 | mips_opts.ase_dspr2 = 1; | |
14682 | mips_opts.ase_dsp = 1; | |
14683 | break; | |
14684 | ||
14685 | case OPTION_NO_DSPR2: | |
14686 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14687 | mips_opts.ase_dsp = 0; |
14688 | break; | |
14689 | ||
ef2e4d86 CF |
14690 | case OPTION_MT: |
14691 | mips_opts.ase_mt = 1; | |
14692 | break; | |
14693 | ||
14694 | case OPTION_NO_MT: | |
14695 | mips_opts.ase_mt = 0; | |
14696 | break; | |
14697 | ||
dec0624d MR |
14698 | case OPTION_MCU: |
14699 | mips_opts.ase_mcu = 1; | |
14700 | break; | |
14701 | ||
14702 | case OPTION_NO_MCU: | |
14703 | mips_opts.ase_mcu = 0; | |
14704 | break; | |
14705 | ||
df58fc94 RS |
14706 | case OPTION_MICROMIPS: |
14707 | if (mips_opts.mips16 == 1) | |
14708 | { | |
14709 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14710 | return 0; | |
14711 | } | |
14712 | mips_opts.micromips = 1; | |
14713 | mips_no_prev_insn (); | |
14714 | break; | |
14715 | ||
14716 | case OPTION_NO_MICROMIPS: | |
14717 | mips_opts.micromips = 0; | |
14718 | mips_no_prev_insn (); | |
14719 | break; | |
14720 | ||
252b5132 | 14721 | case OPTION_MIPS16: |
df58fc94 RS |
14722 | if (mips_opts.micromips == 1) |
14723 | { | |
14724 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14725 | return 0; | |
14726 | } | |
252b5132 | 14727 | mips_opts.mips16 = 1; |
7d10b47d | 14728 | mips_no_prev_insn (); |
252b5132 RH |
14729 | break; |
14730 | ||
14731 | case OPTION_NO_MIPS16: | |
14732 | mips_opts.mips16 = 0; | |
7d10b47d | 14733 | mips_no_prev_insn (); |
252b5132 RH |
14734 | break; |
14735 | ||
1f25f5d3 CD |
14736 | case OPTION_MIPS3D: |
14737 | mips_opts.ase_mips3d = 1; | |
14738 | break; | |
14739 | ||
14740 | case OPTION_NO_MIPS3D: | |
14741 | mips_opts.ase_mips3d = 0; | |
14742 | break; | |
14743 | ||
e16bfa71 TS |
14744 | case OPTION_SMARTMIPS: |
14745 | mips_opts.ase_smartmips = 1; | |
14746 | break; | |
14747 | ||
14748 | case OPTION_NO_SMARTMIPS: | |
14749 | mips_opts.ase_smartmips = 0; | |
14750 | break; | |
14751 | ||
6a32d874 CM |
14752 | case OPTION_FIX_24K: |
14753 | mips_fix_24k = 1; | |
14754 | break; | |
14755 | ||
14756 | case OPTION_NO_FIX_24K: | |
14757 | mips_fix_24k = 0; | |
14758 | break; | |
14759 | ||
c67a084a NC |
14760 | case OPTION_FIX_LOONGSON2F_JUMP: |
14761 | mips_fix_loongson2f_jump = TRUE; | |
14762 | break; | |
14763 | ||
14764 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14765 | mips_fix_loongson2f_jump = FALSE; | |
14766 | break; | |
14767 | ||
14768 | case OPTION_FIX_LOONGSON2F_NOP: | |
14769 | mips_fix_loongson2f_nop = TRUE; | |
14770 | break; | |
14771 | ||
14772 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14773 | mips_fix_loongson2f_nop = FALSE; | |
14774 | break; | |
14775 | ||
d766e8ec RS |
14776 | case OPTION_FIX_VR4120: |
14777 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14778 | break; |
14779 | ||
d766e8ec RS |
14780 | case OPTION_NO_FIX_VR4120: |
14781 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14782 | break; |
14783 | ||
7d8e00cf RS |
14784 | case OPTION_FIX_VR4130: |
14785 | mips_fix_vr4130 = 1; | |
14786 | break; | |
14787 | ||
14788 | case OPTION_NO_FIX_VR4130: | |
14789 | mips_fix_vr4130 = 0; | |
14790 | break; | |
14791 | ||
d954098f DD |
14792 | case OPTION_FIX_CN63XXP1: |
14793 | mips_fix_cn63xxp1 = TRUE; | |
14794 | break; | |
14795 | ||
14796 | case OPTION_NO_FIX_CN63XXP1: | |
14797 | mips_fix_cn63xxp1 = FALSE; | |
14798 | break; | |
14799 | ||
4a6a3df4 AO |
14800 | case OPTION_RELAX_BRANCH: |
14801 | mips_relax_branch = 1; | |
14802 | break; | |
14803 | ||
14804 | case OPTION_NO_RELAX_BRANCH: | |
14805 | mips_relax_branch = 0; | |
14806 | break; | |
14807 | ||
aa6975fb ILT |
14808 | case OPTION_MSHARED: |
14809 | mips_in_shared = TRUE; | |
14810 | break; | |
14811 | ||
14812 | case OPTION_MNO_SHARED: | |
14813 | mips_in_shared = FALSE; | |
14814 | break; | |
14815 | ||
aed1a261 RS |
14816 | case OPTION_MSYM32: |
14817 | mips_opts.sym32 = TRUE; | |
14818 | break; | |
14819 | ||
14820 | case OPTION_MNO_SYM32: | |
14821 | mips_opts.sym32 = FALSE; | |
14822 | break; | |
14823 | ||
0f074f60 | 14824 | #ifdef OBJ_ELF |
252b5132 RH |
14825 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14826 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14827 | intended to be compatible with Irix 5. */ | |
14828 | case OPTION_CALL_SHARED: | |
f43abd2b | 14829 | if (!IS_ELF) |
252b5132 RH |
14830 | { |
14831 | as_bad (_("-call_shared is supported only for ELF format")); | |
14832 | return 0; | |
14833 | } | |
14834 | mips_pic = SVR4_PIC; | |
143d77c5 | 14835 | mips_abicalls = TRUE; |
252b5132 RH |
14836 | break; |
14837 | ||
861fb55a DJ |
14838 | case OPTION_CALL_NONPIC: |
14839 | if (!IS_ELF) | |
14840 | { | |
14841 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14842 | return 0; | |
14843 | } | |
14844 | mips_pic = NO_PIC; | |
14845 | mips_abicalls = TRUE; | |
14846 | break; | |
14847 | ||
252b5132 | 14848 | case OPTION_NON_SHARED: |
f43abd2b | 14849 | if (!IS_ELF) |
252b5132 RH |
14850 | { |
14851 | as_bad (_("-non_shared is supported only for ELF format")); | |
14852 | return 0; | |
14853 | } | |
14854 | mips_pic = NO_PIC; | |
143d77c5 | 14855 | mips_abicalls = FALSE; |
252b5132 RH |
14856 | break; |
14857 | ||
44075ae2 TS |
14858 | /* The -xgot option tells the assembler to use 32 bit offsets |
14859 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14860 | compatibility. */ |
14861 | case OPTION_XGOT: | |
14862 | mips_big_got = 1; | |
14863 | break; | |
0f074f60 | 14864 | #endif /* OBJ_ELF */ |
252b5132 RH |
14865 | |
14866 | case 'G': | |
6caf9ef4 TS |
14867 | g_switch_value = atoi (arg); |
14868 | g_switch_seen = 1; | |
252b5132 RH |
14869 | break; |
14870 | ||
34ba82a8 TS |
14871 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14872 | and -mabi=64. */ | |
252b5132 | 14873 | case OPTION_32: |
23fce1e3 NC |
14874 | if (IS_ELF) |
14875 | mips_abi = O32_ABI; | |
14876 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14877 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14878 | break; |
14879 | ||
23fce1e3 | 14880 | #ifdef OBJ_ELF |
e013f690 | 14881 | case OPTION_N32: |
f43abd2b | 14882 | if (!IS_ELF) |
34ba82a8 TS |
14883 | { |
14884 | as_bad (_("-n32 is supported for ELF format only")); | |
14885 | return 0; | |
14886 | } | |
316f5878 | 14887 | mips_abi = N32_ABI; |
e013f690 | 14888 | break; |
252b5132 | 14889 | |
e013f690 | 14890 | case OPTION_64: |
f43abd2b | 14891 | if (!IS_ELF) |
34ba82a8 TS |
14892 | { |
14893 | as_bad (_("-64 is supported for ELF format only")); | |
14894 | return 0; | |
14895 | } | |
316f5878 | 14896 | mips_abi = N64_ABI; |
f43abd2b | 14897 | if (!support_64bit_objects()) |
e013f690 | 14898 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14899 | break; |
ae948b86 | 14900 | #endif /* OBJ_ELF */ |
252b5132 | 14901 | |
c97ef257 | 14902 | case OPTION_GP32: |
a325df1d | 14903 | file_mips_gp32 = 1; |
c97ef257 AH |
14904 | break; |
14905 | ||
14906 | case OPTION_GP64: | |
a325df1d | 14907 | file_mips_gp32 = 0; |
c97ef257 | 14908 | break; |
252b5132 | 14909 | |
ca4e0257 | 14910 | case OPTION_FP32: |
a325df1d | 14911 | file_mips_fp32 = 1; |
316f5878 RS |
14912 | break; |
14913 | ||
14914 | case OPTION_FP64: | |
14915 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14916 | break; |
14917 | ||
037b32b9 AN |
14918 | case OPTION_SINGLE_FLOAT: |
14919 | file_mips_single_float = 1; | |
14920 | break; | |
14921 | ||
14922 | case OPTION_DOUBLE_FLOAT: | |
14923 | file_mips_single_float = 0; | |
14924 | break; | |
14925 | ||
14926 | case OPTION_SOFT_FLOAT: | |
14927 | file_mips_soft_float = 1; | |
14928 | break; | |
14929 | ||
14930 | case OPTION_HARD_FLOAT: | |
14931 | file_mips_soft_float = 0; | |
14932 | break; | |
14933 | ||
ae948b86 | 14934 | #ifdef OBJ_ELF |
252b5132 | 14935 | case OPTION_MABI: |
f43abd2b | 14936 | if (!IS_ELF) |
34ba82a8 TS |
14937 | { |
14938 | as_bad (_("-mabi is supported for ELF format only")); | |
14939 | return 0; | |
14940 | } | |
e013f690 | 14941 | if (strcmp (arg, "32") == 0) |
316f5878 | 14942 | mips_abi = O32_ABI; |
e013f690 | 14943 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14944 | mips_abi = O64_ABI; |
e013f690 | 14945 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14946 | mips_abi = N32_ABI; |
e013f690 TS |
14947 | else if (strcmp (arg, "64") == 0) |
14948 | { | |
316f5878 | 14949 | mips_abi = N64_ABI; |
e013f690 TS |
14950 | if (! support_64bit_objects()) |
14951 | as_fatal (_("No compiled in support for 64 bit object file " | |
14952 | "format")); | |
14953 | } | |
14954 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14955 | mips_abi = EABI_ABI; |
e013f690 | 14956 | else |
da0e507f TS |
14957 | { |
14958 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14959 | return 0; | |
14960 | } | |
252b5132 | 14961 | break; |
e013f690 | 14962 | #endif /* OBJ_ELF */ |
252b5132 | 14963 | |
6b76fefe | 14964 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14965 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14966 | break; |
14967 | ||
9ee72ff1 | 14968 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14969 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14970 | break; |
14971 | ||
ecb4347a DJ |
14972 | #ifdef OBJ_ELF |
14973 | case OPTION_MDEBUG: | |
b34976b6 | 14974 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14975 | break; |
14976 | ||
14977 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14978 | mips_flag_mdebug = FALSE; |
ecb4347a | 14979 | break; |
dcd410fe RO |
14980 | |
14981 | case OPTION_PDR: | |
14982 | mips_flag_pdr = TRUE; | |
14983 | break; | |
14984 | ||
14985 | case OPTION_NO_PDR: | |
14986 | mips_flag_pdr = FALSE; | |
14987 | break; | |
0a44bf69 RS |
14988 | |
14989 | case OPTION_MVXWORKS_PIC: | |
14990 | mips_pic = VXWORKS_PIC; | |
14991 | break; | |
ecb4347a DJ |
14992 | #endif /* OBJ_ELF */ |
14993 | ||
252b5132 RH |
14994 | default: |
14995 | return 0; | |
14996 | } | |
14997 | ||
c67a084a NC |
14998 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14999 | ||
252b5132 RH |
15000 | return 1; |
15001 | } | |
316f5878 RS |
15002 | \f |
15003 | /* Set up globals to generate code for the ISA or processor | |
15004 | described by INFO. */ | |
252b5132 | 15005 | |
252b5132 | 15006 | static void |
17a2f251 | 15007 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15008 | { |
316f5878 | 15009 | if (info != 0) |
252b5132 | 15010 | { |
fef14a42 TS |
15011 | file_mips_arch = info->cpu; |
15012 | mips_opts.arch = info->cpu; | |
316f5878 | 15013 | mips_opts.isa = info->isa; |
252b5132 | 15014 | } |
252b5132 RH |
15015 | } |
15016 | ||
252b5132 | 15017 | |
316f5878 | 15018 | /* Likewise for tuning. */ |
252b5132 | 15019 | |
316f5878 | 15020 | static void |
17a2f251 | 15021 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15022 | { |
15023 | if (info != 0) | |
fef14a42 | 15024 | mips_tune = info->cpu; |
316f5878 | 15025 | } |
80cc45a5 | 15026 | |
34ba82a8 | 15027 | |
252b5132 | 15028 | void |
17a2f251 | 15029 | mips_after_parse_args (void) |
e9670677 | 15030 | { |
fef14a42 TS |
15031 | const struct mips_cpu_info *arch_info = 0; |
15032 | const struct mips_cpu_info *tune_info = 0; | |
15033 | ||
e9670677 | 15034 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15035 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15036 | { |
6caf9ef4 | 15037 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15038 | as_bad (_("-G not supported in this configuration.")); |
15039 | g_switch_value = 0; | |
15040 | } | |
15041 | ||
cac012d6 AO |
15042 | if (mips_abi == NO_ABI) |
15043 | mips_abi = MIPS_DEFAULT_ABI; | |
15044 | ||
22923709 RS |
15045 | /* The following code determines the architecture and register size. |
15046 | Similar code was added to GCC 3.3 (see override_options() in | |
15047 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15048 | as much as possible. */ | |
e9670677 | 15049 | |
316f5878 | 15050 | if (mips_arch_string != 0) |
fef14a42 | 15051 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15052 | |
316f5878 | 15053 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15054 | { |
316f5878 | 15055 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15056 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15057 | the -march selection (if any). */ |
fef14a42 | 15058 | if (arch_info != 0) |
e9670677 | 15059 | { |
316f5878 RS |
15060 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15061 | There's no harm in specifying both as long as the ISA levels | |
15062 | are the same. */ | |
fef14a42 | 15063 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15064 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15065 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15066 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15067 | } |
316f5878 | 15068 | else |
fef14a42 | 15069 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15070 | } |
15071 | ||
fef14a42 | 15072 | if (arch_info == 0) |
95bfe26e MF |
15073 | { |
15074 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15075 | gas_assert (arch_info); | |
15076 | } | |
e9670677 | 15077 | |
fef14a42 | 15078 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15079 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15080 | arch_info->name); |
15081 | ||
15082 | mips_set_architecture (arch_info); | |
15083 | ||
15084 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15085 | if (mips_tune_string != 0) | |
15086 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15087 | |
fef14a42 TS |
15088 | if (tune_info == 0) |
15089 | mips_set_tune (arch_info); | |
15090 | else | |
15091 | mips_set_tune (tune_info); | |
e9670677 | 15092 | |
316f5878 | 15093 | if (file_mips_gp32 >= 0) |
e9670677 | 15094 | { |
316f5878 RS |
15095 | /* The user specified the size of the integer registers. Make sure |
15096 | it agrees with the ABI and ISA. */ | |
15097 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15098 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15099 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15100 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15101 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15102 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15103 | } |
15104 | else | |
15105 | { | |
316f5878 RS |
15106 | /* Infer the integer register size from the ABI and processor. |
15107 | Restrict ourselves to 32-bit registers if that's all the | |
15108 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15109 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15110 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15111 | } |
15112 | ||
ad3fea08 TS |
15113 | switch (file_mips_fp32) |
15114 | { | |
15115 | default: | |
15116 | case -1: | |
15117 | /* No user specified float register size. | |
15118 | ??? GAS treats single-float processors as though they had 64-bit | |
15119 | float registers (although it complains when double-precision | |
15120 | instructions are used). As things stand, saying they have 32-bit | |
15121 | registers would lead to spurious "register must be even" messages. | |
15122 | So here we assume float registers are never smaller than the | |
15123 | integer ones. */ | |
15124 | if (file_mips_gp32 == 0) | |
15125 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15126 | file_mips_fp32 = 0; | |
15127 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15128 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15129 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15130 | file_mips_fp32 = 0; | |
15131 | else | |
15132 | /* 32-bit float registers. */ | |
15133 | file_mips_fp32 = 1; | |
15134 | break; | |
15135 | ||
15136 | /* The user specified the size of the float registers. Check if it | |
15137 | agrees with the ABI and ISA. */ | |
15138 | case 0: | |
15139 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15140 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15141 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15142 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15143 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15144 | break; | |
15145 | case 1: | |
15146 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15147 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15148 | break; | |
15149 | } | |
e9670677 | 15150 | |
316f5878 | 15151 | /* End of GCC-shared inference code. */ |
e9670677 | 15152 | |
17a2f251 TS |
15153 | /* This flag is set when we have a 64-bit capable CPU but use only |
15154 | 32-bit wide registers. Note that EABI does not use it. */ | |
15155 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15156 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15157 | || mips_abi == O32_ABI)) | |
316f5878 | 15158 | mips_32bitmode = 1; |
e9670677 MR |
15159 | |
15160 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15161 | as_bad (_("trap exception not supported at ISA 1")); | |
15162 | ||
e9670677 MR |
15163 | /* If the selected architecture includes support for ASEs, enable |
15164 | generation of code for them. */ | |
a4672219 | 15165 | if (mips_opts.mips16 == -1) |
fef14a42 | 15166 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15167 | if (mips_opts.micromips == -1) |
15168 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15169 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15170 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15171 | && file_mips_fp32 == 0) ? 1 : 0; |
15172 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15173 | as_bad (_("-mfp32 used with -mips3d")); | |
15174 | ||
ffdefa66 | 15175 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15176 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15177 | && file_mips_fp32 == 0) ? 1 : 0; |
15178 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15179 | as_bad (_("-mfp32 used with -mdmx")); | |
15180 | ||
15181 | if (mips_opts.ase_smartmips == -1) | |
15182 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15183 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15184 | as_warn (_("%s ISA does not support SmartMIPS"), |
15185 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15186 | |
74cd071d | 15187 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15188 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15189 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15190 | as_warn (_("%s ISA does not support DSP ASE"), |
15191 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15192 | |
8b082fb1 TS |
15193 | if (mips_opts.ase_dspr2 == -1) |
15194 | { | |
15195 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15196 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15197 | } | |
15198 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15199 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15200 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15201 | |
ef2e4d86 | 15202 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15203 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15204 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15205 | as_warn (_("%s ISA does not support MT ASE"), |
15206 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15207 | |
dec0624d MR |
15208 | if (mips_opts.ase_mcu == -1) |
15209 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15210 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15211 | as_warn (_("%s ISA does not support MCU ASE"), | |
15212 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15213 | ||
e9670677 | 15214 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15215 | file_ase_mips3d = mips_opts.ase_mips3d; |
15216 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15217 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15218 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15219 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15220 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15221 | mips_opts.gp32 = file_mips_gp32; |
15222 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15223 | mips_opts.soft_float = file_mips_soft_float; |
15224 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15225 | |
ecb4347a DJ |
15226 | if (mips_flag_mdebug < 0) |
15227 | { | |
15228 | #ifdef OBJ_MAYBE_ECOFF | |
15229 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15230 | mips_flag_mdebug = 1; | |
15231 | else | |
15232 | #endif /* OBJ_MAYBE_ECOFF */ | |
15233 | mips_flag_mdebug = 0; | |
15234 | } | |
e9670677 MR |
15235 | } |
15236 | \f | |
15237 | void | |
17a2f251 | 15238 | mips_init_after_args (void) |
252b5132 RH |
15239 | { |
15240 | /* initialize opcodes */ | |
15241 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15242 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15243 | } |
15244 | ||
15245 | long | |
17a2f251 | 15246 | md_pcrel_from (fixS *fixP) |
252b5132 | 15247 | { |
a7ebbfdf TS |
15248 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15249 | switch (fixP->fx_r_type) | |
15250 | { | |
df58fc94 RS |
15251 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15252 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15253 | /* Return the address of the delay slot. */ | |
15254 | return addr + 2; | |
15255 | ||
15256 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15257 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15258 | case BFD_RELOC_16_PCREL_S2: |
15259 | case BFD_RELOC_MIPS_JMP: | |
15260 | /* Return the address of the delay slot. */ | |
15261 | return addr + 4; | |
df58fc94 | 15262 | |
a7ebbfdf | 15263 | default: |
58ea3d6a | 15264 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15265 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15266 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15267 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15268 | return addr; |
15269 | } | |
252b5132 RH |
15270 | } |
15271 | ||
252b5132 RH |
15272 | /* This is called before the symbol table is processed. In order to |
15273 | work with gcc when using mips-tfile, we must keep all local labels. | |
15274 | However, in other cases, we want to discard them. If we were | |
15275 | called with -g, but we didn't see any debugging information, it may | |
15276 | mean that gcc is smuggling debugging information through to | |
15277 | mips-tfile, in which case we must generate all local labels. */ | |
15278 | ||
15279 | void | |
17a2f251 | 15280 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15281 | { |
15282 | #ifndef NO_ECOFF_DEBUGGING | |
15283 | if (ECOFF_DEBUGGING | |
15284 | && mips_debug != 0 | |
15285 | && ! ecoff_debugging_seen) | |
15286 | flag_keep_locals = 1; | |
15287 | #endif | |
15288 | } | |
15289 | ||
3b91255e | 15290 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15291 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15292 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15293 | relocation operators. | |
15294 | ||
15295 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15296 | expression if: | |
15297 | ||
15298 | (a) it refers to the same symbol; and | |
15299 | (b) the offset applied in the %lo() expression is no lower than | |
15300 | the offset applied in the %got() or %hi(). | |
15301 | ||
15302 | (b) allows us to cope with code like: | |
15303 | ||
15304 | lui $4,%hi(foo) | |
15305 | lh $4,%lo(foo+2)($4) | |
15306 | ||
15307 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15308 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15309 | the high 16 bits. | |
15310 | ||
15311 | When several %lo()s match a particular %got() or %hi(), we use the | |
15312 | following rules to distinguish them: | |
15313 | ||
15314 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15315 | higher offsets. | |
15316 | ||
15317 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15318 | that already have a matching %got() or %hi(). | |
15319 | ||
15320 | (3) later %lo()s are better than earlier %lo()s. | |
15321 | ||
15322 | These rules are applied in order. | |
15323 | ||
15324 | (1) means, among other things, that %lo()s with identical offsets are | |
15325 | chosen if they exist. | |
15326 | ||
15327 | (2) means that we won't associate several high-part relocations with | |
15328 | the same low-part relocation unless there's no alternative. Having | |
15329 | several high parts for the same low part is a GNU extension; this rule | |
15330 | allows careful users to avoid it. | |
15331 | ||
15332 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15333 | with the last high-part relocation being at the front of the list. | |
15334 | It therefore makes sense to choose the last matching low-part | |
15335 | relocation, all other things being equal. It's also easier | |
15336 | to code that way. */ | |
252b5132 RH |
15337 | |
15338 | void | |
17a2f251 | 15339 | mips_frob_file (void) |
252b5132 RH |
15340 | { |
15341 | struct mips_hi_fixup *l; | |
35903be0 | 15342 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15343 | |
15344 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15345 | { | |
15346 | segment_info_type *seginfo; | |
3b91255e RS |
15347 | bfd_boolean matched_lo_p; |
15348 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15349 | |
9c2799c2 | 15350 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15351 | |
5919d012 RS |
15352 | /* If a GOT16 relocation turns out to be against a global symbol, |
15353 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15354 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15355 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15356 | continue; | |
15357 | ||
15358 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15359 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15360 | continue; |
15361 | ||
252b5132 | 15362 | seginfo = seg_info (l->seg); |
252b5132 | 15363 | |
3b91255e RS |
15364 | /* Set HI_POS to the position of this relocation in the chain. |
15365 | Set LO_POS to the position of the chosen low-part relocation. | |
15366 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15367 | relocation that matches an immediately-preceding high-part | |
15368 | relocation. */ | |
15369 | hi_pos = NULL; | |
15370 | lo_pos = NULL; | |
15371 | matched_lo_p = FALSE; | |
738e5348 | 15372 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15373 | |
3b91255e RS |
15374 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15375 | { | |
15376 | if (*pos == l->fixp) | |
15377 | hi_pos = pos; | |
15378 | ||
35903be0 | 15379 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15380 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15381 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15382 | && (lo_pos == NULL | |
15383 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15384 | || (!matched_lo_p | |
15385 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15386 | lo_pos = pos; | |
15387 | ||
15388 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15389 | && fixup_has_matching_lo_p (*pos)); | |
15390 | } | |
15391 | ||
15392 | /* If we found a match, remove the high-part relocation from its | |
15393 | current position and insert it before the low-part relocation. | |
15394 | Make the offsets match so that fixup_has_matching_lo_p() | |
15395 | will return true. | |
15396 | ||
15397 | We don't warn about unmatched high-part relocations since some | |
15398 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15399 | instructions. */ | |
15400 | if (lo_pos != NULL) | |
15401 | { | |
15402 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15403 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15404 | { |
3b91255e RS |
15405 | *hi_pos = l->fixp->fx_next; |
15406 | l->fixp->fx_next = *lo_pos; | |
15407 | *lo_pos = l->fixp; | |
252b5132 | 15408 | } |
252b5132 RH |
15409 | } |
15410 | } | |
15411 | } | |
15412 | ||
3e722fb5 | 15413 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15414 | We have to prevent gas from dropping them. */ |
252b5132 | 15415 | |
252b5132 | 15416 | int |
17a2f251 | 15417 | mips_force_relocation (fixS *fixp) |
252b5132 | 15418 | { |
ae6063d4 | 15419 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15420 | return 1; |
15421 | ||
df58fc94 RS |
15422 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15423 | so that the linker relaxation can update targets. */ | |
15424 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15425 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15426 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15427 | return 1; | |
15428 | ||
f6688943 TS |
15429 | if (HAVE_NEWABI |
15430 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15431 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15432 | || hi16_reloc_p (fixp->fx_r_type) |
15433 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15434 | return 1; |
15435 | ||
3e722fb5 | 15436 | return 0; |
252b5132 RH |
15437 | } |
15438 | ||
15439 | /* Apply a fixup to the object file. */ | |
15440 | ||
94f592af | 15441 | void |
55cf6793 | 15442 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15443 | { |
4d68580a | 15444 | char *buf; |
98aa84af | 15445 | long insn; |
a7ebbfdf | 15446 | reloc_howto_type *howto; |
252b5132 | 15447 | |
a7ebbfdf TS |
15448 | /* We ignore generic BFD relocations we don't know about. */ |
15449 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15450 | if (! howto) | |
15451 | return; | |
65551fa4 | 15452 | |
df58fc94 RS |
15453 | gas_assert (fixP->fx_size == 2 |
15454 | || fixP->fx_size == 4 | |
90ecf173 MR |
15455 | || fixP->fx_r_type == BFD_RELOC_16 |
15456 | || fixP->fx_r_type == BFD_RELOC_64 | |
15457 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15458 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15459 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15460 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15461 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15462 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15463 | |
4d68580a | 15464 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15465 | |
df58fc94 RS |
15466 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15467 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15468 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15469 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15470 | |
15471 | /* Don't treat parts of a composite relocation as done. There are two | |
15472 | reasons for this: | |
15473 | ||
15474 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15475 | should nevertheless be emitted if the first part is. | |
15476 | ||
15477 | (2) In normal usage, composite relocations are never assembly-time | |
15478 | constants. The easiest way of dealing with the pathological | |
15479 | exceptions is to generate a relocation against STN_UNDEF and | |
15480 | leave everything up to the linker. */ | |
3994f87e | 15481 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15482 | fixP->fx_done = 1; |
15483 | ||
15484 | switch (fixP->fx_r_type) | |
15485 | { | |
3f98094e DJ |
15486 | case BFD_RELOC_MIPS_TLS_GD: |
15487 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15488 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15489 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15490 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15491 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15492 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15493 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15494 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15495 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15496 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15497 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15498 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15499 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15500 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15501 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15502 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15503 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15504 | case BFD_RELOC_MIPS16_TLS_GD: |
15505 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15506 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15507 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15508 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15509 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15510 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
3f98094e DJ |
15511 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15512 | /* fall through */ | |
15513 | ||
252b5132 | 15514 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15515 | case BFD_RELOC_MIPS_SHIFT5: |
15516 | case BFD_RELOC_MIPS_SHIFT6: | |
15517 | case BFD_RELOC_MIPS_GOT_DISP: | |
15518 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15519 | case BFD_RELOC_MIPS_GOT_OFST: | |
15520 | case BFD_RELOC_MIPS_SUB: | |
15521 | case BFD_RELOC_MIPS_INSERT_A: | |
15522 | case BFD_RELOC_MIPS_INSERT_B: | |
15523 | case BFD_RELOC_MIPS_DELETE: | |
15524 | case BFD_RELOC_MIPS_HIGHEST: | |
15525 | case BFD_RELOC_MIPS_HIGHER: | |
15526 | case BFD_RELOC_MIPS_SCN_DISP: | |
15527 | case BFD_RELOC_MIPS_REL16: | |
15528 | case BFD_RELOC_MIPS_RELGOT: | |
15529 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15530 | case BFD_RELOC_HI16: |
15531 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15532 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15533 | case BFD_RELOC_MIPS_LITERAL: |
15534 | case BFD_RELOC_MIPS_CALL16: | |
15535 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15536 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15537 | case BFD_RELOC_MIPS_GOT_HI16: |
15538 | case BFD_RELOC_MIPS_GOT_LO16: | |
15539 | case BFD_RELOC_MIPS_CALL_HI16: | |
15540 | case BFD_RELOC_MIPS_CALL_LO16: | |
15541 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15542 | case BFD_RELOC_MIPS16_GOT16: |
15543 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15544 | case BFD_RELOC_MIPS16_HI16: |
15545 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15546 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15547 | case BFD_RELOC_MICROMIPS_JMP: |
15548 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15549 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15550 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15551 | case BFD_RELOC_MICROMIPS_SUB: | |
15552 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15553 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15554 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15555 | case BFD_RELOC_MICROMIPS_JALR: | |
15556 | case BFD_RELOC_MICROMIPS_HI16: | |
15557 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15558 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15559 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15560 | case BFD_RELOC_MICROMIPS_CALL16: | |
15561 | case BFD_RELOC_MICROMIPS_GOT16: | |
15562 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15563 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15564 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15565 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15566 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15567 | break; |
15568 | ||
252b5132 RH |
15569 | case BFD_RELOC_64: |
15570 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15571 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15572 | if (fixP->fx_done) |
252b5132 RH |
15573 | { |
15574 | if (8 <= sizeof (valueT)) | |
4d68580a | 15575 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15576 | else |
15577 | { | |
a7ebbfdf | 15578 | valueT hiv; |
252b5132 | 15579 | |
a7ebbfdf | 15580 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15581 | hiv = 0xffffffff; |
15582 | else | |
15583 | hiv = 0; | |
4d68580a RS |
15584 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15585 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15586 | } |
15587 | } | |
15588 | break; | |
15589 | ||
056350c6 | 15590 | case BFD_RELOC_RVA: |
252b5132 | 15591 | case BFD_RELOC_32: |
252b5132 RH |
15592 | case BFD_RELOC_16: |
15593 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15594 | value now. This can happen if we have a .word which is not |
15595 | resolved when it appears but is later defined. */ | |
252b5132 | 15596 | if (fixP->fx_done) |
4d68580a | 15597 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15598 | break; |
15599 | ||
15600 | case BFD_RELOC_LO16: | |
d6f16593 | 15601 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15602 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15603 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15604 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15605 | /* When handling an embedded PIC switch statement, we can wind |
15606 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15607 | if (fixP->fx_done) | |
15608 | { | |
a7ebbfdf | 15609 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15610 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15611 | _("relocation overflow")); | |
df58fc94 RS |
15612 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15613 | Relocations always refer to the second halfword, regardless | |
15614 | of endianness. */ | |
15615 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15616 | buf += 2; |
4d68580a | 15617 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
15618 | } |
15619 | break; | |
15620 | ||
15621 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15622 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15623 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15624 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15625 | |
54f4ddb3 TS |
15626 | /* We need to save the bits in the instruction since fixup_segment() |
15627 | might be deleting the relocation entry (i.e., a branch within | |
15628 | the current segment). */ | |
a7ebbfdf | 15629 | if (! fixP->fx_done) |
bb2d6cd7 | 15630 | break; |
252b5132 | 15631 | |
54f4ddb3 | 15632 | /* Update old instruction data. */ |
4d68580a | 15633 | insn = read_insn (buf); |
252b5132 | 15634 | |
a7ebbfdf TS |
15635 | if (*valP + 0x20000 <= 0x3ffff) |
15636 | { | |
15637 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15638 | write_insn (buf, insn); |
a7ebbfdf TS |
15639 | } |
15640 | else if (mips_pic == NO_PIC | |
15641 | && fixP->fx_done | |
15642 | && fixP->fx_frag->fr_address >= text_section->vma | |
15643 | && (fixP->fx_frag->fr_address | |
587aac4e | 15644 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15645 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15646 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15647 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15648 | { |
15649 | /* The branch offset is too large. If this is an | |
15650 | unconditional branch, and we are not generating PIC code, | |
15651 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15652 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15653 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15654 | else |
a7ebbfdf TS |
15655 | insn = 0x08000000; /* j */ |
15656 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15657 | fixP->fx_done = 0; | |
15658 | fixP->fx_addsy = section_symbol (text_section); | |
15659 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15660 | write_insn (buf, insn); |
a7ebbfdf TS |
15661 | } |
15662 | else | |
15663 | { | |
15664 | /* If we got here, we have branch-relaxation disabled, | |
15665 | and there's nothing we can do to fix this instruction | |
15666 | without turning it into a longer sequence. */ | |
15667 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15668 | _("Branch out of range")); | |
252b5132 | 15669 | } |
252b5132 RH |
15670 | break; |
15671 | ||
df58fc94 RS |
15672 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15673 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15674 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15675 | /* We adjust the offset back to even. */ | |
15676 | if ((*valP & 0x1) != 0) | |
15677 | --(*valP); | |
15678 | ||
15679 | if (! fixP->fx_done) | |
15680 | break; | |
15681 | ||
15682 | /* Should never visit here, because we keep the relocation. */ | |
15683 | abort (); | |
15684 | break; | |
15685 | ||
252b5132 RH |
15686 | case BFD_RELOC_VTABLE_INHERIT: |
15687 | fixP->fx_done = 0; | |
15688 | if (fixP->fx_addsy | |
15689 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15690 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15691 | S_SET_WEAK (fixP->fx_addsy); | |
15692 | break; | |
15693 | ||
15694 | case BFD_RELOC_VTABLE_ENTRY: | |
15695 | fixP->fx_done = 0; | |
15696 | break; | |
15697 | ||
15698 | default: | |
15699 | internalError (); | |
15700 | } | |
a7ebbfdf TS |
15701 | |
15702 | /* Remember value for tc_gen_reloc. */ | |
15703 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15704 | } |
15705 | ||
252b5132 | 15706 | static symbolS * |
17a2f251 | 15707 | get_symbol (void) |
252b5132 RH |
15708 | { |
15709 | int c; | |
15710 | char *name; | |
15711 | symbolS *p; | |
15712 | ||
15713 | name = input_line_pointer; | |
15714 | c = get_symbol_end (); | |
15715 | p = (symbolS *) symbol_find_or_make (name); | |
15716 | *input_line_pointer = c; | |
15717 | return p; | |
15718 | } | |
15719 | ||
742a56fe RS |
15720 | /* Align the current frag to a given power of two. If a particular |
15721 | fill byte should be used, FILL points to an integer that contains | |
15722 | that byte, otherwise FILL is null. | |
15723 | ||
462427c4 RS |
15724 | This function used to have the comment: |
15725 | ||
15726 | The MIPS assembler also automatically adjusts any preceding label. | |
15727 | ||
15728 | The implementation therefore applied the adjustment to a maximum of | |
15729 | one label. However, other label adjustments are applied to batches | |
15730 | of labels, and adjusting just one caused problems when new labels | |
15731 | were added for the sake of debugging or unwind information. | |
15732 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15733 | |
15734 | static void | |
462427c4 | 15735 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15736 | { |
7d10b47d | 15737 | mips_emit_delays (); |
df58fc94 | 15738 | mips_record_compressed_mode (); |
742a56fe RS |
15739 | if (fill == NULL && subseg_text_p (now_seg)) |
15740 | frag_align_code (to, 0); | |
15741 | else | |
15742 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15743 | record_alignment (now_seg, to); |
462427c4 | 15744 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15745 | } |
15746 | ||
15747 | /* Align to a given power of two. .align 0 turns off the automatic | |
15748 | alignment used by the data creating pseudo-ops. */ | |
15749 | ||
15750 | static void | |
17a2f251 | 15751 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15752 | { |
742a56fe | 15753 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15754 | long max_alignment = 28; |
252b5132 | 15755 | |
54f4ddb3 | 15756 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15757 | to the aligned address. |
54f4ddb3 | 15758 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15759 | a .align pseudo instruction. |
54f4ddb3 | 15760 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15761 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15762 | We don't. */ |
252b5132 RH |
15763 | |
15764 | temp = get_absolute_expression (); | |
15765 | if (temp > max_alignment) | |
15766 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15767 | else if (temp < 0) | |
15768 | { | |
15769 | as_warn (_("Alignment negative: 0 assumed.")); | |
15770 | temp = 0; | |
15771 | } | |
15772 | if (*input_line_pointer == ',') | |
15773 | { | |
f9419b05 | 15774 | ++input_line_pointer; |
742a56fe RS |
15775 | fill_value = get_absolute_expression (); |
15776 | fill_ptr = &fill_value; | |
252b5132 RH |
15777 | } |
15778 | else | |
742a56fe | 15779 | fill_ptr = 0; |
252b5132 RH |
15780 | if (temp) |
15781 | { | |
a8dbcb85 TS |
15782 | segment_info_type *si = seg_info (now_seg); |
15783 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15784 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15785 | auto_align = 1; |
462427c4 | 15786 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15787 | } |
15788 | else | |
15789 | { | |
15790 | auto_align = 0; | |
15791 | } | |
15792 | ||
15793 | demand_empty_rest_of_line (); | |
15794 | } | |
15795 | ||
252b5132 | 15796 | static void |
17a2f251 | 15797 | s_change_sec (int sec) |
252b5132 RH |
15798 | { |
15799 | segT seg; | |
15800 | ||
252b5132 RH |
15801 | #ifdef OBJ_ELF |
15802 | /* The ELF backend needs to know that we are changing sections, so | |
15803 | that .previous works correctly. We could do something like check | |
b6ff326e | 15804 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15805 | as it would not be appropriate to use it in the section changing |
15806 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15807 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15808 | if (IS_ELF) |
15809 | obj_elf_section_change_hook (); | |
252b5132 RH |
15810 | #endif |
15811 | ||
7d10b47d | 15812 | mips_emit_delays (); |
6a32d874 | 15813 | |
252b5132 RH |
15814 | switch (sec) |
15815 | { | |
15816 | case 't': | |
15817 | s_text (0); | |
15818 | break; | |
15819 | case 'd': | |
15820 | s_data (0); | |
15821 | break; | |
15822 | case 'b': | |
15823 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15824 | demand_empty_rest_of_line (); | |
15825 | break; | |
15826 | ||
15827 | case 'r': | |
4d0d148d TS |
15828 | seg = subseg_new (RDATA_SECTION_NAME, |
15829 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15830 | if (IS_ELF) |
252b5132 | 15831 | { |
4d0d148d TS |
15832 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15833 | | SEC_READONLY | SEC_RELOC | |
15834 | | SEC_DATA)); | |
c41e87e3 | 15835 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15836 | record_alignment (seg, 4); |
252b5132 | 15837 | } |
4d0d148d | 15838 | demand_empty_rest_of_line (); |
252b5132 RH |
15839 | break; |
15840 | ||
15841 | case 's': | |
4d0d148d | 15842 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15843 | if (IS_ELF) |
252b5132 | 15844 | { |
4d0d148d TS |
15845 | bfd_set_section_flags (stdoutput, seg, |
15846 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15847 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15848 | record_alignment (seg, 4); |
252b5132 | 15849 | } |
4d0d148d TS |
15850 | demand_empty_rest_of_line (); |
15851 | break; | |
998b3c36 MR |
15852 | |
15853 | case 'B': | |
15854 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15855 | if (IS_ELF) | |
15856 | { | |
15857 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15858 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15859 | record_alignment (seg, 4); | |
15860 | } | |
15861 | demand_empty_rest_of_line (); | |
15862 | break; | |
252b5132 RH |
15863 | } |
15864 | ||
15865 | auto_align = 1; | |
15866 | } | |
b34976b6 | 15867 | |
cca86cc8 | 15868 | void |
17a2f251 | 15869 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15870 | { |
7ed4a06a | 15871 | #ifdef OBJ_ELF |
cca86cc8 SC |
15872 | char *section_name; |
15873 | char c; | |
684022ea | 15874 | char next_c = 0; |
cca86cc8 SC |
15875 | int section_type; |
15876 | int section_flag; | |
15877 | int section_entry_size; | |
15878 | int section_alignment; | |
b34976b6 | 15879 | |
f43abd2b | 15880 | if (!IS_ELF) |
7ed4a06a TS |
15881 | return; |
15882 | ||
cca86cc8 SC |
15883 | section_name = input_line_pointer; |
15884 | c = get_symbol_end (); | |
a816d1ed AO |
15885 | if (c) |
15886 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15887 | |
4cf0dd0d TS |
15888 | /* Do we have .section Name<,"flags">? */ |
15889 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15890 | { |
4cf0dd0d TS |
15891 | /* just after name is now '\0'. */ |
15892 | *input_line_pointer = c; | |
cca86cc8 SC |
15893 | input_line_pointer = section_name; |
15894 | obj_elf_section (ignore); | |
15895 | return; | |
15896 | } | |
15897 | input_line_pointer++; | |
15898 | ||
15899 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15900 | if (c == ',') | |
15901 | section_type = get_absolute_expression (); | |
15902 | else | |
15903 | section_type = 0; | |
15904 | if (*input_line_pointer++ == ',') | |
15905 | section_flag = get_absolute_expression (); | |
15906 | else | |
15907 | section_flag = 0; | |
15908 | if (*input_line_pointer++ == ',') | |
15909 | section_entry_size = get_absolute_expression (); | |
15910 | else | |
15911 | section_entry_size = 0; | |
15912 | if (*input_line_pointer++ == ',') | |
15913 | section_alignment = get_absolute_expression (); | |
15914 | else | |
15915 | section_alignment = 0; | |
87975d2a AM |
15916 | /* FIXME: really ignore? */ |
15917 | (void) section_alignment; | |
cca86cc8 | 15918 | |
a816d1ed AO |
15919 | section_name = xstrdup (section_name); |
15920 | ||
8ab8a5c8 RS |
15921 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15922 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15923 | traditionally had to fall back on the more common @progbits instead. | |
15924 | ||
15925 | There's nothing really harmful in this, since bfd will correct | |
15926 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15927 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15928 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15929 | ||
15930 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15931 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15932 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15933 | generic type-checking code. */ | |
15934 | if (section_type == SHT_MIPS_DWARF) | |
15935 | section_type = SHT_PROGBITS; | |
15936 | ||
cca86cc8 SC |
15937 | obj_elf_change_section (section_name, section_type, section_flag, |
15938 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15939 | |
15940 | if (now_seg->name != section_name) | |
15941 | free (section_name); | |
7ed4a06a | 15942 | #endif /* OBJ_ELF */ |
cca86cc8 | 15943 | } |
252b5132 RH |
15944 | |
15945 | void | |
17a2f251 | 15946 | mips_enable_auto_align (void) |
252b5132 RH |
15947 | { |
15948 | auto_align = 1; | |
15949 | } | |
15950 | ||
15951 | static void | |
17a2f251 | 15952 | s_cons (int log_size) |
252b5132 | 15953 | { |
a8dbcb85 TS |
15954 | segment_info_type *si = seg_info (now_seg); |
15955 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15956 | |
7d10b47d | 15957 | mips_emit_delays (); |
252b5132 | 15958 | if (log_size > 0 && auto_align) |
462427c4 | 15959 | mips_align (log_size, 0, l); |
252b5132 | 15960 | cons (1 << log_size); |
a1facbec | 15961 | mips_clear_insn_labels (); |
252b5132 RH |
15962 | } |
15963 | ||
15964 | static void | |
17a2f251 | 15965 | s_float_cons (int type) |
252b5132 | 15966 | { |
a8dbcb85 TS |
15967 | segment_info_type *si = seg_info (now_seg); |
15968 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15969 | |
7d10b47d | 15970 | mips_emit_delays (); |
252b5132 RH |
15971 | |
15972 | if (auto_align) | |
49309057 ILT |
15973 | { |
15974 | if (type == 'd') | |
462427c4 | 15975 | mips_align (3, 0, l); |
49309057 | 15976 | else |
462427c4 | 15977 | mips_align (2, 0, l); |
49309057 | 15978 | } |
252b5132 | 15979 | |
252b5132 | 15980 | float_cons (type); |
a1facbec | 15981 | mips_clear_insn_labels (); |
252b5132 RH |
15982 | } |
15983 | ||
15984 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15985 | permitted to say | |
15986 | .globl foo .text | |
15987 | where foo is an undefined symbol, to mean that foo should be | |
15988 | considered to be the address of a function. */ | |
15989 | ||
15990 | static void | |
17a2f251 | 15991 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15992 | { |
15993 | char *name; | |
15994 | int c; | |
15995 | symbolS *symbolP; | |
15996 | flagword flag; | |
15997 | ||
8a06b769 | 15998 | do |
252b5132 | 15999 | { |
8a06b769 | 16000 | name = input_line_pointer; |
252b5132 | 16001 | c = get_symbol_end (); |
8a06b769 TS |
16002 | symbolP = symbol_find_or_make (name); |
16003 | S_SET_EXTERNAL (symbolP); | |
16004 | ||
252b5132 | 16005 | *input_line_pointer = c; |
8a06b769 | 16006 | SKIP_WHITESPACE (); |
252b5132 | 16007 | |
8a06b769 TS |
16008 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16009 | being a function is apparently labelled as being an object. */ | |
16010 | flag = BSF_OBJECT; | |
252b5132 | 16011 | |
8a06b769 TS |
16012 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16013 | && (*input_line_pointer != ',')) | |
16014 | { | |
16015 | char *secname; | |
16016 | asection *sec; | |
16017 | ||
16018 | secname = input_line_pointer; | |
16019 | c = get_symbol_end (); | |
16020 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16021 | if (sec == NULL) | |
16022 | as_bad (_("%s: no such section"), secname); | |
16023 | *input_line_pointer = c; | |
16024 | ||
16025 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16026 | flag = BSF_FUNCTION; | |
16027 | } | |
16028 | ||
16029 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16030 | ||
16031 | c = *input_line_pointer; | |
16032 | if (c == ',') | |
16033 | { | |
16034 | input_line_pointer++; | |
16035 | SKIP_WHITESPACE (); | |
16036 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16037 | c = '\n'; | |
16038 | } | |
16039 | } | |
16040 | while (c == ','); | |
252b5132 | 16041 | |
252b5132 RH |
16042 | demand_empty_rest_of_line (); |
16043 | } | |
16044 | ||
16045 | static void | |
17a2f251 | 16046 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16047 | { |
16048 | char *opt; | |
16049 | char c; | |
16050 | ||
16051 | opt = input_line_pointer; | |
16052 | c = get_symbol_end (); | |
16053 | ||
16054 | if (*opt == 'O') | |
16055 | { | |
16056 | /* FIXME: What does this mean? */ | |
16057 | } | |
16058 | else if (strncmp (opt, "pic", 3) == 0) | |
16059 | { | |
16060 | int i; | |
16061 | ||
16062 | i = atoi (opt + 3); | |
16063 | if (i == 0) | |
16064 | mips_pic = NO_PIC; | |
16065 | else if (i == 2) | |
143d77c5 | 16066 | { |
8b828383 | 16067 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16068 | mips_abicalls = TRUE; |
16069 | } | |
252b5132 RH |
16070 | else |
16071 | as_bad (_(".option pic%d not supported"), i); | |
16072 | ||
4d0d148d | 16073 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16074 | { |
16075 | if (g_switch_seen && g_switch_value != 0) | |
16076 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16077 | g_switch_value = 0; | |
16078 | bfd_set_gp_size (stdoutput, 0); | |
16079 | } | |
16080 | } | |
16081 | else | |
16082 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16083 | ||
16084 | *input_line_pointer = c; | |
16085 | demand_empty_rest_of_line (); | |
16086 | } | |
16087 | ||
16088 | /* This structure is used to hold a stack of .set values. */ | |
16089 | ||
e972090a NC |
16090 | struct mips_option_stack |
16091 | { | |
252b5132 RH |
16092 | struct mips_option_stack *next; |
16093 | struct mips_set_options options; | |
16094 | }; | |
16095 | ||
16096 | static struct mips_option_stack *mips_opts_stack; | |
16097 | ||
16098 | /* Handle the .set pseudo-op. */ | |
16099 | ||
16100 | static void | |
17a2f251 | 16101 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16102 | { |
16103 | char *name = input_line_pointer, ch; | |
16104 | ||
16105 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16106 | ++input_line_pointer; |
252b5132 RH |
16107 | ch = *input_line_pointer; |
16108 | *input_line_pointer = '\0'; | |
16109 | ||
16110 | if (strcmp (name, "reorder") == 0) | |
16111 | { | |
7d10b47d RS |
16112 | if (mips_opts.noreorder) |
16113 | end_noreorder (); | |
252b5132 RH |
16114 | } |
16115 | else if (strcmp (name, "noreorder") == 0) | |
16116 | { | |
7d10b47d RS |
16117 | if (!mips_opts.noreorder) |
16118 | start_noreorder (); | |
252b5132 | 16119 | } |
741fe287 MR |
16120 | else if (strncmp (name, "at=", 3) == 0) |
16121 | { | |
16122 | char *s = name + 3; | |
16123 | ||
16124 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16125 | as_bad (_("Unrecognized register name `%s'"), s); | |
16126 | } | |
252b5132 RH |
16127 | else if (strcmp (name, "at") == 0) |
16128 | { | |
741fe287 | 16129 | mips_opts.at = ATREG; |
252b5132 RH |
16130 | } |
16131 | else if (strcmp (name, "noat") == 0) | |
16132 | { | |
741fe287 | 16133 | mips_opts.at = ZERO; |
252b5132 RH |
16134 | } |
16135 | else if (strcmp (name, "macro") == 0) | |
16136 | { | |
16137 | mips_opts.warn_about_macros = 0; | |
16138 | } | |
16139 | else if (strcmp (name, "nomacro") == 0) | |
16140 | { | |
16141 | if (mips_opts.noreorder == 0) | |
16142 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16143 | mips_opts.warn_about_macros = 1; | |
16144 | } | |
16145 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16146 | { | |
16147 | mips_opts.nomove = 0; | |
16148 | } | |
16149 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16150 | { | |
16151 | mips_opts.nomove = 1; | |
16152 | } | |
16153 | else if (strcmp (name, "bopt") == 0) | |
16154 | { | |
16155 | mips_opts.nobopt = 0; | |
16156 | } | |
16157 | else if (strcmp (name, "nobopt") == 0) | |
16158 | { | |
16159 | mips_opts.nobopt = 1; | |
16160 | } | |
ad3fea08 TS |
16161 | else if (strcmp (name, "gp=default") == 0) |
16162 | mips_opts.gp32 = file_mips_gp32; | |
16163 | else if (strcmp (name, "gp=32") == 0) | |
16164 | mips_opts.gp32 = 1; | |
16165 | else if (strcmp (name, "gp=64") == 0) | |
16166 | { | |
16167 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16168 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16169 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16170 | mips_opts.gp32 = 0; | |
16171 | } | |
16172 | else if (strcmp (name, "fp=default") == 0) | |
16173 | mips_opts.fp32 = file_mips_fp32; | |
16174 | else if (strcmp (name, "fp=32") == 0) | |
16175 | mips_opts.fp32 = 1; | |
16176 | else if (strcmp (name, "fp=64") == 0) | |
16177 | { | |
16178 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16179 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16180 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16181 | mips_opts.fp32 = 0; | |
16182 | } | |
037b32b9 AN |
16183 | else if (strcmp (name, "softfloat") == 0) |
16184 | mips_opts.soft_float = 1; | |
16185 | else if (strcmp (name, "hardfloat") == 0) | |
16186 | mips_opts.soft_float = 0; | |
16187 | else if (strcmp (name, "singlefloat") == 0) | |
16188 | mips_opts.single_float = 1; | |
16189 | else if (strcmp (name, "doublefloat") == 0) | |
16190 | mips_opts.single_float = 0; | |
252b5132 RH |
16191 | else if (strcmp (name, "mips16") == 0 |
16192 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16193 | { |
16194 | if (mips_opts.micromips == 1) | |
16195 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16196 | mips_opts.mips16 = 1; | |
16197 | } | |
252b5132 RH |
16198 | else if (strcmp (name, "nomips16") == 0 |
16199 | || strcmp (name, "noMIPS-16") == 0) | |
16200 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16201 | else if (strcmp (name, "micromips") == 0) |
16202 | { | |
16203 | if (mips_opts.mips16 == 1) | |
16204 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16205 | mips_opts.micromips = 1; | |
16206 | } | |
16207 | else if (strcmp (name, "nomicromips") == 0) | |
16208 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16209 | else if (strcmp (name, "smartmips") == 0) |
16210 | { | |
ad3fea08 | 16211 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16212 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16213 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16214 | mips_opts.ase_smartmips = 1; | |
16215 | } | |
16216 | else if (strcmp (name, "nosmartmips") == 0) | |
16217 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16218 | else if (strcmp (name, "mips3d") == 0) |
16219 | mips_opts.ase_mips3d = 1; | |
16220 | else if (strcmp (name, "nomips3d") == 0) | |
16221 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16222 | else if (strcmp (name, "mdmx") == 0) |
16223 | mips_opts.ase_mdmx = 1; | |
16224 | else if (strcmp (name, "nomdmx") == 0) | |
16225 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16226 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16227 | { |
16228 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16229 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16230 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16231 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16232 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16233 | } |
74cd071d | 16234 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16235 | { |
16236 | mips_opts.ase_dsp = 0; | |
16237 | mips_opts.ase_dspr2 = 0; | |
16238 | } | |
16239 | else if (strcmp (name, "dspr2") == 0) | |
16240 | { | |
16241 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16242 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16243 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16244 | mips_opts.ase_dspr2 = 1; | |
16245 | mips_opts.ase_dsp = 1; | |
16246 | } | |
16247 | else if (strcmp (name, "nodspr2") == 0) | |
16248 | { | |
16249 | mips_opts.ase_dspr2 = 0; | |
16250 | mips_opts.ase_dsp = 0; | |
16251 | } | |
ef2e4d86 | 16252 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16253 | { |
16254 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16255 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16256 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16257 | mips_opts.ase_mt = 1; | |
16258 | } | |
ef2e4d86 CF |
16259 | else if (strcmp (name, "nomt") == 0) |
16260 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16261 | else if (strcmp (name, "mcu") == 0) |
16262 | mips_opts.ase_mcu = 1; | |
16263 | else if (strcmp (name, "nomcu") == 0) | |
16264 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16265 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16266 | { |
af7ee8bf | 16267 | int reset = 0; |
252b5132 | 16268 | |
1a2c1fad CD |
16269 | /* Permit the user to change the ISA and architecture on the fly. |
16270 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16271 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16272 | { |
16273 | reset = 1; | |
16274 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16275 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16276 | } |
16277 | else if (strncmp (name, "arch=", 5) == 0) | |
16278 | { | |
16279 | const struct mips_cpu_info *p; | |
16280 | ||
16281 | p = mips_parse_cpu("internal use", name + 5); | |
16282 | if (!p) | |
16283 | as_bad (_("unknown architecture %s"), name + 5); | |
16284 | else | |
16285 | { | |
16286 | mips_opts.arch = p->cpu; | |
16287 | mips_opts.isa = p->isa; | |
16288 | } | |
16289 | } | |
81a21e38 TS |
16290 | else if (strncmp (name, "mips", 4) == 0) |
16291 | { | |
16292 | const struct mips_cpu_info *p; | |
16293 | ||
16294 | p = mips_parse_cpu("internal use", name); | |
16295 | if (!p) | |
16296 | as_bad (_("unknown ISA level %s"), name + 4); | |
16297 | else | |
16298 | { | |
16299 | mips_opts.arch = p->cpu; | |
16300 | mips_opts.isa = p->isa; | |
16301 | } | |
16302 | } | |
af7ee8bf | 16303 | else |
81a21e38 | 16304 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16305 | |
16306 | switch (mips_opts.isa) | |
98d3f06f KH |
16307 | { |
16308 | case 0: | |
98d3f06f | 16309 | break; |
af7ee8bf CD |
16310 | case ISA_MIPS1: |
16311 | case ISA_MIPS2: | |
16312 | case ISA_MIPS32: | |
16313 | case ISA_MIPS32R2: | |
98d3f06f KH |
16314 | mips_opts.gp32 = 1; |
16315 | mips_opts.fp32 = 1; | |
16316 | break; | |
af7ee8bf CD |
16317 | case ISA_MIPS3: |
16318 | case ISA_MIPS4: | |
16319 | case ISA_MIPS5: | |
16320 | case ISA_MIPS64: | |
5f74bc13 | 16321 | case ISA_MIPS64R2: |
98d3f06f KH |
16322 | mips_opts.gp32 = 0; |
16323 | mips_opts.fp32 = 0; | |
16324 | break; | |
16325 | default: | |
16326 | as_bad (_("unknown ISA level %s"), name + 4); | |
16327 | break; | |
16328 | } | |
af7ee8bf | 16329 | if (reset) |
98d3f06f | 16330 | { |
af7ee8bf CD |
16331 | mips_opts.gp32 = file_mips_gp32; |
16332 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16333 | } |
252b5132 RH |
16334 | } |
16335 | else if (strcmp (name, "autoextend") == 0) | |
16336 | mips_opts.noautoextend = 0; | |
16337 | else if (strcmp (name, "noautoextend") == 0) | |
16338 | mips_opts.noautoextend = 1; | |
16339 | else if (strcmp (name, "push") == 0) | |
16340 | { | |
16341 | struct mips_option_stack *s; | |
16342 | ||
16343 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16344 | s->next = mips_opts_stack; | |
16345 | s->options = mips_opts; | |
16346 | mips_opts_stack = s; | |
16347 | } | |
16348 | else if (strcmp (name, "pop") == 0) | |
16349 | { | |
16350 | struct mips_option_stack *s; | |
16351 | ||
16352 | s = mips_opts_stack; | |
16353 | if (s == NULL) | |
16354 | as_bad (_(".set pop with no .set push")); | |
16355 | else | |
16356 | { | |
16357 | /* If we're changing the reorder mode we need to handle | |
16358 | delay slots correctly. */ | |
16359 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16360 | start_noreorder (); |
252b5132 | 16361 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16362 | end_noreorder (); |
252b5132 RH |
16363 | |
16364 | mips_opts = s->options; | |
16365 | mips_opts_stack = s->next; | |
16366 | free (s); | |
16367 | } | |
16368 | } | |
aed1a261 RS |
16369 | else if (strcmp (name, "sym32") == 0) |
16370 | mips_opts.sym32 = TRUE; | |
16371 | else if (strcmp (name, "nosym32") == 0) | |
16372 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16373 | else if (strchr (name, ',')) |
16374 | { | |
16375 | /* Generic ".set" directive; use the generic handler. */ | |
16376 | *input_line_pointer = ch; | |
16377 | input_line_pointer = name; | |
16378 | s_set (0); | |
16379 | return; | |
16380 | } | |
252b5132 RH |
16381 | else |
16382 | { | |
16383 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16384 | } | |
16385 | *input_line_pointer = ch; | |
16386 | demand_empty_rest_of_line (); | |
16387 | } | |
16388 | ||
16389 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16390 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16391 | ||
16392 | static void | |
17a2f251 | 16393 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16394 | { |
16395 | mips_pic = SVR4_PIC; | |
143d77c5 | 16396 | mips_abicalls = TRUE; |
4d0d148d TS |
16397 | |
16398 | if (g_switch_seen && g_switch_value != 0) | |
16399 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16400 | g_switch_value = 0; | |
16401 | ||
252b5132 RH |
16402 | bfd_set_gp_size (stdoutput, 0); |
16403 | demand_empty_rest_of_line (); | |
16404 | } | |
16405 | ||
16406 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16407 | PIC code. It sets the $gp register for the function based on the | |
16408 | function address, which is in the register named in the argument. | |
16409 | This uses a relocation against _gp_disp, which is handled specially | |
16410 | by the linker. The result is: | |
16411 | lui $gp,%hi(_gp_disp) | |
16412 | addiu $gp,$gp,%lo(_gp_disp) | |
16413 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16414 | The .cpload argument is normally $25 == $t9. |
16415 | ||
16416 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16417 | lui $gp,%hi(__gnu_local_gp) |
16418 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16419 | and the argument is ignored. This saves an instruction, but the |
16420 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16421 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16422 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16423 | |
16424 | static void | |
17a2f251 | 16425 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16426 | { |
16427 | expressionS ex; | |
aa6975fb ILT |
16428 | int reg; |
16429 | int in_shared; | |
252b5132 | 16430 | |
6478892d TS |
16431 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16432 | .cpload is ignored. */ | |
16433 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16434 | { |
16435 | s_ignore (0); | |
16436 | return; | |
16437 | } | |
16438 | ||
a276b80c MR |
16439 | if (mips_opts.mips16) |
16440 | { | |
16441 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16442 | ignore_rest_of_line (); | |
16443 | return; | |
16444 | } | |
16445 | ||
d3ecfc59 | 16446 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16447 | if (mips_opts.noreorder == 0) |
16448 | as_warn (_(".cpload not in noreorder section")); | |
16449 | ||
aa6975fb ILT |
16450 | reg = tc_get_register (0); |
16451 | ||
16452 | /* If we need to produce a 64-bit address, we are better off using | |
16453 | the default instruction sequence. */ | |
aed1a261 | 16454 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16455 | |
252b5132 | 16456 | ex.X_op = O_symbol; |
bbe506e8 TS |
16457 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16458 | "__gnu_local_gp"); | |
252b5132 RH |
16459 | ex.X_op_symbol = NULL; |
16460 | ex.X_add_number = 0; | |
16461 | ||
16462 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16463 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16464 | |
584892a6 | 16465 | macro_start (); |
67c0d1eb RS |
16466 | macro_build_lui (&ex, mips_gp_register); |
16467 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16468 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16469 | if (in_shared) |
16470 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16471 | mips_gp_register, reg); | |
584892a6 | 16472 | macro_end (); |
252b5132 RH |
16473 | |
16474 | demand_empty_rest_of_line (); | |
16475 | } | |
16476 | ||
6478892d TS |
16477 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16478 | .cpsetup $reg1, offset|$reg2, label | |
16479 | ||
16480 | If offset is given, this results in: | |
16481 | sd $gp, offset($sp) | |
956cd1d6 | 16482 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16483 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16484 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16485 | |
16486 | If $reg2 is given, this results in: | |
16487 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16488 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16489 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16490 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16491 | $reg1 is normally $25 == $t9. |
16492 | ||
16493 | The -mno-shared option replaces the last three instructions with | |
16494 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16495 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16496 | |
6478892d | 16497 | static void |
17a2f251 | 16498 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16499 | { |
16500 | expressionS ex_off; | |
16501 | expressionS ex_sym; | |
16502 | int reg1; | |
6478892d | 16503 | |
8586fc66 | 16504 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16505 | We also need NewABI support. */ |
16506 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16507 | { | |
16508 | s_ignore (0); | |
16509 | return; | |
16510 | } | |
16511 | ||
a276b80c MR |
16512 | if (mips_opts.mips16) |
16513 | { | |
16514 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16515 | ignore_rest_of_line (); | |
16516 | return; | |
16517 | } | |
16518 | ||
6478892d TS |
16519 | reg1 = tc_get_register (0); |
16520 | SKIP_WHITESPACE (); | |
16521 | if (*input_line_pointer != ',') | |
16522 | { | |
16523 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16524 | return; | |
16525 | } | |
16526 | else | |
80245285 | 16527 | ++input_line_pointer; |
6478892d TS |
16528 | SKIP_WHITESPACE (); |
16529 | if (*input_line_pointer == '$') | |
80245285 TS |
16530 | { |
16531 | mips_cpreturn_register = tc_get_register (0); | |
16532 | mips_cpreturn_offset = -1; | |
16533 | } | |
6478892d | 16534 | else |
80245285 TS |
16535 | { |
16536 | mips_cpreturn_offset = get_absolute_expression (); | |
16537 | mips_cpreturn_register = -1; | |
16538 | } | |
6478892d TS |
16539 | SKIP_WHITESPACE (); |
16540 | if (*input_line_pointer != ',') | |
16541 | { | |
16542 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16543 | return; | |
16544 | } | |
16545 | else | |
f9419b05 | 16546 | ++input_line_pointer; |
6478892d | 16547 | SKIP_WHITESPACE (); |
f21f8242 | 16548 | expression (&ex_sym); |
6478892d | 16549 | |
584892a6 | 16550 | macro_start (); |
6478892d TS |
16551 | if (mips_cpreturn_register == -1) |
16552 | { | |
16553 | ex_off.X_op = O_constant; | |
16554 | ex_off.X_add_symbol = NULL; | |
16555 | ex_off.X_op_symbol = NULL; | |
16556 | ex_off.X_add_number = mips_cpreturn_offset; | |
16557 | ||
67c0d1eb | 16558 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16559 | BFD_RELOC_LO16, SP); |
6478892d TS |
16560 | } |
16561 | else | |
67c0d1eb | 16562 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16563 | mips_gp_register, 0); |
6478892d | 16564 | |
aed1a261 | 16565 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16566 | { |
df58fc94 | 16567 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16568 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16569 | BFD_RELOC_HI16_S); | |
16570 | ||
16571 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16572 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16573 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16574 | ||
16575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16576 | mips_gp_register, reg1); | |
16577 | } | |
16578 | else | |
16579 | { | |
16580 | expressionS ex; | |
16581 | ||
16582 | ex.X_op = O_symbol; | |
4184909a | 16583 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16584 | ex.X_op_symbol = NULL; |
16585 | ex.X_add_number = 0; | |
6e1304d8 | 16586 | |
aa6975fb ILT |
16587 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16588 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16589 | ||
16590 | macro_build_lui (&ex, mips_gp_register); | |
16591 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16592 | mips_gp_register, BFD_RELOC_LO16); | |
16593 | } | |
f21f8242 | 16594 | |
584892a6 | 16595 | macro_end (); |
6478892d TS |
16596 | |
16597 | demand_empty_rest_of_line (); | |
16598 | } | |
16599 | ||
16600 | static void | |
17a2f251 | 16601 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16602 | { |
16603 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16604 | .cplocal is ignored. */ |
6478892d TS |
16605 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16606 | { | |
16607 | s_ignore (0); | |
16608 | return; | |
16609 | } | |
16610 | ||
a276b80c MR |
16611 | if (mips_opts.mips16) |
16612 | { | |
16613 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16614 | ignore_rest_of_line (); | |
16615 | return; | |
16616 | } | |
16617 | ||
6478892d | 16618 | mips_gp_register = tc_get_register (0); |
85b51719 | 16619 | demand_empty_rest_of_line (); |
6478892d TS |
16620 | } |
16621 | ||
252b5132 RH |
16622 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16623 | offset from $sp. The offset is remembered, and after making a PIC | |
16624 | call $gp is restored from that location. */ | |
16625 | ||
16626 | static void | |
17a2f251 | 16627 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16628 | { |
16629 | expressionS ex; | |
252b5132 | 16630 | |
6478892d | 16631 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16632 | .cprestore is ignored. */ |
6478892d | 16633 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16634 | { |
16635 | s_ignore (0); | |
16636 | return; | |
16637 | } | |
16638 | ||
a276b80c MR |
16639 | if (mips_opts.mips16) |
16640 | { | |
16641 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16642 | ignore_rest_of_line (); | |
16643 | return; | |
16644 | } | |
16645 | ||
252b5132 | 16646 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16647 | mips_cprestore_valid = 1; |
252b5132 RH |
16648 | |
16649 | ex.X_op = O_constant; | |
16650 | ex.X_add_symbol = NULL; | |
16651 | ex.X_op_symbol = NULL; | |
16652 | ex.X_add_number = mips_cprestore_offset; | |
16653 | ||
584892a6 | 16654 | macro_start (); |
67c0d1eb RS |
16655 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16656 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16657 | macro_end (); |
252b5132 RH |
16658 | |
16659 | demand_empty_rest_of_line (); | |
16660 | } | |
16661 | ||
6478892d | 16662 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16663 | was given in the preceding .cpsetup, it results in: |
6478892d | 16664 | ld $gp, offset($sp) |
76b3015f | 16665 | |
6478892d | 16666 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16667 | daddu $gp, $reg2, $0 */ |
16668 | ||
6478892d | 16669 | static void |
17a2f251 | 16670 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16671 | { |
16672 | expressionS ex; | |
6478892d TS |
16673 | |
16674 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16675 | We also need NewABI support. */ | |
16676 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16677 | { | |
16678 | s_ignore (0); | |
16679 | return; | |
16680 | } | |
16681 | ||
a276b80c MR |
16682 | if (mips_opts.mips16) |
16683 | { | |
16684 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16685 | ignore_rest_of_line (); | |
16686 | return; | |
16687 | } | |
16688 | ||
584892a6 | 16689 | macro_start (); |
6478892d TS |
16690 | if (mips_cpreturn_register == -1) |
16691 | { | |
16692 | ex.X_op = O_constant; | |
16693 | ex.X_add_symbol = NULL; | |
16694 | ex.X_op_symbol = NULL; | |
16695 | ex.X_add_number = mips_cpreturn_offset; | |
16696 | ||
67c0d1eb | 16697 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16698 | } |
16699 | else | |
67c0d1eb | 16700 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16701 | mips_cpreturn_register, 0); |
584892a6 | 16702 | macro_end (); |
6478892d TS |
16703 | |
16704 | demand_empty_rest_of_line (); | |
16705 | } | |
16706 | ||
d0f13682 CLT |
16707 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16708 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16709 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16710 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16711 | |
16712 | static void | |
d0f13682 CLT |
16713 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16714 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16715 | { |
16716 | expressionS ex; | |
16717 | char *p; | |
16718 | ||
16719 | expression (&ex); | |
16720 | ||
16721 | if (ex.X_op != O_symbol) | |
16722 | { | |
d0f13682 | 16723 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16724 | ignore_rest_of_line (); |
16725 | } | |
16726 | ||
16727 | p = frag_more (bytes); | |
16728 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16729 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16730 | demand_empty_rest_of_line (); |
de64cffd | 16731 | mips_clear_insn_labels (); |
741d6ea8 JM |
16732 | } |
16733 | ||
16734 | /* Handle .dtprelword. */ | |
16735 | ||
16736 | static void | |
16737 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16738 | { | |
d0f13682 | 16739 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16740 | } |
16741 | ||
16742 | /* Handle .dtpreldword. */ | |
16743 | ||
16744 | static void | |
16745 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16746 | { | |
d0f13682 CLT |
16747 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16748 | } | |
16749 | ||
16750 | /* Handle .tprelword. */ | |
16751 | ||
16752 | static void | |
16753 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16754 | { | |
16755 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16756 | } | |
16757 | ||
16758 | /* Handle .tpreldword. */ | |
16759 | ||
16760 | static void | |
16761 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16762 | { | |
16763 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16764 | } |
16765 | ||
6478892d TS |
16766 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16767 | code. It sets the offset to use in gp_rel relocations. */ | |
16768 | ||
16769 | static void | |
17a2f251 | 16770 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16771 | { |
16772 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16773 | We also need NewABI support. */ | |
16774 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16775 | { | |
16776 | s_ignore (0); | |
16777 | return; | |
16778 | } | |
16779 | ||
def2e0dd | 16780 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16781 | |
16782 | demand_empty_rest_of_line (); | |
16783 | } | |
16784 | ||
252b5132 RH |
16785 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16786 | code. It generates a 32 bit GP relative reloc. */ | |
16787 | ||
16788 | static void | |
17a2f251 | 16789 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16790 | { |
a8dbcb85 TS |
16791 | segment_info_type *si; |
16792 | struct insn_label_list *l; | |
252b5132 RH |
16793 | expressionS ex; |
16794 | char *p; | |
16795 | ||
16796 | /* When not generating PIC code, this is treated as .word. */ | |
16797 | if (mips_pic != SVR4_PIC) | |
16798 | { | |
16799 | s_cons (2); | |
16800 | return; | |
16801 | } | |
16802 | ||
a8dbcb85 TS |
16803 | si = seg_info (now_seg); |
16804 | l = si->label_list; | |
7d10b47d | 16805 | mips_emit_delays (); |
252b5132 | 16806 | if (auto_align) |
462427c4 | 16807 | mips_align (2, 0, l); |
252b5132 RH |
16808 | |
16809 | expression (&ex); | |
a1facbec | 16810 | mips_clear_insn_labels (); |
252b5132 RH |
16811 | |
16812 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16813 | { | |
16814 | as_bad (_("Unsupported use of .gpword")); | |
16815 | ignore_rest_of_line (); | |
16816 | } | |
16817 | ||
16818 | p = frag_more (4); | |
17a2f251 | 16819 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16820 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16821 | BFD_RELOC_GPREL32); |
252b5132 RH |
16822 | |
16823 | demand_empty_rest_of_line (); | |
16824 | } | |
16825 | ||
10181a0d | 16826 | static void |
17a2f251 | 16827 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16828 | { |
a8dbcb85 TS |
16829 | segment_info_type *si; |
16830 | struct insn_label_list *l; | |
10181a0d AO |
16831 | expressionS ex; |
16832 | char *p; | |
16833 | ||
16834 | /* When not generating PIC code, this is treated as .dword. */ | |
16835 | if (mips_pic != SVR4_PIC) | |
16836 | { | |
16837 | s_cons (3); | |
16838 | return; | |
16839 | } | |
16840 | ||
a8dbcb85 TS |
16841 | si = seg_info (now_seg); |
16842 | l = si->label_list; | |
7d10b47d | 16843 | mips_emit_delays (); |
10181a0d | 16844 | if (auto_align) |
462427c4 | 16845 | mips_align (3, 0, l); |
10181a0d AO |
16846 | |
16847 | expression (&ex); | |
a1facbec | 16848 | mips_clear_insn_labels (); |
10181a0d AO |
16849 | |
16850 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16851 | { | |
16852 | as_bad (_("Unsupported use of .gpdword")); | |
16853 | ignore_rest_of_line (); | |
16854 | } | |
16855 | ||
16856 | p = frag_more (8); | |
17a2f251 | 16857 | md_number_to_chars (p, 0, 8); |
a105a300 | 16858 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16859 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16860 | |
16861 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16862 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16863 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16864 | |
16865 | demand_empty_rest_of_line (); | |
16866 | } | |
16867 | ||
252b5132 RH |
16868 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16869 | tables in SVR4 PIC code. */ | |
16870 | ||
16871 | static void | |
17a2f251 | 16872 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16873 | { |
252b5132 RH |
16874 | int reg; |
16875 | ||
10181a0d AO |
16876 | /* This is ignored when not generating SVR4 PIC code. */ |
16877 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16878 | { |
16879 | s_ignore (0); | |
16880 | return; | |
16881 | } | |
16882 | ||
16883 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16884 | macro_start (); |
252b5132 | 16885 | reg = tc_get_register (0); |
67c0d1eb | 16886 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16887 | macro_end (); |
252b5132 | 16888 | |
bdaaa2e1 | 16889 | demand_empty_rest_of_line (); |
252b5132 RH |
16890 | } |
16891 | ||
16892 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16893 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16894 | such as generating jalx instructions when needed. We also make |
16895 | them odd for the duration of the assembly, in order to generate the | |
16896 | right sort of code. We will make them even in the adjust_symtab | |
16897 | routine, while leaving them marked. This is convenient for the | |
16898 | debugger and the disassembler. The linker knows to make them odd | |
16899 | again. */ | |
16900 | ||
16901 | static void | |
17a2f251 | 16902 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16903 | { |
df58fc94 | 16904 | mips_mark_labels (); |
252b5132 RH |
16905 | |
16906 | demand_empty_rest_of_line (); | |
16907 | } | |
16908 | ||
16909 | /* Handle a .stabn directive. We need these in order to mark a label | |
16910 | as being a mips16 text label correctly. Sometimes the compiler | |
16911 | will emit a label, followed by a .stabn, and then switch sections. | |
16912 | If the label and .stabn are in mips16 mode, then the label is | |
16913 | really a mips16 text label. */ | |
16914 | ||
16915 | static void | |
17a2f251 | 16916 | s_mips_stab (int type) |
252b5132 | 16917 | { |
f9419b05 | 16918 | if (type == 'n') |
df58fc94 | 16919 | mips_mark_labels (); |
252b5132 RH |
16920 | |
16921 | s_stab (type); | |
16922 | } | |
16923 | ||
54f4ddb3 | 16924 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16925 | |
16926 | static void | |
17a2f251 | 16927 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16928 | { |
16929 | char *name; | |
16930 | int c; | |
16931 | symbolS *symbolP; | |
16932 | expressionS exp; | |
16933 | ||
16934 | name = input_line_pointer; | |
16935 | c = get_symbol_end (); | |
16936 | symbolP = symbol_find_or_make (name); | |
16937 | S_SET_WEAK (symbolP); | |
16938 | *input_line_pointer = c; | |
16939 | ||
16940 | SKIP_WHITESPACE (); | |
16941 | ||
16942 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16943 | { | |
16944 | if (S_IS_DEFINED (symbolP)) | |
16945 | { | |
20203fb9 | 16946 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16947 | S_GET_NAME (symbolP)); |
16948 | ignore_rest_of_line (); | |
16949 | return; | |
16950 | } | |
bdaaa2e1 | 16951 | |
252b5132 RH |
16952 | if (*input_line_pointer == ',') |
16953 | { | |
16954 | ++input_line_pointer; | |
16955 | SKIP_WHITESPACE (); | |
16956 | } | |
bdaaa2e1 | 16957 | |
252b5132 RH |
16958 | expression (&exp); |
16959 | if (exp.X_op != O_symbol) | |
16960 | { | |
20203fb9 | 16961 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16962 | ignore_rest_of_line (); |
252b5132 RH |
16963 | return; |
16964 | } | |
49309057 | 16965 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16966 | } |
16967 | ||
16968 | demand_empty_rest_of_line (); | |
16969 | } | |
16970 | ||
16971 | /* Parse a register string into a number. Called from the ECOFF code | |
16972 | to parse .frame. The argument is non-zero if this is the frame | |
16973 | register, so that we can record it in mips_frame_reg. */ | |
16974 | ||
16975 | int | |
17a2f251 | 16976 | tc_get_register (int frame) |
252b5132 | 16977 | { |
707bfff6 | 16978 | unsigned int reg; |
252b5132 RH |
16979 | |
16980 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16981 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16982 | reg = 0; | |
252b5132 | 16983 | if (frame) |
7a621144 DJ |
16984 | { |
16985 | mips_frame_reg = reg != 0 ? reg : SP; | |
16986 | mips_frame_reg_valid = 1; | |
16987 | mips_cprestore_valid = 0; | |
16988 | } | |
252b5132 RH |
16989 | return reg; |
16990 | } | |
16991 | ||
16992 | valueT | |
17a2f251 | 16993 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16994 | { |
16995 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16996 | ||
b4c71f56 TS |
16997 | if (IS_ELF) |
16998 | { | |
16999 | /* We don't need to align ELF sections to the full alignment. | |
17000 | However, Irix 5 may prefer that we align them at least to a 16 | |
17001 | byte boundary. We don't bother to align the sections if we | |
17002 | are targeted for an embedded system. */ | |
c41e87e3 | 17003 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
17004 | return addr; |
17005 | if (align > 4) | |
17006 | align = 4; | |
17007 | } | |
252b5132 RH |
17008 | |
17009 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17010 | } | |
17011 | ||
17012 | /* Utility routine, called from above as well. If called while the | |
17013 | input file is still being read, it's only an approximation. (For | |
17014 | example, a symbol may later become defined which appeared to be | |
17015 | undefined earlier.) */ | |
17016 | ||
17017 | static int | |
17a2f251 | 17018 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17019 | { |
17020 | if (sym == 0) | |
17021 | return 0; | |
17022 | ||
4d0d148d | 17023 | if (g_switch_value > 0) |
252b5132 RH |
17024 | { |
17025 | const char *symname; | |
17026 | int change; | |
17027 | ||
c9914766 | 17028 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17029 | register. It can be if it is smaller than the -G size or if |
17030 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17031 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17032 | they can. */ |
17033 | symname = S_GET_NAME (sym); | |
17034 | if (symname != (const char *) NULL | |
17035 | && (strcmp (symname, "eprol") == 0 | |
17036 | || strcmp (symname, "etext") == 0 | |
17037 | || strcmp (symname, "_gp") == 0 | |
17038 | || strcmp (symname, "edata") == 0 | |
17039 | || strcmp (symname, "_fbss") == 0 | |
17040 | || strcmp (symname, "_fdata") == 0 | |
17041 | || strcmp (symname, "_ftext") == 0 | |
17042 | || strcmp (symname, "end") == 0 | |
17043 | || strcmp (symname, "_gp_disp") == 0)) | |
17044 | change = 1; | |
17045 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17046 | && (0 | |
17047 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17048 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17049 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17050 | <= g_switch_value)) | |
252b5132 RH |
17051 | #endif |
17052 | /* We must defer this decision until after the whole | |
17053 | file has been read, since there might be a .extern | |
17054 | after the first use of this symbol. */ | |
17055 | || (before_relaxing | |
17056 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17057 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17058 | #endif |
17059 | && S_GET_VALUE (sym) == 0) | |
17060 | || (S_GET_VALUE (sym) != 0 | |
17061 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17062 | change = 0; | |
17063 | else | |
17064 | { | |
17065 | const char *segname; | |
17066 | ||
17067 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17068 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17069 | && strcmp (segname, ".lit4") != 0); |
17070 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17071 | && strcmp (segname, ".sbss") != 0 |
17072 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17073 | && strncmp (segname, ".sbss.", 6) != 0 |
17074 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17075 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17076 | } |
17077 | return change; | |
17078 | } | |
17079 | else | |
c9914766 | 17080 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17081 | return 1; |
17082 | } | |
17083 | ||
5919d012 RS |
17084 | |
17085 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17086 | ||
17087 | static bfd_boolean | |
17a2f251 | 17088 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17089 | { |
17090 | asection *symsec; | |
5919d012 RS |
17091 | |
17092 | /* Handle the case of a symbol equated to another symbol. */ | |
17093 | while (symbol_equated_reloc_p (sym)) | |
17094 | { | |
17095 | symbolS *n; | |
17096 | ||
5f0fe04b | 17097 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17098 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17099 | if (n == sym) | |
17100 | break; | |
17101 | sym = n; | |
17102 | } | |
17103 | ||
df1f3cda DD |
17104 | if (symbol_section_p (sym)) |
17105 | return TRUE; | |
17106 | ||
5919d012 RS |
17107 | symsec = S_GET_SEGMENT (sym); |
17108 | ||
5919d012 | 17109 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17110 | return (!bfd_is_und_section (symsec) |
17111 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17112 | && !bfd_is_com_section (symsec) |
17113 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17114 | #ifdef OBJ_ELF |
17115 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17116 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17117 | #endif |
17118 | ); | |
17119 | } | |
17120 | ||
17121 | ||
252b5132 RH |
17122 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17123 | extended opcode. SEC is the section the frag is in. */ | |
17124 | ||
17125 | static int | |
17a2f251 | 17126 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17127 | { |
17128 | int type; | |
3994f87e | 17129 | const struct mips16_immed_operand *op; |
252b5132 RH |
17130 | offsetT val; |
17131 | int mintiny, maxtiny; | |
17132 | segT symsec; | |
98aa84af | 17133 | fragS *sym_frag; |
252b5132 RH |
17134 | |
17135 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17136 | return 0; | |
17137 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17138 | return 1; | |
17139 | ||
17140 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17141 | op = mips16_immed_operands; | |
17142 | while (op->type != type) | |
17143 | { | |
17144 | ++op; | |
9c2799c2 | 17145 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17146 | } |
17147 | ||
17148 | if (op->unsp) | |
17149 | { | |
17150 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17151 | { | |
17152 | mintiny = 1; | |
17153 | maxtiny = 1 << op->nbits; | |
17154 | } | |
17155 | else | |
17156 | { | |
17157 | mintiny = 0; | |
17158 | maxtiny = (1 << op->nbits) - 1; | |
17159 | } | |
17160 | } | |
17161 | else | |
17162 | { | |
17163 | mintiny = - (1 << (op->nbits - 1)); | |
17164 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17165 | } | |
17166 | ||
98aa84af | 17167 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17168 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17169 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17170 | |
17171 | if (op->pcrel) | |
17172 | { | |
17173 | addressT addr; | |
17174 | ||
17175 | /* We won't have the section when we are called from | |
17176 | mips_relax_frag. However, we will always have been called | |
17177 | from md_estimate_size_before_relax first. If this is a | |
17178 | branch to a different section, we mark it as such. If SEC is | |
17179 | NULL, and the frag is not marked, then it must be a branch to | |
17180 | the same section. */ | |
17181 | if (sec == NULL) | |
17182 | { | |
17183 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17184 | return 1; | |
17185 | } | |
17186 | else | |
17187 | { | |
98aa84af | 17188 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17189 | if (symsec != sec) |
17190 | { | |
17191 | fragp->fr_subtype = | |
17192 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17193 | ||
17194 | /* FIXME: We should support this, and let the linker | |
17195 | catch branches and loads that are out of range. */ | |
17196 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17197 | _("unsupported PC relative reference to different section")); | |
17198 | ||
17199 | return 1; | |
17200 | } | |
98aa84af AM |
17201 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17202 | /* Assume non-extended on the first relaxation pass. | |
17203 | The address we have calculated will be bogus if this is | |
17204 | a forward branch to another frag, as the forward frag | |
17205 | will have fr_address == 0. */ | |
17206 | return 0; | |
252b5132 RH |
17207 | } |
17208 | ||
17209 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17210 | the same section. If the relax_marker of the symbol fragment |
17211 | differs from the relax_marker of this fragment, we have not | |
17212 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17213 | in STRETCH in order to get a better estimate of the address. |
17214 | This particularly matters because of the shift bits. */ | |
17215 | if (stretch != 0 | |
98aa84af | 17216 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17217 | { |
17218 | fragS *f; | |
17219 | ||
17220 | /* Adjust stretch for any alignment frag. Note that if have | |
17221 | been expanding the earlier code, the symbol may be | |
17222 | defined in what appears to be an earlier frag. FIXME: | |
17223 | This doesn't handle the fr_subtype field, which specifies | |
17224 | a maximum number of bytes to skip when doing an | |
17225 | alignment. */ | |
98aa84af | 17226 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17227 | { |
17228 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17229 | { | |
17230 | if (stretch < 0) | |
17231 | stretch = - ((- stretch) | |
17232 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17233 | else | |
17234 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17235 | if (stretch == 0) | |
17236 | break; | |
17237 | } | |
17238 | } | |
17239 | if (f != NULL) | |
17240 | val += stretch; | |
17241 | } | |
17242 | ||
17243 | addr = fragp->fr_address + fragp->fr_fix; | |
17244 | ||
17245 | /* The base address rules are complicated. The base address of | |
17246 | a branch is the following instruction. The base address of a | |
17247 | PC relative load or add is the instruction itself, but if it | |
17248 | is in a delay slot (in which case it can not be extended) use | |
17249 | the address of the instruction whose delay slot it is in. */ | |
17250 | if (type == 'p' || type == 'q') | |
17251 | { | |
17252 | addr += 2; | |
17253 | ||
17254 | /* If we are currently assuming that this frag should be | |
17255 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17256 | higher. */ |
252b5132 RH |
17257 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17258 | addr += 2; | |
17259 | ||
17260 | /* Ignore the low bit in the target, since it will be set | |
17261 | for a text label. */ | |
17262 | if ((val & 1) != 0) | |
17263 | --val; | |
17264 | } | |
17265 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17266 | addr -= 4; | |
17267 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17268 | addr -= 2; | |
17269 | ||
17270 | val -= addr & ~ ((1 << op->shift) - 1); | |
17271 | ||
17272 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17273 | if (type == 'p' || type == 'q') | |
17274 | val /= 2; | |
17275 | ||
17276 | /* If any of the shifted bits are set, we must use an extended | |
17277 | opcode. If the address depends on the size of this | |
17278 | instruction, this can lead to a loop, so we arrange to always | |
17279 | use an extended opcode. We only check this when we are in | |
17280 | the main relaxation loop, when SEC is NULL. */ | |
17281 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17282 | { | |
17283 | fragp->fr_subtype = | |
17284 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17285 | return 1; | |
17286 | } | |
17287 | ||
17288 | /* If we are about to mark a frag as extended because the value | |
17289 | is precisely maxtiny + 1, then there is a chance of an | |
17290 | infinite loop as in the following code: | |
17291 | la $4,foo | |
17292 | .skip 1020 | |
17293 | .align 2 | |
17294 | foo: | |
17295 | In this case when the la is extended, foo is 0x3fc bytes | |
17296 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17297 | the la must be extended. To avoid this loop, we mark the | |
17298 | frag as extended if it was small, and is about to become | |
17299 | extended with a value of maxtiny + 1. */ | |
17300 | if (val == ((maxtiny + 1) << op->shift) | |
17301 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17302 | && sec == NULL) | |
17303 | { | |
17304 | fragp->fr_subtype = | |
17305 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17306 | return 1; | |
17307 | } | |
17308 | } | |
17309 | else if (symsec != absolute_section && sec != NULL) | |
17310 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17311 | ||
17312 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17313 | || val < (mintiny << op->shift) | |
17314 | || val > (maxtiny << op->shift)) | |
17315 | return 1; | |
17316 | else | |
17317 | return 0; | |
17318 | } | |
17319 | ||
4a6a3df4 AO |
17320 | /* Compute the length of a branch sequence, and adjust the |
17321 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17322 | worst-case length is computed, with UPDATE being used to indicate | |
17323 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17324 | branch is to be computed. */ | |
17325 | static int | |
17a2f251 | 17326 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17327 | { |
b34976b6 | 17328 | bfd_boolean toofar; |
4a6a3df4 AO |
17329 | int length; |
17330 | ||
17331 | if (fragp | |
17332 | && S_IS_DEFINED (fragp->fr_symbol) | |
17333 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17334 | { | |
17335 | addressT addr; | |
17336 | offsetT val; | |
17337 | ||
17338 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17339 | ||
17340 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17341 | ||
17342 | val -= addr; | |
17343 | ||
17344 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17345 | } | |
17346 | else if (fragp) | |
17347 | /* If the symbol is not defined or it's in a different segment, | |
17348 | assume the user knows what's going on and emit a short | |
17349 | branch. */ | |
b34976b6 | 17350 | toofar = FALSE; |
4a6a3df4 | 17351 | else |
b34976b6 | 17352 | toofar = TRUE; |
4a6a3df4 AO |
17353 | |
17354 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17355 | fragp->fr_subtype | |
66b3e8da MR |
17356 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17357 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17358 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17359 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17360 | toofar); | |
17361 | ||
17362 | length = 4; | |
17363 | if (toofar) | |
17364 | { | |
17365 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17366 | length += 8; | |
17367 | ||
17368 | if (mips_pic != NO_PIC) | |
17369 | { | |
17370 | /* Additional space for PIC loading of target address. */ | |
17371 | length += 8; | |
17372 | if (mips_opts.isa == ISA_MIPS1) | |
17373 | /* Additional space for $at-stabilizing nop. */ | |
17374 | length += 4; | |
17375 | } | |
17376 | ||
17377 | /* If branch is conditional. */ | |
17378 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17379 | length += 8; | |
17380 | } | |
b34976b6 | 17381 | |
4a6a3df4 AO |
17382 | return length; |
17383 | } | |
17384 | ||
df58fc94 RS |
17385 | /* Compute the length of a branch sequence, and adjust the |
17386 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17387 | worst-case length is computed, with UPDATE being used to indicate | |
17388 | whether an unconditional (-1), or regular (0) branch is to be | |
17389 | computed. */ | |
17390 | ||
17391 | static int | |
17392 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17393 | { | |
17394 | bfd_boolean toofar; | |
17395 | int length; | |
17396 | ||
17397 | if (fragp | |
17398 | && S_IS_DEFINED (fragp->fr_symbol) | |
17399 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17400 | { | |
17401 | addressT addr; | |
17402 | offsetT val; | |
17403 | ||
17404 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17405 | /* Ignore the low bit in the target, since it will be set | |
17406 | for a text label. */ | |
17407 | if ((val & 1) != 0) | |
17408 | --val; | |
17409 | ||
17410 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17411 | ||
17412 | val -= addr; | |
17413 | ||
17414 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17415 | } | |
17416 | else if (fragp) | |
17417 | /* If the symbol is not defined or it's in a different segment, | |
17418 | assume the user knows what's going on and emit a short | |
17419 | branch. */ | |
17420 | toofar = FALSE; | |
17421 | else | |
17422 | toofar = TRUE; | |
17423 | ||
17424 | if (fragp && update | |
17425 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17426 | fragp->fr_subtype = (toofar | |
17427 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17428 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17429 | ||
17430 | length = 4; | |
17431 | if (toofar) | |
17432 | { | |
17433 | bfd_boolean compact_known = fragp != NULL; | |
17434 | bfd_boolean compact = FALSE; | |
17435 | bfd_boolean uncond; | |
17436 | ||
17437 | if (compact_known) | |
17438 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17439 | if (fragp) | |
17440 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17441 | else | |
17442 | uncond = update < 0; | |
17443 | ||
17444 | /* If label is out of range, we turn branch <br>: | |
17445 | ||
17446 | <br> label # 4 bytes | |
17447 | 0: | |
17448 | ||
17449 | into: | |
17450 | ||
17451 | j label # 4 bytes | |
17452 | nop # 2 bytes if compact && !PIC | |
17453 | 0: | |
17454 | */ | |
17455 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17456 | length += 2; | |
17457 | ||
17458 | /* If assembling PIC code, we further turn: | |
17459 | ||
17460 | j label # 4 bytes | |
17461 | ||
17462 | into: | |
17463 | ||
17464 | lw/ld at, %got(label)(gp) # 4 bytes | |
17465 | d/addiu at, %lo(label) # 4 bytes | |
17466 | jr/c at # 2 bytes | |
17467 | */ | |
17468 | if (mips_pic != NO_PIC) | |
17469 | length += 6; | |
17470 | ||
17471 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17472 | ||
17473 | <brneg> 0f # 4 bytes | |
17474 | nop # 2 bytes if !compact | |
17475 | */ | |
17476 | if (!uncond) | |
17477 | length += (compact_known && compact) ? 4 : 6; | |
17478 | } | |
17479 | ||
17480 | return length; | |
17481 | } | |
17482 | ||
17483 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17484 | bit accordingly. */ | |
17485 | ||
17486 | static int | |
17487 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17488 | { | |
17489 | bfd_boolean toofar; | |
17490 | ||
df58fc94 RS |
17491 | if (fragp |
17492 | && S_IS_DEFINED (fragp->fr_symbol) | |
17493 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17494 | { | |
17495 | addressT addr; | |
17496 | offsetT val; | |
17497 | int type; | |
17498 | ||
17499 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17500 | /* Ignore the low bit in the target, since it will be set | |
17501 | for a text label. */ | |
17502 | if ((val & 1) != 0) | |
17503 | --val; | |
17504 | ||
17505 | /* Assume this is a 2-byte branch. */ | |
17506 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17507 | ||
17508 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17509 | long branches. */ | |
17510 | ||
17511 | val -= addr; | |
17512 | ||
17513 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17514 | if (type == 'D') | |
17515 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17516 | else if (type == 'E') | |
17517 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17518 | else | |
17519 | abort (); | |
17520 | } | |
17521 | else | |
17522 | /* If the symbol is not defined or it's in a different segment, | |
17523 | we emit a normal 32-bit branch. */ | |
17524 | toofar = TRUE; | |
17525 | ||
17526 | if (fragp && update | |
17527 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17528 | fragp->fr_subtype | |
17529 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17530 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17531 | ||
17532 | if (toofar) | |
17533 | return 4; | |
17534 | ||
17535 | return 2; | |
17536 | } | |
17537 | ||
252b5132 RH |
17538 | /* Estimate the size of a frag before relaxing. Unless this is the |
17539 | mips16, we are not really relaxing here, and the final size is | |
17540 | encoded in the subtype information. For the mips16, we have to | |
17541 | decide whether we are using an extended opcode or not. */ | |
17542 | ||
252b5132 | 17543 | int |
17a2f251 | 17544 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17545 | { |
5919d012 | 17546 | int change; |
252b5132 | 17547 | |
4a6a3df4 AO |
17548 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17549 | { | |
17550 | ||
b34976b6 AM |
17551 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17552 | ||
4a6a3df4 AO |
17553 | return fragp->fr_var; |
17554 | } | |
17555 | ||
252b5132 | 17556 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17557 | /* We don't want to modify the EXTENDED bit here; it might get us |
17558 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17559 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17560 | |
df58fc94 RS |
17561 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17562 | { | |
17563 | int length = 4; | |
17564 | ||
17565 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17566 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17567 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17568 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17569 | fragp->fr_var = length; | |
17570 | ||
17571 | return length; | |
17572 | } | |
17573 | ||
252b5132 | 17574 | if (mips_pic == NO_PIC) |
5919d012 | 17575 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17576 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17577 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17578 | else if (mips_pic == VXWORKS_PIC) |
17579 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17580 | change = 0; | |
252b5132 RH |
17581 | else |
17582 | abort (); | |
17583 | ||
17584 | if (change) | |
17585 | { | |
4d7206a2 | 17586 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17587 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17588 | } |
4d7206a2 RS |
17589 | else |
17590 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17591 | } |
17592 | ||
17593 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17594 | should be converted into a reloc against a section. */ |
252b5132 RH |
17595 | |
17596 | int | |
17a2f251 | 17597 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17598 | { |
252b5132 RH |
17599 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17600 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17601 | return 0; | |
a161fe53 | 17602 | |
252b5132 RH |
17603 | if (fixp->fx_addsy == NULL) |
17604 | return 1; | |
a161fe53 | 17605 | |
de7e6852 RS |
17606 | /* If symbol SYM is in a mergeable section, relocations of the form |
17607 | SYM + 0 can usually be made section-relative. The mergeable data | |
17608 | is then identified by the section offset rather than by the symbol. | |
17609 | ||
17610 | However, if we're generating REL LO16 relocations, the offset is split | |
17611 | between the LO16 and parterning high part relocation. The linker will | |
17612 | need to recalculate the complete offset in order to correctly identify | |
17613 | the merge data. | |
17614 | ||
17615 | The linker has traditionally not looked for the parterning high part | |
17616 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17617 | placed anywhere. Rather than break backwards compatibility by changing | |
17618 | this, it seems better not to force the issue, and instead keep the | |
17619 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17620 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17621 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17622 | && HAVE_IN_PLACE_ADDENDS |
17623 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17624 | return 0; | |
17625 | ||
ce70d90a MR |
17626 | /* There is no place to store an in-place offset for JALR relocations. |
17627 | Likewise an in-range offset of PC-relative relocations may overflow | |
17628 | the in-place relocatable field if recalculated against the start | |
17629 | address of the symbol's containing section. */ | |
17630 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17631 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17632 | return 0; |
17633 | ||
252b5132 | 17634 | #ifdef OBJ_ELF |
b314ec0e RS |
17635 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17636 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17637 | relocations against MIPS16 functions; in this case, the stub becomes | |
17638 | the function's canonical address. | |
17639 | ||
17640 | Floating-point stubs are stored in unique .mips16.call.* or | |
17641 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17642 | the first relocation in section S must be against F; this is how the | |
17643 | linker determines the target function. All relocations that might | |
17644 | resolve to T must also be against F. We therefore have the following | |
17645 | restrictions, which are given in an intentionally-redundant way: | |
17646 | ||
17647 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17648 | symbols. | |
17649 | ||
17650 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17651 | if that stub might be used. | |
17652 | ||
17653 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17654 | symbols. | |
17655 | ||
17656 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17657 | that stub might be used. | |
17658 | ||
17659 | There is a further restriction: | |
17660 | ||
df58fc94 RS |
17661 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17662 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17663 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17664 | encode the low bit. |
17665 | ||
df58fc94 RS |
17666 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17667 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17668 | such relocations on REL targets. | |
b314ec0e RS |
17669 | |
17670 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17671 | relocation against some symbol R, no relocation against R may be | |
17672 | reduced. (Note that this deals with (2) as well as (1) because | |
17673 | relocations against global symbols will never be reduced on ELF | |
17674 | targets.) This approach is a little simpler than trying to detect | |
17675 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17676 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17677 | if (IS_ELF |
b314ec0e | 17678 | && fixp->fx_subsy == NULL |
30c09090 | 17679 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17680 | || *symbol_get_tc (fixp->fx_addsy) |
17681 | || (HAVE_IN_PLACE_ADDENDS | |
17682 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17683 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17684 | return 0; |
17685 | #endif | |
a161fe53 | 17686 | |
252b5132 RH |
17687 | return 1; |
17688 | } | |
17689 | ||
17690 | /* Translate internal representation of relocation info to BFD target | |
17691 | format. */ | |
17692 | ||
17693 | arelent ** | |
17a2f251 | 17694 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17695 | { |
17696 | static arelent *retval[4]; | |
17697 | arelent *reloc; | |
17698 | bfd_reloc_code_real_type code; | |
17699 | ||
4b0cff4e TS |
17700 | memset (retval, 0, sizeof(retval)); |
17701 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17702 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17703 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17704 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17705 | ||
bad36eac DJ |
17706 | if (fixp->fx_pcrel) |
17707 | { | |
df58fc94 RS |
17708 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17709 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17710 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17711 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17712 | |
17713 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17714 | Relocations want only the symbol offset. */ | |
17715 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17716 | if (!IS_ELF) |
bad36eac DJ |
17717 | { |
17718 | /* A gruesome hack which is a result of the gruesome gas | |
17719 | reloc handling. What's worse, for COFF (as opposed to | |
17720 | ECOFF), we might need yet another copy of reloc->address. | |
17721 | See bfd_install_relocation. */ | |
17722 | reloc->addend += reloc->address; | |
17723 | } | |
17724 | } | |
17725 | else | |
17726 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17727 | |
438c16b8 TS |
17728 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17729 | entry to be used in the relocation's section offset. */ | |
17730 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17731 | { |
17732 | reloc->address = reloc->addend; | |
17733 | reloc->addend = 0; | |
17734 | } | |
17735 | ||
252b5132 | 17736 | code = fixp->fx_r_type; |
252b5132 | 17737 | |
bad36eac | 17738 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17739 | if (reloc->howto == NULL) |
17740 | { | |
17741 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17742 | _("Can not represent %s relocation in this object file format"), | |
17743 | bfd_get_reloc_code_name (code)); | |
17744 | retval[0] = NULL; | |
17745 | } | |
17746 | ||
17747 | return retval; | |
17748 | } | |
17749 | ||
17750 | /* Relax a machine dependent frag. This returns the amount by which | |
17751 | the current size of the frag should change. */ | |
17752 | ||
17753 | int | |
17a2f251 | 17754 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17755 | { |
4a6a3df4 AO |
17756 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17757 | { | |
17758 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17759 | |
17760 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17761 | |
17762 | return fragp->fr_var - old_var; | |
17763 | } | |
17764 | ||
df58fc94 RS |
17765 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17766 | { | |
17767 | offsetT old_var = fragp->fr_var; | |
17768 | offsetT new_var = 4; | |
17769 | ||
17770 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17771 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17772 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17773 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17774 | fragp->fr_var = new_var; | |
17775 | ||
17776 | return new_var - old_var; | |
17777 | } | |
17778 | ||
252b5132 RH |
17779 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17780 | return 0; | |
17781 | ||
c4e7957c | 17782 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17783 | { |
17784 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17785 | return 0; | |
17786 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17787 | return 2; | |
17788 | } | |
17789 | else | |
17790 | { | |
17791 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17792 | return 0; | |
17793 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17794 | return -2; | |
17795 | } | |
17796 | ||
17797 | return 0; | |
17798 | } | |
17799 | ||
17800 | /* Convert a machine dependent frag. */ | |
17801 | ||
17802 | void | |
17a2f251 | 17803 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17804 | { |
4a6a3df4 AO |
17805 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17806 | { | |
4d68580a | 17807 | char *buf; |
4a6a3df4 AO |
17808 | unsigned long insn; |
17809 | expressionS exp; | |
17810 | fixS *fixp; | |
b34976b6 | 17811 | |
4d68580a RS |
17812 | buf = fragp->fr_literal + fragp->fr_fix; |
17813 | insn = read_insn (buf); | |
b34976b6 | 17814 | |
4a6a3df4 AO |
17815 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17816 | { | |
17817 | /* We generate a fixup instead of applying it right now | |
17818 | because, if there are linker relaxations, we're going to | |
17819 | need the relocations. */ | |
17820 | exp.X_op = O_symbol; | |
17821 | exp.X_add_symbol = fragp->fr_symbol; | |
17822 | exp.X_add_number = fragp->fr_offset; | |
17823 | ||
4d68580a RS |
17824 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
17825 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
17826 | fixp->fx_file = fragp->fr_file; |
17827 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17828 | |
4d68580a | 17829 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17830 | } |
17831 | else | |
17832 | { | |
17833 | int i; | |
17834 | ||
17835 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17836 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17837 | |
17838 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17839 | goto uncond; | |
17840 | ||
17841 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17842 | { | |
17843 | /* Reverse the branch. */ | |
17844 | switch ((insn >> 28) & 0xf) | |
17845 | { | |
17846 | case 4: | |
17847 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17848 | have the condition reversed by tweaking a single | |
17849 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17850 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17851 | insn ^= 0x00010000; |
17852 | break; | |
17853 | ||
17854 | case 0: | |
17855 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17856 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17857 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17858 | insn ^= 0x00010000; |
17859 | break; | |
b34976b6 | 17860 | |
4a6a3df4 AO |
17861 | case 1: |
17862 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17863 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17864 | insn ^= 0x04000000; |
17865 | break; | |
17866 | ||
17867 | default: | |
17868 | abort (); | |
17869 | } | |
17870 | } | |
17871 | ||
17872 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17873 | { | |
17874 | /* Clear the and-link bit. */ | |
9c2799c2 | 17875 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17876 | |
54f4ddb3 TS |
17877 | /* bltzal 0x04100000 bgezal 0x04110000 |
17878 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17879 | insn &= ~0x00100000; |
17880 | } | |
17881 | ||
17882 | /* Branch over the branch (if the branch was likely) or the | |
17883 | full jump (not likely case). Compute the offset from the | |
17884 | current instruction to branch to. */ | |
17885 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17886 | i = 16; | |
17887 | else | |
17888 | { | |
17889 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17890 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17891 | /* How many bytes in instructions from here to the end? */ |
17892 | i = fragp->fr_var - i; | |
17893 | } | |
17894 | /* Convert to instruction count. */ | |
17895 | i >>= 2; | |
17896 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17897 | i--; |
4a6a3df4 AO |
17898 | insn |= i; |
17899 | /* Branch over the jump. */ | |
4d68580a | 17900 | buf = write_insn (buf, insn); |
4a6a3df4 | 17901 | |
54f4ddb3 | 17902 | /* nop */ |
4d68580a | 17903 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
17904 | |
17905 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17906 | { | |
17907 | /* beql $0, $0, 2f */ | |
17908 | insn = 0x50000000; | |
17909 | /* Compute the PC offset from the current instruction to | |
17910 | the end of the variable frag. */ | |
17911 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 17912 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
17913 | /* How many bytes in instructions from here to the end? */ |
17914 | i = fragp->fr_var - i; | |
17915 | /* Convert to instruction count. */ | |
17916 | i >>= 2; | |
17917 | /* Don't decrement i, because we want to branch over the | |
17918 | delay slot. */ | |
4a6a3df4 | 17919 | insn |= i; |
4a6a3df4 | 17920 | |
4d68580a RS |
17921 | buf = write_insn (buf, insn); |
17922 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
17923 | } |
17924 | ||
17925 | uncond: | |
17926 | if (mips_pic == NO_PIC) | |
17927 | { | |
17928 | /* j or jal. */ | |
17929 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17930 | ? 0x0c000000 : 0x08000000); | |
17931 | exp.X_op = O_symbol; | |
17932 | exp.X_add_symbol = fragp->fr_symbol; | |
17933 | exp.X_add_number = fragp->fr_offset; | |
17934 | ||
4d68580a RS |
17935 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17936 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
17937 | fixp->fx_file = fragp->fr_file; |
17938 | fixp->fx_line = fragp->fr_line; | |
17939 | ||
4d68580a | 17940 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17941 | } |
17942 | else | |
17943 | { | |
66b3e8da MR |
17944 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17945 | ||
4a6a3df4 | 17946 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17947 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17948 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17949 | exp.X_op = O_symbol; |
17950 | exp.X_add_symbol = fragp->fr_symbol; | |
17951 | exp.X_add_number = fragp->fr_offset; | |
17952 | ||
17953 | if (fragp->fr_offset) | |
17954 | { | |
17955 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17956 | exp.X_add_number = 0; | |
17957 | } | |
17958 | ||
4d68580a RS |
17959 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17960 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
17961 | fixp->fx_file = fragp->fr_file; |
17962 | fixp->fx_line = fragp->fr_line; | |
17963 | ||
4d68580a | 17964 | buf = write_insn (buf, insn); |
b34976b6 | 17965 | |
4a6a3df4 | 17966 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
17967 | /* nop */ |
17968 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
17969 | |
17970 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17971 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17972 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 17973 | |
4d68580a RS |
17974 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
17975 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
17976 | fixp->fx_file = fragp->fr_file; |
17977 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17978 | |
4d68580a | 17979 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17980 | |
17981 | /* j(al)r $at. */ | |
17982 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17983 | insn = 0x0000f809; |
4a6a3df4 | 17984 | else |
66b3e8da MR |
17985 | insn = 0x00000008; |
17986 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17987 | |
4d68580a | 17988 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
17989 | } |
17990 | } | |
17991 | ||
4a6a3df4 | 17992 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 17993 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
17994 | return; |
17995 | } | |
17996 | ||
df58fc94 RS |
17997 | /* Relax microMIPS branches. */ |
17998 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17999 | { | |
4d68580a | 18000 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18001 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18002 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18003 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18004 | bfd_boolean short_ds; |
df58fc94 RS |
18005 | unsigned long insn; |
18006 | expressionS exp; | |
18007 | fixS *fixp; | |
18008 | ||
18009 | exp.X_op = O_symbol; | |
18010 | exp.X_add_symbol = fragp->fr_symbol; | |
18011 | exp.X_add_number = fragp->fr_offset; | |
18012 | ||
18013 | fragp->fr_fix += fragp->fr_var; | |
18014 | ||
18015 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18016 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18017 | { | |
18018 | /* We generate a fixup instead of applying it right now, | |
18019 | because if there is linker relaxation, we're going to | |
18020 | need the relocations. */ | |
18021 | if (type == 'D') | |
4d68580a | 18022 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18023 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18024 | else if (type == 'E') | |
4d68580a | 18025 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18026 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18027 | else | |
18028 | abort (); | |
18029 | ||
18030 | fixp->fx_file = fragp->fr_file; | |
18031 | fixp->fx_line = fragp->fr_line; | |
18032 | ||
18033 | /* These relocations can have an addend that won't fit in | |
18034 | 2 octets. */ | |
18035 | fixp->fx_no_overflow = 1; | |
18036 | ||
18037 | return; | |
18038 | } | |
18039 | ||
2309ddf2 | 18040 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18041 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18042 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18043 | { | |
18044 | /* We generate a fixup instead of applying it right now, | |
18045 | because if there is linker relaxation, we're going to | |
18046 | need the relocations. */ | |
4d68580a RS |
18047 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18048 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18049 | fixp->fx_file = fragp->fr_file; |
18050 | fixp->fx_line = fragp->fr_line; | |
18051 | ||
18052 | if (type == 0) | |
18053 | return; | |
18054 | } | |
18055 | ||
18056 | /* Relax 16-bit branches to 32-bit branches. */ | |
18057 | if (type != 0) | |
18058 | { | |
4d68580a | 18059 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18060 | |
18061 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18062 | insn = 0x94000000; /* beq */ | |
18063 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18064 | { | |
18065 | unsigned long regno; | |
18066 | ||
18067 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18068 | regno = micromips_to_32_reg_d_map [regno]; | |
18069 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18070 | insn |= regno << MICROMIPSOP_SH_RS; | |
18071 | } | |
18072 | else | |
18073 | abort (); | |
18074 | ||
18075 | /* Nothing else to do, just write it out. */ | |
18076 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18077 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18078 | { | |
4d68580a RS |
18079 | buf = write_compressed_insn (buf, insn, 4); |
18080 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18081 | return; |
18082 | } | |
18083 | } | |
18084 | else | |
4d68580a | 18085 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18086 | |
18087 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18088 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18089 | _("Relaxed out-of-range branch into a jump")); | |
18090 | ||
2309ddf2 MR |
18091 | /* Set the short-delay-slot bit. */ |
18092 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18093 | |
18094 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18095 | { | |
18096 | symbolS *l; | |
18097 | ||
18098 | /* Reverse the branch. */ | |
18099 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18100 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18101 | insn ^= 0x20000000; | |
18102 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18103 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18104 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18105 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18106 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18107 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18108 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18109 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18110 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18111 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18112 | insn ^= 0x00400000; | |
18113 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18114 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18115 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18116 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18117 | insn ^= 0x00200000; | |
18118 | else | |
18119 | abort (); | |
18120 | ||
18121 | if (al) | |
18122 | { | |
18123 | /* Clear the and-link and short-delay-slot bits. */ | |
18124 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18125 | ||
18126 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18127 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18128 | insn &= ~0x02200000; | |
18129 | } | |
18130 | ||
18131 | /* Make a label at the end for use with the branch. */ | |
18132 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18133 | micromips_label_inc (); | |
18134 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18135 | if (IS_ELF) | |
18136 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18137 | #endif | |
18138 | ||
18139 | /* Refer to it. */ | |
4d68580a RS |
18140 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18141 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18142 | fixp->fx_file = fragp->fr_file; |
18143 | fixp->fx_line = fragp->fr_line; | |
18144 | ||
18145 | /* Branch over the jump. */ | |
4d68580a | 18146 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18147 | if (!compact) |
4d68580a RS |
18148 | /* nop */ |
18149 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18150 | } |
18151 | ||
18152 | if (mips_pic == NO_PIC) | |
18153 | { | |
2309ddf2 MR |
18154 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18155 | ||
df58fc94 RS |
18156 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18157 | insn = al ? jal : 0xd4000000; | |
18158 | ||
4d68580a RS |
18159 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18160 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18161 | fixp->fx_file = fragp->fr_file; |
18162 | fixp->fx_line = fragp->fr_line; | |
18163 | ||
4d68580a | 18164 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18165 | if (compact) |
4d68580a RS |
18166 | /* nop */ |
18167 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18168 | } |
18169 | else | |
18170 | { | |
18171 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18172 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18173 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18174 | |
18175 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18176 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18177 | insn |= at << MICROMIPSOP_SH_RT; | |
18178 | ||
18179 | if (exp.X_add_number) | |
18180 | { | |
18181 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18182 | exp.X_add_number = 0; | |
18183 | } | |
18184 | ||
4d68580a RS |
18185 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18186 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18187 | fixp->fx_file = fragp->fr_file; |
18188 | fixp->fx_line = fragp->fr_line; | |
18189 | ||
4d68580a | 18190 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18191 | |
18192 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18193 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18194 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18195 | ||
4d68580a RS |
18196 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18197 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18198 | fixp->fx_file = fragp->fr_file; |
18199 | fixp->fx_line = fragp->fr_line; | |
18200 | ||
4d68580a | 18201 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18202 | |
18203 | /* jr/jrc/jalr/jalrs $at */ | |
18204 | insn = al ? jalr : jr; | |
18205 | insn |= at << MICROMIPSOP_SH_MJ; | |
18206 | ||
4d68580a | 18207 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18208 | } |
18209 | ||
4d68580a | 18210 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18211 | return; |
18212 | } | |
18213 | ||
252b5132 RH |
18214 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18215 | { | |
18216 | int type; | |
3994f87e | 18217 | const struct mips16_immed_operand *op; |
252b5132 | 18218 | offsetT val; |
5c04167a RS |
18219 | char *buf; |
18220 | unsigned int user_length, length; | |
252b5132 | 18221 | unsigned long insn; |
5c04167a | 18222 | bfd_boolean ext; |
252b5132 RH |
18223 | |
18224 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18225 | op = mips16_immed_operands; | |
18226 | while (op->type != type) | |
18227 | ++op; | |
18228 | ||
5c04167a | 18229 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18230 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18231 | if (op->pcrel) |
18232 | { | |
18233 | addressT addr; | |
18234 | ||
18235 | addr = fragp->fr_address + fragp->fr_fix; | |
18236 | ||
18237 | /* The rules for the base address of a PC relative reloc are | |
18238 | complicated; see mips16_extended_frag. */ | |
18239 | if (type == 'p' || type == 'q') | |
18240 | { | |
18241 | addr += 2; | |
18242 | if (ext) | |
18243 | addr += 2; | |
18244 | /* Ignore the low bit in the target, since it will be | |
18245 | set for a text label. */ | |
18246 | if ((val & 1) != 0) | |
18247 | --val; | |
18248 | } | |
18249 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18250 | addr -= 4; | |
18251 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18252 | addr -= 2; | |
18253 | ||
18254 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18255 | val -= addr; | |
18256 | ||
18257 | /* Make sure the section winds up with the alignment we have | |
18258 | assumed. */ | |
18259 | if (op->shift > 0) | |
18260 | record_alignment (asec, op->shift); | |
18261 | } | |
18262 | ||
18263 | if (ext | |
18264 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18265 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18266 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18267 | _("extended instruction in delay slot")); | |
18268 | ||
5c04167a | 18269 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18270 | |
4d68580a | 18271 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18272 | if (ext) |
18273 | insn |= MIPS16_EXTEND; | |
252b5132 | 18274 | |
5c04167a RS |
18275 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18276 | user_length = 4; | |
18277 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18278 | user_length = 2; | |
18279 | else | |
18280 | user_length = 0; | |
18281 | ||
43c0598f | 18282 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18283 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18284 | |
5c04167a RS |
18285 | length = (ext ? 4 : 2); |
18286 | gas_assert (mips16_opcode_length (insn) == length); | |
18287 | write_compressed_insn (buf, insn, length); | |
18288 | fragp->fr_fix += length; | |
252b5132 RH |
18289 | } |
18290 | else | |
18291 | { | |
df58fc94 RS |
18292 | relax_substateT subtype = fragp->fr_subtype; |
18293 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18294 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18295 | int first, second; |
18296 | fixS *fixp; | |
252b5132 | 18297 | |
df58fc94 RS |
18298 | first = RELAX_FIRST (subtype); |
18299 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18300 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18301 | |
df58fc94 RS |
18302 | /* If the delay slot chosen does not match the size of the instruction, |
18303 | then emit a warning. */ | |
18304 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18305 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18306 | { | |
18307 | relax_substateT s; | |
18308 | const char *msg; | |
18309 | ||
18310 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18311 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18312 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18313 | msg = macro_warning (s); | |
18314 | if (msg != NULL) | |
db9b2be4 | 18315 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18316 | subtype &= ~s; |
18317 | } | |
18318 | ||
584892a6 | 18319 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18320 | if (use_second == second_longer) |
584892a6 | 18321 | { |
df58fc94 RS |
18322 | relax_substateT s; |
18323 | const char *msg; | |
18324 | ||
18325 | s = (subtype | |
18326 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18327 | msg = macro_warning (s); | |
18328 | if (msg != NULL) | |
db9b2be4 | 18329 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18330 | subtype &= ~s; |
584892a6 RS |
18331 | } |
18332 | ||
4d7206a2 RS |
18333 | /* Go through all the fixups for the first sequence. Disable them |
18334 | (by marking them as done) if we're going to use the second | |
18335 | sequence instead. */ | |
18336 | while (fixp | |
18337 | && fixp->fx_frag == fragp | |
18338 | && fixp->fx_where < fragp->fr_fix - second) | |
18339 | { | |
df58fc94 | 18340 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18341 | fixp->fx_done = 1; |
18342 | fixp = fixp->fx_next; | |
18343 | } | |
252b5132 | 18344 | |
4d7206a2 RS |
18345 | /* Go through the fixups for the second sequence. Disable them if |
18346 | we're going to use the first sequence, otherwise adjust their | |
18347 | addresses to account for the relaxation. */ | |
18348 | while (fixp && fixp->fx_frag == fragp) | |
18349 | { | |
df58fc94 | 18350 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18351 | fixp->fx_where -= first; |
18352 | else | |
18353 | fixp->fx_done = 1; | |
18354 | fixp = fixp->fx_next; | |
18355 | } | |
18356 | ||
18357 | /* Now modify the frag contents. */ | |
df58fc94 | 18358 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18359 | { |
18360 | char *start; | |
18361 | ||
18362 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18363 | memmove (start, start + first, second); | |
18364 | fragp->fr_fix -= first; | |
18365 | } | |
18366 | else | |
18367 | fragp->fr_fix -= second; | |
252b5132 RH |
18368 | } |
18369 | } | |
18370 | ||
18371 | #ifdef OBJ_ELF | |
18372 | ||
18373 | /* This function is called after the relocs have been generated. | |
18374 | We've been storing mips16 text labels as odd. Here we convert them | |
18375 | back to even for the convenience of the debugger. */ | |
18376 | ||
18377 | void | |
17a2f251 | 18378 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18379 | { |
18380 | asymbol **syms; | |
18381 | unsigned int count, i; | |
18382 | ||
f43abd2b | 18383 | if (!IS_ELF) |
252b5132 RH |
18384 | return; |
18385 | ||
18386 | syms = bfd_get_outsymbols (stdoutput); | |
18387 | count = bfd_get_symcount (stdoutput); | |
18388 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18389 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18390 | && ((*syms)->value & 1) != 0) | |
18391 | { | |
18392 | (*syms)->value &= ~1; | |
18393 | /* If the symbol has an odd size, it was probably computed | |
18394 | incorrectly, so adjust that as well. */ | |
18395 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18396 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18397 | } | |
252b5132 RH |
18398 | } |
18399 | ||
18400 | #endif | |
18401 | ||
a1facbec MR |
18402 | /* This function is called whenever a label is defined, including fake |
18403 | labels instantiated off the dot special symbol. It is used when | |
18404 | handling branch delays; if a branch has a label, we assume we cannot | |
18405 | move it. This also bumps the value of the symbol by 1 in compressed | |
18406 | code. */ | |
252b5132 RH |
18407 | |
18408 | void | |
a1facbec | 18409 | mips_record_label (symbolS *sym) |
252b5132 | 18410 | { |
a8dbcb85 | 18411 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18412 | struct insn_label_list *l; |
18413 | ||
18414 | if (free_insn_labels == NULL) | |
18415 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18416 | else | |
18417 | { | |
18418 | l = free_insn_labels; | |
18419 | free_insn_labels = l->next; | |
18420 | } | |
18421 | ||
18422 | l->label = sym; | |
a8dbcb85 TS |
18423 | l->next = si->label_list; |
18424 | si->label_list = l; | |
a1facbec | 18425 | } |
07a53e5c | 18426 | |
a1facbec MR |
18427 | /* This function is called as tc_frob_label() whenever a label is defined |
18428 | and adds a DWARF-2 record we only want for true labels. */ | |
18429 | ||
18430 | void | |
18431 | mips_define_label (symbolS *sym) | |
18432 | { | |
18433 | mips_record_label (sym); | |
07a53e5c RH |
18434 | #ifdef OBJ_ELF |
18435 | dwarf2_emit_label (sym); | |
18436 | #endif | |
252b5132 RH |
18437 | } |
18438 | \f | |
18439 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18440 | ||
18441 | /* Some special processing for a MIPS ELF file. */ | |
18442 | ||
18443 | void | |
17a2f251 | 18444 | mips_elf_final_processing (void) |
252b5132 RH |
18445 | { |
18446 | /* Write out the register information. */ | |
316f5878 | 18447 | if (mips_abi != N64_ABI) |
252b5132 RH |
18448 | { |
18449 | Elf32_RegInfo s; | |
18450 | ||
18451 | s.ri_gprmask = mips_gprmask; | |
18452 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18453 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18454 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18455 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18456 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18457 | ||
18458 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18459 | ((Elf32_External_RegInfo *) | |
18460 | mips_regmask_frag)); | |
18461 | } | |
18462 | else | |
18463 | { | |
18464 | Elf64_Internal_RegInfo s; | |
18465 | ||
18466 | s.ri_gprmask = mips_gprmask; | |
18467 | s.ri_pad = 0; | |
18468 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18469 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18470 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18471 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18472 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18473 | ||
18474 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18475 | ((Elf64_External_RegInfo *) | |
18476 | mips_regmask_frag)); | |
18477 | } | |
18478 | ||
18479 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18480 | sort of BFD interface for this. */ | |
18481 | if (mips_any_noreorder) | |
18482 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18483 | if (mips_pic != NO_PIC) | |
143d77c5 | 18484 | { |
8b828383 | 18485 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18486 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18487 | } | |
18488 | if (mips_abicalls) | |
18489 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18490 | |
98d3f06f | 18491 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18492 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18493 | file_ase_dsp is true. */ | |
8b082fb1 | 18494 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18495 | /* We may need to define a new flag for MT ASE, and set this flag when |
18496 | file_ase_mt is true. */ | |
a4672219 TS |
18497 | if (file_ase_mips16) |
18498 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18499 | if (file_ase_micromips) |
18500 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18501 | #if 0 /* XXX FIXME */ |
18502 | if (file_ase_mips3d) | |
18503 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18504 | #endif | |
deec1734 CD |
18505 | if (file_ase_mdmx) |
18506 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18507 | |
bdaaa2e1 | 18508 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18509 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18510 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18511 | else if (mips_abi == O64_ABI) |
252b5132 | 18512 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18513 | else if (mips_abi == EABI_ABI) |
252b5132 | 18514 | { |
316f5878 | 18515 | if (!file_mips_gp32) |
252b5132 RH |
18516 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18517 | else | |
18518 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18519 | } | |
316f5878 | 18520 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18521 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18522 | ||
c9914766 | 18523 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18524 | |
18525 | if (mips_32bitmode) | |
18526 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18527 | |
18528 | #if 0 /* XXX FIXME */ | |
18529 | /* 32 bit code with 64 bit FP registers. */ | |
18530 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18531 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18532 | #endif | |
252b5132 RH |
18533 | } |
18534 | ||
18535 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18536 | \f | |
beae10d5 | 18537 | typedef struct proc { |
9b2f1d35 EC |
18538 | symbolS *func_sym; |
18539 | symbolS *func_end_sym; | |
beae10d5 KH |
18540 | unsigned long reg_mask; |
18541 | unsigned long reg_offset; | |
18542 | unsigned long fpreg_mask; | |
18543 | unsigned long fpreg_offset; | |
18544 | unsigned long frame_offset; | |
18545 | unsigned long frame_reg; | |
18546 | unsigned long pc_reg; | |
18547 | } procS; | |
252b5132 RH |
18548 | |
18549 | static procS cur_proc; | |
18550 | static procS *cur_proc_ptr; | |
18551 | static int numprocs; | |
18552 | ||
df58fc94 RS |
18553 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18554 | as "2", and a normal nop as "0". */ | |
18555 | ||
18556 | #define NOP_OPCODE_MIPS 0 | |
18557 | #define NOP_OPCODE_MIPS16 1 | |
18558 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18559 | |
18560 | char | |
18561 | mips_nop_opcode (void) | |
18562 | { | |
df58fc94 RS |
18563 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18564 | return NOP_OPCODE_MICROMIPS; | |
18565 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18566 | return NOP_OPCODE_MIPS16; | |
18567 | else | |
18568 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18569 | } |
18570 | ||
df58fc94 RS |
18571 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18572 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18573 | |
0a9ef439 | 18574 | void |
17a2f251 | 18575 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18576 | { |
df58fc94 | 18577 | char nop_opcode; |
742a56fe | 18578 | char *p; |
c67a084a NC |
18579 | int bytes, size, excess; |
18580 | valueT opcode; | |
742a56fe | 18581 | |
0a9ef439 RH |
18582 | if (fragp->fr_type != rs_align_code) |
18583 | return; | |
18584 | ||
742a56fe | 18585 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18586 | nop_opcode = *p; |
18587 | switch (nop_opcode) | |
a19d8eb0 | 18588 | { |
df58fc94 RS |
18589 | case NOP_OPCODE_MICROMIPS: |
18590 | opcode = micromips_nop32_insn.insn_opcode; | |
18591 | size = 4; | |
18592 | break; | |
18593 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18594 | opcode = mips16_nop_insn.insn_opcode; |
18595 | size = 2; | |
df58fc94 RS |
18596 | break; |
18597 | case NOP_OPCODE_MIPS: | |
18598 | default: | |
c67a084a NC |
18599 | opcode = nop_insn.insn_opcode; |
18600 | size = 4; | |
df58fc94 | 18601 | break; |
c67a084a | 18602 | } |
a19d8eb0 | 18603 | |
c67a084a NC |
18604 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18605 | excess = bytes % size; | |
df58fc94 RS |
18606 | |
18607 | /* Handle the leading part if we're not inserting a whole number of | |
18608 | instructions, and make it the end of the fixed part of the frag. | |
18609 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18610 | and use zeroes otherwise. */ | |
18611 | gas_assert (excess < 4); | |
18612 | fragp->fr_fix += excess; | |
18613 | switch (excess) | |
c67a084a | 18614 | { |
df58fc94 RS |
18615 | case 3: |
18616 | *p++ = '\0'; | |
18617 | /* Fall through. */ | |
18618 | case 2: | |
18619 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18620 | { | |
4d68580a | 18621 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18622 | break; |
18623 | } | |
18624 | *p++ = '\0'; | |
18625 | /* Fall through. */ | |
18626 | case 1: | |
18627 | *p++ = '\0'; | |
18628 | /* Fall through. */ | |
18629 | case 0: | |
18630 | break; | |
a19d8eb0 | 18631 | } |
c67a084a NC |
18632 | |
18633 | md_number_to_chars (p, opcode, size); | |
18634 | fragp->fr_var = size; | |
a19d8eb0 CP |
18635 | } |
18636 | ||
252b5132 | 18637 | static void |
17a2f251 | 18638 | md_obj_begin (void) |
252b5132 RH |
18639 | { |
18640 | } | |
18641 | ||
18642 | static void | |
17a2f251 | 18643 | md_obj_end (void) |
252b5132 | 18644 | { |
54f4ddb3 | 18645 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18646 | if (cur_proc_ptr) |
9a41af64 | 18647 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18648 | } |
18649 | ||
18650 | static long | |
17a2f251 | 18651 | get_number (void) |
252b5132 RH |
18652 | { |
18653 | int negative = 0; | |
18654 | long val = 0; | |
18655 | ||
18656 | if (*input_line_pointer == '-') | |
18657 | { | |
18658 | ++input_line_pointer; | |
18659 | negative = 1; | |
18660 | } | |
3882b010 | 18661 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18662 | as_bad (_("expected simple number")); |
252b5132 RH |
18663 | if (input_line_pointer[0] == '0') |
18664 | { | |
18665 | if (input_line_pointer[1] == 'x') | |
18666 | { | |
18667 | input_line_pointer += 2; | |
3882b010 | 18668 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18669 | { |
18670 | val <<= 4; | |
18671 | val |= hex_value (*input_line_pointer++); | |
18672 | } | |
18673 | return negative ? -val : val; | |
18674 | } | |
18675 | else | |
18676 | { | |
18677 | ++input_line_pointer; | |
3882b010 | 18678 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18679 | { |
18680 | val <<= 3; | |
18681 | val |= *input_line_pointer++ - '0'; | |
18682 | } | |
18683 | return negative ? -val : val; | |
18684 | } | |
18685 | } | |
3882b010 | 18686 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18687 | { |
18688 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18689 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18690 | as_warn (_("invalid number")); |
252b5132 RH |
18691 | return -1; |
18692 | } | |
3882b010 | 18693 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18694 | { |
18695 | val *= 10; | |
18696 | val += *input_line_pointer++ - '0'; | |
18697 | } | |
18698 | return negative ? -val : val; | |
18699 | } | |
18700 | ||
18701 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18702 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18703 | case .file implies DWARF-2. */ | |
18704 | ||
18705 | static void | |
17a2f251 | 18706 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18707 | { |
ecb4347a DJ |
18708 | static int first_file_directive = 0; |
18709 | ||
c5dd6aab DJ |
18710 | if (ECOFF_DEBUGGING) |
18711 | { | |
18712 | get_number (); | |
18713 | s_app_file (0); | |
18714 | } | |
18715 | else | |
ecb4347a DJ |
18716 | { |
18717 | char *filename; | |
18718 | ||
18719 | filename = dwarf2_directive_file (0); | |
18720 | ||
18721 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18722 | directive even for stabs output. Make sure that this | |
18723 | ".file" is handled. Note that you need a version of GCC | |
18724 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18725 | if (filename != NULL && ! first_file_directive) | |
18726 | { | |
18727 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18728 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18729 | } |
18730 | first_file_directive = 1; | |
18731 | } | |
c5dd6aab DJ |
18732 | } |
18733 | ||
18734 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18735 | |
18736 | static void | |
17a2f251 | 18737 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18738 | { |
c5dd6aab DJ |
18739 | if (!ECOFF_DEBUGGING) |
18740 | dwarf2_directive_loc (0); | |
252b5132 RH |
18741 | } |
18742 | ||
252b5132 RH |
18743 | /* The .end directive. */ |
18744 | ||
18745 | static void | |
17a2f251 | 18746 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18747 | { |
18748 | symbolS *p; | |
252b5132 | 18749 | |
7a621144 DJ |
18750 | /* Following functions need their own .frame and .cprestore directives. */ |
18751 | mips_frame_reg_valid = 0; | |
18752 | mips_cprestore_valid = 0; | |
18753 | ||
252b5132 RH |
18754 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18755 | { | |
18756 | p = get_symbol (); | |
18757 | demand_empty_rest_of_line (); | |
18758 | } | |
18759 | else | |
18760 | p = NULL; | |
18761 | ||
14949570 | 18762 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18763 | as_warn (_(".end not in text section")); |
18764 | ||
18765 | if (!cur_proc_ptr) | |
18766 | { | |
18767 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18768 | demand_empty_rest_of_line (); | |
18769 | return; | |
18770 | } | |
18771 | ||
18772 | if (p != NULL) | |
18773 | { | |
9c2799c2 | 18774 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18775 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18776 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18777 | |
18778 | if (debug_type == DEBUG_STABS) | |
18779 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18780 | S_GET_NAME (p)); | |
252b5132 RH |
18781 | } |
18782 | else | |
18783 | as_warn (_(".end directive missing or unknown symbol")); | |
18784 | ||
2132e3a3 | 18785 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18786 | /* Create an expression to calculate the size of the function. */ |
18787 | if (p && cur_proc_ptr) | |
18788 | { | |
18789 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18790 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18791 | ||
18792 | obj->size = exp; | |
18793 | exp->X_op = O_subtract; | |
18794 | exp->X_add_symbol = symbol_temp_new_now (); | |
18795 | exp->X_op_symbol = p; | |
18796 | exp->X_add_number = 0; | |
18797 | ||
18798 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18799 | } | |
18800 | ||
ecb4347a | 18801 | /* Generate a .pdr section. */ |
f43abd2b | 18802 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18803 | { |
18804 | segT saved_seg = now_seg; | |
18805 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18806 | expressionS exp; |
18807 | char *fragp; | |
252b5132 | 18808 | |
252b5132 | 18809 | #ifdef md_flush_pending_output |
ecb4347a | 18810 | md_flush_pending_output (); |
252b5132 RH |
18811 | #endif |
18812 | ||
9c2799c2 | 18813 | gas_assert (pdr_seg); |
ecb4347a | 18814 | subseg_set (pdr_seg, 0); |
252b5132 | 18815 | |
ecb4347a DJ |
18816 | /* Write the symbol. */ |
18817 | exp.X_op = O_symbol; | |
18818 | exp.X_add_symbol = p; | |
18819 | exp.X_add_number = 0; | |
18820 | emit_expr (&exp, 4); | |
252b5132 | 18821 | |
ecb4347a | 18822 | fragp = frag_more (7 * 4); |
252b5132 | 18823 | |
17a2f251 TS |
18824 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18825 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18826 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18827 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18828 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18829 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18830 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18831 | |
ecb4347a DJ |
18832 | subseg_set (saved_seg, saved_subseg); |
18833 | } | |
18834 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18835 | |
18836 | cur_proc_ptr = NULL; | |
18837 | } | |
18838 | ||
18839 | /* The .aent and .ent directives. */ | |
18840 | ||
18841 | static void | |
17a2f251 | 18842 | s_mips_ent (int aent) |
252b5132 | 18843 | { |
252b5132 | 18844 | symbolS *symbolP; |
252b5132 RH |
18845 | |
18846 | symbolP = get_symbol (); | |
18847 | if (*input_line_pointer == ',') | |
f9419b05 | 18848 | ++input_line_pointer; |
252b5132 | 18849 | SKIP_WHITESPACE (); |
3882b010 | 18850 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18851 | || *input_line_pointer == '-') |
874e8986 | 18852 | get_number (); |
252b5132 | 18853 | |
14949570 | 18854 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18855 | as_warn (_(".ent or .aent not in text section.")); |
18856 | ||
18857 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18858 | as_warn (_("missing .end")); |
252b5132 RH |
18859 | |
18860 | if (!aent) | |
18861 | { | |
7a621144 DJ |
18862 | /* This function needs its own .frame and .cprestore directives. */ |
18863 | mips_frame_reg_valid = 0; | |
18864 | mips_cprestore_valid = 0; | |
18865 | ||
252b5132 RH |
18866 | cur_proc_ptr = &cur_proc; |
18867 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18868 | ||
9b2f1d35 | 18869 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18870 | |
f9419b05 | 18871 | ++numprocs; |
ecb4347a DJ |
18872 | |
18873 | if (debug_type == DEBUG_STABS) | |
18874 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18875 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18876 | } |
18877 | ||
7c0fc524 MR |
18878 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18879 | ||
252b5132 RH |
18880 | demand_empty_rest_of_line (); |
18881 | } | |
18882 | ||
18883 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18884 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18885 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18886 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18887 | symbol table (in the mdebug section). */ |
18888 | ||
18889 | static void | |
17a2f251 | 18890 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18891 | { |
ecb4347a | 18892 | #ifdef OBJ_ELF |
f43abd2b | 18893 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18894 | { |
18895 | long val; | |
252b5132 | 18896 | |
ecb4347a DJ |
18897 | if (cur_proc_ptr == (procS *) NULL) |
18898 | { | |
18899 | as_warn (_(".frame outside of .ent")); | |
18900 | demand_empty_rest_of_line (); | |
18901 | return; | |
18902 | } | |
252b5132 | 18903 | |
ecb4347a DJ |
18904 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18905 | ||
18906 | SKIP_WHITESPACE (); | |
18907 | if (*input_line_pointer++ != ',' | |
18908 | || get_absolute_expression_and_terminator (&val) != ',') | |
18909 | { | |
18910 | as_warn (_("Bad .frame directive")); | |
18911 | --input_line_pointer; | |
18912 | demand_empty_rest_of_line (); | |
18913 | return; | |
18914 | } | |
252b5132 | 18915 | |
ecb4347a DJ |
18916 | cur_proc_ptr->frame_offset = val; |
18917 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18918 | |
252b5132 | 18919 | demand_empty_rest_of_line (); |
252b5132 | 18920 | } |
ecb4347a DJ |
18921 | else |
18922 | #endif /* OBJ_ELF */ | |
18923 | s_ignore (ignore); | |
252b5132 RH |
18924 | } |
18925 | ||
bdaaa2e1 KH |
18926 | /* The .fmask and .mask directives. If the mdebug section is present |
18927 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18928 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18929 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18930 | make reference to the ecoff symbol table (in the mdebug section). */ |
18931 | ||
18932 | static void | |
17a2f251 | 18933 | s_mips_mask (int reg_type) |
252b5132 | 18934 | { |
ecb4347a | 18935 | #ifdef OBJ_ELF |
f43abd2b | 18936 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18937 | { |
ecb4347a | 18938 | long mask, off; |
252b5132 | 18939 | |
ecb4347a DJ |
18940 | if (cur_proc_ptr == (procS *) NULL) |
18941 | { | |
18942 | as_warn (_(".mask/.fmask outside of .ent")); | |
18943 | demand_empty_rest_of_line (); | |
18944 | return; | |
18945 | } | |
252b5132 | 18946 | |
ecb4347a DJ |
18947 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18948 | { | |
18949 | as_warn (_("Bad .mask/.fmask directive")); | |
18950 | --input_line_pointer; | |
18951 | demand_empty_rest_of_line (); | |
18952 | return; | |
18953 | } | |
252b5132 | 18954 | |
ecb4347a DJ |
18955 | off = get_absolute_expression (); |
18956 | ||
18957 | if (reg_type == 'F') | |
18958 | { | |
18959 | cur_proc_ptr->fpreg_mask = mask; | |
18960 | cur_proc_ptr->fpreg_offset = off; | |
18961 | } | |
18962 | else | |
18963 | { | |
18964 | cur_proc_ptr->reg_mask = mask; | |
18965 | cur_proc_ptr->reg_offset = off; | |
18966 | } | |
18967 | ||
18968 | demand_empty_rest_of_line (); | |
252b5132 RH |
18969 | } |
18970 | else | |
ecb4347a DJ |
18971 | #endif /* OBJ_ELF */ |
18972 | s_ignore (reg_type); | |
252b5132 RH |
18973 | } |
18974 | ||
316f5878 RS |
18975 | /* A table describing all the processors gas knows about. Names are |
18976 | matched in the order listed. | |
e7af610e | 18977 | |
316f5878 RS |
18978 | To ease comparison, please keep this table in the same order as |
18979 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18980 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18981 | { | |
316f5878 | 18982 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18983 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18984 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18985 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18986 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18987 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18988 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18989 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18990 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18991 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18992 | |
18993 | /* MIPS I */ | |
ad3fea08 TS |
18994 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18995 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18996 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18997 | |
18998 | /* MIPS II */ | |
ad3fea08 | 18999 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19000 | |
19001 | /* MIPS III */ | |
ad3fea08 TS |
19002 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
19003 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
19004 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
19005 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
19006 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
19007 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
19008 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
19009 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
19010 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
19011 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
19012 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
19013 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
19014 | /* ST Microelectronics Loongson 2E and 2F cores */ |
19015 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
19016 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19017 | |
19018 | /* MIPS IV */ | |
ad3fea08 TS |
19019 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19020 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19021 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19022 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19023 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19024 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19025 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19026 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19027 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19028 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19029 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19030 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19031 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19032 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19033 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19034 | |
19035 | /* MIPS 32 */ | |
ad3fea08 TS |
19036 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19037 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19038 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19039 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19040 | ||
19041 | /* MIPS 32 Release 2 */ | |
19042 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19043 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19044 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19045 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19046 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19047 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19048 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19049 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19050 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19051 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19052 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19053 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19054 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19055 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19056 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19057 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19058 | /* Deprecated forms of the above. */ | |
19059 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19060 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19061 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19062 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19063 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19064 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19065 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19066 | /* Deprecated forms of the above. */ | |
19067 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19068 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19069 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19070 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19071 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19072 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19073 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19074 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19075 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19076 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19077 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19078 | /* Deprecated forms of the above. */ | |
19079 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19080 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19081 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19082 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 SL |
19083 | /* 34Kn is a 34kc without DSP. */ |
19084 | { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19085 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19086 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19087 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19088 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19089 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19090 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19091 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19092 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19093 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19094 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19095 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19096 | /* Deprecated forms of the above. */ | |
19097 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19098 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19099 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19100 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19101 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19102 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19103 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19104 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19105 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19106 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19107 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19108 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19109 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19110 | |
316f5878 | 19111 | /* MIPS 64 */ |
ad3fea08 TS |
19112 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19113 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19114 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19115 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19116 | |
c7a23324 | 19117 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19118 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19119 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19120 | /* Broadcom SB-1A CPU core */ |
19121 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19122 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19123 | |
19124 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19125 | |
ed163775 MR |
19126 | /* MIPS 64 Release 2 */ |
19127 | ||
967344c6 AN |
19128 | /* Cavium Networks Octeon CPU core */ |
19129 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19130 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19131 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19132 | |
52b6b6b9 JM |
19133 | /* RMI Xlr */ |
19134 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19135 | ||
55a36193 MK |
19136 | /* Broadcom XLP. |
19137 | XLP is mostly like XLR, with the prominent exception that it is | |
19138 | MIPS64R2 rather than MIPS64. */ | |
19139 | { "xlp", 0, ISA_MIPS64R2, CPU_XLR }, | |
19140 | ||
316f5878 RS |
19141 | /* End marker */ |
19142 | { NULL, 0, 0, 0 } | |
19143 | }; | |
e7af610e | 19144 | |
84ea6cf2 | 19145 | |
316f5878 RS |
19146 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19147 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19148 | |
316f5878 | 19149 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19150 | |
b34976b6 | 19151 | static bfd_boolean |
17a2f251 | 19152 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19153 | { |
19154 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19155 | given++, canonical++; | |
19156 | ||
19157 | return ((*given == 0 && *canonical == 0) | |
19158 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19159 | } | |
19160 | ||
19161 | ||
19162 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19163 | CPU name. We've traditionally allowed a lot of variation here. | |
19164 | ||
19165 | Note: this function is shared between GCC and GAS. */ | |
19166 | ||
b34976b6 | 19167 | static bfd_boolean |
17a2f251 | 19168 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19169 | { |
19170 | /* First see if the name matches exactly, or with a final "000" | |
19171 | turned into "k". */ | |
19172 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19173 | return TRUE; |
316f5878 RS |
19174 | |
19175 | /* If not, try comparing based on numerical designation alone. | |
19176 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19177 | if (TOLOWER (*given) == 'r') | |
19178 | given++; | |
19179 | if (!ISDIGIT (*given)) | |
b34976b6 | 19180 | return FALSE; |
316f5878 RS |
19181 | |
19182 | /* Skip over some well-known prefixes in the canonical name, | |
19183 | hoping to find a number there too. */ | |
19184 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19185 | canonical += 2; | |
19186 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19187 | canonical += 2; | |
19188 | else if (TOLOWER (canonical[0]) == 'r') | |
19189 | canonical += 1; | |
19190 | ||
19191 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19192 | } | |
19193 | ||
19194 | ||
19195 | /* Parse an option that takes the name of a processor as its argument. | |
19196 | OPTION is the name of the option and CPU_STRING is the argument. | |
19197 | Return the corresponding processor enumeration if the CPU_STRING is | |
19198 | recognized, otherwise report an error and return null. | |
19199 | ||
19200 | A similar function exists in GCC. */ | |
e7af610e NC |
19201 | |
19202 | static const struct mips_cpu_info * | |
17a2f251 | 19203 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19204 | { |
316f5878 | 19205 | const struct mips_cpu_info *p; |
e7af610e | 19206 | |
316f5878 RS |
19207 | /* 'from-abi' selects the most compatible architecture for the given |
19208 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19209 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19210 | version. Look first at the -mgp options, if given, otherwise base | |
19211 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19212 | |
316f5878 RS |
19213 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19214 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19215 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19216 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19217 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19218 | { | |
19219 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19220 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19221 | ||
19222 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19223 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19224 | ||
19225 | if (file_mips_gp32 >= 0) | |
19226 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19227 | ||
19228 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19229 | ? ISA_MIPS3 | |
19230 | : ISA_MIPS1); | |
19231 | } | |
19232 | ||
19233 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19234 | if (strcasecmp (cpu_string, "default") == 0) | |
19235 | return 0; | |
19236 | ||
19237 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19238 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19239 | return p; | |
19240 | ||
20203fb9 | 19241 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19242 | return 0; |
e7af610e NC |
19243 | } |
19244 | ||
316f5878 RS |
19245 | /* Return the canonical processor information for ISA (a member of the |
19246 | ISA_MIPS* enumeration). */ | |
19247 | ||
e7af610e | 19248 | static const struct mips_cpu_info * |
17a2f251 | 19249 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19250 | { |
19251 | int i; | |
19252 | ||
19253 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19254 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19255 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19256 | return (&mips_cpu_info_table[i]); |
19257 | ||
e972090a | 19258 | return NULL; |
e7af610e | 19259 | } |
fef14a42 TS |
19260 | |
19261 | static const struct mips_cpu_info * | |
17a2f251 | 19262 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19263 | { |
19264 | int i; | |
19265 | ||
19266 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19267 | if (arch == mips_cpu_info_table[i].cpu) | |
19268 | return (&mips_cpu_info_table[i]); | |
19269 | ||
19270 | return NULL; | |
19271 | } | |
316f5878 RS |
19272 | \f |
19273 | static void | |
17a2f251 | 19274 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19275 | { |
19276 | if (*first_p) | |
19277 | { | |
19278 | fprintf (stream, "%24s", ""); | |
19279 | *col_p = 24; | |
19280 | } | |
19281 | else | |
19282 | { | |
19283 | fprintf (stream, ", "); | |
19284 | *col_p += 2; | |
19285 | } | |
e7af610e | 19286 | |
316f5878 RS |
19287 | if (*col_p + strlen (string) > 72) |
19288 | { | |
19289 | fprintf (stream, "\n%24s", ""); | |
19290 | *col_p = 24; | |
19291 | } | |
19292 | ||
19293 | fprintf (stream, "%s", string); | |
19294 | *col_p += strlen (string); | |
19295 | ||
19296 | *first_p = 0; | |
19297 | } | |
19298 | ||
19299 | void | |
17a2f251 | 19300 | md_show_usage (FILE *stream) |
e7af610e | 19301 | { |
316f5878 RS |
19302 | int column, first; |
19303 | size_t i; | |
19304 | ||
19305 | fprintf (stream, _("\ | |
19306 | MIPS options:\n\ | |
316f5878 RS |
19307 | -EB generate big endian output\n\ |
19308 | -EL generate little endian output\n\ | |
19309 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19310 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19311 | implicitly with the gp register [default 8]\n")); | |
19312 | fprintf (stream, _("\ | |
19313 | -mips1 generate MIPS ISA I instructions\n\ | |
19314 | -mips2 generate MIPS ISA II instructions\n\ | |
19315 | -mips3 generate MIPS ISA III instructions\n\ | |
19316 | -mips4 generate MIPS ISA IV instructions\n\ | |
19317 | -mips5 generate MIPS ISA V instructions\n\ | |
19318 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19319 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19320 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19321 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19322 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19323 | ||
19324 | first = 1; | |
e7af610e NC |
19325 | |
19326 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19327 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19328 | show (stream, "from-abi", &column, &first); | |
19329 | fputc ('\n', stream); | |
e7af610e | 19330 | |
316f5878 RS |
19331 | fprintf (stream, _("\ |
19332 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19333 | -no-mCPU don't generate code specific to CPU.\n\ | |
19334 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19335 | ||
19336 | first = 1; | |
19337 | ||
19338 | show (stream, "3900", &column, &first); | |
19339 | show (stream, "4010", &column, &first); | |
19340 | show (stream, "4100", &column, &first); | |
19341 | show (stream, "4650", &column, &first); | |
19342 | fputc ('\n', stream); | |
19343 | ||
19344 | fprintf (stream, _("\ | |
19345 | -mips16 generate mips16 instructions\n\ | |
19346 | -no-mips16 do not generate mips16 instructions\n")); | |
19347 | fprintf (stream, _("\ | |
df58fc94 RS |
19348 | -mmicromips generate microMIPS instructions\n\ |
19349 | -mno-micromips do not generate microMIPS instructions\n")); | |
19350 | fprintf (stream, _("\ | |
e16bfa71 TS |
19351 | -msmartmips generate smartmips instructions\n\ |
19352 | -mno-smartmips do not generate smartmips instructions\n")); | |
19353 | fprintf (stream, _("\ | |
74cd071d CF |
19354 | -mdsp generate DSP instructions\n\ |
19355 | -mno-dsp do not generate DSP instructions\n")); | |
19356 | fprintf (stream, _("\ | |
8b082fb1 TS |
19357 | -mdspr2 generate DSP R2 instructions\n\ |
19358 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19359 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19360 | -mmt generate MT instructions\n\ |
19361 | -mno-mt do not generate MT instructions\n")); | |
19362 | fprintf (stream, _("\ | |
dec0624d MR |
19363 | -mmcu generate MCU instructions\n\ |
19364 | -mno-mcu do not generate MCU instructions\n")); | |
19365 | fprintf (stream, _("\ | |
c67a084a NC |
19366 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19367 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19368 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19369 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19370 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19371 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19372 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19373 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19374 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19375 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19376 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19377 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19378 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19379 | fprintf (stream, _("\ |
19380 | -mhard-float allow floating-point instructions\n\ | |
19381 | -msoft-float do not allow floating-point instructions\n\ | |
19382 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19383 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19384 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19385 | )); | |
316f5878 RS |
19386 | #ifdef OBJ_ELF |
19387 | fprintf (stream, _("\ | |
19388 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19389 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19390 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19391 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19392 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19393 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19394 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19395 | position dependent (non shared) code\n\ |
316f5878 RS |
19396 | -mabi=ABI create ABI conformant object file for:\n")); |
19397 | ||
19398 | first = 1; | |
19399 | ||
19400 | show (stream, "32", &column, &first); | |
19401 | show (stream, "o64", &column, &first); | |
19402 | show (stream, "n32", &column, &first); | |
19403 | show (stream, "64", &column, &first); | |
19404 | show (stream, "eabi", &column, &first); | |
19405 | ||
19406 | fputc ('\n', stream); | |
19407 | ||
19408 | fprintf (stream, _("\ | |
19409 | -32 create o32 ABI object file (default)\n\ | |
19410 | -n32 create n32 ABI object file\n\ | |
19411 | -64 create 64 ABI object file\n")); | |
19412 | #endif | |
e7af610e | 19413 | } |
14e777e0 | 19414 | |
1575952e | 19415 | #ifdef TE_IRIX |
14e777e0 | 19416 | enum dwarf2_format |
413a266c | 19417 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19418 | { |
369943fe | 19419 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19420 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19421 | else |
19422 | return dwarf2_format_32bit; | |
19423 | } | |
1575952e | 19424 | #endif |
73369e65 EC |
19425 | |
19426 | int | |
19427 | mips_dwarf2_addr_size (void) | |
19428 | { | |
6b6b3450 | 19429 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19430 | return 8; |
73369e65 EC |
19431 | else |
19432 | return 4; | |
19433 | } | |
5862107c EC |
19434 | |
19435 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19436 | void | |
19437 | mips_cfi_frame_initial_instructions (void) | |
19438 | { | |
19439 | cfi_add_CFA_def_cfa_register (SP); | |
19440 | } | |
19441 | ||
707bfff6 TS |
19442 | int |
19443 | tc_mips_regname_to_dw2regnum (char *regname) | |
19444 | { | |
19445 | unsigned int regnum = -1; | |
19446 | unsigned int reg; | |
19447 | ||
19448 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19449 | regnum = reg; | |
19450 | ||
19451 | return regnum; | |
19452 | } |