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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
fb251650 | 2 | Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
b2b8c24e | 28 | #include "libiberty.h" |
3d3c5039 ILT |
29 | |
30 | #include <ctype.h> | |
31 | ||
1dc1e798 | 32 | #ifdef USE_STDARG |
3d3c5039 | 33 | #include <stdarg.h> |
1dc1e798 KR |
34 | #endif |
35 | #ifdef USE_VARARGS | |
3d3c5039 | 36 | #include <varargs.h> |
1dc1e798 | 37 | #endif |
3d3c5039 | 38 | |
918692a5 | 39 | #include "opcode/mips.h" |
3d3c5039 | 40 | |
739708fa KR |
41 | #ifdef OBJ_MAYBE_ELF |
42 | /* Clean up namespace so we can include obj-elf.h too. */ | |
43 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
44 | #undef OBJ_PROCESS_STAB | |
45 | #undef OUTPUT_FLAVOR | |
46 | #undef S_GET_ALIGN | |
47 | #undef S_GET_SIZE | |
48 | #undef S_SET_ALIGN | |
49 | #undef S_SET_SIZE | |
50 | #undef TARGET_SYMBOL_FIELDS | |
51 | #undef obj_frob_file | |
52 | #undef obj_frob_symbol | |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
f2a663d3 | 73 | static char *mips_regmask_frag; |
f2a663d3 | 74 | |
3d3c5039 | 75 | #define AT 1 |
9226253a | 76 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
77 | #define KT0 26 |
78 | #define KT1 27 | |
670a50eb | 79 | #define GP 28 |
9226253a ILT |
80 | #define SP 29 |
81 | #define FP 30 | |
3d3c5039 ILT |
82 | #define RA 31 |
83 | ||
1dc1e798 | 84 | extern int target_big_endian; |
88225433 | 85 | |
04cb3372 | 86 | /* The default target format to use. */ |
1dc1e798 KR |
87 | const char * |
88 | mips_target_format () | |
89 | { | |
90 | switch (OUTPUT_FLAVOR) | |
91 | { | |
92 | case bfd_target_aout_flavour: | |
93 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
94 | case bfd_target_ecoff_flavour: | |
95 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
96 | case bfd_target_elf_flavour: | |
97 | return target_big_endian ? "elf32-bigmips" : "elf32-littlemips"; | |
98 | default: | |
99 | abort (); | |
100 | } | |
101 | } | |
04cb3372 | 102 | |
d2c71068 | 103 | /* The name of the readonly data section. */ |
1dc1e798 KR |
104 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
105 | ? ".data" \ | |
106 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
107 | ? ".rdata" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
109 | ? ".rodata" \ | |
110 | : (abort (), "")) | |
d2c71068 | 111 | |
1aa6938e ILT |
112 | /* These variables are filled in with the masks of registers used. |
113 | The object format code reads them and puts them in the appropriate | |
114 | place. */ | |
115 | unsigned long mips_gprmask; | |
116 | unsigned long mips_cprmask[4]; | |
117 | ||
1051c97f ILT |
118 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
119 | temporarily using .set mipsN). */ | |
8358c818 ILT |
120 | static int mips_isa = -1; |
121 | ||
1051c97f ILT |
122 | /* MIPS ISA we are using for this output file. */ |
123 | static int file_mips_isa; | |
124 | ||
8c63448a | 125 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 126 | static int mips_cpu = -1; |
8c63448a | 127 | |
b2b8c24e ILT |
128 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
129 | static int mips_4650 = -1; | |
130 | ||
e532b44c ILT |
131 | /* Whether the 4010 instructions are permitted. */ |
132 | static int mips_4010 = -1; | |
133 | ||
c625fc23 JSC |
134 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
135 | static int mips_4100 = -1; | |
136 | ||
e532b44c ILT |
137 | /* Whether the processor uses hardware interlocks, and thus does not |
138 | require nops to be inserted. */ | |
139 | static int interlocks = -1; | |
140 | ||
d9aba805 ILT |
141 | /* MIPS PIC level. */ |
142 | ||
143 | enum mips_pic_level | |
144 | { | |
145 | /* Do not generate PIC code. */ | |
146 | NO_PIC, | |
147 | ||
148 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
149 | not sure what it is supposed to do. */ | |
150 | IRIX4_PIC, | |
151 | ||
152 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
153 | SVR4_PIC, | |
154 | ||
155 | /* Generate PIC code without using a global offset table: the data | |
156 | segment has a maximum size of 64K, all data references are off | |
157 | the $gp register, and all text references are PC relative. This | |
158 | is used on some embedded systems. */ | |
159 | EMBEDDED_PIC | |
160 | }; | |
161 | ||
162 | static enum mips_pic_level mips_pic; | |
9226253a | 163 | |
fb251650 ILT |
164 | /* 1 if we should generate 32 bit offsets from the GP register in |
165 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
166 | static int mips_big_got; | |
167 | ||
8ea7f4e8 ILT |
168 | /* 1 if trap instructions should used for overflow rather than break |
169 | instructions. */ | |
170 | static int mips_trap; | |
171 | ||
3d3c5039 ILT |
172 | static int mips_warn_about_macros; |
173 | static int mips_noreorder; | |
0dd2d296 | 174 | static int mips_any_noreorder; |
3d3c5039 ILT |
175 | static int mips_nomove; |
176 | static int mips_noat; | |
177 | static int mips_nobopt; | |
178 | ||
670a50eb ILT |
179 | /* The size of the small data section. */ |
180 | static int g_switch_value = 8; | |
42562568 ILT |
181 | /* Whether the -G option was used. */ |
182 | static int g_switch_seen = 0; | |
670a50eb | 183 | |
3d3c5039 ILT |
184 | #define N_RMASK 0xc4 |
185 | #define N_VFP 0xd4 | |
186 | ||
d8a1c247 KR |
187 | /* If we can determine in advance that GP optimization won't be |
188 | possible, we can skip the relaxation stuff that tries to produce | |
189 | GP-relative references. This makes delay slot optimization work | |
190 | better. | |
191 | ||
192 | This function can only provide a guess, but it seems to work for | |
193 | gcc output. If it guesses wrong, the only loss should be in | |
194 | efficiency; it shouldn't introduce any bugs. | |
195 | ||
196 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
197 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
198 | static int nopic_need_relax PARAMS ((symbolS *)); | |
199 | ||
3d3c5039 ILT |
200 | /* handle of the OPCODE hash table */ |
201 | static struct hash_control *op_hash = NULL; | |
202 | ||
203 | /* This array holds the chars that always start a comment. If the | |
204 | pre-processor is disabled, these aren't very useful */ | |
205 | const char comment_chars[] = "#"; | |
206 | ||
207 | /* This array holds the chars that only start a comment at the beginning of | |
208 | a line. If the line seems to have the form '# 123 filename' | |
209 | .line and .file directives will appear in the pre-processed output */ | |
210 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
211 | first line of the input file. This is because the compiler outputs | |
212 | #NO_APP at the beginning of its output. */ | |
213 | /* Also note that C style comments are always supported. */ | |
214 | const char line_comment_chars[] = "#"; | |
215 | ||
216 | /* This array holds machine specific line separator characters. */ | |
217 | const char line_separator_chars[] = ""; | |
218 | ||
219 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
220 | const char EXP_CHARS[] = "eE"; | |
221 | ||
222 | /* Chars that mean this number is a floating point constant */ | |
223 | /* As in 0f12.456 */ | |
224 | /* or 0d1.2345e12 */ | |
225 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
226 | ||
227 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
228 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
229 | but nothing is ideal around here. | |
230 | */ | |
231 | ||
670a50eb | 232 | static char *insn_error; |
3d3c5039 | 233 | |
22ba90ce | 234 | static int byte_order; |
3d3c5039 ILT |
235 | |
236 | static int auto_align = 1; | |
becfe05e ILT |
237 | |
238 | /* Symbol labelling the current insn. */ | |
239 | static symbolS *insn_label; | |
240 | ||
9226253a ILT |
241 | /* When outputting SVR4 PIC code, the assembler needs to know the |
242 | offset in the stack frame from which to restore the $gp register. | |
243 | This is set by the .cprestore pseudo-op, and saved in this | |
244 | variable. */ | |
0dd2d296 ILT |
245 | static offsetT mips_cprestore_offset = -1; |
246 | ||
247 | /* This is the register which holds the stack frame, as set by the | |
248 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
249 | static int mips_frame_reg = SP; | |
9226253a | 250 | |
becfe05e ILT |
251 | /* To output NOP instructions correctly, we need to keep information |
252 | about the previous two instructions. */ | |
253 | ||
0aa07269 ILT |
254 | /* Whether we are optimizing. The default value of 2 means to remove |
255 | unneeded NOPs and swap branch instructions when possible. A value | |
256 | of 1 means to not swap branches. A value of 0 means to always | |
257 | insert NOPs. */ | |
258 | static int mips_optimize = 2; | |
4e95866e | 259 | |
22ba90ce ILT |
260 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
261 | equivalent to seeing no -g option at all. */ | |
262 | static int mips_debug = 0; | |
263 | ||
becfe05e ILT |
264 | /* The previous instruction. */ |
265 | static struct mips_cl_insn prev_insn; | |
266 | ||
267 | /* The instruction before prev_insn. */ | |
268 | static struct mips_cl_insn prev_prev_insn; | |
269 | ||
270 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
271 | point the insn_mo field at this dummy integer. */ | |
272 | static const struct mips_opcode dummy_opcode = { 0 }; | |
273 | ||
274 | /* Non-zero if prev_insn is valid. */ | |
275 | static int prev_insn_valid; | |
276 | ||
277 | /* The frag for the previous instruction. */ | |
278 | static struct frag *prev_insn_frag; | |
279 | ||
280 | /* The offset into prev_insn_frag for the previous instruction. */ | |
281 | static long prev_insn_where; | |
282 | ||
283 | /* The reloc for the previous instruction, if any. */ | |
284 | static fixS *prev_insn_fixp; | |
285 | ||
286 | /* Non-zero if the previous instruction was in a delay slot. */ | |
287 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
288 | |
289 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
290 | static int prev_insn_unreordered; | |
291 | ||
292 | /* Non-zero if the previous previous instruction was in a .set | |
293 | noreorder. */ | |
294 | static int prev_prev_insn_unreordered; | |
3d3c5039 | 295 | \f |
0dd2d296 ILT |
296 | /* Since the MIPS does not have multiple forms of PC relative |
297 | instructions, we do not have to do relaxing as is done on other | |
298 | platforms. However, we do have to handle GP relative addressing | |
299 | correctly, which turns out to be a similar problem. | |
300 | ||
301 | Every macro that refers to a symbol can occur in (at least) two | |
302 | forms, one with GP relative addressing and one without. For | |
303 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 304 | a macro instruction like this: |
0dd2d296 ILT |
305 | lw $4,i |
306 | If i can be addressed off the GP register (this is true if it is in | |
307 | the .sbss or .sdata section, or if it is known to be smaller than | |
308 | the -G argument) this will generate the following instruction: | |
309 | lw $4,i($gp) | |
310 | This instruction will use a GPREL reloc. If i can not be addressed | |
311 | off the GP register, the following instruction sequence will be used: | |
312 | lui $at,i | |
313 | lw $4,i($at) | |
314 | In this case the first instruction will have a HI16 reloc, and the | |
315 | second reloc will have a LO16 reloc. Both relocs will be against | |
316 | the symbol i. | |
317 | ||
318 | The issue here is that we may not know whether i is GP addressable | |
319 | until after we see the instruction that uses it. Therefore, we | |
320 | want to be able to choose the final instruction sequence only at | |
321 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 322 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
323 | end of assembly. |
324 | ||
325 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
326 | addressing in quite the same way, but the issue still arises as |
327 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
328 | |
329 | We handle these issues by actually generating both possible | |
330 | instruction sequences. The longer one is put in a frag_var with | |
331 | type rs_machine_dependent. We encode what to do with the frag in | |
332 | the subtype field. We encode (1) the number of existing bytes to | |
333 | replace, (2) the number of new bytes to use, (3) the offset from | |
334 | the start of the existing bytes to the first reloc we must generate | |
335 | (that is, the offset is applied from the start of the existing | |
336 | bytes after they are replaced by the new bytes, if any), (4) the | |
337 | offset from the start of the existing bytes to the second reloc, | |
338 | (5) whether a third reloc is needed (the third reloc is always four | |
339 | bytes after the second reloc), and (6) whether to warn if this | |
340 | variant is used (this is sometimes needed if .set nomacro or .set | |
341 | noat is in effect). All these numbers are reasonably small. | |
342 | ||
343 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
344 | ensure that delay slots are handled correctly. Fortunately, there |
345 | are a limited number of cases. When the second instruction | |
346 | sequence is generated, append_insn is directed to maintain the | |
347 | existing delay slot information, so it continues to apply to any | |
348 | code after the second instruction sequence. This means that the | |
349 | second instruction sequence must not impose any requirements not | |
350 | required by the first instruction sequence. | |
0dd2d296 ILT |
351 | |
352 | These variant frags are then handled in functions called by the | |
353 | machine independent code. md_estimate_size_before_relax returns | |
354 | the final size of the frag. md_convert_frag sets up the final form | |
355 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
356 | one if needed. */ | |
357 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
358 | ((relax_substateT) \ | |
359 | (((old) << 24) \ | |
360 | | ((new) << 16) \ | |
361 | | (((reloc1) + 64) << 9) \ | |
362 | | (((reloc2) + 64) << 2) \ | |
363 | | ((reloc3) ? (1 << 1) : 0) \ | |
364 | | ((warn) ? 1 : 0))) | |
365 | #define RELAX_OLD(i) (((i) >> 24) & 0xff) | |
366 | #define RELAX_NEW(i) (((i) >> 16) & 0xff) | |
483971bd KR |
367 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
368 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
369 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
370 | #define RELAX_WARN(i) ((i) & 1) | |
371 | \f | |
3d3c5039 ILT |
372 | /* Prototypes for static functions. */ |
373 | ||
374 | #ifdef __STDC__ | |
375 | #define internalError() \ | |
376 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
377 | #else | |
378 | #define internalError() as_fatal ("MIPS internal Error"); | |
379 | #endif | |
380 | ||
becfe05e | 381 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
604633ae | 382 | unsigned int reg, int fpr)); |
fb251650 | 383 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
384 | static void append_insn PARAMS ((char *place, |
385 | struct mips_cl_insn * ip, | |
670a50eb | 386 | expressionS * p, |
3d3c5039 | 387 | bfd_reloc_code_real_type r)); |
becfe05e ILT |
388 | static void mips_no_prev_insn PARAMS ((void)); |
389 | static void mips_emit_delays PARAMS ((void)); | |
c625fc23 | 390 | #ifdef USE_STDARG |
0dd2d296 | 391 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
392 | const char *name, const char *fmt, |
393 | ...)); | |
c625fc23 JSC |
394 | #else |
395 | static void macro_build (); | |
396 | #endif | |
0dd2d296 ILT |
397 | static void macro_build_lui PARAMS ((char *place, int *counter, |
398 | expressionS * ep, int regnum)); | |
6e8dda9c | 399 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 400 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 401 | expressionS *)); |
d8a1c247 | 402 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 403 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 404 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
405 | #ifdef LOSING_COMPILER |
406 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
407 | #endif | |
670a50eb ILT |
408 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
409 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
410 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 411 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 412 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
413 | static void s_align PARAMS ((int)); |
414 | static void s_change_sec PARAMS ((int)); | |
415 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 416 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 417 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
418 | static void s_option PARAMS ((int)); |
419 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
420 | static void s_abicalls PARAMS ((int)); |
421 | static void s_cpload PARAMS ((int)); | |
422 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
423 | static void s_gpword PARAMS ((int)); |
424 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
425 | static void md_obj_begin PARAMS ((void)); |
426 | static void md_obj_end PARAMS ((void)); | |
427 | static long get_number PARAMS ((void)); | |
428 | static void s_ent PARAMS ((int)); | |
429 | static void s_mipsend PARAMS ((int)); | |
430 | static void s_file PARAMS ((int)); | |
3d3c5039 ILT |
431 | \f |
432 | /* Pseudo-op table. | |
433 | ||
434 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
435 | should be defined here, but are currently unsupported: .alias, | |
436 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
437 | ||
438 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
439 | specific to the type of debugging information being generated, and | |
440 | should be defined by the object format: .aent, .begin, .bend, | |
441 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
442 | .vreg. | |
443 | ||
444 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
445 | not MIPS CPU specific, but are also not specific to the object file | |
446 | format. This file is probably the best place to define them, but | |
447 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
448 | .struct, .weakext. */ | |
449 | ||
739708fa | 450 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 451 | { |
670a50eb ILT |
452 | /* MIPS specific pseudo-ops. */ |
453 | {"option", s_option, 0}, | |
454 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
455 | {"rdata", s_change_sec, 'r'}, |
456 | {"sdata", s_change_sec, 's'}, | |
457 | {"livereg", s_ignore, 0}, | |
739708fa KR |
458 | {"abicalls", s_abicalls, 0}, |
459 | {"cpload", s_cpload, 0}, | |
460 | {"cprestore", s_cprestore, 0}, | |
461 | {"gpword", s_gpword, 0}, | |
462 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 463 | |
670a50eb | 464 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 465 | chips. */ |
739708fa | 466 | {"asciiz", stringer, 1}, |
670a50eb ILT |
467 | {"bss", s_change_sec, 'b'}, |
468 | {"err", s_err, 0}, | |
469 | {"half", s_cons, 1}, | |
52aa70b5 | 470 | {"dword", s_cons, 3}, |
3d3c5039 | 471 | |
670a50eb | 472 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 473 | here for one reason or another. */ |
670a50eb ILT |
474 | {"align", s_align, 0}, |
475 | {"byte", s_cons, 0}, | |
476 | {"data", s_change_sec, 'd'}, | |
becfe05e | 477 | {"double", s_float_cons, 'd'}, |
becfe05e | 478 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
479 | {"globl", s_mips_globl, 0}, |
480 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
481 | {"hword", s_cons, 1}, |
482 | {"int", s_cons, 2}, | |
483 | {"long", s_cons, 2}, | |
484 | {"octa", s_cons, 4}, | |
485 | {"quad", s_cons, 3}, | |
486 | {"short", s_cons, 1}, | |
487 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
488 | {"text", s_change_sec, 't'}, |
489 | {"word", s_cons, 2}, | |
739708fa KR |
490 | { 0 }, |
491 | }; | |
3d3c5039 | 492 | |
739708fa | 493 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 494 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 495 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 496 | {"aent", s_ent, 1}, |
9226253a | 497 | {"bgnb", s_ignore, 0}, |
670a50eb | 498 | {"end", s_mipsend, 0}, |
9226253a | 499 | {"endb", s_ignore, 0}, |
670a50eb ILT |
500 | {"ent", s_ent, 0}, |
501 | {"file", s_file, 0}, | |
502 | {"fmask", s_ignore, 'F'}, | |
503 | {"frame", s_ignore, 0}, | |
504 | {"loc", s_ignore, 0}, | |
505 | {"mask", s_ignore, 'R'}, | |
506 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
507 | { 0 }, |
508 | }; | |
61420a20 | 509 | |
739708fa KR |
510 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
511 | ||
512 | void | |
513 | mips_pop_insert () | |
514 | { | |
515 | pop_insert (mips_pseudo_table); | |
516 | if (! ECOFF_DEBUGGING) | |
517 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 518 | } |
3d3c5039 | 519 | \f |
3d3c5039 ILT |
520 | static char *expr_end; |
521 | ||
522 | static expressionS imm_expr; | |
523 | static expressionS offset_expr; | |
524 | static bfd_reloc_code_real_type imm_reloc; | |
525 | static bfd_reloc_code_real_type offset_reloc; | |
526 | ||
527 | /* | |
528 | * This function is called once, at assembler startup time. It should | |
529 | * set up all the tables, etc. that the MD part of the assembler will need. | |
530 | */ | |
531 | void | |
670a50eb | 532 | md_begin () |
3d3c5039 | 533 | { |
0dd2d296 | 534 | boolean ok = false; |
604633ae | 535 | register const char *retval = NULL; |
670a50eb | 536 | register unsigned int i = 0; |
3d3c5039 | 537 | |
8358c818 ILT |
538 | if (mips_isa == -1) |
539 | { | |
8c63448a ILT |
540 | const char *cpu; |
541 | char *a = NULL; | |
542 | ||
543 | cpu = TARGET_CPU; | |
544 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
545 | { | |
546 | a = xmalloc (sizeof TARGET_CPU); | |
547 | strcpy (a, TARGET_CPU); | |
548 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
549 | cpu = a; | |
550 | } | |
551 | ||
552 | if (strcmp (cpu, "mips") == 0) | |
553 | { | |
554 | mips_isa = 1; | |
4bb0cc41 ILT |
555 | if (mips_cpu == -1) |
556 | mips_cpu = 3000; | |
8c63448a ILT |
557 | } |
558 | else if (strcmp (cpu, "r6000") == 0 | |
559 | || strcmp (cpu, "mips2") == 0) | |
560 | { | |
561 | mips_isa = 2; | |
4bb0cc41 ILT |
562 | if (mips_cpu == -1) |
563 | mips_cpu = 6000; | |
8c63448a ILT |
564 | } |
565 | else if (strcmp (cpu, "mips64") == 0 | |
566 | || strcmp (cpu, "r4000") == 0 | |
567 | || strcmp (cpu, "mips3") == 0) | |
568 | { | |
569 | mips_isa = 3; | |
4bb0cc41 ILT |
570 | if (mips_cpu == -1) |
571 | mips_cpu = 4000; | |
8c63448a ILT |
572 | } |
573 | else if (strcmp (cpu, "r4400") == 0) | |
574 | { | |
575 | mips_isa = 3; | |
4bb0cc41 ILT |
576 | if (mips_cpu == -1) |
577 | mips_cpu = 4400; | |
8c63448a ILT |
578 | } |
579 | else if (strcmp (cpu, "mips64orion") == 0 | |
580 | || strcmp (cpu, "r4600") == 0) | |
581 | { | |
582 | mips_isa = 3; | |
4bb0cc41 ILT |
583 | if (mips_cpu == -1) |
584 | mips_cpu = 4600; | |
8c63448a | 585 | } |
b2b8c24e ILT |
586 | else if (strcmp (cpu, "r4650") == 0) |
587 | { | |
588 | mips_isa = 3; | |
589 | if (mips_cpu == -1) | |
590 | mips_cpu = 4650; | |
591 | if (mips_4650 == -1) | |
592 | mips_4650 = 1; | |
593 | } | |
c625fc23 JSC |
594 | else if (strcmp (cpu, "mips64vr4300") == 0) |
595 | { | |
596 | mips_isa = 3; | |
597 | if (mips_cpu == -1) | |
598 | mips_cpu = 4300; | |
599 | } | |
600 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
601 | { | |
602 | mips_isa = 3; | |
603 | if (mips_cpu == -1) | |
604 | mips_cpu = 4100; | |
605 | if (mips_4100 == -1) | |
606 | mips_4100 = 1; | |
607 | } | |
e532b44c ILT |
608 | else if (strcmp (cpu, "r4010") == 0) |
609 | { | |
610 | mips_isa = 2; | |
611 | if (mips_cpu == -1) | |
612 | mips_cpu = 4010; | |
613 | if (mips_4010 == -1) | |
614 | mips_4010 = 1; | |
615 | } | |
d8a1c247 KR |
616 | else if (strcmp (cpu, "r8000") == 0 |
617 | || strcmp (cpu, "mips4") == 0) | |
618 | { | |
619 | mips_isa = 4; | |
620 | if (mips_cpu == -1) | |
621 | mips_cpu = 8000; | |
622 | } | |
623 | else if (strcmp (cpu, "r10000") == 0) | |
624 | { | |
625 | mips_isa = 4; | |
626 | if (mips_cpu == -1) | |
627 | mips_cpu = 10000; | |
628 | } | |
8358c818 | 629 | else |
8c63448a ILT |
630 | { |
631 | mips_isa = 1; | |
4bb0cc41 ILT |
632 | if (mips_cpu == -1) |
633 | mips_cpu = 3000; | |
8c63448a ILT |
634 | } |
635 | ||
636 | if (a != NULL) | |
637 | free (a); | |
8358c818 ILT |
638 | } |
639 | ||
b2b8c24e ILT |
640 | if (mips_4650 < 0) |
641 | mips_4650 = 0; | |
642 | ||
e532b44c ILT |
643 | if (mips_4010 < 0) |
644 | mips_4010 = 0; | |
645 | ||
c625fc23 JSC |
646 | if (mips_4100 < 0) |
647 | mips_4100 = 0; | |
648 | ||
649 | if (mips_4650 || mips_4010 || mips_4100) | |
e532b44c ILT |
650 | interlocks = 1; |
651 | else | |
652 | interlocks = 0; | |
653 | ||
8ea7f4e8 ILT |
654 | if (mips_isa < 2 && mips_trap) |
655 | as_bad ("trap exception not supported at ISA 1"); | |
656 | ||
97f99d11 ILT |
657 | switch (mips_isa) |
658 | { | |
659 | case 1: | |
660 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
661 | break; | |
662 | case 2: | |
663 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
664 | break; | |
665 | case 3: | |
666 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
667 | break; | |
d8a1c247 KR |
668 | case 4: |
669 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
670 | break; | |
97f99d11 ILT |
671 | } |
672 | if (! ok) | |
673 | as_warn ("Could not set architecture and machine"); | |
674 | ||
1051c97f ILT |
675 | file_mips_isa = mips_isa; |
676 | ||
13fe1379 ILT |
677 | op_hash = hash_new (); |
678 | ||
670a50eb ILT |
679 | for (i = 0; i < NUMOPCODES;) |
680 | { | |
681 | const char *name = mips_opcodes[i].name; | |
682 | ||
604633ae | 683 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 684 | if (retval != NULL) |
670a50eb ILT |
685 | { |
686 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
687 | mips_opcodes[i].name, retval); | |
688 | as_fatal ("Broken assembler. No assembly attempted."); | |
689 | } | |
690 | do | |
691 | { | |
8358c818 ILT |
692 | if (mips_opcodes[i].pinfo != INSN_MACRO |
693 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
694 | != mips_opcodes[i].match)) | |
670a50eb ILT |
695 | { |
696 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
697 | mips_opcodes[i].name, mips_opcodes[i].args); | |
698 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 699 | } |
670a50eb ILT |
700 | ++i; |
701 | } | |
702 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
703 | } |
704 | ||
becfe05e ILT |
705 | mips_no_prev_insn (); |
706 | ||
1aa6938e ILT |
707 | mips_gprmask = 0; |
708 | mips_cprmask[0] = 0; | |
709 | mips_cprmask[1] = 0; | |
710 | mips_cprmask[2] = 0; | |
711 | mips_cprmask[3] = 0; | |
712 | ||
8358c818 ILT |
713 | /* set the default alignment for the text section (2**2) */ |
714 | record_alignment (text_section, 2); | |
715 | ||
1dc1e798 KR |
716 | if (USE_GLOBAL_POINTER_OPT) |
717 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 718 | |
1dc1e798 KR |
719 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
720 | { | |
721 | /* Sections must be aligned to 16 byte boundaries. */ | |
722 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
723 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
724 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
725 | ||
726 | /* Create a .reginfo section for register masks and a .mdebug | |
727 | section for debugging information. */ | |
728 | { | |
729 | segT seg; | |
730 | subsegT subseg; | |
731 | segT sec; | |
732 | ||
733 | seg = now_seg; | |
734 | subseg = now_subseg; | |
735 | sec = subseg_new (".reginfo", (subsegT) 0); | |
736 | ||
737 | /* The ABI says this section should be loaded so that the | |
738 | running program can access it. */ | |
739 | (void) bfd_set_section_flags (stdoutput, sec, | |
740 | (SEC_ALLOC | SEC_LOAD | |
741 | | SEC_READONLY | SEC_DATA)); | |
742 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
8358c818 | 743 | |
f2a663d3 | 744 | #ifdef OBJ_ELF |
1dc1e798 KR |
745 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
746 | #endif | |
f2a663d3 | 747 | |
739708fa KR |
748 | if (ECOFF_DEBUGGING) |
749 | { | |
750 | sec = subseg_new (".mdebug", (subsegT) 0); | |
751 | (void) bfd_set_section_flags (stdoutput, sec, | |
752 | SEC_HAS_CONTENTS | SEC_READONLY); | |
753 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
754 | } | |
0dd2d296 | 755 | |
1dc1e798 KR |
756 | subseg_set (seg, subseg); |
757 | } | |
758 | } | |
f2a663d3 | 759 | |
739708fa KR |
760 | if (! ECOFF_DEBUGGING) |
761 | md_obj_begin (); | |
3d3c5039 ILT |
762 | } |
763 | ||
764 | void | |
13fe1379 | 765 | md_mips_end () |
3d3c5039 | 766 | { |
739708fa KR |
767 | if (! ECOFF_DEBUGGING) |
768 | md_obj_end (); | |
3d3c5039 ILT |
769 | } |
770 | ||
771 | void | |
670a50eb ILT |
772 | md_assemble (str) |
773 | char *str; | |
3d3c5039 | 774 | { |
670a50eb | 775 | struct mips_cl_insn insn; |
3d3c5039 | 776 | |
5ac34ac3 ILT |
777 | imm_expr.X_op = O_absent; |
778 | offset_expr.X_op = O_absent; | |
3d3c5039 | 779 | |
670a50eb ILT |
780 | mips_ip (str, &insn); |
781 | if (insn_error) | |
782 | { | |
783 | as_bad ("%s `%s'", insn_error, str); | |
784 | return; | |
785 | } | |
786 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
787 | { | |
788 | macro (&insn); | |
3d3c5039 | 789 | } |
670a50eb ILT |
790 | else |
791 | { | |
5ac34ac3 | 792 | if (imm_expr.X_op != O_absent) |
0dd2d296 | 793 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc); |
5ac34ac3 | 794 | else if (offset_expr.X_op != O_absent) |
0dd2d296 | 795 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc); |
670a50eb | 796 | else |
0dd2d296 | 797 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED); |
3d3c5039 ILT |
798 | } |
799 | } | |
800 | ||
becfe05e ILT |
801 | /* See whether instruction IP reads register REG. If FPR is non-zero, |
802 | REG is a floating point register. */ | |
803 | ||
804 | static int | |
805 | insn_uses_reg (ip, reg, fpr) | |
806 | struct mips_cl_insn *ip; | |
604633ae | 807 | unsigned int reg; |
becfe05e ILT |
808 | int fpr; |
809 | { | |
810 | /* Don't report on general register 0, since it never changes. */ | |
811 | if (! fpr && reg == 0) | |
812 | return 0; | |
813 | ||
814 | if (fpr) | |
815 | { | |
816 | /* If we are called with either $f0 or $f1, we must check $f0. | |
817 | This is not optimal, because it will introduce an unnecessary | |
818 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
819 | need to distinguish reading both $f0 and $f1 or just one of | |
820 | them. Note that we don't have to check the other way, | |
821 | because there is no instruction that sets both $f0 and $f1 | |
822 | and requires a delay. */ | |
823 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
824 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
825 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
826 | return 1; |
827 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
828 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
829 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
830 | return 1; |
831 | } | |
832 | else | |
833 | { | |
834 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
835 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
836 | return 1; | |
837 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
838 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
839 | return 1; | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
fb251650 ILT |
845 | /* This function returns true if modifying a register requires a |
846 | delay. */ | |
847 | ||
848 | static int | |
849 | reg_needs_delay (reg) | |
850 | int reg; | |
851 | { | |
852 | unsigned long prev_pinfo; | |
853 | ||
854 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
855 | if (! mips_noreorder | |
856 | && mips_isa < 4 | |
857 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
858 | || (mips_isa < 2 | |
859 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
860 | { | |
861 | /* A load from a coprocessor or from memory. All load | |
862 | delays delay the use of general register rt for one | |
863 | instruction on the r3000. The r6000 and r4000 use | |
864 | interlocks. */ | |
865 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
866 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
867 | return 1; | |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
0dd2d296 ILT |
873 | /* Output an instruction. PLACE is where to put the instruction; if |
874 | it is NULL, this uses frag_more to get room. IP is the instruction | |
875 | information. ADDRESS_EXPR is an operand of the instruction to be | |
876 | used with RELOC_TYPE. */ | |
3d3c5039 | 877 | |
3d3c5039 | 878 | static void |
0dd2d296 ILT |
879 | append_insn (place, ip, address_expr, reloc_type) |
880 | char *place; | |
670a50eb ILT |
881 | struct mips_cl_insn *ip; |
882 | expressionS *address_expr; | |
883 | bfd_reloc_code_real_type reloc_type; | |
3d3c5039 | 884 | { |
1aa6938e | 885 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 886 | char *f; |
becfe05e ILT |
887 | fixS *fixp; |
888 | int nops = 0; | |
3d3c5039 | 889 | |
1aa6938e ILT |
890 | prev_pinfo = prev_insn.insn_mo->pinfo; |
891 | pinfo = ip->insn_mo->pinfo; | |
892 | ||
0dd2d296 | 893 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
894 | { |
895 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 896 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 897 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
898 | (1) a load from memory delay |
899 | (2) a load from a coprocessor delay | |
900 | (3) an unconditional branch delay | |
901 | (4) a conditional branch delay | |
902 | (5) a move to coprocessor register delay | |
903 | (6) a load coprocessor register from memory delay | |
904 | (7) a coprocessor condition code delay | |
905 | (8) a HI/LO special register delay | |
becfe05e ILT |
906 | |
907 | There are a lot of optimizations we could do that we don't. | |
908 | In particular, we do not, in general, reorder instructions. | |
909 | If you use gcc with optimization, it will reorder | |
910 | instructions and generally do much more optimization then we | |
911 | do here; repeating all that work in the assembler would only | |
912 | benefit hand written assembly code, and does not seem worth | |
913 | it. */ | |
914 | ||
915 | /* This is how a NOP is emitted. */ | |
916 | #define emit_nop() md_number_to_chars (frag_more (4), 0, 4) | |
917 | ||
918 | /* The previous insn might require a delay slot, depending upon | |
919 | the contents of the current insn. */ | |
d8a1c247 KR |
920 | if (mips_isa < 4 |
921 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
922 | || (mips_isa < 2 | |
923 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
924 | { |
925 | /* A load from a coprocessor or from memory. All load | |
926 | delays delay the use of general register rt for one | |
927 | instruction on the r3000. The r6000 and r4000 use | |
928 | interlocks. */ | |
1aa6938e | 929 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
930 | if (mips_optimize == 0 |
931 | || insn_uses_reg (ip, | |
932 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
933 | & OP_MASK_RT), | |
934 | 0)) | |
becfe05e ILT |
935 | ++nops; |
936 | } | |
d8a1c247 KR |
937 | else if (mips_isa < 4 |
938 | && ((prev_pinfo & INSN_COPROC_MOVE_DELAY) | |
939 | || (mips_isa < 2 | |
940 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
941 | { |
942 | /* A generic coprocessor delay. The previous instruction | |
943 | modified a coprocessor general or control register. If | |
944 | it modified a control register, we need to avoid any | |
945 | coprocessor instruction (this is probably not always | |
946 | required, but it sometimes is). If it modified a general | |
947 | register, we avoid using that register. | |
948 | ||
8358c818 ILT |
949 | On the r6000 and r4000 loading a coprocessor register |
950 | from memory is interlocked, and does not require a delay. | |
951 | ||
becfe05e ILT |
952 | This case is not handled very well. There is no special |
953 | knowledge of CP0 handling, and the coprocessors other | |
954 | than the floating point unit are not distinguished at | |
955 | all. */ | |
1aa6938e | 956 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 957 | { |
0aa07269 ILT |
958 | if (mips_optimize == 0 |
959 | || insn_uses_reg (ip, | |
8358c818 ILT |
960 | ((prev_insn.insn_opcode >> OP_SH_FT) |
961 | & OP_MASK_FT), | |
0aa07269 | 962 | 1)) |
becfe05e ILT |
963 | ++nops; |
964 | } | |
1aa6938e | 965 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 966 | { |
0aa07269 ILT |
967 | if (mips_optimize == 0 |
968 | || insn_uses_reg (ip, | |
8358c818 ILT |
969 | ((prev_insn.insn_opcode >> OP_SH_FS) |
970 | & OP_MASK_FS), | |
0aa07269 | 971 | 1)) |
becfe05e ILT |
972 | ++nops; |
973 | } | |
974 | else | |
975 | { | |
976 | /* We don't know exactly what the previous instruction | |
977 | does. If the current instruction uses a coprocessor | |
978 | register, we must insert a NOP. If previous | |
979 | instruction may set the condition codes, and the | |
980 | current instruction uses them, we must insert two | |
981 | NOPS. */ | |
0aa07269 | 982 | if (mips_optimize == 0 |
1aa6938e ILT |
983 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
984 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 985 | nops += 2; |
1aa6938e | 986 | else if (pinfo & INSN_COP) |
becfe05e ILT |
987 | ++nops; |
988 | } | |
989 | } | |
d8a1c247 KR |
990 | else if (mips_isa < 4 |
991 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
becfe05e ILT |
992 | { |
993 | /* The previous instruction sets the coprocessor condition | |
994 | codes, but does not require a general coprocessor delay | |
995 | (this means it is a floating point comparison | |
996 | instruction). If this instruction uses the condition | |
997 | codes, we need to insert a single NOP. */ | |
0aa07269 | 998 | if (mips_optimize == 0 |
1aa6938e | 999 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1000 | ++nops; |
1001 | } | |
1aa6938e | 1002 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1003 | { |
1004 | /* The previous instruction reads the LO register; if the | |
1005 | current instruction writes to the LO register, we must | |
c625fc23 | 1006 | insert two NOPS. The R4650 and VR4100 have interlocks. */ |
e532b44c | 1007 | if (! interlocks |
b2b8c24e ILT |
1008 | && (mips_optimize == 0 |
1009 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1010 | nops += 2; |
1011 | } | |
1012 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1013 | { | |
1014 | /* The previous instruction reads the HI register; if the | |
1015 | current instruction writes to the HI register, we must | |
c625fc23 | 1016 | insert a NOP. The R4650 and VR4100 have interlocks. */ |
e532b44c | 1017 | if (! interlocks |
b2b8c24e ILT |
1018 | && (mips_optimize == 0 |
1019 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1020 | nops += 2; |
1021 | } | |
1022 | ||
1023 | /* There are two cases which require two intervening | |
1024 | instructions: 1) setting the condition codes using a move to | |
1025 | coprocessor instruction which requires a general coprocessor | |
1026 | delay and then reading the condition codes 2) reading the HI | |
b2b8c24e | 1027 | or LO register and then writing to it (except on the R4650, |
c625fc23 JSC |
1028 | and VR4100 which have interlocks). If we are not already |
1029 | emitting a NOP instruction, we must check for these cases | |
1030 | compared to the instruction previous to the previous | |
1031 | instruction. */ | |
becfe05e | 1032 | if (nops == 0 |
d8a1c247 KR |
1033 | && ((mips_isa < 4 |
1034 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) | |
becfe05e | 1035 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
1aa6938e | 1036 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e | 1037 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1038 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1039 | && ! interlocks) |
becfe05e | 1040 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1041 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1042 | && ! interlocks))) |
becfe05e ILT |
1043 | ++nops; |
1044 | ||
0dd2d296 ILT |
1045 | /* If we are being given a nop instruction, don't bother with |
1046 | one of the nops we would otherwise output. This will only | |
1047 | happen when a nop instruction is used with mips_optimize set | |
1048 | to 0. */ | |
1049 | if (nops > 0 && ip->insn_opcode == 0) | |
1050 | --nops; | |
1051 | ||
becfe05e ILT |
1052 | /* Now emit the right number of NOP instructions. */ |
1053 | if (nops > 0) | |
1054 | { | |
8c63448a ILT |
1055 | int i; |
1056 | ||
1057 | for (i = 0; i < nops; i++) | |
becfe05e | 1058 | emit_nop (); |
af255ca0 | 1059 | if (listing) |
546f5536 ILT |
1060 | { |
1061 | listing_prev_line (); | |
1062 | /* We may be at the start of a variant frag. In case we | |
1063 | are, make sure there is enough space for the frag | |
1064 | after the frags created by listing_prev_line. The | |
1065 | argument to frag_grow here must be at least as large | |
1066 | as the argument to all other calls to frag_grow in | |
1067 | this file. We don't have to worry about being in the | |
1068 | middle of a variant frag, because the variants insert | |
1069 | all needed nop instructions themselves. */ | |
1070 | frag_grow (40); | |
1071 | } | |
becfe05e ILT |
1072 | if (insn_label != NULL) |
1073 | { | |
1074 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1075 | insn_label->sy_frag = frag_now; | |
604633ae | 1076 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e ILT |
1077 | } |
1078 | } | |
1079 | } | |
1080 | ||
0dd2d296 ILT |
1081 | if (place == NULL) |
1082 | f = frag_more (4); | |
1083 | else | |
1084 | f = place; | |
becfe05e | 1085 | fixp = NULL; |
670a50eb ILT |
1086 | if (address_expr != NULL) |
1087 | { | |
5ac34ac3 | 1088 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1089 | { |
1090 | switch (reloc_type) | |
1091 | { | |
3d3c5039 | 1092 | case BFD_RELOC_32: |
670a50eb ILT |
1093 | ip->insn_opcode |= address_expr->X_add_number; |
1094 | break; | |
3d3c5039 ILT |
1095 | |
1096 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1097 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1098 | break; | |
3d3c5039 ILT |
1099 | |
1100 | case BFD_RELOC_MIPS_JMP: | |
1101 | case BFD_RELOC_16_PCREL_S2: | |
670a50eb | 1102 | goto need_reloc; |
3d3c5039 ILT |
1103 | |
1104 | default: | |
670a50eb | 1105 | internalError (); |
3d3c5039 | 1106 | } |
670a50eb ILT |
1107 | } |
1108 | else | |
1109 | { | |
1110 | assert (reloc_type != BFD_RELOC_UNUSED); | |
3d3c5039 | 1111 | need_reloc: |
0dd2d296 ILT |
1112 | /* Don't generate a reloc if we are writing into a variant |
1113 | frag. */ | |
1114 | if (place == NULL) | |
1115 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1116 | address_expr, | |
1117 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1118 | reloc_type); | |
3d3c5039 ILT |
1119 | } |
1120 | } | |
becfe05e | 1121 | |
670a50eb ILT |
1122 | md_number_to_chars (f, ip->insn_opcode, 4); |
1123 | ||
1aa6938e ILT |
1124 | /* Update the register mask information. */ |
1125 | if (pinfo & INSN_WRITE_GPR_D) | |
1126 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1127 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1128 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1129 | if (pinfo & INSN_READ_GPR_S) | |
1130 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1131 | if (pinfo & INSN_WRITE_GPR_31) | |
1132 | mips_gprmask |= 1 << 31; | |
1133 | if (pinfo & INSN_WRITE_FPR_D) | |
1134 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1135 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1136 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1137 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1138 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
d8a1c247 KR |
1139 | if ((pinfo & INSN_READ_FPR_R) != 0) |
1140 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1aa6938e ILT |
1141 | if (pinfo & INSN_COP) |
1142 | { | |
1143 | /* We don't keep enough information to sort these cases out. */ | |
1144 | } | |
1145 | /* Never set the bit for $0, which is always zero. */ | |
1146 | mips_gprmask &=~ 1 << 0; | |
1147 | ||
0dd2d296 | 1148 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1149 | { |
becfe05e ILT |
1150 | /* Filling the branch delay slot is more complex. We try to |
1151 | switch the branch with the previous instruction, which we can | |
1152 | do if the previous instruction does not set up a condition | |
1153 | that the branch tests and if the branch is not itself the | |
1154 | target of any branch. */ | |
1aa6938e ILT |
1155 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1156 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1157 | { |
0aa07269 | 1158 | if (mips_optimize < 2 |
19ed8960 ILT |
1159 | /* If we have seen .set volatile or .set nomove, don't |
1160 | optimize. */ | |
1161 | || mips_nomove != 0 | |
4e95866e ILT |
1162 | /* If we had to emit any NOP instructions, then we |
1163 | already know we can not swap. */ | |
1164 | || nops != 0 | |
becfe05e ILT |
1165 | /* If we don't even know the previous insn, we can not |
1166 | swap. */ | |
1167 | || ! prev_insn_valid | |
1168 | /* If the previous insn is already in a branch delay | |
1169 | slot, then we can not swap. */ | |
1170 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1171 | /* If the previous previous insn was in a .set |
1172 | noreorder, we can't swap. Actually, the MIPS | |
1173 | assembler will swap in this situation. However, gcc | |
1174 | configured -with-gnu-as will generate code like | |
1175 | .set noreorder | |
1176 | lw $4,XXX | |
1177 | .set reorder | |
1178 | INSN | |
1179 | bne $4,$0,foo | |
1180 | in which we can not swap the bne and INSN. If gcc is | |
1181 | not configured -with-gnu-as, it does not output the | |
1182 | .set pseudo-ops. We don't have to check | |
1183 | prev_insn_unreordered, because prev_insn_valid will | |
1184 | be 0 in that case. We don't want to use | |
1185 | prev_prev_insn_valid, because we do want to be able | |
1186 | to swap at the start of a function. */ | |
1187 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1188 | /* If the branch is itself the target of a branch, we |
1189 | can not swap. We cheat on this; all we check for is | |
1190 | whether there is a label on this instruction. If | |
1191 | there are any branches to anything other than a | |
1192 | label, users must use .set noreorder. */ | |
1193 | || insn_label != NULL | |
777ad64d ILT |
1194 | /* If the previous instruction is in a variant frag, we |
1195 | can not do the swap. */ | |
1196 | || prev_insn_frag->fr_type == rs_machine_dependent | |
becfe05e ILT |
1197 | /* If the branch reads the condition codes, we don't |
1198 | even try to swap, because in the sequence | |
1199 | ctc1 $X,$31 | |
1200 | INSN | |
1201 | INSN | |
1202 | bc1t LABEL | |
1203 | we can not swap, and I don't feel like handling that | |
1204 | case. */ | |
d8a1c247 KR |
1205 | || (mips_isa < 4 |
1206 | && (pinfo & INSN_READ_COND_CODE)) | |
becfe05e ILT |
1207 | /* We can not swap with an instruction that requires a |
1208 | delay slot, becase the target of the branch might | |
1209 | interfere with that instruction. */ | |
d8a1c247 KR |
1210 | || (mips_isa < 4 |
1211 | && (prev_pinfo | |
1212 | & (INSN_LOAD_COPROC_DELAY | |
1213 | | INSN_COPROC_MOVE_DELAY | |
1214 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1215 | || (! interlocks |
b2b8c24e ILT |
1216 | && (prev_pinfo |
1217 | & (INSN_READ_LO | |
1218 | | INSN_READ_HI))) | |
8358c818 | 1219 | || (mips_isa < 2 |
1aa6938e | 1220 | && (prev_pinfo |
8358c818 ILT |
1221 | & (INSN_LOAD_MEMORY_DELAY |
1222 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1223 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1224 | || (prev_pinfo |
6e8dda9c ILT |
1225 | & (INSN_UNCOND_BRANCH_DELAY |
1226 | | INSN_COND_BRANCH_DELAY | |
1227 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1228 | /* We do not swap with a trap instruction, since it |
1229 | complicates trap handlers to have the trap | |
1230 | instruction be in a delay slot. */ | |
1aa6938e | 1231 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1232 | /* If the branch reads a register that the previous |
1233 | instruction sets, we can not swap. */ | |
1aa6938e | 1234 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1235 | && insn_uses_reg (ip, |
1236 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1237 | & OP_MASK_RT), | |
1238 | 0)) | |
1aa6938e | 1239 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1240 | && insn_uses_reg (ip, |
1241 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1242 | & OP_MASK_RD), | |
1243 | 0)) | |
1849d646 ILT |
1244 | /* If the branch writes a register that the previous |
1245 | instruction sets, we can not swap (we know that | |
1246 | branches write only to RD or to $31). */ | |
1aa6938e ILT |
1247 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
1248 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1249 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1250 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1251 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1252 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1253 | & OP_MASK_RT) | |
1254 | == 31)))) | |
1aa6938e ILT |
1255 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
1256 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1257 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1258 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1259 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1260 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1261 | & OP_MASK_RD) | |
1262 | == 31)))) | |
becfe05e ILT |
1263 | /* If the branch writes a register that the previous |
1264 | instruction reads, we can not swap (we know that | |
1265 | branches only write to RD or to $31). */ | |
1aa6938e | 1266 | || ((pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1267 | && insn_uses_reg (&prev_insn, |
1268 | ((ip->insn_opcode >> OP_SH_RD) | |
1269 | & OP_MASK_RD), | |
1270 | 0)) | |
1aa6938e | 1271 | || ((pinfo & INSN_WRITE_GPR_31) |
becfe05e | 1272 | && insn_uses_reg (&prev_insn, 31, 0)) |
5b63f465 ILT |
1273 | /* If we are generating embedded PIC code, the branch |
1274 | might be expanded into a sequence which uses $at, so | |
1275 | we can't swap with an instruction which reads it. */ | |
1276 | || (mips_pic == EMBEDDED_PIC | |
1277 | && insn_uses_reg (&prev_insn, AT, 0)) | |
becfe05e ILT |
1278 | /* If the previous previous instruction has a load |
1279 | delay, and sets a register that the branch reads, we | |
1280 | can not swap. */ | |
d8a1c247 KR |
1281 | || (mips_isa < 4 |
1282 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) | |
1283 | || (mips_isa < 2 | |
1284 | && (prev_prev_insn.insn_mo->pinfo | |
1285 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1286 | && insn_uses_reg (ip, |
1287 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1288 | & OP_MASK_RT), | |
1289 | 0))) | |
1290 | { | |
1291 | /* We could do even better for unconditional branches to | |
1292 | portions of this object file; we could pick up the | |
1293 | instruction at the destination, put it in the delay | |
1294 | slot, and bump the destination address. */ | |
1295 | emit_nop (); | |
1296 | /* Update the previous insn information. */ | |
1297 | prev_prev_insn = *ip; | |
1298 | prev_insn.insn_mo = &dummy_opcode; | |
1299 | } | |
1300 | else | |
1301 | { | |
1302 | char *prev_f; | |
1303 | char temp[4]; | |
1304 | ||
1305 | /* It looks like we can actually do the swap. */ | |
1306 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1307 | memcpy (temp, prev_f, 4); | |
1308 | memcpy (prev_f, f, 4); | |
1309 | memcpy (f, temp, 4); | |
1310 | if (prev_insn_fixp) | |
1311 | { | |
1312 | prev_insn_fixp->fx_frag = frag_now; | |
1313 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1314 | } | |
1315 | if (fixp) | |
1316 | { | |
1317 | fixp->fx_frag = prev_insn_frag; | |
1318 | fixp->fx_where = prev_insn_where; | |
1319 | } | |
1320 | /* Update the previous insn information; leave prev_insn | |
1321 | unchanged. */ | |
1322 | prev_prev_insn = *ip; | |
1323 | } | |
1324 | prev_insn_is_delay_slot = 1; | |
1325 | ||
1326 | /* If that was an unconditional branch, forget the previous | |
1327 | insn information. */ | |
1aa6938e | 1328 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1329 | { |
1330 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1331 | prev_insn.insn_mo = &dummy_opcode; | |
1332 | } | |
1333 | } | |
1aa6938e | 1334 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1335 | { |
1336 | /* We don't yet optimize a branch likely. What we should do | |
1337 | is look at the target, copy the instruction found there | |
1338 | into the delay slot, and increment the branch to jump to | |
1339 | the next instruction. */ | |
1340 | emit_nop (); | |
1341 | /* Update the previous insn information. */ | |
1342 | prev_prev_insn = *ip; | |
1343 | prev_insn.insn_mo = &dummy_opcode; | |
1344 | } | |
becfe05e | 1345 | else |
670a50eb | 1346 | { |
becfe05e ILT |
1347 | /* Update the previous insn information. */ |
1348 | if (nops > 0) | |
1349 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1350 | else | |
1351 | prev_prev_insn = prev_insn; | |
1352 | prev_insn = *ip; | |
1353 | ||
1354 | /* Any time we see a branch, we always fill the delay slot | |
1355 | immediately; since this insn is not a branch, we know it | |
1356 | is not in a delay slot. */ | |
1357 | prev_insn_is_delay_slot = 0; | |
1358 | } | |
1359 | ||
4e95866e ILT |
1360 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1361 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1362 | prev_insn_frag = frag_now; |
1363 | prev_insn_where = f - frag_now->fr_literal; | |
1364 | prev_insn_fixp = fixp; | |
1365 | prev_insn_valid = 1; | |
1366 | } | |
3d3c5039 | 1367 | |
becfe05e ILT |
1368 | /* We just output an insn, so the next one doesn't have a label. */ |
1369 | insn_label = NULL; | |
1370 | } | |
1371 | ||
1372 | /* This function forgets that there was any previous instruction or | |
1373 | label. */ | |
1374 | ||
1375 | static void | |
1376 | mips_no_prev_insn () | |
1377 | { | |
1378 | prev_insn.insn_mo = &dummy_opcode; | |
1379 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1380 | prev_insn_valid = 0; | |
1381 | prev_insn_is_delay_slot = 0; | |
4e95866e ILT |
1382 | prev_insn_unreordered = 0; |
1383 | prev_prev_insn_unreordered = 0; | |
becfe05e ILT |
1384 | insn_label = NULL; |
1385 | } | |
1386 | ||
1387 | /* This function must be called whenever we turn on noreorder or emit | |
1388 | something other than instructions. It inserts any NOPS which might | |
1389 | be needed by the previous instruction, and clears the information | |
1390 | kept for the previous instructions. */ | |
1391 | ||
1392 | static void | |
1393 | mips_emit_delays () | |
1394 | { | |
1395 | if (! mips_noreorder) | |
1396 | { | |
1397 | int nop; | |
1398 | ||
1399 | nop = 0; | |
d8a1c247 KR |
1400 | if ((mips_isa < 4 |
1401 | && (prev_insn.insn_mo->pinfo | |
1402 | & (INSN_LOAD_COPROC_DELAY | |
1403 | | INSN_COPROC_MOVE_DELAY | |
1404 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1405 | || (! interlocks |
b2b8c24e ILT |
1406 | && (prev_insn.insn_mo->pinfo |
1407 | & (INSN_READ_LO | |
1408 | | INSN_READ_HI))) | |
8358c818 ILT |
1409 | || (mips_isa < 2 |
1410 | && (prev_insn.insn_mo->pinfo | |
1411 | & (INSN_LOAD_MEMORY_DELAY | |
1412 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1413 | { |
1414 | nop = 1; | |
d8a1c247 KR |
1415 | if ((mips_isa < 4 |
1416 | && (prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1417 | || (! interlocks |
b2b8c24e ILT |
1418 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1419 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1420 | emit_nop (); |
1421 | } | |
d8a1c247 KR |
1422 | else if ((mips_isa < 4 |
1423 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1424 | || (! interlocks |
b2b8c24e ILT |
1425 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1426 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1427 | nop = 1; |
1428 | if (nop) | |
670a50eb | 1429 | { |
becfe05e ILT |
1430 | emit_nop (); |
1431 | if (insn_label != NULL) | |
1432 | { | |
1433 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1434 | insn_label->sy_frag = frag_now; | |
604633ae | 1435 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1436 | } |
3d3c5039 ILT |
1437 | } |
1438 | } | |
0221ddf7 ILT |
1439 | |
1440 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1441 | } |
1442 | ||
670a50eb ILT |
1443 | /* Build an instruction created by a macro expansion. This is passed |
1444 | a pointer to the count of instructions created so far, an | |
1445 | expression, the name of the instruction to build, an operand format | |
1446 | string, and corresponding arguments. */ | |
1447 | ||
1dc1e798 | 1448 | #ifdef USE_STDARG |
3d3c5039 | 1449 | static void |
0dd2d296 ILT |
1450 | macro_build (char *place, |
1451 | int *counter, | |
670a50eb | 1452 | expressionS * ep, |
3d3c5039 ILT |
1453 | const char *name, |
1454 | const char *fmt, | |
1455 | ...) | |
1dc1e798 | 1456 | #else |
3d3c5039 | 1457 | static void |
0dd2d296 ILT |
1458 | macro_build (place, counter, ep, name, fmt, va_alist) |
1459 | char *place; | |
3d3c5039 ILT |
1460 | int *counter; |
1461 | expressionS *ep; | |
1462 | const char *name; | |
1463 | const char *fmt; | |
1464 | va_dcl | |
1dc1e798 | 1465 | #endif |
3d3c5039 | 1466 | { |
670a50eb ILT |
1467 | struct mips_cl_insn insn; |
1468 | bfd_reloc_code_real_type r; | |
1469 | va_list args; | |
3d3c5039 | 1470 | |
1dc1e798 | 1471 | #ifdef USE_STDARG |
670a50eb | 1472 | va_start (args, fmt); |
3d3c5039 | 1473 | #else |
670a50eb | 1474 | va_start (args); |
3d3c5039 ILT |
1475 | #endif |
1476 | ||
670a50eb ILT |
1477 | /* |
1478 | * If the macro is about to expand into a second instruction, | |
1479 | * print a warning if needed. We need to pass ip as a parameter | |
1480 | * to generate a better warning message here... | |
1481 | */ | |
0dd2d296 | 1482 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1483 | as_warn ("Macro instruction expanded into multiple instructions"); |
1484 | ||
0dd2d296 ILT |
1485 | if (place == NULL) |
1486 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1487 | |
1488 | r = BFD_RELOC_UNUSED; | |
1489 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1490 | assert (insn.insn_mo); | |
1491 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1492 | ||
9226253a | 1493 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
1494 | || insn.insn_mo->pinfo == INSN_MACRO |
1495 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
1496 | && mips_isa < 2) | |
1497 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
1498 | && mips_isa < 3) | |
1499 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
1500 | && mips_isa < 4) | |
1501 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
1502 | && ! mips_4650) | |
1503 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
1504 | && ! mips_4010) | |
1505 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
1506 | && ! mips_4100)) | |
670a50eb ILT |
1507 | { |
1508 | ++insn.insn_mo; | |
1509 | assert (insn.insn_mo->name); | |
1510 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1511 | } |
670a50eb ILT |
1512 | insn.insn_opcode = insn.insn_mo->match; |
1513 | for (;;) | |
1514 | { | |
1515 | switch (*fmt++) | |
1516 | { | |
3d3c5039 | 1517 | case '\0': |
670a50eb | 1518 | break; |
3d3c5039 ILT |
1519 | |
1520 | case ',': | |
1521 | case '(': | |
1522 | case ')': | |
670a50eb | 1523 | continue; |
3d3c5039 ILT |
1524 | |
1525 | case 't': | |
1526 | case 'w': | |
918692a5 | 1527 | case 'E': |
670a50eb ILT |
1528 | insn.insn_opcode |= va_arg (args, int) << 16; |
1529 | continue; | |
3d3c5039 ILT |
1530 | |
1531 | case 'c': | |
1532 | case 'T': | |
1533 | case 'W': | |
670a50eb ILT |
1534 | insn.insn_opcode |= va_arg (args, int) << 16; |
1535 | continue; | |
3d3c5039 ILT |
1536 | |
1537 | case 'd': | |
918692a5 | 1538 | case 'G': |
670a50eb ILT |
1539 | insn.insn_opcode |= va_arg (args, int) << 11; |
1540 | continue; | |
3d3c5039 ILT |
1541 | |
1542 | case 'V': | |
1543 | case 'S': | |
670a50eb ILT |
1544 | insn.insn_opcode |= va_arg (args, int) << 11; |
1545 | continue; | |
3d3c5039 | 1546 | |
ff3a5c18 ILT |
1547 | case 'z': |
1548 | continue; | |
1549 | ||
3d3c5039 | 1550 | case '<': |
670a50eb ILT |
1551 | insn.insn_opcode |= va_arg (args, int) << 6; |
1552 | continue; | |
3d3c5039 ILT |
1553 | |
1554 | case 'D': | |
670a50eb ILT |
1555 | insn.insn_opcode |= va_arg (args, int) << 6; |
1556 | continue; | |
3d3c5039 | 1557 | |
918692a5 ILT |
1558 | case 'B': |
1559 | insn.insn_opcode |= va_arg (args, int) << 6; | |
1560 | continue; | |
1561 | ||
3d3c5039 ILT |
1562 | case 'b': |
1563 | case 's': | |
1564 | case 'r': | |
1565 | case 'v': | |
670a50eb ILT |
1566 | insn.insn_opcode |= va_arg (args, int) << 21; |
1567 | continue; | |
3d3c5039 ILT |
1568 | |
1569 | case 'i': | |
1570 | case 'j': | |
1571 | case 'o': | |
9226253a | 1572 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
1573 | assert (r == BFD_RELOC_MIPS_GPREL |
1574 | || r == BFD_RELOC_MIPS_LITERAL | |
1575 | || r == BFD_RELOC_LO16 | |
1576 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 1577 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
1578 | || r == BFD_RELOC_MIPS_GOT_LO16 |
1579 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
1580 | || (ep->X_op == O_subtract |
1581 | && now_seg == text_section | |
ecd4ca1c | 1582 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 1583 | continue; |
3d3c5039 | 1584 | |
6e8dda9c | 1585 | case 'u': |
ecd4ca1c ILT |
1586 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
1587 | assert (ep != NULL | |
1588 | && (ep->X_op == O_constant | |
1589 | || (ep->X_op == O_symbol | |
1590 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
1591 | || r == BFD_RELOC_HI16 |
1592 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
1593 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
1594 | || (ep->X_op == O_subtract |
1595 | && now_seg == text_section | |
ecd4ca1c ILT |
1596 | && r == BFD_RELOC_PCREL_HI16_S))); |
1597 | if (ep->X_op == O_constant) | |
1598 | { | |
1599 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
1600 | ep = NULL; | |
1601 | r = BFD_RELOC_UNUSED; | |
1602 | } | |
6e8dda9c ILT |
1603 | continue; |
1604 | ||
3d3c5039 | 1605 | case 'p': |
670a50eb ILT |
1606 | assert (ep != NULL); |
1607 | /* | |
1608 | * This allows macro() to pass an immediate expression for | |
1609 | * creating short branches without creating a symbol. | |
1610 | * Note that the expression still might come from the assembly | |
1611 | * input, in which case the value is not checked for range nor | |
1612 | * is a relocation entry generated (yuck). | |
1613 | */ | |
5ac34ac3 | 1614 | if (ep->X_op == O_constant) |
670a50eb ILT |
1615 | { |
1616 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
1617 | ep = NULL; | |
1618 | } | |
1619 | else | |
1620 | r = BFD_RELOC_16_PCREL_S2; | |
1621 | continue; | |
3d3c5039 | 1622 | |
9226253a ILT |
1623 | case 'a': |
1624 | assert (ep != NULL); | |
1625 | r = BFD_RELOC_MIPS_JMP; | |
1626 | continue; | |
1627 | ||
3d3c5039 | 1628 | default: |
670a50eb | 1629 | internalError (); |
3d3c5039 | 1630 | } |
670a50eb | 1631 | break; |
3d3c5039 | 1632 | } |
670a50eb ILT |
1633 | va_end (args); |
1634 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1635 | ||
0dd2d296 | 1636 | append_insn (place, &insn, ep, r); |
3d3c5039 ILT |
1637 | } |
1638 | ||
1639 | /* | |
1640 | * Generate a "lui" instruction. | |
1641 | */ | |
1642 | static void | |
0dd2d296 ILT |
1643 | macro_build_lui (place, counter, ep, regnum) |
1644 | char *place; | |
3d3c5039 ILT |
1645 | int *counter; |
1646 | expressionS *ep; | |
1647 | int regnum; | |
1648 | { | |
670a50eb ILT |
1649 | expressionS high_expr; |
1650 | struct mips_cl_insn insn; | |
1651 | bfd_reloc_code_real_type r; | |
1652 | CONST char *name = "lui"; | |
1653 | CONST char *fmt = "t,u"; | |
1654 | ||
0dd2d296 ILT |
1655 | if (place == NULL) |
1656 | high_expr = *ep; | |
1657 | else | |
1658 | { | |
1659 | high_expr.X_op = O_constant; | |
fb251650 | 1660 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 1661 | } |
670a50eb | 1662 | |
5ac34ac3 | 1663 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
1664 | { |
1665 | /* we can compute the instruction now without a relocation entry */ | |
1666 | if (high_expr.X_add_number & 0x8000) | |
1667 | high_expr.X_add_number += 0x10000; | |
1668 | high_expr.X_add_number = | |
1669 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
1670 | r = BFD_RELOC_UNUSED; | |
1671 | } | |
1672 | else | |
0dd2d296 ILT |
1673 | { |
1674 | assert (ep->X_op == O_symbol); | |
1675 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 1676 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
1677 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
1678 | r = BFD_RELOC_HI16_S; | |
1679 | } | |
670a50eb ILT |
1680 | |
1681 | /* | |
1682 | * If the macro is about to expand into a second instruction, | |
1683 | * print a warning if needed. We need to pass ip as a parameter | |
1684 | * to generate a better warning message here... | |
1685 | */ | |
0dd2d296 | 1686 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1687 | as_warn ("Macro instruction expanded into multiple instructions"); |
1688 | ||
0dd2d296 ILT |
1689 | if (place == NULL) |
1690 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1691 | |
1692 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1693 | assert (insn.insn_mo); | |
1694 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1695 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
1696 | ||
0dd2d296 | 1697 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
1698 | if (r == BFD_RELOC_UNUSED) |
1699 | { | |
1700 | insn.insn_opcode |= high_expr.X_add_number; | |
0dd2d296 | 1701 | append_insn (place, &insn, NULL, r); |
670a50eb ILT |
1702 | } |
1703 | else | |
0dd2d296 | 1704 | append_insn (place, &insn, &high_expr, r); |
3d3c5039 ILT |
1705 | } |
1706 | ||
1707 | /* set_at() | |
1708 | * Generates code to set the $at register to true (one) | |
1709 | * if reg is less than the immediate expression. | |
1710 | */ | |
1711 | static void | |
6e8dda9c | 1712 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
1713 | int *counter; |
1714 | int reg; | |
6e8dda9c | 1715 | int unsignedp; |
3d3c5039 | 1716 | { |
6e8dda9c | 1717 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 1718 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 1719 | unsignedp ? "sltiu" : "slti", |
9226253a | 1720 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 1721 | else |
670a50eb | 1722 | { |
d8a1c247 | 1723 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 1724 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
1725 | unsignedp ? "sltu" : "slt", |
1726 | "d,v,t", AT, reg, AT); | |
670a50eb | 1727 | } |
3d3c5039 ILT |
1728 | } |
1729 | ||
6e8dda9c | 1730 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
1731 | |
1732 | static void | |
19ed8960 | 1733 | check_absolute_expr (ip, ex) |
3d3c5039 | 1734 | struct mips_cl_insn *ip; |
19ed8960 | 1735 | expressionS *ex; |
3d3c5039 | 1736 | { |
19ed8960 | 1737 | if (ex->X_op != O_constant) |
670a50eb | 1738 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
1739 | } |
1740 | ||
1741 | /* load_register() | |
1742 | * This routine generates the least number of instructions neccessary to load | |
1743 | * an absolute expression value into a register. | |
1744 | */ | |
1745 | static void | |
d8a1c247 | 1746 | load_register (counter, reg, ep, dbl) |
670a50eb | 1747 | int *counter; |
670a50eb ILT |
1748 | int reg; |
1749 | expressionS *ep; | |
d8a1c247 | 1750 | int dbl; |
3d3c5039 | 1751 | { |
d8a1c247 | 1752 | int shift, freg; |
7811254c | 1753 | expressionS hi32, lo32, tmp; |
847a01cd ILT |
1754 | |
1755 | if (ep->X_op != O_big) | |
6e8dda9c | 1756 | { |
847a01cd | 1757 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
1758 | if (ep->X_add_number < 0x8000 |
1759 | && (ep->X_add_number >= 0 | |
1760 | || (ep->X_add_number >= -0x8000 | |
1761 | && (! dbl | |
1762 | || ! ep->X_unsigned | |
1763 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
1764 | { |
1765 | /* We can handle 16 bit signed values with an addiu to | |
1766 | $zero. No need to ever use daddiu here, since $zero and | |
1767 | the result are always correct in 32 bit mode. */ | |
1768 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
1769 | (int) BFD_RELOC_LO16); | |
1770 | return; | |
1771 | } | |
1772 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
1773 | { | |
1774 | /* We can handle 16 bit unsigned values with an ori to | |
1775 | $zero. */ | |
1776 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
1777 | (int) BFD_RELOC_LO16); | |
1778 | return; | |
1779 | } | |
7811254c ILT |
1780 | else if (((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
1781 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
1782 | == ~ (offsetT) 0x7fffffff)) | |
d8a1c247 | 1783 | && (! dbl |
6b67ed78 | 1784 | || ! ep->X_unsigned |
7811254c ILT |
1785 | || sizeof (ep->X_add_number) > 4 |
1786 | || (ep->X_add_number & 0x80000000) == 0)) | |
847a01cd ILT |
1787 | { |
1788 | /* 32 bit values require an lui. */ | |
1789 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
1790 | (int) BFD_RELOC_HI16); | |
1791 | if ((ep->X_add_number & 0xffff) != 0) | |
1792 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
1793 | (int) BFD_RELOC_LO16); | |
1794 | return; | |
1795 | } | |
7811254c ILT |
1796 | else |
1797 | { | |
1798 | /* 32 bit value with high bit set being loaded into a 64 bit | |
1799 | register. We can't use lui, because that would | |
1800 | incorrectly set the 32 high bits. */ | |
1801 | generic_bignum[3] = 0; | |
1802 | generic_bignum[2] = 0; | |
1803 | generic_bignum[1] = (ep->X_add_number >> 16) & 0xffff; | |
1804 | generic_bignum[0] = ep->X_add_number & 0xffff; | |
1805 | tmp.X_op = O_big; | |
1806 | tmp.X_add_number = 4; | |
1807 | ep = &tmp; | |
1808 | } | |
6e8dda9c | 1809 | } |
847a01cd ILT |
1810 | |
1811 | /* The value is larger than 32 bits. */ | |
1812 | ||
1813 | if (mips_isa < 3) | |
670a50eb | 1814 | { |
6e8dda9c | 1815 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 1816 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 1817 | (int) BFD_RELOC_LO16); |
847a01cd | 1818 | return; |
6e8dda9c | 1819 | } |
6e8dda9c | 1820 | |
847a01cd ILT |
1821 | if (ep->X_op != O_big) |
1822 | { | |
6e8dda9c ILT |
1823 | hi32 = *ep; |
1824 | shift = 32; | |
1825 | hi32.X_add_number >>= shift; | |
1826 | hi32.X_add_number &= 0xffffffff; | |
1827 | if ((hi32.X_add_number & 0x80000000) != 0) | |
1828 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
6e8dda9c ILT |
1829 | lo32 = *ep; |
1830 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 1831 | } |
847a01cd ILT |
1832 | else |
1833 | { | |
1834 | assert (ep->X_add_number > 2); | |
1835 | if (ep->X_add_number == 3) | |
1836 | generic_bignum[3] = 0; | |
1837 | else if (ep->X_add_number > 4) | |
1838 | as_bad ("Number larger than 64 bits"); | |
1839 | lo32.X_op = O_constant; | |
1840 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
1841 | hi32.X_op = O_constant; | |
1842 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
1843 | } | |
1844 | ||
d8a1c247 KR |
1845 | if (hi32.X_add_number == 0) |
1846 | freg = 0; | |
1847 | else | |
1848 | { | |
fb251650 ILT |
1849 | if (hi32.X_add_number == 0xffffffff) |
1850 | { | |
1851 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
1852 | { | |
1853 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, | |
1854 | (int) BFD_RELOC_LO16); | |
1855 | return; | |
1856 | } | |
1857 | if (lo32.X_add_number & 0x80000000) | |
1858 | { | |
1859 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
1860 | (int) BFD_RELOC_HI16); | |
1861 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, | |
1862 | (int) BFD_RELOC_LO16); | |
1863 | return; | |
1864 | } | |
1865 | } | |
d8a1c247 KR |
1866 | load_register (counter, reg, &hi32, 0); |
1867 | freg = reg; | |
1868 | } | |
847a01cd | 1869 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
1870 | { |
1871 | if (freg != 0) | |
1872 | { | |
1873 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
1874 | freg, 0); | |
1875 | freg = reg; | |
1876 | } | |
1877 | } | |
847a01cd ILT |
1878 | else |
1879 | { | |
1880 | expressionS mid16; | |
1881 | ||
fb251650 ILT |
1882 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
1883 | { | |
1884 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
1885 | (int) BFD_RELOC_HI16); | |
1886 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
1887 | reg, 32); | |
1888 | return; | |
1889 | } | |
1890 | ||
d8a1c247 KR |
1891 | if (freg != 0) |
1892 | { | |
1893 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
1894 | freg, 16); | |
1895 | freg = reg; | |
1896 | } | |
847a01cd ILT |
1897 | mid16 = lo32; |
1898 | mid16.X_add_number >>= 16; | |
1899 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 1900 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
1901 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
1902 | reg, 16); | |
d8a1c247 | 1903 | freg = reg; |
847a01cd ILT |
1904 | } |
1905 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 1906 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 1907 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
1908 | } |
1909 | ||
0dd2d296 ILT |
1910 | /* Load an address into a register. */ |
1911 | ||
1912 | static void | |
1913 | load_address (counter, reg, ep) | |
1914 | int *counter; | |
1915 | int reg; | |
1916 | expressionS *ep; | |
1917 | { | |
1918 | char *p; | |
1919 | ||
1920 | if (ep->X_op != O_constant | |
1921 | && ep->X_op != O_symbol) | |
1922 | { | |
1923 | as_bad ("expression too complex"); | |
1924 | ep->X_op = O_constant; | |
1925 | } | |
1926 | ||
1927 | if (ep->X_op == O_constant) | |
d9aba805 | 1928 | { |
d8a1c247 | 1929 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
1930 | return; |
1931 | } | |
1932 | ||
1933 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
1934 | { |
1935 | /* If this is a reference to a GP relative symbol, we want | |
1936 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1937 | Otherwise we want | |
04cb3372 | 1938 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
1939 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
1940 | If we have an addend, we always use the latter form. */ | |
d8a1c247 | 1941 | if (ep->X_add_number != 0 || nopic_need_relax (ep->X_add_symbol)) |
0dd2d296 ILT |
1942 | p = NULL; |
1943 | else | |
1944 | { | |
8ea7f4e8 | 1945 | frag_grow (20); |
0dd2d296 ILT |
1946 | macro_build ((char *) NULL, counter, ep, |
1947 | mips_isa < 3 ? "addiu" : "daddiu", | |
1948 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1949 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 1950 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
1951 | ep->X_add_symbol, (long) 0, (char *) NULL); |
1952 | } | |
1953 | macro_build_lui (p, counter, ep, reg); | |
1954 | if (p != NULL) | |
1955 | p += 4; | |
1956 | macro_build (p, counter, ep, | |
1957 | mips_isa < 3 ? "addiu" : "daddiu", | |
1958 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1959 | } | |
fb251650 | 1960 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
1961 | { |
1962 | expressionS ex; | |
1963 | ||
1964 | /* If this is a reference to an external symbol, we want | |
1965 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1966 | Otherwise we want | |
1967 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1968 | nop | |
1969 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 1970 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
1971 | ex.X_add_number = ep->X_add_number; |
1972 | ep->X_add_number = 0; | |
8ea7f4e8 | 1973 | frag_grow (20); |
0dd2d296 ILT |
1974 | macro_build ((char *) NULL, counter, ep, |
1975 | mips_isa < 3 ? "lw" : "ld", | |
1976 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
1977 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
1978 | p = frag_var (rs_machine_dependent, 4, 0, | |
1979 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
1980 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1981 | macro_build (p, counter, ep, | |
1982 | mips_isa < 3 ? "addiu" : "daddiu", | |
1983 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1984 | if (ex.X_add_number != 0) | |
1985 | { | |
1986 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
1987 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
1988 | ex.X_op = O_constant; | |
fb251650 ILT |
1989 | macro_build ((char *) NULL, counter, &ex, |
1990 | mips_isa < 3 ? "addiu" : "daddiu", | |
1991 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1992 | } | |
1993 | } | |
1994 | else if (mips_pic == SVR4_PIC) | |
1995 | { | |
1996 | expressionS ex; | |
1997 | int off; | |
1998 | ||
1999 | /* This is the large GOT case. If this is a reference to an | |
2000 | external symbol, we want | |
2001 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2002 | addu $reg,$reg,$gp | |
2003 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2004 | Otherwise, for a reference to a local symbol, we want | |
2005 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2006 | nop | |
2007 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2008 | If there is a constant, it must be added in after. */ | |
2009 | ex.X_add_number = ep->X_add_number; | |
2010 | ep->X_add_number = 0; | |
2011 | if (reg_needs_delay (GP)) | |
2012 | off = 4; | |
2013 | else | |
2014 | off = 0; | |
2015 | frag_grow (32); | |
2016 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2017 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2018 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2019 | mips_isa < 3 ? "addu" : "daddu", | |
2020 | "d,v,t", reg, reg, GP); | |
2021 | macro_build ((char *) NULL, counter, ep, | |
2022 | mips_isa < 3 ? "lw" : "ld", | |
2023 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2024 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2025 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2026 | mips_warn_about_macros), | |
2027 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2028 | if (off > 0) | |
2029 | { | |
2030 | /* We need a nop before loading from $gp. This special | |
2031 | check is required because the lui which starts the main | |
2032 | instruction stream does not refer to $gp, and so will not | |
2033 | insert the nop which may be required. */ | |
2034 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2035 | p += 4; | |
2036 | } | |
2037 | macro_build (p, counter, ep, | |
2038 | mips_isa < 3 ? "lw" : "ld", | |
2039 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2040 | p += 4; | |
2041 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2042 | p += 4; | |
2043 | macro_build (p, counter, ep, | |
2044 | mips_isa < 3 ? "addiu" : "daddiu", | |
2045 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2046 | if (ex.X_add_number != 0) | |
2047 | { | |
2048 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2049 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2050 | ex.X_op = O_constant; | |
2051 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2052 | mips_isa < 3 ? "addiu" : "daddiu", |
2053 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2054 | } | |
d9aba805 ILT |
2055 | } |
2056 | else if (mips_pic == EMBEDDED_PIC) | |
2057 | { | |
2058 | /* We always do | |
2059 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2060 | */ | |
2061 | macro_build ((char *) NULL, counter, ep, | |
2062 | mips_isa < 3 ? "addiu" : "daddiu", | |
2063 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2064 | } | |
2065 | else | |
2066 | abort (); | |
0dd2d296 ILT |
2067 | } |
2068 | ||
3d3c5039 ILT |
2069 | /* |
2070 | * Build macros | |
2071 | * This routine implements the seemingly endless macro or synthesized | |
2072 | * instructions and addressing modes in the mips assembly language. Many | |
2073 | * of these macros are simple and are similar to each other. These could | |
2074 | * probably be handled by some kind of table or grammer aproach instead of | |
2075 | * this verbose method. Others are not simple macros but are more like | |
2076 | * optimizing code generation. | |
2077 | * One interesting optimization is when several store macros appear | |
2078 | * consecutivly that would load AT with the upper half of the same address. | |
2079 | * The ensuing load upper instructions are ommited. This implies some kind | |
2080 | * of global optimization. We currently only optimize within a single macro. | |
2081 | * For many of the load and store macros if the address is specified as a | |
2082 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2083 | * first load register 'at' with zero and use it as the base register. The | |
2084 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2085 | * we're missing. | |
2086 | */ | |
2087 | static void | |
2088 | macro (ip) | |
2089 | struct mips_cl_insn *ip; | |
2090 | { | |
670a50eb ILT |
2091 | register int treg, sreg, dreg, breg; |
2092 | int tempreg; | |
2093 | int mask; | |
2094 | int icnt = 0; | |
2095 | int used_at; | |
670a50eb ILT |
2096 | expressionS expr1; |
2097 | const char *s; | |
8358c818 | 2098 | const char *s2; |
670a50eb | 2099 | const char *fmt; |
8358c818 ILT |
2100 | int likely = 0; |
2101 | int dbl = 0; | |
2102 | int coproc = 0; | |
b2b8c24e | 2103 | int lr = 0; |
6e8dda9c | 2104 | offsetT maxnum; |
adcf2b9d | 2105 | int off; |
9226253a | 2106 | bfd_reloc_code_real_type r; |
0dd2d296 | 2107 | char *p; |
55933a58 | 2108 | int hold_mips_optimize; |
670a50eb ILT |
2109 | |
2110 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
2111 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
2112 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
2113 | mask = ip->insn_mo->mask; | |
2114 | ||
5ac34ac3 ILT |
2115 | expr1.X_op = O_constant; |
2116 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
2117 | expr1.X_add_symbol = NULL; |
2118 | expr1.X_add_number = 1; | |
2119 | ||
2120 | switch (mask) | |
2121 | { | |
6e8dda9c ILT |
2122 | case M_DABS: |
2123 | dbl = 1; | |
3d3c5039 | 2124 | case M_ABS: |
6e8dda9c ILT |
2125 | /* bgez $a0,.+12 |
2126 | move v0,$a0 | |
2127 | sub v0,$zero,$a0 | |
2128 | */ | |
3d3c5039 | 2129 | |
becfe05e ILT |
2130 | mips_emit_delays (); |
2131 | ++mips_noreorder; | |
0dd2d296 | 2132 | mips_any_noreorder = 1; |
3d3c5039 | 2133 | |
670a50eb | 2134 | expr1.X_add_number = 8; |
0dd2d296 | 2135 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 2136 | if (dreg == sreg) |
0dd2d296 | 2137 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 2138 | else |
0dd2d296 ILT |
2139 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
2140 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
2141 | dbl ? "dsub" : "sub", |
2142 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 2143 | |
becfe05e | 2144 | --mips_noreorder; |
670a50eb | 2145 | return; |
3d3c5039 ILT |
2146 | |
2147 | case M_ADD_I: | |
8358c818 ILT |
2148 | s = "addi"; |
2149 | s2 = "add"; | |
2150 | goto do_addi; | |
3d3c5039 | 2151 | case M_ADDU_I: |
8358c818 ILT |
2152 | s = "addiu"; |
2153 | s2 = "addu"; | |
2154 | goto do_addi; | |
2155 | case M_DADD_I: | |
6e8dda9c | 2156 | dbl = 1; |
8358c818 ILT |
2157 | s = "daddi"; |
2158 | s2 = "dadd"; | |
2159 | goto do_addi; | |
2160 | case M_DADDU_I: | |
6e8dda9c | 2161 | dbl = 1; |
8358c818 ILT |
2162 | s = "daddiu"; |
2163 | s2 = "daddu"; | |
2164 | do_addi: | |
6e8dda9c | 2165 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 2166 | { |
0dd2d296 | 2167 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 2168 | (int) BFD_RELOC_LO16); |
670a50eb | 2169 | return; |
3d3c5039 | 2170 | } |
d8a1c247 | 2171 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 2172 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2173 | break; |
3d3c5039 ILT |
2174 | |
2175 | case M_AND_I: | |
6e8dda9c ILT |
2176 | s = "andi"; |
2177 | s2 = "and"; | |
2178 | goto do_bit; | |
3d3c5039 | 2179 | case M_OR_I: |
6e8dda9c ILT |
2180 | s = "ori"; |
2181 | s2 = "or"; | |
2182 | goto do_bit; | |
3d3c5039 | 2183 | case M_NOR_I: |
6e8dda9c ILT |
2184 | s = ""; |
2185 | s2 = "nor"; | |
2186 | goto do_bit; | |
3d3c5039 | 2187 | case M_XOR_I: |
6e8dda9c ILT |
2188 | s = "xori"; |
2189 | s2 = "xor"; | |
2190 | do_bit: | |
2191 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 2192 | { |
6e8dda9c | 2193 | if (mask != M_NOR_I) |
0dd2d296 ILT |
2194 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
2195 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 2196 | else |
670a50eb | 2197 | { |
0dd2d296 ILT |
2198 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
2199 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 2200 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 2201 | treg, treg, 0); |
3d3c5039 | 2202 | } |
6e8dda9c | 2203 | return; |
3d3c5039 | 2204 | } |
6e8dda9c | 2205 | |
d8a1c247 | 2206 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2207 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 2208 | break; |
3d3c5039 ILT |
2209 | |
2210 | case M_BEQ_I: | |
8358c818 ILT |
2211 | s = "beq"; |
2212 | goto beq_i; | |
2213 | case M_BEQL_I: | |
2214 | s = "beql"; | |
2215 | likely = 1; | |
2216 | goto beq_i; | |
3d3c5039 | 2217 | case M_BNE_I: |
8358c818 ILT |
2218 | s = "bne"; |
2219 | goto beq_i; | |
2220 | case M_BNEL_I: | |
2221 | s = "bnel"; | |
2222 | likely = 1; | |
2223 | beq_i: | |
670a50eb ILT |
2224 | if (imm_expr.X_add_number == 0) |
2225 | { | |
0dd2d296 ILT |
2226 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
2227 | 0); | |
670a50eb ILT |
2228 | return; |
2229 | } | |
d8a1c247 | 2230 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 2231 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 2232 | break; |
3d3c5039 | 2233 | |
8358c818 ILT |
2234 | case M_BGEL: |
2235 | likely = 1; | |
3d3c5039 | 2236 | case M_BGE: |
670a50eb ILT |
2237 | if (treg == 0) |
2238 | { | |
0dd2d296 | 2239 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2240 | likely ? "bgezl" : "bgez", |
2241 | "s,p", sreg); | |
670a50eb | 2242 | return; |
3d3c5039 | 2243 | } |
9a7d824a ILT |
2244 | if (sreg == 0) |
2245 | { | |
0dd2d296 | 2246 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2247 | likely ? "blezl" : "blez", |
2248 | "s,p", treg); | |
9a7d824a ILT |
2249 | return; |
2250 | } | |
0dd2d296 ILT |
2251 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2252 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2253 | likely ? "beql" : "beq", |
2254 | "s,t,p", AT, 0); | |
670a50eb | 2255 | break; |
3d3c5039 | 2256 | |
8358c818 ILT |
2257 | case M_BGTL_I: |
2258 | likely = 1; | |
3d3c5039 | 2259 | case M_BGT_I: |
9a7d824a | 2260 | /* check for > max integer */ |
6e8dda9c ILT |
2261 | maxnum = 0x7fffffff; |
2262 | if (mips_isa >= 3) | |
2263 | { | |
2264 | maxnum <<= 16; | |
2265 | maxnum |= 0xffff; | |
2266 | maxnum <<= 16; | |
2267 | maxnum |= 0xffff; | |
2268 | } | |
7b777690 ILT |
2269 | if (imm_expr.X_add_number >= maxnum |
2270 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2271 | { |
2272 | do_false: | |
2273 | /* result is always false */ | |
8358c818 ILT |
2274 | if (! likely) |
2275 | { | |
2276 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 2277 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
2278 | } |
2279 | else | |
2280 | { | |
2281 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
2282 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
2283 | "s,t,p", 0, 0); | |
8358c818 | 2284 | } |
9a7d824a ILT |
2285 | return; |
2286 | } | |
670a50eb ILT |
2287 | imm_expr.X_add_number++; |
2288 | /* FALLTHROUGH */ | |
3d3c5039 | 2289 | case M_BGE_I: |
8358c818 ILT |
2290 | case M_BGEL_I: |
2291 | if (mask == M_BGEL_I) | |
2292 | likely = 1; | |
670a50eb ILT |
2293 | if (imm_expr.X_add_number == 0) |
2294 | { | |
0dd2d296 | 2295 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2296 | likely ? "bgezl" : "bgez", |
2297 | "s,p", sreg); | |
670a50eb | 2298 | return; |
3d3c5039 | 2299 | } |
670a50eb ILT |
2300 | if (imm_expr.X_add_number == 1) |
2301 | { | |
0dd2d296 | 2302 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2303 | likely ? "bgtzl" : "bgtz", |
2304 | "s,p", sreg); | |
670a50eb | 2305 | return; |
3d3c5039 | 2306 | } |
6e8dda9c ILT |
2307 | maxnum = 0x7fffffff; |
2308 | if (mips_isa >= 3) | |
2309 | { | |
2310 | maxnum <<= 16; | |
2311 | maxnum |= 0xffff; | |
2312 | maxnum <<= 16; | |
2313 | maxnum |= 0xffff; | |
2314 | } | |
2315 | maxnum = - maxnum - 1; | |
7b777690 ILT |
2316 | if (imm_expr.X_add_number <= maxnum |
2317 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2318 | { |
2319 | do_true: | |
2320 | /* result is always true */ | |
2321 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 2322 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
2323 | return; |
2324 | } | |
6e8dda9c | 2325 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2326 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2327 | likely ? "beql" : "beq", |
2328 | "s,t,p", AT, 0); | |
670a50eb | 2329 | break; |
3d3c5039 | 2330 | |
8358c818 ILT |
2331 | case M_BGEUL: |
2332 | likely = 1; | |
3d3c5039 | 2333 | case M_BGEU: |
670a50eb | 2334 | if (treg == 0) |
9a7d824a ILT |
2335 | goto do_true; |
2336 | if (sreg == 0) | |
670a50eb | 2337 | { |
0dd2d296 | 2338 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2339 | likely ? "beql" : "beq", |
2340 | "s,t,p", 0, treg); | |
670a50eb | 2341 | return; |
3d3c5039 | 2342 | } |
0dd2d296 ILT |
2343 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2344 | treg); | |
2345 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2346 | likely ? "beql" : "beq", |
2347 | "s,t,p", AT, 0); | |
670a50eb | 2348 | break; |
3d3c5039 | 2349 | |
8358c818 ILT |
2350 | case M_BGTUL_I: |
2351 | likely = 1; | |
9a7d824a | 2352 | case M_BGTU_I: |
6e8dda9c | 2353 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2354 | goto do_false; |
2355 | imm_expr.X_add_number++; | |
2356 | /* FALLTHROUGH */ | |
3d3c5039 | 2357 | case M_BGEU_I: |
8358c818 ILT |
2358 | case M_BGEUL_I: |
2359 | if (mask == M_BGEUL_I) | |
2360 | likely = 1; | |
670a50eb | 2361 | if (imm_expr.X_add_number == 0) |
9a7d824a | 2362 | goto do_true; |
670a50eb ILT |
2363 | if (imm_expr.X_add_number == 1) |
2364 | { | |
0dd2d296 | 2365 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2366 | likely ? "bnel" : "bne", |
2367 | "s,t,p", sreg, 0); | |
670a50eb | 2368 | return; |
3d3c5039 | 2369 | } |
6e8dda9c | 2370 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2371 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2372 | likely ? "beql" : "beq", |
2373 | "s,t,p", AT, 0); | |
670a50eb | 2374 | break; |
3d3c5039 | 2375 | |
8358c818 ILT |
2376 | case M_BGTL: |
2377 | likely = 1; | |
3d3c5039 | 2378 | case M_BGT: |
670a50eb ILT |
2379 | if (treg == 0) |
2380 | { | |
0dd2d296 | 2381 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2382 | likely ? "bgtzl" : "bgtz", |
2383 | "s,p", sreg); | |
670a50eb | 2384 | return; |
3d3c5039 | 2385 | } |
9a7d824a ILT |
2386 | if (sreg == 0) |
2387 | { | |
0dd2d296 | 2388 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2389 | likely ? "bltzl" : "bltz", |
2390 | "s,p", treg); | |
9a7d824a ILT |
2391 | return; |
2392 | } | |
0dd2d296 ILT |
2393 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2394 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2395 | likely ? "bnel" : "bne", |
2396 | "s,t,p", AT, 0); | |
670a50eb | 2397 | break; |
3d3c5039 | 2398 | |
8358c818 ILT |
2399 | case M_BGTUL: |
2400 | likely = 1; | |
3d3c5039 | 2401 | case M_BGTU: |
670a50eb ILT |
2402 | if (treg == 0) |
2403 | { | |
0dd2d296 | 2404 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2405 | likely ? "bnel" : "bne", |
2406 | "s,t,p", sreg, 0); | |
670a50eb | 2407 | return; |
3d3c5039 | 2408 | } |
9a7d824a ILT |
2409 | if (sreg == 0) |
2410 | goto do_false; | |
0dd2d296 ILT |
2411 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2412 | sreg); | |
2413 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2414 | likely ? "bnel" : "bne", |
2415 | "s,t,p", AT, 0); | |
670a50eb | 2416 | break; |
3d3c5039 | 2417 | |
8358c818 ILT |
2418 | case M_BLEL: |
2419 | likely = 1; | |
3d3c5039 | 2420 | case M_BLE: |
670a50eb ILT |
2421 | if (treg == 0) |
2422 | { | |
0dd2d296 | 2423 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2424 | likely ? "blezl" : "blez", |
2425 | "s,p", sreg); | |
670a50eb ILT |
2426 | return; |
2427 | } | |
9a7d824a ILT |
2428 | if (sreg == 0) |
2429 | { | |
0dd2d296 | 2430 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2431 | likely ? "bgezl" : "bgez", |
2432 | "s,p", treg); | |
9a7d824a ILT |
2433 | return; |
2434 | } | |
0dd2d296 ILT |
2435 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2436 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2437 | likely ? "beql" : "beq", |
2438 | "s,t,p", AT, 0); | |
670a50eb | 2439 | break; |
3d3c5039 | 2440 | |
8358c818 ILT |
2441 | case M_BLEL_I: |
2442 | likely = 1; | |
3d3c5039 | 2443 | case M_BLE_I: |
6e8dda9c ILT |
2444 | maxnum = 0x7fffffff; |
2445 | if (mips_isa >= 3) | |
2446 | { | |
2447 | maxnum <<= 16; | |
2448 | maxnum |= 0xffff; | |
2449 | maxnum <<= 16; | |
2450 | maxnum |= 0xffff; | |
2451 | } | |
7b777690 ILT |
2452 | if (imm_expr.X_add_number >= maxnum |
2453 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2454 | goto do_true; |
2455 | imm_expr.X_add_number++; | |
2456 | /* FALLTHROUGH */ | |
9a7d824a | 2457 | case M_BLT_I: |
8358c818 ILT |
2458 | case M_BLTL_I: |
2459 | if (mask == M_BLTL_I) | |
2460 | likely = 1; | |
670a50eb ILT |
2461 | if (imm_expr.X_add_number == 0) |
2462 | { | |
0dd2d296 | 2463 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2464 | likely ? "bltzl" : "bltz", |
2465 | "s,p", sreg); | |
670a50eb ILT |
2466 | return; |
2467 | } | |
9a7d824a | 2468 | if (imm_expr.X_add_number == 1) |
670a50eb | 2469 | { |
0dd2d296 | 2470 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2471 | likely ? "blezl" : "blez", |
2472 | "s,p", sreg); | |
670a50eb ILT |
2473 | return; |
2474 | } | |
6e8dda9c | 2475 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2476 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2477 | likely ? "bnel" : "bne", |
2478 | "s,t,p", AT, 0); | |
670a50eb | 2479 | break; |
3d3c5039 | 2480 | |
8358c818 ILT |
2481 | case M_BLEUL: |
2482 | likely = 1; | |
3d3c5039 | 2483 | case M_BLEU: |
670a50eb ILT |
2484 | if (treg == 0) |
2485 | { | |
0dd2d296 | 2486 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2487 | likely ? "beql" : "beq", |
2488 | "s,t,p", sreg, 0); | |
670a50eb | 2489 | return; |
3d3c5039 | 2490 | } |
9a7d824a ILT |
2491 | if (sreg == 0) |
2492 | goto do_true; | |
0dd2d296 ILT |
2493 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2494 | sreg); | |
2495 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2496 | likely ? "beql" : "beq", |
2497 | "s,t,p", AT, 0); | |
670a50eb | 2498 | break; |
3d3c5039 | 2499 | |
8358c818 ILT |
2500 | case M_BLEUL_I: |
2501 | likely = 1; | |
3d3c5039 | 2502 | case M_BLEU_I: |
6e8dda9c | 2503 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2504 | goto do_true; |
2505 | imm_expr.X_add_number++; | |
2506 | /* FALLTHROUGH */ | |
9a7d824a | 2507 | case M_BLTU_I: |
8358c818 ILT |
2508 | case M_BLTUL_I: |
2509 | if (mask == M_BLTUL_I) | |
2510 | likely = 1; | |
670a50eb | 2511 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
2512 | goto do_false; |
2513 | if (imm_expr.X_add_number == 1) | |
670a50eb | 2514 | { |
0dd2d296 | 2515 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2516 | likely ? "beql" : "beq", |
2517 | "s,t,p", sreg, 0); | |
670a50eb | 2518 | return; |
3d3c5039 | 2519 | } |
6e8dda9c | 2520 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2521 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2522 | likely ? "bnel" : "bne", |
2523 | "s,t,p", AT, 0); | |
670a50eb | 2524 | break; |
3d3c5039 | 2525 | |
8358c818 ILT |
2526 | case M_BLTL: |
2527 | likely = 1; | |
3d3c5039 | 2528 | case M_BLT: |
670a50eb ILT |
2529 | if (treg == 0) |
2530 | { | |
0dd2d296 | 2531 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2532 | likely ? "bltzl" : "bltz", |
2533 | "s,p", sreg); | |
670a50eb | 2534 | return; |
3d3c5039 | 2535 | } |
9a7d824a | 2536 | if (sreg == 0) |
670a50eb | 2537 | { |
0dd2d296 | 2538 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2539 | likely ? "bgtzl" : "bgtz", |
2540 | "s,p", treg); | |
670a50eb | 2541 | return; |
3d3c5039 | 2542 | } |
0dd2d296 ILT |
2543 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2544 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2545 | likely ? "bnel" : "bne", |
2546 | "s,t,p", AT, 0); | |
670a50eb | 2547 | break; |
3d3c5039 | 2548 | |
8358c818 ILT |
2549 | case M_BLTUL: |
2550 | likely = 1; | |
3d3c5039 | 2551 | case M_BLTU: |
670a50eb | 2552 | if (treg == 0) |
9a7d824a ILT |
2553 | goto do_false; |
2554 | if (sreg == 0) | |
670a50eb | 2555 | { |
0dd2d296 | 2556 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2557 | likely ? "bnel" : "bne", |
2558 | "s,t,p", 0, treg); | |
670a50eb ILT |
2559 | return; |
2560 | } | |
0dd2d296 ILT |
2561 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2562 | treg); | |
2563 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2564 | likely ? "bnel" : "bne", |
2565 | "s,t,p", AT, 0); | |
670a50eb | 2566 | break; |
3d3c5039 | 2567 | |
8358c818 ILT |
2568 | case M_DDIV_3: |
2569 | dbl = 1; | |
3d3c5039 | 2570 | case M_DIV_3: |
8358c818 ILT |
2571 | s = "mflo"; |
2572 | goto do_div3; | |
2573 | case M_DREM_3: | |
2574 | dbl = 1; | |
3d3c5039 | 2575 | case M_REM_3: |
8358c818 ILT |
2576 | s = "mfhi"; |
2577 | do_div3: | |
670a50eb ILT |
2578 | if (treg == 0) |
2579 | { | |
2580 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2581 | if (mips_trap) |
2582 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2583 | else | |
2584 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2585 | return; |
2586 | } | |
2587 | ||
becfe05e ILT |
2588 | mips_emit_delays (); |
2589 | ++mips_noreorder; | |
0dd2d296 ILT |
2590 | mips_any_noreorder = 1; |
2591 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 2592 | dbl ? "ddiv" : "div", |
ff3a5c18 | 2593 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
2594 | if (mips_trap) |
2595 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2596 | else | |
2597 | { | |
2598 | expr1.X_add_number = 8; | |
2599 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2600 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2601 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2602 | } | |
670a50eb | 2603 | expr1.X_add_number = -1; |
0dd2d296 | 2604 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 2605 | dbl ? "daddiu" : "addiu", |
9226253a | 2606 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 2607 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 2608 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
2609 | if (dbl) |
2610 | { | |
2611 | expr1.X_add_number = 1; | |
0dd2d296 | 2612 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 2613 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
2614 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
2615 | 31); | |
8358c818 ILT |
2616 | } |
2617 | else | |
2618 | { | |
2619 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
2620 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
2621 | (int) BFD_RELOC_HI16); | |
8358c818 | 2622 | } |
8ea7f4e8 ILT |
2623 | if (mips_trap) |
2624 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
2625 | else | |
2626 | { | |
2627 | expr1.X_add_number = 8; | |
2628 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2629 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2630 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
2631 | } | |
becfe05e | 2632 | --mips_noreorder; |
0dd2d296 | 2633 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 2634 | break; |
3d3c5039 ILT |
2635 | |
2636 | case M_DIV_3I: | |
8358c818 ILT |
2637 | s = "div"; |
2638 | s2 = "mflo"; | |
2639 | goto do_divi; | |
3d3c5039 | 2640 | case M_DIVU_3I: |
8358c818 ILT |
2641 | s = "divu"; |
2642 | s2 = "mflo"; | |
2643 | goto do_divi; | |
3d3c5039 | 2644 | case M_REM_3I: |
8358c818 ILT |
2645 | s = "div"; |
2646 | s2 = "mfhi"; | |
2647 | goto do_divi; | |
3d3c5039 | 2648 | case M_REMU_3I: |
8358c818 ILT |
2649 | s = "divu"; |
2650 | s2 = "mfhi"; | |
2651 | goto do_divi; | |
2652 | case M_DDIV_3I: | |
2653 | dbl = 1; | |
2654 | s = "ddiv"; | |
2655 | s2 = "mflo"; | |
2656 | goto do_divi; | |
2657 | case M_DDIVU_3I: | |
2658 | dbl = 1; | |
2659 | s = "ddivu"; | |
2660 | s2 = "mflo"; | |
2661 | goto do_divi; | |
2662 | case M_DREM_3I: | |
2663 | dbl = 1; | |
2664 | s = "ddiv"; | |
2665 | s2 = "mfhi"; | |
2666 | goto do_divi; | |
2667 | case M_DREMU_3I: | |
2668 | dbl = 1; | |
2669 | s = "ddivu"; | |
2670 | s2 = "mfhi"; | |
2671 | do_divi: | |
670a50eb ILT |
2672 | if (imm_expr.X_add_number == 0) |
2673 | { | |
2674 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2675 | if (mips_trap) |
2676 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2677 | else | |
2678 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2679 | return; |
2680 | } | |
2681 | if (imm_expr.X_add_number == 1) | |
2682 | { | |
8358c818 | 2683 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
2684 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
2685 | sreg); | |
3d3c5039 | 2686 | else |
0dd2d296 | 2687 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
2688 | return; |
2689 | } | |
8358c818 ILT |
2690 | if (imm_expr.X_add_number == -1 |
2691 | && s[strlen (s) - 1] != 'u') | |
2692 | { | |
2693 | if (strcmp (s2, "mflo") == 0) | |
2694 | { | |
2695 | if (dbl) | |
0dd2d296 ILT |
2696 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
2697 | sreg); | |
8358c818 | 2698 | else |
0dd2d296 ILT |
2699 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
2700 | sreg); | |
8358c818 ILT |
2701 | } |
2702 | else | |
0dd2d296 | 2703 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
2704 | return; |
2705 | } | |
3d3c5039 | 2706 | |
d8a1c247 | 2707 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
2708 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
2709 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
2710 | break; |
2711 | ||
2712 | case M_DIVU_3: | |
8358c818 ILT |
2713 | s = "divu"; |
2714 | s2 = "mflo"; | |
2715 | goto do_divu3; | |
670a50eb | 2716 | case M_REMU_3: |
8358c818 ILT |
2717 | s = "divu"; |
2718 | s2 = "mfhi"; | |
2719 | goto do_divu3; | |
2720 | case M_DDIVU_3: | |
2721 | s = "ddivu"; | |
2722 | s2 = "mflo"; | |
2723 | goto do_divu3; | |
2724 | case M_DREMU_3: | |
2725 | s = "ddivu"; | |
2726 | s2 = "mfhi"; | |
2727 | do_divu3: | |
becfe05e ILT |
2728 | mips_emit_delays (); |
2729 | ++mips_noreorder; | |
0dd2d296 ILT |
2730 | mips_any_noreorder = 1; |
2731 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
2732 | if (mips_trap) |
2733 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2734 | else | |
2735 | { | |
2736 | expr1.X_add_number = 8; | |
2737 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2738 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2739 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2740 | } | |
becfe05e | 2741 | --mips_noreorder; |
0dd2d296 | 2742 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 2743 | return; |
3d3c5039 | 2744 | |
d8a1c247 KR |
2745 | case M_DLA_AB: |
2746 | dbl = 1; | |
0dd2d296 | 2747 | case M_LA_AB: |
d9aba805 ILT |
2748 | /* Load the address of a symbol into a register. If breg is not |
2749 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
2750 | |
2751 | /* When generating embedded PIC code, we permit expressions of | |
2752 | the form | |
2753 | la $4,foo-bar | |
2754 | where bar is an address in the .text section. These are used | |
2755 | when getting the addresses of functions. We don't permit | |
2756 | X_add_number to be non-zero, because if the symbol is | |
2757 | external the relaxing code needs to know that any addend is | |
2758 | purely the offset to X_op_symbol. */ | |
2759 | if (mips_pic == EMBEDDED_PIC | |
2760 | && offset_expr.X_op == O_subtract | |
2761 | && now_seg == text_section | |
847a01cd ILT |
2762 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
2763 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
2764 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
2765 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
2766 | ->sy_value.X_add_symbol) | |
2767 | == text_section))) | |
ecd4ca1c ILT |
2768 | && breg == 0 |
2769 | && offset_expr.X_add_number == 0) | |
2770 | { | |
2771 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
2772 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
2773 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2774 | mips_isa < 3 ? "addiu" : "daddiu", | |
2775 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
2776 | return; | |
2777 | } | |
2778 | ||
0dd2d296 ILT |
2779 | if (offset_expr.X_op != O_symbol |
2780 | && offset_expr.X_op != O_constant) | |
670a50eb | 2781 | { |
0dd2d296 ILT |
2782 | as_bad ("expression too complex"); |
2783 | offset_expr.X_op = O_constant; | |
2784 | } | |
2785 | ||
2786 | if (treg == breg) | |
2787 | { | |
2788 | tempreg = AT; | |
2789 | used_at = 1; | |
3d3c5039 | 2790 | } |
670a50eb ILT |
2791 | else |
2792 | { | |
0dd2d296 ILT |
2793 | tempreg = treg; |
2794 | used_at = 0; | |
670a50eb | 2795 | } |
3d3c5039 | 2796 | |
5ac34ac3 | 2797 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 2798 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 2799 | else if (mips_pic == NO_PIC) |
670a50eb | 2800 | { |
0dd2d296 ILT |
2801 | /* If this is a reference to an GP relative symbol, we want |
2802 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2803 | Otherwise we want | |
2804 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2805 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2806 | If we have a constant, we need two instructions anyhow, | |
2807 | so we may as well always use the latter form. */ | |
d8a1c247 KR |
2808 | if (offset_expr.X_add_number != 0 |
2809 | || nopic_need_relax (offset_expr.X_add_symbol)) | |
0dd2d296 ILT |
2810 | p = NULL; |
2811 | else | |
2812 | { | |
8ea7f4e8 | 2813 | frag_grow (20); |
0dd2d296 ILT |
2814 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2815 | mips_isa < 3 ? "addiu" : "daddiu", | |
2816 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2817 | p = frag_var (rs_machine_dependent, 8, 0, | |
2818 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
2819 | mips_warn_about_macros), | |
2820 | offset_expr.X_add_symbol, (long) 0, | |
2821 | (char *) NULL); | |
2822 | } | |
2823 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2824 | if (p != NULL) | |
2825 | p += 4; | |
2826 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 2827 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
2828 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
2829 | } | |
fb251650 | 2830 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2831 | { |
2832 | /* If this is a reference to an external symbol, and there | |
2833 | is no constant, we want | |
2834 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2835 | For a local symbol, we want | |
2836 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2837 | nop | |
2838 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2839 | ||
2840 | If we have a small constant, and this is a reference to | |
2841 | an external symbol, we want | |
2842 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2843 | nop | |
2844 | addiu $tempreg,$tempreg,<constant> | |
2845 | For a local symbol, we want the same instruction | |
2846 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2847 | addiu instruction. | |
2848 | ||
2849 | If we have a large constant, and this is a reference to | |
2850 | an external symbol, we want | |
2851 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2852 | lui $at,<hiconstant> | |
2853 | addiu $at,$at,<loconstant> | |
2854 | addu $tempreg,$tempreg,$at | |
2855 | For a local symbol, we want the same instruction | |
2856 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2857 | addiu instruction. */ | |
2858 | expr1.X_add_number = offset_expr.X_add_number; | |
2859 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 2860 | frag_grow (32); |
0dd2d296 | 2861 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 2862 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
2863 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
2864 | if (expr1.X_add_number == 0) | |
2865 | { | |
2866 | int off; | |
2867 | ||
2868 | if (breg == 0) | |
2869 | off = 0; | |
2870 | else | |
2871 | { | |
2872 | /* We're going to put in an addu instruction using | |
2873 | tempreg, so we may as well insert the nop right | |
2874 | now. */ | |
2875 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2876 | "nop", ""); | |
2877 | off = 4; | |
2878 | } | |
2879 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
2880 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
2881 | (breg == 0 | |
2882 | ? mips_warn_about_macros | |
2883 | : 0)), | |
2884 | offset_expr.X_add_symbol, (long) 0, | |
2885 | (char *) NULL); | |
2886 | if (breg == 0) | |
2887 | { | |
2888 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
2889 | p += 4; | |
2890 | } | |
2891 | macro_build (p, &icnt, &expr1, | |
2892 | mips_isa < 3 ? "addiu" : "daddiu", | |
2893 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2894 | /* FIXME: If breg == 0, and the next instruction uses | |
2895 | $tempreg, then if this variant case is used an extra | |
2896 | nop will be generated. */ | |
2897 | } | |
2898 | else if (expr1.X_add_number >= -0x8000 | |
2899 | && expr1.X_add_number < 0x8000) | |
2900 | { | |
2901 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2902 | "nop", ""); | |
2903 | macro_build ((char *) NULL, &icnt, &expr1, | |
2904 | mips_isa < 3 ? "addiu" : "daddiu", | |
2905 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2906 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2907 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
2908 | offset_expr.X_add_symbol, (long) 0, | |
2909 | (char *) NULL); | |
2910 | } | |
2911 | else | |
2912 | { | |
2913 | int off1; | |
2914 | ||
2915 | /* If we are going to add in a base register, and the | |
2916 | target register and the base register are the same, | |
2917 | then we are using AT as a temporary register. Since | |
2918 | we want to load the constant into AT, we add our | |
2919 | current AT (from the global offset table) and the | |
2920 | register into the register now, and pretend we were | |
2921 | not using a base register. */ | |
2922 | if (breg != treg) | |
2923 | off1 = 0; | |
2924 | else | |
2925 | { | |
2926 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2927 | "nop", ""); | |
2928 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2929 | mips_isa < 3 ? "addu" : "daddu", | |
2930 | "d,v,t", treg, AT, breg); | |
2931 | breg = 0; | |
2932 | tempreg = treg; | |
2933 | off1 = -8; | |
2934 | } | |
2935 | ||
55933a58 ILT |
2936 | /* Set mips_optimize around the lui instruction to avoid |
2937 | inserting an unnecessary nop after the lw. */ | |
2938 | hold_mips_optimize = mips_optimize; | |
2939 | mips_optimize = 2; | |
0dd2d296 | 2940 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
2941 | mips_optimize = hold_mips_optimize; |
2942 | ||
0dd2d296 ILT |
2943 | macro_build ((char *) NULL, &icnt, &expr1, |
2944 | mips_isa < 3 ? "addiu" : "daddiu", | |
2945 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
2946 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2947 | mips_isa < 3 ? "addu" : "daddu", | |
2948 | "d,v,t", tempreg, tempreg, AT); | |
2949 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2950 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
2951 | offset_expr.X_add_symbol, (long) 0, | |
2952 | (char *) NULL); | |
2953 | used_at = 1; | |
2954 | } | |
670a50eb | 2955 | } |
fb251650 ILT |
2956 | else if (mips_pic == SVR4_PIC) |
2957 | { | |
2958 | int gpdel; | |
2959 | ||
2960 | /* This is the large GOT case. If this is a reference to an | |
2961 | external symbol, and there is no constant, we want | |
2962 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2963 | addu $tempreg,$tempreg,$gp | |
2964 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
2965 | For a local symbol, we want | |
2966 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2967 | nop | |
2968 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2969 | ||
2970 | If we have a small constant, and this is a reference to | |
2971 | an external symbol, we want | |
2972 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2973 | addu $tempreg,$tempreg,$gp | |
2974 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
2975 | nop | |
2976 | addiu $tempreg,$tempreg,<constant> | |
2977 | For a local symbol, we want | |
2978 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2979 | nop | |
2980 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
2981 | ||
2982 | If we have a large constant, and this is a reference to | |
2983 | an external symbol, we want | |
2984 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2985 | addu $tempreg,$tempreg,$gp | |
2986 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
2987 | lui $at,<hiconstant> | |
2988 | addiu $at,$at,<loconstant> | |
2989 | addu $tempreg,$tempreg,$at | |
2990 | For a local symbol, we want | |
2991 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2992 | lui $at,<hiconstant> | |
2993 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
2994 | addu $tempreg,$tempreg,$at | |
2995 | */ | |
2996 | expr1.X_add_number = offset_expr.X_add_number; | |
2997 | offset_expr.X_add_number = 0; | |
2998 | frag_grow (52); | |
2999 | if (reg_needs_delay (GP)) | |
3000 | gpdel = 4; | |
3001 | else | |
3002 | gpdel = 0; | |
3003 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3004 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3005 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3006 | mips_isa < 3 ? "addu" : "daddu", | |
3007 | "d,v,t", tempreg, tempreg, GP); | |
3008 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3009 | dbl ? "ld" : "lw", | |
3010 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3011 | tempreg); | |
3012 | if (expr1.X_add_number == 0) | |
3013 | { | |
3014 | int off; | |
3015 | ||
3016 | if (breg == 0) | |
3017 | off = 0; | |
3018 | else | |
3019 | { | |
3020 | /* We're going to put in an addu instruction using | |
3021 | tempreg, so we may as well insert the nop right | |
3022 | now. */ | |
3023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3024 | "nop", ""); | |
3025 | off = 4; | |
3026 | } | |
3027 | ||
3028 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3029 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3030 | 8 + gpdel, 0, | |
3031 | (breg == 0 | |
3032 | ? mips_warn_about_macros | |
3033 | : 0)), | |
3034 | offset_expr.X_add_symbol, (long) 0, | |
3035 | (char *) NULL); | |
3036 | } | |
3037 | else if (expr1.X_add_number >= -0x8000 | |
3038 | && expr1.X_add_number < 0x8000) | |
3039 | { | |
3040 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3041 | "nop", ""); | |
3042 | macro_build ((char *) NULL, &icnt, &expr1, | |
3043 | mips_isa < 3 ? "addiu" : "daddiu", | |
3044 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3045 | ||
3046 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3047 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3048 | (breg == 0 | |
3049 | ? mips_warn_about_macros | |
3050 | : 0)), | |
3051 | offset_expr.X_add_symbol, (long) 0, | |
3052 | (char *) NULL); | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | int adj, dreg; | |
3057 | ||
3058 | /* If we are going to add in a base register, and the | |
3059 | target register and the base register are the same, | |
3060 | then we are using AT as a temporary register. Since | |
3061 | we want to load the constant into AT, we add our | |
3062 | current AT (from the global offset table) and the | |
3063 | register into the register now, and pretend we were | |
3064 | not using a base register. */ | |
3065 | if (breg != treg) | |
3066 | { | |
3067 | adj = 0; | |
3068 | dreg = tempreg; | |
3069 | } | |
3070 | else | |
3071 | { | |
3072 | assert (tempreg == AT); | |
3073 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3074 | "nop", ""); | |
3075 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3076 | mips_isa < 3 ? "addu" : "daddu", | |
3077 | "d,v,t", treg, AT, breg); | |
3078 | dreg = treg; | |
3079 | adj = 8; | |
3080 | } | |
3081 | ||
3082 | /* Set mips_optimize around the lui instruction to avoid | |
3083 | inserting an unnecessary nop after the lw. */ | |
3084 | hold_mips_optimize = mips_optimize; | |
3085 | mips_optimize = 2; | |
3086 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3087 | mips_optimize = hold_mips_optimize; | |
3088 | ||
3089 | macro_build ((char *) NULL, &icnt, &expr1, | |
3090 | mips_isa < 3 ? "addiu" : "daddiu", | |
3091 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3092 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3093 | mips_isa < 3 ? "addu" : "daddu", | |
3094 | "d,v,t", dreg, dreg, AT); | |
3095 | ||
3096 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
3097 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
3098 | 8 + gpdel, 0, | |
3099 | (breg == 0 | |
3100 | ? mips_warn_about_macros | |
3101 | : 0)), | |
3102 | offset_expr.X_add_symbol, (long) 0, | |
3103 | (char *) NULL); | |
3104 | ||
3105 | used_at = 1; | |
3106 | } | |
3107 | ||
3108 | if (gpdel > 0) | |
3109 | { | |
3110 | /* This is needed because this instruction uses $gp, but | |
3111 | the first instruction on the main stream does not. */ | |
3112 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3113 | p += 4; | |
3114 | } | |
3115 | macro_build (p, &icnt, &offset_expr, | |
3116 | dbl ? "ld" : "lw", | |
3117 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3118 | p += 4; | |
3119 | if (expr1.X_add_number >= -0x8000 | |
3120 | && expr1.X_add_number < 0x8000) | |
3121 | { | |
3122 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3123 | p += 4; | |
3124 | macro_build (p, &icnt, &expr1, | |
3125 | mips_isa < 3 ? "addiu" : "daddiu", | |
3126 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3127 | /* FIXME: If add_number is 0, and there was no base | |
3128 | register, the external symbol case ended with a load, | |
3129 | so if the symbol turns out to not be external, and | |
3130 | the next instruction uses tempreg, an unnecessary nop | |
3131 | will be inserted. */ | |
3132 | } | |
3133 | else | |
3134 | { | |
3135 | if (breg == treg) | |
3136 | { | |
3137 | /* We must add in the base register now, as in the | |
3138 | external symbol case. */ | |
3139 | assert (tempreg == AT); | |
3140 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3141 | p += 4; | |
3142 | macro_build (p, &icnt, (expressionS *) NULL, | |
3143 | mips_isa < 3 ? "addu" : "daddu", | |
3144 | "d,v,t", treg, AT, breg); | |
3145 | p += 4; | |
3146 | tempreg = treg; | |
3147 | /* We set breg to 0 because we have arranged to add | |
3148 | it in in both cases. */ | |
3149 | breg = 0; | |
3150 | } | |
3151 | ||
3152 | macro_build_lui (p, &icnt, &expr1, AT); | |
3153 | p += 4; | |
3154 | macro_build (p, &icnt, &expr1, | |
3155 | mips_isa < 3 ? "addiu" : "daddiu", | |
3156 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3157 | p += 4; | |
3158 | macro_build (p, &icnt, (expressionS *) NULL, | |
3159 | mips_isa < 3 ? "addu" : "daddu", | |
3160 | "d,v,t", tempreg, tempreg, AT); | |
3161 | p += 4; | |
3162 | } | |
3163 | } | |
d9aba805 ILT |
3164 | else if (mips_pic == EMBEDDED_PIC) |
3165 | { | |
3166 | /* We use | |
3167 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3168 | */ | |
3169 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3170 | mips_isa < 3 ? "addiu" : "daddiu", | |
3171 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3172 | } | |
3173 | else | |
3174 | abort (); | |
0dd2d296 | 3175 | |
670a50eb | 3176 | if (breg != 0) |
0dd2d296 ILT |
3177 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3178 | mips_isa < 3 ? "addu" : "daddu", | |
3179 | "d,v,t", treg, tempreg, breg); | |
3180 | ||
3181 | if (! used_at) | |
3182 | return; | |
3183 | ||
3184 | break; | |
3185 | ||
3186 | case M_J_A: | |
3187 | /* The j instruction may not be used in PIC code, since it | |
3188 | requires an absolute address. We convert it to a b | |
3189 | instruction. */ | |
d9aba805 | 3190 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
3191 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
3192 | else | |
3193 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 3194 | return; |
3d3c5039 | 3195 | |
9226253a ILT |
3196 | /* The jal instructions must be handled as macros because when |
3197 | generating PIC code they expand to multi-instruction | |
3198 | sequences. Normally they are simple instructions. */ | |
3199 | case M_JAL_1: | |
3200 | dreg = RA; | |
3201 | /* Fall through. */ | |
3202 | case M_JAL_2: | |
d9aba805 ILT |
3203 | if (mips_pic == NO_PIC |
3204 | || mips_pic == EMBEDDED_PIC) | |
3205 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
3206 | "d,s", dreg, sreg); | |
3207 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3208 | { |
d9aba805 ILT |
3209 | if (sreg != PIC_CALL_REG) |
3210 | as_warn ("MIPS PIC call to register other than $25"); | |
3211 | ||
0dd2d296 ILT |
3212 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
3213 | "d,s", dreg, sreg); | |
d9aba805 ILT |
3214 | if (mips_cprestore_offset < 0) |
3215 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
3216 | else | |
3217 | { | |
3218 | expr1.X_add_number = mips_cprestore_offset; | |
3219 | macro_build ((char *) NULL, &icnt, &expr1, | |
3220 | mips_isa < 3 ? "lw" : "ld", | |
3221 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
3222 | } | |
9226253a | 3223 | } |
0dd2d296 | 3224 | else |
d9aba805 ILT |
3225 | abort (); |
3226 | ||
9226253a ILT |
3227 | return; |
3228 | ||
3229 | case M_JAL_A: | |
d9aba805 ILT |
3230 | if (mips_pic == NO_PIC) |
3231 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
3232 | else if (mips_pic == SVR4_PIC) | |
9226253a | 3233 | { |
fb251650 ILT |
3234 | /* If this is a reference to an external symbol, and we are |
3235 | using a small GOT, we want | |
d9aba805 ILT |
3236 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
3237 | nop | |
3238 | jalr $25 | |
3239 | nop | |
3240 | lw $gp,cprestore($sp) | |
3241 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
3242 | pseudo-op. If we are using a big GOT, we want |
3243 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
3244 | addu $25,$25,$gp | |
3245 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
3246 | nop | |
3247 | jalr $25 | |
3248 | nop | |
3249 | lw $gp,cprestore($sp) | |
3250 | If the symbol is not external, we want | |
d9aba805 ILT |
3251 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3252 | nop | |
3253 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
3254 | jalr $25 | |
3255 | nop | |
fb251650 ILT |
3256 | lw $gp,cprestore($sp) */ |
3257 | frag_grow (40); | |
3258 | if (! mips_big_got) | |
3259 | { | |
3260 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3261 | mips_isa < 3 ? "lw" : "ld", | |
3262 | "t,o(b)", PIC_CALL_REG, | |
3263 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
3264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3265 | "nop", ""); | |
3266 | p = frag_var (rs_machine_dependent, 4, 0, | |
3267 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3268 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3269 | } | |
3270 | else | |
3271 | { | |
3272 | int gpdel; | |
3273 | ||
3274 | if (reg_needs_delay (GP)) | |
3275 | gpdel = 4; | |
3276 | else | |
3277 | gpdel = 0; | |
3278 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3279 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
3280 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3281 | mips_isa < 3 ? "addu" : "daddu", | |
3282 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
3283 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3284 | mips_isa < 3 ? "lw" : "ld", | |
3285 | "t,o(b)", PIC_CALL_REG, | |
3286 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
3287 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3288 | "nop", ""); | |
3289 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3290 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
3291 | 0, 0), | |
3292 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3293 | if (gpdel > 0) | |
3294 | { | |
3295 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3296 | p += 4; | |
3297 | } | |
3298 | macro_build (p, &icnt, &offset_expr, | |
3299 | mips_isa < 3 ? "lw" : "ld", | |
3300 | "t,o(b)", PIC_CALL_REG, | |
3301 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
3302 | p += 4; | |
3303 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3304 | p += 4; | |
3305 | } | |
d9aba805 ILT |
3306 | macro_build (p, &icnt, &offset_expr, |
3307 | mips_isa < 3 ? "addiu" : "daddiu", | |
3308 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
3309 | (int) BFD_RELOC_LO16); | |
3310 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3311 | "jalr", "s", PIC_CALL_REG); | |
3312 | if (mips_cprestore_offset < 0) | |
3313 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
3314 | else | |
3315 | { | |
3316 | if (mips_noreorder) | |
3317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3318 | "nop", ""); | |
3319 | expr1.X_add_number = mips_cprestore_offset; | |
3320 | macro_build ((char *) NULL, &icnt, &expr1, | |
3321 | mips_isa < 3 ? "lw" : "ld", | |
3322 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
3323 | mips_frame_reg); | |
3324 | } | |
0dd2d296 | 3325 | } |
d9aba805 | 3326 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
3327 | { |
3328 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
3329 | /* The linker may expand the call to a longer sequence which | |
3330 | uses $at, so we must break rather than return. */ | |
3331 | break; | |
3332 | } | |
d9aba805 ILT |
3333 | else |
3334 | abort (); | |
3335 | ||
9226253a ILT |
3336 | return; |
3337 | ||
3d3c5039 | 3338 | case M_LB_AB: |
670a50eb ILT |
3339 | s = "lb"; |
3340 | goto ld; | |
3d3c5039 | 3341 | case M_LBU_AB: |
670a50eb ILT |
3342 | s = "lbu"; |
3343 | goto ld; | |
3d3c5039 | 3344 | case M_LH_AB: |
670a50eb ILT |
3345 | s = "lh"; |
3346 | goto ld; | |
3d3c5039 | 3347 | case M_LHU_AB: |
670a50eb ILT |
3348 | s = "lhu"; |
3349 | goto ld; | |
3d3c5039 | 3350 | case M_LW_AB: |
670a50eb ILT |
3351 | s = "lw"; |
3352 | goto ld; | |
3d3c5039 | 3353 | case M_LWC0_AB: |
670a50eb | 3354 | s = "lwc0"; |
8358c818 | 3355 | coproc = 1; |
670a50eb | 3356 | goto ld; |
3d3c5039 | 3357 | case M_LWC1_AB: |
670a50eb | 3358 | s = "lwc1"; |
8358c818 | 3359 | coproc = 1; |
670a50eb | 3360 | goto ld; |
3d3c5039 | 3361 | case M_LWC2_AB: |
670a50eb | 3362 | s = "lwc2"; |
8358c818 | 3363 | coproc = 1; |
670a50eb | 3364 | goto ld; |
3d3c5039 | 3365 | case M_LWC3_AB: |
670a50eb | 3366 | s = "lwc3"; |
8358c818 | 3367 | coproc = 1; |
670a50eb | 3368 | goto ld; |
3d3c5039 | 3369 | case M_LWL_AB: |
670a50eb | 3370 | s = "lwl"; |
b2b8c24e | 3371 | lr = 1; |
670a50eb | 3372 | goto ld; |
3d3c5039 | 3373 | case M_LWR_AB: |
670a50eb | 3374 | s = "lwr"; |
b2b8c24e | 3375 | lr = 1; |
8358c818 ILT |
3376 | goto ld; |
3377 | case M_LDC1_AB: | |
3378 | s = "ldc1"; | |
3379 | coproc = 1; | |
3380 | goto ld; | |
3381 | case M_LDC2_AB: | |
3382 | s = "ldc2"; | |
3383 | coproc = 1; | |
3384 | goto ld; | |
3385 | case M_LDC3_AB: | |
3386 | s = "ldc3"; | |
3387 | coproc = 1; | |
3388 | goto ld; | |
3389 | case M_LDL_AB: | |
3390 | s = "ldl"; | |
b2b8c24e | 3391 | lr = 1; |
8358c818 ILT |
3392 | goto ld; |
3393 | case M_LDR_AB: | |
3394 | s = "ldr"; | |
b2b8c24e | 3395 | lr = 1; |
8358c818 ILT |
3396 | goto ld; |
3397 | case M_LL_AB: | |
3398 | s = "ll"; | |
3399 | goto ld; | |
3400 | case M_LLD_AB: | |
3401 | s = "lld"; | |
3402 | goto ld; | |
3403 | case M_LWU_AB: | |
3404 | s = "lwu"; | |
3d3c5039 | 3405 | ld: |
b2b8c24e | 3406 | if (breg == treg || coproc || lr) |
670a50eb ILT |
3407 | { |
3408 | tempreg = AT; | |
3409 | used_at = 1; | |
3410 | } | |
3411 | else | |
3412 | { | |
3413 | tempreg = treg; | |
3414 | used_at = 0; | |
3415 | } | |
3416 | goto ld_st; | |
3d3c5039 | 3417 | case M_SB_AB: |
670a50eb ILT |
3418 | s = "sb"; |
3419 | goto st; | |
3d3c5039 | 3420 | case M_SH_AB: |
670a50eb ILT |
3421 | s = "sh"; |
3422 | goto st; | |
3d3c5039 | 3423 | case M_SW_AB: |
670a50eb ILT |
3424 | s = "sw"; |
3425 | goto st; | |
3d3c5039 | 3426 | case M_SWC0_AB: |
670a50eb | 3427 | s = "swc0"; |
8358c818 | 3428 | coproc = 1; |
670a50eb | 3429 | goto st; |
3d3c5039 | 3430 | case M_SWC1_AB: |
670a50eb | 3431 | s = "swc1"; |
8358c818 | 3432 | coproc = 1; |
670a50eb | 3433 | goto st; |
3d3c5039 | 3434 | case M_SWC2_AB: |
670a50eb | 3435 | s = "swc2"; |
8358c818 | 3436 | coproc = 1; |
670a50eb | 3437 | goto st; |
3d3c5039 | 3438 | case M_SWC3_AB: |
670a50eb | 3439 | s = "swc3"; |
8358c818 | 3440 | coproc = 1; |
670a50eb | 3441 | goto st; |
3d3c5039 | 3442 | case M_SWL_AB: |
670a50eb ILT |
3443 | s = "swl"; |
3444 | goto st; | |
3d3c5039 | 3445 | case M_SWR_AB: |
670a50eb | 3446 | s = "swr"; |
8358c818 ILT |
3447 | goto st; |
3448 | case M_SC_AB: | |
3449 | s = "sc"; | |
3450 | goto st; | |
3451 | case M_SCD_AB: | |
3452 | s = "scd"; | |
3453 | goto st; | |
3454 | case M_SDC1_AB: | |
3455 | s = "sdc1"; | |
3456 | coproc = 1; | |
3457 | goto st; | |
3458 | case M_SDC2_AB: | |
3459 | s = "sdc2"; | |
3460 | coproc = 1; | |
3461 | goto st; | |
3462 | case M_SDC3_AB: | |
3463 | s = "sdc3"; | |
3464 | coproc = 1; | |
3465 | goto st; | |
3466 | case M_SDL_AB: | |
3467 | s = "sdl"; | |
3468 | goto st; | |
3469 | case M_SDR_AB: | |
3470 | s = "sdr"; | |
3d3c5039 | 3471 | st: |
670a50eb ILT |
3472 | tempreg = AT; |
3473 | used_at = 1; | |
3d3c5039 | 3474 | ld_st: |
8358c818 ILT |
3475 | if (mask == M_LWC1_AB |
3476 | || mask == M_SWC1_AB | |
8358c818 | 3477 | || mask == M_LDC1_AB |
0dd2d296 ILT |
3478 | || mask == M_SDC1_AB |
3479 | || mask == M_L_DAB | |
3480 | || mask == M_S_DAB) | |
670a50eb | 3481 | fmt = "T,o(b)"; |
8358c818 | 3482 | else if (coproc) |
19ed8960 | 3483 | fmt = "E,o(b)"; |
670a50eb ILT |
3484 | else |
3485 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
3486 | |
3487 | if (offset_expr.X_op != O_constant | |
3488 | && offset_expr.X_op != O_symbol) | |
3489 | { | |
3490 | as_bad ("expression too complex"); | |
3491 | offset_expr.X_op = O_constant; | |
3492 | } | |
3493 | ||
3494 | /* A constant expression in PIC code can be handled just as it | |
3495 | is in non PIC code. */ | |
d9aba805 | 3496 | if (mips_pic == NO_PIC |
0dd2d296 | 3497 | || offset_expr.X_op == O_constant) |
670a50eb | 3498 | { |
0dd2d296 ILT |
3499 | /* If this is a reference to a GP relative symbol, and there |
3500 | is no base register, we want | |
3501 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 3502 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
3503 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
3504 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
3505 | If we have a constant, we need two instructions anyhow, | |
3506 | so we always use the latter form. | |
3507 | ||
3508 | If we have a base register, and this is a reference to a | |
3509 | GP relative symbol, we want | |
3510 | addu $tempreg,$breg,$gp | |
3511 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3512 | Otherwise we want | |
3513 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3514 | addu $tempreg,$tempreg,$breg | |
3515 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
3516 | With a constant we always use the latter case. */ | |
670a50eb ILT |
3517 | if (breg == 0) |
3518 | { | |
d8a1c247 KR |
3519 | if (offset_expr.X_add_number != 0 |
3520 | || nopic_need_relax (offset_expr.X_add_symbol)) | |
0dd2d296 ILT |
3521 | p = NULL; |
3522 | else | |
3523 | { | |
8ea7f4e8 | 3524 | frag_grow (20); |
0dd2d296 ILT |
3525 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
3526 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3527 | p = frag_var (rs_machine_dependent, 8, 0, | |
3528 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
3529 | (mips_warn_about_macros |
3530 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
3531 | offset_expr.X_add_symbol, (long) 0, |
3532 | (char *) NULL); | |
8197b589 | 3533 | used_at = 0; |
0dd2d296 ILT |
3534 | } |
3535 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3536 | if (p != NULL) | |
3537 | p += 4; | |
3538 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
3539 | (int) BFD_RELOC_LO16, tempreg); | |
3540 | } | |
3541 | else | |
3542 | { | |
d8a1c247 KR |
3543 | if (offset_expr.X_add_number != 0 |
3544 | || nopic_need_relax (offset_expr.X_add_symbol)) | |
0dd2d296 ILT |
3545 | p = NULL; |
3546 | else | |
3547 | { | |
8ea7f4e8 | 3548 | frag_grow (28); |
0dd2d296 ILT |
3549 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3550 | mips_isa < 3 ? "addu" : "daddu", | |
3551 | "d,v,t", tempreg, breg, GP); | |
3552 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3553 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3554 | p = frag_var (rs_machine_dependent, 12, 0, | |
3555 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
3556 | offset_expr.X_add_symbol, (long) 0, | |
3557 | (char *) NULL); | |
3558 | } | |
3559 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3560 | if (p != NULL) | |
3561 | p += 4; | |
3562 | macro_build (p, &icnt, (expressionS *) NULL, | |
3563 | mips_isa < 3 ? "addu" : "daddu", | |
3564 | "d,v,t", tempreg, tempreg, breg); | |
3565 | if (p != NULL) | |
3566 | p += 4; | |
3567 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
3568 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3569 | } |
670a50eb | 3570 | } |
fb251650 | 3571 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 3572 | { |
0dd2d296 ILT |
3573 | /* If this is a reference to an external symbol, we want |
3574 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3575 | nop | |
3576 | <op> $treg,0($tempreg) | |
3577 | Otherwise we want | |
3578 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3579 | nop | |
3580 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3581 | <op> $treg,0($tempreg) | |
3582 | If there is a base register, we add it to $tempreg before | |
3583 | the <op>. If there is a constant, we stick it in the | |
3584 | <op> instruction. We don't handle constants larger than | |
3585 | 16 bits, because we have no way to load the upper 16 bits | |
3586 | (actually, we could handle them for the subset of cases | |
3587 | in which we are not using $at). */ | |
3588 | assert (offset_expr.X_op == O_symbol); | |
3589 | expr1.X_add_number = offset_expr.X_add_number; | |
3590 | offset_expr.X_add_number = 0; | |
3591 | if (expr1.X_add_number < -0x8000 | |
3592 | || expr1.X_add_number >= 0x8000) | |
3593 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 3594 | frag_grow (20); |
0dd2d296 ILT |
3595 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3596 | mips_isa < 3 ? "lw" : "ld", | |
3597 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3598 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
3599 | p = frag_var (rs_machine_dependent, 4, 0, | |
3600 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3601 | offset_expr.X_add_symbol, (long) 0, | |
3602 | (char *) NULL); | |
3603 | macro_build (p, &icnt, &offset_expr, | |
3604 | mips_isa < 3 ? "addiu" : "daddiu", | |
3605 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3606 | if (breg != 0) |
0dd2d296 | 3607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
3608 | mips_isa < 3 ? "addu" : "daddu", |
3609 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
3610 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
3611 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3612 | } |
fb251650 ILT |
3613 | else if (mips_pic == SVR4_PIC) |
3614 | { | |
3615 | int gpdel; | |
3616 | ||
3617 | /* If this is a reference to an external symbol, we want | |
3618 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3619 | addu $tempreg,$tempreg,$gp | |
3620 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3621 | <op> $treg,0($tempreg) | |
3622 | Otherwise we want | |
3623 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3624 | nop | |
3625 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3626 | <op> $treg,0($tempreg) | |
3627 | If there is a base register, we add it to $tempreg before | |
3628 | the <op>. If there is a constant, we stick it in the | |
3629 | <op> instruction. We don't handle constants larger than | |
3630 | 16 bits, because we have no way to load the upper 16 bits | |
3631 | (actually, we could handle them for the subset of cases | |
3632 | in which we are not using $at). */ | |
3633 | assert (offset_expr.X_op == O_symbol); | |
3634 | expr1.X_add_number = offset_expr.X_add_number; | |
3635 | offset_expr.X_add_number = 0; | |
3636 | if (expr1.X_add_number < -0x8000 | |
3637 | || expr1.X_add_number >= 0x8000) | |
3638 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3639 | if (reg_needs_delay (GP)) | |
3640 | gpdel = 4; | |
3641 | else | |
3642 | gpdel = 0; | |
3643 | frag_grow (36); | |
3644 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3645 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3646 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3647 | mips_isa < 3 ? "addu" : "daddu", | |
3648 | "d,v,t", tempreg, tempreg, GP); | |
3649 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3650 | mips_isa < 3 ? "lw" : "ld", | |
3651 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16); | |
3652 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3653 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
3654 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
3655 | if (gpdel > 0) | |
3656 | { | |
3657 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3658 | p += 4; | |
3659 | } | |
3660 | macro_build (p, &icnt, &offset_expr, | |
3661 | mips_isa < 3 ? "lw" : "ld", | |
3662 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16); | |
3663 | p += 4; | |
3664 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3665 | p += 4; | |
3666 | macro_build (p, &icnt, &offset_expr, | |
3667 | mips_isa < 3 ? "addiu" : "daddiu", | |
3668 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3669 | if (breg != 0) | |
3670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3671 | mips_isa < 3 ? "addu" : "daddu", | |
3672 | "d,v,t", tempreg, tempreg, breg); | |
3673 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
3674 | (int) BFD_RELOC_LO16, tempreg); | |
3675 | } | |
d9aba805 ILT |
3676 | else if (mips_pic == EMBEDDED_PIC) |
3677 | { | |
3678 | /* If there is no base register, we want | |
3679 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3680 | If there is a base register, we want | |
3681 | addu $tempreg,$breg,$gp | |
3682 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3683 | */ | |
3684 | assert (offset_expr.X_op == O_symbol); | |
3685 | if (breg == 0) | |
3686 | { | |
3687 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3688 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3689 | used_at = 0; | |
3690 | } | |
3691 | else | |
3692 | { | |
3693 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3694 | mips_isa < 3 ? "addu" : "daddu", | |
3695 | "d,v,t", tempreg, breg, GP); | |
3696 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3697 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3698 | } | |
3699 | } | |
3700 | else | |
3701 | abort (); | |
0dd2d296 ILT |
3702 | |
3703 | if (! used_at) | |
3704 | return; | |
3705 | ||
3706 | break; | |
3d3c5039 ILT |
3707 | |
3708 | case M_LI: | |
19ed8960 | 3709 | case M_LI_S: |
d8a1c247 KR |
3710 | load_register (&icnt, treg, &imm_expr, 0); |
3711 | return; | |
3712 | ||
3713 | case M_DLI: | |
3714 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 3715 | return; |
3d3c5039 | 3716 | |
0dd2d296 | 3717 | case M_LI_SS: |
55933a58 | 3718 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 3719 | { |
d8a1c247 | 3720 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
3721 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3722 | "mtc1", "t,G", AT, treg); | |
3723 | break; | |
0dd2d296 | 3724 | } |
d9aba805 | 3725 | else |
d2c71068 | 3726 | { |
55933a58 ILT |
3727 | assert (offset_expr.X_op == O_symbol |
3728 | && strcmp (segment_name (S_GET_SEGMENT | |
3729 | (offset_expr.X_add_symbol)), | |
3730 | ".lit4") == 0 | |
3731 | && offset_expr.X_add_number == 0); | |
3732 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
3733 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
3734 | return; |
3735 | } | |
0dd2d296 | 3736 | |
3d3c5039 | 3737 | case M_LI_D: |
d9aba805 ILT |
3738 | /* We know that sym is in the .rdata section. First we get the |
3739 | upper 16 bits of the address. */ | |
3740 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3741 | { |
3742 | /* FIXME: This won't work for a 64 bit address. */ | |
3743 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3744 | } | |
d9aba805 | 3745 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
3746 | { |
3747 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3748 | mips_isa < 3 ? "lw" : "ld", | |
3749 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3750 | } | |
d9aba805 ILT |
3751 | else if (mips_pic == EMBEDDED_PIC) |
3752 | { | |
3753 | /* For embedded PIC we pick up the entire address off $gp in | |
3754 | a single instruction. */ | |
3755 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3756 | mips_isa < 3 ? "addiu" : "daddiu", | |
3757 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3758 | offset_expr.X_op = O_constant; | |
3759 | offset_expr.X_add_number = 0; | |
3760 | } | |
3761 | else | |
3762 | abort (); | |
3763 | ||
0dd2d296 | 3764 | /* Now we load the register(s). */ |
8358c818 | 3765 | if (mips_isa >= 3) |
0dd2d296 ILT |
3766 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
3767 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
3768 | else |
3769 | { | |
0dd2d296 ILT |
3770 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
3771 | treg, (int) BFD_RELOC_LO16, AT); | |
3772 | if (treg != 31) | |
3773 | { | |
3774 | /* FIXME: How in the world do we deal with the possible | |
3775 | overflow here? */ | |
3776 | offset_expr.X_add_number += 4; | |
3777 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
3778 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
3779 | } | |
8358c818 | 3780 | } |
d2c71068 ILT |
3781 | |
3782 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3783 | does not become a variant frag. */ | |
3784 | frag_wane (frag_now); | |
3785 | frag_new (0); | |
3786 | ||
670a50eb | 3787 | break; |
3d3c5039 ILT |
3788 | |
3789 | case M_LI_DD: | |
55933a58 ILT |
3790 | assert (offset_expr.X_op == O_symbol |
3791 | && offset_expr.X_add_number == 0); | |
3792 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
3793 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 3794 | { |
0dd2d296 ILT |
3795 | if (mips_isa >= 2) |
3796 | { | |
3797 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
3798 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
3799 | return; | |
3800 | } | |
3801 | breg = GP; | |
3802 | r = BFD_RELOC_MIPS_LITERAL; | |
3803 | goto dob; | |
3804 | } | |
55933a58 | 3805 | else |
0dd2d296 | 3806 | { |
55933a58 ILT |
3807 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
3808 | if (mips_pic == SVR4_PIC) | |
3809 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3810 | mips_isa < 3 ? "lw" : "ld", | |
3811 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3812 | else | |
3813 | { | |
3814 | /* FIXME: This won't work for a 64 bit address. */ | |
3815 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3816 | } | |
3817 | ||
0dd2d296 ILT |
3818 | if (mips_isa >= 2) |
3819 | { | |
3820 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 3821 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
3822 | |
3823 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3824 | that this does not become a variant frag. */ | |
3825 | frag_wane (frag_now); | |
3826 | frag_new (0); | |
3827 | ||
0dd2d296 ILT |
3828 | break; |
3829 | } | |
3830 | breg = AT; | |
3831 | r = BFD_RELOC_LO16; | |
3832 | goto dob; | |
8358c818 | 3833 | } |
9226253a | 3834 | |
3d3c5039 | 3835 | case M_L_DOB: |
9a7d824a ILT |
3836 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3837 | to adjust when loading from memory. */ | |
9226253a ILT |
3838 | r = BFD_RELOC_LO16; |
3839 | dob: | |
8358c818 | 3840 | assert (mips_isa < 2); |
0dd2d296 | 3841 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3842 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3843 | (int) r, breg); |
0dd2d296 ILT |
3844 | /* FIXME: A possible overflow which I don't know how to deal |
3845 | with. */ | |
670a50eb | 3846 | offset_expr.X_add_number += 4; |
0dd2d296 | 3847 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3848 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3849 | (int) r, breg); |
d2c71068 ILT |
3850 | |
3851 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3852 | does not become a variant frag. */ | |
3853 | frag_wane (frag_now); | |
3854 | frag_new (0); | |
3855 | ||
0dd2d296 ILT |
3856 | if (breg != AT) |
3857 | return; | |
3858 | break; | |
3d3c5039 ILT |
3859 | |
3860 | case M_L_DAB: | |
670a50eb ILT |
3861 | /* |
3862 | * The MIPS assembler seems to check for X_add_number not | |
3863 | * being double aligned and generating: | |
3864 | * lui at,%hi(foo+1) | |
3865 | * addu at,at,v1 | |
3866 | * addiu at,at,%lo(foo+1) | |
3867 | * lwc1 f2,0(at) | |
3868 | * lwc1 f3,4(at) | |
3869 | * But, the resulting address is the same after relocation so why | |
3870 | * generate the extra instruction? | |
3871 | */ | |
4032d3f0 | 3872 | coproc = 1; |
0dd2d296 | 3873 | if (mips_isa >= 2) |
670a50eb | 3874 | { |
0dd2d296 ILT |
3875 | s = "ldc1"; |
3876 | goto ld; | |
670a50eb | 3877 | } |
0dd2d296 ILT |
3878 | |
3879 | s = "lwc1"; | |
3880 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
3881 | goto ldd_std; |
3882 | ||
3883 | case M_S_DAB: | |
8358c818 | 3884 | if (mips_isa >= 2) |
8358c818 | 3885 | { |
0dd2d296 ILT |
3886 | s = "sdc1"; |
3887 | goto st; | |
8358c818 | 3888 | } |
3d3c5039 | 3889 | |
0dd2d296 ILT |
3890 | s = "swc1"; |
3891 | fmt = "T,o(b)"; | |
3892 | coproc = 1; | |
3893 | goto ldd_std; | |
3d3c5039 ILT |
3894 | |
3895 | case M_LD_AB: | |
0dd2d296 | 3896 | if (mips_isa >= 3) |
670a50eb | 3897 | { |
0dd2d296 ILT |
3898 | s = "ld"; |
3899 | goto ld; | |
670a50eb | 3900 | } |
0dd2d296 ILT |
3901 | |
3902 | s = "lw"; | |
3903 | fmt = "t,o(b)"; | |
3904 | goto ldd_std; | |
3905 | ||
3906 | case M_SD_AB: | |
3907 | if (mips_isa >= 3) | |
670a50eb | 3908 | { |
0dd2d296 ILT |
3909 | s = "sd"; |
3910 | goto st; | |
670a50eb | 3911 | } |
0dd2d296 | 3912 | |
670a50eb | 3913 | s = "sw"; |
0dd2d296 ILT |
3914 | fmt = "t,o(b)"; |
3915 | ||
3916 | ldd_std: | |
3917 | if (offset_expr.X_op != O_symbol | |
3918 | && offset_expr.X_op != O_constant) | |
670a50eb | 3919 | { |
0dd2d296 ILT |
3920 | as_bad ("expression too complex"); |
3921 | offset_expr.X_op = O_constant; | |
3922 | } | |
3923 | ||
3924 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
3925 | to adjust when loading from memory. We set coproc if we must | |
3926 | load $fn+1 first. */ | |
3927 | if (byte_order == LITTLE_ENDIAN) | |
3928 | coproc = 0; | |
3929 | ||
d9aba805 | 3930 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
3931 | || offset_expr.X_op == O_constant) |
3932 | { | |
3933 | /* If this is a reference to a GP relative symbol, we want | |
3934 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3935 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3936 | If we have a base register, we use this | |
3937 | addu $at,$breg,$gp | |
3938 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3939 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3940 | If this is not a GP relative symbol, we want | |
3941 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3942 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3943 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3944 | If there is a base register, we add it to $at after the | |
3945 | lui instruction. If there is a constant, we always use | |
3946 | the last case. */ | |
d8a1c247 KR |
3947 | if (offset_expr.X_add_number != 0 |
3948 | || nopic_need_relax (offset_expr.X_add_symbol)) | |
670a50eb | 3949 | { |
0dd2d296 ILT |
3950 | p = NULL; |
3951 | used_at = 1; | |
670a50eb ILT |
3952 | } |
3953 | else | |
0dd2d296 ILT |
3954 | { |
3955 | int off; | |
3956 | ||
3957 | if (breg == 0) | |
3958 | { | |
8ea7f4e8 | 3959 | frag_grow (28); |
0dd2d296 ILT |
3960 | tempreg = GP; |
3961 | off = 0; | |
3962 | used_at = 0; | |
3963 | } | |
3964 | else | |
3965 | { | |
8ea7f4e8 | 3966 | frag_grow (36); |
0dd2d296 ILT |
3967 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3968 | mips_isa < 3 ? "addu" : "daddu", | |
3969 | "d,v,t", AT, breg, GP); | |
3970 | tempreg = AT; | |
3971 | off = 4; | |
3972 | used_at = 1; | |
3973 | } | |
3974 | ||
3975 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3976 | coproc ? treg + 1 : treg, | |
3977 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3978 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
3979 | |
3980 | /* Set mips_optimize to 2 to avoid inserting an | |
3981 | undesired nop. */ | |
3982 | hold_mips_optimize = mips_optimize; | |
3983 | mips_optimize = 2; | |
0dd2d296 ILT |
3984 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
3985 | coproc ? treg : treg + 1, | |
3986 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
3987 | mips_optimize = hold_mips_optimize; |
3988 | ||
0dd2d296 ILT |
3989 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3990 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 3991 | used_at && mips_noat), |
0dd2d296 ILT |
3992 | offset_expr.X_add_symbol, (long) 0, |
3993 | (char *) NULL); | |
777ad64d ILT |
3994 | |
3995 | /* We just generated two relocs. When tc_gen_reloc | |
3996 | handles this case, it will skip the first reloc and | |
3997 | handle the second. The second reloc already has an | |
3998 | extra addend of 4, which we added above. We must | |
3999 | subtract it out, and then subtract another 4 to make | |
4000 | the first reloc come out right. The second reloc | |
4001 | will come out right because we are going to add 4 to | |
4002 | offset_expr when we build its instruction below. */ | |
4003 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4004 | offset_expr.X_op = O_constant; |
4005 | } | |
4006 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4007 | if (p != NULL) | |
4008 | p += 4; | |
4009 | if (breg != 0) | |
4010 | { | |
4011 | macro_build (p, &icnt, (expressionS *) NULL, | |
4012 | mips_isa < 3 ? "addu" : "daddu", | |
4013 | "d,v,t", AT, breg, AT); | |
4014 | if (p != NULL) | |
4015 | p += 4; | |
4016 | } | |
4017 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4018 | coproc ? treg + 1 : treg, | |
4019 | (int) BFD_RELOC_LO16, AT); | |
4020 | if (p != NULL) | |
4021 | p += 4; | |
4022 | /* FIXME: How do we handle overflow here? */ | |
4023 | offset_expr.X_add_number += 4; | |
4024 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4025 | coproc ? treg : treg + 1, | |
4026 | (int) BFD_RELOC_LO16, AT); | |
4027 | } | |
fb251650 | 4028 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4029 | { |
0dd2d296 ILT |
4030 | int off; |
4031 | ||
4032 | /* If this is a reference to an external symbol, we want | |
4033 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4034 | nop | |
4035 | <op> $treg,0($at) | |
4036 | <op> $treg+1,4($at) | |
4037 | Otherwise we want | |
4038 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4039 | nop | |
4040 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4041 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4042 | If there is a base register we add it to $at before the | |
4043 | lwc1 instructions. If there is a constant we include it | |
4044 | in the lwc1 instructions. */ | |
4045 | used_at = 1; | |
4046 | expr1.X_add_number = offset_expr.X_add_number; | |
4047 | offset_expr.X_add_number = 0; | |
4048 | if (expr1.X_add_number < -0x8000 | |
4049 | || expr1.X_add_number >= 0x8000 - 4) | |
4050 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4051 | if (breg == 0) | |
4052 | off = 0; | |
4053 | else | |
4054 | off = 4; | |
8ea7f4e8 | 4055 | frag_grow (24 + off); |
0dd2d296 ILT |
4056 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4057 | mips_isa < 3 ? "lw" : "ld", | |
4058 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4059 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4060 | if (breg != 0) |
0dd2d296 | 4061 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4062 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4063 | "d,v,t", AT, breg, AT); |
4064 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4065 | coproc ? treg + 1 : treg, | |
4066 | (int) BFD_RELOC_LO16, AT); | |
4067 | expr1.X_add_number += 4; | |
55933a58 ILT |
4068 | |
4069 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4070 | nop. */ | |
4071 | hold_mips_optimize = mips_optimize; | |
4072 | mips_optimize = 2; | |
0dd2d296 ILT |
4073 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4074 | coproc ? treg : treg + 1, | |
4075 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4076 | mips_optimize = hold_mips_optimize; |
4077 | ||
0dd2d296 ILT |
4078 | (void) frag_var (rs_machine_dependent, 0, 0, |
4079 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4080 | offset_expr.X_add_symbol, (long) 0, | |
4081 | (char *) NULL); | |
8358c818 | 4082 | } |
fb251650 ILT |
4083 | else if (mips_pic == SVR4_PIC) |
4084 | { | |
4085 | int gpdel, off; | |
4086 | ||
4087 | /* If this is a reference to an external symbol, we want | |
4088 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4089 | addu $at,$at,$gp | |
4090 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4091 | nop | |
4092 | <op> $treg,0($at) | |
4093 | <op> $treg+1,4($at) | |
4094 | Otherwise we want | |
4095 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4096 | nop | |
4097 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4098 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4099 | If there is a base register we add it to $at before the | |
4100 | lwc1 instructions. If there is a constant we include it | |
4101 | in the lwc1 instructions. */ | |
4102 | used_at = 1; | |
4103 | expr1.X_add_number = offset_expr.X_add_number; | |
4104 | offset_expr.X_add_number = 0; | |
4105 | if (expr1.X_add_number < -0x8000 | |
4106 | || expr1.X_add_number >= 0x8000 - 4) | |
4107 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4108 | if (reg_needs_delay (GP)) | |
4109 | gpdel = 4; | |
4110 | else | |
4111 | gpdel = 0; | |
4112 | if (breg == 0) | |
4113 | off = 0; | |
4114 | else | |
4115 | off = 4; | |
4116 | frag_grow (56); | |
4117 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4118 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4119 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4120 | mips_isa < 3 ? "addu" : "daddu", | |
4121 | "d,v,t", AT, AT, GP); | |
4122 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4123 | mips_isa < 3 ? "lw" : "ld", | |
4124 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
4125 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4126 | if (breg != 0) | |
4127 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4128 | mips_isa < 3 ? "addu" : "daddu", | |
4129 | "d,v,t", AT, breg, AT); | |
4130 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4131 | coproc ? treg + 1 : treg, | |
4132 | (int) BFD_RELOC_LO16, AT); | |
4133 | expr1.X_add_number += 4; | |
4134 | ||
4135 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4136 | nop. */ | |
4137 | hold_mips_optimize = mips_optimize; | |
4138 | mips_optimize = 2; | |
4139 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4140 | coproc ? treg : treg + 1, | |
4141 | (int) BFD_RELOC_LO16, AT); | |
4142 | mips_optimize = hold_mips_optimize; | |
4143 | expr1.X_add_number -= 4; | |
4144 | ||
4145 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
4146 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
4147 | 8 + gpdel + off, 1, 0), | |
4148 | offset_expr.X_add_symbol, (long) 0, | |
4149 | (char *) NULL); | |
4150 | if (gpdel > 0) | |
4151 | { | |
4152 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4153 | p += 4; | |
4154 | } | |
4155 | macro_build (p, &icnt, &offset_expr, | |
4156 | mips_isa < 3 ? "lw" : "ld", | |
4157 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4158 | p += 4; | |
4159 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4160 | p += 4; | |
4161 | if (breg != 0) | |
4162 | { | |
4163 | macro_build (p, &icnt, (expressionS *) NULL, | |
4164 | mips_isa < 3 ? "addu" : "daddu", | |
4165 | "d,v,t", AT, breg, AT); | |
4166 | p += 4; | |
4167 | } | |
4168 | macro_build (p, &icnt, &expr1, s, fmt, | |
4169 | coproc ? treg + 1 : treg, | |
4170 | (int) BFD_RELOC_LO16, AT); | |
4171 | p += 4; | |
4172 | expr1.X_add_number += 4; | |
4173 | ||
4174 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4175 | nop. */ | |
4176 | hold_mips_optimize = mips_optimize; | |
4177 | mips_optimize = 2; | |
4178 | macro_build (p, &icnt, &expr1, s, fmt, | |
4179 | coproc ? treg : treg + 1, | |
4180 | (int) BFD_RELOC_LO16, AT); | |
4181 | mips_optimize = hold_mips_optimize; | |
4182 | } | |
d9aba805 ILT |
4183 | else if (mips_pic == EMBEDDED_PIC) |
4184 | { | |
4185 | /* If there is no base register, we use | |
4186 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4187 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4188 | If we have a base register, we use | |
4189 | addu $at,$breg,$gp | |
4190 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4191 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4192 | */ | |
4193 | if (breg == 0) | |
4194 | { | |
4195 | tempreg = GP; | |
4196 | used_at = 0; | |
4197 | } | |
4198 | else | |
4199 | { | |
4200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4201 | mips_isa < 3 ? "addu" : "daddu", | |
4202 | "d,v,t", AT, breg, GP); | |
4203 | tempreg = AT; | |
4204 | used_at = 1; | |
4205 | } | |
4206 | ||
4207 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4208 | coproc ? treg + 1 : treg, | |
4209 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4210 | offset_expr.X_add_number += 4; | |
4211 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4212 | coproc ? treg : treg + 1, | |
4213 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4214 | } | |
4215 | else | |
4216 | abort (); | |
0dd2d296 ILT |
4217 | |
4218 | if (! used_at) | |
4219 | return; | |
4220 | ||
4221 | break; | |
4222 | ||
4223 | case M_LD_OB: | |
4224 | s = "lw"; | |
4225 | goto sd_ob; | |
4226 | case M_SD_OB: | |
4227 | s = "sw"; | |
4228 | sd_ob: | |
4229 | assert (mips_isa < 3); | |
4230 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
4231 | (int) BFD_RELOC_LO16, breg); | |
4232 | offset_expr.X_add_number += 4; | |
4233 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
4234 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 4235 | return; |
917fae09 SS |
4236 | #ifdef LOSING_COMPILER |
4237 | default: | |
4238 | macro2 (ip); | |
4239 | return; | |
4240 | } | |
4241 | if (mips_noat) | |
4242 | as_warn ("Macro used $at after \".set noat\""); | |
4243 | } | |
4244 | ||
4245 | static void | |
4246 | macro2 (ip) | |
4247 | struct mips_cl_insn *ip; | |
4248 | { | |
4249 | register int treg, sreg, dreg, breg; | |
4250 | int tempreg; | |
4251 | int mask; | |
4252 | int icnt = 0; | |
4253 | int used_at; | |
4254 | expressionS expr1; | |
4255 | const char *s; | |
4256 | const char *s2; | |
4257 | const char *fmt; | |
4258 | int likely = 0; | |
4259 | int dbl = 0; | |
4260 | int coproc = 0; | |
adcf2b9d ILT |
4261 | int lr = 0; |
4262 | int off; | |
917fae09 SS |
4263 | offsetT maxnum; |
4264 | bfd_reloc_code_real_type r; | |
4265 | char *p; | |
4266 | ||
4267 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4268 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4269 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4270 | mask = ip->insn_mo->mask; | |
4271 | ||
4272 | expr1.X_op = O_constant; | |
4273 | expr1.X_op_symbol = NULL; | |
4274 | expr1.X_add_symbol = NULL; | |
4275 | expr1.X_add_number = 1; | |
4276 | ||
4277 | switch (mask) | |
4278 | { | |
4279 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 4280 | |
8358c818 ILT |
4281 | case M_DMUL: |
4282 | dbl = 1; | |
3d3c5039 | 4283 | case M_MUL: |
0dd2d296 | 4284 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4285 | dbl ? "dmultu" : "multu", |
4286 | "s,t", sreg, treg); | |
0dd2d296 | 4287 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 4288 | return; |
3d3c5039 | 4289 | |
8358c818 ILT |
4290 | case M_DMUL_I: |
4291 | dbl = 1; | |
3d3c5039 | 4292 | case M_MUL_I: |
8358c818 ILT |
4293 | /* The MIPS assembler some times generates shifts and adds. I'm |
4294 | not trying to be that fancy. GCC should do this for us | |
4295 | anyway. */ | |
d8a1c247 | 4296 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4297 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4298 | dbl ? "dmult" : "mult", |
4299 | "s,t", sreg, AT); | |
0dd2d296 | 4300 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 4301 | break; |
3d3c5039 | 4302 | |
8358c818 ILT |
4303 | case M_DMULO: |
4304 | dbl = 1; | |
4305 | case M_MULO: | |
4306 | mips_emit_delays (); | |
4307 | ++mips_noreorder; | |
0dd2d296 ILT |
4308 | mips_any_noreorder = 1; |
4309 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4310 | dbl ? "dmult" : "mult", |
4311 | "s,t", sreg, treg); | |
0dd2d296 ILT |
4312 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
4313 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4314 | dbl ? "dsra32" : "sra", |
4315 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 4316 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
4317 | if (mips_trap) |
4318 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
4319 | else | |
4320 | { | |
4321 | expr1.X_add_number = 8; | |
4322 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
4323 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4324 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4325 | } | |
8358c818 | 4326 | --mips_noreorder; |
0dd2d296 | 4327 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
4328 | break; |
4329 | ||
4330 | case M_DMULOU: | |
4331 | dbl = 1; | |
4332 | case M_MULOU: | |
4333 | mips_emit_delays (); | |
4334 | ++mips_noreorder; | |
0dd2d296 ILT |
4335 | mips_any_noreorder = 1; |
4336 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
4337 | dbl ? "dmultu" : "multu", |
4338 | "s,t", sreg, treg); | |
0dd2d296 ILT |
4339 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
4340 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
4341 | if (mips_trap) |
4342 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
4343 | else | |
4344 | { | |
4345 | expr1.X_add_number = 8; | |
4346 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
4347 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4348 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4349 | } | |
8358c818 ILT |
4350 | --mips_noreorder; |
4351 | break; | |
4352 | ||
3d3c5039 | 4353 | case M_ROL: |
0dd2d296 ILT |
4354 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
4355 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
4356 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
4357 | treg); | |
4358 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 4359 | break; |
3d3c5039 ILT |
4360 | |
4361 | case M_ROL_I: | |
0dd2d296 | 4362 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
670a50eb | 4363 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 4364 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
670a50eb | 4365 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 4366 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 4367 | break; |
3d3c5039 ILT |
4368 | |
4369 | case M_ROR: | |
0dd2d296 ILT |
4370 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
4371 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
4372 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
4373 | treg); | |
4374 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 4375 | break; |
3d3c5039 ILT |
4376 | |
4377 | case M_ROR_I: | |
0dd2d296 | 4378 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
670a50eb | 4379 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 4380 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
670a50eb | 4381 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 4382 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 4383 | break; |
3d3c5039 ILT |
4384 | |
4385 | case M_S_DOB: | |
8358c818 | 4386 | assert (mips_isa < 2); |
9a7d824a ILT |
4387 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4388 | to adjust when storing to memory. */ | |
0dd2d296 | 4389 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 4390 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 4391 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4392 | offset_expr.X_add_number += 4; |
0dd2d296 | 4393 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 4394 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 4395 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4396 | return; |
3d3c5039 | 4397 | |
3d3c5039 | 4398 | case M_SEQ: |
670a50eb | 4399 | if (sreg == 0) |
0dd2d296 ILT |
4400 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4401 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 4402 | else if (treg == 0) |
0dd2d296 ILT |
4403 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4404 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
4405 | else |
4406 | { | |
0dd2d296 ILT |
4407 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4408 | sreg, treg); | |
4409 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
4410 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 4411 | } |
670a50eb | 4412 | return; |
3d3c5039 ILT |
4413 | |
4414 | case M_SEQ_I: | |
670a50eb ILT |
4415 | if (imm_expr.X_add_number == 0) |
4416 | { | |
0dd2d296 ILT |
4417 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
4418 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4419 | return; |
3d3c5039 | 4420 | } |
670a50eb ILT |
4421 | if (sreg == 0) |
4422 | { | |
9a7d824a | 4423 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 4424 | ip->insn_mo->name); |
0dd2d296 | 4425 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 4426 | return; |
3d3c5039 | 4427 | } |
6e8dda9c | 4428 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 4429 | { |
0dd2d296 ILT |
4430 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
4431 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4432 | used_at = 0; |
6e8dda9c ILT |
4433 | } |
4434 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
4435 | { | |
4436 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4437 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 4438 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
4439 | "t,r,j", dreg, sreg, |
4440 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
4441 | used_at = 0; |
4442 | } | |
4443 | else | |
4444 | { | |
d8a1c247 | 4445 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4446 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4447 | sreg, AT); | |
670a50eb ILT |
4448 | used_at = 1; |
4449 | } | |
0dd2d296 | 4450 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 4451 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
4452 | if (used_at) |
4453 | break; | |
4454 | return; | |
3d3c5039 ILT |
4455 | |
4456 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
4457 | s = "slt"; |
4458 | goto sge; | |
3d3c5039 | 4459 | case M_SGEU: |
670a50eb | 4460 | s = "sltu"; |
3d3c5039 | 4461 | sge: |
0dd2d296 ILT |
4462 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
4463 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4464 | (int) BFD_RELOC_LO16); |
670a50eb | 4465 | return; |
3d3c5039 | 4466 | |
670a50eb | 4467 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 4468 | case M_SGEU_I: |
6e8dda9c | 4469 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4470 | { |
0dd2d296 | 4471 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 4472 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 4473 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
4474 | used_at = 0; |
4475 | } | |
4476 | else | |
4477 | { | |
d8a1c247 | 4478 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4479 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
4480 | mask == M_SGE_I ? "slt" : "sltu", |
4481 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
4482 | used_at = 1; |
4483 | } | |
0dd2d296 | 4484 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 4485 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
4486 | if (used_at) |
4487 | break; | |
4488 | return; | |
3d3c5039 ILT |
4489 | |
4490 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
4491 | s = "slt"; |
4492 | goto sgt; | |
3d3c5039 | 4493 | case M_SGTU: |
670a50eb | 4494 | s = "sltu"; |
3d3c5039 | 4495 | sgt: |
0dd2d296 | 4496 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 4497 | return; |
3d3c5039 | 4498 | |
670a50eb ILT |
4499 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
4500 | s = "slt"; | |
4501 | goto sgti; | |
3d3c5039 | 4502 | case M_SGTU_I: |
670a50eb | 4503 | s = "sltu"; |
3d3c5039 | 4504 | sgti: |
d8a1c247 | 4505 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4506 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 4507 | break; |
3d3c5039 | 4508 | |
670a50eb ILT |
4509 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
4510 | s = "slt"; | |
4511 | goto sle; | |
3d3c5039 | 4512 | case M_SLEU: |
670a50eb | 4513 | s = "sltu"; |
3d3c5039 | 4514 | sle: |
0dd2d296 ILT |
4515 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
4516 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4517 | (int) BFD_RELOC_LO16); |
670a50eb | 4518 | return; |
3d3c5039 | 4519 | |
670a50eb ILT |
4520 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
4521 | s = "slt"; | |
4522 | goto slei; | |
3d3c5039 | 4523 | case M_SLEU_I: |
670a50eb | 4524 | s = "sltu"; |
3d3c5039 | 4525 | slei: |
d8a1c247 | 4526 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4527 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
4528 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 4529 | (int) BFD_RELOC_LO16); |
670a50eb | 4530 | break; |
3d3c5039 ILT |
4531 | |
4532 | case M_SLT_I: | |
6e8dda9c | 4533 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4534 | { |
0dd2d296 ILT |
4535 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
4536 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4537 | return; |
3d3c5039 | 4538 | } |
d8a1c247 | 4539 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4540 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 4541 | break; |
3d3c5039 ILT |
4542 | |
4543 | case M_SLTU_I: | |
6e8dda9c | 4544 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 4545 | { |
0dd2d296 ILT |
4546 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
4547 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4548 | return; |
3d3c5039 | 4549 | } |
d8a1c247 | 4550 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4551 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
4552 | AT); | |
670a50eb | 4553 | break; |
3d3c5039 ILT |
4554 | |
4555 | case M_SNE: | |
670a50eb | 4556 | if (sreg == 0) |
0dd2d296 ILT |
4557 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4558 | treg); | |
670a50eb | 4559 | else if (treg == 0) |
0dd2d296 ILT |
4560 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4561 | sreg); | |
670a50eb ILT |
4562 | else |
4563 | { | |
0dd2d296 ILT |
4564 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4565 | sreg, treg); | |
4566 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
4567 | dreg); | |
3d3c5039 | 4568 | } |
670a50eb | 4569 | return; |
3d3c5039 ILT |
4570 | |
4571 | case M_SNE_I: | |
670a50eb ILT |
4572 | if (imm_expr.X_add_number == 0) |
4573 | { | |
0dd2d296 ILT |
4574 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
4575 | sreg); | |
670a50eb | 4576 | return; |
3d3c5039 | 4577 | } |
670a50eb ILT |
4578 | if (sreg == 0) |
4579 | { | |
9a7d824a | 4580 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 4581 | ip->insn_mo->name); |
0dd2d296 | 4582 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 4583 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 4584 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 4585 | return; |
3d3c5039 | 4586 | } |
6e8dda9c | 4587 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 4588 | { |
0dd2d296 ILT |
4589 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
4590 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4591 | used_at = 0; |
6e8dda9c ILT |
4592 | } |
4593 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
4594 | { | |
4595 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4596 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 4597 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 4598 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
4599 | used_at = 0; |
4600 | } | |
4601 | else | |
4602 | { | |
d8a1c247 | 4603 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
4604 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
4605 | sreg, AT); | |
670a50eb ILT |
4606 | used_at = 1; |
4607 | } | |
0dd2d296 | 4608 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
4609 | if (used_at) |
4610 | break; | |
4611 | return; | |
3d3c5039 | 4612 | |
8358c818 ILT |
4613 | case M_DSUB_I: |
4614 | dbl = 1; | |
3d3c5039 | 4615 | case M_SUB_I: |
6e8dda9c | 4616 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
4617 | { |
4618 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4619 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 4620 | dbl ? "daddi" : "addi", |
9226253a | 4621 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 4622 | return; |
3d3c5039 | 4623 | } |
d8a1c247 | 4624 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4625 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4626 | dbl ? "dsub" : "sub", |
4627 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 4628 | break; |
3d3c5039 | 4629 | |
8358c818 ILT |
4630 | case M_DSUBU_I: |
4631 | dbl = 1; | |
3d3c5039 | 4632 | case M_SUBU_I: |
6e8dda9c | 4633 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
4634 | { |
4635 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 4636 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 4637 | dbl ? "daddiu" : "addiu", |
9226253a | 4638 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 4639 | return; |
3d3c5039 | 4640 | } |
d8a1c247 | 4641 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 4642 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
4643 | dbl ? "dsubu" : "subu", |
4644 | "d,v,t", dreg, sreg, AT); | |
4645 | break; | |
4646 | ||
4647 | case M_TEQ_I: | |
4648 | s = "teq"; | |
4649 | goto trap; | |
4650 | case M_TGE_I: | |
4651 | s = "tge"; | |
4652 | goto trap; | |
4653 | case M_TGEU_I: | |
4654 | s = "tgeu"; | |
4655 | goto trap; | |
4656 | case M_TLT_I: | |
4657 | s = "tlt"; | |
4658 | goto trap; | |
4659 | case M_TLTU_I: | |
4660 | s = "tltu"; | |
4661 | goto trap; | |
4662 | case M_TNE_I: | |
4663 | s = "tne"; | |
4664 | trap: | |
d8a1c247 | 4665 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 4666 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 4667 | break; |
3d3c5039 ILT |
4668 | |
4669 | case M_TRUNCWD: | |
4670 | case M_TRUNCWS: | |
8358c818 | 4671 | assert (mips_isa < 2); |
670a50eb ILT |
4672 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
4673 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
4674 | ||
4675 | /* | |
4676 | * Is the double cfc1 instruction a bug in the mips assembler; | |
4677 | * or is there a reason for it? | |
4678 | */ | |
becfe05e ILT |
4679 | mips_emit_delays (); |
4680 | ++mips_noreorder; | |
0dd2d296 ILT |
4681 | mips_any_noreorder = 1; |
4682 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
4683 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
4684 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 4685 | expr1.X_add_number = 3; |
0dd2d296 | 4686 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 4687 | (int) BFD_RELOC_LO16); |
670a50eb | 4688 | expr1.X_add_number = 2; |
0dd2d296 | 4689 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 4690 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
4691 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
4692 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
4693 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 4694 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
4695 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
4696 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 4697 | --mips_noreorder; |
670a50eb | 4698 | break; |
3d3c5039 ILT |
4699 | |
4700 | case M_ULH: | |
670a50eb ILT |
4701 | s = "lb"; |
4702 | goto ulh; | |
3d3c5039 | 4703 | case M_ULHU: |
670a50eb | 4704 | s = "lbu"; |
3d3c5039 | 4705 | ulh: |
8ea7f4e8 ILT |
4706 | if (offset_expr.X_add_number >= 0x7fff) |
4707 | as_bad ("operand overflow"); | |
670a50eb | 4708 | /* avoid load delay */ |
8ea7f4e8 ILT |
4709 | if (byte_order == LITTLE_ENDIAN) |
4710 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4711 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 4712 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
4713 | if (byte_order == LITTLE_ENDIAN) |
4714 | offset_expr.X_add_number -= 1; | |
4715 | else | |
4716 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4717 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 4718 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
4719 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
4720 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 4721 | break; |
3d3c5039 | 4722 | |
adcf2b9d ILT |
4723 | case M_ULD: |
4724 | s = "ldl"; | |
4725 | s2 = "ldr"; | |
4726 | off = 7; | |
4727 | goto ulw; | |
3d3c5039 | 4728 | case M_ULW: |
adcf2b9d ILT |
4729 | s = "lwl"; |
4730 | s2 = "lwr"; | |
4731 | off = 3; | |
4732 | ulw: | |
4733 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
4734 | as_bad ("operand overflow"); |
4735 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
4736 | offset_expr.X_add_number += off; |
4737 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 4738 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 4739 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 4740 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 4741 | else |
adcf2b9d ILT |
4742 | offset_expr.X_add_number += off; |
4743 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 4744 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4745 | return; |
3d3c5039 | 4746 | |
adcf2b9d ILT |
4747 | case M_ULD_A: |
4748 | s = "ldl"; | |
4749 | s2 = "ldr"; | |
4750 | off = 7; | |
4751 | goto ulwa; | |
4752 | case M_ULW_A: | |
4753 | s = "lwl"; | |
4754 | s2 = "lwr"; | |
4755 | off = 3; | |
4756 | ulwa: | |
4757 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
4758 | if (breg != 0) |
4759 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4760 | mips_isa < 3 ? "addu" : "daddu", | |
4761 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
4762 | if (byte_order == LITTLE_ENDIAN) |
4763 | expr1.X_add_number = off; | |
4764 | else | |
4765 | expr1.X_add_number = 0; | |
4766 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
4767 | (int) BFD_RELOC_LO16, AT); | |
4768 | if (byte_order == LITTLE_ENDIAN) | |
4769 | expr1.X_add_number = 0; | |
4770 | else | |
4771 | expr1.X_add_number = off; | |
4772 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
4773 | (int) BFD_RELOC_LO16, AT); | |
4774 | break; | |
4775 | ||
3d3c5039 ILT |
4776 | case M_ULH_A: |
4777 | case M_ULHU_A: | |
0dd2d296 | 4778 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
4779 | if (breg != 0) |
4780 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4781 | mips_isa < 3 ? "addu" : "daddu", | |
4782 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
4783 | if (byte_order == BIG_ENDIAN) |
4784 | expr1.X_add_number = 0; | |
4785 | macro_build ((char *) NULL, &icnt, &expr1, | |
4786 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
4787 | (int) BFD_RELOC_LO16, AT); | |
4788 | if (byte_order == BIG_ENDIAN) | |
4789 | expr1.X_add_number = 1; | |
670a50eb | 4790 | else |
adcf2b9d ILT |
4791 | expr1.X_add_number = 0; |
4792 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
4793 | (int) BFD_RELOC_LO16, AT); | |
4794 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
4795 | treg, 8); | |
4796 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4797 | treg, AT); | |
670a50eb | 4798 | break; |
3d3c5039 ILT |
4799 | |
4800 | case M_USH: | |
8ea7f4e8 ILT |
4801 | if (offset_expr.X_add_number >= 0x7fff) |
4802 | as_bad ("operand overflow"); | |
4803 | if (byte_order == BIG_ENDIAN) | |
4804 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4805 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 4806 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 4807 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
4808 | if (byte_order == BIG_ENDIAN) |
4809 | offset_expr.X_add_number -= 1; | |
4810 | else | |
4811 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4812 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 4813 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4814 | break; |
3d3c5039 | 4815 | |
adcf2b9d ILT |
4816 | case M_USD: |
4817 | s = "sdl"; | |
4818 | s2 = "sdr"; | |
4819 | off = 7; | |
4820 | goto usw; | |
3d3c5039 | 4821 | case M_USW: |
adcf2b9d ILT |
4822 | s = "swl"; |
4823 | s2 = "swr"; | |
4824 | off = 3; | |
4825 | usw: | |
4826 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
4827 | as_bad ("operand overflow"); |
4828 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
4829 | offset_expr.X_add_number += off; |
4830 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 4831 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 4832 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 4833 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 4834 | else |
adcf2b9d ILT |
4835 | offset_expr.X_add_number += off; |
4836 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 4837 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4838 | return; |
3d3c5039 | 4839 | |
adcf2b9d ILT |
4840 | case M_USD_A: |
4841 | s = "sdl"; | |
4842 | s2 = "sdr"; | |
4843 | off = 7; | |
4844 | goto uswa; | |
3d3c5039 | 4845 | case M_USW_A: |
adcf2b9d ILT |
4846 | s = "swl"; |
4847 | s2 = "swr"; | |
4848 | off = 3; | |
4849 | uswa: | |
0dd2d296 | 4850 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
4851 | if (breg != 0) |
4852 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4853 | mips_isa < 3 ? "addu" : "daddu", | |
4854 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
4855 | if (byte_order == LITTLE_ENDIAN) |
4856 | expr1.X_add_number = off; | |
670a50eb | 4857 | else |
adcf2b9d ILT |
4858 | expr1.X_add_number = 0; |
4859 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
4860 | (int) BFD_RELOC_LO16, AT); | |
4861 | if (byte_order == LITTLE_ENDIAN) | |
4862 | expr1.X_add_number = 0; | |
4863 | else | |
4864 | expr1.X_add_number = off; | |
4865 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
4866 | (int) BFD_RELOC_LO16, AT); | |
4867 | break; | |
4868 | ||
4869 | case M_USH_A: | |
4870 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
4871 | if (breg != 0) |
4872 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4873 | mips_isa < 3 ? "addu" : "daddu", | |
4874 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
4875 | if (byte_order == LITTLE_ENDIAN) |
4876 | expr1.X_add_number = 0; | |
4877 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
4878 | (int) BFD_RELOC_LO16, AT); | |
4879 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
4880 | treg, 8); | |
4881 | if (byte_order == LITTLE_ENDIAN) | |
4882 | expr1.X_add_number = 1; | |
4883 | else | |
4884 | expr1.X_add_number = 0; | |
4885 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
4886 | (int) BFD_RELOC_LO16, AT); | |
4887 | if (byte_order == LITTLE_ENDIAN) | |
4888 | expr1.X_add_number = 0; | |
4889 | else | |
4890 | expr1.X_add_number = 1; | |
4891 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
4892 | (int) BFD_RELOC_LO16, AT); | |
4893 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
4894 | treg, 8); | |
4895 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4896 | treg, AT); | |
670a50eb | 4897 | break; |
3d3c5039 ILT |
4898 | |
4899 | default: | |
670a50eb | 4900 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 4901 | break; |
3d3c5039 | 4902 | } |
670a50eb ILT |
4903 | if (mips_noat) |
4904 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
4905 | } |
4906 | ||
4907 | ||
4908 | /* | |
4909 | This routine assembles an instruction into its binary format. As a side | |
4910 | effect it sets one of the global variables imm_reloc or offset_reloc to the | |
4911 | type of relocation to do if one of the operands is an address expression. | |
4912 | */ | |
4913 | static void | |
4914 | mips_ip (str, ip) | |
4915 | char *str; | |
4916 | struct mips_cl_insn *ip; | |
4917 | { | |
670a50eb ILT |
4918 | char *s; |
4919 | const char *args; | |
4920 | char c; | |
4921 | struct mips_opcode *insn; | |
4922 | char *argsStart; | |
4923 | unsigned int regno; | |
4924 | unsigned int lastregno = 0; | |
4925 | char *s_reset; | |
4926 | ||
4927 | insn_error = NULL; | |
4928 | ||
c625fc23 | 4929 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) |
670a50eb ILT |
4930 | continue; |
4931 | switch (*s) | |
4932 | { | |
3d3c5039 | 4933 | case '\0': |
670a50eb | 4934 | break; |
3d3c5039 ILT |
4935 | |
4936 | case ' ': | |
670a50eb ILT |
4937 | *s++ = '\0'; |
4938 | break; | |
3d3c5039 ILT |
4939 | |
4940 | default: | |
460531da | 4941 | as_fatal ("Unknown opcode: `%s'", str); |
3d3c5039 | 4942 | } |
670a50eb ILT |
4943 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
4944 | { | |
4945 | as_warn ("`%s' not in hash table.", str); | |
4946 | insn_error = "ERROR: Unrecognized opcode"; | |
4947 | return; | |
3d3c5039 | 4948 | } |
670a50eb ILT |
4949 | argsStart = s; |
4950 | for (;;) | |
4951 | { | |
8358c818 ILT |
4952 | int insn_isa; |
4953 | ||
670a50eb | 4954 | assert (strcmp (insn->name, str) == 0); |
8358c818 ILT |
4955 | |
4956 | if (insn->pinfo == INSN_MACRO) | |
4957 | insn_isa = insn->match; | |
b2b8c24e | 4958 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) |
8358c818 | 4959 | insn_isa = 2; |
b2b8c24e | 4960 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) |
8358c818 | 4961 | insn_isa = 3; |
d8a1c247 KR |
4962 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) |
4963 | insn_isa = 4; | |
8358c818 ILT |
4964 | else |
4965 | insn_isa = 1; | |
4966 | ||
b2b8c24e ILT |
4967 | if (insn_isa > mips_isa |
4968 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
e532b44c ILT |
4969 | && ! mips_4650) |
4970 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
c625fc23 JSC |
4971 | && ! mips_4010) |
4972 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
4973 | && ! mips_4100)) | |
8358c818 ILT |
4974 | { |
4975 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
4976 | && strcmp (insn->name, insn[1].name) == 0) | |
4977 | { | |
4978 | ++insn; | |
4979 | continue; | |
4980 | } | |
8bbad6fd | 4981 | as_warn ("Instruction not supported on this processor"); |
8358c818 ILT |
4982 | } |
4983 | ||
670a50eb ILT |
4984 | ip->insn_mo = insn; |
4985 | ip->insn_opcode = insn->match; | |
4986 | for (args = insn->args;; ++args) | |
4987 | { | |
4988 | if (*s == ' ') | |
4989 | ++s; | |
4990 | switch (*args) | |
4991 | { | |
4992 | case '\0': /* end of args */ | |
4993 | if (*s == '\0') | |
4994 | return; | |
4995 | break; | |
3d3c5039 ILT |
4996 | |
4997 | case ',': | |
670a50eb ILT |
4998 | if (*s++ == *args) |
4999 | continue; | |
5000 | s--; | |
5001 | switch (*++args) | |
5002 | { | |
3d3c5039 ILT |
5003 | case 'r': |
5004 | case 'v': | |
670a50eb ILT |
5005 | ip->insn_opcode |= lastregno << 21; |
5006 | continue; | |
3d3c5039 ILT |
5007 | |
5008 | case 'w': | |
5009 | case 'W': | |
670a50eb ILT |
5010 | ip->insn_opcode |= lastregno << 16; |
5011 | continue; | |
3d3c5039 ILT |
5012 | |
5013 | case 'V': | |
670a50eb ILT |
5014 | ip->insn_opcode |= lastregno << 11; |
5015 | continue; | |
3d3c5039 | 5016 | } |
670a50eb | 5017 | break; |
3d3c5039 ILT |
5018 | |
5019 | case '(': | |
670a50eb ILT |
5020 | /* handle optional base register. |
5021 | Either the base register is omitted or | |
5022 | we must have a left paren. */ | |
5023 | /* this is dependent on the next operand specifier | |
5024 | is a 'b' for base register */ | |
5025 | assert (args[1] == 'b'); | |
5026 | if (*s == '\0') | |
5027 | return; | |
3d3c5039 | 5028 | |
670a50eb ILT |
5029 | case ')': /* these must match exactly */ |
5030 | if (*s++ == *args) | |
3d3c5039 | 5031 | continue; |
670a50eb ILT |
5032 | break; |
5033 | ||
5034 | case '<': /* must be at least one digit */ | |
5035 | /* | |
5036 | * According to the manual, if the shift amount is greater | |
5037 | * than 31 or less than 0 the the shift amount should be | |
5038 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 5039 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
5040 | */ |
5041 | my_getExpression (&imm_expr, s); | |
5042 | check_absolute_expr (ip, &imm_expr); | |
5043 | if ((unsigned long) imm_expr.X_add_number > 31) | |
5044 | { | |
58d4951d ILT |
5045 | as_warn ("Improper shift amount (%ld)", |
5046 | (long) imm_expr.X_add_number); | |
9226253a | 5047 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
5048 | } |
5049 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 5050 | imm_expr.X_op = O_absent; |
670a50eb ILT |
5051 | s = expr_end; |
5052 | continue; | |
5053 | ||
56c96faa ILT |
5054 | case '>': /* shift amount minus 32 */ |
5055 | my_getExpression (&imm_expr, s); | |
5056 | check_absolute_expr (ip, &imm_expr); | |
5057 | if ((unsigned long) imm_expr.X_add_number < 32 | |
5058 | || (unsigned long) imm_expr.X_add_number > 63) | |
5059 | break; | |
5060 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
5061 | imm_expr.X_op = O_absent; | |
5062 | s = expr_end; | |
5063 | continue; | |
5064 | ||
9226253a | 5065 | case 'k': /* cache code */ |
d8a1c247 | 5066 | case 'h': /* prefx code */ |
9226253a ILT |
5067 | my_getExpression (&imm_expr, s); |
5068 | check_absolute_expr (ip, &imm_expr); | |
5069 | if ((unsigned long) imm_expr.X_add_number > 31) | |
5070 | { | |
d8a1c247 KR |
5071 | as_warn ("Invalid value for `%s' (%lu)", |
5072 | ip->insn_mo->name, | |
9226253a ILT |
5073 | (unsigned long) imm_expr.X_add_number); |
5074 | imm_expr.X_add_number &= 0x1f; | |
5075 | } | |
d8a1c247 KR |
5076 | if (*args == 'k') |
5077 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
5078 | else | |
5079 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
5080 | imm_expr.X_op = O_absent; |
5081 | s = expr_end; | |
5082 | continue; | |
5083 | ||
670a50eb ILT |
5084 | case 'c': /* break code */ |
5085 | my_getExpression (&imm_expr, s); | |
5086 | check_absolute_expr (ip, &imm_expr); | |
5087 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
5088 | as_warn ("Illegal break code (%ld)", |
5089 | (long) imm_expr.X_add_number); | |
670a50eb | 5090 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 5091 | imm_expr.X_op = O_absent; |
670a50eb ILT |
5092 | s = expr_end; |
5093 | continue; | |
5094 | ||
918692a5 ILT |
5095 | case 'B': /* syscall code */ |
5096 | my_getExpression (&imm_expr, s); | |
5097 | check_absolute_expr (ip, &imm_expr); | |
5098 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
5099 | as_warn ("Illegal syscall code (%ld)", |
5100 | (long) imm_expr.X_add_number); | |
918692a5 | 5101 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 5102 | imm_expr.X_op = O_absent; |
918692a5 ILT |
5103 | s = expr_end; |
5104 | continue; | |
5105 | ||
0aa07269 ILT |
5106 | case 'C': /* Coprocessor code */ |
5107 | my_getExpression (&imm_expr, s); | |
5108 | check_absolute_expr (ip, &imm_expr); | |
5109 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
5110 | { | |
58d4951d ILT |
5111 | as_warn ("Coproccesor code > 25 bits (%ld)", |
5112 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
5113 | imm_expr.X_add_number &= ((1<<25) - 1); |
5114 | } | |
5115 | ip->insn_opcode |= imm_expr.X_add_number; | |
5116 | imm_expr.X_op = O_absent; | |
5117 | s = expr_end; | |
5118 | continue; | |
5119 | ||
670a50eb ILT |
5120 | case 'b': /* base register */ |
5121 | case 'd': /* destination register */ | |
5122 | case 's': /* source register */ | |
5123 | case 't': /* target register */ | |
5124 | case 'r': /* both target and source */ | |
5125 | case 'v': /* both dest and source */ | |
5126 | case 'w': /* both dest and target */ | |
918692a5 ILT |
5127 | case 'E': /* coprocessor target register */ |
5128 | case 'G': /* coprocessor destination register */ | |
8358c818 | 5129 | case 'x': /* ignore register name */ |
ff3a5c18 | 5130 | case 'z': /* must be zero register */ |
670a50eb ILT |
5131 | s_reset = s; |
5132 | if (s[0] == '$') | |
5133 | { | |
5134 | if (isdigit (s[1])) | |
5135 | { | |
5136 | ++s; | |
5137 | regno = 0; | |
5138 | do | |
5139 | { | |
5140 | regno *= 10; | |
5141 | regno += *s - '0'; | |
5142 | ++s; | |
5143 | } | |
5144 | while (isdigit (*s)); | |
0aa07269 ILT |
5145 | if (regno > 31) |
5146 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 5147 | } |
0dd2d296 ILT |
5148 | else if (*args == 'E' || *args == 'G') |
5149 | goto notreg; | |
5150 | else | |
670a50eb | 5151 | { |
0aa07269 ILT |
5152 | if (s[1] == 'f' && s[2] == 'p') |
5153 | { | |
5154 | s += 3; | |
9226253a | 5155 | regno = FP; |
0aa07269 ILT |
5156 | } |
5157 | else if (s[1] == 's' && s[2] == 'p') | |
5158 | { | |
5159 | s += 3; | |
9226253a | 5160 | regno = SP; |
0aa07269 ILT |
5161 | } |
5162 | else if (s[1] == 'g' && s[2] == 'p') | |
5163 | { | |
5164 | s += 3; | |
9226253a | 5165 | regno = GP; |
0aa07269 ILT |
5166 | } |
5167 | else if (s[1] == 'a' && s[2] == 't') | |
5168 | { | |
5169 | s += 3; | |
9226253a | 5170 | regno = AT; |
0aa07269 | 5171 | } |
b2b8c24e ILT |
5172 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
5173 | { | |
5174 | s += 4; | |
5175 | regno = KT0; | |
5176 | } | |
5177 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
5178 | { | |
5179 | s += 4; | |
5180 | regno = KT1; | |
5181 | } | |
0aa07269 ILT |
5182 | else |
5183 | goto notreg; | |
670a50eb | 5184 | } |
13fe1379 ILT |
5185 | if (regno == AT && ! mips_noat) |
5186 | as_warn ("Used $at without \".set noat\""); | |
670a50eb ILT |
5187 | c = *args; |
5188 | if (*s == ' ') | |
5189 | s++; | |
5190 | if (args[1] != *s) | |
5191 | { | |
5192 | if (c == 'r' || c == 'v' || c == 'w') | |
5193 | { | |
5194 | regno = lastregno; | |
5195 | s = s_reset; | |
5196 | args++; | |
5197 | } | |
5198 | } | |
ff3a5c18 ILT |
5199 | /* 'z' only matches $0. */ |
5200 | if (c == 'z' && regno != 0) | |
5201 | break; | |
670a50eb ILT |
5202 | switch (c) |
5203 | { | |
3d3c5039 ILT |
5204 | case 'r': |
5205 | case 's': | |
5206 | case 'v': | |
5207 | case 'b': | |
670a50eb ILT |
5208 | ip->insn_opcode |= regno << 21; |
5209 | break; | |
3d3c5039 | 5210 | case 'd': |
918692a5 | 5211 | case 'G': |
670a50eb ILT |
5212 | ip->insn_opcode |= regno << 11; |
5213 | break; | |
3d3c5039 ILT |
5214 | case 'w': |
5215 | case 't': | |
918692a5 | 5216 | case 'E': |
670a50eb | 5217 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
5218 | break; |
5219 | case 'x': | |
5220 | /* This case exists because on the r3000 trunc | |
5221 | expands into a macro which requires a gp | |
5222 | register. On the r6000 or r4000 it is | |
5223 | assembled into a single instruction which | |
5224 | ignores the register. Thus the insn version | |
5225 | is MIPS_ISA2 and uses 'x', and the macro | |
5226 | version is MIPS_ISA1 and uses 't'. */ | |
5227 | break; | |
ff3a5c18 ILT |
5228 | case 'z': |
5229 | /* This case is for the div instruction, which | |
5230 | acts differently if the destination argument | |
5231 | is $0. This only matches $0, and is checked | |
5232 | outside the switch. */ | |
5233 | break; | |
3d3c5039 | 5234 | } |
670a50eb ILT |
5235 | lastregno = regno; |
5236 | continue; | |
3d3c5039 ILT |
5237 | } |
5238 | notreg: | |
670a50eb ILT |
5239 | switch (*args++) |
5240 | { | |
3d3c5039 ILT |
5241 | case 'r': |
5242 | case 'v': | |
670a50eb ILT |
5243 | ip->insn_opcode |= lastregno << 21; |
5244 | continue; | |
3d3c5039 | 5245 | case 'w': |
670a50eb ILT |
5246 | ip->insn_opcode |= lastregno << 16; |
5247 | continue; | |
3d3c5039 | 5248 | } |
670a50eb | 5249 | break; |
3d3c5039 | 5250 | |
670a50eb ILT |
5251 | case 'D': /* floating point destination register */ |
5252 | case 'S': /* floating point source register */ | |
5253 | case 'T': /* floating point target register */ | |
d8a1c247 | 5254 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
5255 | case 'V': |
5256 | case 'W': | |
670a50eb ILT |
5257 | s_reset = s; |
5258 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
5259 | { | |
5260 | s += 2; | |
5261 | regno = 0; | |
5262 | do | |
5263 | { | |
5264 | regno *= 10; | |
5265 | regno += *s - '0'; | |
5266 | ++s; | |
5267 | } | |
5268 | while (isdigit (*s)); | |
5269 | ||
5270 | if (regno > 31) | |
5271 | as_bad ("Invalid float register number (%d)", regno); | |
5272 | ||
9226253a ILT |
5273 | if ((regno & 1) != 0 |
5274 | && mips_isa < 3 | |
5275 | && ! (strcmp (str, "mtc1") == 0 || | |
5276 | strcmp (str, "mfc1") == 0 || | |
5277 | strcmp (str, "lwc1") == 0 || | |
5278 | strcmp (str, "swc1") == 0)) | |
670a50eb ILT |
5279 | as_warn ("Float register should be even, was %d", |
5280 | regno); | |
5281 | ||
5282 | c = *args; | |
5283 | if (*s == ' ') | |
5284 | s++; | |
5285 | if (args[1] != *s) | |
5286 | { | |
5287 | if (c == 'V' || c == 'W') | |
5288 | { | |
5289 | regno = lastregno; | |
5290 | s = s_reset; | |
5291 | args++; | |
3d3c5039 ILT |
5292 | } |
5293 | } | |
670a50eb ILT |
5294 | switch (c) |
5295 | { | |
3d3c5039 | 5296 | case 'D': |
670a50eb ILT |
5297 | ip->insn_opcode |= regno << 6; |
5298 | break; | |
3d3c5039 ILT |
5299 | case 'V': |
5300 | case 'S': | |
670a50eb ILT |
5301 | ip->insn_opcode |= regno << 11; |
5302 | break; | |
3d3c5039 ILT |
5303 | case 'W': |
5304 | case 'T': | |
670a50eb | 5305 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
5306 | break; |
5307 | case 'R': | |
5308 | ip->insn_opcode |= regno << 21; | |
5309 | break; | |
3d3c5039 | 5310 | } |
670a50eb ILT |
5311 | lastregno = regno; |
5312 | continue; | |
3d3c5039 | 5313 | } |
670a50eb ILT |
5314 | switch (*args++) |
5315 | { | |
3d3c5039 | 5316 | case 'V': |
670a50eb ILT |
5317 | ip->insn_opcode |= lastregno << 11; |
5318 | continue; | |
3d3c5039 | 5319 | case 'W': |
670a50eb ILT |
5320 | ip->insn_opcode |= lastregno << 16; |
5321 | continue; | |
3d3c5039 | 5322 | } |
670a50eb | 5323 | break; |
3d3c5039 ILT |
5324 | |
5325 | case 'I': | |
670a50eb | 5326 | my_getExpression (&imm_expr, s); |
847a01cd ILT |
5327 | if (imm_expr.X_op != O_big) |
5328 | check_absolute_expr (ip, &imm_expr); | |
670a50eb ILT |
5329 | s = expr_end; |
5330 | continue; | |
3d3c5039 ILT |
5331 | |
5332 | case 'A': | |
670a50eb ILT |
5333 | my_getExpression (&offset_expr, s); |
5334 | imm_reloc = BFD_RELOC_32; | |
5335 | s = expr_end; | |
5336 | continue; | |
3d3c5039 ILT |
5337 | |
5338 | case 'F': | |
19ed8960 ILT |
5339 | case 'L': |
5340 | case 'f': | |
5341 | case 'l': | |
5342 | { | |
5343 | int f64; | |
5344 | char *save_in; | |
5345 | char *err; | |
5346 | unsigned char temp[8]; | |
604633ae ILT |
5347 | int len; |
5348 | unsigned int length; | |
19ed8960 ILT |
5349 | segT seg; |
5350 | subsegT subseg; | |
5351 | char *p; | |
5352 | ||
5353 | /* These only appear as the last operand in an | |
5354 | instruction, and every instruction that accepts | |
5355 | them in any variant accepts them in all variants. | |
5356 | This means we don't have to worry about backing out | |
5357 | any changes if the instruction does not match. | |
5358 | ||
5359 | The difference between them is the size of the | |
5360 | floating point constant and where it goes. For 'F' | |
5361 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
5362 | is 32 bits. Where the constant is placed is based | |
5363 | on how the MIPS assembler does things: | |
5364 | F -- .rdata | |
5365 | L -- .lit8 | |
5366 | f -- immediate value | |
5367 | l -- .lit4 | |
0dd2d296 | 5368 | |
55933a58 ILT |
5369 | The .lit4 and .lit8 sections are only used if |
5370 | permitted by the -G argument. | |
5371 | ||
5372 | When generating embedded PIC code, we use the | |
5373 | .lit8 section but not the .lit4 section (we can do | |
5374 | .lit4 inline easily; we need to put .lit8 | |
5375 | somewhere in the data segment, and using .lit8 | |
5376 | permits the linker to eventually combine identical | |
5377 | .lit8 entries). */ | |
19ed8960 ILT |
5378 | |
5379 | f64 = *args == 'F' || *args == 'L'; | |
5380 | ||
5381 | save_in = input_line_pointer; | |
5382 | input_line_pointer = s; | |
604633ae ILT |
5383 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
5384 | length = len; | |
19ed8960 ILT |
5385 | s = input_line_pointer; |
5386 | input_line_pointer = save_in; | |
5387 | if (err != NULL && *err != '\0') | |
5388 | { | |
5389 | as_bad ("Bad floating point constant: %s", err); | |
5390 | memset (temp, '\0', sizeof temp); | |
5391 | length = f64 ? 8 : 4; | |
5392 | } | |
5393 | ||
5394 | assert (length == (f64 ? 8 : 4)); | |
5395 | ||
0dd2d296 | 5396 | if (*args == 'f' |
55933a58 | 5397 | || (*args == 'l' |
1dc1e798 KR |
5398 | && (! USE_GLOBAL_POINTER_OPT |
5399 | || mips_pic == EMBEDDED_PIC | |
1113140a | 5400 | || g_switch_value < 4) |
1113140a | 5401 | )) |
19ed8960 ILT |
5402 | { |
5403 | imm_expr.X_op = O_constant; | |
5404 | if (byte_order == LITTLE_ENDIAN) | |
5405 | imm_expr.X_add_number = | |
5406 | (((((((int) temp[3] << 8) | |
5407 | | temp[2]) << 8) | |
5408 | | temp[1]) << 8) | |
5409 | | temp[0]); | |
5410 | else | |
5411 | imm_expr.X_add_number = | |
5412 | (((((((int) temp[0] << 8) | |
5413 | | temp[1]) << 8) | |
5414 | | temp[2]) << 8) | |
5415 | | temp[3]); | |
5416 | } | |
5417 | else | |
5418 | { | |
0dd2d296 ILT |
5419 | const char *newname; |
5420 | segT new_seg; | |
5421 | ||
19ed8960 ILT |
5422 | /* Switch to the right section. */ |
5423 | seg = now_seg; | |
5424 | subseg = now_subseg; | |
5425 | switch (*args) | |
5426 | { | |
0dd2d296 | 5427 | default: /* unused default case avoids warnings. */ |
19ed8960 | 5428 | case 'L': |
1113140a | 5429 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 5430 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 5431 | newname = ".lit8"; |
0dd2d296 ILT |
5432 | break; |
5433 | case 'F': | |
d2c71068 | 5434 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
5435 | break; |
5436 | case 'l': | |
1dc1e798 KR |
5437 | assert (!USE_GLOBAL_POINTER_OPT |
5438 | || g_switch_value >= 4); | |
0dd2d296 | 5439 | newname = ".lit4"; |
19ed8960 ILT |
5440 | break; |
5441 | } | |
0dd2d296 | 5442 | new_seg = subseg_new (newname, (subsegT) 0); |
0221ddf7 | 5443 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
5444 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
5445 | record_alignment (new_seg, 4); | |
5446 | else | |
5447 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
5448 | if (seg == now_seg) |
5449 | as_bad ("Can't use floating point insn in this section"); | |
5450 | ||
5451 | /* Set the argument to the current address in the | |
6e8dda9c | 5452 | section. */ |
19ed8960 ILT |
5453 | offset_expr.X_op = O_symbol; |
5454 | offset_expr.X_add_symbol = | |
5455 | symbol_new ("L0\001", now_seg, | |
5456 | (valueT) frag_now_fix (), frag_now); | |
5457 | offset_expr.X_add_number = 0; | |
5458 | ||
5459 | /* Put the floating point number into the section. */ | |
604633ae | 5460 | p = frag_more ((int) length); |
19ed8960 ILT |
5461 | memcpy (p, temp, length); |
5462 | ||
5463 | /* Switch back to the original section. */ | |
5464 | subseg_set (seg, subseg); | |
5465 | } | |
5466 | } | |
670a50eb ILT |
5467 | continue; |
5468 | ||
5469 | case 'i': /* 16 bit unsigned immediate */ | |
5470 | case 'j': /* 16 bit signed immediate */ | |
5471 | imm_reloc = BFD_RELOC_LO16; | |
5472 | c = my_getSmallExpression (&imm_expr, s); | |
5473 | if (c) | |
5474 | { | |
5475 | if (c != 'l') | |
5476 | { | |
5ac34ac3 | 5477 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
5478 | imm_expr.X_add_number = |
5479 | (imm_expr.X_add_number >> 16) & 0xffff; | |
5480 | else if (c == 'h') | |
5481 | imm_reloc = BFD_RELOC_HI16_S; | |
5482 | else | |
5483 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 5484 | } |
670a50eb | 5485 | } |
847a01cd | 5486 | else if (imm_expr.X_op != O_big) |
670a50eb ILT |
5487 | check_absolute_expr (ip, &imm_expr); |
5488 | if (*args == 'i') | |
5489 | { | |
847a01cd ILT |
5490 | if (imm_expr.X_op == O_big |
5491 | || imm_expr.X_add_number < 0 | |
6e8dda9c | 5492 | || imm_expr.X_add_number >= 0x10000) |
99c24539 ILT |
5493 | { |
5494 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5495 | !strcmp (insn->name, insn[1].name)) | |
5496 | break; | |
5497 | as_bad ("16 bit expression not in range 0..65535"); | |
5498 | } | |
670a50eb ILT |
5499 | } |
5500 | else | |
5501 | { | |
d9aba805 ILT |
5502 | int more; |
5503 | offsetT max; | |
5504 | ||
be22008b ILT |
5505 | /* The upper bound should be 0x8000, but |
5506 | unfortunately the MIPS assembler accepts numbers | |
5507 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
5508 | we want to be compatible. We only permit this |
5509 | extended range for an instruction which does not | |
5510 | provide any further alternates, since those | |
5511 | alternates may handle other cases. People should | |
5512 | use the numbers they mean, rather than relying on | |
5513 | a mysterious sign extension. */ | |
5514 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5515 | strcmp (insn->name, insn[1].name) == 0); | |
5516 | if (more) | |
5517 | max = 0x8000; | |
5518 | else | |
5519 | max = 0x10000; | |
847a01cd ILT |
5520 | if (imm_expr.X_op == O_big |
5521 | || imm_expr.X_add_number < -0x8000 | |
d8a1c247 KR |
5522 | || imm_expr.X_add_number >= max |
5523 | || (more | |
5524 | && imm_expr.X_add_number < 0 | |
5525 | && mips_isa >= 3 | |
5526 | && imm_expr.X_unsigned | |
5527 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 5528 | { |
d9aba805 | 5529 | if (more) |
99c24539 ILT |
5530 | break; |
5531 | as_bad ("16 bit expression not in range -32768..32767"); | |
5532 | } | |
3d3c5039 | 5533 | } |
670a50eb ILT |
5534 | s = expr_end; |
5535 | continue; | |
5536 | ||
5537 | case 'o': /* 16 bit offset */ | |
5538 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
5539 | |
5540 | /* If this value won't fit into a 16 bit offset, then go | |
5541 | find a macro that will generate the 32 bit offset | |
5542 | code pattern. As a special hack, we accept the | |
5543 | difference of two local symbols as a constant. This | |
5544 | is required to suppose embedded PIC switches, which | |
5545 | use an instruction which looks like | |
5546 | lw $4,$L12-$LS12($4) | |
5547 | The problem with handling this in a more general | |
5548 | fashion is that the macro function doesn't expect to | |
5549 | see anything which can be handled in a single | |
5550 | constant instruction. */ | |
6f0b87c3 SS |
5551 | if (c == 0 |
5552 | && (offset_expr.X_op != O_constant | |
5553 | || offset_expr.X_add_number >= 0x8000 | |
5554 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
5555 | && (mips_pic != EMBEDDED_PIC |
5556 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
5557 | || now_seg != text_section |
5558 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
5559 | != text_section))) | |
670a50eb | 5560 | break; |
3d3c5039 | 5561 | |
670a50eb ILT |
5562 | offset_reloc = BFD_RELOC_LO16; |
5563 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
5564 | { |
5565 | assert (offset_expr.X_op == O_constant); | |
5566 | offset_expr.X_add_number = | |
5567 | (offset_expr.X_add_number >> 16) & 0xffff; | |
5568 | } | |
670a50eb ILT |
5569 | s = expr_end; |
5570 | continue; | |
5571 | ||
5572 | case 'p': /* pc relative offset */ | |
5573 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
5574 | my_getExpression (&offset_expr, s); | |
5575 | s = expr_end; | |
5576 | continue; | |
5577 | ||
5578 | case 'u': /* upper 16 bits */ | |
5579 | c = my_getSmallExpression (&imm_expr, s); | |
36a87ad7 ILT |
5580 | if (imm_expr.X_op == O_constant |
5581 | && (imm_expr.X_add_number < 0 | |
5582 | || imm_expr.X_add_number >= 0x10000)) | |
670a50eb ILT |
5583 | as_bad ("lui expression not in range 0..65535"); |
5584 | imm_reloc = BFD_RELOC_LO16; | |
5585 | if (c) | |
5586 | { | |
5587 | if (c != 'l') | |
5588 | { | |
5ac34ac3 | 5589 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
5590 | imm_expr.X_add_number = |
5591 | (imm_expr.X_add_number >> 16) & 0xffff; | |
5592 | else if (c == 'h') | |
5593 | imm_reloc = BFD_RELOC_HI16_S; | |
5594 | else | |
5595 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 ILT |
5596 | } |
5597 | } | |
670a50eb ILT |
5598 | s = expr_end; |
5599 | continue; | |
3d3c5039 | 5600 | |
670a50eb ILT |
5601 | case 'a': /* 26 bit address */ |
5602 | my_getExpression (&offset_expr, s); | |
5603 | s = expr_end; | |
5604 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
5605 | continue; | |
3d3c5039 | 5606 | |
d8a1c247 KR |
5607 | case 'N': /* 3 bit branch condition code */ |
5608 | case 'M': /* 3 bit compare condition code */ | |
5609 | my_getExpression (&imm_expr, s); | |
5610 | check_absolute_expr (ip, &imm_expr); | |
5611 | if ((unsigned long) imm_expr.X_add_number > 7) | |
5612 | { | |
5613 | as_warn ("Condition code > 7 (%ld)", | |
5614 | (long) imm_expr.X_add_number); | |
5615 | imm_expr.X_add_number &= 7; | |
5616 | } | |
5617 | if (*args == 'N') | |
5618 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_BCC; | |
5619 | else | |
5620 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CCC; | |
5621 | imm_expr.X_op = O_absent; | |
5622 | s = expr_end; | |
5623 | continue; | |
5624 | ||
3d3c5039 | 5625 | default: |
670a50eb ILT |
5626 | fprintf (stderr, "bad char = '%c'\n", *args); |
5627 | internalError (); | |
3d3c5039 | 5628 | } |
670a50eb | 5629 | break; |
3d3c5039 | 5630 | } |
670a50eb ILT |
5631 | /* Args don't match. */ |
5632 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
5633 | !strcmp (insn->name, insn[1].name)) | |
5634 | { | |
5635 | ++insn; | |
5636 | s = argsStart; | |
5637 | continue; | |
3d3c5039 | 5638 | } |
670a50eb ILT |
5639 | insn_error = "ERROR: Illegal operands"; |
5640 | return; | |
3d3c5039 ILT |
5641 | } |
5642 | } | |
5643 | ||
5644 | #define LP '(' | |
5645 | #define RP ')' | |
5646 | ||
5647 | static int | |
5648 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
5649 | expressionS *ep; |
5650 | char *str; | |
3d3c5039 | 5651 | { |
670a50eb ILT |
5652 | char *sp; |
5653 | int c = 0; | |
5654 | ||
5655 | if (*str == ' ') | |
5656 | str++; | |
5657 | if (*str == LP | |
5658 | || (*str == '%' && | |
5659 | ((str[1] == 'h' && str[2] == 'i') | |
5660 | || (str[1] == 'H' && str[2] == 'I') | |
5661 | || (str[1] == 'l' && str[2] == 'o')) | |
5662 | && str[3] == LP)) | |
5663 | { | |
5664 | if (*str == LP) | |
5665 | c = 0; | |
5666 | else | |
5667 | { | |
5668 | c = str[1]; | |
5669 | str += 3; | |
5670 | } | |
5671 | ||
5672 | /* | |
5673 | * A small expression may be followed by a base register. | |
5674 | * Scan to the end of this operand, and then back over a possible | |
5675 | * base register. Then scan the small expression up to that | |
5676 | * point. (Based on code in sparc.c...) | |
5677 | */ | |
5678 | for (sp = str; *sp && *sp != ','; sp++) | |
5679 | ; | |
5680 | if (sp - 4 >= str && sp[-1] == RP) | |
5681 | { | |
5682 | if (isdigit (sp[-2])) | |
5683 | { | |
5684 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
5685 | ; | |
5686 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
5687 | { | |
5688 | sp--; | |
5689 | goto do_it; | |
3d3c5039 | 5690 | } |
670a50eb ILT |
5691 | } |
5692 | else if (sp - 5 >= str | |
5693 | && sp[-5] == LP | |
5694 | && sp[-4] == '$' | |
5695 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
5696 | || (sp[-3] == 's' && sp[-2] == 'p') | |
5697 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
5698 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
5699 | { | |
5700 | sp -= 5; | |
3d3c5039 | 5701 | do_it: |
670a50eb ILT |
5702 | if (sp == str) |
5703 | { | |
5704 | /* no expression means zero offset */ | |
5705 | if (c) | |
5706 | { | |
5707 | /* %xx(reg) is an error */ | |
5ac34ac3 | 5708 | ep->X_op = O_absent; |
670a50eb | 5709 | expr_end = str - 3; |
3d3c5039 | 5710 | } |
670a50eb ILT |
5711 | else |
5712 | { | |
52aa70b5 | 5713 | ep->X_op = O_constant; |
670a50eb ILT |
5714 | expr_end = sp; |
5715 | } | |
5716 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 5717 | ep->X_op_symbol = NULL; |
670a50eb ILT |
5718 | ep->X_add_number = 0; |
5719 | } | |
5720 | else | |
5721 | { | |
5722 | *sp = '\0'; | |
5723 | my_getExpression (ep, str); | |
5724 | *sp = LP; | |
3d3c5039 | 5725 | } |
670a50eb | 5726 | return c; |
3d3c5039 ILT |
5727 | } |
5728 | } | |
5729 | } | |
670a50eb ILT |
5730 | my_getExpression (ep, str); |
5731 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
5732 | } |
5733 | ||
5734 | static void | |
5735 | my_getExpression (ep, str) | |
670a50eb ILT |
5736 | expressionS *ep; |
5737 | char *str; | |
3d3c5039 | 5738 | { |
670a50eb | 5739 | char *save_in; |
670a50eb ILT |
5740 | |
5741 | save_in = input_line_pointer; | |
5742 | input_line_pointer = str; | |
5ac34ac3 | 5743 | expression (ep); |
670a50eb ILT |
5744 | expr_end = input_line_pointer; |
5745 | input_line_pointer = save_in; | |
3d3c5039 ILT |
5746 | } |
5747 | ||
becfe05e ILT |
5748 | /* Turn a string in input_line_pointer into a floating point constant |
5749 | of type type, and store the appropriate bytes in *litP. The number | |
5750 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
5751 | returned, or NULL on OK. */ | |
5752 | ||
3d3c5039 | 5753 | char * |
670a50eb | 5754 | md_atof (type, litP, sizeP) |
becfe05e | 5755 | int type; |
3d3c5039 ILT |
5756 | char *litP; |
5757 | int *sizeP; | |
5758 | { | |
becfe05e ILT |
5759 | int prec; |
5760 | LITTLENUM_TYPE words[4]; | |
5761 | char *t; | |
5762 | int i; | |
5763 | ||
5764 | switch (type) | |
5765 | { | |
5766 | case 'f': | |
5767 | prec = 2; | |
5768 | break; | |
5769 | ||
5770 | case 'd': | |
5771 | prec = 4; | |
5772 | break; | |
5773 | ||
5774 | default: | |
5775 | *sizeP = 0; | |
5776 | return "bad call to md_atof"; | |
5777 | } | |
5778 | ||
5779 | t = atof_ieee (input_line_pointer, type, words); | |
5780 | if (t) | |
5781 | input_line_pointer = t; | |
5782 | ||
5783 | *sizeP = prec * 2; | |
5784 | ||
5785 | if (byte_order == LITTLE_ENDIAN) | |
5786 | { | |
5787 | for (i = prec - 1; i >= 0; i--) | |
5788 | { | |
5789 | md_number_to_chars (litP, (valueT) words[i], 2); | |
5790 | litP += 2; | |
5791 | } | |
5792 | } | |
5793 | else | |
5794 | { | |
5795 | for (i = 0; i < prec; i++) | |
5796 | { | |
5797 | md_number_to_chars (litP, (valueT) words[i], 2); | |
5798 | litP += 2; | |
5799 | } | |
5800 | } | |
5801 | ||
670a50eb | 5802 | return NULL; |
3d3c5039 ILT |
5803 | } |
5804 | ||
5805 | void | |
5806 | md_number_to_chars (buf, val, n) | |
5807 | char *buf; | |
918692a5 | 5808 | valueT val; |
3d3c5039 ILT |
5809 | int n; |
5810 | { | |
670a50eb ILT |
5811 | switch (byte_order) |
5812 | { | |
3d3c5039 | 5813 | case LITTLE_ENDIAN: |
13fe1379 ILT |
5814 | number_to_chars_littleendian (buf, val, n); |
5815 | break; | |
3d3c5039 ILT |
5816 | |
5817 | case BIG_ENDIAN: | |
13fe1379 ILT |
5818 | number_to_chars_bigendian (buf, val, n); |
5819 | break; | |
3d3c5039 ILT |
5820 | |
5821 | default: | |
670a50eb | 5822 | internalError (); |
3d3c5039 ILT |
5823 | } |
5824 | } | |
f3d817d8 | 5825 | \f |
e8d4d475 | 5826 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 5827 | |
f3d817d8 DM |
5828 | struct option md_longopts[] = { |
5829 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
5830 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
5831 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
5832 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
5833 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
5834 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
5835 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
5836 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
5837 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
5838 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 5839 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 5840 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 5841 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 5842 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
5843 | {"trap", no_argument, NULL, OPTION_TRAP}, |
5844 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 5845 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
5846 | {"break", no_argument, NULL, OPTION_BREAK}, |
5847 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 5848 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 5849 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 5850 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 5851 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 5852 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 5853 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 5854 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 5855 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
5856 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
5857 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
5858 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
5859 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
5860 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
5861 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
5862 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
5863 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
f3d817d8 | 5864 | |
d8a1c247 | 5865 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 5866 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 5867 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
1dc1e798 | 5868 | #ifdef OBJ_ELF |
f3d817d8 | 5869 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 5870 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 5871 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 DM |
5872 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
5873 | #endif | |
5874 | ||
5875 | {NULL, no_argument, NULL, 0} | |
5876 | }; | |
5877 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
5878 | |
5879 | int | |
f3d817d8 DM |
5880 | md_parse_option (c, arg) |
5881 | int c; | |
5882 | char *arg; | |
3d3c5039 | 5883 | { |
f3d817d8 | 5884 | switch (c) |
670a50eb | 5885 | { |
f3d817d8 DM |
5886 | case OPTION_TRAP: |
5887 | mips_trap = 1; | |
5888 | break; | |
670a50eb | 5889 | |
f3d817d8 DM |
5890 | case OPTION_BREAK: |
5891 | mips_trap = 0; | |
5892 | break; | |
5893 | ||
e8d4d475 | 5894 | case OPTION_EB: |
1dc1e798 | 5895 | target_big_endian = 1; |
e8d4d475 | 5896 | break; |
04cb3372 | 5897 | |
e8d4d475 | 5898 | case OPTION_EL: |
1dc1e798 | 5899 | target_big_endian = 0; |
f3d817d8 | 5900 | break; |
670a50eb | 5901 | |
f3d817d8 DM |
5902 | case 'O': |
5903 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
5904 | mips_optimize = 1; |
5905 | else | |
5906 | mips_optimize = 2; | |
f3d817d8 | 5907 | break; |
0aa07269 | 5908 | |
f3d817d8 | 5909 | case 'g': |
22ba90ce ILT |
5910 | if (arg == NULL) |
5911 | mips_debug = 2; | |
5912 | else | |
5913 | mips_debug = atoi (arg); | |
5914 | /* When the MIPS assembler sees -g or -g2, it does not do | |
5915 | optimizations which limit full symbolic debugging. We take | |
5916 | that to be equivalent to -O0. */ | |
5917 | if (mips_debug == 2) | |
0aa07269 | 5918 | mips_optimize = 0; |
f3d817d8 | 5919 | break; |
4e95866e | 5920 | |
f3d817d8 DM |
5921 | case OPTION_MIPS1: |
5922 | mips_isa = 1; | |
4bb0cc41 ILT |
5923 | if (mips_cpu == -1) |
5924 | mips_cpu = 3000; | |
f3d817d8 | 5925 | break; |
8358c818 | 5926 | |
f3d817d8 DM |
5927 | case OPTION_MIPS2: |
5928 | mips_isa = 2; | |
4bb0cc41 ILT |
5929 | if (mips_cpu == -1) |
5930 | mips_cpu = 6000; | |
f3d817d8 | 5931 | break; |
8358c818 | 5932 | |
f3d817d8 DM |
5933 | case OPTION_MIPS3: |
5934 | mips_isa = 3; | |
4bb0cc41 ILT |
5935 | if (mips_cpu == -1) |
5936 | mips_cpu = 4000; | |
f3d817d8 | 5937 | break; |
8358c818 | 5938 | |
d8a1c247 KR |
5939 | case OPTION_MIPS4: |
5940 | mips_isa = 4; | |
5941 | if (mips_cpu == -1) | |
5942 | mips_cpu = 8000; | |
5943 | break; | |
5944 | ||
f3d817d8 DM |
5945 | case OPTION_MCPU: |
5946 | { | |
5947 | char *p; | |
5948 | ||
5949 | /* Identify the processor type */ | |
5950 | p = arg; | |
5951 | if (strcmp (p, "default") == 0 | |
5952 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 5953 | mips_cpu = -1; |
f3d817d8 DM |
5954 | else |
5955 | { | |
c625fc23 JSC |
5956 | int sv = 0; |
5957 | ||
5958 | /* We need to cope with the various "vr" prefixes for the 4300 | |
5959 | processor. */ | |
5960 | if (*p == 'v' || *p == 'V') | |
5961 | { | |
5962 | sv = 1; | |
5963 | p++; | |
5964 | } | |
5965 | ||
f3d817d8 DM |
5966 | if (*p == 'r' || *p == 'R') |
5967 | p++; | |
8358c818 | 5968 | |
4bb0cc41 | 5969 | mips_cpu = -1; |
f3d817d8 DM |
5970 | switch (*p) |
5971 | { | |
d8a1c247 KR |
5972 | case '1': |
5973 | if (strcmp (p, "10000") == 0 | |
5974 | || strcmp (p, "10k") == 0 | |
5975 | || strcmp (p, "10K") == 0) | |
5976 | mips_cpu = 10000; | |
5977 | break; | |
5978 | ||
f3d817d8 DM |
5979 | case '2': |
5980 | if (strcmp (p, "2000") == 0 | |
5981 | || strcmp (p, "2k") == 0 | |
5982 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 5983 | mips_cpu = 2000; |
f3d817d8 | 5984 | break; |
8358c818 | 5985 | |
f3d817d8 DM |
5986 | case '3': |
5987 | if (strcmp (p, "3000") == 0 | |
5988 | || strcmp (p, "3k") == 0 | |
5989 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 5990 | mips_cpu = 3000; |
f3d817d8 | 5991 | break; |
8358c818 | 5992 | |
f3d817d8 DM |
5993 | case '4': |
5994 | if (strcmp (p, "4000") == 0 | |
5995 | || strcmp (p, "4k") == 0 | |
8c63448a | 5996 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 5997 | mips_cpu = 4000; |
c625fc23 JSC |
5998 | else if (strcmp (p, "4100") == 0) |
5999 | { | |
6000 | mips_cpu = 4100; | |
6001 | if (mips_4100 < 0) | |
6002 | mips_4100 = 1; | |
6003 | } | |
6004 | else if (strcmp (p, "4300") == 0) | |
6005 | mips_cpu = 4300; | |
8c63448a | 6006 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 6007 | mips_cpu = 4400; |
8c63448a | 6008 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 6009 | mips_cpu = 4600; |
b2b8c24e ILT |
6010 | else if (strcmp (p, "4650") == 0) |
6011 | { | |
6012 | mips_cpu = 4650; | |
6013 | if (mips_4650 < 0) | |
6014 | mips_4650 = 1; | |
6015 | } | |
e532b44c ILT |
6016 | else if (strcmp (p, "4010") == 0) |
6017 | { | |
6018 | mips_cpu = 4010; | |
6019 | if (mips_4010 < 0) | |
6020 | mips_4010 = 1; | |
6021 | } | |
f3d817d8 | 6022 | break; |
8358c818 | 6023 | |
f3d817d8 DM |
6024 | case '6': |
6025 | if (strcmp (p, "6000") == 0 | |
6026 | || strcmp (p, "6k") == 0 | |
6027 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 6028 | mips_cpu = 6000; |
f3d817d8 | 6029 | break; |
55933a58 | 6030 | |
d8a1c247 KR |
6031 | case '8': |
6032 | if (strcmp (p, "8000") == 0 | |
6033 | || strcmp (p, "8k") == 0 | |
6034 | || strcmp (p, "8K") == 0) | |
6035 | mips_cpu = 8000; | |
6036 | break; | |
6037 | ||
55933a58 ILT |
6038 | case 'o': |
6039 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 6040 | mips_cpu = 4600; |
55933a58 | 6041 | break; |
f3d817d8 | 6042 | } |
8358c818 | 6043 | |
c625fc23 JSC |
6044 | if (sv && mips_cpu != 4300 && mips_cpu != 4100) |
6045 | { | |
6046 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
6047 | return 0; | |
6048 | } | |
6049 | ||
4bb0cc41 | 6050 | if (mips_cpu == -1) |
f3d817d8 DM |
6051 | { |
6052 | as_bad ("invalid architecture -mcpu=%s", arg); | |
6053 | return 0; | |
6054 | } | |
6055 | } | |
6056 | } | |
6057 | break; | |
8358c818 | 6058 | |
b2b8c24e ILT |
6059 | case OPTION_M4650: |
6060 | mips_4650 = 1; | |
6061 | break; | |
6062 | ||
6063 | case OPTION_NO_M4650: | |
6064 | mips_4650 = 0; | |
6065 | break; | |
6066 | ||
e532b44c ILT |
6067 | case OPTION_M4010: |
6068 | mips_4010 = 1; | |
6069 | break; | |
6070 | ||
6071 | case OPTION_NO_M4010: | |
6072 | mips_4010 = 0; | |
6073 | break; | |
6074 | ||
c625fc23 JSC |
6075 | case OPTION_M4100: |
6076 | mips_4100 = 1; | |
6077 | break; | |
6078 | ||
6079 | case OPTION_NO_M4100: | |
6080 | mips_4100 = 0; | |
6081 | break; | |
6082 | ||
f3d817d8 | 6083 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 6084 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 6085 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
6086 | { |
6087 | as_bad ("-G may not be used with embedded PIC code"); | |
6088 | return 0; | |
6089 | } | |
5b63f465 | 6090 | g_switch_value = 0x7fffffff; |
f3d817d8 | 6091 | break; |
d9aba805 | 6092 | |
fb251650 ILT |
6093 | /* When generating ELF code, we permit -KPIC and -call_shared to |
6094 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
6095 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 6096 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
6097 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
6098 | { | |
6099 | as_bad ("-call_shared is supported only for ELF format"); | |
6100 | return 0; | |
6101 | } | |
d9aba805 ILT |
6102 | mips_pic = SVR4_PIC; |
6103 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
6104 | { |
6105 | as_bad ("-G may not be used with SVR4 PIC code"); | |
6106 | return 0; | |
6107 | } | |
d9aba805 | 6108 | g_switch_value = 0; |
f3d817d8 DM |
6109 | break; |
6110 | ||
6111 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
6112 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
6113 | { | |
6114 | as_bad ("-non_shared is supported only for ELF format"); | |
6115 | return 0; | |
6116 | } | |
d9aba805 | 6117 | mips_pic = NO_PIC; |
f3d817d8 | 6118 | break; |
8358c818 | 6119 | |
fb251650 ILT |
6120 | /* The -xgot option tells the assembler to use 32 offsets when |
6121 | accessing the got in SVR4_PIC mode. It is for Irix | |
6122 | compatibility. */ | |
6123 | case OPTION_XGOT: | |
6124 | mips_big_got = 1; | |
6125 | break; | |
6126 | ||
f3d817d8 | 6127 | case 'G': |
1dc1e798 KR |
6128 | if (! USE_GLOBAL_POINTER_OPT) |
6129 | { | |
6130 | as_bad ("-G is not supported for this configuration"); | |
6131 | return 0; | |
6132 | } | |
6133 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 6134 | { |
f3d817d8 DM |
6135 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
6136 | return 0; | |
670a50eb ILT |
6137 | } |
6138 | else | |
f3d817d8 | 6139 | g_switch_value = atoi (arg); |
42562568 | 6140 | g_switch_seen = 1; |
f3d817d8 | 6141 | break; |
4e95866e | 6142 | |
f3d817d8 DM |
6143 | default: |
6144 | return 0; | |
8ea7f4e8 ILT |
6145 | } |
6146 | ||
f3d817d8 | 6147 | return 1; |
8ea7f4e8 ILT |
6148 | } |
6149 | ||
f3d817d8 DM |
6150 | void |
6151 | md_show_usage (stream) | |
6152 | FILE *stream; | |
6153 | { | |
6154 | fprintf(stream, "\ | |
6155 | MIPS options:\n\ | |
6156 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
6157 | -EB generate big endian output\n\ |
6158 | -EL generate little endian output\n\ | |
6159 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
6160 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
6161 | implicitly with the gp register [default 8]\n"); |
6162 | fprintf(stream, "\ | |
f3d817d8 DM |
6163 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
6164 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
6165 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 6166 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 6167 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 6168 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
6169 | -m4650 permit R4650 instructions\n\ |
6170 | -no-m4650 do not permit R4650 instructions\n\ | |
6171 | -m4010 permit R4010 instructions\n\ | |
6172 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
6173 | -m4100 permit VR4100 instructions\n\ |
6174 | -no-m4100 do not permit VR4100 instructions\n"); | |
6175 | fprintf(stream, "\ | |
f3d817d8 DM |
6176 | -O0 remove unneeded NOPs, do not swap branches\n\ |
6177 | -O remove unneeded NOPs and swap branches\n\ | |
6178 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
6179 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
6180 | #ifdef OBJ_ELF | |
6181 | fprintf(stream, "\ | |
6182 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 ILT |
6183 | -non_shared do not generate position independent code\n\ |
6184 | -xgot assume a 32 bit GOT\n"); | |
f3d817d8 DM |
6185 | #endif |
6186 | } | |
22ba90ce ILT |
6187 | |
6188 | void | |
6189 | mips_init_after_args () | |
6190 | { | |
6191 | if (target_big_endian) | |
6192 | byte_order = BIG_ENDIAN; | |
6193 | else | |
6194 | byte_order = LITTLE_ENDIAN; | |
6195 | } | |
f3d817d8 | 6196 | \f |
3d3c5039 ILT |
6197 | long |
6198 | md_pcrel_from (fixP) | |
6199 | fixS *fixP; | |
6200 | { | |
1dc1e798 KR |
6201 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
6202 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
6203 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
6204 | { | |
6205 | /* This makes a branch to an undefined symbol be a branch to the | |
6206 | current location. */ | |
6207 | return 4; | |
6208 | } | |
5b63f465 | 6209 | |
670a50eb ILT |
6210 | /* return the address of the delay slot */ |
6211 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
6212 | } |
6213 | ||
abdad6bc ILT |
6214 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
6215 | reloc for a cons. We could use the definition there, except that | |
6216 | we want to handle 64 bit relocs specially. */ | |
6217 | ||
6218 | void | |
6219 | cons_fix_new_mips (frag, where, nbytes, exp) | |
6220 | fragS *frag; | |
6221 | int where; | |
6222 | unsigned int nbytes; | |
6223 | expressionS *exp; | |
6224 | { | |
6225 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
6226 | 4 byte reloc. | |
6227 | FIXME: There is no way to select anything but 32 bit mode right | |
6228 | now. */ | |
6229 | if (nbytes == 8) | |
6230 | { | |
6231 | if (byte_order == BIG_ENDIAN) | |
6232 | where += 4; | |
6233 | nbytes = 4; | |
6234 | } | |
6235 | ||
6236 | if (nbytes != 2 && nbytes != 4) | |
6237 | as_bad ("Unsupported reloc size %d", nbytes); | |
6238 | ||
6239 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
6240 | nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32); | |
6241 | } | |
6242 | ||
1c803e52 ILT |
6243 | /* When generating embedded PIC code we need to use a special |
6244 | relocation to represent the difference of two symbols in the .text | |
6245 | section (switch tables use a difference of this sort). See | |
6246 | include/coff/mips.h for details. This macro checks whether this | |
6247 | fixup requires the special reloc. */ | |
6248 | #define SWITCH_TABLE(fixp) \ | |
6249 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
6250 | && (fixp)->fx_addsy != NULL \ | |
6251 | && (fixp)->fx_subsy != NULL \ | |
6252 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
6253 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
6254 | ||
5b63f465 | 6255 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
6256 | relocations, in case the linker has to relax a call. We also need |
6257 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
6258 | |
6259 | /*ARGSUSED*/ | |
6260 | int | |
6261 | mips_force_relocation (fixp) | |
6262 | fixS *fixp; | |
6263 | { | |
1c803e52 | 6264 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
6265 | && (fixp->fx_pcrel |
6266 | || SWITCH_TABLE (fixp) | |
6267 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
6268 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
6269 | } |
6270 | ||
6271 | /* Apply a fixup to the object file. */ | |
6272 | ||
3d3c5039 ILT |
6273 | int |
6274 | md_apply_fix (fixP, valueP) | |
6275 | fixS *fixP; | |
918692a5 | 6276 | valueT *valueP; |
3d3c5039 | 6277 | { |
670a50eb ILT |
6278 | unsigned char *buf; |
6279 | long insn, value; | |
3d3c5039 | 6280 | |
49ad0c4c | 6281 | assert (fixP->fx_size == 4 || fixP->fx_r_type == BFD_RELOC_16); |
3d3c5039 | 6282 | |
670a50eb ILT |
6283 | value = *valueP; |
6284 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 6285 | |
5b63f465 ILT |
6286 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
6287 | fixP->fx_done = 1; | |
6288 | ||
670a50eb ILT |
6289 | switch (fixP->fx_r_type) |
6290 | { | |
3d3c5039 ILT |
6291 | case BFD_RELOC_MIPS_JMP: |
6292 | case BFD_RELOC_HI16: | |
6293 | case BFD_RELOC_HI16_S: | |
670a50eb | 6294 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
6295 | case BFD_RELOC_MIPS_LITERAL: |
6296 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
6297 | case BFD_RELOC_MIPS_GOT16: |
6298 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
6299 | case BFD_RELOC_MIPS_GOT_HI16: |
6300 | case BFD_RELOC_MIPS_GOT_LO16: | |
6301 | case BFD_RELOC_MIPS_CALL_HI16: | |
6302 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 6303 | if (fixP->fx_pcrel) |
7b777690 ILT |
6304 | as_bad_where (fixP->fx_file, fixP->fx_line, |
6305 | "Invalid PC relative reloc"); | |
670a50eb | 6306 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 6307 | break; |
3d3c5039 | 6308 | |
ecd4ca1c ILT |
6309 | case BFD_RELOC_PCREL_HI16_S: |
6310 | /* The addend for this is tricky if it is internal, so we just | |
6311 | do everything here rather than in bfd_perform_relocation. */ | |
6312 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
6313 | { | |
6314 | /* For an external symbol adjust by the address to make it | |
6315 | pcrel_offset. We use the address of the RELLO reloc | |
6316 | which follows this one. */ | |
6317 | value += (fixP->fx_next->fx_frag->fr_address | |
6318 | + fixP->fx_next->fx_where); | |
6319 | } | |
6320 | if (value & 0x8000) | |
6321 | value += 0x10000; | |
6322 | value >>= 16; | |
0221ddf7 | 6323 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
6324 | if (byte_order == BIG_ENDIAN) |
6325 | buf += 2; | |
6326 | md_number_to_chars (buf, value, 2); | |
6327 | break; | |
6328 | ||
6329 | case BFD_RELOC_PCREL_LO16: | |
6330 | /* The addend for this is tricky if it is internal, so we just | |
6331 | do everything here rather than in bfd_perform_relocation. */ | |
6332 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
6333 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 6334 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
6335 | if (byte_order == BIG_ENDIAN) |
6336 | buf += 2; | |
6337 | md_number_to_chars (buf, value, 2); | |
6338 | break; | |
6339 | ||
f3645945 ILT |
6340 | case BFD_RELOC_32: |
6341 | /* If we are deleting this reloc entry, we must fill in the | |
6342 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
6343 | resolved when it appears but is later defined. We also need |
6344 | to fill in the value if this is an embedded PIC switch table | |
6345 | entry. */ | |
6346 | if (fixP->fx_done | |
6347 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
6348 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
6349 | value, 4); | |
6350 | break; | |
6351 | ||
49ad0c4c ILT |
6352 | case BFD_RELOC_16: |
6353 | /* If we are deleting this reloc entry, we must fill in the | |
6354 | value now. */ | |
6355 | assert (fixP->fx_size == 2); | |
6356 | if (fixP->fx_done) | |
6357 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
6358 | value, 2); | |
6359 | break; | |
6360 | ||
f3645945 ILT |
6361 | case BFD_RELOC_LO16: |
6362 | /* When handling an embedded PIC switch statement, we can wind | |
6363 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
6364 | if (fixP->fx_done) | |
6365 | { | |
6366 | if (value < -0x8000 || value > 0x7fff) | |
6367 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6368 | "relocation overflow"); | |
0221ddf7 | 6369 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
6370 | if (byte_order == BIG_ENDIAN) |
6371 | buf += 2; | |
6372 | md_number_to_chars (buf, value, 2); | |
6373 | } | |
6374 | break; | |
6375 | ||
3d3c5039 | 6376 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
6377 | /* |
6378 | * We need to save the bits in the instruction since fixup_segment() | |
6379 | * might be deleting the relocation entry (i.e., a branch within | |
6380 | * the current segment). | |
6381 | */ | |
6382 | if (value & 0x3) | |
7b777690 ILT |
6383 | as_warn_where (fixP->fx_file, fixP->fx_line, |
6384 | "Branch to odd address (%lx)", value); | |
670a50eb | 6385 | value >>= 2; |
670a50eb ILT |
6386 | |
6387 | /* update old instruction data */ | |
6388 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
6389 | switch (byte_order) | |
6390 | { | |
3d3c5039 | 6391 | case LITTLE_ENDIAN: |
670a50eb ILT |
6392 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
6393 | break; | |
3d3c5039 ILT |
6394 | |
6395 | case BIG_ENDIAN: | |
670a50eb ILT |
6396 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
6397 | break; | |
3d3c5039 ILT |
6398 | |
6399 | default: | |
670a50eb ILT |
6400 | internalError (); |
6401 | return 0; | |
3d3c5039 | 6402 | } |
9da4c5d1 ILT |
6403 | |
6404 | if (value >= -0x8000 && value < 0x8000) | |
6405 | insn |= value & 0xffff; | |
6406 | else | |
6407 | { | |
6408 | /* The branch offset is too large. If this is an | |
6409 | unconditional branch, and we are not generating PIC code, | |
6410 | we can convert it to an absolute jump instruction. */ | |
6411 | if (mips_pic == NO_PIC | |
6412 | && fixP->fx_done | |
6413 | && fixP->fx_frag->fr_address >= text_section->vma | |
6414 | && (fixP->fx_frag->fr_address | |
6415 | < text_section->vma + text_section->_raw_size) | |
6416 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6417 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6418 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6419 | { | |
6420 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
6421 | insn = 0x0c000000; /* jal */ | |
6422 | else | |
6423 | insn = 0x08000000; /* j */ | |
6424 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
6425 | fixP->fx_done = 0; | |
6426 | fixP->fx_addsy = section_symbol (text_section); | |
6427 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
6428 | } | |
6429 | else | |
6430 | { | |
6431 | /* FIXME. It would be possible in principle to handle | |
6432 | conditional branches which overflow. They could be | |
6433 | transformed into a branch around a jump. This would | |
6434 | require setting up variant frags for each different | |
6435 | branch type. The native MIPS assembler attempts to | |
6436 | handle these cases, but it appears to do it | |
6437 | incorrectly. */ | |
6438 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6439 | "Relocation overflow"); | |
6440 | } | |
6441 | } | |
6442 | ||
604633ae | 6443 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 6444 | break; |
3d3c5039 ILT |
6445 | |
6446 | default: | |
670a50eb | 6447 | internalError (); |
3d3c5039 | 6448 | } |
5b63f465 | 6449 | |
670a50eb | 6450 | return 1; |
3d3c5039 ILT |
6451 | } |
6452 | ||
6453 | #if 0 | |
6454 | void | |
670a50eb ILT |
6455 | printInsn (oc) |
6456 | unsigned long oc; | |
3d3c5039 | 6457 | { |
670a50eb ILT |
6458 | const struct mips_opcode *p; |
6459 | int treg, sreg, dreg, shamt; | |
6460 | short imm; | |
6461 | const char *args; | |
6462 | int i; | |
3d3c5039 | 6463 | |
670a50eb ILT |
6464 | for (i = 0; i < NUMOPCODES; ++i) |
6465 | { | |
6466 | p = &mips_opcodes[i]; | |
6467 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
6468 | { | |
6469 | printf ("%08lx %s\t", oc, p->name); | |
6470 | treg = (oc >> 16) & 0x1f; | |
6471 | sreg = (oc >> 21) & 0x1f; | |
6472 | dreg = (oc >> 11) & 0x1f; | |
6473 | shamt = (oc >> 6) & 0x1f; | |
6474 | imm = oc; | |
6475 | for (args = p->args;; ++args) | |
6476 | { | |
6477 | switch (*args) | |
6478 | { | |
3d3c5039 | 6479 | case '\0': |
670a50eb ILT |
6480 | printf ("\n"); |
6481 | break; | |
3d3c5039 ILT |
6482 | |
6483 | case ',': | |
6484 | case '(': | |
6485 | case ')': | |
670a50eb ILT |
6486 | printf ("%c", *args); |
6487 | continue; | |
3d3c5039 ILT |
6488 | |
6489 | case 'r': | |
670a50eb ILT |
6490 | assert (treg == sreg); |
6491 | printf ("$%d,$%d", treg, sreg); | |
6492 | continue; | |
3d3c5039 ILT |
6493 | |
6494 | case 'd': | |
918692a5 | 6495 | case 'G': |
670a50eb ILT |
6496 | printf ("$%d", dreg); |
6497 | continue; | |
3d3c5039 ILT |
6498 | |
6499 | case 't': | |
918692a5 | 6500 | case 'E': |
670a50eb ILT |
6501 | printf ("$%d", treg); |
6502 | continue; | |
3d3c5039 | 6503 | |
9226253a ILT |
6504 | case 'k': |
6505 | printf ("0x%x", treg); | |
6506 | continue; | |
6507 | ||
3d3c5039 ILT |
6508 | case 'b': |
6509 | case 's': | |
670a50eb ILT |
6510 | printf ("$%d", sreg); |
6511 | continue; | |
3d3c5039 ILT |
6512 | |
6513 | case 'a': | |
670a50eb ILT |
6514 | printf ("0x%08lx", oc & 0x1ffffff); |
6515 | continue; | |
3d3c5039 ILT |
6516 | |
6517 | case 'i': | |
6518 | case 'j': | |
6519 | case 'o': | |
6520 | case 'u': | |
670a50eb ILT |
6521 | printf ("%d", imm); |
6522 | continue; | |
3d3c5039 ILT |
6523 | |
6524 | case '<': | |
56c96faa | 6525 | case '>': |
670a50eb ILT |
6526 | printf ("$%d", shamt); |
6527 | continue; | |
3d3c5039 ILT |
6528 | |
6529 | default: | |
670a50eb | 6530 | internalError (); |
3d3c5039 | 6531 | } |
670a50eb | 6532 | break; |
3d3c5039 | 6533 | } |
670a50eb | 6534 | return; |
3d3c5039 ILT |
6535 | } |
6536 | } | |
670a50eb | 6537 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
6538 | } |
6539 | #endif | |
6540 | ||
6541 | static symbolS * | |
6542 | get_symbol () | |
6543 | { | |
670a50eb ILT |
6544 | int c; |
6545 | char *name; | |
6546 | symbolS *p; | |
6547 | ||
6548 | name = input_line_pointer; | |
6549 | c = get_symbol_end (); | |
6550 | p = (symbolS *) symbol_find_or_make (name); | |
6551 | *input_line_pointer = c; | |
6552 | return p; | |
3d3c5039 ILT |
6553 | } |
6554 | ||
becfe05e ILT |
6555 | /* Align the current frag to a given power of two. The MIPS assembler |
6556 | also automatically adjusts any preceding label. */ | |
6557 | ||
6558 | static void | |
23dc1ae3 | 6559 | mips_align (to, fill, label) |
becfe05e ILT |
6560 | int to; |
6561 | int fill; | |
23dc1ae3 | 6562 | symbolS *label; |
becfe05e ILT |
6563 | { |
6564 | mips_emit_delays (); | |
6565 | frag_align (to, fill); | |
6566 | record_alignment (now_seg, to); | |
23dc1ae3 | 6567 | if (label != NULL) |
becfe05e | 6568 | { |
23dc1ae3 ILT |
6569 | assert (S_GET_SEGMENT (label) == now_seg); |
6570 | label->sy_frag = frag_now; | |
6571 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
6572 | } |
6573 | } | |
6574 | ||
6575 | /* Align to a given power of two. .align 0 turns off the automatic | |
6576 | alignment used by the data creating pseudo-ops. */ | |
6577 | ||
3d3c5039 ILT |
6578 | static void |
6579 | s_align (x) | |
6580 | int x; | |
6581 | { | |
670a50eb ILT |
6582 | register int temp; |
6583 | register long temp_fill; | |
6584 | long max_alignment = 15; | |
3d3c5039 | 6585 | |
670a50eb | 6586 | /* |
3d3c5039 ILT |
6587 | |
6588 | o Note that the assembler pulls down any immediately preceeding label | |
6589 | to the aligned address. | |
6590 | o It's not documented but auto alignment is reinstated by | |
6591 | a .align pseudo instruction. | |
6592 | o Note also that after auto alignment is turned off the mips assembler | |
6593 | issues an error on attempt to assemble an improperly aligned data item. | |
6594 | We don't. | |
6595 | ||
6596 | */ | |
6597 | ||
670a50eb ILT |
6598 | temp = get_absolute_expression (); |
6599 | if (temp > max_alignment) | |
6600 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
6601 | else if (temp < 0) | |
6602 | { | |
6603 | as_warn ("Alignment negative: 0 assumed."); | |
6604 | temp = 0; | |
6605 | } | |
6606 | if (*input_line_pointer == ',') | |
6607 | { | |
6608 | input_line_pointer++; | |
6609 | temp_fill = get_absolute_expression (); | |
6610 | } | |
6611 | else | |
6612 | temp_fill = 0; | |
6613 | if (temp) | |
6614 | { | |
6615 | auto_align = 1; | |
23dc1ae3 | 6616 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 6617 | } |
670a50eb ILT |
6618 | else |
6619 | { | |
6620 | auto_align = 0; | |
3d3c5039 ILT |
6621 | } |
6622 | ||
670a50eb | 6623 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
6624 | } |
6625 | ||
739708fa KR |
6626 | void |
6627 | mips_flush_pending_output () | |
becfe05e ILT |
6628 | { |
6629 | mips_emit_delays (); | |
1849d646 | 6630 | insn_label = NULL; |
becfe05e ILT |
6631 | } |
6632 | ||
3d3c5039 ILT |
6633 | static void |
6634 | s_change_sec (sec) | |
6635 | int sec; | |
6636 | { | |
88225433 | 6637 | segT seg; |
becfe05e | 6638 | |
5b63f465 ILT |
6639 | /* When generating embedded PIC code, we only use the .text, .lit8, |
6640 | .sdata and .sbss sections. We change the .data and .rdata | |
6641 | pseudo-ops to use .sdata. */ | |
6642 | if (mips_pic == EMBEDDED_PIC | |
6643 | && (sec == 'd' || sec == 'r')) | |
6644 | sec = 's'; | |
6645 | ||
becfe05e | 6646 | mips_emit_delays (); |
670a50eb ILT |
6647 | switch (sec) |
6648 | { | |
3d3c5039 | 6649 | case 't': |
604633ae | 6650 | s_text (0); |
670a50eb | 6651 | break; |
3d3c5039 | 6652 | case 'd': |
604633ae | 6653 | s_data (0); |
670a50eb | 6654 | break; |
3d3c5039 | 6655 | case 'b': |
670a50eb | 6656 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
6657 | demand_empty_rest_of_line (); |
6658 | break; | |
88225433 ILT |
6659 | |
6660 | case 'r': | |
1dc1e798 KR |
6661 | if (USE_GLOBAL_POINTER_OPT) |
6662 | { | |
6663 | seg = subseg_new (RDATA_SECTION_NAME, | |
6664 | (subsegT) get_absolute_expression ()); | |
6665 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6666 | { | |
6667 | bfd_set_section_flags (stdoutput, seg, | |
6668 | (SEC_ALLOC | |
6669 | | SEC_LOAD | |
6670 | | SEC_READONLY | |
6671 | | SEC_RELOC | |
6672 | | SEC_DATA)); | |
6673 | bfd_set_section_alignment (stdoutput, seg, 4); | |
6674 | } | |
6675 | demand_empty_rest_of_line (); | |
6676 | } | |
6677 | else | |
6678 | { | |
6679 | as_bad ("No read only data section in this object file format"); | |
6680 | demand_empty_rest_of_line (); | |
6681 | return; | |
6682 | } | |
88225433 | 6683 | break; |
88225433 ILT |
6684 | |
6685 | case 's': | |
1dc1e798 KR |
6686 | if (USE_GLOBAL_POINTER_OPT) |
6687 | { | |
6688 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
6689 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6690 | { | |
6691 | bfd_set_section_flags (stdoutput, seg, | |
6692 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
6693 | | SEC_DATA); | |
6694 | bfd_set_section_alignment (stdoutput, seg, 4); | |
6695 | } | |
6696 | demand_empty_rest_of_line (); | |
6697 | break; | |
6698 | } | |
6699 | else | |
6700 | { | |
6701 | as_bad ("Global pointers not supported; recompile -G 0"); | |
6702 | demand_empty_rest_of_line (); | |
6703 | return; | |
6704 | } | |
3d3c5039 | 6705 | } |
88225433 | 6706 | |
670a50eb | 6707 | auto_align = 1; |
3d3c5039 ILT |
6708 | } |
6709 | ||
739708fa KR |
6710 | void |
6711 | mips_enable_auto_align () | |
9da4c5d1 | 6712 | { |
9da4c5d1 ILT |
6713 | auto_align = 1; |
6714 | } | |
6715 | ||
3d3c5039 ILT |
6716 | static void |
6717 | s_cons (log_size) | |
6718 | int log_size; | |
6719 | { | |
23dc1ae3 ILT |
6720 | symbolS *label; |
6721 | ||
6722 | label = insn_label; | |
becfe05e | 6723 | mips_emit_delays (); |
670a50eb | 6724 | if (log_size > 0 && auto_align) |
23dc1ae3 | 6725 | mips_align (log_size, 0, label); |
1849d646 | 6726 | insn_label = NULL; |
670a50eb | 6727 | cons (1 << log_size); |
3d3c5039 ILT |
6728 | } |
6729 | ||
3d3c5039 | 6730 | static void |
becfe05e ILT |
6731 | s_float_cons (type) |
6732 | int type; | |
3d3c5039 | 6733 | { |
23dc1ae3 ILT |
6734 | symbolS *label; |
6735 | ||
6736 | label = insn_label; | |
6737 | ||
becfe05e | 6738 | mips_emit_delays (); |
670a50eb ILT |
6739 | |
6740 | if (auto_align) | |
becfe05e | 6741 | if (type == 'd') |
23dc1ae3 | 6742 | mips_align (3, 0, label); |
670a50eb | 6743 | else |
23dc1ae3 | 6744 | mips_align (2, 0, label); |
670a50eb | 6745 | |
1849d646 ILT |
6746 | insn_label = NULL; |
6747 | ||
becfe05e | 6748 | float_cons (type); |
3d3c5039 ILT |
6749 | } |
6750 | ||
c1444ec4 ILT |
6751 | /* Handle .globl. We need to override it because on Irix 5 you are |
6752 | permitted to say | |
6753 | .globl foo .text | |
6754 | where foo is an undefined symbol, to mean that foo should be | |
6755 | considered to be the address of a function. */ | |
6756 | ||
6757 | static void | |
6758 | s_mips_globl (x) | |
6759 | int x; | |
6760 | { | |
6761 | char *name; | |
6762 | int c; | |
6763 | symbolS *symbolP; | |
fb251650 | 6764 | flagword flag; |
c1444ec4 ILT |
6765 | |
6766 | name = input_line_pointer; | |
6767 | c = get_symbol_end (); | |
6768 | symbolP = symbol_find_or_make (name); | |
6769 | *input_line_pointer = c; | |
6770 | SKIP_WHITESPACE (); | |
fb251650 ILT |
6771 | |
6772 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
6773 | being a function is apparently labelled as being an object. */ | |
6774 | flag = BSF_OBJECT; | |
6775 | ||
c1444ec4 ILT |
6776 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
6777 | { | |
6778 | char *secname; | |
6779 | asection *sec; | |
6780 | ||
6781 | secname = input_line_pointer; | |
6782 | c = get_symbol_end (); | |
6783 | sec = bfd_get_section_by_name (stdoutput, secname); | |
6784 | if (sec == NULL) | |
6785 | as_bad ("%s: no such section", secname); | |
6786 | *input_line_pointer = c; | |
6787 | ||
6788 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 6789 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
6790 | } |
6791 | ||
fb251650 ILT |
6792 | symbolP->bsym->flags |= flag; |
6793 | ||
c1444ec4 ILT |
6794 | S_SET_EXTERNAL (symbolP); |
6795 | demand_empty_rest_of_line (); | |
6796 | } | |
6797 | ||
3d3c5039 ILT |
6798 | static void |
6799 | s_option (x) | |
6800 | int x; | |
6801 | { | |
dd3f1f76 ILT |
6802 | char *opt; |
6803 | char c; | |
6804 | ||
6805 | opt = input_line_pointer; | |
6806 | c = get_symbol_end (); | |
6807 | ||
dd3f1f76 | 6808 | if (*opt == 'O') |
9226253a ILT |
6809 | { |
6810 | /* FIXME: What does this mean? */ | |
6811 | } | |
dd3f1f76 | 6812 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 6813 | { |
d9aba805 | 6814 | int i; |
42562568 | 6815 | |
d9aba805 ILT |
6816 | i = atoi (opt + 3); |
6817 | if (i == 0) | |
6818 | mips_pic = NO_PIC; | |
6819 | else if (i == 2) | |
6820 | mips_pic = SVR4_PIC; | |
6821 | else | |
6822 | as_bad (".option pic%d not supported", i); | |
6823 | ||
1dc1e798 | 6824 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
6825 | { |
6826 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 6827 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
6828 | g_switch_value = 0; |
6829 | bfd_set_gp_size (stdoutput, 0); | |
6830 | } | |
9226253a | 6831 | } |
dd3f1f76 ILT |
6832 | else |
6833 | as_warn ("Unrecognized option \"%s\"", opt); | |
6834 | ||
6835 | *input_line_pointer = c; | |
670a50eb | 6836 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
6837 | } |
6838 | ||
6839 | static void | |
6840 | s_mipsset (x) | |
6841 | int x; | |
6842 | { | |
670a50eb ILT |
6843 | char *name = input_line_pointer, ch; |
6844 | ||
6845 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
6846 | input_line_pointer++; | |
6847 | ch = *input_line_pointer; | |
6848 | *input_line_pointer = '\0'; | |
6849 | ||
6850 | if (strcmp (name, "reorder") == 0) | |
6851 | { | |
4e95866e ILT |
6852 | if (mips_noreorder) |
6853 | { | |
6854 | prev_insn_unreordered = 1; | |
6855 | prev_prev_insn_unreordered = 1; | |
6856 | } | |
670a50eb ILT |
6857 | mips_noreorder = 0; |
6858 | } | |
6859 | else if (strcmp (name, "noreorder") == 0) | |
6860 | { | |
becfe05e | 6861 | mips_emit_delays (); |
670a50eb | 6862 | mips_noreorder = 1; |
0dd2d296 | 6863 | mips_any_noreorder = 1; |
670a50eb ILT |
6864 | } |
6865 | else if (strcmp (name, "at") == 0) | |
6866 | { | |
6867 | mips_noat = 0; | |
6868 | } | |
6869 | else if (strcmp (name, "noat") == 0) | |
6870 | { | |
6871 | mips_noat = 1; | |
3d3c5039 | 6872 | } |
670a50eb ILT |
6873 | else if (strcmp (name, "macro") == 0) |
6874 | { | |
6875 | mips_warn_about_macros = 0; | |
6876 | } | |
6877 | else if (strcmp (name, "nomacro") == 0) | |
6878 | { | |
6879 | if (mips_noreorder == 0) | |
6880 | as_bad ("`noreorder' must be set before `nomacro'"); | |
6881 | mips_warn_about_macros = 1; | |
6882 | } | |
6883 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
6884 | { | |
6885 | mips_nomove = 0; | |
6886 | } | |
6887 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
6888 | { | |
6889 | mips_nomove = 1; | |
6890 | } | |
6891 | else if (strcmp (name, "bopt") == 0) | |
6892 | { | |
6893 | mips_nobopt = 0; | |
6894 | } | |
6895 | else if (strcmp (name, "nobopt") == 0) | |
6896 | { | |
6897 | mips_nobopt = 1; | |
6898 | } | |
1051c97f ILT |
6899 | else if (strncmp (name, "mips", 4) == 0) |
6900 | { | |
6901 | int isa; | |
6902 | ||
6903 | /* Permit the user to change the ISA on the fly. Needless to | |
6904 | say, misuse can cause serious problems. */ | |
6905 | isa = atoi (name + 4); | |
6906 | if (isa == 0) | |
6907 | mips_isa = file_mips_isa; | |
d8a1c247 | 6908 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
6909 | as_bad ("unknown ISA level"); |
6910 | else | |
6911 | mips_isa = isa; | |
6912 | } | |
670a50eb ILT |
6913 | else |
6914 | { | |
6915 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
6916 | } | |
6917 | *input_line_pointer = ch; | |
6918 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
6919 | } |
6920 | ||
9226253a ILT |
6921 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
6922 | .option pic2. It means to generate SVR4 PIC calls. */ | |
6923 | ||
6924 | static void | |
6925 | s_abicalls (ignore) | |
6926 | int ignore; | |
6927 | { | |
d9aba805 | 6928 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
6929 | if (USE_GLOBAL_POINTER_OPT) |
6930 | { | |
6931 | if (g_switch_seen && g_switch_value != 0) | |
6932 | as_warn ("-G may not be used with SVR4 PIC code"); | |
6933 | g_switch_value = 0; | |
6934 | } | |
d9aba805 | 6935 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
6936 | demand_empty_rest_of_line (); |
6937 | } | |
6938 | ||
6939 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
6940 | PIC code. It sets the $gp register for the function based on the | |
6941 | function address, which is in the register named in the argument. | |
6942 | This uses a relocation against _gp_disp, which is handled specially | |
6943 | by the linker. The result is: | |
6944 | lui $gp,%hi(_gp_disp) | |
6945 | addiu $gp,$gp,%lo(_gp_disp) | |
6946 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 6947 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
6948 | |
6949 | static void | |
6950 | s_cpload (ignore) | |
6951 | int ignore; | |
6952 | { | |
6953 | expressionS ex; | |
6954 | int icnt = 0; | |
6955 | ||
d9aba805 ILT |
6956 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
6957 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
6958 | { |
6959 | s_ignore (0); | |
6960 | return; | |
6961 | } | |
6962 | ||
6963 | /* .cpload should be a in .set noreorder section. */ | |
6964 | if (mips_noreorder == 0) | |
6965 | as_warn (".cpload not in noreorder section"); | |
6966 | ||
9226253a ILT |
6967 | ex.X_op = O_symbol; |
6968 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
6969 | ex.X_op_symbol = NULL; | |
6970 | ex.X_add_number = 0; | |
6971 | ||
fb251650 ILT |
6972 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
6973 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
6974 | ||
0dd2d296 ILT |
6975 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
6976 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
6977 | (int) BFD_RELOC_LO16); |
6978 | ||
0dd2d296 ILT |
6979 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
6980 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
6981 | |
6982 | demand_empty_rest_of_line (); | |
6983 | } | |
6984 | ||
6985 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
6986 | offset from $sp. The offset is remembered, and after making a PIC | |
6987 | call $gp is restored from that location. */ | |
6988 | ||
6989 | static void | |
6990 | s_cprestore (ignore) | |
6991 | int ignore; | |
6992 | { | |
6993 | expressionS ex; | |
6994 | int icnt = 0; | |
6995 | ||
d9aba805 ILT |
6996 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
6997 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
6998 | { |
6999 | s_ignore (0); | |
7000 | return; | |
7001 | } | |
7002 | ||
9226253a ILT |
7003 | mips_cprestore_offset = get_absolute_expression (); |
7004 | ||
7005 | ex.X_op = O_constant; | |
7006 | ex.X_add_symbol = NULL; | |
7007 | ex.X_op_symbol = NULL; | |
7008 | ex.X_add_number = mips_cprestore_offset; | |
7009 | ||
0dd2d296 | 7010 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
7011 | mips_isa < 3 ? "sw" : "sd", |
7012 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
7013 | ||
7014 | demand_empty_rest_of_line (); | |
7015 | } | |
7016 | ||
0dd2d296 ILT |
7017 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
7018 | code. It generates a 32 bit GP relative reloc. */ | |
7019 | ||
7020 | static void | |
7021 | s_gpword (ignore) | |
7022 | int ignore; | |
7023 | { | |
23dc1ae3 | 7024 | symbolS *label; |
0dd2d296 ILT |
7025 | expressionS ex; |
7026 | char *p; | |
7027 | ||
7028 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 7029 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
7030 | { |
7031 | s_cons (2); | |
7032 | return; | |
7033 | } | |
7034 | ||
23dc1ae3 | 7035 | label = insn_label; |
0dd2d296 ILT |
7036 | mips_emit_delays (); |
7037 | if (auto_align) | |
23dc1ae3 | 7038 | mips_align (2, 0, label); |
0dd2d296 ILT |
7039 | insn_label = NULL; |
7040 | ||
7041 | expression (&ex); | |
7042 | ||
7043 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
7044 | { | |
7045 | as_bad ("Unsupported use of .gpword"); | |
7046 | ignore_rest_of_line (); | |
7047 | } | |
7048 | ||
7049 | p = frag_more (4); | |
7050 | md_number_to_chars (p, (valueT) 0, 4); | |
7051 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
7052 | BFD_RELOC_MIPS_GPREL32); | |
7053 | ||
7054 | demand_empty_rest_of_line (); | |
7055 | } | |
7056 | ||
7057 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
7058 | tables in SVR4 PIC code. */ | |
7059 | ||
7060 | static void | |
7061 | s_cpadd (ignore) | |
7062 | int ignore; | |
7063 | { | |
7064 | int icnt = 0; | |
7065 | int reg; | |
7066 | ||
7067 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 7068 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
7069 | { |
7070 | s_ignore (0); | |
7071 | return; | |
7072 | } | |
7073 | ||
7074 | /* Add $gp to the register named as an argument. */ | |
7075 | reg = tc_get_register (0); | |
7076 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7077 | mips_isa < 3 ? "addu" : "daddu", | |
7078 | "d,v,t", reg, reg, GP); | |
7079 | ||
7080 | demand_empty_rest_of_line (); | |
7081 | } | |
7082 | ||
9226253a | 7083 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
7084 | to parse .frame. The argument is non-zero if this is the frame |
7085 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 7086 | |
3d3c5039 | 7087 | int |
0dd2d296 ILT |
7088 | tc_get_register (frame) |
7089 | int frame; | |
3d3c5039 ILT |
7090 | { |
7091 | int reg; | |
7092 | ||
7093 | SKIP_WHITESPACE (); | |
7094 | if (*input_line_pointer++ != '$') | |
7095 | { | |
7096 | as_warn ("expected `$'"); | |
0dd2d296 | 7097 | reg = 0; |
3d3c5039 | 7098 | } |
0dd2d296 | 7099 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
7100 | { |
7101 | reg = get_absolute_expression (); | |
7102 | if (reg < 0 || reg >= 32) | |
7103 | { | |
7104 | as_warn ("Bad register number"); | |
7105 | reg = 0; | |
7106 | } | |
7107 | } | |
7108 | else | |
7109 | { | |
7110 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 7111 | reg = FP; |
3d3c5039 | 7112 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 7113 | reg = SP; |
3d3c5039 | 7114 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 7115 | reg = GP; |
3d3c5039 | 7116 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 7117 | reg = AT; |
3d3c5039 ILT |
7118 | else |
7119 | { | |
7120 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 7121 | reg = 0; |
3d3c5039 ILT |
7122 | } |
7123 | input_line_pointer += 2; | |
7124 | } | |
0dd2d296 ILT |
7125 | if (frame) |
7126 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
7127 | return reg; |
7128 | } | |
7129 | ||
0dd2d296 ILT |
7130 | valueT |
7131 | md_section_align (seg, addr) | |
7132 | asection *seg; | |
7133 | valueT addr; | |
7134 | { | |
7135 | int align = bfd_get_section_alignment (stdoutput, seg); | |
7136 | ||
7137 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
7138 | } | |
7139 | ||
d8a1c247 KR |
7140 | /* Utility routine, called from above as well. If called while the |
7141 | input file is still being read, it's only an approximation. (For | |
7142 | example, a symbol may later become defined which appeared to be | |
7143 | undefined earlier.) */ | |
22ba90ce ILT |
7144 | |
7145 | static int | |
7146 | nopic_need_relax (sym) | |
d8a1c247 KR |
7147 | symbolS *sym; |
7148 | { | |
7149 | if (sym == 0) | |
7150 | return 0; | |
7151 | ||
1dc1e798 KR |
7152 | if (USE_GLOBAL_POINTER_OPT) |
7153 | { | |
7154 | const char *symname; | |
7155 | int change; | |
7156 | ||
7157 | /* Find out whether this symbol can be referenced off the GP | |
7158 | register. It can be if it is smaller than the -G size or if | |
7159 | it is in the .sdata or .sbss section. Certain symbols can | |
7160 | not be referenced off the GP, although it appears as though | |
7161 | they can. */ | |
7162 | symname = S_GET_NAME (sym); | |
7163 | if (symname != (const char *) NULL | |
7164 | && (strcmp (symname, "eprol") == 0 | |
7165 | || strcmp (symname, "etext") == 0 | |
7166 | || strcmp (symname, "_gp") == 0 | |
7167 | || strcmp (symname, "edata") == 0 | |
7168 | || strcmp (symname, "_fbss") == 0 | |
7169 | || strcmp (symname, "_fdata") == 0 | |
7170 | || strcmp (symname, "_ftext") == 0 | |
7171 | || strcmp (symname, "end") == 0 | |
7172 | || strcmp (symname, "_gp_disp") == 0)) | |
7173 | change = 1; | |
7174 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
7175 | && (0 |
7176 | #ifndef NO_ECOFF_DEBUGGING | |
7177 | || (sym->ecoff_extern_size != 0 | |
7178 | && sym->ecoff_extern_size <= g_switch_value) | |
7179 | #endif | |
1dc1e798 KR |
7180 | || (S_GET_VALUE (sym) != 0 |
7181 | && S_GET_VALUE (sym) <= g_switch_value))) | |
7182 | change = 0; | |
7183 | else | |
7184 | { | |
7185 | const char *segname; | |
d8a1c247 | 7186 | |
1dc1e798 KR |
7187 | segname = segment_name (S_GET_SEGMENT (sym)); |
7188 | assert (strcmp (segname, ".lit8") != 0 | |
7189 | && strcmp (segname, ".lit4") != 0); | |
7190 | change = (strcmp (segname, ".sdata") != 0 | |
7191 | && strcmp (segname, ".sbss") != 0); | |
7192 | } | |
7193 | return change; | |
7194 | } | |
7195 | else | |
7196 | /* We are not optimizing for the GP register. */ | |
7197 | return 1; | |
d8a1c247 KR |
7198 | } |
7199 | ||
22ba90ce ILT |
7200 | /* Estimate the size of a frag before relaxing. We are not really |
7201 | relaxing here, and the final size is encoded in the subtype | |
7202 | information. */ | |
7203 | ||
0dd2d296 ILT |
7204 | /*ARGSUSED*/ |
7205 | int | |
7206 | md_estimate_size_before_relax (fragp, segtype) | |
7207 | fragS *fragp; | |
7208 | asection *segtype; | |
7209 | { | |
7210 | int change; | |
7211 | ||
d9aba805 | 7212 | if (mips_pic == NO_PIC) |
0dd2d296 | 7213 | { |
d8a1c247 | 7214 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 7215 | } |
d9aba805 | 7216 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
7217 | { |
7218 | asection *symsec = fragp->fr_symbol->bsym->section; | |
7219 | ||
7220 | /* This must duplicate the test in adjust_reloc_syms. */ | |
7221 | change = (symsec != &bfd_und_section | |
7222 | && symsec != &bfd_abs_section | |
7223 | && ! bfd_is_com_section (symsec)); | |
7224 | } | |
d9aba805 ILT |
7225 | else |
7226 | abort (); | |
0dd2d296 ILT |
7227 | |
7228 | if (change) | |
7229 | { | |
7230 | /* Record the offset to the first reloc in the fr_opcode field. | |
7231 | This lets md_convert_frag and tc_gen_reloc know that the code | |
7232 | must be expanded. */ | |
7233 | fragp->fr_opcode = (fragp->fr_literal | |
7234 | + fragp->fr_fix | |
7235 | - RELAX_OLD (fragp->fr_subtype) | |
7236 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
7237 | /* FIXME: This really needs as_warn_where. */ | |
7238 | if (RELAX_WARN (fragp->fr_subtype)) | |
7239 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
7240 | } | |
7241 | ||
7242 | if (! change) | |
7243 | return 0; | |
7244 | else | |
7245 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
7246 | } | |
7247 | ||
7248 | /* Translate internal representation of relocation info to BFD target | |
7249 | format. */ | |
7250 | ||
7251 | arelent ** | |
3d3c5039 ILT |
7252 | tc_gen_reloc (section, fixp) |
7253 | asection *section; | |
7254 | fixS *fixp; | |
7255 | { | |
0dd2d296 | 7256 | static arelent *retval[4]; |
3d3c5039 ILT |
7257 | arelent *reloc; |
7258 | ||
0dd2d296 ILT |
7259 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
7260 | retval[1] = NULL; | |
3d3c5039 ILT |
7261 | |
7262 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
7263 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
7264 | |
7265 | if (mips_pic == EMBEDDED_PIC | |
7266 | && SWITCH_TABLE (fixp)) | |
7267 | { | |
7268 | /* For a switch table entry we use a special reloc. The addend | |
7269 | is actually the difference between the reloc address and the | |
7270 | subtrahend. */ | |
7271 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
7272 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
7273 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
7274 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
7275 | } | |
ecd4ca1c ILT |
7276 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
7277 | { | |
7278 | /* We use a special addend for an internal RELLO reloc. */ | |
7279 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
7280 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
7281 | else | |
7282 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
7283 | } | |
7284 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
7285 | { | |
7286 | assert (fixp->fx_next != NULL | |
7287 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
7288 | /* We use a special addend for an internal RELHI reloc. The | |
7289 | reloc is relative to the RELLO; adjust the addend | |
7290 | accordingly. */ | |
7291 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
7292 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
7293 | + fixp->fx_next->fx_where | |
7294 | - S_GET_VALUE (fixp->fx_subsy)); | |
7295 | else | |
7296 | reloc->addend = (fixp->fx_addnumber | |
7297 | + fixp->fx_next->fx_frag->fr_address | |
7298 | + fixp->fx_next->fx_where); | |
7299 | } | |
1c803e52 | 7300 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
7301 | reloc->addend = fixp->fx_addnumber; |
7302 | else | |
5b63f465 | 7303 | { |
1dc1e798 KR |
7304 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
7305 | /* A gruesome hack which is a result of the gruesome gas reloc | |
7306 | handling. */ | |
7307 | reloc->addend = reloc->address; | |
7308 | else | |
7309 | reloc->addend = -reloc->address; | |
5b63f465 | 7310 | } |
0dd2d296 ILT |
7311 | |
7312 | /* If this is a variant frag, we may need to adjust the existing | |
7313 | reloc and generate a new one. */ | |
7314 | if (fixp->fx_frag->fr_opcode != NULL | |
7315 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
7316 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
7317 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
7318 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
7319 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
7320 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
7321 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
7322 | { |
7323 | arelent *reloc2; | |
7324 | ||
7325 | /* If this is not the last reloc in this frag, then we have two | |
fb251650 ILT |
7326 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
7327 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
7328 | the second one handle all of them. */ | |
0dd2d296 ILT |
7329 | if (fixp->fx_next != NULL |
7330 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
7331 | { | |
fb251650 ILT |
7332 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
7333 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
7334 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
7335 | && (fixp->fx_next->fx_r_type | |
7336 | == BFD_RELOC_MIPS_GOT_LO16)) | |
7337 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
7338 | && (fixp->fx_next->fx_r_type | |
7339 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
7340 | retval[0] = NULL; |
7341 | return retval; | |
7342 | } | |
7343 | ||
7344 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
7345 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7346 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
7347 | retval[2] = NULL; | |
7348 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
7349 | reloc2->address = (reloc->address | |
7350 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
7351 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
7352 | reloc2->addend = fixp->fx_addnumber; | |
7353 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
7354 | assert (reloc2->howto != NULL); | |
7355 | ||
7356 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
7357 | { | |
7358 | arelent *reloc3; | |
7359 | ||
7360 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
7361 | retval[3] = NULL; | |
7362 | *reloc3 = *reloc2; | |
7363 | reloc3->address += 4; | |
7364 | } | |
7365 | ||
d9aba805 | 7366 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
7367 | { |
7368 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
7369 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
7370 | } | |
d9aba805 | 7371 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 7372 | { |
fb251650 | 7373 | switch (fixp->fx_r_type) |
0dd2d296 | 7374 | { |
fb251650 ILT |
7375 | default: |
7376 | abort (); | |
7377 | case BFD_RELOC_MIPS_GOT16: | |
7378 | break; | |
7379 | case BFD_RELOC_MIPS_CALL16: | |
7380 | case BFD_RELOC_MIPS_GOT_LO16: | |
7381 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 7382 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 7383 | break; |
0dd2d296 ILT |
7384 | } |
7385 | } | |
d9aba805 ILT |
7386 | else |
7387 | abort (); | |
0dd2d296 ILT |
7388 | } |
7389 | ||
d9aba805 ILT |
7390 | /* To support a PC relative reloc when generating embedded PIC code |
7391 | for ECOFF, we use a Cygnus extension. We check for that here to | |
7392 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 KR |
7393 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
7394 | && fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
d9aba805 ILT |
7395 | && mips_pic != EMBEDDED_PIC) |
7396 | reloc->howto = NULL; | |
7397 | else | |
d9aba805 | 7398 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
0dd2d296 | 7399 | |
52aa70b5 JW |
7400 | if (reloc->howto == NULL) |
7401 | { | |
7402 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7403 | "Can not represent relocation in this object file format"); | |
0dd2d296 | 7404 | retval[0] = NULL; |
52aa70b5 | 7405 | } |
3d3c5039 | 7406 | |
0dd2d296 | 7407 | return retval; |
3d3c5039 ILT |
7408 | } |
7409 | ||
0dd2d296 ILT |
7410 | /* Convert a machine dependent frag. */ |
7411 | ||
7412 | void | |
7413 | md_convert_frag (abfd, asec, fragp) | |
7414 | bfd *abfd; | |
7415 | segT asec; | |
7416 | fragS *fragp; | |
3d3c5039 | 7417 | { |
0dd2d296 ILT |
7418 | int old, new; |
7419 | char *fixptr; | |
3d3c5039 | 7420 | |
0dd2d296 ILT |
7421 | if (fragp->fr_opcode == NULL) |
7422 | return; | |
3d3c5039 | 7423 | |
0dd2d296 ILT |
7424 | old = RELAX_OLD (fragp->fr_subtype); |
7425 | new = RELAX_NEW (fragp->fr_subtype); | |
7426 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
7427 | ||
7428 | if (new > 0) | |
7429 | memcpy (fixptr - old, fixptr, new); | |
7430 | ||
7431 | fragp->fr_fix += new - old; | |
7432 | } | |
becfe05e ILT |
7433 | |
7434 | /* This function is called whenever a label is defined. It is used | |
7435 | when handling branch delays; if a branch has a label, we assume we | |
7436 | can not move it. */ | |
7437 | ||
7438 | void | |
7439 | mips_define_label (sym) | |
7440 | symbolS *sym; | |
7441 | { | |
7442 | insn_label = sym; | |
7443 | } | |
22ba90ce ILT |
7444 | |
7445 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
7446 | In order to work with gcc when using mips-tfile, we must keep all | |
7447 | local labels. However, in other cases, we want to discard them, | |
7448 | since they are useless. */ | |
7449 | ||
7450 | int | |
7451 | mips_local_label (name) | |
7452 | const char *name; | |
7453 | { | |
c625fc23 | 7454 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
7455 | if (ECOFF_DEBUGGING |
7456 | && mips_debug != 0 | |
7457 | && ! ecoff_debugging_seen) | |
7458 | { | |
7459 | /* We were called with -g, but we didn't see any debugging | |
7460 | information. That may mean that gcc is smuggling debugging | |
7461 | information through to mips-tfile, in which case we must | |
7462 | generate all local labels. */ | |
7463 | return 0; | |
7464 | } | |
c625fc23 | 7465 | #endif |
22ba90ce ILT |
7466 | |
7467 | /* Here it's OK to discard local labels. */ | |
7468 | ||
3af584b4 | 7469 | return name[0] == '$'; |
22ba90ce | 7470 | } |
3d3c5039 | 7471 | \f |
739708fa | 7472 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 7473 | |
0dd2d296 | 7474 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
7475 | |
7476 | void | |
7477 | mips_elf_final_processing () | |
7478 | { | |
7479 | Elf32_RegInfo s; | |
7480 | ||
0dd2d296 | 7481 | /* Write out the .reginfo section. */ |
f2a663d3 ILT |
7482 | s.ri_gprmask = mips_gprmask; |
7483 | s.ri_cprmask[0] = mips_cprmask[0]; | |
7484 | s.ri_cprmask[1] = mips_cprmask[1]; | |
7485 | s.ri_cprmask[2] = mips_cprmask[2]; | |
7486 | s.ri_cprmask[3] = mips_cprmask[3]; | |
7487 | /* The gp_value field is set by the MIPS ELF backend. */ | |
7488 | ||
7489 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
7490 | ((Elf32_External_RegInfo *) | |
7491 | mips_regmask_frag)); | |
0dd2d296 ILT |
7492 | |
7493 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
7494 | sort of BFD interface for this. */ | |
7495 | if (mips_any_noreorder) | |
7496 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 7497 | if (mips_pic != NO_PIC) |
0dd2d296 | 7498 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
7499 | } |
7500 | ||
739708fa | 7501 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 7502 | \f |
3d3c5039 ILT |
7503 | /* These functions should really be defined by the object file format, |
7504 | since they are related to debugging information. However, this | |
7505 | code has to work for the a.out format, which does not define them, | |
7506 | so we provide simple versions here. These don't actually generate | |
7507 | any debugging information, but they do simple checking and someday | |
7508 | somebody may make them useful. */ | |
7509 | ||
670a50eb ILT |
7510 | typedef struct loc |
7511 | { | |
7512 | struct loc *loc_next; | |
7513 | unsigned long loc_fileno; | |
7514 | unsigned long loc_lineno; | |
7515 | unsigned long loc_offset; | |
7516 | unsigned short loc_delta; | |
7517 | unsigned short loc_count; | |
3d3c5039 | 7518 | #if 0 |
670a50eb | 7519 | fragS *loc_frag; |
3d3c5039 | 7520 | #endif |
670a50eb ILT |
7521 | } |
7522 | locS; | |
3d3c5039 | 7523 | |
670a50eb ILT |
7524 | typedef struct proc |
7525 | { | |
3d3c5039 ILT |
7526 | struct proc *proc_next; |
7527 | struct symbol *proc_isym; | |
7528 | struct symbol *proc_end; | |
7529 | unsigned long proc_reg_mask; | |
7530 | unsigned long proc_reg_offset; | |
7531 | unsigned long proc_fpreg_mask; | |
7532 | unsigned long proc_fpreg_offset; | |
7533 | unsigned long proc_frameoffset; | |
7534 | unsigned long proc_framereg; | |
7535 | unsigned long proc_pcreg; | |
7536 | locS *proc_iline; | |
7537 | struct file *proc_file; | |
7538 | int proc_index; | |
670a50eb ILT |
7539 | } |
7540 | procS; | |
3d3c5039 | 7541 | |
670a50eb ILT |
7542 | typedef struct file |
7543 | { | |
3d3c5039 ILT |
7544 | struct file *file_next; |
7545 | unsigned long file_fileno; | |
7546 | struct symbol *file_symbol; | |
7547 | struct symbol *file_end; | |
7548 | struct proc *file_proc; | |
7549 | int file_numprocs; | |
670a50eb ILT |
7550 | } |
7551 | fileS; | |
3d3c5039 ILT |
7552 | |
7553 | static struct obstack proc_frags; | |
7554 | static procS *proc_lastP; | |
7555 | static procS *proc_rootP; | |
7556 | static int numprocs; | |
7557 | ||
7558 | static void | |
7559 | md_obj_begin () | |
7560 | { | |
670a50eb | 7561 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
7562 | } |
7563 | ||
7564 | static void | |
7565 | md_obj_end () | |
7566 | { | |
7567 | /* check for premature end, nesting errors, etc */ | |
7568 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 7569 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
7570 | } |
7571 | ||
3d3c5039 ILT |
7572 | static long |
7573 | get_number () | |
7574 | { | |
670a50eb ILT |
7575 | int negative = 0; |
7576 | long val = 0; | |
3d3c5039 | 7577 | |
670a50eb ILT |
7578 | if (*input_line_pointer == '-') |
7579 | { | |
7580 | ++input_line_pointer; | |
7581 | negative = 1; | |
3d3c5039 | 7582 | } |
670a50eb ILT |
7583 | if (!isdigit (*input_line_pointer)) |
7584 | as_bad ("Expected simple number."); | |
7585 | if (input_line_pointer[0] == '0') | |
7586 | { | |
7587 | if (input_line_pointer[1] == 'x') | |
7588 | { | |
7589 | input_line_pointer += 2; | |
7590 | while (isxdigit (*input_line_pointer)) | |
7591 | { | |
7592 | val <<= 4; | |
3a762a0b | 7593 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 7594 | } |
670a50eb ILT |
7595 | return negative ? -val : val; |
7596 | } | |
7597 | else | |
7598 | { | |
7599 | ++input_line_pointer; | |
7600 | while (isdigit (*input_line_pointer)) | |
7601 | { | |
7602 | val <<= 3; | |
7603 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 7604 | } |
670a50eb | 7605 | return negative ? -val : val; |
3d3c5039 ILT |
7606 | } |
7607 | } | |
670a50eb ILT |
7608 | if (!isdigit (*input_line_pointer)) |
7609 | { | |
7610 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
7611 | *input_line_pointer, *input_line_pointer); | |
7612 | as_warn ("Invalid number"); | |
7613 | return -1; | |
3d3c5039 | 7614 | } |
670a50eb ILT |
7615 | while (isdigit (*input_line_pointer)) |
7616 | { | |
7617 | val *= 10; | |
7618 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 7619 | } |
670a50eb | 7620 | return negative ? -val : val; |
3d3c5039 ILT |
7621 | } |
7622 | ||
7623 | /* The .file directive; just like the usual .file directive, but there | |
7624 | is an initial number which is the ECOFF file index. */ | |
7625 | ||
7626 | static void | |
7627 | s_file (x) | |
7628 | int x; | |
7629 | { | |
670a50eb | 7630 | int line; |
3d3c5039 | 7631 | |
670a50eb | 7632 | line = get_number (); |
9a7d824a | 7633 | s_app_file (0); |
3d3c5039 ILT |
7634 | } |
7635 | ||
7636 | ||
7637 | /* The .end directive. */ | |
7638 | ||
7639 | static void | |
7640 | s_mipsend (x) | |
7641 | int x; | |
7642 | { | |
670a50eb ILT |
7643 | symbolS *p; |
7644 | ||
7645 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
7646 | { | |
7647 | p = get_symbol (); | |
7648 | demand_empty_rest_of_line (); | |
7649 | } | |
7650 | else | |
7651 | p = NULL; | |
7652 | if (now_seg != text_section) | |
7653 | as_warn (".end not in text section"); | |
7654 | if (!proc_lastP) | |
7655 | { | |
7656 | as_warn (".end and no .ent seen yet."); | |
7657 | return; | |
3d3c5039 ILT |
7658 | } |
7659 | ||
670a50eb ILT |
7660 | if (p != NULL) |
7661 | { | |
7662 | assert (S_GET_NAME (p)); | |
7663 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
7664 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
7665 | } |
7666 | ||
670a50eb | 7667 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
7668 | } |
7669 | ||
7670 | /* The .aent and .ent directives. */ | |
7671 | ||
7672 | static void | |
7673 | s_ent (aent) | |
7674 | int aent; | |
7675 | { | |
670a50eb ILT |
7676 | int number = 0; |
7677 | procS *procP; | |
7678 | symbolS *symbolP; | |
7679 | ||
7680 | symbolP = get_symbol (); | |
7681 | if (*input_line_pointer == ',') | |
7682 | input_line_pointer++; | |
dd3f1f76 | 7683 | SKIP_WHITESPACE (); |
670a50eb ILT |
7684 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
7685 | number = get_number (); | |
7686 | if (now_seg != text_section) | |
7687 | as_warn (".ent or .aent not in text section."); | |
7688 | ||
7689 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
7690 | as_warn ("missing `.end'"); | |
7691 | ||
7692 | if (!aent) | |
7693 | { | |
7694 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
7695 | procP->proc_isym = symbolP; | |
7696 | procP->proc_reg_mask = 0; | |
7697 | procP->proc_reg_offset = 0; | |
7698 | procP->proc_fpreg_mask = 0; | |
7699 | procP->proc_fpreg_offset = 0; | |
7700 | procP->proc_frameoffset = 0; | |
7701 | procP->proc_framereg = 0; | |
7702 | procP->proc_pcreg = 0; | |
7703 | procP->proc_end = NULL; | |
7704 | procP->proc_next = NULL; | |
7705 | if (proc_lastP) | |
7706 | proc_lastP->proc_next = procP; | |
7707 | else | |
7708 | proc_rootP = procP; | |
7709 | proc_lastP = procP; | |
7710 | numprocs++; | |
3d3c5039 | 7711 | } |
670a50eb | 7712 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
7713 | } |
7714 | ||
7715 | /* The .frame directive. */ | |
7716 | ||
88225433 | 7717 | #if 0 |
3d3c5039 ILT |
7718 | static void |
7719 | s_frame (x) | |
670a50eb | 7720 | int x; |
3d3c5039 | 7721 | { |
670a50eb ILT |
7722 | char str[100]; |
7723 | symbolS *symP; | |
7724 | int frame_reg; | |
7725 | int frame_off; | |
7726 | int pcreg; | |
7727 | ||
0dd2d296 | 7728 | frame_reg = tc_get_register (1); |
670a50eb ILT |
7729 | if (*input_line_pointer == ',') |
7730 | input_line_pointer++; | |
5ac34ac3 | 7731 | frame_off = get_absolute_expression (); |
670a50eb ILT |
7732 | if (*input_line_pointer == ',') |
7733 | input_line_pointer++; | |
0dd2d296 | 7734 | pcreg = tc_get_register (0); |
670a50eb ILT |
7735 | |
7736 | /* bob third eye */ | |
7737 | assert (proc_rootP); | |
7738 | proc_rootP->proc_framereg = frame_reg; | |
7739 | proc_rootP->proc_frameoffset = frame_off; | |
7740 | proc_rootP->proc_pcreg = pcreg; | |
7741 | /* bob macho .frame */ | |
7742 | ||
7743 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 7744 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
7745 | { |
7746 | if (!proc_lastP) | |
7747 | as_warn ("No .ent for .frame to use."); | |
7748 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
7749 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
7750 | S_SET_TYPE (symP, N_RMASK); | |
7751 | S_SET_OTHER (symP, 0); | |
7752 | S_SET_DESC (symP, 0); | |
7753 | symP->sy_forward = proc_lastP->proc_isym; | |
7754 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 7755 | } |
670a50eb | 7756 | demand_empty_rest_of_line (); |
3d3c5039 | 7757 | } |
88225433 | 7758 | #endif |
3d3c5039 ILT |
7759 | |
7760 | /* The .fmask and .mask directives. */ | |
7761 | ||
88225433 | 7762 | #if 0 |
3d3c5039 ILT |
7763 | static void |
7764 | s_mask (reg_type) | |
7765 | char reg_type; | |
7766 | { | |
670a50eb ILT |
7767 | char str[100], *strP; |
7768 | symbolS *symP; | |
7769 | int i; | |
7770 | unsigned int mask; | |
7771 | int off; | |
7772 | ||
7773 | mask = get_number (); | |
7774 | if (*input_line_pointer == ',') | |
7775 | input_line_pointer++; | |
7776 | off = get_absolute_expression (); | |
7777 | ||
7778 | /* bob only for coff */ | |
7779 | assert (proc_rootP); | |
7780 | if (reg_type == 'F') | |
7781 | { | |
7782 | proc_rootP->proc_fpreg_mask = mask; | |
7783 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 7784 | } |
670a50eb ILT |
7785 | else |
7786 | { | |
7787 | proc_rootP->proc_reg_mask = mask; | |
7788 | proc_rootP->proc_reg_offset = off; | |
7789 | } | |
7790 | ||
7791 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 7792 | |
670a50eb ILT |
7793 | /* We don't have to write out a mask stab if no saved regs. */ |
7794 | if (!(mask == 0)) | |
7795 | { | |
7796 | if (!proc_lastP) | |
7797 | as_warn ("No .ent for .mask to use."); | |
7798 | strP = str; | |
7799 | for (i = 0; i < 32; i++) | |
7800 | { | |
7801 | if (mask % 2) | |
7802 | { | |
7803 | sprintf (strP, "%c%d,", reg_type, i); | |
7804 | strP += strlen (strP); | |
7805 | } | |
3d3c5039 | 7806 | mask /= 2; |
670a50eb ILT |
7807 | } |
7808 | sprintf (strP, ";%d,", off); | |
7809 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
7810 | S_SET_TYPE (symP, N_RMASK); | |
7811 | S_SET_OTHER (symP, 0); | |
7812 | S_SET_DESC (symP, 0); | |
7813 | symP->sy_forward = proc_lastP->proc_isym; | |
7814 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 7815 | } |
3d3c5039 | 7816 | } |
88225433 | 7817 | #endif |
3d3c5039 ILT |
7818 | |
7819 | /* The .loc directive. */ | |
7820 | ||
88225433 | 7821 | #if 0 |
3d3c5039 ILT |
7822 | static void |
7823 | s_loc (x) | |
7824 | int x; | |
7825 | { | |
670a50eb ILT |
7826 | symbolS *symbolP; |
7827 | int lineno; | |
7828 | int addroff; | |
3d3c5039 | 7829 | |
670a50eb | 7830 | assert (now_seg == text_section); |
3d3c5039 | 7831 | |
670a50eb | 7832 | lineno = get_number (); |
87e48495 | 7833 | addroff = frag_now_fix (); |
3d3c5039 | 7834 | |
670a50eb ILT |
7835 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
7836 | S_SET_TYPE (symbolP, N_SLINE); | |
7837 | S_SET_OTHER (symbolP, 0); | |
7838 | S_SET_DESC (symbolP, lineno); | |
7839 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 7840 | } |
88225433 | 7841 | #endif |