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252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
a2c58332 | 2 | Copyright (C) 1994-2022 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
85645aed TG |
34 | #ifdef OBJ_XCOFF |
35 | #include "coff/xcoff.h" | |
36 | #include "libxcoff.h" | |
37 | #endif | |
38 | ||
252b5132 RH |
39 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
40 | ||
41 | /* Tell the main code what the endianness is. */ | |
42 | extern int target_big_endian; | |
43 | ||
44 | /* Whether or not, we've set target_big_endian. */ | |
45 | static int set_target_endian = 0; | |
46 | ||
47 | /* Whether to use user friendly register names. */ | |
48 | #ifndef TARGET_REG_NAMES_P | |
5b7c81bd | 49 | #define TARGET_REG_NAMES_P false |
252b5132 | 50 | #endif |
252b5132 | 51 | |
0baf16f2 AM |
52 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
53 | HIGHESTA. */ | |
54 | ||
55 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
56 | #define PPC_LO(v) ((v) & 0xffff) | |
57 | ||
58 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
59 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
60 | ||
61 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
62 | the indicated value, compensating for #lo() being treated as a | |
63 | signed number. */ | |
15c1449b | 64 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
65 | |
66 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 67 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
68 | |
69 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
70 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 71 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
72 | |
73 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 74 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
75 | |
76 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
77 | compensating for #lo being treated as a signed number. */ |
78 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 79 | |
f9c6b907 AM |
80 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
81 | ||
82 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
83 | applied to constants. */ | |
84 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 85 | |
5b7c81bd | 86 | static bool reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 87 | |
98027b10 | 88 | static void ppc_byte (int); |
0baf16f2 AM |
89 | |
90 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
91 | static void ppc_tc (int); |
92 | static void ppc_machine (int); | |
0baf16f2 | 93 | #endif |
252b5132 RH |
94 | |
95 | #ifdef OBJ_XCOFF | |
98027b10 AM |
96 | static void ppc_comm (int); |
97 | static void ppc_bb (int); | |
98 | static void ppc_bc (int); | |
99 | static void ppc_bf (int); | |
100 | static void ppc_biei (int); | |
101 | static void ppc_bs (int); | |
102 | static void ppc_eb (int); | |
103 | static void ppc_ec (int); | |
104 | static void ppc_ef (int); | |
105 | static void ppc_es (int); | |
106 | static void ppc_csect (int); | |
85645aed | 107 | static void ppc_dwsect (int); |
98027b10 | 108 | static void ppc_change_csect (symbolS *, offsetT); |
e86fc4a5 | 109 | static void ppc_file (int); |
98027b10 AM |
110 | static void ppc_function (int); |
111 | static void ppc_extern (int); | |
add588a8 | 112 | static void ppc_globl (int); |
98027b10 | 113 | static void ppc_lglobl (int); |
c865e45b | 114 | static void ppc_ref (int); |
98027b10 AM |
115 | static void ppc_section (int); |
116 | static void ppc_named_section (int); | |
117 | static void ppc_stabx (int); | |
118 | static void ppc_rename (int); | |
119 | static void ppc_toc (int); | |
120 | static void ppc_xcoff_cons (int); | |
121 | static void ppc_vbyte (int); | |
add588a8 | 122 | static void ppc_weak (int); |
09d4578f | 123 | static void ppc_GNU_visibility (int); |
252b5132 RH |
124 | #endif |
125 | ||
126 | #ifdef OBJ_ELF | |
98027b10 AM |
127 | static void ppc_elf_rdata (int); |
128 | static void ppc_elf_lcomm (int); | |
6911b7dc | 129 | static void ppc_elf_localentry (int); |
ee67d69a | 130 | static void ppc_elf_abiversion (int); |
005d79fd | 131 | static void ppc_elf_gnu_attribute (int); |
252b5132 | 132 | #endif |
252b5132 RH |
133 | \f |
134 | /* Generic assembler global variables which must be defined by all | |
135 | targets. */ | |
136 | ||
137 | #ifdef OBJ_ELF | |
138 | /* This string holds the chars that always start a comment. If the | |
139 | pre-processor is disabled, these aren't very useful. The macro | |
140 | tc_comment_chars points to this. We use this, rather than the | |
141 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
142 | static const char ppc_solaris_comment_chars[] = "#!"; | |
143 | static const char ppc_eabi_comment_chars[] = "#"; | |
144 | ||
145 | #ifdef TARGET_SOLARIS_COMMENT | |
146 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
147 | #else | |
148 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
149 | #endif | |
150 | #else | |
151 | const char comment_chars[] = "#"; | |
152 | #endif | |
153 | ||
154 | /* Characters which start a comment at the beginning of a line. */ | |
155 | const char line_comment_chars[] = "#"; | |
156 | ||
157 | /* Characters which may be used to separate multiple commands on a | |
158 | single line. */ | |
159 | const char line_separator_chars[] = ";"; | |
160 | ||
161 | /* Characters which are used to indicate an exponent in a floating | |
162 | point number. */ | |
163 | const char EXP_CHARS[] = "eE"; | |
164 | ||
165 | /* Characters which mean that a number is a floating point constant, | |
166 | as in 0d1.0. */ | |
167 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 168 | |
5e02f92e | 169 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 170 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 171 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
172 | |
173 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
174 | int ppc_cie_data_alignment; | |
783de163 | 175 | |
8fbf7334 JL |
176 | /* The dwarf2 minimum instruction length. */ |
177 | int ppc_dwarf2_line_min_insn_length; | |
178 | ||
cef4f754 AM |
179 | /* More than this number of nops in an alignment op gets a branch |
180 | instead. */ | |
181 | unsigned long nop_limit = 4; | |
182 | ||
783de163 AM |
183 | /* The type of processor we are assembling for. This is one or more |
184 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 185 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 186 | ppc_cpu_t sticky = 0; |
01efc3af | 187 | |
ee67d69a AM |
188 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
189 | unsigned int ppc_abiversion = 0; | |
190 | ||
05f7541e | 191 | #ifdef OBJ_ELF |
01efc3af | 192 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 193 | static enum { |
01efc3af AM |
194 | has_large_toc_reloc = 1, |
195 | has_small_toc_reloc = 2 | |
196 | } toc_reloc_types; | |
05f7541e | 197 | #endif |
bf7279d5 AM |
198 | |
199 | /* Warn on emitting data to code sections. */ | |
200 | int warn_476; | |
0f873fd5 | 201 | uint64_t last_insn; |
bf7279d5 AM |
202 | segT last_seg; |
203 | subsegT last_subseg; | |
252b5132 RH |
204 | \f |
205 | /* The target specific pseudo-ops which we support. */ | |
206 | ||
207 | const pseudo_typeS md_pseudo_table[] = | |
208 | { | |
209 | /* Pseudo-ops which must be overridden. */ | |
210 | { "byte", ppc_byte, 0 }, | |
211 | ||
212 | #ifdef OBJ_XCOFF | |
213 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
214 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
215 | on COFF, and is only implemented for the RS/6000. We just use | |
216 | obj-coff.c, and add what we need here. */ | |
217 | { "comm", ppc_comm, 0 }, | |
218 | { "lcomm", ppc_comm, 1 }, | |
219 | { "bb", ppc_bb, 0 }, | |
220 | { "bc", ppc_bc, 0 }, | |
221 | { "bf", ppc_bf, 0 }, | |
222 | { "bi", ppc_biei, 0 }, | |
223 | { "bs", ppc_bs, 0 }, | |
224 | { "csect", ppc_csect, 0 }, | |
85645aed | 225 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
226 | { "data", ppc_section, 'd' }, |
227 | { "eb", ppc_eb, 0 }, | |
228 | { "ec", ppc_ec, 0 }, | |
229 | { "ef", ppc_ef, 0 }, | |
230 | { "ei", ppc_biei, 1 }, | |
231 | { "es", ppc_es, 0 }, | |
232 | { "extern", ppc_extern, 0 }, | |
e86fc4a5 | 233 | { "file", ppc_file, 0 }, |
252b5132 | 234 | { "function", ppc_function, 0 }, |
add588a8 | 235 | { "globl", ppc_globl, 0 }, |
252b5132 | 236 | { "lglobl", ppc_lglobl, 0 }, |
c865e45b | 237 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
238 | { "rename", ppc_rename, 0 }, |
239 | { "section", ppc_named_section, 0 }, | |
240 | { "stabx", ppc_stabx, 0 }, | |
241 | { "text", ppc_section, 't' }, | |
242 | { "toc", ppc_toc, 0 }, | |
243 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 244 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
245 | { "word", ppc_xcoff_cons, 1 }, |
246 | { "short", ppc_xcoff_cons, 1 }, | |
247 | { "vbyte", ppc_vbyte, 0 }, | |
add588a8 | 248 | { "weak", ppc_weak, 0 }, |
09d4578f CC |
249 | |
250 | /* Enable GNU syntax for symbol visibility. */ | |
251 | {"internal", ppc_GNU_visibility, SYM_V_INTERNAL}, | |
252 | {"hidden", ppc_GNU_visibility, SYM_V_HIDDEN}, | |
253 | {"protected", ppc_GNU_visibility, SYM_V_PROTECTED}, | |
252b5132 RH |
254 | #endif |
255 | ||
256 | #ifdef OBJ_ELF | |
62ebcb5c | 257 | { "llong", cons, 8 }, |
252b5132 RH |
258 | { "rdata", ppc_elf_rdata, 0 }, |
259 | { "rodata", ppc_elf_rdata, 0 }, | |
260 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 261 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 262 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 263 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
264 | #endif |
265 | ||
0baf16f2 | 266 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 267 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
268 | { "machine", ppc_machine, 0 }, |
269 | #endif | |
252b5132 RH |
270 | |
271 | { NULL, NULL, 0 } | |
272 | }; | |
273 | ||
274 | \f | |
99a814a1 AM |
275 | /* Predefined register names if -mregnames (or default for Windows NT). |
276 | In general, there are lots of them, in an attempt to be compatible | |
277 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
278 | |
279 | /* Structure to hold information about predefined registers. */ | |
280 | struct pd_reg | |
281 | { | |
e0471c16 | 282 | const char *name; |
7e0de605 AM |
283 | unsigned short value; |
284 | unsigned short flags; | |
252b5132 RH |
285 | }; |
286 | ||
287 | /* List of registers that are pre-defined: | |
288 | ||
289 | Each general register has predefined names of the form: | |
290 | 1. r<reg_num> which has the value <reg_num>. | |
291 | 2. r.<reg_num> which has the value <reg_num>. | |
292 | ||
252b5132 RH |
293 | Each floating point register has predefined names of the form: |
294 | 1. f<reg_num> which has the value <reg_num>. | |
295 | 2. f.<reg_num> which has the value <reg_num>. | |
296 | ||
7a899fff C |
297 | Each vector unit register has predefined names of the form: |
298 | 1. v<reg_num> which has the value <reg_num>. | |
299 | 2. v.<reg_num> which has the value <reg_num>. | |
300 | ||
252b5132 RH |
301 | Each condition register has predefined names of the form: |
302 | 1. cr<reg_num> which has the value <reg_num>. | |
303 | 2. cr.<reg_num> which has the value <reg_num>. | |
304 | ||
305 | There are individual registers as well: | |
306 | sp or r.sp has the value 1 | |
307 | rtoc or r.toc has the value 2 | |
252b5132 RH |
308 | xer has the value 1 |
309 | lr has the value 8 | |
310 | ctr has the value 9 | |
252b5132 RH |
311 | dar has the value 19 |
312 | dsisr has the value 18 | |
313 | dec has the value 22 | |
314 | sdr1 has the value 25 | |
315 | srr0 has the value 26 | |
316 | srr1 has the value 27 | |
317 | ||
81d4177b | 318 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
319 | |
320 | static const struct pd_reg pre_defined_registers[] = | |
321 | { | |
aa3c112f AM |
322 | /* VSX accumulators. */ |
323 | { "a0", 0, PPC_OPERAND_ACC }, | |
324 | { "a1", 1, PPC_OPERAND_ACC }, | |
325 | { "a2", 2, PPC_OPERAND_ACC }, | |
326 | { "a3", 3, PPC_OPERAND_ACC }, | |
327 | { "a4", 4, PPC_OPERAND_ACC }, | |
328 | { "a5", 5, PPC_OPERAND_ACC }, | |
329 | { "a6", 6, PPC_OPERAND_ACC }, | |
330 | { "a7", 7, PPC_OPERAND_ACC }, | |
331 | ||
7e0de605 AM |
332 | /* Condition Registers */ |
333 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
334 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
335 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
336 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
337 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
338 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
339 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
340 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
341 | ||
342 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
343 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
344 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
345 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
346 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
347 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
348 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
349 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
350 | ||
351 | { "ctr", 9, PPC_OPERAND_SPR }, | |
352 | { "dar", 19, PPC_OPERAND_SPR }, | |
353 | { "dec", 22, PPC_OPERAND_SPR }, | |
354 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
355 | ||
356 | /* Floating point registers */ | |
357 | { "f.0", 0, PPC_OPERAND_FPR }, | |
358 | { "f.1", 1, PPC_OPERAND_FPR }, | |
359 | { "f.10", 10, PPC_OPERAND_FPR }, | |
360 | { "f.11", 11, PPC_OPERAND_FPR }, | |
361 | { "f.12", 12, PPC_OPERAND_FPR }, | |
362 | { "f.13", 13, PPC_OPERAND_FPR }, | |
363 | { "f.14", 14, PPC_OPERAND_FPR }, | |
364 | { "f.15", 15, PPC_OPERAND_FPR }, | |
365 | { "f.16", 16, PPC_OPERAND_FPR }, | |
366 | { "f.17", 17, PPC_OPERAND_FPR }, | |
367 | { "f.18", 18, PPC_OPERAND_FPR }, | |
368 | { "f.19", 19, PPC_OPERAND_FPR }, | |
369 | { "f.2", 2, PPC_OPERAND_FPR }, | |
370 | { "f.20", 20, PPC_OPERAND_FPR }, | |
371 | { "f.21", 21, PPC_OPERAND_FPR }, | |
372 | { "f.22", 22, PPC_OPERAND_FPR }, | |
373 | { "f.23", 23, PPC_OPERAND_FPR }, | |
374 | { "f.24", 24, PPC_OPERAND_FPR }, | |
375 | { "f.25", 25, PPC_OPERAND_FPR }, | |
376 | { "f.26", 26, PPC_OPERAND_FPR }, | |
377 | { "f.27", 27, PPC_OPERAND_FPR }, | |
378 | { "f.28", 28, PPC_OPERAND_FPR }, | |
379 | { "f.29", 29, PPC_OPERAND_FPR }, | |
380 | { "f.3", 3, PPC_OPERAND_FPR }, | |
381 | { "f.30", 30, PPC_OPERAND_FPR }, | |
382 | { "f.31", 31, PPC_OPERAND_FPR }, | |
383 | { "f.32", 32, PPC_OPERAND_VSR }, | |
384 | { "f.33", 33, PPC_OPERAND_VSR }, | |
385 | { "f.34", 34, PPC_OPERAND_VSR }, | |
386 | { "f.35", 35, PPC_OPERAND_VSR }, | |
387 | { "f.36", 36, PPC_OPERAND_VSR }, | |
388 | { "f.37", 37, PPC_OPERAND_VSR }, | |
389 | { "f.38", 38, PPC_OPERAND_VSR }, | |
390 | { "f.39", 39, PPC_OPERAND_VSR }, | |
391 | { "f.4", 4, PPC_OPERAND_FPR }, | |
392 | { "f.40", 40, PPC_OPERAND_VSR }, | |
393 | { "f.41", 41, PPC_OPERAND_VSR }, | |
394 | { "f.42", 42, PPC_OPERAND_VSR }, | |
395 | { "f.43", 43, PPC_OPERAND_VSR }, | |
396 | { "f.44", 44, PPC_OPERAND_VSR }, | |
397 | { "f.45", 45, PPC_OPERAND_VSR }, | |
398 | { "f.46", 46, PPC_OPERAND_VSR }, | |
399 | { "f.47", 47, PPC_OPERAND_VSR }, | |
400 | { "f.48", 48, PPC_OPERAND_VSR }, | |
401 | { "f.49", 49, PPC_OPERAND_VSR }, | |
402 | { "f.5", 5, PPC_OPERAND_FPR }, | |
403 | { "f.50", 50, PPC_OPERAND_VSR }, | |
404 | { "f.51", 51, PPC_OPERAND_VSR }, | |
405 | { "f.52", 52, PPC_OPERAND_VSR }, | |
406 | { "f.53", 53, PPC_OPERAND_VSR }, | |
407 | { "f.54", 54, PPC_OPERAND_VSR }, | |
408 | { "f.55", 55, PPC_OPERAND_VSR }, | |
409 | { "f.56", 56, PPC_OPERAND_VSR }, | |
410 | { "f.57", 57, PPC_OPERAND_VSR }, | |
411 | { "f.58", 58, PPC_OPERAND_VSR }, | |
412 | { "f.59", 59, PPC_OPERAND_VSR }, | |
413 | { "f.6", 6, PPC_OPERAND_FPR }, | |
414 | { "f.60", 60, PPC_OPERAND_VSR }, | |
415 | { "f.61", 61, PPC_OPERAND_VSR }, | |
416 | { "f.62", 62, PPC_OPERAND_VSR }, | |
417 | { "f.63", 63, PPC_OPERAND_VSR }, | |
418 | { "f.7", 7, PPC_OPERAND_FPR }, | |
419 | { "f.8", 8, PPC_OPERAND_FPR }, | |
420 | { "f.9", 9, PPC_OPERAND_FPR }, | |
421 | ||
422 | { "f0", 0, PPC_OPERAND_FPR }, | |
423 | { "f1", 1, PPC_OPERAND_FPR }, | |
424 | { "f10", 10, PPC_OPERAND_FPR }, | |
425 | { "f11", 11, PPC_OPERAND_FPR }, | |
426 | { "f12", 12, PPC_OPERAND_FPR }, | |
427 | { "f13", 13, PPC_OPERAND_FPR }, | |
428 | { "f14", 14, PPC_OPERAND_FPR }, | |
429 | { "f15", 15, PPC_OPERAND_FPR }, | |
430 | { "f16", 16, PPC_OPERAND_FPR }, | |
431 | { "f17", 17, PPC_OPERAND_FPR }, | |
432 | { "f18", 18, PPC_OPERAND_FPR }, | |
433 | { "f19", 19, PPC_OPERAND_FPR }, | |
434 | { "f2", 2, PPC_OPERAND_FPR }, | |
435 | { "f20", 20, PPC_OPERAND_FPR }, | |
436 | { "f21", 21, PPC_OPERAND_FPR }, | |
437 | { "f22", 22, PPC_OPERAND_FPR }, | |
438 | { "f23", 23, PPC_OPERAND_FPR }, | |
439 | { "f24", 24, PPC_OPERAND_FPR }, | |
440 | { "f25", 25, PPC_OPERAND_FPR }, | |
441 | { "f26", 26, PPC_OPERAND_FPR }, | |
442 | { "f27", 27, PPC_OPERAND_FPR }, | |
443 | { "f28", 28, PPC_OPERAND_FPR }, | |
444 | { "f29", 29, PPC_OPERAND_FPR }, | |
445 | { "f3", 3, PPC_OPERAND_FPR }, | |
446 | { "f30", 30, PPC_OPERAND_FPR }, | |
447 | { "f31", 31, PPC_OPERAND_FPR }, | |
448 | { "f32", 32, PPC_OPERAND_VSR }, | |
449 | { "f33", 33, PPC_OPERAND_VSR }, | |
450 | { "f34", 34, PPC_OPERAND_VSR }, | |
451 | { "f35", 35, PPC_OPERAND_VSR }, | |
452 | { "f36", 36, PPC_OPERAND_VSR }, | |
453 | { "f37", 37, PPC_OPERAND_VSR }, | |
454 | { "f38", 38, PPC_OPERAND_VSR }, | |
455 | { "f39", 39, PPC_OPERAND_VSR }, | |
456 | { "f4", 4, PPC_OPERAND_FPR }, | |
457 | { "f40", 40, PPC_OPERAND_VSR }, | |
458 | { "f41", 41, PPC_OPERAND_VSR }, | |
459 | { "f42", 42, PPC_OPERAND_VSR }, | |
460 | { "f43", 43, PPC_OPERAND_VSR }, | |
461 | { "f44", 44, PPC_OPERAND_VSR }, | |
462 | { "f45", 45, PPC_OPERAND_VSR }, | |
463 | { "f46", 46, PPC_OPERAND_VSR }, | |
464 | { "f47", 47, PPC_OPERAND_VSR }, | |
465 | { "f48", 48, PPC_OPERAND_VSR }, | |
466 | { "f49", 49, PPC_OPERAND_VSR }, | |
467 | { "f5", 5, PPC_OPERAND_FPR }, | |
468 | { "f50", 50, PPC_OPERAND_VSR }, | |
469 | { "f51", 51, PPC_OPERAND_VSR }, | |
470 | { "f52", 52, PPC_OPERAND_VSR }, | |
471 | { "f53", 53, PPC_OPERAND_VSR }, | |
472 | { "f54", 54, PPC_OPERAND_VSR }, | |
473 | { "f55", 55, PPC_OPERAND_VSR }, | |
474 | { "f56", 56, PPC_OPERAND_VSR }, | |
475 | { "f57", 57, PPC_OPERAND_VSR }, | |
476 | { "f58", 58, PPC_OPERAND_VSR }, | |
477 | { "f59", 59, PPC_OPERAND_VSR }, | |
478 | { "f6", 6, PPC_OPERAND_FPR }, | |
479 | { "f60", 60, PPC_OPERAND_VSR }, | |
480 | { "f61", 61, PPC_OPERAND_VSR }, | |
481 | { "f62", 62, PPC_OPERAND_VSR }, | |
482 | { "f63", 63, PPC_OPERAND_VSR }, | |
483 | { "f7", 7, PPC_OPERAND_FPR }, | |
484 | { "f8", 8, PPC_OPERAND_FPR }, | |
485 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 486 | |
c3d65c1c | 487 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
488 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
489 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
490 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
491 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
492 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
493 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
494 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
495 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
496 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
497 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
498 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
499 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
500 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
501 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
502 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
503 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
504 | ||
505 | { "lr", 8, PPC_OPERAND_SPR }, | |
506 | ||
507 | /* General Purpose Registers */ | |
508 | { "r.0", 0, PPC_OPERAND_GPR }, | |
509 | { "r.1", 1, PPC_OPERAND_GPR }, | |
510 | { "r.10", 10, PPC_OPERAND_GPR }, | |
511 | { "r.11", 11, PPC_OPERAND_GPR }, | |
512 | { "r.12", 12, PPC_OPERAND_GPR }, | |
513 | { "r.13", 13, PPC_OPERAND_GPR }, | |
514 | { "r.14", 14, PPC_OPERAND_GPR }, | |
515 | { "r.15", 15, PPC_OPERAND_GPR }, | |
516 | { "r.16", 16, PPC_OPERAND_GPR }, | |
517 | { "r.17", 17, PPC_OPERAND_GPR }, | |
518 | { "r.18", 18, PPC_OPERAND_GPR }, | |
519 | { "r.19", 19, PPC_OPERAND_GPR }, | |
520 | { "r.2", 2, PPC_OPERAND_GPR }, | |
521 | { "r.20", 20, PPC_OPERAND_GPR }, | |
522 | { "r.21", 21, PPC_OPERAND_GPR }, | |
523 | { "r.22", 22, PPC_OPERAND_GPR }, | |
524 | { "r.23", 23, PPC_OPERAND_GPR }, | |
525 | { "r.24", 24, PPC_OPERAND_GPR }, | |
526 | { "r.25", 25, PPC_OPERAND_GPR }, | |
527 | { "r.26", 26, PPC_OPERAND_GPR }, | |
528 | { "r.27", 27, PPC_OPERAND_GPR }, | |
529 | { "r.28", 28, PPC_OPERAND_GPR }, | |
530 | { "r.29", 29, PPC_OPERAND_GPR }, | |
531 | { "r.3", 3, PPC_OPERAND_GPR }, | |
532 | { "r.30", 30, PPC_OPERAND_GPR }, | |
533 | { "r.31", 31, PPC_OPERAND_GPR }, | |
534 | { "r.4", 4, PPC_OPERAND_GPR }, | |
535 | { "r.5", 5, PPC_OPERAND_GPR }, | |
536 | { "r.6", 6, PPC_OPERAND_GPR }, | |
537 | { "r.7", 7, PPC_OPERAND_GPR }, | |
538 | { "r.8", 8, PPC_OPERAND_GPR }, | |
539 | { "r.9", 9, PPC_OPERAND_GPR }, | |
540 | ||
541 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
542 | ||
543 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
544 | ||
545 | { "r0", 0, PPC_OPERAND_GPR }, | |
546 | { "r1", 1, PPC_OPERAND_GPR }, | |
547 | { "r10", 10, PPC_OPERAND_GPR }, | |
548 | { "r11", 11, PPC_OPERAND_GPR }, | |
549 | { "r12", 12, PPC_OPERAND_GPR }, | |
550 | { "r13", 13, PPC_OPERAND_GPR }, | |
551 | { "r14", 14, PPC_OPERAND_GPR }, | |
552 | { "r15", 15, PPC_OPERAND_GPR }, | |
553 | { "r16", 16, PPC_OPERAND_GPR }, | |
554 | { "r17", 17, PPC_OPERAND_GPR }, | |
555 | { "r18", 18, PPC_OPERAND_GPR }, | |
556 | { "r19", 19, PPC_OPERAND_GPR }, | |
557 | { "r2", 2, PPC_OPERAND_GPR }, | |
558 | { "r20", 20, PPC_OPERAND_GPR }, | |
559 | { "r21", 21, PPC_OPERAND_GPR }, | |
560 | { "r22", 22, PPC_OPERAND_GPR }, | |
561 | { "r23", 23, PPC_OPERAND_GPR }, | |
562 | { "r24", 24, PPC_OPERAND_GPR }, | |
563 | { "r25", 25, PPC_OPERAND_GPR }, | |
564 | { "r26", 26, PPC_OPERAND_GPR }, | |
565 | { "r27", 27, PPC_OPERAND_GPR }, | |
566 | { "r28", 28, PPC_OPERAND_GPR }, | |
567 | { "r29", 29, PPC_OPERAND_GPR }, | |
568 | { "r3", 3, PPC_OPERAND_GPR }, | |
569 | { "r30", 30, PPC_OPERAND_GPR }, | |
570 | { "r31", 31, PPC_OPERAND_GPR }, | |
571 | { "r4", 4, PPC_OPERAND_GPR }, | |
572 | { "r5", 5, PPC_OPERAND_GPR }, | |
573 | { "r6", 6, PPC_OPERAND_GPR }, | |
574 | { "r7", 7, PPC_OPERAND_GPR }, | |
575 | { "r8", 8, PPC_OPERAND_GPR }, | |
576 | { "r9", 9, PPC_OPERAND_GPR }, | |
577 | ||
578 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
579 | ||
580 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
581 | ||
582 | { "sp", 1, PPC_OPERAND_GPR }, | |
583 | ||
584 | { "srr0", 26, PPC_OPERAND_SPR }, | |
585 | { "srr1", 27, PPC_OPERAND_SPR }, | |
586 | ||
587 | /* Vector (Altivec/VMX) registers */ | |
588 | { "v.0", 0, PPC_OPERAND_VR }, | |
589 | { "v.1", 1, PPC_OPERAND_VR }, | |
590 | { "v.10", 10, PPC_OPERAND_VR }, | |
591 | { "v.11", 11, PPC_OPERAND_VR }, | |
592 | { "v.12", 12, PPC_OPERAND_VR }, | |
593 | { "v.13", 13, PPC_OPERAND_VR }, | |
594 | { "v.14", 14, PPC_OPERAND_VR }, | |
595 | { "v.15", 15, PPC_OPERAND_VR }, | |
596 | { "v.16", 16, PPC_OPERAND_VR }, | |
597 | { "v.17", 17, PPC_OPERAND_VR }, | |
598 | { "v.18", 18, PPC_OPERAND_VR }, | |
599 | { "v.19", 19, PPC_OPERAND_VR }, | |
600 | { "v.2", 2, PPC_OPERAND_VR }, | |
601 | { "v.20", 20, PPC_OPERAND_VR }, | |
602 | { "v.21", 21, PPC_OPERAND_VR }, | |
603 | { "v.22", 22, PPC_OPERAND_VR }, | |
604 | { "v.23", 23, PPC_OPERAND_VR }, | |
605 | { "v.24", 24, PPC_OPERAND_VR }, | |
606 | { "v.25", 25, PPC_OPERAND_VR }, | |
607 | { "v.26", 26, PPC_OPERAND_VR }, | |
608 | { "v.27", 27, PPC_OPERAND_VR }, | |
609 | { "v.28", 28, PPC_OPERAND_VR }, | |
610 | { "v.29", 29, PPC_OPERAND_VR }, | |
611 | { "v.3", 3, PPC_OPERAND_VR }, | |
612 | { "v.30", 30, PPC_OPERAND_VR }, | |
613 | { "v.31", 31, PPC_OPERAND_VR }, | |
614 | { "v.4", 4, PPC_OPERAND_VR }, | |
615 | { "v.5", 5, PPC_OPERAND_VR }, | |
616 | { "v.6", 6, PPC_OPERAND_VR }, | |
617 | { "v.7", 7, PPC_OPERAND_VR }, | |
618 | { "v.8", 8, PPC_OPERAND_VR }, | |
619 | { "v.9", 9, PPC_OPERAND_VR }, | |
620 | ||
621 | { "v0", 0, PPC_OPERAND_VR }, | |
622 | { "v1", 1, PPC_OPERAND_VR }, | |
623 | { "v10", 10, PPC_OPERAND_VR }, | |
624 | { "v11", 11, PPC_OPERAND_VR }, | |
625 | { "v12", 12, PPC_OPERAND_VR }, | |
626 | { "v13", 13, PPC_OPERAND_VR }, | |
627 | { "v14", 14, PPC_OPERAND_VR }, | |
628 | { "v15", 15, PPC_OPERAND_VR }, | |
629 | { "v16", 16, PPC_OPERAND_VR }, | |
630 | { "v17", 17, PPC_OPERAND_VR }, | |
631 | { "v18", 18, PPC_OPERAND_VR }, | |
632 | { "v19", 19, PPC_OPERAND_VR }, | |
633 | { "v2", 2, PPC_OPERAND_VR }, | |
634 | { "v20", 20, PPC_OPERAND_VR }, | |
635 | { "v21", 21, PPC_OPERAND_VR }, | |
636 | { "v22", 22, PPC_OPERAND_VR }, | |
637 | { "v23", 23, PPC_OPERAND_VR }, | |
638 | { "v24", 24, PPC_OPERAND_VR }, | |
639 | { "v25", 25, PPC_OPERAND_VR }, | |
640 | { "v26", 26, PPC_OPERAND_VR }, | |
641 | { "v27", 27, PPC_OPERAND_VR }, | |
642 | { "v28", 28, PPC_OPERAND_VR }, | |
643 | { "v29", 29, PPC_OPERAND_VR }, | |
644 | { "v3", 3, PPC_OPERAND_VR }, | |
645 | { "v30", 30, PPC_OPERAND_VR }, | |
646 | { "v31", 31, PPC_OPERAND_VR }, | |
647 | { "v4", 4, PPC_OPERAND_VR }, | |
648 | { "v5", 5, PPC_OPERAND_VR }, | |
649 | { "v6", 6, PPC_OPERAND_VR }, | |
650 | { "v7", 7, PPC_OPERAND_VR }, | |
651 | { "v8", 8, PPC_OPERAND_VR }, | |
652 | { "v9", 9, PPC_OPERAND_VR }, | |
653 | ||
654 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
655 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
656 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
657 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
658 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
659 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
660 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
661 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
662 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
663 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
664 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
665 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
666 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
667 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
668 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
669 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
670 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
671 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
672 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
673 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
674 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
675 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
676 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
677 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
678 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
679 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
680 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
681 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
682 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
683 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
684 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
685 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
686 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
687 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
688 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
689 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
690 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
691 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
692 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
693 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
694 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
695 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
696 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
697 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
698 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
699 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
700 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
701 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
702 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
703 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
704 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
705 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
706 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
707 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
708 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
709 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
710 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
711 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
712 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
713 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
714 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
715 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
716 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
717 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
718 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
719 | ||
720 | { "vs0", 0, PPC_OPERAND_VSR }, | |
721 | { "vs1", 1, PPC_OPERAND_VSR }, | |
722 | { "vs10", 10, PPC_OPERAND_VSR }, | |
723 | { "vs11", 11, PPC_OPERAND_VSR }, | |
724 | { "vs12", 12, PPC_OPERAND_VSR }, | |
725 | { "vs13", 13, PPC_OPERAND_VSR }, | |
726 | { "vs14", 14, PPC_OPERAND_VSR }, | |
727 | { "vs15", 15, PPC_OPERAND_VSR }, | |
728 | { "vs16", 16, PPC_OPERAND_VSR }, | |
729 | { "vs17", 17, PPC_OPERAND_VSR }, | |
730 | { "vs18", 18, PPC_OPERAND_VSR }, | |
731 | { "vs19", 19, PPC_OPERAND_VSR }, | |
732 | { "vs2", 2, PPC_OPERAND_VSR }, | |
733 | { "vs20", 20, PPC_OPERAND_VSR }, | |
734 | { "vs21", 21, PPC_OPERAND_VSR }, | |
735 | { "vs22", 22, PPC_OPERAND_VSR }, | |
736 | { "vs23", 23, PPC_OPERAND_VSR }, | |
737 | { "vs24", 24, PPC_OPERAND_VSR }, | |
738 | { "vs25", 25, PPC_OPERAND_VSR }, | |
739 | { "vs26", 26, PPC_OPERAND_VSR }, | |
740 | { "vs27", 27, PPC_OPERAND_VSR }, | |
741 | { "vs28", 28, PPC_OPERAND_VSR }, | |
742 | { "vs29", 29, PPC_OPERAND_VSR }, | |
743 | { "vs3", 3, PPC_OPERAND_VSR }, | |
744 | { "vs30", 30, PPC_OPERAND_VSR }, | |
745 | { "vs31", 31, PPC_OPERAND_VSR }, | |
746 | { "vs32", 32, PPC_OPERAND_VSR }, | |
747 | { "vs33", 33, PPC_OPERAND_VSR }, | |
748 | { "vs34", 34, PPC_OPERAND_VSR }, | |
749 | { "vs35", 35, PPC_OPERAND_VSR }, | |
750 | { "vs36", 36, PPC_OPERAND_VSR }, | |
751 | { "vs37", 37, PPC_OPERAND_VSR }, | |
752 | { "vs38", 38, PPC_OPERAND_VSR }, | |
753 | { "vs39", 39, PPC_OPERAND_VSR }, | |
754 | { "vs4", 4, PPC_OPERAND_VSR }, | |
755 | { "vs40", 40, PPC_OPERAND_VSR }, | |
756 | { "vs41", 41, PPC_OPERAND_VSR }, | |
757 | { "vs42", 42, PPC_OPERAND_VSR }, | |
758 | { "vs43", 43, PPC_OPERAND_VSR }, | |
759 | { "vs44", 44, PPC_OPERAND_VSR }, | |
760 | { "vs45", 45, PPC_OPERAND_VSR }, | |
761 | { "vs46", 46, PPC_OPERAND_VSR }, | |
762 | { "vs47", 47, PPC_OPERAND_VSR }, | |
763 | { "vs48", 48, PPC_OPERAND_VSR }, | |
764 | { "vs49", 49, PPC_OPERAND_VSR }, | |
765 | { "vs5", 5, PPC_OPERAND_VSR }, | |
766 | { "vs50", 50, PPC_OPERAND_VSR }, | |
767 | { "vs51", 51, PPC_OPERAND_VSR }, | |
768 | { "vs52", 52, PPC_OPERAND_VSR }, | |
769 | { "vs53", 53, PPC_OPERAND_VSR }, | |
770 | { "vs54", 54, PPC_OPERAND_VSR }, | |
771 | { "vs55", 55, PPC_OPERAND_VSR }, | |
772 | { "vs56", 56, PPC_OPERAND_VSR }, | |
773 | { "vs57", 57, PPC_OPERAND_VSR }, | |
774 | { "vs58", 58, PPC_OPERAND_VSR }, | |
775 | { "vs59", 59, PPC_OPERAND_VSR }, | |
776 | { "vs6", 6, PPC_OPERAND_VSR }, | |
777 | { "vs60", 60, PPC_OPERAND_VSR }, | |
778 | { "vs61", 61, PPC_OPERAND_VSR }, | |
779 | { "vs62", 62, PPC_OPERAND_VSR }, | |
780 | { "vs63", 63, PPC_OPERAND_VSR }, | |
781 | { "vs7", 7, PPC_OPERAND_VSR }, | |
782 | { "vs8", 8, PPC_OPERAND_VSR }, | |
783 | { "vs9", 9, PPC_OPERAND_VSR }, | |
784 | ||
785 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
786 | }; |
787 | ||
252b5132 RH |
788 | /* Given NAME, find the register number associated with that name, return |
789 | the integer value associated with the given name or -1 on failure. */ | |
790 | ||
7e0de605 | 791 | static const struct pd_reg * |
98027b10 | 792 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
793 | { |
794 | int middle, low, high; | |
795 | int cmp; | |
796 | ||
797 | low = 0; | |
798 | high = regcount - 1; | |
799 | ||
800 | do | |
801 | { | |
802 | middle = (low + high) / 2; | |
803 | cmp = strcasecmp (name, regs[middle].name); | |
804 | if (cmp < 0) | |
805 | high = middle - 1; | |
806 | else if (cmp > 0) | |
807 | low = middle + 1; | |
808 | else | |
7e0de605 | 809 | return ®s[middle]; |
252b5132 RH |
810 | } |
811 | while (low <= high); | |
812 | ||
7e0de605 | 813 | return NULL; |
252b5132 RH |
814 | } |
815 | ||
00b37cc4 | 816 | /* Called for a non-symbol, non-number operand. Handles %reg. */ |
252b5132 | 817 | |
00b37cc4 AM |
818 | void |
819 | md_operand (expressionS *expressionP) | |
252b5132 | 820 | { |
7e0de605 | 821 | const struct pd_reg *reg; |
252b5132 RH |
822 | char *name; |
823 | char *start; | |
824 | char c; | |
825 | ||
00b37cc4 AM |
826 | if (input_line_pointer[0] != '%' || !ISALPHA (input_line_pointer[1])) |
827 | return; | |
252b5132 | 828 | |
00b37cc4 AM |
829 | start = input_line_pointer; |
830 | ++input_line_pointer; | |
252b5132 | 831 | |
d02603dc | 832 | c = get_symbol_name (&name); |
00b37cc4 AM |
833 | reg = reg_name_search (pre_defined_registers, |
834 | ARRAY_SIZE (pre_defined_registers), name); | |
468cced8 AM |
835 | *input_line_pointer = c; |
836 | ||
7e0de605 | 837 | if (reg != NULL) |
252b5132 RH |
838 | { |
839 | expressionP->X_op = O_register; | |
7e0de605 AM |
840 | expressionP->X_add_number = reg->value; |
841 | expressionP->X_md = reg->flags; | |
252b5132 | 842 | } |
00b37cc4 AM |
843 | else |
844 | input_line_pointer = start; | |
252b5132 | 845 | } |
252b5132 RH |
846 | |
847 | /* Whether to do the special parsing. */ | |
5b7c81bd | 848 | static bool cr_operand; |
252b5132 | 849 | |
00b37cc4 AM |
850 | /* Extra names to recognise in a condition code. This table is sorted. */ |
851 | static const struct pd_reg cr_cond[] = | |
252b5132 | 852 | { |
7e0de605 AM |
853 | { "eq", 2, PPC_OPERAND_CR_BIT }, |
854 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
855 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
856 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
857 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
858 | }; |
859 | ||
00b37cc4 AM |
860 | /* This function is called for each symbol seen in an expression. It |
861 | handles the special parsing which PowerPC assemblers are supposed | |
862 | to use for condition codes, and recognises other registers when | |
863 | -mregnames. */ | |
252b5132 | 864 | |
5f6c9229 | 865 | void |
00b37cc4 | 866 | ppc_parse_name (const char *name, expressionS *exp, enum expr_mode mode) |
252b5132 | 867 | { |
00b37cc4 | 868 | const struct pd_reg *reg = NULL; |
252b5132 | 869 | |
00b37cc4 AM |
870 | if (cr_operand) |
871 | reg = reg_name_search (cr_cond, ARRAY_SIZE (cr_cond), name); | |
872 | if (reg == NULL && (cr_operand || reg_names_p)) | |
873 | reg = reg_name_search (pre_defined_registers, | |
874 | ARRAY_SIZE (pre_defined_registers), name); | |
875 | if (reg != NULL) | |
876 | { | |
877 | exp->X_op = O_register; | |
878 | exp->X_add_number = reg->value; | |
879 | exp->X_md = reg->flags; | |
5f6c9229 | 880 | return; |
00b37cc4 | 881 | } |
252b5132 | 882 | |
00b37cc4 AM |
883 | /* The following replaces code in expr.c operand() after the |
884 | md_parse_name call. There is too much difference between targets | |
885 | in the way X_md is used to move this code into expr.c. If you | |
886 | do, you'll get failures on x86 due to uninitialised X_md fields, | |
887 | failures on alpha and other targets due to creating register | |
888 | symbols as O_constant rather than O_register, and failures on arc | |
889 | and others due to expecting expr() to leave X_md alone. */ | |
890 | symbolS *sym = symbol_find_or_make (name); | |
891 | ||
892 | /* If we have an absolute symbol or a reg, then we know its value | |
893 | now. Copy the symbol value expression to propagate X_md. */ | |
894 | bool done = false; | |
895 | if (mode != expr_defer | |
896 | && !S_FORCE_RELOC (sym, 0)) | |
897 | { | |
898 | segT segment = S_GET_SEGMENT (sym); | |
899 | if (segment == absolute_section || segment == reg_section) | |
900 | { | |
901 | resolve_symbol_value (sym); | |
902 | *exp = *symbol_get_value_expression (sym); | |
903 | done = true; | |
904 | } | |
905 | } | |
906 | if (!done) | |
907 | { | |
908 | exp->X_op = O_symbol; | |
909 | exp->X_add_symbol = sym; | |
910 | exp->X_add_number = 0; | |
911 | } | |
252b5132 | 912 | } |
7e0de605 AM |
913 | |
914 | /* Propagate X_md and check register expressions. This is to support | |
915 | condition codes like 4*cr5+eq. */ | |
916 | ||
917 | int | |
918 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
919 | { | |
920 | /* Accept 4*cr<n> and cr<n>*4. */ | |
921 | if (op == O_multiply | |
922 | && ((right->X_op == O_register | |
923 | && right->X_md == PPC_OPERAND_CR_REG | |
924 | && left->X_op == O_constant | |
925 | && left->X_add_number == 4) | |
926 | || (left->X_op == O_register | |
927 | && left->X_md == PPC_OPERAND_CR_REG | |
928 | && right->X_op == O_constant | |
929 | && right->X_add_number == 4))) | |
930 | { | |
931 | left->X_op = O_register; | |
932 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
933 | left->X_add_number *= right->X_add_number; | |
934 | return 1; | |
935 | } | |
936 | ||
937 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
938 | if (right->X_op == O_register | |
939 | && left->X_op == O_register | |
940 | && op == O_add | |
941 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
942 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
943 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
944 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
945 | { | |
946 | left->X_md = PPC_OPERAND_CR_BIT; | |
947 | right->X_op = O_constant; | |
948 | return 0; | |
949 | } | |
950 | ||
951 | /* Accept reg +/- constant. */ | |
952 | if (left->X_op == O_register | |
953 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 954 | as_warn (_("invalid register expression")); |
7e0de605 AM |
955 | |
956 | /* Accept constant + reg. */ | |
957 | if (right->X_op == O_register) | |
958 | { | |
959 | if (op == O_add && left->X_op == O_constant) | |
960 | left->X_md = right->X_md; | |
961 | else | |
ece5dcc1 | 962 | as_warn (_("invalid register expression")); |
7e0de605 AM |
963 | } |
964 | ||
965 | return 0; | |
966 | } | |
252b5132 RH |
967 | \f |
968 | /* Local variables. */ | |
969 | ||
2b3c4602 AM |
970 | /* Whether to target xcoff64/elf64. */ |
971 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 972 | |
a887be69 AM |
973 | /* A separate obstack for use by ppc_hash, so that we can quickly |
974 | throw away hash table memory . */ | |
975 | struct obstack insn_obstack; | |
976 | ||
252b5132 | 977 | /* Opcode hash table. */ |
629310ab | 978 | static htab_t ppc_hash; |
252b5132 | 979 | |
252b5132 | 980 | #ifdef OBJ_ELF |
99a814a1 | 981 | /* What type of shared library support to use. */ |
5d6f4f16 | 982 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 983 | |
99a814a1 | 984 | /* Flags to set in the elf header. */ |
252b5132 RH |
985 | static flagword ppc_flags = 0; |
986 | ||
987 | /* Whether this is Solaris or not. */ | |
988 | #ifdef TARGET_SOLARIS_COMMENT | |
5b7c81bd | 989 | #define SOLARIS_P true |
252b5132 | 990 | #else |
5b7c81bd | 991 | #define SOLARIS_P false |
252b5132 RH |
992 | #endif |
993 | ||
5b7c81bd | 994 | static bool msolaris = SOLARIS_P; |
252b5132 RH |
995 | #endif |
996 | ||
997 | #ifdef OBJ_XCOFF | |
998 | ||
999 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
1000 | using a bunch of different sections. These assembler sections, | |
1b2cb8e2 CC |
1001 | however, are all encompassed within the .text, .data or .bss sections |
1002 | of the final output file. We handle this by using different | |
1003 | subsegments within these main segments. | |
1004 | .tdata and .tbss sections only have one type of csects for now, | |
1005 | but it's better to follow the same construction like the others. */ | |
1006 | ||
1007 | struct ppc_xcoff_section ppc_xcoff_text_section; | |
1008 | struct ppc_xcoff_section ppc_xcoff_data_section; | |
1009 | struct ppc_xcoff_section ppc_xcoff_bss_section; | |
1010 | struct ppc_xcoff_section ppc_xcoff_tdata_section; | |
1011 | struct ppc_xcoff_section ppc_xcoff_tbss_section; | |
1012 | ||
1013 | /* Return true if the ppc_xcoff_section structure is already | |
1014 | initialized. */ | |
5b7c81bd | 1015 | static bool |
1b2cb8e2 CC |
1016 | ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section) |
1017 | { | |
1018 | return section->segment != NULL; | |
1019 | } | |
252b5132 | 1020 | |
1b2cb8e2 CC |
1021 | /* Initialize a ppc_xcoff_section. |
1022 | Dummy symbols are used to ensure the position of .text over .data | |
934cb849 CC |
1023 | and .tdata. Moreover, they allow all algorithms here to be sure that |
1024 | csects isn't NULL. These symbols won't be output. */ | |
1b2cb8e2 | 1025 | static void |
934cb849 | 1026 | ppc_init_xcoff_section (struct ppc_xcoff_section *s, segT seg) |
1b2cb8e2 CC |
1027 | { |
1028 | s->segment = seg; | |
1029 | s->next_subsegment = 2; | |
934cb849 CC |
1030 | s->csects = symbol_make ("dummy\001"); |
1031 | symbol_get_tc (s->csects)->within = s->csects; | |
1b2cb8e2 | 1032 | } |
252b5132 RH |
1033 | |
1034 | /* The current csect. */ | |
1035 | static symbolS *ppc_current_csect; | |
1036 | ||
1037 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1038 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1039 | A special relocation is used when accessing TOC entries. We handle | |
1040 | the TOC as a subsegment within the .data segment. We set it up if | |
1041 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1042 | static symbolS *ppc_toc_csect; | |
1043 | ||
1044 | /* The first frag in the TOC subsegment. */ | |
1045 | static fragS *ppc_toc_frag; | |
1046 | ||
1047 | /* The first frag in the first subsegment after the TOC in the .data | |
1048 | segment. NULL if there are no subsegments after the TOC. */ | |
1049 | static fragS *ppc_after_toc_frag; | |
1050 | ||
1051 | /* The current static block. */ | |
1052 | static symbolS *ppc_current_block; | |
1053 | ||
1054 | /* The COFF debugging section; set by md_begin. This is not the | |
1055 | .debug section, but is instead the secret BFD section which will | |
1056 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1057 | static asection *ppc_coff_debug_section; | |
1058 | ||
85645aed TG |
1059 | /* Structure to set the length field of the dwarf sections. */ |
1060 | struct dw_subsection { | |
1061 | /* Subsections are simply linked. */ | |
1062 | struct dw_subsection *link; | |
1063 | ||
1064 | /* The subsection number. */ | |
1065 | subsegT subseg; | |
1066 | ||
1067 | /* Expression to compute the length of the section. */ | |
1068 | expressionS end_exp; | |
1069 | }; | |
1070 | ||
1071 | static struct dw_section { | |
1072 | /* Corresponding section. */ | |
1073 | segT sect; | |
1074 | ||
1075 | /* Simply linked list of subsections with a label. */ | |
1076 | struct dw_subsection *list_subseg; | |
1077 | ||
1078 | /* The anonymous subsection. */ | |
1079 | struct dw_subsection *anon_subseg; | |
1080 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1081 | #endif /* OBJ_XCOFF */ |
1082 | ||
252b5132 RH |
1083 | #ifdef OBJ_ELF |
1084 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1085 | unsigned long *ppc_apuinfo_list; |
1086 | unsigned int ppc_apuinfo_num; | |
1087 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1088 | #endif /* OBJ_ELF */ |
1089 | \f | |
1090 | #ifdef OBJ_ELF | |
15c1449b | 1091 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1092 | #else |
15c1449b | 1093 | const char *const md_shortopts = "um:"; |
252b5132 | 1094 | #endif |
cef4f754 | 1095 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1096 | const struct option md_longopts[] = { |
cef4f754 | 1097 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1098 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1099 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1100 | {NULL, no_argument, NULL, 0} |
1101 | }; | |
15c1449b | 1102 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1103 | |
1104 | int | |
17b9d67d | 1105 | md_parse_option (int c, const char *arg) |
252b5132 | 1106 | { |
69fe9ce5 AM |
1107 | ppc_cpu_t new_cpu; |
1108 | ||
252b5132 RH |
1109 | switch (c) |
1110 | { | |
1111 | case 'u': | |
1112 | /* -u means that any undefined symbols should be treated as | |
1113 | external, which is the default for gas anyhow. */ | |
1114 | break; | |
1115 | ||
1116 | #ifdef OBJ_ELF | |
1117 | case 'l': | |
1118 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1119 | sake, recognize -be also. */ |
252b5132 RH |
1120 | if (strcmp (arg, "e") == 0) |
1121 | { | |
1122 | target_big_endian = 0; | |
1123 | set_target_endian = 1; | |
b9c361e0 | 1124 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1125 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1126 | } |
1127 | else | |
1128 | return 0; | |
1129 | ||
1130 | break; | |
1131 | ||
1132 | case 'b': | |
1133 | if (strcmp (arg, "e") == 0) | |
1134 | { | |
1135 | target_big_endian = 1; | |
1136 | set_target_endian = 1; | |
1137 | } | |
1138 | else | |
1139 | return 0; | |
1140 | ||
1141 | break; | |
1142 | ||
1143 | case 'K': | |
99a814a1 | 1144 | /* Recognize -K PIC. */ |
252b5132 RH |
1145 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1146 | { | |
1147 | shlib = SHLIB_PIC; | |
1148 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1149 | } | |
1150 | else | |
1151 | return 0; | |
1152 | ||
1153 | break; | |
1154 | #endif | |
1155 | ||
7f6d05e8 CP |
1156 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1157 | case 'a': | |
1158 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1159 | { |
1160 | #ifdef BFD64 | |
1161 | ppc_obj64 = 1; | |
d6ed37ed AM |
1162 | if (ppc_cpu & PPC_OPCODE_VLE) |
1163 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1164 | #else |
1165 | as_fatal (_("%s unsupported"), "-a64"); | |
1166 | #endif | |
1167 | } | |
7f6d05e8 | 1168 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1169 | ppc_obj64 = 0; |
7f6d05e8 CP |
1170 | else |
1171 | return 0; | |
1172 | break; | |
81d4177b | 1173 | |
252b5132 | 1174 | case 'm': |
776fc418 | 1175 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1176 | /* "raw" is only valid for the disassembler. */ |
1177 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1178 | { |
1179 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1180 | if (strcmp (arg, "vle") == 0) |
1181 | { | |
1182 | if (set_target_endian && target_big_endian == 0) | |
1183 | as_bad (_("the use of -mvle requires big endian.")); | |
1184 | if (ppc_obj64) | |
1185 | as_bad (_("the use of -mvle requires -a32.")); | |
1186 | } | |
b9c361e0 | 1187 | } |
252b5132 | 1188 | |
83eef883 AFB |
1189 | else if (strcmp (arg, "no-vle") == 0) |
1190 | { | |
1191 | sticky &= ~PPC_OPCODE_VLE; | |
1192 | ||
1193 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1194 | new_cpu &= ~PPC_OPCODE_VLE; | |
1195 | ||
1196 | ppc_cpu = new_cpu; | |
1197 | } | |
1198 | ||
252b5132 | 1199 | else if (strcmp (arg, "regnames") == 0) |
5b7c81bd | 1200 | reg_names_p = true; |
252b5132 RH |
1201 | |
1202 | else if (strcmp (arg, "no-regnames") == 0) | |
5b7c81bd | 1203 | reg_names_p = false; |
252b5132 RH |
1204 | |
1205 | #ifdef OBJ_ELF | |
99a814a1 AM |
1206 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1207 | that require relocation. */ | |
252b5132 RH |
1208 | else if (strcmp (arg, "relocatable") == 0) |
1209 | { | |
5d6f4f16 | 1210 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1211 | ppc_flags |= EF_PPC_RELOCATABLE; |
1212 | } | |
1213 | ||
1214 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1215 | { | |
5d6f4f16 | 1216 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1217 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1218 | } | |
1219 | ||
99a814a1 | 1220 | /* -memb, set embedded bit. */ |
252b5132 RH |
1221 | else if (strcmp (arg, "emb") == 0) |
1222 | ppc_flags |= EF_PPC_EMB; | |
1223 | ||
cc643b88 | 1224 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1225 | else if (strcmp (arg, "little") == 0 |
1226 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1227 | { |
1228 | target_big_endian = 0; | |
1229 | set_target_endian = 1; | |
b9c361e0 | 1230 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1231 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1232 | } |
1233 | ||
1234 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1235 | { | |
1236 | target_big_endian = 1; | |
1237 | set_target_endian = 1; | |
1238 | } | |
1239 | ||
1240 | else if (strcmp (arg, "solaris") == 0) | |
1241 | { | |
5b7c81bd | 1242 | msolaris = true; |
252b5132 RH |
1243 | ppc_comment_chars = ppc_solaris_comment_chars; |
1244 | } | |
1245 | ||
1246 | else if (strcmp (arg, "no-solaris") == 0) | |
1247 | { | |
5b7c81bd | 1248 | msolaris = false; |
252b5132 RH |
1249 | ppc_comment_chars = ppc_eabi_comment_chars; |
1250 | } | |
74081948 AF |
1251 | else if (strcmp (arg, "spe2") == 0) |
1252 | { | |
1253 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1254 | } | |
252b5132 RH |
1255 | #endif |
1256 | else | |
1257 | { | |
1258 | as_bad (_("invalid switch -m%s"), arg); | |
1259 | return 0; | |
1260 | } | |
1261 | break; | |
1262 | ||
1263 | #ifdef OBJ_ELF | |
1264 | /* -V: SVR4 argument to print version ID. */ | |
1265 | case 'V': | |
1266 | print_version_id (); | |
1267 | break; | |
1268 | ||
1269 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1270 | should be emitted or not. FIXME: Not implemented. */ | |
1271 | case 'Q': | |
1272 | break; | |
1273 | ||
1274 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1275 | rather than .stabs.excl, which is ignored by the linker. | |
1276 | FIXME: Not implemented. */ | |
1277 | case 's': | |
1278 | if (arg) | |
1279 | return 0; | |
1280 | ||
1281 | break; | |
1282 | #endif | |
1283 | ||
cef4f754 AM |
1284 | case OPTION_NOPS: |
1285 | { | |
1286 | char *end; | |
1287 | nop_limit = strtoul (optarg, &end, 0); | |
1288 | if (*end) | |
1289 | as_bad (_("--nops needs a numeric argument")); | |
1290 | } | |
1291 | break; | |
85645aed | 1292 | |
bf7279d5 AM |
1293 | case 0: |
1294 | break; | |
1295 | ||
252b5132 RH |
1296 | default: |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | return 1; | |
1301 | } | |
1302 | ||
5f63875b AM |
1303 | static int |
1304 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1305 | { | |
1306 | switch (targ->flavour) | |
1307 | { | |
1308 | #ifdef OBJ_ELF | |
1309 | case bfd_target_elf_flavour: | |
d34049e8 | 1310 | return startswith (targ->name, "elf64-powerpc"); |
5f63875b AM |
1311 | #endif |
1312 | #ifdef OBJ_XCOFF | |
1313 | case bfd_target_xcoff_flavour: | |
1314 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1315 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1316 | #endif | |
1317 | default: | |
1318 | return 0; | |
1319 | } | |
1320 | } | |
1321 | ||
252b5132 | 1322 | void |
98027b10 | 1323 | md_show_usage (FILE *stream) |
252b5132 | 1324 | { |
bc805888 | 1325 | fprintf (stream, _("\ |
5f63875b AM |
1326 | PowerPC options:\n")); |
1327 | fprintf (stream, _("\ | |
1328 | -a32 generate ELF32/XCOFF32\n")); | |
1329 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1330 | fprintf (stream, _("\ | |
1331 | -a64 generate ELF64/XCOFF64\n")); | |
1332 | fprintf (stream, _("\ | |
1333 | -u ignored\n")); | |
1334 | fprintf (stream, _("\ | |
1335 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1336 | fprintf (stream, _("\ | |
1337 | -mpwr generate code for POWER (RIOS1)\n")); | |
1338 | fprintf (stream, _("\ | |
1339 | -m601 generate code for PowerPC 601\n")); | |
1340 | fprintf (stream, _("\ | |
418c1742 | 1341 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1342 | generate code for PowerPC 603/604\n")); |
1343 | fprintf (stream, _("\ | |
1344 | -m403 generate code for PowerPC 403\n")); | |
1345 | fprintf (stream, _("\ | |
1346 | -m405 generate code for PowerPC 405\n")); | |
1347 | fprintf (stream, _("\ | |
1348 | -m440 generate code for PowerPC 440\n")); | |
1349 | fprintf (stream, _("\ | |
1350 | -m464 generate code for PowerPC 464\n")); | |
1351 | fprintf (stream, _("\ | |
1352 | -m476 generate code for PowerPC 476\n")); | |
1353 | fprintf (stream, _("\ | |
f5c120c5 | 1354 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1355 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1356 | fprintf (stream, _("\ | |
fa758a70 | 1357 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1358 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1359 | fprintf (stream, _("\ | |
ef5a96d5 | 1360 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1361 | fprintf (stream, _("\ |
5f63875b AM |
1362 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1363 | fprintf (stream, _("\ | |
1364 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1365 | fprintf (stream, _("\ | |
1366 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1367 | fprintf (stream, _("\ | |
1368 | -ma2 generate code for A2 architecture\n")); | |
1369 | fprintf (stream, _("\ | |
1370 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1371 | fprintf (stream, _("\ | |
cdc51b07 | 1372 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1373 | generate code for Power5 architecture\n")); |
1374 | fprintf (stream, _("\ | |
1375 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1376 | fprintf (stream, _("\ | |
1377 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1378 | fprintf (stream, _("\ | |
1379 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1380 | fprintf (stream, _("\ | |
1381 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1382 | fprintf (stream, _("\ | |
1424c35d AM |
1383 | -mpower10, -mpwr10 generate code for Power10 architecture\n")); |
1384 | fprintf (stream, _("\ | |
33ae8a3a DS |
1385 | -mlibresoc generate code for Libre-SOC architecture\n")); |
1386 | fprintf (stream, _("\ | |
5f63875b AM |
1387 | -mcell generate code for Cell Broadband Engine architecture\n")); |
1388 | fprintf (stream, _("\ | |
1389 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1390 | fprintf (stream, _("\ | |
ce3d2015 | 1391 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1392 | fprintf (stream, _("\ |
5f63875b AM |
1393 | -maltivec generate code for AltiVec\n")); |
1394 | fprintf (stream, _("\ | |
1395 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1396 | fprintf (stream, _("\ | |
1397 | -me300 generate code for PowerPC e300 family\n")); | |
1398 | fprintf (stream, _("\ | |
1399 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1400 | fprintf (stream, _("\ | |
1401 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1402 | fprintf (stream, _("\ | |
1403 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1404 | fprintf (stream, _("\ | |
1405 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1406 | fprintf (stream, _("\ | |
1407 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1408 | fprintf (stream, _("\ | |
1409 | -mspe generate code for Motorola SPE instructions\n")); | |
1410 | fprintf (stream, _("\ | |
1411 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1412 | fprintf (stream, _("\ | |
1413 | -mvle generate code for Freescale VLE instructions\n")); | |
1414 | fprintf (stream, _("\ | |
1415 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1416 | fprintf (stream, _("\ | |
1417 | -mregnames Allow symbolic names for registers\n")); | |
1418 | fprintf (stream, _("\ | |
ce3d2015 | 1419 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1420 | #ifdef OBJ_ELF |
bc805888 | 1421 | fprintf (stream, _("\ |
5f63875b AM |
1422 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1423 | fprintf (stream, _("\ | |
1424 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1425 | fprintf (stream, _("\ | |
1426 | -memb set PPC_EMB bit in ELF flags\n")); | |
1427 | fprintf (stream, _("\ | |
b8b738ac | 1428 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1429 | generate code for a little endian machine\n")); |
1430 | fprintf (stream, _("\ | |
b8b738ac | 1431 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1432 | generate code for a big endian machine\n")); |
1433 | fprintf (stream, _("\ | |
1434 | -msolaris generate code for Solaris\n")); | |
1435 | fprintf (stream, _("\ | |
1436 | -mno-solaris do not generate code for Solaris\n")); | |
1437 | fprintf (stream, _("\ | |
1438 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1439 | fprintf (stream, _("\ | |
1440 | -V print assembler version number\n")); | |
1441 | fprintf (stream, _("\ | |
ce3d2015 | 1442 | -Qy, -Qn ignored\n")); |
252b5132 | 1443 | #endif |
cef4f754 | 1444 | fprintf (stream, _("\ |
5f63875b AM |
1445 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1446 | fprintf (stream, _("\ | |
bf7279d5 | 1447 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1448 | } |
1449 | \f | |
1450 | /* Set ppc_cpu if it is not already set. */ | |
1451 | ||
1452 | static void | |
98027b10 | 1453 | ppc_set_cpu (void) |
252b5132 RH |
1454 | { |
1455 | const char *default_os = TARGET_OS; | |
1456 | const char *default_cpu = TARGET_CPU; | |
1457 | ||
7102e95e | 1458 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1459 | { |
2a98c3a6 | 1460 | if (ppc_obj64) |
f2ab4b42 PB |
1461 | if (target_big_endian) |
1462 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1463 | else | |
1464 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1465 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
d34049e8 | 1466 | else if (startswith (default_os, "aix") |
2a98c3a6 | 1467 | && default_os[3] >= '4' && default_os[3] <= '9') |
bdc70b4a | 1468 | ppc_cpu |= PPC_OPCODE_COMMON; |
d34049e8 | 1469 | else if (startswith (default_os, "aix3")) |
bdc70b4a | 1470 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1471 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1472 | ppc_cpu |= PPC_OPCODE_POWER; |
d34049e8 | 1473 | else if (startswith (default_cpu, "powerpc")) |
bdc70b4a | 1474 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1475 | else |
d6ed37ed | 1476 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1477 | default_cpu, default_os); |
252b5132 RH |
1478 | } |
1479 | } | |
1480 | ||
9232bbb0 AM |
1481 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1482 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1483 | |
1484 | enum bfd_architecture | |
98027b10 | 1485 | ppc_arch (void) |
252b5132 RH |
1486 | { |
1487 | const char *default_cpu = TARGET_CPU; | |
1488 | ppc_set_cpu (); | |
1489 | ||
1490 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1491 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1492 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1493 | return bfd_arch_powerpc; | |
1494 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1495 | return bfd_arch_rs6000; |
b9c361e0 | 1496 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1497 | { |
1498 | if (strcmp (default_cpu, "rs6000") == 0) | |
1499 | return bfd_arch_rs6000; | |
d34049e8 | 1500 | else if (startswith (default_cpu, "powerpc")) |
252b5132 RH |
1501 | return bfd_arch_powerpc; |
1502 | } | |
1503 | ||
d6ed37ed | 1504 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1505 | return bfd_arch_unknown; |
1506 | } | |
1507 | ||
7f6d05e8 | 1508 | unsigned long |
98027b10 | 1509 | ppc_mach (void) |
7f6d05e8 | 1510 | { |
2a98c3a6 AM |
1511 | if (ppc_obj64) |
1512 | return bfd_mach_ppc64; | |
1513 | else if (ppc_arch () == bfd_arch_rs6000) | |
1514 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1515 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1516 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1517 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1518 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1519 | else |
1520 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1521 | } |
1522 | ||
e0471c16 | 1523 | extern const char* |
98027b10 | 1524 | ppc_target_format (void) |
7f6d05e8 CP |
1525 | { |
1526 | #ifdef OBJ_COFF | |
fe49679d | 1527 | #if TE_POWERMAC |
0baf16f2 | 1528 | return "xcoff-powermac"; |
7f6d05e8 | 1529 | #else |
eb1e0e80 | 1530 | # ifdef TE_AIX5 |
edc1d652 | 1531 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1532 | # else |
edc1d652 | 1533 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1534 | # endif |
7f6d05e8 | 1535 | #endif |
7f6d05e8 CP |
1536 | #endif |
1537 | #ifdef OBJ_ELF | |
edc1d652 AM |
1538 | # ifdef TE_FreeBSD |
1539 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1540 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1541 | return "elf32-powerpc-vxworks"; |
1542 | # else | |
0baf16f2 | 1543 | return (target_big_endian |
2b3c4602 AM |
1544 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1545 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1546 | # endif |
7f6d05e8 CP |
1547 | #endif |
1548 | } | |
1549 | ||
b9c361e0 JL |
1550 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1551 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1552 | ||
5b7c81bd | 1553 | static bool |
b9c361e0 JL |
1554 | insn_validate (const struct powerpc_opcode *op) |
1555 | { | |
8e5eb8e1 | 1556 | const ppc_opindex_t *o; |
0f873fd5 | 1557 | uint64_t omask = op->mask; |
b9c361e0 JL |
1558 | |
1559 | /* The mask had better not trim off opcode bits. */ | |
1560 | if ((op->opcode & omask) != op->opcode) | |
1561 | { | |
1562 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
5b7c81bd | 1563 | return true; |
b9c361e0 JL |
1564 | } |
1565 | ||
1566 | /* The operands must not overlap the opcode or each other. */ | |
1567 | for (o = op->operands; *o; ++o) | |
1568 | { | |
5b7c81bd | 1569 | bool optional = false; |
b9c361e0 JL |
1570 | if (*o >= num_powerpc_operands) |
1571 | { | |
1572 | as_bad (_("operand index error for %s"), op->name); | |
5b7c81bd | 1573 | return true; |
b9c361e0 JL |
1574 | } |
1575 | else | |
1576 | { | |
71553718 | 1577 | uint64_t mask; |
b9c361e0 | 1578 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1579 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1580 | { |
71553718 | 1581 | const char *errmsg; |
32d71569 | 1582 | uint64_t val; |
71553718 AM |
1583 | |
1584 | errmsg = NULL; | |
1585 | val = -1; | |
1586 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1587 | val = -val; | |
71553718 | 1588 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); |
b9c361e0 | 1589 | } |
42952a96 AM |
1590 | else if (operand->shift == (int) PPC_OPSHIFT_SH6) |
1591 | mask = (0x1f << 11) | 0x2; | |
71553718 AM |
1592 | else if (operand->shift >= 0) |
1593 | mask = operand->bitm << operand->shift; | |
1594 | else | |
1595 | mask = operand->bitm >> -operand->shift; | |
1596 | if (omask & mask) | |
1597 | { | |
1598 | as_bad (_("operand %d overlap in %s"), | |
1599 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1600 | return true; |
71553718 AM |
1601 | } |
1602 | omask |= mask; | |
2eac3da1 | 1603 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
5b7c81bd | 1604 | optional = true; |
2eac3da1 AM |
1605 | else if (optional) |
1606 | { | |
1607 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1608 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1609 | return true; |
2eac3da1 | 1610 | } |
b9c361e0 JL |
1611 | } |
1612 | } | |
5b7c81bd | 1613 | return false; |
b9c361e0 JL |
1614 | } |
1615 | ||
a887be69 AM |
1616 | static void * |
1617 | insn_calloc (size_t n, size_t size) | |
1618 | { | |
a14413dd AM |
1619 | size_t amt = n * size; |
1620 | void *ret = obstack_alloc (&insn_obstack, amt); | |
a887be69 AM |
1621 | memset (ret, 0, amt); |
1622 | return ret; | |
1623 | } | |
1624 | ||
dc3ff926 AM |
1625 | /* Insert opcodes into hash tables. Called at startup and for |
1626 | .machine pseudo. */ | |
252b5132 | 1627 | |
69c040df AM |
1628 | static void |
1629 | ppc_setup_opcodes (void) | |
252b5132 | 1630 | { |
98027b10 | 1631 | const struct powerpc_opcode *op; |
252b5132 | 1632 | const struct powerpc_opcode *op_end; |
5b7c81bd | 1633 | bool bad_insn = false; |
252b5132 | 1634 | |
69c040df | 1635 | if (ppc_hash != NULL) |
a887be69 AM |
1636 | { |
1637 | htab_delete (ppc_hash); | |
1638 | _obstack_free (&insn_obstack, NULL); | |
1639 | } | |
1640 | ||
1641 | obstack_begin (&insn_obstack, chunksize); | |
252b5132 RH |
1642 | |
1643 | /* Insert the opcodes into a hash table. */ | |
a887be69 AM |
1644 | ppc_hash = htab_create_alloc (5000, hash_string_tuple, eq_string_tuple, |
1645 | NULL, insn_calloc, NULL); | |
252b5132 | 1646 | |
c43a438d | 1647 | if (ENABLE_CHECKING) |
b84bf58a | 1648 | { |
c43a438d | 1649 | unsigned int i; |
b84bf58a | 1650 | |
3b8b57a9 | 1651 | /* An index into powerpc_operands is stored in struct fix |
8e5eb8e1 DS |
1652 | fx_pcrel_adjust which is a 16 bit field. */ |
1653 | gas_assert (num_powerpc_operands <= PPC_OPINDEX_MAX + 1); | |
3b8b57a9 | 1654 | |
c43a438d AM |
1655 | /* Check operand masks. Code here and in the disassembler assumes |
1656 | all the 1's in the mask are contiguous. */ | |
1657 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1658 | { |
0f873fd5 | 1659 | uint64_t mask = powerpc_operands[i].bitm; |
59f08271 | 1660 | unsigned long flags = powerpc_operands[i].flags; |
0f873fd5 | 1661 | uint64_t right_bit; |
c43a438d AM |
1662 | unsigned int j; |
1663 | ||
59f08271 DS |
1664 | if ((flags & PPC_OPERAND_PLUS1) != 0 |
1665 | && (flags & PPC_OPERAND_NONZERO) != 0) | |
1666 | as_bad ("mutually exclusive operand flags"); | |
1667 | ||
c43a438d AM |
1668 | right_bit = mask & -mask; |
1669 | mask += right_bit; | |
1670 | right_bit = mask & -mask; | |
1671 | if (mask != right_bit) | |
1672 | { | |
1673 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
5b7c81bd | 1674 | bad_insn = true; |
c43a438d AM |
1675 | } |
1676 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1677 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1678 | sizeof (powerpc_operands[0])) == 0) | |
1679 | { | |
1680 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1681 | j, i); | |
5b7c81bd | 1682 | bad_insn = true; |
c43a438d | 1683 | } |
b84bf58a AM |
1684 | } |
1685 | } | |
1686 | ||
252b5132 RH |
1687 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1688 | for (op = powerpc_opcodes; op < op_end; op++) | |
1689 | { | |
c43a438d | 1690 | if (ENABLE_CHECKING) |
b84bf58a | 1691 | { |
2ceb7719 | 1692 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1693 | |
1694 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1695 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1696 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1697 | new_opcode, (unsigned long long) op->opcode, | |
1698 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1699 | #endif |
1700 | ||
2ceb7719 PB |
1701 | /* The major opcodes had better be sorted. Code in the disassembler |
1702 | assumes the insns are sorted according to major opcode. */ | |
1703 | if (op != powerpc_opcodes | |
1704 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1705 | { | |
1706 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1707 | bad_insn = true; |
8dbcd839 | 1708 | } |
2ceb7719 | 1709 | |
14b57c7c AM |
1710 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1711 | { | |
1712 | as_bad (_("%s is enabled by vle flag"), op->name); | |
5b7c81bd | 1713 | bad_insn = true; |
14b57c7c AM |
1714 | } |
1715 | if (PPC_OP (op->opcode) != 4 | |
1716 | && PPC_OP (op->opcode) != 31 | |
1717 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1718 | { | |
1719 | as_bad (_("%s not disabled by vle flag"), op->name); | |
5b7c81bd | 1720 | bad_insn = true; |
14b57c7c | 1721 | } |
b9c361e0 JL |
1722 | bad_insn |= insn_validate (op); |
1723 | } | |
c43a438d | 1724 | |
b9c361e0 | 1725 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1726 | && !(ppc_cpu & op->deprecated) |
1727 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1728 | { | |
1729 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1730 | bad_insn = true; |
fe0e921f | 1731 | } |
b9c361e0 | 1732 | } |
c43a438d | 1733 | |
b9c361e0 JL |
1734 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1735 | for (op = powerpc_opcodes; op < op_end; op++) | |
fe0e921f | 1736 | str_hash_insert (ppc_hash, op->name, op, 0); |
b9c361e0 | 1737 | |
dd7efa79 PB |
1738 | op_end = prefix_opcodes + prefix_num_opcodes; |
1739 | for (op = prefix_opcodes; op < op_end; op++) | |
1740 | { | |
1741 | if (ENABLE_CHECKING) | |
1742 | { | |
1743 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1744 | ||
1745 | #ifdef PRINT_OPCODE_TABLE | |
1746 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1747 | op->name, (unsigned int) (op - prefix_opcodes), | |
1748 | new_opcode, (unsigned long long) op->opcode, | |
1749 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1750 | #endif | |
1751 | ||
1752 | /* The major opcodes had better be sorted. Code in the disassembler | |
1753 | assumes the insns are sorted according to major opcode. */ | |
1754 | if (op != prefix_opcodes | |
1755 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1756 | { | |
1757 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1758 | bad_insn = true; |
dd7efa79 PB |
1759 | } |
1760 | bad_insn |= insn_validate (op); | |
1761 | } | |
1762 | ||
1763 | if ((ppc_cpu & op->flags) != 0 | |
fe0e921f AM |
1764 | && !(ppc_cpu & op->deprecated) |
1765 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1766 | { | |
1767 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1768 | bad_insn = true; |
fe0e921f | 1769 | } |
dd7efa79 PB |
1770 | } |
1771 | ||
1772 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1773 | for (op = prefix_opcodes; op < op_end; op++) | |
fe0e921f | 1774 | str_hash_insert (ppc_hash, op->name, op, 0); |
dd7efa79 | 1775 | |
b9c361e0 JL |
1776 | op_end = vle_opcodes + vle_num_opcodes; |
1777 | for (op = vle_opcodes; op < op_end; op++) | |
1778 | { | |
1779 | if (ENABLE_CHECKING) | |
1780 | { | |
2ceb7719 | 1781 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1782 | |
1783 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1784 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1785 | op->name, (unsigned int) (op - vle_opcodes), | |
1786 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1787 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1788 | #endif |
2ceb7719 PB |
1789 | |
1790 | /* The major opcodes had better be sorted. Code in the disassembler | |
1791 | assumes the insns are sorted according to major opcode. */ | |
1792 | if (op != vle_opcodes | |
1793 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1794 | { | |
1795 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1796 | bad_insn = true; |
b9c361e0 JL |
1797 | } |
1798 | ||
1799 | bad_insn |= insn_validate (op); | |
c43a438d | 1800 | } |
252b5132 | 1801 | |
bdc70b4a | 1802 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1803 | && !(ppc_cpu & op->deprecated) |
1804 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1805 | { | |
1806 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1807 | bad_insn = true; |
fe0e921f | 1808 | } |
252b5132 RH |
1809 | } |
1810 | ||
74081948 AF |
1811 | /* SPE2 instructions */ |
1812 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1813 | { | |
1814 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1815 | for (op = spe2_opcodes; op < op_end; op++) | |
1816 | { | |
1817 | if (ENABLE_CHECKING) | |
1818 | { | |
1819 | if (op != spe2_opcodes) | |
1820 | { | |
1821 | unsigned old_seg, new_seg; | |
1822 | ||
1823 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1824 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1825 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1826 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1827 | ||
1828 | /* The major opcodes had better be sorted. Code in the | |
1829 | disassembler assumes the insns are sorted according to | |
1830 | major opcode. */ | |
1831 | if (new_seg < old_seg) | |
1832 | { | |
1833 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1834 | bad_insn = true; |
74081948 AF |
1835 | } |
1836 | } | |
1837 | ||
1838 | bad_insn |= insn_validate (op); | |
1839 | } | |
1840 | ||
fe0e921f AM |
1841 | if ((ppc_cpu & op->flags) != 0 |
1842 | && !(ppc_cpu & op->deprecated) | |
1843 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1844 | { | |
1845 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1846 | bad_insn = true; |
fe0e921f | 1847 | } |
74081948 AF |
1848 | } |
1849 | ||
1850 | for (op = spe2_opcodes; op < op_end; op++) | |
fe0e921f | 1851 | str_hash_insert (ppc_hash, op->name, op, 0); |
74081948 AF |
1852 | } |
1853 | ||
b84bf58a | 1854 | if (bad_insn) |
252b5132 | 1855 | abort (); |
69c040df AM |
1856 | } |
1857 | ||
1858 | /* This function is called when the assembler starts up. It is called | |
1859 | after the options have been parsed and the output file has been | |
1860 | opened. */ | |
1861 | ||
1862 | void | |
98027b10 | 1863 | md_begin (void) |
69c040df AM |
1864 | { |
1865 | ppc_set_cpu (); | |
1866 | ||
1867 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1868 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1869 | |
1870 | #ifdef OBJ_ELF | |
1871 | /* Set the ELF flags if desired. */ | |
1872 | if (ppc_flags && !msolaris) | |
1873 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1874 | #endif | |
1875 | ||
1876 | ppc_setup_opcodes (); | |
252b5132 | 1877 | |
67c1ffbe | 1878 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1879 | by the user. */ |
252b5132 RH |
1880 | if (!set_target_endian) |
1881 | { | |
1882 | set_target_endian = 1; | |
1883 | target_big_endian = PPC_BIG_ENDIAN; | |
1884 | } | |
1885 | ||
1886 | #ifdef OBJ_XCOFF | |
1887 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1888 | ||
1b2cb8e2 CC |
1889 | /* Create XCOFF sections with .text in first, as it's creating dummy symbols |
1890 | to serve as initial csects. This forces the text csects to precede the | |
1891 | data csects. These symbols will not be output. */ | |
934cb849 CC |
1892 | ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section); |
1893 | ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section); | |
1894 | ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section); | |
252b5132 | 1895 | #endif |
252b5132 RH |
1896 | } |
1897 | ||
a887be69 AM |
1898 | void |
1899 | ppc_md_end (void) | |
1900 | { | |
a14413dd AM |
1901 | if (ppc_hash) |
1902 | { | |
1903 | htab_delete (ppc_hash); | |
1904 | _obstack_free (&insn_obstack, NULL); | |
1905 | } | |
1906 | ppc_hash = NULL; | |
a887be69 AM |
1907 | } |
1908 | ||
6a0c61b7 | 1909 | void |
98027b10 | 1910 | ppc_cleanup (void) |
6a0c61b7 | 1911 | { |
dc1d03fc | 1912 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1913 | if (ppc_apuinfo_list == NULL) |
1914 | return; | |
1915 | ||
1916 | /* Ok, so write the section info out. We have this layout: | |
1917 | ||
1918 | byte data what | |
1919 | ---- ---- ---- | |
1920 | 0 8 length of "APUinfo\0" | |
1921 | 4 (n*4) number of APU's (4 bytes each) | |
1922 | 8 2 note type 2 | |
1923 | 12 "APUinfo\0" name | |
1924 | 20 APU#1 first APU's info | |
1925 | 24 APU#2 second APU's info | |
1926 | ... ... | |
1927 | */ | |
1928 | { | |
1929 | char *p; | |
1930 | asection *seg = now_seg; | |
1931 | subsegT subseg = now_subseg; | |
1932 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1933 | unsigned int i; |
6a0c61b7 EZ |
1934 | |
1935 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1936 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1937 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1938 | |
1939 | p = frag_more (4); | |
1940 | md_number_to_chars (p, (valueT) 8, 4); | |
1941 | ||
1942 | p = frag_more (4); | |
e98d298c | 1943 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1944 | |
1945 | p = frag_more (4); | |
1946 | md_number_to_chars (p, (valueT) 2, 4); | |
1947 | ||
1948 | p = frag_more (8); | |
14b57c7c | 1949 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
1950 | |
1951 | for (i = 0; i < ppc_apuinfo_num; i++) | |
1952 | { | |
b34976b6 AM |
1953 | p = frag_more (4); |
1954 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
1955 | } |
1956 | ||
1957 | frag_align (2, 0, 0); | |
1958 | ||
1959 | /* We probably can't restore the current segment, for there likely | |
1960 | isn't one yet... */ | |
1961 | if (seg && subseg) | |
1962 | subseg_set (seg, subseg); | |
1963 | } | |
dc1d03fc | 1964 | #endif |
6a0c61b7 EZ |
1965 | } |
1966 | ||
252b5132 RH |
1967 | /* Insert an operand value into an instruction. */ |
1968 | ||
0f873fd5 PB |
1969 | static uint64_t |
1970 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 1971 | const struct powerpc_operand *operand, |
0f873fd5 | 1972 | int64_t val, |
91d6fa6a | 1973 | ppc_cpu_t cpu, |
3b4dbbbf | 1974 | const char *file, |
a1867a27 | 1975 | unsigned int line) |
252b5132 | 1976 | { |
0f873fd5 | 1977 | int64_t min, max, right; |
eb42fac1 | 1978 | |
b84bf58a AM |
1979 | max = operand->bitm; |
1980 | right = max & -max; | |
1981 | min = 0; | |
1982 | ||
a47622ac | 1983 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 1984 | { |
a255f00a AM |
1985 | /* Extend the allowed range for addis to [-32768, 65535]. |
1986 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
1987 | it would be good to disable this for signed fields since the | |
a47622ac AM |
1988 | value is sign extended into the high 32 bits of the register. |
1989 | If the value is, say, an address, then we might care about | |
1990 | the high bits. However, gcc as of 2014-06 uses unsigned | |
1991 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
1992 | lis. */ |
1993 | min = ~(max >> 1) & -right; | |
a47622ac AM |
1994 | } |
1995 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
1996 | { | |
1997 | max = (max >> 1) & -right; | |
931774a9 | 1998 | min = ~max & -right; |
b84bf58a | 1999 | } |
59f08271 DS |
2000 | else if ((operand->flags & PPC_OPERAND_NONZERO) != 0) |
2001 | { | |
2002 | ++min; | |
2003 | ++max; | |
2004 | } | |
252b5132 | 2005 | |
b84bf58a | 2006 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 2007 | max++; |
252b5132 | 2008 | |
b84bf58a | 2009 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 2010 | { |
0f873fd5 | 2011 | int64_t tmp = min; |
a1867a27 AM |
2012 | min = -max; |
2013 | max = -tmp; | |
2014 | } | |
b84bf58a | 2015 | |
a1867a27 AM |
2016 | if (min <= max) |
2017 | { | |
2018 | /* Some people write constants with the sign extension done by | |
2019 | hand but only up to 32 bits. This shouldn't really be valid, | |
2020 | but, to permit this code to assemble on a 64-bit host, we | |
2021 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
2022 | value valid. We only do this for operands that are 32-bits or |
2023 | smaller. */ | |
a1867a27 | 2024 | if (val > max |
8acf1435 | 2025 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2026 | && (val - (1LL << 32)) >= min |
2027 | && (val - (1LL << 32)) <= max | |
2028 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
2029 | val = val - (1LL << 32); | |
a1867a27 AM |
2030 | |
2031 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2032 | this to be OK for a 32-bit unsigned value. */ | |
2033 | else if (val < min | |
8acf1435 | 2034 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2035 | && (val + (1LL << 32)) >= min |
2036 | && (val + (1LL << 32)) <= max | |
2037 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
2038 | val = val + (1LL << 32); | |
a1867a27 AM |
2039 | |
2040 | else if (val < min | |
2041 | || val > max | |
2042 | || (val & (right - 1)) != 0) | |
2043 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2044 | } | |
b84bf58a | 2045 | |
252b5132 RH |
2046 | if (operand->insert) |
2047 | { | |
2048 | const char *errmsg; | |
2049 | ||
2050 | errmsg = NULL; | |
0f873fd5 | 2051 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2052 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2053 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2054 | } |
b9c361e0 | 2055 | else |
59f08271 DS |
2056 | { |
2057 | if ((operand->flags & PPC_OPERAND_NONZERO) != 0) | |
2058 | --val; | |
2059 | if (operand->shift >= 0) | |
2060 | insn |= (val & operand->bitm) << operand->shift; | |
2061 | else | |
2062 | insn |= (val & operand->bitm) >> -operand->shift; | |
2063 | } | |
252b5132 RH |
2064 | |
2065 | return insn; | |
2066 | } | |
2067 | ||
2068 | \f | |
2069 | #ifdef OBJ_ELF | |
2070 | /* Parse @got, etc. and return the desired relocation. */ | |
2071 | static bfd_reloc_code_real_type | |
98027b10 | 2072 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2073 | { |
2074 | struct map_bfd { | |
e0471c16 | 2075 | const char *string; |
b7d7dc63 AM |
2076 | unsigned int length : 8; |
2077 | unsigned int valid32 : 1; | |
2078 | unsigned int valid64 : 1; | |
2079 | unsigned int reloc; | |
252b5132 RH |
2080 | }; |
2081 | ||
2082 | char ident[20]; | |
2083 | char *str = *str_p; | |
2084 | char *str2; | |
2085 | int ch; | |
2086 | int len; | |
15c1449b | 2087 | const struct map_bfd *ptr; |
252b5132 | 2088 | |
b7d7dc63 AM |
2089 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2090 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2091 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2092 | |
15c1449b | 2093 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2094 | MAP ("l", BFD_RELOC_LO16), |
2095 | MAP ("h", BFD_RELOC_HI16), | |
2096 | MAP ("ha", BFD_RELOC_HI16_S), | |
2097 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2098 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2099 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2100 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2101 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2102 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2103 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2104 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2105 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2106 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2107 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2108 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2109 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2110 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2111 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2112 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2113 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2114 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2115 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2116 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2117 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2118 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2119 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2120 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2121 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2122 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2123 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2124 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2125 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2126 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2127 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2128 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2129 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2130 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2131 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2132 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2133 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2134 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2135 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2136 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2137 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2138 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2139 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2140 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2141 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2142 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2143 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2144 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2145 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2146 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2147 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2148 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2149 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2150 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2151 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2152 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2153 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2154 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2155 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2156 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2157 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2158 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2159 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2160 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2161 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2162 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2163 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2164 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2165 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2166 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2167 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2168 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2169 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2170 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2171 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2172 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2173 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2174 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2175 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2176 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2177 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2178 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2179 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2180 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2181 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2182 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2183 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2184 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2185 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2186 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2187 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2188 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2189 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2190 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2191 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2192 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2193 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a | 2194 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
87c69f97 AM |
2195 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34), |
2196 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34), | |
2197 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34), | |
2198 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34), | |
5663e321 AM |
2199 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2200 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2201 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2202 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2203 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2204 | }; |
2205 | ||
2206 | if (*str++ != '@') | |
62ebcb5c | 2207 | return BFD_RELOC_NONE; |
252b5132 RH |
2208 | |
2209 | for (ch = *str, str2 = ident; | |
2210 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2211 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2212 | ch = *++str) |
2213 | { | |
3882b010 | 2214 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2215 | } |
2216 | ||
2217 | *str2 = '\0'; | |
2218 | len = str2 - ident; | |
2219 | ||
2220 | ch = ident[0]; | |
2221 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2222 | if (ch == ptr->string[0] | |
2223 | && len == ptr->length | |
b7d7dc63 AM |
2224 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2225 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2226 | { |
15c1449b AM |
2227 | int reloc = ptr->reloc; |
2228 | ||
32d71569 | 2229 | if (!ppc_obj64 && (exp_p->X_op == O_big || exp_p->X_add_number != 0)) |
727fc41e AM |
2230 | { |
2231 | switch (reloc) | |
2232 | { | |
2233 | case BFD_RELOC_16_GOTOFF: | |
2234 | case BFD_RELOC_LO16_GOTOFF: | |
2235 | case BFD_RELOC_HI16_GOTOFF: | |
2236 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2237 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2238 | ptr->string, ptr->string); | |
727fc41e AM |
2239 | break; |
2240 | ||
2241 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2242 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2243 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2244 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2245 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2246 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2247 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2248 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2249 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2250 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2251 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2252 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2253 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2254 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2255 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2256 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2257 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2258 | break; |
2259 | } | |
2260 | } | |
5f6db75a AM |
2261 | |
2262 | /* Now check for identifier@suffix+constant. */ | |
2263 | if (*str == '-' || *str == '+') | |
252b5132 | 2264 | { |
5f6db75a AM |
2265 | char *orig_line = input_line_pointer; |
2266 | expressionS new_exp; | |
2267 | ||
2268 | input_line_pointer = str; | |
2269 | expression (&new_exp); | |
32d71569 | 2270 | if (new_exp.X_op == O_constant && exp_p->X_op != O_big) |
252b5132 | 2271 | { |
5f6db75a AM |
2272 | exp_p->X_add_number += new_exp.X_add_number; |
2273 | str = input_line_pointer; | |
252b5132 | 2274 | } |
32d71569 | 2275 | input_line_pointer = orig_line; |
252b5132 | 2276 | } |
252b5132 | 2277 | *str_p = str; |
0baf16f2 | 2278 | |
2b3c4602 | 2279 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2280 | && exp_p->X_op == O_symbol |
2281 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2282 | { |
9f2b53d7 AM |
2283 | /* Change the symbol so that the dummy .TOC. symbol can be |
2284 | omitted from the object file. */ | |
0baf16f2 AM |
2285 | exp_p->X_add_symbol = &abs_symbol; |
2286 | } | |
2287 | ||
7aba54da AM |
2288 | if (reloc == BFD_RELOC_PPC64_REL24_NOTOC |
2289 | && (ppc_cpu & PPC_OPCODE_POWER10) == 0) | |
2290 | reloc = BFD_RELOC_PPC64_REL24_P9NOTOC; | |
2291 | ||
15c1449b | 2292 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2293 | } |
2294 | ||
62ebcb5c | 2295 | return BFD_RELOC_NONE; |
252b5132 RH |
2296 | } |
2297 | ||
62ebcb5c | 2298 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2299 | |
62ebcb5c AM |
2300 | bfd_reloc_code_real_type |
2301 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2302 | { | |
2303 | expression (exp); | |
2304 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2305 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2306 | return BFD_RELOC_NONE; | |
252b5132 RH |
2307 | } |
2308 | ||
bf7279d5 AM |
2309 | /* Warn when emitting data to code sections, unless we are emitting |
2310 | a relocation that ld --ppc476-workaround uses to recognise data | |
2311 | *and* there was an unconditional branch prior to the data. */ | |
2312 | ||
2313 | void | |
2314 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2315 | unsigned int nbytes, fixS *fix) | |
2316 | { | |
2317 | if (warn_476 | |
2318 | && (now_seg->flags & SEC_CODE) != 0 | |
2319 | && (nbytes != 4 | |
2320 | || fix == NULL | |
2321 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2322 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2323 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2324 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2325 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2326 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2327 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2328 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2329 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2330 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2331 | { | |
2332 | /* Flag that we've warned. */ | |
2333 | if (fix != NULL) | |
2334 | fix->fx_tcbit = 1; | |
2335 | ||
2336 | as_warn (_("data in executable section")); | |
2337 | } | |
2338 | } | |
2339 | ||
252b5132 RH |
2340 | /* Solaris pseduo op to change to the .rodata section. */ |
2341 | static void | |
98027b10 | 2342 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2343 | { |
2344 | char *save_line = input_line_pointer; | |
2345 | static char section[] = ".rodata\n"; | |
2346 | ||
99a814a1 | 2347 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2348 | input_line_pointer = section; |
2349 | obj_elf_section (xxx); | |
2350 | ||
2351 | input_line_pointer = save_line; | |
2352 | } | |
2353 | ||
99a814a1 | 2354 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2355 | static void |
98027b10 | 2356 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2357 | { |
98027b10 AM |
2358 | char *name; |
2359 | char c; | |
2360 | char *p; | |
252b5132 | 2361 | offsetT size; |
98027b10 | 2362 | symbolS *symbolP; |
252b5132 RH |
2363 | offsetT align; |
2364 | segT old_sec; | |
2365 | int old_subsec; | |
2366 | char *pfrag; | |
2367 | int align2; | |
2368 | ||
d02603dc | 2369 | c = get_symbol_name (&name); |
252b5132 | 2370 | |
d02603dc | 2371 | /* Just after name is now '\0'. */ |
252b5132 RH |
2372 | p = input_line_pointer; |
2373 | *p = c; | |
d02603dc | 2374 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2375 | if (*input_line_pointer != ',') |
2376 | { | |
d6ed37ed | 2377 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2378 | ignore_rest_of_line (); |
2379 | return; | |
2380 | } | |
2381 | ||
2382 | input_line_pointer++; /* skip ',' */ | |
2383 | if ((size = get_absolute_expression ()) < 0) | |
2384 | { | |
2385 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2386 | ignore_rest_of_line (); | |
2387 | return; | |
2388 | } | |
2389 | ||
2390 | /* The third argument to .lcomm is the alignment. */ | |
2391 | if (*input_line_pointer != ',') | |
2392 | align = 8; | |
2393 | else | |
2394 | { | |
2395 | ++input_line_pointer; | |
2396 | align = get_absolute_expression (); | |
2397 | if (align <= 0) | |
2398 | { | |
2399 | as_warn (_("ignoring bad alignment")); | |
2400 | align = 8; | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | *p = 0; | |
2405 | symbolP = symbol_find_or_make (name); | |
2406 | *p = c; | |
2407 | ||
2408 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2409 | { | |
d6ed37ed | 2410 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2411 | S_GET_NAME (symbolP)); |
2412 | ignore_rest_of_line (); | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2417 | { | |
d6ed37ed | 2418 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2419 | S_GET_NAME (symbolP), |
2420 | (long) S_GET_VALUE (symbolP), | |
2421 | (long) size); | |
2422 | ||
2423 | ignore_rest_of_line (); | |
2424 | return; | |
2425 | } | |
2426 | ||
99a814a1 | 2427 | /* Allocate_bss. */ |
252b5132 RH |
2428 | old_sec = now_seg; |
2429 | old_subsec = now_subseg; | |
2430 | if (align) | |
2431 | { | |
99a814a1 | 2432 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2433 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2434 | if (align != 1) | |
2435 | { | |
d6ed37ed | 2436 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2437 | ignore_rest_of_line (); |
2438 | return; | |
2439 | } | |
2440 | } | |
2441 | else | |
2442 | align2 = 0; | |
2443 | ||
2444 | record_alignment (bss_section, align2); | |
cbe02d4f | 2445 | subseg_set (bss_section, 1); |
252b5132 RH |
2446 | if (align2) |
2447 | frag_align (align2, 0, 0); | |
2448 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2449 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2450 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2451 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2452 | (char *) 0); | |
2453 | *pfrag = 0; | |
2454 | S_SET_SIZE (symbolP, size); | |
2455 | S_SET_SEGMENT (symbolP, bss_section); | |
2456 | subseg_set (old_sec, old_subsec); | |
2457 | demand_empty_rest_of_line (); | |
2458 | } | |
2459 | ||
6911b7dc AM |
2460 | /* Pseudo op to set symbol local entry point. */ |
2461 | static void | |
2462 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2463 | { | |
d02603dc NC |
2464 | char *name; |
2465 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2466 | char *p; |
2467 | expressionS exp; | |
2468 | symbolS *sym; | |
2469 | asymbol *bfdsym; | |
2470 | elf_symbol_type *elfsym; | |
2471 | ||
2472 | p = input_line_pointer; | |
2473 | *p = c; | |
d02603dc | 2474 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2475 | if (*input_line_pointer != ',') |
2476 | { | |
2477 | *p = 0; | |
2478 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2479 | name); | |
2480 | *p = c; | |
2481 | ignore_rest_of_line (); | |
2482 | return; | |
2483 | } | |
2484 | input_line_pointer++; | |
2485 | expression (&exp); | |
2486 | if (exp.X_op == O_absent) | |
2487 | { | |
2488 | as_bad (_("missing expression in .localentry directive")); | |
2489 | exp.X_op = O_constant; | |
2490 | exp.X_add_number = 0; | |
2491 | } | |
2492 | *p = 0; | |
2493 | sym = symbol_find_or_make (name); | |
2494 | *p = c; | |
2495 | ||
2496 | if (resolve_expression (&exp) | |
2497 | && exp.X_op == O_constant) | |
2498 | { | |
33cb30a1 | 2499 | unsigned int encoded, ok; |
6911b7dc | 2500 | |
33cb30a1 AM |
2501 | ok = 1; |
2502 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2503 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2504 | else |
33cb30a1 AM |
2505 | { |
2506 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2507 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2508 | { | |
2509 | as_bad (_(".localentry expression for `%s' " | |
2510 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2511 | ok = 0; | |
2512 | } | |
2513 | } | |
2514 | if (ok) | |
6911b7dc AM |
2515 | { |
2516 | bfdsym = symbol_get_bfdsym (sym); | |
c1229f84 | 2517 | elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
2518 | gas_assert (elfsym); |
2519 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2520 | elfsym->internal_elf_sym.st_other |= encoded; | |
2521 | if (ppc_abiversion == 0) | |
2522 | ppc_abiversion = 2; | |
2523 | } | |
2524 | } | |
2525 | else | |
2526 | as_bad (_(".localentry expression for `%s' " | |
2527 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2528 | ||
2529 | demand_empty_rest_of_line (); | |
2530 | } | |
2531 | ||
ee67d69a AM |
2532 | /* Pseudo op to set ABI version. */ |
2533 | static void | |
2534 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2535 | { | |
2536 | expressionS exp; | |
2537 | ||
2538 | expression (&exp); | |
2539 | if (exp.X_op == O_absent) | |
2540 | { | |
2541 | as_bad (_("missing expression in .abiversion directive")); | |
2542 | exp.X_op = O_constant; | |
2543 | exp.X_add_number = 0; | |
2544 | } | |
2545 | ||
2546 | if (resolve_expression (&exp) | |
2547 | && exp.X_op == O_constant) | |
2548 | ppc_abiversion = exp.X_add_number; | |
2549 | else | |
2550 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2551 | demand_empty_rest_of_line (); | |
2552 | } | |
2553 | ||
005d79fd AM |
2554 | /* Parse a .gnu_attribute directive. */ |
2555 | static void | |
2556 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2557 | { | |
2558 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2559 | ||
2560 | /* Check validity of defined powerpc tags. */ | |
2561 | if (tag == Tag_GNU_Power_ABI_FP | |
2562 | || tag == Tag_GNU_Power_ABI_Vector | |
2563 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2564 | { | |
2565 | unsigned int val; | |
2566 | ||
2567 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2568 | ||
2569 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2570 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2571 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2572 | as_warn (_("unknown .gnu_attribute value")); | |
2573 | } | |
2574 | } | |
2575 | ||
ee67d69a AM |
2576 | /* Set ABI version in output file. */ |
2577 | void | |
ed2917de | 2578 | ppc_elf_md_finish (void) |
ee67d69a AM |
2579 | { |
2580 | if (ppc_obj64 && ppc_abiversion != 0) | |
2581 | { | |
2582 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2583 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2584 | } | |
22f72c48 AM |
2585 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2586 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2587 | must select opcodes based on the machine in force at the point | |
2588 | where the fixup or alignment frag was created, not the machine in | |
2589 | force at the end of file. */ | |
2590 | ppc_cpu = 0; | |
ee67d69a AM |
2591 | } |
2592 | ||
252b5132 RH |
2593 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2594 | fixups for word relocations in writable segments, so we can adjust | |
2595 | them at runtime. */ | |
2596 | static void | |
98027b10 | 2597 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2598 | { |
2599 | if (fixp->fx_done || fixp->fx_pcrel) | |
2600 | return; | |
2601 | ||
2602 | switch (shlib) | |
2603 | { | |
2604 | case SHLIB_NONE: | |
2605 | case SHLIB_PIC: | |
2606 | return; | |
2607 | ||
5d6f4f16 | 2608 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2609 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2610 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2611 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2612 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2613 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2614 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2615 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2616 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2617 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2618 | && strcmp (segment_name (seg), ".got2") != 0 |
2619 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2620 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2621 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2622 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2623 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2624 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2625 | { | |
2626 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2627 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2628 | { | |
2629 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2630 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2631 | } |
2632 | } | |
2633 | return; | |
2634 | } | |
2635 | } | |
0baf16f2 | 2636 | |
7e8d4ab4 AM |
2637 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2638 | function descriptor sym if the corresponding code sym is used. */ | |
2639 | ||
2640 | void | |
98027b10 | 2641 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2642 | { |
7e8d4ab4 | 2643 | symbolS *symp; |
9232bbb0 | 2644 | asection *toc; |
0baf16f2 | 2645 | |
7e8d4ab4 AM |
2646 | if (!ppc_obj64) |
2647 | return; | |
2648 | ||
2649 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2650 | { |
7e8d4ab4 AM |
2651 | const char *name; |
2652 | char *dotname; | |
2653 | symbolS *dotsym; | |
7e8d4ab4 AM |
2654 | |
2655 | name = S_GET_NAME (symp); | |
2656 | if (name[0] == '.') | |
2657 | continue; | |
2658 | ||
2659 | if (! S_IS_WEAK (symp) | |
2660 | || S_IS_DEFINED (symp)) | |
2661 | continue; | |
2662 | ||
a44e2901 | 2663 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2664 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2665 | free (dotname); |
2666 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2667 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2668 | symbol_mark_used (symp); |
2669 | ||
0baf16f2 AM |
2670 | } |
2671 | ||
9232bbb0 AM |
2672 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2673 | if (toc != NULL | |
01efc3af | 2674 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2675 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2676 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2677 | } |
2678 | ||
2679 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2680 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2681 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2682 | |
a38a07e0 AM |
2683 | void |
2684 | ppc_elf_adjust_symtab (void) | |
2685 | { | |
2686 | if (ppc_obj64) | |
2687 | { | |
2688 | symbolS *symp; | |
2689 | symp = symbol_find (".TOC."); | |
2690 | if (symp != NULL) | |
2691 | { | |
2692 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2693 | if ((bsym->flags & BSF_KEEP) == 0) | |
2694 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2695 | } |
2696 | } | |
0baf16f2 | 2697 | } |
252b5132 | 2698 | #endif /* OBJ_ELF */ |
4a403be0 CC |
2699 | |
2700 | #ifdef OBJ_XCOFF | |
2701 | /* Parse XCOFF relocations. */ | |
2702 | static bfd_reloc_code_real_type | |
2703 | ppc_xcoff_suffix (char **str_p) | |
2704 | { | |
2705 | struct map_bfd { | |
2706 | const char *string; | |
2707 | unsigned int length : 8; | |
2708 | unsigned int valid32 : 1; | |
2709 | unsigned int valid64 : 1; | |
2710 | unsigned int reloc; | |
2711 | }; | |
2712 | ||
2713 | char ident[20]; | |
2714 | char *str = *str_p; | |
2715 | char *str2; | |
2716 | int ch; | |
2717 | int len; | |
2718 | const struct map_bfd *ptr; | |
2719 | ||
2720 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } | |
2721 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2722 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
2723 | ||
2724 | static const struct map_bfd mapping[] = { | |
2725 | MAP ("l", BFD_RELOC_PPC_TOC16_LO), | |
2726 | MAP ("u", BFD_RELOC_PPC_TOC16_HI), | |
1b2cb8e2 CC |
2727 | MAP32 ("ie", BFD_RELOC_PPC_TLSIE), |
2728 | MAP32 ("ld", BFD_RELOC_PPC_TLSLD), | |
2729 | MAP32 ("le", BFD_RELOC_PPC_TLSLE), | |
2730 | MAP32 ("m", BFD_RELOC_PPC_TLSM), | |
2731 | MAP32 ("ml", BFD_RELOC_PPC_TLSML), | |
2732 | MAP64 ("ie", BFD_RELOC_PPC64_TLSIE), | |
2733 | MAP64 ("ld", BFD_RELOC_PPC64_TLSLD), | |
2734 | MAP64 ("le", BFD_RELOC_PPC64_TLSLE), | |
2735 | MAP64 ("m", BFD_RELOC_PPC64_TLSM), | |
2736 | MAP64 ("ml", BFD_RELOC_PPC64_TLSML), | |
4a403be0 CC |
2737 | }; |
2738 | ||
2739 | if (*str++ != '@') | |
2740 | return BFD_RELOC_NONE; | |
2741 | ||
2742 | for (ch = *str, str2 = ident; | |
2743 | (str2 < ident + sizeof (ident) - 1 | |
2744 | && (ISALNUM (ch) || ch == '@')); | |
2745 | ch = *++str) | |
2746 | { | |
2747 | *str2++ = TOLOWER (ch); | |
2748 | } | |
2749 | ||
2750 | *str2 = '\0'; | |
2751 | len = str2 - ident; | |
2752 | ||
2753 | ch = ident[0]; | |
2754 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2755 | if (ch == ptr->string[0] | |
2756 | && len == ptr->length | |
2757 | && memcmp (ident, ptr->string, ptr->length) == 0 | |
2758 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
2759 | { | |
2760 | *str_p = str; | |
2761 | return (bfd_reloc_code_real_type) ptr->reloc; | |
2762 | } | |
2763 | ||
2764 | return BFD_RELOC_NONE; | |
2765 | } | |
2766 | ||
2767 | /* Restore XCOFF addis instruction to ELF format. | |
2768 | AIX often generates addis instructions using "addis RT,D(RA)" | |
2769 | format instead of the ELF "addis RT,RA,SI" one. | |
2770 | On entry RT_E is at the comma after RT, D_E is at the open | |
2771 | parenthesis after D, and RA_E is at the close parenthesis after RA. */ | |
2772 | static void | |
2773 | ppc_xcoff_fixup_addis (char *rt_e, char *d_e, char *ra_e) | |
2774 | { | |
2775 | size_t ra_size = ra_e - d_e - 1; | |
2776 | char *save_ra = xmalloc (ra_size); | |
2777 | ||
2778 | /* Copy RA. */ | |
2779 | memcpy (save_ra, d_e + 1, ra_size); | |
2780 | /* Shuffle D to make room for RA, copying the comma too. */ | |
2781 | memmove (rt_e + ra_size + 1, rt_e, d_e - rt_e); | |
2782 | /* Erase the trailing ')', keeping any rubbish for potential errors. */ | |
2783 | memmove (ra_e, ra_e + 1, strlen (ra_e)); | |
2784 | /* Write RA back. */ | |
2785 | memcpy (rt_e + 1, save_ra, ra_size); | |
2786 | free (save_ra); | |
2787 | } | |
2788 | ||
1b2cb8e2 CC |
2789 | /* Support @ie, etc. on constants emitted via .short, .int etc. */ |
2790 | ||
2791 | bfd_reloc_code_real_type | |
2792 | ppc_xcoff_parse_cons (expressionS *exp, unsigned int nbytes) | |
2793 | { | |
2794 | expression (exp); | |
2795 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2796 | return ppc_xcoff_suffix (&input_line_pointer); | |
2797 | ||
2798 | /* There isn't any @ symbol for default TLS relocations (R_TLS). */ | |
2799 | if (exp->X_add_symbol != NULL | |
2800 | && (symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_TL | |
2801 | || symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_UL)) | |
2802 | return (ppc_obj64 ? BFD_RELOC_PPC64_TLSGD: BFD_RELOC_PPC_TLSGD); | |
2803 | ||
2804 | return BFD_RELOC_NONE; | |
2805 | } | |
2806 | ||
4a403be0 | 2807 | #endif /* OBJ_XCOFF */ |
252b5132 | 2808 | \f |
3e60bf4d | 2809 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2810 | /* See whether a symbol is in the TOC section. */ |
2811 | ||
2812 | static int | |
2813 | ppc_is_toc_sym (symbolS *sym) | |
2814 | { | |
3e60bf4d | 2815 | #ifdef OBJ_XCOFF |
9f6e76f4 | 2816 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
4a403be0 | 2817 | || symbol_get_tc (sym)->symbol_class == XMC_TE |
9f6e76f4 | 2818 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); |
f50c47f1 | 2819 | #endif |
3e60bf4d AM |
2820 | #ifdef OBJ_ELF |
2821 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2822 | if (ppc_obj64) | |
2823 | return strcmp (sname, ".toc") == 0; | |
2824 | else | |
2825 | return strcmp (sname, ".got") == 0; | |
2826 | #endif | |
2827 | } | |
2828 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2829 | \f |
2830 | ||
dc1d03fc | 2831 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2832 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2833 | static void | |
98027b10 | 2834 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2835 | { |
2836 | unsigned int i; | |
2837 | ||
2838 | /* Check we don't already exist. */ | |
2839 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2840 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2841 | return; |
b34976b6 | 2842 | |
6a0c61b7 EZ |
2843 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2844 | { | |
2845 | if (ppc_apuinfo_num_alloc == 0) | |
2846 | { | |
2847 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2848 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2849 | } |
2850 | else | |
2851 | { | |
2852 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2853 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2854 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2855 | } |
2856 | } | |
dc1d03fc | 2857 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2858 | } |
2859 | #undef APUID | |
dc1d03fc | 2860 | #endif |
6a0c61b7 | 2861 | \f |
dd7efa79 PB |
2862 | /* Various frobbings of labels and their addresses. */ |
2863 | ||
2864 | /* Symbols labelling the current insn. */ | |
2865 | struct insn_label_list | |
2866 | { | |
2867 | struct insn_label_list *next; | |
2868 | symbolS *label; | |
2869 | }; | |
2870 | ||
2871 | static struct insn_label_list *insn_labels; | |
2872 | static struct insn_label_list *free_insn_labels; | |
2873 | ||
2874 | static void | |
2875 | ppc_record_label (symbolS *sym) | |
2876 | { | |
2877 | struct insn_label_list *l; | |
2878 | ||
2879 | if (free_insn_labels == NULL) | |
2880 | l = XNEW (struct insn_label_list); | |
2881 | else | |
2882 | { | |
2883 | l = free_insn_labels; | |
2884 | free_insn_labels = l->next; | |
2885 | } | |
2886 | ||
2887 | l->label = sym; | |
2888 | l->next = insn_labels; | |
2889 | insn_labels = l; | |
2890 | } | |
2891 | ||
2892 | static void | |
2893 | ppc_clear_labels (void) | |
2894 | { | |
2895 | while (insn_labels != NULL) | |
2896 | { | |
2897 | struct insn_label_list *l = insn_labels; | |
2898 | insn_labels = l->next; | |
2899 | l->next = free_insn_labels; | |
2900 | free_insn_labels = l; | |
2901 | } | |
2902 | } | |
2903 | ||
2904 | void | |
2905 | ppc_start_line_hook (void) | |
2906 | { | |
2907 | ppc_clear_labels (); | |
2908 | } | |
2909 | ||
2910 | void | |
2911 | ppc_new_dot_label (symbolS *sym) | |
2912 | { | |
2913 | ppc_record_label (sym); | |
2914 | #ifdef OBJ_XCOFF | |
2915 | /* Anchor this label to the current csect for relocations. */ | |
2916 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2917 | #endif | |
2918 | } | |
2919 | ||
2920 | void | |
2921 | ppc_frob_label (symbolS *sym) | |
2922 | { | |
2923 | ppc_record_label (sym); | |
2924 | ||
2925 | #ifdef OBJ_XCOFF | |
2926 | /* Set the class of a label based on where it is defined. This handles | |
2927 | symbols without suffixes. Also, move the symbol so that it follows | |
2928 | the csect symbol. */ | |
2929 | if (ppc_current_csect != (symbolS *) NULL) | |
2930 | { | |
2931 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2932 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2933 | ||
2934 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2935 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2936 | &symbol_rootP, &symbol_lastP); | |
cd026728 | 2937 | /* Update last csect symbol. */ |
dd7efa79 | 2938 | symbol_get_tc (ppc_current_csect)->within = sym; |
cd026728 CC |
2939 | |
2940 | /* Some labels like .bs are using within differently. | |
2941 | So avoid changing it, if it's already set. */ | |
2942 | if (symbol_get_tc (sym)->within == NULL) | |
2943 | symbol_get_tc (sym)->within = ppc_current_csect; | |
dd7efa79 PB |
2944 | } |
2945 | #endif | |
2946 | ||
2947 | #ifdef OBJ_ELF | |
2948 | dwarf2_emit_label (sym); | |
2949 | #endif | |
2950 | } | |
6a0c61b7 | 2951 | |
252b5132 RH |
2952 | /* We need to keep a list of fixups. We can't simply generate them as |
2953 | we go, because that would require us to first create the frag, and | |
2954 | that would screw up references to ``.''. */ | |
2955 | ||
2956 | struct ppc_fixup | |
2957 | { | |
2958 | expressionS exp; | |
2959 | int opindex; | |
2960 | bfd_reloc_code_real_type reloc; | |
2961 | }; | |
2962 | ||
2963 | #define MAX_INSN_FIXUPS (5) | |
2964 | ||
0e2779e9 AM |
2965 | /* Return the field size operated on by RELOC, and whether it is |
2966 | pc-relative in PC_RELATIVE. */ | |
2967 | ||
2968 | static unsigned int | |
5b7c81bd | 2969 | fixup_size (bfd_reloc_code_real_type reloc, bool *pc_relative) |
0e2779e9 AM |
2970 | { |
2971 | unsigned int size = 0; | |
5b7c81bd | 2972 | bool pcrel = false; |
0e2779e9 AM |
2973 | |
2974 | switch (reloc) | |
2975 | { | |
2976 | /* This switch statement must handle all BFD_RELOC values | |
2977 | possible in instruction fixups. As is, it handles all | |
2978 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
fe49679d | 2979 | bfd/coff-rs6000.c and bfd/coff64-rs6000.c. |
0e2779e9 AM |
2980 | Overkill since data and marker relocs need not be handled |
2981 | here, but this way we can be sure a needed fixup reloc isn't | |
2982 | accidentally omitted. */ | |
2983 | case BFD_RELOC_PPC_EMB_MRKREF: | |
2984 | case BFD_RELOC_VTABLE_ENTRY: | |
2985 | case BFD_RELOC_VTABLE_INHERIT: | |
2986 | break; | |
2987 | ||
2988 | case BFD_RELOC_8: | |
2989 | size = 1; | |
2990 | break; | |
2991 | ||
2992 | case BFD_RELOC_16: | |
2993 | case BFD_RELOC_16_BASEREL: | |
2994 | case BFD_RELOC_16_GOTOFF: | |
2995 | case BFD_RELOC_GPREL16: | |
2996 | case BFD_RELOC_HI16: | |
2997 | case BFD_RELOC_HI16_BASEREL: | |
2998 | case BFD_RELOC_HI16_GOTOFF: | |
2999 | case BFD_RELOC_HI16_PLTOFF: | |
3000 | case BFD_RELOC_HI16_S: | |
3001 | case BFD_RELOC_HI16_S_BASEREL: | |
3002 | case BFD_RELOC_HI16_S_GOTOFF: | |
3003 | case BFD_RELOC_HI16_S_PLTOFF: | |
3004 | case BFD_RELOC_LO16: | |
3005 | case BFD_RELOC_LO16_BASEREL: | |
3006 | case BFD_RELOC_LO16_GOTOFF: | |
3007 | case BFD_RELOC_LO16_PLTOFF: | |
3008 | case BFD_RELOC_PPC64_ADDR16_DS: | |
3009 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3010 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
3011 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
3012 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
3013 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
3014 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
3015 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
3016 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
3017 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
3018 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3019 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
3020 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
3021 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
3022 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
3023 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
3024 | case BFD_RELOC_PPC64_GOT16_DS: | |
3025 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
3026 | case BFD_RELOC_PPC64_HIGHER: | |
3027 | case BFD_RELOC_PPC64_HIGHER_S: | |
3028 | case BFD_RELOC_PPC64_HIGHEST: | |
3029 | case BFD_RELOC_PPC64_HIGHEST_S: | |
3030 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
3031 | case BFD_RELOC_PPC64_PLTGOT16: | |
3032 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
3033 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
3034 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
3035 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
3036 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
3037 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
3038 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
3039 | case BFD_RELOC_PPC64_TOC16_DS: | |
3040 | case BFD_RELOC_PPC64_TOC16_HA: | |
3041 | case BFD_RELOC_PPC64_TOC16_HI: | |
3042 | case BFD_RELOC_PPC64_TOC16_LO: | |
3043 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
3044 | case BFD_RELOC_PPC64_TPREL16_DS: | |
3045 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
3046 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3047 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
3048 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
3049 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
3050 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
3051 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
3052 | #ifdef OBJ_XCOFF | |
3053 | case BFD_RELOC_PPC_BA16: | |
3054 | #endif | |
3055 | case BFD_RELOC_PPC_DTPREL16: | |
3056 | case BFD_RELOC_PPC_DTPREL16_HA: | |
3057 | case BFD_RELOC_PPC_DTPREL16_HI: | |
3058 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3059 | case BFD_RELOC_PPC_EMB_NADDR16: | |
3060 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
3061 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
3062 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
3063 | case BFD_RELOC_PPC_EMB_RELSDA: | |
3064 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
3065 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
3066 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
3067 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
3068 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
3069 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
3070 | case BFD_RELOC_PPC_EMB_SDAI16: | |
3071 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3072 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
3073 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
3074 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3075 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
3076 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
3077 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
3078 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
3079 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
3080 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
3081 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
3082 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
3083 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3084 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
3085 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
3086 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3087 | case BFD_RELOC_PPC_TOC16: | |
4a403be0 CC |
3088 | case BFD_RELOC_PPC_TOC16_HI: |
3089 | case BFD_RELOC_PPC_TOC16_LO: | |
0e2779e9 AM |
3090 | case BFD_RELOC_PPC_TPREL16: |
3091 | case BFD_RELOC_PPC_TPREL16_HA: | |
3092 | case BFD_RELOC_PPC_TPREL16_HI: | |
3093 | case BFD_RELOC_PPC_TPREL16_LO: | |
3094 | size = 2; | |
3095 | break; | |
3096 | ||
3097 | case BFD_RELOC_16_PCREL: | |
3098 | case BFD_RELOC_HI16_PCREL: | |
3099 | case BFD_RELOC_HI16_S_PCREL: | |
3100 | case BFD_RELOC_LO16_PCREL: | |
3101 | case BFD_RELOC_PPC64_REL16_HIGH: | |
3102 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
3103 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 3104 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 3105 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 3106 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 3107 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 3108 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 3109 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 3110 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
3111 | #ifdef OBJ_XCOFF |
3112 | case BFD_RELOC_PPC_B16: | |
3113 | #endif | |
3114 | case BFD_RELOC_PPC_VLE_REL8: | |
3115 | size = 2; | |
5b7c81bd | 3116 | pcrel = true; |
0e2779e9 AM |
3117 | break; |
3118 | ||
0e2779e9 | 3119 | case BFD_RELOC_32: |
0e2779e9 AM |
3120 | case BFD_RELOC_32_PLTOFF: |
3121 | #ifdef OBJ_XCOFF | |
3122 | case BFD_RELOC_CTOR: | |
3123 | #endif | |
3124 | case BFD_RELOC_PPC64_ENTRY: | |
3125 | case BFD_RELOC_PPC_16DX_HA: | |
3126 | #ifndef OBJ_XCOFF | |
3127 | case BFD_RELOC_PPC_BA16: | |
3128 | #endif | |
3129 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
3130 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
3131 | case BFD_RELOC_PPC_BA26: | |
3132 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
3133 | case BFD_RELOC_PPC_EMB_NADDR32: | |
3134 | case BFD_RELOC_PPC_EMB_SDA21: | |
3135 | case BFD_RELOC_PPC_TLS: | |
3136 | case BFD_RELOC_PPC_TLSGD: | |
3137 | case BFD_RELOC_PPC_TLSLD: | |
1b2cb8e2 CC |
3138 | case BFD_RELOC_PPC_TLSLE: |
3139 | case BFD_RELOC_PPC_TLSIE: | |
3140 | case BFD_RELOC_PPC_TLSM: | |
3141 | case BFD_RELOC_PPC_TLSML: | |
0e2779e9 AM |
3142 | case BFD_RELOC_PPC_VLE_HA16A: |
3143 | case BFD_RELOC_PPC_VLE_HA16D: | |
3144 | case BFD_RELOC_PPC_VLE_HI16A: | |
3145 | case BFD_RELOC_PPC_VLE_HI16D: | |
3146 | case BFD_RELOC_PPC_VLE_LO16A: | |
3147 | case BFD_RELOC_PPC_VLE_LO16D: | |
3148 | case BFD_RELOC_PPC_VLE_SDA21: | |
3149 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
3150 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3151 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
3152 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3153 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
3154 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3155 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 3156 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
3157 | case BFD_RELOC_RVA: |
3158 | size = 4; | |
3159 | break; | |
3160 | ||
3161 | case BFD_RELOC_24_PLT_PCREL: | |
3162 | case BFD_RELOC_32_PCREL: | |
3163 | case BFD_RELOC_32_PLT_PCREL: | |
3164 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
7aba54da | 3165 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
0e2779e9 AM |
3166 | #ifndef OBJ_XCOFF |
3167 | case BFD_RELOC_PPC_B16: | |
3168 | #endif | |
3169 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3170 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3171 | case BFD_RELOC_PPC_B26: | |
3172 | case BFD_RELOC_PPC_LOCAL24PC: | |
3173 | case BFD_RELOC_PPC_REL16DX_HA: | |
3174 | case BFD_RELOC_PPC_VLE_REL15: | |
3175 | case BFD_RELOC_PPC_VLE_REL24: | |
3176 | size = 4; | |
5b7c81bd | 3177 | pcrel = true; |
0e2779e9 AM |
3178 | break; |
3179 | ||
3180 | #ifndef OBJ_XCOFF | |
3181 | case BFD_RELOC_CTOR: | |
3182 | #endif | |
3183 | case BFD_RELOC_PPC_COPY: | |
3184 | case BFD_RELOC_PPC_DTPMOD: | |
3185 | case BFD_RELOC_PPC_DTPREL: | |
3186 | case BFD_RELOC_PPC_GLOB_DAT: | |
3187 | case BFD_RELOC_PPC_TPREL: | |
3188 | size = ppc_obj64 ? 8 : 4; | |
3189 | break; | |
3190 | ||
3191 | case BFD_RELOC_64: | |
3192 | case BFD_RELOC_64_PLTOFF: | |
3193 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3194 | case BFD_RELOC_PPC64_D28: |
3195 | case BFD_RELOC_PPC64_D34: | |
3196 | case BFD_RELOC_PPC64_D34_LO: | |
3197 | case BFD_RELOC_PPC64_D34_HI30: | |
3198 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3199 | case BFD_RELOC_PPC64_TPREL34: |
3200 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 | 3201 | case BFD_RELOC_PPC64_TOC: |
1b2cb8e2 CC |
3202 | case BFD_RELOC_PPC64_TLSGD: |
3203 | case BFD_RELOC_PPC64_TLSLD: | |
3204 | case BFD_RELOC_PPC64_TLSLE: | |
3205 | case BFD_RELOC_PPC64_TLSIE: | |
3206 | case BFD_RELOC_PPC64_TLSM: | |
3207 | case BFD_RELOC_PPC64_TLSML: | |
0e2779e9 AM |
3208 | size = 8; |
3209 | break; | |
3210 | ||
3211 | case BFD_RELOC_64_PCREL: | |
3212 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3213 | case BFD_RELOC_PPC64_GOT_PCREL34: |
87c69f97 AM |
3214 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3215 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3216 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3217 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 AM |
3218 | case BFD_RELOC_PPC64_PCREL28: |
3219 | case BFD_RELOC_PPC64_PCREL34: | |
3220 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 | 3221 | size = 8; |
5b7c81bd | 3222 | pcrel = true; |
0e2779e9 AM |
3223 | break; |
3224 | ||
3225 | default: | |
3226 | abort (); | |
3227 | } | |
3228 | ||
3229 | if (ENABLE_CHECKING) | |
3230 | { | |
3231 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3232 | if (reloc_howto != NULL | |
3233 | && (size != bfd_get_reloc_size (reloc_howto) | |
3234 | || pcrel != reloc_howto->pc_relative)) | |
3235 | { | |
3236 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3237 | reloc_howto->name); | |
3238 | abort (); | |
3239 | } | |
3240 | } | |
3241 | *pc_relative = pcrel; | |
3242 | return size; | |
3243 | } | |
3244 | ||
a894d76a | 3245 | #ifdef OBJ_ELF |
160eba93 AM |
3246 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3247 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3248 | is successfully parsed, *STR is updated past the trailing | |
3249 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3250 | reloc and arg expression. */ | |
3251 | ||
3252 | static int | |
3253 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3254 | { | |
3255 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3256 | if (sym_name[0] == '.') | |
3257 | ++sym_name; | |
3258 | ||
3259 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3260 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3261 | && (sym_name[14] == 0 | |
3262 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3263 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3264 | { |
3265 | char *hold = input_line_pointer; | |
3266 | input_line_pointer = *str + 1; | |
3267 | expression (&tls_fix->exp); | |
3268 | if (tls_fix->exp.X_op == O_symbol) | |
3269 | { | |
3270 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3271 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3272 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3273 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3274 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3275 | { | |
3276 | input_line_pointer += 7; | |
3277 | SKIP_WHITESPACE (); | |
3278 | *str = input_line_pointer; | |
3279 | } | |
3280 | } | |
3281 | input_line_pointer = hold; | |
3282 | } | |
3283 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3284 | } | |
a894d76a | 3285 | #endif |
160eba93 | 3286 | |
252b5132 RH |
3287 | /* This routine is called for each instruction to be assembled. */ |
3288 | ||
3289 | void | |
98027b10 | 3290 | md_assemble (char *str) |
252b5132 RH |
3291 | { |
3292 | char *s; | |
3293 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3294 | uint64_t insn; |
8e5eb8e1 | 3295 | const ppc_opindex_t *opindex_ptr; |
252b5132 RH |
3296 | int need_paren; |
3297 | int next_opindex; | |
3298 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3299 | int fc; | |
3300 | char *f; | |
a9479dc0 | 3301 | int addr_mask; |
252b5132 | 3302 | int i; |
b9c361e0 | 3303 | unsigned int insn_length; |
252b5132 RH |
3304 | |
3305 | /* Get the opcode. */ | |
3882b010 | 3306 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3307 | ; |
3308 | if (*s != '\0') | |
3309 | *s++ = '\0'; | |
3310 | ||
3311 | /* Look up the opcode in the hash table. */ | |
629310ab | 3312 | opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str); |
252b5132 RH |
3313 | if (opcode == (const struct powerpc_opcode *) NULL) |
3314 | { | |
dc3ff926 | 3315 | as_bad (_("unrecognized opcode: `%s'"), str); |
dd7efa79 | 3316 | ppc_clear_labels (); |
252b5132 RH |
3317 | return; |
3318 | } | |
3319 | ||
3320 | insn = opcode->opcode; | |
86c0f617 AM |
3321 | if (!target_big_endian |
3322 | && ((insn & ~(1 << 26)) == 46u << 26 | |
3323 | || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1))) | |
3324 | { | |
3325 | /* lmw, stmw, lswi, lswx, stswi, stswx */ | |
3326 | as_bad (_("`%s' invalid when little-endian"), str); | |
3327 | ppc_clear_labels (); | |
3328 | return; | |
3329 | } | |
252b5132 RH |
3330 | |
3331 | str = s; | |
3882b010 | 3332 | while (ISSPACE (*str)) |
252b5132 RH |
3333 | ++str; |
3334 | ||
4a403be0 CC |
3335 | #ifdef OBJ_XCOFF |
3336 | /* AIX often generates addis instructions using "addis RT, D(RA)" | |
3337 | format instead of the classic "addis RT, RA, SI" one. | |
3338 | Restore it to the default format as it's the one encoded | |
3339 | in ppc opcodes. */ | |
3340 | if (!strcmp (opcode->name, "addis")) | |
3341 | { | |
3342 | char *rt_e = strchr (str, ','); | |
3343 | if (rt_e != NULL | |
3344 | && strchr (rt_e + 1, ',') == NULL) | |
3345 | { | |
3346 | char *d_e = strchr (rt_e + 1, '('); | |
3347 | if (d_e != NULL && d_e != rt_e + 1) | |
3348 | { | |
3349 | char *ra_e = strrchr (d_e + 1, ')'); | |
3350 | if (ra_e != NULL && ra_e != d_e + 1) | |
3351 | ppc_xcoff_fixup_addis (rt_e, d_e, ra_e); | |
3352 | } | |
3353 | } | |
3354 | } | |
3355 | #endif | |
3356 | ||
252b5132 | 3357 | /* PowerPC operands are just expressions. The only real issue is |
9cf7e568 AM |
3358 | that a few operand types are optional. If an instruction has |
3359 | multiple optional operands and one is omitted, then all optional | |
3360 | operands past the first omitted one must also be omitted. */ | |
3361 | int num_optional_operands = 0; | |
3362 | int num_optional_provided = 0; | |
252b5132 RH |
3363 | |
3364 | /* Gather the operands. */ | |
3365 | need_paren = 0; | |
3366 | next_opindex = 0; | |
3367 | fc = 0; | |
3368 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3369 | { | |
3370 | const struct powerpc_operand *operand; | |
3371 | const char *errmsg; | |
3372 | char *hold; | |
3373 | expressionS ex; | |
3374 | char endc; | |
3375 | ||
3376 | if (next_opindex == 0) | |
3377 | operand = &powerpc_operands[*opindex_ptr]; | |
3378 | else | |
3379 | { | |
3380 | operand = &powerpc_operands[next_opindex]; | |
3381 | next_opindex = 0; | |
3382 | } | |
252b5132 RH |
3383 | errmsg = NULL; |
3384 | ||
252b5132 | 3385 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3386 | insert the default value, usually a zero. */ |
252b5132 | 3387 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3388 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3389 | { |
9cf7e568 AM |
3390 | if (num_optional_operands == 0) |
3391 | { | |
8e5eb8e1 | 3392 | const ppc_opindex_t *optr; |
9cf7e568 AM |
3393 | int total = 0; |
3394 | int provided = 0; | |
3395 | int omitted; | |
3396 | ||
3397 | s = str; | |
3398 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3399 | { | |
3400 | const struct powerpc_operand *op; | |
3401 | op = &powerpc_operands[*optr]; | |
3402 | ||
3403 | ++total; | |
3404 | ||
3405 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3406 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3407 | && ppc_obj64)) | |
3408 | ++num_optional_operands; | |
3409 | ||
3410 | if (s != NULL && *s != '\0') | |
3411 | { | |
3412 | ++provided; | |
3413 | ||
3414 | /* Look for the start of the next operand. */ | |
3415 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3416 | s = strpbrk (s, "(,"); | |
3417 | else | |
3418 | s = strchr (s, ','); | |
3419 | ||
3420 | if (s != NULL) | |
3421 | ++s; | |
3422 | } | |
3423 | } | |
3424 | omitted = total - provided; | |
3425 | num_optional_provided = num_optional_operands - omitted; | |
3426 | } | |
3427 | if (--num_optional_provided < 0) | |
252b5132 | 3428 | { |
32d71569 AM |
3429 | uint64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3430 | num_optional_provided); | |
9cf7e568 AM |
3431 | if (operand->insert) |
3432 | { | |
3433 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3434 | if (errmsg != (const char *) NULL) | |
3435 | as_bad ("%s", errmsg); | |
3436 | } | |
3437 | else if (operand->shift >= 0) | |
3438 | insn |= (val & operand->bitm) << operand->shift; | |
3439 | else | |
3440 | insn |= (val & operand->bitm) >> -operand->shift; | |
3441 | ||
3442 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3443 | next_opindex = *opindex_ptr + 1; | |
3444 | continue; | |
252b5132 | 3445 | } |
252b5132 RH |
3446 | } |
3447 | ||
3448 | /* Gather the operand. */ | |
3449 | hold = input_line_pointer; | |
3450 | input_line_pointer = str; | |
00b37cc4 AM |
3451 | cr_operand = ((operand->flags & PPC_OPERAND_CR_BIT) != 0 |
3452 | || (operand->flags & PPC_OPERAND_CR_REG) != 0); | |
3453 | expression (&ex); | |
3454 | cr_operand = false; | |
252b5132 RH |
3455 | str = input_line_pointer; |
3456 | input_line_pointer = hold; | |
3457 | ||
3458 | if (ex.X_op == O_illegal) | |
3459 | as_bad (_("illegal operand")); | |
3460 | else if (ex.X_op == O_absent) | |
3461 | as_bad (_("missing operand")); | |
3462 | else if (ex.X_op == O_register) | |
3463 | { | |
7e0de605 AM |
3464 | if ((ex.X_md |
3465 | & ~operand->flags | |
3466 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3467 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3468 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3469 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3470 | && ex.X_add_number != 0 | |
3471 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3472 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3473 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3474 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3475 | } |
32d71569 AM |
3476 | else if (ex.X_op == O_constant |
3477 | || (ex.X_op == O_big && ex.X_add_number > 0)) | |
252b5132 | 3478 | { |
32d71569 AM |
3479 | uint64_t val; |
3480 | if (ex.X_op == O_constant) | |
3481 | { | |
3482 | val = ex.X_add_number; | |
3483 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3484 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3485 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3486 | } | |
3487 | else | |
3488 | val = generic_bignum_to_int64 (); | |
252b5132 | 3489 | #ifdef OBJ_ELF |
81d4177b | 3490 | /* Allow @HA, @L, @H on constants. */ |
252b5132 | 3491 | char *orig_str = str; |
32d71569 | 3492 | bfd_reloc_code_real_type reloc = ppc_elf_suffix (&str, &ex); |
252b5132 | 3493 | |
32d71569 AM |
3494 | if (ex.X_op == O_constant) |
3495 | { | |
3496 | val = ex.X_add_number; | |
3497 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3498 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3499 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3500 | } | |
3501 | if (reloc != BFD_RELOC_NONE) | |
252b5132 RH |
3502 | switch (reloc) |
3503 | { | |
3504 | default: | |
3505 | str = orig_str; | |
3506 | break; | |
3507 | ||
3508 | case BFD_RELOC_LO16: | |
32d71569 | 3509 | val &= 0xffff; |
f9c6b907 | 3510 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3511 | val = SEX16 (val); |
252b5132 RH |
3512 | break; |
3513 | ||
3514 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3515 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3516 | { | |
3517 | /* PowerPC64 @h is tested for overflow. */ | |
32d71569 | 3518 | val = val >> 16; |
f9c6b907 AM |
3519 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3520 | { | |
32d71569 AM |
3521 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3522 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3523 | } |
3524 | break; | |
3525 | } | |
2b0f3761 | 3526 | /* Fallthru */ |
f9c6b907 AM |
3527 | |
3528 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
32d71569 | 3529 | val = PPC_HI (val); |
f9c6b907 | 3530 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3531 | val = SEX16 (val); |
252b5132 RH |
3532 | break; |
3533 | ||
3534 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3535 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3536 | { | |
3537 | /* PowerPC64 @ha is tested for overflow. */ | |
32d71569 | 3538 | val = (val + 0x8000) >> 16; |
f9c6b907 AM |
3539 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3540 | { | |
32d71569 AM |
3541 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3542 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3543 | } |
3544 | break; | |
3545 | } | |
2b0f3761 | 3546 | /* Fallthru */ |
f9c6b907 AM |
3547 | |
3548 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
32d71569 | 3549 | val = PPC_HA (val); |
f9c6b907 | 3550 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3551 | val = SEX16 (val); |
0baf16f2 AM |
3552 | break; |
3553 | ||
0baf16f2 | 3554 | case BFD_RELOC_PPC64_HIGHER: |
32d71569 | 3555 | val = PPC_HIGHER (val); |
f9c6b907 | 3556 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3557 | val = SEX16 (val); |
0baf16f2 AM |
3558 | break; |
3559 | ||
3560 | case BFD_RELOC_PPC64_HIGHER_S: | |
32d71569 | 3561 | val = PPC_HIGHERA (val); |
f9c6b907 | 3562 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3563 | val = SEX16 (val); |
252b5132 | 3564 | break; |
0baf16f2 AM |
3565 | |
3566 | case BFD_RELOC_PPC64_HIGHEST: | |
32d71569 | 3567 | val = PPC_HIGHEST (val); |
f9c6b907 | 3568 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3569 | val = SEX16 (val); |
0baf16f2 AM |
3570 | break; |
3571 | ||
3572 | case BFD_RELOC_PPC64_HIGHEST_S: | |
32d71569 | 3573 | val = PPC_HIGHESTA (val); |
f9c6b907 | 3574 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3575 | val = SEX16 (val); |
0baf16f2 | 3576 | break; |
252b5132 | 3577 | } |
0baf16f2 | 3578 | #endif /* OBJ_ELF */ |
32d71569 | 3579 | insn = ppc_insert_operand (insn, operand, val, ppc_cpu, NULL, 0); |
252b5132 | 3580 | } |
727fc41e | 3581 | else |
252b5132 | 3582 | { |
62ebcb5c | 3583 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3584 | #ifdef OBJ_ELF |
160eba93 AM |
3585 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3586 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3587 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3588 | { |
160eba93 AM |
3589 | fixups[fc].opindex = *opindex_ptr; |
3590 | ++fc; | |
252b5132 RH |
3591 | } |
3592 | ||
62ebcb5c | 3593 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3594 | { |
b9c361e0 JL |
3595 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3596 | if (opcode->flags & PPC_OPCODE_VLE) | |
3597 | { | |
0f873fd5 | 3598 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3599 | |
08dc996f | 3600 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3601 | || tmp_insn == E_AND2I_DOT_INSN |
3602 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3603 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3604 | || tmp_insn == E_LIS_INSN |
3605 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3606 | ||
3607 | ||
08dc996f | 3608 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3609 | || tmp_insn == E_ADD2IS_INSN |
3610 | || tmp_insn == E_CMP16I_INSN | |
3611 | || tmp_insn == E_MULL2I_INSN | |
3612 | || tmp_insn == E_CMPL16I_INSN | |
3613 | || tmp_insn == E_CMPH16I_INSN | |
3614 | || tmp_insn == E_CMPHL16I_INSN); | |
3615 | ||
3616 | switch (reloc) | |
3617 | { | |
3618 | default: | |
3619 | break; | |
3620 | ||
3621 | case BFD_RELOC_PPC_EMB_SDA21: | |
3622 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3623 | break; | |
3624 | ||
3625 | case BFD_RELOC_LO16: | |
3626 | if (use_d_reloc) | |
3627 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3628 | else if (use_a_reloc) | |
3629 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3630 | break; | |
3631 | ||
3632 | case BFD_RELOC_HI16: | |
3633 | if (use_d_reloc) | |
3634 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3635 | else if (use_a_reloc) | |
3636 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3637 | break; | |
3739860c | 3638 | |
b9c361e0 JL |
3639 | case BFD_RELOC_HI16_S: |
3640 | if (use_d_reloc) | |
3641 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3642 | else if (use_a_reloc) | |
3643 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3644 | break; | |
3645 | ||
3646 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3647 | if (use_d_reloc) | |
3648 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3649 | break; | |
3650 | ||
3651 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3652 | if (use_d_reloc) | |
3653 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3654 | break; | |
3655 | ||
3656 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3657 | if (use_d_reloc) | |
3658 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3659 | break; | |
3660 | } | |
3661 | } | |
bb6bf75e AM |
3662 | |
3663 | /* TLS and other tweaks. */ | |
3664 | switch (reloc) | |
3665 | { | |
3666 | default: | |
3667 | break; | |
3668 | ||
3669 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3670 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3671 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3672 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3673 | opcode->name); | |
3674 | else if (operand->shift != 11) | |
3675 | as_bad (_("@tls may only be used in last operand")); | |
3676 | else | |
3677 | insn = ppc_insert_operand (insn, operand, | |
3678 | ppc_obj64 ? 13 : 2, | |
3679 | ppc_cpu, (char *) NULL, 0); | |
3680 | break; | |
3681 | ||
3682 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3683 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3684 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3685 | if (operand->bitm == 0x3ffffffffULL) |
3686 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3687 | else | |
3688 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3689 | break; |
3690 | ||
3691 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3692 | if (operand->bitm == 0x3ffffffffULL) |
3693 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3694 | else | |
3695 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3696 | break; |
3697 | ||
5663e321 AM |
3698 | case BFD_RELOC_PPC64_PCREL34: |
3699 | if (operand->bitm == 0xfffffffULL) | |
3700 | { | |
3701 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3702 | break; | |
3703 | } | |
3704 | /* Fall through. */ | |
3705 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3706 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
87c69f97 AM |
3707 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3708 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3709 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3710 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 | 3711 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3712 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3713 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3714 | break; | |
3715 | ||
3716 | case BFD_RELOC_LO16: | |
3717 | if (operand->bitm == 0x3ffffffffULL | |
3718 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3719 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3720 | else if ((operand->bitm | 0xf) != 0xffff | |
3721 | || operand->shift != 0 | |
3722 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3723 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3724 | break; | |
3725 | ||
3726 | case BFD_RELOC_HI16: | |
5663e321 AM |
3727 | if (operand->bitm == 0x3ffffffffULL |
3728 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3729 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3730 | else if (operand->bitm != 0xffff | |
3731 | || operand->shift != 0 | |
3732 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3733 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3734 | break; | |
3735 | ||
3736 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3737 | if (operand->bitm == 0x3ffffffffULL |
3738 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3739 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3740 | else if (operand->bitm == 0xffff | |
3741 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3742 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3743 | /* addpcis. */ |
3744 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3745 | else if (operand->bitm != 0xffff | |
3746 | || operand->shift != 0 | |
3747 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3748 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3749 | } | |
0baf16f2 | 3750 | } |
3b8b57a9 | 3751 | #endif /* OBJ_ELF */ |
4a403be0 CC |
3752 | #ifdef OBJ_XCOFF |
3753 | reloc = ppc_xcoff_suffix (&str); | |
3754 | #endif /* OBJ_XCOFF */ | |
3b8b57a9 | 3755 | |
62ebcb5c | 3756 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3757 | ; |
3758 | /* Determine a BFD reloc value based on the operand information. | |
3759 | We are only prepared to turn a few of the operands into | |
3760 | relocs. */ | |
a0593ad9 AM |
3761 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3762 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3763 | && operand->bitm == 0x3fffffc |
3764 | && operand->shift == 0) | |
3765 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3766 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3767 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3768 | && operand->bitm == 0xfffc |
3769 | && operand->shift == 0) | |
3770 | reloc = BFD_RELOC_PPC_B16; | |
3771 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3772 | && operand->bitm == 0x1fe | |
3773 | && operand->shift == -1) | |
3774 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3775 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3776 | && operand->bitm == 0xfffe | |
3777 | && operand->shift == 0) | |
3778 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3779 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3780 | && operand->bitm == 0x1fffffe | |
3781 | && operand->shift == 0) | |
3782 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3783 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3784 | && (operand->bitm & 0xfff0) == 0xfff0 |
3785 | && operand->shift == 0) | |
3786 | { | |
f50c47f1 | 3787 | reloc = BFD_RELOC_16; |
3e60bf4d | 3788 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3789 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3790 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3791 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3792 | { |
3793 | reloc = BFD_RELOC_PPC_TOC16; | |
3794 | #ifdef OBJ_ELF | |
3795 | as_warn (_("assuming %s on symbol"), | |
3796 | ppc_obj64 ? "@toc" : "@xgot"); | |
3797 | #endif | |
3798 | } | |
3b8b57a9 | 3799 | #endif |
3b8b57a9 | 3800 | } |
5663e321 AM |
3801 | else if (operand->bitm == 0x3ffffffffULL) |
3802 | reloc = BFD_RELOC_PPC64_D34; | |
3803 | else if (operand->bitm == 0xfffffffULL) | |
3804 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3805 | |
3806 | /* For the absolute forms of branches, convert the PC | |
3807 | relative form back into the absolute. */ | |
3808 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3809 | { | |
3810 | switch (reloc) | |
3811 | { | |
3812 | case BFD_RELOC_PPC_B26: | |
3813 | reloc = BFD_RELOC_PPC_BA26; | |
3814 | break; | |
3815 | case BFD_RELOC_PPC_B16: | |
3816 | reloc = BFD_RELOC_PPC_BA16; | |
3817 | break; | |
3818 | #ifdef OBJ_ELF | |
3819 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3820 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3821 | break; | |
3822 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3823 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3824 | break; | |
3825 | #endif | |
3826 | default: | |
3827 | break; | |
3828 | } | |
3829 | } | |
3830 | ||
3831 | #ifdef OBJ_ELF | |
3832 | switch (reloc) | |
3833 | { | |
3834 | case BFD_RELOC_PPC_TOC16: | |
3835 | toc_reloc_types |= has_small_toc_reloc; | |
3836 | break; | |
3837 | case BFD_RELOC_PPC64_TOC16_LO: | |
3838 | case BFD_RELOC_PPC64_TOC16_HI: | |
3839 | case BFD_RELOC_PPC64_TOC16_HA: | |
3840 | toc_reloc_types |= has_large_toc_reloc; | |
3841 | break; | |
3842 | default: | |
3843 | break; | |
3844 | } | |
3845 | ||
3846 | if (ppc_obj64 | |
3847 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3848 | { | |
3849 | switch (reloc) | |
3850 | { | |
3851 | case BFD_RELOC_16: | |
3852 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3853 | break; | |
5663e321 | 3854 | |
a0593ad9 AM |
3855 | case BFD_RELOC_LO16: |
3856 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3857 | break; | |
5663e321 | 3858 | |
a0593ad9 AM |
3859 | case BFD_RELOC_16_GOTOFF: |
3860 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3861 | break; | |
5663e321 | 3862 | |
a0593ad9 AM |
3863 | case BFD_RELOC_LO16_GOTOFF: |
3864 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3865 | break; | |
5663e321 | 3866 | |
a0593ad9 AM |
3867 | case BFD_RELOC_LO16_PLTOFF: |
3868 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3869 | break; | |
5663e321 | 3870 | |
a0593ad9 AM |
3871 | case BFD_RELOC_16_BASEREL: |
3872 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3873 | break; | |
5663e321 | 3874 | |
a0593ad9 AM |
3875 | case BFD_RELOC_LO16_BASEREL: |
3876 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3877 | break; | |
5663e321 | 3878 | |
a0593ad9 AM |
3879 | case BFD_RELOC_PPC_TOC16: |
3880 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3881 | break; | |
5663e321 | 3882 | |
a0593ad9 AM |
3883 | case BFD_RELOC_PPC64_TOC16_LO: |
3884 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3885 | break; | |
5663e321 | 3886 | |
a0593ad9 AM |
3887 | case BFD_RELOC_PPC64_PLTGOT16: |
3888 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3889 | break; | |
5663e321 | 3890 | |
a0593ad9 AM |
3891 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3892 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3893 | break; | |
5663e321 | 3894 | |
a0593ad9 AM |
3895 | case BFD_RELOC_PPC_DTPREL16: |
3896 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3897 | break; | |
5663e321 | 3898 | |
a0593ad9 AM |
3899 | case BFD_RELOC_PPC_DTPREL16_LO: |
3900 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3901 | break; | |
5663e321 | 3902 | |
a0593ad9 AM |
3903 | case BFD_RELOC_PPC_TPREL16: |
3904 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
3905 | break; | |
5663e321 | 3906 | |
a0593ad9 AM |
3907 | case BFD_RELOC_PPC_TPREL16_LO: |
3908 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
3909 | break; | |
5663e321 | 3910 | |
a0593ad9 AM |
3911 | case BFD_RELOC_PPC_GOT_DTPREL16: |
3912 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3913 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3914 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3915 | break; | |
5663e321 | 3916 | |
a0593ad9 AM |
3917 | default: |
3918 | as_bad (_("unsupported relocation for DS offset field")); | |
3919 | break; | |
3920 | } | |
3921 | } | |
160eba93 AM |
3922 | |
3923 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
3924 | modifiers like @plt. This fixup must be emitted before | |
3925 | the usual call fixup. */ | |
3926 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3927 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
3928 | { | |
3929 | fixups[fc].opindex = *opindex_ptr; | |
3930 | ++fc; | |
3931 | } | |
a0593ad9 | 3932 | #endif |
0baf16f2 | 3933 | |
252b5132 RH |
3934 | /* We need to generate a fixup for this expression. */ |
3935 | if (fc >= MAX_INSN_FIXUPS) | |
3936 | as_fatal (_("too many fixups")); | |
3937 | fixups[fc].exp = ex; | |
727fc41e | 3938 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
3939 | fixups[fc].reloc = reloc; |
3940 | ++fc; | |
3941 | } | |
252b5132 RH |
3942 | |
3943 | if (need_paren) | |
3944 | { | |
3945 | endc = ')'; | |
3946 | need_paren = 0; | |
c3d65c1c BE |
3947 | /* If expecting more operands, then we want to see "),". */ |
3948 | if (*str == endc && opindex_ptr[1] != 0) | |
3949 | { | |
3950 | do | |
3951 | ++str; | |
3952 | while (ISSPACE (*str)); | |
3953 | endc = ','; | |
3954 | } | |
252b5132 RH |
3955 | } |
3956 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 3957 | endc = '('; |
252b5132 RH |
3958 | else |
3959 | endc = ','; | |
3960 | ||
3961 | /* The call to expression should have advanced str past any | |
3962 | whitespace. */ | |
9cf7e568 | 3963 | if (*str == endc) |
252b5132 | 3964 | { |
9cf7e568 AM |
3965 | ++str; |
3966 | if (endc == '(') | |
3967 | need_paren = 1; | |
3968 | } | |
3969 | else if (*str != '\0') | |
3970 | { | |
3971 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
3972 | break; | |
3973 | } | |
3974 | else if (endc == ')') | |
3975 | { | |
3976 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
3977 | break; |
3978 | } | |
252b5132 RH |
3979 | } |
3980 | ||
3882b010 | 3981 | while (ISSPACE (*str)) |
252b5132 RH |
3982 | ++str; |
3983 | ||
3984 | if (*str != '\0') | |
3985 | as_bad (_("junk at end of line: `%s'"), str); | |
3986 | ||
dc1d03fc | 3987 | #ifdef OBJ_ELF |
b9c361e0 | 3988 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
3989 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
3990 | && !ppc_obj64) | |
6a0c61b7 EZ |
3991 | { |
3992 | /* These are all version "1". */ | |
3993 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 3994 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 3995 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 3996 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 3997 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 3998 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 3999 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 4000 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 4001 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 4002 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 4003 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 4004 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 4005 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 4006 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
4007 | /* Only set the VLE flag if the instruction has been pulled via |
4008 | the VLE instruction set. This way the flag is guaranteed to | |
4009 | be set for VLE-only instructions or for VLE-only processors, | |
4010 | however it'll remain clear for dual-mode instructions on | |
4011 | dual-mode and, more importantly, standard-mode processors. */ | |
4012 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
4013 | { |
4014 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
4015 | if (elf_section_data (now_seg) != NULL) | |
4016 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
4017 | } | |
6a0c61b7 | 4018 | } |
dc1d03fc | 4019 | #endif |
6a0c61b7 | 4020 | |
252b5132 | 4021 | /* Write out the instruction. */ |
a9479dc0 AM |
4022 | |
4023 | addr_mask = 3; | |
f7d69005 | 4024 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
4025 | /* All instructions can start on a 2 byte boundary for VLE. */ |
4026 | addr_mask = 1; | |
4027 | ||
4028 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 4029 | { |
a9479dc0 AM |
4030 | /* Don't emit instructions to a frag started for data, or for a |
4031 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
4032 | and it's possible to start a new frag in the middle of | |
4033 | misaligned data. */ | |
4034 | frag_wane (frag_now); | |
4035 | frag_new (0); | |
b9c361e0 | 4036 | } |
a9479dc0 AM |
4037 | |
4038 | /* Check that insns within the frag are aligned. ppc_frag_check | |
4039 | will ensure that the frag start address is aligned. */ | |
4040 | if ((frag_now_fix () & addr_mask) != 0) | |
4041 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
4042 | ||
dd7efa79 | 4043 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
4044 | insn_length = 4; |
4045 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
4046 | insn_length = 2; | |
7c1f4227 | 4047 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
4048 | && PPC_PREFIX_P (insn)) |
4049 | { | |
4050 | struct insn_label_list *l; | |
4051 | ||
4052 | insn_length = 8; | |
4053 | ||
4054 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
4055 | boundaries. */ | |
4056 | frag_align_code (6, 4); | |
4057 | record_alignment (now_seg, 6); | |
1daf786b CC |
4058 | #ifdef OBJ_XCOFF |
4059 | /* Update alignment of the containing csect. */ | |
4060 | if (symbol_get_tc (ppc_current_csect)->align < 6) | |
4061 | symbol_get_tc (ppc_current_csect)->align = 6; | |
4062 | #endif | |
dd7efa79 PB |
4063 | |
4064 | /* Update "dot" in any expressions used by this instruction, and | |
4065 | a label attached to the instruction. By "attached" we mean | |
4066 | on the same source line as the instruction and without any | |
4067 | intervening semicolons. */ | |
4068 | dot_value = frag_now_fix (); | |
4069 | dot_frag = frag_now; | |
4070 | for (l = insn_labels; l != NULL; l = l->next) | |
4071 | { | |
4072 | symbol_set_frag (l->label, dot_frag); | |
4073 | S_SET_VALUE (l->label, dot_value); | |
4074 | } | |
4075 | } | |
4076 | ||
4077 | ppc_clear_labels (); | |
a9479dc0 | 4078 | |
b9c361e0 | 4079 | f = frag_more (insn_length); |
a9479dc0 | 4080 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
4081 | |
4082 | /* The prefix part of an 8-byte instruction always occupies the lower | |
4083 | addressed word in a doubleword, regardless of endianness. */ | |
15a32af5 AM |
4084 | if (insn_length == 8 |
4085 | && (sizeof (insn) > sizeof (valueT) || !target_big_endian)) | |
dd7efa79 PB |
4086 | { |
4087 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
4088 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
4089 | } | |
4090 | else | |
4091 | md_number_to_chars (f, insn, insn_length); | |
4092 | ||
bf7279d5 AM |
4093 | last_insn = insn; |
4094 | last_seg = now_seg; | |
4095 | last_subseg = now_subseg; | |
252b5132 | 4096 | |
5d6f4f16 | 4097 | #ifdef OBJ_ELF |
b9c361e0 | 4098 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
4099 | #endif |
4100 | ||
3b8b57a9 | 4101 | /* Create any fixups. */ |
252b5132 RH |
4102 | for (i = 0; i < fc; i++) |
4103 | { | |
3b8b57a9 | 4104 | fixS *fixP; |
62ebcb5c | 4105 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 4106 | { |
5b7c81bd | 4107 | bool pcrel; |
0e2779e9 AM |
4108 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); |
4109 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 4110 | |
99a814a1 AM |
4111 | fixP = fix_new_exp (frag_now, |
4112 | f - frag_now->fr_literal + offset, | |
4113 | size, | |
4114 | &fixups[i].exp, | |
0e2779e9 | 4115 | pcrel, |
252b5132 | 4116 | fixups[i].reloc); |
252b5132 RH |
4117 | } |
4118 | else | |
727fc41e AM |
4119 | { |
4120 | const struct powerpc_operand *operand; | |
4121 | ||
4122 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
4123 | fixP = fix_new_exp (frag_now, |
4124 | f - frag_now->fr_literal, | |
4125 | insn_length, | |
4126 | &fixups[i].exp, | |
4127 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 4128 | BFD_RELOC_NONE); |
727fc41e | 4129 | } |
3b8b57a9 | 4130 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
4131 | } |
4132 | } | |
252b5132 RH |
4133 | \f |
4134 | #ifdef OBJ_ELF | |
18ae9cc1 | 4135 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4136 | |
4137 | int | |
98027b10 | 4138 | ppc_section_type (char *str, size_t len) |
252b5132 | 4139 | { |
d34049e8 | 4140 | if (len == 7 && startswith (str, "ordered")) |
9de8d8f1 | 4141 | return SHT_ORDERED; |
252b5132 | 4142 | |
9de8d8f1 | 4143 | return -1; |
252b5132 RH |
4144 | } |
4145 | ||
4146 | int | |
1239de13 | 4147 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4148 | { |
4149 | if (type == SHT_ORDERED) | |
4150 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4151 | ||
252b5132 RH |
4152 | return flags; |
4153 | } | |
83eef883 AFB |
4154 | |
4155 | bfd_vma | |
4156 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4157 | { | |
4158 | if (letter == 'v') | |
4159 | return SHF_PPC_VLE; | |
4160 | ||
4161 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4162 | return -1; | |
4163 | } | |
252b5132 RH |
4164 | #endif /* OBJ_ELF */ |
4165 | ||
4166 | \f | |
4167 | /* Pseudo-op handling. */ | |
4168 | ||
4169 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4170 | pseudo-op, but it can also take a single ASCII string. */ | |
4171 | ||
4172 | static void | |
98027b10 | 4173 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4174 | { |
bf7279d5 AM |
4175 | int count = 0; |
4176 | ||
252b5132 RH |
4177 | if (*input_line_pointer != '\"') |
4178 | { | |
4179 | cons (1); | |
4180 | return; | |
4181 | } | |
4182 | ||
4183 | /* Gather characters. A real double quote is doubled. Unusual | |
4184 | characters are not permitted. */ | |
4185 | ++input_line_pointer; | |
4186 | while (1) | |
4187 | { | |
4188 | char c; | |
4189 | ||
4190 | c = *input_line_pointer++; | |
4191 | ||
4192 | if (c == '\"') | |
4193 | { | |
4194 | if (*input_line_pointer != '\"') | |
4195 | break; | |
4196 | ++input_line_pointer; | |
4197 | } | |
4198 | ||
4199 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4200 | ++count; |
252b5132 RH |
4201 | } |
4202 | ||
bf7279d5 AM |
4203 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4204 | as_warn (_("data in executable section")); | |
252b5132 RH |
4205 | demand_empty_rest_of_line (); |
4206 | } | |
4207 | \f | |
4208 | #ifdef OBJ_XCOFF | |
4209 | ||
4210 | /* XCOFF specific pseudo-op handling. */ | |
4211 | ||
4212 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4213 | to handle symbol suffixes for such symbols. */ | |
5b7c81bd | 4214 | static bool ppc_stab_symbol; |
252b5132 | 4215 | |
add588a8 CC |
4216 | /* Retrieve the visiblity input for pseudo-ops having ones. */ |
4217 | static unsigned short | |
4218 | ppc_xcoff_get_visibility (void) { | |
4219 | SKIP_WHITESPACE(); | |
4220 | ||
4221 | if (startswith (input_line_pointer, "exported")) | |
4222 | { | |
4223 | input_line_pointer += 8; | |
4224 | return SYM_V_EXPORTED; | |
4225 | } | |
4226 | ||
4227 | if (startswith (input_line_pointer, "hidden")) | |
4228 | { | |
4229 | input_line_pointer += 6; | |
4230 | return SYM_V_HIDDEN; | |
4231 | } | |
4232 | ||
4233 | if (startswith (input_line_pointer, "internal")) | |
4234 | { | |
4235 | input_line_pointer += 8; | |
4236 | return SYM_V_INTERNAL; | |
4237 | } | |
4238 | ||
4239 | if (startswith (input_line_pointer, "protected")) | |
4240 | { | |
4241 | input_line_pointer += 9; | |
4242 | return SYM_V_PROTECTED; | |
4243 | } | |
4244 | ||
4245 | return 0; | |
4246 | } | |
4247 | ||
09d4578f CC |
4248 | /* Retrieve visiblity using GNU syntax. */ |
4249 | static void ppc_GNU_visibility (int visibility) { | |
4250 | int c; | |
4251 | char *name; | |
4252 | symbolS *symbolP; | |
4253 | coff_symbol_type *coffsym; | |
4254 | ||
4255 | do | |
4256 | { | |
4257 | if ((name = read_symbol_name ()) == NULL) | |
4258 | break; | |
4259 | symbolP = symbol_find_or_make (name); | |
9f6e5897 | 4260 | free (name); |
09d4578f CC |
4261 | coffsym = coffsymbol (symbol_get_bfdsym (symbolP)); |
4262 | ||
4263 | coffsym->native->u.syment.n_type &= ~SYM_V_MASK; | |
4264 | coffsym->native->u.syment.n_type |= visibility; | |
4265 | ||
4266 | c = *input_line_pointer; | |
4267 | if (c == ',') | |
4268 | { | |
4269 | input_line_pointer ++; | |
4270 | ||
4271 | SKIP_WHITESPACE (); | |
4272 | ||
4273 | if (*input_line_pointer == '\n') | |
4274 | c = '\n'; | |
4275 | } | |
4276 | } | |
4277 | while (c == ','); | |
4278 | ||
4279 | demand_empty_rest_of_line (); | |
4280 | } | |
add588a8 | 4281 | |
252b5132 RH |
4282 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common |
4283 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4284 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1b2cb8e2 CC |
4285 | aligns .comm and .lcomm to 4 bytes. |
4286 | Symbols having a XMC_UL storage class are uninialized thread-local | |
4287 | data. */ | |
252b5132 RH |
4288 | |
4289 | static void | |
98027b10 | 4290 | ppc_comm (int lcomm) |
252b5132 RH |
4291 | { |
4292 | asection *current_seg = now_seg; | |
4293 | subsegT current_subseg = now_subseg; | |
4294 | char *name; | |
4295 | char endc; | |
4296 | char *end_name; | |
4297 | offsetT size; | |
4298 | offsetT align; | |
4299 | symbolS *lcomm_sym = NULL; | |
4300 | symbolS *sym; | |
4301 | char *pfrag; | |
1ffce3f8 | 4302 | unsigned short visibility = 0; |
1b2cb8e2 | 4303 | struct ppc_xcoff_section *section; |
252b5132 | 4304 | |
d02603dc | 4305 | endc = get_symbol_name (&name); |
252b5132 | 4306 | end_name = input_line_pointer; |
d02603dc | 4307 | (void) restore_line_pointer (endc); |
252b5132 RH |
4308 | |
4309 | if (*input_line_pointer != ',') | |
4310 | { | |
4311 | as_bad (_("missing size")); | |
4312 | ignore_rest_of_line (); | |
4313 | return; | |
4314 | } | |
4315 | ++input_line_pointer; | |
4316 | ||
4317 | size = get_absolute_expression (); | |
4318 | if (size < 0) | |
4319 | { | |
4320 | as_bad (_("negative size")); | |
4321 | ignore_rest_of_line (); | |
4322 | return; | |
4323 | } | |
4324 | ||
4325 | if (! lcomm) | |
4326 | { | |
4327 | /* The third argument to .comm is the alignment. */ | |
4328 | if (*input_line_pointer != ',') | |
1ad63b2f | 4329 | align = 2; |
252b5132 RH |
4330 | else |
4331 | { | |
4332 | ++input_line_pointer; | |
4333 | align = get_absolute_expression (); | |
4334 | if (align <= 0) | |
4335 | { | |
4336 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4337 | align = 2; |
252b5132 | 4338 | } |
add588a8 CC |
4339 | |
4340 | /* The fourth argument to .comm is the visibility. */ | |
4341 | if (*input_line_pointer == ',') | |
4342 | { | |
4343 | input_line_pointer++; | |
4344 | visibility = ppc_xcoff_get_visibility (); | |
4345 | if (!visibility) | |
4346 | { | |
4347 | as_bad (_("Unknown visibility field in .comm")); | |
4348 | ignore_rest_of_line (); | |
4349 | return; | |
4350 | } | |
4351 | } | |
252b5132 RH |
4352 | } |
4353 | } | |
4354 | else | |
4355 | { | |
4356 | char *lcomm_name; | |
4357 | char lcomm_endc; | |
4358 | ||
252b5132 RH |
4359 | /* The third argument to .lcomm appears to be the real local |
4360 | common symbol to create. References to the symbol named in | |
4361 | the first argument are turned into references to the third | |
4362 | argument. */ | |
4363 | if (*input_line_pointer != ',') | |
4364 | { | |
4365 | as_bad (_("missing real symbol name")); | |
4366 | ignore_rest_of_line (); | |
4367 | return; | |
4368 | } | |
4369 | ++input_line_pointer; | |
4370 | ||
d02603dc | 4371 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4372 | |
252b5132 RH |
4373 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4374 | ||
d02603dc | 4375 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4376 | |
4377 | /* The fourth argument to .lcomm is the alignment. */ | |
4378 | if (*input_line_pointer != ',') | |
4379 | { | |
4380 | if (size <= 4) | |
4381 | align = 2; | |
4382 | else | |
4383 | align = 3; | |
4384 | } | |
4385 | else | |
4386 | { | |
4387 | ++input_line_pointer; | |
4388 | align = get_absolute_expression (); | |
4389 | if (align <= 0) | |
4390 | { | |
4391 | as_warn (_("ignoring bad alignment")); | |
4392 | align = 2; | |
4393 | } | |
4394 | } | |
252b5132 RH |
4395 | } |
4396 | ||
4397 | *end_name = '\0'; | |
4398 | sym = symbol_find_or_make (name); | |
4399 | *end_name = endc; | |
4400 | ||
4401 | if (S_IS_DEFINED (sym) | |
4402 | || S_GET_VALUE (sym) != 0) | |
4403 | { | |
4404 | as_bad (_("attempt to redefine symbol")); | |
4405 | ignore_rest_of_line (); | |
4406 | return; | |
4407 | } | |
81d4177b | 4408 | |
1b2cb8e2 CC |
4409 | if (symbol_get_tc (sym)->symbol_class == XMC_UL |
4410 | || (lcomm && symbol_get_tc (lcomm_sym)->symbol_class == XMC_UL)) | |
4411 | { | |
4412 | section = &ppc_xcoff_tbss_section; | |
4413 | if (!ppc_xcoff_section_is_initialized (section)) | |
4414 | { | |
934cb849 | 4415 | ppc_init_xcoff_section (section, subseg_new (".tbss", 0)); |
1b2cb8e2 CC |
4416 | bfd_set_section_flags (section->segment, |
4417 | SEC_ALLOC | SEC_THREAD_LOCAL); | |
4418 | seg_info (section->segment)->bss = 1; | |
4419 | } | |
4420 | } | |
4421 | else | |
4422 | section = &ppc_xcoff_bss_section; | |
4423 | ||
4424 | record_alignment (section->segment, align); | |
81d4177b | 4425 | |
252b5132 RH |
4426 | if (! lcomm |
4427 | || ! S_IS_DEFINED (lcomm_sym)) | |
4428 | { | |
4429 | symbolS *def_sym; | |
4430 | offsetT def_size; | |
4431 | ||
4432 | if (! lcomm) | |
4433 | { | |
4434 | def_sym = sym; | |
4435 | def_size = size; | |
4436 | S_SET_EXTERNAL (sym); | |
4437 | } | |
4438 | else | |
4439 | { | |
809ffe0d | 4440 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4441 | def_sym = lcomm_sym; |
4442 | def_size = 0; | |
4443 | } | |
4444 | ||
1b2cb8e2 | 4445 | subseg_set (section->segment, 1); |
252b5132 | 4446 | frag_align (align, 0, 0); |
81d4177b | 4447 | |
809ffe0d | 4448 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4449 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4450 | def_size, (char *) NULL); | |
4451 | *pfrag = 0; | |
1b2cb8e2 | 4452 | S_SET_SEGMENT (def_sym, section->segment); |
809ffe0d | 4453 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4454 | } |
4455 | else if (lcomm) | |
4456 | { | |
4457 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4458 | symbol_get_frag (lcomm_sym)->fr_offset = |
4459 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4460 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4461 | if (align > symbol_get_tc (lcomm_sym)->align) |
4462 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4463 | } |
4464 | ||
4465 | if (lcomm) | |
4466 | { | |
4467 | /* Make sym an offset from lcomm_sym. */ | |
1b2cb8e2 | 4468 | S_SET_SEGMENT (sym, section->segment); |
809ffe0d ILT |
4469 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4470 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4471 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4472 | } |
4473 | ||
add588a8 CC |
4474 | if (!lcomm && visibility) |
4475 | { | |
4476 | /* Add visibility to .comm symbol. */ | |
4477 | coff_symbol_type *coffsym = coffsymbol (symbol_get_bfdsym (sym)); | |
4478 | coffsym->native->u.syment.n_type &= ~SYM_V_MASK; | |
4479 | coffsym->native->u.syment.n_type |= visibility; | |
4480 | } | |
4481 | ||
252b5132 RH |
4482 | subseg_set (current_seg, current_subseg); |
4483 | ||
4484 | demand_empty_rest_of_line (); | |
4485 | } | |
4486 | ||
4487 | /* The .csect pseudo-op. This switches us into a different | |
4488 | subsegment. The first argument is a symbol whose value is the | |
4489 | start of the .csect. In COFF, csect symbols get special aux | |
4490 | entries defined by the x_csect field of union internal_auxent. The | |
4491 | optional second argument is the alignment (the default is 2). */ | |
4492 | ||
4493 | static void | |
98027b10 | 4494 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4495 | { |
4496 | char *name; | |
4497 | char endc; | |
4498 | symbolS *sym; | |
931e13a6 | 4499 | offsetT align; |
252b5132 | 4500 | |
d02603dc | 4501 | endc = get_symbol_name (&name); |
81d4177b | 4502 | |
252b5132 RH |
4503 | sym = symbol_find_or_make (name); |
4504 | ||
d02603dc | 4505 | (void) restore_line_pointer (endc); |
252b5132 RH |
4506 | |
4507 | if (S_GET_NAME (sym)[0] == '\0') | |
4508 | { | |
4509 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4510 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4511 | } |
4512 | ||
931e13a6 | 4513 | align = 2; |
252b5132 RH |
4514 | if (*input_line_pointer == ',') |
4515 | { | |
4516 | ++input_line_pointer; | |
931e13a6 | 4517 | align = get_absolute_expression (); |
252b5132 RH |
4518 | } |
4519 | ||
931e13a6 AM |
4520 | ppc_change_csect (sym, align); |
4521 | ||
252b5132 RH |
4522 | demand_empty_rest_of_line (); |
4523 | } | |
4524 | ||
4525 | /* Change to a different csect. */ | |
4526 | ||
4527 | static void | |
98027b10 | 4528 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4529 | { |
4530 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4531 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4532 | else |
4533 | { | |
1b2cb8e2 | 4534 | struct ppc_xcoff_section *section; |
252b5132 RH |
4535 | int after_toc; |
4536 | int hold_chunksize; | |
4537 | symbolS *list; | |
931e13a6 AM |
4538 | int is_code; |
4539 | segT sec; | |
252b5132 RH |
4540 | |
4541 | /* This is a new csect. We need to look at the symbol class to | |
4542 | figure out whether it should go in the text section or the | |
4543 | data section. */ | |
4544 | after_toc = 0; | |
931e13a6 | 4545 | is_code = 0; |
96d56e9f | 4546 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4547 | { |
4548 | case XMC_PR: | |
4549 | case XMC_RO: | |
4550 | case XMC_DB: | |
4551 | case XMC_GL: | |
4552 | case XMC_XO: | |
4553 | case XMC_SV: | |
4554 | case XMC_TI: | |
4555 | case XMC_TB: | |
1b2cb8e2 | 4556 | section = &ppc_xcoff_text_section; |
931e13a6 | 4557 | is_code = 1; |
252b5132 RH |
4558 | break; |
4559 | case XMC_RW: | |
4560 | case XMC_TC0: | |
4561 | case XMC_TC: | |
4a403be0 | 4562 | case XMC_TE: |
252b5132 RH |
4563 | case XMC_DS: |
4564 | case XMC_UA: | |
252b5132 | 4565 | case XMC_UC: |
1b2cb8e2 | 4566 | section = &ppc_xcoff_data_section; |
252b5132 | 4567 | if (ppc_toc_csect != NULL |
809ffe0d | 4568 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
1b2cb8e2 | 4569 | == section->next_subsegment)) |
252b5132 | 4570 | after_toc = 1; |
1b2cb8e2 CC |
4571 | break; |
4572 | case XMC_BS: | |
4573 | section = &ppc_xcoff_bss_section; | |
4574 | break; | |
4575 | case XMC_TL: | |
4576 | section = &ppc_xcoff_tdata_section; | |
4577 | /* Create .tdata section if not yet done. */ | |
4578 | if (!ppc_xcoff_section_is_initialized (section)) | |
4579 | { | |
934cb849 | 4580 | ppc_init_xcoff_section (section, subseg_new (".tdata", 0)); |
1b2cb8e2 CC |
4581 | bfd_set_section_flags (section->segment, SEC_ALLOC |
4582 | | SEC_LOAD | SEC_RELOC | SEC_DATA | |
4583 | | SEC_THREAD_LOCAL); | |
4584 | } | |
4585 | break; | |
4586 | case XMC_UL: | |
4587 | section = &ppc_xcoff_tbss_section; | |
4588 | /* Create .tbss section if not yet done. */ | |
4589 | if (!ppc_xcoff_section_is_initialized (section)) | |
4590 | { | |
934cb849 | 4591 | ppc_init_xcoff_section (section, subseg_new (".tbss", 0)); |
1b2cb8e2 CC |
4592 | bfd_set_section_flags (section->segment, SEC_ALLOC | |
4593 | SEC_THREAD_LOCAL); | |
4594 | seg_info (section->segment)->bss = 1; | |
4595 | } | |
252b5132 RH |
4596 | break; |
4597 | default: | |
4598 | abort (); | |
4599 | } | |
4600 | ||
1b2cb8e2 CC |
4601 | S_SET_SEGMENT (sym, section->segment); |
4602 | symbol_get_tc (sym)->subseg = section->next_subsegment; | |
4603 | ++section->next_subsegment; | |
4604 | ||
252b5132 | 4605 | /* We set the obstack chunk size to a small value before |
99a814a1 AM |
4606 | changing subsegments, so that we don't use a lot of memory |
4607 | space for what may be a small section. */ | |
252b5132 RH |
4608 | hold_chunksize = chunksize; |
4609 | chunksize = 64; | |
4610 | ||
931e13a6 AM |
4611 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4612 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4613 | |
4614 | chunksize = hold_chunksize; | |
4615 | ||
4616 | if (after_toc) | |
4617 | ppc_after_toc_frag = frag_now; | |
4618 | ||
931e13a6 AM |
4619 | record_alignment (sec, align); |
4620 | if (is_code) | |
4621 | frag_align_code (align, 0); | |
4622 | else | |
4623 | frag_align (align, 0, 0); | |
4624 | ||
809ffe0d | 4625 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4626 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4627 | ||
931e13a6 | 4628 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4629 | symbol_get_tc (sym)->output = 1; |
4630 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4631 | |
1b2cb8e2 | 4632 | for (list = section->csects; |
809ffe0d ILT |
4633 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4634 | list = symbol_get_tc (list)->next) | |
252b5132 | 4635 | ; |
809ffe0d | 4636 | symbol_get_tc (list)->next = sym; |
81d4177b | 4637 | |
252b5132 | 4638 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4639 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4640 | &symbol_lastP); | |
252b5132 RH |
4641 | } |
4642 | ||
4643 | ppc_current_csect = sym; | |
4644 | } | |
4645 | ||
85645aed TG |
4646 | static void |
4647 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4648 | { | |
4649 | segT sec; | |
4650 | flagword oldflags; | |
4651 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4652 | ||
51d29b8c | 4653 | sec = subseg_new (dw->xcoff_name, subseg); |
fd361982 | 4654 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4655 | if (oldflags == SEC_NO_FLAGS) |
4656 | { | |
4657 | /* Just created section. */ | |
4658 | gas_assert (dw_sections[idx].sect == NULL); | |
4659 | ||
fd361982 AM |
4660 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4661 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4662 | dw_sections[idx].sect = sec; |
4663 | } | |
4664 | ||
4665 | /* Not anymore in a csect. */ | |
4666 | ppc_current_csect = NULL; | |
4667 | } | |
4668 | ||
4669 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4670 | .dwsect flag [, opt-label ] | |
4671 | */ | |
4672 | ||
4673 | static void | |
4674 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4675 | { | |
16de26a6 | 4676 | valueT flag; |
85645aed TG |
4677 | symbolS *opt_label; |
4678 | const struct xcoff_dwsect_name *dw; | |
4679 | struct dw_subsection *subseg; | |
4680 | struct dw_section *dws; | |
4681 | int i; | |
4682 | ||
4683 | /* Find section. */ | |
4684 | flag = get_absolute_expression (); | |
4685 | dw = NULL; | |
4686 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4687 | if (xcoff_dwsect_names[i].flag == flag) | |
4688 | { | |
4689 | dw = &xcoff_dwsect_names[i]; | |
4690 | break; | |
4691 | } | |
4692 | ||
4693 | /* Parse opt-label. */ | |
4694 | if (*input_line_pointer == ',') | |
4695 | { | |
d02603dc | 4696 | char *label; |
85645aed TG |
4697 | char c; |
4698 | ||
4699 | ++input_line_pointer; | |
4700 | ||
d02603dc | 4701 | c = get_symbol_name (&label); |
85645aed | 4702 | opt_label = symbol_find_or_make (label); |
d02603dc | 4703 | (void) restore_line_pointer (c); |
85645aed TG |
4704 | } |
4705 | else | |
4706 | opt_label = NULL; | |
4707 | ||
4708 | demand_empty_rest_of_line (); | |
4709 | ||
4710 | /* Return now in case of unknown subsection. */ | |
4711 | if (dw == NULL) | |
4712 | { | |
d6ed37ed | 4713 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4714 | (unsigned)flag); |
4715 | return; | |
4716 | } | |
4717 | ||
4718 | /* Find the subsection. */ | |
4719 | dws = &dw_sections[i]; | |
4720 | subseg = NULL; | |
4721 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4722 | { | |
4723 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4724 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4725 | { | |
4726 | as_bad (_("label %s was not defined in this dwarf section"), | |
4727 | S_GET_NAME (opt_label)); | |
4728 | subseg = dws->anon_subseg; | |
4729 | opt_label = NULL; | |
4730 | } | |
4731 | else | |
4732 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4733 | } | |
4734 | ||
4735 | if (subseg != NULL) | |
4736 | { | |
4737 | /* Switch to the subsection. */ | |
4738 | ppc_change_debug_section (i, subseg->subseg); | |
4739 | } | |
4740 | else | |
4741 | { | |
4742 | /* Create a new dw subsection. */ | |
f681e586 | 4743 | subseg = XCNEW (struct dw_subsection); |
85645aed TG |
4744 | |
4745 | if (opt_label == NULL) | |
4746 | { | |
4747 | /* The anonymous one. */ | |
4748 | subseg->subseg = 0; | |
4749 | subseg->link = NULL; | |
4750 | dws->anon_subseg = subseg; | |
4751 | } | |
4752 | else | |
4753 | { | |
4754 | /* A named one. */ | |
4755 | if (dws->list_subseg != NULL) | |
4756 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4757 | else | |
4758 | subseg->subseg = 1; | |
4759 | ||
4760 | subseg->link = dws->list_subseg; | |
4761 | dws->list_subseg = subseg; | |
4762 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4763 | } | |
4764 | ||
4765 | ppc_change_debug_section (i, subseg->subseg); | |
4766 | ||
4767 | if (dw->def_size) | |
4768 | { | |
4769 | /* Add the length field. */ | |
4770 | expressionS *exp = &subseg->end_exp; | |
4771 | int sz; | |
4772 | ||
4773 | if (opt_label != NULL) | |
4774 | symbol_set_value_now (opt_label); | |
4775 | ||
4776 | /* Add the length field. Note that according to the AIX assembler | |
4777 | manual, the size of the length field is 4 for powerpc32 but | |
4778 | 12 for powerpc64. */ | |
4779 | if (ppc_obj64) | |
4780 | { | |
4781 | /* Write the 64bit marker. */ | |
4782 | md_number_to_chars (frag_more (4), -1, 4); | |
4783 | } | |
4784 | ||
4785 | exp->X_op = O_subtract; | |
4786 | exp->X_op_symbol = symbol_temp_new_now (); | |
4787 | exp->X_add_symbol = symbol_temp_make (); | |
4788 | ||
4789 | sz = ppc_obj64 ? 8 : 4; | |
4790 | exp->X_add_number = -sz; | |
4791 | emit_expr (exp, sz); | |
4792 | } | |
4793 | } | |
4794 | } | |
4795 | ||
252b5132 RH |
4796 | /* This function handles the .text and .data pseudo-ops. These |
4797 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4798 | convenience of people who aren't used to XCOFF. */ | |
4799 | ||
4800 | static void | |
98027b10 | 4801 | ppc_section (int type) |
252b5132 RH |
4802 | { |
4803 | const char *name; | |
4804 | symbolS *sym; | |
4805 | ||
4806 | if (type == 't') | |
4807 | name = ".text[PR]"; | |
4808 | else if (type == 'd') | |
4809 | name = ".data[RW]"; | |
4810 | else | |
4811 | abort (); | |
4812 | ||
4813 | sym = symbol_find_or_make (name); | |
4814 | ||
931e13a6 | 4815 | ppc_change_csect (sym, 2); |
252b5132 RH |
4816 | |
4817 | demand_empty_rest_of_line (); | |
4818 | } | |
4819 | ||
4820 | /* This function handles the .section pseudo-op. This is mostly to | |
4821 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4822 | we do permit the user to name the text or data section. */ | |
4823 | ||
4824 | static void | |
98027b10 | 4825 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4826 | { |
4827 | char *user_name; | |
4828 | const char *real_name; | |
4829 | char c; | |
4830 | symbolS *sym; | |
4831 | ||
d02603dc | 4832 | c = get_symbol_name (&user_name); |
252b5132 RH |
4833 | |
4834 | if (strcmp (user_name, ".text") == 0) | |
4835 | real_name = ".text[PR]"; | |
4836 | else if (strcmp (user_name, ".data") == 0) | |
4837 | real_name = ".data[RW]"; | |
4838 | else | |
4839 | { | |
d6ed37ed | 4840 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4841 | (void) restore_line_pointer (c); |
252b5132 RH |
4842 | ignore_rest_of_line (); |
4843 | return; | |
4844 | } | |
4845 | ||
d02603dc | 4846 | (void) restore_line_pointer (c); |
252b5132 RH |
4847 | |
4848 | sym = symbol_find_or_make (real_name); | |
4849 | ||
931e13a6 | 4850 | ppc_change_csect (sym, 2); |
252b5132 RH |
4851 | |
4852 | demand_empty_rest_of_line (); | |
4853 | } | |
4854 | ||
4855 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4856 | ||
4857 | static void | |
98027b10 | 4858 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4859 | { |
4860 | char *name; | |
add588a8 | 4861 | symbolS *sym; |
252b5132 | 4862 | |
add588a8 CC |
4863 | if ((name = read_symbol_name ()) == NULL) |
4864 | return; | |
252b5132 | 4865 | |
add588a8 | 4866 | sym = symbol_find_or_make (name); |
9f6e5897 | 4867 | free (name); |
252b5132 | 4868 | |
add588a8 CC |
4869 | if (*input_line_pointer == ',') |
4870 | { | |
4871 | unsigned short visibility; | |
4872 | coff_symbol_type *coffsym = coffsymbol (symbol_get_bfdsym (sym)); | |
4873 | ||
4874 | input_line_pointer++; | |
4875 | visibility = ppc_xcoff_get_visibility (); | |
4876 | if (!visibility) | |
4877 | { | |
4878 | as_bad (_("Unknown visibility field in .extern")); | |
4879 | ignore_rest_of_line (); | |
4880 | return; | |
4881 | } | |
4882 | ||
4883 | coffsym->native->u.syment.n_type &= ~SYM_V_MASK; | |
4884 | coffsym->native->u.syment.n_type |= visibility; | |
4885 | } | |
4886 | ||
4887 | demand_empty_rest_of_line (); | |
4888 | } | |
4889 | ||
4890 | /* XCOFF semantic for .globl says that the second parameter is | |
4891 | the symbol visibility. */ | |
4892 | ||
4893 | static void | |
4894 | ppc_globl (int ignore ATTRIBUTE_UNUSED) | |
4895 | { | |
4896 | char *name; | |
4897 | symbolS *sym; | |
4898 | ||
4899 | if ((name = read_symbol_name ()) == NULL) | |
4900 | return; | |
4901 | ||
4902 | sym = symbol_find_or_make (name); | |
9f6e5897 | 4903 | free (name); |
add588a8 CC |
4904 | S_SET_EXTERNAL (sym); |
4905 | ||
4906 | if (*input_line_pointer == ',') | |
4907 | { | |
4908 | unsigned short visibility; | |
4909 | coff_symbol_type *coffsym = coffsymbol (symbol_get_bfdsym (sym)); | |
4910 | ||
4911 | input_line_pointer++; | |
4912 | visibility = ppc_xcoff_get_visibility (); | |
4913 | if (!visibility) | |
4914 | { | |
4915 | as_bad (_("Unknown visibility field in .globl")); | |
4916 | ignore_rest_of_line (); | |
4917 | return; | |
4918 | } | |
4919 | ||
4920 | coffsym->native->u.syment.n_type &= ~SYM_V_MASK; | |
4921 | coffsym->native->u.syment.n_type |= visibility; | |
4922 | } | |
4923 | ||
4924 | demand_empty_rest_of_line (); | |
4925 | } | |
4926 | ||
4927 | /* XCOFF semantic for .weak says that the second parameter is | |
4928 | the symbol visibility. */ | |
4929 | ||
4930 | static void | |
4931 | ppc_weak (int ignore ATTRIBUTE_UNUSED) | |
4932 | { | |
4933 | char *name; | |
4934 | symbolS *sym; | |
4935 | ||
4936 | if ((name = read_symbol_name ()) == NULL) | |
4937 | return; | |
4938 | ||
4939 | sym = symbol_find_or_make (name); | |
9f6e5897 | 4940 | free (name); |
add588a8 CC |
4941 | S_SET_WEAK (sym); |
4942 | ||
4943 | if (*input_line_pointer == ',') | |
4944 | { | |
4945 | unsigned short visibility; | |
4946 | coff_symbol_type *coffsym = coffsymbol (symbol_get_bfdsym (sym)); | |
4947 | ||
4948 | input_line_pointer++; | |
4949 | visibility = ppc_xcoff_get_visibility (); | |
4950 | if (!visibility) | |
4951 | { | |
4952 | as_bad (_("Unknown visibility field in .weak")); | |
4953 | ignore_rest_of_line (); | |
4954 | return; | |
4955 | } | |
4956 | ||
4957 | coffsym->native->u.syment.n_type &= ~SYM_V_MASK; | |
4958 | coffsym->native->u.syment.n_type |= visibility; | |
4959 | } | |
252b5132 RH |
4960 | |
4961 | demand_empty_rest_of_line (); | |
4962 | } | |
4963 | ||
4964 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4965 | ||
4966 | static void | |
98027b10 | 4967 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4968 | { |
4969 | char *name; | |
4970 | char endc; | |
4971 | symbolS *sym; | |
4972 | ||
d02603dc | 4973 | endc = get_symbol_name (&name); |
252b5132 RH |
4974 | |
4975 | sym = symbol_find_or_make (name); | |
4976 | ||
d02603dc | 4977 | (void) restore_line_pointer (endc); |
252b5132 | 4978 | |
809ffe0d | 4979 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4980 | |
4981 | demand_empty_rest_of_line (); | |
4982 | } | |
4983 | ||
c865e45b RS |
4984 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4985 | relocations at the beginning of the current csect. | |
4986 | ||
4987 | (In principle, there's no reason why the relocations _have_ to be at | |
4988 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4989 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4990 | deal with cases where the .ref statements follow the section contents.) |
4991 | ||
4992 | ??? .refs don't work for empty .csects. However, the native assembler | |
4993 | doesn't report an error in this case, and neither yet do we. */ | |
4994 | ||
4995 | static void | |
4996 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4997 | { | |
4998 | char *name; | |
4999 | char c; | |
5000 | ||
5001 | if (ppc_current_csect == NULL) | |
5002 | { | |
5003 | as_bad (_(".ref outside .csect")); | |
5004 | ignore_rest_of_line (); | |
5005 | return; | |
5006 | } | |
5007 | ||
5008 | do | |
5009 | { | |
d02603dc | 5010 | c = get_symbol_name (&name); |
c865e45b RS |
5011 | |
5012 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
5b7c81bd | 5013 | symbol_find_or_make (name), 0, false, BFD_RELOC_NONE); |
c865e45b RS |
5014 | |
5015 | *input_line_pointer = c; | |
d02603dc | 5016 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
5017 | c = *input_line_pointer; |
5018 | if (c == ',') | |
5019 | { | |
5020 | input_line_pointer++; | |
5021 | SKIP_WHITESPACE (); | |
5022 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
5023 | { | |
5024 | as_bad (_("missing symbol name")); | |
5025 | ignore_rest_of_line (); | |
5026 | return; | |
5027 | } | |
5028 | } | |
5029 | } | |
5030 | while (c == ','); | |
5031 | ||
5032 | demand_empty_rest_of_line (); | |
5033 | } | |
5034 | ||
252b5132 RH |
5035 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
5036 | although I don't know why it bothers. */ | |
5037 | ||
5038 | static void | |
98027b10 | 5039 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5040 | { |
5041 | char *name; | |
5042 | char endc; | |
5043 | symbolS *sym; | |
5044 | int len; | |
5045 | ||
d02603dc | 5046 | endc = get_symbol_name (&name); |
252b5132 RH |
5047 | |
5048 | sym = symbol_find_or_make (name); | |
5049 | ||
d02603dc | 5050 | (void) restore_line_pointer (endc); |
252b5132 RH |
5051 | |
5052 | if (*input_line_pointer != ',') | |
5053 | { | |
5054 | as_bad (_("missing rename string")); | |
5055 | ignore_rest_of_line (); | |
5056 | return; | |
5057 | } | |
5058 | ++input_line_pointer; | |
5059 | ||
809ffe0d | 5060 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
5061 | |
5062 | demand_empty_rest_of_line (); | |
5063 | } | |
5064 | ||
5065 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
5066 | pseudo-op, but slightly different. A sample is | |
5067 | .stabx "main:F-1",.main,142,0 | |
5068 | The first argument is the symbol name to create. The second is the | |
5069 | value, and the third is the storage class. The fourth seems to be | |
5070 | always zero, and I am assuming it is the type. */ | |
5071 | ||
5072 | static void | |
98027b10 | 5073 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5074 | { |
5075 | char *name; | |
5076 | int len; | |
5077 | symbolS *sym; | |
5078 | expressionS exp; | |
5079 | ||
5080 | name = demand_copy_C_string (&len); | |
5081 | ||
5082 | if (*input_line_pointer != ',') | |
5083 | { | |
5084 | as_bad (_("missing value")); | |
5085 | return; | |
5086 | } | |
5087 | ++input_line_pointer; | |
5088 | ||
5b7c81bd | 5089 | ppc_stab_symbol = true; |
252b5132 | 5090 | sym = symbol_make (name); |
5b7c81bd | 5091 | ppc_stab_symbol = false; |
252b5132 | 5092 | |
809ffe0d | 5093 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
5094 | |
5095 | (void) expression (&exp); | |
5096 | ||
5097 | switch (exp.X_op) | |
5098 | { | |
5099 | case O_illegal: | |
5100 | case O_absent: | |
5101 | case O_big: | |
5102 | as_bad (_("illegal .stabx expression; zero assumed")); | |
5103 | exp.X_add_number = 0; | |
5104 | /* Fall through. */ | |
5105 | case O_constant: | |
5106 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 5107 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
5108 | break; |
5109 | ||
5110 | case O_symbol: | |
5111 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 5112 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5113 | else |
5114 | { | |
5115 | S_SET_VALUE (sym, | |
5116 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 5117 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
5118 | } |
5119 | break; | |
5120 | ||
5121 | default: | |
5122 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
5123 | fail at some later point, but this is probably the right |
5124 | thing to do here. */ | |
809ffe0d | 5125 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5126 | break; |
5127 | } | |
5128 | ||
5129 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5130 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5131 | |
5132 | if (*input_line_pointer != ',') | |
5133 | { | |
5134 | as_bad (_("missing class")); | |
5135 | return; | |
5136 | } | |
5137 | ++input_line_pointer; | |
5138 | ||
5139 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
5140 | ||
5141 | if (*input_line_pointer != ',') | |
5142 | { | |
5143 | as_bad (_("missing type")); | |
5144 | return; | |
5145 | } | |
5146 | ++input_line_pointer; | |
5147 | ||
5148 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
5149 | ||
809ffe0d | 5150 | symbol_get_tc (sym)->output = 1; |
252b5132 | 5151 | |
c734e7e3 TG |
5152 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
5153 | { | |
5154 | /* In this case : | |
252b5132 | 5155 | |
c734e7e3 TG |
5156 | .bs name |
5157 | .stabx "z",arrays_,133,0 | |
5158 | .es | |
99a814a1 | 5159 | |
c734e7e3 | 5160 | .comm arrays_,13768,3 |
99a814a1 | 5161 | |
c734e7e3 TG |
5162 | resolve_symbol_value will copy the exp's "within" into sym's when the |
5163 | offset is 0. Since this seems to be corner case problem, | |
5164 | only do the correction for storage class C_STSYM. A better solution | |
5165 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 5166 | |
c734e7e3 TG |
5167 | if (exp.X_op == O_symbol) |
5168 | { | |
5169 | if (ppc_current_block == NULL) | |
5170 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 5171 | |
c734e7e3 | 5172 | symbol_get_tc (sym)->within = ppc_current_block; |
c734e7e3 TG |
5173 | } |
5174 | } | |
99a814a1 | 5175 | |
252b5132 RH |
5176 | if (exp.X_op != O_symbol |
5177 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
5178 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
5179 | ppc_frob_label (sym); | |
5180 | else | |
5181 | { | |
5182 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5183 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5184 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
5185 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
5186 | } |
5187 | ||
5188 | demand_empty_rest_of_line (); | |
5189 | } | |
5190 | ||
e86fc4a5 CC |
5191 | /* The .file pseudo-op. On XCOFF, .file can have several parameters |
5192 | which are being added to the symbol table to provide additional | |
5193 | information. */ | |
5194 | ||
5195 | static void | |
5196 | ppc_file (int ignore ATTRIBUTE_UNUSED) | |
5197 | { | |
5198 | char *sfname, *s1 = NULL, *s2 = NULL, *s3 = NULL; | |
5199 | int length, auxnb = 1; | |
5200 | ||
5201 | /* Some assemblers tolerate immediately following '"'. */ | |
5202 | if ((sfname = demand_copy_string (&length)) != 0) | |
5203 | { | |
5204 | coff_symbol_type *coffsym; | |
5205 | if (*input_line_pointer == ',') | |
5206 | { | |
5207 | ++input_line_pointer; | |
5208 | s1 = demand_copy_string (&length); | |
5209 | auxnb++; | |
5210 | ||
5211 | if (*input_line_pointer == ',') | |
5212 | { | |
5213 | ++input_line_pointer; | |
5214 | s2 = demand_copy_string (&length); | |
5215 | auxnb++; | |
5216 | ||
5217 | if (*input_line_pointer == ',') | |
5218 | { | |
5219 | ++input_line_pointer; | |
5220 | s3 = demand_copy_string (&length); | |
5221 | auxnb++; | |
5222 | } | |
5223 | } | |
5224 | } | |
5225 | ||
5226 | /* Use coff dot_file creation and adjust auxiliary entries. */ | |
c39e89c3 | 5227 | c_dot_file_symbol (sfname); |
e86fc4a5 CC |
5228 | S_SET_NUMBER_AUXILIARY (symbol_rootP, auxnb); |
5229 | coffsym = coffsymbol (symbol_get_bfdsym (symbol_rootP)); | |
5230 | coffsym->native[1].u.auxent.x_file.x_ftype = XFT_FN; | |
5231 | ||
5232 | if (s1) | |
5233 | { | |
5234 | coffsym->native[2].u.auxent.x_file.x_ftype = XFT_CT; | |
5235 | coffsym->native[2].extrap = s1; | |
5236 | } | |
5237 | if (s2) | |
5238 | { | |
5239 | coffsym->native[3].u.auxent.x_file.x_ftype = XFT_CV; | |
5240 | coffsym->native[3].extrap = s2; | |
5241 | } | |
5242 | if (s3) | |
5243 | { | |
5244 | coffsym->native[4].u.auxent.x_file.x_ftype = XFT_CD; | |
5245 | coffsym->native[4].extrap = s3; | |
5246 | } | |
5247 | ||
5248 | demand_empty_rest_of_line (); | |
5249 | } | |
5250 | } | |
5251 | ||
252b5132 RH |
5252 | /* The .function pseudo-op. This takes several arguments. The first |
5253 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 5254 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
5255 | uses the same name for both. I have no idea what the third and |
5256 | fourth arguments are meant to be. The optional fifth argument is | |
5257 | an expression for the size of the function. In COFF this symbol | |
5258 | gets an aux entry like that used for a csect. */ | |
5259 | ||
5260 | static void | |
98027b10 | 5261 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5262 | { |
5263 | char *name; | |
5264 | char endc; | |
5265 | char *s; | |
5266 | symbolS *ext_sym; | |
5267 | symbolS *lab_sym; | |
5268 | ||
d02603dc | 5269 | endc = get_symbol_name (&name); |
252b5132 RH |
5270 | |
5271 | /* Ignore any [PR] suffix. */ | |
5272 | name = ppc_canonicalize_symbol_name (name); | |
5273 | s = strchr (name, '['); | |
5274 | if (s != (char *) NULL | |
5275 | && strcmp (s + 1, "PR]") == 0) | |
5276 | *s = '\0'; | |
5277 | ||
5278 | ext_sym = symbol_find_or_make (name); | |
5279 | ||
d02603dc | 5280 | (void) restore_line_pointer (endc); |
252b5132 RH |
5281 | |
5282 | if (*input_line_pointer != ',') | |
5283 | { | |
5284 | as_bad (_("missing symbol name")); | |
5285 | ignore_rest_of_line (); | |
5286 | return; | |
5287 | } | |
5288 | ++input_line_pointer; | |
5289 | ||
d02603dc | 5290 | endc = get_symbol_name (&name); |
252b5132 RH |
5291 | |
5292 | lab_sym = symbol_find_or_make (name); | |
5293 | ||
d02603dc | 5294 | (void) restore_line_pointer (endc); |
252b5132 RH |
5295 | |
5296 | if (ext_sym != lab_sym) | |
5297 | { | |
809ffe0d ILT |
5298 | expressionS exp; |
5299 | ||
5300 | exp.X_op = O_symbol; | |
5301 | exp.X_add_symbol = lab_sym; | |
5302 | exp.X_op_symbol = NULL; | |
5303 | exp.X_add_number = 0; | |
5304 | exp.X_unsigned = 0; | |
5305 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
5306 | } |
5307 | ||
96d56e9f NC |
5308 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
5309 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 5310 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
5311 | |
5312 | if (*input_line_pointer == ',') | |
5313 | { | |
91d6fa6a | 5314 | expressionS exp; |
252b5132 RH |
5315 | |
5316 | /* Ignore the third argument. */ | |
5317 | ++input_line_pointer; | |
91d6fa6a | 5318 | expression (& exp); |
252b5132 RH |
5319 | if (*input_line_pointer == ',') |
5320 | { | |
5321 | /* Ignore the fourth argument. */ | |
5322 | ++input_line_pointer; | |
91d6fa6a | 5323 | expression (& exp); |
252b5132 RH |
5324 | if (*input_line_pointer == ',') |
5325 | { | |
97834047 CC |
5326 | /* The fifth argument is the function size. |
5327 | If it's omitted, the size will be the containing csect. | |
5328 | This will be donce during ppc_frob_symtab. */ | |
252b5132 | 5329 | ++input_line_pointer; |
e01e1cee AM |
5330 | symbol_get_tc (ext_sym)->u.size |
5331 | = symbol_new ("L0\001", absolute_section, | |
5332 | &zero_address_frag, 0); | |
85645aed | 5333 | pseudo_set (symbol_get_tc (ext_sym)->u.size); |
252b5132 RH |
5334 | } |
5335 | } | |
5336 | } | |
5337 | ||
5338 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5339 | SF_SET_FUNCTION (ext_sym); | |
5340 | SF_SET_PROCESS (ext_sym); | |
5341 | coff_add_linesym (ext_sym); | |
5342 | ||
5343 | demand_empty_rest_of_line (); | |
5344 | } | |
5345 | ||
5346 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
5347 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
5348 | with the correct line number */ | |
5d6255fe | 5349 | |
8642cce8 | 5350 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
5351 | |
5352 | static void | |
98027b10 | 5353 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5354 | { |
5355 | symbolS *sym; | |
5356 | ||
5357 | sym = symbol_make (".bf"); | |
5358 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5359 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5360 | S_SET_VALUE (sym, frag_now_fix ()); |
5361 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5362 | ||
5363 | coff_line_base = get_absolute_expression (); | |
5364 | ||
5365 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5366 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
5367 | ||
8642cce8 | 5368 | /* Line number for bi. */ |
5d6255fe | 5369 | if (saved_bi_sym) |
8642cce8 TR |
5370 | { |
5371 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
5372 | saved_bi_sym = 0; | |
5373 | } | |
5d6255fe | 5374 | |
8642cce8 | 5375 | |
809ffe0d | 5376 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5377 | |
5378 | ppc_frob_label (sym); | |
5379 | ||
5380 | demand_empty_rest_of_line (); | |
5381 | } | |
5382 | ||
5383 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
5384 | ".ef", except that the line number is absolute, not relative to the | |
5385 | most recent ".bf" symbol. */ | |
5386 | ||
5387 | static void | |
98027b10 | 5388 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5389 | { |
5390 | symbolS *sym; | |
5391 | ||
5392 | sym = symbol_make (".ef"); | |
5393 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5394 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5395 | S_SET_VALUE (sym, frag_now_fix ()); |
5396 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5397 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5398 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5399 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5400 | |
5401 | ppc_frob_label (sym); | |
5402 | ||
5403 | demand_empty_rest_of_line (); | |
5404 | } | |
5405 | ||
5406 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5407 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5408 | the symbol list. The value of .bi will be know when the next .bf |
5409 | is encountered. */ | |
252b5132 RH |
5410 | |
5411 | static void | |
98027b10 | 5412 | ppc_biei (int ei) |
252b5132 RH |
5413 | { |
5414 | static symbolS *last_biei; | |
5415 | ||
5416 | char *name; | |
5417 | int len; | |
5418 | symbolS *sym; | |
5419 | symbolS *look; | |
5420 | ||
5421 | name = demand_copy_C_string (&len); | |
5422 | ||
5423 | /* The value of these symbols is actually file offset. Here we set | |
5424 | the value to the index into the line number entries. In | |
5425 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5426 | to do the right thing. */ | |
5427 | ||
5428 | sym = symbol_make (name); | |
5429 | /* obj-coff.c currently only handles line numbers correctly in the | |
5430 | .text section. */ | |
5431 | S_SET_SEGMENT (sym, text_section); | |
5432 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5433 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5434 | |
5435 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5436 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5437 | |
8642cce8 | 5438 | /* Save bi. */ |
5d6255fe | 5439 | if (ei) |
8642cce8 TR |
5440 | saved_bi_sym = 0; |
5441 | else | |
5442 | saved_bi_sym = sym; | |
5443 | ||
252b5132 RH |
5444 | for (look = last_biei ? last_biei : symbol_rootP; |
5445 | (look != (symbolS *) NULL | |
5446 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5447 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5448 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5449 | look = symbol_next (look)) | |
5450 | ; | |
5451 | if (look != (symbolS *) NULL) | |
5452 | { | |
5453 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5454 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5455 | last_biei = sym; | |
5456 | } | |
5457 | ||
5458 | demand_empty_rest_of_line (); | |
5459 | } | |
5460 | ||
5461 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5462 | There is one argument, which is a csect symbol. The value of the | |
5463 | .bs symbol is the index of this csect symbol. */ | |
5464 | ||
5465 | static void | |
98027b10 | 5466 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5467 | { |
5468 | char *name; | |
5469 | char endc; | |
5470 | symbolS *csect; | |
5471 | symbolS *sym; | |
5472 | ||
5473 | if (ppc_current_block != NULL) | |
5474 | as_bad (_("nested .bs blocks")); | |
5475 | ||
d02603dc | 5476 | endc = get_symbol_name (&name); |
252b5132 RH |
5477 | |
5478 | csect = symbol_find_or_make (name); | |
5479 | ||
d02603dc | 5480 | (void) restore_line_pointer (endc); |
252b5132 RH |
5481 | |
5482 | sym = symbol_make (".bs"); | |
5483 | S_SET_SEGMENT (sym, now_seg); | |
5484 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5485 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5486 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5487 | |
809ffe0d | 5488 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5489 | |
5490 | ppc_frob_label (sym); | |
5491 | ||
5492 | ppc_current_block = sym; | |
5493 | ||
5494 | demand_empty_rest_of_line (); | |
5495 | } | |
5496 | ||
5497 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5498 | ||
5499 | static void | |
98027b10 | 5500 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5501 | { |
5502 | symbolS *sym; | |
5503 | ||
5504 | if (ppc_current_block == NULL) | |
5505 | as_bad (_(".es without preceding .bs")); | |
5506 | ||
5507 | sym = symbol_make (".es"); | |
5508 | S_SET_SEGMENT (sym, now_seg); | |
5509 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5510 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5511 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5512 | |
5513 | ppc_frob_label (sym); | |
5514 | ||
5515 | ppc_current_block = NULL; | |
5516 | ||
5517 | demand_empty_rest_of_line (); | |
5518 | } | |
5519 | ||
5520 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5521 | line number. */ | |
5522 | ||
5523 | static void | |
98027b10 | 5524 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5525 | { |
5526 | symbolS *sym; | |
5527 | ||
5528 | sym = symbol_make (".bb"); | |
5529 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5530 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5531 | S_SET_VALUE (sym, frag_now_fix ()); |
5532 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5533 | ||
5534 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5535 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5536 | ||
809ffe0d | 5537 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5538 | |
5539 | SF_SET_PROCESS (sym); | |
5540 | ||
5541 | ppc_frob_label (sym); | |
5542 | ||
5543 | demand_empty_rest_of_line (); | |
5544 | } | |
5545 | ||
5546 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5547 | line number. */ | |
5548 | ||
5549 | static void | |
98027b10 | 5550 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5551 | { |
5552 | symbolS *sym; | |
5553 | ||
5554 | sym = symbol_make (".eb"); | |
5555 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5556 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5557 | S_SET_VALUE (sym, frag_now_fix ()); |
5558 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5559 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5560 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5561 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5562 | |
5563 | SF_SET_PROCESS (sym); | |
5564 | ||
5565 | ppc_frob_label (sym); | |
5566 | ||
5567 | demand_empty_rest_of_line (); | |
5568 | } | |
5569 | ||
5570 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5571 | specified name. */ | |
5572 | ||
5573 | static void | |
98027b10 | 5574 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5575 | { |
5576 | char *name; | |
5577 | int len; | |
5578 | symbolS *sym; | |
5579 | ||
5580 | name = demand_copy_C_string (&len); | |
5581 | sym = symbol_make (name); | |
5582 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5583 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5584 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5585 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5586 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5587 | |
5588 | ppc_frob_label (sym); | |
5589 | ||
5590 | demand_empty_rest_of_line (); | |
5591 | } | |
5592 | ||
5593 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5594 | ||
5595 | static void | |
98027b10 | 5596 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5597 | { |
5598 | symbolS *sym; | |
5599 | ||
5600 | sym = symbol_make (".ec"); | |
5601 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5602 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5603 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5604 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5605 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5606 | |
5607 | ppc_frob_label (sym); | |
5608 | ||
5609 | demand_empty_rest_of_line (); | |
5610 | } | |
5611 | ||
5612 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5613 | ||
5614 | static void | |
98027b10 | 5615 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5616 | { |
5617 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5618 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5619 | else |
5620 | { | |
5621 | subsegT subseg; | |
5622 | symbolS *sym; | |
5623 | symbolS *list; | |
81d4177b | 5624 | |
1b2cb8e2 CC |
5625 | subseg = ppc_xcoff_data_section.next_subsegment; |
5626 | ++ppc_xcoff_data_section.next_subsegment; | |
252b5132 RH |
5627 | |
5628 | subseg_new (segment_name (data_section), subseg); | |
5629 | ppc_toc_frag = frag_now; | |
5630 | ||
5631 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5632 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5633 | S_SET_SEGMENT (sym, data_section); |
5634 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5635 | symbol_get_tc (sym)->subseg = subseg; |
5636 | symbol_get_tc (sym)->output = 1; | |
5637 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5638 | |
5639 | ppc_toc_csect = sym; | |
81d4177b | 5640 | |
1b2cb8e2 | 5641 | for (list = ppc_xcoff_data_section.csects; |
809ffe0d ILT |
5642 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5643 | list = symbol_get_tc (list)->next) | |
252b5132 | 5644 | ; |
809ffe0d | 5645 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5646 | |
5647 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5648 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5649 | &symbol_lastP); | |
252b5132 RH |
5650 | } |
5651 | ||
5652 | ppc_current_csect = ppc_toc_csect; | |
5653 | ||
5654 | demand_empty_rest_of_line (); | |
5655 | } | |
5656 | ||
5657 | /* The AIX assembler automatically aligns the operands of a .long or | |
5658 | .short pseudo-op, and we want to be compatible. */ | |
5659 | ||
5660 | static void | |
98027b10 | 5661 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5662 | { |
5663 | frag_align (log_size, 0, 0); | |
5664 | record_alignment (now_seg, log_size); | |
5665 | cons (1 << log_size); | |
5666 | } | |
5667 | ||
5668 | static void | |
98027b10 | 5669 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5670 | { |
5671 | expressionS exp; | |
5672 | int byte_count; | |
5673 | ||
5674 | (void) expression (&exp); | |
5675 | ||
5676 | if (exp.X_op != O_constant) | |
5677 | { | |
5678 | as_bad (_("non-constant byte count")); | |
5679 | return; | |
5680 | } | |
5681 | ||
5682 | byte_count = exp.X_add_number; | |
5683 | ||
5684 | if (*input_line_pointer != ',') | |
5685 | { | |
5686 | as_bad (_("missing value")); | |
5687 | return; | |
5688 | } | |
5689 | ||
5690 | ++input_line_pointer; | |
5691 | cons (byte_count); | |
5692 | } | |
5693 | ||
85645aed | 5694 | void |
ed2917de | 5695 | ppc_xcoff_md_finish (void) |
85645aed TG |
5696 | { |
5697 | int i; | |
5698 | ||
5699 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5700 | { | |
5701 | struct dw_section *dws = &dw_sections[i]; | |
5702 | struct dw_subsection *dwss; | |
5703 | ||
5704 | if (dws->anon_subseg) | |
5705 | { | |
5706 | dwss = dws->anon_subseg; | |
5707 | dwss->link = dws->list_subseg; | |
5708 | } | |
5709 | else | |
5710 | dwss = dws->list_subseg; | |
5711 | ||
5712 | for (; dwss != NULL; dwss = dwss->link) | |
5713 | if (dwss->end_exp.X_add_symbol != NULL) | |
5714 | { | |
5715 | subseg_set (dws->sect, dwss->subseg); | |
5716 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5717 | } | |
5718 | } | |
22f72c48 | 5719 | ppc_cpu = 0; |
85645aed TG |
5720 | } |
5721 | ||
252b5132 | 5722 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5723 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5724 | \f |
5725 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5726 | ELF. This takes two or more arguments. | |
5727 | ||
5728 | When generating XCOFF output, the first argument is the name to | |
5729 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5730 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5731 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5732 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5733 | depends on target word size. A 32-bit target uses 4-byte values, a |
5734 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5735 | |
5736 | When not generating XCOFF output, the arguments are the same, but | |
5737 | the first argument is simply ignored. */ | |
5738 | ||
5739 | static void | |
98027b10 | 5740 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5741 | { |
5742 | #ifdef OBJ_XCOFF | |
5743 | ||
5744 | /* Define the TOC symbol name. */ | |
5745 | { | |
5746 | char *name; | |
5747 | char endc; | |
5748 | symbolS *sym; | |
5749 | ||
5750 | if (ppc_toc_csect == (symbolS *) NULL | |
5751 | || ppc_toc_csect != ppc_current_csect) | |
5752 | { | |
5753 | as_bad (_(".tc not in .toc section")); | |
5754 | ignore_rest_of_line (); | |
5755 | return; | |
5756 | } | |
5757 | ||
d02603dc | 5758 | endc = get_symbol_name (&name); |
252b5132 RH |
5759 | |
5760 | sym = symbol_find_or_make (name); | |
5761 | ||
d02603dc | 5762 | (void) restore_line_pointer (endc); |
252b5132 RH |
5763 | |
5764 | if (S_IS_DEFINED (sym)) | |
5765 | { | |
5766 | symbolS *label; | |
5767 | ||
809ffe0d | 5768 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5769 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5770 | { |
5771 | as_bad (_(".tc with no label")); | |
5772 | ignore_rest_of_line (); | |
5773 | return; | |
5774 | } | |
5775 | ||
5776 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5777 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5778 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5779 | ||
5780 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5781 | ++input_line_pointer; | |
5782 | ||
5783 | return; | |
5784 | } | |
5785 | ||
5786 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5787 | symbol_set_frag (sym, frag_now); |
252b5132 | 5788 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4a403be0 CC |
5789 | |
5790 | /* AIX assembler seems to allow any storage class to be set in .tc. | |
5791 | But for now, only XMC_TC and XMC_TE are supported by us. */ | |
5792 | switch (symbol_get_tc (sym)->symbol_class) | |
5793 | { | |
5794 | case XMC_TC: | |
5795 | case XMC_TE: | |
5796 | break; | |
5797 | ||
5798 | default: | |
5799 | as_bad (_(".tc with storage class %d not yet supported"), | |
5800 | symbol_get_tc (sym)->symbol_class); | |
5801 | ignore_rest_of_line (); | |
5802 | return; | |
5803 | } | |
809ffe0d | 5804 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5805 | |
5806 | ppc_frob_label (sym); | |
5807 | } | |
5808 | ||
0baf16f2 AM |
5809 | #endif /* OBJ_XCOFF */ |
5810 | #ifdef OBJ_ELF | |
9c7977b3 | 5811 | int align; |
252b5132 RH |
5812 | |
5813 | /* Skip the TOC symbol name. */ | |
5814 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5815 | || *input_line_pointer == ' ' |
252b5132 RH |
5816 | || *input_line_pointer == '[' |
5817 | || *input_line_pointer == ']' | |
5818 | || *input_line_pointer == '{' | |
5819 | || *input_line_pointer == '}') | |
5820 | ++input_line_pointer; | |
5821 | ||
0baf16f2 | 5822 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5823 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5824 | frag_align (align, 0, 0); |
5825 | record_alignment (now_seg, align); | |
0baf16f2 | 5826 | #endif /* OBJ_ELF */ |
252b5132 RH |
5827 | |
5828 | if (*input_line_pointer != ',') | |
5829 | demand_empty_rest_of_line (); | |
5830 | else | |
5831 | { | |
5832 | ++input_line_pointer; | |
2b3c4602 | 5833 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5834 | } |
5835 | } | |
0baf16f2 AM |
5836 | |
5837 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5838 | |
5839 | static void | |
98027b10 | 5840 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5841 | { |
d02603dc | 5842 | char c; |
69c040df AM |
5843 | char *cpu_string; |
5844 | #define MAX_HISTORY 100 | |
fa452fa6 | 5845 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5846 | static int curr_hist; |
5847 | ||
5848 | SKIP_WHITESPACE (); | |
5849 | ||
d02603dc NC |
5850 | c = get_symbol_name (&cpu_string); |
5851 | cpu_string = xstrdup (cpu_string); | |
5852 | (void) restore_line_pointer (c); | |
69c040df AM |
5853 | |
5854 | if (cpu_string != NULL) | |
5855 | { | |
fa452fa6 | 5856 | ppc_cpu_t old_cpu = ppc_cpu; |
69c040df AM |
5857 | char *p; |
5858 | ||
5859 | for (p = cpu_string; *p != 0; p++) | |
5860 | *p = TOLOWER (*p); | |
5861 | ||
5862 | if (strcmp (cpu_string, "push") == 0) | |
5863 | { | |
5864 | if (cpu_history == NULL) | |
325801bd | 5865 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5866 | |
5867 | if (curr_hist >= MAX_HISTORY) | |
5868 | as_bad (_(".machine stack overflow")); | |
5869 | else | |
5870 | cpu_history[curr_hist++] = ppc_cpu; | |
5871 | } | |
5872 | else if (strcmp (cpu_string, "pop") == 0) | |
5873 | { | |
5874 | if (curr_hist <= 0) | |
5875 | as_bad (_(".machine stack underflow")); | |
5876 | else | |
5877 | ppc_cpu = cpu_history[--curr_hist]; | |
5878 | } | |
69c040df | 5879 | else |
b25f942e AM |
5880 | { |
5881 | ppc_cpu_t new_cpu; | |
5882 | /* Not using the global "sticky" variable here results in | |
5883 | none of the extra functional unit command line options, | |
5884 | -many, -maltivec, -mspe, -mspe2, -mvle, -mvsx, being in | |
5885 | force after selecting a new cpu with .machine. | |
5886 | ".machine altivec" and other extra functional unit | |
5887 | options do not count as a new machine, instead they add | |
5888 | to currently selected opcodes. */ | |
5889 | ppc_cpu_t machine_sticky = 0; | |
cebc89b9 AM |
5890 | /* Unfortunately, some versions of gcc emit a .machine |
5891 | directive very near the start of the compiler's assembly | |
5892 | output file. This is bad because it overrides user -Wa | |
5893 | cpu selection. Worse, there are versions of gcc that | |
5894 | emit the *wrong* cpu, not even respecting the -mcpu given | |
5895 | to gcc. See gcc pr101393. And to compound the problem, | |
5896 | as of 20220222 gcc doesn't pass the correct cpu option to | |
5897 | gas on the command line. See gcc pr59828. Hack around | |
5898 | this by keeping sticky options for an early .machine. */ | |
5899 | asection *sec; | |
5900 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
5901 | { | |
5902 | segment_info_type *info = seg_info (sec); | |
5903 | /* Are the frags for this section perturbed from their | |
5904 | initial state? Even .align will count here. */ | |
5905 | if (info != NULL | |
5906 | && (info->frchainP->frch_root != info->frchainP->frch_last | |
5907 | || info->frchainP->frch_root->fr_type != rs_fill | |
5908 | || info->frchainP->frch_root->fr_fix != 0)) | |
5909 | break; | |
5910 | } | |
5911 | new_cpu = ppc_parse_cpu (ppc_cpu, | |
5912 | sec == NULL ? &sticky : &machine_sticky, | |
5913 | cpu_string); | |
b25f942e AM |
5914 | if (new_cpu != 0) |
5915 | ppc_cpu = new_cpu; | |
5916 | else | |
5917 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5918 | } | |
69c040df AM |
5919 | |
5920 | if (ppc_cpu != old_cpu) | |
5921 | ppc_setup_opcodes (); | |
5922 | } | |
5923 | ||
5924 | demand_empty_rest_of_line (); | |
0baf16f2 | 5925 | } |
0baf16f2 | 5926 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 | 5927 | \f |
252b5132 RH |
5928 | #ifdef OBJ_XCOFF |
5929 | ||
5930 | /* XCOFF specific symbol and file handling. */ | |
5931 | ||
5932 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
5933 | any, to use square brackets, and to be in upper case. */ | |
5934 | ||
5935 | char * | |
98027b10 | 5936 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
5937 | { |
5938 | char *s; | |
5939 | ||
5940 | if (ppc_stab_symbol) | |
5941 | return name; | |
5942 | ||
5943 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
5944 | ; | |
5945 | if (*s != '\0') | |
5946 | { | |
5947 | char brac; | |
5948 | ||
5949 | if (*s == '[') | |
5950 | brac = ']'; | |
5951 | else | |
5952 | { | |
5953 | *s = '['; | |
5954 | brac = '}'; | |
5955 | } | |
5956 | ||
5957 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 5958 | *s = TOUPPER (*s); |
252b5132 RH |
5959 | |
5960 | if (*s == '\0' || s[1] != '\0') | |
5961 | as_bad (_("bad symbol suffix")); | |
5962 | ||
5963 | *s = ']'; | |
5964 | } | |
5965 | ||
5966 | return name; | |
5967 | } | |
5968 | ||
5969 | /* Set the class of a symbol based on the suffix, if any. This is | |
5970 | called whenever a new symbol is created. */ | |
5971 | ||
5972 | void | |
98027b10 | 5973 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 5974 | { |
809ffe0d | 5975 | struct ppc_tc_sy *tc; |
252b5132 RH |
5976 | const char *s; |
5977 | ||
809ffe0d ILT |
5978 | tc = symbol_get_tc (sym); |
5979 | tc->next = NULL; | |
5980 | tc->output = 0; | |
96d56e9f | 5981 | tc->symbol_class = -1; |
809ffe0d ILT |
5982 | tc->real_name = NULL; |
5983 | tc->subseg = 0; | |
5984 | tc->align = 0; | |
85645aed TG |
5985 | tc->u.size = NULL; |
5986 | tc->u.dw = NULL; | |
809ffe0d | 5987 | tc->within = NULL; |
252b5132 RH |
5988 | |
5989 | if (ppc_stab_symbol) | |
5990 | return; | |
5991 | ||
5992 | s = strchr (S_GET_NAME (sym), '['); | |
5993 | if (s == (const char *) NULL) | |
5994 | { | |
5995 | /* There is no suffix. */ | |
5996 | return; | |
5997 | } | |
5998 | ||
5999 | ++s; | |
6000 | ||
6001 | switch (s[0]) | |
6002 | { | |
6003 | case 'B': | |
6004 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 6005 | tc->symbol_class = XMC_BS; |
252b5132 RH |
6006 | break; |
6007 | case 'D': | |
6008 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 6009 | tc->symbol_class = XMC_DB; |
252b5132 | 6010 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 6011 | tc->symbol_class = XMC_DS; |
252b5132 RH |
6012 | break; |
6013 | case 'G': | |
6014 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 6015 | tc->symbol_class = XMC_GL; |
252b5132 RH |
6016 | break; |
6017 | case 'P': | |
6018 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 6019 | tc->symbol_class = XMC_PR; |
252b5132 RH |
6020 | break; |
6021 | case 'R': | |
6022 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 6023 | tc->symbol_class = XMC_RO; |
252b5132 | 6024 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 6025 | tc->symbol_class = XMC_RW; |
252b5132 RH |
6026 | break; |
6027 | case 'S': | |
6028 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 6029 | tc->symbol_class = XMC_SV; |
252b5132 RH |
6030 | break; |
6031 | case 'T': | |
6032 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 6033 | tc->symbol_class = XMC_TC; |
252b5132 | 6034 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 6035 | tc->symbol_class = XMC_TI; |
252b5132 | 6036 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 6037 | tc->symbol_class = XMC_TB; |
252b5132 | 6038 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 6039 | tc->symbol_class = XMC_TC0; |
4a403be0 CC |
6040 | else if (strcmp (s, "TE]") == 0) |
6041 | tc->symbol_class = XMC_TE; | |
1b2cb8e2 CC |
6042 | else if (strcmp (s, "TL]") == 0) |
6043 | tc->symbol_class = XMC_TL; | |
252b5132 RH |
6044 | break; |
6045 | case 'U': | |
6046 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 6047 | tc->symbol_class = XMC_UA; |
252b5132 | 6048 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 6049 | tc->symbol_class = XMC_UC; |
1b2cb8e2 CC |
6050 | else if (strcmp (s, "UL]") == 0) |
6051 | tc->symbol_class = XMC_UL; | |
252b5132 RH |
6052 | break; |
6053 | case 'X': | |
6054 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 6055 | tc->symbol_class = XMC_XO; |
252b5132 RH |
6056 | break; |
6057 | } | |
6058 | ||
96d56e9f | 6059 | if (tc->symbol_class == -1) |
d6ed37ed | 6060 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
6061 | } |
6062 | ||
252b5132 RH |
6063 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
6064 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
6065 | the symbols. */ | |
6066 | ||
5b7c81bd | 6067 | static bool ppc_saw_abs; |
252b5132 RH |
6068 | |
6069 | /* Change the name of a symbol just before writing it out. Set the | |
6070 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
6071 | class suffix. Return 1 if the symbol should not be included in the | |
6072 | symbol table. */ | |
6073 | ||
6074 | int | |
98027b10 | 6075 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
6076 | { |
6077 | static symbolS *ppc_last_function; | |
6078 | static symbolS *set_end; | |
6079 | ||
6080 | /* Discard symbols that should not be included in the output symbol | |
6081 | table. */ | |
809ffe0d | 6082 | if (! symbol_used_in_reloc_p (sym) |
97834047 | 6083 | && S_GET_STORAGE_CLASS (sym) != C_DWARF |
809ffe0d | 6084 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 |
670ec21d | 6085 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6086 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
6087 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
6088 | return 1; | |
6089 | ||
a161fe53 AM |
6090 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
6091 | if (sym == abs_section_sym) | |
6092 | return 1; | |
6093 | ||
809ffe0d ILT |
6094 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
6095 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
6096 | else |
6097 | { | |
6098 | const char *name; | |
6099 | const char *s; | |
6100 | ||
6101 | name = S_GET_NAME (sym); | |
6102 | s = strchr (name, '['); | |
6103 | if (s != (char *) NULL) | |
6104 | { | |
6105 | unsigned int len; | |
6106 | char *snew; | |
6107 | ||
6108 | len = s - name; | |
a44e2901 | 6109 | snew = xstrndup (name, len); |
252b5132 RH |
6110 | |
6111 | S_SET_NAME (sym, snew); | |
6112 | } | |
6113 | } | |
6114 | ||
6115 | if (set_end != (symbolS *) NULL) | |
6116 | { | |
6117 | SA_SET_SYM_ENDNDX (set_end, sym); | |
6118 | set_end = NULL; | |
6119 | } | |
6120 | ||
6121 | if (SF_GET_FUNCTION (sym)) | |
6122 | { | |
97834047 CC |
6123 | /* Make sure coff_last_function is reset. Otherwise, we won't create |
6124 | the auxent for the next function. */ | |
6125 | coff_last_function = 0; | |
252b5132 | 6126 | ppc_last_function = sym; |
85645aed | 6127 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 6128 | { |
85645aed | 6129 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 6130 | SA_SET_SYM_FSIZE (sym, |
85645aed | 6131 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 | 6132 | } |
97834047 CC |
6133 | else |
6134 | { | |
6135 | /* Size of containing csect. */ | |
6136 | symbolS* within = symbol_get_tc (sym)->within; | |
6137 | union internal_auxent *csectaux; | |
6138 | csectaux = &coffsymbol (symbol_get_bfdsym (within)) | |
6139 | ->native[S_GET_NUMBER_AUXILIARY(within)].u.auxent; | |
6140 | ||
6141 | SA_SET_SYM_FSIZE (sym, csectaux->x_csect.x_scnlen.l); | |
6142 | } | |
252b5132 RH |
6143 | } |
6144 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
6145 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
6146 | { | |
6147 | if (ppc_last_function == (symbolS *) NULL) | |
6148 | as_bad (_(".ef with no preceding .function")); | |
6149 | else | |
6150 | { | |
6151 | set_end = ppc_last_function; | |
6152 | ppc_last_function = NULL; | |
6153 | ||
6154 | /* We don't have a C_EFCN symbol, but we need to force the | |
6155 | COFF backend to believe that it has seen one. */ | |
6156 | coff_last_function = NULL; | |
6157 | } | |
6158 | } | |
6159 | ||
670ec21d | 6160 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6161 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
6162 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
6163 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
6164 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
6165 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
6166 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
6167 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
6168 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
6169 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
6170 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
6171 | ||
6172 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 6173 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
6174 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
6175 | { | |
6176 | int i; | |
6177 | union internal_auxent *a; | |
6178 | ||
6179 | /* Create a csect aux. */ | |
6180 | i = S_GET_NUMBER_AUXILIARY (sym); | |
6181 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 6182 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 6183 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
6184 | { |
6185 | /* This is the TOC table. */ | |
6186 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
6187 | a->x_csect.x_scnlen.l = 0; | |
6188 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6189 | } | |
809ffe0d | 6190 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
6191 | { |
6192 | /* This is a csect symbol. x_scnlen is the size of the | |
6193 | csect. */ | |
809ffe0d | 6194 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 6195 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
6196 | - S_GET_VALUE (sym)); |
6197 | else | |
6198 | { | |
6386f3a7 | 6199 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 6200 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
6201 | - S_GET_VALUE (sym)); |
6202 | } | |
a83ef1c7 CC |
6203 | if (symbol_get_tc (sym)->symbol_class == XMC_BS |
6204 | || symbol_get_tc (sym)->symbol_class == XMC_UL) | |
bcf84703 CC |
6205 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; |
6206 | else | |
6207 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; | |
252b5132 | 6208 | } |
1b2cb8e2 CC |
6209 | else if (S_GET_SEGMENT (sym) == bss_section |
6210 | || S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) | |
252b5132 RH |
6211 | { |
6212 | /* This is a common symbol. */ | |
809ffe0d ILT |
6213 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
6214 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
1b2cb8e2 CC |
6215 | if (S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) |
6216 | symbol_get_tc (sym)->symbol_class = XMC_UL; | |
6217 | else if (S_IS_EXTERNAL (sym)) | |
96d56e9f | 6218 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 6219 | else |
96d56e9f | 6220 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
6221 | } |
6222 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
6223 | { | |
6224 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 6225 | ppc_adjust_symtab. */ |
5b7c81bd | 6226 | ppc_saw_abs = true; |
252b5132 | 6227 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
6228 | if (symbol_get_tc (sym)->symbol_class == -1) |
6229 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
6230 | } |
6231 | else if (! S_IS_DEFINED (sym)) | |
6232 | { | |
6233 | /* This is an external symbol. */ | |
6234 | a->x_csect.x_scnlen.l = 0; | |
6235 | a->x_csect.x_smtyp = XTY_ER; | |
6236 | } | |
4a403be0 | 6237 | else if (ppc_is_toc_sym (sym)) |
252b5132 RH |
6238 | { |
6239 | symbolS *next; | |
6240 | ||
6241 | /* This is a TOC definition. x_scnlen is the size of the | |
6242 | TOC entry. */ | |
6243 | next = symbol_next (sym); | |
96d56e9f | 6244 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6245 | next = symbol_next (next); |
6246 | if (next == (symbolS *) NULL | |
4a403be0 | 6247 | || (!ppc_is_toc_sym (next))) |
252b5132 RH |
6248 | { |
6249 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 6250 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
6251 | - S_GET_VALUE (sym)); |
6252 | else | |
6253 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6254 | - S_GET_VALUE (sym)); | |
6255 | } | |
6256 | else | |
6257 | { | |
6386f3a7 | 6258 | resolve_symbol_value (next); |
252b5132 RH |
6259 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6260 | - S_GET_VALUE (sym)); | |
6261 | } | |
6262 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6263 | } | |
6264 | else | |
6265 | { | |
6266 | symbolS *csect; | |
6267 | ||
6268 | /* This is a normal symbol definition. x_scnlen is the | |
6269 | symbol index of the containing csect. */ | |
6270 | if (S_GET_SEGMENT (sym) == text_section) | |
1b2cb8e2 | 6271 | csect = ppc_xcoff_text_section.csects; |
252b5132 | 6272 | else if (S_GET_SEGMENT (sym) == data_section) |
1b2cb8e2 CC |
6273 | csect = ppc_xcoff_data_section.csects; |
6274 | else if (S_GET_SEGMENT (sym) == ppc_xcoff_tdata_section.segment) | |
6275 | csect = ppc_xcoff_tdata_section.csects; | |
252b5132 RH |
6276 | else |
6277 | abort (); | |
6278 | ||
6279 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6280 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6281 | |
6282 | if (csect == (symbolS *) NULL) | |
6283 | { | |
6284 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6285 | a->x_csect.x_scnlen.l = 0; | |
6286 | } | |
6287 | else | |
6288 | { | |
809ffe0d | 6289 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6290 | { |
6386f3a7 | 6291 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6292 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6293 | > S_GET_VALUE (sym)) | |
252b5132 | 6294 | break; |
809ffe0d | 6295 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6296 | } |
6297 | ||
809ffe0d ILT |
6298 | a->x_csect.x_scnlen.p = |
6299 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6300 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6301 | 1; | |
252b5132 RH |
6302 | } |
6303 | a->x_csect.x_smtyp = XTY_LD; | |
6304 | } | |
81d4177b | 6305 | |
252b5132 RH |
6306 | a->x_csect.x_parmhash = 0; |
6307 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6308 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6309 | a->x_csect.x_smclas = XMC_PR; |
6310 | else | |
96d56e9f | 6311 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6312 | a->x_csect.x_stab = 0; |
6313 | a->x_csect.x_snstab = 0; | |
6314 | ||
6315 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6316 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6317 | } |
6318 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6319 | { | |
6320 | /* We want the value to be the symbol index of the referenced | |
6321 | csect symbol. BFD will do that for us if we set the right | |
6322 | flags. */ | |
b782de16 AM |
6323 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6324 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6325 | ||
6326 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6327 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6328 | } |
6329 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6330 | { | |
6331 | symbolS *block; | |
c734e7e3 | 6332 | valueT base; |
252b5132 | 6333 | |
809ffe0d | 6334 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6335 | if (block) |
6336 | { | |
6337 | /* The value is the offset from the enclosing csect. */ | |
6338 | symbolS *csect; | |
6339 | ||
6340 | csect = symbol_get_tc (block)->within; | |
6341 | resolve_symbol_value (csect); | |
6342 | base = S_GET_VALUE (csect); | |
6343 | } | |
6344 | else | |
6345 | base = 0; | |
6346 | ||
6347 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6348 | } |
6349 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6350 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6351 | { | |
6352 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6353 | BFD will do that for us if we set the right flags. We have |
6354 | already set the value correctly. */ | |
809ffe0d | 6355 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6356 | } |
6357 | ||
6358 | return 0; | |
6359 | } | |
6360 | ||
97834047 | 6361 | /* Adjust the symbol table. */ |
252b5132 RH |
6362 | |
6363 | void | |
98027b10 | 6364 | ppc_adjust_symtab (void) |
252b5132 RH |
6365 | { |
6366 | symbolS *sym; | |
97834047 CC |
6367 | symbolS *anchorSym; |
6368 | ||
6369 | /* Make sure C_DWARF symbols come right after C_FILE. | |
6370 | As the C_FILE might not be defined yet and as C_DWARF | |
6371 | might already be ordered, we insert them before the | |
6372 | first symbol which isn't a C_FILE or a C_DWARF. */ | |
6373 | for (anchorSym = symbol_rootP; anchorSym != NULL; | |
6374 | anchorSym = symbol_next (anchorSym)) | |
6375 | { | |
6376 | if (S_GET_STORAGE_CLASS (anchorSym) != C_FILE | |
6377 | && S_GET_STORAGE_CLASS (anchorSym) != C_DWARF) | |
6378 | break; | |
6379 | } | |
6380 | ||
6381 | sym = anchorSym; | |
6382 | while (sym != NULL) | |
6383 | { | |
6384 | if (S_GET_STORAGE_CLASS (sym) != C_DWARF) | |
6385 | { | |
6386 | sym = symbol_next (sym); | |
6387 | continue; | |
6388 | } | |
6389 | ||
6390 | symbolS* tsym = sym; | |
6391 | sym = symbol_next (sym); | |
6392 | ||
6393 | symbol_remove (tsym, &symbol_rootP, &symbol_lastP); | |
6394 | symbol_insert (tsym, anchorSym, &symbol_rootP, &symbol_lastP); | |
6395 | } | |
6396 | ||
6397 | /* Create csect symbols for all absolute symbols. */ | |
252b5132 RH |
6398 | |
6399 | if (! ppc_saw_abs) | |
6400 | return; | |
6401 | ||
6402 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6403 | { | |
6404 | symbolS *csect; | |
6405 | int i; | |
6406 | union internal_auxent *a; | |
6407 | ||
6408 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6409 | continue; | |
6410 | ||
6411 | csect = symbol_create (".abs[XO]", absolute_section, | |
e01e1cee | 6412 | &zero_address_frag, S_GET_VALUE (sym)); |
809ffe0d | 6413 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6414 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6415 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6416 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6417 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6418 | a->x_csect.x_scnlen.l = 0; |
6419 | a->x_csect.x_smtyp = XTY_SD; | |
6420 | a->x_csect.x_parmhash = 0; | |
6421 | a->x_csect.x_snhash = 0; | |
6422 | a->x_csect.x_smclas = XMC_XO; | |
6423 | a->x_csect.x_stab = 0; | |
6424 | a->x_csect.x_snstab = 0; | |
6425 | ||
6426 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6427 | ||
6428 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6429 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6430 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6431 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6432 | } |
6433 | ||
5b7c81bd | 6434 | ppc_saw_abs = false; |
252b5132 RH |
6435 | } |
6436 | ||
6437 | /* Set the VMA for a section. This is called on all the sections in | |
6438 | turn. */ | |
6439 | ||
6440 | void | |
98027b10 | 6441 | ppc_frob_section (asection *sec) |
252b5132 | 6442 | { |
931e13a6 | 6443 | static bfd_vma vma = 0; |
252b5132 | 6444 | |
85645aed | 6445 | /* Dwarf sections start at 0. */ |
fd361982 | 6446 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
6447 | return; |
6448 | ||
931e13a6 | 6449 | vma = md_section_align (sec, vma); |
fd361982 AM |
6450 | bfd_set_section_vma (sec, vma); |
6451 | vma += bfd_section_size (sec); | |
252b5132 RH |
6452 | } |
6453 | ||
6454 | #endif /* OBJ_XCOFF */ | |
6455 | \f | |
6d4af3c2 | 6456 | const char * |
98027b10 | 6457 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6458 | { |
499ac353 | 6459 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6460 | } |
6461 | ||
6462 | /* Write a value out to the object file, using the appropriate | |
6463 | endianness. */ | |
6464 | ||
6465 | void | |
98027b10 | 6466 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6467 | { |
6468 | if (target_big_endian) | |
6469 | number_to_chars_bigendian (buf, val, n); | |
6470 | else | |
6471 | number_to_chars_littleendian (buf, val, n); | |
6472 | } | |
6473 | ||
6474 | /* Align a section (I don't know why this is machine dependent). */ | |
6475 | ||
6476 | valueT | |
3aeeedbb | 6477 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6478 | { |
3aeeedbb AM |
6479 | #ifdef OBJ_ELF |
6480 | return addr; | |
6481 | #else | |
fd361982 | 6482 | int align = bfd_section_alignment (seg); |
252b5132 | 6483 | |
8d3842cd | 6484 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6485 | #endif |
252b5132 RH |
6486 | } |
6487 | ||
6488 | /* We don't have any form of relaxing. */ | |
6489 | ||
6490 | int | |
98027b10 AM |
6491 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6492 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6493 | { |
6494 | abort (); | |
6495 | return 0; | |
6496 | } | |
6497 | ||
6498 | /* Convert a machine dependent frag. We never generate these. */ | |
6499 | ||
6500 | void | |
98027b10 AM |
6501 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6502 | asection *sec ATTRIBUTE_UNUSED, | |
6503 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6504 | { |
6505 | abort (); | |
6506 | } | |
6507 | ||
6508 | /* We have no need to default values of symbols. */ | |
6509 | ||
252b5132 | 6510 | symbolS * |
98027b10 | 6511 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6512 | { |
6513 | return 0; | |
6514 | } | |
6515 | \f | |
6516 | /* Functions concerning relocs. */ | |
6517 | ||
6518 | /* The location from which a PC relative jump should be calculated, | |
6519 | given a PC relative reloc. */ | |
6520 | ||
6521 | long | |
98027b10 | 6522 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6523 | { |
6524 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6525 | } | |
6526 | ||
6527 | #ifdef OBJ_XCOFF | |
6528 | ||
c5df7e44 CC |
6529 | /* Return the surrending csect for sym when possible. */ |
6530 | ||
6531 | static symbolS* | |
6532 | ppc_get_csect_to_adjust (symbolS *sym) | |
6533 | { | |
6534 | if (sym == NULL) | |
6535 | return NULL; | |
6536 | ||
6537 | valueT val = resolve_symbol_value (sym); | |
6538 | TC_SYMFIELD_TYPE *tc = symbol_get_tc (sym); | |
6539 | segT symseg = S_GET_SEGMENT (sym); | |
6540 | ||
6541 | if (tc->subseg == 0 | |
6542 | && tc->symbol_class != XMC_TC0 | |
6543 | && tc->symbol_class != XMC_TC | |
6544 | && tc->symbol_class != XMC_TE | |
6545 | && symseg != bss_section | |
6546 | && symseg != ppc_xcoff_tbss_section.segment | |
6547 | /* Don't adjust if this is a reloc in the toc section. */ | |
6548 | && (symseg != data_section | |
6549 | || ppc_toc_csect == NULL | |
6550 | || val < ppc_toc_frag->fr_address | |
6551 | || (ppc_after_toc_frag != NULL | |
6552 | && val >= ppc_after_toc_frag->fr_address))) | |
6553 | { | |
6554 | symbolS* csect = tc->within; | |
6555 | ||
6556 | /* If the symbol was not declared by a label (eg: a section symbol), | |
6557 | use the section instead of the csect. This doesn't happen in | |
6558 | normal AIX assembly code. */ | |
6559 | if (csect == NULL) | |
6560 | csect = seg_info (symseg)->sym; | |
6561 | ||
6562 | return csect; | |
6563 | } | |
6564 | ||
6565 | return NULL; | |
6566 | } | |
6567 | ||
252b5132 RH |
6568 | /* This is called to see whether a fixup should be adjusted to use a |
6569 | section symbol. We take the opportunity to change a fixup against | |
6570 | a symbol in the TOC subsegment into a reloc against the | |
6571 | corresponding .tc symbol. */ | |
6572 | ||
6573 | int | |
98027b10 | 6574 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6575 | { |
b782de16 AM |
6576 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6577 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
c5df7e44 | 6578 | symbolS* csect; |
b782de16 AM |
6579 | |
6580 | if (symseg == absolute_section) | |
6581 | return 0; | |
252b5132 | 6582 | |
85645aed | 6583 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6584 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6585 | return 1; |
6586 | ||
252b5132 | 6587 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6588 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6589 | && symseg == data_section |
252b5132 RH |
6590 | && val >= ppc_toc_frag->fr_address |
6591 | && (ppc_after_toc_frag == (fragS *) NULL | |
6592 | || val < ppc_after_toc_frag->fr_address)) | |
6593 | { | |
6594 | symbolS *sy; | |
6595 | ||
6596 | for (sy = symbol_next (ppc_toc_csect); | |
6597 | sy != (symbolS *) NULL; | |
6598 | sy = symbol_next (sy)) | |
6599 | { | |
b782de16 AM |
6600 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6601 | ||
96d56e9f | 6602 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6603 | continue; |
4a403be0 CC |
6604 | if (sy_tc->symbol_class != XMC_TC |
6605 | && sy_tc->symbol_class != XMC_TE) | |
252b5132 | 6606 | break; |
b782de16 | 6607 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6608 | { |
6609 | fix->fx_addsy = sy; | |
6610 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6611 | return 0; | |
6612 | } | |
6613 | } | |
6614 | ||
6615 | as_bad_where (fix->fx_file, fix->fx_line, | |
6616 | _("symbol in .toc does not match any .tc")); | |
6617 | } | |
6618 | ||
6619 | /* Possibly adjust the reloc to be against the csect. */ | |
c5df7e44 | 6620 | if ((csect = ppc_get_csect_to_adjust (fix->fx_addsy)) != NULL) |
252b5132 | 6621 | { |
2fb4b302 TG |
6622 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6623 | fix->fx_addsy = csect; | |
c5df7e44 | 6624 | } |
252b5132 | 6625 | |
c5df7e44 CC |
6626 | if ((csect = ppc_get_csect_to_adjust (fix->fx_subsy)) != NULL) |
6627 | { | |
6628 | fix->fx_offset -= resolve_symbol_value (fix->fx_subsy) | |
6629 | - symbol_get_frag (csect)->fr_address; | |
6630 | fix->fx_subsy = csect; | |
252b5132 RH |
6631 | } |
6632 | ||
6633 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6634 | .lcomm. */ | |
b782de16 | 6635 | if (symseg == bss_section |
bcf84703 CC |
6636 | && ! S_IS_EXTERNAL (fix->fx_addsy) |
6637 | && symbol_get_tc (fix->fx_addsy)->subseg == 0) | |
252b5132 | 6638 | { |
b782de16 AM |
6639 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6640 | ||
6641 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6642 | fix->fx_addsy = sy; | |
252b5132 RH |
6643 | } |
6644 | ||
6645 | return 0; | |
6646 | } | |
6647 | ||
6648 | /* A reloc from one csect to another must be kept. The assembler | |
6649 | will, of course, keep relocs between sections, and it will keep | |
6650 | absolute relocs, but we need to force it to keep PC relative relocs | |
6651 | between two csects in the same section. */ | |
6652 | ||
6653 | int | |
98027b10 | 6654 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6655 | { |
6656 | /* At this point fix->fx_addsy should already have been converted to | |
6657 | a csect symbol. If the csect does not include the fragment, then | |
6658 | we need to force the relocation. */ | |
6659 | if (fix->fx_pcrel | |
6660 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6661 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6662 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6663 | > fix->fx_frag->fr_address) | |
6664 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6665 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6666 | <= fix->fx_frag->fr_address)))) |
6667 | return 1; | |
6668 | ||
ae6063d4 | 6669 | return generic_force_reloc (fix); |
252b5132 | 6670 | } |
252b5132 RH |
6671 | #endif /* OBJ_XCOFF */ |
6672 | ||
0baf16f2 | 6673 | #ifdef OBJ_ELF |
a161fe53 AM |
6674 | /* If this function returns non-zero, it guarantees that a relocation |
6675 | will be emitted for a fixup. */ | |
6676 | ||
6677 | int | |
98027b10 | 6678 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6679 | { |
6680 | /* Branch prediction relocations must force a relocation, as must | |
6681 | the vtable description relocs. */ | |
6682 | switch (fix->fx_r_type) | |
6683 | { | |
6684 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6685 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6686 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6687 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 6688 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 6689 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 6690 | return 1; |
6911b7dc AM |
6691 | case BFD_RELOC_PPC_B26: |
6692 | case BFD_RELOC_PPC_BA26: | |
6693 | case BFD_RELOC_PPC_B16: | |
6694 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 6695 | case BFD_RELOC_PPC64_REL24_NOTOC: |
7aba54da | 6696 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
6911b7dc AM |
6697 | /* All branch fixups targeting a localentry symbol must |
6698 | force a relocation. */ | |
6699 | if (fix->fx_addsy) | |
6700 | { | |
6701 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6702 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6703 | gas_assert (elfsym); |
6704 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6705 | return 1; | |
6706 | } | |
6707 | break; | |
a161fe53 AM |
6708 | default: |
6709 | break; | |
6710 | } | |
6711 | ||
cdba85ec | 6712 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6713 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
6714 | return 1; |
6715 | ||
ae6063d4 | 6716 | return generic_force_reloc (fix); |
a161fe53 AM |
6717 | } |
6718 | ||
0baf16f2 | 6719 | int |
98027b10 | 6720 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6721 | { |
6911b7dc AM |
6722 | switch (fix->fx_r_type) |
6723 | { | |
6724 | /* All branch fixups targeting a localentry symbol must | |
6725 | continue using the symbol. */ | |
6726 | case BFD_RELOC_PPC_B26: | |
6727 | case BFD_RELOC_PPC_BA26: | |
6728 | case BFD_RELOC_PPC_B16: | |
6729 | case BFD_RELOC_PPC_BA16: | |
6730 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6731 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6732 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6733 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 6734 | case BFD_RELOC_PPC64_REL24_NOTOC: |
7aba54da | 6735 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
6911b7dc AM |
6736 | if (fix->fx_addsy) |
6737 | { | |
6738 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6739 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6740 | gas_assert (elfsym); |
6741 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6742 | return 0; | |
6743 | } | |
6744 | break; | |
6745 | default: | |
6746 | break; | |
6747 | } | |
6748 | ||
0baf16f2 AM |
6749 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
6750 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
6751 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
6752 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
6753 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
6754 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
5663e321 | 6755 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
6756 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
6757 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
6758 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
6759 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
6760 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
6761 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
6762 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
6763 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
6764 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 6765 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
6766 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
6767 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
6768 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
6769 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
6770 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
6771 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 6772 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
6773 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
6774 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
6775 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
6776 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
6777 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 6778 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6779 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 6780 | } |
0baf16f2 | 6781 | #endif |
252b5132 | 6782 | |
b9c361e0 JL |
6783 | void |
6784 | ppc_frag_check (struct frag *fragP) | |
6785 | { | |
a9479dc0 AM |
6786 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
6787 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6788 | _("instruction address is not a multiple of %d"), | |
6789 | fragP->insn_addr + 1); | |
b9c361e0 JL |
6790 | } |
6791 | ||
22f72c48 AM |
6792 | /* rs_align_code frag handling. */ |
6793 | ||
6794 | enum ppc_nop_encoding_for_rs_align_code | |
6795 | { | |
6796 | PPC_NOP_VANILLA, | |
6797 | PPC_NOP_VLE, | |
6798 | PPC_NOP_GROUP_P6, | |
6799 | PPC_NOP_GROUP_P7 | |
6800 | }; | |
6801 | ||
6802 | unsigned int | |
6803 | ppc_nop_select (void) | |
6804 | { | |
6805 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
6806 | return PPC_NOP_VLE; | |
6807 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
6808 | { | |
6809 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
6810 | return PPC_NOP_GROUP_P7; | |
6811 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
6812 | return PPC_NOP_GROUP_P6; | |
6813 | } | |
6814 | return PPC_NOP_VANILLA; | |
6815 | } | |
3aeeedbb AM |
6816 | |
6817 | void | |
6818 | ppc_handle_align (struct frag *fragP) | |
6819 | { | |
6820 | valueT count = (fragP->fr_next->fr_address | |
6821 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
6822 | char *dest = fragP->fr_literal + fragP->fr_fix; |
6823 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
6824 | ||
6825 | /* Pad with zeros if not inserting a whole number of instructions. | |
6826 | We could pad with zeros up to an instruction boundary then follow | |
6827 | with nops but odd counts indicate data in an executable section | |
6828 | so padding with zeros is most appropriate. */ | |
6829 | if (count == 0 | |
de626965 | 6830 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
6831 | { |
6832 | *dest = 0; | |
6833 | return; | |
6834 | } | |
3aeeedbb | 6835 | |
22f72c48 | 6836 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 6837 | { |
b9c361e0 JL |
6838 | |
6839 | fragP->fr_var = 2; | |
6840 | md_number_to_chars (dest, 0x4400, 2); | |
6841 | } | |
22f72c48 | 6842 | else |
3aeeedbb | 6843 | { |
3aeeedbb | 6844 | fragP->fr_var = 4; |
cef4f754 AM |
6845 | |
6846 | if (count > 4 * nop_limit && count < 0x2000000) | |
6847 | { | |
6848 | struct frag *rest; | |
6849 | ||
6850 | /* Make a branch, then follow with nops. Insert another | |
6851 | frag to handle the nops. */ | |
6852 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
6853 | count -= 4; | |
6854 | if (count == 0) | |
6855 | return; | |
6856 | ||
6857 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6858 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
6859 | fragP->fr_next = rest; | |
6860 | fragP = rest; | |
6861 | rest->fr_address += rest->fr_fix + 4; | |
6862 | rest->fr_fix = 0; | |
6863 | /* If we leave the next frag as rs_align_code we'll come here | |
6864 | again, resulting in a bunch of branches rather than a | |
6865 | branch followed by nops. */ | |
6866 | rest->fr_type = rs_align; | |
6867 | dest = rest->fr_literal; | |
6868 | } | |
6869 | ||
3aeeedbb AM |
6870 | md_number_to_chars (dest, 0x60000000, 4); |
6871 | ||
22f72c48 | 6872 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 6873 | { |
3fea0c3b AM |
6874 | /* For power6, power7, and power8, we want the last nop to |
6875 | be a group terminating one. Do this by inserting an | |
6876 | rs_fill frag immediately after this one, with its address | |
6877 | set to the last nop location. This will automatically | |
6878 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
6879 | if (count > 4) |
6880 | { | |
6881 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6882 | ||
6883 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
6884 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
6885 | group_nop->fr_fix = 0; | |
6886 | group_nop->fr_offset = 1; | |
6887 | group_nop->fr_type = rs_fill; | |
6888 | fragP->fr_next = group_nop; | |
6889 | dest = group_nop->fr_literal; | |
6890 | } | |
6891 | ||
22f72c48 | 6892 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
6893 | /* power6 group terminating nop: "ori 1,1,0". */ |
6894 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
6895 | else |
6896 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
6897 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
6898 | } |
6899 | } | |
6900 | } | |
6901 | ||
252b5132 | 6902 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 6903 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 6904 | |
94f592af | 6905 | void |
62ebcb5c | 6906 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 6907 | { |
94f592af | 6908 | valueT value = * valP; |
5656a981 AM |
6909 | offsetT fieldval; |
6910 | const struct powerpc_operand *operand; | |
252b5132 RH |
6911 | |
6912 | #ifdef OBJ_ELF | |
94f592af | 6913 | if (fixP->fx_addsy != NULL) |
252b5132 | 6914 | { |
a161fe53 | 6915 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
6916 | if (fixP->fx_pcrel) |
6917 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
6918 | |
6919 | if (fixP->fx_addsy == abs_section_sym) | |
6920 | fixP->fx_done = 1; | |
252b5132 RH |
6921 | } |
6922 | else | |
94f592af | 6923 | fixP->fx_done = 1; |
252b5132 | 6924 | #else |
a161fe53 | 6925 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
6926 | the symbol values. If we are doing this relocation the code in |
6927 | write.c is going to call bfd_install_relocation, which is also | |
6928 | going to use the symbol value. That means that if the reloc is | |
6929 | fully resolved we want to use *valP since bfd_install_relocation is | |
6930 | not being used. | |
9f0eb232 RS |
6931 | However, if the reloc is not fully resolved we do not want to |
6932 | use *valP, and must use fx_offset instead. If the relocation | |
6933 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
6934 | to this new relocation value. */ | |
94f592af NC |
6935 | if (fixP->fx_addsy == (symbolS *) NULL) |
6936 | fixP->fx_done = 1; | |
6937 | ||
252b5132 | 6938 | else |
9f0eb232 RS |
6939 | { |
6940 | value = fixP->fx_offset; | |
6941 | if (fixP->fx_pcrel) | |
6942 | value -= md_pcrel_from_section (fixP, seg); | |
6943 | } | |
a161fe53 AM |
6944 | #endif |
6945 | ||
7ba71655 AM |
6946 | /* We are only able to convert some relocs to pc-relative. */ |
6947 | if (fixP->fx_pcrel) | |
6948 | { | |
6949 | switch (fixP->fx_r_type) | |
6950 | { | |
4a969973 AM |
6951 | case BFD_RELOC_64: |
6952 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6953 | break; | |
6954 | ||
6955 | case BFD_RELOC_32: | |
6956 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
6957 | break; | |
6958 | ||
6959 | case BFD_RELOC_16: | |
6960 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6961 | break; | |
6962 | ||
7ba71655 AM |
6963 | case BFD_RELOC_LO16: |
6964 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
6965 | break; | |
6966 | ||
6967 | case BFD_RELOC_HI16: | |
6968 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
6969 | break; | |
6970 | ||
6971 | case BFD_RELOC_HI16_S: | |
6972 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
6973 | break; | |
6974 | ||
4a969973 AM |
6975 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6976 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
6977 | break; |
6978 | ||
4a969973 AM |
6979 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
6980 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
6981 | break; |
6982 | ||
4a969973 AM |
6983 | case BFD_RELOC_PPC64_HIGHER: |
6984 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
6985 | break; | |
6986 | ||
6987 | case BFD_RELOC_PPC64_HIGHER_S: | |
6988 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
6989 | break; | |
6990 | ||
6991 | case BFD_RELOC_PPC64_HIGHEST: | |
6992 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
6993 | break; | |
6994 | ||
6995 | case BFD_RELOC_PPC64_HIGHEST_S: | |
6996 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
6997 | break; |
6998 | ||
5663e321 AM |
6999 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
7000 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
7001 | break; | |
7002 | ||
7003 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
7004 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
7005 | break; | |
7006 | ||
7007 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
7008 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
7009 | break; | |
7010 | ||
7011 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
7012 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
7013 | break; | |
7014 | ||
7ba71655 AM |
7015 | case BFD_RELOC_PPC_16DX_HA: |
7016 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7017 | break; | |
7018 | ||
5663e321 AM |
7019 | case BFD_RELOC_PPC64_D34: |
7020 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
7021 | break; | |
7022 | ||
7023 | case BFD_RELOC_PPC64_D28: | |
7024 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
7025 | break; | |
7026 | ||
7ba71655 AM |
7027 | default: |
7028 | break; | |
7029 | } | |
7030 | } | |
7031 | else if (!fixP->fx_done | |
7032 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 7033 | { |
7ba71655 AM |
7034 | /* addpcis is relative to next insn address. */ |
7035 | value -= 4; | |
7036 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7037 | fixP->fx_pcrel = 1; | |
252b5132 | 7038 | } |
252b5132 | 7039 | |
5656a981 | 7040 | operand = NULL; |
3b8b57a9 | 7041 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 7042 | { |
5656a981 | 7043 | /* This is a fixup on an instruction. */ |
8e5eb8e1 | 7044 | ppc_opindex_t opindex = fixP->fx_pcrel_adjust & PPC_OPINDEX_MAX; |
252b5132 | 7045 | |
5656a981 | 7046 | operand = &powerpc_operands[opindex]; |
252b5132 | 7047 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
7048 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
7049 | does not generate a reloc. It uses the offset of `sym' within its | |
7050 | csect. Other usages, such as `.long sym', generate relocs. This | |
7051 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 7052 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 7053 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 7054 | && operand->shift == 0 |
2b3c4602 | 7055 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
7056 | && fixP->fx_addsy != NULL |
7057 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
4a403be0 | 7058 | && !ppc_is_toc_sym (fixP->fx_addsy) |
94f592af | 7059 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 7060 | { |
94f592af NC |
7061 | value = fixP->fx_offset; |
7062 | fixP->fx_done = 1; | |
252b5132 | 7063 | } |
ac21e7da TG |
7064 | |
7065 | /* During parsing of instructions, a TOC16 reloc is generated for | |
7066 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
7067 | in the toc. But at parse time, SYM may be not yet defined, so | |
7068 | check again here. */ | |
7069 | if (fixP->fx_r_type == BFD_RELOC_16 | |
7070 | && fixP->fx_addsy != NULL | |
7071 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
4a403be0 | 7072 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; |
252b5132 | 7073 | #endif |
5656a981 AM |
7074 | } |
7075 | ||
7076 | /* Calculate value to be stored in field. */ | |
7077 | fieldval = value; | |
7078 | switch (fixP->fx_r_type) | |
7079 | { | |
1ec2d25e | 7080 | #ifdef OBJ_ELF |
5656a981 AM |
7081 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
7082 | case BFD_RELOC_PPC_VLE_LO16A: | |
7083 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 7084 | #endif |
5656a981 AM |
7085 | case BFD_RELOC_LO16: |
7086 | case BFD_RELOC_LO16_PCREL: | |
7087 | fieldval = value & 0xffff; | |
7088 | sign_extend_16: | |
7089 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 7090 | fieldval = SEX16 (fieldval); |
5656a981 AM |
7091 | fixP->fx_no_overflow = 1; |
7092 | break; | |
3c9d25f4 | 7093 | |
f9c6b907 AM |
7094 | case BFD_RELOC_HI16: |
7095 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 7096 | #ifdef OBJ_ELF |
f9c6b907 AM |
7097 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7098 | { | |
7099 | fieldval = value >> 16; | |
7100 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7101 | { | |
7102 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7103 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7104 | } | |
7105 | break; | |
7106 | } | |
2b0f3761 | 7107 | /* Fallthru */ |
f9c6b907 | 7108 | |
5656a981 AM |
7109 | case BFD_RELOC_PPC_VLE_HI16A: |
7110 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 7111 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 7112 | #endif |
5656a981 AM |
7113 | fieldval = PPC_HI (value); |
7114 | goto sign_extend_16; | |
0baf16f2 | 7115 | |
f9c6b907 AM |
7116 | case BFD_RELOC_HI16_S: |
7117 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 7118 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 7119 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 7120 | #ifdef OBJ_ELF |
f9c6b907 AM |
7121 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7122 | { | |
7123 | fieldval = (value + 0x8000) >> 16; | |
7124 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7125 | { | |
7126 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7127 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7128 | } | |
7129 | break; | |
7130 | } | |
2b0f3761 | 7131 | /* Fallthru */ |
f9c6b907 | 7132 | |
5656a981 AM |
7133 | case BFD_RELOC_PPC_VLE_HA16A: |
7134 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 7135 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 7136 | #endif |
5656a981 AM |
7137 | fieldval = PPC_HA (value); |
7138 | goto sign_extend_16; | |
0baf16f2 | 7139 | |
3b8b57a9 | 7140 | #ifdef OBJ_ELF |
5656a981 AM |
7141 | case BFD_RELOC_PPC64_HIGHER: |
7142 | fieldval = PPC_HIGHER (value); | |
7143 | goto sign_extend_16; | |
252b5132 | 7144 | |
5656a981 AM |
7145 | case BFD_RELOC_PPC64_HIGHER_S: |
7146 | fieldval = PPC_HIGHERA (value); | |
7147 | goto sign_extend_16; | |
0baf16f2 | 7148 | |
5656a981 AM |
7149 | case BFD_RELOC_PPC64_HIGHEST: |
7150 | fieldval = PPC_HIGHEST (value); | |
7151 | goto sign_extend_16; | |
0baf16f2 | 7152 | |
5656a981 AM |
7153 | case BFD_RELOC_PPC64_HIGHEST_S: |
7154 | fieldval = PPC_HIGHESTA (value); | |
7155 | goto sign_extend_16; | |
7156 | #endif | |
7157 | ||
7158 | default: | |
7159 | break; | |
7160 | } | |
7161 | ||
7162 | if (operand != NULL) | |
7163 | { | |
7164 | /* Handle relocs in an insn. */ | |
5656a981 AM |
7165 | switch (fixP->fx_r_type) |
7166 | { | |
7fa9fcb6 | 7167 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7168 | /* The following relocs can't be calculated by the assembler. |
7169 | Leave the field zero. */ | |
cdba85ec AM |
7170 | case BFD_RELOC_PPC_TPREL16: |
7171 | case BFD_RELOC_PPC_TPREL16_LO: | |
7172 | case BFD_RELOC_PPC_TPREL16_HI: | |
7173 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
7174 | case BFD_RELOC_PPC_DTPREL16: |
7175 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7176 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7177 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
7178 | case BFD_RELOC_PPC_GOT_TLSGD16: |
7179 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7180 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7181 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7182 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7183 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7184 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7185 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7186 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7187 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7188 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7189 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7190 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7191 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7192 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7193 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7194 | case BFD_RELOC_PPC64_TPREL16_DS: | |
7195 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
7196 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7197 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
7198 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7199 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7200 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7201 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
7202 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7203 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
7204 | case BFD_RELOC_PPC64_DTPREL16_DS: |
7205 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
7206 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
7207 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7208 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7209 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
7210 | case BFD_RELOC_PPC64_TPREL34: |
7211 | case BFD_RELOC_PPC64_DTPREL34: | |
87c69f97 AM |
7212 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
7213 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
7214 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
7215 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
3b8b57a9 | 7216 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 7217 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 7218 | fieldval = 0; |
cdba85ec | 7219 | break; |
3b8b57a9 AM |
7220 | |
7221 | /* These also should leave the field zero for the same | |
7222 | reason. Note that older versions of gas wrote values | |
7223 | here. If we want to go back to the old behaviour, then | |
7224 | all _LO and _LO_DS cases will need to be treated like | |
7225 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
7226 | case BFD_RELOC_16_GOTOFF: | |
7227 | case BFD_RELOC_LO16_GOTOFF: | |
7228 | case BFD_RELOC_HI16_GOTOFF: | |
7229 | case BFD_RELOC_HI16_S_GOTOFF: | |
7230 | case BFD_RELOC_LO16_PLTOFF: | |
7231 | case BFD_RELOC_HI16_PLTOFF: | |
7232 | case BFD_RELOC_HI16_S_PLTOFF: | |
7233 | case BFD_RELOC_GPREL16: | |
7234 | case BFD_RELOC_16_BASEREL: | |
7235 | case BFD_RELOC_LO16_BASEREL: | |
7236 | case BFD_RELOC_HI16_BASEREL: | |
7237 | case BFD_RELOC_HI16_S_BASEREL: | |
7238 | case BFD_RELOC_PPC_TOC16: | |
7239 | case BFD_RELOC_PPC64_TOC16_LO: | |
7240 | case BFD_RELOC_PPC64_TOC16_HI: | |
7241 | case BFD_RELOC_PPC64_TOC16_HA: | |
7242 | case BFD_RELOC_PPC64_PLTGOT16: | |
7243 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
7244 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
7245 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
7246 | case BFD_RELOC_PPC64_GOT16_DS: | |
7247 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
7248 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
7249 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
7250 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
7251 | case BFD_RELOC_PPC64_TOC16_DS: | |
7252 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
7253 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
7254 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
7255 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7256 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7257 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7258 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7259 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7260 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7261 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 7262 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
7263 | case BFD_RELOC_PPC_EMB_MRKREF: |
7264 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7265 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7266 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7267 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7268 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7269 | case BFD_RELOC_PPC_EMB_RELSDA: | |
7270 | case BFD_RELOC_PPC_VLE_SDA21: | |
7271 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7272 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7273 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
7274 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7275 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
7276 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7277 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
7278 | case BFD_RELOC_PPC64_GOT_PCREL34: |
7279 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 7280 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 7281 | /* Fallthru */ |
3b8b57a9 AM |
7282 | |
7283 | case BFD_RELOC_PPC_TLS: | |
7284 | case BFD_RELOC_PPC_TLSGD: | |
7285 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 7286 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 7287 | fieldval = 0; |
3b8b57a9 | 7288 | break; |
7fa9fcb6 TG |
7289 | #endif |
7290 | ||
7291 | #ifdef OBJ_XCOFF | |
7292 | case BFD_RELOC_PPC_B16: | |
7293 | /* Adjust the offset to the instruction boundary. */ | |
7294 | fieldval += 2; | |
7295 | break; | |
7296 | #endif | |
252b5132 | 7297 | |
f728387b AM |
7298 | case BFD_RELOC_VTABLE_INHERIT: |
7299 | case BFD_RELOC_VTABLE_ENTRY: | |
7300 | case BFD_RELOC_PPC_DTPMOD: | |
7301 | case BFD_RELOC_PPC_TPREL: | |
7302 | case BFD_RELOC_PPC_DTPREL: | |
7303 | case BFD_RELOC_PPC_COPY: | |
7304 | case BFD_RELOC_PPC_GLOB_DAT: | |
7305 | case BFD_RELOC_32_PLT_PCREL: | |
7306 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7307 | case BFD_RELOC_PPC64_TOC: | |
7308 | case BFD_RELOC_CTOR: | |
7309 | case BFD_RELOC_32: | |
7310 | case BFD_RELOC_32_PCREL: | |
7311 | case BFD_RELOC_RVA: | |
7312 | case BFD_RELOC_64: | |
7313 | case BFD_RELOC_64_PCREL: | |
7314 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7315 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7316 | _("%s unsupported as instruction fixup"), | |
7317 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7318 | fixP->fx_done = 1; | |
7319 | return; | |
7320 | ||
3b8b57a9 | 7321 | default: |
252b5132 | 7322 | break; |
3b8b57a9 | 7323 | } |
252b5132 | 7324 | |
3b8b57a9 AM |
7325 | #ifdef OBJ_ELF |
7326 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7327 | contents can stay at zero. */ | |
7328 | #define APPLY_RELOC fixP->fx_done | |
7329 | #else | |
7330 | #define APPLY_RELOC 1 | |
7331 | #endif | |
5663e321 AM |
7332 | /* We need to call the insert function even when fieldval is |
7333 | zero if the insert function would translate that zero to a | |
7334 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
7335 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
7336 | { | |
5663e321 | 7337 | uint64_t insn; |
487b24d8 AM |
7338 | unsigned char *where; |
7339 | ||
3b8b57a9 AM |
7340 | /* Fetch the instruction, insert the fully resolved operand |
7341 | value, and stuff the instruction back again. */ | |
487b24d8 | 7342 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7343 | if (target_big_endian) |
31a91399 | 7344 | { |
5663e321 | 7345 | if (fixP->fx_size < 4) |
487b24d8 | 7346 | insn = bfd_getb16 (where); |
5663e321 AM |
7347 | else |
7348 | { | |
7349 | insn = bfd_getb32 (where); | |
7350 | if (fixP->fx_size > 4) | |
7351 | insn = insn << 32 | bfd_getb32 (where + 4); | |
7352 | } | |
31a91399 NC |
7353 | } |
7354 | else | |
3b8b57a9 | 7355 | { |
5663e321 | 7356 | if (fixP->fx_size < 4) |
487b24d8 | 7357 | insn = bfd_getl16 (where); |
5663e321 AM |
7358 | else |
7359 | { | |
7360 | insn = bfd_getl32 (where); | |
7361 | if (fixP->fx_size > 4) | |
7362 | insn = insn << 32 | bfd_getl32 (where + 4); | |
7363 | } | |
3b8b57a9 AM |
7364 | } |
7365 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7366 | fixP->tc_fix_data.ppc_cpu, | |
7367 | fixP->fx_file, fixP->fx_line); | |
7368 | if (target_big_endian) | |
7369 | { | |
5663e321 | 7370 | if (fixP->fx_size < 4) |
487b24d8 | 7371 | bfd_putb16 (insn, where); |
5663e321 AM |
7372 | else |
7373 | { | |
7374 | if (fixP->fx_size > 4) | |
7375 | { | |
7376 | bfd_putb32 (insn, where + 4); | |
7377 | insn >>= 32; | |
7378 | } | |
7379 | bfd_putb32 (insn, where); | |
7380 | } | |
3b8b57a9 AM |
7381 | } |
7382 | else | |
7383 | { | |
5663e321 | 7384 | if (fixP->fx_size < 4) |
487b24d8 | 7385 | bfd_putl16 (insn, where); |
5663e321 AM |
7386 | else |
7387 | { | |
7388 | if (fixP->fx_size > 4) | |
7389 | { | |
7390 | bfd_putl32 (insn, where + 4); | |
7391 | insn >>= 32; | |
7392 | } | |
7393 | bfd_putl32 (insn, where); | |
7394 | } | |
3b8b57a9 AM |
7395 | } |
7396 | } | |
7397 | ||
7398 | if (fixP->fx_done) | |
7399 | /* Nothing else to do here. */ | |
7400 | return; | |
7401 | ||
7402 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7403 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7404 | { |
3b4dbbbf | 7405 | const char *sfile; |
3b8b57a9 AM |
7406 | unsigned int sline; |
7407 | ||
7408 | /* Use expr_symbol_where to see if this is an expression | |
7409 | symbol. */ | |
7410 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7411 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7412 | _("unresolved expression that must be resolved")); | |
7413 | else | |
7414 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7415 | _("unsupported relocation against %s"), | |
7416 | S_GET_NAME (fixP->fx_addsy)); | |
7417 | fixP->fx_done = 1; | |
7418 | return; | |
7419 | } | |
7420 | } | |
7421 | else | |
7422 | { | |
7423 | /* Handle relocs in data. */ | |
7424 | switch (fixP->fx_r_type) | |
7425 | { | |
252b5132 | 7426 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7427 | if (fixP->fx_addsy |
7428 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7429 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7430 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7431 | /* Fallthru */ |
252b5132 RH |
7432 | |
7433 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7434 | fixP->fx_done = 0; |
252b5132 RH |
7435 | break; |
7436 | ||
0baf16f2 | 7437 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7438 | /* These can appear with @l etc. in data. */ |
7439 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7440 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7441 | case BFD_RELOC_HI16: |
3b8b57a9 | 7442 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7443 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7444 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7445 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7446 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7447 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7448 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7449 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7450 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7451 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7452 | break; |
7453 | ||
7454 | case BFD_RELOC_PPC_DTPMOD: | |
7455 | case BFD_RELOC_PPC_TPREL: | |
7456 | case BFD_RELOC_PPC_DTPREL: | |
7457 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7458 | break; | |
7459 | ||
7460 | /* Just punt all of these to the linker. */ | |
7461 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7462 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7463 | case BFD_RELOC_16_GOTOFF: | |
7464 | case BFD_RELOC_LO16_GOTOFF: | |
7465 | case BFD_RELOC_HI16_GOTOFF: | |
7466 | case BFD_RELOC_HI16_S_GOTOFF: | |
7467 | case BFD_RELOC_LO16_PLTOFF: | |
7468 | case BFD_RELOC_HI16_PLTOFF: | |
7469 | case BFD_RELOC_HI16_S_PLTOFF: | |
7470 | case BFD_RELOC_PPC_COPY: | |
7471 | case BFD_RELOC_PPC_GLOB_DAT: | |
7472 | case BFD_RELOC_16_BASEREL: | |
7473 | case BFD_RELOC_LO16_BASEREL: | |
7474 | case BFD_RELOC_HI16_BASEREL: | |
7475 | case BFD_RELOC_HI16_S_BASEREL: | |
7476 | case BFD_RELOC_PPC_TLS: | |
7477 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7478 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7479 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7480 | case BFD_RELOC_PPC_TPREL16_LO: | |
7481 | case BFD_RELOC_PPC_TPREL16_HI: | |
7482 | case BFD_RELOC_PPC_TPREL16_HA: | |
7483 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7484 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7485 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7486 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7487 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7488 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7489 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7490 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7491 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7492 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7493 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7494 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7495 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7496 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7497 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7498 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7499 | case BFD_RELOC_24_PLT_PCREL: | |
7500 | case BFD_RELOC_PPC_LOCAL24PC: | |
7501 | case BFD_RELOC_32_PLT_PCREL: | |
7502 | case BFD_RELOC_GPREL16: | |
7503 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7504 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7505 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7506 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7507 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7508 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7509 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7510 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7511 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7512 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7513 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7514 | case BFD_RELOC_PPC_EMB_SDA21: | |
7515 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7516 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7517 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7518 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7519 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7520 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7521 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7522 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7523 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 | 7524 | case BFD_RELOC_PPC_TOC16: |
4a403be0 CC |
7525 | case BFD_RELOC_PPC_TOC16_LO: |
7526 | case BFD_RELOC_PPC_TOC16_HI: | |
3b8b57a9 AM |
7527 | case BFD_RELOC_PPC64_TOC16_LO: |
7528 | case BFD_RELOC_PPC64_TOC16_HI: | |
7529 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7530 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7531 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7532 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7533 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7534 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7535 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7536 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7537 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7538 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7539 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7540 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7541 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7542 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7543 | fixP->fx_done = 0; |
0baf16f2 | 7544 | break; |
0baf16f2 | 7545 | #endif |
3b8b57a9 AM |
7546 | |
7547 | #ifdef OBJ_XCOFF | |
1b2cb8e2 CC |
7548 | case BFD_RELOC_PPC_TLSGD: |
7549 | case BFD_RELOC_PPC_TLSLD: | |
7550 | case BFD_RELOC_PPC_TLSLE: | |
7551 | case BFD_RELOC_PPC_TLSIE: | |
7552 | case BFD_RELOC_PPC_TLSM: | |
7553 | case BFD_RELOC_PPC64_TLSGD: | |
7554 | case BFD_RELOC_PPC64_TLSLD: | |
7555 | case BFD_RELOC_PPC64_TLSLE: | |
7556 | case BFD_RELOC_PPC64_TLSIE: | |
7557 | case BFD_RELOC_PPC64_TLSM: | |
7558 | gas_assert (fixP->fx_addsy != NULL); | |
7559 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
1b2cb8e2 CC |
7560 | break; |
7561 | ||
3c503824 CC |
7562 | /* Officially, R_TLSML relocations must be from a TOC entry |
7563 | targeting itself. In practice, this TOC entry is always | |
7564 | named (or .rename) "_$TLSML". | |
7565 | Thus, as it doesn't seem possible to retrieve the symbol | |
7566 | being relocated here, we simply check that the symbol | |
7567 | targeted by R_TLSML is indeed a TOC entry named "_$TLSML". | |
7568 | FIXME: Find a way to correctly check R_TLSML relocations | |
7569 | as described above. */ | |
1b2cb8e2 CC |
7570 | case BFD_RELOC_PPC_TLSML: |
7571 | case BFD_RELOC_PPC64_TLSML: | |
7572 | gas_assert (fixP->fx_addsy != NULL); | |
3c503824 CC |
7573 | if ((symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC |
7574 | || symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TE) | |
7575 | && strcmp (symbol_get_tc (fixP->fx_addsy)->real_name, "_$TLSML") != 0) | |
7576 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7577 | _("R_TLSML relocation doesn't target a " | |
7578 | "TOC entry named \"_$TLSML\": %s"), S_GET_NAME(fixP->fx_addsy)); | |
1b2cb8e2 CC |
7579 | fieldval = 0; |
7580 | break; | |
7581 | ||
3b8b57a9 | 7582 | case BFD_RELOC_NONE: |
3b8b57a9 | 7583 | #endif |
5656a981 AM |
7584 | case BFD_RELOC_CTOR: |
7585 | case BFD_RELOC_32: | |
7586 | case BFD_RELOC_32_PCREL: | |
7587 | case BFD_RELOC_RVA: | |
7588 | case BFD_RELOC_64: | |
7589 | case BFD_RELOC_64_PCREL: | |
7590 | case BFD_RELOC_16: | |
7591 | case BFD_RELOC_16_PCREL: | |
7592 | case BFD_RELOC_8: | |
7593 | break; | |
3b8b57a9 | 7594 | |
252b5132 | 7595 | default: |
bc805888 | 7596 | fprintf (stderr, |
94f592af | 7597 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7598 | fflush (stderr); |
252b5132 RH |
7599 | abort (); |
7600 | } | |
46b596ff | 7601 | |
5656a981 | 7602 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7603 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7604 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7605 | if (warn_476 |
7606 | && (seg->flags & SEC_CODE) != 0 | |
7607 | && fixP->fx_size == 4 | |
7608 | && fixP->fx_done | |
7609 | && !fixP->fx_tcbit | |
7610 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7611 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7612 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7613 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7614 | _("data in executable section")); | |
5656a981 AM |
7615 | } |
7616 | ||
252b5132 | 7617 | #ifdef OBJ_ELF |
3b8b57a9 | 7618 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7619 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7620 | |
7621 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7622 | from the section contents. If we are going to be emitting a reloc | |
7623 | then the section contents are immaterial, so don't warn if they | |
7624 | happen to overflow. Leave such warnings to ld. */ | |
7625 | if (!fixP->fx_done) | |
a38a07e0 AM |
7626 | { |
7627 | fixP->fx_no_overflow = 1; | |
7628 | ||
7629 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7630 | but .TOC.@tocbase. */ | |
7631 | if (ppc_obj64 | |
7632 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7633 | && fixP->fx_addsy != NULL | |
7634 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7635 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7636 | } | |
252b5132 | 7637 | #else |
3478a63d CC |
7638 | if (fixP->fx_r_type == BFD_RELOC_PPC_TOC16 |
7639 | || fixP->fx_r_type == BFD_RELOC_PPC_TOC16_HI | |
7640 | || fixP->fx_r_type == BFD_RELOC_PPC_TOC16_LO) | |
252b5132 | 7641 | { |
8edcbfcd TG |
7642 | /* We want to use the offset within the toc, not the actual VMA |
7643 | of the symbol. */ | |
fd361982 AM |
7644 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7645 | - S_GET_VALUE (ppc_toc_csect)); | |
4a403be0 CC |
7646 | |
7647 | /* The high bits must be adjusted for the low bits being signed. */ | |
7648 | if (fixP->fx_r_type == BFD_RELOC_PPC_TOC16_HI) { | |
7649 | fixP->fx_addnumber += 0x8000; | |
7650 | } | |
7651 | ||
ac21e7da TG |
7652 | /* Set *valP to avoid errors. */ |
7653 | *valP = value; | |
252b5132 | 7654 | } |
3478a63d | 7655 | else if (fixP->fx_r_type == BFD_RELOC_PPC_TLSM |
3c503824 CC |
7656 | || fixP->fx_r_type == BFD_RELOC_PPC64_TLSM |
7657 | || fixP->fx_r_type == BFD_RELOC_PPC_TLSML | |
7658 | || fixP->fx_r_type == BFD_RELOC_PPC64_TLSML) | |
3478a63d CC |
7659 | /* AIX ld expects the section contents for these relocations |
7660 | to be zero. Arrange for that to occur when | |
7661 | bfd_install_relocation is called. */ | |
7662 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) | |
3c503824 CC |
7663 | - S_GET_VALUE (fixP->fx_addsy) |
7664 | - fieldval); | |
3478a63d CC |
7665 | else |
7666 | fixP->fx_addnumber = 0; | |
252b5132 | 7667 | #endif |
252b5132 RH |
7668 | } |
7669 | ||
7670 | /* Generate a reloc for a fixup. */ | |
7671 | ||
c5df7e44 | 7672 | arelent ** |
98027b10 | 7673 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 | 7674 | { |
c5df7e44 | 7675 | static arelent *relocs[3]; |
252b5132 RH |
7676 | arelent *reloc; |
7677 | ||
c5df7e44 CC |
7678 | relocs[0] = reloc = XNEW (arelent); |
7679 | relocs[1] = NULL; | |
252b5132 | 7680 | |
325801bd | 7681 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7682 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7683 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7684 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7685 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7686 | reloc->address++; | |
252b5132 RH |
7687 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7688 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7689 | { | |
7690 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7691 | _("reloc %d not supported by object file format"), |
7692 | (int) fixp->fx_r_type); | |
c5df7e44 | 7693 | relocs[0] = NULL; |
252b5132 RH |
7694 | } |
7695 | reloc->addend = fixp->fx_addnumber; | |
7696 | ||
4bf09429 | 7697 | if (fixp->fx_subsy != NULL) |
c5df7e44 CC |
7698 | { |
7699 | relocs[1] = reloc = XNEW (arelent); | |
7700 | relocs[2] = NULL; | |
7701 | ||
7702 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
7703 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); | |
7704 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7705 | ||
7706 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_PPC_NEG); | |
7707 | reloc->addend = fixp->fx_addnumber; | |
7708 | ||
7709 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7710 | { | |
4bf09429 AM |
7711 | as_bad_subtract (fixp); |
7712 | free (relocs[1]->sym_ptr_ptr); | |
7713 | free (relocs[1]); | |
7714 | free (relocs[0]->sym_ptr_ptr); | |
7715 | free (relocs[0]); | |
c5df7e44 CC |
7716 | relocs[0] = NULL; |
7717 | } | |
7718 | } | |
7719 | ||
7720 | ||
7721 | return relocs; | |
252b5132 | 7722 | } |
75e21f08 JJ |
7723 | |
7724 | void | |
98027b10 | 7725 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7726 | { |
7727 | cfi_add_CFA_def_cfa (1, 0); | |
7728 | } | |
7729 | ||
7730 | int | |
1df69f4f | 7731 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7732 | { |
7733 | unsigned int regnum = -1; | |
7734 | unsigned int i; | |
7735 | const char *p; | |
7736 | char *q; | |
e0471c16 | 7737 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7738 | { |
7739 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7740 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7741 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7742 | { "spe_acc", 111 }, { "spefscr", 112 } |
7743 | }; | |
7744 | ||
7745 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7746 | if (strcmp (regnames[i].name, regname) == 0) | |
7747 | return regnames[i].dw2regnum; | |
7748 | ||
7749 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7750 | { | |
7751 | p = regname + 1 + (regname[1] == '.'); | |
7752 | regnum = strtoul (p, &q, 10); | |
7753 | if (p == q || *q || regnum >= 32) | |
7754 | return -1; | |
7755 | if (regname[0] == 'f') | |
b7d7dc63 | 7756 | regnum += 32; |
75e21f08 | 7757 | else if (regname[0] == 'v') |
b7d7dc63 | 7758 | regnum += 77; |
75e21f08 JJ |
7759 | } |
7760 | else if (regname[0] == 'c' && regname[1] == 'r') | |
7761 | { | |
7762 | p = regname + 2 + (regname[2] == '.'); | |
7763 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 7764 | return -1; |
75e21f08 JJ |
7765 | regnum = p[0] - '0' + 68; |
7766 | } | |
7767 | return regnum; | |
7768 | } |