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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
d87bef3a | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
1080bf78 | 32 | #include "bfd/elfxx-riscv.h" |
e23eba97 NC |
33 | #include "elf/riscv.h" |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
634001bb TO |
45 | /* The encoded instruction bits |
46 | (first bits enough to extract instruction length on a long opcode). */ | |
e23eba97 NC |
47 | insn_t insn_opcode; |
48 | ||
634001bb TO |
49 | /* The long encoded instruction bits ([0] is non-zero on a long opcode). */ |
50 | char insn_long_opcode[RISCV_MAX_INSN_LEN]; | |
51 | ||
e23eba97 NC |
52 | /* The frag that contains the instruction. */ |
53 | struct frag *frag; | |
54 | ||
55 | /* The offset into FRAG of the first instruction byte. */ | |
56 | long where; | |
57 | ||
58 | /* The relocs associated with the instruction, if any. */ | |
59 | fixS *fixp; | |
60 | }; | |
61 | ||
3d73d29e NC |
62 | /* All RISC-V CSR belong to one of these classes. */ |
63 | enum riscv_csr_class | |
64 | { | |
65 | CSR_CLASS_NONE, | |
66 | ||
67 | CSR_CLASS_I, | |
65e4a99a NC |
68 | CSR_CLASS_I_32, /* rv32 only */ |
69 | CSR_CLASS_F, /* f-ext only */ | |
70 | CSR_CLASS_ZKR, /* zkr only */ | |
71 | CSR_CLASS_V, /* rvv only */ | |
c625f4ed NC |
72 | CSR_CLASS_DEBUG, /* debug CSR */ |
73 | CSR_CLASS_H, /* hypervisor */ | |
74 | CSR_CLASS_H_32, /* hypervisor, rv32 only */ | |
ac8df5a1 CM |
75 | CSR_CLASS_SMAIA, /* Smaia */ |
76 | CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ | |
a303646f TO |
77 | CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ |
78 | CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ | |
6af47b08 | 79 | CSR_CLASS_SMSTATEEN, /* Smstateen only */ |
6af47b08 | 80 | CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ |
ac8df5a1 CM |
81 | CSR_CLASS_SSAIA, /* Ssaia */ |
82 | CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ | |
83 | CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ | |
84 | CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ | |
15253318 TO |
85 | CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ |
86 | CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ | |
87 | CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ | |
713f3708 TO |
88 | CSR_CLASS_SSCOFPMF, /* Sscofpmf only */ |
89 | CSR_CLASS_SSCOFPMF_32, /* Sscofpmf RV32 only */ | |
766077c1 TO |
90 | CSR_CLASS_SSTC, /* Sstc only */ |
91 | CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ | |
92 | CSR_CLASS_SSTC_32, /* Sstc RV32 only */ | |
93 | CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ | |
6fdd02bb | 94 | CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */ |
3d73d29e NC |
95 | }; |
96 | ||
97 | /* This structure holds all restricted conditions for a CSR. */ | |
98 | struct riscv_csr_extra | |
99 | { | |
100 | /* Class to which this CSR belongs. Used to decide whether or | |
101 | not this CSR is legal in the current -march context. */ | |
102 | enum riscv_csr_class csr_class; | |
103 | ||
104 | /* CSR may have differnet numbers in the previous priv spec. */ | |
105 | unsigned address; | |
106 | ||
107 | /* Record the CSR is defined/valid in which versions. */ | |
108 | enum riscv_spec_class define_version; | |
109 | ||
110 | /* Record the CSR is aborted/invalid from which versions. If it isn't | |
a63375ac | 111 | aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */ |
3d73d29e NC |
112 | enum riscv_spec_class abort_version; |
113 | ||
114 | /* The CSR may have more than one setting. */ | |
115 | struct riscv_csr_extra *next; | |
116 | }; | |
117 | ||
e4028336 PN |
118 | /* This structure contains information about errors that occur within the |
119 | riscv_ip function */ | |
120 | struct riscv_ip_error | |
121 | { | |
122 | /* General error message */ | |
123 | const char* msg; | |
124 | ||
125 | /* Statement that caused the error */ | |
126 | char* statement; | |
127 | ||
128 | /* Missing extension that needs to be enabled */ | |
129 | const char* missing_ext; | |
130 | }; | |
131 | ||
e23eba97 NC |
132 | #ifndef DEFAULT_ARCH |
133 | #define DEFAULT_ARCH "riscv64" | |
134 | #endif | |
135 | ||
2dc8dd17 JW |
136 | #ifndef DEFAULT_RISCV_ATTR |
137 | #define DEFAULT_RISCV_ATTR 0 | |
138 | #endif | |
139 | ||
8f595e9b | 140 | /* Let riscv_after_parse_args set the default value according to xlen. */ |
8f595e9b NC |
141 | #ifndef DEFAULT_RISCV_ARCH_WITH_EXT |
142 | #define DEFAULT_RISCV_ARCH_WITH_EXT NULL | |
143 | #endif | |
144 | ||
dcd709e0 | 145 | /* Need to sync the version with RISC-V compiler. */ |
8f595e9b | 146 | #ifndef DEFAULT_RISCV_ISA_SPEC |
aed44286 | 147 | #define DEFAULT_RISCV_ISA_SPEC "20191213" |
8f595e9b NC |
148 | #endif |
149 | ||
150 | #ifndef DEFAULT_RISCV_PRIV_SPEC | |
151 | #define DEFAULT_RISCV_PRIV_SPEC "1.11" | |
152 | #endif | |
153 | ||
e23eba97 | 154 | static const char default_arch[] = DEFAULT_ARCH; |
8f595e9b | 155 | static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT; |
3d73d29e NC |
156 | static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE; |
157 | static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; | |
e23eba97 | 158 | |
dcd709e0 NC |
159 | static unsigned xlen = 0; /* The width of an x-register. */ |
160 | static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */ | |
5b7c81bd | 161 | static bool rve_abi = false; |
1942a048 NC |
162 | enum float_abi |
163 | { | |
6e1605e4 NC |
164 | FLOAT_ABI_DEFAULT = -1, |
165 | FLOAT_ABI_SOFT, | |
166 | FLOAT_ABI_SINGLE, | |
167 | FLOAT_ABI_DOUBLE, | |
168 | FLOAT_ABI_QUAD | |
169 | }; | |
170 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; | |
e23eba97 | 171 | |
2922d21d | 172 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
173 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
174 | ||
175 | static unsigned elf_flags = 0; | |
176 | ||
7a29ee29 JB |
177 | static bool probing_insn_operands; |
178 | ||
dcd709e0 NC |
179 | /* Set the default_isa_spec. Return 0 if the spec isn't supported. |
180 | Otherwise, return 1. */ | |
8f595e9b NC |
181 | |
182 | static int | |
183 | riscv_set_default_isa_spec (const char *s) | |
184 | { | |
3d73d29e NC |
185 | enum riscv_spec_class class = ISA_SPEC_CLASS_NONE; |
186 | RISCV_GET_ISA_SPEC_CLASS (s, class); | |
187 | if (class == ISA_SPEC_CLASS_NONE) | |
8f595e9b | 188 | { |
b800637e NC |
189 | as_bad ("unknown default ISA spec `%s' set by " |
190 | "-misa-spec or --with-isa-spec", s); | |
8f595e9b NC |
191 | return 0; |
192 | } | |
193 | else | |
194 | default_isa_spec = class; | |
195 | return 1; | |
196 | } | |
197 | ||
dcd709e0 NC |
198 | /* Set the default_priv_spec. Find the privileged elf attributes when |
199 | the input string is NULL. Return 0 if the spec isn't supported. | |
200 | Otherwise, return 1. */ | |
8f595e9b NC |
201 | |
202 | static int | |
203 | riscv_set_default_priv_spec (const char *s) | |
204 | { | |
3d73d29e | 205 | enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE; |
8f595e9b NC |
206 | unsigned major, minor, revision; |
207 | obj_attribute *attr; | |
8f595e9b | 208 | |
3d73d29e NC |
209 | RISCV_GET_PRIV_SPEC_CLASS (s, class); |
210 | if (class != PRIV_SPEC_CLASS_NONE) | |
8f595e9b NC |
211 | { |
212 | default_priv_spec = class; | |
213 | return 1; | |
214 | } | |
215 | ||
216 | if (s != NULL) | |
217 | { | |
b800637e NC |
218 | as_bad (_("unknown default privileged spec `%s' set by " |
219 | "-mpriv-spec or --with-priv-spec"), s); | |
8f595e9b NC |
220 | return 0; |
221 | } | |
222 | ||
dcd709e0 | 223 | /* Set the default_priv_spec by the privileged elf attributes. */ |
8f595e9b NC |
224 | attr = elf_known_obj_attributes_proc (stdoutput); |
225 | major = (unsigned) attr[Tag_RISCV_priv_spec].i; | |
226 | minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i; | |
227 | revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i; | |
3d73d29e NC |
228 | /* Version 0.0.0 is the default value and meningless. */ |
229 | if (major == 0 && minor == 0 && revision == 0) | |
230 | return 1; | |
8f595e9b | 231 | |
3d73d29e NC |
232 | riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class); |
233 | if (class != PRIV_SPEC_CLASS_NONE) | |
234 | { | |
8f595e9b | 235 | default_priv_spec = class; |
8f595e9b NC |
236 | return 1; |
237 | } | |
238 | ||
dcd709e0 | 239 | /* Still can not find the privileged spec class. */ |
b800637e NC |
240 | as_bad (_("unknown default privileged spec `%d.%d.%d' set by " |
241 | "privileged elf attributes"), major, minor, revision); | |
8f595e9b NC |
242 | return 0; |
243 | } | |
244 | ||
e23eba97 | 245 | /* This is the set of options which the .option pseudo-op may modify. */ |
e23eba97 NC |
246 | struct riscv_set_options |
247 | { | |
248 | int pic; /* Generate position-independent code. */ | |
249 | int rvc; /* Generate RVC code. */ | |
45f76423 | 250 | int relax; /* Emit relocs the linker is allowed to relax. */ |
dcd709e0 | 251 | int arch_attr; /* Emit architecture and privileged elf attributes. */ |
2ca89224 | 252 | int csr_check; /* Enable the CSR checking. */ |
e23eba97 NC |
253 | }; |
254 | ||
255 | static struct riscv_set_options riscv_opts = | |
256 | { | |
dcd709e0 NC |
257 | 0, /* pic */ |
258 | 0, /* rvc */ | |
dcd709e0 | 259 | 1, /* relax */ |
2dc8dd17 | 260 | DEFAULT_RISCV_ATTR, /* arch_attr */ |
dcd709e0 | 261 | 0, /* csr_check */ |
e23eba97 NC |
262 | }; |
263 | ||
437e2ff1 NC |
264 | /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag |
265 | for elf_flags once we have enabled c extension. */ | |
266 | ||
e23eba97 | 267 | static void |
5b7c81bd | 268 | riscv_set_rvc (bool rvc_value) |
e23eba97 NC |
269 | { |
270 | if (rvc_value) | |
271 | elf_flags |= EF_RISCV_RVC; | |
272 | ||
273 | riscv_opts.rvc = rvc_value; | |
274 | } | |
275 | ||
96462b01 S |
276 | /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */ |
277 | ||
278 | static void | |
0242db99 | 279 | riscv_set_tso (void) |
96462b01 S |
280 | { |
281 | elf_flags |= EF_RISCV_TSO; | |
282 | } | |
283 | ||
f5cb31a8 JB |
284 | /* The linked list hanging off of .subsets_list records all enabled extensions, |
285 | which are parsed from the architecture string. The architecture string can | |
286 | be set by the -march option, the elf architecture attributes, and the | |
287 | --with-arch configure option. */ | |
f786c359 | 288 | static riscv_parse_subset_t riscv_rps_as = |
43135d3b | 289 | { |
d3ffd7f7 NC |
290 | NULL, /* subset_list, we will set it later once |
291 | riscv_opts_stack is created or updated. */ | |
f786c359 NC |
292 | as_bad, /* error_handler. */ |
293 | &xlen, /* xlen. */ | |
294 | &default_isa_spec, /* isa_spec. */ | |
295 | true, /* check_unknown_prefixed_ext. */ | |
296 | }; | |
43135d3b | 297 | |
40f1a1a4 NC |
298 | /* Update the architecture string in the subset_list. */ |
299 | ||
300 | static void | |
301 | riscv_reset_subsets_list_arch_str (void) | |
302 | { | |
303 | riscv_subset_list_t *subsets = riscv_rps_as.subset_list; | |
304 | if (subsets->arch_str != NULL) | |
305 | free ((void *) subsets->arch_str); | |
306 | subsets->arch_str = riscv_arch_str (xlen, subsets); | |
307 | } | |
308 | ||
d3ffd7f7 NC |
309 | /* This structure is used to hold a stack of .option values. */ |
310 | struct riscv_option_stack | |
311 | { | |
312 | struct riscv_option_stack *next; | |
313 | struct riscv_set_options options; | |
314 | riscv_subset_list_t *subset_list; | |
315 | }; | |
316 | ||
317 | static struct riscv_option_stack *riscv_opts_stack = NULL; | |
318 | ||
2922d21d | 319 | /* Set which ISA and extensions are available. */ |
e23eba97 | 320 | |
e23eba97 | 321 | static void |
2922d21d | 322 | riscv_set_arch (const char *s) |
e23eba97 | 323 | { |
c9f27991 NC |
324 | if (s != NULL && strcmp (s, "") == 0) |
325 | { | |
326 | as_bad (_("the architecture string of -march and elf architecture " | |
327 | "attributes cannot be empty")); | |
328 | return; | |
329 | } | |
7f999549 | 330 | |
f5cb31a8 | 331 | if (riscv_rps_as.subset_list == NULL) |
d3ffd7f7 | 332 | { |
f5cb31a8 JB |
333 | riscv_rps_as.subset_list = XNEW (riscv_subset_list_t); |
334 | riscv_rps_as.subset_list->head = NULL; | |
335 | riscv_rps_as.subset_list->tail = NULL; | |
40f1a1a4 | 336 | riscv_rps_as.subset_list->arch_str = NULL; |
d3ffd7f7 | 337 | } |
f5cb31a8 | 338 | riscv_release_subset_list (riscv_rps_as.subset_list); |
f786c359 | 339 | riscv_parse_subset (&riscv_rps_as, s); |
40f1a1a4 | 340 | riscv_reset_subsets_list_arch_str (); |
28b2963f | 341 | |
28b2963f | 342 | riscv_set_rvc (false); |
b5c37946 SJ |
343 | if (riscv_subset_supports (&riscv_rps_as, "c") |
344 | || riscv_subset_supports (&riscv_rps_as, "zca")) | |
28b2963f | 345 | riscv_set_rvc (true); |
96462b01 S |
346 | |
347 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
348 | riscv_set_tso (); | |
e23eba97 NC |
349 | } |
350 | ||
dcd709e0 | 351 | /* Indicate -mabi option is explictly set. */ |
5b7c81bd | 352 | static bool explicit_mabi = false; |
6e1605e4 | 353 | |
437e2ff1 NC |
354 | /* Set the abi information. */ |
355 | ||
6e1605e4 | 356 | static void |
5b7c81bd | 357 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve) |
6e1605e4 NC |
358 | { |
359 | abi_xlen = new_xlen; | |
360 | float_abi = new_float_abi; | |
361 | rve_abi = rve; | |
362 | } | |
363 | ||
dcd709e0 NC |
364 | /* If the -mabi option isn't set, then set the abi according to the |
365 | ISA string. Otherwise, check if there is any conflict. */ | |
6e1605e4 NC |
366 | |
367 | static void | |
368 | riscv_set_abi_by_arch (void) | |
369 | { | |
370 | if (!explicit_mabi) | |
371 | { | |
f786c359 | 372 | if (riscv_subset_supports (&riscv_rps_as, "q")) |
5b7c81bd | 373 | riscv_set_abi (xlen, FLOAT_ABI_QUAD, false); |
f786c359 | 374 | else if (riscv_subset_supports (&riscv_rps_as, "d")) |
5b7c81bd | 375 | riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false); |
f786c359 | 376 | else if (riscv_subset_supports (&riscv_rps_as, "e")) |
5d0ed830 | 377 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, true); |
6e1605e4 | 378 | else |
5b7c81bd | 379 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, false); |
6e1605e4 NC |
380 | } |
381 | else | |
382 | { | |
383 | gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT); | |
384 | if (abi_xlen > xlen) | |
385 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
386 | else if (abi_xlen < xlen) | |
387 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
5d0ed830 | 388 | |
f786c359 | 389 | if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) |
6674b23f | 390 | as_bad ("only ilp32e/lp64e ABI are supported for e extension"); |
5d0ed830 NC |
391 | |
392 | if (float_abi == FLOAT_ABI_SINGLE | |
f786c359 | 393 | && !riscv_subset_supports (&riscv_rps_as, "f")) |
5d0ed830 NC |
394 | as_bad ("ilp32f/lp64f ABI can't be used when f extension " |
395 | "isn't supported"); | |
396 | else if (float_abi == FLOAT_ABI_DOUBLE | |
f786c359 | 397 | && !riscv_subset_supports (&riscv_rps_as, "d")) |
5d0ed830 NC |
398 | as_bad ("ilp32d/lp64d ABI can't be used when d extension " |
399 | "isn't supported"); | |
400 | else if (float_abi == FLOAT_ABI_QUAD | |
f786c359 | 401 | && !riscv_subset_supports (&riscv_rps_as, "q")) |
5d0ed830 NC |
402 | as_bad ("ilp32q/lp64q ABI can't be used when q extension " |
403 | "isn't supported"); | |
6e1605e4 NC |
404 | } |
405 | ||
406 | /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */ | |
407 | elf_flags &= ~EF_RISCV_FLOAT_ABI; | |
408 | elf_flags |= float_abi << 1; | |
409 | ||
410 | if (rve_abi) | |
411 | elf_flags |= EF_RISCV_RVE; | |
412 | } | |
413 | ||
e23eba97 | 414 | /* Handle of the OPCODE hash table. */ |
629310ab | 415 | static htab_t op_hash = NULL; |
e23eba97 | 416 | |
0e35537d | 417 | /* Handle of the type of .insn hash table. */ |
629310ab | 418 | static htab_t insn_type_hash = NULL; |
0e35537d | 419 | |
e23eba97 | 420 | /* This array holds the chars that always start a comment. If the |
dcd709e0 | 421 | pre-processor is disabled, these aren't very useful. */ |
e23eba97 NC |
422 | const char comment_chars[] = "#"; |
423 | ||
424 | /* This array holds the chars that only start a comment at the beginning of | |
425 | a line. If the line seems to have the form '# 123 filename' | |
dcd709e0 NC |
426 | .line and .file directives will appear in the pre-processed output |
427 | ||
428 | Note that input_file.c hand checks for '#' at the beginning of the | |
e23eba97 | 429 | first line of the input file. This is because the compiler outputs |
dcd709e0 NC |
430 | #NO_APP at the beginning of its output. |
431 | ||
432 | Also note that C style comments are always supported. */ | |
e23eba97 NC |
433 | const char line_comment_chars[] = "#"; |
434 | ||
435 | /* This array holds machine specific line separator characters. */ | |
436 | const char line_separator_chars[] = ";"; | |
437 | ||
dcd709e0 | 438 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
e23eba97 NC |
439 | const char EXP_CHARS[] = "eE"; |
440 | ||
dcd709e0 NC |
441 | /* Chars that mean this number is a floating point constant. |
442 | As in 0f12.456 or 0d1.2345e12. */ | |
035784e3 | 443 | const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; |
e23eba97 | 444 | |
2dc8dd17 | 445 | /* Indicate we are already assemble any instructions or not. */ |
5b7c81bd | 446 | static bool start_assemble = false; |
2dc8dd17 | 447 | |
f9a6a8f0 | 448 | /* Indicate ELF attributes are explicitly set. */ |
5b7c81bd | 449 | static bool explicit_attr = false; |
2dc8dd17 | 450 | |
f9a6a8f0 | 451 | /* Indicate CSR or priv instructions are explicitly used. */ |
5b7c81bd | 452 | static bool explicit_priv_attr = false; |
3fc6c3dc | 453 | |
6eb099ae | 454 | static char *expr_parse_end; |
437e2ff1 | 455 | |
e23eba97 NC |
456 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ |
457 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
458 | ((relax_substateT) \ | |
459 | (0xc0000000 \ | |
460 | | ((uncond) ? 1 : 0) \ | |
461 | | ((rvc) ? 2 : 0) \ | |
462 | | ((length) << 2))) | |
463 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
464 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
465 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
466 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
467 | ||
468 | /* Is the given value a sign-extended 32-bit value? */ | |
469 | #define IS_SEXT_32BIT_NUM(x) \ | |
470 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
471 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
472 | ||
473 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
474 | #define IS_ZEXT_32BIT_NUM(x) \ | |
475 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
476 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
477 | ||
478 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
479 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
480 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
481 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
482 | ||
8b7419c4 CM |
483 | #define INSERT_IMM(n, s, INSN, VALUE) \ |
484 | INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s) | |
485 | ||
e23eba97 NC |
486 | /* Determine if an instruction matches an opcode. */ |
487 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
488 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
489 | ||
9b9b1092 NC |
490 | /* Create a new mapping symbol for the transition to STATE. */ |
491 | ||
492 | static void | |
493 | make_mapping_symbol (enum riscv_seg_mstate state, | |
494 | valueT value, | |
40f1a1a4 | 495 | fragS *frag, |
d918451a NC |
496 | const char *arch_str, |
497 | bool odd_data_padding) | |
9b9b1092 NC |
498 | { |
499 | const char *name; | |
615d4f41 | 500 | char *buff = NULL; |
9b9b1092 NC |
501 | switch (state) |
502 | { | |
503 | case MAP_DATA: | |
504 | name = "$d"; | |
505 | break; | |
506 | case MAP_INSN: | |
d918451a | 507 | if (arch_str != NULL) |
40f1a1a4 | 508 | { |
d918451a | 509 | size_t size = strlen (arch_str) + 3; /* "$x" + '\0' */ |
40f1a1a4 | 510 | buff = xmalloc (size); |
d918451a | 511 | snprintf (buff, size, "$x%s", arch_str); |
40f1a1a4 NC |
512 | name = buff; |
513 | } | |
514 | else | |
515 | name = "$x"; | |
9b9b1092 NC |
516 | break; |
517 | default: | |
518 | abort (); | |
519 | } | |
520 | ||
521 | symbolS *symbol = symbol_new (name, now_seg, frag, value); | |
522 | symbol_get_bfdsym (symbol)->flags |= (BSF_NO_FLAGS | BSF_LOCAL); | |
d918451a | 523 | if (arch_str != NULL) |
40f1a1a4 NC |
524 | { |
525 | /* Store current $x+arch into tc_segment_info. */ | |
526 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol = symbol; | |
527 | xfree ((void *) buff); | |
528 | } | |
9b9b1092 NC |
529 | |
530 | /* If .fill or other data filling directive generates zero sized data, | |
40f1a1a4 NC |
531 | then mapping symbol for the following code will have the same value. |
532 | ||
533 | Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first | |
534 | and .text.zero.fill.last. */ | |
535 | symbolS *first = frag->tc_frag_data.first_map_symbol; | |
536 | symbolS *last = frag->tc_frag_data.last_map_symbol; | |
d918451a | 537 | symbolS *removed = NULL; |
9b9b1092 NC |
538 | if (value == 0) |
539 | { | |
40f1a1a4 | 540 | if (first != NULL) |
9b9b1092 | 541 | { |
40f1a1a4 NC |
542 | know (S_GET_VALUE (first) == S_GET_VALUE (symbol) |
543 | && first == last); | |
9b9b1092 | 544 | /* Remove the old one. */ |
d918451a | 545 | removed = first; |
9b9b1092 NC |
546 | } |
547 | frag->tc_frag_data.first_map_symbol = symbol; | |
548 | } | |
40f1a1a4 | 549 | else if (last != NULL) |
9b9b1092 NC |
550 | { |
551 | /* The mapping symbols should be added in offset order. */ | |
40f1a1a4 | 552 | know (S_GET_VALUE (last) <= S_GET_VALUE (symbol)); |
9b9b1092 | 553 | /* Remove the old one. */ |
40f1a1a4 | 554 | if (S_GET_VALUE (last) == S_GET_VALUE (symbol)) |
d918451a | 555 | removed = last; |
9b9b1092 NC |
556 | } |
557 | frag->tc_frag_data.last_map_symbol = symbol; | |
d918451a NC |
558 | |
559 | if (removed == NULL) | |
560 | return; | |
561 | ||
562 | if (odd_data_padding) | |
563 | { | |
564 | /* If the removed mapping symbol is $x+arch, then add it back to | |
565 | the next $x. */ | |
566 | const char *str = strncmp (S_GET_NAME (removed), "$xrv", 4) == 0 | |
567 | ? S_GET_NAME (removed) + 2 : NULL; | |
568 | make_mapping_symbol (MAP_INSN, frag->fr_fix + 1, frag, str, | |
569 | false/* odd_data_padding */); | |
570 | } | |
571 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
572 | } |
573 | ||
574 | /* Set the mapping state for frag_now. */ | |
575 | ||
576 | void | |
577 | riscv_mapping_state (enum riscv_seg_mstate to_state, | |
40f1a1a4 | 578 | int max_chars, |
3190ebcb | 579 | bool fr_align_code) |
9b9b1092 NC |
580 | { |
581 | enum riscv_seg_mstate from_state = | |
582 | seg_info (now_seg)->tc_segment_info_data.map_state; | |
40f1a1a4 | 583 | bool reset_seg_arch_str = false; |
9b9b1092 NC |
584 | |
585 | if (!SEG_NORMAL (now_seg) | |
40f1a1a4 | 586 | /* For now we only add the mapping symbols to text sections. |
9b9b1092 NC |
587 | Therefore, the dis-assembler only show the actual contents |
588 | distribution for text. Other sections will be shown as | |
589 | data without the details. */ | |
590 | || !subseg_text_p (now_seg)) | |
591 | return; | |
592 | ||
593 | /* The mapping symbol should be emitted if not in the right | |
40f1a1a4 NC |
594 | mapping state. */ |
595 | symbolS *seg_arch_symbol = | |
596 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol; | |
597 | if (to_state == MAP_INSN && seg_arch_symbol == 0) | |
598 | { | |
599 | /* Always add $x+arch at the first instruction of section. */ | |
600 | reset_seg_arch_str = true; | |
601 | } | |
602 | else if (seg_arch_symbol != 0 | |
603 | && to_state == MAP_INSN | |
3190ebcb | 604 | && !fr_align_code |
40f1a1a4 NC |
605 | && strcmp (riscv_rps_as.subset_list->arch_str, |
606 | S_GET_NAME (seg_arch_symbol) + 2) != 0) | |
607 | { | |
608 | reset_seg_arch_str = true; | |
40f1a1a4 NC |
609 | } |
610 | else if (from_state == to_state) | |
9b9b1092 NC |
611 | return; |
612 | ||
613 | valueT value = (valueT) (frag_now_fix () - max_chars); | |
614 | seg_info (now_seg)->tc_segment_info_data.map_state = to_state; | |
d918451a NC |
615 | const char *arch_str = reset_seg_arch_str |
616 | ? riscv_rps_as.subset_list->arch_str : NULL; | |
617 | make_mapping_symbol (to_state, value, frag_now, arch_str, | |
618 | false/* odd_data_padding */); | |
9b9b1092 NC |
619 | } |
620 | ||
621 | /* Add the odd bytes of paddings for riscv_handle_align. */ | |
622 | ||
623 | static void | |
624 | riscv_add_odd_padding_symbol (fragS *frag) | |
625 | { | |
626 | /* If there was already a mapping symbol, it should be | |
40f1a1a4 NC |
627 | removed in the make_mapping_symbol. |
628 | ||
d918451a NC |
629 | Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */ |
630 | make_mapping_symbol (MAP_DATA, frag->fr_fix, frag, | |
631 | NULL/* arch_str */, true/* odd_data_padding */); | |
9b9b1092 NC |
632 | } |
633 | ||
634 | /* Remove any excess mapping symbols generated for alignment frags in | |
635 | SEC. We may have created a mapping symbol before a zero byte | |
636 | alignment; remove it if there's a mapping symbol after the | |
637 | alignment. */ | |
638 | ||
639 | static void | |
640 | riscv_check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, | |
641 | asection *sec, | |
642 | void *dummy ATTRIBUTE_UNUSED) | |
643 | { | |
644 | segment_info_type *seginfo = seg_info (sec); | |
645 | fragS *fragp; | |
646 | ||
647 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
648 | return; | |
649 | ||
650 | for (fragp = seginfo->frchainP->frch_root; | |
651 | fragp != NULL; | |
652 | fragp = fragp->fr_next) | |
653 | { | |
654 | symbolS *last = fragp->tc_frag_data.last_map_symbol; | |
655 | fragS *next = fragp->fr_next; | |
656 | ||
657 | if (last == NULL || next == NULL) | |
658 | continue; | |
659 | ||
660 | /* Check the last mapping symbol if it is at the boundary of | |
661 | fragment. */ | |
662 | if (S_GET_VALUE (last) < next->fr_address) | |
663 | continue; | |
664 | know (S_GET_VALUE (last) == next->fr_address); | |
665 | ||
666 | do | |
667 | { | |
40f1a1a4 NC |
668 | symbolS *next_first = next->tc_frag_data.first_map_symbol; |
669 | if (next_first != NULL) | |
9b9b1092 NC |
670 | { |
671 | /* The last mapping symbol overlaps with another one | |
40f1a1a4 NC |
672 | which at the start of the next frag. |
673 | ||
674 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
675 | .text.zero.fill.align.A and .text.zero.fill.align.B. */ | |
d918451a NC |
676 | know (S_GET_VALUE (last) == S_GET_VALUE (next_first)); |
677 | symbolS *removed = last; | |
678 | if (strncmp (S_GET_NAME (last), "$xrv", 4) == 0 | |
679 | && strcmp (S_GET_NAME (next_first), "$x") == 0) | |
680 | removed = next_first; | |
681 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
682 | break; |
683 | } | |
684 | ||
685 | if (next->fr_next == NULL) | |
686 | { | |
40f1a1a4 NC |
687 | /* The last mapping symbol is at the end of the section. |
688 | ||
689 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
690 | .text.last.section. */ | |
9b9b1092 NC |
691 | know (next->fr_fix == 0 && next->fr_var == 0); |
692 | symbol_remove (last, &symbol_rootP, &symbol_lastP); | |
693 | break; | |
694 | } | |
695 | ||
696 | /* Since we may have empty frags without any mapping symbols, | |
697 | keep looking until the non-empty frag. */ | |
698 | if (next->fr_address != next->fr_next->fr_address) | |
699 | break; | |
700 | ||
701 | next = next->fr_next; | |
702 | } | |
703 | while (next != NULL); | |
704 | } | |
705 | } | |
706 | ||
e23eba97 NC |
707 | /* The default target format to use. */ |
708 | ||
709 | const char * | |
710 | riscv_target_format (void) | |
711 | { | |
fbc09e7a MC |
712 | if (target_big_endian) |
713 | return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; | |
714 | else | |
715 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
e23eba97 NC |
716 | } |
717 | ||
718 | /* Return the length of instruction INSN. */ | |
719 | ||
720 | static inline unsigned int | |
721 | insn_length (const struct riscv_cl_insn *insn) | |
722 | { | |
723 | return riscv_insn_length (insn->insn_opcode); | |
724 | } | |
725 | ||
726 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
727 | ||
728 | static void | |
729 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
730 | { | |
731 | insn->insn_mo = mo; | |
732 | insn->insn_opcode = mo->match; | |
634001bb | 733 | insn->insn_long_opcode[0] = 0; |
e23eba97 NC |
734 | insn->frag = NULL; |
735 | insn->where = 0; | |
736 | insn->fixp = NULL; | |
737 | } | |
738 | ||
739 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
740 | ||
741 | static void | |
742 | install_insn (const struct riscv_cl_insn *insn) | |
743 | { | |
744 | char *f = insn->frag->fr_literal + insn->where; | |
634001bb TO |
745 | if (insn->insn_long_opcode[0] != 0) |
746 | memcpy (f, insn->insn_long_opcode, insn_length (insn)); | |
747 | else | |
748 | number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); | |
e23eba97 NC |
749 | } |
750 | ||
751 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
752 | and install the opcode in the new location. */ | |
753 | ||
754 | static void | |
755 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
756 | { | |
757 | insn->frag = frag; | |
758 | insn->where = where; | |
759 | if (insn->fixp != NULL) | |
760 | { | |
761 | insn->fixp->fx_frag = frag; | |
762 | insn->fixp->fx_where = where; | |
763 | } | |
764 | install_insn (insn); | |
765 | } | |
766 | ||
767 | /* Add INSN to the end of the output. */ | |
768 | ||
769 | static void | |
770 | add_fixed_insn (struct riscv_cl_insn *insn) | |
771 | { | |
772 | char *f = frag_more (insn_length (insn)); | |
773 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
774 | } | |
775 | ||
776 | static void | |
777 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
778 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
779 | { | |
780 | frag_grow (max_chars); | |
781 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
782 | frag_var (rs_machine_dependent, max_chars, var, | |
783 | subtype, symbol, offset, NULL); | |
784 | } | |
785 | ||
786 | /* Compute the length of a branch sequence, and adjust the stored length | |
787 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
788 | ||
789 | static unsigned | |
790 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
791 | { | |
792 | int jump, rvc, length = 8; | |
793 | ||
794 | if (!fragp) | |
795 | return length; | |
796 | ||
797 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
798 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
799 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
800 | ||
801 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
802 | length = jump ? 4 : 8; | |
803 | ||
804 | if (fragp->fr_symbol != NULL | |
805 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 806 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
807 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
808 | { | |
809 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
810 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
811 | val -= fragp->fr_address + fragp->fr_fix; | |
812 | ||
813 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
814 | length = 2; | |
815 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
816 | length = 4; | |
817 | else if (!jump && rvc) | |
818 | length = 6; | |
819 | } | |
820 | ||
821 | if (update) | |
822 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
823 | ||
824 | return length; | |
825 | } | |
826 | ||
0e35537d JW |
827 | /* Information about an opcode name, mnemonics and its value. */ |
828 | struct opcode_name_t | |
829 | { | |
830 | const char *name; | |
831 | unsigned int val; | |
832 | }; | |
833 | ||
834 | /* List for all supported opcode name. */ | |
835 | static const struct opcode_name_t opcode_name_list[] = | |
836 | { | |
837 | {"C0", 0x0}, | |
838 | {"C1", 0x1}, | |
839 | {"C2", 0x2}, | |
840 | ||
841 | {"LOAD", 0x03}, | |
842 | {"LOAD_FP", 0x07}, | |
843 | {"CUSTOM_0", 0x0b}, | |
844 | {"MISC_MEM", 0x0f}, | |
845 | {"OP_IMM", 0x13}, | |
846 | {"AUIPC", 0x17}, | |
847 | {"OP_IMM_32", 0x1b}, | |
848 | /* 48b 0x1f. */ | |
849 | ||
850 | {"STORE", 0x23}, | |
851 | {"STORE_FP", 0x27}, | |
852 | {"CUSTOM_1", 0x2b}, | |
853 | {"AMO", 0x2f}, | |
854 | {"OP", 0x33}, | |
855 | {"LUI", 0x37}, | |
856 | {"OP_32", 0x3b}, | |
857 | /* 64b 0x3f. */ | |
858 | ||
859 | {"MADD", 0x43}, | |
860 | {"MSUB", 0x47}, | |
861 | {"NMADD", 0x4f}, | |
862 | {"NMSUB", 0x4b}, | |
863 | {"OP_FP", 0x53}, | |
f8ad70a1 | 864 | {"OP_V", 0x57}, |
0e35537d JW |
865 | {"CUSTOM_2", 0x5b}, |
866 | /* 48b 0x5f. */ | |
867 | ||
868 | {"BRANCH", 0x63}, | |
869 | {"JALR", 0x67}, | |
870 | /*reserved 0x5b. */ | |
871 | {"JAL", 0x6f}, | |
872 | {"SYSTEM", 0x73}, | |
873 | /*reserved 0x77. */ | |
874 | {"CUSTOM_3", 0x7b}, | |
875 | /* >80b 0x7f. */ | |
876 | ||
877 | {NULL, 0} | |
878 | }; | |
879 | ||
880 | /* Hash table for lookup opcode name. */ | |
629310ab | 881 | static htab_t opcode_names_hash = NULL; |
0e35537d JW |
882 | |
883 | /* Initialization for hash table of opcode name. */ | |
dcd709e0 | 884 | |
0e35537d JW |
885 | static void |
886 | init_opcode_names_hash (void) | |
887 | { | |
0e35537d JW |
888 | const struct opcode_name_t *opcode; |
889 | ||
890 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
fe0e921f | 891 | if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL) |
b800637e | 892 | as_fatal (_("internal: duplicate %s"), opcode->name); |
0e35537d JW |
893 | } |
894 | ||
dcd709e0 NC |
895 | /* Find `s` is a valid opcode name or not, return the opcode name info |
896 | if found. */ | |
897 | ||
0e35537d JW |
898 | static const struct opcode_name_t * |
899 | opcode_name_lookup (char **s) | |
900 | { | |
901 | char *e; | |
902 | char save_c; | |
903 | struct opcode_name_t *o; | |
904 | ||
905 | /* Find end of name. */ | |
906 | e = *s; | |
907 | if (is_name_beginner (*e)) | |
908 | ++e; | |
909 | while (is_part_of_name (*e)) | |
910 | ++e; | |
911 | ||
912 | /* Terminate name. */ | |
913 | save_c = *e; | |
914 | *e = '\0'; | |
915 | ||
629310ab | 916 | o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s); |
0e35537d JW |
917 | |
918 | /* Advance to next token if one was recognized. */ | |
919 | if (o) | |
920 | *s = e; | |
921 | ||
922 | *e = save_c; | |
6eb099ae | 923 | expr_parse_end = e; |
0e35537d JW |
924 | |
925 | return o; | |
926 | } | |
927 | ||
437e2ff1 | 928 | /* All RISC-V registers belong to one of these classes. */ |
e23eba97 NC |
929 | enum reg_class |
930 | { | |
931 | RCLASS_GPR, | |
932 | RCLASS_FPR, | |
65e4a99a NC |
933 | RCLASS_VECR, |
934 | RCLASS_VECM, | |
8f595e9b NC |
935 | RCLASS_MAX, |
936 | ||
937 | RCLASS_CSR | |
e23eba97 NC |
938 | }; |
939 | ||
629310ab ML |
940 | static htab_t reg_names_hash = NULL; |
941 | static htab_t csr_extra_hash = NULL; | |
e23eba97 NC |
942 | |
943 | #define ENCODE_REG_HASH(cls, n) \ | |
944 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
945 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
946 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
947 | ||
948 | static void | |
949 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
950 | { | |
951 | void *hash = ENCODE_REG_HASH (class, n); | |
fe0e921f | 952 | if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL) |
b800637e | 953 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
954 | } |
955 | ||
956 | static void | |
02a63525 | 957 | hash_reg_names (enum reg_class class, const char names[][NRC], unsigned n) |
e23eba97 NC |
958 | { |
959 | unsigned i; | |
960 | ||
961 | for (i = 0; i < n; i++) | |
962 | hash_reg_name (class, names[i], i); | |
963 | } | |
964 | ||
8f595e9b | 965 | /* Init hash table csr_extra_hash to handle CSR. */ |
dcd709e0 | 966 | |
8f595e9b NC |
967 | static void |
968 | riscv_init_csr_hash (const char *name, | |
3d73d29e NC |
969 | unsigned address, |
970 | enum riscv_csr_class class, | |
971 | enum riscv_spec_class define_version, | |
972 | enum riscv_spec_class abort_version) | |
8f595e9b NC |
973 | { |
974 | struct riscv_csr_extra *entry, *pre_entry; | |
5b7c81bd | 975 | bool need_enrty = true; |
8f595e9b NC |
976 | |
977 | pre_entry = NULL; | |
629310ab | 978 | entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name); |
8f595e9b NC |
979 | while (need_enrty && entry != NULL) |
980 | { | |
981 | if (entry->csr_class == class | |
1942a048 NC |
982 | && entry->address == address |
983 | && entry->define_version == define_version | |
984 | && entry->abort_version == abort_version) | |
5b7c81bd | 985 | need_enrty = false; |
8f595e9b NC |
986 | pre_entry = entry; |
987 | entry = entry->next; | |
988 | } | |
1942a048 | 989 | |
dcd709e0 | 990 | /* Duplicate CSR. */ |
8f595e9b NC |
991 | if (!need_enrty) |
992 | return; | |
bd0cf5a6 | 993 | |
7bfc4db2 | 994 | entry = notes_alloc (sizeof (*entry)); |
8f595e9b NC |
995 | entry->csr_class = class; |
996 | entry->address = address; | |
997 | entry->define_version = define_version; | |
998 | entry->abort_version = abort_version; | |
5c505568 | 999 | entry->next = NULL; |
8f595e9b | 1000 | |
8f595e9b | 1001 | if (pre_entry == NULL) |
fe0e921f | 1002 | str_hash_insert (csr_extra_hash, name, entry, 0); |
8f595e9b NC |
1003 | else |
1004 | pre_entry->next = entry; | |
1005 | } | |
bd0cf5a6 | 1006 | |
dcd709e0 NC |
1007 | /* Return the CSR address after checking the ISA dependency and |
1008 | the privileged spec version. | |
1009 | ||
1010 | There are one warning and two errors for CSR, | |
1011 | ||
1012 | Invalid CSR: the CSR was defined, but isn't allowed for the current ISA | |
1013 | or the privileged spec, report warning only if -mcsr-check is set. | |
1014 | Unknown CSR: the CSR has never been defined, report error. | |
1015 | Improper CSR: the CSR number over the range (> 0xfff), report error. */ | |
bd0cf5a6 | 1016 | |
08ccfccf NC |
1017 | static unsigned int |
1018 | riscv_csr_address (const char *csr_name, | |
1019 | struct riscv_csr_extra *entry) | |
bd0cf5a6 | 1020 | { |
08ccfccf NC |
1021 | struct riscv_csr_extra *saved_entry = entry; |
1022 | enum riscv_csr_class csr_class = entry->csr_class; | |
df0a549e | 1023 | bool need_check_version = false; |
39590abd TO |
1024 | bool is_rv32_only = false; |
1025 | bool is_h_required = false; | |
df0a549e | 1026 | const char* extension = NULL; |
8f595e9b | 1027 | |
8f595e9b | 1028 | switch (csr_class) |
bd0cf5a6 | 1029 | { |
08ccfccf | 1030 | case CSR_CLASS_I_32: |
39590abd | 1031 | is_rv32_only = true; |
df0a549e PN |
1032 | /* Fall through. */ |
1033 | case CSR_CLASS_I: | |
1034 | need_check_version = true; | |
1035 | extension = "i"; | |
08ccfccf | 1036 | break; |
c625f4ed | 1037 | case CSR_CLASS_H_32: |
39590abd | 1038 | is_rv32_only = true; |
c625f4ed NC |
1039 | /* Fall through. */ |
1040 | case CSR_CLASS_H: | |
1041 | extension = "h"; | |
1042 | break; | |
8f595e9b | 1043 | case CSR_CLASS_F: |
df0a549e | 1044 | extension = "f"; |
8f595e9b | 1045 | break; |
3d1cafa0 | 1046 | case CSR_CLASS_ZKR: |
df0a549e | 1047 | extension = "zkr"; |
3d1cafa0 | 1048 | break; |
65e4a99a | 1049 | case CSR_CLASS_V: |
1daabcc7 | 1050 | extension = "zve32x"; |
65e4a99a | 1051 | break; |
ac8df5a1 CM |
1052 | case CSR_CLASS_SMAIA_32: |
1053 | is_rv32_only = true; | |
1054 | /* Fall through. */ | |
1055 | case CSR_CLASS_SMAIA: | |
1056 | extension = "smaia"; | |
1057 | break; | |
a303646f TO |
1058 | case CSR_CLASS_SMCNTRPMF_32: |
1059 | is_rv32_only = true; | |
1060 | /* Fall through. */ | |
1061 | case CSR_CLASS_SMCNTRPMF: | |
1062 | need_check_version = true; | |
1063 | extension = "smcntrpmf"; | |
1064 | break; | |
6af47b08 | 1065 | case CSR_CLASS_SMSTATEEN_32: |
c509db05 TO |
1066 | is_rv32_only = true; |
1067 | /* Fall through. */ | |
1068 | case CSR_CLASS_SMSTATEEN: | |
6af47b08 TO |
1069 | extension = "smstateen"; |
1070 | break; | |
ac8df5a1 CM |
1071 | case CSR_CLASS_SSAIA: |
1072 | case CSR_CLASS_SSAIA_AND_H: | |
1073 | case CSR_CLASS_SSAIA_32: | |
1074 | case CSR_CLASS_SSAIA_AND_H_32: | |
1075 | is_rv32_only = (csr_class == CSR_CLASS_SSAIA_32 | |
1076 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1077 | is_h_required = (csr_class == CSR_CLASS_SSAIA_AND_H | |
1078 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1079 | extension = "ssaia"; | |
1080 | break; | |
15253318 | 1081 | case CSR_CLASS_SSSTATEEN_AND_H_32: |
c509db05 TO |
1082 | is_rv32_only = true; |
1083 | /* Fall through. */ | |
1084 | case CSR_CLASS_SSSTATEEN_AND_H: | |
1085 | is_h_required = true; | |
1086 | /* Fall through. */ | |
1087 | case CSR_CLASS_SSSTATEEN: | |
15253318 TO |
1088 | extension = "ssstateen"; |
1089 | break; | |
713f3708 TO |
1090 | case CSR_CLASS_SSCOFPMF_32: |
1091 | is_rv32_only = true; | |
1092 | /* Fall through. */ | |
1093 | case CSR_CLASS_SSCOFPMF: | |
1094 | extension = "sscofpmf"; | |
1095 | break; | |
766077c1 TO |
1096 | case CSR_CLASS_SSTC: |
1097 | case CSR_CLASS_SSTC_AND_H: | |
1098 | case CSR_CLASS_SSTC_32: | |
1099 | case CSR_CLASS_SSTC_AND_H_32: | |
1100 | is_rv32_only = (csr_class == CSR_CLASS_SSTC_32 | |
1101 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1102 | is_h_required = (csr_class == CSR_CLASS_SSTC_AND_H | |
1103 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1104 | extension = "sstc"; | |
1105 | break; | |
08ccfccf | 1106 | case CSR_CLASS_DEBUG: |
8f595e9b | 1107 | break; |
6fdd02bb JM |
1108 | case CSR_CLASS_XTHEADVECTOR: |
1109 | extension = "xtheadvector"; | |
1110 | break; | |
8f595e9b NC |
1111 | default: |
1112 | as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class); | |
bd0cf5a6 NC |
1113 | } |
1114 | ||
df0a549e PN |
1115 | if (riscv_opts.csr_check) |
1116 | { | |
39590abd | 1117 | if (is_rv32_only && xlen != 32) |
df0a549e | 1118 | as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name); |
39590abd TO |
1119 | if (is_h_required && !riscv_subset_supports (&riscv_rps_as, "h")) |
1120 | as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name); | |
df0a549e PN |
1121 | |
1122 | if (extension != NULL | |
1123 | && !riscv_subset_supports (&riscv_rps_as, extension)) | |
1124 | as_warn (_("invalid CSR `%s', needs `%s' extension"), | |
1125 | csr_name, extension); | |
1126 | } | |
8f595e9b NC |
1127 | |
1128 | while (entry != NULL) | |
bd0cf5a6 | 1129 | { |
08ccfccf NC |
1130 | if (!need_check_version |
1131 | || (default_priv_spec >= entry->define_version | |
1132 | && default_priv_spec < entry->abort_version)) | |
8f595e9b | 1133 | { |
dcd709e0 | 1134 | /* Find the CSR according to the specific version. */ |
08ccfccf | 1135 | return entry->address; |
8f595e9b NC |
1136 | } |
1137 | entry = entry->next; | |
1138 | } | |
bd0cf5a6 | 1139 | |
dcd709e0 NC |
1140 | /* Can not find the CSR address from the chosen privileged version, |
1141 | so use the newly defined value. */ | |
8f595e9b NC |
1142 | if (riscv_opts.csr_check) |
1143 | { | |
3d73d29e NC |
1144 | const char *priv_name = NULL; |
1145 | RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec); | |
8f595e9b | 1146 | if (priv_name != NULL) |
b800637e | 1147 | as_warn (_("invalid CSR `%s' for the privileged spec `%s'"), |
8f595e9b | 1148 | csr_name, priv_name); |
bd0cf5a6 | 1149 | } |
08ccfccf NC |
1150 | |
1151 | return saved_entry->address; | |
bd0cf5a6 NC |
1152 | } |
1153 | ||
dcd709e0 NC |
1154 | /* Return -1 if the CSR has never been defined. Otherwise, return |
1155 | the address. */ | |
bd0cf5a6 | 1156 | |
8f595e9b | 1157 | static unsigned int |
bd0cf5a6 NC |
1158 | reg_csr_lookup_internal (const char *s) |
1159 | { | |
1160 | struct riscv_csr_extra *r = | |
629310ab | 1161 | (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s); |
bd0cf5a6 NC |
1162 | |
1163 | if (r == NULL) | |
8f595e9b | 1164 | return -1U; |
bd0cf5a6 | 1165 | |
08ccfccf | 1166 | return riscv_csr_address (s, r); |
bd0cf5a6 NC |
1167 | } |
1168 | ||
e23eba97 NC |
1169 | static unsigned int |
1170 | reg_lookup_internal (const char *s, enum reg_class class) | |
1171 | { | |
8f595e9b NC |
1172 | void *r; |
1173 | ||
1174 | if (class == RCLASS_CSR) | |
1175 | return reg_csr_lookup_internal (s); | |
e23eba97 | 1176 | |
629310ab | 1177 | r = str_hash_find (reg_names_hash, s); |
e23eba97 NC |
1178 | if (r == NULL || DECODE_REG_CLASS (r) != class) |
1179 | return -1; | |
7f999549 | 1180 | |
f786c359 | 1181 | if (riscv_subset_supports (&riscv_rps_as, "e") |
edc77c59 NC |
1182 | && class == RCLASS_GPR |
1183 | && DECODE_REG_NUM (r) > 15) | |
7f999549 JW |
1184 | return -1; |
1185 | ||
e23eba97 NC |
1186 | return DECODE_REG_NUM (r); |
1187 | } | |
1188 | ||
5b7c81bd | 1189 | static bool |
e23eba97 NC |
1190 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) |
1191 | { | |
1192 | char *e; | |
1193 | char save_c; | |
1194 | int reg = -1; | |
1195 | ||
1196 | /* Find end of name. */ | |
1197 | e = *s; | |
1198 | if (is_name_beginner (*e)) | |
1199 | ++e; | |
1200 | while (is_part_of_name (*e)) | |
1201 | ++e; | |
1202 | ||
1203 | /* Terminate name. */ | |
1204 | save_c = *e; | |
1205 | *e = '\0'; | |
1206 | ||
1207 | /* Look for the register. Advance to next token if one was recognized. */ | |
1208 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
1209 | *s = e; | |
1210 | ||
1211 | *e = save_c; | |
1212 | if (regnop) | |
1213 | *regnop = reg; | |
1214 | return reg >= 0; | |
1215 | } | |
1216 | ||
5b7c81bd | 1217 | static bool |
e23eba97 NC |
1218 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) |
1219 | { | |
1220 | const char *p = strchr (*s, ','); | |
1221 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
1222 | ||
bfb218e3 | 1223 | if (len == 0) |
5b7c81bd | 1224 | return false; |
bfb218e3 | 1225 | |
e23eba97 | 1226 | for (i = 0; i < size; i++) |
207cc92d LX |
1227 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0 |
1228 | && array[i][len] == '\0') | |
e23eba97 NC |
1229 | { |
1230 | *regnop = i; | |
1231 | *s += len; | |
5b7c81bd | 1232 | return true; |
e23eba97 NC |
1233 | } |
1234 | ||
5b7c81bd | 1235 | return false; |
e23eba97 NC |
1236 | } |
1237 | ||
1f3fc45b CM |
1238 | static bool |
1239 | flt_lookup (float f, const float *array, size_t size, unsigned *regnop) | |
1240 | { | |
1241 | size_t i; | |
1242 | ||
1243 | for (i = 0; i < size; i++) | |
1244 | if (array[i] == f) | |
1245 | { | |
1246 | *regnop = i; | |
1247 | return true; | |
1248 | } | |
1249 | ||
1250 | return false; | |
1251 | } | |
1252 | ||
437e2ff1 | 1253 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) |
8b7419c4 CM |
1254 | #define USE_IMM(n, s) \ |
1255 | (used_bits |= ((insn_t)((1ull<<n)-1) << (s))) | |
437e2ff1 | 1256 | |
e23eba97 NC |
1257 | /* For consistency checking, verify that all bits are specified either |
1258 | by the match/mask part of the instruction definition, or by the | |
83029f7f TO |
1259 | operand list. The `length` could be the actual instruction length or |
1260 | 0 for auto-detection. */ | |
0e35537d | 1261 | |
5b7c81bd | 1262 | static bool |
0e35537d | 1263 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 | 1264 | { |
437e2ff1 | 1265 | const char *oparg, *opargStart; |
e23eba97 | 1266 | insn_t used_bits = opc->mask; |
0e35537d JW |
1267 | int insn_width; |
1268 | insn_t required_bits; | |
1269 | ||
1270 | if (length == 0) | |
83029f7f TO |
1271 | length = riscv_insn_length (opc->match); |
1272 | /* We don't support instructions longer than 64-bits yet. */ | |
1273 | if (length > 8) | |
1274 | length = 8; | |
1275 | insn_width = 8 * length; | |
0e35537d | 1276 | |
83029f7f | 1277 | required_bits = ((insn_t)~0ULL) >> (64 - insn_width); |
e23eba97 NC |
1278 | |
1279 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
1280 | { | |
1281 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
1282 | opc->name, opc->args); | |
5b7c81bd | 1283 | return false; |
e23eba97 NC |
1284 | } |
1285 | ||
437e2ff1 NC |
1286 | for (oparg = opc->args; *oparg; ++oparg) |
1287 | { | |
1288 | opargStart = oparg; | |
1289 | switch (*oparg) | |
1290 | { | |
1291 | case 'C': /* RVC */ | |
1292 | switch (*++oparg) | |
1293 | { | |
1294 | case 'U': break; /* CRS1, constrained to equal RD. */ | |
1295 | case 'c': break; /* CRS1, constrained to equal sp. */ | |
1296 | case 'T': /* CRS2, floating point. */ | |
1297 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1298 | case 'S': /* CRS1S, floating point. */ | |
1299 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
1300 | case 'w': break; /* CRS1S, constrained to equal RD. */ | |
1301 | case 'D': /* CRS2S, floating point. */ | |
1302 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1303 | case 'x': break; /* CRS2S, constrained to equal RD. */ | |
1304 | case 'z': break; /* CRS2S, constrained to be x0. */ | |
1305 | case '>': /* CITYPE immediate, compressed shift. */ | |
1306 | case 'u': /* CITYPE immediate, compressed lui. */ | |
1307 | case 'v': /* CITYPE immediate, li to compressed lui. */ | |
1308 | case 'o': /* CITYPE immediate, allow zero. */ | |
1309 | case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break; | |
1310 | case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break; | |
1311 | case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break; | |
1312 | case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break; | |
1313 | case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break; | |
1314 | case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break; | |
1315 | case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break; | |
1316 | case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break; | |
1317 | case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break; | |
1318 | /* CLTYPE and CSTYPE have the same immediate encoding. */ | |
1319 | case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break; | |
1320 | case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break; | |
1321 | case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break; | |
1322 | case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break; | |
1323 | case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break; | |
1324 | case 'F': /* Compressed funct for .insn directive. */ | |
1325 | switch (*++oparg) | |
1326 | { | |
65e4a99a NC |
1327 | case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; |
1328 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; | |
1329 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
1330 | case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; | |
1331 | default: | |
1332 | goto unknown_validate_operand; | |
437e2ff1 NC |
1333 | } |
1334 | break; | |
0e35537d | 1335 | default: |
437e2ff1 NC |
1336 | goto unknown_validate_operand; |
1337 | } | |
a63375ac | 1338 | break; /* end RVC */ |
65e4a99a NC |
1339 | case 'V': /* RVV */ |
1340 | switch (*++oparg) | |
1341 | { | |
1342 | case 'd': | |
1343 | case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break; | |
1344 | case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break; | |
1345 | case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break; | |
1346 | case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1347 | case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1348 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1349 | case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD); | |
1350 | USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1351 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1352 | case '0': break; | |
1353 | case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break; | |
1354 | case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break; | |
1355 | case 'i': | |
1356 | case 'j': | |
1357 | case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; | |
c8cb3734 | 1358 | case 'l': used_bits |= ENCODE_RVV_VI_UIMM6 (-1U); break; |
65e4a99a | 1359 | case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; |
c1ecdee7 TO |
1360 | case 'M': break; /* Macro operand, must be a mask register. */ |
1361 | case 'T': break; /* Macro operand, must be a vector register. */ | |
65e4a99a NC |
1362 | default: |
1363 | goto unknown_validate_operand; | |
1364 | } | |
a63375ac | 1365 | break; /* end RVV */ |
437e2ff1 NC |
1366 | case ',': break; |
1367 | case '(': break; | |
1368 | case ')': break; | |
1369 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
1370 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
1371 | case 'A': break; /* Macro operand, must be symbol. */ | |
1372 | case 'B': break; /* Macro operand, must be symbol or constant. */ | |
c1ecdee7 | 1373 | case 'c': break; /* Macro operand, must be symbol or constant. */ |
437e2ff1 NC |
1374 | case 'I': break; /* Macro operand, must be constant. */ |
1375 | case 'D': /* RD, floating point. */ | |
1376 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
3d1cafa0 | 1377 | case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; |
1378 | case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; | |
437e2ff1 NC |
1379 | case 'Z': /* RS1, CSR number. */ |
1380 | case 'S': /* RS1, floating point. */ | |
1381 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
1382 | case 'U': /* RS1 and RS2 are the same, floating point. */ | |
1383 | USE_BITS (OP_MASK_RS1, OP_SH_RS1); | |
1384 | /* Fall through. */ | |
1385 | case 'T': /* RS2, floating point. */ | |
1386 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
1387 | case 'R': /* RS3, floating point. */ | |
1388 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
1389 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
1390 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
1391 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; | |
1392 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
1393 | case 'o': /* ITYPE immediate, load displacement. */ | |
1394 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; | |
1395 | case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; | |
1396 | case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; | |
1397 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
1398 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
1399 | case 'z': break; /* Zero immediate. */ | |
1400 | case '[': break; /* Unused operand. */ | |
1401 | case ']': break; /* Unused operand. */ | |
1402 | case '0': break; /* AMO displacement, must to zero. */ | |
1403 | case '1': break; /* Relaxation operand. */ | |
1404 | case 'F': /* Funct for .insn directive. */ | |
1405 | switch (*++oparg) | |
1406 | { | |
6de11ff6 NC |
1407 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; |
1408 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
1409 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
1410 | default: | |
1411 | goto unknown_validate_operand; | |
437e2ff1 NC |
1412 | } |
1413 | break; | |
1414 | case 'O': /* Opcode for .insn directive. */ | |
1415 | switch (*++oparg) | |
1416 | { | |
6de11ff6 NC |
1417 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; |
1418 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
1419 | default: | |
1420 | goto unknown_validate_operand; | |
437e2ff1 NC |
1421 | } |
1422 | break; | |
6de11ff6 | 1423 | case 'W': /* Various operands for standard z extensions. */ |
54bca63b TO |
1424 | switch (*++oparg) |
1425 | { | |
1426 | case 'i': | |
1427 | switch (*++oparg) | |
1428 | { | |
1429 | case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
1430 | default: | |
1431 | goto unknown_validate_operand; | |
1432 | } | |
1433 | break; | |
1f3fc45b CM |
1434 | case 'f': |
1435 | switch (*++oparg) | |
1436 | { | |
1437 | case 'v': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
1438 | default: | |
1439 | goto unknown_validate_operand; | |
1440 | } | |
1441 | break; | |
b5c37946 SJ |
1442 | case 'c': |
1443 | switch (*++oparg) | |
1444 | { | |
1445 | /* byte immediate operators, load/store byte insns. */ | |
1446 | case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; | |
1447 | /* halfword immediate operators, load/store halfword insns. */ | |
1448 | case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; | |
1449 | case 'f': break; | |
1450 | default: | |
1451 | goto unknown_validate_operand; | |
1452 | } | |
1453 | break; | |
54bca63b TO |
1454 | default: |
1455 | goto unknown_validate_operand; | |
1456 | } | |
1457 | break; | |
6de11ff6 NC |
1458 | case 'X': /* Vendor-specific operands. */ |
1459 | switch (*++oparg) | |
1460 | { | |
1461 | case 't': /* Vendor-specific (T-head) operands. */ | |
8b7419c4 | 1462 | { |
6de11ff6 NC |
1463 | size_t n; |
1464 | size_t s; | |
1465 | switch (*++oparg) | |
1466 | { | |
1467 | case 'l': /* Integer immediate, literal. */ | |
1468 | oparg += strcspn(oparg, ",") - 1; | |
1469 | break; | |
1470 | case 's': /* Integer immediate, 'XtsN@S' ... N-bit signed immediate at bit S. */ | |
1471 | goto use_imm; | |
1472 | case 'u': /* Integer immediate, 'XtuN@S' ... N-bit unsigned immediate at bit S. */ | |
1473 | goto use_imm; | |
1474 | use_imm: | |
1475 | n = strtol (oparg + 1, (char **)&oparg, 10); | |
1476 | if (*oparg != '@') | |
1477 | goto unknown_validate_operand; | |
1478 | s = strtol (oparg + 1, (char **)&oparg, 10); | |
1479 | oparg--; | |
1480 | ||
1481 | USE_IMM (n, s); | |
1482 | break; | |
1483 | default: | |
8b7419c4 | 1484 | goto unknown_validate_operand; |
6de11ff6 | 1485 | } |
8b7419c4 | 1486 | } |
6de11ff6 | 1487 | break; |
ccb388ca MB |
1488 | case 'c': /* Vendor-specific (CORE-V) operands. */ |
1489 | switch (*++oparg) | |
1490 | { | |
d1bd9787 MB |
1491 | case '2': |
1492 | /* ls2[4:0] */ | |
1493 | used_bits |= ENCODE_CV_IS2_UIMM5 (-1U); | |
1494 | break; | |
ccb388ca MB |
1495 | case '3': |
1496 | used_bits |= ENCODE_CV_IS3_UIMM5 (-1U); | |
1497 | break; | |
1498 | default: | |
1499 | goto unknown_validate_operand; | |
1500 | } | |
1501 | break; | |
6de11ff6 NC |
1502 | default: |
1503 | goto unknown_validate_operand; | |
1504 | } | |
8b7419c4 | 1505 | break; |
437e2ff1 NC |
1506 | default: |
1507 | unknown_validate_operand: | |
1508 | as_bad (_("internal: bad RISC-V opcode " | |
1509 | "(unknown operand type `%s'): %s %s"), | |
1510 | opargStart, opc->name, opc->args); | |
1511 | return false; | |
1512 | } | |
1513 | } | |
1514 | ||
e23eba97 NC |
1515 | if (used_bits != required_bits) |
1516 | { | |
b800637e | 1517 | as_bad (_("internal: bad RISC-V opcode " |
6b84c098 TO |
1518 | "(bits %#llx undefined or invalid): %s %s"), |
1519 | (unsigned long long)(used_bits ^ required_bits), | |
e23eba97 | 1520 | opc->name, opc->args); |
5b7c81bd | 1521 | return false; |
e23eba97 | 1522 | } |
5b7c81bd | 1523 | return true; |
e23eba97 NC |
1524 | } |
1525 | ||
437e2ff1 NC |
1526 | #undef USE_BITS |
1527 | ||
e23eba97 NC |
1528 | struct percent_op_match |
1529 | { | |
1530 | const char *str; | |
1531 | bfd_reloc_code_real_type reloc; | |
1532 | }; | |
1533 | ||
dcd709e0 NC |
1534 | /* Common hash table initialization function for instruction and .insn |
1535 | directive. */ | |
1536 | ||
629310ab | 1537 | static htab_t |
0e35537d | 1538 | init_opcode_hash (const struct riscv_opcode *opcodes, |
5b7c81bd | 1539 | bool insn_directive_p) |
e23eba97 NC |
1540 | { |
1541 | int i = 0; | |
0e35537d | 1542 | int length; |
629310ab | 1543 | htab_t hash = str_htab_create (); |
0e35537d | 1544 | while (opcodes[i].name) |
e23eba97 | 1545 | { |
0e35537d | 1546 | const char *name = opcodes[i].name; |
fe0e921f | 1547 | if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL) |
b800637e | 1548 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
1549 | |
1550 | do | |
1551 | { | |
0e35537d | 1552 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 1553 | { |
0e35537d JW |
1554 | if (insn_directive_p) |
1555 | length = ((name[0] == 'c') ? 2 : 4); | |
1556 | else | |
dcd709e0 | 1557 | length = 0; /* Let assembler determine the length. */ |
0e35537d | 1558 | if (!validate_riscv_insn (&opcodes[i], length)) |
b800637e NC |
1559 | as_fatal (_("internal: broken assembler. " |
1560 | "No assembly attempted")); | |
e23eba97 | 1561 | } |
0e35537d JW |
1562 | else |
1563 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
1564 | ++i; |
1565 | } | |
0e35537d | 1566 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
1567 | } |
1568 | ||
0e35537d JW |
1569 | return hash; |
1570 | } | |
1571 | ||
1572 | /* This function is called once, at assembler startup time. It should set up | |
1573 | all the tables, etc. that the MD part of the assembler will need. */ | |
1574 | ||
1575 | void | |
1576 | md_begin (void) | |
1577 | { | |
1578 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
1579 | ||
1580 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 1581 | as_warn (_("could not set architecture and machine")); |
0e35537d | 1582 | |
5b7c81bd AM |
1583 | op_hash = init_opcode_hash (riscv_opcodes, false); |
1584 | insn_type_hash = init_opcode_hash (riscv_insn_types, true); | |
0e35537d | 1585 | |
629310ab | 1586 | reg_names_hash = str_htab_create (); |
e23eba97 NC |
1587 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); |
1588 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
1589 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
1590 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
65e4a99a NC |
1591 | hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR); |
1592 | hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM); | |
b9c04e5a JW |
1593 | /* Add "fp" as an alias for "s0". */ |
1594 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
1595 | ||
bd0cf5a6 | 1596 | /* Create and insert CSR hash tables. */ |
629310ab | 1597 | csr_extra_hash = str_htab_create (); |
8f595e9b NC |
1598 | #define DECLARE_CSR(name, num, class, define_version, abort_version) \ |
1599 | riscv_init_csr_hash (#name, num, class, define_version, abort_version); | |
1600 | #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ | |
1601 | DECLARE_CSR(name, num, class, define_version, abort_version); | |
e23eba97 NC |
1602 | #include "opcode/riscv-opc.h" |
1603 | #undef DECLARE_CSR | |
1604 | ||
629310ab | 1605 | opcode_names_hash = str_htab_create (); |
bd0cf5a6 NC |
1606 | init_opcode_names_hash (); |
1607 | ||
e23eba97 NC |
1608 | /* Set the default alignment for the text section. */ |
1609 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
1610 | } | |
1611 | ||
45f76423 AW |
1612 | static insn_t |
1613 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
1614 | { | |
1615 | switch (reloc_type) | |
1616 | { | |
1617 | case BFD_RELOC_32: | |
1618 | return value; | |
1619 | ||
1620 | case BFD_RELOC_RISCV_HI20: | |
1621 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
1622 | ||
1623 | case BFD_RELOC_RISCV_LO12_S: | |
1624 | return ENCODE_STYPE_IMM (value); | |
1625 | ||
1626 | case BFD_RELOC_RISCV_LO12_I: | |
1627 | return ENCODE_ITYPE_IMM (value); | |
1628 | ||
1629 | default: | |
1630 | abort (); | |
1631 | } | |
1632 | } | |
1633 | ||
e23eba97 NC |
1634 | /* Output an instruction. IP is the instruction information. |
1635 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1636 | RELOC_TYPE. */ | |
1637 | ||
1638 | static void | |
1639 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
1640 | bfd_reloc_code_real_type reloc_type) | |
1641 | { | |
1642 | dwarf2_emit_insn (0); | |
1643 | ||
1644 | if (reloc_type != BFD_RELOC_UNUSED) | |
1645 | { | |
1646 | reloc_howto_type *howto; | |
1647 | ||
1d65abb5 | 1648 | gas_assert (address_expr); |
e23eba97 NC |
1649 | if (reloc_type == BFD_RELOC_12_PCREL |
1650 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
1651 | { | |
1652 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
8c07e983 | 1653 | int best_case = insn_length (ip); |
e23eba97 | 1654 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); |
743f5cfc JW |
1655 | |
1656 | if (now_seg == absolute_section) | |
1657 | { | |
1658 | as_bad (_("relaxable branches not supported in absolute section")); | |
1659 | return; | |
1660 | } | |
1661 | ||
e23eba97 NC |
1662 | add_relaxed_insn (ip, worst_case, best_case, |
1663 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
1664 | address_expr->X_add_symbol, | |
1665 | address_expr->X_add_number); | |
1666 | return; | |
1667 | } | |
45f76423 | 1668 | else |
e23eba97 | 1669 | { |
45f76423 AW |
1670 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
1671 | if (howto == NULL) | |
579f0281 | 1672 | as_bad (_("internal: unsupported RISC-V relocation number %d"), |
b800637e | 1673 | reloc_type); |
e23eba97 | 1674 | |
45f76423 AW |
1675 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
1676 | bfd_get_reloc_size (howto), | |
5b7c81bd | 1677 | address_expr, false, reloc_type); |
e23eba97 | 1678 | |
45f76423 | 1679 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 1680 | } |
e23eba97 NC |
1681 | } |
1682 | ||
e23eba97 | 1683 | add_fixed_insn (ip); |
f77bb6c5 JW |
1684 | |
1685 | /* We need to start a new frag after any instruction that can be | |
1686 | optimized away or compressed by the linker during relaxation, to prevent | |
1687 | the assembler from computing static offsets across such an instruction. | |
1688 | This is necessary to get correct EH info. */ | |
b1b11e92 | 1689 | if (reloc_type == BFD_RELOC_RISCV_HI20 |
f77bb6c5 JW |
1690 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 |
1691 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
1692 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
1693 | { | |
1694 | frag_wane (frag_now); | |
1695 | frag_new (0); | |
1696 | } | |
e23eba97 NC |
1697 | } |
1698 | ||
1699 | /* Build an instruction created by a macro expansion. This is passed | |
dcd709e0 NC |
1700 | a pointer to the count of instructions created so far, an expression, |
1701 | the name of the instruction to build, an operand format string, and | |
1702 | corresponding arguments. */ | |
e23eba97 NC |
1703 | |
1704 | static void | |
1705 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
1706 | { | |
1707 | const struct riscv_opcode *mo; | |
1708 | struct riscv_cl_insn insn; | |
1709 | bfd_reloc_code_real_type r; | |
1710 | va_list args; | |
437e2ff1 | 1711 | const char *fmtStart; |
e23eba97 NC |
1712 | |
1713 | va_start (args, fmt); | |
1714 | ||
1715 | r = BFD_RELOC_UNUSED; | |
629310ab | 1716 | mo = (struct riscv_opcode *) str_hash_find (op_hash, name); |
e23eba97 NC |
1717 | gas_assert (mo); |
1718 | ||
1719 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
1720 | it if possible. */ | |
1721 | while (riscv_insn_length (mo->match) < 4) | |
1722 | mo++; | |
1723 | gas_assert (strcmp (name, mo->name) == 0); | |
1724 | ||
1725 | create_insn (&insn, mo); | |
437e2ff1 | 1726 | for (;; ++fmt) |
e23eba97 | 1727 | { |
437e2ff1 NC |
1728 | fmtStart = fmt; |
1729 | switch (*fmt) | |
e23eba97 | 1730 | { |
65e4a99a NC |
1731 | case 'V': /* RVV */ |
1732 | switch (*++fmt) | |
1733 | { | |
1734 | case 'd': | |
1735 | INSERT_OPERAND (VD, insn, va_arg (args, int)); | |
1736 | continue; | |
1737 | case 's': | |
1738 | INSERT_OPERAND (VS1, insn, va_arg (args, int)); | |
1739 | continue; | |
1740 | case 't': | |
1741 | INSERT_OPERAND (VS2, insn, va_arg (args, int)); | |
1742 | continue; | |
1743 | case 'm': | |
1744 | { | |
1745 | int reg = va_arg (args, int); | |
1746 | if (reg == -1) | |
1747 | { | |
1748 | INSERT_OPERAND (VMASK, insn, 1); | |
1749 | continue; | |
1750 | } | |
1751 | else if (reg == 0) | |
1752 | { | |
1753 | INSERT_OPERAND (VMASK, insn, 0); | |
1754 | continue; | |
1755 | } | |
1756 | else | |
1757 | goto unknown_macro_argument; | |
1758 | } | |
1759 | default: | |
1760 | goto unknown_macro_argument; | |
1761 | } | |
1762 | break; | |
1763 | ||
e23eba97 NC |
1764 | case 'd': |
1765 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
1766 | continue; | |
e23eba97 NC |
1767 | case 's': |
1768 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
1769 | continue; | |
e23eba97 NC |
1770 | case 't': |
1771 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
1772 | continue; | |
1773 | ||
e23eba97 NC |
1774 | case 'j': |
1775 | case 'u': | |
1776 | case 'q': | |
1777 | gas_assert (ep != NULL); | |
1778 | r = va_arg (args, int); | |
1779 | continue; | |
1780 | ||
1781 | case '\0': | |
1782 | break; | |
1783 | case ',': | |
1784 | continue; | |
1785 | default: | |
65e4a99a | 1786 | unknown_macro_argument: |
437e2ff1 | 1787 | as_fatal (_("internal: invalid macro argument `%s'"), fmtStart); |
e23eba97 NC |
1788 | } |
1789 | break; | |
1790 | } | |
1791 | va_end (args); | |
1792 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1793 | ||
1794 | append_insn (&insn, ep, r); | |
1795 | } | |
1796 | ||
db3b6ecc KC |
1797 | /* Build an instruction created by a macro expansion. Like md_assemble but |
1798 | accept a printf-style format string and arguments. */ | |
1799 | ||
1800 | static void | |
1801 | md_assemblef (const char *format, ...) | |
1802 | { | |
1803 | char *buf = NULL; | |
1804 | va_list ap; | |
1805 | int r; | |
1806 | ||
1807 | va_start (ap, format); | |
1808 | ||
1809 | r = vasprintf (&buf, format, ap); | |
1810 | ||
1811 | if (r < 0) | |
b800637e | 1812 | as_fatal (_("internal: vasprintf failed")); |
db3b6ecc KC |
1813 | |
1814 | md_assemble (buf); | |
1815 | free(buf); | |
1816 | ||
1817 | va_end (ap); | |
1818 | } | |
1819 | ||
e23eba97 NC |
1820 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits |
1821 | unset. */ | |
dcd709e0 | 1822 | |
e23eba97 NC |
1823 | static void |
1824 | normalize_constant_expr (expressionS *ex) | |
1825 | { | |
1826 | if (xlen > 32) | |
1827 | return; | |
1828 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
1829 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
1830 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
1831 | - 0x80000000); | |
1832 | } | |
1833 | ||
ca2fd32c JW |
1834 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
1835 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
1836 | |
1837 | static void | |
ca2fd32c | 1838 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
5b7c81bd | 1839 | bool maybe_csr) |
e23eba97 NC |
1840 | { |
1841 | if (ex->X_op == O_big) | |
1842 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
1843 | else if (maybe_csr && ex->X_op == O_symbol) |
1844 | as_bad (_("unknown CSR `%s'"), | |
1845 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 | 1846 | else if (ex->X_op != O_constant) |
b800637e | 1847 | as_bad (_("instruction %s requires absolute expression"), |
e23eba97 NC |
1848 | ip->insn_mo->name); |
1849 | normalize_constant_expr (ex); | |
1850 | } | |
1851 | ||
1852 | static symbolS * | |
1853 | make_internal_label (void) | |
1854 | { | |
e01e1cee AM |
1855 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now, |
1856 | frag_now_fix ()); | |
e23eba97 NC |
1857 | } |
1858 | ||
1859 | /* Load an entry from the GOT. */ | |
dcd709e0 | 1860 | |
e23eba97 NC |
1861 | static void |
1862 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
1863 | const char *lo_insn, const char *lo_pattern, | |
1864 | bfd_reloc_code_real_type hi_reloc, | |
1865 | bfd_reloc_code_real_type lo_reloc) | |
1866 | { | |
1867 | expressionS ep2; | |
1868 | ep2.X_op = O_symbol; | |
1869 | ep2.X_add_symbol = make_internal_label (); | |
1870 | ep2.X_add_number = 0; | |
1871 | ||
1872 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
1873 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
1874 | } | |
1875 | ||
1876 | static void | |
1877 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1878 | bfd_reloc_code_real_type hi_reloc, | |
1879 | bfd_reloc_code_real_type lo_reloc) | |
1880 | { | |
1881 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
1882 | } | |
1883 | ||
1884 | static void | |
1885 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1886 | bfd_reloc_code_real_type hi_reloc, | |
1887 | bfd_reloc_code_real_type lo_reloc) | |
1888 | { | |
1889 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
1890 | } | |
1891 | ||
1892 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
dcd709e0 | 1893 | |
e23eba97 NC |
1894 | static void |
1895 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
1896 | bfd_reloc_code_real_type reloc) | |
1897 | { | |
b1b11e92 AM |
1898 | /* Ensure the jalr is emitted to the same frag as the auipc. */ |
1899 | frag_grow (8); | |
e23eba97 NC |
1900 | macro_build (ep, "auipc", "d,u", tempreg, reloc); |
1901 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
b1b11e92 AM |
1902 | /* See comment at end of append_insn. */ |
1903 | frag_wane (frag_now); | |
1904 | frag_new (0); | |
e23eba97 NC |
1905 | } |
1906 | ||
1907 | /* Load an integer constant into a register. */ | |
1908 | ||
1909 | static void | |
1910 | load_const (int reg, expressionS *ep) | |
1911 | { | |
1912 | int shift = RISCV_IMM_BITS; | |
4f7cc141 | 1913 | bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1); |
e23eba97 | 1914 | expressionS upper = *ep, lower = *ep; |
4f7cc141 | 1915 | lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign; |
e23eba97 NC |
1916 | upper.X_add_number -= lower.X_add_number; |
1917 | ||
1918 | if (ep->X_op != O_constant) | |
1919 | { | |
1920 | as_bad (_("unsupported large constant")); | |
1921 | return; | |
1922 | } | |
1923 | ||
1d65abb5 | 1924 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1925 | { |
1926 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1927 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1928 | shift++; | |
1929 | ||
1930 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1931 | load_const (reg, &upper); |
e23eba97 | 1932 | |
db3b6ecc | 1933 | md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift); |
e23eba97 | 1934 | if (lower.X_add_number != 0) |
b8281767 AM |
1935 | md_assemblef ("addi x%d, x%d, %" PRId64, reg, reg, |
1936 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1937 | } |
1938 | else | |
1939 | { | |
1940 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1941 | int hi_reg = 0; | |
1942 | ||
1943 | if (upper.X_add_number != 0) | |
1944 | { | |
db3b6ecc KC |
1945 | /* Discard low part and zero-extend upper immediate. */ |
1946 | upper_imm = ((uint32_t)upper.X_add_number >> shift); | |
1947 | ||
b8281767 | 1948 | md_assemblef ("lui x%d, 0x%" PRIx64, reg, (uint64_t) upper_imm); |
e23eba97 NC |
1949 | hi_reg = reg; |
1950 | } | |
1951 | ||
1952 | if (lower.X_add_number != 0 || hi_reg == 0) | |
b8281767 AM |
1953 | md_assemblef ("%s x%d, x%d, %" PRId64, ADD32_INSN, reg, hi_reg, |
1954 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1955 | } |
1956 | } | |
1957 | ||
c2137f55 NC |
1958 | /* Zero extend and sign extend byte/half-word/word. */ |
1959 | ||
1960 | static void | |
5b7c81bd | 1961 | riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) |
c2137f55 | 1962 | { |
eb5e952f JB |
1963 | md_assemblef ("slli x%d, x%d, %#x", destreg, srcreg, shift); |
1964 | md_assemblef ("sr%ci x%d, x%d, %#x", | |
1965 | sign ? 'a' : 'l', destreg, destreg, shift); | |
c2137f55 NC |
1966 | } |
1967 | ||
65e4a99a NC |
1968 | /* Expand RISC-V Vector macros into one or more instructions. */ |
1969 | ||
1970 | static void | |
1971 | vector_macro (struct riscv_cl_insn *ip) | |
1972 | { | |
1973 | int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD; | |
1974 | int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1; | |
1975 | int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2; | |
1976 | int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK; | |
1977 | int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6; | |
d4868004 | 1978 | const char *vmslt_vx = ip->insn_mo->match ? "vmsltu.vx" : "vmslt.vx"; |
65e4a99a NC |
1979 | int mask = ip->insn_mo->mask; |
1980 | ||
1981 | switch (mask) | |
1982 | { | |
1983 | case M_VMSGE: | |
1984 | if (vm) | |
1985 | { | |
1986 | /* Unmasked. */ | |
d4868004 | 1987 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vd, vs2, vs1, -1); |
65e4a99a NC |
1988 | macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); |
1989 | break; | |
1990 | } | |
1991 | if (vtemp != 0) | |
1992 | { | |
1993 | /* Masked. Have vtemp to avoid overlap constraints. */ | |
1994 | if (vd == vm) | |
1995 | { | |
d4868004 | 1996 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vtemp, vs2, vs1, -1); |
65e4a99a NC |
1997 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); |
1998 | } | |
1999 | else | |
2000 | { | |
2001 | /* Preserve the value of vd if not updating by vm. */ | |
d4868004 | 2002 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vtemp, vs2, vs1, -1); |
65e4a99a NC |
2003 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); |
2004 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); | |
2005 | macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); | |
2006 | } | |
2007 | } | |
2008 | else if (vd != vm) | |
2009 | { | |
2010 | /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ | |
d4868004 | 2011 | macro_build (NULL, vmslt_vx, "Vd,Vt,sVm", vd, vs2, vs1, vm); |
65e4a99a NC |
2012 | macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); |
2013 | } | |
2014 | else | |
2015 | as_bad (_("must provide temp if destination overlaps mask")); | |
2016 | break; | |
2017 | ||
2018 | default: | |
2019 | break; | |
2020 | } | |
2021 | } | |
2022 | ||
e23eba97 | 2023 | /* Expand RISC-V assembly macros into one or more instructions. */ |
2652cfad | 2024 | |
e23eba97 NC |
2025 | static void |
2026 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
2027 | bfd_reloc_code_real_type *imm_reloc) | |
2028 | { | |
2029 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
2030 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
2031 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
2032 | int mask = ip->insn_mo->mask; | |
2033 | ||
2034 | switch (mask) | |
2035 | { | |
2036 | case M_LI: | |
2037 | load_const (rd, imm_expr); | |
2038 | break; | |
2039 | ||
2040 | case M_LA: | |
2041 | case M_LLA: | |
ec2260af | 2042 | case M_LGA: |
e23eba97 NC |
2043 | /* Load the address of a symbol into a register. */ |
2044 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
2045 | as_bad (_("offset too large")); | |
2046 | ||
2047 | if (imm_expr->X_op == O_constant) | |
2048 | load_const (rd, imm_expr); | |
ec2260af JW |
2049 | /* Global PIC symbol. */ |
2050 | else if ((riscv_opts.pic && mask == M_LA) | |
2051 | || mask == M_LGA) | |
e23eba97 NC |
2052 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, |
2053 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
ec2260af JW |
2054 | /* Local PIC symbol, or any non-PIC symbol. */ |
2055 | else | |
e23eba97 NC |
2056 | pcrel_load (rd, rd, imm_expr, "addi", |
2057 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2058 | break; | |
2059 | ||
2060 | case M_LA_TLS_GD: | |
2061 | pcrel_load (rd, rd, imm_expr, "addi", | |
2062 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2063 | break; | |
2064 | ||
2065 | case M_LA_TLS_IE: | |
2066 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
2067 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2068 | break; | |
2069 | ||
c76820a0 JB |
2070 | case M_Lx: |
2071 | pcrel_load (rd, rd, imm_expr, ip->insn_mo->name, | |
e23eba97 NC |
2072 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); |
2073 | break; | |
2074 | ||
c76820a0 JB |
2075 | case M_FLx: |
2076 | pcrel_load (rd, rs1, imm_expr, ip->insn_mo->name, | |
e23eba97 NC |
2077 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); |
2078 | break; | |
2079 | ||
c76820a0 JB |
2080 | case M_Sx_FSx: |
2081 | pcrel_store (rs2, rs1, imm_expr, ip->insn_mo->name, | |
e4bec45d JB |
2082 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); |
2083 | break; | |
2084 | ||
e23eba97 NC |
2085 | case M_CALL: |
2086 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
2087 | break; | |
2088 | ||
eb5e952f JB |
2089 | case M_EXTH: |
2090 | riscv_ext (rd, rs1, xlen - 16, *ip->insn_mo->name == 's'); | |
c2137f55 NC |
2091 | break; |
2092 | ||
2093 | case M_ZEXTW: | |
5b7c81bd | 2094 | riscv_ext (rd, rs1, xlen - 32, false); |
c2137f55 NC |
2095 | break; |
2096 | ||
2097 | case M_SEXTB: | |
5b7c81bd | 2098 | riscv_ext (rd, rs1, xlen - 8, true); |
c2137f55 NC |
2099 | break; |
2100 | ||
65e4a99a | 2101 | case M_VMSGE: |
65e4a99a NC |
2102 | vector_macro (ip); |
2103 | break; | |
2104 | ||
e23eba97 | 2105 | default: |
b800637e | 2106 | as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); |
e23eba97 NC |
2107 | break; |
2108 | } | |
2109 | } | |
2110 | ||
2111 | static const struct percent_op_match percent_op_utype[] = | |
2112 | { | |
85bd4bfb JB |
2113 | {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, |
2114 | {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
2115 | {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, | |
2116 | {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, | |
2117 | {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
2118 | {"hi", BFD_RELOC_RISCV_HI20}, | |
e23eba97 NC |
2119 | {0, 0} |
2120 | }; | |
2121 | ||
2122 | static const struct percent_op_match percent_op_itype[] = | |
2123 | { | |
85bd4bfb JB |
2124 | {"lo", BFD_RELOC_RISCV_LO12_I}, |
2125 | {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
2126 | {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
e23eba97 NC |
2127 | {0, 0} |
2128 | }; | |
2129 | ||
2130 | static const struct percent_op_match percent_op_stype[] = | |
2131 | { | |
85bd4bfb JB |
2132 | {"lo", BFD_RELOC_RISCV_LO12_S}, |
2133 | {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
2134 | {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
e23eba97 NC |
2135 | {0, 0} |
2136 | }; | |
2137 | ||
2138 | static const struct percent_op_match percent_op_rtype[] = | |
2139 | { | |
85bd4bfb | 2140 | {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, |
e23eba97 NC |
2141 | {0, 0} |
2142 | }; | |
2143 | ||
f50fabe4 JW |
2144 | static const struct percent_op_match percent_op_null[] = |
2145 | { | |
2146 | {0, 0} | |
2147 | }; | |
2148 | ||
e23eba97 NC |
2149 | /* Return true if *STR points to a relocation operator. When returning true, |
2150 | move *STR over the operator and store its relocation code in *RELOC. | |
2151 | Leave both *STR and *RELOC alone when returning false. */ | |
2152 | ||
5b7c81bd | 2153 | static bool |
e23eba97 NC |
2154 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, |
2155 | const struct percent_op_match *percent_op) | |
2156 | { | |
2157 | for ( ; percent_op->str; percent_op++) | |
85bd4bfb | 2158 | if (strncasecmp (*str + 1, percent_op->str, strlen (percent_op->str)) == 0) |
e23eba97 | 2159 | { |
85bd4bfb | 2160 | size_t len = 1 + strlen (percent_op->str); |
e23eba97 | 2161 | |
654dfab0 JB |
2162 | while (ISSPACE ((*str)[len])) |
2163 | ++len; | |
2164 | if ((*str)[len] != '(') | |
e23eba97 NC |
2165 | continue; |
2166 | ||
85bd4bfb | 2167 | *str += len; |
e23eba97 NC |
2168 | *reloc = percent_op->reloc; |
2169 | ||
2170 | /* Check whether the output BFD supports this relocation. | |
2171 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
2172 | if (*reloc != BFD_RELOC_UNUSED |
2173 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 | 2174 | { |
b800637e NC |
2175 | as_bad ("internal: relocation %s isn't supported by the " |
2176 | "current ABI", percent_op->str); | |
e23eba97 NC |
2177 | *reloc = BFD_RELOC_UNUSED; |
2178 | } | |
5b7c81bd | 2179 | return true; |
e23eba97 | 2180 | } |
5b7c81bd | 2181 | return false; |
e23eba97 NC |
2182 | } |
2183 | ||
2184 | static void | |
2185 | my_getExpression (expressionS *ep, char *str) | |
2186 | { | |
2187 | char *save_in; | |
2188 | ||
2189 | save_in = input_line_pointer; | |
2190 | input_line_pointer = str; | |
2191 | expression (ep); | |
6eb099ae | 2192 | expr_parse_end = input_line_pointer; |
e23eba97 NC |
2193 | input_line_pointer = save_in; |
2194 | } | |
2195 | ||
2196 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
2197 | expression in *EP and the relocation, if any, in RELOC. | |
2198 | Return the number of relocation operators used (0 or 1). | |
2199 | ||
6eb099ae AM |
2200 | On exit, EXPR_PARSE_END points to the first character after the |
2201 | expression. */ | |
e23eba97 NC |
2202 | |
2203 | static size_t | |
2204 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
2205 | char *str, const struct percent_op_match *percent_op) | |
2206 | { | |
2207 | size_t reloc_index; | |
7a29ee29 JB |
2208 | unsigned crux_depth, str_depth; |
2209 | bool orig_probing = probing_insn_operands; | |
e23eba97 NC |
2210 | char *crux; |
2211 | ||
e23eba97 | 2212 | /* Search for the start of the main expression. |
dcd709e0 NC |
2213 | |
2214 | End the loop with CRUX pointing to the start of the main expression and | |
2215 | with CRUX_DEPTH containing the number of open brackets at that point. */ | |
e23eba97 NC |
2216 | reloc_index = -1; |
2217 | str_depth = 0; | |
2218 | do | |
2219 | { | |
2220 | reloc_index++; | |
2221 | crux = str; | |
2222 | crux_depth = str_depth; | |
2223 | ||
2224 | /* Skip over whitespace and brackets, keeping count of the number | |
2225 | of brackets. */ | |
2226 | while (*str == ' ' || *str == '\t' || *str == '(') | |
2227 | if (*str++ == '(') | |
2228 | str_depth++; | |
2229 | } | |
2230 | while (*str == '%' | |
2231 | && reloc_index < 1 | |
2232 | && parse_relocation (&str, reloc, percent_op)); | |
2233 | ||
a5e756e6 JB |
2234 | if (*str == '%') |
2235 | { | |
2236 | /* expression() will choke on anything looking like an (unrecognized) | |
2237 | relocation specifier. Don't even call it, avoiding multiple (and | |
2238 | perhaps redundant) error messages; our caller will issue one. */ | |
2239 | ep->X_op = O_illegal; | |
2240 | return 0; | |
2241 | } | |
2242 | ||
7a29ee29 JB |
2243 | /* Anything inside parentheses or subject to a relocation operator cannot |
2244 | be a register and hence can be treated the same as operands to | |
2245 | directives (other than .insn). */ | |
2246 | if (str_depth || reloc_index) | |
2247 | probing_insn_operands = false; | |
2248 | ||
e23eba97 | 2249 | my_getExpression (ep, crux); |
6eb099ae | 2250 | str = expr_parse_end; |
e23eba97 | 2251 | |
7a29ee29 JB |
2252 | probing_insn_operands = orig_probing; |
2253 | ||
e23eba97 NC |
2254 | /* Match every open bracket. */ |
2255 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
2256 | if (*str++ == ')') | |
2257 | crux_depth--; | |
2258 | ||
2259 | if (crux_depth > 0) | |
2260 | as_bad ("unclosed '('"); | |
2261 | ||
6eb099ae | 2262 | expr_parse_end = str; |
e23eba97 NC |
2263 | |
2264 | return reloc_index; | |
2265 | } | |
2266 | ||
0e35537d | 2267 | /* Parse opcode name, could be an mnemonics or number. */ |
dcd709e0 | 2268 | |
0e35537d JW |
2269 | static size_t |
2270 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
408ab016 | 2271 | char *str) |
0e35537d JW |
2272 | { |
2273 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
2274 | ||
2275 | if (o != NULL) | |
2276 | { | |
2277 | ep->X_op = O_constant; | |
2278 | ep->X_add_number = o->val; | |
2279 | return 0; | |
2280 | } | |
2281 | ||
408ab016 | 2282 | return my_getSmallExpression (ep, reloc, str, percent_op_null); |
0e35537d JW |
2283 | } |
2284 | ||
65e4a99a | 2285 | /* Parse string STR as a vsetvli operand. Store the expression in *EP. |
6eb099ae AM |
2286 | On exit, EXPR_PARSE_END points to the first character after the |
2287 | expression. */ | |
65e4a99a NC |
2288 | |
2289 | static void | |
2290 | my_getVsetvliExpression (expressionS *ep, char *str) | |
2291 | { | |
2292 | unsigned int vsew_value = 0, vlmul_value = 0; | |
2293 | unsigned int vta_value = 0, vma_value = 0; | |
2294 | bfd_boolean vsew_found = FALSE, vlmul_found = FALSE; | |
2295 | bfd_boolean vta_found = FALSE, vma_found = FALSE; | |
2296 | ||
2297 | if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value)) | |
2298 | { | |
2299 | if (*str == ',') | |
2300 | ++str; | |
2301 | if (vsew_found) | |
2302 | as_bad (_("multiple vsew constants")); | |
2303 | vsew_found = TRUE; | |
2304 | } | |
2305 | if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value)) | |
2306 | { | |
2307 | if (*str == ',') | |
2308 | ++str; | |
2309 | if (vlmul_found) | |
2310 | as_bad (_("multiple vlmul constants")); | |
2311 | vlmul_found = TRUE; | |
2312 | } | |
2313 | if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value)) | |
2314 | { | |
2315 | if (*str == ',') | |
2316 | ++str; | |
2317 | if (vta_found) | |
2318 | as_bad (_("multiple vta constants")); | |
2319 | vta_found = TRUE; | |
2320 | } | |
2321 | if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value)) | |
2322 | { | |
2323 | if (*str == ',') | |
2324 | ++str; | |
2325 | if (vma_found) | |
2326 | as_bad (_("multiple vma constants")); | |
2327 | vma_found = TRUE; | |
2328 | } | |
2329 | ||
2330 | if (vsew_found || vlmul_found || vta_found || vma_found) | |
2331 | { | |
2332 | ep->X_op = O_constant; | |
2333 | ep->X_add_number = (vlmul_value << OP_SH_VLMUL) | |
2334 | | (vsew_value << OP_SH_VSEW) | |
2335 | | (vta_value << OP_SH_VTA) | |
2336 | | (vma_value << OP_SH_VMA); | |
6eb099ae | 2337 | expr_parse_end = str; |
65e4a99a NC |
2338 | } |
2339 | else | |
2340 | { | |
2341 | my_getExpression (ep, str); | |
6eb099ae | 2342 | str = expr_parse_end; |
65e4a99a NC |
2343 | } |
2344 | } | |
2345 | ||
f0531ed6 | 2346 | /* Detect and handle implicitly zero load-store offsets. For example, |
437e2ff1 | 2347 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such |
f0531ed6 JW |
2348 | an implicit offset was detected. */ |
2349 | ||
5b7c81bd | 2350 | static bool |
89424b1d | 2351 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
2352 | { |
2353 | /* Check whether there is only a single bracketed expression left. | |
2354 | If so, it must be the base register and the constant must be zero. */ | |
2355 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
2356 | { | |
89424b1d MR |
2357 | ep->X_op = O_constant; |
2358 | ep->X_add_number = 0; | |
5b7c81bd | 2359 | return true; |
f0531ed6 JW |
2360 | } |
2361 | ||
5b7c81bd | 2362 | return false; |
f0531ed6 JW |
2363 | } |
2364 | ||
54b2aec1 | 2365 | /* All RISC-V CSR instructions belong to one of these classes. */ |
54b2aec1 NC |
2366 | enum csr_insn_type |
2367 | { | |
2368 | INSN_NOT_CSR, | |
2369 | INSN_CSRRW, | |
2370 | INSN_CSRRS, | |
2371 | INSN_CSRRC | |
2372 | }; | |
2373 | ||
2374 | /* Return which CSR instruction is checking. */ | |
2375 | ||
2376 | static enum csr_insn_type | |
2377 | riscv_csr_insn_type (insn_t insn) | |
2378 | { | |
2379 | if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0 | |
2380 | || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0) | |
2381 | return INSN_CSRRW; | |
2382 | else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0 | |
2383 | || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0) | |
2384 | return INSN_CSRRS; | |
2385 | else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0 | |
2386 | || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0) | |
2387 | return INSN_CSRRC; | |
2388 | else | |
2389 | return INSN_NOT_CSR; | |
2390 | } | |
2391 | ||
2392 | /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write | |
2393 | CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of | |
2394 | CSR address is 0x3. */ | |
2395 | ||
5b7c81bd | 2396 | static bool |
54b2aec1 NC |
2397 | riscv_csr_read_only_check (insn_t insn) |
2398 | { | |
2399 | int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR; | |
2400 | int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1; | |
2401 | int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3); | |
2402 | enum csr_insn_type csr_insn = riscv_csr_insn_type (insn); | |
2403 | ||
2404 | if (readonly | |
2405 | && (((csr_insn == INSN_CSRRS | |
2406 | || csr_insn == INSN_CSRRC) | |
2407 | && rs1 != 0) | |
2408 | || csr_insn == INSN_CSRRW)) | |
5b7c81bd | 2409 | return false; |
54b2aec1 | 2410 | |
5b7c81bd | 2411 | return true; |
54b2aec1 NC |
2412 | } |
2413 | ||
437e2ff1 | 2414 | /* Return true if it is a privileged instruction. Otherwise, return false. |
1a79004f NC |
2415 | |
2416 | uret is actually a N-ext instruction. So it is better to regard it as | |
2417 | an user instruction rather than the priv instruction. | |
2418 | ||
2419 | hret is used to return from traps in H-mode. H-mode is removed since | |
2420 | the v1.10 priv spec, but probably be added in the new hypervisor spec. | |
2421 | Therefore, hret should be controlled by the hypervisor spec rather than | |
2422 | priv spec in the future. | |
2423 | ||
2424 | dret is defined in the debug spec, so it should be checked in the future, | |
2425 | too. */ | |
2426 | ||
5b7c81bd | 2427 | static bool |
1a79004f NC |
2428 | riscv_is_priv_insn (insn_t insn) |
2429 | { | |
2430 | return (((insn ^ MATCH_SRET) & MASK_SRET) == 0 | |
2431 | || ((insn ^ MATCH_MRET) & MASK_MRET) == 0 | |
2432 | || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0 | |
2433 | || ((insn ^ MATCH_WFI) & MASK_WFI) == 0 | |
2434 | /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to | |
dcd709e0 | 2435 | check it here to keep the compatible. */ |
1a79004f NC |
2436 | || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0); |
2437 | } | |
2438 | ||
7a29ee29 JB |
2439 | static symbolS *deferred_sym_rootP; |
2440 | static symbolS *deferred_sym_lastP; | |
2441 | /* Since symbols can't easily be freed, try to recycle ones which weren't | |
2442 | committed. */ | |
2443 | static symbolS *orphan_sym_rootP; | |
2444 | static symbolS *orphan_sym_lastP; | |
2445 | ||
e23eba97 NC |
2446 | /* This routine assembles an instruction into its binary format. As a |
2447 | side effect, it sets the global variable imm_reloc to the type of | |
2448 | relocation to do if one of the operands is an address expression. */ | |
2449 | ||
e4028336 | 2450 | static struct riscv_ip_error |
e23eba97 | 2451 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, |
629310ab | 2452 | bfd_reloc_code_real_type *imm_reloc, htab_t hash) |
e23eba97 | 2453 | { |
437e2ff1 NC |
2454 | /* The operand string defined in the riscv_opcodes. */ |
2455 | const char *oparg, *opargStart; | |
2456 | /* The parsed operands from assembly. */ | |
2457 | char *asarg, *asargStart; | |
2458 | char save_c = 0; | |
e23eba97 | 2459 | struct riscv_opcode *insn; |
e23eba97 | 2460 | unsigned int regno; |
e23eba97 | 2461 | const struct percent_op_match *p; |
e4028336 PN |
2462 | struct riscv_ip_error error; |
2463 | error.msg = "unrecognized opcode"; | |
2464 | error.statement = str; | |
2465 | error.missing_ext = NULL; | |
54b2aec1 | 2466 | /* Indicate we are assembling instruction with CSR. */ |
5b7c81bd | 2467 | bool insn_with_csr = false; |
e23eba97 NC |
2468 | |
2469 | /* Parse the name of the instruction. Terminate the string if whitespace | |
629310ab | 2470 | is found so that str_hash_find only sees the name part of the string. */ |
437e2ff1 NC |
2471 | for (asarg = str; *asarg!= '\0'; ++asarg) |
2472 | if (ISSPACE (*asarg)) | |
e23eba97 | 2473 | { |
437e2ff1 NC |
2474 | save_c = *asarg; |
2475 | *asarg++ = '\0'; | |
e23eba97 NC |
2476 | break; |
2477 | } | |
2478 | ||
629310ab | 2479 | insn = (struct riscv_opcode *) str_hash_find (hash, str); |
e23eba97 | 2480 | |
7a29ee29 JB |
2481 | probing_insn_operands = true; |
2482 | ||
437e2ff1 | 2483 | asargStart = asarg; |
e23eba97 NC |
2484 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) |
2485 | { | |
1080bf78 JW |
2486 | if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) |
2487 | continue; | |
2488 | ||
f786c359 | 2489 | if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) |
e4028336 PN |
2490 | { |
2491 | error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, | |
2492 | insn->insn_class); | |
2493 | continue; | |
2494 | } | |
e23eba97 | 2495 | |
65e4a99a | 2496 | /* Reset error message of the previous round. */ |
e4028336 PN |
2497 | error.msg = _("illegal operands"); |
2498 | error.missing_ext = NULL; | |
7a29ee29 JB |
2499 | |
2500 | /* Purge deferred symbols from the previous round, if any. */ | |
2501 | while (deferred_sym_rootP) | |
2502 | { | |
2503 | symbolS *sym = deferred_sym_rootP; | |
2504 | ||
2505 | symbol_remove (sym, &deferred_sym_rootP, &deferred_sym_lastP); | |
2506 | symbol_append (sym, orphan_sym_lastP, &orphan_sym_rootP, | |
2507 | &orphan_sym_lastP); | |
2508 | } | |
2509 | ||
e23eba97 | 2510 | create_insn (ip, insn); |
e23eba97 NC |
2511 | |
2512 | imm_expr->X_op = O_absent; | |
2513 | *imm_reloc = BFD_RELOC_UNUSED; | |
b33e94cf | 2514 | p = percent_op_null; |
e23eba97 | 2515 | |
437e2ff1 | 2516 | for (oparg = insn->args;; ++oparg) |
e23eba97 | 2517 | { |
437e2ff1 NC |
2518 | opargStart = oparg; |
2519 | asarg += strspn (asarg, " \t"); | |
2520 | switch (*oparg) | |
e23eba97 | 2521 | { |
dcd709e0 | 2522 | case '\0': /* End of args. */ |
27b33966 JB |
2523 | if (insn->match_func && !insn->match_func (insn, ip->insn_opcode)) |
2524 | break; | |
2525 | ||
e23eba97 NC |
2526 | if (insn->pinfo != INSN_MACRO) |
2527 | { | |
0e35537d JW |
2528 | /* For .insn, insn->match and insn->mask are 0. */ |
2529 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
2530 | ? ip->insn_opcode | |
2531 | : insn->match) == 2 | |
2532 | && !riscv_opts.rvc) | |
e23eba97 | 2533 | break; |
54b2aec1 | 2534 | |
1a79004f | 2535 | if (riscv_is_priv_insn (ip->insn_opcode)) |
5b7c81bd | 2536 | explicit_priv_attr = true; |
1a79004f | 2537 | |
54b2aec1 NC |
2538 | /* Check if we write a read-only CSR by the CSR |
2539 | instruction. */ | |
2540 | if (insn_with_csr | |
2541 | && riscv_opts.csr_check | |
2542 | && !riscv_csr_read_only_check (ip->insn_opcode)) | |
2543 | { | |
2544 | /* Restore the character in advance, since we want to | |
2545 | report the detailed warning message here. */ | |
2546 | if (save_c) | |
437e2ff1 | 2547 | *(asargStart - 1) = save_c; |
b800637e | 2548 | as_warn (_("read-only CSR is written `%s'"), str); |
5b7c81bd | 2549 | insn_with_csr = false; |
54b2aec1 | 2550 | } |
65e4a99a NC |
2551 | |
2552 | /* The (segmant) load and store with EEW 64 cannot be used | |
2553 | when zve32x is enabled. */ | |
2554 | if (ip->insn_mo->pinfo & INSN_V_EEW64 | |
2555 | && riscv_subset_supports (&riscv_rps_as, "zve32x") | |
2556 | && !riscv_subset_supports (&riscv_rps_as, "zve64x")) | |
2557 | { | |
e4028336 | 2558 | error.msg = _("illegal opcode for zve32x"); |
65e4a99a NC |
2559 | break; |
2560 | } | |
e23eba97 | 2561 | } |
437e2ff1 | 2562 | if (*asarg != '\0') |
e23eba97 | 2563 | break; |
7a29ee29 | 2564 | |
e23eba97 | 2565 | /* Successful assembly. */ |
e4028336 | 2566 | error.msg = NULL; |
5b7c81bd | 2567 | insn_with_csr = false; |
7a29ee29 JB |
2568 | |
2569 | /* Commit deferred symbols, if any. */ | |
2570 | while (deferred_sym_rootP) | |
2571 | { | |
2572 | symbolS *sym = deferred_sym_rootP; | |
2573 | ||
2574 | symbol_remove (sym, &deferred_sym_rootP, | |
2575 | &deferred_sym_lastP); | |
2576 | symbol_append (sym, symbol_lastP, &symbol_rootP, | |
2577 | &symbol_lastP); | |
2578 | symbol_table_insert (sym); | |
2579 | } | |
e23eba97 NC |
2580 | goto out; |
2581 | ||
2582 | case 'C': /* RVC */ | |
437e2ff1 | 2583 | switch (*++oparg) |
e23eba97 | 2584 | { |
dcd709e0 | 2585 | case 's': /* RS1 x8-x15. */ |
437e2ff1 | 2586 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2587 | || !(regno >= 8 && regno <= 15)) |
2588 | break; | |
2589 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2590 | continue; | |
2591 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2592 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2593 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) |
2594 | break; | |
2595 | continue; | |
dcd709e0 | 2596 | case 't': /* RS2 x8-x15. */ |
437e2ff1 | 2597 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2598 | || !(regno >= 8 && regno <= 15)) |
2599 | break; | |
2600 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2601 | continue; | |
2602 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2603 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2604 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) |
2605 | break; | |
2606 | continue; | |
2607 | case 'U': /* RS1, constrained to equal RD. */ | |
437e2ff1 | 2608 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2609 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) |
2610 | break; | |
2611 | continue; | |
2612 | case 'V': /* RS2 */ | |
437e2ff1 | 2613 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 NC |
2614 | break; |
2615 | INSERT_OPERAND (CRS2, *ip, regno); | |
2616 | continue; | |
2617 | case 'c': /* RS1, constrained to equal sp. */ | |
437e2ff1 | 2618 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2619 | || regno != X_SP) |
2620 | break; | |
2621 | continue; | |
dcd709e0 | 2622 | case 'z': /* RS2, constrained to equal x0. */ |
437e2ff1 | 2623 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
ca0bc150 JW |
2624 | || regno != 0) |
2625 | break; | |
2626 | continue; | |
768589d1 | 2627 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 2628 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2629 | || imm_expr->X_op != O_constant |
768589d1 | 2630 | || (unsigned long) imm_expr->X_add_number >= xlen) |
e23eba97 | 2631 | break; |
5a9f5403 | 2632 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
dc1e8a47 | 2633 | rvc_imm_done: |
6eb099ae | 2634 | asarg = expr_parse_end; |
e23eba97 NC |
2635 | imm_expr->X_op = O_absent; |
2636 | continue; | |
5a9f5403 | 2637 | case '5': |
437e2ff1 | 2638 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2639 | || imm_expr->X_op != O_constant |
5a9f5403 | 2640 | || imm_expr->X_add_number < 0 |
169ec512 | 2641 | || imm_expr->X_add_number >= 32 |
5a9f5403 | 2642 | || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2643 | break; |
0257c2ff | 2644 | ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number); |
e23eba97 | 2645 | goto rvc_imm_done; |
5a9f5403 | 2646 | case '6': |
437e2ff1 | 2647 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d | 2648 | || imm_expr->X_op != O_constant |
0e35537d | 2649 | || imm_expr->X_add_number < 0 |
5a9f5403 NC |
2650 | || imm_expr->X_add_number >= 64 |
2651 | || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
0e35537d | 2652 | break; |
0257c2ff | 2653 | ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number); |
0e35537d | 2654 | goto rvc_imm_done; |
5a9f5403 | 2655 | case '8': |
437e2ff1 | 2656 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2657 | || imm_expr->X_op != O_constant |
5a9f5403 NC |
2658 | || imm_expr->X_add_number < 0 |
2659 | || imm_expr->X_add_number >= 256 | |
2660 | || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
e23eba97 | 2661 | break; |
0257c2ff | 2662 | ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2663 | goto rvc_imm_done; |
2664 | case 'j': | |
437e2ff1 | 2665 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2666 | || imm_expr->X_op != O_constant |
2667 | || imm_expr->X_add_number == 0 | |
5a9f5403 | 2668 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2669 | break; |
5a9f5403 | 2670 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2671 | goto rvc_imm_done; |
2672 | case 'k': | |
437e2ff1 | 2673 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2674 | continue; |
437e2ff1 | 2675 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2676 | || imm_expr->X_op != O_constant |
5a9f5403 | 2677 | || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2678 | break; |
5a9f5403 | 2679 | ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2680 | goto rvc_imm_done; |
2681 | case 'l': | |
437e2ff1 | 2682 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2683 | continue; |
437e2ff1 | 2684 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2685 | || imm_expr->X_op != O_constant |
5a9f5403 | 2686 | || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2687 | break; |
5a9f5403 | 2688 | ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2689 | goto rvc_imm_done; |
2690 | case 'm': | |
437e2ff1 | 2691 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2692 | continue; |
437e2ff1 | 2693 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2694 | || imm_expr->X_op != O_constant |
5a9f5403 | 2695 | || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2696 | break; |
2697 | ip->insn_opcode |= | |
5a9f5403 | 2698 | ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2699 | goto rvc_imm_done; |
2700 | case 'n': | |
437e2ff1 | 2701 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2702 | continue; |
437e2ff1 | 2703 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2704 | || imm_expr->X_op != O_constant |
5a9f5403 | 2705 | || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2706 | break; |
2707 | ip->insn_opcode |= | |
5a9f5403 | 2708 | ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number); |
e23eba97 | 2709 | goto rvc_imm_done; |
b416fe87 | 2710 | case 'o': |
437e2ff1 | 2711 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
b416fe87 | 2712 | || imm_expr->X_op != O_constant |
21a186f2 JW |
2713 | /* C.addiw, c.li, and c.andi allow zero immediate. |
2714 | C.addi allows zero immediate as hint. Otherwise this | |
2715 | is same as 'j'. */ | |
5a9f5403 | 2716 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
b416fe87 | 2717 | break; |
5a9f5403 | 2718 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
b416fe87 | 2719 | goto rvc_imm_done; |
e23eba97 | 2720 | case 'K': |
437e2ff1 | 2721 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2722 | || imm_expr->X_op != O_constant |
169ec512 | 2723 | || imm_expr->X_add_number == 0 |
5a9f5403 | 2724 | || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2725 | break; |
2726 | ip->insn_opcode |= | |
5a9f5403 | 2727 | ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2728 | goto rvc_imm_done; |
2729 | case 'L': | |
437e2ff1 | 2730 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2731 | || imm_expr->X_op != O_constant |
5a9f5403 | 2732 | || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2733 | break; |
2734 | ip->insn_opcode |= | |
5a9f5403 | 2735 | ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2736 | goto rvc_imm_done; |
2737 | case 'M': | |
437e2ff1 | 2738 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2739 | continue; |
437e2ff1 | 2740 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2741 | || imm_expr->X_op != O_constant |
5a9f5403 | 2742 | || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2743 | break; |
2744 | ip->insn_opcode |= | |
5a9f5403 | 2745 | ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2746 | goto rvc_imm_done; |
2747 | case 'N': | |
437e2ff1 | 2748 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2749 | continue; |
437e2ff1 | 2750 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2751 | || imm_expr->X_op != O_constant |
5a9f5403 | 2752 | || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2753 | break; |
2754 | ip->insn_opcode |= | |
5a9f5403 | 2755 | ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2756 | goto rvc_imm_done; |
2757 | case 'u': | |
2758 | p = percent_op_utype; | |
437e2ff1 | 2759 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 2760 | break; |
dc1e8a47 | 2761 | rvc_lui: |
e23eba97 NC |
2762 | if (imm_expr->X_op != O_constant |
2763 | || imm_expr->X_add_number <= 0 | |
2764 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
2765 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
2766 | && (imm_expr->X_add_number < | |
2767 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
2768 | break; | |
5a9f5403 | 2769 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2770 | goto rvc_imm_done; |
2771 | case 'v': | |
437e2ff1 | 2772 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2773 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) |
2774 | || ((int32_t)imm_expr->X_add_number | |
2775 | != imm_expr->X_add_number)) | |
2776 | break; | |
2777 | imm_expr->X_add_number = | |
2778 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
2779 | goto rvc_lui; | |
2780 | case 'p': | |
2781 | goto branch; | |
2782 | case 'a': | |
2783 | goto jump; | |
0e35537d | 2784 | case 'S': /* Floating-point RS1 x8-x15. */ |
437e2ff1 | 2785 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
0e35537d JW |
2786 | || !(regno >= 8 && regno <= 15)) |
2787 | break; | |
2788 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2789 | continue; | |
e23eba97 | 2790 | case 'D': /* Floating-point RS2 x8-x15. */ |
437e2ff1 | 2791 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
e23eba97 NC |
2792 | || !(regno >= 8 && regno <= 15)) |
2793 | break; | |
2794 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2795 | continue; | |
2796 | case 'T': /* Floating-point RS2. */ | |
437e2ff1 | 2797 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no)) |
e23eba97 NC |
2798 | break; |
2799 | INSERT_OPERAND (CRS2, *ip, regno); | |
2800 | continue; | |
0e35537d | 2801 | case 'F': |
437e2ff1 | 2802 | switch (*++oparg) |
0e35537d | 2803 | { |
4765cd61 | 2804 | case '6': |
437e2ff1 | 2805 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2806 | || imm_expr->X_op != O_constant |
2807 | || imm_expr->X_add_number < 0 | |
2808 | || imm_expr->X_add_number >= 64) | |
2809 | { | |
b800637e | 2810 | as_bad (_("bad value for compressed funct6 " |
b215cdf5 | 2811 | "field, value must be 0...63")); |
4765cd61 JW |
2812 | break; |
2813 | } | |
4765cd61 JW |
2814 | INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); |
2815 | imm_expr->X_op = O_absent; | |
6eb099ae | 2816 | asarg = expr_parse_end; |
4765cd61 | 2817 | continue; |
1942a048 | 2818 | |
0e35537d | 2819 | case '4': |
437e2ff1 | 2820 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2821 | || imm_expr->X_op != O_constant |
2822 | || imm_expr->X_add_number < 0 | |
2823 | || imm_expr->X_add_number >= 16) | |
2824 | { | |
b800637e NC |
2825 | as_bad (_("bad value for compressed funct4 " |
2826 | "field, value must be 0...15")); | |
0e35537d JW |
2827 | break; |
2828 | } | |
0e35537d JW |
2829 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); |
2830 | imm_expr->X_op = O_absent; | |
6eb099ae | 2831 | asarg = expr_parse_end; |
0e35537d | 2832 | continue; |
1942a048 | 2833 | |
0e35537d | 2834 | case '3': |
437e2ff1 | 2835 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2836 | || imm_expr->X_op != O_constant |
2837 | || imm_expr->X_add_number < 0 | |
2838 | || imm_expr->X_add_number >= 8) | |
2839 | { | |
b800637e NC |
2840 | as_bad (_("bad value for compressed funct3 " |
2841 | "field, value must be 0...7")); | |
0e35537d JW |
2842 | break; |
2843 | } | |
2844 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
2845 | imm_expr->X_op = O_absent; | |
6eb099ae | 2846 | asarg = expr_parse_end; |
0e35537d | 2847 | continue; |
1942a048 | 2848 | |
4765cd61 | 2849 | case '2': |
437e2ff1 | 2850 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2851 | || imm_expr->X_op != O_constant |
2852 | || imm_expr->X_add_number < 0 | |
2853 | || imm_expr->X_add_number >= 4) | |
2854 | { | |
b800637e NC |
2855 | as_bad (_("bad value for compressed funct2 " |
2856 | "field, value must be 0...3")); | |
4765cd61 JW |
2857 | break; |
2858 | } | |
2859 | INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); | |
2860 | imm_expr->X_op = O_absent; | |
6eb099ae | 2861 | asarg = expr_parse_end; |
4765cd61 | 2862 | continue; |
1942a048 | 2863 | |
0e35537d | 2864 | default: |
437e2ff1 | 2865 | goto unknown_riscv_ip_operand; |
0e35537d JW |
2866 | } |
2867 | break; | |
2868 | ||
e23eba97 | 2869 | default: |
437e2ff1 | 2870 | goto unknown_riscv_ip_operand; |
e23eba97 | 2871 | } |
a63375ac | 2872 | break; /* end RVC */ |
e23eba97 | 2873 | |
65e4a99a NC |
2874 | case 'V': /* RVV */ |
2875 | switch (*++oparg) | |
2876 | { | |
2877 | case 'd': /* VD */ | |
2878 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2879 | break; | |
2880 | INSERT_OPERAND (VD, *ip, regno); | |
2881 | continue; | |
2882 | ||
2883 | case 'e': /* AMO VD */ | |
2884 | if (reg_lookup (&asarg, RCLASS_GPR, ®no) && regno == 0) | |
2885 | INSERT_OPERAND (VWD, *ip, 0); | |
2886 | else if (reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2887 | { | |
2888 | INSERT_OPERAND (VWD, *ip, 1); | |
2889 | INSERT_OPERAND (VD, *ip, regno); | |
2890 | } | |
2891 | else | |
2892 | break; | |
2893 | continue; | |
2894 | ||
2895 | case 'f': /* AMO VS3 */ | |
2896 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2897 | break; | |
2898 | if (!EXTRACT_OPERAND (VWD, ip->insn_opcode)) | |
2899 | INSERT_OPERAND (VD, *ip, regno); | |
2900 | else | |
2901 | { | |
2902 | /* VS3 must match VD. */ | |
2903 | if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno) | |
2904 | break; | |
2905 | } | |
2906 | continue; | |
2907 | ||
2908 | case 's': /* VS1 */ | |
2909 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2910 | break; | |
2911 | INSERT_OPERAND (VS1, *ip, regno); | |
2912 | continue; | |
2913 | ||
2914 | case 't': /* VS2 */ | |
2915 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2916 | break; | |
2917 | INSERT_OPERAND (VS2, *ip, regno); | |
2918 | continue; | |
2919 | ||
2920 | case 'u': /* VS1 == VS2 */ | |
2921 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2922 | break; | |
2923 | INSERT_OPERAND (VS1, *ip, regno); | |
2924 | INSERT_OPERAND (VS2, *ip, regno); | |
2925 | continue; | |
2926 | ||
2927 | case 'v': /* VD == VS1 == VS2 */ | |
2928 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2929 | break; | |
2930 | INSERT_OPERAND (VD, *ip, regno); | |
2931 | INSERT_OPERAND (VS1, *ip, regno); | |
2932 | INSERT_OPERAND (VS2, *ip, regno); | |
2933 | continue; | |
2934 | ||
2935 | /* The `V0` is carry-in register for v[m]adc and v[m]sbc, | |
2936 | and is used to choose vs1/rs1/frs1/imm or vs2 for | |
2937 | v[f]merge. It use the same encoding as the vector mask | |
2938 | register. */ | |
2939 | case '0': | |
2940 | if (reg_lookup (&asarg, RCLASS_VECR, ®no) && regno == 0) | |
2941 | continue; | |
2942 | break; | |
2943 | ||
2944 | case 'b': /* vtypei for vsetivli */ | |
2945 | my_getVsetvliExpression (imm_expr, asarg); | |
2946 | check_absolute_expr (ip, imm_expr, FALSE); | |
2947 | if (!VALID_RVV_VB_IMM (imm_expr->X_add_number)) | |
2948 | as_bad (_("bad value for vsetivli immediate field, " | |
2949 | "value must be 0..1023")); | |
2950 | ip->insn_opcode | |
2951 | |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number); | |
2952 | imm_expr->X_op = O_absent; | |
6eb099ae | 2953 | asarg = expr_parse_end; |
65e4a99a NC |
2954 | continue; |
2955 | ||
2956 | case 'c': /* vtypei for vsetvli */ | |
2957 | my_getVsetvliExpression (imm_expr, asarg); | |
2958 | check_absolute_expr (ip, imm_expr, FALSE); | |
2959 | if (!VALID_RVV_VC_IMM (imm_expr->X_add_number)) | |
2960 | as_bad (_("bad value for vsetvli immediate field, " | |
2961 | "value must be 0..2047")); | |
2962 | ip->insn_opcode | |
2963 | |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number); | |
2964 | imm_expr->X_op = O_absent; | |
6eb099ae | 2965 | asarg = expr_parse_end; |
65e4a99a NC |
2966 | continue; |
2967 | ||
2968 | case 'i': /* vector arith signed immediate */ | |
2969 | my_getExpression (imm_expr, asarg); | |
2970 | check_absolute_expr (ip, imm_expr, FALSE); | |
2971 | if (imm_expr->X_add_number > 15 | |
2972 | || imm_expr->X_add_number < -16) | |
2973 | as_bad (_("bad value for vector immediate field, " | |
2974 | "value must be -16...15")); | |
2975 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
2976 | imm_expr->X_op = O_absent; | |
6eb099ae | 2977 | asarg = expr_parse_end; |
65e4a99a NC |
2978 | continue; |
2979 | ||
2980 | case 'j': /* vector arith unsigned immediate */ | |
2981 | my_getExpression (imm_expr, asarg); | |
2982 | check_absolute_expr (ip, imm_expr, FALSE); | |
2983 | if (imm_expr->X_add_number < 0 | |
2984 | || imm_expr->X_add_number >= 32) | |
2985 | as_bad (_("bad value for vector immediate field, " | |
2986 | "value must be 0...31")); | |
2987 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
2988 | imm_expr->X_op = O_absent; | |
6eb099ae | 2989 | asarg = expr_parse_end; |
65e4a99a NC |
2990 | continue; |
2991 | ||
2992 | case 'k': /* vector arith signed immediate, minus 1 */ | |
2993 | my_getExpression (imm_expr, asarg); | |
2994 | check_absolute_expr (ip, imm_expr, FALSE); | |
2995 | if (imm_expr->X_add_number > 16 | |
2996 | || imm_expr->X_add_number < -15) | |
2997 | as_bad (_("bad value for vector immediate field, " | |
2998 | "value must be -15...16")); | |
2999 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1); | |
3000 | imm_expr->X_op = O_absent; | |
6eb099ae | 3001 | asarg = expr_parse_end; |
65e4a99a NC |
3002 | continue; |
3003 | ||
c8cb3734 CM |
3004 | case 'l': /* 6-bit vector arith unsigned immediate */ |
3005 | my_getExpression (imm_expr, asarg); | |
3006 | check_absolute_expr (ip, imm_expr, FALSE); | |
3007 | if (imm_expr->X_add_number < 0 | |
3008 | || imm_expr->X_add_number >= 64) | |
3009 | as_bad (_("bad value for vector immediate field, " | |
3010 | "value must be 0...63")); | |
3011 | ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number); | |
3012 | imm_expr->X_op = O_absent; | |
3013 | asarg = expr_parse_end; | |
3014 | continue; | |
3015 | ||
65e4a99a NC |
3016 | case 'm': /* optional vector mask */ |
3017 | if (*asarg == '\0') | |
3018 | { | |
3019 | INSERT_OPERAND (VMASK, *ip, 1); | |
3020 | continue; | |
3021 | } | |
3022 | else if (*asarg == ',' && asarg++ | |
3023 | && reg_lookup (&asarg, RCLASS_VECM, ®no) | |
3024 | && regno == 0) | |
3025 | { | |
3026 | INSERT_OPERAND (VMASK, *ip, 0); | |
3027 | continue; | |
3028 | } | |
3029 | break; | |
3030 | ||
3031 | case 'M': /* required vector mask */ | |
3032 | if (reg_lookup (&asarg, RCLASS_VECM, ®no) && regno == 0) | |
3033 | { | |
3034 | INSERT_OPERAND (VMASK, *ip, 0); | |
3035 | continue; | |
3036 | } | |
3037 | break; | |
3038 | ||
3039 | case 'T': /* vector macro temporary register */ | |
3040 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no) || regno == 0) | |
3041 | break; | |
3042 | /* Store it in the FUNCT6 field as we don't have anyplace | |
3043 | else to store it. */ | |
3044 | INSERT_OPERAND (VFUNCT6, *ip, regno); | |
3045 | continue; | |
3046 | ||
3047 | default: | |
3048 | goto unknown_riscv_ip_operand; | |
3049 | } | |
a63375ac | 3050 | break; /* end RVV */ |
65e4a99a | 3051 | |
e23eba97 | 3052 | case ',': |
437e2ff1 | 3053 | if (*asarg++ == *oparg) |
e23eba97 | 3054 | continue; |
437e2ff1 | 3055 | asarg--; |
e23eba97 NC |
3056 | break; |
3057 | ||
3058 | case '(': | |
3059 | case ')': | |
3060 | case '[': | |
3061 | case ']': | |
437e2ff1 | 3062 | if (*asarg++ == *oparg) |
e23eba97 NC |
3063 | continue; |
3064 | break; | |
3065 | ||
dcd709e0 | 3066 | case '<': /* Shift amount, 0 - 31. */ |
437e2ff1 | 3067 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3068 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3069 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3070 | as_bad (_("improper shift amount (%"PRIu64")"), |
3071 | imm_expr->X_add_number); | |
e23eba97 NC |
3072 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
3073 | imm_expr->X_op = O_absent; | |
6eb099ae | 3074 | asarg = expr_parse_end; |
e23eba97 NC |
3075 | continue; |
3076 | ||
dcd709e0 | 3077 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 3078 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3079 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3080 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
a6eeb20a CM |
3081 | as_bad (_("improper shift amount (%"PRIu64")"), |
3082 | imm_expr->X_add_number); | |
e23eba97 NC |
3083 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
3084 | imm_expr->X_op = O_absent; | |
6eb099ae | 3085 | asarg = expr_parse_end; |
e23eba97 NC |
3086 | continue; |
3087 | ||
dcd709e0 | 3088 | case 'Z': /* CSRRxI immediate. */ |
437e2ff1 | 3089 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3090 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3091 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3092 | as_bad (_("improper CSRxI immediate (%"PRIu64")"), |
3093 | imm_expr->X_add_number); | |
e23eba97 NC |
3094 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
3095 | imm_expr->X_op = O_absent; | |
6eb099ae | 3096 | asarg = expr_parse_end; |
e23eba97 NC |
3097 | continue; |
3098 | ||
dcd709e0 | 3099 | case 'E': /* Control register. */ |
5b7c81bd AM |
3100 | insn_with_csr = true; |
3101 | explicit_priv_attr = true; | |
437e2ff1 | 3102 | if (reg_lookup (&asarg, RCLASS_CSR, ®no)) |
e23eba97 NC |
3103 | INSERT_OPERAND (CSR, *ip, regno); |
3104 | else | |
3105 | { | |
437e2ff1 | 3106 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3107 | check_absolute_expr (ip, imm_expr, true); |
e23eba97 | 3108 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
a6eeb20a CM |
3109 | as_bad (_("improper CSR address (%"PRIu64")"), |
3110 | imm_expr->X_add_number); | |
e23eba97 NC |
3111 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
3112 | imm_expr->X_op = O_absent; | |
6eb099ae | 3113 | asarg = expr_parse_end; |
e23eba97 NC |
3114 | } |
3115 | continue; | |
3116 | ||
dcd709e0 | 3117 | case 'm': /* Rounding mode. */ |
437e2ff1 NC |
3118 | if (arg_lookup (&asarg, riscv_rm, |
3119 | ARRAY_SIZE (riscv_rm), ®no)) | |
e23eba97 NC |
3120 | { |
3121 | INSERT_OPERAND (RM, *ip, regno); | |
3122 | continue; | |
3123 | } | |
3124 | break; | |
3125 | ||
3126 | case 'P': | |
dcd709e0 | 3127 | case 'Q': /* Fence predecessor/successor. */ |
437e2ff1 NC |
3128 | if (arg_lookup (&asarg, riscv_pred_succ, |
3129 | ARRAY_SIZE (riscv_pred_succ), ®no)) | |
e23eba97 | 3130 | { |
437e2ff1 | 3131 | if (*oparg == 'P') |
e23eba97 NC |
3132 | INSERT_OPERAND (PRED, *ip, regno); |
3133 | else | |
3134 | INSERT_OPERAND (SUCC, *ip, regno); | |
3135 | continue; | |
3136 | } | |
3137 | break; | |
3138 | ||
dcd709e0 NC |
3139 | case 'd': /* Destination register. */ |
3140 | case 's': /* Source register. */ | |
3141 | case 't': /* Target register. */ | |
3142 | case 'r': /* RS3 */ | |
437e2ff1 | 3143 | if (reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 | 3144 | { |
437e2ff1 NC |
3145 | char c = *oparg; |
3146 | if (*asarg == ' ') | |
3147 | ++asarg; | |
e23eba97 NC |
3148 | |
3149 | /* Now that we have assembled one operand, we use the args | |
3150 | string to figure out where it goes in the instruction. */ | |
3151 | switch (c) | |
3152 | { | |
3153 | case 's': | |
3154 | INSERT_OPERAND (RS1, *ip, regno); | |
3155 | break; | |
3156 | case 'd': | |
3157 | INSERT_OPERAND (RD, *ip, regno); | |
3158 | break; | |
3159 | case 't': | |
3160 | INSERT_OPERAND (RS2, *ip, regno); | |
3161 | break; | |
0e35537d JW |
3162 | case 'r': |
3163 | INSERT_OPERAND (RS3, *ip, regno); | |
3164 | break; | |
e23eba97 NC |
3165 | } |
3166 | continue; | |
3167 | } | |
3168 | break; | |
3169 | ||
dcd709e0 NC |
3170 | case 'D': /* Floating point RD. */ |
3171 | case 'S': /* Floating point RS1. */ | |
3172 | case 'T': /* Floating point RS2. */ | |
3173 | case 'U': /* Floating point RS1 and RS2. */ | |
3174 | case 'R': /* Floating point RS3. */ | |
de83e514 | 3175 | if (reg_lookup (&asarg, |
3176 | (riscv_subset_supports (&riscv_rps_as, "zfinx") | |
3177 | ? RCLASS_GPR : RCLASS_FPR), ®no)) | |
e23eba97 | 3178 | { |
437e2ff1 NC |
3179 | char c = *oparg; |
3180 | if (*asarg == ' ') | |
3181 | ++asarg; | |
e23eba97 NC |
3182 | switch (c) |
3183 | { | |
3184 | case 'D': | |
3185 | INSERT_OPERAND (RD, *ip, regno); | |
3186 | break; | |
3187 | case 'S': | |
3188 | INSERT_OPERAND (RS1, *ip, regno); | |
3189 | break; | |
3190 | case 'U': | |
3191 | INSERT_OPERAND (RS1, *ip, regno); | |
dcd709e0 | 3192 | /* Fall through. */ |
e23eba97 NC |
3193 | case 'T': |
3194 | INSERT_OPERAND (RS2, *ip, regno); | |
3195 | break; | |
3196 | case 'R': | |
3197 | INSERT_OPERAND (RS3, *ip, regno); | |
3198 | break; | |
3199 | } | |
3200 | continue; | |
3201 | } | |
e23eba97 NC |
3202 | break; |
3203 | ||
3204 | case 'I': | |
437e2ff1 | 3205 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3206 | if (imm_expr->X_op != O_big |
3207 | && imm_expr->X_op != O_constant) | |
3208 | break; | |
3209 | normalize_constant_expr (imm_expr); | |
6eb099ae | 3210 | asarg = expr_parse_end; |
e23eba97 NC |
3211 | continue; |
3212 | ||
3213 | case 'A': | |
437e2ff1 | 3214 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3215 | normalize_constant_expr (imm_expr); |
3216 | /* The 'A' format specifier must be a symbol. */ | |
3217 | if (imm_expr->X_op != O_symbol) | |
3218 | break; | |
3219 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3220 | asarg = expr_parse_end; |
e23eba97 NC |
3221 | continue; |
3222 | ||
160d1b3d | 3223 | case 'B': |
437e2ff1 | 3224 | my_getExpression (imm_expr, asarg); |
160d1b3d SH |
3225 | normalize_constant_expr (imm_expr); |
3226 | /* The 'B' format specifier must be a symbol or a constant. */ | |
3227 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
3228 | break; | |
3229 | if (imm_expr->X_op == O_symbol) | |
3230 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3231 | asarg = expr_parse_end; |
160d1b3d SH |
3232 | continue; |
3233 | ||
e23eba97 | 3234 | case 'j': /* Sign-extended immediate. */ |
e23eba97 | 3235 | p = percent_op_itype; |
f50fabe4 | 3236 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; |
e23eba97 NC |
3237 | goto alu_op; |
3238 | case 'q': /* Store displacement. */ | |
3239 | p = percent_op_stype; | |
3240 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
3241 | goto load_store; | |
3242 | case 'o': /* Load displacement. */ | |
3243 | p = percent_op_itype; | |
3244 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
3245 | goto load_store; | |
dcd709e0 NC |
3246 | case '1': |
3247 | /* This is used for TLS, where the fourth operand is | |
3248 | %tprel_add, to get a relocation applied to an add | |
3249 | instruction, for relaxation to use. */ | |
e23eba97 | 3250 | p = percent_op_rtype; |
f50fabe4 | 3251 | goto alu_op; |
dcd709e0 | 3252 | case '0': /* AMO displacement, which must be zero. */ |
dc1e8a47 | 3253 | load_store: |
437e2ff1 | 3254 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
e23eba97 | 3255 | continue; |
dc1e8a47 | 3256 | alu_op: |
e23eba97 NC |
3257 | /* If this value won't fit into a 16 bit offset, then go |
3258 | find a macro that will generate the 32 bit offset | |
3259 | code pattern. */ | |
437e2ff1 | 3260 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 NC |
3261 | { |
3262 | normalize_constant_expr (imm_expr); | |
3263 | if (imm_expr->X_op != O_constant | |
437e2ff1 NC |
3264 | || (*oparg == '0' && imm_expr->X_add_number != 0) |
3265 | || (*oparg == '1') | |
e23eba97 NC |
3266 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 |
3267 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
3268 | break; | |
3269 | } | |
6eb099ae | 3270 | asarg = expr_parse_end; |
e23eba97 NC |
3271 | continue; |
3272 | ||
dcd709e0 | 3273 | case 'p': /* PC-relative offset. */ |
dc1e8a47 | 3274 | branch: |
e23eba97 | 3275 | *imm_reloc = BFD_RELOC_12_PCREL; |
437e2ff1 | 3276 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3277 | asarg = expr_parse_end; |
e23eba97 NC |
3278 | continue; |
3279 | ||
dcd709e0 | 3280 | case 'u': /* Upper 20 bits. */ |
e23eba97 | 3281 | p = percent_op_utype; |
437e2ff1 | 3282 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 3283 | { |
4288405d JW |
3284 | if (imm_expr->X_op != O_constant) |
3285 | break; | |
3286 | ||
e23eba97 NC |
3287 | if (imm_expr->X_add_number < 0 |
3288 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
3289 | as_bad (_("lui expression not in range 0..1048575")); | |
3290 | ||
3291 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
3292 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
3293 | } | |
6eb099ae | 3294 | asarg = expr_parse_end; |
e23eba97 NC |
3295 | continue; |
3296 | ||
dcd709e0 | 3297 | case 'a': /* 20-bit PC-relative offset. */ |
dc1e8a47 | 3298 | jump: |
437e2ff1 | 3299 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3300 | asarg = expr_parse_end; |
e23eba97 NC |
3301 | *imm_reloc = BFD_RELOC_RISCV_JMP; |
3302 | continue; | |
3303 | ||
3304 | case 'c': | |
437e2ff1 | 3305 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3306 | asarg = expr_parse_end; |
437e2ff1 | 3307 | if (strcmp (asarg, "@plt") == 0) |
70f35d72 NC |
3308 | asarg += 4; |
3309 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
e23eba97 | 3310 | continue; |
1942a048 | 3311 | |
0e35537d | 3312 | case 'O': |
437e2ff1 | 3313 | switch (*++oparg) |
0e35537d JW |
3314 | { |
3315 | case '4': | |
408ab016 | 3316 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg) |
0e35537d JW |
3317 | || imm_expr->X_op != O_constant |
3318 | || imm_expr->X_add_number < 0 | |
3319 | || imm_expr->X_add_number >= 128 | |
3320 | || (imm_expr->X_add_number & 0x3) != 3) | |
3321 | { | |
3322 | as_bad (_("bad value for opcode field, " | |
3323 | "value must be 0...127 and " | |
3324 | "lower 2 bits must be 0x3")); | |
3325 | break; | |
3326 | } | |
0e35537d JW |
3327 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); |
3328 | imm_expr->X_op = O_absent; | |
6eb099ae | 3329 | asarg = expr_parse_end; |
0e35537d | 3330 | continue; |
1942a048 | 3331 | |
0e35537d | 3332 | case '2': |
408ab016 | 3333 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg) |
0e35537d JW |
3334 | || imm_expr->X_op != O_constant |
3335 | || imm_expr->X_add_number < 0 | |
3336 | || imm_expr->X_add_number >= 3) | |
3337 | { | |
3338 | as_bad (_("bad value for opcode field, " | |
3339 | "value must be 0...2")); | |
3340 | break; | |
3341 | } | |
0e35537d JW |
3342 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); |
3343 | imm_expr->X_op = O_absent; | |
6eb099ae | 3344 | asarg = expr_parse_end; |
0e35537d | 3345 | continue; |
1942a048 | 3346 | |
0e35537d | 3347 | default: |
437e2ff1 | 3348 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3349 | } |
3350 | break; | |
3351 | ||
3352 | case 'F': | |
437e2ff1 | 3353 | switch (*++oparg) |
0e35537d JW |
3354 | { |
3355 | case '7': | |
437e2ff1 | 3356 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3357 | || imm_expr->X_op != O_constant |
3358 | || imm_expr->X_add_number < 0 | |
3359 | || imm_expr->X_add_number >= 128) | |
3360 | { | |
3361 | as_bad (_("bad value for funct7 field, " | |
3362 | "value must be 0...127")); | |
3363 | break; | |
3364 | } | |
0e35537d JW |
3365 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); |
3366 | imm_expr->X_op = O_absent; | |
6eb099ae | 3367 | asarg = expr_parse_end; |
0e35537d | 3368 | continue; |
1942a048 | 3369 | |
0e35537d | 3370 | case '3': |
437e2ff1 | 3371 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3372 | || imm_expr->X_op != O_constant |
3373 | || imm_expr->X_add_number < 0 | |
3374 | || imm_expr->X_add_number >= 8) | |
3375 | { | |
3376 | as_bad (_("bad value for funct3 field, " | |
3377 | "value must be 0...7")); | |
3378 | break; | |
3379 | } | |
0e35537d JW |
3380 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); |
3381 | imm_expr->X_op = O_absent; | |
6eb099ae | 3382 | asarg = expr_parse_end; |
0e35537d | 3383 | continue; |
1942a048 | 3384 | |
0e35537d | 3385 | case '2': |
437e2ff1 | 3386 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3387 | || imm_expr->X_op != O_constant |
3388 | || imm_expr->X_add_number < 0 | |
3389 | || imm_expr->X_add_number >= 4) | |
3390 | { | |
3391 | as_bad (_("bad value for funct2 field, " | |
3392 | "value must be 0...3")); | |
3393 | break; | |
3394 | } | |
0e35537d JW |
3395 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); |
3396 | imm_expr->X_op = O_absent; | |
6eb099ae | 3397 | asarg = expr_parse_end; |
0e35537d JW |
3398 | continue; |
3399 | ||
3400 | default: | |
437e2ff1 | 3401 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3402 | } |
3403 | break; | |
e23eba97 | 3404 | |
3d1cafa0 | 3405 | case 'y': /* bs immediate */ |
3406 | my_getExpression (imm_expr, asarg); | |
3407 | check_absolute_expr (ip, imm_expr, FALSE); | |
3408 | if ((unsigned long)imm_expr->X_add_number > 3) | |
3409 | as_bad(_("Improper bs immediate (%lu)"), | |
3410 | (unsigned long)imm_expr->X_add_number); | |
3411 | INSERT_OPERAND(BS, *ip, imm_expr->X_add_number); | |
3412 | imm_expr->X_op = O_absent; | |
6eb099ae | 3413 | asarg = expr_parse_end; |
3d1cafa0 | 3414 | continue; |
3415 | ||
3416 | case 'Y': /* rnum immediate */ | |
3417 | my_getExpression (imm_expr, asarg); | |
3418 | check_absolute_expr (ip, imm_expr, FALSE); | |
3419 | if ((unsigned long)imm_expr->X_add_number > 10) | |
3420 | as_bad(_("Improper rnum immediate (%lu)"), | |
3421 | (unsigned long)imm_expr->X_add_number); | |
3422 | INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number); | |
3423 | imm_expr->X_op = O_absent; | |
6eb099ae | 3424 | asarg = expr_parse_end; |
3d1cafa0 | 3425 | continue; |
3426 | ||
e925c834 | 3427 | case 'z': |
437e2ff1 | 3428 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e925c834 JW |
3429 | || imm_expr->X_op != O_constant |
3430 | || imm_expr->X_add_number != 0) | |
3431 | break; | |
6eb099ae | 3432 | asarg = expr_parse_end; |
e925c834 JW |
3433 | imm_expr->X_op = O_absent; |
3434 | continue; | |
3435 | ||
6de11ff6 | 3436 | case 'W': /* Various operands for standard z extensions. */ |
54bca63b TO |
3437 | switch (*++oparg) |
3438 | { | |
3439 | case 'i': | |
3440 | switch (*++oparg) | |
3441 | { | |
3442 | case 'f': | |
3443 | /* Prefetch offset for 'Zicbop' extension. | |
3444 | pseudo S-type but lower 5-bits zero. */ | |
3445 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3446 | continue; | |
3447 | my_getExpression (imm_expr, asarg); | |
3448 | check_absolute_expr (ip, imm_expr, false); | |
3449 | if (((unsigned) (imm_expr->X_add_number) & 0x1fU) | |
3450 | || imm_expr->X_add_number >= RISCV_IMM_REACH / 2 | |
3451 | || imm_expr->X_add_number < -RISCV_IMM_REACH / 2) | |
3452 | as_bad (_ ("improper prefetch offset (%ld)"), | |
3453 | (long) imm_expr->X_add_number); | |
3454 | ip->insn_opcode |= ENCODE_STYPE_IMM ( | |
3455 | (unsigned) (imm_expr->X_add_number) & ~0x1fU); | |
3456 | imm_expr->X_op = O_absent; | |
3457 | asarg = expr_parse_end; | |
3458 | continue; | |
3459 | default: | |
3460 | goto unknown_riscv_ip_operand; | |
3461 | } | |
3462 | break; | |
6de11ff6 | 3463 | |
1f3fc45b CM |
3464 | case 'f': |
3465 | switch (*++oparg) | |
3466 | { | |
3467 | case 'v': | |
3468 | /* FLI.[HSDQ] value field for 'Zfa' extension. */ | |
3469 | if (!arg_lookup (&asarg, riscv_fli_symval, | |
3470 | ARRAY_SIZE (riscv_fli_symval), ®no)) | |
3471 | { | |
3472 | /* 0.0 is not a valid entry in riscv_fli_numval. */ | |
3473 | errno = 0; | |
3474 | float f = strtof (asarg, &asarg); | |
3475 | if (errno != 0 || f == 0.0 | |
3476 | || !flt_lookup (f, riscv_fli_numval, | |
3477 | ARRAY_SIZE(riscv_fli_numval), | |
3478 | ®no)) | |
3479 | { | |
3480 | as_bad (_("bad fli constant operand, " | |
3481 | "supported constants must be in " | |
3482 | "decimal or hexadecimal floating-point " | |
3483 | "literal form")); | |
3484 | break; | |
3485 | } | |
3486 | } | |
3487 | INSERT_OPERAND (RS1, *ip, regno); | |
3488 | continue; | |
3489 | default: | |
3490 | goto unknown_riscv_ip_operand; | |
3491 | } | |
3492 | break; | |
b5c37946 SJ |
3493 | |
3494 | case 'c': | |
3495 | switch (*++oparg) | |
3496 | { | |
3497 | case 'h': /* Immediate field for c.lh/c.lhu/c.sh. */ | |
3498 | /* Handle cases, such as c.sh rs2', (rs1'). */ | |
3499 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3500 | continue; | |
3501 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3502 | || imm_expr->X_op != O_constant | |
3503 | || !VALID_ZCB_HALFWORD_UIMM ((valueT) imm_expr->X_add_number)) | |
3504 | break; | |
3505 | ip->insn_opcode |= ENCODE_ZCB_HALFWORD_UIMM (imm_expr->X_add_number); | |
3506 | goto rvc_imm_done; | |
b5c37946 SJ |
3507 | case 'b': /* Immediate field for c.lbu/c.sb. */ |
3508 | /* Handle cases, such as c.lbu rd', (rs1'). */ | |
3509 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3510 | continue; | |
3511 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3512 | || imm_expr->X_op != O_constant | |
3513 | || !VALID_ZCB_BYTE_UIMM ((valueT) imm_expr->X_add_number)) | |
3514 | break; | |
3515 | ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); | |
3516 | goto rvc_imm_done; | |
b5c37946 SJ |
3517 | case 'f': /* Operand for matching immediate 255. */ |
3518 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) | |
3519 | || imm_expr->X_op != O_constant | |
3520 | || imm_expr->X_add_number != 255) | |
3521 | break; | |
3522 | /* This operand is used for matching immediate 255, and | |
3523 | we do not write anything to encoding by this operand. */ | |
3524 | asarg = expr_parse_end; | |
3525 | imm_expr->X_op = O_absent; | |
3526 | continue; | |
b5c37946 SJ |
3527 | default: |
3528 | goto unknown_riscv_ip_operand; | |
3529 | } | |
3530 | break; | |
6de11ff6 | 3531 | |
54bca63b TO |
3532 | default: |
3533 | goto unknown_riscv_ip_operand; | |
3534 | } | |
3535 | break; | |
3b374308 | 3536 | |
6de11ff6 NC |
3537 | case 'X': /* Vendor-specific operands. */ |
3538 | switch (*++oparg) | |
3539 | { | |
3540 | case 't': /* Vendor-specific (T-head) operands. */ | |
8b7419c4 | 3541 | { |
6de11ff6 NC |
3542 | size_t n; |
3543 | size_t s; | |
3544 | bool sign; | |
3545 | switch (*++oparg) | |
3546 | { | |
3547 | case 'l': /* Integer immediate, literal. */ | |
3548 | n = strcspn (++oparg, ","); | |
3549 | if (strncmp (oparg, asarg, n)) | |
3550 | as_bad (_("unexpected literal (%s)"), asarg); | |
3551 | oparg += n - 1; | |
3552 | asarg += n; | |
3553 | continue; | |
3554 | case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */ | |
3555 | sign = true; | |
3556 | goto parse_imm; | |
3557 | case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */ | |
3558 | sign = false; | |
3559 | goto parse_imm; | |
3560 | parse_imm: | |
3561 | n = strtol (oparg + 1, (char **)&oparg, 10); | |
3562 | if (*oparg != '@') | |
3563 | goto unknown_riscv_ip_operand; | |
3564 | s = strtol (oparg + 1, (char **)&oparg, 10); | |
3565 | oparg--; | |
3566 | ||
3567 | my_getExpression (imm_expr, asarg); | |
3568 | check_absolute_expr (ip, imm_expr, false); | |
3569 | if (!sign) | |
3570 | { | |
3571 | if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) | |
3572 | as_bad (_("improper immediate value (%"PRIu64")"), | |
3573 | imm_expr->X_add_number); | |
3574 | } | |
3575 | else | |
3576 | { | |
3577 | if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) | |
3578 | as_bad (_("improper immediate value (%"PRIi64")"), | |
3579 | imm_expr->X_add_number); | |
3580 | } | |
3581 | INSERT_IMM (n, s, *ip, imm_expr->X_add_number); | |
3582 | imm_expr->X_op = O_absent; | |
3583 | asarg = expr_parse_end; | |
3584 | continue; | |
3585 | default: | |
8b7419c4 | 3586 | goto unknown_riscv_ip_operand; |
6de11ff6 | 3587 | } |
8b7419c4 | 3588 | } |
6de11ff6 NC |
3589 | break; |
3590 | ||
ccb388ca MB |
3591 | case 'c': /* Vendor-specific (CORE-V) operands. */ |
3592 | switch (*++oparg) | |
3593 | { | |
d1bd9787 MB |
3594 | case '2': |
3595 | my_getExpression (imm_expr, asarg); | |
3596 | check_absolute_expr (ip, imm_expr, FALSE); | |
3597 | asarg = expr_parse_end; | |
3598 | if (imm_expr->X_add_number<0 | |
3599 | || imm_expr->X_add_number>31) | |
3600 | break; | |
3601 | ip->insn_opcode | |
3602 | |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number); | |
3603 | continue; | |
ccb388ca MB |
3604 | case '3': |
3605 | my_getExpression (imm_expr, asarg); | |
3606 | check_absolute_expr (ip, imm_expr, FALSE); | |
3607 | asarg = expr_parse_end; | |
3608 | if (imm_expr->X_add_number < 0 | |
3609 | || imm_expr->X_add_number > 31) | |
3610 | break; | |
3611 | ip->insn_opcode | |
3612 | |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number); | |
3613 | continue; | |
3614 | default: | |
3615 | goto unknown_riscv_ip_operand; | |
3616 | } | |
3617 | break; | |
3618 | ||
6de11ff6 NC |
3619 | default: |
3620 | goto unknown_riscv_ip_operand; | |
3621 | } | |
8b7419c4 | 3622 | break; |
54bca63b | 3623 | |
e23eba97 | 3624 | default: |
437e2ff1 NC |
3625 | unknown_riscv_ip_operand: |
3626 | as_fatal (_("internal: unknown argument type `%s'"), | |
3627 | opargStart); | |
e23eba97 NC |
3628 | } |
3629 | break; | |
3630 | } | |
437e2ff1 | 3631 | asarg = asargStart; |
5b7c81bd | 3632 | insn_with_csr = false; |
e23eba97 NC |
3633 | } |
3634 | ||
dc1e8a47 | 3635 | out: |
e23eba97 NC |
3636 | /* Restore the character we might have clobbered above. */ |
3637 | if (save_c) | |
437e2ff1 | 3638 | *(asargStart - 1) = save_c; |
e23eba97 | 3639 | |
7a29ee29 JB |
3640 | probing_insn_operands = false; |
3641 | ||
e23eba97 NC |
3642 | return error; |
3643 | } | |
3644 | ||
a262b82f NC |
3645 | /* Similar to riscv_ip, but assembles an instruction according to the |
3646 | hardcode values of .insn directive. */ | |
3647 | ||
3648 | static const char * | |
3649 | riscv_ip_hardcode (char *str, | |
3650 | struct riscv_cl_insn *ip, | |
3651 | expressionS *imm_expr, | |
3652 | const char *error) | |
3653 | { | |
3654 | struct riscv_opcode *insn; | |
3655 | insn_t values[2] = {0, 0}; | |
3656 | unsigned int num = 0; | |
3657 | ||
3658 | input_line_pointer = str; | |
3659 | do | |
3660 | { | |
3661 | expression (imm_expr); | |
bb996692 | 3662 | switch (imm_expr->X_op) |
a262b82f | 3663 | { |
bb996692 JB |
3664 | case O_constant: |
3665 | values[num++] = (insn_t) imm_expr->X_add_number; | |
3666 | break; | |
3667 | case O_big: | |
634001bb TO |
3668 | /* Extract lower 32-bits of a big number. |
3669 | Assume that generic_bignum_to_int32 work on such number. */ | |
3670 | values[num++] = (insn_t) generic_bignum_to_int32 (); | |
bb996692 JB |
3671 | break; |
3672 | default: | |
a262b82f NC |
3673 | /* The first value isn't constant, so it should be |
3674 | .insn <type> <operands>. We have been parsed it | |
3675 | in the riscv_ip. */ | |
3676 | if (num == 0) | |
3677 | return error; | |
3678 | return _("values must be constant"); | |
3679 | } | |
a262b82f | 3680 | } |
bb996692 | 3681 | while (*input_line_pointer++ == ',' && num < 2 && imm_expr->X_op != O_big); |
a262b82f NC |
3682 | |
3683 | input_line_pointer--; | |
3684 | if (*input_line_pointer != '\0') | |
3685 | return _("unrecognized values"); | |
3686 | ||
cf2ab5ef | 3687 | insn = XCNEW (struct riscv_opcode); |
a262b82f NC |
3688 | insn->match = values[num - 1]; |
3689 | create_insn (ip, insn); | |
3690 | unsigned int bytes = riscv_insn_length (insn->match); | |
bb996692 JB |
3691 | |
3692 | if (num == 2 && values[0] != bytes) | |
3693 | return _("value conflicts with instruction length"); | |
3694 | ||
3695 | if (imm_expr->X_op == O_big) | |
3696 | { | |
634001bb TO |
3697 | unsigned int llen = 0; |
3698 | for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; | |
3699 | lval != 0; llen++) | |
3700 | lval >>= BITS_PER_CHAR; | |
3701 | unsigned int repr_bytes | |
3702 | = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; | |
3703 | if (bytes < repr_bytes) | |
bb996692 | 3704 | return _("value conflicts with instruction length"); |
634001bb TO |
3705 | for (num = 0; num < imm_expr->X_add_number - 1; ++num) |
3706 | number_to_chars_littleendian ( | |
3707 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3708 | generic_bignum[num], | |
3709 | CHARS_PER_LITTLENUM); | |
3710 | if (llen != 0) | |
3711 | number_to_chars_littleendian ( | |
3712 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3713 | generic_bignum[num], | |
3714 | llen); | |
3715 | memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); | |
bb996692 JB |
3716 | return NULL; |
3717 | } | |
3718 | ||
3719 | if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0) | |
a262b82f NC |
3720 | return _("value conflicts with instruction length"); |
3721 | ||
3722 | return NULL; | |
3723 | } | |
3724 | ||
e23eba97 NC |
3725 | void |
3726 | md_assemble (char *str) | |
3727 | { | |
3728 | struct riscv_cl_insn insn; | |
3729 | expressionS imm_expr; | |
3730 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
3731 | ||
dcd709e0 NC |
3732 | /* The architecture and privileged elf attributes should be set |
3733 | before assembling. */ | |
8f595e9b NC |
3734 | if (!start_assemble) |
3735 | { | |
5b7c81bd | 3736 | start_assemble = true; |
e23eba97 | 3737 | |
dcd709e0 | 3738 | riscv_set_abi_by_arch (); |
8f595e9b NC |
3739 | if (!riscv_set_default_priv_spec (NULL)) |
3740 | return; | |
3741 | } | |
3742 | ||
3190ebcb | 3743 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 3744 | |
e4028336 PN |
3745 | const struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
3746 | &imm_reloc, op_hash); | |
2dc8dd17 | 3747 | |
e4028336 | 3748 | if (error.msg) |
e23eba97 | 3749 | { |
e4028336 PN |
3750 | if (error.missing_ext) |
3751 | as_bad ("%s `%s', extension `%s' required", error.msg, | |
3752 | error.statement, error.missing_ext); | |
3753 | else | |
3754 | as_bad ("%s `%s'", error.msg, error.statement); | |
e23eba97 NC |
3755 | return; |
3756 | } | |
3757 | ||
3758 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
3759 | macro (&insn, &imm_expr, &imm_reloc); | |
3760 | else | |
3761 | append_insn (&insn, &imm_expr, imm_reloc); | |
3762 | } | |
3763 | ||
3764 | const char * | |
3765 | md_atof (int type, char *litP, int *sizeP) | |
3766 | { | |
71a75b51 | 3767 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e23eba97 NC |
3768 | } |
3769 | ||
3770 | void | |
3771 | md_number_to_chars (char *buf, valueT val, int n) | |
3772 | { | |
fbc09e7a MC |
3773 | if (target_big_endian) |
3774 | number_to_chars_bigendian (buf, val, n); | |
3775 | else | |
3776 | number_to_chars_littleendian (buf, val, n); | |
e23eba97 NC |
3777 | } |
3778 | ||
3779 | const char *md_shortopts = "O::g::G:"; | |
3780 | ||
3781 | enum options | |
3782 | { | |
2922d21d | 3783 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
3784 | OPTION_PIC, |
3785 | OPTION_NO_PIC, | |
2922d21d | 3786 | OPTION_MABI, |
71060565 JW |
3787 | OPTION_RELAX, |
3788 | OPTION_NO_RELAX, | |
2dc8dd17 JW |
3789 | OPTION_ARCH_ATTR, |
3790 | OPTION_NO_ARCH_ATTR, | |
2ca89224 NC |
3791 | OPTION_CSR_CHECK, |
3792 | OPTION_NO_CSR_CHECK, | |
8f595e9b NC |
3793 | OPTION_MISA_SPEC, |
3794 | OPTION_MPRIV_SPEC, | |
fbc09e7a MC |
3795 | OPTION_BIG_ENDIAN, |
3796 | OPTION_LITTLE_ENDIAN, | |
e23eba97 NC |
3797 | OPTION_END_OF_ENUM |
3798 | }; | |
3799 | ||
3800 | struct option md_longopts[] = | |
3801 | { | |
e23eba97 NC |
3802 | {"march", required_argument, NULL, OPTION_MARCH}, |
3803 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
3804 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
3805 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 3806 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
3807 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
3808 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
2dc8dd17 JW |
3809 | {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, |
3810 | {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, | |
2ca89224 NC |
3811 | {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK}, |
3812 | {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK}, | |
8f595e9b NC |
3813 | {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC}, |
3814 | {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC}, | |
fbc09e7a MC |
3815 | {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN}, |
3816 | {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
e23eba97 NC |
3817 | |
3818 | {NULL, no_argument, NULL, 0} | |
3819 | }; | |
3820 | size_t md_longopts_size = sizeof (md_longopts); | |
3821 | ||
e23eba97 NC |
3822 | int |
3823 | md_parse_option (int c, const char *arg) | |
3824 | { | |
3825 | switch (c) | |
3826 | { | |
e23eba97 | 3827 | case OPTION_MARCH: |
8f595e9b | 3828 | default_arch_with_ext = arg; |
e23eba97 NC |
3829 | break; |
3830 | ||
3831 | case OPTION_NO_PIC: | |
5b7c81bd | 3832 | riscv_opts.pic = false; |
e23eba97 NC |
3833 | break; |
3834 | ||
3835 | case OPTION_PIC: | |
5b7c81bd | 3836 | riscv_opts.pic = true; |
e23eba97 NC |
3837 | break; |
3838 | ||
2922d21d AW |
3839 | case OPTION_MABI: |
3840 | if (strcmp (arg, "ilp32") == 0) | |
5b7c81bd | 3841 | riscv_set_abi (32, FLOAT_ABI_SOFT, false); |
7f999549 | 3842 | else if (strcmp (arg, "ilp32e") == 0) |
5b7c81bd | 3843 | riscv_set_abi (32, FLOAT_ABI_SOFT, true); |
2922d21d | 3844 | else if (strcmp (arg, "ilp32f") == 0) |
5b7c81bd | 3845 | riscv_set_abi (32, FLOAT_ABI_SINGLE, false); |
2922d21d | 3846 | else if (strcmp (arg, "ilp32d") == 0) |
5b7c81bd | 3847 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3848 | else if (strcmp (arg, "ilp32q") == 0) |
5b7c81bd | 3849 | riscv_set_abi (32, FLOAT_ABI_QUAD, false); |
2922d21d | 3850 | else if (strcmp (arg, "lp64") == 0) |
5b7c81bd | 3851 | riscv_set_abi (64, FLOAT_ABI_SOFT, false); |
6674b23f TO |
3852 | else if (strcmp (arg, "lp64e") == 0) |
3853 | riscv_set_abi (64, FLOAT_ABI_SOFT, true); | |
2922d21d | 3854 | else if (strcmp (arg, "lp64f") == 0) |
5b7c81bd | 3855 | riscv_set_abi (64, FLOAT_ABI_SINGLE, false); |
2922d21d | 3856 | else if (strcmp (arg, "lp64d") == 0) |
5b7c81bd | 3857 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3858 | else if (strcmp (arg, "lp64q") == 0) |
5b7c81bd | 3859 | riscv_set_abi (64, FLOAT_ABI_QUAD, false); |
2922d21d AW |
3860 | else |
3861 | return 0; | |
5b7c81bd | 3862 | explicit_mabi = true; |
2922d21d AW |
3863 | break; |
3864 | ||
71060565 | 3865 | case OPTION_RELAX: |
5b7c81bd | 3866 | riscv_opts.relax = true; |
71060565 JW |
3867 | break; |
3868 | ||
3869 | case OPTION_NO_RELAX: | |
5b7c81bd | 3870 | riscv_opts.relax = false; |
71060565 JW |
3871 | break; |
3872 | ||
2dc8dd17 | 3873 | case OPTION_ARCH_ATTR: |
5b7c81bd | 3874 | riscv_opts.arch_attr = true; |
2dc8dd17 JW |
3875 | break; |
3876 | ||
3877 | case OPTION_NO_ARCH_ATTR: | |
5b7c81bd | 3878 | riscv_opts.arch_attr = false; |
2dc8dd17 JW |
3879 | break; |
3880 | ||
2ca89224 | 3881 | case OPTION_CSR_CHECK: |
5b7c81bd | 3882 | riscv_opts.csr_check = true; |
2ca89224 NC |
3883 | break; |
3884 | ||
3885 | case OPTION_NO_CSR_CHECK: | |
5b7c81bd | 3886 | riscv_opts.csr_check = false; |
2ca89224 NC |
3887 | break; |
3888 | ||
8f595e9b NC |
3889 | case OPTION_MISA_SPEC: |
3890 | return riscv_set_default_isa_spec (arg); | |
3891 | ||
3892 | case OPTION_MPRIV_SPEC: | |
3893 | return riscv_set_default_priv_spec (arg); | |
3894 | ||
fbc09e7a MC |
3895 | case OPTION_BIG_ENDIAN: |
3896 | target_big_endian = 1; | |
3897 | break; | |
3898 | ||
3899 | case OPTION_LITTLE_ENDIAN: | |
3900 | target_big_endian = 0; | |
3901 | break; | |
3902 | ||
e23eba97 NC |
3903 | default: |
3904 | return 0; | |
3905 | } | |
3906 | ||
3907 | return 1; | |
3908 | } | |
3909 | ||
3910 | void | |
3911 | riscv_after_parse_args (void) | |
3912 | { | |
dcd709e0 NC |
3913 | /* The --with-arch is optional for now, so we still need to set the xlen |
3914 | according to the default_arch, which is set by the --target. */ | |
e23eba97 NC |
3915 | if (xlen == 0) |
3916 | { | |
3917 | if (strcmp (default_arch, "riscv32") == 0) | |
3918 | xlen = 32; | |
3919 | else if (strcmp (default_arch, "riscv64") == 0) | |
3920 | xlen = 64; | |
3921 | else | |
3922 | as_bad ("unknown default architecture `%s'", default_arch); | |
3923 | } | |
8f595e9b | 3924 | |
dcd709e0 | 3925 | /* Set default specs. */ |
8f595e9b NC |
3926 | if (default_isa_spec == ISA_SPEC_CLASS_NONE) |
3927 | riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC); | |
dcd709e0 NC |
3928 | if (default_priv_spec == PRIV_SPEC_CLASS_NONE) |
3929 | riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC); | |
2922d21d | 3930 | |
8f595e9b | 3931 | riscv_set_arch (default_arch_with_ext); |
2922d21d | 3932 | |
0ac2b354 AB |
3933 | /* If the CIE to be produced has not been overridden on the command line, |
3934 | then produce version 3 by default. This allows us to use the full | |
3935 | range of registers in a .cfi_return_column directive. */ | |
3936 | if (flag_dwarf_cie_version == -1) | |
3937 | flag_dwarf_cie_version = 3; | |
e23eba97 NC |
3938 | } |
3939 | ||
7a29ee29 JB |
3940 | bool riscv_parse_name (const char *name, struct expressionS *ep, |
3941 | enum expr_mode mode) | |
3942 | { | |
3943 | unsigned int regno; | |
3944 | symbolS *sym; | |
3945 | ||
3946 | if (!probing_insn_operands) | |
3947 | return false; | |
3948 | ||
3949 | gas_assert (mode == expr_normal); | |
3950 | ||
3951 | regno = reg_lookup_internal (name, RCLASS_GPR); | |
3952 | if (regno == (unsigned int)-1) | |
3953 | return false; | |
3954 | ||
3955 | if (symbol_find (name) != NULL) | |
3956 | return false; | |
3957 | ||
3958 | /* Create a symbol without adding it to the symbol table yet. | |
3959 | Insertion will happen only once we commit to using the insn | |
3960 | we're probing operands for. */ | |
3961 | for (sym = deferred_sym_rootP; sym; sym = symbol_next (sym)) | |
3962 | if (strcmp (name, S_GET_NAME (sym)) == 0) | |
3963 | break; | |
3964 | if (!sym) | |
3965 | { | |
3966 | for (sym = orphan_sym_rootP; sym; sym = symbol_next (sym)) | |
3967 | if (strcmp (name, S_GET_NAME (sym)) == 0) | |
3968 | { | |
3969 | symbol_remove (sym, &orphan_sym_rootP, &orphan_sym_lastP); | |
3970 | break; | |
3971 | } | |
3972 | if (!sym) | |
3973 | sym = symbol_create (name, undefined_section, | |
3974 | &zero_address_frag, 0); | |
3975 | ||
3976 | symbol_append (sym, deferred_sym_lastP, &deferred_sym_rootP, | |
3977 | &deferred_sym_lastP); | |
3978 | } | |
3979 | ||
3980 | ep->X_op = O_symbol; | |
3981 | ep->X_add_symbol = sym; | |
3982 | ep->X_add_number = 0; | |
3983 | ||
3984 | return true; | |
3985 | } | |
3986 | ||
e23eba97 NC |
3987 | long |
3988 | md_pcrel_from (fixS *fixP) | |
3989 | { | |
3990 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
3991 | } | |
3992 | ||
3993 | /* Apply a fixup to the object file. */ | |
3994 | ||
3995 | void | |
3996 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
3997 | { | |
45f76423 | 3998 | unsigned int subtype; |
e23eba97 | 3999 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
5b7c81bd | 4000 | bool relaxable = false; |
c1b465c9 | 4001 | offsetT loc; |
a6cbf936 | 4002 | segT sub_segment; |
e23eba97 NC |
4003 | |
4004 | /* Remember value for tc_gen_reloc. */ | |
4005 | fixP->fx_addnumber = *valP; | |
4006 | ||
4007 | switch (fixP->fx_r_type) | |
4008 | { | |
e23eba97 NC |
4009 | case BFD_RELOC_RISCV_HI20: |
4010 | case BFD_RELOC_RISCV_LO12_I: | |
4011 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
4012 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
4013 | | bfd_getl32 (buf), buf); | |
a5ec5e3f | 4014 | if (fixP->fx_addsy == NULL) |
5b7c81bd AM |
4015 | fixP->fx_done = true; |
4016 | relaxable = true; | |
45f76423 AW |
4017 | break; |
4018 | ||
4019 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
4020 | case BFD_RELOC_RISCV_ADD8: |
4021 | case BFD_RELOC_RISCV_ADD16: | |
4022 | case BFD_RELOC_RISCV_ADD32: | |
4023 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 4024 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
4025 | case BFD_RELOC_RISCV_SUB8: |
4026 | case BFD_RELOC_RISCV_SUB16: | |
4027 | case BFD_RELOC_RISCV_SUB32: | |
4028 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 | 4029 | case BFD_RELOC_RISCV_RELAX: |
f1cd8b94 KLC |
4030 | /* cvt_frag_to_fill () has called output_leb128 (). */ |
4031 | case BFD_RELOC_RISCV_SET_ULEB128: | |
4032 | case BFD_RELOC_RISCV_SUB_ULEB128: | |
45f76423 AW |
4033 | break; |
4034 | ||
4035 | case BFD_RELOC_RISCV_TPREL_HI20: | |
4036 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
4037 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
4038 | case BFD_RELOC_RISCV_TPREL_ADD: | |
5b7c81bd | 4039 | relaxable = true; |
45f76423 AW |
4040 | /* Fall through. */ |
4041 | ||
4042 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
4043 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
4044 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
4045 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
4046 | if (fixP->fx_addsy != NULL) |
4047 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4048 | else | |
4049 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4050 | _("TLS relocation against a constant")); | |
e23eba97 NC |
4051 | break; |
4052 | ||
e23eba97 | 4053 | case BFD_RELOC_32: |
a6cbf936 KLC |
4054 | /* Use pc-relative relocation for FDE initial location. |
4055 | The symbol address in .eh_frame may be adjusted in | |
4056 | _bfd_elf_discard_section_eh_frame, and the content of | |
4057 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
4058 | Therefore, we cannot insert a relocation whose addend symbol is | |
dcd709e0 | 4059 | in .eh_frame. Othrewise, the value may be adjusted twice. */ |
a6cbf936 KLC |
4060 | if (fixP->fx_addsy && fixP->fx_subsy |
4061 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
4062 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
4063 | && S_GET_VALUE (fixP->fx_subsy) | |
4064 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
4065 | { | |
4066 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
4067 | fixP->fx_subsy = NULL; | |
4068 | break; | |
4069 | } | |
4070 | /* Fall through. */ | |
4071 | case BFD_RELOC_64: | |
e23eba97 NC |
4072 | case BFD_RELOC_16: |
4073 | case BFD_RELOC_8: | |
45f76423 | 4074 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
4075 | if (fixP->fx_addsy && fixP->fx_subsy) |
4076 | { | |
4077 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
4078 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
4079 | fixP->fx_next->fx_subsy = NULL; | |
4080 | fixP->fx_next->fx_offset = 0; | |
4081 | fixP->fx_subsy = NULL; | |
4082 | ||
4083 | switch (fixP->fx_r_type) | |
4084 | { | |
4085 | case BFD_RELOC_64: | |
4086 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
4087 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
4088 | break; | |
4089 | ||
4090 | case BFD_RELOC_32: | |
4091 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
4092 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
4093 | break; | |
4094 | ||
4095 | case BFD_RELOC_16: | |
4096 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
4097 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
4098 | break; | |
4099 | ||
4100 | case BFD_RELOC_8: | |
4101 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
4102 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 4103 | break; |
e23eba97 | 4104 | |
45f76423 AW |
4105 | case BFD_RELOC_RISCV_CFA: |
4106 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
4107 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
4108 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
4109 | switch (subtype) |
4110 | { | |
4111 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
4112 | fixP->fx_where = loc + 1; |
4113 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
4114 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
4115 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
4116 | break; | |
4117 | ||
4118 | case DW_CFA_advance_loc2: | |
4119 | fixP->fx_size = 2; | |
45f76423 | 4120 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
4121 | fixP->fx_where = loc + 1; |
4122 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
4123 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
4124 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
4125 | break; | |
4126 | ||
4127 | case DW_CFA_advance_loc4: | |
4128 | fixP->fx_size = 4; | |
45f76423 | 4129 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
4130 | fixP->fx_where = loc; |
4131 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
4132 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
4133 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
4134 | break; | |
4135 | ||
4136 | default: | |
4137 | if (subtype < 0x80 && (subtype & 0x40)) | |
4138 | { | |
4139 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
4140 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
4141 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
4142 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
4143 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
4144 | } | |
4145 | else | |
b800637e | 4146 | as_fatal (_("internal: bad CFA value #%d"), subtype); |
45f76423 AW |
4147 | break; |
4148 | } | |
4149 | break; | |
4150 | ||
e23eba97 NC |
4151 | default: |
4152 | /* This case is unreachable. */ | |
4153 | abort (); | |
4154 | } | |
4155 | } | |
4156 | /* Fall through. */ | |
4157 | ||
4158 | case BFD_RELOC_RVA: | |
4159 | /* If we are deleting this reloc entry, we must fill in the | |
4160 | value now. This can happen if we have a .word which is not | |
4161 | resolved when it appears but is later defined. */ | |
4162 | if (fixP->fx_addsy == NULL) | |
4163 | { | |
4164 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
4165 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
4166 | fixP->fx_done = 1; | |
4167 | } | |
4168 | break; | |
4169 | ||
4170 | case BFD_RELOC_RISCV_JMP: | |
4171 | if (fixP->fx_addsy) | |
4172 | { | |
4173 | /* Fill in a tentative value to improve objdump readability. */ | |
4174 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4175 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4176 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf); |
e23eba97 NC |
4177 | } |
4178 | break; | |
4179 | ||
4180 | case BFD_RELOC_12_PCREL: | |
4181 | if (fixP->fx_addsy) | |
4182 | { | |
4183 | /* Fill in a tentative value to improve objdump readability. */ | |
4184 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4185 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4186 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf); |
e23eba97 NC |
4187 | } |
4188 | break; | |
4189 | ||
4190 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
4191 | if (fixP->fx_addsy) | |
4192 | { | |
4193 | /* Fill in a tentative value to improve objdump readability. */ | |
4194 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4195 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4196 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf); |
e23eba97 NC |
4197 | } |
4198 | break; | |
4199 | ||
4200 | case BFD_RELOC_RISCV_RVC_JUMP: | |
4201 | if (fixP->fx_addsy) | |
4202 | { | |
4203 | /* Fill in a tentative value to improve objdump readability. */ | |
4204 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4205 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4206 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf); |
e23eba97 NC |
4207 | } |
4208 | break; | |
4209 | ||
e23eba97 NC |
4210 | case BFD_RELOC_RISCV_CALL: |
4211 | case BFD_RELOC_RISCV_CALL_PLT: | |
5b7c81bd | 4212 | relaxable = true; |
45f76423 AW |
4213 | break; |
4214 | ||
9d06997a | 4215 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
4216 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
4217 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
4218 | relaxable = riscv_opts.relax; |
4219 | break; | |
4220 | ||
e23eba97 NC |
4221 | case BFD_RELOC_RISCV_ALIGN: |
4222 | break; | |
4223 | ||
4224 | default: | |
4225 | /* We ignore generic BFD relocations we don't know about. */ | |
4226 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
b800637e | 4227 | as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type); |
e23eba97 | 4228 | } |
45f76423 | 4229 | |
e294484e | 4230 | if (fixP->fx_subsy != NULL) |
4bf09429 | 4231 | as_bad_subtract (fixP); |
e294484e | 4232 | |
45f76423 AW |
4233 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
4234 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
4235 | { | |
4236 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
4237 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
4238 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
b1b11e92 | 4239 | fixP->fx_next->fx_size = 0; |
45f76423 AW |
4240 | } |
4241 | } | |
4242 | ||
4243 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
4244 | we insert a fix to relocate it again in link-time. */ | |
4245 | ||
4246 | void | |
4247 | riscv_pre_output_hook (void) | |
4248 | { | |
4249 | const frchainS *frch; | |
72393fd1 JW |
4250 | segT s; |
4251 | ||
4252 | /* Save the current segment info. */ | |
4253 | segT seg = now_seg; | |
4254 | subsegT subseg = now_subseg; | |
45f76423 AW |
4255 | |
4256 | for (s = stdoutput->sections; s; s = s->next) | |
4257 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
4258 | { | |
7cb7b948 | 4259 | fragS *frag; |
45f76423 AW |
4260 | |
4261 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
4262 | { | |
4263 | if (frag->fr_type == rs_cfa) | |
4264 | { | |
45f76423 | 4265 | expressionS exp; |
8d1015a8 | 4266 | expressionS *symval; |
45f76423 | 4267 | |
8d1015a8 | 4268 | symval = symbol_get_value_expression (frag->fr_symbol); |
45f76423 | 4269 | exp.X_op = O_subtract; |
8d1015a8 | 4270 | exp.X_add_symbol = symval->X_add_symbol; |
45f76423 | 4271 | exp.X_add_number = 0; |
8d1015a8 | 4272 | exp.X_op_symbol = symval->X_op_symbol; |
45f76423 | 4273 | |
72393fd1 JW |
4274 | /* We must set the segment before creating a frag after all |
4275 | frag chains have been chained together. */ | |
4276 | subseg_set (s, frch->frch_subseg); | |
4277 | ||
c1b465c9 | 4278 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
4279 | BFD_RELOC_RISCV_CFA); |
4280 | } | |
4281 | } | |
4282 | } | |
72393fd1 JW |
4283 | |
4284 | /* Restore the original segment info. */ | |
4285 | subseg_set (seg, subseg); | |
e23eba97 NC |
4286 | } |
4287 | ||
e23eba97 NC |
4288 | /* Handle the .option pseudo-op. */ |
4289 | ||
4290 | static void | |
4291 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
4292 | { | |
4293 | char *name = input_line_pointer, ch; | |
4294 | ||
4295 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4296 | ++input_line_pointer; | |
4297 | ch = *input_line_pointer; | |
4298 | *input_line_pointer = '\0'; | |
4299 | ||
4300 | if (strcmp (name, "rvc") == 0) | |
edc77c59 | 4301 | { |
d3ffd7f7 | 4302 | riscv_update_subset (&riscv_rps_as, "+c"); |
40f1a1a4 | 4303 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4304 | riscv_set_rvc (true); |
4305 | } | |
e23eba97 | 4306 | else if (strcmp (name, "norvc") == 0) |
edc77c59 | 4307 | { |
d3ffd7f7 | 4308 | riscv_update_subset (&riscv_rps_as, "-c"); |
40f1a1a4 | 4309 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4310 | riscv_set_rvc (false); |
4311 | } | |
e23eba97 | 4312 | else if (strcmp (name, "pic") == 0) |
5b7c81bd | 4313 | riscv_opts.pic = true; |
e23eba97 | 4314 | else if (strcmp (name, "nopic") == 0) |
5b7c81bd | 4315 | riscv_opts.pic = false; |
45f76423 | 4316 | else if (strcmp (name, "relax") == 0) |
5b7c81bd | 4317 | riscv_opts.relax = true; |
45f76423 | 4318 | else if (strcmp (name, "norelax") == 0) |
5b7c81bd | 4319 | riscv_opts.relax = false; |
2ca89224 | 4320 | else if (strcmp (name, "csr-check") == 0) |
5b7c81bd | 4321 | riscv_opts.csr_check = true; |
2ca89224 | 4322 | else if (strcmp (name, "no-csr-check") == 0) |
5b7c81bd | 4323 | riscv_opts.csr_check = false; |
d3ffd7f7 NC |
4324 | else if (strncmp (name, "arch,", 5) == 0) |
4325 | { | |
4326 | name += 5; | |
4327 | if (ISSPACE (*name) && *name != '\0') | |
4328 | name++; | |
4329 | riscv_update_subset (&riscv_rps_as, name); | |
40f1a1a4 | 4330 | riscv_reset_subsets_list_arch_str (); |
e7e599a1 NC |
4331 | |
4332 | riscv_set_rvc (false); | |
b5c37946 SJ |
4333 | if (riscv_subset_supports (&riscv_rps_as, "c") |
4334 | || riscv_subset_supports (&riscv_rps_as, "zca")) | |
e7e599a1 | 4335 | riscv_set_rvc (true); |
acab2a68 TO |
4336 | |
4337 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
4338 | riscv_set_tso (); | |
d3ffd7f7 | 4339 | } |
e23eba97 NC |
4340 | else if (strcmp (name, "push") == 0) |
4341 | { | |
4342 | struct riscv_option_stack *s; | |
4343 | ||
d3ffd7f7 | 4344 | s = XNEW (struct riscv_option_stack); |
e23eba97 NC |
4345 | s->next = riscv_opts_stack; |
4346 | s->options = riscv_opts; | |
f5cb31a8 | 4347 | s->subset_list = riscv_rps_as.subset_list; |
e23eba97 | 4348 | riscv_opts_stack = s; |
f5cb31a8 | 4349 | riscv_rps_as.subset_list = riscv_copy_subset_list (s->subset_list); |
e23eba97 NC |
4350 | } |
4351 | else if (strcmp (name, "pop") == 0) | |
4352 | { | |
4353 | struct riscv_option_stack *s; | |
4354 | ||
4355 | s = riscv_opts_stack; | |
4356 | if (s == NULL) | |
4357 | as_bad (_(".option pop with no .option push")); | |
4358 | else | |
4359 | { | |
f5cb31a8 | 4360 | riscv_subset_list_t *release_subsets = riscv_rps_as.subset_list; |
e23eba97 | 4361 | riscv_opts_stack = s->next; |
d3ffd7f7 | 4362 | riscv_opts = s->options; |
f5cb31a8 | 4363 | riscv_rps_as.subset_list = s->subset_list; |
d3ffd7f7 | 4364 | riscv_release_subset_list (release_subsets); |
e23eba97 NC |
4365 | free (s); |
4366 | } | |
4367 | } | |
4368 | else | |
4369 | { | |
c84b3d7e | 4370 | as_warn (_("unrecognized .option directive: %s"), name); |
e23eba97 NC |
4371 | } |
4372 | *input_line_pointer = ch; | |
4373 | demand_empty_rest_of_line (); | |
4374 | } | |
4375 | ||
4376 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
4377 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
4378 | use in DWARF debug information. */ | |
4379 | ||
4380 | static void | |
4381 | s_dtprel (int bytes) | |
4382 | { | |
4383 | expressionS ex; | |
4384 | char *p; | |
4385 | ||
4386 | expression (&ex); | |
4387 | ||
4388 | if (ex.X_op != O_symbol) | |
4389 | { | |
b800637e | 4390 | as_bad (_("unsupported use of %s"), (bytes == 8 |
e23eba97 NC |
4391 | ? ".dtpreldword" |
4392 | : ".dtprelword")); | |
4393 | ignore_rest_of_line (); | |
4394 | } | |
4395 | ||
4396 | p = frag_more (bytes); | |
4397 | md_number_to_chars (p, 0, bytes); | |
5b7c81bd | 4398 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, |
e23eba97 NC |
4399 | (bytes == 8 |
4400 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
4401 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
4402 | ||
4403 | demand_empty_rest_of_line (); | |
4404 | } | |
4405 | ||
4406 | /* Handle the .bss pseudo-op. */ | |
4407 | ||
4408 | static void | |
4409 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
4410 | { | |
4411 | subseg_set (bss_section, 0); | |
4412 | demand_empty_rest_of_line (); | |
4413 | } | |
4414 | ||
e23eba97 | 4415 | static void |
d115ab8e | 4416 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 4417 | { |
d115ab8e | 4418 | bfd_vma i = 0; |
e23eba97 | 4419 | |
e5b737de AW |
4420 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
4421 | means we are not within a valid instruction sequence. It is thus safe | |
4422 | to use a zero byte, even though that is not a valid instruction. */ | |
4423 | if (bytes % 2 == 1) | |
4424 | buf[i++] = 0; | |
4425 | ||
4426 | /* Use at most one 2-byte NOP. */ | |
4427 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 4428 | { |
fbc09e7a | 4429 | number_to_chars_littleendian (buf + i, RVC_NOP, 2); |
d115ab8e | 4430 | i += 2; |
e23eba97 NC |
4431 | } |
4432 | ||
e5b737de | 4433 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e | 4434 | for ( ; i < bytes; i += 4) |
fbc09e7a | 4435 | number_to_chars_littleendian (buf + i, RISCV_NOP, 4); |
d115ab8e | 4436 | } |
e23eba97 | 4437 | |
d115ab8e AW |
4438 | /* Called from md_do_align. Used to create an alignment frag in a |
4439 | code section by emitting a worst-case NOP sequence that the linker | |
4440 | will later relax to the correct number of NOPs. We can't compute | |
4441 | the correct alignment now because of other linker relaxations. */ | |
4442 | ||
5b7c81bd | 4443 | bool |
d115ab8e AW |
4444 | riscv_frag_align_code (int n) |
4445 | { | |
e5b737de | 4446 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
4447 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
4448 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
4449 | char *nops; | |
ed0816bd | 4450 | expressionS ex; |
d115ab8e | 4451 | |
36877bfb JW |
4452 | /* If we are moving to a smaller alignment than the instruction size, then no |
4453 | alignment is required. */ | |
4454 | if (bytes <= insn_alignment) | |
5b7c81bd | 4455 | return true; |
36877bfb | 4456 | |
d115ab8e AW |
4457 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
4458 | if (!riscv_opts.relax) | |
5b7c81bd | 4459 | return false; |
e23eba97 | 4460 | |
40f1a1a4 NC |
4461 | /* Maybe we should use frag_var to create a new rs_align_code fragment, |
4462 | rather than just use frag_more to handle an alignment here? So that we | |
4463 | don't need to call riscv_mapping_state again later, and then only need | |
4464 | to check frag->fr_type to see if it is frag_align_code. */ | |
e80ae190 JW |
4465 | nops = frag_more (worst_case_bytes); |
4466 | ||
ed0816bd PD |
4467 | ex.X_op = O_constant; |
4468 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 4469 | |
ed0816bd | 4470 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 4471 | |
ed0816bd | 4472 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
5b7c81bd | 4473 | &ex, false, BFD_RELOC_RISCV_ALIGN); |
e23eba97 | 4474 | |
3190ebcb | 4475 | riscv_mapping_state (MAP_INSN, worst_case_bytes, true/* fr_align_code */); |
9b9b1092 | 4476 | |
cb2562f5 LX |
4477 | /* We need to start a new frag after the alignment which may be removed by |
4478 | the linker, to prevent the assembler from computing static offsets. | |
4479 | This is necessary to get correct EH info. */ | |
4480 | frag_wane (frag_now); | |
4481 | frag_new (0); | |
4482 | ||
5b7c81bd | 4483 | return true; |
d115ab8e | 4484 | } |
e23eba97 | 4485 | |
d115ab8e AW |
4486 | /* Implement HANDLE_ALIGN. */ |
4487 | ||
4488 | void | |
4489 | riscv_handle_align (fragS *fragP) | |
4490 | { | |
4491 | switch (fragP->fr_type) | |
4492 | { | |
4493 | case rs_align_code: | |
4494 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
4495 | if (!riscv_opts.relax) | |
4496 | { | |
e80ae190 JW |
4497 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
4498 | - fragP->fr_address - fragP->fr_fix); | |
4499 | /* We have 4 byte uncompressed nops. */ | |
4500 | bfd_signed_vma size = 4; | |
4501 | bfd_signed_vma excess = bytes % size; | |
9b9b1092 | 4502 | bfd_boolean odd_padding = (excess % 2 == 1); |
e80ae190 JW |
4503 | char *p = fragP->fr_literal + fragP->fr_fix; |
4504 | ||
4505 | if (bytes <= 0) | |
d115ab8e AW |
4506 | break; |
4507 | ||
e80ae190 JW |
4508 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
4509 | if (excess) | |
4510 | { | |
9b9b1092 NC |
4511 | if (odd_padding) |
4512 | riscv_add_odd_padding_symbol (fragP); | |
e80ae190 JW |
4513 | riscv_make_nops (p, excess); |
4514 | fragP->fr_fix += excess; | |
4515 | p += excess; | |
4516 | } | |
4517 | ||
9b9b1092 NC |
4518 | /* The frag will be changed to `rs_fill` later. The function |
4519 | `write_contents` will try to fill the remaining spaces | |
4520 | according to the patterns we give. In this case, we give | |
4521 | a 4 byte uncompressed nop as the pattern, and set the size | |
4522 | of the pattern into `fr_var`. The nop will be output to the | |
4523 | file `fr_offset` times. However, `fr_offset` could be zero | |
4524 | if we don't need to pad the boundary finally. */ | |
e80ae190 JW |
4525 | riscv_make_nops (p, size); |
4526 | fragP->fr_var = size; | |
d115ab8e AW |
4527 | } |
4528 | break; | |
4529 | ||
4530 | default: | |
4531 | break; | |
4532 | } | |
e23eba97 NC |
4533 | } |
4534 | ||
9b9b1092 NC |
4535 | /* This usually called from frag_var. */ |
4536 | ||
4537 | void | |
4538 | riscv_init_frag (fragS * fragP, int max_chars) | |
4539 | { | |
4540 | /* Do not add mapping symbol to debug sections. */ | |
4541 | if (bfd_section_flags (now_seg) & SEC_DEBUGGING) | |
4542 | return; | |
4543 | ||
4544 | switch (fragP->fr_type) | |
4545 | { | |
4546 | case rs_fill: | |
4547 | case rs_align: | |
4548 | case rs_align_test: | |
3190ebcb | 4549 | riscv_mapping_state (MAP_DATA, max_chars, false/* fr_align_code */); |
9b9b1092 NC |
4550 | break; |
4551 | case rs_align_code: | |
3190ebcb | 4552 | riscv_mapping_state (MAP_INSN, max_chars, true/* fr_align_code */); |
9b9b1092 NC |
4553 | break; |
4554 | default: | |
4555 | break; | |
4556 | } | |
4557 | } | |
4558 | ||
e23eba97 NC |
4559 | int |
4560 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
4561 | { | |
5b7c81bd | 4562 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false)); |
e23eba97 NC |
4563 | } |
4564 | ||
4565 | /* Translate internal representation of relocation info to BFD target | |
4566 | format. */ | |
4567 | ||
4568 | arelent * | |
4569 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
4570 | { | |
4571 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
4572 | ||
4573 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
4574 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
4575 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4576 | reloc->addend = fixp->fx_addnumber; | |
4577 | ||
4578 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
4579 | if (reloc->howto == NULL) | |
4580 | { | |
4581 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
4582 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
4583 | { | |
4584 | /* We don't have R_RISCV_8/16, but for this special case, | |
4585 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
4586 | return reloc; | |
4587 | } | |
4588 | ||
4589 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
4590 | _("cannot represent %s relocation in object file"), | |
4591 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
4592 | return NULL; | |
4593 | } | |
4594 | ||
4595 | return reloc; | |
4596 | } | |
4597 | ||
4598 | int | |
4599 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
4600 | { | |
4601 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
4602 | { | |
4603 | offsetT old_var = fragp->fr_var; | |
5b7c81bd | 4604 | fragp->fr_var = relaxed_branch_length (fragp, sec, true); |
e23eba97 NC |
4605 | return fragp->fr_var - old_var; |
4606 | } | |
4607 | ||
4608 | return 0; | |
4609 | } | |
4610 | ||
4611 | /* Expand far branches to multi-instruction sequences. */ | |
4612 | ||
4613 | static void | |
4614 | md_convert_frag_branch (fragS *fragp) | |
4615 | { | |
4616 | bfd_byte *buf; | |
4617 | expressionS exp; | |
4618 | fixS *fixp; | |
4619 | insn_t insn; | |
4620 | int rs1, reloc; | |
4621 | ||
4622 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
4623 | ||
4624 | exp.X_op = O_symbol; | |
4625 | exp.X_add_symbol = fragp->fr_symbol; | |
4626 | exp.X_add_number = fragp->fr_offset; | |
4627 | ||
4628 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
4629 | ||
4630 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
4631 | { | |
4632 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4633 | { | |
4634 | case 8: | |
4635 | case 4: | |
4636 | /* Expand the RVC branch into a RISC-V one. */ | |
4637 | insn = bfd_getl16 (buf); | |
4638 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
4639 | if ((insn & MASK_C_J) == MATCH_C_J) | |
4640 | insn = MATCH_JAL; | |
4641 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
4642 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
4643 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
4644 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
4645 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
4646 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
4647 | else | |
4648 | abort (); | |
4649 | bfd_putl32 (insn, buf); | |
4650 | break; | |
4651 | ||
4652 | case 6: | |
4653 | /* Invert the branch condition. Branch over the jump. */ | |
4654 | insn = bfd_getl16 (buf); | |
4655 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
5a9f5403 | 4656 | insn |= ENCODE_CBTYPE_IMM (6); |
e23eba97 NC |
4657 | bfd_putl16 (insn, buf); |
4658 | buf += 2; | |
4659 | goto jump; | |
4660 | ||
4661 | case 2: | |
4662 | /* Just keep the RVC branch. */ | |
4663 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4664 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
4665 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4666 | 2, &exp, false, reloc); |
e23eba97 NC |
4667 | buf += 2; |
4668 | goto done; | |
4669 | ||
4670 | default: | |
1d65abb5 | 4671 | abort (); |
e23eba97 NC |
4672 | } |
4673 | } | |
4674 | ||
4675 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4676 | { | |
4677 | case 8: | |
4678 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
4679 | ||
4680 | /* Invert the branch condition. Branch over the jump. */ | |
4681 | insn = bfd_getl32 (buf); | |
4682 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
5a9f5403 | 4683 | insn |= ENCODE_BTYPE_IMM (8); |
fbc09e7a | 4684 | bfd_putl32 (insn, buf); |
e23eba97 NC |
4685 | buf += 4; |
4686 | ||
dc1e8a47 | 4687 | jump: |
e23eba97 NC |
4688 | /* Jump to the target. */ |
4689 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4690 | 4, &exp, false, BFD_RELOC_RISCV_JMP); |
fbc09e7a | 4691 | bfd_putl32 (MATCH_JAL, buf); |
e23eba97 NC |
4692 | buf += 4; |
4693 | break; | |
4694 | ||
4695 | case 4: | |
4696 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4697 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
4698 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4699 | 4, &exp, false, reloc); |
e23eba97 NC |
4700 | buf += 4; |
4701 | break; | |
4702 | ||
4703 | default: | |
4704 | abort (); | |
4705 | } | |
4706 | ||
dc1e8a47 | 4707 | done: |
e23eba97 NC |
4708 | fixp->fx_file = fragp->fr_file; |
4709 | fixp->fx_line = fragp->fr_line; | |
4710 | ||
4711 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
4712 | + fragp->fr_fix + fragp->fr_var); | |
4713 | ||
4714 | fragp->fr_fix += fragp->fr_var; | |
4715 | } | |
4716 | ||
4717 | /* Relax a machine dependent frag. This returns the amount by which | |
4718 | the current size of the frag should change. */ | |
4719 | ||
4720 | void | |
4721 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
4722 | fragS *fragp) | |
4723 | { | |
4724 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
4725 | md_convert_frag_branch (fragp); | |
4726 | } | |
4727 | ||
4728 | void | |
4729 | md_show_usage (FILE *stream) | |
4730 | { | |
4731 | fprintf (stream, _("\ | |
4732 | RISC-V options:\n\ | |
437e2ff1 | 4733 | -fpic or -fPIC generate position-independent code\n\ |
8f595e9b NC |
4734 | -fno-pic don't generate position-independent code (default)\n\ |
4735 | -march=ISA set the RISC-V architecture\n\ | |
4736 | -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ | |
86d39e66 | 4737 | -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\ |
8f595e9b NC |
4738 | -mabi=ABI set the RISC-V ABI\n\ |
4739 | -mrelax enable relax (default)\n\ | |
4740 | -mno-relax disable relax\n\ | |
4741 | -march-attr generate RISC-V arch attribute\n\ | |
4742 | -mno-arch-attr don't generate RISC-V arch attribute\n\ | |
437e2ff1 NC |
4743 | -mcsr-check enable the csr ISA and privilege spec version checks\n\ |
4744 | -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\ | |
4745 | -mbig-endian assemble for big-endian\n\ | |
4746 | -mlittle-endian assemble for little-endian\n\ | |
e23eba97 NC |
4747 | ")); |
4748 | } | |
4749 | ||
4750 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
dcd709e0 | 4751 | |
e23eba97 NC |
4752 | void |
4753 | riscv_cfi_frame_initial_instructions (void) | |
4754 | { | |
4755 | cfi_add_CFA_def_cfa_register (X_SP); | |
4756 | } | |
4757 | ||
4758 | int | |
4759 | tc_riscv_regname_to_dw2regnum (char *regname) | |
4760 | { | |
4761 | int reg; | |
4762 | ||
4763 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
4764 | return reg; | |
4765 | ||
4766 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
4767 | return reg + 32; | |
4768 | ||
7b4f2407 TO |
4769 | if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0) |
4770 | return reg + 96; | |
4771 | ||
4762fe62 AB |
4772 | /* CSRs are numbered 4096 -> 8191. */ |
4773 | if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) | |
4774 | return reg + 4096; | |
4775 | ||
e23eba97 NC |
4776 | as_bad (_("unknown register `%s'"), regname); |
4777 | return -1; | |
4778 | } | |
4779 | ||
4780 | void | |
4781 | riscv_elf_final_processing (void) | |
4782 | { | |
6e1605e4 | 4783 | riscv_set_abi_by_arch (); |
40f1a1a4 | 4784 | riscv_release_subset_list (riscv_rps_as.subset_list); |
e23eba97 | 4785 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
4786 | } |
4787 | ||
4788 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
4789 | since these directives break relaxation when used with symbol deltas. */ | |
4790 | ||
4791 | static void | |
4792 | s_riscv_leb128 (int sign) | |
4793 | { | |
4794 | expressionS exp; | |
4795 | char *save_in = input_line_pointer; | |
4796 | ||
4797 | expression (&exp); | |
f1cd8b94 KLC |
4798 | if (sign && exp.X_op != O_constant) |
4799 | as_bad (_("non-constant .sleb128 is not supported")); | |
4800 | else if (!sign && exp.X_op != O_constant && exp.X_op != O_subtract) | |
4801 | as_bad (_(".uleb128 only supports constant or subtract expressions")); | |
4802 | ||
e23eba97 NC |
4803 | demand_empty_rest_of_line (); |
4804 | ||
4805 | input_line_pointer = save_in; | |
4806 | return s_leb128 (sign); | |
4807 | } | |
4808 | ||
a262b82f NC |
4809 | /* Parse the .insn directive. There are three formats, |
4810 | Format 1: .insn <type> <operand1>, <operand2>, ... | |
4811 | Format 2: .insn <length>, <value> | |
4812 | Format 3: .insn <value>. */ | |
0e35537d JW |
4813 | |
4814 | static void | |
4815 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
4816 | { | |
4817 | char *str = input_line_pointer; | |
4818 | struct riscv_cl_insn insn; | |
4819 | expressionS imm_expr; | |
4820 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
4821 | char save_c; | |
4822 | ||
4823 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4824 | ++input_line_pointer; | |
4825 | ||
4826 | save_c = *input_line_pointer; | |
4827 | *input_line_pointer = '\0'; | |
4828 | ||
3190ebcb | 4829 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 4830 | |
e4028336 | 4831 | struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
0e35537d | 4832 | &imm_reloc, insn_type_hash); |
e4028336 | 4833 | if (error.msg) |
0e35537d | 4834 | { |
a262b82f | 4835 | char *save_in = input_line_pointer; |
e4028336 | 4836 | error.msg = riscv_ip_hardcode (str, &insn, &imm_expr, error.msg); |
a262b82f | 4837 | input_line_pointer = save_in; |
0e35537d | 4838 | } |
a262b82f | 4839 | |
e4028336 PN |
4840 | if (error.msg) |
4841 | { | |
4842 | if (error.missing_ext) | |
4843 | as_bad ("%s `%s', extension `%s' required", error.msg, error.statement, | |
4844 | error.missing_ext); | |
4845 | else | |
4846 | as_bad ("%s `%s'", error.msg, error.statement); | |
4847 | } | |
634001bb | 4848 | else |
0e35537d JW |
4849 | { |
4850 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
4851 | append_insn (&insn, &imm_expr, imm_reloc); | |
4852 | } | |
4853 | ||
4854 | *input_line_pointer = save_c; | |
4855 | demand_empty_rest_of_line (); | |
4856 | } | |
4857 | ||
dcd709e0 NC |
4858 | /* Update architecture and privileged elf attributes. If we don't set |
4859 | them, then try to output the default ones. */ | |
2dc8dd17 JW |
4860 | |
4861 | static void | |
8f595e9b | 4862 | riscv_write_out_attrs (void) |
2dc8dd17 | 4863 | { |
8f595e9b | 4864 | const char *arch_str, *priv_str, *p; |
dcd709e0 NC |
4865 | /* versions[0]: major version. |
4866 | versions[1]: minor version. | |
4867 | versions[2]: revision version. */ | |
8f595e9b NC |
4868 | unsigned versions[3] = {0}, number = 0; |
4869 | unsigned int i; | |
2dc8dd17 | 4870 | |
dcd709e0 | 4871 | /* Re-write architecture elf attribute. */ |
40f1a1a4 | 4872 | arch_str = riscv_rps_as.subset_list->arch_str; |
a1d1634d AM |
4873 | if (!bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str)) |
4874 | as_fatal (_("error adding attribute: %s"), | |
4875 | bfd_errmsg (bfd_get_error ())); | |
8f595e9b NC |
4876 | |
4877 | /* For the file without any instruction, we don't set the default_priv_spec | |
dcd709e0 NC |
4878 | according to the privileged elf attributes since the md_assemble isn't |
4879 | called. */ | |
8f595e9b NC |
4880 | if (!start_assemble |
4881 | && !riscv_set_default_priv_spec (NULL)) | |
4882 | return; | |
4883 | ||
dcd709e0 NC |
4884 | /* If we already have set privileged elf attributes, then no need to do |
4885 | anything. Otherwise, don't generate or update them when no CSR and | |
4886 | privileged instructions are used. */ | |
1a79004f | 4887 | if (!explicit_priv_attr) |
3fc6c3dc NC |
4888 | return; |
4889 | ||
3d73d29e | 4890 | RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec); |
8f595e9b NC |
4891 | p = priv_str; |
4892 | for (i = 0; *p; ++p) | |
4893 | { | |
4894 | if (*p == '.' && i < 3) | |
4895 | { | |
4896 | versions[i++] = number; | |
4897 | number = 0; | |
4898 | } | |
4899 | else if (ISDIGIT (*p)) | |
4900 | number = (number * 10) + (*p - '0'); | |
4901 | else | |
4902 | { | |
b800637e | 4903 | as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str); |
8f595e9b NC |
4904 | return; |
4905 | } | |
4906 | } | |
4907 | versions[i] = number; | |
4908 | ||
dcd709e0 | 4909 | /* Re-write privileged elf attributes. */ |
a1d1634d AM |
4910 | if (!bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, |
4911 | versions[0]) | |
4912 | || !bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, | |
4913 | versions[1]) | |
4914 | || !bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, | |
4915 | versions[2])) | |
4916 | as_fatal (_("error adding attribute: %s"), | |
4917 | bfd_errmsg (bfd_get_error ())); | |
2dc8dd17 JW |
4918 | } |
4919 | ||
dcd709e0 | 4920 | /* Add the default contents for the .riscv.attributes section. */ |
2dc8dd17 JW |
4921 | |
4922 | static void | |
4923 | riscv_set_public_attributes (void) | |
4924 | { | |
8f595e9b NC |
4925 | if (riscv_opts.arch_attr || explicit_attr) |
4926 | riscv_write_out_attrs (); | |
2dc8dd17 JW |
4927 | } |
4928 | ||
f1cd8b94 KLC |
4929 | /* Scan uleb128 subtraction expressions and insert fixups for them. |
4930 | e.g., .uleb128 .L1 - .L0 | |
4931 | Because relaxation may change the value of the subtraction, we | |
4932 | must resolve them at link-time. */ | |
4933 | ||
4934 | static void | |
4935 | riscv_insert_uleb128_fixes (bfd *abfd ATTRIBUTE_UNUSED, | |
4936 | asection *sec, void *xxx ATTRIBUTE_UNUSED) | |
4937 | { | |
4938 | segment_info_type *seginfo = seg_info (sec); | |
4939 | struct frag *fragP; | |
4940 | ||
4941 | subseg_set (sec, 0); | |
4942 | ||
4943 | for (fragP = seginfo->frchainP->frch_root; | |
4944 | fragP; fragP = fragP->fr_next) | |
4945 | { | |
4946 | expressionS *exp, *exp_dup; | |
4947 | ||
4948 | if (fragP->fr_type != rs_leb128 || fragP->fr_symbol == NULL) | |
4949 | continue; | |
4950 | ||
4951 | exp = symbol_get_value_expression (fragP->fr_symbol); | |
4952 | ||
4953 | if (exp->X_op != O_subtract) | |
4954 | continue; | |
4955 | ||
4956 | /* Only unsigned leb128 can be handled. */ | |
4957 | gas_assert (fragP->fr_subtype == 0); | |
4958 | exp_dup = xmemdup (exp, sizeof (*exp), sizeof (*exp)); | |
4959 | exp_dup->X_op = O_symbol; | |
4960 | exp_dup->X_op_symbol = NULL; | |
4961 | ||
4962 | /* Insert relocations to resolve the subtraction at link-time. | |
4963 | Emit the SET relocation first in riscv. */ | |
4964 | exp_dup->X_add_symbol = exp->X_add_symbol; | |
4965 | fix_new_exp (fragP, fragP->fr_fix, 0, | |
4966 | exp_dup, 0, BFD_RELOC_RISCV_SET_ULEB128); | |
4967 | exp_dup->X_add_symbol = exp->X_op_symbol; | |
2029e139 | 4968 | exp_dup->X_add_number = 0; /* Set addend of SUB_ULEB128 to zero. */ |
f1cd8b94 KLC |
4969 | fix_new_exp (fragP, fragP->fr_fix, 0, |
4970 | exp_dup, 0, BFD_RELOC_RISCV_SUB_ULEB128); | |
dc63d568 | 4971 | free ((void *) exp_dup); |
f1cd8b94 KLC |
4972 | } |
4973 | } | |
4974 | ||
2dc8dd17 JW |
4975 | /* Called after all assembly has been done. */ |
4976 | ||
4977 | void | |
ed2917de | 4978 | riscv_md_finish (void) |
2dc8dd17 JW |
4979 | { |
4980 | riscv_set_public_attributes (); | |
f1cd8b94 KLC |
4981 | if (riscv_opts.relax) |
4982 | bfd_map_over_sections (stdoutput, riscv_insert_uleb128_fixes, NULL); | |
2dc8dd17 JW |
4983 | } |
4984 | ||
9b9b1092 NC |
4985 | /* Adjust the symbol table. */ |
4986 | ||
4987 | void | |
4988 | riscv_adjust_symtab (void) | |
4989 | { | |
4990 | bfd_map_over_sections (stdoutput, riscv_check_mapping_symbols, (char *) 0); | |
4991 | elf_adjust_symtab (); | |
4992 | } | |
4993 | ||
2dc8dd17 JW |
4994 | /* Given a symbolic attribute NAME, return the proper integer value. |
4995 | Returns -1 if the attribute is not known. */ | |
4996 | ||
4997 | int | |
4998 | riscv_convert_symbolic_attribute (const char *name) | |
4999 | { | |
5000 | static const struct | |
5001 | { | |
1942a048 NC |
5002 | const char *name; |
5003 | const int tag; | |
2dc8dd17 JW |
5004 | } |
5005 | attribute_table[] = | |
1942a048 NC |
5006 | { |
5007 | /* When you modify this table you should | |
5008 | also modify the list in doc/c-riscv.texi. */ | |
5009 | #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag} | |
5010 | T(arch), | |
5011 | T(priv_spec), | |
5012 | T(priv_spec_minor), | |
5013 | T(priv_spec_revision), | |
5014 | T(unaligned_access), | |
5015 | T(stack_align), | |
2dc8dd17 | 5016 | #undef T |
1942a048 | 5017 | }; |
2dc8dd17 JW |
5018 | |
5019 | if (name == NULL) | |
5020 | return -1; | |
5021 | ||
1942a048 | 5022 | unsigned int i; |
2dc8dd17 JW |
5023 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
5024 | if (strcmp (name, attribute_table[i].name) == 0) | |
5025 | return attribute_table[i].tag; | |
5026 | ||
5027 | return -1; | |
5028 | } | |
5029 | ||
5030 | /* Parse a .attribute directive. */ | |
5031 | ||
5032 | static void | |
5033 | s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) | |
5034 | { | |
5035 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); | |
8f595e9b NC |
5036 | unsigned old_xlen; |
5037 | obj_attribute *attr; | |
2dc8dd17 | 5038 | |
5b7c81bd | 5039 | explicit_attr = true; |
8f595e9b | 5040 | switch (tag) |
2dc8dd17 | 5041 | { |
8f595e9b NC |
5042 | case Tag_RISCV_arch: |
5043 | old_xlen = xlen; | |
2dc8dd17 JW |
5044 | attr = elf_known_obj_attributes_proc (stdoutput); |
5045 | if (!start_assemble) | |
5046 | riscv_set_arch (attr[Tag_RISCV_arch].s); | |
5047 | else | |
b800637e NC |
5048 | as_fatal (_("architecture elf attributes must set before " |
5049 | "any instructions")); | |
2dc8dd17 JW |
5050 | |
5051 | if (old_xlen != xlen) | |
5052 | { | |
5053 | /* We must re-init bfd again if xlen is changed. */ | |
5054 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
5055 | bfd_find_target (riscv_target_format (), stdoutput); | |
5056 | ||
5057 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 5058 | as_warn (_("could not set architecture and machine")); |
2dc8dd17 | 5059 | } |
8f595e9b NC |
5060 | break; |
5061 | ||
5062 | case Tag_RISCV_priv_spec: | |
5063 | case Tag_RISCV_priv_spec_minor: | |
5064 | case Tag_RISCV_priv_spec_revision: | |
5065 | if (start_assemble) | |
b800637e NC |
5066 | as_fatal (_("privileged elf attributes must set before " |
5067 | "any instructions")); | |
8f595e9b NC |
5068 | break; |
5069 | ||
5070 | default: | |
5071 | break; | |
2dc8dd17 JW |
5072 | } |
5073 | } | |
5074 | ||
8155b853 NC |
5075 | /* Mark symbol that it follows a variant CC convention. */ |
5076 | ||
5077 | static void | |
5078 | s_variant_cc (int ignored ATTRIBUTE_UNUSED) | |
5079 | { | |
5080 | char *name; | |
5081 | char c; | |
5082 | symbolS *sym; | |
5083 | asymbol *bfdsym; | |
5084 | elf_symbol_type *elfsym; | |
5085 | ||
5086 | c = get_symbol_name (&name); | |
5087 | if (!*name) | |
5088 | as_bad (_("missing symbol name for .variant_cc directive")); | |
5089 | sym = symbol_find_or_make (name); | |
5090 | restore_line_pointer (c); | |
5091 | demand_empty_rest_of_line (); | |
5092 | ||
5093 | bfdsym = symbol_get_bfdsym (sym); | |
5094 | elfsym = elf_symbol_from (bfdsym); | |
5095 | gas_assert (elfsym); | |
5096 | elfsym->internal_elf_sym.st_other |= STO_RISCV_VARIANT_CC; | |
5097 | } | |
5098 | ||
5099 | /* Same as elf_copy_symbol_attributes, but without copying st_other. | |
5100 | This is needed so RISC-V specific st_other values can be independently | |
5101 | specified for an IFUNC resolver (that is called by the dynamic linker) | |
5102 | and the symbol it resolves (aliased to the resolver). In particular, | |
5103 | if a function symbol has special st_other value set via directives, | |
5104 | then attaching an IFUNC resolver to that symbol should not override | |
5105 | the st_other setting. Requiring the directive on the IFUNC resolver | |
5106 | symbol would be unexpected and problematic in C code, where the two | |
5107 | symbols appear as two independent function declarations. */ | |
5108 | ||
5109 | void | |
5110 | riscv_elf_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
5111 | { | |
5112 | struct elf_obj_sy *srcelf = symbol_get_obj (src); | |
5113 | struct elf_obj_sy *destelf = symbol_get_obj (dest); | |
a3a7f5e1 FS |
5114 | /* If size is unset, copy size from src. Because we don't track whether |
5115 | .size has been used, we can't differentiate .size dest, 0 from the case | |
5116 | where dest's size is unset. */ | |
5117 | if (!destelf->size && S_GET_SIZE (dest) == 0) | |
8155b853 | 5118 | { |
a3a7f5e1 FS |
5119 | if (srcelf->size) |
5120 | { | |
5121 | destelf->size = XNEW (expressionS); | |
5122 | *destelf->size = *srcelf->size; | |
5123 | } | |
5124 | S_SET_SIZE (dest, S_GET_SIZE (src)); | |
8155b853 | 5125 | } |
8155b853 NC |
5126 | } |
5127 | ||
dcd709e0 | 5128 | /* RISC-V pseudo-ops table. */ |
e23eba97 NC |
5129 | static const pseudo_typeS riscv_pseudo_table[] = |
5130 | { | |
e23eba97 NC |
5131 | {"option", s_riscv_option, 0}, |
5132 | {"half", cons, 2}, | |
5133 | {"word", cons, 4}, | |
5134 | {"dword", cons, 8}, | |
5135 | {"dtprelword", s_dtprel, 4}, | |
5136 | {"dtpreldword", s_dtprel, 8}, | |
5137 | {"bss", s_bss, 0}, | |
e23eba97 NC |
5138 | {"uleb128", s_riscv_leb128, 0}, |
5139 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 5140 | {"insn", s_riscv_insn, 0}, |
2dc8dd17 | 5141 | {"attribute", s_riscv_attribute, 0}, |
8155b853 | 5142 | {"variant_cc", s_variant_cc, 0}, |
035784e3 | 5143 | {"float16", float_cons, 'h'}, |
e23eba97 NC |
5144 | |
5145 | { NULL, NULL, 0 }, | |
5146 | }; | |
5147 | ||
5148 | void | |
5149 | riscv_pop_insert (void) | |
5150 | { | |
5151 | extern void pop_insert (const pseudo_typeS *); | |
5152 | ||
5153 | pop_insert (riscv_pseudo_table); | |
5154 | } |