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Jakub Jelinek <jj@ultra.linux.cz>
[thirdparty/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
252b5132 1/* tc-sparc.c -- Assemble for the SPARC
49309057 2 Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc.
252b5132
RH		 3 This file is part of GAS, the GNU Assembler.
4
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
19
20#include <stdio.h>
21#include <ctype.h>
22
23#include "as.h"
24#include "subsegs.h"
25
26#include "opcode/sparc.h"
27
28#ifdef OBJ_ELF
29#include "elf/sparc.h"
30#endif
31
32static struct sparc_arch *lookup_arch PARAMS ((char *));
33static void init_default_arch PARAMS ((void));
a22b281c 34static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 35static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
36static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
37static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 39static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
40static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
41static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 42static bfd_vma BSR PARAMS ((bfd_vma, int));
43static int cmp_reg_entry PARAMS ((const PTR, const PTR));
44static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
45static int parse_const_expr_arg PARAMS ((char **, int *));
46static int get_expression PARAMS ((char *str));
47
48/* Default architecture. */
49/* ??? The default value should be V8, but sparclite support was added
50 by making it the default. GCC now passes -Asparclite, so maybe sometime in
51 the future we can set this to V8. */
52#ifndef DEFAULT_ARCH
53#define DEFAULT_ARCH "sparclite"
54#endif
55static char *default_arch = DEFAULT_ARCH;
56
57/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
58 have been set. */
59static int default_init_p;
60
61/* Current architecture. We don't bump up unless necessary. */
62static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
63
64/* The maximum architecture level we can bump up to.
65 In a 32 bit environment, don't allow bumping up to v9 by default.
66 The native assembler works this way. The user is required to pass
67 an explicit argument before we'll create v9 object files. However, if
68 we don't see any v9 insns, a v8plus object file is not created. */
69static enum sparc_opcode_arch_val max_architecture;
70
71/* Either 32 or 64, selects file format. */
72static int sparc_arch_size;
73/* Initial (default) value, recorded separately in case a user option
74 changes the value before md_show_usage is called. */
75static int default_arch_size;
76
77#ifdef OBJ_ELF
78/* The currently selected v9 memory model. Currently only used for
79 ELF. */
80static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
81#endif
82
83static int architecture_requested;
84static int warn_on_bump;
85
86/* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88static enum sparc_opcode_arch_val warn_after_architecture;
89
90/* Non-zero if we are generating PIC code. */
91int sparc_pic_code;
92
93/* Non-zero if we should give an error when misaligned data is seen. */
94static int enforce_aligned_data;
95
96extern int target_big_endian;
97
98static int target_little_endian_data;
99
100/* V9 and 86x have big and little endian data, but instructions are always big
101 endian. The sparclet has bi-endian support but both data and insns have
102 the same endianness. Global `target_big_endian' is used for data.
103 The following macro is used for instructions. */
104#ifndef INSN_BIG_ENDIAN
105#define INSN_BIG_ENDIAN (target_big_endian \
106 || default_arch_type == sparc86x \
107 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
108#endif
109
110/* handle of the OPCODE hash table */
111static struct hash_control *op_hash;
112
113static int log2 PARAMS ((int));
114static void s_data1 PARAMS ((void));
115static void s_seg PARAMS ((int));
116static void s_proc PARAMS ((int));
117static void s_reserve PARAMS ((int));
118static void s_common PARAMS ((int));
119static void s_empty PARAMS ((int));
120static void s_uacons PARAMS ((int));
cf9a1301 121static void s_ncons PARAMS ((int));
252b5132
RH		 122
123const pseudo_typeS md_pseudo_table[] =
124{
125 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
126 {"common", s_common, 0},
127 {"empty", s_empty, 0},
128 {"global", s_globl, 0},
129 {"half", cons, 2},
cf9a1301 130 {"nword", s_ncons, 0},
252b5132
RH		 131 {"optim", s_ignore, 0},
132 {"proc", s_proc, 0},
133 {"reserve", s_reserve, 0},
134 {"seg", s_seg, 0},
135 {"skip", s_space, 0},
136 {"word", cons, 4},
137 {"xword", cons, 8},
138 {"uahalf", s_uacons, 2},
139 {"uaword", s_uacons, 4},
140 {"uaxword", s_uacons, 8},
141#ifdef OBJ_ELF
142 /* these are specific to sparc/svr4 */
252b5132
RH		 143 {"2byte", s_uacons, 2},
144 {"4byte", s_uacons, 4},
145 {"8byte", s_uacons, 8},
146#endif
147 {NULL, 0, 0},
148};
149
150const int md_reloc_size = 12; /* Size of relocation record */
151
152/* This array holds the chars that always start a comment. If the
153 pre-processor is disabled, these aren't very useful */
154const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
155
156/* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output */
159/* Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output. */
162/* Also note that comments started like this one will always
163 work if '/' isn't otherwise defined. */
164const char line_comment_chars[] = "#";
165
166const char line_separator_chars[] = "";
167
168/* Chars that can be used to separate mant from exp in floating point nums */
169const char EXP_CHARS[] = "eE";
170
171/* Chars that mean this number is a floating point constant */
172/* As in 0f12.456 */
173/* or 0d1.2345e12 */
174const char FLT_CHARS[] = "rRsSfFdDxXpP";
175
176/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
177 changed in read.c. Ideally it shouldn't have to know about it at all,
178 but nothing is ideal around here. */
179
a22b281c 180#define isoctal(c) ((unsigned)((c) - '0') < '8')
252b5132
RH		 181
182struct sparc_it
183 {
184 char *error;
185 unsigned long opcode;
186 struct nlist *nlistp;
187 expressionS exp;
cf9a1301 188 expressionS exp2;
252b5132
RH		 189 int pcrel;
190 bfd_reloc_code_real_type reloc;
191 };
192
193struct sparc_it the_insn, set_insn;
194
195static void output_insn
196 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
197\f
198/* Table of arguments to -A.
199 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
200 for this use. That table is for opcodes only. This table is for opcodes
201 and file formats. */
202
203enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
204 v8plusa, v9, v9a, v9_64};
205
206static struct sparc_arch {
207 char *name;
208 char *opcode_arch;
209 enum sparc_arch_types arch_type;
210 /* Default word size, as specified during configuration.
211 A value of zero means can't be used to specify default architecture. */
212 int default_arch_size;
213 /* Allowable arg to -A? */
214 int user_option_p;
215} sparc_arch_table[] = {
216 { "v6", "v6", v6, 0, 1 },
217 { "v7", "v7", v7, 0, 1 },
218 { "v8", "v8", v8, 32, 1 },
219 { "sparclet", "sparclet", sparclet, 32, 1 },
220 { "sparclite", "sparclite", sparclite, 32, 1 },
221 { "sparc86x", "sparclite", sparc86x, 32, 1 },
222 { "v8plus", "v9", v9, 0, 1 },
223 { "v8plusa", "v9a", v9, 0, 1 },
224 { "v9", "v9", v9, 0, 1 },
225 { "v9a", "v9a", v9, 0, 1 },
226 /* This exists to allow configure.in/Makefile.in to pass one
227 value to specify both the default machine and default word size. */
228 { "v9-64", "v9", v9, 64, 0 },
229 { NULL, NULL, v8, 0, 0 }
230};
231
232/* Variant of default_arch */
233static enum sparc_arch_types default_arch_type;
234
235static struct sparc_arch *
236lookup_arch (name)
237 char *name;
238{
239 struct sparc_arch *sa;
240
241 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
242 if (strcmp (sa->name, name) == 0)
243 break;
244 if (sa->name == NULL)
245 return NULL;
246 return sa;
247}
248
249/* Initialize the default opcode arch and word size from the default
250 architecture name. */
251
252static void
253init_default_arch ()
254{
255 struct sparc_arch *sa = lookup_arch (default_arch);
256
257 if (sa == NULL
258 || sa->default_arch_size == 0)
259 as_fatal (_("Invalid default architecture, broken assembler."));
260
261 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
262 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
263 as_fatal (_("Bad opcode table, broken assembler."));
264 default_arch_size = sparc_arch_size = sa->default_arch_size;
265 default_init_p = 1;
266 default_arch_type = sa->arch_type;
267}
268
269/* Called by TARGET_FORMAT. */
270
271const char *
272sparc_target_format ()
273{
274 /* We don't get a chance to initialize anything before we're called,
275 so handle that now. */
276 if (! default_init_p)
277 init_default_arch ();
278
279#ifdef OBJ_AOUT
280#ifdef TE_NetBSD
281 return "a.out-sparc-netbsd";
282#else
283#ifdef TE_SPARCAOUT
284 if (target_big_endian)
285 return "a.out-sunos-big";
286 else if (default_arch_type == sparc86x && target_little_endian_data)
287 return "a.out-sunos-big";
288 else return "a.out-sparc-little";
289#else
290 return "a.out-sunos-big";
291#endif
292#endif
293#endif
294
295#ifdef OBJ_BOUT
296 return "b.out.big";
297#endif
298
299#ifdef OBJ_COFF
300#ifdef TE_LYNX
301 return "coff-sparc-lynx";
302#else
303 return "coff-sparc";
304#endif
305#endif
306
307#ifdef OBJ_ELF
308 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
309#endif
310
311 abort ();
312}
313\f
314/*
315 * md_parse_option
316 * Invocation line includes a switch not recognized by the base assembler.
317 * See if it's a processor-specific option. These are:
318 *
319 * -bump
320 * Warn on architecture bumps. See also -A.
321 *
322 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
323 * Standard 32 bit architectures.
324 * -Av8plus, -Av8plusa
325 * Sparc64 in a 32 bit world.
326 * -Av9, -Av9a
327 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
328 * This used to only mean 64 bits, but properly specifying it
329 * complicated gcc's ASM_SPECs, so now opcode selection is
330 * specified orthogonally to word size (except when specifying
331 * the default, but that is an internal implementation detail).
332 * -xarch=v8plus, -xarch=v8plusa
333 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
334 *
335 * Select the architecture and possibly the file format.
336 * Instructions or features not supported by the selected
337 * architecture cause fatal errors.
338 *
339 * The default is to start at v6, and bump the architecture up
340 * whenever an instruction is seen at a higher level. In 32 bit
341 * environments, v9 is not bumped up to, the user must pass
342 * -Av8plus{,a}.
343 *
344 * If -bump is specified, a warning is printing when bumping to
345 * higher levels.
346 *
347 * If an architecture is specified, all instructions must match
348 * that architecture. Any higher level instructions are flagged
349 * as errors. Note that in the 32 bit environment specifying
350 * -Av8plus does not automatically create a v8plus object file, a
351 * v9 insn must be seen.
352 *
353 * If both an architecture and -bump are specified, the
354 * architecture starts at the specified level, but bumps are
355 * warnings. Note that we can't set `current_architecture' to
356 * the requested level in this case: in the 32 bit environment,
357 * we still must avoid creating v8plus object files unless v9
358 * insns are seen.
359 *
360 * Note:
361 * Bumping between incompatible architectures is always an
362 * error. For example, from sparclite to v9.
363 */
364
365#ifdef OBJ_ELF
366CONST char *md_shortopts = "A:K:VQ:sq";
367#else
368#ifdef OBJ_AOUT
369CONST char *md_shortopts = "A:k";
370#else
371CONST char *md_shortopts = "A:";
372#endif
373#endif
374struct option md_longopts[] = {
375#define OPTION_BUMP (OPTION_MD_BASE)
376 {"bump", no_argument, NULL, OPTION_BUMP},
377#define OPTION_SPARC (OPTION_MD_BASE + 1)
378 {"sparc", no_argument, NULL, OPTION_SPARC},
379#define OPTION_XARCH (OPTION_MD_BASE + 2)
380 {"xarch", required_argument, NULL, OPTION_XARCH},
381#ifdef OBJ_ELF
382#define OPTION_32 (OPTION_MD_BASE + 3)
383 {"32", no_argument, NULL, OPTION_32},
384#define OPTION_64 (OPTION_MD_BASE + 4)
385 {"64", no_argument, NULL, OPTION_64},
386#define OPTION_TSO (OPTION_MD_BASE + 5)
387 {"TSO", no_argument, NULL, OPTION_TSO},
388#define OPTION_PSO (OPTION_MD_BASE + 6)
389 {"PSO", no_argument, NULL, OPTION_PSO},
390#define OPTION_RMO (OPTION_MD_BASE + 7)
391 {"RMO", no_argument, NULL, OPTION_RMO},
392#endif
393#ifdef SPARC_BIENDIAN
394#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
395 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
396#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
397 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
398#endif
399#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
400 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
401#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
402 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
403 {NULL, no_argument, NULL, 0}
404};
405size_t md_longopts_size = sizeof(md_longopts);
406
407int
408md_parse_option (c, arg)
409 int c;
410 char *arg;
411{
412 /* We don't get a chance to initialize anything before we're called,
413 so handle that now. */
414 if (! default_init_p)
415 init_default_arch ();
416
417 switch (c)
418 {
419 case OPTION_BUMP:
420 warn_on_bump = 1;
421 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
422 break;
423
424 case OPTION_XARCH:
425 /* This is for compatibility with Sun's assembler. */
426 if (strcmp (arg, "v8plus") != 0
427 && strcmp (arg, "v8plusa") != 0)
428 {
429 as_bad (_("invalid architecture -xarch=%s"), arg);
430 return 0;
431 }
432
433 /* fall through */
434
435 case 'A':
436 {
437 struct sparc_arch *sa;
438 enum sparc_opcode_arch_val opcode_arch;
439
440 sa = lookup_arch (arg);
441 if (sa == NULL
442 || ! sa->user_option_p)
443 {
444 as_bad (_("invalid architecture -A%s"), arg);
445 return 0;
446 }
447
448 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
449 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
450 as_fatal (_("Bad opcode table, broken assembler."));
451
452 max_architecture = opcode_arch;
453 architecture_requested = 1;
454 }
455 break;
456
457 case OPTION_SPARC:
458 /* Ignore -sparc, used by SunOS make default .s.o rule. */
459 break;
460
461 case OPTION_ENFORCE_ALIGNED_DATA:
462 enforce_aligned_data = 1;
463 break;
464
465#ifdef SPARC_BIENDIAN
466 case OPTION_LITTLE_ENDIAN:
467 target_big_endian = 0;
468 if (default_arch_type != sparclet)
469 as_fatal ("This target does not support -EL");
470 break;
471 case OPTION_LITTLE_ENDIAN_DATA:
472 target_little_endian_data = 1;
473 target_big_endian = 0;
474 if (default_arch_type != sparc86x
475 && default_arch_type != v9)
476 as_fatal ("This target does not support --little-endian-data");
477 break;
478 case OPTION_BIG_ENDIAN:
479 target_big_endian = 1;
480 break;
481#endif
482
483#ifdef OBJ_AOUT
484 case 'k':
485 sparc_pic_code = 1;
486 break;
487#endif
488
489#ifdef OBJ_ELF
490 case OPTION_32:
491 case OPTION_64:
492 {
493 const char **list, **l;
494
495 sparc_arch_size = c == OPTION_32 ? 32 : 64;
496 list = bfd_target_list ();
497 for (l = list; *l != NULL; l++)
498 {
499 if (sparc_arch_size == 32)
500 {
501 if (strcmp (*l, "elf32-sparc") == 0)
502 break;
503 }
504 else
505 {
506 if (strcmp (*l, "elf64-sparc") == 0)
507 break;
508 }
509 }
510 if (*l == NULL)
511 as_fatal (_("No compiled in support for %d bit object file format"),
512 sparc_arch_size);
513 free (list);
514 }
515 break;
516
517 case OPTION_TSO:
518 sparc_memory_model = MM_TSO;
519 break;
520
521 case OPTION_PSO:
522 sparc_memory_model = MM_PSO;
523 break;
524
525 case OPTION_RMO:
526 sparc_memory_model = MM_RMO;
527 break;
528
529 case 'V':
530 print_version_id ();
531 break;
532
533 case 'Q':
534 /* Qy - do emit .comment
535 Qn - do not emit .comment */
536 break;
537
538 case 's':
539 /* use .stab instead of .stab.excl */
540 break;
541
542 case 'q':
543 /* quick -- native assembler does fewer checks */
544 break;
545
546 case 'K':
547 if (strcmp (arg, "PIC") != 0)
548 as_warn (_("Unrecognized option following -K"));
549 else
550 sparc_pic_code = 1;
551 break;
552#endif
553
554 default:
555 return 0;
556 }
557
558 return 1;
559}
560
561void
562md_show_usage (stream)
563 FILE *stream;
564{
565 const struct sparc_arch *arch;
566
567 /* We don't get a chance to initialize anything before we're called,
568 so handle that now. */
569 if (! default_init_p)
570 init_default_arch ();
571
572 fprintf(stream, _("SPARC options:\n"));
573 for (arch = &sparc_arch_table[0]; arch->name; arch++)
574 {
575 if (arch != &sparc_arch_table[0])
576 fprintf (stream, " | ");
577 if (arch->user_option_p)
578 fprintf (stream, "-A%s", arch->name);
579 }
580 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
581 fprintf (stream, _("\
582 specify variant of SPARC architecture\n\
583-bump warn when assembler switches architectures\n\
584-sparc ignored\n\
585--enforce-aligned-data force .long, etc., to be aligned correctly\n"));
586#ifdef OBJ_AOUT
587 fprintf (stream, _("\
588-k generate PIC\n"));
589#endif
590#ifdef OBJ_ELF
591 fprintf (stream, _("\
592-32 create 32 bit object file\n\
593-64 create 64 bit object file\n"));
594 fprintf (stream, _("\
595 [default is %d]\n"), default_arch_size);
596 fprintf (stream, _("\
597-TSO use Total Store Ordering\n\
598-PSO use Partial Store Ordering\n\
599-RMO use Relaxed Memory Ordering\n"));
600 fprintf (stream, _("\
601 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
602 fprintf (stream, _("\
603-KPIC generate PIC\n\
604-V print assembler version number\n\
605-q ignored\n\
606-Qy, -Qn ignored\n\
607-s ignored\n"));
608#endif
609#ifdef SPARC_BIENDIAN
610 fprintf (stream, _("\
611-EL generate code for a little endian machine\n\
612-EB generate code for a big endian machine\n\
613--little-endian-data generate code for a machine having big endian\n\
614 instructions and little endian data."));
615#endif
616}
617\f
cf9a1301
RH		 618/* native operand size opcode translation */
619struct
620 {
621 char *name;
622 char *name32;
623 char *name64;
624 } native_op_table[] =
625{
626 {"ldn", "ld", "ldx"},
627 {"ldna", "lda", "ldxa"},
628 {"stn", "st", "stx"},
629 {"stna", "sta", "stxa"},
630 {"slln", "sll", "sllx"},
631 {"srln", "srl", "srlx"},
632 {"sran", "sra", "srax"},
633 {"casn", "cas", "casx"},
634 {"casna", "casa", "casxa"},
635 {"clrn", "clr", "clrx"},
636 {NULL, NULL, NULL},
637};
638\f
252b5132
RH		 639/* sparc64 priviledged registers */
640
641struct priv_reg_entry
642 {
643 char *name;
644 int regnum;
645 };
646
647struct priv_reg_entry priv_reg_table[] =
648{
649 {"tpc", 0},
650 {"tnpc", 1},
651 {"tstate", 2},
652 {"tt", 3},
653 {"tick", 4},
654 {"tba", 5},
655 {"pstate", 6},
656 {"tl", 7},
657 {"pil", 8},
658 {"cwp", 9},
659 {"cansave", 10},
660 {"canrestore", 11},
661 {"cleanwin", 12},
662 {"otherwin", 13},
663 {"wstate", 14},
664 {"fq", 15},
665 {"ver", 31},
666 {"", -1}, /* end marker */
667};
668
669/* v9a specific asrs */
670
671struct priv_reg_entry v9a_asr_table[] =
672{
673 {"tick_cmpr", 23},
674 {"softint", 22},
675 {"set_softint", 20},
676 {"pic", 17},
677 {"pcr", 16},
678 {"gsr", 19},
679 {"dcr", 18},
680 {"clear_softint", 21},
681 {"", -1}, /* end marker */
682};
683
684static int
685cmp_reg_entry (parg, qarg)
686 const PTR parg;
687 const PTR qarg;
688{
689 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
690 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
691
692 return strcmp (q->name, p->name);
693}
694\f
695/* This function is called once, at assembler startup time. It should
696 set up all the tables, etc. that the MD part of the assembler will need. */
697
698void
699md_begin ()
700{
701 register const char *retval = NULL;
702 int lose = 0;
703 register unsigned int i = 0;
704
705 /* We don't get a chance to initialize anything before md_parse_option
706 is called, and it may not be called, so handle default initialization
707 now if not already done. */
708 if (! default_init_p)
709 init_default_arch ();
710
711 op_hash = hash_new ();
712
713 while (i < (unsigned int) sparc_num_opcodes)
714 {
715 const char *name = sparc_opcodes[i].name;
716 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
717 if (retval != NULL)
718 {
cf9a1301
RH		 719 as_bad (_("Internal error: can't hash `%s': %s\n"),
720 sparc_opcodes[i].name, retval);
252b5132
RH		 721 lose = 1;
722 }
723 do
724 {
725 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
726 {
cf9a1301
RH		 727 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
728 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 729 lose = 1;
730 }
731 ++i;
732 }
733 while (i < (unsigned int) sparc_num_opcodes
734 && !strcmp (sparc_opcodes[i].name, name));
735 }
736
cf9a1301
RH		 737 for (i = 0; native_op_table[i].name; i++)
738 {
739 const struct sparc_opcode *insn;
740 char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
741 native_op_table[i].name64;
742 insn = (struct sparc_opcode *)hash_find (op_hash, name);
743 if (insn == NULL)
744 {
745 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
746 name, native_op_table[i].name);
747 lose = 1;
748 }
749 else
750 {
751 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
752 if (retval != NULL)
753 {
754 as_bad (_("Internal error: can't hash `%s': %s\n"),
755 sparc_opcodes[i].name, retval);
756 lose = 1;
757 }
758 }
759 }
760
252b5132
RH		 761 if (lose)
762 as_fatal (_("Broken assembler. No assembly attempted."));
763
252b5132
RH		 764 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
765 sizeof (priv_reg_table[0]), cmp_reg_entry);
766
767 /* If -bump, record the architecture level at which we start issuing
768 warnings. The behaviour is different depending upon whether an
769 architecture was explicitly specified. If it wasn't, we issue warnings
770 for all upwards bumps. If it was, we don't start issuing warnings until
771 we need to bump beyond the requested architecture or when we bump between
772 conflicting architectures. */
773
774 if (warn_on_bump
775 && architecture_requested)
776 {
777 /* `max_architecture' records the requested architecture.
778 Issue warnings if we go above it. */
779 warn_after_architecture = max_architecture;
780
781 /* Find the highest architecture level that doesn't conflict with
782 the requested one. */
783 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
784 max_architecture > warn_after_architecture;
785 --max_architecture)
786 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
787 warn_after_architecture))
788 break;
789 }
790}
791
792/* Called after all assembly has been done. */
793
794void
795sparc_md_end ()
796{
797 if (sparc_arch_size == 64)
798 {
799 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
800 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
801 else
802 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
803 }
804 else
805 {
806 if (current_architecture == SPARC_OPCODE_ARCH_V9)
807 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
808 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
809 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
810 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
811 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
812 else if (default_arch_type == sparc86x && target_little_endian_data)
813 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
814 else
815 {
816 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
817 be but for now it is (since that's the way it's always been
818 treated). */
819 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
820 }
821 }
822}
823\f
824/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
825
826static INLINE int
827in_signed_range (val, max)
828 bfd_signed_vma val, max;
829{
830 if (max <= 0)
831 abort ();
832 /* Sign-extend the value from the architecture word size, so that
833 0xffffffff is always considered -1 on sparc32. */
834 if (sparc_arch_size == 32)
835 {
836 bfd_signed_vma sign = (bfd_signed_vma)1 << 31;
837 val = ((val & 0xffffffff) ^ sign) - sign;
838 }
839 if (val > max)
840 return 0;
841 if (val < ~max)
842 return 0;
843 return 1;
844}
845
846/* Return non-zero if VAL is in the range 0 to MAX. */
847
848static INLINE int
849in_unsigned_range (val, max)
850 bfd_vma val, max;
851{
852 if (val > max)
853 return 0;
854 return 1;
855}
856
857/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
858 (e.g. -15 to +31). */
859
860static INLINE int
861in_bitfield_range (val, max)
862 bfd_signed_vma val, max;
863{
864 if (max <= 0)
865 abort ();
866 if (val > max)
867 return 0;
868 if (val < ~(max >> 1))
869 return 0;
870 return 1;
871}
872
873static int
874sparc_ffs (mask)
875 unsigned int mask;
876{
877 int i;
878
879 if (mask == 0)
880 return -1;
881
882 for (i = 0; (mask & 1) == 0; ++i)
883 mask >>= 1;
884 return i;
885}
886
887/* Implement big shift right. */
888static bfd_vma
889BSR (val, amount)
890 bfd_vma val;
891 int amount;
892{
893 if (sizeof (bfd_vma) <= 4 && amount >= 32)
894 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
895 return val >> amount;
896}
897\f
898/* For communication between sparc_ip and get_expression. */
899static char *expr_end;
900
252b5132
RH		 901/* Values for `special_case'.
902 Instructions that require wierd handling because they're longer than
903 4 bytes. */
904#define SPECIAL_CASE_NONE 0
905#define SPECIAL_CASE_SET 1
906#define SPECIAL_CASE_SETSW 2
907#define SPECIAL_CASE_SETX 3
908/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
909#define SPECIAL_CASE_FDIV 4
910
911/* Bit masks of various insns. */
912#define NOP_INSN 0x01000000
913#define OR_INSN 0x80100000
63fab58c 914#define XOR_INSN 0x80180000
252b5132
RH		 915#define FMOVS_INSN 0x81A00020
916#define SETHI_INSN 0x01000000
917#define SLLX_INSN 0x81281000
918#define SRA_INSN 0x81380000
919
920/* The last instruction to be assembled. */
921static const struct sparc_opcode *last_insn;
922/* The assembled opcode of `last_insn'. */
923static unsigned long last_opcode;
924\f
a22b281c
RH		 925/* Handle the set and setuw synthetic instructions. */
926static void
927synthetize_setuw (insn)
928 const struct sparc_opcode *insn;
929{
930 int need_hi22_p = 0;
931 int rd = (the_insn.opcode & RD (~0)) >> 25;
932
933 if (the_insn.exp.X_op == O_constant)
934 {
935 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
936 {
937 if (sizeof(offsetT) > 4
938 && (the_insn.exp.X_add_number < 0
939 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
940 as_warn (_("set: number not in 0..4294967295 range"));
941 }
942 else
943 {
944 if (sizeof(offsetT) > 4
945 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
946 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
947 as_warn (_("set: number not in -2147483648..4294967295 range"));
948 the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number;
949 }
950 }
951
952 /* See if operand is absolute and small; skip sethi if so. */
953 if (the_insn.exp.X_op != O_constant
954 || the_insn.exp.X_add_number >= (1 << 12)
955 || the_insn.exp.X_add_number < -(1 << 12))
956 {
957 the_insn.opcode = (SETHI_INSN | RD (rd)
958 | ((the_insn.exp.X_add_number >> 10)
959 & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0)));
960 the_insn.reloc = (the_insn.exp.X_op != O_constant
961 ? BFD_RELOC_HI22
962 : BFD_RELOC_NONE);
963 output_insn (insn, &the_insn);
964 need_hi22_p = 1;
965 }
966
967 /* See if operand has no low-order bits; skip OR if so. */
968 if (the_insn.exp.X_op != O_constant
969 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
970 || ! need_hi22_p)
971 {
972 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
973 | RD (rd) | IMMED
974 | (the_insn.exp.X_add_number
975 & (the_insn.exp.X_op != O_constant ? 0 :
976 need_hi22_p ? 0x3ff : 0x1fff)));
977 the_insn.reloc = (the_insn.exp.X_op != O_constant
978 ? BFD_RELOC_LO10
979 : BFD_RELOC_NONE);
980 output_insn (insn, &the_insn);
981 }
982}
983
984/* Handle the setsw synthetic instruction. */
985static void
986synthetize_setsw (insn)
987 const struct sparc_opcode *insn;
988{
989 int low32, rd, opc;
990
991 rd = (the_insn.opcode & RD (~0)) >> 25;
992
993 if (the_insn.exp.X_op != O_constant)
994 {
995 synthetize_setuw (insn);
996
997 /* Need to sign extend it. */
998 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
999 the_insn.reloc = BFD_RELOC_NONE;
1000 output_insn (insn, &the_insn);
1001 return;
1002 }
1003
1004 if (sizeof(offsetT) > 4
1005 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1006 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1007 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1008
1009 low32 = the_insn.exp.X_add_number;
1010
1011 if (low32 >= 0)
1012 {
1013 synthetize_setuw (insn);
1014 return;
1015 }
1016
1017 opc = OR_INSN;
1018
1019 the_insn.reloc = BFD_RELOC_NONE;
1020 /* See if operand is absolute and small; skip sethi if so. */
1021 if (low32 < -(1 << 12))
1022 {
1023 the_insn.opcode = (SETHI_INSN | RD (rd)
1024 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1025 output_insn (insn, &the_insn);
1026 low32 = 0x1c00 | (low32 & 0x3ff);
1027 opc = RS1 (rd) | XOR_INSN;
1028 }
1029
1030 the_insn.opcode = (opc | RD (rd) | IMMED
1031 | (low32 & 0x1fff));
1032 output_insn (insn, &the_insn);
1033}
1034
1035/* Handle the setsw synthetic instruction. */
1036static void
1037synthetize_setx (insn)
1038 const struct sparc_opcode *insn;
1039{
1040 int upper32, lower32;
1041 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1042 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1043 int upper_dstreg;
1044 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1045 int need_xor10_p = 0;
1046
1047#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1048 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1049 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1050#undef SIGNEXT32
1051
1052 upper_dstreg = tmpreg;
1053 /* The tmp reg should not be the dst reg. */
1054 if (tmpreg == dstreg)
1055 as_warn (_("setx: temporary register same as destination register"));
1056
1057 /* ??? Obviously there are other optimizations we can do
1058 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1059 doing some of these. Later. If you do change things, try to
1060 change all of this to be table driven as well. */
1061 /* What to output depends on the number if it's constant.
1062 Compute that first, then output what we've decided upon. */
1063 if (the_insn.exp.X_op != O_constant)
1064 {
1065 if (sparc_arch_size == 32)
1066 {
1067 /* When arch size is 32, we want setx to be equivalent
1068 to setuw for anything but constants. */
1069 the_insn.exp.X_add_number &= 0xffffffff;
1070 synthetize_setuw (insn);
1071 return;
1072 }
1073 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1074 lower32 = 0; upper32 = 0;
1075 }
1076 else
1077 {
1078 /* Reset X_add_number, we've extracted it as upper32/lower32.
1079 Otherwise fixup_segment will complain about not being able to
1080 write an 8 byte number in a 4 byte field. */
1081 the_insn.exp.X_add_number = 0;
1082
1083 /* Only need hh22 if `or' insn can't handle constant. */
1084 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1085 need_hh22_p = 1;
1086
1087 /* Does bottom part (after sethi) have bits? */
1088 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1089 /* No hh22, but does upper32 still have bits we can't set
1090 from lower32? */
1091 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1092 need_hm10_p = 1;
1093
1094 /* If the lower half is all zero, we build the upper half directly
1095 into the dst reg. */
1096 if (lower32 != 0
1097 /* Need lower half if number is zero or 0xffffffff00000000. */
1098 || (! need_hh22_p && ! need_hm10_p))
1099 {
1100 /* No need for sethi if `or' insn can handle constant. */
1101 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1102 /* Note that we can't use a negative constant in the `or'
1103 insn unless the upper 32 bits are all ones. */
1104 || (lower32 < 0 && upper32 != -1)
1105 || (lower32 >= 0 && upper32 == -1))
1106 need_hi22_p = 1;
1107
1108 if (need_hi22_p && upper32 == -1)
1109 need_xor10_p = 1;
1110
1111 /* Does bottom part (after sethi) have bits? */
1112 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1113 /* No sethi. */
1114 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1115 /* Need `or' if we didn't set anything else. */
1116 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1117 need_lo10_p = 1;
1118 }
1119 else
1120 /* Output directly to dst reg if lower 32 bits are all zero. */
1121 upper_dstreg = dstreg;
1122 }
1123
1124 if (!upper_dstreg && dstreg)
1125 as_warn (_("setx: illegal temporary register g0"));
1126
1127 if (need_hh22_p)
1128 {
1129 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1130 | ((upper32 >> 10) & 0x3fffff));
1131 the_insn.reloc = (the_insn.exp.X_op != O_constant
1132 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1133 output_insn (insn, &the_insn);
1134 }
1135
1136 if (need_hi22_p)
1137 {
1138 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1139 | (((need_xor10_p ? ~lower32 : lower32)
1140 >> 10) & 0x3fffff));
1141 the_insn.reloc = (the_insn.exp.X_op != O_constant
1142 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1143 output_insn (insn, &the_insn);
1144 }
1145
1146 if (need_hm10_p)
1147 {
1148 the_insn.opcode = (OR_INSN
1149 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1150 | RD (upper_dstreg)
1151 | IMMED
1152 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1153 the_insn.reloc = (the_insn.exp.X_op != O_constant
1154 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1155 output_insn (insn, &the_insn);
1156 }
1157
1158 if (need_lo10_p)
1159 {
1160 /* FIXME: One nice optimization to do here is to OR the low part
1161 with the highpart if hi22 isn't needed and the low part is
1162 positive. */
1163 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1164 | RD (dstreg)
1165 | IMMED
1166 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1167 the_insn.reloc = (the_insn.exp.X_op != O_constant
1168 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1169 output_insn (insn, &the_insn);
1170 }
1171
1172 /* If we needed to build the upper part, shift it into place. */
1173 if (need_hh22_p || need_hm10_p)
1174 {
1175 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1176 | IMMED | 32);
1177 the_insn.reloc = BFD_RELOC_NONE;
1178 output_insn (insn, &the_insn);
1179 }
1180
1181 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1182 if (need_xor10_p)
1183 {
1184 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1185 | 0x1c00 | (lower32 & 0x3ff));
1186 the_insn.reloc = BFD_RELOC_NONE;
1187 output_insn (insn, &the_insn);
1188 }
1189
1190 /* If we needed to build both upper and lower parts, OR them together. */
1191 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1192 {
1193 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1194 | RD (dstreg));
1195 the_insn.reloc = BFD_RELOC_NONE;
1196 output_insn (insn, &the_insn);
1197 }
1198}
1199\f
252b5132
RH		 1200/* Main entry point to assemble one instruction. */
1201
1202void
1203md_assemble (str)
1204 char *str;
1205{
1206 const struct sparc_opcode *insn;
a22b281c 1207 int special_case;
252b5132
RH		 1208
1209 know (str);
a22b281c 1210 special_case = sparc_ip (str, &insn);
252b5132
RH		 1211
1212 /* We warn about attempts to put a floating point branch in a delay slot,
1213 unless the delay slot has been annulled. */
1214 if (insn != NULL
1215 && last_insn != NULL
1216 && (insn->flags & F_FBR) != 0
1217 && (last_insn->flags & F_DELAYED) != 0
1218 /* ??? This test isn't completely accurate. We assume anything with
1219 F_{UNBR,CONDBR,FBR} set is annullable. */
1220 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1221 || (last_opcode & ANNUL) == 0))
1222 as_warn (_("FP branch in delay slot"));
1223
1224 /* SPARC before v9 requires a nop instruction between a floating
1225 point instruction and a floating point branch. We insert one
1226 automatically, with a warning. */
1227 if (max_architecture < SPARC_OPCODE_ARCH_V9
1228 && insn != NULL
1229 && last_insn != NULL
1230 && (insn->flags & F_FBR) != 0
1231 && (last_insn->flags & F_FLOAT) != 0)
1232 {
1233 struct sparc_it nop_insn;
1234
1235 nop_insn.opcode = NOP_INSN;
1236 nop_insn.reloc = BFD_RELOC_NONE;
1237 output_insn (insn, &nop_insn);
1238 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1239 }
1240
a22b281c
RH		 1241 switch (special_case)
1242 {
1243 case SPECIAL_CASE_NONE:
1244 /* normal insn */
1245 output_insn (insn, &the_insn);
1246 break;
252b5132 1247
a22b281c
RH		 1248 case SPECIAL_CASE_SETSW:
1249 synthetize_setsw (insn);
1250 break;
1251
1252 case SPECIAL_CASE_SET:
1253 synthetize_setuw (insn);
1254 break;
252b5132 1255
a22b281c
RH		 1256 case SPECIAL_CASE_SETX:
1257 synthetize_setx (insn);
1258 break;
1259
1260 case SPECIAL_CASE_FDIV:
1261 {
1262 int rd = (the_insn.opcode >> 25) & 0x1f;
63fab58c 1263
a22b281c 1264 output_insn (insn, &the_insn);
63fab58c 1265
a22b281c
RH		 1266 /* According to information leaked from Sun, the "fdiv" instructions
1267 on early SPARC machines would produce incorrect results sometimes.
1268 The workaround is to add an fmovs of the destination register to
1269 itself just after the instruction. This was true on machines
1270 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1271 assert (the_insn.reloc == BFD_RELOC_NONE);
1272 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1273 output_insn (insn, &the_insn);
1274 return;
1275 }
63fab58c 1276
a22b281c
RH		 1277 default:
1278 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1279 }
1280}
1281
1282/* Subroutine of md_assemble to do the actual parsing. */
1283
a22b281c 1284static int
252b5132
RH		 1285sparc_ip (str, pinsn)
1286 char *str;
1287 const struct sparc_opcode **pinsn;
1288{
1289 char *error_message = "";
1290 char *s;
1291 const char *args;
1292 char c;
1293 const struct sparc_opcode *insn;
1294 char *argsStart;
1295 unsigned long opcode;
1296 unsigned int mask = 0;
1297 int match = 0;
1298 int comma = 0;
1299 int v9_arg_p;
a22b281c 1300 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1301
1302 s = str;
1303 if (islower ((unsigned char) *s))
1304 {
1305 do
1306 ++s;
1307 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1308 }
1309
1310 switch (*s)
1311 {
1312 case '\0':
1313 break;
1314
1315 case ',':
1316 comma = 1;
1317
1318 /*FALLTHROUGH */
1319
1320 case ' ':
1321 *s++ = '\0';
1322 break;
1323
1324 default:
1325 as_fatal (_("Unknown opcode: `%s'"), str);
1326 }
1327 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1328 *pinsn = insn;
1329 if (insn == NULL)
1330 {
1331 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1332 return special_case;
252b5132
RH		 1333 }
1334 if (comma)
1335 {
1336 *--s = ',';
1337 }
1338
1339 argsStart = s;
1340 for (;;)
1341 {
1342 opcode = insn->match;
1343 memset (&the_insn, '\0', sizeof (the_insn));
1344 the_insn.reloc = BFD_RELOC_NONE;
1345 v9_arg_p = 0;
1346
1347 /*
1348 * Build the opcode, checking as we go to make
1349 * sure that the operands match
1350 */
1351 for (args = insn->args;; ++args)
1352 {
1353 switch (*args)
1354 {
1355 case 'K':
1356 {
1357 int kmask = 0;
1358
1359 /* Parse a series of masks. */
1360 if (*s == '#')
1361 {
1362 while (*s == '#')
1363 {
1364 int mask;
1365
1366 if (! parse_keyword_arg (sparc_encode_membar, &s,
1367 &mask))
1368 {
1369 error_message = _(": invalid membar mask name");
1370 goto error;
1371 }
1372 kmask |= mask;
1373 while (*s == ' ') { ++s; continue; }
1374 if (*s == '|' || *s == '+')
1375 ++s;
1376 while (*s == ' ') { ++s; continue; }
1377 }
1378 }
1379 else
1380 {
1381 if (! parse_const_expr_arg (&s, &kmask))
1382 {
1383 error_message = _(": invalid membar mask expression");
1384 goto error;
1385 }
1386 if (kmask < 0 || kmask > 127)
1387 {
1388 error_message = _(": invalid membar mask number");
1389 goto error;
1390 }
1391 }
1392
1393 opcode |= MEMBAR (kmask);
1394 continue;
1395 }
1396
1397 case '*':
1398 {
1399 int fcn = 0;
1400
1401 /* Parse a prefetch function. */
1402 if (*s == '#')
1403 {
1404 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1405 {
1406 error_message = _(": invalid prefetch function name");
1407 goto error;
1408 }
1409 }
1410 else
1411 {
1412 if (! parse_const_expr_arg (&s, &fcn))
1413 {
1414 error_message = _(": invalid prefetch function expression");
1415 goto error;
1416 }
1417 if (fcn < 0 || fcn > 31)
1418 {
1419 error_message = _(": invalid prefetch function number");
1420 goto error;
1421 }
1422 }
1423 opcode |= RD (fcn);
1424 continue;
1425 }
1426
1427 case '!':
1428 case '?':
1429 /* Parse a sparc64 privileged register. */
1430 if (*s == '%')
1431 {
1432 struct priv_reg_entry *p = priv_reg_table;
1433 unsigned int len = 9999999; /* init to make gcc happy */
1434
1435 s += 1;
1436 while (p->name[0] > s[0])
1437 p++;
1438 while (p->name[0] == s[0])
1439 {
1440 len = strlen (p->name);
1441 if (strncmp (p->name, s, len) == 0)
1442 break;
1443 p++;
1444 }
1445 if (p->name[0] != s[0])
1446 {
1447 error_message = _(": unrecognizable privileged register");
1448 goto error;
1449 }
1450 if (*args == '?')
1451 opcode |= (p->regnum << 14);
1452 else
1453 opcode |= (p->regnum << 25);
1454 s += len;
1455 continue;
1456 }
1457 else
1458 {
1459 error_message = _(": unrecognizable privileged register");
1460 goto error;
1461 }
1462
1463 case '_':
1464 case '/':
1465 /* Parse a v9a ancillary state register. */
1466 if (*s == '%')
1467 {
1468 struct priv_reg_entry *p = v9a_asr_table;
1469 unsigned int len = 9999999; /* init to make gcc happy */
1470
1471 s += 1;
1472 while (p->name[0] > s[0])
1473 p++;
1474 while (p->name[0] == s[0])
1475 {
1476 len = strlen (p->name);
1477 if (strncmp (p->name, s, len) == 0)
1478 break;
1479 p++;
1480 }
1481 if (p->name[0] != s[0])
1482 {
1483 error_message = _(": unrecognizable v9a ancillary state register");
1484 goto error;
1485 }
1486 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1487 {
1488 error_message = _(": rd on write only ancillary state register");
1489 goto error;
1490 }
1491 if (*args == '/')
1492 opcode |= (p->regnum << 14);
1493 else
1494 opcode |= (p->regnum << 25);
1495 s += len;
1496 continue;
1497 }
1498 else
1499 {
1500 error_message = _(": unrecognizable v9a ancillary state register");
1501 goto error;
1502 }
1503
1504 case 'M':
1505 case 'm':
1506 if (strncmp (s, "%asr", 4) == 0)
1507 {
1508 s += 4;
1509
1510 if (isdigit ((unsigned char) *s))
1511 {
1512 long num = 0;
1513
1514 while (isdigit ((unsigned char) *s))
1515 {
1516 num = num * 10 + *s - '0';
1517 ++s;
1518 }
1519
1520 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1521 {
1522 if (num < 16 || 31 < num)
1523 {
1524 error_message = _(": asr number must be between 16 and 31");
1525 goto error;
1526 }
1527 }
1528 else
1529 {
1530 if (num < 0 || 31 < num)
1531 {
1532 error_message = _(": asr number must be between 0 and 31");
1533 goto error;
1534 }
1535 }
1536
1537 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1538 continue;
1539 }
1540 else
1541 {
1542 error_message = _(": expecting %asrN");
1543 goto error;
1544 }
1545 } /* if %asr */
1546 break;
1547
1548 case 'I':
1549 the_insn.reloc = BFD_RELOC_SPARC_11;
1550 goto immediate;
1551
1552 case 'j':
1553 the_insn.reloc = BFD_RELOC_SPARC_10;
1554 goto immediate;
1555
1556 case 'X':
1557 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1558 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1559 the_insn.reloc = BFD_RELOC_SPARC_5;
1560 else
1561 the_insn.reloc = BFD_RELOC_SPARC13;
1562 /* These fields are unsigned, but for upward compatibility,
1563 allow negative values as well. */
1564 goto immediate;
1565
1566 case 'Y':
1567 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1568 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1569 the_insn.reloc = BFD_RELOC_SPARC_6;
1570 else
1571 the_insn.reloc = BFD_RELOC_SPARC13;
1572 /* These fields are unsigned, but for upward compatibility,
1573 allow negative values as well. */
1574 goto immediate;
1575
1576 case 'k':
1577 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1578 the_insn.pcrel = 1;
1579 goto immediate;
1580
1581 case 'G':
1582 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1583 the_insn.pcrel = 1;
1584 goto immediate;
1585
1586 case 'N':
1587 if (*s == 'p' && s[1] == 'n')
1588 {
1589 s += 2;
1590 continue;
1591 }
1592 break;
1593
1594 case 'T':
1595 if (*s == 'p' && s[1] == 't')
1596 {
1597 s += 2;
1598 continue;
1599 }
1600 break;
1601
1602 case 'z':
1603 if (*s == ' ')
1604 {
1605 ++s;
1606 }
1607 if (strncmp (s, "%icc", 4) == 0)
1608 {
1609 s += 4;
1610 continue;
1611 }
1612 break;
1613
1614 case 'Z':
1615 if (*s == ' ')
1616 {
1617 ++s;
1618 }
1619 if (strncmp (s, "%xcc", 4) == 0)
1620 {
1621 s += 4;
1622 continue;
1623 }
1624 break;
1625
1626 case '6':
1627 if (*s == ' ')
1628 {
1629 ++s;
1630 }
1631 if (strncmp (s, "%fcc0", 5) == 0)
1632 {
1633 s += 5;
1634 continue;
1635 }
1636 break;
1637
1638 case '7':
1639 if (*s == ' ')
1640 {
1641 ++s;
1642 }
1643 if (strncmp (s, "%fcc1", 5) == 0)
1644 {
1645 s += 5;
1646 continue;
1647 }
1648 break;
1649
1650 case '8':
1651 if (*s == ' ')
1652 {
1653 ++s;
1654 }
1655 if (strncmp (s, "%fcc2", 5) == 0)
1656 {
1657 s += 5;
1658 continue;
1659 }
1660 break;
1661
1662 case '9':
1663 if (*s == ' ')
1664 {
1665 ++s;
1666 }
1667 if (strncmp (s, "%fcc3", 5) == 0)
1668 {
1669 s += 5;
1670 continue;
1671 }
1672 break;
1673
1674 case 'P':
1675 if (strncmp (s, "%pc", 3) == 0)
1676 {
1677 s += 3;
1678 continue;
1679 }
1680 break;
1681
1682 case 'W':
1683 if (strncmp (s, "%tick", 5) == 0)
1684 {
1685 s += 5;
1686 continue;
1687 }
1688 break;
1689
1690 case '\0': /* end of args */
1691 if (*s == '\0')
1692 {
1693 match = 1;
1694 }
1695 break;
1696
1697 case '+':
1698 if (*s == '+')
1699 {
1700 ++s;
1701 continue;
1702 }
1703 if (*s == '-')
1704 {
1705 continue;
1706 }
1707 break;
1708
1709 case '[': /* these must match exactly */
1710 case ']':
1711 case ',':
1712 case ' ':
1713 if (*s++ == *args)
1714 continue;
1715 break;
1716
1717 case '#': /* must be at least one digit */
1718 if (isdigit ((unsigned char) *s++))
1719 {
1720 while (isdigit ((unsigned char) *s))
1721 {
1722 ++s;
1723 }
1724 continue;
1725 }
1726 break;
1727
1728 case 'C': /* coprocessor state register */
1729 if (strncmp (s, "%csr", 4) == 0)
1730 {
1731 s += 4;
1732 continue;
1733 }
1734 break;
1735
1736 case 'b': /* next operand is a coprocessor register */
1737 case 'c':
1738 case 'D':
1739 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1740 {
1741 mask = *s++;
1742 if (isdigit ((unsigned char) *s))
1743 {
1744 mask = 10 * (mask - '0') + (*s++ - '0');
1745 if (mask >= 32)
1746 {
1747 break;
1748 }
1749 }
1750 else
1751 {
1752 mask -= '0';
1753 }
1754 switch (*args)
1755 {
1756
1757 case 'b':
1758 opcode |= mask << 14;
1759 continue;
1760
1761 case 'c':
1762 opcode |= mask;
1763 continue;
1764
1765 case 'D':
1766 opcode |= mask << 25;
1767 continue;
1768 }
1769 }
1770 break;
1771
1772 case 'r': /* next operand must be a register */
1773 case 'O':
1774 case '1':
1775 case '2':
1776 case 'd':
1777 if (*s++ == '%')
1778 {
1779 switch (c = *s++)
1780 {
1781
1782 case 'f': /* frame pointer */
1783 if (*s++ == 'p')
1784 {
1785 mask = 0x1e;
1786 break;
1787 }
1788 goto error;
1789
1790 case 'g': /* global register */
a22b281c
RH		 1791 c = *s++;
1792 if (isoctal (c))
252b5132
RH		 1793 {
1794 mask = c - '0';
1795 break;
1796 }
1797 goto error;
1798
1799 case 'i': /* in register */
a22b281c
RH		 1800 c = *s++;
1801 if (isoctal (c))
252b5132
RH		 1802 {
1803 mask = c - '0' + 24;
1804 break;
1805 }
1806 goto error;
1807
1808 case 'l': /* local register */
a22b281c
RH		 1809 c = *s++;
1810 if (isoctal (c))
252b5132
RH		 1811 {
1812 mask = (c - '0' + 16);
1813 break;
1814 }
1815 goto error;
1816
1817 case 'o': /* out register */
a22b281c
RH		 1818 c = *s++;
1819 if (isoctal (c))
252b5132
RH		 1820 {
1821 mask = (c - '0' + 8);
1822 break;
1823 }
1824 goto error;
1825
1826 case 's': /* stack pointer */
1827 if (*s++ == 'p')
1828 {
1829 mask = 0xe;
1830 break;
1831 }
1832 goto error;
1833
1834 case 'r': /* any register */
1835 if (!isdigit ((unsigned char) (c = *s++)))
1836 {
1837 goto error;
1838 }
1839 /* FALLTHROUGH */
1840 case '0':
1841 case '1':
1842 case '2':
1843 case '3':
1844 case '4':
1845 case '5':
1846 case '6':
1847 case '7':
1848 case '8':
1849 case '9':
1850 if (isdigit ((unsigned char) *s))
1851 {
1852 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1853 {
1854 goto error;
1855 }
1856 }
1857 else
1858 {
1859 c -= '0';
1860 }
1861 mask = c;
1862 break;
1863
1864 default:
1865 goto error;
1866 }
1867
1868 /* Got the register, now figure out where
1869 it goes in the opcode. */
1870 switch (*args)
1871 {
1872 case '1':
1873 opcode |= mask << 14;
1874 continue;
1875
1876 case '2':
1877 opcode |= mask;
1878 continue;
1879
1880 case 'd':
1881 opcode |= mask << 25;
1882 continue;
1883
1884 case 'r':
1885 opcode |= (mask << 25) | (mask << 14);
1886 continue;
1887
1888 case 'O':
1889 opcode |= (mask << 25) | (mask << 0);
1890 continue;
1891 }
1892 }
1893 break;
1894
1895 case 'e': /* next operand is a floating point register */
1896 case 'v':
1897 case 'V':
1898
1899 case 'f':
1900 case 'B':
1901 case 'R':
1902
1903 case 'g':
1904 case 'H':
1905 case 'J':
1906 {
1907 char format;
1908
1909 if (*s++ == '%'
1910 && ((format = *s) == 'f')
1911 && isdigit ((unsigned char) *++s))
1912 {
1913 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1914 {
1915 mask = 10 * mask + (*s - '0');
1916 } /* read the number */
1917
1918 if ((*args == 'v'
1919 || *args == 'B'
1920 || *args == 'H')
1921 && (mask & 1))
1922 {
1923 break;
1924 } /* register must be even numbered */
1925
1926 if ((*args == 'V'
1927 || *args == 'R'
1928 || *args == 'J')
1929 && (mask & 3))
1930 {
1931 break;
1932 } /* register must be multiple of 4 */
1933
1934 if (mask >= 64)
1935 {
1936 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1937 error_message = _(": There are only 64 f registers; [0-63]");
1938 else
1939 error_message = _(": There are only 32 f registers; [0-31]");
1940 goto error;
1941 } /* on error */
1942 else if (mask >= 32)
1943 {
1944 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1945 {
1946 v9_arg_p = 1;
1947 mask -= 31; /* wrap high bit */
1948 }
1949 else
1950 {
1951 error_message = _(": There are only 32 f registers; [0-31]");
1952 goto error;
1953 }
1954 }
1955 }
1956 else
1957 {
1958 break;
1959 } /* if not an 'f' register. */
1960
1961 switch (*args)
1962 {
1963 case 'v':
1964 case 'V':
1965 case 'e':
1966 opcode |= RS1 (mask);
1967 continue;
1968
1969
1970 case 'f':
1971 case 'B':
1972 case 'R':
1973 opcode |= RS2 (mask);
1974 continue;
1975
1976 case 'g':
1977 case 'H':
1978 case 'J':
1979 opcode |= RD (mask);
1980 continue;
1981 } /* pack it in. */
1982
1983 know (0);
1984 break;
1985 } /* float arg */
1986
1987 case 'F':
1988 if (strncmp (s, "%fsr", 4) == 0)
1989 {
1990 s += 4;
1991 continue;
1992 }
1993 break;
1994
63fab58c 1995 case '0': /* 64 bit immediate (set, setsw, setx insn) */
252b5132
RH		 1996 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1997 goto immediate;
1998
252b5132
RH		 1999 case 'l': /* 22 bit PC relative immediate */
2000 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2001 the_insn.pcrel = 1;
2002 goto immediate;
2003
2004 case 'L': /* 30 bit immediate */
2005 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2006 the_insn.pcrel = 1;
2007 goto immediate;
2008
63fab58c 2009 case 'h':
252b5132
RH		 2010 case 'n': /* 22 bit immediate */
2011 the_insn.reloc = BFD_RELOC_SPARC22;
2012 goto immediate;
2013
2014 case 'i': /* 13 bit immediate */
2015 the_insn.reloc = BFD_RELOC_SPARC13;
2016
2017 /* fallthrough */
2018
2019 immediate:
2020 if (*s == ' ')
2021 s++;
2022
cf9a1301
RH		 2023 {
2024 char *s1;
2025 char *op_arg = NULL;
2026 expressionS op_exp;
2027 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2028
2029 /* Check for %hi, etc. */
2030 if (*s == '%')
2031 {
2032 static const struct ops {
2033 /* The name as it appears in assembler. */
2034 char *name;
2035 /* strlen (name), precomputed for speed */
2036 int len;
2037 /* The reloc this pseudo-op translates to. */
2038 int reloc;
2039 /* Non-zero if for v9 only. */
2040 int v9_p;
2041 /* Non-zero if can be used in pc-relative contexts. */
2042 int pcrel_p;/*FIXME:wip*/
2043 } ops[] = {
2044 /* hix/lox must appear before hi/lo so %hix won't be
2045 mistaken for %hi. */
2046 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2047 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2048 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2049 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2050 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2051 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2052 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2053 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2054 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2055 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2056 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2057 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2058 { NULL }
2059 };
2060 const struct ops *o;
2061
2062 for (o = ops; o->name; o++)
2063 if (strncmp (s + 1, o->name, o->len) == 0)
2064 break;
2065 if (o->name == NULL)
252b5132 2066 break;
cf9a1301
RH		 2067
2068 if (s[o->len + 1] != '(')
2069 {
2070 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2071 return special_case;
cf9a1301 2072 }
252b5132 2073
cf9a1301
RH		 2074 op_arg = o->name;
2075 the_insn.reloc = o->reloc;
2076 s += o->len + 2;
2077 v9_arg_p = o->v9_p;
2078 }
2079
2080 /* Note that if the get_expression() fails, we will still
2081 have created U entries in the symbol table for the
2082 'symbols' in the input string. Try not to create U
2083 symbols for registers, etc. */
252b5132 2084
252b5132
RH		 2085 /* This stuff checks to see if the expression ends in
2086 +%reg. If it does, it removes the register from
2087 the expression, and re-sets 's' to point to the
2088 right place. */
2089
cf9a1301
RH		 2090 if (op_arg)
2091 {
2092 int npar = 0;
2093
2094 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2095 if (*s1 == '(')
2096 npar++;
2097 else if (*s1 == ')')
2098 {
2099 if (!npar)
2100 break;
2101 npar--;
2102 }
2103
2104 if (*s1 != ')')
2105 {
2106 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2107 return special_case;
cf9a1301
RH		 2108 }
2109
2110 *s1 = '\0';
2111 (void) get_expression (s);
2112 *s1 = ')';
2113 s = s1 + 1;
2114 if (*s == ',' || *s == ']' || !*s)
2115 continue;
2116 if (*s != '+' && *s != '-')
2117 {
2118 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2119 return special_case;
cf9a1301
RH		 2120 }
2121 *s1 = '0';
2122 s = s1;
2123 op_exp = the_insn.exp;
2124 memset (&the_insn.exp, 0, sizeof(the_insn.exp));
2125 }
252b5132
RH		 2126
2127 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
2128
2129 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2130 {
2131 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2132 s1 -= 3;
2133 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2134 s1 -= 4;
2135 else
2136 s1 = NULL;
2137 if (s1)
252b5132 2138 {
252b5132
RH		 2139 *s1 = '\0';
2140 (void) get_expression (s);
2141 *s1 = '+';
cf9a1301
RH		 2142 if (op_arg)
2143 *s = ')';
252b5132 2144 s = s1;
252b5132 2145 }
cf9a1301
RH		 2146 }
2147 else
2148 s1 = NULL;
2149
2150 if (!s1)
2151 {
2152 (void) get_expression (s);
2153 if (op_arg)
2154 *s = ')';
2155 s = expr_end;
2156 }
2157
2158 if (op_arg)
2159 {
2160 the_insn.exp2 = the_insn.exp;
2161 the_insn.exp = op_exp;
2162 if (the_insn.exp2.X_op == O_absent)
2163 the_insn.exp2.X_op = O_illegal;
2164 else if (the_insn.exp.X_op == O_absent)
252b5132 2165 {
cf9a1301
RH		 2166 the_insn.exp = the_insn.exp2;
2167 the_insn.exp2.X_op = O_illegal;
2168 }
2169 else if (the_insn.exp.X_op == O_constant)
2170 {
2171 valueT val = the_insn.exp.X_add_number;
2172 switch (the_insn.reloc)
2173 {
1b50c718
ILT		 2174 default:
2175 break;
2176
cf9a1301
RH		 2177 case BFD_RELOC_SPARC_HH22:
2178 val = BSR (val, 32);
2179 /* intentional fallthrough */
2180
2181 case BFD_RELOC_SPARC_LM22:
2182 case BFD_RELOC_HI22:
2183 val = (val >> 10) & 0x3fffff;
2184 break;
2185
2186 case BFD_RELOC_SPARC_HM10:
2187 val = BSR (val, 32);
2188 /* intentional fallthrough */
2189
2190 case BFD_RELOC_LO10:
2191 val &= 0x3ff;
2192 break;
2193
2194 case BFD_RELOC_SPARC_H44:
2195 val >>= 22;
2196 val &= 0x3fffff;
2197 break;
2198
2199 case BFD_RELOC_SPARC_M44:
2200 val >>= 12;
2201 val &= 0x3ff;
2202 break;
2203
2204 case BFD_RELOC_SPARC_L44:
2205 val &= 0xfff;
2206 break;
2207
2208 case BFD_RELOC_SPARC_HIX22:
2209 val = ~ val;
2210 val = (val >> 10) & 0x3fffff;
2211 break;
2212
2213 case BFD_RELOC_SPARC_LOX10:
2214 val = (val & 0x3ff) | 0x1c00;
2215 break;
2216 }
2217 the_insn.exp = the_insn.exp2;
2218 the_insn.exp.X_add_number += val;
2219 the_insn.exp2.X_op = O_illegal;
2220 the_insn.reloc = old_reloc;
2221 }
2222 else if (the_insn.exp2.X_op != O_constant)
2223 {
2224 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2225 return special_case;
cf9a1301
RH		 2226 }
2227 else
2228 {
dabe3bbc 2229 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2230 || the_insn.reloc != BFD_RELOC_LO10
2231 || sparc_arch_size != 64
2232 || sparc_pic_code)
2233 {
2234 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2235 return special_case;
cf9a1301
RH		 2236 }
2237 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2238 }
2239 }
2240 }
252b5132
RH		 2241 /* Check for constants that don't require emitting a reloc. */
2242 if (the_insn.exp.X_op == O_constant
2243 && the_insn.exp.X_add_symbol == 0
2244 && the_insn.exp.X_op_symbol == 0)
2245 {
2246 /* For pc-relative call instructions, we reject
2247 constants to get better code. */
2248 if (the_insn.pcrel
2249 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2250 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2251 {
2252 error_message = _(": PC-relative operand can't be a constant");
2253 goto error;
2254 }
2255
2256 /* Constants that won't fit are checked in md_apply_fix3
2257 and bfd_install_relocation.
2258 ??? It would be preferable to install the constants
2259 into the insn here and save having to create a fixS
2260 for each one. There already exists code to handle
2261 all the various cases (e.g. in md_apply_fix3 and
2262 bfd_install_relocation) so duplicating all that code
2263 here isn't right. */
2264 }
2265
2266 continue;
2267
2268 case 'a':
2269 if (*s++ == 'a')
2270 {
2271 opcode |= ANNUL;
2272 continue;
2273 }
2274 break;
2275
2276 case 'A':
2277 {
2278 int asi = 0;
2279
2280 /* Parse an asi. */
2281 if (*s == '#')
2282 {
2283 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2284 {
2285 error_message = _(": invalid ASI name");
2286 goto error;
2287 }
2288 }
2289 else
2290 {
2291 if (! parse_const_expr_arg (&s, &asi))
2292 {
2293 error_message = _(": invalid ASI expression");
2294 goto error;
2295 }
2296 if (asi < 0 || asi > 255)
2297 {
2298 error_message = _(": invalid ASI number");
2299 goto error;
2300 }
2301 }
2302 opcode |= ASI (asi);
2303 continue;
2304 } /* alternate space */
2305
2306 case 'p':
2307 if (strncmp (s, "%psr", 4) == 0)
2308 {
2309 s += 4;
2310 continue;
2311 }
2312 break;
2313
2314 case 'q': /* floating point queue */
2315 if (strncmp (s, "%fq", 3) == 0)
2316 {
2317 s += 3;
2318 continue;
2319 }
2320 break;
2321
2322 case 'Q': /* coprocessor queue */
2323 if (strncmp (s, "%cq", 3) == 0)
2324 {
2325 s += 3;
2326 continue;
2327 }
2328 break;
2329
2330 case 'S':
2331 if (strcmp (str, "set") == 0
2332 || strcmp (str, "setuw") == 0)
2333 {
2334 special_case = SPECIAL_CASE_SET;
2335 continue;
2336 }
2337 else if (strcmp (str, "setsw") == 0)
2338 {
2339 special_case = SPECIAL_CASE_SETSW;
2340 continue;
2341 }
2342 else if (strcmp (str, "setx") == 0)
2343 {
2344 special_case = SPECIAL_CASE_SETX;
2345 continue;
2346 }
2347 else if (strncmp (str, "fdiv", 4) == 0)
2348 {
2349 special_case = SPECIAL_CASE_FDIV;
2350 continue;
2351 }
2352 break;
2353
2354 case 'o':
2355 if (strncmp (s, "%asi", 4) != 0)
2356 break;
2357 s += 4;
2358 continue;
2359
2360 case 's':
2361 if (strncmp (s, "%fprs", 5) != 0)
2362 break;
2363 s += 5;
2364 continue;
2365
2366 case 'E':
2367 if (strncmp (s, "%ccr", 4) != 0)
2368 break;
2369 s += 4;
2370 continue;
2371
2372 case 't':
2373 if (strncmp (s, "%tbr", 4) != 0)
2374 break;
2375 s += 4;
2376 continue;
2377
2378 case 'w':
2379 if (strncmp (s, "%wim", 4) != 0)
2380 break;
2381 s += 4;
2382 continue;
2383
2384 case 'x':
2385 {
2386 char *push = input_line_pointer;
2387 expressionS e;
2388
2389 input_line_pointer = s;
2390 expression (&e);
2391 if (e.X_op == O_constant)
2392 {
2393 int n = e.X_add_number;
2394 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2395 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2396 else
2397 opcode |= e.X_add_number << 5;
2398 }
2399 else
2400 as_bad (_("non-immediate OPF operand, ignored"));
2401 s = input_line_pointer;
2402 input_line_pointer = push;
2403 continue;
2404 }
2405
2406 case 'y':
2407 if (strncmp (s, "%y", 2) != 0)
2408 break;
2409 s += 2;
2410 continue;
2411
2412 case 'u':
2413 case 'U':
2414 {
2415 /* Parse a sparclet cpreg. */
2416 int cpreg;
2417 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2418 {
2419 error_message = _(": invalid cpreg name");
2420 goto error;
2421 }
2422 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2423 continue;
2424 }
2425
2426 default:
2427 as_fatal (_("failed sanity check."));
2428 } /* switch on arg code */
2429
2430 /* Break out of for() loop. */
2431 break;
2432 } /* for each arg that we expect */
2433
2434 error:
2435 if (match == 0)
2436 {
2437 /* Args don't match. */
2438 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2439 && (insn->name == insn[1].name
2440 || !strcmp (insn->name, insn[1].name)))
2441 {
2442 ++insn;
2443 s = argsStart;
2444 continue;
2445 }
2446 else
2447 {
2448 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2449 return special_case;
252b5132
RH		 2450 }
2451 }
2452 else
2453 {
2454 /* We have a match. Now see if the architecture is ok. */
2455 int needed_arch_mask = insn->architecture;
2456
2457 if (v9_arg_p)
2458 {
2459 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2460 | (1 << SPARC_OPCODE_ARCH_V9A));
2461 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2462 }
2463
2464 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2465 ; /* ok */
2466 /* Can we bump up the architecture? */
2467 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2468 {
2469 enum sparc_opcode_arch_val needed_architecture =
2470 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2471 & needed_arch_mask);
2472
2473 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2474 if (warn_on_bump
2475 && needed_architecture > warn_after_architecture)
2476 {
2477 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2478 sparc_opcode_archs[current_architecture].name,
2479 sparc_opcode_archs[needed_architecture].name,
2480 str);
2481 warn_after_architecture = needed_architecture;
2482 }
2483 current_architecture = needed_architecture;
2484 }
2485 /* Conflict. */
2486 /* ??? This seems to be a bit fragile. What if the next entry in
2487 the opcode table is the one we want and it is supported?
2488 It is possible to arrange the table today so that this can't
2489 happen but what about tomorrow? */
2490 else
2491 {
2492 int arch,printed_one_p = 0;
2493 char *p;
2494 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2495
2496 /* Create a list of the architectures that support the insn. */
2497 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2498 p = required_archs;
2499 arch = sparc_ffs (needed_arch_mask);
2500 while ((1 << arch) <= needed_arch_mask)
2501 {
2502 if ((1 << arch) & needed_arch_mask)
2503 {
2504 if (printed_one_p)
2505 *p++ = '|';
2506 strcpy (p, sparc_opcode_archs[arch].name);
2507 p += strlen (p);
2508 printed_one_p = 1;
2509 }
2510 ++arch;
2511 }
2512
2513 as_bad (_("Architecture mismatch on \"%s\"."), str);
2514 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2515 required_archs,
2516 sparc_opcode_archs[max_architecture].name);
a22b281c 2517 return special_case;
252b5132
RH		 2518 }
2519 } /* if no match */
2520
2521 break;
2522 } /* forever looking for a match */
2523
2524 the_insn.opcode = opcode;
a22b281c 2525 return special_case;
252b5132
RH		 2526}
2527
2528/* Parse an argument that can be expressed as a keyword.
2529 (eg: #StoreStore or %ccfr).
2530 The result is a boolean indicating success.
2531 If successful, INPUT_POINTER is updated. */
2532
2533static int
2534parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2535 int (*lookup_fn) PARAMS ((const char *));
2536 char **input_pointerP;
2537 int *valueP;
2538{
2539 int value;
2540 char c, *p, *q;
2541
2542 p = *input_pointerP;
2543 for (q = p + (*p == '#' || *p == '%');
2544 isalnum ((unsigned char) *q) || *q == '_';
2545 ++q)
2546 continue;
2547 c = *q;
2548 *q = 0;
2549 value = (*lookup_fn) (p);
2550 *q = c;
2551 if (value == -1)
2552 return 0;
2553 *valueP = value;
2554 *input_pointerP = q;
2555 return 1;
2556}
2557
2558/* Parse an argument that is a constant expression.
2559 The result is a boolean indicating success. */
2560
2561static int
2562parse_const_expr_arg (input_pointerP, valueP)
2563 char **input_pointerP;
2564 int *valueP;
2565{
2566 char *save = input_line_pointer;
2567 expressionS exp;
2568
2569 input_line_pointer = *input_pointerP;
2570 /* The next expression may be something other than a constant
2571 (say if we're not processing the right variant of the insn).
2572 Don't call expression unless we're sure it will succeed as it will
2573 signal an error (which we want to defer until later). */
2574 /* FIXME: It might be better to define md_operand and have it recognize
2575 things like %asi, etc. but continuing that route through to the end
2576 is a lot of work. */
2577 if (*input_line_pointer == '%')
2578 {
2579 input_line_pointer = save;
2580 return 0;
2581 }
2582 expression (&exp);
2583 *input_pointerP = input_line_pointer;
2584 input_line_pointer = save;
2585 if (exp.X_op != O_constant)
2586 return 0;
2587 *valueP = exp.X_add_number;
2588 return 1;
2589}
2590
2591/* Subroutine of sparc_ip to parse an expression. */
2592
2593static int
2594get_expression (str)
2595 char *str;
2596{
2597 char *save_in;
2598 segT seg;
2599
2600 save_in = input_line_pointer;
2601 input_line_pointer = str;
2602 seg = expression (&the_insn.exp);
2603 if (seg != absolute_section
2604 && seg != text_section
2605 && seg != data_section
2606 && seg != bss_section
2607 && seg != undefined_section)
2608 {
2609 the_insn.error = _("bad segment");
2610 expr_end = input_line_pointer;
2611 input_line_pointer = save_in;
2612 return 1;
2613 }
2614 expr_end = input_line_pointer;
2615 input_line_pointer = save_in;
2616 return 0;
2617}
2618
2619/* Subroutine of md_assemble to output one insn. */
2620
2621static void
2622output_insn (insn, the_insn)
2623 const struct sparc_opcode *insn;
2624 struct sparc_it *the_insn;
2625{
2626 char *toP = frag_more (4);
2627
2628 /* put out the opcode */
2629 if (INSN_BIG_ENDIAN)
2630 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2631 else
2632 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2633
2634 /* put out the symbol-dependent stuff */
2635 if (the_insn->reloc != BFD_RELOC_NONE)
2636 {
2637 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2638 (toP - frag_now->fr_literal), /* where */
2639 4, /* size */
2640 &the_insn->exp,
2641 the_insn->pcrel,
2642 the_insn->reloc);
2643 /* Turn off overflow checking in fixup_segment. We'll do our
2644 own overflow checking in md_apply_fix3. This is necessary because
2645 the insn size is 4 and fixup_segment will signal an overflow for
2646 large 8 byte quantities. */
2647 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2648 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2649 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2650 }
2651
2652 last_insn = insn;
2653 last_opcode = the_insn->opcode;
2654}
2655\f
2656/*
2657 This is identical to the md_atof in m68k.c. I think this is right,
2658 but I'm not sure.
2659
2660 Turn a string in input_line_pointer into a floating point constant of type
2661 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2662 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2663 */
2664
2665/* Equal to MAX_PRECISION in atof-ieee.c */
2666#define MAX_LITTLENUMS 6
2667
2668char *
2669md_atof (type, litP, sizeP)
2670 char type;
2671 char *litP;
2672 int *sizeP;
2673{
2674 int i,prec;
2675 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2676 char *t;
2677
2678 switch (type)
2679 {
2680 case 'f':
2681 case 'F':
2682 case 's':
2683 case 'S':
2684 prec = 2;
2685 break;
2686
2687 case 'd':
2688 case 'D':
2689 case 'r':
2690 case 'R':
2691 prec = 4;
2692 break;
2693
2694 case 'x':
2695 case 'X':
2696 prec = 6;
2697 break;
2698
2699 case 'p':
2700 case 'P':
2701 prec = 6;
2702 break;
2703
2704 default:
2705 *sizeP = 0;
2706 return _("Bad call to MD_ATOF()");
2707 }
2708
2709 t = atof_ieee (input_line_pointer, type, words);
2710 if (t)
2711 input_line_pointer = t;
2712 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2713
2714 if (target_big_endian)
2715 {
2716 for (i = 0; i < prec; i++)
2717 {
2718 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2719 litP += sizeof (LITTLENUM_TYPE);
2720 }
2721 }
2722 else
2723 {
2724 for (i = prec - 1; i >= 0; i--)
2725 {
2726 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2727 litP += sizeof (LITTLENUM_TYPE);
2728 }
2729 }
2730
2731 return 0;
2732}
2733
2734/* Write a value out to the object file, using the appropriate
2735 endianness. */
2736
2737void
2738md_number_to_chars (buf, val, n)
2739 char *buf;
2740 valueT val;
2741 int n;
2742{
2743 if (target_big_endian)
2744 number_to_chars_bigendian (buf, val, n);
2745 else if (target_little_endian_data
2746 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2747 /* Output debug words, which are not in allocated sections, as big endian */
2748 number_to_chars_bigendian (buf, val, n);
2749 else if (target_little_endian_data || ! target_big_endian)
2750 number_to_chars_littleendian (buf, val, n);
2751}
2752\f
2753/* Apply a fixS to the frags, now that we know the value it ought to
2754 hold. */
2755
2756int
2757md_apply_fix3 (fixP, value, segment)
2758 fixS *fixP;
2759 valueT *value;
2760 segT segment;
2761{
2762 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2763 offsetT val;
2764 long insn;
2765
2766 val = *value;
2767
2768 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2769
2770 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2771
2772#ifdef OBJ_ELF
2773 /* FIXME: SPARC ELF relocations don't use an addend in the data
2774 field itself. This whole approach should be somehow combined
2775 with the calls to bfd_install_relocation. Also, the value passed
2776 in by fixup_segment includes the value of a defined symbol. We
2777 don't want to include the value of an externally visible symbol. */
2778 if (fixP->fx_addsy != NULL)
2779 {
49309057 2780 if (symbol_used_in_reloc_p (fixP->fx_addsy)
252b5132
RH		 2781 && (S_IS_EXTERNAL (fixP->fx_addsy)
2782 || S_IS_WEAK (fixP->fx_addsy)
2783 || (sparc_pic_code && ! fixP->fx_pcrel)
2784 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2785 && ((bfd_get_section_flags (stdoutput,
2786 S_GET_SEGMENT (fixP->fx_addsy))
2787 & SEC_LINK_ONCE) != 0
2788 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2789 ".gnu.linkonce",
2790 sizeof ".gnu.linkonce" - 1) == 0)))
2791 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2792 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2793 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2794 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2795 return 1;
2796 }
2797#endif
2798
2799 /* This is a hack. There should be a better way to
2800 handle this. Probably in terms of howto fields, once
2801 we can look at these fixups in terms of howtos. */
2802 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2803 val += fixP->fx_where + fixP->fx_frag->fr_address;
2804
2805#ifdef OBJ_AOUT
2806 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2807 generate a reloc, then we just want to let the reloc addend set
2808 the value. We do not want to also stuff the addend into the
2809 object file. Including the addend in the object file works when
2810 doing a static link, because the linker will ignore the object
2811 file contents. However, the dynamic linker does not ignore the
2812 object file contents. */
2813 if (fixP->fx_addsy != NULL
2814 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2815 val = 0;
2816
2817 /* When generating PIC code, we do not want an addend for a reloc
2818 against a local symbol. We adjust fx_addnumber to cancel out the
2819 value already included in val, and to also cancel out the
2820 adjustment which bfd_install_relocation will create. */
2821 if (sparc_pic_code
2822 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2823 && fixP->fx_addsy != NULL
2824 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 2825 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2826 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2827
2828 /* When generating PIC code, we need to fiddle to get
2829 bfd_install_relocation to do the right thing for a PC relative
2830 reloc against a local symbol which we are going to keep. */
2831 if (sparc_pic_code
2832 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2833 && fixP->fx_addsy != NULL
2834 && (S_IS_EXTERNAL (fixP->fx_addsy)
2835 || S_IS_WEAK (fixP->fx_addsy))
2836 && S_IS_DEFINED (fixP->fx_addsy)
2837 && ! S_IS_COMMON (fixP->fx_addsy))
2838 {
2839 val = 0;
2840 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2841 }
2842#endif
2843
2844 /* If this is a data relocation, just output VAL. */
2845
2846 if (fixP->fx_r_type == BFD_RELOC_16)
2847 {
2848 md_number_to_chars (buf, val, 2);
2849 }
2850 else if (fixP->fx_r_type == BFD_RELOC_32
2851 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2852 {
2853 md_number_to_chars (buf, val, 4);
2854 }
2855 else if (fixP->fx_r_type == BFD_RELOC_64)
2856 {
2857 md_number_to_chars (buf, val, 8);
2858 }
2859 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2860 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2861 {
2862 fixP->fx_done = 0;
2863 return 1;
2864 }
2865 else
2866 {
2867 /* It's a relocation against an instruction. */
2868
2869 if (INSN_BIG_ENDIAN)
2870 insn = bfd_getb32 ((unsigned char *) buf);
2871 else
2872 insn = bfd_getl32 ((unsigned char *) buf);
2873
2874 switch (fixP->fx_r_type)
2875 {
2876 case BFD_RELOC_32_PCREL_S2:
2877 val = val >> 2;
2878 /* FIXME: This increment-by-one deserves a comment of why it's
2879 being done! */
2880 if (! sparc_pic_code
2881 || fixP->fx_addsy == NULL
49309057 2882 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2883 ++val;
2884 insn |= val & 0x3fffffff;
2885 break;
2886
2887 case BFD_RELOC_SPARC_11:
2888 if (! in_signed_range (val, 0x7ff))
2889 as_bad_where (fixP->fx_file, fixP->fx_line,
2890 _("relocation overflow"));
2891 insn |= val & 0x7ff;
2892 break;
2893
2894 case BFD_RELOC_SPARC_10:
2895 if (! in_signed_range (val, 0x3ff))
2896 as_bad_where (fixP->fx_file, fixP->fx_line,
2897 _("relocation overflow"));
2898 insn |= val & 0x3ff;
2899 break;
2900
2901 case BFD_RELOC_SPARC_7:
2902 if (! in_bitfield_range (val, 0x7f))
2903 as_bad_where (fixP->fx_file, fixP->fx_line,
2904 _("relocation overflow"));
2905 insn |= val & 0x7f;
2906 break;
2907
2908 case BFD_RELOC_SPARC_6:
2909 if (! in_bitfield_range (val, 0x3f))
2910 as_bad_where (fixP->fx_file, fixP->fx_line,
2911 _("relocation overflow"));
2912 insn |= val & 0x3f;
2913 break;
2914
2915 case BFD_RELOC_SPARC_5:
2916 if (! in_bitfield_range (val, 0x1f))
2917 as_bad_where (fixP->fx_file, fixP->fx_line,
2918 _("relocation overflow"));
2919 insn |= val & 0x1f;
2920 break;
2921
2922 case BFD_RELOC_SPARC_WDISP16:
2923 /* FIXME: simplify */
2924 if (((val > 0) && (val & ~0x3fffc))
2925 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2926 as_bad_where (fixP->fx_file, fixP->fx_line,
2927 _("relocation overflow"));
2928 /* FIXME: The +1 deserves a comment. */
2929 val = (val >> 2) + 1;
2930 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2931 break;
2932
2933 case BFD_RELOC_SPARC_WDISP19:
2934 /* FIXME: simplify */
2935 if (((val > 0) && (val & ~0x1ffffc))
2936 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2937 as_bad_where (fixP->fx_file, fixP->fx_line,
2938 _("relocation overflow"));
2939 /* FIXME: The +1 deserves a comment. */
2940 val = (val >> 2) + 1;
2941 insn |= val & 0x7ffff;
2942 break;
2943
2944 case BFD_RELOC_SPARC_HH22:
2945 val = BSR (val, 32);
2946 /* intentional fallthrough */
2947
2948 case BFD_RELOC_SPARC_LM22:
2949 case BFD_RELOC_HI22:
2950 if (!fixP->fx_addsy)
2951 {
2952 insn |= (val >> 10) & 0x3fffff;
2953 }
2954 else
2955 {
2956 /* FIXME: Need comment explaining why we do this. */
2957 insn &= ~0xffff;
2958 }
2959 break;
2960
2961 case BFD_RELOC_SPARC22:
2962 if (val & ~0x003fffff)
2963 as_bad_where (fixP->fx_file, fixP->fx_line,
2964 _("relocation overflow"));
2965 insn |= (val & 0x3fffff);
2966 break;
2967
2968 case BFD_RELOC_SPARC_HM10:
2969 val = BSR (val, 32);
2970 /* intentional fallthrough */
2971
2972 case BFD_RELOC_LO10:
2973 if (!fixP->fx_addsy)
2974 {
2975 insn |= val & 0x3ff;
2976 }
2977 else
2978 {
2979 /* FIXME: Need comment explaining why we do this. */
2980 insn &= ~0xff;
2981 }
2982 break;
2983
dabe3bbc
RH		 2984 case BFD_RELOC_SPARC_OLO10:
2985 val &= 0x3ff;
2986 val += fixP->tc_fix_data;
2987 /* intentional fallthrough */
2988
252b5132
RH		 2989 case BFD_RELOC_SPARC13:
2990 if (! in_signed_range (val, 0x1fff))
2991 as_bad_where (fixP->fx_file, fixP->fx_line,
2992 _("relocation overflow"));
2993 insn |= val & 0x1fff;
2994 break;
2995
2996 case BFD_RELOC_SPARC_WDISP22:
2997 val = (val >> 2) + 1;
2998 /* FALLTHROUGH */
2999 case BFD_RELOC_SPARC_BASE22:
3000 insn |= val & 0x3fffff;
3001 break;
3002
3003 case BFD_RELOC_SPARC_H44:
3004 if (!fixP->fx_addsy)
3005 {
3006 bfd_vma tval = val;
3007 tval >>= 22;
3008 insn |= tval & 0x3fffff;
3009 }
3010 break;
3011
3012 case BFD_RELOC_SPARC_M44:
3013 if (!fixP->fx_addsy)
3014 insn |= (val >> 12) & 0x3ff;
3015 break;
3016
3017 case BFD_RELOC_SPARC_L44:
3018 if (!fixP->fx_addsy)
3019 insn |= val & 0xfff;
3020 break;
3021
3022 case BFD_RELOC_SPARC_HIX22:
3023 if (!fixP->fx_addsy)
3024 {
3025 val ^= ~ (offsetT) 0;
3026 insn |= (val >> 10) & 0x3fffff;
3027 }
3028 break;
3029
3030 case BFD_RELOC_SPARC_LOX10:
3031 if (!fixP->fx_addsy)
3032 insn |= 0x1c00 | (val & 0x3ff);
3033 break;
3034
3035 case BFD_RELOC_NONE:
3036 default:
3037 as_bad_where (fixP->fx_file, fixP->fx_line,
3038 _("bad or unhandled relocation type: 0x%02x"),
3039 fixP->fx_r_type);
3040 break;
3041 }
3042
3043 if (INSN_BIG_ENDIAN)
3044 bfd_putb32 (insn, (unsigned char *) buf);
3045 else
3046 bfd_putl32 (insn, (unsigned char *) buf);
3047 }
3048
3049 /* Are we finished with this relocation now? */
3050 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3051 fixP->fx_done = 1;
3052
3053 return 1;
3054}
3055
3056/* Translate internal representation of relocation info to BFD target
3057 format. */
dabe3bbc 3058arelent **
252b5132
RH		 3059tc_gen_reloc (section, fixp)
3060 asection *section;
3061 fixS *fixp;
3062{
dabe3bbc 3063 static arelent *relocs[3];
252b5132
RH		 3064 arelent *reloc;
3065 bfd_reloc_code_real_type code;
3066
dabe3bbc
RH		 3067 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3068 relocs[1] = NULL;
252b5132 3069
49309057
ILT		 3070 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3071 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3072 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3073
3074 switch (fixp->fx_r_type)
3075 {
3076 case BFD_RELOC_16:
3077 case BFD_RELOC_32:
3078 case BFD_RELOC_HI22:
3079 case BFD_RELOC_LO10:
3080 case BFD_RELOC_32_PCREL_S2:
3081 case BFD_RELOC_SPARC13:
63fab58c 3082 case BFD_RELOC_SPARC22:
252b5132
RH		 3083 case BFD_RELOC_SPARC_BASE13:
3084 case BFD_RELOC_SPARC_WDISP16:
3085 case BFD_RELOC_SPARC_WDISP19:
3086 case BFD_RELOC_SPARC_WDISP22:
3087 case BFD_RELOC_64:
3088 case BFD_RELOC_SPARC_5:
3089 case BFD_RELOC_SPARC_6:
3090 case BFD_RELOC_SPARC_7:
3091 case BFD_RELOC_SPARC_10:
3092 case BFD_RELOC_SPARC_11:
3093 case BFD_RELOC_SPARC_HH22:
3094 case BFD_RELOC_SPARC_HM10:
3095 case BFD_RELOC_SPARC_LM22:
3096 case BFD_RELOC_SPARC_PC_HH22:
3097 case BFD_RELOC_SPARC_PC_HM10:
3098 case BFD_RELOC_SPARC_PC_LM22:
3099 case BFD_RELOC_SPARC_H44:
3100 case BFD_RELOC_SPARC_M44:
3101 case BFD_RELOC_SPARC_L44:
3102 case BFD_RELOC_SPARC_HIX22:
3103 case BFD_RELOC_SPARC_LOX10:
3104 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3105 case BFD_RELOC_SPARC_OLO10:
252b5132
RH		 3106 case BFD_RELOC_VTABLE_ENTRY:
3107 case BFD_RELOC_VTABLE_INHERIT:
3108 code = fixp->fx_r_type;
3109 break;
3110 default:
3111 abort ();
3112 return NULL;
3113 }
3114
3115#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3116 /* If we are generating PIC code, we need to generate a different
3117 set of relocs. */
3118
3119#ifdef OBJ_ELF
3120#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3121#else
3122#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3123#endif
3124
3125 if (sparc_pic_code)
3126 {
3127 switch (code)
3128 {
3129 case BFD_RELOC_32_PCREL_S2:
3130 if (! S_IS_DEFINED (fixp->fx_addsy)
3131 || S_IS_COMMON (fixp->fx_addsy)
3132 || S_IS_EXTERNAL (fixp->fx_addsy)
3133 || S_IS_WEAK (fixp->fx_addsy))
3134 code = BFD_RELOC_SPARC_WPLT30;
3135 break;
3136 case BFD_RELOC_HI22:
3137 if (fixp->fx_addsy != NULL
3138 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3139 code = BFD_RELOC_SPARC_PC22;
3140 else
3141 code = BFD_RELOC_SPARC_GOT22;
3142 break;
3143 case BFD_RELOC_LO10:
3144 if (fixp->fx_addsy != NULL
3145 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3146 code = BFD_RELOC_SPARC_PC10;
3147 else
3148 code = BFD_RELOC_SPARC_GOT10;
3149 break;
3150 case BFD_RELOC_SPARC13:
3151 code = BFD_RELOC_SPARC_GOT13;
3152 break;
3153 default:
3154 break;
3155 }
3156 }
3157#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3158
dabe3bbc
RH		 3159 if (code == BFD_RELOC_SPARC_OLO10)
3160 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3161 else
3162 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3163 if (reloc->howto == 0)
3164 {
3165 as_bad_where (fixp->fx_file, fixp->fx_line,
3166 _("internal error: can't export reloc type %d (`%s')"),
3167 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3168 xfree (reloc);
3169 relocs[0] = NULL;
3170 return relocs;
252b5132
RH		 3171 }
3172
3173 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3174#ifdef OBJ_AOUT
3175
3176 if (reloc->howto->pc_relative == 0
3177 || code == BFD_RELOC_SPARC_PC10
3178 || code == BFD_RELOC_SPARC_PC22)
3179 reloc->addend = fixp->fx_addnumber;
3180 else if (sparc_pic_code
3181 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3182 && fixp->fx_addsy != NULL
3183 && (S_IS_EXTERNAL (fixp->fx_addsy)
3184 || S_IS_WEAK (fixp->fx_addsy))
3185 && S_IS_DEFINED (fixp->fx_addsy)
3186 && ! S_IS_COMMON (fixp->fx_addsy))
3187 reloc->addend = fixp->fx_addnumber;
3188 else
3189 reloc->addend = fixp->fx_offset - reloc->address;
3190
3191#else /* elf or coff */
3192
3193 if (reloc->howto->pc_relative == 0
3194 || code == BFD_RELOC_SPARC_PC10
3195 || code == BFD_RELOC_SPARC_PC22)
3196 reloc->addend = fixp->fx_addnumber;
49309057 3197 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3198 reloc->addend = (section->vma
3199 + fixp->fx_addnumber
3200 + md_pcrel_from (fixp));
3201 else
3202 reloc->addend = fixp->fx_offset;
3203#endif
3204
dabe3bbc
RH		 3205 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3206 on the same location. */
3207 if (code == BFD_RELOC_SPARC_OLO10)
3208 {
3209 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3210 relocs[2] = NULL;
3211
3212 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3213 *reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section));
3214 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3215 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3216 reloc->addend = fixp->tc_fix_data;
3217 }
3218
3219 return relocs;
252b5132
RH		 3220}
3221\f
3222/* We have no need to default values of symbols. */
3223
3224/* ARGSUSED */
3225symbolS *
3226md_undefined_symbol (name)
3227 char *name;
3228{
3229 return 0;
3230} /* md_undefined_symbol() */
3231
3232/* Round up a section size to the appropriate boundary. */
3233valueT
3234md_section_align (segment, size)
3235 segT segment;
3236 valueT size;
3237{
3238#ifndef OBJ_ELF
3239 /* This is not right for ELF; a.out wants it, and COFF will force
3240 the alignment anyways. */
3241 valueT align = ((valueT) 1
3242 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3243 valueT newsize;
3244 /* turn alignment value into a mask */
3245 align--;
3246 newsize = (size + align) & ~align;
3247 return newsize;
3248#else
3249 return size;
3250#endif
3251}
3252
3253/* Exactly what point is a PC-relative offset relative TO?
3254 On the sparc, they're relative to the address of the offset, plus
3255 its size. This gets us to the following instruction.
3256 (??? Is this right? FIXME-SOON) */
3257long
3258md_pcrel_from (fixP)
3259 fixS *fixP;
3260{
3261 long ret;
3262
3263 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3264 if (! sparc_pic_code
3265 || fixP->fx_addsy == NULL
49309057 3266 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3267 ret += fixP->fx_size;
3268 return ret;
3269}
3270\f
3271/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3272 of two. */
3273
3274static int
3275log2 (value)
3276 int value;
3277{
3278 int shift;
3279
3280 if (value <= 0)
3281 return -1;
3282
3283 for (shift = 0; (value & 1) == 0; value >>= 1)
3284 ++shift;
3285
3286 return (value == 1) ? shift : -1;
3287}
3288
3289/*
3290 * sort of like s_lcomm
3291 */
3292
3293#ifndef OBJ_ELF
3294static int max_alignment = 15;
3295#endif
3296
3297static void
3298s_reserve (ignore)
3299 int ignore;
3300{
3301 char *name;
3302 char *p;
3303 char c;
3304 int align;
3305 int size;
3306 int temp;
3307 symbolS *symbolP;
3308
3309 name = input_line_pointer;
3310 c = get_symbol_end ();
3311 p = input_line_pointer;
3312 *p = c;
3313 SKIP_WHITESPACE ();
3314
3315 if (*input_line_pointer != ',')
3316 {
3317 as_bad (_("Expected comma after name"));
3318 ignore_rest_of_line ();
3319 return;
3320 }
3321
3322 ++input_line_pointer;
3323
3324 if ((size = get_absolute_expression ()) < 0)
3325 {
3326 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3327 ignore_rest_of_line ();
3328 return;
3329 } /* bad length */
3330
3331 *p = 0;
3332 symbolP = symbol_find_or_make (name);
3333 *p = c;
3334
3335 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3336 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3337 {
3338 as_bad (_("bad .reserve segment -- expected BSS segment"));
3339 return;
3340 }
3341
3342 if (input_line_pointer[2] == '.')
3343 input_line_pointer += 7;
3344 else
3345 input_line_pointer += 6;
3346 SKIP_WHITESPACE ();
3347
3348 if (*input_line_pointer == ',')
3349 {
3350 ++input_line_pointer;
3351
3352 SKIP_WHITESPACE ();
3353 if (*input_line_pointer == '\n')
3354 {
3355 as_bad (_("missing alignment"));
3356 ignore_rest_of_line ();
3357 return;
3358 }
3359
3360 align = (int) get_absolute_expression ();
3361
3362#ifndef OBJ_ELF
3363 if (align > max_alignment)
3364 {
3365 align = max_alignment;
3366 as_warn (_("alignment too large; assuming %d"), align);
3367 }
3368#endif
3369
3370 if (align < 0)
3371 {
3372 as_bad (_("negative alignment"));
3373 ignore_rest_of_line ();
3374 return;
3375 }
3376
3377 if (align != 0)
3378 {
3379 temp = log2 (align);
3380 if (temp < 0)
3381 {
3382 as_bad (_("alignment not a power of 2"));
3383 ignore_rest_of_line ();
3384 return;
3385 }
3386
3387 align = temp;
3388 }
3389
3390 record_alignment (bss_section, align);
3391 }
3392 else
3393 align = 0;
3394
3395 if (!S_IS_DEFINED (symbolP)
3396#ifdef OBJ_AOUT
3397 && S_GET_OTHER (symbolP) == 0
3398 && S_GET_DESC (symbolP) == 0
3399#endif
3400 )
3401 {
3402 if (! need_pass_2)
3403 {
3404 char *pfrag;
3405 segT current_seg = now_seg;
3406 subsegT current_subseg = now_subseg;
3407
3408 subseg_set (bss_section, 1); /* switch to bss */
3409
3410 if (align)
3411 frag_align (align, 0, 0); /* do alignment */
3412
3413 /* detach from old frag */
3414 if (S_GET_SEGMENT(symbolP) == bss_section)
49309057 3415 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3416
49309057 3417 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3418 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3419 (offsetT) size, (char *)0);
3420 *pfrag = 0;
3421
3422 S_SET_SEGMENT (symbolP, bss_section);
3423
3424 subseg_set (current_seg, current_subseg);
3425
3426#ifdef OBJ_ELF
3427 S_SET_SIZE (symbolP, size);
3428#endif
3429 }
3430 }
3431 else
3432 {
3433 as_warn("Ignoring attempt to re-define symbol %s",
3434 S_GET_NAME (symbolP));
3435 } /* if not redefining */
3436
3437 demand_empty_rest_of_line ();
3438}
3439
3440static void
3441s_common (ignore)
3442 int ignore;
3443{
3444 char *name;
3445 char c;
3446 char *p;
3447 int temp, size;
3448 symbolS *symbolP;
3449
3450 name = input_line_pointer;
3451 c = get_symbol_end ();
3452 /* just after name is now '\0' */
3453 p = input_line_pointer;
3454 *p = c;
3455 SKIP_WHITESPACE ();
3456 if (*input_line_pointer != ',')
3457 {
3458 as_bad (_("Expected comma after symbol-name"));
3459 ignore_rest_of_line ();
3460 return;
3461 }
3462 input_line_pointer++; /* skip ',' */
3463 if ((temp = get_absolute_expression ()) < 0)
3464 {
3465 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3466 ignore_rest_of_line ();
3467 return;
3468 }
3469 size = temp;
3470 *p = 0;
3471 symbolP = symbol_find_or_make (name);
3472 *p = c;
3473 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3474 {
3475 as_bad (_("Ignoring attempt to re-define symbol"));
3476 ignore_rest_of_line ();
3477 return;
3478 }
3479 if (S_GET_VALUE (symbolP) != 0)
3480 {
3481 if (S_GET_VALUE (symbolP) != (valueT) size)
3482 {
3483 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3484 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3485 }
3486 }
3487 else
3488 {
3489#ifndef OBJ_ELF
3490 S_SET_VALUE (symbolP, (valueT) size);
3491 S_SET_EXTERNAL (symbolP);
3492#endif
3493 }
7dcc9865 3494 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3495 if (*input_line_pointer != ',')
3496 {
3497 as_bad (_("Expected comma after common length"));
3498 ignore_rest_of_line ();
3499 return;
3500 }
3501 input_line_pointer++;
3502 SKIP_WHITESPACE ();
3503 if (*input_line_pointer != '"')
3504 {
3505 temp = get_absolute_expression ();
3506
3507#ifndef OBJ_ELF
3508 if (temp > max_alignment)
3509 {
3510 temp = max_alignment;
3511 as_warn (_("alignment too large; assuming %d"), temp);
3512 }
3513#endif
3514
3515 if (temp < 0)
3516 {
3517 as_bad (_("negative alignment"));
3518 ignore_rest_of_line ();
3519 return;
3520 }
3521
3522#ifdef OBJ_ELF
49309057 3523 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3524 {
3525 segT old_sec;
3526 int old_subsec;
3527 char *p;
3528 int align;
3529
3530 old_sec = now_seg;
3531 old_subsec = now_subseg;
3532
3533 if (temp == 0)
3534 align = 0;
3535 else
3536 align = log2 (temp);
3537
3538 if (align < 0)
3539 {
3540 as_bad (_("alignment not a power of 2"));
3541 ignore_rest_of_line ();
3542 return;
3543 }
3544
3545 record_alignment (bss_section, align);
3546 subseg_set (bss_section, 0);
3547 if (align)
3548 frag_align (align, 0, 0);
3549 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3550 symbol_get_frag (symbolP)->fr_symbol = 0;
3551 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3552 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3553 (offsetT) size, (char *) 0);
3554 *p = 0;
3555 S_SET_SEGMENT (symbolP, bss_section);
3556 S_CLEAR_EXTERNAL (symbolP);
3557 S_SET_SIZE (symbolP, size);
3558 subseg_set (old_sec, old_subsec);
3559 }
3560 else
3561#endif /* OBJ_ELF */
3562 {
3563 allocate_common:
3564 S_SET_VALUE (symbolP, (valueT) size);
3565#ifdef OBJ_ELF
3566 S_SET_ALIGN (symbolP, temp);
3567 S_SET_SIZE (symbolP, size);
3568#endif
3569 S_SET_EXTERNAL (symbolP);
3570 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3571 }
3572 }
3573 else
3574 {
3575 input_line_pointer++;
3576 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3577 if (*input_line_pointer == '.')
3578 input_line_pointer++;
3579 /* @@ Some say data, some say bss. */
3580 if (strncmp (input_line_pointer, "bss\"", 4)
3581 && strncmp (input_line_pointer, "data\"", 5))
3582 {
3583 while (*--input_line_pointer != '"')
3584 ;
3585 input_line_pointer--;
3586 goto bad_common_segment;
3587 }
3588 while (*input_line_pointer++ != '"')
3589 ;
3590 goto allocate_common;
3591 }
3592
3593#ifdef BFD_ASSEMBLER
49309057 3594 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3595#endif
3596
3597 demand_empty_rest_of_line ();
3598 return;
3599
3600 {
3601 bad_common_segment:
3602 p = input_line_pointer;
3603 while (*p && *p != '\n')
3604 p++;
3605 c = *p;
3606 *p = '\0';
3607 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3608 *p = c;
3609 input_line_pointer = p;
3610 ignore_rest_of_line ();
3611 return;
3612 }
3613}
3614
3615/* Handle the .empty pseudo-op. This supresses the warnings about
3616 invalid delay slot usage. */
3617
3618static void
3619s_empty (ignore)
3620 int ignore;
3621{
3622 /* The easy way to implement is to just forget about the last
3623 instruction. */
3624 last_insn = NULL;
3625}
3626
3627static void
3628s_seg (ignore)
3629 int ignore;
3630{
3631
3632 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3633 {
3634 input_line_pointer += 6;
3635 s_text (0);
3636 return;
3637 }
3638 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3639 {
3640 input_line_pointer += 6;
3641 s_data (0);
3642 return;
3643 }
3644 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3645 {
3646 input_line_pointer += 7;
3647 s_data1 ();
3648 return;
3649 }
3650 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3651 {
3652 input_line_pointer += 5;
3653 /* We only support 2 segments -- text and data -- for now, so
3654 things in the "bss segment" will have to go into data for now.
3655 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3656 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3657 return;
3658 }
3659 as_bad (_("Unknown segment type"));
3660 demand_empty_rest_of_line ();
3661}
3662
3663static void
3664s_data1 ()
3665{
3666 subseg_set (data_section, 1);
3667 demand_empty_rest_of_line ();
3668}
3669
3670static void
3671s_proc (ignore)
3672 int ignore;
3673{
3674 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3675 {
3676 ++input_line_pointer;
3677 }
3678 ++input_line_pointer;
3679}
3680
3681/* This static variable is set by s_uacons to tell sparc_cons_align
3682 that the expession does not need to be aligned. */
3683
3684static int sparc_no_align_cons = 0;
3685
3686/* This handles the unaligned space allocation pseudo-ops, such as
3687 .uaword. .uaword is just like .word, but the value does not need
3688 to be aligned. */
3689
3690static void
3691s_uacons (bytes)
3692 int bytes;
3693{
3694 /* Tell sparc_cons_align not to align this value. */
3695 sparc_no_align_cons = 1;
3696 cons (bytes);
3697}
3698
cf9a1301
RH		 3699/* This handles the native word allocation pseudo-op .nword.
3700 For sparc_arch_size 32 it is equivalent to .word, for
3701 sparc_arch_size 64 it is equivalent to .xword. */
3702
3703static void
3704s_ncons (bytes)
3705 int bytes;
3706{
3707 cons (sparc_arch_size == 32 ? 4 : 8);
3708}
3709
252b5132
RH		 3710/* If the --enforce-aligned-data option is used, we require .word,
3711 et. al., to be aligned correctly. We do it by setting up an
3712 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3713 no unexpected alignment was introduced.
3714
3715 The SunOS and Solaris native assemblers enforce aligned data by
3716 default. We don't want to do that, because gcc can deliberately
3717 generate misaligned data if the packed attribute is used. Instead,
3718 we permit misaligned data by default, and permit the user to set an
3719 option to check for it. */
3720
3721void
3722sparc_cons_align (nbytes)
3723 int nbytes;
3724{
3725 int nalign;
3726 char *p;
3727
3728 /* Only do this if we are enforcing aligned data. */
3729 if (! enforce_aligned_data)
3730 return;
3731
3732 if (sparc_no_align_cons)
3733 {
3734 /* This is an unaligned pseudo-op. */
3735 sparc_no_align_cons = 0;
3736 return;
3737 }
3738
3739 nalign = log2 (nbytes);
3740 if (nalign == 0)
3741 return;
3742
3743 assert (nalign > 0);
3744
3745 if (now_seg == absolute_section)
3746 {
3747 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3748 as_bad (_("misaligned data"));
3749 return;
3750 }
3751
3752 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3753 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3754
3755 record_alignment (now_seg, nalign);
3756}
3757
3758/* This is where we do the unexpected alignment check.
3759 This is called from HANDLE_ALIGN in tc-sparc.h. */
3760
3761void
3762sparc_handle_align (fragp)
3763 fragS *fragp;
3764{
3765 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
3766 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
3767 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
3768 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3769 {
3770 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3771
3772 if (count >= 4
3773 && !(count & 3)
3774 && count <= 1024
3775 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
3776 {
3777 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3778 int i;
3779
3780 for (i = 0; i < count; i += 4, p++)
3781 if (INSN_BIG_ENDIAN)
3782 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3783 else
3784 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3785
3786 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
3787 {
3788 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3789 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3790 if (INSN_BIG_ENDIAN)
3791 number_to_chars_bigendian (waddr, wval, 4);
3792 else
3793 number_to_chars_littleendian (waddr, wval, 4);
3794 }
3795 fragp->fr_var = count;
3796 }
3797 }
3798}
3799
3800#ifdef OBJ_ELF
3801/* Some special processing for a Sparc ELF file. */
3802
3803void
3804sparc_elf_final_processing ()
3805{
3806 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3807 sort of BFD interface for this. */
3808 if (sparc_arch_size == 64)
3809 {
3810 switch (sparc_memory_model)
3811 {
3812 case MM_RMO:
3813 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3814 break;
3815 case MM_PSO:
3816 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3817 break;
3818 default:
3819 break;
3820 }
3821 }
3822 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3823 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3824 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3825 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3826}
3827#endif
3828
3829/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3830 reloc for a cons. We could use the definition there, except that
3831 we want to handle little endian relocs specially. */
3832
3833void
3834cons_fix_new_sparc (frag, where, nbytes, exp)
3835 fragS *frag;
3836 int where;
3837 unsigned int nbytes;
3838 expressionS *exp;
3839{
3840 bfd_reloc_code_real_type r;
3841
3842 r = (nbytes == 1 ? BFD_RELOC_8 :
3843 (nbytes == 2 ? BFD_RELOC_16 :
3844 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
3845
3846 if (target_little_endian_data && nbytes == 4
3847 && now_seg->flags & SEC_ALLOC)
3848 r = BFD_RELOC_SPARC_REV32;
3849 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
3850}
3851
3852#ifdef OBJ_ELF
3853int
3854elf32_sparc_force_relocation (fixp)
3855 struct fix *fixp;
3856{
3857 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3858 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3859 return 1;
3860
3861 return 0;
3862}
3863#endif
3864
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