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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
f7e42eb4 | 2 | Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
9e8c70f9 DM |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
4 | 2011 | |
e0c6ed95 | 5 | Free Software Foundation, Inc. |
252b5132 RH |
6 | This file is part of GAS, the GNU Assembler. |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public | |
19 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
20 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
252b5132 RH |
25 | #include "subsegs.h" |
26 | ||
27 | #include "opcode/sparc.h" | |
364b6d8b | 28 | #include "dw2gencfi.h" |
252b5132 RH |
29 | |
30 | #ifdef OBJ_ELF | |
31 | #include "elf/sparc.h" | |
732d96b6 | 32 | #include "dwarf2dbg.h" |
252b5132 RH |
33 | #endif |
34 | ||
6c1b24e4 AO |
35 | /* Some ancient Sun C compilers would not take such hex constants as |
36 | unsigned, and would end up sign-extending them to form an offsetT, | |
37 | so use these constants instead. */ | |
38 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
39 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
40 | ||
5a49b8ac AM |
41 | static int sparc_ip (char *, const struct sparc_opcode **); |
42 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
43 | static int parse_const_expr_arg (char **, int *); | |
44 | static int get_expression (char *); | |
252b5132 RH |
45 | |
46 | /* Default architecture. */ | |
47 | /* ??? The default value should be V8, but sparclite support was added | |
48 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
49 | the future we can set this to V8. */ | |
50 | #ifndef DEFAULT_ARCH | |
51 | #define DEFAULT_ARCH "sparclite" | |
52 | #endif | |
53 | static char *default_arch = DEFAULT_ARCH; | |
54 | ||
55 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
56 | have been set. */ | |
57 | static int default_init_p; | |
58 | ||
59 | /* Current architecture. We don't bump up unless necessary. */ | |
60 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
61 | ||
62 | /* The maximum architecture level we can bump up to. | |
63 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
64 | The native assembler works this way. The user is required to pass | |
65 | an explicit argument before we'll create v9 object files. However, if | |
66 | we don't see any v9 insns, a v8plus object file is not created. */ | |
67 | static enum sparc_opcode_arch_val max_architecture; | |
68 | ||
69 | /* Either 32 or 64, selects file format. */ | |
70 | static int sparc_arch_size; | |
71 | /* Initial (default) value, recorded separately in case a user option | |
72 | changes the value before md_show_usage is called. */ | |
73 | static int default_arch_size; | |
74 | ||
75 | #ifdef OBJ_ELF | |
76 | /* The currently selected v9 memory model. Currently only used for | |
77 | ELF. */ | |
78 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
79 | |
80 | #ifndef TE_SOLARIS | |
81 | /* Bitmask of instruction types seen so far, used to populate the | |
82 | GNU attributes section with hwcap information. */ | |
83 | static int hwcap_seen; | |
84 | #endif | |
252b5132 RH |
85 | #endif |
86 | ||
87 | static int architecture_requested; | |
88 | static int warn_on_bump; | |
89 | ||
90 | /* If warn_on_bump and the needed architecture is higher than this | |
91 | architecture, issue a warning. */ | |
92 | static enum sparc_opcode_arch_val warn_after_architecture; | |
93 | ||
6d8809aa RH |
94 | /* Non-zero if as should generate error if an undeclared g[23] register |
95 | has been used in -64. */ | |
96 | static int no_undeclared_regs; | |
97 | ||
6faf3d66 JJ |
98 | /* Non-zero if we should try to relax jumps and calls. */ |
99 | static int sparc_relax; | |
100 | ||
252b5132 RH |
101 | /* Non-zero if we are generating PIC code. */ |
102 | int sparc_pic_code; | |
103 | ||
104 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
105 | static int enforce_aligned_data; | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
109 | static int target_little_endian_data; | |
110 | ||
6d8809aa RH |
111 | /* Symbols for global registers on v9. */ |
112 | static symbolS *globals[8]; | |
113 | ||
364b6d8b JJ |
114 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
115 | int sparc_cie_data_alignment; | |
116 | ||
252b5132 RH |
117 | /* V9 and 86x have big and little endian data, but instructions are always big |
118 | endian. The sparclet has bi-endian support but both data and insns have | |
119 | the same endianness. Global `target_big_endian' is used for data. | |
120 | The following macro is used for instructions. */ | |
121 | #ifndef INSN_BIG_ENDIAN | |
122 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
123 | || default_arch_type == sparc86x \ | |
124 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
125 | #endif | |
126 | ||
e0c6ed95 | 127 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
128 | static struct hash_control *op_hash; |
129 | ||
5a49b8ac AM |
130 | static void s_data1 (void); |
131 | static void s_seg (int); | |
132 | static void s_proc (int); | |
133 | static void s_reserve (int); | |
134 | static void s_common (int); | |
135 | static void s_empty (int); | |
136 | static void s_uacons (int); | |
137 | static void s_ncons (int); | |
a7982600 | 138 | #ifdef OBJ_ELF |
5a49b8ac | 139 | static void s_register (int); |
a7982600 | 140 | #endif |
252b5132 RH |
141 | |
142 | const pseudo_typeS md_pseudo_table[] = | |
143 | { | |
e0c6ed95 | 144 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
145 | {"common", s_common, 0}, |
146 | {"empty", s_empty, 0}, | |
147 | {"global", s_globl, 0}, | |
148 | {"half", cons, 2}, | |
cf9a1301 | 149 | {"nword", s_ncons, 0}, |
252b5132 RH |
150 | {"optim", s_ignore, 0}, |
151 | {"proc", s_proc, 0}, | |
152 | {"reserve", s_reserve, 0}, | |
153 | {"seg", s_seg, 0}, | |
154 | {"skip", s_space, 0}, | |
155 | {"word", cons, 4}, | |
156 | {"xword", cons, 8}, | |
157 | {"uahalf", s_uacons, 2}, | |
158 | {"uaword", s_uacons, 4}, | |
159 | {"uaxword", s_uacons, 8}, | |
160 | #ifdef OBJ_ELF | |
e0c6ed95 | 161 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
162 | {"2byte", s_uacons, 2}, |
163 | {"4byte", s_uacons, 4}, | |
164 | {"8byte", s_uacons, 8}, | |
6d8809aa | 165 | {"register", s_register, 0}, |
252b5132 RH |
166 | #endif |
167 | {NULL, 0, 0}, | |
168 | }; | |
169 | ||
252b5132 | 170 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
171 | pre-processor is disabled, these aren't very useful. */ |
172 | const char comment_chars[] = "!"; /* JF removed '|' from | |
173 | comment_chars. */ | |
252b5132 RH |
174 | |
175 | /* This array holds the chars that only start a comment at the beginning of | |
176 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 177 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
178 | /* Note that input_file.c hand checks for '#' at the beginning of the |
179 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 180 | #NO_APP at the beginning of its output. */ |
252b5132 | 181 | /* Also note that comments started like this one will always |
e0c6ed95 | 182 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
183 | const char line_comment_chars[] = "#"; |
184 | ||
63a0b638 | 185 | const char line_separator_chars[] = ";"; |
252b5132 | 186 | |
e0c6ed95 AM |
187 | /* Chars that can be used to separate mant from exp in floating point |
188 | nums. */ | |
252b5132 RH |
189 | const char EXP_CHARS[] = "eE"; |
190 | ||
e0c6ed95 AM |
191 | /* Chars that mean this number is a floating point constant. |
192 | As in 0f12.456 | |
193 | or 0d1.2345e12 */ | |
252b5132 RH |
194 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
195 | ||
196 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
197 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
198 | but nothing is ideal around here. */ | |
199 | ||
74b56d1f | 200 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
201 | |
202 | struct sparc_it | |
203 | { | |
204 | char *error; | |
205 | unsigned long opcode; | |
206 | struct nlist *nlistp; | |
207 | expressionS exp; | |
cf9a1301 | 208 | expressionS exp2; |
252b5132 RH |
209 | int pcrel; |
210 | bfd_reloc_code_real_type reloc; | |
211 | }; | |
212 | ||
213 | struct sparc_it the_insn, set_insn; | |
214 | ||
5a49b8ac | 215 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
216 | \f |
217 | /* Table of arguments to -A. | |
218 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
219 | for this use. That table is for opcodes only. This table is for opcodes | |
220 | and file formats. */ | |
221 | ||
222 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
19f7b010 | 223 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
224 | |
225 | static struct sparc_arch { | |
226 | char *name; | |
227 | char *opcode_arch; | |
228 | enum sparc_arch_types arch_type; | |
229 | /* Default word size, as specified during configuration. | |
230 | A value of zero means can't be used to specify default architecture. */ | |
231 | int default_arch_size; | |
232 | /* Allowable arg to -A? */ | |
233 | int user_option_p; | |
234 | } sparc_arch_table[] = { | |
235 | { "v6", "v6", v6, 0, 1 }, | |
236 | { "v7", "v7", v7, 0, 1 }, | |
237 | { "v8", "v8", v8, 32, 1 }, | |
238 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
239 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
240 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
241 | { "v8plus", "v9", v9, 0, 1 }, | |
242 | { "v8plusa", "v9a", v9, 0, 1 }, | |
19f7b010 | 243 | { "v8plusb", "v9b", v9, 0, 1 }, |
252b5132 RH |
244 | { "v9", "v9", v9, 0, 1 }, |
245 | { "v9a", "v9a", v9, 0, 1 }, | |
19f7b010 | 246 | { "v9b", "v9b", v9, 0, 1 }, |
252b5132 RH |
247 | /* This exists to allow configure.in/Makefile.in to pass one |
248 | value to specify both the default machine and default word size. */ | |
249 | { "v9-64", "v9", v9, 64, 0 }, | |
250 | { NULL, NULL, v8, 0, 0 } | |
251 | }; | |
252 | ||
253 | /* Variant of default_arch */ | |
254 | static enum sparc_arch_types default_arch_type; | |
255 | ||
256 | static struct sparc_arch * | |
5a49b8ac | 257 | lookup_arch (char *name) |
252b5132 RH |
258 | { |
259 | struct sparc_arch *sa; | |
260 | ||
261 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
262 | if (strcmp (sa->name, name) == 0) | |
263 | break; | |
264 | if (sa->name == NULL) | |
265 | return NULL; | |
266 | return sa; | |
267 | } | |
268 | ||
269 | /* Initialize the default opcode arch and word size from the default | |
270 | architecture name. */ | |
271 | ||
272 | static void | |
5a49b8ac | 273 | init_default_arch (void) |
252b5132 RH |
274 | { |
275 | struct sparc_arch *sa = lookup_arch (default_arch); | |
276 | ||
277 | if (sa == NULL | |
278 | || sa->default_arch_size == 0) | |
279 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
280 | ||
281 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
282 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
283 | as_fatal (_("Bad opcode table, broken assembler.")); | |
284 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
285 | default_init_p = 1; | |
286 | default_arch_type = sa->arch_type; | |
287 | } | |
288 | ||
289 | /* Called by TARGET_FORMAT. */ | |
290 | ||
291 | const char * | |
5a49b8ac | 292 | sparc_target_format (void) |
252b5132 RH |
293 | { |
294 | /* We don't get a chance to initialize anything before we're called, | |
295 | so handle that now. */ | |
296 | if (! default_init_p) | |
297 | init_default_arch (); | |
298 | ||
299 | #ifdef OBJ_AOUT | |
300 | #ifdef TE_NetBSD | |
301 | return "a.out-sparc-netbsd"; | |
302 | #else | |
303 | #ifdef TE_SPARCAOUT | |
304 | if (target_big_endian) | |
305 | return "a.out-sunos-big"; | |
306 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
307 | return "a.out-sunos-big"; | |
ab3e48dc KH |
308 | else |
309 | return "a.out-sparc-little"; | |
252b5132 RH |
310 | #else |
311 | return "a.out-sunos-big"; | |
312 | #endif | |
313 | #endif | |
314 | #endif | |
315 | ||
316 | #ifdef OBJ_BOUT | |
317 | return "b.out.big"; | |
318 | #endif | |
319 | ||
320 | #ifdef OBJ_COFF | |
321 | #ifdef TE_LYNX | |
322 | return "coff-sparc-lynx"; | |
323 | #else | |
324 | return "coff-sparc"; | |
325 | #endif | |
326 | #endif | |
327 | ||
910600e9 RS |
328 | #ifdef TE_VXWORKS |
329 | return "elf32-sparc-vxworks"; | |
330 | #endif | |
331 | ||
252b5132 | 332 | #ifdef OBJ_ELF |
71a75f6f | 333 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
334 | #endif |
335 | ||
336 | abort (); | |
337 | } | |
338 | \f | |
e0c6ed95 | 339 | /* md_parse_option |
252b5132 RH |
340 | * Invocation line includes a switch not recognized by the base assembler. |
341 | * See if it's a processor-specific option. These are: | |
342 | * | |
343 | * -bump | |
344 | * Warn on architecture bumps. See also -A. | |
345 | * | |
346 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
347 | * Standard 32 bit architectures. | |
19f7b010 | 348 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
349 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
350 | * This used to only mean 64 bits, but properly specifying it | |
351 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
352 | * specified orthogonally to word size (except when specifying | |
353 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
354 | * -Av8plus, -Av8plusa, -Av8plusb |
355 | * Same as -Av9{,a,b}. | |
356 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
357 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
358 | * assembler. | |
359 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
360 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 361 | * assembler. |
252b5132 RH |
362 | * |
363 | * Select the architecture and possibly the file format. | |
364 | * Instructions or features not supported by the selected | |
365 | * architecture cause fatal errors. | |
366 | * | |
367 | * The default is to start at v6, and bump the architecture up | |
368 | * whenever an instruction is seen at a higher level. In 32 bit | |
369 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 370 | * -Av8plus{,a,b}. |
252b5132 RH |
371 | * |
372 | * If -bump is specified, a warning is printing when bumping to | |
373 | * higher levels. | |
374 | * | |
375 | * If an architecture is specified, all instructions must match | |
376 | * that architecture. Any higher level instructions are flagged | |
377 | * as errors. Note that in the 32 bit environment specifying | |
378 | * -Av8plus does not automatically create a v8plus object file, a | |
379 | * v9 insn must be seen. | |
380 | * | |
381 | * If both an architecture and -bump are specified, the | |
382 | * architecture starts at the specified level, but bumps are | |
383 | * warnings. Note that we can't set `current_architecture' to | |
384 | * the requested level in this case: in the 32 bit environment, | |
385 | * we still must avoid creating v8plus object files unless v9 | |
386 | * insns are seen. | |
387 | * | |
388 | * Note: | |
389 | * Bumping between incompatible architectures is always an | |
390 | * error. For example, from sparclite to v9. | |
391 | */ | |
392 | ||
393 | #ifdef OBJ_ELF | |
5a38dc70 | 394 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
395 | #else |
396 | #ifdef OBJ_AOUT | |
5a38dc70 | 397 | const char *md_shortopts = "A:k"; |
252b5132 | 398 | #else |
5a38dc70 | 399 | const char *md_shortopts = "A:"; |
252b5132 RH |
400 | #endif |
401 | #endif | |
402 | struct option md_longopts[] = { | |
403 | #define OPTION_BUMP (OPTION_MD_BASE) | |
404 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
405 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
406 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
407 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
408 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
409 | #ifdef OBJ_ELF | |
410 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
411 | {"32", no_argument, NULL, OPTION_32}, | |
412 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
413 | {"64", no_argument, NULL, OPTION_64}, | |
414 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
415 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
416 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
417 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
418 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
419 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
420 | #endif | |
421 | #ifdef SPARC_BIENDIAN | |
422 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
423 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
424 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
425 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
426 | #endif | |
427 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
428 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
429 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
430 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
431 | #ifdef OBJ_ELF |
432 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
433 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
434 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
435 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 436 | #endif |
6faf3d66 JJ |
437 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
438 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
439 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
440 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
441 | {NULL, no_argument, NULL, 0} |
442 | }; | |
e0c6ed95 AM |
443 | |
444 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
445 | |
446 | int | |
5a49b8ac | 447 | md_parse_option (int c, char *arg) |
252b5132 RH |
448 | { |
449 | /* We don't get a chance to initialize anything before we're called, | |
450 | so handle that now. */ | |
451 | if (! default_init_p) | |
452 | init_default_arch (); | |
453 | ||
454 | switch (c) | |
455 | { | |
456 | case OPTION_BUMP: | |
457 | warn_on_bump = 1; | |
458 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
459 | break; | |
460 | ||
461 | case OPTION_XARCH: | |
c2158c24 JJ |
462 | #ifdef OBJ_ELF |
463 | if (strncmp (arg, "v9", 2) != 0) | |
464 | md_parse_option (OPTION_32, NULL); | |
465 | else | |
466 | md_parse_option (OPTION_64, NULL); | |
467 | #endif | |
e0c6ed95 | 468 | /* Fall through. */ |
252b5132 RH |
469 | |
470 | case 'A': | |
471 | { | |
472 | struct sparc_arch *sa; | |
473 | enum sparc_opcode_arch_val opcode_arch; | |
474 | ||
475 | sa = lookup_arch (arg); | |
476 | if (sa == NULL | |
477 | || ! sa->user_option_p) | |
478 | { | |
c2158c24 JJ |
479 | if (c == OPTION_XARCH) |
480 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
481 | else | |
482 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
483 | return 0; |
484 | } | |
485 | ||
486 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
487 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
488 | as_fatal (_("Bad opcode table, broken assembler.")); | |
489 | ||
490 | max_architecture = opcode_arch; | |
491 | architecture_requested = 1; | |
492 | } | |
493 | break; | |
494 | ||
495 | case OPTION_SPARC: | |
496 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
497 | break; | |
498 | ||
499 | case OPTION_ENFORCE_ALIGNED_DATA: | |
500 | enforce_aligned_data = 1; | |
501 | break; | |
502 | ||
503 | #ifdef SPARC_BIENDIAN | |
504 | case OPTION_LITTLE_ENDIAN: | |
505 | target_big_endian = 0; | |
506 | if (default_arch_type != sparclet) | |
507 | as_fatal ("This target does not support -EL"); | |
508 | break; | |
509 | case OPTION_LITTLE_ENDIAN_DATA: | |
510 | target_little_endian_data = 1; | |
511 | target_big_endian = 0; | |
512 | if (default_arch_type != sparc86x | |
513 | && default_arch_type != v9) | |
514 | as_fatal ("This target does not support --little-endian-data"); | |
515 | break; | |
516 | case OPTION_BIG_ENDIAN: | |
517 | target_big_endian = 1; | |
518 | break; | |
519 | #endif | |
520 | ||
521 | #ifdef OBJ_AOUT | |
522 | case 'k': | |
523 | sparc_pic_code = 1; | |
524 | break; | |
525 | #endif | |
526 | ||
527 | #ifdef OBJ_ELF | |
528 | case OPTION_32: | |
529 | case OPTION_64: | |
530 | { | |
531 | const char **list, **l; | |
532 | ||
533 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
534 | list = bfd_target_list (); | |
535 | for (l = list; *l != NULL; l++) | |
536 | { | |
537 | if (sparc_arch_size == 32) | |
538 | { | |
71a75f6f | 539 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
540 | break; |
541 | } | |
542 | else | |
543 | { | |
71a75f6f | 544 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
545 | break; |
546 | } | |
547 | } | |
548 | if (*l == NULL) | |
549 | as_fatal (_("No compiled in support for %d bit object file format"), | |
550 | sparc_arch_size); | |
551 | free (list); | |
b7cac25f DM |
552 | |
553 | if (sparc_arch_size == 64 | |
554 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
555 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
556 | } |
557 | break; | |
558 | ||
559 | case OPTION_TSO: | |
560 | sparc_memory_model = MM_TSO; | |
561 | break; | |
562 | ||
563 | case OPTION_PSO: | |
564 | sparc_memory_model = MM_PSO; | |
565 | break; | |
566 | ||
567 | case OPTION_RMO: | |
568 | sparc_memory_model = MM_RMO; | |
569 | break; | |
570 | ||
571 | case 'V': | |
572 | print_version_id (); | |
573 | break; | |
574 | ||
575 | case 'Q': | |
576 | /* Qy - do emit .comment | |
e0c6ed95 | 577 | Qn - do not emit .comment. */ |
252b5132 RH |
578 | break; |
579 | ||
580 | case 's': | |
e0c6ed95 | 581 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
582 | break; |
583 | ||
584 | case 'q': | |
e0c6ed95 | 585 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
586 | break; |
587 | ||
588 | case 'K': | |
589 | if (strcmp (arg, "PIC") != 0) | |
590 | as_warn (_("Unrecognized option following -K")); | |
591 | else | |
592 | sparc_pic_code = 1; | |
593 | break; | |
6d8809aa RH |
594 | |
595 | case OPTION_NO_UNDECLARED_REGS: | |
596 | no_undeclared_regs = 1; | |
597 | break; | |
a25fe906 ILT |
598 | |
599 | case OPTION_UNDECLARED_REGS: | |
600 | no_undeclared_regs = 0; | |
601 | break; | |
252b5132 RH |
602 | #endif |
603 | ||
6faf3d66 JJ |
604 | case OPTION_RELAX: |
605 | sparc_relax = 1; | |
606 | break; | |
607 | ||
608 | case OPTION_NO_RELAX: | |
609 | sparc_relax = 0; | |
610 | break; | |
611 | ||
252b5132 RH |
612 | default: |
613 | return 0; | |
614 | } | |
615 | ||
616 | return 1; | |
617 | } | |
618 | ||
619 | void | |
5a49b8ac | 620 | md_show_usage (FILE *stream) |
252b5132 RH |
621 | { |
622 | const struct sparc_arch *arch; | |
c2158c24 | 623 | int column; |
252b5132 RH |
624 | |
625 | /* We don't get a chance to initialize anything before we're called, | |
626 | so handle that now. */ | |
627 | if (! default_init_p) | |
628 | init_default_arch (); | |
629 | ||
e0c6ed95 | 630 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 631 | column = 0; |
252b5132 RH |
632 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
633 | { | |
c2158c24 JJ |
634 | if (!arch->user_option_p) |
635 | continue; | |
252b5132 RH |
636 | if (arch != &sparc_arch_table[0]) |
637 | fprintf (stream, " | "); | |
07726851 | 638 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
639 | { |
640 | column = 0; | |
641 | fputc ('\n', stream); | |
642 | } | |
07726851 | 643 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 644 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 645 | } |
c2158c24 JJ |
646 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
647 | { | |
648 | if (!arch->user_option_p) | |
649 | continue; | |
650 | fprintf (stream, " | "); | |
07726851 | 651 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
652 | { |
653 | column = 0; | |
654 | fputc ('\n', stream); | |
655 | } | |
07726851 | 656 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
657 | fprintf (stream, "-xarch=%s", arch->name); |
658 | } | |
659 | fprintf (stream, _("\n\ | |
252b5132 RH |
660 | specify variant of SPARC architecture\n\ |
661 | -bump warn when assembler switches architectures\n\ | |
662 | -sparc ignored\n\ | |
6faf3d66 JJ |
663 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
664 | -relax relax jumps and branches (default)\n\ | |
665 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
666 | #ifdef OBJ_AOUT |
667 | fprintf (stream, _("\ | |
668 | -k generate PIC\n")); | |
669 | #endif | |
670 | #ifdef OBJ_ELF | |
671 | fprintf (stream, _("\ | |
672 | -32 create 32 bit object file\n\ | |
673 | -64 create 64 bit object file\n")); | |
674 | fprintf (stream, _("\ | |
675 | [default is %d]\n"), default_arch_size); | |
676 | fprintf (stream, _("\ | |
677 | -TSO use Total Store Ordering\n\ | |
678 | -PSO use Partial Store Ordering\n\ | |
679 | -RMO use Relaxed Memory Ordering\n")); | |
680 | fprintf (stream, _("\ | |
681 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
682 | fprintf (stream, _("\ | |
683 | -KPIC generate PIC\n\ | |
684 | -V print assembler version number\n\ | |
a25fe906 ILT |
685 | -undeclared-regs ignore application global register usage without\n\ |
686 | appropriate .register directive (default)\n\ | |
687 | -no-undeclared-regs force error on application global register usage\n\ | |
688 | without appropriate .register directive\n\ | |
252b5132 RH |
689 | -q ignored\n\ |
690 | -Qy, -Qn ignored\n\ | |
691 | -s ignored\n")); | |
692 | #endif | |
693 | #ifdef SPARC_BIENDIAN | |
694 | fprintf (stream, _("\ | |
695 | -EL generate code for a little endian machine\n\ | |
696 | -EB generate code for a big endian machine\n\ | |
697 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 698 | instructions and little endian data.\n")); |
252b5132 RH |
699 | #endif |
700 | } | |
701 | \f | |
e0c6ed95 | 702 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
703 | struct |
704 | { | |
705 | char *name; | |
706 | char *name32; | |
707 | char *name64; | |
708 | } native_op_table[] = | |
709 | { | |
710 | {"ldn", "ld", "ldx"}, | |
711 | {"ldna", "lda", "ldxa"}, | |
712 | {"stn", "st", "stx"}, | |
713 | {"stna", "sta", "stxa"}, | |
714 | {"slln", "sll", "sllx"}, | |
715 | {"srln", "srl", "srlx"}, | |
716 | {"sran", "sra", "srax"}, | |
717 | {"casn", "cas", "casx"}, | |
718 | {"casna", "casa", "casxa"}, | |
719 | {"clrn", "clr", "clrx"}, | |
720 | {NULL, NULL, NULL}, | |
721 | }; | |
722 | \f | |
10156f83 | 723 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
724 | |
725 | struct priv_reg_entry | |
ab3e48dc KH |
726 | { |
727 | char *name; | |
728 | int regnum; | |
729 | }; | |
252b5132 RH |
730 | |
731 | struct priv_reg_entry priv_reg_table[] = | |
732 | { | |
733 | {"tpc", 0}, | |
734 | {"tnpc", 1}, | |
735 | {"tstate", 2}, | |
736 | {"tt", 3}, | |
737 | {"tick", 4}, | |
738 | {"tba", 5}, | |
739 | {"pstate", 6}, | |
740 | {"tl", 7}, | |
741 | {"pil", 8}, | |
742 | {"cwp", 9}, | |
743 | {"cansave", 10}, | |
744 | {"canrestore", 11}, | |
745 | {"cleanwin", 12}, | |
746 | {"otherwin", 13}, | |
747 | {"wstate", 14}, | |
748 | {"fq", 15}, | |
10156f83 | 749 | {"gl", 16}, |
252b5132 | 750 | {"ver", 31}, |
e0c6ed95 | 751 | {"", -1}, /* End marker. */ |
252b5132 RH |
752 | }; |
753 | ||
10156f83 DM |
754 | struct priv_reg_entry hpriv_reg_table[] = |
755 | { | |
756 | {"hpstate", 0}, | |
757 | {"htstate", 1}, | |
758 | {"hintp", 3}, | |
759 | {"htba", 5}, | |
760 | {"hver", 6}, | |
761 | {"hstick_cmpr", 31}, | |
762 | {"", -1}, /* End marker. */ | |
763 | }; | |
764 | ||
1a6b486f DM |
765 | /* v9a specific asrs. This table is ordered by initial |
766 | letter, in reverse. */ | |
252b5132 RH |
767 | |
768 | struct priv_reg_entry v9a_asr_table[] = | |
769 | { | |
770 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
771 | {"sys_tick_cmpr", 25}, |
772 | {"sys_tick", 24}, | |
1a6b486f DM |
773 | {"stick_cmpr", 25}, |
774 | {"stick", 24}, | |
f04d18b7 DM |
775 | {"softint_clear", 21}, |
776 | {"softint_set", 20}, | |
2b661f3d | 777 | {"softint", 22}, |
252b5132 RH |
778 | {"set_softint", 20}, |
779 | {"pic", 17}, | |
780 | {"pcr", 16}, | |
781 | {"gsr", 19}, | |
782 | {"dcr", 18}, | |
ea783ef3 | 783 | {"cps", 28}, |
252b5132 | 784 | {"clear_softint", 21}, |
e0c6ed95 | 785 | {"", -1}, /* End marker. */ |
252b5132 RH |
786 | }; |
787 | ||
788 | static int | |
5a49b8ac | 789 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
790 | { |
791 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
792 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
793 | ||
794 | return strcmp (q->name, p->name); | |
795 | } | |
796 | \f | |
797 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
798 | set up all the tables, etc. that the MD part of the assembler will |
799 | need. */ | |
252b5132 RH |
800 | |
801 | void | |
5a49b8ac | 802 | md_begin (void) |
252b5132 RH |
803 | { |
804 | register const char *retval = NULL; | |
805 | int lose = 0; | |
806 | register unsigned int i = 0; | |
807 | ||
808 | /* We don't get a chance to initialize anything before md_parse_option | |
809 | is called, and it may not be called, so handle default initialization | |
810 | now if not already done. */ | |
811 | if (! default_init_p) | |
812 | init_default_arch (); | |
813 | ||
364b6d8b | 814 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
815 | op_hash = hash_new (); |
816 | ||
817 | while (i < (unsigned int) sparc_num_opcodes) | |
818 | { | |
819 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 820 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
821 | if (retval != NULL) |
822 | { | |
cf9a1301 RH |
823 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
824 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
825 | lose = 1; |
826 | } | |
827 | do | |
828 | { | |
829 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
830 | { | |
cf9a1301 RH |
831 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
832 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
833 | lose = 1; |
834 | } | |
835 | ++i; | |
836 | } | |
837 | while (i < (unsigned int) sparc_num_opcodes | |
838 | && !strcmp (sparc_opcodes[i].name, name)); | |
839 | } | |
840 | ||
cf9a1301 RH |
841 | for (i = 0; native_op_table[i].name; i++) |
842 | { | |
843 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
844 | char *name = ((sparc_arch_size == 32) |
845 | ? native_op_table[i].name32 | |
846 | : native_op_table[i].name64); | |
e0c6ed95 | 847 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 848 | if (insn == NULL) |
e0c6ed95 AM |
849 | { |
850 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
851 | name, native_op_table[i].name); | |
852 | lose = 1; | |
853 | } | |
cf9a1301 RH |
854 | else |
855 | { | |
5a49b8ac AM |
856 | retval = hash_insert (op_hash, native_op_table[i].name, |
857 | (void *) insn); | |
cf9a1301 RH |
858 | if (retval != NULL) |
859 | { | |
860 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
861 | sparc_opcodes[i].name, retval); | |
862 | lose = 1; | |
863 | } | |
864 | } | |
865 | } | |
866 | ||
252b5132 RH |
867 | if (lose) |
868 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
869 | ||
252b5132 RH |
870 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
871 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
872 | ||
873 | /* If -bump, record the architecture level at which we start issuing | |
874 | warnings. The behaviour is different depending upon whether an | |
875 | architecture was explicitly specified. If it wasn't, we issue warnings | |
876 | for all upwards bumps. If it was, we don't start issuing warnings until | |
877 | we need to bump beyond the requested architecture or when we bump between | |
878 | conflicting architectures. */ | |
879 | ||
880 | if (warn_on_bump | |
881 | && architecture_requested) | |
882 | { | |
883 | /* `max_architecture' records the requested architecture. | |
884 | Issue warnings if we go above it. */ | |
885 | warn_after_architecture = max_architecture; | |
886 | ||
887 | /* Find the highest architecture level that doesn't conflict with | |
888 | the requested one. */ | |
889 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
890 | max_architecture > warn_after_architecture; | |
891 | --max_architecture) | |
892 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
893 | warn_after_architecture)) | |
894 | break; | |
895 | } | |
896 | } | |
897 | ||
898 | /* Called after all assembly has been done. */ | |
899 | ||
900 | void | |
5a49b8ac | 901 | sparc_md_end (void) |
252b5132 | 902 | { |
19f7b010 JJ |
903 | unsigned long mach = bfd_mach_sparc; |
904 | ||
252b5132 | 905 | if (sparc_arch_size == 64) |
19f7b010 JJ |
906 | switch (current_architecture) |
907 | { | |
908 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
909 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
910 | default: mach = bfd_mach_sparc_v9; break; | |
911 | } | |
252b5132 | 912 | else |
19f7b010 JJ |
913 | switch (current_architecture) |
914 | { | |
915 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
916 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
917 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
918 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
919 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
920 | be but for now it is (since that's the way it's always been | |
921 | treated). */ | |
922 | default: break; | |
923 | } | |
924 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
925 | |
926 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
927 | if (hwcap_seen) | |
928 | { | |
929 | int bits = 0; | |
930 | ||
931 | if (hwcap_seen & F_MUL32) | |
932 | bits |= ELF_SPARC_HWCAP_MUL32; | |
933 | if (hwcap_seen & F_DIV32) | |
934 | bits |= ELF_SPARC_HWCAP_DIV32; | |
935 | if (hwcap_seen & F_FSMULD) | |
936 | bits |= ELF_SPARC_HWCAP_FSMULD; | |
937 | if (hwcap_seen & F_V8PLUS) | |
938 | bits |= ELF_SPARC_HWCAP_V8PLUS; | |
939 | if (hwcap_seen & F_POPC) | |
940 | bits |= ELF_SPARC_HWCAP_POPC; | |
941 | if (hwcap_seen & F_VIS) | |
942 | bits |= ELF_SPARC_HWCAP_VIS; | |
943 | if (hwcap_seen & F_VIS2) | |
944 | bits |= ELF_SPARC_HWCAP_VIS2; | |
945 | if (hwcap_seen & F_ASI_BLK_INIT) | |
946 | bits |= ELF_SPARC_HWCAP_ASI_BLK_INIT; | |
947 | if (hwcap_seen & F_FMAF) | |
948 | bits |= ELF_SPARC_HWCAP_FMAF; | |
949 | if (hwcap_seen & F_VIS3) | |
950 | bits |= ELF_SPARC_HWCAP_VIS3; | |
951 | if (hwcap_seen & F_HPC) | |
952 | bits |= ELF_SPARC_HWCAP_HPC; | |
953 | if (hwcap_seen & F_RANDOM) | |
954 | bits |= ELF_SPARC_HWCAP_RANDOM; | |
955 | if (hwcap_seen & F_TRANS) | |
956 | bits |= ELF_SPARC_HWCAP_TRANS; | |
957 | if (hwcap_seen & F_FJFMAU) | |
958 | bits |= ELF_SPARC_HWCAP_FJFMAU; | |
959 | if (hwcap_seen & F_IMA) | |
960 | bits |= ELF_SPARC_HWCAP_IMA; | |
961 | if (hwcap_seen & F_ASI_CACHE_SPARING) | |
962 | bits |= ELF_SPARC_HWCAP_ASI_CACHE_SPARING; | |
963 | ||
964 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, bits); | |
965 | } | |
966 | #endif | |
252b5132 RH |
967 | } |
968 | \f | |
969 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
970 | ||
5a49b8ac AM |
971 | static inline int |
972 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
973 | { |
974 | if (max <= 0) | |
975 | abort (); | |
976 | /* Sign-extend the value from the architecture word size, so that | |
977 | 0xffffffff is always considered -1 on sparc32. */ | |
978 | if (sparc_arch_size == 32) | |
979 | { | |
e0c6ed95 | 980 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 981 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
982 | } |
983 | if (val > max) | |
984 | return 0; | |
985 | if (val < ~max) | |
986 | return 0; | |
987 | return 1; | |
988 | } | |
989 | ||
990 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
991 | ||
5a49b8ac AM |
992 | static inline int |
993 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
994 | { |
995 | if (val > max) | |
996 | return 0; | |
997 | return 1; | |
998 | } | |
999 | ||
1000 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
1001 | (e.g. -15 to +31). */ | |
1002 | ||
5a49b8ac AM |
1003 | static inline int |
1004 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1005 | { |
1006 | if (max <= 0) | |
1007 | abort (); | |
1008 | if (val > max) | |
1009 | return 0; | |
1010 | if (val < ~(max >> 1)) | |
1011 | return 0; | |
1012 | return 1; | |
1013 | } | |
1014 | ||
1015 | static int | |
5a49b8ac | 1016 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1017 | { |
1018 | int i; | |
1019 | ||
1020 | if (mask == 0) | |
1021 | return -1; | |
1022 | ||
1023 | for (i = 0; (mask & 1) == 0; ++i) | |
1024 | mask >>= 1; | |
1025 | return i; | |
1026 | } | |
1027 | ||
1028 | /* Implement big shift right. */ | |
1029 | static bfd_vma | |
5a49b8ac | 1030 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1031 | { |
1032 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1033 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1034 | return val >> amount; | |
1035 | } | |
1036 | \f | |
1037 | /* For communication between sparc_ip and get_expression. */ | |
1038 | static char *expr_end; | |
1039 | ||
252b5132 RH |
1040 | /* Values for `special_case'. |
1041 | Instructions that require wierd handling because they're longer than | |
1042 | 4 bytes. */ | |
1043 | #define SPECIAL_CASE_NONE 0 | |
1044 | #define SPECIAL_CASE_SET 1 | |
1045 | #define SPECIAL_CASE_SETSW 2 | |
1046 | #define SPECIAL_CASE_SETX 3 | |
1047 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1048 | #define SPECIAL_CASE_FDIV 4 | |
1049 | ||
1050 | /* Bit masks of various insns. */ | |
1051 | #define NOP_INSN 0x01000000 | |
1052 | #define OR_INSN 0x80100000 | |
63fab58c | 1053 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1054 | #define FMOVS_INSN 0x81A00020 |
1055 | #define SETHI_INSN 0x01000000 | |
1056 | #define SLLX_INSN 0x81281000 | |
1057 | #define SRA_INSN 0x81380000 | |
1058 | ||
1059 | /* The last instruction to be assembled. */ | |
1060 | static const struct sparc_opcode *last_insn; | |
1061 | /* The assembled opcode of `last_insn'. */ | |
1062 | static unsigned long last_opcode; | |
1063 | \f | |
a22b281c | 1064 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1065 | |
a22b281c | 1066 | static void |
5a49b8ac | 1067 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1068 | { |
1069 | int need_hi22_p = 0; | |
1070 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1071 | ||
1072 | if (the_insn.exp.X_op == O_constant) | |
1073 | { | |
1074 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1075 | { | |
e0c6ed95 | 1076 | if (sizeof (offsetT) > 4 |
a22b281c | 1077 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1078 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1079 | as_warn (_("set: number not in 0..4294967295 range")); |
1080 | } | |
1081 | else | |
1082 | { | |
e0c6ed95 | 1083 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1084 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1085 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1086 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1087 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1088 | } |
1089 | } | |
1090 | ||
1091 | /* See if operand is absolute and small; skip sethi if so. */ | |
1092 | if (the_insn.exp.X_op != O_constant | |
1093 | || the_insn.exp.X_add_number >= (1 << 12) | |
1094 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1095 | { | |
1096 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1097 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1098 | & (the_insn.exp.X_op == O_constant |
1099 | ? 0x3fffff : 0))); | |
a22b281c | 1100 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1101 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1102 | output_insn (insn, &the_insn); |
1103 | need_hi22_p = 1; | |
1104 | } | |
1105 | ||
1106 | /* See if operand has no low-order bits; skip OR if so. */ | |
1107 | if (the_insn.exp.X_op != O_constant | |
1108 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1109 | || ! need_hi22_p) | |
1110 | { | |
1111 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1112 | | RD (rd) | IMMED | |
1113 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1114 | & (the_insn.exp.X_op != O_constant |
1115 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1116 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1117 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1118 | output_insn (insn, &the_insn); |
1119 | } | |
1120 | } | |
e0c6ed95 | 1121 | |
a22b281c | 1122 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1123 | |
a22b281c | 1124 | static void |
5a49b8ac | 1125 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1126 | { |
1127 | int low32, rd, opc; | |
1128 | ||
1129 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1130 | ||
1131 | if (the_insn.exp.X_op != O_constant) | |
1132 | { | |
1133 | synthetize_setuw (insn); | |
1134 | ||
1135 | /* Need to sign extend it. */ | |
1136 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1137 | the_insn.reloc = BFD_RELOC_NONE; | |
1138 | output_insn (insn, &the_insn); | |
1139 | return; | |
1140 | } | |
1141 | ||
e0c6ed95 | 1142 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1143 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1144 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1145 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1146 | ||
e0c6ed95 AM |
1147 | low32 = the_insn.exp.X_add_number; |
1148 | ||
a22b281c RH |
1149 | if (low32 >= 0) |
1150 | { | |
1151 | synthetize_setuw (insn); | |
1152 | return; | |
1153 | } | |
1154 | ||
1155 | opc = OR_INSN; | |
e0c6ed95 | 1156 | |
a22b281c RH |
1157 | the_insn.reloc = BFD_RELOC_NONE; |
1158 | /* See if operand is absolute and small; skip sethi if so. */ | |
1159 | if (low32 < -(1 << 12)) | |
1160 | { | |
1161 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1162 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1163 | output_insn (insn, &the_insn); | |
1164 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1165 | opc = RS1 (rd) | XOR_INSN; | |
1166 | } | |
1167 | ||
1168 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1169 | | (low32 & 0x1fff)); | |
1170 | output_insn (insn, &the_insn); | |
1171 | } | |
1172 | ||
1173 | /* Handle the setsw synthetic instruction. */ | |
e0c6ed95 | 1174 | |
a22b281c | 1175 | static void |
5a49b8ac | 1176 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1177 | { |
1178 | int upper32, lower32; | |
1179 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1180 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1181 | int upper_dstreg; | |
1182 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1183 | int need_xor10_p = 0; | |
e0c6ed95 | 1184 | |
6c1b24e4 | 1185 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1186 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1187 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1188 | #undef SIGNEXT32 | |
1189 | ||
1190 | upper_dstreg = tmpreg; | |
1191 | /* The tmp reg should not be the dst reg. */ | |
1192 | if (tmpreg == dstreg) | |
1193 | as_warn (_("setx: temporary register same as destination register")); | |
1194 | ||
1195 | /* ??? Obviously there are other optimizations we can do | |
1196 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1197 | doing some of these. Later. If you do change things, try to | |
1198 | change all of this to be table driven as well. */ | |
1199 | /* What to output depends on the number if it's constant. | |
1200 | Compute that first, then output what we've decided upon. */ | |
1201 | if (the_insn.exp.X_op != O_constant) | |
1202 | { | |
1203 | if (sparc_arch_size == 32) | |
1204 | { | |
1205 | /* When arch size is 32, we want setx to be equivalent | |
1206 | to setuw for anything but constants. */ | |
1207 | the_insn.exp.X_add_number &= 0xffffffff; | |
1208 | synthetize_setuw (insn); | |
1209 | return; | |
1210 | } | |
1211 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1212 | lower32 = 0; |
1213 | upper32 = 0; | |
a22b281c RH |
1214 | } |
1215 | else | |
1216 | { | |
1217 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1218 | Otherwise fixup_segment will complain about not being able to | |
1219 | write an 8 byte number in a 4 byte field. */ | |
1220 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1221 | |
a22b281c RH |
1222 | /* Only need hh22 if `or' insn can't handle constant. */ |
1223 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1224 | need_hh22_p = 1; | |
e0c6ed95 | 1225 | |
a22b281c RH |
1226 | /* Does bottom part (after sethi) have bits? */ |
1227 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1228 | /* No hh22, but does upper32 still have bits we can't set | |
1229 | from lower32? */ | |
1230 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1231 | need_hm10_p = 1; | |
e0c6ed95 | 1232 | |
a22b281c RH |
1233 | /* If the lower half is all zero, we build the upper half directly |
1234 | into the dst reg. */ | |
1235 | if (lower32 != 0 | |
1236 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1237 | || (! need_hh22_p && ! need_hm10_p)) | |
1238 | { | |
1239 | /* No need for sethi if `or' insn can handle constant. */ | |
1240 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1241 | /* Note that we can't use a negative constant in the `or' | |
1242 | insn unless the upper 32 bits are all ones. */ | |
1243 | || (lower32 < 0 && upper32 != -1) | |
1244 | || (lower32 >= 0 && upper32 == -1)) | |
1245 | need_hi22_p = 1; | |
e0c6ed95 | 1246 | |
a22b281c RH |
1247 | if (need_hi22_p && upper32 == -1) |
1248 | need_xor10_p = 1; | |
1249 | ||
1250 | /* Does bottom part (after sethi) have bits? */ | |
1251 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1252 | /* No sethi. */ | |
1253 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1254 | /* Need `or' if we didn't set anything else. */ | |
1255 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1256 | need_lo10_p = 1; | |
1257 | } | |
1258 | else | |
1259 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1260 | upper_dstreg = dstreg; | |
1261 | } | |
e0c6ed95 | 1262 | |
a22b281c RH |
1263 | if (!upper_dstreg && dstreg) |
1264 | as_warn (_("setx: illegal temporary register g0")); | |
1265 | ||
1266 | if (need_hh22_p) | |
1267 | { | |
1268 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1269 | | ((upper32 >> 10) & 0x3fffff)); | |
1270 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1271 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1272 | output_insn (insn, &the_insn); | |
1273 | } | |
e0c6ed95 | 1274 | |
a22b281c RH |
1275 | if (need_hi22_p) |
1276 | { | |
1277 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1278 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1279 | >> 10) & 0x3fffff)); |
a22b281c RH |
1280 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1281 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1282 | output_insn (insn, &the_insn); | |
1283 | } | |
1284 | ||
1285 | if (need_hm10_p) | |
1286 | { | |
1287 | the_insn.opcode = (OR_INSN | |
1288 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1289 | | RD (upper_dstreg) | |
1290 | | IMMED | |
1291 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1292 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1293 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1294 | output_insn (insn, &the_insn); | |
1295 | } | |
e0c6ed95 | 1296 | |
a22b281c RH |
1297 | if (need_lo10_p) |
1298 | { | |
1299 | /* FIXME: One nice optimization to do here is to OR the low part | |
1300 | with the highpart if hi22 isn't needed and the low part is | |
1301 | positive. */ | |
1302 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1303 | | RD (dstreg) | |
1304 | | IMMED | |
1305 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1306 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1307 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1308 | output_insn (insn, &the_insn); | |
1309 | } | |
e0c6ed95 | 1310 | |
a22b281c RH |
1311 | /* If we needed to build the upper part, shift it into place. */ |
1312 | if (need_hh22_p || need_hm10_p) | |
1313 | { | |
1314 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1315 | | IMMED | 32); | |
1316 | the_insn.reloc = BFD_RELOC_NONE; | |
1317 | output_insn (insn, &the_insn); | |
1318 | } | |
e0c6ed95 | 1319 | |
a22b281c RH |
1320 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1321 | if (need_xor10_p) | |
1322 | { | |
1323 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1324 | | 0x1c00 | (lower32 & 0x3ff)); | |
1325 | the_insn.reloc = BFD_RELOC_NONE; | |
1326 | output_insn (insn, &the_insn); | |
1327 | } | |
1328 | ||
1329 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1330 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1331 | { | |
1332 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1333 | | RD (dstreg)); | |
1334 | the_insn.reloc = BFD_RELOC_NONE; | |
1335 | output_insn (insn, &the_insn); | |
1336 | } | |
1337 | } | |
1338 | \f | |
252b5132 RH |
1339 | /* Main entry point to assemble one instruction. */ |
1340 | ||
1341 | void | |
5a49b8ac | 1342 | md_assemble (char *str) |
252b5132 RH |
1343 | { |
1344 | const struct sparc_opcode *insn; | |
a22b281c | 1345 | int special_case; |
252b5132 RH |
1346 | |
1347 | know (str); | |
a22b281c | 1348 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1349 | if (insn == NULL) |
1350 | return; | |
252b5132 RH |
1351 | |
1352 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1353 | unless the delay slot has been annulled. */ | |
b0825cc2 | 1354 | if (last_insn != NULL |
252b5132 RH |
1355 | && (insn->flags & F_FBR) != 0 |
1356 | && (last_insn->flags & F_DELAYED) != 0 | |
1357 | /* ??? This test isn't completely accurate. We assume anything with | |
1358 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1359 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1360 | || (last_opcode & ANNUL) == 0)) | |
1361 | as_warn (_("FP branch in delay slot")); | |
1362 | ||
1363 | /* SPARC before v9 requires a nop instruction between a floating | |
1364 | point instruction and a floating point branch. We insert one | |
1365 | automatically, with a warning. */ | |
1366 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1367 | && last_insn != NULL |
1368 | && (insn->flags & F_FBR) != 0 | |
1369 | && (last_insn->flags & F_FLOAT) != 0) | |
1370 | { | |
1371 | struct sparc_it nop_insn; | |
1372 | ||
1373 | nop_insn.opcode = NOP_INSN; | |
1374 | nop_insn.reloc = BFD_RELOC_NONE; | |
1375 | output_insn (insn, &nop_insn); | |
1376 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1377 | } | |
1378 | ||
a22b281c RH |
1379 | switch (special_case) |
1380 | { | |
1381 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1382 | /* Normal insn. */ |
a22b281c RH |
1383 | output_insn (insn, &the_insn); |
1384 | break; | |
252b5132 | 1385 | |
a22b281c RH |
1386 | case SPECIAL_CASE_SETSW: |
1387 | synthetize_setsw (insn); | |
1388 | break; | |
e0c6ed95 | 1389 | |
a22b281c RH |
1390 | case SPECIAL_CASE_SET: |
1391 | synthetize_setuw (insn); | |
1392 | break; | |
252b5132 | 1393 | |
a22b281c RH |
1394 | case SPECIAL_CASE_SETX: |
1395 | synthetize_setx (insn); | |
1396 | break; | |
e0c6ed95 | 1397 | |
a22b281c RH |
1398 | case SPECIAL_CASE_FDIV: |
1399 | { | |
1400 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1401 | |
a22b281c | 1402 | output_insn (insn, &the_insn); |
e0c6ed95 | 1403 | |
a22b281c RH |
1404 | /* According to information leaked from Sun, the "fdiv" instructions |
1405 | on early SPARC machines would produce incorrect results sometimes. | |
1406 | The workaround is to add an fmovs of the destination register to | |
1407 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1408 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1409 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1410 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1411 | output_insn (insn, &the_insn); | |
1412 | return; | |
1413 | } | |
e0c6ed95 | 1414 | |
a22b281c RH |
1415 | default: |
1416 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1417 | } |
1418 | } | |
1419 | ||
1420 | /* Subroutine of md_assemble to do the actual parsing. */ | |
1421 | ||
a22b281c | 1422 | static int |
5a49b8ac | 1423 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 RH |
1424 | { |
1425 | char *error_message = ""; | |
1426 | char *s; | |
1427 | const char *args; | |
1428 | char c; | |
1429 | const struct sparc_opcode *insn; | |
1430 | char *argsStart; | |
1431 | unsigned long opcode; | |
1432 | unsigned int mask = 0; | |
1433 | int match = 0; | |
1434 | int comma = 0; | |
1435 | int v9_arg_p; | |
a22b281c | 1436 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1437 | |
1438 | s = str; | |
3882b010 | 1439 | if (ISLOWER (*s)) |
252b5132 RH |
1440 | { |
1441 | do | |
1442 | ++s; | |
3882b010 | 1443 | while (ISLOWER (*s) || ISDIGIT (*s)); |
252b5132 RH |
1444 | } |
1445 | ||
1446 | switch (*s) | |
1447 | { | |
1448 | case '\0': | |
1449 | break; | |
1450 | ||
1451 | case ',': | |
1452 | comma = 1; | |
e0c6ed95 | 1453 | /* Fall through. */ |
252b5132 RH |
1454 | |
1455 | case ' ': | |
1456 | *s++ = '\0'; | |
1457 | break; | |
1458 | ||
1459 | default: | |
b0825cc2 DM |
1460 | as_bad (_("Unknown opcode: `%s'"), str); |
1461 | *pinsn = NULL; | |
1462 | return special_case; | |
252b5132 RH |
1463 | } |
1464 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1465 | *pinsn = insn; | |
1466 | if (insn == NULL) | |
1467 | { | |
1468 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1469 | return special_case; |
252b5132 RH |
1470 | } |
1471 | if (comma) | |
1472 | { | |
1473 | *--s = ','; | |
1474 | } | |
1475 | ||
1476 | argsStart = s; | |
1477 | for (;;) | |
1478 | { | |
1479 | opcode = insn->match; | |
1480 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1481 | the_insn.reloc = BFD_RELOC_NONE; | |
1482 | v9_arg_p = 0; | |
1483 | ||
e0c6ed95 AM |
1484 | /* Build the opcode, checking as we go to make sure that the |
1485 | operands match. */ | |
252b5132 RH |
1486 | for (args = insn->args;; ++args) |
1487 | { | |
1488 | switch (*args) | |
1489 | { | |
1490 | case 'K': | |
1491 | { | |
1492 | int kmask = 0; | |
1493 | ||
1494 | /* Parse a series of masks. */ | |
1495 | if (*s == '#') | |
1496 | { | |
1497 | while (*s == '#') | |
1498 | { | |
91d6fa6a | 1499 | int jmask; |
252b5132 RH |
1500 | |
1501 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1502 | &jmask)) |
252b5132 RH |
1503 | { |
1504 | error_message = _(": invalid membar mask name"); | |
1505 | goto error; | |
1506 | } | |
91d6fa6a | 1507 | kmask |= jmask; |
47926f60 KH |
1508 | while (*s == ' ') |
1509 | ++s; | |
252b5132 RH |
1510 | if (*s == '|' || *s == '+') |
1511 | ++s; | |
47926f60 KH |
1512 | while (*s == ' ') |
1513 | ++s; | |
252b5132 RH |
1514 | } |
1515 | } | |
1516 | else | |
1517 | { | |
1518 | if (! parse_const_expr_arg (&s, &kmask)) | |
1519 | { | |
1520 | error_message = _(": invalid membar mask expression"); | |
1521 | goto error; | |
1522 | } | |
1523 | if (kmask < 0 || kmask > 127) | |
1524 | { | |
1525 | error_message = _(": invalid membar mask number"); | |
1526 | goto error; | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | opcode |= MEMBAR (kmask); | |
1531 | continue; | |
1532 | } | |
1533 | ||
19f7b010 JJ |
1534 | case '3': |
1535 | { | |
1536 | int smask = 0; | |
1537 | ||
1538 | if (! parse_const_expr_arg (&s, &smask)) | |
1539 | { | |
1540 | error_message = _(": invalid siam mode expression"); | |
1541 | goto error; | |
1542 | } | |
1543 | if (smask < 0 || smask > 7) | |
1544 | { | |
1545 | error_message = _(": invalid siam mode number"); | |
1546 | goto error; | |
1547 | } | |
1548 | opcode |= smask; | |
1549 | continue; | |
1550 | } | |
1551 | ||
252b5132 RH |
1552 | case '*': |
1553 | { | |
1554 | int fcn = 0; | |
1555 | ||
1556 | /* Parse a prefetch function. */ | |
1557 | if (*s == '#') | |
1558 | { | |
1559 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1560 | { | |
1561 | error_message = _(": invalid prefetch function name"); | |
1562 | goto error; | |
1563 | } | |
1564 | } | |
1565 | else | |
1566 | { | |
1567 | if (! parse_const_expr_arg (&s, &fcn)) | |
1568 | { | |
1569 | error_message = _(": invalid prefetch function expression"); | |
1570 | goto error; | |
1571 | } | |
1572 | if (fcn < 0 || fcn > 31) | |
1573 | { | |
1574 | error_message = _(": invalid prefetch function number"); | |
1575 | goto error; | |
1576 | } | |
1577 | } | |
1578 | opcode |= RD (fcn); | |
1579 | continue; | |
1580 | } | |
1581 | ||
1582 | case '!': | |
1583 | case '?': | |
1584 | /* Parse a sparc64 privileged register. */ | |
1585 | if (*s == '%') | |
1586 | { | |
1587 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1588 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1589 | |
1590 | s += 1; | |
1591 | while (p->name[0] > s[0]) | |
1592 | p++; | |
1593 | while (p->name[0] == s[0]) | |
1594 | { | |
1595 | len = strlen (p->name); | |
1596 | if (strncmp (p->name, s, len) == 0) | |
1597 | break; | |
1598 | p++; | |
1599 | } | |
1600 | if (p->name[0] != s[0]) | |
1601 | { | |
1602 | error_message = _(": unrecognizable privileged register"); | |
1603 | goto error; | |
1604 | } | |
1605 | if (*args == '?') | |
1606 | opcode |= (p->regnum << 14); | |
1607 | else | |
1608 | opcode |= (p->regnum << 25); | |
1609 | s += len; | |
1610 | continue; | |
1611 | } | |
1612 | else | |
1613 | { | |
1614 | error_message = _(": unrecognizable privileged register"); | |
1615 | goto error; | |
1616 | } | |
1617 | ||
10156f83 DM |
1618 | case '$': |
1619 | case '%': | |
1620 | /* Parse a sparc64 hyperprivileged register. */ | |
1621 | if (*s == '%') | |
1622 | { | |
1623 | struct priv_reg_entry *p = hpriv_reg_table; | |
1624 | unsigned int len = 9999999; /* Init to make gcc happy. */ | |
1625 | ||
1626 | s += 1; | |
1627 | while (p->name[0] > s[0]) | |
1628 | p++; | |
1629 | while (p->name[0] == s[0]) | |
1630 | { | |
1631 | len = strlen (p->name); | |
1632 | if (strncmp (p->name, s, len) == 0) | |
1633 | break; | |
1634 | p++; | |
1635 | } | |
1636 | if (p->name[0] != s[0]) | |
1637 | { | |
1638 | error_message = _(": unrecognizable hyperprivileged register"); | |
1639 | goto error; | |
1640 | } | |
1641 | if (*args == '$') | |
1642 | opcode |= (p->regnum << 14); | |
1643 | else | |
1644 | opcode |= (p->regnum << 25); | |
1645 | s += len; | |
1646 | continue; | |
1647 | } | |
1648 | else | |
1649 | { | |
1650 | error_message = _(": unrecognizable hyperprivileged register"); | |
1651 | goto error; | |
1652 | } | |
1653 | ||
252b5132 RH |
1654 | case '_': |
1655 | case '/': | |
19f7b010 | 1656 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1657 | if (*s == '%') |
1658 | { | |
1659 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1660 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1661 | |
1662 | s += 1; | |
1663 | while (p->name[0] > s[0]) | |
1664 | p++; | |
1665 | while (p->name[0] == s[0]) | |
1666 | { | |
1667 | len = strlen (p->name); | |
1668 | if (strncmp (p->name, s, len) == 0) | |
1669 | break; | |
1670 | p++; | |
1671 | } | |
1672 | if (p->name[0] != s[0]) | |
1673 | { | |
19f7b010 | 1674 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1675 | goto error; |
1676 | } | |
1677 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1678 | { | |
1679 | error_message = _(": rd on write only ancillary state register"); | |
1680 | goto error; | |
e0c6ed95 | 1681 | } |
19f7b010 JJ |
1682 | if (p->regnum >= 24 |
1683 | && (insn->architecture | |
1684 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1685 | { | |
1686 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1687 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1688 | goto error; | |
1689 | } | |
252b5132 RH |
1690 | if (*args == '/') |
1691 | opcode |= (p->regnum << 14); | |
1692 | else | |
1693 | opcode |= (p->regnum << 25); | |
1694 | s += len; | |
1695 | continue; | |
1696 | } | |
1697 | else | |
1698 | { | |
19f7b010 | 1699 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1700 | goto error; |
1701 | } | |
1702 | ||
1703 | case 'M': | |
1704 | case 'm': | |
1705 | if (strncmp (s, "%asr", 4) == 0) | |
1706 | { | |
1707 | s += 4; | |
1708 | ||
3882b010 | 1709 | if (ISDIGIT (*s)) |
252b5132 RH |
1710 | { |
1711 | long num = 0; | |
1712 | ||
3882b010 | 1713 | while (ISDIGIT (*s)) |
252b5132 RH |
1714 | { |
1715 | num = num * 10 + *s - '0'; | |
1716 | ++s; | |
1717 | } | |
1718 | ||
1719 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1720 | { | |
1721 | if (num < 16 || 31 < num) | |
1722 | { | |
1723 | error_message = _(": asr number must be between 16 and 31"); | |
1724 | goto error; | |
1725 | } | |
1726 | } | |
1727 | else | |
1728 | { | |
1729 | if (num < 0 || 31 < num) | |
1730 | { | |
1731 | error_message = _(": asr number must be between 0 and 31"); | |
1732 | goto error; | |
1733 | } | |
1734 | } | |
1735 | ||
1736 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1737 | continue; | |
1738 | } | |
1739 | else | |
1740 | { | |
1741 | error_message = _(": expecting %asrN"); | |
1742 | goto error; | |
1743 | } | |
e0c6ed95 | 1744 | } /* if %asr */ |
252b5132 RH |
1745 | break; |
1746 | ||
1747 | case 'I': | |
1748 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1749 | goto immediate; | |
1750 | ||
1751 | case 'j': | |
1752 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1753 | goto immediate; | |
1754 | ||
1755 | case 'X': | |
1756 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1757 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1758 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1759 | else | |
1760 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1761 | /* These fields are unsigned, but for upward compatibility, | |
1762 | allow negative values as well. */ | |
1763 | goto immediate; | |
1764 | ||
1765 | case 'Y': | |
1766 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1767 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1768 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1769 | else | |
1770 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1771 | /* These fields are unsigned, but for upward compatibility, | |
1772 | allow negative values as well. */ | |
1773 | goto immediate; | |
1774 | ||
1775 | case 'k': | |
1776 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1777 | the_insn.pcrel = 1; | |
1778 | goto immediate; | |
1779 | ||
1780 | case 'G': | |
1781 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1782 | the_insn.pcrel = 1; | |
1783 | goto immediate; | |
1784 | ||
1785 | case 'N': | |
1786 | if (*s == 'p' && s[1] == 'n') | |
1787 | { | |
1788 | s += 2; | |
1789 | continue; | |
1790 | } | |
1791 | break; | |
1792 | ||
1793 | case 'T': | |
1794 | if (*s == 'p' && s[1] == 't') | |
1795 | { | |
1796 | s += 2; | |
1797 | continue; | |
1798 | } | |
1799 | break; | |
1800 | ||
1801 | case 'z': | |
1802 | if (*s == ' ') | |
1803 | { | |
1804 | ++s; | |
1805 | } | |
1806 | if (strncmp (s, "%icc", 4) == 0) | |
1807 | { | |
1808 | s += 4; | |
1809 | continue; | |
1810 | } | |
1811 | break; | |
1812 | ||
1813 | case 'Z': | |
1814 | if (*s == ' ') | |
1815 | { | |
1816 | ++s; | |
1817 | } | |
1818 | if (strncmp (s, "%xcc", 4) == 0) | |
1819 | { | |
1820 | s += 4; | |
1821 | continue; | |
1822 | } | |
1823 | break; | |
1824 | ||
1825 | case '6': | |
1826 | if (*s == ' ') | |
1827 | { | |
1828 | ++s; | |
1829 | } | |
1830 | if (strncmp (s, "%fcc0", 5) == 0) | |
1831 | { | |
1832 | s += 5; | |
1833 | continue; | |
1834 | } | |
1835 | break; | |
1836 | ||
1837 | case '7': | |
1838 | if (*s == ' ') | |
1839 | { | |
1840 | ++s; | |
1841 | } | |
1842 | if (strncmp (s, "%fcc1", 5) == 0) | |
1843 | { | |
1844 | s += 5; | |
1845 | continue; | |
1846 | } | |
1847 | break; | |
1848 | ||
1849 | case '8': | |
1850 | if (*s == ' ') | |
1851 | { | |
1852 | ++s; | |
1853 | } | |
1854 | if (strncmp (s, "%fcc2", 5) == 0) | |
1855 | { | |
1856 | s += 5; | |
1857 | continue; | |
1858 | } | |
1859 | break; | |
1860 | ||
1861 | case '9': | |
1862 | if (*s == ' ') | |
1863 | { | |
1864 | ++s; | |
1865 | } | |
1866 | if (strncmp (s, "%fcc3", 5) == 0) | |
1867 | { | |
1868 | s += 5; | |
1869 | continue; | |
1870 | } | |
1871 | break; | |
1872 | ||
1873 | case 'P': | |
1874 | if (strncmp (s, "%pc", 3) == 0) | |
1875 | { | |
1876 | s += 3; | |
1877 | continue; | |
1878 | } | |
1879 | break; | |
1880 | ||
1881 | case 'W': | |
1882 | if (strncmp (s, "%tick", 5) == 0) | |
1883 | { | |
1884 | s += 5; | |
1885 | continue; | |
1886 | } | |
1887 | break; | |
1888 | ||
e0c6ed95 | 1889 | case '\0': /* End of args. */ |
b9734f35 | 1890 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 1891 | { |
739f7f82 | 1892 | static const struct ops |
dfeb0666 | 1893 | { |
b9734f35 JJ |
1894 | /* The name as it appears in assembler. */ |
1895 | char *name; | |
1896 | /* strlen (name), precomputed for speed */ | |
1897 | int len; | |
1898 | /* The reloc this pseudo-op translates to. */ | |
1899 | int reloc; | |
739f7f82 DM |
1900 | /* 1 if tls call. */ |
1901 | int tls_call; | |
dfeb0666 | 1902 | } |
739f7f82 | 1903 | ops[] = |
dfeb0666 | 1904 | { |
b9734f35 JJ |
1905 | { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, |
1906 | { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, | |
1907 | { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, | |
1908 | { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, | |
1909 | { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, | |
1910 | { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, | |
1911 | { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, | |
dfeb0666 | 1912 | { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, |
739f7f82 | 1913 | { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, |
dfeb0666 | 1914 | { NULL, 0, 0, 0 } |
b9734f35 | 1915 | }; |
739f7f82 | 1916 | const struct ops *o; |
b9734f35 JJ |
1917 | char *s1; |
1918 | int npar = 0; | |
1919 | ||
739f7f82 | 1920 | for (o = ops; o->name; o++) |
b9734f35 JJ |
1921 | if (strncmp (s + 2, o->name, o->len) == 0) |
1922 | break; | |
1923 | if (o->name == NULL) | |
1924 | break; | |
1925 | ||
1926 | if (s[o->len + 2] != '(') | |
1927 | { | |
1928 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1929 | return special_case; | |
1930 | } | |
1931 | ||
739f7f82 | 1932 | if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) |
b9734f35 JJ |
1933 | { |
1934 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
1935 | o->name); | |
1936 | return special_case; | |
1937 | } | |
1938 | ||
739f7f82 | 1939 | if (o->tls_call |
b9734f35 JJ |
1940 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
1941 | || the_insn.exp.X_add_number != 0 | |
1942 | || the_insn.exp.X_add_symbol | |
1943 | != symbol_find_or_make ("__tls_get_addr"))) | |
1944 | { | |
1945 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
1946 | o->name); | |
1947 | return special_case; | |
1948 | } | |
1949 | ||
1950 | the_insn.reloc = o->reloc; | |
1951 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); | |
1952 | s += o->len + 3; | |
1953 | ||
1954 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
1955 | if (*s1 == '(') | |
1956 | npar++; | |
1957 | else if (*s1 == ')') | |
1958 | { | |
1959 | if (!npar) | |
1960 | break; | |
1961 | npar--; | |
1962 | } | |
1963 | ||
1964 | if (*s1 != ')') | |
1965 | { | |
1966 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1967 | return special_case; | |
1968 | } | |
1969 | ||
1970 | *s1 = '\0'; | |
1971 | (void) get_expression (s); | |
1972 | *s1 = ')'; | |
1973 | s = s1 + 1; | |
252b5132 | 1974 | } |
b9734f35 JJ |
1975 | if (*s == '\0') |
1976 | match = 1; | |
252b5132 RH |
1977 | break; |
1978 | ||
1979 | case '+': | |
1980 | if (*s == '+') | |
1981 | { | |
1982 | ++s; | |
1983 | continue; | |
1984 | } | |
1985 | if (*s == '-') | |
1986 | { | |
1987 | continue; | |
1988 | } | |
1989 | break; | |
1990 | ||
e0c6ed95 | 1991 | case '[': /* These must match exactly. */ |
252b5132 RH |
1992 | case ']': |
1993 | case ',': | |
1994 | case ' ': | |
1995 | if (*s++ == *args) | |
1996 | continue; | |
1997 | break; | |
1998 | ||
e0c6ed95 | 1999 | case '#': /* Must be at least one digit. */ |
3882b010 | 2000 | if (ISDIGIT (*s++)) |
252b5132 | 2001 | { |
3882b010 | 2002 | while (ISDIGIT (*s)) |
252b5132 RH |
2003 | { |
2004 | ++s; | |
2005 | } | |
2006 | continue; | |
2007 | } | |
2008 | break; | |
2009 | ||
e0c6ed95 | 2010 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2011 | if (strncmp (s, "%csr", 4) == 0) |
2012 | { | |
2013 | s += 4; | |
2014 | continue; | |
2015 | } | |
2016 | break; | |
2017 | ||
e0c6ed95 | 2018 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2019 | case 'c': |
2020 | case 'D': | |
3882b010 | 2021 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2022 | { |
2023 | mask = *s++; | |
3882b010 | 2024 | if (ISDIGIT (*s)) |
252b5132 RH |
2025 | { |
2026 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2027 | if (mask >= 32) | |
2028 | { | |
2029 | break; | |
2030 | } | |
2031 | } | |
2032 | else | |
2033 | { | |
2034 | mask -= '0'; | |
2035 | } | |
2036 | switch (*args) | |
2037 | { | |
2038 | ||
2039 | case 'b': | |
2040 | opcode |= mask << 14; | |
2041 | continue; | |
2042 | ||
2043 | case 'c': | |
2044 | opcode |= mask; | |
2045 | continue; | |
2046 | ||
2047 | case 'D': | |
2048 | opcode |= mask << 25; | |
2049 | continue; | |
2050 | } | |
2051 | } | |
2052 | break; | |
2053 | ||
2054 | case 'r': /* next operand must be a register */ | |
2055 | case 'O': | |
2056 | case '1': | |
2057 | case '2': | |
2058 | case 'd': | |
2059 | if (*s++ == '%') | |
2060 | { | |
2061 | switch (c = *s++) | |
2062 | { | |
2063 | ||
2064 | case 'f': /* frame pointer */ | |
2065 | if (*s++ == 'p') | |
2066 | { | |
2067 | mask = 0x1e; | |
2068 | break; | |
2069 | } | |
2070 | goto error; | |
2071 | ||
2072 | case 'g': /* global register */ | |
a22b281c RH |
2073 | c = *s++; |
2074 | if (isoctal (c)) | |
252b5132 RH |
2075 | { |
2076 | mask = c - '0'; | |
2077 | break; | |
2078 | } | |
2079 | goto error; | |
2080 | ||
2081 | case 'i': /* in register */ | |
a22b281c RH |
2082 | c = *s++; |
2083 | if (isoctal (c)) | |
252b5132 RH |
2084 | { |
2085 | mask = c - '0' + 24; | |
2086 | break; | |
2087 | } | |
2088 | goto error; | |
2089 | ||
2090 | case 'l': /* local register */ | |
a22b281c RH |
2091 | c = *s++; |
2092 | if (isoctal (c)) | |
252b5132 RH |
2093 | { |
2094 | mask = (c - '0' + 16); | |
2095 | break; | |
2096 | } | |
2097 | goto error; | |
2098 | ||
2099 | case 'o': /* out register */ | |
a22b281c RH |
2100 | c = *s++; |
2101 | if (isoctal (c)) | |
252b5132 RH |
2102 | { |
2103 | mask = (c - '0' + 8); | |
2104 | break; | |
2105 | } | |
2106 | goto error; | |
2107 | ||
2108 | case 's': /* stack pointer */ | |
2109 | if (*s++ == 'p') | |
2110 | { | |
2111 | mask = 0xe; | |
2112 | break; | |
2113 | } | |
2114 | goto error; | |
2115 | ||
2116 | case 'r': /* any register */ | |
3882b010 | 2117 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2118 | { |
2119 | goto error; | |
2120 | } | |
2121 | /* FALLTHROUGH */ | |
2122 | case '0': | |
2123 | case '1': | |
2124 | case '2': | |
2125 | case '3': | |
2126 | case '4': | |
2127 | case '5': | |
2128 | case '6': | |
2129 | case '7': | |
2130 | case '8': | |
2131 | case '9': | |
3882b010 | 2132 | if (ISDIGIT (*s)) |
252b5132 RH |
2133 | { |
2134 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2135 | { | |
2136 | goto error; | |
2137 | } | |
2138 | } | |
2139 | else | |
2140 | { | |
2141 | c -= '0'; | |
2142 | } | |
2143 | mask = c; | |
2144 | break; | |
2145 | ||
2146 | default: | |
2147 | goto error; | |
2148 | } | |
2149 | ||
6d8809aa | 2150 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2151 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2152 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2153 | |
252b5132 RH |
2154 | /* Got the register, now figure out where |
2155 | it goes in the opcode. */ | |
2156 | switch (*args) | |
2157 | { | |
2158 | case '1': | |
2159 | opcode |= mask << 14; | |
2160 | continue; | |
2161 | ||
2162 | case '2': | |
2163 | opcode |= mask; | |
2164 | continue; | |
2165 | ||
2166 | case 'd': | |
2167 | opcode |= mask << 25; | |
2168 | continue; | |
2169 | ||
2170 | case 'r': | |
2171 | opcode |= (mask << 25) | (mask << 14); | |
2172 | continue; | |
2173 | ||
2174 | case 'O': | |
2175 | opcode |= (mask << 25) | (mask << 0); | |
2176 | continue; | |
2177 | } | |
2178 | } | |
2179 | break; | |
2180 | ||
2181 | case 'e': /* next operand is a floating point register */ | |
2182 | case 'v': | |
2183 | case 'V': | |
2184 | ||
2185 | case 'f': | |
2186 | case 'B': | |
2187 | case 'R': | |
2188 | ||
ea783ef3 DM |
2189 | case '4': |
2190 | case '5': | |
2191 | ||
252b5132 RH |
2192 | case 'g': |
2193 | case 'H': | |
2194 | case 'J': | |
2195 | { | |
2196 | char format; | |
2197 | ||
2198 | if (*s++ == '%' | |
2199 | && ((format = *s) == 'f') | |
3882b010 | 2200 | && ISDIGIT (*++s)) |
252b5132 | 2201 | { |
3882b010 | 2202 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2203 | { |
2204 | mask = 10 * mask + (*s - '0'); | |
2205 | } /* read the number */ | |
2206 | ||
2207 | if ((*args == 'v' | |
2208 | || *args == 'B' | |
ea783ef3 | 2209 | || *args == '5' |
252b5132 RH |
2210 | || *args == 'H') |
2211 | && (mask & 1)) | |
2212 | { | |
2213 | break; | |
2214 | } /* register must be even numbered */ | |
2215 | ||
2216 | if ((*args == 'V' | |
2217 | || *args == 'R' | |
2218 | || *args == 'J') | |
2219 | && (mask & 3)) | |
2220 | { | |
2221 | break; | |
2222 | } /* register must be multiple of 4 */ | |
2223 | ||
2224 | if (mask >= 64) | |
2225 | { | |
2226 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2227 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2228 | else | |
2229 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2230 | goto error; | |
2231 | } /* on error */ | |
2232 | else if (mask >= 32) | |
2233 | { | |
2234 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2235 | { | |
26664553 JJ |
2236 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2237 | { | |
2238 | error_message | |
2239 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2240 | goto error; | |
2241 | } | |
252b5132 RH |
2242 | v9_arg_p = 1; |
2243 | mask -= 31; /* wrap high bit */ | |
2244 | } | |
2245 | else | |
2246 | { | |
2247 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2248 | goto error; | |
2249 | } | |
2250 | } | |
2251 | } | |
2252 | else | |
2253 | { | |
2254 | break; | |
ab3e48dc | 2255 | } /* if not an 'f' register. */ |
252b5132 RH |
2256 | |
2257 | switch (*args) | |
2258 | { | |
2259 | case 'v': | |
2260 | case 'V': | |
2261 | case 'e': | |
2262 | opcode |= RS1 (mask); | |
2263 | continue; | |
2264 | ||
252b5132 RH |
2265 | case 'f': |
2266 | case 'B': | |
2267 | case 'R': | |
2268 | opcode |= RS2 (mask); | |
2269 | continue; | |
2270 | ||
ea783ef3 DM |
2271 | case '4': |
2272 | case '5': | |
2273 | opcode |= RS3 (mask); | |
2274 | continue; | |
2275 | ||
252b5132 RH |
2276 | case 'g': |
2277 | case 'H': | |
2278 | case 'J': | |
2279 | opcode |= RD (mask); | |
2280 | continue; | |
ab3e48dc | 2281 | } /* Pack it in. */ |
252b5132 RH |
2282 | |
2283 | know (0); | |
2284 | break; | |
ab3e48dc | 2285 | } /* float arg */ |
252b5132 RH |
2286 | |
2287 | case 'F': | |
2288 | if (strncmp (s, "%fsr", 4) == 0) | |
2289 | { | |
2290 | s += 4; | |
2291 | continue; | |
2292 | } | |
2293 | break; | |
2294 | ||
ea783ef3 DM |
2295 | case '(': |
2296 | if (strncmp (s, "%efsr", 5) == 0) | |
2297 | { | |
2298 | s += 5; | |
2299 | continue; | |
2300 | } | |
2301 | break; | |
2302 | ||
ab3e48dc KH |
2303 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2304 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2305 | goto immediate; |
2306 | ||
ab3e48dc | 2307 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2308 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2309 | the_insn.pcrel = 1; | |
2310 | goto immediate; | |
2311 | ||
ab3e48dc | 2312 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2313 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2314 | the_insn.pcrel = 1; | |
2315 | goto immediate; | |
2316 | ||
63fab58c | 2317 | case 'h': |
ab3e48dc | 2318 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2319 | the_insn.reloc = BFD_RELOC_SPARC22; |
2320 | goto immediate; | |
2321 | ||
ab3e48dc | 2322 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2323 | the_insn.reloc = BFD_RELOC_SPARC13; |
2324 | ||
2325 | /* fallthrough */ | |
2326 | ||
2327 | immediate: | |
2328 | if (*s == ' ') | |
2329 | s++; | |
2330 | ||
cf9a1301 RH |
2331 | { |
2332 | char *s1; | |
2333 | char *op_arg = NULL; | |
30eb9c17 | 2334 | static expressionS op_exp; |
cf9a1301 RH |
2335 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2336 | ||
2337 | /* Check for %hi, etc. */ | |
2338 | if (*s == '%') | |
2339 | { | |
2340 | static const struct ops { | |
2341 | /* The name as it appears in assembler. */ | |
2342 | char *name; | |
2343 | /* strlen (name), precomputed for speed */ | |
2344 | int len; | |
2345 | /* The reloc this pseudo-op translates to. */ | |
2346 | int reloc; | |
2347 | /* Non-zero if for v9 only. */ | |
2348 | int v9_p; | |
2349 | /* Non-zero if can be used in pc-relative contexts. */ | |
2350 | int pcrel_p;/*FIXME:wip*/ | |
2351 | } ops[] = { | |
2352 | /* hix/lox must appear before hi/lo so %hix won't be | |
2353 | mistaken for %hi. */ | |
2354 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2355 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2356 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2357 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
14865d76 DM |
2358 | { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, |
2359 | { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, | |
cf9a1301 RH |
2360 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, |
2361 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2362 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2363 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
2364 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2365 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2366 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2367 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
b9734f35 JJ |
2368 | { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, |
2369 | { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, | |
2370 | { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, | |
2371 | { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, | |
2372 | { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, | |
2373 | 0 }, | |
2374 | { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, | |
2375 | 0 }, | |
2376 | { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, | |
2377 | { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, | |
2378 | { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, | |
2379 | { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, | |
739f7f82 DM |
2380 | { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, |
2381 | 0, 0 }, | |
2382 | { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, | |
2383 | 0, 0 }, | |
c2158c24 | 2384 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2385 | }; |
2386 | const struct ops *o; | |
e0c6ed95 | 2387 | |
cf9a1301 RH |
2388 | for (o = ops; o->name; o++) |
2389 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2390 | break; | |
2391 | if (o->name == NULL) | |
252b5132 | 2392 | break; |
e0c6ed95 | 2393 | |
cf9a1301 RH |
2394 | if (s[o->len + 1] != '(') |
2395 | { | |
2396 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2397 | return special_case; |
cf9a1301 | 2398 | } |
252b5132 | 2399 | |
cf9a1301 RH |
2400 | op_arg = o->name; |
2401 | the_insn.reloc = o->reloc; | |
2402 | s += o->len + 2; | |
2403 | v9_arg_p = o->v9_p; | |
2404 | } | |
2405 | ||
2406 | /* Note that if the get_expression() fails, we will still | |
2407 | have created U entries in the symbol table for the | |
2408 | 'symbols' in the input string. Try not to create U | |
2409 | symbols for registers, etc. */ | |
252b5132 | 2410 | |
252b5132 RH |
2411 | /* This stuff checks to see if the expression ends in |
2412 | +%reg. If it does, it removes the register from | |
2413 | the expression, and re-sets 's' to point to the | |
2414 | right place. */ | |
2415 | ||
cf9a1301 RH |
2416 | if (op_arg) |
2417 | { | |
2418 | int npar = 0; | |
2419 | ||
2420 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2421 | if (*s1 == '(') | |
2422 | npar++; | |
2423 | else if (*s1 == ')') | |
2424 | { | |
2425 | if (!npar) | |
2426 | break; | |
2427 | npar--; | |
2428 | } | |
2429 | ||
2430 | if (*s1 != ')') | |
2431 | { | |
2432 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2433 | return special_case; |
cf9a1301 | 2434 | } |
e0c6ed95 | 2435 | |
cf9a1301 RH |
2436 | *s1 = '\0'; |
2437 | (void) get_expression (s); | |
2438 | *s1 = ')'; | |
2439 | s = s1 + 1; | |
2440 | if (*s == ',' || *s == ']' || !*s) | |
2441 | continue; | |
2442 | if (*s != '+' && *s != '-') | |
2443 | { | |
2444 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2445 | return special_case; |
cf9a1301 RH |
2446 | } |
2447 | *s1 = '0'; | |
2448 | s = s1; | |
2449 | op_exp = the_insn.exp; | |
e0c6ed95 | 2450 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2451 | } |
252b5132 | 2452 | |
e0c6ed95 AM |
2453 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2454 | ; | |
252b5132 | 2455 | |
3882b010 | 2456 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2457 | { |
2458 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2459 | s1 -= 3; |
f124dd4f | 2460 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2461 | s1 -= 4; |
f124dd4f DM |
2462 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2463 | s1 -= 5; | |
cf9a1301 RH |
2464 | else |
2465 | s1 = NULL; | |
2466 | if (s1) | |
252b5132 | 2467 | { |
252b5132 | 2468 | *s1 = '\0'; |
1eb7027c RH |
2469 | if (op_arg && s1 == s + 1) |
2470 | the_insn.exp.X_op = O_absent; | |
2471 | else | |
2472 | (void) get_expression (s); | |
252b5132 | 2473 | *s1 = '+'; |
cf9a1301 RH |
2474 | if (op_arg) |
2475 | *s = ')'; | |
252b5132 | 2476 | s = s1; |
252b5132 | 2477 | } |
cf9a1301 RH |
2478 | } |
2479 | else | |
2480 | s1 = NULL; | |
2481 | ||
2482 | if (!s1) | |
2483 | { | |
2484 | (void) get_expression (s); | |
2485 | if (op_arg) | |
2486 | *s = ')'; | |
2487 | s = expr_end; | |
2488 | } | |
2489 | ||
2490 | if (op_arg) | |
2491 | { | |
2492 | the_insn.exp2 = the_insn.exp; | |
2493 | the_insn.exp = op_exp; | |
2494 | if (the_insn.exp2.X_op == O_absent) | |
2495 | the_insn.exp2.X_op = O_illegal; | |
2496 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2497 | { |
cf9a1301 RH |
2498 | the_insn.exp = the_insn.exp2; |
2499 | the_insn.exp2.X_op = O_illegal; | |
2500 | } | |
2501 | else if (the_insn.exp.X_op == O_constant) | |
2502 | { | |
2503 | valueT val = the_insn.exp.X_add_number; | |
2504 | switch (the_insn.reloc) | |
2505 | { | |
1b50c718 ILT |
2506 | default: |
2507 | break; | |
2508 | ||
cf9a1301 RH |
2509 | case BFD_RELOC_SPARC_HH22: |
2510 | val = BSR (val, 32); | |
e0c6ed95 | 2511 | /* Fall through. */ |
cf9a1301 RH |
2512 | |
2513 | case BFD_RELOC_SPARC_LM22: | |
2514 | case BFD_RELOC_HI22: | |
2515 | val = (val >> 10) & 0x3fffff; | |
2516 | break; | |
2517 | ||
2518 | case BFD_RELOC_SPARC_HM10: | |
2519 | val = BSR (val, 32); | |
e0c6ed95 | 2520 | /* Fall through. */ |
cf9a1301 RH |
2521 | |
2522 | case BFD_RELOC_LO10: | |
2523 | val &= 0x3ff; | |
2524 | break; | |
2525 | ||
2526 | case BFD_RELOC_SPARC_H44: | |
2527 | val >>= 22; | |
2528 | val &= 0x3fffff; | |
2529 | break; | |
2530 | ||
2531 | case BFD_RELOC_SPARC_M44: | |
2532 | val >>= 12; | |
2533 | val &= 0x3ff; | |
2534 | break; | |
2535 | ||
2536 | case BFD_RELOC_SPARC_L44: | |
2537 | val &= 0xfff; | |
2538 | break; | |
2539 | ||
2540 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2541 | val = ~val; |
cf9a1301 RH |
2542 | val = (val >> 10) & 0x3fffff; |
2543 | break; | |
2544 | ||
2545 | case BFD_RELOC_SPARC_LOX10: | |
2546 | val = (val & 0x3ff) | 0x1c00; | |
2547 | break; | |
2548 | } | |
2549 | the_insn.exp = the_insn.exp2; | |
2550 | the_insn.exp.X_add_number += val; | |
2551 | the_insn.exp2.X_op = O_illegal; | |
2552 | the_insn.reloc = old_reloc; | |
2553 | } | |
2554 | else if (the_insn.exp2.X_op != O_constant) | |
2555 | { | |
2556 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2557 | return special_case; |
cf9a1301 RH |
2558 | } |
2559 | else | |
2560 | { | |
dabe3bbc | 2561 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2562 | || the_insn.reloc != BFD_RELOC_LO10 |
2563 | || sparc_arch_size != 64 | |
2564 | || sparc_pic_code) | |
2565 | { | |
2566 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2567 | return special_case; |
cf9a1301 RH |
2568 | } |
2569 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2570 | } |
2571 | } | |
2572 | } | |
252b5132 RH |
2573 | /* Check for constants that don't require emitting a reloc. */ |
2574 | if (the_insn.exp.X_op == O_constant | |
2575 | && the_insn.exp.X_add_symbol == 0 | |
2576 | && the_insn.exp.X_op_symbol == 0) | |
2577 | { | |
2578 | /* For pc-relative call instructions, we reject | |
2579 | constants to get better code. */ | |
2580 | if (the_insn.pcrel | |
2581 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2582 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2583 | { | |
2584 | error_message = _(": PC-relative operand can't be a constant"); | |
2585 | goto error; | |
2586 | } | |
2587 | ||
b9734f35 JJ |
2588 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2589 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2590 | { | |
2591 | error_message = _(": TLS operand can't be a constant"); | |
2592 | goto error; | |
2593 | } | |
2594 | ||
55cf6793 | 2595 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2596 | and bfd_install_relocation. |
2597 | ??? It would be preferable to install the constants | |
2598 | into the insn here and save having to create a fixS | |
2599 | for each one. There already exists code to handle | |
55cf6793 | 2600 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2601 | bfd_install_relocation) so duplicating all that code |
2602 | here isn't right. */ | |
2603 | } | |
2604 | ||
2605 | continue; | |
2606 | ||
2607 | case 'a': | |
2608 | if (*s++ == 'a') | |
2609 | { | |
2610 | opcode |= ANNUL; | |
2611 | continue; | |
2612 | } | |
2613 | break; | |
2614 | ||
2615 | case 'A': | |
2616 | { | |
2617 | int asi = 0; | |
2618 | ||
2619 | /* Parse an asi. */ | |
2620 | if (*s == '#') | |
2621 | { | |
2622 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2623 | { | |
2624 | error_message = _(": invalid ASI name"); | |
2625 | goto error; | |
2626 | } | |
2627 | } | |
2628 | else | |
2629 | { | |
2630 | if (! parse_const_expr_arg (&s, &asi)) | |
2631 | { | |
2632 | error_message = _(": invalid ASI expression"); | |
2633 | goto error; | |
2634 | } | |
2635 | if (asi < 0 || asi > 255) | |
2636 | { | |
2637 | error_message = _(": invalid ASI number"); | |
2638 | goto error; | |
2639 | } | |
2640 | } | |
2641 | opcode |= ASI (asi); | |
2642 | continue; | |
e0c6ed95 | 2643 | } /* Alternate space. */ |
252b5132 RH |
2644 | |
2645 | case 'p': | |
2646 | if (strncmp (s, "%psr", 4) == 0) | |
2647 | { | |
2648 | s += 4; | |
2649 | continue; | |
2650 | } | |
2651 | break; | |
2652 | ||
e0c6ed95 | 2653 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2654 | if (strncmp (s, "%fq", 3) == 0) |
2655 | { | |
2656 | s += 3; | |
2657 | continue; | |
2658 | } | |
2659 | break; | |
2660 | ||
e0c6ed95 | 2661 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2662 | if (strncmp (s, "%cq", 3) == 0) |
2663 | { | |
2664 | s += 3; | |
2665 | continue; | |
2666 | } | |
2667 | break; | |
2668 | ||
2669 | case 'S': | |
2670 | if (strcmp (str, "set") == 0 | |
2671 | || strcmp (str, "setuw") == 0) | |
2672 | { | |
2673 | special_case = SPECIAL_CASE_SET; | |
2674 | continue; | |
2675 | } | |
2676 | else if (strcmp (str, "setsw") == 0) | |
2677 | { | |
2678 | special_case = SPECIAL_CASE_SETSW; | |
2679 | continue; | |
2680 | } | |
2681 | else if (strcmp (str, "setx") == 0) | |
2682 | { | |
2683 | special_case = SPECIAL_CASE_SETX; | |
2684 | continue; | |
2685 | } | |
2686 | else if (strncmp (str, "fdiv", 4) == 0) | |
2687 | { | |
2688 | special_case = SPECIAL_CASE_FDIV; | |
2689 | continue; | |
2690 | } | |
2691 | break; | |
2692 | ||
2693 | case 'o': | |
2694 | if (strncmp (s, "%asi", 4) != 0) | |
2695 | break; | |
2696 | s += 4; | |
2697 | continue; | |
2698 | ||
2699 | case 's': | |
2700 | if (strncmp (s, "%fprs", 5) != 0) | |
2701 | break; | |
2702 | s += 5; | |
2703 | continue; | |
2704 | ||
2705 | case 'E': | |
2706 | if (strncmp (s, "%ccr", 4) != 0) | |
2707 | break; | |
2708 | s += 4; | |
2709 | continue; | |
2710 | ||
2711 | case 't': | |
2712 | if (strncmp (s, "%tbr", 4) != 0) | |
2713 | break; | |
2714 | s += 4; | |
2715 | continue; | |
2716 | ||
2717 | case 'w': | |
2718 | if (strncmp (s, "%wim", 4) != 0) | |
2719 | break; | |
2720 | s += 4; | |
2721 | continue; | |
2722 | ||
2723 | case 'x': | |
2724 | { | |
2725 | char *push = input_line_pointer; | |
2726 | expressionS e; | |
2727 | ||
2728 | input_line_pointer = s; | |
2729 | expression (&e); | |
2730 | if (e.X_op == O_constant) | |
2731 | { | |
2732 | int n = e.X_add_number; | |
2733 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2734 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2735 | else | |
2736 | opcode |= e.X_add_number << 5; | |
2737 | } | |
2738 | else | |
2739 | as_bad (_("non-immediate OPF operand, ignored")); | |
2740 | s = input_line_pointer; | |
2741 | input_line_pointer = push; | |
2742 | continue; | |
2743 | } | |
2744 | ||
2745 | case 'y': | |
2746 | if (strncmp (s, "%y", 2) != 0) | |
2747 | break; | |
2748 | s += 2; | |
2749 | continue; | |
2750 | ||
2751 | case 'u': | |
2752 | case 'U': | |
2753 | { | |
2754 | /* Parse a sparclet cpreg. */ | |
2755 | int cpreg; | |
2756 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2757 | { | |
2758 | error_message = _(": invalid cpreg name"); | |
2759 | goto error; | |
2760 | } | |
2761 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2762 | continue; | |
2763 | } | |
2764 | ||
2765 | default: | |
2766 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2767 | } /* switch on arg code. */ |
252b5132 RH |
2768 | |
2769 | /* Break out of for() loop. */ | |
2770 | break; | |
e0c6ed95 | 2771 | } /* For each arg that we expect. */ |
252b5132 RH |
2772 | |
2773 | error: | |
2774 | if (match == 0) | |
2775 | { | |
e0c6ed95 | 2776 | /* Args don't match. */ |
252b5132 RH |
2777 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2778 | && (insn->name == insn[1].name | |
2779 | || !strcmp (insn->name, insn[1].name))) | |
2780 | { | |
2781 | ++insn; | |
2782 | s = argsStart; | |
2783 | continue; | |
2784 | } | |
2785 | else | |
2786 | { | |
2787 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2788 | return special_case; |
252b5132 RH |
2789 | } |
2790 | } | |
2791 | else | |
2792 | { | |
e0c6ed95 | 2793 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 | 2794 | int needed_arch_mask = insn->architecture; |
9e8c70f9 DM |
2795 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
2796 | int hwcaps = insn->flags & F_HWCAP_MASK; | |
252b5132 | 2797 | |
9e8c70f9 DM |
2798 | if (hwcaps) |
2799 | hwcap_seen |= hwcaps; | |
2800 | #endif | |
252b5132 RH |
2801 | if (v9_arg_p) |
2802 | { | |
19f7b010 JJ |
2803 | needed_arch_mask &= |
2804 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
2805 | if (! needed_arch_mask) | |
2806 | needed_arch_mask = | |
2807 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
2808 | } |
2809 | ||
e0c6ed95 AM |
2810 | if (needed_arch_mask |
2811 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2812 | /* OK. */ | |
2813 | ; | |
252b5132 | 2814 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
2815 | else if (needed_arch_mask |
2816 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
2817 | { |
2818 | enum sparc_opcode_arch_val needed_architecture = | |
2819 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2820 | & needed_arch_mask); | |
2821 | ||
9c2799c2 | 2822 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
2823 | if (warn_on_bump |
2824 | && needed_architecture > warn_after_architecture) | |
2825 | { | |
2826 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2827 | sparc_opcode_archs[current_architecture].name, | |
2828 | sparc_opcode_archs[needed_architecture].name, | |
2829 | str); | |
2830 | warn_after_architecture = needed_architecture; | |
2831 | } | |
2832 | current_architecture = needed_architecture; | |
2833 | } | |
2834 | /* Conflict. */ | |
2835 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2836 | the opcode table is the one we want and it is supported? | |
2837 | It is possible to arrange the table today so that this can't | |
2838 | happen but what about tomorrow? */ | |
2839 | else | |
2840 | { | |
e0c6ed95 | 2841 | int arch, printed_one_p = 0; |
252b5132 RH |
2842 | char *p; |
2843 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2844 | ||
2845 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 2846 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
2847 | p = required_archs; |
2848 | arch = sparc_ffs (needed_arch_mask); | |
2849 | while ((1 << arch) <= needed_arch_mask) | |
2850 | { | |
2851 | if ((1 << arch) & needed_arch_mask) | |
2852 | { | |
2853 | if (printed_one_p) | |
2854 | *p++ = '|'; | |
2855 | strcpy (p, sparc_opcode_archs[arch].name); | |
2856 | p += strlen (p); | |
2857 | printed_one_p = 1; | |
2858 | } | |
2859 | ++arch; | |
2860 | } | |
2861 | ||
2862 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2863 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2864 | required_archs, | |
2865 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2866 | return special_case; |
252b5132 | 2867 | } |
e0c6ed95 | 2868 | } /* If no match. */ |
252b5132 RH |
2869 | |
2870 | break; | |
e0c6ed95 | 2871 | } /* Forever looking for a match. */ |
252b5132 RH |
2872 | |
2873 | the_insn.opcode = opcode; | |
a22b281c | 2874 | return special_case; |
252b5132 RH |
2875 | } |
2876 | ||
2877 | /* Parse an argument that can be expressed as a keyword. | |
2878 | (eg: #StoreStore or %ccfr). | |
2879 | The result is a boolean indicating success. | |
2880 | If successful, INPUT_POINTER is updated. */ | |
2881 | ||
2882 | static int | |
5a49b8ac AM |
2883 | parse_keyword_arg (int (*lookup_fn) (const char *), |
2884 | char **input_pointerP, | |
2885 | int *valueP) | |
252b5132 RH |
2886 | { |
2887 | int value; | |
2888 | char c, *p, *q; | |
2889 | ||
2890 | p = *input_pointerP; | |
2891 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 2892 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
2893 | ++q) |
2894 | continue; | |
2895 | c = *q; | |
2896 | *q = 0; | |
2897 | value = (*lookup_fn) (p); | |
2898 | *q = c; | |
2899 | if (value == -1) | |
2900 | return 0; | |
2901 | *valueP = value; | |
2902 | *input_pointerP = q; | |
2903 | return 1; | |
2904 | } | |
2905 | ||
2906 | /* Parse an argument that is a constant expression. | |
2907 | The result is a boolean indicating success. */ | |
2908 | ||
2909 | static int | |
5a49b8ac | 2910 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
2911 | { |
2912 | char *save = input_line_pointer; | |
2913 | expressionS exp; | |
2914 | ||
2915 | input_line_pointer = *input_pointerP; | |
2916 | /* The next expression may be something other than a constant | |
2917 | (say if we're not processing the right variant of the insn). | |
2918 | Don't call expression unless we're sure it will succeed as it will | |
2919 | signal an error (which we want to defer until later). */ | |
2920 | /* FIXME: It might be better to define md_operand and have it recognize | |
2921 | things like %asi, etc. but continuing that route through to the end | |
2922 | is a lot of work. */ | |
2923 | if (*input_line_pointer == '%') | |
2924 | { | |
2925 | input_line_pointer = save; | |
2926 | return 0; | |
2927 | } | |
2928 | expression (&exp); | |
2929 | *input_pointerP = input_line_pointer; | |
2930 | input_line_pointer = save; | |
2931 | if (exp.X_op != O_constant) | |
2932 | return 0; | |
2933 | *valueP = exp.X_add_number; | |
2934 | return 1; | |
2935 | } | |
2936 | ||
2937 | /* Subroutine of sparc_ip to parse an expression. */ | |
2938 | ||
2939 | static int | |
5a49b8ac | 2940 | get_expression (char *str) |
252b5132 RH |
2941 | { |
2942 | char *save_in; | |
2943 | segT seg; | |
2944 | ||
2945 | save_in = input_line_pointer; | |
2946 | input_line_pointer = str; | |
2947 | seg = expression (&the_insn.exp); | |
2948 | if (seg != absolute_section | |
2949 | && seg != text_section | |
2950 | && seg != data_section | |
2951 | && seg != bss_section | |
2952 | && seg != undefined_section) | |
2953 | { | |
2954 | the_insn.error = _("bad segment"); | |
2955 | expr_end = input_line_pointer; | |
2956 | input_line_pointer = save_in; | |
2957 | return 1; | |
2958 | } | |
2959 | expr_end = input_line_pointer; | |
2960 | input_line_pointer = save_in; | |
2961 | return 0; | |
2962 | } | |
2963 | ||
2964 | /* Subroutine of md_assemble to output one insn. */ | |
2965 | ||
2966 | static void | |
91d6fa6a | 2967 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
2968 | { |
2969 | char *toP = frag_more (4); | |
2970 | ||
e0c6ed95 | 2971 | /* Put out the opcode. */ |
252b5132 | 2972 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 2973 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 2974 | else |
91d6fa6a | 2975 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 2976 | |
e0c6ed95 | 2977 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 2978 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 2979 | { |
e0c6ed95 AM |
2980 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
2981 | (toP - frag_now->fr_literal), /* Where. */ | |
2982 | 4, /* Size. */ | |
91d6fa6a NC |
2983 | &theinsn->exp, |
2984 | theinsn->pcrel, | |
2985 | theinsn->reloc); | |
252b5132 | 2986 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 2987 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
2988 | the insn size is 4 and fixup_segment will signal an overflow for |
2989 | large 8 byte quantities. */ | |
2990 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
2991 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
2992 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
2993 | } |
2994 | ||
2995 | last_insn = insn; | |
91d6fa6a | 2996 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
2997 | |
2998 | #ifdef OBJ_ELF | |
2999 | dwarf2_emit_insn (4); | |
3000 | #endif | |
252b5132 RH |
3001 | } |
3002 | \f | |
252b5132 | 3003 | char * |
499ac353 | 3004 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3005 | { |
499ac353 | 3006 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3007 | } |
3008 | ||
3009 | /* Write a value out to the object file, using the appropriate | |
3010 | endianness. */ | |
3011 | ||
3012 | void | |
5a49b8ac | 3013 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3014 | { |
3015 | if (target_big_endian) | |
3016 | number_to_chars_bigendian (buf, val, n); | |
3017 | else if (target_little_endian_data | |
3018 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3019 | /* Output debug words, which are not in allocated sections, as big |
3020 | endian. */ | |
252b5132 RH |
3021 | number_to_chars_bigendian (buf, val, n); |
3022 | else if (target_little_endian_data || ! target_big_endian) | |
3023 | number_to_chars_littleendian (buf, val, n); | |
3024 | } | |
3025 | \f | |
3026 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3027 | hold. */ |
252b5132 | 3028 | |
94f592af | 3029 | void |
5a49b8ac | 3030 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3031 | { |
3032 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3033 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3034 | long insn; |
3035 | ||
9c2799c2 | 3036 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3037 | |
e0c6ed95 | 3038 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3039 | |
3040 | #ifdef OBJ_ELF | |
a161fe53 | 3041 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3042 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3043 | { |
3044 | switch (fixP->fx_r_type) | |
3045 | { | |
3046 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3047 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3048 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3049 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3050 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3051 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3052 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3053 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3054 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3055 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3056 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3057 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3058 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3059 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3060 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3061 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3062 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3063 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3064 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3065 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3066 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3067 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3068 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3069 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3070 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3071 | ||
3072 | default: | |
3073 | break; | |
3074 | } | |
3075 | ||
3076 | return; | |
3077 | } | |
252b5132 RH |
3078 | #endif |
3079 | ||
3080 | /* This is a hack. There should be a better way to | |
3081 | handle this. Probably in terms of howto fields, once | |
3082 | we can look at these fixups in terms of howtos. */ | |
3083 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3084 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3085 | ||
3086 | #ifdef OBJ_AOUT | |
3087 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3088 | generate a reloc, then we just want to let the reloc addend set | |
3089 | the value. We do not want to also stuff the addend into the | |
3090 | object file. Including the addend in the object file works when | |
3091 | doing a static link, because the linker will ignore the object | |
3092 | file contents. However, the dynamic linker does not ignore the | |
3093 | object file contents. */ | |
3094 | if (fixP->fx_addsy != NULL | |
3095 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3096 | val = 0; | |
3097 | ||
3098 | /* When generating PIC code, we do not want an addend for a reloc | |
3099 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3100 | value already included in val, and to also cancel out the | |
3101 | adjustment which bfd_install_relocation will create. */ | |
3102 | if (sparc_pic_code | |
3103 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3104 | && fixP->fx_addsy != NULL | |
3105 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3106 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3107 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3108 | ||
3109 | /* When generating PIC code, we need to fiddle to get | |
3110 | bfd_install_relocation to do the right thing for a PC relative | |
3111 | reloc against a local symbol which we are going to keep. */ | |
3112 | if (sparc_pic_code | |
3113 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3114 | && fixP->fx_addsy != NULL | |
3115 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3116 | || S_IS_WEAK (fixP->fx_addsy)) | |
3117 | && S_IS_DEFINED (fixP->fx_addsy) | |
3118 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3119 | { | |
3120 | val = 0; | |
3121 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3122 | } | |
3123 | #endif | |
3124 | ||
3125 | /* If this is a data relocation, just output VAL. */ | |
3126 | ||
0f2712ed NC |
3127 | if (fixP->fx_r_type == BFD_RELOC_16 |
3128 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3129 | { |
3130 | md_number_to_chars (buf, val, 2); | |
3131 | } | |
3132 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3133 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3134 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3135 | { | |
3136 | md_number_to_chars (buf, val, 4); | |
3137 | } | |
0f2712ed NC |
3138 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3139 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3140 | { |
3141 | md_number_to_chars (buf, val, 8); | |
3142 | } | |
e0c6ed95 | 3143 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3144 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3145 | { | |
3146 | fixP->fx_done = 0; | |
94f592af | 3147 | return; |
252b5132 RH |
3148 | } |
3149 | else | |
3150 | { | |
3151 | /* It's a relocation against an instruction. */ | |
3152 | ||
3153 | if (INSN_BIG_ENDIAN) | |
3154 | insn = bfd_getb32 ((unsigned char *) buf); | |
3155 | else | |
3156 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3157 | |
252b5132 RH |
3158 | switch (fixP->fx_r_type) |
3159 | { | |
3160 | case BFD_RELOC_32_PCREL_S2: | |
3161 | val = val >> 2; | |
3162 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3163 | being done! */ | |
3164 | if (! sparc_pic_code | |
3165 | || fixP->fx_addsy == NULL | |
49309057 | 3166 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3167 | ++val; |
6faf3d66 | 3168 | |
252b5132 | 3169 | insn |= val & 0x3fffffff; |
6faf3d66 | 3170 | |
e0c6ed95 | 3171 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3172 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3173 | { | |
3174 | #define G0 0 | |
3175 | #define O7 15 | |
3176 | #define XCC (2 << 20) | |
3177 | #define COND(x) (((x)&0xf)<<25) | |
3178 | #define CONDA COND(0x8) | |
3179 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3180 | #define INSN_BA (F2(0,2) | CONDA) | |
3181 | #define INSN_OR F3(2, 0x2, 0) | |
3182 | #define INSN_NOP F2(0,4) | |
3183 | ||
3184 | long delay; | |
3185 | ||
3186 | /* If the instruction is a call with either: | |
3187 | restore | |
3188 | arithmetic instruction with rd == %o7 | |
3189 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3190 | then we can optimize if the call destination is near | |
3191 | by changing the call into a branch always. */ | |
3192 | if (INSN_BIG_ENDIAN) | |
3193 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3194 | else | |
3195 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3196 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3197 | break; |
e0c6ed95 AM |
3198 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3199 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3200 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3201 | break; |
e0c6ed95 AM |
3202 | if ((delay & RS1 (~0)) == RS1 (O7) |
3203 | || ((delay & F3I (~0)) == 0 | |
3204 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3205 | break; |
3206 | /* Ensure the branch will fit into simm22. */ | |
3207 | if ((val & 0x3fe00000) | |
3208 | && (val & 0x3fe00000) != 0x3fe00000) | |
3209 | break; | |
3210 | /* Check if the arch is v9 and branch will fit | |
3211 | into simm19. */ | |
3212 | if (((val & 0x3c0000) == 0 | |
3213 | || (val & 0x3c0000) == 0x3c0000) | |
3214 | && (sparc_arch_size == 64 | |
3215 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3216 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3217 | insn = INSN_BPA | (val & 0x7ffff); |
3218 | else | |
e0c6ed95 | 3219 | /* ba */ |
6faf3d66 JJ |
3220 | insn = INSN_BA | (val & 0x3fffff); |
3221 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3222 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3223 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3224 | { |
3225 | long setter; | |
3226 | int reg; | |
3227 | ||
3228 | if (INSN_BIG_ENDIAN) | |
3229 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3230 | else | |
3231 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3232 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3233 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3234 | break; |
3235 | /* The sequence was | |
3236 | or %o7, %g0, %rN | |
3237 | call foo | |
3238 | or %rN, %g0, %o7 | |
3239 | ||
3240 | If call foo was replaced with ba, replace | |
3241 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3242 | reg = (delay & RS1 (~0)) >> 14; |
3243 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3244 | || reg == G0 || reg == O7) |
3245 | break; | |
3246 | ||
3247 | if (INSN_BIG_ENDIAN) | |
3248 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3249 | else | |
3250 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3251 | } | |
3252 | } | |
252b5132 RH |
3253 | break; |
3254 | ||
3255 | case BFD_RELOC_SPARC_11: | |
3256 | if (! in_signed_range (val, 0x7ff)) | |
3257 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3258 | _("relocation overflow")); | |
3259 | insn |= val & 0x7ff; | |
3260 | break; | |
3261 | ||
3262 | case BFD_RELOC_SPARC_10: | |
3263 | if (! in_signed_range (val, 0x3ff)) | |
3264 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3265 | _("relocation overflow")); | |
3266 | insn |= val & 0x3ff; | |
3267 | break; | |
3268 | ||
3269 | case BFD_RELOC_SPARC_7: | |
3270 | if (! in_bitfield_range (val, 0x7f)) | |
3271 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3272 | _("relocation overflow")); | |
3273 | insn |= val & 0x7f; | |
3274 | break; | |
3275 | ||
3276 | case BFD_RELOC_SPARC_6: | |
3277 | if (! in_bitfield_range (val, 0x3f)) | |
3278 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3279 | _("relocation overflow")); | |
3280 | insn |= val & 0x3f; | |
3281 | break; | |
3282 | ||
3283 | case BFD_RELOC_SPARC_5: | |
3284 | if (! in_bitfield_range (val, 0x1f)) | |
3285 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3286 | _("relocation overflow")); | |
3287 | insn |= val & 0x1f; | |
3288 | break; | |
3289 | ||
3290 | case BFD_RELOC_SPARC_WDISP16: | |
c699f087 JJ |
3291 | if ((val & 3) |
3292 | || val >= 0x1fffc | |
3293 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3294 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3295 | _("relocation overflow")); | |
3296 | /* FIXME: The +1 deserves a comment. */ | |
3297 | val = (val >> 2) + 1; | |
3298 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3299 | break; | |
3300 | ||
3301 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3302 | if ((val & 3) |
3303 | || val >= 0xffffc | |
3304 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3305 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3306 | _("relocation overflow")); | |
3307 | /* FIXME: The +1 deserves a comment. */ | |
3308 | val = (val >> 2) + 1; | |
3309 | insn |= val & 0x7ffff; | |
3310 | break; | |
3311 | ||
3312 | case BFD_RELOC_SPARC_HH22: | |
3313 | val = BSR (val, 32); | |
e0c6ed95 | 3314 | /* Fall through. */ |
252b5132 RH |
3315 | |
3316 | case BFD_RELOC_SPARC_LM22: | |
3317 | case BFD_RELOC_HI22: | |
3318 | if (!fixP->fx_addsy) | |
94f592af | 3319 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3320 | else |
94f592af NC |
3321 | /* FIXME: Need comment explaining why we do this. */ |
3322 | insn &= ~0xffff; | |
252b5132 RH |
3323 | break; |
3324 | ||
3325 | case BFD_RELOC_SPARC22: | |
3326 | if (val & ~0x003fffff) | |
3327 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3328 | _("relocation overflow")); | |
3329 | insn |= (val & 0x3fffff); | |
3330 | break; | |
3331 | ||
3332 | case BFD_RELOC_SPARC_HM10: | |
3333 | val = BSR (val, 32); | |
e0c6ed95 | 3334 | /* Fall through. */ |
252b5132 RH |
3335 | |
3336 | case BFD_RELOC_LO10: | |
3337 | if (!fixP->fx_addsy) | |
94f592af | 3338 | insn |= val & 0x3ff; |
252b5132 | 3339 | else |
94f592af NC |
3340 | /* FIXME: Need comment explaining why we do this. */ |
3341 | insn &= ~0xff; | |
252b5132 RH |
3342 | break; |
3343 | ||
dabe3bbc RH |
3344 | case BFD_RELOC_SPARC_OLO10: |
3345 | val &= 0x3ff; | |
3346 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3347 | /* Fall through. */ |
dabe3bbc | 3348 | |
252b5132 RH |
3349 | case BFD_RELOC_SPARC13: |
3350 | if (! in_signed_range (val, 0x1fff)) | |
3351 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3352 | _("relocation overflow")); | |
3353 | insn |= val & 0x1fff; | |
3354 | break; | |
3355 | ||
3356 | case BFD_RELOC_SPARC_WDISP22: | |
3357 | val = (val >> 2) + 1; | |
e0c6ed95 | 3358 | /* Fall through. */ |
252b5132 RH |
3359 | case BFD_RELOC_SPARC_BASE22: |
3360 | insn |= val & 0x3fffff; | |
3361 | break; | |
3362 | ||
3363 | case BFD_RELOC_SPARC_H44: | |
3364 | if (!fixP->fx_addsy) | |
3365 | { | |
3366 | bfd_vma tval = val; | |
3367 | tval >>= 22; | |
3368 | insn |= tval & 0x3fffff; | |
3369 | } | |
3370 | break; | |
3371 | ||
3372 | case BFD_RELOC_SPARC_M44: | |
3373 | if (!fixP->fx_addsy) | |
3374 | insn |= (val >> 12) & 0x3ff; | |
3375 | break; | |
3376 | ||
3377 | case BFD_RELOC_SPARC_L44: | |
3378 | if (!fixP->fx_addsy) | |
3379 | insn |= val & 0xfff; | |
3380 | break; | |
3381 | ||
3382 | case BFD_RELOC_SPARC_HIX22: | |
3383 | if (!fixP->fx_addsy) | |
3384 | { | |
ab3e48dc | 3385 | val ^= ~(offsetT) 0; |
252b5132 RH |
3386 | insn |= (val >> 10) & 0x3fffff; |
3387 | } | |
3388 | break; | |
3389 | ||
3390 | case BFD_RELOC_SPARC_LOX10: | |
3391 | if (!fixP->fx_addsy) | |
3392 | insn |= 0x1c00 | (val & 0x3ff); | |
3393 | break; | |
3394 | ||
3395 | case BFD_RELOC_NONE: | |
3396 | default: | |
3397 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3398 | _("bad or unhandled relocation type: 0x%02x"), | |
3399 | fixP->fx_r_type); | |
3400 | break; | |
3401 | } | |
3402 | ||
3403 | if (INSN_BIG_ENDIAN) | |
3404 | bfd_putb32 (insn, (unsigned char *) buf); | |
3405 | else | |
3406 | bfd_putl32 (insn, (unsigned char *) buf); | |
3407 | } | |
3408 | ||
3409 | /* Are we finished with this relocation now? */ | |
3410 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3411 | fixP->fx_done = 1; | |
252b5132 RH |
3412 | } |
3413 | ||
3414 | /* Translate internal representation of relocation info to BFD target | |
3415 | format. */ | |
e0c6ed95 | 3416 | |
dabe3bbc | 3417 | arelent ** |
5a49b8ac | 3418 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3419 | { |
dabe3bbc | 3420 | static arelent *relocs[3]; |
252b5132 RH |
3421 | arelent *reloc; |
3422 | bfd_reloc_code_real_type code; | |
3423 | ||
dabe3bbc RH |
3424 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3425 | relocs[1] = NULL; | |
252b5132 | 3426 | |
49309057 ILT |
3427 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3428 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3429 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3430 | ||
3431 | switch (fixp->fx_r_type) | |
3432 | { | |
3433 | case BFD_RELOC_16: | |
3434 | case BFD_RELOC_32: | |
3435 | case BFD_RELOC_HI22: | |
3436 | case BFD_RELOC_LO10: | |
3437 | case BFD_RELOC_32_PCREL_S2: | |
3438 | case BFD_RELOC_SPARC13: | |
63fab58c | 3439 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3440 | case BFD_RELOC_SPARC_PC22: |
3441 | case BFD_RELOC_SPARC_PC10: | |
252b5132 RH |
3442 | case BFD_RELOC_SPARC_BASE13: |
3443 | case BFD_RELOC_SPARC_WDISP16: | |
3444 | case BFD_RELOC_SPARC_WDISP19: | |
3445 | case BFD_RELOC_SPARC_WDISP22: | |
3446 | case BFD_RELOC_64: | |
3447 | case BFD_RELOC_SPARC_5: | |
3448 | case BFD_RELOC_SPARC_6: | |
3449 | case BFD_RELOC_SPARC_7: | |
3450 | case BFD_RELOC_SPARC_10: | |
3451 | case BFD_RELOC_SPARC_11: | |
3452 | case BFD_RELOC_SPARC_HH22: | |
3453 | case BFD_RELOC_SPARC_HM10: | |
3454 | case BFD_RELOC_SPARC_LM22: | |
3455 | case BFD_RELOC_SPARC_PC_HH22: | |
3456 | case BFD_RELOC_SPARC_PC_HM10: | |
3457 | case BFD_RELOC_SPARC_PC_LM22: | |
3458 | case BFD_RELOC_SPARC_H44: | |
3459 | case BFD_RELOC_SPARC_M44: | |
3460 | case BFD_RELOC_SPARC_L44: | |
3461 | case BFD_RELOC_SPARC_HIX22: | |
3462 | case BFD_RELOC_SPARC_LOX10: | |
3463 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3464 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3465 | case BFD_RELOC_SPARC_UA16: |
3466 | case BFD_RELOC_SPARC_UA32: | |
3467 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3468 | case BFD_RELOC_8_PCREL: |
3469 | case BFD_RELOC_16_PCREL: | |
3470 | case BFD_RELOC_32_PCREL: | |
3471 | case BFD_RELOC_64_PCREL: | |
3472 | case BFD_RELOC_SPARC_PLT32: | |
3473 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3474 | case BFD_RELOC_VTABLE_ENTRY: |
3475 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3476 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3477 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3478 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3479 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3480 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3481 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3482 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3483 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3484 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3485 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3486 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3487 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3488 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3489 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3490 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3491 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3492 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3493 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3494 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3495 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3496 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3497 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3498 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3499 | code = fixp->fx_r_type; |
3500 | break; | |
3501 | default: | |
3502 | abort (); | |
3503 | return NULL; | |
3504 | } | |
3505 | ||
3506 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3507 | /* If we are generating PIC code, we need to generate a different | |
3508 | set of relocs. */ | |
3509 | ||
3510 | #ifdef OBJ_ELF | |
3511 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3512 | #else | |
3513 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3514 | #endif |
3515 | #ifdef TE_VXWORKS | |
3516 | #define GOTT_BASE "__GOTT_BASE__" | |
3517 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3518 | #endif |
3519 | ||
153b546a ILT |
3520 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3521 | ||
252b5132 RH |
3522 | if (sparc_pic_code) |
3523 | { | |
3524 | switch (code) | |
3525 | { | |
3526 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3527 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3528 | code = BFD_RELOC_SPARC_WPLT30; |
3529 | break; | |
3530 | case BFD_RELOC_HI22: | |
910600e9 RS |
3531 | code = BFD_RELOC_SPARC_GOT22; |
3532 | if (fixp->fx_addsy != NULL) | |
3533 | { | |
3534 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3535 | code = BFD_RELOC_SPARC_PC22; | |
3536 | #ifdef TE_VXWORKS | |
3537 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3538 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3539 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3540 | #endif | |
3541 | } | |
252b5132 RH |
3542 | break; |
3543 | case BFD_RELOC_LO10: | |
910600e9 RS |
3544 | code = BFD_RELOC_SPARC_GOT10; |
3545 | if (fixp->fx_addsy != NULL) | |
3546 | { | |
3547 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3548 | code = BFD_RELOC_SPARC_PC10; | |
3549 | #ifdef TE_VXWORKS | |
3550 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3551 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3552 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3553 | #endif | |
3554 | } | |
252b5132 RH |
3555 | break; |
3556 | case BFD_RELOC_SPARC13: | |
3557 | code = BFD_RELOC_SPARC_GOT13; | |
3558 | break; | |
3559 | default: | |
3560 | break; | |
3561 | } | |
3562 | } | |
e0c6ed95 | 3563 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3564 | |
062cf837 EB |
3565 | /* Nothing is aligned in DWARF debugging sections. */ |
3566 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3567 | switch (code) | |
3568 | { | |
3569 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3570 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3571 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3572 | default: break; | |
3573 | } | |
3574 | ||
dabe3bbc RH |
3575 | if (code == BFD_RELOC_SPARC_OLO10) |
3576 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3577 | else | |
3578 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3579 | if (reloc->howto == 0) |
3580 | { | |
3581 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3582 | _("internal error: can't export reloc type %d (`%s')"), | |
3583 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3584 | xfree (reloc); |
3585 | relocs[0] = NULL; | |
3586 | return relocs; | |
252b5132 RH |
3587 | } |
3588 | ||
3589 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3590 | #ifdef OBJ_AOUT | |
3591 | ||
3592 | if (reloc->howto->pc_relative == 0 | |
3593 | || code == BFD_RELOC_SPARC_PC10 | |
3594 | || code == BFD_RELOC_SPARC_PC22) | |
3595 | reloc->addend = fixp->fx_addnumber; | |
3596 | else if (sparc_pic_code | |
3597 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3598 | && fixp->fx_addsy != NULL | |
3599 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3600 | || S_IS_WEAK (fixp->fx_addsy)) | |
3601 | && S_IS_DEFINED (fixp->fx_addsy) | |
3602 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3603 | reloc->addend = fixp->fx_addnumber; | |
3604 | else | |
3605 | reloc->addend = fixp->fx_offset - reloc->address; | |
3606 | ||
e0c6ed95 | 3607 | #else /* elf or coff */ |
252b5132 | 3608 | |
bd5e6e7e JJ |
3609 | if (code != BFD_RELOC_32_PCREL_S2 |
3610 | && code != BFD_RELOC_SPARC_WDISP22 | |
3611 | && code != BFD_RELOC_SPARC_WDISP16 | |
3612 | && code != BFD_RELOC_SPARC_WDISP19 | |
b9734f35 JJ |
3613 | && code != BFD_RELOC_SPARC_WPLT30 |
3614 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
3615 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 3616 | reloc->addend = fixp->fx_addnumber; |
49309057 | 3617 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3618 | reloc->addend = (section->vma |
3619 | + fixp->fx_addnumber | |
3620 | + md_pcrel_from (fixp)); | |
3621 | else | |
3622 | reloc->addend = fixp->fx_offset; | |
3623 | #endif | |
3624 | ||
dabe3bbc RH |
3625 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3626 | on the same location. */ | |
3627 | if (code == BFD_RELOC_SPARC_OLO10) | |
3628 | { | |
3629 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3630 | relocs[2] = NULL; | |
3631 | ||
3632 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3633 | *reloc->sym_ptr_ptr |
3634 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3635 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3636 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3637 | reloc->addend = fixp->tc_fix_data; | |
3638 | } | |
3639 | ||
3640 | return relocs; | |
252b5132 RH |
3641 | } |
3642 | \f | |
e0c6ed95 | 3643 | /* We have no need to default values of symbols. */ |
252b5132 | 3644 | |
252b5132 | 3645 | symbolS * |
5a49b8ac | 3646 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
3647 | { |
3648 | return 0; | |
e0c6ed95 AM |
3649 | } |
3650 | ||
3651 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3652 | |
252b5132 | 3653 | valueT |
5a49b8ac | 3654 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
3655 | { |
3656 | #ifndef OBJ_ELF | |
3657 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3658 | the alignment anyways. */ | |
3659 | valueT align = ((valueT) 1 | |
3660 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3661 | valueT newsize; | |
e0c6ed95 AM |
3662 | |
3663 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3664 | align--; |
3665 | newsize = (size + align) & ~align; | |
3666 | return newsize; | |
3667 | #else | |
3668 | return size; | |
3669 | #endif | |
3670 | } | |
3671 | ||
3672 | /* Exactly what point is a PC-relative offset relative TO? | |
3673 | On the sparc, they're relative to the address of the offset, plus | |
3674 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3675 | (??? Is this right? FIXME-SOON) */ |
3676 | long | |
5a49b8ac | 3677 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
3678 | { |
3679 | long ret; | |
3680 | ||
3681 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3682 | if (! sparc_pic_code | |
3683 | || fixP->fx_addsy == NULL | |
49309057 | 3684 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3685 | ret += fixP->fx_size; |
3686 | return ret; | |
3687 | } | |
3688 | \f | |
3689 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3690 | of two. */ | |
3691 | ||
3692 | static int | |
5a49b8ac | 3693 | mylog2 (int value) |
252b5132 RH |
3694 | { |
3695 | int shift; | |
3696 | ||
3697 | if (value <= 0) | |
3698 | return -1; | |
3699 | ||
3700 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3701 | ++shift; | |
3702 | ||
3703 | return (value == 1) ? shift : -1; | |
3704 | } | |
3705 | ||
e0c6ed95 | 3706 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3707 | |
3708 | #ifndef OBJ_ELF | |
3709 | static int max_alignment = 15; | |
3710 | #endif | |
3711 | ||
3712 | static void | |
5a49b8ac | 3713 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3714 | { |
3715 | char *name; | |
3716 | char *p; | |
3717 | char c; | |
3718 | int align; | |
3719 | int size; | |
3720 | int temp; | |
3721 | symbolS *symbolP; | |
3722 | ||
3723 | name = input_line_pointer; | |
3724 | c = get_symbol_end (); | |
3725 | p = input_line_pointer; | |
3726 | *p = c; | |
3727 | SKIP_WHITESPACE (); | |
3728 | ||
3729 | if (*input_line_pointer != ',') | |
3730 | { | |
3731 | as_bad (_("Expected comma after name")); | |
3732 | ignore_rest_of_line (); | |
3733 | return; | |
3734 | } | |
3735 | ||
3736 | ++input_line_pointer; | |
3737 | ||
3738 | if ((size = get_absolute_expression ()) < 0) | |
3739 | { | |
3740 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3741 | ignore_rest_of_line (); | |
3742 | return; | |
e0c6ed95 | 3743 | } /* Bad length. */ |
252b5132 RH |
3744 | |
3745 | *p = 0; | |
3746 | symbolP = symbol_find_or_make (name); | |
3747 | *p = c; | |
3748 | ||
3749 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3750 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3751 | { | |
3752 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3753 | return; | |
3754 | } | |
3755 | ||
3756 | if (input_line_pointer[2] == '.') | |
3757 | input_line_pointer += 7; | |
3758 | else | |
3759 | input_line_pointer += 6; | |
3760 | SKIP_WHITESPACE (); | |
3761 | ||
3762 | if (*input_line_pointer == ',') | |
3763 | { | |
3764 | ++input_line_pointer; | |
3765 | ||
3766 | SKIP_WHITESPACE (); | |
3767 | if (*input_line_pointer == '\n') | |
3768 | { | |
3769 | as_bad (_("missing alignment")); | |
3770 | ignore_rest_of_line (); | |
3771 | return; | |
3772 | } | |
3773 | ||
3774 | align = (int) get_absolute_expression (); | |
3775 | ||
3776 | #ifndef OBJ_ELF | |
3777 | if (align > max_alignment) | |
3778 | { | |
3779 | align = max_alignment; | |
3780 | as_warn (_("alignment too large; assuming %d"), align); | |
3781 | } | |
3782 | #endif | |
3783 | ||
3784 | if (align < 0) | |
3785 | { | |
3786 | as_bad (_("negative alignment")); | |
3787 | ignore_rest_of_line (); | |
3788 | return; | |
3789 | } | |
3790 | ||
3791 | if (align != 0) | |
3792 | { | |
f17c130b | 3793 | temp = mylog2 (align); |
252b5132 RH |
3794 | if (temp < 0) |
3795 | { | |
3796 | as_bad (_("alignment not a power of 2")); | |
3797 | ignore_rest_of_line (); | |
3798 | return; | |
3799 | } | |
3800 | ||
3801 | align = temp; | |
3802 | } | |
3803 | ||
3804 | record_alignment (bss_section, align); | |
3805 | } | |
3806 | else | |
3807 | align = 0; | |
3808 | ||
3809 | if (!S_IS_DEFINED (symbolP) | |
3810 | #ifdef OBJ_AOUT | |
3811 | && S_GET_OTHER (symbolP) == 0 | |
3812 | && S_GET_DESC (symbolP) == 0 | |
3813 | #endif | |
3814 | ) | |
3815 | { | |
3816 | if (! need_pass_2) | |
3817 | { | |
3818 | char *pfrag; | |
3819 | segT current_seg = now_seg; | |
3820 | subsegT current_subseg = now_subseg; | |
3821 | ||
e0c6ed95 AM |
3822 | /* Switch to bss. */ |
3823 | subseg_set (bss_section, 1); | |
252b5132 RH |
3824 | |
3825 | if (align) | |
e0c6ed95 AM |
3826 | /* Do alignment. */ |
3827 | frag_align (align, 0, 0); | |
252b5132 | 3828 | |
e0c6ed95 | 3829 | /* Detach from old frag. */ |
ab3e48dc | 3830 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 3831 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 3832 | |
49309057 | 3833 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
3834 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3835 | (offsetT) size, (char *) 0); | |
252b5132 RH |
3836 | *pfrag = 0; |
3837 | ||
3838 | S_SET_SEGMENT (symbolP, bss_section); | |
3839 | ||
3840 | subseg_set (current_seg, current_subseg); | |
3841 | ||
3842 | #ifdef OBJ_ELF | |
3843 | S_SET_SIZE (symbolP, size); | |
3844 | #endif | |
3845 | } | |
3846 | } | |
3847 | else | |
3848 | { | |
20203fb9 | 3849 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 3850 | S_GET_NAME (symbolP)); |
20203fb9 | 3851 | } |
252b5132 RH |
3852 | |
3853 | demand_empty_rest_of_line (); | |
3854 | } | |
3855 | ||
3856 | static void | |
5a49b8ac | 3857 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3858 | { |
3859 | char *name; | |
3860 | char c; | |
3861 | char *p; | |
685736be | 3862 | offsetT temp, size; |
252b5132 RH |
3863 | symbolS *symbolP; |
3864 | ||
3865 | name = input_line_pointer; | |
3866 | c = get_symbol_end (); | |
e0c6ed95 | 3867 | /* Just after name is now '\0'. */ |
252b5132 RH |
3868 | p = input_line_pointer; |
3869 | *p = c; | |
3870 | SKIP_WHITESPACE (); | |
3871 | if (*input_line_pointer != ',') | |
3872 | { | |
3873 | as_bad (_("Expected comma after symbol-name")); | |
3874 | ignore_rest_of_line (); | |
3875 | return; | |
3876 | } | |
e0c6ed95 AM |
3877 | |
3878 | /* Skip ','. */ | |
3879 | input_line_pointer++; | |
3880 | ||
252b5132 RH |
3881 | if ((temp = get_absolute_expression ()) < 0) |
3882 | { | |
685736be NC |
3883 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
3884 | (unsigned long) temp); | |
252b5132 RH |
3885 | ignore_rest_of_line (); |
3886 | return; | |
3887 | } | |
3888 | size = temp; | |
3889 | *p = 0; | |
3890 | symbolP = symbol_find_or_make (name); | |
3891 | *p = c; | |
3892 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3893 | { | |
3894 | as_bad (_("Ignoring attempt to re-define symbol")); | |
3895 | ignore_rest_of_line (); | |
3896 | return; | |
3897 | } | |
3898 | if (S_GET_VALUE (symbolP) != 0) | |
3899 | { | |
3900 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
3901 | { | |
364b6d8b JJ |
3902 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
3903 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
3904 | } |
3905 | } | |
3906 | else | |
3907 | { | |
3908 | #ifndef OBJ_ELF | |
3909 | S_SET_VALUE (symbolP, (valueT) size); | |
3910 | S_SET_EXTERNAL (symbolP); | |
3911 | #endif | |
3912 | } | |
7dcc9865 | 3913 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
3914 | if (*input_line_pointer != ',') |
3915 | { | |
3916 | as_bad (_("Expected comma after common length")); | |
3917 | ignore_rest_of_line (); | |
3918 | return; | |
3919 | } | |
3920 | input_line_pointer++; | |
3921 | SKIP_WHITESPACE (); | |
3922 | if (*input_line_pointer != '"') | |
3923 | { | |
3924 | temp = get_absolute_expression (); | |
3925 | ||
3926 | #ifndef OBJ_ELF | |
3927 | if (temp > max_alignment) | |
3928 | { | |
3929 | temp = max_alignment; | |
f17c130b | 3930 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
3931 | } |
3932 | #endif | |
3933 | ||
3934 | if (temp < 0) | |
3935 | { | |
3936 | as_bad (_("negative alignment")); | |
3937 | ignore_rest_of_line (); | |
3938 | return; | |
3939 | } | |
3940 | ||
3941 | #ifdef OBJ_ELF | |
49309057 | 3942 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
3943 | { |
3944 | segT old_sec; | |
3945 | int old_subsec; | |
252b5132 RH |
3946 | int align; |
3947 | ||
3948 | old_sec = now_seg; | |
3949 | old_subsec = now_subseg; | |
3950 | ||
3951 | if (temp == 0) | |
3952 | align = 0; | |
3953 | else | |
f17c130b | 3954 | align = mylog2 (temp); |
252b5132 RH |
3955 | |
3956 | if (align < 0) | |
3957 | { | |
3958 | as_bad (_("alignment not a power of 2")); | |
3959 | ignore_rest_of_line (); | |
3960 | return; | |
3961 | } | |
3962 | ||
3963 | record_alignment (bss_section, align); | |
3964 | subseg_set (bss_section, 0); | |
3965 | if (align) | |
3966 | frag_align (align, 0, 0); | |
3967 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
3968 | symbol_get_frag (symbolP)->fr_symbol = 0; |
3969 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
3970 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3971 | (offsetT) size, (char *) 0); | |
3972 | *p = 0; | |
3973 | S_SET_SEGMENT (symbolP, bss_section); | |
3974 | S_CLEAR_EXTERNAL (symbolP); | |
3975 | S_SET_SIZE (symbolP, size); | |
3976 | subseg_set (old_sec, old_subsec); | |
3977 | } | |
3978 | else | |
e0c6ed95 | 3979 | #endif /* OBJ_ELF */ |
252b5132 RH |
3980 | { |
3981 | allocate_common: | |
3982 | S_SET_VALUE (symbolP, (valueT) size); | |
3983 | #ifdef OBJ_ELF | |
3984 | S_SET_ALIGN (symbolP, temp); | |
3985 | S_SET_SIZE (symbolP, size); | |
3986 | #endif | |
3987 | S_SET_EXTERNAL (symbolP); | |
3988 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3989 | } | |
3990 | } | |
3991 | else | |
3992 | { | |
3993 | input_line_pointer++; | |
3994 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3995 | if (*input_line_pointer == '.') | |
3996 | input_line_pointer++; | |
3997 | /* @@ Some say data, some say bss. */ | |
3998 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3999 | && strncmp (input_line_pointer, "data\"", 5)) | |
4000 | { | |
4001 | while (*--input_line_pointer != '"') | |
4002 | ; | |
4003 | input_line_pointer--; | |
4004 | goto bad_common_segment; | |
4005 | } | |
4006 | while (*input_line_pointer++ != '"') | |
4007 | ; | |
4008 | goto allocate_common; | |
4009 | } | |
4010 | ||
49309057 | 4011 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4012 | |
4013 | demand_empty_rest_of_line (); | |
4014 | return; | |
4015 | ||
4016 | { | |
4017 | bad_common_segment: | |
4018 | p = input_line_pointer; | |
4019 | while (*p && *p != '\n') | |
4020 | p++; | |
4021 | c = *p; | |
4022 | *p = '\0'; | |
4023 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4024 | *p = c; | |
4025 | input_line_pointer = p; | |
4026 | ignore_rest_of_line (); | |
4027 | return; | |
4028 | } | |
4029 | } | |
4030 | ||
67c1ffbe | 4031 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4032 | invalid delay slot usage. */ |
4033 | ||
4034 | static void | |
5a49b8ac | 4035 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4036 | { |
4037 | /* The easy way to implement is to just forget about the last | |
4038 | instruction. */ | |
4039 | last_insn = NULL; | |
4040 | } | |
4041 | ||
4042 | static void | |
5a49b8ac | 4043 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4044 | { |
4045 | ||
4046 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4047 | { | |
4048 | input_line_pointer += 6; | |
4049 | s_text (0); | |
4050 | return; | |
4051 | } | |
4052 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4053 | { | |
4054 | input_line_pointer += 6; | |
4055 | s_data (0); | |
4056 | return; | |
4057 | } | |
4058 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4059 | { | |
4060 | input_line_pointer += 7; | |
4061 | s_data1 (); | |
4062 | return; | |
4063 | } | |
4064 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4065 | { | |
4066 | input_line_pointer += 5; | |
4067 | /* We only support 2 segments -- text and data -- for now, so | |
4068 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4069 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4070 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4071 | return; |
4072 | } | |
4073 | as_bad (_("Unknown segment type")); | |
4074 | demand_empty_rest_of_line (); | |
4075 | } | |
4076 | ||
4077 | static void | |
5a49b8ac | 4078 | s_data1 (void) |
252b5132 RH |
4079 | { |
4080 | subseg_set (data_section, 1); | |
4081 | demand_empty_rest_of_line (); | |
4082 | } | |
4083 | ||
4084 | static void | |
5a49b8ac | 4085 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4086 | { |
4087 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4088 | { | |
4089 | ++input_line_pointer; | |
4090 | } | |
4091 | ++input_line_pointer; | |
4092 | } | |
4093 | ||
4094 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4095 | that the expression does not need to be aligned. */ |
252b5132 RH |
4096 | |
4097 | static int sparc_no_align_cons = 0; | |
4098 | ||
bd5e6e7e JJ |
4099 | /* This static variable is set by sparc_cons to emit requested types |
4100 | of relocations in cons_fix_new_sparc. */ | |
4101 | ||
4102 | static const char *sparc_cons_special_reloc; | |
4103 | ||
252b5132 RH |
4104 | /* This handles the unaligned space allocation pseudo-ops, such as |
4105 | .uaword. .uaword is just like .word, but the value does not need | |
4106 | to be aligned. */ | |
4107 | ||
4108 | static void | |
5a49b8ac | 4109 | s_uacons (int bytes) |
252b5132 RH |
4110 | { |
4111 | /* Tell sparc_cons_align not to align this value. */ | |
4112 | sparc_no_align_cons = 1; | |
4113 | cons (bytes); | |
4ffadb11 | 4114 | sparc_no_align_cons = 0; |
252b5132 RH |
4115 | } |
4116 | ||
cf9a1301 RH |
4117 | /* This handles the native word allocation pseudo-op .nword. |
4118 | For sparc_arch_size 32 it is equivalent to .word, for | |
4119 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4120 | ||
4121 | static void | |
5a49b8ac | 4122 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4123 | { |
4124 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4125 | } | |
4126 | ||
6d8809aa RH |
4127 | #ifdef OBJ_ELF |
4128 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4129 | global register. | |
4130 | The syntax is: | |
e0c6ed95 | 4131 | |
6d8809aa | 4132 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4133 | */ |
6d8809aa RH |
4134 | |
4135 | static void | |
5a49b8ac | 4136 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4137 | { |
4138 | char c; | |
4139 | int reg; | |
4140 | int flags; | |
4141 | const char *regname; | |
4142 | ||
4143 | if (input_line_pointer[0] != '%' | |
4144 | || input_line_pointer[1] != 'g' | |
4145 | || ((input_line_pointer[2] & ~1) != '2' | |
4146 | && (input_line_pointer[2] & ~1) != '6') | |
4147 | || input_line_pointer[3] != ',') | |
4148 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4149 | reg = input_line_pointer[2] - '0'; | |
4150 | input_line_pointer += 4; | |
4151 | ||
4152 | if (*input_line_pointer == '#') | |
4153 | { | |
4154 | ++input_line_pointer; | |
4155 | regname = input_line_pointer; | |
4156 | c = get_symbol_end (); | |
4157 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
4158 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4159 | if (regname[0] == 'i') |
6d8809aa RH |
4160 | regname = NULL; |
4161 | else | |
4162 | regname = ""; | |
4163 | } | |
4164 | else | |
4165 | { | |
4166 | regname = input_line_pointer; | |
4167 | c = get_symbol_end (); | |
4168 | } | |
4169 | if (sparc_arch_size == 64) | |
4170 | { | |
e0c6ed95 | 4171 | if (globals[reg]) |
6d8809aa | 4172 | { |
e0c6ed95 AM |
4173 | if ((regname && globals[reg] != (symbolS *) 1 |
4174 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4175 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4176 | as_bad (_("redefinition of global register")); |
4177 | } | |
4178 | else | |
4179 | { | |
4180 | if (regname == NULL) | |
e0c6ed95 | 4181 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4182 | else |
4183 | { | |
4184 | if (*regname) | |
4185 | { | |
4186 | if (symbol_find (regname)) | |
4187 | as_bad (_("Register symbol %s already defined."), | |
4188 | regname); | |
4189 | } | |
e0c6ed95 AM |
4190 | globals[reg] = symbol_make (regname); |
4191 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4192 | if (! *regname) |
4193 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4194 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4195 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4196 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4197 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4198 | S_SET_ALIGN (globals[reg], reg); | |
4199 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4200 | /* Although we actually want undefined_section here, |
4201 | we have to use absolute_section, because otherwise | |
4202 | generic as code will make it a COM section. | |
4203 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4204 | S_SET_SEGMENT (globals[reg], absolute_section); |
4205 | S_SET_OTHER (globals[reg], 0); | |
4206 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4207 | ->internal_elf_sym.st_info = |
4208 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4209 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4210 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4211 | } | |
4212 | } | |
4213 | } | |
4214 | ||
4215 | *input_line_pointer = c; | |
4216 | ||
4217 | demand_empty_rest_of_line (); | |
4218 | } | |
4219 | ||
4220 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4221 | symbols which need it. */ | |
e0c6ed95 | 4222 | |
6d8809aa | 4223 | void |
5a49b8ac | 4224 | sparc_adjust_symtab (void) |
6d8809aa RH |
4225 | { |
4226 | symbolS *sym; | |
e0c6ed95 | 4227 | |
6d8809aa RH |
4228 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4229 | { | |
4230 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4231 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4232 | continue; | |
4233 | ||
4234 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4235 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4236 | continue; | |
4237 | ||
4238 | S_SET_SEGMENT (sym, undefined_section); | |
4239 | } | |
4240 | } | |
4241 | #endif | |
4242 | ||
252b5132 RH |
4243 | /* If the --enforce-aligned-data option is used, we require .word, |
4244 | et. al., to be aligned correctly. We do it by setting up an | |
4245 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4246 | no unexpected alignment was introduced. | |
4247 | ||
4248 | The SunOS and Solaris native assemblers enforce aligned data by | |
4249 | default. We don't want to do that, because gcc can deliberately | |
4250 | generate misaligned data if the packed attribute is used. Instead, | |
4251 | we permit misaligned data by default, and permit the user to set an | |
4252 | option to check for it. */ | |
4253 | ||
4254 | void | |
5a49b8ac | 4255 | sparc_cons_align (int nbytes) |
252b5132 RH |
4256 | { |
4257 | int nalign; | |
252b5132 RH |
4258 | |
4259 | /* Only do this if we are enforcing aligned data. */ | |
4260 | if (! enforce_aligned_data) | |
4261 | return; | |
4262 | ||
0f2712ed | 4263 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4264 | if (sparc_no_align_cons) |
0f2712ed | 4265 | return; |
252b5132 | 4266 | |
f17c130b | 4267 | nalign = mylog2 (nbytes); |
252b5132 RH |
4268 | if (nalign == 0) |
4269 | return; | |
4270 | ||
9c2799c2 | 4271 | gas_assert (nalign > 0); |
252b5132 RH |
4272 | |
4273 | if (now_seg == absolute_section) | |
4274 | { | |
4275 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4276 | as_bad (_("misaligned data")); | |
4277 | return; | |
4278 | } | |
4279 | ||
87975d2a AM |
4280 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4281 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4282 | |
4283 | record_alignment (now_seg, nalign); | |
4284 | } | |
4285 | ||
0a9ef439 | 4286 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4287 | |
4288 | void | |
5a49b8ac | 4289 | sparc_handle_align (fragS *fragp) |
252b5132 | 4290 | { |
0a9ef439 RH |
4291 | int count, fix; |
4292 | char *p; | |
4293 | ||
4294 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4295 | |
0a9ef439 | 4296 | switch (fragp->fr_type) |
252b5132 | 4297 | { |
0a9ef439 RH |
4298 | case rs_align_test: |
4299 | if (count != 0) | |
4300 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4301 | break; | |
e0c6ed95 | 4302 | |
0a9ef439 RH |
4303 | case rs_align_code: |
4304 | p = fragp->fr_literal + fragp->fr_fix; | |
4305 | fix = 0; | |
e0c6ed95 | 4306 | |
0a9ef439 RH |
4307 | if (count & 3) |
4308 | { | |
4309 | fix = count & 3; | |
4310 | memset (p, 0, fix); | |
4311 | p += fix; | |
4312 | count -= fix; | |
4313 | } | |
e0c6ed95 | 4314 | |
0a9ef439 RH |
4315 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4316 | { | |
4317 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4318 | if (INSN_BIG_ENDIAN) | |
4319 | number_to_chars_bigendian (p, wval, 4); | |
4320 | else | |
4321 | number_to_chars_littleendian (p, wval, 4); | |
4322 | p += 4; | |
4323 | count -= 4; | |
4324 | fix += 4; | |
e0c6ed95 | 4325 | } |
0a9ef439 RH |
4326 | |
4327 | if (INSN_BIG_ENDIAN) | |
4328 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4329 | else | |
4330 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4331 | ||
4332 | fragp->fr_fix += fix; | |
4333 | fragp->fr_var = 4; | |
4334 | break; | |
4335 | ||
4336 | default: | |
4337 | break; | |
252b5132 RH |
4338 | } |
4339 | } | |
4340 | ||
4341 | #ifdef OBJ_ELF | |
4342 | /* Some special processing for a Sparc ELF file. */ | |
4343 | ||
4344 | void | |
5a49b8ac | 4345 | sparc_elf_final_processing (void) |
252b5132 RH |
4346 | { |
4347 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4348 | sort of BFD interface for this. */ | |
4349 | if (sparc_arch_size == 64) | |
4350 | { | |
4351 | switch (sparc_memory_model) | |
4352 | { | |
4353 | case MM_RMO: | |
4354 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4355 | break; | |
4356 | case MM_PSO: | |
4357 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4358 | break; | |
4359 | default: | |
4360 | break; | |
4361 | } | |
4362 | } | |
4363 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4364 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4365 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4366 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4367 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4368 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4369 | } |
bd5e6e7e JJ |
4370 | |
4371 | void | |
5a49b8ac | 4372 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4373 | { |
4374 | char *save; | |
4375 | ||
4376 | SKIP_WHITESPACE (); | |
4377 | sparc_cons_special_reloc = NULL; | |
4378 | save = input_line_pointer; | |
4379 | if (input_line_pointer[0] == '%' | |
4380 | && input_line_pointer[1] == 'r' | |
4381 | && input_line_pointer[2] == '_') | |
4382 | { | |
4383 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4384 | { | |
4385 | input_line_pointer += 7; | |
4386 | sparc_cons_special_reloc = "disp"; | |
4387 | } | |
4388 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4389 | { | |
4390 | if (size != 4 && size != 8) | |
4391 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4392 | else | |
4393 | { | |
4394 | input_line_pointer += 6; | |
4395 | sparc_cons_special_reloc = "plt"; | |
4396 | } | |
4397 | } | |
b9734f35 JJ |
4398 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4399 | { | |
4400 | if (size != 4 && size != 8) | |
4401 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4402 | else | |
4403 | { | |
4404 | input_line_pointer += 13; | |
4405 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4406 | } | |
4407 | } | |
bd5e6e7e JJ |
4408 | if (sparc_cons_special_reloc) |
4409 | { | |
4410 | int bad = 0; | |
4411 | ||
4412 | switch (size) | |
4413 | { | |
4414 | case 1: | |
4415 | if (*input_line_pointer != '8') | |
4416 | bad = 1; | |
4417 | input_line_pointer--; | |
4418 | break; | |
4419 | case 2: | |
4420 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4421 | bad = 1; | |
4422 | break; | |
4423 | case 4: | |
4424 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4425 | bad = 1; | |
4426 | break; | |
4427 | case 8: | |
4428 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4429 | bad = 1; | |
4430 | break; | |
4431 | default: | |
4432 | bad = 1; | |
4433 | break; | |
4434 | } | |
4435 | ||
4436 | if (bad) | |
4437 | { | |
4438 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4439 | sparc_cons_special_reloc, size * 8, size); | |
4440 | } | |
4441 | else | |
4442 | { | |
4443 | input_line_pointer += 2; | |
4444 | if (*input_line_pointer != '(') | |
4445 | { | |
4446 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4447 | sparc_cons_special_reloc, size * 8); | |
4448 | bad = 1; | |
4449 | } | |
4450 | } | |
4451 | ||
4452 | if (bad) | |
4453 | { | |
4454 | input_line_pointer = save; | |
4455 | sparc_cons_special_reloc = NULL; | |
4456 | } | |
4457 | else | |
4458 | { | |
4459 | int c; | |
4460 | char *end = ++input_line_pointer; | |
4461 | int npar = 0; | |
4462 | ||
4463 | while (! is_end_of_line[(c = *end)]) | |
4464 | { | |
4465 | if (c == '(') | |
4466 | npar++; | |
4467 | else if (c == ')') | |
4468 | { | |
4469 | if (!npar) | |
4470 | break; | |
4471 | npar--; | |
4472 | } | |
4473 | end++; | |
4474 | } | |
4475 | ||
4476 | if (c != ')') | |
4477 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4478 | sparc_cons_special_reloc, size * 8); | |
4479 | else | |
4480 | { | |
4481 | *end = '\0'; | |
4482 | expression (exp); | |
4483 | *end = c; | |
4484 | if (input_line_pointer != end) | |
4485 | { | |
4486 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4487 | sparc_cons_special_reloc, size * 8); | |
4488 | } | |
4489 | else | |
4490 | { | |
4491 | input_line_pointer++; | |
4492 | SKIP_WHITESPACE (); | |
4493 | c = *input_line_pointer; | |
4494 | if (! is_end_of_line[c] && c != ',') | |
4495 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4496 | sparc_cons_special_reloc, size * 8); | |
4497 | } | |
4498 | } | |
4499 | } | |
4500 | } | |
4501 | } | |
4502 | if (sparc_cons_special_reloc == NULL) | |
4503 | expression (exp); | |
4504 | } | |
4505 | ||
252b5132 RH |
4506 | #endif |
4507 | ||
4508 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4509 | reloc for a cons. We could use the definition there, except that | |
4510 | we want to handle little endian relocs specially. */ | |
4511 | ||
4512 | void | |
5a49b8ac AM |
4513 | cons_fix_new_sparc (fragS *frag, |
4514 | int where, | |
4515 | unsigned int nbytes, | |
4516 | expressionS *exp) | |
252b5132 RH |
4517 | { |
4518 | bfd_reloc_code_real_type r; | |
4519 | ||
4520 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4521 | (nbytes == 2 ? BFD_RELOC_16 : | |
4522 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4523 | ||
0f2712ed NC |
4524 | if (target_little_endian_data |
4525 | && nbytes == 4 | |
e0c6ed95 | 4526 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4527 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4528 | |
bd5e6e7e JJ |
4529 | if (sparc_cons_special_reloc) |
4530 | { | |
4531 | if (*sparc_cons_special_reloc == 'd') | |
4532 | switch (nbytes) | |
4533 | { | |
4534 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4535 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4536 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4537 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4538 | default: abort (); | |
4539 | } | |
b9734f35 | 4540 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4541 | switch (nbytes) |
4542 | { | |
4543 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4544 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4545 | } | |
b9734f35 JJ |
4546 | else |
4547 | switch (nbytes) | |
4548 | { | |
4549 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4550 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4551 | } | |
bd5e6e7e JJ |
4552 | } |
4553 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4554 | { |
4555 | switch (nbytes) | |
4556 | { | |
4557 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4558 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
4559 | case 8: r = BFD_RELOC_SPARC_UA64; break; | |
4560 | default: abort (); | |
4561 | } | |
4ffadb11 | 4562 | } |
0f2712ed | 4563 | |
252b5132 | 4564 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4565 | sparc_cons_special_reloc = NULL; |
4566 | } | |
4567 | ||
4568 | void | |
5a49b8ac | 4569 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4570 | { |
4571 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4572 | } | |
4573 | ||
4574 | int | |
1df69f4f | 4575 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b JJ |
4576 | { |
4577 | char *p, *q; | |
4578 | ||
4579 | if (!regname[0]) | |
4580 | return -1; | |
4581 | ||
4582 | q = "goli"; | |
4583 | p = strchr (q, regname[0]); | |
4584 | if (p) | |
4585 | { | |
4586 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
4587 | return -1; | |
4588 | return (p - q) * 8 + regname[1] - '0'; | |
4589 | } | |
4590 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
4591 | return 14; | |
4592 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
4593 | return 30; | |
4594 | if (regname[0] == 'f' || regname[0] == 'r') | |
4595 | { | |
4596 | unsigned int regnum; | |
4597 | ||
4598 | regnum = strtoul (regname + 1, &q, 10); | |
4599 | if (p == q || *q) | |
4600 | return -1; | |
4601 | if (regnum >= ((regname[0] == 'f' | |
4602 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
4603 | ? 64 : 32)) | |
4604 | return -1; | |
4605 | if (regname[0] == 'f') | |
4606 | { | |
4607 | regnum += 32; | |
4608 | if (regnum >= 64 && (regnum & 1)) | |
4609 | return -1; | |
4610 | } | |
4611 | return regnum; | |
4612 | } | |
4613 | return -1; | |
4614 | } | |
4615 | ||
4616 | void | |
4617 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
4618 | { | |
4619 | sparc_cons_special_reloc = "disp"; | |
4620 | sparc_no_align_cons = 1; | |
4621 | emit_expr (exp, nbytes); | |
4622 | sparc_no_align_cons = 0; | |
4623 | sparc_cons_special_reloc = NULL; | |
252b5132 | 4624 | } |