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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | This file is part of GAS, the GNU Assembler. |
4 | ||
5 | GAS is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 7 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
8 | any later version. |
9 | ||
10 | GAS is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public | |
16 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
17 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
18 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 19 | |
252b5132 | 20 | #include "as.h" |
3882b010 | 21 | #include "safe-ctype.h" |
252b5132 RH |
22 | #include "subsegs.h" |
23 | ||
24 | #include "opcode/sparc.h" | |
364b6d8b | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | |
27 | #ifdef OBJ_ELF | |
28 | #include "elf/sparc.h" | |
732d96b6 | 29 | #include "dwarf2dbg.h" |
252b5132 RH |
30 | #endif |
31 | ||
6c1b24e4 AO |
32 | /* Some ancient Sun C compilers would not take such hex constants as |
33 | unsigned, and would end up sign-extending them to form an offsetT, | |
34 | so use these constants instead. */ | |
35 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
36 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
37 | ||
5a49b8ac | 38 | static int sparc_ip (char *, const struct sparc_opcode **); |
1e9d41d4 | 39 | static int parse_sparc_asi (char **, const sparc_asi **); |
5a49b8ac AM |
40 | static int parse_keyword_arg (int (*) (const char *), char **, int *); |
41 | static int parse_const_expr_arg (char **, int *); | |
42 | static int get_expression (char *); | |
252b5132 RH |
43 | |
44 | /* Default architecture. */ | |
45 | /* ??? The default value should be V8, but sparclite support was added | |
46 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
47 | the future we can set this to V8. */ | |
48 | #ifndef DEFAULT_ARCH | |
49 | #define DEFAULT_ARCH "sparclite" | |
50 | #endif | |
e0471c16 | 51 | static const char *default_arch = DEFAULT_ARCH; |
252b5132 RH |
52 | |
53 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
54 | have been set. */ | |
55 | static int default_init_p; | |
56 | ||
57 | /* Current architecture. We don't bump up unless necessary. */ | |
58 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
59 | ||
60 | /* The maximum architecture level we can bump up to. | |
61 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
62 | The native assembler works this way. The user is required to pass | |
63 | an explicit argument before we'll create v9 object files. However, if | |
64 | we don't see any v9 insns, a v8plus object file is not created. */ | |
65 | static enum sparc_opcode_arch_val max_architecture; | |
66 | ||
67 | /* Either 32 or 64, selects file format. */ | |
68 | static int sparc_arch_size; | |
69 | /* Initial (default) value, recorded separately in case a user option | |
70 | changes the value before md_show_usage is called. */ | |
71 | static int default_arch_size; | |
72 | ||
73 | #ifdef OBJ_ELF | |
74 | /* The currently selected v9 memory model. Currently only used for | |
75 | ELF. */ | |
76 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
77 | |
78 | #ifndef TE_SOLARIS | |
79 | /* Bitmask of instruction types seen so far, used to populate the | |
80 | GNU attributes section with hwcap information. */ | |
3d68f91c | 81 | static bfd_uint64_t hwcap_seen; |
9e8c70f9 | 82 | #endif |
252b5132 RH |
83 | #endif |
84 | ||
3d68f91c | 85 | static bfd_uint64_t hwcap_allowed; |
4bafe00e | 86 | |
252b5132 RH |
87 | static int architecture_requested; |
88 | static int warn_on_bump; | |
89 | ||
90 | /* If warn_on_bump and the needed architecture is higher than this | |
91 | architecture, issue a warning. */ | |
92 | static enum sparc_opcode_arch_val warn_after_architecture; | |
93 | ||
46a2d504 JM |
94 | /* Non-zero if the assembler should generate error if an undeclared |
95 | g[23] register has been used in -64. */ | |
6d8809aa RH |
96 | static int no_undeclared_regs; |
97 | ||
46a2d504 JM |
98 | /* Non-zero if the assembler should generate a warning if an |
99 | unpredictable DCTI (delayed control transfer instruction) couple is | |
100 | found. */ | |
101 | static int dcti_couples_detect; | |
102 | ||
6faf3d66 JJ |
103 | /* Non-zero if we should try to relax jumps and calls. */ |
104 | static int sparc_relax; | |
105 | ||
252b5132 RH |
106 | /* Non-zero if we are generating PIC code. */ |
107 | int sparc_pic_code; | |
108 | ||
109 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
110 | static int enforce_aligned_data; | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
114 | static int target_little_endian_data; | |
115 | ||
6d8809aa RH |
116 | /* Symbols for global registers on v9. */ |
117 | static symbolS *globals[8]; | |
118 | ||
364b6d8b JJ |
119 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
120 | int sparc_cie_data_alignment; | |
121 | ||
252b5132 RH |
122 | /* V9 and 86x have big and little endian data, but instructions are always big |
123 | endian. The sparclet has bi-endian support but both data and insns have | |
124 | the same endianness. Global `target_big_endian' is used for data. | |
125 | The following macro is used for instructions. */ | |
126 | #ifndef INSN_BIG_ENDIAN | |
127 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
128 | || default_arch_type == sparc86x \ | |
129 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
130 | #endif | |
131 | ||
e0c6ed95 | 132 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
133 | static struct hash_control *op_hash; |
134 | ||
5a49b8ac AM |
135 | static void s_data1 (void); |
136 | static void s_seg (int); | |
137 | static void s_proc (int); | |
138 | static void s_reserve (int); | |
139 | static void s_common (int); | |
140 | static void s_empty (int); | |
141 | static void s_uacons (int); | |
142 | static void s_ncons (int); | |
a7982600 | 143 | #ifdef OBJ_ELF |
5a49b8ac | 144 | static void s_register (int); |
a7982600 | 145 | #endif |
252b5132 RH |
146 | |
147 | const pseudo_typeS md_pseudo_table[] = | |
148 | { | |
e0c6ed95 | 149 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
150 | {"common", s_common, 0}, |
151 | {"empty", s_empty, 0}, | |
152 | {"global", s_globl, 0}, | |
153 | {"half", cons, 2}, | |
cf9a1301 | 154 | {"nword", s_ncons, 0}, |
252b5132 RH |
155 | {"optim", s_ignore, 0}, |
156 | {"proc", s_proc, 0}, | |
157 | {"reserve", s_reserve, 0}, | |
158 | {"seg", s_seg, 0}, | |
159 | {"skip", s_space, 0}, | |
160 | {"word", cons, 4}, | |
161 | {"xword", cons, 8}, | |
162 | {"uahalf", s_uacons, 2}, | |
163 | {"uaword", s_uacons, 4}, | |
164 | {"uaxword", s_uacons, 8}, | |
165 | #ifdef OBJ_ELF | |
e0c6ed95 | 166 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
167 | {"2byte", s_uacons, 2}, |
168 | {"4byte", s_uacons, 4}, | |
169 | {"8byte", s_uacons, 8}, | |
6d8809aa | 170 | {"register", s_register, 0}, |
252b5132 RH |
171 | #endif |
172 | {NULL, 0, 0}, | |
173 | }; | |
174 | ||
252b5132 | 175 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
176 | pre-processor is disabled, these aren't very useful. */ |
177 | const char comment_chars[] = "!"; /* JF removed '|' from | |
178 | comment_chars. */ | |
252b5132 RH |
179 | |
180 | /* This array holds the chars that only start a comment at the beginning of | |
181 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 182 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
183 | /* Note that input_file.c hand checks for '#' at the beginning of the |
184 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 185 | #NO_APP at the beginning of its output. */ |
252b5132 | 186 | /* Also note that comments started like this one will always |
e0c6ed95 | 187 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
188 | const char line_comment_chars[] = "#"; |
189 | ||
63a0b638 | 190 | const char line_separator_chars[] = ";"; |
252b5132 | 191 | |
e0c6ed95 AM |
192 | /* Chars that can be used to separate mant from exp in floating point |
193 | nums. */ | |
252b5132 RH |
194 | const char EXP_CHARS[] = "eE"; |
195 | ||
e0c6ed95 AM |
196 | /* Chars that mean this number is a floating point constant. |
197 | As in 0f12.456 | |
198 | or 0d1.2345e12 */ | |
252b5132 RH |
199 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
200 | ||
201 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
202 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
203 | but nothing is ideal around here. */ | |
204 | ||
74b56d1f | 205 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
206 | |
207 | struct sparc_it | |
208 | { | |
6d4af3c2 | 209 | const char *error; |
252b5132 RH |
210 | unsigned long opcode; |
211 | struct nlist *nlistp; | |
212 | expressionS exp; | |
cf9a1301 | 213 | expressionS exp2; |
252b5132 RH |
214 | int pcrel; |
215 | bfd_reloc_code_real_type reloc; | |
216 | }; | |
217 | ||
218 | struct sparc_it the_insn, set_insn; | |
219 | ||
5a49b8ac | 220 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
221 | \f |
222 | /* Table of arguments to -A. | |
223 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
224 | for this use. That table is for opcodes only. This table is for opcodes | |
225 | and file formats. */ | |
226 | ||
d6787ef9 | 227 | enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, |
19f7b010 | 228 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
229 | |
230 | static struct sparc_arch { | |
e0471c16 TS |
231 | const char *name; |
232 | const char *opcode_arch; | |
252b5132 RH |
233 | enum sparc_arch_types arch_type; |
234 | /* Default word size, as specified during configuration. | |
235 | A value of zero means can't be used to specify default architecture. */ | |
236 | int default_arch_size; | |
237 | /* Allowable arg to -A? */ | |
238 | int user_option_p; | |
6884417a JM |
239 | /* Extra hardware capabilities allowed. These are added to the |
240 | hardware capabilities associated with the opcode | |
241 | architecture. */ | |
4bafe00e | 242 | int hwcap_allowed; |
3d68f91c | 243 | int hwcap2_allowed; |
252b5132 | 244 | } sparc_arch_table[] = { |
3d68f91c JM |
245 | { "v6", "v6", v6, 0, 1, 0, 0 }, |
246 | { "v7", "v7", v7, 0, 1, 0, 0 }, | |
6884417a JM |
247 | { "v8", "v8", v8, 32, 1, 0, 0 }, |
248 | { "v8a", "v8", v8, 32, 1, 0, 0 }, | |
249 | { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
250 | { "sparcvis", "v9a", v9, 0, 1, 0, 0 }, | |
251 | { "sparcvis2", "v9b", v9, 0, 1, 0, 0 }, | |
252 | { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 }, | |
253 | { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 }, | |
254 | { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, | |
255 | { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, | |
256 | ||
257 | { "sparc4", "v9v", v9, 0, 1, 0, 0 }, | |
258 | { "sparc5", "v9m", v9, 0, 1, 0, 0 }, | |
64517994 | 259 | { "sparc6", "m8", v9, 0, 1, 0, 0 }, |
6884417a JM |
260 | |
261 | { "leon", "leon", leon, 32, 1, 0, 0 }, | |
262 | { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 }, | |
263 | { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 }, | |
264 | { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 }, | |
265 | ||
266 | { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
267 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
268 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
269 | { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
270 | { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
271 | { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
272 | { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
273 | { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
64517994 JM |
274 | { "v8plusm8", "m8", v9, 0, 1, HWCAP_V8PLUS, 0 }, |
275 | ||
6884417a JM |
276 | { "v9", "v9", v9, 0, 1, 0, 0 }, |
277 | { "v9a", "v9a", v9, 0, 1, 0, 0 }, | |
278 | { "v9b", "v9b", v9, 0, 1, 0, 0 }, | |
279 | { "v9c", "v9c", v9, 0, 1, 0, 0 }, | |
280 | { "v9d", "v9d", v9, 0, 1, 0, 0 }, | |
281 | { "v9e", "v9e", v9, 0, 1, 0, 0 }, | |
282 | { "v9v", "v9v", v9, 0, 1, 0, 0 }, | |
283 | { "v9m", "v9m", v9, 0, 1, 0, 0 }, | |
64517994 | 284 | { "v9m8", "m8", v9, 0, 1, 0, 0 }, |
3d68f91c | 285 | |
1110793a | 286 | /* This exists to allow configure.tgt to pass one |
252b5132 | 287 | value to specify both the default machine and default word size. */ |
6884417a | 288 | { "v9-64", "v9", v9, 64, 0, 0, 0 }, |
3d68f91c | 289 | { NULL, NULL, v8, 0, 0, 0, 0 } |
252b5132 RH |
290 | }; |
291 | ||
292 | /* Variant of default_arch */ | |
293 | static enum sparc_arch_types default_arch_type; | |
294 | ||
295 | static struct sparc_arch * | |
e0471c16 | 296 | lookup_arch (const char *name) |
252b5132 RH |
297 | { |
298 | struct sparc_arch *sa; | |
299 | ||
300 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
301 | if (strcmp (sa->name, name) == 0) | |
302 | break; | |
303 | if (sa->name == NULL) | |
304 | return NULL; | |
305 | return sa; | |
306 | } | |
307 | ||
308 | /* Initialize the default opcode arch and word size from the default | |
309 | architecture name. */ | |
310 | ||
311 | static void | |
5a49b8ac | 312 | init_default_arch (void) |
252b5132 RH |
313 | { |
314 | struct sparc_arch *sa = lookup_arch (default_arch); | |
315 | ||
316 | if (sa == NULL | |
317 | || sa->default_arch_size == 0) | |
318 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
319 | ||
320 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
321 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
322 | as_fatal (_("Bad opcode table, broken assembler.")); | |
323 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
324 | default_init_p = 1; | |
325 | default_arch_type = sa->arch_type; | |
326 | } | |
327 | ||
d85815e2 EB |
328 | /* Called by TARGET_MACH. */ |
329 | ||
330 | unsigned long | |
331 | sparc_mach (void) | |
332 | { | |
333 | /* We don't get a chance to initialize anything before we're called, | |
334 | so handle that now. */ | |
335 | if (! default_init_p) | |
336 | init_default_arch (); | |
337 | ||
338 | return sparc_arch_size == 64 ? bfd_mach_sparc_v9 : bfd_mach_sparc; | |
339 | } | |
340 | ||
252b5132 RH |
341 | /* Called by TARGET_FORMAT. */ |
342 | ||
343 | const char * | |
5a49b8ac | 344 | sparc_target_format (void) |
252b5132 RH |
345 | { |
346 | /* We don't get a chance to initialize anything before we're called, | |
347 | so handle that now. */ | |
348 | if (! default_init_p) | |
349 | init_default_arch (); | |
350 | ||
351 | #ifdef OBJ_AOUT | |
352 | #ifdef TE_NetBSD | |
353 | return "a.out-sparc-netbsd"; | |
354 | #else | |
355 | #ifdef TE_SPARCAOUT | |
356 | if (target_big_endian) | |
357 | return "a.out-sunos-big"; | |
358 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
359 | return "a.out-sunos-big"; | |
ab3e48dc KH |
360 | else |
361 | return "a.out-sparc-little"; | |
252b5132 RH |
362 | #else |
363 | return "a.out-sunos-big"; | |
364 | #endif | |
365 | #endif | |
366 | #endif | |
367 | ||
252b5132 RH |
368 | #ifdef OBJ_COFF |
369 | #ifdef TE_LYNX | |
370 | return "coff-sparc-lynx"; | |
371 | #else | |
372 | return "coff-sparc"; | |
373 | #endif | |
374 | #endif | |
375 | ||
910600e9 RS |
376 | #ifdef TE_VXWORKS |
377 | return "elf32-sparc-vxworks"; | |
378 | #endif | |
379 | ||
252b5132 | 380 | #ifdef OBJ_ELF |
71a75f6f | 381 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
382 | #endif |
383 | ||
384 | abort (); | |
385 | } | |
386 | \f | |
e0c6ed95 | 387 | /* md_parse_option |
252b5132 RH |
388 | * Invocation line includes a switch not recognized by the base assembler. |
389 | * See if it's a processor-specific option. These are: | |
390 | * | |
391 | * -bump | |
392 | * Warn on architecture bumps. See also -A. | |
393 | * | |
d6787ef9 | 394 | * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet |
252b5132 | 395 | * Standard 32 bit architectures. |
19f7b010 | 396 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
397 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
398 | * This used to only mean 64 bits, but properly specifying it | |
399 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
400 | * specified orthogonally to word size (except when specifying | |
401 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
402 | * -Av8plus, -Av8plusa, -Av8plusb |
403 | * Same as -Av9{,a,b}. | |
404 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
405 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
406 | * assembler. | |
407 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
408 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 409 | * assembler. |
252b5132 RH |
410 | * |
411 | * Select the architecture and possibly the file format. | |
412 | * Instructions or features not supported by the selected | |
413 | * architecture cause fatal errors. | |
414 | * | |
415 | * The default is to start at v6, and bump the architecture up | |
416 | * whenever an instruction is seen at a higher level. In 32 bit | |
417 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 418 | * -Av8plus{,a,b}. |
252b5132 RH |
419 | * |
420 | * If -bump is specified, a warning is printing when bumping to | |
421 | * higher levels. | |
422 | * | |
423 | * If an architecture is specified, all instructions must match | |
424 | * that architecture. Any higher level instructions are flagged | |
425 | * as errors. Note that in the 32 bit environment specifying | |
426 | * -Av8plus does not automatically create a v8plus object file, a | |
427 | * v9 insn must be seen. | |
428 | * | |
429 | * If both an architecture and -bump are specified, the | |
430 | * architecture starts at the specified level, but bumps are | |
431 | * warnings. Note that we can't set `current_architecture' to | |
432 | * the requested level in this case: in the 32 bit environment, | |
433 | * we still must avoid creating v8plus object files unless v9 | |
434 | * insns are seen. | |
435 | * | |
436 | * Note: | |
437 | * Bumping between incompatible architectures is always an | |
438 | * error. For example, from sparclite to v9. | |
439 | */ | |
440 | ||
441 | #ifdef OBJ_ELF | |
5a38dc70 | 442 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
443 | #else |
444 | #ifdef OBJ_AOUT | |
5a38dc70 | 445 | const char *md_shortopts = "A:k"; |
252b5132 | 446 | #else |
5a38dc70 | 447 | const char *md_shortopts = "A:"; |
252b5132 RH |
448 | #endif |
449 | #endif | |
450 | struct option md_longopts[] = { | |
451 | #define OPTION_BUMP (OPTION_MD_BASE) | |
452 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
453 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
454 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
455 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
456 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
457 | #ifdef OBJ_ELF | |
458 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
459 | {"32", no_argument, NULL, OPTION_32}, | |
460 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
461 | {"64", no_argument, NULL, OPTION_64}, | |
462 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
463 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
464 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
465 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
466 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
467 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
468 | #endif | |
469 | #ifdef SPARC_BIENDIAN | |
470 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
471 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
472 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
473 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
474 | #endif | |
475 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
476 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
477 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
478 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
479 | #ifdef OBJ_ELF |
480 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
481 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
482 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
483 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 484 | #endif |
6faf3d66 JJ |
485 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
486 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
487 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
488 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
46a2d504 JM |
489 | #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16) |
490 | {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT}, | |
252b5132 RH |
491 | {NULL, no_argument, NULL, 0} |
492 | }; | |
e0c6ed95 AM |
493 | |
494 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
495 | |
496 | int | |
17b9d67d | 497 | md_parse_option (int c, const char *arg) |
252b5132 RH |
498 | { |
499 | /* We don't get a chance to initialize anything before we're called, | |
500 | so handle that now. */ | |
501 | if (! default_init_p) | |
502 | init_default_arch (); | |
503 | ||
504 | switch (c) | |
505 | { | |
506 | case OPTION_BUMP: | |
507 | warn_on_bump = 1; | |
508 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
509 | break; | |
510 | ||
511 | case OPTION_XARCH: | |
c2158c24 | 512 | #ifdef OBJ_ELF |
668b27ea | 513 | if (!strncmp (arg, "v9", 2)) |
c2158c24 | 514 | md_parse_option (OPTION_64, NULL); |
668b27ea DM |
515 | else |
516 | { | |
517 | if (!strncmp (arg, "v8", 2) | |
518 | || !strncmp (arg, "v7", 2) | |
519 | || !strncmp (arg, "v6", 2) | |
520 | || !strcmp (arg, "sparclet") | |
521 | || !strcmp (arg, "sparclite") | |
522 | || !strcmp (arg, "sparc86x")) | |
523 | md_parse_option (OPTION_32, NULL); | |
524 | } | |
c2158c24 | 525 | #endif |
e0c6ed95 | 526 | /* Fall through. */ |
252b5132 RH |
527 | |
528 | case 'A': | |
529 | { | |
530 | struct sparc_arch *sa; | |
531 | enum sparc_opcode_arch_val opcode_arch; | |
532 | ||
533 | sa = lookup_arch (arg); | |
534 | if (sa == NULL | |
535 | || ! sa->user_option_p) | |
536 | { | |
c2158c24 JJ |
537 | if (c == OPTION_XARCH) |
538 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
539 | else | |
540 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
541 | return 0; |
542 | } | |
543 | ||
544 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
545 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
546 | as_fatal (_("Bad opcode table, broken assembler.")); | |
547 | ||
4bafe00e DM |
548 | if (!architecture_requested |
549 | || opcode_arch > max_architecture) | |
550 | max_architecture = opcode_arch; | |
6884417a JM |
551 | |
552 | /* The allowed hardware capabilities are the implied by the | |
553 | opcodes arch plus any extra capabilities defined in the GAS | |
554 | arch. */ | |
555 | hwcap_allowed | |
556 | = (hwcap_allowed | |
557 | | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32) | |
558 | | (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | |
559 | | sparc_opcode_archs[opcode_arch].hwcaps | |
560 | | sa->hwcap_allowed); | |
252b5132 RH |
561 | architecture_requested = 1; |
562 | } | |
563 | break; | |
564 | ||
565 | case OPTION_SPARC: | |
566 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
567 | break; | |
568 | ||
569 | case OPTION_ENFORCE_ALIGNED_DATA: | |
570 | enforce_aligned_data = 1; | |
571 | break; | |
572 | ||
573 | #ifdef SPARC_BIENDIAN | |
574 | case OPTION_LITTLE_ENDIAN: | |
575 | target_big_endian = 0; | |
576 | if (default_arch_type != sparclet) | |
577 | as_fatal ("This target does not support -EL"); | |
578 | break; | |
579 | case OPTION_LITTLE_ENDIAN_DATA: | |
580 | target_little_endian_data = 1; | |
581 | target_big_endian = 0; | |
582 | if (default_arch_type != sparc86x | |
583 | && default_arch_type != v9) | |
584 | as_fatal ("This target does not support --little-endian-data"); | |
585 | break; | |
586 | case OPTION_BIG_ENDIAN: | |
587 | target_big_endian = 1; | |
588 | break; | |
589 | #endif | |
590 | ||
591 | #ifdef OBJ_AOUT | |
592 | case 'k': | |
593 | sparc_pic_code = 1; | |
594 | break; | |
595 | #endif | |
596 | ||
597 | #ifdef OBJ_ELF | |
598 | case OPTION_32: | |
599 | case OPTION_64: | |
600 | { | |
601 | const char **list, **l; | |
602 | ||
603 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
604 | list = bfd_target_list (); | |
605 | for (l = list; *l != NULL; l++) | |
606 | { | |
607 | if (sparc_arch_size == 32) | |
608 | { | |
71a75f6f | 609 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
610 | break; |
611 | } | |
612 | else | |
613 | { | |
71a75f6f | 614 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
615 | break; |
616 | } | |
617 | } | |
618 | if (*l == NULL) | |
619 | as_fatal (_("No compiled in support for %d bit object file format"), | |
620 | sparc_arch_size); | |
621 | free (list); | |
b7cac25f DM |
622 | |
623 | if (sparc_arch_size == 64 | |
624 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
625 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
626 | } |
627 | break; | |
628 | ||
629 | case OPTION_TSO: | |
630 | sparc_memory_model = MM_TSO; | |
631 | break; | |
632 | ||
633 | case OPTION_PSO: | |
634 | sparc_memory_model = MM_PSO; | |
635 | break; | |
636 | ||
637 | case OPTION_RMO: | |
638 | sparc_memory_model = MM_RMO; | |
639 | break; | |
640 | ||
641 | case 'V': | |
642 | print_version_id (); | |
643 | break; | |
644 | ||
645 | case 'Q': | |
646 | /* Qy - do emit .comment | |
e0c6ed95 | 647 | Qn - do not emit .comment. */ |
252b5132 RH |
648 | break; |
649 | ||
650 | case 's': | |
e0c6ed95 | 651 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
652 | break; |
653 | ||
654 | case 'q': | |
e0c6ed95 | 655 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
656 | break; |
657 | ||
658 | case 'K': | |
659 | if (strcmp (arg, "PIC") != 0) | |
660 | as_warn (_("Unrecognized option following -K")); | |
661 | else | |
662 | sparc_pic_code = 1; | |
663 | break; | |
6d8809aa RH |
664 | |
665 | case OPTION_NO_UNDECLARED_REGS: | |
666 | no_undeclared_regs = 1; | |
667 | break; | |
a25fe906 ILT |
668 | |
669 | case OPTION_UNDECLARED_REGS: | |
670 | no_undeclared_regs = 0; | |
671 | break; | |
252b5132 RH |
672 | #endif |
673 | ||
6faf3d66 JJ |
674 | case OPTION_RELAX: |
675 | sparc_relax = 1; | |
676 | break; | |
677 | ||
678 | case OPTION_NO_RELAX: | |
679 | sparc_relax = 0; | |
680 | break; | |
681 | ||
46a2d504 JM |
682 | case OPTION_DCTI_COUPLES_DETECT: |
683 | dcti_couples_detect = 1; | |
684 | break; | |
685 | ||
252b5132 RH |
686 | default: |
687 | return 0; | |
688 | } | |
689 | ||
690 | return 1; | |
691 | } | |
692 | ||
693 | void | |
5a49b8ac | 694 | md_show_usage (FILE *stream) |
252b5132 RH |
695 | { |
696 | const struct sparc_arch *arch; | |
c2158c24 | 697 | int column; |
252b5132 RH |
698 | |
699 | /* We don't get a chance to initialize anything before we're called, | |
700 | so handle that now. */ | |
701 | if (! default_init_p) | |
702 | init_default_arch (); | |
703 | ||
e0c6ed95 | 704 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 705 | column = 0; |
252b5132 RH |
706 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
707 | { | |
c2158c24 JJ |
708 | if (!arch->user_option_p) |
709 | continue; | |
252b5132 RH |
710 | if (arch != &sparc_arch_table[0]) |
711 | fprintf (stream, " | "); | |
07726851 | 712 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
713 | { |
714 | column = 0; | |
715 | fputc ('\n', stream); | |
716 | } | |
07726851 | 717 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 718 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 719 | } |
c2158c24 JJ |
720 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
721 | { | |
722 | if (!arch->user_option_p) | |
723 | continue; | |
724 | fprintf (stream, " | "); | |
07726851 | 725 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
726 | { |
727 | column = 0; | |
728 | fputc ('\n', stream); | |
729 | } | |
07726851 | 730 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
731 | fprintf (stream, "-xarch=%s", arch->name); |
732 | } | |
733 | fprintf (stream, _("\n\ | |
252b5132 RH |
734 | specify variant of SPARC architecture\n\ |
735 | -bump warn when assembler switches architectures\n\ | |
736 | -sparc ignored\n\ | |
6faf3d66 JJ |
737 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
738 | -relax relax jumps and branches (default)\n\ | |
739 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
740 | #ifdef OBJ_AOUT |
741 | fprintf (stream, _("\ | |
742 | -k generate PIC\n")); | |
743 | #endif | |
744 | #ifdef OBJ_ELF | |
745 | fprintf (stream, _("\ | |
746 | -32 create 32 bit object file\n\ | |
747 | -64 create 64 bit object file\n")); | |
748 | fprintf (stream, _("\ | |
749 | [default is %d]\n"), default_arch_size); | |
750 | fprintf (stream, _("\ | |
751 | -TSO use Total Store Ordering\n\ | |
752 | -PSO use Partial Store Ordering\n\ | |
753 | -RMO use Relaxed Memory Ordering\n")); | |
754 | fprintf (stream, _("\ | |
755 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
756 | fprintf (stream, _("\ | |
757 | -KPIC generate PIC\n\ | |
758 | -V print assembler version number\n\ | |
a25fe906 ILT |
759 | -undeclared-regs ignore application global register usage without\n\ |
760 | appropriate .register directive (default)\n\ | |
761 | -no-undeclared-regs force error on application global register usage\n\ | |
762 | without appropriate .register directive\n\ | |
46a2d504 | 763 | --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\ |
252b5132 RH |
764 | -q ignored\n\ |
765 | -Qy, -Qn ignored\n\ | |
766 | -s ignored\n")); | |
767 | #endif | |
768 | #ifdef SPARC_BIENDIAN | |
769 | fprintf (stream, _("\ | |
770 | -EL generate code for a little endian machine\n\ | |
771 | -EB generate code for a big endian machine\n\ | |
772 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 773 | instructions and little endian data.\n")); |
252b5132 RH |
774 | #endif |
775 | } | |
776 | \f | |
e0c6ed95 | 777 | /* Native operand size opcode translation. */ |
4f2a7b51 | 778 | static struct |
cf9a1301 | 779 | { |
e0471c16 TS |
780 | const char *name; |
781 | const char *name32; | |
782 | const char *name64; | |
cf9a1301 RH |
783 | } native_op_table[] = |
784 | { | |
785 | {"ldn", "ld", "ldx"}, | |
786 | {"ldna", "lda", "ldxa"}, | |
787 | {"stn", "st", "stx"}, | |
788 | {"stna", "sta", "stxa"}, | |
789 | {"slln", "sll", "sllx"}, | |
790 | {"srln", "srl", "srlx"}, | |
791 | {"sran", "sra", "srax"}, | |
792 | {"casn", "cas", "casx"}, | |
793 | {"casna", "casa", "casxa"}, | |
794 | {"clrn", "clr", "clrx"}, | |
795 | {NULL, NULL, NULL}, | |
796 | }; | |
797 | \f | |
10156f83 | 798 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
799 | |
800 | struct priv_reg_entry | |
ab3e48dc | 801 | { |
e0471c16 | 802 | const char *name; |
ab3e48dc KH |
803 | int regnum; |
804 | }; | |
252b5132 RH |
805 | |
806 | struct priv_reg_entry priv_reg_table[] = | |
807 | { | |
808 | {"tpc", 0}, | |
809 | {"tnpc", 1}, | |
810 | {"tstate", 2}, | |
811 | {"tt", 3}, | |
812 | {"tick", 4}, | |
813 | {"tba", 5}, | |
814 | {"pstate", 6}, | |
815 | {"tl", 7}, | |
816 | {"pil", 8}, | |
817 | {"cwp", 9}, | |
818 | {"cansave", 10}, | |
819 | {"canrestore", 11}, | |
820 | {"cleanwin", 12}, | |
821 | {"otherwin", 13}, | |
822 | {"wstate", 14}, | |
823 | {"fq", 15}, | |
10156f83 | 824 | {"gl", 16}, |
38074311 | 825 | {"pmcdper", 23}, |
252b5132 | 826 | {"ver", 31}, |
8b8c7c9f | 827 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
828 | }; |
829 | ||
10156f83 DM |
830 | struct priv_reg_entry hpriv_reg_table[] = |
831 | { | |
832 | {"hpstate", 0}, | |
833 | {"htstate", 1}, | |
834 | {"hintp", 3}, | |
835 | {"htba", 5}, | |
836 | {"hver", 6}, | |
96074adc JM |
837 | {"hmcdper", 23}, |
838 | {"hmcddfr", 24}, | |
839 | {"hva_mask_nz", 27}, | |
ec92c392 JM |
840 | {"hstick_offset", 28}, |
841 | {"hstick_enable", 29}, | |
10156f83 | 842 | {"hstick_cmpr", 31}, |
8b8c7c9f | 843 | {NULL, -1}, /* End marker. */ |
10156f83 DM |
844 | }; |
845 | ||
8b8c7c9f | 846 | /* v9a or later specific ancillary state registers. */ |
252b5132 RH |
847 | |
848 | struct priv_reg_entry v9a_asr_table[] = | |
849 | { | |
850 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
851 | {"sys_tick_cmpr", 25}, |
852 | {"sys_tick", 24}, | |
1a6b486f DM |
853 | {"stick_cmpr", 25}, |
854 | {"stick", 24}, | |
f04d18b7 DM |
855 | {"softint_clear", 21}, |
856 | {"softint_set", 20}, | |
2b661f3d | 857 | {"softint", 22}, |
252b5132 | 858 | {"set_softint", 20}, |
58004e23 | 859 | {"pause", 27}, |
252b5132 RH |
860 | {"pic", 17}, |
861 | {"pcr", 16}, | |
3d68f91c | 862 | {"mwait", 28}, |
252b5132 RH |
863 | {"gsr", 19}, |
864 | {"dcr", 18}, | |
2e52845b | 865 | {"cfr", 26}, |
252b5132 | 866 | {"clear_softint", 21}, |
8b8c7c9f | 867 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
868 | }; |
869 | ||
870 | static int | |
5a49b8ac | 871 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
872 | { |
873 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
874 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
875 | ||
8b8c7c9f JM |
876 | if (p->name == q->name) |
877 | return 0; | |
878 | else if (p->name == NULL) | |
879 | return 1; | |
880 | else if (q->name == NULL) | |
881 | return -1; | |
882 | else | |
883 | return strcmp (q->name, p->name); | |
884 | } | |
885 | \f | |
886 | /* sparc %-pseudo-operations. */ | |
887 | ||
888 | ||
889 | #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ | |
890 | #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative | |
891 | contexts. */ | |
892 | #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ | |
893 | #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the | |
894 | last operand of an | |
895 | instruction. (Generally they can appear | |
896 | anywhere an immediate operand is | |
897 | expected. */ | |
898 | struct pop_entry | |
899 | { | |
900 | /* The name as it appears in assembler. */ | |
901 | const char *name; | |
902 | /* The reloc this pseudo-op translates to. */ | |
9bceab41 | 903 | bfd_reloc_code_real_type reloc; |
8b8c7c9f JM |
904 | /* Flags. See F_POP_* above. */ |
905 | int flags; | |
906 | }; | |
907 | ||
908 | struct pop_entry pop_table[] = | |
909 | { | |
910 | { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, | |
911 | { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, | |
912 | { "hi", BFD_RELOC_HI22, F_POP_PCREL }, | |
913 | { "lo", BFD_RELOC_LO10, F_POP_PCREL }, | |
914 | { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, | |
915 | { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, | |
916 | { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, | |
917 | { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, | |
918 | { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, | |
919 | { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, | |
920 | { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
921 | { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, | |
922 | { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, | |
923 | { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
924 | { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, | |
925 | { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, | |
926 | { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, | |
927 | { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, | |
928 | { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, | |
929 | { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, | |
930 | { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, | |
931 | { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, | |
932 | { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, | |
933 | { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, | |
934 | { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, | |
935 | { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, | |
936 | { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, | |
937 | { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, | |
938 | { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, | |
939 | { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
940 | { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, | |
941 | { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
942 | { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, | |
943 | { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, | |
944 | { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, | |
945 | { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, | |
cf80913a | 946 | { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX } |
8b8c7c9f JM |
947 | }; |
948 | \f | |
949 | /* Table of %-names that can appear in a sparc assembly program. This | |
950 | table is initialized in md_begin and contains entries for each | |
951 | privileged/hyperprivileged/alternate register and %-pseudo-op. */ | |
952 | ||
953 | enum perc_entry_type | |
954 | { | |
955 | perc_entry_none = 0, | |
956 | perc_entry_reg, | |
957 | perc_entry_post_pop, | |
958 | perc_entry_imm_pop | |
959 | }; | |
960 | ||
961 | struct perc_entry | |
962 | { | |
963 | /* Entry type. */ | |
964 | enum perc_entry_type type; | |
965 | /* Name of the %-entity. */ | |
966 | const char *name; | |
967 | /* strlen (name). */ | |
968 | int len; | |
969 | /* Value. Either a pop or a reg depending on type.*/ | |
970 | union | |
971 | { | |
972 | struct pop_entry *pop; | |
973 | struct priv_reg_entry *reg; | |
974 | }; | |
975 | }; | |
976 | ||
977 | #define NUM_PERC_ENTRIES \ | |
978 | (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ | |
979 | + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ | |
980 | + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ | |
cf80913a | 981 | + ARRAY_SIZE (pop_table) \ |
8b8c7c9f JM |
982 | + 1) |
983 | ||
984 | struct perc_entry perc_table[NUM_PERC_ENTRIES]; | |
985 | ||
986 | static int | |
987 | cmp_perc_entry (const void *parg, const void *qarg) | |
988 | { | |
989 | const struct perc_entry *p = (const struct perc_entry *) parg; | |
990 | const struct perc_entry *q = (const struct perc_entry *) qarg; | |
991 | ||
992 | if (p->name == q->name) | |
993 | return 0; | |
994 | else if (p->name == NULL) | |
995 | return 1; | |
996 | else if (q->name == NULL) | |
997 | return -1; | |
998 | else | |
999 | return strcmp (q->name, p->name); | |
252b5132 RH |
1000 | } |
1001 | \f | |
1002 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
1003 | set up all the tables, etc. that the MD part of the assembler will |
1004 | need. */ | |
252b5132 RH |
1005 | |
1006 | void | |
5a49b8ac | 1007 | md_begin (void) |
252b5132 | 1008 | { |
ed9e98c2 | 1009 | const char *retval = NULL; |
252b5132 | 1010 | int lose = 0; |
ed9e98c2 | 1011 | unsigned int i = 0; |
252b5132 RH |
1012 | |
1013 | /* We don't get a chance to initialize anything before md_parse_option | |
1014 | is called, and it may not be called, so handle default initialization | |
1015 | now if not already done. */ | |
1016 | if (! default_init_p) | |
1017 | init_default_arch (); | |
1018 | ||
364b6d8b | 1019 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
1020 | op_hash = hash_new (); |
1021 | ||
1022 | while (i < (unsigned int) sparc_num_opcodes) | |
1023 | { | |
1024 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 1025 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
1026 | if (retval != NULL) |
1027 | { | |
cf9a1301 RH |
1028 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
1029 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
1030 | lose = 1; |
1031 | } | |
1032 | do | |
1033 | { | |
1034 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
1035 | { | |
cf9a1301 RH |
1036 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
1037 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
1038 | lose = 1; |
1039 | } | |
1040 | ++i; | |
1041 | } | |
1042 | while (i < (unsigned int) sparc_num_opcodes | |
1043 | && !strcmp (sparc_opcodes[i].name, name)); | |
1044 | } | |
1045 | ||
cf9a1301 RH |
1046 | for (i = 0; native_op_table[i].name; i++) |
1047 | { | |
1048 | const struct sparc_opcode *insn; | |
e0471c16 | 1049 | const char *name = ((sparc_arch_size == 32) |
3d4ae3c0 NC |
1050 | ? native_op_table[i].name32 |
1051 | : native_op_table[i].name64); | |
e0c6ed95 | 1052 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 1053 | if (insn == NULL) |
e0c6ed95 AM |
1054 | { |
1055 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
1056 | name, native_op_table[i].name); | |
1057 | lose = 1; | |
1058 | } | |
cf9a1301 RH |
1059 | else |
1060 | { | |
5a49b8ac AM |
1061 | retval = hash_insert (op_hash, native_op_table[i].name, |
1062 | (void *) insn); | |
cf9a1301 RH |
1063 | if (retval != NULL) |
1064 | { | |
1065 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
1066 | sparc_opcodes[i].name, retval); | |
1067 | lose = 1; | |
1068 | } | |
1069 | } | |
1070 | } | |
1071 | ||
252b5132 RH |
1072 | if (lose) |
1073 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1074 | ||
252b5132 RH |
1075 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
1076 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
8b8c7c9f JM |
1077 | qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), |
1078 | sizeof (hpriv_reg_table[0]), cmp_reg_entry); | |
1079 | qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), | |
1080 | sizeof (v9a_asr_table[0]), cmp_reg_entry); | |
1081 | ||
252b5132 RH |
1082 | /* If -bump, record the architecture level at which we start issuing |
1083 | warnings. The behaviour is different depending upon whether an | |
1084 | architecture was explicitly specified. If it wasn't, we issue warnings | |
1085 | for all upwards bumps. If it was, we don't start issuing warnings until | |
1086 | we need to bump beyond the requested architecture or when we bump between | |
1087 | conflicting architectures. */ | |
1088 | ||
1089 | if (warn_on_bump | |
1090 | && architecture_requested) | |
1091 | { | |
1092 | /* `max_architecture' records the requested architecture. | |
1093 | Issue warnings if we go above it. */ | |
1094 | warn_after_architecture = max_architecture; | |
252b5132 | 1095 | } |
75ac3a7f JM |
1096 | |
1097 | /* Find the highest architecture level that doesn't conflict with | |
1098 | the requested one. */ | |
1099 | ||
1100 | if (warn_on_bump | |
1101 | || !architecture_requested) | |
1102 | { | |
1103 | enum sparc_opcode_arch_val current_max_architecture | |
1104 | = max_architecture; | |
1105 | ||
1106 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
1107 | max_architecture > warn_after_architecture; | |
1108 | --max_architecture) | |
1109 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
1110 | current_max_architecture)) | |
1111 | break; | |
1112 | } | |
8b8c7c9f JM |
1113 | |
1114 | /* Prepare the tables of %-pseudo-ops. */ | |
1115 | { | |
1116 | struct priv_reg_entry *reg_tables[] | |
1117 | = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; | |
1118 | struct priv_reg_entry **reg_table; | |
1119 | int entry = 0; | |
1120 | ||
1121 | /* Add registers. */ | |
1122 | for (reg_table = reg_tables; reg_table[0]; reg_table++) | |
1123 | { | |
1124 | struct priv_reg_entry *reg; | |
1125 | for (reg = *reg_table; reg->name; reg++) | |
1126 | { | |
1127 | struct perc_entry *p = &perc_table[entry++]; | |
1128 | p->type = perc_entry_reg; | |
1129 | p->name = reg->name; | |
1130 | p->len = strlen (reg->name); | |
1131 | p->reg = reg; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | /* Add %-pseudo-ops. */ | |
cf80913a TS |
1136 | for (i = 0; i < ARRAY_SIZE (pop_table); i++) |
1137 | { | |
1138 | struct perc_entry *p = &perc_table[entry++]; | |
1139 | p->type = (pop_table[i].flags & F_POP_POSTFIX | |
1140 | ? perc_entry_post_pop : perc_entry_imm_pop); | |
1141 | p->name = pop_table[i].name; | |
1142 | p->len = strlen (pop_table[i].name); | |
1143 | p->pop = &pop_table[i]; | |
1144 | } | |
8b8c7c9f | 1145 | |
33eaf5de | 1146 | /* Last entry is the sentinel. */ |
8b8c7c9f JM |
1147 | perc_table[entry].type = perc_entry_none; |
1148 | ||
1149 | qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), | |
1150 | sizeof (perc_table[0]), cmp_perc_entry); | |
1151 | ||
1152 | } | |
252b5132 RH |
1153 | } |
1154 | ||
1155 | /* Called after all assembly has been done. */ | |
1156 | ||
1157 | void | |
5a49b8ac | 1158 | sparc_md_end (void) |
252b5132 | 1159 | { |
d85815e2 | 1160 | unsigned long mach; |
daf5e10e | 1161 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
3d68f91c | 1162 | int hwcaps, hwcaps2; |
daf5e10e | 1163 | #endif |
19f7b010 | 1164 | |
252b5132 | 1165 | if (sparc_arch_size == 64) |
19f7b010 JJ |
1166 | switch (current_architecture) |
1167 | { | |
1168 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
1169 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
7a10c22f JM |
1170 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; |
1171 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; | |
1172 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; | |
1173 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; | |
1174 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; | |
64517994 | 1175 | case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v9m8; break; |
19f7b010 JJ |
1176 | default: mach = bfd_mach_sparc_v9; break; |
1177 | } | |
252b5132 | 1178 | else |
19f7b010 JJ |
1179 | switch (current_architecture) |
1180 | { | |
1181 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
1182 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
1183 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
1184 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
7a10c22f JM |
1185 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; |
1186 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; | |
1187 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; | |
1188 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; | |
1189 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; | |
64517994 | 1190 | case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v8plusm8; break; |
19f7b010 JJ |
1191 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't |
1192 | be but for now it is (since that's the way it's always been | |
1193 | treated). */ | |
d85815e2 | 1194 | default: mach = bfd_mach_sparc; break; |
19f7b010 JJ |
1195 | } |
1196 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
1197 | |
1198 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
3d68f91c JM |
1199 | hwcaps = hwcap_seen & U0xffffffff; |
1200 | hwcaps2 = hwcap_seen >> 32; | |
1201 | ||
1202 | if (hwcaps) | |
1203 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); | |
1204 | if (hwcaps2) | |
1205 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); | |
9e8c70f9 | 1206 | #endif |
252b5132 RH |
1207 | } |
1208 | \f | |
1209 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
1210 | ||
5a49b8ac AM |
1211 | static inline int |
1212 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1213 | { |
1214 | if (max <= 0) | |
1215 | abort (); | |
1216 | /* Sign-extend the value from the architecture word size, so that | |
1217 | 0xffffffff is always considered -1 on sparc32. */ | |
1218 | if (sparc_arch_size == 32) | |
1219 | { | |
e0c6ed95 | 1220 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 1221 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
1222 | } |
1223 | if (val > max) | |
1224 | return 0; | |
1225 | if (val < ~max) | |
1226 | return 0; | |
1227 | return 1; | |
1228 | } | |
1229 | ||
1230 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
1231 | ||
5a49b8ac AM |
1232 | static inline int |
1233 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
1234 | { |
1235 | if (val > max) | |
1236 | return 0; | |
1237 | return 1; | |
1238 | } | |
1239 | ||
1240 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
1241 | (e.g. -15 to +31). */ | |
1242 | ||
5a49b8ac AM |
1243 | static inline int |
1244 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1245 | { |
1246 | if (max <= 0) | |
1247 | abort (); | |
1248 | if (val > max) | |
1249 | return 0; | |
1250 | if (val < ~(max >> 1)) | |
1251 | return 0; | |
1252 | return 1; | |
1253 | } | |
1254 | ||
1255 | static int | |
5a49b8ac | 1256 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1257 | { |
1258 | int i; | |
1259 | ||
1260 | if (mask == 0) | |
1261 | return -1; | |
1262 | ||
1263 | for (i = 0; (mask & 1) == 0; ++i) | |
1264 | mask >>= 1; | |
1265 | return i; | |
1266 | } | |
1267 | ||
1268 | /* Implement big shift right. */ | |
1269 | static bfd_vma | |
5a49b8ac | 1270 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1271 | { |
1272 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1273 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1274 | return val >> amount; | |
1275 | } | |
1276 | \f | |
1277 | /* For communication between sparc_ip and get_expression. */ | |
1278 | static char *expr_end; | |
1279 | ||
252b5132 | 1280 | /* Values for `special_case'. |
2b0f3761 | 1281 | Instructions that require weird handling because they're longer than |
252b5132 RH |
1282 | 4 bytes. */ |
1283 | #define SPECIAL_CASE_NONE 0 | |
1284 | #define SPECIAL_CASE_SET 1 | |
1285 | #define SPECIAL_CASE_SETSW 2 | |
1286 | #define SPECIAL_CASE_SETX 3 | |
1287 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1288 | #define SPECIAL_CASE_FDIV 4 | |
1289 | ||
1290 | /* Bit masks of various insns. */ | |
1291 | #define NOP_INSN 0x01000000 | |
1292 | #define OR_INSN 0x80100000 | |
63fab58c | 1293 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1294 | #define FMOVS_INSN 0x81A00020 |
1295 | #define SETHI_INSN 0x01000000 | |
1296 | #define SLLX_INSN 0x81281000 | |
1297 | #define SRA_INSN 0x81380000 | |
1298 | ||
1299 | /* The last instruction to be assembled. */ | |
1300 | static const struct sparc_opcode *last_insn; | |
1301 | /* The assembled opcode of `last_insn'. */ | |
1302 | static unsigned long last_opcode; | |
1303 | \f | |
a22b281c | 1304 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1305 | |
a22b281c | 1306 | static void |
5a49b8ac | 1307 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1308 | { |
1309 | int need_hi22_p = 0; | |
1310 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1311 | ||
1312 | if (the_insn.exp.X_op == O_constant) | |
1313 | { | |
1314 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1315 | { | |
e0c6ed95 | 1316 | if (sizeof (offsetT) > 4 |
a22b281c | 1317 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1318 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1319 | as_warn (_("set: number not in 0..4294967295 range")); |
1320 | } | |
1321 | else | |
1322 | { | |
e0c6ed95 | 1323 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1324 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1325 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1326 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1327 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1328 | } |
1329 | } | |
1330 | ||
1331 | /* See if operand is absolute and small; skip sethi if so. */ | |
1332 | if (the_insn.exp.X_op != O_constant | |
1333 | || the_insn.exp.X_add_number >= (1 << 12) | |
1334 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1335 | { | |
1336 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1337 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1338 | & (the_insn.exp.X_op == O_constant |
1339 | ? 0x3fffff : 0))); | |
a22b281c | 1340 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1341 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1342 | output_insn (insn, &the_insn); |
1343 | need_hi22_p = 1; | |
1344 | } | |
1345 | ||
1346 | /* See if operand has no low-order bits; skip OR if so. */ | |
1347 | if (the_insn.exp.X_op != O_constant | |
1348 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1349 | || ! need_hi22_p) | |
1350 | { | |
1351 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1352 | | RD (rd) | IMMED | |
1353 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1354 | & (the_insn.exp.X_op != O_constant |
1355 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1356 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1357 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1358 | output_insn (insn, &the_insn); |
1359 | } | |
1360 | } | |
e0c6ed95 | 1361 | |
a22b281c | 1362 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1363 | |
a22b281c | 1364 | static void |
5a49b8ac | 1365 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1366 | { |
1367 | int low32, rd, opc; | |
1368 | ||
1369 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1370 | ||
1371 | if (the_insn.exp.X_op != O_constant) | |
1372 | { | |
1373 | synthetize_setuw (insn); | |
1374 | ||
1375 | /* Need to sign extend it. */ | |
1376 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1377 | the_insn.reloc = BFD_RELOC_NONE; | |
1378 | output_insn (insn, &the_insn); | |
1379 | return; | |
1380 | } | |
1381 | ||
e0c6ed95 | 1382 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1383 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1384 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1385 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1386 | ||
e0c6ed95 AM |
1387 | low32 = the_insn.exp.X_add_number; |
1388 | ||
a22b281c RH |
1389 | if (low32 >= 0) |
1390 | { | |
1391 | synthetize_setuw (insn); | |
1392 | return; | |
1393 | } | |
1394 | ||
1395 | opc = OR_INSN; | |
e0c6ed95 | 1396 | |
a22b281c RH |
1397 | the_insn.reloc = BFD_RELOC_NONE; |
1398 | /* See if operand is absolute and small; skip sethi if so. */ | |
1399 | if (low32 < -(1 << 12)) | |
1400 | { | |
1401 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1402 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1403 | output_insn (insn, &the_insn); | |
1404 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1405 | opc = RS1 (rd) | XOR_INSN; | |
1406 | } | |
1407 | ||
1408 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1409 | | (low32 & 0x1fff)); | |
1410 | output_insn (insn, &the_insn); | |
1411 | } | |
1412 | ||
0d495746 | 1413 | /* Handle the setx synthetic instruction. */ |
e0c6ed95 | 1414 | |
a22b281c | 1415 | static void |
5a49b8ac | 1416 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1417 | { |
1418 | int upper32, lower32; | |
1419 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1420 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1421 | int upper_dstreg; | |
1422 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1423 | int need_xor10_p = 0; | |
e0c6ed95 | 1424 | |
6c1b24e4 | 1425 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1426 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1427 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1428 | #undef SIGNEXT32 | |
1429 | ||
1430 | upper_dstreg = tmpreg; | |
1431 | /* The tmp reg should not be the dst reg. */ | |
1432 | if (tmpreg == dstreg) | |
1433 | as_warn (_("setx: temporary register same as destination register")); | |
1434 | ||
1435 | /* ??? Obviously there are other optimizations we can do | |
1436 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1437 | doing some of these. Later. If you do change things, try to | |
1438 | change all of this to be table driven as well. */ | |
1439 | /* What to output depends on the number if it's constant. | |
1440 | Compute that first, then output what we've decided upon. */ | |
1441 | if (the_insn.exp.X_op != O_constant) | |
1442 | { | |
1443 | if (sparc_arch_size == 32) | |
1444 | { | |
1445 | /* When arch size is 32, we want setx to be equivalent | |
1446 | to setuw for anything but constants. */ | |
1447 | the_insn.exp.X_add_number &= 0xffffffff; | |
1448 | synthetize_setuw (insn); | |
1449 | return; | |
1450 | } | |
1451 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1452 | lower32 = 0; |
1453 | upper32 = 0; | |
a22b281c RH |
1454 | } |
1455 | else | |
1456 | { | |
1457 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1458 | Otherwise fixup_segment will complain about not being able to | |
1459 | write an 8 byte number in a 4 byte field. */ | |
1460 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1461 | |
a22b281c RH |
1462 | /* Only need hh22 if `or' insn can't handle constant. */ |
1463 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1464 | need_hh22_p = 1; | |
e0c6ed95 | 1465 | |
a22b281c RH |
1466 | /* Does bottom part (after sethi) have bits? */ |
1467 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1468 | /* No hh22, but does upper32 still have bits we can't set | |
1469 | from lower32? */ | |
1470 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1471 | need_hm10_p = 1; | |
e0c6ed95 | 1472 | |
a22b281c RH |
1473 | /* If the lower half is all zero, we build the upper half directly |
1474 | into the dst reg. */ | |
1475 | if (lower32 != 0 | |
1476 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1477 | || (! need_hh22_p && ! need_hm10_p)) | |
1478 | { | |
1479 | /* No need for sethi if `or' insn can handle constant. */ | |
1480 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1481 | /* Note that we can't use a negative constant in the `or' | |
1482 | insn unless the upper 32 bits are all ones. */ | |
1483 | || (lower32 < 0 && upper32 != -1) | |
1484 | || (lower32 >= 0 && upper32 == -1)) | |
1485 | need_hi22_p = 1; | |
e0c6ed95 | 1486 | |
a22b281c RH |
1487 | if (need_hi22_p && upper32 == -1) |
1488 | need_xor10_p = 1; | |
1489 | ||
1490 | /* Does bottom part (after sethi) have bits? */ | |
1491 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1492 | /* No sethi. */ | |
1493 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1494 | /* Need `or' if we didn't set anything else. */ | |
1495 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1496 | need_lo10_p = 1; | |
1497 | } | |
1498 | else | |
1499 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1500 | upper_dstreg = dstreg; | |
1501 | } | |
e0c6ed95 | 1502 | |
a22b281c RH |
1503 | if (!upper_dstreg && dstreg) |
1504 | as_warn (_("setx: illegal temporary register g0")); | |
1505 | ||
1506 | if (need_hh22_p) | |
1507 | { | |
1508 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1509 | | ((upper32 >> 10) & 0x3fffff)); | |
1510 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1511 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1512 | output_insn (insn, &the_insn); | |
1513 | } | |
e0c6ed95 | 1514 | |
a22b281c RH |
1515 | if (need_hi22_p) |
1516 | { | |
1517 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1518 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1519 | >> 10) & 0x3fffff)); |
a22b281c RH |
1520 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1521 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1522 | output_insn (insn, &the_insn); | |
1523 | } | |
1524 | ||
1525 | if (need_hm10_p) | |
1526 | { | |
1527 | the_insn.opcode = (OR_INSN | |
1528 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1529 | | RD (upper_dstreg) | |
1530 | | IMMED | |
1531 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1532 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1533 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1534 | output_insn (insn, &the_insn); | |
1535 | } | |
e0c6ed95 | 1536 | |
a22b281c RH |
1537 | if (need_lo10_p) |
1538 | { | |
1539 | /* FIXME: One nice optimization to do here is to OR the low part | |
1540 | with the highpart if hi22 isn't needed and the low part is | |
1541 | positive. */ | |
1542 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1543 | | RD (dstreg) | |
1544 | | IMMED | |
1545 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1546 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1547 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1548 | output_insn (insn, &the_insn); | |
1549 | } | |
e0c6ed95 | 1550 | |
a22b281c RH |
1551 | /* If we needed to build the upper part, shift it into place. */ |
1552 | if (need_hh22_p || need_hm10_p) | |
1553 | { | |
1554 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1555 | | IMMED | 32); | |
1556 | the_insn.reloc = BFD_RELOC_NONE; | |
1557 | output_insn (insn, &the_insn); | |
1558 | } | |
e0c6ed95 | 1559 | |
a22b281c RH |
1560 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1561 | if (need_xor10_p) | |
1562 | { | |
1563 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1564 | | 0x1c00 | (lower32 & 0x3ff)); | |
1565 | the_insn.reloc = BFD_RELOC_NONE; | |
1566 | output_insn (insn, &the_insn); | |
1567 | } | |
1568 | ||
1569 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1570 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1571 | { | |
1572 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1573 | | RD (dstreg)); | |
1574 | the_insn.reloc = BFD_RELOC_NONE; | |
1575 | output_insn (insn, &the_insn); | |
1576 | } | |
1577 | } | |
1578 | \f | |
252b5132 RH |
1579 | /* Main entry point to assemble one instruction. */ |
1580 | ||
1581 | void | |
5a49b8ac | 1582 | md_assemble (char *str) |
252b5132 RH |
1583 | { |
1584 | const struct sparc_opcode *insn; | |
a22b281c | 1585 | int special_case; |
252b5132 RH |
1586 | |
1587 | know (str); | |
a22b281c | 1588 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1589 | if (insn == NULL) |
1590 | return; | |
252b5132 | 1591 | |
46a2d504 JM |
1592 | /* Certain instructions may not appear on delay slots. Check for |
1593 | these situations. */ | |
b0825cc2 | 1594 | if (last_insn != NULL |
46a2d504 JM |
1595 | && (last_insn->flags & F_DELAYED) != 0) |
1596 | { | |
1597 | /* Before SPARC V9 the effect of having a delayed branch | |
1598 | instruction in the delay slot of a conditional delayed branch | |
1599 | was undefined. | |
1600 | ||
1601 | In SPARC V9 DCTI couples are well defined. | |
1602 | ||
1603 | However, starting with the UltraSPARC Architecture 2005, DCTI | |
1604 | couples (of all kind) are deprecated and should not be used, | |
1605 | as they may be slow or behave differently to what the | |
1606 | programmer expects. */ | |
1607 | if (dcti_couples_detect | |
1608 | && (insn->flags & F_DELAYED) != 0 | |
1609 | && ((max_architecture < SPARC_OPCODE_ARCH_V9 | |
1610 | && (last_insn->flags & F_CONDBR) != 0) | |
1611 | || max_architecture >= SPARC_OPCODE_ARCH_V9C)) | |
1612 | as_warn (_("unpredictable DCTI couple")); | |
1613 | ||
1614 | ||
1615 | /* We warn about attempts to put a floating point branch in a | |
1616 | delay slot, unless the delay slot has been annulled. */ | |
1617 | if ((insn->flags & F_FBR) != 0 | |
1618 | /* ??? This test isn't completely accurate. We assume anything with | |
1619 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1620 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1621 | || (last_opcode & ANNUL) == 0)) | |
1622 | as_warn (_("FP branch in delay slot")); | |
1623 | } | |
252b5132 RH |
1624 | |
1625 | /* SPARC before v9 requires a nop instruction between a floating | |
1626 | point instruction and a floating point branch. We insert one | |
1627 | automatically, with a warning. */ | |
1628 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1629 | && last_insn != NULL |
1630 | && (insn->flags & F_FBR) != 0 | |
1631 | && (last_insn->flags & F_FLOAT) != 0) | |
1632 | { | |
1633 | struct sparc_it nop_insn; | |
1634 | ||
1635 | nop_insn.opcode = NOP_INSN; | |
1636 | nop_insn.reloc = BFD_RELOC_NONE; | |
1637 | output_insn (insn, &nop_insn); | |
1638 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1639 | } | |
1640 | ||
a22b281c RH |
1641 | switch (special_case) |
1642 | { | |
1643 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1644 | /* Normal insn. */ |
a22b281c RH |
1645 | output_insn (insn, &the_insn); |
1646 | break; | |
252b5132 | 1647 | |
a22b281c RH |
1648 | case SPECIAL_CASE_SETSW: |
1649 | synthetize_setsw (insn); | |
1650 | break; | |
e0c6ed95 | 1651 | |
a22b281c RH |
1652 | case SPECIAL_CASE_SET: |
1653 | synthetize_setuw (insn); | |
1654 | break; | |
252b5132 | 1655 | |
a22b281c RH |
1656 | case SPECIAL_CASE_SETX: |
1657 | synthetize_setx (insn); | |
1658 | break; | |
e0c6ed95 | 1659 | |
a22b281c RH |
1660 | case SPECIAL_CASE_FDIV: |
1661 | { | |
1662 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1663 | |
a22b281c | 1664 | output_insn (insn, &the_insn); |
e0c6ed95 | 1665 | |
a22b281c RH |
1666 | /* According to information leaked from Sun, the "fdiv" instructions |
1667 | on early SPARC machines would produce incorrect results sometimes. | |
1668 | The workaround is to add an fmovs of the destination register to | |
1669 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1670 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1671 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1672 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1673 | output_insn (insn, &the_insn); | |
1674 | return; | |
1675 | } | |
e0c6ed95 | 1676 | |
a22b281c RH |
1677 | default: |
1678 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1679 | } |
1680 | } | |
1681 | ||
4bafe00e | 1682 | static const char * |
3d68f91c | 1683 | get_hwcap_name (bfd_uint64_t mask) |
4bafe00e | 1684 | { |
ec668d69 | 1685 | if (mask & HWCAP_MUL32) |
4bafe00e | 1686 | return "mul32"; |
ec668d69 | 1687 | if (mask & HWCAP_DIV32) |
4bafe00e | 1688 | return "div32"; |
ec668d69 | 1689 | if (mask & HWCAP_FSMULD) |
4bafe00e | 1690 | return "fsmuld"; |
ec668d69 | 1691 | if (mask & HWCAP_V8PLUS) |
4bafe00e | 1692 | return "v8plus"; |
ec668d69 | 1693 | if (mask & HWCAP_POPC) |
4bafe00e | 1694 | return "popc"; |
ec668d69 | 1695 | if (mask & HWCAP_VIS) |
4bafe00e | 1696 | return "vis"; |
ec668d69 | 1697 | if (mask & HWCAP_VIS2) |
4bafe00e | 1698 | return "vis2"; |
ec668d69 | 1699 | if (mask & HWCAP_ASI_BLK_INIT) |
4bafe00e | 1700 | return "ASIBlkInit"; |
ec668d69 | 1701 | if (mask & HWCAP_FMAF) |
4bafe00e | 1702 | return "fmaf"; |
ec668d69 | 1703 | if (mask & HWCAP_VIS3) |
4bafe00e | 1704 | return "vis3"; |
ec668d69 | 1705 | if (mask & HWCAP_HPC) |
4bafe00e | 1706 | return "hpc"; |
ec668d69 | 1707 | if (mask & HWCAP_RANDOM) |
4bafe00e | 1708 | return "random"; |
ec668d69 | 1709 | if (mask & HWCAP_TRANS) |
4bafe00e | 1710 | return "trans"; |
ec668d69 | 1711 | if (mask & HWCAP_FJFMAU) |
4bafe00e | 1712 | return "fjfmau"; |
ec668d69 | 1713 | if (mask & HWCAP_IMA) |
4bafe00e | 1714 | return "ima"; |
ec668d69 | 1715 | if (mask & HWCAP_ASI_CACHE_SPARING) |
4bafe00e | 1716 | return "cspare"; |
ec668d69 DM |
1717 | if (mask & HWCAP_AES) |
1718 | return "aes"; | |
1719 | if (mask & HWCAP_DES) | |
1720 | return "des"; | |
1721 | if (mask & HWCAP_KASUMI) | |
1722 | return "kasumi"; | |
1723 | if (mask & HWCAP_CAMELLIA) | |
1724 | return "camellia"; | |
1725 | if (mask & HWCAP_MD5) | |
1726 | return "md5"; | |
1727 | if (mask & HWCAP_SHA1) | |
1728 | return "sha1"; | |
1729 | if (mask & HWCAP_SHA256) | |
1730 | return "sha256"; | |
1731 | if (mask & HWCAP_SHA512) | |
1732 | return "sha512"; | |
1733 | if (mask & HWCAP_MPMUL) | |
1734 | return "mpmul"; | |
1735 | if (mask & HWCAP_MONT) | |
1736 | return "mont"; | |
1737 | if (mask & HWCAP_PAUSE) | |
1738 | return "pause"; | |
1739 | if (mask & HWCAP_CBCOND) | |
1740 | return "cbcond"; | |
1741 | if (mask & HWCAP_CRC32C) | |
1742 | return "crc32c"; | |
3d68f91c JM |
1743 | |
1744 | mask = mask >> 32; | |
1745 | if (mask & HWCAP2_FJATHPLUS) | |
1746 | return "fjathplus"; | |
1747 | if (mask & HWCAP2_VIS3B) | |
1748 | return "vis3b"; | |
1749 | if (mask & HWCAP2_ADP) | |
1750 | return "adp"; | |
1751 | if (mask & HWCAP2_SPARC5) | |
1752 | return "sparc5"; | |
1753 | if (mask & HWCAP2_MWAIT) | |
1754 | return "mwait"; | |
1755 | if (mask & HWCAP2_XMPMUL) | |
1756 | return "xmpmul"; | |
1757 | if (mask & HWCAP2_XMONT) | |
1758 | return "xmont"; | |
1759 | if (mask & HWCAP2_NSEC) | |
1760 | return "nsec"; | |
64517994 JM |
1761 | if (mask & HWCAP2_SPARC6) |
1762 | return "sparc6"; | |
1763 | if (mask & HWCAP2_ONADDSUB) | |
1764 | return "onaddsub"; | |
1765 | if (mask & HWCAP2_ONMUL) | |
1766 | return "onmul"; | |
1767 | if (mask & HWCAP2_ONDIV) | |
1768 | return "ondiv"; | |
1769 | if (mask & HWCAP2_DICTUNP) | |
1770 | return "dictunp"; | |
1771 | if (mask & HWCAP2_FPCMPSHL) | |
1772 | return "fpcmpshl"; | |
1773 | if (mask & HWCAP2_RLE) | |
1774 | return "rle"; | |
1775 | if (mask & HWCAP2_SHA3) | |
1776 | return "sha3"; | |
3d68f91c | 1777 | |
4bafe00e DM |
1778 | return "UNKNOWN"; |
1779 | } | |
1780 | ||
252b5132 RH |
1781 | /* Subroutine of md_assemble to do the actual parsing. */ |
1782 | ||
a22b281c | 1783 | static int |
5a49b8ac | 1784 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 | 1785 | { |
e0471c16 | 1786 | const char *error_message = ""; |
252b5132 RH |
1787 | char *s; |
1788 | const char *args; | |
1789 | char c; | |
1790 | const struct sparc_opcode *insn; | |
1791 | char *argsStart; | |
1792 | unsigned long opcode; | |
1793 | unsigned int mask = 0; | |
1794 | int match = 0; | |
1795 | int comma = 0; | |
1796 | int v9_arg_p; | |
a22b281c | 1797 | int special_case = SPECIAL_CASE_NONE; |
1e9d41d4 | 1798 | const sparc_asi *sasi = NULL; |
252b5132 RH |
1799 | |
1800 | s = str; | |
3882b010 | 1801 | if (ISLOWER (*s)) |
252b5132 RH |
1802 | { |
1803 | do | |
1804 | ++s; | |
6cda1326 | 1805 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
252b5132 RH |
1806 | } |
1807 | ||
1808 | switch (*s) | |
1809 | { | |
1810 | case '\0': | |
1811 | break; | |
1812 | ||
1813 | case ',': | |
1814 | comma = 1; | |
e0c6ed95 | 1815 | /* Fall through. */ |
252b5132 RH |
1816 | |
1817 | case ' ': | |
1818 | *s++ = '\0'; | |
1819 | break; | |
1820 | ||
1821 | default: | |
b0825cc2 DM |
1822 | as_bad (_("Unknown opcode: `%s'"), str); |
1823 | *pinsn = NULL; | |
1824 | return special_case; | |
252b5132 RH |
1825 | } |
1826 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1827 | *pinsn = insn; | |
1828 | if (insn == NULL) | |
1829 | { | |
1830 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1831 | return special_case; |
252b5132 RH |
1832 | } |
1833 | if (comma) | |
1834 | { | |
1835 | *--s = ','; | |
1836 | } | |
1837 | ||
1838 | argsStart = s; | |
1839 | for (;;) | |
1840 | { | |
1841 | opcode = insn->match; | |
1842 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1843 | the_insn.reloc = BFD_RELOC_NONE; | |
1844 | v9_arg_p = 0; | |
1845 | ||
e0c6ed95 AM |
1846 | /* Build the opcode, checking as we go to make sure that the |
1847 | operands match. */ | |
252b5132 RH |
1848 | for (args = insn->args;; ++args) |
1849 | { | |
1850 | switch (*args) | |
1851 | { | |
1852 | case 'K': | |
1853 | { | |
1854 | int kmask = 0; | |
1855 | ||
1856 | /* Parse a series of masks. */ | |
1857 | if (*s == '#') | |
1858 | { | |
1859 | while (*s == '#') | |
1860 | { | |
91d6fa6a | 1861 | int jmask; |
252b5132 RH |
1862 | |
1863 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1864 | &jmask)) |
252b5132 RH |
1865 | { |
1866 | error_message = _(": invalid membar mask name"); | |
1867 | goto error; | |
1868 | } | |
91d6fa6a | 1869 | kmask |= jmask; |
47926f60 KH |
1870 | while (*s == ' ') |
1871 | ++s; | |
252b5132 RH |
1872 | if (*s == '|' || *s == '+') |
1873 | ++s; | |
47926f60 KH |
1874 | while (*s == ' ') |
1875 | ++s; | |
252b5132 RH |
1876 | } |
1877 | } | |
1878 | else | |
1879 | { | |
1880 | if (! parse_const_expr_arg (&s, &kmask)) | |
1881 | { | |
1882 | error_message = _(": invalid membar mask expression"); | |
1883 | goto error; | |
1884 | } | |
1885 | if (kmask < 0 || kmask > 127) | |
1886 | { | |
1887 | error_message = _(": invalid membar mask number"); | |
1888 | goto error; | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | opcode |= MEMBAR (kmask); | |
1893 | continue; | |
1894 | } | |
1895 | ||
19f7b010 JJ |
1896 | case '3': |
1897 | { | |
1898 | int smask = 0; | |
1899 | ||
1900 | if (! parse_const_expr_arg (&s, &smask)) | |
1901 | { | |
1902 | error_message = _(": invalid siam mode expression"); | |
1903 | goto error; | |
1904 | } | |
1905 | if (smask < 0 || smask > 7) | |
1906 | { | |
1907 | error_message = _(": invalid siam mode number"); | |
1908 | goto error; | |
1909 | } | |
1910 | opcode |= smask; | |
1911 | continue; | |
1912 | } | |
1913 | ||
252b5132 RH |
1914 | case '*': |
1915 | { | |
1916 | int fcn = 0; | |
1917 | ||
1918 | /* Parse a prefetch function. */ | |
1919 | if (*s == '#') | |
1920 | { | |
1921 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1922 | { | |
1923 | error_message = _(": invalid prefetch function name"); | |
1924 | goto error; | |
1925 | } | |
1926 | } | |
1927 | else | |
1928 | { | |
1929 | if (! parse_const_expr_arg (&s, &fcn)) | |
1930 | { | |
1931 | error_message = _(": invalid prefetch function expression"); | |
1932 | goto error; | |
1933 | } | |
1934 | if (fcn < 0 || fcn > 31) | |
1935 | { | |
1936 | error_message = _(": invalid prefetch function number"); | |
1937 | goto error; | |
1938 | } | |
1939 | } | |
1940 | opcode |= RD (fcn); | |
1941 | continue; | |
1942 | } | |
1943 | ||
1944 | case '!': | |
1945 | case '?': | |
1946 | /* Parse a sparc64 privileged register. */ | |
1947 | if (*s == '%') | |
1948 | { | |
8b8c7c9f | 1949 | struct priv_reg_entry *p; |
e0c6ed95 | 1950 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1951 | |
1952 | s += 1; | |
8b8c7c9f JM |
1953 | for (p = priv_reg_table; p->name; p++) |
1954 | if (p->name[0] == s[0]) | |
1955 | { | |
1956 | len = strlen (p->name); | |
1957 | if (strncmp (p->name, s, len) == 0) | |
1958 | break; | |
1959 | } | |
1960 | ||
1961 | if (!p->name) | |
252b5132 RH |
1962 | { |
1963 | error_message = _(": unrecognizable privileged register"); | |
1964 | goto error; | |
1965 | } | |
96074adc JM |
1966 | |
1967 | if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
1968 | { | |
1969 | error_message = _(": unrecognizable privileged register"); | |
1970 | goto error; | |
1971 | } | |
1972 | ||
252b5132 RH |
1973 | s += len; |
1974 | continue; | |
1975 | } | |
1976 | else | |
1977 | { | |
1978 | error_message = _(": unrecognizable privileged register"); | |
1979 | goto error; | |
1980 | } | |
1981 | ||
10156f83 DM |
1982 | case '$': |
1983 | case '%': | |
1984 | /* Parse a sparc64 hyperprivileged register. */ | |
1985 | if (*s == '%') | |
1986 | { | |
8b8c7c9f | 1987 | struct priv_reg_entry *p; |
10156f83 DM |
1988 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
1989 | ||
1990 | s += 1; | |
8b8c7c9f JM |
1991 | for (p = hpriv_reg_table; p->name; p++) |
1992 | if (p->name[0] == s[0]) | |
1993 | { | |
1994 | len = strlen (p->name); | |
1995 | if (strncmp (p->name, s, len) == 0) | |
1996 | break; | |
1997 | } | |
1998 | ||
1999 | if (!p->name) | |
10156f83 DM |
2000 | { |
2001 | error_message = _(": unrecognizable hyperprivileged register"); | |
2002 | goto error; | |
2003 | } | |
96074adc JM |
2004 | |
2005 | if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
2006 | { | |
2007 | error_message = _(": unrecognizable hyperprivileged register"); | |
2008 | goto error; | |
2009 | } | |
2010 | ||
2011 | s += len; | |
10156f83 DM |
2012 | continue; |
2013 | } | |
2014 | else | |
2015 | { | |
2016 | error_message = _(": unrecognizable hyperprivileged register"); | |
2017 | goto error; | |
2018 | } | |
2019 | ||
252b5132 RH |
2020 | case '_': |
2021 | case '/': | |
7a10c22f | 2022 | /* Parse a v9a or later ancillary state register. */ |
252b5132 RH |
2023 | if (*s == '%') |
2024 | { | |
8b8c7c9f | 2025 | struct priv_reg_entry *p; |
e0c6ed95 | 2026 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
2027 | |
2028 | s += 1; | |
8b8c7c9f JM |
2029 | for (p = v9a_asr_table; p->name; p++) |
2030 | if (p->name[0] == s[0]) | |
2031 | { | |
2032 | len = strlen (p->name); | |
2033 | if (strncmp (p->name, s, len) == 0) | |
2034 | break; | |
2035 | } | |
2036 | ||
2037 | if (!p->name) | |
252b5132 | 2038 | { |
7a10c22f | 2039 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2040 | goto error; |
2041 | } | |
96074adc JM |
2042 | |
2043 | if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
2044 | { | |
2045 | error_message = _(": unrecognizable ancillary state register"); | |
2046 | goto error; | |
2047 | } | |
2048 | ||
252b5132 RH |
2049 | s += len; |
2050 | continue; | |
2051 | } | |
2052 | else | |
2053 | { | |
7a10c22f | 2054 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2055 | goto error; |
2056 | } | |
2057 | ||
2058 | case 'M': | |
2059 | case 'm': | |
2060 | if (strncmp (s, "%asr", 4) == 0) | |
2061 | { | |
2062 | s += 4; | |
2063 | ||
3882b010 | 2064 | if (ISDIGIT (*s)) |
252b5132 RH |
2065 | { |
2066 | long num = 0; | |
2067 | ||
3882b010 | 2068 | while (ISDIGIT (*s)) |
252b5132 RH |
2069 | { |
2070 | num = num * 10 + *s - '0'; | |
2071 | ++s; | |
2072 | } | |
2073 | ||
f65c3d1b JM |
2074 | /* We used to check here for the asr number to |
2075 | be between 16 and 31 in V9 and later, as | |
2076 | mandated by the section C.1.1 "Register | |
2077 | Names" in the SPARC spec. However, we | |
2078 | decided to remove this restriction as a) it | |
2079 | introduces problems when new V9 asr registers | |
2080 | are introduced, b) the Solaris assembler | |
2081 | doesn't implement this restriction and c) the | |
2082 | restriction will go away in future revisions | |
2083 | of the Oracle SPARC Architecture. */ | |
2084 | ||
2085 | if (num < 0 || 31 < num) | |
2086 | { | |
2087 | error_message = _(": asr number must be between 0 and 31"); | |
2088 | goto error; | |
2089 | } | |
252b5132 RH |
2090 | |
2091 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
2092 | continue; | |
2093 | } | |
2094 | else | |
2095 | { | |
2096 | error_message = _(": expecting %asrN"); | |
2097 | goto error; | |
2098 | } | |
e0c6ed95 | 2099 | } /* if %asr */ |
252b5132 RH |
2100 | break; |
2101 | ||
2102 | case 'I': | |
2103 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
2104 | goto immediate; | |
2105 | ||
2106 | case 'j': | |
2107 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
2108 | goto immediate; | |
2109 | ||
6cda1326 DM |
2110 | case ')': |
2111 | if (*s == ' ') | |
2112 | s++; | |
2113 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) | |
2114 | || ISDIGIT (*s)) | |
2115 | { | |
2116 | long num = 0; | |
2117 | ||
2118 | if (s[0] == '0' && s[1] == 'x') | |
2119 | { | |
2120 | s += 2; | |
2121 | while (ISXDIGIT (*s)) | |
2122 | { | |
2123 | num <<= 4; | |
2124 | num |= hex_value (*s); | |
2125 | ++s; | |
2126 | } | |
2127 | } | |
2128 | else | |
2129 | { | |
2130 | while (ISDIGIT (*s)) | |
2131 | { | |
2132 | num = num * 10 + *s - '0'; | |
2133 | ++s; | |
2134 | } | |
2135 | } | |
2136 | if (num < 0 || num > 31) | |
2137 | { | |
2138 | error_message = _(": crypto immediate must be between 0 and 31"); | |
2139 | goto error; | |
2140 | } | |
2141 | ||
2142 | opcode |= RS3 (num); | |
2143 | continue; | |
2144 | } | |
2145 | else | |
2146 | { | |
2147 | error_message = _(": expecting crypto immediate"); | |
2148 | goto error; | |
2149 | } | |
2150 | ||
252b5132 RH |
2151 | case 'X': |
2152 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
2153 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2154 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
2155 | else | |
2156 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2157 | /* These fields are unsigned, but for upward compatibility, | |
2158 | allow negative values as well. */ | |
2159 | goto immediate; | |
2160 | ||
2161 | case 'Y': | |
2162 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
2163 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2164 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
2165 | else | |
2166 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2167 | /* These fields are unsigned, but for upward compatibility, | |
2168 | allow negative values as well. */ | |
2169 | goto immediate; | |
2170 | ||
2171 | case 'k': | |
2172 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
2173 | the_insn.pcrel = 1; | |
2174 | goto immediate; | |
2175 | ||
2615994e DM |
2176 | case '=': |
2177 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; | |
2178 | the_insn.pcrel = 1; | |
2179 | goto immediate; | |
2180 | ||
252b5132 RH |
2181 | case 'G': |
2182 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
2183 | the_insn.pcrel = 1; | |
2184 | goto immediate; | |
2185 | ||
2186 | case 'N': | |
2187 | if (*s == 'p' && s[1] == 'n') | |
2188 | { | |
2189 | s += 2; | |
2190 | continue; | |
2191 | } | |
2192 | break; | |
2193 | ||
2194 | case 'T': | |
2195 | if (*s == 'p' && s[1] == 't') | |
2196 | { | |
2197 | s += 2; | |
2198 | continue; | |
2199 | } | |
2200 | break; | |
2201 | ||
2202 | case 'z': | |
2203 | if (*s == ' ') | |
2204 | { | |
2205 | ++s; | |
2206 | } | |
f9911beb JM |
2207 | if ((strncmp (s, "%icc", 4) == 0) |
2208 | || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2209 | { |
2210 | s += 4; | |
2211 | continue; | |
2212 | } | |
2213 | break; | |
2214 | ||
2215 | case 'Z': | |
2216 | if (*s == ' ') | |
2217 | { | |
2218 | ++s; | |
2219 | } | |
f9911beb JM |
2220 | if ((strncmp (s, "%xcc", 4) == 0) |
2221 | || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2222 | { |
2223 | s += 4; | |
2224 | continue; | |
2225 | } | |
2226 | break; | |
2227 | ||
2228 | case '6': | |
2229 | if (*s == ' ') | |
2230 | { | |
2231 | ++s; | |
2232 | } | |
2233 | if (strncmp (s, "%fcc0", 5) == 0) | |
2234 | { | |
2235 | s += 5; | |
2236 | continue; | |
2237 | } | |
2238 | break; | |
2239 | ||
2240 | case '7': | |
2241 | if (*s == ' ') | |
2242 | { | |
2243 | ++s; | |
2244 | } | |
2245 | if (strncmp (s, "%fcc1", 5) == 0) | |
2246 | { | |
2247 | s += 5; | |
2248 | continue; | |
2249 | } | |
2250 | break; | |
2251 | ||
2252 | case '8': | |
2253 | if (*s == ' ') | |
2254 | { | |
2255 | ++s; | |
2256 | } | |
2257 | if (strncmp (s, "%fcc2", 5) == 0) | |
2258 | { | |
2259 | s += 5; | |
2260 | continue; | |
2261 | } | |
2262 | break; | |
2263 | ||
2264 | case '9': | |
2265 | if (*s == ' ') | |
2266 | { | |
2267 | ++s; | |
2268 | } | |
2269 | if (strncmp (s, "%fcc3", 5) == 0) | |
2270 | { | |
2271 | s += 5; | |
2272 | continue; | |
2273 | } | |
2274 | break; | |
2275 | ||
2276 | case 'P': | |
2277 | if (strncmp (s, "%pc", 3) == 0) | |
2278 | { | |
2279 | s += 3; | |
2280 | continue; | |
2281 | } | |
2282 | break; | |
2283 | ||
2284 | case 'W': | |
2285 | if (strncmp (s, "%tick", 5) == 0) | |
2286 | { | |
2287 | s += 5; | |
2288 | continue; | |
2289 | } | |
2290 | break; | |
2291 | ||
e0c6ed95 | 2292 | case '\0': /* End of args. */ |
b9734f35 | 2293 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 2294 | { |
b9734f35 JJ |
2295 | char *s1; |
2296 | int npar = 0; | |
8b8c7c9f | 2297 | const struct perc_entry *p; |
b9734f35 | 2298 | |
8b8c7c9f JM |
2299 | for (p = perc_table; p->type != perc_entry_none; p++) |
2300 | if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) | |
2301 | && strncmp (s + 2, p->name, p->len) == 0) | |
2302 | break; | |
2303 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2304 | break; | |
b9734f35 | 2305 | |
8b8c7c9f | 2306 | if (s[p->len + 2] != '(') |
b9734f35 | 2307 | { |
8b8c7c9f | 2308 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2309 | return special_case; |
2310 | } | |
2311 | ||
8b8c7c9f JM |
2312 | if (! (p->pop->flags & F_POP_TLS_CALL) |
2313 | && the_insn.reloc != BFD_RELOC_NONE) | |
b9734f35 JJ |
2314 | { |
2315 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
8b8c7c9f | 2316 | p->name); |
b9734f35 JJ |
2317 | return special_case; |
2318 | } | |
2319 | ||
8b8c7c9f | 2320 | if ((p->pop->flags & F_POP_TLS_CALL) |
b9734f35 JJ |
2321 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
2322 | || the_insn.exp.X_add_number != 0 | |
2323 | || the_insn.exp.X_add_symbol | |
2324 | != symbol_find_or_make ("__tls_get_addr"))) | |
2325 | { | |
2326 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
8b8c7c9f | 2327 | p->name); |
b9734f35 JJ |
2328 | return special_case; |
2329 | } | |
2330 | ||
8b8c7c9f | 2331 | the_insn.reloc = p->pop->reloc; |
b9734f35 | 2332 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
8b8c7c9f | 2333 | s += p->len + 3; |
b9734f35 JJ |
2334 | |
2335 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2336 | if (*s1 == '(') | |
2337 | npar++; | |
2338 | else if (*s1 == ')') | |
2339 | { | |
2340 | if (!npar) | |
2341 | break; | |
2342 | npar--; | |
2343 | } | |
2344 | ||
2345 | if (*s1 != ')') | |
2346 | { | |
8b8c7c9f | 2347 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2348 | return special_case; |
2349 | } | |
2350 | ||
2351 | *s1 = '\0'; | |
2352 | (void) get_expression (s); | |
2353 | *s1 = ')'; | |
2354 | s = s1 + 1; | |
252b5132 | 2355 | } |
b9734f35 JJ |
2356 | if (*s == '\0') |
2357 | match = 1; | |
252b5132 RH |
2358 | break; |
2359 | ||
2360 | case '+': | |
2361 | if (*s == '+') | |
2362 | { | |
2363 | ++s; | |
2364 | continue; | |
2365 | } | |
2366 | if (*s == '-') | |
2367 | { | |
2368 | continue; | |
2369 | } | |
2370 | break; | |
2371 | ||
e0c6ed95 | 2372 | case '[': /* These must match exactly. */ |
252b5132 RH |
2373 | case ']': |
2374 | case ',': | |
2375 | case ' ': | |
2376 | if (*s++ == *args) | |
2377 | continue; | |
2378 | break; | |
2379 | ||
e0c6ed95 | 2380 | case '#': /* Must be at least one digit. */ |
3882b010 | 2381 | if (ISDIGIT (*s++)) |
252b5132 | 2382 | { |
3882b010 | 2383 | while (ISDIGIT (*s)) |
252b5132 RH |
2384 | { |
2385 | ++s; | |
2386 | } | |
2387 | continue; | |
2388 | } | |
2389 | break; | |
2390 | ||
e0c6ed95 | 2391 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2392 | if (strncmp (s, "%csr", 4) == 0) |
2393 | { | |
2394 | s += 4; | |
2395 | continue; | |
2396 | } | |
2397 | break; | |
2398 | ||
e0c6ed95 | 2399 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2400 | case 'c': |
2401 | case 'D': | |
3882b010 | 2402 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2403 | { |
2404 | mask = *s++; | |
3882b010 | 2405 | if (ISDIGIT (*s)) |
252b5132 RH |
2406 | { |
2407 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2408 | if (mask >= 32) | |
2409 | { | |
2410 | break; | |
2411 | } | |
2412 | } | |
2413 | else | |
2414 | { | |
2415 | mask -= '0'; | |
2416 | } | |
2417 | switch (*args) | |
2418 | { | |
2419 | ||
2420 | case 'b': | |
2421 | opcode |= mask << 14; | |
2422 | continue; | |
2423 | ||
2424 | case 'c': | |
2425 | opcode |= mask; | |
2426 | continue; | |
2427 | ||
2428 | case 'D': | |
2429 | opcode |= mask << 25; | |
2430 | continue; | |
2431 | } | |
2432 | } | |
2433 | break; | |
2434 | ||
2435 | case 'r': /* next operand must be a register */ | |
2436 | case 'O': | |
2437 | case '1': | |
2438 | case '2': | |
2439 | case 'd': | |
2440 | if (*s++ == '%') | |
2441 | { | |
2442 | switch (c = *s++) | |
2443 | { | |
2444 | ||
2445 | case 'f': /* frame pointer */ | |
2446 | if (*s++ == 'p') | |
2447 | { | |
2448 | mask = 0x1e; | |
2449 | break; | |
2450 | } | |
2451 | goto error; | |
2452 | ||
2453 | case 'g': /* global register */ | |
a22b281c RH |
2454 | c = *s++; |
2455 | if (isoctal (c)) | |
252b5132 RH |
2456 | { |
2457 | mask = c - '0'; | |
2458 | break; | |
2459 | } | |
2460 | goto error; | |
2461 | ||
2462 | case 'i': /* in register */ | |
a22b281c RH |
2463 | c = *s++; |
2464 | if (isoctal (c)) | |
252b5132 RH |
2465 | { |
2466 | mask = c - '0' + 24; | |
2467 | break; | |
2468 | } | |
2469 | goto error; | |
2470 | ||
2471 | case 'l': /* local register */ | |
a22b281c RH |
2472 | c = *s++; |
2473 | if (isoctal (c)) | |
252b5132 RH |
2474 | { |
2475 | mask = (c - '0' + 16); | |
2476 | break; | |
2477 | } | |
2478 | goto error; | |
2479 | ||
2480 | case 'o': /* out register */ | |
a22b281c RH |
2481 | c = *s++; |
2482 | if (isoctal (c)) | |
252b5132 RH |
2483 | { |
2484 | mask = (c - '0' + 8); | |
2485 | break; | |
2486 | } | |
2487 | goto error; | |
2488 | ||
2489 | case 's': /* stack pointer */ | |
2490 | if (*s++ == 'p') | |
2491 | { | |
2492 | mask = 0xe; | |
2493 | break; | |
2494 | } | |
2495 | goto error; | |
2496 | ||
2497 | case 'r': /* any register */ | |
3882b010 | 2498 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2499 | { |
2500 | goto error; | |
2501 | } | |
2502 | /* FALLTHROUGH */ | |
2503 | case '0': | |
2504 | case '1': | |
2505 | case '2': | |
2506 | case '3': | |
2507 | case '4': | |
2508 | case '5': | |
2509 | case '6': | |
2510 | case '7': | |
2511 | case '8': | |
2512 | case '9': | |
3882b010 | 2513 | if (ISDIGIT (*s)) |
252b5132 RH |
2514 | { |
2515 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2516 | { | |
2517 | goto error; | |
2518 | } | |
2519 | } | |
2520 | else | |
2521 | { | |
2522 | c -= '0'; | |
2523 | } | |
2524 | mask = c; | |
2525 | break; | |
2526 | ||
2527 | default: | |
2528 | goto error; | |
2529 | } | |
2530 | ||
6d8809aa | 2531 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2532 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2533 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2534 | |
252b5132 RH |
2535 | /* Got the register, now figure out where |
2536 | it goes in the opcode. */ | |
2537 | switch (*args) | |
2538 | { | |
2539 | case '1': | |
2540 | opcode |= mask << 14; | |
2541 | continue; | |
2542 | ||
2543 | case '2': | |
2544 | opcode |= mask; | |
2545 | continue; | |
2546 | ||
2547 | case 'd': | |
2548 | opcode |= mask << 25; | |
2549 | continue; | |
2550 | ||
2551 | case 'r': | |
2552 | opcode |= (mask << 25) | (mask << 14); | |
2553 | continue; | |
2554 | ||
2555 | case 'O': | |
2556 | opcode |= (mask << 25) | (mask << 0); | |
2557 | continue; | |
2558 | } | |
2559 | } | |
2560 | break; | |
2561 | ||
2562 | case 'e': /* next operand is a floating point register */ | |
2563 | case 'v': | |
2564 | case 'V': | |
64517994 | 2565 | case ';': |
252b5132 RH |
2566 | |
2567 | case 'f': | |
2568 | case 'B': | |
2569 | case 'R': | |
64517994 JM |
2570 | case ':': |
2571 | case '\'': | |
252b5132 | 2572 | |
ea783ef3 DM |
2573 | case '4': |
2574 | case '5': | |
2575 | ||
252b5132 RH |
2576 | case 'g': |
2577 | case 'H': | |
2578 | case 'J': | |
3d68f91c | 2579 | case '}': |
64517994 | 2580 | case '^': |
252b5132 RH |
2581 | { |
2582 | char format; | |
2583 | ||
2584 | if (*s++ == '%' | |
ec892a07 JM |
2585 | && ((format = *s) == 'f' |
2586 | || format == 'd' | |
2587 | || format == 'q') | |
3882b010 | 2588 | && ISDIGIT (*++s)) |
252b5132 | 2589 | { |
3882b010 | 2590 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2591 | { |
2592 | mask = 10 * mask + (*s - '0'); | |
2593 | } /* read the number */ | |
2594 | ||
2595 | if ((*args == 'v' | |
2596 | || *args == 'B' | |
ea783ef3 | 2597 | || *args == '5' |
ec892a07 | 2598 | || *args == 'H' |
64517994 | 2599 | || *args == '\'' |
ec892a07 | 2600 | || format == 'd') |
252b5132 RH |
2601 | && (mask & 1)) |
2602 | { | |
ec892a07 | 2603 | /* register must be even numbered */ |
252b5132 | 2604 | break; |
ec892a07 | 2605 | } |
252b5132 RH |
2606 | |
2607 | if ((*args == 'V' | |
2608 | || *args == 'R' | |
ec892a07 JM |
2609 | || *args == 'J' |
2610 | || format == 'q') | |
252b5132 RH |
2611 | && (mask & 3)) |
2612 | { | |
ec892a07 | 2613 | /* register must be multiple of 4 */ |
252b5132 | 2614 | break; |
ec892a07 | 2615 | } |
252b5132 | 2616 | |
64517994 JM |
2617 | if ((*args == ':' |
2618 | || *args == ';' | |
2619 | || *args == '^') | |
2620 | && (mask & 7)) | |
2621 | { | |
2622 | /* register must be multiple of 8 */ | |
2623 | break; | |
2624 | } | |
2625 | ||
2626 | if (*args == '\'' && mask < 48) | |
2627 | { | |
2628 | /* register must be higher or equal than %f48 */ | |
2629 | break; | |
2630 | } | |
2631 | ||
252b5132 RH |
2632 | if (mask >= 64) |
2633 | { | |
2634 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2635 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2636 | else | |
2637 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2638 | goto error; | |
2639 | } /* on error */ | |
2640 | else if (mask >= 32) | |
2641 | { | |
2642 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2643 | { | |
26664553 JJ |
2644 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2645 | { | |
2646 | error_message | |
2647 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2648 | goto error; | |
2649 | } | |
252b5132 RH |
2650 | v9_arg_p = 1; |
2651 | mask -= 31; /* wrap high bit */ | |
2652 | } | |
2653 | else | |
2654 | { | |
2655 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2656 | goto error; | |
2657 | } | |
2658 | } | |
2659 | } | |
2660 | else | |
2661 | { | |
2662 | break; | |
ab3e48dc | 2663 | } /* if not an 'f' register. */ |
252b5132 | 2664 | |
3d68f91c JM |
2665 | if (*args == '}' && mask != RS2 (opcode)) |
2666 | { | |
2667 | error_message | |
2668 | = _(": Instruction requires frs2 and frsd must be the same register"); | |
2669 | goto error; | |
2670 | } | |
2671 | ||
252b5132 RH |
2672 | switch (*args) |
2673 | { | |
2674 | case 'v': | |
2675 | case 'V': | |
2676 | case 'e': | |
64517994 | 2677 | case ';': |
252b5132 RH |
2678 | opcode |= RS1 (mask); |
2679 | continue; | |
2680 | ||
252b5132 RH |
2681 | case 'f': |
2682 | case 'B': | |
2683 | case 'R': | |
64517994 | 2684 | case ':': |
252b5132 RH |
2685 | opcode |= RS2 (mask); |
2686 | continue; | |
2687 | ||
64517994 JM |
2688 | case '\'': |
2689 | opcode |= RS2 (mask & 0xe); | |
2690 | continue; | |
2691 | ||
ea783ef3 DM |
2692 | case '4': |
2693 | case '5': | |
2694 | opcode |= RS3 (mask); | |
2695 | continue; | |
2696 | ||
252b5132 RH |
2697 | case 'g': |
2698 | case 'H': | |
2699 | case 'J': | |
3d68f91c | 2700 | case '}': |
64517994 | 2701 | case '^': |
252b5132 RH |
2702 | opcode |= RD (mask); |
2703 | continue; | |
ab3e48dc | 2704 | } /* Pack it in. */ |
252b5132 RH |
2705 | |
2706 | know (0); | |
2707 | break; | |
ab3e48dc | 2708 | } /* float arg */ |
252b5132 RH |
2709 | |
2710 | case 'F': | |
2711 | if (strncmp (s, "%fsr", 4) == 0) | |
2712 | { | |
2713 | s += 4; | |
2714 | continue; | |
2715 | } | |
2716 | break; | |
2717 | ||
ea783ef3 DM |
2718 | case '(': |
2719 | if (strncmp (s, "%efsr", 5) == 0) | |
2720 | { | |
2721 | s += 5; | |
2722 | continue; | |
2723 | } | |
2724 | break; | |
2725 | ||
ab3e48dc KH |
2726 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2727 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2728 | goto immediate; |
2729 | ||
ab3e48dc | 2730 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2731 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2732 | the_insn.pcrel = 1; | |
2733 | goto immediate; | |
2734 | ||
ab3e48dc | 2735 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2736 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2737 | the_insn.pcrel = 1; | |
2738 | goto immediate; | |
2739 | ||
63fab58c | 2740 | case 'h': |
ab3e48dc | 2741 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2742 | the_insn.reloc = BFD_RELOC_SPARC22; |
2743 | goto immediate; | |
2744 | ||
ab3e48dc | 2745 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2746 | the_insn.reloc = BFD_RELOC_SPARC13; |
2747 | ||
2748 | /* fallthrough */ | |
2749 | ||
2750 | immediate: | |
2751 | if (*s == ' ') | |
2752 | s++; | |
2753 | ||
cf9a1301 RH |
2754 | { |
2755 | char *s1; | |
e0471c16 | 2756 | const char *op_arg = NULL; |
30eb9c17 | 2757 | static expressionS op_exp; |
cf9a1301 RH |
2758 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2759 | ||
2760 | /* Check for %hi, etc. */ | |
2761 | if (*s == '%') | |
2762 | { | |
8b8c7c9f JM |
2763 | const struct perc_entry *p; |
2764 | ||
2765 | for (p = perc_table; p->type != perc_entry_none; p++) | |
2766 | if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) | |
2767 | && strncmp (s + 1, p->name, p->len) == 0) | |
2768 | break; | |
2769 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2770 | break; | |
2771 | ||
2772 | if (s[p->len + 1] != '(') | |
cf9a1301 | 2773 | { |
8b8c7c9f | 2774 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
a22b281c | 2775 | return special_case; |
cf9a1301 | 2776 | } |
252b5132 | 2777 | |
8b8c7c9f JM |
2778 | op_arg = p->name; |
2779 | the_insn.reloc = p->pop->reloc; | |
2780 | s += p->len + 2; | |
2781 | v9_arg_p = p->pop->flags & F_POP_V9; | |
cf9a1301 RH |
2782 | } |
2783 | ||
2784 | /* Note that if the get_expression() fails, we will still | |
2785 | have created U entries in the symbol table for the | |
2786 | 'symbols' in the input string. Try not to create U | |
2787 | symbols for registers, etc. */ | |
252b5132 | 2788 | |
252b5132 RH |
2789 | /* This stuff checks to see if the expression ends in |
2790 | +%reg. If it does, it removes the register from | |
2791 | the expression, and re-sets 's' to point to the | |
2792 | right place. */ | |
2793 | ||
cf9a1301 RH |
2794 | if (op_arg) |
2795 | { | |
2796 | int npar = 0; | |
2797 | ||
2798 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2799 | if (*s1 == '(') | |
2800 | npar++; | |
2801 | else if (*s1 == ')') | |
2802 | { | |
2803 | if (!npar) | |
2804 | break; | |
2805 | npar--; | |
2806 | } | |
2807 | ||
2808 | if (*s1 != ')') | |
2809 | { | |
2810 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2811 | return special_case; |
cf9a1301 | 2812 | } |
e0c6ed95 | 2813 | |
cf9a1301 RH |
2814 | *s1 = '\0'; |
2815 | (void) get_expression (s); | |
2816 | *s1 = ')'; | |
e140100a NC |
2817 | if (expr_end != s1) |
2818 | { | |
2819 | as_bad (_("Expression inside %%%s could not be parsed"), op_arg); | |
2820 | return special_case; | |
2821 | } | |
cf9a1301 RH |
2822 | s = s1 + 1; |
2823 | if (*s == ',' || *s == ']' || !*s) | |
2824 | continue; | |
2825 | if (*s != '+' && *s != '-') | |
2826 | { | |
2827 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2828 | return special_case; |
cf9a1301 RH |
2829 | } |
2830 | *s1 = '0'; | |
2831 | s = s1; | |
2832 | op_exp = the_insn.exp; | |
e0c6ed95 | 2833 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2834 | } |
252b5132 | 2835 | |
e0c6ed95 AM |
2836 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2837 | ; | |
252b5132 | 2838 | |
3882b010 | 2839 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2840 | { |
2841 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2842 | s1 -= 3; |
f124dd4f | 2843 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2844 | s1 -= 4; |
f124dd4f DM |
2845 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2846 | s1 -= 5; | |
cf9a1301 RH |
2847 | else |
2848 | s1 = NULL; | |
2849 | if (s1) | |
252b5132 | 2850 | { |
252b5132 | 2851 | *s1 = '\0'; |
1eb7027c RH |
2852 | if (op_arg && s1 == s + 1) |
2853 | the_insn.exp.X_op = O_absent; | |
2854 | else | |
2855 | (void) get_expression (s); | |
252b5132 | 2856 | *s1 = '+'; |
cf9a1301 RH |
2857 | if (op_arg) |
2858 | *s = ')'; | |
252b5132 | 2859 | s = s1; |
252b5132 | 2860 | } |
cf9a1301 RH |
2861 | } |
2862 | else | |
2863 | s1 = NULL; | |
2864 | ||
2865 | if (!s1) | |
2866 | { | |
2867 | (void) get_expression (s); | |
2868 | if (op_arg) | |
2869 | *s = ')'; | |
2870 | s = expr_end; | |
2871 | } | |
2872 | ||
2873 | if (op_arg) | |
2874 | { | |
2875 | the_insn.exp2 = the_insn.exp; | |
2876 | the_insn.exp = op_exp; | |
2877 | if (the_insn.exp2.X_op == O_absent) | |
2878 | the_insn.exp2.X_op = O_illegal; | |
2879 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2880 | { |
cf9a1301 RH |
2881 | the_insn.exp = the_insn.exp2; |
2882 | the_insn.exp2.X_op = O_illegal; | |
2883 | } | |
2884 | else if (the_insn.exp.X_op == O_constant) | |
2885 | { | |
2886 | valueT val = the_insn.exp.X_add_number; | |
2887 | switch (the_insn.reloc) | |
2888 | { | |
1b50c718 ILT |
2889 | default: |
2890 | break; | |
2891 | ||
cf9a1301 RH |
2892 | case BFD_RELOC_SPARC_HH22: |
2893 | val = BSR (val, 32); | |
e0c6ed95 | 2894 | /* Fall through. */ |
cf9a1301 RH |
2895 | |
2896 | case BFD_RELOC_SPARC_LM22: | |
2897 | case BFD_RELOC_HI22: | |
2898 | val = (val >> 10) & 0x3fffff; | |
2899 | break; | |
2900 | ||
2901 | case BFD_RELOC_SPARC_HM10: | |
2902 | val = BSR (val, 32); | |
e0c6ed95 | 2903 | /* Fall through. */ |
cf9a1301 RH |
2904 | |
2905 | case BFD_RELOC_LO10: | |
2906 | val &= 0x3ff; | |
2907 | break; | |
2908 | ||
2615994e DM |
2909 | case BFD_RELOC_SPARC_H34: |
2910 | val >>= 12; | |
2911 | val &= 0x3fffff; | |
2912 | break; | |
2913 | ||
cf9a1301 RH |
2914 | case BFD_RELOC_SPARC_H44: |
2915 | val >>= 22; | |
2916 | val &= 0x3fffff; | |
2917 | break; | |
2918 | ||
2919 | case BFD_RELOC_SPARC_M44: | |
2920 | val >>= 12; | |
2921 | val &= 0x3ff; | |
2922 | break; | |
2923 | ||
2924 | case BFD_RELOC_SPARC_L44: | |
2925 | val &= 0xfff; | |
2926 | break; | |
2927 | ||
2928 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2929 | val = ~val; |
cf9a1301 RH |
2930 | val = (val >> 10) & 0x3fffff; |
2931 | break; | |
2932 | ||
2933 | case BFD_RELOC_SPARC_LOX10: | |
2934 | val = (val & 0x3ff) | 0x1c00; | |
2935 | break; | |
2936 | } | |
2937 | the_insn.exp = the_insn.exp2; | |
2938 | the_insn.exp.X_add_number += val; | |
2939 | the_insn.exp2.X_op = O_illegal; | |
2940 | the_insn.reloc = old_reloc; | |
2941 | } | |
2942 | else if (the_insn.exp2.X_op != O_constant) | |
2943 | { | |
2944 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2945 | return special_case; |
cf9a1301 RH |
2946 | } |
2947 | else | |
2948 | { | |
dabe3bbc | 2949 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2950 | || the_insn.reloc != BFD_RELOC_LO10 |
2951 | || sparc_arch_size != 64 | |
2952 | || sparc_pic_code) | |
2953 | { | |
2954 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2955 | return special_case; |
cf9a1301 RH |
2956 | } |
2957 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2958 | } |
2959 | } | |
2960 | } | |
252b5132 RH |
2961 | /* Check for constants that don't require emitting a reloc. */ |
2962 | if (the_insn.exp.X_op == O_constant | |
2963 | && the_insn.exp.X_add_symbol == 0 | |
2964 | && the_insn.exp.X_op_symbol == 0) | |
2965 | { | |
2966 | /* For pc-relative call instructions, we reject | |
2967 | constants to get better code. */ | |
2968 | if (the_insn.pcrel | |
2969 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2970 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2971 | { | |
2972 | error_message = _(": PC-relative operand can't be a constant"); | |
2973 | goto error; | |
2974 | } | |
2975 | ||
b9734f35 JJ |
2976 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2977 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2978 | { | |
2979 | error_message = _(": TLS operand can't be a constant"); | |
2980 | goto error; | |
2981 | } | |
2982 | ||
55cf6793 | 2983 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2984 | and bfd_install_relocation. |
2985 | ??? It would be preferable to install the constants | |
2986 | into the insn here and save having to create a fixS | |
2987 | for each one. There already exists code to handle | |
55cf6793 | 2988 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2989 | bfd_install_relocation) so duplicating all that code |
2990 | here isn't right. */ | |
698544e1 DM |
2991 | |
2992 | /* This is a special case to handle cbcond instructions | |
2993 | properly, which can need two relocations. The first | |
2994 | one is for the 5-bit immediate field and the latter | |
2995 | is going to be for the WDISP10 branch part. We | |
2996 | handle the R_SPARC_5 immediate directly here so that | |
2997 | we don't need to add support for multiple relocations | |
2998 | in one instruction just yet. */ | |
65d1cff9 JM |
2999 | if (the_insn.reloc == BFD_RELOC_SPARC_5 |
3000 | && ((insn->match & OP(0x3)) == 0)) | |
698544e1 DM |
3001 | { |
3002 | valueT val = the_insn.exp.X_add_number; | |
3003 | ||
65d1cff9 | 3004 | the_insn.reloc = BFD_RELOC_NONE; |
698544e1 DM |
3005 | if (! in_bitfield_range (val, 0x1f)) |
3006 | { | |
3007 | error_message = _(": Immediate value in cbcond is out of range."); | |
3008 | goto error; | |
3009 | } | |
3010 | opcode |= val & 0x1f; | |
698544e1 | 3011 | } |
252b5132 RH |
3012 | } |
3013 | ||
3014 | continue; | |
3015 | ||
3016 | case 'a': | |
3017 | if (*s++ == 'a') | |
3018 | { | |
3019 | opcode |= ANNUL; | |
3020 | continue; | |
3021 | } | |
3022 | break; | |
3023 | ||
3024 | case 'A': | |
3025 | { | |
3026 | int asi = 0; | |
3027 | ||
3028 | /* Parse an asi. */ | |
3029 | if (*s == '#') | |
3030 | { | |
1e9d41d4 | 3031 | if (! parse_sparc_asi (&s, &sasi)) |
252b5132 RH |
3032 | { |
3033 | error_message = _(": invalid ASI name"); | |
3034 | goto error; | |
3035 | } | |
1e9d41d4 | 3036 | asi = sasi->value; |
252b5132 RH |
3037 | } |
3038 | else | |
3039 | { | |
3040 | if (! parse_const_expr_arg (&s, &asi)) | |
3041 | { | |
3042 | error_message = _(": invalid ASI expression"); | |
3043 | goto error; | |
3044 | } | |
3045 | if (asi < 0 || asi > 255) | |
3046 | { | |
3047 | error_message = _(": invalid ASI number"); | |
3048 | goto error; | |
3049 | } | |
3050 | } | |
3051 | opcode |= ASI (asi); | |
3052 | continue; | |
e0c6ed95 | 3053 | } /* Alternate space. */ |
252b5132 RH |
3054 | |
3055 | case 'p': | |
3056 | if (strncmp (s, "%psr", 4) == 0) | |
3057 | { | |
3058 | s += 4; | |
3059 | continue; | |
3060 | } | |
3061 | break; | |
3062 | ||
e0c6ed95 | 3063 | case 'q': /* Floating point queue. */ |
252b5132 RH |
3064 | if (strncmp (s, "%fq", 3) == 0) |
3065 | { | |
3066 | s += 3; | |
3067 | continue; | |
3068 | } | |
3069 | break; | |
3070 | ||
e0c6ed95 | 3071 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
3072 | if (strncmp (s, "%cq", 3) == 0) |
3073 | { | |
3074 | s += 3; | |
3075 | continue; | |
3076 | } | |
3077 | break; | |
3078 | ||
3079 | case 'S': | |
3080 | if (strcmp (str, "set") == 0 | |
3081 | || strcmp (str, "setuw") == 0) | |
3082 | { | |
3083 | special_case = SPECIAL_CASE_SET; | |
3084 | continue; | |
3085 | } | |
3086 | else if (strcmp (str, "setsw") == 0) | |
3087 | { | |
3088 | special_case = SPECIAL_CASE_SETSW; | |
3089 | continue; | |
3090 | } | |
3091 | else if (strcmp (str, "setx") == 0) | |
3092 | { | |
3093 | special_case = SPECIAL_CASE_SETX; | |
3094 | continue; | |
3095 | } | |
3096 | else if (strncmp (str, "fdiv", 4) == 0) | |
3097 | { | |
3098 | special_case = SPECIAL_CASE_FDIV; | |
3099 | continue; | |
3100 | } | |
3101 | break; | |
3102 | ||
3103 | case 'o': | |
3104 | if (strncmp (s, "%asi", 4) != 0) | |
3105 | break; | |
3106 | s += 4; | |
3107 | continue; | |
3108 | ||
3109 | case 's': | |
3110 | if (strncmp (s, "%fprs", 5) != 0) | |
3111 | break; | |
3112 | s += 5; | |
3113 | continue; | |
3114 | ||
3d68f91c JM |
3115 | case '{': |
3116 | if (strncmp (s, "%mcdper",7) != 0) | |
3117 | break; | |
3118 | s += 7; | |
3119 | continue; | |
3120 | ||
64517994 JM |
3121 | case '&': |
3122 | if (strncmp (s, "%entropy", 8) != 0) | |
3123 | break; | |
3124 | s += 8; | |
3125 | continue; | |
3126 | ||
252b5132 RH |
3127 | case 'E': |
3128 | if (strncmp (s, "%ccr", 4) != 0) | |
3129 | break; | |
3130 | s += 4; | |
3131 | continue; | |
3132 | ||
3133 | case 't': | |
3134 | if (strncmp (s, "%tbr", 4) != 0) | |
3135 | break; | |
3136 | s += 4; | |
3137 | continue; | |
3138 | ||
3139 | case 'w': | |
3140 | if (strncmp (s, "%wim", 4) != 0) | |
3141 | break; | |
3142 | s += 4; | |
3143 | continue; | |
3144 | ||
64517994 JM |
3145 | case '|': |
3146 | { | |
3147 | int imm2 = 0; | |
3148 | ||
3149 | /* Parse a 2-bit immediate. */ | |
3150 | if (! parse_const_expr_arg (&s, &imm2)) | |
3151 | { | |
3152 | error_message = _(": non-immdiate imm2 operand"); | |
3153 | goto error; | |
3154 | } | |
3155 | if ((imm2 & ~0x3) != 0) | |
3156 | { | |
3157 | error_message = _(": imm2 immediate operand out of range (0-3)"); | |
3158 | goto error; | |
3159 | } | |
3160 | ||
3161 | opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1); | |
3162 | continue; | |
3163 | } | |
3164 | ||
252b5132 RH |
3165 | case 'x': |
3166 | { | |
3167 | char *push = input_line_pointer; | |
3168 | expressionS e; | |
3169 | ||
3170 | input_line_pointer = s; | |
3171 | expression (&e); | |
3172 | if (e.X_op == O_constant) | |
3173 | { | |
3174 | int n = e.X_add_number; | |
3175 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
3176 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
3177 | else | |
3178 | opcode |= e.X_add_number << 5; | |
3179 | } | |
3180 | else | |
3181 | as_bad (_("non-immediate OPF operand, ignored")); | |
3182 | s = input_line_pointer; | |
3183 | input_line_pointer = push; | |
3184 | continue; | |
3185 | } | |
3186 | ||
3187 | case 'y': | |
3188 | if (strncmp (s, "%y", 2) != 0) | |
3189 | break; | |
3190 | s += 2; | |
3191 | continue; | |
3192 | ||
3193 | case 'u': | |
3194 | case 'U': | |
3195 | { | |
3196 | /* Parse a sparclet cpreg. */ | |
3197 | int cpreg; | |
3198 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
3199 | { | |
3200 | error_message = _(": invalid cpreg name"); | |
3201 | goto error; | |
3202 | } | |
3203 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
3204 | continue; | |
3205 | } | |
3206 | ||
3207 | default: | |
3208 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 3209 | } /* switch on arg code. */ |
252b5132 RH |
3210 | |
3211 | /* Break out of for() loop. */ | |
3212 | break; | |
e0c6ed95 | 3213 | } /* For each arg that we expect. */ |
252b5132 RH |
3214 | |
3215 | error: | |
3216 | if (match == 0) | |
3217 | { | |
e0c6ed95 | 3218 | /* Args don't match. */ |
252b5132 RH |
3219 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
3220 | && (insn->name == insn[1].name | |
3221 | || !strcmp (insn->name, insn[1].name))) | |
3222 | { | |
3223 | ++insn; | |
3224 | s = argsStart; | |
3225 | continue; | |
3226 | } | |
3227 | else | |
3228 | { | |
3229 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 3230 | return special_case; |
252b5132 RH |
3231 | } |
3232 | } | |
3233 | else | |
3234 | { | |
e0c6ed95 | 3235 | /* We have a match. Now see if the architecture is OK. */ |
1e9d41d4 SL |
3236 | /* String to use in case of architecture warning. */ |
3237 | const char *msg_str = str; | |
252b5132 | 3238 | int needed_arch_mask = insn->architecture; |
1e9d41d4 SL |
3239 | |
3240 | /* Include the ASI architecture needed as well */ | |
3241 | if (sasi && needed_arch_mask > sasi->architecture) | |
3242 | { | |
3243 | needed_arch_mask = sasi->architecture; | |
3244 | msg_str = sasi->name; | |
3245 | } | |
3246 | ||
3247 | bfd_uint64_t hwcaps | |
3d68f91c | 3248 | = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; |
252b5132 | 3249 | |
4bafe00e | 3250 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
9e8c70f9 DM |
3251 | if (hwcaps) |
3252 | hwcap_seen |= hwcaps; | |
3253 | #endif | |
252b5132 RH |
3254 | if (v9_arg_p) |
3255 | { | |
19f7b010 JJ |
3256 | needed_arch_mask &= |
3257 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
3258 | if (! needed_arch_mask) | |
3259 | needed_arch_mask = | |
3260 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
3261 | } |
3262 | ||
e0c6ed95 AM |
3263 | if (needed_arch_mask |
3264 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
3265 | /* OK. */ | |
3266 | ; | |
252b5132 | 3267 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
3268 | else if (needed_arch_mask |
3269 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
3270 | { |
3271 | enum sparc_opcode_arch_val needed_architecture = | |
3272 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
3273 | & needed_arch_mask); | |
3274 | ||
9c2799c2 | 3275 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
3276 | if (warn_on_bump |
3277 | && needed_architecture > warn_after_architecture) | |
3278 | { | |
3279 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
3280 | sparc_opcode_archs[current_architecture].name, | |
3281 | sparc_opcode_archs[needed_architecture].name, | |
1e9d41d4 | 3282 | msg_str); |
252b5132 RH |
3283 | warn_after_architecture = needed_architecture; |
3284 | } | |
3285 | current_architecture = needed_architecture; | |
6884417a JM |
3286 | hwcap_allowed |
3287 | = (hwcap_allowed | |
3288 | | hwcaps | |
3289 | | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32) | |
3290 | | sparc_opcode_archs[current_architecture].hwcaps); | |
252b5132 RH |
3291 | } |
3292 | /* Conflict. */ | |
3293 | /* ??? This seems to be a bit fragile. What if the next entry in | |
3294 | the opcode table is the one we want and it is supported? | |
3295 | It is possible to arrange the table today so that this can't | |
3296 | happen but what about tomorrow? */ | |
3297 | else | |
3298 | { | |
e0c6ed95 | 3299 | int arch, printed_one_p = 0; |
252b5132 RH |
3300 | char *p; |
3301 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
3302 | ||
3303 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 3304 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
3305 | p = required_archs; |
3306 | arch = sparc_ffs (needed_arch_mask); | |
3307 | while ((1 << arch) <= needed_arch_mask) | |
3308 | { | |
3309 | if ((1 << arch) & needed_arch_mask) | |
3310 | { | |
3311 | if (printed_one_p) | |
3312 | *p++ = '|'; | |
3313 | strcpy (p, sparc_opcode_archs[arch].name); | |
3314 | p += strlen (p); | |
3315 | printed_one_p = 1; | |
3316 | } | |
3317 | ++arch; | |
3318 | } | |
3319 | ||
fc7514d6 | 3320 | as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart); |
33eaf5de | 3321 | as_tsktsk (_("(Requires %s; requested architecture is %s.)"), |
252b5132 RH |
3322 | required_archs, |
3323 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 3324 | return special_case; |
252b5132 | 3325 | } |
4bafe00e | 3326 | |
9aff4b7a | 3327 | /* Make sure the hwcaps used by the instruction are |
4bafe00e DM |
3328 | currently enabled. */ |
3329 | if (hwcaps & ~hwcap_allowed) | |
3330 | { | |
3331 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); | |
3332 | ||
3333 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), | |
3334 | hwcap_name, str); | |
3335 | return special_case; | |
3336 | } | |
e0c6ed95 | 3337 | } /* If no match. */ |
252b5132 RH |
3338 | |
3339 | break; | |
e0c6ed95 | 3340 | } /* Forever looking for a match. */ |
252b5132 RH |
3341 | |
3342 | the_insn.opcode = opcode; | |
a22b281c | 3343 | return special_case; |
252b5132 RH |
3344 | } |
3345 | ||
1e9d41d4 SL |
3346 | static char * |
3347 | skip_over_keyword (char *q) | |
3348 | { | |
3349 | for (q = q + (*q == '#' || *q == '%'); | |
3350 | ISALNUM (*q) || *q == '_'; | |
3351 | ++q) | |
3352 | continue; | |
3353 | return q; | |
3354 | } | |
3355 | ||
3356 | static int | |
3357 | parse_sparc_asi (char **input_pointer_p, const sparc_asi **value_p) | |
3358 | { | |
3359 | const sparc_asi *value; | |
3360 | char c, *p, *q; | |
3361 | ||
3362 | p = *input_pointer_p; | |
3363 | q = skip_over_keyword(p); | |
3364 | c = *q; | |
3365 | *q = 0; | |
3366 | value = sparc_encode_asi (p); | |
3367 | *q = c; | |
3368 | if (value == NULL) | |
3369 | return 0; | |
3370 | *value_p = value; | |
3371 | *input_pointer_p = q; | |
3372 | return 1; | |
3373 | } | |
3374 | ||
252b5132 RH |
3375 | /* Parse an argument that can be expressed as a keyword. |
3376 | (eg: #StoreStore or %ccfr). | |
3377 | The result is a boolean indicating success. | |
3378 | If successful, INPUT_POINTER is updated. */ | |
3379 | ||
3380 | static int | |
5a49b8ac AM |
3381 | parse_keyword_arg (int (*lookup_fn) (const char *), |
3382 | char **input_pointerP, | |
3383 | int *valueP) | |
252b5132 RH |
3384 | { |
3385 | int value; | |
3386 | char c, *p, *q; | |
3387 | ||
3388 | p = *input_pointerP; | |
1e9d41d4 | 3389 | q = skip_over_keyword(p); |
252b5132 RH |
3390 | c = *q; |
3391 | *q = 0; | |
3392 | value = (*lookup_fn) (p); | |
3393 | *q = c; | |
3394 | if (value == -1) | |
3395 | return 0; | |
3396 | *valueP = value; | |
3397 | *input_pointerP = q; | |
3398 | return 1; | |
3399 | } | |
3400 | ||
3401 | /* Parse an argument that is a constant expression. | |
3402 | The result is a boolean indicating success. */ | |
3403 | ||
3404 | static int | |
5a49b8ac | 3405 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
3406 | { |
3407 | char *save = input_line_pointer; | |
3408 | expressionS exp; | |
3409 | ||
3410 | input_line_pointer = *input_pointerP; | |
3411 | /* The next expression may be something other than a constant | |
3412 | (say if we're not processing the right variant of the insn). | |
3413 | Don't call expression unless we're sure it will succeed as it will | |
3414 | signal an error (which we want to defer until later). */ | |
3415 | /* FIXME: It might be better to define md_operand and have it recognize | |
3416 | things like %asi, etc. but continuing that route through to the end | |
3417 | is a lot of work. */ | |
3418 | if (*input_line_pointer == '%') | |
3419 | { | |
3420 | input_line_pointer = save; | |
3421 | return 0; | |
3422 | } | |
3423 | expression (&exp); | |
3424 | *input_pointerP = input_line_pointer; | |
3425 | input_line_pointer = save; | |
3426 | if (exp.X_op != O_constant) | |
3427 | return 0; | |
3428 | *valueP = exp.X_add_number; | |
3429 | return 1; | |
3430 | } | |
3431 | ||
3432 | /* Subroutine of sparc_ip to parse an expression. */ | |
3433 | ||
3434 | static int | |
5a49b8ac | 3435 | get_expression (char *str) |
252b5132 RH |
3436 | { |
3437 | char *save_in; | |
3438 | segT seg; | |
3439 | ||
3440 | save_in = input_line_pointer; | |
3441 | input_line_pointer = str; | |
3442 | seg = expression (&the_insn.exp); | |
3443 | if (seg != absolute_section | |
3444 | && seg != text_section | |
3445 | && seg != data_section | |
3446 | && seg != bss_section | |
3447 | && seg != undefined_section) | |
3448 | { | |
3449 | the_insn.error = _("bad segment"); | |
3450 | expr_end = input_line_pointer; | |
3451 | input_line_pointer = save_in; | |
3452 | return 1; | |
3453 | } | |
3454 | expr_end = input_line_pointer; | |
3455 | input_line_pointer = save_in; | |
3456 | return 0; | |
3457 | } | |
3458 | ||
3459 | /* Subroutine of md_assemble to output one insn. */ | |
3460 | ||
3461 | static void | |
91d6fa6a | 3462 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
3463 | { |
3464 | char *toP = frag_more (4); | |
3465 | ||
e0c6ed95 | 3466 | /* Put out the opcode. */ |
252b5132 | 3467 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 3468 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3469 | else |
91d6fa6a | 3470 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3471 | |
e0c6ed95 | 3472 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 3473 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 3474 | { |
e0c6ed95 AM |
3475 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
3476 | (toP - frag_now->fr_literal), /* Where. */ | |
3477 | 4, /* Size. */ | |
91d6fa6a NC |
3478 | &theinsn->exp, |
3479 | theinsn->pcrel, | |
3480 | theinsn->reloc); | |
252b5132 | 3481 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 3482 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
3483 | the insn size is 4 and fixup_segment will signal an overflow for |
3484 | large 8 byte quantities. */ | |
3485 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
3486 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
3487 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
3488 | } |
3489 | ||
3490 | last_insn = insn; | |
91d6fa6a | 3491 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
3492 | |
3493 | #ifdef OBJ_ELF | |
3494 | dwarf2_emit_insn (4); | |
3495 | #endif | |
252b5132 RH |
3496 | } |
3497 | \f | |
6d4af3c2 | 3498 | const char * |
499ac353 | 3499 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3500 | { |
499ac353 | 3501 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3502 | } |
3503 | ||
3504 | /* Write a value out to the object file, using the appropriate | |
3505 | endianness. */ | |
3506 | ||
3507 | void | |
5a49b8ac | 3508 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3509 | { |
3510 | if (target_big_endian) | |
3511 | number_to_chars_bigendian (buf, val, n); | |
3512 | else if (target_little_endian_data | |
3513 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3514 | /* Output debug words, which are not in allocated sections, as big |
3515 | endian. */ | |
252b5132 RH |
3516 | number_to_chars_bigendian (buf, val, n); |
3517 | else if (target_little_endian_data || ! target_big_endian) | |
3518 | number_to_chars_littleendian (buf, val, n); | |
3519 | } | |
3520 | \f | |
3521 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3522 | hold. */ |
252b5132 | 3523 | |
94f592af | 3524 | void |
5a49b8ac | 3525 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3526 | { |
3527 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3528 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3529 | long insn; |
3530 | ||
9c2799c2 | 3531 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3532 | |
e0c6ed95 | 3533 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3534 | |
3535 | #ifdef OBJ_ELF | |
a161fe53 | 3536 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3537 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3538 | { |
3539 | switch (fixP->fx_r_type) | |
3540 | { | |
3541 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3542 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3543 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3544 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3545 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3546 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3547 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3548 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3549 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3550 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3551 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3552 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3553 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3554 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3555 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3556 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3557 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3558 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3559 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3560 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3561 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3562 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3563 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3564 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3565 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3566 | ||
3567 | default: | |
3568 | break; | |
3569 | } | |
3570 | ||
3571 | return; | |
3572 | } | |
252b5132 RH |
3573 | #endif |
3574 | ||
3575 | /* This is a hack. There should be a better way to | |
3576 | handle this. Probably in terms of howto fields, once | |
3577 | we can look at these fixups in terms of howtos. */ | |
3578 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3579 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3580 | ||
3581 | #ifdef OBJ_AOUT | |
3582 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3583 | generate a reloc, then we just want to let the reloc addend set | |
3584 | the value. We do not want to also stuff the addend into the | |
3585 | object file. Including the addend in the object file works when | |
3586 | doing a static link, because the linker will ignore the object | |
3587 | file contents. However, the dynamic linker does not ignore the | |
3588 | object file contents. */ | |
3589 | if (fixP->fx_addsy != NULL | |
3590 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3591 | val = 0; | |
3592 | ||
3593 | /* When generating PIC code, we do not want an addend for a reloc | |
3594 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3595 | value already included in val, and to also cancel out the | |
3596 | adjustment which bfd_install_relocation will create. */ | |
3597 | if (sparc_pic_code | |
3598 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3599 | && fixP->fx_addsy != NULL | |
3600 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3601 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3602 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3603 | ||
3604 | /* When generating PIC code, we need to fiddle to get | |
3605 | bfd_install_relocation to do the right thing for a PC relative | |
3606 | reloc against a local symbol which we are going to keep. */ | |
3607 | if (sparc_pic_code | |
3608 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3609 | && fixP->fx_addsy != NULL | |
3610 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3611 | || S_IS_WEAK (fixP->fx_addsy)) | |
3612 | && S_IS_DEFINED (fixP->fx_addsy) | |
3613 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3614 | { | |
3615 | val = 0; | |
3616 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3617 | } | |
3618 | #endif | |
3619 | ||
3620 | /* If this is a data relocation, just output VAL. */ | |
3621 | ||
a7bbf4e9 DM |
3622 | if (fixP->fx_r_type == BFD_RELOC_8) |
3623 | { | |
3624 | md_number_to_chars (buf, val, 1); | |
3625 | } | |
3626 | else if (fixP->fx_r_type == BFD_RELOC_16 | |
3627 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3628 | { |
3629 | md_number_to_chars (buf, val, 2); | |
3630 | } | |
3631 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3632 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3633 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3634 | { | |
3635 | md_number_to_chars (buf, val, 4); | |
3636 | } | |
0f2712ed NC |
3637 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3638 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3639 | { |
3640 | md_number_to_chars (buf, val, 8); | |
3641 | } | |
e0c6ed95 | 3642 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3643 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3644 | { | |
3645 | fixP->fx_done = 0; | |
94f592af | 3646 | return; |
252b5132 RH |
3647 | } |
3648 | else | |
3649 | { | |
3650 | /* It's a relocation against an instruction. */ | |
3651 | ||
3652 | if (INSN_BIG_ENDIAN) | |
3653 | insn = bfd_getb32 ((unsigned char *) buf); | |
3654 | else | |
3655 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3656 | |
252b5132 RH |
3657 | switch (fixP->fx_r_type) |
3658 | { | |
3659 | case BFD_RELOC_32_PCREL_S2: | |
3660 | val = val >> 2; | |
3661 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3662 | being done! */ | |
3663 | if (! sparc_pic_code | |
3664 | || fixP->fx_addsy == NULL | |
49309057 | 3665 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3666 | ++val; |
6faf3d66 | 3667 | |
252b5132 | 3668 | insn |= val & 0x3fffffff; |
6faf3d66 | 3669 | |
d28b6364 JM |
3670 | /* See if we have a delay slot. In that case we attempt to |
3671 | optimize several cases transforming CALL instructions | |
3672 | into branches. But we can only do that if the relocation | |
3673 | can be completely resolved here, i.e. if no undefined | |
3674 | symbol is associated with it. */ | |
3675 | if (sparc_relax && fixP->fx_addsy == NULL | |
3676 | && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) | |
6faf3d66 JJ |
3677 | { |
3678 | #define G0 0 | |
3679 | #define O7 15 | |
3680 | #define XCC (2 << 20) | |
3681 | #define COND(x) (((x)&0xf)<<25) | |
3682 | #define CONDA COND(0x8) | |
3683 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3684 | #define INSN_BA (F2(0,2) | CONDA) | |
3685 | #define INSN_OR F3(2, 0x2, 0) | |
3686 | #define INSN_NOP F2(0,4) | |
3687 | ||
3688 | long delay; | |
3689 | ||
3690 | /* If the instruction is a call with either: | |
3691 | restore | |
3692 | arithmetic instruction with rd == %o7 | |
3693 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3694 | then we can optimize if the call destination is near | |
3695 | by changing the call into a branch always. */ | |
3696 | if (INSN_BIG_ENDIAN) | |
3697 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3698 | else | |
3699 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3700 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3701 | break; |
e0c6ed95 AM |
3702 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3703 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3704 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3705 | break; |
e0c6ed95 AM |
3706 | if ((delay & RS1 (~0)) == RS1 (O7) |
3707 | || ((delay & F3I (~0)) == 0 | |
3708 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3709 | break; |
3710 | /* Ensure the branch will fit into simm22. */ | |
3711 | if ((val & 0x3fe00000) | |
3712 | && (val & 0x3fe00000) != 0x3fe00000) | |
3713 | break; | |
3714 | /* Check if the arch is v9 and branch will fit | |
3715 | into simm19. */ | |
3716 | if (((val & 0x3c0000) == 0 | |
3717 | || (val & 0x3c0000) == 0x3c0000) | |
3718 | && (sparc_arch_size == 64 | |
3719 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3720 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3721 | insn = INSN_BPA | (val & 0x7ffff); |
3722 | else | |
e0c6ed95 | 3723 | /* ba */ |
6faf3d66 JJ |
3724 | insn = INSN_BA | (val & 0x3fffff); |
3725 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3726 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3727 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3728 | { |
3729 | long setter; | |
3730 | int reg; | |
3731 | ||
3732 | if (INSN_BIG_ENDIAN) | |
3733 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3734 | else | |
3735 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3736 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3737 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3738 | break; |
3739 | /* The sequence was | |
3740 | or %o7, %g0, %rN | |
3741 | call foo | |
3742 | or %rN, %g0, %o7 | |
3743 | ||
3744 | If call foo was replaced with ba, replace | |
3745 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3746 | reg = (delay & RS1 (~0)) >> 14; |
3747 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3748 | || reg == G0 || reg == O7) |
3749 | break; | |
3750 | ||
3751 | if (INSN_BIG_ENDIAN) | |
3752 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3753 | else | |
3754 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3755 | } | |
3756 | } | |
252b5132 RH |
3757 | break; |
3758 | ||
3759 | case BFD_RELOC_SPARC_11: | |
3760 | if (! in_signed_range (val, 0x7ff)) | |
3761 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3762 | _("relocation overflow")); | |
3763 | insn |= val & 0x7ff; | |
3764 | break; | |
3765 | ||
3766 | case BFD_RELOC_SPARC_10: | |
3767 | if (! in_signed_range (val, 0x3ff)) | |
3768 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3769 | _("relocation overflow")); | |
3770 | insn |= val & 0x3ff; | |
3771 | break; | |
3772 | ||
3773 | case BFD_RELOC_SPARC_7: | |
3774 | if (! in_bitfield_range (val, 0x7f)) | |
3775 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3776 | _("relocation overflow")); | |
3777 | insn |= val & 0x7f; | |
3778 | break; | |
3779 | ||
3780 | case BFD_RELOC_SPARC_6: | |
3781 | if (! in_bitfield_range (val, 0x3f)) | |
3782 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3783 | _("relocation overflow")); | |
3784 | insn |= val & 0x3f; | |
3785 | break; | |
3786 | ||
3787 | case BFD_RELOC_SPARC_5: | |
3788 | if (! in_bitfield_range (val, 0x1f)) | |
3789 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3790 | _("relocation overflow")); | |
3791 | insn |= val & 0x1f; | |
3792 | break; | |
3793 | ||
2615994e DM |
3794 | case BFD_RELOC_SPARC_WDISP10: |
3795 | if ((val & 3) | |
3796 | || val >= 0x007fc | |
3797 | || val <= -(offsetT) 0x808) | |
3798 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3799 | _("relocation overflow")); | |
3800 | /* FIXME: The +1 deserves a comment. */ | |
3801 | val = (val >> 2) + 1; | |
3802 | insn |= ((val & 0x300) << 11) | |
3803 | | ((val & 0xff) << 5); | |
3804 | break; | |
3805 | ||
252b5132 | 3806 | case BFD_RELOC_SPARC_WDISP16: |
c699f087 JJ |
3807 | if ((val & 3) |
3808 | || val >= 0x1fffc | |
3809 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3810 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3811 | _("relocation overflow")); | |
3812 | /* FIXME: The +1 deserves a comment. */ | |
3813 | val = (val >> 2) + 1; | |
3814 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3815 | break; | |
3816 | ||
3817 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3818 | if ((val & 3) |
3819 | || val >= 0xffffc | |
3820 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3821 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3822 | _("relocation overflow")); | |
3823 | /* FIXME: The +1 deserves a comment. */ | |
3824 | val = (val >> 2) + 1; | |
3825 | insn |= val & 0x7ffff; | |
3826 | break; | |
3827 | ||
3828 | case BFD_RELOC_SPARC_HH22: | |
3829 | val = BSR (val, 32); | |
e0c6ed95 | 3830 | /* Fall through. */ |
252b5132 RH |
3831 | |
3832 | case BFD_RELOC_SPARC_LM22: | |
3833 | case BFD_RELOC_HI22: | |
3834 | if (!fixP->fx_addsy) | |
94f592af | 3835 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3836 | else |
94f592af NC |
3837 | /* FIXME: Need comment explaining why we do this. */ |
3838 | insn &= ~0xffff; | |
252b5132 RH |
3839 | break; |
3840 | ||
3841 | case BFD_RELOC_SPARC22: | |
3842 | if (val & ~0x003fffff) | |
3843 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3844 | _("relocation overflow")); | |
3845 | insn |= (val & 0x3fffff); | |
3846 | break; | |
3847 | ||
3848 | case BFD_RELOC_SPARC_HM10: | |
3849 | val = BSR (val, 32); | |
e0c6ed95 | 3850 | /* Fall through. */ |
252b5132 RH |
3851 | |
3852 | case BFD_RELOC_LO10: | |
3853 | if (!fixP->fx_addsy) | |
94f592af | 3854 | insn |= val & 0x3ff; |
252b5132 | 3855 | else |
94f592af NC |
3856 | /* FIXME: Need comment explaining why we do this. */ |
3857 | insn &= ~0xff; | |
252b5132 RH |
3858 | break; |
3859 | ||
dabe3bbc RH |
3860 | case BFD_RELOC_SPARC_OLO10: |
3861 | val &= 0x3ff; | |
3862 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3863 | /* Fall through. */ |
dabe3bbc | 3864 | |
252b5132 RH |
3865 | case BFD_RELOC_SPARC13: |
3866 | if (! in_signed_range (val, 0x1fff)) | |
3867 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3868 | _("relocation overflow")); | |
3869 | insn |= val & 0x1fff; | |
3870 | break; | |
3871 | ||
3872 | case BFD_RELOC_SPARC_WDISP22: | |
3873 | val = (val >> 2) + 1; | |
e0c6ed95 | 3874 | /* Fall through. */ |
252b5132 RH |
3875 | case BFD_RELOC_SPARC_BASE22: |
3876 | insn |= val & 0x3fffff; | |
3877 | break; | |
3878 | ||
2615994e DM |
3879 | case BFD_RELOC_SPARC_H34: |
3880 | if (!fixP->fx_addsy) | |
3881 | { | |
3882 | bfd_vma tval = val; | |
3883 | tval >>= 12; | |
3884 | insn |= tval & 0x3fffff; | |
3885 | } | |
3886 | break; | |
3887 | ||
252b5132 RH |
3888 | case BFD_RELOC_SPARC_H44: |
3889 | if (!fixP->fx_addsy) | |
3890 | { | |
3891 | bfd_vma tval = val; | |
3892 | tval >>= 22; | |
3893 | insn |= tval & 0x3fffff; | |
3894 | } | |
3895 | break; | |
3896 | ||
3897 | case BFD_RELOC_SPARC_M44: | |
3898 | if (!fixP->fx_addsy) | |
3899 | insn |= (val >> 12) & 0x3ff; | |
3900 | break; | |
3901 | ||
3902 | case BFD_RELOC_SPARC_L44: | |
3903 | if (!fixP->fx_addsy) | |
3904 | insn |= val & 0xfff; | |
3905 | break; | |
3906 | ||
3907 | case BFD_RELOC_SPARC_HIX22: | |
3908 | if (!fixP->fx_addsy) | |
3909 | { | |
ab3e48dc | 3910 | val ^= ~(offsetT) 0; |
252b5132 RH |
3911 | insn |= (val >> 10) & 0x3fffff; |
3912 | } | |
3913 | break; | |
3914 | ||
3915 | case BFD_RELOC_SPARC_LOX10: | |
3916 | if (!fixP->fx_addsy) | |
3917 | insn |= 0x1c00 | (val & 0x3ff); | |
3918 | break; | |
3919 | ||
3920 | case BFD_RELOC_NONE: | |
3921 | default: | |
3922 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3923 | _("bad or unhandled relocation type: 0x%02x"), | |
3924 | fixP->fx_r_type); | |
3925 | break; | |
3926 | } | |
3927 | ||
3928 | if (INSN_BIG_ENDIAN) | |
3929 | bfd_putb32 (insn, (unsigned char *) buf); | |
3930 | else | |
3931 | bfd_putl32 (insn, (unsigned char *) buf); | |
3932 | } | |
3933 | ||
3934 | /* Are we finished with this relocation now? */ | |
3935 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3936 | fixP->fx_done = 1; | |
252b5132 RH |
3937 | } |
3938 | ||
3939 | /* Translate internal representation of relocation info to BFD target | |
3940 | format. */ | |
e0c6ed95 | 3941 | |
dabe3bbc | 3942 | arelent ** |
5a49b8ac | 3943 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3944 | { |
dabe3bbc | 3945 | static arelent *relocs[3]; |
252b5132 RH |
3946 | arelent *reloc; |
3947 | bfd_reloc_code_real_type code; | |
3948 | ||
add39d23 | 3949 | relocs[0] = reloc = XNEW (arelent); |
dabe3bbc | 3950 | relocs[1] = NULL; |
252b5132 | 3951 | |
add39d23 | 3952 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 3953 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
3954 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3955 | ||
3956 | switch (fixp->fx_r_type) | |
3957 | { | |
f6a36b0c | 3958 | case BFD_RELOC_8: |
252b5132 RH |
3959 | case BFD_RELOC_16: |
3960 | case BFD_RELOC_32: | |
f6a36b0c JC |
3961 | case BFD_RELOC_64: |
3962 | if (fixp->fx_pcrel) | |
3963 | { | |
3964 | switch (fixp->fx_size) | |
3965 | { | |
3966 | default: | |
3967 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3968 | _("can not do %d byte pc-relative relocation"), | |
3969 | fixp->fx_size); | |
3970 | code = fixp->fx_r_type; | |
3971 | fixp->fx_pcrel = 0; | |
3972 | break; | |
3973 | case 1: code = BFD_RELOC_8_PCREL; break; | |
3974 | case 2: code = BFD_RELOC_16_PCREL; break; | |
3975 | case 4: code = BFD_RELOC_32_PCREL; break; | |
3976 | #ifdef BFD64 | |
3977 | case 8: code = BFD_RELOC_64_PCREL; break; | |
3978 | #endif | |
3979 | } | |
3980 | if (fixp->fx_pcrel) | |
3981 | fixp->fx_addnumber = fixp->fx_offset; | |
3982 | break; | |
3983 | } | |
3984 | /* Fall through. */ | |
252b5132 RH |
3985 | case BFD_RELOC_HI22: |
3986 | case BFD_RELOC_LO10: | |
3987 | case BFD_RELOC_32_PCREL_S2: | |
3988 | case BFD_RELOC_SPARC13: | |
63fab58c | 3989 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3990 | case BFD_RELOC_SPARC_PC22: |
3991 | case BFD_RELOC_SPARC_PC10: | |
252b5132 | 3992 | case BFD_RELOC_SPARC_BASE13: |
2615994e | 3993 | case BFD_RELOC_SPARC_WDISP10: |
252b5132 RH |
3994 | case BFD_RELOC_SPARC_WDISP16: |
3995 | case BFD_RELOC_SPARC_WDISP19: | |
3996 | case BFD_RELOC_SPARC_WDISP22: | |
252b5132 RH |
3997 | case BFD_RELOC_SPARC_5: |
3998 | case BFD_RELOC_SPARC_6: | |
3999 | case BFD_RELOC_SPARC_7: | |
4000 | case BFD_RELOC_SPARC_10: | |
4001 | case BFD_RELOC_SPARC_11: | |
4002 | case BFD_RELOC_SPARC_HH22: | |
4003 | case BFD_RELOC_SPARC_HM10: | |
4004 | case BFD_RELOC_SPARC_LM22: | |
4005 | case BFD_RELOC_SPARC_PC_HH22: | |
4006 | case BFD_RELOC_SPARC_PC_HM10: | |
4007 | case BFD_RELOC_SPARC_PC_LM22: | |
2615994e | 4008 | case BFD_RELOC_SPARC_H34: |
252b5132 RH |
4009 | case BFD_RELOC_SPARC_H44: |
4010 | case BFD_RELOC_SPARC_M44: | |
4011 | case BFD_RELOC_SPARC_L44: | |
4012 | case BFD_RELOC_SPARC_HIX22: | |
4013 | case BFD_RELOC_SPARC_LOX10: | |
4014 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 4015 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
4016 | case BFD_RELOC_SPARC_UA16: |
4017 | case BFD_RELOC_SPARC_UA32: | |
4018 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
4019 | case BFD_RELOC_8_PCREL: |
4020 | case BFD_RELOC_16_PCREL: | |
4021 | case BFD_RELOC_32_PCREL: | |
4022 | case BFD_RELOC_64_PCREL: | |
4023 | case BFD_RELOC_SPARC_PLT32: | |
4024 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
4025 | case BFD_RELOC_VTABLE_ENTRY: |
4026 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
4027 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
4028 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
4029 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
4030 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
4031 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
4032 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
4033 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
4034 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
4035 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
4036 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
4037 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
4038 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
4039 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
4040 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
4041 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
4042 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
4043 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
4044 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
4045 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
4046 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
4047 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
4048 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
4049 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
4050 | code = fixp->fx_r_type; |
4051 | break; | |
4052 | default: | |
4053 | abort (); | |
4054 | return NULL; | |
4055 | } | |
4056 | ||
4057 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
4058 | /* If we are generating PIC code, we need to generate a different | |
4059 | set of relocs. */ | |
4060 | ||
4061 | #ifdef OBJ_ELF | |
4062 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
4063 | #else | |
4064 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
4065 | #endif |
4066 | #ifdef TE_VXWORKS | |
4067 | #define GOTT_BASE "__GOTT_BASE__" | |
4068 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
4069 | #endif |
4070 | ||
153b546a ILT |
4071 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
4072 | ||
252b5132 RH |
4073 | if (sparc_pic_code) |
4074 | { | |
4075 | switch (code) | |
4076 | { | |
4077 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 4078 | if (generic_force_reloc (fixp)) |
252b5132 RH |
4079 | code = BFD_RELOC_SPARC_WPLT30; |
4080 | break; | |
4081 | case BFD_RELOC_HI22: | |
910600e9 RS |
4082 | code = BFD_RELOC_SPARC_GOT22; |
4083 | if (fixp->fx_addsy != NULL) | |
4084 | { | |
4085 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
4086 | code = BFD_RELOC_SPARC_PC22; | |
4087 | #ifdef TE_VXWORKS | |
4088 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
4089 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
4090 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
4091 | #endif | |
4092 | } | |
252b5132 RH |
4093 | break; |
4094 | case BFD_RELOC_LO10: | |
910600e9 RS |
4095 | code = BFD_RELOC_SPARC_GOT10; |
4096 | if (fixp->fx_addsy != NULL) | |
4097 | { | |
4098 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
4099 | code = BFD_RELOC_SPARC_PC10; | |
4100 | #ifdef TE_VXWORKS | |
4101 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
4102 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
4103 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
4104 | #endif | |
4105 | } | |
252b5132 RH |
4106 | break; |
4107 | case BFD_RELOC_SPARC13: | |
4108 | code = BFD_RELOC_SPARC_GOT13; | |
4109 | break; | |
4110 | default: | |
4111 | break; | |
4112 | } | |
4113 | } | |
e0c6ed95 | 4114 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 4115 | |
062cf837 EB |
4116 | /* Nothing is aligned in DWARF debugging sections. */ |
4117 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
4118 | switch (code) | |
4119 | { | |
4120 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
4121 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
4122 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
4123 | default: break; | |
4124 | } | |
4125 | ||
dabe3bbc RH |
4126 | if (code == BFD_RELOC_SPARC_OLO10) |
4127 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
4128 | else | |
4129 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
4130 | if (reloc->howto == 0) |
4131 | { | |
4132 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
4133 | _("internal error: can't export reloc type %d (`%s')"), | |
4134 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
4135 | xfree (reloc); |
4136 | relocs[0] = NULL; | |
4137 | return relocs; | |
252b5132 RH |
4138 | } |
4139 | ||
4140 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
4141 | #ifdef OBJ_AOUT | |
4142 | ||
4143 | if (reloc->howto->pc_relative == 0 | |
4144 | || code == BFD_RELOC_SPARC_PC10 | |
4145 | || code == BFD_RELOC_SPARC_PC22) | |
4146 | reloc->addend = fixp->fx_addnumber; | |
4147 | else if (sparc_pic_code | |
4148 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
4149 | && fixp->fx_addsy != NULL | |
4150 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
4151 | || S_IS_WEAK (fixp->fx_addsy)) | |
4152 | && S_IS_DEFINED (fixp->fx_addsy) | |
4153 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
4154 | reloc->addend = fixp->fx_addnumber; | |
4155 | else | |
4156 | reloc->addend = fixp->fx_offset - reloc->address; | |
4157 | ||
e0c6ed95 | 4158 | #else /* elf or coff */ |
252b5132 | 4159 | |
bd5e6e7e JJ |
4160 | if (code != BFD_RELOC_32_PCREL_S2 |
4161 | && code != BFD_RELOC_SPARC_WDISP22 | |
4162 | && code != BFD_RELOC_SPARC_WDISP16 | |
4163 | && code != BFD_RELOC_SPARC_WDISP19 | |
2615994e | 4164 | && code != BFD_RELOC_SPARC_WDISP10 |
b9734f35 JJ |
4165 | && code != BFD_RELOC_SPARC_WPLT30 |
4166 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
4167 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 4168 | reloc->addend = fixp->fx_addnumber; |
49309057 | 4169 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
4170 | reloc->addend = (section->vma |
4171 | + fixp->fx_addnumber | |
4172 | + md_pcrel_from (fixp)); | |
4173 | else | |
4174 | reloc->addend = fixp->fx_offset; | |
4175 | #endif | |
4176 | ||
dabe3bbc RH |
4177 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
4178 | on the same location. */ | |
4179 | if (code == BFD_RELOC_SPARC_OLO10) | |
4180 | { | |
add39d23 | 4181 | relocs[1] = reloc = XNEW (arelent); |
dabe3bbc RH |
4182 | relocs[2] = NULL; |
4183 | ||
add39d23 | 4184 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
ab3e48dc KH |
4185 | *reloc->sym_ptr_ptr |
4186 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
4187 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
4188 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
4189 | reloc->addend = fixp->tc_fix_data; | |
4190 | } | |
4191 | ||
4192 | return relocs; | |
252b5132 RH |
4193 | } |
4194 | \f | |
e0c6ed95 | 4195 | /* We have no need to default values of symbols. */ |
252b5132 | 4196 | |
252b5132 | 4197 | symbolS * |
5a49b8ac | 4198 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
4199 | { |
4200 | return 0; | |
e0c6ed95 AM |
4201 | } |
4202 | ||
4203 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 4204 | |
252b5132 | 4205 | valueT |
5a49b8ac | 4206 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
4207 | { |
4208 | #ifndef OBJ_ELF | |
4209 | /* This is not right for ELF; a.out wants it, and COFF will force | |
4210 | the alignment anyways. */ | |
4211 | valueT align = ((valueT) 1 | |
4212 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
4213 | valueT newsize; | |
e0c6ed95 AM |
4214 | |
4215 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
4216 | align--; |
4217 | newsize = (size + align) & ~align; | |
4218 | return newsize; | |
4219 | #else | |
4220 | return size; | |
4221 | #endif | |
4222 | } | |
4223 | ||
4224 | /* Exactly what point is a PC-relative offset relative TO? | |
4225 | On the sparc, they're relative to the address of the offset, plus | |
4226 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
4227 | (??? Is this right? FIXME-SOON) */ |
4228 | long | |
5a49b8ac | 4229 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
4230 | { |
4231 | long ret; | |
4232 | ||
4233 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
4234 | if (! sparc_pic_code | |
4235 | || fixP->fx_addsy == NULL | |
49309057 | 4236 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
4237 | ret += fixP->fx_size; |
4238 | return ret; | |
4239 | } | |
4240 | \f | |
4241 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
4242 | of two. */ | |
4243 | ||
4244 | static int | |
5a49b8ac | 4245 | mylog2 (int value) |
252b5132 RH |
4246 | { |
4247 | int shift; | |
4248 | ||
4249 | if (value <= 0) | |
4250 | return -1; | |
4251 | ||
4252 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
4253 | ++shift; | |
4254 | ||
4255 | return (value == 1) ? shift : -1; | |
4256 | } | |
4257 | ||
e0c6ed95 | 4258 | /* Sort of like s_lcomm. */ |
252b5132 RH |
4259 | |
4260 | #ifndef OBJ_ELF | |
4261 | static int max_alignment = 15; | |
4262 | #endif | |
4263 | ||
4264 | static void | |
5a49b8ac | 4265 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4266 | { |
4267 | char *name; | |
4268 | char *p; | |
4269 | char c; | |
4270 | int align; | |
4271 | int size; | |
4272 | int temp; | |
4273 | symbolS *symbolP; | |
4274 | ||
d02603dc | 4275 | c = get_symbol_name (&name); |
252b5132 RH |
4276 | p = input_line_pointer; |
4277 | *p = c; | |
d02603dc | 4278 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4279 | |
4280 | if (*input_line_pointer != ',') | |
4281 | { | |
4282 | as_bad (_("Expected comma after name")); | |
4283 | ignore_rest_of_line (); | |
4284 | return; | |
4285 | } | |
4286 | ||
4287 | ++input_line_pointer; | |
4288 | ||
4289 | if ((size = get_absolute_expression ()) < 0) | |
4290 | { | |
4291 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
4292 | ignore_rest_of_line (); | |
4293 | return; | |
e0c6ed95 | 4294 | } /* Bad length. */ |
252b5132 RH |
4295 | |
4296 | *p = 0; | |
4297 | symbolP = symbol_find_or_make (name); | |
4298 | *p = c; | |
4299 | ||
4300 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
4301 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
4302 | { | |
4303 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
4304 | return; | |
4305 | } | |
4306 | ||
4307 | if (input_line_pointer[2] == '.') | |
4308 | input_line_pointer += 7; | |
4309 | else | |
4310 | input_line_pointer += 6; | |
4311 | SKIP_WHITESPACE (); | |
4312 | ||
4313 | if (*input_line_pointer == ',') | |
4314 | { | |
4315 | ++input_line_pointer; | |
4316 | ||
4317 | SKIP_WHITESPACE (); | |
4318 | if (*input_line_pointer == '\n') | |
4319 | { | |
4320 | as_bad (_("missing alignment")); | |
4321 | ignore_rest_of_line (); | |
4322 | return; | |
4323 | } | |
4324 | ||
4325 | align = (int) get_absolute_expression (); | |
4326 | ||
4327 | #ifndef OBJ_ELF | |
4328 | if (align > max_alignment) | |
4329 | { | |
4330 | align = max_alignment; | |
4331 | as_warn (_("alignment too large; assuming %d"), align); | |
4332 | } | |
4333 | #endif | |
4334 | ||
4335 | if (align < 0) | |
4336 | { | |
4337 | as_bad (_("negative alignment")); | |
4338 | ignore_rest_of_line (); | |
4339 | return; | |
4340 | } | |
4341 | ||
4342 | if (align != 0) | |
4343 | { | |
f17c130b | 4344 | temp = mylog2 (align); |
252b5132 RH |
4345 | if (temp < 0) |
4346 | { | |
4347 | as_bad (_("alignment not a power of 2")); | |
4348 | ignore_rest_of_line (); | |
4349 | return; | |
4350 | } | |
4351 | ||
4352 | align = temp; | |
4353 | } | |
4354 | ||
4355 | record_alignment (bss_section, align); | |
4356 | } | |
4357 | else | |
4358 | align = 0; | |
4359 | ||
4360 | if (!S_IS_DEFINED (symbolP) | |
4361 | #ifdef OBJ_AOUT | |
4362 | && S_GET_OTHER (symbolP) == 0 | |
4363 | && S_GET_DESC (symbolP) == 0 | |
4364 | #endif | |
4365 | ) | |
4366 | { | |
4367 | if (! need_pass_2) | |
4368 | { | |
4369 | char *pfrag; | |
4370 | segT current_seg = now_seg; | |
4371 | subsegT current_subseg = now_subseg; | |
4372 | ||
e0c6ed95 AM |
4373 | /* Switch to bss. */ |
4374 | subseg_set (bss_section, 1); | |
252b5132 RH |
4375 | |
4376 | if (align) | |
e0c6ed95 AM |
4377 | /* Do alignment. */ |
4378 | frag_align (align, 0, 0); | |
252b5132 | 4379 | |
e0c6ed95 | 4380 | /* Detach from old frag. */ |
ab3e48dc | 4381 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 4382 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 4383 | |
49309057 | 4384 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
4385 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4386 | (offsetT) size, (char *) 0); | |
252b5132 RH |
4387 | *pfrag = 0; |
4388 | ||
4389 | S_SET_SEGMENT (symbolP, bss_section); | |
4390 | ||
4391 | subseg_set (current_seg, current_subseg); | |
4392 | ||
4393 | #ifdef OBJ_ELF | |
4394 | S_SET_SIZE (symbolP, size); | |
4395 | #endif | |
4396 | } | |
4397 | } | |
4398 | else | |
4399 | { | |
20203fb9 | 4400 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 4401 | S_GET_NAME (symbolP)); |
20203fb9 | 4402 | } |
252b5132 RH |
4403 | |
4404 | demand_empty_rest_of_line (); | |
4405 | } | |
4406 | ||
4407 | static void | |
5a49b8ac | 4408 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4409 | { |
4410 | char *name; | |
4411 | char c; | |
4412 | char *p; | |
685736be | 4413 | offsetT temp, size; |
252b5132 RH |
4414 | symbolS *symbolP; |
4415 | ||
d02603dc | 4416 | c = get_symbol_name (&name); |
e0c6ed95 | 4417 | /* Just after name is now '\0'. */ |
252b5132 RH |
4418 | p = input_line_pointer; |
4419 | *p = c; | |
d02603dc | 4420 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4421 | if (*input_line_pointer != ',') |
4422 | { | |
4423 | as_bad (_("Expected comma after symbol-name")); | |
4424 | ignore_rest_of_line (); | |
4425 | return; | |
4426 | } | |
e0c6ed95 AM |
4427 | |
4428 | /* Skip ','. */ | |
4429 | input_line_pointer++; | |
4430 | ||
252b5132 RH |
4431 | if ((temp = get_absolute_expression ()) < 0) |
4432 | { | |
685736be NC |
4433 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
4434 | (unsigned long) temp); | |
252b5132 RH |
4435 | ignore_rest_of_line (); |
4436 | return; | |
4437 | } | |
4438 | size = temp; | |
4439 | *p = 0; | |
4440 | symbolP = symbol_find_or_make (name); | |
4441 | *p = c; | |
4442 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
4443 | { | |
4444 | as_bad (_("Ignoring attempt to re-define symbol")); | |
4445 | ignore_rest_of_line (); | |
4446 | return; | |
4447 | } | |
4448 | if (S_GET_VALUE (symbolP) != 0) | |
4449 | { | |
4450 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
4451 | { | |
364b6d8b JJ |
4452 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
4453 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
4454 | } |
4455 | } | |
4456 | else | |
4457 | { | |
4458 | #ifndef OBJ_ELF | |
4459 | S_SET_VALUE (symbolP, (valueT) size); | |
4460 | S_SET_EXTERNAL (symbolP); | |
4461 | #endif | |
4462 | } | |
7dcc9865 | 4463 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
4464 | if (*input_line_pointer != ',') |
4465 | { | |
4466 | as_bad (_("Expected comma after common length")); | |
4467 | ignore_rest_of_line (); | |
4468 | return; | |
4469 | } | |
4470 | input_line_pointer++; | |
4471 | SKIP_WHITESPACE (); | |
4472 | if (*input_line_pointer != '"') | |
4473 | { | |
4474 | temp = get_absolute_expression (); | |
4475 | ||
4476 | #ifndef OBJ_ELF | |
4477 | if (temp > max_alignment) | |
4478 | { | |
4479 | temp = max_alignment; | |
f17c130b | 4480 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
4481 | } |
4482 | #endif | |
4483 | ||
4484 | if (temp < 0) | |
4485 | { | |
4486 | as_bad (_("negative alignment")); | |
4487 | ignore_rest_of_line (); | |
4488 | return; | |
4489 | } | |
4490 | ||
4491 | #ifdef OBJ_ELF | |
49309057 | 4492 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
4493 | { |
4494 | segT old_sec; | |
4495 | int old_subsec; | |
252b5132 RH |
4496 | int align; |
4497 | ||
4498 | old_sec = now_seg; | |
4499 | old_subsec = now_subseg; | |
4500 | ||
4501 | if (temp == 0) | |
4502 | align = 0; | |
4503 | else | |
f17c130b | 4504 | align = mylog2 (temp); |
252b5132 RH |
4505 | |
4506 | if (align < 0) | |
4507 | { | |
4508 | as_bad (_("alignment not a power of 2")); | |
4509 | ignore_rest_of_line (); | |
4510 | return; | |
4511 | } | |
4512 | ||
4513 | record_alignment (bss_section, align); | |
4514 | subseg_set (bss_section, 0); | |
4515 | if (align) | |
4516 | frag_align (align, 0, 0); | |
4517 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
4518 | symbol_get_frag (symbolP)->fr_symbol = 0; |
4519 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
4520 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4521 | (offsetT) size, (char *) 0); | |
4522 | *p = 0; | |
4523 | S_SET_SEGMENT (symbolP, bss_section); | |
4524 | S_CLEAR_EXTERNAL (symbolP); | |
4525 | S_SET_SIZE (symbolP, size); | |
4526 | subseg_set (old_sec, old_subsec); | |
4527 | } | |
4528 | else | |
e0c6ed95 | 4529 | #endif /* OBJ_ELF */ |
252b5132 RH |
4530 | { |
4531 | allocate_common: | |
4532 | S_SET_VALUE (symbolP, (valueT) size); | |
4533 | #ifdef OBJ_ELF | |
4534 | S_SET_ALIGN (symbolP, temp); | |
4535 | S_SET_SIZE (symbolP, size); | |
4536 | #endif | |
4537 | S_SET_EXTERNAL (symbolP); | |
4538 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
4539 | } | |
4540 | } | |
4541 | else | |
4542 | { | |
4543 | input_line_pointer++; | |
4544 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
4545 | if (*input_line_pointer == '.') | |
4546 | input_line_pointer++; | |
4547 | /* @@ Some say data, some say bss. */ | |
4548 | if (strncmp (input_line_pointer, "bss\"", 4) | |
4549 | && strncmp (input_line_pointer, "data\"", 5)) | |
4550 | { | |
4551 | while (*--input_line_pointer != '"') | |
4552 | ; | |
4553 | input_line_pointer--; | |
4554 | goto bad_common_segment; | |
4555 | } | |
4556 | while (*input_line_pointer++ != '"') | |
4557 | ; | |
4558 | goto allocate_common; | |
4559 | } | |
4560 | ||
49309057 | 4561 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4562 | |
4563 | demand_empty_rest_of_line (); | |
4564 | return; | |
4565 | ||
4566 | { | |
4567 | bad_common_segment: | |
4568 | p = input_line_pointer; | |
4569 | while (*p && *p != '\n') | |
4570 | p++; | |
4571 | c = *p; | |
4572 | *p = '\0'; | |
4573 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4574 | *p = c; | |
4575 | input_line_pointer = p; | |
4576 | ignore_rest_of_line (); | |
4577 | return; | |
4578 | } | |
4579 | } | |
4580 | ||
67c1ffbe | 4581 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4582 | invalid delay slot usage. */ |
4583 | ||
4584 | static void | |
5a49b8ac | 4585 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4586 | { |
4587 | /* The easy way to implement is to just forget about the last | |
4588 | instruction. */ | |
4589 | last_insn = NULL; | |
4590 | } | |
4591 | ||
4592 | static void | |
5a49b8ac | 4593 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4594 | { |
4595 | ||
4596 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4597 | { | |
4598 | input_line_pointer += 6; | |
4599 | s_text (0); | |
4600 | return; | |
4601 | } | |
4602 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4603 | { | |
4604 | input_line_pointer += 6; | |
4605 | s_data (0); | |
4606 | return; | |
4607 | } | |
4608 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4609 | { | |
4610 | input_line_pointer += 7; | |
4611 | s_data1 (); | |
4612 | return; | |
4613 | } | |
4614 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4615 | { | |
4616 | input_line_pointer += 5; | |
4617 | /* We only support 2 segments -- text and data -- for now, so | |
4618 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4619 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4620 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4621 | return; |
4622 | } | |
4623 | as_bad (_("Unknown segment type")); | |
4624 | demand_empty_rest_of_line (); | |
4625 | } | |
4626 | ||
4627 | static void | |
5a49b8ac | 4628 | s_data1 (void) |
252b5132 RH |
4629 | { |
4630 | subseg_set (data_section, 1); | |
4631 | demand_empty_rest_of_line (); | |
4632 | } | |
4633 | ||
4634 | static void | |
5a49b8ac | 4635 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4636 | { |
4637 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4638 | { | |
4639 | ++input_line_pointer; | |
4640 | } | |
4641 | ++input_line_pointer; | |
4642 | } | |
4643 | ||
4644 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4645 | that the expression does not need to be aligned. */ |
252b5132 RH |
4646 | |
4647 | static int sparc_no_align_cons = 0; | |
4648 | ||
4649 | /* This handles the unaligned space allocation pseudo-ops, such as | |
4650 | .uaword. .uaword is just like .word, but the value does not need | |
4651 | to be aligned. */ | |
4652 | ||
4653 | static void | |
5a49b8ac | 4654 | s_uacons (int bytes) |
252b5132 RH |
4655 | { |
4656 | /* Tell sparc_cons_align not to align this value. */ | |
4657 | sparc_no_align_cons = 1; | |
4658 | cons (bytes); | |
4ffadb11 | 4659 | sparc_no_align_cons = 0; |
252b5132 RH |
4660 | } |
4661 | ||
cf9a1301 RH |
4662 | /* This handles the native word allocation pseudo-op .nword. |
4663 | For sparc_arch_size 32 it is equivalent to .word, for | |
4664 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4665 | ||
4666 | static void | |
5a49b8ac | 4667 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4668 | { |
4669 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4670 | } | |
4671 | ||
6d8809aa RH |
4672 | #ifdef OBJ_ELF |
4673 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4674 | global register. | |
4675 | The syntax is: | |
e0c6ed95 | 4676 | |
6d8809aa | 4677 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4678 | */ |
6d8809aa RH |
4679 | |
4680 | static void | |
5a49b8ac | 4681 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4682 | { |
4683 | char c; | |
4684 | int reg; | |
4685 | int flags; | |
d02603dc | 4686 | char *regname; |
6d8809aa RH |
4687 | |
4688 | if (input_line_pointer[0] != '%' | |
4689 | || input_line_pointer[1] != 'g' | |
4690 | || ((input_line_pointer[2] & ~1) != '2' | |
4691 | && (input_line_pointer[2] & ~1) != '6') | |
4692 | || input_line_pointer[3] != ',') | |
4693 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4694 | reg = input_line_pointer[2] - '0'; | |
4695 | input_line_pointer += 4; | |
4696 | ||
4697 | if (*input_line_pointer == '#') | |
4698 | { | |
4699 | ++input_line_pointer; | |
d02603dc | 4700 | c = get_symbol_name (®name); |
6d8809aa RH |
4701 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) |
4702 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4703 | if (regname[0] == 'i') |
6d8809aa RH |
4704 | regname = NULL; |
4705 | else | |
e87de513 | 4706 | regname = (char *) ""; |
6d8809aa RH |
4707 | } |
4708 | else | |
4709 | { | |
d02603dc | 4710 | c = get_symbol_name (®name); |
6d8809aa | 4711 | } |
d02603dc | 4712 | |
6d8809aa RH |
4713 | if (sparc_arch_size == 64) |
4714 | { | |
e0c6ed95 | 4715 | if (globals[reg]) |
6d8809aa | 4716 | { |
e0c6ed95 AM |
4717 | if ((regname && globals[reg] != (symbolS *) 1 |
4718 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4719 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4720 | as_bad (_("redefinition of global register")); |
4721 | } | |
4722 | else | |
4723 | { | |
4724 | if (regname == NULL) | |
e0c6ed95 | 4725 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4726 | else |
4727 | { | |
4728 | if (*regname) | |
4729 | { | |
4730 | if (symbol_find (regname)) | |
4731 | as_bad (_("Register symbol %s already defined."), | |
4732 | regname); | |
4733 | } | |
e0c6ed95 AM |
4734 | globals[reg] = symbol_make (regname); |
4735 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4736 | if (! *regname) |
4737 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4738 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4739 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4740 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4741 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4742 | S_SET_ALIGN (globals[reg], reg); | |
4743 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4744 | /* Although we actually want undefined_section here, |
4745 | we have to use absolute_section, because otherwise | |
4746 | generic as code will make it a COM section. | |
4747 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4748 | S_SET_SEGMENT (globals[reg], absolute_section); |
4749 | S_SET_OTHER (globals[reg], 0); | |
4750 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4751 | ->internal_elf_sym.st_info = |
4752 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4753 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4754 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4755 | } | |
4756 | } | |
4757 | } | |
4758 | ||
d02603dc | 4759 | (void) restore_line_pointer (c); |
6d8809aa RH |
4760 | |
4761 | demand_empty_rest_of_line (); | |
4762 | } | |
4763 | ||
4764 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4765 | symbols which need it. */ | |
e0c6ed95 | 4766 | |
6d8809aa | 4767 | void |
5a49b8ac | 4768 | sparc_adjust_symtab (void) |
6d8809aa RH |
4769 | { |
4770 | symbolS *sym; | |
e0c6ed95 | 4771 | |
6d8809aa RH |
4772 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4773 | { | |
4774 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4775 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4776 | continue; | |
4777 | ||
4778 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4779 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4780 | continue; | |
4781 | ||
4782 | S_SET_SEGMENT (sym, undefined_section); | |
4783 | } | |
4784 | } | |
4785 | #endif | |
4786 | ||
252b5132 RH |
4787 | /* If the --enforce-aligned-data option is used, we require .word, |
4788 | et. al., to be aligned correctly. We do it by setting up an | |
4789 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4790 | no unexpected alignment was introduced. | |
4791 | ||
4792 | The SunOS and Solaris native assemblers enforce aligned data by | |
4793 | default. We don't want to do that, because gcc can deliberately | |
4794 | generate misaligned data if the packed attribute is used. Instead, | |
4795 | we permit misaligned data by default, and permit the user to set an | |
4796 | option to check for it. */ | |
4797 | ||
4798 | void | |
5a49b8ac | 4799 | sparc_cons_align (int nbytes) |
252b5132 RH |
4800 | { |
4801 | int nalign; | |
252b5132 RH |
4802 | |
4803 | /* Only do this if we are enforcing aligned data. */ | |
4804 | if (! enforce_aligned_data) | |
4805 | return; | |
4806 | ||
0f2712ed | 4807 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4808 | if (sparc_no_align_cons) |
0f2712ed | 4809 | return; |
252b5132 | 4810 | |
f17c130b | 4811 | nalign = mylog2 (nbytes); |
252b5132 RH |
4812 | if (nalign == 0) |
4813 | return; | |
4814 | ||
9c2799c2 | 4815 | gas_assert (nalign > 0); |
252b5132 RH |
4816 | |
4817 | if (now_seg == absolute_section) | |
4818 | { | |
4819 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4820 | as_bad (_("misaligned data")); | |
4821 | return; | |
4822 | } | |
4823 | ||
87975d2a AM |
4824 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4825 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4826 | |
4827 | record_alignment (now_seg, nalign); | |
4828 | } | |
4829 | ||
0a9ef439 | 4830 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4831 | |
4832 | void | |
5a49b8ac | 4833 | sparc_handle_align (fragS *fragp) |
252b5132 | 4834 | { |
0a9ef439 RH |
4835 | int count, fix; |
4836 | char *p; | |
4837 | ||
4838 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4839 | |
0a9ef439 | 4840 | switch (fragp->fr_type) |
252b5132 | 4841 | { |
0a9ef439 RH |
4842 | case rs_align_test: |
4843 | if (count != 0) | |
4844 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4845 | break; | |
e0c6ed95 | 4846 | |
0a9ef439 RH |
4847 | case rs_align_code: |
4848 | p = fragp->fr_literal + fragp->fr_fix; | |
4849 | fix = 0; | |
e0c6ed95 | 4850 | |
0a9ef439 RH |
4851 | if (count & 3) |
4852 | { | |
4853 | fix = count & 3; | |
4854 | memset (p, 0, fix); | |
4855 | p += fix; | |
4856 | count -= fix; | |
4857 | } | |
e0c6ed95 | 4858 | |
0a9ef439 RH |
4859 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4860 | { | |
4861 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4862 | if (INSN_BIG_ENDIAN) | |
4863 | number_to_chars_bigendian (p, wval, 4); | |
4864 | else | |
4865 | number_to_chars_littleendian (p, wval, 4); | |
4866 | p += 4; | |
4867 | count -= 4; | |
4868 | fix += 4; | |
e0c6ed95 | 4869 | } |
0a9ef439 RH |
4870 | |
4871 | if (INSN_BIG_ENDIAN) | |
4872 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4873 | else | |
4874 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4875 | ||
4876 | fragp->fr_fix += fix; | |
4877 | fragp->fr_var = 4; | |
4878 | break; | |
4879 | ||
4880 | default: | |
4881 | break; | |
252b5132 RH |
4882 | } |
4883 | } | |
4884 | ||
4885 | #ifdef OBJ_ELF | |
4886 | /* Some special processing for a Sparc ELF file. */ | |
4887 | ||
4888 | void | |
5a49b8ac | 4889 | sparc_elf_final_processing (void) |
252b5132 RH |
4890 | { |
4891 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4892 | sort of BFD interface for this. */ | |
4893 | if (sparc_arch_size == 64) | |
4894 | { | |
4895 | switch (sparc_memory_model) | |
4896 | { | |
4897 | case MM_RMO: | |
4898 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4899 | break; | |
4900 | case MM_PSO: | |
4901 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4902 | break; | |
4903 | default: | |
4904 | break; | |
4905 | } | |
4906 | } | |
4907 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4908 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4909 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4910 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4911 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4912 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4913 | } |
bd5e6e7e | 4914 | |
62ebcb5c | 4915 | const char * |
5a49b8ac | 4916 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4917 | { |
4918 | char *save; | |
62ebcb5c | 4919 | const char *sparc_cons_special_reloc = NULL; |
bd5e6e7e JJ |
4920 | |
4921 | SKIP_WHITESPACE (); | |
bd5e6e7e JJ |
4922 | save = input_line_pointer; |
4923 | if (input_line_pointer[0] == '%' | |
4924 | && input_line_pointer[1] == 'r' | |
4925 | && input_line_pointer[2] == '_') | |
4926 | { | |
4927 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4928 | { | |
4929 | input_line_pointer += 7; | |
4930 | sparc_cons_special_reloc = "disp"; | |
4931 | } | |
4932 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4933 | { | |
4934 | if (size != 4 && size != 8) | |
4935 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4936 | else | |
4937 | { | |
4938 | input_line_pointer += 6; | |
4939 | sparc_cons_special_reloc = "plt"; | |
4940 | } | |
4941 | } | |
b9734f35 JJ |
4942 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4943 | { | |
4944 | if (size != 4 && size != 8) | |
4945 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4946 | else | |
4947 | { | |
4948 | input_line_pointer += 13; | |
4949 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4950 | } | |
4951 | } | |
bd5e6e7e JJ |
4952 | if (sparc_cons_special_reloc) |
4953 | { | |
4954 | int bad = 0; | |
4955 | ||
4956 | switch (size) | |
4957 | { | |
4958 | case 1: | |
4959 | if (*input_line_pointer != '8') | |
4960 | bad = 1; | |
4961 | input_line_pointer--; | |
4962 | break; | |
4963 | case 2: | |
4964 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4965 | bad = 1; | |
4966 | break; | |
4967 | case 4: | |
4968 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4969 | bad = 1; | |
4970 | break; | |
4971 | case 8: | |
4972 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4973 | bad = 1; | |
4974 | break; | |
4975 | default: | |
4976 | bad = 1; | |
4977 | break; | |
4978 | } | |
4979 | ||
4980 | if (bad) | |
4981 | { | |
4982 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4983 | sparc_cons_special_reloc, size * 8, size); | |
4984 | } | |
4985 | else | |
4986 | { | |
4987 | input_line_pointer += 2; | |
4988 | if (*input_line_pointer != '(') | |
4989 | { | |
4990 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4991 | sparc_cons_special_reloc, size * 8); | |
4992 | bad = 1; | |
4993 | } | |
4994 | } | |
4995 | ||
4996 | if (bad) | |
4997 | { | |
4998 | input_line_pointer = save; | |
4999 | sparc_cons_special_reloc = NULL; | |
5000 | } | |
5001 | else | |
5002 | { | |
5003 | int c; | |
5004 | char *end = ++input_line_pointer; | |
5005 | int npar = 0; | |
5006 | ||
5007 | while (! is_end_of_line[(c = *end)]) | |
5008 | { | |
5009 | if (c == '(') | |
5010 | npar++; | |
5011 | else if (c == ')') | |
5012 | { | |
5013 | if (!npar) | |
5014 | break; | |
5015 | npar--; | |
5016 | } | |
5017 | end++; | |
5018 | } | |
5019 | ||
5020 | if (c != ')') | |
5021 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
5022 | sparc_cons_special_reloc, size * 8); | |
5023 | else | |
5024 | { | |
5025 | *end = '\0'; | |
5026 | expression (exp); | |
5027 | *end = c; | |
5028 | if (input_line_pointer != end) | |
5029 | { | |
5030 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
5031 | sparc_cons_special_reloc, size * 8); | |
5032 | } | |
5033 | else | |
5034 | { | |
5035 | input_line_pointer++; | |
5036 | SKIP_WHITESPACE (); | |
5037 | c = *input_line_pointer; | |
5038 | if (! is_end_of_line[c] && c != ',') | |
5039 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
5040 | sparc_cons_special_reloc, size * 8); | |
5041 | } | |
5042 | } | |
5043 | } | |
5044 | } | |
5045 | } | |
5046 | if (sparc_cons_special_reloc == NULL) | |
5047 | expression (exp); | |
62ebcb5c | 5048 | return sparc_cons_special_reloc; |
bd5e6e7e JJ |
5049 | } |
5050 | ||
252b5132 RH |
5051 | #endif |
5052 | ||
5053 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
5054 | reloc for a cons. We could use the definition there, except that | |
5055 | we want to handle little endian relocs specially. */ | |
5056 | ||
5057 | void | |
5a49b8ac AM |
5058 | cons_fix_new_sparc (fragS *frag, |
5059 | int where, | |
5060 | unsigned int nbytes, | |
62ebcb5c AM |
5061 | expressionS *exp, |
5062 | const char *sparc_cons_special_reloc) | |
252b5132 RH |
5063 | { |
5064 | bfd_reloc_code_real_type r; | |
5065 | ||
5066 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
5067 | (nbytes == 2 ? BFD_RELOC_16 : | |
5068 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
5069 | ||
0f2712ed NC |
5070 | if (target_little_endian_data |
5071 | && nbytes == 4 | |
e0c6ed95 | 5072 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 5073 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 5074 | |
02442566 ST |
5075 | #ifdef TE_SOLARIS |
5076 | /* The Solaris linker does not allow R_SPARC_UA64 | |
5077 | relocations for 32-bit executables. */ | |
5078 | if (!target_little_endian_data | |
5079 | && sparc_arch_size != 64 | |
5080 | && r == BFD_RELOC_64) | |
5081 | r = BFD_RELOC_32; | |
5082 | #endif | |
5083 | ||
bd5e6e7e JJ |
5084 | if (sparc_cons_special_reloc) |
5085 | { | |
5086 | if (*sparc_cons_special_reloc == 'd') | |
5087 | switch (nbytes) | |
5088 | { | |
5089 | case 1: r = BFD_RELOC_8_PCREL; break; | |
5090 | case 2: r = BFD_RELOC_16_PCREL; break; | |
5091 | case 4: r = BFD_RELOC_32_PCREL; break; | |
5092 | case 8: r = BFD_RELOC_64_PCREL; break; | |
5093 | default: abort (); | |
5094 | } | |
b9734f35 | 5095 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
5096 | switch (nbytes) |
5097 | { | |
5098 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
5099 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
5100 | } | |
b9734f35 JJ |
5101 | else |
5102 | switch (nbytes) | |
5103 | { | |
5104 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
5105 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
5106 | } | |
bd5e6e7e | 5107 | } |
93ca3936 NC |
5108 | else if (sparc_no_align_cons |
5109 | || /* PR 20803 - relocs in the .eh_frame section | |
5110 | need to support unaligned access. */ | |
5111 | strcmp (now_seg->name, ".eh_frame") == 0) | |
0f2712ed NC |
5112 | { |
5113 | switch (nbytes) | |
5114 | { | |
5115 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
5116 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
02442566 ST |
5117 | #ifdef TE_SOLARIS |
5118 | /* The Solaris linker does not allow R_SPARC_UA64 | |
5119 | relocations for 32-bit executables. */ | |
5120 | case 8: r = sparc_arch_size == 64 ? | |
5121 | BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break; | |
5122 | #else | |
0f2712ed | 5123 | case 8: r = BFD_RELOC_SPARC_UA64; break; |
02442566 | 5124 | #endif |
0f2712ed NC |
5125 | default: abort (); |
5126 | } | |
4ffadb11 | 5127 | } |
0f2712ed | 5128 | |
252b5132 | 5129 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
5130 | } |
5131 | ||
5132 | void | |
5a49b8ac | 5133 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
5134 | { |
5135 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
5136 | } | |
5137 | ||
5138 | int | |
1df69f4f | 5139 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b | 5140 | { |
74b4e47a TS |
5141 | char *q; |
5142 | int i; | |
364b6d8b JJ |
5143 | |
5144 | if (!regname[0]) | |
5145 | return -1; | |
5146 | ||
74b4e47a TS |
5147 | switch (regname[0]) |
5148 | { | |
5149 | case 'g': i = 0; break; | |
5150 | case 'o': i = 1; break; | |
5151 | case 'l': i = 2; break; | |
5152 | case 'i': i = 3; break; | |
5153 | default: i = -1; break; | |
5154 | } | |
5155 | if (i != -1) | |
364b6d8b JJ |
5156 | { |
5157 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
5158 | return -1; | |
74b4e47a | 5159 | return i * 8 + regname[1] - '0'; |
364b6d8b JJ |
5160 | } |
5161 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
5162 | return 14; | |
5163 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
5164 | return 30; | |
5165 | if (regname[0] == 'f' || regname[0] == 'r') | |
5166 | { | |
5167 | unsigned int regnum; | |
5168 | ||
5169 | regnum = strtoul (regname + 1, &q, 10); | |
74b4e47a | 5170 | if (q == NULL || *q) |
364b6d8b JJ |
5171 | return -1; |
5172 | if (regnum >= ((regname[0] == 'f' | |
5173 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
5174 | ? 64 : 32)) | |
5175 | return -1; | |
5176 | if (regname[0] == 'f') | |
5177 | { | |
5178 | regnum += 32; | |
5179 | if (regnum >= 64 && (regnum & 1)) | |
5180 | return -1; | |
5181 | } | |
5182 | return regnum; | |
5183 | } | |
5184 | return -1; | |
5185 | } | |
5186 | ||
5187 | void | |
5188 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
5189 | { | |
364b6d8b | 5190 | sparc_no_align_cons = 1; |
62ebcb5c | 5191 | emit_expr_with_reloc (exp, nbytes, "disp"); |
364b6d8b | 5192 | sparc_no_align_cons = 0; |
252b5132 | 5193 | } |