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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
63a7429b | 2 | Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
d77b99c9 | 82 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
83 | |
84 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
85 | ||
86 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 87 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
88 | back end. */ |
89 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
90 | |
91 | /* Flags for properties of the last instruction in a segment. */ | |
92 | #define FLAG_IS_A0_WRITER 0x1 | |
93 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
94 | ||
95 | ||
96 | /* We define a special segment names ".literal" to place literals | |
97 | into. The .fini and .init sections are special because they | |
98 | contain code that is moved together by the linker. We give them | |
99 | their own special .fini.literal and .init.literal sections. */ | |
100 | ||
101 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 102 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 103 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 104 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
105 | |
106 | ||
43cd72b9 | 107 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
108 | state of the literal collection pools. If lit_prefix is set, it is |
109 | used to determine the literal section names; otherwise, the literal | |
110 | sections are determined based on the current text section. The | |
111 | lit_seg and lit4_seg fields cache these literal sections, with the | |
112 | current_text_seg field used a tag to indicate whether the cached | |
113 | values are valid. */ | |
e0001a05 NC |
114 | |
115 | typedef struct lit_state_struct | |
116 | { | |
74869ac7 BW |
117 | char *lit_prefix; |
118 | segT current_text_seg; | |
e0001a05 | 119 | segT lit_seg; |
43cd72b9 | 120 | segT lit4_seg; |
e0001a05 NC |
121 | } lit_state; |
122 | ||
123 | static lit_state default_lit_sections; | |
124 | ||
125 | ||
74869ac7 BW |
126 | /* We keep a list of literal segments. The seg_list type is the node |
127 | for this list. The literal_head pointer is the head of the list, | |
128 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
129 | |
130 | typedef struct seg_list_struct | |
131 | { | |
132 | struct seg_list_struct *next; | |
133 | segT seg; | |
134 | } seg_list; | |
135 | ||
136 | static seg_list literal_head_h; | |
137 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
138 | |
139 | ||
82e7541d BW |
140 | /* Lists of symbols. We keep a list of symbols that label the current |
141 | instruction, so that we can adjust the symbols when inserting alignment | |
142 | for various instructions. We also keep a list of all the symbols on | |
143 | literals, so that we can fix up those symbols when the literals are | |
144 | later moved into the text sections. */ | |
145 | ||
146 | typedef struct sym_list_struct | |
147 | { | |
148 | struct sym_list_struct *next; | |
149 | symbolS *sym; | |
150 | } sym_list; | |
151 | ||
152 | static sym_list *insn_labels = NULL; | |
153 | static sym_list *free_insn_labels = NULL; | |
154 | static sym_list *saved_insn_labels = NULL; | |
155 | ||
156 | static sym_list *literal_syms; | |
157 | ||
158 | ||
43cd72b9 BW |
159 | /* Flags to determine whether to prefer const16 or l32r |
160 | if both options are available. */ | |
161 | int prefer_const16 = 0; | |
162 | int prefer_l32r = 0; | |
163 | ||
e0001a05 NC |
164 | /* Global flag to indicate when we are emitting literals. */ |
165 | int generating_literals = 0; | |
166 | ||
43cd72b9 BW |
167 | /* The following PROPERTY table definitions are copied from |
168 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
169 | ||
170 | /* Flags in the property tables to specify whether blocks of memory | |
171 | are literals, instructions, data, or unreachable. For | |
172 | instructions, blocks that begin loop targets and branch targets are | |
173 | designated. Blocks that do not allow density, instruction | |
174 | reordering or transformation are also specified. Finally, for | |
175 | branch targets, branch target alignment priority is included. | |
176 | Alignment of the next block is specified in the current block | |
177 | and the size of the current block does not include any fill required | |
178 | to align to the next block. */ | |
179 | ||
180 | #define XTENSA_PROP_LITERAL 0x00000001 | |
181 | #define XTENSA_PROP_INSN 0x00000002 | |
182 | #define XTENSA_PROP_DATA 0x00000004 | |
183 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
184 | /* Instruction only properties at beginning of code. */ | |
185 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
186 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
187 | /* Instruction only properties about code. */ | |
188 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
189 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
190 | /* Historically, NO_TRANSFORM was a property of instructions, |
191 | but it should apply to literals under certain circumstances. */ | |
192 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
193 | |
194 | /* Branch target alignment information. This transmits information | |
195 | to the linker optimization about the priority of aligning a | |
196 | particular block for branch target alignment: None, low priority, | |
197 | high priority, or required. These only need to be checked in | |
198 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
199 | Common usage is | |
200 | ||
201 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
202 | case XTENSA_PROP_BT_ALIGN_NONE: | |
203 | case XTENSA_PROP_BT_ALIGN_LOW: | |
204 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
205 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
206 | */ | |
207 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
208 | ||
209 | /* No branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
211 | /* Low priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
213 | /* High priority branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
215 | /* Required branch target alignment. */ | |
216 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
217 | ||
218 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
219 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
220 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
221 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
222 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
223 | ||
224 | ||
225 | /* Alignment is specified in the block BEFORE the one that needs | |
226 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
227 | get the required alignment specified as a power of 2. Use | |
228 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
229 | alignment. Be careful of side effects since the SET will evaluate | |
230 | flags twice. Also, note that the SIZE of a block in the property | |
231 | table does not include the alignment size, so the alignment fill | |
232 | must be calculated to determine if two blocks are contiguous. | |
233 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
234 | possible future implementation. */ | |
235 | ||
236 | #define XTENSA_PROP_ALIGN 0x00000800 | |
237 | ||
238 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
239 | ||
240 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
241 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
242 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
243 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
244 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
245 | ||
246 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
247 | ||
248 | ||
249 | /* Structure for saving instruction and alignment per-fragment data | |
250 | that will be written to the object file. This structure is | |
251 | equivalent to the actual data that will be written out to the file | |
252 | but is easier to use. We provide a conversion to file flags | |
253 | in frag_flags_to_number. */ | |
254 | ||
255 | typedef struct frag_flags_struct frag_flags; | |
256 | ||
257 | struct frag_flags_struct | |
258 | { | |
259 | /* is_literal should only be used after xtensa_move_literals. | |
260 | If you need to check if you are generating a literal fragment, | |
261 | then use the generating_literals global. */ | |
262 | ||
263 | unsigned is_literal : 1; | |
264 | unsigned is_insn : 1; | |
265 | unsigned is_data : 1; | |
266 | unsigned is_unreachable : 1; | |
267 | ||
99ded152 BW |
268 | /* is_specific_opcode implies no_transform. */ |
269 | unsigned is_no_transform : 1; | |
270 | ||
43cd72b9 BW |
271 | struct |
272 | { | |
273 | unsigned is_loop_target : 1; | |
274 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
275 | unsigned bt_align_priority : 2; | |
276 | ||
277 | unsigned is_no_density : 1; | |
278 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
279 | |
280 | unsigned is_no_reorder : 1; | |
281 | ||
282 | /* Uses absolute literal addressing for l32r. */ | |
283 | unsigned is_abslit : 1; | |
284 | } insn; | |
285 | unsigned is_align : 1; | |
286 | unsigned alignment : 5; | |
287 | }; | |
288 | ||
289 | ||
290 | /* Structure for saving information about a block of property data | |
291 | for frags that have the same flags. */ | |
292 | struct xtensa_block_info_struct | |
293 | { | |
294 | segT sec; | |
295 | bfd_vma offset; | |
296 | size_t size; | |
297 | frag_flags flags; | |
298 | struct xtensa_block_info_struct *next; | |
299 | }; | |
300 | ||
e0001a05 NC |
301 | |
302 | /* Structure for saving the current state before emitting literals. */ | |
303 | typedef struct emit_state_struct | |
304 | { | |
305 | const char *name; | |
306 | segT now_seg; | |
307 | subsegT now_subseg; | |
308 | int generating_literals; | |
309 | } emit_state; | |
310 | ||
311 | ||
43cd72b9 BW |
312 | /* Opcode placement information */ |
313 | ||
314 | typedef unsigned long long bitfield; | |
315 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
316 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
317 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
318 | ||
319 | #define MAX_FORMATS 32 | |
320 | ||
321 | typedef struct op_placement_info_struct | |
322 | { | |
323 | int num_formats; | |
324 | /* A number describing how restrictive the issue is for this | |
325 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 326 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 327 | only one format but many slots in that format. The most |
c138bc38 | 328 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
329 | format. */ |
330 | int issuef; | |
43cd72b9 | 331 | xtensa_format narrowest; |
43cd72b9 | 332 | char narrowest_size; |
b2d179be | 333 | char narrowest_slot; |
43cd72b9 BW |
334 | |
335 | /* formats is a bitfield with the Nth bit set | |
336 | if the opcode fits in the Nth xtensa_format. */ | |
337 | bitfield formats; | |
338 | ||
339 | /* slots[N]'s Mth bit is set if the op fits in the | |
340 | Mth slot of the Nth xtensa_format. */ | |
341 | bitfield slots[MAX_FORMATS]; | |
342 | ||
343 | /* A count of the number of slots in a given format | |
344 | an op can fit (i.e., the bitcount of the slot field above). */ | |
345 | char slots_in_format[MAX_FORMATS]; | |
346 | ||
347 | } op_placement_info, *op_placement_info_table; | |
348 | ||
349 | op_placement_info_table op_placement_table; | |
350 | ||
351 | ||
352 | /* Extra expression types. */ | |
353 | ||
354 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
355 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
356 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 357 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
43cd72b9 | 358 | |
bbdd25a8 BW |
359 | struct suffix_reloc_map |
360 | { | |
361 | char *suffix; | |
362 | int length; | |
363 | bfd_reloc_code_real_type reloc; | |
364 | unsigned char operator; | |
365 | }; | |
366 | ||
367 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
368 | ||
369 | static struct suffix_reloc_map suffix_relocs[] = | |
370 | { | |
371 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
372 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
373 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 374 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
bbdd25a8 BW |
375 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } |
376 | }; | |
377 | ||
43cd72b9 | 378 | |
e0001a05 NC |
379 | /* Directives. */ |
380 | ||
381 | typedef enum | |
382 | { | |
383 | directive_none = 0, | |
384 | directive_literal, | |
385 | directive_density, | |
43cd72b9 | 386 | directive_transform, |
e0001a05 NC |
387 | directive_freeregs, |
388 | directive_longcalls, | |
43cd72b9 BW |
389 | directive_literal_prefix, |
390 | directive_schedule, | |
391 | directive_absolute_literals, | |
392 | directive_last_directive | |
e0001a05 NC |
393 | } directiveE; |
394 | ||
395 | typedef struct | |
396 | { | |
397 | const char *name; | |
398 | bfd_boolean can_be_negated; | |
399 | } directive_infoS; | |
400 | ||
401 | const directive_infoS directive_info[] = | |
402 | { | |
43cd72b9 BW |
403 | { "none", FALSE }, |
404 | { "literal", FALSE }, | |
405 | { "density", TRUE }, | |
406 | { "transform", TRUE }, | |
407 | { "freeregs", FALSE }, | |
408 | { "longcalls", TRUE }, | |
409 | { "literal_prefix", FALSE }, | |
410 | { "schedule", TRUE }, | |
411 | { "absolute-literals", TRUE } | |
e0001a05 NC |
412 | }; |
413 | ||
414 | bfd_boolean directive_state[] = | |
415 | { | |
416 | FALSE, /* none */ | |
417 | FALSE, /* literal */ | |
43cd72b9 | 418 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
419 | FALSE, /* density */ |
420 | #else | |
421 | TRUE, /* density */ | |
422 | #endif | |
43cd72b9 | 423 | TRUE, /* transform */ |
e0001a05 NC |
424 | FALSE, /* freeregs */ |
425 | FALSE, /* longcalls */ | |
43cd72b9 | 426 | FALSE, /* literal_prefix */ |
2caa7ca0 | 427 | FALSE, /* schedule */ |
43cd72b9 BW |
428 | #if XSHAL_USE_ABSOLUTE_LITERALS |
429 | TRUE /* absolute_literals */ | |
430 | #else | |
431 | FALSE /* absolute_literals */ | |
432 | #endif | |
e0001a05 NC |
433 | }; |
434 | ||
e0001a05 NC |
435 | |
436 | /* Directive functions. */ | |
437 | ||
7fa3d080 BW |
438 | static void xtensa_begin_directive (int); |
439 | static void xtensa_end_directive (int); | |
74869ac7 | 440 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
441 | static void xtensa_literal_position (int); |
442 | static void xtensa_literal_pseudo (int); | |
443 | static void xtensa_frequency_pseudo (int); | |
444 | static void xtensa_elf_cons (int); | |
e0001a05 | 445 | |
7fa3d080 | 446 | /* Parsing and Idiom Translation. */ |
e0001a05 | 447 | |
7fa3d080 | 448 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 449 | |
e0001a05 NC |
450 | /* Various Other Internal Functions. */ |
451 | ||
84b08ed9 BW |
452 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
453 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
454 | static void xtensa_mark_literal_pool_location (void); |
455 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
456 | static fragS *get_literal_pool_location (segT); | |
457 | static void set_literal_pool_location (segT, fragS *); | |
458 | static void xtensa_set_frag_assembly_state (fragS *); | |
459 | static void finish_vinsn (vliw_insn *); | |
460 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 461 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
462 | |
463 | /* Alignment Functions. */ | |
464 | ||
d77b99c9 BW |
465 | static int get_text_align_power (unsigned); |
466 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 467 | static int branch_align_power (segT); |
e0001a05 NC |
468 | |
469 | /* Helpers for xtensa_relax_frag(). */ | |
470 | ||
7fa3d080 | 471 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 472 | |
b08b5071 | 473 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 474 | |
7fa3d080 BW |
475 | static unsigned get_last_insn_flags (segT, subsegT); |
476 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
477 | static float get_subseg_total_freq (segT, subsegT); |
478 | static float get_subseg_target_freq (segT, subsegT); | |
479 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
480 | |
481 | /* Segment list functions. */ | |
482 | ||
7fa3d080 BW |
483 | static void xtensa_move_literals (void); |
484 | static void xtensa_reorder_segments (void); | |
485 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
486 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
487 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
488 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 489 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 490 | |
e0001a05 | 491 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 492 | |
74869ac7 | 493 | extern asection *xtensa_get_property_section (asection *, const char *); |
e0001a05 | 494 | |
43cd72b9 BW |
495 | /* op_placement_info functions. */ |
496 | ||
7fa3d080 BW |
497 | static void init_op_placement_info_table (void); |
498 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
499 | static int xg_get_single_size (xtensa_opcode); | |
500 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 501 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 502 | |
e0001a05 | 503 | /* TInsn and IStack functions. */ |
43cd72b9 | 504 | |
7fa3d080 BW |
505 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
506 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
507 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
508 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
509 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
510 | static void tinsn_from_chars (TInsn *, char *, int); | |
511 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
512 | static int get_num_stack_text_bytes (IStack *); | |
513 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 514 | |
43cd72b9 BW |
515 | /* vliw_insn functions. */ |
516 | ||
7fa3d080 BW |
517 | static void xg_init_vinsn (vliw_insn *); |
518 | static void xg_clear_vinsn (vliw_insn *); | |
519 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
520 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 521 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
522 | (vliw_insn *, char *, fragS *, bfd_boolean); |
523 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 524 | |
e0001a05 | 525 | /* Expression Utilities. */ |
43cd72b9 | 526 | |
7fa3d080 BW |
527 | bfd_boolean expr_is_const (const expressionS *); |
528 | offsetT get_expr_const (const expressionS *); | |
529 | void set_expr_const (expressionS *, offsetT); | |
530 | bfd_boolean expr_is_register (const expressionS *); | |
531 | offsetT get_expr_register (const expressionS *); | |
532 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
533 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
534 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 535 | |
9456465c BW |
536 | /* Section renaming. */ |
537 | ||
7fa3d080 | 538 | static void build_section_rename (const char *); |
e0001a05 | 539 | |
e0001a05 NC |
540 | |
541 | /* ISA imported from bfd. */ | |
542 | extern xtensa_isa xtensa_default_isa; | |
543 | ||
544 | extern int target_big_endian; | |
545 | ||
546 | static xtensa_opcode xtensa_addi_opcode; | |
547 | static xtensa_opcode xtensa_addmi_opcode; | |
548 | static xtensa_opcode xtensa_call0_opcode; | |
549 | static xtensa_opcode xtensa_call4_opcode; | |
550 | static xtensa_opcode xtensa_call8_opcode; | |
551 | static xtensa_opcode xtensa_call12_opcode; | |
552 | static xtensa_opcode xtensa_callx0_opcode; | |
553 | static xtensa_opcode xtensa_callx4_opcode; | |
554 | static xtensa_opcode xtensa_callx8_opcode; | |
555 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 556 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 557 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 558 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
559 | static xtensa_opcode xtensa_movi_opcode; |
560 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 561 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 562 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 563 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
564 | static xtensa_opcode xtensa_loop_opcode; |
565 | static xtensa_opcode xtensa_loopnez_opcode; | |
566 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 567 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
568 | static xtensa_opcode xtensa_nop_n_opcode; |
569 | static xtensa_opcode xtensa_or_opcode; | |
570 | static xtensa_opcode xtensa_ret_opcode; | |
571 | static xtensa_opcode xtensa_ret_n_opcode; | |
572 | static xtensa_opcode xtensa_retw_opcode; | |
573 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 574 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
575 | static xtensa_opcode xtensa_waiti_opcode; |
576 | ||
577 | \f | |
578 | /* Command-line Options. */ | |
579 | ||
580 | bfd_boolean use_literal_section = TRUE; | |
581 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 582 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 583 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
584 | static bfd_boolean workaround_a0_b_retw = FALSE; |
585 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
586 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 587 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 588 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 589 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 590 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 591 | |
43cd72b9 BW |
592 | /* When workaround_short_loops is TRUE, all loops with early exits must |
593 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
594 | to the workaround_short_loop flag. In addition to the | |
595 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
596 | must have at least 3 instructions. */ | |
e0001a05 | 597 | |
43cd72b9 | 598 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 599 | |
7fa3d080 BW |
600 | |
601 | static void | |
602 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
603 | { | |
604 | if (earliest > latest) | |
605 | as_fatal (_("illegal range of target hardware versions")); | |
606 | ||
607 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
608 | if (earliest < 105000 || latest < 105000) | |
609 | { | |
610 | workaround_a0_b_retw |= TRUE; | |
611 | workaround_b_j_loop_end |= TRUE; | |
612 | workaround_short_loop |= TRUE; | |
613 | workaround_close_loop_end |= TRUE; | |
614 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 615 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
616 | } |
617 | } | |
618 | ||
619 | ||
e0001a05 NC |
620 | enum |
621 | { | |
622 | option_density = OPTION_MD_BASE, | |
623 | option_no_density, | |
624 | ||
625 | option_relax, | |
626 | option_no_relax, | |
627 | ||
43cd72b9 BW |
628 | option_link_relax, |
629 | option_no_link_relax, | |
630 | ||
e0001a05 NC |
631 | option_generics, |
632 | option_no_generics, | |
633 | ||
43cd72b9 BW |
634 | option_transform, |
635 | option_no_transform, | |
636 | ||
e0001a05 NC |
637 | option_text_section_literals, |
638 | option_no_text_section_literals, | |
639 | ||
43cd72b9 BW |
640 | option_absolute_literals, |
641 | option_no_absolute_literals, | |
642 | ||
e0001a05 NC |
643 | option_align_targets, |
644 | option_no_align_targets, | |
645 | ||
43cd72b9 | 646 | option_warn_unaligned_targets, |
e0001a05 NC |
647 | |
648 | option_longcalls, | |
649 | option_no_longcalls, | |
650 | ||
651 | option_workaround_a0_b_retw, | |
652 | option_no_workaround_a0_b_retw, | |
653 | ||
654 | option_workaround_b_j_loop_end, | |
655 | option_no_workaround_b_j_loop_end, | |
656 | ||
657 | option_workaround_short_loop, | |
658 | option_no_workaround_short_loop, | |
659 | ||
660 | option_workaround_all_short_loops, | |
661 | option_no_workaround_all_short_loops, | |
662 | ||
663 | option_workaround_close_loop_end, | |
664 | option_no_workaround_close_loop_end, | |
665 | ||
666 | option_no_workarounds, | |
667 | ||
e0001a05 | 668 | option_rename_section_name, |
e0001a05 | 669 | |
43cd72b9 BW |
670 | option_prefer_l32r, |
671 | option_prefer_const16, | |
672 | ||
673 | option_target_hardware | |
e0001a05 NC |
674 | }; |
675 | ||
676 | const char *md_shortopts = ""; | |
677 | ||
678 | struct option md_longopts[] = | |
679 | { | |
43cd72b9 BW |
680 | { "density", no_argument, NULL, option_density }, |
681 | { "no-density", no_argument, NULL, option_no_density }, | |
682 | ||
683 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
684 | to the "transform" option. */ | |
685 | { "relax", no_argument, NULL, option_relax }, | |
686 | { "no-relax", no_argument, NULL, option_no_relax }, | |
687 | { "generics", no_argument, NULL, option_generics }, | |
688 | { "no-generics", no_argument, NULL, option_no_generics }, | |
689 | ||
690 | { "transform", no_argument, NULL, option_transform }, | |
691 | { "no-transform", no_argument, NULL, option_no_transform }, | |
692 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
693 | { "no-text-section-literals", no_argument, NULL, | |
694 | option_no_text_section_literals }, | |
695 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
696 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
697 | /* This option was changed from -align-target to -target-align |
698 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 699 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
700 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
701 | { "warn-unaligned-targets", no_argument, NULL, | |
702 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
703 | { "longcalls", no_argument, NULL, option_longcalls }, |
704 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
705 | ||
706 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
707 | option_no_workaround_a0_b_retw }, | |
708 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 709 | |
43cd72b9 BW |
710 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
711 | option_no_workaround_b_j_loop_end }, | |
712 | { "workaround-b-j-loop-end", no_argument, NULL, | |
713 | option_workaround_b_j_loop_end }, | |
e0001a05 | 714 | |
43cd72b9 BW |
715 | { "no-workaround-short-loops", no_argument, NULL, |
716 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
717 | { "workaround-short-loops", no_argument, NULL, |
718 | option_workaround_short_loop }, | |
e0001a05 | 719 | |
43cd72b9 BW |
720 | { "no-workaround-all-short-loops", no_argument, NULL, |
721 | option_no_workaround_all_short_loops }, | |
722 | { "workaround-all-short-loop", no_argument, NULL, | |
723 | option_workaround_all_short_loops }, | |
724 | ||
725 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
726 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
727 | ||
728 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
729 | ||
730 | { "no-workaround-close-loop-end", no_argument, NULL, | |
731 | option_no_workaround_close_loop_end }, | |
732 | { "workaround-close-loop-end", no_argument, NULL, | |
733 | option_workaround_close_loop_end }, | |
e0001a05 | 734 | |
7fa3d080 | 735 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 736 | |
43cd72b9 BW |
737 | { "link-relax", no_argument, NULL, option_link_relax }, |
738 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
739 | ||
740 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
741 | ||
742 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
743 | }; |
744 | ||
745 | size_t md_longopts_size = sizeof md_longopts; | |
746 | ||
747 | ||
748 | int | |
7fa3d080 | 749 | md_parse_option (int c, char *arg) |
e0001a05 NC |
750 | { |
751 | switch (c) | |
752 | { | |
753 | case option_density: | |
43cd72b9 | 754 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
755 | return 1; |
756 | case option_no_density: | |
43cd72b9 | 757 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 758 | return 1; |
43cd72b9 BW |
759 | case option_link_relax: |
760 | linkrelax = 1; | |
e0001a05 | 761 | return 1; |
43cd72b9 BW |
762 | case option_no_link_relax: |
763 | linkrelax = 0; | |
e0001a05 | 764 | return 1; |
43cd72b9 BW |
765 | case option_generics: |
766 | as_warn (_("--generics is deprecated; use --transform instead")); | |
767 | return md_parse_option (option_transform, arg); | |
768 | case option_no_generics: | |
769 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
770 | return md_parse_option (option_no_transform, arg); | |
771 | case option_relax: | |
772 | as_warn (_("--relax is deprecated; use --transform instead")); | |
773 | return md_parse_option (option_transform, arg); | |
774 | case option_no_relax: | |
775 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
776 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
777 | case option_longcalls: |
778 | directive_state[directive_longcalls] = TRUE; | |
779 | return 1; | |
780 | case option_no_longcalls: | |
781 | directive_state[directive_longcalls] = FALSE; | |
782 | return 1; | |
783 | case option_text_section_literals: | |
784 | use_literal_section = FALSE; | |
785 | return 1; | |
786 | case option_no_text_section_literals: | |
787 | use_literal_section = TRUE; | |
788 | return 1; | |
43cd72b9 BW |
789 | case option_absolute_literals: |
790 | if (!absolute_literals_supported) | |
791 | { | |
792 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
793 | return 0; | |
794 | } | |
795 | directive_state[directive_absolute_literals] = TRUE; | |
796 | return 1; | |
797 | case option_no_absolute_literals: | |
798 | directive_state[directive_absolute_literals] = FALSE; | |
799 | return 1; | |
800 | ||
e0001a05 NC |
801 | case option_workaround_a0_b_retw: |
802 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
803 | return 1; |
804 | case option_no_workaround_a0_b_retw: | |
805 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
806 | return 1; |
807 | case option_workaround_b_j_loop_end: | |
808 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
809 | return 1; |
810 | case option_no_workaround_b_j_loop_end: | |
811 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
812 | return 1; |
813 | ||
814 | case option_workaround_short_loop: | |
815 | workaround_short_loop = TRUE; | |
e0001a05 NC |
816 | return 1; |
817 | case option_no_workaround_short_loop: | |
818 | workaround_short_loop = FALSE; | |
e0001a05 NC |
819 | return 1; |
820 | ||
821 | case option_workaround_all_short_loops: | |
822 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
823 | return 1; |
824 | case option_no_workaround_all_short_loops: | |
825 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
826 | return 1; |
827 | ||
828 | case option_workaround_close_loop_end: | |
829 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
830 | return 1; |
831 | case option_no_workaround_close_loop_end: | |
832 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
833 | return 1; |
834 | ||
835 | case option_no_workarounds: | |
836 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 837 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 838 | workaround_short_loop = FALSE; |
e0001a05 | 839 | workaround_all_short_loops = FALSE; |
e0001a05 | 840 | workaround_close_loop_end = FALSE; |
e0001a05 | 841 | return 1; |
43cd72b9 | 842 | |
e0001a05 NC |
843 | case option_align_targets: |
844 | align_targets = TRUE; | |
845 | return 1; | |
846 | case option_no_align_targets: | |
847 | align_targets = FALSE; | |
848 | return 1; | |
849 | ||
43cd72b9 BW |
850 | case option_warn_unaligned_targets: |
851 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
852 | return 1; |
853 | ||
e0001a05 NC |
854 | case option_rename_section_name: |
855 | build_section_rename (arg); | |
856 | return 1; | |
e0001a05 NC |
857 | |
858 | case 'Q': | |
859 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
860 | should be emitted or not. FIXME: Not implemented. */ | |
861 | return 1; | |
c138bc38 | 862 | |
43cd72b9 BW |
863 | case option_prefer_l32r: |
864 | if (prefer_const16) | |
865 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
866 | prefer_l32r = 1; | |
867 | return 1; | |
868 | ||
869 | case option_prefer_const16: | |
870 | if (prefer_l32r) | |
871 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
872 | prefer_const16 = 1; | |
873 | return 1; | |
874 | ||
c138bc38 | 875 | case option_target_hardware: |
43cd72b9 BW |
876 | { |
877 | int earliest, latest = 0; | |
878 | if (*arg == 0 || *arg == '-') | |
879 | as_fatal (_("invalid target hardware version")); | |
880 | ||
881 | earliest = strtol (arg, &arg, 0); | |
882 | ||
883 | if (*arg == 0) | |
884 | latest = earliest; | |
885 | else if (*arg == '-') | |
886 | { | |
887 | if (*++arg == 0) | |
888 | as_fatal (_("invalid target hardware version")); | |
889 | latest = strtol (arg, &arg, 0); | |
890 | } | |
891 | if (*arg != 0) | |
892 | as_fatal (_("invalid target hardware version")); | |
893 | ||
894 | xtensa_setup_hw_workarounds (earliest, latest); | |
895 | return 1; | |
896 | } | |
897 | ||
898 | case option_transform: | |
899 | /* This option has no affect other than to use the defaults, | |
900 | which are already set. */ | |
901 | return 1; | |
902 | ||
903 | case option_no_transform: | |
904 | /* This option turns off all transformations of any kind. | |
905 | However, because we want to preserve the state of other | |
906 | directives, we only change its own field. Thus, before | |
907 | you perform any transformation, always check if transform | |
908 | is available. If you use the functions we provide for this | |
909 | purpose, you will be ok. */ | |
910 | directive_state[directive_transform] = FALSE; | |
911 | return 1; | |
912 | ||
e0001a05 NC |
913 | default: |
914 | return 0; | |
915 | } | |
916 | } | |
917 | ||
918 | ||
919 | void | |
7fa3d080 | 920 | md_show_usage (FILE *stream) |
e0001a05 | 921 | { |
43cd72b9 BW |
922 | fputs ("\n\ |
923 | Xtensa options:\n\ | |
9456465c BW |
924 | --[no-]text-section-literals\n\ |
925 | [Do not] put literals in the text section\n\ | |
926 | --[no-]absolute-literals\n\ | |
927 | [Do not] default to use non-PC-relative literals\n\ | |
928 | --[no-]target-align [Do not] try to align branch targets\n\ | |
929 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
930 | --[no-]transform [Do not] transform instructions\n\ | |
931 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
932 | } |
933 | ||
7fa3d080 BW |
934 | \f |
935 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
936 | |
937 | static void | |
7fa3d080 | 938 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 939 | { |
7fa3d080 | 940 | sym_list *l; |
43cd72b9 | 941 | |
7fa3d080 BW |
942 | if (!free_insn_labels) |
943 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
944 | else | |
43cd72b9 | 945 | { |
7fa3d080 BW |
946 | l = free_insn_labels; |
947 | free_insn_labels = l->next; | |
948 | } | |
949 | ||
950 | l->sym = sym; | |
951 | l->next = insn_labels; | |
952 | insn_labels = l; | |
953 | } | |
954 | ||
955 | ||
956 | static void | |
957 | xtensa_clear_insn_labels (void) | |
958 | { | |
959 | sym_list **pl; | |
960 | ||
961 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
962 | ; | |
963 | *pl = insn_labels; | |
964 | insn_labels = NULL; | |
965 | } | |
966 | ||
967 | ||
7fa3d080 | 968 | static void |
c3ea6048 | 969 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
970 | { |
971 | sym_list *lit; | |
972 | ||
973 | for (lit = insn_labels; lit; lit = lit->next) | |
974 | { | |
975 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
976 | S_SET_VALUE (lit_sym, new_offset); |
977 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
978 | } |
979 | } | |
980 | ||
e0001a05 NC |
981 | \f |
982 | /* Directive data and functions. */ | |
983 | ||
984 | typedef struct state_stackS_struct | |
985 | { | |
986 | directiveE directive; | |
987 | bfd_boolean negated; | |
988 | bfd_boolean old_state; | |
989 | const char *file; | |
990 | unsigned int line; | |
991 | const void *datum; | |
992 | struct state_stackS_struct *prev; | |
993 | } state_stackS; | |
994 | ||
995 | state_stackS *directive_state_stack; | |
996 | ||
997 | const pseudo_typeS md_pseudo_table[] = | |
998 | { | |
43cd72b9 BW |
999 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1000 | { "literal_position", xtensa_literal_position, 0 }, | |
1001 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1002 | { "long", xtensa_elf_cons, 4 }, | |
1003 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1004 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1005 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1006 | { "2byte", xtensa_elf_cons, 2 }, |
43cd72b9 BW |
1007 | { "begin", xtensa_begin_directive, 0 }, |
1008 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1009 | { "literal", xtensa_literal_pseudo, 0 }, |
1010 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1011 | { NULL, 0, 0 }, | |
e0001a05 NC |
1012 | }; |
1013 | ||
1014 | ||
7fa3d080 BW |
1015 | static bfd_boolean |
1016 | use_transform (void) | |
e0001a05 | 1017 | { |
43cd72b9 BW |
1018 | /* After md_end, you should be checking frag by frag, rather |
1019 | than state directives. */ | |
1020 | assert (!past_xtensa_end); | |
1021 | return directive_state[directive_transform]; | |
e0001a05 NC |
1022 | } |
1023 | ||
1024 | ||
7fa3d080 BW |
1025 | static bfd_boolean |
1026 | do_align_targets (void) | |
e0001a05 | 1027 | { |
7b1cc377 BW |
1028 | /* Do not use this function after md_end; just look at align_targets |
1029 | instead. There is no target-align directive, so alignment is either | |
1030 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1031 | assert (!past_xtensa_end); |
1032 | return align_targets && use_transform (); | |
e0001a05 NC |
1033 | } |
1034 | ||
1035 | ||
1036 | static void | |
7fa3d080 | 1037 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1038 | { |
1039 | char *file; | |
1040 | unsigned int line; | |
1041 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1042 | ||
1043 | as_where (&file, &line); | |
1044 | ||
1045 | stack->directive = directive; | |
1046 | stack->negated = negated; | |
1047 | stack->old_state = directive_state[directive]; | |
1048 | stack->file = file; | |
1049 | stack->line = line; | |
1050 | stack->datum = datum; | |
1051 | stack->prev = directive_state_stack; | |
1052 | directive_state_stack = stack; | |
1053 | ||
1054 | directive_state[directive] = !negated; | |
1055 | } | |
1056 | ||
7fa3d080 | 1057 | |
e0001a05 | 1058 | static void |
7fa3d080 BW |
1059 | directive_pop (directiveE *directive, |
1060 | bfd_boolean *negated, | |
1061 | const char **file, | |
1062 | unsigned int *line, | |
1063 | const void **datum) | |
e0001a05 NC |
1064 | { |
1065 | state_stackS *top = directive_state_stack; | |
1066 | ||
1067 | if (!directive_state_stack) | |
1068 | { | |
1069 | as_bad (_("unmatched end directive")); | |
1070 | *directive = directive_none; | |
1071 | return; | |
1072 | } | |
1073 | ||
1074 | directive_state[directive_state_stack->directive] = top->old_state; | |
1075 | *directive = top->directive; | |
1076 | *negated = top->negated; | |
1077 | *file = top->file; | |
1078 | *line = top->line; | |
1079 | *datum = top->datum; | |
1080 | directive_state_stack = top->prev; | |
1081 | free (top); | |
1082 | } | |
1083 | ||
1084 | ||
1085 | static void | |
7fa3d080 | 1086 | directive_balance (void) |
e0001a05 NC |
1087 | { |
1088 | while (directive_state_stack) | |
1089 | { | |
1090 | directiveE directive; | |
1091 | bfd_boolean negated; | |
1092 | const char *file; | |
1093 | unsigned int line; | |
1094 | const void *datum; | |
1095 | ||
1096 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1097 | as_warn_where ((char *) file, line, | |
1098 | _(".begin directive with no matching .end directive")); | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | ||
1103 | static bfd_boolean | |
7fa3d080 | 1104 | inside_directive (directiveE dir) |
e0001a05 NC |
1105 | { |
1106 | state_stackS *top = directive_state_stack; | |
1107 | ||
1108 | while (top && top->directive != dir) | |
1109 | top = top->prev; | |
1110 | ||
1111 | return (top != NULL); | |
1112 | } | |
1113 | ||
1114 | ||
1115 | static void | |
7fa3d080 | 1116 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1117 | { |
1118 | int len; | |
1119 | unsigned i; | |
43cd72b9 | 1120 | char *directive_string; |
e0001a05 NC |
1121 | |
1122 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1123 | *negated = FALSE; | |
1124 | else | |
1125 | { | |
1126 | *negated = TRUE; | |
1127 | input_line_pointer += 3; | |
1128 | } | |
1129 | ||
1130 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1131 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1132 | ||
1133 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1134 | equivalent to .begin [no-]transform. We should remove it when | |
1135 | we stop accepting those options. */ | |
c138bc38 | 1136 | |
43cd72b9 BW |
1137 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1138 | { | |
1139 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1140 | directive_string = "transform"; | |
1141 | } | |
1142 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1143 | { | |
1144 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1145 | directive_string = "transform"; | |
c138bc38 | 1146 | } |
43cd72b9 BW |
1147 | else |
1148 | directive_string = input_line_pointer; | |
e0001a05 NC |
1149 | |
1150 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1151 | { | |
43cd72b9 | 1152 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1153 | { |
1154 | input_line_pointer += len; | |
1155 | *directive = (directiveE) i; | |
1156 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1157 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1158 | directive_info[i].name); |
1159 | return; | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | as_bad (_("unknown directive")); | |
1164 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1165 | } | |
1166 | ||
1167 | ||
1168 | static void | |
7fa3d080 | 1169 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1170 | { |
1171 | directiveE directive; | |
1172 | bfd_boolean negated; | |
1173 | emit_state *state; | |
e0001a05 NC |
1174 | lit_state *ls; |
1175 | ||
1176 | get_directive (&directive, &negated); | |
1177 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1178 | { | |
1179 | discard_rest_of_line (); | |
1180 | return; | |
1181 | } | |
1182 | ||
43cd72b9 BW |
1183 | if (cur_vinsn.inside_bundle) |
1184 | as_bad (_("directives are not valid inside bundles")); | |
1185 | ||
e0001a05 NC |
1186 | switch (directive) |
1187 | { | |
1188 | case directive_literal: | |
82e7541d BW |
1189 | if (!inside_directive (directive_literal)) |
1190 | { | |
1191 | /* Previous labels go with whatever follows this directive, not with | |
1192 | the literal, so save them now. */ | |
1193 | saved_insn_labels = insn_labels; | |
1194 | insn_labels = NULL; | |
1195 | } | |
43cd72b9 | 1196 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1197 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1198 | xtensa_switch_to_literal_fragment (state); | |
1199 | directive_push (directive_literal, negated, state); | |
1200 | break; | |
1201 | ||
1202 | case directive_literal_prefix: | |
c138bc38 | 1203 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1204 | might produce a literal. */ |
1205 | md_flush_pending_output (); | |
e0001a05 NC |
1206 | /* Check to see if the current fragment is a literal |
1207 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1208 | if (generating_literals) |
e0001a05 NC |
1209 | { |
1210 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1211 | return; | |
1212 | } | |
1213 | ||
1214 | /* Allocate the literal state for this section and push | |
1215 | onto the directive stack. */ | |
1216 | ls = xmalloc (sizeof (lit_state)); | |
1217 | assert (ls); | |
1218 | ||
1219 | *ls = default_lit_sections; | |
e0001a05 NC |
1220 | directive_push (directive_literal_prefix, negated, ls); |
1221 | ||
e0001a05 | 1222 | /* Process the new prefix. */ |
74869ac7 | 1223 | xtensa_literal_prefix (); |
e0001a05 NC |
1224 | break; |
1225 | ||
1226 | case directive_freeregs: | |
1227 | /* This information is currently unused, but we'll accept the statement | |
1228 | and just discard the rest of the line. This won't check the syntax, | |
1229 | but it will accept every correct freeregs directive. */ | |
1230 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1231 | directive_push (directive_freeregs, negated, 0); | |
1232 | break; | |
1233 | ||
43cd72b9 BW |
1234 | case directive_schedule: |
1235 | md_flush_pending_output (); | |
1236 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1237 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1238 | directive_push (directive_schedule, negated, 0); | |
1239 | xtensa_set_frag_assembly_state (frag_now); | |
1240 | break; | |
1241 | ||
e0001a05 | 1242 | case directive_density: |
43cd72b9 BW |
1243 | as_warn (_(".begin [no-]density is ignored")); |
1244 | break; | |
1245 | ||
1246 | case directive_absolute_literals: | |
1247 | md_flush_pending_output (); | |
1248 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1249 | { |
43cd72b9 | 1250 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1251 | break; |
1252 | } | |
43cd72b9 BW |
1253 | xtensa_set_frag_assembly_state (frag_now); |
1254 | directive_push (directive, negated, 0); | |
1255 | break; | |
e0001a05 NC |
1256 | |
1257 | default: | |
43cd72b9 BW |
1258 | md_flush_pending_output (); |
1259 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1260 | directive_push (directive, negated, 0); |
1261 | break; | |
1262 | } | |
1263 | ||
1264 | demand_empty_rest_of_line (); | |
1265 | } | |
1266 | ||
1267 | ||
1268 | static void | |
7fa3d080 | 1269 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1270 | { |
1271 | directiveE begin_directive, end_directive; | |
1272 | bfd_boolean begin_negated, end_negated; | |
1273 | const char *file; | |
1274 | unsigned int line; | |
1275 | emit_state *state; | |
43cd72b9 | 1276 | emit_state **state_ptr; |
e0001a05 NC |
1277 | lit_state *s; |
1278 | ||
43cd72b9 BW |
1279 | if (cur_vinsn.inside_bundle) |
1280 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1281 | |
e0001a05 | 1282 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1283 | |
1284 | md_flush_pending_output (); | |
1285 | ||
1286 | switch (end_directive) | |
e0001a05 | 1287 | { |
43cd72b9 | 1288 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1289 | discard_rest_of_line (); |
1290 | return; | |
e0001a05 | 1291 | |
43cd72b9 BW |
1292 | case directive_density: |
1293 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1294 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1295 | break; |
1296 | ||
1297 | case directive_absolute_literals: | |
1298 | if (!absolute_literals_supported && !end_negated) | |
1299 | { | |
1300 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1301 | demand_empty_rest_of_line (); | |
1302 | return; | |
1303 | } | |
1304 | break; | |
1305 | ||
1306 | default: | |
1307 | break; | |
e0001a05 NC |
1308 | } |
1309 | ||
43cd72b9 | 1310 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1311 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1312 | (const void **) state_ptr); |
e0001a05 NC |
1313 | |
1314 | if (begin_directive != directive_none) | |
1315 | { | |
1316 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1317 | { | |
1318 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1319 | begin_negated ? "no-" : "", | |
1320 | directive_info[begin_directive].name, file, line); | |
1321 | } | |
1322 | else | |
1323 | { | |
1324 | switch (end_directive) | |
1325 | { | |
1326 | case directive_literal: | |
1327 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1328 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1329 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1330 | free (state); |
82e7541d BW |
1331 | if (!inside_directive (directive_literal)) |
1332 | { | |
1333 | /* Restore the list of current labels. */ | |
1334 | xtensa_clear_insn_labels (); | |
1335 | insn_labels = saved_insn_labels; | |
1336 | } | |
e0001a05 NC |
1337 | break; |
1338 | ||
e0001a05 NC |
1339 | case directive_literal_prefix: |
1340 | /* Restore the default collection sections from saved state. */ | |
1341 | s = (lit_state *) state; | |
1342 | assert (s); | |
e8247da7 | 1343 | default_lit_sections = *s; |
e0001a05 | 1344 | |
74869ac7 BW |
1345 | /* Free the state storage. */ |
1346 | free (s->lit_prefix); | |
e0001a05 NC |
1347 | free (s); |
1348 | break; | |
1349 | ||
43cd72b9 BW |
1350 | case directive_schedule: |
1351 | case directive_freeregs: | |
1352 | break; | |
1353 | ||
e0001a05 | 1354 | default: |
43cd72b9 | 1355 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1356 | break; |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | demand_empty_rest_of_line (); | |
1362 | } | |
1363 | ||
1364 | ||
1365 | /* Place an aligned literal fragment at the current location. */ | |
1366 | ||
1367 | static void | |
7fa3d080 | 1368 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1369 | { |
43cd72b9 BW |
1370 | md_flush_pending_output (); |
1371 | ||
e0001a05 NC |
1372 | if (inside_directive (directive_literal)) |
1373 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1374 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1375 | |
1376 | demand_empty_rest_of_line (); | |
82e7541d | 1377 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1378 | } |
1379 | ||
1380 | ||
43cd72b9 | 1381 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1382 | |
1383 | static void | |
7fa3d080 | 1384 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1385 | { |
1386 | emit_state state; | |
1745fcba | 1387 | char *p, *base_name; |
e0001a05 | 1388 | char c; |
e0001a05 NC |
1389 | segT dest_seg; |
1390 | ||
82e7541d BW |
1391 | if (inside_directive (directive_literal)) |
1392 | { | |
1393 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1394 | ignore_rest_of_line (); | |
1395 | return; | |
1396 | } | |
1397 | ||
43cd72b9 BW |
1398 | md_flush_pending_output (); |
1399 | ||
82e7541d BW |
1400 | /* Previous labels go with whatever follows this directive, not with |
1401 | the literal, so save them now. */ | |
1402 | saved_insn_labels = insn_labels; | |
1403 | insn_labels = NULL; | |
1404 | ||
e0001a05 NC |
1405 | /* If we are using text-section literals, then this is the right value... */ |
1406 | dest_seg = now_seg; | |
1407 | ||
1408 | base_name = input_line_pointer; | |
1409 | ||
1410 | xtensa_switch_to_literal_fragment (&state); | |
1411 | ||
43cd72b9 | 1412 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1413 | need to put them in the section we just switched to. */ |
43cd72b9 | 1414 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1415 | dest_seg = now_seg; |
1416 | ||
43cd72b9 BW |
1417 | /* All literals are aligned to four-byte boundaries. */ |
1418 | frag_align (2, 0, 0); | |
1419 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1420 | |
1421 | c = get_symbol_end (); | |
1422 | /* Just after name is now '\0'. */ | |
1423 | p = input_line_pointer; | |
1424 | *p = c; | |
1425 | SKIP_WHITESPACE (); | |
1426 | ||
1427 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1428 | { | |
1429 | as_bad (_("expected comma or colon after symbol name; " | |
1430 | "rest of line ignored")); | |
1431 | ignore_rest_of_line (); | |
1432 | xtensa_restore_emit_state (&state); | |
1433 | return; | |
1434 | } | |
1435 | *p = 0; | |
1436 | ||
e0001a05 | 1437 | colon (base_name); |
e0001a05 | 1438 | |
e0001a05 | 1439 | *p = c; |
43cd72b9 | 1440 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1441 | |
43cd72b9 | 1442 | xtensa_elf_cons (4); |
e0001a05 NC |
1443 | |
1444 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1445 | |
1446 | /* Restore the list of current labels. */ | |
1447 | xtensa_clear_insn_labels (); | |
1448 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1449 | } |
1450 | ||
1451 | ||
1452 | static void | |
74869ac7 | 1453 | xtensa_literal_prefix (void) |
e0001a05 | 1454 | { |
74869ac7 BW |
1455 | char *name; |
1456 | int len; | |
1457 | ||
1458 | /* Parse the new prefix from the input_line_pointer. */ | |
1459 | SKIP_WHITESPACE (); | |
1460 | len = strspn (input_line_pointer, | |
1461 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1462 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1463 | |
1464 | /* Get a null-terminated copy of the name. */ | |
1465 | name = xmalloc (len + 1); | |
1466 | assert (name); | |
74869ac7 | 1467 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1468 | name[len] = 0; |
1469 | ||
74869ac7 BW |
1470 | /* Skip the name in the input line. */ |
1471 | input_line_pointer += len; | |
43cd72b9 | 1472 | |
74869ac7 | 1473 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1474 | |
74869ac7 | 1475 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1476 | default_lit_sections.lit_seg = NULL; |
1477 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1478 | } |
1479 | ||
1480 | ||
1481 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1482 | ||
1483 | static void | |
7fa3d080 | 1484 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1485 | { |
1486 | float fall_through_f, target_f; | |
43cd72b9 BW |
1487 | |
1488 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1489 | if (fall_through_f < 0) | |
1490 | { | |
1491 | as_bad (_("fall through frequency must be greater than 0")); | |
1492 | ignore_rest_of_line (); | |
1493 | return; | |
1494 | } | |
1495 | ||
1496 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1497 | if (target_f < 0) | |
1498 | { | |
1499 | as_bad (_("branch target frequency must be greater than 0")); | |
1500 | ignore_rest_of_line (); | |
1501 | return; | |
1502 | } | |
1503 | ||
b08b5071 | 1504 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1505 | |
1506 | demand_empty_rest_of_line (); | |
1507 | } | |
1508 | ||
1509 | ||
1510 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1511 | Clobbers input_line_pointer, checks end-of-line. */ | |
1512 | ||
1513 | static void | |
7fa3d080 | 1514 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1515 | { |
1516 | expressionS exp; | |
1517 | bfd_reloc_code_real_type reloc; | |
1518 | ||
1519 | md_flush_pending_output (); | |
1520 | ||
1521 | if (cur_vinsn.inside_bundle) | |
1522 | as_bad (_("directives are not valid inside bundles")); | |
1523 | ||
1524 | if (is_it_end_of_statement ()) | |
1525 | { | |
1526 | demand_empty_rest_of_line (); | |
1527 | return; | |
1528 | } | |
1529 | ||
1530 | do | |
1531 | { | |
1532 | expression (&exp); | |
1533 | if (exp.X_op == O_symbol | |
1534 | && *input_line_pointer == '@' | |
1535 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1536 | != BFD_RELOC_NONE)) | |
1537 | { | |
1538 | reloc_howto_type *reloc_howto = | |
1539 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1540 | ||
1541 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1542 | as_bad (_("unsupported relocation")); | |
1543 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1544 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1545 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1546 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1547 | as_bad (_("opcode-specific %s relocation used outside " | |
1548 | "an instruction"), reloc_howto->name); | |
1549 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1550 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1551 | reloc_howto->name, nbytes); | |
1552 | else | |
1553 | { | |
1554 | char *p = frag_more ((int) nbytes); | |
1555 | xtensa_set_frag_assembly_state (frag_now); | |
1556 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1557 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1558 | } |
1559 | } | |
1560 | else | |
1561 | emit_expr (&exp, (unsigned int) nbytes); | |
1562 | } | |
1563 | while (*input_line_pointer++ == ','); | |
1564 | ||
1565 | input_line_pointer--; /* Put terminator back into stream. */ | |
1566 | demand_empty_rest_of_line (); | |
1567 | } | |
1568 | ||
7fa3d080 BW |
1569 | \f |
1570 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1571 | |
1572 | /* Parse @plt, etc. and return the desired relocation. */ | |
1573 | static bfd_reloc_code_real_type | |
7fa3d080 | 1574 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1575 | { |
43cd72b9 BW |
1576 | char ident[20]; |
1577 | char *str = *str_p; | |
1578 | char *str2; | |
1579 | int ch; | |
1580 | int len; | |
bbdd25a8 | 1581 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1582 | |
1583 | if (*str++ != '@') | |
1584 | return BFD_RELOC_NONE; | |
1585 | ||
1586 | for (ch = *str, str2 = ident; | |
1587 | (str2 < ident + sizeof (ident) - 1 | |
1588 | && (ISALNUM (ch) || ch == '@')); | |
1589 | ch = *++str) | |
1590 | { | |
1591 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1592 | } | |
1593 | ||
1594 | *str2 = '\0'; | |
1595 | len = str2 - ident; | |
1596 | ||
1597 | ch = ident[0]; | |
bbdd25a8 BW |
1598 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1599 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1600 | && len == ptr->length |
bbdd25a8 | 1601 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1602 | { |
1603 | /* Now check for "identifier@suffix+constant". */ | |
1604 | if (*str == '-' || *str == '+') | |
1605 | { | |
1606 | char *orig_line = input_line_pointer; | |
1607 | expressionS new_exp; | |
1608 | ||
1609 | input_line_pointer = str; | |
1610 | expression (&new_exp); | |
1611 | if (new_exp.X_op == O_constant) | |
1612 | { | |
1613 | exp_p->X_add_number += new_exp.X_add_number; | |
1614 | str = input_line_pointer; | |
1615 | } | |
1616 | ||
1617 | if (&input_line_pointer != str_p) | |
1618 | input_line_pointer = orig_line; | |
1619 | } | |
1620 | ||
1621 | *str_p = str; | |
1622 | return ptr->reloc; | |
1623 | } | |
1624 | ||
1625 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1626 | } |
1627 | ||
e0001a05 | 1628 | |
bbdd25a8 BW |
1629 | /* Find the matching operator type. */ |
1630 | static unsigned char | |
1631 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1632 | { | |
1633 | struct suffix_reloc_map *sfx; | |
1634 | unsigned char operator = (unsigned char) -1; | |
1635 | ||
1636 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1637 | { | |
1638 | if (sfx->reloc == reloc) | |
1639 | { | |
1640 | operator = sfx->operator; | |
1641 | break; | |
1642 | } | |
1643 | } | |
1644 | assert (operator != (unsigned char) -1); | |
1645 | return operator; | |
1646 | } | |
1647 | ||
1648 | ||
1649 | /* Find the matching reloc type. */ | |
1650 | static bfd_reloc_code_real_type | |
1651 | map_operator_to_reloc (unsigned char operator) | |
1652 | { | |
1653 | struct suffix_reloc_map *sfx; | |
1654 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1655 | ||
1656 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1657 | { | |
1658 | if (sfx->operator == operator) | |
1659 | { | |
1660 | reloc = sfx->reloc; | |
1661 | break; | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | if (reloc == BFD_RELOC_UNUSED) | |
1666 | return BFD_RELOC_32; | |
1667 | ||
1668 | return reloc; | |
1669 | } | |
1670 | ||
1671 | ||
e0001a05 | 1672 | static const char * |
7fa3d080 | 1673 | expression_end (const char *name) |
e0001a05 NC |
1674 | { |
1675 | while (1) | |
1676 | { | |
1677 | switch (*name) | |
1678 | { | |
43cd72b9 | 1679 | case '}': |
e0001a05 NC |
1680 | case ';': |
1681 | case '\0': | |
1682 | case ',': | |
43cd72b9 | 1683 | case ':': |
e0001a05 NC |
1684 | return name; |
1685 | case ' ': | |
1686 | case '\t': | |
1687 | ++name; | |
1688 | continue; | |
1689 | default: | |
1690 | return 0; | |
1691 | } | |
1692 | } | |
1693 | } | |
1694 | ||
1695 | ||
1696 | #define ERROR_REG_NUM ((unsigned) -1) | |
1697 | ||
1698 | static unsigned | |
7fa3d080 | 1699 | tc_get_register (const char *prefix) |
e0001a05 NC |
1700 | { |
1701 | unsigned reg; | |
1702 | const char *next_expr; | |
1703 | const char *old_line_pointer; | |
1704 | ||
1705 | SKIP_WHITESPACE (); | |
1706 | old_line_pointer = input_line_pointer; | |
1707 | ||
1708 | if (*input_line_pointer == '$') | |
1709 | ++input_line_pointer; | |
1710 | ||
1711 | /* Accept "sp" as a synonym for "a1". */ | |
1712 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1713 | && expression_end (input_line_pointer + 2)) | |
1714 | { | |
1715 | input_line_pointer += 2; | |
1716 | return 1; /* AR[1] */ | |
1717 | } | |
1718 | ||
1719 | while (*input_line_pointer++ == *prefix++) | |
1720 | ; | |
1721 | --input_line_pointer; | |
1722 | --prefix; | |
1723 | ||
1724 | if (*prefix) | |
1725 | { | |
1726 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1727 | return ERROR_REG_NUM; | |
1728 | } | |
1729 | ||
1730 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1731 | { | |
1732 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1733 | return ERROR_REG_NUM; | |
1734 | } | |
1735 | ||
1736 | reg = 0; | |
1737 | ||
1738 | while (ISDIGIT ((int) *input_line_pointer)) | |
1739 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1740 | ||
1741 | if (!(next_expr = expression_end (input_line_pointer))) | |
1742 | { | |
1743 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1744 | return ERROR_REG_NUM; | |
1745 | } | |
1746 | ||
1747 | input_line_pointer = (char *) next_expr; | |
1748 | ||
1749 | return reg; | |
1750 | } | |
1751 | ||
1752 | ||
e0001a05 | 1753 | static void |
7fa3d080 | 1754 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1755 | { |
43cd72b9 | 1756 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1757 | |
43cd72b9 BW |
1758 | /* Check if this is an immediate operand. */ |
1759 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1760 | { |
43cd72b9 | 1761 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1762 | segT t = expression (tok); |
43cd72b9 BW |
1763 | if (t == absolute_section |
1764 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1765 | { |
1766 | assert (tok->X_op == O_constant); | |
1767 | tok->X_op = O_symbol; | |
1768 | tok->X_add_symbol = &abs_symbol; | |
1769 | } | |
43cd72b9 BW |
1770 | |
1771 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1772 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1773 | != BFD_RELOC_NONE)) | |
e0001a05 | 1774 | { |
1bbb5f21 | 1775 | switch (reloc) |
43cd72b9 | 1776 | { |
1bbb5f21 BW |
1777 | case BFD_RELOC_LO16: |
1778 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1779 | { |
43cd72b9 | 1780 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1781 | return; |
1bbb5f21 BW |
1782 | } |
1783 | break; | |
1784 | case BFD_RELOC_HI16: | |
1785 | if (tok->X_op == O_constant) | |
1786 | { | |
43cd72b9 | 1787 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1788 | return; |
bbdd25a8 | 1789 | } |
1bbb5f21 BW |
1790 | break; |
1791 | case BFD_RELOC_UNUSED: | |
1792 | as_bad (_("unsupported relocation")); | |
1793 | return; | |
1794 | case BFD_RELOC_32_PCREL: | |
1795 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1796 | return; | |
1797 | default: | |
1798 | break; | |
43cd72b9 | 1799 | } |
bbdd25a8 | 1800 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1801 | } |
e0001a05 NC |
1802 | } |
1803 | else | |
1804 | { | |
43cd72b9 BW |
1805 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1806 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1807 | |
1808 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1809 | { | |
1810 | uint32 buf = reg; | |
43cd72b9 | 1811 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1812 | as_bad (_("register number out of range")); |
1813 | } | |
1814 | ||
1815 | tok->X_op = O_register; | |
1816 | tok->X_add_symbol = 0; | |
1817 | tok->X_add_number = reg; | |
1818 | } | |
1819 | } | |
1820 | ||
1821 | ||
1822 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1823 | ||
1824 | static int | |
7fa3d080 | 1825 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1826 | { |
1827 | char *old_input_line_pointer; | |
1828 | bfd_boolean saw_comma = FALSE; | |
1829 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1830 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1831 | int num_args = 0; |
1832 | char *arg_end, *arg; | |
1833 | int arg_len; | |
43cd72b9 BW |
1834 | |
1835 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1836 | old_input_line_pointer = input_line_pointer; |
1837 | input_line_pointer = str; | |
1838 | ||
1839 | while (*input_line_pointer) | |
1840 | { | |
1841 | SKIP_WHITESPACE (); | |
1842 | switch (*input_line_pointer) | |
1843 | { | |
1844 | case '\0': | |
43cd72b9 | 1845 | case '}': |
e0001a05 NC |
1846 | goto fini; |
1847 | ||
43cd72b9 BW |
1848 | case ':': |
1849 | input_line_pointer++; | |
1850 | if (saw_comma || saw_colon || !saw_arg) | |
1851 | goto err; | |
1852 | saw_colon = TRUE; | |
1853 | break; | |
1854 | ||
e0001a05 NC |
1855 | case ',': |
1856 | input_line_pointer++; | |
43cd72b9 | 1857 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1858 | goto err; |
1859 | saw_comma = TRUE; | |
1860 | break; | |
1861 | ||
1862 | default: | |
43cd72b9 | 1863 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1864 | goto err; |
1865 | ||
1866 | arg_end = input_line_pointer + 1; | |
1867 | while (!expression_end (arg_end)) | |
1868 | arg_end += 1; | |
43cd72b9 | 1869 | |
e0001a05 | 1870 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1871 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1872 | args[num_args] = arg; |
1873 | ||
43cd72b9 BW |
1874 | if (saw_colon) |
1875 | *arg++ = ':'; | |
e0001a05 NC |
1876 | strncpy (arg, input_line_pointer, arg_len); |
1877 | arg[arg_len] = '\0'; | |
43cd72b9 | 1878 | |
e0001a05 NC |
1879 | input_line_pointer = arg_end; |
1880 | num_args += 1; | |
c138bc38 | 1881 | saw_comma = FALSE; |
43cd72b9 | 1882 | saw_colon = FALSE; |
c138bc38 | 1883 | saw_arg = TRUE; |
e0001a05 NC |
1884 | break; |
1885 | } | |
1886 | } | |
1887 | ||
1888 | fini: | |
43cd72b9 | 1889 | if (saw_comma || saw_colon) |
e0001a05 NC |
1890 | goto err; |
1891 | input_line_pointer = old_input_line_pointer; | |
1892 | return num_args; | |
1893 | ||
1894 | err: | |
43cd72b9 BW |
1895 | if (saw_comma) |
1896 | as_bad (_("extra comma")); | |
1897 | else if (saw_colon) | |
1898 | as_bad (_("extra colon")); | |
1899 | else if (!saw_arg) | |
c138bc38 | 1900 | as_bad (_("missing argument")); |
43cd72b9 BW |
1901 | else |
1902 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1903 | input_line_pointer = old_input_line_pointer; |
1904 | return -1; | |
1905 | } | |
1906 | ||
1907 | ||
43cd72b9 | 1908 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1909 | |
1910 | static bfd_boolean | |
7fa3d080 | 1911 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1912 | { |
43cd72b9 | 1913 | expressionS *tok, *last_tok; |
e0001a05 NC |
1914 | xtensa_opcode opcode = insn->opcode; |
1915 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1916 | xtensa_isa isa = xtensa_default_isa; |
1917 | int n, num_regs = 0; | |
e0001a05 | 1918 | int opcode_operand_count; |
43cd72b9 BW |
1919 | int opnd_cnt, last_opnd_cnt; |
1920 | unsigned int next_reg = 0; | |
e0001a05 NC |
1921 | char *old_input_line_pointer; |
1922 | ||
1923 | if (insn->insn_type == ITYPE_LITERAL) | |
1924 | opcode_operand_count = 1; | |
1925 | else | |
43cd72b9 | 1926 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1927 | |
43cd72b9 | 1928 | tok = insn->tok; |
e0001a05 NC |
1929 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1930 | ||
1931 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1932 | old_input_line_pointer = input_line_pointer; |
1933 | ||
1934 | last_tok = 0; | |
1935 | last_opnd_cnt = -1; | |
1936 | opnd_cnt = 0; | |
1937 | ||
1938 | /* Skip invisible operands. */ | |
1939 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1940 | { | |
1941 | opnd_cnt += 1; | |
1942 | tok++; | |
1943 | } | |
e0001a05 NC |
1944 | |
1945 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1946 | { |
e0001a05 | 1947 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1948 | if (*input_line_pointer == ':') |
1949 | { | |
1950 | xtensa_regfile opnd_rf; | |
1951 | input_line_pointer++; | |
1952 | if (num_regs == 0) | |
1953 | goto err; | |
1954 | assert (opnd_cnt > 0); | |
1955 | num_regs--; | |
1956 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1957 | if (next_reg | |
1958 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1959 | as_warn (_("incorrect register number, ignoring")); | |
1960 | next_reg++; | |
1961 | } | |
1962 | else | |
1963 | { | |
1964 | if (opnd_cnt >= opcode_operand_count) | |
1965 | { | |
1966 | as_warn (_("too many arguments")); | |
1967 | goto err; | |
1968 | } | |
1969 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1970 | ||
1971 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1972 | next_reg = tok->X_add_number + 1; | |
1973 | ||
1974 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1975 | goto err; | |
1976 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1977 | { | |
1978 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1979 | /* minus 1 because we are seeing one right now */ | |
1980 | } | |
1981 | else | |
1982 | num_regs = 0; | |
e0001a05 | 1983 | |
43cd72b9 BW |
1984 | last_tok = tok; |
1985 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 1986 | |
43cd72b9 BW |
1987 | do |
1988 | { | |
1989 | opnd_cnt += 1; | |
1990 | tok++; | |
1991 | } | |
1992 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
1993 | } | |
1994 | } | |
e0001a05 | 1995 | |
43cd72b9 BW |
1996 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
1997 | goto err; | |
e0001a05 NC |
1998 | |
1999 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2000 | had_error = FALSE; |
e0001a05 NC |
2001 | |
2002 | err: | |
43cd72b9 | 2003 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2004 | return had_error; |
2005 | } | |
2006 | ||
2007 | ||
43cd72b9 | 2008 | static int |
7fa3d080 | 2009 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2010 | { |
2011 | xtensa_isa isa = xtensa_default_isa; | |
2012 | static xtensa_insnbuf slotbuf = NULL; | |
2013 | xtensa_format fmt; | |
2014 | xtensa_opcode opc = insn->opcode; | |
2015 | int slot, opnd, fmt_found; | |
2016 | unsigned val; | |
2017 | ||
2018 | if (!slotbuf) | |
2019 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2020 | ||
2021 | /* Find format/slot where this can be encoded. */ | |
2022 | fmt_found = 0; | |
2023 | slot = 0; | |
2024 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2025 | { | |
2026 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2027 | { | |
2028 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2029 | { | |
2030 | fmt_found = 1; | |
2031 | break; | |
2032 | } | |
2033 | } | |
2034 | if (fmt_found) break; | |
2035 | } | |
2036 | ||
2037 | if (!fmt_found) | |
2038 | { | |
2039 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2040 | return -1; | |
2041 | } | |
2042 | ||
2043 | /* First encode all the visible operands | |
2044 | (to deal with shared field operands). */ | |
2045 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2046 | { | |
2047 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2048 | && (insn->tok[opnd].X_op == O_register | |
2049 | || insn->tok[opnd].X_op == O_constant)) | |
2050 | { | |
2051 | val = insn->tok[opnd].X_add_number; | |
2052 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2053 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2054 | } | |
2055 | } | |
2056 | ||
2057 | /* Then pull out the values for the invisible ones. */ | |
2058 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2059 | { | |
2060 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2061 | { | |
2062 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2063 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2064 | insn->tok[opnd].X_add_number = val; | |
2065 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2066 | insn->tok[opnd].X_op = O_register; | |
2067 | else | |
2068 | insn->tok[opnd].X_op = O_constant; | |
2069 | } | |
2070 | } | |
2071 | ||
2072 | return 0; | |
2073 | } | |
2074 | ||
2075 | ||
e0001a05 | 2076 | static void |
7fa3d080 | 2077 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2078 | { |
2079 | char *cnt_arg, *new_arg; | |
2080 | cnt_arg = *cnt_argp; | |
2081 | ||
2082 | /* replace the argument with "31-(argument)" */ | |
2083 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2084 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2085 | ||
2086 | free (cnt_arg); | |
2087 | *cnt_argp = new_arg; | |
2088 | } | |
2089 | ||
2090 | ||
2091 | /* If "arg" is a constant expression, return non-zero with the value | |
2092 | in *valp. */ | |
2093 | ||
2094 | static int | |
7fa3d080 | 2095 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2096 | { |
2097 | expressionS exp; | |
2098 | char *save_ptr = input_line_pointer; | |
2099 | ||
2100 | input_line_pointer = arg; | |
2101 | expression (&exp); | |
2102 | input_line_pointer = save_ptr; | |
2103 | ||
2104 | if (exp.X_op == O_constant) | |
2105 | { | |
2106 | *valp = exp.X_add_number; | |
2107 | return 1; | |
2108 | } | |
2109 | ||
2110 | return 0; | |
2111 | } | |
2112 | ||
2113 | ||
2114 | static void | |
7fa3d080 | 2115 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2116 | { |
2117 | free (*popname); | |
2118 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2119 | strcpy (*popname, newop); | |
2120 | } | |
2121 | ||
2122 | ||
2123 | static int | |
7fa3d080 BW |
2124 | xg_check_num_args (int *pnum_args, |
2125 | int expected_num, | |
2126 | char *opname, | |
2127 | char **arg_strings) | |
e0001a05 NC |
2128 | { |
2129 | int num_args = *pnum_args; | |
2130 | ||
43cd72b9 | 2131 | if (num_args < expected_num) |
e0001a05 NC |
2132 | { |
2133 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2134 | num_args, opname, expected_num); | |
2135 | return -1; | |
2136 | } | |
2137 | ||
2138 | if (num_args > expected_num) | |
2139 | { | |
2140 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2141 | num_args, opname, expected_num); | |
2142 | while (num_args-- > expected_num) | |
2143 | { | |
2144 | free (arg_strings[num_args]); | |
2145 | arg_strings[num_args] = 0; | |
2146 | } | |
2147 | *pnum_args = expected_num; | |
2148 | return -1; | |
2149 | } | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | ||
43cd72b9 BW |
2155 | /* If the register is not specified as part of the opcode, |
2156 | then get it from the operand and move it to the opcode. */ | |
2157 | ||
e0001a05 | 2158 | static int |
7fa3d080 | 2159 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2160 | { |
43cd72b9 BW |
2161 | xtensa_isa isa = xtensa_default_isa; |
2162 | xtensa_sysreg sr; | |
e0001a05 | 2163 | char *opname, *new_opname; |
43cd72b9 BW |
2164 | const char *sr_name; |
2165 | int is_user, is_write; | |
e0001a05 NC |
2166 | |
2167 | opname = *popname; | |
2168 | if (*opname == '_') | |
80ca4e2c | 2169 | opname += 1; |
43cd72b9 BW |
2170 | is_user = (opname[1] == 'u'); |
2171 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2172 | |
43cd72b9 | 2173 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2174 | |
43cd72b9 BW |
2175 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2176 | return -1; | |
e0001a05 | 2177 | |
43cd72b9 BW |
2178 | /* Check if the argument is a symbolic register name. */ |
2179 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2180 | /* Handle WSR to "INTSET" as a special case. */ | |
2181 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2182 | && !strcasecmp (arg_strings[1], "intset")) | |
2183 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2184 | if (sr == XTENSA_UNDEFINED | |
2185 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2186 | { | |
2187 | /* Maybe it's a register number.... */ | |
2188 | offsetT val; | |
e0001a05 NC |
2189 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2190 | { | |
43cd72b9 BW |
2191 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2192 | arg_strings[1], opname); | |
e0001a05 NC |
2193 | return -1; |
2194 | } | |
43cd72b9 BW |
2195 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2196 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2197 | { |
43cd72b9 | 2198 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2199 | (long) val, opname); |
e0001a05 NC |
2200 | return -1; |
2201 | } | |
43cd72b9 | 2202 | } |
e0001a05 | 2203 | |
43cd72b9 BW |
2204 | /* Remove the last argument, which is now part of the opcode. */ |
2205 | free (arg_strings[1]); | |
2206 | arg_strings[1] = 0; | |
2207 | *pnum_args = 1; | |
2208 | ||
2209 | /* Translate the opcode. */ | |
2210 | sr_name = xtensa_sysreg_name (isa, sr); | |
2211 | /* Another special case for "WSR.INTSET".... */ | |
2212 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2213 | sr_name = "intset"; | |
2214 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2215 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2216 | free (*popname); |
2217 | *popname = new_opname; | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | ||
2223 | static int | |
7fa3d080 | 2224 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2225 | { |
2226 | xtensa_isa isa = xtensa_default_isa; | |
2227 | xtensa_sysreg sr; | |
2228 | char *opname, *new_opname; | |
2229 | const char *sr_name; | |
2230 | bfd_boolean has_underbar = FALSE; | |
2231 | ||
2232 | opname = *popname; | |
2233 | if (opname[0] == '_') | |
2234 | { | |
2235 | has_underbar = TRUE; | |
2236 | opname += 1; | |
2237 | } | |
2238 | ||
2239 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2240 | if (sr != XTENSA_UNDEFINED) | |
2241 | { | |
2242 | /* The new default name ("nnn") is different from the old default | |
2243 | name ("URnnn"). The old default is handled below, and we don't | |
2244 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2245 | default. */ | |
2246 | static char namebuf[10]; | |
2247 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2248 | if (strcmp (namebuf, opname + 1) == 0) | |
2249 | return 0; | |
2250 | } | |
2251 | else | |
2252 | { | |
2253 | offsetT val; | |
2254 | char *end; | |
2255 | ||
2256 | /* Only continue if the reg name is "URnnn". */ | |
2257 | if (opname[1] != 'u' || opname[2] != 'r') | |
2258 | return 0; | |
2259 | val = strtoul (opname + 3, &end, 10); | |
2260 | if (*end != '\0') | |
2261 | return 0; | |
2262 | ||
2263 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2264 | if (sr == XTENSA_UNDEFINED) | |
2265 | { | |
2266 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2267 | (long) val, opname); |
43cd72b9 BW |
2268 | return -1; |
2269 | } | |
2270 | } | |
2271 | ||
2272 | /* Translate the opcode. */ | |
2273 | sr_name = xtensa_sysreg_name (isa, sr); | |
2274 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2275 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2276 | opname[0], sr_name); | |
2277 | free (*popname); | |
2278 | *popname = new_opname; | |
2279 | ||
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | ||
2284 | static int | |
7fa3d080 BW |
2285 | xtensa_translate_zero_immed (char *old_op, |
2286 | char *new_op, | |
2287 | char **popname, | |
2288 | int *pnum_args, | |
2289 | char **arg_strings) | |
43cd72b9 BW |
2290 | { |
2291 | char *opname; | |
2292 | offsetT val; | |
2293 | ||
2294 | opname = *popname; | |
2295 | assert (opname[0] != '_'); | |
2296 | ||
2297 | if (strcmp (opname, old_op) != 0) | |
2298 | return 0; | |
e0001a05 | 2299 | |
43cd72b9 BW |
2300 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2301 | return -1; | |
2302 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2303 | { | |
2304 | xg_replace_opname (popname, new_op); | |
2305 | free (arg_strings[1]); | |
2306 | arg_strings[1] = arg_strings[2]; | |
2307 | arg_strings[2] = 0; | |
2308 | *pnum_args = 2; | |
e0001a05 NC |
2309 | } |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | ||
2315 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2316 | Returns non-zero if an error was found. */ | |
2317 | ||
2318 | static int | |
7fa3d080 | 2319 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2320 | { |
2321 | char *opname = *popname; | |
2322 | bfd_boolean has_underbar = FALSE; | |
2323 | ||
2324 | if (*opname == '_') | |
2325 | { | |
2326 | has_underbar = TRUE; | |
2327 | opname += 1; | |
2328 | } | |
2329 | ||
2330 | if (strcmp (opname, "mov") == 0) | |
2331 | { | |
43cd72b9 | 2332 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2333 | xg_replace_opname (popname, "mov.n"); |
2334 | else | |
2335 | { | |
2336 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2337 | return -1; | |
2338 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2339 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2340 | strcpy (arg_strings[2], arg_strings[1]); | |
2341 | *pnum_args = 3; | |
2342 | } | |
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | if (strcmp (opname, "bbsi.l") == 0) | |
2347 | { | |
2348 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2349 | return -1; | |
2350 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2351 | if (target_big_endian) | |
2352 | xg_reverse_shift_count (&arg_strings[1]); | |
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | if (strcmp (opname, "bbci.l") == 0) | |
2357 | { | |
2358 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2359 | return -1; | |
2360 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2361 | if (target_big_endian) | |
2362 | xg_reverse_shift_count (&arg_strings[1]); | |
2363 | return 0; | |
2364 | } | |
2365 | ||
eb6d9dce BW |
2366 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2367 | are handled elsewhere. Real NOP instructions are always available | |
2368 | in configurations with FLIX, so this should never be an issue but | |
2369 | check for it anyway. */ | |
2370 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2371 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2372 | { |
43cd72b9 | 2373 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2374 | xg_replace_opname (popname, "nop.n"); |
2375 | else | |
2376 | { | |
2377 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2378 | return -1; | |
2379 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2380 | arg_strings[0] = (char *) xmalloc (3); | |
2381 | arg_strings[1] = (char *) xmalloc (3); | |
2382 | arg_strings[2] = (char *) xmalloc (3); | |
2383 | strcpy (arg_strings[0], "a1"); | |
2384 | strcpy (arg_strings[1], "a1"); | |
2385 | strcpy (arg_strings[2], "a1"); | |
2386 | *pnum_args = 3; | |
2387 | } | |
2388 | return 0; | |
2389 | } | |
2390 | ||
43cd72b9 BW |
2391 | /* Recognize [RW]UR and [RWX]SR. */ |
2392 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2393 | && (opname[1] == 'u' || opname[1] == 's')) | |
2394 | || (opname[0] == 'x' && opname[1] == 's')) | |
2395 | && opname[2] == 'r' | |
2396 | && opname[3] == '\0') | |
e0001a05 NC |
2397 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2398 | ||
43cd72b9 BW |
2399 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2400 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2401 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2402 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2403 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2404 | |
43cd72b9 BW |
2405 | /* Relax branches that don't allow comparisons against an immediate value |
2406 | of zero to the corresponding branches with implicit zero immediates. */ | |
2407 | if (!has_underbar && use_transform ()) | |
2408 | { | |
2409 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2410 | pnum_args, arg_strings)) | |
2411 | return -1; | |
e0001a05 | 2412 | |
43cd72b9 BW |
2413 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2414 | pnum_args, arg_strings)) | |
2415 | return -1; | |
e0001a05 | 2416 | |
43cd72b9 BW |
2417 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2418 | pnum_args, arg_strings)) | |
2419 | return -1; | |
e0001a05 | 2420 | |
43cd72b9 BW |
2421 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2422 | pnum_args, arg_strings)) | |
2423 | return -1; | |
2424 | } | |
e0001a05 | 2425 | |
43cd72b9 BW |
2426 | return 0; |
2427 | } | |
e0001a05 | 2428 | |
43cd72b9 BW |
2429 | \f |
2430 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2431 | |
43cd72b9 BW |
2432 | /* Currently the assembler only allows us to use a single target per |
2433 | fragment. Because of this, only one operand for a given | |
2434 | instruction may be symbolic. If there is a PC-relative operand, | |
2435 | the last one is chosen. Otherwise, the result is the number of the | |
2436 | last immediate operand, and if there are none of those, we fail and | |
2437 | return -1. */ | |
e0001a05 | 2438 | |
7fa3d080 BW |
2439 | static int |
2440 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2441 | { |
2442 | int last_immed = -1; | |
2443 | int noperands, opi; | |
e0001a05 | 2444 | |
43cd72b9 BW |
2445 | if (opcode == XTENSA_UNDEFINED) |
2446 | return -1; | |
e0001a05 | 2447 | |
43cd72b9 BW |
2448 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2449 | for (opi = noperands - 1; opi >= 0; opi--) | |
2450 | { | |
2451 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2452 | continue; | |
2453 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2454 | return opi; | |
2455 | if (last_immed == -1 | |
2456 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2457 | last_immed = opi; | |
e0001a05 | 2458 | } |
43cd72b9 | 2459 | return last_immed; |
e0001a05 NC |
2460 | } |
2461 | ||
e0001a05 | 2462 | |
43cd72b9 | 2463 | static xtensa_opcode |
7fa3d080 | 2464 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2465 | { |
43cd72b9 BW |
2466 | static xtensa_insnbuf insnbuf = NULL; |
2467 | static xtensa_insnbuf slotbuf = NULL; | |
2468 | xtensa_isa isa = xtensa_default_isa; | |
2469 | xtensa_format fmt; | |
2470 | ||
2471 | if (!insnbuf) | |
e0001a05 | 2472 | { |
43cd72b9 BW |
2473 | insnbuf = xtensa_insnbuf_alloc (isa); |
2474 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2475 | } |
e0001a05 | 2476 | |
d77b99c9 | 2477 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2478 | fmt = xtensa_format_decode (isa, insnbuf); |
2479 | if (fmt == XTENSA_UNDEFINED) | |
2480 | return XTENSA_UNDEFINED; | |
e0001a05 | 2481 | |
43cd72b9 BW |
2482 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2483 | return XTENSA_UNDEFINED; | |
e0001a05 | 2484 | |
43cd72b9 BW |
2485 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2486 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2487 | } |
2488 | ||
2489 | ||
43cd72b9 | 2490 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2491 | |
43cd72b9 | 2492 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2493 | |
7fa3d080 BW |
2494 | static void |
2495 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2496 | { |
2497 | int num_opcodes, num_operands; | |
2498 | xtensa_opcode opcode; | |
2499 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2500 | |
43cd72b9 BW |
2501 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2502 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2503 | { |
43cd72b9 BW |
2504 | int opn; |
2505 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2506 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2507 | for (opn = 0; opn < num_operands; opn++) | |
2508 | { | |
2509 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2510 | continue; | |
2511 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2512 | { | |
2513 | xtensa_regfile opnd_rf = | |
2514 | xtensa_operand_regfile (isa, opcode, opn); | |
2515 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2516 | } | |
2517 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2518 | fputs ("[lLr] ", stderr); | |
2519 | else | |
2520 | fputs ("i ", stderr); | |
2521 | } | |
2522 | fprintf (stderr, "\n"); | |
e0001a05 | 2523 | } |
e0001a05 NC |
2524 | } |
2525 | ||
2526 | ||
43cd72b9 | 2527 | static void |
7fa3d080 | 2528 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2529 | { |
e0001a05 | 2530 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2531 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2532 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2533 | int op; | |
e0001a05 | 2534 | |
43cd72b9 | 2535 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2536 | |
43cd72b9 BW |
2537 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2538 | { | |
2539 | xtensa_opcode opcode; | |
2540 | const char *opname; | |
2541 | int operands; | |
2542 | ||
2543 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2544 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2545 | opname = xtensa_opcode_name (isa, opcode); | |
2546 | ||
2547 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2548 | fprintf (stderr, " operands = "); | |
2549 | for (operands = 0; | |
2550 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2551 | operands++) | |
2552 | { | |
2553 | unsigned int val; | |
2554 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2555 | continue; | |
2556 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2557 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2558 | fprintf (stderr, "%d ", val); | |
2559 | } | |
2560 | fprintf (stderr, "\n"); | |
2561 | } | |
2562 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2563 | } |
2564 | ||
43cd72b9 BW |
2565 | #endif /* TENSILICA_DEBUG */ |
2566 | ||
e0001a05 NC |
2567 | |
2568 | static bfd_boolean | |
7fa3d080 | 2569 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2570 | { |
43cd72b9 BW |
2571 | xtensa_isa isa = xtensa_default_isa; |
2572 | int n, num_operands; | |
e0001a05 | 2573 | |
64b607e6 | 2574 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2575 | return FALSE; |
2576 | ||
43cd72b9 BW |
2577 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2578 | for (n = 0; n < num_operands; n++) | |
2579 | { | |
2580 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2581 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2582 | return TRUE; | |
2583 | } | |
2584 | return FALSE; | |
e0001a05 NC |
2585 | } |
2586 | ||
2587 | ||
43cd72b9 BW |
2588 | /* Convert from BFD relocation type code to slot and operand number. |
2589 | Returns non-zero on failure. */ | |
e0001a05 | 2590 | |
43cd72b9 | 2591 | static int |
7fa3d080 | 2592 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2593 | { |
43cd72b9 BW |
2594 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2595 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2596 | { |
43cd72b9 BW |
2597 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2598 | *is_alt = FALSE; | |
e0001a05 | 2599 | } |
43cd72b9 BW |
2600 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2601 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2602 | { |
43cd72b9 BW |
2603 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2604 | *is_alt = TRUE; | |
e0001a05 | 2605 | } |
43cd72b9 BW |
2606 | else |
2607 | return -1; | |
2608 | ||
2609 | return 0; | |
e0001a05 NC |
2610 | } |
2611 | ||
2612 | ||
43cd72b9 BW |
2613 | /* Convert from slot number to BFD relocation type code for the |
2614 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2615 | failure. */ | |
e0001a05 | 2616 | |
43cd72b9 | 2617 | static bfd_reloc_code_real_type |
7fa3d080 | 2618 | encode_reloc (int slot) |
e0001a05 | 2619 | { |
43cd72b9 BW |
2620 | if (slot < 0 || slot > 14) |
2621 | return BFD_RELOC_NONE; | |
2622 | ||
2623 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2624 | } |
2625 | ||
2626 | ||
43cd72b9 BW |
2627 | /* Convert from slot numbers to BFD relocation type code for the |
2628 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2629 | |
43cd72b9 | 2630 | static bfd_reloc_code_real_type |
7fa3d080 | 2631 | encode_alt_reloc (int slot) |
e0001a05 | 2632 | { |
43cd72b9 BW |
2633 | if (slot < 0 || slot > 14) |
2634 | return BFD_RELOC_NONE; | |
2635 | ||
2636 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2637 | } |
2638 | ||
2639 | ||
2640 | static void | |
7fa3d080 BW |
2641 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2642 | xtensa_format fmt, | |
2643 | int slot, | |
2644 | xtensa_opcode opcode, | |
2645 | int operand, | |
2646 | uint32 value, | |
2647 | const char *file, | |
2648 | unsigned int line) | |
e0001a05 | 2649 | { |
e0001a05 NC |
2650 | uint32 valbuf = value; |
2651 | ||
43cd72b9 | 2652 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2653 | { |
43cd72b9 BW |
2654 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2655 | == 1) | |
2656 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2657 | _("operand %d of '%s' has out of range value '%u'"), |
2658 | operand + 1, | |
2659 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2660 | value); | |
43cd72b9 BW |
2661 | else |
2662 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2663 | _("operand %d of '%s' has invalid value '%u'"), |
2664 | operand + 1, | |
2665 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2666 | value); | |
43cd72b9 | 2667 | return; |
e0001a05 NC |
2668 | } |
2669 | ||
43cd72b9 BW |
2670 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2671 | slotbuf, valbuf); | |
e0001a05 NC |
2672 | } |
2673 | ||
2674 | ||
2675 | static uint32 | |
7fa3d080 BW |
2676 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2677 | xtensa_format fmt, | |
2678 | int slot, | |
2679 | xtensa_opcode opcode, | |
2680 | int opnum) | |
e0001a05 | 2681 | { |
43cd72b9 BW |
2682 | uint32 val = 0; |
2683 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2684 | fmt, slot, slotbuf, &val); | |
2685 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2686 | return val; | |
e0001a05 NC |
2687 | } |
2688 | ||
e0001a05 | 2689 | \f |
7fa3d080 | 2690 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2691 | |
7fa3d080 BW |
2692 | /* The routine xg_instruction_matches_option_term must return TRUE |
2693 | when a given option term is true. The meaning of all of the option | |
2694 | terms is given interpretation by this function. This is needed when | |
2695 | an option depends on the state of a directive, but there are no such | |
2696 | options in use right now. */ | |
e0001a05 | 2697 | |
7fa3d080 BW |
2698 | static bfd_boolean |
2699 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2700 | const ReqOrOption *option) | |
e0001a05 | 2701 | { |
7fa3d080 BW |
2702 | if (strcmp (option->option_name, "realnop") == 0 |
2703 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2704 | { | |
2705 | /* These conditions were evaluated statically when building the | |
2706 | relaxation table. There's no need to reevaluate them now. */ | |
2707 | return TRUE; | |
2708 | } | |
2709 | else | |
2710 | { | |
2711 | as_fatal (_("internal error: unknown option name '%s'"), | |
2712 | option->option_name); | |
2713 | } | |
e0001a05 NC |
2714 | } |
2715 | ||
2716 | ||
7fa3d080 BW |
2717 | static bfd_boolean |
2718 | xg_instruction_matches_or_options (TInsn *insn, | |
2719 | const ReqOrOptionList *or_option) | |
e0001a05 | 2720 | { |
7fa3d080 BW |
2721 | const ReqOrOption *option; |
2722 | /* Must match each of the AND terms. */ | |
2723 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2724 | { |
7fa3d080 BW |
2725 | if (xg_instruction_matches_option_term (insn, option)) |
2726 | return TRUE; | |
e0001a05 | 2727 | } |
7fa3d080 | 2728 | return FALSE; |
e0001a05 NC |
2729 | } |
2730 | ||
2731 | ||
7fa3d080 BW |
2732 | static bfd_boolean |
2733 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2734 | { |
7fa3d080 BW |
2735 | const ReqOption *req_options; |
2736 | /* Must match each of the AND terms. */ | |
2737 | for (req_options = options; | |
2738 | req_options != NULL; | |
2739 | req_options = req_options->next) | |
e0001a05 | 2740 | { |
7fa3d080 BW |
2741 | /* Must match one of the OR clauses. */ |
2742 | if (!xg_instruction_matches_or_options (insn, | |
2743 | req_options->or_option_terms)) | |
2744 | return FALSE; | |
e0001a05 | 2745 | } |
7fa3d080 | 2746 | return TRUE; |
e0001a05 NC |
2747 | } |
2748 | ||
2749 | ||
7fa3d080 | 2750 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2751 | |
7fa3d080 BW |
2752 | static bfd_boolean |
2753 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2754 | { |
7fa3d080 | 2755 | PreconditionList *condition_l; |
e0001a05 | 2756 | |
7fa3d080 BW |
2757 | if (rule->opcode != insn->opcode) |
2758 | return FALSE; | |
e0001a05 | 2759 | |
7fa3d080 BW |
2760 | for (condition_l = rule->conditions; |
2761 | condition_l != NULL; | |
2762 | condition_l = condition_l->next) | |
e0001a05 | 2763 | { |
7fa3d080 BW |
2764 | expressionS *exp1; |
2765 | expressionS *exp2; | |
2766 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2767 | |
7fa3d080 | 2768 | switch (cond->typ) |
e0001a05 | 2769 | { |
7fa3d080 BW |
2770 | case OP_CONSTANT: |
2771 | /* The expression must be the constant. */ | |
2772 | assert (cond->op_num < insn->ntok); | |
2773 | exp1 = &insn->tok[cond->op_num]; | |
2774 | if (expr_is_const (exp1)) | |
2775 | { | |
2776 | switch (cond->cmp) | |
2777 | { | |
2778 | case OP_EQUAL: | |
2779 | if (get_expr_const (exp1) != cond->op_data) | |
2780 | return FALSE; | |
2781 | break; | |
2782 | case OP_NOTEQUAL: | |
2783 | if (get_expr_const (exp1) == cond->op_data) | |
2784 | return FALSE; | |
2785 | break; | |
2786 | default: | |
2787 | return FALSE; | |
2788 | } | |
2789 | } | |
2790 | else if (expr_is_register (exp1)) | |
2791 | { | |
2792 | switch (cond->cmp) | |
2793 | { | |
2794 | case OP_EQUAL: | |
2795 | if (get_expr_register (exp1) != cond->op_data) | |
2796 | return FALSE; | |
2797 | break; | |
2798 | case OP_NOTEQUAL: | |
2799 | if (get_expr_register (exp1) == cond->op_data) | |
2800 | return FALSE; | |
2801 | break; | |
2802 | default: | |
2803 | return FALSE; | |
2804 | } | |
2805 | } | |
2806 | else | |
2807 | return FALSE; | |
2808 | break; | |
2809 | ||
2810 | case OP_OPERAND: | |
2811 | assert (cond->op_num < insn->ntok); | |
2812 | assert (cond->op_data < insn->ntok); | |
2813 | exp1 = &insn->tok[cond->op_num]; | |
2814 | exp2 = &insn->tok[cond->op_data]; | |
2815 | ||
2816 | switch (cond->cmp) | |
2817 | { | |
2818 | case OP_EQUAL: | |
2819 | if (!expr_is_equal (exp1, exp2)) | |
2820 | return FALSE; | |
2821 | break; | |
2822 | case OP_NOTEQUAL: | |
2823 | if (expr_is_equal (exp1, exp2)) | |
2824 | return FALSE; | |
2825 | break; | |
2826 | } | |
2827 | break; | |
2828 | ||
2829 | case OP_LITERAL: | |
2830 | case OP_LABEL: | |
2831 | default: | |
2832 | return FALSE; | |
2833 | } | |
2834 | } | |
2835 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2836 | return FALSE; | |
2837 | ||
2838 | return TRUE; | |
2839 | } | |
2840 | ||
2841 | ||
2842 | static int | |
2843 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2844 | { | |
2845 | bfd_boolean a_greater = FALSE; | |
2846 | bfd_boolean b_greater = FALSE; | |
2847 | ||
2848 | ReqOptionList *l_a = a->options; | |
2849 | ReqOptionList *l_b = b->options; | |
2850 | ||
2851 | /* We only care if they both are the same except for | |
2852 | a const16 vs. an l32r. */ | |
2853 | ||
2854 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2855 | { | |
2856 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2857 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2858 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2859 | { | |
2860 | if (l_or_a->is_true != l_or_b->is_true) | |
2861 | return 0; | |
2862 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2863 | { | |
2864 | /* This is the case we care about. */ | |
2865 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2866 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2867 | { | |
2868 | if (prefer_const16) | |
2869 | a_greater = TRUE; | |
2870 | else | |
2871 | b_greater = TRUE; | |
2872 | } | |
2873 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2874 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2875 | { | |
2876 | if (prefer_const16) | |
2877 | b_greater = TRUE; | |
2878 | else | |
2879 | a_greater = TRUE; | |
2880 | } | |
2881 | else | |
2882 | return 0; | |
2883 | } | |
2884 | l_or_a = l_or_a->next; | |
2885 | l_or_b = l_or_b->next; | |
2886 | } | |
2887 | if (l_or_a || l_or_b) | |
2888 | return 0; | |
2889 | ||
2890 | l_a = l_a->next; | |
2891 | l_b = l_b->next; | |
2892 | } | |
2893 | if (l_a || l_b) | |
2894 | return 0; | |
2895 | ||
2896 | /* Incomparable if the substitution was used differently in two cases. */ | |
2897 | if (a_greater && b_greater) | |
2898 | return 0; | |
2899 | ||
2900 | if (b_greater) | |
2901 | return 1; | |
2902 | if (a_greater) | |
2903 | return -1; | |
2904 | ||
2905 | return 0; | |
2906 | } | |
2907 | ||
2908 | ||
2909 | static TransitionRule * | |
2910 | xg_instruction_match (TInsn *insn) | |
2911 | { | |
2912 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2913 | TransitionList *l; | |
2914 | assert (insn->opcode < table->num_opcodes); | |
2915 | ||
2916 | /* Walk through all of the possible transitions. */ | |
2917 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2918 | { | |
2919 | TransitionRule *rule = l->rule; | |
2920 | if (xg_instruction_matches_rule (insn, rule)) | |
2921 | return rule; | |
2922 | } | |
2923 | return NULL; | |
2924 | } | |
2925 | ||
2926 | \f | |
2927 | /* Various Other Internal Functions. */ | |
2928 | ||
2929 | static bfd_boolean | |
2930 | is_unique_insn_expansion (TransitionRule *r) | |
2931 | { | |
2932 | if (!r->to_instr || r->to_instr->next != NULL) | |
2933 | return FALSE; | |
2934 | if (r->to_instr->typ != INSTR_INSTR) | |
2935 | return FALSE; | |
2936 | return TRUE; | |
2937 | } | |
2938 | ||
2939 | ||
84b08ed9 BW |
2940 | /* Check if there is exactly one relaxation for INSN that converts it to |
2941 | another instruction of equal or larger size. If so, and if TARG is | |
2942 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2943 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2944 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2945 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2946 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2947 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2948 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2949 | |
84b08ed9 BW |
2950 | bfd_boolean |
2951 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2952 | { |
2953 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2954 | TransitionList *l; | |
84b08ed9 | 2955 | TransitionRule *match = 0; |
7fa3d080 | 2956 | |
7fa3d080 BW |
2957 | assert (insn->insn_type == ITYPE_INSN); |
2958 | assert (insn->opcode < table->num_opcodes); | |
2959 | ||
2960 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2961 | { | |
2962 | TransitionRule *rule = l->rule; | |
2963 | ||
2964 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2965 | && is_unique_insn_expansion (rule) |
2966 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2967 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2968 | { |
84b08ed9 BW |
2969 | if (match) |
2970 | return FALSE; | |
2971 | match = rule; | |
7fa3d080 BW |
2972 | } |
2973 | } | |
84b08ed9 BW |
2974 | if (!match) |
2975 | return FALSE; | |
2976 | ||
2977 | if (targ) | |
2978 | xg_build_to_insn (targ, insn, match->to_instr); | |
2979 | return TRUE; | |
7fa3d080 BW |
2980 | } |
2981 | ||
2982 | ||
2983 | /* Return the maximum number of bytes this opcode can expand to. */ | |
2984 | ||
2985 | static int | |
2986 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
2987 | { | |
2988 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2989 | TransitionList *l; | |
2990 | int max_size = xg_get_single_size (opcode); | |
2991 | ||
2992 | assert (opcode < table->num_opcodes); | |
2993 | ||
2994 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
2995 | { | |
2996 | TransitionRule *rule = l->rule; | |
2997 | BuildInstr *build_list; | |
2998 | int this_size = 0; | |
2999 | ||
3000 | if (!rule) | |
3001 | continue; | |
3002 | build_list = rule->to_instr; | |
3003 | if (is_unique_insn_expansion (rule)) | |
3004 | { | |
3005 | assert (build_list->typ == INSTR_INSTR); | |
3006 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3007 | } | |
3008 | else | |
3009 | for (; build_list != NULL; build_list = build_list->next) | |
3010 | { | |
3011 | switch (build_list->typ) | |
3012 | { | |
3013 | case INSTR_INSTR: | |
3014 | this_size += xg_get_single_size (build_list->opcode); | |
3015 | break; | |
3016 | case INSTR_LITERAL_DEF: | |
3017 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3018 | default: |
3019 | break; | |
3020 | } | |
3021 | } | |
3022 | if (this_size > max_size) | |
3023 | max_size = this_size; | |
3024 | } | |
3025 | return max_size; | |
3026 | } | |
3027 | ||
3028 | ||
3029 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3030 | ||
7fa3d080 BW |
3031 | static int |
3032 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3033 | { |
43cd72b9 | 3034 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3035 | TransitionList *l; |
3036 | int max_size = 0; | |
3037 | ||
3038 | assert (opcode < table->num_opcodes); | |
3039 | ||
3040 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3041 | { | |
3042 | TransitionRule *rule = l->rule; | |
3043 | BuildInstr *build_list; | |
3044 | int this_size = 0; | |
3045 | ||
3046 | if (!rule) | |
3047 | continue; | |
3048 | build_list = rule->to_instr; | |
3049 | if (is_unique_insn_expansion (rule)) | |
3050 | { | |
3051 | assert (build_list->typ == INSTR_INSTR); | |
3052 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3053 | } | |
3054 | else | |
3055 | for (; build_list != NULL; build_list = build_list->next) | |
3056 | { | |
3057 | switch (build_list->typ) | |
3058 | { | |
3059 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3060 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3061 | this_size += 4; |
3062 | break; | |
3063 | case INSTR_INSTR: | |
3064 | case INSTR_LABEL_DEF: | |
3065 | default: | |
3066 | break; | |
3067 | } | |
3068 | } | |
3069 | if (this_size > max_size) | |
3070 | max_size = this_size; | |
3071 | } | |
3072 | return max_size; | |
3073 | } | |
3074 | ||
3075 | ||
7fa3d080 BW |
3076 | static bfd_boolean |
3077 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3078 | { | |
3079 | int steps_taken = 0; | |
3080 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3081 | TransitionList *l; | |
3082 | ||
3083 | assert (insn->insn_type == ITYPE_INSN); | |
3084 | assert (insn->opcode < table->num_opcodes); | |
3085 | ||
3086 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3087 | { | |
3088 | TransitionRule *rule = l->rule; | |
3089 | ||
3090 | if (xg_instruction_matches_rule (insn, rule)) | |
3091 | { | |
3092 | if (steps_taken == lateral_steps) | |
3093 | return TRUE; | |
3094 | steps_taken++; | |
3095 | } | |
3096 | } | |
3097 | return FALSE; | |
3098 | } | |
3099 | ||
3100 | ||
3101 | static symbolS * | |
3102 | get_special_literal_symbol (void) | |
3103 | { | |
3104 | static symbolS *sym = NULL; | |
3105 | ||
3106 | if (sym == NULL) | |
3107 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3108 | return sym; | |
3109 | } | |
3110 | ||
3111 | ||
3112 | static symbolS * | |
3113 | get_special_label_symbol (void) | |
3114 | { | |
3115 | static symbolS *sym = NULL; | |
3116 | ||
3117 | if (sym == NULL) | |
3118 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3119 | return sym; | |
3120 | } | |
3121 | ||
3122 | ||
3123 | static bfd_boolean | |
3124 | xg_valid_literal_expression (const expressionS *exp) | |
3125 | { | |
3126 | switch (exp->X_op) | |
3127 | { | |
3128 | case O_constant: | |
3129 | case O_symbol: | |
3130 | case O_big: | |
3131 | case O_uminus: | |
3132 | case O_subtract: | |
3133 | case O_pltrel: | |
1bbb5f21 | 3134 | case O_pcrel: |
7fa3d080 BW |
3135 | return TRUE; |
3136 | default: | |
3137 | return FALSE; | |
3138 | } | |
3139 | } | |
3140 | ||
3141 | ||
3142 | /* This will check to see if the value can be converted into the | |
3143 | operand type. It will return TRUE if it does not fit. */ | |
3144 | ||
3145 | static bfd_boolean | |
3146 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3147 | { | |
3148 | uint32 valbuf = value; | |
3149 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3150 | return TRUE; | |
3151 | return FALSE; | |
3152 | } | |
3153 | ||
3154 | ||
3155 | /* Assumes: All immeds are constants. Check that all constants fit | |
3156 | into their immeds; return FALSE if not. */ | |
3157 | ||
3158 | static bfd_boolean | |
3159 | xg_immeds_fit (const TInsn *insn) | |
3160 | { | |
3161 | xtensa_isa isa = xtensa_default_isa; | |
3162 | int i; | |
3163 | ||
3164 | int n = insn->ntok; | |
3165 | assert (insn->insn_type == ITYPE_INSN); | |
3166 | for (i = 0; i < n; ++i) | |
3167 | { | |
3168 | const expressionS *expr = &insn->tok[i]; | |
3169 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3170 | continue; | |
3171 | ||
3172 | switch (expr->X_op) | |
3173 | { | |
3174 | case O_register: | |
3175 | case O_constant: | |
3176 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3177 | return FALSE; | |
3178 | break; | |
3179 | ||
3180 | default: | |
3181 | /* The symbol should have a fixup associated with it. */ | |
3182 | assert (FALSE); | |
3183 | break; | |
3184 | } | |
3185 | } | |
3186 | return TRUE; | |
3187 | } | |
3188 | ||
3189 | ||
3190 | /* This should only be called after we have an initial | |
3191 | estimate of the addresses. */ | |
3192 | ||
3193 | static bfd_boolean | |
3194 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3195 | segT pc_seg, | |
3196 | fragS *pc_frag, | |
3197 | offsetT pc_offset, | |
3198 | long stretch) | |
e0001a05 | 3199 | { |
7fa3d080 BW |
3200 | xtensa_isa isa = xtensa_default_isa; |
3201 | symbolS *symbolP; | |
3202 | fragS *sym_frag; | |
3203 | offsetT target, pc; | |
3204 | uint32 new_offset; | |
3205 | int i; | |
3206 | int n = insn->ntok; | |
e0001a05 NC |
3207 | |
3208 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3209 | |
7fa3d080 | 3210 | for (i = 0; i < n; ++i) |
e0001a05 | 3211 | { |
7fa3d080 BW |
3212 | const expressionS *expr = &insn->tok[i]; |
3213 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3214 | continue; | |
e0001a05 | 3215 | |
7fa3d080 | 3216 | switch (expr->X_op) |
e0001a05 | 3217 | { |
7fa3d080 BW |
3218 | case O_register: |
3219 | case O_constant: | |
3220 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3221 | return FALSE; | |
3222 | break; | |
e0001a05 | 3223 | |
7fa3d080 BW |
3224 | case O_lo16: |
3225 | case O_hi16: | |
3226 | /* Check for the worst case. */ | |
3227 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3228 | return FALSE; | |
3229 | break; | |
e0001a05 | 3230 | |
7fa3d080 | 3231 | case O_symbol: |
7c834684 | 3232 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3233 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3234 | if (pc_frag == 0 |
3235 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3236 | return FALSE; |
e0001a05 | 3237 | |
7c834684 BW |
3238 | /* If it is a weak symbol, then assume it won't reach. */ |
3239 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3240 | return FALSE; |
e0001a05 | 3241 | |
7c834684 BW |
3242 | if (is_direct_call_opcode (insn->opcode) |
3243 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3244 | { | |
3245 | /* If callee is undefined or in a different segment, be | |
3246 | optimistic and assume it will be in range. */ | |
3247 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3248 | return TRUE; | |
3249 | } | |
3250 | ||
3251 | /* Only references within a segment can be known to fit in the | |
3252 | operands at assembly time. */ | |
3253 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3254 | return FALSE; |
e0001a05 | 3255 | |
7fa3d080 BW |
3256 | symbolP = expr->X_add_symbol; |
3257 | sym_frag = symbol_get_frag (symbolP); | |
3258 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3259 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3260 | |
7fa3d080 BW |
3261 | /* If frag has yet to be reached on this pass, assume it |
3262 | will move by STRETCH just as we did. If this is not so, | |
3263 | it will be because some frag between grows, and that will | |
3264 | force another pass. Beware zero-length frags. There | |
3265 | should be a faster way to do this. */ | |
3266 | ||
3267 | if (stretch != 0 | |
3268 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3269 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3270 | { | |
3271 | target += stretch; | |
3272 | } | |
c138bc38 | 3273 | |
7fa3d080 BW |
3274 | new_offset = target; |
3275 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3276 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3277 | return FALSE; | |
3278 | break; | |
3279 | ||
3280 | default: | |
3281 | /* The symbol should have a fixup associated with it. */ | |
3282 | return FALSE; | |
3283 | } | |
3284 | } | |
3285 | ||
3286 | return TRUE; | |
e0001a05 NC |
3287 | } |
3288 | ||
3289 | ||
43cd72b9 | 3290 | /* Return TRUE on success. */ |
e0001a05 | 3291 | |
7fa3d080 BW |
3292 | static bfd_boolean |
3293 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3294 | { |
3295 | BuildOp *op; | |
3296 | symbolS *sym; | |
3297 | ||
60242db2 | 3298 | tinsn_init (targ); |
b224e962 BW |
3299 | targ->debug_line = insn->debug_line; |
3300 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3301 | switch (bi->typ) |
3302 | { | |
3303 | case INSTR_INSTR: | |
3304 | op = bi->ops; | |
3305 | targ->opcode = bi->opcode; | |
3306 | targ->insn_type = ITYPE_INSN; | |
3307 | targ->is_specific_opcode = FALSE; | |
3308 | ||
3309 | for (; op != NULL; op = op->next) | |
3310 | { | |
3311 | int op_num = op->op_num; | |
3312 | int op_data = op->op_data; | |
3313 | ||
3314 | assert (op->op_num < MAX_INSN_ARGS); | |
3315 | ||
3316 | if (targ->ntok <= op_num) | |
3317 | targ->ntok = op_num + 1; | |
3318 | ||
3319 | switch (op->typ) | |
3320 | { | |
3321 | case OP_CONSTANT: | |
3322 | set_expr_const (&targ->tok[op_num], op_data); | |
3323 | break; | |
3324 | case OP_OPERAND: | |
3325 | assert (op_data < insn->ntok); | |
3326 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3327 | break; | |
3328 | case OP_LITERAL: | |
3329 | sym = get_special_literal_symbol (); | |
3330 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3331 | break; | |
3332 | case OP_LABEL: | |
3333 | sym = get_special_label_symbol (); | |
3334 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3335 | break; | |
43cd72b9 BW |
3336 | case OP_OPERAND_HI16U: |
3337 | case OP_OPERAND_LOW16U: | |
3338 | assert (op_data < insn->ntok); | |
3339 | if (expr_is_const (&insn->tok[op_data])) | |
3340 | { | |
3341 | long val; | |
3342 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3343 | val = xg_apply_userdef_op_fn (op->typ, | |
3344 | targ->tok[op_num]. | |
3345 | X_add_number); | |
3346 | targ->tok[op_num].X_add_number = val; | |
3347 | } | |
3348 | else | |
3349 | { | |
3350 | /* For const16 we can create relocations for these. */ | |
3351 | if (targ->opcode == XTENSA_UNDEFINED | |
3352 | || (targ->opcode != xtensa_const16_opcode)) | |
3353 | return FALSE; | |
3354 | assert (op_data < insn->ntok); | |
3355 | /* Need to build a O_lo16 or O_hi16. */ | |
3356 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3357 | if (targ->tok[op_num].X_op == O_symbol) | |
3358 | { | |
3359 | if (op->typ == OP_OPERAND_HI16U) | |
3360 | targ->tok[op_num].X_op = O_hi16; | |
3361 | else if (op->typ == OP_OPERAND_LOW16U) | |
3362 | targ->tok[op_num].X_op = O_lo16; | |
3363 | else | |
3364 | return FALSE; | |
3365 | } | |
3366 | } | |
3367 | break; | |
e0001a05 NC |
3368 | default: |
3369 | /* currently handles: | |
3370 | OP_OPERAND_LOW8 | |
3371 | OP_OPERAND_HI24S | |
3372 | OP_OPERAND_F32MINUS */ | |
3373 | if (xg_has_userdef_op_fn (op->typ)) | |
3374 | { | |
3375 | assert (op_data < insn->ntok); | |
3376 | if (expr_is_const (&insn->tok[op_data])) | |
3377 | { | |
3378 | long val; | |
3379 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3380 | val = xg_apply_userdef_op_fn (op->typ, | |
3381 | targ->tok[op_num]. | |
3382 | X_add_number); | |
3383 | targ->tok[op_num].X_add_number = val; | |
3384 | } | |
3385 | else | |
3386 | return FALSE; /* We cannot use a relocation for this. */ | |
3387 | break; | |
3388 | } | |
3389 | assert (0); | |
3390 | break; | |
3391 | } | |
3392 | } | |
3393 | break; | |
3394 | ||
3395 | case INSTR_LITERAL_DEF: | |
3396 | op = bi->ops; | |
3397 | targ->opcode = XTENSA_UNDEFINED; | |
3398 | targ->insn_type = ITYPE_LITERAL; | |
3399 | targ->is_specific_opcode = FALSE; | |
3400 | for (; op != NULL; op = op->next) | |
3401 | { | |
3402 | int op_num = op->op_num; | |
3403 | int op_data = op->op_data; | |
3404 | assert (op->op_num < MAX_INSN_ARGS); | |
3405 | ||
3406 | if (targ->ntok <= op_num) | |
3407 | targ->ntok = op_num + 1; | |
3408 | ||
3409 | switch (op->typ) | |
3410 | { | |
3411 | case OP_OPERAND: | |
3412 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3413 | /* We can only pass resolvable literals through. */ |
3414 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3415 | return FALSE; | |
e0001a05 NC |
3416 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3417 | break; | |
3418 | case OP_LITERAL: | |
3419 | case OP_CONSTANT: | |
3420 | case OP_LABEL: | |
3421 | default: | |
3422 | assert (0); | |
3423 | break; | |
3424 | } | |
3425 | } | |
3426 | break; | |
3427 | ||
3428 | case INSTR_LABEL_DEF: | |
3429 | op = bi->ops; | |
3430 | targ->opcode = XTENSA_UNDEFINED; | |
3431 | targ->insn_type = ITYPE_LABEL; | |
3432 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3433 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3434 | assert (op == NULL); |
3435 | break; | |
3436 | ||
3437 | default: | |
3438 | assert (0); | |
3439 | } | |
3440 | ||
3441 | return TRUE; | |
3442 | } | |
3443 | ||
3444 | ||
43cd72b9 | 3445 | /* Return TRUE on success. */ |
e0001a05 | 3446 | |
7fa3d080 BW |
3447 | static bfd_boolean |
3448 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3449 | { |
3450 | for (; bi != NULL; bi = bi->next) | |
3451 | { | |
3452 | TInsn *next_insn = istack_push_space (istack); | |
3453 | ||
3454 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3455 | return FALSE; | |
3456 | } | |
3457 | return TRUE; | |
3458 | } | |
3459 | ||
3460 | ||
43cd72b9 | 3461 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3462 | |
7fa3d080 BW |
3463 | static bfd_boolean |
3464 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3465 | { |
3466 | int stack_size = istack->ninsn; | |
3467 | int steps_taken = 0; | |
43cd72b9 | 3468 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3469 | TransitionList *l; |
3470 | ||
3471 | assert (insn->insn_type == ITYPE_INSN); | |
3472 | assert (insn->opcode < table->num_opcodes); | |
3473 | ||
3474 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3475 | { | |
3476 | TransitionRule *rule = l->rule; | |
3477 | ||
3478 | if (xg_instruction_matches_rule (insn, rule)) | |
3479 | { | |
3480 | if (lateral_steps == steps_taken) | |
3481 | { | |
3482 | int i; | |
3483 | ||
3484 | /* This is it. Expand the rule to the stack. */ | |
3485 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3486 | return FALSE; | |
3487 | ||
3488 | /* Check to see if it fits. */ | |
3489 | for (i = stack_size; i < istack->ninsn; i++) | |
3490 | { | |
3491 | TInsn *insn = &istack->insn[i]; | |
3492 | ||
3493 | if (insn->insn_type == ITYPE_INSN | |
3494 | && !tinsn_has_symbolic_operands (insn) | |
3495 | && !xg_immeds_fit (insn)) | |
3496 | { | |
3497 | istack->ninsn = stack_size; | |
3498 | return FALSE; | |
3499 | } | |
3500 | } | |
3501 | return TRUE; | |
3502 | } | |
3503 | steps_taken++; | |
3504 | } | |
3505 | } | |
3506 | return FALSE; | |
3507 | } | |
3508 | ||
43cd72b9 | 3509 | \f |
43cd72b9 | 3510 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3511 | Return the number of steps taken. |
3512 | ||
3513 | For relaxation to correctly terminate, every relaxation chain must | |
3514 | terminate in one of two ways: | |
3515 | ||
3516 | 1. If the chain from one instruction to the next consists entirely of | |
3517 | single instructions, then the chain *must* handle all possible | |
3518 | immediates without failing. It must not ever fail because an | |
3519 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3520 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3521 | immediate larger than 32 bits, so it satisfies this condition. | |
3522 | Single instruction relaxation chains are as defined by | |
3523 | xg_is_single_relaxable_instruction. | |
3524 | ||
3525 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3526 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3527 | ||
3528 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3529 | -- in particular when the last two instructions have the same single | |
3530 | size. But nevertheless, you should guarantee the above two conditions. | |
3531 | ||
3532 | We could fix this so that single-instruction expansions correctly | |
3533 | terminate when they can't handle the range, but the error messages are | |
3534 | worse, and it actually turns out that in every case but one (18-bit wide | |
3535 | branches), you need a multi-instruction expansion to get the full range | |
3536 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3537 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3538 | |
7fa3d080 BW |
3539 | static int |
3540 | xg_assembly_relax (IStack *istack, | |
3541 | TInsn *insn, | |
3542 | segT pc_seg, | |
3543 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3544 | offsetT pc_offset, /* offset in fragment */ | |
3545 | int min_steps, /* minimum conversion steps */ | |
3546 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3547 | { |
3548 | int steps_taken = 0; | |
3549 | ||
b81bf389 BW |
3550 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3551 | This may go through a couple of stages of single instruction | |
3552 | transformations before we get there. */ | |
e0001a05 NC |
3553 | |
3554 | TInsn single_target; | |
3555 | TInsn current_insn; | |
3556 | int lateral_steps = 0; | |
3557 | int istack_size = istack->ninsn; | |
3558 | ||
3559 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3560 | && steps_taken >= min_steps) | |
3561 | { | |
3562 | istack_push (istack, insn); | |
3563 | return steps_taken; | |
3564 | } | |
43cd72b9 | 3565 | current_insn = *insn; |
e0001a05 | 3566 | |
7c834684 | 3567 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3568 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3569 | { |
21af2bbd | 3570 | steps_taken++; |
e0001a05 NC |
3571 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3572 | stretch)) | |
3573 | { | |
e0001a05 NC |
3574 | if (steps_taken >= min_steps) |
3575 | { | |
3576 | istack_push (istack, &single_target); | |
3577 | return steps_taken; | |
3578 | } | |
3579 | } | |
43cd72b9 | 3580 | current_insn = single_target; |
e0001a05 NC |
3581 | } |
3582 | ||
3583 | /* Now check for a multi-instruction expansion. */ | |
3584 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3585 | { | |
3586 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3587 | stretch)) | |
3588 | { | |
3589 | if (steps_taken >= min_steps) | |
3590 | { | |
3591 | istack_push (istack, ¤t_insn); | |
3592 | return steps_taken; | |
3593 | } | |
3594 | } | |
3595 | steps_taken++; | |
3596 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3597 | { | |
3598 | if (steps_taken >= min_steps) | |
3599 | return steps_taken; | |
3600 | } | |
3601 | lateral_steps++; | |
3602 | istack->ninsn = istack_size; | |
3603 | } | |
3604 | ||
3605 | /* It's not going to work -- use the original. */ | |
3606 | istack_push (istack, insn); | |
3607 | return steps_taken; | |
3608 | } | |
3609 | ||
3610 | ||
7fa3d080 BW |
3611 | static void |
3612 | xg_finish_frag (char *last_insn, | |
3613 | enum xtensa_relax_statesE frag_state, | |
3614 | enum xtensa_relax_statesE slot0_state, | |
3615 | int max_growth, | |
3616 | bfd_boolean is_insn) | |
e0001a05 NC |
3617 | { |
3618 | /* Finish off this fragment so that it has at LEAST the desired | |
3619 | max_growth. If it doesn't fit in this fragment, close this one | |
3620 | and start a new one. In either case, return a pointer to the | |
3621 | beginning of the growth area. */ | |
3622 | ||
3623 | fragS *old_frag; | |
43cd72b9 | 3624 | |
542f8b94 | 3625 | frag_grow (max_growth); |
e0001a05 NC |
3626 | old_frag = frag_now; |
3627 | ||
3628 | frag_now->fr_opcode = last_insn; | |
3629 | if (is_insn) | |
3630 | frag_now->tc_frag_data.is_insn = TRUE; | |
3631 | ||
3632 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3633 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3634 | ||
3635 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3636 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3637 | |
3638 | /* Just to make sure that we did not split it up. */ | |
3639 | assert (old_frag->fr_next == frag_now); | |
3640 | } | |
3641 | ||
3642 | ||
7fa3d080 BW |
3643 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3644 | ||
3645 | static bfd_boolean | |
3646 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3647 | { | |
3648 | if (fragP == NULL) | |
3649 | return FALSE; | |
3650 | ||
3651 | for (; fragP; fragP = fragP->fr_next) | |
3652 | { | |
3653 | if (fragP == target) | |
3654 | return TRUE; | |
3655 | if (fragP->fr_fix != 0) | |
3656 | return FALSE; | |
3657 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3658 | return FALSE; | |
3659 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3660 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3661 | return FALSE; | |
3662 | if (fragP->fr_type == rs_space) | |
3663 | return FALSE; | |
3664 | } | |
3665 | return FALSE; | |
3666 | } | |
3667 | ||
3668 | ||
e0001a05 | 3669 | static bfd_boolean |
7fa3d080 | 3670 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3671 | { |
3672 | xtensa_isa isa = xtensa_default_isa; | |
3673 | int i; | |
43cd72b9 | 3674 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3675 | int target_op = -1; |
3676 | symbolS *sym; | |
3677 | fragS *target_frag; | |
3678 | ||
64b607e6 BW |
3679 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3680 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3681 | return FALSE; |
3682 | ||
3683 | for (i = 0; i < num_ops; i++) | |
3684 | { | |
43cd72b9 | 3685 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3686 | { |
3687 | target_op = i; | |
3688 | break; | |
3689 | } | |
3690 | } | |
3691 | if (target_op == -1) | |
3692 | return FALSE; | |
3693 | ||
3694 | if (insn->ntok <= target_op) | |
3695 | return FALSE; | |
3696 | ||
3697 | if (insn->tok[target_op].X_op != O_symbol) | |
3698 | return FALSE; | |
3699 | ||
3700 | sym = insn->tok[target_op].X_add_symbol; | |
3701 | if (sym == NULL) | |
3702 | return FALSE; | |
3703 | ||
3704 | if (insn->tok[target_op].X_add_number != 0) | |
3705 | return FALSE; | |
3706 | ||
3707 | target_frag = symbol_get_frag (sym); | |
3708 | if (target_frag == NULL) | |
3709 | return FALSE; | |
3710 | ||
c138bc38 | 3711 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3712 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3713 | return TRUE; | |
3714 | ||
3715 | return FALSE; | |
3716 | } | |
3717 | ||
3718 | ||
3719 | static void | |
7fa3d080 | 3720 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3721 | { |
3722 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3723 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3724 | |
7fa3d080 BW |
3725 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3726 | { | |
3727 | int i = 1; | |
3728 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3729 | && insn->tok[i].X_op == O_symbol) | |
3730 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3731 | return; | |
3732 | } | |
e0001a05 | 3733 | |
7fa3d080 BW |
3734 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3735 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3736 | { |
7fa3d080 BW |
3737 | int i; |
3738 | ||
3739 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3740 | { | |
3741 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3742 | && insn->tok[i].X_op == O_symbol) | |
3743 | { | |
3744 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3745 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3746 | if (S_IS_DEFINED (sym)) | |
3747 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3748 | } | |
3749 | } | |
e0001a05 | 3750 | } |
e0001a05 NC |
3751 | } |
3752 | ||
3753 | ||
43cd72b9 | 3754 | /* Return FALSE if no error. */ |
e0001a05 | 3755 | |
7fa3d080 BW |
3756 | static bfd_boolean |
3757 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3758 | { |
3759 | int num_ops = 0; | |
3760 | BuildOp *b_op; | |
3761 | ||
3762 | switch (instr_spec->typ) | |
3763 | { | |
3764 | case INSTR_INSTR: | |
3765 | new_insn->insn_type = ITYPE_INSN; | |
3766 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3767 | break; |
3768 | case INSTR_LITERAL_DEF: | |
3769 | new_insn->insn_type = ITYPE_LITERAL; | |
3770 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3771 | break; |
3772 | case INSTR_LABEL_DEF: | |
b224e962 | 3773 | abort (); |
e0001a05 | 3774 | } |
b224e962 BW |
3775 | new_insn->is_specific_opcode = FALSE; |
3776 | new_insn->debug_line = old_insn->debug_line; | |
3777 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3778 | |
3779 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3780 | { | |
3781 | expressionS *exp; | |
3782 | const expressionS *src_exp; | |
3783 | ||
3784 | num_ops++; | |
3785 | switch (b_op->typ) | |
3786 | { | |
3787 | case OP_CONSTANT: | |
3788 | /* The expression must be the constant. */ | |
3789 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3790 | exp = &new_insn->tok[b_op->op_num]; | |
3791 | set_expr_const (exp, b_op->op_data); | |
3792 | break; | |
3793 | ||
3794 | case OP_OPERAND: | |
3795 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3796 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3797 | src_exp = &old_insn->tok[b_op->op_data]; | |
3798 | exp = &new_insn->tok[b_op->op_num]; | |
3799 | copy_expr (exp, src_exp); | |
3800 | break; | |
3801 | ||
3802 | case OP_LITERAL: | |
3803 | case OP_LABEL: | |
3804 | as_bad (_("can't handle generation of literal/labels yet")); | |
3805 | assert (0); | |
3806 | ||
3807 | default: | |
3808 | as_bad (_("can't handle undefined OP TYPE")); | |
3809 | assert (0); | |
3810 | } | |
3811 | } | |
3812 | ||
3813 | new_insn->ntok = num_ops; | |
3814 | return FALSE; | |
3815 | } | |
3816 | ||
3817 | ||
43cd72b9 | 3818 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3819 | |
7fa3d080 BW |
3820 | static bfd_boolean |
3821 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3822 | { |
43cd72b9 | 3823 | TransitionRule *rule; |
e0001a05 | 3824 | BuildInstr *insn_spec; |
43cd72b9 BW |
3825 | |
3826 | if (old_insn->is_specific_opcode || !density_supported) | |
3827 | return FALSE; | |
3828 | ||
3829 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3830 | if (rule == NULL) |
3831 | return FALSE; | |
3832 | ||
3833 | insn_spec = rule->to_instr; | |
3834 | /* There should only be one. */ | |
3835 | assert (insn_spec != NULL); | |
3836 | assert (insn_spec->next == NULL); | |
3837 | if (insn_spec->next != NULL) | |
3838 | return FALSE; | |
3839 | ||
3840 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3841 | ||
3842 | return TRUE; | |
3843 | } | |
3844 | ||
3845 | ||
3846 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3847 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3848 | tokens into the stack or relax it and place multiple |
3849 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3850 | |
3851 | static bfd_boolean | |
7fa3d080 | 3852 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3853 | { |
3854 | int noperands; | |
3855 | TInsn new_insn; | |
7c834684 BW |
3856 | bfd_boolean do_expand; |
3857 | ||
60242db2 | 3858 | tinsn_init (&new_insn); |
e0001a05 | 3859 | |
43cd72b9 BW |
3860 | /* Narrow it if we can. xg_simplify_insn now does all the |
3861 | appropriate checking (e.g., for the density option). */ | |
3862 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3863 | orig_insn = &new_insn; | |
e0001a05 | 3864 | |
43cd72b9 BW |
3865 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3866 | orig_insn->opcode); | |
e0001a05 NC |
3867 | if (orig_insn->ntok < noperands) |
3868 | { | |
3869 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3870 | orig_insn->ntok, | |
3871 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3872 | noperands); | |
3873 | return TRUE; | |
3874 | } | |
3875 | if (orig_insn->ntok > noperands) | |
3876 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3877 | orig_insn->ntok, | |
3878 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3879 | noperands); | |
3880 | ||
43cd72b9 | 3881 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3882 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3883 | orig_insn->ntok = noperands; |
3884 | ||
e0001a05 NC |
3885 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3886 | return TRUE; | |
3887 | ||
d12f9798 BW |
3888 | /* Special case for extui opcode which has constraints not handled |
3889 | by the ordinary operand encoding checks. The number of operands | |
3890 | and related syntax issues have already been checked. */ | |
3891 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3892 | { | |
3893 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3894 | int maskimm = orig_insn->tok[3].X_add_number; | |
3895 | if (shiftimm + maskimm > 32) | |
3896 | { | |
3897 | as_bad (_("immediate operands sum to greater than 32")); | |
3898 | return TRUE; | |
3899 | } | |
3900 | } | |
3901 | ||
7c834684 BW |
3902 | /* If the instruction will definitely need to be relaxed, it is better |
3903 | to expand it now for better scheduling. Decide whether to expand | |
3904 | now.... */ | |
3905 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3906 | ||
3907 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3908 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3909 | adjacent. */ | |
3910 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3911 | do_expand = FALSE; | |
e0001a05 NC |
3912 | |
3913 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3914 | { | |
7c834684 BW |
3915 | /* The values of symbolic operands are not known yet, so only expand |
3916 | now if an operand is "complex" (e.g., difference of symbols) and | |
3917 | will have to be stored as a literal regardless of the value. */ | |
3918 | if (!tinsn_has_complex_operands (orig_insn)) | |
3919 | do_expand = FALSE; | |
e0001a05 | 3920 | } |
7c834684 BW |
3921 | else if (xg_immeds_fit (orig_insn)) |
3922 | do_expand = FALSE; | |
3923 | ||
3924 | if (do_expand) | |
3925 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3926 | else |
7c834684 | 3927 | istack_push (istack, orig_insn); |
e0001a05 | 3928 | |
e0001a05 NC |
3929 | return FALSE; |
3930 | } | |
3931 | ||
3932 | ||
7fa3d080 | 3933 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3934 | or the name is .gnu.linkonce.*. */ |
3935 | ||
3936 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3937 | |
3938 | static bfd_boolean | |
3939 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3940 | { | |
3941 | flagword flags, link_once_flags; | |
3942 | ||
3943 | flags = bfd_get_section_flags (abfd, sec); | |
3944 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3945 | ||
3946 | /* Flags might not be set yet. */ | |
74869ac7 BW |
3947 | if (!link_once_flags |
3948 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
3949 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 3950 | |
7fa3d080 BW |
3951 | return (link_once_flags != 0); |
3952 | } | |
3953 | ||
3954 | ||
3955 | static void | |
3956 | xtensa_add_literal_sym (symbolS *sym) | |
3957 | { | |
3958 | sym_list *l; | |
3959 | ||
3960 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3961 | l->sym = sym; | |
3962 | l->next = literal_syms; | |
3963 | literal_syms = l; | |
3964 | } | |
3965 | ||
3966 | ||
3967 | static symbolS * | |
3968 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3969 | { | |
3970 | static int lit_num = 0; | |
3971 | static char name[256]; | |
3972 | symbolS *symbolP; | |
3973 | ||
3974 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3975 | ||
3976 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3977 | be careful to make sure that if it is used in a relocation that the | |
3978 | symbol will be in the output file. */ | |
3979 | if (get_is_linkonce_section (stdoutput, sec)) | |
3980 | { | |
3981 | symbolP = symbol_new (name, sec, 0, frag); | |
3982 | S_CLEAR_EXTERNAL (symbolP); | |
3983 | /* symbolP->local = 1; */ | |
3984 | } | |
3985 | else | |
3986 | symbolP = symbol_new (name, sec, 0, frag); | |
3987 | ||
3988 | xtensa_add_literal_sym (symbolP); | |
3989 | ||
7fa3d080 BW |
3990 | lit_num++; |
3991 | return symbolP; | |
3992 | } | |
3993 | ||
3994 | ||
e0001a05 NC |
3995 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
3996 | ||
7fa3d080 BW |
3997 | static symbolS * |
3998 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
3999 | { |
4000 | emit_state state; | |
4001 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4002 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4003 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4004 | char *p; |
e0001a05 NC |
4005 | |
4006 | /* size = 4 for L32R. It could easily be larger when we move to | |
4007 | larger constants. Add a parameter later. */ | |
4008 | offsetT litsize = 4; | |
4009 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4010 | expressionS saved_loc; | |
43cd72b9 BW |
4011 | expressionS * emit_val; |
4012 | ||
e0001a05 NC |
4013 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4014 | ||
4015 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4016 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4017 | |
4018 | xtensa_switch_to_literal_fragment (&state); | |
4019 | ||
43cd72b9 BW |
4020 | emit_val = &insn->tok[0]; |
4021 | if (emit_val->X_op == O_big) | |
4022 | { | |
4023 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4024 | if (size > litsize) | |
4025 | { | |
4026 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4027 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4028 | _("invalid immediate")); |
4029 | xtensa_restore_emit_state (&state); | |
4030 | return NULL; | |
4031 | } | |
4032 | } | |
4033 | ||
e0001a05 NC |
4034 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4035 | literals done with this function have a frag to themselves. That's | |
4036 | important for the way text section literals work. */ | |
4037 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4038 | record_alignment (now_seg, litalign); |
e0001a05 | 4039 | |
bbdd25a8 | 4040 | switch (emit_val->X_op) |
43cd72b9 | 4041 | { |
1bbb5f21 BW |
4042 | case O_pcrel: |
4043 | pcrel = TRUE; | |
4044 | /* fall through */ | |
bbdd25a8 BW |
4045 | case O_pltrel: |
4046 | p = frag_more (litsize); | |
43cd72b9 | 4047 | xtensa_set_frag_assembly_state (frag_now); |
bbdd25a8 | 4048 | reloc = map_operator_to_reloc (emit_val->X_op); |
43cd72b9 BW |
4049 | if (emit_val->X_add_symbol) |
4050 | emit_val->X_op = O_symbol; | |
4051 | else | |
4052 | emit_val->X_op = O_constant; | |
4053 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4054 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4055 | break; |
4056 | ||
4057 | default: | |
4058 | emit_expr (emit_val, litsize); | |
4059 | break; | |
43cd72b9 | 4060 | } |
e0001a05 NC |
4061 | |
4062 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4063 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4064 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4065 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4066 | |
4067 | /* Go back. */ | |
4068 | xtensa_restore_emit_state (&state); | |
4069 | return lit_sym; | |
4070 | } | |
4071 | ||
4072 | ||
4073 | static void | |
7fa3d080 | 4074 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4075 | { |
4076 | emit_state state; | |
43cd72b9 | 4077 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4078 | takes effect if something is placed here. */ |
4079 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4080 | fragS *lit_saved_frag; | |
4081 | ||
e0001a05 | 4082 | assert (size % 4 == 0); |
e0001a05 NC |
4083 | |
4084 | xtensa_switch_to_literal_fragment (&state); | |
4085 | ||
4086 | /* Force a 4-byte align here. */ | |
4087 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4088 | record_alignment (now_seg, litalign); |
e0001a05 | 4089 | |
542f8b94 | 4090 | frag_grow (size); |
e0001a05 NC |
4091 | |
4092 | lit_saved_frag = frag_now; | |
4093 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4094 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4095 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4096 | |
4097 | /* Go back. */ | |
4098 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4099 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4100 | } |
4101 | ||
4102 | ||
e0001a05 | 4103 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4104 | Return TRUE on success. */ |
e0001a05 | 4105 | |
7fa3d080 BW |
4106 | static bfd_boolean |
4107 | xg_add_opcode_fix (TInsn *tinsn, | |
4108 | int opnum, | |
4109 | xtensa_format fmt, | |
4110 | int slot, | |
4111 | expressionS *expr, | |
4112 | fragS *fragP, | |
4113 | offsetT offset) | |
43cd72b9 BW |
4114 | { |
4115 | xtensa_opcode opcode = tinsn->opcode; | |
4116 | bfd_reloc_code_real_type reloc; | |
4117 | reloc_howto_type *howto; | |
4118 | int fmt_length; | |
e0001a05 NC |
4119 | fixS *the_fix; |
4120 | ||
43cd72b9 BW |
4121 | reloc = BFD_RELOC_NONE; |
4122 | ||
4123 | /* First try the special cases for "alternate" relocs. */ | |
4124 | if (opcode == xtensa_l32r_opcode) | |
4125 | { | |
4126 | if (fragP->tc_frag_data.use_absolute_literals) | |
4127 | reloc = encode_alt_reloc (slot); | |
4128 | } | |
4129 | else if (opcode == xtensa_const16_opcode) | |
4130 | { | |
4131 | if (expr->X_op == O_lo16) | |
4132 | { | |
4133 | reloc = encode_reloc (slot); | |
4134 | expr->X_op = O_symbol; | |
4135 | } | |
4136 | else if (expr->X_op == O_hi16) | |
4137 | { | |
4138 | reloc = encode_alt_reloc (slot); | |
4139 | expr->X_op = O_symbol; | |
4140 | } | |
4141 | } | |
4142 | ||
4143 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4144 | { |
43cd72b9 | 4145 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4146 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4147 | return FALSE; |
4148 | } | |
4149 | ||
43cd72b9 BW |
4150 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4151 | into the symbol table where the generic portions of the assembler | |
4152 | won't know what to do with them. */ | |
4153 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4154 | { | |
4155 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4156 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4157 | return FALSE; |
4158 | } | |
4159 | ||
4160 | /* Next try the generic relocs. */ | |
4161 | if (reloc == BFD_RELOC_NONE) | |
4162 | reloc = encode_reloc (slot); | |
4163 | if (reloc == BFD_RELOC_NONE) | |
4164 | { | |
4165 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4166 | return FALSE; | |
4167 | } | |
e0001a05 | 4168 | |
43cd72b9 | 4169 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4170 | if (!howto) |
4171 | { | |
43cd72b9 | 4172 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4173 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4174 | return FALSE; | |
4175 | } | |
4176 | ||
43cd72b9 BW |
4177 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4178 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4179 | howto->pc_relative, reloc); |
d9740523 | 4180 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4181 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4182 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4183 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4184 | |
7fa3d080 BW |
4185 | return TRUE; |
4186 | } | |
4187 | ||
4188 | ||
4189 | static bfd_boolean | |
4190 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4191 | char *buf, |
4192 | fragS *fragP, | |
4193 | offsetT offset, | |
4194 | bfd_boolean build_fix) | |
4195 | { | |
4196 | static xtensa_insnbuf insnbuf = NULL; | |
4197 | bfd_boolean has_symbolic_immed = FALSE; | |
4198 | bfd_boolean ok = TRUE; | |
b2d179be | 4199 | |
7fa3d080 BW |
4200 | if (!insnbuf) |
4201 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4202 | ||
4203 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4204 | if (has_symbolic_immed && build_fix) | |
4205 | { | |
4206 | /* Add a fixup. */ | |
b2d179be BW |
4207 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4208 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4209 | int opnum = get_relaxable_immed (tinsn->opcode); |
4210 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4211 | |
b2d179be | 4212 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4213 | ok = FALSE; |
4214 | } | |
4215 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4216 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4217 | (unsigned char *) buf, 0); | |
7fa3d080 | 4218 | return ok; |
e0001a05 NC |
4219 | } |
4220 | ||
4221 | ||
7fa3d080 BW |
4222 | static void |
4223 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4224 | { |
4225 | symbolS *sym = get_special_literal_symbol (); | |
4226 | int i; | |
4227 | if (lit_sym == 0) | |
4228 | return; | |
4229 | assert (insn->insn_type == ITYPE_INSN); | |
4230 | for (i = 0; i < insn->ntok; i++) | |
4231 | if (insn->tok[i].X_add_symbol == sym) | |
4232 | insn->tok[i].X_add_symbol = lit_sym; | |
4233 | ||
4234 | } | |
4235 | ||
4236 | ||
7fa3d080 BW |
4237 | static void |
4238 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4239 | { |
4240 | symbolS *sym = get_special_label_symbol (); | |
4241 | int i; | |
e0001a05 NC |
4242 | for (i = 0; i < insn->ntok; i++) |
4243 | if (insn->tok[i].X_add_symbol == sym) | |
4244 | insn->tok[i].X_add_symbol = label_sym; | |
4245 | ||
4246 | } | |
4247 | ||
4248 | ||
43cd72b9 | 4249 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4250 | integer register. */ |
4251 | ||
4252 | static bfd_boolean | |
7fa3d080 | 4253 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4254 | { |
4255 | int i; | |
4256 | int num_ops; | |
4257 | xtensa_isa isa = xtensa_default_isa; | |
4258 | ||
43cd72b9 | 4259 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4260 | |
4261 | for (i = 0; i < num_ops; i++) | |
4262 | { | |
43cd72b9 BW |
4263 | char inout; |
4264 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4265 | if ((inout == 'o' || inout == 'm') | |
4266 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4267 | { |
43cd72b9 BW |
4268 | xtensa_regfile opnd_rf = |
4269 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4270 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4271 | { |
4272 | if ((insn->tok[i].X_op == O_register) | |
4273 | && (insn->tok[i].X_add_number == regnum)) | |
4274 | return TRUE; | |
4275 | } | |
4276 | } | |
4277 | } | |
4278 | return FALSE; | |
4279 | } | |
4280 | ||
4281 | ||
4282 | static bfd_boolean | |
7fa3d080 | 4283 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4284 | { |
4285 | xtensa_opcode opcode = tinsn->opcode; | |
4286 | ||
4287 | if (opcode == XTENSA_UNDEFINED) | |
4288 | return FALSE; | |
4289 | ||
4290 | if (opcode == xtensa_call0_opcode | |
4291 | || opcode == xtensa_callx0_opcode | |
4292 | || opcode == xtensa_call4_opcode | |
4293 | || opcode == xtensa_callx4_opcode | |
4294 | || opcode == xtensa_call8_opcode | |
4295 | || opcode == xtensa_callx8_opcode | |
4296 | || opcode == xtensa_call12_opcode | |
4297 | || opcode == xtensa_callx12_opcode | |
4298 | || opcode == xtensa_isync_opcode | |
4299 | || opcode == xtensa_ret_opcode | |
4300 | || opcode == xtensa_ret_n_opcode | |
4301 | || opcode == xtensa_retw_opcode | |
4302 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4303 | || opcode == xtensa_waiti_opcode |
4304 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4305 | return TRUE; |
c138bc38 | 4306 | |
e0001a05 NC |
4307 | return FALSE; |
4308 | } | |
4309 | ||
4310 | ||
4311 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4312 | This allows the debugger to add unaligned labels. | |
4313 | Also, the assembler generates stabs labels that need | |
4314 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4315 | ||
7fa3d080 BW |
4316 | static bfd_boolean |
4317 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4318 | { |
4319 | const char *name = S_GET_NAME (sym); | |
4320 | static size_t fake_size = 0; | |
4321 | ||
4322 | if (name | |
4323 | && name[0] == '.' | |
4324 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4325 | return TRUE; | |
4326 | ||
4327 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4328 | if (fake_size == 0) | |
4329 | fake_size = strlen (FAKE_LABEL_NAME); | |
4330 | ||
43cd72b9 | 4331 | if (name |
e0001a05 NC |
4332 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4333 | && (name[fake_size] == 'F' | |
4334 | || name[fake_size] == 'L' | |
4335 | || (name[fake_size] == 'e' | |
4336 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4337 | return TRUE; | |
4338 | ||
4339 | return FALSE; | |
4340 | } | |
4341 | ||
4342 | ||
7fa3d080 BW |
4343 | static fragS * |
4344 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4345 | { |
4346 | fragS *next_fragP = fragP->fr_next; | |
4347 | ||
c138bc38 | 4348 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4349 | So we have to skip until we find something legit. */ |
4350 | while (next_fragP && next_fragP->fr_fix == 0) | |
4351 | next_fragP = next_fragP->fr_next; | |
4352 | ||
4353 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4354 | return NULL; | |
4355 | ||
4356 | return next_fragP; | |
4357 | } | |
4358 | ||
4359 | ||
43cd72b9 | 4360 | static bfd_boolean |
7fa3d080 | 4361 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4362 | { |
4363 | xtensa_opcode out_opcode; | |
4364 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4365 | ||
4366 | if (next_fragP == NULL) | |
4367 | return FALSE; | |
4368 | ||
4369 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4370 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4371 | { | |
4372 | *opcode = out_opcode; | |
4373 | return TRUE; | |
4374 | } | |
4375 | return FALSE; | |
4376 | } | |
4377 | ||
4378 | ||
4379 | static int | |
7fa3d080 | 4380 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4381 | { |
e0001a05 NC |
4382 | static xtensa_insnbuf insnbuf = NULL; |
4383 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4384 | xtensa_format fmt; |
c138bc38 | 4385 | int fmt_size; |
e0001a05 NC |
4386 | |
4387 | if (!insnbuf) | |
4388 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4389 | ||
43cd72b9 BW |
4390 | if (fragP == NULL) |
4391 | return XTENSA_UNDEFINED; | |
4392 | ||
d77b99c9 BW |
4393 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4394 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4395 | |
4396 | fmt = xtensa_format_decode (isa, insnbuf); | |
4397 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4398 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4399 | fmt_size = xtensa_format_length (isa, fmt); |
4400 | ||
4401 | /* If the next format won't be changing due to relaxation, just | |
4402 | return the length of the first format. */ | |
4403 | if (fragP->fr_opcode != fragP->fr_literal) | |
4404 | return fmt_size; | |
4405 | ||
c138bc38 | 4406 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4407 | multi-slot instruction, we will return the more conservative |
4408 | number. This works because alignment on bigger instructions | |
4409 | is more restrictive than alignment on smaller instructions. | |
4410 | This is more conservative than we would like, but it happens | |
4411 | infrequently. */ | |
4412 | ||
4413 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4414 | return fmt_size; | |
4415 | ||
4416 | /* If we aren't doing one of our own relaxations or it isn't | |
4417 | slot-based, then the insn size won't change. */ | |
4418 | if (fragP->fr_type != rs_machine_dependent) | |
4419 | return fmt_size; | |
4420 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4421 | return fmt_size; | |
4422 | ||
4423 | /* If an instruction is about to grow, return the longer size. */ | |
4424 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4425 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4426 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
43cd72b9 | 4427 | return 3; |
c138bc38 | 4428 | |
43cd72b9 BW |
4429 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4430 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4431 | |
43cd72b9 | 4432 | return fmt_size; |
e0001a05 NC |
4433 | } |
4434 | ||
4435 | ||
7fa3d080 BW |
4436 | static int |
4437 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4438 | { |
7fa3d080 BW |
4439 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4440 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4441 | } |
4442 | ||
4443 | ||
03aaa593 BW |
4444 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4445 | required two-byte instructions to be treated as three-byte instructions | |
4446 | for loop instruction alignment. This restriction was removed beginning | |
4447 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4448 | is that the first instruction of the loop must appear at an address that | |
4449 | does not cross a fetch boundary. */ | |
4450 | ||
4451 | static int | |
4452 | get_loop_align_size (int insn_size) | |
4453 | { | |
4454 | if (insn_size == XTENSA_UNDEFINED) | |
4455 | return xtensa_fetch_width; | |
4456 | ||
4457 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4458 | return 3; | |
4459 | ||
4460 | return insn_size; | |
4461 | } | |
4462 | ||
4463 | ||
e0001a05 NC |
4464 | /* If the next legit fragment is an end-of-loop marker, |
4465 | switch its state so it will instantiate a NOP. */ | |
4466 | ||
4467 | static void | |
1d19a770 | 4468 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4469 | { |
4470 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4471 | fragS *new_target = NULL; |
e0001a05 | 4472 | |
7b1cc377 | 4473 | if (align_targets) |
43cd72b9 BW |
4474 | { |
4475 | /* We are guaranteed there will be one of these... */ | |
4476 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4477 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4478 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4479 | next_fragP = next_fragP->fr_next; | |
4480 | ||
4481 | assert (next_fragP->fr_type == rs_machine_dependent | |
4482 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4483 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4484 | ||
4485 | /* ...and one of these. */ | |
4486 | new_target = next_fragP->fr_next; | |
4487 | while (!(new_target->fr_type == rs_machine_dependent | |
4488 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4489 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4490 | new_target = new_target->fr_next; | |
4491 | ||
4492 | assert (new_target->fr_type == rs_machine_dependent | |
4493 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4494 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4495 | } | |
43cd72b9 | 4496 | |
1d19a770 | 4497 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4498 | { |
1d19a770 BW |
4499 | if (next_fragP->fr_type == rs_machine_dependent |
4500 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4501 | { |
1d19a770 BW |
4502 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4503 | return; | |
e0001a05 | 4504 | } |
1d19a770 BW |
4505 | |
4506 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4507 | } |
4508 | } | |
4509 | ||
4510 | ||
4511 | static bfd_boolean | |
7fa3d080 | 4512 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4513 | { |
43cd72b9 | 4514 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4515 | so we have to skip until we find something legit. */ |
4516 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4517 | { | |
4518 | if (fragP->tc_frag_data.is_branch_target) | |
4519 | return TRUE; | |
4520 | if (fragP->fr_fix != 0) | |
4521 | break; | |
4522 | } | |
4523 | return FALSE; | |
4524 | } | |
4525 | ||
4526 | ||
4527 | static bfd_boolean | |
7fa3d080 | 4528 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4529 | { |
c138bc38 | 4530 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4531 | So we have to skip until we find something legit. */ |
4532 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4533 | { | |
4534 | if (fragP->tc_frag_data.is_loop_target) | |
4535 | return TRUE; | |
4536 | if (fragP->fr_fix != 0) | |
4537 | break; | |
4538 | } | |
4539 | return FALSE; | |
4540 | } | |
4541 | ||
4542 | ||
4543 | static addressT | |
7fa3d080 | 4544 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4545 | { |
4546 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4547 | xtensa_opcode next_opcode; |
e0001a05 | 4548 | |
43cd72b9 | 4549 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4550 | return 0; |
4551 | ||
43cd72b9 BW |
4552 | /* Sometimes an empty will end up here due to storage allocation issues, |
4553 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4554 | while (next_fragp->fr_fix == 0) |
4555 | next_fragp = next_fragp->fr_next; | |
4556 | ||
4557 | if (next_fragp->fr_type != rs_machine_dependent) | |
4558 | return 0; | |
4559 | ||
4560 | /* There is some implicit knowledge encoded in here. | |
4561 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4562 | been relaxed. Note that we can assume that the LOOP |
4563 | instruction is in slot 0 because loops aren't bundleable. */ | |
4564 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4565 | return get_expanded_loop_offset (next_opcode); |
4566 | ||
4567 | return 0; | |
4568 | } | |
4569 | ||
4570 | ||
4571 | /* Mark a location where we can later insert literal frags. Update | |
4572 | the section's literal_pool_loc, so subsequent literals can be | |
4573 | placed nearest to their use. */ | |
4574 | ||
4575 | static void | |
7fa3d080 | 4576 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4577 | { |
4578 | /* Any labels pointing to the current location need | |
4579 | to be adjusted to after the literal pool. */ | |
4580 | emit_state s; | |
e0001a05 | 4581 | fragS *pool_location; |
e0001a05 | 4582 | |
1f2a7e38 | 4583 | if (use_literal_section) |
43cd72b9 BW |
4584 | return; |
4585 | ||
dd49a749 BW |
4586 | /* We stash info in these frags so we can later move the literal's |
4587 | fixes into this frchain's fix list. */ | |
e0001a05 | 4588 | pool_location = frag_now; |
dd49a749 | 4589 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4590 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4591 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4592 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4593 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4594 | frag_now->tc_frag_data.lit_seg = now_seg; |
4595 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4596 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4597 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4598 | |
4599 | /* Now put a frag into the literal pool that points to this location. */ | |
4600 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4601 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4602 | frag_align (2, 0, 0); | |
4603 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4604 | |
4605 | /* Close whatever frag is there. */ | |
4606 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4607 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4608 | frag_now->tc_frag_data.literal_frag = pool_location; |
4609 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4610 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4611 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4612 | } |
4613 | ||
4614 | ||
43cd72b9 BW |
4615 | /* Build a nop of the correct size into tinsn. */ |
4616 | ||
4617 | static void | |
7fa3d080 | 4618 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4619 | { |
4620 | tinsn_init (tinsn); | |
4621 | switch (size) | |
4622 | { | |
4623 | case 2: | |
4624 | tinsn->opcode = xtensa_nop_n_opcode; | |
4625 | tinsn->ntok = 0; | |
4626 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4627 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4628 | break; | |
4629 | ||
4630 | case 3: | |
4631 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4632 | { | |
4633 | tinsn->opcode = xtensa_or_opcode; | |
4634 | set_expr_const (&tinsn->tok[0], 1); | |
4635 | set_expr_const (&tinsn->tok[1], 1); | |
4636 | set_expr_const (&tinsn->tok[2], 1); | |
4637 | tinsn->ntok = 3; | |
4638 | } | |
4639 | else | |
4640 | tinsn->opcode = xtensa_nop_opcode; | |
4641 | ||
4642 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4643 | } | |
4644 | } | |
4645 | ||
4646 | ||
e0001a05 NC |
4647 | /* Assemble a NOP of the requested size in the buffer. User must have |
4648 | allocated "buf" with at least "size" bytes. */ | |
4649 | ||
7fa3d080 | 4650 | static void |
d77b99c9 | 4651 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4652 | { |
4653 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4654 | TInsn tinsn; |
e0001a05 | 4655 | |
43cd72b9 | 4656 | build_nop (&tinsn, size); |
e0001a05 | 4657 | |
43cd72b9 BW |
4658 | if (!insnbuf) |
4659 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4660 | |
43cd72b9 | 4661 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4662 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4663 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4664 | } |
4665 | ||
4666 | ||
4667 | /* Return the number of bytes for the offset of the expanded loop | |
4668 | instruction. This should be incorporated into the relaxation | |
4669 | specification but is hard-coded here. This is used to auto-align | |
4670 | the loop instruction. It is invalid to call this function if the | |
4671 | configuration does not have loops or if the opcode is not a loop | |
4672 | opcode. */ | |
4673 | ||
4674 | static addressT | |
7fa3d080 | 4675 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4676 | { |
4677 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4678 | This MUST correspond directly to the specification of the loop | |
4679 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4680 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4681 | if (opcode == xtensa_loop_opcode) |
4682 | return 0; | |
4683 | if (opcode == xtensa_loopnez_opcode) | |
4684 | return 3; | |
4685 | if (opcode == xtensa_loopgtz_opcode) | |
4686 | return 6; | |
4687 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4688 | return 0; | |
4689 | } | |
4690 | ||
4691 | ||
7fa3d080 BW |
4692 | static fragS * |
4693 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4694 | { |
4695 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4696 | } | |
4697 | ||
4698 | ||
4699 | static void | |
7fa3d080 | 4700 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4701 | { |
4702 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4703 | } | |
4704 | ||
43cd72b9 BW |
4705 | |
4706 | /* Set frag assembly state should be called when a new frag is | |
4707 | opened and after a frag has been closed. */ | |
4708 | ||
7fa3d080 BW |
4709 | static void |
4710 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4711 | { |
4712 | if (!density_supported) | |
4713 | fragP->tc_frag_data.is_no_density = TRUE; | |
4714 | ||
4715 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4716 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4717 | "use_schedule" here. */ |
4718 | if (!directive_state[directive_transform]) | |
4719 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4720 | if (directive_state[directive_longcalls]) |
4721 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4722 | fragP->tc_frag_data.use_absolute_literals = |
4723 | directive_state[directive_absolute_literals]; | |
4724 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4725 | } | |
4726 | ||
4727 | ||
7fa3d080 BW |
4728 | static bfd_boolean |
4729 | relaxable_section (asection *sec) | |
43cd72b9 | 4730 | { |
11ac2671 BW |
4731 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4732 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4733 | } |
4734 | ||
4735 | ||
99ded152 BW |
4736 | static void |
4737 | xtensa_mark_frags_for_org (void) | |
4738 | { | |
4739 | segT *seclist; | |
4740 | ||
4741 | /* Walk over each fragment of all of the current segments. If we find | |
4742 | a .org frag in any of the segments, mark all frags prior to it as | |
4743 | "no transform", which will prevent linker optimizations from messing | |
4744 | up the .org distance. This should be done after | |
4745 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4746 | about that function trashing the data we save here. */ | |
4747 | ||
4748 | for (seclist = &stdoutput->sections; | |
4749 | seclist && *seclist; | |
4750 | seclist = &(*seclist)->next) | |
4751 | { | |
4752 | segT sec = *seclist; | |
4753 | segment_info_type *seginfo; | |
4754 | fragS *fragP; | |
4755 | flagword flags; | |
4756 | flags = bfd_get_section_flags (stdoutput, sec); | |
4757 | if (flags & SEC_DEBUGGING) | |
4758 | continue; | |
4759 | if (!(flags & SEC_ALLOC)) | |
4760 | continue; | |
4761 | ||
4762 | seginfo = seg_info (sec); | |
4763 | if (seginfo && seginfo->frchainP) | |
4764 | { | |
4765 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4766 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4767 | fragP = fragP->fr_next) | |
4768 | { | |
4769 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4770 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4771 | if (fragP->fr_subtype == RELAX_ORG) | |
4772 | { | |
4773 | while (last_fragP != fragP->fr_next) | |
4774 | { | |
4775 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4776 | last_fragP = last_fragP->fr_next; | |
4777 | } | |
4778 | } | |
4779 | } | |
4780 | } | |
4781 | } | |
4782 | } | |
4783 | ||
4784 | ||
43cd72b9 | 4785 | static void |
7fa3d080 | 4786 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4787 | { |
4788 | segT *seclist; | |
4789 | ||
4790 | /* Walk over each fragment of all of the current segments. For each | |
4791 | unmarked fragment, mark it with the same info as the previous | |
4792 | fragment. */ | |
4793 | for (seclist = &stdoutput->sections; | |
4794 | seclist && *seclist; | |
4795 | seclist = &(*seclist)->next) | |
4796 | { | |
4797 | segT sec = *seclist; | |
4798 | segment_info_type *seginfo; | |
4799 | fragS *fragP; | |
4800 | flagword flags; | |
4801 | flags = bfd_get_section_flags (stdoutput, sec); | |
4802 | if (flags & SEC_DEBUGGING) | |
4803 | continue; | |
4804 | if (!(flags & SEC_ALLOC)) | |
4805 | continue; | |
4806 | ||
4807 | seginfo = seg_info (sec); | |
4808 | if (seginfo && seginfo->frchainP) | |
4809 | { | |
4810 | fragS *last_fragP = 0; | |
4811 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4812 | fragP = fragP->fr_next) | |
4813 | { | |
4814 | if (fragP->fr_fix != 0 | |
4815 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4816 | { | |
4817 | if (last_fragP == 0) | |
4818 | { | |
4819 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4820 | _("assembly state not set for first frag in section %s"), | |
4821 | sec->name); | |
4822 | } | |
4823 | else | |
4824 | { | |
4825 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4826 | fragP->tc_frag_data.is_no_density = | |
4827 | last_fragP->tc_frag_data.is_no_density; | |
4828 | fragP->tc_frag_data.is_no_transform = | |
4829 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4830 | fragP->tc_frag_data.use_longcalls = |
4831 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4832 | fragP->tc_frag_data.use_absolute_literals = |
4833 | last_fragP->tc_frag_data.use_absolute_literals; | |
4834 | } | |
4835 | } | |
4836 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4837 | last_fragP = fragP; | |
4838 | } | |
4839 | } | |
4840 | } | |
4841 | } | |
4842 | ||
4843 | ||
4844 | static void | |
7fa3d080 BW |
4845 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4846 | asection *sec, | |
4847 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4848 | { |
4849 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4850 | segment_info_type *seginfo = seg_info (sec); | |
4851 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4852 | |
43cd72b9 | 4853 | if (flags & SEC_CODE) |
c138bc38 | 4854 | { |
43cd72b9 BW |
4855 | xtensa_isa isa = xtensa_default_isa; |
4856 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4857 | while (frag != NULL) | |
4858 | { | |
4859 | if (frag->tc_frag_data.is_branch_target) | |
4860 | { | |
4861 | int op_size; | |
664df4e4 | 4862 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4863 | xtensa_format fmt; |
4864 | ||
d77b99c9 BW |
4865 | xtensa_insnbuf_from_chars |
4866 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4867 | fmt = xtensa_format_decode (isa, insnbuf); |
4868 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4869 | branch_align = 1 << branch_align_power (sec); |
4870 | frag_addr = frag->fr_address % branch_align; | |
4871 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4872 | as_warn_where (frag->fr_file, frag->fr_line, |
4873 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4874 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4875 | } |
4876 | frag = frag->fr_next; | |
4877 | } | |
4878 | xtensa_insnbuf_free (isa, insnbuf); | |
4879 | } | |
4880 | } | |
4881 | ||
4882 | ||
4883 | static void | |
7fa3d080 BW |
4884 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4885 | asection *sec, | |
4886 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4887 | { |
4888 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4889 | segment_info_type *seginfo = seg_info (sec); | |
4890 | fragS *frag = seginfo->frchainP->frch_root; | |
4891 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4892 | |
43cd72b9 | 4893 | if (flags & SEC_CODE) |
c138bc38 | 4894 | { |
43cd72b9 BW |
4895 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4896 | while (frag != NULL) | |
4897 | { | |
4898 | if (frag->tc_frag_data.is_first_loop_insn) | |
4899 | { | |
4900 | int op_size; | |
d77b99c9 | 4901 | addressT frag_addr; |
43cd72b9 BW |
4902 | xtensa_format fmt; |
4903 | ||
d77b99c9 BW |
4904 | xtensa_insnbuf_from_chars |
4905 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4906 | fmt = xtensa_format_decode (isa, insnbuf); |
4907 | op_size = xtensa_format_length (isa, fmt); | |
4908 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4909 | ||
d77b99c9 | 4910 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4911 | as_warn_where (frag->fr_file, frag->fr_line, |
4912 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4913 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4914 | } |
4915 | frag = frag->fr_next; | |
4916 | } | |
4917 | xtensa_insnbuf_free (isa, insnbuf); | |
4918 | } | |
4919 | } | |
4920 | ||
4921 | ||
30f725a1 BW |
4922 | static int |
4923 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4924 | { |
4925 | xtensa_isa isa = xtensa_default_isa; | |
4926 | static xtensa_insnbuf insnbuf = NULL; | |
4927 | static xtensa_insnbuf slotbuf = NULL; | |
4928 | xtensa_format fmt; | |
4929 | int slot; | |
4930 | bfd_boolean alt_reloc; | |
4931 | xtensa_opcode opcode; | |
4932 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4933 | ||
4934 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4935 | if (alt_reloc) | |
4936 | as_fatal (_("unexpected fix")); | |
4937 | ||
4938 | if (!insnbuf) | |
4939 | { | |
4940 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4941 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4942 | } | |
4943 | ||
d77b99c9 | 4944 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4945 | fmt = xtensa_format_decode (isa, insnbuf); |
4946 | if (fmt == XTENSA_UNDEFINED) | |
4947 | as_fatal (_("undecodable fix")); | |
4948 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4949 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4950 | if (opcode == XTENSA_UNDEFINED) | |
4951 | as_fatal (_("undecodable fix")); | |
4952 | ||
4953 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4954 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4955 | of a CONST16 operand. */ |
43cd72b9 | 4956 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4957 | return 0; |
43cd72b9 BW |
4958 | |
4959 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4960 | get_relaxable_immed (opcode), val, | |
4961 | fixP->fx_file, fixP->fx_line); | |
4962 | ||
4963 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4964 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4965 | |
4966 | return 1; | |
43cd72b9 BW |
4967 | } |
4968 | ||
e0001a05 NC |
4969 | \f |
4970 | /* External Functions and Other GAS Hooks. */ | |
4971 | ||
4972 | const char * | |
7fa3d080 | 4973 | xtensa_target_format (void) |
e0001a05 NC |
4974 | { |
4975 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4976 | } | |
4977 | ||
4978 | ||
4979 | void | |
7fa3d080 | 4980 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4981 | { |
4982 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4983 | } | |
4984 | ||
4985 | ||
4986 | void | |
7fa3d080 | 4987 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4988 | { |
4989 | if (target_big_endian) | |
4990 | number_to_chars_bigendian (buf, val, n); | |
4991 | else | |
4992 | number_to_chars_littleendian (buf, val, n); | |
4993 | } | |
4994 | ||
4995 | ||
4996 | /* This function is called once, at assembler startup time. It should | |
4997 | set up all the tables, etc. that the MD part of the assembler will | |
4998 | need. */ | |
4999 | ||
5000 | void | |
7fa3d080 | 5001 | md_begin (void) |
e0001a05 NC |
5002 | { |
5003 | segT current_section = now_seg; | |
5004 | int current_subsec = now_subseg; | |
5005 | xtensa_isa isa; | |
5006 | ||
43cd72b9 | 5007 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5008 | isa = xtensa_default_isa; |
e0001a05 | 5009 | |
43cd72b9 BW |
5010 | linkrelax = 1; |
5011 | ||
74869ac7 | 5012 | /* Set up the literal sections. */ |
e0001a05 | 5013 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5014 | |
5015 | subseg_set (current_section, current_subsec); | |
5016 | ||
43cd72b9 BW |
5017 | xg_init_vinsn (&cur_vinsn); |
5018 | ||
e0001a05 NC |
5019 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
5020 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5021 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5022 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5023 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5024 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5025 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5026 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5027 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5028 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5029 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5030 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5031 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5032 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5033 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5034 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 5035 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5036 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5037 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5038 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5039 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5040 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5041 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5042 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5043 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5044 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5045 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5046 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5047 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5048 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
5049 | |
5050 | init_op_placement_info_table (); | |
5051 | ||
5052 | /* Set up the assembly state. */ | |
5053 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5054 | xtensa_set_frag_assembly_state (frag_now); | |
5055 | } | |
5056 | ||
5057 | ||
5058 | /* TC_INIT_FIX_DATA hook */ | |
5059 | ||
5060 | void | |
7fa3d080 | 5061 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5062 | { |
5063 | x->tc_fix_data.slot = 0; | |
5064 | x->tc_fix_data.X_add_symbol = NULL; | |
5065 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5066 | } |
5067 | ||
5068 | ||
5069 | /* tc_frob_label hook */ | |
5070 | ||
5071 | void | |
7fa3d080 | 5072 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5073 | { |
3ea38ac2 BW |
5074 | float freq; |
5075 | ||
5076 | if (cur_vinsn.inside_bundle) | |
5077 | { | |
5078 | as_bad (_("labels are not valid inside bundles")); | |
5079 | return; | |
5080 | } | |
5081 | ||
5082 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5083 | |
43cd72b9 BW |
5084 | /* Since the label was already attached to a frag associated with the |
5085 | previous basic block, it now needs to be reset to the current frag. */ | |
5086 | symbol_set_frag (sym, frag_now); | |
5087 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5088 | ||
82e7541d BW |
5089 | if (generating_literals) |
5090 | xtensa_add_literal_sym (sym); | |
5091 | else | |
5092 | xtensa_add_insn_label (sym); | |
5093 | ||
7b1cc377 BW |
5094 | if (symbol_get_tc (sym)->is_loop_target) |
5095 | { | |
5096 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5097 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5098 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5099 | ||
5100 | xtensa_set_frag_assembly_state (frag_now); | |
5101 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5102 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5103 | ||
5104 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5105 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5106 | } |
e0001a05 NC |
5107 | |
5108 | /* No target aligning in the absolute section. */ | |
61846f28 | 5109 | if (now_seg != absolute_section |
43cd72b9 | 5110 | && do_align_targets () |
61846f28 | 5111 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5112 | && !generating_literals) |
5113 | { | |
43cd72b9 BW |
5114 | xtensa_set_frag_assembly_state (frag_now); |
5115 | ||
43cd72b9 | 5116 | frag_var (rs_machine_dependent, |
7b1cc377 | 5117 | 0, (int) freq, |
e0001a05 NC |
5118 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5119 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5120 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5121 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5122 | } |
5123 | ||
5124 | /* We need to mark the following properties even if we aren't aligning. */ | |
5125 | ||
5126 | /* If the label is already known to be a branch target, i.e., a | |
5127 | forward branch, mark the frag accordingly. Backward branches | |
5128 | are handled by xg_add_branch_and_loop_targets. */ | |
5129 | if (symbol_get_tc (sym)->is_branch_target) | |
5130 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5131 | ||
5132 | /* Loops only go forward, so they can be identified here. */ | |
5133 | if (symbol_get_tc (sym)->is_loop_target) | |
5134 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5135 | |
5136 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5137 | } |
5138 | ||
5139 | ||
5140 | /* tc_unrecognized_line hook */ | |
5141 | ||
5142 | int | |
7fa3d080 | 5143 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5144 | { |
5145 | switch (ch) | |
5146 | { | |
5147 | case '{' : | |
5148 | if (cur_vinsn.inside_bundle == 0) | |
5149 | { | |
5150 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5151 | when using --gstabs. Temporarily disable debug info. */ | |
5152 | generate_lineno_debug (); | |
5153 | if (debug_type == DEBUG_STABS) | |
5154 | { | |
5155 | xt_saved_debug_type = debug_type; | |
5156 | debug_type = DEBUG_NONE; | |
5157 | } | |
82e7541d | 5158 | |
43cd72b9 BW |
5159 | cur_vinsn.inside_bundle = 1; |
5160 | } | |
5161 | else | |
5162 | { | |
5163 | as_bad (_("extra opening brace")); | |
5164 | return 0; | |
5165 | } | |
5166 | break; | |
82e7541d | 5167 | |
43cd72b9 BW |
5168 | case '}' : |
5169 | if (cur_vinsn.inside_bundle) | |
5170 | finish_vinsn (&cur_vinsn); | |
5171 | else | |
5172 | { | |
5173 | as_bad (_("extra closing brace")); | |
5174 | return 0; | |
5175 | } | |
5176 | break; | |
5177 | default: | |
5178 | as_bad (_("syntax error")); | |
5179 | return 0; | |
e0001a05 | 5180 | } |
43cd72b9 | 5181 | return 1; |
e0001a05 NC |
5182 | } |
5183 | ||
5184 | ||
5185 | /* md_flush_pending_output hook */ | |
5186 | ||
5187 | void | |
7fa3d080 | 5188 | xtensa_flush_pending_output (void) |
e0001a05 | 5189 | { |
a3582eee BW |
5190 | /* This line fixes a bug where automatically generated gstabs info |
5191 | separates a function label from its entry instruction, ending up | |
5192 | with the literal position between the function label and the entry | |
5193 | instruction and crashing code. It only happens with --gstabs and | |
5194 | --text-section-literals, and when several other obscure relaxation | |
5195 | conditions are met. */ | |
5196 | if (outputting_stabs_line_debug) | |
5197 | return; | |
5198 | ||
43cd72b9 BW |
5199 | if (cur_vinsn.inside_bundle) |
5200 | as_bad (_("missing closing brace")); | |
5201 | ||
e0001a05 NC |
5202 | /* If there is a non-zero instruction fragment, close it. */ |
5203 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5204 | { | |
5205 | frag_wane (frag_now); | |
5206 | frag_new (0); | |
43cd72b9 | 5207 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5208 | } |
5209 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5210 | |
5211 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5212 | } |
5213 | ||
5214 | ||
43cd72b9 BW |
5215 | /* We had an error while parsing an instruction. The string might look |
5216 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5217 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5218 | and the num_slots field will grow past the end of the array of slots, | |
5219 | and bad things happen. */ | |
5220 | ||
5221 | static void | |
7fa3d080 | 5222 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5223 | { |
5224 | if (cur_vinsn.inside_bundle) | |
5225 | { | |
5226 | if (*input_line_pointer == '}' | |
5227 | || *(input_line_pointer - 1) == '}' | |
5228 | || *(input_line_pointer - 2) == '}') | |
5229 | xg_clear_vinsn (&cur_vinsn); | |
5230 | } | |
5231 | } | |
5232 | ||
5233 | ||
e0001a05 | 5234 | void |
7fa3d080 | 5235 | md_assemble (char *str) |
e0001a05 NC |
5236 | { |
5237 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5238 | char *opname; |
e0001a05 NC |
5239 | unsigned opnamelen; |
5240 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5241 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5242 | int num_args; |
e0001a05 | 5243 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5244 | |
e0001a05 NC |
5245 | tinsn_init (&orig_insn); |
5246 | ||
5247 | /* Split off the opcode. */ | |
5248 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5249 | opname = xmalloc (opnamelen + 1); | |
5250 | memcpy (opname, str, opnamelen); | |
5251 | opname[opnamelen] = '\0'; | |
5252 | ||
5253 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5254 | if (num_args == -1) | |
5255 | { | |
5256 | as_bad (_("syntax error")); | |
5257 | return; | |
5258 | } | |
5259 | ||
5260 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5261 | return; | |
5262 | ||
5263 | /* Check for an underbar prefix. */ | |
5264 | if (*opname == '_') | |
5265 | { | |
5266 | has_underbar = TRUE; | |
5267 | opname += 1; | |
5268 | } | |
5269 | ||
5270 | orig_insn.insn_type = ITYPE_INSN; | |
5271 | orig_insn.ntok = 0; | |
43cd72b9 | 5272 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5273 | |
5274 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5275 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5276 | { | |
43cd72b9 BW |
5277 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5278 | if (fmt == XTENSA_UNDEFINED) | |
5279 | { | |
5280 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5281 | error_reset_cur_vinsn (); | |
5282 | return; | |
5283 | } | |
5284 | if (!cur_vinsn.inside_bundle) | |
5285 | { | |
5286 | as_bad (_("format names only valid inside bundles")); | |
5287 | error_reset_cur_vinsn (); | |
5288 | return; | |
5289 | } | |
5290 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5291 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5292 | opname); | |
5293 | cur_vinsn.format = fmt; | |
5294 | free (has_underbar ? opname - 1 : opname); | |
5295 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5296 | return; |
5297 | } | |
5298 | ||
e0001a05 NC |
5299 | /* Parse the arguments. */ |
5300 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5301 | { | |
5302 | as_bad (_("syntax error")); | |
43cd72b9 | 5303 | error_reset_cur_vinsn (); |
e0001a05 NC |
5304 | return; |
5305 | } | |
5306 | ||
5307 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5308 | free (has_underbar ? opname - 1 : opname); | |
5309 | opname = 0; | |
5310 | while (num_args-- > 0) | |
5311 | free (arg_strings[num_args]); | |
5312 | ||
43cd72b9 BW |
5313 | /* Get expressions for invisible operands. */ |
5314 | if (get_invisible_operands (&orig_insn)) | |
5315 | { | |
5316 | error_reset_cur_vinsn (); | |
5317 | return; | |
5318 | } | |
5319 | ||
e0001a05 NC |
5320 | /* Check for the right number and type of arguments. */ |
5321 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5322 | { |
43cd72b9 BW |
5323 | error_reset_cur_vinsn (); |
5324 | return; | |
e0001a05 NC |
5325 | } |
5326 | ||
b224e962 BW |
5327 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5328 | spread across multiple input lines and individual instructions may be | |
5329 | moved around in some cases. */ | |
5330 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5331 | dwarf2_where (&orig_insn.debug_line); | |
5332 | dwarf2_consume_line_info (); | |
c138bc38 | 5333 | |
43cd72b9 BW |
5334 | xg_add_branch_and_loop_targets (&orig_insn); |
5335 | ||
431ad2d0 BW |
5336 | /* Check that immediate value for ENTRY is >= 16. */ |
5337 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5338 | { |
431ad2d0 BW |
5339 | expressionS *exp = &orig_insn.tok[2]; |
5340 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5341 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5342 | } |
5343 | ||
e0001a05 | 5344 | /* Finish it off: |
43cd72b9 BW |
5345 | assemble_tokens (opcode, tok, ntok); |
5346 | expand the tokens from the orig_insn into the | |
5347 | stack of instructions that will not expand | |
e0001a05 | 5348 | unless required at relaxation time. */ |
e0001a05 | 5349 | |
43cd72b9 BW |
5350 | if (!cur_vinsn.inside_bundle) |
5351 | emit_single_op (&orig_insn); | |
5352 | else /* We are inside a bundle. */ | |
e0001a05 | 5353 | { |
43cd72b9 BW |
5354 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5355 | cur_vinsn.num_slots++; | |
5356 | if (*input_line_pointer == '}' | |
5357 | || *(input_line_pointer - 1) == '}' | |
5358 | || *(input_line_pointer - 2) == '}') | |
5359 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5360 | } |
5361 | ||
43cd72b9 BW |
5362 | /* We've just emitted a new instruction so clear the list of labels. */ |
5363 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5364 | } |
5365 | ||
5366 | ||
43cd72b9 | 5367 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5368 | |
43cd72b9 BW |
5369 | /* For a .align directive, we mark the previous block with the alignment |
5370 | information. This will be placed in the object file in the | |
5371 | property section corresponding to this section. */ | |
e0001a05 | 5372 | |
43cd72b9 | 5373 | void |
7fa3d080 | 5374 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5375 | { |
5376 | if (linkrelax | |
b08b5071 | 5377 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5378 | && (fragP->fr_type == rs_align |
5379 | || fragP->fr_type == rs_align_code) | |
5380 | && fragP->fr_address + fragP->fr_fix > 0 | |
5381 | && fragP->fr_offset > 0 | |
5382 | && now_seg != bss_section) | |
e0001a05 | 5383 | { |
43cd72b9 BW |
5384 | fragP->tc_frag_data.is_align = TRUE; |
5385 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5386 | } |
5387 | ||
43cd72b9 | 5388 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5389 | { |
43cd72b9 BW |
5390 | int count; |
5391 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5392 | if (count != 0) | |
c138bc38 | 5393 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5394 | _("unaligned entry instruction")); |
e0001a05 | 5395 | } |
99ded152 BW |
5396 | |
5397 | if (linkrelax && fragP->fr_type == rs_org) | |
5398 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5399 | } |
43cd72b9 | 5400 | |
e0001a05 NC |
5401 | |
5402 | /* TC_FRAG_INIT hook */ | |
5403 | ||
5404 | void | |
7fa3d080 | 5405 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5406 | { |
43cd72b9 | 5407 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5408 | } |
5409 | ||
5410 | ||
5411 | symbolS * | |
7fa3d080 | 5412 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5413 | { |
5414 | return NULL; | |
5415 | } | |
5416 | ||
5417 | ||
5418 | /* Round up a section size to the appropriate boundary. */ | |
5419 | ||
5420 | valueT | |
7fa3d080 | 5421 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5422 | { |
5423 | return size; /* Byte alignment is fine. */ | |
5424 | } | |
5425 | ||
5426 | ||
5427 | long | |
7fa3d080 | 5428 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5429 | { |
5430 | char *insn_p; | |
5431 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5432 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5433 | int opnum; |
43cd72b9 | 5434 | uint32 opnd_value; |
e0001a05 | 5435 | xtensa_opcode opcode; |
43cd72b9 BW |
5436 | xtensa_format fmt; |
5437 | int slot; | |
e0001a05 NC |
5438 | xtensa_isa isa = xtensa_default_isa; |
5439 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5440 | bfd_boolean alt_reloc; |
e0001a05 | 5441 | |
e0001a05 | 5442 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5443 | return 0; |
e0001a05 | 5444 | |
1bbb5f21 BW |
5445 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5446 | return addr; | |
5447 | ||
e0001a05 | 5448 | if (!insnbuf) |
43cd72b9 BW |
5449 | { |
5450 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5451 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5452 | } | |
e0001a05 NC |
5453 | |
5454 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5455 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5456 | fmt = xtensa_format_decode (isa, insnbuf); |
5457 | ||
5458 | if (fmt == XTENSA_UNDEFINED) | |
5459 | as_fatal (_("bad instruction format")); | |
5460 | ||
5461 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5462 | as_fatal (_("invalid relocation")); | |
5463 | ||
5464 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5465 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5466 | ||
30f725a1 BW |
5467 | /* Check for "alternate" relocations (operand not specified). None |
5468 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5469 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5470 | { | |
5471 | if (opcode != xtensa_l32r_opcode | |
5472 | && opcode != xtensa_const16_opcode) | |
5473 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5474 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5475 | return 0; |
e0001a05 NC |
5476 | } |
5477 | ||
43cd72b9 BW |
5478 | opnum = get_relaxable_immed (opcode); |
5479 | opnd_value = 0; | |
5480 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5481 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5482 | { |
5483 | as_bad_where (fixP->fx_file, | |
5484 | fixP->fx_line, | |
5485 | _("invalid relocation for operand %d of '%s'"), | |
5486 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5487 | return 0; |
e0001a05 | 5488 | } |
43cd72b9 BW |
5489 | return 0 - opnd_value; |
5490 | } | |
5491 | ||
5492 | ||
5493 | /* TC_FORCE_RELOCATION hook */ | |
5494 | ||
5495 | int | |
7fa3d080 | 5496 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5497 | { |
5498 | switch (fix->fx_r_type) | |
30f725a1 BW |
5499 | { |
5500 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5501 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5502 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5503 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5504 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5505 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5506 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5507 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5508 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5509 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5510 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5511 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5512 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5513 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5514 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5515 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5516 | return 1; |
5517 | default: | |
5518 | break; | |
e0001a05 NC |
5519 | } |
5520 | ||
43cd72b9 BW |
5521 | if (linkrelax && fix->fx_addsy |
5522 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5523 | return 1; | |
5524 | ||
5525 | return generic_force_reloc (fix); | |
5526 | } | |
5527 | ||
5528 | ||
30f725a1 BW |
5529 | /* TC_VALIDATE_FIX_SUB hook */ |
5530 | ||
5531 | int | |
5532 | xtensa_validate_fix_sub (fixS *fix) | |
5533 | { | |
5534 | segT add_symbol_segment, sub_symbol_segment; | |
5535 | ||
5536 | /* The difference of two symbols should be resolved by the assembler when | |
5537 | linkrelax is not set. If the linker may relax the section containing | |
5538 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5539 | the linker knows to adjust the difference value. */ | |
5540 | if (!linkrelax || fix->fx_addsy == NULL) | |
5541 | return 0; | |
5542 | ||
5543 | /* Make sure both symbols are in the same segment, and that segment is | |
5544 | "normal" and relaxable. If the segment is not "normal", then the | |
5545 | fix is not valid. If the segment is not "relaxable", then the fix | |
5546 | should have been handled earlier. */ | |
5547 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5548 | if (! SEG_NORMAL (add_symbol_segment) || | |
5549 | ! relaxable_section (add_symbol_segment)) | |
5550 | return 0; | |
5551 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5552 | return (sub_symbol_segment == add_symbol_segment); | |
5553 | } | |
5554 | ||
5555 | ||
43cd72b9 BW |
5556 | /* NO_PSEUDO_DOT hook */ |
5557 | ||
5558 | /* This function has nothing to do with pseudo dots, but this is the | |
5559 | nearest macro to where the check needs to take place. FIXME: This | |
5560 | seems wrong. */ | |
5561 | ||
5562 | bfd_boolean | |
7fa3d080 | 5563 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5564 | { |
5565 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5566 | as_bad (_("directives are not valid inside bundles")); | |
5567 | ||
5568 | /* This function must always return FALSE because it is called via a | |
5569 | macro that has nothing to do with bundling. */ | |
5570 | return FALSE; | |
e0001a05 NC |
5571 | } |
5572 | ||
5573 | ||
43cd72b9 | 5574 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5575 | |
5576 | void | |
7fa3d080 | 5577 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5578 | { |
43cd72b9 BW |
5579 | /* Set up the assembly state. */ |
5580 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5581 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5582 | } |
5583 | ||
5584 | ||
5585 | /* tc_fix_adjustable hook */ | |
5586 | ||
5587 | bfd_boolean | |
7fa3d080 | 5588 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5589 | { |
43cd72b9 BW |
5590 | /* An offset is not allowed in combination with the difference of two |
5591 | symbols, but that cannot be easily detected after a local symbol | |
5592 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5593 | an fix will not be adjusted. */ | |
5594 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5595 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5596 | return 0; | |
5597 | ||
e0001a05 NC |
5598 | /* We need the symbol name for the VTABLE entries. */ |
5599 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5600 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5601 | return 0; | |
5602 | ||
5603 | return 1; | |
5604 | } | |
5605 | ||
5606 | ||
6a7eedfe BW |
5607 | /* tc_symbol_new_hook */ |
5608 | ||
5609 | symbolS *expr_symbols = NULL; | |
5610 | ||
5611 | void | |
5612 | xtensa_symbol_new_hook (symbolS *sym) | |
5613 | { | |
5614 | if (S_GET_SEGMENT (sym) == expr_section) | |
5615 | { | |
5616 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5617 | expr_symbols = sym; | |
5618 | } | |
5619 | } | |
5620 | ||
5621 | ||
e0001a05 | 5622 | void |
55cf6793 | 5623 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5624 | { |
30f725a1 | 5625 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5626 | valueT val = 0; |
30f725a1 | 5627 | |
e7da6241 BW |
5628 | /* Subtracted symbols are only allowed for a few relocation types, and |
5629 | unless linkrelax is enabled, they should not make it to this point. */ | |
5630 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5631 | || fixP->fx_r_type == BFD_RELOC_16 | |
5632 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5633 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5634 | ||
30f725a1 | 5635 | switch (fixP->fx_r_type) |
e0001a05 | 5636 | { |
1bbb5f21 | 5637 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5638 | case BFD_RELOC_32: |
5639 | case BFD_RELOC_16: | |
5640 | case BFD_RELOC_8: | |
e7da6241 | 5641 | if (fixP->fx_subsy) |
30f725a1 BW |
5642 | { |
5643 | switch (fixP->fx_r_type) | |
5644 | { | |
5645 | case BFD_RELOC_8: | |
5646 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5647 | break; | |
5648 | case BFD_RELOC_16: | |
5649 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5650 | break; | |
5651 | case BFD_RELOC_32: | |
5652 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5653 | break; | |
5654 | default: | |
5655 | break; | |
5656 | } | |
e0001a05 | 5657 | |
30f725a1 BW |
5658 | /* An offset is only allowed when it results from adjusting a |
5659 | local symbol into a section-relative offset. If the offset | |
5660 | came from the original expression, tc_fix_adjustable will have | |
5661 | prevented the fix from being converted to a section-relative | |
5662 | form so that we can flag the error here. */ | |
5663 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5664 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5665 | _("cannot represent subtraction with an offset")); | |
5666 | ||
5667 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5668 | - S_GET_VALUE (fixP->fx_subsy)); | |
5669 | ||
5670 | /* The difference value gets written out, and the DIFF reloc | |
5671 | identifies the address of the subtracted symbol (i.e., the one | |
5672 | with the lowest address). */ | |
5673 | *valP = val; | |
5674 | fixP->fx_offset -= val; | |
5675 | fixP->fx_subsy = NULL; | |
5676 | } | |
5677 | else if (! fixP->fx_addsy) | |
e0001a05 | 5678 | { |
30f725a1 | 5679 | val = *valP; |
e0001a05 | 5680 | fixP->fx_done = 1; |
30f725a1 | 5681 | } |
d47d412e BW |
5682 | /* fall through */ |
5683 | ||
5684 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5685 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5686 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5687 | break; | |
e0001a05 | 5688 | |
30f725a1 BW |
5689 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5690 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5691 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5692 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5693 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5694 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5695 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5696 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5697 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5698 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5699 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5700 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5701 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5702 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5703 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5704 | if (linkrelax) | |
5705 | { | |
5706 | /* Write the tentative value of a PC-relative relocation to a | |
5707 | local symbol into the instruction. The value will be ignored | |
5708 | by the linker, and it makes the object file disassembly | |
5709 | readable when all branch targets are encoded in relocations. */ | |
5710 | ||
5711 | assert (fixP->fx_addsy); | |
20ee54e8 | 5712 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5713 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5714 | { | |
5715 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5716 | - md_pcrel_from (fixP)); | |
5717 | (void) xg_apply_fix_value (fixP, val); | |
5718 | } | |
5719 | } | |
5720 | else if (! fixP->fx_addsy) | |
5721 | { | |
5722 | val = *valP; | |
5723 | if (xg_apply_fix_value (fixP, val)) | |
5724 | fixP->fx_done = 1; | |
5725 | } | |
5726 | break; | |
e0001a05 | 5727 | |
30f725a1 BW |
5728 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5729 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5730 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5731 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5732 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5733 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5734 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5735 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5736 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5737 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5738 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5739 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5740 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5741 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5742 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5743 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5744 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5745 | break; | |
e0001a05 | 5746 | |
30f725a1 BW |
5747 | case BFD_RELOC_VTABLE_INHERIT: |
5748 | case BFD_RELOC_VTABLE_ENTRY: | |
5749 | fixP->fx_done = 0; | |
5750 | break; | |
e0001a05 | 5751 | |
30f725a1 BW |
5752 | default: |
5753 | as_bad (_("unhandled local relocation fix %s"), | |
5754 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5755 | } |
5756 | } | |
5757 | ||
5758 | ||
5759 | char * | |
7fa3d080 | 5760 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5761 | { |
499ac353 | 5762 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5763 | } |
5764 | ||
5765 | ||
5766 | int | |
7fa3d080 | 5767 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5768 | { |
34e41783 | 5769 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5770 | } |
5771 | ||
5772 | ||
5773 | /* Translate internal representation of relocation info to BFD target | |
5774 | format. */ | |
5775 | ||
5776 | arelent * | |
30f725a1 | 5777 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5778 | { |
5779 | arelent *reloc; | |
5780 | ||
5781 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5782 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5783 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5784 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5785 | ||
5786 | /* Make sure none of our internal relocations make it this far. | |
5787 | They'd better have been fully resolved by this point. */ | |
5788 | assert ((int) fixp->fx_r_type > 0); | |
5789 | ||
30f725a1 | 5790 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5791 | |
e0001a05 NC |
5792 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5793 | if (reloc->howto == NULL) | |
5794 | { | |
5795 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5796 | _("cannot represent `%s' relocation in object file"), | |
5797 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5798 | free (reloc->sym_ptr_ptr); |
5799 | free (reloc); | |
e0001a05 NC |
5800 | return NULL; |
5801 | } | |
5802 | ||
5803 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 5804 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 5805 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 5806 | |
e0001a05 NC |
5807 | return reloc; |
5808 | } | |
5809 | ||
7fa3d080 BW |
5810 | \f |
5811 | /* Checks for resource conflicts between instructions. */ | |
5812 | ||
c138bc38 BW |
5813 | /* The func unit stuff could be implemented as bit-vectors rather |
5814 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5815 | slow, we will switch it. */ |
5816 | ||
c138bc38 | 5817 | resource_table * |
7fa3d080 BW |
5818 | new_resource_table (void *data, |
5819 | int cycles, | |
5820 | int nu, | |
5821 | unit_num_copies_func uncf, | |
5822 | opcode_num_units_func onuf, | |
5823 | opcode_funcUnit_use_unit_func ouuf, | |
5824 | opcode_funcUnit_use_stage_func ousf) | |
5825 | { | |
5826 | int i; | |
5827 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5828 | rt->data = data; | |
5829 | rt->cycles = cycles; | |
5830 | rt->allocated_cycles = cycles; | |
5831 | rt->num_units = nu; | |
5832 | rt->unit_num_copies = uncf; | |
5833 | rt->opcode_num_units = onuf; | |
5834 | rt->opcode_unit_use = ouuf; | |
5835 | rt->opcode_unit_stage = ousf; | |
5836 | ||
0bf60745 | 5837 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5838 | for (i = 0; i < cycles; i++) |
0bf60745 | 5839 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5840 | |
5841 | return rt; | |
5842 | } | |
5843 | ||
5844 | ||
c138bc38 | 5845 | void |
7fa3d080 BW |
5846 | clear_resource_table (resource_table *rt) |
5847 | { | |
5848 | int i, j; | |
5849 | for (i = 0; i < rt->allocated_cycles; i++) | |
5850 | for (j = 0; j < rt->num_units; j++) | |
5851 | rt->units[i][j] = 0; | |
5852 | } | |
5853 | ||
5854 | ||
5855 | /* We never shrink it, just fake it into thinking so. */ | |
5856 | ||
c138bc38 | 5857 | void |
7fa3d080 BW |
5858 | resize_resource_table (resource_table *rt, int cycles) |
5859 | { | |
5860 | int i, old_cycles; | |
5861 | ||
5862 | rt->cycles = cycles; | |
5863 | if (cycles <= rt->allocated_cycles) | |
5864 | return; | |
5865 | ||
5866 | old_cycles = rt->allocated_cycles; | |
5867 | rt->allocated_cycles = cycles; | |
5868 | ||
0bf60745 BW |
5869 | rt->units = xrealloc (rt->units, |
5870 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5871 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5872 | rt->units[i] = xrealloc (rt->units[i], |
5873 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5874 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5875 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5876 | } |
5877 | ||
5878 | ||
c138bc38 | 5879 | bfd_boolean |
7fa3d080 BW |
5880 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5881 | { | |
5882 | int i; | |
5883 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5884 | ||
c138bc38 | 5885 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5886 | { |
5887 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5888 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5889 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5890 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5891 | if (copies_in_use >= copies) | |
5892 | return FALSE; | |
5893 | } | |
5894 | return TRUE; | |
5895 | } | |
7fa3d080 | 5896 | |
c138bc38 BW |
5897 | |
5898 | void | |
7fa3d080 BW |
5899 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5900 | { | |
5901 | int i; | |
5902 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5903 | ||
c138bc38 | 5904 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5905 | { |
5906 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5907 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5908 | /* Note that this allows resources to be oversubscribed. That's |
5909 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5910 | resources_available reports when a resource is over-subscribed, |
5911 | so it's easy to tell. */ | |
5912 | rt->units[stage + cycle][unit]++; | |
5913 | } | |
5914 | } | |
5915 | ||
5916 | ||
c138bc38 | 5917 | void |
7fa3d080 BW |
5918 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5919 | { | |
5920 | int i; | |
5921 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5922 | ||
c138bc38 | 5923 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5924 | { |
5925 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5926 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5927 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5928 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5929 | } |
5930 | } | |
c138bc38 | 5931 | |
7fa3d080 BW |
5932 | |
5933 | /* Wrapper functions make parameterized resource reservation | |
5934 | more convenient. */ | |
5935 | ||
c138bc38 | 5936 | int |
7fa3d080 BW |
5937 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5938 | { | |
5939 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5940 | return use->unit; |
7fa3d080 BW |
5941 | } |
5942 | ||
5943 | ||
c138bc38 | 5944 | int |
7fa3d080 BW |
5945 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5946 | { | |
5947 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5948 | return use->stage; | |
5949 | } | |
5950 | ||
5951 | ||
5952 | /* Note that this function does not check issue constraints, but | |
5953 | solely whether the hardware is available to execute the given | |
c138bc38 | 5954 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5955 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5956 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5957 | |
5958 | static bfd_boolean | |
5959 | resources_conflict (vliw_insn *vinsn) | |
5960 | { | |
5961 | int i; | |
5962 | static resource_table *rt = NULL; | |
5963 | ||
5964 | /* This is the most common case by far. Optimize it. */ | |
5965 | if (vinsn->num_slots == 1) | |
5966 | return FALSE; | |
43cd72b9 | 5967 | |
c138bc38 | 5968 | if (rt == NULL) |
7fa3d080 BW |
5969 | { |
5970 | xtensa_isa isa = xtensa_default_isa; | |
5971 | rt = new_resource_table | |
5972 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5973 | xtensa_isa_num_funcUnits (isa), | |
5974 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5975 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5976 | opcode_funcUnit_use_unit, | |
5977 | opcode_funcUnit_use_stage); | |
5978 | } | |
43cd72b9 | 5979 | |
7fa3d080 | 5980 | clear_resource_table (rt); |
43cd72b9 | 5981 | |
7fa3d080 BW |
5982 | for (i = 0; i < vinsn->num_slots; i++) |
5983 | { | |
5984 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5985 | return TRUE; | |
5986 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5987 | } | |
e0001a05 | 5988 | |
7fa3d080 BW |
5989 | return FALSE; |
5990 | } | |
e0001a05 | 5991 | |
7fa3d080 BW |
5992 | \f |
5993 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5994 | |
7fa3d080 BW |
5995 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5996 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5997 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5998 | |
5999 | ||
43cd72b9 BW |
6000 | /* We have reached the end of a bundle; emit into the frag. */ |
6001 | ||
e0001a05 | 6002 | static void |
7fa3d080 | 6003 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6004 | { |
43cd72b9 BW |
6005 | IStack slotstack; |
6006 | int i; | |
6007 | char *file_name; | |
d77b99c9 | 6008 | unsigned line; |
e0001a05 | 6009 | |
43cd72b9 | 6010 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6011 | { |
6012 | xg_clear_vinsn (vinsn); | |
6013 | return; | |
6014 | } | |
43cd72b9 BW |
6015 | |
6016 | /* First, find a format that works. */ | |
6017 | if (vinsn->format == XTENSA_UNDEFINED) | |
6018 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6019 | ||
6020 | if (vinsn->format == XTENSA_UNDEFINED) | |
6021 | { | |
6022 | as_where (&file_name, &line); | |
6023 | as_bad_where (file_name, line, | |
6024 | _("couldn't find a valid instruction format")); | |
6025 | fprintf (stderr, _(" ops were: ")); | |
6026 | for (i = 0; i < vinsn->num_slots; i++) | |
6027 | fprintf (stderr, _(" %s;"), | |
6028 | xtensa_opcode_name (xtensa_default_isa, | |
6029 | vinsn->slots[i].opcode)); | |
6030 | fprintf (stderr, _("\n")); | |
6031 | xg_clear_vinsn (vinsn); | |
6032 | return; | |
6033 | } | |
6034 | ||
6035 | if (vinsn->num_slots | |
6036 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6037 | { |
43cd72b9 BW |
6038 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6039 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6040 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6041 | vinsn->num_slots); | |
6042 | xg_clear_vinsn (vinsn); | |
6043 | return; | |
6044 | } | |
e0001a05 | 6045 | |
c138bc38 | 6046 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6047 | { |
6048 | as_where (&file_name, &line); | |
6049 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6050 | fprintf (stderr, " ops were: "); | |
6051 | for (i = 0; i < vinsn->num_slots; i++) | |
6052 | fprintf (stderr, " %s;", | |
6053 | xtensa_opcode_name (xtensa_default_isa, | |
6054 | vinsn->slots[i].opcode)); | |
6055 | fprintf (stderr, "\n"); | |
6056 | xg_clear_vinsn (vinsn); | |
6057 | return; | |
6058 | } | |
6059 | ||
6060 | for (i = 0; i < vinsn->num_slots; i++) | |
6061 | { | |
6062 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6063 | { |
43cd72b9 BW |
6064 | symbolS *lit_sym = NULL; |
6065 | int j; | |
6066 | bfd_boolean e = FALSE; | |
6067 | bfd_boolean saved_density = density_supported; | |
6068 | ||
6069 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6070 | if (vinsn->num_slots > 1) | |
6071 | density_supported = FALSE; | |
6072 | ||
6073 | istack_init (&slotstack); | |
6074 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6075 | { |
43cd72b9 BW |
6076 | vinsn->slots[i].opcode = |
6077 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6078 | vinsn->format, i); | |
6079 | vinsn->slots[i].ntok = 0; | |
6080 | } | |
e0001a05 | 6081 | |
43cd72b9 BW |
6082 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6083 | { | |
6084 | e = TRUE; | |
6085 | continue; | |
e0001a05 | 6086 | } |
e0001a05 | 6087 | |
43cd72b9 | 6088 | density_supported = saved_density; |
e0001a05 | 6089 | |
43cd72b9 BW |
6090 | if (e) |
6091 | { | |
6092 | xg_clear_vinsn (vinsn); | |
6093 | return; | |
6094 | } | |
e0001a05 | 6095 | |
0fa77c95 | 6096 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6097 | { |
6098 | TInsn *insn = &slotstack.insn[j]; | |
6099 | if (insn->insn_type == ITYPE_LITERAL) | |
6100 | { | |
6101 | assert (lit_sym == NULL); | |
6102 | lit_sym = xg_assemble_literal (insn); | |
6103 | } | |
6104 | else | |
6105 | { | |
0fa77c95 | 6106 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6107 | if (lit_sym) |
6108 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6109 | if (j != slotstack.ninsn - 1) |
6110 | emit_single_op (insn); | |
43cd72b9 BW |
6111 | } |
6112 | } | |
6113 | ||
6114 | if (vinsn->num_slots > 1) | |
6115 | { | |
6116 | if (opcode_fits_format_slot | |
6117 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6118 | vinsn->format, i)) | |
6119 | { | |
6120 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6121 | } | |
6122 | else | |
6123 | { | |
b2d179be | 6124 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6125 | if (vinsn->format == XTENSA_UNDEFINED) |
6126 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6127 | else | |
c138bc38 | 6128 | vinsn->slots[i].opcode |
43cd72b9 BW |
6129 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6130 | vinsn->format, i); | |
6131 | ||
6132 | vinsn->slots[i].ntok = 0; | |
6133 | } | |
6134 | } | |
6135 | else | |
6136 | { | |
6137 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6138 | vinsn->format = XTENSA_UNDEFINED; | |
6139 | } | |
6140 | } | |
6141 | } | |
6142 | ||
6143 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6144 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6145 | { |
6146 | as_where (&file_name, &line); | |
6147 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6148 | fprintf (stderr, " ops were: "); | |
6149 | for (i = 0; i < vinsn->num_slots; i++) | |
6150 | fprintf (stderr, " %s;", | |
6151 | xtensa_opcode_name (xtensa_default_isa, | |
6152 | vinsn->slots[i].opcode)); | |
6153 | fprintf (stderr, "\n"); | |
6154 | xg_clear_vinsn (vinsn); | |
6155 | return; | |
6156 | } | |
6157 | ||
6158 | /* First, find a format that works. */ | |
6159 | if (vinsn->format == XTENSA_UNDEFINED) | |
6160 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6161 | ||
6162 | xg_assemble_vliw_tokens (vinsn); | |
6163 | ||
6164 | xg_clear_vinsn (vinsn); | |
6165 | } | |
6166 | ||
6167 | ||
6168 | /* Given an vliw instruction, what conflicts are there in register | |
6169 | usage and in writes to states and queues? | |
6170 | ||
6171 | This function does two things: | |
6172 | 1. Reports an error when a vinsn contains illegal combinations | |
6173 | of writes to registers states or queues. | |
6174 | 2. Marks individual tinsns as not relaxable if the combination | |
6175 | contains antidependencies. | |
6176 | ||
6177 | Job 2 handles things like swap semantics in instructions that need | |
6178 | to be relaxed. For example, | |
6179 | ||
6180 | addi a0, a1, 100000 | |
6181 | ||
6182 | normally would be relaxed to | |
6183 | ||
6184 | l32r a0, some_label | |
6185 | add a0, a1, a0 | |
6186 | ||
6187 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6188 | ||
6189 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6190 | ||
6191 | then we can't relax it into | |
6192 | ||
6193 | l32r a0, some_label | |
6194 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6195 | ||
6196 | because the value of a0 is trashed before the second add can read it. */ | |
6197 | ||
7fa3d080 BW |
6198 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6199 | ||
43cd72b9 | 6200 | static bfd_boolean |
7fa3d080 | 6201 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6202 | { |
6203 | int i, j; | |
6204 | int branches = 0; | |
6205 | xtensa_isa isa = xtensa_default_isa; | |
6206 | ||
6207 | assert (!past_xtensa_end); | |
6208 | ||
6209 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6210 | { | |
6211 | TInsn *op1 = &vinsn->slots[i]; | |
6212 | if (op1->is_specific_opcode) | |
6213 | op1->keep_wide = TRUE; | |
6214 | else | |
6215 | op1->keep_wide = FALSE; | |
6216 | } | |
6217 | ||
6218 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6219 | { | |
6220 | TInsn *op1 = &vinsn->slots[i]; | |
6221 | ||
6222 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6223 | branches++; | |
6224 | ||
6225 | for (j = 0; j < vinsn->num_slots; j++) | |
6226 | { | |
6227 | if (i != j) | |
6228 | { | |
6229 | TInsn *op2 = &vinsn->slots[j]; | |
6230 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6231 | switch (conflict_type) | |
6232 | { | |
6233 | case 'c': | |
6234 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6235 | xtensa_opcode_name (isa, op1->opcode), i, | |
6236 | xtensa_opcode_name (isa, op2->opcode), j); | |
6237 | return TRUE; | |
6238 | case 'd': | |
6239 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6240 | xtensa_opcode_name (isa, op1->opcode), i, | |
6241 | xtensa_opcode_name (isa, op2->opcode), j); | |
6242 | return TRUE; | |
6243 | case 'e': | |
53dfbcc7 | 6244 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6245 | xtensa_opcode_name (isa, op1->opcode), i, |
6246 | xtensa_opcode_name (isa, op2->opcode), j); | |
6247 | return TRUE; | |
6248 | case 'f': | |
53dfbcc7 | 6249 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6250 | xtensa_opcode_name (isa, op1->opcode), i, |
6251 | xtensa_opcode_name (isa, op2->opcode), j); | |
6252 | return TRUE; | |
6253 | default: | |
6254 | /* Everything is OK. */ | |
6255 | break; | |
6256 | } | |
6257 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6258 | || conflict_type == 'a'); | |
6259 | } | |
6260 | } | |
6261 | } | |
6262 | ||
6263 | if (branches > 1) | |
6264 | { | |
6265 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6266 | return TRUE; | |
6267 | } | |
6268 | ||
6269 | return FALSE; | |
6270 | } | |
6271 | ||
6272 | ||
a1ace8d8 | 6273 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6274 | Cases found are: |
6275 | ||
6276 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6277 | case B: no relationship between what is read and written (both could | |
6278 | read the same reg though) | |
c138bc38 | 6279 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6280 | bundle) |
6281 | case D: t1 writes a state that t2 also writes | |
6282 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6283 | case F: two volatile queue accesses |
43cd72b9 BW |
6284 | */ |
6285 | ||
6286 | static char | |
7fa3d080 | 6287 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6288 | { |
6289 | xtensa_isa isa = xtensa_default_isa; | |
6290 | xtensa_regfile t1_regfile, t2_regfile; | |
6291 | int t1_reg, t2_reg; | |
6292 | int t1_base_reg, t1_last_reg; | |
6293 | int t2_base_reg, t2_last_reg; | |
6294 | char t1_inout, t2_inout; | |
6295 | int i, j; | |
6296 | char conflict = 'b'; | |
6297 | int t1_states; | |
6298 | int t2_states; | |
6299 | int t1_interfaces; | |
6300 | int t2_interfaces; | |
6301 | bfd_boolean t1_volatile = FALSE; | |
6302 | bfd_boolean t2_volatile = FALSE; | |
6303 | ||
6304 | /* Check registers. */ | |
6305 | for (j = 0; j < t2->ntok; j++) | |
6306 | { | |
6307 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6308 | continue; | |
6309 | ||
6310 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6311 | t2_base_reg = t2->tok[j].X_add_number; | |
6312 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6313 | ||
6314 | for (i = 0; i < t1->ntok; i++) | |
6315 | { | |
6316 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6317 | continue; | |
6318 | ||
6319 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6320 | ||
6321 | if (t1_regfile != t2_regfile) | |
6322 | continue; | |
6323 | ||
6324 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6325 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6326 | ||
6327 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6328 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6329 | { | |
6330 | if (t1_inout == 'm' || t1_inout == 'o' | |
6331 | || t2_inout == 'm' || t2_inout == 'o') | |
6332 | { | |
6333 | conflict = 'a'; | |
6334 | continue; | |
6335 | } | |
6336 | } | |
6337 | ||
6338 | t1_base_reg = t1->tok[i].X_add_number; | |
6339 | t1_last_reg = (t1_base_reg | |
6340 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6341 | ||
6342 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6343 | { | |
6344 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6345 | { | |
6346 | if (t1_reg != t2_reg) | |
6347 | continue; | |
6348 | ||
6349 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6350 | { |
6351 | conflict = 'a'; | |
6352 | continue; | |
6353 | } | |
43cd72b9 | 6354 | |
7fa3d080 BW |
6355 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6356 | { | |
6357 | conflict = 'a'; | |
6358 | continue; | |
6359 | } | |
43cd72b9 | 6360 | |
7fa3d080 BW |
6361 | if (t1_inout != 'i' && t2_inout != 'i') |
6362 | return 'c'; | |
6363 | } | |
6364 | } | |
6365 | } | |
6366 | } | |
43cd72b9 | 6367 | |
7fa3d080 BW |
6368 | /* Check states. */ |
6369 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6370 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6371 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6372 | { |
7fa3d080 BW |
6373 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6374 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6375 | for (i = 0; i < t1_states; i++) | |
6376 | { | |
6377 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6378 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6379 | if (t1_so != t2_so) |
7fa3d080 | 6380 | continue; |
43cd72b9 | 6381 | |
7fa3d080 BW |
6382 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6383 | { | |
6384 | conflict = 'a'; | |
6385 | continue; | |
6386 | } | |
c138bc38 | 6387 | |
7fa3d080 BW |
6388 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6389 | { | |
6390 | conflict = 'a'; | |
6391 | continue; | |
6392 | } | |
c138bc38 | 6393 | |
7fa3d080 BW |
6394 | if (t1_inout != 'i' && t2_inout != 'i') |
6395 | return 'd'; | |
c138bc38 | 6396 | } |
7fa3d080 | 6397 | } |
43cd72b9 | 6398 | |
7fa3d080 BW |
6399 | /* Check tieports. */ |
6400 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6401 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6402 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6403 | { |
7fa3d080 BW |
6404 | xtensa_interface t2_int |
6405 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6406 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6407 | ||
53dfbcc7 | 6408 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6409 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6410 | t2_volatile = TRUE; |
a1ace8d8 | 6411 | |
7fa3d080 BW |
6412 | for (i = 0; i < t1_interfaces; i++) |
6413 | { | |
6414 | xtensa_interface t1_int | |
6415 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6416 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6417 | |
53dfbcc7 | 6418 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6419 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6420 | t1_volatile = TRUE; |
a1ace8d8 BW |
6421 | |
6422 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6423 | return 'f'; | |
c138bc38 | 6424 | |
7fa3d080 BW |
6425 | if (t1_int != t2_int) |
6426 | continue; | |
c138bc38 | 6427 | |
7fa3d080 BW |
6428 | if (t2_inout == 'i' && t1_inout == 'o') |
6429 | { | |
6430 | conflict = 'a'; | |
6431 | continue; | |
6432 | } | |
c138bc38 | 6433 | |
7fa3d080 BW |
6434 | if (t1_inout == 'i' && t2_inout == 'o') |
6435 | { | |
6436 | conflict = 'a'; | |
6437 | continue; | |
6438 | } | |
c138bc38 | 6439 | |
7fa3d080 BW |
6440 | if (t1_inout != 'i' && t2_inout != 'i') |
6441 | return 'e'; | |
6442 | } | |
43cd72b9 | 6443 | } |
c138bc38 | 6444 | |
7fa3d080 | 6445 | return conflict; |
43cd72b9 BW |
6446 | } |
6447 | ||
6448 | ||
6449 | static xtensa_format | |
7fa3d080 | 6450 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6451 | { |
6452 | /* Right now we assume that the ops within the vinsn are properly | |
6453 | ordered for the slots that the programmer wanted them in. In | |
6454 | other words, we don't rearrange the ops in hopes of finding a | |
6455 | better format. The scheduler handles that. */ | |
6456 | ||
6457 | xtensa_isa isa = xtensa_default_isa; | |
6458 | xtensa_format format; | |
6459 | vliw_insn v_copy = *vinsn; | |
6460 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6461 | ||
65738a7d BW |
6462 | if (vinsn->num_slots == 1) |
6463 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6464 | ||
43cd72b9 BW |
6465 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6466 | { | |
6467 | v_copy = *vinsn; | |
6468 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6469 | { | |
6470 | int slot; | |
6471 | int fit = 0; | |
6472 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6473 | { | |
6474 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6475 | { | |
6476 | v_copy.slots[slot].opcode = | |
6477 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6478 | v_copy.slots[slot].ntok = 0; | |
6479 | } | |
6480 | ||
6481 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6482 | format, slot)) | |
6483 | fit++; | |
7fa3d080 | 6484 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6485 | { |
7fa3d080 BW |
6486 | TInsn widened; |
6487 | /* Try the widened version. */ | |
6488 | if (!v_copy.slots[slot].keep_wide | |
6489 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6490 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6491 | &widened, TRUE) | |
7fa3d080 BW |
6492 | && opcode_fits_format_slot (widened.opcode, |
6493 | format, slot)) | |
43cd72b9 | 6494 | { |
7fa3d080 BW |
6495 | v_copy.slots[slot] = widened; |
6496 | fit++; | |
43cd72b9 BW |
6497 | } |
6498 | } | |
6499 | } | |
6500 | if (fit == v_copy.num_slots) | |
6501 | { | |
6502 | *vinsn = v_copy; | |
6503 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6504 | vinsn->format = format; | |
6505 | break; | |
6506 | } | |
6507 | } | |
6508 | } | |
6509 | ||
6510 | if (format == xtensa_isa_num_formats (isa)) | |
6511 | return XTENSA_UNDEFINED; | |
6512 | ||
6513 | return format; | |
6514 | } | |
6515 | ||
6516 | ||
6517 | /* Return the additional space needed in a frag | |
6518 | for possible relaxations of any ops in a VLIW insn. | |
6519 | Also fill out the relaxations that might be required of | |
6520 | each tinsn in the vinsn. */ | |
6521 | ||
6522 | static int | |
e7da6241 | 6523 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6524 | { |
e7da6241 | 6525 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6526 | int extra_space = 0; |
6527 | int slot; | |
6528 | ||
6529 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6530 | { | |
6531 | TInsn *tinsn = &vinsn->slots[slot]; | |
6532 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6533 | { | |
6534 | /* A narrow instruction could be widened later to help | |
6535 | alignment issues. */ | |
84b08ed9 | 6536 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6537 | && !tinsn->is_specific_opcode |
6538 | && vinsn->num_slots == 1) | |
6539 | { | |
6540 | /* Difference in bytes between narrow and wide insns... */ | |
6541 | extra_space += 1; | |
6542 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6543 | } |
6544 | } | |
6545 | else | |
6546 | { | |
b08b5071 BW |
6547 | if (workaround_b_j_loop_end |
6548 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6549 | && use_transform ()) |
6550 | { | |
6551 | /* Add 2 of these. */ | |
6552 | extra_space += 3; /* for the nop size */ | |
6553 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6554 | } | |
c138bc38 | 6555 | |
43cd72b9 BW |
6556 | /* Need to assemble it with space for the relocation. */ |
6557 | if (xg_is_relaxable_insn (tinsn, 0) | |
6558 | && !tinsn->is_specific_opcode) | |
6559 | { | |
6560 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6561 | int max_literal_size = | |
6562 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6563 | |
43cd72b9 | 6564 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6565 | |
43cd72b9 | 6566 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6567 | extra_space += max_size; |
6568 | } | |
6569 | else | |
6570 | { | |
e7da6241 BW |
6571 | /* A fix record will be added for this instruction prior |
6572 | to relaxation, so make it end the frag. */ | |
6573 | finish_frag = TRUE; | |
43cd72b9 BW |
6574 | } |
6575 | } | |
6576 | } | |
e7da6241 | 6577 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6578 | return extra_space; |
6579 | } | |
6580 | ||
6581 | ||
6582 | static void | |
b2d179be | 6583 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6584 | { |
6585 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6586 | int slot, chosen_slot; |
43cd72b9 | 6587 | |
b2d179be BW |
6588 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6589 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6590 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6591 | |
b2d179be BW |
6592 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6593 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6594 | { |
b2d179be BW |
6595 | if (slot == chosen_slot) |
6596 | vinsn->slots[slot] = *tinsn; | |
6597 | else | |
6598 | { | |
6599 | vinsn->slots[slot].opcode = | |
6600 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6601 | vinsn->slots[slot].ntok = 0; | |
6602 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6603 | } | |
43cd72b9 | 6604 | } |
43cd72b9 BW |
6605 | } |
6606 | ||
6607 | ||
6608 | static bfd_boolean | |
7fa3d080 | 6609 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6610 | { |
6611 | int i; | |
6612 | IStack istack; /* put instructions into here */ | |
6613 | symbolS *lit_sym = NULL; | |
6614 | symbolS *label_sym = NULL; | |
6615 | ||
6616 | istack_init (&istack); | |
6617 | ||
6618 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6619 | Because the scheduling and bundling characteristics of movi and |
6620 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6621 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6622 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6623 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6624 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6625 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6626 | || orig_insn->tok[1].X_op == O_pltrel) |
6627 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6628 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6629 | else | |
6630 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6631 | return TRUE; | |
6632 | ||
6633 | for (i = 0; i < istack.ninsn; i++) | |
6634 | { | |
6635 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6636 | switch (insn->insn_type) |
43cd72b9 BW |
6637 | { |
6638 | case ITYPE_LITERAL: | |
6639 | assert (lit_sym == NULL); | |
6640 | lit_sym = xg_assemble_literal (insn); | |
6641 | break; | |
6642 | case ITYPE_LABEL: | |
6643 | { | |
6644 | static int relaxed_sym_idx = 0; | |
6645 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6646 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6647 | colon (label); | |
6648 | assert (label_sym == NULL); | |
6649 | label_sym = symbol_find_or_make (label); | |
6650 | assert (label_sym); | |
6651 | free (label); | |
6652 | } | |
6653 | break; | |
6654 | case ITYPE_INSN: | |
b2d179be BW |
6655 | { |
6656 | vliw_insn v; | |
6657 | if (lit_sym) | |
6658 | xg_resolve_literals (insn, lit_sym); | |
6659 | if (label_sym) | |
6660 | xg_resolve_labels (insn, label_sym); | |
6661 | xg_init_vinsn (&v); | |
6662 | bundle_tinsn (insn, &v); | |
6663 | finish_vinsn (&v); | |
6664 | xg_free_vinsn (&v); | |
6665 | } | |
43cd72b9 BW |
6666 | break; |
6667 | default: | |
6668 | assert (0); | |
6669 | break; | |
6670 | } | |
6671 | } | |
6672 | return FALSE; | |
6673 | } | |
6674 | ||
6675 | ||
34e41783 BW |
6676 | static int |
6677 | total_frag_text_expansion (fragS *fragP) | |
6678 | { | |
6679 | int slot; | |
6680 | int total_expansion = 0; | |
6681 | ||
6682 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6683 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6684 | ||
6685 | return total_expansion; | |
6686 | } | |
6687 | ||
6688 | ||
43cd72b9 BW |
6689 | /* Emit a vliw instruction to the current fragment. */ |
6690 | ||
7fa3d080 BW |
6691 | static void |
6692 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6693 | { |
e7da6241 | 6694 | bfd_boolean finish_frag; |
43cd72b9 BW |
6695 | bfd_boolean is_jump = FALSE; |
6696 | bfd_boolean is_branch = FALSE; | |
6697 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
6698 | int insn_size; |
6699 | int extra_space; | |
6700 | char *f = NULL; | |
6701 | int slot; | |
b224e962 BW |
6702 | struct dwarf2_line_info debug_line; |
6703 | bfd_boolean loc_directive_seen = FALSE; | |
6704 | TInsn *tinsn; | |
43cd72b9 | 6705 | |
b224e962 | 6706 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
6707 | |
6708 | if (generating_literals) | |
6709 | { | |
6710 | static int reported = 0; | |
6711 | if (reported < 4) | |
6712 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6713 | _("cannot assemble into a literal fragment")); | |
6714 | if (reported == 3) | |
6715 | as_bad (_("...")); | |
6716 | reported++; | |
6717 | return; | |
6718 | } | |
6719 | ||
6720 | if (frag_now_fix () != 0 | |
b08b5071 | 6721 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6722 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6723 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6724 | || (directive_state[directive_longcalls] |
6725 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6726 | || (directive_state[directive_absolute_literals] |
6727 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6728 | { | |
6729 | frag_wane (frag_now); | |
6730 | frag_new (0); | |
6731 | xtensa_set_frag_assembly_state (frag_now); | |
6732 | } | |
6733 | ||
6734 | if (workaround_a0_b_retw | |
6735 | && vinsn->num_slots == 1 | |
6736 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6737 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6738 | && use_transform ()) | |
6739 | { | |
6740 | has_a0_b_retw = TRUE; | |
6741 | ||
6742 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6743 | After the first assembly pass we will check all of them and | |
6744 | add a nop if needed. */ | |
6745 | frag_now->tc_frag_data.is_insn = TRUE; | |
6746 | frag_var (rs_machine_dependent, 4, 4, | |
6747 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6748 | frag_now->fr_symbol, | |
6749 | frag_now->fr_offset, | |
6750 | NULL); | |
6751 | xtensa_set_frag_assembly_state (frag_now); | |
6752 | frag_now->tc_frag_data.is_insn = TRUE; | |
6753 | frag_var (rs_machine_dependent, 4, 4, | |
6754 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6755 | frag_now->fr_symbol, | |
6756 | frag_now->fr_offset, | |
6757 | NULL); | |
6758 | xtensa_set_frag_assembly_state (frag_now); | |
6759 | } | |
6760 | ||
b224e962 | 6761 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 6762 | { |
b224e962 BW |
6763 | tinsn = &vinsn->slots[slot]; |
6764 | ||
43cd72b9 | 6765 | /* See if the instruction implies an aligned section. */ |
b224e962 | 6766 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 6767 | record_alignment (now_seg, 2); |
c138bc38 | 6768 | |
b224e962 BW |
6769 | /* Determine the best line number for debug info. */ |
6770 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
6771 | && (tinsn->debug_line.filenum != debug_line.filenum | |
6772 | || tinsn->debug_line.line < debug_line.line | |
6773 | || tinsn->debug_line.column < debug_line.column)) | |
6774 | debug_line = tinsn->debug_line; | |
6775 | if (tinsn->loc_directive_seen) | |
6776 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
6777 | } |
6778 | ||
6779 | /* Special cases for instructions that force an alignment... */ | |
6780 | /* None of these opcodes are bundle-able. */ | |
6781 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6782 | { | |
d77b99c9 | 6783 | int max_fill; |
c138bc38 | 6784 | |
05d58145 BW |
6785 | /* Remember the symbol that marks the end of the loop in the frag |
6786 | that marks the start of the loop. This way we can easily find | |
6787 | the end of the loop at the beginning, without adding special code | |
6788 | to mark the loop instructions themselves. */ | |
6789 | symbolS *target_sym = NULL; | |
6790 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6791 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6792 | ||
43cd72b9 BW |
6793 | xtensa_set_frag_assembly_state (frag_now); |
6794 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6795 | |
43cd72b9 BW |
6796 | max_fill = get_text_align_max_fill_size |
6797 | (get_text_align_power (xtensa_fetch_width), | |
6798 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6799 | ||
6800 | if (use_transform ()) | |
6801 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6802 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6803 | else |
c138bc38 | 6804 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6805 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6806 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
6807 | } |
6808 | ||
b08b5071 | 6809 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6810 | && !vinsn->slots[0].is_specific_opcode) |
6811 | { | |
6812 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 6813 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
6814 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
6815 | } | |
6816 | ||
6817 | if (vinsn->num_slots == 1) | |
6818 | { | |
6819 | if (workaround_a0_b_retw && use_transform ()) | |
6820 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6821 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6822 | ||
6823 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6824 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6825 | } | |
6826 | else | |
6827 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6828 | ||
6829 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6830 | ||
e7da6241 | 6831 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6832 | |
6833 | /* vinsn_to_insnbuf will produce the error. */ | |
6834 | if (vinsn->format != XTENSA_UNDEFINED) | |
6835 | { | |
d77b99c9 | 6836 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6837 | xtensa_set_frag_assembly_state (frag_now); |
6838 | frag_now->tc_frag_data.is_insn = TRUE; | |
6839 | } | |
6840 | ||
e7da6241 | 6841 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6842 | if (vinsn->format == XTENSA_UNDEFINED) |
6843 | return; | |
6844 | ||
d77b99c9 | 6845 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6846 | |
b224e962 BW |
6847 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
6848 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
6849 | &debug_line); | |
43cd72b9 BW |
6850 | |
6851 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6852 | { | |
b224e962 | 6853 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 6854 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 6855 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6856 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6857 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6858 | if (tinsn->literal_space != 0) | |
6859 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6860 | ||
6861 | if (tinsn->subtype == RELAX_NARROW) | |
6862 | assert (vinsn->num_slots == 1); | |
6863 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6864 | is_jump = TRUE; | |
6865 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6866 | is_branch = TRUE; | |
6867 | ||
e7da6241 BW |
6868 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6869 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6870 | finish_frag = TRUE; |
6871 | } | |
6872 | ||
6873 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6874 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6875 | |
6876 | if (finish_frag) | |
6877 | { | |
6878 | frag_variant (rs_machine_dependent, | |
6879 | extra_space, extra_space, RELAX_SLOTS, | |
6880 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6881 | xtensa_set_frag_assembly_state (frag_now); | |
6882 | } | |
6883 | ||
6884 | /* Special cases for loops: | |
6885 | close_loop_end should be inserted AFTER short_loop. | |
6886 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6887 | when converting them. */ | |
6888 | ||
6889 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6890 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6891 | && !vinsn->slots[0].is_specific_opcode) |
6892 | { | |
6893 | if (workaround_short_loop && use_transform ()) | |
6894 | { | |
6895 | maybe_has_short_loop = TRUE; | |
6896 | frag_now->tc_frag_data.is_insn = TRUE; | |
6897 | frag_var (rs_machine_dependent, 4, 4, | |
6898 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6899 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6900 | frag_now->tc_frag_data.is_insn = TRUE; | |
6901 | frag_var (rs_machine_dependent, 4, 4, | |
6902 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6903 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6904 | } | |
6905 | ||
6906 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6907 | loop at least 12 bytes away from another loop's end. */ | |
6908 | if (workaround_close_loop_end && use_transform ()) | |
6909 | { | |
6910 | maybe_has_close_loop_end = TRUE; | |
6911 | frag_now->tc_frag_data.is_insn = TRUE; | |
6912 | frag_var (rs_machine_dependent, 12, 12, | |
6913 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6914 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6915 | } | |
6916 | } | |
6917 | ||
6918 | if (use_transform ()) | |
6919 | { | |
6920 | if (is_jump) | |
6921 | { | |
6922 | assert (finish_frag); | |
6923 | frag_var (rs_machine_dependent, | |
6924 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6925 | RELAX_UNREACHABLE, | |
6926 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6927 | xtensa_set_frag_assembly_state (frag_now); | |
6928 | } | |
7b1cc377 | 6929 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6930 | { |
6931 | assert (finish_frag); | |
6932 | frag_var (rs_machine_dependent, | |
6933 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6934 | RELAX_MAYBE_UNREACHABLE, | |
6935 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6936 | xtensa_set_frag_assembly_state (frag_now); | |
6937 | frag_var (rs_machine_dependent, | |
6938 | 0, 0, | |
6939 | RELAX_MAYBE_DESIRE_ALIGN, | |
6940 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6941 | xtensa_set_frag_assembly_state (frag_now); | |
6942 | } | |
6943 | } | |
6944 | ||
6945 | /* Now, if the original opcode was a call... */ | |
6946 | if (do_align_targets () | |
6947 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6948 | { | |
b08b5071 | 6949 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6950 | frag_now->tc_frag_data.is_insn = TRUE; |
6951 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6952 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6953 | xtensa_set_frag_assembly_state (frag_now); | |
6954 | } | |
6955 | ||
6956 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6957 | { | |
6958 | frag_wane (frag_now); | |
6959 | frag_new (0); | |
6960 | xtensa_set_frag_assembly_state (frag_now); | |
6961 | } | |
6962 | } | |
6963 | ||
6964 | \f | |
7fa3d080 BW |
6965 | /* xtensa_end and helper functions. */ |
6966 | ||
6967 | static void xtensa_cleanup_align_frags (void); | |
6968 | static void xtensa_fix_target_frags (void); | |
6969 | static void xtensa_mark_narrow_branches (void); | |
6970 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 6971 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
6972 | static void xtensa_fix_a0_b_retw_frags (void); |
6973 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6974 | static void xtensa_fix_close_loop_end_frags (void); | |
6975 | static void xtensa_fix_short_loop_frags (void); | |
6976 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 6977 | static void xtensa_add_config_info (void); |
7fa3d080 | 6978 | |
43cd72b9 | 6979 | void |
7fa3d080 | 6980 | xtensa_end (void) |
43cd72b9 BW |
6981 | { |
6982 | directive_balance (); | |
6983 | xtensa_flush_pending_output (); | |
6984 | ||
6985 | past_xtensa_end = TRUE; | |
6986 | ||
6987 | xtensa_move_literals (); | |
6988 | ||
6989 | xtensa_reorder_segments (); | |
6990 | xtensa_cleanup_align_frags (); | |
6991 | xtensa_fix_target_frags (); | |
6992 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6993 | xtensa_fix_a0_b_retw_frags (); | |
6994 | if (workaround_b_j_loop_end) | |
6995 | xtensa_fix_b_j_loop_end_frags (); | |
6996 | ||
6997 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6998 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6999 | xtensa_fix_close_loop_end_frags (); | |
7000 | ||
7001 | if (workaround_short_loop && maybe_has_short_loop) | |
7002 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7003 | if (align_targets) |
7004 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7005 | xtensa_mark_zcl_first_insns (); |
7006 | ||
7007 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7008 | |
7009 | xtensa_add_config_info (); | |
43cd72b9 BW |
7010 | } |
7011 | ||
7012 | ||
7013 | static void | |
7fa3d080 | 7014 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7015 | { |
7016 | frchainS *frchP; | |
c9049d30 | 7017 | asection *s; |
43cd72b9 | 7018 | |
c9049d30 AM |
7019 | for (s = stdoutput->sections; s; s = s->next) |
7020 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7021 | { | |
7022 | fragS *fragP; | |
7023 | /* Walk over all of the fragments in a subsection. */ | |
7024 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7025 | { | |
7026 | if ((fragP->fr_type == rs_align | |
7027 | || fragP->fr_type == rs_align_code | |
7028 | || (fragP->fr_type == rs_machine_dependent | |
7029 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7030 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7031 | && fragP->fr_fix == 0) | |
7032 | { | |
7033 | fragS *next = fragP->fr_next; | |
7034 | ||
7035 | while (next | |
7036 | && next->fr_fix == 0 | |
7037 | && next->fr_type == rs_machine_dependent | |
7038 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7039 | { | |
7040 | frag_wane (next); | |
7041 | next = next->fr_next; | |
7042 | } | |
7043 | } | |
7044 | /* If we don't widen branch targets, then they | |
7045 | will be easier to align. */ | |
7046 | if (fragP->tc_frag_data.is_branch_target | |
7047 | && fragP->fr_opcode == fragP->fr_literal | |
7048 | && fragP->fr_type == rs_machine_dependent | |
7049 | && fragP->fr_subtype == RELAX_SLOTS | |
7050 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7051 | frag_wane (fragP); | |
7052 | if (fragP->fr_type == rs_machine_dependent | |
7053 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7054 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7055 | } | |
7056 | } | |
43cd72b9 BW |
7057 | } |
7058 | ||
7059 | ||
7060 | /* Re-process all of the fragments looking to convert all of the | |
7061 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7062 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7063 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7064 | |
43cd72b9 | 7065 | static void |
7fa3d080 | 7066 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7067 | { |
7068 | frchainS *frchP; | |
c9049d30 | 7069 | asection *s; |
e0001a05 NC |
7070 | |
7071 | /* When this routine is called, all of the subsections are still intact | |
7072 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7073 | for (s = stdoutput->sections; s; s = s->next) |
7074 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7075 | { | |
7076 | fragS *fragP; | |
e0001a05 | 7077 | |
c9049d30 AM |
7078 | /* Walk over all of the fragments in a subsection. */ |
7079 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7080 | { | |
7081 | if (fragP->fr_type == rs_machine_dependent | |
7082 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7083 | { | |
7084 | if (next_frag_is_branch_target (fragP)) | |
7085 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7086 | else | |
7087 | frag_wane (fragP); | |
7088 | } | |
7089 | } | |
7090 | } | |
e0001a05 NC |
7091 | } |
7092 | ||
7093 | ||
7fa3d080 BW |
7094 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7095 | ||
43cd72b9 | 7096 | static void |
7fa3d080 | 7097 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7098 | { |
7099 | frchainS *frchP; | |
c9049d30 | 7100 | asection *s; |
43cd72b9 | 7101 | |
c9049d30 AM |
7102 | for (s = stdoutput->sections; s; s = s->next) |
7103 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7104 | { | |
7105 | fragS *fragP; | |
7106 | /* Walk over all of the fragments in a subsection. */ | |
7107 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7108 | { | |
7109 | if (fragP->fr_type == rs_machine_dependent | |
7110 | && fragP->fr_subtype == RELAX_SLOTS | |
7111 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7112 | { | |
7113 | vliw_insn vinsn; | |
7114 | ||
7115 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7116 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7117 | ||
7118 | if (vinsn.num_slots == 1 | |
7119 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7120 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7121 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7122 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7123 | &vinsn.slots[0])) | |
7124 | { | |
7125 | fragP->fr_subtype = RELAX_SLOTS; | |
7126 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7127 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7128 | } | |
7129 | } | |
7130 | } | |
7131 | } | |
43cd72b9 BW |
7132 | } |
7133 | ||
7134 | ||
7135 | /* A branch is typically widened only when its target is out of | |
7136 | range. However, we would like to widen them to align a subsequent | |
7137 | branch target when possible. | |
7138 | ||
7139 | Because the branch relaxation code is so convoluted, the optimal solution | |
7140 | (combining the two cases) is difficult to get right in all circumstances. | |
7141 | We therefore go with an "almost as good" solution, where we only | |
7142 | use for alignment narrow branches that definitely will not expand to a | |
7143 | jump and a branch. These functions find and mark these cases. */ | |
7144 | ||
a67517f4 BW |
7145 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7146 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7147 | We start counting beginning with the frag after the 2-byte branch, so the | |
7148 | maximum offset is (4 - 2) + 63 = 65. */ | |
7149 | #define MAX_IMMED6 65 | |
43cd72b9 | 7150 | |
d77b99c9 | 7151 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7152 | |
43cd72b9 | 7153 | static bfd_boolean |
7fa3d080 | 7154 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7155 | { |
7156 | const expressionS *expr = &tinsn->tok[1]; | |
7157 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7158 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7159 | fragS *target_frag; |
7160 | ||
7161 | if (expr->X_op != O_symbol) | |
7162 | return FALSE; | |
7163 | ||
7164 | target_frag = symbol_get_frag (symbolP); | |
7165 | ||
43cd72b9 BW |
7166 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7167 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7168 | return FALSE; | |
7169 | ||
7170 | /* The branch doesn't branch over it's own frag, | |
7171 | but over the subsequent ones. */ | |
7172 | fragP = fragP->fr_next; | |
7173 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7174 | { | |
7175 | max_distance += unrelaxed_frag_max_size (fragP); | |
7176 | fragP = fragP->fr_next; | |
7177 | } | |
7178 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7179 | return TRUE; | |
e0001a05 NC |
7180 | return FALSE; |
7181 | } | |
7182 | ||
7183 | ||
43cd72b9 | 7184 | static void |
7fa3d080 | 7185 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7186 | { |
7187 | frchainS *frchP; | |
c9049d30 | 7188 | asection *s; |
43cd72b9 | 7189 | |
c9049d30 AM |
7190 | for (s = stdoutput->sections; s; s = s->next) |
7191 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7192 | { | |
7193 | fragS *fragP; | |
7194 | /* Walk over all of the fragments in a subsection. */ | |
7195 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7196 | { | |
7197 | if (fragP->fr_type == rs_machine_dependent | |
7198 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7199 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7200 | { | |
7201 | /* Find the loop frag. */ | |
7202 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7203 | /* Find the first insn frag. */ | |
7204 | targ_frag = next_non_empty_frag (targ_frag); | |
7205 | ||
7206 | /* Of course, sometimes (mostly for toy test cases) a | |
7207 | zero-cost loop instruction is the last in a section. */ | |
7208 | if (targ_frag) | |
7209 | { | |
7210 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7211 | /* Do not widen a frag that is the first instruction of a | |
7212 | zero-cost loop. It makes that loop harder to align. */ | |
7213 | if (targ_frag->fr_type == rs_machine_dependent | |
7214 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7215 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7216 | == RELAX_NARROW)) | |
7217 | { | |
7218 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7219 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7220 | else | |
7221 | { | |
7222 | frag_wane (targ_frag); | |
7223 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7224 | } | |
7225 | } | |
7226 | } | |
7227 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7228 | frag_wane (fragP); | |
7229 | } | |
7230 | } | |
7231 | } | |
43cd72b9 BW |
7232 | } |
7233 | ||
7234 | ||
6a7eedfe BW |
7235 | /* Some difference-of-symbols expressions make it out to the linker. Some |
7236 | don't. If one does, then the linker can optimize between the two labels. | |
7237 | If it doesn't, then the linker shouldn't. */ | |
7238 | ||
7239 | static void | |
7240 | xtensa_mark_difference_of_two_symbols (void) | |
7241 | { | |
7242 | symbolS *expr_sym; | |
7243 | ||
7244 | for (expr_sym = expr_symbols; expr_sym; | |
7245 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7246 | { | |
7247 | expressionS *expr = symbol_get_value_expression (expr_sym); | |
7248 | ||
7249 | if (expr->X_op == O_subtract) | |
7250 | { | |
7251 | symbolS *left = expr->X_add_symbol; | |
7252 | symbolS *right = expr->X_op_symbol; | |
7253 | ||
7254 | /* Difference of two symbols not in the same section | |
7255 | are handled with relocations in the linker. */ | |
7256 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7257 | { | |
7258 | fragS *start; | |
7259 | fragS *end; | |
7260 | ||
7261 | if (symbol_get_frag (left)->fr_address | |
7262 | <= symbol_get_frag (right)->fr_address) | |
7263 | { | |
7264 | start = symbol_get_frag (left); | |
7265 | end = symbol_get_frag (right); | |
7266 | } | |
7267 | else | |
7268 | { | |
7269 | start = symbol_get_frag (right); | |
7270 | end = symbol_get_frag (left); | |
7271 | } | |
7272 | do | |
7273 | { | |
7274 | start->tc_frag_data.is_no_transform = 1; | |
7275 | start = start->fr_next; | |
7276 | } | |
7277 | while (start && start->fr_address < end->fr_address); | |
7278 | } | |
7279 | } | |
7280 | } | |
7281 | } | |
7282 | ||
7283 | ||
e0001a05 NC |
7284 | /* Re-process all of the fragments looking to convert all of the |
7285 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7286 | conditional branch or a retw/retw.n, convert this frag to one that | |
7287 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7288 | ||
7fa3d080 BW |
7289 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7290 | ||
e0001a05 | 7291 | static void |
7fa3d080 | 7292 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7293 | { |
7294 | frchainS *frchP; | |
c9049d30 | 7295 | asection *s; |
e0001a05 NC |
7296 | |
7297 | /* When this routine is called, all of the subsections are still intact | |
7298 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7299 | for (s = stdoutput->sections; s; s = s->next) |
7300 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7301 | { | |
7302 | fragS *fragP; | |
e0001a05 | 7303 | |
c9049d30 AM |
7304 | /* Walk over all of the fragments in a subsection. */ |
7305 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7306 | { | |
7307 | if (fragP->fr_type == rs_machine_dependent | |
7308 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7309 | { | |
7310 | if (next_instrs_are_b_retw (fragP)) | |
7311 | { | |
7312 | if (fragP->tc_frag_data.is_no_transform) | |
7313 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7314 | else | |
7315 | relax_frag_add_nop (fragP); | |
7316 | } | |
7317 | frag_wane (fragP); | |
7318 | } | |
7319 | } | |
7320 | } | |
e0001a05 NC |
7321 | } |
7322 | ||
7323 | ||
7fa3d080 BW |
7324 | static bfd_boolean |
7325 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7326 | { |
7327 | xtensa_opcode opcode; | |
43cd72b9 | 7328 | xtensa_format fmt; |
e0001a05 NC |
7329 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7330 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7331 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7332 | xtensa_isa isa = xtensa_default_isa; |
7333 | int offset = 0; | |
43cd72b9 BW |
7334 | int slot; |
7335 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7336 | |
7337 | if (!insnbuf) | |
43cd72b9 BW |
7338 | { |
7339 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7340 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7341 | } | |
e0001a05 NC |
7342 | |
7343 | if (next_fragP == NULL) | |
7344 | return FALSE; | |
7345 | ||
7346 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7347 | xtensa_insnbuf_from_chars |
7348 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7349 | fmt = xtensa_format_decode (isa, insnbuf); |
7350 | if (fmt == XTENSA_UNDEFINED) | |
7351 | return FALSE; | |
7352 | ||
7353 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7354 | { | |
7355 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7356 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7357 | ||
7358 | branch_seen = (branch_seen | |
7359 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7360 | } | |
e0001a05 | 7361 | |
43cd72b9 | 7362 | if (!branch_seen) |
e0001a05 NC |
7363 | return FALSE; |
7364 | ||
43cd72b9 | 7365 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7366 | if (offset == next_fragP->fr_fix) |
7367 | { | |
7368 | next_fragP = next_non_empty_frag (next_fragP); | |
7369 | offset = 0; | |
7370 | } | |
43cd72b9 | 7371 | |
e0001a05 NC |
7372 | if (next_fragP == NULL) |
7373 | return FALSE; | |
7374 | ||
7375 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7376 | xtensa_insnbuf_from_chars |
7377 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7378 | fmt = xtensa_format_decode (isa, insnbuf); |
7379 | ||
7380 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7381 | have no problems. */ | |
7382 | if (fmt == XTENSA_UNDEFINED | |
7383 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7384 | return FALSE; | |
7385 | ||
7386 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7387 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7388 | |
b08b5071 | 7389 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7390 | return TRUE; |
43cd72b9 | 7391 | |
e0001a05 NC |
7392 | return FALSE; |
7393 | } | |
7394 | ||
7395 | ||
7396 | /* Re-process all of the fragments looking to convert all of the | |
7397 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7398 | loop end label, convert this frag to one that will generate a NOP. | |
7399 | In any case close it off with a .fill 0. */ | |
7400 | ||
7fa3d080 BW |
7401 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7402 | ||
e0001a05 | 7403 | static void |
7fa3d080 | 7404 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7405 | { |
7406 | frchainS *frchP; | |
c9049d30 | 7407 | asection *s; |
e0001a05 NC |
7408 | |
7409 | /* When this routine is called, all of the subsections are still intact | |
7410 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7411 | for (s = stdoutput->sections; s; s = s->next) |
7412 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7413 | { | |
7414 | fragS *fragP; | |
e0001a05 | 7415 | |
c9049d30 AM |
7416 | /* Walk over all of the fragments in a subsection. */ |
7417 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7418 | { | |
7419 | if (fragP->fr_type == rs_machine_dependent | |
7420 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7421 | { | |
7422 | if (next_instr_is_loop_end (fragP)) | |
7423 | { | |
7424 | if (fragP->tc_frag_data.is_no_transform) | |
7425 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7426 | else | |
7427 | relax_frag_add_nop (fragP); | |
7428 | } | |
7429 | frag_wane (fragP); | |
7430 | } | |
7431 | } | |
7432 | } | |
e0001a05 NC |
7433 | } |
7434 | ||
7435 | ||
7fa3d080 BW |
7436 | static bfd_boolean |
7437 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7438 | { |
7439 | const fragS *next_fragP; | |
7440 | ||
7441 | if (next_frag_is_loop_target (fragP)) | |
7442 | return FALSE; | |
7443 | ||
7444 | next_fragP = next_non_empty_frag (fragP); | |
7445 | if (next_fragP == NULL) | |
7446 | return FALSE; | |
7447 | ||
7448 | if (!next_frag_is_loop_target (next_fragP)) | |
7449 | return FALSE; | |
7450 | ||
7451 | /* If the size is >= 3 then there is more than one instruction here. | |
7452 | The hardware bug will not fire. */ | |
7453 | if (next_fragP->fr_fix > 3) | |
7454 | return FALSE; | |
7455 | ||
7456 | return TRUE; | |
7457 | } | |
7458 | ||
7459 | ||
7460 | /* Re-process all of the fragments looking to convert all of the | |
7461 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7462 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7463 | make it at least 12 bytes away. In any case close it off with a | |
7464 | .fill 0. */ | |
7465 | ||
d77b99c9 | 7466 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7467 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7468 | |
e0001a05 | 7469 | static void |
7fa3d080 | 7470 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7471 | { |
7472 | frchainS *frchP; | |
c9049d30 | 7473 | asection *s; |
e0001a05 NC |
7474 | |
7475 | /* When this routine is called, all of the subsections are still intact | |
7476 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7477 | for (s = stdoutput->sections; s; s = s->next) |
7478 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7479 | { | |
7480 | fragS *fragP; | |
e0001a05 | 7481 | |
c9049d30 | 7482 | fragS *current_target = NULL; |
e0001a05 | 7483 | |
c9049d30 AM |
7484 | /* Walk over all of the fragments in a subsection. */ |
7485 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7486 | { | |
7487 | if (fragP->fr_type == rs_machine_dependent | |
7488 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7489 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7490 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7491 | |
c9049d30 AM |
7492 | if (current_target |
7493 | && fragP->fr_type == rs_machine_dependent | |
7494 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7495 | { | |
7496 | offsetT min_bytes; | |
7497 | int bytes_added = 0; | |
e0001a05 NC |
7498 | |
7499 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7500 | /* Max out at 12. */ |
7501 | min_bytes = min_bytes_to_other_loop_end | |
7502 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7503 | ||
7504 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7505 | { | |
7506 | if (fragP->tc_frag_data.is_no_transform) | |
7507 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7508 | else | |
7509 | { | |
7510 | while (min_bytes + bytes_added | |
7511 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7512 | { | |
7513 | int length = 3; | |
7514 | ||
7515 | if (fragP->fr_var < length) | |
7516 | as_fatal (_("fr_var %lu < length %d"), | |
7517 | (long) fragP->fr_var, length); | |
7518 | else | |
7519 | { | |
7520 | assemble_nop (length, | |
7521 | fragP->fr_literal + fragP->fr_fix); | |
7522 | fragP->fr_fix += length; | |
7523 | fragP->fr_var -= length; | |
7524 | } | |
7525 | bytes_added += length; | |
7526 | } | |
7527 | } | |
7528 | } | |
7529 | frag_wane (fragP); | |
7530 | } | |
7531 | assert (fragP->fr_type != rs_machine_dependent | |
7532 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7533 | } | |
7534 | } | |
e0001a05 NC |
7535 | } |
7536 | ||
7537 | ||
d77b99c9 | 7538 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7539 | |
d77b99c9 | 7540 | static offsetT |
7fa3d080 BW |
7541 | min_bytes_to_other_loop_end (fragS *fragP, |
7542 | fragS *current_target, | |
d77b99c9 | 7543 | offsetT max_size) |
e0001a05 | 7544 | { |
d77b99c9 | 7545 | offsetT offset = 0; |
e0001a05 NC |
7546 | fragS *current_fragP; |
7547 | ||
7548 | for (current_fragP = fragP; | |
7549 | current_fragP; | |
7550 | current_fragP = current_fragP->fr_next) | |
7551 | { | |
7552 | if (current_fragP->tc_frag_data.is_loop_target | |
7553 | && current_fragP != current_target) | |
05d58145 | 7554 | return offset; |
e0001a05 NC |
7555 | |
7556 | offset += unrelaxed_frag_min_size (current_fragP); | |
7557 | ||
05d58145 | 7558 | if (offset >= max_size) |
e0001a05 NC |
7559 | return max_size; |
7560 | } | |
7561 | return max_size; | |
7562 | } | |
7563 | ||
7564 | ||
d77b99c9 | 7565 | static offsetT |
7fa3d080 | 7566 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7567 | { |
d77b99c9 | 7568 | offsetT size = fragP->fr_fix; |
e0001a05 | 7569 | |
d77b99c9 | 7570 | /* Add fill size. */ |
e0001a05 NC |
7571 | if (fragP->fr_type == rs_fill) |
7572 | size += fragP->fr_offset; | |
7573 | ||
7574 | return size; | |
7575 | } | |
7576 | ||
7577 | ||
d77b99c9 | 7578 | static offsetT |
7fa3d080 | 7579 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7580 | { |
d77b99c9 | 7581 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7582 | switch (fragP->fr_type) |
7583 | { | |
7584 | case 0: | |
c138bc38 | 7585 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7586 | end up with type 0. */ |
7587 | break; | |
7588 | case rs_fill: | |
7589 | case rs_org: | |
7590 | case rs_space: | |
7591 | size += fragP->fr_offset; | |
7592 | break; | |
7593 | case rs_align: | |
7594 | case rs_align_code: | |
7595 | case rs_align_test: | |
7596 | case rs_leb128: | |
7597 | case rs_cfa: | |
7598 | case rs_dwarf2dbg: | |
7599 | /* No further adjustments needed. */ | |
7600 | break; | |
7601 | case rs_machine_dependent: | |
7602 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7603 | size += fragP->fr_var; | |
7604 | break; | |
7605 | default: | |
7606 | /* We had darn well better know how big it is. */ | |
7607 | assert (0); | |
7608 | break; | |
7609 | } | |
7610 | ||
7611 | return size; | |
7612 | } | |
7613 | ||
7614 | ||
e0001a05 NC |
7615 | /* Re-process all of the fragments looking to convert all |
7616 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7617 | ||
7618 | A) | |
7619 | 1) the instruction size count to the loop end label | |
7620 | is too short (<= 2 instructions), | |
7621 | 2) loop has a jump or branch in it | |
7622 | ||
7623 | or B) | |
43cd72b9 | 7624 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7625 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7626 | 3) the instruction size count to the loop end label is too short | |
7627 | (<= 2 instructions) | |
7628 | then convert this frag (and maybe the next one) to generate a NOP. | |
7629 | In any case close it off with a .fill 0. */ | |
7630 | ||
d77b99c9 | 7631 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7632 | static bfd_boolean branch_before_loop_end (fragS *); |
7633 | ||
e0001a05 | 7634 | static void |
7fa3d080 | 7635 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7636 | { |
7637 | frchainS *frchP; | |
c9049d30 | 7638 | asection *s; |
e0001a05 NC |
7639 | |
7640 | /* When this routine is called, all of the subsections are still intact | |
7641 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7642 | for (s = stdoutput->sections; s; s = s->next) |
7643 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7644 | { | |
7645 | fragS *fragP; | |
7646 | fragS *current_target = NULL; | |
7647 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7648 | |
c9049d30 AM |
7649 | /* Walk over all of the fragments in a subsection. */ |
7650 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7651 | { | |
7652 | if (fragP->fr_type == rs_machine_dependent | |
7653 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7654 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7655 | { | |
7656 | TInsn t_insn; | |
7657 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7658 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7659 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7660 | current_opcode = t_insn.opcode; | |
7661 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7662 | current_opcode) == 1); |
c9049d30 | 7663 | } |
e0001a05 | 7664 | |
c9049d30 AM |
7665 | if (fragP->fr_type == rs_machine_dependent |
7666 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7667 | { | |
7668 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7669 | && (branch_before_loop_end (fragP->fr_next) | |
7670 | || (workaround_all_short_loops | |
7671 | && current_opcode != XTENSA_UNDEFINED | |
7672 | && current_opcode != xtensa_loop_opcode))) | |
7673 | { | |
7674 | if (fragP->tc_frag_data.is_no_transform) | |
7675 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7676 | else | |
7677 | relax_frag_add_nop (fragP); | |
7678 | } | |
7679 | frag_wane (fragP); | |
7680 | } | |
7681 | } | |
7682 | } | |
e0001a05 NC |
7683 | } |
7684 | ||
7685 | ||
d77b99c9 | 7686 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7687 | |
d77b99c9 | 7688 | static int |
7fa3d080 BW |
7689 | count_insns_to_loop_end (fragS *base_fragP, |
7690 | bfd_boolean count_relax_add, | |
d77b99c9 | 7691 | int max_count) |
e0001a05 NC |
7692 | { |
7693 | fragS *fragP = NULL; | |
d77b99c9 | 7694 | int insn_count = 0; |
e0001a05 NC |
7695 | |
7696 | fragP = base_fragP; | |
7697 | ||
7698 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7699 | { | |
7700 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7701 | if (insn_count >= max_count) | |
7702 | return max_count; | |
7703 | ||
7704 | if (count_relax_add) | |
7705 | { | |
7706 | if (fragP->fr_type == rs_machine_dependent | |
7707 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7708 | { | |
7709 | /* In order to add the appropriate number of | |
7710 | NOPs, we count an instruction for downstream | |
7711 | occurrences. */ | |
7712 | insn_count++; | |
7713 | if (insn_count >= max_count) | |
7714 | return max_count; | |
7715 | } | |
7716 | } | |
7717 | } | |
7718 | return insn_count; | |
7719 | } | |
7720 | ||
7721 | ||
d77b99c9 | 7722 | static int |
7fa3d080 | 7723 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7724 | { |
43cd72b9 BW |
7725 | xtensa_isa isa = xtensa_default_isa; |
7726 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7727 | int insn_count = 0; |
e0001a05 NC |
7728 | int offset = 0; |
7729 | ||
7730 | if (!fragP->tc_frag_data.is_insn) | |
7731 | return insn_count; | |
7732 | ||
43cd72b9 BW |
7733 | if (!insnbuf) |
7734 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7735 | ||
e0001a05 NC |
7736 | /* Decode the fixed instructions. */ |
7737 | while (offset < fragP->fr_fix) | |
7738 | { | |
43cd72b9 BW |
7739 | xtensa_format fmt; |
7740 | ||
d77b99c9 BW |
7741 | xtensa_insnbuf_from_chars |
7742 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7743 | fmt = xtensa_format_decode (isa, insnbuf); |
7744 | ||
7745 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7746 | { |
7747 | as_fatal (_("undecodable instruction in instruction frag")); | |
7748 | return insn_count; | |
7749 | } | |
43cd72b9 | 7750 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7751 | insn_count++; |
7752 | } | |
7753 | ||
7754 | return insn_count; | |
7755 | } | |
7756 | ||
7757 | ||
7fa3d080 BW |
7758 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7759 | ||
43cd72b9 | 7760 | static bfd_boolean |
7fa3d080 | 7761 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7762 | { |
7763 | fragS *fragP; | |
7764 | ||
7765 | for (fragP = base_fragP; | |
7766 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7767 | fragP = fragP->fr_next) | |
7768 | { | |
7769 | if (unrelaxed_frag_has_b_j (fragP)) | |
7770 | return TRUE; | |
7771 | } | |
7772 | return FALSE; | |
7773 | } | |
7774 | ||
7775 | ||
43cd72b9 | 7776 | static bfd_boolean |
7fa3d080 | 7777 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7778 | { |
43cd72b9 BW |
7779 | static xtensa_insnbuf insnbuf = NULL; |
7780 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7781 | int offset = 0; |
7782 | ||
7783 | if (!fragP->tc_frag_data.is_insn) | |
7784 | return FALSE; | |
7785 | ||
43cd72b9 BW |
7786 | if (!insnbuf) |
7787 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7788 | ||
e0001a05 NC |
7789 | /* Decode the fixed instructions. */ |
7790 | while (offset < fragP->fr_fix) | |
7791 | { | |
43cd72b9 BW |
7792 | xtensa_format fmt; |
7793 | int slot; | |
7794 | ||
d77b99c9 BW |
7795 | xtensa_insnbuf_from_chars |
7796 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7797 | fmt = xtensa_format_decode (isa, insnbuf); |
7798 | if (fmt == XTENSA_UNDEFINED) | |
7799 | return FALSE; | |
7800 | ||
7801 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7802 | { |
43cd72b9 BW |
7803 | xtensa_opcode opcode = |
7804 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7805 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7806 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7807 | return TRUE; | |
e0001a05 | 7808 | } |
43cd72b9 | 7809 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7810 | } |
7811 | return FALSE; | |
7812 | } | |
7813 | ||
7814 | ||
7815 | /* Checks to be made after initial assembly but before relaxation. */ | |
7816 | ||
7fa3d080 BW |
7817 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7818 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7819 | ||
e0001a05 | 7820 | static void |
7fa3d080 | 7821 | xtensa_sanity_check (void) |
e0001a05 NC |
7822 | { |
7823 | char *file_name; | |
d77b99c9 | 7824 | unsigned line; |
e0001a05 | 7825 | frchainS *frchP; |
c9049d30 | 7826 | asection *s; |
e0001a05 NC |
7827 | |
7828 | as_where (&file_name, &line); | |
c9049d30 AM |
7829 | for (s = stdoutput->sections; s; s = s->next) |
7830 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7831 | { | |
7832 | fragS *fragP; | |
e0001a05 | 7833 | |
c9049d30 AM |
7834 | /* Walk over all of the fragments in a subsection. */ |
7835 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7836 | { | |
c9049d30 | 7837 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
7838 | && fragP->fr_subtype == RELAX_SLOTS |
7839 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
7840 | { |
7841 | static xtensa_insnbuf insnbuf = NULL; | |
7842 | TInsn t_insn; | |
7843 | ||
7844 | if (fragP->fr_opcode != NULL) | |
7845 | { | |
7846 | if (!insnbuf) | |
7847 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7848 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7849 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7850 | ||
7851 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7852 | t_insn.opcode) == 1) | |
7853 | { | |
7854 | if (is_empty_loop (&t_insn, fragP)) | |
7855 | { | |
7856 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7857 | as_bad (_("invalid empty loop")); | |
7858 | } | |
7859 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7860 | { | |
7861 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7862 | as_bad (_("loop target does not follow " | |
7863 | "loop instruction in section")); | |
7864 | } | |
7865 | } | |
7866 | } | |
7867 | } | |
7868 | } | |
7869 | } | |
e0001a05 NC |
7870 | new_logical_line (file_name, line); |
7871 | } | |
7872 | ||
7873 | ||
7874 | #define LOOP_IMMED_OPN 1 | |
7875 | ||
43cd72b9 | 7876 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7877 | |
7fa3d080 BW |
7878 | static bfd_boolean |
7879 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7880 | { |
7881 | const expressionS *expr; | |
7882 | symbolS *symbolP; | |
7883 | fragS *next_fragP; | |
7884 | ||
7885 | if (insn->insn_type != ITYPE_INSN) | |
7886 | return FALSE; | |
7887 | ||
43cd72b9 | 7888 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7889 | return FALSE; |
7890 | ||
7891 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7892 | return FALSE; | |
7893 | ||
7894 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7895 | ||
7896 | if (expr->X_op != O_symbol) | |
7897 | return FALSE; | |
7898 | ||
7899 | symbolP = expr->X_add_symbol; | |
7900 | if (!symbolP) | |
7901 | return FALSE; | |
7902 | ||
7903 | if (symbol_get_frag (symbolP) == NULL) | |
7904 | return FALSE; | |
7905 | ||
7906 | if (S_GET_VALUE (symbolP) != 0) | |
7907 | return FALSE; | |
7908 | ||
7909 | /* Walk through the zero-size fragments from this one. If we find | |
7910 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7911 | |
e0001a05 NC |
7912 | for (next_fragP = fragP->fr_next; |
7913 | next_fragP != NULL; | |
7914 | next_fragP = next_fragP->fr_next) | |
7915 | { | |
7916 | if (next_fragP == symbol_get_frag (symbolP)) | |
7917 | return TRUE; | |
7918 | if (next_fragP->fr_fix != 0) | |
7919 | return FALSE; | |
7920 | } | |
7921 | return FALSE; | |
7922 | } | |
7923 | ||
7924 | ||
7fa3d080 BW |
7925 | static bfd_boolean |
7926 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7927 | { |
7928 | const expressionS *expr; | |
7929 | symbolS *symbolP; | |
7930 | fragS *next_fragP; | |
7931 | ||
7932 | if (insn->insn_type != ITYPE_INSN) | |
7933 | return FALSE; | |
7934 | ||
64b607e6 | 7935 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7936 | return FALSE; |
7937 | ||
7938 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7939 | return FALSE; | |
7940 | ||
7941 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7942 | ||
7943 | if (expr->X_op != O_symbol) | |
7944 | return FALSE; | |
7945 | ||
7946 | symbolP = expr->X_add_symbol; | |
7947 | if (!symbolP) | |
7948 | return FALSE; | |
7949 | ||
7950 | if (symbol_get_frag (symbolP) == NULL) | |
7951 | return FALSE; | |
7952 | ||
7953 | /* Walk through fragments until we find the target. | |
7954 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7955 | |
e0001a05 NC |
7956 | for (next_fragP = fragP->fr_next; |
7957 | next_fragP != NULL; | |
7958 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7959 | { |
7960 | if (next_fragP == symbol_get_frag (symbolP)) | |
7961 | return TRUE; | |
7962 | } | |
e0001a05 NC |
7963 | |
7964 | return FALSE; | |
7965 | } | |
7966 | ||
2caa7ca0 BW |
7967 | |
7968 | #define XTINFO_NAME "Xtensa_Info" | |
7969 | #define XTINFO_NAMESZ 12 | |
7970 | #define XTINFO_TYPE 1 | |
7971 | ||
7972 | static void | |
7973 | xtensa_add_config_info (void) | |
7974 | { | |
7975 | asection *info_sec; | |
7976 | char *data, *p; | |
7977 | int sz; | |
7978 | ||
7979 | info_sec = subseg_new (".xtensa.info", 0); | |
7980 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
7981 | ||
7982 | data = xmalloc (100); | |
7983 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
7984 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
7985 | sz = strlen (data) + 1; | |
7986 | ||
7987 | /* Add enough null terminators to pad to a word boundary. */ | |
7988 | do | |
7989 | data[sz++] = 0; | |
7990 | while ((sz & 3) != 0); | |
7991 | ||
7992 | /* Follow the standard note section layout: | |
7993 | First write the length of the name string. */ | |
7994 | p = frag_more (4); | |
7995 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
7996 | ||
7997 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
7998 | p = frag_more (4); | |
7999 | md_number_to_chars (p, (valueT) sz, 4); | |
8000 | ||
8001 | /* Write the note type. */ | |
8002 | p = frag_more (4); | |
8003 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8004 | ||
8005 | /* Write the name field. */ | |
8006 | p = frag_more (XTINFO_NAMESZ); | |
8007 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8008 | ||
8009 | /* Finally, write the descriptor. */ | |
8010 | p = frag_more (sz); | |
8011 | memcpy (p, data, sz); | |
8012 | ||
8013 | free (data); | |
8014 | } | |
8015 | ||
e0001a05 NC |
8016 | \f |
8017 | /* Alignment Functions. */ | |
8018 | ||
d77b99c9 BW |
8019 | static int |
8020 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8021 | { |
03aaa593 BW |
8022 | if (target_size <= 4) |
8023 | return 2; | |
8024 | assert (target_size == 8); | |
8025 | return 3; | |
e0001a05 NC |
8026 | } |
8027 | ||
8028 | ||
d77b99c9 | 8029 | static int |
7fa3d080 BW |
8030 | get_text_align_max_fill_size (int align_pow, |
8031 | bfd_boolean use_nops, | |
8032 | bfd_boolean use_no_density) | |
e0001a05 NC |
8033 | { |
8034 | if (!use_nops) | |
8035 | return (1 << align_pow); | |
8036 | if (use_no_density) | |
8037 | return 3 * (1 << align_pow); | |
8038 | ||
8039 | return 1 + (1 << align_pow); | |
8040 | } | |
8041 | ||
8042 | ||
d77b99c9 BW |
8043 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8044 | target instruction of size "target_size" so that it does not cross a | |
8045 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8046 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8047 | be filled by NOP instructions. */ | |
e0001a05 | 8048 | |
d77b99c9 | 8049 | static int |
7fa3d080 BW |
8050 | get_text_align_fill_size (addressT address, |
8051 | int align_pow, | |
8052 | int target_size, | |
8053 | bfd_boolean use_nops, | |
8054 | bfd_boolean use_no_density) | |
e0001a05 | 8055 | { |
d77b99c9 BW |
8056 | addressT alignment, fill, fill_limit, fill_step; |
8057 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8058 | |
d77b99c9 BW |
8059 | alignment = (1 << align_pow); |
8060 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 8061 | |
e0001a05 NC |
8062 | if (!use_nops) |
8063 | { | |
d77b99c9 BW |
8064 | fill_limit = alignment; |
8065 | fill_step = 1; | |
e0001a05 | 8066 | } |
d77b99c9 | 8067 | else if (!use_no_density) |
e0001a05 | 8068 | { |
d77b99c9 BW |
8069 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8070 | fill_limit = alignment * 2; | |
8071 | fill_step = 1; | |
8072 | skip_one = TRUE; | |
e0001a05 NC |
8073 | } |
8074 | else | |
8075 | { | |
d77b99c9 BW |
8076 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8077 | fill_limit = alignment * 3; | |
8078 | fill_step = 3; | |
8079 | } | |
e0001a05 | 8080 | |
d77b99c9 BW |
8081 | /* Try all fill sizes until finding one that works. */ |
8082 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8083 | { | |
8084 | if (skip_one && fill == 1) | |
8085 | continue; | |
8086 | if ((address + fill) >> align_pow | |
8087 | == (address + fill + target_size - 1) >> align_pow) | |
8088 | return fill; | |
e0001a05 NC |
8089 | } |
8090 | assert (0); | |
8091 | return 0; | |
8092 | } | |
8093 | ||
8094 | ||
664df4e4 BW |
8095 | static int |
8096 | branch_align_power (segT sec) | |
8097 | { | |
8098 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8099 | is aligned to at least an 8-byte boundary, then a branch target need | |
8100 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8101 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8102 | (which may be insufficient, e.g., if the section has no alignment, but | |
8103 | it's good enough). */ | |
8104 | if (xtensa_fetch_width == 8) | |
8105 | { | |
8106 | if (get_recorded_alignment (sec) >= 3) | |
8107 | return 3; | |
8108 | } | |
8109 | else | |
8110 | assert (xtensa_fetch_width == 4); | |
8111 | ||
8112 | return 2; | |
8113 | } | |
8114 | ||
8115 | ||
e0001a05 NC |
8116 | /* This will assert if it is not possible. */ |
8117 | ||
d77b99c9 BW |
8118 | static int |
8119 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8120 | { |
d77b99c9 BW |
8121 | int count = 0; |
8122 | ||
e0001a05 NC |
8123 | if (use_no_density) |
8124 | { | |
8125 | assert (fill_size % 3 == 0); | |
8126 | return (fill_size / 3); | |
8127 | } | |
8128 | ||
8129 | assert (fill_size != 1); /* Bad argument. */ | |
8130 | ||
8131 | while (fill_size > 1) | |
8132 | { | |
d77b99c9 | 8133 | int insn_size = 3; |
e0001a05 NC |
8134 | if (fill_size == 2 || fill_size == 4) |
8135 | insn_size = 2; | |
8136 | fill_size -= insn_size; | |
8137 | count++; | |
8138 | } | |
8139 | assert (fill_size != 1); /* Bad algorithm. */ | |
8140 | return count; | |
8141 | } | |
8142 | ||
8143 | ||
d77b99c9 BW |
8144 | static int |
8145 | get_text_align_nth_nop_size (offsetT fill_size, | |
8146 | int n, | |
7fa3d080 | 8147 | bfd_boolean use_no_density) |
e0001a05 | 8148 | { |
d77b99c9 | 8149 | int count = 0; |
e0001a05 NC |
8150 | |
8151 | if (use_no_density) | |
8152 | return 3; | |
8153 | ||
d77b99c9 BW |
8154 | assert (fill_size != 1); /* Bad argument. */ |
8155 | ||
e0001a05 NC |
8156 | while (fill_size > 1) |
8157 | { | |
d77b99c9 | 8158 | int insn_size = 3; |
e0001a05 NC |
8159 | if (fill_size == 2 || fill_size == 4) |
8160 | insn_size = 2; | |
8161 | fill_size -= insn_size; | |
8162 | count++; | |
8163 | if (n + 1 == count) | |
8164 | return insn_size; | |
8165 | } | |
8166 | assert (0); | |
8167 | return 0; | |
8168 | } | |
8169 | ||
8170 | ||
8171 | /* For the given fragment, find the appropriate address | |
8172 | for it to begin at if we are using NOPs to align it. */ | |
8173 | ||
8174 | static addressT | |
7fa3d080 | 8175 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8176 | { |
43cd72b9 BW |
8177 | /* The rule is: get next fragment's FIRST instruction. Find |
8178 | the smallest number of bytes that need to be added to | |
8179 | ensure that the next fragment's FIRST instruction will fit | |
8180 | in a single word. | |
c138bc38 | 8181 | |
43cd72b9 BW |
8182 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8183 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8184 | |
43cd72b9 BW |
8185 | If the FIRST instruction MIGHT be relaxed, |
8186 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8187 | |
43cd72b9 BW |
8188 | Note again here that LOOP instructions are not bundleable, |
8189 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8190 | |
d77b99c9 | 8191 | int fill_size = 0; |
43cd72b9 BW |
8192 | int first_insn_size; |
8193 | int loop_insn_size; | |
8194 | addressT pre_opcode_bytes; | |
d77b99c9 | 8195 | int align_power; |
43cd72b9 BW |
8196 | fragS *first_insn; |
8197 | xtensa_opcode opcode; | |
8198 | bfd_boolean is_loop; | |
e0001a05 | 8199 | |
43cd72b9 BW |
8200 | assert (fragP->fr_type == rs_machine_dependent); |
8201 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8202 | |
43cd72b9 BW |
8203 | /* Find the loop frag. */ |
8204 | first_insn = next_non_empty_frag (fragP); | |
8205 | /* Now find the first insn frag. */ | |
8206 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8207 | |
43cd72b9 BW |
8208 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8209 | assert (is_loop); | |
8210 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8211 | |
43cd72b9 BW |
8212 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8213 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8214 | |
43cd72b9 BW |
8215 | /* For loops, the alignment depends on the size of the |
8216 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8217 | |
43cd72b9 | 8218 | if (first_insn == NULL) |
03aaa593 BW |
8219 | first_insn_size = xtensa_fetch_width; |
8220 | else | |
8221 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8222 | |
43cd72b9 | 8223 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8224 | align_power = get_text_align_power (first_insn_size); |
8225 | record_alignment (now_seg, align_power); | |
c138bc38 | 8226 | |
43cd72b9 | 8227 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8228 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8229 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8230 | |
8231 | return address + fill_size; | |
8232 | } | |
8233 | ||
8234 | ||
43cd72b9 BW |
8235 | /* 3 mechanisms for relaxing an alignment: |
8236 | ||
8237 | Align to a power of 2. | |
8238 | Align so the next fragment's instruction does not cross a word boundary. | |
8239 | Align the current instruction so that if the next instruction | |
8240 | were 3 bytes, it would not cross a word boundary. | |
8241 | ||
e0001a05 NC |
8242 | We can align with: |
8243 | ||
43cd72b9 BW |
8244 | zeros - This is easy; always insert zeros. |
8245 | nops - 3-byte and 2-byte instructions | |
8246 | 2 - 2-byte nop | |
8247 | 3 - 3-byte nop | |
8248 | 4 - 2 2-byte nops | |
8249 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8250 | widening - widen previous instructions. */ |
8251 | ||
d77b99c9 BW |
8252 | static offsetT |
8253 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8254 | { |
43cd72b9 BW |
8255 | addressT target_address, loop_insn_offset; |
8256 | int target_size; | |
8257 | xtensa_opcode loop_opcode; | |
8258 | bfd_boolean is_loop; | |
d77b99c9 BW |
8259 | int align_power; |
8260 | offsetT opt_diff; | |
5f9084e9 | 8261 | offsetT branch_align; |
e0001a05 | 8262 | |
43cd72b9 BW |
8263 | assert (fragP->fr_type == rs_machine_dependent); |
8264 | switch (fragP->fr_subtype) | |
e0001a05 | 8265 | { |
43cd72b9 BW |
8266 | case RELAX_DESIRE_ALIGN: |
8267 | target_size = next_frag_format_size (fragP); | |
8268 | if (target_size == XTENSA_UNDEFINED) | |
8269 | target_size = 3; | |
664df4e4 BW |
8270 | align_power = branch_align_power (now_seg); |
8271 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8272 | /* Don't count on the section alignment being as large as the target. */ |
8273 | if (target_size > branch_align) | |
8274 | target_size = branch_align; | |
d77b99c9 | 8275 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8276 | target_size, FALSE, FALSE); |
8277 | ||
664df4e4 BW |
8278 | *max_diff = (opt_diff + branch_align |
8279 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8280 | assert (*max_diff >= opt_diff); |
8281 | return opt_diff; | |
e0001a05 | 8282 | |
43cd72b9 | 8283 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8284 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8285 | loop_insn_offset = 0; |
8286 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8287 | assert (is_loop); | |
8288 | ||
8289 | /* If the loop has been expanded then the LOOP instruction | |
8290 | could be at an offset from this fragment. */ | |
8291 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8292 | != RELAX_IMMED) | |
8293 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8294 | ||
43cd72b9 BW |
8295 | /* In an ideal world, which is what we are shooting for here, |
8296 | we wouldn't need to use any NOPs immediately prior to the | |
8297 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8298 | will call get_noop_aligned_address. */ | |
8299 | target_address = | |
8300 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8301 | align_power = get_text_align_power (target_size), |
8302 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8303 | target_size, FALSE, FALSE); |
8304 | ||
8305 | *max_diff = xtensa_fetch_width | |
8306 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8307 | - target_size + opt_diff; | |
8308 | assert (*max_diff >= opt_diff); | |
8309 | return opt_diff; | |
e0001a05 | 8310 | |
43cd72b9 BW |
8311 | default: |
8312 | break; | |
e0001a05 | 8313 | } |
43cd72b9 BW |
8314 | assert (0); |
8315 | return 0; | |
e0001a05 NC |
8316 | } |
8317 | ||
8318 | \f | |
8319 | /* md_relax_frag Hook and Helper Functions. */ | |
8320 | ||
7fa3d080 BW |
8321 | static long relax_frag_loop_align (fragS *, long); |
8322 | static long relax_frag_for_align (fragS *, long); | |
8323 | static long relax_frag_immed | |
8324 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8325 | ||
8326 | ||
e0001a05 NC |
8327 | /* Return the number of bytes added to this fragment, given that the |
8328 | input has been stretched already by "stretch". */ | |
8329 | ||
8330 | long | |
7fa3d080 | 8331 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8332 | { |
43cd72b9 | 8333 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8334 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8335 | long new_stretch = 0; | |
8336 | char *file_name; | |
d77b99c9 BW |
8337 | unsigned line; |
8338 | int lit_size; | |
43cd72b9 BW |
8339 | static xtensa_insnbuf vbuf = NULL; |
8340 | int slot, num_slots; | |
8341 | xtensa_format fmt; | |
e0001a05 NC |
8342 | |
8343 | as_where (&file_name, &line); | |
8344 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8345 | ||
8346 | fragP->tc_frag_data.unreported_expansion = 0; | |
8347 | ||
8348 | switch (fragP->fr_subtype) | |
8349 | { | |
8350 | case RELAX_ALIGN_NEXT_OPCODE: | |
8351 | /* Always convert. */ | |
43cd72b9 BW |
8352 | if (fragP->tc_frag_data.relax_seen) |
8353 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8354 | break; |
8355 | ||
8356 | case RELAX_LOOP_END: | |
8357 | /* Do nothing. */ | |
8358 | break; | |
8359 | ||
8360 | case RELAX_LOOP_END_ADD_NOP: | |
8361 | /* Add a NOP and switch to .fill 0. */ | |
8362 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8363 | frag_wane (fragP); |
e0001a05 NC |
8364 | break; |
8365 | ||
8366 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8367 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8368 | it or not. */ |
8369 | break; | |
8370 | ||
8371 | case RELAX_LITERAL: | |
8372 | case RELAX_LITERAL_FINAL: | |
8373 | return 0; | |
8374 | ||
8375 | case RELAX_LITERAL_NR: | |
8376 | lit_size = 4; | |
8377 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8378 | assert (unreported == lit_size); | |
8379 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8380 | fragP->fr_var -= lit_size; | |
8381 | fragP->fr_fix += lit_size; | |
8382 | new_stretch = 4; | |
8383 | break; | |
8384 | ||
43cd72b9 BW |
8385 | case RELAX_SLOTS: |
8386 | if (vbuf == NULL) | |
8387 | vbuf = xtensa_insnbuf_alloc (isa); | |
8388 | ||
d77b99c9 BW |
8389 | xtensa_insnbuf_from_chars |
8390 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8391 | fmt = xtensa_format_decode (isa, vbuf); |
8392 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8393 | |
43cd72b9 BW |
8394 | for (slot = 0; slot < num_slots; slot++) |
8395 | { | |
8396 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8397 | { | |
8398 | case RELAX_NARROW: | |
8399 | if (fragP->tc_frag_data.relax_seen) | |
8400 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8401 | break; | |
8402 | ||
8403 | case RELAX_IMMED: | |
8404 | case RELAX_IMMED_STEP1: | |
8405 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8406 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8407 | /* Place the immediate. */ |
8408 | new_stretch += relax_frag_immed | |
8409 | (now_seg, fragP, stretch, | |
8410 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8411 | fmt, slot, stretched_p, FALSE); | |
8412 | break; | |
8413 | ||
8414 | default: | |
8415 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8416 | break; | |
8417 | } | |
8418 | } | |
e0001a05 NC |
8419 | break; |
8420 | ||
8421 | case RELAX_LITERAL_POOL_BEGIN: | |
8422 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8423 | case RELAX_MAYBE_UNREACHABLE: |
8424 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8425 | /* No relaxation required. */ |
8426 | break; | |
8427 | ||
43cd72b9 BW |
8428 | case RELAX_FILL_NOP: |
8429 | case RELAX_UNREACHABLE: | |
8430 | if (fragP->tc_frag_data.relax_seen) | |
8431 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8432 | break; | |
8433 | ||
e0001a05 NC |
8434 | default: |
8435 | as_bad (_("bad relaxation state")); | |
8436 | } | |
8437 | ||
43cd72b9 | 8438 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8439 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8440 | { |
8441 | fragP->tc_frag_data.relax_seen = TRUE; | |
8442 | *stretched_p = 1; | |
8443 | } | |
8444 | ||
e0001a05 NC |
8445 | new_logical_line (file_name, line); |
8446 | return new_stretch; | |
8447 | } | |
8448 | ||
8449 | ||
8450 | static long | |
7fa3d080 | 8451 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8452 | { |
8453 | addressT old_address, old_next_address, old_size; | |
8454 | addressT new_address, new_next_address, new_size; | |
8455 | addressT growth; | |
8456 | ||
43cd72b9 BW |
8457 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8458 | section have been done, hopefully eliminating the need for a NOP here. | |
8459 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8460 | |
8461 | /* Calculate the old address of this fragment and the next fragment. */ | |
8462 | old_address = fragP->fr_address - stretch; | |
8463 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8464 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8465 | old_size = old_next_address - old_address; |
8466 | ||
8467 | /* Calculate the new address of this fragment and the next fragment. */ | |
8468 | new_address = fragP->fr_address; | |
8469 | new_next_address = | |
8470 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8471 | new_size = new_next_address - new_address; | |
8472 | ||
8473 | growth = new_size - old_size; | |
8474 | ||
8475 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8476 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8477 | return growth; |
8478 | } | |
8479 | ||
8480 | ||
43cd72b9 | 8481 | /* Add a NOP instruction. */ |
e0001a05 NC |
8482 | |
8483 | static long | |
7fa3d080 | 8484 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8485 | { |
e0001a05 | 8486 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8487 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8488 | assemble_nop (length, nop_buf); | |
e0001a05 | 8489 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8490 | |
e0001a05 NC |
8491 | if (fragP->fr_var < length) |
8492 | { | |
dd49a749 | 8493 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8494 | return 0; |
8495 | } | |
8496 | ||
8497 | fragP->fr_fix += length; | |
8498 | fragP->fr_var -= length; | |
e0001a05 NC |
8499 | return length; |
8500 | } | |
8501 | ||
8502 | ||
7fa3d080 BW |
8503 | static long future_alignment_required (fragS *, long); |
8504 | ||
e0001a05 | 8505 | static long |
7fa3d080 | 8506 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8507 | { |
43cd72b9 BW |
8508 | /* Overview of the relaxation procedure for alignment: |
8509 | We can widen with NOPs or by widening instructions or by filling | |
8510 | bytes after jump instructions. Find the opportune places and widen | |
8511 | them if necessary. */ | |
8512 | ||
8513 | long stretch_me; | |
8514 | long diff; | |
e0001a05 | 8515 | |
43cd72b9 BW |
8516 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8517 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8518 | || (fragP->fr_subtype == RELAX_SLOTS | |
8519 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8520 | ||
8521 | stretch_me = future_alignment_required (fragP, stretch); | |
8522 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8523 | if (diff == 0) | |
8524 | return 0; | |
e0001a05 | 8525 | |
43cd72b9 | 8526 | if (diff < 0) |
e0001a05 | 8527 | { |
43cd72b9 BW |
8528 | /* We expanded on a previous pass. Can we shrink now? */ |
8529 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8530 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8531 | { |
43cd72b9 BW |
8532 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8533 | return -shrink; | |
e0001a05 NC |
8534 | } |
8535 | return 0; | |
8536 | } | |
8537 | ||
43cd72b9 BW |
8538 | /* Below here, diff > 0. */ |
8539 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8540 | |
43cd72b9 | 8541 | return diff; |
e0001a05 NC |
8542 | } |
8543 | ||
8544 | ||
43cd72b9 BW |
8545 | /* Return the address of the next frag that should be aligned. |
8546 | ||
8547 | By "address" we mean the address it _would_ be at if there | |
8548 | is no action taken to align it between here and the target frag. | |
8549 | In other words, if no narrows and no fill nops are used between | |
8550 | here and the frag to align, _even_if_ some of the frags we use | |
8551 | to align targets have already expanded on a previous relaxation | |
8552 | pass. | |
8553 | ||
8554 | Also, count each frag that may be used to help align the target. | |
8555 | ||
8556 | Return 0 if there are no frags left in the chain that need to be | |
8557 | aligned. */ | |
8558 | ||
8559 | static addressT | |
7fa3d080 BW |
8560 | find_address_of_next_align_frag (fragS **fragPP, |
8561 | int *wide_nops, | |
8562 | int *narrow_nops, | |
8563 | int *widens, | |
8564 | bfd_boolean *paddable) | |
e0001a05 | 8565 | { |
43cd72b9 BW |
8566 | fragS *fragP = *fragPP; |
8567 | addressT address = fragP->fr_address; | |
8568 | ||
8569 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8570 | |
8571 | while (fragP) | |
8572 | { | |
8573 | /* Limit this to a small search. */ | |
b5e4a23d | 8574 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8575 | { |
8576 | *fragPP = fragP; | |
8577 | return 0; | |
8578 | } | |
e0001a05 NC |
8579 | address += fragP->fr_fix; |
8580 | ||
43cd72b9 BW |
8581 | if (fragP->fr_type == rs_fill) |
8582 | address += fragP->fr_offset * fragP->fr_var; | |
8583 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8584 | { |
e0001a05 NC |
8585 | switch (fragP->fr_subtype) |
8586 | { | |
43cd72b9 BW |
8587 | case RELAX_UNREACHABLE: |
8588 | *paddable = TRUE; | |
8589 | break; | |
8590 | ||
8591 | case RELAX_FILL_NOP: | |
8592 | (*wide_nops)++; | |
8593 | if (!fragP->tc_frag_data.is_no_density) | |
8594 | (*narrow_nops)++; | |
8595 | break; | |
8596 | ||
8597 | case RELAX_SLOTS: | |
8598 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8599 | { | |
8600 | (*widens)++; | |
8601 | break; | |
8602 | } | |
34e41783 | 8603 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8604 | break; |
8605 | ||
8606 | case RELAX_IMMED: | |
43cd72b9 | 8607 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8608 | break; |
8609 | ||
8610 | case RELAX_ALIGN_NEXT_OPCODE: | |
8611 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8612 | *fragPP = fragP; |
8613 | return address; | |
8614 | ||
8615 | case RELAX_MAYBE_UNREACHABLE: | |
8616 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8617 | /* Do nothing. */ | |
e0001a05 NC |
8618 | break; |
8619 | ||
8620 | default: | |
43cd72b9 BW |
8621 | /* Just punt if we don't know the type. */ |
8622 | *fragPP = fragP; | |
8623 | return 0; | |
e0001a05 | 8624 | } |
43cd72b9 | 8625 | } |
c138bc38 | 8626 | else |
43cd72b9 BW |
8627 | { |
8628 | /* Just punt if we don't know the type. */ | |
8629 | *fragPP = fragP; | |
8630 | return 0; | |
8631 | } | |
8632 | fragP = fragP->fr_next; | |
8633 | } | |
8634 | ||
8635 | *fragPP = fragP; | |
8636 | return 0; | |
8637 | } | |
8638 | ||
8639 | ||
7fa3d080 BW |
8640 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8641 | ||
43cd72b9 | 8642 | static long |
7fa3d080 | 8643 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8644 | { |
8645 | fragS *this_frag = fragP; | |
8646 | long address; | |
8647 | int num_widens = 0; | |
8648 | int wide_nops = 0; | |
8649 | int narrow_nops = 0; | |
8650 | bfd_boolean paddable = FALSE; | |
8651 | offsetT local_opt_diff; | |
8652 | offsetT opt_diff; | |
8653 | offsetT max_diff; | |
8654 | int stretch_amount = 0; | |
8655 | int local_stretch_amount; | |
8656 | int global_stretch_amount; | |
8657 | ||
7fa3d080 BW |
8658 | address = find_address_of_next_align_frag |
8659 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8660 | |
b5e4a23d BW |
8661 | if (!address) |
8662 | { | |
8663 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8664 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8665 | else | |
8666 | frag_wane (this_frag); | |
8667 | } | |
8668 | else | |
43cd72b9 BW |
8669 | { |
8670 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8671 | opt_diff = local_opt_diff; | |
8672 | assert (opt_diff >= 0); | |
8673 | assert (max_diff >= opt_diff); | |
c138bc38 | 8674 | if (max_diff == 0) |
43cd72b9 | 8675 | return 0; |
d2a033cd | 8676 | |
43cd72b9 BW |
8677 | if (fragP) |
8678 | fragP = fragP->fr_next; | |
8679 | ||
8680 | while (fragP && opt_diff < max_diff && address) | |
8681 | { | |
8682 | /* We only use these to determine if we can exit early | |
c138bc38 | 8683 | because there will be plenty of ways to align future |
43cd72b9 | 8684 | align frags. */ |
d77b99c9 | 8685 | int glob_widens = 0; |
43cd72b9 BW |
8686 | int dnn = 0; |
8687 | int dw = 0; | |
8688 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8689 | address = find_address_of_next_align_frag |
8690 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8691 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8692 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8693 | address = 0; |
43cd72b9 | 8694 | |
c138bc38 | 8695 | if (address) |
43cd72b9 BW |
8696 | { |
8697 | offsetT next_m_diff; | |
8698 | offsetT next_o_diff; | |
8699 | ||
8700 | /* Downrange frags haven't had stretch added to them yet. */ | |
8701 | address += stretch; | |
8702 | ||
8703 | /* The address also includes any text expansion from this | |
8704 | frag in a previous pass, but we don't want that. */ | |
8705 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8706 | ||
8707 | /* Assume we are going to move at least opt_diff. In | |
8708 | reality, we might not be able to, but assuming that | |
8709 | we will helps catch cases where moving opt_diff pushes | |
8710 | the next target from aligned to unaligned. */ | |
8711 | address += opt_diff; | |
8712 | ||
8713 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8714 | ||
8715 | /* Now cleanup for the adjustments to address. */ | |
8716 | next_o_diff += opt_diff; | |
8717 | next_m_diff += opt_diff; | |
8718 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8719 | opt_diff = next_o_diff; | |
8720 | if (next_m_diff < max_diff) | |
8721 | max_diff = next_m_diff; | |
8722 | fragP = fragP->fr_next; | |
8723 | } | |
8724 | } | |
d2a033cd | 8725 | |
43cd72b9 BW |
8726 | /* If there are enough wideners in between, do it. */ |
8727 | if (paddable) | |
8728 | { | |
8729 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8730 | { | |
8731 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8732 | return opt_diff; | |
8733 | } | |
8734 | return 0; | |
8735 | } | |
c138bc38 | 8736 | local_stretch_amount |
43cd72b9 BW |
8737 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8738 | num_widens, local_opt_diff); | |
c138bc38 BW |
8739 | global_stretch_amount |
8740 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8741 | num_widens, opt_diff); |
c138bc38 BW |
8742 | /* If the condition below is true, then the frag couldn't |
8743 | stretch the correct amount for the global case, so we just | |
8744 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8745 | the correct alignment in the global case. */ |
8746 | if (global_stretch_amount < local_stretch_amount) | |
8747 | stretch_amount = local_stretch_amount; | |
8748 | else | |
8749 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8750 | |
43cd72b9 BW |
8751 | if (this_frag->fr_subtype == RELAX_SLOTS |
8752 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8753 | assert (stretch_amount <= 1); | |
8754 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8755 | { | |
8756 | if (this_frag->tc_frag_data.is_no_density) | |
8757 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8758 | else | |
8759 | assert (stretch_amount <= 3); | |
8760 | } | |
8761 | } | |
8762 | return stretch_amount; | |
8763 | } | |
8764 | ||
8765 | ||
8766 | /* The idea: widen everything you can to get a target or loop aligned, | |
8767 | then start using NOPs. | |
8768 | ||
8769 | When we must have a NOP, here is a table of how we decide | |
8770 | (so you don't have to fight through the control flow below): | |
8771 | ||
8772 | wide_nops = the number of wide NOPs available for aligning | |
8773 | narrow_nops = the number of narrow NOPs available for aligning | |
8774 | (a subset of wide_nops) | |
8775 | widens = the number of narrow instructions that should be widened | |
8776 | ||
8777 | Desired wide narrow | |
8778 | Diff nop nop widens | |
8779 | 1 0 0 1 | |
8780 | 2 0 1 0 | |
8781 | 3a 1 0 0 | |
8782 | b 0 1 1 (case 3a makes this case unnecessary) | |
8783 | 4a 1 0 1 | |
8784 | b 0 2 0 | |
8785 | c 0 1 2 (case 4a makes this case unnecessary) | |
8786 | 5a 1 0 2 | |
8787 | b 1 1 0 | |
8788 | c 0 2 1 (case 5b makes this case unnecessary) | |
8789 | 6a 2 0 0 | |
8790 | b 1 0 3 | |
708587a4 | 8791 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8792 | d 1 1 1 (case 6a makes this case unnecessary) |
8793 | e 0 2 2 (case 6a makes this case unnecessary) | |
8794 | f 0 3 0 (case 6a makes this case unnecessary) | |
8795 | 7a 1 0 4 | |
8796 | b 2 0 1 | |
8797 | c 1 1 2 (case 7b makes this case unnecessary) | |
8798 | d 0 1 5 (case 7a makes this case unnecessary) | |
8799 | e 0 2 3 (case 7b makes this case unnecessary) | |
8800 | f 0 3 1 (case 7b makes this case unnecessary) | |
8801 | g 1 2 1 (case 7b makes this case unnecessary) | |
8802 | */ | |
8803 | ||
8804 | static long | |
7fa3d080 BW |
8805 | bytes_to_stretch (fragS *this_frag, |
8806 | int wide_nops, | |
8807 | int narrow_nops, | |
8808 | int num_widens, | |
8809 | int desired_diff) | |
43cd72b9 BW |
8810 | { |
8811 | int bytes_short = desired_diff - num_widens; | |
8812 | ||
8813 | assert (desired_diff >= 0 && desired_diff < 8); | |
8814 | if (desired_diff == 0) | |
8815 | return 0; | |
c138bc38 | 8816 | |
43cd72b9 | 8817 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8818 | |
43cd72b9 BW |
8819 | /* Always prefer widening to NOP-filling. */ |
8820 | if (bytes_short < 0) | |
8821 | { | |
8822 | /* There are enough RELAX_NARROW frags after this one | |
8823 | to align the target without widening this frag in any way. */ | |
8824 | return 0; | |
8825 | } | |
c138bc38 | 8826 | |
43cd72b9 BW |
8827 | if (bytes_short == 0) |
8828 | { | |
8829 | /* Widen every narrow between here and the align target | |
8830 | and the align target will be properly aligned. */ | |
8831 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8832 | return 0; | |
8833 | else | |
8834 | return 1; | |
8835 | } | |
c138bc38 | 8836 | |
43cd72b9 BW |
8837 | /* From here we will need at least one NOP to get an alignment. |
8838 | However, we may not be able to align at all, in which case, | |
8839 | don't widen. */ | |
8840 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8841 | { | |
8842 | switch (desired_diff) | |
8843 | { | |
8844 | case 1: | |
8845 | return 0; | |
8846 | case 2: | |
8847 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8848 | return 2; /* case 2 */ | |
8849 | return 0; | |
c138bc38 | 8850 | case 3: |
43cd72b9 BW |
8851 | if (wide_nops > 1) |
8852 | return 0; | |
8853 | else | |
8854 | return 3; /* case 3a */ | |
8855 | case 4: | |
8856 | if (num_widens >= 1 && wide_nops == 1) | |
8857 | return 3; /* case 4a */ | |
8858 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8859 | return 2; /* case 4b */ | |
8860 | return 0; | |
8861 | case 5: | |
8862 | if (num_widens >= 2 && wide_nops == 1) | |
8863 | return 3; /* case 5a */ | |
c138bc38 | 8864 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8865 | between here and the align target? */ |
8866 | if (wide_nops < 2 || narrow_nops == 0) | |
8867 | return 0; | |
8868 | /* Are there other nops closer that can serve instead? */ | |
8869 | if (wide_nops > 2 && narrow_nops > 1) | |
8870 | return 0; | |
8871 | /* Take the density one first, because there might not be | |
8872 | another density one available. */ | |
8873 | if (!this_frag->tc_frag_data.is_no_density) | |
8874 | return 2; /* case 5b narrow */ | |
8875 | else | |
8876 | return 3; /* case 5b wide */ | |
8877 | return 0; | |
8878 | case 6: | |
8879 | if (wide_nops == 2) | |
8880 | return 3; /* case 6a */ | |
8881 | else if (num_widens >= 3 && wide_nops == 1) | |
8882 | return 3; /* case 6b */ | |
8883 | return 0; | |
8884 | case 7: | |
8885 | if (wide_nops == 1 && num_widens >= 4) | |
8886 | return 3; /* case 7a */ | |
8887 | else if (wide_nops == 2 && num_widens >= 1) | |
8888 | return 3; /* case 7b */ | |
8889 | return 0; | |
e0001a05 | 8890 | default: |
43cd72b9 | 8891 | assert (0); |
e0001a05 | 8892 | } |
e0001a05 | 8893 | } |
43cd72b9 BW |
8894 | else |
8895 | { | |
c138bc38 | 8896 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8897 | this instruction to help? |
e0001a05 | 8898 | |
03aaa593 | 8899 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8900 | switch (desired_diff) |
8901 | { | |
8902 | case 1: | |
8903 | assert (0); | |
8904 | return 0; | |
8905 | case 2: | |
8906 | case 3: | |
8907 | return 0; | |
8908 | case 4: | |
8909 | if (wide_nops >= 1 && num_widens == 1) | |
8910 | return 1; /* case 4a */ | |
8911 | return 0; | |
8912 | case 5: | |
8913 | if (wide_nops >= 1 && num_widens == 2) | |
8914 | return 1; /* case 5a */ | |
8915 | return 0; | |
8916 | case 6: | |
8917 | if (wide_nops >= 2) | |
8918 | return 0; /* case 6a */ | |
8919 | else if (wide_nops >= 1 && num_widens == 3) | |
8920 | return 1; /* case 6b */ | |
8921 | return 0; | |
8922 | case 7: | |
8923 | if (wide_nops >= 1 && num_widens == 4) | |
8924 | return 1; /* case 7a */ | |
8925 | else if (wide_nops >= 2 && num_widens == 1) | |
8926 | return 1; /* case 7b */ | |
8927 | return 0; | |
8928 | default: | |
8929 | assert (0); | |
8930 | return 0; | |
8931 | } | |
8932 | } | |
8933 | assert (0); | |
8934 | return 0; | |
e0001a05 NC |
8935 | } |
8936 | ||
8937 | ||
8938 | static long | |
7fa3d080 BW |
8939 | relax_frag_immed (segT segP, |
8940 | fragS *fragP, | |
8941 | long stretch, | |
8942 | int min_steps, | |
8943 | xtensa_format fmt, | |
8944 | int slot, | |
8945 | int *stretched_p, | |
8946 | bfd_boolean estimate_only) | |
e0001a05 | 8947 | { |
43cd72b9 | 8948 | TInsn tinsn; |
e0001a05 NC |
8949 | int old_size; |
8950 | bfd_boolean negatable_branch = FALSE; | |
8951 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8952 | bfd_boolean wide_insn = FALSE; |
8953 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8954 | IStack istack; |
8955 | offsetT frag_offset; | |
8956 | int num_steps; | |
8957 | fragS *lit_fragP; | |
8958 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8959 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8960 | |
8961 | assert (fragP->fr_opcode != NULL); | |
8962 | ||
b5e4a23d BW |
8963 | xg_clear_vinsn (&cur_vinsn); |
8964 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8965 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8966 | wide_insn = TRUE; |
8967 | ||
b5e4a23d | 8968 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8969 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8970 | |
64b607e6 | 8971 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 8972 | return 0; |
e0001a05 | 8973 | |
b08b5071 | 8974 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8975 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8976 | |
43cd72b9 | 8977 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8978 | |
43cd72b9 | 8979 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8980 | |
8981 | /* Special case: replace a branch to the next instruction with a NOP. | |
8982 | This is required to work around a hardware bug in T1040.0 and also | |
8983 | serves as an optimization. */ | |
8984 | ||
8985 | if (branch_jmp_to_next | |
8986 | && ((old_size == 2) || (old_size == 3)) | |
8987 | && !next_frag_is_loop_target (fragP)) | |
8988 | return 0; | |
8989 | ||
8990 | /* Here is the fun stuff: Get the immediate field from this | |
8991 | instruction. If it fits, we are done. If not, find the next | |
8992 | instruction sequence that fits. */ | |
8993 | ||
8994 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8995 | istack_init (&istack); | |
43cd72b9 | 8996 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8997 | min_steps, stretch); |
8998 | if (num_steps < min_steps) | |
8999 | { | |
9000 | as_fatal (_("internal error: relaxation failed")); | |
9001 | return 0; | |
9002 | } | |
9003 | ||
9004 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
9005 | { | |
9006 | as_fatal (_("internal error: relaxation requires too many steps")); | |
9007 | return 0; | |
9008 | } | |
9009 | ||
43cd72b9 | 9010 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9011 | |
9012 | /* Figure out the number of bytes needed. */ | |
9013 | lit_fragP = 0; | |
e0001a05 | 9014 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
9015 | literal_diff = |
9016 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9017 | first = 0; | |
9018 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9019 | first++; | |
9020 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
9021 | if (wide_insn) | |
9022 | { | |
9023 | num_text_bytes += old_size; | |
9024 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9025 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
9026 | } | |
9027 | total_text_diff = num_text_bytes - old_size; | |
9028 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9029 | |
9030 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
9031 | assert (num_text_bytes >= 0); |
9032 | assert (literal_diff >= 0); | |
9033 | assert (total_text_diff >= 0); | |
e0001a05 | 9034 | |
43cd72b9 BW |
9035 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9036 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9037 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
9038 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9039 | |
9040 | /* Find the associated expandable literal for this. */ | |
9041 | if (literal_diff != 0) | |
9042 | { | |
43cd72b9 | 9043 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9044 | if (lit_fragP) |
9045 | { | |
9046 | assert (literal_diff == 4); | |
9047 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
9048 | ||
9049 | /* We expect that the literal section state has NOT been | |
9050 | modified yet. */ | |
9051 | assert (lit_fragP->fr_type == rs_machine_dependent | |
9052 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
9053 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9054 | ||
9055 | /* We need to mark this section for another iteration | |
9056 | of relaxation. */ | |
9057 | (*stretched_p)++; | |
9058 | } | |
9059 | } | |
9060 | ||
43cd72b9 | 9061 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9062 | update_next_frag_state (fragP); |
e0001a05 | 9063 | |
43cd72b9 | 9064 | return this_text_diff; |
e0001a05 NC |
9065 | } |
9066 | ||
9067 | \f | |
9068 | /* md_convert_frag Hook and Helper Functions. */ | |
9069 | ||
7fa3d080 BW |
9070 | static void convert_frag_align_next_opcode (fragS *); |
9071 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9072 | static void convert_frag_fill_nop (fragS *); | |
9073 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9074 | ||
e0001a05 | 9075 | void |
7fa3d080 | 9076 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9077 | { |
43cd72b9 BW |
9078 | static xtensa_insnbuf vbuf = NULL; |
9079 | xtensa_isa isa = xtensa_default_isa; | |
9080 | int slot; | |
9081 | int num_slots; | |
9082 | xtensa_format fmt; | |
e0001a05 | 9083 | char *file_name; |
d77b99c9 | 9084 | unsigned line; |
e0001a05 NC |
9085 | |
9086 | as_where (&file_name, &line); | |
9087 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9088 | ||
9089 | switch (fragp->fr_subtype) | |
9090 | { | |
9091 | case RELAX_ALIGN_NEXT_OPCODE: | |
9092 | /* Always convert. */ | |
9093 | convert_frag_align_next_opcode (fragp); | |
9094 | break; | |
9095 | ||
9096 | case RELAX_DESIRE_ALIGN: | |
9097 | /* Do nothing. If not aligned already, too bad. */ | |
9098 | break; | |
9099 | ||
43cd72b9 BW |
9100 | case RELAX_LITERAL: |
9101 | case RELAX_LITERAL_FINAL: | |
9102 | break; | |
9103 | ||
9104 | case RELAX_SLOTS: | |
9105 | if (vbuf == NULL) | |
9106 | vbuf = xtensa_insnbuf_alloc (isa); | |
9107 | ||
d77b99c9 BW |
9108 | xtensa_insnbuf_from_chars |
9109 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9110 | fmt = xtensa_format_decode (isa, vbuf); |
9111 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9112 | ||
9113 | for (slot = 0; slot < num_slots; slot++) | |
9114 | { | |
9115 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9116 | { | |
9117 | case RELAX_NARROW: | |
9118 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9119 | break; | |
9120 | ||
9121 | case RELAX_IMMED: | |
9122 | case RELAX_IMMED_STEP1: | |
9123 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9124 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9125 | /* Place the immediate. */ |
9126 | convert_frag_immed | |
9127 | (sec, fragp, | |
9128 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9129 | fmt, slot); | |
9130 | break; | |
9131 | ||
9132 | default: | |
9133 | /* This is OK because some slots could have | |
9134 | relaxations and others have none. */ | |
9135 | break; | |
9136 | } | |
9137 | } | |
9138 | break; | |
9139 | ||
9140 | case RELAX_UNREACHABLE: | |
9141 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9142 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9143 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9144 | frag_wane (fragp); | |
e0001a05 NC |
9145 | break; |
9146 | ||
43cd72b9 BW |
9147 | case RELAX_MAYBE_UNREACHABLE: |
9148 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9149 | frag_wane (fragp); | |
e0001a05 NC |
9150 | break; |
9151 | ||
43cd72b9 BW |
9152 | case RELAX_FILL_NOP: |
9153 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9154 | break; |
9155 | ||
9156 | case RELAX_LITERAL_NR: | |
9157 | if (use_literal_section) | |
9158 | { | |
9159 | /* This should have been handled during relaxation. When | |
9160 | relaxing a code segment, literals sometimes need to be | |
9161 | added to the corresponding literal segment. If that | |
9162 | literal segment has already been relaxed, then we end up | |
9163 | in this situation. Marking the literal segments as data | |
9164 | would make this happen less often (since GAS always relaxes | |
9165 | code before data), but we could still get into trouble if | |
9166 | there are instructions in a segment that is not marked as | |
9167 | containing code. Until we can implement a better solution, | |
9168 | cheat and adjust the addresses of all the following frags. | |
9169 | This could break subsequent alignments, but the linker's | |
9170 | literal coalescing will do that anyway. */ | |
9171 | ||
9172 | fragS *f; | |
9173 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9174 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9175 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9176 | fragp->fr_var -= 4; | |
9177 | fragp->fr_fix += 4; | |
9178 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9179 | f->fr_address += 4; | |
9180 | } | |
9181 | else | |
9182 | as_bad (_("invalid relaxation fragment result")); | |
9183 | break; | |
9184 | } | |
9185 | ||
9186 | fragp->fr_var = 0; | |
9187 | new_logical_line (file_name, line); | |
9188 | } | |
9189 | ||
9190 | ||
7fa3d080 BW |
9191 | static void |
9192 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9193 | { |
9194 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9195 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9196 | addressT aligned_address; | |
d77b99c9 BW |
9197 | offsetT fill_size; |
9198 | int nop, nop_count; | |
e0001a05 NC |
9199 | |
9200 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9201 | fragp->fr_fix); | |
9202 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9203 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9204 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9205 | ||
d77b99c9 | 9206 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9207 | { |
d77b99c9 BW |
9208 | int nop_size; |
9209 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9210 | |
9211 | assemble_nop (nop_size, nop_buf); | |
9212 | nop_buf += nop_size; | |
9213 | } | |
9214 | ||
9215 | fragp->fr_fix += fill_size; | |
9216 | fragp->fr_var -= fill_size; | |
9217 | } | |
9218 | ||
9219 | ||
9220 | static void | |
7fa3d080 | 9221 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9222 | { |
43cd72b9 | 9223 | TInsn tinsn, single_target; |
84b08ed9 | 9224 | int size, old_size, diff; |
e0001a05 NC |
9225 | offsetT frag_offset; |
9226 | ||
43cd72b9 BW |
9227 | assert (slot == 0); |
9228 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9229 | ||
b5e4a23d | 9230 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9231 | { |
9232 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9233 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9234 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9235 | fmt, slot); | |
9236 | return; | |
9237 | } | |
9238 | ||
9239 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9240 | { |
9241 | /* No conversion. */ | |
9242 | fragP->fr_var = 0; | |
9243 | return; | |
9244 | } | |
9245 | ||
9246 | assert (fragP->fr_opcode != NULL); | |
9247 | ||
43cd72b9 BW |
9248 | /* Frags in this relaxation state should only contain |
9249 | single instruction bundles. */ | |
9250 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9251 | |
9252 | /* Just convert it to a wide form.... */ | |
9253 | size = 0; | |
43cd72b9 | 9254 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9255 | |
9256 | tinsn_init (&single_target); | |
9257 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9258 | ||
84b08ed9 | 9259 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9260 | { |
9261 | as_bad (_("unable to widen instruction")); | |
9262 | return; | |
9263 | } | |
9264 | ||
9265 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9266 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9267 | frag_offset, TRUE); | |
e0001a05 NC |
9268 | |
9269 | diff = size - old_size; | |
9270 | assert (diff >= 0); | |
9271 | assert (diff <= fragP->fr_var); | |
9272 | fragP->fr_var -= diff; | |
9273 | fragP->fr_fix += diff; | |
9274 | ||
9275 | /* clean it up */ | |
9276 | fragP->fr_var = 0; | |
9277 | } | |
9278 | ||
9279 | ||
9280 | static void | |
7fa3d080 | 9281 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9282 | { |
9283 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9284 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9285 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9286 | - fragP->fr_address - fragP->fr_fix)); | |
9287 | if (size == 0) | |
9288 | { | |
9289 | /* No conversion. */ | |
9290 | fragP->fr_var = 0; | |
9291 | return; | |
9292 | } | |
9293 | assemble_nop (size, loc); | |
9294 | fragP->tc_frag_data.is_insn = TRUE; | |
9295 | fragP->fr_var -= size; | |
9296 | fragP->fr_fix += size; | |
9297 | frag_wane (fragP); | |
9298 | } | |
9299 | ||
9300 | ||
7fa3d080 BW |
9301 | static fixS *fix_new_exp_in_seg |
9302 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9303 | bfd_reloc_code_real_type); | |
9304 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9305 | ||
43cd72b9 | 9306 | static void |
7fa3d080 BW |
9307 | convert_frag_immed (segT segP, |
9308 | fragS *fragP, | |
9309 | int min_steps, | |
9310 | xtensa_format fmt, | |
9311 | int slot) | |
e0001a05 NC |
9312 | { |
9313 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9314 | TInsn orig_tinsn; |
e0001a05 | 9315 | bfd_boolean expanded = FALSE; |
e0001a05 | 9316 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9317 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9318 | xtensa_isa isa = xtensa_default_isa; |
9319 | bfd_boolean wide_insn = FALSE; | |
9320 | int bytes; | |
9321 | bfd_boolean is_loop; | |
e0001a05 | 9322 | |
43cd72b9 | 9323 | assert (fr_opcode != NULL); |
e0001a05 | 9324 | |
b5e4a23d | 9325 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9326 | |
b5e4a23d | 9327 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9328 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9329 | wide_insn = TRUE; |
e0001a05 | 9330 | |
b5e4a23d | 9331 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9332 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9333 | ||
9334 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9335 | |
b08b5071 | 9336 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9337 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9338 | |
9339 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9340 | { | |
9341 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9342 | bytes = xtensa_format_length (isa, fmt); |
9343 | if (bytes >= 4) | |
9344 | { | |
b5e4a23d BW |
9345 | cur_vinsn.slots[slot].opcode = |
9346 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9347 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9348 | } |
9349 | else | |
9350 | { | |
9351 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9352 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9353 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9354 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9355 | } | |
e7da6241 | 9356 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9357 | xtensa_insnbuf_to_chars |
b5e4a23d | 9358 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9359 | fragP->fr_var = 0; |
9360 | } | |
7c834684 | 9361 | else |
e0001a05 | 9362 | { |
43cd72b9 BW |
9363 | /* Here is the fun stuff: Get the immediate field from this |
9364 | instruction. If it fits, we're done. If not, find the next | |
9365 | instruction sequence that fits. */ | |
9366 | ||
e0001a05 NC |
9367 | IStack istack; |
9368 | int i; | |
9369 | symbolS *lit_sym = NULL; | |
9370 | int total_size = 0; | |
43cd72b9 | 9371 | int target_offset = 0; |
e0001a05 NC |
9372 | int old_size; |
9373 | int diff; | |
9374 | symbolS *gen_label = NULL; | |
9375 | offsetT frag_offset; | |
43cd72b9 BW |
9376 | bfd_boolean first = TRUE; |
9377 | bfd_boolean last_is_jump; | |
e0001a05 | 9378 | |
43cd72b9 | 9379 | /* It does not fit. Find something that does and |
e0001a05 | 9380 | convert immediately. */ |
43cd72b9 | 9381 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9382 | istack_init (&istack); |
43cd72b9 | 9383 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9384 | segP, fragP, frag_offset, min_steps, 0); |
9385 | ||
43cd72b9 | 9386 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9387 | |
9388 | /* Assemble this right inline. */ | |
9389 | ||
9390 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9391 | target_offset = 0; |
e0001a05 NC |
9392 | for (i = 0; i < istack.ninsn; i++) |
9393 | { | |
43cd72b9 | 9394 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9395 | fragS *lit_frag; |
9396 | ||
43cd72b9 | 9397 | switch (tinsn->insn_type) |
e0001a05 NC |
9398 | { |
9399 | case ITYPE_LITERAL: | |
9400 | if (lit_sym != NULL) | |
9401 | as_bad (_("multiple literals in expansion")); | |
9402 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9403 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9404 | if (lit_frag == NULL) |
9405 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9406 | if (tinsn->ntok != 1) |
e0001a05 NC |
9407 | as_bad (_("number of literal tokens != 1")); |
9408 | ||
9409 | /* Set the literal symbol and add a fixup. */ | |
9410 | lit_sym = lit_frag->fr_symbol; | |
9411 | break; | |
9412 | ||
9413 | case ITYPE_LABEL: | |
43cd72b9 BW |
9414 | if (align_targets && !is_loop) |
9415 | { | |
9416 | fragS *unreach = fragP->fr_next; | |
9417 | while (!(unreach->fr_type == rs_machine_dependent | |
9418 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9419 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9420 | { | |
9421 | unreach = unreach->fr_next; | |
9422 | } | |
9423 | ||
9424 | assert (unreach->fr_type == rs_machine_dependent | |
9425 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9426 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9427 | ||
9428 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9429 | } | |
e0001a05 NC |
9430 | assert (gen_label == NULL); |
9431 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9432 | fr_opcode - fragP->fr_literal |
9433 | + target_offset, fragP); | |
e0001a05 NC |
9434 | break; |
9435 | ||
9436 | case ITYPE_INSN: | |
43cd72b9 BW |
9437 | if (first && wide_insn) |
9438 | { | |
9439 | target_offset += xtensa_format_length (isa, fmt); | |
9440 | first = FALSE; | |
9441 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9442 | target_offset += xg_get_single_size (tinsn->opcode); | |
9443 | } | |
9444 | else | |
9445 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9446 | break; |
9447 | } | |
9448 | } | |
9449 | ||
9450 | total_size = 0; | |
43cd72b9 BW |
9451 | first = TRUE; |
9452 | last_is_jump = FALSE; | |
e0001a05 NC |
9453 | for (i = 0; i < istack.ninsn; i++) |
9454 | { | |
43cd72b9 | 9455 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9456 | fragS *lit_frag; |
9457 | int size; | |
9458 | segT target_seg; | |
43cd72b9 | 9459 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9460 | |
43cd72b9 | 9461 | switch (tinsn->insn_type) |
e0001a05 NC |
9462 | { |
9463 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9464 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9465 | /* Already checked. */ | |
e0001a05 NC |
9466 | assert (lit_frag != NULL); |
9467 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9468 | assert (tinsn->ntok == 1); |
9469 | /* Add a fixup. */ | |
e0001a05 NC |
9470 | target_seg = S_GET_SEGMENT (lit_sym); |
9471 | assert (target_seg); | |
bbdd25a8 | 9472 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op); |
e0001a05 | 9473 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9474 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9475 | break; |
9476 | ||
9477 | case ITYPE_LABEL: | |
9478 | break; | |
9479 | ||
9480 | case ITYPE_INSN: | |
43cd72b9 BW |
9481 | xg_resolve_labels (tinsn, gen_label); |
9482 | xg_resolve_literals (tinsn, lit_sym); | |
9483 | if (wide_insn && first) | |
9484 | { | |
9485 | first = FALSE; | |
9486 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9487 | { | |
b5e4a23d | 9488 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9489 | } |
9490 | else | |
9491 | { | |
b5e4a23d | 9492 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9493 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9494 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9495 | } |
b5e4a23d BW |
9496 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9497 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9498 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9499 | fragP->tc_frag_data.is_insn = TRUE; |
9500 | size = xtensa_format_length (isa, fmt); | |
9501 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9502 | { | |
43cd72b9 | 9503 | xg_emit_insn_to_buf |
b2d179be | 9504 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9505 | immed_instr - fragP->fr_literal + size, TRUE); |
9506 | size += xg_get_single_size (tinsn->opcode); | |
9507 | } | |
9508 | } | |
9509 | else | |
9510 | { | |
43cd72b9 | 9511 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9512 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9513 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9514 | } |
e0001a05 | 9515 | immed_instr += size; |
43cd72b9 | 9516 | total_size += size; |
e0001a05 NC |
9517 | break; |
9518 | } | |
9519 | } | |
9520 | ||
9521 | diff = total_size - old_size; | |
9522 | assert (diff >= 0); | |
9523 | if (diff != 0) | |
9524 | expanded = TRUE; | |
9525 | assert (diff <= fragP->fr_var); | |
9526 | fragP->fr_var -= diff; | |
9527 | fragP->fr_fix += diff; | |
9528 | } | |
9529 | ||
e0001a05 | 9530 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9531 | if (is_loop) |
e0001a05 NC |
9532 | { |
9533 | symbolS *sym; | |
43cd72b9 | 9534 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9535 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9536 | { | |
9537 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9538 | return; | |
9539 | } | |
43cd72b9 | 9540 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9541 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9542 | { | |
9543 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9544 | return; | |
9545 | } | |
9546 | } | |
9547 | ||
43cd72b9 BW |
9548 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9549 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9550 | |
43cd72b9 | 9551 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9552 | { |
9553 | /* Add an expansion note on the expanded instruction. */ | |
9554 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9555 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9556 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9557 | } |
9558 | } | |
9559 | ||
9560 | ||
9561 | /* Add a new fix expression into the desired segment. We have to | |
9562 | switch to that segment to do this. */ | |
9563 | ||
9564 | static fixS * | |
7fa3d080 BW |
9565 | fix_new_exp_in_seg (segT new_seg, |
9566 | subsegT new_subseg, | |
9567 | fragS *frag, | |
9568 | int where, | |
9569 | int size, | |
9570 | expressionS *exp, | |
9571 | int pcrel, | |
9572 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9573 | { |
9574 | fixS *new_fix; | |
9575 | segT seg = now_seg; | |
9576 | subsegT subseg = now_subseg; | |
43cd72b9 | 9577 | |
e0001a05 NC |
9578 | assert (new_seg != 0); |
9579 | subseg_set (new_seg, new_subseg); | |
9580 | ||
e0001a05 NC |
9581 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9582 | subseg_set (seg, subseg); | |
9583 | return new_fix; | |
9584 | } | |
9585 | ||
9586 | ||
43cd72b9 BW |
9587 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9588 | ||
9589 | loop as, .L1 | |
9590 | .L0: | |
9591 | rsr as, LEND | |
9592 | wsr as, LBEG | |
9593 | addi as, as, lo8 (label-.L1) | |
9594 | addmi as, as, mid8 (label-.L1) | |
9595 | wsr as, LEND | |
9596 | isync | |
9597 | rsr as, LCOUNT | |
9598 | addi as, as, 1 | |
9599 | .L1: | |
9600 | <<body>> | |
9601 | label: | |
9602 | */ | |
e0001a05 NC |
9603 | |
9604 | static void | |
7fa3d080 | 9605 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9606 | { |
9607 | TInsn loop_insn; | |
9608 | TInsn addi_insn; | |
9609 | TInsn addmi_insn; | |
9610 | unsigned long target; | |
9611 | static xtensa_insnbuf insnbuf = NULL; | |
9612 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9613 | xtensa_isa isa = xtensa_default_isa; | |
9614 | addressT loop_offset; | |
9615 | addressT addi_offset = 9; | |
9616 | addressT addmi_offset = 12; | |
43cd72b9 | 9617 | fragS *next_fragP; |
d77b99c9 | 9618 | int target_count; |
e0001a05 NC |
9619 | |
9620 | if (!insnbuf) | |
9621 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9622 | ||
9623 | /* Get the loop offset. */ | |
43cd72b9 | 9624 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9625 | |
43cd72b9 BW |
9626 | /* Validate that there really is a LOOP at the loop_offset. Because |
9627 | loops are not bundleable, we can assume that the instruction will be | |
9628 | in slot 0. */ | |
9629 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9630 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9631 | ||
9632 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9633 | addi_offset += loop_offset; |
9634 | addmi_offset += loop_offset; | |
9635 | ||
43cd72b9 | 9636 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9637 | if (tinsn->tok[1].X_op == O_constant) |
9638 | target = tinsn->tok[1].X_add_number; | |
9639 | else if (tinsn->tok[1].X_op == O_symbol) | |
9640 | { | |
9641 | /* Find the fragment. */ | |
9642 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9643 | assert (S_GET_SEGMENT (sym) == segP | |
9644 | || S_GET_SEGMENT (sym) == absolute_section); | |
9645 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9646 | } | |
9647 | else | |
9648 | { | |
9649 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9650 | target = 0; | |
9651 | } | |
e0001a05 | 9652 | |
e0001a05 NC |
9653 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9654 | loop_length_hi = loop_length & ~0x0ff; | |
9655 | loop_length_lo = loop_length & 0x0ff; | |
9656 | if (loop_length_lo >= 128) | |
9657 | { | |
9658 | loop_length_lo -= 256; | |
9659 | loop_length_hi += 256; | |
9660 | } | |
9661 | ||
43cd72b9 | 9662 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9663 | 32512. If the loop is larger than that, then we just fail. */ |
9664 | if (loop_length_hi > 32512) | |
9665 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9666 | _("loop too long for LOOP instruction")); | |
9667 | ||
43cd72b9 | 9668 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9669 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9670 | ||
43cd72b9 | 9671 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9672 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9673 | ||
9674 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9675 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9676 | |
e0001a05 | 9677 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9678 | xtensa_insnbuf_to_chars |
9679 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9680 | |
9681 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9682 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9683 | xtensa_insnbuf_to_chars |
9684 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9685 | |
9686 | /* Walk through all of the frags from here to the loop end | |
9687 | and mark them as no_transform to keep them from being modified | |
9688 | by the linker. If we ever have a relocation for the | |
9689 | addi/addmi of the difference of two symbols we can remove this. */ | |
9690 | ||
9691 | target_count = 0; | |
9692 | for (next_fragP = fragP; next_fragP != NULL; | |
9693 | next_fragP = next_fragP->fr_next) | |
9694 | { | |
b08b5071 | 9695 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9696 | if (next_fragP->tc_frag_data.is_loop_target) |
9697 | target_count++; | |
9698 | if (target_count == 2) | |
9699 | break; | |
9700 | } | |
e0001a05 NC |
9701 | } |
9702 | ||
b08b5071 BW |
9703 | \f |
9704 | /* A map that keeps information on a per-subsegment basis. This is | |
9705 | maintained during initial assembly, but is invalid once the | |
9706 | subsegments are smashed together. I.E., it cannot be used during | |
9707 | the relaxation. */ | |
e0001a05 | 9708 | |
b08b5071 | 9709 | typedef struct subseg_map_struct |
e0001a05 | 9710 | { |
b08b5071 BW |
9711 | /* the key */ |
9712 | segT seg; | |
9713 | subsegT subseg; | |
e0001a05 | 9714 | |
b08b5071 BW |
9715 | /* the data */ |
9716 | unsigned flags; | |
9717 | float total_freq; /* fall-through + branch target frequency */ | |
9718 | float target_freq; /* branch target frequency alone */ | |
9719 | ||
9720 | struct subseg_map_struct *next; | |
9721 | } subseg_map; | |
e0001a05 | 9722 | |
e0001a05 | 9723 | |
e0001a05 NC |
9724 | static subseg_map *sseg_map = NULL; |
9725 | ||
43cd72b9 | 9726 | static subseg_map * |
7fa3d080 | 9727 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9728 | { |
9729 | subseg_map *subseg_e; | |
9730 | ||
9731 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9732 | { |
43cd72b9 | 9733 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9734 | break; |
e0001a05 | 9735 | } |
b08b5071 BW |
9736 | return subseg_e; |
9737 | } | |
9738 | ||
9739 | ||
9740 | static subseg_map * | |
9741 | add_subseg_info (segT seg, subsegT subseg) | |
9742 | { | |
9743 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9744 | memset (subseg_e, 0, sizeof (subseg_map)); |
9745 | subseg_e->seg = seg; | |
9746 | subseg_e->subseg = subseg; | |
9747 | subseg_e->flags = 0; | |
9748 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9749 | subseg_e->target_freq = 1.0; |
9750 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9751 | subseg_e->next = sseg_map; |
9752 | sseg_map = subseg_e; | |
43cd72b9 BW |
9753 | return subseg_e; |
9754 | } | |
e0001a05 | 9755 | |
7fa3d080 BW |
9756 | |
9757 | static unsigned | |
9758 | get_last_insn_flags (segT seg, subsegT subseg) | |
9759 | { | |
9760 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9761 | if (subseg_e) |
9762 | return subseg_e->flags; | |
9763 | return 0; | |
7fa3d080 BW |
9764 | } |
9765 | ||
9766 | ||
43cd72b9 | 9767 | static void |
7fa3d080 BW |
9768 | set_last_insn_flags (segT seg, |
9769 | subsegT subseg, | |
9770 | unsigned fl, | |
9771 | bfd_boolean val) | |
43cd72b9 BW |
9772 | { |
9773 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9774 | if (! subseg_e) |
9775 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9776 | if (val) |
9777 | subseg_e->flags |= fl; | |
9778 | else | |
9779 | subseg_e->flags &= ~fl; | |
9780 | } | |
9781 | ||
b08b5071 BW |
9782 | |
9783 | static float | |
9784 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9785 | { | |
9786 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9787 | if (subseg_e) | |
9788 | return subseg_e->total_freq; | |
9789 | return 1.0; | |
9790 | } | |
9791 | ||
9792 | ||
9793 | static float | |
9794 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9795 | { | |
9796 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9797 | if (subseg_e) | |
9798 | return subseg_e->target_freq; | |
9799 | return 1.0; | |
9800 | } | |
9801 | ||
9802 | ||
9803 | static void | |
9804 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9805 | { | |
9806 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9807 | if (! subseg_e) | |
9808 | subseg_e = add_subseg_info (seg, subseg); | |
9809 | subseg_e->total_freq = total_f; | |
9810 | subseg_e->target_freq = target_f; | |
9811 | } | |
9812 | ||
e0001a05 NC |
9813 | \f |
9814 | /* Segment Lists and emit_state Stuff. */ | |
9815 | ||
e0001a05 | 9816 | static void |
7fa3d080 | 9817 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9818 | { |
9819 | head = head->next; | |
9820 | while (head) | |
9821 | { | |
9822 | segT literal_section = head->seg; | |
9823 | ||
9824 | /* Move the literal section to the front of the section list. */ | |
9825 | assert (literal_section); | |
69852798 AM |
9826 | if (literal_section != stdoutput->sections) |
9827 | { | |
9828 | bfd_section_list_remove (stdoutput, literal_section); | |
9829 | bfd_section_list_prepend (stdoutput, literal_section); | |
9830 | } | |
e0001a05 NC |
9831 | head = head->next; |
9832 | } | |
9833 | } | |
9834 | ||
9835 | ||
7fa3d080 BW |
9836 | static void mark_literal_frags (seg_list *); |
9837 | ||
9838 | static void | |
9839 | xtensa_move_literals (void) | |
e0001a05 NC |
9840 | { |
9841 | seg_list *segment; | |
9842 | frchainS *frchain_from, *frchain_to; | |
9843 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9844 | fragS **frag_splice; | |
9845 | emit_state state; | |
9846 | segT dest_seg; | |
9847 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9848 | sym_list *lit; |
e0001a05 | 9849 | |
a7877748 | 9850 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
9851 | |
9852 | if (use_literal_section) | |
9853 | return; | |
9854 | ||
74869ac7 | 9855 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 9856 | { |
74869ac7 BW |
9857 | /* Keep the literals for .init and .fini in separate sections. */ |
9858 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
9859 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
9860 | continue; | |
9861 | ||
e0001a05 NC |
9862 | frchain_from = seg_info (segment->seg)->frchainP; |
9863 | search_frag = frchain_from->frch_root; | |
9864 | literal_pool = NULL; | |
9865 | frchain_to = NULL; | |
9866 | frag_splice = &(frchain_from->frch_root); | |
9867 | ||
9868 | while (!search_frag->tc_frag_data.literal_frag) | |
9869 | { | |
9870 | assert (search_frag->fr_fix == 0 | |
9871 | || search_frag->fr_type == rs_align); | |
9872 | search_frag = search_frag->fr_next; | |
9873 | } | |
9874 | ||
9875 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9876 | == RELAX_LITERAL_POOL_BEGIN); | |
9877 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9878 | ||
9879 | /* Make sure that all the frags in this series are closed, and | |
9880 | that there is at least one left over of zero-size. This | |
9881 | prevents us from making a segment with an frchain without any | |
9882 | frags in it. */ | |
9883 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9884 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9885 | last_frag = frag_now; |
9886 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9887 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9888 | |
43cd72b9 | 9889 | while (search_frag != frag_now) |
e0001a05 NC |
9890 | { |
9891 | next_frag = search_frag->fr_next; | |
9892 | ||
43cd72b9 | 9893 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9894 | to the appropriate place. */ |
9895 | if (search_frag->tc_frag_data.literal_frag) | |
9896 | { | |
9897 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9898 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9899 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9900 | assert (frchain_to); | |
e0001a05 | 9901 | } |
c48aaca0 | 9902 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 9903 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9904 | |
e0001a05 NC |
9905 | *frag_splice = next_frag; |
9906 | search_frag->fr_next = insert_after->fr_next; | |
9907 | insert_after->fr_next = search_frag; | |
9908 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 9909 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
9910 | |
9911 | /* Now move any fixups associated with this frag to the | |
9912 | right section. */ | |
9913 | fix = frchain_from->fix_root; | |
9914 | fix_splice = &(frchain_from->fix_root); | |
9915 | while (fix) | |
9916 | { | |
9917 | next_fix = fix->fx_next; | |
9918 | if (fix->fx_frag == search_frag) | |
9919 | { | |
9920 | *fix_splice = next_fix; | |
9921 | fix->fx_next = frchain_to->fix_root; | |
9922 | frchain_to->fix_root = fix; | |
9923 | if (frchain_to->fix_tail == NULL) | |
9924 | frchain_to->fix_tail = fix; | |
9925 | } | |
9926 | else | |
9927 | fix_splice = &(fix->fx_next); | |
9928 | fix = next_fix; | |
9929 | } | |
9930 | search_frag = next_frag; | |
9931 | } | |
9932 | ||
9933 | if (frchain_from->fix_root != NULL) | |
9934 | { | |
9935 | frchain_from = seg_info (segment->seg)->frchainP; | |
9936 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9937 | ||
9938 | assert (frchain_from->fix_root == NULL); | |
9939 | } | |
9940 | frchain_from->fix_tail = NULL; | |
9941 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
9942 | } |
9943 | ||
82e7541d BW |
9944 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9945 | for (lit = literal_syms; lit; lit = lit->next) | |
9946 | { | |
9947 | symbolS *lit_sym = lit->sym; | |
9948 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9949 | if (dest_seg) |
9950 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9951 | } |
e0001a05 NC |
9952 | } |
9953 | ||
9954 | ||
a7877748 BW |
9955 | /* Walk over all the frags for segments in a list and mark them as |
9956 | containing literals. As clunky as this is, we can't rely on frag_var | |
9957 | and frag_variant to get called in all situations. */ | |
9958 | ||
9959 | static void | |
7fa3d080 | 9960 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9961 | { |
9962 | frchainS *frchain_from; | |
9963 | fragS *search_frag; | |
9964 | ||
9965 | while (segment) | |
9966 | { | |
9967 | frchain_from = seg_info (segment->seg)->frchainP; | |
9968 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9969 | while (search_frag) |
a7877748 BW |
9970 | { |
9971 | search_frag->tc_frag_data.is_literal = TRUE; | |
9972 | search_frag = search_frag->fr_next; | |
9973 | } | |
9974 | segment = segment->next; | |
9975 | } | |
9976 | } | |
9977 | ||
9978 | ||
e0001a05 | 9979 | static void |
7fa3d080 | 9980 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9981 | { |
9982 | /* Move all of the sections in the section list to come | |
9983 | after "after" in the gnu segment list. */ | |
9984 | ||
9985 | head = head->next; | |
9986 | while (head) | |
9987 | { | |
9988 | segT literal_section = head->seg; | |
9989 | ||
9990 | /* Move the literal section after "after". */ | |
9991 | assert (literal_section); | |
9992 | if (literal_section != after) | |
9993 | { | |
69852798 AM |
9994 | bfd_section_list_remove (stdoutput, literal_section); |
9995 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9996 | } |
9997 | ||
9998 | head = head->next; | |
9999 | } | |
10000 | } | |
10001 | ||
10002 | ||
10003 | /* Push all the literal segments to the end of the gnu list. */ | |
10004 | ||
7fa3d080 BW |
10005 | static void |
10006 | xtensa_reorder_segments (void) | |
e0001a05 NC |
10007 | { |
10008 | segT sec; | |
b08b5071 | 10009 | segT last_sec = 0; |
e0001a05 NC |
10010 | int old_count = 0; |
10011 | int new_count = 0; | |
10012 | ||
10013 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10014 | { |
10015 | last_sec = sec; | |
10016 | old_count++; | |
10017 | } | |
e0001a05 NC |
10018 | |
10019 | /* Now that we have the last section, push all the literal | |
10020 | sections to the end. */ | |
e0001a05 | 10021 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10022 | |
10023 | /* Now perform the final error check. */ | |
10024 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10025 | new_count++; | |
10026 | assert (new_count == old_count); | |
10027 | } | |
10028 | ||
10029 | ||
e0001a05 NC |
10030 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10031 | correct location. Return a emit_state which can be passed to | |
10032 | xtensa_restore_emit_state to return to current fragment. */ | |
10033 | ||
7fa3d080 BW |
10034 | static void |
10035 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10036 | { |
10037 | if (directive_state[directive_absolute_literals]) | |
10038 | { | |
74869ac7 BW |
10039 | segT lit4_seg = cache_literal_section (TRUE); |
10040 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10041 | } |
10042 | else | |
10043 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10044 | ||
10045 | /* Do a 4-byte align here. */ | |
10046 | frag_align (2, 0, 0); | |
10047 | record_alignment (now_seg, 2); | |
10048 | } | |
10049 | ||
10050 | ||
7fa3d080 BW |
10051 | static void |
10052 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10053 | { |
e0001a05 NC |
10054 | static bfd_boolean recursive = FALSE; |
10055 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10056 | segT lit_seg; |
c138bc38 | 10057 | bfd_boolean is_init = |
e0001a05 | 10058 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10059 | bfd_boolean is_fini = |
e0001a05 | 10060 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10061 | |
43cd72b9 BW |
10062 | if (pool_location == NULL |
10063 | && !use_literal_section | |
e0001a05 NC |
10064 | && !recursive |
10065 | && !is_init && ! is_fini) | |
10066 | { | |
43cd72b9 | 10067 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10068 | |
10069 | /* When we mark a literal pool location, we want to put a frag in | |
10070 | the literal pool that points to it. But to do that, we want to | |
10071 | switch_to_literal_fragment. But literal sections don't have | |
10072 | literal pools, so their location is always null, so we would | |
10073 | recurse forever. This is kind of hacky, but it works. */ | |
10074 | ||
e0001a05 | 10075 | recursive = TRUE; |
61846f28 | 10076 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10077 | recursive = FALSE; |
10078 | } | |
10079 | ||
74869ac7 BW |
10080 | lit_seg = cache_literal_section (FALSE); |
10081 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10082 | |
43cd72b9 BW |
10083 | if (!use_literal_section |
10084 | && !is_init && !is_fini | |
10085 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10086 | { |
10087 | /* Close whatever frag is there. */ | |
10088 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10089 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10090 | frag_now->tc_frag_data.literal_frag = pool_location; |
10091 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10092 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10093 | } |
e0001a05 NC |
10094 | } |
10095 | ||
10096 | ||
10097 | /* Call this function before emitting data into the literal section. | |
10098 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10099 | This is similar to a .section new_now_seg subseg. */ | |
10100 | ||
7fa3d080 BW |
10101 | static void |
10102 | xtensa_switch_section_emit_state (emit_state *state, | |
10103 | segT new_now_seg, | |
10104 | subsegT new_now_subseg) | |
e0001a05 NC |
10105 | { |
10106 | state->name = now_seg->name; | |
10107 | state->now_seg = now_seg; | |
10108 | state->now_subseg = now_subseg; | |
10109 | state->generating_literals = generating_literals; | |
10110 | generating_literals++; | |
2b0210eb | 10111 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10112 | } |
10113 | ||
10114 | ||
10115 | /* Use to restore the emitting into the normal place. */ | |
10116 | ||
7fa3d080 BW |
10117 | static void |
10118 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10119 | { |
10120 | generating_literals = state->generating_literals; | |
2b0210eb | 10121 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10122 | } |
10123 | ||
10124 | ||
74869ac7 | 10125 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10126 | |
74869ac7 BW |
10127 | static bfd_boolean |
10128 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10129 | { |
74869ac7 BW |
10130 | const char *gname = inf; |
10131 | const char *group_name = elf_group_name (sec); | |
10132 | ||
10133 | return (group_name == gname | |
10134 | || (group_name != NULL | |
10135 | && gname != NULL | |
10136 | && strcmp (group_name, gname) == 0)); | |
10137 | } | |
e0001a05 | 10138 | |
e0001a05 | 10139 | |
74869ac7 BW |
10140 | /* Get the literal section to be used for the current text section. |
10141 | The result may be cached in the default_lit_sections structure. */ | |
10142 | ||
10143 | static segT | |
10144 | cache_literal_section (bfd_boolean use_abs_literals) | |
10145 | { | |
10146 | const char *text_name, *group_name = 0; | |
10147 | char *base_name, *name, *suffix; | |
10148 | segT *pcached; | |
10149 | segT seg, current_section; | |
10150 | int current_subsec; | |
10151 | bfd_boolean linkonce = FALSE; | |
10152 | ||
10153 | /* Save the current section/subsection. */ | |
10154 | current_section = now_seg; | |
10155 | current_subsec = now_subseg; | |
10156 | ||
10157 | /* Clear the cached values if they are no longer valid. */ | |
10158 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10159 | { |
74869ac7 BW |
10160 | default_lit_sections.current_text_seg = now_seg; |
10161 | default_lit_sections.lit_seg = NULL; | |
10162 | default_lit_sections.lit4_seg = NULL; | |
10163 | } | |
10164 | ||
10165 | /* Check if the literal section is already cached. */ | |
10166 | if (use_abs_literals) | |
10167 | pcached = &default_lit_sections.lit4_seg; | |
10168 | else | |
10169 | pcached = &default_lit_sections.lit_seg; | |
10170 | ||
10171 | if (*pcached) | |
10172 | return *pcached; | |
10173 | ||
10174 | text_name = default_lit_sections.lit_prefix; | |
10175 | if (! text_name || ! *text_name) | |
10176 | { | |
10177 | text_name = segment_name (current_section); | |
10178 | group_name = elf_group_name (current_section); | |
10179 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10180 | } | |
10181 | ||
10182 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10183 | if (group_name) | |
10184 | { | |
10185 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10186 | sprintf (name, "%s.%s", base_name, group_name); | |
10187 | } | |
10188 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10189 | { | |
10190 | suffix = strchr (text_name + linkonce_len, '.'); | |
10191 | ||
10192 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10193 | + (suffix ? strlen (suffix) : 0)); | |
10194 | strcpy (name, ".gnu.linkonce"); | |
10195 | strcat (name, base_name); | |
10196 | if (suffix) | |
10197 | strcat (name, suffix); | |
10198 | linkonce = TRUE; | |
10199 | } | |
10200 | else | |
10201 | { | |
10202 | /* If the section name ends with ".text", then replace that suffix | |
10203 | instead of appending an additional suffix. */ | |
10204 | size_t len = strlen (text_name); | |
10205 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10206 | len -= 5; | |
10207 | ||
10208 | name = xmalloc (len + strlen (base_name) + 1); | |
10209 | strcpy (name, text_name); | |
10210 | strcpy (name + len, base_name); | |
b08b5071 | 10211 | } |
e0001a05 | 10212 | |
74869ac7 BW |
10213 | /* Canonicalize section names to allow renaming literal sections. |
10214 | The group name, if any, came from the current text section and | |
10215 | has already been canonicalized. */ | |
10216 | name = tc_canonicalize_symbol_name (name); | |
10217 | ||
10218 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10219 | (void *) group_name); | |
10220 | if (! seg) | |
e0001a05 | 10221 | { |
74869ac7 BW |
10222 | flagword flags; |
10223 | ||
10224 | seg = subseg_force_new (name, 0); | |
10225 | ||
10226 | if (! use_abs_literals) | |
b08b5071 | 10227 | { |
74869ac7 | 10228 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10229 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10230 | n->seg = seg; | |
74869ac7 BW |
10231 | n->next = literal_head->next; |
10232 | literal_head->next = n; | |
b08b5071 | 10233 | } |
74869ac7 BW |
10234 | |
10235 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10236 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10237 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10238 | ||
10239 | elf_group_name (seg) = group_name; | |
10240 | ||
10241 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10242 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10243 | } |
10244 | ||
74869ac7 | 10245 | *pcached = seg; |
b08b5071 | 10246 | subseg_set (current_section, current_subsec); |
74869ac7 | 10247 | return seg; |
e0001a05 NC |
10248 | } |
10249 | ||
43cd72b9 BW |
10250 | \f |
10251 | /* Property Tables Stuff. */ | |
10252 | ||
7fa3d080 BW |
10253 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10254 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10255 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10256 | ||
10257 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10258 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10259 | ||
b08b5071 | 10260 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10261 | static void xtensa_create_property_segments |
10262 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10263 | static void xtensa_create_xproperty_segments | |
10264 | (frag_flags_fn, const char *, xt_section_type); | |
7fa3d080 BW |
10265 | static bfd_boolean section_has_property (segT, frag_predicate); |
10266 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10267 | static void add_xt_block_frags | |
542f8b94 | 10268 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
10269 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
10270 | static void xtensa_frag_flags_init (frag_flags *); | |
10271 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10272 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
542f8b94 | 10273 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
10274 | |
10275 | /* Set up property tables after relaxation. */ | |
10276 | ||
10277 | void | |
10278 | xtensa_post_relax_hook (void) | |
10279 | { | |
10280 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10281 | |
10282 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10283 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10284 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10285 | |
b29757dc BW |
10286 | xtensa_create_property_segments (get_frag_is_literal, |
10287 | NULL, | |
10288 | XTENSA_LIT_SEC_NAME, | |
10289 | xt_literal_sec); | |
7fa3d080 BW |
10290 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10291 | XTENSA_PROP_SEC_NAME, | |
10292 | xt_prop_sec); | |
10293 | ||
10294 | if (warn_unaligned_branch_targets) | |
10295 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10296 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10297 | } | |
10298 | ||
10299 | ||
43cd72b9 BW |
10300 | /* This function is only meaningful after xtensa_move_literals. */ |
10301 | ||
10302 | static bfd_boolean | |
7fa3d080 | 10303 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10304 | { |
10305 | assert (fragP != NULL); | |
10306 | return fragP->tc_frag_data.is_literal; | |
10307 | } | |
10308 | ||
10309 | ||
43cd72b9 | 10310 | static void |
7fa3d080 BW |
10311 | xtensa_create_property_segments (frag_predicate property_function, |
10312 | frag_predicate end_property_function, | |
10313 | const char *section_name_base, | |
10314 | xt_section_type sec_type) | |
43cd72b9 BW |
10315 | { |
10316 | segT *seclist; | |
10317 | ||
10318 | /* Walk over all of the current segments. | |
10319 | Walk over each fragment | |
10320 | For each non-empty fragment, | |
10321 | Build a property record (append where possible). */ | |
10322 | ||
10323 | for (seclist = &stdoutput->sections; | |
10324 | seclist && *seclist; | |
10325 | seclist = &(*seclist)->next) | |
10326 | { | |
10327 | segT sec = *seclist; | |
10328 | flagword flags; | |
10329 | ||
10330 | flags = bfd_get_section_flags (stdoutput, sec); | |
10331 | if (flags & SEC_DEBUGGING) | |
10332 | continue; | |
10333 | if (!(flags & SEC_ALLOC)) | |
10334 | continue; | |
10335 | ||
10336 | if (section_has_property (sec, property_function)) | |
10337 | { | |
542f8b94 BW |
10338 | segment_info_type *xt_seg_info; |
10339 | xtensa_block_info **xt_blocks; | |
10340 | segT prop_sec = xtensa_get_property_section (sec, section_name_base); | |
10341 | ||
10342 | prop_sec->output_section = prop_sec; | |
10343 | subseg_set (prop_sec, 0); | |
10344 | xt_seg_info = seg_info (prop_sec); | |
10345 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10346 | ||
43cd72b9 | 10347 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10348 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
10349 | end_property_function); |
10350 | } | |
10351 | } | |
10352 | ||
10353 | /* Now we fill them out.... */ | |
10354 | ||
10355 | for (seclist = &stdoutput->sections; | |
10356 | seclist && *seclist; | |
10357 | seclist = &(*seclist)->next) | |
10358 | { | |
10359 | segment_info_type *seginfo; | |
10360 | xtensa_block_info *block; | |
10361 | segT sec = *seclist; | |
10362 | ||
10363 | seginfo = seg_info (sec); | |
10364 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10365 | ||
10366 | if (block) | |
10367 | { | |
10368 | xtensa_block_info *cur_block; | |
43cd72b9 | 10369 | int num_recs = 0; |
d77b99c9 | 10370 | bfd_size_type rec_size; |
43cd72b9 BW |
10371 | |
10372 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10373 | num_recs++; | |
10374 | ||
10375 | rec_size = num_recs * 8; | |
10376 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10377 | ||
43cd72b9 BW |
10378 | if (num_recs) |
10379 | { | |
43cd72b9 | 10380 | char *frag_data; |
542f8b94 | 10381 | int i; |
43cd72b9 | 10382 | |
542f8b94 BW |
10383 | subseg_set (sec, 0); |
10384 | frag_data = frag_more (rec_size); | |
43cd72b9 | 10385 | cur_block = block; |
43cd72b9 BW |
10386 | for (i = 0; i < num_recs; i++) |
10387 | { | |
542f8b94 | 10388 | fixS *fix; |
e0001a05 | 10389 | |
43cd72b9 | 10390 | /* Write the fixup. */ |
542f8b94 BW |
10391 | assert (cur_block); |
10392 | fix = fix_new (frag_now, i * 8, 4, | |
10393 | section_symbol (cur_block->sec), | |
10394 | cur_block->offset, | |
10395 | FALSE, BFD_RELOC_32); | |
10396 | fix->fx_file = "<internal>"; | |
43cd72b9 | 10397 | fix->fx_line = 0; |
e0001a05 | 10398 | |
43cd72b9 | 10399 | /* Write the length. */ |
542f8b94 | 10400 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
10401 | cur_block->size, 4); |
10402 | cur_block = cur_block->next; | |
10403 | } | |
542f8b94 BW |
10404 | frag_wane (frag_now); |
10405 | frag_new (0); | |
10406 | frag_wane (frag_now); | |
43cd72b9 BW |
10407 | } |
10408 | } | |
10409 | } | |
e0001a05 NC |
10410 | } |
10411 | ||
10412 | ||
7fa3d080 BW |
10413 | static void |
10414 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10415 | const char *section_name_base, | |
10416 | xt_section_type sec_type) | |
e0001a05 NC |
10417 | { |
10418 | segT *seclist; | |
10419 | ||
10420 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10421 | Walk over each fragment. |
10422 | For each fragment that has instructions, | |
10423 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10424 | |
10425 | for (seclist = &stdoutput->sections; | |
10426 | seclist && *seclist; | |
10427 | seclist = &(*seclist)->next) | |
10428 | { | |
10429 | segT sec = *seclist; | |
43cd72b9 BW |
10430 | flagword flags; |
10431 | ||
10432 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10433 | if ((flags & SEC_DEBUGGING) |
10434 | || !(flags & SEC_ALLOC) | |
10435 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10436 | continue; |
10437 | ||
10438 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10439 | { |
542f8b94 BW |
10440 | segment_info_type *xt_seg_info; |
10441 | xtensa_block_info **xt_blocks; | |
10442 | segT prop_sec = xtensa_get_property_section (sec, section_name_base); | |
10443 | ||
10444 | prop_sec->output_section = prop_sec; | |
10445 | subseg_set (prop_sec, 0); | |
10446 | xt_seg_info = seg_info (prop_sec); | |
10447 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10448 | ||
e0001a05 | 10449 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10450 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
10451 | } |
10452 | } | |
10453 | ||
10454 | /* Now we fill them out.... */ | |
10455 | ||
10456 | for (seclist = &stdoutput->sections; | |
10457 | seclist && *seclist; | |
10458 | seclist = &(*seclist)->next) | |
10459 | { | |
10460 | segment_info_type *seginfo; | |
10461 | xtensa_block_info *block; | |
10462 | segT sec = *seclist; | |
43cd72b9 | 10463 | |
e0001a05 NC |
10464 | seginfo = seg_info (sec); |
10465 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10466 | ||
10467 | if (block) | |
10468 | { | |
10469 | xtensa_block_info *cur_block; | |
43cd72b9 | 10470 | int num_recs = 0; |
d77b99c9 | 10471 | bfd_size_type rec_size; |
e0001a05 NC |
10472 | |
10473 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10474 | num_recs++; | |
10475 | ||
43cd72b9 | 10476 | rec_size = num_recs * (8 + 4); |
e0001a05 | 10477 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
10478 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10479 | ||
e0001a05 NC |
10480 | if (num_recs) |
10481 | { | |
e0001a05 | 10482 | char *frag_data; |
542f8b94 | 10483 | int i; |
e0001a05 | 10484 | |
542f8b94 BW |
10485 | subseg_set (sec, 0); |
10486 | frag_data = frag_more (rec_size); | |
e0001a05 | 10487 | cur_block = block; |
e0001a05 NC |
10488 | for (i = 0; i < num_recs; i++) |
10489 | { | |
542f8b94 | 10490 | fixS *fix; |
e0001a05 NC |
10491 | |
10492 | /* Write the fixup. */ | |
542f8b94 BW |
10493 | assert (cur_block); |
10494 | fix = fix_new (frag_now, i * 12, 4, | |
10495 | section_symbol (cur_block->sec), | |
10496 | cur_block->offset, | |
10497 | FALSE, BFD_RELOC_32); | |
10498 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
10499 | fix->fx_line = 0; |
10500 | ||
10501 | /* Write the length. */ | |
542f8b94 | 10502 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 10503 | cur_block->size, 4); |
542f8b94 | 10504 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 BW |
10505 | frag_flags_to_number (&cur_block->flags), |
10506 | 4); | |
e0001a05 NC |
10507 | cur_block = cur_block->next; |
10508 | } | |
542f8b94 BW |
10509 | frag_wane (frag_now); |
10510 | frag_new (0); | |
10511 | frag_wane (frag_now); | |
e0001a05 NC |
10512 | } |
10513 | } | |
10514 | } | |
10515 | } | |
10516 | ||
10517 | ||
7fa3d080 BW |
10518 | static bfd_boolean |
10519 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10520 | { |
10521 | segment_info_type *seginfo = seg_info (sec); | |
10522 | fragS *fragP; | |
10523 | ||
10524 | if (seginfo && seginfo->frchainP) | |
10525 | { | |
10526 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10527 | { | |
10528 | if (property_function (fragP) | |
10529 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10530 | return TRUE; | |
10531 | } | |
10532 | } | |
10533 | return FALSE; | |
10534 | } | |
10535 | ||
10536 | ||
7fa3d080 BW |
10537 | static bfd_boolean |
10538 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10539 | { |
10540 | segment_info_type *seginfo = seg_info (sec); | |
10541 | fragS *fragP; | |
10542 | ||
10543 | if (seginfo && seginfo->frchainP) | |
10544 | { | |
10545 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10546 | { | |
10547 | frag_flags prop_flags; | |
10548 | property_function (fragP, &prop_flags); | |
10549 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10550 | return TRUE; | |
10551 | } | |
10552 | } | |
10553 | return FALSE; | |
10554 | } | |
10555 | ||
10556 | ||
e0001a05 NC |
10557 | /* Two types of block sections exist right now: literal and insns. */ |
10558 | ||
7fa3d080 BW |
10559 | static void |
10560 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
10561 | xtensa_block_info **xt_block, |
10562 | frag_predicate property_function, | |
10563 | frag_predicate end_property_function) | |
e0001a05 | 10564 | { |
e0001a05 NC |
10565 | bfd_vma seg_offset; |
10566 | fragS *fragP; | |
10567 | ||
e0001a05 NC |
10568 | /* Build it if needed. */ |
10569 | while (*xt_block != NULL) | |
10570 | xt_block = &(*xt_block)->next; | |
10571 | /* We are either at NULL at the beginning or at the end. */ | |
10572 | ||
10573 | /* Walk through the frags. */ | |
10574 | seg_offset = 0; | |
10575 | ||
542f8b94 | 10576 | if (seg_info (sec)->frchainP) |
e0001a05 | 10577 | { |
542f8b94 | 10578 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
10579 | fragP; |
10580 | fragP = fragP->fr_next) | |
10581 | { | |
10582 | if (property_function (fragP) | |
10583 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10584 | { | |
10585 | if (*xt_block != NULL) | |
10586 | { | |
10587 | if ((*xt_block)->offset + (*xt_block)->size | |
10588 | == fragP->fr_address) | |
10589 | (*xt_block)->size += fragP->fr_fix; | |
10590 | else | |
10591 | xt_block = &((*xt_block)->next); | |
10592 | } | |
10593 | if (*xt_block == NULL) | |
10594 | { | |
43cd72b9 BW |
10595 | xtensa_block_info *new_block = (xtensa_block_info *) |
10596 | xmalloc (sizeof (xtensa_block_info)); | |
10597 | new_block->sec = sec; | |
10598 | new_block->offset = fragP->fr_address; | |
10599 | new_block->size = fragP->fr_fix; | |
10600 | new_block->next = NULL; | |
10601 | xtensa_frag_flags_init (&new_block->flags); | |
10602 | *xt_block = new_block; | |
10603 | } | |
10604 | if (end_property_function | |
10605 | && end_property_function (fragP)) | |
10606 | { | |
10607 | xt_block = &((*xt_block)->next); | |
10608 | } | |
10609 | } | |
10610 | } | |
10611 | } | |
10612 | } | |
10613 | ||
10614 | ||
10615 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10616 | ||
7fa3d080 BW |
10617 | static bfd_boolean |
10618 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10619 | { |
10620 | if (prop_flags->is_literal | |
10621 | || prop_flags->is_insn | |
10622 | || prop_flags->is_data | |
10623 | || prop_flags->is_unreachable) | |
10624 | return FALSE; | |
10625 | return TRUE; | |
10626 | } | |
10627 | ||
10628 | ||
7fa3d080 BW |
10629 | static void |
10630 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10631 | { |
10632 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10633 | } | |
10634 | ||
10635 | ||
7fa3d080 BW |
10636 | static void |
10637 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10638 | { |
10639 | xtensa_frag_flags_init (prop_flags); | |
10640 | if (fragP->tc_frag_data.is_literal) | |
10641 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10642 | if (fragP->tc_frag_data.is_specific_opcode |
10643 | || fragP->tc_frag_data.is_no_transform) | |
10644 | prop_flags->is_no_transform = TRUE; | |
43cd72b9 | 10645 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10646 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10647 | else if (fragP->tc_frag_data.is_insn) |
10648 | { | |
10649 | prop_flags->is_insn = TRUE; | |
10650 | if (fragP->tc_frag_data.is_loop_target) | |
10651 | prop_flags->insn.is_loop_target = TRUE; | |
10652 | if (fragP->tc_frag_data.is_branch_target) | |
10653 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10654 | if (fragP->tc_frag_data.is_no_density) |
10655 | prop_flags->insn.is_no_density = TRUE; | |
10656 | if (fragP->tc_frag_data.use_absolute_literals) | |
10657 | prop_flags->insn.is_abslit = TRUE; | |
10658 | } | |
10659 | if (fragP->tc_frag_data.is_align) | |
10660 | { | |
10661 | prop_flags->is_align = TRUE; | |
10662 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10663 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10664 | prop_flags->is_data = TRUE; | |
10665 | } | |
10666 | } | |
10667 | ||
10668 | ||
7fa3d080 BW |
10669 | static bfd_vma |
10670 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10671 | { |
10672 | bfd_vma num = 0; | |
10673 | if (prop_flags->is_literal) | |
10674 | num |= XTENSA_PROP_LITERAL; | |
10675 | if (prop_flags->is_insn) | |
10676 | num |= XTENSA_PROP_INSN; | |
10677 | if (prop_flags->is_data) | |
10678 | num |= XTENSA_PROP_DATA; | |
10679 | if (prop_flags->is_unreachable) | |
10680 | num |= XTENSA_PROP_UNREACHABLE; | |
10681 | if (prop_flags->insn.is_loop_target) | |
10682 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10683 | if (prop_flags->insn.is_branch_target) | |
10684 | { | |
10685 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10686 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10687 | } | |
10688 | ||
10689 | if (prop_flags->insn.is_no_density) | |
10690 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10691 | if (prop_flags->is_no_transform) |
10692 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10693 | if (prop_flags->insn.is_no_reorder) |
10694 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10695 | if (prop_flags->insn.is_abslit) | |
10696 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10697 | ||
10698 | if (prop_flags->is_align) | |
10699 | { | |
10700 | num |= XTENSA_PROP_ALIGN; | |
10701 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10702 | } | |
10703 | ||
10704 | return num; | |
10705 | } | |
10706 | ||
10707 | ||
10708 | static bfd_boolean | |
7fa3d080 BW |
10709 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10710 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10711 | { |
10712 | /* Cannot combine with an end marker. */ | |
10713 | ||
10714 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10715 | return FALSE; | |
10716 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10717 | return FALSE; | |
10718 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10719 | return FALSE; | |
10720 | ||
10721 | if (prop_flags_1->is_insn) | |
10722 | { | |
10723 | /* Properties of the beginning of the frag. */ | |
10724 | if (prop_flags_2->insn.is_loop_target) | |
10725 | return FALSE; | |
10726 | if (prop_flags_2->insn.is_branch_target) | |
10727 | return FALSE; | |
10728 | if (prop_flags_1->insn.is_no_density != | |
10729 | prop_flags_2->insn.is_no_density) | |
10730 | return FALSE; | |
99ded152 BW |
10731 | if (prop_flags_1->is_no_transform != |
10732 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10733 | return FALSE; |
10734 | if (prop_flags_1->insn.is_no_reorder != | |
10735 | prop_flags_2->insn.is_no_reorder) | |
10736 | return FALSE; | |
10737 | if (prop_flags_1->insn.is_abslit != | |
10738 | prop_flags_2->insn.is_abslit) | |
10739 | return FALSE; | |
10740 | } | |
10741 | ||
10742 | if (prop_flags_1->is_align) | |
10743 | return FALSE; | |
10744 | ||
10745 | return TRUE; | |
10746 | } | |
10747 | ||
10748 | ||
7fa3d080 BW |
10749 | static bfd_vma |
10750 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10751 | { |
10752 | bfd_vma end_addr; | |
d77b99c9 | 10753 | unsigned align_bits; |
43cd72b9 BW |
10754 | |
10755 | if (!xt_block->flags.is_align) | |
10756 | return xt_block->size; | |
10757 | ||
10758 | end_addr = xt_block->offset + xt_block->size; | |
10759 | align_bits = xt_block->flags.alignment; | |
10760 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10761 | return end_addr - xt_block->offset; | |
10762 | } | |
10763 | ||
10764 | ||
10765 | static bfd_boolean | |
7fa3d080 BW |
10766 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10767 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10768 | { |
10769 | if (xt_block->sec != xt_block_2->sec) | |
10770 | return FALSE; | |
10771 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10772 | != xt_block_2->offset) | |
10773 | return FALSE; | |
10774 | ||
10775 | if (xt_block_2->size == 0 | |
10776 | && (!xt_block_2->flags.is_unreachable | |
10777 | || xt_block->flags.is_unreachable)) | |
10778 | { | |
10779 | if (xt_block_2->flags.is_align | |
10780 | && xt_block->flags.is_align) | |
10781 | { | |
10782 | /* Nothing needed. */ | |
10783 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10784 | return TRUE; | |
10785 | } | |
10786 | else | |
10787 | { | |
10788 | if (xt_block_2->flags.is_align) | |
10789 | { | |
10790 | /* Push alignment to previous entry. */ | |
10791 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10792 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10793 | } | |
10794 | return TRUE; | |
10795 | } | |
10796 | } | |
10797 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10798 | &xt_block_2->flags)) | |
10799 | return FALSE; | |
10800 | ||
10801 | xt_block->size += xt_block_2->size; | |
10802 | ||
10803 | if (xt_block_2->flags.is_align) | |
10804 | { | |
10805 | xt_block->flags.is_align = TRUE; | |
10806 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10807 | } | |
10808 | ||
10809 | return TRUE; | |
10810 | } | |
10811 | ||
10812 | ||
7fa3d080 BW |
10813 | static void |
10814 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
10815 | xtensa_block_info **xt_block, |
10816 | frag_flags_fn property_function) | |
43cd72b9 | 10817 | { |
43cd72b9 BW |
10818 | bfd_vma seg_offset; |
10819 | fragS *fragP; | |
10820 | ||
43cd72b9 BW |
10821 | /* Build it if needed. */ |
10822 | while (*xt_block != NULL) | |
10823 | { | |
10824 | xt_block = &(*xt_block)->next; | |
10825 | } | |
10826 | /* We are either at NULL at the beginning or at the end. */ | |
10827 | ||
10828 | /* Walk through the frags. */ | |
10829 | seg_offset = 0; | |
10830 | ||
542f8b94 | 10831 | if (seg_info (sec)->frchainP) |
43cd72b9 | 10832 | { |
542f8b94 | 10833 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
10834 | fragP = fragP->fr_next) |
10835 | { | |
10836 | xtensa_block_info tmp_block; | |
10837 | tmp_block.sec = sec; | |
10838 | tmp_block.offset = fragP->fr_address; | |
10839 | tmp_block.size = fragP->fr_fix; | |
10840 | tmp_block.next = NULL; | |
10841 | property_function (fragP, &tmp_block.flags); | |
10842 | ||
10843 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10844 | /* && fragP->fr_fix != 0) */ | |
10845 | { | |
10846 | if ((*xt_block) == NULL | |
10847 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10848 | { | |
10849 | xtensa_block_info *new_block; | |
10850 | if ((*xt_block) != NULL) | |
10851 | xt_block = &(*xt_block)->next; | |
10852 | new_block = (xtensa_block_info *) | |
10853 | xmalloc (sizeof (xtensa_block_info)); | |
10854 | *new_block = tmp_block; | |
10855 | *xt_block = new_block; | |
10856 | } | |
10857 | } | |
10858 | } | |
10859 | } | |
10860 | } | |
10861 | ||
10862 | \f | |
10863 | /* op_placement_info_table */ | |
10864 | ||
10865 | /* op_placement_info makes it easier to determine which | |
10866 | ops can go in which slots. */ | |
10867 | ||
10868 | static void | |
7fa3d080 | 10869 | init_op_placement_info_table (void) |
43cd72b9 BW |
10870 | { |
10871 | xtensa_isa isa = xtensa_default_isa; | |
10872 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10873 | xtensa_opcode opcode; | |
10874 | xtensa_format fmt; | |
10875 | int slot; | |
10876 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10877 | ||
10878 | op_placement_table = (op_placement_info_table) | |
10879 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10880 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10881 | ||
10882 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10883 | { | |
10884 | op_placement_info *opi = &op_placement_table[opcode]; | |
10885 | /* FIXME: Make tinsn allocation dynamic. */ | |
10886 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10887 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10888 | opi->narrowest = XTENSA_UNDEFINED; |
10889 | opi->narrowest_size = 0x7F; | |
b2d179be | 10890 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10891 | opi->formats = 0; |
10892 | opi->num_formats = 0; | |
10893 | opi->issuef = 0; | |
10894 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10895 | { | |
10896 | opi->slots[fmt] = 0; | |
10897 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10898 | { | |
10899 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10900 | { | |
10901 | int fmt_length = xtensa_format_length (isa, fmt); | |
10902 | opi->issuef++; | |
10903 | set_bit (fmt, opi->formats); | |
10904 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10905 | if (fmt_length < opi->narrowest_size |
10906 | || (fmt_length == opi->narrowest_size | |
10907 | && (xtensa_format_num_slots (isa, fmt) | |
10908 | < xtensa_format_num_slots (isa, | |
10909 | opi->narrowest)))) | |
43cd72b9 BW |
10910 | { |
10911 | opi->narrowest = fmt; | |
10912 | opi->narrowest_size = fmt_length; | |
b2d179be | 10913 | opi->narrowest_slot = slot; |
43cd72b9 | 10914 | } |
e0001a05 NC |
10915 | } |
10916 | } | |
43cd72b9 BW |
10917 | if (opi->formats) |
10918 | opi->num_formats++; | |
e0001a05 NC |
10919 | } |
10920 | } | |
43cd72b9 BW |
10921 | xtensa_insnbuf_free (isa, ibuf); |
10922 | } | |
10923 | ||
10924 | ||
10925 | bfd_boolean | |
7fa3d080 | 10926 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10927 | { |
10928 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10929 | } | |
10930 | ||
10931 | ||
10932 | /* If the opcode is available in a single slot format, return its size. */ | |
10933 | ||
7fa3d080 BW |
10934 | static int |
10935 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10936 | { |
b2d179be | 10937 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
10938 | } |
10939 | ||
10940 | ||
7fa3d080 BW |
10941 | static xtensa_format |
10942 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 10943 | { |
b2d179be BW |
10944 | return op_placement_table[opcode].narrowest; |
10945 | } | |
10946 | ||
10947 | ||
10948 | static int | |
10949 | xg_get_single_slot (xtensa_opcode opcode) | |
10950 | { | |
10951 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
10952 | } |
10953 | ||
10954 | \f | |
10955 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
10956 | ||
10957 | void | |
7fa3d080 | 10958 | istack_init (IStack *stack) |
e0001a05 NC |
10959 | { |
10960 | memset (stack, 0, sizeof (IStack)); | |
10961 | stack->ninsn = 0; | |
10962 | } | |
10963 | ||
10964 | ||
10965 | bfd_boolean | |
7fa3d080 | 10966 | istack_empty (IStack *stack) |
e0001a05 NC |
10967 | { |
10968 | return (stack->ninsn == 0); | |
10969 | } | |
10970 | ||
10971 | ||
10972 | bfd_boolean | |
7fa3d080 | 10973 | istack_full (IStack *stack) |
e0001a05 NC |
10974 | { |
10975 | return (stack->ninsn == MAX_ISTACK); | |
10976 | } | |
10977 | ||
10978 | ||
10979 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 10980 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
10981 | |
10982 | TInsn * | |
7fa3d080 | 10983 | istack_top (IStack *stack) |
e0001a05 NC |
10984 | { |
10985 | int rec = stack->ninsn - 1; | |
10986 | assert (!istack_empty (stack)); | |
10987 | return &stack->insn[rec]; | |
10988 | } | |
10989 | ||
10990 | ||
10991 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 10992 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10993 | |
10994 | void | |
7fa3d080 | 10995 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
10996 | { |
10997 | int rec = stack->ninsn; | |
10998 | assert (!istack_full (stack)); | |
43cd72b9 | 10999 | stack->insn[rec] = *insn; |
e0001a05 NC |
11000 | stack->ninsn++; |
11001 | } | |
11002 | ||
11003 | ||
11004 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11005 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11006 | |
11007 | TInsn * | |
7fa3d080 | 11008 | istack_push_space (IStack *stack) |
e0001a05 NC |
11009 | { |
11010 | int rec = stack->ninsn; | |
11011 | TInsn *insn; | |
11012 | assert (!istack_full (stack)); | |
11013 | insn = &stack->insn[rec]; | |
60242db2 | 11014 | tinsn_init (insn); |
e0001a05 NC |
11015 | stack->ninsn++; |
11016 | return insn; | |
11017 | } | |
11018 | ||
11019 | ||
11020 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11021 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11022 | |
11023 | void | |
7fa3d080 | 11024 | istack_pop (IStack *stack) |
e0001a05 NC |
11025 | { |
11026 | int rec = stack->ninsn - 1; | |
11027 | assert (!istack_empty (stack)); | |
11028 | stack->ninsn--; | |
60242db2 | 11029 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11030 | } |
11031 | ||
11032 | \f | |
11033 | /* TInsn functions. */ | |
11034 | ||
11035 | void | |
7fa3d080 | 11036 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11037 | { |
11038 | memset (dst, 0, sizeof (TInsn)); | |
11039 | } | |
11040 | ||
11041 | ||
43cd72b9 | 11042 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11043 | |
11044 | static bfd_boolean | |
7fa3d080 | 11045 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11046 | { |
11047 | int i; | |
11048 | int n = insn->ntok; | |
11049 | ||
11050 | assert (insn->insn_type == ITYPE_INSN); | |
11051 | ||
11052 | for (i = 0; i < n; ++i) | |
11053 | { | |
11054 | switch (insn->tok[i].X_op) | |
11055 | { | |
11056 | case O_register: | |
11057 | case O_constant: | |
11058 | break; | |
11059 | default: | |
11060 | return TRUE; | |
11061 | } | |
11062 | } | |
11063 | return FALSE; | |
11064 | } | |
11065 | ||
11066 | ||
11067 | bfd_boolean | |
7fa3d080 | 11068 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11069 | { |
43cd72b9 | 11070 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11071 | int i; |
11072 | int n = insn->ntok; | |
11073 | ||
11074 | assert (insn->insn_type == ITYPE_INSN); | |
11075 | ||
11076 | for (i = 0; i < n; ++i) | |
11077 | { | |
11078 | switch (insn->tok[i].X_op) | |
11079 | { | |
11080 | case O_register: | |
11081 | case O_constant: | |
11082 | break; | |
43cd72b9 BW |
11083 | case O_big: |
11084 | case O_illegal: | |
11085 | case O_absent: | |
11086 | /* Errors for these types are caught later. */ | |
11087 | break; | |
11088 | case O_hi16: | |
11089 | case O_lo16: | |
e0001a05 | 11090 | default: |
43cd72b9 BW |
11091 | /* Symbolic immediates are only allowed on the last immediate |
11092 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11093 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11094 | if (i != get_relaxable_immed (insn->opcode) |
11095 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11096 | && insn->opcode != xtensa_const16_opcode)) | |
11097 | { | |
431ad2d0 | 11098 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11099 | return TRUE; |
11100 | } | |
e0001a05 NC |
11101 | } |
11102 | } | |
11103 | return FALSE; | |
11104 | } | |
11105 | ||
11106 | ||
11107 | /* For assembly code with complex expressions (e.g. subtraction), | |
11108 | we have to build them in the literal pool so that | |
11109 | their results are calculated correctly after relaxation. | |
11110 | The relaxation only handles expressions that | |
11111 | boil down to SYMBOL + OFFSET. */ | |
11112 | ||
11113 | static bfd_boolean | |
7fa3d080 | 11114 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11115 | { |
11116 | int i; | |
11117 | int n = insn->ntok; | |
11118 | assert (insn->insn_type == ITYPE_INSN); | |
11119 | for (i = 0; i < n; ++i) | |
11120 | { | |
11121 | switch (insn->tok[i].X_op) | |
11122 | { | |
11123 | case O_register: | |
11124 | case O_constant: | |
11125 | case O_symbol: | |
43cd72b9 BW |
11126 | case O_lo16: |
11127 | case O_hi16: | |
e0001a05 NC |
11128 | break; |
11129 | default: | |
11130 | return TRUE; | |
11131 | } | |
11132 | } | |
11133 | return FALSE; | |
11134 | } | |
11135 | ||
11136 | ||
b2d179be BW |
11137 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11138 | Return TRUE if there is a symbol in the immediate field. This | |
11139 | function assumes that: | |
11140 | 1) The number of operands are correct. | |
11141 | 2) The insn_type is ITYPE_INSN. | |
11142 | 3) The opcode can be encoded in the specified format and slot. | |
11143 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11144 | |
11145 | static bfd_boolean | |
7fa3d080 BW |
11146 | tinsn_to_slotbuf (xtensa_format fmt, |
11147 | int slot, | |
11148 | TInsn *tinsn, | |
11149 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11150 | { |
11151 | xtensa_isa isa = xtensa_default_isa; | |
11152 | xtensa_opcode opcode = tinsn->opcode; | |
11153 | bfd_boolean has_fixup = FALSE; | |
11154 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11155 | int i; | |
11156 | ||
43cd72b9 BW |
11157 | assert (tinsn->insn_type == ITYPE_INSN); |
11158 | if (noperands != tinsn->ntok) | |
11159 | as_fatal (_("operand number mismatch")); | |
11160 | ||
11161 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11162 | { | |
11163 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11164 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11165 | return FALSE; | |
11166 | } | |
11167 | ||
11168 | for (i = 0; i < noperands; i++) | |
11169 | { | |
11170 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11171 | int rc; |
11172 | unsigned line; | |
43cd72b9 BW |
11173 | char *file_name; |
11174 | uint32 opnd_value; | |
11175 | ||
11176 | switch (expr->X_op) | |
11177 | { | |
11178 | case O_register: | |
11179 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11180 | break; | |
11181 | /* The register number has already been checked in | |
11182 | expression_maybe_register, so we don't need to check here. */ | |
11183 | opnd_value = expr->X_add_number; | |
11184 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11185 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11186 | opnd_value); | |
11187 | if (rc != 0) | |
11188 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11189 | break; | |
11190 | ||
11191 | case O_constant: | |
11192 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11193 | break; | |
11194 | as_where (&file_name, &line); | |
11195 | /* It is a constant and we called this function | |
11196 | then we have to try to fit it. */ | |
11197 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11198 | expr->X_add_number, file_name, line); |
11199 | break; | |
11200 | ||
e0001a05 NC |
11201 | default: |
11202 | has_fixup = TRUE; | |
11203 | break; | |
11204 | } | |
11205 | } | |
43cd72b9 | 11206 | |
e0001a05 NC |
11207 | return has_fixup; |
11208 | } | |
11209 | ||
11210 | ||
b2d179be BW |
11211 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11212 | into a multi-slot instruction, fill the other slots with NOPs. | |
11213 | Return TRUE if there is a symbol in the immediate field. See also the | |
11214 | assumptions listed for tinsn_to_slotbuf. */ | |
11215 | ||
11216 | static bfd_boolean | |
11217 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11218 | { | |
11219 | static xtensa_insnbuf slotbuf = 0; | |
11220 | static vliw_insn vinsn; | |
11221 | xtensa_isa isa = xtensa_default_isa; | |
11222 | bfd_boolean has_fixup = FALSE; | |
11223 | int i; | |
11224 | ||
11225 | if (!slotbuf) | |
11226 | { | |
11227 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11228 | xg_init_vinsn (&vinsn); | |
11229 | } | |
11230 | ||
11231 | xg_clear_vinsn (&vinsn); | |
11232 | ||
11233 | bundle_tinsn (tinsn, &vinsn); | |
11234 | ||
11235 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11236 | ||
11237 | for (i = 0; i < vinsn.num_slots; i++) | |
11238 | { | |
11239 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11240 | has_fixup |= | |
11241 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11242 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11243 | } | |
11244 | ||
11245 | return has_fixup; | |
11246 | } | |
11247 | ||
11248 | ||
43cd72b9 | 11249 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11250 | |
7fa3d080 BW |
11251 | static bfd_boolean |
11252 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11253 | { |
11254 | xtensa_isa isa = xtensa_default_isa; | |
11255 | xtensa_opcode opcode = insn->opcode; | |
11256 | ||
11257 | if (opcode == XTENSA_UNDEFINED) | |
11258 | { | |
11259 | as_bad (_("invalid opcode")); | |
11260 | return TRUE; | |
11261 | } | |
11262 | ||
43cd72b9 | 11263 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11264 | { |
11265 | as_bad (_("too few operands")); | |
11266 | return TRUE; | |
11267 | } | |
11268 | ||
43cd72b9 | 11269 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11270 | { |
11271 | as_bad (_("too many operands")); | |
11272 | return TRUE; | |
11273 | } | |
11274 | return FALSE; | |
11275 | } | |
11276 | ||
11277 | ||
11278 | /* Load an instruction from its encoded form. */ | |
11279 | ||
11280 | static void | |
7fa3d080 | 11281 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11282 | { |
43cd72b9 | 11283 | vliw_insn vinsn; |
e0001a05 | 11284 | |
43cd72b9 BW |
11285 | xg_init_vinsn (&vinsn); |
11286 | vinsn_from_chars (&vinsn, f); | |
11287 | ||
11288 | *tinsn = vinsn.slots[slot]; | |
11289 | xg_free_vinsn (&vinsn); | |
11290 | } | |
e0001a05 | 11291 | |
43cd72b9 BW |
11292 | |
11293 | static void | |
7fa3d080 BW |
11294 | tinsn_from_insnbuf (TInsn *tinsn, |
11295 | xtensa_insnbuf slotbuf, | |
11296 | xtensa_format fmt, | |
11297 | int slot) | |
43cd72b9 BW |
11298 | { |
11299 | int i; | |
11300 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11301 | |
11302 | /* Find the immed. */ | |
43cd72b9 BW |
11303 | tinsn_init (tinsn); |
11304 | tinsn->insn_type = ITYPE_INSN; | |
11305 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11306 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11307 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11308 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11309 | { |
43cd72b9 BW |
11310 | set_expr_const (&tinsn->tok[i], |
11311 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11312 | tinsn->opcode, i)); | |
e0001a05 NC |
11313 | } |
11314 | } | |
11315 | ||
11316 | ||
11317 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11318 | ||
11319 | static void | |
7fa3d080 | 11320 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11321 | { |
43cd72b9 | 11322 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11323 | int opnum; |
11324 | ||
43cd72b9 | 11325 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11326 | { |
11327 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11328 | assert (opnum >= 0); |
e7da6241 BW |
11329 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11330 | fragP->tc_frag_data.slot_symbols[slot], | |
11331 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11332 | } |
11333 | } | |
11334 | ||
11335 | ||
11336 | static int | |
7fa3d080 | 11337 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11338 | { |
11339 | int i; | |
11340 | int text_bytes = 0; | |
11341 | ||
11342 | for (i = 0; i < istack->ninsn; i++) | |
11343 | { | |
43cd72b9 BW |
11344 | TInsn *tinsn = &istack->insn[i]; |
11345 | if (tinsn->insn_type == ITYPE_INSN) | |
11346 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11347 | } |
11348 | return text_bytes; | |
11349 | } | |
11350 | ||
11351 | ||
11352 | static int | |
7fa3d080 | 11353 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11354 | { |
11355 | int i; | |
11356 | int lit_bytes = 0; | |
11357 | ||
11358 | for (i = 0; i < istack->ninsn; i++) | |
11359 | { | |
43cd72b9 BW |
11360 | TInsn *tinsn = &istack->insn[i]; |
11361 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11362 | lit_bytes += 4; |
11363 | } | |
11364 | return lit_bytes; | |
11365 | } | |
11366 | ||
43cd72b9 BW |
11367 | \f |
11368 | /* vliw_insn functions. */ | |
11369 | ||
7fa3d080 BW |
11370 | static void |
11371 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11372 | { |
11373 | int i; | |
11374 | xtensa_isa isa = xtensa_default_isa; | |
11375 | ||
11376 | xg_clear_vinsn (v); | |
11377 | ||
11378 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11379 | if (v->insnbuf == NULL) | |
11380 | as_fatal (_("out of memory")); | |
11381 | ||
11382 | for (i = 0; i < MAX_SLOTS; i++) | |
11383 | { | |
43cd72b9 BW |
11384 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11385 | if (v->slotbuf[i] == NULL) | |
11386 | as_fatal (_("out of memory")); | |
11387 | } | |
11388 | } | |
11389 | ||
11390 | ||
7fa3d080 BW |
11391 | static void |
11392 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11393 | { |
11394 | int i; | |
65738a7d BW |
11395 | |
11396 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11397 | ||
43cd72b9 BW |
11398 | v->format = XTENSA_UNDEFINED; |
11399 | v->num_slots = 0; | |
11400 | v->inside_bundle = FALSE; | |
11401 | ||
11402 | if (xt_saved_debug_type != DEBUG_NONE) | |
11403 | debug_type = xt_saved_debug_type; | |
11404 | ||
11405 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11406 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11407 | } |
11408 | ||
11409 | ||
7fa3d080 BW |
11410 | static bfd_boolean |
11411 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11412 | { |
11413 | int i; | |
c138bc38 | 11414 | |
43cd72b9 BW |
11415 | for (i = 0; i < v->num_slots; i++) |
11416 | { | |
11417 | if (v->slots[i].is_specific_opcode) | |
11418 | return TRUE; | |
11419 | } | |
11420 | return FALSE; | |
11421 | } | |
11422 | ||
11423 | ||
7fa3d080 BW |
11424 | static void |
11425 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11426 | { |
11427 | int i; | |
11428 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11429 | for (i = 0; i < MAX_SLOTS; i++) | |
11430 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11431 | } | |
11432 | ||
11433 | ||
e7da6241 BW |
11434 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11435 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11436 | |
11437 | static bfd_boolean | |
7fa3d080 BW |
11438 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11439 | char *frag_offset, | |
11440 | fragS *fragP, | |
11441 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11442 | { |
11443 | xtensa_isa isa = xtensa_default_isa; | |
11444 | xtensa_format fmt = vinsn->format; | |
11445 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11446 | int slot; | |
11447 | bfd_boolean has_fixup = FALSE; | |
11448 | ||
11449 | xtensa_format_encode (isa, fmt, insnbuf); | |
11450 | ||
11451 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11452 | { | |
11453 | TInsn *tinsn = &vinsn->slots[slot]; | |
11454 | bfd_boolean tinsn_has_fixup = | |
11455 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11456 | vinsn->slotbuf[slot]); | |
11457 | ||
11458 | xtensa_format_set_slot (isa, fmt, slot, | |
11459 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11460 | if (tinsn_has_fixup) |
43cd72b9 BW |
11461 | { |
11462 | int i; | |
11463 | xtensa_opcode opcode = tinsn->opcode; | |
11464 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11465 | has_fixup = TRUE; | |
11466 | ||
11467 | for (i = 0; i < noperands; i++) | |
11468 | { | |
11469 | expressionS* expr = &tinsn->tok[i]; | |
11470 | switch (expr->X_op) | |
11471 | { | |
11472 | case O_symbol: | |
11473 | case O_lo16: | |
11474 | case O_hi16: | |
11475 | if (get_relaxable_immed (opcode) == i) | |
11476 | { | |
e7da6241 BW |
11477 | /* Add a fix record for the instruction, except if this |
11478 | function is being called prior to relaxation, i.e., | |
11479 | if record_fixup is false, and the instruction might | |
11480 | be relaxed later. */ | |
11481 | if (record_fixup | |
11482 | || tinsn->is_specific_opcode | |
11483 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11484 | { |
e7da6241 BW |
11485 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11486 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11487 | } |
11488 | else | |
11489 | { | |
e7da6241 BW |
11490 | if (expr->X_op != O_symbol) |
11491 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11492 | tinsn->symbol = expr->X_add_symbol; |
11493 | tinsn->offset = expr->X_add_number; | |
11494 | } | |
11495 | } | |
11496 | else | |
e7da6241 | 11497 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11498 | break; |
11499 | ||
11500 | case O_constant: | |
11501 | case O_register: | |
11502 | break; | |
11503 | ||
43cd72b9 | 11504 | default: |
e7da6241 | 11505 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11506 | break; |
11507 | } | |
11508 | } | |
11509 | } | |
11510 | } | |
11511 | ||
11512 | return has_fixup; | |
11513 | } | |
11514 | ||
11515 | ||
11516 | static void | |
7fa3d080 | 11517 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11518 | { |
11519 | static xtensa_insnbuf insnbuf = NULL; | |
11520 | static xtensa_insnbuf slotbuf = NULL; | |
11521 | int i; | |
11522 | xtensa_format fmt; | |
11523 | xtensa_isa isa = xtensa_default_isa; | |
11524 | ||
11525 | if (!insnbuf) | |
11526 | { | |
11527 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11528 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11529 | } | |
11530 | ||
d77b99c9 | 11531 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11532 | fmt = xtensa_format_decode (isa, insnbuf); |
11533 | if (fmt == XTENSA_UNDEFINED) | |
11534 | as_fatal (_("cannot decode instruction format")); | |
11535 | vinsn->format = fmt; | |
11536 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11537 | ||
11538 | for (i = 0; i < vinsn->num_slots; i++) | |
11539 | { | |
11540 | TInsn *tinsn = &vinsn->slots[i]; | |
11541 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11542 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11543 | } | |
11544 | } | |
11545 | ||
e0001a05 NC |
11546 | \f |
11547 | /* Expression utilities. */ | |
11548 | ||
43cd72b9 | 11549 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11550 | |
11551 | bfd_boolean | |
7fa3d080 | 11552 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11553 | { |
11554 | return (s->X_op == O_constant); | |
11555 | } | |
11556 | ||
11557 | ||
11558 | /* Get the expression constant. | |
43cd72b9 | 11559 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11560 | |
11561 | offsetT | |
7fa3d080 | 11562 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11563 | { |
11564 | assert (expr_is_const (s)); | |
11565 | return s->X_add_number; | |
11566 | } | |
11567 | ||
11568 | ||
11569 | /* Set the expression to a constant value. */ | |
11570 | ||
11571 | void | |
7fa3d080 | 11572 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11573 | { |
11574 | s->X_op = O_constant; | |
11575 | s->X_add_number = val; | |
11576 | s->X_add_symbol = NULL; | |
11577 | s->X_op_symbol = NULL; | |
11578 | } | |
11579 | ||
11580 | ||
43cd72b9 | 11581 | bfd_boolean |
7fa3d080 | 11582 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11583 | { |
11584 | return (s->X_op == O_register); | |
11585 | } | |
11586 | ||
11587 | ||
11588 | /* Get the expression constant. | |
11589 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11590 | ||
11591 | offsetT | |
7fa3d080 | 11592 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11593 | { |
11594 | assert (expr_is_register (s)); | |
11595 | return s->X_add_number; | |
11596 | } | |
11597 | ||
11598 | ||
e0001a05 NC |
11599 | /* Set the expression to a symbol + constant offset. */ |
11600 | ||
11601 | void | |
7fa3d080 | 11602 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11603 | { |
11604 | s->X_op = O_symbol; | |
11605 | s->X_add_symbol = sym; | |
11606 | s->X_op_symbol = NULL; /* unused */ | |
11607 | s->X_add_number = offset; | |
11608 | } | |
11609 | ||
11610 | ||
43cd72b9 BW |
11611 | /* Return TRUE if the two expressions are equal. */ |
11612 | ||
e0001a05 | 11613 | bfd_boolean |
7fa3d080 | 11614 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11615 | { |
11616 | if (s1->X_op != s2->X_op) | |
11617 | return FALSE; | |
11618 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11619 | return FALSE; | |
11620 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11621 | return FALSE; | |
11622 | if (s1->X_add_number != s2->X_add_number) | |
11623 | return FALSE; | |
11624 | return TRUE; | |
11625 | } | |
11626 | ||
11627 | ||
11628 | static void | |
7fa3d080 | 11629 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11630 | { |
11631 | memcpy (dst, src, sizeof (expressionS)); | |
11632 | } | |
11633 | ||
11634 | \f | |
9456465c | 11635 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11636 | |
11637 | struct rename_section_struct | |
11638 | { | |
11639 | char *old_name; | |
11640 | char *new_name; | |
11641 | struct rename_section_struct *next; | |
11642 | }; | |
11643 | ||
11644 | static struct rename_section_struct *section_rename; | |
11645 | ||
11646 | ||
9456465c BW |
11647 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11648 | entries to the section_rename list. Note: Specifying multiple | |
11649 | renamings separated by colons is not documented and is retained only | |
11650 | for backward compatibility. */ | |
e0001a05 | 11651 | |
7fa3d080 BW |
11652 | static void |
11653 | build_section_rename (const char *arg) | |
e0001a05 | 11654 | { |
9456465c | 11655 | struct rename_section_struct *r; |
e0001a05 NC |
11656 | char *this_arg = NULL; |
11657 | char *next_arg = NULL; | |
11658 | ||
9456465c | 11659 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11660 | { |
9456465c BW |
11661 | char *old_name, *new_name; |
11662 | ||
e0001a05 NC |
11663 | if (this_arg) |
11664 | { | |
11665 | next_arg = strchr (this_arg, ':'); | |
11666 | if (next_arg) | |
11667 | { | |
11668 | *next_arg = '\0'; | |
11669 | next_arg++; | |
11670 | } | |
11671 | } | |
e0001a05 | 11672 | |
9456465c BW |
11673 | old_name = this_arg; |
11674 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11675 | |
9456465c BW |
11676 | if (*old_name == '\0') |
11677 | { | |
11678 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11679 | continue; | |
11680 | } | |
11681 | if (!new_name || new_name[1] == '\0') | |
11682 | { | |
11683 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11684 | old_name); | |
11685 | continue; | |
11686 | } | |
11687 | *new_name = '\0'; | |
11688 | new_name++; | |
e0001a05 | 11689 | |
9456465c BW |
11690 | /* Check for invalid section renaming. */ |
11691 | for (r = section_rename; r != NULL; r = r->next) | |
11692 | { | |
11693 | if (strcmp (r->old_name, old_name) == 0) | |
11694 | as_bad (_("section %s renamed multiple times"), old_name); | |
11695 | if (strcmp (r->new_name, new_name) == 0) | |
11696 | as_bad (_("multiple sections remapped to output section %s"), | |
11697 | new_name); | |
11698 | } | |
e0001a05 | 11699 | |
9456465c BW |
11700 | /* Now add it. */ |
11701 | r = (struct rename_section_struct *) | |
11702 | xmalloc (sizeof (struct rename_section_struct)); | |
11703 | r->old_name = xstrdup (old_name); | |
11704 | r->new_name = xstrdup (new_name); | |
11705 | r->next = section_rename; | |
11706 | section_rename = r; | |
e0001a05 | 11707 | } |
e0001a05 NC |
11708 | } |
11709 | ||
11710 | ||
9456465c BW |
11711 | char * |
11712 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11713 | { |
11714 | struct rename_section_struct *r = section_rename; | |
11715 | ||
11716 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11717 | { |
11718 | if (strcmp (r->old_name, name) == 0) | |
11719 | return r->new_name; | |
11720 | } | |
e0001a05 NC |
11721 | |
11722 | return name; | |
11723 | } |