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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
fb227da0 | 2 | Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
77cba8a3 | 82 | unsigned xtensa_num_pipe_stages; |
d77b99c9 | 83 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
84 | |
85 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
86 | ||
87 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 88 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
89 | back end. */ |
90 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
91 | |
92 | /* Flags for properties of the last instruction in a segment. */ | |
93 | #define FLAG_IS_A0_WRITER 0x1 | |
94 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
95 | ||
96 | ||
97 | /* We define a special segment names ".literal" to place literals | |
98 | into. The .fini and .init sections are special because they | |
99 | contain code that is moved together by the linker. We give them | |
100 | their own special .fini.literal and .init.literal sections. */ | |
101 | ||
102 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 103 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 104 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 105 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
106 | |
107 | ||
43cd72b9 | 108 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
109 | state of the literal collection pools. If lit_prefix is set, it is |
110 | used to determine the literal section names; otherwise, the literal | |
111 | sections are determined based on the current text section. The | |
112 | lit_seg and lit4_seg fields cache these literal sections, with the | |
113 | current_text_seg field used a tag to indicate whether the cached | |
114 | values are valid. */ | |
e0001a05 NC |
115 | |
116 | typedef struct lit_state_struct | |
117 | { | |
74869ac7 BW |
118 | char *lit_prefix; |
119 | segT current_text_seg; | |
e0001a05 | 120 | segT lit_seg; |
43cd72b9 | 121 | segT lit4_seg; |
e0001a05 NC |
122 | } lit_state; |
123 | ||
124 | static lit_state default_lit_sections; | |
125 | ||
126 | ||
74869ac7 BW |
127 | /* We keep a list of literal segments. The seg_list type is the node |
128 | for this list. The literal_head pointer is the head of the list, | |
129 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
130 | |
131 | typedef struct seg_list_struct | |
132 | { | |
133 | struct seg_list_struct *next; | |
134 | segT seg; | |
135 | } seg_list; | |
136 | ||
137 | static seg_list literal_head_h; | |
138 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
139 | |
140 | ||
82e7541d BW |
141 | /* Lists of symbols. We keep a list of symbols that label the current |
142 | instruction, so that we can adjust the symbols when inserting alignment | |
143 | for various instructions. We also keep a list of all the symbols on | |
144 | literals, so that we can fix up those symbols when the literals are | |
145 | later moved into the text sections. */ | |
146 | ||
147 | typedef struct sym_list_struct | |
148 | { | |
149 | struct sym_list_struct *next; | |
150 | symbolS *sym; | |
151 | } sym_list; | |
152 | ||
153 | static sym_list *insn_labels = NULL; | |
154 | static sym_list *free_insn_labels = NULL; | |
155 | static sym_list *saved_insn_labels = NULL; | |
156 | ||
157 | static sym_list *literal_syms; | |
158 | ||
159 | ||
43cd72b9 BW |
160 | /* Flags to determine whether to prefer const16 or l32r |
161 | if both options are available. */ | |
162 | int prefer_const16 = 0; | |
163 | int prefer_l32r = 0; | |
164 | ||
e0001a05 NC |
165 | /* Global flag to indicate when we are emitting literals. */ |
166 | int generating_literals = 0; | |
167 | ||
43cd72b9 BW |
168 | /* The following PROPERTY table definitions are copied from |
169 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
170 | ||
171 | /* Flags in the property tables to specify whether blocks of memory | |
172 | are literals, instructions, data, or unreachable. For | |
173 | instructions, blocks that begin loop targets and branch targets are | |
174 | designated. Blocks that do not allow density, instruction | |
175 | reordering or transformation are also specified. Finally, for | |
176 | branch targets, branch target alignment priority is included. | |
177 | Alignment of the next block is specified in the current block | |
178 | and the size of the current block does not include any fill required | |
179 | to align to the next block. */ | |
180 | ||
181 | #define XTENSA_PROP_LITERAL 0x00000001 | |
182 | #define XTENSA_PROP_INSN 0x00000002 | |
183 | #define XTENSA_PROP_DATA 0x00000004 | |
184 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
185 | /* Instruction only properties at beginning of code. */ | |
186 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
187 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
188 | /* Instruction only properties about code. */ | |
189 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
190 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
191 | /* Historically, NO_TRANSFORM was a property of instructions, |
192 | but it should apply to literals under certain circumstances. */ | |
193 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
194 | |
195 | /* Branch target alignment information. This transmits information | |
196 | to the linker optimization about the priority of aligning a | |
197 | particular block for branch target alignment: None, low priority, | |
198 | high priority, or required. These only need to be checked in | |
199 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
200 | Common usage is | |
201 | ||
202 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
203 | case XTENSA_PROP_BT_ALIGN_NONE: | |
204 | case XTENSA_PROP_BT_ALIGN_LOW: | |
205 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
206 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
207 | */ | |
208 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
209 | ||
210 | /* No branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
212 | /* Low priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
214 | /* High priority branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
216 | /* Required branch target alignment. */ | |
217 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
218 | ||
219 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
220 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
221 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
222 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
223 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
224 | ||
225 | ||
226 | /* Alignment is specified in the block BEFORE the one that needs | |
227 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
228 | get the required alignment specified as a power of 2. Use | |
229 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
230 | alignment. Be careful of side effects since the SET will evaluate | |
231 | flags twice. Also, note that the SIZE of a block in the property | |
232 | table does not include the alignment size, so the alignment fill | |
233 | must be calculated to determine if two blocks are contiguous. | |
234 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
235 | possible future implementation. */ | |
236 | ||
237 | #define XTENSA_PROP_ALIGN 0x00000800 | |
238 | ||
239 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
240 | ||
241 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
242 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
243 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
244 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
245 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
246 | ||
247 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
248 | ||
249 | ||
250 | /* Structure for saving instruction and alignment per-fragment data | |
251 | that will be written to the object file. This structure is | |
252 | equivalent to the actual data that will be written out to the file | |
253 | but is easier to use. We provide a conversion to file flags | |
254 | in frag_flags_to_number. */ | |
255 | ||
256 | typedef struct frag_flags_struct frag_flags; | |
257 | ||
258 | struct frag_flags_struct | |
259 | { | |
260 | /* is_literal should only be used after xtensa_move_literals. | |
261 | If you need to check if you are generating a literal fragment, | |
262 | then use the generating_literals global. */ | |
263 | ||
264 | unsigned is_literal : 1; | |
265 | unsigned is_insn : 1; | |
266 | unsigned is_data : 1; | |
267 | unsigned is_unreachable : 1; | |
268 | ||
99ded152 BW |
269 | /* is_specific_opcode implies no_transform. */ |
270 | unsigned is_no_transform : 1; | |
271 | ||
43cd72b9 BW |
272 | struct |
273 | { | |
274 | unsigned is_loop_target : 1; | |
275 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
276 | unsigned bt_align_priority : 2; | |
277 | ||
278 | unsigned is_no_density : 1; | |
279 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
280 | |
281 | unsigned is_no_reorder : 1; | |
282 | ||
283 | /* Uses absolute literal addressing for l32r. */ | |
284 | unsigned is_abslit : 1; | |
285 | } insn; | |
286 | unsigned is_align : 1; | |
287 | unsigned alignment : 5; | |
288 | }; | |
289 | ||
290 | ||
291 | /* Structure for saving information about a block of property data | |
292 | for frags that have the same flags. */ | |
293 | struct xtensa_block_info_struct | |
294 | { | |
295 | segT sec; | |
296 | bfd_vma offset; | |
297 | size_t size; | |
298 | frag_flags flags; | |
299 | struct xtensa_block_info_struct *next; | |
300 | }; | |
301 | ||
e0001a05 NC |
302 | |
303 | /* Structure for saving the current state before emitting literals. */ | |
304 | typedef struct emit_state_struct | |
305 | { | |
306 | const char *name; | |
307 | segT now_seg; | |
308 | subsegT now_subseg; | |
309 | int generating_literals; | |
310 | } emit_state; | |
311 | ||
312 | ||
43cd72b9 BW |
313 | /* Opcode placement information */ |
314 | ||
315 | typedef unsigned long long bitfield; | |
316 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
317 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
318 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
319 | ||
320 | #define MAX_FORMATS 32 | |
321 | ||
322 | typedef struct op_placement_info_struct | |
323 | { | |
324 | int num_formats; | |
325 | /* A number describing how restrictive the issue is for this | |
326 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 327 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 328 | only one format but many slots in that format. The most |
c138bc38 | 329 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
330 | format. */ |
331 | int issuef; | |
43cd72b9 | 332 | xtensa_format narrowest; |
43cd72b9 | 333 | char narrowest_size; |
b2d179be | 334 | char narrowest_slot; |
43cd72b9 BW |
335 | |
336 | /* formats is a bitfield with the Nth bit set | |
337 | if the opcode fits in the Nth xtensa_format. */ | |
338 | bitfield formats; | |
339 | ||
340 | /* slots[N]'s Mth bit is set if the op fits in the | |
341 | Mth slot of the Nth xtensa_format. */ | |
342 | bitfield slots[MAX_FORMATS]; | |
343 | ||
344 | /* A count of the number of slots in a given format | |
345 | an op can fit (i.e., the bitcount of the slot field above). */ | |
346 | char slots_in_format[MAX_FORMATS]; | |
347 | ||
348 | } op_placement_info, *op_placement_info_table; | |
349 | ||
350 | op_placement_info_table op_placement_table; | |
351 | ||
352 | ||
353 | /* Extra expression types. */ | |
354 | ||
355 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
356 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
357 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 358 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
359 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
360 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
361 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
362 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
363 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 364 | |
bbdd25a8 BW |
365 | struct suffix_reloc_map |
366 | { | |
367 | char *suffix; | |
368 | int length; | |
369 | bfd_reloc_code_real_type reloc; | |
370 | unsigned char operator; | |
371 | }; | |
372 | ||
373 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
374 | ||
375 | static struct suffix_reloc_map suffix_relocs[] = | |
376 | { | |
377 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
378 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
379 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 380 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
381 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
382 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
383 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
384 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
385 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
386 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } |
387 | }; | |
388 | ||
43cd72b9 | 389 | |
e0001a05 NC |
390 | /* Directives. */ |
391 | ||
392 | typedef enum | |
393 | { | |
394 | directive_none = 0, | |
395 | directive_literal, | |
396 | directive_density, | |
43cd72b9 | 397 | directive_transform, |
e0001a05 NC |
398 | directive_freeregs, |
399 | directive_longcalls, | |
43cd72b9 BW |
400 | directive_literal_prefix, |
401 | directive_schedule, | |
402 | directive_absolute_literals, | |
403 | directive_last_directive | |
e0001a05 NC |
404 | } directiveE; |
405 | ||
406 | typedef struct | |
407 | { | |
408 | const char *name; | |
409 | bfd_boolean can_be_negated; | |
410 | } directive_infoS; | |
411 | ||
412 | const directive_infoS directive_info[] = | |
413 | { | |
43cd72b9 BW |
414 | { "none", FALSE }, |
415 | { "literal", FALSE }, | |
416 | { "density", TRUE }, | |
417 | { "transform", TRUE }, | |
418 | { "freeregs", FALSE }, | |
419 | { "longcalls", TRUE }, | |
420 | { "literal_prefix", FALSE }, | |
421 | { "schedule", TRUE }, | |
422 | { "absolute-literals", TRUE } | |
e0001a05 NC |
423 | }; |
424 | ||
425 | bfd_boolean directive_state[] = | |
426 | { | |
427 | FALSE, /* none */ | |
428 | FALSE, /* literal */ | |
43cd72b9 | 429 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
430 | FALSE, /* density */ |
431 | #else | |
432 | TRUE, /* density */ | |
433 | #endif | |
43cd72b9 | 434 | TRUE, /* transform */ |
e0001a05 NC |
435 | FALSE, /* freeregs */ |
436 | FALSE, /* longcalls */ | |
43cd72b9 | 437 | FALSE, /* literal_prefix */ |
2caa7ca0 | 438 | FALSE, /* schedule */ |
43cd72b9 BW |
439 | #if XSHAL_USE_ABSOLUTE_LITERALS |
440 | TRUE /* absolute_literals */ | |
441 | #else | |
442 | FALSE /* absolute_literals */ | |
443 | #endif | |
e0001a05 NC |
444 | }; |
445 | ||
e0001a05 NC |
446 | |
447 | /* Directive functions. */ | |
448 | ||
7fa3d080 BW |
449 | static void xtensa_begin_directive (int); |
450 | static void xtensa_end_directive (int); | |
74869ac7 | 451 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
452 | static void xtensa_literal_position (int); |
453 | static void xtensa_literal_pseudo (int); | |
454 | static void xtensa_frequency_pseudo (int); | |
455 | static void xtensa_elf_cons (int); | |
fb227da0 | 456 | static void xtensa_leb128 (int); |
e0001a05 | 457 | |
7fa3d080 | 458 | /* Parsing and Idiom Translation. */ |
e0001a05 | 459 | |
7fa3d080 | 460 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 461 | |
e0001a05 NC |
462 | /* Various Other Internal Functions. */ |
463 | ||
84b08ed9 BW |
464 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
465 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
466 | static void xtensa_mark_literal_pool_location (void); |
467 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
468 | static fragS *get_literal_pool_location (segT); | |
469 | static void set_literal_pool_location (segT, fragS *); | |
470 | static void xtensa_set_frag_assembly_state (fragS *); | |
471 | static void finish_vinsn (vliw_insn *); | |
472 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 473 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
474 | |
475 | /* Alignment Functions. */ | |
476 | ||
d77b99c9 BW |
477 | static int get_text_align_power (unsigned); |
478 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 479 | static int branch_align_power (segT); |
e0001a05 NC |
480 | |
481 | /* Helpers for xtensa_relax_frag(). */ | |
482 | ||
7fa3d080 | 483 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 484 | |
b08b5071 | 485 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 486 | |
7fa3d080 BW |
487 | static unsigned get_last_insn_flags (segT, subsegT); |
488 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
489 | static float get_subseg_total_freq (segT, subsegT); |
490 | static float get_subseg_target_freq (segT, subsegT); | |
491 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
492 | |
493 | /* Segment list functions. */ | |
494 | ||
7fa3d080 BW |
495 | static void xtensa_move_literals (void); |
496 | static void xtensa_reorder_segments (void); | |
497 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
498 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
499 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
500 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 501 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 502 | |
e0001a05 | 503 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 504 | |
51c8ebc1 | 505 | extern asection *xtensa_make_property_section (asection *, const char *); |
e0001a05 | 506 | |
43cd72b9 BW |
507 | /* op_placement_info functions. */ |
508 | ||
7fa3d080 BW |
509 | static void init_op_placement_info_table (void); |
510 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
511 | static int xg_get_single_size (xtensa_opcode); | |
512 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 513 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 514 | |
e0001a05 | 515 | /* TInsn and IStack functions. */ |
43cd72b9 | 516 | |
7fa3d080 BW |
517 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
518 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
519 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
520 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
521 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
522 | static void tinsn_from_chars (TInsn *, char *, int); | |
523 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
524 | static int get_num_stack_text_bytes (IStack *); | |
525 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 526 | |
43cd72b9 BW |
527 | /* vliw_insn functions. */ |
528 | ||
7fa3d080 BW |
529 | static void xg_init_vinsn (vliw_insn *); |
530 | static void xg_clear_vinsn (vliw_insn *); | |
531 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
532 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 533 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
534 | (vliw_insn *, char *, fragS *, bfd_boolean); |
535 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 536 | |
e0001a05 | 537 | /* Expression Utilities. */ |
43cd72b9 | 538 | |
7fa3d080 BW |
539 | bfd_boolean expr_is_const (const expressionS *); |
540 | offsetT get_expr_const (const expressionS *); | |
541 | void set_expr_const (expressionS *, offsetT); | |
542 | bfd_boolean expr_is_register (const expressionS *); | |
543 | offsetT get_expr_register (const expressionS *); | |
544 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
545 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
546 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 547 | |
9456465c BW |
548 | /* Section renaming. */ |
549 | ||
7fa3d080 | 550 | static void build_section_rename (const char *); |
e0001a05 | 551 | |
e0001a05 NC |
552 | |
553 | /* ISA imported from bfd. */ | |
554 | extern xtensa_isa xtensa_default_isa; | |
555 | ||
556 | extern int target_big_endian; | |
557 | ||
558 | static xtensa_opcode xtensa_addi_opcode; | |
559 | static xtensa_opcode xtensa_addmi_opcode; | |
560 | static xtensa_opcode xtensa_call0_opcode; | |
561 | static xtensa_opcode xtensa_call4_opcode; | |
562 | static xtensa_opcode xtensa_call8_opcode; | |
563 | static xtensa_opcode xtensa_call12_opcode; | |
564 | static xtensa_opcode xtensa_callx0_opcode; | |
565 | static xtensa_opcode xtensa_callx4_opcode; | |
566 | static xtensa_opcode xtensa_callx8_opcode; | |
567 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 568 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 569 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 570 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
571 | static xtensa_opcode xtensa_movi_opcode; |
572 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 573 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 574 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 575 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 576 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
577 | static xtensa_opcode xtensa_loop_opcode; |
578 | static xtensa_opcode xtensa_loopnez_opcode; | |
579 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 580 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
581 | static xtensa_opcode xtensa_nop_n_opcode; |
582 | static xtensa_opcode xtensa_or_opcode; | |
583 | static xtensa_opcode xtensa_ret_opcode; | |
584 | static xtensa_opcode xtensa_ret_n_opcode; | |
585 | static xtensa_opcode xtensa_retw_opcode; | |
586 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 587 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
588 | static xtensa_opcode xtensa_waiti_opcode; |
589 | ||
590 | \f | |
591 | /* Command-line Options. */ | |
592 | ||
593 | bfd_boolean use_literal_section = TRUE; | |
594 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 595 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 596 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
597 | static bfd_boolean workaround_a0_b_retw = FALSE; |
598 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
599 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 600 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 601 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 602 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 603 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 604 | |
43cd72b9 BW |
605 | /* When workaround_short_loops is TRUE, all loops with early exits must |
606 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
607 | to the workaround_short_loop flag. In addition to the | |
608 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
609 | must have at least 3 instructions. */ | |
e0001a05 | 610 | |
43cd72b9 | 611 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 612 | |
7fa3d080 BW |
613 | |
614 | static void | |
615 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
616 | { | |
617 | if (earliest > latest) | |
618 | as_fatal (_("illegal range of target hardware versions")); | |
619 | ||
620 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
621 | if (earliest < 105000 || latest < 105000) | |
622 | { | |
623 | workaround_a0_b_retw |= TRUE; | |
624 | workaround_b_j_loop_end |= TRUE; | |
625 | workaround_short_loop |= TRUE; | |
626 | workaround_close_loop_end |= TRUE; | |
627 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 628 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
629 | } |
630 | } | |
631 | ||
632 | ||
e0001a05 NC |
633 | enum |
634 | { | |
635 | option_density = OPTION_MD_BASE, | |
636 | option_no_density, | |
637 | ||
638 | option_relax, | |
639 | option_no_relax, | |
640 | ||
43cd72b9 BW |
641 | option_link_relax, |
642 | option_no_link_relax, | |
643 | ||
e0001a05 NC |
644 | option_generics, |
645 | option_no_generics, | |
646 | ||
43cd72b9 BW |
647 | option_transform, |
648 | option_no_transform, | |
649 | ||
e0001a05 NC |
650 | option_text_section_literals, |
651 | option_no_text_section_literals, | |
652 | ||
43cd72b9 BW |
653 | option_absolute_literals, |
654 | option_no_absolute_literals, | |
655 | ||
e0001a05 NC |
656 | option_align_targets, |
657 | option_no_align_targets, | |
658 | ||
43cd72b9 | 659 | option_warn_unaligned_targets, |
e0001a05 NC |
660 | |
661 | option_longcalls, | |
662 | option_no_longcalls, | |
663 | ||
664 | option_workaround_a0_b_retw, | |
665 | option_no_workaround_a0_b_retw, | |
666 | ||
667 | option_workaround_b_j_loop_end, | |
668 | option_no_workaround_b_j_loop_end, | |
669 | ||
670 | option_workaround_short_loop, | |
671 | option_no_workaround_short_loop, | |
672 | ||
673 | option_workaround_all_short_loops, | |
674 | option_no_workaround_all_short_loops, | |
675 | ||
676 | option_workaround_close_loop_end, | |
677 | option_no_workaround_close_loop_end, | |
678 | ||
679 | option_no_workarounds, | |
680 | ||
e0001a05 | 681 | option_rename_section_name, |
e0001a05 | 682 | |
43cd72b9 BW |
683 | option_prefer_l32r, |
684 | option_prefer_const16, | |
685 | ||
686 | option_target_hardware | |
e0001a05 NC |
687 | }; |
688 | ||
689 | const char *md_shortopts = ""; | |
690 | ||
691 | struct option md_longopts[] = | |
692 | { | |
43cd72b9 BW |
693 | { "density", no_argument, NULL, option_density }, |
694 | { "no-density", no_argument, NULL, option_no_density }, | |
695 | ||
696 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
697 | to the "transform" option. */ | |
698 | { "relax", no_argument, NULL, option_relax }, | |
699 | { "no-relax", no_argument, NULL, option_no_relax }, | |
700 | { "generics", no_argument, NULL, option_generics }, | |
701 | { "no-generics", no_argument, NULL, option_no_generics }, | |
702 | ||
703 | { "transform", no_argument, NULL, option_transform }, | |
704 | { "no-transform", no_argument, NULL, option_no_transform }, | |
705 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
706 | { "no-text-section-literals", no_argument, NULL, | |
707 | option_no_text_section_literals }, | |
708 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
709 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
710 | /* This option was changed from -align-target to -target-align |
711 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 712 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
713 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
714 | { "warn-unaligned-targets", no_argument, NULL, | |
715 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
716 | { "longcalls", no_argument, NULL, option_longcalls }, |
717 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
718 | ||
719 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
720 | option_no_workaround_a0_b_retw }, | |
721 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 722 | |
43cd72b9 BW |
723 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
724 | option_no_workaround_b_j_loop_end }, | |
725 | { "workaround-b-j-loop-end", no_argument, NULL, | |
726 | option_workaround_b_j_loop_end }, | |
e0001a05 | 727 | |
43cd72b9 BW |
728 | { "no-workaround-short-loops", no_argument, NULL, |
729 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
730 | { "workaround-short-loops", no_argument, NULL, |
731 | option_workaround_short_loop }, | |
e0001a05 | 732 | |
43cd72b9 BW |
733 | { "no-workaround-all-short-loops", no_argument, NULL, |
734 | option_no_workaround_all_short_loops }, | |
735 | { "workaround-all-short-loop", no_argument, NULL, | |
736 | option_workaround_all_short_loops }, | |
737 | ||
738 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
739 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
740 | ||
741 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
742 | ||
743 | { "no-workaround-close-loop-end", no_argument, NULL, | |
744 | option_no_workaround_close_loop_end }, | |
745 | { "workaround-close-loop-end", no_argument, NULL, | |
746 | option_workaround_close_loop_end }, | |
e0001a05 | 747 | |
7fa3d080 | 748 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 749 | |
43cd72b9 BW |
750 | { "link-relax", no_argument, NULL, option_link_relax }, |
751 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
752 | ||
753 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
754 | ||
755 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
756 | }; |
757 | ||
758 | size_t md_longopts_size = sizeof md_longopts; | |
759 | ||
760 | ||
761 | int | |
7fa3d080 | 762 | md_parse_option (int c, char *arg) |
e0001a05 NC |
763 | { |
764 | switch (c) | |
765 | { | |
766 | case option_density: | |
43cd72b9 | 767 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
768 | return 1; |
769 | case option_no_density: | |
43cd72b9 | 770 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 771 | return 1; |
43cd72b9 BW |
772 | case option_link_relax: |
773 | linkrelax = 1; | |
e0001a05 | 774 | return 1; |
43cd72b9 BW |
775 | case option_no_link_relax: |
776 | linkrelax = 0; | |
e0001a05 | 777 | return 1; |
43cd72b9 BW |
778 | case option_generics: |
779 | as_warn (_("--generics is deprecated; use --transform instead")); | |
780 | return md_parse_option (option_transform, arg); | |
781 | case option_no_generics: | |
782 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
783 | return md_parse_option (option_no_transform, arg); | |
784 | case option_relax: | |
785 | as_warn (_("--relax is deprecated; use --transform instead")); | |
786 | return md_parse_option (option_transform, arg); | |
787 | case option_no_relax: | |
788 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
789 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
790 | case option_longcalls: |
791 | directive_state[directive_longcalls] = TRUE; | |
792 | return 1; | |
793 | case option_no_longcalls: | |
794 | directive_state[directive_longcalls] = FALSE; | |
795 | return 1; | |
796 | case option_text_section_literals: | |
797 | use_literal_section = FALSE; | |
798 | return 1; | |
799 | case option_no_text_section_literals: | |
800 | use_literal_section = TRUE; | |
801 | return 1; | |
43cd72b9 BW |
802 | case option_absolute_literals: |
803 | if (!absolute_literals_supported) | |
804 | { | |
805 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
806 | return 0; | |
807 | } | |
808 | directive_state[directive_absolute_literals] = TRUE; | |
809 | return 1; | |
810 | case option_no_absolute_literals: | |
811 | directive_state[directive_absolute_literals] = FALSE; | |
812 | return 1; | |
813 | ||
e0001a05 NC |
814 | case option_workaround_a0_b_retw: |
815 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
816 | return 1; |
817 | case option_no_workaround_a0_b_retw: | |
818 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
819 | return 1; |
820 | case option_workaround_b_j_loop_end: | |
821 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
822 | return 1; |
823 | case option_no_workaround_b_j_loop_end: | |
824 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
825 | return 1; |
826 | ||
827 | case option_workaround_short_loop: | |
828 | workaround_short_loop = TRUE; | |
e0001a05 NC |
829 | return 1; |
830 | case option_no_workaround_short_loop: | |
831 | workaround_short_loop = FALSE; | |
e0001a05 NC |
832 | return 1; |
833 | ||
834 | case option_workaround_all_short_loops: | |
835 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
836 | return 1; |
837 | case option_no_workaround_all_short_loops: | |
838 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
839 | return 1; |
840 | ||
841 | case option_workaround_close_loop_end: | |
842 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
843 | return 1; |
844 | case option_no_workaround_close_loop_end: | |
845 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
846 | return 1; |
847 | ||
848 | case option_no_workarounds: | |
849 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 850 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 851 | workaround_short_loop = FALSE; |
e0001a05 | 852 | workaround_all_short_loops = FALSE; |
e0001a05 | 853 | workaround_close_loop_end = FALSE; |
e0001a05 | 854 | return 1; |
43cd72b9 | 855 | |
e0001a05 NC |
856 | case option_align_targets: |
857 | align_targets = TRUE; | |
858 | return 1; | |
859 | case option_no_align_targets: | |
860 | align_targets = FALSE; | |
861 | return 1; | |
862 | ||
43cd72b9 BW |
863 | case option_warn_unaligned_targets: |
864 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
865 | return 1; |
866 | ||
e0001a05 NC |
867 | case option_rename_section_name: |
868 | build_section_rename (arg); | |
869 | return 1; | |
e0001a05 NC |
870 | |
871 | case 'Q': | |
872 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
873 | should be emitted or not. FIXME: Not implemented. */ | |
874 | return 1; | |
c138bc38 | 875 | |
43cd72b9 BW |
876 | case option_prefer_l32r: |
877 | if (prefer_const16) | |
878 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
879 | prefer_l32r = 1; | |
880 | return 1; | |
881 | ||
882 | case option_prefer_const16: | |
883 | if (prefer_l32r) | |
884 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
885 | prefer_const16 = 1; | |
886 | return 1; | |
887 | ||
c138bc38 | 888 | case option_target_hardware: |
43cd72b9 BW |
889 | { |
890 | int earliest, latest = 0; | |
891 | if (*arg == 0 || *arg == '-') | |
892 | as_fatal (_("invalid target hardware version")); | |
893 | ||
894 | earliest = strtol (arg, &arg, 0); | |
895 | ||
896 | if (*arg == 0) | |
897 | latest = earliest; | |
898 | else if (*arg == '-') | |
899 | { | |
900 | if (*++arg == 0) | |
901 | as_fatal (_("invalid target hardware version")); | |
902 | latest = strtol (arg, &arg, 0); | |
903 | } | |
904 | if (*arg != 0) | |
905 | as_fatal (_("invalid target hardware version")); | |
906 | ||
907 | xtensa_setup_hw_workarounds (earliest, latest); | |
908 | return 1; | |
909 | } | |
910 | ||
911 | case option_transform: | |
912 | /* This option has no affect other than to use the defaults, | |
913 | which are already set. */ | |
914 | return 1; | |
915 | ||
916 | case option_no_transform: | |
917 | /* This option turns off all transformations of any kind. | |
918 | However, because we want to preserve the state of other | |
919 | directives, we only change its own field. Thus, before | |
920 | you perform any transformation, always check if transform | |
921 | is available. If you use the functions we provide for this | |
922 | purpose, you will be ok. */ | |
923 | directive_state[directive_transform] = FALSE; | |
924 | return 1; | |
925 | ||
e0001a05 NC |
926 | default: |
927 | return 0; | |
928 | } | |
929 | } | |
930 | ||
931 | ||
932 | void | |
7fa3d080 | 933 | md_show_usage (FILE *stream) |
e0001a05 | 934 | { |
43cd72b9 BW |
935 | fputs ("\n\ |
936 | Xtensa options:\n\ | |
9456465c BW |
937 | --[no-]text-section-literals\n\ |
938 | [Do not] put literals in the text section\n\ | |
939 | --[no-]absolute-literals\n\ | |
940 | [Do not] default to use non-PC-relative literals\n\ | |
941 | --[no-]target-align [Do not] try to align branch targets\n\ | |
942 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
943 | --[no-]transform [Do not] transform instructions\n\ | |
944 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
945 | } |
946 | ||
7fa3d080 BW |
947 | \f |
948 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
949 | |
950 | static void | |
7fa3d080 | 951 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 952 | { |
7fa3d080 | 953 | sym_list *l; |
43cd72b9 | 954 | |
7fa3d080 BW |
955 | if (!free_insn_labels) |
956 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
957 | else | |
43cd72b9 | 958 | { |
7fa3d080 BW |
959 | l = free_insn_labels; |
960 | free_insn_labels = l->next; | |
961 | } | |
962 | ||
963 | l->sym = sym; | |
964 | l->next = insn_labels; | |
965 | insn_labels = l; | |
966 | } | |
967 | ||
968 | ||
969 | static void | |
970 | xtensa_clear_insn_labels (void) | |
971 | { | |
972 | sym_list **pl; | |
973 | ||
974 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
975 | ; | |
976 | *pl = insn_labels; | |
977 | insn_labels = NULL; | |
978 | } | |
979 | ||
980 | ||
7fa3d080 | 981 | static void |
c3ea6048 | 982 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
983 | { |
984 | sym_list *lit; | |
985 | ||
986 | for (lit = insn_labels; lit; lit = lit->next) | |
987 | { | |
988 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
989 | S_SET_VALUE (lit_sym, new_offset); |
990 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
991 | } |
992 | } | |
993 | ||
e0001a05 NC |
994 | \f |
995 | /* Directive data and functions. */ | |
996 | ||
997 | typedef struct state_stackS_struct | |
998 | { | |
999 | directiveE directive; | |
1000 | bfd_boolean negated; | |
1001 | bfd_boolean old_state; | |
1002 | const char *file; | |
1003 | unsigned int line; | |
1004 | const void *datum; | |
1005 | struct state_stackS_struct *prev; | |
1006 | } state_stackS; | |
1007 | ||
1008 | state_stackS *directive_state_stack; | |
1009 | ||
1010 | const pseudo_typeS md_pseudo_table[] = | |
1011 | { | |
43cd72b9 BW |
1012 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1013 | { "literal_position", xtensa_literal_position, 0 }, | |
1014 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1015 | { "long", xtensa_elf_cons, 4 }, | |
1016 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1017 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1018 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1019 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1020 | { "sleb128", xtensa_leb128, 1}, |
1021 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1022 | { "begin", xtensa_begin_directive, 0 }, |
1023 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1024 | { "literal", xtensa_literal_pseudo, 0 }, |
1025 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1026 | { NULL, 0, 0 }, | |
e0001a05 NC |
1027 | }; |
1028 | ||
1029 | ||
7fa3d080 BW |
1030 | static bfd_boolean |
1031 | use_transform (void) | |
e0001a05 | 1032 | { |
43cd72b9 BW |
1033 | /* After md_end, you should be checking frag by frag, rather |
1034 | than state directives. */ | |
1035 | assert (!past_xtensa_end); | |
1036 | return directive_state[directive_transform]; | |
e0001a05 NC |
1037 | } |
1038 | ||
1039 | ||
7fa3d080 BW |
1040 | static bfd_boolean |
1041 | do_align_targets (void) | |
e0001a05 | 1042 | { |
7b1cc377 BW |
1043 | /* Do not use this function after md_end; just look at align_targets |
1044 | instead. There is no target-align directive, so alignment is either | |
1045 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1046 | assert (!past_xtensa_end); |
1047 | return align_targets && use_transform (); | |
e0001a05 NC |
1048 | } |
1049 | ||
1050 | ||
1051 | static void | |
7fa3d080 | 1052 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1053 | { |
1054 | char *file; | |
1055 | unsigned int line; | |
1056 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1057 | ||
1058 | as_where (&file, &line); | |
1059 | ||
1060 | stack->directive = directive; | |
1061 | stack->negated = negated; | |
1062 | stack->old_state = directive_state[directive]; | |
1063 | stack->file = file; | |
1064 | stack->line = line; | |
1065 | stack->datum = datum; | |
1066 | stack->prev = directive_state_stack; | |
1067 | directive_state_stack = stack; | |
1068 | ||
1069 | directive_state[directive] = !negated; | |
1070 | } | |
1071 | ||
7fa3d080 | 1072 | |
e0001a05 | 1073 | static void |
7fa3d080 BW |
1074 | directive_pop (directiveE *directive, |
1075 | bfd_boolean *negated, | |
1076 | const char **file, | |
1077 | unsigned int *line, | |
1078 | const void **datum) | |
e0001a05 NC |
1079 | { |
1080 | state_stackS *top = directive_state_stack; | |
1081 | ||
1082 | if (!directive_state_stack) | |
1083 | { | |
1084 | as_bad (_("unmatched end directive")); | |
1085 | *directive = directive_none; | |
1086 | return; | |
1087 | } | |
1088 | ||
1089 | directive_state[directive_state_stack->directive] = top->old_state; | |
1090 | *directive = top->directive; | |
1091 | *negated = top->negated; | |
1092 | *file = top->file; | |
1093 | *line = top->line; | |
1094 | *datum = top->datum; | |
1095 | directive_state_stack = top->prev; | |
1096 | free (top); | |
1097 | } | |
1098 | ||
1099 | ||
1100 | static void | |
7fa3d080 | 1101 | directive_balance (void) |
e0001a05 NC |
1102 | { |
1103 | while (directive_state_stack) | |
1104 | { | |
1105 | directiveE directive; | |
1106 | bfd_boolean negated; | |
1107 | const char *file; | |
1108 | unsigned int line; | |
1109 | const void *datum; | |
1110 | ||
1111 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1112 | as_warn_where ((char *) file, line, | |
1113 | _(".begin directive with no matching .end directive")); | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | ||
1118 | static bfd_boolean | |
7fa3d080 | 1119 | inside_directive (directiveE dir) |
e0001a05 NC |
1120 | { |
1121 | state_stackS *top = directive_state_stack; | |
1122 | ||
1123 | while (top && top->directive != dir) | |
1124 | top = top->prev; | |
1125 | ||
1126 | return (top != NULL); | |
1127 | } | |
1128 | ||
1129 | ||
1130 | static void | |
7fa3d080 | 1131 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1132 | { |
1133 | int len; | |
1134 | unsigned i; | |
43cd72b9 | 1135 | char *directive_string; |
e0001a05 NC |
1136 | |
1137 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1138 | *negated = FALSE; | |
1139 | else | |
1140 | { | |
1141 | *negated = TRUE; | |
1142 | input_line_pointer += 3; | |
1143 | } | |
1144 | ||
1145 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1146 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1147 | ||
1148 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1149 | equivalent to .begin [no-]transform. We should remove it when | |
1150 | we stop accepting those options. */ | |
c138bc38 | 1151 | |
43cd72b9 BW |
1152 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1153 | { | |
1154 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1155 | directive_string = "transform"; | |
1156 | } | |
1157 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1158 | { | |
1159 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1160 | directive_string = "transform"; | |
c138bc38 | 1161 | } |
43cd72b9 BW |
1162 | else |
1163 | directive_string = input_line_pointer; | |
e0001a05 NC |
1164 | |
1165 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1166 | { | |
43cd72b9 | 1167 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1168 | { |
1169 | input_line_pointer += len; | |
1170 | *directive = (directiveE) i; | |
1171 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1172 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1173 | directive_info[i].name); |
1174 | return; | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | as_bad (_("unknown directive")); | |
1179 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1180 | } | |
1181 | ||
1182 | ||
1183 | static void | |
7fa3d080 | 1184 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1185 | { |
1186 | directiveE directive; | |
1187 | bfd_boolean negated; | |
1188 | emit_state *state; | |
e0001a05 NC |
1189 | lit_state *ls; |
1190 | ||
1191 | get_directive (&directive, &negated); | |
1192 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1193 | { | |
1194 | discard_rest_of_line (); | |
1195 | return; | |
1196 | } | |
1197 | ||
43cd72b9 BW |
1198 | if (cur_vinsn.inside_bundle) |
1199 | as_bad (_("directives are not valid inside bundles")); | |
1200 | ||
e0001a05 NC |
1201 | switch (directive) |
1202 | { | |
1203 | case directive_literal: | |
82e7541d BW |
1204 | if (!inside_directive (directive_literal)) |
1205 | { | |
1206 | /* Previous labels go with whatever follows this directive, not with | |
1207 | the literal, so save them now. */ | |
1208 | saved_insn_labels = insn_labels; | |
1209 | insn_labels = NULL; | |
1210 | } | |
43cd72b9 | 1211 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1212 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1213 | xtensa_switch_to_literal_fragment (state); | |
1214 | directive_push (directive_literal, negated, state); | |
1215 | break; | |
1216 | ||
1217 | case directive_literal_prefix: | |
c138bc38 | 1218 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1219 | might produce a literal. */ |
1220 | md_flush_pending_output (); | |
e0001a05 NC |
1221 | /* Check to see if the current fragment is a literal |
1222 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1223 | if (generating_literals) |
e0001a05 NC |
1224 | { |
1225 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1226 | return; | |
1227 | } | |
1228 | ||
1229 | /* Allocate the literal state for this section and push | |
1230 | onto the directive stack. */ | |
1231 | ls = xmalloc (sizeof (lit_state)); | |
1232 | assert (ls); | |
1233 | ||
1234 | *ls = default_lit_sections; | |
e0001a05 NC |
1235 | directive_push (directive_literal_prefix, negated, ls); |
1236 | ||
e0001a05 | 1237 | /* Process the new prefix. */ |
74869ac7 | 1238 | xtensa_literal_prefix (); |
e0001a05 NC |
1239 | break; |
1240 | ||
1241 | case directive_freeregs: | |
1242 | /* This information is currently unused, but we'll accept the statement | |
1243 | and just discard the rest of the line. This won't check the syntax, | |
1244 | but it will accept every correct freeregs directive. */ | |
1245 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1246 | directive_push (directive_freeregs, negated, 0); | |
1247 | break; | |
1248 | ||
43cd72b9 BW |
1249 | case directive_schedule: |
1250 | md_flush_pending_output (); | |
1251 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1252 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1253 | directive_push (directive_schedule, negated, 0); | |
1254 | xtensa_set_frag_assembly_state (frag_now); | |
1255 | break; | |
1256 | ||
e0001a05 | 1257 | case directive_density: |
43cd72b9 BW |
1258 | as_warn (_(".begin [no-]density is ignored")); |
1259 | break; | |
1260 | ||
1261 | case directive_absolute_literals: | |
1262 | md_flush_pending_output (); | |
1263 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1264 | { |
43cd72b9 | 1265 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1266 | break; |
1267 | } | |
43cd72b9 BW |
1268 | xtensa_set_frag_assembly_state (frag_now); |
1269 | directive_push (directive, negated, 0); | |
1270 | break; | |
e0001a05 NC |
1271 | |
1272 | default: | |
43cd72b9 BW |
1273 | md_flush_pending_output (); |
1274 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1275 | directive_push (directive, negated, 0); |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | demand_empty_rest_of_line (); | |
1280 | } | |
1281 | ||
1282 | ||
1283 | static void | |
7fa3d080 | 1284 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1285 | { |
1286 | directiveE begin_directive, end_directive; | |
1287 | bfd_boolean begin_negated, end_negated; | |
1288 | const char *file; | |
1289 | unsigned int line; | |
1290 | emit_state *state; | |
43cd72b9 | 1291 | emit_state **state_ptr; |
e0001a05 NC |
1292 | lit_state *s; |
1293 | ||
43cd72b9 BW |
1294 | if (cur_vinsn.inside_bundle) |
1295 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1296 | |
e0001a05 | 1297 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1298 | |
1299 | md_flush_pending_output (); | |
1300 | ||
1301 | switch (end_directive) | |
e0001a05 | 1302 | { |
43cd72b9 | 1303 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1304 | discard_rest_of_line (); |
1305 | return; | |
e0001a05 | 1306 | |
43cd72b9 BW |
1307 | case directive_density: |
1308 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1309 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1310 | break; |
1311 | ||
1312 | case directive_absolute_literals: | |
1313 | if (!absolute_literals_supported && !end_negated) | |
1314 | { | |
1315 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1316 | demand_empty_rest_of_line (); | |
1317 | return; | |
1318 | } | |
1319 | break; | |
1320 | ||
1321 | default: | |
1322 | break; | |
e0001a05 NC |
1323 | } |
1324 | ||
43cd72b9 | 1325 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1326 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1327 | (const void **) state_ptr); |
e0001a05 NC |
1328 | |
1329 | if (begin_directive != directive_none) | |
1330 | { | |
1331 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1332 | { | |
1333 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1334 | begin_negated ? "no-" : "", | |
1335 | directive_info[begin_directive].name, file, line); | |
1336 | } | |
1337 | else | |
1338 | { | |
1339 | switch (end_directive) | |
1340 | { | |
1341 | case directive_literal: | |
1342 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1343 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1344 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1345 | free (state); |
82e7541d BW |
1346 | if (!inside_directive (directive_literal)) |
1347 | { | |
1348 | /* Restore the list of current labels. */ | |
1349 | xtensa_clear_insn_labels (); | |
1350 | insn_labels = saved_insn_labels; | |
1351 | } | |
e0001a05 NC |
1352 | break; |
1353 | ||
e0001a05 NC |
1354 | case directive_literal_prefix: |
1355 | /* Restore the default collection sections from saved state. */ | |
1356 | s = (lit_state *) state; | |
1357 | assert (s); | |
e8247da7 | 1358 | default_lit_sections = *s; |
e0001a05 | 1359 | |
74869ac7 BW |
1360 | /* Free the state storage. */ |
1361 | free (s->lit_prefix); | |
e0001a05 NC |
1362 | free (s); |
1363 | break; | |
1364 | ||
43cd72b9 BW |
1365 | case directive_schedule: |
1366 | case directive_freeregs: | |
1367 | break; | |
1368 | ||
e0001a05 | 1369 | default: |
43cd72b9 | 1370 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1371 | break; |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | demand_empty_rest_of_line (); | |
1377 | } | |
1378 | ||
1379 | ||
1380 | /* Place an aligned literal fragment at the current location. */ | |
1381 | ||
1382 | static void | |
7fa3d080 | 1383 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1384 | { |
43cd72b9 BW |
1385 | md_flush_pending_output (); |
1386 | ||
e0001a05 NC |
1387 | if (inside_directive (directive_literal)) |
1388 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1389 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1390 | |
1391 | demand_empty_rest_of_line (); | |
82e7541d | 1392 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1393 | } |
1394 | ||
1395 | ||
43cd72b9 | 1396 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1397 | |
1398 | static void | |
7fa3d080 | 1399 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1400 | { |
1401 | emit_state state; | |
1745fcba | 1402 | char *p, *base_name; |
e0001a05 | 1403 | char c; |
e0001a05 NC |
1404 | segT dest_seg; |
1405 | ||
82e7541d BW |
1406 | if (inside_directive (directive_literal)) |
1407 | { | |
1408 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1409 | ignore_rest_of_line (); | |
1410 | return; | |
1411 | } | |
1412 | ||
43cd72b9 BW |
1413 | md_flush_pending_output (); |
1414 | ||
82e7541d BW |
1415 | /* Previous labels go with whatever follows this directive, not with |
1416 | the literal, so save them now. */ | |
1417 | saved_insn_labels = insn_labels; | |
1418 | insn_labels = NULL; | |
1419 | ||
e0001a05 NC |
1420 | /* If we are using text-section literals, then this is the right value... */ |
1421 | dest_seg = now_seg; | |
1422 | ||
1423 | base_name = input_line_pointer; | |
1424 | ||
1425 | xtensa_switch_to_literal_fragment (&state); | |
1426 | ||
43cd72b9 | 1427 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1428 | need to put them in the section we just switched to. */ |
43cd72b9 | 1429 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1430 | dest_seg = now_seg; |
1431 | ||
43cd72b9 BW |
1432 | /* All literals are aligned to four-byte boundaries. */ |
1433 | frag_align (2, 0, 0); | |
1434 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1435 | |
1436 | c = get_symbol_end (); | |
1437 | /* Just after name is now '\0'. */ | |
1438 | p = input_line_pointer; | |
1439 | *p = c; | |
1440 | SKIP_WHITESPACE (); | |
1441 | ||
1442 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1443 | { | |
1444 | as_bad (_("expected comma or colon after symbol name; " | |
1445 | "rest of line ignored")); | |
1446 | ignore_rest_of_line (); | |
1447 | xtensa_restore_emit_state (&state); | |
1448 | return; | |
1449 | } | |
1450 | *p = 0; | |
1451 | ||
e0001a05 | 1452 | colon (base_name); |
e0001a05 | 1453 | |
e0001a05 | 1454 | *p = c; |
43cd72b9 | 1455 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1456 | |
43cd72b9 | 1457 | xtensa_elf_cons (4); |
e0001a05 NC |
1458 | |
1459 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1460 | |
1461 | /* Restore the list of current labels. */ | |
1462 | xtensa_clear_insn_labels (); | |
1463 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1464 | } |
1465 | ||
1466 | ||
1467 | static void | |
74869ac7 | 1468 | xtensa_literal_prefix (void) |
e0001a05 | 1469 | { |
74869ac7 BW |
1470 | char *name; |
1471 | int len; | |
1472 | ||
1473 | /* Parse the new prefix from the input_line_pointer. */ | |
1474 | SKIP_WHITESPACE (); | |
1475 | len = strspn (input_line_pointer, | |
1476 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1477 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1478 | |
1479 | /* Get a null-terminated copy of the name. */ | |
1480 | name = xmalloc (len + 1); | |
1481 | assert (name); | |
74869ac7 | 1482 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1483 | name[len] = 0; |
1484 | ||
74869ac7 BW |
1485 | /* Skip the name in the input line. */ |
1486 | input_line_pointer += len; | |
43cd72b9 | 1487 | |
74869ac7 | 1488 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1489 | |
74869ac7 | 1490 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1491 | default_lit_sections.lit_seg = NULL; |
1492 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1493 | } |
1494 | ||
1495 | ||
1496 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1497 | ||
1498 | static void | |
7fa3d080 | 1499 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1500 | { |
1501 | float fall_through_f, target_f; | |
43cd72b9 BW |
1502 | |
1503 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1504 | if (fall_through_f < 0) | |
1505 | { | |
1506 | as_bad (_("fall through frequency must be greater than 0")); | |
1507 | ignore_rest_of_line (); | |
1508 | return; | |
1509 | } | |
1510 | ||
1511 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1512 | if (target_f < 0) | |
1513 | { | |
1514 | as_bad (_("branch target frequency must be greater than 0")); | |
1515 | ignore_rest_of_line (); | |
1516 | return; | |
1517 | } | |
1518 | ||
b08b5071 | 1519 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1520 | |
1521 | demand_empty_rest_of_line (); | |
1522 | } | |
1523 | ||
1524 | ||
1525 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1526 | Clobbers input_line_pointer, checks end-of-line. */ | |
1527 | ||
1528 | static void | |
7fa3d080 | 1529 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1530 | { |
1531 | expressionS exp; | |
1532 | bfd_reloc_code_real_type reloc; | |
1533 | ||
1534 | md_flush_pending_output (); | |
1535 | ||
1536 | if (cur_vinsn.inside_bundle) | |
1537 | as_bad (_("directives are not valid inside bundles")); | |
1538 | ||
1539 | if (is_it_end_of_statement ()) | |
1540 | { | |
1541 | demand_empty_rest_of_line (); | |
1542 | return; | |
1543 | } | |
1544 | ||
1545 | do | |
1546 | { | |
1547 | expression (&exp); | |
1548 | if (exp.X_op == O_symbol | |
1549 | && *input_line_pointer == '@' | |
1550 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1551 | != BFD_RELOC_NONE)) | |
1552 | { | |
1553 | reloc_howto_type *reloc_howto = | |
1554 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1555 | ||
1556 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1557 | as_bad (_("unsupported relocation")); | |
1558 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1559 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1560 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1561 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1562 | as_bad (_("opcode-specific %s relocation used outside " | |
1563 | "an instruction"), reloc_howto->name); | |
1564 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1565 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1566 | reloc_howto->name, nbytes); | |
28dbbc02 BW |
1567 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1568 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1569 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1570 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1571 | else |
1572 | { | |
1573 | char *p = frag_more ((int) nbytes); | |
1574 | xtensa_set_frag_assembly_state (frag_now); | |
1575 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1576 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1577 | } |
1578 | } | |
1579 | else | |
1f7efbae BW |
1580 | { |
1581 | xtensa_set_frag_assembly_state (frag_now); | |
1582 | emit_expr (&exp, (unsigned int) nbytes); | |
1583 | } | |
43cd72b9 BW |
1584 | } |
1585 | while (*input_line_pointer++ == ','); | |
1586 | ||
1587 | input_line_pointer--; /* Put terminator back into stream. */ | |
1588 | demand_empty_rest_of_line (); | |
1589 | } | |
1590 | ||
fb227da0 BW |
1591 | static bfd_boolean is_leb128_expr; |
1592 | ||
1593 | static void | |
1594 | xtensa_leb128 (int sign) | |
1595 | { | |
1596 | is_leb128_expr = TRUE; | |
1597 | s_leb128 (sign); | |
1598 | is_leb128_expr = FALSE; | |
1599 | } | |
1600 | ||
7fa3d080 BW |
1601 | \f |
1602 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1603 | |
1604 | /* Parse @plt, etc. and return the desired relocation. */ | |
1605 | static bfd_reloc_code_real_type | |
7fa3d080 | 1606 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1607 | { |
43cd72b9 BW |
1608 | char ident[20]; |
1609 | char *str = *str_p; | |
1610 | char *str2; | |
1611 | int ch; | |
1612 | int len; | |
bbdd25a8 | 1613 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1614 | |
1615 | if (*str++ != '@') | |
1616 | return BFD_RELOC_NONE; | |
1617 | ||
1618 | for (ch = *str, str2 = ident; | |
1619 | (str2 < ident + sizeof (ident) - 1 | |
1620 | && (ISALNUM (ch) || ch == '@')); | |
1621 | ch = *++str) | |
1622 | { | |
1623 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1624 | } | |
1625 | ||
1626 | *str2 = '\0'; | |
1627 | len = str2 - ident; | |
1628 | ||
1629 | ch = ident[0]; | |
bbdd25a8 BW |
1630 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1631 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1632 | && len == ptr->length |
bbdd25a8 | 1633 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1634 | { |
1635 | /* Now check for "identifier@suffix+constant". */ | |
1636 | if (*str == '-' || *str == '+') | |
1637 | { | |
1638 | char *orig_line = input_line_pointer; | |
1639 | expressionS new_exp; | |
1640 | ||
1641 | input_line_pointer = str; | |
1642 | expression (&new_exp); | |
1643 | if (new_exp.X_op == O_constant) | |
1644 | { | |
1645 | exp_p->X_add_number += new_exp.X_add_number; | |
1646 | str = input_line_pointer; | |
1647 | } | |
1648 | ||
1649 | if (&input_line_pointer != str_p) | |
1650 | input_line_pointer = orig_line; | |
1651 | } | |
1652 | ||
1653 | *str_p = str; | |
1654 | return ptr->reloc; | |
1655 | } | |
1656 | ||
1657 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1658 | } |
1659 | ||
e0001a05 | 1660 | |
bbdd25a8 BW |
1661 | /* Find the matching operator type. */ |
1662 | static unsigned char | |
1663 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1664 | { | |
1665 | struct suffix_reloc_map *sfx; | |
1666 | unsigned char operator = (unsigned char) -1; | |
1667 | ||
1668 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1669 | { | |
1670 | if (sfx->reloc == reloc) | |
1671 | { | |
1672 | operator = sfx->operator; | |
1673 | break; | |
1674 | } | |
1675 | } | |
1676 | assert (operator != (unsigned char) -1); | |
1677 | return operator; | |
1678 | } | |
1679 | ||
1680 | ||
1681 | /* Find the matching reloc type. */ | |
1682 | static bfd_reloc_code_real_type | |
28dbbc02 | 1683 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 BW |
1684 | { |
1685 | struct suffix_reloc_map *sfx; | |
1686 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1687 | ||
1688 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1689 | { | |
1690 | if (sfx->operator == operator) | |
1691 | { | |
1692 | reloc = sfx->reloc; | |
1693 | break; | |
1694 | } | |
1695 | } | |
1696 | ||
28dbbc02 BW |
1697 | if (is_literal) |
1698 | { | |
1699 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1700 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1701 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1702 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1703 | } | |
1704 | ||
bbdd25a8 BW |
1705 | if (reloc == BFD_RELOC_UNUSED) |
1706 | return BFD_RELOC_32; | |
1707 | ||
1708 | return reloc; | |
1709 | } | |
1710 | ||
1711 | ||
e0001a05 | 1712 | static const char * |
7fa3d080 | 1713 | expression_end (const char *name) |
e0001a05 NC |
1714 | { |
1715 | while (1) | |
1716 | { | |
1717 | switch (*name) | |
1718 | { | |
43cd72b9 | 1719 | case '}': |
e0001a05 NC |
1720 | case ';': |
1721 | case '\0': | |
1722 | case ',': | |
43cd72b9 | 1723 | case ':': |
e0001a05 NC |
1724 | return name; |
1725 | case ' ': | |
1726 | case '\t': | |
1727 | ++name; | |
1728 | continue; | |
1729 | default: | |
1730 | return 0; | |
1731 | } | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | ||
1736 | #define ERROR_REG_NUM ((unsigned) -1) | |
1737 | ||
1738 | static unsigned | |
7fa3d080 | 1739 | tc_get_register (const char *prefix) |
e0001a05 NC |
1740 | { |
1741 | unsigned reg; | |
1742 | const char *next_expr; | |
1743 | const char *old_line_pointer; | |
1744 | ||
1745 | SKIP_WHITESPACE (); | |
1746 | old_line_pointer = input_line_pointer; | |
1747 | ||
1748 | if (*input_line_pointer == '$') | |
1749 | ++input_line_pointer; | |
1750 | ||
1751 | /* Accept "sp" as a synonym for "a1". */ | |
1752 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1753 | && expression_end (input_line_pointer + 2)) | |
1754 | { | |
1755 | input_line_pointer += 2; | |
1756 | return 1; /* AR[1] */ | |
1757 | } | |
1758 | ||
1759 | while (*input_line_pointer++ == *prefix++) | |
1760 | ; | |
1761 | --input_line_pointer; | |
1762 | --prefix; | |
1763 | ||
1764 | if (*prefix) | |
1765 | { | |
1766 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1767 | return ERROR_REG_NUM; | |
1768 | } | |
1769 | ||
1770 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1771 | { | |
1772 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1773 | return ERROR_REG_NUM; | |
1774 | } | |
1775 | ||
1776 | reg = 0; | |
1777 | ||
1778 | while (ISDIGIT ((int) *input_line_pointer)) | |
1779 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1780 | ||
1781 | if (!(next_expr = expression_end (input_line_pointer))) | |
1782 | { | |
1783 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1784 | return ERROR_REG_NUM; | |
1785 | } | |
1786 | ||
1787 | input_line_pointer = (char *) next_expr; | |
1788 | ||
1789 | return reg; | |
1790 | } | |
1791 | ||
1792 | ||
e0001a05 | 1793 | static void |
7fa3d080 | 1794 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1795 | { |
43cd72b9 | 1796 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1797 | |
43cd72b9 BW |
1798 | /* Check if this is an immediate operand. */ |
1799 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1800 | { |
43cd72b9 | 1801 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1802 | segT t = expression (tok); |
43cd72b9 BW |
1803 | if (t == absolute_section |
1804 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1805 | { |
1806 | assert (tok->X_op == O_constant); | |
1807 | tok->X_op = O_symbol; | |
1808 | tok->X_add_symbol = &abs_symbol; | |
1809 | } | |
43cd72b9 BW |
1810 | |
1811 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1812 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1813 | != BFD_RELOC_NONE)) | |
e0001a05 | 1814 | { |
1bbb5f21 | 1815 | switch (reloc) |
43cd72b9 | 1816 | { |
1bbb5f21 BW |
1817 | case BFD_RELOC_LO16: |
1818 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1819 | { |
43cd72b9 | 1820 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1821 | return; |
1bbb5f21 BW |
1822 | } |
1823 | break; | |
1824 | case BFD_RELOC_HI16: | |
1825 | if (tok->X_op == O_constant) | |
1826 | { | |
43cd72b9 | 1827 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1828 | return; |
bbdd25a8 | 1829 | } |
1bbb5f21 BW |
1830 | break; |
1831 | case BFD_RELOC_UNUSED: | |
1832 | as_bad (_("unsupported relocation")); | |
1833 | return; | |
1834 | case BFD_RELOC_32_PCREL: | |
1835 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1836 | return; | |
1837 | default: | |
1838 | break; | |
43cd72b9 | 1839 | } |
bbdd25a8 | 1840 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1841 | } |
e0001a05 NC |
1842 | } |
1843 | else | |
1844 | { | |
43cd72b9 BW |
1845 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1846 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1847 | |
1848 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1849 | { | |
1850 | uint32 buf = reg; | |
43cd72b9 | 1851 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1852 | as_bad (_("register number out of range")); |
1853 | } | |
1854 | ||
1855 | tok->X_op = O_register; | |
1856 | tok->X_add_symbol = 0; | |
1857 | tok->X_add_number = reg; | |
1858 | } | |
1859 | } | |
1860 | ||
1861 | ||
1862 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1863 | ||
1864 | static int | |
7fa3d080 | 1865 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1866 | { |
1867 | char *old_input_line_pointer; | |
1868 | bfd_boolean saw_comma = FALSE; | |
1869 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1870 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1871 | int num_args = 0; |
1872 | char *arg_end, *arg; | |
1873 | int arg_len; | |
43cd72b9 BW |
1874 | |
1875 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1876 | old_input_line_pointer = input_line_pointer; |
1877 | input_line_pointer = str; | |
1878 | ||
1879 | while (*input_line_pointer) | |
1880 | { | |
1881 | SKIP_WHITESPACE (); | |
1882 | switch (*input_line_pointer) | |
1883 | { | |
1884 | case '\0': | |
43cd72b9 | 1885 | case '}': |
e0001a05 NC |
1886 | goto fini; |
1887 | ||
43cd72b9 BW |
1888 | case ':': |
1889 | input_line_pointer++; | |
1890 | if (saw_comma || saw_colon || !saw_arg) | |
1891 | goto err; | |
1892 | saw_colon = TRUE; | |
1893 | break; | |
1894 | ||
e0001a05 NC |
1895 | case ',': |
1896 | input_line_pointer++; | |
43cd72b9 | 1897 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1898 | goto err; |
1899 | saw_comma = TRUE; | |
1900 | break; | |
1901 | ||
1902 | default: | |
43cd72b9 | 1903 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1904 | goto err; |
1905 | ||
1906 | arg_end = input_line_pointer + 1; | |
1907 | while (!expression_end (arg_end)) | |
1908 | arg_end += 1; | |
43cd72b9 | 1909 | |
e0001a05 | 1910 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1911 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1912 | args[num_args] = arg; |
1913 | ||
43cd72b9 BW |
1914 | if (saw_colon) |
1915 | *arg++ = ':'; | |
e0001a05 NC |
1916 | strncpy (arg, input_line_pointer, arg_len); |
1917 | arg[arg_len] = '\0'; | |
43cd72b9 | 1918 | |
e0001a05 NC |
1919 | input_line_pointer = arg_end; |
1920 | num_args += 1; | |
c138bc38 | 1921 | saw_comma = FALSE; |
43cd72b9 | 1922 | saw_colon = FALSE; |
c138bc38 | 1923 | saw_arg = TRUE; |
e0001a05 NC |
1924 | break; |
1925 | } | |
1926 | } | |
1927 | ||
1928 | fini: | |
43cd72b9 | 1929 | if (saw_comma || saw_colon) |
e0001a05 NC |
1930 | goto err; |
1931 | input_line_pointer = old_input_line_pointer; | |
1932 | return num_args; | |
1933 | ||
1934 | err: | |
43cd72b9 BW |
1935 | if (saw_comma) |
1936 | as_bad (_("extra comma")); | |
1937 | else if (saw_colon) | |
1938 | as_bad (_("extra colon")); | |
1939 | else if (!saw_arg) | |
c138bc38 | 1940 | as_bad (_("missing argument")); |
43cd72b9 BW |
1941 | else |
1942 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1943 | input_line_pointer = old_input_line_pointer; |
1944 | return -1; | |
1945 | } | |
1946 | ||
1947 | ||
43cd72b9 | 1948 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1949 | |
1950 | static bfd_boolean | |
7fa3d080 | 1951 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1952 | { |
43cd72b9 | 1953 | expressionS *tok, *last_tok; |
e0001a05 NC |
1954 | xtensa_opcode opcode = insn->opcode; |
1955 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1956 | xtensa_isa isa = xtensa_default_isa; |
1957 | int n, num_regs = 0; | |
e0001a05 | 1958 | int opcode_operand_count; |
43cd72b9 BW |
1959 | int opnd_cnt, last_opnd_cnt; |
1960 | unsigned int next_reg = 0; | |
e0001a05 NC |
1961 | char *old_input_line_pointer; |
1962 | ||
1963 | if (insn->insn_type == ITYPE_LITERAL) | |
1964 | opcode_operand_count = 1; | |
1965 | else | |
43cd72b9 | 1966 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1967 | |
43cd72b9 | 1968 | tok = insn->tok; |
e0001a05 NC |
1969 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1970 | ||
1971 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1972 | old_input_line_pointer = input_line_pointer; |
1973 | ||
1974 | last_tok = 0; | |
1975 | last_opnd_cnt = -1; | |
1976 | opnd_cnt = 0; | |
1977 | ||
1978 | /* Skip invisible operands. */ | |
1979 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1980 | { | |
1981 | opnd_cnt += 1; | |
1982 | tok++; | |
1983 | } | |
e0001a05 NC |
1984 | |
1985 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1986 | { |
e0001a05 | 1987 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1988 | if (*input_line_pointer == ':') |
1989 | { | |
1990 | xtensa_regfile opnd_rf; | |
1991 | input_line_pointer++; | |
1992 | if (num_regs == 0) | |
1993 | goto err; | |
1994 | assert (opnd_cnt > 0); | |
1995 | num_regs--; | |
1996 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1997 | if (next_reg | |
1998 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1999 | as_warn (_("incorrect register number, ignoring")); | |
2000 | next_reg++; | |
2001 | } | |
2002 | else | |
2003 | { | |
2004 | if (opnd_cnt >= opcode_operand_count) | |
2005 | { | |
2006 | as_warn (_("too many arguments")); | |
2007 | goto err; | |
2008 | } | |
2009 | assert (opnd_cnt < MAX_INSN_ARGS); | |
2010 | ||
2011 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2012 | next_reg = tok->X_add_number + 1; | |
2013 | ||
2014 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2015 | goto err; | |
2016 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2017 | { | |
2018 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2019 | /* minus 1 because we are seeing one right now */ | |
2020 | } | |
2021 | else | |
2022 | num_regs = 0; | |
e0001a05 | 2023 | |
43cd72b9 BW |
2024 | last_tok = tok; |
2025 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2026 | |
43cd72b9 BW |
2027 | do |
2028 | { | |
2029 | opnd_cnt += 1; | |
2030 | tok++; | |
2031 | } | |
2032 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2033 | } | |
2034 | } | |
e0001a05 | 2035 | |
43cd72b9 BW |
2036 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2037 | goto err; | |
e0001a05 NC |
2038 | |
2039 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2040 | had_error = FALSE; |
e0001a05 NC |
2041 | |
2042 | err: | |
43cd72b9 | 2043 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2044 | return had_error; |
2045 | } | |
2046 | ||
2047 | ||
43cd72b9 | 2048 | static int |
7fa3d080 | 2049 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2050 | { |
2051 | xtensa_isa isa = xtensa_default_isa; | |
2052 | static xtensa_insnbuf slotbuf = NULL; | |
2053 | xtensa_format fmt; | |
2054 | xtensa_opcode opc = insn->opcode; | |
2055 | int slot, opnd, fmt_found; | |
2056 | unsigned val; | |
2057 | ||
2058 | if (!slotbuf) | |
2059 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2060 | ||
2061 | /* Find format/slot where this can be encoded. */ | |
2062 | fmt_found = 0; | |
2063 | slot = 0; | |
2064 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2065 | { | |
2066 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2067 | { | |
2068 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2069 | { | |
2070 | fmt_found = 1; | |
2071 | break; | |
2072 | } | |
2073 | } | |
2074 | if (fmt_found) break; | |
2075 | } | |
2076 | ||
2077 | if (!fmt_found) | |
2078 | { | |
2079 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2080 | return -1; | |
2081 | } | |
2082 | ||
2083 | /* First encode all the visible operands | |
2084 | (to deal with shared field operands). */ | |
2085 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2086 | { | |
2087 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2088 | && (insn->tok[opnd].X_op == O_register | |
2089 | || insn->tok[opnd].X_op == O_constant)) | |
2090 | { | |
2091 | val = insn->tok[opnd].X_add_number; | |
2092 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2093 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2094 | } | |
2095 | } | |
2096 | ||
2097 | /* Then pull out the values for the invisible ones. */ | |
2098 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2099 | { | |
2100 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2101 | { | |
2102 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2103 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2104 | insn->tok[opnd].X_add_number = val; | |
2105 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2106 | insn->tok[opnd].X_op = O_register; | |
2107 | else | |
2108 | insn->tok[opnd].X_op = O_constant; | |
2109 | } | |
2110 | } | |
2111 | ||
2112 | return 0; | |
2113 | } | |
2114 | ||
2115 | ||
e0001a05 | 2116 | static void |
7fa3d080 | 2117 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2118 | { |
2119 | char *cnt_arg, *new_arg; | |
2120 | cnt_arg = *cnt_argp; | |
2121 | ||
2122 | /* replace the argument with "31-(argument)" */ | |
2123 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2124 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2125 | ||
2126 | free (cnt_arg); | |
2127 | *cnt_argp = new_arg; | |
2128 | } | |
2129 | ||
2130 | ||
2131 | /* If "arg" is a constant expression, return non-zero with the value | |
2132 | in *valp. */ | |
2133 | ||
2134 | static int | |
7fa3d080 | 2135 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2136 | { |
2137 | expressionS exp; | |
2138 | char *save_ptr = input_line_pointer; | |
2139 | ||
2140 | input_line_pointer = arg; | |
2141 | expression (&exp); | |
2142 | input_line_pointer = save_ptr; | |
2143 | ||
2144 | if (exp.X_op == O_constant) | |
2145 | { | |
2146 | *valp = exp.X_add_number; | |
2147 | return 1; | |
2148 | } | |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
2153 | ||
2154 | static void | |
7fa3d080 | 2155 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2156 | { |
2157 | free (*popname); | |
2158 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2159 | strcpy (*popname, newop); | |
2160 | } | |
2161 | ||
2162 | ||
2163 | static int | |
7fa3d080 BW |
2164 | xg_check_num_args (int *pnum_args, |
2165 | int expected_num, | |
2166 | char *opname, | |
2167 | char **arg_strings) | |
e0001a05 NC |
2168 | { |
2169 | int num_args = *pnum_args; | |
2170 | ||
43cd72b9 | 2171 | if (num_args < expected_num) |
e0001a05 NC |
2172 | { |
2173 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2174 | num_args, opname, expected_num); | |
2175 | return -1; | |
2176 | } | |
2177 | ||
2178 | if (num_args > expected_num) | |
2179 | { | |
2180 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2181 | num_args, opname, expected_num); | |
2182 | while (num_args-- > expected_num) | |
2183 | { | |
2184 | free (arg_strings[num_args]); | |
2185 | arg_strings[num_args] = 0; | |
2186 | } | |
2187 | *pnum_args = expected_num; | |
2188 | return -1; | |
2189 | } | |
2190 | ||
2191 | return 0; | |
2192 | } | |
2193 | ||
2194 | ||
43cd72b9 BW |
2195 | /* If the register is not specified as part of the opcode, |
2196 | then get it from the operand and move it to the opcode. */ | |
2197 | ||
e0001a05 | 2198 | static int |
7fa3d080 | 2199 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2200 | { |
43cd72b9 BW |
2201 | xtensa_isa isa = xtensa_default_isa; |
2202 | xtensa_sysreg sr; | |
e0001a05 | 2203 | char *opname, *new_opname; |
43cd72b9 BW |
2204 | const char *sr_name; |
2205 | int is_user, is_write; | |
e0001a05 NC |
2206 | |
2207 | opname = *popname; | |
2208 | if (*opname == '_') | |
80ca4e2c | 2209 | opname += 1; |
43cd72b9 BW |
2210 | is_user = (opname[1] == 'u'); |
2211 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2212 | |
43cd72b9 | 2213 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2214 | |
43cd72b9 BW |
2215 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2216 | return -1; | |
e0001a05 | 2217 | |
43cd72b9 BW |
2218 | /* Check if the argument is a symbolic register name. */ |
2219 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2220 | /* Handle WSR to "INTSET" as a special case. */ | |
2221 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2222 | && !strcasecmp (arg_strings[1], "intset")) | |
2223 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2224 | if (sr == XTENSA_UNDEFINED | |
2225 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2226 | { | |
2227 | /* Maybe it's a register number.... */ | |
2228 | offsetT val; | |
e0001a05 NC |
2229 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2230 | { | |
43cd72b9 BW |
2231 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2232 | arg_strings[1], opname); | |
e0001a05 NC |
2233 | return -1; |
2234 | } | |
43cd72b9 BW |
2235 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2236 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2237 | { |
43cd72b9 | 2238 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2239 | (long) val, opname); |
e0001a05 NC |
2240 | return -1; |
2241 | } | |
43cd72b9 | 2242 | } |
e0001a05 | 2243 | |
43cd72b9 BW |
2244 | /* Remove the last argument, which is now part of the opcode. */ |
2245 | free (arg_strings[1]); | |
2246 | arg_strings[1] = 0; | |
2247 | *pnum_args = 1; | |
2248 | ||
2249 | /* Translate the opcode. */ | |
2250 | sr_name = xtensa_sysreg_name (isa, sr); | |
2251 | /* Another special case for "WSR.INTSET".... */ | |
2252 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2253 | sr_name = "intset"; | |
2254 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2255 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2256 | free (*popname); |
2257 | *popname = new_opname; | |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | ||
2262 | ||
2263 | static int | |
7fa3d080 | 2264 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2265 | { |
2266 | xtensa_isa isa = xtensa_default_isa; | |
2267 | xtensa_sysreg sr; | |
2268 | char *opname, *new_opname; | |
2269 | const char *sr_name; | |
2270 | bfd_boolean has_underbar = FALSE; | |
2271 | ||
2272 | opname = *popname; | |
2273 | if (opname[0] == '_') | |
2274 | { | |
2275 | has_underbar = TRUE; | |
2276 | opname += 1; | |
2277 | } | |
2278 | ||
2279 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2280 | if (sr != XTENSA_UNDEFINED) | |
2281 | { | |
2282 | /* The new default name ("nnn") is different from the old default | |
2283 | name ("URnnn"). The old default is handled below, and we don't | |
2284 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2285 | default. */ | |
2286 | static char namebuf[10]; | |
2287 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2288 | if (strcmp (namebuf, opname + 1) == 0) | |
2289 | return 0; | |
2290 | } | |
2291 | else | |
2292 | { | |
2293 | offsetT val; | |
2294 | char *end; | |
2295 | ||
2296 | /* Only continue if the reg name is "URnnn". */ | |
2297 | if (opname[1] != 'u' || opname[2] != 'r') | |
2298 | return 0; | |
2299 | val = strtoul (opname + 3, &end, 10); | |
2300 | if (*end != '\0') | |
2301 | return 0; | |
2302 | ||
2303 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2304 | if (sr == XTENSA_UNDEFINED) | |
2305 | { | |
2306 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2307 | (long) val, opname); |
43cd72b9 BW |
2308 | return -1; |
2309 | } | |
2310 | } | |
2311 | ||
2312 | /* Translate the opcode. */ | |
2313 | sr_name = xtensa_sysreg_name (isa, sr); | |
2314 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2315 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2316 | opname[0], sr_name); | |
2317 | free (*popname); | |
2318 | *popname = new_opname; | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | ||
2324 | static int | |
7fa3d080 BW |
2325 | xtensa_translate_zero_immed (char *old_op, |
2326 | char *new_op, | |
2327 | char **popname, | |
2328 | int *pnum_args, | |
2329 | char **arg_strings) | |
43cd72b9 BW |
2330 | { |
2331 | char *opname; | |
2332 | offsetT val; | |
2333 | ||
2334 | opname = *popname; | |
2335 | assert (opname[0] != '_'); | |
2336 | ||
2337 | if (strcmp (opname, old_op) != 0) | |
2338 | return 0; | |
e0001a05 | 2339 | |
43cd72b9 BW |
2340 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2341 | return -1; | |
2342 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2343 | { | |
2344 | xg_replace_opname (popname, new_op); | |
2345 | free (arg_strings[1]); | |
2346 | arg_strings[1] = arg_strings[2]; | |
2347 | arg_strings[2] = 0; | |
2348 | *pnum_args = 2; | |
e0001a05 NC |
2349 | } |
2350 | ||
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | ||
2355 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2356 | Returns non-zero if an error was found. */ | |
2357 | ||
2358 | static int | |
7fa3d080 | 2359 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2360 | { |
2361 | char *opname = *popname; | |
2362 | bfd_boolean has_underbar = FALSE; | |
2363 | ||
2364 | if (*opname == '_') | |
2365 | { | |
2366 | has_underbar = TRUE; | |
2367 | opname += 1; | |
2368 | } | |
2369 | ||
2370 | if (strcmp (opname, "mov") == 0) | |
2371 | { | |
43cd72b9 | 2372 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2373 | xg_replace_opname (popname, "mov.n"); |
2374 | else | |
2375 | { | |
2376 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2377 | return -1; | |
2378 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2379 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2380 | strcpy (arg_strings[2], arg_strings[1]); | |
2381 | *pnum_args = 3; | |
2382 | } | |
2383 | return 0; | |
2384 | } | |
2385 | ||
2386 | if (strcmp (opname, "bbsi.l") == 0) | |
2387 | { | |
2388 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2389 | return -1; | |
2390 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2391 | if (target_big_endian) | |
2392 | xg_reverse_shift_count (&arg_strings[1]); | |
2393 | return 0; | |
2394 | } | |
2395 | ||
2396 | if (strcmp (opname, "bbci.l") == 0) | |
2397 | { | |
2398 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2399 | return -1; | |
2400 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2401 | if (target_big_endian) | |
2402 | xg_reverse_shift_count (&arg_strings[1]); | |
2403 | return 0; | |
2404 | } | |
2405 | ||
eb6d9dce BW |
2406 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2407 | are handled elsewhere. Real NOP instructions are always available | |
2408 | in configurations with FLIX, so this should never be an issue but | |
2409 | check for it anyway. */ | |
2410 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2411 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2412 | { |
43cd72b9 | 2413 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2414 | xg_replace_opname (popname, "nop.n"); |
2415 | else | |
2416 | { | |
2417 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2418 | return -1; | |
2419 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2420 | arg_strings[0] = (char *) xmalloc (3); | |
2421 | arg_strings[1] = (char *) xmalloc (3); | |
2422 | arg_strings[2] = (char *) xmalloc (3); | |
2423 | strcpy (arg_strings[0], "a1"); | |
2424 | strcpy (arg_strings[1], "a1"); | |
2425 | strcpy (arg_strings[2], "a1"); | |
2426 | *pnum_args = 3; | |
2427 | } | |
2428 | return 0; | |
2429 | } | |
2430 | ||
43cd72b9 BW |
2431 | /* Recognize [RW]UR and [RWX]SR. */ |
2432 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2433 | && (opname[1] == 'u' || opname[1] == 's')) | |
2434 | || (opname[0] == 'x' && opname[1] == 's')) | |
2435 | && opname[2] == 'r' | |
2436 | && opname[3] == '\0') | |
e0001a05 NC |
2437 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2438 | ||
43cd72b9 BW |
2439 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2440 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2441 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2442 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2443 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2444 | |
43cd72b9 BW |
2445 | /* Relax branches that don't allow comparisons against an immediate value |
2446 | of zero to the corresponding branches with implicit zero immediates. */ | |
2447 | if (!has_underbar && use_transform ()) | |
2448 | { | |
2449 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2450 | pnum_args, arg_strings)) | |
2451 | return -1; | |
e0001a05 | 2452 | |
43cd72b9 BW |
2453 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2454 | pnum_args, arg_strings)) | |
2455 | return -1; | |
e0001a05 | 2456 | |
43cd72b9 BW |
2457 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2458 | pnum_args, arg_strings)) | |
2459 | return -1; | |
e0001a05 | 2460 | |
43cd72b9 BW |
2461 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2462 | pnum_args, arg_strings)) | |
2463 | return -1; | |
2464 | } | |
e0001a05 | 2465 | |
43cd72b9 BW |
2466 | return 0; |
2467 | } | |
e0001a05 | 2468 | |
43cd72b9 BW |
2469 | \f |
2470 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2471 | |
43cd72b9 BW |
2472 | /* Currently the assembler only allows us to use a single target per |
2473 | fragment. Because of this, only one operand for a given | |
2474 | instruction may be symbolic. If there is a PC-relative operand, | |
2475 | the last one is chosen. Otherwise, the result is the number of the | |
2476 | last immediate operand, and if there are none of those, we fail and | |
2477 | return -1. */ | |
e0001a05 | 2478 | |
7fa3d080 BW |
2479 | static int |
2480 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2481 | { |
2482 | int last_immed = -1; | |
2483 | int noperands, opi; | |
e0001a05 | 2484 | |
43cd72b9 BW |
2485 | if (opcode == XTENSA_UNDEFINED) |
2486 | return -1; | |
e0001a05 | 2487 | |
43cd72b9 BW |
2488 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2489 | for (opi = noperands - 1; opi >= 0; opi--) | |
2490 | { | |
2491 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2492 | continue; | |
2493 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2494 | return opi; | |
2495 | if (last_immed == -1 | |
2496 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2497 | last_immed = opi; | |
e0001a05 | 2498 | } |
43cd72b9 | 2499 | return last_immed; |
e0001a05 NC |
2500 | } |
2501 | ||
e0001a05 | 2502 | |
43cd72b9 | 2503 | static xtensa_opcode |
7fa3d080 | 2504 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2505 | { |
43cd72b9 BW |
2506 | static xtensa_insnbuf insnbuf = NULL; |
2507 | static xtensa_insnbuf slotbuf = NULL; | |
2508 | xtensa_isa isa = xtensa_default_isa; | |
2509 | xtensa_format fmt; | |
2510 | ||
2511 | if (!insnbuf) | |
e0001a05 | 2512 | { |
43cd72b9 BW |
2513 | insnbuf = xtensa_insnbuf_alloc (isa); |
2514 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2515 | } |
e0001a05 | 2516 | |
d77b99c9 | 2517 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2518 | fmt = xtensa_format_decode (isa, insnbuf); |
2519 | if (fmt == XTENSA_UNDEFINED) | |
2520 | return XTENSA_UNDEFINED; | |
e0001a05 | 2521 | |
43cd72b9 BW |
2522 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2523 | return XTENSA_UNDEFINED; | |
e0001a05 | 2524 | |
43cd72b9 BW |
2525 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2526 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2527 | } |
2528 | ||
2529 | ||
43cd72b9 | 2530 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2531 | |
43cd72b9 | 2532 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2533 | |
7fa3d080 BW |
2534 | static void |
2535 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2536 | { |
2537 | int num_opcodes, num_operands; | |
2538 | xtensa_opcode opcode; | |
2539 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2540 | |
43cd72b9 BW |
2541 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2542 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2543 | { |
43cd72b9 BW |
2544 | int opn; |
2545 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2546 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2547 | for (opn = 0; opn < num_operands; opn++) | |
2548 | { | |
2549 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2550 | continue; | |
2551 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2552 | { | |
2553 | xtensa_regfile opnd_rf = | |
2554 | xtensa_operand_regfile (isa, opcode, opn); | |
2555 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2556 | } | |
2557 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2558 | fputs ("[lLr] ", stderr); | |
2559 | else | |
2560 | fputs ("i ", stderr); | |
2561 | } | |
2562 | fprintf (stderr, "\n"); | |
e0001a05 | 2563 | } |
e0001a05 NC |
2564 | } |
2565 | ||
2566 | ||
43cd72b9 | 2567 | static void |
7fa3d080 | 2568 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2569 | { |
e0001a05 | 2570 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2571 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2572 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2573 | int op; | |
e0001a05 | 2574 | |
43cd72b9 | 2575 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2576 | |
43cd72b9 BW |
2577 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2578 | { | |
2579 | xtensa_opcode opcode; | |
2580 | const char *opname; | |
2581 | int operands; | |
2582 | ||
2583 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2584 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2585 | opname = xtensa_opcode_name (isa, opcode); | |
2586 | ||
2587 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2588 | fprintf (stderr, " operands = "); | |
2589 | for (operands = 0; | |
2590 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2591 | operands++) | |
2592 | { | |
2593 | unsigned int val; | |
2594 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2595 | continue; | |
2596 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2597 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2598 | fprintf (stderr, "%d ", val); | |
2599 | } | |
2600 | fprintf (stderr, "\n"); | |
2601 | } | |
2602 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2603 | } |
2604 | ||
43cd72b9 BW |
2605 | #endif /* TENSILICA_DEBUG */ |
2606 | ||
e0001a05 NC |
2607 | |
2608 | static bfd_boolean | |
7fa3d080 | 2609 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2610 | { |
43cd72b9 BW |
2611 | xtensa_isa isa = xtensa_default_isa; |
2612 | int n, num_operands; | |
e0001a05 | 2613 | |
64b607e6 | 2614 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2615 | return FALSE; |
2616 | ||
43cd72b9 BW |
2617 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2618 | for (n = 0; n < num_operands; n++) | |
2619 | { | |
2620 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2621 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2622 | return TRUE; | |
2623 | } | |
2624 | return FALSE; | |
e0001a05 NC |
2625 | } |
2626 | ||
2627 | ||
43cd72b9 BW |
2628 | /* Convert from BFD relocation type code to slot and operand number. |
2629 | Returns non-zero on failure. */ | |
e0001a05 | 2630 | |
43cd72b9 | 2631 | static int |
7fa3d080 | 2632 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2633 | { |
43cd72b9 BW |
2634 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2635 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2636 | { |
43cd72b9 BW |
2637 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2638 | *is_alt = FALSE; | |
e0001a05 | 2639 | } |
43cd72b9 BW |
2640 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2641 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2642 | { |
43cd72b9 BW |
2643 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2644 | *is_alt = TRUE; | |
e0001a05 | 2645 | } |
43cd72b9 BW |
2646 | else |
2647 | return -1; | |
2648 | ||
2649 | return 0; | |
e0001a05 NC |
2650 | } |
2651 | ||
2652 | ||
43cd72b9 BW |
2653 | /* Convert from slot number to BFD relocation type code for the |
2654 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2655 | failure. */ | |
e0001a05 | 2656 | |
43cd72b9 | 2657 | static bfd_reloc_code_real_type |
7fa3d080 | 2658 | encode_reloc (int slot) |
e0001a05 | 2659 | { |
43cd72b9 BW |
2660 | if (slot < 0 || slot > 14) |
2661 | return BFD_RELOC_NONE; | |
2662 | ||
2663 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2664 | } |
2665 | ||
2666 | ||
43cd72b9 BW |
2667 | /* Convert from slot numbers to BFD relocation type code for the |
2668 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2669 | |
43cd72b9 | 2670 | static bfd_reloc_code_real_type |
7fa3d080 | 2671 | encode_alt_reloc (int slot) |
e0001a05 | 2672 | { |
43cd72b9 BW |
2673 | if (slot < 0 || slot > 14) |
2674 | return BFD_RELOC_NONE; | |
2675 | ||
2676 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2677 | } |
2678 | ||
2679 | ||
2680 | static void | |
7fa3d080 BW |
2681 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2682 | xtensa_format fmt, | |
2683 | int slot, | |
2684 | xtensa_opcode opcode, | |
2685 | int operand, | |
2686 | uint32 value, | |
2687 | const char *file, | |
2688 | unsigned int line) | |
e0001a05 | 2689 | { |
e0001a05 NC |
2690 | uint32 valbuf = value; |
2691 | ||
43cd72b9 | 2692 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2693 | { |
43cd72b9 BW |
2694 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2695 | == 1) | |
2696 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2697 | _("operand %d of '%s' has out of range value '%u'"), |
2698 | operand + 1, | |
2699 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2700 | value); | |
43cd72b9 BW |
2701 | else |
2702 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2703 | _("operand %d of '%s' has invalid value '%u'"), |
2704 | operand + 1, | |
2705 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2706 | value); | |
43cd72b9 | 2707 | return; |
e0001a05 NC |
2708 | } |
2709 | ||
43cd72b9 BW |
2710 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2711 | slotbuf, valbuf); | |
e0001a05 NC |
2712 | } |
2713 | ||
2714 | ||
2715 | static uint32 | |
7fa3d080 BW |
2716 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2717 | xtensa_format fmt, | |
2718 | int slot, | |
2719 | xtensa_opcode opcode, | |
2720 | int opnum) | |
e0001a05 | 2721 | { |
43cd72b9 BW |
2722 | uint32 val = 0; |
2723 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2724 | fmt, slot, slotbuf, &val); | |
2725 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2726 | return val; | |
e0001a05 NC |
2727 | } |
2728 | ||
e0001a05 | 2729 | \f |
7fa3d080 | 2730 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2731 | |
7fa3d080 BW |
2732 | /* The routine xg_instruction_matches_option_term must return TRUE |
2733 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2734 | terms is given interpretation by this function. */ |
e0001a05 | 2735 | |
7fa3d080 | 2736 | static bfd_boolean |
19e8f41a | 2737 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2738 | { |
7fa3d080 BW |
2739 | if (strcmp (option->option_name, "realnop") == 0 |
2740 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2741 | { | |
2742 | /* These conditions were evaluated statically when building the | |
2743 | relaxation table. There's no need to reevaluate them now. */ | |
2744 | return TRUE; | |
2745 | } | |
19e8f41a BW |
2746 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2747 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2748 | else |
2749 | { | |
2750 | as_fatal (_("internal error: unknown option name '%s'"), | |
2751 | option->option_name); | |
2752 | } | |
e0001a05 NC |
2753 | } |
2754 | ||
2755 | ||
7fa3d080 BW |
2756 | static bfd_boolean |
2757 | xg_instruction_matches_or_options (TInsn *insn, | |
2758 | const ReqOrOptionList *or_option) | |
e0001a05 | 2759 | { |
7fa3d080 BW |
2760 | const ReqOrOption *option; |
2761 | /* Must match each of the AND terms. */ | |
2762 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2763 | { |
7fa3d080 BW |
2764 | if (xg_instruction_matches_option_term (insn, option)) |
2765 | return TRUE; | |
e0001a05 | 2766 | } |
7fa3d080 | 2767 | return FALSE; |
e0001a05 NC |
2768 | } |
2769 | ||
2770 | ||
7fa3d080 BW |
2771 | static bfd_boolean |
2772 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2773 | { |
7fa3d080 BW |
2774 | const ReqOption *req_options; |
2775 | /* Must match each of the AND terms. */ | |
2776 | for (req_options = options; | |
2777 | req_options != NULL; | |
2778 | req_options = req_options->next) | |
e0001a05 | 2779 | { |
7fa3d080 BW |
2780 | /* Must match one of the OR clauses. */ |
2781 | if (!xg_instruction_matches_or_options (insn, | |
2782 | req_options->or_option_terms)) | |
2783 | return FALSE; | |
e0001a05 | 2784 | } |
7fa3d080 | 2785 | return TRUE; |
e0001a05 NC |
2786 | } |
2787 | ||
2788 | ||
7fa3d080 | 2789 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2790 | |
7fa3d080 BW |
2791 | static bfd_boolean |
2792 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2793 | { |
7fa3d080 | 2794 | PreconditionList *condition_l; |
e0001a05 | 2795 | |
7fa3d080 BW |
2796 | if (rule->opcode != insn->opcode) |
2797 | return FALSE; | |
e0001a05 | 2798 | |
7fa3d080 BW |
2799 | for (condition_l = rule->conditions; |
2800 | condition_l != NULL; | |
2801 | condition_l = condition_l->next) | |
e0001a05 | 2802 | { |
7fa3d080 BW |
2803 | expressionS *exp1; |
2804 | expressionS *exp2; | |
2805 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2806 | |
7fa3d080 | 2807 | switch (cond->typ) |
e0001a05 | 2808 | { |
7fa3d080 BW |
2809 | case OP_CONSTANT: |
2810 | /* The expression must be the constant. */ | |
2811 | assert (cond->op_num < insn->ntok); | |
2812 | exp1 = &insn->tok[cond->op_num]; | |
2813 | if (expr_is_const (exp1)) | |
2814 | { | |
2815 | switch (cond->cmp) | |
2816 | { | |
2817 | case OP_EQUAL: | |
2818 | if (get_expr_const (exp1) != cond->op_data) | |
2819 | return FALSE; | |
2820 | break; | |
2821 | case OP_NOTEQUAL: | |
2822 | if (get_expr_const (exp1) == cond->op_data) | |
2823 | return FALSE; | |
2824 | break; | |
2825 | default: | |
2826 | return FALSE; | |
2827 | } | |
2828 | } | |
2829 | else if (expr_is_register (exp1)) | |
2830 | { | |
2831 | switch (cond->cmp) | |
2832 | { | |
2833 | case OP_EQUAL: | |
2834 | if (get_expr_register (exp1) != cond->op_data) | |
2835 | return FALSE; | |
2836 | break; | |
2837 | case OP_NOTEQUAL: | |
2838 | if (get_expr_register (exp1) == cond->op_data) | |
2839 | return FALSE; | |
2840 | break; | |
2841 | default: | |
2842 | return FALSE; | |
2843 | } | |
2844 | } | |
2845 | else | |
2846 | return FALSE; | |
2847 | break; | |
2848 | ||
2849 | case OP_OPERAND: | |
2850 | assert (cond->op_num < insn->ntok); | |
2851 | assert (cond->op_data < insn->ntok); | |
2852 | exp1 = &insn->tok[cond->op_num]; | |
2853 | exp2 = &insn->tok[cond->op_data]; | |
2854 | ||
2855 | switch (cond->cmp) | |
2856 | { | |
2857 | case OP_EQUAL: | |
2858 | if (!expr_is_equal (exp1, exp2)) | |
2859 | return FALSE; | |
2860 | break; | |
2861 | case OP_NOTEQUAL: | |
2862 | if (expr_is_equal (exp1, exp2)) | |
2863 | return FALSE; | |
2864 | break; | |
2865 | } | |
2866 | break; | |
2867 | ||
2868 | case OP_LITERAL: | |
2869 | case OP_LABEL: | |
2870 | default: | |
2871 | return FALSE; | |
2872 | } | |
2873 | } | |
2874 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2875 | return FALSE; | |
2876 | ||
2877 | return TRUE; | |
2878 | } | |
2879 | ||
2880 | ||
2881 | static int | |
2882 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2883 | { | |
2884 | bfd_boolean a_greater = FALSE; | |
2885 | bfd_boolean b_greater = FALSE; | |
2886 | ||
2887 | ReqOptionList *l_a = a->options; | |
2888 | ReqOptionList *l_b = b->options; | |
2889 | ||
2890 | /* We only care if they both are the same except for | |
2891 | a const16 vs. an l32r. */ | |
2892 | ||
2893 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2894 | { | |
2895 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2896 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2897 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2898 | { | |
2899 | if (l_or_a->is_true != l_or_b->is_true) | |
2900 | return 0; | |
2901 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2902 | { | |
2903 | /* This is the case we care about. */ | |
2904 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2905 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2906 | { | |
2907 | if (prefer_const16) | |
2908 | a_greater = TRUE; | |
2909 | else | |
2910 | b_greater = TRUE; | |
2911 | } | |
2912 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2913 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2914 | { | |
2915 | if (prefer_const16) | |
2916 | b_greater = TRUE; | |
2917 | else | |
2918 | a_greater = TRUE; | |
2919 | } | |
2920 | else | |
2921 | return 0; | |
2922 | } | |
2923 | l_or_a = l_or_a->next; | |
2924 | l_or_b = l_or_b->next; | |
2925 | } | |
2926 | if (l_or_a || l_or_b) | |
2927 | return 0; | |
2928 | ||
2929 | l_a = l_a->next; | |
2930 | l_b = l_b->next; | |
2931 | } | |
2932 | if (l_a || l_b) | |
2933 | return 0; | |
2934 | ||
2935 | /* Incomparable if the substitution was used differently in two cases. */ | |
2936 | if (a_greater && b_greater) | |
2937 | return 0; | |
2938 | ||
2939 | if (b_greater) | |
2940 | return 1; | |
2941 | if (a_greater) | |
2942 | return -1; | |
2943 | ||
2944 | return 0; | |
2945 | } | |
2946 | ||
2947 | ||
2948 | static TransitionRule * | |
2949 | xg_instruction_match (TInsn *insn) | |
2950 | { | |
2951 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2952 | TransitionList *l; | |
2953 | assert (insn->opcode < table->num_opcodes); | |
2954 | ||
2955 | /* Walk through all of the possible transitions. */ | |
2956 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2957 | { | |
2958 | TransitionRule *rule = l->rule; | |
2959 | if (xg_instruction_matches_rule (insn, rule)) | |
2960 | return rule; | |
2961 | } | |
2962 | return NULL; | |
2963 | } | |
2964 | ||
2965 | \f | |
2966 | /* Various Other Internal Functions. */ | |
2967 | ||
2968 | static bfd_boolean | |
2969 | is_unique_insn_expansion (TransitionRule *r) | |
2970 | { | |
2971 | if (!r->to_instr || r->to_instr->next != NULL) | |
2972 | return FALSE; | |
2973 | if (r->to_instr->typ != INSTR_INSTR) | |
2974 | return FALSE; | |
2975 | return TRUE; | |
2976 | } | |
2977 | ||
2978 | ||
84b08ed9 BW |
2979 | /* Check if there is exactly one relaxation for INSN that converts it to |
2980 | another instruction of equal or larger size. If so, and if TARG is | |
2981 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2982 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2983 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2984 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2985 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2986 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2987 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2988 | |
84b08ed9 BW |
2989 | bfd_boolean |
2990 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2991 | { |
2992 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2993 | TransitionList *l; | |
84b08ed9 | 2994 | TransitionRule *match = 0; |
7fa3d080 | 2995 | |
7fa3d080 BW |
2996 | assert (insn->insn_type == ITYPE_INSN); |
2997 | assert (insn->opcode < table->num_opcodes); | |
2998 | ||
2999 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3000 | { | |
3001 | TransitionRule *rule = l->rule; | |
3002 | ||
3003 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3004 | && is_unique_insn_expansion (rule) |
3005 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3006 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3007 | { |
84b08ed9 BW |
3008 | if (match) |
3009 | return FALSE; | |
3010 | match = rule; | |
7fa3d080 BW |
3011 | } |
3012 | } | |
84b08ed9 BW |
3013 | if (!match) |
3014 | return FALSE; | |
3015 | ||
3016 | if (targ) | |
3017 | xg_build_to_insn (targ, insn, match->to_instr); | |
3018 | return TRUE; | |
7fa3d080 BW |
3019 | } |
3020 | ||
3021 | ||
3022 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3023 | ||
3024 | static int | |
3025 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3026 | { | |
3027 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3028 | TransitionList *l; | |
3029 | int max_size = xg_get_single_size (opcode); | |
3030 | ||
3031 | assert (opcode < table->num_opcodes); | |
3032 | ||
3033 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3034 | { | |
3035 | TransitionRule *rule = l->rule; | |
3036 | BuildInstr *build_list; | |
3037 | int this_size = 0; | |
3038 | ||
3039 | if (!rule) | |
3040 | continue; | |
3041 | build_list = rule->to_instr; | |
3042 | if (is_unique_insn_expansion (rule)) | |
3043 | { | |
3044 | assert (build_list->typ == INSTR_INSTR); | |
3045 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3046 | } | |
3047 | else | |
3048 | for (; build_list != NULL; build_list = build_list->next) | |
3049 | { | |
3050 | switch (build_list->typ) | |
3051 | { | |
3052 | case INSTR_INSTR: | |
3053 | this_size += xg_get_single_size (build_list->opcode); | |
3054 | break; | |
3055 | case INSTR_LITERAL_DEF: | |
3056 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3057 | default: |
3058 | break; | |
3059 | } | |
3060 | } | |
3061 | if (this_size > max_size) | |
3062 | max_size = this_size; | |
3063 | } | |
3064 | return max_size; | |
3065 | } | |
3066 | ||
3067 | ||
3068 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3069 | ||
7fa3d080 BW |
3070 | static int |
3071 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3072 | { |
43cd72b9 | 3073 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3074 | TransitionList *l; |
3075 | int max_size = 0; | |
3076 | ||
3077 | assert (opcode < table->num_opcodes); | |
3078 | ||
3079 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3080 | { | |
3081 | TransitionRule *rule = l->rule; | |
3082 | BuildInstr *build_list; | |
3083 | int this_size = 0; | |
3084 | ||
3085 | if (!rule) | |
3086 | continue; | |
3087 | build_list = rule->to_instr; | |
3088 | if (is_unique_insn_expansion (rule)) | |
3089 | { | |
3090 | assert (build_list->typ == INSTR_INSTR); | |
3091 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3092 | } | |
3093 | else | |
3094 | for (; build_list != NULL; build_list = build_list->next) | |
3095 | { | |
3096 | switch (build_list->typ) | |
3097 | { | |
3098 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3099 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3100 | this_size += 4; |
3101 | break; | |
3102 | case INSTR_INSTR: | |
3103 | case INSTR_LABEL_DEF: | |
3104 | default: | |
3105 | break; | |
3106 | } | |
3107 | } | |
3108 | if (this_size > max_size) | |
3109 | max_size = this_size; | |
3110 | } | |
3111 | return max_size; | |
3112 | } | |
3113 | ||
3114 | ||
7fa3d080 BW |
3115 | static bfd_boolean |
3116 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3117 | { | |
3118 | int steps_taken = 0; | |
3119 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3120 | TransitionList *l; | |
3121 | ||
3122 | assert (insn->insn_type == ITYPE_INSN); | |
3123 | assert (insn->opcode < table->num_opcodes); | |
3124 | ||
3125 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3126 | { | |
3127 | TransitionRule *rule = l->rule; | |
3128 | ||
3129 | if (xg_instruction_matches_rule (insn, rule)) | |
3130 | { | |
3131 | if (steps_taken == lateral_steps) | |
3132 | return TRUE; | |
3133 | steps_taken++; | |
3134 | } | |
3135 | } | |
3136 | return FALSE; | |
3137 | } | |
3138 | ||
3139 | ||
3140 | static symbolS * | |
3141 | get_special_literal_symbol (void) | |
3142 | { | |
3143 | static symbolS *sym = NULL; | |
3144 | ||
3145 | if (sym == NULL) | |
3146 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3147 | return sym; | |
3148 | } | |
3149 | ||
3150 | ||
3151 | static symbolS * | |
3152 | get_special_label_symbol (void) | |
3153 | { | |
3154 | static symbolS *sym = NULL; | |
3155 | ||
3156 | if (sym == NULL) | |
3157 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3158 | return sym; | |
3159 | } | |
3160 | ||
3161 | ||
3162 | static bfd_boolean | |
3163 | xg_valid_literal_expression (const expressionS *exp) | |
3164 | { | |
3165 | switch (exp->X_op) | |
3166 | { | |
3167 | case O_constant: | |
3168 | case O_symbol: | |
3169 | case O_big: | |
3170 | case O_uminus: | |
3171 | case O_subtract: | |
3172 | case O_pltrel: | |
1bbb5f21 | 3173 | case O_pcrel: |
28dbbc02 BW |
3174 | case O_tlsfunc: |
3175 | case O_tlsarg: | |
3176 | case O_tpoff: | |
3177 | case O_dtpoff: | |
7fa3d080 BW |
3178 | return TRUE; |
3179 | default: | |
3180 | return FALSE; | |
3181 | } | |
3182 | } | |
3183 | ||
3184 | ||
3185 | /* This will check to see if the value can be converted into the | |
3186 | operand type. It will return TRUE if it does not fit. */ | |
3187 | ||
3188 | static bfd_boolean | |
3189 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3190 | { | |
3191 | uint32 valbuf = value; | |
3192 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3193 | return TRUE; | |
3194 | return FALSE; | |
3195 | } | |
3196 | ||
3197 | ||
3198 | /* Assumes: All immeds are constants. Check that all constants fit | |
3199 | into their immeds; return FALSE if not. */ | |
3200 | ||
3201 | static bfd_boolean | |
3202 | xg_immeds_fit (const TInsn *insn) | |
3203 | { | |
3204 | xtensa_isa isa = xtensa_default_isa; | |
3205 | int i; | |
3206 | ||
3207 | int n = insn->ntok; | |
3208 | assert (insn->insn_type == ITYPE_INSN); | |
3209 | for (i = 0; i < n; ++i) | |
3210 | { | |
3211 | const expressionS *expr = &insn->tok[i]; | |
3212 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3213 | continue; | |
3214 | ||
3215 | switch (expr->X_op) | |
3216 | { | |
3217 | case O_register: | |
3218 | case O_constant: | |
3219 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3220 | return FALSE; | |
3221 | break; | |
3222 | ||
3223 | default: | |
3224 | /* The symbol should have a fixup associated with it. */ | |
3225 | assert (FALSE); | |
3226 | break; | |
3227 | } | |
3228 | } | |
3229 | return TRUE; | |
3230 | } | |
3231 | ||
3232 | ||
3233 | /* This should only be called after we have an initial | |
3234 | estimate of the addresses. */ | |
3235 | ||
3236 | static bfd_boolean | |
3237 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3238 | segT pc_seg, | |
3239 | fragS *pc_frag, | |
3240 | offsetT pc_offset, | |
3241 | long stretch) | |
e0001a05 | 3242 | { |
7fa3d080 BW |
3243 | xtensa_isa isa = xtensa_default_isa; |
3244 | symbolS *symbolP; | |
3245 | fragS *sym_frag; | |
3246 | offsetT target, pc; | |
3247 | uint32 new_offset; | |
3248 | int i; | |
3249 | int n = insn->ntok; | |
e0001a05 NC |
3250 | |
3251 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3252 | |
7fa3d080 | 3253 | for (i = 0; i < n; ++i) |
e0001a05 | 3254 | { |
7fa3d080 BW |
3255 | const expressionS *expr = &insn->tok[i]; |
3256 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3257 | continue; | |
e0001a05 | 3258 | |
7fa3d080 | 3259 | switch (expr->X_op) |
e0001a05 | 3260 | { |
7fa3d080 BW |
3261 | case O_register: |
3262 | case O_constant: | |
3263 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3264 | return FALSE; | |
3265 | break; | |
e0001a05 | 3266 | |
7fa3d080 BW |
3267 | case O_lo16: |
3268 | case O_hi16: | |
3269 | /* Check for the worst case. */ | |
3270 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3271 | return FALSE; | |
3272 | break; | |
e0001a05 | 3273 | |
7fa3d080 | 3274 | case O_symbol: |
7c834684 | 3275 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3276 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3277 | if (pc_frag == 0 |
3278 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3279 | return FALSE; |
e0001a05 | 3280 | |
8e6bc631 BW |
3281 | /* If it is a weak symbol or a symbol in a different section, |
3282 | it cannot be known to fit at assembly time. */ | |
3283 | if (S_IS_WEAK (expr->X_add_symbol) | |
3284 | || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7c834684 | 3285 | { |
8e6bc631 | 3286 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3287 | assume it will be in range. If the symbol is weak and |
3288 | undefined, it may remain undefined at link-time, in which | |
3289 | case it will have a zero value and almost certainly be out | |
3290 | of range for a direct call; thus, relax for undefined weak | |
3291 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3292 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f BW |
3293 | && ! pc_frag->tc_frag_data.use_longcalls |
3294 | && (! S_IS_WEAK (expr->X_add_symbol) | |
3295 | || S_IS_DEFINED (expr->X_add_symbol))) | |
7c834684 | 3296 | return TRUE; |
7c834684 | 3297 | |
8e6bc631 BW |
3298 | return FALSE; |
3299 | } | |
e0001a05 | 3300 | |
7fa3d080 BW |
3301 | symbolP = expr->X_add_symbol; |
3302 | sym_frag = symbol_get_frag (symbolP); | |
3303 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3304 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3305 | |
7fa3d080 BW |
3306 | /* If frag has yet to be reached on this pass, assume it |
3307 | will move by STRETCH just as we did. If this is not so, | |
3308 | it will be because some frag between grows, and that will | |
3309 | force another pass. Beware zero-length frags. There | |
3310 | should be a faster way to do this. */ | |
3311 | ||
3312 | if (stretch != 0 | |
3313 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3314 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3315 | { | |
3316 | target += stretch; | |
3317 | } | |
c138bc38 | 3318 | |
7fa3d080 BW |
3319 | new_offset = target; |
3320 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3321 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3322 | return FALSE; | |
3323 | break; | |
3324 | ||
3325 | default: | |
3326 | /* The symbol should have a fixup associated with it. */ | |
3327 | return FALSE; | |
3328 | } | |
3329 | } | |
3330 | ||
3331 | return TRUE; | |
e0001a05 NC |
3332 | } |
3333 | ||
3334 | ||
43cd72b9 | 3335 | /* Return TRUE on success. */ |
e0001a05 | 3336 | |
7fa3d080 BW |
3337 | static bfd_boolean |
3338 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3339 | { |
3340 | BuildOp *op; | |
3341 | symbolS *sym; | |
3342 | ||
60242db2 | 3343 | tinsn_init (targ); |
b224e962 BW |
3344 | targ->debug_line = insn->debug_line; |
3345 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3346 | switch (bi->typ) |
3347 | { | |
3348 | case INSTR_INSTR: | |
3349 | op = bi->ops; | |
3350 | targ->opcode = bi->opcode; | |
3351 | targ->insn_type = ITYPE_INSN; | |
3352 | targ->is_specific_opcode = FALSE; | |
3353 | ||
3354 | for (; op != NULL; op = op->next) | |
3355 | { | |
3356 | int op_num = op->op_num; | |
3357 | int op_data = op->op_data; | |
3358 | ||
3359 | assert (op->op_num < MAX_INSN_ARGS); | |
3360 | ||
3361 | if (targ->ntok <= op_num) | |
3362 | targ->ntok = op_num + 1; | |
3363 | ||
3364 | switch (op->typ) | |
3365 | { | |
3366 | case OP_CONSTANT: | |
3367 | set_expr_const (&targ->tok[op_num], op_data); | |
3368 | break; | |
3369 | case OP_OPERAND: | |
3370 | assert (op_data < insn->ntok); | |
3371 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3372 | break; | |
19e8f41a BW |
3373 | case OP_FREEREG: |
3374 | if (insn->extra_arg.X_op != O_register) | |
3375 | return FALSE; | |
3376 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3377 | break; | |
e0001a05 NC |
3378 | case OP_LITERAL: |
3379 | sym = get_special_literal_symbol (); | |
3380 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3381 | if (insn->tok[op_data].X_op == O_tlsfunc |
3382 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3383 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3384 | break; |
3385 | case OP_LABEL: | |
3386 | sym = get_special_label_symbol (); | |
3387 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3388 | break; | |
43cd72b9 BW |
3389 | case OP_OPERAND_HI16U: |
3390 | case OP_OPERAND_LOW16U: | |
3391 | assert (op_data < insn->ntok); | |
3392 | if (expr_is_const (&insn->tok[op_data])) | |
3393 | { | |
3394 | long val; | |
3395 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3396 | val = xg_apply_userdef_op_fn (op->typ, | |
3397 | targ->tok[op_num]. | |
3398 | X_add_number); | |
3399 | targ->tok[op_num].X_add_number = val; | |
3400 | } | |
3401 | else | |
3402 | { | |
3403 | /* For const16 we can create relocations for these. */ | |
3404 | if (targ->opcode == XTENSA_UNDEFINED | |
3405 | || (targ->opcode != xtensa_const16_opcode)) | |
3406 | return FALSE; | |
3407 | assert (op_data < insn->ntok); | |
3408 | /* Need to build a O_lo16 or O_hi16. */ | |
3409 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3410 | if (targ->tok[op_num].X_op == O_symbol) | |
3411 | { | |
3412 | if (op->typ == OP_OPERAND_HI16U) | |
3413 | targ->tok[op_num].X_op = O_hi16; | |
3414 | else if (op->typ == OP_OPERAND_LOW16U) | |
3415 | targ->tok[op_num].X_op = O_lo16; | |
3416 | else | |
3417 | return FALSE; | |
3418 | } | |
3419 | } | |
3420 | break; | |
e0001a05 NC |
3421 | default: |
3422 | /* currently handles: | |
3423 | OP_OPERAND_LOW8 | |
3424 | OP_OPERAND_HI24S | |
3425 | OP_OPERAND_F32MINUS */ | |
3426 | if (xg_has_userdef_op_fn (op->typ)) | |
3427 | { | |
3428 | assert (op_data < insn->ntok); | |
3429 | if (expr_is_const (&insn->tok[op_data])) | |
3430 | { | |
3431 | long val; | |
3432 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3433 | val = xg_apply_userdef_op_fn (op->typ, | |
3434 | targ->tok[op_num]. | |
3435 | X_add_number); | |
3436 | targ->tok[op_num].X_add_number = val; | |
3437 | } | |
3438 | else | |
3439 | return FALSE; /* We cannot use a relocation for this. */ | |
3440 | break; | |
3441 | } | |
3442 | assert (0); | |
3443 | break; | |
3444 | } | |
3445 | } | |
3446 | break; | |
3447 | ||
3448 | case INSTR_LITERAL_DEF: | |
3449 | op = bi->ops; | |
3450 | targ->opcode = XTENSA_UNDEFINED; | |
3451 | targ->insn_type = ITYPE_LITERAL; | |
3452 | targ->is_specific_opcode = FALSE; | |
3453 | for (; op != NULL; op = op->next) | |
3454 | { | |
3455 | int op_num = op->op_num; | |
3456 | int op_data = op->op_data; | |
3457 | assert (op->op_num < MAX_INSN_ARGS); | |
3458 | ||
3459 | if (targ->ntok <= op_num) | |
3460 | targ->ntok = op_num + 1; | |
3461 | ||
3462 | switch (op->typ) | |
3463 | { | |
3464 | case OP_OPERAND: | |
3465 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3466 | /* We can only pass resolvable literals through. */ |
3467 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3468 | return FALSE; | |
e0001a05 NC |
3469 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3470 | break; | |
3471 | case OP_LITERAL: | |
3472 | case OP_CONSTANT: | |
3473 | case OP_LABEL: | |
3474 | default: | |
3475 | assert (0); | |
3476 | break; | |
3477 | } | |
3478 | } | |
3479 | break; | |
3480 | ||
3481 | case INSTR_LABEL_DEF: | |
3482 | op = bi->ops; | |
3483 | targ->opcode = XTENSA_UNDEFINED; | |
3484 | targ->insn_type = ITYPE_LABEL; | |
3485 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3486 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3487 | assert (op == NULL); |
3488 | break; | |
3489 | ||
3490 | default: | |
3491 | assert (0); | |
3492 | } | |
3493 | ||
3494 | return TRUE; | |
3495 | } | |
3496 | ||
3497 | ||
43cd72b9 | 3498 | /* Return TRUE on success. */ |
e0001a05 | 3499 | |
7fa3d080 BW |
3500 | static bfd_boolean |
3501 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3502 | { |
3503 | for (; bi != NULL; bi = bi->next) | |
3504 | { | |
3505 | TInsn *next_insn = istack_push_space (istack); | |
3506 | ||
3507 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3508 | return FALSE; | |
3509 | } | |
3510 | return TRUE; | |
3511 | } | |
3512 | ||
3513 | ||
43cd72b9 | 3514 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3515 | |
7fa3d080 BW |
3516 | static bfd_boolean |
3517 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3518 | { |
3519 | int stack_size = istack->ninsn; | |
3520 | int steps_taken = 0; | |
43cd72b9 | 3521 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3522 | TransitionList *l; |
3523 | ||
3524 | assert (insn->insn_type == ITYPE_INSN); | |
3525 | assert (insn->opcode < table->num_opcodes); | |
3526 | ||
3527 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3528 | { | |
3529 | TransitionRule *rule = l->rule; | |
3530 | ||
3531 | if (xg_instruction_matches_rule (insn, rule)) | |
3532 | { | |
3533 | if (lateral_steps == steps_taken) | |
3534 | { | |
3535 | int i; | |
3536 | ||
3537 | /* This is it. Expand the rule to the stack. */ | |
3538 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3539 | return FALSE; | |
3540 | ||
3541 | /* Check to see if it fits. */ | |
3542 | for (i = stack_size; i < istack->ninsn; i++) | |
3543 | { | |
3544 | TInsn *insn = &istack->insn[i]; | |
3545 | ||
3546 | if (insn->insn_type == ITYPE_INSN | |
3547 | && !tinsn_has_symbolic_operands (insn) | |
3548 | && !xg_immeds_fit (insn)) | |
3549 | { | |
3550 | istack->ninsn = stack_size; | |
3551 | return FALSE; | |
3552 | } | |
3553 | } | |
3554 | return TRUE; | |
3555 | } | |
3556 | steps_taken++; | |
3557 | } | |
3558 | } | |
3559 | return FALSE; | |
3560 | } | |
3561 | ||
43cd72b9 | 3562 | \f |
43cd72b9 | 3563 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3564 | Return the number of steps taken. |
3565 | ||
3566 | For relaxation to correctly terminate, every relaxation chain must | |
3567 | terminate in one of two ways: | |
3568 | ||
3569 | 1. If the chain from one instruction to the next consists entirely of | |
3570 | single instructions, then the chain *must* handle all possible | |
3571 | immediates without failing. It must not ever fail because an | |
3572 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3573 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3574 | immediate larger than 32 bits, so it satisfies this condition. | |
3575 | Single instruction relaxation chains are as defined by | |
3576 | xg_is_single_relaxable_instruction. | |
3577 | ||
3578 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3579 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3580 | ||
3581 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3582 | -- in particular when the last two instructions have the same single | |
3583 | size. But nevertheless, you should guarantee the above two conditions. | |
3584 | ||
3585 | We could fix this so that single-instruction expansions correctly | |
3586 | terminate when they can't handle the range, but the error messages are | |
3587 | worse, and it actually turns out that in every case but one (18-bit wide | |
3588 | branches), you need a multi-instruction expansion to get the full range | |
3589 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3590 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3591 | |
7fa3d080 BW |
3592 | static int |
3593 | xg_assembly_relax (IStack *istack, | |
3594 | TInsn *insn, | |
3595 | segT pc_seg, | |
3596 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3597 | offsetT pc_offset, /* offset in fragment */ | |
3598 | int min_steps, /* minimum conversion steps */ | |
3599 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3600 | { |
3601 | int steps_taken = 0; | |
3602 | ||
b81bf389 BW |
3603 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3604 | This may go through a couple of stages of single instruction | |
3605 | transformations before we get there. */ | |
e0001a05 NC |
3606 | |
3607 | TInsn single_target; | |
3608 | TInsn current_insn; | |
3609 | int lateral_steps = 0; | |
3610 | int istack_size = istack->ninsn; | |
3611 | ||
3612 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3613 | && steps_taken >= min_steps) | |
3614 | { | |
3615 | istack_push (istack, insn); | |
3616 | return steps_taken; | |
3617 | } | |
43cd72b9 | 3618 | current_insn = *insn; |
e0001a05 | 3619 | |
7c834684 | 3620 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3621 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3622 | { |
21af2bbd | 3623 | steps_taken++; |
e0001a05 NC |
3624 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3625 | stretch)) | |
3626 | { | |
e0001a05 NC |
3627 | if (steps_taken >= min_steps) |
3628 | { | |
3629 | istack_push (istack, &single_target); | |
3630 | return steps_taken; | |
3631 | } | |
3632 | } | |
43cd72b9 | 3633 | current_insn = single_target; |
e0001a05 NC |
3634 | } |
3635 | ||
3636 | /* Now check for a multi-instruction expansion. */ | |
3637 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3638 | { | |
3639 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3640 | stretch)) | |
3641 | { | |
3642 | if (steps_taken >= min_steps) | |
3643 | { | |
3644 | istack_push (istack, ¤t_insn); | |
3645 | return steps_taken; | |
3646 | } | |
3647 | } | |
3648 | steps_taken++; | |
3649 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3650 | { | |
3651 | if (steps_taken >= min_steps) | |
3652 | return steps_taken; | |
3653 | } | |
3654 | lateral_steps++; | |
3655 | istack->ninsn = istack_size; | |
3656 | } | |
3657 | ||
3658 | /* It's not going to work -- use the original. */ | |
3659 | istack_push (istack, insn); | |
3660 | return steps_taken; | |
3661 | } | |
3662 | ||
3663 | ||
7fa3d080 BW |
3664 | static void |
3665 | xg_finish_frag (char *last_insn, | |
3666 | enum xtensa_relax_statesE frag_state, | |
3667 | enum xtensa_relax_statesE slot0_state, | |
3668 | int max_growth, | |
3669 | bfd_boolean is_insn) | |
e0001a05 NC |
3670 | { |
3671 | /* Finish off this fragment so that it has at LEAST the desired | |
3672 | max_growth. If it doesn't fit in this fragment, close this one | |
3673 | and start a new one. In either case, return a pointer to the | |
3674 | beginning of the growth area. */ | |
3675 | ||
3676 | fragS *old_frag; | |
43cd72b9 | 3677 | |
542f8b94 | 3678 | frag_grow (max_growth); |
e0001a05 NC |
3679 | old_frag = frag_now; |
3680 | ||
3681 | frag_now->fr_opcode = last_insn; | |
3682 | if (is_insn) | |
3683 | frag_now->tc_frag_data.is_insn = TRUE; | |
3684 | ||
3685 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3686 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3687 | ||
3688 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3689 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3690 | |
3691 | /* Just to make sure that we did not split it up. */ | |
3692 | assert (old_frag->fr_next == frag_now); | |
3693 | } | |
3694 | ||
3695 | ||
7fa3d080 BW |
3696 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3697 | ||
3698 | static bfd_boolean | |
3699 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3700 | { | |
3701 | if (fragP == NULL) | |
3702 | return FALSE; | |
3703 | ||
3704 | for (; fragP; fragP = fragP->fr_next) | |
3705 | { | |
3706 | if (fragP == target) | |
3707 | return TRUE; | |
3708 | if (fragP->fr_fix != 0) | |
3709 | return FALSE; | |
3710 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3711 | return FALSE; | |
3712 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3713 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3714 | return FALSE; | |
3715 | if (fragP->fr_type == rs_space) | |
3716 | return FALSE; | |
3717 | } | |
3718 | return FALSE; | |
3719 | } | |
3720 | ||
3721 | ||
e0001a05 | 3722 | static bfd_boolean |
7fa3d080 | 3723 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3724 | { |
3725 | xtensa_isa isa = xtensa_default_isa; | |
3726 | int i; | |
43cd72b9 | 3727 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3728 | int target_op = -1; |
3729 | symbolS *sym; | |
3730 | fragS *target_frag; | |
3731 | ||
64b607e6 BW |
3732 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3733 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3734 | return FALSE; |
3735 | ||
3736 | for (i = 0; i < num_ops; i++) | |
3737 | { | |
43cd72b9 | 3738 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3739 | { |
3740 | target_op = i; | |
3741 | break; | |
3742 | } | |
3743 | } | |
3744 | if (target_op == -1) | |
3745 | return FALSE; | |
3746 | ||
3747 | if (insn->ntok <= target_op) | |
3748 | return FALSE; | |
3749 | ||
3750 | if (insn->tok[target_op].X_op != O_symbol) | |
3751 | return FALSE; | |
3752 | ||
3753 | sym = insn->tok[target_op].X_add_symbol; | |
3754 | if (sym == NULL) | |
3755 | return FALSE; | |
3756 | ||
3757 | if (insn->tok[target_op].X_add_number != 0) | |
3758 | return FALSE; | |
3759 | ||
3760 | target_frag = symbol_get_frag (sym); | |
3761 | if (target_frag == NULL) | |
3762 | return FALSE; | |
3763 | ||
c138bc38 | 3764 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3765 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3766 | return TRUE; | |
3767 | ||
3768 | return FALSE; | |
3769 | } | |
3770 | ||
3771 | ||
3772 | static void | |
7fa3d080 | 3773 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3774 | { |
3775 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3776 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3777 | |
7fa3d080 BW |
3778 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3779 | { | |
3780 | int i = 1; | |
3781 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3782 | && insn->tok[i].X_op == O_symbol) | |
3783 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3784 | return; | |
3785 | } | |
e0001a05 | 3786 | |
7fa3d080 BW |
3787 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3788 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3789 | { |
7fa3d080 BW |
3790 | int i; |
3791 | ||
3792 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3793 | { | |
3794 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3795 | && insn->tok[i].X_op == O_symbol) | |
3796 | { | |
3797 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3798 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3799 | if (S_IS_DEFINED (sym)) | |
3800 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3801 | } | |
3802 | } | |
e0001a05 | 3803 | } |
e0001a05 NC |
3804 | } |
3805 | ||
3806 | ||
43cd72b9 | 3807 | /* Return FALSE if no error. */ |
e0001a05 | 3808 | |
7fa3d080 BW |
3809 | static bfd_boolean |
3810 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3811 | { |
3812 | int num_ops = 0; | |
3813 | BuildOp *b_op; | |
3814 | ||
3815 | switch (instr_spec->typ) | |
3816 | { | |
3817 | case INSTR_INSTR: | |
3818 | new_insn->insn_type = ITYPE_INSN; | |
3819 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3820 | break; |
3821 | case INSTR_LITERAL_DEF: | |
3822 | new_insn->insn_type = ITYPE_LITERAL; | |
3823 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3824 | break; |
3825 | case INSTR_LABEL_DEF: | |
b224e962 | 3826 | abort (); |
e0001a05 | 3827 | } |
b224e962 BW |
3828 | new_insn->is_specific_opcode = FALSE; |
3829 | new_insn->debug_line = old_insn->debug_line; | |
3830 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3831 | |
3832 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3833 | { | |
3834 | expressionS *exp; | |
3835 | const expressionS *src_exp; | |
3836 | ||
3837 | num_ops++; | |
3838 | switch (b_op->typ) | |
3839 | { | |
3840 | case OP_CONSTANT: | |
3841 | /* The expression must be the constant. */ | |
3842 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3843 | exp = &new_insn->tok[b_op->op_num]; | |
3844 | set_expr_const (exp, b_op->op_data); | |
3845 | break; | |
3846 | ||
3847 | case OP_OPERAND: | |
3848 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3849 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3850 | src_exp = &old_insn->tok[b_op->op_data]; | |
3851 | exp = &new_insn->tok[b_op->op_num]; | |
3852 | copy_expr (exp, src_exp); | |
3853 | break; | |
3854 | ||
3855 | case OP_LITERAL: | |
3856 | case OP_LABEL: | |
3857 | as_bad (_("can't handle generation of literal/labels yet")); | |
3858 | assert (0); | |
3859 | ||
3860 | default: | |
3861 | as_bad (_("can't handle undefined OP TYPE")); | |
3862 | assert (0); | |
3863 | } | |
3864 | } | |
3865 | ||
3866 | new_insn->ntok = num_ops; | |
3867 | return FALSE; | |
3868 | } | |
3869 | ||
3870 | ||
43cd72b9 | 3871 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3872 | |
7fa3d080 BW |
3873 | static bfd_boolean |
3874 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3875 | { |
43cd72b9 | 3876 | TransitionRule *rule; |
e0001a05 | 3877 | BuildInstr *insn_spec; |
43cd72b9 BW |
3878 | |
3879 | if (old_insn->is_specific_opcode || !density_supported) | |
3880 | return FALSE; | |
3881 | ||
3882 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3883 | if (rule == NULL) |
3884 | return FALSE; | |
3885 | ||
3886 | insn_spec = rule->to_instr; | |
3887 | /* There should only be one. */ | |
3888 | assert (insn_spec != NULL); | |
3889 | assert (insn_spec->next == NULL); | |
3890 | if (insn_spec->next != NULL) | |
3891 | return FALSE; | |
3892 | ||
3893 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3894 | ||
3895 | return TRUE; | |
3896 | } | |
3897 | ||
3898 | ||
3899 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3900 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3901 | tokens into the stack or relax it and place multiple |
3902 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3903 | |
3904 | static bfd_boolean | |
7fa3d080 | 3905 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3906 | { |
3907 | int noperands; | |
3908 | TInsn new_insn; | |
7c834684 BW |
3909 | bfd_boolean do_expand; |
3910 | ||
60242db2 | 3911 | tinsn_init (&new_insn); |
e0001a05 | 3912 | |
43cd72b9 BW |
3913 | /* Narrow it if we can. xg_simplify_insn now does all the |
3914 | appropriate checking (e.g., for the density option). */ | |
3915 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3916 | orig_insn = &new_insn; | |
e0001a05 | 3917 | |
43cd72b9 BW |
3918 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3919 | orig_insn->opcode); | |
e0001a05 NC |
3920 | if (orig_insn->ntok < noperands) |
3921 | { | |
3922 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3923 | orig_insn->ntok, | |
3924 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3925 | noperands); | |
3926 | return TRUE; | |
3927 | } | |
3928 | if (orig_insn->ntok > noperands) | |
3929 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3930 | orig_insn->ntok, | |
3931 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3932 | noperands); | |
3933 | ||
43cd72b9 | 3934 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3935 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3936 | orig_insn->ntok = noperands; |
3937 | ||
e0001a05 NC |
3938 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3939 | return TRUE; | |
3940 | ||
d12f9798 BW |
3941 | /* Special case for extui opcode which has constraints not handled |
3942 | by the ordinary operand encoding checks. The number of operands | |
3943 | and related syntax issues have already been checked. */ | |
3944 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3945 | { | |
3946 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3947 | int maskimm = orig_insn->tok[3].X_add_number; | |
3948 | if (shiftimm + maskimm > 32) | |
3949 | { | |
3950 | as_bad (_("immediate operands sum to greater than 32")); | |
3951 | return TRUE; | |
3952 | } | |
3953 | } | |
3954 | ||
7c834684 BW |
3955 | /* If the instruction will definitely need to be relaxed, it is better |
3956 | to expand it now for better scheduling. Decide whether to expand | |
3957 | now.... */ | |
3958 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3959 | ||
3960 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3961 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3962 | adjacent. */ | |
3963 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3964 | do_expand = FALSE; | |
e0001a05 NC |
3965 | |
3966 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3967 | { | |
7c834684 BW |
3968 | /* The values of symbolic operands are not known yet, so only expand |
3969 | now if an operand is "complex" (e.g., difference of symbols) and | |
3970 | will have to be stored as a literal regardless of the value. */ | |
3971 | if (!tinsn_has_complex_operands (orig_insn)) | |
3972 | do_expand = FALSE; | |
e0001a05 | 3973 | } |
7c834684 BW |
3974 | else if (xg_immeds_fit (orig_insn)) |
3975 | do_expand = FALSE; | |
3976 | ||
3977 | if (do_expand) | |
3978 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3979 | else |
7c834684 | 3980 | istack_push (istack, orig_insn); |
e0001a05 | 3981 | |
e0001a05 NC |
3982 | return FALSE; |
3983 | } | |
3984 | ||
3985 | ||
7fa3d080 | 3986 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3987 | or the name is .gnu.linkonce.*. */ |
3988 | ||
3989 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3990 | |
3991 | static bfd_boolean | |
3992 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3993 | { | |
3994 | flagword flags, link_once_flags; | |
3995 | ||
3996 | flags = bfd_get_section_flags (abfd, sec); | |
3997 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3998 | ||
3999 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4000 | if (!link_once_flags |
4001 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4002 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4003 | |
7fa3d080 BW |
4004 | return (link_once_flags != 0); |
4005 | } | |
4006 | ||
4007 | ||
4008 | static void | |
4009 | xtensa_add_literal_sym (symbolS *sym) | |
4010 | { | |
4011 | sym_list *l; | |
4012 | ||
4013 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
4014 | l->sym = sym; | |
4015 | l->next = literal_syms; | |
4016 | literal_syms = l; | |
4017 | } | |
4018 | ||
4019 | ||
4020 | static symbolS * | |
4021 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4022 | { | |
4023 | static int lit_num = 0; | |
4024 | static char name[256]; | |
4025 | symbolS *symbolP; | |
4026 | ||
4027 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4028 | ||
4029 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4030 | be careful to make sure that if it is used in a relocation that the | |
4031 | symbol will be in the output file. */ | |
4032 | if (get_is_linkonce_section (stdoutput, sec)) | |
4033 | { | |
4034 | symbolP = symbol_new (name, sec, 0, frag); | |
4035 | S_CLEAR_EXTERNAL (symbolP); | |
4036 | /* symbolP->local = 1; */ | |
4037 | } | |
4038 | else | |
4039 | symbolP = symbol_new (name, sec, 0, frag); | |
4040 | ||
4041 | xtensa_add_literal_sym (symbolP); | |
4042 | ||
7fa3d080 BW |
4043 | lit_num++; |
4044 | return symbolP; | |
4045 | } | |
4046 | ||
4047 | ||
e0001a05 NC |
4048 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4049 | ||
7fa3d080 BW |
4050 | static symbolS * |
4051 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4052 | { |
4053 | emit_state state; | |
4054 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4055 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4056 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4057 | char *p; |
e0001a05 NC |
4058 | |
4059 | /* size = 4 for L32R. It could easily be larger when we move to | |
4060 | larger constants. Add a parameter later. */ | |
4061 | offsetT litsize = 4; | |
4062 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4063 | expressionS saved_loc; | |
43cd72b9 BW |
4064 | expressionS * emit_val; |
4065 | ||
e0001a05 NC |
4066 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4067 | ||
4068 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4069 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4070 | |
4071 | xtensa_switch_to_literal_fragment (&state); | |
4072 | ||
43cd72b9 BW |
4073 | emit_val = &insn->tok[0]; |
4074 | if (emit_val->X_op == O_big) | |
4075 | { | |
4076 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4077 | if (size > litsize) | |
4078 | { | |
4079 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4080 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4081 | _("invalid immediate")); |
4082 | xtensa_restore_emit_state (&state); | |
4083 | return NULL; | |
4084 | } | |
4085 | } | |
4086 | ||
e0001a05 NC |
4087 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4088 | literals done with this function have a frag to themselves. That's | |
4089 | important for the way text section literals work. */ | |
4090 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4091 | record_alignment (now_seg, litalign); |
e0001a05 | 4092 | |
bbdd25a8 | 4093 | switch (emit_val->X_op) |
43cd72b9 | 4094 | { |
1bbb5f21 BW |
4095 | case O_pcrel: |
4096 | pcrel = TRUE; | |
4097 | /* fall through */ | |
bbdd25a8 | 4098 | case O_pltrel: |
28dbbc02 BW |
4099 | case O_tlsfunc: |
4100 | case O_tlsarg: | |
4101 | case O_tpoff: | |
4102 | case O_dtpoff: | |
bbdd25a8 | 4103 | p = frag_more (litsize); |
43cd72b9 | 4104 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4105 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4106 | if (emit_val->X_add_symbol) |
4107 | emit_val->X_op = O_symbol; | |
4108 | else | |
4109 | emit_val->X_op = O_constant; | |
4110 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4111 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4112 | break; |
4113 | ||
4114 | default: | |
4115 | emit_expr (emit_val, litsize); | |
4116 | break; | |
43cd72b9 | 4117 | } |
e0001a05 NC |
4118 | |
4119 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4120 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4121 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4122 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4123 | |
4124 | /* Go back. */ | |
4125 | xtensa_restore_emit_state (&state); | |
4126 | return lit_sym; | |
4127 | } | |
4128 | ||
4129 | ||
4130 | static void | |
7fa3d080 | 4131 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4132 | { |
4133 | emit_state state; | |
43cd72b9 | 4134 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4135 | takes effect if something is placed here. */ |
4136 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4137 | fragS *lit_saved_frag; | |
4138 | ||
e0001a05 | 4139 | assert (size % 4 == 0); |
e0001a05 NC |
4140 | |
4141 | xtensa_switch_to_literal_fragment (&state); | |
4142 | ||
4143 | /* Force a 4-byte align here. */ | |
4144 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4145 | record_alignment (now_seg, litalign); |
e0001a05 | 4146 | |
542f8b94 | 4147 | frag_grow (size); |
e0001a05 NC |
4148 | |
4149 | lit_saved_frag = frag_now; | |
4150 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4151 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4152 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4153 | |
4154 | /* Go back. */ | |
4155 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4156 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4157 | } |
4158 | ||
4159 | ||
e0001a05 | 4160 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4161 | Return TRUE on success. */ |
e0001a05 | 4162 | |
7fa3d080 BW |
4163 | static bfd_boolean |
4164 | xg_add_opcode_fix (TInsn *tinsn, | |
4165 | int opnum, | |
4166 | xtensa_format fmt, | |
4167 | int slot, | |
4168 | expressionS *expr, | |
4169 | fragS *fragP, | |
4170 | offsetT offset) | |
43cd72b9 BW |
4171 | { |
4172 | xtensa_opcode opcode = tinsn->opcode; | |
4173 | bfd_reloc_code_real_type reloc; | |
4174 | reloc_howto_type *howto; | |
4175 | int fmt_length; | |
e0001a05 NC |
4176 | fixS *the_fix; |
4177 | ||
43cd72b9 BW |
4178 | reloc = BFD_RELOC_NONE; |
4179 | ||
4180 | /* First try the special cases for "alternate" relocs. */ | |
4181 | if (opcode == xtensa_l32r_opcode) | |
4182 | { | |
4183 | if (fragP->tc_frag_data.use_absolute_literals) | |
4184 | reloc = encode_alt_reloc (slot); | |
4185 | } | |
4186 | else if (opcode == xtensa_const16_opcode) | |
4187 | { | |
4188 | if (expr->X_op == O_lo16) | |
4189 | { | |
4190 | reloc = encode_reloc (slot); | |
4191 | expr->X_op = O_symbol; | |
4192 | } | |
4193 | else if (expr->X_op == O_hi16) | |
4194 | { | |
4195 | reloc = encode_alt_reloc (slot); | |
4196 | expr->X_op = O_symbol; | |
4197 | } | |
4198 | } | |
4199 | ||
4200 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4201 | { |
43cd72b9 | 4202 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4203 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4204 | return FALSE; |
4205 | } | |
4206 | ||
43cd72b9 BW |
4207 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4208 | into the symbol table where the generic portions of the assembler | |
4209 | won't know what to do with them. */ | |
4210 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4211 | { | |
4212 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4213 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4214 | return FALSE; |
4215 | } | |
4216 | ||
4217 | /* Next try the generic relocs. */ | |
4218 | if (reloc == BFD_RELOC_NONE) | |
4219 | reloc = encode_reloc (slot); | |
4220 | if (reloc == BFD_RELOC_NONE) | |
4221 | { | |
4222 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4223 | return FALSE; | |
4224 | } | |
e0001a05 | 4225 | |
43cd72b9 | 4226 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4227 | if (!howto) |
4228 | { | |
43cd72b9 | 4229 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4230 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4231 | return FALSE; | |
4232 | } | |
4233 | ||
43cd72b9 BW |
4234 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4235 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4236 | howto->pc_relative, reloc); |
d9740523 | 4237 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4238 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4239 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4240 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4241 | |
7fa3d080 BW |
4242 | return TRUE; |
4243 | } | |
4244 | ||
4245 | ||
4246 | static bfd_boolean | |
4247 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4248 | char *buf, |
4249 | fragS *fragP, | |
4250 | offsetT offset, | |
4251 | bfd_boolean build_fix) | |
4252 | { | |
4253 | static xtensa_insnbuf insnbuf = NULL; | |
4254 | bfd_boolean has_symbolic_immed = FALSE; | |
4255 | bfd_boolean ok = TRUE; | |
b2d179be | 4256 | |
7fa3d080 BW |
4257 | if (!insnbuf) |
4258 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4259 | ||
4260 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4261 | if (has_symbolic_immed && build_fix) | |
4262 | { | |
4263 | /* Add a fixup. */ | |
b2d179be BW |
4264 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4265 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4266 | int opnum = get_relaxable_immed (tinsn->opcode); |
4267 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4268 | |
b2d179be | 4269 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4270 | ok = FALSE; |
4271 | } | |
4272 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4273 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4274 | (unsigned char *) buf, 0); | |
7fa3d080 | 4275 | return ok; |
e0001a05 NC |
4276 | } |
4277 | ||
4278 | ||
7fa3d080 BW |
4279 | static void |
4280 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4281 | { |
4282 | symbolS *sym = get_special_literal_symbol (); | |
4283 | int i; | |
4284 | if (lit_sym == 0) | |
4285 | return; | |
4286 | assert (insn->insn_type == ITYPE_INSN); | |
4287 | for (i = 0; i < insn->ntok; i++) | |
4288 | if (insn->tok[i].X_add_symbol == sym) | |
4289 | insn->tok[i].X_add_symbol = lit_sym; | |
4290 | ||
4291 | } | |
4292 | ||
4293 | ||
7fa3d080 BW |
4294 | static void |
4295 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4296 | { |
4297 | symbolS *sym = get_special_label_symbol (); | |
4298 | int i; | |
e0001a05 NC |
4299 | for (i = 0; i < insn->ntok; i++) |
4300 | if (insn->tok[i].X_add_symbol == sym) | |
4301 | insn->tok[i].X_add_symbol = label_sym; | |
4302 | ||
4303 | } | |
4304 | ||
4305 | ||
43cd72b9 | 4306 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4307 | integer register. */ |
4308 | ||
4309 | static bfd_boolean | |
7fa3d080 | 4310 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4311 | { |
4312 | int i; | |
4313 | int num_ops; | |
4314 | xtensa_isa isa = xtensa_default_isa; | |
4315 | ||
43cd72b9 | 4316 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4317 | |
4318 | for (i = 0; i < num_ops; i++) | |
4319 | { | |
43cd72b9 BW |
4320 | char inout; |
4321 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4322 | if ((inout == 'o' || inout == 'm') | |
4323 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4324 | { |
43cd72b9 BW |
4325 | xtensa_regfile opnd_rf = |
4326 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4327 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4328 | { |
4329 | if ((insn->tok[i].X_op == O_register) | |
4330 | && (insn->tok[i].X_add_number == regnum)) | |
4331 | return TRUE; | |
4332 | } | |
4333 | } | |
4334 | } | |
4335 | return FALSE; | |
4336 | } | |
4337 | ||
4338 | ||
4339 | static bfd_boolean | |
7fa3d080 | 4340 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4341 | { |
4342 | xtensa_opcode opcode = tinsn->opcode; | |
4343 | ||
4344 | if (opcode == XTENSA_UNDEFINED) | |
4345 | return FALSE; | |
4346 | ||
4347 | if (opcode == xtensa_call0_opcode | |
4348 | || opcode == xtensa_callx0_opcode | |
4349 | || opcode == xtensa_call4_opcode | |
4350 | || opcode == xtensa_callx4_opcode | |
4351 | || opcode == xtensa_call8_opcode | |
4352 | || opcode == xtensa_callx8_opcode | |
4353 | || opcode == xtensa_call12_opcode | |
4354 | || opcode == xtensa_callx12_opcode | |
4355 | || opcode == xtensa_isync_opcode | |
4356 | || opcode == xtensa_ret_opcode | |
4357 | || opcode == xtensa_ret_n_opcode | |
4358 | || opcode == xtensa_retw_opcode | |
4359 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4360 | || opcode == xtensa_waiti_opcode |
4361 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4362 | return TRUE; |
c138bc38 | 4363 | |
e0001a05 NC |
4364 | return FALSE; |
4365 | } | |
4366 | ||
4367 | ||
4368 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4369 | This allows the debugger to add unaligned labels. | |
4370 | Also, the assembler generates stabs labels that need | |
4371 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4372 | ||
7fa3d080 BW |
4373 | static bfd_boolean |
4374 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4375 | { |
4376 | const char *name = S_GET_NAME (sym); | |
4377 | static size_t fake_size = 0; | |
4378 | ||
4379 | if (name | |
4380 | && name[0] == '.' | |
4381 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4382 | return TRUE; | |
4383 | ||
4384 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4385 | if (fake_size == 0) | |
4386 | fake_size = strlen (FAKE_LABEL_NAME); | |
4387 | ||
43cd72b9 | 4388 | if (name |
e0001a05 NC |
4389 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4390 | && (name[fake_size] == 'F' | |
4391 | || name[fake_size] == 'L' | |
4392 | || (name[fake_size] == 'e' | |
4393 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4394 | return TRUE; | |
4395 | ||
4396 | return FALSE; | |
4397 | } | |
4398 | ||
4399 | ||
7fa3d080 BW |
4400 | static fragS * |
4401 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4402 | { |
4403 | fragS *next_fragP = fragP->fr_next; | |
4404 | ||
c138bc38 | 4405 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4406 | So we have to skip until we find something legit. */ |
4407 | while (next_fragP && next_fragP->fr_fix == 0) | |
4408 | next_fragP = next_fragP->fr_next; | |
4409 | ||
4410 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4411 | return NULL; | |
4412 | ||
4413 | return next_fragP; | |
4414 | } | |
4415 | ||
4416 | ||
43cd72b9 | 4417 | static bfd_boolean |
7fa3d080 | 4418 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4419 | { |
4420 | xtensa_opcode out_opcode; | |
4421 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4422 | ||
4423 | if (next_fragP == NULL) | |
4424 | return FALSE; | |
4425 | ||
4426 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4427 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4428 | { | |
4429 | *opcode = out_opcode; | |
4430 | return TRUE; | |
4431 | } | |
4432 | return FALSE; | |
4433 | } | |
4434 | ||
4435 | ||
4436 | static int | |
7fa3d080 | 4437 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4438 | { |
e0001a05 NC |
4439 | static xtensa_insnbuf insnbuf = NULL; |
4440 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4441 | xtensa_format fmt; |
c138bc38 | 4442 | int fmt_size; |
e0001a05 NC |
4443 | |
4444 | if (!insnbuf) | |
4445 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4446 | ||
43cd72b9 BW |
4447 | if (fragP == NULL) |
4448 | return XTENSA_UNDEFINED; | |
4449 | ||
d77b99c9 BW |
4450 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4451 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4452 | |
4453 | fmt = xtensa_format_decode (isa, insnbuf); | |
4454 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4455 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4456 | fmt_size = xtensa_format_length (isa, fmt); |
4457 | ||
4458 | /* If the next format won't be changing due to relaxation, just | |
4459 | return the length of the first format. */ | |
4460 | if (fragP->fr_opcode != fragP->fr_literal) | |
4461 | return fmt_size; | |
4462 | ||
c138bc38 | 4463 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4464 | multi-slot instruction, we will return the more conservative |
4465 | number. This works because alignment on bigger instructions | |
4466 | is more restrictive than alignment on smaller instructions. | |
4467 | This is more conservative than we would like, but it happens | |
4468 | infrequently. */ | |
4469 | ||
4470 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4471 | return fmt_size; | |
4472 | ||
4473 | /* If we aren't doing one of our own relaxations or it isn't | |
4474 | slot-based, then the insn size won't change. */ | |
4475 | if (fragP->fr_type != rs_machine_dependent) | |
4476 | return fmt_size; | |
4477 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4478 | return fmt_size; | |
4479 | ||
4480 | /* If an instruction is about to grow, return the longer size. */ | |
4481 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4482 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4483 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4484 | { |
4485 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4486 | instruction in the relaxed version is of length 3. (The case | |
4487 | where we have to pull the instruction out of a FLIX bundle | |
4488 | is handled conservatively above.) However, frags with opcodes | |
4489 | that are expanding to wide branches end up having formats that | |
4490 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4491 | we can't tell directly what format the relaxer picked. This | |
4492 | is a wart in the design of the relaxer that should someday be | |
4493 | fixed, but would require major changes, or at least should | |
4494 | be accompanied by major changes to make use of that data. | |
4495 | ||
4496 | In any event, we can tell that we are expanding from a single-slot | |
4497 | three-byte format to a wider one with the logic below. */ | |
4498 | ||
4499 | if (fmt_size <= 3 && fragP->tc_frag_data.text_expansion[0] != 3) | |
4500 | return 3 + fragP->tc_frag_data.text_expansion[0]; | |
4501 | else | |
4502 | return 3; | |
4503 | } | |
c138bc38 | 4504 | |
43cd72b9 BW |
4505 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4506 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4507 | |
43cd72b9 | 4508 | return fmt_size; |
e0001a05 NC |
4509 | } |
4510 | ||
4511 | ||
7fa3d080 BW |
4512 | static int |
4513 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4514 | { |
7fa3d080 BW |
4515 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4516 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4517 | } |
4518 | ||
4519 | ||
03aaa593 BW |
4520 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4521 | required two-byte instructions to be treated as three-byte instructions | |
4522 | for loop instruction alignment. This restriction was removed beginning | |
4523 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4524 | is that the first instruction of the loop must appear at an address that | |
4525 | does not cross a fetch boundary. */ | |
4526 | ||
4527 | static int | |
4528 | get_loop_align_size (int insn_size) | |
4529 | { | |
4530 | if (insn_size == XTENSA_UNDEFINED) | |
4531 | return xtensa_fetch_width; | |
4532 | ||
4533 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4534 | return 3; | |
4535 | ||
4536 | return insn_size; | |
4537 | } | |
4538 | ||
4539 | ||
e0001a05 NC |
4540 | /* If the next legit fragment is an end-of-loop marker, |
4541 | switch its state so it will instantiate a NOP. */ | |
4542 | ||
4543 | static void | |
1d19a770 | 4544 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4545 | { |
4546 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4547 | fragS *new_target = NULL; |
e0001a05 | 4548 | |
7b1cc377 | 4549 | if (align_targets) |
43cd72b9 BW |
4550 | { |
4551 | /* We are guaranteed there will be one of these... */ | |
4552 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4553 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4554 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4555 | next_fragP = next_fragP->fr_next; | |
4556 | ||
4557 | assert (next_fragP->fr_type == rs_machine_dependent | |
4558 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4559 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4560 | ||
4561 | /* ...and one of these. */ | |
4562 | new_target = next_fragP->fr_next; | |
4563 | while (!(new_target->fr_type == rs_machine_dependent | |
4564 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4565 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4566 | new_target = new_target->fr_next; | |
4567 | ||
4568 | assert (new_target->fr_type == rs_machine_dependent | |
4569 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4570 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4571 | } | |
43cd72b9 | 4572 | |
1d19a770 | 4573 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4574 | { |
1d19a770 BW |
4575 | if (next_fragP->fr_type == rs_machine_dependent |
4576 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4577 | { |
1d19a770 BW |
4578 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4579 | return; | |
e0001a05 | 4580 | } |
1d19a770 BW |
4581 | |
4582 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4583 | } |
4584 | } | |
4585 | ||
4586 | ||
4587 | static bfd_boolean | |
7fa3d080 | 4588 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4589 | { |
43cd72b9 | 4590 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4591 | so we have to skip until we find something legit. */ |
4592 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4593 | { | |
4594 | if (fragP->tc_frag_data.is_branch_target) | |
4595 | return TRUE; | |
4596 | if (fragP->fr_fix != 0) | |
4597 | break; | |
4598 | } | |
4599 | return FALSE; | |
4600 | } | |
4601 | ||
4602 | ||
4603 | static bfd_boolean | |
7fa3d080 | 4604 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4605 | { |
c138bc38 | 4606 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4607 | So we have to skip until we find something legit. */ |
4608 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4609 | { | |
4610 | if (fragP->tc_frag_data.is_loop_target) | |
4611 | return TRUE; | |
4612 | if (fragP->fr_fix != 0) | |
4613 | break; | |
4614 | } | |
4615 | return FALSE; | |
4616 | } | |
4617 | ||
4618 | ||
4619 | static addressT | |
7fa3d080 | 4620 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4621 | { |
4622 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4623 | xtensa_opcode next_opcode; |
e0001a05 | 4624 | |
43cd72b9 | 4625 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4626 | return 0; |
4627 | ||
43cd72b9 BW |
4628 | /* Sometimes an empty will end up here due to storage allocation issues, |
4629 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4630 | while (next_fragp->fr_fix == 0) |
4631 | next_fragp = next_fragp->fr_next; | |
4632 | ||
4633 | if (next_fragp->fr_type != rs_machine_dependent) | |
4634 | return 0; | |
4635 | ||
4636 | /* There is some implicit knowledge encoded in here. | |
4637 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4638 | been relaxed. Note that we can assume that the LOOP |
4639 | instruction is in slot 0 because loops aren't bundleable. */ | |
4640 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4641 | return get_expanded_loop_offset (next_opcode); |
4642 | ||
4643 | return 0; | |
4644 | } | |
4645 | ||
4646 | ||
4647 | /* Mark a location where we can later insert literal frags. Update | |
4648 | the section's literal_pool_loc, so subsequent literals can be | |
4649 | placed nearest to their use. */ | |
4650 | ||
4651 | static void | |
7fa3d080 | 4652 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4653 | { |
4654 | /* Any labels pointing to the current location need | |
4655 | to be adjusted to after the literal pool. */ | |
4656 | emit_state s; | |
e0001a05 | 4657 | fragS *pool_location; |
e0001a05 | 4658 | |
1f2a7e38 | 4659 | if (use_literal_section) |
43cd72b9 BW |
4660 | return; |
4661 | ||
dd49a749 BW |
4662 | /* We stash info in these frags so we can later move the literal's |
4663 | fixes into this frchain's fix list. */ | |
e0001a05 | 4664 | pool_location = frag_now; |
dd49a749 | 4665 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4666 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4667 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4668 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4669 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4670 | frag_now->tc_frag_data.lit_seg = now_seg; |
4671 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4672 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4673 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4674 | |
4675 | /* Now put a frag into the literal pool that points to this location. */ | |
4676 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4677 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4678 | frag_align (2, 0, 0); | |
4679 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4680 | |
4681 | /* Close whatever frag is there. */ | |
4682 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4683 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4684 | frag_now->tc_frag_data.literal_frag = pool_location; |
4685 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4686 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4687 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4688 | } |
4689 | ||
4690 | ||
43cd72b9 BW |
4691 | /* Build a nop of the correct size into tinsn. */ |
4692 | ||
4693 | static void | |
7fa3d080 | 4694 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4695 | { |
4696 | tinsn_init (tinsn); | |
4697 | switch (size) | |
4698 | { | |
4699 | case 2: | |
4700 | tinsn->opcode = xtensa_nop_n_opcode; | |
4701 | tinsn->ntok = 0; | |
4702 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4703 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4704 | break; | |
4705 | ||
4706 | case 3: | |
4707 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4708 | { | |
4709 | tinsn->opcode = xtensa_or_opcode; | |
4710 | set_expr_const (&tinsn->tok[0], 1); | |
4711 | set_expr_const (&tinsn->tok[1], 1); | |
4712 | set_expr_const (&tinsn->tok[2], 1); | |
4713 | tinsn->ntok = 3; | |
4714 | } | |
4715 | else | |
4716 | tinsn->opcode = xtensa_nop_opcode; | |
4717 | ||
4718 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4719 | } | |
4720 | } | |
4721 | ||
4722 | ||
e0001a05 NC |
4723 | /* Assemble a NOP of the requested size in the buffer. User must have |
4724 | allocated "buf" with at least "size" bytes. */ | |
4725 | ||
7fa3d080 | 4726 | static void |
d77b99c9 | 4727 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4728 | { |
4729 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4730 | TInsn tinsn; |
e0001a05 | 4731 | |
43cd72b9 | 4732 | build_nop (&tinsn, size); |
e0001a05 | 4733 | |
43cd72b9 BW |
4734 | if (!insnbuf) |
4735 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4736 | |
43cd72b9 | 4737 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4738 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4739 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4740 | } |
4741 | ||
4742 | ||
4743 | /* Return the number of bytes for the offset of the expanded loop | |
4744 | instruction. This should be incorporated into the relaxation | |
4745 | specification but is hard-coded here. This is used to auto-align | |
4746 | the loop instruction. It is invalid to call this function if the | |
4747 | configuration does not have loops or if the opcode is not a loop | |
4748 | opcode. */ | |
4749 | ||
4750 | static addressT | |
7fa3d080 | 4751 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4752 | { |
4753 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4754 | This MUST correspond directly to the specification of the loop | |
4755 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4756 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4757 | if (opcode == xtensa_loop_opcode) |
4758 | return 0; | |
4759 | if (opcode == xtensa_loopnez_opcode) | |
4760 | return 3; | |
4761 | if (opcode == xtensa_loopgtz_opcode) | |
4762 | return 6; | |
4763 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4764 | return 0; | |
4765 | } | |
4766 | ||
4767 | ||
7fa3d080 BW |
4768 | static fragS * |
4769 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4770 | { |
4771 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4772 | } | |
4773 | ||
4774 | ||
4775 | static void | |
7fa3d080 | 4776 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4777 | { |
4778 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4779 | } | |
4780 | ||
43cd72b9 BW |
4781 | |
4782 | /* Set frag assembly state should be called when a new frag is | |
4783 | opened and after a frag has been closed. */ | |
4784 | ||
7fa3d080 BW |
4785 | static void |
4786 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4787 | { |
4788 | if (!density_supported) | |
4789 | fragP->tc_frag_data.is_no_density = TRUE; | |
4790 | ||
4791 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4792 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4793 | "use_schedule" here. */ |
4794 | if (!directive_state[directive_transform]) | |
4795 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4796 | if (directive_state[directive_longcalls]) |
4797 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4798 | fragP->tc_frag_data.use_absolute_literals = |
4799 | directive_state[directive_absolute_literals]; | |
4800 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4801 | } | |
4802 | ||
4803 | ||
7fa3d080 BW |
4804 | static bfd_boolean |
4805 | relaxable_section (asection *sec) | |
43cd72b9 | 4806 | { |
11ac2671 BW |
4807 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4808 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4809 | } |
4810 | ||
4811 | ||
99ded152 BW |
4812 | static void |
4813 | xtensa_mark_frags_for_org (void) | |
4814 | { | |
4815 | segT *seclist; | |
4816 | ||
4817 | /* Walk over each fragment of all of the current segments. If we find | |
4818 | a .org frag in any of the segments, mark all frags prior to it as | |
4819 | "no transform", which will prevent linker optimizations from messing | |
4820 | up the .org distance. This should be done after | |
4821 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4822 | about that function trashing the data we save here. */ | |
4823 | ||
4824 | for (seclist = &stdoutput->sections; | |
4825 | seclist && *seclist; | |
4826 | seclist = &(*seclist)->next) | |
4827 | { | |
4828 | segT sec = *seclist; | |
4829 | segment_info_type *seginfo; | |
4830 | fragS *fragP; | |
4831 | flagword flags; | |
4832 | flags = bfd_get_section_flags (stdoutput, sec); | |
4833 | if (flags & SEC_DEBUGGING) | |
4834 | continue; | |
4835 | if (!(flags & SEC_ALLOC)) | |
4836 | continue; | |
4837 | ||
4838 | seginfo = seg_info (sec); | |
4839 | if (seginfo && seginfo->frchainP) | |
4840 | { | |
4841 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4842 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4843 | fragP = fragP->fr_next) | |
4844 | { | |
4845 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4846 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4847 | if (fragP->fr_subtype == RELAX_ORG) | |
4848 | { | |
4849 | while (last_fragP != fragP->fr_next) | |
4850 | { | |
4851 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4852 | last_fragP = last_fragP->fr_next; | |
4853 | } | |
4854 | } | |
4855 | } | |
4856 | } | |
4857 | } | |
4858 | } | |
4859 | ||
4860 | ||
43cd72b9 | 4861 | static void |
7fa3d080 | 4862 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4863 | { |
4864 | segT *seclist; | |
4865 | ||
4866 | /* Walk over each fragment of all of the current segments. For each | |
4867 | unmarked fragment, mark it with the same info as the previous | |
4868 | fragment. */ | |
4869 | for (seclist = &stdoutput->sections; | |
4870 | seclist && *seclist; | |
4871 | seclist = &(*seclist)->next) | |
4872 | { | |
4873 | segT sec = *seclist; | |
4874 | segment_info_type *seginfo; | |
4875 | fragS *fragP; | |
4876 | flagword flags; | |
4877 | flags = bfd_get_section_flags (stdoutput, sec); | |
4878 | if (flags & SEC_DEBUGGING) | |
4879 | continue; | |
4880 | if (!(flags & SEC_ALLOC)) | |
4881 | continue; | |
4882 | ||
4883 | seginfo = seg_info (sec); | |
4884 | if (seginfo && seginfo->frchainP) | |
4885 | { | |
4886 | fragS *last_fragP = 0; | |
4887 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4888 | fragP = fragP->fr_next) | |
4889 | { | |
4890 | if (fragP->fr_fix != 0 | |
4891 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4892 | { | |
4893 | if (last_fragP == 0) | |
4894 | { | |
4895 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4896 | _("assembly state not set for first frag in section %s"), | |
4897 | sec->name); | |
4898 | } | |
4899 | else | |
4900 | { | |
4901 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4902 | fragP->tc_frag_data.is_no_density = | |
4903 | last_fragP->tc_frag_data.is_no_density; | |
4904 | fragP->tc_frag_data.is_no_transform = | |
4905 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4906 | fragP->tc_frag_data.use_longcalls = |
4907 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4908 | fragP->tc_frag_data.use_absolute_literals = |
4909 | last_fragP->tc_frag_data.use_absolute_literals; | |
4910 | } | |
4911 | } | |
4912 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4913 | last_fragP = fragP; | |
4914 | } | |
4915 | } | |
4916 | } | |
4917 | } | |
4918 | ||
4919 | ||
4920 | static void | |
7fa3d080 BW |
4921 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4922 | asection *sec, | |
4923 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4924 | { |
4925 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4926 | segment_info_type *seginfo = seg_info (sec); | |
4927 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4928 | |
43cd72b9 | 4929 | if (flags & SEC_CODE) |
c138bc38 | 4930 | { |
43cd72b9 BW |
4931 | xtensa_isa isa = xtensa_default_isa; |
4932 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4933 | while (frag != NULL) | |
4934 | { | |
4935 | if (frag->tc_frag_data.is_branch_target) | |
4936 | { | |
4937 | int op_size; | |
664df4e4 | 4938 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4939 | xtensa_format fmt; |
4940 | ||
d77b99c9 BW |
4941 | xtensa_insnbuf_from_chars |
4942 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4943 | fmt = xtensa_format_decode (isa, insnbuf); |
4944 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4945 | branch_align = 1 << branch_align_power (sec); |
4946 | frag_addr = frag->fr_address % branch_align; | |
4947 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4948 | as_warn_where (frag->fr_file, frag->fr_line, |
4949 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4950 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4951 | } |
4952 | frag = frag->fr_next; | |
4953 | } | |
4954 | xtensa_insnbuf_free (isa, insnbuf); | |
4955 | } | |
4956 | } | |
4957 | ||
4958 | ||
4959 | static void | |
7fa3d080 BW |
4960 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4961 | asection *sec, | |
4962 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4963 | { |
4964 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4965 | segment_info_type *seginfo = seg_info (sec); | |
4966 | fragS *frag = seginfo->frchainP->frch_root; | |
4967 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4968 | |
43cd72b9 | 4969 | if (flags & SEC_CODE) |
c138bc38 | 4970 | { |
43cd72b9 BW |
4971 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4972 | while (frag != NULL) | |
4973 | { | |
4974 | if (frag->tc_frag_data.is_first_loop_insn) | |
4975 | { | |
4976 | int op_size; | |
d77b99c9 | 4977 | addressT frag_addr; |
43cd72b9 BW |
4978 | xtensa_format fmt; |
4979 | ||
d77b99c9 BW |
4980 | xtensa_insnbuf_from_chars |
4981 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4982 | fmt = xtensa_format_decode (isa, insnbuf); |
4983 | op_size = xtensa_format_length (isa, fmt); | |
4984 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4985 | ||
d77b99c9 | 4986 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4987 | as_warn_where (frag->fr_file, frag->fr_line, |
4988 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4989 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4990 | } |
4991 | frag = frag->fr_next; | |
4992 | } | |
4993 | xtensa_insnbuf_free (isa, insnbuf); | |
4994 | } | |
4995 | } | |
4996 | ||
4997 | ||
30f725a1 BW |
4998 | static int |
4999 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5000 | { |
5001 | xtensa_isa isa = xtensa_default_isa; | |
5002 | static xtensa_insnbuf insnbuf = NULL; | |
5003 | static xtensa_insnbuf slotbuf = NULL; | |
5004 | xtensa_format fmt; | |
5005 | int slot; | |
5006 | bfd_boolean alt_reloc; | |
5007 | xtensa_opcode opcode; | |
5008 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5009 | ||
1b6e95c2 BW |
5010 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5011 | || alt_reloc) | |
43cd72b9 BW |
5012 | as_fatal (_("unexpected fix")); |
5013 | ||
5014 | if (!insnbuf) | |
5015 | { | |
5016 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5017 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5018 | } | |
5019 | ||
d77b99c9 | 5020 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5021 | fmt = xtensa_format_decode (isa, insnbuf); |
5022 | if (fmt == XTENSA_UNDEFINED) | |
5023 | as_fatal (_("undecodable fix")); | |
5024 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5025 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5026 | if (opcode == XTENSA_UNDEFINED) | |
5027 | as_fatal (_("undecodable fix")); | |
5028 | ||
5029 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5030 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5031 | of a CONST16 operand. */ |
43cd72b9 | 5032 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5033 | return 0; |
43cd72b9 BW |
5034 | |
5035 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5036 | get_relaxable_immed (opcode), val, | |
5037 | fixP->fx_file, fixP->fx_line); | |
5038 | ||
5039 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5040 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5041 | |
5042 | return 1; | |
43cd72b9 BW |
5043 | } |
5044 | ||
e0001a05 NC |
5045 | \f |
5046 | /* External Functions and Other GAS Hooks. */ | |
5047 | ||
5048 | const char * | |
7fa3d080 | 5049 | xtensa_target_format (void) |
e0001a05 NC |
5050 | { |
5051 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5052 | } | |
5053 | ||
5054 | ||
5055 | void | |
7fa3d080 | 5056 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5057 | { |
5058 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5059 | } | |
5060 | ||
5061 | ||
5062 | void | |
7fa3d080 | 5063 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5064 | { |
5065 | if (target_big_endian) | |
5066 | number_to_chars_bigendian (buf, val, n); | |
5067 | else | |
5068 | number_to_chars_littleendian (buf, val, n); | |
5069 | } | |
5070 | ||
5071 | ||
5072 | /* This function is called once, at assembler startup time. It should | |
5073 | set up all the tables, etc. that the MD part of the assembler will | |
5074 | need. */ | |
5075 | ||
5076 | void | |
7fa3d080 | 5077 | md_begin (void) |
e0001a05 NC |
5078 | { |
5079 | segT current_section = now_seg; | |
5080 | int current_subsec = now_subseg; | |
5081 | xtensa_isa isa; | |
5082 | ||
43cd72b9 | 5083 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5084 | isa = xtensa_default_isa; |
e0001a05 | 5085 | |
43cd72b9 BW |
5086 | linkrelax = 1; |
5087 | ||
74869ac7 | 5088 | /* Set up the literal sections. */ |
e0001a05 | 5089 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5090 | |
5091 | subseg_set (current_section, current_subsec); | |
5092 | ||
43cd72b9 BW |
5093 | xg_init_vinsn (&cur_vinsn); |
5094 | ||
e0001a05 NC |
5095 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
5096 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5097 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5098 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5099 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5100 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5101 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5102 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5103 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5104 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5105 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5106 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5107 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5108 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5109 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5110 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5111 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5112 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5113 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5114 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5115 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5116 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5117 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5118 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5119 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5120 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5121 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5122 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5123 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5124 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5125 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5126 | |
77cba8a3 BW |
5127 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5128 | ||
43cd72b9 BW |
5129 | init_op_placement_info_table (); |
5130 | ||
5131 | /* Set up the assembly state. */ | |
5132 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5133 | xtensa_set_frag_assembly_state (frag_now); | |
5134 | } | |
5135 | ||
5136 | ||
5137 | /* TC_INIT_FIX_DATA hook */ | |
5138 | ||
5139 | void | |
7fa3d080 | 5140 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5141 | { |
5142 | x->tc_fix_data.slot = 0; | |
5143 | x->tc_fix_data.X_add_symbol = NULL; | |
5144 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5145 | } |
5146 | ||
5147 | ||
5148 | /* tc_frob_label hook */ | |
5149 | ||
5150 | void | |
7fa3d080 | 5151 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5152 | { |
3ea38ac2 BW |
5153 | float freq; |
5154 | ||
5155 | if (cur_vinsn.inside_bundle) | |
5156 | { | |
5157 | as_bad (_("labels are not valid inside bundles")); | |
5158 | return; | |
5159 | } | |
5160 | ||
5161 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5162 | |
43cd72b9 BW |
5163 | /* Since the label was already attached to a frag associated with the |
5164 | previous basic block, it now needs to be reset to the current frag. */ | |
5165 | symbol_set_frag (sym, frag_now); | |
5166 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5167 | ||
82e7541d BW |
5168 | if (generating_literals) |
5169 | xtensa_add_literal_sym (sym); | |
5170 | else | |
5171 | xtensa_add_insn_label (sym); | |
5172 | ||
7b1cc377 BW |
5173 | if (symbol_get_tc (sym)->is_loop_target) |
5174 | { | |
5175 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5176 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5177 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5178 | ||
5179 | xtensa_set_frag_assembly_state (frag_now); | |
5180 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5181 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5182 | ||
5183 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5184 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5185 | } |
e0001a05 NC |
5186 | |
5187 | /* No target aligning in the absolute section. */ | |
61846f28 | 5188 | if (now_seg != absolute_section |
43cd72b9 | 5189 | && do_align_targets () |
61846f28 | 5190 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5191 | && !generating_literals) |
5192 | { | |
43cd72b9 BW |
5193 | xtensa_set_frag_assembly_state (frag_now); |
5194 | ||
43cd72b9 | 5195 | frag_var (rs_machine_dependent, |
7b1cc377 | 5196 | 0, (int) freq, |
e0001a05 NC |
5197 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5198 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5199 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5200 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5201 | } |
5202 | ||
5203 | /* We need to mark the following properties even if we aren't aligning. */ | |
5204 | ||
5205 | /* If the label is already known to be a branch target, i.e., a | |
5206 | forward branch, mark the frag accordingly. Backward branches | |
5207 | are handled by xg_add_branch_and_loop_targets. */ | |
5208 | if (symbol_get_tc (sym)->is_branch_target) | |
5209 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5210 | ||
5211 | /* Loops only go forward, so they can be identified here. */ | |
5212 | if (symbol_get_tc (sym)->is_loop_target) | |
5213 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5214 | |
5215 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5216 | } |
5217 | ||
5218 | ||
5219 | /* tc_unrecognized_line hook */ | |
5220 | ||
5221 | int | |
7fa3d080 | 5222 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5223 | { |
5224 | switch (ch) | |
5225 | { | |
5226 | case '{' : | |
5227 | if (cur_vinsn.inside_bundle == 0) | |
5228 | { | |
5229 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5230 | when using --gstabs. Temporarily disable debug info. */ | |
5231 | generate_lineno_debug (); | |
5232 | if (debug_type == DEBUG_STABS) | |
5233 | { | |
5234 | xt_saved_debug_type = debug_type; | |
5235 | debug_type = DEBUG_NONE; | |
5236 | } | |
82e7541d | 5237 | |
43cd72b9 BW |
5238 | cur_vinsn.inside_bundle = 1; |
5239 | } | |
5240 | else | |
5241 | { | |
5242 | as_bad (_("extra opening brace")); | |
5243 | return 0; | |
5244 | } | |
5245 | break; | |
82e7541d | 5246 | |
43cd72b9 BW |
5247 | case '}' : |
5248 | if (cur_vinsn.inside_bundle) | |
5249 | finish_vinsn (&cur_vinsn); | |
5250 | else | |
5251 | { | |
5252 | as_bad (_("extra closing brace")); | |
5253 | return 0; | |
5254 | } | |
5255 | break; | |
5256 | default: | |
5257 | as_bad (_("syntax error")); | |
5258 | return 0; | |
e0001a05 | 5259 | } |
43cd72b9 | 5260 | return 1; |
e0001a05 NC |
5261 | } |
5262 | ||
5263 | ||
5264 | /* md_flush_pending_output hook */ | |
5265 | ||
5266 | void | |
7fa3d080 | 5267 | xtensa_flush_pending_output (void) |
e0001a05 | 5268 | { |
a3582eee BW |
5269 | /* This line fixes a bug where automatically generated gstabs info |
5270 | separates a function label from its entry instruction, ending up | |
5271 | with the literal position between the function label and the entry | |
5272 | instruction and crashing code. It only happens with --gstabs and | |
5273 | --text-section-literals, and when several other obscure relaxation | |
5274 | conditions are met. */ | |
5275 | if (outputting_stabs_line_debug) | |
5276 | return; | |
5277 | ||
43cd72b9 BW |
5278 | if (cur_vinsn.inside_bundle) |
5279 | as_bad (_("missing closing brace")); | |
5280 | ||
e0001a05 NC |
5281 | /* If there is a non-zero instruction fragment, close it. */ |
5282 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5283 | { | |
5284 | frag_wane (frag_now); | |
5285 | frag_new (0); | |
43cd72b9 | 5286 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5287 | } |
5288 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5289 | |
5290 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5291 | } |
5292 | ||
5293 | ||
43cd72b9 BW |
5294 | /* We had an error while parsing an instruction. The string might look |
5295 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5296 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5297 | and the num_slots field will grow past the end of the array of slots, | |
5298 | and bad things happen. */ | |
5299 | ||
5300 | static void | |
7fa3d080 | 5301 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5302 | { |
5303 | if (cur_vinsn.inside_bundle) | |
5304 | { | |
5305 | if (*input_line_pointer == '}' | |
5306 | || *(input_line_pointer - 1) == '}' | |
5307 | || *(input_line_pointer - 2) == '}') | |
5308 | xg_clear_vinsn (&cur_vinsn); | |
5309 | } | |
5310 | } | |
5311 | ||
5312 | ||
e0001a05 | 5313 | void |
7fa3d080 | 5314 | md_assemble (char *str) |
e0001a05 NC |
5315 | { |
5316 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5317 | char *opname; |
e0001a05 NC |
5318 | unsigned opnamelen; |
5319 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5320 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5321 | int num_args; |
e0001a05 | 5322 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5323 | |
e0001a05 NC |
5324 | tinsn_init (&orig_insn); |
5325 | ||
5326 | /* Split off the opcode. */ | |
5327 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5328 | opname = xmalloc (opnamelen + 1); | |
5329 | memcpy (opname, str, opnamelen); | |
5330 | opname[opnamelen] = '\0'; | |
5331 | ||
5332 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5333 | if (num_args == -1) | |
5334 | { | |
5335 | as_bad (_("syntax error")); | |
5336 | return; | |
5337 | } | |
5338 | ||
5339 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5340 | return; | |
5341 | ||
5342 | /* Check for an underbar prefix. */ | |
5343 | if (*opname == '_') | |
5344 | { | |
5345 | has_underbar = TRUE; | |
5346 | opname += 1; | |
5347 | } | |
5348 | ||
5349 | orig_insn.insn_type = ITYPE_INSN; | |
5350 | orig_insn.ntok = 0; | |
43cd72b9 | 5351 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5352 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 BW |
5353 | |
5354 | /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its | |
5355 | extra argument and set the opcode to "CALLXn". */ | |
5356 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5357 | && strncasecmp (opname, "callx", 5) == 0) | |
5358 | { | |
5359 | unsigned long window_size; | |
5360 | char *suffix; | |
5361 | ||
5362 | window_size = strtoul (opname + 5, &suffix, 10); | |
5363 | if (suffix != opname + 5 | |
5364 | && (window_size == 0 | |
5365 | || window_size == 4 | |
5366 | || window_size == 8 | |
5367 | || window_size == 12) | |
5368 | && strcasecmp (suffix, ".tls") == 0) | |
5369 | { | |
5370 | switch (window_size) | |
5371 | { | |
5372 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5373 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5374 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5375 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5376 | } | |
5377 | ||
5378 | if (num_args != 2) | |
5379 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5380 | else | |
5381 | { | |
5382 | bfd_reloc_code_real_type reloc; | |
5383 | char *old_input_line_pointer; | |
19e8f41a | 5384 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5385 | segT t; |
5386 | ||
5387 | old_input_line_pointer = input_line_pointer; | |
5388 | input_line_pointer = arg_strings[num_args - 1]; | |
5389 | ||
5390 | t = expression (tok); | |
5391 | if (tok->X_op == O_symbol | |
5392 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5393 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5394 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5395 | else | |
5396 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5397 | ||
5398 | input_line_pointer = old_input_line_pointer; | |
5399 | num_args -= 1; | |
5400 | } | |
5401 | } | |
5402 | } | |
5403 | ||
19e8f41a BW |
5404 | /* Special case: Check for "j.l" psuedo op. */ |
5405 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5406 | && strncasecmp (opname, "j.l", 3) == 0) | |
5407 | { | |
5408 | if (num_args != 2) | |
5409 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5410 | else | |
5411 | { | |
5412 | char *old_input_line_pointer; | |
5413 | expressionS *tok = &orig_insn.extra_arg; | |
5414 | ||
5415 | old_input_line_pointer = input_line_pointer; | |
5416 | input_line_pointer = arg_strings[num_args - 1]; | |
5417 | ||
5418 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5419 | input_line_pointer = old_input_line_pointer; | |
5420 | ||
5421 | num_args -= 1; | |
5422 | orig_insn.opcode = xtensa_j_opcode; | |
5423 | } | |
5424 | } | |
5425 | ||
e0001a05 NC |
5426 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5427 | { | |
43cd72b9 BW |
5428 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5429 | if (fmt == XTENSA_UNDEFINED) | |
5430 | { | |
5431 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5432 | error_reset_cur_vinsn (); | |
5433 | return; | |
5434 | } | |
5435 | if (!cur_vinsn.inside_bundle) | |
5436 | { | |
5437 | as_bad (_("format names only valid inside bundles")); | |
5438 | error_reset_cur_vinsn (); | |
5439 | return; | |
5440 | } | |
5441 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5442 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5443 | opname); | |
5444 | cur_vinsn.format = fmt; | |
5445 | free (has_underbar ? opname - 1 : opname); | |
5446 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5447 | return; |
5448 | } | |
5449 | ||
e0001a05 NC |
5450 | /* Parse the arguments. */ |
5451 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5452 | { | |
5453 | as_bad (_("syntax error")); | |
43cd72b9 | 5454 | error_reset_cur_vinsn (); |
e0001a05 NC |
5455 | return; |
5456 | } | |
5457 | ||
5458 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5459 | free (has_underbar ? opname - 1 : opname); | |
5460 | opname = 0; | |
5461 | while (num_args-- > 0) | |
5462 | free (arg_strings[num_args]); | |
5463 | ||
43cd72b9 BW |
5464 | /* Get expressions for invisible operands. */ |
5465 | if (get_invisible_operands (&orig_insn)) | |
5466 | { | |
5467 | error_reset_cur_vinsn (); | |
5468 | return; | |
5469 | } | |
5470 | ||
e0001a05 NC |
5471 | /* Check for the right number and type of arguments. */ |
5472 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5473 | { |
43cd72b9 BW |
5474 | error_reset_cur_vinsn (); |
5475 | return; | |
e0001a05 NC |
5476 | } |
5477 | ||
b224e962 BW |
5478 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5479 | spread across multiple input lines and individual instructions may be | |
5480 | moved around in some cases. */ | |
5481 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5482 | dwarf2_where (&orig_insn.debug_line); | |
5483 | dwarf2_consume_line_info (); | |
c138bc38 | 5484 | |
43cd72b9 BW |
5485 | xg_add_branch_and_loop_targets (&orig_insn); |
5486 | ||
431ad2d0 BW |
5487 | /* Check that immediate value for ENTRY is >= 16. */ |
5488 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5489 | { |
431ad2d0 BW |
5490 | expressionS *exp = &orig_insn.tok[2]; |
5491 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5492 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5493 | } |
5494 | ||
e0001a05 | 5495 | /* Finish it off: |
43cd72b9 BW |
5496 | assemble_tokens (opcode, tok, ntok); |
5497 | expand the tokens from the orig_insn into the | |
5498 | stack of instructions that will not expand | |
e0001a05 | 5499 | unless required at relaxation time. */ |
e0001a05 | 5500 | |
43cd72b9 BW |
5501 | if (!cur_vinsn.inside_bundle) |
5502 | emit_single_op (&orig_insn); | |
5503 | else /* We are inside a bundle. */ | |
e0001a05 | 5504 | { |
43cd72b9 BW |
5505 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5506 | cur_vinsn.num_slots++; | |
5507 | if (*input_line_pointer == '}' | |
5508 | || *(input_line_pointer - 1) == '}' | |
5509 | || *(input_line_pointer - 2) == '}') | |
5510 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5511 | } |
5512 | ||
43cd72b9 BW |
5513 | /* We've just emitted a new instruction so clear the list of labels. */ |
5514 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5515 | } |
5516 | ||
5517 | ||
43cd72b9 | 5518 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5519 | |
43cd72b9 BW |
5520 | /* For a .align directive, we mark the previous block with the alignment |
5521 | information. This will be placed in the object file in the | |
5522 | property section corresponding to this section. */ | |
e0001a05 | 5523 | |
43cd72b9 | 5524 | void |
7fa3d080 | 5525 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5526 | { |
5527 | if (linkrelax | |
b08b5071 | 5528 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5529 | && (fragP->fr_type == rs_align |
5530 | || fragP->fr_type == rs_align_code) | |
5531 | && fragP->fr_address + fragP->fr_fix > 0 | |
5532 | && fragP->fr_offset > 0 | |
5533 | && now_seg != bss_section) | |
e0001a05 | 5534 | { |
43cd72b9 BW |
5535 | fragP->tc_frag_data.is_align = TRUE; |
5536 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5537 | } |
5538 | ||
43cd72b9 | 5539 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5540 | { |
43cd72b9 BW |
5541 | int count; |
5542 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5543 | if (count != 0) | |
c138bc38 | 5544 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5545 | _("unaligned entry instruction")); |
e0001a05 | 5546 | } |
99ded152 BW |
5547 | |
5548 | if (linkrelax && fragP->fr_type == rs_org) | |
5549 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5550 | } |
43cd72b9 | 5551 | |
e0001a05 NC |
5552 | |
5553 | /* TC_FRAG_INIT hook */ | |
5554 | ||
5555 | void | |
7fa3d080 | 5556 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5557 | { |
43cd72b9 | 5558 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5559 | } |
5560 | ||
5561 | ||
5562 | symbolS * | |
7fa3d080 | 5563 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5564 | { |
5565 | return NULL; | |
5566 | } | |
5567 | ||
5568 | ||
5569 | /* Round up a section size to the appropriate boundary. */ | |
5570 | ||
5571 | valueT | |
7fa3d080 | 5572 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5573 | { |
5574 | return size; /* Byte alignment is fine. */ | |
5575 | } | |
5576 | ||
5577 | ||
5578 | long | |
7fa3d080 | 5579 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5580 | { |
5581 | char *insn_p; | |
5582 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5583 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5584 | int opnum; |
43cd72b9 | 5585 | uint32 opnd_value; |
e0001a05 | 5586 | xtensa_opcode opcode; |
43cd72b9 BW |
5587 | xtensa_format fmt; |
5588 | int slot; | |
e0001a05 NC |
5589 | xtensa_isa isa = xtensa_default_isa; |
5590 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5591 | bfd_boolean alt_reloc; |
e0001a05 | 5592 | |
e0001a05 | 5593 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5594 | return 0; |
e0001a05 | 5595 | |
1bbb5f21 BW |
5596 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5597 | return addr; | |
5598 | ||
e0001a05 | 5599 | if (!insnbuf) |
43cd72b9 BW |
5600 | { |
5601 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5602 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5603 | } | |
e0001a05 NC |
5604 | |
5605 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5606 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5607 | fmt = xtensa_format_decode (isa, insnbuf); |
5608 | ||
5609 | if (fmt == XTENSA_UNDEFINED) | |
5610 | as_fatal (_("bad instruction format")); | |
5611 | ||
5612 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5613 | as_fatal (_("invalid relocation")); | |
5614 | ||
5615 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5616 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5617 | ||
30f725a1 BW |
5618 | /* Check for "alternate" relocations (operand not specified). None |
5619 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5620 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5621 | { | |
5622 | if (opcode != xtensa_l32r_opcode | |
5623 | && opcode != xtensa_const16_opcode) | |
5624 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5625 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5626 | return 0; |
e0001a05 NC |
5627 | } |
5628 | ||
43cd72b9 BW |
5629 | opnum = get_relaxable_immed (opcode); |
5630 | opnd_value = 0; | |
5631 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5632 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5633 | { |
5634 | as_bad_where (fixP->fx_file, | |
5635 | fixP->fx_line, | |
5636 | _("invalid relocation for operand %d of '%s'"), | |
5637 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5638 | return 0; |
e0001a05 | 5639 | } |
43cd72b9 BW |
5640 | return 0 - opnd_value; |
5641 | } | |
5642 | ||
5643 | ||
5644 | /* TC_FORCE_RELOCATION hook */ | |
5645 | ||
5646 | int | |
7fa3d080 | 5647 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5648 | { |
5649 | switch (fix->fx_r_type) | |
30f725a1 BW |
5650 | { |
5651 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5652 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5653 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5654 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5655 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5656 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5657 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5658 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5659 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5660 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5661 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5662 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5663 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5664 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5665 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5666 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5667 | return 1; |
5668 | default: | |
5669 | break; | |
e0001a05 NC |
5670 | } |
5671 | ||
43cd72b9 BW |
5672 | if (linkrelax && fix->fx_addsy |
5673 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5674 | return 1; | |
5675 | ||
5676 | return generic_force_reloc (fix); | |
5677 | } | |
5678 | ||
5679 | ||
30f725a1 BW |
5680 | /* TC_VALIDATE_FIX_SUB hook */ |
5681 | ||
5682 | int | |
5683 | xtensa_validate_fix_sub (fixS *fix) | |
5684 | { | |
5685 | segT add_symbol_segment, sub_symbol_segment; | |
5686 | ||
5687 | /* The difference of two symbols should be resolved by the assembler when | |
5688 | linkrelax is not set. If the linker may relax the section containing | |
5689 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5690 | the linker knows to adjust the difference value. */ | |
5691 | if (!linkrelax || fix->fx_addsy == NULL) | |
5692 | return 0; | |
5693 | ||
5694 | /* Make sure both symbols are in the same segment, and that segment is | |
5695 | "normal" and relaxable. If the segment is not "normal", then the | |
5696 | fix is not valid. If the segment is not "relaxable", then the fix | |
5697 | should have been handled earlier. */ | |
5698 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5699 | if (! SEG_NORMAL (add_symbol_segment) || | |
5700 | ! relaxable_section (add_symbol_segment)) | |
5701 | return 0; | |
5702 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5703 | return (sub_symbol_segment == add_symbol_segment); | |
5704 | } | |
5705 | ||
5706 | ||
43cd72b9 BW |
5707 | /* NO_PSEUDO_DOT hook */ |
5708 | ||
5709 | /* This function has nothing to do with pseudo dots, but this is the | |
5710 | nearest macro to where the check needs to take place. FIXME: This | |
5711 | seems wrong. */ | |
5712 | ||
5713 | bfd_boolean | |
7fa3d080 | 5714 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5715 | { |
5716 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5717 | as_bad (_("directives are not valid inside bundles")); | |
5718 | ||
5719 | /* This function must always return FALSE because it is called via a | |
5720 | macro that has nothing to do with bundling. */ | |
5721 | return FALSE; | |
e0001a05 NC |
5722 | } |
5723 | ||
5724 | ||
43cd72b9 | 5725 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5726 | |
5727 | void | |
7fa3d080 | 5728 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5729 | { |
43cd72b9 BW |
5730 | /* Set up the assembly state. */ |
5731 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5732 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5733 | } |
5734 | ||
5735 | ||
5736 | /* tc_fix_adjustable hook */ | |
5737 | ||
5738 | bfd_boolean | |
7fa3d080 | 5739 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5740 | { |
43cd72b9 BW |
5741 | /* An offset is not allowed in combination with the difference of two |
5742 | symbols, but that cannot be easily detected after a local symbol | |
5743 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5744 | an fix will not be adjusted. */ | |
5745 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5746 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5747 | return 0; | |
5748 | ||
e0001a05 NC |
5749 | /* We need the symbol name for the VTABLE entries. */ |
5750 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5751 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5752 | return 0; | |
5753 | ||
5754 | return 1; | |
5755 | } | |
5756 | ||
5757 | ||
6a7eedfe BW |
5758 | /* tc_symbol_new_hook */ |
5759 | ||
5760 | symbolS *expr_symbols = NULL; | |
5761 | ||
5762 | void | |
5763 | xtensa_symbol_new_hook (symbolS *sym) | |
5764 | { | |
fb227da0 | 5765 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5766 | { |
5767 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5768 | expr_symbols = sym; | |
5769 | } | |
5770 | } | |
5771 | ||
5772 | ||
e0001a05 | 5773 | void |
55cf6793 | 5774 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5775 | { |
30f725a1 | 5776 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5777 | valueT val = 0; |
30f725a1 | 5778 | |
e7da6241 BW |
5779 | /* Subtracted symbols are only allowed for a few relocation types, and |
5780 | unless linkrelax is enabled, they should not make it to this point. */ | |
5781 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5782 | || fixP->fx_r_type == BFD_RELOC_16 | |
5783 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5784 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5785 | ||
30f725a1 | 5786 | switch (fixP->fx_r_type) |
e0001a05 | 5787 | { |
1bbb5f21 | 5788 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5789 | case BFD_RELOC_32: |
5790 | case BFD_RELOC_16: | |
5791 | case BFD_RELOC_8: | |
e7da6241 | 5792 | if (fixP->fx_subsy) |
30f725a1 BW |
5793 | { |
5794 | switch (fixP->fx_r_type) | |
5795 | { | |
5796 | case BFD_RELOC_8: | |
5797 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5798 | break; | |
5799 | case BFD_RELOC_16: | |
5800 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5801 | break; | |
5802 | case BFD_RELOC_32: | |
5803 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5804 | break; | |
5805 | default: | |
5806 | break; | |
5807 | } | |
e0001a05 | 5808 | |
30f725a1 BW |
5809 | /* An offset is only allowed when it results from adjusting a |
5810 | local symbol into a section-relative offset. If the offset | |
5811 | came from the original expression, tc_fix_adjustable will have | |
5812 | prevented the fix from being converted to a section-relative | |
5813 | form so that we can flag the error here. */ | |
5814 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5815 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5816 | _("cannot represent subtraction with an offset")); | |
5817 | ||
5818 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5819 | - S_GET_VALUE (fixP->fx_subsy)); | |
5820 | ||
5821 | /* The difference value gets written out, and the DIFF reloc | |
5822 | identifies the address of the subtracted symbol (i.e., the one | |
5823 | with the lowest address). */ | |
5824 | *valP = val; | |
5825 | fixP->fx_offset -= val; | |
5826 | fixP->fx_subsy = NULL; | |
5827 | } | |
5828 | else if (! fixP->fx_addsy) | |
e0001a05 | 5829 | { |
30f725a1 | 5830 | val = *valP; |
e0001a05 | 5831 | fixP->fx_done = 1; |
30f725a1 | 5832 | } |
d47d412e BW |
5833 | /* fall through */ |
5834 | ||
5835 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5836 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5837 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5838 | break; | |
e0001a05 | 5839 | |
28dbbc02 BW |
5840 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
5841 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
5842 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
5843 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
5844 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
5845 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
5846 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5847 | break; | |
5848 | ||
30f725a1 BW |
5849 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5850 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5851 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5852 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5853 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5854 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5855 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5856 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5857 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5858 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5859 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5860 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5861 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5862 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5863 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5864 | if (linkrelax) | |
5865 | { | |
5866 | /* Write the tentative value of a PC-relative relocation to a | |
5867 | local symbol into the instruction. The value will be ignored | |
5868 | by the linker, and it makes the object file disassembly | |
5869 | readable when all branch targets are encoded in relocations. */ | |
5870 | ||
5871 | assert (fixP->fx_addsy); | |
20ee54e8 | 5872 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5873 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5874 | { | |
5875 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5876 | - md_pcrel_from (fixP)); | |
5877 | (void) xg_apply_fix_value (fixP, val); | |
5878 | } | |
5879 | } | |
5880 | else if (! fixP->fx_addsy) | |
5881 | { | |
5882 | val = *valP; | |
5883 | if (xg_apply_fix_value (fixP, val)) | |
5884 | fixP->fx_done = 1; | |
5885 | } | |
5886 | break; | |
e0001a05 | 5887 | |
30f725a1 | 5888 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
5889 | case BFD_RELOC_XTENSA_TLS_FUNC: |
5890 | case BFD_RELOC_XTENSA_TLS_ARG: | |
5891 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
5892 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5893 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5894 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5895 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5896 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5897 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5898 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5899 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5900 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5901 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5902 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5903 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5904 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5905 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5906 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5907 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5908 | break; | |
e0001a05 | 5909 | |
30f725a1 BW |
5910 | case BFD_RELOC_VTABLE_INHERIT: |
5911 | case BFD_RELOC_VTABLE_ENTRY: | |
5912 | fixP->fx_done = 0; | |
5913 | break; | |
e0001a05 | 5914 | |
30f725a1 BW |
5915 | default: |
5916 | as_bad (_("unhandled local relocation fix %s"), | |
5917 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5918 | } |
5919 | } | |
5920 | ||
5921 | ||
5922 | char * | |
7fa3d080 | 5923 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5924 | { |
499ac353 | 5925 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5926 | } |
5927 | ||
5928 | ||
5929 | int | |
7fa3d080 | 5930 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5931 | { |
34e41783 | 5932 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5933 | } |
5934 | ||
5935 | ||
5936 | /* Translate internal representation of relocation info to BFD target | |
5937 | format. */ | |
5938 | ||
5939 | arelent * | |
30f725a1 | 5940 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5941 | { |
5942 | arelent *reloc; | |
5943 | ||
5944 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5945 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5946 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5947 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5948 | ||
5949 | /* Make sure none of our internal relocations make it this far. | |
5950 | They'd better have been fully resolved by this point. */ | |
5951 | assert ((int) fixp->fx_r_type > 0); | |
5952 | ||
30f725a1 | 5953 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5954 | |
e0001a05 NC |
5955 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5956 | if (reloc->howto == NULL) | |
5957 | { | |
5958 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5959 | _("cannot represent `%s' relocation in object file"), | |
5960 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5961 | free (reloc->sym_ptr_ptr); |
5962 | free (reloc); | |
e0001a05 NC |
5963 | return NULL; |
5964 | } | |
5965 | ||
5966 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 5967 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 5968 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 5969 | |
e0001a05 NC |
5970 | return reloc; |
5971 | } | |
5972 | ||
7fa3d080 BW |
5973 | \f |
5974 | /* Checks for resource conflicts between instructions. */ | |
5975 | ||
c138bc38 BW |
5976 | /* The func unit stuff could be implemented as bit-vectors rather |
5977 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5978 | slow, we will switch it. */ |
5979 | ||
c138bc38 | 5980 | resource_table * |
7fa3d080 BW |
5981 | new_resource_table (void *data, |
5982 | int cycles, | |
5983 | int nu, | |
5984 | unit_num_copies_func uncf, | |
5985 | opcode_num_units_func onuf, | |
5986 | opcode_funcUnit_use_unit_func ouuf, | |
5987 | opcode_funcUnit_use_stage_func ousf) | |
5988 | { | |
5989 | int i; | |
5990 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5991 | rt->data = data; | |
5992 | rt->cycles = cycles; | |
5993 | rt->allocated_cycles = cycles; | |
5994 | rt->num_units = nu; | |
5995 | rt->unit_num_copies = uncf; | |
5996 | rt->opcode_num_units = onuf; | |
5997 | rt->opcode_unit_use = ouuf; | |
5998 | rt->opcode_unit_stage = ousf; | |
5999 | ||
0bf60745 | 6000 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 6001 | for (i = 0; i < cycles; i++) |
0bf60745 | 6002 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
6003 | |
6004 | return rt; | |
6005 | } | |
6006 | ||
6007 | ||
c138bc38 | 6008 | void |
7fa3d080 BW |
6009 | clear_resource_table (resource_table *rt) |
6010 | { | |
6011 | int i, j; | |
6012 | for (i = 0; i < rt->allocated_cycles; i++) | |
6013 | for (j = 0; j < rt->num_units; j++) | |
6014 | rt->units[i][j] = 0; | |
6015 | } | |
6016 | ||
6017 | ||
6018 | /* We never shrink it, just fake it into thinking so. */ | |
6019 | ||
c138bc38 | 6020 | void |
7fa3d080 BW |
6021 | resize_resource_table (resource_table *rt, int cycles) |
6022 | { | |
6023 | int i, old_cycles; | |
6024 | ||
6025 | rt->cycles = cycles; | |
6026 | if (cycles <= rt->allocated_cycles) | |
6027 | return; | |
6028 | ||
6029 | old_cycles = rt->allocated_cycles; | |
6030 | rt->allocated_cycles = cycles; | |
6031 | ||
0bf60745 BW |
6032 | rt->units = xrealloc (rt->units, |
6033 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 6034 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
6035 | rt->units[i] = xrealloc (rt->units[i], |
6036 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 6037 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 6038 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
6039 | } |
6040 | ||
6041 | ||
c138bc38 | 6042 | bfd_boolean |
7fa3d080 BW |
6043 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6044 | { | |
6045 | int i; | |
6046 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6047 | ||
c138bc38 | 6048 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6049 | { |
6050 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6051 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6052 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6053 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6054 | if (copies_in_use >= copies) | |
6055 | return FALSE; | |
6056 | } | |
6057 | return TRUE; | |
6058 | } | |
7fa3d080 | 6059 | |
c138bc38 BW |
6060 | |
6061 | void | |
7fa3d080 BW |
6062 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6063 | { | |
6064 | int i; | |
6065 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6066 | ||
c138bc38 | 6067 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6068 | { |
6069 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6070 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6071 | /* Note that this allows resources to be oversubscribed. That's |
6072 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6073 | resources_available reports when a resource is over-subscribed, |
6074 | so it's easy to tell. */ | |
6075 | rt->units[stage + cycle][unit]++; | |
6076 | } | |
6077 | } | |
6078 | ||
6079 | ||
c138bc38 | 6080 | void |
7fa3d080 BW |
6081 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6082 | { | |
6083 | int i; | |
6084 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6085 | ||
c138bc38 | 6086 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6087 | { |
6088 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6089 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 6090 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6091 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6092 | } |
6093 | } | |
c138bc38 | 6094 | |
7fa3d080 BW |
6095 | |
6096 | /* Wrapper functions make parameterized resource reservation | |
6097 | more convenient. */ | |
6098 | ||
c138bc38 | 6099 | int |
7fa3d080 BW |
6100 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6101 | { | |
6102 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6103 | return use->unit; |
7fa3d080 BW |
6104 | } |
6105 | ||
6106 | ||
c138bc38 | 6107 | int |
7fa3d080 BW |
6108 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6109 | { | |
6110 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6111 | return use->stage; | |
6112 | } | |
6113 | ||
6114 | ||
6115 | /* Note that this function does not check issue constraints, but | |
6116 | solely whether the hardware is available to execute the given | |
c138bc38 | 6117 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6118 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6119 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6120 | |
6121 | static bfd_boolean | |
6122 | resources_conflict (vliw_insn *vinsn) | |
6123 | { | |
6124 | int i; | |
6125 | static resource_table *rt = NULL; | |
6126 | ||
6127 | /* This is the most common case by far. Optimize it. */ | |
6128 | if (vinsn->num_slots == 1) | |
6129 | return FALSE; | |
43cd72b9 | 6130 | |
c138bc38 | 6131 | if (rt == NULL) |
7fa3d080 BW |
6132 | { |
6133 | xtensa_isa isa = xtensa_default_isa; | |
6134 | rt = new_resource_table | |
77cba8a3 | 6135 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6136 | xtensa_isa_num_funcUnits (isa), |
6137 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6138 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6139 | opcode_funcUnit_use_unit, | |
6140 | opcode_funcUnit_use_stage); | |
6141 | } | |
43cd72b9 | 6142 | |
7fa3d080 | 6143 | clear_resource_table (rt); |
43cd72b9 | 6144 | |
7fa3d080 BW |
6145 | for (i = 0; i < vinsn->num_slots; i++) |
6146 | { | |
6147 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6148 | return TRUE; | |
6149 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6150 | } | |
e0001a05 | 6151 | |
7fa3d080 BW |
6152 | return FALSE; |
6153 | } | |
e0001a05 | 6154 | |
7fa3d080 BW |
6155 | \f |
6156 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6157 | |
7fa3d080 BW |
6158 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6159 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6160 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6161 | |
6162 | ||
43cd72b9 BW |
6163 | /* We have reached the end of a bundle; emit into the frag. */ |
6164 | ||
e0001a05 | 6165 | static void |
7fa3d080 | 6166 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6167 | { |
43cd72b9 BW |
6168 | IStack slotstack; |
6169 | int i; | |
6170 | char *file_name; | |
d77b99c9 | 6171 | unsigned line; |
e0001a05 | 6172 | |
43cd72b9 | 6173 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6174 | { |
6175 | xg_clear_vinsn (vinsn); | |
6176 | return; | |
6177 | } | |
43cd72b9 BW |
6178 | |
6179 | /* First, find a format that works. */ | |
6180 | if (vinsn->format == XTENSA_UNDEFINED) | |
6181 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6182 | ||
6183 | if (vinsn->format == XTENSA_UNDEFINED) | |
6184 | { | |
6185 | as_where (&file_name, &line); | |
6186 | as_bad_where (file_name, line, | |
6187 | _("couldn't find a valid instruction format")); | |
6188 | fprintf (stderr, _(" ops were: ")); | |
6189 | for (i = 0; i < vinsn->num_slots; i++) | |
6190 | fprintf (stderr, _(" %s;"), | |
6191 | xtensa_opcode_name (xtensa_default_isa, | |
6192 | vinsn->slots[i].opcode)); | |
6193 | fprintf (stderr, _("\n")); | |
6194 | xg_clear_vinsn (vinsn); | |
6195 | return; | |
6196 | } | |
6197 | ||
6198 | if (vinsn->num_slots | |
6199 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6200 | { |
43cd72b9 BW |
6201 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6202 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6203 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6204 | vinsn->num_slots); | |
6205 | xg_clear_vinsn (vinsn); | |
6206 | return; | |
6207 | } | |
e0001a05 | 6208 | |
c138bc38 | 6209 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6210 | { |
6211 | as_where (&file_name, &line); | |
6212 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6213 | fprintf (stderr, " ops were: "); | |
6214 | for (i = 0; i < vinsn->num_slots; i++) | |
6215 | fprintf (stderr, " %s;", | |
6216 | xtensa_opcode_name (xtensa_default_isa, | |
6217 | vinsn->slots[i].opcode)); | |
6218 | fprintf (stderr, "\n"); | |
6219 | xg_clear_vinsn (vinsn); | |
6220 | return; | |
6221 | } | |
6222 | ||
6223 | for (i = 0; i < vinsn->num_slots; i++) | |
6224 | { | |
6225 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6226 | { |
43cd72b9 BW |
6227 | symbolS *lit_sym = NULL; |
6228 | int j; | |
6229 | bfd_boolean e = FALSE; | |
6230 | bfd_boolean saved_density = density_supported; | |
6231 | ||
6232 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6233 | if (vinsn->num_slots > 1) | |
6234 | density_supported = FALSE; | |
6235 | ||
6236 | istack_init (&slotstack); | |
6237 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6238 | { |
43cd72b9 BW |
6239 | vinsn->slots[i].opcode = |
6240 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6241 | vinsn->format, i); | |
6242 | vinsn->slots[i].ntok = 0; | |
6243 | } | |
e0001a05 | 6244 | |
43cd72b9 BW |
6245 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6246 | { | |
6247 | e = TRUE; | |
6248 | continue; | |
e0001a05 | 6249 | } |
e0001a05 | 6250 | |
43cd72b9 | 6251 | density_supported = saved_density; |
e0001a05 | 6252 | |
43cd72b9 BW |
6253 | if (e) |
6254 | { | |
6255 | xg_clear_vinsn (vinsn); | |
6256 | return; | |
6257 | } | |
e0001a05 | 6258 | |
0fa77c95 | 6259 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6260 | { |
6261 | TInsn *insn = &slotstack.insn[j]; | |
6262 | if (insn->insn_type == ITYPE_LITERAL) | |
6263 | { | |
6264 | assert (lit_sym == NULL); | |
6265 | lit_sym = xg_assemble_literal (insn); | |
6266 | } | |
6267 | else | |
6268 | { | |
0fa77c95 | 6269 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6270 | if (lit_sym) |
6271 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6272 | if (j != slotstack.ninsn - 1) |
6273 | emit_single_op (insn); | |
43cd72b9 BW |
6274 | } |
6275 | } | |
6276 | ||
6277 | if (vinsn->num_slots > 1) | |
6278 | { | |
6279 | if (opcode_fits_format_slot | |
6280 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6281 | vinsn->format, i)) | |
6282 | { | |
6283 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6284 | } | |
6285 | else | |
6286 | { | |
b2d179be | 6287 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6288 | if (vinsn->format == XTENSA_UNDEFINED) |
6289 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6290 | else | |
c138bc38 | 6291 | vinsn->slots[i].opcode |
43cd72b9 BW |
6292 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6293 | vinsn->format, i); | |
6294 | ||
6295 | vinsn->slots[i].ntok = 0; | |
6296 | } | |
6297 | } | |
6298 | else | |
6299 | { | |
6300 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6301 | vinsn->format = XTENSA_UNDEFINED; | |
6302 | } | |
6303 | } | |
6304 | } | |
6305 | ||
6306 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6307 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6308 | { |
6309 | as_where (&file_name, &line); | |
6310 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6311 | fprintf (stderr, " ops were: "); | |
6312 | for (i = 0; i < vinsn->num_slots; i++) | |
6313 | fprintf (stderr, " %s;", | |
6314 | xtensa_opcode_name (xtensa_default_isa, | |
6315 | vinsn->slots[i].opcode)); | |
6316 | fprintf (stderr, "\n"); | |
6317 | xg_clear_vinsn (vinsn); | |
6318 | return; | |
6319 | } | |
6320 | ||
6321 | /* First, find a format that works. */ | |
6322 | if (vinsn->format == XTENSA_UNDEFINED) | |
6323 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6324 | ||
6325 | xg_assemble_vliw_tokens (vinsn); | |
6326 | ||
6327 | xg_clear_vinsn (vinsn); | |
6328 | } | |
6329 | ||
6330 | ||
6331 | /* Given an vliw instruction, what conflicts are there in register | |
6332 | usage and in writes to states and queues? | |
6333 | ||
6334 | This function does two things: | |
6335 | 1. Reports an error when a vinsn contains illegal combinations | |
6336 | of writes to registers states or queues. | |
6337 | 2. Marks individual tinsns as not relaxable if the combination | |
6338 | contains antidependencies. | |
6339 | ||
6340 | Job 2 handles things like swap semantics in instructions that need | |
6341 | to be relaxed. For example, | |
6342 | ||
6343 | addi a0, a1, 100000 | |
6344 | ||
6345 | normally would be relaxed to | |
6346 | ||
6347 | l32r a0, some_label | |
6348 | add a0, a1, a0 | |
6349 | ||
6350 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6351 | ||
6352 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6353 | ||
6354 | then we can't relax it into | |
6355 | ||
6356 | l32r a0, some_label | |
6357 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6358 | ||
6359 | because the value of a0 is trashed before the second add can read it. */ | |
6360 | ||
7fa3d080 BW |
6361 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6362 | ||
43cd72b9 | 6363 | static bfd_boolean |
7fa3d080 | 6364 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6365 | { |
6366 | int i, j; | |
6367 | int branches = 0; | |
6368 | xtensa_isa isa = xtensa_default_isa; | |
6369 | ||
6370 | assert (!past_xtensa_end); | |
6371 | ||
6372 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6373 | { | |
6374 | TInsn *op1 = &vinsn->slots[i]; | |
6375 | if (op1->is_specific_opcode) | |
6376 | op1->keep_wide = TRUE; | |
6377 | else | |
6378 | op1->keep_wide = FALSE; | |
6379 | } | |
6380 | ||
6381 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6382 | { | |
6383 | TInsn *op1 = &vinsn->slots[i]; | |
6384 | ||
6385 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6386 | branches++; | |
6387 | ||
6388 | for (j = 0; j < vinsn->num_slots; j++) | |
6389 | { | |
6390 | if (i != j) | |
6391 | { | |
6392 | TInsn *op2 = &vinsn->slots[j]; | |
6393 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6394 | switch (conflict_type) | |
6395 | { | |
6396 | case 'c': | |
6397 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6398 | xtensa_opcode_name (isa, op1->opcode), i, | |
6399 | xtensa_opcode_name (isa, op2->opcode), j); | |
6400 | return TRUE; | |
6401 | case 'd': | |
6402 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6403 | xtensa_opcode_name (isa, op1->opcode), i, | |
6404 | xtensa_opcode_name (isa, op2->opcode), j); | |
6405 | return TRUE; | |
6406 | case 'e': | |
53dfbcc7 | 6407 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6408 | xtensa_opcode_name (isa, op1->opcode), i, |
6409 | xtensa_opcode_name (isa, op2->opcode), j); | |
6410 | return TRUE; | |
6411 | case 'f': | |
53dfbcc7 | 6412 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6413 | xtensa_opcode_name (isa, op1->opcode), i, |
6414 | xtensa_opcode_name (isa, op2->opcode), j); | |
6415 | return TRUE; | |
6416 | default: | |
6417 | /* Everything is OK. */ | |
6418 | break; | |
6419 | } | |
6420 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6421 | || conflict_type == 'a'); | |
6422 | } | |
6423 | } | |
6424 | } | |
6425 | ||
6426 | if (branches > 1) | |
6427 | { | |
6428 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6429 | return TRUE; | |
6430 | } | |
6431 | ||
6432 | return FALSE; | |
6433 | } | |
6434 | ||
6435 | ||
a1ace8d8 | 6436 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6437 | Cases found are: |
6438 | ||
6439 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6440 | case B: no relationship between what is read and written (both could | |
6441 | read the same reg though) | |
c138bc38 | 6442 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6443 | bundle) |
6444 | case D: t1 writes a state that t2 also writes | |
6445 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6446 | case F: two volatile queue accesses |
43cd72b9 BW |
6447 | */ |
6448 | ||
6449 | static char | |
7fa3d080 | 6450 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6451 | { |
6452 | xtensa_isa isa = xtensa_default_isa; | |
6453 | xtensa_regfile t1_regfile, t2_regfile; | |
6454 | int t1_reg, t2_reg; | |
6455 | int t1_base_reg, t1_last_reg; | |
6456 | int t2_base_reg, t2_last_reg; | |
6457 | char t1_inout, t2_inout; | |
6458 | int i, j; | |
6459 | char conflict = 'b'; | |
6460 | int t1_states; | |
6461 | int t2_states; | |
6462 | int t1_interfaces; | |
6463 | int t2_interfaces; | |
6464 | bfd_boolean t1_volatile = FALSE; | |
6465 | bfd_boolean t2_volatile = FALSE; | |
6466 | ||
6467 | /* Check registers. */ | |
6468 | for (j = 0; j < t2->ntok; j++) | |
6469 | { | |
6470 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6471 | continue; | |
6472 | ||
6473 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6474 | t2_base_reg = t2->tok[j].X_add_number; | |
6475 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6476 | ||
6477 | for (i = 0; i < t1->ntok; i++) | |
6478 | { | |
6479 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6480 | continue; | |
6481 | ||
6482 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6483 | ||
6484 | if (t1_regfile != t2_regfile) | |
6485 | continue; | |
6486 | ||
6487 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6488 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6489 | ||
6490 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6491 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6492 | { | |
6493 | if (t1_inout == 'm' || t1_inout == 'o' | |
6494 | || t2_inout == 'm' || t2_inout == 'o') | |
6495 | { | |
6496 | conflict = 'a'; | |
6497 | continue; | |
6498 | } | |
6499 | } | |
6500 | ||
6501 | t1_base_reg = t1->tok[i].X_add_number; | |
6502 | t1_last_reg = (t1_base_reg | |
6503 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6504 | ||
6505 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6506 | { | |
6507 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6508 | { | |
6509 | if (t1_reg != t2_reg) | |
6510 | continue; | |
6511 | ||
6512 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6513 | { |
6514 | conflict = 'a'; | |
6515 | continue; | |
6516 | } | |
43cd72b9 | 6517 | |
7fa3d080 BW |
6518 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6519 | { | |
6520 | conflict = 'a'; | |
6521 | continue; | |
6522 | } | |
43cd72b9 | 6523 | |
7fa3d080 BW |
6524 | if (t1_inout != 'i' && t2_inout != 'i') |
6525 | return 'c'; | |
6526 | } | |
6527 | } | |
6528 | } | |
6529 | } | |
43cd72b9 | 6530 | |
7fa3d080 BW |
6531 | /* Check states. */ |
6532 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6533 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6534 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6535 | { |
7fa3d080 BW |
6536 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6537 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6538 | for (i = 0; i < t1_states; i++) | |
6539 | { | |
6540 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6541 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6542 | if (t1_so != t2_so) |
7fa3d080 | 6543 | continue; |
43cd72b9 | 6544 | |
7fa3d080 BW |
6545 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6546 | { | |
6547 | conflict = 'a'; | |
6548 | continue; | |
6549 | } | |
c138bc38 | 6550 | |
7fa3d080 BW |
6551 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6552 | { | |
6553 | conflict = 'a'; | |
6554 | continue; | |
6555 | } | |
c138bc38 | 6556 | |
7fa3d080 BW |
6557 | if (t1_inout != 'i' && t2_inout != 'i') |
6558 | return 'd'; | |
c138bc38 | 6559 | } |
7fa3d080 | 6560 | } |
43cd72b9 | 6561 | |
7fa3d080 BW |
6562 | /* Check tieports. */ |
6563 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6564 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6565 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6566 | { |
7fa3d080 BW |
6567 | xtensa_interface t2_int |
6568 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6569 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6570 | ||
53dfbcc7 | 6571 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6572 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6573 | t2_volatile = TRUE; |
a1ace8d8 | 6574 | |
7fa3d080 BW |
6575 | for (i = 0; i < t1_interfaces; i++) |
6576 | { | |
6577 | xtensa_interface t1_int | |
6578 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6579 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6580 | |
53dfbcc7 | 6581 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6582 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6583 | t1_volatile = TRUE; |
a1ace8d8 BW |
6584 | |
6585 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6586 | return 'f'; | |
c138bc38 | 6587 | |
7fa3d080 BW |
6588 | if (t1_int != t2_int) |
6589 | continue; | |
c138bc38 | 6590 | |
7fa3d080 BW |
6591 | if (t2_inout == 'i' && t1_inout == 'o') |
6592 | { | |
6593 | conflict = 'a'; | |
6594 | continue; | |
6595 | } | |
c138bc38 | 6596 | |
7fa3d080 BW |
6597 | if (t1_inout == 'i' && t2_inout == 'o') |
6598 | { | |
6599 | conflict = 'a'; | |
6600 | continue; | |
6601 | } | |
c138bc38 | 6602 | |
7fa3d080 BW |
6603 | if (t1_inout != 'i' && t2_inout != 'i') |
6604 | return 'e'; | |
6605 | } | |
43cd72b9 | 6606 | } |
c138bc38 | 6607 | |
7fa3d080 | 6608 | return conflict; |
43cd72b9 BW |
6609 | } |
6610 | ||
6611 | ||
6612 | static xtensa_format | |
7fa3d080 | 6613 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6614 | { |
6615 | /* Right now we assume that the ops within the vinsn are properly | |
6616 | ordered for the slots that the programmer wanted them in. In | |
6617 | other words, we don't rearrange the ops in hopes of finding a | |
6618 | better format. The scheduler handles that. */ | |
6619 | ||
6620 | xtensa_isa isa = xtensa_default_isa; | |
6621 | xtensa_format format; | |
6622 | vliw_insn v_copy = *vinsn; | |
6623 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6624 | ||
65738a7d BW |
6625 | if (vinsn->num_slots == 1) |
6626 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6627 | ||
43cd72b9 BW |
6628 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6629 | { | |
6630 | v_copy = *vinsn; | |
6631 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6632 | { | |
6633 | int slot; | |
6634 | int fit = 0; | |
6635 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6636 | { | |
6637 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6638 | { | |
6639 | v_copy.slots[slot].opcode = | |
6640 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6641 | v_copy.slots[slot].ntok = 0; | |
6642 | } | |
6643 | ||
6644 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6645 | format, slot)) | |
6646 | fit++; | |
7fa3d080 | 6647 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6648 | { |
7fa3d080 BW |
6649 | TInsn widened; |
6650 | /* Try the widened version. */ | |
6651 | if (!v_copy.slots[slot].keep_wide | |
6652 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6653 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6654 | &widened, TRUE) | |
7fa3d080 BW |
6655 | && opcode_fits_format_slot (widened.opcode, |
6656 | format, slot)) | |
43cd72b9 | 6657 | { |
7fa3d080 BW |
6658 | v_copy.slots[slot] = widened; |
6659 | fit++; | |
43cd72b9 BW |
6660 | } |
6661 | } | |
6662 | } | |
6663 | if (fit == v_copy.num_slots) | |
6664 | { | |
6665 | *vinsn = v_copy; | |
6666 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6667 | vinsn->format = format; | |
6668 | break; | |
6669 | } | |
6670 | } | |
6671 | } | |
6672 | ||
6673 | if (format == xtensa_isa_num_formats (isa)) | |
6674 | return XTENSA_UNDEFINED; | |
6675 | ||
6676 | return format; | |
6677 | } | |
6678 | ||
6679 | ||
6680 | /* Return the additional space needed in a frag | |
6681 | for possible relaxations of any ops in a VLIW insn. | |
6682 | Also fill out the relaxations that might be required of | |
6683 | each tinsn in the vinsn. */ | |
6684 | ||
6685 | static int | |
e7da6241 | 6686 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6687 | { |
e7da6241 | 6688 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6689 | int extra_space = 0; |
6690 | int slot; | |
6691 | ||
6692 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6693 | { | |
6694 | TInsn *tinsn = &vinsn->slots[slot]; | |
6695 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6696 | { | |
6697 | /* A narrow instruction could be widened later to help | |
6698 | alignment issues. */ | |
84b08ed9 | 6699 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6700 | && !tinsn->is_specific_opcode |
6701 | && vinsn->num_slots == 1) | |
6702 | { | |
6703 | /* Difference in bytes between narrow and wide insns... */ | |
6704 | extra_space += 1; | |
6705 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6706 | } |
6707 | } | |
6708 | else | |
6709 | { | |
b08b5071 BW |
6710 | if (workaround_b_j_loop_end |
6711 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6712 | && use_transform ()) |
6713 | { | |
6714 | /* Add 2 of these. */ | |
6715 | extra_space += 3; /* for the nop size */ | |
6716 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6717 | } | |
c138bc38 | 6718 | |
43cd72b9 BW |
6719 | /* Need to assemble it with space for the relocation. */ |
6720 | if (xg_is_relaxable_insn (tinsn, 0) | |
6721 | && !tinsn->is_specific_opcode) | |
6722 | { | |
6723 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6724 | int max_literal_size = | |
6725 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6726 | |
43cd72b9 | 6727 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6728 | |
43cd72b9 | 6729 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6730 | extra_space += max_size; |
6731 | } | |
6732 | else | |
6733 | { | |
e7da6241 BW |
6734 | /* A fix record will be added for this instruction prior |
6735 | to relaxation, so make it end the frag. */ | |
6736 | finish_frag = TRUE; | |
43cd72b9 BW |
6737 | } |
6738 | } | |
6739 | } | |
e7da6241 | 6740 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6741 | return extra_space; |
6742 | } | |
6743 | ||
6744 | ||
6745 | static void | |
b2d179be | 6746 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6747 | { |
6748 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6749 | int slot, chosen_slot; |
43cd72b9 | 6750 | |
b2d179be BW |
6751 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6752 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6753 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6754 | |
b2d179be BW |
6755 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6756 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6757 | { |
b2d179be BW |
6758 | if (slot == chosen_slot) |
6759 | vinsn->slots[slot] = *tinsn; | |
6760 | else | |
6761 | { | |
6762 | vinsn->slots[slot].opcode = | |
6763 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6764 | vinsn->slots[slot].ntok = 0; | |
6765 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6766 | } | |
43cd72b9 | 6767 | } |
43cd72b9 BW |
6768 | } |
6769 | ||
6770 | ||
6771 | static bfd_boolean | |
7fa3d080 | 6772 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6773 | { |
6774 | int i; | |
6775 | IStack istack; /* put instructions into here */ | |
6776 | symbolS *lit_sym = NULL; | |
6777 | symbolS *label_sym = NULL; | |
6778 | ||
6779 | istack_init (&istack); | |
6780 | ||
6781 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6782 | Because the scheduling and bundling characteristics of movi and |
6783 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6784 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6785 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6786 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6787 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6788 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6789 | || orig_insn->tok[1].X_op == O_pltrel |
6790 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6791 | || orig_insn->tok[1].X_op == O_tlsarg | |
6792 | || orig_insn->tok[1].X_op == O_tpoff | |
6793 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6794 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6795 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6796 | else | |
6797 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6798 | return TRUE; | |
6799 | ||
6800 | for (i = 0; i < istack.ninsn; i++) | |
6801 | { | |
6802 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6803 | switch (insn->insn_type) |
43cd72b9 BW |
6804 | { |
6805 | case ITYPE_LITERAL: | |
6806 | assert (lit_sym == NULL); | |
6807 | lit_sym = xg_assemble_literal (insn); | |
6808 | break; | |
6809 | case ITYPE_LABEL: | |
6810 | { | |
6811 | static int relaxed_sym_idx = 0; | |
6812 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6813 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6814 | colon (label); | |
6815 | assert (label_sym == NULL); | |
6816 | label_sym = symbol_find_or_make (label); | |
6817 | assert (label_sym); | |
6818 | free (label); | |
6819 | } | |
6820 | break; | |
6821 | case ITYPE_INSN: | |
b2d179be BW |
6822 | { |
6823 | vliw_insn v; | |
6824 | if (lit_sym) | |
6825 | xg_resolve_literals (insn, lit_sym); | |
6826 | if (label_sym) | |
6827 | xg_resolve_labels (insn, label_sym); | |
6828 | xg_init_vinsn (&v); | |
6829 | bundle_tinsn (insn, &v); | |
6830 | finish_vinsn (&v); | |
6831 | xg_free_vinsn (&v); | |
6832 | } | |
43cd72b9 BW |
6833 | break; |
6834 | default: | |
6835 | assert (0); | |
6836 | break; | |
6837 | } | |
6838 | } | |
6839 | return FALSE; | |
6840 | } | |
6841 | ||
6842 | ||
34e41783 BW |
6843 | static int |
6844 | total_frag_text_expansion (fragS *fragP) | |
6845 | { | |
6846 | int slot; | |
6847 | int total_expansion = 0; | |
6848 | ||
6849 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6850 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6851 | ||
6852 | return total_expansion; | |
6853 | } | |
6854 | ||
6855 | ||
43cd72b9 BW |
6856 | /* Emit a vliw instruction to the current fragment. */ |
6857 | ||
7fa3d080 BW |
6858 | static void |
6859 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6860 | { |
e7da6241 | 6861 | bfd_boolean finish_frag; |
43cd72b9 BW |
6862 | bfd_boolean is_jump = FALSE; |
6863 | bfd_boolean is_branch = FALSE; | |
6864 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
6865 | int insn_size; |
6866 | int extra_space; | |
6867 | char *f = NULL; | |
6868 | int slot; | |
b224e962 BW |
6869 | struct dwarf2_line_info debug_line; |
6870 | bfd_boolean loc_directive_seen = FALSE; | |
6871 | TInsn *tinsn; | |
43cd72b9 | 6872 | |
b224e962 | 6873 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
6874 | |
6875 | if (generating_literals) | |
6876 | { | |
6877 | static int reported = 0; | |
6878 | if (reported < 4) | |
6879 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6880 | _("cannot assemble into a literal fragment")); | |
6881 | if (reported == 3) | |
6882 | as_bad (_("...")); | |
6883 | reported++; | |
6884 | return; | |
6885 | } | |
6886 | ||
6887 | if (frag_now_fix () != 0 | |
b08b5071 | 6888 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6889 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6890 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6891 | || (directive_state[directive_longcalls] |
6892 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6893 | || (directive_state[directive_absolute_literals] |
6894 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6895 | { | |
6896 | frag_wane (frag_now); | |
6897 | frag_new (0); | |
6898 | xtensa_set_frag_assembly_state (frag_now); | |
6899 | } | |
6900 | ||
6901 | if (workaround_a0_b_retw | |
6902 | && vinsn->num_slots == 1 | |
6903 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6904 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6905 | && use_transform ()) | |
6906 | { | |
6907 | has_a0_b_retw = TRUE; | |
6908 | ||
6909 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6910 | After the first assembly pass we will check all of them and | |
6911 | add a nop if needed. */ | |
6912 | frag_now->tc_frag_data.is_insn = TRUE; | |
6913 | frag_var (rs_machine_dependent, 4, 4, | |
6914 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6915 | frag_now->fr_symbol, | |
6916 | frag_now->fr_offset, | |
6917 | NULL); | |
6918 | xtensa_set_frag_assembly_state (frag_now); | |
6919 | frag_now->tc_frag_data.is_insn = TRUE; | |
6920 | frag_var (rs_machine_dependent, 4, 4, | |
6921 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6922 | frag_now->fr_symbol, | |
6923 | frag_now->fr_offset, | |
6924 | NULL); | |
6925 | xtensa_set_frag_assembly_state (frag_now); | |
6926 | } | |
6927 | ||
b224e962 | 6928 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 6929 | { |
b224e962 BW |
6930 | tinsn = &vinsn->slots[slot]; |
6931 | ||
43cd72b9 | 6932 | /* See if the instruction implies an aligned section. */ |
b224e962 | 6933 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 6934 | record_alignment (now_seg, 2); |
c138bc38 | 6935 | |
b224e962 BW |
6936 | /* Determine the best line number for debug info. */ |
6937 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
6938 | && (tinsn->debug_line.filenum != debug_line.filenum | |
6939 | || tinsn->debug_line.line < debug_line.line | |
6940 | || tinsn->debug_line.column < debug_line.column)) | |
6941 | debug_line = tinsn->debug_line; | |
6942 | if (tinsn->loc_directive_seen) | |
6943 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
6944 | } |
6945 | ||
6946 | /* Special cases for instructions that force an alignment... */ | |
6947 | /* None of these opcodes are bundle-able. */ | |
6948 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6949 | { | |
d77b99c9 | 6950 | int max_fill; |
c138bc38 | 6951 | |
05d58145 BW |
6952 | /* Remember the symbol that marks the end of the loop in the frag |
6953 | that marks the start of the loop. This way we can easily find | |
6954 | the end of the loop at the beginning, without adding special code | |
6955 | to mark the loop instructions themselves. */ | |
6956 | symbolS *target_sym = NULL; | |
6957 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6958 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6959 | ||
43cd72b9 BW |
6960 | xtensa_set_frag_assembly_state (frag_now); |
6961 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6962 | |
43cd72b9 BW |
6963 | max_fill = get_text_align_max_fill_size |
6964 | (get_text_align_power (xtensa_fetch_width), | |
6965 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6966 | ||
6967 | if (use_transform ()) | |
6968 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6969 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6970 | else |
c138bc38 | 6971 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6972 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6973 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
6974 | } |
6975 | ||
b08b5071 | 6976 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6977 | && !vinsn->slots[0].is_specific_opcode) |
6978 | { | |
6979 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 6980 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
6981 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
6982 | } | |
6983 | ||
6984 | if (vinsn->num_slots == 1) | |
6985 | { | |
6986 | if (workaround_a0_b_retw && use_transform ()) | |
6987 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6988 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6989 | ||
6990 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6991 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6992 | } | |
6993 | else | |
6994 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6995 | ||
6996 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6997 | ||
e7da6241 | 6998 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6999 | |
7000 | /* vinsn_to_insnbuf will produce the error. */ | |
7001 | if (vinsn->format != XTENSA_UNDEFINED) | |
7002 | { | |
d77b99c9 | 7003 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7004 | xtensa_set_frag_assembly_state (frag_now); |
7005 | frag_now->tc_frag_data.is_insn = TRUE; | |
7006 | } | |
7007 | ||
e7da6241 | 7008 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7009 | if (vinsn->format == XTENSA_UNDEFINED) |
7010 | return; | |
7011 | ||
d77b99c9 | 7012 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7013 | |
b224e962 BW |
7014 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7015 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7016 | &debug_line); | |
43cd72b9 BW |
7017 | |
7018 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7019 | { | |
b224e962 | 7020 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7021 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7022 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7023 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
7024 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
7025 | if (tinsn->literal_space != 0) | |
7026 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7027 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7028 | |
7029 | if (tinsn->subtype == RELAX_NARROW) | |
7030 | assert (vinsn->num_slots == 1); | |
7031 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
7032 | is_jump = TRUE; | |
7033 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7034 | is_branch = TRUE; | |
7035 | ||
e7da6241 BW |
7036 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7037 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7038 | finish_frag = TRUE; |
7039 | } | |
7040 | ||
7041 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7042 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7043 | |
7044 | if (finish_frag) | |
7045 | { | |
7046 | frag_variant (rs_machine_dependent, | |
7047 | extra_space, extra_space, RELAX_SLOTS, | |
7048 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7049 | xtensa_set_frag_assembly_state (frag_now); | |
7050 | } | |
7051 | ||
7052 | /* Special cases for loops: | |
7053 | close_loop_end should be inserted AFTER short_loop. | |
7054 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7055 | when converting them. */ | |
7056 | ||
7057 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7058 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7059 | && !vinsn->slots[0].is_specific_opcode) |
7060 | { | |
7061 | if (workaround_short_loop && use_transform ()) | |
7062 | { | |
7063 | maybe_has_short_loop = TRUE; | |
7064 | frag_now->tc_frag_data.is_insn = TRUE; | |
7065 | frag_var (rs_machine_dependent, 4, 4, | |
7066 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7067 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7068 | frag_now->tc_frag_data.is_insn = TRUE; | |
7069 | frag_var (rs_machine_dependent, 4, 4, | |
7070 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7071 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7072 | } | |
7073 | ||
7074 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7075 | loop at least 12 bytes away from another loop's end. */ | |
7076 | if (workaround_close_loop_end && use_transform ()) | |
7077 | { | |
7078 | maybe_has_close_loop_end = TRUE; | |
7079 | frag_now->tc_frag_data.is_insn = TRUE; | |
7080 | frag_var (rs_machine_dependent, 12, 12, | |
7081 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7082 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7083 | } | |
7084 | } | |
7085 | ||
7086 | if (use_transform ()) | |
7087 | { | |
7088 | if (is_jump) | |
7089 | { | |
7090 | assert (finish_frag); | |
7091 | frag_var (rs_machine_dependent, | |
7092 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7093 | RELAX_UNREACHABLE, | |
7094 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7095 | xtensa_set_frag_assembly_state (frag_now); | |
7096 | } | |
7b1cc377 | 7097 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
7098 | { |
7099 | assert (finish_frag); | |
7100 | frag_var (rs_machine_dependent, | |
7101 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
7102 | RELAX_MAYBE_UNREACHABLE, | |
7103 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7104 | xtensa_set_frag_assembly_state (frag_now); | |
7105 | frag_var (rs_machine_dependent, | |
7106 | 0, 0, | |
7107 | RELAX_MAYBE_DESIRE_ALIGN, | |
7108 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7109 | xtensa_set_frag_assembly_state (frag_now); | |
7110 | } | |
7111 | } | |
7112 | ||
7113 | /* Now, if the original opcode was a call... */ | |
7114 | if (do_align_targets () | |
7115 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7116 | { | |
b08b5071 | 7117 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7118 | frag_now->tc_frag_data.is_insn = TRUE; |
7119 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7120 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7121 | xtensa_set_frag_assembly_state (frag_now); | |
7122 | } | |
7123 | ||
7124 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7125 | { | |
7126 | frag_wane (frag_now); | |
7127 | frag_new (0); | |
7128 | xtensa_set_frag_assembly_state (frag_now); | |
7129 | } | |
7130 | } | |
7131 | ||
7132 | \f | |
7fa3d080 BW |
7133 | /* xtensa_end and helper functions. */ |
7134 | ||
7135 | static void xtensa_cleanup_align_frags (void); | |
7136 | static void xtensa_fix_target_frags (void); | |
7137 | static void xtensa_mark_narrow_branches (void); | |
7138 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7139 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7140 | static void xtensa_fix_a0_b_retw_frags (void); |
7141 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7142 | static void xtensa_fix_close_loop_end_frags (void); | |
7143 | static void xtensa_fix_short_loop_frags (void); | |
7144 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7145 | static void xtensa_add_config_info (void); |
7fa3d080 | 7146 | |
43cd72b9 | 7147 | void |
7fa3d080 | 7148 | xtensa_end (void) |
43cd72b9 BW |
7149 | { |
7150 | directive_balance (); | |
7151 | xtensa_flush_pending_output (); | |
7152 | ||
7153 | past_xtensa_end = TRUE; | |
7154 | ||
7155 | xtensa_move_literals (); | |
7156 | ||
7157 | xtensa_reorder_segments (); | |
7158 | xtensa_cleanup_align_frags (); | |
7159 | xtensa_fix_target_frags (); | |
7160 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7161 | xtensa_fix_a0_b_retw_frags (); | |
7162 | if (workaround_b_j_loop_end) | |
7163 | xtensa_fix_b_j_loop_end_frags (); | |
7164 | ||
7165 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7166 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7167 | xtensa_fix_close_loop_end_frags (); | |
7168 | ||
7169 | if (workaround_short_loop && maybe_has_short_loop) | |
7170 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7171 | if (align_targets) |
7172 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7173 | xtensa_mark_zcl_first_insns (); |
7174 | ||
7175 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7176 | |
7177 | xtensa_add_config_info (); | |
43cd72b9 BW |
7178 | } |
7179 | ||
7180 | ||
7181 | static void | |
7fa3d080 | 7182 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7183 | { |
7184 | frchainS *frchP; | |
c9049d30 | 7185 | asection *s; |
43cd72b9 | 7186 | |
c9049d30 AM |
7187 | for (s = stdoutput->sections; s; s = s->next) |
7188 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7189 | { | |
7190 | fragS *fragP; | |
7191 | /* Walk over all of the fragments in a subsection. */ | |
7192 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7193 | { | |
7194 | if ((fragP->fr_type == rs_align | |
7195 | || fragP->fr_type == rs_align_code | |
7196 | || (fragP->fr_type == rs_machine_dependent | |
7197 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7198 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7199 | && fragP->fr_fix == 0) | |
7200 | { | |
7201 | fragS *next = fragP->fr_next; | |
7202 | ||
7203 | while (next | |
7204 | && next->fr_fix == 0 | |
7205 | && next->fr_type == rs_machine_dependent | |
7206 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7207 | { | |
7208 | frag_wane (next); | |
7209 | next = next->fr_next; | |
7210 | } | |
7211 | } | |
7212 | /* If we don't widen branch targets, then they | |
7213 | will be easier to align. */ | |
7214 | if (fragP->tc_frag_data.is_branch_target | |
7215 | && fragP->fr_opcode == fragP->fr_literal | |
7216 | && fragP->fr_type == rs_machine_dependent | |
7217 | && fragP->fr_subtype == RELAX_SLOTS | |
7218 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7219 | frag_wane (fragP); | |
7220 | if (fragP->fr_type == rs_machine_dependent | |
7221 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7222 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7223 | } | |
7224 | } | |
43cd72b9 BW |
7225 | } |
7226 | ||
7227 | ||
7228 | /* Re-process all of the fragments looking to convert all of the | |
7229 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7230 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7231 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7232 | |
43cd72b9 | 7233 | static void |
7fa3d080 | 7234 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7235 | { |
7236 | frchainS *frchP; | |
c9049d30 | 7237 | asection *s; |
e0001a05 NC |
7238 | |
7239 | /* When this routine is called, all of the subsections are still intact | |
7240 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7241 | for (s = stdoutput->sections; s; s = s->next) |
7242 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7243 | { | |
7244 | fragS *fragP; | |
e0001a05 | 7245 | |
c9049d30 AM |
7246 | /* Walk over all of the fragments in a subsection. */ |
7247 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7248 | { | |
7249 | if (fragP->fr_type == rs_machine_dependent | |
7250 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7251 | { | |
7252 | if (next_frag_is_branch_target (fragP)) | |
7253 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7254 | else | |
7255 | frag_wane (fragP); | |
7256 | } | |
7257 | } | |
7258 | } | |
e0001a05 NC |
7259 | } |
7260 | ||
7261 | ||
7fa3d080 BW |
7262 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7263 | ||
43cd72b9 | 7264 | static void |
7fa3d080 | 7265 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7266 | { |
7267 | frchainS *frchP; | |
c9049d30 | 7268 | asection *s; |
43cd72b9 | 7269 | |
c9049d30 AM |
7270 | for (s = stdoutput->sections; s; s = s->next) |
7271 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7272 | { | |
7273 | fragS *fragP; | |
7274 | /* Walk over all of the fragments in a subsection. */ | |
7275 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7276 | { | |
7277 | if (fragP->fr_type == rs_machine_dependent | |
7278 | && fragP->fr_subtype == RELAX_SLOTS | |
7279 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7280 | { | |
7281 | vliw_insn vinsn; | |
7282 | ||
7283 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7284 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7285 | ||
7286 | if (vinsn.num_slots == 1 | |
7287 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7288 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7289 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7290 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7291 | &vinsn.slots[0])) | |
7292 | { | |
7293 | fragP->fr_subtype = RELAX_SLOTS; | |
7294 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7295 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7296 | } | |
7297 | } | |
7298 | } | |
7299 | } | |
43cd72b9 BW |
7300 | } |
7301 | ||
7302 | ||
7303 | /* A branch is typically widened only when its target is out of | |
7304 | range. However, we would like to widen them to align a subsequent | |
7305 | branch target when possible. | |
7306 | ||
7307 | Because the branch relaxation code is so convoluted, the optimal solution | |
7308 | (combining the two cases) is difficult to get right in all circumstances. | |
7309 | We therefore go with an "almost as good" solution, where we only | |
7310 | use for alignment narrow branches that definitely will not expand to a | |
7311 | jump and a branch. These functions find and mark these cases. */ | |
7312 | ||
a67517f4 BW |
7313 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7314 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7315 | We start counting beginning with the frag after the 2-byte branch, so the | |
7316 | maximum offset is (4 - 2) + 63 = 65. */ | |
7317 | #define MAX_IMMED6 65 | |
43cd72b9 | 7318 | |
d77b99c9 | 7319 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7320 | |
43cd72b9 | 7321 | static bfd_boolean |
7fa3d080 | 7322 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7323 | { |
7324 | const expressionS *expr = &tinsn->tok[1]; | |
7325 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7326 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7327 | fragS *target_frag; |
7328 | ||
7329 | if (expr->X_op != O_symbol) | |
7330 | return FALSE; | |
7331 | ||
7332 | target_frag = symbol_get_frag (symbolP); | |
7333 | ||
43cd72b9 BW |
7334 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7335 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7336 | return FALSE; | |
7337 | ||
7338 | /* The branch doesn't branch over it's own frag, | |
7339 | but over the subsequent ones. */ | |
7340 | fragP = fragP->fr_next; | |
7341 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7342 | { | |
7343 | max_distance += unrelaxed_frag_max_size (fragP); | |
7344 | fragP = fragP->fr_next; | |
7345 | } | |
7346 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7347 | return TRUE; | |
e0001a05 NC |
7348 | return FALSE; |
7349 | } | |
7350 | ||
7351 | ||
43cd72b9 | 7352 | static void |
7fa3d080 | 7353 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7354 | { |
7355 | frchainS *frchP; | |
c9049d30 | 7356 | asection *s; |
43cd72b9 | 7357 | |
c9049d30 AM |
7358 | for (s = stdoutput->sections; s; s = s->next) |
7359 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7360 | { | |
7361 | fragS *fragP; | |
7362 | /* Walk over all of the fragments in a subsection. */ | |
7363 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7364 | { | |
7365 | if (fragP->fr_type == rs_machine_dependent | |
7366 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7367 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7368 | { | |
7369 | /* Find the loop frag. */ | |
7370 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7371 | /* Find the first insn frag. */ | |
7372 | targ_frag = next_non_empty_frag (targ_frag); | |
7373 | ||
7374 | /* Of course, sometimes (mostly for toy test cases) a | |
7375 | zero-cost loop instruction is the last in a section. */ | |
7376 | if (targ_frag) | |
7377 | { | |
7378 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7379 | /* Do not widen a frag that is the first instruction of a | |
7380 | zero-cost loop. It makes that loop harder to align. */ | |
7381 | if (targ_frag->fr_type == rs_machine_dependent | |
7382 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7383 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7384 | == RELAX_NARROW)) | |
7385 | { | |
7386 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7387 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7388 | else | |
7389 | { | |
7390 | frag_wane (targ_frag); | |
7391 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7392 | } | |
7393 | } | |
7394 | } | |
7395 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7396 | frag_wane (fragP); | |
7397 | } | |
7398 | } | |
7399 | } | |
43cd72b9 BW |
7400 | } |
7401 | ||
7402 | ||
fb227da0 BW |
7403 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7404 | sleb128 value, the linker is unable to adjust that value to account for | |
7405 | link-time relaxation. Mark all the code between such symbols so that | |
7406 | its size cannot be changed by linker relaxation. */ | |
7407 | ||
6a7eedfe BW |
7408 | static void |
7409 | xtensa_mark_difference_of_two_symbols (void) | |
7410 | { | |
7411 | symbolS *expr_sym; | |
7412 | ||
7413 | for (expr_sym = expr_symbols; expr_sym; | |
7414 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7415 | { | |
7416 | expressionS *expr = symbol_get_value_expression (expr_sym); | |
7417 | ||
7418 | if (expr->X_op == O_subtract) | |
7419 | { | |
7420 | symbolS *left = expr->X_add_symbol; | |
7421 | symbolS *right = expr->X_op_symbol; | |
7422 | ||
7423 | /* Difference of two symbols not in the same section | |
7424 | are handled with relocations in the linker. */ | |
7425 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7426 | { | |
7427 | fragS *start; | |
7428 | fragS *end; | |
7429 | ||
7430 | if (symbol_get_frag (left)->fr_address | |
7431 | <= symbol_get_frag (right)->fr_address) | |
7432 | { | |
7433 | start = symbol_get_frag (left); | |
7434 | end = symbol_get_frag (right); | |
7435 | } | |
7436 | else | |
7437 | { | |
7438 | start = symbol_get_frag (right); | |
7439 | end = symbol_get_frag (left); | |
7440 | } | |
7441 | do | |
7442 | { | |
7443 | start->tc_frag_data.is_no_transform = 1; | |
7444 | start = start->fr_next; | |
7445 | } | |
7446 | while (start && start->fr_address < end->fr_address); | |
7447 | } | |
7448 | } | |
7449 | } | |
7450 | } | |
7451 | ||
7452 | ||
e0001a05 NC |
7453 | /* Re-process all of the fragments looking to convert all of the |
7454 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7455 | conditional branch or a retw/retw.n, convert this frag to one that | |
7456 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7457 | ||
7fa3d080 BW |
7458 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7459 | ||
e0001a05 | 7460 | static void |
7fa3d080 | 7461 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7462 | { |
7463 | frchainS *frchP; | |
c9049d30 | 7464 | asection *s; |
e0001a05 NC |
7465 | |
7466 | /* When this routine is called, all of the subsections are still intact | |
7467 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7468 | for (s = stdoutput->sections; s; s = s->next) |
7469 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7470 | { | |
7471 | fragS *fragP; | |
e0001a05 | 7472 | |
c9049d30 AM |
7473 | /* Walk over all of the fragments in a subsection. */ |
7474 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7475 | { | |
7476 | if (fragP->fr_type == rs_machine_dependent | |
7477 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7478 | { | |
7479 | if (next_instrs_are_b_retw (fragP)) | |
7480 | { | |
7481 | if (fragP->tc_frag_data.is_no_transform) | |
7482 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7483 | else | |
7484 | relax_frag_add_nop (fragP); | |
7485 | } | |
7486 | frag_wane (fragP); | |
7487 | } | |
7488 | } | |
7489 | } | |
e0001a05 NC |
7490 | } |
7491 | ||
7492 | ||
7fa3d080 BW |
7493 | static bfd_boolean |
7494 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7495 | { |
7496 | xtensa_opcode opcode; | |
43cd72b9 | 7497 | xtensa_format fmt; |
e0001a05 NC |
7498 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7499 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7500 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7501 | xtensa_isa isa = xtensa_default_isa; |
7502 | int offset = 0; | |
43cd72b9 BW |
7503 | int slot; |
7504 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7505 | |
7506 | if (!insnbuf) | |
43cd72b9 BW |
7507 | { |
7508 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7509 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7510 | } | |
e0001a05 NC |
7511 | |
7512 | if (next_fragP == NULL) | |
7513 | return FALSE; | |
7514 | ||
7515 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7516 | xtensa_insnbuf_from_chars |
7517 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7518 | fmt = xtensa_format_decode (isa, insnbuf); |
7519 | if (fmt == XTENSA_UNDEFINED) | |
7520 | return FALSE; | |
7521 | ||
7522 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7523 | { | |
7524 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7525 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7526 | ||
7527 | branch_seen = (branch_seen | |
7528 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7529 | } | |
e0001a05 | 7530 | |
43cd72b9 | 7531 | if (!branch_seen) |
e0001a05 NC |
7532 | return FALSE; |
7533 | ||
43cd72b9 | 7534 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7535 | if (offset == next_fragP->fr_fix) |
7536 | { | |
7537 | next_fragP = next_non_empty_frag (next_fragP); | |
7538 | offset = 0; | |
7539 | } | |
43cd72b9 | 7540 | |
e0001a05 NC |
7541 | if (next_fragP == NULL) |
7542 | return FALSE; | |
7543 | ||
7544 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7545 | xtensa_insnbuf_from_chars |
7546 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7547 | fmt = xtensa_format_decode (isa, insnbuf); |
7548 | ||
7549 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7550 | have no problems. */ | |
7551 | if (fmt == XTENSA_UNDEFINED | |
7552 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7553 | return FALSE; | |
7554 | ||
7555 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7556 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7557 | |
b08b5071 | 7558 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7559 | return TRUE; |
43cd72b9 | 7560 | |
e0001a05 NC |
7561 | return FALSE; |
7562 | } | |
7563 | ||
7564 | ||
7565 | /* Re-process all of the fragments looking to convert all of the | |
7566 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7567 | loop end label, convert this frag to one that will generate a NOP. | |
7568 | In any case close it off with a .fill 0. */ | |
7569 | ||
7fa3d080 BW |
7570 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7571 | ||
e0001a05 | 7572 | static void |
7fa3d080 | 7573 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7574 | { |
7575 | frchainS *frchP; | |
c9049d30 | 7576 | asection *s; |
e0001a05 NC |
7577 | |
7578 | /* When this routine is called, all of the subsections are still intact | |
7579 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7580 | for (s = stdoutput->sections; s; s = s->next) |
7581 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7582 | { | |
7583 | fragS *fragP; | |
e0001a05 | 7584 | |
c9049d30 AM |
7585 | /* Walk over all of the fragments in a subsection. */ |
7586 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7587 | { | |
7588 | if (fragP->fr_type == rs_machine_dependent | |
7589 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7590 | { | |
7591 | if (next_instr_is_loop_end (fragP)) | |
7592 | { | |
7593 | if (fragP->tc_frag_data.is_no_transform) | |
7594 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7595 | else | |
7596 | relax_frag_add_nop (fragP); | |
7597 | } | |
7598 | frag_wane (fragP); | |
7599 | } | |
7600 | } | |
7601 | } | |
e0001a05 NC |
7602 | } |
7603 | ||
7604 | ||
7fa3d080 BW |
7605 | static bfd_boolean |
7606 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7607 | { |
7608 | const fragS *next_fragP; | |
7609 | ||
7610 | if (next_frag_is_loop_target (fragP)) | |
7611 | return FALSE; | |
7612 | ||
7613 | next_fragP = next_non_empty_frag (fragP); | |
7614 | if (next_fragP == NULL) | |
7615 | return FALSE; | |
7616 | ||
7617 | if (!next_frag_is_loop_target (next_fragP)) | |
7618 | return FALSE; | |
7619 | ||
7620 | /* If the size is >= 3 then there is more than one instruction here. | |
7621 | The hardware bug will not fire. */ | |
7622 | if (next_fragP->fr_fix > 3) | |
7623 | return FALSE; | |
7624 | ||
7625 | return TRUE; | |
7626 | } | |
7627 | ||
7628 | ||
7629 | /* Re-process all of the fragments looking to convert all of the | |
7630 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7631 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7632 | make it at least 12 bytes away. In any case close it off with a | |
7633 | .fill 0. */ | |
7634 | ||
d77b99c9 | 7635 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7636 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7637 | |
e0001a05 | 7638 | static void |
7fa3d080 | 7639 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7640 | { |
7641 | frchainS *frchP; | |
c9049d30 | 7642 | asection *s; |
e0001a05 NC |
7643 | |
7644 | /* When this routine is called, all of the subsections are still intact | |
7645 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7646 | for (s = stdoutput->sections; s; s = s->next) |
7647 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7648 | { | |
7649 | fragS *fragP; | |
e0001a05 | 7650 | |
c9049d30 | 7651 | fragS *current_target = NULL; |
e0001a05 | 7652 | |
c9049d30 AM |
7653 | /* Walk over all of the fragments in a subsection. */ |
7654 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7655 | { | |
7656 | if (fragP->fr_type == rs_machine_dependent | |
7657 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7658 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7659 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7660 | |
c9049d30 AM |
7661 | if (current_target |
7662 | && fragP->fr_type == rs_machine_dependent | |
7663 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7664 | { | |
7665 | offsetT min_bytes; | |
7666 | int bytes_added = 0; | |
e0001a05 NC |
7667 | |
7668 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7669 | /* Max out at 12. */ |
7670 | min_bytes = min_bytes_to_other_loop_end | |
7671 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7672 | ||
7673 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7674 | { | |
7675 | if (fragP->tc_frag_data.is_no_transform) | |
7676 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7677 | else | |
7678 | { | |
7679 | while (min_bytes + bytes_added | |
7680 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7681 | { | |
7682 | int length = 3; | |
7683 | ||
7684 | if (fragP->fr_var < length) | |
7685 | as_fatal (_("fr_var %lu < length %d"), | |
7686 | (long) fragP->fr_var, length); | |
7687 | else | |
7688 | { | |
7689 | assemble_nop (length, | |
7690 | fragP->fr_literal + fragP->fr_fix); | |
7691 | fragP->fr_fix += length; | |
7692 | fragP->fr_var -= length; | |
7693 | } | |
7694 | bytes_added += length; | |
7695 | } | |
7696 | } | |
7697 | } | |
7698 | frag_wane (fragP); | |
7699 | } | |
7700 | assert (fragP->fr_type != rs_machine_dependent | |
7701 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7702 | } | |
7703 | } | |
e0001a05 NC |
7704 | } |
7705 | ||
7706 | ||
d77b99c9 | 7707 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7708 | |
d77b99c9 | 7709 | static offsetT |
7fa3d080 BW |
7710 | min_bytes_to_other_loop_end (fragS *fragP, |
7711 | fragS *current_target, | |
d77b99c9 | 7712 | offsetT max_size) |
e0001a05 | 7713 | { |
d77b99c9 | 7714 | offsetT offset = 0; |
e0001a05 NC |
7715 | fragS *current_fragP; |
7716 | ||
7717 | for (current_fragP = fragP; | |
7718 | current_fragP; | |
7719 | current_fragP = current_fragP->fr_next) | |
7720 | { | |
7721 | if (current_fragP->tc_frag_data.is_loop_target | |
7722 | && current_fragP != current_target) | |
05d58145 | 7723 | return offset; |
e0001a05 NC |
7724 | |
7725 | offset += unrelaxed_frag_min_size (current_fragP); | |
7726 | ||
05d58145 | 7727 | if (offset >= max_size) |
e0001a05 NC |
7728 | return max_size; |
7729 | } | |
7730 | return max_size; | |
7731 | } | |
7732 | ||
7733 | ||
d77b99c9 | 7734 | static offsetT |
7fa3d080 | 7735 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7736 | { |
d77b99c9 | 7737 | offsetT size = fragP->fr_fix; |
e0001a05 | 7738 | |
d77b99c9 | 7739 | /* Add fill size. */ |
e0001a05 NC |
7740 | if (fragP->fr_type == rs_fill) |
7741 | size += fragP->fr_offset; | |
7742 | ||
7743 | return size; | |
7744 | } | |
7745 | ||
7746 | ||
d77b99c9 | 7747 | static offsetT |
7fa3d080 | 7748 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7749 | { |
d77b99c9 | 7750 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7751 | switch (fragP->fr_type) |
7752 | { | |
7753 | case 0: | |
c138bc38 | 7754 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7755 | end up with type 0. */ |
7756 | break; | |
7757 | case rs_fill: | |
7758 | case rs_org: | |
7759 | case rs_space: | |
7760 | size += fragP->fr_offset; | |
7761 | break; | |
7762 | case rs_align: | |
7763 | case rs_align_code: | |
7764 | case rs_align_test: | |
7765 | case rs_leb128: | |
7766 | case rs_cfa: | |
7767 | case rs_dwarf2dbg: | |
7768 | /* No further adjustments needed. */ | |
7769 | break; | |
7770 | case rs_machine_dependent: | |
7771 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7772 | size += fragP->fr_var; | |
7773 | break; | |
7774 | default: | |
7775 | /* We had darn well better know how big it is. */ | |
7776 | assert (0); | |
7777 | break; | |
7778 | } | |
7779 | ||
7780 | return size; | |
7781 | } | |
7782 | ||
7783 | ||
e0001a05 NC |
7784 | /* Re-process all of the fragments looking to convert all |
7785 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7786 | ||
7787 | A) | |
7788 | 1) the instruction size count to the loop end label | |
7789 | is too short (<= 2 instructions), | |
7790 | 2) loop has a jump or branch in it | |
7791 | ||
7792 | or B) | |
43cd72b9 | 7793 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7794 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7795 | 3) the instruction size count to the loop end label is too short | |
7796 | (<= 2 instructions) | |
7797 | then convert this frag (and maybe the next one) to generate a NOP. | |
7798 | In any case close it off with a .fill 0. */ | |
7799 | ||
d77b99c9 | 7800 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7801 | static bfd_boolean branch_before_loop_end (fragS *); |
7802 | ||
e0001a05 | 7803 | static void |
7fa3d080 | 7804 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7805 | { |
7806 | frchainS *frchP; | |
c9049d30 | 7807 | asection *s; |
e0001a05 NC |
7808 | |
7809 | /* When this routine is called, all of the subsections are still intact | |
7810 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7811 | for (s = stdoutput->sections; s; s = s->next) |
7812 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7813 | { | |
7814 | fragS *fragP; | |
7815 | fragS *current_target = NULL; | |
7816 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7817 | |
c9049d30 AM |
7818 | /* Walk over all of the fragments in a subsection. */ |
7819 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7820 | { | |
7821 | if (fragP->fr_type == rs_machine_dependent | |
7822 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7823 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7824 | { | |
7825 | TInsn t_insn; | |
7826 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7827 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7828 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7829 | current_opcode = t_insn.opcode; | |
7830 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7831 | current_opcode) == 1); |
c9049d30 | 7832 | } |
e0001a05 | 7833 | |
c9049d30 AM |
7834 | if (fragP->fr_type == rs_machine_dependent |
7835 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7836 | { | |
7837 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7838 | && (branch_before_loop_end (fragP->fr_next) | |
7839 | || (workaround_all_short_loops | |
7840 | && current_opcode != XTENSA_UNDEFINED | |
7841 | && current_opcode != xtensa_loop_opcode))) | |
7842 | { | |
7843 | if (fragP->tc_frag_data.is_no_transform) | |
7844 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7845 | else | |
7846 | relax_frag_add_nop (fragP); | |
7847 | } | |
7848 | frag_wane (fragP); | |
7849 | } | |
7850 | } | |
7851 | } | |
e0001a05 NC |
7852 | } |
7853 | ||
7854 | ||
d77b99c9 | 7855 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7856 | |
d77b99c9 | 7857 | static int |
7fa3d080 BW |
7858 | count_insns_to_loop_end (fragS *base_fragP, |
7859 | bfd_boolean count_relax_add, | |
d77b99c9 | 7860 | int max_count) |
e0001a05 NC |
7861 | { |
7862 | fragS *fragP = NULL; | |
d77b99c9 | 7863 | int insn_count = 0; |
e0001a05 NC |
7864 | |
7865 | fragP = base_fragP; | |
7866 | ||
7867 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7868 | { | |
7869 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7870 | if (insn_count >= max_count) | |
7871 | return max_count; | |
7872 | ||
7873 | if (count_relax_add) | |
7874 | { | |
7875 | if (fragP->fr_type == rs_machine_dependent | |
7876 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7877 | { | |
7878 | /* In order to add the appropriate number of | |
7879 | NOPs, we count an instruction for downstream | |
7880 | occurrences. */ | |
7881 | insn_count++; | |
7882 | if (insn_count >= max_count) | |
7883 | return max_count; | |
7884 | } | |
7885 | } | |
7886 | } | |
7887 | return insn_count; | |
7888 | } | |
7889 | ||
7890 | ||
d77b99c9 | 7891 | static int |
7fa3d080 | 7892 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7893 | { |
43cd72b9 BW |
7894 | xtensa_isa isa = xtensa_default_isa; |
7895 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7896 | int insn_count = 0; |
e0001a05 NC |
7897 | int offset = 0; |
7898 | ||
7899 | if (!fragP->tc_frag_data.is_insn) | |
7900 | return insn_count; | |
7901 | ||
43cd72b9 BW |
7902 | if (!insnbuf) |
7903 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7904 | ||
e0001a05 NC |
7905 | /* Decode the fixed instructions. */ |
7906 | while (offset < fragP->fr_fix) | |
7907 | { | |
43cd72b9 BW |
7908 | xtensa_format fmt; |
7909 | ||
d77b99c9 BW |
7910 | xtensa_insnbuf_from_chars |
7911 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7912 | fmt = xtensa_format_decode (isa, insnbuf); |
7913 | ||
7914 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7915 | { |
7916 | as_fatal (_("undecodable instruction in instruction frag")); | |
7917 | return insn_count; | |
7918 | } | |
43cd72b9 | 7919 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7920 | insn_count++; |
7921 | } | |
7922 | ||
7923 | return insn_count; | |
7924 | } | |
7925 | ||
7926 | ||
7fa3d080 BW |
7927 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7928 | ||
43cd72b9 | 7929 | static bfd_boolean |
7fa3d080 | 7930 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7931 | { |
7932 | fragS *fragP; | |
7933 | ||
7934 | for (fragP = base_fragP; | |
7935 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7936 | fragP = fragP->fr_next) | |
7937 | { | |
7938 | if (unrelaxed_frag_has_b_j (fragP)) | |
7939 | return TRUE; | |
7940 | } | |
7941 | return FALSE; | |
7942 | } | |
7943 | ||
7944 | ||
43cd72b9 | 7945 | static bfd_boolean |
7fa3d080 | 7946 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7947 | { |
43cd72b9 BW |
7948 | static xtensa_insnbuf insnbuf = NULL; |
7949 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7950 | int offset = 0; |
7951 | ||
7952 | if (!fragP->tc_frag_data.is_insn) | |
7953 | return FALSE; | |
7954 | ||
43cd72b9 BW |
7955 | if (!insnbuf) |
7956 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7957 | ||
e0001a05 NC |
7958 | /* Decode the fixed instructions. */ |
7959 | while (offset < fragP->fr_fix) | |
7960 | { | |
43cd72b9 BW |
7961 | xtensa_format fmt; |
7962 | int slot; | |
7963 | ||
d77b99c9 BW |
7964 | xtensa_insnbuf_from_chars |
7965 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7966 | fmt = xtensa_format_decode (isa, insnbuf); |
7967 | if (fmt == XTENSA_UNDEFINED) | |
7968 | return FALSE; | |
7969 | ||
7970 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7971 | { |
43cd72b9 BW |
7972 | xtensa_opcode opcode = |
7973 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7974 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7975 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7976 | return TRUE; | |
e0001a05 | 7977 | } |
43cd72b9 | 7978 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7979 | } |
7980 | return FALSE; | |
7981 | } | |
7982 | ||
7983 | ||
7984 | /* Checks to be made after initial assembly but before relaxation. */ | |
7985 | ||
7fa3d080 BW |
7986 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7987 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7988 | ||
e0001a05 | 7989 | static void |
7fa3d080 | 7990 | xtensa_sanity_check (void) |
e0001a05 NC |
7991 | { |
7992 | char *file_name; | |
d77b99c9 | 7993 | unsigned line; |
e0001a05 | 7994 | frchainS *frchP; |
c9049d30 | 7995 | asection *s; |
e0001a05 NC |
7996 | |
7997 | as_where (&file_name, &line); | |
c9049d30 AM |
7998 | for (s = stdoutput->sections; s; s = s->next) |
7999 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8000 | { | |
8001 | fragS *fragP; | |
e0001a05 | 8002 | |
c9049d30 AM |
8003 | /* Walk over all of the fragments in a subsection. */ |
8004 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8005 | { | |
c9049d30 | 8006 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
8007 | && fragP->fr_subtype == RELAX_SLOTS |
8008 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
8009 | { |
8010 | static xtensa_insnbuf insnbuf = NULL; | |
8011 | TInsn t_insn; | |
8012 | ||
8013 | if (fragP->fr_opcode != NULL) | |
8014 | { | |
8015 | if (!insnbuf) | |
8016 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8017 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8018 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8019 | ||
8020 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8021 | t_insn.opcode) == 1) | |
8022 | { | |
8023 | if (is_empty_loop (&t_insn, fragP)) | |
8024 | { | |
8025 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8026 | as_bad (_("invalid empty loop")); | |
8027 | } | |
8028 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8029 | { | |
8030 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8031 | as_bad (_("loop target does not follow " | |
8032 | "loop instruction in section")); | |
8033 | } | |
8034 | } | |
8035 | } | |
8036 | } | |
8037 | } | |
8038 | } | |
e0001a05 NC |
8039 | new_logical_line (file_name, line); |
8040 | } | |
8041 | ||
8042 | ||
8043 | #define LOOP_IMMED_OPN 1 | |
8044 | ||
43cd72b9 | 8045 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8046 | |
7fa3d080 BW |
8047 | static bfd_boolean |
8048 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
8049 | { |
8050 | const expressionS *expr; | |
8051 | symbolS *symbolP; | |
8052 | fragS *next_fragP; | |
8053 | ||
8054 | if (insn->insn_type != ITYPE_INSN) | |
8055 | return FALSE; | |
8056 | ||
43cd72b9 | 8057 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8058 | return FALSE; |
8059 | ||
8060 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8061 | return FALSE; | |
8062 | ||
8063 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
8064 | ||
8065 | if (expr->X_op != O_symbol) | |
8066 | return FALSE; | |
8067 | ||
8068 | symbolP = expr->X_add_symbol; | |
8069 | if (!symbolP) | |
8070 | return FALSE; | |
8071 | ||
8072 | if (symbol_get_frag (symbolP) == NULL) | |
8073 | return FALSE; | |
8074 | ||
8075 | if (S_GET_VALUE (symbolP) != 0) | |
8076 | return FALSE; | |
8077 | ||
8078 | /* Walk through the zero-size fragments from this one. If we find | |
8079 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8080 | |
e0001a05 NC |
8081 | for (next_fragP = fragP->fr_next; |
8082 | next_fragP != NULL; | |
8083 | next_fragP = next_fragP->fr_next) | |
8084 | { | |
8085 | if (next_fragP == symbol_get_frag (symbolP)) | |
8086 | return TRUE; | |
8087 | if (next_fragP->fr_fix != 0) | |
8088 | return FALSE; | |
8089 | } | |
8090 | return FALSE; | |
8091 | } | |
8092 | ||
8093 | ||
7fa3d080 BW |
8094 | static bfd_boolean |
8095 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
8096 | { |
8097 | const expressionS *expr; | |
8098 | symbolS *symbolP; | |
8099 | fragS *next_fragP; | |
8100 | ||
8101 | if (insn->insn_type != ITYPE_INSN) | |
8102 | return FALSE; | |
8103 | ||
64b607e6 | 8104 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8105 | return FALSE; |
8106 | ||
8107 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8108 | return FALSE; | |
8109 | ||
8110 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
8111 | ||
8112 | if (expr->X_op != O_symbol) | |
8113 | return FALSE; | |
8114 | ||
8115 | symbolP = expr->X_add_symbol; | |
8116 | if (!symbolP) | |
8117 | return FALSE; | |
8118 | ||
8119 | if (symbol_get_frag (symbolP) == NULL) | |
8120 | return FALSE; | |
8121 | ||
8122 | /* Walk through fragments until we find the target. | |
8123 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8124 | |
e0001a05 NC |
8125 | for (next_fragP = fragP->fr_next; |
8126 | next_fragP != NULL; | |
8127 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8128 | { |
8129 | if (next_fragP == symbol_get_frag (symbolP)) | |
8130 | return TRUE; | |
8131 | } | |
e0001a05 NC |
8132 | |
8133 | return FALSE; | |
8134 | } | |
8135 | ||
2caa7ca0 BW |
8136 | |
8137 | #define XTINFO_NAME "Xtensa_Info" | |
8138 | #define XTINFO_NAMESZ 12 | |
8139 | #define XTINFO_TYPE 1 | |
8140 | ||
8141 | static void | |
8142 | xtensa_add_config_info (void) | |
8143 | { | |
8144 | asection *info_sec; | |
8145 | char *data, *p; | |
8146 | int sz; | |
8147 | ||
8148 | info_sec = subseg_new (".xtensa.info", 0); | |
8149 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8150 | ||
8151 | data = xmalloc (100); | |
8152 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
8153 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8154 | sz = strlen (data) + 1; | |
8155 | ||
8156 | /* Add enough null terminators to pad to a word boundary. */ | |
8157 | do | |
8158 | data[sz++] = 0; | |
8159 | while ((sz & 3) != 0); | |
8160 | ||
8161 | /* Follow the standard note section layout: | |
8162 | First write the length of the name string. */ | |
8163 | p = frag_more (4); | |
8164 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8165 | ||
8166 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8167 | p = frag_more (4); | |
8168 | md_number_to_chars (p, (valueT) sz, 4); | |
8169 | ||
8170 | /* Write the note type. */ | |
8171 | p = frag_more (4); | |
8172 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8173 | ||
8174 | /* Write the name field. */ | |
8175 | p = frag_more (XTINFO_NAMESZ); | |
8176 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8177 | ||
8178 | /* Finally, write the descriptor. */ | |
8179 | p = frag_more (sz); | |
8180 | memcpy (p, data, sz); | |
8181 | ||
8182 | free (data); | |
8183 | } | |
8184 | ||
e0001a05 NC |
8185 | \f |
8186 | /* Alignment Functions. */ | |
8187 | ||
d77b99c9 BW |
8188 | static int |
8189 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8190 | { |
03aaa593 BW |
8191 | if (target_size <= 4) |
8192 | return 2; | |
8193 | assert (target_size == 8); | |
8194 | return 3; | |
e0001a05 NC |
8195 | } |
8196 | ||
8197 | ||
d77b99c9 | 8198 | static int |
7fa3d080 BW |
8199 | get_text_align_max_fill_size (int align_pow, |
8200 | bfd_boolean use_nops, | |
8201 | bfd_boolean use_no_density) | |
e0001a05 NC |
8202 | { |
8203 | if (!use_nops) | |
8204 | return (1 << align_pow); | |
8205 | if (use_no_density) | |
8206 | return 3 * (1 << align_pow); | |
8207 | ||
8208 | return 1 + (1 << align_pow); | |
8209 | } | |
8210 | ||
8211 | ||
d77b99c9 BW |
8212 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8213 | target instruction of size "target_size" so that it does not cross a | |
8214 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8215 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8216 | be filled by NOP instructions. */ | |
e0001a05 | 8217 | |
d77b99c9 | 8218 | static int |
7fa3d080 BW |
8219 | get_text_align_fill_size (addressT address, |
8220 | int align_pow, | |
8221 | int target_size, | |
8222 | bfd_boolean use_nops, | |
8223 | bfd_boolean use_no_density) | |
e0001a05 | 8224 | { |
d77b99c9 BW |
8225 | addressT alignment, fill, fill_limit, fill_step; |
8226 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8227 | |
d77b99c9 BW |
8228 | alignment = (1 << align_pow); |
8229 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 8230 | |
e0001a05 NC |
8231 | if (!use_nops) |
8232 | { | |
d77b99c9 BW |
8233 | fill_limit = alignment; |
8234 | fill_step = 1; | |
e0001a05 | 8235 | } |
d77b99c9 | 8236 | else if (!use_no_density) |
e0001a05 | 8237 | { |
d77b99c9 BW |
8238 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8239 | fill_limit = alignment * 2; | |
8240 | fill_step = 1; | |
8241 | skip_one = TRUE; | |
e0001a05 NC |
8242 | } |
8243 | else | |
8244 | { | |
d77b99c9 BW |
8245 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8246 | fill_limit = alignment * 3; | |
8247 | fill_step = 3; | |
8248 | } | |
e0001a05 | 8249 | |
d77b99c9 BW |
8250 | /* Try all fill sizes until finding one that works. */ |
8251 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8252 | { | |
8253 | if (skip_one && fill == 1) | |
8254 | continue; | |
8255 | if ((address + fill) >> align_pow | |
8256 | == (address + fill + target_size - 1) >> align_pow) | |
8257 | return fill; | |
e0001a05 NC |
8258 | } |
8259 | assert (0); | |
8260 | return 0; | |
8261 | } | |
8262 | ||
8263 | ||
664df4e4 BW |
8264 | static int |
8265 | branch_align_power (segT sec) | |
8266 | { | |
8267 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8268 | is aligned to at least an 8-byte boundary, then a branch target need | |
8269 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8270 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8271 | (which may be insufficient, e.g., if the section has no alignment, but | |
8272 | it's good enough). */ | |
8273 | if (xtensa_fetch_width == 8) | |
8274 | { | |
8275 | if (get_recorded_alignment (sec) >= 3) | |
8276 | return 3; | |
8277 | } | |
8278 | else | |
8279 | assert (xtensa_fetch_width == 4); | |
8280 | ||
8281 | return 2; | |
8282 | } | |
8283 | ||
8284 | ||
e0001a05 NC |
8285 | /* This will assert if it is not possible. */ |
8286 | ||
d77b99c9 BW |
8287 | static int |
8288 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8289 | { |
d77b99c9 BW |
8290 | int count = 0; |
8291 | ||
e0001a05 NC |
8292 | if (use_no_density) |
8293 | { | |
8294 | assert (fill_size % 3 == 0); | |
8295 | return (fill_size / 3); | |
8296 | } | |
8297 | ||
8298 | assert (fill_size != 1); /* Bad argument. */ | |
8299 | ||
8300 | while (fill_size > 1) | |
8301 | { | |
d77b99c9 | 8302 | int insn_size = 3; |
e0001a05 NC |
8303 | if (fill_size == 2 || fill_size == 4) |
8304 | insn_size = 2; | |
8305 | fill_size -= insn_size; | |
8306 | count++; | |
8307 | } | |
8308 | assert (fill_size != 1); /* Bad algorithm. */ | |
8309 | return count; | |
8310 | } | |
8311 | ||
8312 | ||
d77b99c9 BW |
8313 | static int |
8314 | get_text_align_nth_nop_size (offsetT fill_size, | |
8315 | int n, | |
7fa3d080 | 8316 | bfd_boolean use_no_density) |
e0001a05 | 8317 | { |
d77b99c9 | 8318 | int count = 0; |
e0001a05 NC |
8319 | |
8320 | if (use_no_density) | |
8321 | return 3; | |
8322 | ||
d77b99c9 BW |
8323 | assert (fill_size != 1); /* Bad argument. */ |
8324 | ||
e0001a05 NC |
8325 | while (fill_size > 1) |
8326 | { | |
d77b99c9 | 8327 | int insn_size = 3; |
e0001a05 NC |
8328 | if (fill_size == 2 || fill_size == 4) |
8329 | insn_size = 2; | |
8330 | fill_size -= insn_size; | |
8331 | count++; | |
8332 | if (n + 1 == count) | |
8333 | return insn_size; | |
8334 | } | |
8335 | assert (0); | |
8336 | return 0; | |
8337 | } | |
8338 | ||
8339 | ||
8340 | /* For the given fragment, find the appropriate address | |
8341 | for it to begin at if we are using NOPs to align it. */ | |
8342 | ||
8343 | static addressT | |
7fa3d080 | 8344 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8345 | { |
43cd72b9 BW |
8346 | /* The rule is: get next fragment's FIRST instruction. Find |
8347 | the smallest number of bytes that need to be added to | |
8348 | ensure that the next fragment's FIRST instruction will fit | |
8349 | in a single word. | |
c138bc38 | 8350 | |
43cd72b9 BW |
8351 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8352 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8353 | |
43cd72b9 BW |
8354 | If the FIRST instruction MIGHT be relaxed, |
8355 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8356 | |
43cd72b9 BW |
8357 | Note again here that LOOP instructions are not bundleable, |
8358 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8359 | |
d77b99c9 | 8360 | int fill_size = 0; |
43cd72b9 BW |
8361 | int first_insn_size; |
8362 | int loop_insn_size; | |
8363 | addressT pre_opcode_bytes; | |
d77b99c9 | 8364 | int align_power; |
43cd72b9 BW |
8365 | fragS *first_insn; |
8366 | xtensa_opcode opcode; | |
8367 | bfd_boolean is_loop; | |
e0001a05 | 8368 | |
43cd72b9 BW |
8369 | assert (fragP->fr_type == rs_machine_dependent); |
8370 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8371 | |
43cd72b9 BW |
8372 | /* Find the loop frag. */ |
8373 | first_insn = next_non_empty_frag (fragP); | |
8374 | /* Now find the first insn frag. */ | |
8375 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8376 | |
43cd72b9 BW |
8377 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8378 | assert (is_loop); | |
8379 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8380 | |
43cd72b9 BW |
8381 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8382 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8383 | |
43cd72b9 BW |
8384 | /* For loops, the alignment depends on the size of the |
8385 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8386 | |
43cd72b9 | 8387 | if (first_insn == NULL) |
03aaa593 BW |
8388 | first_insn_size = xtensa_fetch_width; |
8389 | else | |
8390 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8391 | |
43cd72b9 | 8392 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8393 | align_power = get_text_align_power (first_insn_size); |
8394 | record_alignment (now_seg, align_power); | |
c138bc38 | 8395 | |
43cd72b9 | 8396 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8397 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8398 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8399 | |
8400 | return address + fill_size; | |
8401 | } | |
8402 | ||
8403 | ||
43cd72b9 BW |
8404 | /* 3 mechanisms for relaxing an alignment: |
8405 | ||
8406 | Align to a power of 2. | |
8407 | Align so the next fragment's instruction does not cross a word boundary. | |
8408 | Align the current instruction so that if the next instruction | |
8409 | were 3 bytes, it would not cross a word boundary. | |
8410 | ||
e0001a05 NC |
8411 | We can align with: |
8412 | ||
43cd72b9 BW |
8413 | zeros - This is easy; always insert zeros. |
8414 | nops - 3-byte and 2-byte instructions | |
8415 | 2 - 2-byte nop | |
8416 | 3 - 3-byte nop | |
8417 | 4 - 2 2-byte nops | |
8418 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8419 | widening - widen previous instructions. */ |
8420 | ||
d77b99c9 BW |
8421 | static offsetT |
8422 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8423 | { |
43cd72b9 BW |
8424 | addressT target_address, loop_insn_offset; |
8425 | int target_size; | |
8426 | xtensa_opcode loop_opcode; | |
8427 | bfd_boolean is_loop; | |
d77b99c9 BW |
8428 | int align_power; |
8429 | offsetT opt_diff; | |
5f9084e9 | 8430 | offsetT branch_align; |
def13efb | 8431 | fragS *loop_frag; |
e0001a05 | 8432 | |
43cd72b9 BW |
8433 | assert (fragP->fr_type == rs_machine_dependent); |
8434 | switch (fragP->fr_subtype) | |
e0001a05 | 8435 | { |
43cd72b9 BW |
8436 | case RELAX_DESIRE_ALIGN: |
8437 | target_size = next_frag_format_size (fragP); | |
8438 | if (target_size == XTENSA_UNDEFINED) | |
8439 | target_size = 3; | |
664df4e4 BW |
8440 | align_power = branch_align_power (now_seg); |
8441 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8442 | /* Don't count on the section alignment being as large as the target. */ |
8443 | if (target_size > branch_align) | |
8444 | target_size = branch_align; | |
d77b99c9 | 8445 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8446 | target_size, FALSE, FALSE); |
8447 | ||
664df4e4 BW |
8448 | *max_diff = (opt_diff + branch_align |
8449 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8450 | assert (*max_diff >= opt_diff); |
8451 | return opt_diff; | |
e0001a05 | 8452 | |
43cd72b9 | 8453 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8454 | /* The next non-empty frag after this one holds the LOOP instruction |
8455 | that needs to be aligned. The required alignment depends on the | |
8456 | size of the next non-empty frag after the loop frag, i.e., the | |
8457 | first instruction in the loop. */ | |
8458 | loop_frag = next_non_empty_frag (fragP); | |
8459 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8460 | loop_insn_offset = 0; |
8461 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8462 | assert (is_loop); | |
8463 | ||
8464 | /* If the loop has been expanded then the LOOP instruction | |
8465 | could be at an offset from this fragment. */ | |
def13efb | 8466 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8467 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8468 | ||
43cd72b9 BW |
8469 | /* In an ideal world, which is what we are shooting for here, |
8470 | we wouldn't need to use any NOPs immediately prior to the | |
8471 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8472 | will call get_noop_aligned_address. */ | |
8473 | target_address = | |
8474 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8475 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8476 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8477 | target_size, FALSE, FALSE); |
8478 | ||
8479 | *max_diff = xtensa_fetch_width | |
8480 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8481 | - target_size + opt_diff; | |
8482 | assert (*max_diff >= opt_diff); | |
8483 | return opt_diff; | |
e0001a05 | 8484 | |
43cd72b9 BW |
8485 | default: |
8486 | break; | |
e0001a05 | 8487 | } |
43cd72b9 BW |
8488 | assert (0); |
8489 | return 0; | |
e0001a05 NC |
8490 | } |
8491 | ||
8492 | \f | |
8493 | /* md_relax_frag Hook and Helper Functions. */ | |
8494 | ||
7fa3d080 BW |
8495 | static long relax_frag_loop_align (fragS *, long); |
8496 | static long relax_frag_for_align (fragS *, long); | |
8497 | static long relax_frag_immed | |
8498 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8499 | ||
8500 | ||
e0001a05 NC |
8501 | /* Return the number of bytes added to this fragment, given that the |
8502 | input has been stretched already by "stretch". */ | |
8503 | ||
8504 | long | |
7fa3d080 | 8505 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8506 | { |
43cd72b9 | 8507 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8508 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8509 | long new_stretch = 0; | |
8510 | char *file_name; | |
d77b99c9 BW |
8511 | unsigned line; |
8512 | int lit_size; | |
43cd72b9 BW |
8513 | static xtensa_insnbuf vbuf = NULL; |
8514 | int slot, num_slots; | |
8515 | xtensa_format fmt; | |
e0001a05 NC |
8516 | |
8517 | as_where (&file_name, &line); | |
8518 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8519 | ||
8520 | fragP->tc_frag_data.unreported_expansion = 0; | |
8521 | ||
8522 | switch (fragP->fr_subtype) | |
8523 | { | |
8524 | case RELAX_ALIGN_NEXT_OPCODE: | |
8525 | /* Always convert. */ | |
43cd72b9 BW |
8526 | if (fragP->tc_frag_data.relax_seen) |
8527 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8528 | break; |
8529 | ||
8530 | case RELAX_LOOP_END: | |
8531 | /* Do nothing. */ | |
8532 | break; | |
8533 | ||
8534 | case RELAX_LOOP_END_ADD_NOP: | |
8535 | /* Add a NOP and switch to .fill 0. */ | |
8536 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8537 | frag_wane (fragP); |
e0001a05 NC |
8538 | break; |
8539 | ||
8540 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8541 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8542 | it or not. */ |
8543 | break; | |
8544 | ||
8545 | case RELAX_LITERAL: | |
8546 | case RELAX_LITERAL_FINAL: | |
8547 | return 0; | |
8548 | ||
8549 | case RELAX_LITERAL_NR: | |
8550 | lit_size = 4; | |
8551 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8552 | assert (unreported == lit_size); | |
8553 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8554 | fragP->fr_var -= lit_size; | |
8555 | fragP->fr_fix += lit_size; | |
8556 | new_stretch = 4; | |
8557 | break; | |
8558 | ||
43cd72b9 BW |
8559 | case RELAX_SLOTS: |
8560 | if (vbuf == NULL) | |
8561 | vbuf = xtensa_insnbuf_alloc (isa); | |
8562 | ||
d77b99c9 BW |
8563 | xtensa_insnbuf_from_chars |
8564 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8565 | fmt = xtensa_format_decode (isa, vbuf); |
8566 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8567 | |
43cd72b9 BW |
8568 | for (slot = 0; slot < num_slots; slot++) |
8569 | { | |
8570 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8571 | { | |
8572 | case RELAX_NARROW: | |
8573 | if (fragP->tc_frag_data.relax_seen) | |
8574 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8575 | break; | |
8576 | ||
8577 | case RELAX_IMMED: | |
8578 | case RELAX_IMMED_STEP1: | |
8579 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8580 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8581 | /* Place the immediate. */ |
8582 | new_stretch += relax_frag_immed | |
8583 | (now_seg, fragP, stretch, | |
8584 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8585 | fmt, slot, stretched_p, FALSE); | |
8586 | break; | |
8587 | ||
8588 | default: | |
8589 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8590 | break; | |
8591 | } | |
8592 | } | |
e0001a05 NC |
8593 | break; |
8594 | ||
8595 | case RELAX_LITERAL_POOL_BEGIN: | |
8596 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8597 | case RELAX_MAYBE_UNREACHABLE: |
8598 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8599 | /* No relaxation required. */ |
8600 | break; | |
8601 | ||
43cd72b9 BW |
8602 | case RELAX_FILL_NOP: |
8603 | case RELAX_UNREACHABLE: | |
8604 | if (fragP->tc_frag_data.relax_seen) | |
8605 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8606 | break; | |
8607 | ||
e0001a05 NC |
8608 | default: |
8609 | as_bad (_("bad relaxation state")); | |
8610 | } | |
8611 | ||
43cd72b9 | 8612 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8613 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8614 | { |
8615 | fragP->tc_frag_data.relax_seen = TRUE; | |
8616 | *stretched_p = 1; | |
8617 | } | |
8618 | ||
e0001a05 NC |
8619 | new_logical_line (file_name, line); |
8620 | return new_stretch; | |
8621 | } | |
8622 | ||
8623 | ||
8624 | static long | |
7fa3d080 | 8625 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8626 | { |
8627 | addressT old_address, old_next_address, old_size; | |
8628 | addressT new_address, new_next_address, new_size; | |
8629 | addressT growth; | |
8630 | ||
43cd72b9 BW |
8631 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8632 | section have been done, hopefully eliminating the need for a NOP here. | |
8633 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8634 | |
8635 | /* Calculate the old address of this fragment and the next fragment. */ | |
8636 | old_address = fragP->fr_address - stretch; | |
8637 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8638 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8639 | old_size = old_next_address - old_address; |
8640 | ||
8641 | /* Calculate the new address of this fragment and the next fragment. */ | |
8642 | new_address = fragP->fr_address; | |
8643 | new_next_address = | |
8644 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8645 | new_size = new_next_address - new_address; | |
8646 | ||
8647 | growth = new_size - old_size; | |
8648 | ||
8649 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8650 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8651 | return growth; |
8652 | } | |
8653 | ||
8654 | ||
43cd72b9 | 8655 | /* Add a NOP instruction. */ |
e0001a05 NC |
8656 | |
8657 | static long | |
7fa3d080 | 8658 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8659 | { |
e0001a05 | 8660 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8661 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8662 | assemble_nop (length, nop_buf); | |
e0001a05 | 8663 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8664 | |
e0001a05 NC |
8665 | if (fragP->fr_var < length) |
8666 | { | |
dd49a749 | 8667 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8668 | return 0; |
8669 | } | |
8670 | ||
8671 | fragP->fr_fix += length; | |
8672 | fragP->fr_var -= length; | |
e0001a05 NC |
8673 | return length; |
8674 | } | |
8675 | ||
8676 | ||
7fa3d080 BW |
8677 | static long future_alignment_required (fragS *, long); |
8678 | ||
e0001a05 | 8679 | static long |
7fa3d080 | 8680 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8681 | { |
43cd72b9 BW |
8682 | /* Overview of the relaxation procedure for alignment: |
8683 | We can widen with NOPs or by widening instructions or by filling | |
8684 | bytes after jump instructions. Find the opportune places and widen | |
8685 | them if necessary. */ | |
8686 | ||
8687 | long stretch_me; | |
8688 | long diff; | |
e0001a05 | 8689 | |
43cd72b9 BW |
8690 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8691 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8692 | || (fragP->fr_subtype == RELAX_SLOTS | |
8693 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8694 | ||
8695 | stretch_me = future_alignment_required (fragP, stretch); | |
8696 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8697 | if (diff == 0) | |
8698 | return 0; | |
e0001a05 | 8699 | |
43cd72b9 | 8700 | if (diff < 0) |
e0001a05 | 8701 | { |
43cd72b9 BW |
8702 | /* We expanded on a previous pass. Can we shrink now? */ |
8703 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8704 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8705 | { |
43cd72b9 BW |
8706 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8707 | return -shrink; | |
e0001a05 NC |
8708 | } |
8709 | return 0; | |
8710 | } | |
8711 | ||
43cd72b9 BW |
8712 | /* Below here, diff > 0. */ |
8713 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8714 | |
43cd72b9 | 8715 | return diff; |
e0001a05 NC |
8716 | } |
8717 | ||
8718 | ||
43cd72b9 BW |
8719 | /* Return the address of the next frag that should be aligned. |
8720 | ||
8721 | By "address" we mean the address it _would_ be at if there | |
8722 | is no action taken to align it between here and the target frag. | |
8723 | In other words, if no narrows and no fill nops are used between | |
8724 | here and the frag to align, _even_if_ some of the frags we use | |
8725 | to align targets have already expanded on a previous relaxation | |
8726 | pass. | |
8727 | ||
8728 | Also, count each frag that may be used to help align the target. | |
8729 | ||
8730 | Return 0 if there are no frags left in the chain that need to be | |
8731 | aligned. */ | |
8732 | ||
8733 | static addressT | |
7fa3d080 BW |
8734 | find_address_of_next_align_frag (fragS **fragPP, |
8735 | int *wide_nops, | |
8736 | int *narrow_nops, | |
8737 | int *widens, | |
8738 | bfd_boolean *paddable) | |
e0001a05 | 8739 | { |
43cd72b9 BW |
8740 | fragS *fragP = *fragPP; |
8741 | addressT address = fragP->fr_address; | |
8742 | ||
8743 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8744 | |
8745 | while (fragP) | |
8746 | { | |
8747 | /* Limit this to a small search. */ | |
b5e4a23d | 8748 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8749 | { |
8750 | *fragPP = fragP; | |
8751 | return 0; | |
8752 | } | |
e0001a05 NC |
8753 | address += fragP->fr_fix; |
8754 | ||
43cd72b9 BW |
8755 | if (fragP->fr_type == rs_fill) |
8756 | address += fragP->fr_offset * fragP->fr_var; | |
8757 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8758 | { |
e0001a05 NC |
8759 | switch (fragP->fr_subtype) |
8760 | { | |
43cd72b9 BW |
8761 | case RELAX_UNREACHABLE: |
8762 | *paddable = TRUE; | |
8763 | break; | |
8764 | ||
8765 | case RELAX_FILL_NOP: | |
8766 | (*wide_nops)++; | |
8767 | if (!fragP->tc_frag_data.is_no_density) | |
8768 | (*narrow_nops)++; | |
8769 | break; | |
8770 | ||
8771 | case RELAX_SLOTS: | |
8772 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8773 | { | |
8774 | (*widens)++; | |
8775 | break; | |
8776 | } | |
34e41783 | 8777 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8778 | break; |
8779 | ||
8780 | case RELAX_IMMED: | |
43cd72b9 | 8781 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8782 | break; |
8783 | ||
8784 | case RELAX_ALIGN_NEXT_OPCODE: | |
8785 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8786 | *fragPP = fragP; |
8787 | return address; | |
8788 | ||
8789 | case RELAX_MAYBE_UNREACHABLE: | |
8790 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8791 | /* Do nothing. */ | |
e0001a05 NC |
8792 | break; |
8793 | ||
8794 | default: | |
43cd72b9 BW |
8795 | /* Just punt if we don't know the type. */ |
8796 | *fragPP = fragP; | |
8797 | return 0; | |
e0001a05 | 8798 | } |
43cd72b9 | 8799 | } |
c138bc38 | 8800 | else |
43cd72b9 BW |
8801 | { |
8802 | /* Just punt if we don't know the type. */ | |
8803 | *fragPP = fragP; | |
8804 | return 0; | |
8805 | } | |
8806 | fragP = fragP->fr_next; | |
8807 | } | |
8808 | ||
8809 | *fragPP = fragP; | |
8810 | return 0; | |
8811 | } | |
8812 | ||
8813 | ||
7fa3d080 BW |
8814 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8815 | ||
43cd72b9 | 8816 | static long |
7fa3d080 | 8817 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8818 | { |
8819 | fragS *this_frag = fragP; | |
8820 | long address; | |
8821 | int num_widens = 0; | |
8822 | int wide_nops = 0; | |
8823 | int narrow_nops = 0; | |
8824 | bfd_boolean paddable = FALSE; | |
8825 | offsetT local_opt_diff; | |
8826 | offsetT opt_diff; | |
8827 | offsetT max_diff; | |
8828 | int stretch_amount = 0; | |
8829 | int local_stretch_amount; | |
8830 | int global_stretch_amount; | |
8831 | ||
7fa3d080 BW |
8832 | address = find_address_of_next_align_frag |
8833 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8834 | |
b5e4a23d BW |
8835 | if (!address) |
8836 | { | |
8837 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8838 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8839 | else | |
8840 | frag_wane (this_frag); | |
8841 | } | |
8842 | else | |
43cd72b9 BW |
8843 | { |
8844 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8845 | opt_diff = local_opt_diff; | |
8846 | assert (opt_diff >= 0); | |
8847 | assert (max_diff >= opt_diff); | |
c138bc38 | 8848 | if (max_diff == 0) |
43cd72b9 | 8849 | return 0; |
d2a033cd | 8850 | |
43cd72b9 BW |
8851 | if (fragP) |
8852 | fragP = fragP->fr_next; | |
8853 | ||
8854 | while (fragP && opt_diff < max_diff && address) | |
8855 | { | |
8856 | /* We only use these to determine if we can exit early | |
c138bc38 | 8857 | because there will be plenty of ways to align future |
43cd72b9 | 8858 | align frags. */ |
d77b99c9 | 8859 | int glob_widens = 0; |
43cd72b9 BW |
8860 | int dnn = 0; |
8861 | int dw = 0; | |
8862 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8863 | address = find_address_of_next_align_frag |
8864 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8865 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8866 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8867 | address = 0; |
43cd72b9 | 8868 | |
c138bc38 | 8869 | if (address) |
43cd72b9 BW |
8870 | { |
8871 | offsetT next_m_diff; | |
8872 | offsetT next_o_diff; | |
8873 | ||
8874 | /* Downrange frags haven't had stretch added to them yet. */ | |
8875 | address += stretch; | |
8876 | ||
8877 | /* The address also includes any text expansion from this | |
8878 | frag in a previous pass, but we don't want that. */ | |
8879 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8880 | ||
8881 | /* Assume we are going to move at least opt_diff. In | |
8882 | reality, we might not be able to, but assuming that | |
8883 | we will helps catch cases where moving opt_diff pushes | |
8884 | the next target from aligned to unaligned. */ | |
8885 | address += opt_diff; | |
8886 | ||
8887 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8888 | ||
8889 | /* Now cleanup for the adjustments to address. */ | |
8890 | next_o_diff += opt_diff; | |
8891 | next_m_diff += opt_diff; | |
8892 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8893 | opt_diff = next_o_diff; | |
8894 | if (next_m_diff < max_diff) | |
8895 | max_diff = next_m_diff; | |
8896 | fragP = fragP->fr_next; | |
8897 | } | |
8898 | } | |
d2a033cd | 8899 | |
43cd72b9 BW |
8900 | /* If there are enough wideners in between, do it. */ |
8901 | if (paddable) | |
8902 | { | |
8903 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8904 | { | |
8905 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8906 | return opt_diff; | |
8907 | } | |
8908 | return 0; | |
8909 | } | |
c138bc38 | 8910 | local_stretch_amount |
43cd72b9 BW |
8911 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8912 | num_widens, local_opt_diff); | |
c138bc38 BW |
8913 | global_stretch_amount |
8914 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8915 | num_widens, opt_diff); |
c138bc38 BW |
8916 | /* If the condition below is true, then the frag couldn't |
8917 | stretch the correct amount for the global case, so we just | |
8918 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8919 | the correct alignment in the global case. */ |
8920 | if (global_stretch_amount < local_stretch_amount) | |
8921 | stretch_amount = local_stretch_amount; | |
8922 | else | |
8923 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8924 | |
43cd72b9 BW |
8925 | if (this_frag->fr_subtype == RELAX_SLOTS |
8926 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8927 | assert (stretch_amount <= 1); | |
8928 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8929 | { | |
8930 | if (this_frag->tc_frag_data.is_no_density) | |
8931 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8932 | else | |
8933 | assert (stretch_amount <= 3); | |
8934 | } | |
8935 | } | |
8936 | return stretch_amount; | |
8937 | } | |
8938 | ||
8939 | ||
8940 | /* The idea: widen everything you can to get a target or loop aligned, | |
8941 | then start using NOPs. | |
8942 | ||
8943 | When we must have a NOP, here is a table of how we decide | |
8944 | (so you don't have to fight through the control flow below): | |
8945 | ||
8946 | wide_nops = the number of wide NOPs available for aligning | |
8947 | narrow_nops = the number of narrow NOPs available for aligning | |
8948 | (a subset of wide_nops) | |
8949 | widens = the number of narrow instructions that should be widened | |
8950 | ||
8951 | Desired wide narrow | |
8952 | Diff nop nop widens | |
8953 | 1 0 0 1 | |
8954 | 2 0 1 0 | |
8955 | 3a 1 0 0 | |
8956 | b 0 1 1 (case 3a makes this case unnecessary) | |
8957 | 4a 1 0 1 | |
8958 | b 0 2 0 | |
8959 | c 0 1 2 (case 4a makes this case unnecessary) | |
8960 | 5a 1 0 2 | |
8961 | b 1 1 0 | |
8962 | c 0 2 1 (case 5b makes this case unnecessary) | |
8963 | 6a 2 0 0 | |
8964 | b 1 0 3 | |
708587a4 | 8965 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8966 | d 1 1 1 (case 6a makes this case unnecessary) |
8967 | e 0 2 2 (case 6a makes this case unnecessary) | |
8968 | f 0 3 0 (case 6a makes this case unnecessary) | |
8969 | 7a 1 0 4 | |
8970 | b 2 0 1 | |
8971 | c 1 1 2 (case 7b makes this case unnecessary) | |
8972 | d 0 1 5 (case 7a makes this case unnecessary) | |
8973 | e 0 2 3 (case 7b makes this case unnecessary) | |
8974 | f 0 3 1 (case 7b makes this case unnecessary) | |
8975 | g 1 2 1 (case 7b makes this case unnecessary) | |
8976 | */ | |
8977 | ||
8978 | static long | |
7fa3d080 BW |
8979 | bytes_to_stretch (fragS *this_frag, |
8980 | int wide_nops, | |
8981 | int narrow_nops, | |
8982 | int num_widens, | |
8983 | int desired_diff) | |
43cd72b9 BW |
8984 | { |
8985 | int bytes_short = desired_diff - num_widens; | |
8986 | ||
8987 | assert (desired_diff >= 0 && desired_diff < 8); | |
8988 | if (desired_diff == 0) | |
8989 | return 0; | |
c138bc38 | 8990 | |
43cd72b9 | 8991 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8992 | |
43cd72b9 BW |
8993 | /* Always prefer widening to NOP-filling. */ |
8994 | if (bytes_short < 0) | |
8995 | { | |
8996 | /* There are enough RELAX_NARROW frags after this one | |
8997 | to align the target without widening this frag in any way. */ | |
8998 | return 0; | |
8999 | } | |
c138bc38 | 9000 | |
43cd72b9 BW |
9001 | if (bytes_short == 0) |
9002 | { | |
9003 | /* Widen every narrow between here and the align target | |
9004 | and the align target will be properly aligned. */ | |
9005 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9006 | return 0; | |
9007 | else | |
9008 | return 1; | |
9009 | } | |
c138bc38 | 9010 | |
43cd72b9 BW |
9011 | /* From here we will need at least one NOP to get an alignment. |
9012 | However, we may not be able to align at all, in which case, | |
9013 | don't widen. */ | |
9014 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9015 | { | |
9016 | switch (desired_diff) | |
9017 | { | |
9018 | case 1: | |
9019 | return 0; | |
9020 | case 2: | |
9021 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
9022 | return 2; /* case 2 */ | |
9023 | return 0; | |
c138bc38 | 9024 | case 3: |
43cd72b9 BW |
9025 | if (wide_nops > 1) |
9026 | return 0; | |
9027 | else | |
9028 | return 3; /* case 3a */ | |
9029 | case 4: | |
9030 | if (num_widens >= 1 && wide_nops == 1) | |
9031 | return 3; /* case 4a */ | |
9032 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
9033 | return 2; /* case 4b */ | |
9034 | return 0; | |
9035 | case 5: | |
9036 | if (num_widens >= 2 && wide_nops == 1) | |
9037 | return 3; /* case 5a */ | |
c138bc38 | 9038 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
9039 | between here and the align target? */ |
9040 | if (wide_nops < 2 || narrow_nops == 0) | |
9041 | return 0; | |
9042 | /* Are there other nops closer that can serve instead? */ | |
9043 | if (wide_nops > 2 && narrow_nops > 1) | |
9044 | return 0; | |
9045 | /* Take the density one first, because there might not be | |
9046 | another density one available. */ | |
9047 | if (!this_frag->tc_frag_data.is_no_density) | |
9048 | return 2; /* case 5b narrow */ | |
9049 | else | |
9050 | return 3; /* case 5b wide */ | |
9051 | return 0; | |
9052 | case 6: | |
9053 | if (wide_nops == 2) | |
9054 | return 3; /* case 6a */ | |
9055 | else if (num_widens >= 3 && wide_nops == 1) | |
9056 | return 3; /* case 6b */ | |
9057 | return 0; | |
9058 | case 7: | |
9059 | if (wide_nops == 1 && num_widens >= 4) | |
9060 | return 3; /* case 7a */ | |
9061 | else if (wide_nops == 2 && num_widens >= 1) | |
9062 | return 3; /* case 7b */ | |
9063 | return 0; | |
e0001a05 | 9064 | default: |
43cd72b9 | 9065 | assert (0); |
e0001a05 | 9066 | } |
e0001a05 | 9067 | } |
43cd72b9 BW |
9068 | else |
9069 | { | |
c138bc38 | 9070 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 9071 | this instruction to help? |
e0001a05 | 9072 | |
03aaa593 | 9073 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
9074 | switch (desired_diff) |
9075 | { | |
9076 | case 1: | |
9077 | assert (0); | |
9078 | return 0; | |
9079 | case 2: | |
9080 | case 3: | |
9081 | return 0; | |
9082 | case 4: | |
9083 | if (wide_nops >= 1 && num_widens == 1) | |
9084 | return 1; /* case 4a */ | |
9085 | return 0; | |
9086 | case 5: | |
9087 | if (wide_nops >= 1 && num_widens == 2) | |
9088 | return 1; /* case 5a */ | |
9089 | return 0; | |
9090 | case 6: | |
9091 | if (wide_nops >= 2) | |
9092 | return 0; /* case 6a */ | |
9093 | else if (wide_nops >= 1 && num_widens == 3) | |
9094 | return 1; /* case 6b */ | |
9095 | return 0; | |
9096 | case 7: | |
9097 | if (wide_nops >= 1 && num_widens == 4) | |
9098 | return 1; /* case 7a */ | |
9099 | else if (wide_nops >= 2 && num_widens == 1) | |
9100 | return 1; /* case 7b */ | |
9101 | return 0; | |
9102 | default: | |
9103 | assert (0); | |
9104 | return 0; | |
9105 | } | |
9106 | } | |
9107 | assert (0); | |
9108 | return 0; | |
e0001a05 NC |
9109 | } |
9110 | ||
9111 | ||
9112 | static long | |
7fa3d080 BW |
9113 | relax_frag_immed (segT segP, |
9114 | fragS *fragP, | |
9115 | long stretch, | |
9116 | int min_steps, | |
9117 | xtensa_format fmt, | |
9118 | int slot, | |
9119 | int *stretched_p, | |
9120 | bfd_boolean estimate_only) | |
e0001a05 | 9121 | { |
43cd72b9 | 9122 | TInsn tinsn; |
e0001a05 NC |
9123 | int old_size; |
9124 | bfd_boolean negatable_branch = FALSE; | |
9125 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 9126 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 9127 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9128 | IStack istack; |
9129 | offsetT frag_offset; | |
9130 | int num_steps; | |
e0001a05 | 9131 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 9132 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 NC |
9133 | |
9134 | assert (fragP->fr_opcode != NULL); | |
9135 | ||
b5e4a23d BW |
9136 | xg_clear_vinsn (&cur_vinsn); |
9137 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 9138 | if (cur_vinsn.num_slots > 1) |
def13efb | 9139 | from_wide_insn = TRUE; |
43cd72b9 | 9140 | |
b5e4a23d | 9141 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 9142 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 9143 | |
64b607e6 | 9144 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 9145 | return 0; |
e0001a05 | 9146 | |
b08b5071 | 9147 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9148 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 9149 | |
43cd72b9 | 9150 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 9151 | |
43cd72b9 | 9152 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9153 | |
9154 | /* Special case: replace a branch to the next instruction with a NOP. | |
9155 | This is required to work around a hardware bug in T1040.0 and also | |
9156 | serves as an optimization. */ | |
9157 | ||
9158 | if (branch_jmp_to_next | |
9159 | && ((old_size == 2) || (old_size == 3)) | |
9160 | && !next_frag_is_loop_target (fragP)) | |
9161 | return 0; | |
9162 | ||
9163 | /* Here is the fun stuff: Get the immediate field from this | |
9164 | instruction. If it fits, we are done. If not, find the next | |
9165 | instruction sequence that fits. */ | |
9166 | ||
9167 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9168 | istack_init (&istack); | |
43cd72b9 | 9169 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 9170 | min_steps, stretch); |
2276bc20 | 9171 | assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 9172 | |
43cd72b9 | 9173 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9174 | |
9175 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 9176 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
9177 | literal_diff |
9178 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 9179 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
9180 | |
9181 | if (from_wide_insn) | |
43cd72b9 | 9182 | { |
2276bc20 BW |
9183 | int first = 0; |
9184 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9185 | first++; | |
9186 | ||
43cd72b9 BW |
9187 | num_text_bytes += old_size; |
9188 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9189 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
9190 | else |
9191 | { | |
9192 | /* The first instruction in the relaxed sequence will go after | |
9193 | the current wide instruction, and thus its symbolic immediates | |
9194 | might not fit. */ | |
9195 | ||
9196 | istack_init (&istack); | |
9197 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, | |
9198 | frag_offset + old_size, | |
9199 | min_steps, stretch + old_size); | |
9200 | assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); | |
9201 | ||
9202 | fragP->tc_frag_data.slot_subtypes[slot] | |
9203 | = (int) RELAX_IMMED + num_steps; | |
9204 | ||
9205 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
9206 | literal_diff | |
9207 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9208 | ||
9209 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; | |
9210 | } | |
43cd72b9 | 9211 | } |
def13efb | 9212 | |
43cd72b9 BW |
9213 | total_text_diff = num_text_bytes - old_size; |
9214 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9215 | |
9216 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
9217 | assert (num_text_bytes >= 0); |
9218 | assert (literal_diff >= 0); | |
9219 | assert (total_text_diff >= 0); | |
e0001a05 | 9220 | |
43cd72b9 BW |
9221 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9222 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9223 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
9224 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9225 | |
9226 | /* Find the associated expandable literal for this. */ | |
9227 | if (literal_diff != 0) | |
9228 | { | |
2276bc20 | 9229 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9230 | if (lit_fragP) |
9231 | { | |
9232 | assert (literal_diff == 4); | |
9233 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
9234 | ||
9235 | /* We expect that the literal section state has NOT been | |
9236 | modified yet. */ | |
9237 | assert (lit_fragP->fr_type == rs_machine_dependent | |
9238 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
9239 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9240 | ||
9241 | /* We need to mark this section for another iteration | |
9242 | of relaxation. */ | |
9243 | (*stretched_p)++; | |
9244 | } | |
9245 | } | |
9246 | ||
43cd72b9 | 9247 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9248 | update_next_frag_state (fragP); |
e0001a05 | 9249 | |
43cd72b9 | 9250 | return this_text_diff; |
e0001a05 NC |
9251 | } |
9252 | ||
9253 | \f | |
9254 | /* md_convert_frag Hook and Helper Functions. */ | |
9255 | ||
7fa3d080 BW |
9256 | static void convert_frag_align_next_opcode (fragS *); |
9257 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9258 | static void convert_frag_fill_nop (fragS *); | |
9259 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9260 | ||
e0001a05 | 9261 | void |
7fa3d080 | 9262 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9263 | { |
43cd72b9 BW |
9264 | static xtensa_insnbuf vbuf = NULL; |
9265 | xtensa_isa isa = xtensa_default_isa; | |
9266 | int slot; | |
9267 | int num_slots; | |
9268 | xtensa_format fmt; | |
e0001a05 | 9269 | char *file_name; |
d77b99c9 | 9270 | unsigned line; |
e0001a05 NC |
9271 | |
9272 | as_where (&file_name, &line); | |
9273 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9274 | ||
9275 | switch (fragp->fr_subtype) | |
9276 | { | |
9277 | case RELAX_ALIGN_NEXT_OPCODE: | |
9278 | /* Always convert. */ | |
9279 | convert_frag_align_next_opcode (fragp); | |
9280 | break; | |
9281 | ||
9282 | case RELAX_DESIRE_ALIGN: | |
9283 | /* Do nothing. If not aligned already, too bad. */ | |
9284 | break; | |
9285 | ||
43cd72b9 BW |
9286 | case RELAX_LITERAL: |
9287 | case RELAX_LITERAL_FINAL: | |
9288 | break; | |
9289 | ||
9290 | case RELAX_SLOTS: | |
9291 | if (vbuf == NULL) | |
9292 | vbuf = xtensa_insnbuf_alloc (isa); | |
9293 | ||
d77b99c9 BW |
9294 | xtensa_insnbuf_from_chars |
9295 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9296 | fmt = xtensa_format_decode (isa, vbuf); |
9297 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9298 | ||
9299 | for (slot = 0; slot < num_slots; slot++) | |
9300 | { | |
9301 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9302 | { | |
9303 | case RELAX_NARROW: | |
9304 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9305 | break; | |
9306 | ||
9307 | case RELAX_IMMED: | |
9308 | case RELAX_IMMED_STEP1: | |
9309 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9310 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9311 | /* Place the immediate. */ |
9312 | convert_frag_immed | |
9313 | (sec, fragp, | |
9314 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9315 | fmt, slot); | |
9316 | break; | |
9317 | ||
9318 | default: | |
9319 | /* This is OK because some slots could have | |
9320 | relaxations and others have none. */ | |
9321 | break; | |
9322 | } | |
9323 | } | |
9324 | break; | |
9325 | ||
9326 | case RELAX_UNREACHABLE: | |
9327 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9328 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9329 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9330 | frag_wane (fragp); | |
e0001a05 NC |
9331 | break; |
9332 | ||
43cd72b9 BW |
9333 | case RELAX_MAYBE_UNREACHABLE: |
9334 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9335 | frag_wane (fragp); | |
e0001a05 NC |
9336 | break; |
9337 | ||
43cd72b9 BW |
9338 | case RELAX_FILL_NOP: |
9339 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9340 | break; |
9341 | ||
9342 | case RELAX_LITERAL_NR: | |
9343 | if (use_literal_section) | |
9344 | { | |
9345 | /* This should have been handled during relaxation. When | |
9346 | relaxing a code segment, literals sometimes need to be | |
9347 | added to the corresponding literal segment. If that | |
9348 | literal segment has already been relaxed, then we end up | |
9349 | in this situation. Marking the literal segments as data | |
9350 | would make this happen less often (since GAS always relaxes | |
9351 | code before data), but we could still get into trouble if | |
9352 | there are instructions in a segment that is not marked as | |
9353 | containing code. Until we can implement a better solution, | |
9354 | cheat and adjust the addresses of all the following frags. | |
9355 | This could break subsequent alignments, but the linker's | |
9356 | literal coalescing will do that anyway. */ | |
9357 | ||
9358 | fragS *f; | |
9359 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9360 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9361 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9362 | fragp->fr_var -= 4; | |
9363 | fragp->fr_fix += 4; | |
9364 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9365 | f->fr_address += 4; | |
9366 | } | |
9367 | else | |
9368 | as_bad (_("invalid relaxation fragment result")); | |
9369 | break; | |
9370 | } | |
9371 | ||
9372 | fragp->fr_var = 0; | |
9373 | new_logical_line (file_name, line); | |
9374 | } | |
9375 | ||
9376 | ||
7fa3d080 BW |
9377 | static void |
9378 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9379 | { |
9380 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9381 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9382 | addressT aligned_address; | |
d77b99c9 BW |
9383 | offsetT fill_size; |
9384 | int nop, nop_count; | |
e0001a05 NC |
9385 | |
9386 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9387 | fragp->fr_fix); | |
9388 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9389 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9390 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9391 | ||
d77b99c9 | 9392 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9393 | { |
d77b99c9 BW |
9394 | int nop_size; |
9395 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9396 | |
9397 | assemble_nop (nop_size, nop_buf); | |
9398 | nop_buf += nop_size; | |
9399 | } | |
9400 | ||
9401 | fragp->fr_fix += fill_size; | |
9402 | fragp->fr_var -= fill_size; | |
9403 | } | |
9404 | ||
9405 | ||
9406 | static void | |
7fa3d080 | 9407 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9408 | { |
43cd72b9 | 9409 | TInsn tinsn, single_target; |
84b08ed9 | 9410 | int size, old_size, diff; |
e0001a05 NC |
9411 | offsetT frag_offset; |
9412 | ||
43cd72b9 BW |
9413 | assert (slot == 0); |
9414 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9415 | ||
b5e4a23d | 9416 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9417 | { |
9418 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9419 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9420 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9421 | fmt, slot); | |
9422 | return; | |
9423 | } | |
9424 | ||
9425 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9426 | { |
9427 | /* No conversion. */ | |
9428 | fragP->fr_var = 0; | |
9429 | return; | |
9430 | } | |
9431 | ||
9432 | assert (fragP->fr_opcode != NULL); | |
9433 | ||
43cd72b9 BW |
9434 | /* Frags in this relaxation state should only contain |
9435 | single instruction bundles. */ | |
9436 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9437 | |
9438 | /* Just convert it to a wide form.... */ | |
9439 | size = 0; | |
43cd72b9 | 9440 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9441 | |
9442 | tinsn_init (&single_target); | |
9443 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9444 | ||
84b08ed9 | 9445 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9446 | { |
9447 | as_bad (_("unable to widen instruction")); | |
9448 | return; | |
9449 | } | |
9450 | ||
9451 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9452 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9453 | frag_offset, TRUE); | |
e0001a05 NC |
9454 | |
9455 | diff = size - old_size; | |
9456 | assert (diff >= 0); | |
9457 | assert (diff <= fragP->fr_var); | |
9458 | fragP->fr_var -= diff; | |
9459 | fragP->fr_fix += diff; | |
9460 | ||
9461 | /* clean it up */ | |
9462 | fragP->fr_var = 0; | |
9463 | } | |
9464 | ||
9465 | ||
9466 | static void | |
7fa3d080 | 9467 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9468 | { |
9469 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9470 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9471 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9472 | - fragP->fr_address - fragP->fr_fix)); | |
9473 | if (size == 0) | |
9474 | { | |
9475 | /* No conversion. */ | |
9476 | fragP->fr_var = 0; | |
9477 | return; | |
9478 | } | |
9479 | assemble_nop (size, loc); | |
9480 | fragP->tc_frag_data.is_insn = TRUE; | |
9481 | fragP->fr_var -= size; | |
9482 | fragP->fr_fix += size; | |
9483 | frag_wane (fragP); | |
9484 | } | |
9485 | ||
9486 | ||
7fa3d080 BW |
9487 | static fixS *fix_new_exp_in_seg |
9488 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9489 | bfd_reloc_code_real_type); | |
9490 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9491 | ||
43cd72b9 | 9492 | static void |
7fa3d080 BW |
9493 | convert_frag_immed (segT segP, |
9494 | fragS *fragP, | |
9495 | int min_steps, | |
9496 | xtensa_format fmt, | |
9497 | int slot) | |
e0001a05 NC |
9498 | { |
9499 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9500 | TInsn orig_tinsn; |
e0001a05 | 9501 | bfd_boolean expanded = FALSE; |
e0001a05 | 9502 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9503 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 9504 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 9505 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
9506 | int bytes; |
9507 | bfd_boolean is_loop; | |
e0001a05 | 9508 | |
43cd72b9 | 9509 | assert (fr_opcode != NULL); |
e0001a05 | 9510 | |
b5e4a23d | 9511 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9512 | |
b5e4a23d | 9513 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9514 | if (cur_vinsn.num_slots > 1) |
def13efb | 9515 | from_wide_insn = TRUE; |
e0001a05 | 9516 | |
b5e4a23d | 9517 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9518 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9519 | ||
9520 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9521 | |
b08b5071 | 9522 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9523 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9524 | |
9525 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9526 | { | |
9527 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9528 | bytes = xtensa_format_length (isa, fmt); |
9529 | if (bytes >= 4) | |
9530 | { | |
b5e4a23d BW |
9531 | cur_vinsn.slots[slot].opcode = |
9532 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9533 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9534 | } |
9535 | else | |
9536 | { | |
9537 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9538 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9539 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9540 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9541 | } | |
e7da6241 | 9542 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9543 | xtensa_insnbuf_to_chars |
b5e4a23d | 9544 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9545 | fragP->fr_var = 0; |
9546 | } | |
7c834684 | 9547 | else |
e0001a05 | 9548 | { |
43cd72b9 BW |
9549 | /* Here is the fun stuff: Get the immediate field from this |
9550 | instruction. If it fits, we're done. If not, find the next | |
9551 | instruction sequence that fits. */ | |
9552 | ||
e0001a05 NC |
9553 | IStack istack; |
9554 | int i; | |
9555 | symbolS *lit_sym = NULL; | |
9556 | int total_size = 0; | |
43cd72b9 | 9557 | int target_offset = 0; |
e0001a05 NC |
9558 | int old_size; |
9559 | int diff; | |
9560 | symbolS *gen_label = NULL; | |
9561 | offsetT frag_offset; | |
43cd72b9 BW |
9562 | bfd_boolean first = TRUE; |
9563 | bfd_boolean last_is_jump; | |
e0001a05 | 9564 | |
43cd72b9 | 9565 | /* It does not fit. Find something that does and |
e0001a05 | 9566 | convert immediately. */ |
43cd72b9 | 9567 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9568 | istack_init (&istack); |
43cd72b9 | 9569 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9570 | segP, fragP, frag_offset, min_steps, 0); |
9571 | ||
43cd72b9 | 9572 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9573 | |
9574 | /* Assemble this right inline. */ | |
9575 | ||
9576 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9577 | target_offset = 0; |
e0001a05 NC |
9578 | for (i = 0; i < istack.ninsn; i++) |
9579 | { | |
43cd72b9 | 9580 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9581 | fragS *lit_frag; |
9582 | ||
43cd72b9 | 9583 | switch (tinsn->insn_type) |
e0001a05 NC |
9584 | { |
9585 | case ITYPE_LITERAL: | |
9586 | if (lit_sym != NULL) | |
9587 | as_bad (_("multiple literals in expansion")); | |
9588 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9589 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9590 | if (lit_frag == NULL) |
9591 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9592 | if (tinsn->ntok != 1) |
e0001a05 NC |
9593 | as_bad (_("number of literal tokens != 1")); |
9594 | ||
9595 | /* Set the literal symbol and add a fixup. */ | |
9596 | lit_sym = lit_frag->fr_symbol; | |
9597 | break; | |
9598 | ||
9599 | case ITYPE_LABEL: | |
43cd72b9 BW |
9600 | if (align_targets && !is_loop) |
9601 | { | |
9602 | fragS *unreach = fragP->fr_next; | |
9603 | while (!(unreach->fr_type == rs_machine_dependent | |
9604 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9605 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9606 | { | |
9607 | unreach = unreach->fr_next; | |
9608 | } | |
9609 | ||
9610 | assert (unreach->fr_type == rs_machine_dependent | |
9611 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9612 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9613 | ||
9614 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9615 | } | |
e0001a05 NC |
9616 | assert (gen_label == NULL); |
9617 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9618 | fr_opcode - fragP->fr_literal |
9619 | + target_offset, fragP); | |
e0001a05 NC |
9620 | break; |
9621 | ||
9622 | case ITYPE_INSN: | |
def13efb | 9623 | if (first && from_wide_insn) |
43cd72b9 BW |
9624 | { |
9625 | target_offset += xtensa_format_length (isa, fmt); | |
9626 | first = FALSE; | |
9627 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9628 | target_offset += xg_get_single_size (tinsn->opcode); | |
9629 | } | |
9630 | else | |
9631 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9632 | break; |
9633 | } | |
9634 | } | |
9635 | ||
9636 | total_size = 0; | |
43cd72b9 BW |
9637 | first = TRUE; |
9638 | last_is_jump = FALSE; | |
e0001a05 NC |
9639 | for (i = 0; i < istack.ninsn; i++) |
9640 | { | |
43cd72b9 | 9641 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9642 | fragS *lit_frag; |
9643 | int size; | |
9644 | segT target_seg; | |
43cd72b9 | 9645 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9646 | |
43cd72b9 | 9647 | switch (tinsn->insn_type) |
e0001a05 NC |
9648 | { |
9649 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9650 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9651 | /* Already checked. */ | |
e0001a05 NC |
9652 | assert (lit_frag != NULL); |
9653 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9654 | assert (tinsn->ntok == 1); |
9655 | /* Add a fixup. */ | |
e0001a05 NC |
9656 | target_seg = S_GET_SEGMENT (lit_sym); |
9657 | assert (target_seg); | |
28dbbc02 | 9658 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 9659 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9660 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9661 | break; |
9662 | ||
9663 | case ITYPE_LABEL: | |
9664 | break; | |
9665 | ||
9666 | case ITYPE_INSN: | |
43cd72b9 BW |
9667 | xg_resolve_labels (tinsn, gen_label); |
9668 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 9669 | if (from_wide_insn && first) |
43cd72b9 BW |
9670 | { |
9671 | first = FALSE; | |
9672 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9673 | { | |
b5e4a23d | 9674 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9675 | } |
9676 | else | |
9677 | { | |
b5e4a23d | 9678 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9679 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9680 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9681 | } |
b5e4a23d BW |
9682 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9683 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9684 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9685 | fragP->tc_frag_data.is_insn = TRUE; |
9686 | size = xtensa_format_length (isa, fmt); | |
9687 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9688 | { | |
43cd72b9 | 9689 | xg_emit_insn_to_buf |
b2d179be | 9690 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9691 | immed_instr - fragP->fr_literal + size, TRUE); |
9692 | size += xg_get_single_size (tinsn->opcode); | |
9693 | } | |
9694 | } | |
9695 | else | |
9696 | { | |
43cd72b9 | 9697 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9698 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9699 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9700 | } |
e0001a05 | 9701 | immed_instr += size; |
43cd72b9 | 9702 | total_size += size; |
e0001a05 NC |
9703 | break; |
9704 | } | |
9705 | } | |
9706 | ||
9707 | diff = total_size - old_size; | |
9708 | assert (diff >= 0); | |
9709 | if (diff != 0) | |
9710 | expanded = TRUE; | |
9711 | assert (diff <= fragP->fr_var); | |
9712 | fragP->fr_var -= diff; | |
9713 | fragP->fr_fix += diff; | |
9714 | } | |
9715 | ||
e0001a05 | 9716 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9717 | if (is_loop) |
e0001a05 NC |
9718 | { |
9719 | symbolS *sym; | |
43cd72b9 | 9720 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9721 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9722 | { | |
9723 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9724 | return; | |
9725 | } | |
43cd72b9 | 9726 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9727 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9728 | { | |
9729 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9730 | return; | |
9731 | } | |
9732 | } | |
9733 | ||
43cd72b9 BW |
9734 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9735 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9736 | |
43cd72b9 | 9737 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9738 | { |
9739 | /* Add an expansion note on the expanded instruction. */ | |
9740 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9741 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9742 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9743 | } |
9744 | } | |
9745 | ||
9746 | ||
9747 | /* Add a new fix expression into the desired segment. We have to | |
9748 | switch to that segment to do this. */ | |
9749 | ||
9750 | static fixS * | |
7fa3d080 BW |
9751 | fix_new_exp_in_seg (segT new_seg, |
9752 | subsegT new_subseg, | |
9753 | fragS *frag, | |
9754 | int where, | |
9755 | int size, | |
9756 | expressionS *exp, | |
9757 | int pcrel, | |
9758 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9759 | { |
9760 | fixS *new_fix; | |
9761 | segT seg = now_seg; | |
9762 | subsegT subseg = now_subseg; | |
43cd72b9 | 9763 | |
e0001a05 NC |
9764 | assert (new_seg != 0); |
9765 | subseg_set (new_seg, new_subseg); | |
9766 | ||
e0001a05 NC |
9767 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9768 | subseg_set (seg, subseg); | |
9769 | return new_fix; | |
9770 | } | |
9771 | ||
9772 | ||
43cd72b9 BW |
9773 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9774 | ||
9775 | loop as, .L1 | |
9776 | .L0: | |
9777 | rsr as, LEND | |
9778 | wsr as, LBEG | |
9779 | addi as, as, lo8 (label-.L1) | |
9780 | addmi as, as, mid8 (label-.L1) | |
9781 | wsr as, LEND | |
9782 | isync | |
9783 | rsr as, LCOUNT | |
9784 | addi as, as, 1 | |
9785 | .L1: | |
9786 | <<body>> | |
9787 | label: | |
9788 | */ | |
e0001a05 NC |
9789 | |
9790 | static void | |
7fa3d080 | 9791 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9792 | { |
9793 | TInsn loop_insn; | |
9794 | TInsn addi_insn; | |
9795 | TInsn addmi_insn; | |
9796 | unsigned long target; | |
9797 | static xtensa_insnbuf insnbuf = NULL; | |
9798 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9799 | xtensa_isa isa = xtensa_default_isa; | |
9800 | addressT loop_offset; | |
9801 | addressT addi_offset = 9; | |
9802 | addressT addmi_offset = 12; | |
43cd72b9 | 9803 | fragS *next_fragP; |
d77b99c9 | 9804 | int target_count; |
e0001a05 NC |
9805 | |
9806 | if (!insnbuf) | |
9807 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9808 | ||
9809 | /* Get the loop offset. */ | |
43cd72b9 | 9810 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9811 | |
43cd72b9 BW |
9812 | /* Validate that there really is a LOOP at the loop_offset. Because |
9813 | loops are not bundleable, we can assume that the instruction will be | |
9814 | in slot 0. */ | |
9815 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9816 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9817 | ||
9818 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9819 | addi_offset += loop_offset; |
9820 | addmi_offset += loop_offset; | |
9821 | ||
43cd72b9 | 9822 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9823 | if (tinsn->tok[1].X_op == O_constant) |
9824 | target = tinsn->tok[1].X_add_number; | |
9825 | else if (tinsn->tok[1].X_op == O_symbol) | |
9826 | { | |
9827 | /* Find the fragment. */ | |
9828 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9829 | assert (S_GET_SEGMENT (sym) == segP | |
9830 | || S_GET_SEGMENT (sym) == absolute_section); | |
9831 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9832 | } | |
9833 | else | |
9834 | { | |
9835 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9836 | target = 0; | |
9837 | } | |
e0001a05 | 9838 | |
e0001a05 NC |
9839 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9840 | loop_length_hi = loop_length & ~0x0ff; | |
9841 | loop_length_lo = loop_length & 0x0ff; | |
9842 | if (loop_length_lo >= 128) | |
9843 | { | |
9844 | loop_length_lo -= 256; | |
9845 | loop_length_hi += 256; | |
9846 | } | |
9847 | ||
43cd72b9 | 9848 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9849 | 32512. If the loop is larger than that, then we just fail. */ |
9850 | if (loop_length_hi > 32512) | |
9851 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9852 | _("loop too long for LOOP instruction")); | |
9853 | ||
43cd72b9 | 9854 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9855 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9856 | ||
43cd72b9 | 9857 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9858 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9859 | ||
9860 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9861 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9862 | |
e0001a05 | 9863 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9864 | xtensa_insnbuf_to_chars |
9865 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9866 | |
9867 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9868 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9869 | xtensa_insnbuf_to_chars |
9870 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9871 | |
9872 | /* Walk through all of the frags from here to the loop end | |
9873 | and mark them as no_transform to keep them from being modified | |
9874 | by the linker. If we ever have a relocation for the | |
9875 | addi/addmi of the difference of two symbols we can remove this. */ | |
9876 | ||
9877 | target_count = 0; | |
9878 | for (next_fragP = fragP; next_fragP != NULL; | |
9879 | next_fragP = next_fragP->fr_next) | |
9880 | { | |
b08b5071 | 9881 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9882 | if (next_fragP->tc_frag_data.is_loop_target) |
9883 | target_count++; | |
9884 | if (target_count == 2) | |
9885 | break; | |
9886 | } | |
e0001a05 NC |
9887 | } |
9888 | ||
b08b5071 BW |
9889 | \f |
9890 | /* A map that keeps information on a per-subsegment basis. This is | |
9891 | maintained during initial assembly, but is invalid once the | |
9892 | subsegments are smashed together. I.E., it cannot be used during | |
9893 | the relaxation. */ | |
e0001a05 | 9894 | |
b08b5071 | 9895 | typedef struct subseg_map_struct |
e0001a05 | 9896 | { |
b08b5071 BW |
9897 | /* the key */ |
9898 | segT seg; | |
9899 | subsegT subseg; | |
e0001a05 | 9900 | |
b08b5071 BW |
9901 | /* the data */ |
9902 | unsigned flags; | |
9903 | float total_freq; /* fall-through + branch target frequency */ | |
9904 | float target_freq; /* branch target frequency alone */ | |
9905 | ||
9906 | struct subseg_map_struct *next; | |
9907 | } subseg_map; | |
e0001a05 | 9908 | |
e0001a05 | 9909 | |
e0001a05 NC |
9910 | static subseg_map *sseg_map = NULL; |
9911 | ||
43cd72b9 | 9912 | static subseg_map * |
7fa3d080 | 9913 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9914 | { |
9915 | subseg_map *subseg_e; | |
9916 | ||
9917 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9918 | { |
43cd72b9 | 9919 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9920 | break; |
e0001a05 | 9921 | } |
b08b5071 BW |
9922 | return subseg_e; |
9923 | } | |
9924 | ||
9925 | ||
9926 | static subseg_map * | |
9927 | add_subseg_info (segT seg, subsegT subseg) | |
9928 | { | |
9929 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9930 | memset (subseg_e, 0, sizeof (subseg_map)); |
9931 | subseg_e->seg = seg; | |
9932 | subseg_e->subseg = subseg; | |
9933 | subseg_e->flags = 0; | |
9934 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9935 | subseg_e->target_freq = 1.0; |
9936 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9937 | subseg_e->next = sseg_map; |
9938 | sseg_map = subseg_e; | |
43cd72b9 BW |
9939 | return subseg_e; |
9940 | } | |
e0001a05 | 9941 | |
7fa3d080 BW |
9942 | |
9943 | static unsigned | |
9944 | get_last_insn_flags (segT seg, subsegT subseg) | |
9945 | { | |
9946 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9947 | if (subseg_e) |
9948 | return subseg_e->flags; | |
9949 | return 0; | |
7fa3d080 BW |
9950 | } |
9951 | ||
9952 | ||
43cd72b9 | 9953 | static void |
7fa3d080 BW |
9954 | set_last_insn_flags (segT seg, |
9955 | subsegT subseg, | |
9956 | unsigned fl, | |
9957 | bfd_boolean val) | |
43cd72b9 BW |
9958 | { |
9959 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9960 | if (! subseg_e) |
9961 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9962 | if (val) |
9963 | subseg_e->flags |= fl; | |
9964 | else | |
9965 | subseg_e->flags &= ~fl; | |
9966 | } | |
9967 | ||
b08b5071 BW |
9968 | |
9969 | static float | |
9970 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9971 | { | |
9972 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9973 | if (subseg_e) | |
9974 | return subseg_e->total_freq; | |
9975 | return 1.0; | |
9976 | } | |
9977 | ||
9978 | ||
9979 | static float | |
9980 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9981 | { | |
9982 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9983 | if (subseg_e) | |
9984 | return subseg_e->target_freq; | |
9985 | return 1.0; | |
9986 | } | |
9987 | ||
9988 | ||
9989 | static void | |
9990 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9991 | { | |
9992 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9993 | if (! subseg_e) | |
9994 | subseg_e = add_subseg_info (seg, subseg); | |
9995 | subseg_e->total_freq = total_f; | |
9996 | subseg_e->target_freq = target_f; | |
9997 | } | |
9998 | ||
e0001a05 NC |
9999 | \f |
10000 | /* Segment Lists and emit_state Stuff. */ | |
10001 | ||
e0001a05 | 10002 | static void |
7fa3d080 | 10003 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
10004 | { |
10005 | head = head->next; | |
10006 | while (head) | |
10007 | { | |
10008 | segT literal_section = head->seg; | |
10009 | ||
10010 | /* Move the literal section to the front of the section list. */ | |
10011 | assert (literal_section); | |
69852798 AM |
10012 | if (literal_section != stdoutput->sections) |
10013 | { | |
10014 | bfd_section_list_remove (stdoutput, literal_section); | |
10015 | bfd_section_list_prepend (stdoutput, literal_section); | |
10016 | } | |
e0001a05 NC |
10017 | head = head->next; |
10018 | } | |
10019 | } | |
10020 | ||
10021 | ||
7fa3d080 BW |
10022 | static void mark_literal_frags (seg_list *); |
10023 | ||
10024 | static void | |
10025 | xtensa_move_literals (void) | |
e0001a05 NC |
10026 | { |
10027 | seg_list *segment; | |
10028 | frchainS *frchain_from, *frchain_to; | |
10029 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
10030 | fragS **frag_splice; | |
10031 | emit_state state; | |
10032 | segT dest_seg; | |
10033 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 10034 | sym_list *lit; |
e0001a05 | 10035 | |
a7877748 | 10036 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
10037 | |
10038 | if (use_literal_section) | |
10039 | return; | |
10040 | ||
74869ac7 | 10041 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 10042 | { |
74869ac7 BW |
10043 | /* Keep the literals for .init and .fini in separate sections. */ |
10044 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
10045 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
10046 | continue; | |
10047 | ||
e0001a05 NC |
10048 | frchain_from = seg_info (segment->seg)->frchainP; |
10049 | search_frag = frchain_from->frch_root; | |
10050 | literal_pool = NULL; | |
10051 | frchain_to = NULL; | |
10052 | frag_splice = &(frchain_from->frch_root); | |
10053 | ||
10054 | while (!search_frag->tc_frag_data.literal_frag) | |
10055 | { | |
10056 | assert (search_frag->fr_fix == 0 | |
10057 | || search_frag->fr_type == rs_align); | |
10058 | search_frag = search_frag->fr_next; | |
10059 | } | |
10060 | ||
10061 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
10062 | == RELAX_LITERAL_POOL_BEGIN); | |
10063 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
10064 | ||
10065 | /* Make sure that all the frags in this series are closed, and | |
10066 | that there is at least one left over of zero-size. This | |
10067 | prevents us from making a segment with an frchain without any | |
10068 | frags in it. */ | |
10069 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10070 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10071 | last_frag = frag_now; |
10072 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10073 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10074 | |
43cd72b9 | 10075 | while (search_frag != frag_now) |
e0001a05 NC |
10076 | { |
10077 | next_frag = search_frag->fr_next; | |
10078 | ||
43cd72b9 | 10079 | /* First, move the frag out of the literal section and |
e0001a05 NC |
10080 | to the appropriate place. */ |
10081 | if (search_frag->tc_frag_data.literal_frag) | |
10082 | { | |
10083 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
10084 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
10085 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
10086 | assert (frchain_to); | |
e0001a05 | 10087 | } |
c48aaca0 | 10088 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 10089 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 10090 | |
e0001a05 NC |
10091 | *frag_splice = next_frag; |
10092 | search_frag->fr_next = insert_after->fr_next; | |
10093 | insert_after->fr_next = search_frag; | |
10094 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 10095 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
10096 | |
10097 | /* Now move any fixups associated with this frag to the | |
10098 | right section. */ | |
10099 | fix = frchain_from->fix_root; | |
10100 | fix_splice = &(frchain_from->fix_root); | |
10101 | while (fix) | |
10102 | { | |
10103 | next_fix = fix->fx_next; | |
10104 | if (fix->fx_frag == search_frag) | |
10105 | { | |
10106 | *fix_splice = next_fix; | |
10107 | fix->fx_next = frchain_to->fix_root; | |
10108 | frchain_to->fix_root = fix; | |
10109 | if (frchain_to->fix_tail == NULL) | |
10110 | frchain_to->fix_tail = fix; | |
10111 | } | |
10112 | else | |
10113 | fix_splice = &(fix->fx_next); | |
10114 | fix = next_fix; | |
10115 | } | |
10116 | search_frag = next_frag; | |
10117 | } | |
10118 | ||
10119 | if (frchain_from->fix_root != NULL) | |
10120 | { | |
10121 | frchain_from = seg_info (segment->seg)->frchainP; | |
10122 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
10123 | ||
10124 | assert (frchain_from->fix_root == NULL); | |
10125 | } | |
10126 | frchain_from->fix_tail = NULL; | |
10127 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
10128 | } |
10129 | ||
82e7541d BW |
10130 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
10131 | for (lit = literal_syms; lit; lit = lit->next) | |
10132 | { | |
10133 | symbolS *lit_sym = lit->sym; | |
10134 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
10135 | if (dest_seg) |
10136 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 10137 | } |
e0001a05 NC |
10138 | } |
10139 | ||
10140 | ||
a7877748 BW |
10141 | /* Walk over all the frags for segments in a list and mark them as |
10142 | containing literals. As clunky as this is, we can't rely on frag_var | |
10143 | and frag_variant to get called in all situations. */ | |
10144 | ||
10145 | static void | |
7fa3d080 | 10146 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
10147 | { |
10148 | frchainS *frchain_from; | |
10149 | fragS *search_frag; | |
10150 | ||
10151 | while (segment) | |
10152 | { | |
10153 | frchain_from = seg_info (segment->seg)->frchainP; | |
10154 | search_frag = frchain_from->frch_root; | |
c138bc38 | 10155 | while (search_frag) |
a7877748 BW |
10156 | { |
10157 | search_frag->tc_frag_data.is_literal = TRUE; | |
10158 | search_frag = search_frag->fr_next; | |
10159 | } | |
10160 | segment = segment->next; | |
10161 | } | |
10162 | } | |
10163 | ||
10164 | ||
e0001a05 | 10165 | static void |
7fa3d080 | 10166 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
10167 | { |
10168 | /* Move all of the sections in the section list to come | |
10169 | after "after" in the gnu segment list. */ | |
10170 | ||
10171 | head = head->next; | |
10172 | while (head) | |
10173 | { | |
10174 | segT literal_section = head->seg; | |
10175 | ||
10176 | /* Move the literal section after "after". */ | |
10177 | assert (literal_section); | |
10178 | if (literal_section != after) | |
10179 | { | |
69852798 AM |
10180 | bfd_section_list_remove (stdoutput, literal_section); |
10181 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
10182 | } |
10183 | ||
10184 | head = head->next; | |
10185 | } | |
10186 | } | |
10187 | ||
10188 | ||
10189 | /* Push all the literal segments to the end of the gnu list. */ | |
10190 | ||
7fa3d080 BW |
10191 | static void |
10192 | xtensa_reorder_segments (void) | |
e0001a05 NC |
10193 | { |
10194 | segT sec; | |
b08b5071 | 10195 | segT last_sec = 0; |
e0001a05 NC |
10196 | int old_count = 0; |
10197 | int new_count = 0; | |
10198 | ||
10199 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10200 | { |
10201 | last_sec = sec; | |
10202 | old_count++; | |
10203 | } | |
e0001a05 NC |
10204 | |
10205 | /* Now that we have the last section, push all the literal | |
10206 | sections to the end. */ | |
e0001a05 | 10207 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10208 | |
10209 | /* Now perform the final error check. */ | |
10210 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10211 | new_count++; | |
10212 | assert (new_count == old_count); | |
10213 | } | |
10214 | ||
10215 | ||
e0001a05 NC |
10216 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10217 | correct location. Return a emit_state which can be passed to | |
10218 | xtensa_restore_emit_state to return to current fragment. */ | |
10219 | ||
7fa3d080 BW |
10220 | static void |
10221 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10222 | { |
10223 | if (directive_state[directive_absolute_literals]) | |
10224 | { | |
74869ac7 BW |
10225 | segT lit4_seg = cache_literal_section (TRUE); |
10226 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10227 | } |
10228 | else | |
10229 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10230 | ||
10231 | /* Do a 4-byte align here. */ | |
10232 | frag_align (2, 0, 0); | |
10233 | record_alignment (now_seg, 2); | |
10234 | } | |
10235 | ||
10236 | ||
7fa3d080 BW |
10237 | static void |
10238 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10239 | { |
e0001a05 NC |
10240 | static bfd_boolean recursive = FALSE; |
10241 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10242 | segT lit_seg; |
c138bc38 | 10243 | bfd_boolean is_init = |
e0001a05 | 10244 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10245 | bfd_boolean is_fini = |
e0001a05 | 10246 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10247 | |
43cd72b9 BW |
10248 | if (pool_location == NULL |
10249 | && !use_literal_section | |
e0001a05 NC |
10250 | && !recursive |
10251 | && !is_init && ! is_fini) | |
10252 | { | |
43cd72b9 | 10253 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10254 | |
10255 | /* When we mark a literal pool location, we want to put a frag in | |
10256 | the literal pool that points to it. But to do that, we want to | |
10257 | switch_to_literal_fragment. But literal sections don't have | |
10258 | literal pools, so their location is always null, so we would | |
10259 | recurse forever. This is kind of hacky, but it works. */ | |
10260 | ||
e0001a05 | 10261 | recursive = TRUE; |
61846f28 | 10262 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10263 | recursive = FALSE; |
10264 | } | |
10265 | ||
74869ac7 BW |
10266 | lit_seg = cache_literal_section (FALSE); |
10267 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10268 | |
43cd72b9 BW |
10269 | if (!use_literal_section |
10270 | && !is_init && !is_fini | |
10271 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10272 | { |
10273 | /* Close whatever frag is there. */ | |
10274 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10275 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10276 | frag_now->tc_frag_data.literal_frag = pool_location; |
10277 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10278 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10279 | } |
e0001a05 NC |
10280 | } |
10281 | ||
10282 | ||
10283 | /* Call this function before emitting data into the literal section. | |
10284 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10285 | This is similar to a .section new_now_seg subseg. */ | |
10286 | ||
7fa3d080 BW |
10287 | static void |
10288 | xtensa_switch_section_emit_state (emit_state *state, | |
10289 | segT new_now_seg, | |
10290 | subsegT new_now_subseg) | |
e0001a05 NC |
10291 | { |
10292 | state->name = now_seg->name; | |
10293 | state->now_seg = now_seg; | |
10294 | state->now_subseg = now_subseg; | |
10295 | state->generating_literals = generating_literals; | |
10296 | generating_literals++; | |
2b0210eb | 10297 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10298 | } |
10299 | ||
10300 | ||
10301 | /* Use to restore the emitting into the normal place. */ | |
10302 | ||
7fa3d080 BW |
10303 | static void |
10304 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10305 | { |
10306 | generating_literals = state->generating_literals; | |
2b0210eb | 10307 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10308 | } |
10309 | ||
10310 | ||
74869ac7 | 10311 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10312 | |
74869ac7 BW |
10313 | static bfd_boolean |
10314 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10315 | { |
74869ac7 BW |
10316 | const char *gname = inf; |
10317 | const char *group_name = elf_group_name (sec); | |
10318 | ||
10319 | return (group_name == gname | |
10320 | || (group_name != NULL | |
10321 | && gname != NULL | |
10322 | && strcmp (group_name, gname) == 0)); | |
10323 | } | |
e0001a05 | 10324 | |
e0001a05 | 10325 | |
74869ac7 BW |
10326 | /* Get the literal section to be used for the current text section. |
10327 | The result may be cached in the default_lit_sections structure. */ | |
10328 | ||
10329 | static segT | |
10330 | cache_literal_section (bfd_boolean use_abs_literals) | |
10331 | { | |
10332 | const char *text_name, *group_name = 0; | |
10333 | char *base_name, *name, *suffix; | |
10334 | segT *pcached; | |
10335 | segT seg, current_section; | |
10336 | int current_subsec; | |
10337 | bfd_boolean linkonce = FALSE; | |
10338 | ||
10339 | /* Save the current section/subsection. */ | |
10340 | current_section = now_seg; | |
10341 | current_subsec = now_subseg; | |
10342 | ||
10343 | /* Clear the cached values if they are no longer valid. */ | |
10344 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10345 | { |
74869ac7 BW |
10346 | default_lit_sections.current_text_seg = now_seg; |
10347 | default_lit_sections.lit_seg = NULL; | |
10348 | default_lit_sections.lit4_seg = NULL; | |
10349 | } | |
10350 | ||
10351 | /* Check if the literal section is already cached. */ | |
10352 | if (use_abs_literals) | |
10353 | pcached = &default_lit_sections.lit4_seg; | |
10354 | else | |
10355 | pcached = &default_lit_sections.lit_seg; | |
10356 | ||
10357 | if (*pcached) | |
10358 | return *pcached; | |
10359 | ||
10360 | text_name = default_lit_sections.lit_prefix; | |
10361 | if (! text_name || ! *text_name) | |
10362 | { | |
10363 | text_name = segment_name (current_section); | |
10364 | group_name = elf_group_name (current_section); | |
10365 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10366 | } | |
10367 | ||
10368 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10369 | if (group_name) | |
10370 | { | |
10371 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10372 | sprintf (name, "%s.%s", base_name, group_name); | |
10373 | } | |
10374 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10375 | { | |
10376 | suffix = strchr (text_name + linkonce_len, '.'); | |
10377 | ||
10378 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10379 | + (suffix ? strlen (suffix) : 0)); | |
10380 | strcpy (name, ".gnu.linkonce"); | |
10381 | strcat (name, base_name); | |
10382 | if (suffix) | |
10383 | strcat (name, suffix); | |
10384 | linkonce = TRUE; | |
10385 | } | |
10386 | else | |
10387 | { | |
10388 | /* If the section name ends with ".text", then replace that suffix | |
10389 | instead of appending an additional suffix. */ | |
10390 | size_t len = strlen (text_name); | |
10391 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10392 | len -= 5; | |
10393 | ||
10394 | name = xmalloc (len + strlen (base_name) + 1); | |
10395 | strcpy (name, text_name); | |
10396 | strcpy (name + len, base_name); | |
b08b5071 | 10397 | } |
e0001a05 | 10398 | |
74869ac7 BW |
10399 | /* Canonicalize section names to allow renaming literal sections. |
10400 | The group name, if any, came from the current text section and | |
10401 | has already been canonicalized. */ | |
10402 | name = tc_canonicalize_symbol_name (name); | |
10403 | ||
10404 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10405 | (void *) group_name); | |
10406 | if (! seg) | |
e0001a05 | 10407 | { |
74869ac7 BW |
10408 | flagword flags; |
10409 | ||
10410 | seg = subseg_force_new (name, 0); | |
10411 | ||
10412 | if (! use_abs_literals) | |
b08b5071 | 10413 | { |
74869ac7 | 10414 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10415 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10416 | n->seg = seg; | |
74869ac7 BW |
10417 | n->next = literal_head->next; |
10418 | literal_head->next = n; | |
b08b5071 | 10419 | } |
74869ac7 BW |
10420 | |
10421 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10422 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10423 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10424 | ||
10425 | elf_group_name (seg) = group_name; | |
10426 | ||
10427 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10428 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10429 | } |
10430 | ||
74869ac7 | 10431 | *pcached = seg; |
b08b5071 | 10432 | subseg_set (current_section, current_subsec); |
74869ac7 | 10433 | return seg; |
e0001a05 NC |
10434 | } |
10435 | ||
43cd72b9 BW |
10436 | \f |
10437 | /* Property Tables Stuff. */ | |
10438 | ||
7fa3d080 BW |
10439 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10440 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10441 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10442 | ||
10443 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10444 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10445 | ||
b08b5071 | 10446 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10447 | static void xtensa_create_property_segments |
10448 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10449 | static void xtensa_create_xproperty_segments | |
10450 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 10451 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
10452 | static bfd_boolean section_has_property (segT, frag_predicate); |
10453 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10454 | static void add_xt_block_frags | |
542f8b94 | 10455 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
10456 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
10457 | static void xtensa_frag_flags_init (frag_flags *); | |
10458 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10459 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
542f8b94 | 10460 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
10461 | |
10462 | /* Set up property tables after relaxation. */ | |
10463 | ||
10464 | void | |
10465 | xtensa_post_relax_hook (void) | |
10466 | { | |
10467 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10468 | |
10469 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10470 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10471 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10472 | |
b29757dc BW |
10473 | xtensa_create_property_segments (get_frag_is_literal, |
10474 | NULL, | |
10475 | XTENSA_LIT_SEC_NAME, | |
10476 | xt_literal_sec); | |
7fa3d080 BW |
10477 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10478 | XTENSA_PROP_SEC_NAME, | |
10479 | xt_prop_sec); | |
10480 | ||
10481 | if (warn_unaligned_branch_targets) | |
10482 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10483 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10484 | } | |
10485 | ||
10486 | ||
43cd72b9 BW |
10487 | /* This function is only meaningful after xtensa_move_literals. */ |
10488 | ||
10489 | static bfd_boolean | |
7fa3d080 | 10490 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10491 | { |
10492 | assert (fragP != NULL); | |
10493 | return fragP->tc_frag_data.is_literal; | |
10494 | } | |
10495 | ||
10496 | ||
43cd72b9 | 10497 | static void |
7fa3d080 BW |
10498 | xtensa_create_property_segments (frag_predicate property_function, |
10499 | frag_predicate end_property_function, | |
10500 | const char *section_name_base, | |
10501 | xt_section_type sec_type) | |
43cd72b9 BW |
10502 | { |
10503 | segT *seclist; | |
10504 | ||
10505 | /* Walk over all of the current segments. | |
10506 | Walk over each fragment | |
10507 | For each non-empty fragment, | |
10508 | Build a property record (append where possible). */ | |
10509 | ||
10510 | for (seclist = &stdoutput->sections; | |
10511 | seclist && *seclist; | |
10512 | seclist = &(*seclist)->next) | |
10513 | { | |
10514 | segT sec = *seclist; | |
43cd72b9 | 10515 | |
532f93bd | 10516 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10517 | continue; |
10518 | ||
10519 | if (section_has_property (sec, property_function)) | |
10520 | { | |
542f8b94 BW |
10521 | segment_info_type *xt_seg_info; |
10522 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10523 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10524 | |
10525 | prop_sec->output_section = prop_sec; | |
10526 | subseg_set (prop_sec, 0); | |
10527 | xt_seg_info = seg_info (prop_sec); | |
10528 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10529 | ||
43cd72b9 | 10530 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10531 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
10532 | end_property_function); |
10533 | } | |
10534 | } | |
10535 | ||
10536 | /* Now we fill them out.... */ | |
10537 | ||
10538 | for (seclist = &stdoutput->sections; | |
10539 | seclist && *seclist; | |
10540 | seclist = &(*seclist)->next) | |
10541 | { | |
10542 | segment_info_type *seginfo; | |
10543 | xtensa_block_info *block; | |
10544 | segT sec = *seclist; | |
10545 | ||
10546 | seginfo = seg_info (sec); | |
10547 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10548 | ||
10549 | if (block) | |
10550 | { | |
10551 | xtensa_block_info *cur_block; | |
43cd72b9 | 10552 | int num_recs = 0; |
d77b99c9 | 10553 | bfd_size_type rec_size; |
43cd72b9 BW |
10554 | |
10555 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10556 | num_recs++; | |
10557 | ||
10558 | rec_size = num_recs * 8; | |
10559 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10560 | ||
43cd72b9 BW |
10561 | if (num_recs) |
10562 | { | |
43cd72b9 | 10563 | char *frag_data; |
542f8b94 | 10564 | int i; |
43cd72b9 | 10565 | |
542f8b94 BW |
10566 | subseg_set (sec, 0); |
10567 | frag_data = frag_more (rec_size); | |
43cd72b9 | 10568 | cur_block = block; |
43cd72b9 BW |
10569 | for (i = 0; i < num_recs; i++) |
10570 | { | |
542f8b94 | 10571 | fixS *fix; |
e0001a05 | 10572 | |
43cd72b9 | 10573 | /* Write the fixup. */ |
542f8b94 BW |
10574 | assert (cur_block); |
10575 | fix = fix_new (frag_now, i * 8, 4, | |
10576 | section_symbol (cur_block->sec), | |
10577 | cur_block->offset, | |
10578 | FALSE, BFD_RELOC_32); | |
10579 | fix->fx_file = "<internal>"; | |
43cd72b9 | 10580 | fix->fx_line = 0; |
e0001a05 | 10581 | |
43cd72b9 | 10582 | /* Write the length. */ |
542f8b94 | 10583 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
10584 | cur_block->size, 4); |
10585 | cur_block = cur_block->next; | |
10586 | } | |
542f8b94 BW |
10587 | frag_wane (frag_now); |
10588 | frag_new (0); | |
10589 | frag_wane (frag_now); | |
43cd72b9 BW |
10590 | } |
10591 | } | |
10592 | } | |
e0001a05 NC |
10593 | } |
10594 | ||
10595 | ||
7fa3d080 BW |
10596 | static void |
10597 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10598 | const char *section_name_base, | |
10599 | xt_section_type sec_type) | |
e0001a05 NC |
10600 | { |
10601 | segT *seclist; | |
10602 | ||
10603 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10604 | Walk over each fragment. |
10605 | For each fragment that has instructions, | |
10606 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10607 | |
10608 | for (seclist = &stdoutput->sections; | |
10609 | seclist && *seclist; | |
10610 | seclist = &(*seclist)->next) | |
10611 | { | |
10612 | segT sec = *seclist; | |
43cd72b9 | 10613 | |
532f93bd | 10614 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
10615 | continue; |
10616 | ||
10617 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10618 | { |
542f8b94 BW |
10619 | segment_info_type *xt_seg_info; |
10620 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 10621 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
10622 | |
10623 | prop_sec->output_section = prop_sec; | |
10624 | subseg_set (prop_sec, 0); | |
10625 | xt_seg_info = seg_info (prop_sec); | |
10626 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10627 | ||
e0001a05 | 10628 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 10629 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
10630 | } |
10631 | } | |
10632 | ||
10633 | /* Now we fill them out.... */ | |
10634 | ||
10635 | for (seclist = &stdoutput->sections; | |
10636 | seclist && *seclist; | |
10637 | seclist = &(*seclist)->next) | |
10638 | { | |
10639 | segment_info_type *seginfo; | |
10640 | xtensa_block_info *block; | |
10641 | segT sec = *seclist; | |
43cd72b9 | 10642 | |
e0001a05 NC |
10643 | seginfo = seg_info (sec); |
10644 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10645 | ||
10646 | if (block) | |
10647 | { | |
10648 | xtensa_block_info *cur_block; | |
43cd72b9 | 10649 | int num_recs = 0; |
d77b99c9 | 10650 | bfd_size_type rec_size; |
e0001a05 NC |
10651 | |
10652 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10653 | num_recs++; | |
10654 | ||
43cd72b9 | 10655 | rec_size = num_recs * (8 + 4); |
e0001a05 | 10656 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
10657 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10658 | ||
e0001a05 NC |
10659 | if (num_recs) |
10660 | { | |
e0001a05 | 10661 | char *frag_data; |
542f8b94 | 10662 | int i; |
e0001a05 | 10663 | |
542f8b94 BW |
10664 | subseg_set (sec, 0); |
10665 | frag_data = frag_more (rec_size); | |
e0001a05 | 10666 | cur_block = block; |
e0001a05 NC |
10667 | for (i = 0; i < num_recs; i++) |
10668 | { | |
542f8b94 | 10669 | fixS *fix; |
e0001a05 NC |
10670 | |
10671 | /* Write the fixup. */ | |
542f8b94 BW |
10672 | assert (cur_block); |
10673 | fix = fix_new (frag_now, i * 12, 4, | |
10674 | section_symbol (cur_block->sec), | |
10675 | cur_block->offset, | |
10676 | FALSE, BFD_RELOC_32); | |
10677 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
10678 | fix->fx_line = 0; |
10679 | ||
10680 | /* Write the length. */ | |
542f8b94 | 10681 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 10682 | cur_block->size, 4); |
542f8b94 | 10683 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 BW |
10684 | frag_flags_to_number (&cur_block->flags), |
10685 | 4); | |
e0001a05 NC |
10686 | cur_block = cur_block->next; |
10687 | } | |
542f8b94 BW |
10688 | frag_wane (frag_now); |
10689 | frag_new (0); | |
10690 | frag_wane (frag_now); | |
e0001a05 NC |
10691 | } |
10692 | } | |
10693 | } | |
10694 | } | |
10695 | ||
10696 | ||
532f93bd BW |
10697 | static bfd_boolean |
10698 | exclude_section_from_property_tables (segT sec) | |
10699 | { | |
10700 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
10701 | ||
10702 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
10703 | if ((flags & SEC_DEBUGGING) | |
10704 | || !(flags & SEC_ALLOC) | |
10705 | || (flags & SEC_MERGE)) | |
10706 | return TRUE; | |
10707 | ||
10708 | /* Linker cie and fde optimizations mess up property entries for | |
10709 | eh_frame sections, but there is nothing inside them relevant to | |
10710 | property tables anyway. */ | |
10711 | if (strcmp (sec->name, ".eh_frame") == 0) | |
10712 | return TRUE; | |
10713 | ||
10714 | return FALSE; | |
10715 | } | |
10716 | ||
10717 | ||
7fa3d080 BW |
10718 | static bfd_boolean |
10719 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10720 | { |
10721 | segment_info_type *seginfo = seg_info (sec); | |
10722 | fragS *fragP; | |
10723 | ||
10724 | if (seginfo && seginfo->frchainP) | |
10725 | { | |
10726 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10727 | { | |
10728 | if (property_function (fragP) | |
10729 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10730 | return TRUE; | |
10731 | } | |
10732 | } | |
10733 | return FALSE; | |
10734 | } | |
10735 | ||
10736 | ||
7fa3d080 BW |
10737 | static bfd_boolean |
10738 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10739 | { |
10740 | segment_info_type *seginfo = seg_info (sec); | |
10741 | fragS *fragP; | |
10742 | ||
10743 | if (seginfo && seginfo->frchainP) | |
10744 | { | |
10745 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10746 | { | |
10747 | frag_flags prop_flags; | |
10748 | property_function (fragP, &prop_flags); | |
10749 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10750 | return TRUE; | |
10751 | } | |
10752 | } | |
10753 | return FALSE; | |
10754 | } | |
10755 | ||
10756 | ||
e0001a05 NC |
10757 | /* Two types of block sections exist right now: literal and insns. */ |
10758 | ||
7fa3d080 BW |
10759 | static void |
10760 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
10761 | xtensa_block_info **xt_block, |
10762 | frag_predicate property_function, | |
10763 | frag_predicate end_property_function) | |
e0001a05 | 10764 | { |
e0001a05 NC |
10765 | bfd_vma seg_offset; |
10766 | fragS *fragP; | |
10767 | ||
e0001a05 NC |
10768 | /* Build it if needed. */ |
10769 | while (*xt_block != NULL) | |
10770 | xt_block = &(*xt_block)->next; | |
10771 | /* We are either at NULL at the beginning or at the end. */ | |
10772 | ||
10773 | /* Walk through the frags. */ | |
10774 | seg_offset = 0; | |
10775 | ||
542f8b94 | 10776 | if (seg_info (sec)->frchainP) |
e0001a05 | 10777 | { |
542f8b94 | 10778 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
10779 | fragP; |
10780 | fragP = fragP->fr_next) | |
10781 | { | |
10782 | if (property_function (fragP) | |
10783 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10784 | { | |
10785 | if (*xt_block != NULL) | |
10786 | { | |
10787 | if ((*xt_block)->offset + (*xt_block)->size | |
10788 | == fragP->fr_address) | |
10789 | (*xt_block)->size += fragP->fr_fix; | |
10790 | else | |
10791 | xt_block = &((*xt_block)->next); | |
10792 | } | |
10793 | if (*xt_block == NULL) | |
10794 | { | |
43cd72b9 BW |
10795 | xtensa_block_info *new_block = (xtensa_block_info *) |
10796 | xmalloc (sizeof (xtensa_block_info)); | |
10797 | new_block->sec = sec; | |
10798 | new_block->offset = fragP->fr_address; | |
10799 | new_block->size = fragP->fr_fix; | |
10800 | new_block->next = NULL; | |
10801 | xtensa_frag_flags_init (&new_block->flags); | |
10802 | *xt_block = new_block; | |
10803 | } | |
10804 | if (end_property_function | |
10805 | && end_property_function (fragP)) | |
10806 | { | |
10807 | xt_block = &((*xt_block)->next); | |
10808 | } | |
10809 | } | |
10810 | } | |
10811 | } | |
10812 | } | |
10813 | ||
10814 | ||
10815 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10816 | ||
7fa3d080 BW |
10817 | static bfd_boolean |
10818 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10819 | { |
10820 | if (prop_flags->is_literal | |
10821 | || prop_flags->is_insn | |
10822 | || prop_flags->is_data | |
10823 | || prop_flags->is_unreachable) | |
10824 | return FALSE; | |
10825 | return TRUE; | |
10826 | } | |
10827 | ||
10828 | ||
7fa3d080 BW |
10829 | static void |
10830 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10831 | { |
10832 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10833 | } | |
10834 | ||
10835 | ||
7fa3d080 BW |
10836 | static void |
10837 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10838 | { |
10839 | xtensa_frag_flags_init (prop_flags); | |
10840 | if (fragP->tc_frag_data.is_literal) | |
10841 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10842 | if (fragP->tc_frag_data.is_specific_opcode |
10843 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
10844 | { |
10845 | prop_flags->is_no_transform = TRUE; | |
10846 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10847 | prop_flags->is_data = TRUE; | |
10848 | } | |
43cd72b9 | 10849 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10850 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10851 | else if (fragP->tc_frag_data.is_insn) |
10852 | { | |
10853 | prop_flags->is_insn = TRUE; | |
10854 | if (fragP->tc_frag_data.is_loop_target) | |
10855 | prop_flags->insn.is_loop_target = TRUE; | |
10856 | if (fragP->tc_frag_data.is_branch_target) | |
10857 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10858 | if (fragP->tc_frag_data.is_no_density) |
10859 | prop_flags->insn.is_no_density = TRUE; | |
10860 | if (fragP->tc_frag_data.use_absolute_literals) | |
10861 | prop_flags->insn.is_abslit = TRUE; | |
10862 | } | |
10863 | if (fragP->tc_frag_data.is_align) | |
10864 | { | |
10865 | prop_flags->is_align = TRUE; | |
10866 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10867 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10868 | prop_flags->is_data = TRUE; | |
10869 | } | |
10870 | } | |
10871 | ||
10872 | ||
7fa3d080 BW |
10873 | static bfd_vma |
10874 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10875 | { |
10876 | bfd_vma num = 0; | |
10877 | if (prop_flags->is_literal) | |
10878 | num |= XTENSA_PROP_LITERAL; | |
10879 | if (prop_flags->is_insn) | |
10880 | num |= XTENSA_PROP_INSN; | |
10881 | if (prop_flags->is_data) | |
10882 | num |= XTENSA_PROP_DATA; | |
10883 | if (prop_flags->is_unreachable) | |
10884 | num |= XTENSA_PROP_UNREACHABLE; | |
10885 | if (prop_flags->insn.is_loop_target) | |
10886 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10887 | if (prop_flags->insn.is_branch_target) | |
10888 | { | |
10889 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10890 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10891 | } | |
10892 | ||
10893 | if (prop_flags->insn.is_no_density) | |
10894 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10895 | if (prop_flags->is_no_transform) |
10896 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10897 | if (prop_flags->insn.is_no_reorder) |
10898 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10899 | if (prop_flags->insn.is_abslit) | |
10900 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10901 | ||
10902 | if (prop_flags->is_align) | |
10903 | { | |
10904 | num |= XTENSA_PROP_ALIGN; | |
10905 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10906 | } | |
10907 | ||
10908 | return num; | |
10909 | } | |
10910 | ||
10911 | ||
10912 | static bfd_boolean | |
7fa3d080 BW |
10913 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10914 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10915 | { |
10916 | /* Cannot combine with an end marker. */ | |
10917 | ||
10918 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10919 | return FALSE; | |
10920 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10921 | return FALSE; | |
10922 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10923 | return FALSE; | |
10924 | ||
10925 | if (prop_flags_1->is_insn) | |
10926 | { | |
10927 | /* Properties of the beginning of the frag. */ | |
10928 | if (prop_flags_2->insn.is_loop_target) | |
10929 | return FALSE; | |
10930 | if (prop_flags_2->insn.is_branch_target) | |
10931 | return FALSE; | |
10932 | if (prop_flags_1->insn.is_no_density != | |
10933 | prop_flags_2->insn.is_no_density) | |
10934 | return FALSE; | |
99ded152 BW |
10935 | if (prop_flags_1->is_no_transform != |
10936 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10937 | return FALSE; |
10938 | if (prop_flags_1->insn.is_no_reorder != | |
10939 | prop_flags_2->insn.is_no_reorder) | |
10940 | return FALSE; | |
10941 | if (prop_flags_1->insn.is_abslit != | |
10942 | prop_flags_2->insn.is_abslit) | |
10943 | return FALSE; | |
10944 | } | |
10945 | ||
10946 | if (prop_flags_1->is_align) | |
10947 | return FALSE; | |
10948 | ||
10949 | return TRUE; | |
10950 | } | |
10951 | ||
10952 | ||
7fa3d080 BW |
10953 | static bfd_vma |
10954 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10955 | { |
10956 | bfd_vma end_addr; | |
d77b99c9 | 10957 | unsigned align_bits; |
43cd72b9 BW |
10958 | |
10959 | if (!xt_block->flags.is_align) | |
10960 | return xt_block->size; | |
10961 | ||
10962 | end_addr = xt_block->offset + xt_block->size; | |
10963 | align_bits = xt_block->flags.alignment; | |
10964 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10965 | return end_addr - xt_block->offset; | |
10966 | } | |
10967 | ||
10968 | ||
10969 | static bfd_boolean | |
7fa3d080 BW |
10970 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10971 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10972 | { |
10973 | if (xt_block->sec != xt_block_2->sec) | |
10974 | return FALSE; | |
10975 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10976 | != xt_block_2->offset) | |
10977 | return FALSE; | |
10978 | ||
10979 | if (xt_block_2->size == 0 | |
10980 | && (!xt_block_2->flags.is_unreachable | |
10981 | || xt_block->flags.is_unreachable)) | |
10982 | { | |
10983 | if (xt_block_2->flags.is_align | |
10984 | && xt_block->flags.is_align) | |
10985 | { | |
10986 | /* Nothing needed. */ | |
10987 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10988 | return TRUE; | |
10989 | } | |
10990 | else | |
10991 | { | |
10992 | if (xt_block_2->flags.is_align) | |
10993 | { | |
10994 | /* Push alignment to previous entry. */ | |
10995 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10996 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10997 | } | |
10998 | return TRUE; | |
10999 | } | |
11000 | } | |
11001 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
11002 | &xt_block_2->flags)) | |
11003 | return FALSE; | |
11004 | ||
11005 | xt_block->size += xt_block_2->size; | |
11006 | ||
11007 | if (xt_block_2->flags.is_align) | |
11008 | { | |
11009 | xt_block->flags.is_align = TRUE; | |
11010 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
11011 | } | |
11012 | ||
11013 | return TRUE; | |
11014 | } | |
11015 | ||
11016 | ||
7fa3d080 BW |
11017 | static void |
11018 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
11019 | xtensa_block_info **xt_block, |
11020 | frag_flags_fn property_function) | |
43cd72b9 | 11021 | { |
43cd72b9 BW |
11022 | bfd_vma seg_offset; |
11023 | fragS *fragP; | |
11024 | ||
43cd72b9 BW |
11025 | /* Build it if needed. */ |
11026 | while (*xt_block != NULL) | |
11027 | { | |
11028 | xt_block = &(*xt_block)->next; | |
11029 | } | |
11030 | /* We are either at NULL at the beginning or at the end. */ | |
11031 | ||
11032 | /* Walk through the frags. */ | |
11033 | seg_offset = 0; | |
11034 | ||
542f8b94 | 11035 | if (seg_info (sec)->frchainP) |
43cd72b9 | 11036 | { |
542f8b94 | 11037 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
11038 | fragP = fragP->fr_next) |
11039 | { | |
11040 | xtensa_block_info tmp_block; | |
11041 | tmp_block.sec = sec; | |
11042 | tmp_block.offset = fragP->fr_address; | |
11043 | tmp_block.size = fragP->fr_fix; | |
11044 | tmp_block.next = NULL; | |
11045 | property_function (fragP, &tmp_block.flags); | |
11046 | ||
11047 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
11048 | /* && fragP->fr_fix != 0) */ | |
11049 | { | |
11050 | if ((*xt_block) == NULL | |
11051 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
11052 | { | |
11053 | xtensa_block_info *new_block; | |
11054 | if ((*xt_block) != NULL) | |
11055 | xt_block = &(*xt_block)->next; | |
11056 | new_block = (xtensa_block_info *) | |
11057 | xmalloc (sizeof (xtensa_block_info)); | |
11058 | *new_block = tmp_block; | |
11059 | *xt_block = new_block; | |
11060 | } | |
11061 | } | |
11062 | } | |
11063 | } | |
11064 | } | |
11065 | ||
11066 | \f | |
11067 | /* op_placement_info_table */ | |
11068 | ||
11069 | /* op_placement_info makes it easier to determine which | |
11070 | ops can go in which slots. */ | |
11071 | ||
11072 | static void | |
7fa3d080 | 11073 | init_op_placement_info_table (void) |
43cd72b9 BW |
11074 | { |
11075 | xtensa_isa isa = xtensa_default_isa; | |
11076 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
11077 | xtensa_opcode opcode; | |
11078 | xtensa_format fmt; | |
11079 | int slot; | |
11080 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
11081 | ||
11082 | op_placement_table = (op_placement_info_table) | |
11083 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
11084 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
11085 | ||
11086 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
11087 | { | |
11088 | op_placement_info *opi = &op_placement_table[opcode]; | |
11089 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 11090 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 11091 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
11092 | opi->narrowest = XTENSA_UNDEFINED; |
11093 | opi->narrowest_size = 0x7F; | |
b2d179be | 11094 | opi->narrowest_slot = 0; |
43cd72b9 BW |
11095 | opi->formats = 0; |
11096 | opi->num_formats = 0; | |
11097 | opi->issuef = 0; | |
11098 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
11099 | { | |
11100 | opi->slots[fmt] = 0; | |
11101 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
11102 | { | |
11103 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
11104 | { | |
11105 | int fmt_length = xtensa_format_length (isa, fmt); | |
11106 | opi->issuef++; | |
11107 | set_bit (fmt, opi->formats); | |
11108 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
11109 | if (fmt_length < opi->narrowest_size |
11110 | || (fmt_length == opi->narrowest_size | |
11111 | && (xtensa_format_num_slots (isa, fmt) | |
11112 | < xtensa_format_num_slots (isa, | |
11113 | opi->narrowest)))) | |
43cd72b9 BW |
11114 | { |
11115 | opi->narrowest = fmt; | |
11116 | opi->narrowest_size = fmt_length; | |
b2d179be | 11117 | opi->narrowest_slot = slot; |
43cd72b9 | 11118 | } |
e0001a05 NC |
11119 | } |
11120 | } | |
43cd72b9 BW |
11121 | if (opi->formats) |
11122 | opi->num_formats++; | |
e0001a05 NC |
11123 | } |
11124 | } | |
43cd72b9 BW |
11125 | xtensa_insnbuf_free (isa, ibuf); |
11126 | } | |
11127 | ||
11128 | ||
11129 | bfd_boolean | |
7fa3d080 | 11130 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
11131 | { |
11132 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
11133 | } | |
11134 | ||
11135 | ||
11136 | /* If the opcode is available in a single slot format, return its size. */ | |
11137 | ||
7fa3d080 BW |
11138 | static int |
11139 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 11140 | { |
b2d179be | 11141 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
11142 | } |
11143 | ||
11144 | ||
7fa3d080 BW |
11145 | static xtensa_format |
11146 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 11147 | { |
b2d179be BW |
11148 | return op_placement_table[opcode].narrowest; |
11149 | } | |
11150 | ||
11151 | ||
11152 | static int | |
11153 | xg_get_single_slot (xtensa_opcode opcode) | |
11154 | { | |
11155 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
11156 | } |
11157 | ||
11158 | \f | |
11159 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11160 | ||
11161 | void | |
7fa3d080 | 11162 | istack_init (IStack *stack) |
e0001a05 NC |
11163 | { |
11164 | memset (stack, 0, sizeof (IStack)); | |
11165 | stack->ninsn = 0; | |
11166 | } | |
11167 | ||
11168 | ||
11169 | bfd_boolean | |
7fa3d080 | 11170 | istack_empty (IStack *stack) |
e0001a05 NC |
11171 | { |
11172 | return (stack->ninsn == 0); | |
11173 | } | |
11174 | ||
11175 | ||
11176 | bfd_boolean | |
7fa3d080 | 11177 | istack_full (IStack *stack) |
e0001a05 NC |
11178 | { |
11179 | return (stack->ninsn == MAX_ISTACK); | |
11180 | } | |
11181 | ||
11182 | ||
11183 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11184 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11185 | |
11186 | TInsn * | |
7fa3d080 | 11187 | istack_top (IStack *stack) |
e0001a05 NC |
11188 | { |
11189 | int rec = stack->ninsn - 1; | |
11190 | assert (!istack_empty (stack)); | |
11191 | return &stack->insn[rec]; | |
11192 | } | |
11193 | ||
11194 | ||
11195 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11196 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11197 | |
11198 | void | |
7fa3d080 | 11199 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11200 | { |
11201 | int rec = stack->ninsn; | |
11202 | assert (!istack_full (stack)); | |
43cd72b9 | 11203 | stack->insn[rec] = *insn; |
e0001a05 NC |
11204 | stack->ninsn++; |
11205 | } | |
11206 | ||
11207 | ||
11208 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11209 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11210 | |
11211 | TInsn * | |
7fa3d080 | 11212 | istack_push_space (IStack *stack) |
e0001a05 NC |
11213 | { |
11214 | int rec = stack->ninsn; | |
11215 | TInsn *insn; | |
11216 | assert (!istack_full (stack)); | |
11217 | insn = &stack->insn[rec]; | |
60242db2 | 11218 | tinsn_init (insn); |
e0001a05 NC |
11219 | stack->ninsn++; |
11220 | return insn; | |
11221 | } | |
11222 | ||
11223 | ||
11224 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11225 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11226 | |
11227 | void | |
7fa3d080 | 11228 | istack_pop (IStack *stack) |
e0001a05 NC |
11229 | { |
11230 | int rec = stack->ninsn - 1; | |
11231 | assert (!istack_empty (stack)); | |
11232 | stack->ninsn--; | |
60242db2 | 11233 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11234 | } |
11235 | ||
11236 | \f | |
11237 | /* TInsn functions. */ | |
11238 | ||
11239 | void | |
7fa3d080 | 11240 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11241 | { |
11242 | memset (dst, 0, sizeof (TInsn)); | |
11243 | } | |
11244 | ||
11245 | ||
43cd72b9 | 11246 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11247 | |
11248 | static bfd_boolean | |
7fa3d080 | 11249 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11250 | { |
11251 | int i; | |
11252 | int n = insn->ntok; | |
11253 | ||
11254 | assert (insn->insn_type == ITYPE_INSN); | |
11255 | ||
11256 | for (i = 0; i < n; ++i) | |
11257 | { | |
11258 | switch (insn->tok[i].X_op) | |
11259 | { | |
11260 | case O_register: | |
11261 | case O_constant: | |
11262 | break; | |
11263 | default: | |
11264 | return TRUE; | |
11265 | } | |
11266 | } | |
11267 | return FALSE; | |
11268 | } | |
11269 | ||
11270 | ||
11271 | bfd_boolean | |
7fa3d080 | 11272 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11273 | { |
43cd72b9 | 11274 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11275 | int i; |
11276 | int n = insn->ntok; | |
11277 | ||
11278 | assert (insn->insn_type == ITYPE_INSN); | |
11279 | ||
11280 | for (i = 0; i < n; ++i) | |
11281 | { | |
11282 | switch (insn->tok[i].X_op) | |
11283 | { | |
11284 | case O_register: | |
11285 | case O_constant: | |
11286 | break; | |
43cd72b9 BW |
11287 | case O_big: |
11288 | case O_illegal: | |
11289 | case O_absent: | |
11290 | /* Errors for these types are caught later. */ | |
11291 | break; | |
11292 | case O_hi16: | |
11293 | case O_lo16: | |
e0001a05 | 11294 | default: |
43cd72b9 BW |
11295 | /* Symbolic immediates are only allowed on the last immediate |
11296 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11297 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11298 | if (i != get_relaxable_immed (insn->opcode) |
11299 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11300 | && insn->opcode != xtensa_const16_opcode)) | |
11301 | { | |
431ad2d0 | 11302 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11303 | return TRUE; |
11304 | } | |
e0001a05 NC |
11305 | } |
11306 | } | |
11307 | return FALSE; | |
11308 | } | |
11309 | ||
11310 | ||
11311 | /* For assembly code with complex expressions (e.g. subtraction), | |
11312 | we have to build them in the literal pool so that | |
11313 | their results are calculated correctly after relaxation. | |
11314 | The relaxation only handles expressions that | |
11315 | boil down to SYMBOL + OFFSET. */ | |
11316 | ||
11317 | static bfd_boolean | |
7fa3d080 | 11318 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11319 | { |
11320 | int i; | |
11321 | int n = insn->ntok; | |
11322 | assert (insn->insn_type == ITYPE_INSN); | |
11323 | for (i = 0; i < n; ++i) | |
11324 | { | |
11325 | switch (insn->tok[i].X_op) | |
11326 | { | |
11327 | case O_register: | |
11328 | case O_constant: | |
11329 | case O_symbol: | |
43cd72b9 BW |
11330 | case O_lo16: |
11331 | case O_hi16: | |
e0001a05 NC |
11332 | break; |
11333 | default: | |
11334 | return TRUE; | |
11335 | } | |
11336 | } | |
11337 | return FALSE; | |
11338 | } | |
11339 | ||
11340 | ||
b2d179be BW |
11341 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11342 | Return TRUE if there is a symbol in the immediate field. This | |
11343 | function assumes that: | |
11344 | 1) The number of operands are correct. | |
11345 | 2) The insn_type is ITYPE_INSN. | |
11346 | 3) The opcode can be encoded in the specified format and slot. | |
11347 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11348 | |
11349 | static bfd_boolean | |
7fa3d080 BW |
11350 | tinsn_to_slotbuf (xtensa_format fmt, |
11351 | int slot, | |
11352 | TInsn *tinsn, | |
11353 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11354 | { |
11355 | xtensa_isa isa = xtensa_default_isa; | |
11356 | xtensa_opcode opcode = tinsn->opcode; | |
11357 | bfd_boolean has_fixup = FALSE; | |
11358 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11359 | int i; | |
11360 | ||
43cd72b9 BW |
11361 | assert (tinsn->insn_type == ITYPE_INSN); |
11362 | if (noperands != tinsn->ntok) | |
11363 | as_fatal (_("operand number mismatch")); | |
11364 | ||
11365 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11366 | { | |
11367 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11368 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11369 | return FALSE; | |
11370 | } | |
11371 | ||
11372 | for (i = 0; i < noperands; i++) | |
11373 | { | |
11374 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11375 | int rc; |
11376 | unsigned line; | |
43cd72b9 BW |
11377 | char *file_name; |
11378 | uint32 opnd_value; | |
11379 | ||
11380 | switch (expr->X_op) | |
11381 | { | |
11382 | case O_register: | |
11383 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11384 | break; | |
11385 | /* The register number has already been checked in | |
11386 | expression_maybe_register, so we don't need to check here. */ | |
11387 | opnd_value = expr->X_add_number; | |
11388 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11389 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11390 | opnd_value); | |
11391 | if (rc != 0) | |
11392 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11393 | break; | |
11394 | ||
11395 | case O_constant: | |
11396 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11397 | break; | |
11398 | as_where (&file_name, &line); | |
11399 | /* It is a constant and we called this function | |
11400 | then we have to try to fit it. */ | |
11401 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11402 | expr->X_add_number, file_name, line); |
11403 | break; | |
11404 | ||
e0001a05 NC |
11405 | default: |
11406 | has_fixup = TRUE; | |
11407 | break; | |
11408 | } | |
11409 | } | |
43cd72b9 | 11410 | |
e0001a05 NC |
11411 | return has_fixup; |
11412 | } | |
11413 | ||
11414 | ||
b2d179be BW |
11415 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11416 | into a multi-slot instruction, fill the other slots with NOPs. | |
11417 | Return TRUE if there is a symbol in the immediate field. See also the | |
11418 | assumptions listed for tinsn_to_slotbuf. */ | |
11419 | ||
11420 | static bfd_boolean | |
11421 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11422 | { | |
11423 | static xtensa_insnbuf slotbuf = 0; | |
11424 | static vliw_insn vinsn; | |
11425 | xtensa_isa isa = xtensa_default_isa; | |
11426 | bfd_boolean has_fixup = FALSE; | |
11427 | int i; | |
11428 | ||
11429 | if (!slotbuf) | |
11430 | { | |
11431 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11432 | xg_init_vinsn (&vinsn); | |
11433 | } | |
11434 | ||
11435 | xg_clear_vinsn (&vinsn); | |
11436 | ||
11437 | bundle_tinsn (tinsn, &vinsn); | |
11438 | ||
11439 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11440 | ||
11441 | for (i = 0; i < vinsn.num_slots; i++) | |
11442 | { | |
11443 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11444 | has_fixup |= | |
11445 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11446 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11447 | } | |
11448 | ||
11449 | return has_fixup; | |
11450 | } | |
11451 | ||
11452 | ||
43cd72b9 | 11453 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11454 | |
7fa3d080 BW |
11455 | static bfd_boolean |
11456 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11457 | { |
11458 | xtensa_isa isa = xtensa_default_isa; | |
11459 | xtensa_opcode opcode = insn->opcode; | |
11460 | ||
11461 | if (opcode == XTENSA_UNDEFINED) | |
11462 | { | |
11463 | as_bad (_("invalid opcode")); | |
11464 | return TRUE; | |
11465 | } | |
11466 | ||
43cd72b9 | 11467 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11468 | { |
11469 | as_bad (_("too few operands")); | |
11470 | return TRUE; | |
11471 | } | |
11472 | ||
43cd72b9 | 11473 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11474 | { |
11475 | as_bad (_("too many operands")); | |
11476 | return TRUE; | |
11477 | } | |
11478 | return FALSE; | |
11479 | } | |
11480 | ||
11481 | ||
11482 | /* Load an instruction from its encoded form. */ | |
11483 | ||
11484 | static void | |
7fa3d080 | 11485 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11486 | { |
43cd72b9 | 11487 | vliw_insn vinsn; |
e0001a05 | 11488 | |
43cd72b9 BW |
11489 | xg_init_vinsn (&vinsn); |
11490 | vinsn_from_chars (&vinsn, f); | |
11491 | ||
11492 | *tinsn = vinsn.slots[slot]; | |
11493 | xg_free_vinsn (&vinsn); | |
11494 | } | |
e0001a05 | 11495 | |
43cd72b9 BW |
11496 | |
11497 | static void | |
7fa3d080 BW |
11498 | tinsn_from_insnbuf (TInsn *tinsn, |
11499 | xtensa_insnbuf slotbuf, | |
11500 | xtensa_format fmt, | |
11501 | int slot) | |
43cd72b9 BW |
11502 | { |
11503 | int i; | |
11504 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11505 | |
11506 | /* Find the immed. */ | |
43cd72b9 BW |
11507 | tinsn_init (tinsn); |
11508 | tinsn->insn_type = ITYPE_INSN; | |
11509 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11510 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11511 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11512 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11513 | { |
43cd72b9 BW |
11514 | set_expr_const (&tinsn->tok[i], |
11515 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11516 | tinsn->opcode, i)); | |
e0001a05 NC |
11517 | } |
11518 | } | |
11519 | ||
11520 | ||
11521 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11522 | ||
11523 | static void | |
7fa3d080 | 11524 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11525 | { |
43cd72b9 | 11526 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11527 | int opnum; |
11528 | ||
43cd72b9 | 11529 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11530 | { |
11531 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11532 | assert (opnum >= 0); |
e7da6241 BW |
11533 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11534 | fragP->tc_frag_data.slot_symbols[slot], | |
11535 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 11536 | } |
19e8f41a | 11537 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
11538 | } |
11539 | ||
11540 | ||
11541 | static int | |
7fa3d080 | 11542 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11543 | { |
11544 | int i; | |
11545 | int text_bytes = 0; | |
11546 | ||
11547 | for (i = 0; i < istack->ninsn; i++) | |
11548 | { | |
43cd72b9 BW |
11549 | TInsn *tinsn = &istack->insn[i]; |
11550 | if (tinsn->insn_type == ITYPE_INSN) | |
11551 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11552 | } |
11553 | return text_bytes; | |
11554 | } | |
11555 | ||
11556 | ||
11557 | static int | |
7fa3d080 | 11558 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11559 | { |
11560 | int i; | |
11561 | int lit_bytes = 0; | |
11562 | ||
11563 | for (i = 0; i < istack->ninsn; i++) | |
11564 | { | |
43cd72b9 BW |
11565 | TInsn *tinsn = &istack->insn[i]; |
11566 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11567 | lit_bytes += 4; |
11568 | } | |
11569 | return lit_bytes; | |
11570 | } | |
11571 | ||
43cd72b9 BW |
11572 | \f |
11573 | /* vliw_insn functions. */ | |
11574 | ||
7fa3d080 BW |
11575 | static void |
11576 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11577 | { |
11578 | int i; | |
11579 | xtensa_isa isa = xtensa_default_isa; | |
11580 | ||
11581 | xg_clear_vinsn (v); | |
11582 | ||
11583 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11584 | if (v->insnbuf == NULL) | |
11585 | as_fatal (_("out of memory")); | |
11586 | ||
11587 | for (i = 0; i < MAX_SLOTS; i++) | |
11588 | { | |
43cd72b9 BW |
11589 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11590 | if (v->slotbuf[i] == NULL) | |
11591 | as_fatal (_("out of memory")); | |
11592 | } | |
11593 | } | |
11594 | ||
11595 | ||
7fa3d080 BW |
11596 | static void |
11597 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11598 | { |
11599 | int i; | |
65738a7d BW |
11600 | |
11601 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11602 | ||
43cd72b9 BW |
11603 | v->format = XTENSA_UNDEFINED; |
11604 | v->num_slots = 0; | |
11605 | v->inside_bundle = FALSE; | |
11606 | ||
11607 | if (xt_saved_debug_type != DEBUG_NONE) | |
11608 | debug_type = xt_saved_debug_type; | |
11609 | ||
11610 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11611 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11612 | } |
11613 | ||
11614 | ||
7fa3d080 BW |
11615 | static bfd_boolean |
11616 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11617 | { |
11618 | int i; | |
c138bc38 | 11619 | |
43cd72b9 BW |
11620 | for (i = 0; i < v->num_slots; i++) |
11621 | { | |
11622 | if (v->slots[i].is_specific_opcode) | |
11623 | return TRUE; | |
11624 | } | |
11625 | return FALSE; | |
11626 | } | |
11627 | ||
11628 | ||
7fa3d080 BW |
11629 | static void |
11630 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11631 | { |
11632 | int i; | |
11633 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11634 | for (i = 0; i < MAX_SLOTS; i++) | |
11635 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11636 | } | |
11637 | ||
11638 | ||
e7da6241 BW |
11639 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11640 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11641 | |
11642 | static bfd_boolean | |
7fa3d080 BW |
11643 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11644 | char *frag_offset, | |
11645 | fragS *fragP, | |
11646 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11647 | { |
11648 | xtensa_isa isa = xtensa_default_isa; | |
11649 | xtensa_format fmt = vinsn->format; | |
11650 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11651 | int slot; | |
11652 | bfd_boolean has_fixup = FALSE; | |
11653 | ||
11654 | xtensa_format_encode (isa, fmt, insnbuf); | |
11655 | ||
11656 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11657 | { | |
11658 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 11659 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
11660 | bfd_boolean tinsn_has_fixup = |
11661 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11662 | vinsn->slotbuf[slot]); | |
11663 | ||
11664 | xtensa_format_set_slot (isa, fmt, slot, | |
11665 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 11666 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
11667 | { |
11668 | if (vinsn->num_slots != 1) | |
11669 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
11670 | else if (record_fixup) | |
11671 | /* Instructions that generate TLS relocations should always be | |
11672 | relaxed in the front-end. If "record_fixup" is set, then this | |
11673 | function is being called during back-end relaxation, so flag | |
11674 | the unexpected behavior as an error. */ | |
11675 | as_bad (_("unexpected TLS relocation")); | |
11676 | else | |
11677 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
11678 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
11679 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
11680 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 11681 | } |
e7da6241 | 11682 | if (tinsn_has_fixup) |
43cd72b9 BW |
11683 | { |
11684 | int i; | |
11685 | xtensa_opcode opcode = tinsn->opcode; | |
11686 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11687 | has_fixup = TRUE; | |
11688 | ||
11689 | for (i = 0; i < noperands; i++) | |
11690 | { | |
11691 | expressionS* expr = &tinsn->tok[i]; | |
11692 | switch (expr->X_op) | |
11693 | { | |
11694 | case O_symbol: | |
11695 | case O_lo16: | |
11696 | case O_hi16: | |
11697 | if (get_relaxable_immed (opcode) == i) | |
11698 | { | |
e7da6241 BW |
11699 | /* Add a fix record for the instruction, except if this |
11700 | function is being called prior to relaxation, i.e., | |
11701 | if record_fixup is false, and the instruction might | |
11702 | be relaxed later. */ | |
11703 | if (record_fixup | |
11704 | || tinsn->is_specific_opcode | |
11705 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11706 | { |
e7da6241 BW |
11707 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11708 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11709 | } |
11710 | else | |
11711 | { | |
e7da6241 BW |
11712 | if (expr->X_op != O_symbol) |
11713 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11714 | tinsn->symbol = expr->X_add_symbol; |
11715 | tinsn->offset = expr->X_add_number; | |
11716 | } | |
11717 | } | |
11718 | else | |
e7da6241 | 11719 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11720 | break; |
11721 | ||
11722 | case O_constant: | |
11723 | case O_register: | |
11724 | break; | |
11725 | ||
43cd72b9 | 11726 | default: |
e7da6241 | 11727 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11728 | break; |
11729 | } | |
11730 | } | |
11731 | } | |
11732 | } | |
11733 | ||
11734 | return has_fixup; | |
11735 | } | |
11736 | ||
11737 | ||
11738 | static void | |
7fa3d080 | 11739 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11740 | { |
11741 | static xtensa_insnbuf insnbuf = NULL; | |
11742 | static xtensa_insnbuf slotbuf = NULL; | |
11743 | int i; | |
11744 | xtensa_format fmt; | |
11745 | xtensa_isa isa = xtensa_default_isa; | |
11746 | ||
11747 | if (!insnbuf) | |
11748 | { | |
11749 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11750 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11751 | } | |
11752 | ||
d77b99c9 | 11753 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11754 | fmt = xtensa_format_decode (isa, insnbuf); |
11755 | if (fmt == XTENSA_UNDEFINED) | |
11756 | as_fatal (_("cannot decode instruction format")); | |
11757 | vinsn->format = fmt; | |
11758 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11759 | ||
11760 | for (i = 0; i < vinsn->num_slots; i++) | |
11761 | { | |
11762 | TInsn *tinsn = &vinsn->slots[i]; | |
11763 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11764 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11765 | } | |
11766 | } | |
11767 | ||
e0001a05 NC |
11768 | \f |
11769 | /* Expression utilities. */ | |
11770 | ||
43cd72b9 | 11771 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11772 | |
11773 | bfd_boolean | |
7fa3d080 | 11774 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11775 | { |
11776 | return (s->X_op == O_constant); | |
11777 | } | |
11778 | ||
11779 | ||
11780 | /* Get the expression constant. | |
43cd72b9 | 11781 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11782 | |
11783 | offsetT | |
7fa3d080 | 11784 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11785 | { |
11786 | assert (expr_is_const (s)); | |
11787 | return s->X_add_number; | |
11788 | } | |
11789 | ||
11790 | ||
11791 | /* Set the expression to a constant value. */ | |
11792 | ||
11793 | void | |
7fa3d080 | 11794 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11795 | { |
11796 | s->X_op = O_constant; | |
11797 | s->X_add_number = val; | |
11798 | s->X_add_symbol = NULL; | |
11799 | s->X_op_symbol = NULL; | |
11800 | } | |
11801 | ||
11802 | ||
43cd72b9 | 11803 | bfd_boolean |
7fa3d080 | 11804 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11805 | { |
11806 | return (s->X_op == O_register); | |
11807 | } | |
11808 | ||
11809 | ||
11810 | /* Get the expression constant. | |
11811 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11812 | ||
11813 | offsetT | |
7fa3d080 | 11814 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11815 | { |
11816 | assert (expr_is_register (s)); | |
11817 | return s->X_add_number; | |
11818 | } | |
11819 | ||
11820 | ||
e0001a05 NC |
11821 | /* Set the expression to a symbol + constant offset. */ |
11822 | ||
11823 | void | |
7fa3d080 | 11824 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11825 | { |
11826 | s->X_op = O_symbol; | |
11827 | s->X_add_symbol = sym; | |
11828 | s->X_op_symbol = NULL; /* unused */ | |
11829 | s->X_add_number = offset; | |
11830 | } | |
11831 | ||
11832 | ||
43cd72b9 BW |
11833 | /* Return TRUE if the two expressions are equal. */ |
11834 | ||
e0001a05 | 11835 | bfd_boolean |
7fa3d080 | 11836 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11837 | { |
11838 | if (s1->X_op != s2->X_op) | |
11839 | return FALSE; | |
11840 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11841 | return FALSE; | |
11842 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11843 | return FALSE; | |
11844 | if (s1->X_add_number != s2->X_add_number) | |
11845 | return FALSE; | |
11846 | return TRUE; | |
11847 | } | |
11848 | ||
11849 | ||
11850 | static void | |
7fa3d080 | 11851 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11852 | { |
11853 | memcpy (dst, src, sizeof (expressionS)); | |
11854 | } | |
11855 | ||
11856 | \f | |
9456465c | 11857 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11858 | |
11859 | struct rename_section_struct | |
11860 | { | |
11861 | char *old_name; | |
11862 | char *new_name; | |
11863 | struct rename_section_struct *next; | |
11864 | }; | |
11865 | ||
11866 | static struct rename_section_struct *section_rename; | |
11867 | ||
11868 | ||
9456465c BW |
11869 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11870 | entries to the section_rename list. Note: Specifying multiple | |
11871 | renamings separated by colons is not documented and is retained only | |
11872 | for backward compatibility. */ | |
e0001a05 | 11873 | |
7fa3d080 BW |
11874 | static void |
11875 | build_section_rename (const char *arg) | |
e0001a05 | 11876 | { |
9456465c | 11877 | struct rename_section_struct *r; |
e0001a05 NC |
11878 | char *this_arg = NULL; |
11879 | char *next_arg = NULL; | |
11880 | ||
9456465c | 11881 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11882 | { |
9456465c BW |
11883 | char *old_name, *new_name; |
11884 | ||
e0001a05 NC |
11885 | if (this_arg) |
11886 | { | |
11887 | next_arg = strchr (this_arg, ':'); | |
11888 | if (next_arg) | |
11889 | { | |
11890 | *next_arg = '\0'; | |
11891 | next_arg++; | |
11892 | } | |
11893 | } | |
e0001a05 | 11894 | |
9456465c BW |
11895 | old_name = this_arg; |
11896 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11897 | |
9456465c BW |
11898 | if (*old_name == '\0') |
11899 | { | |
11900 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11901 | continue; | |
11902 | } | |
11903 | if (!new_name || new_name[1] == '\0') | |
11904 | { | |
11905 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11906 | old_name); | |
11907 | continue; | |
11908 | } | |
11909 | *new_name = '\0'; | |
11910 | new_name++; | |
e0001a05 | 11911 | |
9456465c BW |
11912 | /* Check for invalid section renaming. */ |
11913 | for (r = section_rename; r != NULL; r = r->next) | |
11914 | { | |
11915 | if (strcmp (r->old_name, old_name) == 0) | |
11916 | as_bad (_("section %s renamed multiple times"), old_name); | |
11917 | if (strcmp (r->new_name, new_name) == 0) | |
11918 | as_bad (_("multiple sections remapped to output section %s"), | |
11919 | new_name); | |
11920 | } | |
e0001a05 | 11921 | |
9456465c BW |
11922 | /* Now add it. */ |
11923 | r = (struct rename_section_struct *) | |
11924 | xmalloc (sizeof (struct rename_section_struct)); | |
11925 | r->old_name = xstrdup (old_name); | |
11926 | r->new_name = xstrdup (new_name); | |
11927 | r->next = section_rename; | |
11928 | section_rename = r; | |
e0001a05 | 11929 | } |
e0001a05 NC |
11930 | } |
11931 | ||
11932 | ||
9456465c BW |
11933 | char * |
11934 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11935 | { |
11936 | struct rename_section_struct *r = section_rename; | |
11937 | ||
11938 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11939 | { |
11940 | if (strcmp (r->old_name, name) == 0) | |
11941 | return r->new_name; | |
11942 | } | |
e0001a05 NC |
11943 | |
11944 | return name; | |
11945 | } |