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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
fd67aa11 | 2 | Copyright (C) 2003-2024 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
e0001a05 | 21 | #include "as.h" |
df7b86aa | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "sb.h" |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
d0a2cfbd | 30 | #include "xtensa-dynconfig.h" |
b0b79343 | 31 | #include "elf/xtensa.h" |
e0001a05 NC |
32 | |
33 | #ifndef uint32 | |
34 | #define uint32 unsigned int | |
35 | #endif | |
36 | #ifndef int32 | |
37 | #define int32 signed int | |
38 | #endif | |
39 | ||
40 | /* Notes: | |
41 | ||
e0001a05 NC |
42 | Naming conventions (used somewhat inconsistently): |
43 | The xtensa_ functions are exported | |
44 | The xg_ functions are internal | |
45 | ||
46 | We also have a couple of different extensibility mechanisms. | |
47 | 1) The idiom replacement: | |
48 | This is used when a line is first parsed to | |
49 | replace an instruction pattern with another instruction | |
50 | It is currently limited to replacements of instructions | |
51 | with constant operands. | |
52 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
53 | replacement patterns. When an instruction's immediate field | |
54 | does not fit the next instruction sequence is attempted. | |
55 | In addition, "narrow" opcodes are supported this way. */ | |
56 | ||
57 | ||
58 | /* Define characters with special meanings to GAS. */ | |
59 | const char comment_chars[] = "#"; | |
60 | const char line_comment_chars[] = "#"; | |
61 | const char line_separator_chars[] = ";"; | |
62 | const char EXP_CHARS[] = "eE"; | |
63 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
64 | ||
65 | ||
43cd72b9 BW |
66 | /* Flags to indicate whether the hardware supports the density and |
67 | absolute literals options. */ | |
e0001a05 | 68 | |
5b7c81bd AM |
69 | bool density_supported; |
70 | bool absolute_literals_supported; | |
43cd72b9 | 71 | |
935f1f4b MF |
72 | static unsigned microarch_earliest; |
73 | ||
43cd72b9 BW |
74 | static vliw_insn cur_vinsn; |
75 | ||
77cba8a3 | 76 | unsigned xtensa_num_pipe_stages; |
f7e16c2a | 77 | unsigned xtensa_fetch_width; |
43cd72b9 BW |
78 | |
79 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
80 | ||
81 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 82 | allows us to assert that we haven't crossed over into the |
43cd72b9 | 83 | back end. */ |
ed2917de | 84 | static bool past_xtensa_md_finish = false; |
e0001a05 NC |
85 | |
86 | /* Flags for properties of the last instruction in a segment. */ | |
87 | #define FLAG_IS_A0_WRITER 0x1 | |
88 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
89 | ||
90 | ||
91 | /* We define a special segment names ".literal" to place literals | |
92 | into. The .fini and .init sections are special because they | |
93 | contain code that is moved together by the linker. We give them | |
94 | their own special .fini.literal and .init.literal sections. */ | |
95 | ||
96 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 97 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 98 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 99 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
100 | |
101 | ||
43cd72b9 | 102 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
103 | state of the literal collection pools. If lit_prefix is set, it is |
104 | used to determine the literal section names; otherwise, the literal | |
105 | sections are determined based on the current text section. The | |
106 | lit_seg and lit4_seg fields cache these literal sections, with the | |
107 | current_text_seg field used a tag to indicate whether the cached | |
108 | values are valid. */ | |
e0001a05 NC |
109 | |
110 | typedef struct lit_state_struct | |
111 | { | |
74869ac7 BW |
112 | char *lit_prefix; |
113 | segT current_text_seg; | |
e0001a05 | 114 | segT lit_seg; |
43cd72b9 | 115 | segT lit4_seg; |
e0001a05 NC |
116 | } lit_state; |
117 | ||
118 | static lit_state default_lit_sections; | |
119 | ||
120 | ||
74869ac7 BW |
121 | /* We keep a list of literal segments. The seg_list type is the node |
122 | for this list. The literal_head pointer is the head of the list, | |
123 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
124 | |
125 | typedef struct seg_list_struct | |
126 | { | |
127 | struct seg_list_struct *next; | |
128 | segT seg; | |
129 | } seg_list; | |
130 | ||
131 | static seg_list literal_head_h; | |
132 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
133 | |
134 | ||
82e7541d BW |
135 | /* Lists of symbols. We keep a list of symbols that label the current |
136 | instruction, so that we can adjust the symbols when inserting alignment | |
137 | for various instructions. We also keep a list of all the symbols on | |
138 | literals, so that we can fix up those symbols when the literals are | |
139 | later moved into the text sections. */ | |
140 | ||
141 | typedef struct sym_list_struct | |
142 | { | |
143 | struct sym_list_struct *next; | |
144 | symbolS *sym; | |
145 | } sym_list; | |
146 | ||
147 | static sym_list *insn_labels = NULL; | |
148 | static sym_list *free_insn_labels = NULL; | |
149 | static sym_list *saved_insn_labels = NULL; | |
150 | ||
151 | static sym_list *literal_syms; | |
152 | ||
153 | ||
43cd72b9 BW |
154 | /* Flags to determine whether to prefer const16 or l32r |
155 | if both options are available. */ | |
156 | int prefer_const16 = 0; | |
157 | int prefer_l32r = 0; | |
158 | ||
e0001a05 NC |
159 | /* Global flag to indicate when we are emitting literals. */ |
160 | int generating_literals = 0; | |
161 | ||
43cd72b9 BW |
162 | /* The following PROPERTY table definitions are copied from |
163 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
164 | ||
165 | /* Flags in the property tables to specify whether blocks of memory | |
166 | are literals, instructions, data, or unreachable. For | |
167 | instructions, blocks that begin loop targets and branch targets are | |
168 | designated. Blocks that do not allow density, instruction | |
169 | reordering or transformation are also specified. Finally, for | |
170 | branch targets, branch target alignment priority is included. | |
171 | Alignment of the next block is specified in the current block | |
172 | and the size of the current block does not include any fill required | |
173 | to align to the next block. */ | |
174 | ||
175 | #define XTENSA_PROP_LITERAL 0x00000001 | |
176 | #define XTENSA_PROP_INSN 0x00000002 | |
177 | #define XTENSA_PROP_DATA 0x00000004 | |
178 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
179 | /* Instruction only properties at beginning of code. */ | |
180 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
181 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
182 | /* Instruction only properties about code. */ | |
183 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
184 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
185 | /* Historically, NO_TRANSFORM was a property of instructions, |
186 | but it should apply to literals under certain circumstances. */ | |
187 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
188 | |
189 | /* Branch target alignment information. This transmits information | |
190 | to the linker optimization about the priority of aligning a | |
191 | particular block for branch target alignment: None, low priority, | |
192 | high priority, or required. These only need to be checked in | |
193 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
194 | Common usage is | |
195 | ||
196 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
197 | case XTENSA_PROP_BT_ALIGN_NONE: | |
198 | case XTENSA_PROP_BT_ALIGN_LOW: | |
199 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
200 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
201 | */ | |
202 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
203 | ||
204 | /* No branch target alignment. */ | |
205 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
206 | /* Low priority branch target alignment. */ | |
207 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
208 | /* High priority branch target alignment. */ | |
209 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
210 | /* Required branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
212 | ||
43cd72b9 BW |
213 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ |
214 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
215 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
216 | ||
217 | ||
218 | /* Alignment is specified in the block BEFORE the one that needs | |
219 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
220 | get the required alignment specified as a power of 2. Use | |
221 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
222 | alignment. Be careful of side effects since the SET will evaluate | |
223 | flags twice. Also, note that the SIZE of a block in the property | |
224 | table does not include the alignment size, so the alignment fill | |
225 | must be calculated to determine if two blocks are contiguous. | |
226 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
227 | possible future implementation. */ | |
228 | ||
229 | #define XTENSA_PROP_ALIGN 0x00000800 | |
230 | ||
231 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
232 | ||
43cd72b9 BW |
233 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ |
234 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
235 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
236 | ||
237 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
238 | ||
239 | ||
240 | /* Structure for saving instruction and alignment per-fragment data | |
241 | that will be written to the object file. This structure is | |
242 | equivalent to the actual data that will be written out to the file | |
243 | but is easier to use. We provide a conversion to file flags | |
244 | in frag_flags_to_number. */ | |
245 | ||
246 | typedef struct frag_flags_struct frag_flags; | |
247 | ||
248 | struct frag_flags_struct | |
249 | { | |
250 | /* is_literal should only be used after xtensa_move_literals. | |
251 | If you need to check if you are generating a literal fragment, | |
252 | then use the generating_literals global. */ | |
253 | ||
254 | unsigned is_literal : 1; | |
255 | unsigned is_insn : 1; | |
256 | unsigned is_data : 1; | |
257 | unsigned is_unreachable : 1; | |
258 | ||
99ded152 BW |
259 | /* is_specific_opcode implies no_transform. */ |
260 | unsigned is_no_transform : 1; | |
261 | ||
43cd72b9 BW |
262 | struct |
263 | { | |
264 | unsigned is_loop_target : 1; | |
265 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
266 | unsigned bt_align_priority : 2; | |
267 | ||
268 | unsigned is_no_density : 1; | |
269 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
270 | |
271 | unsigned is_no_reorder : 1; | |
272 | ||
273 | /* Uses absolute literal addressing for l32r. */ | |
274 | unsigned is_abslit : 1; | |
275 | } insn; | |
276 | unsigned is_align : 1; | |
277 | unsigned alignment : 5; | |
278 | }; | |
279 | ||
280 | ||
281 | /* Structure for saving information about a block of property data | |
282 | for frags that have the same flags. */ | |
283 | struct xtensa_block_info_struct | |
284 | { | |
285 | segT sec; | |
286 | bfd_vma offset; | |
287 | size_t size; | |
288 | frag_flags flags; | |
289 | struct xtensa_block_info_struct *next; | |
290 | }; | |
291 | ||
e0001a05 NC |
292 | |
293 | /* Structure for saving the current state before emitting literals. */ | |
294 | typedef struct emit_state_struct | |
295 | { | |
296 | const char *name; | |
297 | segT now_seg; | |
298 | subsegT now_subseg; | |
299 | int generating_literals; | |
300 | } emit_state; | |
301 | ||
302 | ||
43cd72b9 BW |
303 | /* Opcode placement information */ |
304 | ||
305 | typedef unsigned long long bitfield; | |
306 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
307 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
308 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
309 | ||
310 | #define MAX_FORMATS 32 | |
311 | ||
312 | typedef struct op_placement_info_struct | |
313 | { | |
314 | int num_formats; | |
315 | /* A number describing how restrictive the issue is for this | |
316 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 317 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 318 | only one format but many slots in that format. The most |
c138bc38 | 319 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
320 | format. */ |
321 | int issuef; | |
43cd72b9 | 322 | xtensa_format narrowest; |
43cd72b9 | 323 | char narrowest_size; |
b2d179be | 324 | char narrowest_slot; |
43cd72b9 BW |
325 | |
326 | /* formats is a bitfield with the Nth bit set | |
327 | if the opcode fits in the Nth xtensa_format. */ | |
328 | bitfield formats; | |
329 | ||
330 | /* slots[N]'s Mth bit is set if the op fits in the | |
331 | Mth slot of the Nth xtensa_format. */ | |
332 | bitfield slots[MAX_FORMATS]; | |
333 | ||
334 | /* A count of the number of slots in a given format | |
335 | an op can fit (i.e., the bitcount of the slot field above). */ | |
336 | char slots_in_format[MAX_FORMATS]; | |
337 | ||
338 | } op_placement_info, *op_placement_info_table; | |
339 | ||
340 | op_placement_info_table op_placement_table; | |
341 | ||
342 | ||
343 | /* Extra expression types. */ | |
344 | ||
345 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
346 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
347 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 348 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
349 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
350 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
351 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
352 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
353 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 354 | |
bbdd25a8 BW |
355 | struct suffix_reloc_map |
356 | { | |
b9bb4a93 | 357 | const char *suffix; |
bbdd25a8 BW |
358 | int length; |
359 | bfd_reloc_code_real_type reloc; | |
cc34adb2 | 360 | operatorT operator; |
bbdd25a8 BW |
361 | }; |
362 | ||
363 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
364 | ||
365 | static struct suffix_reloc_map suffix_relocs[] = | |
366 | { | |
367 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
368 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
369 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 370 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
371 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
372 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
373 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
374 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
375 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
376 | }; |
377 | ||
43cd72b9 | 378 | |
e0001a05 NC |
379 | /* Directives. */ |
380 | ||
381 | typedef enum | |
382 | { | |
383 | directive_none = 0, | |
384 | directive_literal, | |
385 | directive_density, | |
43cd72b9 | 386 | directive_transform, |
e0001a05 NC |
387 | directive_freeregs, |
388 | directive_longcalls, | |
43cd72b9 BW |
389 | directive_literal_prefix, |
390 | directive_schedule, | |
391 | directive_absolute_literals, | |
392 | directive_last_directive | |
e0001a05 NC |
393 | } directiveE; |
394 | ||
395 | typedef struct | |
396 | { | |
397 | const char *name; | |
5b7c81bd | 398 | bool can_be_negated; |
e0001a05 NC |
399 | } directive_infoS; |
400 | ||
401 | const directive_infoS directive_info[] = | |
402 | { | |
5b7c81bd AM |
403 | { "none", false }, |
404 | { "literal", false }, | |
405 | { "density", true }, | |
406 | { "transform", true }, | |
407 | { "freeregs", false }, | |
408 | { "longcalls", true }, | |
409 | { "literal_prefix", false }, | |
410 | { "schedule", true }, | |
411 | { "absolute-literals", true } | |
e0001a05 NC |
412 | }; |
413 | ||
5b7c81bd AM |
414 | bool directive_state[] = |
415 | { | |
416 | false, /* none */ | |
417 | false, /* literal */ | |
418 | false, /* density */ | |
419 | true, /* transform */ | |
420 | false, /* freeregs */ | |
421 | false, /* longcalls */ | |
422 | false, /* literal_prefix */ | |
423 | false, /* schedule */ | |
424 | false /* absolute_literals */ | |
e0001a05 NC |
425 | }; |
426 | ||
b46824bd MF |
427 | /* A circular list of all potential and actual literal pool locations |
428 | in a segment. */ | |
429 | struct litpool_frag | |
430 | { | |
431 | struct litpool_frag *next; | |
432 | struct litpool_frag *prev; | |
433 | fragS *fragP; | |
434 | addressT addr; | |
435 | short priority; /* 1, 2, or 3 -- 1 is highest */ | |
436 | short original_priority; | |
cd665a94 | 437 | int literal_count; |
b46824bd MF |
438 | }; |
439 | ||
440 | /* Map a segment to its litpool_frag list. */ | |
441 | struct litpool_seg | |
442 | { | |
443 | struct litpool_seg *next; | |
444 | asection *seg; | |
445 | struct litpool_frag frag_list; | |
446 | int frag_count; /* since last litpool location */ | |
447 | }; | |
448 | ||
449 | static struct litpool_seg litpool_seg_list; | |
450 | ||
cd665a94 MF |
451 | /* Limit maximal size of auto litpool by half of the j range. */ |
452 | #define MAX_AUTO_POOL_LITERALS 16384 | |
453 | ||
454 | /* Limit maximal size of explicit literal pool by l32r range. */ | |
455 | #define MAX_EXPLICIT_POOL_LITERALS 65536 | |
456 | ||
457 | #define MAX_POOL_LITERALS \ | |
458 | (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS) | |
e0001a05 NC |
459 | |
460 | /* Directive functions. */ | |
461 | ||
7fa3d080 BW |
462 | static void xtensa_begin_directive (int); |
463 | static void xtensa_end_directive (int); | |
74869ac7 | 464 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
465 | static void xtensa_literal_position (int); |
466 | static void xtensa_literal_pseudo (int); | |
467 | static void xtensa_frequency_pseudo (int); | |
468 | static void xtensa_elf_cons (int); | |
fb227da0 | 469 | static void xtensa_leb128 (int); |
e0001a05 | 470 | |
7fa3d080 | 471 | /* Parsing and Idiom Translation. */ |
e0001a05 | 472 | |
7fa3d080 | 473 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 474 | |
e0001a05 NC |
475 | /* Various Other Internal Functions. */ |
476 | ||
5b7c81bd AM |
477 | extern bool xg_is_single_relaxable_insn (TInsn *, TInsn *, bool); |
478 | static bool xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
479 | static void xtensa_mark_literal_pool_location (void); |
480 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
481 | static fragS *get_literal_pool_location (segT); | |
482 | static void set_literal_pool_location (segT, fragS *); | |
483 | static void xtensa_set_frag_assembly_state (fragS *); | |
484 | static void finish_vinsn (vliw_insn *); | |
5b7c81bd | 485 | static bool emit_single_op (TInsn *); |
34e41783 | 486 | static int total_frag_text_expansion (fragS *); |
5b7c81bd | 487 | static bool use_trampolines = true; |
a82c7d90 | 488 | static void xtensa_check_frag_count (void); |
5b7c81bd | 489 | static void xtensa_create_trampoline_frag (bool); |
a82c7d90 DW |
490 | static void xtensa_maybe_create_trampoline_frag (void); |
491 | struct trampoline_frag; | |
46888d71 MF |
492 | static int init_trampoline_frag (fragS *); |
493 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset); | |
5b7c81bd AM |
494 | static void xtensa_maybe_create_literal_pool_frag (bool, bool); |
495 | static bool auto_litpools = false; | |
cd665a94 | 496 | static int auto_litpool_limit = 0; |
5b7c81bd | 497 | static bool xtensa_is_init_fini (segT seg); |
e0001a05 NC |
498 | |
499 | /* Alignment Functions. */ | |
500 | ||
d77b99c9 | 501 | static int get_text_align_power (unsigned); |
5b7c81bd | 502 | static int get_text_align_max_fill_size (int, bool, bool); |
664df4e4 | 503 | static int branch_align_power (segT); |
e0001a05 NC |
504 | |
505 | /* Helpers for xtensa_relax_frag(). */ | |
506 | ||
7fa3d080 | 507 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 508 | |
b08b5071 | 509 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 510 | |
7fa3d080 | 511 | static unsigned get_last_insn_flags (segT, subsegT); |
5b7c81bd | 512 | static void set_last_insn_flags (segT, subsegT, unsigned, bool); |
b08b5071 BW |
513 | static float get_subseg_total_freq (segT, subsegT); |
514 | static float get_subseg_target_freq (segT, subsegT); | |
515 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
516 | |
517 | /* Segment list functions. */ | |
518 | ||
7fa3d080 BW |
519 | static void xtensa_move_literals (void); |
520 | static void xtensa_reorder_segments (void); | |
521 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
522 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
523 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
524 | static void xtensa_restore_emit_state (emit_state *); | |
5b7c81bd | 525 | static segT cache_literal_section (bool); |
e0001a05 | 526 | |
43cd72b9 BW |
527 | /* op_placement_info functions. */ |
528 | ||
7fa3d080 | 529 | static void init_op_placement_info_table (void); |
5b7c81bd | 530 | extern bool opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); |
7fa3d080 BW |
531 | static int xg_get_single_size (xtensa_opcode); |
532 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 533 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 534 | |
e0001a05 | 535 | /* TInsn and IStack functions. */ |
43cd72b9 | 536 | |
5b7c81bd AM |
537 | static bool tinsn_has_symbolic_operands (const TInsn *); |
538 | static bool tinsn_has_invalid_symbolic_operands (const TInsn *); | |
539 | static bool tinsn_has_complex_operands (const TInsn *); | |
540 | static bool tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
541 | static bool tinsn_check_arguments (const TInsn *); | |
7fa3d080 BW |
542 | static void tinsn_from_chars (TInsn *, char *, int); |
543 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
544 | static int get_num_stack_text_bytes (IStack *); | |
545 | static int get_num_stack_literal_bytes (IStack *); | |
5b7c81bd | 546 | static bool tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); |
e0001a05 | 547 | |
43cd72b9 BW |
548 | /* vliw_insn functions. */ |
549 | ||
7fa3d080 | 550 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 551 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 | 552 | static void xg_clear_vinsn (vliw_insn *); |
5b7c81bd | 553 | static bool vinsn_has_specific_opcodes (vliw_insn *); |
7fa3d080 | 554 | static void xg_free_vinsn (vliw_insn *); |
5b7c81bd AM |
555 | static bool vinsn_to_insnbuf |
556 | (vliw_insn *, char *, fragS *, bool); | |
7fa3d080 | 557 | static void vinsn_from_chars (vliw_insn *, char *); |
43cd72b9 | 558 | |
e0001a05 | 559 | /* Expression Utilities. */ |
43cd72b9 | 560 | |
5b7c81bd | 561 | bool expr_is_const (const expressionS *); |
7fa3d080 BW |
562 | offsetT get_expr_const (const expressionS *); |
563 | void set_expr_const (expressionS *, offsetT); | |
5b7c81bd | 564 | bool expr_is_register (const expressionS *); |
7fa3d080 BW |
565 | offsetT get_expr_register (const expressionS *); |
566 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
5b7c81bd | 567 | bool expr_is_equal (expressionS *, expressionS *); |
7fa3d080 | 568 | static void copy_expr (expressionS *, const expressionS *); |
e0001a05 | 569 | |
9456465c BW |
570 | /* Section renaming. */ |
571 | ||
7fa3d080 | 572 | static void build_section_rename (const char *); |
e0001a05 | 573 | |
e0001a05 NC |
574 | |
575 | /* ISA imported from bfd. */ | |
576 | extern xtensa_isa xtensa_default_isa; | |
577 | ||
578 | extern int target_big_endian; | |
579 | ||
580 | static xtensa_opcode xtensa_addi_opcode; | |
581 | static xtensa_opcode xtensa_addmi_opcode; | |
582 | static xtensa_opcode xtensa_call0_opcode; | |
583 | static xtensa_opcode xtensa_call4_opcode; | |
584 | static xtensa_opcode xtensa_call8_opcode; | |
585 | static xtensa_opcode xtensa_call12_opcode; | |
586 | static xtensa_opcode xtensa_callx0_opcode; | |
587 | static xtensa_opcode xtensa_callx4_opcode; | |
588 | static xtensa_opcode xtensa_callx8_opcode; | |
589 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 590 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 591 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 592 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
593 | static xtensa_opcode xtensa_movi_opcode; |
594 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 595 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 596 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 597 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 598 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
599 | static xtensa_opcode xtensa_loop_opcode; |
600 | static xtensa_opcode xtensa_loopnez_opcode; | |
601 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 602 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
603 | static xtensa_opcode xtensa_nop_n_opcode; |
604 | static xtensa_opcode xtensa_or_opcode; | |
605 | static xtensa_opcode xtensa_ret_opcode; | |
606 | static xtensa_opcode xtensa_ret_n_opcode; | |
607 | static xtensa_opcode xtensa_retw_opcode; | |
608 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 609 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 610 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 611 | static int config_max_slots = 0; |
e0001a05 NC |
612 | |
613 | \f | |
614 | /* Command-line Options. */ | |
615 | ||
5b7c81bd | 616 | bool use_literal_section = true; |
19fc3723 | 617 | enum flix_level produce_flix = FLIX_ALL; |
5b7c81bd AM |
618 | static bool align_targets = true; |
619 | static bool warn_unaligned_branch_targets = false; | |
620 | static bool has_a0_b_retw = false; | |
621 | static bool workaround_a0_b_retw = false; | |
622 | static bool workaround_b_j_loop_end = false; | |
623 | static bool workaround_short_loop = false; | |
624 | static bool maybe_has_short_loop = false; | |
625 | static bool workaround_close_loop_end = false; | |
626 | static bool maybe_has_close_loop_end = false; | |
627 | static bool enforce_three_byte_loop_align = false; | |
628 | static bool opt_linkrelax = true; | |
e0001a05 | 629 | |
43cd72b9 BW |
630 | /* When workaround_short_loops is TRUE, all loops with early exits must |
631 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
632 | to the workaround_short_loop flag. In addition to the | |
633 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
634 | must have at least 3 instructions. */ | |
e0001a05 | 635 | |
5b7c81bd | 636 | static bool workaround_all_short_loops = false; |
e0001a05 | 637 | |
8255c61b MF |
638 | /* Generate individual property section for every section. |
639 | This option is defined in BDF library. */ | |
5b7c81bd | 640 | extern bool elf32xtensa_separate_props; |
7fa3d080 | 641 | |
7a77f1ac MF |
642 | /* Xtensa ABI. |
643 | This option is defined in BDF library. */ | |
644 | extern int elf32xtensa_abi; | |
645 | ||
7fa3d080 BW |
646 | static void |
647 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
648 | { | |
649 | if (earliest > latest) | |
650 | as_fatal (_("illegal range of target hardware versions")); | |
651 | ||
652 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
653 | if (earliest < 105000 || latest < 105000) | |
654 | { | |
5b7c81bd AM |
655 | workaround_a0_b_retw |= true; |
656 | workaround_b_j_loop_end |= true; | |
657 | workaround_short_loop |= true; | |
658 | workaround_close_loop_end |= true; | |
659 | workaround_all_short_loops |= true; | |
660 | enforce_three_byte_loop_align = true; | |
7fa3d080 BW |
661 | } |
662 | } | |
663 | ||
664 | ||
e0001a05 NC |
665 | enum |
666 | { | |
667 | option_density = OPTION_MD_BASE, | |
668 | option_no_density, | |
669 | ||
19fc3723 SA |
670 | option_flix, |
671 | option_no_generate_flix, | |
672 | option_no_flix, | |
673 | ||
e0001a05 NC |
674 | option_relax, |
675 | option_no_relax, | |
676 | ||
43cd72b9 BW |
677 | option_link_relax, |
678 | option_no_link_relax, | |
679 | ||
e0001a05 NC |
680 | option_generics, |
681 | option_no_generics, | |
682 | ||
43cd72b9 BW |
683 | option_transform, |
684 | option_no_transform, | |
685 | ||
e0001a05 NC |
686 | option_text_section_literals, |
687 | option_no_text_section_literals, | |
688 | ||
43cd72b9 BW |
689 | option_absolute_literals, |
690 | option_no_absolute_literals, | |
691 | ||
e0001a05 NC |
692 | option_align_targets, |
693 | option_no_align_targets, | |
694 | ||
43cd72b9 | 695 | option_warn_unaligned_targets, |
e0001a05 NC |
696 | |
697 | option_longcalls, | |
698 | option_no_longcalls, | |
699 | ||
700 | option_workaround_a0_b_retw, | |
701 | option_no_workaround_a0_b_retw, | |
702 | ||
703 | option_workaround_b_j_loop_end, | |
704 | option_no_workaround_b_j_loop_end, | |
705 | ||
706 | option_workaround_short_loop, | |
707 | option_no_workaround_short_loop, | |
708 | ||
709 | option_workaround_all_short_loops, | |
710 | option_no_workaround_all_short_loops, | |
711 | ||
712 | option_workaround_close_loop_end, | |
713 | option_no_workaround_close_loop_end, | |
714 | ||
715 | option_no_workarounds, | |
716 | ||
e0001a05 | 717 | option_rename_section_name, |
e0001a05 | 718 | |
43cd72b9 BW |
719 | option_prefer_l32r, |
720 | option_prefer_const16, | |
721 | ||
a82c7d90 DW |
722 | option_target_hardware, |
723 | ||
724 | option_trampolines, | |
725 | option_no_trampolines, | |
b46824bd MF |
726 | |
727 | option_auto_litpools, | |
728 | option_no_auto_litpools, | |
729 | option_auto_litpool_limit, | |
8255c61b MF |
730 | |
731 | option_separate_props, | |
732 | option_no_separate_props, | |
7a77f1ac MF |
733 | |
734 | option_abi_windowed, | |
735 | option_abi_call0, | |
e0001a05 NC |
736 | }; |
737 | ||
738 | const char *md_shortopts = ""; | |
739 | ||
740 | struct option md_longopts[] = | |
741 | { | |
43cd72b9 BW |
742 | { "density", no_argument, NULL, option_density }, |
743 | { "no-density", no_argument, NULL, option_no_density }, | |
744 | ||
19fc3723 SA |
745 | { "flix", no_argument, NULL, option_flix }, |
746 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
747 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
748 | ||
43cd72b9 BW |
749 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
750 | to the "transform" option. */ | |
751 | { "relax", no_argument, NULL, option_relax }, | |
752 | { "no-relax", no_argument, NULL, option_no_relax }, | |
753 | { "generics", no_argument, NULL, option_generics }, | |
754 | { "no-generics", no_argument, NULL, option_no_generics }, | |
755 | ||
756 | { "transform", no_argument, NULL, option_transform }, | |
757 | { "no-transform", no_argument, NULL, option_no_transform }, | |
758 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
759 | { "no-text-section-literals", no_argument, NULL, | |
760 | option_no_text_section_literals }, | |
761 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
762 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
763 | /* This option was changed from -align-target to -target-align |
764 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 765 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
766 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
767 | { "warn-unaligned-targets", no_argument, NULL, | |
768 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
769 | { "longcalls", no_argument, NULL, option_longcalls }, |
770 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
771 | ||
772 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
773 | option_no_workaround_a0_b_retw }, | |
774 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 775 | |
43cd72b9 BW |
776 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
777 | option_no_workaround_b_j_loop_end }, | |
778 | { "workaround-b-j-loop-end", no_argument, NULL, | |
779 | option_workaround_b_j_loop_end }, | |
e0001a05 | 780 | |
43cd72b9 BW |
781 | { "no-workaround-short-loops", no_argument, NULL, |
782 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
783 | { "workaround-short-loops", no_argument, NULL, |
784 | option_workaround_short_loop }, | |
e0001a05 | 785 | |
43cd72b9 BW |
786 | { "no-workaround-all-short-loops", no_argument, NULL, |
787 | option_no_workaround_all_short_loops }, | |
788 | { "workaround-all-short-loop", no_argument, NULL, | |
789 | option_workaround_all_short_loops }, | |
790 | ||
791 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
792 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
793 | ||
794 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
795 | ||
796 | { "no-workaround-close-loop-end", no_argument, NULL, | |
797 | option_no_workaround_close_loop_end }, | |
798 | { "workaround-close-loop-end", no_argument, NULL, | |
799 | option_workaround_close_loop_end }, | |
e0001a05 | 800 | |
7fa3d080 | 801 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 802 | |
43cd72b9 BW |
803 | { "link-relax", no_argument, NULL, option_link_relax }, |
804 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
805 | ||
806 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
807 | ||
a82c7d90 DW |
808 | { "trampolines", no_argument, NULL, option_trampolines }, |
809 | { "no-trampolines", no_argument, NULL, option_no_trampolines }, | |
810 | ||
b46824bd MF |
811 | { "auto-litpools", no_argument, NULL, option_auto_litpools }, |
812 | { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, | |
813 | { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, | |
814 | ||
8255c61b MF |
815 | { "separate-prop-tables", no_argument, NULL, option_separate_props }, |
816 | ||
7a77f1ac MF |
817 | { "abi-windowed", no_argument, NULL, option_abi_windowed }, |
818 | { "abi-call0", no_argument, NULL, option_abi_call0 }, | |
819 | ||
43cd72b9 | 820 | { NULL, no_argument, NULL, 0 } |
e0001a05 NC |
821 | }; |
822 | ||
823 | size_t md_longopts_size = sizeof md_longopts; | |
824 | ||
825 | ||
826 | int | |
17b9d67d | 827 | md_parse_option (int c, const char *arg) |
e0001a05 NC |
828 | { |
829 | switch (c) | |
830 | { | |
831 | case option_density: | |
43cd72b9 | 832 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
833 | return 1; |
834 | case option_no_density: | |
43cd72b9 | 835 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 836 | return 1; |
43cd72b9 | 837 | case option_link_relax: |
5b7c81bd | 838 | opt_linkrelax = true; |
e0001a05 | 839 | return 1; |
43cd72b9 | 840 | case option_no_link_relax: |
5b7c81bd | 841 | opt_linkrelax = false; |
e0001a05 | 842 | return 1; |
19fc3723 SA |
843 | case option_flix: |
844 | produce_flix = FLIX_ALL; | |
845 | return 1; | |
846 | case option_no_generate_flix: | |
847 | produce_flix = FLIX_NO_GENERATE; | |
848 | return 1; | |
849 | case option_no_flix: | |
850 | produce_flix = FLIX_NONE; | |
851 | return 1; | |
43cd72b9 BW |
852 | case option_generics: |
853 | as_warn (_("--generics is deprecated; use --transform instead")); | |
854 | return md_parse_option (option_transform, arg); | |
855 | case option_no_generics: | |
856 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
857 | return md_parse_option (option_no_transform, arg); | |
858 | case option_relax: | |
859 | as_warn (_("--relax is deprecated; use --transform instead")); | |
860 | return md_parse_option (option_transform, arg); | |
861 | case option_no_relax: | |
862 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
863 | return md_parse_option (option_no_transform, arg); | |
e0001a05 | 864 | case option_longcalls: |
5b7c81bd | 865 | directive_state[directive_longcalls] = true; |
e0001a05 NC |
866 | return 1; |
867 | case option_no_longcalls: | |
5b7c81bd | 868 | directive_state[directive_longcalls] = false; |
e0001a05 NC |
869 | return 1; |
870 | case option_text_section_literals: | |
5b7c81bd | 871 | use_literal_section = false; |
e0001a05 NC |
872 | return 1; |
873 | case option_no_text_section_literals: | |
5b7c81bd | 874 | use_literal_section = true; |
e0001a05 | 875 | return 1; |
43cd72b9 BW |
876 | case option_absolute_literals: |
877 | if (!absolute_literals_supported) | |
878 | { | |
879 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
880 | return 0; | |
881 | } | |
5b7c81bd | 882 | directive_state[directive_absolute_literals] = true; |
43cd72b9 BW |
883 | return 1; |
884 | case option_no_absolute_literals: | |
5b7c81bd | 885 | directive_state[directive_absolute_literals] = false; |
43cd72b9 BW |
886 | return 1; |
887 | ||
e0001a05 | 888 | case option_workaround_a0_b_retw: |
5b7c81bd | 889 | workaround_a0_b_retw = true; |
e0001a05 NC |
890 | return 1; |
891 | case option_no_workaround_a0_b_retw: | |
5b7c81bd | 892 | workaround_a0_b_retw = false; |
e0001a05 NC |
893 | return 1; |
894 | case option_workaround_b_j_loop_end: | |
5b7c81bd | 895 | workaround_b_j_loop_end = true; |
e0001a05 NC |
896 | return 1; |
897 | case option_no_workaround_b_j_loop_end: | |
5b7c81bd | 898 | workaround_b_j_loop_end = false; |
e0001a05 NC |
899 | return 1; |
900 | ||
901 | case option_workaround_short_loop: | |
5b7c81bd | 902 | workaround_short_loop = true; |
e0001a05 NC |
903 | return 1; |
904 | case option_no_workaround_short_loop: | |
5b7c81bd | 905 | workaround_short_loop = false; |
e0001a05 NC |
906 | return 1; |
907 | ||
908 | case option_workaround_all_short_loops: | |
5b7c81bd | 909 | workaround_all_short_loops = true; |
e0001a05 NC |
910 | return 1; |
911 | case option_no_workaround_all_short_loops: | |
5b7c81bd | 912 | workaround_all_short_loops = false; |
e0001a05 NC |
913 | return 1; |
914 | ||
915 | case option_workaround_close_loop_end: | |
5b7c81bd | 916 | workaround_close_loop_end = true; |
e0001a05 NC |
917 | return 1; |
918 | case option_no_workaround_close_loop_end: | |
5b7c81bd | 919 | workaround_close_loop_end = false; |
e0001a05 NC |
920 | return 1; |
921 | ||
922 | case option_no_workarounds: | |
5b7c81bd AM |
923 | workaround_a0_b_retw = false; |
924 | workaround_b_j_loop_end = false; | |
925 | workaround_short_loop = false; | |
926 | workaround_all_short_loops = false; | |
927 | workaround_close_loop_end = false; | |
e0001a05 | 928 | return 1; |
43cd72b9 | 929 | |
e0001a05 | 930 | case option_align_targets: |
5b7c81bd | 931 | align_targets = true; |
e0001a05 NC |
932 | return 1; |
933 | case option_no_align_targets: | |
5b7c81bd | 934 | align_targets = false; |
e0001a05 NC |
935 | return 1; |
936 | ||
43cd72b9 | 937 | case option_warn_unaligned_targets: |
5b7c81bd | 938 | warn_unaligned_branch_targets = true; |
e0001a05 NC |
939 | return 1; |
940 | ||
e0001a05 NC |
941 | case option_rename_section_name: |
942 | build_section_rename (arg); | |
943 | return 1; | |
e0001a05 NC |
944 | |
945 | case 'Q': | |
946 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
947 | should be emitted or not. FIXME: Not implemented. */ | |
948 | return 1; | |
c138bc38 | 949 | |
43cd72b9 BW |
950 | case option_prefer_l32r: |
951 | if (prefer_const16) | |
952 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
953 | prefer_l32r = 1; | |
954 | return 1; | |
955 | ||
956 | case option_prefer_const16: | |
957 | if (prefer_l32r) | |
958 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
959 | prefer_const16 = 1; | |
960 | return 1; | |
961 | ||
c138bc38 | 962 | case option_target_hardware: |
43cd72b9 BW |
963 | { |
964 | int earliest, latest = 0; | |
17b9d67d | 965 | char *end; |
43cd72b9 BW |
966 | if (*arg == 0 || *arg == '-') |
967 | as_fatal (_("invalid target hardware version")); | |
968 | ||
17b9d67d | 969 | earliest = strtol (arg, &end, 0); |
43cd72b9 | 970 | |
17b9d67d | 971 | if (*end == 0) |
43cd72b9 | 972 | latest = earliest; |
17b9d67d | 973 | else if (*end == '-') |
43cd72b9 | 974 | { |
17b9d67d | 975 | if (*++end == 0) |
43cd72b9 | 976 | as_fatal (_("invalid target hardware version")); |
17b9d67d | 977 | latest = strtol (end, &end, 0); |
43cd72b9 | 978 | } |
17b9d67d | 979 | if (*end != 0) |
43cd72b9 BW |
980 | as_fatal (_("invalid target hardware version")); |
981 | ||
982 | xtensa_setup_hw_workarounds (earliest, latest); | |
983 | return 1; | |
984 | } | |
985 | ||
986 | case option_transform: | |
987 | /* This option has no affect other than to use the defaults, | |
988 | which are already set. */ | |
989 | return 1; | |
990 | ||
991 | case option_no_transform: | |
992 | /* This option turns off all transformations of any kind. | |
993 | However, because we want to preserve the state of other | |
994 | directives, we only change its own field. Thus, before | |
995 | you perform any transformation, always check if transform | |
996 | is available. If you use the functions we provide for this | |
997 | purpose, you will be ok. */ | |
5b7c81bd | 998 | directive_state[directive_transform] = false; |
43cd72b9 BW |
999 | return 1; |
1000 | ||
a82c7d90 | 1001 | case option_trampolines: |
5b7c81bd | 1002 | use_trampolines = true; |
a82c7d90 DW |
1003 | return 1; |
1004 | ||
1005 | case option_no_trampolines: | |
5b7c81bd | 1006 | use_trampolines = false; |
a82c7d90 DW |
1007 | return 1; |
1008 | ||
b46824bd | 1009 | case option_auto_litpools: |
5b7c81bd AM |
1010 | auto_litpools = true; |
1011 | use_literal_section = false; | |
cd665a94 MF |
1012 | if (auto_litpool_limit <= 0) |
1013 | auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2; | |
b46824bd MF |
1014 | return 1; |
1015 | ||
1016 | case option_no_auto_litpools: | |
5b7c81bd | 1017 | auto_litpools = false; |
b46824bd MF |
1018 | auto_litpool_limit = -1; |
1019 | return 1; | |
1020 | ||
1021 | case option_auto_litpool_limit: | |
1022 | { | |
1023 | int value = 0; | |
17b9d67d | 1024 | char *end; |
b46824bd MF |
1025 | if (auto_litpool_limit < 0) |
1026 | as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); | |
1027 | if (*arg == 0 || *arg == '-') | |
1028 | as_fatal (_("invalid auto-litpool-limit argument")); | |
17b9d67d TS |
1029 | value = strtol (arg, &end, 10); |
1030 | if (*end != 0) | |
b46824bd MF |
1031 | as_fatal (_("invalid auto-litpool-limit argument")); |
1032 | if (value < 100 || value > 10000) | |
1033 | as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); | |
1034 | auto_litpool_limit = value; | |
5b7c81bd AM |
1035 | auto_litpools = true; |
1036 | use_literal_section = false; | |
b46824bd MF |
1037 | return 1; |
1038 | } | |
1039 | ||
8255c61b | 1040 | case option_separate_props: |
5b7c81bd | 1041 | elf32xtensa_separate_props = true; |
8255c61b MF |
1042 | return 1; |
1043 | ||
1044 | case option_no_separate_props: | |
5b7c81bd | 1045 | elf32xtensa_separate_props = false; |
8255c61b MF |
1046 | return 1; |
1047 | ||
7a77f1ac MF |
1048 | case option_abi_windowed: |
1049 | elf32xtensa_abi = XTHAL_ABI_WINDOWED; | |
1050 | return 1; | |
1051 | ||
1052 | case option_abi_call0: | |
1053 | elf32xtensa_abi = XTHAL_ABI_CALL0; | |
1054 | return 1; | |
1055 | ||
e0001a05 NC |
1056 | default: |
1057 | return 0; | |
1058 | } | |
1059 | } | |
1060 | ||
1061 | ||
1062 | void | |
7fa3d080 | 1063 | md_show_usage (FILE *stream) |
e0001a05 | 1064 | { |
43cd72b9 BW |
1065 | fputs ("\n\ |
1066 | Xtensa options:\n\ | |
9456465c BW |
1067 | --[no-]text-section-literals\n\ |
1068 | [Do not] put literals in the text section\n\ | |
1069 | --[no-]absolute-literals\n\ | |
1070 | [Do not] default to use non-PC-relative literals\n\ | |
1071 | --[no-]target-align [Do not] try to align branch targets\n\ | |
1072 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
1073 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
1074 | --flix both allow hand-written and generate flix bundles\n\ |
1075 | --no-generate-flix allow hand-written but do not generate\n\ | |
1076 | flix bundles\n\ | |
1077 | --no-allow-flix neither allow hand-written nor generate\n\ | |
1078 | flix bundles\n\ | |
a82c7d90 DW |
1079 | --rename-section old=new Rename section 'old' to 'new'\n\ |
1080 | --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ | |
b46824bd MF |
1081 | when jumps do not reach their targets\n\ |
1082 | --[no-]auto-litpools [Do not] automatically create literal pools\n\ | |
1083 | --auto-litpool-limit=<value>\n\ | |
1084 | (range 100-10000) Maximum number of blocks of\n\ | |
1085 | instructions to emit between literal pool\n\ | |
8255c61b MF |
1086 | locations; implies --auto-litpools flag\n\ |
1087 | --[no-]separate-prop-tables\n\ | |
1088 | [Do not] place Xtensa property records into\n\ | |
1089 | individual property sections for each section.\n\ | |
1090 | Default is to generate single property section.\n", stream); | |
e0001a05 NC |
1091 | } |
1092 | ||
7fa3d080 BW |
1093 | \f |
1094 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
1095 | |
1096 | static void | |
7fa3d080 | 1097 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 1098 | { |
7fa3d080 | 1099 | sym_list *l; |
43cd72b9 | 1100 | |
7fa3d080 | 1101 | if (!free_insn_labels) |
325801bd | 1102 | l = XNEW (sym_list); |
7fa3d080 | 1103 | else |
43cd72b9 | 1104 | { |
7fa3d080 BW |
1105 | l = free_insn_labels; |
1106 | free_insn_labels = l->next; | |
1107 | } | |
1108 | ||
1109 | l->sym = sym; | |
1110 | l->next = insn_labels; | |
1111 | insn_labels = l; | |
1112 | } | |
1113 | ||
1114 | ||
1115 | static void | |
1116 | xtensa_clear_insn_labels (void) | |
1117 | { | |
1118 | sym_list **pl; | |
1119 | ||
1120 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1121 | ; | |
1122 | *pl = insn_labels; | |
1123 | insn_labels = NULL; | |
1124 | } | |
1125 | ||
1126 | ||
7fa3d080 | 1127 | static void |
c3ea6048 | 1128 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1129 | { |
1130 | sym_list *lit; | |
1131 | ||
1132 | for (lit = insn_labels; lit; lit = lit->next) | |
1133 | { | |
1134 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1135 | S_SET_VALUE (lit_sym, new_offset); |
1136 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1137 | } |
1138 | } | |
1139 | ||
e0001a05 NC |
1140 | \f |
1141 | /* Directive data and functions. */ | |
1142 | ||
1143 | typedef struct state_stackS_struct | |
1144 | { | |
1145 | directiveE directive; | |
5b7c81bd AM |
1146 | bool negated; |
1147 | bool old_state; | |
e0001a05 NC |
1148 | const char *file; |
1149 | unsigned int line; | |
1150 | const void *datum; | |
1151 | struct state_stackS_struct *prev; | |
1152 | } state_stackS; | |
1153 | ||
1154 | state_stackS *directive_state_stack; | |
1155 | ||
1156 | const pseudo_typeS md_pseudo_table[] = | |
1157 | { | |
43cd72b9 BW |
1158 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1159 | { "literal_position", xtensa_literal_position, 0 }, | |
1160 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1161 | { "long", xtensa_elf_cons, 4 }, | |
1162 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1163 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1164 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1165 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1166 | { "sleb128", xtensa_leb128, 1}, |
1167 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1168 | { "begin", xtensa_begin_directive, 0 }, |
1169 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1170 | { "literal", xtensa_literal_pseudo, 0 }, |
1171 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1172 | { NULL, 0, 0 }, | |
e0001a05 NC |
1173 | }; |
1174 | ||
1175 | ||
5b7c81bd | 1176 | static bool |
7fa3d080 | 1177 | use_transform (void) |
e0001a05 | 1178 | { |
ed2917de | 1179 | /* After md_finish, you should be checking frag by frag, rather |
43cd72b9 | 1180 | than state directives. */ |
ed2917de | 1181 | gas_assert (!past_xtensa_md_finish); |
43cd72b9 | 1182 | return directive_state[directive_transform]; |
e0001a05 NC |
1183 | } |
1184 | ||
1185 | ||
5b7c81bd | 1186 | static bool |
7fa3d080 | 1187 | do_align_targets (void) |
e0001a05 | 1188 | { |
ed2917de | 1189 | /* Do not use this function after md_finish; just look at align_targets |
7b1cc377 BW |
1190 | instead. There is no target-align directive, so alignment is either |
1191 | enabled for all frags or not done at all. */ | |
ed2917de | 1192 | gas_assert (!past_xtensa_md_finish); |
43cd72b9 | 1193 | return align_targets && use_transform (); |
e0001a05 NC |
1194 | } |
1195 | ||
1196 | ||
1197 | static void | |
5b7c81bd | 1198 | directive_push (directiveE directive, bool negated, const void *datum) |
e0001a05 | 1199 | { |
3b4dbbbf | 1200 | const char *file; |
e0001a05 | 1201 | unsigned int line; |
325801bd | 1202 | state_stackS *stack = XNEW (state_stackS); |
e0001a05 | 1203 | |
3b4dbbbf | 1204 | file = as_where (&line); |
e0001a05 NC |
1205 | |
1206 | stack->directive = directive; | |
1207 | stack->negated = negated; | |
1208 | stack->old_state = directive_state[directive]; | |
1209 | stack->file = file; | |
1210 | stack->line = line; | |
1211 | stack->datum = datum; | |
1212 | stack->prev = directive_state_stack; | |
1213 | directive_state_stack = stack; | |
1214 | ||
1215 | directive_state[directive] = !negated; | |
1216 | } | |
1217 | ||
7fa3d080 | 1218 | |
e0001a05 | 1219 | static void |
7fa3d080 | 1220 | directive_pop (directiveE *directive, |
5b7c81bd | 1221 | bool *negated, |
7fa3d080 BW |
1222 | const char **file, |
1223 | unsigned int *line, | |
1224 | const void **datum) | |
e0001a05 NC |
1225 | { |
1226 | state_stackS *top = directive_state_stack; | |
1227 | ||
1228 | if (!directive_state_stack) | |
1229 | { | |
33eaf5de | 1230 | as_bad (_("unmatched .end directive")); |
e0001a05 NC |
1231 | *directive = directive_none; |
1232 | return; | |
1233 | } | |
1234 | ||
1235 | directive_state[directive_state_stack->directive] = top->old_state; | |
1236 | *directive = top->directive; | |
1237 | *negated = top->negated; | |
1238 | *file = top->file; | |
1239 | *line = top->line; | |
1240 | *datum = top->datum; | |
1241 | directive_state_stack = top->prev; | |
1242 | free (top); | |
1243 | } | |
1244 | ||
1245 | ||
1246 | static void | |
7fa3d080 | 1247 | directive_balance (void) |
e0001a05 NC |
1248 | { |
1249 | while (directive_state_stack) | |
1250 | { | |
1251 | directiveE directive; | |
5b7c81bd | 1252 | bool negated; |
e0001a05 NC |
1253 | const char *file; |
1254 | unsigned int line; | |
1255 | const void *datum; | |
1256 | ||
1257 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1258 | as_warn_where ((char *) file, line, | |
1259 | _(".begin directive with no matching .end directive")); | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | ||
5b7c81bd | 1264 | static bool |
7fa3d080 | 1265 | inside_directive (directiveE dir) |
e0001a05 NC |
1266 | { |
1267 | state_stackS *top = directive_state_stack; | |
1268 | ||
1269 | while (top && top->directive != dir) | |
1270 | top = top->prev; | |
1271 | ||
1272 | return (top != NULL); | |
1273 | } | |
1274 | ||
1275 | ||
1276 | static void | |
5b7c81bd | 1277 | get_directive (directiveE *directive, bool *negated) |
e0001a05 NC |
1278 | { |
1279 | int len; | |
1280 | unsigned i; | |
b9bb4a93 | 1281 | const char *directive_string; |
e0001a05 | 1282 | |
d34049e8 | 1283 | if (!startswith (input_line_pointer, "no-")) |
5b7c81bd | 1284 | *negated = false; |
e0001a05 NC |
1285 | else |
1286 | { | |
5b7c81bd | 1287 | *negated = true; |
e0001a05 NC |
1288 | input_line_pointer += 3; |
1289 | } | |
1290 | ||
1291 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1292 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1293 | ||
1294 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1295 | equivalent to .begin [no-]transform. We should remove it when | |
1296 | we stop accepting those options. */ | |
c138bc38 | 1297 | |
d34049e8 | 1298 | if (startswith (input_line_pointer, "generics")) |
43cd72b9 BW |
1299 | { |
1300 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1301 | directive_string = "transform"; | |
1302 | } | |
d34049e8 | 1303 | else if (startswith (input_line_pointer, "relax")) |
43cd72b9 BW |
1304 | { |
1305 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1306 | directive_string = "transform"; | |
c138bc38 | 1307 | } |
43cd72b9 BW |
1308 | else |
1309 | directive_string = input_line_pointer; | |
e0001a05 NC |
1310 | |
1311 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1312 | { | |
43cd72b9 | 1313 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1314 | { |
1315 | input_line_pointer += len; | |
1316 | *directive = (directiveE) i; | |
1317 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1318 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1319 | directive_info[i].name); |
1320 | return; | |
1321 | } | |
1322 | } | |
1323 | ||
1324 | as_bad (_("unknown directive")); | |
1325 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1326 | } | |
1327 | ||
1328 | ||
1329 | static void | |
7fa3d080 | 1330 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1331 | { |
1332 | directiveE directive; | |
5b7c81bd | 1333 | bool negated; |
e0001a05 | 1334 | emit_state *state; |
e0001a05 NC |
1335 | lit_state *ls; |
1336 | ||
1337 | get_directive (&directive, &negated); | |
1338 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1339 | { | |
1340 | discard_rest_of_line (); | |
1341 | return; | |
1342 | } | |
1343 | ||
43cd72b9 BW |
1344 | if (cur_vinsn.inside_bundle) |
1345 | as_bad (_("directives are not valid inside bundles")); | |
1346 | ||
e0001a05 NC |
1347 | switch (directive) |
1348 | { | |
1349 | case directive_literal: | |
82e7541d BW |
1350 | if (!inside_directive (directive_literal)) |
1351 | { | |
1352 | /* Previous labels go with whatever follows this directive, not with | |
1353 | the literal, so save them now. */ | |
1354 | saved_insn_labels = insn_labels; | |
1355 | insn_labels = NULL; | |
1356 | } | |
43cd72b9 | 1357 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
325801bd | 1358 | state = XNEW (emit_state); |
e0001a05 NC |
1359 | xtensa_switch_to_literal_fragment (state); |
1360 | directive_push (directive_literal, negated, state); | |
1361 | break; | |
1362 | ||
1363 | case directive_literal_prefix: | |
c138bc38 | 1364 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1365 | might produce a literal. */ |
1366 | md_flush_pending_output (); | |
e0001a05 NC |
1367 | /* Check to see if the current fragment is a literal |
1368 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1369 | if (generating_literals) |
e0001a05 NC |
1370 | { |
1371 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1372 | return; | |
1373 | } | |
1374 | ||
1375 | /* Allocate the literal state for this section and push | |
1376 | onto the directive stack. */ | |
325801bd | 1377 | ls = XNEW (lit_state); |
9c2799c2 | 1378 | gas_assert (ls); |
e0001a05 NC |
1379 | |
1380 | *ls = default_lit_sections; | |
e0001a05 NC |
1381 | directive_push (directive_literal_prefix, negated, ls); |
1382 | ||
e0001a05 | 1383 | /* Process the new prefix. */ |
74869ac7 | 1384 | xtensa_literal_prefix (); |
e0001a05 NC |
1385 | break; |
1386 | ||
1387 | case directive_freeregs: | |
1388 | /* This information is currently unused, but we'll accept the statement | |
1389 | and just discard the rest of the line. This won't check the syntax, | |
1390 | but it will accept every correct freeregs directive. */ | |
1391 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1392 | directive_push (directive_freeregs, negated, 0); | |
1393 | break; | |
1394 | ||
43cd72b9 BW |
1395 | case directive_schedule: |
1396 | md_flush_pending_output (); | |
1397 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1398 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1399 | directive_push (directive_schedule, negated, 0); | |
1400 | xtensa_set_frag_assembly_state (frag_now); | |
1401 | break; | |
1402 | ||
e0001a05 | 1403 | case directive_density: |
43cd72b9 BW |
1404 | as_warn (_(".begin [no-]density is ignored")); |
1405 | break; | |
1406 | ||
1407 | case directive_absolute_literals: | |
1408 | md_flush_pending_output (); | |
1409 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1410 | { |
43cd72b9 | 1411 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1412 | break; |
1413 | } | |
43cd72b9 BW |
1414 | xtensa_set_frag_assembly_state (frag_now); |
1415 | directive_push (directive, negated, 0); | |
1416 | break; | |
e0001a05 NC |
1417 | |
1418 | default: | |
43cd72b9 BW |
1419 | md_flush_pending_output (); |
1420 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1421 | directive_push (directive, negated, 0); |
1422 | break; | |
1423 | } | |
1424 | ||
1425 | demand_empty_rest_of_line (); | |
1426 | } | |
1427 | ||
1428 | ||
1429 | static void | |
7fa3d080 | 1430 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1431 | { |
1432 | directiveE begin_directive, end_directive; | |
5b7c81bd | 1433 | bool begin_negated, end_negated; |
e0001a05 NC |
1434 | const char *file; |
1435 | unsigned int line; | |
1436 | emit_state *state; | |
43cd72b9 | 1437 | emit_state **state_ptr; |
e0001a05 NC |
1438 | lit_state *s; |
1439 | ||
43cd72b9 BW |
1440 | if (cur_vinsn.inside_bundle) |
1441 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1442 | |
e0001a05 | 1443 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1444 | |
1445 | md_flush_pending_output (); | |
1446 | ||
87975d2a | 1447 | switch ((int) end_directive) |
e0001a05 | 1448 | { |
87975d2a | 1449 | case XTENSA_UNDEFINED: |
e0001a05 NC |
1450 | discard_rest_of_line (); |
1451 | return; | |
e0001a05 | 1452 | |
87975d2a | 1453 | case (int) directive_density: |
43cd72b9 | 1454 | as_warn (_(".end [no-]density is ignored")); |
e0001a05 | 1455 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1456 | break; |
1457 | ||
87975d2a | 1458 | case (int) directive_absolute_literals: |
43cd72b9 BW |
1459 | if (!absolute_literals_supported && !end_negated) |
1460 | { | |
1461 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1462 | demand_empty_rest_of_line (); | |
1463 | return; | |
1464 | } | |
1465 | break; | |
1466 | ||
1467 | default: | |
1468 | break; | |
e0001a05 NC |
1469 | } |
1470 | ||
43cd72b9 | 1471 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1472 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1473 | (const void **) state_ptr); |
e0001a05 NC |
1474 | |
1475 | if (begin_directive != directive_none) | |
1476 | { | |
1477 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1478 | { | |
1479 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1480 | begin_negated ? "no-" : "", | |
1481 | directive_info[begin_directive].name, file, line); | |
1482 | } | |
1483 | else | |
1484 | { | |
1485 | switch (end_directive) | |
1486 | { | |
1487 | case directive_literal: | |
1488 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1489 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1490 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1491 | free (state); |
82e7541d BW |
1492 | if (!inside_directive (directive_literal)) |
1493 | { | |
1494 | /* Restore the list of current labels. */ | |
1495 | xtensa_clear_insn_labels (); | |
1496 | insn_labels = saved_insn_labels; | |
1497 | } | |
e0001a05 NC |
1498 | break; |
1499 | ||
e0001a05 NC |
1500 | case directive_literal_prefix: |
1501 | /* Restore the default collection sections from saved state. */ | |
1502 | s = (lit_state *) state; | |
9c2799c2 | 1503 | gas_assert (s); |
e8247da7 | 1504 | default_lit_sections = *s; |
e0001a05 | 1505 | |
74869ac7 BW |
1506 | /* Free the state storage. */ |
1507 | free (s->lit_prefix); | |
e0001a05 NC |
1508 | free (s); |
1509 | break; | |
1510 | ||
43cd72b9 BW |
1511 | case directive_schedule: |
1512 | case directive_freeregs: | |
1513 | break; | |
1514 | ||
e0001a05 | 1515 | default: |
43cd72b9 | 1516 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1517 | break; |
1518 | } | |
1519 | } | |
1520 | } | |
1521 | ||
1522 | demand_empty_rest_of_line (); | |
1523 | } | |
1524 | ||
1525 | ||
1526 | /* Place an aligned literal fragment at the current location. */ | |
1527 | ||
1528 | static void | |
7fa3d080 | 1529 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1530 | { |
43cd72b9 BW |
1531 | md_flush_pending_output (); |
1532 | ||
e0001a05 NC |
1533 | if (inside_directive (directive_literal)) |
1534 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1535 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1536 | |
1537 | demand_empty_rest_of_line (); | |
82e7541d | 1538 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1539 | } |
1540 | ||
1541 | ||
43cd72b9 | 1542 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1543 | |
1544 | static void | |
7fa3d080 | 1545 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1546 | { |
1547 | emit_state state; | |
1745fcba | 1548 | char *p, *base_name; |
e0001a05 | 1549 | char c; |
e0001a05 | 1550 | |
82e7541d BW |
1551 | if (inside_directive (directive_literal)) |
1552 | { | |
1553 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1554 | ignore_rest_of_line (); | |
1555 | return; | |
1556 | } | |
1557 | ||
43cd72b9 BW |
1558 | md_flush_pending_output (); |
1559 | ||
82e7541d BW |
1560 | /* Previous labels go with whatever follows this directive, not with |
1561 | the literal, so save them now. */ | |
1562 | saved_insn_labels = insn_labels; | |
1563 | insn_labels = NULL; | |
1564 | ||
e0001a05 NC |
1565 | base_name = input_line_pointer; |
1566 | ||
1567 | xtensa_switch_to_literal_fragment (&state); | |
1568 | ||
43cd72b9 BW |
1569 | /* All literals are aligned to four-byte boundaries. */ |
1570 | frag_align (2, 0, 0); | |
1571 | record_alignment (now_seg, 2); | |
e0001a05 | 1572 | |
d02603dc | 1573 | c = get_symbol_name (&base_name); |
e0001a05 NC |
1574 | /* Just after name is now '\0'. */ |
1575 | p = input_line_pointer; | |
1576 | *p = c; | |
d02603dc | 1577 | SKIP_WHITESPACE_AFTER_NAME (); |
e0001a05 NC |
1578 | |
1579 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1580 | { | |
1581 | as_bad (_("expected comma or colon after symbol name; " | |
1582 | "rest of line ignored")); | |
1583 | ignore_rest_of_line (); | |
1584 | xtensa_restore_emit_state (&state); | |
1585 | return; | |
1586 | } | |
e0001a05 | 1587 | |
d02603dc | 1588 | *p = 0; |
e0001a05 | 1589 | colon (base_name); |
e0001a05 | 1590 | *p = c; |
d02603dc | 1591 | |
43cd72b9 | 1592 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1593 | |
43cd72b9 | 1594 | xtensa_elf_cons (4); |
e0001a05 NC |
1595 | |
1596 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1597 | |
1598 | /* Restore the list of current labels. */ | |
1599 | xtensa_clear_insn_labels (); | |
1600 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1601 | } |
1602 | ||
1603 | ||
1604 | static void | |
74869ac7 | 1605 | xtensa_literal_prefix (void) |
e0001a05 | 1606 | { |
74869ac7 BW |
1607 | char *name; |
1608 | int len; | |
1609 | ||
1610 | /* Parse the new prefix from the input_line_pointer. */ | |
1611 | SKIP_WHITESPACE (); | |
1612 | len = strspn (input_line_pointer, | |
1613 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1614 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1615 | |
1616 | /* Get a null-terminated copy of the name. */ | |
29a2809e | 1617 | name = xmemdup0 (input_line_pointer, len); |
e0001a05 | 1618 | |
74869ac7 BW |
1619 | /* Skip the name in the input line. */ |
1620 | input_line_pointer += len; | |
43cd72b9 | 1621 | |
74869ac7 | 1622 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1623 | |
74869ac7 | 1624 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1625 | default_lit_sections.lit_seg = NULL; |
1626 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1627 | } |
1628 | ||
1629 | ||
1630 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1631 | ||
1632 | static void | |
7fa3d080 | 1633 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1634 | { |
1635 | float fall_through_f, target_f; | |
43cd72b9 BW |
1636 | |
1637 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1638 | if (fall_through_f < 0) | |
1639 | { | |
1640 | as_bad (_("fall through frequency must be greater than 0")); | |
1641 | ignore_rest_of_line (); | |
1642 | return; | |
1643 | } | |
1644 | ||
1645 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1646 | if (target_f < 0) | |
1647 | { | |
1648 | as_bad (_("branch target frequency must be greater than 0")); | |
1649 | ignore_rest_of_line (); | |
1650 | return; | |
1651 | } | |
1652 | ||
b08b5071 | 1653 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1654 | |
1655 | demand_empty_rest_of_line (); | |
1656 | } | |
1657 | ||
1658 | ||
1659 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1660 | Clobbers input_line_pointer, checks end-of-line. */ | |
1661 | ||
1662 | static void | |
7fa3d080 | 1663 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1664 | { |
1665 | expressionS exp; | |
1666 | bfd_reloc_code_real_type reloc; | |
1667 | ||
1668 | md_flush_pending_output (); | |
1669 | ||
1670 | if (cur_vinsn.inside_bundle) | |
1671 | as_bad (_("directives are not valid inside bundles")); | |
1672 | ||
1673 | if (is_it_end_of_statement ()) | |
1674 | { | |
1675 | demand_empty_rest_of_line (); | |
1676 | return; | |
1677 | } | |
1678 | ||
1679 | do | |
1680 | { | |
1681 | expression (&exp); | |
1682 | if (exp.X_op == O_symbol | |
1683 | && *input_line_pointer == '@' | |
1684 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1685 | != BFD_RELOC_NONE)) | |
1686 | { | |
1687 | reloc_howto_type *reloc_howto = | |
1688 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1689 | ||
1690 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1691 | as_bad (_("unsupported relocation")); | |
1692 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1693 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1694 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1695 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1696 | as_bad (_("opcode-specific %s relocation used outside " | |
1697 | "an instruction"), reloc_howto->name); | |
1698 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
992a06ee AM |
1699 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
1700 | "%s relocations do not fit in %d bytes", | |
1701 | nbytes), | |
43cd72b9 | 1702 | reloc_howto->name, nbytes); |
28dbbc02 BW |
1703 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1704 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1705 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1706 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1707 | else |
1708 | { | |
1709 | char *p = frag_more ((int) nbytes); | |
1710 | xtensa_set_frag_assembly_state (frag_now); | |
1711 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1712 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1713 | } |
1714 | } | |
1715 | else | |
1f7efbae BW |
1716 | { |
1717 | xtensa_set_frag_assembly_state (frag_now); | |
1718 | emit_expr (&exp, (unsigned int) nbytes); | |
1719 | } | |
43cd72b9 BW |
1720 | } |
1721 | while (*input_line_pointer++ == ','); | |
1722 | ||
1723 | input_line_pointer--; /* Put terminator back into stream. */ | |
1724 | demand_empty_rest_of_line (); | |
1725 | } | |
1726 | ||
5b7c81bd | 1727 | static bool is_leb128_expr; |
fb227da0 BW |
1728 | |
1729 | static void | |
1730 | xtensa_leb128 (int sign) | |
1731 | { | |
5b7c81bd | 1732 | is_leb128_expr = true; |
fb227da0 | 1733 | s_leb128 (sign); |
5b7c81bd | 1734 | is_leb128_expr = false; |
fb227da0 BW |
1735 | } |
1736 | ||
7fa3d080 BW |
1737 | \f |
1738 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1739 | |
1740 | /* Parse @plt, etc. and return the desired relocation. */ | |
1741 | static bfd_reloc_code_real_type | |
7fa3d080 | 1742 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1743 | { |
43cd72b9 BW |
1744 | char ident[20]; |
1745 | char *str = *str_p; | |
1746 | char *str2; | |
1747 | int ch; | |
1748 | int len; | |
e066bf5f | 1749 | unsigned int i; |
43cd72b9 BW |
1750 | |
1751 | if (*str++ != '@') | |
1752 | return BFD_RELOC_NONE; | |
1753 | ||
1754 | for (ch = *str, str2 = ident; | |
1755 | (str2 < ident + sizeof (ident) - 1 | |
1756 | && (ISALNUM (ch) || ch == '@')); | |
1757 | ch = *++str) | |
1758 | { | |
1759 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1760 | } | |
1761 | ||
1762 | *str2 = '\0'; | |
1763 | len = str2 - ident; | |
1764 | ||
1765 | ch = ident[0]; | |
e066bf5f TS |
1766 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
1767 | if (ch == suffix_relocs[i].suffix[0] | |
1768 | && len == suffix_relocs[i].length | |
1769 | && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) | |
43cd72b9 BW |
1770 | { |
1771 | /* Now check for "identifier@suffix+constant". */ | |
1772 | if (*str == '-' || *str == '+') | |
1773 | { | |
1774 | char *orig_line = input_line_pointer; | |
1775 | expressionS new_exp; | |
1776 | ||
1777 | input_line_pointer = str; | |
1778 | expression (&new_exp); | |
1779 | if (new_exp.X_op == O_constant) | |
1780 | { | |
1781 | exp_p->X_add_number += new_exp.X_add_number; | |
1782 | str = input_line_pointer; | |
1783 | } | |
1784 | ||
1785 | if (&input_line_pointer != str_p) | |
1786 | input_line_pointer = orig_line; | |
1787 | } | |
1788 | ||
1789 | *str_p = str; | |
e066bf5f | 1790 | return suffix_relocs[i].reloc; |
43cd72b9 BW |
1791 | } |
1792 | ||
1793 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1794 | } |
1795 | ||
e0001a05 | 1796 | |
bbdd25a8 | 1797 | /* Find the matching operator type. */ |
cc34adb2 | 1798 | static operatorT |
bbdd25a8 BW |
1799 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) |
1800 | { | |
cc34adb2 | 1801 | operatorT operator = O_illegal; |
e066bf5f | 1802 | unsigned int i; |
3739860c | 1803 | |
e066bf5f | 1804 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1805 | { |
e066bf5f | 1806 | if (suffix_relocs[i].reloc == reloc) |
bbdd25a8 | 1807 | { |
e066bf5f | 1808 | operator = suffix_relocs[i].operator; |
bbdd25a8 BW |
1809 | break; |
1810 | } | |
1811 | } | |
cc34adb2 | 1812 | gas_assert (operator != O_illegal); |
bbdd25a8 BW |
1813 | return operator; |
1814 | } | |
1815 | ||
1816 | ||
1817 | /* Find the matching reloc type. */ | |
1818 | static bfd_reloc_code_real_type | |
5b7c81bd | 1819 | map_operator_to_reloc (unsigned char operator, bool is_literal) |
bbdd25a8 | 1820 | { |
e066bf5f | 1821 | unsigned int i; |
bbdd25a8 BW |
1822 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; |
1823 | ||
e066bf5f | 1824 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1825 | { |
e066bf5f | 1826 | if (suffix_relocs[i].operator == operator) |
bbdd25a8 | 1827 | { |
e066bf5f | 1828 | reloc = suffix_relocs[i].reloc; |
bbdd25a8 BW |
1829 | break; |
1830 | } | |
1831 | } | |
1832 | ||
28dbbc02 BW |
1833 | if (is_literal) |
1834 | { | |
1835 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1836 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1837 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1838 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1839 | } | |
1840 | ||
bbdd25a8 BW |
1841 | if (reloc == BFD_RELOC_UNUSED) |
1842 | return BFD_RELOC_32; | |
1843 | ||
1844 | return reloc; | |
1845 | } | |
1846 | ||
1847 | ||
e0001a05 | 1848 | static const char * |
7fa3d080 | 1849 | expression_end (const char *name) |
e0001a05 NC |
1850 | { |
1851 | while (1) | |
1852 | { | |
1853 | switch (*name) | |
1854 | { | |
43cd72b9 | 1855 | case '}': |
e0001a05 NC |
1856 | case ';': |
1857 | case '\0': | |
1858 | case ',': | |
43cd72b9 | 1859 | case ':': |
e0001a05 NC |
1860 | return name; |
1861 | case ' ': | |
1862 | case '\t': | |
1863 | ++name; | |
1864 | continue; | |
1865 | default: | |
1866 | return 0; | |
1867 | } | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | ||
1872 | #define ERROR_REG_NUM ((unsigned) -1) | |
1873 | ||
1874 | static unsigned | |
7fa3d080 | 1875 | tc_get_register (const char *prefix) |
e0001a05 NC |
1876 | { |
1877 | unsigned reg; | |
1878 | const char *next_expr; | |
1879 | const char *old_line_pointer; | |
1880 | ||
1881 | SKIP_WHITESPACE (); | |
1882 | old_line_pointer = input_line_pointer; | |
1883 | ||
1884 | if (*input_line_pointer == '$') | |
1885 | ++input_line_pointer; | |
1886 | ||
1887 | /* Accept "sp" as a synonym for "a1". */ | |
1888 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1889 | && expression_end (input_line_pointer + 2)) | |
1890 | { | |
1891 | input_line_pointer += 2; | |
1892 | return 1; /* AR[1] */ | |
1893 | } | |
1894 | ||
1895 | while (*input_line_pointer++ == *prefix++) | |
1896 | ; | |
1897 | --input_line_pointer; | |
1898 | --prefix; | |
1899 | ||
1900 | if (*prefix) | |
1901 | { | |
1902 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1903 | return ERROR_REG_NUM; | |
1904 | } | |
1905 | ||
1906 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1907 | { | |
1908 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1909 | return ERROR_REG_NUM; | |
1910 | } | |
1911 | ||
1912 | reg = 0; | |
1913 | ||
1914 | while (ISDIGIT ((int) *input_line_pointer)) | |
1915 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1916 | ||
1917 | if (!(next_expr = expression_end (input_line_pointer))) | |
1918 | { | |
1919 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1920 | return ERROR_REG_NUM; | |
1921 | } | |
1922 | ||
1923 | input_line_pointer = (char *) next_expr; | |
1924 | ||
1925 | return reg; | |
1926 | } | |
1927 | ||
1928 | ||
e0001a05 | 1929 | static void |
7fa3d080 | 1930 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1931 | { |
43cd72b9 | 1932 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1933 | |
43cd72b9 BW |
1934 | /* Check if this is an immediate operand. */ |
1935 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1936 | { |
43cd72b9 | 1937 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1938 | segT t = expression (tok); |
91d6fa6a | 1939 | |
43cd72b9 BW |
1940 | if (t == absolute_section |
1941 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1942 | { |
9c2799c2 | 1943 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1944 | tok->X_op = O_symbol; |
1945 | tok->X_add_symbol = &abs_symbol; | |
1946 | } | |
43cd72b9 BW |
1947 | |
1948 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1949 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1950 | != BFD_RELOC_NONE)) | |
e0001a05 | 1951 | { |
1bbb5f21 | 1952 | switch (reloc) |
43cd72b9 | 1953 | { |
1bbb5f21 BW |
1954 | case BFD_RELOC_LO16: |
1955 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1956 | { |
43cd72b9 | 1957 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1958 | return; |
1bbb5f21 BW |
1959 | } |
1960 | break; | |
1961 | case BFD_RELOC_HI16: | |
1962 | if (tok->X_op == O_constant) | |
1963 | { | |
43cd72b9 | 1964 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1965 | return; |
bbdd25a8 | 1966 | } |
1bbb5f21 BW |
1967 | break; |
1968 | case BFD_RELOC_UNUSED: | |
1969 | as_bad (_("unsupported relocation")); | |
1970 | return; | |
1971 | case BFD_RELOC_32_PCREL: | |
1972 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1973 | return; | |
1974 | default: | |
1975 | break; | |
43cd72b9 | 1976 | } |
bbdd25a8 | 1977 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1978 | } |
e0001a05 NC |
1979 | } |
1980 | else | |
1981 | { | |
43cd72b9 BW |
1982 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1983 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1984 | |
1985 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1986 | { | |
1987 | uint32 buf = reg; | |
43cd72b9 | 1988 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1989 | as_bad (_("register number out of range")); |
1990 | } | |
1991 | ||
1992 | tok->X_op = O_register; | |
1993 | tok->X_add_symbol = 0; | |
1994 | tok->X_add_number = reg; | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | ||
1999 | /* Split up the arguments for an opcode or pseudo-op. */ | |
2000 | ||
2001 | static int | |
7fa3d080 | 2002 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
2003 | { |
2004 | char *old_input_line_pointer; | |
5b7c81bd AM |
2005 | bool saw_comma = false; |
2006 | bool saw_arg = false; | |
2007 | bool saw_colon = false; | |
e0001a05 NC |
2008 | int num_args = 0; |
2009 | char *arg_end, *arg; | |
2010 | int arg_len; | |
43cd72b9 BW |
2011 | |
2012 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
2013 | old_input_line_pointer = input_line_pointer; |
2014 | input_line_pointer = str; | |
2015 | ||
2016 | while (*input_line_pointer) | |
2017 | { | |
2018 | SKIP_WHITESPACE (); | |
2019 | switch (*input_line_pointer) | |
2020 | { | |
2021 | case '\0': | |
43cd72b9 | 2022 | case '}': |
e0001a05 NC |
2023 | goto fini; |
2024 | ||
43cd72b9 BW |
2025 | case ':': |
2026 | input_line_pointer++; | |
2027 | if (saw_comma || saw_colon || !saw_arg) | |
2028 | goto err; | |
5b7c81bd | 2029 | saw_colon = true; |
43cd72b9 BW |
2030 | break; |
2031 | ||
e0001a05 NC |
2032 | case ',': |
2033 | input_line_pointer++; | |
43cd72b9 | 2034 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 | 2035 | goto err; |
5b7c81bd | 2036 | saw_comma = true; |
e0001a05 NC |
2037 | break; |
2038 | ||
2039 | default: | |
43cd72b9 | 2040 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
2041 | goto err; |
2042 | ||
2043 | arg_end = input_line_pointer + 1; | |
2044 | while (!expression_end (arg_end)) | |
2045 | arg_end += 1; | |
43cd72b9 | 2046 | |
e0001a05 | 2047 | arg_len = arg_end - input_line_pointer; |
325801bd | 2048 | arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
2049 | args[num_args] = arg; |
2050 | ||
43cd72b9 BW |
2051 | if (saw_colon) |
2052 | *arg++ = ':'; | |
e0001a05 NC |
2053 | strncpy (arg, input_line_pointer, arg_len); |
2054 | arg[arg_len] = '\0'; | |
43cd72b9 | 2055 | |
e0001a05 NC |
2056 | input_line_pointer = arg_end; |
2057 | num_args += 1; | |
5b7c81bd AM |
2058 | saw_comma = false; |
2059 | saw_colon = false; | |
2060 | saw_arg = true; | |
e0001a05 NC |
2061 | break; |
2062 | } | |
2063 | } | |
2064 | ||
dc1e8a47 | 2065 | fini: |
43cd72b9 | 2066 | if (saw_comma || saw_colon) |
e0001a05 NC |
2067 | goto err; |
2068 | input_line_pointer = old_input_line_pointer; | |
2069 | return num_args; | |
2070 | ||
dc1e8a47 | 2071 | err: |
43cd72b9 BW |
2072 | if (saw_comma) |
2073 | as_bad (_("extra comma")); | |
2074 | else if (saw_colon) | |
2075 | as_bad (_("extra colon")); | |
2076 | else if (!saw_arg) | |
c138bc38 | 2077 | as_bad (_("missing argument")); |
43cd72b9 BW |
2078 | else |
2079 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
2080 | input_line_pointer = old_input_line_pointer; |
2081 | return -1; | |
2082 | } | |
2083 | ||
2084 | ||
43cd72b9 | 2085 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 | 2086 | |
5b7c81bd | 2087 | static bool |
7fa3d080 | 2088 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 2089 | { |
43cd72b9 | 2090 | expressionS *tok, *last_tok; |
e0001a05 | 2091 | xtensa_opcode opcode = insn->opcode; |
5b7c81bd | 2092 | bool had_error = true; |
43cd72b9 BW |
2093 | xtensa_isa isa = xtensa_default_isa; |
2094 | int n, num_regs = 0; | |
e0001a05 | 2095 | int opcode_operand_count; |
43cd72b9 BW |
2096 | int opnd_cnt, last_opnd_cnt; |
2097 | unsigned int next_reg = 0; | |
e0001a05 NC |
2098 | char *old_input_line_pointer; |
2099 | ||
2100 | if (insn->insn_type == ITYPE_LITERAL) | |
2101 | opcode_operand_count = 1; | |
2102 | else | |
43cd72b9 | 2103 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 2104 | |
43cd72b9 | 2105 | tok = insn->tok; |
e0001a05 NC |
2106 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
2107 | ||
2108 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
2109 | old_input_line_pointer = input_line_pointer; |
2110 | ||
2111 | last_tok = 0; | |
2112 | last_opnd_cnt = -1; | |
2113 | opnd_cnt = 0; | |
2114 | ||
2115 | /* Skip invisible operands. */ | |
2116 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2117 | { | |
2118 | opnd_cnt += 1; | |
2119 | tok++; | |
2120 | } | |
e0001a05 NC |
2121 | |
2122 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2123 | { |
e0001a05 | 2124 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2125 | if (*input_line_pointer == ':') |
2126 | { | |
2127 | xtensa_regfile opnd_rf; | |
2128 | input_line_pointer++; | |
2129 | if (num_regs == 0) | |
2130 | goto err; | |
9c2799c2 | 2131 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2132 | num_regs--; |
2133 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2134 | if (next_reg | |
2135 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2136 | as_warn (_("incorrect register number, ignoring")); | |
2137 | next_reg++; | |
2138 | } | |
2139 | else | |
2140 | { | |
2141 | if (opnd_cnt >= opcode_operand_count) | |
2142 | { | |
2143 | as_warn (_("too many arguments")); | |
2144 | goto err; | |
2145 | } | |
9c2799c2 | 2146 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2147 | |
2148 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2149 | next_reg = tok->X_add_number + 1; | |
2150 | ||
2151 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2152 | goto err; | |
2153 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2154 | { | |
2155 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2156 | /* minus 1 because we are seeing one right now */ | |
2157 | } | |
2158 | else | |
2159 | num_regs = 0; | |
e0001a05 | 2160 | |
43cd72b9 BW |
2161 | last_tok = tok; |
2162 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2163 | demand_empty_rest_of_line (); |
e0001a05 | 2164 | |
43cd72b9 BW |
2165 | do |
2166 | { | |
2167 | opnd_cnt += 1; | |
2168 | tok++; | |
2169 | } | |
2170 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2171 | } | |
2172 | } | |
e0001a05 | 2173 | |
43cd72b9 BW |
2174 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2175 | goto err; | |
e0001a05 NC |
2176 | |
2177 | insn->ntok = tok - insn->tok; | |
5b7c81bd | 2178 | had_error = false; |
e0001a05 NC |
2179 | |
2180 | err: | |
43cd72b9 | 2181 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2182 | return had_error; |
2183 | } | |
2184 | ||
2185 | ||
43cd72b9 | 2186 | static int |
7fa3d080 | 2187 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2188 | { |
2189 | xtensa_isa isa = xtensa_default_isa; | |
2190 | static xtensa_insnbuf slotbuf = NULL; | |
2191 | xtensa_format fmt; | |
2192 | xtensa_opcode opc = insn->opcode; | |
2193 | int slot, opnd, fmt_found; | |
2194 | unsigned val; | |
2195 | ||
2196 | if (!slotbuf) | |
2197 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2198 | ||
2199 | /* Find format/slot where this can be encoded. */ | |
2200 | fmt_found = 0; | |
2201 | slot = 0; | |
2202 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2203 | { | |
2204 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2205 | { | |
2206 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2207 | { | |
2208 | fmt_found = 1; | |
2209 | break; | |
2210 | } | |
2211 | } | |
2212 | if (fmt_found) break; | |
2213 | } | |
2214 | ||
2215 | if (!fmt_found) | |
2216 | { | |
2217 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2218 | return -1; | |
2219 | } | |
2220 | ||
2221 | /* First encode all the visible operands | |
2222 | (to deal with shared field operands). */ | |
2223 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2224 | { | |
2225 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2226 | && (insn->tok[opnd].X_op == O_register | |
2227 | || insn->tok[opnd].X_op == O_constant)) | |
2228 | { | |
2229 | val = insn->tok[opnd].X_add_number; | |
2230 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2231 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2232 | } | |
2233 | } | |
2234 | ||
2235 | /* Then pull out the values for the invisible ones. */ | |
2236 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2237 | { | |
2238 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2239 | { | |
2240 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2241 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2242 | insn->tok[opnd].X_add_number = val; | |
2243 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2244 | insn->tok[opnd].X_op = O_register; | |
2245 | else | |
2246 | insn->tok[opnd].X_op = O_constant; | |
2247 | } | |
2248 | } | |
2249 | ||
2250 | return 0; | |
2251 | } | |
2252 | ||
2253 | ||
e0001a05 | 2254 | static void |
7fa3d080 | 2255 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2256 | { |
2257 | char *cnt_arg, *new_arg; | |
2258 | cnt_arg = *cnt_argp; | |
2259 | ||
2260 | /* replace the argument with "31-(argument)" */ | |
78fb7e37 | 2261 | new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); |
e0001a05 NC |
2262 | |
2263 | free (cnt_arg); | |
2264 | *cnt_argp = new_arg; | |
2265 | } | |
2266 | ||
2267 | ||
2268 | /* If "arg" is a constant expression, return non-zero with the value | |
2269 | in *valp. */ | |
2270 | ||
2271 | static int | |
7fa3d080 | 2272 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2273 | { |
2274 | expressionS exp; | |
2275 | char *save_ptr = input_line_pointer; | |
2276 | ||
2277 | input_line_pointer = arg; | |
2278 | expression (&exp); | |
2279 | input_line_pointer = save_ptr; | |
2280 | ||
2281 | if (exp.X_op == O_constant) | |
2282 | { | |
2283 | *valp = exp.X_add_number; | |
2284 | return 1; | |
2285 | } | |
2286 | ||
2287 | return 0; | |
2288 | } | |
2289 | ||
2290 | ||
2291 | static void | |
b9bb4a93 | 2292 | xg_replace_opname (char **popname, const char *newop) |
e0001a05 NC |
2293 | { |
2294 | free (*popname); | |
4ec9d7d5 | 2295 | *popname = xstrdup (newop); |
e0001a05 NC |
2296 | } |
2297 | ||
2298 | ||
2299 | static int | |
7fa3d080 BW |
2300 | xg_check_num_args (int *pnum_args, |
2301 | int expected_num, | |
2302 | char *opname, | |
2303 | char **arg_strings) | |
e0001a05 NC |
2304 | { |
2305 | int num_args = *pnum_args; | |
2306 | ||
43cd72b9 | 2307 | if (num_args < expected_num) |
e0001a05 NC |
2308 | { |
2309 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2310 | num_args, opname, expected_num); | |
2311 | return -1; | |
2312 | } | |
2313 | ||
2314 | if (num_args > expected_num) | |
2315 | { | |
2316 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2317 | num_args, opname, expected_num); | |
2318 | while (num_args-- > expected_num) | |
2319 | { | |
2320 | free (arg_strings[num_args]); | |
2321 | arg_strings[num_args] = 0; | |
2322 | } | |
2323 | *pnum_args = expected_num; | |
2324 | return -1; | |
2325 | } | |
2326 | ||
2327 | return 0; | |
2328 | } | |
2329 | ||
2330 | ||
43cd72b9 BW |
2331 | /* If the register is not specified as part of the opcode, |
2332 | then get it from the operand and move it to the opcode. */ | |
2333 | ||
e0001a05 | 2334 | static int |
7fa3d080 | 2335 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2336 | { |
43cd72b9 BW |
2337 | xtensa_isa isa = xtensa_default_isa; |
2338 | xtensa_sysreg sr; | |
e0001a05 | 2339 | char *opname, *new_opname; |
43cd72b9 BW |
2340 | const char *sr_name; |
2341 | int is_user, is_write; | |
e0001a05 NC |
2342 | |
2343 | opname = *popname; | |
2344 | if (*opname == '_') | |
80ca4e2c | 2345 | opname += 1; |
43cd72b9 BW |
2346 | is_user = (opname[1] == 'u'); |
2347 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2348 | |
43cd72b9 | 2349 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2350 | |
43cd72b9 BW |
2351 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2352 | return -1; | |
e0001a05 | 2353 | |
43cd72b9 BW |
2354 | /* Check if the argument is a symbolic register name. */ |
2355 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2356 | /* Handle WSR to "INTSET" as a special case. */ | |
2357 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2358 | && !strcasecmp (arg_strings[1], "intset")) | |
2359 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2360 | if (sr == XTENSA_UNDEFINED | |
2361 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2362 | { | |
2363 | /* Maybe it's a register number.... */ | |
2364 | offsetT val; | |
e0001a05 NC |
2365 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2366 | { | |
43cd72b9 BW |
2367 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2368 | arg_strings[1], opname); | |
e0001a05 NC |
2369 | return -1; |
2370 | } | |
43cd72b9 BW |
2371 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2372 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2373 | { |
43cd72b9 | 2374 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2375 | (long) val, opname); |
e0001a05 NC |
2376 | return -1; |
2377 | } | |
43cd72b9 | 2378 | } |
e0001a05 | 2379 | |
43cd72b9 BW |
2380 | /* Remove the last argument, which is now part of the opcode. */ |
2381 | free (arg_strings[1]); | |
2382 | arg_strings[1] = 0; | |
2383 | *pnum_args = 1; | |
2384 | ||
2385 | /* Translate the opcode. */ | |
2386 | sr_name = xtensa_sysreg_name (isa, sr); | |
2387 | /* Another special case for "WSR.INTSET".... */ | |
2388 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2389 | sr_name = "intset"; | |
4ec9d7d5 | 2390 | new_opname = concat (*popname, ".", sr_name, (char *) NULL); |
43cd72b9 BW |
2391 | free (*popname); |
2392 | *popname = new_opname; | |
2393 | ||
2394 | return 0; | |
2395 | } | |
2396 | ||
2397 | ||
2398 | static int | |
7fa3d080 | 2399 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2400 | { |
2401 | xtensa_isa isa = xtensa_default_isa; | |
2402 | xtensa_sysreg sr; | |
2403 | char *opname, *new_opname; | |
2404 | const char *sr_name; | |
5b7c81bd | 2405 | bool has_underbar = false; |
43cd72b9 BW |
2406 | |
2407 | opname = *popname; | |
2408 | if (opname[0] == '_') | |
2409 | { | |
5b7c81bd | 2410 | has_underbar = true; |
43cd72b9 BW |
2411 | opname += 1; |
2412 | } | |
2413 | ||
2414 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2415 | if (sr != XTENSA_UNDEFINED) | |
2416 | { | |
2417 | /* The new default name ("nnn") is different from the old default | |
2418 | name ("URnnn"). The old default is handled below, and we don't | |
2419 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2420 | default. */ | |
2421 | static char namebuf[10]; | |
2422 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2423 | if (strcmp (namebuf, opname + 1) == 0) | |
2424 | return 0; | |
2425 | } | |
2426 | else | |
2427 | { | |
2428 | offsetT val; | |
2429 | char *end; | |
2430 | ||
2431 | /* Only continue if the reg name is "URnnn". */ | |
2432 | if (opname[1] != 'u' || opname[2] != 'r') | |
2433 | return 0; | |
2434 | val = strtoul (opname + 3, &end, 10); | |
2435 | if (*end != '\0') | |
2436 | return 0; | |
2437 | ||
2438 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2439 | if (sr == XTENSA_UNDEFINED) | |
2440 | { | |
2441 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2442 | (long) val, opname); |
43cd72b9 BW |
2443 | return -1; |
2444 | } | |
2445 | } | |
2446 | ||
2447 | /* Translate the opcode. */ | |
2448 | sr_name = xtensa_sysreg_name (isa, sr); | |
add39d23 | 2449 | new_opname = XNEWVEC (char, strlen (sr_name) + 6); |
43cd72b9 BW |
2450 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), |
2451 | opname[0], sr_name); | |
2452 | free (*popname); | |
2453 | *popname = new_opname; | |
2454 | ||
2455 | return 0; | |
2456 | } | |
2457 | ||
2458 | ||
2459 | static int | |
b9bb4a93 TS |
2460 | xtensa_translate_zero_immed (const char *old_op, |
2461 | const char *new_op, | |
7fa3d080 BW |
2462 | char **popname, |
2463 | int *pnum_args, | |
2464 | char **arg_strings) | |
43cd72b9 BW |
2465 | { |
2466 | char *opname; | |
2467 | offsetT val; | |
2468 | ||
2469 | opname = *popname; | |
9c2799c2 | 2470 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2471 | |
2472 | if (strcmp (opname, old_op) != 0) | |
2473 | return 0; | |
e0001a05 | 2474 | |
43cd72b9 BW |
2475 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2476 | return -1; | |
2477 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2478 | { | |
2479 | xg_replace_opname (popname, new_op); | |
2480 | free (arg_strings[1]); | |
2481 | arg_strings[1] = arg_strings[2]; | |
2482 | arg_strings[2] = 0; | |
2483 | *pnum_args = 2; | |
e0001a05 NC |
2484 | } |
2485 | ||
2486 | return 0; | |
2487 | } | |
2488 | ||
2489 | ||
2490 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2491 | Returns non-zero if an error was found. */ | |
2492 | ||
2493 | static int | |
7fa3d080 | 2494 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2495 | { |
2496 | char *opname = *popname; | |
5b7c81bd | 2497 | bool has_underbar = false; |
e0001a05 NC |
2498 | |
2499 | if (*opname == '_') | |
2500 | { | |
5b7c81bd | 2501 | has_underbar = true; |
e0001a05 NC |
2502 | opname += 1; |
2503 | } | |
2504 | ||
2505 | if (strcmp (opname, "mov") == 0) | |
2506 | { | |
43cd72b9 | 2507 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2508 | xg_replace_opname (popname, "mov.n"); |
2509 | else | |
2510 | { | |
2511 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2512 | return -1; | |
2513 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 | 2514 | arg_strings[2] = xstrdup (arg_strings[1]); |
e0001a05 NC |
2515 | *pnum_args = 3; |
2516 | } | |
2517 | return 0; | |
2518 | } | |
2519 | ||
935f1f4b MF |
2520 | /* Without an operand, this is given a default immediate operand of 0. */ |
2521 | if ((strcmp (opname, "simcall") == 0 && microarch_earliest >= 280000)) | |
2522 | { | |
2523 | if (*pnum_args == 0) | |
2524 | { | |
2525 | arg_strings[0] = (char *) xmalloc (2); | |
2526 | strcpy (arg_strings[0], "0"); | |
2527 | *pnum_args = 1; | |
2528 | } | |
2529 | return 0; | |
2530 | } | |
2531 | ||
e0001a05 NC |
2532 | if (strcmp (opname, "bbsi.l") == 0) |
2533 | { | |
2534 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2535 | return -1; | |
2536 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2537 | if (target_big_endian) | |
2538 | xg_reverse_shift_count (&arg_strings[1]); | |
2539 | return 0; | |
2540 | } | |
2541 | ||
2542 | if (strcmp (opname, "bbci.l") == 0) | |
2543 | { | |
2544 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2545 | return -1; | |
2546 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2547 | if (target_big_endian) | |
2548 | xg_reverse_shift_count (&arg_strings[1]); | |
2549 | return 0; | |
2550 | } | |
2551 | ||
eb6d9dce | 2552 | /* Don't do anything special with NOPs inside FLIX instructions. They |
3739860c | 2553 | are handled elsewhere. Real NOP instructions are always available |
eb6d9dce BW |
2554 | in configurations with FLIX, so this should never be an issue but |
2555 | check for it anyway. */ | |
2556 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2557 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2558 | { |
43cd72b9 | 2559 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2560 | xg_replace_opname (popname, "nop.n"); |
2561 | else | |
2562 | { | |
2563 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2564 | return -1; | |
2565 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 TS |
2566 | arg_strings[0] = xstrdup ("a1"); |
2567 | arg_strings[1] = xstrdup ("a1"); | |
2568 | arg_strings[2] = xstrdup ("a1"); | |
e0001a05 NC |
2569 | *pnum_args = 3; |
2570 | } | |
2571 | return 0; | |
2572 | } | |
2573 | ||
43cd72b9 BW |
2574 | /* Recognize [RW]UR and [RWX]SR. */ |
2575 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2576 | && (opname[1] == 'u' || opname[1] == 's')) | |
2577 | || (opname[0] == 'x' && opname[1] == 's')) | |
2578 | && opname[2] == 'r' | |
2579 | && opname[3] == '\0') | |
e0001a05 NC |
2580 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2581 | ||
43cd72b9 BW |
2582 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2583 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2584 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2585 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2586 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2587 | |
43cd72b9 BW |
2588 | /* Relax branches that don't allow comparisons against an immediate value |
2589 | of zero to the corresponding branches with implicit zero immediates. */ | |
2590 | if (!has_underbar && use_transform ()) | |
2591 | { | |
2592 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2593 | pnum_args, arg_strings)) | |
2594 | return -1; | |
e0001a05 | 2595 | |
43cd72b9 BW |
2596 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2597 | pnum_args, arg_strings)) | |
2598 | return -1; | |
e0001a05 | 2599 | |
43cd72b9 BW |
2600 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2601 | pnum_args, arg_strings)) | |
2602 | return -1; | |
e0001a05 | 2603 | |
43cd72b9 BW |
2604 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2605 | pnum_args, arg_strings)) | |
2606 | return -1; | |
2607 | } | |
e0001a05 | 2608 | |
43cd72b9 BW |
2609 | return 0; |
2610 | } | |
e0001a05 | 2611 | |
43cd72b9 BW |
2612 | \f |
2613 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2614 | |
43cd72b9 BW |
2615 | /* Currently the assembler only allows us to use a single target per |
2616 | fragment. Because of this, only one operand for a given | |
2617 | instruction may be symbolic. If there is a PC-relative operand, | |
2618 | the last one is chosen. Otherwise, the result is the number of the | |
2619 | last immediate operand, and if there are none of those, we fail and | |
2620 | return -1. */ | |
e0001a05 | 2621 | |
7fa3d080 BW |
2622 | static int |
2623 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2624 | { |
2625 | int last_immed = -1; | |
2626 | int noperands, opi; | |
e0001a05 | 2627 | |
43cd72b9 BW |
2628 | if (opcode == XTENSA_UNDEFINED) |
2629 | return -1; | |
e0001a05 | 2630 | |
43cd72b9 BW |
2631 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2632 | for (opi = noperands - 1; opi >= 0; opi--) | |
2633 | { | |
2634 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2635 | continue; | |
2636 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2637 | return opi; | |
2638 | if (last_immed == -1 | |
2639 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2640 | last_immed = opi; | |
e0001a05 | 2641 | } |
43cd72b9 | 2642 | return last_immed; |
e0001a05 NC |
2643 | } |
2644 | ||
e0001a05 | 2645 | |
43cd72b9 | 2646 | static xtensa_opcode |
7fa3d080 | 2647 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2648 | { |
43cd72b9 BW |
2649 | static xtensa_insnbuf insnbuf = NULL; |
2650 | static xtensa_insnbuf slotbuf = NULL; | |
2651 | xtensa_isa isa = xtensa_default_isa; | |
2652 | xtensa_format fmt; | |
2653 | ||
2654 | if (!insnbuf) | |
e0001a05 | 2655 | { |
43cd72b9 BW |
2656 | insnbuf = xtensa_insnbuf_alloc (isa); |
2657 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2658 | } |
e0001a05 | 2659 | |
d77b99c9 | 2660 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2661 | fmt = xtensa_format_decode (isa, insnbuf); |
2662 | if (fmt == XTENSA_UNDEFINED) | |
2663 | return XTENSA_UNDEFINED; | |
e0001a05 | 2664 | |
43cd72b9 BW |
2665 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2666 | return XTENSA_UNDEFINED; | |
e0001a05 | 2667 | |
43cd72b9 BW |
2668 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2669 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2670 | } |
2671 | ||
2672 | ||
43cd72b9 | 2673 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2674 | |
43cd72b9 | 2675 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2676 | |
7fa3d080 BW |
2677 | static void |
2678 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2679 | { |
2680 | int num_opcodes, num_operands; | |
2681 | xtensa_opcode opcode; | |
2682 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2683 | |
43cd72b9 BW |
2684 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2685 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2686 | { |
43cd72b9 BW |
2687 | int opn; |
2688 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2689 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2690 | for (opn = 0; opn < num_operands; opn++) | |
2691 | { | |
2692 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2693 | continue; | |
2694 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2695 | { | |
2696 | xtensa_regfile opnd_rf = | |
2697 | xtensa_operand_regfile (isa, opcode, opn); | |
2698 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2699 | } | |
2700 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2701 | fputs ("[lLr] ", stderr); | |
2702 | else | |
2703 | fputs ("i ", stderr); | |
2704 | } | |
2705 | fprintf (stderr, "\n"); | |
e0001a05 | 2706 | } |
e0001a05 NC |
2707 | } |
2708 | ||
2709 | ||
43cd72b9 | 2710 | static void |
7fa3d080 | 2711 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2712 | { |
e0001a05 | 2713 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2714 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2715 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2716 | int op; | |
e0001a05 | 2717 | |
43cd72b9 | 2718 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2719 | |
43cd72b9 BW |
2720 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2721 | { | |
2722 | xtensa_opcode opcode; | |
2723 | const char *opname; | |
2724 | int operands; | |
2725 | ||
2726 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2727 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2728 | opname = xtensa_opcode_name (isa, opcode); | |
2729 | ||
2730 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2731 | fprintf (stderr, " operands = "); | |
2732 | for (operands = 0; | |
2733 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2734 | operands++) | |
2735 | { | |
2736 | unsigned int val; | |
2737 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2738 | continue; | |
2739 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2740 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2741 | fprintf (stderr, "%d ", val); | |
2742 | } | |
2743 | fprintf (stderr, "\n"); | |
2744 | } | |
2745 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2746 | } |
2747 | ||
43cd72b9 BW |
2748 | #endif /* TENSILICA_DEBUG */ |
2749 | ||
e0001a05 | 2750 | |
5b7c81bd | 2751 | static bool |
7fa3d080 | 2752 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2753 | { |
43cd72b9 BW |
2754 | xtensa_isa isa = xtensa_default_isa; |
2755 | int n, num_operands; | |
e0001a05 | 2756 | |
64b607e6 | 2757 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
5b7c81bd | 2758 | return false; |
e0001a05 | 2759 | |
43cd72b9 BW |
2760 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2761 | for (n = 0; n < num_operands; n++) | |
2762 | { | |
2763 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2764 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
5b7c81bd | 2765 | return true; |
43cd72b9 | 2766 | } |
5b7c81bd | 2767 | return false; |
e0001a05 NC |
2768 | } |
2769 | ||
2770 | ||
43cd72b9 BW |
2771 | /* Convert from BFD relocation type code to slot and operand number. |
2772 | Returns non-zero on failure. */ | |
e0001a05 | 2773 | |
43cd72b9 | 2774 | static int |
5b7c81bd | 2775 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bool *is_alt) |
e0001a05 | 2776 | { |
43cd72b9 BW |
2777 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2778 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2779 | { |
43cd72b9 | 2780 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
5b7c81bd | 2781 | *is_alt = false; |
e0001a05 | 2782 | } |
43cd72b9 BW |
2783 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2784 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2785 | { |
43cd72b9 | 2786 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
5b7c81bd | 2787 | *is_alt = true; |
e0001a05 | 2788 | } |
43cd72b9 BW |
2789 | else |
2790 | return -1; | |
2791 | ||
2792 | return 0; | |
e0001a05 NC |
2793 | } |
2794 | ||
2795 | ||
43cd72b9 BW |
2796 | /* Convert from slot number to BFD relocation type code for the |
2797 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2798 | failure. */ | |
e0001a05 | 2799 | |
43cd72b9 | 2800 | static bfd_reloc_code_real_type |
7fa3d080 | 2801 | encode_reloc (int slot) |
e0001a05 | 2802 | { |
43cd72b9 BW |
2803 | if (slot < 0 || slot > 14) |
2804 | return BFD_RELOC_NONE; | |
2805 | ||
2806 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2807 | } |
2808 | ||
2809 | ||
43cd72b9 BW |
2810 | /* Convert from slot numbers to BFD relocation type code for the |
2811 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2812 | |
43cd72b9 | 2813 | static bfd_reloc_code_real_type |
7fa3d080 | 2814 | encode_alt_reloc (int slot) |
e0001a05 | 2815 | { |
43cd72b9 BW |
2816 | if (slot < 0 || slot > 14) |
2817 | return BFD_RELOC_NONE; | |
2818 | ||
2819 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2820 | } |
2821 | ||
2822 | ||
2823 | static void | |
7fa3d080 BW |
2824 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2825 | xtensa_format fmt, | |
2826 | int slot, | |
2827 | xtensa_opcode opcode, | |
2828 | int operand, | |
2829 | uint32 value, | |
2830 | const char *file, | |
2831 | unsigned int line) | |
e0001a05 | 2832 | { |
e0001a05 NC |
2833 | uint32 valbuf = value; |
2834 | ||
43cd72b9 | 2835 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2836 | { |
43cd72b9 BW |
2837 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2838 | == 1) | |
2839 | as_bad_where ((char *) file, line, | |
3739860c | 2840 | _("operand %d of '%s' has out of range value '%u'"), |
d7c531cd BW |
2841 | operand + 1, |
2842 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2843 | value); | |
43cd72b9 BW |
2844 | else |
2845 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2846 | _("operand %d of '%s' has invalid value '%u'"), |
2847 | operand + 1, | |
2848 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2849 | value); | |
43cd72b9 | 2850 | return; |
e0001a05 NC |
2851 | } |
2852 | ||
43cd72b9 BW |
2853 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2854 | slotbuf, valbuf); | |
e0001a05 NC |
2855 | } |
2856 | ||
2857 | ||
2858 | static uint32 | |
7fa3d080 BW |
2859 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2860 | xtensa_format fmt, | |
2861 | int slot, | |
2862 | xtensa_opcode opcode, | |
2863 | int opnum) | |
e0001a05 | 2864 | { |
43cd72b9 BW |
2865 | uint32 val = 0; |
2866 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2867 | fmt, slot, slotbuf, &val); | |
2868 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2869 | return val; | |
e0001a05 NC |
2870 | } |
2871 | ||
e0001a05 | 2872 | \f |
7fa3d080 | 2873 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2874 | |
7fa3d080 BW |
2875 | /* The routine xg_instruction_matches_option_term must return TRUE |
2876 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2877 | terms is given interpretation by this function. */ |
e0001a05 | 2878 | |
5b7c81bd | 2879 | static bool |
19e8f41a | 2880 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2881 | { |
7fa3d080 | 2882 | if (strcmp (option->option_name, "realnop") == 0 |
d34049e8 | 2883 | || startswith (option->option_name, "IsaUse")) |
7fa3d080 BW |
2884 | { |
2885 | /* These conditions were evaluated statically when building the | |
2886 | relaxation table. There's no need to reevaluate them now. */ | |
5b7c81bd | 2887 | return true; |
7fa3d080 | 2888 | } |
19e8f41a BW |
2889 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2890 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2891 | else |
2892 | { | |
2893 | as_fatal (_("internal error: unknown option name '%s'"), | |
2894 | option->option_name); | |
2895 | } | |
e0001a05 NC |
2896 | } |
2897 | ||
2898 | ||
5b7c81bd | 2899 | static bool |
7fa3d080 BW |
2900 | xg_instruction_matches_or_options (TInsn *insn, |
2901 | const ReqOrOptionList *or_option) | |
e0001a05 | 2902 | { |
7fa3d080 BW |
2903 | const ReqOrOption *option; |
2904 | /* Must match each of the AND terms. */ | |
2905 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2906 | { |
7fa3d080 | 2907 | if (xg_instruction_matches_option_term (insn, option)) |
5b7c81bd | 2908 | return true; |
e0001a05 | 2909 | } |
5b7c81bd | 2910 | return false; |
e0001a05 NC |
2911 | } |
2912 | ||
2913 | ||
5b7c81bd | 2914 | static bool |
7fa3d080 | 2915 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) |
e0001a05 | 2916 | { |
7fa3d080 BW |
2917 | const ReqOption *req_options; |
2918 | /* Must match each of the AND terms. */ | |
2919 | for (req_options = options; | |
2920 | req_options != NULL; | |
2921 | req_options = req_options->next) | |
e0001a05 | 2922 | { |
7fa3d080 BW |
2923 | /* Must match one of the OR clauses. */ |
2924 | if (!xg_instruction_matches_or_options (insn, | |
2925 | req_options->or_option_terms)) | |
5b7c81bd | 2926 | return false; |
e0001a05 | 2927 | } |
5b7c81bd | 2928 | return true; |
e0001a05 NC |
2929 | } |
2930 | ||
2931 | ||
7fa3d080 | 2932 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2933 | |
5b7c81bd | 2934 | static bool |
7fa3d080 | 2935 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) |
e0001a05 | 2936 | { |
7fa3d080 | 2937 | PreconditionList *condition_l; |
e0001a05 | 2938 | |
7fa3d080 | 2939 | if (rule->opcode != insn->opcode) |
5b7c81bd | 2940 | return false; |
e0001a05 | 2941 | |
7fa3d080 BW |
2942 | for (condition_l = rule->conditions; |
2943 | condition_l != NULL; | |
2944 | condition_l = condition_l->next) | |
e0001a05 | 2945 | { |
7fa3d080 BW |
2946 | expressionS *exp1; |
2947 | expressionS *exp2; | |
2948 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2949 | |
7fa3d080 | 2950 | switch (cond->typ) |
e0001a05 | 2951 | { |
7fa3d080 BW |
2952 | case OP_CONSTANT: |
2953 | /* The expression must be the constant. */ | |
9c2799c2 | 2954 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2955 | exp1 = &insn->tok[cond->op_num]; |
2956 | if (expr_is_const (exp1)) | |
2957 | { | |
2958 | switch (cond->cmp) | |
2959 | { | |
2960 | case OP_EQUAL: | |
2961 | if (get_expr_const (exp1) != cond->op_data) | |
5b7c81bd | 2962 | return false; |
7fa3d080 BW |
2963 | break; |
2964 | case OP_NOTEQUAL: | |
2965 | if (get_expr_const (exp1) == cond->op_data) | |
5b7c81bd | 2966 | return false; |
7fa3d080 BW |
2967 | break; |
2968 | default: | |
5b7c81bd | 2969 | return false; |
7fa3d080 BW |
2970 | } |
2971 | } | |
2972 | else if (expr_is_register (exp1)) | |
2973 | { | |
2974 | switch (cond->cmp) | |
2975 | { | |
2976 | case OP_EQUAL: | |
2977 | if (get_expr_register (exp1) != cond->op_data) | |
5b7c81bd | 2978 | return false; |
7fa3d080 BW |
2979 | break; |
2980 | case OP_NOTEQUAL: | |
2981 | if (get_expr_register (exp1) == cond->op_data) | |
5b7c81bd | 2982 | return false; |
7fa3d080 BW |
2983 | break; |
2984 | default: | |
5b7c81bd | 2985 | return false; |
7fa3d080 BW |
2986 | } |
2987 | } | |
2988 | else | |
5b7c81bd | 2989 | return false; |
7fa3d080 BW |
2990 | break; |
2991 | ||
2992 | case OP_OPERAND: | |
9c2799c2 NC |
2993 | gas_assert (cond->op_num < insn->ntok); |
2994 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2995 | exp1 = &insn->tok[cond->op_num]; |
2996 | exp2 = &insn->tok[cond->op_data]; | |
2997 | ||
2998 | switch (cond->cmp) | |
2999 | { | |
3000 | case OP_EQUAL: | |
3001 | if (!expr_is_equal (exp1, exp2)) | |
5b7c81bd | 3002 | return false; |
7fa3d080 BW |
3003 | break; |
3004 | case OP_NOTEQUAL: | |
3005 | if (expr_is_equal (exp1, exp2)) | |
5b7c81bd | 3006 | return false; |
7fa3d080 BW |
3007 | break; |
3008 | } | |
3009 | break; | |
3010 | ||
3011 | case OP_LITERAL: | |
3012 | case OP_LABEL: | |
3013 | default: | |
5b7c81bd | 3014 | return false; |
7fa3d080 BW |
3015 | } |
3016 | } | |
3017 | if (!xg_instruction_matches_options (insn, rule->options)) | |
5b7c81bd | 3018 | return false; |
7fa3d080 | 3019 | |
5b7c81bd | 3020 | return true; |
7fa3d080 BW |
3021 | } |
3022 | ||
3023 | ||
3024 | static int | |
3025 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
3026 | { | |
5b7c81bd AM |
3027 | bool a_greater = false; |
3028 | bool b_greater = false; | |
7fa3d080 BW |
3029 | |
3030 | ReqOptionList *l_a = a->options; | |
3031 | ReqOptionList *l_b = b->options; | |
3032 | ||
3033 | /* We only care if they both are the same except for | |
3034 | a const16 vs. an l32r. */ | |
3035 | ||
3036 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
3037 | { | |
3038 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
3039 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
3040 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
3041 | { | |
3042 | if (l_or_a->is_true != l_or_b->is_true) | |
3043 | return 0; | |
3044 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
3045 | { | |
3046 | /* This is the case we care about. */ | |
3047 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
3048 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
3049 | { | |
3050 | if (prefer_const16) | |
5b7c81bd | 3051 | a_greater = true; |
7fa3d080 | 3052 | else |
5b7c81bd | 3053 | b_greater = true; |
7fa3d080 BW |
3054 | } |
3055 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
3056 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
3057 | { | |
3058 | if (prefer_const16) | |
5b7c81bd | 3059 | b_greater = true; |
7fa3d080 | 3060 | else |
5b7c81bd | 3061 | a_greater = true; |
7fa3d080 BW |
3062 | } |
3063 | else | |
3064 | return 0; | |
3065 | } | |
3066 | l_or_a = l_or_a->next; | |
3067 | l_or_b = l_or_b->next; | |
3068 | } | |
3069 | if (l_or_a || l_or_b) | |
3070 | return 0; | |
3071 | ||
3072 | l_a = l_a->next; | |
3073 | l_b = l_b->next; | |
3074 | } | |
3075 | if (l_a || l_b) | |
3076 | return 0; | |
3077 | ||
3078 | /* Incomparable if the substitution was used differently in two cases. */ | |
3079 | if (a_greater && b_greater) | |
3080 | return 0; | |
3081 | ||
3082 | if (b_greater) | |
3083 | return 1; | |
3084 | if (a_greater) | |
3085 | return -1; | |
3086 | ||
3087 | return 0; | |
3088 | } | |
3089 | ||
3090 | ||
3091 | static TransitionRule * | |
3092 | xg_instruction_match (TInsn *insn) | |
3093 | { | |
3094 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
3095 | TransitionList *l; | |
9c2799c2 | 3096 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
3097 | |
3098 | /* Walk through all of the possible transitions. */ | |
3099 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3100 | { | |
3101 | TransitionRule *rule = l->rule; | |
3102 | if (xg_instruction_matches_rule (insn, rule)) | |
3103 | return rule; | |
3104 | } | |
3105 | return NULL; | |
3106 | } | |
3107 | ||
3108 | \f | |
3109 | /* Various Other Internal Functions. */ | |
3110 | ||
5b7c81bd | 3111 | static bool |
7fa3d080 BW |
3112 | is_unique_insn_expansion (TransitionRule *r) |
3113 | { | |
3114 | if (!r->to_instr || r->to_instr->next != NULL) | |
5b7c81bd | 3115 | return false; |
7fa3d080 | 3116 | if (r->to_instr->typ != INSTR_INSTR) |
5b7c81bd AM |
3117 | return false; |
3118 | return true; | |
7fa3d080 BW |
3119 | } |
3120 | ||
3121 | ||
84b08ed9 BW |
3122 | /* Check if there is exactly one relaxation for INSN that converts it to |
3123 | another instruction of equal or larger size. If so, and if TARG is | |
3124 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3125 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3126 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3127 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3128 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3129 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3130 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3131 | |
5b7c81bd AM |
3132 | bool |
3133 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bool narrow_only) | |
7fa3d080 BW |
3134 | { |
3135 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3136 | TransitionList *l; | |
84b08ed9 | 3137 | TransitionRule *match = 0; |
7fa3d080 | 3138 | |
9c2799c2 NC |
3139 | gas_assert (insn->insn_type == ITYPE_INSN); |
3140 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3141 | |
3142 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3143 | { | |
3144 | TransitionRule *rule = l->rule; | |
3145 | ||
3146 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3147 | && is_unique_insn_expansion (rule) |
3148 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3149 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3150 | { |
84b08ed9 | 3151 | if (match) |
5b7c81bd | 3152 | return false; |
84b08ed9 | 3153 | match = rule; |
7fa3d080 BW |
3154 | } |
3155 | } | |
84b08ed9 | 3156 | if (!match) |
5b7c81bd | 3157 | return false; |
84b08ed9 BW |
3158 | |
3159 | if (targ) | |
3160 | xg_build_to_insn (targ, insn, match->to_instr); | |
5b7c81bd | 3161 | return true; |
7fa3d080 BW |
3162 | } |
3163 | ||
3164 | ||
3165 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3166 | ||
3167 | static int | |
3168 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3169 | { | |
3170 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3171 | TransitionList *l; | |
3172 | int max_size = xg_get_single_size (opcode); | |
3173 | ||
9c2799c2 | 3174 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3175 | |
3176 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3177 | { | |
3178 | TransitionRule *rule = l->rule; | |
3179 | BuildInstr *build_list; | |
3180 | int this_size = 0; | |
3181 | ||
3182 | if (!rule) | |
3183 | continue; | |
3184 | build_list = rule->to_instr; | |
3185 | if (is_unique_insn_expansion (rule)) | |
3186 | { | |
9c2799c2 | 3187 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3188 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3189 | } | |
3190 | else | |
3191 | for (; build_list != NULL; build_list = build_list->next) | |
3192 | { | |
3193 | switch (build_list->typ) | |
3194 | { | |
3195 | case INSTR_INSTR: | |
3196 | this_size += xg_get_single_size (build_list->opcode); | |
3197 | break; | |
3198 | case INSTR_LITERAL_DEF: | |
3199 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3200 | default: |
3201 | break; | |
3202 | } | |
3203 | } | |
3204 | if (this_size > max_size) | |
3205 | max_size = this_size; | |
3206 | } | |
3207 | return max_size; | |
3208 | } | |
3209 | ||
3210 | ||
3211 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3212 | ||
7fa3d080 BW |
3213 | static int |
3214 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3215 | { |
43cd72b9 | 3216 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3217 | TransitionList *l; |
3218 | int max_size = 0; | |
3219 | ||
9c2799c2 | 3220 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3221 | |
3222 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3223 | { | |
3224 | TransitionRule *rule = l->rule; | |
3225 | BuildInstr *build_list; | |
3226 | int this_size = 0; | |
3227 | ||
3228 | if (!rule) | |
3229 | continue; | |
3230 | build_list = rule->to_instr; | |
3231 | if (is_unique_insn_expansion (rule)) | |
3232 | { | |
9c2799c2 | 3233 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3234 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3235 | } | |
3236 | else | |
3237 | for (; build_list != NULL; build_list = build_list->next) | |
3238 | { | |
3239 | switch (build_list->typ) | |
3240 | { | |
3241 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3242 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3243 | this_size += 4; |
3244 | break; | |
3245 | case INSTR_INSTR: | |
3246 | case INSTR_LABEL_DEF: | |
3247 | default: | |
3248 | break; | |
3249 | } | |
3250 | } | |
3251 | if (this_size > max_size) | |
3252 | max_size = this_size; | |
3253 | } | |
3254 | return max_size; | |
3255 | } | |
3256 | ||
3257 | ||
5b7c81bd | 3258 | static bool |
7fa3d080 BW |
3259 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) |
3260 | { | |
3261 | int steps_taken = 0; | |
3262 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3263 | TransitionList *l; | |
3264 | ||
9c2799c2 NC |
3265 | gas_assert (insn->insn_type == ITYPE_INSN); |
3266 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3267 | |
3268 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3269 | { | |
3270 | TransitionRule *rule = l->rule; | |
3271 | ||
3272 | if (xg_instruction_matches_rule (insn, rule)) | |
3273 | { | |
3274 | if (steps_taken == lateral_steps) | |
5b7c81bd | 3275 | return true; |
7fa3d080 BW |
3276 | steps_taken++; |
3277 | } | |
3278 | } | |
5b7c81bd | 3279 | return false; |
7fa3d080 BW |
3280 | } |
3281 | ||
3282 | ||
3283 | static symbolS * | |
3284 | get_special_literal_symbol (void) | |
3285 | { | |
3286 | static symbolS *sym = NULL; | |
3287 | ||
3288 | if (sym == NULL) | |
3289 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3290 | return sym; | |
3291 | } | |
3292 | ||
3293 | ||
3294 | static symbolS * | |
3295 | get_special_label_symbol (void) | |
3296 | { | |
3297 | static symbolS *sym = NULL; | |
3298 | ||
3299 | if (sym == NULL) | |
3300 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3301 | return sym; | |
3302 | } | |
3303 | ||
3304 | ||
5b7c81bd | 3305 | static bool |
7fa3d080 BW |
3306 | xg_valid_literal_expression (const expressionS *exp) |
3307 | { | |
3308 | switch (exp->X_op) | |
3309 | { | |
3310 | case O_constant: | |
3311 | case O_symbol: | |
3312 | case O_big: | |
3313 | case O_uminus: | |
3314 | case O_subtract: | |
3315 | case O_pltrel: | |
1bbb5f21 | 3316 | case O_pcrel: |
28dbbc02 BW |
3317 | case O_tlsfunc: |
3318 | case O_tlsarg: | |
3319 | case O_tpoff: | |
3320 | case O_dtpoff: | |
5b7c81bd | 3321 | return true; |
7fa3d080 | 3322 | default: |
5b7c81bd | 3323 | return false; |
7fa3d080 BW |
3324 | } |
3325 | } | |
3326 | ||
3327 | ||
3328 | /* This will check to see if the value can be converted into the | |
3329 | operand type. It will return TRUE if it does not fit. */ | |
3330 | ||
5b7c81bd | 3331 | static bool |
7fa3d080 BW |
3332 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) |
3333 | { | |
3334 | uint32 valbuf = value; | |
3335 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
5b7c81bd AM |
3336 | return true; |
3337 | return false; | |
7fa3d080 BW |
3338 | } |
3339 | ||
3340 | ||
3341 | /* Assumes: All immeds are constants. Check that all constants fit | |
3342 | into their immeds; return FALSE if not. */ | |
3343 | ||
5b7c81bd | 3344 | static bool |
7fa3d080 BW |
3345 | xg_immeds_fit (const TInsn *insn) |
3346 | { | |
3347 | xtensa_isa isa = xtensa_default_isa; | |
3348 | int i; | |
3349 | ||
3350 | int n = insn->ntok; | |
9c2799c2 | 3351 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3352 | for (i = 0; i < n; ++i) |
3353 | { | |
91d6fa6a NC |
3354 | const expressionS *exp = &insn->tok[i]; |
3355 | ||
7fa3d080 BW |
3356 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3357 | continue; | |
3358 | ||
91d6fa6a | 3359 | switch (exp->X_op) |
7fa3d080 BW |
3360 | { |
3361 | case O_register: | |
3362 | case O_constant: | |
91d6fa6a | 3363 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
5b7c81bd | 3364 | return false; |
7fa3d080 BW |
3365 | break; |
3366 | ||
3367 | default: | |
3368 | /* The symbol should have a fixup associated with it. */ | |
5b7c81bd | 3369 | gas_assert (false); |
7fa3d080 BW |
3370 | break; |
3371 | } | |
3372 | } | |
5b7c81bd | 3373 | return true; |
7fa3d080 BW |
3374 | } |
3375 | ||
3376 | ||
3377 | /* This should only be called after we have an initial | |
3378 | estimate of the addresses. */ | |
3379 | ||
5b7c81bd | 3380 | static bool |
7fa3d080 BW |
3381 | xg_symbolic_immeds_fit (const TInsn *insn, |
3382 | segT pc_seg, | |
3383 | fragS *pc_frag, | |
3384 | offsetT pc_offset, | |
3385 | long stretch) | |
e0001a05 | 3386 | { |
7fa3d080 BW |
3387 | xtensa_isa isa = xtensa_default_isa; |
3388 | symbolS *symbolP; | |
3389 | fragS *sym_frag; | |
3390 | offsetT target, pc; | |
3391 | uint32 new_offset; | |
3392 | int i; | |
3393 | int n = insn->ntok; | |
e0001a05 | 3394 | |
9c2799c2 | 3395 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3396 | |
7fa3d080 | 3397 | for (i = 0; i < n; ++i) |
e0001a05 | 3398 | { |
91d6fa6a NC |
3399 | const expressionS *exp = &insn->tok[i]; |
3400 | ||
7fa3d080 BW |
3401 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3402 | continue; | |
e0001a05 | 3403 | |
91d6fa6a | 3404 | switch (exp->X_op) |
e0001a05 | 3405 | { |
7fa3d080 BW |
3406 | case O_register: |
3407 | case O_constant: | |
91d6fa6a | 3408 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
5b7c81bd | 3409 | return false; |
7fa3d080 | 3410 | break; |
e0001a05 | 3411 | |
7fa3d080 BW |
3412 | case O_lo16: |
3413 | case O_hi16: | |
3414 | /* Check for the worst case. */ | |
3415 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
5b7c81bd | 3416 | return false; |
7fa3d080 | 3417 | break; |
e0001a05 | 3418 | |
7fa3d080 | 3419 | case O_symbol: |
7c834684 | 3420 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3421 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3422 | if (pc_frag == 0 |
3423 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
5b7c81bd | 3424 | return false; |
e0001a05 | 3425 | |
8e6bc631 BW |
3426 | /* If it is a weak symbol or a symbol in a different section, |
3427 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3428 | if (S_IS_WEAK (exp->X_add_symbol) |
3429 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3430 | { |
8e6bc631 | 3431 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3432 | assume it will be in range. If the symbol is weak and |
3433 | undefined, it may remain undefined at link-time, in which | |
3434 | case it will have a zero value and almost certainly be out | |
3435 | of range for a direct call; thus, relax for undefined weak | |
3436 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3437 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3438 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3439 | && (! S_IS_WEAK (exp->X_add_symbol) |
3440 | || S_IS_DEFINED (exp->X_add_symbol))) | |
5b7c81bd | 3441 | return true; |
7c834684 | 3442 | |
5b7c81bd | 3443 | return false; |
8e6bc631 | 3444 | } |
e0001a05 | 3445 | |
91d6fa6a | 3446 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3447 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3448 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3449 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3450 | |
7fa3d080 BW |
3451 | /* If frag has yet to be reached on this pass, assume it |
3452 | will move by STRETCH just as we did. If this is not so, | |
3453 | it will be because some frag between grows, and that will | |
3454 | force another pass. Beware zero-length frags. There | |
3455 | should be a faster way to do this. */ | |
3456 | ||
3457 | if (stretch != 0 | |
3458 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3459 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3460 | { | |
3461 | target += stretch; | |
3462 | } | |
c138bc38 | 3463 | |
7fa3d080 BW |
3464 | new_offset = target; |
3465 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3466 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
5b7c81bd | 3467 | return false; |
7fa3d080 BW |
3468 | break; |
3469 | ||
3470 | default: | |
3471 | /* The symbol should have a fixup associated with it. */ | |
5b7c81bd | 3472 | return false; |
7fa3d080 BW |
3473 | } |
3474 | } | |
3475 | ||
5b7c81bd | 3476 | return true; |
e0001a05 NC |
3477 | } |
3478 | ||
3479 | ||
43cd72b9 | 3480 | /* Return TRUE on success. */ |
e0001a05 | 3481 | |
5b7c81bd | 3482 | static bool |
7fa3d080 | 3483 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) |
e0001a05 NC |
3484 | { |
3485 | BuildOp *op; | |
3486 | symbolS *sym; | |
3487 | ||
60242db2 | 3488 | tinsn_init (targ); |
b224e962 BW |
3489 | targ->debug_line = insn->debug_line; |
3490 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3491 | switch (bi->typ) |
3492 | { | |
3493 | case INSTR_INSTR: | |
3494 | op = bi->ops; | |
3495 | targ->opcode = bi->opcode; | |
3496 | targ->insn_type = ITYPE_INSN; | |
5b7c81bd | 3497 | targ->is_specific_opcode = false; |
e0001a05 NC |
3498 | |
3499 | for (; op != NULL; op = op->next) | |
3500 | { | |
3501 | int op_num = op->op_num; | |
3502 | int op_data = op->op_data; | |
3503 | ||
9c2799c2 | 3504 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3505 | |
3506 | if (targ->ntok <= op_num) | |
3507 | targ->ntok = op_num + 1; | |
3508 | ||
3509 | switch (op->typ) | |
3510 | { | |
3511 | case OP_CONSTANT: | |
3512 | set_expr_const (&targ->tok[op_num], op_data); | |
3513 | break; | |
3514 | case OP_OPERAND: | |
9c2799c2 | 3515 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3516 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3517 | break; | |
19e8f41a BW |
3518 | case OP_FREEREG: |
3519 | if (insn->extra_arg.X_op != O_register) | |
5b7c81bd | 3520 | return false; |
19e8f41a BW |
3521 | copy_expr (&targ->tok[op_num], &insn->extra_arg); |
3522 | break; | |
e0001a05 NC |
3523 | case OP_LITERAL: |
3524 | sym = get_special_literal_symbol (); | |
3525 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3526 | if (insn->tok[op_data].X_op == O_tlsfunc |
3527 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3528 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3529 | break; |
3530 | case OP_LABEL: | |
3531 | sym = get_special_label_symbol (); | |
3532 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3533 | break; | |
43cd72b9 BW |
3534 | case OP_OPERAND_HI16U: |
3535 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3536 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3537 | if (expr_is_const (&insn->tok[op_data])) |
3538 | { | |
3539 | long val; | |
3540 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3541 | val = xg_apply_userdef_op_fn (op->typ, | |
3542 | targ->tok[op_num]. | |
3543 | X_add_number); | |
3544 | targ->tok[op_num].X_add_number = val; | |
3545 | } | |
3546 | else | |
3547 | { | |
3548 | /* For const16 we can create relocations for these. */ | |
3549 | if (targ->opcode == XTENSA_UNDEFINED | |
3550 | || (targ->opcode != xtensa_const16_opcode)) | |
5b7c81bd | 3551 | return false; |
9c2799c2 | 3552 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3553 | /* Need to build a O_lo16 or O_hi16. */ |
3554 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3555 | if (targ->tok[op_num].X_op == O_symbol) | |
3556 | { | |
3557 | if (op->typ == OP_OPERAND_HI16U) | |
3558 | targ->tok[op_num].X_op = O_hi16; | |
3559 | else if (op->typ == OP_OPERAND_LOW16U) | |
3560 | targ->tok[op_num].X_op = O_lo16; | |
3561 | else | |
5b7c81bd | 3562 | return false; |
43cd72b9 BW |
3563 | } |
3564 | } | |
3565 | break; | |
e0001a05 NC |
3566 | default: |
3567 | /* currently handles: | |
3568 | OP_OPERAND_LOW8 | |
3569 | OP_OPERAND_HI24S | |
3570 | OP_OPERAND_F32MINUS */ | |
3571 | if (xg_has_userdef_op_fn (op->typ)) | |
3572 | { | |
9c2799c2 | 3573 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3574 | if (expr_is_const (&insn->tok[op_data])) |
3575 | { | |
3576 | long val; | |
3577 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3578 | val = xg_apply_userdef_op_fn (op->typ, | |
3579 | targ->tok[op_num]. | |
3580 | X_add_number); | |
3581 | targ->tok[op_num].X_add_number = val; | |
3582 | } | |
3583 | else | |
5b7c81bd | 3584 | return false; /* We cannot use a relocation for this. */ |
e0001a05 NC |
3585 | break; |
3586 | } | |
9c2799c2 | 3587 | gas_assert (0); |
e0001a05 NC |
3588 | break; |
3589 | } | |
3590 | } | |
3591 | break; | |
3592 | ||
3593 | case INSTR_LITERAL_DEF: | |
3594 | op = bi->ops; | |
3595 | targ->opcode = XTENSA_UNDEFINED; | |
3596 | targ->insn_type = ITYPE_LITERAL; | |
5b7c81bd | 3597 | targ->is_specific_opcode = false; |
e0001a05 NC |
3598 | for (; op != NULL; op = op->next) |
3599 | { | |
3600 | int op_num = op->op_num; | |
3601 | int op_data = op->op_data; | |
9c2799c2 | 3602 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3603 | |
3604 | if (targ->ntok <= op_num) | |
3605 | targ->ntok = op_num + 1; | |
3606 | ||
3607 | switch (op->typ) | |
3608 | { | |
3609 | case OP_OPERAND: | |
9c2799c2 | 3610 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3611 | /* We can only pass resolvable literals through. */ |
3612 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
5b7c81bd | 3613 | return false; |
e0001a05 NC |
3614 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3615 | break; | |
3616 | case OP_LITERAL: | |
3617 | case OP_CONSTANT: | |
3618 | case OP_LABEL: | |
3619 | default: | |
9c2799c2 | 3620 | gas_assert (0); |
e0001a05 NC |
3621 | break; |
3622 | } | |
3623 | } | |
3624 | break; | |
3625 | ||
3626 | case INSTR_LABEL_DEF: | |
3627 | op = bi->ops; | |
3628 | targ->opcode = XTENSA_UNDEFINED; | |
3629 | targ->insn_type = ITYPE_LABEL; | |
5b7c81bd | 3630 | targ->is_specific_opcode = false; |
43cd72b9 | 3631 | /* Literal with no ops is a label? */ |
9c2799c2 | 3632 | gas_assert (op == NULL); |
e0001a05 NC |
3633 | break; |
3634 | ||
3635 | default: | |
9c2799c2 | 3636 | gas_assert (0); |
e0001a05 NC |
3637 | } |
3638 | ||
5b7c81bd | 3639 | return true; |
e0001a05 NC |
3640 | } |
3641 | ||
3642 | ||
43cd72b9 | 3643 | /* Return TRUE on success. */ |
e0001a05 | 3644 | |
5b7c81bd | 3645 | static bool |
7fa3d080 | 3646 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) |
e0001a05 NC |
3647 | { |
3648 | for (; bi != NULL; bi = bi->next) | |
3649 | { | |
3650 | TInsn *next_insn = istack_push_space (istack); | |
3651 | ||
3652 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
5b7c81bd | 3653 | return false; |
e0001a05 | 3654 | } |
5b7c81bd | 3655 | return true; |
e0001a05 NC |
3656 | } |
3657 | ||
3658 | ||
43cd72b9 | 3659 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3660 | |
5b7c81bd | 3661 | static bool |
7fa3d080 | 3662 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) |
e0001a05 NC |
3663 | { |
3664 | int stack_size = istack->ninsn; | |
3665 | int steps_taken = 0; | |
43cd72b9 | 3666 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3667 | TransitionList *l; |
3668 | ||
9c2799c2 NC |
3669 | gas_assert (insn->insn_type == ITYPE_INSN); |
3670 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3671 | |
3672 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3673 | { | |
3674 | TransitionRule *rule = l->rule; | |
3675 | ||
3676 | if (xg_instruction_matches_rule (insn, rule)) | |
3677 | { | |
3678 | if (lateral_steps == steps_taken) | |
3679 | { | |
3680 | int i; | |
3681 | ||
3682 | /* This is it. Expand the rule to the stack. */ | |
3683 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
5b7c81bd | 3684 | return false; |
e0001a05 NC |
3685 | |
3686 | /* Check to see if it fits. */ | |
3687 | for (i = stack_size; i < istack->ninsn; i++) | |
3688 | { | |
91d6fa6a | 3689 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3690 | |
91d6fa6a NC |
3691 | if (tinsn->insn_type == ITYPE_INSN |
3692 | && !tinsn_has_symbolic_operands (tinsn) | |
3693 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3694 | { |
3695 | istack->ninsn = stack_size; | |
5b7c81bd | 3696 | return false; |
e0001a05 NC |
3697 | } |
3698 | } | |
5b7c81bd | 3699 | return true; |
e0001a05 NC |
3700 | } |
3701 | steps_taken++; | |
3702 | } | |
3703 | } | |
5b7c81bd | 3704 | return false; |
e0001a05 NC |
3705 | } |
3706 | ||
43cd72b9 | 3707 | \f |
43cd72b9 | 3708 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3709 | Return the number of steps taken. |
3710 | ||
3711 | For relaxation to correctly terminate, every relaxation chain must | |
3712 | terminate in one of two ways: | |
3713 | ||
3714 | 1. If the chain from one instruction to the next consists entirely of | |
3715 | single instructions, then the chain *must* handle all possible | |
3716 | immediates without failing. It must not ever fail because an | |
3717 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3718 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3719 | immediate larger than 32 bits, so it satisfies this condition. | |
3720 | Single instruction relaxation chains are as defined by | |
3721 | xg_is_single_relaxable_instruction. | |
3722 | ||
3723 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3724 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3725 | ||
3726 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3727 | -- in particular when the last two instructions have the same single | |
3728 | size. But nevertheless, you should guarantee the above two conditions. | |
3729 | ||
3730 | We could fix this so that single-instruction expansions correctly | |
3731 | terminate when they can't handle the range, but the error messages are | |
3732 | worse, and it actually turns out that in every case but one (18-bit wide | |
3733 | branches), you need a multi-instruction expansion to get the full range | |
3734 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3735 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3736 | |
7fa3d080 BW |
3737 | static int |
3738 | xg_assembly_relax (IStack *istack, | |
3739 | TInsn *insn, | |
3740 | segT pc_seg, | |
3741 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3742 | offsetT pc_offset, /* offset in fragment */ | |
3743 | int min_steps, /* minimum conversion steps */ | |
3744 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3745 | { |
3746 | int steps_taken = 0; | |
3747 | ||
b81bf389 BW |
3748 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3749 | This may go through a couple of stages of single instruction | |
3750 | transformations before we get there. */ | |
e0001a05 NC |
3751 | |
3752 | TInsn single_target; | |
3753 | TInsn current_insn; | |
3754 | int lateral_steps = 0; | |
3755 | int istack_size = istack->ninsn; | |
3756 | ||
3757 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3758 | && steps_taken >= min_steps) | |
3759 | { | |
3760 | istack_push (istack, insn); | |
3761 | return steps_taken; | |
3762 | } | |
43cd72b9 | 3763 | current_insn = *insn; |
e0001a05 | 3764 | |
7c834684 | 3765 | /* Walk through all of the single instruction expansions. */ |
5b7c81bd | 3766 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, false)) |
e0001a05 | 3767 | { |
21af2bbd | 3768 | steps_taken++; |
e0001a05 NC |
3769 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3770 | stretch)) | |
3771 | { | |
e0001a05 NC |
3772 | if (steps_taken >= min_steps) |
3773 | { | |
3774 | istack_push (istack, &single_target); | |
3775 | return steps_taken; | |
3776 | } | |
3777 | } | |
43cd72b9 | 3778 | current_insn = single_target; |
e0001a05 NC |
3779 | } |
3780 | ||
3781 | /* Now check for a multi-instruction expansion. */ | |
3782 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3783 | { | |
3784 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3785 | stretch)) | |
3786 | { | |
3787 | if (steps_taken >= min_steps) | |
3788 | { | |
3789 | istack_push (istack, ¤t_insn); | |
3790 | return steps_taken; | |
3791 | } | |
3792 | } | |
3793 | steps_taken++; | |
3794 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3795 | { | |
3796 | if (steps_taken >= min_steps) | |
3797 | return steps_taken; | |
3798 | } | |
3799 | lateral_steps++; | |
3800 | istack->ninsn = istack_size; | |
3801 | } | |
3802 | ||
3803 | /* It's not going to work -- use the original. */ | |
3804 | istack_push (istack, insn); | |
3805 | return steps_taken; | |
3806 | } | |
3807 | ||
3808 | ||
7fa3d080 BW |
3809 | static void |
3810 | xg_finish_frag (char *last_insn, | |
3811 | enum xtensa_relax_statesE frag_state, | |
3812 | enum xtensa_relax_statesE slot0_state, | |
3813 | int max_growth, | |
5b7c81bd | 3814 | bool is_insn) |
e0001a05 NC |
3815 | { |
3816 | /* Finish off this fragment so that it has at LEAST the desired | |
3817 | max_growth. If it doesn't fit in this fragment, close this one | |
3818 | and start a new one. In either case, return a pointer to the | |
3819 | beginning of the growth area. */ | |
3820 | ||
3821 | fragS *old_frag; | |
43cd72b9 | 3822 | |
542f8b94 | 3823 | frag_grow (max_growth); |
e0001a05 NC |
3824 | old_frag = frag_now; |
3825 | ||
3826 | frag_now->fr_opcode = last_insn; | |
3827 | if (is_insn) | |
5b7c81bd | 3828 | frag_now->tc_frag_data.is_insn = true; |
e0001a05 NC |
3829 | |
3830 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3831 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3832 | ||
3833 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3834 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3835 | |
3836 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3837 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3838 | } |
3839 | ||
3840 | ||
7fa3d080 BW |
3841 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3842 | ||
5b7c81bd | 3843 | static bool |
7fa3d080 BW |
3844 | is_next_frag_target (const fragS *fragP, const fragS *target) |
3845 | { | |
3846 | if (fragP == NULL) | |
5b7c81bd | 3847 | return false; |
7fa3d080 BW |
3848 | |
3849 | for (; fragP; fragP = fragP->fr_next) | |
3850 | { | |
3851 | if (fragP == target) | |
5b7c81bd | 3852 | return true; |
7fa3d080 | 3853 | if (fragP->fr_fix != 0) |
5b7c81bd | 3854 | return false; |
7fa3d080 | 3855 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) |
5b7c81bd | 3856 | return false; |
7fa3d080 BW |
3857 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) |
3858 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
5b7c81bd | 3859 | return false; |
7fa3d080 | 3860 | if (fragP->fr_type == rs_space) |
5b7c81bd | 3861 | return false; |
7fa3d080 | 3862 | } |
5b7c81bd | 3863 | return false; |
7fa3d080 BW |
3864 | } |
3865 | ||
3866 | ||
5b7c81bd | 3867 | static bool |
7fa3d080 | 3868 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3869 | { |
3870 | xtensa_isa isa = xtensa_default_isa; | |
3871 | int i; | |
43cd72b9 | 3872 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3873 | int target_op = -1; |
3874 | symbolS *sym; | |
3875 | fragS *target_frag; | |
3876 | ||
64b607e6 BW |
3877 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3878 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
5b7c81bd | 3879 | return false; |
e0001a05 NC |
3880 | |
3881 | for (i = 0; i < num_ops; i++) | |
3882 | { | |
43cd72b9 | 3883 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3884 | { |
3885 | target_op = i; | |
3886 | break; | |
3887 | } | |
3888 | } | |
3889 | if (target_op == -1) | |
5b7c81bd | 3890 | return false; |
e0001a05 NC |
3891 | |
3892 | if (insn->ntok <= target_op) | |
5b7c81bd | 3893 | return false; |
e0001a05 NC |
3894 | |
3895 | if (insn->tok[target_op].X_op != O_symbol) | |
5b7c81bd | 3896 | return false; |
e0001a05 NC |
3897 | |
3898 | sym = insn->tok[target_op].X_add_symbol; | |
3899 | if (sym == NULL) | |
5b7c81bd | 3900 | return false; |
e0001a05 NC |
3901 | |
3902 | if (insn->tok[target_op].X_add_number != 0) | |
5b7c81bd | 3903 | return false; |
e0001a05 NC |
3904 | |
3905 | target_frag = symbol_get_frag (sym); | |
3906 | if (target_frag == NULL) | |
5b7c81bd | 3907 | return false; |
e0001a05 | 3908 | |
c138bc38 | 3909 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 | 3910 | && S_GET_VALUE (sym) == target_frag->fr_address) |
5b7c81bd | 3911 | return true; |
e0001a05 | 3912 | |
5b7c81bd | 3913 | return false; |
e0001a05 NC |
3914 | } |
3915 | ||
3916 | ||
3917 | static void | |
7fa3d080 | 3918 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3919 | { |
3920 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3921 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3922 | |
7fa3d080 BW |
3923 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3924 | { | |
3925 | int i = 1; | |
3926 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3927 | && insn->tok[i].X_op == O_symbol) | |
5b7c81bd | 3928 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = true; |
7fa3d080 BW |
3929 | return; |
3930 | } | |
e0001a05 | 3931 | |
7fa3d080 BW |
3932 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3933 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3934 | { |
7fa3d080 BW |
3935 | int i; |
3936 | ||
3937 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3938 | { | |
3939 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3940 | && insn->tok[i].X_op == O_symbol) | |
3941 | { | |
3942 | symbolS *sym = insn->tok[i].X_add_symbol; | |
5b7c81bd | 3943 | symbol_get_tc (sym)->is_branch_target = true; |
7fa3d080 | 3944 | if (S_IS_DEFINED (sym)) |
5b7c81bd | 3945 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = true; |
7fa3d080 BW |
3946 | } |
3947 | } | |
e0001a05 | 3948 | } |
e0001a05 NC |
3949 | } |
3950 | ||
3951 | ||
43cd72b9 | 3952 | /* Return FALSE if no error. */ |
e0001a05 | 3953 | |
5b7c81bd | 3954 | static bool |
7fa3d080 | 3955 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) |
e0001a05 NC |
3956 | { |
3957 | int num_ops = 0; | |
3958 | BuildOp *b_op; | |
3959 | ||
3960 | switch (instr_spec->typ) | |
3961 | { | |
3962 | case INSTR_INSTR: | |
3963 | new_insn->insn_type = ITYPE_INSN; | |
3964 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3965 | break; |
3966 | case INSTR_LITERAL_DEF: | |
3967 | new_insn->insn_type = ITYPE_LITERAL; | |
3968 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3969 | break; |
3970 | case INSTR_LABEL_DEF: | |
b224e962 | 3971 | abort (); |
e0001a05 | 3972 | } |
5b7c81bd | 3973 | new_insn->is_specific_opcode = false; |
b224e962 BW |
3974 | new_insn->debug_line = old_insn->debug_line; |
3975 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3976 | |
3977 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3978 | { | |
3979 | expressionS *exp; | |
3980 | const expressionS *src_exp; | |
3981 | ||
3982 | num_ops++; | |
3983 | switch (b_op->typ) | |
3984 | { | |
3985 | case OP_CONSTANT: | |
3986 | /* The expression must be the constant. */ | |
9c2799c2 | 3987 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3988 | exp = &new_insn->tok[b_op->op_num]; |
3989 | set_expr_const (exp, b_op->op_data); | |
3990 | break; | |
3991 | ||
3992 | case OP_OPERAND: | |
9c2799c2 NC |
3993 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3994 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3995 | src_exp = &old_insn->tok[b_op->op_data]; |
3996 | exp = &new_insn->tok[b_op->op_num]; | |
3997 | copy_expr (exp, src_exp); | |
3998 | break; | |
3999 | ||
4000 | case OP_LITERAL: | |
4001 | case OP_LABEL: | |
4002 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 4003 | gas_assert (0); |
e0001a05 NC |
4004 | |
4005 | default: | |
4006 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 4007 | gas_assert (0); |
e0001a05 NC |
4008 | } |
4009 | } | |
4010 | ||
4011 | new_insn->ntok = num_ops; | |
5b7c81bd | 4012 | return false; |
e0001a05 NC |
4013 | } |
4014 | ||
4015 | ||
43cd72b9 | 4016 | /* Return TRUE if it was simplified. */ |
e0001a05 | 4017 | |
5b7c81bd | 4018 | static bool |
7fa3d080 | 4019 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) |
e0001a05 | 4020 | { |
43cd72b9 | 4021 | TransitionRule *rule; |
e0001a05 | 4022 | BuildInstr *insn_spec; |
43cd72b9 BW |
4023 | |
4024 | if (old_insn->is_specific_opcode || !density_supported) | |
5b7c81bd | 4025 | return false; |
43cd72b9 BW |
4026 | |
4027 | rule = xg_instruction_match (old_insn); | |
e0001a05 | 4028 | if (rule == NULL) |
5b7c81bd | 4029 | return false; |
e0001a05 NC |
4030 | |
4031 | insn_spec = rule->to_instr; | |
4032 | /* There should only be one. */ | |
9c2799c2 NC |
4033 | gas_assert (insn_spec != NULL); |
4034 | gas_assert (insn_spec->next == NULL); | |
e0001a05 | 4035 | if (insn_spec->next != NULL) |
5b7c81bd | 4036 | return false; |
e0001a05 NC |
4037 | |
4038 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
4039 | ||
5b7c81bd | 4040 | return true; |
e0001a05 NC |
4041 | } |
4042 | ||
4043 | ||
4044 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
4045 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
4046 | tokens into the stack or relax it and place multiple |
4047 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 | 4048 | |
5b7c81bd | 4049 | static bool |
7fa3d080 | 4050 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
4051 | { |
4052 | int noperands; | |
4053 | TInsn new_insn; | |
5b7c81bd | 4054 | bool do_expand; |
7c834684 | 4055 | |
60242db2 | 4056 | tinsn_init (&new_insn); |
e0001a05 | 4057 | |
43cd72b9 BW |
4058 | /* Narrow it if we can. xg_simplify_insn now does all the |
4059 | appropriate checking (e.g., for the density option). */ | |
4060 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
4061 | orig_insn = &new_insn; | |
e0001a05 | 4062 | |
43cd72b9 BW |
4063 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
4064 | orig_insn->opcode); | |
e0001a05 NC |
4065 | if (orig_insn->ntok < noperands) |
4066 | { | |
992a06ee AM |
4067 | as_bad (ngettext ("found %d operand for '%s': Expected %d", |
4068 | "found %d operands for '%s': Expected %d", | |
4069 | orig_insn->ntok), | |
e0001a05 NC |
4070 | orig_insn->ntok, |
4071 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4072 | noperands); | |
5b7c81bd | 4073 | return true; |
e0001a05 NC |
4074 | } |
4075 | if (orig_insn->ntok > noperands) | |
992a06ee AM |
4076 | as_warn (ngettext ("found %d operand for '%s': Expected %d", |
4077 | "found %d operands for '%s': Expected %d", | |
4078 | orig_insn->ntok), | |
e0001a05 NC |
4079 | orig_insn->ntok, |
4080 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4081 | noperands); | |
4082 | ||
43cd72b9 | 4083 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 4084 | are too many, just cut out the extras here. */ |
e0001a05 NC |
4085 | orig_insn->ntok = noperands; |
4086 | ||
e0001a05 | 4087 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
5b7c81bd | 4088 | return true; |
e0001a05 | 4089 | |
d12f9798 BW |
4090 | /* Special case for extui opcode which has constraints not handled |
4091 | by the ordinary operand encoding checks. The number of operands | |
4092 | and related syntax issues have already been checked. */ | |
4093 | if (orig_insn->opcode == xtensa_extui_opcode) | |
4094 | { | |
4095 | int shiftimm = orig_insn->tok[2].X_add_number; | |
4096 | int maskimm = orig_insn->tok[3].X_add_number; | |
4097 | if (shiftimm + maskimm > 32) | |
4098 | { | |
4099 | as_bad (_("immediate operands sum to greater than 32")); | |
5b7c81bd | 4100 | return true; |
d12f9798 BW |
4101 | } |
4102 | } | |
4103 | ||
7c834684 BW |
4104 | /* If the instruction will definitely need to be relaxed, it is better |
4105 | to expand it now for better scheduling. Decide whether to expand | |
4106 | now.... */ | |
4107 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
4108 | ||
4109 | /* Calls should be expanded to longcalls only in the backend relaxation | |
4110 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
4111 | adjacent. */ | |
4112 | if (is_direct_call_opcode (orig_insn->opcode)) | |
5b7c81bd | 4113 | do_expand = false; |
e0001a05 NC |
4114 | |
4115 | if (tinsn_has_symbolic_operands (orig_insn)) | |
4116 | { | |
7c834684 BW |
4117 | /* The values of symbolic operands are not known yet, so only expand |
4118 | now if an operand is "complex" (e.g., difference of symbols) and | |
4119 | will have to be stored as a literal regardless of the value. */ | |
4120 | if (!tinsn_has_complex_operands (orig_insn)) | |
5b7c81bd | 4121 | do_expand = false; |
e0001a05 | 4122 | } |
7c834684 | 4123 | else if (xg_immeds_fit (orig_insn)) |
5b7c81bd | 4124 | do_expand = false; |
7c834684 BW |
4125 | |
4126 | if (do_expand) | |
4127 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4128 | else |
7c834684 | 4129 | istack_push (istack, orig_insn); |
e0001a05 | 4130 | |
5b7c81bd | 4131 | return false; |
e0001a05 NC |
4132 | } |
4133 | ||
4134 | ||
7fa3d080 | 4135 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4136 | or the name is .gnu.linkonce.*. */ |
4137 | ||
4138 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 | 4139 | |
5b7c81bd | 4140 | static bool |
7fa3d080 BW |
4141 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) |
4142 | { | |
4143 | flagword flags, link_once_flags; | |
4144 | ||
fd361982 | 4145 | flags = bfd_section_flags (sec); |
7fa3d080 BW |
4146 | link_once_flags = (flags & SEC_LINK_ONCE); |
4147 | ||
4148 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4149 | if (!link_once_flags |
4150 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4151 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4152 | |
7fa3d080 BW |
4153 | return (link_once_flags != 0); |
4154 | } | |
4155 | ||
4156 | ||
4157 | static void | |
4158 | xtensa_add_literal_sym (symbolS *sym) | |
4159 | { | |
4160 | sym_list *l; | |
4161 | ||
325801bd | 4162 | l = XNEW (sym_list); |
7fa3d080 BW |
4163 | l->sym = sym; |
4164 | l->next = literal_syms; | |
4165 | literal_syms = l; | |
4166 | } | |
4167 | ||
4168 | ||
4169 | static symbolS * | |
4170 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4171 | { | |
4172 | static int lit_num = 0; | |
4173 | static char name[256]; | |
4174 | symbolS *symbolP; | |
4175 | ||
4176 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4177 | ||
4178 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4179 | be careful to make sure that if it is used in a relocation that the | |
4180 | symbol will be in the output file. */ | |
4181 | if (get_is_linkonce_section (stdoutput, sec)) | |
4182 | { | |
e01e1cee | 4183 | symbolP = symbol_new (name, sec, frag, 0); |
7fa3d080 BW |
4184 | S_CLEAR_EXTERNAL (symbolP); |
4185 | /* symbolP->local = 1; */ | |
4186 | } | |
4187 | else | |
e01e1cee | 4188 | symbolP = symbol_new (name, sec, frag, 0); |
7fa3d080 BW |
4189 | |
4190 | xtensa_add_literal_sym (symbolP); | |
4191 | ||
7fa3d080 BW |
4192 | lit_num++; |
4193 | return symbolP; | |
4194 | } | |
4195 | ||
4196 | ||
e0001a05 NC |
4197 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4198 | ||
7fa3d080 BW |
4199 | static symbolS * |
4200 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4201 | { |
4202 | emit_state state; | |
4203 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4204 | bfd_reloc_code_real_type reloc; |
5b7c81bd | 4205 | bool pcrel = false; |
bbdd25a8 | 4206 | char *p; |
e0001a05 NC |
4207 | |
4208 | /* size = 4 for L32R. It could easily be larger when we move to | |
4209 | larger constants. Add a parameter later. */ | |
4210 | offsetT litsize = 4; | |
4211 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4212 | expressionS saved_loc; | |
43cd72b9 BW |
4213 | expressionS * emit_val; |
4214 | ||
e0001a05 NC |
4215 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4216 | ||
9c2799c2 NC |
4217 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4218 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4219 | |
4220 | xtensa_switch_to_literal_fragment (&state); | |
4221 | ||
43cd72b9 BW |
4222 | emit_val = &insn->tok[0]; |
4223 | if (emit_val->X_op == O_big) | |
4224 | { | |
4225 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4226 | if (size > litsize) | |
4227 | { | |
4228 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4229 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4230 | _("invalid immediate")); |
4231 | xtensa_restore_emit_state (&state); | |
4232 | return NULL; | |
4233 | } | |
4234 | } | |
4235 | ||
e0001a05 NC |
4236 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4237 | literals done with this function have a frag to themselves. That's | |
4238 | important for the way text section literals work. */ | |
4239 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4240 | record_alignment (now_seg, litalign); |
e0001a05 | 4241 | |
bbdd25a8 | 4242 | switch (emit_val->X_op) |
43cd72b9 | 4243 | { |
1bbb5f21 | 4244 | case O_pcrel: |
5b7c81bd | 4245 | pcrel = true; |
1bbb5f21 | 4246 | /* fall through */ |
bbdd25a8 | 4247 | case O_pltrel: |
28dbbc02 BW |
4248 | case O_tlsfunc: |
4249 | case O_tlsarg: | |
4250 | case O_tpoff: | |
4251 | case O_dtpoff: | |
bbdd25a8 | 4252 | p = frag_more (litsize); |
43cd72b9 | 4253 | xtensa_set_frag_assembly_state (frag_now); |
5b7c81bd | 4254 | reloc = map_operator_to_reloc (emit_val->X_op, true); |
43cd72b9 BW |
4255 | if (emit_val->X_add_symbol) |
4256 | emit_val->X_op = O_symbol; | |
4257 | else | |
4258 | emit_val->X_op = O_constant; | |
4259 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4260 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4261 | break; |
4262 | ||
4263 | default: | |
4264 | emit_expr (emit_val, litsize); | |
4265 | break; | |
43cd72b9 | 4266 | } |
e0001a05 | 4267 | |
9c2799c2 | 4268 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4269 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4270 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4271 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4272 | |
4273 | /* Go back. */ | |
4274 | xtensa_restore_emit_state (&state); | |
4275 | return lit_sym; | |
4276 | } | |
4277 | ||
4278 | ||
4279 | static void | |
7fa3d080 | 4280 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4281 | { |
4282 | emit_state state; | |
43cd72b9 | 4283 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4284 | takes effect if something is placed here. */ |
4285 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4286 | fragS *lit_saved_frag; | |
4287 | ||
9c2799c2 | 4288 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4289 | |
4290 | xtensa_switch_to_literal_fragment (&state); | |
4291 | ||
4292 | /* Force a 4-byte align here. */ | |
4293 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4294 | record_alignment (now_seg, litalign); |
e0001a05 | 4295 | |
542f8b94 | 4296 | frag_grow (size); |
e0001a05 NC |
4297 | |
4298 | lit_saved_frag = frag_now; | |
4299 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4300 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
5b7c81bd | 4301 | xg_finish_frag (0, RELAX_LITERAL, 0, size, false); |
e0001a05 NC |
4302 | |
4303 | /* Go back. */ | |
4304 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4305 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4306 | } |
4307 | ||
4308 | ||
e0001a05 | 4309 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4310 | Return TRUE on success. */ |
e0001a05 | 4311 | |
5b7c81bd | 4312 | static bool |
7fa3d080 BW |
4313 | xg_add_opcode_fix (TInsn *tinsn, |
4314 | int opnum, | |
4315 | xtensa_format fmt, | |
4316 | int slot, | |
91d6fa6a | 4317 | expressionS *exp, |
7fa3d080 BW |
4318 | fragS *fragP, |
4319 | offsetT offset) | |
43cd72b9 BW |
4320 | { |
4321 | xtensa_opcode opcode = tinsn->opcode; | |
4322 | bfd_reloc_code_real_type reloc; | |
4323 | reloc_howto_type *howto; | |
4324 | int fmt_length; | |
e0001a05 NC |
4325 | fixS *the_fix; |
4326 | ||
43cd72b9 BW |
4327 | reloc = BFD_RELOC_NONE; |
4328 | ||
4329 | /* First try the special cases for "alternate" relocs. */ | |
4330 | if (opcode == xtensa_l32r_opcode) | |
4331 | { | |
4332 | if (fragP->tc_frag_data.use_absolute_literals) | |
4333 | reloc = encode_alt_reloc (slot); | |
4334 | } | |
4335 | else if (opcode == xtensa_const16_opcode) | |
4336 | { | |
91d6fa6a | 4337 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4338 | { |
4339 | reloc = encode_reloc (slot); | |
91d6fa6a | 4340 | exp->X_op = O_symbol; |
43cd72b9 | 4341 | } |
91d6fa6a | 4342 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4343 | { |
4344 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4345 | exp->X_op = O_symbol; |
43cd72b9 BW |
4346 | } |
4347 | } | |
4348 | ||
4349 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4350 | { |
43cd72b9 | 4351 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4352 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
5b7c81bd | 4353 | return false; |
e0001a05 NC |
4354 | } |
4355 | ||
43cd72b9 BW |
4356 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4357 | into the symbol table where the generic portions of the assembler | |
4358 | won't know what to do with them. */ | |
91d6fa6a | 4359 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4360 | { |
4361 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4362 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
5b7c81bd | 4363 | return false; |
43cd72b9 BW |
4364 | } |
4365 | ||
4366 | /* Next try the generic relocs. */ | |
4367 | if (reloc == BFD_RELOC_NONE) | |
4368 | reloc = encode_reloc (slot); | |
4369 | if (reloc == BFD_RELOC_NONE) | |
4370 | { | |
4371 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
5b7c81bd | 4372 | return false; |
43cd72b9 | 4373 | } |
e0001a05 | 4374 | |
43cd72b9 | 4375 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4376 | if (!howto) |
4377 | { | |
43cd72b9 | 4378 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 | 4379 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
5b7c81bd | 4380 | return false; |
e0001a05 NC |
4381 | } |
4382 | ||
43cd72b9 | 4383 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4384 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4385 | howto->pc_relative, reloc); |
d9740523 | 4386 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4387 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4388 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4389 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4390 | |
5b7c81bd | 4391 | return true; |
7fa3d080 BW |
4392 | } |
4393 | ||
4394 | ||
5b7c81bd | 4395 | static bool |
7fa3d080 | 4396 | xg_emit_insn_to_buf (TInsn *tinsn, |
7fa3d080 BW |
4397 | char *buf, |
4398 | fragS *fragP, | |
4399 | offsetT offset, | |
5b7c81bd | 4400 | bool build_fix) |
7fa3d080 BW |
4401 | { |
4402 | static xtensa_insnbuf insnbuf = NULL; | |
5b7c81bd AM |
4403 | bool has_symbolic_immed = false; |
4404 | bool ok = true; | |
b2d179be | 4405 | |
7fa3d080 BW |
4406 | if (!insnbuf) |
4407 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4408 | ||
4409 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4410 | if (has_symbolic_immed && build_fix) | |
4411 | { | |
4412 | /* Add a fixup. */ | |
b2d179be BW |
4413 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4414 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4415 | int opnum = get_relaxable_immed (tinsn->opcode); |
4416 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4417 | |
b2d179be | 4418 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
5b7c81bd | 4419 | ok = false; |
7fa3d080 | 4420 | } |
5b7c81bd | 4421 | fragP->tc_frag_data.is_insn = true; |
d77b99c9 BW |
4422 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4423 | (unsigned char *) buf, 0); | |
7fa3d080 | 4424 | return ok; |
e0001a05 NC |
4425 | } |
4426 | ||
4427 | ||
7fa3d080 BW |
4428 | static void |
4429 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4430 | { |
4431 | symbolS *sym = get_special_literal_symbol (); | |
4432 | int i; | |
4433 | if (lit_sym == 0) | |
4434 | return; | |
9c2799c2 | 4435 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4436 | for (i = 0; i < insn->ntok; i++) |
4437 | if (insn->tok[i].X_add_symbol == sym) | |
4438 | insn->tok[i].X_add_symbol = lit_sym; | |
4439 | ||
4440 | } | |
4441 | ||
4442 | ||
7fa3d080 BW |
4443 | static void |
4444 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4445 | { |
4446 | symbolS *sym = get_special_label_symbol (); | |
4447 | int i; | |
e0001a05 NC |
4448 | for (i = 0; i < insn->ntok; i++) |
4449 | if (insn->tok[i].X_add_symbol == sym) | |
4450 | insn->tok[i].X_add_symbol = label_sym; | |
4451 | ||
4452 | } | |
4453 | ||
4454 | ||
43cd72b9 | 4455 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4456 | integer register. */ |
4457 | ||
5b7c81bd | 4458 | static bool |
7fa3d080 | 4459 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4460 | { |
4461 | int i; | |
4462 | int num_ops; | |
4463 | xtensa_isa isa = xtensa_default_isa; | |
4464 | ||
43cd72b9 | 4465 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4466 | |
4467 | for (i = 0; i < num_ops; i++) | |
4468 | { | |
43cd72b9 BW |
4469 | char inout; |
4470 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4471 | if ((inout == 'o' || inout == 'm') | |
4472 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4473 | { |
43cd72b9 BW |
4474 | xtensa_regfile opnd_rf = |
4475 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4476 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4477 | { |
4478 | if ((insn->tok[i].X_op == O_register) | |
4479 | && (insn->tok[i].X_add_number == regnum)) | |
5b7c81bd | 4480 | return true; |
e0001a05 NC |
4481 | } |
4482 | } | |
4483 | } | |
5b7c81bd | 4484 | return false; |
e0001a05 NC |
4485 | } |
4486 | ||
4487 | ||
5b7c81bd | 4488 | static bool |
7fa3d080 | 4489 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4490 | { |
4491 | xtensa_opcode opcode = tinsn->opcode; | |
4492 | ||
4493 | if (opcode == XTENSA_UNDEFINED) | |
5b7c81bd | 4494 | return false; |
e0001a05 NC |
4495 | |
4496 | if (opcode == xtensa_call0_opcode | |
4497 | || opcode == xtensa_callx0_opcode | |
4498 | || opcode == xtensa_call4_opcode | |
4499 | || opcode == xtensa_callx4_opcode | |
4500 | || opcode == xtensa_call8_opcode | |
4501 | || opcode == xtensa_callx8_opcode | |
4502 | || opcode == xtensa_call12_opcode | |
4503 | || opcode == xtensa_callx12_opcode | |
4504 | || opcode == xtensa_isync_opcode | |
4505 | || opcode == xtensa_ret_opcode | |
4506 | || opcode == xtensa_ret_n_opcode | |
4507 | || opcode == xtensa_retw_opcode | |
4508 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4509 | || opcode == xtensa_waiti_opcode |
4510 | || opcode == xtensa_rsr_lcount_opcode) | |
5b7c81bd | 4511 | return true; |
c138bc38 | 4512 | |
5b7c81bd | 4513 | return false; |
e0001a05 NC |
4514 | } |
4515 | ||
4516 | ||
4517 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4518 | This allows the debugger to add unaligned labels. | |
4519 | Also, the assembler generates stabs labels that need | |
4520 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4521 | ||
5b7c81bd | 4522 | static bool |
7fa3d080 | 4523 | is_unaligned_label (symbolS *sym) |
e0001a05 NC |
4524 | { |
4525 | const char *name = S_GET_NAME (sym); | |
4526 | static size_t fake_size = 0; | |
4527 | ||
4528 | if (name | |
4529 | && name[0] == '.' | |
4530 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
5b7c81bd | 4531 | return true; |
e0001a05 NC |
4532 | |
4533 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4534 | if (fake_size == 0) | |
4535 | fake_size = strlen (FAKE_LABEL_NAME); | |
4536 | ||
43cd72b9 | 4537 | if (name |
e0001a05 NC |
4538 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4539 | && (name[fake_size] == 'F' | |
4540 | || name[fake_size] == 'L' | |
4541 | || (name[fake_size] == 'e' | |
d34049e8 | 4542 | && startswith (name + fake_size, "endfunc")))) |
5b7c81bd | 4543 | return true; |
e0001a05 | 4544 | |
5b7c81bd | 4545 | return false; |
e0001a05 NC |
4546 | } |
4547 | ||
4548 | ||
7fa3d080 BW |
4549 | static fragS * |
4550 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4551 | { |
4552 | fragS *next_fragP = fragP->fr_next; | |
4553 | ||
c138bc38 | 4554 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4555 | So we have to skip until we find something legit. */ |
4556 | while (next_fragP && next_fragP->fr_fix == 0) | |
4557 | next_fragP = next_fragP->fr_next; | |
4558 | ||
4559 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4560 | return NULL; | |
4561 | ||
4562 | return next_fragP; | |
4563 | } | |
4564 | ||
4565 | ||
5b7c81bd | 4566 | static bool |
7fa3d080 | 4567 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4568 | { |
4569 | xtensa_opcode out_opcode; | |
4570 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4571 | ||
4572 | if (next_fragP == NULL) | |
5b7c81bd | 4573 | return false; |
43cd72b9 BW |
4574 | |
4575 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4576 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4577 | { | |
4578 | *opcode = out_opcode; | |
5b7c81bd | 4579 | return true; |
43cd72b9 | 4580 | } |
5b7c81bd | 4581 | return false; |
43cd72b9 BW |
4582 | } |
4583 | ||
4584 | ||
4585 | static int | |
7fa3d080 | 4586 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4587 | { |
e0001a05 NC |
4588 | static xtensa_insnbuf insnbuf = NULL; |
4589 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4590 | xtensa_format fmt; |
c138bc38 | 4591 | int fmt_size; |
e0001a05 NC |
4592 | |
4593 | if (!insnbuf) | |
4594 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4595 | ||
43cd72b9 BW |
4596 | if (fragP == NULL) |
4597 | return XTENSA_UNDEFINED; | |
4598 | ||
d77b99c9 BW |
4599 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4600 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4601 | |
4602 | fmt = xtensa_format_decode (isa, insnbuf); | |
4603 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4604 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4605 | fmt_size = xtensa_format_length (isa, fmt); |
4606 | ||
4607 | /* If the next format won't be changing due to relaxation, just | |
4608 | return the length of the first format. */ | |
4609 | if (fragP->fr_opcode != fragP->fr_literal) | |
4610 | return fmt_size; | |
4611 | ||
c138bc38 | 4612 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4613 | multi-slot instruction, we will return the more conservative |
4614 | number. This works because alignment on bigger instructions | |
4615 | is more restrictive than alignment on smaller instructions. | |
4616 | This is more conservative than we would like, but it happens | |
4617 | infrequently. */ | |
4618 | ||
4619 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4620 | return fmt_size; | |
4621 | ||
4622 | /* If we aren't doing one of our own relaxations or it isn't | |
4623 | slot-based, then the insn size won't change. */ | |
4624 | if (fragP->fr_type != rs_machine_dependent) | |
4625 | return fmt_size; | |
4626 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4627 | return fmt_size; | |
4628 | ||
4629 | /* If an instruction is about to grow, return the longer size. */ | |
4630 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4631 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4632 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4633 | { |
4634 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4635 | instruction in the relaxed version is of length 3. (The case | |
4636 | where we have to pull the instruction out of a FLIX bundle | |
4637 | is handled conservatively above.) However, frags with opcodes | |
4638 | that are expanding to wide branches end up having formats that | |
4639 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4640 | we can't tell directly what format the relaxer picked. This | |
4641 | is a wart in the design of the relaxer that should someday be | |
4642 | fixed, but would require major changes, or at least should | |
4643 | be accompanied by major changes to make use of that data. | |
4644 | ||
4645 | In any event, we can tell that we are expanding from a single-slot | |
19ef5f3d | 4646 | format to a wider one with the logic below. */ |
def13efb | 4647 | |
19ef5f3d SA |
4648 | int i; |
4649 | int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; | |
4650 | ||
4651 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) | |
4652 | { | |
4653 | if (relaxed_size == xtensa_format_length (isa, i)) | |
4654 | return relaxed_size; | |
4655 | } | |
4656 | ||
4657 | return 3; | |
def13efb | 4658 | } |
c138bc38 | 4659 | |
43cd72b9 BW |
4660 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4661 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4662 | |
43cd72b9 | 4663 | return fmt_size; |
e0001a05 NC |
4664 | } |
4665 | ||
4666 | ||
7fa3d080 BW |
4667 | static int |
4668 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4669 | { |
7fa3d080 BW |
4670 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4671 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4672 | } |
4673 | ||
4674 | ||
03aaa593 BW |
4675 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4676 | required two-byte instructions to be treated as three-byte instructions | |
4677 | for loop instruction alignment. This restriction was removed beginning | |
4678 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4679 | is that the first instruction of the loop must appear at an address that | |
4680 | does not cross a fetch boundary. */ | |
4681 | ||
4682 | static int | |
4683 | get_loop_align_size (int insn_size) | |
4684 | { | |
4685 | if (insn_size == XTENSA_UNDEFINED) | |
4686 | return xtensa_fetch_width; | |
4687 | ||
4688 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4689 | return 3; | |
4690 | ||
4691 | return insn_size; | |
4692 | } | |
4693 | ||
4694 | ||
e0001a05 NC |
4695 | /* If the next legit fragment is an end-of-loop marker, |
4696 | switch its state so it will instantiate a NOP. */ | |
4697 | ||
4698 | static void | |
1d19a770 | 4699 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4700 | { |
4701 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4702 | fragS *new_target = NULL; |
e0001a05 | 4703 | |
7b1cc377 | 4704 | if (align_targets) |
43cd72b9 BW |
4705 | { |
4706 | /* We are guaranteed there will be one of these... */ | |
4707 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4708 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4709 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4710 | next_fragP = next_fragP->fr_next; | |
4711 | ||
9c2799c2 | 4712 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4713 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4714 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4715 | ||
4716 | /* ...and one of these. */ | |
4717 | new_target = next_fragP->fr_next; | |
4718 | while (!(new_target->fr_type == rs_machine_dependent | |
4719 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4720 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4721 | new_target = new_target->fr_next; | |
4722 | ||
9c2799c2 | 4723 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4724 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4725 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4726 | } | |
43cd72b9 | 4727 | |
1d19a770 | 4728 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4729 | { |
1d19a770 BW |
4730 | if (next_fragP->fr_type == rs_machine_dependent |
4731 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4732 | { |
1d19a770 BW |
4733 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4734 | return; | |
e0001a05 | 4735 | } |
1d19a770 BW |
4736 | |
4737 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4738 | } |
4739 | } | |
4740 | ||
4741 | ||
5b7c81bd | 4742 | static bool |
7fa3d080 | 4743 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4744 | { |
43cd72b9 | 4745 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4746 | so we have to skip until we find something legit. */ |
4747 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4748 | { | |
4749 | if (fragP->tc_frag_data.is_branch_target) | |
5b7c81bd | 4750 | return true; |
e0001a05 NC |
4751 | if (fragP->fr_fix != 0) |
4752 | break; | |
4753 | } | |
5b7c81bd | 4754 | return false; |
e0001a05 NC |
4755 | } |
4756 | ||
4757 | ||
5b7c81bd | 4758 | static bool |
7fa3d080 | 4759 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4760 | { |
c138bc38 | 4761 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4762 | So we have to skip until we find something legit. */ |
4763 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4764 | { | |
4765 | if (fragP->tc_frag_data.is_loop_target) | |
5b7c81bd | 4766 | return true; |
e0001a05 NC |
4767 | if (fragP->fr_fix != 0) |
4768 | break; | |
4769 | } | |
5b7c81bd | 4770 | return false; |
e0001a05 NC |
4771 | } |
4772 | ||
4773 | ||
3a1e9c4a SA |
4774 | /* As specified in the relaxation table, when a loop instruction is |
4775 | relaxed, there are 24 bytes between the loop instruction itself and | |
4776 | the first instruction in the loop. */ | |
4777 | ||
4778 | #define RELAXED_LOOP_INSN_BYTES 24 | |
4779 | ||
e0001a05 | 4780 | static addressT |
7fa3d080 | 4781 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4782 | { |
4783 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4784 | xtensa_opcode next_opcode; |
e0001a05 | 4785 | |
43cd72b9 | 4786 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4787 | return 0; |
4788 | ||
43cd72b9 BW |
4789 | /* Sometimes an empty will end up here due to storage allocation issues, |
4790 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4791 | while (next_fragp->fr_fix == 0) |
4792 | next_fragp = next_fragp->fr_next; | |
4793 | ||
4794 | if (next_fragp->fr_type != rs_machine_dependent) | |
4795 | return 0; | |
4796 | ||
4797 | /* There is some implicit knowledge encoded in here. | |
4798 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4799 | been relaxed. Note that we can assume that the LOOP |
4800 | instruction is in slot 0 because loops aren't bundleable. */ | |
4801 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
3a1e9c4a | 4802 | return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; |
e0001a05 NC |
4803 | |
4804 | return 0; | |
4805 | } | |
4806 | ||
4807 | ||
4808 | /* Mark a location where we can later insert literal frags. Update | |
4809 | the section's literal_pool_loc, so subsequent literals can be | |
4810 | placed nearest to their use. */ | |
4811 | ||
4812 | static void | |
7fa3d080 | 4813 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4814 | { |
4815 | /* Any labels pointing to the current location need | |
4816 | to be adjusted to after the literal pool. */ | |
e0001a05 | 4817 | fragS *pool_location; |
e0001a05 | 4818 | |
1f2a7e38 | 4819 | if (use_literal_section) |
43cd72b9 BW |
4820 | return; |
4821 | ||
dd49a749 BW |
4822 | /* We stash info in these frags so we can later move the literal's |
4823 | fixes into this frchain's fix list. */ | |
e0001a05 | 4824 | pool_location = frag_now; |
dd49a749 | 4825 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4826 | frag_now->tc_frag_data.literal_frag = frag_now; |
b46824bd | 4827 | /* Just record this frag. */ |
5b7c81bd | 4828 | xtensa_maybe_create_literal_pool_frag (false, false); |
dd49a749 | 4829 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4830 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4831 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4832 | frag_now->tc_frag_data.lit_seg = now_seg; |
4833 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4834 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4835 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 4836 | |
e0001a05 | 4837 | set_literal_pool_location (now_seg, pool_location); |
e0001a05 NC |
4838 | } |
4839 | ||
4840 | ||
43cd72b9 BW |
4841 | /* Build a nop of the correct size into tinsn. */ |
4842 | ||
4843 | static void | |
7fa3d080 | 4844 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4845 | { |
4846 | tinsn_init (tinsn); | |
4847 | switch (size) | |
4848 | { | |
4849 | case 2: | |
4850 | tinsn->opcode = xtensa_nop_n_opcode; | |
4851 | tinsn->ntok = 0; | |
4852 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4853 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4854 | break; | |
4855 | ||
4856 | case 3: | |
4857 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4858 | { | |
4859 | tinsn->opcode = xtensa_or_opcode; | |
4860 | set_expr_const (&tinsn->tok[0], 1); | |
4861 | set_expr_const (&tinsn->tok[1], 1); | |
4862 | set_expr_const (&tinsn->tok[2], 1); | |
4863 | tinsn->ntok = 3; | |
4864 | } | |
4865 | else | |
4866 | tinsn->opcode = xtensa_nop_opcode; | |
4867 | ||
9c2799c2 | 4868 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4869 | } |
4870 | } | |
4871 | ||
4872 | ||
e0001a05 NC |
4873 | /* Assemble a NOP of the requested size in the buffer. User must have |
4874 | allocated "buf" with at least "size" bytes. */ | |
4875 | ||
7fa3d080 | 4876 | static void |
d77b99c9 | 4877 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4878 | { |
4879 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4880 | TInsn tinsn; |
e0001a05 | 4881 | |
43cd72b9 | 4882 | build_nop (&tinsn, size); |
e0001a05 | 4883 | |
43cd72b9 BW |
4884 | if (!insnbuf) |
4885 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4886 | |
43cd72b9 | 4887 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4888 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4889 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4890 | } |
4891 | ||
4892 | ||
4893 | /* Return the number of bytes for the offset of the expanded loop | |
4894 | instruction. This should be incorporated into the relaxation | |
4895 | specification but is hard-coded here. This is used to auto-align | |
4896 | the loop instruction. It is invalid to call this function if the | |
4897 | configuration does not have loops or if the opcode is not a loop | |
4898 | opcode. */ | |
4899 | ||
4900 | static addressT | |
7fa3d080 | 4901 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4902 | { |
4903 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4904 | This MUST correspond directly to the specification of the loop | |
4905 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4906 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4907 | if (opcode == xtensa_loop_opcode) |
4908 | return 0; | |
4909 | if (opcode == xtensa_loopnez_opcode) | |
4910 | return 3; | |
4911 | if (opcode == xtensa_loopgtz_opcode) | |
4912 | return 6; | |
4913 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4914 | return 0; | |
4915 | } | |
4916 | ||
4917 | ||
7fa3d080 BW |
4918 | static fragS * |
4919 | get_literal_pool_location (segT seg) | |
e0001a05 | 4920 | { |
f8aecf3c | 4921 | if (auto_litpools) |
b46824bd | 4922 | { |
f8aecf3c MF |
4923 | struct litpool_seg *lps = litpool_seg_list.next; |
4924 | struct litpool_frag *lpf; | |
4925 | for ( ; lps && lps->seg->id != seg->id; lps = lps->next) | |
4926 | ; | |
4927 | if (lps) | |
b46824bd | 4928 | { |
f8aecf3c MF |
4929 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) |
4930 | { /* Skip "candidates" for now. */ | |
4931 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
4932 | lpf->priority == 1) | |
4933 | return lpf->fragP; | |
4934 | } | |
4935 | /* Must convert a lower-priority pool. */ | |
4936 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4937 | { | |
4938 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
4939 | return lpf->fragP; | |
4940 | } | |
4941 | /* Still no match -- try for a low priority pool. */ | |
4942 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4943 | { | |
4944 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
4945 | return lpf->fragP; | |
4946 | } | |
b46824bd MF |
4947 | } |
4948 | } | |
e0001a05 NC |
4949 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; |
4950 | } | |
4951 | ||
4952 | ||
4953 | static void | |
7fa3d080 | 4954 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4955 | { |
4956 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4957 | } | |
4958 | ||
43cd72b9 BW |
4959 | |
4960 | /* Set frag assembly state should be called when a new frag is | |
4961 | opened and after a frag has been closed. */ | |
4962 | ||
7fa3d080 BW |
4963 | static void |
4964 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4965 | { |
4966 | if (!density_supported) | |
5b7c81bd | 4967 | fragP->tc_frag_data.is_no_density = true; |
43cd72b9 BW |
4968 | |
4969 | /* This function is called from subsegs_finish, which is called | |
ed2917de | 4970 | after xtensa_md_finish, so we can't use "use_transform" or |
43cd72b9 BW |
4971 | "use_schedule" here. */ |
4972 | if (!directive_state[directive_transform]) | |
5b7c81bd | 4973 | fragP->tc_frag_data.is_no_transform = true; |
7c834684 | 4974 | if (directive_state[directive_longcalls]) |
5b7c81bd | 4975 | fragP->tc_frag_data.use_longcalls = true; |
43cd72b9 BW |
4976 | fragP->tc_frag_data.use_absolute_literals = |
4977 | directive_state[directive_absolute_literals]; | |
5b7c81bd | 4978 | fragP->tc_frag_data.is_assembly_state_set = true; |
43cd72b9 BW |
4979 | } |
4980 | ||
4981 | ||
5b7c81bd | 4982 | static bool |
7fa3d080 | 4983 | relaxable_section (asection *sec) |
43cd72b9 | 4984 | { |
11ac2671 BW |
4985 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4986 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4987 | } |
4988 | ||
4989 | ||
99ded152 BW |
4990 | static void |
4991 | xtensa_mark_frags_for_org (void) | |
4992 | { | |
4993 | segT *seclist; | |
4994 | ||
4995 | /* Walk over each fragment of all of the current segments. If we find | |
4996 | a .org frag in any of the segments, mark all frags prior to it as | |
4997 | "no transform", which will prevent linker optimizations from messing | |
4998 | up the .org distance. This should be done after | |
4999 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
5000 | about that function trashing the data we save here. */ | |
5001 | ||
5002 | for (seclist = &stdoutput->sections; | |
5003 | seclist && *seclist; | |
5004 | seclist = &(*seclist)->next) | |
5005 | { | |
5006 | segT sec = *seclist; | |
5007 | segment_info_type *seginfo; | |
5008 | fragS *fragP; | |
5009 | flagword flags; | |
fd361982 | 5010 | flags = bfd_section_flags (sec); |
99ded152 BW |
5011 | if (flags & SEC_DEBUGGING) |
5012 | continue; | |
5013 | if (!(flags & SEC_ALLOC)) | |
5014 | continue; | |
5015 | ||
5016 | seginfo = seg_info (sec); | |
5017 | if (seginfo && seginfo->frchainP) | |
5018 | { | |
5019 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
5020 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5021 | fragP = fragP->fr_next) | |
5022 | { | |
5023 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
5024 | rs_fill, so use the value as cached in rs_subtype here. */ | |
5025 | if (fragP->fr_subtype == RELAX_ORG) | |
5026 | { | |
5027 | while (last_fragP != fragP->fr_next) | |
5028 | { | |
5b7c81bd | 5029 | last_fragP->tc_frag_data.is_no_transform = true; |
99ded152 BW |
5030 | last_fragP = last_fragP->fr_next; |
5031 | } | |
5032 | } | |
5033 | } | |
5034 | } | |
5035 | } | |
5036 | } | |
5037 | ||
5038 | ||
43cd72b9 | 5039 | static void |
7fa3d080 | 5040 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
5041 | { |
5042 | segT *seclist; | |
5043 | ||
5044 | /* Walk over each fragment of all of the current segments. For each | |
5045 | unmarked fragment, mark it with the same info as the previous | |
5046 | fragment. */ | |
5047 | for (seclist = &stdoutput->sections; | |
5048 | seclist && *seclist; | |
5049 | seclist = &(*seclist)->next) | |
5050 | { | |
5051 | segT sec = *seclist; | |
5052 | segment_info_type *seginfo; | |
5053 | fragS *fragP; | |
5054 | flagword flags; | |
fd361982 | 5055 | flags = bfd_section_flags (sec); |
43cd72b9 BW |
5056 | if (flags & SEC_DEBUGGING) |
5057 | continue; | |
5058 | if (!(flags & SEC_ALLOC)) | |
5059 | continue; | |
5060 | ||
5061 | seginfo = seg_info (sec); | |
5062 | if (seginfo && seginfo->frchainP) | |
5063 | { | |
5064 | fragS *last_fragP = 0; | |
5065 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5066 | fragP = fragP->fr_next) | |
5067 | { | |
5068 | if (fragP->fr_fix != 0 | |
5069 | && !fragP->tc_frag_data.is_assembly_state_set) | |
5070 | { | |
5071 | if (last_fragP == 0) | |
5072 | { | |
5073 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
5074 | _("assembly state not set for first frag in section %s"), | |
5075 | sec->name); | |
5076 | } | |
5077 | else | |
5078 | { | |
5b7c81bd | 5079 | fragP->tc_frag_data.is_assembly_state_set = true; |
43cd72b9 BW |
5080 | fragP->tc_frag_data.is_no_density = |
5081 | last_fragP->tc_frag_data.is_no_density; | |
5082 | fragP->tc_frag_data.is_no_transform = | |
5083 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
5084 | fragP->tc_frag_data.use_longcalls = |
5085 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
5086 | fragP->tc_frag_data.use_absolute_literals = |
5087 | last_fragP->tc_frag_data.use_absolute_literals; | |
5088 | } | |
5089 | } | |
5090 | if (fragP->tc_frag_data.is_assembly_state_set) | |
5091 | last_fragP = fragP; | |
5092 | } | |
5093 | } | |
5094 | } | |
5095 | } | |
5096 | ||
5097 | ||
5098 | static void | |
7fa3d080 BW |
5099 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
5100 | asection *sec, | |
5101 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 | 5102 | { |
fd361982 | 5103 | flagword flags = bfd_section_flags (sec); |
43cd72b9 BW |
5104 | segment_info_type *seginfo = seg_info (sec); |
5105 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 5106 | |
43cd72b9 | 5107 | if (flags & SEC_CODE) |
c138bc38 | 5108 | { |
43cd72b9 BW |
5109 | xtensa_isa isa = xtensa_default_isa; |
5110 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
5111 | while (frag != NULL) | |
5112 | { | |
5113 | if (frag->tc_frag_data.is_branch_target) | |
5114 | { | |
5115 | int op_size; | |
664df4e4 | 5116 | addressT branch_align, frag_addr; |
43cd72b9 BW |
5117 | xtensa_format fmt; |
5118 | ||
d77b99c9 BW |
5119 | xtensa_insnbuf_from_chars |
5120 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5121 | fmt = xtensa_format_decode (isa, insnbuf); |
5122 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
5123 | branch_align = 1 << branch_align_power (sec); |
5124 | frag_addr = frag->fr_address % branch_align; | |
5125 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
5126 | as_warn_where (frag->fr_file, frag->fr_line, |
5127 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 5128 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5129 | } |
5130 | frag = frag->fr_next; | |
5131 | } | |
5132 | xtensa_insnbuf_free (isa, insnbuf); | |
5133 | } | |
5134 | } | |
5135 | ||
5136 | ||
5137 | static void | |
7fa3d080 BW |
5138 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
5139 | asection *sec, | |
5140 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 | 5141 | { |
fd361982 | 5142 | flagword flags = bfd_section_flags (sec); |
43cd72b9 BW |
5143 | segment_info_type *seginfo = seg_info (sec); |
5144 | fragS *frag = seginfo->frchainP->frch_root; | |
5145 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 5146 | |
43cd72b9 | 5147 | if (flags & SEC_CODE) |
c138bc38 | 5148 | { |
43cd72b9 BW |
5149 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5150 | while (frag != NULL) | |
5151 | { | |
5152 | if (frag->tc_frag_data.is_first_loop_insn) | |
5153 | { | |
5154 | int op_size; | |
d77b99c9 | 5155 | addressT frag_addr; |
43cd72b9 BW |
5156 | xtensa_format fmt; |
5157 | ||
3c83b96e SA |
5158 | if (frag->fr_fix == 0) |
5159 | frag = next_non_empty_frag (frag); | |
3739860c | 5160 | |
3c83b96e SA |
5161 | if (frag) |
5162 | { | |
5163 | xtensa_insnbuf_from_chars | |
5164 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
5165 | fmt = xtensa_format_decode (isa, insnbuf); | |
5166 | op_size = xtensa_format_length (isa, fmt); | |
5167 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
3739860c | 5168 | |
3c83b96e SA |
5169 | if (frag_addr + op_size > xtensa_fetch_width) |
5170 | as_warn_where (frag->fr_file, frag->fr_line, | |
5171 | _("unaligned loop: %d bytes at 0x%lx"), | |
5172 | op_size, (long) frag->fr_address); | |
5173 | } | |
43cd72b9 BW |
5174 | } |
5175 | frag = frag->fr_next; | |
5176 | } | |
5177 | xtensa_insnbuf_free (isa, insnbuf); | |
5178 | } | |
5179 | } | |
5180 | ||
5181 | ||
30f725a1 BW |
5182 | static int |
5183 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5184 | { |
5185 | xtensa_isa isa = xtensa_default_isa; | |
5186 | static xtensa_insnbuf insnbuf = NULL; | |
5187 | static xtensa_insnbuf slotbuf = NULL; | |
5188 | xtensa_format fmt; | |
5189 | int slot; | |
5b7c81bd | 5190 | bool alt_reloc; |
43cd72b9 BW |
5191 | xtensa_opcode opcode; |
5192 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5193 | ||
1b6e95c2 BW |
5194 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5195 | || alt_reloc) | |
43cd72b9 BW |
5196 | as_fatal (_("unexpected fix")); |
5197 | ||
5198 | if (!insnbuf) | |
5199 | { | |
5200 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5201 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5202 | } | |
5203 | ||
d77b99c9 | 5204 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5205 | fmt = xtensa_format_decode (isa, insnbuf); |
5206 | if (fmt == XTENSA_UNDEFINED) | |
5207 | as_fatal (_("undecodable fix")); | |
5208 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5209 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5210 | if (opcode == XTENSA_UNDEFINED) | |
5211 | as_fatal (_("undecodable fix")); | |
5212 | ||
5213 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5214 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5215 | of a CONST16 operand. */ |
43cd72b9 | 5216 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5217 | return 0; |
43cd72b9 BW |
5218 | |
5219 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5220 | get_relaxable_immed (opcode), val, | |
5221 | fixP->fx_file, fixP->fx_line); | |
5222 | ||
5223 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5224 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5225 | |
5226 | return 1; | |
43cd72b9 BW |
5227 | } |
5228 | ||
e0001a05 NC |
5229 | \f |
5230 | /* External Functions and Other GAS Hooks. */ | |
5231 | ||
5232 | const char * | |
7fa3d080 | 5233 | xtensa_target_format (void) |
e0001a05 NC |
5234 | { |
5235 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5236 | } | |
5237 | ||
5238 | ||
5239 | void | |
7fa3d080 | 5240 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5241 | { |
5242 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5243 | } | |
5244 | ||
5245 | ||
5246 | void | |
7fa3d080 | 5247 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5248 | { |
5249 | if (target_big_endian) | |
5250 | number_to_chars_bigendian (buf, val, n); | |
5251 | else | |
5252 | number_to_chars_littleendian (buf, val, n); | |
5253 | } | |
5254 | ||
f7e16c2a MF |
5255 | static void |
5256 | xg_init_global_config (void) | |
5257 | { | |
5258 | target_big_endian = XCHAL_HAVE_BE; | |
5259 | ||
5260 | density_supported = XCHAL_HAVE_DENSITY; | |
5261 | absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; | |
5262 | xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; | |
5263 | ||
5264 | directive_state[directive_density] = XCHAL_HAVE_DENSITY; | |
5265 | directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; | |
935f1f4b MF |
5266 | |
5267 | microarch_earliest = XTENSA_MARCH_EARLIEST; | |
f7e16c2a MF |
5268 | } |
5269 | ||
5270 | void | |
5271 | xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) | |
5272 | { | |
5273 | xg_init_global_config (); | |
5274 | } | |
e0001a05 NC |
5275 | |
5276 | /* This function is called once, at assembler startup time. It should | |
5277 | set up all the tables, etc. that the MD part of the assembler will | |
5278 | need. */ | |
5279 | ||
5280 | void | |
7fa3d080 | 5281 | md_begin (void) |
e0001a05 NC |
5282 | { |
5283 | segT current_section = now_seg; | |
5284 | int current_subsec = now_subseg; | |
5285 | xtensa_isa isa; | |
62af60e2 | 5286 | int i; |
e0001a05 | 5287 | |
43cd72b9 | 5288 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5289 | isa = xtensa_default_isa; |
e0001a05 | 5290 | |
9632a526 | 5291 | linkrelax = opt_linkrelax; |
43cd72b9 | 5292 | |
74869ac7 | 5293 | /* Set up the literal sections. */ |
e0001a05 | 5294 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5295 | |
5296 | subseg_set (current_section, current_subsec); | |
5297 | ||
5298 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5299 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5300 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5301 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5302 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5303 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5304 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5305 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5306 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5307 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5308 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5309 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5310 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5311 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5312 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5313 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5314 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5315 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5316 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5317 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5318 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5319 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5320 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5321 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5322 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5323 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5324 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5325 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5326 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5327 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5328 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5329 | |
3739860c | 5330 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
62af60e2 SA |
5331 | { |
5332 | int format_slots = xtensa_format_num_slots (isa, i); | |
5333 | if (format_slots > config_max_slots) | |
5334 | config_max_slots = format_slots; | |
5335 | } | |
5336 | ||
5337 | xg_init_vinsn (&cur_vinsn); | |
5338 | ||
77cba8a3 BW |
5339 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5340 | ||
43cd72b9 BW |
5341 | init_op_placement_info_table (); |
5342 | ||
5343 | /* Set up the assembly state. */ | |
5344 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5345 | xtensa_set_frag_assembly_state (frag_now); | |
54879176 MF |
5346 | |
5347 | if (!use_literal_section) | |
5348 | xtensa_mark_literal_pool_location (); | |
43cd72b9 BW |
5349 | } |
5350 | ||
5351 | ||
5352 | /* TC_INIT_FIX_DATA hook */ | |
5353 | ||
5354 | void | |
7fa3d080 | 5355 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5356 | { |
5357 | x->tc_fix_data.slot = 0; | |
5358 | x->tc_fix_data.X_add_symbol = NULL; | |
5359 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5360 | } |
5361 | ||
5362 | ||
5363 | /* tc_frob_label hook */ | |
5364 | ||
5365 | void | |
7fa3d080 | 5366 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5367 | { |
3ea38ac2 BW |
5368 | float freq; |
5369 | ||
5370 | if (cur_vinsn.inside_bundle) | |
5371 | { | |
5372 | as_bad (_("labels are not valid inside bundles")); | |
5373 | return; | |
5374 | } | |
5375 | ||
5376 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5377 | |
43cd72b9 BW |
5378 | /* Since the label was already attached to a frag associated with the |
5379 | previous basic block, it now needs to be reset to the current frag. */ | |
5380 | symbol_set_frag (sym, frag_now); | |
5381 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5382 | ||
82e7541d BW |
5383 | if (generating_literals) |
5384 | xtensa_add_literal_sym (sym); | |
5385 | else | |
5386 | xtensa_add_insn_label (sym); | |
5387 | ||
7b1cc377 BW |
5388 | if (symbol_get_tc (sym)->is_loop_target) |
5389 | { | |
5390 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5391 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5392 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5393 | ||
5394 | xtensa_set_frag_assembly_state (frag_now); | |
5395 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5396 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5397 | ||
5398 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5399 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5400 | } |
e0001a05 NC |
5401 | |
5402 | /* No target aligning in the absolute section. */ | |
61846f28 | 5403 | if (now_seg != absolute_section |
61846f28 | 5404 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5405 | && !generating_literals) |
5406 | { | |
43cd72b9 BW |
5407 | xtensa_set_frag_assembly_state (frag_now); |
5408 | ||
b7afdeef SA |
5409 | if (do_align_targets ()) |
5410 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5411 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5412 | frag_now->fr_offset, NULL); | |
5413 | else | |
5414 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5415 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5416 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5417 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5418 | } |
5419 | ||
5420 | /* We need to mark the following properties even if we aren't aligning. */ | |
5421 | ||
5422 | /* If the label is already known to be a branch target, i.e., a | |
5423 | forward branch, mark the frag accordingly. Backward branches | |
5424 | are handled by xg_add_branch_and_loop_targets. */ | |
5425 | if (symbol_get_tc (sym)->is_branch_target) | |
5b7c81bd | 5426 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = true; |
43cd72b9 BW |
5427 | |
5428 | /* Loops only go forward, so they can be identified here. */ | |
5429 | if (symbol_get_tc (sym)->is_loop_target) | |
5b7c81bd | 5430 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = true; |
07a53e5c RH |
5431 | |
5432 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5433 | } |
5434 | ||
5435 | ||
5436 | /* tc_unrecognized_line hook */ | |
5437 | ||
5438 | int | |
7fa3d080 | 5439 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5440 | { |
5441 | switch (ch) | |
5442 | { | |
5443 | case '{' : | |
5444 | if (cur_vinsn.inside_bundle == 0) | |
5445 | { | |
5446 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5447 | when using --gstabs. Temporarily disable debug info. */ | |
5448 | generate_lineno_debug (); | |
5449 | if (debug_type == DEBUG_STABS) | |
5450 | { | |
5451 | xt_saved_debug_type = debug_type; | |
5452 | debug_type = DEBUG_NONE; | |
5453 | } | |
82e7541d | 5454 | |
43cd72b9 BW |
5455 | cur_vinsn.inside_bundle = 1; |
5456 | } | |
5457 | else | |
5458 | { | |
5459 | as_bad (_("extra opening brace")); | |
5460 | return 0; | |
5461 | } | |
5462 | break; | |
82e7541d | 5463 | |
43cd72b9 BW |
5464 | case '}' : |
5465 | if (cur_vinsn.inside_bundle) | |
5466 | finish_vinsn (&cur_vinsn); | |
5467 | else | |
5468 | { | |
5469 | as_bad (_("extra closing brace")); | |
5470 | return 0; | |
5471 | } | |
5472 | break; | |
5473 | default: | |
5474 | as_bad (_("syntax error")); | |
5475 | return 0; | |
e0001a05 | 5476 | } |
43cd72b9 | 5477 | return 1; |
e0001a05 NC |
5478 | } |
5479 | ||
5480 | ||
5481 | /* md_flush_pending_output hook */ | |
5482 | ||
5483 | void | |
7fa3d080 | 5484 | xtensa_flush_pending_output (void) |
e0001a05 | 5485 | { |
a3582eee BW |
5486 | /* This line fixes a bug where automatically generated gstabs info |
5487 | separates a function label from its entry instruction, ending up | |
5488 | with the literal position between the function label and the entry | |
5489 | instruction and crashing code. It only happens with --gstabs and | |
5490 | --text-section-literals, and when several other obscure relaxation | |
5491 | conditions are met. */ | |
5492 | if (outputting_stabs_line_debug) | |
5493 | return; | |
5494 | ||
43cd72b9 BW |
5495 | if (cur_vinsn.inside_bundle) |
5496 | as_bad (_("missing closing brace")); | |
5497 | ||
e0001a05 NC |
5498 | /* If there is a non-zero instruction fragment, close it. */ |
5499 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5500 | { | |
5501 | frag_wane (frag_now); | |
5502 | frag_new (0); | |
43cd72b9 | 5503 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 5504 | } |
5b7c81bd | 5505 | frag_now->tc_frag_data.is_insn = false; |
82e7541d BW |
5506 | |
5507 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5508 | } |
5509 | ||
5510 | ||
43cd72b9 BW |
5511 | /* We had an error while parsing an instruction. The string might look |
5512 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5513 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5514 | and the num_slots field will grow past the end of the array of slots, | |
5515 | and bad things happen. */ | |
5516 | ||
5517 | static void | |
7fa3d080 | 5518 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5519 | { |
5520 | if (cur_vinsn.inside_bundle) | |
5521 | { | |
5522 | if (*input_line_pointer == '}' | |
5523 | || *(input_line_pointer - 1) == '}' | |
5524 | || *(input_line_pointer - 2) == '}') | |
5525 | xg_clear_vinsn (&cur_vinsn); | |
5526 | } | |
5527 | } | |
5528 | ||
5529 | ||
e0001a05 | 5530 | void |
7fa3d080 | 5531 | md_assemble (char *str) |
e0001a05 NC |
5532 | { |
5533 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5534 | char *opname; |
e0001a05 | 5535 | unsigned opnamelen; |
5b7c81bd | 5536 | bool has_underbar = false; |
43cd72b9 | 5537 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5538 | int num_args; |
e0001a05 | 5539 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5540 | |
e0001a05 NC |
5541 | tinsn_init (&orig_insn); |
5542 | ||
5543 | /* Split off the opcode. */ | |
5544 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
4ec9d7d5 | 5545 | opname = xstrndup (str, opnamelen); |
e0001a05 NC |
5546 | |
5547 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5548 | if (num_args == -1) | |
5549 | { | |
5550 | as_bad (_("syntax error")); | |
5551 | return; | |
5552 | } | |
5553 | ||
5554 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5555 | return; | |
5556 | ||
5557 | /* Check for an underbar prefix. */ | |
5558 | if (*opname == '_') | |
5559 | { | |
5b7c81bd | 5560 | has_underbar = true; |
e0001a05 NC |
5561 | opname += 1; |
5562 | } | |
5563 | ||
5564 | orig_insn.insn_type = ITYPE_INSN; | |
5565 | orig_insn.ntok = 0; | |
43cd72b9 | 5566 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5567 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 | 5568 | |
2b0f3761 | 5569 | /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its |
28dbbc02 BW |
5570 | extra argument and set the opcode to "CALLXn". */ |
5571 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5572 | && strncasecmp (opname, "callx", 5) == 0) | |
5573 | { | |
5574 | unsigned long window_size; | |
5575 | char *suffix; | |
5576 | ||
5577 | window_size = strtoul (opname + 5, &suffix, 10); | |
5578 | if (suffix != opname + 5 | |
5579 | && (window_size == 0 | |
5580 | || window_size == 4 | |
5581 | || window_size == 8 | |
5582 | || window_size == 12) | |
5583 | && strcasecmp (suffix, ".tls") == 0) | |
5584 | { | |
5585 | switch (window_size) | |
5586 | { | |
5587 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5588 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5589 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5590 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5591 | } | |
5592 | ||
5593 | if (num_args != 2) | |
5594 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5595 | else | |
5596 | { | |
5597 | bfd_reloc_code_real_type reloc; | |
5598 | char *old_input_line_pointer; | |
19e8f41a | 5599 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5600 | |
5601 | old_input_line_pointer = input_line_pointer; | |
5602 | input_line_pointer = arg_strings[num_args - 1]; | |
5603 | ||
87975d2a | 5604 | expression (tok); |
28dbbc02 BW |
5605 | if (tok->X_op == O_symbol |
5606 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5607 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5608 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5609 | else | |
5610 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5611 | ||
5612 | input_line_pointer = old_input_line_pointer; | |
5613 | num_args -= 1; | |
5614 | } | |
5615 | } | |
5616 | } | |
5617 | ||
2b0f3761 | 5618 | /* Special case: Check for "j.l" pseudo op. */ |
19e8f41a BW |
5619 | if (orig_insn.opcode == XTENSA_UNDEFINED |
5620 | && strncasecmp (opname, "j.l", 3) == 0) | |
5621 | { | |
5622 | if (num_args != 2) | |
5623 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5624 | else | |
5625 | { | |
5626 | char *old_input_line_pointer; | |
5627 | expressionS *tok = &orig_insn.extra_arg; | |
5628 | ||
5629 | old_input_line_pointer = input_line_pointer; | |
5630 | input_line_pointer = arg_strings[num_args - 1]; | |
5631 | ||
5632 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5633 | input_line_pointer = old_input_line_pointer; | |
5634 | ||
5635 | num_args -= 1; | |
5636 | orig_insn.opcode = xtensa_j_opcode; | |
5637 | } | |
5638 | } | |
5639 | ||
e0001a05 NC |
5640 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5641 | { | |
43cd72b9 BW |
5642 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5643 | if (fmt == XTENSA_UNDEFINED) | |
5644 | { | |
5645 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5646 | error_reset_cur_vinsn (); | |
5647 | return; | |
5648 | } | |
5649 | if (!cur_vinsn.inside_bundle) | |
5650 | { | |
5651 | as_bad (_("format names only valid inside bundles")); | |
5652 | error_reset_cur_vinsn (); | |
5653 | return; | |
5654 | } | |
5655 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5656 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5657 | opname); | |
5658 | cur_vinsn.format = fmt; | |
5659 | free (has_underbar ? opname - 1 : opname); | |
5660 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5661 | return; |
5662 | } | |
5663 | ||
e0001a05 NC |
5664 | /* Parse the arguments. */ |
5665 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5666 | { | |
5667 | as_bad (_("syntax error")); | |
43cd72b9 | 5668 | error_reset_cur_vinsn (); |
e0001a05 NC |
5669 | return; |
5670 | } | |
5671 | ||
5672 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5673 | free (has_underbar ? opname - 1 : opname); | |
5674 | opname = 0; | |
5675 | while (num_args-- > 0) | |
5676 | free (arg_strings[num_args]); | |
5677 | ||
43cd72b9 BW |
5678 | /* Get expressions for invisible operands. */ |
5679 | if (get_invisible_operands (&orig_insn)) | |
5680 | { | |
5681 | error_reset_cur_vinsn (); | |
5682 | return; | |
5683 | } | |
5684 | ||
e0001a05 NC |
5685 | /* Check for the right number and type of arguments. */ |
5686 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5687 | { |
43cd72b9 BW |
5688 | error_reset_cur_vinsn (); |
5689 | return; | |
e0001a05 NC |
5690 | } |
5691 | ||
b224e962 BW |
5692 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5693 | spread across multiple input lines and individual instructions may be | |
5694 | moved around in some cases. */ | |
5695 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5696 | dwarf2_where (&orig_insn.debug_line); | |
5697 | dwarf2_consume_line_info (); | |
c138bc38 | 5698 | |
43cd72b9 BW |
5699 | xg_add_branch_and_loop_targets (&orig_insn); |
5700 | ||
431ad2d0 BW |
5701 | /* Check that immediate value for ENTRY is >= 16. */ |
5702 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5703 | { |
431ad2d0 BW |
5704 | expressionS *exp = &orig_insn.tok[2]; |
5705 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5706 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5707 | } |
5708 | ||
e0001a05 | 5709 | /* Finish it off: |
43cd72b9 BW |
5710 | assemble_tokens (opcode, tok, ntok); |
5711 | expand the tokens from the orig_insn into the | |
5712 | stack of instructions that will not expand | |
e0001a05 | 5713 | unless required at relaxation time. */ |
e0001a05 | 5714 | |
43cd72b9 BW |
5715 | if (!cur_vinsn.inside_bundle) |
5716 | emit_single_op (&orig_insn); | |
5717 | else /* We are inside a bundle. */ | |
e0001a05 | 5718 | { |
43cd72b9 BW |
5719 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5720 | cur_vinsn.num_slots++; | |
5721 | if (*input_line_pointer == '}' | |
5722 | || *(input_line_pointer - 1) == '}' | |
5723 | || *(input_line_pointer - 2) == '}') | |
5724 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5725 | } |
5726 | ||
43cd72b9 BW |
5727 | /* We've just emitted a new instruction so clear the list of labels. */ |
5728 | xtensa_clear_insn_labels (); | |
a82c7d90 DW |
5729 | |
5730 | xtensa_check_frag_count (); | |
e0001a05 NC |
5731 | } |
5732 | ||
5733 | ||
43cd72b9 | 5734 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5735 | |
43cd72b9 BW |
5736 | /* For a .align directive, we mark the previous block with the alignment |
5737 | information. This will be placed in the object file in the | |
5738 | property section corresponding to this section. */ | |
e0001a05 | 5739 | |
43cd72b9 | 5740 | void |
7fa3d080 | 5741 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5742 | { |
5743 | if (linkrelax | |
b08b5071 | 5744 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5745 | && (fragP->fr_type == rs_align |
5746 | || fragP->fr_type == rs_align_code) | |
43cd72b9 BW |
5747 | && fragP->fr_offset > 0 |
5748 | && now_seg != bss_section) | |
e0001a05 | 5749 | { |
5b7c81bd | 5750 | fragP->tc_frag_data.is_align = true; |
43cd72b9 | 5751 | fragP->tc_frag_data.alignment = fragP->fr_offset; |
e0001a05 NC |
5752 | } |
5753 | ||
43cd72b9 | 5754 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5755 | { |
43cd72b9 BW |
5756 | int count; |
5757 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5758 | if (count != 0) | |
c138bc38 | 5759 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5760 | _("unaligned entry instruction")); |
e0001a05 | 5761 | } |
99ded152 BW |
5762 | |
5763 | if (linkrelax && fragP->fr_type == rs_org) | |
5764 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5765 | } |
43cd72b9 | 5766 | |
e0001a05 NC |
5767 | |
5768 | /* TC_FRAG_INIT hook */ | |
5769 | ||
5770 | void | |
7fa3d080 | 5771 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5772 | { |
43cd72b9 | 5773 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5774 | } |
5775 | ||
5776 | ||
5777 | symbolS * | |
7fa3d080 | 5778 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5779 | { |
5780 | return NULL; | |
5781 | } | |
5782 | ||
5783 | ||
5784 | /* Round up a section size to the appropriate boundary. */ | |
5785 | ||
5786 | valueT | |
7fa3d080 | 5787 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5788 | { |
5789 | return size; /* Byte alignment is fine. */ | |
5790 | } | |
5791 | ||
5792 | ||
5793 | long | |
7fa3d080 | 5794 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5795 | { |
5796 | char *insn_p; | |
5797 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5798 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5799 | int opnum; |
43cd72b9 | 5800 | uint32 opnd_value; |
e0001a05 | 5801 | xtensa_opcode opcode; |
43cd72b9 BW |
5802 | xtensa_format fmt; |
5803 | int slot; | |
e0001a05 NC |
5804 | xtensa_isa isa = xtensa_default_isa; |
5805 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
5b7c81bd | 5806 | bool alt_reloc; |
e0001a05 | 5807 | |
e0001a05 | 5808 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5809 | return 0; |
e0001a05 | 5810 | |
1bbb5f21 BW |
5811 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5812 | return addr; | |
5813 | ||
e0001a05 | 5814 | if (!insnbuf) |
43cd72b9 BW |
5815 | { |
5816 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5817 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5818 | } | |
e0001a05 NC |
5819 | |
5820 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5821 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5822 | fmt = xtensa_format_decode (isa, insnbuf); |
5823 | ||
5824 | if (fmt == XTENSA_UNDEFINED) | |
5825 | as_fatal (_("bad instruction format")); | |
5826 | ||
5827 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5828 | as_fatal (_("invalid relocation")); | |
5829 | ||
5830 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5831 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5832 | ||
30f725a1 BW |
5833 | /* Check for "alternate" relocations (operand not specified). None |
5834 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5835 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5836 | { | |
5837 | if (opcode != xtensa_l32r_opcode | |
5838 | && opcode != xtensa_const16_opcode) | |
5839 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5840 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5841 | return 0; |
e0001a05 NC |
5842 | } |
5843 | ||
43cd72b9 BW |
5844 | opnum = get_relaxable_immed (opcode); |
5845 | opnd_value = 0; | |
5846 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5847 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5848 | { |
5849 | as_bad_where (fixP->fx_file, | |
5850 | fixP->fx_line, | |
5851 | _("invalid relocation for operand %d of '%s'"), | |
5852 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5853 | return 0; |
e0001a05 | 5854 | } |
43cd72b9 BW |
5855 | return 0 - opnd_value; |
5856 | } | |
5857 | ||
5858 | ||
5859 | /* TC_FORCE_RELOCATION hook */ | |
5860 | ||
5861 | int | |
7fa3d080 | 5862 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5863 | { |
5864 | switch (fix->fx_r_type) | |
30f725a1 BW |
5865 | { |
5866 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5867 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5868 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5869 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5870 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5871 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5872 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5873 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5874 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5875 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5876 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5877 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5878 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5879 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5880 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5881 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5882 | return 1; |
5883 | default: | |
5884 | break; | |
e0001a05 NC |
5885 | } |
5886 | ||
43cd72b9 BW |
5887 | if (linkrelax && fix->fx_addsy |
5888 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5889 | return 1; | |
5890 | ||
5891 | return generic_force_reloc (fix); | |
5892 | } | |
5893 | ||
5894 | ||
30f725a1 BW |
5895 | /* TC_VALIDATE_FIX_SUB hook */ |
5896 | ||
5897 | int | |
5898 | xtensa_validate_fix_sub (fixS *fix) | |
5899 | { | |
5900 | segT add_symbol_segment, sub_symbol_segment; | |
5901 | ||
5902 | /* The difference of two symbols should be resolved by the assembler when | |
5903 | linkrelax is not set. If the linker may relax the section containing | |
5904 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5905 | the linker knows to adjust the difference value. */ | |
5906 | if (!linkrelax || fix->fx_addsy == NULL) | |
5907 | return 0; | |
5908 | ||
5909 | /* Make sure both symbols are in the same segment, and that segment is | |
5910 | "normal" and relaxable. If the segment is not "normal", then the | |
5911 | fix is not valid. If the segment is not "relaxable", then the fix | |
5912 | should have been handled earlier. */ | |
5913 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5914 | if (! SEG_NORMAL (add_symbol_segment) || | |
5915 | ! relaxable_section (add_symbol_segment)) | |
5916 | return 0; | |
5917 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5918 | return (sub_symbol_segment == add_symbol_segment); | |
5919 | } | |
5920 | ||
5921 | ||
43cd72b9 BW |
5922 | /* NO_PSEUDO_DOT hook */ |
5923 | ||
5924 | /* This function has nothing to do with pseudo dots, but this is the | |
5925 | nearest macro to where the check needs to take place. FIXME: This | |
5926 | seems wrong. */ | |
5927 | ||
5b7c81bd | 5928 | bool |
7fa3d080 | 5929 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5930 | { |
5931 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5932 | as_bad (_("directives are not valid inside bundles")); | |
5933 | ||
5934 | /* This function must always return FALSE because it is called via a | |
5935 | macro that has nothing to do with bundling. */ | |
5b7c81bd | 5936 | return false; |
e0001a05 NC |
5937 | } |
5938 | ||
5939 | ||
43cd72b9 | 5940 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5941 | |
5942 | void | |
7fa3d080 | 5943 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5944 | { |
43cd72b9 BW |
5945 | /* Set up the assembly state. */ |
5946 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5947 | xtensa_set_frag_assembly_state (frag_now); | |
54879176 MF |
5948 | |
5949 | if (!use_literal_section | |
5950 | && seg_info (now_seg)->tc_segment_info_data.literal_pool_loc == NULL | |
5951 | && !xtensa_is_init_fini (now_seg)) | |
5952 | xtensa_mark_literal_pool_location (); | |
e0001a05 NC |
5953 | } |
5954 | ||
5955 | ||
5956 | /* tc_fix_adjustable hook */ | |
5957 | ||
5b7c81bd | 5958 | bool |
7fa3d080 | 5959 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5960 | { |
5961 | /* We need the symbol name for the VTABLE entries. */ | |
5962 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5963 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5964 | return 0; | |
5965 | ||
5966 | return 1; | |
5967 | } | |
5968 | ||
5969 | ||
6a7eedfe BW |
5970 | /* tc_symbol_new_hook */ |
5971 | ||
5972 | symbolS *expr_symbols = NULL; | |
5973 | ||
3739860c | 5974 | void |
6a7eedfe BW |
5975 | xtensa_symbol_new_hook (symbolS *sym) |
5976 | { | |
fb227da0 | 5977 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5978 | { |
5979 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5980 | expr_symbols = sym; | |
5981 | } | |
5982 | } | |
5983 | ||
5984 | ||
e0001a05 | 5985 | void |
55cf6793 | 5986 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5987 | { |
30f725a1 | 5988 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5989 | valueT val = 0; |
30f725a1 | 5990 | |
e7da6241 BW |
5991 | /* Subtracted symbols are only allowed for a few relocation types, and |
5992 | unless linkrelax is enabled, they should not make it to this point. */ | |
5993 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5994 | || fixP->fx_r_type == BFD_RELOC_16 | |
5995 | || fixP->fx_r_type == BFD_RELOC_8))) | |
4bf09429 | 5996 | as_bad_subtract (fixP); |
e7da6241 | 5997 | |
30f725a1 | 5998 | switch (fixP->fx_r_type) |
e0001a05 | 5999 | { |
1bbb5f21 | 6000 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
6001 | case BFD_RELOC_32: |
6002 | case BFD_RELOC_16: | |
6003 | case BFD_RELOC_8: | |
e7da6241 | 6004 | if (fixP->fx_subsy) |
30f725a1 | 6005 | { |
5b7c81bd AM |
6006 | bool neg = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
6007 | < S_GET_VALUE (fixP->fx_subsy)); | |
30ce8e47 | 6008 | |
30f725a1 BW |
6009 | switch (fixP->fx_r_type) |
6010 | { | |
6011 | case BFD_RELOC_8: | |
30ce8e47 MF |
6012 | fixP->fx_r_type = neg |
6013 | ? BFD_RELOC_XTENSA_NDIFF8 : BFD_RELOC_XTENSA_PDIFF8; | |
ea173078 | 6014 | fixP->fx_signed = 0; |
30f725a1 BW |
6015 | break; |
6016 | case BFD_RELOC_16: | |
30ce8e47 MF |
6017 | fixP->fx_r_type = neg |
6018 | ? BFD_RELOC_XTENSA_NDIFF16 : BFD_RELOC_XTENSA_PDIFF16; | |
ea173078 | 6019 | fixP->fx_signed = 0; |
30f725a1 BW |
6020 | break; |
6021 | case BFD_RELOC_32: | |
30ce8e47 MF |
6022 | fixP->fx_r_type = neg |
6023 | ? BFD_RELOC_XTENSA_NDIFF32 : BFD_RELOC_XTENSA_PDIFF32; | |
ea173078 | 6024 | fixP->fx_signed = 0; |
30f725a1 BW |
6025 | break; |
6026 | default: | |
6027 | break; | |
6028 | } | |
e0001a05 | 6029 | |
30f725a1 BW |
6030 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
6031 | - S_GET_VALUE (fixP->fx_subsy)); | |
6032 | ||
6033 | /* The difference value gets written out, and the DIFF reloc | |
6034 | identifies the address of the subtracted symbol (i.e., the one | |
6035 | with the lowest address). */ | |
6036 | *valP = val; | |
6037 | fixP->fx_offset -= val; | |
6038 | fixP->fx_subsy = NULL; | |
6039 | } | |
6040 | else if (! fixP->fx_addsy) | |
e0001a05 | 6041 | { |
30f725a1 | 6042 | val = *valP; |
e0001a05 | 6043 | fixP->fx_done = 1; |
30f725a1 | 6044 | } |
75c1c971 MF |
6045 | else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section) |
6046 | { | |
6047 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
6048 | *valP = val; | |
6049 | fixP->fx_done = 1; | |
6050 | } | |
d47d412e BW |
6051 | /* fall through */ |
6052 | ||
6053 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
6054 | md_number_to_chars (fixpos, val, fixP->fx_size); |
6055 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6056 | break; | |
e0001a05 | 6057 | |
28dbbc02 BW |
6058 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
6059 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
6060 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
6061 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
6062 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6063 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
6064 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6065 | break; | |
6066 | ||
30f725a1 BW |
6067 | case BFD_RELOC_XTENSA_SLOT0_OP: |
6068 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
6069 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
6070 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
6071 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
6072 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
6073 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
6074 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
6075 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
6076 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
6077 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
6078 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
6079 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
6080 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
6081 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
6082 | if (linkrelax) | |
6083 | { | |
6084 | /* Write the tentative value of a PC-relative relocation to a | |
6085 | local symbol into the instruction. The value will be ignored | |
6086 | by the linker, and it makes the object file disassembly | |
6087 | readable when all branch targets are encoded in relocations. */ | |
6088 | ||
9c2799c2 | 6089 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 6090 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
6091 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
6092 | { | |
6093 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
6094 | - md_pcrel_from (fixP)); | |
6095 | (void) xg_apply_fix_value (fixP, val); | |
6096 | } | |
6097 | } | |
6098 | else if (! fixP->fx_addsy) | |
6099 | { | |
6100 | val = *valP; | |
6101 | if (xg_apply_fix_value (fixP, val)) | |
6102 | fixP->fx_done = 1; | |
6103 | } | |
6104 | break; | |
e0001a05 | 6105 | |
30f725a1 | 6106 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
6107 | case BFD_RELOC_XTENSA_TLS_FUNC: |
6108 | case BFD_RELOC_XTENSA_TLS_ARG: | |
6109 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
6110 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
6111 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
6112 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
6113 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
6114 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
6115 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
6116 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
6117 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
6118 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
6119 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
6120 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
6121 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
6122 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
6123 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
6124 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
6125 | /* These all need to be resolved at link-time. Do nothing now. */ | |
6126 | break; | |
e0001a05 | 6127 | |
30f725a1 BW |
6128 | case BFD_RELOC_VTABLE_INHERIT: |
6129 | case BFD_RELOC_VTABLE_ENTRY: | |
6130 | fixP->fx_done = 0; | |
6131 | break; | |
e0001a05 | 6132 | |
30f725a1 BW |
6133 | default: |
6134 | as_bad (_("unhandled local relocation fix %s"), | |
6135 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
6136 | } |
6137 | } | |
6138 | ||
6139 | ||
6d4af3c2 | 6140 | const char * |
7fa3d080 | 6141 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 6142 | { |
499ac353 | 6143 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
6144 | } |
6145 | ||
6146 | ||
6147 | int | |
7fa3d080 | 6148 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 6149 | { |
34e41783 | 6150 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
6151 | } |
6152 | ||
6153 | ||
6154 | /* Translate internal representation of relocation info to BFD target | |
6155 | format. */ | |
6156 | ||
6157 | arelent * | |
30f725a1 | 6158 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
6159 | { |
6160 | arelent *reloc; | |
6161 | ||
325801bd TS |
6162 | reloc = XNEW (arelent); |
6163 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
e0001a05 NC |
6164 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
6165 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6166 | ||
6167 | /* Make sure none of our internal relocations make it this far. | |
6168 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 6169 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 6170 | |
30f725a1 | 6171 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 6172 | |
e0001a05 NC |
6173 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
6174 | if (reloc->howto == NULL) | |
6175 | { | |
6176 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6177 | _("cannot represent `%s' relocation in object file"), | |
6178 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
6179 | free (reloc->sym_ptr_ptr); |
6180 | free (reloc); | |
e0001a05 NC |
6181 | return NULL; |
6182 | } | |
6183 | ||
6184 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6185 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6186 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6187 | |
e0001a05 NC |
6188 | return reloc; |
6189 | } | |
6190 | ||
7fa3d080 BW |
6191 | \f |
6192 | /* Checks for resource conflicts between instructions. */ | |
6193 | ||
c138bc38 BW |
6194 | /* The func unit stuff could be implemented as bit-vectors rather |
6195 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6196 | slow, we will switch it. */ |
6197 | ||
c138bc38 | 6198 | resource_table * |
7fa3d080 BW |
6199 | new_resource_table (void *data, |
6200 | int cycles, | |
6201 | int nu, | |
6202 | unit_num_copies_func uncf, | |
6203 | opcode_num_units_func onuf, | |
6204 | opcode_funcUnit_use_unit_func ouuf, | |
6205 | opcode_funcUnit_use_stage_func ousf) | |
6206 | { | |
6207 | int i; | |
325801bd | 6208 | resource_table *rt = XNEW (resource_table); |
7fa3d080 BW |
6209 | rt->data = data; |
6210 | rt->cycles = cycles; | |
6211 | rt->allocated_cycles = cycles; | |
6212 | rt->num_units = nu; | |
6213 | rt->unit_num_copies = uncf; | |
6214 | rt->opcode_num_units = onuf; | |
6215 | rt->opcode_unit_use = ouuf; | |
6216 | rt->opcode_unit_stage = ousf; | |
6217 | ||
add39d23 | 6218 | rt->units = XCNEWVEC (unsigned char *, cycles); |
7fa3d080 | 6219 | for (i = 0; i < cycles; i++) |
add39d23 | 6220 | rt->units[i] = XCNEWVEC (unsigned char, nu); |
7fa3d080 BW |
6221 | |
6222 | return rt; | |
6223 | } | |
6224 | ||
6225 | ||
c138bc38 | 6226 | void |
7fa3d080 BW |
6227 | clear_resource_table (resource_table *rt) |
6228 | { | |
6229 | int i, j; | |
6230 | for (i = 0; i < rt->allocated_cycles; i++) | |
6231 | for (j = 0; j < rt->num_units; j++) | |
6232 | rt->units[i][j] = 0; | |
6233 | } | |
6234 | ||
6235 | ||
6236 | /* We never shrink it, just fake it into thinking so. */ | |
6237 | ||
c138bc38 | 6238 | void |
7fa3d080 BW |
6239 | resize_resource_table (resource_table *rt, int cycles) |
6240 | { | |
6241 | int i, old_cycles; | |
6242 | ||
6243 | rt->cycles = cycles; | |
6244 | if (cycles <= rt->allocated_cycles) | |
6245 | return; | |
6246 | ||
6247 | old_cycles = rt->allocated_cycles; | |
6248 | rt->allocated_cycles = cycles; | |
6249 | ||
325801bd | 6250 | rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); |
7fa3d080 | 6251 | for (i = 0; i < old_cycles; i++) |
325801bd | 6252 | rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); |
7fa3d080 | 6253 | for (i = old_cycles; i < cycles; i++) |
add39d23 | 6254 | rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); |
7fa3d080 BW |
6255 | } |
6256 | ||
6257 | ||
5b7c81bd | 6258 | bool |
7fa3d080 BW |
6259 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6260 | { | |
6261 | int i; | |
6262 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6263 | ||
c138bc38 | 6264 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6265 | { |
6266 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6267 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6268 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6269 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6270 | if (copies_in_use >= copies) | |
5b7c81bd | 6271 | return false; |
7fa3d080 | 6272 | } |
5b7c81bd | 6273 | return true; |
7fa3d080 | 6274 | } |
7fa3d080 | 6275 | |
c138bc38 BW |
6276 | |
6277 | void | |
7fa3d080 BW |
6278 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6279 | { | |
6280 | int i; | |
6281 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6282 | ||
c138bc38 | 6283 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6284 | { |
6285 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6286 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6287 | /* Note that this allows resources to be oversubscribed. That's |
6288 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6289 | resources_available reports when a resource is over-subscribed, |
6290 | so it's easy to tell. */ | |
6291 | rt->units[stage + cycle][unit]++; | |
6292 | } | |
6293 | } | |
6294 | ||
6295 | ||
c138bc38 | 6296 | void |
7fa3d080 BW |
6297 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6298 | { | |
6299 | int i; | |
6300 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6301 | ||
c138bc38 | 6302 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6303 | { |
6304 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6305 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6306 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6307 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6308 | } |
6309 | } | |
c138bc38 | 6310 | |
7fa3d080 BW |
6311 | |
6312 | /* Wrapper functions make parameterized resource reservation | |
6313 | more convenient. */ | |
6314 | ||
c138bc38 | 6315 | int |
7fa3d080 BW |
6316 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6317 | { | |
6318 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6319 | return use->unit; |
7fa3d080 BW |
6320 | } |
6321 | ||
6322 | ||
c138bc38 | 6323 | int |
7fa3d080 BW |
6324 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6325 | { | |
6326 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6327 | return use->stage; | |
6328 | } | |
6329 | ||
6330 | ||
6331 | /* Note that this function does not check issue constraints, but | |
6332 | solely whether the hardware is available to execute the given | |
c138bc38 | 6333 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6334 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6335 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 | 6336 | |
5b7c81bd | 6337 | static bool |
7fa3d080 BW |
6338 | resources_conflict (vliw_insn *vinsn) |
6339 | { | |
6340 | int i; | |
6341 | static resource_table *rt = NULL; | |
6342 | ||
6343 | /* This is the most common case by far. Optimize it. */ | |
6344 | if (vinsn->num_slots == 1) | |
5b7c81bd | 6345 | return false; |
43cd72b9 | 6346 | |
c138bc38 | 6347 | if (rt == NULL) |
7fa3d080 BW |
6348 | { |
6349 | xtensa_isa isa = xtensa_default_isa; | |
6350 | rt = new_resource_table | |
77cba8a3 | 6351 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6352 | xtensa_isa_num_funcUnits (isa), |
6353 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6354 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6355 | opcode_funcUnit_use_unit, | |
6356 | opcode_funcUnit_use_stage); | |
6357 | } | |
43cd72b9 | 6358 | |
7fa3d080 | 6359 | clear_resource_table (rt); |
43cd72b9 | 6360 | |
7fa3d080 BW |
6361 | for (i = 0; i < vinsn->num_slots; i++) |
6362 | { | |
6363 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5b7c81bd | 6364 | return true; |
7fa3d080 BW |
6365 | reserve_resources (rt, vinsn->slots[i].opcode, 0); |
6366 | } | |
e0001a05 | 6367 | |
5b7c81bd | 6368 | return false; |
7fa3d080 | 6369 | } |
e0001a05 | 6370 | |
7fa3d080 BW |
6371 | \f |
6372 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6373 | |
5b7c81bd | 6374 | static bool find_vinsn_conflicts (vliw_insn *); |
7fa3d080 | 6375 | static xtensa_format xg_find_narrowest_format (vliw_insn *); |
7fa3d080 | 6376 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6377 | |
6378 | ||
43cd72b9 BW |
6379 | /* We have reached the end of a bundle; emit into the frag. */ |
6380 | ||
e0001a05 | 6381 | static void |
7fa3d080 | 6382 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6383 | { |
43cd72b9 BW |
6384 | IStack slotstack; |
6385 | int i; | |
bf3d1399 | 6386 | int slots; |
e0001a05 | 6387 | |
43cd72b9 | 6388 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6389 | { |
6390 | xg_clear_vinsn (vinsn); | |
6391 | return; | |
6392 | } | |
43cd72b9 BW |
6393 | |
6394 | /* First, find a format that works. */ | |
6395 | if (vinsn->format == XTENSA_UNDEFINED) | |
6396 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6397 | ||
bf3d1399 AM |
6398 | slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); |
6399 | if (slots > 1 | |
19fc3723 SA |
6400 | && produce_flix == FLIX_NONE) |
6401 | { | |
6402 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6403 | xg_clear_vinsn (vinsn); | |
6404 | return; | |
6405 | } | |
6406 | ||
43cd72b9 BW |
6407 | if (vinsn->format == XTENSA_UNDEFINED) |
6408 | { | |
3b4dbbbf | 6409 | as_bad (_("couldn't find a valid instruction format")); |
43cd72b9 BW |
6410 | fprintf (stderr, _(" ops were: ")); |
6411 | for (i = 0; i < vinsn->num_slots; i++) | |
6412 | fprintf (stderr, _(" %s;"), | |
6413 | xtensa_opcode_name (xtensa_default_isa, | |
6414 | vinsn->slots[i].opcode)); | |
6415 | fprintf (stderr, _("\n")); | |
6416 | xg_clear_vinsn (vinsn); | |
6417 | return; | |
6418 | } | |
6419 | ||
bf3d1399 | 6420 | if (vinsn->num_slots != slots) |
e0001a05 | 6421 | { |
bf3d1399 AM |
6422 | as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), |
6423 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6e98b342 | 6424 | slots, vinsn->num_slots); |
43cd72b9 BW |
6425 | xg_clear_vinsn (vinsn); |
6426 | return; | |
6427 | } | |
e0001a05 | 6428 | |
c138bc38 | 6429 | if (resources_conflict (vinsn)) |
43cd72b9 | 6430 | { |
3b4dbbbf | 6431 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6432 | fprintf (stderr, " ops were: "); |
6433 | for (i = 0; i < vinsn->num_slots; i++) | |
6434 | fprintf (stderr, " %s;", | |
6435 | xtensa_opcode_name (xtensa_default_isa, | |
6436 | vinsn->slots[i].opcode)); | |
6437 | fprintf (stderr, "\n"); | |
6438 | xg_clear_vinsn (vinsn); | |
6439 | return; | |
6440 | } | |
6441 | ||
6442 | for (i = 0; i < vinsn->num_slots; i++) | |
6443 | { | |
6444 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6445 | { |
43cd72b9 BW |
6446 | symbolS *lit_sym = NULL; |
6447 | int j; | |
5b7c81bd AM |
6448 | bool e = false; |
6449 | bool saved_density = density_supported; | |
43cd72b9 BW |
6450 | |
6451 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6452 | if (vinsn->num_slots > 1) | |
5b7c81bd | 6453 | density_supported = false; |
43cd72b9 BW |
6454 | |
6455 | istack_init (&slotstack); | |
6456 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6457 | { |
43cd72b9 BW |
6458 | vinsn->slots[i].opcode = |
6459 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6460 | vinsn->format, i); | |
6461 | vinsn->slots[i].ntok = 0; | |
6462 | } | |
e0001a05 | 6463 | |
43cd72b9 BW |
6464 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6465 | { | |
5b7c81bd | 6466 | e = true; |
43cd72b9 | 6467 | continue; |
e0001a05 | 6468 | } |
e0001a05 | 6469 | |
43cd72b9 | 6470 | density_supported = saved_density; |
e0001a05 | 6471 | |
43cd72b9 BW |
6472 | if (e) |
6473 | { | |
6474 | xg_clear_vinsn (vinsn); | |
6475 | return; | |
6476 | } | |
e0001a05 | 6477 | |
0fa77c95 | 6478 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6479 | { |
6480 | TInsn *insn = &slotstack.insn[j]; | |
6481 | if (insn->insn_type == ITYPE_LITERAL) | |
6482 | { | |
9c2799c2 | 6483 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6484 | lit_sym = xg_assemble_literal (insn); |
6485 | } | |
6486 | else | |
6487 | { | |
9c2799c2 | 6488 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6489 | if (lit_sym) |
6490 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6491 | if (j != slotstack.ninsn - 1) |
6492 | emit_single_op (insn); | |
43cd72b9 BW |
6493 | } |
6494 | } | |
6495 | ||
6496 | if (vinsn->num_slots > 1) | |
6497 | { | |
6498 | if (opcode_fits_format_slot | |
6499 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6500 | vinsn->format, i)) | |
6501 | { | |
6502 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6503 | } | |
6504 | else | |
6505 | { | |
b2d179be | 6506 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6507 | if (vinsn->format == XTENSA_UNDEFINED) |
6508 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6509 | else | |
c138bc38 | 6510 | vinsn->slots[i].opcode |
43cd72b9 BW |
6511 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6512 | vinsn->format, i); | |
6513 | ||
6514 | vinsn->slots[i].ntok = 0; | |
6515 | } | |
6516 | } | |
6517 | else | |
6518 | { | |
6519 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6520 | vinsn->format = XTENSA_UNDEFINED; | |
6521 | } | |
6522 | } | |
6523 | } | |
6524 | ||
6525 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6526 | if (resources_conflict (vinsn)) |
43cd72b9 | 6527 | { |
3b4dbbbf | 6528 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6529 | fprintf (stderr, " ops were: "); |
6530 | for (i = 0; i < vinsn->num_slots; i++) | |
6531 | fprintf (stderr, " %s;", | |
6532 | xtensa_opcode_name (xtensa_default_isa, | |
6533 | vinsn->slots[i].opcode)); | |
6534 | fprintf (stderr, "\n"); | |
6535 | xg_clear_vinsn (vinsn); | |
6536 | return; | |
6537 | } | |
6538 | ||
6539 | /* First, find a format that works. */ | |
6540 | if (vinsn->format == XTENSA_UNDEFINED) | |
6541 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6542 | ||
6543 | xg_assemble_vliw_tokens (vinsn); | |
6544 | ||
6545 | xg_clear_vinsn (vinsn); | |
a82c7d90 DW |
6546 | |
6547 | xtensa_check_frag_count (); | |
43cd72b9 BW |
6548 | } |
6549 | ||
6550 | ||
6551 | /* Given an vliw instruction, what conflicts are there in register | |
6552 | usage and in writes to states and queues? | |
6553 | ||
6554 | This function does two things: | |
6555 | 1. Reports an error when a vinsn contains illegal combinations | |
6556 | of writes to registers states or queues. | |
6557 | 2. Marks individual tinsns as not relaxable if the combination | |
6558 | contains antidependencies. | |
6559 | ||
6560 | Job 2 handles things like swap semantics in instructions that need | |
6561 | to be relaxed. For example, | |
6562 | ||
6563 | addi a0, a1, 100000 | |
6564 | ||
6565 | normally would be relaxed to | |
6566 | ||
6567 | l32r a0, some_label | |
6568 | add a0, a1, a0 | |
6569 | ||
6570 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6571 | ||
6572 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6573 | ||
6574 | then we can't relax it into | |
6575 | ||
6576 | l32r a0, some_label | |
6577 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6578 | ||
6579 | because the value of a0 is trashed before the second add can read it. */ | |
6580 | ||
7fa3d080 BW |
6581 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6582 | ||
5b7c81bd | 6583 | static bool |
7fa3d080 | 6584 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6585 | { |
6586 | int i, j; | |
6587 | int branches = 0; | |
6588 | xtensa_isa isa = xtensa_default_isa; | |
6589 | ||
ed2917de | 6590 | gas_assert (!past_xtensa_md_finish); |
43cd72b9 BW |
6591 | |
6592 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6593 | { | |
6594 | TInsn *op1 = &vinsn->slots[i]; | |
6595 | if (op1->is_specific_opcode) | |
5b7c81bd | 6596 | op1->keep_wide = true; |
43cd72b9 | 6597 | else |
5b7c81bd | 6598 | op1->keep_wide = false; |
43cd72b9 BW |
6599 | } |
6600 | ||
6601 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6602 | { | |
6603 | TInsn *op1 = &vinsn->slots[i]; | |
6604 | ||
6605 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6606 | branches++; | |
6607 | ||
6608 | for (j = 0; j < vinsn->num_slots; j++) | |
6609 | { | |
6610 | if (i != j) | |
6611 | { | |
6612 | TInsn *op2 = &vinsn->slots[j]; | |
6613 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6614 | switch (conflict_type) | |
6615 | { | |
6616 | case 'c': | |
6617 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6618 | xtensa_opcode_name (isa, op1->opcode), i, | |
6619 | xtensa_opcode_name (isa, op2->opcode), j); | |
5b7c81bd | 6620 | return true; |
43cd72b9 BW |
6621 | case 'd': |
6622 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6623 | xtensa_opcode_name (isa, op1->opcode), i, | |
6624 | xtensa_opcode_name (isa, op2->opcode), j); | |
5b7c81bd | 6625 | return true; |
43cd72b9 | 6626 | case 'e': |
53dfbcc7 | 6627 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6628 | xtensa_opcode_name (isa, op1->opcode), i, |
6629 | xtensa_opcode_name (isa, op2->opcode), j); | |
5b7c81bd | 6630 | return true; |
43cd72b9 | 6631 | case 'f': |
53dfbcc7 | 6632 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6633 | xtensa_opcode_name (isa, op1->opcode), i, |
6634 | xtensa_opcode_name (isa, op2->opcode), j); | |
5b7c81bd | 6635 | return true; |
43cd72b9 BW |
6636 | default: |
6637 | /* Everything is OK. */ | |
6638 | break; | |
6639 | } | |
6640 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6641 | || conflict_type == 'a'); | |
6642 | } | |
6643 | } | |
6644 | } | |
6645 | ||
6646 | if (branches > 1) | |
6647 | { | |
6648 | as_bad (_("multiple branches or jumps in the same bundle")); | |
5b7c81bd | 6649 | return true; |
43cd72b9 BW |
6650 | } |
6651 | ||
5b7c81bd | 6652 | return false; |
43cd72b9 BW |
6653 | } |
6654 | ||
6655 | ||
a1ace8d8 | 6656 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6657 | Cases found are: |
6658 | ||
6659 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6660 | case B: no relationship between what is read and written (both could | |
6661 | read the same reg though) | |
c138bc38 | 6662 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6663 | bundle) |
6664 | case D: t1 writes a state that t2 also writes | |
6665 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6666 | case F: two volatile queue accesses |
43cd72b9 BW |
6667 | */ |
6668 | ||
6669 | static char | |
7fa3d080 | 6670 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6671 | { |
6672 | xtensa_isa isa = xtensa_default_isa; | |
6673 | xtensa_regfile t1_regfile, t2_regfile; | |
6674 | int t1_reg, t2_reg; | |
6675 | int t1_base_reg, t1_last_reg; | |
6676 | int t2_base_reg, t2_last_reg; | |
6677 | char t1_inout, t2_inout; | |
6678 | int i, j; | |
6679 | char conflict = 'b'; | |
6680 | int t1_states; | |
6681 | int t2_states; | |
6682 | int t1_interfaces; | |
6683 | int t2_interfaces; | |
5b7c81bd AM |
6684 | bool t1_volatile = false; |
6685 | bool t2_volatile = false; | |
43cd72b9 BW |
6686 | |
6687 | /* Check registers. */ | |
6688 | for (j = 0; j < t2->ntok; j++) | |
6689 | { | |
6690 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6691 | continue; | |
6692 | ||
6693 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6694 | t2_base_reg = t2->tok[j].X_add_number; | |
6695 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6696 | ||
6697 | for (i = 0; i < t1->ntok; i++) | |
6698 | { | |
6699 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6700 | continue; | |
6701 | ||
6702 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6703 | ||
6704 | if (t1_regfile != t2_regfile) | |
6705 | continue; | |
6706 | ||
6707 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6708 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6709 | ||
6710 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6711 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6712 | { | |
6713 | if (t1_inout == 'm' || t1_inout == 'o' | |
6714 | || t2_inout == 'm' || t2_inout == 'o') | |
6715 | { | |
6716 | conflict = 'a'; | |
6717 | continue; | |
6718 | } | |
6719 | } | |
6720 | ||
6721 | t1_base_reg = t1->tok[i].X_add_number; | |
6722 | t1_last_reg = (t1_base_reg | |
6723 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6724 | ||
6725 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6726 | { | |
6727 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6728 | { | |
6729 | if (t1_reg != t2_reg) | |
6730 | continue; | |
6731 | ||
6732 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6733 | { |
6734 | conflict = 'a'; | |
6735 | continue; | |
6736 | } | |
43cd72b9 | 6737 | |
7fa3d080 BW |
6738 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6739 | { | |
6740 | conflict = 'a'; | |
6741 | continue; | |
6742 | } | |
43cd72b9 | 6743 | |
7fa3d080 BW |
6744 | if (t1_inout != 'i' && t2_inout != 'i') |
6745 | return 'c'; | |
6746 | } | |
6747 | } | |
6748 | } | |
6749 | } | |
43cd72b9 | 6750 | |
7fa3d080 BW |
6751 | /* Check states. */ |
6752 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6753 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6754 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6755 | { |
7fa3d080 BW |
6756 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6757 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6758 | for (i = 0; i < t1_states; i++) | |
6759 | { | |
6760 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6761 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6762 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6763 | continue; |
43cd72b9 | 6764 | |
7fa3d080 BW |
6765 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6766 | { | |
6767 | conflict = 'a'; | |
6768 | continue; | |
6769 | } | |
c138bc38 | 6770 | |
7fa3d080 BW |
6771 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6772 | { | |
6773 | conflict = 'a'; | |
6774 | continue; | |
6775 | } | |
c138bc38 | 6776 | |
7fa3d080 BW |
6777 | if (t1_inout != 'i' && t2_inout != 'i') |
6778 | return 'd'; | |
c138bc38 | 6779 | } |
7fa3d080 | 6780 | } |
43cd72b9 | 6781 | |
7fa3d080 BW |
6782 | /* Check tieports. */ |
6783 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6784 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6785 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6786 | { |
7fa3d080 BW |
6787 | xtensa_interface t2_int |
6788 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6789 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6790 | ||
53dfbcc7 | 6791 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6792 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
5b7c81bd | 6793 | t2_volatile = true; |
a1ace8d8 | 6794 | |
7fa3d080 BW |
6795 | for (i = 0; i < t1_interfaces; i++) |
6796 | { | |
6797 | xtensa_interface t1_int | |
6798 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6799 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6800 | |
53dfbcc7 | 6801 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6802 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
5b7c81bd | 6803 | t1_volatile = true; |
a1ace8d8 BW |
6804 | |
6805 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6806 | return 'f'; | |
c138bc38 | 6807 | |
7fa3d080 BW |
6808 | if (t1_int != t2_int) |
6809 | continue; | |
c138bc38 | 6810 | |
7fa3d080 BW |
6811 | if (t2_inout == 'i' && t1_inout == 'o') |
6812 | { | |
6813 | conflict = 'a'; | |
6814 | continue; | |
6815 | } | |
c138bc38 | 6816 | |
7fa3d080 BW |
6817 | if (t1_inout == 'i' && t2_inout == 'o') |
6818 | { | |
6819 | conflict = 'a'; | |
6820 | continue; | |
6821 | } | |
c138bc38 | 6822 | |
7fa3d080 BW |
6823 | if (t1_inout != 'i' && t2_inout != 'i') |
6824 | return 'e'; | |
6825 | } | |
43cd72b9 | 6826 | } |
c138bc38 | 6827 | |
7fa3d080 | 6828 | return conflict; |
43cd72b9 BW |
6829 | } |
6830 | ||
6831 | ||
6832 | static xtensa_format | |
7fa3d080 | 6833 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6834 | { |
6835 | /* Right now we assume that the ops within the vinsn are properly | |
6836 | ordered for the slots that the programmer wanted them in. In | |
6837 | other words, we don't rearrange the ops in hopes of finding a | |
6838 | better format. The scheduler handles that. */ | |
6839 | ||
6840 | xtensa_isa isa = xtensa_default_isa; | |
6841 | xtensa_format format; | |
43cd72b9 BW |
6842 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6843 | ||
65738a7d BW |
6844 | if (vinsn->num_slots == 1) |
6845 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6846 | ||
43cd72b9 BW |
6847 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6848 | { | |
d8392fd9 SA |
6849 | vliw_insn v_copy; |
6850 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6851 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6852 | { | |
6853 | int slot; | |
6854 | int fit = 0; | |
6855 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6856 | { | |
6857 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6858 | { | |
6859 | v_copy.slots[slot].opcode = | |
6860 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6861 | v_copy.slots[slot].ntok = 0; | |
6862 | } | |
6863 | ||
6864 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6865 | format, slot)) | |
6866 | fit++; | |
7fa3d080 | 6867 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6868 | { |
7fa3d080 BW |
6869 | TInsn widened; |
6870 | /* Try the widened version. */ | |
6871 | if (!v_copy.slots[slot].keep_wide | |
6872 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 | 6873 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
5b7c81bd | 6874 | &widened, true) |
7fa3d080 BW |
6875 | && opcode_fits_format_slot (widened.opcode, |
6876 | format, slot)) | |
43cd72b9 | 6877 | { |
7fa3d080 BW |
6878 | v_copy.slots[slot] = widened; |
6879 | fit++; | |
43cd72b9 BW |
6880 | } |
6881 | } | |
6882 | } | |
6883 | if (fit == v_copy.num_slots) | |
6884 | { | |
d8392fd9 | 6885 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6886 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6887 | vinsn->format = format; | |
6888 | break; | |
6889 | } | |
6890 | } | |
6891 | } | |
6892 | ||
6893 | if (format == xtensa_isa_num_formats (isa)) | |
6894 | return XTENSA_UNDEFINED; | |
6895 | ||
6896 | return format; | |
6897 | } | |
6898 | ||
6899 | ||
6900 | /* Return the additional space needed in a frag | |
6901 | for possible relaxations of any ops in a VLIW insn. | |
6902 | Also fill out the relaxations that might be required of | |
6903 | each tinsn in the vinsn. */ | |
6904 | ||
6905 | static int | |
5b7c81bd | 6906 | relaxation_requirements (vliw_insn *vinsn, bool *pfinish_frag) |
43cd72b9 | 6907 | { |
5b7c81bd | 6908 | bool finish_frag = false; |
43cd72b9 BW |
6909 | int extra_space = 0; |
6910 | int slot; | |
6911 | ||
6912 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6913 | { | |
6914 | TInsn *tinsn = &vinsn->slots[slot]; | |
6915 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6916 | { | |
6917 | /* A narrow instruction could be widened later to help | |
6918 | alignment issues. */ | |
5b7c81bd | 6919 | if (xg_is_single_relaxable_insn (tinsn, 0, true) |
43cd72b9 BW |
6920 | && !tinsn->is_specific_opcode |
6921 | && vinsn->num_slots == 1) | |
6922 | { | |
6923 | /* Difference in bytes between narrow and wide insns... */ | |
6924 | extra_space += 1; | |
6925 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6926 | } |
6927 | } | |
6928 | else | |
6929 | { | |
b08b5071 BW |
6930 | if (workaround_b_j_loop_end |
6931 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6932 | && use_transform ()) |
6933 | { | |
6934 | /* Add 2 of these. */ | |
6935 | extra_space += 3; /* for the nop size */ | |
6936 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6937 | } | |
c138bc38 | 6938 | |
43cd72b9 BW |
6939 | /* Need to assemble it with space for the relocation. */ |
6940 | if (xg_is_relaxable_insn (tinsn, 0) | |
6941 | && !tinsn->is_specific_opcode) | |
6942 | { | |
6943 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6944 | int max_literal_size = | |
6945 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6946 | |
43cd72b9 | 6947 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6948 | |
43cd72b9 | 6949 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6950 | extra_space += max_size; |
6951 | } | |
6952 | else | |
6953 | { | |
e7da6241 BW |
6954 | /* A fix record will be added for this instruction prior |
6955 | to relaxation, so make it end the frag. */ | |
5b7c81bd | 6956 | finish_frag = true; |
43cd72b9 BW |
6957 | } |
6958 | } | |
6959 | } | |
e7da6241 | 6960 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6961 | return extra_space; |
6962 | } | |
6963 | ||
6964 | ||
6965 | static void | |
b2d179be | 6966 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6967 | { |
6968 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6969 | int slot, chosen_slot; |
43cd72b9 | 6970 | |
b2d179be | 6971 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6972 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6973 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6974 | |
b2d179be BW |
6975 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6976 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6977 | { |
b2d179be BW |
6978 | if (slot == chosen_slot) |
6979 | vinsn->slots[slot] = *tinsn; | |
6980 | else | |
6981 | { | |
6982 | vinsn->slots[slot].opcode = | |
6983 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6984 | vinsn->slots[slot].ntok = 0; | |
6985 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6986 | } | |
43cd72b9 | 6987 | } |
43cd72b9 BW |
6988 | } |
6989 | ||
6990 | ||
5b7c81bd | 6991 | static bool |
7fa3d080 | 6992 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6993 | { |
6994 | int i; | |
6995 | IStack istack; /* put instructions into here */ | |
6996 | symbolS *lit_sym = NULL; | |
6997 | symbolS *label_sym = NULL; | |
6998 | ||
6999 | istack_init (&istack); | |
7000 | ||
7001 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
7002 | Because the scheduling and bundling characteristics of movi and |
7003 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 7004 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 7005 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
7006 | || orig_insn->opcode == xtensa_movi_n_opcode) |
7007 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 7008 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
7009 | || orig_insn->tok[1].X_op == O_pltrel |
7010 | || orig_insn->tok[1].X_op == O_tlsfunc | |
7011 | || orig_insn->tok[1].X_op == O_tlsarg | |
7012 | || orig_insn->tok[1].X_op == O_tpoff | |
7013 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 7014 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
7015 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
7016 | else | |
7017 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
5b7c81bd | 7018 | return true; |
43cd72b9 BW |
7019 | |
7020 | for (i = 0; i < istack.ninsn; i++) | |
7021 | { | |
7022 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 7023 | switch (insn->insn_type) |
43cd72b9 BW |
7024 | { |
7025 | case ITYPE_LITERAL: | |
9c2799c2 | 7026 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
7027 | lit_sym = xg_assemble_literal (insn); |
7028 | break; | |
7029 | case ITYPE_LABEL: | |
7030 | { | |
7031 | static int relaxed_sym_idx = 0; | |
325801bd | 7032 | char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); |
43cd72b9 BW |
7033 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); |
7034 | colon (label); | |
9c2799c2 | 7035 | gas_assert (label_sym == NULL); |
43cd72b9 | 7036 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 7037 | gas_assert (label_sym); |
43cd72b9 BW |
7038 | free (label); |
7039 | } | |
7040 | break; | |
7041 | case ITYPE_INSN: | |
b2d179be BW |
7042 | { |
7043 | vliw_insn v; | |
7044 | if (lit_sym) | |
7045 | xg_resolve_literals (insn, lit_sym); | |
7046 | if (label_sym) | |
7047 | xg_resolve_labels (insn, label_sym); | |
7048 | xg_init_vinsn (&v); | |
7049 | bundle_tinsn (insn, &v); | |
7050 | finish_vinsn (&v); | |
7051 | xg_free_vinsn (&v); | |
7052 | } | |
43cd72b9 BW |
7053 | break; |
7054 | default: | |
9c2799c2 | 7055 | gas_assert (0); |
43cd72b9 BW |
7056 | break; |
7057 | } | |
7058 | } | |
5b7c81bd | 7059 | return false; |
43cd72b9 BW |
7060 | } |
7061 | ||
7062 | ||
34e41783 BW |
7063 | static int |
7064 | total_frag_text_expansion (fragS *fragP) | |
7065 | { | |
7066 | int slot; | |
7067 | int total_expansion = 0; | |
7068 | ||
62af60e2 | 7069 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
7070 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
7071 | ||
7072 | return total_expansion; | |
7073 | } | |
7074 | ||
7075 | ||
43cd72b9 BW |
7076 | /* Emit a vliw instruction to the current fragment. */ |
7077 | ||
7fa3d080 BW |
7078 | static void |
7079 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 7080 | { |
5b7c81bd AM |
7081 | bool finish_frag; |
7082 | bool is_jump = false; | |
7083 | bool is_branch = false; | |
43cd72b9 | 7084 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
7085 | int insn_size; |
7086 | int extra_space; | |
7087 | char *f = NULL; | |
7088 | int slot; | |
b224e962 | 7089 | struct dwarf2_line_info debug_line; |
5b7c81bd | 7090 | bool loc_directive_seen = false; |
b224e962 | 7091 | TInsn *tinsn; |
43cd72b9 | 7092 | |
b224e962 | 7093 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
7094 | |
7095 | if (generating_literals) | |
7096 | { | |
7097 | static int reported = 0; | |
7098 | if (reported < 4) | |
7099 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
7100 | _("cannot assemble into a literal fragment")); | |
7101 | if (reported == 3) | |
7102 | as_bad (_("...")); | |
7103 | reported++; | |
7104 | return; | |
7105 | } | |
7106 | ||
7107 | if (frag_now_fix () != 0 | |
b08b5071 | 7108 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 7109 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
28a0da39 | 7110 | || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
7111 | || (directive_state[directive_longcalls] |
7112 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
7113 | || (directive_state[directive_absolute_literals] |
7114 | != frag_now->tc_frag_data.use_absolute_literals))) | |
7115 | { | |
7116 | frag_wane (frag_now); | |
7117 | frag_new (0); | |
7118 | xtensa_set_frag_assembly_state (frag_now); | |
7119 | } | |
7120 | ||
7121 | if (workaround_a0_b_retw | |
7122 | && vinsn->num_slots == 1 | |
7123 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
7124 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
7125 | && use_transform ()) | |
7126 | { | |
5b7c81bd | 7127 | has_a0_b_retw = true; |
43cd72b9 BW |
7128 | |
7129 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
7130 | After the first assembly pass we will check all of them and | |
7131 | add a nop if needed. */ | |
5b7c81bd | 7132 | frag_now->tc_frag_data.is_insn = true; |
43cd72b9 BW |
7133 | frag_var (rs_machine_dependent, 4, 4, |
7134 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7135 | frag_now->fr_symbol, | |
7136 | frag_now->fr_offset, | |
7137 | NULL); | |
7138 | xtensa_set_frag_assembly_state (frag_now); | |
5b7c81bd | 7139 | frag_now->tc_frag_data.is_insn = true; |
43cd72b9 BW |
7140 | frag_var (rs_machine_dependent, 4, 4, |
7141 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7142 | frag_now->fr_symbol, | |
7143 | frag_now->fr_offset, | |
7144 | NULL); | |
7145 | xtensa_set_frag_assembly_state (frag_now); | |
7146 | } | |
7147 | ||
b224e962 | 7148 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 7149 | { |
b224e962 BW |
7150 | tinsn = &vinsn->slots[slot]; |
7151 | ||
43cd72b9 | 7152 | /* See if the instruction implies an aligned section. */ |
b224e962 | 7153 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 7154 | record_alignment (now_seg, 2); |
c138bc38 | 7155 | |
b224e962 BW |
7156 | /* Determine the best line number for debug info. */ |
7157 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
7158 | && (tinsn->debug_line.filenum != debug_line.filenum | |
7159 | || tinsn->debug_line.line < debug_line.line | |
7160 | || tinsn->debug_line.column < debug_line.column)) | |
7161 | debug_line = tinsn->debug_line; | |
7162 | if (tinsn->loc_directive_seen) | |
5b7c81bd | 7163 | loc_directive_seen = true; |
43cd72b9 BW |
7164 | } |
7165 | ||
7166 | /* Special cases for instructions that force an alignment... */ | |
7167 | /* None of these opcodes are bundle-able. */ | |
7168 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
7169 | { | |
d77b99c9 | 7170 | int max_fill; |
c138bc38 | 7171 | |
05d58145 BW |
7172 | /* Remember the symbol that marks the end of the loop in the frag |
7173 | that marks the start of the loop. This way we can easily find | |
7174 | the end of the loop at the beginning, without adding special code | |
7175 | to mark the loop instructions themselves. */ | |
7176 | symbolS *target_sym = NULL; | |
7177 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7178 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7179 | ||
43cd72b9 | 7180 | xtensa_set_frag_assembly_state (frag_now); |
5b7c81bd | 7181 | frag_now->tc_frag_data.is_insn = true; |
c138bc38 | 7182 | |
43cd72b9 BW |
7183 | max_fill = get_text_align_max_fill_size |
7184 | (get_text_align_power (xtensa_fetch_width), | |
5b7c81bd | 7185 | true, frag_now->tc_frag_data.is_no_density); |
43cd72b9 BW |
7186 | |
7187 | if (use_transform ()) | |
7188 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7189 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7190 | else |
c138bc38 | 7191 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7192 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7193 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7194 | } |
7195 | ||
b08b5071 | 7196 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7197 | && !vinsn->slots[0].is_specific_opcode) |
7198 | { | |
7199 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7200 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7201 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7202 | } | |
7203 | ||
7204 | if (vinsn->num_slots == 1) | |
7205 | { | |
7206 | if (workaround_a0_b_retw && use_transform ()) | |
7207 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7208 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7209 | ||
7210 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7211 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7212 | } | |
7213 | else | |
5b7c81bd | 7214 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, false); |
43cd72b9 BW |
7215 | |
7216 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7217 | ||
e7da6241 | 7218 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7219 | |
7220 | /* vinsn_to_insnbuf will produce the error. */ | |
7221 | if (vinsn->format != XTENSA_UNDEFINED) | |
7222 | { | |
d77b99c9 | 7223 | f = frag_more (insn_size + extra_space); |
43cd72b9 | 7224 | xtensa_set_frag_assembly_state (frag_now); |
5b7c81bd | 7225 | frag_now->tc_frag_data.is_insn = true; |
43cd72b9 BW |
7226 | } |
7227 | ||
5b7c81bd | 7228 | vinsn_to_insnbuf (vinsn, f, frag_now, false); |
43cd72b9 BW |
7229 | if (vinsn->format == XTENSA_UNDEFINED) |
7230 | return; | |
7231 | ||
d77b99c9 | 7232 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7233 | |
b224e962 BW |
7234 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7235 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7236 | &debug_line); | |
43cd72b9 BW |
7237 | |
7238 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7239 | { | |
b224e962 | 7240 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7241 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7242 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7243 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 | 7244 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
b46824bd | 7245 | if (tinsn->opcode == xtensa_l32r_opcode) |
8d1015a8 AM |
7246 | frag_now->tc_frag_data.literal_frags[slot] |
7247 | = symbol_get_frag (tinsn->tok[1].X_add_symbol); | |
43cd72b9 BW |
7248 | if (tinsn->literal_space != 0) |
7249 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7250 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7251 | |
7252 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7253 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 | 7254 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
5b7c81bd | 7255 | is_jump = true; |
43cd72b9 | 7256 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) |
5b7c81bd | 7257 | is_branch = true; |
43cd72b9 | 7258 | |
e7da6241 BW |
7259 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7260 | || tinsn->literal_frag || is_jump || is_branch) | |
5b7c81bd | 7261 | finish_frag = true; |
43cd72b9 BW |
7262 | } |
7263 | ||
7264 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
5b7c81bd | 7265 | frag_now->tc_frag_data.is_specific_opcode = true; |
43cd72b9 BW |
7266 | |
7267 | if (finish_frag) | |
7268 | { | |
7269 | frag_variant (rs_machine_dependent, | |
7270 | extra_space, extra_space, RELAX_SLOTS, | |
7271 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7272 | xtensa_set_frag_assembly_state (frag_now); | |
7273 | } | |
7274 | ||
7275 | /* Special cases for loops: | |
7276 | close_loop_end should be inserted AFTER short_loop. | |
7277 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7278 | when converting them. */ | |
7279 | ||
7280 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7281 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7282 | && !vinsn->slots[0].is_specific_opcode) |
7283 | { | |
7284 | if (workaround_short_loop && use_transform ()) | |
7285 | { | |
5b7c81bd AM |
7286 | maybe_has_short_loop = true; |
7287 | frag_now->tc_frag_data.is_insn = true; | |
43cd72b9 BW |
7288 | frag_var (rs_machine_dependent, 4, 4, |
7289 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7290 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5b7c81bd | 7291 | frag_now->tc_frag_data.is_insn = true; |
43cd72b9 BW |
7292 | frag_var (rs_machine_dependent, 4, 4, |
7293 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7294 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7295 | } | |
7296 | ||
7297 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7298 | loop at least 12 bytes away from another loop's end. */ | |
7299 | if (workaround_close_loop_end && use_transform ()) | |
7300 | { | |
5b7c81bd AM |
7301 | maybe_has_close_loop_end = true; |
7302 | frag_now->tc_frag_data.is_insn = true; | |
43cd72b9 BW |
7303 | frag_var (rs_machine_dependent, 12, 12, |
7304 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7305 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7306 | } | |
7307 | } | |
7308 | ||
7309 | if (use_transform ()) | |
7310 | { | |
7311 | if (is_jump) | |
7312 | { | |
9c2799c2 | 7313 | gas_assert (finish_frag); |
43cd72b9 | 7314 | frag_var (rs_machine_dependent, |
1beeb686 | 7315 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7316 | RELAX_UNREACHABLE, |
7317 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7318 | xtensa_set_frag_assembly_state (frag_now); | |
a82c7d90 | 7319 | xtensa_maybe_create_trampoline_frag (); |
b46824bd | 7320 | /* Always create one here. */ |
5b7c81bd | 7321 | xtensa_maybe_create_literal_pool_frag (true, false); |
43cd72b9 | 7322 | } |
7b1cc377 | 7323 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7324 | { |
9c2799c2 | 7325 | gas_assert (finish_frag); |
43cd72b9 | 7326 | frag_var (rs_machine_dependent, |
1beeb686 | 7327 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7328 | RELAX_MAYBE_UNREACHABLE, |
7329 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7330 | xtensa_set_frag_assembly_state (frag_now); | |
7331 | frag_var (rs_machine_dependent, | |
7332 | 0, 0, | |
7333 | RELAX_MAYBE_DESIRE_ALIGN, | |
7334 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7335 | xtensa_set_frag_assembly_state (frag_now); | |
7336 | } | |
7337 | } | |
7338 | ||
7339 | /* Now, if the original opcode was a call... */ | |
7340 | if (do_align_targets () | |
7341 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7342 | { | |
b08b5071 | 7343 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
5b7c81bd | 7344 | frag_now->tc_frag_data.is_insn = true; |
43cd72b9 BW |
7345 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, |
7346 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7347 | xtensa_set_frag_assembly_state (frag_now); | |
7348 | } | |
7349 | ||
7350 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7351 | { | |
7352 | frag_wane (frag_now); | |
7353 | frag_new (0); | |
7354 | xtensa_set_frag_assembly_state (frag_now); | |
7355 | } | |
7356 | } | |
7357 | ||
7358 | \f | |
ed2917de | 7359 | /* xtensa_md_finish and helper functions. */ |
7fa3d080 BW |
7360 | |
7361 | static void xtensa_cleanup_align_frags (void); | |
7362 | static void xtensa_fix_target_frags (void); | |
7363 | static void xtensa_mark_narrow_branches (void); | |
7364 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7365 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7366 | static void xtensa_fix_a0_b_retw_frags (void); |
7367 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7368 | static void xtensa_fix_close_loop_end_frags (void); | |
7369 | static void xtensa_fix_short_loop_frags (void); | |
7370 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7371 | static void xtensa_add_config_info (void); |
7fa3d080 | 7372 | |
43cd72b9 | 7373 | void |
ed2917de | 7374 | xtensa_md_finish (void) |
43cd72b9 BW |
7375 | { |
7376 | directive_balance (); | |
7377 | xtensa_flush_pending_output (); | |
7378 | ||
ed2917de | 7379 | past_xtensa_md_finish = true; |
43cd72b9 BW |
7380 | |
7381 | xtensa_move_literals (); | |
7382 | ||
7383 | xtensa_reorder_segments (); | |
7384 | xtensa_cleanup_align_frags (); | |
7385 | xtensa_fix_target_frags (); | |
7386 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7387 | xtensa_fix_a0_b_retw_frags (); | |
7388 | if (workaround_b_j_loop_end) | |
7389 | xtensa_fix_b_j_loop_end_frags (); | |
7390 | ||
7391 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7392 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7393 | xtensa_fix_close_loop_end_frags (); | |
7394 | ||
7395 | if (workaround_short_loop && maybe_has_short_loop) | |
7396 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7397 | if (align_targets) |
7398 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7399 | xtensa_mark_zcl_first_insns (); |
7400 | ||
7401 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7402 | |
7403 | xtensa_add_config_info (); | |
a82c7d90 DW |
7404 | |
7405 | xtensa_check_frag_count (); | |
43cd72b9 BW |
7406 | } |
7407 | ||
148d6384 MF |
7408 | struct trampoline_chain_entry |
7409 | { | |
7410 | symbolS *sym; | |
7411 | addressT offset; | |
7412 | }; | |
7413 | ||
7414 | /* Trampoline chain for a given (sym, offset) pair is a sorted array | |
7415 | of locations of trampoline jumps leading there. Jumps are represented | |
7416 | as pairs (sym, offset): trampoline frag symbol and offset of the jump | |
7417 | inside the frag. */ | |
7418 | struct trampoline_chain | |
7419 | { | |
7420 | struct trampoline_chain_entry target; | |
7421 | struct trampoline_chain_entry *entry; | |
7422 | size_t n_entries; | |
7423 | size_t n_max; | |
5b7c81bd | 7424 | bool needs_sorting; |
148d6384 MF |
7425 | }; |
7426 | ||
7427 | struct trampoline_chain_index | |
7428 | { | |
7429 | struct trampoline_chain *entry; | |
7430 | size_t n_entries; | |
7431 | size_t n_max; | |
5b7c81bd | 7432 | bool needs_sorting; |
148d6384 MF |
7433 | }; |
7434 | ||
fe6c2f1b MF |
7435 | struct trampoline_index |
7436 | { | |
7437 | fragS **entry; | |
7438 | size_t n_entries; | |
7439 | size_t n_max; | |
7440 | }; | |
43cd72b9 | 7441 | |
a82c7d90 DW |
7442 | struct trampoline_seg |
7443 | { | |
7444 | struct trampoline_seg *next; | |
7445 | asection *seg; | |
148d6384 | 7446 | /* Trampolines ordered by their frag fr_address */ |
fe6c2f1b | 7447 | struct trampoline_index index; |
148d6384 MF |
7448 | /* Known trampoline chains ordered by (sym, offset) pair */ |
7449 | struct trampoline_chain_index chain_index; | |
a82c7d90 DW |
7450 | }; |
7451 | ||
7452 | static struct trampoline_seg trampoline_seg_list; | |
7453 | #define J_RANGE (128 * 1024) | |
fe6c2f1b | 7454 | #define J_MARGIN 4096 |
a82c7d90 DW |
7455 | |
7456 | static int unreachable_count = 0; | |
7457 | ||
7458 | ||
7459 | static void | |
7460 | xtensa_maybe_create_trampoline_frag (void) | |
7461 | { | |
7462 | if (!use_trampolines) | |
7463 | return; | |
7464 | ||
7465 | /* We create an area for possible trampolines every 10 unreachable frags. | |
7466 | These are preferred over the ones not preceded by an unreachable frag, | |
7467 | because we don't have to jump around them. This function is called after | |
7468 | each RELAX_UNREACHABLE frag is created. */ | |
7469 | ||
7470 | if (++unreachable_count > 10) | |
7471 | { | |
5b7c81bd | 7472 | xtensa_create_trampoline_frag (false); |
a82c7d90 DW |
7473 | clear_frag_count (); |
7474 | unreachable_count = 0; | |
7475 | } | |
7476 | } | |
7477 | ||
7478 | static void | |
7479 | xtensa_check_frag_count (void) | |
7480 | { | |
7481 | if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) | |
7482 | return; | |
7483 | ||
7484 | /* We create an area for possible trampolines every 8000 frags or so. This | |
7485 | is an estimate based on the max range of a "j" insn (+/-128K) divided | |
7486 | by a typical frag byte count (16), minus a few for safety. This function | |
7487 | is called after each source line is processed. */ | |
7488 | ||
7489 | if (get_frag_count () > 8000) | |
7490 | { | |
5b7c81bd | 7491 | xtensa_create_trampoline_frag (true); |
a82c7d90 DW |
7492 | clear_frag_count (); |
7493 | unreachable_count = 0; | |
7494 | } | |
b46824bd MF |
7495 | |
7496 | /* We create an area for a possible literal pool every N (default 5000) | |
7497 | frags or so. */ | |
5b7c81bd | 7498 | xtensa_maybe_create_literal_pool_frag (true, true); |
a82c7d90 DW |
7499 | } |
7500 | ||
7501 | static xtensa_insnbuf trampoline_buf = NULL; | |
7502 | static xtensa_insnbuf trampoline_slotbuf = NULL; | |
7503 | ||
b46824bd MF |
7504 | static xtensa_insnbuf litpool_buf = NULL; |
7505 | static xtensa_insnbuf litpool_slotbuf = NULL; | |
7506 | ||
a82c7d90 DW |
7507 | #define TRAMPOLINE_FRAG_SIZE 3000 |
7508 | ||
1c2649f5 MF |
7509 | static struct trampoline_seg * |
7510 | find_trampoline_seg (asection *seg) | |
7511 | { | |
7512 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
407e1140 MF |
7513 | static struct trampoline_seg *mr; |
7514 | ||
7515 | if (mr && mr->seg == seg) | |
7516 | return mr; | |
1c2649f5 MF |
7517 | |
7518 | for ( ; ts; ts = ts->next) | |
7519 | { | |
7520 | if (ts->seg == seg) | |
407e1140 MF |
7521 | { |
7522 | mr = ts; | |
7523 | return ts; | |
7524 | } | |
1c2649f5 MF |
7525 | } |
7526 | ||
7527 | return NULL; | |
7528 | } | |
7529 | ||
fe6c2f1b MF |
7530 | static size_t xg_find_trampoline (const struct trampoline_index *idx, |
7531 | addressT addr) | |
7532 | { | |
7533 | size_t a = 0; | |
7534 | size_t b = idx->n_entries; | |
7535 | ||
7536 | while (b - a > 1) | |
7537 | { | |
7538 | size_t c = (a + b) / 2; | |
7539 | ||
7540 | if (idx->entry[c]->fr_address <= addr) | |
7541 | a = c; | |
7542 | else | |
7543 | b = c; | |
7544 | } | |
7545 | return a; | |
7546 | } | |
7547 | ||
7548 | static void xg_add_trampoline_to_index (struct trampoline_index *idx, | |
7549 | fragS *fragP) | |
7550 | { | |
7551 | if (idx->n_entries == idx->n_max) | |
7552 | { | |
7553 | idx->n_max = (idx->n_entries + 1) * 2; | |
7554 | idx->entry = xrealloc (idx->entry, | |
7555 | sizeof (*idx->entry) * idx->n_max); | |
7556 | } | |
7557 | idx->entry[idx->n_entries] = fragP; | |
7558 | ++idx->n_entries; | |
7559 | } | |
7560 | ||
7561 | static void xg_remove_trampoline_from_index (struct trampoline_index *idx, | |
7562 | size_t i) | |
7563 | { | |
7564 | gas_assert (i < idx->n_entries); | |
7565 | memmove (idx->entry + i, idx->entry + i + 1, | |
7566 | (idx->n_entries - i - 1) * sizeof (*idx->entry)); | |
7567 | --idx->n_entries; | |
7568 | } | |
7569 | ||
7570 | static void xg_add_trampoline_to_seg (struct trampoline_seg *ts, | |
7571 | fragS *fragP) | |
7572 | { | |
7573 | xg_add_trampoline_to_index (&ts->index, fragP); | |
7574 | } | |
1c2649f5 | 7575 | |
a82c7d90 | 7576 | static void |
5b7c81bd | 7577 | xtensa_create_trampoline_frag (bool needs_jump_around) |
a82c7d90 DW |
7578 | { |
7579 | /* Emit a frag where we can place intermediate jump instructions, | |
7580 | in case we need to jump farther than 128K bytes. | |
7581 | Each jump instruction takes three bytes. | |
7582 | We allocate enough for 1000 trampolines in each frag. | |
7583 | If that's not enough, oh well. */ | |
7584 | ||
1c2649f5 | 7585 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
a82c7d90 DW |
7586 | char *varP; |
7587 | fragS *fragP; | |
7588 | int size = TRAMPOLINE_FRAG_SIZE; | |
7589 | ||
a82c7d90 DW |
7590 | if (ts == NULL) |
7591 | { | |
add39d23 | 7592 | ts = XCNEW(struct trampoline_seg); |
a82c7d90 DW |
7593 | ts->next = trampoline_seg_list.next; |
7594 | trampoline_seg_list.next = ts; | |
7595 | ts->seg = now_seg; | |
7596 | } | |
7597 | ||
7598 | frag_wane (frag_now); | |
7599 | frag_new (0); | |
7600 | xtensa_set_frag_assembly_state (frag_now); | |
7601 | varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); | |
7602 | fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); | |
7603 | if (trampoline_buf == NULL) | |
7604 | { | |
7605 | trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7606 | trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7607 | } | |
46888d71 | 7608 | fragP->tc_frag_data.needs_jump_around = needs_jump_around; |
fe6c2f1b | 7609 | xg_add_trampoline_to_seg (ts, fragP); |
a82c7d90 DW |
7610 | } |
7611 | ||
5b7c81bd | 7612 | static bool xg_is_trampoline_frag_full (const fragS *fragP) |
fe6c2f1b MF |
7613 | { |
7614 | return fragP->fr_var < 3; | |
7615 | } | |
a82c7d90 | 7616 | |
148d6384 MF |
7617 | static int xg_order_trampoline_chain_entry (const void *a, const void *b) |
7618 | { | |
7619 | const struct trampoline_chain_entry *pa = a; | |
7620 | const struct trampoline_chain_entry *pb = b; | |
7621 | ||
8ef6decb AM |
7622 | if (pa->sym != pb->sym) |
7623 | { | |
7624 | valueT aval = S_GET_VALUE (pa->sym); | |
7625 | valueT bval = S_GET_VALUE (pb->sym); | |
7626 | ||
7627 | if (aval != bval) | |
7628 | return aval < bval ? -1 : 1; | |
7629 | } | |
7630 | if (pa->offset != pb->offset) | |
7631 | return pa->offset < pb->offset ? -1 : 1; | |
7632 | return 0; | |
148d6384 MF |
7633 | } |
7634 | ||
7635 | static void xg_sort_trampoline_chain (struct trampoline_chain *tc) | |
7636 | { | |
7637 | qsort (tc->entry, tc->n_entries, sizeof (*tc->entry), | |
7638 | xg_order_trampoline_chain_entry); | |
5b7c81bd | 7639 | tc->needs_sorting = false; |
148d6384 MF |
7640 | } |
7641 | ||
7642 | /* Find entry index in the given chain with maximal address <= source. */ | |
7643 | static size_t xg_find_chain_entry (struct trampoline_chain *tc, | |
7644 | addressT source) | |
7645 | { | |
7646 | size_t a = 0; | |
7647 | size_t b = tc->n_entries; | |
7648 | ||
7649 | if (tc->needs_sorting) | |
7650 | xg_sort_trampoline_chain (tc); | |
7651 | ||
7652 | while (b - a > 1) | |
7653 | { | |
7654 | size_t c = (a + b) / 2; | |
7655 | struct trampoline_chain_entry *e = tc->entry + c; | |
7656 | ||
7657 | if (S_GET_VALUE(e->sym) + e->offset <= source) | |
7658 | a = c; | |
7659 | else | |
7660 | b = c; | |
7661 | } | |
7662 | return a; | |
7663 | } | |
7664 | ||
7665 | /* Find the best jump target for the source in the given trampoline chain. | |
7666 | The best jump target is the one that results in the shortest path to the | |
7667 | final target, it's the location of the jump closest to the final target, | |
7668 | but within the J_RANGE - J_MARGIN from the source. */ | |
7669 | static struct trampoline_chain_entry * | |
7670 | xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source) | |
7671 | { | |
7672 | addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset; | |
7673 | size_t i = xg_find_chain_entry (tc, source); | |
7674 | struct trampoline_chain_entry *e = tc->entry + i; | |
7675 | int step = target < source ? -1 : 1; | |
7676 | addressT chained_target; | |
7677 | offsetT off; | |
7678 | ||
7679 | if (target > source && | |
7680 | S_GET_VALUE(e->sym) + e->offset <= source && | |
7681 | i + 1 < tc->n_entries) | |
7682 | ++i; | |
7683 | ||
7684 | while (i + step < tc->n_entries) | |
7685 | { | |
7686 | struct trampoline_chain_entry *next = tc->entry + i + step; | |
7687 | ||
7688 | chained_target = S_GET_VALUE(next->sym) + next->offset; | |
7689 | off = source - chained_target; | |
7690 | ||
7691 | if (labs (off) >= J_RANGE - J_MARGIN) | |
7692 | break; | |
7693 | ||
7694 | i += step; | |
7695 | } | |
7696 | ||
7697 | e = tc->entry + i; | |
7698 | chained_target = S_GET_VALUE(e->sym) + e->offset; | |
7699 | off = source - chained_target; | |
7700 | ||
7701 | if (labs (off) < J_MARGIN || | |
7702 | labs (off) >= J_RANGE - J_MARGIN) | |
7703 | return &tc->target; | |
7704 | return tc->entry + i; | |
7705 | } | |
7706 | ||
7707 | static int xg_order_trampoline_chain (const void *a, const void *b) | |
7708 | { | |
10af2a65 MF |
7709 | const struct trampoline_chain *_pa = a; |
7710 | const struct trampoline_chain *_pb = b; | |
7711 | const struct trampoline_chain_entry *pa = &_pa->target; | |
7712 | const struct trampoline_chain_entry *pb = &_pb->target; | |
7713 | symbolS *s1 = pa->sym; | |
7714 | symbolS *s2 = pb->sym; | |
7715 | ||
8ef6decb AM |
7716 | if (s1 != s2) |
7717 | { | |
7718 | symbolS *tmp = symbol_symbolS (s1); | |
7719 | if (tmp) | |
7720 | s1 = tmp; | |
10af2a65 | 7721 | |
8ef6decb AM |
7722 | tmp = symbol_symbolS (s2); |
7723 | if (tmp) | |
7724 | s2 = tmp; | |
10af2a65 | 7725 | |
8ef6decb AM |
7726 | if (s1 != s2) |
7727 | return s1 < s2 ? -1 : 1; | |
7728 | } | |
7729 | ||
7730 | if (pa->offset != pb->offset) | |
7731 | return pa->offset < pb->offset ? -1 : 1; | |
7732 | return 0; | |
148d6384 MF |
7733 | } |
7734 | ||
7735 | static struct trampoline_chain * | |
7736 | xg_get_trampoline_chain (struct trampoline_seg *ts, | |
7737 | symbolS *sym, | |
7738 | addressT offset) | |
7739 | { | |
7740 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7741 | struct trampoline_chain c; | |
7742 | ||
e637b7ba AM |
7743 | if (idx->n_entries == 0) |
7744 | return NULL; | |
7745 | ||
148d6384 MF |
7746 | if (idx->needs_sorting) |
7747 | { | |
7748 | qsort (idx->entry, idx->n_entries, sizeof (*idx->entry), | |
7749 | xg_order_trampoline_chain); | |
5b7c81bd | 7750 | idx->needs_sorting = false; |
148d6384 MF |
7751 | } |
7752 | c.target.sym = sym; | |
7753 | c.target.offset = offset; | |
7754 | return bsearch (&c, idx->entry, idx->n_entries, | |
7755 | sizeof (struct trampoline_chain), | |
7756 | xg_order_trampoline_chain); | |
7757 | } | |
7758 | ||
7759 | /* Find trampoline chain in the given trampoline segment that is going | |
7760 | to the *sym + *offset. If found, replace *sym and *offset with the | |
7761 | best jump target in that chain. */ | |
7762 | static struct trampoline_chain * | |
7763 | xg_find_best_eq_target (struct trampoline_seg *ts, | |
7764 | addressT source, symbolS **sym, | |
7765 | addressT *offset) | |
7766 | { | |
7767 | struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset); | |
7768 | ||
7769 | if (tc) | |
7770 | { | |
7771 | struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source); | |
7772 | ||
7773 | *sym = e->sym; | |
7774 | *offset = e->offset; | |
7775 | } | |
7776 | return tc; | |
7777 | } | |
7778 | ||
7779 | static void xg_add_location_to_chain (struct trampoline_chain *tc, | |
7780 | symbolS *sym, addressT offset) | |
7781 | { | |
7782 | struct trampoline_chain_entry *e; | |
7783 | ||
7784 | if (tc->n_entries == tc->n_max) | |
7785 | { | |
7786 | tc->n_max = (tc->n_max + 1) * 2; | |
7787 | tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max); | |
7788 | } | |
7789 | e = tc->entry + tc->n_entries; | |
7790 | e->sym = sym; | |
7791 | e->offset = offset; | |
7792 | ++tc->n_entries; | |
5b7c81bd | 7793 | tc->needs_sorting = true; |
148d6384 MF |
7794 | } |
7795 | ||
7796 | static struct trampoline_chain * | |
7797 | xg_create_trampoline_chain (struct trampoline_seg *ts, | |
7798 | symbolS *sym, addressT offset) | |
7799 | { | |
7800 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7801 | struct trampoline_chain *tc; | |
7802 | ||
7803 | if (idx->n_entries == idx->n_max) | |
7804 | { | |
7805 | idx->n_max = (idx->n_max + 1) * 2; | |
7806 | idx->entry = xrealloc (idx->entry, | |
7807 | sizeof (*idx->entry) * idx->n_max); | |
7808 | } | |
7809 | ||
7810 | tc = idx->entry + idx->n_entries; | |
7811 | tc->target.sym = sym; | |
7812 | tc->target.offset = offset; | |
7813 | tc->entry = NULL; | |
7814 | tc->n_entries = 0; | |
7815 | tc->n_max = 0; | |
7816 | xg_add_location_to_chain (tc, sym, offset); | |
7817 | ||
7818 | ++idx->n_entries; | |
5b7c81bd | 7819 | idx->needs_sorting = true; |
148d6384 MF |
7820 | |
7821 | return tc; | |
7822 | } | |
7823 | ||
a82c7d90 DW |
7824 | void dump_trampolines (void); |
7825 | ||
7826 | void | |
7827 | dump_trampolines (void) | |
7828 | { | |
7829 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7830 | ||
7831 | for ( ; ts; ts = ts->next) | |
7832 | { | |
fe6c2f1b | 7833 | size_t i; |
a82c7d90 DW |
7834 | asection *seg = ts->seg; |
7835 | ||
7836 | if (seg == NULL) | |
7837 | continue; | |
7838 | fprintf(stderr, "SECTION %s\n", seg->name); | |
fe6c2f1b MF |
7839 | |
7840 | for (i = 0; i < ts->index.n_entries; ++i) | |
a82c7d90 | 7841 | { |
fe6c2f1b MF |
7842 | fragS *tf = ts->index.entry[i]; |
7843 | ||
a82c7d90 | 7844 | fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", |
46888d71 MF |
7845 | (int)tf->fr_address, (int)tf->fr_fix, |
7846 | tf->tc_frag_data.needs_jump_around ? "T" : "F"); | |
a82c7d90 DW |
7847 | } |
7848 | } | |
7849 | } | |
7850 | ||
b46824bd MF |
7851 | static void dump_litpools (void) __attribute__ ((unused)); |
7852 | ||
7853 | static void | |
7854 | dump_litpools (void) | |
7855 | { | |
7856 | struct litpool_seg *lps = litpool_seg_list.next; | |
7857 | struct litpool_frag *lpf; | |
7858 | ||
7859 | for ( ; lps ; lps = lps->next ) | |
7860 | { | |
7861 | printf("litpool seg %s\n", lps->seg->name); | |
7862 | for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) | |
7863 | { | |
7864 | fragS *litfrag = lpf->fragP->fr_next; | |
7865 | int count = 0; | |
7866 | while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) | |
7867 | { | |
7868 | if (litfrag->fr_fix == 4) | |
7869 | count++; | |
7870 | litfrag = litfrag->fr_next; | |
7871 | } | |
b5c37946 SJ |
7872 | printf(" %" PRId64 " <%d:%d> (%d) [%d]: ", |
7873 | (int64_t) lpf->addr, | |
7874 | lpf->priority, lpf->original_priority, | |
b46824bd | 7875 | lpf->fragP->fr_line, count); |
279edac5 | 7876 | /* dump_frag(lpf->fragP); */ |
b46824bd MF |
7877 | } |
7878 | } | |
7879 | } | |
7880 | ||
7881 | static void | |
5b7c81bd | 7882 | xtensa_maybe_create_literal_pool_frag (bool create, bool only_if_needed) |
b46824bd MF |
7883 | { |
7884 | struct litpool_seg *lps = litpool_seg_list.next; | |
7885 | fragS *fragP; | |
7886 | struct litpool_frag *lpf; | |
5b7c81bd | 7887 | bool needed = false; |
b46824bd MF |
7888 | |
7889 | if (use_literal_section || !auto_litpools) | |
7890 | return; | |
7891 | ||
7892 | for ( ; lps ; lps = lps->next ) | |
7893 | { | |
7894 | if (lps->seg == now_seg) | |
7895 | break; | |
7896 | } | |
7897 | ||
7898 | if (lps == NULL) | |
7899 | { | |
add39d23 | 7900 | lps = XCNEW (struct litpool_seg); |
b46824bd MF |
7901 | lps->next = litpool_seg_list.next; |
7902 | litpool_seg_list.next = lps; | |
7903 | lps->seg = now_seg; | |
7904 | lps->frag_list.next = &lps->frag_list; | |
7905 | lps->frag_list.prev = &lps->frag_list; | |
947fa914 MF |
7906 | /* Put candidate literal pool at the beginning of every section, |
7907 | so that even when section starts with literal load there's a | |
7908 | literal pool available. */ | |
7909 | lps->frag_count = auto_litpool_limit; | |
b46824bd MF |
7910 | } |
7911 | ||
7912 | lps->frag_count++; | |
7913 | ||
7914 | if (create) | |
7915 | { | |
7916 | if (only_if_needed) | |
7917 | { | |
ed2917de | 7918 | if (past_xtensa_md_finish || !use_transform() || |
b46824bd MF |
7919 | frag_now->tc_frag_data.is_no_transform) |
7920 | { | |
7921 | return; | |
7922 | } | |
7923 | if (auto_litpool_limit <= 0) | |
7924 | { | |
7925 | /* Don't create a litpool based only on frag count. */ | |
7926 | return; | |
7927 | } | |
7928 | else if (lps->frag_count > auto_litpool_limit) | |
7929 | { | |
5b7c81bd | 7930 | needed = true; |
b46824bd MF |
7931 | } |
7932 | else | |
7933 | { | |
7934 | return; | |
7935 | } | |
7936 | } | |
7937 | else | |
7938 | { | |
5b7c81bd | 7939 | needed = true; |
b46824bd MF |
7940 | } |
7941 | } | |
7942 | ||
7943 | if (needed) | |
7944 | { | |
7945 | int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ | |
7946 | /* Create a potential site for a literal pool. */ | |
7947 | frag_wane (frag_now); | |
7948 | frag_new (0); | |
7949 | xtensa_set_frag_assembly_state (frag_now); | |
7950 | fragP = frag_now; | |
7951 | fragP->tc_frag_data.lit_frchain = frchain_now; | |
7952 | fragP->tc_frag_data.literal_frag = fragP; | |
7953 | frag_var (rs_machine_dependent, size, size, | |
7954 | (only_if_needed) ? | |
7955 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN : | |
7956 | RELAX_LITERAL_POOL_BEGIN, | |
7957 | NULL, 0, NULL); | |
7958 | frag_now->tc_frag_data.lit_seg = now_seg; | |
7959 | frag_variant (rs_machine_dependent, 0, 0, | |
7960 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); | |
7961 | xtensa_set_frag_assembly_state (frag_now); | |
7962 | } | |
7963 | else | |
7964 | { | |
7965 | /* RELAX_LITERAL_POOL_BEGIN frag is being created; | |
7966 | just record it here. */ | |
7967 | fragP = frag_now; | |
7968 | } | |
7969 | ||
325801bd | 7970 | lpf = XNEW (struct litpool_frag); |
b46824bd MF |
7971 | /* Insert at tail of circular list. */ |
7972 | lpf->addr = 0; | |
7973 | lps->frag_list.prev->next = lpf; | |
7974 | lpf->next = &lps->frag_list; | |
7975 | lpf->prev = lps->frag_list.prev; | |
7976 | lps->frag_list.prev = lpf; | |
7977 | lpf->fragP = fragP; | |
7978 | lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; | |
7979 | lpf->original_priority = lpf->priority; | |
cd665a94 | 7980 | lpf->literal_count = 0; |
b46824bd MF |
7981 | |
7982 | lps->frag_count = 0; | |
7983 | } | |
7984 | ||
43cd72b9 | 7985 | static void |
7fa3d080 | 7986 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7987 | { |
7988 | frchainS *frchP; | |
c9049d30 | 7989 | asection *s; |
43cd72b9 | 7990 | |
c9049d30 AM |
7991 | for (s = stdoutput->sections; s; s = s->next) |
7992 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7993 | { | |
7994 | fragS *fragP; | |
7995 | /* Walk over all of the fragments in a subsection. */ | |
7996 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7997 | { | |
7998 | if ((fragP->fr_type == rs_align | |
7999 | || fragP->fr_type == rs_align_code | |
8000 | || (fragP->fr_type == rs_machine_dependent | |
8001 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
8002 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
8003 | && fragP->fr_fix == 0) | |
8004 | { | |
8005 | fragS *next = fragP->fr_next; | |
8006 | ||
8007 | while (next | |
8008 | && next->fr_fix == 0 | |
8009 | && next->fr_type == rs_machine_dependent | |
8010 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
8011 | { | |
8012 | frag_wane (next); | |
8013 | next = next->fr_next; | |
8014 | } | |
8015 | } | |
8016 | /* If we don't widen branch targets, then they | |
8017 | will be easier to align. */ | |
8018 | if (fragP->tc_frag_data.is_branch_target | |
8019 | && fragP->fr_opcode == fragP->fr_literal | |
8020 | && fragP->fr_type == rs_machine_dependent | |
8021 | && fragP->fr_subtype == RELAX_SLOTS | |
8022 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8023 | frag_wane (fragP); | |
8024 | if (fragP->fr_type == rs_machine_dependent | |
8025 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
5b7c81bd | 8026 | fragP->tc_frag_data.is_unreachable = true; |
c9049d30 AM |
8027 | } |
8028 | } | |
43cd72b9 BW |
8029 | } |
8030 | ||
8031 | ||
8032 | /* Re-process all of the fragments looking to convert all of the | |
8033 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
8034 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 8035 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 8036 | |
43cd72b9 | 8037 | static void |
7fa3d080 | 8038 | xtensa_fix_target_frags (void) |
e0001a05 NC |
8039 | { |
8040 | frchainS *frchP; | |
c9049d30 | 8041 | asection *s; |
e0001a05 NC |
8042 | |
8043 | /* When this routine is called, all of the subsections are still intact | |
8044 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8045 | for (s = stdoutput->sections; s; s = s->next) |
8046 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8047 | { | |
8048 | fragS *fragP; | |
e0001a05 | 8049 | |
c9049d30 AM |
8050 | /* Walk over all of the fragments in a subsection. */ |
8051 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8052 | { | |
8053 | if (fragP->fr_type == rs_machine_dependent | |
8054 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
8055 | { | |
8056 | if (next_frag_is_branch_target (fragP)) | |
8057 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
8058 | else | |
8059 | frag_wane (fragP); | |
8060 | } | |
8061 | } | |
8062 | } | |
e0001a05 NC |
8063 | } |
8064 | ||
8065 | ||
5b7c81bd | 8066 | static bool is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7fa3d080 | 8067 | |
43cd72b9 | 8068 | static void |
7fa3d080 | 8069 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
8070 | { |
8071 | frchainS *frchP; | |
c9049d30 | 8072 | asection *s; |
43cd72b9 | 8073 | |
c9049d30 AM |
8074 | for (s = stdoutput->sections; s; s = s->next) |
8075 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8076 | { | |
8077 | fragS *fragP; | |
8078 | /* Walk over all of the fragments in a subsection. */ | |
8079 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8080 | { | |
8081 | if (fragP->fr_type == rs_machine_dependent | |
8082 | && fragP->fr_subtype == RELAX_SLOTS | |
8083 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
8084 | { | |
8085 | vliw_insn vinsn; | |
8086 | ||
8087 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
8088 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
8089 | ||
8090 | if (vinsn.num_slots == 1 | |
8091 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 8092 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
8093 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
8094 | && is_narrow_branch_guaranteed_in_range (fragP, | |
8095 | &vinsn.slots[0])) | |
8096 | { | |
8097 | fragP->fr_subtype = RELAX_SLOTS; | |
8098 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
8099 | fragP->tc_frag_data.is_aligning_branch = 1; | |
8100 | } | |
8101 | } | |
8102 | } | |
8103 | } | |
43cd72b9 BW |
8104 | } |
8105 | ||
8106 | ||
8107 | /* A branch is typically widened only when its target is out of | |
8108 | range. However, we would like to widen them to align a subsequent | |
8109 | branch target when possible. | |
8110 | ||
8111 | Because the branch relaxation code is so convoluted, the optimal solution | |
8112 | (combining the two cases) is difficult to get right in all circumstances. | |
8113 | We therefore go with an "almost as good" solution, where we only | |
8114 | use for alignment narrow branches that definitely will not expand to a | |
8115 | jump and a branch. These functions find and mark these cases. */ | |
8116 | ||
a67517f4 BW |
8117 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
8118 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
8119 | We start counting beginning with the frag after the 2-byte branch, so the | |
8120 | maximum offset is (4 - 2) + 63 = 65. */ | |
8121 | #define MAX_IMMED6 65 | |
43cd72b9 | 8122 | |
d77b99c9 | 8123 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 8124 | |
5b7c81bd | 8125 | static bool |
7fa3d080 | 8126 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 8127 | { |
91d6fa6a NC |
8128 | const expressionS *exp = &tinsn->tok[1]; |
8129 | symbolS *symbolP = exp->X_add_symbol; | |
8130 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
8131 | fragS *target_frag; |
8132 | ||
91d6fa6a | 8133 | if (exp->X_op != O_symbol) |
5b7c81bd | 8134 | return false; |
e7da6241 BW |
8135 | |
8136 | target_frag = symbol_get_frag (symbolP); | |
8137 | ||
43cd72b9 BW |
8138 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
8139 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
5b7c81bd | 8140 | return false; |
43cd72b9 BW |
8141 | |
8142 | /* The branch doesn't branch over it's own frag, | |
8143 | but over the subsequent ones. */ | |
8144 | fragP = fragP->fr_next; | |
8145 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
8146 | { | |
8147 | max_distance += unrelaxed_frag_max_size (fragP); | |
8148 | fragP = fragP->fr_next; | |
8149 | } | |
8150 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
5b7c81bd AM |
8151 | return true; |
8152 | return false; | |
e0001a05 NC |
8153 | } |
8154 | ||
8155 | ||
43cd72b9 | 8156 | static void |
7fa3d080 | 8157 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
8158 | { |
8159 | frchainS *frchP; | |
c9049d30 | 8160 | asection *s; |
43cd72b9 | 8161 | |
c9049d30 AM |
8162 | for (s = stdoutput->sections; s; s = s->next) |
8163 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8164 | { | |
8165 | fragS *fragP; | |
8166 | /* Walk over all of the fragments in a subsection. */ | |
8167 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8168 | { | |
8169 | if (fragP->fr_type == rs_machine_dependent | |
8170 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
8171 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
8172 | { | |
8173 | /* Find the loop frag. */ | |
3a1e9c4a | 8174 | fragS *loop_frag = next_non_empty_frag (fragP); |
c9049d30 | 8175 | /* Find the first insn frag. */ |
3a1e9c4a SA |
8176 | fragS *targ_frag = next_non_empty_frag (loop_frag); |
8177 | ||
8178 | /* Handle a corner case that comes up in hardware | |
8179 | diagnostics. The original assembly looks like this: | |
3739860c | 8180 | |
3a1e9c4a SA |
8181 | loop aX, LabelA |
8182 | <empty_frag>--not found by next_non_empty_frag | |
8183 | loop aY, LabelB | |
8184 | ||
8185 | Depending on the start address, the assembler may or | |
8186 | may not change it to look something like this: | |
8187 | ||
8188 | loop aX, LabelA | |
8189 | nop--frag isn't empty anymore | |
8190 | loop aY, LabelB | |
8191 | ||
8192 | So set up to check the alignment of the nop if it | |
8193 | exists */ | |
8194 | while (loop_frag != targ_frag) | |
8195 | { | |
8196 | if (loop_frag->fr_type == rs_machine_dependent | |
8197 | && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
3739860c | 8198 | || loop_frag->fr_subtype |
3a1e9c4a SA |
8199 | == RELAX_CHECK_ALIGN_NEXT_OPCODE)) |
8200 | targ_frag = loop_frag; | |
8201 | else | |
8202 | loop_frag = loop_frag->fr_next; | |
8203 | } | |
c9049d30 AM |
8204 | |
8205 | /* Of course, sometimes (mostly for toy test cases) a | |
8206 | zero-cost loop instruction is the last in a section. */ | |
8207 | if (targ_frag) | |
8208 | { | |
5b7c81bd | 8209 | targ_frag->tc_frag_data.is_first_loop_insn = true; |
c9049d30 AM |
8210 | /* Do not widen a frag that is the first instruction of a |
8211 | zero-cost loop. It makes that loop harder to align. */ | |
8212 | if (targ_frag->fr_type == rs_machine_dependent | |
8213 | && targ_frag->fr_subtype == RELAX_SLOTS | |
8214 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
8215 | == RELAX_NARROW)) | |
8216 | { | |
8217 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
8218 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8219 | else | |
8220 | { | |
8221 | frag_wane (targ_frag); | |
8222 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
8223 | } | |
8224 | } | |
8225 | } | |
8226 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
8227 | frag_wane (fragP); | |
8228 | } | |
8229 | } | |
8230 | } | |
43cd72b9 BW |
8231 | } |
8232 | ||
8233 | ||
fb227da0 BW |
8234 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
8235 | sleb128 value, the linker is unable to adjust that value to account for | |
8236 | link-time relaxation. Mark all the code between such symbols so that | |
8237 | its size cannot be changed by linker relaxation. */ | |
3739860c | 8238 | |
6a7eedfe BW |
8239 | static void |
8240 | xtensa_mark_difference_of_two_symbols (void) | |
8241 | { | |
8242 | symbolS *expr_sym; | |
8243 | ||
3739860c | 8244 | for (expr_sym = expr_symbols; expr_sym; |
6a7eedfe BW |
8245 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) |
8246 | { | |
91d6fa6a | 8247 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 8248 | |
91d6fa6a | 8249 | if (exp->X_op == O_subtract) |
6a7eedfe | 8250 | { |
91d6fa6a NC |
8251 | symbolS *left = exp->X_add_symbol; |
8252 | symbolS *right = exp->X_op_symbol; | |
3739860c | 8253 | |
6a7eedfe BW |
8254 | /* Difference of two symbols not in the same section |
8255 | are handled with relocations in the linker. */ | |
8256 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
8257 | { | |
8258 | fragS *start; | |
8259 | fragS *end; | |
983f90e3 | 8260 | fragS *walk; |
6a7eedfe | 8261 | |
3739860c | 8262 | if (symbol_get_frag (left)->fr_address |
6a7eedfe BW |
8263 | <= symbol_get_frag (right)->fr_address) |
8264 | { | |
8265 | start = symbol_get_frag (left); | |
8266 | end = symbol_get_frag (right); | |
8267 | } | |
8268 | else | |
8269 | { | |
8270 | start = symbol_get_frag (right); | |
8271 | end = symbol_get_frag (left); | |
8272 | } | |
983f90e3 SA |
8273 | |
8274 | if (start->tc_frag_data.no_transform_end != NULL) | |
8275 | walk = start->tc_frag_data.no_transform_end; | |
8276 | else | |
8277 | walk = start; | |
3739860c | 8278 | do |
6a7eedfe | 8279 | { |
983f90e3 SA |
8280 | walk->tc_frag_data.is_no_transform = 1; |
8281 | walk = walk->fr_next; | |
6a7eedfe | 8282 | } |
983f90e3 SA |
8283 | while (walk && walk->fr_address < end->fr_address); |
8284 | ||
8285 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
8286 | } |
8287 | } | |
8288 | } | |
8289 | } | |
8290 | ||
8291 | ||
e0001a05 NC |
8292 | /* Re-process all of the fragments looking to convert all of the |
8293 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
8294 | conditional branch or a retw/retw.n, convert this frag to one that | |
8295 | will generate a NOP. In any case close it off with a .fill 0. */ | |
8296 | ||
5b7c81bd | 8297 | static bool next_instrs_are_b_retw (fragS *); |
7fa3d080 | 8298 | |
e0001a05 | 8299 | static void |
7fa3d080 | 8300 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
8301 | { |
8302 | frchainS *frchP; | |
c9049d30 | 8303 | asection *s; |
e0001a05 NC |
8304 | |
8305 | /* When this routine is called, all of the subsections are still intact | |
8306 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8307 | for (s = stdoutput->sections; s; s = s->next) |
8308 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8309 | { | |
8310 | fragS *fragP; | |
e0001a05 | 8311 | |
c9049d30 AM |
8312 | /* Walk over all of the fragments in a subsection. */ |
8313 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8314 | { | |
8315 | if (fragP->fr_type == rs_machine_dependent | |
8316 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
8317 | { | |
8318 | if (next_instrs_are_b_retw (fragP)) | |
8319 | { | |
8320 | if (fragP->tc_frag_data.is_no_transform) | |
8321 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
8322 | else | |
8323 | relax_frag_add_nop (fragP); | |
8324 | } | |
8325 | frag_wane (fragP); | |
8326 | } | |
8327 | } | |
8328 | } | |
e0001a05 NC |
8329 | } |
8330 | ||
8331 | ||
5b7c81bd | 8332 | static bool |
7fa3d080 | 8333 | next_instrs_are_b_retw (fragS *fragP) |
e0001a05 NC |
8334 | { |
8335 | xtensa_opcode opcode; | |
43cd72b9 | 8336 | xtensa_format fmt; |
e0001a05 NC |
8337 | const fragS *next_fragP = next_non_empty_frag (fragP); |
8338 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 8339 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 8340 | xtensa_isa isa = xtensa_default_isa; |
871a6bd2 | 8341 | unsigned int offset = 0; |
43cd72b9 | 8342 | int slot; |
5b7c81bd | 8343 | bool branch_seen = false; |
e0001a05 NC |
8344 | |
8345 | if (!insnbuf) | |
43cd72b9 BW |
8346 | { |
8347 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8348 | slotbuf = xtensa_insnbuf_alloc (isa); | |
8349 | } | |
e0001a05 NC |
8350 | |
8351 | if (next_fragP == NULL) | |
5b7c81bd | 8352 | return false; |
e0001a05 NC |
8353 | |
8354 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
8355 | xtensa_insnbuf_from_chars |
8356 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8357 | fmt = xtensa_format_decode (isa, insnbuf); |
8358 | if (fmt == XTENSA_UNDEFINED) | |
5b7c81bd | 8359 | return false; |
43cd72b9 BW |
8360 | |
8361 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
8362 | { | |
8363 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
8364 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
8365 | ||
8366 | branch_seen = (branch_seen | |
8367 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
8368 | } | |
e0001a05 | 8369 | |
43cd72b9 | 8370 | if (!branch_seen) |
5b7c81bd | 8371 | return false; |
e0001a05 | 8372 | |
43cd72b9 | 8373 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8374 | if (offset == next_fragP->fr_fix) |
8375 | { | |
8376 | next_fragP = next_non_empty_frag (next_fragP); | |
8377 | offset = 0; | |
8378 | } | |
43cd72b9 | 8379 | |
e0001a05 | 8380 | if (next_fragP == NULL) |
5b7c81bd | 8381 | return false; |
e0001a05 NC |
8382 | |
8383 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
8384 | xtensa_insnbuf_from_chars |
8385 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8386 | fmt = xtensa_format_decode (isa, insnbuf); |
8387 | ||
8388 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
8389 | have no problems. */ | |
8390 | if (fmt == XTENSA_UNDEFINED | |
8391 | || xtensa_format_num_slots (isa, fmt) != 1) | |
5b7c81bd | 8392 | return false; |
43cd72b9 BW |
8393 | |
8394 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
8395 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 8396 | |
b08b5071 | 8397 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
5b7c81bd | 8398 | return true; |
43cd72b9 | 8399 | |
5b7c81bd | 8400 | return false; |
e0001a05 NC |
8401 | } |
8402 | ||
8403 | ||
8404 | /* Re-process all of the fragments looking to convert all of the | |
8405 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
8406 | loop end label, convert this frag to one that will generate a NOP. | |
8407 | In any case close it off with a .fill 0. */ | |
8408 | ||
5b7c81bd | 8409 | static bool next_instr_is_loop_end (fragS *); |
7fa3d080 | 8410 | |
e0001a05 | 8411 | static void |
7fa3d080 | 8412 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
8413 | { |
8414 | frchainS *frchP; | |
c9049d30 | 8415 | asection *s; |
e0001a05 NC |
8416 | |
8417 | /* When this routine is called, all of the subsections are still intact | |
8418 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8419 | for (s = stdoutput->sections; s; s = s->next) |
8420 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8421 | { | |
8422 | fragS *fragP; | |
e0001a05 | 8423 | |
c9049d30 AM |
8424 | /* Walk over all of the fragments in a subsection. */ |
8425 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8426 | { | |
8427 | if (fragP->fr_type == rs_machine_dependent | |
8428 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
8429 | { | |
8430 | if (next_instr_is_loop_end (fragP)) | |
8431 | { | |
8432 | if (fragP->tc_frag_data.is_no_transform) | |
8433 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
8434 | else | |
8435 | relax_frag_add_nop (fragP); | |
8436 | } | |
8437 | frag_wane (fragP); | |
8438 | } | |
8439 | } | |
8440 | } | |
e0001a05 NC |
8441 | } |
8442 | ||
8443 | ||
5b7c81bd | 8444 | static bool |
7fa3d080 | 8445 | next_instr_is_loop_end (fragS *fragP) |
e0001a05 NC |
8446 | { |
8447 | const fragS *next_fragP; | |
8448 | ||
8449 | if (next_frag_is_loop_target (fragP)) | |
5b7c81bd | 8450 | return false; |
e0001a05 NC |
8451 | |
8452 | next_fragP = next_non_empty_frag (fragP); | |
8453 | if (next_fragP == NULL) | |
5b7c81bd | 8454 | return false; |
e0001a05 NC |
8455 | |
8456 | if (!next_frag_is_loop_target (next_fragP)) | |
5b7c81bd | 8457 | return false; |
e0001a05 NC |
8458 | |
8459 | /* If the size is >= 3 then there is more than one instruction here. | |
8460 | The hardware bug will not fire. */ | |
8461 | if (next_fragP->fr_fix > 3) | |
5b7c81bd | 8462 | return false; |
e0001a05 | 8463 | |
5b7c81bd | 8464 | return true; |
e0001a05 NC |
8465 | } |
8466 | ||
8467 | ||
8468 | /* Re-process all of the fragments looking to convert all of the | |
8469 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
8470 | not MY loop's loop end within 12 bytes, add enough nops here to | |
8471 | make it at least 12 bytes away. In any case close it off with a | |
8472 | .fill 0. */ | |
8473 | ||
d77b99c9 | 8474 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 8475 | (fragS *, fragS *, offsetT); |
7fa3d080 | 8476 | |
e0001a05 | 8477 | static void |
7fa3d080 | 8478 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
8479 | { |
8480 | frchainS *frchP; | |
c9049d30 | 8481 | asection *s; |
e0001a05 NC |
8482 | |
8483 | /* When this routine is called, all of the subsections are still intact | |
8484 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8485 | for (s = stdoutput->sections; s; s = s->next) |
8486 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8487 | { | |
8488 | fragS *fragP; | |
e0001a05 | 8489 | |
c9049d30 | 8490 | fragS *current_target = NULL; |
e0001a05 | 8491 | |
c9049d30 AM |
8492 | /* Walk over all of the fragments in a subsection. */ |
8493 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8494 | { | |
8495 | if (fragP->fr_type == rs_machine_dependent | |
8496 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8497 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 8498 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 8499 | |
c9049d30 AM |
8500 | if (current_target |
8501 | && fragP->fr_type == rs_machine_dependent | |
8502 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
8503 | { | |
8504 | offsetT min_bytes; | |
8505 | int bytes_added = 0; | |
e0001a05 NC |
8506 | |
8507 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
8508 | /* Max out at 12. */ |
8509 | min_bytes = min_bytes_to_other_loop_end | |
8510 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
8511 | ||
8512 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
8513 | { | |
8514 | if (fragP->tc_frag_data.is_no_transform) | |
8515 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
8516 | else | |
8517 | { | |
8518 | while (min_bytes + bytes_added | |
8519 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
8520 | { | |
8521 | int length = 3; | |
8522 | ||
8523 | if (fragP->fr_var < length) | |
8524 | as_fatal (_("fr_var %lu < length %d"), | |
8525 | (long) fragP->fr_var, length); | |
8526 | else | |
8527 | { | |
8528 | assemble_nop (length, | |
8529 | fragP->fr_literal + fragP->fr_fix); | |
8530 | fragP->fr_fix += length; | |
8531 | fragP->fr_var -= length; | |
8532 | } | |
8533 | bytes_added += length; | |
8534 | } | |
8535 | } | |
8536 | } | |
8537 | frag_wane (fragP); | |
8538 | } | |
9c2799c2 | 8539 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
8540 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
8541 | } | |
8542 | } | |
e0001a05 NC |
8543 | } |
8544 | ||
8545 | ||
d77b99c9 | 8546 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 8547 | |
d77b99c9 | 8548 | static offsetT |
7fa3d080 BW |
8549 | min_bytes_to_other_loop_end (fragS *fragP, |
8550 | fragS *current_target, | |
d77b99c9 | 8551 | offsetT max_size) |
e0001a05 | 8552 | { |
d77b99c9 | 8553 | offsetT offset = 0; |
e0001a05 NC |
8554 | fragS *current_fragP; |
8555 | ||
8556 | for (current_fragP = fragP; | |
8557 | current_fragP; | |
8558 | current_fragP = current_fragP->fr_next) | |
8559 | { | |
8560 | if (current_fragP->tc_frag_data.is_loop_target | |
8561 | && current_fragP != current_target) | |
05d58145 | 8562 | return offset; |
e0001a05 NC |
8563 | |
8564 | offset += unrelaxed_frag_min_size (current_fragP); | |
8565 | ||
05d58145 | 8566 | if (offset >= max_size) |
e0001a05 NC |
8567 | return max_size; |
8568 | } | |
8569 | return max_size; | |
8570 | } | |
8571 | ||
8572 | ||
d77b99c9 | 8573 | static offsetT |
7fa3d080 | 8574 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 8575 | { |
d77b99c9 | 8576 | offsetT size = fragP->fr_fix; |
e0001a05 | 8577 | |
d77b99c9 | 8578 | /* Add fill size. */ |
e0001a05 NC |
8579 | if (fragP->fr_type == rs_fill) |
8580 | size += fragP->fr_offset; | |
8581 | ||
8582 | return size; | |
8583 | } | |
8584 | ||
8585 | ||
d77b99c9 | 8586 | static offsetT |
7fa3d080 | 8587 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 8588 | { |
d77b99c9 | 8589 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
8590 | switch (fragP->fr_type) |
8591 | { | |
8592 | case 0: | |
c138bc38 | 8593 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
8594 | end up with type 0. */ |
8595 | break; | |
8596 | case rs_fill: | |
8597 | case rs_org: | |
8598 | case rs_space: | |
8599 | size += fragP->fr_offset; | |
8600 | break; | |
8601 | case rs_align: | |
8602 | case rs_align_code: | |
8603 | case rs_align_test: | |
8604 | case rs_leb128: | |
8605 | case rs_cfa: | |
8606 | case rs_dwarf2dbg: | |
b52c4ee4 | 8607 | case rs_sframe: |
43cd72b9 BW |
8608 | /* No further adjustments needed. */ |
8609 | break; | |
8610 | case rs_machine_dependent: | |
8611 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
8612 | size += fragP->fr_var; | |
8613 | break; | |
8614 | default: | |
8615 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 8616 | gas_assert (0); |
43cd72b9 BW |
8617 | break; |
8618 | } | |
8619 | ||
8620 | return size; | |
8621 | } | |
8622 | ||
8623 | ||
e0001a05 NC |
8624 | /* Re-process all of the fragments looking to convert all |
8625 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
8626 | ||
8627 | A) | |
8628 | 1) the instruction size count to the loop end label | |
8629 | is too short (<= 2 instructions), | |
8630 | 2) loop has a jump or branch in it | |
8631 | ||
8632 | or B) | |
43cd72b9 | 8633 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
8634 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
8635 | 3) the instruction size count to the loop end label is too short | |
8636 | (<= 2 instructions) | |
8637 | then convert this frag (and maybe the next one) to generate a NOP. | |
8638 | In any case close it off with a .fill 0. */ | |
8639 | ||
5b7c81bd AM |
8640 | static int count_insns_to_loop_end (fragS *, bool, int); |
8641 | static bool branch_before_loop_end (fragS *); | |
7fa3d080 | 8642 | |
e0001a05 | 8643 | static void |
7fa3d080 | 8644 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
8645 | { |
8646 | frchainS *frchP; | |
c9049d30 | 8647 | asection *s; |
e0001a05 NC |
8648 | |
8649 | /* When this routine is called, all of the subsections are still intact | |
8650 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8651 | for (s = stdoutput->sections; s; s = s->next) |
8652 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8653 | { | |
8654 | fragS *fragP; | |
c9049d30 | 8655 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; |
e0001a05 | 8656 | |
c9049d30 AM |
8657 | /* Walk over all of the fragments in a subsection. */ |
8658 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8659 | { | |
8660 | if (fragP->fr_type == rs_machine_dependent | |
8661 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8662 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
8663 | { | |
8664 | TInsn t_insn; | |
8665 | fragS *loop_frag = next_non_empty_frag (fragP); | |
8666 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
c9049d30 | 8667 | current_opcode = t_insn.opcode; |
9c2799c2 | 8668 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 8669 | current_opcode) == 1); |
c9049d30 | 8670 | } |
e0001a05 | 8671 | |
c9049d30 AM |
8672 | if (fragP->fr_type == rs_machine_dependent |
8673 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8674 | { | |
5b7c81bd | 8675 | if (count_insns_to_loop_end (fragP->fr_next, true, 3) < 3 |
c9049d30 AM |
8676 | && (branch_before_loop_end (fragP->fr_next) |
8677 | || (workaround_all_short_loops | |
8678 | && current_opcode != XTENSA_UNDEFINED | |
8679 | && current_opcode != xtensa_loop_opcode))) | |
8680 | { | |
8681 | if (fragP->tc_frag_data.is_no_transform) | |
8682 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
8683 | else | |
8684 | relax_frag_add_nop (fragP); | |
8685 | } | |
8686 | frag_wane (fragP); | |
8687 | } | |
8688 | } | |
8689 | } | |
e0001a05 NC |
8690 | } |
8691 | ||
8692 | ||
d77b99c9 | 8693 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 8694 | |
d77b99c9 | 8695 | static int |
7fa3d080 | 8696 | count_insns_to_loop_end (fragS *base_fragP, |
5b7c81bd | 8697 | bool count_relax_add, |
d77b99c9 | 8698 | int max_count) |
e0001a05 NC |
8699 | { |
8700 | fragS *fragP = NULL; | |
d77b99c9 | 8701 | int insn_count = 0; |
e0001a05 NC |
8702 | |
8703 | fragP = base_fragP; | |
8704 | ||
8705 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
8706 | { | |
8707 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
8708 | if (insn_count >= max_count) | |
8709 | return max_count; | |
8710 | ||
8711 | if (count_relax_add) | |
8712 | { | |
8713 | if (fragP->fr_type == rs_machine_dependent | |
8714 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8715 | { | |
8716 | /* In order to add the appropriate number of | |
8717 | NOPs, we count an instruction for downstream | |
8718 | occurrences. */ | |
8719 | insn_count++; | |
8720 | if (insn_count >= max_count) | |
8721 | return max_count; | |
8722 | } | |
8723 | } | |
8724 | } | |
8725 | return insn_count; | |
8726 | } | |
8727 | ||
8728 | ||
d77b99c9 | 8729 | static int |
7fa3d080 | 8730 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 8731 | { |
43cd72b9 BW |
8732 | xtensa_isa isa = xtensa_default_isa; |
8733 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 8734 | int insn_count = 0; |
871a6bd2 | 8735 | unsigned int offset = 0; |
e0001a05 NC |
8736 | |
8737 | if (!fragP->tc_frag_data.is_insn) | |
8738 | return insn_count; | |
8739 | ||
43cd72b9 BW |
8740 | if (!insnbuf) |
8741 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8742 | ||
e0001a05 NC |
8743 | /* Decode the fixed instructions. */ |
8744 | while (offset < fragP->fr_fix) | |
8745 | { | |
43cd72b9 BW |
8746 | xtensa_format fmt; |
8747 | ||
d77b99c9 BW |
8748 | xtensa_insnbuf_from_chars |
8749 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8750 | fmt = xtensa_format_decode (isa, insnbuf); |
8751 | ||
8752 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
8753 | { |
8754 | as_fatal (_("undecodable instruction in instruction frag")); | |
8755 | return insn_count; | |
8756 | } | |
43cd72b9 | 8757 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8758 | insn_count++; |
8759 | } | |
8760 | ||
8761 | return insn_count; | |
8762 | } | |
8763 | ||
8764 | ||
5b7c81bd | 8765 | static bool unrelaxed_frag_has_b_j (fragS *); |
7fa3d080 | 8766 | |
5b7c81bd | 8767 | static bool |
7fa3d080 | 8768 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
8769 | { |
8770 | fragS *fragP; | |
8771 | ||
8772 | for (fragP = base_fragP; | |
8773 | fragP && !fragP->tc_frag_data.is_loop_target; | |
8774 | fragP = fragP->fr_next) | |
8775 | { | |
8776 | if (unrelaxed_frag_has_b_j (fragP)) | |
5b7c81bd | 8777 | return true; |
e0001a05 | 8778 | } |
5b7c81bd | 8779 | return false; |
e0001a05 NC |
8780 | } |
8781 | ||
8782 | ||
5b7c81bd | 8783 | static bool |
7fa3d080 | 8784 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 8785 | { |
43cd72b9 BW |
8786 | static xtensa_insnbuf insnbuf = NULL; |
8787 | xtensa_isa isa = xtensa_default_isa; | |
871a6bd2 | 8788 | unsigned int offset = 0; |
e0001a05 NC |
8789 | |
8790 | if (!fragP->tc_frag_data.is_insn) | |
5b7c81bd | 8791 | return false; |
e0001a05 | 8792 | |
43cd72b9 BW |
8793 | if (!insnbuf) |
8794 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8795 | ||
e0001a05 NC |
8796 | /* Decode the fixed instructions. */ |
8797 | while (offset < fragP->fr_fix) | |
8798 | { | |
43cd72b9 BW |
8799 | xtensa_format fmt; |
8800 | int slot; | |
8801 | ||
d77b99c9 BW |
8802 | xtensa_insnbuf_from_chars |
8803 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8804 | fmt = xtensa_format_decode (isa, insnbuf); |
8805 | if (fmt == XTENSA_UNDEFINED) | |
5b7c81bd | 8806 | return false; |
43cd72b9 BW |
8807 | |
8808 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8809 | { |
43cd72b9 BW |
8810 | xtensa_opcode opcode = |
8811 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8812 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8813 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
5b7c81bd | 8814 | return true; |
e0001a05 | 8815 | } |
43cd72b9 | 8816 | offset += xtensa_format_length (isa, fmt); |
e0001a05 | 8817 | } |
5b7c81bd | 8818 | return false; |
e0001a05 NC |
8819 | } |
8820 | ||
8821 | ||
8822 | /* Checks to be made after initial assembly but before relaxation. */ | |
8823 | ||
5b7c81bd AM |
8824 | static bool is_empty_loop (const TInsn *, fragS *); |
8825 | static bool is_local_forward_loop (const TInsn *, fragS *); | |
7fa3d080 | 8826 | |
e0001a05 | 8827 | static void |
7fa3d080 | 8828 | xtensa_sanity_check (void) |
e0001a05 | 8829 | { |
3b4dbbbf | 8830 | const char *file_name; |
d77b99c9 | 8831 | unsigned line; |
e0001a05 | 8832 | frchainS *frchP; |
c9049d30 | 8833 | asection *s; |
e0001a05 | 8834 | |
3b4dbbbf | 8835 | file_name = as_where (&line); |
c9049d30 AM |
8836 | for (s = stdoutput->sections; s; s = s->next) |
8837 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8838 | { | |
8839 | fragS *fragP; | |
e0001a05 | 8840 | |
c9049d30 AM |
8841 | /* Walk over all of the fragments in a subsection. */ |
8842 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8843 | { | |
c9049d30 | 8844 | if (fragP->fr_type == rs_machine_dependent |
3739860c | 8845 | && fragP->fr_subtype == RELAX_SLOTS |
a7284bf1 | 8846 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) |
c9049d30 AM |
8847 | { |
8848 | static xtensa_insnbuf insnbuf = NULL; | |
8849 | TInsn t_insn; | |
8850 | ||
8851 | if (fragP->fr_opcode != NULL) | |
8852 | { | |
8853 | if (!insnbuf) | |
8854 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8855 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8856 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8857 | ||
8858 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8859 | t_insn.opcode) == 1) | |
8860 | { | |
8861 | if (is_empty_loop (&t_insn, fragP)) | |
8862 | { | |
8863 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8864 | as_bad (_("invalid empty loop")); | |
8865 | } | |
8866 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8867 | { | |
8868 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8869 | as_bad (_("loop target does not follow " | |
8870 | "loop instruction in section")); | |
8871 | } | |
8872 | } | |
8873 | } | |
8874 | } | |
8875 | } | |
8876 | } | |
e0001a05 NC |
8877 | new_logical_line (file_name, line); |
8878 | } | |
8879 | ||
8880 | ||
8881 | #define LOOP_IMMED_OPN 1 | |
8882 | ||
43cd72b9 | 8883 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8884 | |
5b7c81bd | 8885 | static bool |
7fa3d080 | 8886 | is_empty_loop (const TInsn *insn, fragS *fragP) |
e0001a05 | 8887 | { |
91d6fa6a | 8888 | const expressionS *exp; |
e0001a05 NC |
8889 | symbolS *symbolP; |
8890 | fragS *next_fragP; | |
8891 | ||
8892 | if (insn->insn_type != ITYPE_INSN) | |
5b7c81bd | 8893 | return false; |
e0001a05 | 8894 | |
43cd72b9 | 8895 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
5b7c81bd | 8896 | return false; |
e0001a05 NC |
8897 | |
8898 | if (insn->ntok <= LOOP_IMMED_OPN) | |
5b7c81bd | 8899 | return false; |
e0001a05 | 8900 | |
91d6fa6a | 8901 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8902 | |
91d6fa6a | 8903 | if (exp->X_op != O_symbol) |
5b7c81bd | 8904 | return false; |
e0001a05 | 8905 | |
91d6fa6a | 8906 | symbolP = exp->X_add_symbol; |
e0001a05 | 8907 | if (!symbolP) |
5b7c81bd | 8908 | return false; |
e0001a05 NC |
8909 | |
8910 | if (symbol_get_frag (symbolP) == NULL) | |
5b7c81bd | 8911 | return false; |
e0001a05 NC |
8912 | |
8913 | if (S_GET_VALUE (symbolP) != 0) | |
5b7c81bd | 8914 | return false; |
e0001a05 NC |
8915 | |
8916 | /* Walk through the zero-size fragments from this one. If we find | |
8917 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8918 | |
e0001a05 NC |
8919 | for (next_fragP = fragP->fr_next; |
8920 | next_fragP != NULL; | |
8921 | next_fragP = next_fragP->fr_next) | |
8922 | { | |
8923 | if (next_fragP == symbol_get_frag (symbolP)) | |
5b7c81bd | 8924 | return true; |
e0001a05 | 8925 | if (next_fragP->fr_fix != 0) |
5b7c81bd | 8926 | return false; |
e0001a05 | 8927 | } |
5b7c81bd | 8928 | return false; |
e0001a05 NC |
8929 | } |
8930 | ||
8931 | ||
5b7c81bd | 8932 | static bool |
7fa3d080 | 8933 | is_local_forward_loop (const TInsn *insn, fragS *fragP) |
e0001a05 | 8934 | { |
91d6fa6a | 8935 | const expressionS *exp; |
e0001a05 NC |
8936 | symbolS *symbolP; |
8937 | fragS *next_fragP; | |
8938 | ||
8939 | if (insn->insn_type != ITYPE_INSN) | |
5b7c81bd | 8940 | return false; |
e0001a05 | 8941 | |
64b607e6 | 8942 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
5b7c81bd | 8943 | return false; |
e0001a05 NC |
8944 | |
8945 | if (insn->ntok <= LOOP_IMMED_OPN) | |
5b7c81bd | 8946 | return false; |
e0001a05 | 8947 | |
91d6fa6a | 8948 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8949 | |
91d6fa6a | 8950 | if (exp->X_op != O_symbol) |
5b7c81bd | 8951 | return false; |
e0001a05 | 8952 | |
91d6fa6a | 8953 | symbolP = exp->X_add_symbol; |
e0001a05 | 8954 | if (!symbolP) |
5b7c81bd | 8955 | return false; |
e0001a05 NC |
8956 | |
8957 | if (symbol_get_frag (symbolP) == NULL) | |
5b7c81bd | 8958 | return false; |
e0001a05 NC |
8959 | |
8960 | /* Walk through fragments until we find the target. | |
8961 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8962 | |
e0001a05 NC |
8963 | for (next_fragP = fragP->fr_next; |
8964 | next_fragP != NULL; | |
8965 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8966 | { |
8967 | if (next_fragP == symbol_get_frag (symbolP)) | |
5b7c81bd | 8968 | return true; |
43cd72b9 | 8969 | } |
e0001a05 | 8970 | |
5b7c81bd | 8971 | return false; |
e0001a05 NC |
8972 | } |
8973 | ||
2caa7ca0 BW |
8974 | #define XTINFO_NAME "Xtensa_Info" |
8975 | #define XTINFO_NAMESZ 12 | |
8976 | #define XTINFO_TYPE 1 | |
8977 | ||
8978 | static void | |
8979 | xtensa_add_config_info (void) | |
8980 | { | |
8981 | asection *info_sec; | |
ebfd369c AM |
8982 | char data[100]; |
8983 | char *p; | |
2caa7ca0 BW |
8984 | int sz; |
8985 | ||
8986 | info_sec = subseg_new (".xtensa.info", 0); | |
fd361982 | 8987 | bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY); |
2caa7ca0 | 8988 | |
ebfd369c AM |
8989 | sz = 1 + sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", |
8990 | XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ()); | |
2caa7ca0 BW |
8991 | |
8992 | /* Add enough null terminators to pad to a word boundary. */ | |
8993 | do | |
8994 | data[sz++] = 0; | |
8995 | while ((sz & 3) != 0); | |
8996 | ||
8997 | /* Follow the standard note section layout: | |
8998 | First write the length of the name string. */ | |
8999 | p = frag_more (4); | |
9000 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
9001 | ||
9002 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
9003 | p = frag_more (4); | |
9004 | md_number_to_chars (p, (valueT) sz, 4); | |
9005 | ||
9006 | /* Write the note type. */ | |
9007 | p = frag_more (4); | |
9008 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
9009 | ||
9010 | /* Write the name field. */ | |
9011 | p = frag_more (XTINFO_NAMESZ); | |
9012 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
9013 | ||
9014 | /* Finally, write the descriptor. */ | |
9015 | p = frag_more (sz); | |
9016 | memcpy (p, data, sz); | |
2caa7ca0 BW |
9017 | } |
9018 | ||
e0001a05 NC |
9019 | \f |
9020 | /* Alignment Functions. */ | |
9021 | ||
d77b99c9 BW |
9022 | static int |
9023 | get_text_align_power (unsigned target_size) | |
e0001a05 | 9024 | { |
03aaa593 BW |
9025 | if (target_size <= 4) |
9026 | return 2; | |
19ef5f3d SA |
9027 | |
9028 | if (target_size <= 8) | |
9029 | return 3; | |
9030 | ||
9031 | if (target_size <= 16) | |
9032 | return 4; | |
9033 | ||
9034 | if (target_size <= 32) | |
9035 | return 5; | |
9036 | ||
9037 | if (target_size <= 64) | |
9038 | return 6; | |
9039 | ||
9040 | if (target_size <= 128) | |
9041 | return 7; | |
9042 | ||
9043 | if (target_size <= 256) | |
9044 | return 8; | |
9045 | ||
9046 | if (target_size <= 512) | |
9047 | return 9; | |
9048 | ||
9049 | if (target_size <= 1024) | |
9050 | return 10; | |
9051 | ||
9052 | gas_assert (0); | |
9053 | return 0; | |
e0001a05 NC |
9054 | } |
9055 | ||
9056 | ||
d77b99c9 | 9057 | static int |
7fa3d080 | 9058 | get_text_align_max_fill_size (int align_pow, |
5b7c81bd AM |
9059 | bool use_nops, |
9060 | bool use_no_density) | |
e0001a05 NC |
9061 | { |
9062 | if (!use_nops) | |
9063 | return (1 << align_pow); | |
9064 | if (use_no_density) | |
9065 | return 3 * (1 << align_pow); | |
9066 | ||
9067 | return 1 + (1 << align_pow); | |
9068 | } | |
9069 | ||
9070 | ||
d77b99c9 BW |
9071 | /* Calculate the minimum bytes of fill needed at "address" to align a |
9072 | target instruction of size "target_size" so that it does not cross a | |
9073 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
9074 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
9075 | be filled by NOP instructions. */ | |
e0001a05 | 9076 | |
d77b99c9 | 9077 | static int |
7fa3d080 BW |
9078 | get_text_align_fill_size (addressT address, |
9079 | int align_pow, | |
9080 | int target_size, | |
5b7c81bd AM |
9081 | bool use_nops, |
9082 | bool use_no_density) | |
e0001a05 | 9083 | { |
d77b99c9 | 9084 | addressT alignment, fill, fill_limit, fill_step; |
5b7c81bd | 9085 | bool skip_one = false; |
e0001a05 | 9086 | |
d77b99c9 | 9087 | alignment = (1 << align_pow); |
9c2799c2 | 9088 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 9089 | |
e0001a05 NC |
9090 | if (!use_nops) |
9091 | { | |
d77b99c9 BW |
9092 | fill_limit = alignment; |
9093 | fill_step = 1; | |
e0001a05 | 9094 | } |
d77b99c9 | 9095 | else if (!use_no_density) |
e0001a05 | 9096 | { |
d77b99c9 BW |
9097 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
9098 | fill_limit = alignment * 2; | |
9099 | fill_step = 1; | |
5b7c81bd | 9100 | skip_one = true; |
e0001a05 NC |
9101 | } |
9102 | else | |
9103 | { | |
d77b99c9 BW |
9104 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
9105 | fill_limit = alignment * 3; | |
9106 | fill_step = 3; | |
9107 | } | |
e0001a05 | 9108 | |
d77b99c9 BW |
9109 | /* Try all fill sizes until finding one that works. */ |
9110 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
9111 | { | |
9112 | if (skip_one && fill == 1) | |
9113 | continue; | |
9114 | if ((address + fill) >> align_pow | |
9115 | == (address + fill + target_size - 1) >> align_pow) | |
9116 | return fill; | |
e0001a05 | 9117 | } |
9c2799c2 | 9118 | gas_assert (0); |
e0001a05 NC |
9119 | return 0; |
9120 | } | |
9121 | ||
9122 | ||
664df4e4 BW |
9123 | static int |
9124 | branch_align_power (segT sec) | |
9125 | { | |
19ef5f3d SA |
9126 | /* If the Xtensa processor has a fetch width of X, and |
9127 | the section is aligned to at least that boundary, then a branch | |
9128 | target need only fit within that aligned block of memory to avoid | |
9129 | a stall. Otherwise, try to fit branch targets within 4-byte | |
9130 | aligned blocks (which may be insufficient, e.g., if the section | |
9131 | has no alignment, but it's good enough). */ | |
9132 | int fetch_align = get_text_align_power(xtensa_fetch_width); | |
9133 | int sec_align = get_recorded_alignment (sec); | |
9134 | ||
9135 | if (sec_align >= fetch_align) | |
9136 | return fetch_align; | |
664df4e4 BW |
9137 | |
9138 | return 2; | |
9139 | } | |
9140 | ||
9141 | ||
e0001a05 NC |
9142 | /* This will assert if it is not possible. */ |
9143 | ||
d77b99c9 | 9144 | static int |
5b7c81bd | 9145 | get_text_align_nop_count (offsetT fill_size, bool use_no_density) |
e0001a05 | 9146 | { |
d77b99c9 BW |
9147 | int count = 0; |
9148 | ||
e0001a05 NC |
9149 | if (use_no_density) |
9150 | { | |
9c2799c2 | 9151 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
9152 | return (fill_size / 3); |
9153 | } | |
9154 | ||
9c2799c2 | 9155 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
9156 | |
9157 | while (fill_size > 1) | |
9158 | { | |
d77b99c9 | 9159 | int insn_size = 3; |
e0001a05 NC |
9160 | if (fill_size == 2 || fill_size == 4) |
9161 | insn_size = 2; | |
9162 | fill_size -= insn_size; | |
9163 | count++; | |
9164 | } | |
9c2799c2 | 9165 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
9166 | return count; |
9167 | } | |
9168 | ||
9169 | ||
d77b99c9 BW |
9170 | static int |
9171 | get_text_align_nth_nop_size (offsetT fill_size, | |
9172 | int n, | |
5b7c81bd | 9173 | bool use_no_density) |
e0001a05 | 9174 | { |
d77b99c9 | 9175 | int count = 0; |
e0001a05 NC |
9176 | |
9177 | if (use_no_density) | |
9178 | return 3; | |
9179 | ||
9c2799c2 | 9180 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 9181 | |
e0001a05 NC |
9182 | while (fill_size > 1) |
9183 | { | |
d77b99c9 | 9184 | int insn_size = 3; |
e0001a05 NC |
9185 | if (fill_size == 2 || fill_size == 4) |
9186 | insn_size = 2; | |
9187 | fill_size -= insn_size; | |
9188 | count++; | |
9189 | if (n + 1 == count) | |
9190 | return insn_size; | |
9191 | } | |
9c2799c2 | 9192 | gas_assert (0); |
e0001a05 NC |
9193 | return 0; |
9194 | } | |
9195 | ||
9196 | ||
9197 | /* For the given fragment, find the appropriate address | |
9198 | for it to begin at if we are using NOPs to align it. */ | |
9199 | ||
9200 | static addressT | |
7fa3d080 | 9201 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 9202 | { |
43cd72b9 BW |
9203 | /* The rule is: get next fragment's FIRST instruction. Find |
9204 | the smallest number of bytes that need to be added to | |
9205 | ensure that the next fragment's FIRST instruction will fit | |
9206 | in a single word. | |
c138bc38 | 9207 | |
43cd72b9 BW |
9208 | E.G., 2 bytes : 0, 1, 2 mod 4 |
9209 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 9210 | |
43cd72b9 BW |
9211 | If the FIRST instruction MIGHT be relaxed, |
9212 | assume that it will become a 3-byte instruction. | |
c138bc38 | 9213 | |
43cd72b9 BW |
9214 | Note again here that LOOP instructions are not bundleable, |
9215 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 9216 | |
d77b99c9 | 9217 | int fill_size = 0; |
43cd72b9 BW |
9218 | int first_insn_size; |
9219 | int loop_insn_size; | |
9220 | addressT pre_opcode_bytes; | |
d77b99c9 | 9221 | int align_power; |
43cd72b9 BW |
9222 | fragS *first_insn; |
9223 | xtensa_opcode opcode; | |
5b7c81bd | 9224 | bool is_loop; |
e0001a05 | 9225 | |
9c2799c2 NC |
9226 | gas_assert (fragP->fr_type == rs_machine_dependent); |
9227 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 9228 | |
43cd72b9 BW |
9229 | /* Find the loop frag. */ |
9230 | first_insn = next_non_empty_frag (fragP); | |
9231 | /* Now find the first insn frag. */ | |
9232 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 9233 | |
43cd72b9 | 9234 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 9235 | gas_assert (is_loop); |
43cd72b9 | 9236 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 9237 | |
43cd72b9 BW |
9238 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
9239 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 9240 | |
43cd72b9 BW |
9241 | /* For loops, the alignment depends on the size of the |
9242 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 9243 | |
43cd72b9 | 9244 | if (first_insn == NULL) |
03aaa593 BW |
9245 | first_insn_size = xtensa_fetch_width; |
9246 | else | |
9247 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 9248 | |
43cd72b9 | 9249 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
9250 | align_power = get_text_align_power (first_insn_size); |
9251 | record_alignment (now_seg, align_power); | |
c138bc38 | 9252 | |
43cd72b9 | 9253 | fill_size = get_text_align_fill_size |
5b7c81bd | 9254 | (address + pre_opcode_bytes, align_power, first_insn_size, true, |
d77b99c9 | 9255 | fragP->tc_frag_data.is_no_density); |
e0001a05 NC |
9256 | |
9257 | return address + fill_size; | |
9258 | } | |
9259 | ||
9260 | ||
43cd72b9 BW |
9261 | /* 3 mechanisms for relaxing an alignment: |
9262 | ||
9263 | Align to a power of 2. | |
9264 | Align so the next fragment's instruction does not cross a word boundary. | |
9265 | Align the current instruction so that if the next instruction | |
9266 | were 3 bytes, it would not cross a word boundary. | |
9267 | ||
e0001a05 NC |
9268 | We can align with: |
9269 | ||
43cd72b9 BW |
9270 | zeros - This is easy; always insert zeros. |
9271 | nops - 3-byte and 2-byte instructions | |
9272 | 2 - 2-byte nop | |
9273 | 3 - 3-byte nop | |
9274 | 4 - 2 2-byte nops | |
9275 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
9276 | widening - widen previous instructions. */ |
9277 | ||
d77b99c9 BW |
9278 | static offsetT |
9279 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 9280 | { |
43cd72b9 BW |
9281 | addressT target_address, loop_insn_offset; |
9282 | int target_size; | |
9283 | xtensa_opcode loop_opcode; | |
5b7c81bd | 9284 | bool is_loop; |
d77b99c9 BW |
9285 | int align_power; |
9286 | offsetT opt_diff; | |
5f9084e9 | 9287 | offsetT branch_align; |
def13efb | 9288 | fragS *loop_frag; |
e0001a05 | 9289 | |
9c2799c2 | 9290 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 9291 | switch (fragP->fr_subtype) |
e0001a05 | 9292 | { |
43cd72b9 BW |
9293 | case RELAX_DESIRE_ALIGN: |
9294 | target_size = next_frag_format_size (fragP); | |
9295 | if (target_size == XTENSA_UNDEFINED) | |
9296 | target_size = 3; | |
664df4e4 BW |
9297 | align_power = branch_align_power (now_seg); |
9298 | branch_align = 1 << align_power; | |
0e5cd789 BW |
9299 | /* Don't count on the section alignment being as large as the target. */ |
9300 | if (target_size > branch_align) | |
9301 | target_size = branch_align; | |
d77b99c9 | 9302 | opt_diff = get_text_align_fill_size (address, align_power, |
5b7c81bd | 9303 | target_size, false, false); |
43cd72b9 | 9304 | |
664df4e4 BW |
9305 | *max_diff = (opt_diff + branch_align |
9306 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 9307 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9308 | return opt_diff; |
e0001a05 | 9309 | |
43cd72b9 | 9310 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
9311 | /* The next non-empty frag after this one holds the LOOP instruction |
9312 | that needs to be aligned. The required alignment depends on the | |
9313 | size of the next non-empty frag after the loop frag, i.e., the | |
9314 | first instruction in the loop. */ | |
9315 | loop_frag = next_non_empty_frag (fragP); | |
9316 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
9317 | loop_insn_offset = 0; |
9318 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 9319 | gas_assert (is_loop); |
43cd72b9 BW |
9320 | |
9321 | /* If the loop has been expanded then the LOOP instruction | |
9322 | could be at an offset from this fragment. */ | |
def13efb | 9323 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
9324 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
9325 | ||
43cd72b9 BW |
9326 | /* In an ideal world, which is what we are shooting for here, |
9327 | we wouldn't need to use any NOPs immediately prior to the | |
9328 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
9329 | will call get_noop_aligned_address. */ | |
9330 | target_address = | |
9331 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 9332 | align_power = get_text_align_power (target_size); |
d77b99c9 | 9333 | opt_diff = get_text_align_fill_size (target_address, align_power, |
5b7c81bd | 9334 | target_size, false, false); |
43cd72b9 BW |
9335 | |
9336 | *max_diff = xtensa_fetch_width | |
9337 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
9338 | - target_size + opt_diff; | |
9c2799c2 | 9339 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9340 | return opt_diff; |
e0001a05 | 9341 | |
43cd72b9 BW |
9342 | default: |
9343 | break; | |
e0001a05 | 9344 | } |
9c2799c2 | 9345 | gas_assert (0); |
43cd72b9 | 9346 | return 0; |
e0001a05 NC |
9347 | } |
9348 | ||
9349 | \f | |
9350 | /* md_relax_frag Hook and Helper Functions. */ | |
9351 | ||
7fa3d080 BW |
9352 | static long relax_frag_loop_align (fragS *, long); |
9353 | static long relax_frag_for_align (fragS *, long); | |
9354 | static long relax_frag_immed | |
5b7c81bd | 9355 | (segT, fragS *, long, int, xtensa_format, int, int *, bool); |
7fa3d080 | 9356 | |
fe6c2f1b MF |
9357 | /* Get projected address for the first fulcrum on a path from source to |
9358 | target. */ | |
9359 | static addressT xg_get_fulcrum (addressT source, addressT target) | |
b76f99d7 | 9360 | { |
fe6c2f1b MF |
9361 | offsetT delta = target - source; |
9362 | int n; | |
b76f99d7 | 9363 | |
fe6c2f1b MF |
9364 | n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN); |
9365 | return source + delta / n; | |
9366 | } | |
b76f99d7 | 9367 | |
fe6c2f1b MF |
9368 | /* Given trampoline index, source and target of a jump find the best |
9369 | candidate trampoline for the first fulcrum. The best trampoline is | |
9370 | the one in the reach of "j' instruction from the source, closest to | |
9371 | the projected fulcrum address, and preferrably w/o a jump around or | |
9372 | with already initialized jump around. */ | |
9373 | static size_t xg_find_best_trampoline (struct trampoline_index *idx, | |
9374 | addressT source, addressT target) | |
b76f99d7 | 9375 | { |
fe6c2f1b MF |
9376 | addressT fulcrum = xg_get_fulcrum (source, target); |
9377 | size_t dist = 0; | |
9378 | size_t best = -1; | |
9379 | size_t base_tr = xg_find_trampoline (idx, fulcrum); | |
9380 | int checked = 1; | |
b76f99d7 | 9381 | |
fe6c2f1b MF |
9382 | /* Check trampoline frags around the base_tr to find the best. */ |
9383 | for (dist = 0; checked; ++dist) | |
b76f99d7 | 9384 | { |
fe6c2f1b MF |
9385 | int i; |
9386 | size_t tr = base_tr - dist; | |
9387 | ||
9388 | checked = 0; | |
9389 | ||
9390 | /* Trampolines are checked in the following order: | |
9391 | base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */ | |
9392 | for (i = 0; i < 2; ++i, tr = base_tr + dist + 1) | |
9393 | if (tr < idx->n_entries) | |
9394 | { | |
9395 | fragS *trampoline_frag = idx->entry[tr]; | |
9396 | offsetT off; | |
9397 | ||
9398 | /* Don't check trampolines outside source - target interval. */ | |
9399 | if ((trampoline_frag->fr_address < source && | |
9400 | trampoline_frag->fr_address < target) || | |
9401 | (trampoline_frag->fr_address > source && | |
9402 | trampoline_frag->fr_address > target)) | |
9403 | continue; | |
9404 | ||
db5d5ad1 MF |
9405 | /* Don't choose trampoline that contains the source. */ |
9406 | if (source >= trampoline_frag->fr_address | |
9407 | && source <= trampoline_frag->fr_address + | |
9408 | trampoline_frag->fr_fix) | |
9409 | continue; | |
9410 | ||
fe6c2f1b MF |
9411 | off = trampoline_frag->fr_address - fulcrum; |
9412 | /* Stop if some trampoline is found and the search is more than | |
9413 | J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump | |
9414 | around is nice, but it shouldn't have much overhead. */ | |
9415 | if (best < idx->n_entries && labs (off) > J_RANGE / 4) | |
9416 | return best; | |
9417 | ||
9418 | off = trampoline_frag->fr_address - source; | |
9419 | if (labs (off) < J_RANGE - J_MARGIN) | |
9420 | { | |
9421 | ++checked; | |
9422 | /* Stop if a trampoline w/o jump around is found or initialized | |
9423 | trampoline with jump around is found. */ | |
9424 | if (!trampoline_frag->tc_frag_data.needs_jump_around || | |
9425 | trampoline_frag->fr_fix) | |
9426 | return tr; | |
9427 | else if (best >= idx->n_entries) | |
9428 | best = tr; | |
9429 | } | |
9430 | } | |
b76f99d7 | 9431 | } |
fe6c2f1b MF |
9432 | |
9433 | if (best < idx->n_entries) | |
9434 | return best; | |
9435 | else | |
9436 | as_fatal (_("cannot find suitable trampoline")); | |
b76f99d7 MF |
9437 | } |
9438 | ||
fe6c2f1b MF |
9439 | static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP) |
9440 | { | |
9441 | symbolS *s = fixP->fx_addsy; | |
9442 | addressT source = fixP->fx_frag->fr_address; | |
9443 | addressT target = S_GET_VALUE (s) + fixP->fx_offset; | |
9444 | size_t tr = xg_find_best_trampoline (idx, source, target); | |
9445 | fragS *trampoline_frag = idx->entry[tr]; | |
9446 | fixS *newfixP; | |
9447 | ||
9448 | init_trampoline_frag (trampoline_frag); | |
9449 | newfixP = xg_append_jump (trampoline_frag, | |
9450 | fixP->fx_addsy, fixP->fx_offset); | |
9451 | ||
9452 | /* Adjust the fixup for the original "j" instruction to | |
9453 | point to the newly added jump. */ | |
9454 | fixP->fx_addsy = trampoline_frag->fr_symbol; | |
9455 | fixP->fx_offset = trampoline_frag->fr_fix - 3; | |
9456 | fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol; | |
9457 | fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3; | |
9458 | ||
5b7c81bd | 9459 | trampoline_frag->tc_frag_data.relax_seen = false; |
fe6c2f1b MF |
9460 | |
9461 | if (xg_is_trampoline_frag_full (trampoline_frag)) | |
9462 | xg_remove_trampoline_from_index (idx, tr); | |
9463 | ||
9464 | return newfixP; | |
9465 | } | |
9466 | ||
5b7c81bd | 9467 | static bool xg_is_relaxable_fixup (fixS *fixP) |
b76f99d7 MF |
9468 | { |
9469 | xtensa_isa isa = xtensa_default_isa; | |
fe6c2f1b MF |
9470 | addressT addr = fixP->fx_frag->fr_address; |
9471 | addressT target; | |
9472 | offsetT delta; | |
b76f99d7 MF |
9473 | symbolS *s = fixP->fx_addsy; |
9474 | int slot; | |
9475 | xtensa_format fmt; | |
9476 | xtensa_opcode opcode; | |
9477 | ||
9478 | if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || | |
9479 | fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) | |
5b7c81bd | 9480 | return false; |
fe6c2f1b MF |
9481 | |
9482 | target = S_GET_VALUE (s) + fixP->fx_offset; | |
b76f99d7 MF |
9483 | delta = target - addr; |
9484 | ||
fe6c2f1b | 9485 | if (labs (delta) < J_RANGE - J_MARGIN) |
5b7c81bd | 9486 | return false; |
b76f99d7 MF |
9487 | |
9488 | xtensa_insnbuf_from_chars (isa, trampoline_buf, | |
9489 | (unsigned char *) fixP->fx_frag->fr_literal + | |
9490 | fixP->fx_where, 0); | |
9491 | fmt = xtensa_format_decode (isa, trampoline_buf); | |
9492 | gas_assert (fmt != XTENSA_UNDEFINED); | |
9493 | slot = fixP->tc_fix_data.slot; | |
9494 | xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); | |
9495 | opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); | |
fe6c2f1b | 9496 | return opcode == xtensa_j_opcode; |
b76f99d7 MF |
9497 | } |
9498 | ||
fe6c2f1b | 9499 | static void xg_relax_fixups (struct trampoline_seg *ts) |
b76f99d7 | 9500 | { |
fe6c2f1b MF |
9501 | struct trampoline_index *idx = &ts->index; |
9502 | segment_info_type *seginfo = seg_info (now_seg); | |
9503 | fixS *fx; | |
b76f99d7 | 9504 | |
fe6c2f1b | 9505 | for (fx = seginfo->fix_root; fx; fx = fx->fx_next) |
b76f99d7 | 9506 | { |
fe6c2f1b | 9507 | fixS *fixP = fx; |
148d6384 MF |
9508 | struct trampoline_chain *tc = NULL; |
9509 | ||
9510 | if (xg_is_relaxable_fixup (fixP)) | |
9511 | { | |
9512 | tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address, | |
9513 | &fixP->fx_addsy, &fixP->fx_offset); | |
9514 | if (!tc) | |
9515 | tc = xg_create_trampoline_chain (ts, fixP->fx_addsy, | |
9516 | fixP->fx_offset); | |
9517 | gas_assert (tc); | |
9518 | } | |
b76f99d7 | 9519 | |
fe6c2f1b | 9520 | while (xg_is_relaxable_fixup (fixP)) |
148d6384 MF |
9521 | { |
9522 | fixP = xg_relax_fixup (idx, fixP); | |
9523 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
9524 | fixP->fx_where); | |
9525 | } | |
b76f99d7 | 9526 | } |
b76f99d7 | 9527 | } |
7fa3d080 | 9528 | |
fe6c2f1b MF |
9529 | /* Given a trampoline frag relax all jumps that might want to use this |
9530 | trampoline. Only do real work once per relaxation cycle, when | |
9531 | xg_relax_trampoline is called for the first trampoline in the now_seg. | |
9532 | Don't use stretch, don't update new_stretch: place fulcrums with a | |
9533 | slack to tolerate code movement. In the worst case if a jump between | |
9534 | two trampolines wouldn't reach the next relaxation pass will fix it. */ | |
9535 | static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED, | |
9536 | long *new_stretch ATTRIBUTE_UNUSED) | |
120bc8b8 | 9537 | { |
fe6c2f1b | 9538 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
120bc8b8 | 9539 | |
fe6c2f1b MF |
9540 | if (ts->index.n_entries && ts->index.entry[0] == fragP) |
9541 | xg_relax_fixups (ts); | |
120bc8b8 MF |
9542 | } |
9543 | ||
e0001a05 NC |
9544 | /* Return the number of bytes added to this fragment, given that the |
9545 | input has been stretched already by "stretch". */ | |
9546 | ||
9547 | long | |
7fa3d080 | 9548 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 9549 | { |
43cd72b9 | 9550 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9551 | int unreported = fragP->tc_frag_data.unreported_expansion; |
9552 | long new_stretch = 0; | |
3b4dbbbf | 9553 | const char *file_name; |
d77b99c9 BW |
9554 | unsigned line; |
9555 | int lit_size; | |
43cd72b9 BW |
9556 | static xtensa_insnbuf vbuf = NULL; |
9557 | int slot, num_slots; | |
9558 | xtensa_format fmt; | |
e0001a05 | 9559 | |
3b4dbbbf | 9560 | file_name = as_where (&line); |
e0001a05 NC |
9561 | new_logical_line (fragP->fr_file, fragP->fr_line); |
9562 | ||
9563 | fragP->tc_frag_data.unreported_expansion = 0; | |
9564 | ||
9565 | switch (fragP->fr_subtype) | |
9566 | { | |
9567 | case RELAX_ALIGN_NEXT_OPCODE: | |
9568 | /* Always convert. */ | |
43cd72b9 BW |
9569 | if (fragP->tc_frag_data.relax_seen) |
9570 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
9571 | break; |
9572 | ||
9573 | case RELAX_LOOP_END: | |
9574 | /* Do nothing. */ | |
9575 | break; | |
9576 | ||
9577 | case RELAX_LOOP_END_ADD_NOP: | |
9578 | /* Add a NOP and switch to .fill 0. */ | |
9579 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 9580 | frag_wane (fragP); |
e0001a05 NC |
9581 | break; |
9582 | ||
9583 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 9584 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
9585 | it or not. */ |
9586 | break; | |
9587 | ||
9588 | case RELAX_LITERAL: | |
9589 | case RELAX_LITERAL_FINAL: | |
9590 | return 0; | |
9591 | ||
9592 | case RELAX_LITERAL_NR: | |
9593 | lit_size = 4; | |
9594 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9595 | gas_assert (unreported == lit_size); |
e0001a05 NC |
9596 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
9597 | fragP->fr_var -= lit_size; | |
9598 | fragP->fr_fix += lit_size; | |
9599 | new_stretch = 4; | |
9600 | break; | |
9601 | ||
43cd72b9 BW |
9602 | case RELAX_SLOTS: |
9603 | if (vbuf == NULL) | |
9604 | vbuf = xtensa_insnbuf_alloc (isa); | |
9605 | ||
d77b99c9 BW |
9606 | xtensa_insnbuf_from_chars |
9607 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
9608 | fmt = xtensa_format_decode (isa, vbuf); |
9609 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 9610 | |
43cd72b9 BW |
9611 | for (slot = 0; slot < num_slots; slot++) |
9612 | { | |
9613 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
9614 | { | |
9615 | case RELAX_NARROW: | |
9616 | if (fragP->tc_frag_data.relax_seen) | |
9617 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9618 | break; | |
9619 | ||
9620 | case RELAX_IMMED: | |
9621 | case RELAX_IMMED_STEP1: | |
9622 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9623 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9624 | /* Place the immediate. */ |
9625 | new_stretch += relax_frag_immed | |
9626 | (now_seg, fragP, stretch, | |
9627 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
5b7c81bd | 9628 | fmt, slot, stretched_p, false); |
43cd72b9 BW |
9629 | break; |
9630 | ||
9631 | default: | |
9632 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
9633 | break; | |
9634 | } | |
9635 | } | |
e0001a05 NC |
9636 | break; |
9637 | ||
9638 | case RELAX_LITERAL_POOL_BEGIN: | |
b46824bd MF |
9639 | if (fragP->fr_var != 0) |
9640 | { | |
9641 | /* We have a converted "candidate" literal pool; | |
9642 | assemble a jump around it. */ | |
9643 | TInsn insn; | |
9644 | if (!litpool_slotbuf) | |
9645 | { | |
9646 | litpool_buf = xtensa_insnbuf_alloc (isa); | |
9647 | litpool_slotbuf = xtensa_insnbuf_alloc (isa); | |
9648 | } | |
9649 | new_stretch += 3; | |
5b7c81bd AM |
9650 | fragP->tc_frag_data.relax_seen = false; /* Need another pass. */ |
9651 | fragP->tc_frag_data.is_insn = true; | |
b46824bd MF |
9652 | tinsn_init (&insn); |
9653 | insn.insn_type = ITYPE_INSN; | |
9654 | insn.opcode = xtensa_j_opcode; | |
9655 | insn.ntok = 1; | |
9656 | set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, | |
9657 | fragP->fr_fix); | |
9658 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9659 | tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); | |
9660 | xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); | |
9661 | xtensa_insnbuf_to_chars (isa, litpool_buf, | |
9662 | (unsigned char *)fragP->fr_literal + | |
9663 | fragP->fr_fix, 3); | |
9664 | fragP->fr_fix += 3; | |
9665 | fragP->fr_var -= 3; | |
9666 | /* Add a fix-up. */ | |
5b7c81bd | 9667 | fix_new (fragP, 0, 3, fragP->fr_symbol, 0, true, |
b46824bd MF |
9668 | BFD_RELOC_XTENSA_SLOT0_OP); |
9669 | } | |
9670 | break; | |
9671 | ||
e0001a05 | 9672 | case RELAX_LITERAL_POOL_END: |
b46824bd | 9673 | case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: |
43cd72b9 BW |
9674 | case RELAX_MAYBE_UNREACHABLE: |
9675 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
9676 | /* No relaxation required. */ |
9677 | break; | |
9678 | ||
43cd72b9 BW |
9679 | case RELAX_FILL_NOP: |
9680 | case RELAX_UNREACHABLE: | |
9681 | if (fragP->tc_frag_data.relax_seen) | |
9682 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9683 | break; | |
9684 | ||
a82c7d90 DW |
9685 | case RELAX_TRAMPOLINE: |
9686 | if (fragP->tc_frag_data.relax_seen) | |
120bc8b8 | 9687 | xg_relax_trampoline (fragP, stretch, &new_stretch); |
a82c7d90 DW |
9688 | break; |
9689 | ||
e0001a05 NC |
9690 | default: |
9691 | as_bad (_("bad relaxation state")); | |
9692 | } | |
9693 | ||
43cd72b9 | 9694 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 9695 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 | 9696 | { |
5b7c81bd | 9697 | fragP->tc_frag_data.relax_seen = true; |
43cd72b9 BW |
9698 | *stretched_p = 1; |
9699 | } | |
9700 | ||
e0001a05 NC |
9701 | new_logical_line (file_name, line); |
9702 | return new_stretch; | |
9703 | } | |
9704 | ||
9705 | ||
9706 | static long | |
7fa3d080 | 9707 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
9708 | { |
9709 | addressT old_address, old_next_address, old_size; | |
9710 | addressT new_address, new_next_address, new_size; | |
9711 | addressT growth; | |
9712 | ||
43cd72b9 BW |
9713 | /* All the frags with relax_frag_for_alignment prior to this one in the |
9714 | section have been done, hopefully eliminating the need for a NOP here. | |
9715 | But, this will put it in if necessary. */ | |
e0001a05 NC |
9716 | |
9717 | /* Calculate the old address of this fragment and the next fragment. */ | |
9718 | old_address = fragP->fr_address - stretch; | |
9719 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 9720 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
9721 | old_size = old_next_address - old_address; |
9722 | ||
9723 | /* Calculate the new address of this fragment and the next fragment. */ | |
9724 | new_address = fragP->fr_address; | |
9725 | new_next_address = | |
9726 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
9727 | new_size = new_next_address - new_address; | |
9728 | ||
9729 | growth = new_size - old_size; | |
9730 | ||
9731 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 9732 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
9733 | return growth; |
9734 | } | |
9735 | ||
9736 | ||
43cd72b9 | 9737 | /* Add a NOP instruction. */ |
e0001a05 NC |
9738 | |
9739 | static long | |
7fa3d080 | 9740 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 9741 | { |
e0001a05 | 9742 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
9743 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
9744 | assemble_nop (length, nop_buf); | |
5b7c81bd | 9745 | fragP->tc_frag_data.is_insn = true; |
e0001a05 | 9746 | |
e0001a05 NC |
9747 | if (fragP->fr_var < length) |
9748 | { | |
dd49a749 | 9749 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
9750 | return 0; |
9751 | } | |
9752 | ||
9753 | fragP->fr_fix += length; | |
9754 | fragP->fr_var -= length; | |
e0001a05 NC |
9755 | return length; |
9756 | } | |
9757 | ||
9758 | ||
7fa3d080 BW |
9759 | static long future_alignment_required (fragS *, long); |
9760 | ||
e0001a05 | 9761 | static long |
7fa3d080 | 9762 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 9763 | { |
43cd72b9 BW |
9764 | /* Overview of the relaxation procedure for alignment: |
9765 | We can widen with NOPs or by widening instructions or by filling | |
9766 | bytes after jump instructions. Find the opportune places and widen | |
9767 | them if necessary. */ | |
9768 | ||
9769 | long stretch_me; | |
9770 | long diff; | |
e0001a05 | 9771 | |
9c2799c2 | 9772 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
9773 | || fragP->fr_subtype == RELAX_UNREACHABLE |
9774 | || (fragP->fr_subtype == RELAX_SLOTS | |
9775 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
9776 | ||
9777 | stretch_me = future_alignment_required (fragP, stretch); | |
9778 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
9779 | if (diff == 0) | |
9780 | return 0; | |
e0001a05 | 9781 | |
43cd72b9 | 9782 | if (diff < 0) |
e0001a05 | 9783 | { |
43cd72b9 BW |
9784 | /* We expanded on a previous pass. Can we shrink now? */ |
9785 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
9786 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 9787 | { |
43cd72b9 BW |
9788 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
9789 | return -shrink; | |
e0001a05 NC |
9790 | } |
9791 | return 0; | |
9792 | } | |
9793 | ||
43cd72b9 BW |
9794 | /* Below here, diff > 0. */ |
9795 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 9796 | |
43cd72b9 | 9797 | return diff; |
e0001a05 NC |
9798 | } |
9799 | ||
9800 | ||
43cd72b9 BW |
9801 | /* Return the address of the next frag that should be aligned. |
9802 | ||
9803 | By "address" we mean the address it _would_ be at if there | |
9804 | is no action taken to align it between here and the target frag. | |
9805 | In other words, if no narrows and no fill nops are used between | |
9806 | here and the frag to align, _even_if_ some of the frags we use | |
9807 | to align targets have already expanded on a previous relaxation | |
9808 | pass. | |
9809 | ||
9810 | Also, count each frag that may be used to help align the target. | |
9811 | ||
9812 | Return 0 if there are no frags left in the chain that need to be | |
9813 | aligned. */ | |
9814 | ||
9815 | static addressT | |
7fa3d080 BW |
9816 | find_address_of_next_align_frag (fragS **fragPP, |
9817 | int *wide_nops, | |
9818 | int *narrow_nops, | |
9819 | int *widens, | |
5b7c81bd | 9820 | bool *paddable) |
e0001a05 | 9821 | { |
43cd72b9 BW |
9822 | fragS *fragP = *fragPP; |
9823 | addressT address = fragP->fr_address; | |
9824 | ||
9825 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
9826 | |
9827 | while (fragP) | |
9828 | { | |
9829 | /* Limit this to a small search. */ | |
b5e4a23d | 9830 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
9831 | { |
9832 | *fragPP = fragP; | |
9833 | return 0; | |
9834 | } | |
e0001a05 NC |
9835 | address += fragP->fr_fix; |
9836 | ||
43cd72b9 BW |
9837 | if (fragP->fr_type == rs_fill) |
9838 | address += fragP->fr_offset * fragP->fr_var; | |
9839 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 9840 | { |
e0001a05 NC |
9841 | switch (fragP->fr_subtype) |
9842 | { | |
43cd72b9 | 9843 | case RELAX_UNREACHABLE: |
5b7c81bd | 9844 | *paddable = true; |
43cd72b9 BW |
9845 | break; |
9846 | ||
9847 | case RELAX_FILL_NOP: | |
9848 | (*wide_nops)++; | |
9849 | if (!fragP->tc_frag_data.is_no_density) | |
9850 | (*narrow_nops)++; | |
9851 | break; | |
9852 | ||
9853 | case RELAX_SLOTS: | |
9854 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9855 | { | |
9856 | (*widens)++; | |
9857 | break; | |
9858 | } | |
5bb3703f | 9859 | address += total_frag_text_expansion (fragP); |
e0001a05 NC |
9860 | break; |
9861 | ||
9862 | case RELAX_IMMED: | |
43cd72b9 | 9863 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
9864 | break; |
9865 | ||
9866 | case RELAX_ALIGN_NEXT_OPCODE: | |
9867 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
9868 | *fragPP = fragP; |
9869 | return address; | |
9870 | ||
9871 | case RELAX_MAYBE_UNREACHABLE: | |
9872 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9873 | /* Do nothing. */ | |
e0001a05 NC |
9874 | break; |
9875 | ||
9876 | default: | |
43cd72b9 BW |
9877 | /* Just punt if we don't know the type. */ |
9878 | *fragPP = fragP; | |
9879 | return 0; | |
e0001a05 | 9880 | } |
43cd72b9 | 9881 | } |
c138bc38 | 9882 | else |
43cd72b9 BW |
9883 | { |
9884 | /* Just punt if we don't know the type. */ | |
9885 | *fragPP = fragP; | |
9886 | return 0; | |
9887 | } | |
9888 | fragP = fragP->fr_next; | |
9889 | } | |
9890 | ||
9891 | *fragPP = fragP; | |
9892 | return 0; | |
9893 | } | |
9894 | ||
9895 | ||
7fa3d080 BW |
9896 | static long bytes_to_stretch (fragS *, int, int, int, int); |
9897 | ||
43cd72b9 | 9898 | static long |
7fa3d080 | 9899 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
9900 | { |
9901 | fragS *this_frag = fragP; | |
9902 | long address; | |
9903 | int num_widens = 0; | |
9904 | int wide_nops = 0; | |
9905 | int narrow_nops = 0; | |
5b7c81bd | 9906 | bool paddable = false; |
43cd72b9 BW |
9907 | offsetT local_opt_diff; |
9908 | offsetT opt_diff; | |
9909 | offsetT max_diff; | |
9910 | int stretch_amount = 0; | |
9911 | int local_stretch_amount; | |
9912 | int global_stretch_amount; | |
9913 | ||
7fa3d080 BW |
9914 | address = find_address_of_next_align_frag |
9915 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 9916 | |
b5e4a23d BW |
9917 | if (!address) |
9918 | { | |
9919 | if (this_frag->tc_frag_data.is_aligning_branch) | |
9920 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
9921 | else | |
9922 | frag_wane (this_frag); | |
9923 | } | |
9924 | else | |
43cd72b9 BW |
9925 | { |
9926 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
9927 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
9928 | gas_assert (opt_diff >= 0); |
9929 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 9930 | if (max_diff == 0) |
43cd72b9 | 9931 | return 0; |
d2a033cd | 9932 | |
43cd72b9 BW |
9933 | if (fragP) |
9934 | fragP = fragP->fr_next; | |
9935 | ||
9936 | while (fragP && opt_diff < max_diff && address) | |
9937 | { | |
9938 | /* We only use these to determine if we can exit early | |
c138bc38 | 9939 | because there will be plenty of ways to align future |
43cd72b9 | 9940 | align frags. */ |
d77b99c9 | 9941 | int glob_widens = 0; |
43cd72b9 BW |
9942 | int dnn = 0; |
9943 | int dw = 0; | |
5b7c81bd | 9944 | bool glob_pad = 0; |
7fa3d080 BW |
9945 | address = find_address_of_next_align_frag |
9946 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 9947 | /* If there is a padable portion, then skip. */ |
664df4e4 | 9948 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 9949 | address = 0; |
43cd72b9 | 9950 | |
c138bc38 | 9951 | if (address) |
43cd72b9 BW |
9952 | { |
9953 | offsetT next_m_diff; | |
9954 | offsetT next_o_diff; | |
9955 | ||
9956 | /* Downrange frags haven't had stretch added to them yet. */ | |
9957 | address += stretch; | |
9958 | ||
9959 | /* The address also includes any text expansion from this | |
9960 | frag in a previous pass, but we don't want that. */ | |
9961 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
9962 | ||
9963 | /* Assume we are going to move at least opt_diff. In | |
9964 | reality, we might not be able to, but assuming that | |
9965 | we will helps catch cases where moving opt_diff pushes | |
9966 | the next target from aligned to unaligned. */ | |
9967 | address += opt_diff; | |
9968 | ||
9969 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
9970 | ||
9971 | /* Now cleanup for the adjustments to address. */ | |
9972 | next_o_diff += opt_diff; | |
9973 | next_m_diff += opt_diff; | |
9974 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
9975 | opt_diff = next_o_diff; | |
9976 | if (next_m_diff < max_diff) | |
9977 | max_diff = next_m_diff; | |
9978 | fragP = fragP->fr_next; | |
9979 | } | |
9980 | } | |
d2a033cd | 9981 | |
43cd72b9 BW |
9982 | /* If there are enough wideners in between, do it. */ |
9983 | if (paddable) | |
9984 | { | |
9985 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
9986 | { | |
1beeb686 | 9987 | gas_assert (opt_diff <= (signed) xtensa_fetch_width); |
43cd72b9 BW |
9988 | return opt_diff; |
9989 | } | |
9990 | return 0; | |
9991 | } | |
c138bc38 | 9992 | local_stretch_amount |
43cd72b9 BW |
9993 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
9994 | num_widens, local_opt_diff); | |
c138bc38 BW |
9995 | global_stretch_amount |
9996 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 9997 | num_widens, opt_diff); |
c138bc38 BW |
9998 | /* If the condition below is true, then the frag couldn't |
9999 | stretch the correct amount for the global case, so we just | |
10000 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
10001 | the correct alignment in the global case. */ |
10002 | if (global_stretch_amount < local_stretch_amount) | |
10003 | stretch_amount = local_stretch_amount; | |
10004 | else | |
10005 | stretch_amount = global_stretch_amount; | |
d2a033cd | 10006 | |
43cd72b9 BW |
10007 | if (this_frag->fr_subtype == RELAX_SLOTS |
10008 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 10009 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
10010 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10011 | { | |
10012 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 10013 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 10014 | else |
9c2799c2 | 10015 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
10016 | } |
10017 | } | |
10018 | return stretch_amount; | |
10019 | } | |
10020 | ||
10021 | ||
10022 | /* The idea: widen everything you can to get a target or loop aligned, | |
10023 | then start using NOPs. | |
10024 | ||
43cd72b9 BW |
10025 | wide_nops = the number of wide NOPs available for aligning |
10026 | narrow_nops = the number of narrow NOPs available for aligning | |
10027 | (a subset of wide_nops) | |
10028 | widens = the number of narrow instructions that should be widened | |
10029 | ||
43cd72b9 BW |
10030 | */ |
10031 | ||
10032 | static long | |
7fa3d080 BW |
10033 | bytes_to_stretch (fragS *this_frag, |
10034 | int wide_nops, | |
10035 | int narrow_nops, | |
10036 | int num_widens, | |
10037 | int desired_diff) | |
43cd72b9 | 10038 | { |
19ef5f3d SA |
10039 | int nops_needed; |
10040 | int nop_bytes; | |
10041 | int extra_bytes; | |
43cd72b9 BW |
10042 | int bytes_short = desired_diff - num_widens; |
10043 | ||
3739860c | 10044 | gas_assert (desired_diff >= 0 |
1beeb686 | 10045 | && desired_diff < (signed) xtensa_fetch_width); |
43cd72b9 BW |
10046 | if (desired_diff == 0) |
10047 | return 0; | |
c138bc38 | 10048 | |
9c2799c2 | 10049 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 10050 | |
43cd72b9 BW |
10051 | /* Always prefer widening to NOP-filling. */ |
10052 | if (bytes_short < 0) | |
10053 | { | |
10054 | /* There are enough RELAX_NARROW frags after this one | |
10055 | to align the target without widening this frag in any way. */ | |
10056 | return 0; | |
10057 | } | |
c138bc38 | 10058 | |
43cd72b9 BW |
10059 | if (bytes_short == 0) |
10060 | { | |
10061 | /* Widen every narrow between here and the align target | |
10062 | and the align target will be properly aligned. */ | |
10063 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
10064 | return 0; | |
10065 | else | |
10066 | return 1; | |
10067 | } | |
c138bc38 | 10068 | |
43cd72b9 BW |
10069 | /* From here we will need at least one NOP to get an alignment. |
10070 | However, we may not be able to align at all, in which case, | |
10071 | don't widen. */ | |
19ef5f3d SA |
10072 | nops_needed = desired_diff / 3; |
10073 | ||
10074 | /* If there aren't enough nops, don't widen. */ | |
10075 | if (nops_needed > wide_nops) | |
10076 | return 0; | |
10077 | ||
10078 | /* First try it with all wide nops. */ | |
10079 | nop_bytes = nops_needed * 3; | |
10080 | extra_bytes = desired_diff - nop_bytes; | |
10081 | ||
10082 | if (nop_bytes + num_widens >= desired_diff) | |
43cd72b9 | 10083 | { |
19ef5f3d SA |
10084 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10085 | return 3; | |
10086 | else if (num_widens == extra_bytes) | |
10087 | return 1; | |
10088 | return 0; | |
e0001a05 | 10089 | } |
19ef5f3d SA |
10090 | |
10091 | /* Add a narrow nop. */ | |
10092 | nops_needed++; | |
10093 | nop_bytes += 2; | |
10094 | extra_bytes -= 2; | |
10095 | if (narrow_nops == 0 || nops_needed > wide_nops) | |
10096 | return 0; | |
10097 | ||
10098 | if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) | |
43cd72b9 | 10099 | { |
19ef5f3d SA |
10100 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10101 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10102 | else if (num_widens == extra_bytes) | |
10103 | return 1; | |
10104 | return 0; | |
10105 | } | |
e0001a05 | 10106 | |
19ef5f3d SA |
10107 | /* Replace a wide nop with a narrow nop--we can get here if |
10108 | extra_bytes was negative in the previous conditional. */ | |
10109 | if (narrow_nops == 1) | |
10110 | return 0; | |
10111 | nop_bytes--; | |
10112 | extra_bytes++; | |
10113 | if (nop_bytes + num_widens >= desired_diff) | |
10114 | { | |
10115 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
10116 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10117 | else if (num_widens == extra_bytes) | |
10118 | return 1; | |
10119 | return 0; | |
43cd72b9 | 10120 | } |
19ef5f3d SA |
10121 | |
10122 | /* If we can't satisfy any of the above cases, then we can't align | |
10123 | using padding or fill nops. */ | |
43cd72b9 | 10124 | return 0; |
e0001a05 NC |
10125 | } |
10126 | ||
10127 | ||
46888d71 | 10128 | static fragS * |
76a493ab | 10129 | xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP) |
a82c7d90 | 10130 | { |
76a493ab MF |
10131 | symbolS *sym = tinsn->tok[0].X_add_symbol; |
10132 | addressT source = fragP->fr_address; | |
10133 | addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; | |
a82c7d90 | 10134 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
fe6c2f1b | 10135 | size_t i; |
a82c7d90 | 10136 | |
76a493ab MF |
10137 | if (!ts || !ts->index.n_entries) |
10138 | return NULL; | |
a82c7d90 | 10139 | |
76a493ab | 10140 | i = xg_find_best_trampoline (&ts->index, source, target); |
a82c7d90 | 10141 | |
76a493ab | 10142 | return ts->index.entry[i]; |
a82c7d90 DW |
10143 | } |
10144 | ||
10145 | ||
fe6c2f1b MF |
10146 | /* Append jump to sym + offset to the end of the trampoline frag fragP. |
10147 | Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var | |
10148 | and finish the frag if it's full (but don't remove it from the trampoline | |
10149 | frag index). Return fixup for the newly created jump. */ | |
46888d71 | 10150 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset) |
fec68fb1 MF |
10151 | { |
10152 | fixS *fixP; | |
10153 | TInsn insn; | |
10154 | xtensa_format fmt; | |
10155 | xtensa_isa isa = xtensa_default_isa; | |
10156 | ||
10157 | gas_assert (fragP->fr_var >= 3); | |
10158 | tinsn_init (&insn); | |
10159 | insn.insn_type = ITYPE_INSN; | |
10160 | insn.opcode = xtensa_j_opcode; | |
10161 | insn.ntok = 1; | |
10162 | set_expr_symbol_offset (&insn.tok[0], sym, offset); | |
10163 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10164 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10165 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10166 | xtensa_insnbuf_to_chars (isa, trampoline_buf, | |
10167 | (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3); | |
5b7c81bd | 10168 | fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, true, |
fec68fb1 MF |
10169 | BFD_RELOC_XTENSA_SLOT0_OP); |
10170 | fixP->tc_fix_data.slot = 0; | |
10171 | ||
10172 | fragP->fr_fix += 3; | |
10173 | fragP->fr_var -= 3; | |
10174 | ||
10175 | /* Adjust the jump around this trampoline (if present). */ | |
46888d71 MF |
10176 | if (fragP->tc_frag_data.jump_around_fix) |
10177 | fragP->tc_frag_data.jump_around_fix->fx_offset += 3; | |
fec68fb1 | 10178 | |
fe6c2f1b MF |
10179 | /* Do we have room for more? */ |
10180 | if (xg_is_trampoline_frag_full (fragP)) | |
10181 | { | |
10182 | frag_wane (fragP); | |
10183 | fragP->fr_subtype = 0; | |
10184 | } | |
10185 | ||
fec68fb1 MF |
10186 | return fixP; |
10187 | } | |
10188 | ||
a82c7d90 DW |
10189 | |
10190 | static int | |
46888d71 | 10191 | init_trampoline_frag (fragS *fp) |
a82c7d90 | 10192 | { |
a82c7d90 DW |
10193 | int growth = 0; |
10194 | ||
10195 | if (fp->fr_fix == 0) | |
10196 | { | |
10197 | symbolS *lsym; | |
10198 | char label[10 + 2 * sizeof(fp)]; | |
a82c7d90 | 10199 | |
fec68fb1 | 10200 | sprintf (label, ".L0_TR_%p", fp); |
e01e1cee | 10201 | lsym = (symbolS *) local_symbol_make (label, now_seg, fp, 0); |
a82c7d90 | 10202 | fp->fr_symbol = lsym; |
46888d71 | 10203 | if (fp->tc_frag_data.needs_jump_around) |
a82c7d90 | 10204 | { |
46888d71 | 10205 | fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3); |
a82c7d90 | 10206 | growth = 3; |
a82c7d90 DW |
10207 | } |
10208 | } | |
10209 | return growth; | |
10210 | } | |
10211 | ||
a82c7d90 | 10212 | static int |
148d6384 | 10213 | xg_get_single_symbol_slot (fragS *fragP) |
a82c7d90 | 10214 | { |
148d6384 MF |
10215 | int i; |
10216 | int slot = -1; | |
24e5b4e6 MF |
10217 | |
10218 | for (i = 0; i < MAX_SLOTS; ++i) | |
148d6384 | 10219 | if (fragP->tc_frag_data.slot_symbols[i]) |
24e5b4e6 MF |
10220 | { |
10221 | gas_assert (slot == -1); | |
10222 | slot = i; | |
10223 | } | |
10224 | ||
10225 | gas_assert (slot >= 0 && slot < MAX_SLOTS); | |
a82c7d90 | 10226 | |
148d6384 MF |
10227 | return slot; |
10228 | } | |
10229 | ||
10230 | static fixS * | |
10231 | add_jump_to_trampoline (fragS *tramp, fragS *origfrag) | |
10232 | { | |
10233 | int slot = xg_get_single_symbol_slot (origfrag); | |
10234 | fixS *fixP; | |
10235 | ||
a82c7d90 | 10236 | /* Assemble a jump to the target label in the trampoline frag. */ |
148d6384 MF |
10237 | fixP = xg_append_jump (tramp, |
10238 | origfrag->tc_frag_data.slot_symbols[slot], | |
10239 | origfrag->tc_frag_data.slot_offsets[slot]); | |
fec68fb1 | 10240 | |
a82c7d90 | 10241 | /* Modify the original j to point here. */ |
fec68fb1 | 10242 | origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol; |
24e5b4e6 | 10243 | origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; |
fec68fb1 | 10244 | |
a82c7d90 | 10245 | /* If trampoline is full, remove it from the list. */ |
fe6c2f1b MF |
10246 | if (xg_is_trampoline_frag_full (tramp)) |
10247 | { | |
10248 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
10249 | size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address); | |
10250 | ||
10251 | gas_assert (ts->index.entry[tr] == tramp); | |
10252 | xg_remove_trampoline_from_index (&ts->index, tr); | |
10253 | } | |
a82c7d90 | 10254 | |
148d6384 | 10255 | return fixP; |
a82c7d90 DW |
10256 | } |
10257 | ||
10258 | ||
e0001a05 | 10259 | static long |
7fa3d080 BW |
10260 | relax_frag_immed (segT segP, |
10261 | fragS *fragP, | |
10262 | long stretch, | |
10263 | int min_steps, | |
10264 | xtensa_format fmt, | |
10265 | int slot, | |
10266 | int *stretched_p, | |
5b7c81bd | 10267 | bool estimate_only) |
e0001a05 | 10268 | { |
43cd72b9 | 10269 | TInsn tinsn; |
e0001a05 | 10270 | int old_size; |
5b7c81bd AM |
10271 | bool negatable_branch = false; |
10272 | bool branch_jmp_to_next = false; | |
10273 | bool from_wide_insn = false; | |
43cd72b9 | 10274 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
10275 | IStack istack; |
10276 | offsetT frag_offset; | |
10277 | int num_steps; | |
e0001a05 | 10278 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 10279 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 10280 | |
9c2799c2 | 10281 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10282 | |
b5e4a23d BW |
10283 | xg_clear_vinsn (&cur_vinsn); |
10284 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 10285 | if (cur_vinsn.num_slots > 1) |
5b7c81bd | 10286 | from_wide_insn = true; |
43cd72b9 | 10287 | |
b5e4a23d | 10288 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 10289 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 10290 | |
64b607e6 | 10291 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 10292 | return 0; |
e0001a05 | 10293 | |
b08b5071 | 10294 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10295 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 10296 | |
43cd72b9 | 10297 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 10298 | |
43cd72b9 | 10299 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10300 | |
10301 | /* Special case: replace a branch to the next instruction with a NOP. | |
10302 | This is required to work around a hardware bug in T1040.0 and also | |
10303 | serves as an optimization. */ | |
10304 | ||
10305 | if (branch_jmp_to_next | |
10306 | && ((old_size == 2) || (old_size == 3)) | |
10307 | && !next_frag_is_loop_target (fragP)) | |
10308 | return 0; | |
10309 | ||
10310 | /* Here is the fun stuff: Get the immediate field from this | |
10311 | instruction. If it fits, we are done. If not, find the next | |
10312 | instruction sequence that fits. */ | |
10313 | ||
10314 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10315 | istack_init (&istack); | |
43cd72b9 | 10316 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 10317 | min_steps, stretch); |
9c2799c2 | 10318 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 10319 | |
43cd72b9 | 10320 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
10321 | |
10322 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 10323 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
10324 | literal_diff |
10325 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 10326 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
10327 | |
10328 | if (from_wide_insn) | |
43cd72b9 | 10329 | { |
2276bc20 BW |
10330 | int first = 0; |
10331 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
10332 | first++; | |
10333 | ||
43cd72b9 BW |
10334 | num_text_bytes += old_size; |
10335 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
10336 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
10337 | else |
10338 | { | |
10339 | /* The first instruction in the relaxed sequence will go after | |
10340 | the current wide instruction, and thus its symbolic immediates | |
10341 | might not fit. */ | |
3739860c | 10342 | |
2276bc20 | 10343 | istack_init (&istack); |
3739860c | 10344 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, |
2276bc20 BW |
10345 | frag_offset + old_size, |
10346 | min_steps, stretch + old_size); | |
9c2799c2 | 10347 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 | 10348 | |
3739860c | 10349 | fragP->tc_frag_data.slot_subtypes[slot] |
2276bc20 BW |
10350 | = (int) RELAX_IMMED + num_steps; |
10351 | ||
10352 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
3739860c | 10353 | literal_diff |
2276bc20 | 10354 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; |
3739860c | 10355 | |
2276bc20 BW |
10356 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; |
10357 | } | |
43cd72b9 | 10358 | } |
def13efb | 10359 | |
43cd72b9 BW |
10360 | total_text_diff = num_text_bytes - old_size; |
10361 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
10362 | |
10363 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
10364 | gas_assert (num_text_bytes >= 0); |
10365 | gas_assert (literal_diff >= 0); | |
10366 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 10367 | |
43cd72b9 BW |
10368 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
10369 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
10370 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
10371 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
10372 | |
10373 | /* Find the associated expandable literal for this. */ | |
10374 | if (literal_diff != 0) | |
10375 | { | |
2276bc20 | 10376 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10377 | if (lit_fragP) |
10378 | { | |
9c2799c2 | 10379 | gas_assert (literal_diff == 4); |
e0001a05 NC |
10380 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
10381 | ||
10382 | /* We expect that the literal section state has NOT been | |
10383 | modified yet. */ | |
9c2799c2 | 10384 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
10385 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
10386 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
10387 | ||
10388 | /* We need to mark this section for another iteration | |
10389 | of relaxation. */ | |
10390 | (*stretched_p)++; | |
10391 | } | |
10392 | } | |
10393 | ||
43cd72b9 | 10394 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 10395 | update_next_frag_state (fragP); |
e0001a05 | 10396 | |
a82c7d90 DW |
10397 | /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ |
10398 | if (istack.ninsn > 2 && | |
10399 | istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && | |
10400 | istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && | |
10401 | istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) | |
10402 | { | |
10403 | TInsn *jinsn = &istack.insn[istack.ninsn - 2]; | |
148d6384 MF |
10404 | struct trampoline_seg *ts = find_trampoline_seg (segP); |
10405 | struct trampoline_chain *tc = NULL; | |
10406 | ||
10407 | if (ts && | |
10408 | !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, | |
10409 | total_text_diff)) | |
10410 | { | |
10411 | int s = xg_get_single_symbol_slot (fragP); | |
10412 | addressT offset = fragP->tc_frag_data.slot_offsets[s]; | |
10413 | ||
10414 | tc = xg_find_best_eq_target (ts, fragP->fr_address, | |
10415 | &fragP->tc_frag_data.slot_symbols[s], | |
10416 | &offset); | |
10417 | ||
10418 | if (!tc) | |
10419 | tc = xg_create_trampoline_chain (ts, | |
10420 | fragP->tc_frag_data.slot_symbols[s], | |
10421 | offset); | |
10422 | fragP->tc_frag_data.slot_offsets[s] = offset; | |
10423 | tinsn_immed_from_frag (jinsn, fragP, s); | |
10424 | } | |
a82c7d90 | 10425 | |
148d6384 MF |
10426 | if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, |
10427 | total_text_diff)) | |
a82c7d90 | 10428 | { |
76a493ab | 10429 | fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP); |
a82c7d90 DW |
10430 | |
10431 | if (tf) | |
10432 | { | |
148d6384 MF |
10433 | fixS *fixP; |
10434 | ||
10435 | this_text_diff += init_trampoline_frag (tf) + 3; | |
10436 | fixP = add_jump_to_trampoline (tf, fragP); | |
10437 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
10438 | fixP->fx_where); | |
5b7c81bd | 10439 | fragP->tc_frag_data.relax_seen = false; |
a82c7d90 DW |
10440 | } |
10441 | else | |
10442 | { | |
10443 | /* If target symbol is undefined, assume it will reach once linked. */ | |
10444 | expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; | |
10445 | ||
10446 | if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) | |
10447 | { | |
10448 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10449 | _("jump target out of range; no usable trampoline found")); | |
10450 | } | |
10451 | } | |
10452 | } | |
10453 | } | |
10454 | ||
43cd72b9 | 10455 | return this_text_diff; |
e0001a05 NC |
10456 | } |
10457 | ||
10458 | \f | |
10459 | /* md_convert_frag Hook and Helper Functions. */ | |
10460 | ||
7fa3d080 BW |
10461 | static void convert_frag_align_next_opcode (fragS *); |
10462 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
10463 | static void convert_frag_fill_nop (fragS *); | |
10464 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
10465 | ||
e0001a05 | 10466 | void |
7fa3d080 | 10467 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 10468 | { |
43cd72b9 BW |
10469 | static xtensa_insnbuf vbuf = NULL; |
10470 | xtensa_isa isa = xtensa_default_isa; | |
10471 | int slot; | |
10472 | int num_slots; | |
10473 | xtensa_format fmt; | |
3b4dbbbf | 10474 | const char *file_name; |
d77b99c9 | 10475 | unsigned line; |
e0001a05 | 10476 | |
3b4dbbbf | 10477 | file_name = as_where (&line); |
e0001a05 NC |
10478 | new_logical_line (fragp->fr_file, fragp->fr_line); |
10479 | ||
10480 | switch (fragp->fr_subtype) | |
10481 | { | |
10482 | case RELAX_ALIGN_NEXT_OPCODE: | |
10483 | /* Always convert. */ | |
10484 | convert_frag_align_next_opcode (fragp); | |
10485 | break; | |
10486 | ||
10487 | case RELAX_DESIRE_ALIGN: | |
10488 | /* Do nothing. If not aligned already, too bad. */ | |
10489 | break; | |
10490 | ||
43cd72b9 BW |
10491 | case RELAX_LITERAL: |
10492 | case RELAX_LITERAL_FINAL: | |
10493 | break; | |
10494 | ||
10495 | case RELAX_SLOTS: | |
10496 | if (vbuf == NULL) | |
10497 | vbuf = xtensa_insnbuf_alloc (isa); | |
10498 | ||
d77b99c9 BW |
10499 | xtensa_insnbuf_from_chars |
10500 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
10501 | fmt = xtensa_format_decode (isa, vbuf); |
10502 | num_slots = xtensa_format_num_slots (isa, fmt); | |
10503 | ||
10504 | for (slot = 0; slot < num_slots; slot++) | |
10505 | { | |
10506 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
10507 | { | |
10508 | case RELAX_NARROW: | |
10509 | convert_frag_narrow (sec, fragp, fmt, slot); | |
10510 | break; | |
10511 | ||
10512 | case RELAX_IMMED: | |
10513 | case RELAX_IMMED_STEP1: | |
10514 | case RELAX_IMMED_STEP2: | |
b81bf389 | 10515 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
10516 | /* Place the immediate. */ |
10517 | convert_frag_immed | |
10518 | (sec, fragp, | |
10519 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
10520 | fmt, slot); | |
10521 | break; | |
10522 | ||
10523 | default: | |
10524 | /* This is OK because some slots could have | |
10525 | relaxations and others have none. */ | |
10526 | break; | |
10527 | } | |
10528 | } | |
10529 | break; | |
10530 | ||
10531 | case RELAX_UNREACHABLE: | |
10532 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
10533 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
10534 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
10535 | frag_wane (fragp); | |
e0001a05 NC |
10536 | break; |
10537 | ||
43cd72b9 BW |
10538 | case RELAX_MAYBE_UNREACHABLE: |
10539 | case RELAX_MAYBE_DESIRE_ALIGN: | |
10540 | frag_wane (fragp); | |
e0001a05 NC |
10541 | break; |
10542 | ||
43cd72b9 BW |
10543 | case RELAX_FILL_NOP: |
10544 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
10545 | break; |
10546 | ||
10547 | case RELAX_LITERAL_NR: | |
10548 | if (use_literal_section) | |
10549 | { | |
10550 | /* This should have been handled during relaxation. When | |
10551 | relaxing a code segment, literals sometimes need to be | |
10552 | added to the corresponding literal segment. If that | |
10553 | literal segment has already been relaxed, then we end up | |
10554 | in this situation. Marking the literal segments as data | |
10555 | would make this happen less often (since GAS always relaxes | |
10556 | code before data), but we could still get into trouble if | |
10557 | there are instructions in a segment that is not marked as | |
10558 | containing code. Until we can implement a better solution, | |
10559 | cheat and adjust the addresses of all the following frags. | |
10560 | This could break subsequent alignments, but the linker's | |
10561 | literal coalescing will do that anyway. */ | |
10562 | ||
10563 | fragS *f; | |
10564 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 10565 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
10566 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
10567 | fragp->fr_var -= 4; | |
10568 | fragp->fr_fix += 4; | |
10569 | for (f = fragp->fr_next; f; f = f->fr_next) | |
10570 | f->fr_address += 4; | |
10571 | } | |
10572 | else | |
10573 | as_bad (_("invalid relaxation fragment result")); | |
10574 | break; | |
a82c7d90 DW |
10575 | |
10576 | case RELAX_TRAMPOLINE: | |
10577 | break; | |
e0001a05 NC |
10578 | } |
10579 | ||
10580 | fragp->fr_var = 0; | |
10581 | new_logical_line (file_name, line); | |
10582 | } | |
10583 | ||
10584 | ||
7fa3d080 BW |
10585 | static void |
10586 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
10587 | { |
10588 | char *nop_buf; /* Location for Writing. */ | |
5b7c81bd | 10589 | bool use_no_density = fragp->tc_frag_data.is_no_density; |
e0001a05 | 10590 | addressT aligned_address; |
d77b99c9 BW |
10591 | offsetT fill_size; |
10592 | int nop, nop_count; | |
e0001a05 NC |
10593 | |
10594 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
10595 | fragp->fr_fix); | |
10596 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
10597 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
10598 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
10599 | ||
d77b99c9 | 10600 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 10601 | { |
d77b99c9 BW |
10602 | int nop_size; |
10603 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
10604 | |
10605 | assemble_nop (nop_size, nop_buf); | |
10606 | nop_buf += nop_size; | |
10607 | } | |
10608 | ||
10609 | fragp->fr_fix += fill_size; | |
10610 | fragp->fr_var -= fill_size; | |
10611 | } | |
10612 | ||
10613 | ||
10614 | static void | |
7fa3d080 | 10615 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 10616 | { |
43cd72b9 | 10617 | TInsn tinsn, single_target; |
84b08ed9 | 10618 | int size, old_size, diff; |
e0001a05 NC |
10619 | offsetT frag_offset; |
10620 | ||
9c2799c2 | 10621 | gas_assert (slot == 0); |
43cd72b9 BW |
10622 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
10623 | ||
b5e4a23d | 10624 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 10625 | { |
9c2799c2 | 10626 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
10627 | || fragP->tc_frag_data.text_expansion[0] == 0); |
10628 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
10629 | fmt, slot); | |
10630 | return; | |
10631 | } | |
10632 | ||
10633 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
10634 | { |
10635 | /* No conversion. */ | |
10636 | fragP->fr_var = 0; | |
10637 | return; | |
10638 | } | |
10639 | ||
9c2799c2 | 10640 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10641 | |
43cd72b9 BW |
10642 | /* Frags in this relaxation state should only contain |
10643 | single instruction bundles. */ | |
10644 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
10645 | |
10646 | /* Just convert it to a wide form.... */ | |
10647 | size = 0; | |
43cd72b9 | 10648 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
10649 | |
10650 | tinsn_init (&single_target); | |
10651 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10652 | ||
5b7c81bd | 10653 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, false)) |
43cd72b9 BW |
10654 | { |
10655 | as_bad (_("unable to widen instruction")); | |
10656 | return; | |
10657 | } | |
10658 | ||
10659 | size = xg_get_single_size (single_target.opcode); | |
b2d179be | 10660 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
5b7c81bd | 10661 | frag_offset, true); |
e0001a05 NC |
10662 | |
10663 | diff = size - old_size; | |
9c2799c2 NC |
10664 | gas_assert (diff >= 0); |
10665 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
10666 | fragP->fr_var -= diff; |
10667 | fragP->fr_fix += diff; | |
10668 | ||
10669 | /* clean it up */ | |
10670 | fragP->fr_var = 0; | |
10671 | } | |
10672 | ||
10673 | ||
10674 | static void | |
7fa3d080 | 10675 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
10676 | { |
10677 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
10678 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10679 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
10680 | - fragP->fr_address - fragP->fr_fix)); |
10681 | if (size == 0) | |
10682 | { | |
10683 | /* No conversion. */ | |
10684 | fragP->fr_var = 0; | |
10685 | return; | |
10686 | } | |
10687 | assemble_nop (size, loc); | |
5b7c81bd | 10688 | fragP->tc_frag_data.is_insn = true; |
43cd72b9 BW |
10689 | fragP->fr_var -= size; |
10690 | fragP->fr_fix += size; | |
10691 | frag_wane (fragP); | |
10692 | } | |
10693 | ||
10694 | ||
7fa3d080 BW |
10695 | static fixS *fix_new_exp_in_seg |
10696 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
10697 | bfd_reloc_code_real_type); | |
7fa3d080 | 10698 | |
43cd72b9 | 10699 | static void |
7fa3d080 BW |
10700 | convert_frag_immed (segT segP, |
10701 | fragS *fragP, | |
10702 | int min_steps, | |
10703 | xtensa_format fmt, | |
10704 | int slot) | |
e0001a05 NC |
10705 | { |
10706 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 10707 | TInsn orig_tinsn; |
5b7c81bd AM |
10708 | bool expanded = false; |
10709 | bool branch_jmp_to_next = false; | |
43cd72b9 | 10710 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 10711 | xtensa_isa isa = xtensa_default_isa; |
5b7c81bd | 10712 | bool from_wide_insn = false; |
43cd72b9 | 10713 | int bytes; |
5b7c81bd | 10714 | bool is_loop; |
e0001a05 | 10715 | |
9c2799c2 | 10716 | gas_assert (fr_opcode != NULL); |
e0001a05 | 10717 | |
b5e4a23d | 10718 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 10719 | |
b5e4a23d | 10720 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 10721 | if (cur_vinsn.num_slots > 1) |
5b7c81bd | 10722 | from_wide_insn = true; |
e0001a05 | 10723 | |
b5e4a23d | 10724 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
10725 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
10726 | ||
10727 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 10728 | |
b08b5071 | 10729 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10730 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
10731 | |
10732 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
10733 | { | |
10734 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
10735 | bytes = xtensa_format_length (isa, fmt); |
10736 | if (bytes >= 4) | |
10737 | { | |
b5e4a23d BW |
10738 | cur_vinsn.slots[slot].opcode = |
10739 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
10740 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
10741 | } |
10742 | else | |
10743 | { | |
10744 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10745 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 10746 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
10747 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
10748 | } | |
5b7c81bd | 10749 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, true); |
d77b99c9 | 10750 | xtensa_insnbuf_to_chars |
b5e4a23d | 10751 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
10752 | fragP->fr_var = 0; |
10753 | } | |
7c834684 | 10754 | else |
e0001a05 | 10755 | { |
43cd72b9 BW |
10756 | /* Here is the fun stuff: Get the immediate field from this |
10757 | instruction. If it fits, we're done. If not, find the next | |
10758 | instruction sequence that fits. */ | |
10759 | ||
e0001a05 NC |
10760 | IStack istack; |
10761 | int i; | |
10762 | symbolS *lit_sym = NULL; | |
10763 | int total_size = 0; | |
43cd72b9 | 10764 | int target_offset = 0; |
e0001a05 NC |
10765 | int old_size; |
10766 | int diff; | |
10767 | symbolS *gen_label = NULL; | |
10768 | offsetT frag_offset; | |
5b7c81bd | 10769 | bool first = true; |
e0001a05 | 10770 | |
43cd72b9 | 10771 | /* It does not fit. Find something that does and |
e0001a05 | 10772 | convert immediately. */ |
43cd72b9 | 10773 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 10774 | istack_init (&istack); |
43cd72b9 | 10775 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
10776 | segP, fragP, frag_offset, min_steps, 0); |
10777 | ||
43cd72b9 | 10778 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10779 | |
10780 | /* Assemble this right inline. */ | |
10781 | ||
10782 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 10783 | target_offset = 0; |
e0001a05 NC |
10784 | for (i = 0; i < istack.ninsn; i++) |
10785 | { | |
43cd72b9 | 10786 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10787 | fragS *lit_frag; |
10788 | ||
43cd72b9 | 10789 | switch (tinsn->insn_type) |
e0001a05 NC |
10790 | { |
10791 | case ITYPE_LITERAL: | |
10792 | if (lit_sym != NULL) | |
10793 | as_bad (_("multiple literals in expansion")); | |
10794 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 10795 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10796 | if (lit_frag == NULL) |
10797 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 10798 | if (tinsn->ntok != 1) |
e0001a05 NC |
10799 | as_bad (_("number of literal tokens != 1")); |
10800 | ||
10801 | /* Set the literal symbol and add a fixup. */ | |
10802 | lit_sym = lit_frag->fr_symbol; | |
10803 | break; | |
10804 | ||
10805 | case ITYPE_LABEL: | |
43cd72b9 BW |
10806 | if (align_targets && !is_loop) |
10807 | { | |
10808 | fragS *unreach = fragP->fr_next; | |
10809 | while (!(unreach->fr_type == rs_machine_dependent | |
10810 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
10811 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
10812 | { | |
10813 | unreach = unreach->fr_next; | |
10814 | } | |
10815 | ||
9c2799c2 | 10816 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
10817 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
10818 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
10819 | ||
10820 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
10821 | } | |
9c2799c2 | 10822 | gas_assert (gen_label == NULL); |
e01e1cee | 10823 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, fragP, |
43cd72b9 | 10824 | fr_opcode - fragP->fr_literal |
e01e1cee | 10825 | + target_offset); |
e0001a05 NC |
10826 | break; |
10827 | ||
10828 | case ITYPE_INSN: | |
def13efb | 10829 | if (first && from_wide_insn) |
43cd72b9 BW |
10830 | { |
10831 | target_offset += xtensa_format_length (isa, fmt); | |
5b7c81bd | 10832 | first = false; |
43cd72b9 BW |
10833 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) |
10834 | target_offset += xg_get_single_size (tinsn->opcode); | |
10835 | } | |
10836 | else | |
10837 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
10838 | break; |
10839 | } | |
10840 | } | |
10841 | ||
10842 | total_size = 0; | |
5b7c81bd | 10843 | first = true; |
e0001a05 NC |
10844 | for (i = 0; i < istack.ninsn; i++) |
10845 | { | |
43cd72b9 | 10846 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10847 | fragS *lit_frag; |
10848 | int size; | |
10849 | segT target_seg; | |
43cd72b9 | 10850 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 10851 | |
43cd72b9 | 10852 | switch (tinsn->insn_type) |
e0001a05 NC |
10853 | { |
10854 | case ITYPE_LITERAL: | |
43cd72b9 BW |
10855 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
10856 | /* Already checked. */ | |
9c2799c2 NC |
10857 | gas_assert (lit_frag != NULL); |
10858 | gas_assert (lit_sym != NULL); | |
10859 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 10860 | /* Add a fixup. */ |
e0001a05 | 10861 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 10862 | gas_assert (target_seg); |
5b7c81bd | 10863 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, true); |
e0001a05 | 10864 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
5b7c81bd | 10865 | &tinsn->tok[0], false, reloc_type); |
e0001a05 NC |
10866 | break; |
10867 | ||
10868 | case ITYPE_LABEL: | |
10869 | break; | |
10870 | ||
10871 | case ITYPE_INSN: | |
43cd72b9 BW |
10872 | xg_resolve_labels (tinsn, gen_label); |
10873 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 10874 | if (from_wide_insn && first) |
43cd72b9 | 10875 | { |
5b7c81bd | 10876 | first = false; |
43cd72b9 BW |
10877 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) |
10878 | { | |
b5e4a23d | 10879 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
10880 | } |
10881 | else | |
10882 | { | |
b5e4a23d | 10883 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 10884 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 10885 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 10886 | } |
5b7c81bd | 10887 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, true); |
b5e4a23d | 10888 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, |
d77b99c9 | 10889 | (unsigned char *) immed_instr, 0); |
5b7c81bd | 10890 | fragP->tc_frag_data.is_insn = true; |
43cd72b9 BW |
10891 | size = xtensa_format_length (isa, fmt); |
10892 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10893 | { | |
43cd72b9 | 10894 | xg_emit_insn_to_buf |
b2d179be | 10895 | (tinsn, immed_instr + size, fragP, |
5b7c81bd | 10896 | immed_instr - fragP->fr_literal + size, true); |
43cd72b9 BW |
10897 | size += xg_get_single_size (tinsn->opcode); |
10898 | } | |
10899 | } | |
10900 | else | |
10901 | { | |
43cd72b9 | 10902 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 10903 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
5b7c81bd | 10904 | immed_instr - fragP->fr_literal, true); |
43cd72b9 | 10905 | } |
e0001a05 | 10906 | immed_instr += size; |
43cd72b9 | 10907 | total_size += size; |
e0001a05 NC |
10908 | break; |
10909 | } | |
10910 | } | |
10911 | ||
10912 | diff = total_size - old_size; | |
9c2799c2 | 10913 | gas_assert (diff >= 0); |
e0001a05 | 10914 | if (diff != 0) |
5b7c81bd | 10915 | expanded = true; |
9c2799c2 | 10916 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
10917 | fragP->fr_var -= diff; |
10918 | fragP->fr_fix += diff; | |
10919 | } | |
10920 | ||
e0001a05 | 10921 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 10922 | if (is_loop) |
e0001a05 NC |
10923 | { |
10924 | symbolS *sym; | |
43cd72b9 | 10925 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
10926 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10927 | { | |
10928 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10929 | return; | |
10930 | } | |
43cd72b9 | 10931 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
10932 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10933 | { | |
10934 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10935 | return; | |
10936 | } | |
10937 | } | |
10938 | ||
43cd72b9 | 10939 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
10940 | { |
10941 | /* Add an expansion note on the expanded instruction. */ | |
10942 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
5b7c81bd | 10943 | &orig_tinsn.tok[0], true, |
e0001a05 | 10944 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
10945 | } |
10946 | } | |
10947 | ||
10948 | ||
10949 | /* Add a new fix expression into the desired segment. We have to | |
10950 | switch to that segment to do this. */ | |
10951 | ||
10952 | static fixS * | |
7fa3d080 BW |
10953 | fix_new_exp_in_seg (segT new_seg, |
10954 | subsegT new_subseg, | |
10955 | fragS *frag, | |
10956 | int where, | |
10957 | int size, | |
10958 | expressionS *exp, | |
10959 | int pcrel, | |
10960 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
10961 | { |
10962 | fixS *new_fix; | |
10963 | segT seg = now_seg; | |
10964 | subsegT subseg = now_subseg; | |
43cd72b9 | 10965 | |
9c2799c2 | 10966 | gas_assert (new_seg != 0); |
e0001a05 NC |
10967 | subseg_set (new_seg, new_subseg); |
10968 | ||
e0001a05 NC |
10969 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
10970 | subseg_set (seg, subseg); | |
10971 | return new_fix; | |
10972 | } | |
10973 | ||
10974 | ||
b08b5071 BW |
10975 | \f |
10976 | /* A map that keeps information on a per-subsegment basis. This is | |
10977 | maintained during initial assembly, but is invalid once the | |
10978 | subsegments are smashed together. I.E., it cannot be used during | |
10979 | the relaxation. */ | |
e0001a05 | 10980 | |
b08b5071 | 10981 | typedef struct subseg_map_struct |
e0001a05 | 10982 | { |
b08b5071 BW |
10983 | /* the key */ |
10984 | segT seg; | |
10985 | subsegT subseg; | |
e0001a05 | 10986 | |
b08b5071 BW |
10987 | /* the data */ |
10988 | unsigned flags; | |
10989 | float total_freq; /* fall-through + branch target frequency */ | |
10990 | float target_freq; /* branch target frequency alone */ | |
10991 | ||
10992 | struct subseg_map_struct *next; | |
10993 | } subseg_map; | |
e0001a05 | 10994 | |
e0001a05 | 10995 | |
e0001a05 NC |
10996 | static subseg_map *sseg_map = NULL; |
10997 | ||
43cd72b9 | 10998 | static subseg_map * |
7fa3d080 | 10999 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
11000 | { |
11001 | subseg_map *subseg_e; | |
11002 | ||
11003 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 11004 | { |
43cd72b9 | 11005 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 11006 | break; |
e0001a05 | 11007 | } |
b08b5071 BW |
11008 | return subseg_e; |
11009 | } | |
11010 | ||
11011 | ||
11012 | static subseg_map * | |
11013 | add_subseg_info (segT seg, subsegT subseg) | |
11014 | { | |
325801bd | 11015 | subseg_map *subseg_e = XNEW (subseg_map); |
43cd72b9 BW |
11016 | memset (subseg_e, 0, sizeof (subseg_map)); |
11017 | subseg_e->seg = seg; | |
11018 | subseg_e->subseg = subseg; | |
11019 | subseg_e->flags = 0; | |
11020 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
11021 | subseg_e->target_freq = 1.0; |
11022 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
11023 | subseg_e->next = sseg_map; |
11024 | sseg_map = subseg_e; | |
43cd72b9 BW |
11025 | return subseg_e; |
11026 | } | |
e0001a05 | 11027 | |
7fa3d080 BW |
11028 | |
11029 | static unsigned | |
11030 | get_last_insn_flags (segT seg, subsegT subseg) | |
11031 | { | |
11032 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11033 | if (subseg_e) |
11034 | return subseg_e->flags; | |
11035 | return 0; | |
7fa3d080 BW |
11036 | } |
11037 | ||
11038 | ||
43cd72b9 | 11039 | static void |
7fa3d080 BW |
11040 | set_last_insn_flags (segT seg, |
11041 | subsegT subseg, | |
11042 | unsigned fl, | |
5b7c81bd | 11043 | bool val) |
43cd72b9 BW |
11044 | { |
11045 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11046 | if (! subseg_e) |
11047 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
11048 | if (val) |
11049 | subseg_e->flags |= fl; | |
11050 | else | |
11051 | subseg_e->flags &= ~fl; | |
11052 | } | |
11053 | ||
b08b5071 BW |
11054 | |
11055 | static float | |
11056 | get_subseg_total_freq (segT seg, subsegT subseg) | |
11057 | { | |
11058 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11059 | if (subseg_e) | |
11060 | return subseg_e->total_freq; | |
11061 | return 1.0; | |
11062 | } | |
11063 | ||
11064 | ||
11065 | static float | |
11066 | get_subseg_target_freq (segT seg, subsegT subseg) | |
11067 | { | |
11068 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11069 | if (subseg_e) | |
11070 | return subseg_e->target_freq; | |
11071 | return 1.0; | |
11072 | } | |
11073 | ||
11074 | ||
11075 | static void | |
11076 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
11077 | { | |
11078 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11079 | if (! subseg_e) | |
11080 | subseg_e = add_subseg_info (seg, subseg); | |
11081 | subseg_e->total_freq = total_f; | |
11082 | subseg_e->target_freq = target_f; | |
11083 | } | |
11084 | ||
e0001a05 NC |
11085 | \f |
11086 | /* Segment Lists and emit_state Stuff. */ | |
11087 | ||
e0001a05 | 11088 | static void |
7fa3d080 | 11089 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
11090 | { |
11091 | head = head->next; | |
11092 | while (head) | |
11093 | { | |
11094 | segT literal_section = head->seg; | |
11095 | ||
11096 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 11097 | gas_assert (literal_section); |
69852798 AM |
11098 | if (literal_section != stdoutput->sections) |
11099 | { | |
11100 | bfd_section_list_remove (stdoutput, literal_section); | |
11101 | bfd_section_list_prepend (stdoutput, literal_section); | |
11102 | } | |
e0001a05 NC |
11103 | head = head->next; |
11104 | } | |
11105 | } | |
11106 | ||
11107 | ||
7fa3d080 BW |
11108 | static void mark_literal_frags (seg_list *); |
11109 | ||
947fa914 MF |
11110 | static void |
11111 | xg_promote_candidate_litpool (struct litpool_seg *lps, | |
11112 | struct litpool_frag *lp) | |
11113 | { | |
11114 | fragS *poolbeg; | |
11115 | fragS *poolend; | |
11116 | symbolS *lsym; | |
11117 | char label[10 + 2 * sizeof (fragS *)]; | |
11118 | ||
11119 | poolbeg = lp->fragP; | |
11120 | lp->priority = 1; | |
11121 | poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; | |
11122 | poolend = poolbeg->fr_next; | |
11123 | gas_assert (poolend->fr_type == rs_machine_dependent && | |
11124 | poolend->fr_subtype == RELAX_LITERAL_POOL_END); | |
11125 | /* Create a local symbol pointing to the | |
11126 | end of the pool. */ | |
11127 | sprintf (label, ".L0_LT_%p", poolbeg); | |
e01e1cee | 11128 | lsym = (symbolS *) local_symbol_make (label, lps->seg, poolend, 0); |
947fa914 MF |
11129 | poolbeg->fr_symbol = lsym; |
11130 | /* Rest is done in xtensa_relax_frag. */ | |
11131 | } | |
11132 | ||
cd665a94 MF |
11133 | static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps, |
11134 | struct litpool_frag *lpf, | |
11135 | addressT addr) | |
11136 | { | |
11137 | struct litpool_frag *lp = lpf->prev; | |
11138 | ||
11139 | gas_assert (lp->fragP); | |
11140 | ||
11141 | while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11142 | { | |
11143 | lp = lp->prev; | |
11144 | if (lp->fragP == NULL) | |
11145 | { | |
11146 | /* End of list; have to bite the bullet. | |
11147 | Take the nearest. */ | |
11148 | lp = lpf->prev; | |
11149 | break; | |
11150 | } | |
11151 | /* Does it (conservatively) reach? */ | |
11152 | if (addr - lp->addr <= 128 * 1024) | |
11153 | { | |
11154 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
11155 | lp->literal_count < MAX_POOL_LITERALS) | |
11156 | { | |
11157 | /* Found a good one. */ | |
11158 | break; | |
11159 | } | |
11160 | else if (lp->prev->fragP && | |
11161 | addr - lp->prev->addr > 128 * 1024 && | |
11162 | lp->prev->literal_count < MAX_POOL_LITERALS) | |
11163 | { | |
11164 | /* This is still a "candidate" but the next one | |
11165 | will be too far away, so revert to the nearest | |
11166 | one, convert it and add the jump around. */ | |
11167 | lp = lpf->prev; | |
11168 | break; | |
11169 | } | |
11170 | } | |
11171 | } | |
11172 | ||
11173 | if (lp->literal_count >= MAX_POOL_LITERALS) | |
11174 | { | |
11175 | lp = lpf->prev; | |
11176 | while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS) | |
11177 | { | |
11178 | lp = lp->prev; | |
11179 | } | |
11180 | gas_assert (lp); | |
11181 | } | |
11182 | ||
11183 | gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS); | |
11184 | ++lp->literal_count; | |
11185 | ||
11186 | /* Convert candidate and add the jump around. */ | |
11187 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11188 | xg_promote_candidate_litpool (lps, lp); | |
11189 | ||
11190 | return lp; | |
11191 | } | |
11192 | ||
5b7c81bd | 11193 | static bool xtensa_is_init_fini (segT seg) |
d0ad159d MF |
11194 | { |
11195 | if (!seg) | |
11196 | return 0; | |
11197 | return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0 | |
11198 | || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0; | |
11199 | } | |
11200 | ||
7fa3d080 | 11201 | static void |
f8aecf3c | 11202 | xtensa_assign_litpool_addresses (void) |
e0001a05 | 11203 | { |
b46824bd | 11204 | struct litpool_seg *lps; |
b46824bd MF |
11205 | |
11206 | for (lps = litpool_seg_list.next; lps; lps = lps->next) | |
11207 | { | |
11208 | frchainS *frchP = seg_info (lps->seg)->frchainP; | |
11209 | struct litpool_frag *lpf = lps->frag_list.next; | |
11210 | addressT addr = 0; | |
11211 | ||
d0ad159d MF |
11212 | if (xtensa_is_init_fini (lps->seg)) |
11213 | continue; | |
11214 | ||
b46824bd MF |
11215 | for ( ; frchP; frchP = frchP->frch_next) |
11216 | { | |
11217 | fragS *fragP; | |
11218 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
11219 | { | |
11220 | if (lpf && fragP == lpf->fragP) | |
11221 | { | |
11222 | gas_assert(fragP->fr_type == rs_machine_dependent && | |
11223 | (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || | |
11224 | fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); | |
11225 | /* Found a litpool location. */ | |
11226 | lpf->addr = addr; | |
11227 | lpf = lpf->next; | |
11228 | } | |
11229 | if (fragP->fr_type == rs_machine_dependent && | |
11230 | fragP->fr_subtype == RELAX_SLOTS) | |
11231 | { | |
11232 | int slot; | |
11233 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
11234 | { | |
d0ad159d MF |
11235 | fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; |
11236 | ||
11237 | if (litfrag | |
11238 | && litfrag->tc_frag_data.is_literal | |
11239 | && !litfrag->tc_frag_data.literal_frag) | |
b46824bd | 11240 | { |
d0ad159d MF |
11241 | /* L32R referring .literal or generated as a result |
11242 | of relaxation. Point its literal to the nearest | |
11243 | litpool preferring non-"candidate" positions to | |
11244 | avoid the jump-around. */ | |
11245 | ||
11246 | struct litpool_frag *lp; | |
11247 | ||
11248 | lp = xg_find_litpool (lps, lpf, addr); | |
11249 | /* Take earliest use of this literal to avoid | |
11250 | forward refs. */ | |
11251 | litfrag->tc_frag_data.literal_frag = lp->fragP; | |
b46824bd MF |
11252 | } |
11253 | } | |
11254 | } | |
11255 | addr += fragP->fr_fix; | |
11256 | if (fragP->fr_type == rs_fill) | |
11257 | addr += fragP->fr_offset; | |
11258 | } | |
11259 | } | |
11260 | } | |
f8aecf3c | 11261 | } |
b46824bd | 11262 | |
f8aecf3c MF |
11263 | static void |
11264 | xtensa_move_literals (void) | |
11265 | { | |
11266 | seg_list *segment; | |
11267 | frchainS *frchain_from, *frchain_to; | |
11268 | fragS *search_frag, *next_frag, *literal_pool, *insert_after; | |
11269 | fragS **frag_splice; | |
11270 | emit_state state; | |
11271 | segT dest_seg; | |
11272 | fixS *fix, *next_fix, **fix_splice; | |
11273 | sym_list *lit; | |
11274 | const char *init_name = INIT_SECTION_NAME; | |
11275 | const char *fini_name = FINI_SECTION_NAME; | |
11276 | int init_name_len = strlen(init_name); | |
11277 | int fini_name_len = strlen(fini_name); | |
11278 | ||
11279 | mark_literal_frags (literal_head->next); | |
11280 | ||
11281 | if (use_literal_section) | |
11282 | return; | |
11283 | ||
11284 | /* Assign addresses (rough estimates) to the potential literal pool locations | |
11285 | and create new ones if the gaps are too large. */ | |
11286 | ||
11287 | xtensa_assign_litpool_addresses (); | |
11288 | ||
11289 | /* Walk through the literal segments. */ | |
74869ac7 | 11290 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 11291 | { |
4111950f MF |
11292 | const char *seg_name = segment_name (segment->seg); |
11293 | ||
74869ac7 | 11294 | /* Keep the literals for .init and .fini in separate sections. */ |
4111950f MF |
11295 | if ((!memcmp (seg_name, init_name, init_name_len) && |
11296 | !strcmp (seg_name + init_name_len, ".literal")) || | |
11297 | (!memcmp (seg_name, fini_name, fini_name_len) && | |
11298 | !strcmp (seg_name + fini_name_len, ".literal"))) | |
74869ac7 BW |
11299 | continue; |
11300 | ||
e0001a05 NC |
11301 | frchain_from = seg_info (segment->seg)->frchainP; |
11302 | search_frag = frchain_from->frch_root; | |
11303 | literal_pool = NULL; | |
11304 | frchain_to = NULL; | |
11305 | frag_splice = &(frchain_from->frch_root); | |
11306 | ||
4de0562a | 11307 | while (search_frag && !search_frag->tc_frag_data.literal_frag) |
e0001a05 | 11308 | { |
9c2799c2 | 11309 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
11310 | || search_frag->fr_type == rs_align); |
11311 | search_frag = search_frag->fr_next; | |
11312 | } | |
11313 | ||
4de0562a | 11314 | if (!search_frag) |
f8aecf3c | 11315 | continue; |
4de0562a | 11316 | |
9c2799c2 | 11317 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
11318 | == RELAX_LITERAL_POOL_BEGIN); |
11319 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
11320 | ||
11321 | /* Make sure that all the frags in this series are closed, and | |
11322 | that there is at least one left over of zero-size. This | |
11323 | prevents us from making a segment with an frchain without any | |
11324 | frags in it. */ | |
11325 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11326 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11327 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); |
43cd72b9 | 11328 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11329 | |
43cd72b9 | 11330 | while (search_frag != frag_now) |
e0001a05 NC |
11331 | { |
11332 | next_frag = search_frag->fr_next; | |
e0001a05 NC |
11333 | if (search_frag->tc_frag_data.literal_frag) |
11334 | { | |
11335 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 11336 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 11337 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 11338 | gas_assert (frchain_to); |
e0001a05 | 11339 | } |
b46824bd MF |
11340 | |
11341 | if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) | |
11342 | { | |
11343 | /* Skip empty fill frags. */ | |
11344 | *frag_splice = next_frag; | |
11345 | search_frag = next_frag; | |
11346 | continue; | |
11347 | } | |
11348 | ||
11349 | if (search_frag->fr_type == rs_align) | |
11350 | { | |
11351 | /* Skip alignment frags, because the pool as a whole will be | |
11352 | aligned if used, and we don't want to force alignment if the | |
11353 | pool is unused. */ | |
11354 | *frag_splice = next_frag; | |
11355 | search_frag = next_frag; | |
11356 | continue; | |
11357 | } | |
11358 | ||
11359 | /* First, move the frag out of the literal section and | |
11360 | to the appropriate place. */ | |
11361 | ||
33eaf5de | 11362 | /* Insert an alignment frag at start of pool. */ |
b46824bd MF |
11363 | if (literal_pool->fr_next->fr_type == rs_machine_dependent && |
11364 | literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) | |
11365 | { | |
11366 | segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; | |
11367 | emit_state prev_state; | |
11368 | fragS *prev_frag; | |
11369 | fragS *align_frag; | |
11370 | xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); | |
11371 | prev_frag = frag_now; | |
11372 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
11373 | align_frag = frag_now; | |
11374 | frag_align (2, 0, 0); | |
11375 | /* Splice it into the right place. */ | |
11376 | prev_frag->fr_next = align_frag->fr_next; | |
11377 | align_frag->fr_next = literal_pool->fr_next; | |
11378 | literal_pool->fr_next = align_frag; | |
11379 | /* Insert after this one. */ | |
11380 | literal_pool->tc_frag_data.literal_frag = align_frag; | |
11381 | xtensa_restore_emit_state (&prev_state); | |
11382 | } | |
c48aaca0 | 11383 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 11384 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
b46824bd MF |
11385 | /* Skip align frag. */ |
11386 | if (insert_after->fr_next->fr_type == rs_align) | |
11387 | { | |
11388 | insert_after = insert_after->fr_next; | |
11389 | } | |
43cd72b9 | 11390 | |
e0001a05 NC |
11391 | *frag_splice = next_frag; |
11392 | search_frag->fr_next = insert_after->fr_next; | |
11393 | insert_after->fr_next = search_frag; | |
11394 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 11395 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
11396 | |
11397 | /* Now move any fixups associated with this frag to the | |
11398 | right section. */ | |
11399 | fix = frchain_from->fix_root; | |
11400 | fix_splice = &(frchain_from->fix_root); | |
11401 | while (fix) | |
11402 | { | |
11403 | next_fix = fix->fx_next; | |
11404 | if (fix->fx_frag == search_frag) | |
11405 | { | |
11406 | *fix_splice = next_fix; | |
11407 | fix->fx_next = frchain_to->fix_root; | |
11408 | frchain_to->fix_root = fix; | |
11409 | if (frchain_to->fix_tail == NULL) | |
11410 | frchain_to->fix_tail = fix; | |
11411 | } | |
11412 | else | |
11413 | fix_splice = &(fix->fx_next); | |
11414 | fix = next_fix; | |
11415 | } | |
11416 | search_frag = next_frag; | |
11417 | } | |
11418 | ||
11419 | if (frchain_from->fix_root != NULL) | |
11420 | { | |
11421 | frchain_from = seg_info (segment->seg)->frchainP; | |
11422 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
11423 | ||
9c2799c2 | 11424 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
11425 | } |
11426 | frchain_from->fix_tail = NULL; | |
11427 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
11428 | } |
11429 | ||
82e7541d BW |
11430 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
11431 | for (lit = literal_syms; lit; lit = lit->next) | |
11432 | { | |
11433 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
11434 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
11435 | if (dseg) | |
11436 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 11437 | } |
e0001a05 NC |
11438 | } |
11439 | ||
11440 | ||
a7877748 BW |
11441 | /* Walk over all the frags for segments in a list and mark them as |
11442 | containing literals. As clunky as this is, we can't rely on frag_var | |
11443 | and frag_variant to get called in all situations. */ | |
11444 | ||
11445 | static void | |
7fa3d080 | 11446 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
11447 | { |
11448 | frchainS *frchain_from; | |
11449 | fragS *search_frag; | |
11450 | ||
11451 | while (segment) | |
11452 | { | |
11453 | frchain_from = seg_info (segment->seg)->frchainP; | |
11454 | search_frag = frchain_from->frch_root; | |
c138bc38 | 11455 | while (search_frag) |
a7877748 | 11456 | { |
5b7c81bd | 11457 | search_frag->tc_frag_data.is_literal = true; |
a7877748 BW |
11458 | search_frag = search_frag->fr_next; |
11459 | } | |
11460 | segment = segment->next; | |
11461 | } | |
11462 | } | |
11463 | ||
11464 | ||
e0001a05 | 11465 | static void |
7fa3d080 | 11466 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
11467 | { |
11468 | /* Move all of the sections in the section list to come | |
11469 | after "after" in the gnu segment list. */ | |
11470 | ||
11471 | head = head->next; | |
11472 | while (head) | |
11473 | { | |
11474 | segT literal_section = head->seg; | |
11475 | ||
11476 | /* Move the literal section after "after". */ | |
9c2799c2 | 11477 | gas_assert (literal_section); |
e0001a05 NC |
11478 | if (literal_section != after) |
11479 | { | |
69852798 AM |
11480 | bfd_section_list_remove (stdoutput, literal_section); |
11481 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
11482 | } |
11483 | ||
11484 | head = head->next; | |
11485 | } | |
11486 | } | |
11487 | ||
11488 | ||
11489 | /* Push all the literal segments to the end of the gnu list. */ | |
11490 | ||
7fa3d080 BW |
11491 | static void |
11492 | xtensa_reorder_segments (void) | |
e0001a05 NC |
11493 | { |
11494 | segT sec; | |
b08b5071 | 11495 | segT last_sec = 0; |
e0001a05 NC |
11496 | int old_count = 0; |
11497 | int new_count = 0; | |
11498 | ||
11499 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
11500 | { |
11501 | last_sec = sec; | |
11502 | old_count++; | |
11503 | } | |
e0001a05 NC |
11504 | |
11505 | /* Now that we have the last section, push all the literal | |
11506 | sections to the end. */ | |
e0001a05 | 11507 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
11508 | |
11509 | /* Now perform the final error check. */ | |
11510 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
11511 | new_count++; | |
9c2799c2 | 11512 | gas_assert (new_count == old_count); |
e0001a05 NC |
11513 | } |
11514 | ||
11515 | ||
e0001a05 NC |
11516 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
11517 | correct location. Return a emit_state which can be passed to | |
11518 | xtensa_restore_emit_state to return to current fragment. */ | |
11519 | ||
7fa3d080 BW |
11520 | static void |
11521 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
11522 | { |
11523 | if (directive_state[directive_absolute_literals]) | |
11524 | { | |
5b7c81bd | 11525 | segT lit4_seg = cache_literal_section (true); |
74869ac7 | 11526 | xtensa_switch_section_emit_state (result, lit4_seg, 0); |
43cd72b9 BW |
11527 | } |
11528 | else | |
11529 | xtensa_switch_to_non_abs_literal_fragment (result); | |
11530 | ||
11531 | /* Do a 4-byte align here. */ | |
11532 | frag_align (2, 0, 0); | |
11533 | record_alignment (now_seg, 2); | |
11534 | } | |
11535 | ||
11536 | ||
7fa3d080 BW |
11537 | static void |
11538 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 11539 | { |
e0001a05 | 11540 | fragS *pool_location = get_literal_pool_location (now_seg); |
74869ac7 | 11541 | segT lit_seg; |
5b7c81bd | 11542 | bool is_init_fini = xtensa_is_init_fini (now_seg); |
e0001a05 | 11543 | |
43cd72b9 BW |
11544 | if (pool_location == NULL |
11545 | && !use_literal_section | |
d0ad159d | 11546 | && !is_init_fini) |
e0001a05 | 11547 | { |
b46824bd MF |
11548 | if (!auto_litpools) |
11549 | { | |
11550 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); | |
11551 | } | |
5b7c81bd | 11552 | xtensa_maybe_create_literal_pool_frag (true, true); |
947fa914 | 11553 | pool_location = get_literal_pool_location (now_seg); |
e0001a05 NC |
11554 | } |
11555 | ||
5b7c81bd | 11556 | lit_seg = cache_literal_section (false); |
74869ac7 | 11557 | xtensa_switch_section_emit_state (result, lit_seg, 0); |
e0001a05 | 11558 | |
43cd72b9 | 11559 | if (!use_literal_section |
d0ad159d | 11560 | && !is_init_fini |
43cd72b9 | 11561 | && get_literal_pool_location (now_seg) != pool_location) |
e0001a05 NC |
11562 | { |
11563 | /* Close whatever frag is there. */ | |
11564 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11565 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
11566 | frag_now->tc_frag_data.literal_frag = pool_location; |
11567 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11568 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11569 | } |
e0001a05 NC |
11570 | } |
11571 | ||
11572 | ||
11573 | /* Call this function before emitting data into the literal section. | |
11574 | This is a helper function for xtensa_switch_to_literal_fragment. | |
11575 | This is similar to a .section new_now_seg subseg. */ | |
11576 | ||
7fa3d080 BW |
11577 | static void |
11578 | xtensa_switch_section_emit_state (emit_state *state, | |
11579 | segT new_now_seg, | |
11580 | subsegT new_now_subseg) | |
e0001a05 NC |
11581 | { |
11582 | state->name = now_seg->name; | |
11583 | state->now_seg = now_seg; | |
11584 | state->now_subseg = now_subseg; | |
11585 | state->generating_literals = generating_literals; | |
11586 | generating_literals++; | |
2b0210eb | 11587 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
11588 | } |
11589 | ||
11590 | ||
11591 | /* Use to restore the emitting into the normal place. */ | |
11592 | ||
7fa3d080 BW |
11593 | static void |
11594 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
11595 | { |
11596 | generating_literals = state->generating_literals; | |
2b0210eb | 11597 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
11598 | } |
11599 | ||
11600 | ||
74869ac7 | 11601 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 11602 | |
5b7c81bd | 11603 | static bool |
74869ac7 | 11604 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) |
e0001a05 | 11605 | { |
74869ac7 BW |
11606 | const char *gname = inf; |
11607 | const char *group_name = elf_group_name (sec); | |
3739860c | 11608 | |
74869ac7 BW |
11609 | return (group_name == gname |
11610 | || (group_name != NULL | |
11611 | && gname != NULL | |
11612 | && strcmp (group_name, gname) == 0)); | |
11613 | } | |
e0001a05 | 11614 | |
e0001a05 | 11615 | |
74869ac7 BW |
11616 | /* Get the literal section to be used for the current text section. |
11617 | The result may be cached in the default_lit_sections structure. */ | |
11618 | ||
11619 | static segT | |
5b7c81bd | 11620 | cache_literal_section (bool use_abs_literals) |
74869ac7 BW |
11621 | { |
11622 | const char *text_name, *group_name = 0; | |
b9bb4a93 TS |
11623 | const char *base_name, *suffix; |
11624 | char *name; | |
74869ac7 BW |
11625 | segT *pcached; |
11626 | segT seg, current_section; | |
11627 | int current_subsec; | |
5b7c81bd | 11628 | bool linkonce = false; |
74869ac7 BW |
11629 | |
11630 | /* Save the current section/subsection. */ | |
11631 | current_section = now_seg; | |
11632 | current_subsec = now_subseg; | |
11633 | ||
11634 | /* Clear the cached values if they are no longer valid. */ | |
11635 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 11636 | { |
74869ac7 BW |
11637 | default_lit_sections.current_text_seg = now_seg; |
11638 | default_lit_sections.lit_seg = NULL; | |
11639 | default_lit_sections.lit4_seg = NULL; | |
11640 | } | |
11641 | ||
11642 | /* Check if the literal section is already cached. */ | |
11643 | if (use_abs_literals) | |
11644 | pcached = &default_lit_sections.lit4_seg; | |
11645 | else | |
11646 | pcached = &default_lit_sections.lit_seg; | |
11647 | ||
11648 | if (*pcached) | |
11649 | return *pcached; | |
3739860c | 11650 | |
74869ac7 BW |
11651 | text_name = default_lit_sections.lit_prefix; |
11652 | if (! text_name || ! *text_name) | |
11653 | { | |
11654 | text_name = segment_name (current_section); | |
11655 | group_name = elf_group_name (current_section); | |
11656 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
11657 | } | |
11658 | ||
11659 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
11660 | if (group_name) | |
11661 | { | |
4ec9d7d5 | 11662 | name = concat (base_name, ".", group_name, (char *) NULL); |
74869ac7 BW |
11663 | } |
11664 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
11665 | { | |
11666 | suffix = strchr (text_name + linkonce_len, '.'); | |
11667 | ||
4ec9d7d5 TS |
11668 | name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", |
11669 | (char *) NULL); | |
5b7c81bd | 11670 | linkonce = true; |
74869ac7 BW |
11671 | } |
11672 | else | |
11673 | { | |
a89c407e SA |
11674 | /* If the section name begins or ends with ".text", then replace |
11675 | that portion instead of appending an additional suffix. */ | |
74869ac7 | 11676 | size_t len = strlen (text_name); |
a89c407e SA |
11677 | if (len >= 5 |
11678 | && (strcmp (text_name + len - 5, ".text") == 0 | |
d34049e8 | 11679 | || startswith (text_name, ".text"))) |
74869ac7 BW |
11680 | len -= 5; |
11681 | ||
add39d23 | 11682 | name = XNEWVEC (char, len + strlen (base_name) + 1); |
d34049e8 | 11683 | if (startswith (text_name, ".text")) |
a89c407e SA |
11684 | { |
11685 | strcpy (name, base_name); | |
11686 | strcat (name, text_name + 5); | |
11687 | } | |
11688 | else | |
11689 | { | |
11690 | strcpy (name, text_name); | |
11691 | strcpy (name + len, base_name); | |
11692 | } | |
b08b5071 | 11693 | } |
e0001a05 | 11694 | |
74869ac7 BW |
11695 | /* Canonicalize section names to allow renaming literal sections. |
11696 | The group name, if any, came from the current text section and | |
11697 | has already been canonicalized. */ | |
11698 | name = tc_canonicalize_symbol_name (name); | |
11699 | ||
11700 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
11701 | (void *) group_name); | |
11702 | if (! seg) | |
e0001a05 | 11703 | { |
74869ac7 BW |
11704 | flagword flags; |
11705 | ||
11706 | seg = subseg_force_new (name, 0); | |
11707 | ||
11708 | if (! use_abs_literals) | |
b08b5071 | 11709 | { |
74869ac7 | 11710 | /* Add the newly created literal segment to the list. */ |
325801bd | 11711 | seg_list *n = XNEW (seg_list); |
b08b5071 | 11712 | n->seg = seg; |
74869ac7 BW |
11713 | n->next = literal_head->next; |
11714 | literal_head->next = n; | |
b08b5071 | 11715 | } |
74869ac7 BW |
11716 | |
11717 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
11718 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
11719 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
11720 | ||
11721 | elf_group_name (seg) = group_name; | |
11722 | ||
fd361982 AM |
11723 | bfd_set_section_flags (seg, flags); |
11724 | bfd_set_section_alignment (seg, 2); | |
e0001a05 NC |
11725 | } |
11726 | ||
74869ac7 | 11727 | *pcached = seg; |
b08b5071 | 11728 | subseg_set (current_section, current_subsec); |
74869ac7 | 11729 | return seg; |
e0001a05 NC |
11730 | } |
11731 | ||
43cd72b9 BW |
11732 | \f |
11733 | /* Property Tables Stuff. */ | |
11734 | ||
7fa3d080 BW |
11735 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
11736 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
11737 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
11738 | ||
5b7c81bd | 11739 | typedef bool (*frag_predicate) (const fragS *); |
7fa3d080 BW |
11740 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); |
11741 | ||
5b7c81bd | 11742 | static bool get_frag_is_literal (const fragS *); |
7fa3d080 BW |
11743 | static void xtensa_create_property_segments |
11744 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
11745 | static void xtensa_create_xproperty_segments | |
11746 | (frag_flags_fn, const char *, xt_section_type); | |
5b7c81bd AM |
11747 | static bool exclude_section_from_property_tables (segT); |
11748 | static bool section_has_property (segT, frag_predicate); | |
11749 | static bool section_has_xproperty (segT, frag_flags_fn); | |
7fa3d080 | 11750 | static void add_xt_block_frags |
542f8b94 | 11751 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
5b7c81bd | 11752 | static bool xtensa_frag_flags_is_empty (const frag_flags *); |
7fa3d080 BW |
11753 | static void xtensa_frag_flags_init (frag_flags *); |
11754 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 11755 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 11756 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
11757 | |
11758 | /* Set up property tables after relaxation. */ | |
11759 | ||
11760 | void | |
11761 | xtensa_post_relax_hook (void) | |
11762 | { | |
11763 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
11764 | |
11765 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 11766 | xtensa_mark_frags_for_org (); |
6a7eedfe | 11767 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 11768 | |
b29757dc BW |
11769 | xtensa_create_property_segments (get_frag_is_literal, |
11770 | NULL, | |
11771 | XTENSA_LIT_SEC_NAME, | |
11772 | xt_literal_sec); | |
7fa3d080 BW |
11773 | xtensa_create_xproperty_segments (get_frag_property_flags, |
11774 | XTENSA_PROP_SEC_NAME, | |
11775 | xt_prop_sec); | |
11776 | ||
11777 | if (warn_unaligned_branch_targets) | |
11778 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
11779 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
11780 | } | |
11781 | ||
11782 | ||
43cd72b9 BW |
11783 | /* This function is only meaningful after xtensa_move_literals. */ |
11784 | ||
5b7c81bd | 11785 | static bool |
7fa3d080 | 11786 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 11787 | { |
9c2799c2 | 11788 | gas_assert (fragP != NULL); |
43cd72b9 BW |
11789 | return fragP->tc_frag_data.is_literal; |
11790 | } | |
11791 | ||
11792 | ||
43cd72b9 | 11793 | static void |
7fa3d080 BW |
11794 | xtensa_create_property_segments (frag_predicate property_function, |
11795 | frag_predicate end_property_function, | |
11796 | const char *section_name_base, | |
11797 | xt_section_type sec_type) | |
43cd72b9 BW |
11798 | { |
11799 | segT *seclist; | |
11800 | ||
11801 | /* Walk over all of the current segments. | |
11802 | Walk over each fragment | |
11803 | For each non-empty fragment, | |
11804 | Build a property record (append where possible). */ | |
11805 | ||
11806 | for (seclist = &stdoutput->sections; | |
11807 | seclist && *seclist; | |
11808 | seclist = &(*seclist)->next) | |
11809 | { | |
11810 | segT sec = *seclist; | |
43cd72b9 | 11811 | |
532f93bd | 11812 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11813 | continue; |
11814 | ||
11815 | if (section_has_property (sec, property_function)) | |
11816 | { | |
542f8b94 BW |
11817 | segment_info_type *xt_seg_info; |
11818 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11819 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11820 | |
11821 | prop_sec->output_section = prop_sec; | |
11822 | subseg_set (prop_sec, 0); | |
11823 | xt_seg_info = seg_info (prop_sec); | |
11824 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11825 | ||
43cd72b9 | 11826 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11827 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
11828 | end_property_function); |
11829 | } | |
11830 | } | |
11831 | ||
11832 | /* Now we fill them out.... */ | |
11833 | ||
11834 | for (seclist = &stdoutput->sections; | |
11835 | seclist && *seclist; | |
11836 | seclist = &(*seclist)->next) | |
11837 | { | |
11838 | segment_info_type *seginfo; | |
11839 | xtensa_block_info *block; | |
11840 | segT sec = *seclist; | |
11841 | ||
11842 | seginfo = seg_info (sec); | |
11843 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11844 | ||
11845 | if (block) | |
11846 | { | |
11847 | xtensa_block_info *cur_block; | |
43cd72b9 | 11848 | int num_recs = 0; |
d77b99c9 | 11849 | bfd_size_type rec_size; |
43cd72b9 BW |
11850 | |
11851 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11852 | num_recs++; | |
11853 | ||
11854 | rec_size = num_recs * 8; | |
fd361982 | 11855 | bfd_set_section_size (sec, rec_size); |
43cd72b9 | 11856 | |
43cd72b9 BW |
11857 | if (num_recs) |
11858 | { | |
43cd72b9 | 11859 | char *frag_data; |
542f8b94 | 11860 | int i; |
43cd72b9 | 11861 | |
542f8b94 BW |
11862 | subseg_set (sec, 0); |
11863 | frag_data = frag_more (rec_size); | |
43cd72b9 | 11864 | cur_block = block; |
43cd72b9 BW |
11865 | for (i = 0; i < num_recs; i++) |
11866 | { | |
542f8b94 | 11867 | fixS *fix; |
e0001a05 | 11868 | |
43cd72b9 | 11869 | /* Write the fixup. */ |
9c2799c2 | 11870 | gas_assert (cur_block); |
542f8b94 BW |
11871 | fix = fix_new (frag_now, i * 8, 4, |
11872 | section_symbol (cur_block->sec), | |
11873 | cur_block->offset, | |
5b7c81bd | 11874 | false, BFD_RELOC_32); |
542f8b94 | 11875 | fix->fx_file = "<internal>"; |
43cd72b9 | 11876 | fix->fx_line = 0; |
e0001a05 | 11877 | |
43cd72b9 | 11878 | /* Write the length. */ |
542f8b94 | 11879 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
11880 | cur_block->size, 4); |
11881 | cur_block = cur_block->next; | |
11882 | } | |
542f8b94 BW |
11883 | frag_wane (frag_now); |
11884 | frag_new (0); | |
11885 | frag_wane (frag_now); | |
43cd72b9 BW |
11886 | } |
11887 | } | |
11888 | } | |
e0001a05 NC |
11889 | } |
11890 | ||
11891 | ||
7fa3d080 BW |
11892 | static void |
11893 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
11894 | const char *section_name_base, | |
11895 | xt_section_type sec_type) | |
e0001a05 NC |
11896 | { |
11897 | segT *seclist; | |
11898 | ||
11899 | /* Walk over all of the current segments. | |
43cd72b9 BW |
11900 | Walk over each fragment. |
11901 | For each fragment that has instructions, | |
11902 | build an instruction record (append where possible). */ | |
e0001a05 NC |
11903 | |
11904 | for (seclist = &stdoutput->sections; | |
11905 | seclist && *seclist; | |
11906 | seclist = &(*seclist)->next) | |
11907 | { | |
11908 | segT sec = *seclist; | |
43cd72b9 | 11909 | |
532f93bd | 11910 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11911 | continue; |
11912 | ||
11913 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 11914 | { |
542f8b94 BW |
11915 | segment_info_type *xt_seg_info; |
11916 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11917 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11918 | |
11919 | prop_sec->output_section = prop_sec; | |
11920 | subseg_set (prop_sec, 0); | |
11921 | xt_seg_info = seg_info (prop_sec); | |
11922 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11923 | ||
e0001a05 | 11924 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11925 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
11926 | } |
11927 | } | |
11928 | ||
11929 | /* Now we fill them out.... */ | |
11930 | ||
11931 | for (seclist = &stdoutput->sections; | |
11932 | seclist && *seclist; | |
11933 | seclist = &(*seclist)->next) | |
11934 | { | |
11935 | segment_info_type *seginfo; | |
11936 | xtensa_block_info *block; | |
11937 | segT sec = *seclist; | |
43cd72b9 | 11938 | |
e0001a05 NC |
11939 | seginfo = seg_info (sec); |
11940 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11941 | ||
11942 | if (block) | |
11943 | { | |
11944 | xtensa_block_info *cur_block; | |
43cd72b9 | 11945 | int num_recs = 0; |
d77b99c9 | 11946 | bfd_size_type rec_size; |
e0001a05 NC |
11947 | |
11948 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11949 | num_recs++; | |
11950 | ||
43cd72b9 | 11951 | rec_size = num_recs * (8 + 4); |
fd361982 | 11952 | bfd_set_section_size (sec, rec_size); |
43cd72b9 BW |
11953 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
11954 | ||
e0001a05 NC |
11955 | if (num_recs) |
11956 | { | |
e0001a05 | 11957 | char *frag_data; |
542f8b94 | 11958 | int i; |
e0001a05 | 11959 | |
542f8b94 BW |
11960 | subseg_set (sec, 0); |
11961 | frag_data = frag_more (rec_size); | |
e0001a05 | 11962 | cur_block = block; |
e0001a05 NC |
11963 | for (i = 0; i < num_recs; i++) |
11964 | { | |
542f8b94 | 11965 | fixS *fix; |
e0001a05 NC |
11966 | |
11967 | /* Write the fixup. */ | |
9c2799c2 | 11968 | gas_assert (cur_block); |
542f8b94 BW |
11969 | fix = fix_new (frag_now, i * 12, 4, |
11970 | section_symbol (cur_block->sec), | |
11971 | cur_block->offset, | |
5b7c81bd | 11972 | false, BFD_RELOC_32); |
542f8b94 | 11973 | fix->fx_file = "<internal>"; |
e0001a05 NC |
11974 | fix->fx_line = 0; |
11975 | ||
11976 | /* Write the length. */ | |
542f8b94 | 11977 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 11978 | cur_block->size, 4); |
542f8b94 | 11979 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 11980 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 11981 | sizeof (flagword)); |
e0001a05 NC |
11982 | cur_block = cur_block->next; |
11983 | } | |
542f8b94 BW |
11984 | frag_wane (frag_now); |
11985 | frag_new (0); | |
11986 | frag_wane (frag_now); | |
e0001a05 NC |
11987 | } |
11988 | } | |
11989 | } | |
11990 | } | |
11991 | ||
11992 | ||
5b7c81bd | 11993 | static bool |
532f93bd BW |
11994 | exclude_section_from_property_tables (segT sec) |
11995 | { | |
fd361982 | 11996 | flagword flags = bfd_section_flags (sec); |
532f93bd BW |
11997 | |
11998 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
11999 | if ((flags & SEC_DEBUGGING) | |
12000 | || !(flags & SEC_ALLOC) | |
12001 | || (flags & SEC_MERGE)) | |
5b7c81bd | 12002 | return true; |
532f93bd BW |
12003 | |
12004 | /* Linker cie and fde optimizations mess up property entries for | |
12005 | eh_frame sections, but there is nothing inside them relevant to | |
12006 | property tables anyway. */ | |
12007 | if (strcmp (sec->name, ".eh_frame") == 0) | |
5b7c81bd | 12008 | return true; |
532f93bd | 12009 | |
5b7c81bd | 12010 | return false; |
532f93bd BW |
12011 | } |
12012 | ||
12013 | ||
5b7c81bd | 12014 | static bool |
7fa3d080 | 12015 | section_has_property (segT sec, frag_predicate property_function) |
e0001a05 NC |
12016 | { |
12017 | segment_info_type *seginfo = seg_info (sec); | |
12018 | fragS *fragP; | |
12019 | ||
12020 | if (seginfo && seginfo->frchainP) | |
12021 | { | |
12022 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12023 | { | |
12024 | if (property_function (fragP) | |
12025 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
5b7c81bd | 12026 | return true; |
e0001a05 NC |
12027 | } |
12028 | } | |
5b7c81bd | 12029 | return false; |
e0001a05 NC |
12030 | } |
12031 | ||
12032 | ||
5b7c81bd | 12033 | static bool |
7fa3d080 | 12034 | section_has_xproperty (segT sec, frag_flags_fn property_function) |
43cd72b9 BW |
12035 | { |
12036 | segment_info_type *seginfo = seg_info (sec); | |
12037 | fragS *fragP; | |
12038 | ||
12039 | if (seginfo && seginfo->frchainP) | |
12040 | { | |
12041 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12042 | { | |
12043 | frag_flags prop_flags; | |
12044 | property_function (fragP, &prop_flags); | |
12045 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
5b7c81bd | 12046 | return true; |
43cd72b9 BW |
12047 | } |
12048 | } | |
5b7c81bd | 12049 | return false; |
43cd72b9 BW |
12050 | } |
12051 | ||
12052 | ||
e0001a05 NC |
12053 | /* Two types of block sections exist right now: literal and insns. */ |
12054 | ||
7fa3d080 BW |
12055 | static void |
12056 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
12057 | xtensa_block_info **xt_block, |
12058 | frag_predicate property_function, | |
12059 | frag_predicate end_property_function) | |
e0001a05 | 12060 | { |
e0001a05 NC |
12061 | fragS *fragP; |
12062 | ||
e0001a05 NC |
12063 | /* Build it if needed. */ |
12064 | while (*xt_block != NULL) | |
12065 | xt_block = &(*xt_block)->next; | |
12066 | /* We are either at NULL at the beginning or at the end. */ | |
12067 | ||
12068 | /* Walk through the frags. */ | |
542f8b94 | 12069 | if (seg_info (sec)->frchainP) |
e0001a05 | 12070 | { |
542f8b94 | 12071 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
12072 | fragP; |
12073 | fragP = fragP->fr_next) | |
12074 | { | |
12075 | if (property_function (fragP) | |
12076 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
12077 | { | |
12078 | if (*xt_block != NULL) | |
12079 | { | |
12080 | if ((*xt_block)->offset + (*xt_block)->size | |
12081 | == fragP->fr_address) | |
12082 | (*xt_block)->size += fragP->fr_fix; | |
12083 | else | |
12084 | xt_block = &((*xt_block)->next); | |
12085 | } | |
12086 | if (*xt_block == NULL) | |
12087 | { | |
325801bd | 12088 | xtensa_block_info *new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12089 | new_block->sec = sec; |
12090 | new_block->offset = fragP->fr_address; | |
12091 | new_block->size = fragP->fr_fix; | |
12092 | new_block->next = NULL; | |
12093 | xtensa_frag_flags_init (&new_block->flags); | |
12094 | *xt_block = new_block; | |
12095 | } | |
12096 | if (end_property_function | |
12097 | && end_property_function (fragP)) | |
12098 | { | |
12099 | xt_block = &((*xt_block)->next); | |
12100 | } | |
12101 | } | |
12102 | } | |
12103 | } | |
12104 | } | |
12105 | ||
12106 | ||
12107 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
12108 | ||
5b7c81bd | 12109 | static bool |
7fa3d080 | 12110 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) |
43cd72b9 BW |
12111 | { |
12112 | if (prop_flags->is_literal | |
12113 | || prop_flags->is_insn | |
12114 | || prop_flags->is_data | |
12115 | || prop_flags->is_unreachable) | |
5b7c81bd AM |
12116 | return false; |
12117 | return true; | |
43cd72b9 BW |
12118 | } |
12119 | ||
12120 | ||
7fa3d080 BW |
12121 | static void |
12122 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
12123 | { |
12124 | memset (prop_flags, 0, sizeof (frag_flags)); | |
12125 | } | |
12126 | ||
12127 | ||
7fa3d080 BW |
12128 | static void |
12129 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
12130 | { |
12131 | xtensa_frag_flags_init (prop_flags); | |
12132 | if (fragP->tc_frag_data.is_literal) | |
5b7c81bd | 12133 | prop_flags->is_literal = true; |
99ded152 BW |
12134 | if (fragP->tc_frag_data.is_specific_opcode |
12135 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae | 12136 | { |
5b7c81bd | 12137 | prop_flags->is_no_transform = true; |
1f7efbae | 12138 | if (xtensa_frag_flags_is_empty (prop_flags)) |
5b7c81bd | 12139 | prop_flags->is_data = true; |
1f7efbae | 12140 | } |
43cd72b9 | 12141 | if (fragP->tc_frag_data.is_unreachable) |
5b7c81bd | 12142 | prop_flags->is_unreachable = true; |
43cd72b9 BW |
12143 | else if (fragP->tc_frag_data.is_insn) |
12144 | { | |
5b7c81bd | 12145 | prop_flags->is_insn = true; |
43cd72b9 | 12146 | if (fragP->tc_frag_data.is_loop_target) |
5b7c81bd | 12147 | prop_flags->insn.is_loop_target = true; |
43cd72b9 | 12148 | if (fragP->tc_frag_data.is_branch_target) |
5b7c81bd | 12149 | prop_flags->insn.is_branch_target = true; |
43cd72b9 | 12150 | if (fragP->tc_frag_data.is_no_density) |
5b7c81bd | 12151 | prop_flags->insn.is_no_density = true; |
43cd72b9 | 12152 | if (fragP->tc_frag_data.use_absolute_literals) |
5b7c81bd | 12153 | prop_flags->insn.is_abslit = true; |
43cd72b9 BW |
12154 | } |
12155 | if (fragP->tc_frag_data.is_align) | |
12156 | { | |
5b7c81bd | 12157 | prop_flags->is_align = true; |
43cd72b9 BW |
12158 | prop_flags->alignment = fragP->tc_frag_data.alignment; |
12159 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
5b7c81bd | 12160 | prop_flags->is_data = true; |
43cd72b9 BW |
12161 | } |
12162 | } | |
12163 | ||
12164 | ||
2f1bf5c1 | 12165 | static flagword |
7fa3d080 | 12166 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 12167 | { |
2f1bf5c1 | 12168 | flagword num = 0; |
43cd72b9 BW |
12169 | if (prop_flags->is_literal) |
12170 | num |= XTENSA_PROP_LITERAL; | |
12171 | if (prop_flags->is_insn) | |
12172 | num |= XTENSA_PROP_INSN; | |
12173 | if (prop_flags->is_data) | |
12174 | num |= XTENSA_PROP_DATA; | |
12175 | if (prop_flags->is_unreachable) | |
12176 | num |= XTENSA_PROP_UNREACHABLE; | |
12177 | if (prop_flags->insn.is_loop_target) | |
12178 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
12179 | if (prop_flags->insn.is_branch_target) | |
12180 | { | |
12181 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
12182 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
12183 | } | |
12184 | ||
12185 | if (prop_flags->insn.is_no_density) | |
12186 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
12187 | if (prop_flags->is_no_transform) |
12188 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
12189 | if (prop_flags->insn.is_no_reorder) |
12190 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
12191 | if (prop_flags->insn.is_abslit) | |
12192 | num |= XTENSA_PROP_INSN_ABSLIT; | |
12193 | ||
12194 | if (prop_flags->is_align) | |
12195 | { | |
12196 | num |= XTENSA_PROP_ALIGN; | |
12197 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
12198 | } | |
12199 | ||
12200 | return num; | |
12201 | } | |
12202 | ||
12203 | ||
5b7c81bd | 12204 | static bool |
7fa3d080 BW |
12205 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
12206 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
12207 | { |
12208 | /* Cannot combine with an end marker. */ | |
12209 | ||
12210 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
5b7c81bd | 12211 | return false; |
43cd72b9 | 12212 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) |
5b7c81bd | 12213 | return false; |
43cd72b9 | 12214 | if (prop_flags_1->is_data != prop_flags_2->is_data) |
5b7c81bd | 12215 | return false; |
43cd72b9 BW |
12216 | |
12217 | if (prop_flags_1->is_insn) | |
12218 | { | |
12219 | /* Properties of the beginning of the frag. */ | |
12220 | if (prop_flags_2->insn.is_loop_target) | |
5b7c81bd | 12221 | return false; |
43cd72b9 | 12222 | if (prop_flags_2->insn.is_branch_target) |
5b7c81bd | 12223 | return false; |
43cd72b9 BW |
12224 | if (prop_flags_1->insn.is_no_density != |
12225 | prop_flags_2->insn.is_no_density) | |
5b7c81bd | 12226 | return false; |
99ded152 BW |
12227 | if (prop_flags_1->is_no_transform != |
12228 | prop_flags_2->is_no_transform) | |
5b7c81bd | 12229 | return false; |
43cd72b9 BW |
12230 | if (prop_flags_1->insn.is_no_reorder != |
12231 | prop_flags_2->insn.is_no_reorder) | |
5b7c81bd | 12232 | return false; |
43cd72b9 BW |
12233 | if (prop_flags_1->insn.is_abslit != |
12234 | prop_flags_2->insn.is_abslit) | |
5b7c81bd | 12235 | return false; |
43cd72b9 BW |
12236 | } |
12237 | ||
12238 | if (prop_flags_1->is_align) | |
5b7c81bd | 12239 | return false; |
43cd72b9 | 12240 | |
5b7c81bd | 12241 | return true; |
43cd72b9 BW |
12242 | } |
12243 | ||
12244 | ||
7fa3d080 BW |
12245 | static bfd_vma |
12246 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
12247 | { |
12248 | bfd_vma end_addr; | |
d77b99c9 | 12249 | unsigned align_bits; |
43cd72b9 BW |
12250 | |
12251 | if (!xt_block->flags.is_align) | |
12252 | return xt_block->size; | |
12253 | ||
12254 | end_addr = xt_block->offset + xt_block->size; | |
12255 | align_bits = xt_block->flags.alignment; | |
12256 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
12257 | return end_addr - xt_block->offset; | |
12258 | } | |
12259 | ||
12260 | ||
5b7c81bd | 12261 | static bool |
7fa3d080 BW |
12262 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
12263 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
12264 | { |
12265 | if (xt_block->sec != xt_block_2->sec) | |
5b7c81bd | 12266 | return false; |
43cd72b9 BW |
12267 | if (xt_block->offset + xt_block_aligned_size (xt_block) |
12268 | != xt_block_2->offset) | |
5b7c81bd | 12269 | return false; |
43cd72b9 BW |
12270 | |
12271 | if (xt_block_2->size == 0 | |
12272 | && (!xt_block_2->flags.is_unreachable | |
12273 | || xt_block->flags.is_unreachable)) | |
12274 | { | |
12275 | if (xt_block_2->flags.is_align | |
12276 | && xt_block->flags.is_align) | |
12277 | { | |
12278 | /* Nothing needed. */ | |
12279 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
5b7c81bd | 12280 | return true; |
43cd72b9 BW |
12281 | } |
12282 | else | |
12283 | { | |
12284 | if (xt_block_2->flags.is_align) | |
12285 | { | |
12286 | /* Push alignment to previous entry. */ | |
12287 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
12288 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12289 | } | |
5b7c81bd | 12290 | return true; |
43cd72b9 BW |
12291 | } |
12292 | } | |
12293 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
12294 | &xt_block_2->flags)) | |
5b7c81bd | 12295 | return false; |
43cd72b9 BW |
12296 | |
12297 | xt_block->size += xt_block_2->size; | |
12298 | ||
12299 | if (xt_block_2->flags.is_align) | |
12300 | { | |
5b7c81bd | 12301 | xt_block->flags.is_align = true; |
43cd72b9 BW |
12302 | xt_block->flags.alignment = xt_block_2->flags.alignment; |
12303 | } | |
12304 | ||
5b7c81bd | 12305 | return true; |
43cd72b9 BW |
12306 | } |
12307 | ||
12308 | ||
7fa3d080 BW |
12309 | static void |
12310 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
12311 | xtensa_block_info **xt_block, |
12312 | frag_flags_fn property_function) | |
43cd72b9 | 12313 | { |
43cd72b9 BW |
12314 | fragS *fragP; |
12315 | ||
43cd72b9 BW |
12316 | /* Build it if needed. */ |
12317 | while (*xt_block != NULL) | |
12318 | { | |
12319 | xt_block = &(*xt_block)->next; | |
12320 | } | |
12321 | /* We are either at NULL at the beginning or at the end. */ | |
12322 | ||
12323 | /* Walk through the frags. */ | |
542f8b94 | 12324 | if (seg_info (sec)->frchainP) |
43cd72b9 | 12325 | { |
542f8b94 | 12326 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
12327 | fragP = fragP->fr_next) |
12328 | { | |
12329 | xtensa_block_info tmp_block; | |
12330 | tmp_block.sec = sec; | |
12331 | tmp_block.offset = fragP->fr_address; | |
12332 | tmp_block.size = fragP->fr_fix; | |
12333 | tmp_block.next = NULL; | |
12334 | property_function (fragP, &tmp_block.flags); | |
12335 | ||
12336 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
12337 | /* && fragP->fr_fix != 0) */ | |
12338 | { | |
12339 | if ((*xt_block) == NULL | |
12340 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
12341 | { | |
12342 | xtensa_block_info *new_block; | |
12343 | if ((*xt_block) != NULL) | |
12344 | xt_block = &(*xt_block)->next; | |
325801bd | 12345 | new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12346 | *new_block = tmp_block; |
12347 | *xt_block = new_block; | |
12348 | } | |
12349 | } | |
12350 | } | |
12351 | } | |
12352 | } | |
12353 | ||
12354 | \f | |
12355 | /* op_placement_info_table */ | |
12356 | ||
12357 | /* op_placement_info makes it easier to determine which | |
12358 | ops can go in which slots. */ | |
12359 | ||
12360 | static void | |
7fa3d080 | 12361 | init_op_placement_info_table (void) |
43cd72b9 BW |
12362 | { |
12363 | xtensa_isa isa = xtensa_default_isa; | |
12364 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
12365 | xtensa_opcode opcode; | |
12366 | xtensa_format fmt; | |
12367 | int slot; | |
12368 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
12369 | ||
325801bd | 12370 | op_placement_table = XNEWVEC (op_placement_info, num_opcodes); |
9c2799c2 | 12371 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
12372 | |
12373 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
12374 | { | |
12375 | op_placement_info *opi = &op_placement_table[opcode]; | |
12376 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 12377 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 12378 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
12379 | opi->narrowest = XTENSA_UNDEFINED; |
12380 | opi->narrowest_size = 0x7F; | |
b2d179be | 12381 | opi->narrowest_slot = 0; |
43cd72b9 BW |
12382 | opi->formats = 0; |
12383 | opi->num_formats = 0; | |
12384 | opi->issuef = 0; | |
12385 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
12386 | { | |
12387 | opi->slots[fmt] = 0; | |
12388 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
12389 | { | |
12390 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
12391 | { | |
12392 | int fmt_length = xtensa_format_length (isa, fmt); | |
12393 | opi->issuef++; | |
12394 | set_bit (fmt, opi->formats); | |
12395 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
12396 | if (fmt_length < opi->narrowest_size |
12397 | || (fmt_length == opi->narrowest_size | |
12398 | && (xtensa_format_num_slots (isa, fmt) | |
12399 | < xtensa_format_num_slots (isa, | |
12400 | opi->narrowest)))) | |
43cd72b9 BW |
12401 | { |
12402 | opi->narrowest = fmt; | |
12403 | opi->narrowest_size = fmt_length; | |
b2d179be | 12404 | opi->narrowest_slot = slot; |
43cd72b9 | 12405 | } |
e0001a05 NC |
12406 | } |
12407 | } | |
43cd72b9 BW |
12408 | if (opi->formats) |
12409 | opi->num_formats++; | |
e0001a05 NC |
12410 | } |
12411 | } | |
43cd72b9 BW |
12412 | xtensa_insnbuf_free (isa, ibuf); |
12413 | } | |
12414 | ||
12415 | ||
5b7c81bd | 12416 | bool |
7fa3d080 | 12417 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
12418 | { |
12419 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
12420 | } | |
12421 | ||
12422 | ||
12423 | /* If the opcode is available in a single slot format, return its size. */ | |
12424 | ||
7fa3d080 BW |
12425 | static int |
12426 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 12427 | { |
b2d179be | 12428 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
12429 | } |
12430 | ||
12431 | ||
7fa3d080 BW |
12432 | static xtensa_format |
12433 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 12434 | { |
b2d179be BW |
12435 | return op_placement_table[opcode].narrowest; |
12436 | } | |
12437 | ||
12438 | ||
12439 | static int | |
12440 | xg_get_single_slot (xtensa_opcode opcode) | |
12441 | { | |
12442 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
12443 | } |
12444 | ||
12445 | \f | |
12446 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
12447 | ||
12448 | void | |
7fa3d080 | 12449 | istack_init (IStack *stack) |
e0001a05 | 12450 | { |
e0001a05 NC |
12451 | stack->ninsn = 0; |
12452 | } | |
12453 | ||
12454 | ||
5b7c81bd | 12455 | bool |
7fa3d080 | 12456 | istack_empty (IStack *stack) |
e0001a05 NC |
12457 | { |
12458 | return (stack->ninsn == 0); | |
12459 | } | |
12460 | ||
12461 | ||
5b7c81bd | 12462 | bool |
7fa3d080 | 12463 | istack_full (IStack *stack) |
e0001a05 NC |
12464 | { |
12465 | return (stack->ninsn == MAX_ISTACK); | |
12466 | } | |
12467 | ||
12468 | ||
12469 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 12470 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
12471 | |
12472 | TInsn * | |
7fa3d080 | 12473 | istack_top (IStack *stack) |
e0001a05 NC |
12474 | { |
12475 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12476 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
12477 | return &stack->insn[rec]; |
12478 | } | |
12479 | ||
12480 | ||
12481 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 12482 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12483 | |
12484 | void | |
7fa3d080 | 12485 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
12486 | { |
12487 | int rec = stack->ninsn; | |
9c2799c2 | 12488 | gas_assert (!istack_full (stack)); |
43cd72b9 | 12489 | stack->insn[rec] = *insn; |
e0001a05 NC |
12490 | stack->ninsn++; |
12491 | } | |
12492 | ||
12493 | ||
12494 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 12495 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12496 | |
12497 | TInsn * | |
7fa3d080 | 12498 | istack_push_space (IStack *stack) |
e0001a05 NC |
12499 | { |
12500 | int rec = stack->ninsn; | |
12501 | TInsn *insn; | |
9c2799c2 | 12502 | gas_assert (!istack_full (stack)); |
e0001a05 | 12503 | insn = &stack->insn[rec]; |
60242db2 | 12504 | tinsn_init (insn); |
e0001a05 NC |
12505 | stack->ninsn++; |
12506 | return insn; | |
12507 | } | |
12508 | ||
12509 | ||
12510 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 12511 | istack_empty () returns TRUE. */ |
e0001a05 NC |
12512 | |
12513 | void | |
7fa3d080 | 12514 | istack_pop (IStack *stack) |
e0001a05 NC |
12515 | { |
12516 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12517 | gas_assert (!istack_empty (stack)); |
e0001a05 | 12518 | stack->ninsn--; |
60242db2 | 12519 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
12520 | } |
12521 | ||
12522 | \f | |
12523 | /* TInsn functions. */ | |
12524 | ||
12525 | void | |
7fa3d080 | 12526 | tinsn_init (TInsn *dst) |
e0001a05 NC |
12527 | { |
12528 | memset (dst, 0, sizeof (TInsn)); | |
12529 | } | |
12530 | ||
12531 | ||
43cd72b9 | 12532 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 | 12533 | |
5b7c81bd | 12534 | static bool |
7fa3d080 | 12535 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
12536 | { |
12537 | int i; | |
12538 | int n = insn->ntok; | |
12539 | ||
9c2799c2 | 12540 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12541 | |
12542 | for (i = 0; i < n; ++i) | |
12543 | { | |
12544 | switch (insn->tok[i].X_op) | |
12545 | { | |
12546 | case O_register: | |
12547 | case O_constant: | |
12548 | break; | |
12549 | default: | |
5b7c81bd | 12550 | return true; |
e0001a05 NC |
12551 | } |
12552 | } | |
5b7c81bd | 12553 | return false; |
e0001a05 NC |
12554 | } |
12555 | ||
12556 | ||
5b7c81bd | 12557 | bool |
7fa3d080 | 12558 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 12559 | { |
43cd72b9 | 12560 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
12561 | int i; |
12562 | int n = insn->ntok; | |
12563 | ||
9c2799c2 | 12564 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12565 | |
12566 | for (i = 0; i < n; ++i) | |
12567 | { | |
12568 | switch (insn->tok[i].X_op) | |
12569 | { | |
12570 | case O_register: | |
12571 | case O_constant: | |
12572 | break; | |
43cd72b9 BW |
12573 | case O_big: |
12574 | case O_illegal: | |
12575 | case O_absent: | |
12576 | /* Errors for these types are caught later. */ | |
12577 | break; | |
12578 | case O_hi16: | |
12579 | case O_lo16: | |
e0001a05 | 12580 | default: |
43cd72b9 BW |
12581 | /* Symbolic immediates are only allowed on the last immediate |
12582 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 12583 | support non-PC-relative relocations. */ |
43cd72b9 BW |
12584 | if (i != get_relaxable_immed (insn->opcode) |
12585 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
12586 | && insn->opcode != xtensa_const16_opcode)) | |
12587 | { | |
431ad2d0 | 12588 | as_bad (_("invalid symbolic operand")); |
5b7c81bd | 12589 | return true; |
43cd72b9 | 12590 | } |
e0001a05 NC |
12591 | } |
12592 | } | |
5b7c81bd | 12593 | return false; |
e0001a05 NC |
12594 | } |
12595 | ||
12596 | ||
12597 | /* For assembly code with complex expressions (e.g. subtraction), | |
12598 | we have to build them in the literal pool so that | |
12599 | their results are calculated correctly after relaxation. | |
12600 | The relaxation only handles expressions that | |
12601 | boil down to SYMBOL + OFFSET. */ | |
12602 | ||
5b7c81bd | 12603 | static bool |
7fa3d080 | 12604 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
12605 | { |
12606 | int i; | |
12607 | int n = insn->ntok; | |
9c2799c2 | 12608 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12609 | for (i = 0; i < n; ++i) |
12610 | { | |
12611 | switch (insn->tok[i].X_op) | |
12612 | { | |
12613 | case O_register: | |
12614 | case O_constant: | |
12615 | case O_symbol: | |
43cd72b9 BW |
12616 | case O_lo16: |
12617 | case O_hi16: | |
e0001a05 NC |
12618 | break; |
12619 | default: | |
5b7c81bd | 12620 | return true; |
e0001a05 NC |
12621 | } |
12622 | } | |
5b7c81bd | 12623 | return false; |
e0001a05 NC |
12624 | } |
12625 | ||
12626 | ||
b2d179be BW |
12627 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
12628 | Return TRUE if there is a symbol in the immediate field. This | |
12629 | function assumes that: | |
12630 | 1) The number of operands are correct. | |
12631 | 2) The insn_type is ITYPE_INSN. | |
12632 | 3) The opcode can be encoded in the specified format and slot. | |
12633 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 | 12634 | |
5b7c81bd | 12635 | static bool |
7fa3d080 BW |
12636 | tinsn_to_slotbuf (xtensa_format fmt, |
12637 | int slot, | |
12638 | TInsn *tinsn, | |
12639 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
12640 | { |
12641 | xtensa_isa isa = xtensa_default_isa; | |
12642 | xtensa_opcode opcode = tinsn->opcode; | |
5b7c81bd | 12643 | bool has_fixup = false; |
43cd72b9 BW |
12644 | int noperands = xtensa_opcode_num_operands (isa, opcode); |
12645 | int i; | |
12646 | ||
9c2799c2 | 12647 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
12648 | if (noperands != tinsn->ntok) |
12649 | as_fatal (_("operand number mismatch")); | |
12650 | ||
12651 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
12652 | { | |
12653 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
12654 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
5b7c81bd | 12655 | return false; |
43cd72b9 BW |
12656 | } |
12657 | ||
12658 | for (i = 0; i < noperands; i++) | |
12659 | { | |
91d6fa6a | 12660 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
12661 | int rc; |
12662 | unsigned line; | |
3b4dbbbf | 12663 | const char *file_name; |
43cd72b9 BW |
12664 | uint32 opnd_value; |
12665 | ||
91d6fa6a | 12666 | switch (exp->X_op) |
43cd72b9 BW |
12667 | { |
12668 | case O_register: | |
12669 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12670 | break; | |
12671 | /* The register number has already been checked in | |
12672 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 12673 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
12674 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
12675 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
12676 | opnd_value); | |
12677 | if (rc != 0) | |
12678 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
12679 | break; | |
12680 | ||
12681 | case O_constant: | |
12682 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12683 | break; | |
3b4dbbbf | 12684 | file_name = as_where (&line); |
43cd72b9 BW |
12685 | /* It is a constant and we called this function |
12686 | then we have to try to fit it. */ | |
12687 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 12688 | exp->X_add_number, file_name, line); |
e0001a05 NC |
12689 | break; |
12690 | ||
e0001a05 | 12691 | default: |
5b7c81bd | 12692 | has_fixup = true; |
e0001a05 NC |
12693 | break; |
12694 | } | |
12695 | } | |
43cd72b9 | 12696 | |
e0001a05 NC |
12697 | return has_fixup; |
12698 | } | |
12699 | ||
12700 | ||
b2d179be BW |
12701 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
12702 | into a multi-slot instruction, fill the other slots with NOPs. | |
12703 | Return TRUE if there is a symbol in the immediate field. See also the | |
12704 | assumptions listed for tinsn_to_slotbuf. */ | |
12705 | ||
5b7c81bd | 12706 | static bool |
b2d179be BW |
12707 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) |
12708 | { | |
12709 | static xtensa_insnbuf slotbuf = 0; | |
12710 | static vliw_insn vinsn; | |
12711 | xtensa_isa isa = xtensa_default_isa; | |
5b7c81bd | 12712 | bool has_fixup = false; |
b2d179be BW |
12713 | int i; |
12714 | ||
12715 | if (!slotbuf) | |
12716 | { | |
12717 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12718 | xg_init_vinsn (&vinsn); | |
12719 | } | |
12720 | ||
12721 | xg_clear_vinsn (&vinsn); | |
12722 | ||
12723 | bundle_tinsn (tinsn, &vinsn); | |
12724 | ||
12725 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
12726 | ||
12727 | for (i = 0; i < vinsn.num_slots; i++) | |
12728 | { | |
12729 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
12730 | has_fixup |= | |
12731 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
12732 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
12733 | } | |
12734 | ||
12735 | return has_fixup; | |
12736 | } | |
12737 | ||
12738 | ||
43cd72b9 | 12739 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 12740 | |
5b7c81bd | 12741 | static bool |
7fa3d080 | 12742 | tinsn_check_arguments (const TInsn *insn) |
e0001a05 NC |
12743 | { |
12744 | xtensa_isa isa = xtensa_default_isa; | |
12745 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
12746 | xtensa_regfile t1_regfile, t2_regfile; |
12747 | int t1_reg, t2_reg; | |
12748 | int t1_base_reg, t1_last_reg; | |
12749 | int t2_base_reg, t2_last_reg; | |
12750 | char t1_inout, t2_inout; | |
12751 | int i, j; | |
e0001a05 NC |
12752 | |
12753 | if (opcode == XTENSA_UNDEFINED) | |
12754 | { | |
12755 | as_bad (_("invalid opcode")); | |
5b7c81bd | 12756 | return true; |
e0001a05 NC |
12757 | } |
12758 | ||
43cd72b9 | 12759 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
12760 | { |
12761 | as_bad (_("too few operands")); | |
5b7c81bd | 12762 | return true; |
e0001a05 NC |
12763 | } |
12764 | ||
43cd72b9 | 12765 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
12766 | { |
12767 | as_bad (_("too many operands")); | |
5b7c81bd | 12768 | return true; |
e0001a05 | 12769 | } |
6dc6b655 BW |
12770 | |
12771 | /* Check registers. */ | |
12772 | for (j = 0; j < insn->ntok; j++) | |
12773 | { | |
12774 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
12775 | continue; | |
12776 | ||
12777 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
12778 | t2_base_reg = insn->tok[j].X_add_number; | |
12779 | t2_last_reg | |
12780 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
12781 | ||
12782 | for (i = 0; i < insn->ntok; i++) | |
12783 | { | |
12784 | if (i == j) | |
12785 | continue; | |
12786 | ||
12787 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
12788 | continue; | |
12789 | ||
12790 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
12791 | ||
12792 | if (t1_regfile != t2_regfile) | |
12793 | continue; | |
12794 | ||
12795 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
12796 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
12797 | ||
12798 | t1_base_reg = insn->tok[i].X_add_number; | |
12799 | t1_last_reg = (t1_base_reg | |
12800 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
12801 | ||
12802 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
12803 | { | |
12804 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
12805 | { | |
12806 | if (t1_reg != t2_reg) | |
12807 | continue; | |
12808 | ||
12809 | if (t1_inout != 'i' && t2_inout != 'i') | |
12810 | { | |
12811 | as_bad (_("multiple writes to the same register")); | |
5b7c81bd | 12812 | return true; |
6dc6b655 BW |
12813 | } |
12814 | } | |
12815 | } | |
12816 | } | |
12817 | } | |
5b7c81bd | 12818 | return false; |
e0001a05 NC |
12819 | } |
12820 | ||
12821 | ||
12822 | /* Load an instruction from its encoded form. */ | |
12823 | ||
12824 | static void | |
7fa3d080 | 12825 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 12826 | { |
43cd72b9 | 12827 | vliw_insn vinsn; |
e0001a05 | 12828 | |
43cd72b9 BW |
12829 | xg_init_vinsn (&vinsn); |
12830 | vinsn_from_chars (&vinsn, f); | |
12831 | ||
12832 | *tinsn = vinsn.slots[slot]; | |
12833 | xg_free_vinsn (&vinsn); | |
12834 | } | |
e0001a05 | 12835 | |
43cd72b9 BW |
12836 | |
12837 | static void | |
7fa3d080 BW |
12838 | tinsn_from_insnbuf (TInsn *tinsn, |
12839 | xtensa_insnbuf slotbuf, | |
12840 | xtensa_format fmt, | |
12841 | int slot) | |
43cd72b9 BW |
12842 | { |
12843 | int i; | |
12844 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
12845 | |
12846 | /* Find the immed. */ | |
43cd72b9 BW |
12847 | tinsn_init (tinsn); |
12848 | tinsn->insn_type = ITYPE_INSN; | |
5b7c81bd | 12849 | tinsn->is_specific_opcode = false; /* must not be specific */ |
43cd72b9 BW |
12850 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); |
12851 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
12852 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 12853 | { |
43cd72b9 BW |
12854 | set_expr_const (&tinsn->tok[i], |
12855 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
12856 | tinsn->opcode, i)); | |
e0001a05 NC |
12857 | } |
12858 | } | |
12859 | ||
12860 | ||
12861 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
12862 | ||
12863 | static void | |
7fa3d080 | 12864 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 12865 | { |
43cd72b9 | 12866 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
12867 | int opnum; |
12868 | ||
43cd72b9 | 12869 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
12870 | { |
12871 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 12872 | gas_assert (opnum >= 0); |
e7da6241 BW |
12873 | set_expr_symbol_offset (&tinsn->tok[opnum], |
12874 | fragP->tc_frag_data.slot_symbols[slot], | |
12875 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 12876 | } |
19e8f41a | 12877 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
12878 | } |
12879 | ||
12880 | ||
12881 | static int | |
7fa3d080 | 12882 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
12883 | { |
12884 | int i; | |
12885 | int text_bytes = 0; | |
12886 | ||
12887 | for (i = 0; i < istack->ninsn; i++) | |
12888 | { | |
43cd72b9 BW |
12889 | TInsn *tinsn = &istack->insn[i]; |
12890 | if (tinsn->insn_type == ITYPE_INSN) | |
12891 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
12892 | } |
12893 | return text_bytes; | |
12894 | } | |
12895 | ||
12896 | ||
12897 | static int | |
7fa3d080 | 12898 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
12899 | { |
12900 | int i; | |
12901 | int lit_bytes = 0; | |
12902 | ||
12903 | for (i = 0; i < istack->ninsn; i++) | |
12904 | { | |
43cd72b9 BW |
12905 | TInsn *tinsn = &istack->insn[i]; |
12906 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
12907 | lit_bytes += 4; |
12908 | } | |
12909 | return lit_bytes; | |
12910 | } | |
12911 | ||
43cd72b9 BW |
12912 | \f |
12913 | /* vliw_insn functions. */ | |
12914 | ||
7fa3d080 BW |
12915 | static void |
12916 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12917 | { |
12918 | int i; | |
12919 | xtensa_isa isa = xtensa_default_isa; | |
12920 | ||
12921 | xg_clear_vinsn (v); | |
12922 | ||
12923 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
12924 | if (v->insnbuf == NULL) | |
12925 | as_fatal (_("out of memory")); | |
12926 | ||
62af60e2 | 12927 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 12928 | { |
43cd72b9 BW |
12929 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
12930 | if (v->slotbuf[i] == NULL) | |
12931 | as_fatal (_("out of memory")); | |
12932 | } | |
12933 | } | |
12934 | ||
12935 | ||
7fa3d080 BW |
12936 | static void |
12937 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12938 | { |
12939 | int i; | |
65738a7d | 12940 | |
3739860c | 12941 | memset (v, 0, offsetof (vliw_insn, slots) |
62af60e2 | 12942 | + sizeof(TInsn) * config_max_slots); |
65738a7d | 12943 | |
43cd72b9 BW |
12944 | v->format = XTENSA_UNDEFINED; |
12945 | v->num_slots = 0; | |
5b7c81bd | 12946 | v->inside_bundle = false; |
43cd72b9 BW |
12947 | |
12948 | if (xt_saved_debug_type != DEBUG_NONE) | |
12949 | debug_type = xt_saved_debug_type; | |
12950 | ||
62af60e2 | 12951 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 12952 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
12953 | } |
12954 | ||
12955 | ||
d8392fd9 SA |
12956 | static void |
12957 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
12958 | { | |
3739860c | 12959 | memcpy (dst, src, |
d8392fd9 SA |
12960 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); |
12961 | dst->insnbuf = src->insnbuf; | |
12962 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
12963 | } | |
12964 | ||
12965 | ||
5b7c81bd | 12966 | static bool |
7fa3d080 | 12967 | vinsn_has_specific_opcodes (vliw_insn *v) |
43cd72b9 BW |
12968 | { |
12969 | int i; | |
c138bc38 | 12970 | |
43cd72b9 BW |
12971 | for (i = 0; i < v->num_slots; i++) |
12972 | { | |
12973 | if (v->slots[i].is_specific_opcode) | |
5b7c81bd | 12974 | return true; |
43cd72b9 | 12975 | } |
5b7c81bd | 12976 | return false; |
43cd72b9 BW |
12977 | } |
12978 | ||
12979 | ||
7fa3d080 BW |
12980 | static void |
12981 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12982 | { |
12983 | int i; | |
12984 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 12985 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
12986 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
12987 | } | |
12988 | ||
12989 | ||
e7da6241 BW |
12990 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
12991 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 | 12992 | |
5b7c81bd | 12993 | static bool |
7fa3d080 BW |
12994 | vinsn_to_insnbuf (vliw_insn *vinsn, |
12995 | char *frag_offset, | |
12996 | fragS *fragP, | |
5b7c81bd | 12997 | bool record_fixup) |
43cd72b9 BW |
12998 | { |
12999 | xtensa_isa isa = xtensa_default_isa; | |
13000 | xtensa_format fmt = vinsn->format; | |
13001 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
13002 | int slot; | |
5b7c81bd | 13003 | bool has_fixup = false; |
43cd72b9 BW |
13004 | |
13005 | xtensa_format_encode (isa, fmt, insnbuf); | |
13006 | ||
13007 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
13008 | { | |
13009 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 13010 | expressionS *extra_arg = &tinsn->extra_arg; |
5b7c81bd | 13011 | bool tinsn_has_fixup = |
43cd72b9 BW |
13012 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, |
13013 | vinsn->slotbuf[slot]); | |
13014 | ||
13015 | xtensa_format_set_slot (isa, fmt, slot, | |
13016 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 13017 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
13018 | { |
13019 | if (vinsn->num_slots != 1) | |
13020 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
13021 | else if (record_fixup) | |
13022 | /* Instructions that generate TLS relocations should always be | |
13023 | relaxed in the front-end. If "record_fixup" is set, then this | |
13024 | function is being called during back-end relaxation, so flag | |
13025 | the unexpected behavior as an error. */ | |
13026 | as_bad (_("unexpected TLS relocation")); | |
13027 | else | |
13028 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
13029 | xtensa_format_length (isa, fmt), | |
19e8f41a | 13030 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
5b7c81bd | 13031 | false, map_operator_to_reloc (extra_arg->X_op, false)); |
28dbbc02 | 13032 | } |
e7da6241 | 13033 | if (tinsn_has_fixup) |
43cd72b9 BW |
13034 | { |
13035 | int i; | |
13036 | xtensa_opcode opcode = tinsn->opcode; | |
13037 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
5b7c81bd | 13038 | has_fixup = true; |
43cd72b9 BW |
13039 | |
13040 | for (i = 0; i < noperands; i++) | |
13041 | { | |
91d6fa6a NC |
13042 | expressionS* exp = &tinsn->tok[i]; |
13043 | switch (exp->X_op) | |
43cd72b9 BW |
13044 | { |
13045 | case O_symbol: | |
13046 | case O_lo16: | |
13047 | case O_hi16: | |
13048 | if (get_relaxable_immed (opcode) == i) | |
13049 | { | |
e7da6241 BW |
13050 | /* Add a fix record for the instruction, except if this |
13051 | function is being called prior to relaxation, i.e., | |
13052 | if record_fixup is false, and the instruction might | |
13053 | be relaxed later. */ | |
13054 | if (record_fixup | |
13055 | || tinsn->is_specific_opcode | |
13056 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 13057 | { |
91d6fa6a | 13058 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 13059 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
13060 | } |
13061 | else | |
13062 | { | |
91d6fa6a | 13063 | if (exp->X_op != O_symbol) |
e7da6241 | 13064 | as_bad (_("invalid operand")); |
91d6fa6a NC |
13065 | tinsn->symbol = exp->X_add_symbol; |
13066 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
13067 | } |
13068 | } | |
13069 | else | |
e7da6241 | 13070 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
13071 | break; |
13072 | ||
13073 | case O_constant: | |
13074 | case O_register: | |
13075 | break; | |
13076 | ||
43cd72b9 | 13077 | default: |
e7da6241 | 13078 | as_bad (_("expression too complex")); |
43cd72b9 BW |
13079 | break; |
13080 | } | |
13081 | } | |
13082 | } | |
13083 | } | |
13084 | ||
13085 | return has_fixup; | |
13086 | } | |
13087 | ||
13088 | ||
13089 | static void | |
7fa3d080 | 13090 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
13091 | { |
13092 | static xtensa_insnbuf insnbuf = NULL; | |
13093 | static xtensa_insnbuf slotbuf = NULL; | |
13094 | int i; | |
13095 | xtensa_format fmt; | |
13096 | xtensa_isa isa = xtensa_default_isa; | |
13097 | ||
13098 | if (!insnbuf) | |
13099 | { | |
13100 | insnbuf = xtensa_insnbuf_alloc (isa); | |
13101 | slotbuf = xtensa_insnbuf_alloc (isa); | |
13102 | } | |
13103 | ||
d77b99c9 | 13104 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
13105 | fmt = xtensa_format_decode (isa, insnbuf); |
13106 | if (fmt == XTENSA_UNDEFINED) | |
13107 | as_fatal (_("cannot decode instruction format")); | |
13108 | vinsn->format = fmt; | |
13109 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
13110 | ||
13111 | for (i = 0; i < vinsn->num_slots; i++) | |
13112 | { | |
13113 | TInsn *tinsn = &vinsn->slots[i]; | |
13114 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
13115 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
13116 | } | |
13117 | } | |
13118 | ||
e0001a05 NC |
13119 | \f |
13120 | /* Expression utilities. */ | |
13121 | ||
43cd72b9 | 13122 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 | 13123 | |
5b7c81bd | 13124 | bool |
7fa3d080 | 13125 | expr_is_const (const expressionS *s) |
e0001a05 NC |
13126 | { |
13127 | return (s->X_op == O_constant); | |
13128 | } | |
13129 | ||
13130 | ||
13131 | /* Get the expression constant. | |
43cd72b9 | 13132 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
13133 | |
13134 | offsetT | |
7fa3d080 | 13135 | get_expr_const (const expressionS *s) |
e0001a05 | 13136 | { |
9c2799c2 | 13137 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
13138 | return s->X_add_number; |
13139 | } | |
13140 | ||
13141 | ||
13142 | /* Set the expression to a constant value. */ | |
13143 | ||
13144 | void | |
7fa3d080 | 13145 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
13146 | { |
13147 | s->X_op = O_constant; | |
13148 | s->X_add_number = val; | |
13149 | s->X_add_symbol = NULL; | |
13150 | s->X_op_symbol = NULL; | |
13151 | } | |
13152 | ||
13153 | ||
5b7c81bd | 13154 | bool |
7fa3d080 | 13155 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
13156 | { |
13157 | return (s->X_op == O_register); | |
13158 | } | |
13159 | ||
13160 | ||
13161 | /* Get the expression constant. | |
13162 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
13163 | ||
13164 | offsetT | |
7fa3d080 | 13165 | get_expr_register (const expressionS *s) |
43cd72b9 | 13166 | { |
9c2799c2 | 13167 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
13168 | return s->X_add_number; |
13169 | } | |
13170 | ||
13171 | ||
e0001a05 NC |
13172 | /* Set the expression to a symbol + constant offset. */ |
13173 | ||
13174 | void | |
7fa3d080 | 13175 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
13176 | { |
13177 | s->X_op = O_symbol; | |
13178 | s->X_add_symbol = sym; | |
13179 | s->X_op_symbol = NULL; /* unused */ | |
13180 | s->X_add_number = offset; | |
13181 | } | |
13182 | ||
13183 | ||
43cd72b9 BW |
13184 | /* Return TRUE if the two expressions are equal. */ |
13185 | ||
5b7c81bd | 13186 | bool |
7fa3d080 | 13187 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
13188 | { |
13189 | if (s1->X_op != s2->X_op) | |
5b7c81bd | 13190 | return false; |
e0001a05 | 13191 | if (s1->X_add_symbol != s2->X_add_symbol) |
5b7c81bd | 13192 | return false; |
e0001a05 | 13193 | if (s1->X_op_symbol != s2->X_op_symbol) |
5b7c81bd | 13194 | return false; |
e0001a05 | 13195 | if (s1->X_add_number != s2->X_add_number) |
5b7c81bd AM |
13196 | return false; |
13197 | return true; | |
e0001a05 NC |
13198 | } |
13199 | ||
13200 | ||
13201 | static void | |
7fa3d080 | 13202 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
13203 | { |
13204 | memcpy (dst, src, sizeof (expressionS)); | |
13205 | } | |
13206 | ||
13207 | \f | |
9456465c | 13208 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
13209 | |
13210 | struct rename_section_struct | |
13211 | { | |
e4a0c708 | 13212 | const char *old_name; |
e0001a05 NC |
13213 | char *new_name; |
13214 | struct rename_section_struct *next; | |
13215 | }; | |
13216 | ||
13217 | static struct rename_section_struct *section_rename; | |
13218 | ||
13219 | ||
9456465c BW |
13220 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
13221 | entries to the section_rename list. Note: Specifying multiple | |
13222 | renamings separated by colons is not documented and is retained only | |
13223 | for backward compatibility. */ | |
e0001a05 | 13224 | |
7fa3d080 BW |
13225 | static void |
13226 | build_section_rename (const char *arg) | |
e0001a05 | 13227 | { |
9456465c | 13228 | struct rename_section_struct *r; |
e0001a05 NC |
13229 | char *this_arg = NULL; |
13230 | char *next_arg = NULL; | |
13231 | ||
9456465c | 13232 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 13233 | { |
9456465c BW |
13234 | char *old_name, *new_name; |
13235 | ||
e0001a05 NC |
13236 | if (this_arg) |
13237 | { | |
13238 | next_arg = strchr (this_arg, ':'); | |
13239 | if (next_arg) | |
13240 | { | |
13241 | *next_arg = '\0'; | |
13242 | next_arg++; | |
13243 | } | |
13244 | } | |
e0001a05 | 13245 | |
9456465c BW |
13246 | old_name = this_arg; |
13247 | new_name = strchr (this_arg, '='); | |
e0001a05 | 13248 | |
9456465c BW |
13249 | if (*old_name == '\0') |
13250 | { | |
13251 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
13252 | continue; | |
13253 | } | |
13254 | if (!new_name || new_name[1] == '\0') | |
13255 | { | |
13256 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
13257 | old_name); | |
13258 | continue; | |
13259 | } | |
13260 | *new_name = '\0'; | |
13261 | new_name++; | |
e0001a05 | 13262 | |
9456465c BW |
13263 | /* Check for invalid section renaming. */ |
13264 | for (r = section_rename; r != NULL; r = r->next) | |
13265 | { | |
13266 | if (strcmp (r->old_name, old_name) == 0) | |
13267 | as_bad (_("section %s renamed multiple times"), old_name); | |
13268 | if (strcmp (r->new_name, new_name) == 0) | |
13269 | as_bad (_("multiple sections remapped to output section %s"), | |
13270 | new_name); | |
13271 | } | |
e0001a05 | 13272 | |
9456465c | 13273 | /* Now add it. */ |
325801bd | 13274 | r = XNEW (struct rename_section_struct); |
9456465c BW |
13275 | r->old_name = xstrdup (old_name); |
13276 | r->new_name = xstrdup (new_name); | |
13277 | r->next = section_rename; | |
13278 | section_rename = r; | |
e0001a05 | 13279 | } |
e0001a05 NC |
13280 | } |
13281 | ||
13282 | ||
9456465c | 13283 | char * |
e4a0c708 | 13284 | xtensa_section_rename (const char *name) |
e0001a05 NC |
13285 | { |
13286 | struct rename_section_struct *r = section_rename; | |
13287 | ||
13288 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
13289 | { |
13290 | if (strcmp (r->old_name, name) == 0) | |
13291 | return r->new_name; | |
13292 | } | |
e0001a05 | 13293 | |
e4a0c708 | 13294 | return (char *) name; |
e0001a05 | 13295 | } |