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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
2571583a | 2 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
e0001a05 | 21 | #include "as.h" |
df7b86aa | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "sb.h" |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
b0b79343 | 32 | #include "elf/xtensa.h" |
e0001a05 | 33 | |
2caa7ca0 BW |
34 | /* Provide default values for new configuration settings. */ |
35 | #ifndef XSHAL_ABI | |
36 | #define XSHAL_ABI 0 | |
37 | #endif | |
38 | ||
e0001a05 NC |
39 | #ifndef uint32 |
40 | #define uint32 unsigned int | |
41 | #endif | |
42 | #ifndef int32 | |
43 | #define int32 signed int | |
44 | #endif | |
45 | ||
46 | /* Notes: | |
47 | ||
e0001a05 NC |
48 | Naming conventions (used somewhat inconsistently): |
49 | The xtensa_ functions are exported | |
50 | The xg_ functions are internal | |
51 | ||
52 | We also have a couple of different extensibility mechanisms. | |
53 | 1) The idiom replacement: | |
54 | This is used when a line is first parsed to | |
55 | replace an instruction pattern with another instruction | |
56 | It is currently limited to replacements of instructions | |
57 | with constant operands. | |
58 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
59 | replacement patterns. When an instruction's immediate field | |
60 | does not fit the next instruction sequence is attempted. | |
61 | In addition, "narrow" opcodes are supported this way. */ | |
62 | ||
63 | ||
64 | /* Define characters with special meanings to GAS. */ | |
65 | const char comment_chars[] = "#"; | |
66 | const char line_comment_chars[] = "#"; | |
67 | const char line_separator_chars[] = ";"; | |
68 | const char EXP_CHARS[] = "eE"; | |
69 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
70 | ||
71 | ||
43cd72b9 BW |
72 | /* Flags to indicate whether the hardware supports the density and |
73 | absolute literals options. */ | |
e0001a05 | 74 | |
f7e16c2a MF |
75 | bfd_boolean density_supported; |
76 | bfd_boolean absolute_literals_supported; | |
43cd72b9 | 77 | |
43cd72b9 BW |
78 | static vliw_insn cur_vinsn; |
79 | ||
77cba8a3 | 80 | unsigned xtensa_num_pipe_stages; |
f7e16c2a | 81 | unsigned xtensa_fetch_width; |
43cd72b9 BW |
82 | |
83 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
84 | ||
85 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 86 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
87 | back end. */ |
88 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
89 | |
90 | /* Flags for properties of the last instruction in a segment. */ | |
91 | #define FLAG_IS_A0_WRITER 0x1 | |
92 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
93 | ||
94 | ||
95 | /* We define a special segment names ".literal" to place literals | |
96 | into. The .fini and .init sections are special because they | |
97 | contain code that is moved together by the linker. We give them | |
98 | their own special .fini.literal and .init.literal sections. */ | |
99 | ||
100 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 101 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 102 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 103 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
104 | |
105 | ||
43cd72b9 | 106 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
107 | state of the literal collection pools. If lit_prefix is set, it is |
108 | used to determine the literal section names; otherwise, the literal | |
109 | sections are determined based on the current text section. The | |
110 | lit_seg and lit4_seg fields cache these literal sections, with the | |
111 | current_text_seg field used a tag to indicate whether the cached | |
112 | values are valid. */ | |
e0001a05 NC |
113 | |
114 | typedef struct lit_state_struct | |
115 | { | |
74869ac7 BW |
116 | char *lit_prefix; |
117 | segT current_text_seg; | |
e0001a05 | 118 | segT lit_seg; |
43cd72b9 | 119 | segT lit4_seg; |
e0001a05 NC |
120 | } lit_state; |
121 | ||
122 | static lit_state default_lit_sections; | |
123 | ||
124 | ||
74869ac7 BW |
125 | /* We keep a list of literal segments. The seg_list type is the node |
126 | for this list. The literal_head pointer is the head of the list, | |
127 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
128 | |
129 | typedef struct seg_list_struct | |
130 | { | |
131 | struct seg_list_struct *next; | |
132 | segT seg; | |
133 | } seg_list; | |
134 | ||
135 | static seg_list literal_head_h; | |
136 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
137 | |
138 | ||
82e7541d BW |
139 | /* Lists of symbols. We keep a list of symbols that label the current |
140 | instruction, so that we can adjust the symbols when inserting alignment | |
141 | for various instructions. We also keep a list of all the symbols on | |
142 | literals, so that we can fix up those symbols when the literals are | |
143 | later moved into the text sections. */ | |
144 | ||
145 | typedef struct sym_list_struct | |
146 | { | |
147 | struct sym_list_struct *next; | |
148 | symbolS *sym; | |
149 | } sym_list; | |
150 | ||
151 | static sym_list *insn_labels = NULL; | |
152 | static sym_list *free_insn_labels = NULL; | |
153 | static sym_list *saved_insn_labels = NULL; | |
154 | ||
155 | static sym_list *literal_syms; | |
156 | ||
157 | ||
43cd72b9 BW |
158 | /* Flags to determine whether to prefer const16 or l32r |
159 | if both options are available. */ | |
160 | int prefer_const16 = 0; | |
161 | int prefer_l32r = 0; | |
162 | ||
e0001a05 NC |
163 | /* Global flag to indicate when we are emitting literals. */ |
164 | int generating_literals = 0; | |
165 | ||
43cd72b9 BW |
166 | /* The following PROPERTY table definitions are copied from |
167 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
168 | ||
169 | /* Flags in the property tables to specify whether blocks of memory | |
170 | are literals, instructions, data, or unreachable. For | |
171 | instructions, blocks that begin loop targets and branch targets are | |
172 | designated. Blocks that do not allow density, instruction | |
173 | reordering or transformation are also specified. Finally, for | |
174 | branch targets, branch target alignment priority is included. | |
175 | Alignment of the next block is specified in the current block | |
176 | and the size of the current block does not include any fill required | |
177 | to align to the next block. */ | |
178 | ||
179 | #define XTENSA_PROP_LITERAL 0x00000001 | |
180 | #define XTENSA_PROP_INSN 0x00000002 | |
181 | #define XTENSA_PROP_DATA 0x00000004 | |
182 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
183 | /* Instruction only properties at beginning of code. */ | |
184 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
185 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
186 | /* Instruction only properties about code. */ | |
187 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
188 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
189 | /* Historically, NO_TRANSFORM was a property of instructions, |
190 | but it should apply to literals under certain circumstances. */ | |
191 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
192 | |
193 | /* Branch target alignment information. This transmits information | |
194 | to the linker optimization about the priority of aligning a | |
195 | particular block for branch target alignment: None, low priority, | |
196 | high priority, or required. These only need to be checked in | |
197 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
198 | Common usage is | |
199 | ||
200 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
201 | case XTENSA_PROP_BT_ALIGN_NONE: | |
202 | case XTENSA_PROP_BT_ALIGN_LOW: | |
203 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
204 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
205 | */ | |
206 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
207 | ||
208 | /* No branch target alignment. */ | |
209 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
210 | /* Low priority branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
212 | /* High priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
214 | /* Required branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
216 | ||
43cd72b9 BW |
217 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ |
218 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
219 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
220 | ||
221 | ||
222 | /* Alignment is specified in the block BEFORE the one that needs | |
223 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
224 | get the required alignment specified as a power of 2. Use | |
225 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
226 | alignment. Be careful of side effects since the SET will evaluate | |
227 | flags twice. Also, note that the SIZE of a block in the property | |
228 | table does not include the alignment size, so the alignment fill | |
229 | must be calculated to determine if two blocks are contiguous. | |
230 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
231 | possible future implementation. */ | |
232 | ||
233 | #define XTENSA_PROP_ALIGN 0x00000800 | |
234 | ||
235 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
236 | ||
43cd72b9 BW |
237 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ |
238 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
239 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
240 | ||
241 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
242 | ||
243 | ||
244 | /* Structure for saving instruction and alignment per-fragment data | |
245 | that will be written to the object file. This structure is | |
246 | equivalent to the actual data that will be written out to the file | |
247 | but is easier to use. We provide a conversion to file flags | |
248 | in frag_flags_to_number. */ | |
249 | ||
250 | typedef struct frag_flags_struct frag_flags; | |
251 | ||
252 | struct frag_flags_struct | |
253 | { | |
254 | /* is_literal should only be used after xtensa_move_literals. | |
255 | If you need to check if you are generating a literal fragment, | |
256 | then use the generating_literals global. */ | |
257 | ||
258 | unsigned is_literal : 1; | |
259 | unsigned is_insn : 1; | |
260 | unsigned is_data : 1; | |
261 | unsigned is_unreachable : 1; | |
262 | ||
99ded152 BW |
263 | /* is_specific_opcode implies no_transform. */ |
264 | unsigned is_no_transform : 1; | |
265 | ||
43cd72b9 BW |
266 | struct |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
274 | |
275 | unsigned is_no_reorder : 1; | |
276 | ||
277 | /* Uses absolute literal addressing for l32r. */ | |
278 | unsigned is_abslit : 1; | |
279 | } insn; | |
280 | unsigned is_align : 1; | |
281 | unsigned alignment : 5; | |
282 | }; | |
283 | ||
284 | ||
285 | /* Structure for saving information about a block of property data | |
286 | for frags that have the same flags. */ | |
287 | struct xtensa_block_info_struct | |
288 | { | |
289 | segT sec; | |
290 | bfd_vma offset; | |
291 | size_t size; | |
292 | frag_flags flags; | |
293 | struct xtensa_block_info_struct *next; | |
294 | }; | |
295 | ||
e0001a05 NC |
296 | |
297 | /* Structure for saving the current state before emitting literals. */ | |
298 | typedef struct emit_state_struct | |
299 | { | |
300 | const char *name; | |
301 | segT now_seg; | |
302 | subsegT now_subseg; | |
303 | int generating_literals; | |
304 | } emit_state; | |
305 | ||
306 | ||
43cd72b9 BW |
307 | /* Opcode placement information */ |
308 | ||
309 | typedef unsigned long long bitfield; | |
310 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
311 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
312 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
313 | ||
314 | #define MAX_FORMATS 32 | |
315 | ||
316 | typedef struct op_placement_info_struct | |
317 | { | |
318 | int num_formats; | |
319 | /* A number describing how restrictive the issue is for this | |
320 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 321 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 322 | only one format but many slots in that format. The most |
c138bc38 | 323 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
324 | format. */ |
325 | int issuef; | |
43cd72b9 | 326 | xtensa_format narrowest; |
43cd72b9 | 327 | char narrowest_size; |
b2d179be | 328 | char narrowest_slot; |
43cd72b9 BW |
329 | |
330 | /* formats is a bitfield with the Nth bit set | |
331 | if the opcode fits in the Nth xtensa_format. */ | |
332 | bitfield formats; | |
333 | ||
334 | /* slots[N]'s Mth bit is set if the op fits in the | |
335 | Mth slot of the Nth xtensa_format. */ | |
336 | bitfield slots[MAX_FORMATS]; | |
337 | ||
338 | /* A count of the number of slots in a given format | |
339 | an op can fit (i.e., the bitcount of the slot field above). */ | |
340 | char slots_in_format[MAX_FORMATS]; | |
341 | ||
342 | } op_placement_info, *op_placement_info_table; | |
343 | ||
344 | op_placement_info_table op_placement_table; | |
345 | ||
346 | ||
347 | /* Extra expression types. */ | |
348 | ||
349 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
350 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
351 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 352 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
353 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
354 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
355 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
356 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
357 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 358 | |
bbdd25a8 BW |
359 | struct suffix_reloc_map |
360 | { | |
b9bb4a93 | 361 | const char *suffix; |
bbdd25a8 BW |
362 | int length; |
363 | bfd_reloc_code_real_type reloc; | |
cc34adb2 | 364 | operatorT operator; |
bbdd25a8 BW |
365 | }; |
366 | ||
367 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
368 | ||
369 | static struct suffix_reloc_map suffix_relocs[] = | |
370 | { | |
371 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
372 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
373 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 374 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
375 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
376 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
377 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
378 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
379 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
380 | }; |
381 | ||
43cd72b9 | 382 | |
e0001a05 NC |
383 | /* Directives. */ |
384 | ||
385 | typedef enum | |
386 | { | |
387 | directive_none = 0, | |
388 | directive_literal, | |
389 | directive_density, | |
43cd72b9 | 390 | directive_transform, |
e0001a05 NC |
391 | directive_freeregs, |
392 | directive_longcalls, | |
43cd72b9 BW |
393 | directive_literal_prefix, |
394 | directive_schedule, | |
395 | directive_absolute_literals, | |
396 | directive_last_directive | |
e0001a05 NC |
397 | } directiveE; |
398 | ||
399 | typedef struct | |
400 | { | |
401 | const char *name; | |
402 | bfd_boolean can_be_negated; | |
403 | } directive_infoS; | |
404 | ||
405 | const directive_infoS directive_info[] = | |
406 | { | |
43cd72b9 BW |
407 | { "none", FALSE }, |
408 | { "literal", FALSE }, | |
409 | { "density", TRUE }, | |
410 | { "transform", TRUE }, | |
411 | { "freeregs", FALSE }, | |
412 | { "longcalls", TRUE }, | |
413 | { "literal_prefix", FALSE }, | |
414 | { "schedule", TRUE }, | |
415 | { "absolute-literals", TRUE } | |
e0001a05 NC |
416 | }; |
417 | ||
418 | bfd_boolean directive_state[] = | |
419 | { | |
420 | FALSE, /* none */ | |
421 | FALSE, /* literal */ | |
e0001a05 | 422 | FALSE, /* density */ |
43cd72b9 | 423 | TRUE, /* transform */ |
e0001a05 NC |
424 | FALSE, /* freeregs */ |
425 | FALSE, /* longcalls */ | |
43cd72b9 | 426 | FALSE, /* literal_prefix */ |
2caa7ca0 | 427 | FALSE, /* schedule */ |
43cd72b9 | 428 | FALSE /* absolute_literals */ |
e0001a05 NC |
429 | }; |
430 | ||
b46824bd MF |
431 | /* A circular list of all potential and actual literal pool locations |
432 | in a segment. */ | |
433 | struct litpool_frag | |
434 | { | |
435 | struct litpool_frag *next; | |
436 | struct litpool_frag *prev; | |
437 | fragS *fragP; | |
438 | addressT addr; | |
439 | short priority; /* 1, 2, or 3 -- 1 is highest */ | |
440 | short original_priority; | |
441 | }; | |
442 | ||
443 | /* Map a segment to its litpool_frag list. */ | |
444 | struct litpool_seg | |
445 | { | |
446 | struct litpool_seg *next; | |
447 | asection *seg; | |
448 | struct litpool_frag frag_list; | |
449 | int frag_count; /* since last litpool location */ | |
450 | }; | |
451 | ||
452 | static struct litpool_seg litpool_seg_list; | |
453 | ||
e0001a05 NC |
454 | |
455 | /* Directive functions. */ | |
456 | ||
7fa3d080 BW |
457 | static void xtensa_begin_directive (int); |
458 | static void xtensa_end_directive (int); | |
74869ac7 | 459 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
460 | static void xtensa_literal_position (int); |
461 | static void xtensa_literal_pseudo (int); | |
462 | static void xtensa_frequency_pseudo (int); | |
463 | static void xtensa_elf_cons (int); | |
fb227da0 | 464 | static void xtensa_leb128 (int); |
e0001a05 | 465 | |
7fa3d080 | 466 | /* Parsing and Idiom Translation. */ |
e0001a05 | 467 | |
7fa3d080 | 468 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 469 | |
e0001a05 NC |
470 | /* Various Other Internal Functions. */ |
471 | ||
84b08ed9 BW |
472 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
473 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
474 | static void xtensa_mark_literal_pool_location (void); |
475 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
476 | static fragS *get_literal_pool_location (segT); | |
477 | static void set_literal_pool_location (segT, fragS *); | |
478 | static void xtensa_set_frag_assembly_state (fragS *); | |
479 | static void finish_vinsn (vliw_insn *); | |
480 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 481 | static int total_frag_text_expansion (fragS *); |
a82c7d90 DW |
482 | static bfd_boolean use_trampolines = TRUE; |
483 | static void xtensa_check_frag_count (void); | |
484 | static void xtensa_create_trampoline_frag (bfd_boolean); | |
485 | static void xtensa_maybe_create_trampoline_frag (void); | |
486 | struct trampoline_frag; | |
487 | static int init_trampoline_frag (struct trampoline_frag *); | |
fec68fb1 MF |
488 | static fixS *xg_append_jump (fragS *fragP, fixS *jump_around, |
489 | symbolS *sym, offsetT offset); | |
b46824bd MF |
490 | static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean); |
491 | static bfd_boolean auto_litpools = FALSE; | |
492 | static int auto_litpool_limit = 10000; | |
e0001a05 NC |
493 | |
494 | /* Alignment Functions. */ | |
495 | ||
d77b99c9 BW |
496 | static int get_text_align_power (unsigned); |
497 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 498 | static int branch_align_power (segT); |
e0001a05 NC |
499 | |
500 | /* Helpers for xtensa_relax_frag(). */ | |
501 | ||
7fa3d080 | 502 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 503 | |
b08b5071 | 504 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 505 | |
7fa3d080 BW |
506 | static unsigned get_last_insn_flags (segT, subsegT); |
507 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
508 | static float get_subseg_total_freq (segT, subsegT); |
509 | static float get_subseg_target_freq (segT, subsegT); | |
510 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
511 | |
512 | /* Segment list functions. */ | |
513 | ||
7fa3d080 BW |
514 | static void xtensa_move_literals (void); |
515 | static void xtensa_reorder_segments (void); | |
516 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
517 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
518 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
519 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 520 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 521 | |
43cd72b9 BW |
522 | /* op_placement_info functions. */ |
523 | ||
7fa3d080 BW |
524 | static void init_op_placement_info_table (void); |
525 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
526 | static int xg_get_single_size (xtensa_opcode); | |
527 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 528 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 529 | |
e0001a05 | 530 | /* TInsn and IStack functions. */ |
43cd72b9 | 531 | |
7fa3d080 BW |
532 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
533 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
534 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
535 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
536 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
537 | static void tinsn_from_chars (TInsn *, char *, int); | |
538 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
539 | static int get_num_stack_text_bytes (IStack *); | |
540 | static int get_num_stack_literal_bytes (IStack *); | |
a82c7d90 | 541 | static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); |
e0001a05 | 542 | |
43cd72b9 BW |
543 | /* vliw_insn functions. */ |
544 | ||
7fa3d080 | 545 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 546 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
547 | static void xg_clear_vinsn (vliw_insn *); |
548 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
549 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 550 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
551 | (vliw_insn *, char *, fragS *, bfd_boolean); |
552 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 553 | |
e0001a05 | 554 | /* Expression Utilities. */ |
43cd72b9 | 555 | |
7fa3d080 BW |
556 | bfd_boolean expr_is_const (const expressionS *); |
557 | offsetT get_expr_const (const expressionS *); | |
558 | void set_expr_const (expressionS *, offsetT); | |
559 | bfd_boolean expr_is_register (const expressionS *); | |
560 | offsetT get_expr_register (const expressionS *); | |
561 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
562 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
563 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 564 | |
9456465c BW |
565 | /* Section renaming. */ |
566 | ||
7fa3d080 | 567 | static void build_section_rename (const char *); |
e0001a05 | 568 | |
e0001a05 NC |
569 | |
570 | /* ISA imported from bfd. */ | |
571 | extern xtensa_isa xtensa_default_isa; | |
572 | ||
573 | extern int target_big_endian; | |
574 | ||
575 | static xtensa_opcode xtensa_addi_opcode; | |
576 | static xtensa_opcode xtensa_addmi_opcode; | |
577 | static xtensa_opcode xtensa_call0_opcode; | |
578 | static xtensa_opcode xtensa_call4_opcode; | |
579 | static xtensa_opcode xtensa_call8_opcode; | |
580 | static xtensa_opcode xtensa_call12_opcode; | |
581 | static xtensa_opcode xtensa_callx0_opcode; | |
582 | static xtensa_opcode xtensa_callx4_opcode; | |
583 | static xtensa_opcode xtensa_callx8_opcode; | |
584 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 585 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 586 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 587 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
588 | static xtensa_opcode xtensa_movi_opcode; |
589 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 590 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 591 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 592 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 593 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
594 | static xtensa_opcode xtensa_loop_opcode; |
595 | static xtensa_opcode xtensa_loopnez_opcode; | |
596 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 597 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
598 | static xtensa_opcode xtensa_nop_n_opcode; |
599 | static xtensa_opcode xtensa_or_opcode; | |
600 | static xtensa_opcode xtensa_ret_opcode; | |
601 | static xtensa_opcode xtensa_ret_n_opcode; | |
602 | static xtensa_opcode xtensa_retw_opcode; | |
603 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 604 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 605 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 606 | static int config_max_slots = 0; |
e0001a05 NC |
607 | |
608 | \f | |
609 | /* Command-line Options. */ | |
610 | ||
611 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 612 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 613 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 614 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 615 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
616 | static bfd_boolean workaround_a0_b_retw = FALSE; |
617 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
618 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 619 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 620 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 621 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 622 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 623 | |
43cd72b9 BW |
624 | /* When workaround_short_loops is TRUE, all loops with early exits must |
625 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
626 | to the workaround_short_loop flag. In addition to the | |
627 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
628 | must have at least 3 instructions. */ | |
e0001a05 | 629 | |
43cd72b9 | 630 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 631 | |
7fa3d080 BW |
632 | |
633 | static void | |
634 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
635 | { | |
636 | if (earliest > latest) | |
637 | as_fatal (_("illegal range of target hardware versions")); | |
638 | ||
639 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
640 | if (earliest < 105000 || latest < 105000) | |
641 | { | |
642 | workaround_a0_b_retw |= TRUE; | |
643 | workaround_b_j_loop_end |= TRUE; | |
644 | workaround_short_loop |= TRUE; | |
645 | workaround_close_loop_end |= TRUE; | |
646 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 647 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
648 | } |
649 | } | |
650 | ||
651 | ||
e0001a05 NC |
652 | enum |
653 | { | |
654 | option_density = OPTION_MD_BASE, | |
655 | option_no_density, | |
656 | ||
19fc3723 SA |
657 | option_flix, |
658 | option_no_generate_flix, | |
659 | option_no_flix, | |
660 | ||
e0001a05 NC |
661 | option_relax, |
662 | option_no_relax, | |
663 | ||
43cd72b9 BW |
664 | option_link_relax, |
665 | option_no_link_relax, | |
666 | ||
e0001a05 NC |
667 | option_generics, |
668 | option_no_generics, | |
669 | ||
43cd72b9 BW |
670 | option_transform, |
671 | option_no_transform, | |
672 | ||
e0001a05 NC |
673 | option_text_section_literals, |
674 | option_no_text_section_literals, | |
675 | ||
43cd72b9 BW |
676 | option_absolute_literals, |
677 | option_no_absolute_literals, | |
678 | ||
e0001a05 NC |
679 | option_align_targets, |
680 | option_no_align_targets, | |
681 | ||
43cd72b9 | 682 | option_warn_unaligned_targets, |
e0001a05 NC |
683 | |
684 | option_longcalls, | |
685 | option_no_longcalls, | |
686 | ||
687 | option_workaround_a0_b_retw, | |
688 | option_no_workaround_a0_b_retw, | |
689 | ||
690 | option_workaround_b_j_loop_end, | |
691 | option_no_workaround_b_j_loop_end, | |
692 | ||
693 | option_workaround_short_loop, | |
694 | option_no_workaround_short_loop, | |
695 | ||
696 | option_workaround_all_short_loops, | |
697 | option_no_workaround_all_short_loops, | |
698 | ||
699 | option_workaround_close_loop_end, | |
700 | option_no_workaround_close_loop_end, | |
701 | ||
702 | option_no_workarounds, | |
703 | ||
e0001a05 | 704 | option_rename_section_name, |
e0001a05 | 705 | |
43cd72b9 BW |
706 | option_prefer_l32r, |
707 | option_prefer_const16, | |
708 | ||
a82c7d90 DW |
709 | option_target_hardware, |
710 | ||
711 | option_trampolines, | |
712 | option_no_trampolines, | |
b46824bd MF |
713 | |
714 | option_auto_litpools, | |
715 | option_no_auto_litpools, | |
716 | option_auto_litpool_limit, | |
e0001a05 NC |
717 | }; |
718 | ||
719 | const char *md_shortopts = ""; | |
720 | ||
721 | struct option md_longopts[] = | |
722 | { | |
43cd72b9 BW |
723 | { "density", no_argument, NULL, option_density }, |
724 | { "no-density", no_argument, NULL, option_no_density }, | |
725 | ||
19fc3723 SA |
726 | { "flix", no_argument, NULL, option_flix }, |
727 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
728 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
729 | ||
43cd72b9 BW |
730 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
731 | to the "transform" option. */ | |
732 | { "relax", no_argument, NULL, option_relax }, | |
733 | { "no-relax", no_argument, NULL, option_no_relax }, | |
734 | { "generics", no_argument, NULL, option_generics }, | |
735 | { "no-generics", no_argument, NULL, option_no_generics }, | |
736 | ||
737 | { "transform", no_argument, NULL, option_transform }, | |
738 | { "no-transform", no_argument, NULL, option_no_transform }, | |
739 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
740 | { "no-text-section-literals", no_argument, NULL, | |
741 | option_no_text_section_literals }, | |
742 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
743 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
744 | /* This option was changed from -align-target to -target-align |
745 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 746 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
747 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
748 | { "warn-unaligned-targets", no_argument, NULL, | |
749 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
750 | { "longcalls", no_argument, NULL, option_longcalls }, |
751 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
752 | ||
753 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
754 | option_no_workaround_a0_b_retw }, | |
755 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 756 | |
43cd72b9 BW |
757 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
758 | option_no_workaround_b_j_loop_end }, | |
759 | { "workaround-b-j-loop-end", no_argument, NULL, | |
760 | option_workaround_b_j_loop_end }, | |
e0001a05 | 761 | |
43cd72b9 BW |
762 | { "no-workaround-short-loops", no_argument, NULL, |
763 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
764 | { "workaround-short-loops", no_argument, NULL, |
765 | option_workaround_short_loop }, | |
e0001a05 | 766 | |
43cd72b9 BW |
767 | { "no-workaround-all-short-loops", no_argument, NULL, |
768 | option_no_workaround_all_short_loops }, | |
769 | { "workaround-all-short-loop", no_argument, NULL, | |
770 | option_workaround_all_short_loops }, | |
771 | ||
772 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
773 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
774 | ||
775 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
776 | ||
777 | { "no-workaround-close-loop-end", no_argument, NULL, | |
778 | option_no_workaround_close_loop_end }, | |
779 | { "workaround-close-loop-end", no_argument, NULL, | |
780 | option_workaround_close_loop_end }, | |
e0001a05 | 781 | |
7fa3d080 | 782 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 783 | |
43cd72b9 BW |
784 | { "link-relax", no_argument, NULL, option_link_relax }, |
785 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
786 | ||
787 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
788 | ||
a82c7d90 DW |
789 | { "trampolines", no_argument, NULL, option_trampolines }, |
790 | { "no-trampolines", no_argument, NULL, option_no_trampolines }, | |
791 | ||
b46824bd MF |
792 | { "auto-litpools", no_argument, NULL, option_auto_litpools }, |
793 | { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, | |
794 | { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, | |
795 | ||
43cd72b9 | 796 | { NULL, no_argument, NULL, 0 } |
e0001a05 NC |
797 | }; |
798 | ||
799 | size_t md_longopts_size = sizeof md_longopts; | |
800 | ||
801 | ||
802 | int | |
17b9d67d | 803 | md_parse_option (int c, const char *arg) |
e0001a05 NC |
804 | { |
805 | switch (c) | |
806 | { | |
807 | case option_density: | |
43cd72b9 | 808 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
809 | return 1; |
810 | case option_no_density: | |
43cd72b9 | 811 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 812 | return 1; |
43cd72b9 BW |
813 | case option_link_relax: |
814 | linkrelax = 1; | |
e0001a05 | 815 | return 1; |
43cd72b9 BW |
816 | case option_no_link_relax: |
817 | linkrelax = 0; | |
e0001a05 | 818 | return 1; |
19fc3723 SA |
819 | case option_flix: |
820 | produce_flix = FLIX_ALL; | |
821 | return 1; | |
822 | case option_no_generate_flix: | |
823 | produce_flix = FLIX_NO_GENERATE; | |
824 | return 1; | |
825 | case option_no_flix: | |
826 | produce_flix = FLIX_NONE; | |
827 | return 1; | |
43cd72b9 BW |
828 | case option_generics: |
829 | as_warn (_("--generics is deprecated; use --transform instead")); | |
830 | return md_parse_option (option_transform, arg); | |
831 | case option_no_generics: | |
832 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
833 | return md_parse_option (option_no_transform, arg); | |
834 | case option_relax: | |
835 | as_warn (_("--relax is deprecated; use --transform instead")); | |
836 | return md_parse_option (option_transform, arg); | |
837 | case option_no_relax: | |
838 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
839 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
840 | case option_longcalls: |
841 | directive_state[directive_longcalls] = TRUE; | |
842 | return 1; | |
843 | case option_no_longcalls: | |
844 | directive_state[directive_longcalls] = FALSE; | |
845 | return 1; | |
846 | case option_text_section_literals: | |
847 | use_literal_section = FALSE; | |
848 | return 1; | |
849 | case option_no_text_section_literals: | |
850 | use_literal_section = TRUE; | |
851 | return 1; | |
43cd72b9 BW |
852 | case option_absolute_literals: |
853 | if (!absolute_literals_supported) | |
854 | { | |
855 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
856 | return 0; | |
857 | } | |
858 | directive_state[directive_absolute_literals] = TRUE; | |
859 | return 1; | |
860 | case option_no_absolute_literals: | |
861 | directive_state[directive_absolute_literals] = FALSE; | |
862 | return 1; | |
863 | ||
e0001a05 NC |
864 | case option_workaround_a0_b_retw: |
865 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
866 | return 1; |
867 | case option_no_workaround_a0_b_retw: | |
868 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
869 | return 1; |
870 | case option_workaround_b_j_loop_end: | |
871 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
872 | return 1; |
873 | case option_no_workaround_b_j_loop_end: | |
874 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
875 | return 1; |
876 | ||
877 | case option_workaround_short_loop: | |
878 | workaround_short_loop = TRUE; | |
e0001a05 NC |
879 | return 1; |
880 | case option_no_workaround_short_loop: | |
881 | workaround_short_loop = FALSE; | |
e0001a05 NC |
882 | return 1; |
883 | ||
884 | case option_workaround_all_short_loops: | |
885 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
886 | return 1; |
887 | case option_no_workaround_all_short_loops: | |
888 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
889 | return 1; |
890 | ||
891 | case option_workaround_close_loop_end: | |
892 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
893 | return 1; |
894 | case option_no_workaround_close_loop_end: | |
895 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
896 | return 1; |
897 | ||
898 | case option_no_workarounds: | |
899 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 900 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 901 | workaround_short_loop = FALSE; |
e0001a05 | 902 | workaround_all_short_loops = FALSE; |
e0001a05 | 903 | workaround_close_loop_end = FALSE; |
e0001a05 | 904 | return 1; |
43cd72b9 | 905 | |
e0001a05 NC |
906 | case option_align_targets: |
907 | align_targets = TRUE; | |
908 | return 1; | |
909 | case option_no_align_targets: | |
910 | align_targets = FALSE; | |
911 | return 1; | |
912 | ||
43cd72b9 BW |
913 | case option_warn_unaligned_targets: |
914 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
915 | return 1; |
916 | ||
e0001a05 NC |
917 | case option_rename_section_name: |
918 | build_section_rename (arg); | |
919 | return 1; | |
e0001a05 NC |
920 | |
921 | case 'Q': | |
922 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
923 | should be emitted or not. FIXME: Not implemented. */ | |
924 | return 1; | |
c138bc38 | 925 | |
43cd72b9 BW |
926 | case option_prefer_l32r: |
927 | if (prefer_const16) | |
928 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
929 | prefer_l32r = 1; | |
930 | return 1; | |
931 | ||
932 | case option_prefer_const16: | |
933 | if (prefer_l32r) | |
934 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
935 | prefer_const16 = 1; | |
936 | return 1; | |
937 | ||
c138bc38 | 938 | case option_target_hardware: |
43cd72b9 BW |
939 | { |
940 | int earliest, latest = 0; | |
17b9d67d | 941 | char *end; |
43cd72b9 BW |
942 | if (*arg == 0 || *arg == '-') |
943 | as_fatal (_("invalid target hardware version")); | |
944 | ||
17b9d67d | 945 | earliest = strtol (arg, &end, 0); |
43cd72b9 | 946 | |
17b9d67d | 947 | if (*end == 0) |
43cd72b9 | 948 | latest = earliest; |
17b9d67d | 949 | else if (*end == '-') |
43cd72b9 | 950 | { |
17b9d67d | 951 | if (*++end == 0) |
43cd72b9 | 952 | as_fatal (_("invalid target hardware version")); |
17b9d67d | 953 | latest = strtol (end, &end, 0); |
43cd72b9 | 954 | } |
17b9d67d | 955 | if (*end != 0) |
43cd72b9 BW |
956 | as_fatal (_("invalid target hardware version")); |
957 | ||
958 | xtensa_setup_hw_workarounds (earliest, latest); | |
959 | return 1; | |
960 | } | |
961 | ||
962 | case option_transform: | |
963 | /* This option has no affect other than to use the defaults, | |
964 | which are already set. */ | |
965 | return 1; | |
966 | ||
967 | case option_no_transform: | |
968 | /* This option turns off all transformations of any kind. | |
969 | However, because we want to preserve the state of other | |
970 | directives, we only change its own field. Thus, before | |
971 | you perform any transformation, always check if transform | |
972 | is available. If you use the functions we provide for this | |
973 | purpose, you will be ok. */ | |
974 | directive_state[directive_transform] = FALSE; | |
975 | return 1; | |
976 | ||
a82c7d90 DW |
977 | case option_trampolines: |
978 | use_trampolines = TRUE; | |
979 | return 1; | |
980 | ||
981 | case option_no_trampolines: | |
982 | use_trampolines = FALSE; | |
983 | return 1; | |
984 | ||
b46824bd MF |
985 | case option_auto_litpools: |
986 | auto_litpools = TRUE; | |
987 | use_literal_section = FALSE; | |
988 | return 1; | |
989 | ||
990 | case option_no_auto_litpools: | |
991 | auto_litpools = FALSE; | |
992 | auto_litpool_limit = -1; | |
993 | return 1; | |
994 | ||
995 | case option_auto_litpool_limit: | |
996 | { | |
997 | int value = 0; | |
17b9d67d | 998 | char *end; |
b46824bd MF |
999 | if (auto_litpool_limit < 0) |
1000 | as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); | |
1001 | if (*arg == 0 || *arg == '-') | |
1002 | as_fatal (_("invalid auto-litpool-limit argument")); | |
17b9d67d TS |
1003 | value = strtol (arg, &end, 10); |
1004 | if (*end != 0) | |
b46824bd MF |
1005 | as_fatal (_("invalid auto-litpool-limit argument")); |
1006 | if (value < 100 || value > 10000) | |
1007 | as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); | |
1008 | auto_litpool_limit = value; | |
1009 | auto_litpools = TRUE; | |
1010 | use_literal_section = FALSE; | |
1011 | return 1; | |
1012 | } | |
1013 | ||
e0001a05 NC |
1014 | default: |
1015 | return 0; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | ||
1020 | void | |
7fa3d080 | 1021 | md_show_usage (FILE *stream) |
e0001a05 | 1022 | { |
43cd72b9 BW |
1023 | fputs ("\n\ |
1024 | Xtensa options:\n\ | |
9456465c BW |
1025 | --[no-]text-section-literals\n\ |
1026 | [Do not] put literals in the text section\n\ | |
1027 | --[no-]absolute-literals\n\ | |
1028 | [Do not] default to use non-PC-relative literals\n\ | |
1029 | --[no-]target-align [Do not] try to align branch targets\n\ | |
1030 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
1031 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
1032 | --flix both allow hand-written and generate flix bundles\n\ |
1033 | --no-generate-flix allow hand-written but do not generate\n\ | |
1034 | flix bundles\n\ | |
1035 | --no-allow-flix neither allow hand-written nor generate\n\ | |
1036 | flix bundles\n\ | |
a82c7d90 DW |
1037 | --rename-section old=new Rename section 'old' to 'new'\n\ |
1038 | --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ | |
b46824bd MF |
1039 | when jumps do not reach their targets\n\ |
1040 | --[no-]auto-litpools [Do not] automatically create literal pools\n\ | |
1041 | --auto-litpool-limit=<value>\n\ | |
1042 | (range 100-10000) Maximum number of blocks of\n\ | |
1043 | instructions to emit between literal pool\n\ | |
1044 | locations; implies --auto-litpools flag\n", stream); | |
e0001a05 NC |
1045 | } |
1046 | ||
7fa3d080 BW |
1047 | \f |
1048 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
1049 | |
1050 | static void | |
7fa3d080 | 1051 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 1052 | { |
7fa3d080 | 1053 | sym_list *l; |
43cd72b9 | 1054 | |
7fa3d080 | 1055 | if (!free_insn_labels) |
325801bd | 1056 | l = XNEW (sym_list); |
7fa3d080 | 1057 | else |
43cd72b9 | 1058 | { |
7fa3d080 BW |
1059 | l = free_insn_labels; |
1060 | free_insn_labels = l->next; | |
1061 | } | |
1062 | ||
1063 | l->sym = sym; | |
1064 | l->next = insn_labels; | |
1065 | insn_labels = l; | |
1066 | } | |
1067 | ||
1068 | ||
1069 | static void | |
1070 | xtensa_clear_insn_labels (void) | |
1071 | { | |
1072 | sym_list **pl; | |
1073 | ||
1074 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1075 | ; | |
1076 | *pl = insn_labels; | |
1077 | insn_labels = NULL; | |
1078 | } | |
1079 | ||
1080 | ||
7fa3d080 | 1081 | static void |
c3ea6048 | 1082 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1083 | { |
1084 | sym_list *lit; | |
1085 | ||
1086 | for (lit = insn_labels; lit; lit = lit->next) | |
1087 | { | |
1088 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1089 | S_SET_VALUE (lit_sym, new_offset); |
1090 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1091 | } |
1092 | } | |
1093 | ||
e0001a05 NC |
1094 | \f |
1095 | /* Directive data and functions. */ | |
1096 | ||
1097 | typedef struct state_stackS_struct | |
1098 | { | |
1099 | directiveE directive; | |
1100 | bfd_boolean negated; | |
1101 | bfd_boolean old_state; | |
1102 | const char *file; | |
1103 | unsigned int line; | |
1104 | const void *datum; | |
1105 | struct state_stackS_struct *prev; | |
1106 | } state_stackS; | |
1107 | ||
1108 | state_stackS *directive_state_stack; | |
1109 | ||
1110 | const pseudo_typeS md_pseudo_table[] = | |
1111 | { | |
43cd72b9 BW |
1112 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1113 | { "literal_position", xtensa_literal_position, 0 }, | |
1114 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1115 | { "long", xtensa_elf_cons, 4 }, | |
1116 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1117 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1118 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1119 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1120 | { "sleb128", xtensa_leb128, 1}, |
1121 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1122 | { "begin", xtensa_begin_directive, 0 }, |
1123 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1124 | { "literal", xtensa_literal_pseudo, 0 }, |
1125 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1126 | { NULL, 0, 0 }, | |
e0001a05 NC |
1127 | }; |
1128 | ||
1129 | ||
7fa3d080 BW |
1130 | static bfd_boolean |
1131 | use_transform (void) | |
e0001a05 | 1132 | { |
43cd72b9 BW |
1133 | /* After md_end, you should be checking frag by frag, rather |
1134 | than state directives. */ | |
9c2799c2 | 1135 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1136 | return directive_state[directive_transform]; |
e0001a05 NC |
1137 | } |
1138 | ||
1139 | ||
7fa3d080 BW |
1140 | static bfd_boolean |
1141 | do_align_targets (void) | |
e0001a05 | 1142 | { |
7b1cc377 BW |
1143 | /* Do not use this function after md_end; just look at align_targets |
1144 | instead. There is no target-align directive, so alignment is either | |
1145 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1146 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1147 | return align_targets && use_transform (); |
e0001a05 NC |
1148 | } |
1149 | ||
1150 | ||
1151 | static void | |
7fa3d080 | 1152 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 | 1153 | { |
3b4dbbbf | 1154 | const char *file; |
e0001a05 | 1155 | unsigned int line; |
325801bd | 1156 | state_stackS *stack = XNEW (state_stackS); |
e0001a05 | 1157 | |
3b4dbbbf | 1158 | file = as_where (&line); |
e0001a05 NC |
1159 | |
1160 | stack->directive = directive; | |
1161 | stack->negated = negated; | |
1162 | stack->old_state = directive_state[directive]; | |
1163 | stack->file = file; | |
1164 | stack->line = line; | |
1165 | stack->datum = datum; | |
1166 | stack->prev = directive_state_stack; | |
1167 | directive_state_stack = stack; | |
1168 | ||
1169 | directive_state[directive] = !negated; | |
1170 | } | |
1171 | ||
7fa3d080 | 1172 | |
e0001a05 | 1173 | static void |
7fa3d080 BW |
1174 | directive_pop (directiveE *directive, |
1175 | bfd_boolean *negated, | |
1176 | const char **file, | |
1177 | unsigned int *line, | |
1178 | const void **datum) | |
e0001a05 NC |
1179 | { |
1180 | state_stackS *top = directive_state_stack; | |
1181 | ||
1182 | if (!directive_state_stack) | |
1183 | { | |
33eaf5de | 1184 | as_bad (_("unmatched .end directive")); |
e0001a05 NC |
1185 | *directive = directive_none; |
1186 | return; | |
1187 | } | |
1188 | ||
1189 | directive_state[directive_state_stack->directive] = top->old_state; | |
1190 | *directive = top->directive; | |
1191 | *negated = top->negated; | |
1192 | *file = top->file; | |
1193 | *line = top->line; | |
1194 | *datum = top->datum; | |
1195 | directive_state_stack = top->prev; | |
1196 | free (top); | |
1197 | } | |
1198 | ||
1199 | ||
1200 | static void | |
7fa3d080 | 1201 | directive_balance (void) |
e0001a05 NC |
1202 | { |
1203 | while (directive_state_stack) | |
1204 | { | |
1205 | directiveE directive; | |
1206 | bfd_boolean negated; | |
1207 | const char *file; | |
1208 | unsigned int line; | |
1209 | const void *datum; | |
1210 | ||
1211 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1212 | as_warn_where ((char *) file, line, | |
1213 | _(".begin directive with no matching .end directive")); | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | ||
1218 | static bfd_boolean | |
7fa3d080 | 1219 | inside_directive (directiveE dir) |
e0001a05 NC |
1220 | { |
1221 | state_stackS *top = directive_state_stack; | |
1222 | ||
1223 | while (top && top->directive != dir) | |
1224 | top = top->prev; | |
1225 | ||
1226 | return (top != NULL); | |
1227 | } | |
1228 | ||
1229 | ||
1230 | static void | |
7fa3d080 | 1231 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1232 | { |
1233 | int len; | |
1234 | unsigned i; | |
b9bb4a93 | 1235 | const char *directive_string; |
e0001a05 NC |
1236 | |
1237 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1238 | *negated = FALSE; | |
1239 | else | |
1240 | { | |
1241 | *negated = TRUE; | |
1242 | input_line_pointer += 3; | |
1243 | } | |
1244 | ||
1245 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1246 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1247 | ||
1248 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1249 | equivalent to .begin [no-]transform. We should remove it when | |
1250 | we stop accepting those options. */ | |
c138bc38 | 1251 | |
43cd72b9 BW |
1252 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1253 | { | |
1254 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1255 | directive_string = "transform"; | |
1256 | } | |
1257 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1258 | { | |
1259 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1260 | directive_string = "transform"; | |
c138bc38 | 1261 | } |
43cd72b9 BW |
1262 | else |
1263 | directive_string = input_line_pointer; | |
e0001a05 NC |
1264 | |
1265 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1266 | { | |
43cd72b9 | 1267 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1268 | { |
1269 | input_line_pointer += len; | |
1270 | *directive = (directiveE) i; | |
1271 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1272 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1273 | directive_info[i].name); |
1274 | return; | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | as_bad (_("unknown directive")); | |
1279 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1280 | } | |
1281 | ||
1282 | ||
1283 | static void | |
7fa3d080 | 1284 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1285 | { |
1286 | directiveE directive; | |
1287 | bfd_boolean negated; | |
1288 | emit_state *state; | |
e0001a05 NC |
1289 | lit_state *ls; |
1290 | ||
1291 | get_directive (&directive, &negated); | |
1292 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1293 | { | |
1294 | discard_rest_of_line (); | |
1295 | return; | |
1296 | } | |
1297 | ||
43cd72b9 BW |
1298 | if (cur_vinsn.inside_bundle) |
1299 | as_bad (_("directives are not valid inside bundles")); | |
1300 | ||
e0001a05 NC |
1301 | switch (directive) |
1302 | { | |
1303 | case directive_literal: | |
82e7541d BW |
1304 | if (!inside_directive (directive_literal)) |
1305 | { | |
1306 | /* Previous labels go with whatever follows this directive, not with | |
1307 | the literal, so save them now. */ | |
1308 | saved_insn_labels = insn_labels; | |
1309 | insn_labels = NULL; | |
1310 | } | |
43cd72b9 | 1311 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
325801bd | 1312 | state = XNEW (emit_state); |
e0001a05 NC |
1313 | xtensa_switch_to_literal_fragment (state); |
1314 | directive_push (directive_literal, negated, state); | |
1315 | break; | |
1316 | ||
1317 | case directive_literal_prefix: | |
c138bc38 | 1318 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1319 | might produce a literal. */ |
1320 | md_flush_pending_output (); | |
e0001a05 NC |
1321 | /* Check to see if the current fragment is a literal |
1322 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1323 | if (generating_literals) |
e0001a05 NC |
1324 | { |
1325 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1326 | return; | |
1327 | } | |
1328 | ||
1329 | /* Allocate the literal state for this section and push | |
1330 | onto the directive stack. */ | |
325801bd | 1331 | ls = XNEW (lit_state); |
9c2799c2 | 1332 | gas_assert (ls); |
e0001a05 NC |
1333 | |
1334 | *ls = default_lit_sections; | |
e0001a05 NC |
1335 | directive_push (directive_literal_prefix, negated, ls); |
1336 | ||
e0001a05 | 1337 | /* Process the new prefix. */ |
74869ac7 | 1338 | xtensa_literal_prefix (); |
e0001a05 NC |
1339 | break; |
1340 | ||
1341 | case directive_freeregs: | |
1342 | /* This information is currently unused, but we'll accept the statement | |
1343 | and just discard the rest of the line. This won't check the syntax, | |
1344 | but it will accept every correct freeregs directive. */ | |
1345 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1346 | directive_push (directive_freeregs, negated, 0); | |
1347 | break; | |
1348 | ||
43cd72b9 BW |
1349 | case directive_schedule: |
1350 | md_flush_pending_output (); | |
1351 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1352 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1353 | directive_push (directive_schedule, negated, 0); | |
1354 | xtensa_set_frag_assembly_state (frag_now); | |
1355 | break; | |
1356 | ||
e0001a05 | 1357 | case directive_density: |
43cd72b9 BW |
1358 | as_warn (_(".begin [no-]density is ignored")); |
1359 | break; | |
1360 | ||
1361 | case directive_absolute_literals: | |
1362 | md_flush_pending_output (); | |
1363 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1364 | { |
43cd72b9 | 1365 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1366 | break; |
1367 | } | |
43cd72b9 BW |
1368 | xtensa_set_frag_assembly_state (frag_now); |
1369 | directive_push (directive, negated, 0); | |
1370 | break; | |
e0001a05 NC |
1371 | |
1372 | default: | |
43cd72b9 BW |
1373 | md_flush_pending_output (); |
1374 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1375 | directive_push (directive, negated, 0); |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | demand_empty_rest_of_line (); | |
1380 | } | |
1381 | ||
1382 | ||
1383 | static void | |
7fa3d080 | 1384 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1385 | { |
1386 | directiveE begin_directive, end_directive; | |
1387 | bfd_boolean begin_negated, end_negated; | |
1388 | const char *file; | |
1389 | unsigned int line; | |
1390 | emit_state *state; | |
43cd72b9 | 1391 | emit_state **state_ptr; |
e0001a05 NC |
1392 | lit_state *s; |
1393 | ||
43cd72b9 BW |
1394 | if (cur_vinsn.inside_bundle) |
1395 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1396 | |
e0001a05 | 1397 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1398 | |
1399 | md_flush_pending_output (); | |
1400 | ||
87975d2a | 1401 | switch ((int) end_directive) |
e0001a05 | 1402 | { |
87975d2a | 1403 | case XTENSA_UNDEFINED: |
e0001a05 NC |
1404 | discard_rest_of_line (); |
1405 | return; | |
e0001a05 | 1406 | |
87975d2a | 1407 | case (int) directive_density: |
43cd72b9 | 1408 | as_warn (_(".end [no-]density is ignored")); |
e0001a05 | 1409 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1410 | break; |
1411 | ||
87975d2a | 1412 | case (int) directive_absolute_literals: |
43cd72b9 BW |
1413 | if (!absolute_literals_supported && !end_negated) |
1414 | { | |
1415 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1416 | demand_empty_rest_of_line (); | |
1417 | return; | |
1418 | } | |
1419 | break; | |
1420 | ||
1421 | default: | |
1422 | break; | |
e0001a05 NC |
1423 | } |
1424 | ||
43cd72b9 | 1425 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1426 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1427 | (const void **) state_ptr); |
e0001a05 NC |
1428 | |
1429 | if (begin_directive != directive_none) | |
1430 | { | |
1431 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1432 | { | |
1433 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1434 | begin_negated ? "no-" : "", | |
1435 | directive_info[begin_directive].name, file, line); | |
1436 | } | |
1437 | else | |
1438 | { | |
1439 | switch (end_directive) | |
1440 | { | |
1441 | case directive_literal: | |
1442 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1443 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1444 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1445 | free (state); |
82e7541d BW |
1446 | if (!inside_directive (directive_literal)) |
1447 | { | |
1448 | /* Restore the list of current labels. */ | |
1449 | xtensa_clear_insn_labels (); | |
1450 | insn_labels = saved_insn_labels; | |
1451 | } | |
e0001a05 NC |
1452 | break; |
1453 | ||
e0001a05 NC |
1454 | case directive_literal_prefix: |
1455 | /* Restore the default collection sections from saved state. */ | |
1456 | s = (lit_state *) state; | |
9c2799c2 | 1457 | gas_assert (s); |
e8247da7 | 1458 | default_lit_sections = *s; |
e0001a05 | 1459 | |
74869ac7 BW |
1460 | /* Free the state storage. */ |
1461 | free (s->lit_prefix); | |
e0001a05 NC |
1462 | free (s); |
1463 | break; | |
1464 | ||
43cd72b9 BW |
1465 | case directive_schedule: |
1466 | case directive_freeregs: | |
1467 | break; | |
1468 | ||
e0001a05 | 1469 | default: |
43cd72b9 | 1470 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1471 | break; |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | ||
1476 | demand_empty_rest_of_line (); | |
1477 | } | |
1478 | ||
1479 | ||
1480 | /* Place an aligned literal fragment at the current location. */ | |
1481 | ||
1482 | static void | |
7fa3d080 | 1483 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1484 | { |
43cd72b9 BW |
1485 | md_flush_pending_output (); |
1486 | ||
e0001a05 NC |
1487 | if (inside_directive (directive_literal)) |
1488 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1489 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1490 | |
1491 | demand_empty_rest_of_line (); | |
82e7541d | 1492 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1493 | } |
1494 | ||
1495 | ||
43cd72b9 | 1496 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1497 | |
1498 | static void | |
7fa3d080 | 1499 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1500 | { |
1501 | emit_state state; | |
1745fcba | 1502 | char *p, *base_name; |
e0001a05 | 1503 | char c; |
e0001a05 NC |
1504 | segT dest_seg; |
1505 | ||
82e7541d BW |
1506 | if (inside_directive (directive_literal)) |
1507 | { | |
1508 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1509 | ignore_rest_of_line (); | |
1510 | return; | |
1511 | } | |
1512 | ||
43cd72b9 BW |
1513 | md_flush_pending_output (); |
1514 | ||
82e7541d BW |
1515 | /* Previous labels go with whatever follows this directive, not with |
1516 | the literal, so save them now. */ | |
1517 | saved_insn_labels = insn_labels; | |
1518 | insn_labels = NULL; | |
1519 | ||
e0001a05 NC |
1520 | /* If we are using text-section literals, then this is the right value... */ |
1521 | dest_seg = now_seg; | |
1522 | ||
1523 | base_name = input_line_pointer; | |
1524 | ||
1525 | xtensa_switch_to_literal_fragment (&state); | |
1526 | ||
43cd72b9 | 1527 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1528 | need to put them in the section we just switched to. */ |
43cd72b9 | 1529 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1530 | dest_seg = now_seg; |
1531 | ||
87975d2a AM |
1532 | /* FIXME, despite the previous comments, dest_seg is unused... */ |
1533 | (void) dest_seg; | |
1534 | ||
43cd72b9 BW |
1535 | /* All literals are aligned to four-byte boundaries. */ |
1536 | frag_align (2, 0, 0); | |
1537 | record_alignment (now_seg, 2); | |
e0001a05 | 1538 | |
d02603dc | 1539 | c = get_symbol_name (&base_name); |
e0001a05 NC |
1540 | /* Just after name is now '\0'. */ |
1541 | p = input_line_pointer; | |
1542 | *p = c; | |
d02603dc | 1543 | SKIP_WHITESPACE_AFTER_NAME (); |
e0001a05 NC |
1544 | |
1545 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1546 | { | |
1547 | as_bad (_("expected comma or colon after symbol name; " | |
1548 | "rest of line ignored")); | |
1549 | ignore_rest_of_line (); | |
1550 | xtensa_restore_emit_state (&state); | |
1551 | return; | |
1552 | } | |
e0001a05 | 1553 | |
d02603dc | 1554 | *p = 0; |
e0001a05 | 1555 | colon (base_name); |
e0001a05 | 1556 | *p = c; |
d02603dc | 1557 | |
43cd72b9 | 1558 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1559 | |
43cd72b9 | 1560 | xtensa_elf_cons (4); |
e0001a05 NC |
1561 | |
1562 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1563 | |
1564 | /* Restore the list of current labels. */ | |
1565 | xtensa_clear_insn_labels (); | |
1566 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1567 | } |
1568 | ||
1569 | ||
1570 | static void | |
74869ac7 | 1571 | xtensa_literal_prefix (void) |
e0001a05 | 1572 | { |
74869ac7 BW |
1573 | char *name; |
1574 | int len; | |
1575 | ||
1576 | /* Parse the new prefix from the input_line_pointer. */ | |
1577 | SKIP_WHITESPACE (); | |
1578 | len = strspn (input_line_pointer, | |
1579 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1580 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1581 | |
1582 | /* Get a null-terminated copy of the name. */ | |
29a2809e | 1583 | name = xmemdup0 (input_line_pointer, len); |
e0001a05 | 1584 | |
74869ac7 BW |
1585 | /* Skip the name in the input line. */ |
1586 | input_line_pointer += len; | |
43cd72b9 | 1587 | |
74869ac7 | 1588 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1589 | |
74869ac7 | 1590 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1591 | default_lit_sections.lit_seg = NULL; |
1592 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1593 | } |
1594 | ||
1595 | ||
1596 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1597 | ||
1598 | static void | |
7fa3d080 | 1599 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1600 | { |
1601 | float fall_through_f, target_f; | |
43cd72b9 BW |
1602 | |
1603 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1604 | if (fall_through_f < 0) | |
1605 | { | |
1606 | as_bad (_("fall through frequency must be greater than 0")); | |
1607 | ignore_rest_of_line (); | |
1608 | return; | |
1609 | } | |
1610 | ||
1611 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1612 | if (target_f < 0) | |
1613 | { | |
1614 | as_bad (_("branch target frequency must be greater than 0")); | |
1615 | ignore_rest_of_line (); | |
1616 | return; | |
1617 | } | |
1618 | ||
b08b5071 | 1619 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1620 | |
1621 | demand_empty_rest_of_line (); | |
1622 | } | |
1623 | ||
1624 | ||
1625 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1626 | Clobbers input_line_pointer, checks end-of-line. */ | |
1627 | ||
1628 | static void | |
7fa3d080 | 1629 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1630 | { |
1631 | expressionS exp; | |
1632 | bfd_reloc_code_real_type reloc; | |
1633 | ||
1634 | md_flush_pending_output (); | |
1635 | ||
1636 | if (cur_vinsn.inside_bundle) | |
1637 | as_bad (_("directives are not valid inside bundles")); | |
1638 | ||
1639 | if (is_it_end_of_statement ()) | |
1640 | { | |
1641 | demand_empty_rest_of_line (); | |
1642 | return; | |
1643 | } | |
1644 | ||
1645 | do | |
1646 | { | |
1647 | expression (&exp); | |
1648 | if (exp.X_op == O_symbol | |
1649 | && *input_line_pointer == '@' | |
1650 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1651 | != BFD_RELOC_NONE)) | |
1652 | { | |
1653 | reloc_howto_type *reloc_howto = | |
1654 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1655 | ||
1656 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1657 | as_bad (_("unsupported relocation")); | |
1658 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1659 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1660 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1661 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1662 | as_bad (_("opcode-specific %s relocation used outside " | |
1663 | "an instruction"), reloc_howto->name); | |
1664 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
992a06ee AM |
1665 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
1666 | "%s relocations do not fit in %d bytes", | |
1667 | nbytes), | |
43cd72b9 | 1668 | reloc_howto->name, nbytes); |
28dbbc02 BW |
1669 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1670 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1671 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1672 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1673 | else |
1674 | { | |
1675 | char *p = frag_more ((int) nbytes); | |
1676 | xtensa_set_frag_assembly_state (frag_now); | |
1677 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1678 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1679 | } |
1680 | } | |
1681 | else | |
1f7efbae BW |
1682 | { |
1683 | xtensa_set_frag_assembly_state (frag_now); | |
1684 | emit_expr (&exp, (unsigned int) nbytes); | |
1685 | } | |
43cd72b9 BW |
1686 | } |
1687 | while (*input_line_pointer++ == ','); | |
1688 | ||
1689 | input_line_pointer--; /* Put terminator back into stream. */ | |
1690 | demand_empty_rest_of_line (); | |
1691 | } | |
1692 | ||
fb227da0 BW |
1693 | static bfd_boolean is_leb128_expr; |
1694 | ||
1695 | static void | |
1696 | xtensa_leb128 (int sign) | |
1697 | { | |
1698 | is_leb128_expr = TRUE; | |
1699 | s_leb128 (sign); | |
1700 | is_leb128_expr = FALSE; | |
1701 | } | |
1702 | ||
7fa3d080 BW |
1703 | \f |
1704 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1705 | |
1706 | /* Parse @plt, etc. and return the desired relocation. */ | |
1707 | static bfd_reloc_code_real_type | |
7fa3d080 | 1708 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1709 | { |
43cd72b9 BW |
1710 | char ident[20]; |
1711 | char *str = *str_p; | |
1712 | char *str2; | |
1713 | int ch; | |
1714 | int len; | |
e066bf5f | 1715 | unsigned int i; |
43cd72b9 BW |
1716 | |
1717 | if (*str++ != '@') | |
1718 | return BFD_RELOC_NONE; | |
1719 | ||
1720 | for (ch = *str, str2 = ident; | |
1721 | (str2 < ident + sizeof (ident) - 1 | |
1722 | && (ISALNUM (ch) || ch == '@')); | |
1723 | ch = *++str) | |
1724 | { | |
1725 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1726 | } | |
1727 | ||
1728 | *str2 = '\0'; | |
1729 | len = str2 - ident; | |
1730 | ||
1731 | ch = ident[0]; | |
e066bf5f TS |
1732 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
1733 | if (ch == suffix_relocs[i].suffix[0] | |
1734 | && len == suffix_relocs[i].length | |
1735 | && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) | |
43cd72b9 BW |
1736 | { |
1737 | /* Now check for "identifier@suffix+constant". */ | |
1738 | if (*str == '-' || *str == '+') | |
1739 | { | |
1740 | char *orig_line = input_line_pointer; | |
1741 | expressionS new_exp; | |
1742 | ||
1743 | input_line_pointer = str; | |
1744 | expression (&new_exp); | |
1745 | if (new_exp.X_op == O_constant) | |
1746 | { | |
1747 | exp_p->X_add_number += new_exp.X_add_number; | |
1748 | str = input_line_pointer; | |
1749 | } | |
1750 | ||
1751 | if (&input_line_pointer != str_p) | |
1752 | input_line_pointer = orig_line; | |
1753 | } | |
1754 | ||
1755 | *str_p = str; | |
e066bf5f | 1756 | return suffix_relocs[i].reloc; |
43cd72b9 BW |
1757 | } |
1758 | ||
1759 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1760 | } |
1761 | ||
e0001a05 | 1762 | |
bbdd25a8 | 1763 | /* Find the matching operator type. */ |
cc34adb2 | 1764 | static operatorT |
bbdd25a8 BW |
1765 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) |
1766 | { | |
cc34adb2 | 1767 | operatorT operator = O_illegal; |
e066bf5f | 1768 | unsigned int i; |
3739860c | 1769 | |
e066bf5f | 1770 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1771 | { |
e066bf5f | 1772 | if (suffix_relocs[i].reloc == reloc) |
bbdd25a8 | 1773 | { |
e066bf5f | 1774 | operator = suffix_relocs[i].operator; |
bbdd25a8 BW |
1775 | break; |
1776 | } | |
1777 | } | |
cc34adb2 | 1778 | gas_assert (operator != O_illegal); |
bbdd25a8 BW |
1779 | return operator; |
1780 | } | |
1781 | ||
1782 | ||
1783 | /* Find the matching reloc type. */ | |
1784 | static bfd_reloc_code_real_type | |
28dbbc02 | 1785 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 | 1786 | { |
e066bf5f | 1787 | unsigned int i; |
bbdd25a8 BW |
1788 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; |
1789 | ||
e066bf5f | 1790 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1791 | { |
e066bf5f | 1792 | if (suffix_relocs[i].operator == operator) |
bbdd25a8 | 1793 | { |
e066bf5f | 1794 | reloc = suffix_relocs[i].reloc; |
bbdd25a8 BW |
1795 | break; |
1796 | } | |
1797 | } | |
1798 | ||
28dbbc02 BW |
1799 | if (is_literal) |
1800 | { | |
1801 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1802 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1803 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1804 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1805 | } | |
1806 | ||
bbdd25a8 BW |
1807 | if (reloc == BFD_RELOC_UNUSED) |
1808 | return BFD_RELOC_32; | |
1809 | ||
1810 | return reloc; | |
1811 | } | |
1812 | ||
1813 | ||
e0001a05 | 1814 | static const char * |
7fa3d080 | 1815 | expression_end (const char *name) |
e0001a05 NC |
1816 | { |
1817 | while (1) | |
1818 | { | |
1819 | switch (*name) | |
1820 | { | |
43cd72b9 | 1821 | case '}': |
e0001a05 NC |
1822 | case ';': |
1823 | case '\0': | |
1824 | case ',': | |
43cd72b9 | 1825 | case ':': |
e0001a05 NC |
1826 | return name; |
1827 | case ' ': | |
1828 | case '\t': | |
1829 | ++name; | |
1830 | continue; | |
1831 | default: | |
1832 | return 0; | |
1833 | } | |
1834 | } | |
1835 | } | |
1836 | ||
1837 | ||
1838 | #define ERROR_REG_NUM ((unsigned) -1) | |
1839 | ||
1840 | static unsigned | |
7fa3d080 | 1841 | tc_get_register (const char *prefix) |
e0001a05 NC |
1842 | { |
1843 | unsigned reg; | |
1844 | const char *next_expr; | |
1845 | const char *old_line_pointer; | |
1846 | ||
1847 | SKIP_WHITESPACE (); | |
1848 | old_line_pointer = input_line_pointer; | |
1849 | ||
1850 | if (*input_line_pointer == '$') | |
1851 | ++input_line_pointer; | |
1852 | ||
1853 | /* Accept "sp" as a synonym for "a1". */ | |
1854 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1855 | && expression_end (input_line_pointer + 2)) | |
1856 | { | |
1857 | input_line_pointer += 2; | |
1858 | return 1; /* AR[1] */ | |
1859 | } | |
1860 | ||
1861 | while (*input_line_pointer++ == *prefix++) | |
1862 | ; | |
1863 | --input_line_pointer; | |
1864 | --prefix; | |
1865 | ||
1866 | if (*prefix) | |
1867 | { | |
1868 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1869 | return ERROR_REG_NUM; | |
1870 | } | |
1871 | ||
1872 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1873 | { | |
1874 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1875 | return ERROR_REG_NUM; | |
1876 | } | |
1877 | ||
1878 | reg = 0; | |
1879 | ||
1880 | while (ISDIGIT ((int) *input_line_pointer)) | |
1881 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1882 | ||
1883 | if (!(next_expr = expression_end (input_line_pointer))) | |
1884 | { | |
1885 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1886 | return ERROR_REG_NUM; | |
1887 | } | |
1888 | ||
1889 | input_line_pointer = (char *) next_expr; | |
1890 | ||
1891 | return reg; | |
1892 | } | |
1893 | ||
1894 | ||
e0001a05 | 1895 | static void |
7fa3d080 | 1896 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1897 | { |
43cd72b9 | 1898 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1899 | |
43cd72b9 BW |
1900 | /* Check if this is an immediate operand. */ |
1901 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1902 | { |
43cd72b9 | 1903 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1904 | segT t = expression (tok); |
91d6fa6a | 1905 | |
43cd72b9 BW |
1906 | if (t == absolute_section |
1907 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1908 | { |
9c2799c2 | 1909 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1910 | tok->X_op = O_symbol; |
1911 | tok->X_add_symbol = &abs_symbol; | |
1912 | } | |
43cd72b9 BW |
1913 | |
1914 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1915 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1916 | != BFD_RELOC_NONE)) | |
e0001a05 | 1917 | { |
1bbb5f21 | 1918 | switch (reloc) |
43cd72b9 | 1919 | { |
1bbb5f21 BW |
1920 | case BFD_RELOC_LO16: |
1921 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1922 | { |
43cd72b9 | 1923 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1924 | return; |
1bbb5f21 BW |
1925 | } |
1926 | break; | |
1927 | case BFD_RELOC_HI16: | |
1928 | if (tok->X_op == O_constant) | |
1929 | { | |
43cd72b9 | 1930 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1931 | return; |
bbdd25a8 | 1932 | } |
1bbb5f21 BW |
1933 | break; |
1934 | case BFD_RELOC_UNUSED: | |
1935 | as_bad (_("unsupported relocation")); | |
1936 | return; | |
1937 | case BFD_RELOC_32_PCREL: | |
1938 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1939 | return; | |
1940 | default: | |
1941 | break; | |
43cd72b9 | 1942 | } |
bbdd25a8 | 1943 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1944 | } |
e0001a05 NC |
1945 | } |
1946 | else | |
1947 | { | |
43cd72b9 BW |
1948 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1949 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1950 | |
1951 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1952 | { | |
1953 | uint32 buf = reg; | |
43cd72b9 | 1954 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1955 | as_bad (_("register number out of range")); |
1956 | } | |
1957 | ||
1958 | tok->X_op = O_register; | |
1959 | tok->X_add_symbol = 0; | |
1960 | tok->X_add_number = reg; | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | ||
1965 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1966 | ||
1967 | static int | |
7fa3d080 | 1968 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1969 | { |
1970 | char *old_input_line_pointer; | |
1971 | bfd_boolean saw_comma = FALSE; | |
1972 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1973 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1974 | int num_args = 0; |
1975 | char *arg_end, *arg; | |
1976 | int arg_len; | |
43cd72b9 BW |
1977 | |
1978 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1979 | old_input_line_pointer = input_line_pointer; |
1980 | input_line_pointer = str; | |
1981 | ||
1982 | while (*input_line_pointer) | |
1983 | { | |
1984 | SKIP_WHITESPACE (); | |
1985 | switch (*input_line_pointer) | |
1986 | { | |
1987 | case '\0': | |
43cd72b9 | 1988 | case '}': |
e0001a05 NC |
1989 | goto fini; |
1990 | ||
43cd72b9 BW |
1991 | case ':': |
1992 | input_line_pointer++; | |
1993 | if (saw_comma || saw_colon || !saw_arg) | |
1994 | goto err; | |
1995 | saw_colon = TRUE; | |
1996 | break; | |
1997 | ||
e0001a05 NC |
1998 | case ',': |
1999 | input_line_pointer++; | |
43cd72b9 | 2000 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
2001 | goto err; |
2002 | saw_comma = TRUE; | |
2003 | break; | |
2004 | ||
2005 | default: | |
43cd72b9 | 2006 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
2007 | goto err; |
2008 | ||
2009 | arg_end = input_line_pointer + 1; | |
2010 | while (!expression_end (arg_end)) | |
2011 | arg_end += 1; | |
43cd72b9 | 2012 | |
e0001a05 | 2013 | arg_len = arg_end - input_line_pointer; |
325801bd | 2014 | arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
2015 | args[num_args] = arg; |
2016 | ||
43cd72b9 BW |
2017 | if (saw_colon) |
2018 | *arg++ = ':'; | |
e0001a05 NC |
2019 | strncpy (arg, input_line_pointer, arg_len); |
2020 | arg[arg_len] = '\0'; | |
43cd72b9 | 2021 | |
e0001a05 NC |
2022 | input_line_pointer = arg_end; |
2023 | num_args += 1; | |
c138bc38 | 2024 | saw_comma = FALSE; |
43cd72b9 | 2025 | saw_colon = FALSE; |
c138bc38 | 2026 | saw_arg = TRUE; |
e0001a05 NC |
2027 | break; |
2028 | } | |
2029 | } | |
2030 | ||
2031 | fini: | |
43cd72b9 | 2032 | if (saw_comma || saw_colon) |
e0001a05 NC |
2033 | goto err; |
2034 | input_line_pointer = old_input_line_pointer; | |
2035 | return num_args; | |
2036 | ||
2037 | err: | |
43cd72b9 BW |
2038 | if (saw_comma) |
2039 | as_bad (_("extra comma")); | |
2040 | else if (saw_colon) | |
2041 | as_bad (_("extra colon")); | |
2042 | else if (!saw_arg) | |
c138bc38 | 2043 | as_bad (_("missing argument")); |
43cd72b9 BW |
2044 | else |
2045 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
2046 | input_line_pointer = old_input_line_pointer; |
2047 | return -1; | |
2048 | } | |
2049 | ||
2050 | ||
43cd72b9 | 2051 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
2052 | |
2053 | static bfd_boolean | |
7fa3d080 | 2054 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 2055 | { |
43cd72b9 | 2056 | expressionS *tok, *last_tok; |
e0001a05 NC |
2057 | xtensa_opcode opcode = insn->opcode; |
2058 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
2059 | xtensa_isa isa = xtensa_default_isa; |
2060 | int n, num_regs = 0; | |
e0001a05 | 2061 | int opcode_operand_count; |
43cd72b9 BW |
2062 | int opnd_cnt, last_opnd_cnt; |
2063 | unsigned int next_reg = 0; | |
e0001a05 NC |
2064 | char *old_input_line_pointer; |
2065 | ||
2066 | if (insn->insn_type == ITYPE_LITERAL) | |
2067 | opcode_operand_count = 1; | |
2068 | else | |
43cd72b9 | 2069 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 2070 | |
43cd72b9 | 2071 | tok = insn->tok; |
e0001a05 NC |
2072 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
2073 | ||
2074 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
2075 | old_input_line_pointer = input_line_pointer; |
2076 | ||
2077 | last_tok = 0; | |
2078 | last_opnd_cnt = -1; | |
2079 | opnd_cnt = 0; | |
2080 | ||
2081 | /* Skip invisible operands. */ | |
2082 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2083 | { | |
2084 | opnd_cnt += 1; | |
2085 | tok++; | |
2086 | } | |
e0001a05 NC |
2087 | |
2088 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2089 | { |
e0001a05 | 2090 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2091 | if (*input_line_pointer == ':') |
2092 | { | |
2093 | xtensa_regfile opnd_rf; | |
2094 | input_line_pointer++; | |
2095 | if (num_regs == 0) | |
2096 | goto err; | |
9c2799c2 | 2097 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2098 | num_regs--; |
2099 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2100 | if (next_reg | |
2101 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2102 | as_warn (_("incorrect register number, ignoring")); | |
2103 | next_reg++; | |
2104 | } | |
2105 | else | |
2106 | { | |
2107 | if (opnd_cnt >= opcode_operand_count) | |
2108 | { | |
2109 | as_warn (_("too many arguments")); | |
2110 | goto err; | |
2111 | } | |
9c2799c2 | 2112 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2113 | |
2114 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2115 | next_reg = tok->X_add_number + 1; | |
2116 | ||
2117 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2118 | goto err; | |
2119 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2120 | { | |
2121 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2122 | /* minus 1 because we are seeing one right now */ | |
2123 | } | |
2124 | else | |
2125 | num_regs = 0; | |
e0001a05 | 2126 | |
43cd72b9 BW |
2127 | last_tok = tok; |
2128 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2129 | demand_empty_rest_of_line (); |
e0001a05 | 2130 | |
43cd72b9 BW |
2131 | do |
2132 | { | |
2133 | opnd_cnt += 1; | |
2134 | tok++; | |
2135 | } | |
2136 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2137 | } | |
2138 | } | |
e0001a05 | 2139 | |
43cd72b9 BW |
2140 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2141 | goto err; | |
e0001a05 NC |
2142 | |
2143 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2144 | had_error = FALSE; |
e0001a05 NC |
2145 | |
2146 | err: | |
43cd72b9 | 2147 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2148 | return had_error; |
2149 | } | |
2150 | ||
2151 | ||
43cd72b9 | 2152 | static int |
7fa3d080 | 2153 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2154 | { |
2155 | xtensa_isa isa = xtensa_default_isa; | |
2156 | static xtensa_insnbuf slotbuf = NULL; | |
2157 | xtensa_format fmt; | |
2158 | xtensa_opcode opc = insn->opcode; | |
2159 | int slot, opnd, fmt_found; | |
2160 | unsigned val; | |
2161 | ||
2162 | if (!slotbuf) | |
2163 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2164 | ||
2165 | /* Find format/slot where this can be encoded. */ | |
2166 | fmt_found = 0; | |
2167 | slot = 0; | |
2168 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2169 | { | |
2170 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2171 | { | |
2172 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2173 | { | |
2174 | fmt_found = 1; | |
2175 | break; | |
2176 | } | |
2177 | } | |
2178 | if (fmt_found) break; | |
2179 | } | |
2180 | ||
2181 | if (!fmt_found) | |
2182 | { | |
2183 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2184 | return -1; | |
2185 | } | |
2186 | ||
2187 | /* First encode all the visible operands | |
2188 | (to deal with shared field operands). */ | |
2189 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2190 | { | |
2191 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2192 | && (insn->tok[opnd].X_op == O_register | |
2193 | || insn->tok[opnd].X_op == O_constant)) | |
2194 | { | |
2195 | val = insn->tok[opnd].X_add_number; | |
2196 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2197 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2198 | } | |
2199 | } | |
2200 | ||
2201 | /* Then pull out the values for the invisible ones. */ | |
2202 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2203 | { | |
2204 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2205 | { | |
2206 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2207 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2208 | insn->tok[opnd].X_add_number = val; | |
2209 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2210 | insn->tok[opnd].X_op = O_register; | |
2211 | else | |
2212 | insn->tok[opnd].X_op = O_constant; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | return 0; | |
2217 | } | |
2218 | ||
2219 | ||
e0001a05 | 2220 | static void |
7fa3d080 | 2221 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2222 | { |
2223 | char *cnt_arg, *new_arg; | |
2224 | cnt_arg = *cnt_argp; | |
2225 | ||
2226 | /* replace the argument with "31-(argument)" */ | |
78fb7e37 | 2227 | new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); |
e0001a05 NC |
2228 | |
2229 | free (cnt_arg); | |
2230 | *cnt_argp = new_arg; | |
2231 | } | |
2232 | ||
2233 | ||
2234 | /* If "arg" is a constant expression, return non-zero with the value | |
2235 | in *valp. */ | |
2236 | ||
2237 | static int | |
7fa3d080 | 2238 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2239 | { |
2240 | expressionS exp; | |
2241 | char *save_ptr = input_line_pointer; | |
2242 | ||
2243 | input_line_pointer = arg; | |
2244 | expression (&exp); | |
2245 | input_line_pointer = save_ptr; | |
2246 | ||
2247 | if (exp.X_op == O_constant) | |
2248 | { | |
2249 | *valp = exp.X_add_number; | |
2250 | return 1; | |
2251 | } | |
2252 | ||
2253 | return 0; | |
2254 | } | |
2255 | ||
2256 | ||
2257 | static void | |
b9bb4a93 | 2258 | xg_replace_opname (char **popname, const char *newop) |
e0001a05 NC |
2259 | { |
2260 | free (*popname); | |
4ec9d7d5 | 2261 | *popname = xstrdup (newop); |
e0001a05 NC |
2262 | } |
2263 | ||
2264 | ||
2265 | static int | |
7fa3d080 BW |
2266 | xg_check_num_args (int *pnum_args, |
2267 | int expected_num, | |
2268 | char *opname, | |
2269 | char **arg_strings) | |
e0001a05 NC |
2270 | { |
2271 | int num_args = *pnum_args; | |
2272 | ||
43cd72b9 | 2273 | if (num_args < expected_num) |
e0001a05 NC |
2274 | { |
2275 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2276 | num_args, opname, expected_num); | |
2277 | return -1; | |
2278 | } | |
2279 | ||
2280 | if (num_args > expected_num) | |
2281 | { | |
2282 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2283 | num_args, opname, expected_num); | |
2284 | while (num_args-- > expected_num) | |
2285 | { | |
2286 | free (arg_strings[num_args]); | |
2287 | arg_strings[num_args] = 0; | |
2288 | } | |
2289 | *pnum_args = expected_num; | |
2290 | return -1; | |
2291 | } | |
2292 | ||
2293 | return 0; | |
2294 | } | |
2295 | ||
2296 | ||
43cd72b9 BW |
2297 | /* If the register is not specified as part of the opcode, |
2298 | then get it from the operand and move it to the opcode. */ | |
2299 | ||
e0001a05 | 2300 | static int |
7fa3d080 | 2301 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2302 | { |
43cd72b9 BW |
2303 | xtensa_isa isa = xtensa_default_isa; |
2304 | xtensa_sysreg sr; | |
e0001a05 | 2305 | char *opname, *new_opname; |
43cd72b9 BW |
2306 | const char *sr_name; |
2307 | int is_user, is_write; | |
e0001a05 NC |
2308 | |
2309 | opname = *popname; | |
2310 | if (*opname == '_') | |
80ca4e2c | 2311 | opname += 1; |
43cd72b9 BW |
2312 | is_user = (opname[1] == 'u'); |
2313 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2314 | |
43cd72b9 | 2315 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2316 | |
43cd72b9 BW |
2317 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2318 | return -1; | |
e0001a05 | 2319 | |
43cd72b9 BW |
2320 | /* Check if the argument is a symbolic register name. */ |
2321 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2322 | /* Handle WSR to "INTSET" as a special case. */ | |
2323 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2324 | && !strcasecmp (arg_strings[1], "intset")) | |
2325 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2326 | if (sr == XTENSA_UNDEFINED | |
2327 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2328 | { | |
2329 | /* Maybe it's a register number.... */ | |
2330 | offsetT val; | |
e0001a05 NC |
2331 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2332 | { | |
43cd72b9 BW |
2333 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2334 | arg_strings[1], opname); | |
e0001a05 NC |
2335 | return -1; |
2336 | } | |
43cd72b9 BW |
2337 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2338 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2339 | { |
43cd72b9 | 2340 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2341 | (long) val, opname); |
e0001a05 NC |
2342 | return -1; |
2343 | } | |
43cd72b9 | 2344 | } |
e0001a05 | 2345 | |
43cd72b9 BW |
2346 | /* Remove the last argument, which is now part of the opcode. */ |
2347 | free (arg_strings[1]); | |
2348 | arg_strings[1] = 0; | |
2349 | *pnum_args = 1; | |
2350 | ||
2351 | /* Translate the opcode. */ | |
2352 | sr_name = xtensa_sysreg_name (isa, sr); | |
2353 | /* Another special case for "WSR.INTSET".... */ | |
2354 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2355 | sr_name = "intset"; | |
4ec9d7d5 | 2356 | new_opname = concat (*popname, ".", sr_name, (char *) NULL); |
43cd72b9 BW |
2357 | free (*popname); |
2358 | *popname = new_opname; | |
2359 | ||
2360 | return 0; | |
2361 | } | |
2362 | ||
2363 | ||
2364 | static int | |
7fa3d080 | 2365 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2366 | { |
2367 | xtensa_isa isa = xtensa_default_isa; | |
2368 | xtensa_sysreg sr; | |
2369 | char *opname, *new_opname; | |
2370 | const char *sr_name; | |
2371 | bfd_boolean has_underbar = FALSE; | |
2372 | ||
2373 | opname = *popname; | |
2374 | if (opname[0] == '_') | |
2375 | { | |
2376 | has_underbar = TRUE; | |
2377 | opname += 1; | |
2378 | } | |
2379 | ||
2380 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2381 | if (sr != XTENSA_UNDEFINED) | |
2382 | { | |
2383 | /* The new default name ("nnn") is different from the old default | |
2384 | name ("URnnn"). The old default is handled below, and we don't | |
2385 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2386 | default. */ | |
2387 | static char namebuf[10]; | |
2388 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2389 | if (strcmp (namebuf, opname + 1) == 0) | |
2390 | return 0; | |
2391 | } | |
2392 | else | |
2393 | { | |
2394 | offsetT val; | |
2395 | char *end; | |
2396 | ||
2397 | /* Only continue if the reg name is "URnnn". */ | |
2398 | if (opname[1] != 'u' || opname[2] != 'r') | |
2399 | return 0; | |
2400 | val = strtoul (opname + 3, &end, 10); | |
2401 | if (*end != '\0') | |
2402 | return 0; | |
2403 | ||
2404 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2405 | if (sr == XTENSA_UNDEFINED) | |
2406 | { | |
2407 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2408 | (long) val, opname); |
43cd72b9 BW |
2409 | return -1; |
2410 | } | |
2411 | } | |
2412 | ||
2413 | /* Translate the opcode. */ | |
2414 | sr_name = xtensa_sysreg_name (isa, sr); | |
add39d23 | 2415 | new_opname = XNEWVEC (char, strlen (sr_name) + 6); |
43cd72b9 BW |
2416 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), |
2417 | opname[0], sr_name); | |
2418 | free (*popname); | |
2419 | *popname = new_opname; | |
2420 | ||
2421 | return 0; | |
2422 | } | |
2423 | ||
2424 | ||
2425 | static int | |
b9bb4a93 TS |
2426 | xtensa_translate_zero_immed (const char *old_op, |
2427 | const char *new_op, | |
7fa3d080 BW |
2428 | char **popname, |
2429 | int *pnum_args, | |
2430 | char **arg_strings) | |
43cd72b9 BW |
2431 | { |
2432 | char *opname; | |
2433 | offsetT val; | |
2434 | ||
2435 | opname = *popname; | |
9c2799c2 | 2436 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2437 | |
2438 | if (strcmp (opname, old_op) != 0) | |
2439 | return 0; | |
e0001a05 | 2440 | |
43cd72b9 BW |
2441 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2442 | return -1; | |
2443 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2444 | { | |
2445 | xg_replace_opname (popname, new_op); | |
2446 | free (arg_strings[1]); | |
2447 | arg_strings[1] = arg_strings[2]; | |
2448 | arg_strings[2] = 0; | |
2449 | *pnum_args = 2; | |
e0001a05 NC |
2450 | } |
2451 | ||
2452 | return 0; | |
2453 | } | |
2454 | ||
2455 | ||
2456 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2457 | Returns non-zero if an error was found. */ | |
2458 | ||
2459 | static int | |
7fa3d080 | 2460 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2461 | { |
2462 | char *opname = *popname; | |
2463 | bfd_boolean has_underbar = FALSE; | |
2464 | ||
2465 | if (*opname == '_') | |
2466 | { | |
2467 | has_underbar = TRUE; | |
2468 | opname += 1; | |
2469 | } | |
2470 | ||
2471 | if (strcmp (opname, "mov") == 0) | |
2472 | { | |
43cd72b9 | 2473 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2474 | xg_replace_opname (popname, "mov.n"); |
2475 | else | |
2476 | { | |
2477 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2478 | return -1; | |
2479 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 | 2480 | arg_strings[2] = xstrdup (arg_strings[1]); |
e0001a05 NC |
2481 | *pnum_args = 3; |
2482 | } | |
2483 | return 0; | |
2484 | } | |
2485 | ||
2486 | if (strcmp (opname, "bbsi.l") == 0) | |
2487 | { | |
2488 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2489 | return -1; | |
2490 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2491 | if (target_big_endian) | |
2492 | xg_reverse_shift_count (&arg_strings[1]); | |
2493 | return 0; | |
2494 | } | |
2495 | ||
2496 | if (strcmp (opname, "bbci.l") == 0) | |
2497 | { | |
2498 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2499 | return -1; | |
2500 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2501 | if (target_big_endian) | |
2502 | xg_reverse_shift_count (&arg_strings[1]); | |
2503 | return 0; | |
2504 | } | |
2505 | ||
eb6d9dce | 2506 | /* Don't do anything special with NOPs inside FLIX instructions. They |
3739860c | 2507 | are handled elsewhere. Real NOP instructions are always available |
eb6d9dce BW |
2508 | in configurations with FLIX, so this should never be an issue but |
2509 | check for it anyway. */ | |
2510 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2511 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2512 | { |
43cd72b9 | 2513 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2514 | xg_replace_opname (popname, "nop.n"); |
2515 | else | |
2516 | { | |
2517 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2518 | return -1; | |
2519 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 TS |
2520 | arg_strings[0] = xstrdup ("a1"); |
2521 | arg_strings[1] = xstrdup ("a1"); | |
2522 | arg_strings[2] = xstrdup ("a1"); | |
e0001a05 NC |
2523 | *pnum_args = 3; |
2524 | } | |
2525 | return 0; | |
2526 | } | |
2527 | ||
43cd72b9 BW |
2528 | /* Recognize [RW]UR and [RWX]SR. */ |
2529 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2530 | && (opname[1] == 'u' || opname[1] == 's')) | |
2531 | || (opname[0] == 'x' && opname[1] == 's')) | |
2532 | && opname[2] == 'r' | |
2533 | && opname[3] == '\0') | |
e0001a05 NC |
2534 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2535 | ||
43cd72b9 BW |
2536 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2537 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2538 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2539 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2540 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2541 | |
43cd72b9 BW |
2542 | /* Relax branches that don't allow comparisons against an immediate value |
2543 | of zero to the corresponding branches with implicit zero immediates. */ | |
2544 | if (!has_underbar && use_transform ()) | |
2545 | { | |
2546 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2547 | pnum_args, arg_strings)) | |
2548 | return -1; | |
e0001a05 | 2549 | |
43cd72b9 BW |
2550 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2551 | pnum_args, arg_strings)) | |
2552 | return -1; | |
e0001a05 | 2553 | |
43cd72b9 BW |
2554 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2555 | pnum_args, arg_strings)) | |
2556 | return -1; | |
e0001a05 | 2557 | |
43cd72b9 BW |
2558 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2559 | pnum_args, arg_strings)) | |
2560 | return -1; | |
2561 | } | |
e0001a05 | 2562 | |
43cd72b9 BW |
2563 | return 0; |
2564 | } | |
e0001a05 | 2565 | |
43cd72b9 BW |
2566 | \f |
2567 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2568 | |
43cd72b9 BW |
2569 | /* Currently the assembler only allows us to use a single target per |
2570 | fragment. Because of this, only one operand for a given | |
2571 | instruction may be symbolic. If there is a PC-relative operand, | |
2572 | the last one is chosen. Otherwise, the result is the number of the | |
2573 | last immediate operand, and if there are none of those, we fail and | |
2574 | return -1. */ | |
e0001a05 | 2575 | |
7fa3d080 BW |
2576 | static int |
2577 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2578 | { |
2579 | int last_immed = -1; | |
2580 | int noperands, opi; | |
e0001a05 | 2581 | |
43cd72b9 BW |
2582 | if (opcode == XTENSA_UNDEFINED) |
2583 | return -1; | |
e0001a05 | 2584 | |
43cd72b9 BW |
2585 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2586 | for (opi = noperands - 1; opi >= 0; opi--) | |
2587 | { | |
2588 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2589 | continue; | |
2590 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2591 | return opi; | |
2592 | if (last_immed == -1 | |
2593 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2594 | last_immed = opi; | |
e0001a05 | 2595 | } |
43cd72b9 | 2596 | return last_immed; |
e0001a05 NC |
2597 | } |
2598 | ||
e0001a05 | 2599 | |
43cd72b9 | 2600 | static xtensa_opcode |
7fa3d080 | 2601 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2602 | { |
43cd72b9 BW |
2603 | static xtensa_insnbuf insnbuf = NULL; |
2604 | static xtensa_insnbuf slotbuf = NULL; | |
2605 | xtensa_isa isa = xtensa_default_isa; | |
2606 | xtensa_format fmt; | |
2607 | ||
2608 | if (!insnbuf) | |
e0001a05 | 2609 | { |
43cd72b9 BW |
2610 | insnbuf = xtensa_insnbuf_alloc (isa); |
2611 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2612 | } |
e0001a05 | 2613 | |
d77b99c9 | 2614 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2615 | fmt = xtensa_format_decode (isa, insnbuf); |
2616 | if (fmt == XTENSA_UNDEFINED) | |
2617 | return XTENSA_UNDEFINED; | |
e0001a05 | 2618 | |
43cd72b9 BW |
2619 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2620 | return XTENSA_UNDEFINED; | |
e0001a05 | 2621 | |
43cd72b9 BW |
2622 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2623 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2624 | } |
2625 | ||
2626 | ||
43cd72b9 | 2627 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2628 | |
43cd72b9 | 2629 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2630 | |
7fa3d080 BW |
2631 | static void |
2632 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2633 | { |
2634 | int num_opcodes, num_operands; | |
2635 | xtensa_opcode opcode; | |
2636 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2637 | |
43cd72b9 BW |
2638 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2639 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2640 | { |
43cd72b9 BW |
2641 | int opn; |
2642 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2643 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2644 | for (opn = 0; opn < num_operands; opn++) | |
2645 | { | |
2646 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2647 | continue; | |
2648 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2649 | { | |
2650 | xtensa_regfile opnd_rf = | |
2651 | xtensa_operand_regfile (isa, opcode, opn); | |
2652 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2653 | } | |
2654 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2655 | fputs ("[lLr] ", stderr); | |
2656 | else | |
2657 | fputs ("i ", stderr); | |
2658 | } | |
2659 | fprintf (stderr, "\n"); | |
e0001a05 | 2660 | } |
e0001a05 NC |
2661 | } |
2662 | ||
2663 | ||
43cd72b9 | 2664 | static void |
7fa3d080 | 2665 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2666 | { |
e0001a05 | 2667 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2668 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2669 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2670 | int op; | |
e0001a05 | 2671 | |
43cd72b9 | 2672 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2673 | |
43cd72b9 BW |
2674 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2675 | { | |
2676 | xtensa_opcode opcode; | |
2677 | const char *opname; | |
2678 | int operands; | |
2679 | ||
2680 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2681 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2682 | opname = xtensa_opcode_name (isa, opcode); | |
2683 | ||
2684 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2685 | fprintf (stderr, " operands = "); | |
2686 | for (operands = 0; | |
2687 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2688 | operands++) | |
2689 | { | |
2690 | unsigned int val; | |
2691 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2692 | continue; | |
2693 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2694 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2695 | fprintf (stderr, "%d ", val); | |
2696 | } | |
2697 | fprintf (stderr, "\n"); | |
2698 | } | |
2699 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2700 | } |
2701 | ||
43cd72b9 BW |
2702 | #endif /* TENSILICA_DEBUG */ |
2703 | ||
e0001a05 NC |
2704 | |
2705 | static bfd_boolean | |
7fa3d080 | 2706 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2707 | { |
43cd72b9 BW |
2708 | xtensa_isa isa = xtensa_default_isa; |
2709 | int n, num_operands; | |
e0001a05 | 2710 | |
64b607e6 | 2711 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2712 | return FALSE; |
2713 | ||
43cd72b9 BW |
2714 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2715 | for (n = 0; n < num_operands; n++) | |
2716 | { | |
2717 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2718 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2719 | return TRUE; | |
2720 | } | |
2721 | return FALSE; | |
e0001a05 NC |
2722 | } |
2723 | ||
2724 | ||
43cd72b9 BW |
2725 | /* Convert from BFD relocation type code to slot and operand number. |
2726 | Returns non-zero on failure. */ | |
e0001a05 | 2727 | |
43cd72b9 | 2728 | static int |
7fa3d080 | 2729 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2730 | { |
43cd72b9 BW |
2731 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2732 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2733 | { |
43cd72b9 BW |
2734 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2735 | *is_alt = FALSE; | |
e0001a05 | 2736 | } |
43cd72b9 BW |
2737 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2738 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2739 | { |
43cd72b9 BW |
2740 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2741 | *is_alt = TRUE; | |
e0001a05 | 2742 | } |
43cd72b9 BW |
2743 | else |
2744 | return -1; | |
2745 | ||
2746 | return 0; | |
e0001a05 NC |
2747 | } |
2748 | ||
2749 | ||
43cd72b9 BW |
2750 | /* Convert from slot number to BFD relocation type code for the |
2751 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2752 | failure. */ | |
e0001a05 | 2753 | |
43cd72b9 | 2754 | static bfd_reloc_code_real_type |
7fa3d080 | 2755 | encode_reloc (int slot) |
e0001a05 | 2756 | { |
43cd72b9 BW |
2757 | if (slot < 0 || slot > 14) |
2758 | return BFD_RELOC_NONE; | |
2759 | ||
2760 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2761 | } |
2762 | ||
2763 | ||
43cd72b9 BW |
2764 | /* Convert from slot numbers to BFD relocation type code for the |
2765 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2766 | |
43cd72b9 | 2767 | static bfd_reloc_code_real_type |
7fa3d080 | 2768 | encode_alt_reloc (int slot) |
e0001a05 | 2769 | { |
43cd72b9 BW |
2770 | if (slot < 0 || slot > 14) |
2771 | return BFD_RELOC_NONE; | |
2772 | ||
2773 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2774 | } |
2775 | ||
2776 | ||
2777 | static void | |
7fa3d080 BW |
2778 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2779 | xtensa_format fmt, | |
2780 | int slot, | |
2781 | xtensa_opcode opcode, | |
2782 | int operand, | |
2783 | uint32 value, | |
2784 | const char *file, | |
2785 | unsigned int line) | |
e0001a05 | 2786 | { |
e0001a05 NC |
2787 | uint32 valbuf = value; |
2788 | ||
43cd72b9 | 2789 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2790 | { |
43cd72b9 BW |
2791 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2792 | == 1) | |
2793 | as_bad_where ((char *) file, line, | |
3739860c | 2794 | _("operand %d of '%s' has out of range value '%u'"), |
d7c531cd BW |
2795 | operand + 1, |
2796 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2797 | value); | |
43cd72b9 BW |
2798 | else |
2799 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2800 | _("operand %d of '%s' has invalid value '%u'"), |
2801 | operand + 1, | |
2802 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2803 | value); | |
43cd72b9 | 2804 | return; |
e0001a05 NC |
2805 | } |
2806 | ||
43cd72b9 BW |
2807 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2808 | slotbuf, valbuf); | |
e0001a05 NC |
2809 | } |
2810 | ||
2811 | ||
2812 | static uint32 | |
7fa3d080 BW |
2813 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2814 | xtensa_format fmt, | |
2815 | int slot, | |
2816 | xtensa_opcode opcode, | |
2817 | int opnum) | |
e0001a05 | 2818 | { |
43cd72b9 BW |
2819 | uint32 val = 0; |
2820 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2821 | fmt, slot, slotbuf, &val); | |
2822 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2823 | return val; | |
e0001a05 NC |
2824 | } |
2825 | ||
e0001a05 | 2826 | \f |
7fa3d080 | 2827 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2828 | |
7fa3d080 BW |
2829 | /* The routine xg_instruction_matches_option_term must return TRUE |
2830 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2831 | terms is given interpretation by this function. */ |
e0001a05 | 2832 | |
7fa3d080 | 2833 | static bfd_boolean |
19e8f41a | 2834 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2835 | { |
7fa3d080 BW |
2836 | if (strcmp (option->option_name, "realnop") == 0 |
2837 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2838 | { | |
2839 | /* These conditions were evaluated statically when building the | |
2840 | relaxation table. There's no need to reevaluate them now. */ | |
2841 | return TRUE; | |
2842 | } | |
19e8f41a BW |
2843 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2844 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2845 | else |
2846 | { | |
2847 | as_fatal (_("internal error: unknown option name '%s'"), | |
2848 | option->option_name); | |
2849 | } | |
e0001a05 NC |
2850 | } |
2851 | ||
2852 | ||
7fa3d080 BW |
2853 | static bfd_boolean |
2854 | xg_instruction_matches_or_options (TInsn *insn, | |
2855 | const ReqOrOptionList *or_option) | |
e0001a05 | 2856 | { |
7fa3d080 BW |
2857 | const ReqOrOption *option; |
2858 | /* Must match each of the AND terms. */ | |
2859 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2860 | { |
7fa3d080 BW |
2861 | if (xg_instruction_matches_option_term (insn, option)) |
2862 | return TRUE; | |
e0001a05 | 2863 | } |
7fa3d080 | 2864 | return FALSE; |
e0001a05 NC |
2865 | } |
2866 | ||
2867 | ||
7fa3d080 BW |
2868 | static bfd_boolean |
2869 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2870 | { |
7fa3d080 BW |
2871 | const ReqOption *req_options; |
2872 | /* Must match each of the AND terms. */ | |
2873 | for (req_options = options; | |
2874 | req_options != NULL; | |
2875 | req_options = req_options->next) | |
e0001a05 | 2876 | { |
7fa3d080 BW |
2877 | /* Must match one of the OR clauses. */ |
2878 | if (!xg_instruction_matches_or_options (insn, | |
2879 | req_options->or_option_terms)) | |
2880 | return FALSE; | |
e0001a05 | 2881 | } |
7fa3d080 | 2882 | return TRUE; |
e0001a05 NC |
2883 | } |
2884 | ||
2885 | ||
7fa3d080 | 2886 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2887 | |
7fa3d080 BW |
2888 | static bfd_boolean |
2889 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2890 | { |
7fa3d080 | 2891 | PreconditionList *condition_l; |
e0001a05 | 2892 | |
7fa3d080 BW |
2893 | if (rule->opcode != insn->opcode) |
2894 | return FALSE; | |
e0001a05 | 2895 | |
7fa3d080 BW |
2896 | for (condition_l = rule->conditions; |
2897 | condition_l != NULL; | |
2898 | condition_l = condition_l->next) | |
e0001a05 | 2899 | { |
7fa3d080 BW |
2900 | expressionS *exp1; |
2901 | expressionS *exp2; | |
2902 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2903 | |
7fa3d080 | 2904 | switch (cond->typ) |
e0001a05 | 2905 | { |
7fa3d080 BW |
2906 | case OP_CONSTANT: |
2907 | /* The expression must be the constant. */ | |
9c2799c2 | 2908 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2909 | exp1 = &insn->tok[cond->op_num]; |
2910 | if (expr_is_const (exp1)) | |
2911 | { | |
2912 | switch (cond->cmp) | |
2913 | { | |
2914 | case OP_EQUAL: | |
2915 | if (get_expr_const (exp1) != cond->op_data) | |
2916 | return FALSE; | |
2917 | break; | |
2918 | case OP_NOTEQUAL: | |
2919 | if (get_expr_const (exp1) == cond->op_data) | |
2920 | return FALSE; | |
2921 | break; | |
2922 | default: | |
2923 | return FALSE; | |
2924 | } | |
2925 | } | |
2926 | else if (expr_is_register (exp1)) | |
2927 | { | |
2928 | switch (cond->cmp) | |
2929 | { | |
2930 | case OP_EQUAL: | |
2931 | if (get_expr_register (exp1) != cond->op_data) | |
2932 | return FALSE; | |
2933 | break; | |
2934 | case OP_NOTEQUAL: | |
2935 | if (get_expr_register (exp1) == cond->op_data) | |
2936 | return FALSE; | |
2937 | break; | |
2938 | default: | |
2939 | return FALSE; | |
2940 | } | |
2941 | } | |
2942 | else | |
2943 | return FALSE; | |
2944 | break; | |
2945 | ||
2946 | case OP_OPERAND: | |
9c2799c2 NC |
2947 | gas_assert (cond->op_num < insn->ntok); |
2948 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2949 | exp1 = &insn->tok[cond->op_num]; |
2950 | exp2 = &insn->tok[cond->op_data]; | |
2951 | ||
2952 | switch (cond->cmp) | |
2953 | { | |
2954 | case OP_EQUAL: | |
2955 | if (!expr_is_equal (exp1, exp2)) | |
2956 | return FALSE; | |
2957 | break; | |
2958 | case OP_NOTEQUAL: | |
2959 | if (expr_is_equal (exp1, exp2)) | |
2960 | return FALSE; | |
2961 | break; | |
2962 | } | |
2963 | break; | |
2964 | ||
2965 | case OP_LITERAL: | |
2966 | case OP_LABEL: | |
2967 | default: | |
2968 | return FALSE; | |
2969 | } | |
2970 | } | |
2971 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2972 | return FALSE; | |
2973 | ||
2974 | return TRUE; | |
2975 | } | |
2976 | ||
2977 | ||
2978 | static int | |
2979 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2980 | { | |
2981 | bfd_boolean a_greater = FALSE; | |
2982 | bfd_boolean b_greater = FALSE; | |
2983 | ||
2984 | ReqOptionList *l_a = a->options; | |
2985 | ReqOptionList *l_b = b->options; | |
2986 | ||
2987 | /* We only care if they both are the same except for | |
2988 | a const16 vs. an l32r. */ | |
2989 | ||
2990 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2991 | { | |
2992 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2993 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2994 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2995 | { | |
2996 | if (l_or_a->is_true != l_or_b->is_true) | |
2997 | return 0; | |
2998 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2999 | { | |
3000 | /* This is the case we care about. */ | |
3001 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
3002 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
3003 | { | |
3004 | if (prefer_const16) | |
3005 | a_greater = TRUE; | |
3006 | else | |
3007 | b_greater = TRUE; | |
3008 | } | |
3009 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
3010 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
3011 | { | |
3012 | if (prefer_const16) | |
3013 | b_greater = TRUE; | |
3014 | else | |
3015 | a_greater = TRUE; | |
3016 | } | |
3017 | else | |
3018 | return 0; | |
3019 | } | |
3020 | l_or_a = l_or_a->next; | |
3021 | l_or_b = l_or_b->next; | |
3022 | } | |
3023 | if (l_or_a || l_or_b) | |
3024 | return 0; | |
3025 | ||
3026 | l_a = l_a->next; | |
3027 | l_b = l_b->next; | |
3028 | } | |
3029 | if (l_a || l_b) | |
3030 | return 0; | |
3031 | ||
3032 | /* Incomparable if the substitution was used differently in two cases. */ | |
3033 | if (a_greater && b_greater) | |
3034 | return 0; | |
3035 | ||
3036 | if (b_greater) | |
3037 | return 1; | |
3038 | if (a_greater) | |
3039 | return -1; | |
3040 | ||
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | ||
3045 | static TransitionRule * | |
3046 | xg_instruction_match (TInsn *insn) | |
3047 | { | |
3048 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
3049 | TransitionList *l; | |
9c2799c2 | 3050 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
3051 | |
3052 | /* Walk through all of the possible transitions. */ | |
3053 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3054 | { | |
3055 | TransitionRule *rule = l->rule; | |
3056 | if (xg_instruction_matches_rule (insn, rule)) | |
3057 | return rule; | |
3058 | } | |
3059 | return NULL; | |
3060 | } | |
3061 | ||
3062 | \f | |
3063 | /* Various Other Internal Functions. */ | |
3064 | ||
3065 | static bfd_boolean | |
3066 | is_unique_insn_expansion (TransitionRule *r) | |
3067 | { | |
3068 | if (!r->to_instr || r->to_instr->next != NULL) | |
3069 | return FALSE; | |
3070 | if (r->to_instr->typ != INSTR_INSTR) | |
3071 | return FALSE; | |
3072 | return TRUE; | |
3073 | } | |
3074 | ||
3075 | ||
84b08ed9 BW |
3076 | /* Check if there is exactly one relaxation for INSN that converts it to |
3077 | another instruction of equal or larger size. If so, and if TARG is | |
3078 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3079 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3080 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3081 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3082 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3083 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3084 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3085 | |
84b08ed9 BW |
3086 | bfd_boolean |
3087 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3088 | { |
3089 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3090 | TransitionList *l; | |
84b08ed9 | 3091 | TransitionRule *match = 0; |
7fa3d080 | 3092 | |
9c2799c2 NC |
3093 | gas_assert (insn->insn_type == ITYPE_INSN); |
3094 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3095 | |
3096 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3097 | { | |
3098 | TransitionRule *rule = l->rule; | |
3099 | ||
3100 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3101 | && is_unique_insn_expansion (rule) |
3102 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3103 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3104 | { |
84b08ed9 BW |
3105 | if (match) |
3106 | return FALSE; | |
3107 | match = rule; | |
7fa3d080 BW |
3108 | } |
3109 | } | |
84b08ed9 BW |
3110 | if (!match) |
3111 | return FALSE; | |
3112 | ||
3113 | if (targ) | |
3114 | xg_build_to_insn (targ, insn, match->to_instr); | |
3115 | return TRUE; | |
7fa3d080 BW |
3116 | } |
3117 | ||
3118 | ||
3119 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3120 | ||
3121 | static int | |
3122 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3123 | { | |
3124 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3125 | TransitionList *l; | |
3126 | int max_size = xg_get_single_size (opcode); | |
3127 | ||
9c2799c2 | 3128 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3129 | |
3130 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3131 | { | |
3132 | TransitionRule *rule = l->rule; | |
3133 | BuildInstr *build_list; | |
3134 | int this_size = 0; | |
3135 | ||
3136 | if (!rule) | |
3137 | continue; | |
3138 | build_list = rule->to_instr; | |
3139 | if (is_unique_insn_expansion (rule)) | |
3140 | { | |
9c2799c2 | 3141 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3142 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3143 | } | |
3144 | else | |
3145 | for (; build_list != NULL; build_list = build_list->next) | |
3146 | { | |
3147 | switch (build_list->typ) | |
3148 | { | |
3149 | case INSTR_INSTR: | |
3150 | this_size += xg_get_single_size (build_list->opcode); | |
3151 | break; | |
3152 | case INSTR_LITERAL_DEF: | |
3153 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3154 | default: |
3155 | break; | |
3156 | } | |
3157 | } | |
3158 | if (this_size > max_size) | |
3159 | max_size = this_size; | |
3160 | } | |
3161 | return max_size; | |
3162 | } | |
3163 | ||
3164 | ||
3165 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3166 | ||
7fa3d080 BW |
3167 | static int |
3168 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3169 | { |
43cd72b9 | 3170 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3171 | TransitionList *l; |
3172 | int max_size = 0; | |
3173 | ||
9c2799c2 | 3174 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3175 | |
3176 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3177 | { | |
3178 | TransitionRule *rule = l->rule; | |
3179 | BuildInstr *build_list; | |
3180 | int this_size = 0; | |
3181 | ||
3182 | if (!rule) | |
3183 | continue; | |
3184 | build_list = rule->to_instr; | |
3185 | if (is_unique_insn_expansion (rule)) | |
3186 | { | |
9c2799c2 | 3187 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3188 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3189 | } | |
3190 | else | |
3191 | for (; build_list != NULL; build_list = build_list->next) | |
3192 | { | |
3193 | switch (build_list->typ) | |
3194 | { | |
3195 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3196 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3197 | this_size += 4; |
3198 | break; | |
3199 | case INSTR_INSTR: | |
3200 | case INSTR_LABEL_DEF: | |
3201 | default: | |
3202 | break; | |
3203 | } | |
3204 | } | |
3205 | if (this_size > max_size) | |
3206 | max_size = this_size; | |
3207 | } | |
3208 | return max_size; | |
3209 | } | |
3210 | ||
3211 | ||
7fa3d080 BW |
3212 | static bfd_boolean |
3213 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3214 | { | |
3215 | int steps_taken = 0; | |
3216 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3217 | TransitionList *l; | |
3218 | ||
9c2799c2 NC |
3219 | gas_assert (insn->insn_type == ITYPE_INSN); |
3220 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3221 | |
3222 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3223 | { | |
3224 | TransitionRule *rule = l->rule; | |
3225 | ||
3226 | if (xg_instruction_matches_rule (insn, rule)) | |
3227 | { | |
3228 | if (steps_taken == lateral_steps) | |
3229 | return TRUE; | |
3230 | steps_taken++; | |
3231 | } | |
3232 | } | |
3233 | return FALSE; | |
3234 | } | |
3235 | ||
3236 | ||
3237 | static symbolS * | |
3238 | get_special_literal_symbol (void) | |
3239 | { | |
3240 | static symbolS *sym = NULL; | |
3241 | ||
3242 | if (sym == NULL) | |
3243 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3244 | return sym; | |
3245 | } | |
3246 | ||
3247 | ||
3248 | static symbolS * | |
3249 | get_special_label_symbol (void) | |
3250 | { | |
3251 | static symbolS *sym = NULL; | |
3252 | ||
3253 | if (sym == NULL) | |
3254 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3255 | return sym; | |
3256 | } | |
3257 | ||
3258 | ||
3259 | static bfd_boolean | |
3260 | xg_valid_literal_expression (const expressionS *exp) | |
3261 | { | |
3262 | switch (exp->X_op) | |
3263 | { | |
3264 | case O_constant: | |
3265 | case O_symbol: | |
3266 | case O_big: | |
3267 | case O_uminus: | |
3268 | case O_subtract: | |
3269 | case O_pltrel: | |
1bbb5f21 | 3270 | case O_pcrel: |
28dbbc02 BW |
3271 | case O_tlsfunc: |
3272 | case O_tlsarg: | |
3273 | case O_tpoff: | |
3274 | case O_dtpoff: | |
7fa3d080 BW |
3275 | return TRUE; |
3276 | default: | |
3277 | return FALSE; | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | ||
3282 | /* This will check to see if the value can be converted into the | |
3283 | operand type. It will return TRUE if it does not fit. */ | |
3284 | ||
3285 | static bfd_boolean | |
3286 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3287 | { | |
3288 | uint32 valbuf = value; | |
3289 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3290 | return TRUE; | |
3291 | return FALSE; | |
3292 | } | |
3293 | ||
3294 | ||
3295 | /* Assumes: All immeds are constants. Check that all constants fit | |
3296 | into their immeds; return FALSE if not. */ | |
3297 | ||
3298 | static bfd_boolean | |
3299 | xg_immeds_fit (const TInsn *insn) | |
3300 | { | |
3301 | xtensa_isa isa = xtensa_default_isa; | |
3302 | int i; | |
3303 | ||
3304 | int n = insn->ntok; | |
9c2799c2 | 3305 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3306 | for (i = 0; i < n; ++i) |
3307 | { | |
91d6fa6a NC |
3308 | const expressionS *exp = &insn->tok[i]; |
3309 | ||
7fa3d080 BW |
3310 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3311 | continue; | |
3312 | ||
91d6fa6a | 3313 | switch (exp->X_op) |
7fa3d080 BW |
3314 | { |
3315 | case O_register: | |
3316 | case O_constant: | |
91d6fa6a | 3317 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3318 | return FALSE; |
3319 | break; | |
3320 | ||
3321 | default: | |
3322 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3323 | gas_assert (FALSE); |
7fa3d080 BW |
3324 | break; |
3325 | } | |
3326 | } | |
3327 | return TRUE; | |
3328 | } | |
3329 | ||
3330 | ||
3331 | /* This should only be called after we have an initial | |
3332 | estimate of the addresses. */ | |
3333 | ||
3334 | static bfd_boolean | |
3335 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3336 | segT pc_seg, | |
3337 | fragS *pc_frag, | |
3338 | offsetT pc_offset, | |
3339 | long stretch) | |
e0001a05 | 3340 | { |
7fa3d080 BW |
3341 | xtensa_isa isa = xtensa_default_isa; |
3342 | symbolS *symbolP; | |
3343 | fragS *sym_frag; | |
3344 | offsetT target, pc; | |
3345 | uint32 new_offset; | |
3346 | int i; | |
3347 | int n = insn->ntok; | |
e0001a05 | 3348 | |
9c2799c2 | 3349 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3350 | |
7fa3d080 | 3351 | for (i = 0; i < n; ++i) |
e0001a05 | 3352 | { |
91d6fa6a NC |
3353 | const expressionS *exp = &insn->tok[i]; |
3354 | ||
7fa3d080 BW |
3355 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3356 | continue; | |
e0001a05 | 3357 | |
91d6fa6a | 3358 | switch (exp->X_op) |
e0001a05 | 3359 | { |
7fa3d080 BW |
3360 | case O_register: |
3361 | case O_constant: | |
91d6fa6a | 3362 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3363 | return FALSE; |
3364 | break; | |
e0001a05 | 3365 | |
7fa3d080 BW |
3366 | case O_lo16: |
3367 | case O_hi16: | |
3368 | /* Check for the worst case. */ | |
3369 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3370 | return FALSE; | |
3371 | break; | |
e0001a05 | 3372 | |
7fa3d080 | 3373 | case O_symbol: |
7c834684 | 3374 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3375 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3376 | if (pc_frag == 0 |
3377 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3378 | return FALSE; |
e0001a05 | 3379 | |
8e6bc631 BW |
3380 | /* If it is a weak symbol or a symbol in a different section, |
3381 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3382 | if (S_IS_WEAK (exp->X_add_symbol) |
3383 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3384 | { |
8e6bc631 | 3385 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3386 | assume it will be in range. If the symbol is weak and |
3387 | undefined, it may remain undefined at link-time, in which | |
3388 | case it will have a zero value and almost certainly be out | |
3389 | of range for a direct call; thus, relax for undefined weak | |
3390 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3391 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3392 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3393 | && (! S_IS_WEAK (exp->X_add_symbol) |
3394 | || S_IS_DEFINED (exp->X_add_symbol))) | |
7c834684 | 3395 | return TRUE; |
7c834684 | 3396 | |
8e6bc631 BW |
3397 | return FALSE; |
3398 | } | |
e0001a05 | 3399 | |
91d6fa6a | 3400 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3401 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3402 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3403 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3404 | |
7fa3d080 BW |
3405 | /* If frag has yet to be reached on this pass, assume it |
3406 | will move by STRETCH just as we did. If this is not so, | |
3407 | it will be because some frag between grows, and that will | |
3408 | force another pass. Beware zero-length frags. There | |
3409 | should be a faster way to do this. */ | |
3410 | ||
3411 | if (stretch != 0 | |
3412 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3413 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3414 | { | |
3415 | target += stretch; | |
3416 | } | |
c138bc38 | 3417 | |
7fa3d080 BW |
3418 | new_offset = target; |
3419 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3420 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3421 | return FALSE; | |
3422 | break; | |
3423 | ||
3424 | default: | |
3425 | /* The symbol should have a fixup associated with it. */ | |
3426 | return FALSE; | |
3427 | } | |
3428 | } | |
3429 | ||
3430 | return TRUE; | |
e0001a05 NC |
3431 | } |
3432 | ||
3433 | ||
43cd72b9 | 3434 | /* Return TRUE on success. */ |
e0001a05 | 3435 | |
7fa3d080 BW |
3436 | static bfd_boolean |
3437 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3438 | { |
3439 | BuildOp *op; | |
3440 | symbolS *sym; | |
3441 | ||
60242db2 | 3442 | tinsn_init (targ); |
b224e962 BW |
3443 | targ->debug_line = insn->debug_line; |
3444 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3445 | switch (bi->typ) |
3446 | { | |
3447 | case INSTR_INSTR: | |
3448 | op = bi->ops; | |
3449 | targ->opcode = bi->opcode; | |
3450 | targ->insn_type = ITYPE_INSN; | |
3451 | targ->is_specific_opcode = FALSE; | |
3452 | ||
3453 | for (; op != NULL; op = op->next) | |
3454 | { | |
3455 | int op_num = op->op_num; | |
3456 | int op_data = op->op_data; | |
3457 | ||
9c2799c2 | 3458 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3459 | |
3460 | if (targ->ntok <= op_num) | |
3461 | targ->ntok = op_num + 1; | |
3462 | ||
3463 | switch (op->typ) | |
3464 | { | |
3465 | case OP_CONSTANT: | |
3466 | set_expr_const (&targ->tok[op_num], op_data); | |
3467 | break; | |
3468 | case OP_OPERAND: | |
9c2799c2 | 3469 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3470 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3471 | break; | |
19e8f41a BW |
3472 | case OP_FREEREG: |
3473 | if (insn->extra_arg.X_op != O_register) | |
3474 | return FALSE; | |
3475 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3476 | break; | |
e0001a05 NC |
3477 | case OP_LITERAL: |
3478 | sym = get_special_literal_symbol (); | |
3479 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3480 | if (insn->tok[op_data].X_op == O_tlsfunc |
3481 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3482 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3483 | break; |
3484 | case OP_LABEL: | |
3485 | sym = get_special_label_symbol (); | |
3486 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3487 | break; | |
43cd72b9 BW |
3488 | case OP_OPERAND_HI16U: |
3489 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3490 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3491 | if (expr_is_const (&insn->tok[op_data])) |
3492 | { | |
3493 | long val; | |
3494 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3495 | val = xg_apply_userdef_op_fn (op->typ, | |
3496 | targ->tok[op_num]. | |
3497 | X_add_number); | |
3498 | targ->tok[op_num].X_add_number = val; | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | /* For const16 we can create relocations for these. */ | |
3503 | if (targ->opcode == XTENSA_UNDEFINED | |
3504 | || (targ->opcode != xtensa_const16_opcode)) | |
3505 | return FALSE; | |
9c2799c2 | 3506 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3507 | /* Need to build a O_lo16 or O_hi16. */ |
3508 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3509 | if (targ->tok[op_num].X_op == O_symbol) | |
3510 | { | |
3511 | if (op->typ == OP_OPERAND_HI16U) | |
3512 | targ->tok[op_num].X_op = O_hi16; | |
3513 | else if (op->typ == OP_OPERAND_LOW16U) | |
3514 | targ->tok[op_num].X_op = O_lo16; | |
3515 | else | |
3516 | return FALSE; | |
3517 | } | |
3518 | } | |
3519 | break; | |
e0001a05 NC |
3520 | default: |
3521 | /* currently handles: | |
3522 | OP_OPERAND_LOW8 | |
3523 | OP_OPERAND_HI24S | |
3524 | OP_OPERAND_F32MINUS */ | |
3525 | if (xg_has_userdef_op_fn (op->typ)) | |
3526 | { | |
9c2799c2 | 3527 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3528 | if (expr_is_const (&insn->tok[op_data])) |
3529 | { | |
3530 | long val; | |
3531 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3532 | val = xg_apply_userdef_op_fn (op->typ, | |
3533 | targ->tok[op_num]. | |
3534 | X_add_number); | |
3535 | targ->tok[op_num].X_add_number = val; | |
3536 | } | |
3537 | else | |
3538 | return FALSE; /* We cannot use a relocation for this. */ | |
3539 | break; | |
3540 | } | |
9c2799c2 | 3541 | gas_assert (0); |
e0001a05 NC |
3542 | break; |
3543 | } | |
3544 | } | |
3545 | break; | |
3546 | ||
3547 | case INSTR_LITERAL_DEF: | |
3548 | op = bi->ops; | |
3549 | targ->opcode = XTENSA_UNDEFINED; | |
3550 | targ->insn_type = ITYPE_LITERAL; | |
3551 | targ->is_specific_opcode = FALSE; | |
3552 | for (; op != NULL; op = op->next) | |
3553 | { | |
3554 | int op_num = op->op_num; | |
3555 | int op_data = op->op_data; | |
9c2799c2 | 3556 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3557 | |
3558 | if (targ->ntok <= op_num) | |
3559 | targ->ntok = op_num + 1; | |
3560 | ||
3561 | switch (op->typ) | |
3562 | { | |
3563 | case OP_OPERAND: | |
9c2799c2 | 3564 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3565 | /* We can only pass resolvable literals through. */ |
3566 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3567 | return FALSE; | |
e0001a05 NC |
3568 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3569 | break; | |
3570 | case OP_LITERAL: | |
3571 | case OP_CONSTANT: | |
3572 | case OP_LABEL: | |
3573 | default: | |
9c2799c2 | 3574 | gas_assert (0); |
e0001a05 NC |
3575 | break; |
3576 | } | |
3577 | } | |
3578 | break; | |
3579 | ||
3580 | case INSTR_LABEL_DEF: | |
3581 | op = bi->ops; | |
3582 | targ->opcode = XTENSA_UNDEFINED; | |
3583 | targ->insn_type = ITYPE_LABEL; | |
3584 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3585 | /* Literal with no ops is a label? */ |
9c2799c2 | 3586 | gas_assert (op == NULL); |
e0001a05 NC |
3587 | break; |
3588 | ||
3589 | default: | |
9c2799c2 | 3590 | gas_assert (0); |
e0001a05 NC |
3591 | } |
3592 | ||
3593 | return TRUE; | |
3594 | } | |
3595 | ||
3596 | ||
43cd72b9 | 3597 | /* Return TRUE on success. */ |
e0001a05 | 3598 | |
7fa3d080 BW |
3599 | static bfd_boolean |
3600 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3601 | { |
3602 | for (; bi != NULL; bi = bi->next) | |
3603 | { | |
3604 | TInsn *next_insn = istack_push_space (istack); | |
3605 | ||
3606 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3607 | return FALSE; | |
3608 | } | |
3609 | return TRUE; | |
3610 | } | |
3611 | ||
3612 | ||
43cd72b9 | 3613 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3614 | |
7fa3d080 BW |
3615 | static bfd_boolean |
3616 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3617 | { |
3618 | int stack_size = istack->ninsn; | |
3619 | int steps_taken = 0; | |
43cd72b9 | 3620 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3621 | TransitionList *l; |
3622 | ||
9c2799c2 NC |
3623 | gas_assert (insn->insn_type == ITYPE_INSN); |
3624 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3625 | |
3626 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3627 | { | |
3628 | TransitionRule *rule = l->rule; | |
3629 | ||
3630 | if (xg_instruction_matches_rule (insn, rule)) | |
3631 | { | |
3632 | if (lateral_steps == steps_taken) | |
3633 | { | |
3634 | int i; | |
3635 | ||
3636 | /* This is it. Expand the rule to the stack. */ | |
3637 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3638 | return FALSE; | |
3639 | ||
3640 | /* Check to see if it fits. */ | |
3641 | for (i = stack_size; i < istack->ninsn; i++) | |
3642 | { | |
91d6fa6a | 3643 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3644 | |
91d6fa6a NC |
3645 | if (tinsn->insn_type == ITYPE_INSN |
3646 | && !tinsn_has_symbolic_operands (tinsn) | |
3647 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3648 | { |
3649 | istack->ninsn = stack_size; | |
3650 | return FALSE; | |
3651 | } | |
3652 | } | |
3653 | return TRUE; | |
3654 | } | |
3655 | steps_taken++; | |
3656 | } | |
3657 | } | |
3658 | return FALSE; | |
3659 | } | |
3660 | ||
43cd72b9 | 3661 | \f |
43cd72b9 | 3662 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3663 | Return the number of steps taken. |
3664 | ||
3665 | For relaxation to correctly terminate, every relaxation chain must | |
3666 | terminate in one of two ways: | |
3667 | ||
3668 | 1. If the chain from one instruction to the next consists entirely of | |
3669 | single instructions, then the chain *must* handle all possible | |
3670 | immediates without failing. It must not ever fail because an | |
3671 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3672 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3673 | immediate larger than 32 bits, so it satisfies this condition. | |
3674 | Single instruction relaxation chains are as defined by | |
3675 | xg_is_single_relaxable_instruction. | |
3676 | ||
3677 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3678 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3679 | ||
3680 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3681 | -- in particular when the last two instructions have the same single | |
3682 | size. But nevertheless, you should guarantee the above two conditions. | |
3683 | ||
3684 | We could fix this so that single-instruction expansions correctly | |
3685 | terminate when they can't handle the range, but the error messages are | |
3686 | worse, and it actually turns out that in every case but one (18-bit wide | |
3687 | branches), you need a multi-instruction expansion to get the full range | |
3688 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3689 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3690 | |
7fa3d080 BW |
3691 | static int |
3692 | xg_assembly_relax (IStack *istack, | |
3693 | TInsn *insn, | |
3694 | segT pc_seg, | |
3695 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3696 | offsetT pc_offset, /* offset in fragment */ | |
3697 | int min_steps, /* minimum conversion steps */ | |
3698 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3699 | { |
3700 | int steps_taken = 0; | |
3701 | ||
b81bf389 BW |
3702 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3703 | This may go through a couple of stages of single instruction | |
3704 | transformations before we get there. */ | |
e0001a05 NC |
3705 | |
3706 | TInsn single_target; | |
3707 | TInsn current_insn; | |
3708 | int lateral_steps = 0; | |
3709 | int istack_size = istack->ninsn; | |
3710 | ||
3711 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3712 | && steps_taken >= min_steps) | |
3713 | { | |
3714 | istack_push (istack, insn); | |
3715 | return steps_taken; | |
3716 | } | |
43cd72b9 | 3717 | current_insn = *insn; |
e0001a05 | 3718 | |
7c834684 | 3719 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3720 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3721 | { |
21af2bbd | 3722 | steps_taken++; |
e0001a05 NC |
3723 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3724 | stretch)) | |
3725 | { | |
e0001a05 NC |
3726 | if (steps_taken >= min_steps) |
3727 | { | |
3728 | istack_push (istack, &single_target); | |
3729 | return steps_taken; | |
3730 | } | |
3731 | } | |
43cd72b9 | 3732 | current_insn = single_target; |
e0001a05 NC |
3733 | } |
3734 | ||
3735 | /* Now check for a multi-instruction expansion. */ | |
3736 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3737 | { | |
3738 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3739 | stretch)) | |
3740 | { | |
3741 | if (steps_taken >= min_steps) | |
3742 | { | |
3743 | istack_push (istack, ¤t_insn); | |
3744 | return steps_taken; | |
3745 | } | |
3746 | } | |
3747 | steps_taken++; | |
3748 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3749 | { | |
3750 | if (steps_taken >= min_steps) | |
3751 | return steps_taken; | |
3752 | } | |
3753 | lateral_steps++; | |
3754 | istack->ninsn = istack_size; | |
3755 | } | |
3756 | ||
3757 | /* It's not going to work -- use the original. */ | |
3758 | istack_push (istack, insn); | |
3759 | return steps_taken; | |
3760 | } | |
3761 | ||
3762 | ||
7fa3d080 BW |
3763 | static void |
3764 | xg_finish_frag (char *last_insn, | |
3765 | enum xtensa_relax_statesE frag_state, | |
3766 | enum xtensa_relax_statesE slot0_state, | |
3767 | int max_growth, | |
3768 | bfd_boolean is_insn) | |
e0001a05 NC |
3769 | { |
3770 | /* Finish off this fragment so that it has at LEAST the desired | |
3771 | max_growth. If it doesn't fit in this fragment, close this one | |
3772 | and start a new one. In either case, return a pointer to the | |
3773 | beginning of the growth area. */ | |
3774 | ||
3775 | fragS *old_frag; | |
43cd72b9 | 3776 | |
542f8b94 | 3777 | frag_grow (max_growth); |
e0001a05 NC |
3778 | old_frag = frag_now; |
3779 | ||
3780 | frag_now->fr_opcode = last_insn; | |
3781 | if (is_insn) | |
3782 | frag_now->tc_frag_data.is_insn = TRUE; | |
3783 | ||
3784 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3785 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3786 | ||
3787 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3788 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3789 | |
3790 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3791 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3792 | } |
3793 | ||
3794 | ||
7fa3d080 BW |
3795 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3796 | ||
3797 | static bfd_boolean | |
3798 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3799 | { | |
3800 | if (fragP == NULL) | |
3801 | return FALSE; | |
3802 | ||
3803 | for (; fragP; fragP = fragP->fr_next) | |
3804 | { | |
3805 | if (fragP == target) | |
3806 | return TRUE; | |
3807 | if (fragP->fr_fix != 0) | |
3808 | return FALSE; | |
3809 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3810 | return FALSE; | |
3811 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3812 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3813 | return FALSE; | |
3814 | if (fragP->fr_type == rs_space) | |
3815 | return FALSE; | |
3816 | } | |
3817 | return FALSE; | |
3818 | } | |
3819 | ||
3820 | ||
e0001a05 | 3821 | static bfd_boolean |
7fa3d080 | 3822 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3823 | { |
3824 | xtensa_isa isa = xtensa_default_isa; | |
3825 | int i; | |
43cd72b9 | 3826 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3827 | int target_op = -1; |
3828 | symbolS *sym; | |
3829 | fragS *target_frag; | |
3830 | ||
64b607e6 BW |
3831 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3832 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3833 | return FALSE; |
3834 | ||
3835 | for (i = 0; i < num_ops; i++) | |
3836 | { | |
43cd72b9 | 3837 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3838 | { |
3839 | target_op = i; | |
3840 | break; | |
3841 | } | |
3842 | } | |
3843 | if (target_op == -1) | |
3844 | return FALSE; | |
3845 | ||
3846 | if (insn->ntok <= target_op) | |
3847 | return FALSE; | |
3848 | ||
3849 | if (insn->tok[target_op].X_op != O_symbol) | |
3850 | return FALSE; | |
3851 | ||
3852 | sym = insn->tok[target_op].X_add_symbol; | |
3853 | if (sym == NULL) | |
3854 | return FALSE; | |
3855 | ||
3856 | if (insn->tok[target_op].X_add_number != 0) | |
3857 | return FALSE; | |
3858 | ||
3859 | target_frag = symbol_get_frag (sym); | |
3860 | if (target_frag == NULL) | |
3861 | return FALSE; | |
3862 | ||
c138bc38 | 3863 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3864 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3865 | return TRUE; | |
3866 | ||
3867 | return FALSE; | |
3868 | } | |
3869 | ||
3870 | ||
3871 | static void | |
7fa3d080 | 3872 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3873 | { |
3874 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3875 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3876 | |
7fa3d080 BW |
3877 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3878 | { | |
3879 | int i = 1; | |
3880 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3881 | && insn->tok[i].X_op == O_symbol) | |
3882 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3883 | return; | |
3884 | } | |
e0001a05 | 3885 | |
7fa3d080 BW |
3886 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3887 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3888 | { |
7fa3d080 BW |
3889 | int i; |
3890 | ||
3891 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3892 | { | |
3893 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3894 | && insn->tok[i].X_op == O_symbol) | |
3895 | { | |
3896 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3897 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3898 | if (S_IS_DEFINED (sym)) | |
3899 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3900 | } | |
3901 | } | |
e0001a05 | 3902 | } |
e0001a05 NC |
3903 | } |
3904 | ||
3905 | ||
43cd72b9 | 3906 | /* Return FALSE if no error. */ |
e0001a05 | 3907 | |
7fa3d080 BW |
3908 | static bfd_boolean |
3909 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3910 | { |
3911 | int num_ops = 0; | |
3912 | BuildOp *b_op; | |
3913 | ||
3914 | switch (instr_spec->typ) | |
3915 | { | |
3916 | case INSTR_INSTR: | |
3917 | new_insn->insn_type = ITYPE_INSN; | |
3918 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3919 | break; |
3920 | case INSTR_LITERAL_DEF: | |
3921 | new_insn->insn_type = ITYPE_LITERAL; | |
3922 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3923 | break; |
3924 | case INSTR_LABEL_DEF: | |
b224e962 | 3925 | abort (); |
e0001a05 | 3926 | } |
b224e962 BW |
3927 | new_insn->is_specific_opcode = FALSE; |
3928 | new_insn->debug_line = old_insn->debug_line; | |
3929 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3930 | |
3931 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3932 | { | |
3933 | expressionS *exp; | |
3934 | const expressionS *src_exp; | |
3935 | ||
3936 | num_ops++; | |
3937 | switch (b_op->typ) | |
3938 | { | |
3939 | case OP_CONSTANT: | |
3940 | /* The expression must be the constant. */ | |
9c2799c2 | 3941 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3942 | exp = &new_insn->tok[b_op->op_num]; |
3943 | set_expr_const (exp, b_op->op_data); | |
3944 | break; | |
3945 | ||
3946 | case OP_OPERAND: | |
9c2799c2 NC |
3947 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3948 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3949 | src_exp = &old_insn->tok[b_op->op_data]; |
3950 | exp = &new_insn->tok[b_op->op_num]; | |
3951 | copy_expr (exp, src_exp); | |
3952 | break; | |
3953 | ||
3954 | case OP_LITERAL: | |
3955 | case OP_LABEL: | |
3956 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 3957 | gas_assert (0); |
e0001a05 NC |
3958 | |
3959 | default: | |
3960 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 3961 | gas_assert (0); |
e0001a05 NC |
3962 | } |
3963 | } | |
3964 | ||
3965 | new_insn->ntok = num_ops; | |
3966 | return FALSE; | |
3967 | } | |
3968 | ||
3969 | ||
43cd72b9 | 3970 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3971 | |
7fa3d080 BW |
3972 | static bfd_boolean |
3973 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3974 | { |
43cd72b9 | 3975 | TransitionRule *rule; |
e0001a05 | 3976 | BuildInstr *insn_spec; |
43cd72b9 BW |
3977 | |
3978 | if (old_insn->is_specific_opcode || !density_supported) | |
3979 | return FALSE; | |
3980 | ||
3981 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3982 | if (rule == NULL) |
3983 | return FALSE; | |
3984 | ||
3985 | insn_spec = rule->to_instr; | |
3986 | /* There should only be one. */ | |
9c2799c2 NC |
3987 | gas_assert (insn_spec != NULL); |
3988 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
3989 | if (insn_spec->next != NULL) |
3990 | return FALSE; | |
3991 | ||
3992 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3993 | ||
3994 | return TRUE; | |
3995 | } | |
3996 | ||
3997 | ||
3998 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3999 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
4000 | tokens into the stack or relax it and place multiple |
4001 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
4002 | |
4003 | static bfd_boolean | |
7fa3d080 | 4004 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
4005 | { |
4006 | int noperands; | |
4007 | TInsn new_insn; | |
7c834684 BW |
4008 | bfd_boolean do_expand; |
4009 | ||
60242db2 | 4010 | tinsn_init (&new_insn); |
e0001a05 | 4011 | |
43cd72b9 BW |
4012 | /* Narrow it if we can. xg_simplify_insn now does all the |
4013 | appropriate checking (e.g., for the density option). */ | |
4014 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
4015 | orig_insn = &new_insn; | |
e0001a05 | 4016 | |
43cd72b9 BW |
4017 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
4018 | orig_insn->opcode); | |
e0001a05 NC |
4019 | if (orig_insn->ntok < noperands) |
4020 | { | |
992a06ee AM |
4021 | as_bad (ngettext ("found %d operand for '%s': Expected %d", |
4022 | "found %d operands for '%s': Expected %d", | |
4023 | orig_insn->ntok), | |
e0001a05 NC |
4024 | orig_insn->ntok, |
4025 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4026 | noperands); | |
4027 | return TRUE; | |
4028 | } | |
4029 | if (orig_insn->ntok > noperands) | |
992a06ee AM |
4030 | as_warn (ngettext ("found %d operand for '%s': Expected %d", |
4031 | "found %d operands for '%s': Expected %d", | |
4032 | orig_insn->ntok), | |
e0001a05 NC |
4033 | orig_insn->ntok, |
4034 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4035 | noperands); | |
4036 | ||
43cd72b9 | 4037 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 4038 | are too many, just cut out the extras here. */ |
e0001a05 NC |
4039 | orig_insn->ntok = noperands; |
4040 | ||
e0001a05 NC |
4041 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
4042 | return TRUE; | |
4043 | ||
d12f9798 BW |
4044 | /* Special case for extui opcode which has constraints not handled |
4045 | by the ordinary operand encoding checks. The number of operands | |
4046 | and related syntax issues have already been checked. */ | |
4047 | if (orig_insn->opcode == xtensa_extui_opcode) | |
4048 | { | |
4049 | int shiftimm = orig_insn->tok[2].X_add_number; | |
4050 | int maskimm = orig_insn->tok[3].X_add_number; | |
4051 | if (shiftimm + maskimm > 32) | |
4052 | { | |
4053 | as_bad (_("immediate operands sum to greater than 32")); | |
4054 | return TRUE; | |
4055 | } | |
4056 | } | |
4057 | ||
7c834684 BW |
4058 | /* If the instruction will definitely need to be relaxed, it is better |
4059 | to expand it now for better scheduling. Decide whether to expand | |
4060 | now.... */ | |
4061 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
4062 | ||
4063 | /* Calls should be expanded to longcalls only in the backend relaxation | |
4064 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
4065 | adjacent. */ | |
4066 | if (is_direct_call_opcode (orig_insn->opcode)) | |
4067 | do_expand = FALSE; | |
e0001a05 NC |
4068 | |
4069 | if (tinsn_has_symbolic_operands (orig_insn)) | |
4070 | { | |
7c834684 BW |
4071 | /* The values of symbolic operands are not known yet, so only expand |
4072 | now if an operand is "complex" (e.g., difference of symbols) and | |
4073 | will have to be stored as a literal regardless of the value. */ | |
4074 | if (!tinsn_has_complex_operands (orig_insn)) | |
4075 | do_expand = FALSE; | |
e0001a05 | 4076 | } |
7c834684 BW |
4077 | else if (xg_immeds_fit (orig_insn)) |
4078 | do_expand = FALSE; | |
4079 | ||
4080 | if (do_expand) | |
4081 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4082 | else |
7c834684 | 4083 | istack_push (istack, orig_insn); |
e0001a05 | 4084 | |
e0001a05 NC |
4085 | return FALSE; |
4086 | } | |
4087 | ||
4088 | ||
7fa3d080 | 4089 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4090 | or the name is .gnu.linkonce.*. */ |
4091 | ||
4092 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4093 | |
4094 | static bfd_boolean | |
4095 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4096 | { | |
4097 | flagword flags, link_once_flags; | |
4098 | ||
4099 | flags = bfd_get_section_flags (abfd, sec); | |
4100 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4101 | ||
4102 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4103 | if (!link_once_flags |
4104 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4105 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4106 | |
7fa3d080 BW |
4107 | return (link_once_flags != 0); |
4108 | } | |
4109 | ||
4110 | ||
4111 | static void | |
4112 | xtensa_add_literal_sym (symbolS *sym) | |
4113 | { | |
4114 | sym_list *l; | |
4115 | ||
325801bd | 4116 | l = XNEW (sym_list); |
7fa3d080 BW |
4117 | l->sym = sym; |
4118 | l->next = literal_syms; | |
4119 | literal_syms = l; | |
4120 | } | |
4121 | ||
4122 | ||
4123 | static symbolS * | |
4124 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4125 | { | |
4126 | static int lit_num = 0; | |
4127 | static char name[256]; | |
4128 | symbolS *symbolP; | |
4129 | ||
4130 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4131 | ||
4132 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4133 | be careful to make sure that if it is used in a relocation that the | |
4134 | symbol will be in the output file. */ | |
4135 | if (get_is_linkonce_section (stdoutput, sec)) | |
4136 | { | |
4137 | symbolP = symbol_new (name, sec, 0, frag); | |
4138 | S_CLEAR_EXTERNAL (symbolP); | |
4139 | /* symbolP->local = 1; */ | |
4140 | } | |
4141 | else | |
4142 | symbolP = symbol_new (name, sec, 0, frag); | |
4143 | ||
4144 | xtensa_add_literal_sym (symbolP); | |
4145 | ||
7fa3d080 BW |
4146 | lit_num++; |
4147 | return symbolP; | |
4148 | } | |
4149 | ||
4150 | ||
e0001a05 NC |
4151 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4152 | ||
7fa3d080 BW |
4153 | static symbolS * |
4154 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4155 | { |
4156 | emit_state state; | |
4157 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4158 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4159 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4160 | char *p; |
e0001a05 NC |
4161 | |
4162 | /* size = 4 for L32R. It could easily be larger when we move to | |
4163 | larger constants. Add a parameter later. */ | |
4164 | offsetT litsize = 4; | |
4165 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4166 | expressionS saved_loc; | |
43cd72b9 BW |
4167 | expressionS * emit_val; |
4168 | ||
e0001a05 NC |
4169 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4170 | ||
9c2799c2 NC |
4171 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4172 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4173 | |
4174 | xtensa_switch_to_literal_fragment (&state); | |
4175 | ||
43cd72b9 BW |
4176 | emit_val = &insn->tok[0]; |
4177 | if (emit_val->X_op == O_big) | |
4178 | { | |
4179 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4180 | if (size > litsize) | |
4181 | { | |
4182 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4183 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4184 | _("invalid immediate")); |
4185 | xtensa_restore_emit_state (&state); | |
4186 | return NULL; | |
4187 | } | |
4188 | } | |
4189 | ||
e0001a05 NC |
4190 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4191 | literals done with this function have a frag to themselves. That's | |
4192 | important for the way text section literals work. */ | |
4193 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4194 | record_alignment (now_seg, litalign); |
e0001a05 | 4195 | |
bbdd25a8 | 4196 | switch (emit_val->X_op) |
43cd72b9 | 4197 | { |
1bbb5f21 BW |
4198 | case O_pcrel: |
4199 | pcrel = TRUE; | |
4200 | /* fall through */ | |
bbdd25a8 | 4201 | case O_pltrel: |
28dbbc02 BW |
4202 | case O_tlsfunc: |
4203 | case O_tlsarg: | |
4204 | case O_tpoff: | |
4205 | case O_dtpoff: | |
bbdd25a8 | 4206 | p = frag_more (litsize); |
43cd72b9 | 4207 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4208 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4209 | if (emit_val->X_add_symbol) |
4210 | emit_val->X_op = O_symbol; | |
4211 | else | |
4212 | emit_val->X_op = O_constant; | |
4213 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4214 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4215 | break; |
4216 | ||
4217 | default: | |
4218 | emit_expr (emit_val, litsize); | |
4219 | break; | |
43cd72b9 | 4220 | } |
e0001a05 | 4221 | |
9c2799c2 | 4222 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4223 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4224 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4225 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4226 | |
4227 | /* Go back. */ | |
4228 | xtensa_restore_emit_state (&state); | |
4229 | return lit_sym; | |
4230 | } | |
4231 | ||
4232 | ||
4233 | static void | |
7fa3d080 | 4234 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4235 | { |
4236 | emit_state state; | |
43cd72b9 | 4237 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4238 | takes effect if something is placed here. */ |
4239 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4240 | fragS *lit_saved_frag; | |
4241 | ||
9c2799c2 | 4242 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4243 | |
4244 | xtensa_switch_to_literal_fragment (&state); | |
4245 | ||
4246 | /* Force a 4-byte align here. */ | |
4247 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4248 | record_alignment (now_seg, litalign); |
e0001a05 | 4249 | |
542f8b94 | 4250 | frag_grow (size); |
e0001a05 NC |
4251 | |
4252 | lit_saved_frag = frag_now; | |
4253 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4254 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4255 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4256 | |
4257 | /* Go back. */ | |
4258 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4259 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4260 | } |
4261 | ||
4262 | ||
e0001a05 | 4263 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4264 | Return TRUE on success. */ |
e0001a05 | 4265 | |
7fa3d080 BW |
4266 | static bfd_boolean |
4267 | xg_add_opcode_fix (TInsn *tinsn, | |
4268 | int opnum, | |
4269 | xtensa_format fmt, | |
4270 | int slot, | |
91d6fa6a | 4271 | expressionS *exp, |
7fa3d080 BW |
4272 | fragS *fragP, |
4273 | offsetT offset) | |
43cd72b9 BW |
4274 | { |
4275 | xtensa_opcode opcode = tinsn->opcode; | |
4276 | bfd_reloc_code_real_type reloc; | |
4277 | reloc_howto_type *howto; | |
4278 | int fmt_length; | |
e0001a05 NC |
4279 | fixS *the_fix; |
4280 | ||
43cd72b9 BW |
4281 | reloc = BFD_RELOC_NONE; |
4282 | ||
4283 | /* First try the special cases for "alternate" relocs. */ | |
4284 | if (opcode == xtensa_l32r_opcode) | |
4285 | { | |
4286 | if (fragP->tc_frag_data.use_absolute_literals) | |
4287 | reloc = encode_alt_reloc (slot); | |
4288 | } | |
4289 | else if (opcode == xtensa_const16_opcode) | |
4290 | { | |
91d6fa6a | 4291 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4292 | { |
4293 | reloc = encode_reloc (slot); | |
91d6fa6a | 4294 | exp->X_op = O_symbol; |
43cd72b9 | 4295 | } |
91d6fa6a | 4296 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4297 | { |
4298 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4299 | exp->X_op = O_symbol; |
43cd72b9 BW |
4300 | } |
4301 | } | |
4302 | ||
4303 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4304 | { |
43cd72b9 | 4305 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4306 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4307 | return FALSE; |
4308 | } | |
4309 | ||
43cd72b9 BW |
4310 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4311 | into the symbol table where the generic portions of the assembler | |
4312 | won't know what to do with them. */ | |
91d6fa6a | 4313 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4314 | { |
4315 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4316 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4317 | return FALSE; |
4318 | } | |
4319 | ||
4320 | /* Next try the generic relocs. */ | |
4321 | if (reloc == BFD_RELOC_NONE) | |
4322 | reloc = encode_reloc (slot); | |
4323 | if (reloc == BFD_RELOC_NONE) | |
4324 | { | |
4325 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4326 | return FALSE; | |
4327 | } | |
e0001a05 | 4328 | |
43cd72b9 | 4329 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4330 | if (!howto) |
4331 | { | |
43cd72b9 | 4332 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4333 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4334 | return FALSE; | |
4335 | } | |
4336 | ||
43cd72b9 | 4337 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4338 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4339 | howto->pc_relative, reloc); |
d9740523 | 4340 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4341 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4342 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4343 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4344 | |
7fa3d080 BW |
4345 | return TRUE; |
4346 | } | |
4347 | ||
4348 | ||
4349 | static bfd_boolean | |
4350 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4351 | char *buf, |
4352 | fragS *fragP, | |
4353 | offsetT offset, | |
4354 | bfd_boolean build_fix) | |
4355 | { | |
4356 | static xtensa_insnbuf insnbuf = NULL; | |
4357 | bfd_boolean has_symbolic_immed = FALSE; | |
4358 | bfd_boolean ok = TRUE; | |
b2d179be | 4359 | |
7fa3d080 BW |
4360 | if (!insnbuf) |
4361 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4362 | ||
4363 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4364 | if (has_symbolic_immed && build_fix) | |
4365 | { | |
4366 | /* Add a fixup. */ | |
b2d179be BW |
4367 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4368 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4369 | int opnum = get_relaxable_immed (tinsn->opcode); |
4370 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4371 | |
b2d179be | 4372 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4373 | ok = FALSE; |
4374 | } | |
4375 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4376 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4377 | (unsigned char *) buf, 0); | |
7fa3d080 | 4378 | return ok; |
e0001a05 NC |
4379 | } |
4380 | ||
4381 | ||
7fa3d080 BW |
4382 | static void |
4383 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4384 | { |
4385 | symbolS *sym = get_special_literal_symbol (); | |
4386 | int i; | |
4387 | if (lit_sym == 0) | |
4388 | return; | |
9c2799c2 | 4389 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4390 | for (i = 0; i < insn->ntok; i++) |
4391 | if (insn->tok[i].X_add_symbol == sym) | |
4392 | insn->tok[i].X_add_symbol = lit_sym; | |
4393 | ||
4394 | } | |
4395 | ||
4396 | ||
7fa3d080 BW |
4397 | static void |
4398 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4399 | { |
4400 | symbolS *sym = get_special_label_symbol (); | |
4401 | int i; | |
e0001a05 NC |
4402 | for (i = 0; i < insn->ntok; i++) |
4403 | if (insn->tok[i].X_add_symbol == sym) | |
4404 | insn->tok[i].X_add_symbol = label_sym; | |
4405 | ||
4406 | } | |
4407 | ||
4408 | ||
43cd72b9 | 4409 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4410 | integer register. */ |
4411 | ||
4412 | static bfd_boolean | |
7fa3d080 | 4413 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4414 | { |
4415 | int i; | |
4416 | int num_ops; | |
4417 | xtensa_isa isa = xtensa_default_isa; | |
4418 | ||
43cd72b9 | 4419 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4420 | |
4421 | for (i = 0; i < num_ops; i++) | |
4422 | { | |
43cd72b9 BW |
4423 | char inout; |
4424 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4425 | if ((inout == 'o' || inout == 'm') | |
4426 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4427 | { |
43cd72b9 BW |
4428 | xtensa_regfile opnd_rf = |
4429 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4430 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4431 | { |
4432 | if ((insn->tok[i].X_op == O_register) | |
4433 | && (insn->tok[i].X_add_number == regnum)) | |
4434 | return TRUE; | |
4435 | } | |
4436 | } | |
4437 | } | |
4438 | return FALSE; | |
4439 | } | |
4440 | ||
4441 | ||
4442 | static bfd_boolean | |
7fa3d080 | 4443 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4444 | { |
4445 | xtensa_opcode opcode = tinsn->opcode; | |
4446 | ||
4447 | if (opcode == XTENSA_UNDEFINED) | |
4448 | return FALSE; | |
4449 | ||
4450 | if (opcode == xtensa_call0_opcode | |
4451 | || opcode == xtensa_callx0_opcode | |
4452 | || opcode == xtensa_call4_opcode | |
4453 | || opcode == xtensa_callx4_opcode | |
4454 | || opcode == xtensa_call8_opcode | |
4455 | || opcode == xtensa_callx8_opcode | |
4456 | || opcode == xtensa_call12_opcode | |
4457 | || opcode == xtensa_callx12_opcode | |
4458 | || opcode == xtensa_isync_opcode | |
4459 | || opcode == xtensa_ret_opcode | |
4460 | || opcode == xtensa_ret_n_opcode | |
4461 | || opcode == xtensa_retw_opcode | |
4462 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4463 | || opcode == xtensa_waiti_opcode |
4464 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4465 | return TRUE; |
c138bc38 | 4466 | |
e0001a05 NC |
4467 | return FALSE; |
4468 | } | |
4469 | ||
4470 | ||
4471 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4472 | This allows the debugger to add unaligned labels. | |
4473 | Also, the assembler generates stabs labels that need | |
4474 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4475 | ||
7fa3d080 BW |
4476 | static bfd_boolean |
4477 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4478 | { |
4479 | const char *name = S_GET_NAME (sym); | |
4480 | static size_t fake_size = 0; | |
4481 | ||
4482 | if (name | |
4483 | && name[0] == '.' | |
4484 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4485 | return TRUE; | |
4486 | ||
4487 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4488 | if (fake_size == 0) | |
4489 | fake_size = strlen (FAKE_LABEL_NAME); | |
4490 | ||
43cd72b9 | 4491 | if (name |
e0001a05 NC |
4492 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4493 | && (name[fake_size] == 'F' | |
4494 | || name[fake_size] == 'L' | |
4495 | || (name[fake_size] == 'e' | |
4496 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4497 | return TRUE; | |
4498 | ||
4499 | return FALSE; | |
4500 | } | |
4501 | ||
4502 | ||
7fa3d080 BW |
4503 | static fragS * |
4504 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4505 | { |
4506 | fragS *next_fragP = fragP->fr_next; | |
4507 | ||
c138bc38 | 4508 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4509 | So we have to skip until we find something legit. */ |
4510 | while (next_fragP && next_fragP->fr_fix == 0) | |
4511 | next_fragP = next_fragP->fr_next; | |
4512 | ||
4513 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4514 | return NULL; | |
4515 | ||
4516 | return next_fragP; | |
4517 | } | |
4518 | ||
4519 | ||
43cd72b9 | 4520 | static bfd_boolean |
7fa3d080 | 4521 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4522 | { |
4523 | xtensa_opcode out_opcode; | |
4524 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4525 | ||
4526 | if (next_fragP == NULL) | |
4527 | return FALSE; | |
4528 | ||
4529 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4530 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4531 | { | |
4532 | *opcode = out_opcode; | |
4533 | return TRUE; | |
4534 | } | |
4535 | return FALSE; | |
4536 | } | |
4537 | ||
4538 | ||
4539 | static int | |
7fa3d080 | 4540 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4541 | { |
e0001a05 NC |
4542 | static xtensa_insnbuf insnbuf = NULL; |
4543 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4544 | xtensa_format fmt; |
c138bc38 | 4545 | int fmt_size; |
e0001a05 NC |
4546 | |
4547 | if (!insnbuf) | |
4548 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4549 | ||
43cd72b9 BW |
4550 | if (fragP == NULL) |
4551 | return XTENSA_UNDEFINED; | |
4552 | ||
d77b99c9 BW |
4553 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4554 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4555 | |
4556 | fmt = xtensa_format_decode (isa, insnbuf); | |
4557 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4558 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4559 | fmt_size = xtensa_format_length (isa, fmt); |
4560 | ||
4561 | /* If the next format won't be changing due to relaxation, just | |
4562 | return the length of the first format. */ | |
4563 | if (fragP->fr_opcode != fragP->fr_literal) | |
4564 | return fmt_size; | |
4565 | ||
c138bc38 | 4566 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4567 | multi-slot instruction, we will return the more conservative |
4568 | number. This works because alignment on bigger instructions | |
4569 | is more restrictive than alignment on smaller instructions. | |
4570 | This is more conservative than we would like, but it happens | |
4571 | infrequently. */ | |
4572 | ||
4573 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4574 | return fmt_size; | |
4575 | ||
4576 | /* If we aren't doing one of our own relaxations or it isn't | |
4577 | slot-based, then the insn size won't change. */ | |
4578 | if (fragP->fr_type != rs_machine_dependent) | |
4579 | return fmt_size; | |
4580 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4581 | return fmt_size; | |
4582 | ||
4583 | /* If an instruction is about to grow, return the longer size. */ | |
4584 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4585 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4586 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4587 | { |
4588 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4589 | instruction in the relaxed version is of length 3. (The case | |
4590 | where we have to pull the instruction out of a FLIX bundle | |
4591 | is handled conservatively above.) However, frags with opcodes | |
4592 | that are expanding to wide branches end up having formats that | |
4593 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4594 | we can't tell directly what format the relaxer picked. This | |
4595 | is a wart in the design of the relaxer that should someday be | |
4596 | fixed, but would require major changes, or at least should | |
4597 | be accompanied by major changes to make use of that data. | |
4598 | ||
4599 | In any event, we can tell that we are expanding from a single-slot | |
19ef5f3d | 4600 | format to a wider one with the logic below. */ |
def13efb | 4601 | |
19ef5f3d SA |
4602 | int i; |
4603 | int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; | |
4604 | ||
4605 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) | |
4606 | { | |
4607 | if (relaxed_size == xtensa_format_length (isa, i)) | |
4608 | return relaxed_size; | |
4609 | } | |
4610 | ||
4611 | return 3; | |
def13efb | 4612 | } |
c138bc38 | 4613 | |
43cd72b9 BW |
4614 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4615 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4616 | |
43cd72b9 | 4617 | return fmt_size; |
e0001a05 NC |
4618 | } |
4619 | ||
4620 | ||
7fa3d080 BW |
4621 | static int |
4622 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4623 | { |
7fa3d080 BW |
4624 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4625 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4626 | } |
4627 | ||
4628 | ||
03aaa593 BW |
4629 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4630 | required two-byte instructions to be treated as three-byte instructions | |
4631 | for loop instruction alignment. This restriction was removed beginning | |
4632 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4633 | is that the first instruction of the loop must appear at an address that | |
4634 | does not cross a fetch boundary. */ | |
4635 | ||
4636 | static int | |
4637 | get_loop_align_size (int insn_size) | |
4638 | { | |
4639 | if (insn_size == XTENSA_UNDEFINED) | |
4640 | return xtensa_fetch_width; | |
4641 | ||
4642 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4643 | return 3; | |
4644 | ||
4645 | return insn_size; | |
4646 | } | |
4647 | ||
4648 | ||
e0001a05 NC |
4649 | /* If the next legit fragment is an end-of-loop marker, |
4650 | switch its state so it will instantiate a NOP. */ | |
4651 | ||
4652 | static void | |
1d19a770 | 4653 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4654 | { |
4655 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4656 | fragS *new_target = NULL; |
e0001a05 | 4657 | |
7b1cc377 | 4658 | if (align_targets) |
43cd72b9 BW |
4659 | { |
4660 | /* We are guaranteed there will be one of these... */ | |
4661 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4662 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4663 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4664 | next_fragP = next_fragP->fr_next; | |
4665 | ||
9c2799c2 | 4666 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4667 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4668 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4669 | ||
4670 | /* ...and one of these. */ | |
4671 | new_target = next_fragP->fr_next; | |
4672 | while (!(new_target->fr_type == rs_machine_dependent | |
4673 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4674 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4675 | new_target = new_target->fr_next; | |
4676 | ||
9c2799c2 | 4677 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4678 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4679 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4680 | } | |
43cd72b9 | 4681 | |
1d19a770 | 4682 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4683 | { |
1d19a770 BW |
4684 | if (next_fragP->fr_type == rs_machine_dependent |
4685 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4686 | { |
1d19a770 BW |
4687 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4688 | return; | |
e0001a05 | 4689 | } |
1d19a770 BW |
4690 | |
4691 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4692 | } |
4693 | } | |
4694 | ||
4695 | ||
4696 | static bfd_boolean | |
7fa3d080 | 4697 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4698 | { |
43cd72b9 | 4699 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4700 | so we have to skip until we find something legit. */ |
4701 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4702 | { | |
4703 | if (fragP->tc_frag_data.is_branch_target) | |
4704 | return TRUE; | |
4705 | if (fragP->fr_fix != 0) | |
4706 | break; | |
4707 | } | |
4708 | return FALSE; | |
4709 | } | |
4710 | ||
4711 | ||
4712 | static bfd_boolean | |
7fa3d080 | 4713 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4714 | { |
c138bc38 | 4715 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4716 | So we have to skip until we find something legit. */ |
4717 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4718 | { | |
4719 | if (fragP->tc_frag_data.is_loop_target) | |
4720 | return TRUE; | |
4721 | if (fragP->fr_fix != 0) | |
4722 | break; | |
4723 | } | |
4724 | return FALSE; | |
4725 | } | |
4726 | ||
4727 | ||
3a1e9c4a SA |
4728 | /* As specified in the relaxation table, when a loop instruction is |
4729 | relaxed, there are 24 bytes between the loop instruction itself and | |
4730 | the first instruction in the loop. */ | |
4731 | ||
4732 | #define RELAXED_LOOP_INSN_BYTES 24 | |
4733 | ||
e0001a05 | 4734 | static addressT |
7fa3d080 | 4735 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4736 | { |
4737 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4738 | xtensa_opcode next_opcode; |
e0001a05 | 4739 | |
43cd72b9 | 4740 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4741 | return 0; |
4742 | ||
43cd72b9 BW |
4743 | /* Sometimes an empty will end up here due to storage allocation issues, |
4744 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4745 | while (next_fragp->fr_fix == 0) |
4746 | next_fragp = next_fragp->fr_next; | |
4747 | ||
4748 | if (next_fragp->fr_type != rs_machine_dependent) | |
4749 | return 0; | |
4750 | ||
4751 | /* There is some implicit knowledge encoded in here. | |
4752 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4753 | been relaxed. Note that we can assume that the LOOP |
4754 | instruction is in slot 0 because loops aren't bundleable. */ | |
4755 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
3a1e9c4a | 4756 | return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; |
e0001a05 NC |
4757 | |
4758 | return 0; | |
4759 | } | |
4760 | ||
4761 | ||
4762 | /* Mark a location where we can later insert literal frags. Update | |
4763 | the section's literal_pool_loc, so subsequent literals can be | |
4764 | placed nearest to their use. */ | |
4765 | ||
4766 | static void | |
7fa3d080 | 4767 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4768 | { |
4769 | /* Any labels pointing to the current location need | |
4770 | to be adjusted to after the literal pool. */ | |
4771 | emit_state s; | |
e0001a05 | 4772 | fragS *pool_location; |
e0001a05 | 4773 | |
1f2a7e38 | 4774 | if (use_literal_section) |
43cd72b9 BW |
4775 | return; |
4776 | ||
dd49a749 BW |
4777 | /* We stash info in these frags so we can later move the literal's |
4778 | fixes into this frchain's fix list. */ | |
e0001a05 | 4779 | pool_location = frag_now; |
dd49a749 | 4780 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4781 | frag_now->tc_frag_data.literal_frag = frag_now; |
b46824bd MF |
4782 | /* Just record this frag. */ |
4783 | xtensa_maybe_create_literal_pool_frag (FALSE, FALSE); | |
dd49a749 | 4784 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4785 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4786 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4787 | frag_now->tc_frag_data.lit_seg = now_seg; |
4788 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4789 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4790 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4791 | |
4792 | /* Now put a frag into the literal pool that points to this location. */ | |
4793 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4794 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4795 | frag_align (2, 0, 0); | |
4796 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4797 | |
4798 | /* Close whatever frag is there. */ | |
4799 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4800 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4801 | frag_now->tc_frag_data.literal_frag = pool_location; |
4802 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4803 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4804 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4805 | } |
4806 | ||
4807 | ||
43cd72b9 BW |
4808 | /* Build a nop of the correct size into tinsn. */ |
4809 | ||
4810 | static void | |
7fa3d080 | 4811 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4812 | { |
4813 | tinsn_init (tinsn); | |
4814 | switch (size) | |
4815 | { | |
4816 | case 2: | |
4817 | tinsn->opcode = xtensa_nop_n_opcode; | |
4818 | tinsn->ntok = 0; | |
4819 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4820 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4821 | break; | |
4822 | ||
4823 | case 3: | |
4824 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4825 | { | |
4826 | tinsn->opcode = xtensa_or_opcode; | |
4827 | set_expr_const (&tinsn->tok[0], 1); | |
4828 | set_expr_const (&tinsn->tok[1], 1); | |
4829 | set_expr_const (&tinsn->tok[2], 1); | |
4830 | tinsn->ntok = 3; | |
4831 | } | |
4832 | else | |
4833 | tinsn->opcode = xtensa_nop_opcode; | |
4834 | ||
9c2799c2 | 4835 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4836 | } |
4837 | } | |
4838 | ||
4839 | ||
e0001a05 NC |
4840 | /* Assemble a NOP of the requested size in the buffer. User must have |
4841 | allocated "buf" with at least "size" bytes. */ | |
4842 | ||
7fa3d080 | 4843 | static void |
d77b99c9 | 4844 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4845 | { |
4846 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4847 | TInsn tinsn; |
e0001a05 | 4848 | |
43cd72b9 | 4849 | build_nop (&tinsn, size); |
e0001a05 | 4850 | |
43cd72b9 BW |
4851 | if (!insnbuf) |
4852 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4853 | |
43cd72b9 | 4854 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4855 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4856 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4857 | } |
4858 | ||
4859 | ||
4860 | /* Return the number of bytes for the offset of the expanded loop | |
4861 | instruction. This should be incorporated into the relaxation | |
4862 | specification but is hard-coded here. This is used to auto-align | |
4863 | the loop instruction. It is invalid to call this function if the | |
4864 | configuration does not have loops or if the opcode is not a loop | |
4865 | opcode. */ | |
4866 | ||
4867 | static addressT | |
7fa3d080 | 4868 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4869 | { |
4870 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4871 | This MUST correspond directly to the specification of the loop | |
4872 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4873 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4874 | if (opcode == xtensa_loop_opcode) |
4875 | return 0; | |
4876 | if (opcode == xtensa_loopnez_opcode) | |
4877 | return 3; | |
4878 | if (opcode == xtensa_loopgtz_opcode) | |
4879 | return 6; | |
4880 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4881 | return 0; | |
4882 | } | |
4883 | ||
4884 | ||
7fa3d080 BW |
4885 | static fragS * |
4886 | get_literal_pool_location (segT seg) | |
e0001a05 | 4887 | { |
b46824bd MF |
4888 | struct litpool_seg *lps = litpool_seg_list.next; |
4889 | struct litpool_frag *lpf; | |
4890 | for ( ; lps && lps->seg->id != seg->id; lps = lps->next) | |
4891 | ; | |
4892 | if (lps) | |
4893 | { | |
4894 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4895 | { /* Skip "candidates" for now. */ | |
4896 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
4897 | lpf->priority == 1) | |
4898 | return lpf->fragP; | |
4899 | } | |
4900 | /* Must convert a lower-priority pool. */ | |
4901 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4902 | { | |
4903 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
4904 | return lpf->fragP; | |
4905 | } | |
4906 | /* Still no match -- try for a low priority pool. */ | |
4907 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4908 | { | |
4909 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
4910 | return lpf->fragP; | |
4911 | } | |
4912 | } | |
e0001a05 NC |
4913 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; |
4914 | } | |
4915 | ||
4916 | ||
4917 | static void | |
7fa3d080 | 4918 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4919 | { |
4920 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4921 | } | |
4922 | ||
43cd72b9 BW |
4923 | |
4924 | /* Set frag assembly state should be called when a new frag is | |
4925 | opened and after a frag has been closed. */ | |
4926 | ||
7fa3d080 BW |
4927 | static void |
4928 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4929 | { |
4930 | if (!density_supported) | |
4931 | fragP->tc_frag_data.is_no_density = TRUE; | |
4932 | ||
4933 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4934 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4935 | "use_schedule" here. */ |
4936 | if (!directive_state[directive_transform]) | |
4937 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4938 | if (directive_state[directive_longcalls]) |
4939 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4940 | fragP->tc_frag_data.use_absolute_literals = |
4941 | directive_state[directive_absolute_literals]; | |
4942 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4943 | } | |
4944 | ||
4945 | ||
7fa3d080 BW |
4946 | static bfd_boolean |
4947 | relaxable_section (asection *sec) | |
43cd72b9 | 4948 | { |
11ac2671 BW |
4949 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4950 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4951 | } |
4952 | ||
4953 | ||
99ded152 BW |
4954 | static void |
4955 | xtensa_mark_frags_for_org (void) | |
4956 | { | |
4957 | segT *seclist; | |
4958 | ||
4959 | /* Walk over each fragment of all of the current segments. If we find | |
4960 | a .org frag in any of the segments, mark all frags prior to it as | |
4961 | "no transform", which will prevent linker optimizations from messing | |
4962 | up the .org distance. This should be done after | |
4963 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4964 | about that function trashing the data we save here. */ | |
4965 | ||
4966 | for (seclist = &stdoutput->sections; | |
4967 | seclist && *seclist; | |
4968 | seclist = &(*seclist)->next) | |
4969 | { | |
4970 | segT sec = *seclist; | |
4971 | segment_info_type *seginfo; | |
4972 | fragS *fragP; | |
4973 | flagword flags; | |
4974 | flags = bfd_get_section_flags (stdoutput, sec); | |
4975 | if (flags & SEC_DEBUGGING) | |
4976 | continue; | |
4977 | if (!(flags & SEC_ALLOC)) | |
4978 | continue; | |
4979 | ||
4980 | seginfo = seg_info (sec); | |
4981 | if (seginfo && seginfo->frchainP) | |
4982 | { | |
4983 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4984 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4985 | fragP = fragP->fr_next) | |
4986 | { | |
4987 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4988 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4989 | if (fragP->fr_subtype == RELAX_ORG) | |
4990 | { | |
4991 | while (last_fragP != fragP->fr_next) | |
4992 | { | |
4993 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4994 | last_fragP = last_fragP->fr_next; | |
4995 | } | |
4996 | } | |
4997 | } | |
4998 | } | |
4999 | } | |
5000 | } | |
5001 | ||
5002 | ||
43cd72b9 | 5003 | static void |
7fa3d080 | 5004 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
5005 | { |
5006 | segT *seclist; | |
5007 | ||
5008 | /* Walk over each fragment of all of the current segments. For each | |
5009 | unmarked fragment, mark it with the same info as the previous | |
5010 | fragment. */ | |
5011 | for (seclist = &stdoutput->sections; | |
5012 | seclist && *seclist; | |
5013 | seclist = &(*seclist)->next) | |
5014 | { | |
5015 | segT sec = *seclist; | |
5016 | segment_info_type *seginfo; | |
5017 | fragS *fragP; | |
5018 | flagword flags; | |
5019 | flags = bfd_get_section_flags (stdoutput, sec); | |
5020 | if (flags & SEC_DEBUGGING) | |
5021 | continue; | |
5022 | if (!(flags & SEC_ALLOC)) | |
5023 | continue; | |
5024 | ||
5025 | seginfo = seg_info (sec); | |
5026 | if (seginfo && seginfo->frchainP) | |
5027 | { | |
5028 | fragS *last_fragP = 0; | |
5029 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5030 | fragP = fragP->fr_next) | |
5031 | { | |
5032 | if (fragP->fr_fix != 0 | |
5033 | && !fragP->tc_frag_data.is_assembly_state_set) | |
5034 | { | |
5035 | if (last_fragP == 0) | |
5036 | { | |
5037 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
5038 | _("assembly state not set for first frag in section %s"), | |
5039 | sec->name); | |
5040 | } | |
5041 | else | |
5042 | { | |
5043 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
5044 | fragP->tc_frag_data.is_no_density = | |
5045 | last_fragP->tc_frag_data.is_no_density; | |
5046 | fragP->tc_frag_data.is_no_transform = | |
5047 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
5048 | fragP->tc_frag_data.use_longcalls = |
5049 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
5050 | fragP->tc_frag_data.use_absolute_literals = |
5051 | last_fragP->tc_frag_data.use_absolute_literals; | |
5052 | } | |
5053 | } | |
5054 | if (fragP->tc_frag_data.is_assembly_state_set) | |
5055 | last_fragP = fragP; | |
5056 | } | |
5057 | } | |
5058 | } | |
5059 | } | |
5060 | ||
5061 | ||
5062 | static void | |
7fa3d080 BW |
5063 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
5064 | asection *sec, | |
5065 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5066 | { |
5067 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5068 | segment_info_type *seginfo = seg_info (sec); | |
5069 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 5070 | |
43cd72b9 | 5071 | if (flags & SEC_CODE) |
c138bc38 | 5072 | { |
43cd72b9 BW |
5073 | xtensa_isa isa = xtensa_default_isa; |
5074 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
5075 | while (frag != NULL) | |
5076 | { | |
5077 | if (frag->tc_frag_data.is_branch_target) | |
5078 | { | |
5079 | int op_size; | |
664df4e4 | 5080 | addressT branch_align, frag_addr; |
43cd72b9 BW |
5081 | xtensa_format fmt; |
5082 | ||
d77b99c9 BW |
5083 | xtensa_insnbuf_from_chars |
5084 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5085 | fmt = xtensa_format_decode (isa, insnbuf); |
5086 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
5087 | branch_align = 1 << branch_align_power (sec); |
5088 | frag_addr = frag->fr_address % branch_align; | |
5089 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
5090 | as_warn_where (frag->fr_file, frag->fr_line, |
5091 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 5092 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5093 | } |
5094 | frag = frag->fr_next; | |
5095 | } | |
5096 | xtensa_insnbuf_free (isa, insnbuf); | |
5097 | } | |
5098 | } | |
5099 | ||
5100 | ||
5101 | static void | |
7fa3d080 BW |
5102 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
5103 | asection *sec, | |
5104 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5105 | { |
5106 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5107 | segment_info_type *seginfo = seg_info (sec); | |
5108 | fragS *frag = seginfo->frchainP->frch_root; | |
5109 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 5110 | |
43cd72b9 | 5111 | if (flags & SEC_CODE) |
c138bc38 | 5112 | { |
43cd72b9 BW |
5113 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5114 | while (frag != NULL) | |
5115 | { | |
5116 | if (frag->tc_frag_data.is_first_loop_insn) | |
5117 | { | |
5118 | int op_size; | |
d77b99c9 | 5119 | addressT frag_addr; |
43cd72b9 BW |
5120 | xtensa_format fmt; |
5121 | ||
3c83b96e SA |
5122 | if (frag->fr_fix == 0) |
5123 | frag = next_non_empty_frag (frag); | |
3739860c | 5124 | |
3c83b96e SA |
5125 | if (frag) |
5126 | { | |
5127 | xtensa_insnbuf_from_chars | |
5128 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
5129 | fmt = xtensa_format_decode (isa, insnbuf); | |
5130 | op_size = xtensa_format_length (isa, fmt); | |
5131 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
3739860c | 5132 | |
3c83b96e SA |
5133 | if (frag_addr + op_size > xtensa_fetch_width) |
5134 | as_warn_where (frag->fr_file, frag->fr_line, | |
5135 | _("unaligned loop: %d bytes at 0x%lx"), | |
5136 | op_size, (long) frag->fr_address); | |
5137 | } | |
43cd72b9 BW |
5138 | } |
5139 | frag = frag->fr_next; | |
5140 | } | |
5141 | xtensa_insnbuf_free (isa, insnbuf); | |
5142 | } | |
5143 | } | |
5144 | ||
5145 | ||
30f725a1 BW |
5146 | static int |
5147 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5148 | { |
5149 | xtensa_isa isa = xtensa_default_isa; | |
5150 | static xtensa_insnbuf insnbuf = NULL; | |
5151 | static xtensa_insnbuf slotbuf = NULL; | |
5152 | xtensa_format fmt; | |
5153 | int slot; | |
5154 | bfd_boolean alt_reloc; | |
5155 | xtensa_opcode opcode; | |
5156 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5157 | ||
1b6e95c2 BW |
5158 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5159 | || alt_reloc) | |
43cd72b9 BW |
5160 | as_fatal (_("unexpected fix")); |
5161 | ||
5162 | if (!insnbuf) | |
5163 | { | |
5164 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5165 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5166 | } | |
5167 | ||
d77b99c9 | 5168 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5169 | fmt = xtensa_format_decode (isa, insnbuf); |
5170 | if (fmt == XTENSA_UNDEFINED) | |
5171 | as_fatal (_("undecodable fix")); | |
5172 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5173 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5174 | if (opcode == XTENSA_UNDEFINED) | |
5175 | as_fatal (_("undecodable fix")); | |
5176 | ||
5177 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5178 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5179 | of a CONST16 operand. */ |
43cd72b9 | 5180 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5181 | return 0; |
43cd72b9 BW |
5182 | |
5183 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5184 | get_relaxable_immed (opcode), val, | |
5185 | fixP->fx_file, fixP->fx_line); | |
5186 | ||
5187 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5188 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5189 | |
5190 | return 1; | |
43cd72b9 BW |
5191 | } |
5192 | ||
e0001a05 NC |
5193 | \f |
5194 | /* External Functions and Other GAS Hooks. */ | |
5195 | ||
5196 | const char * | |
7fa3d080 | 5197 | xtensa_target_format (void) |
e0001a05 NC |
5198 | { |
5199 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5200 | } | |
5201 | ||
5202 | ||
5203 | void | |
7fa3d080 | 5204 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5205 | { |
5206 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5207 | } | |
5208 | ||
5209 | ||
5210 | void | |
7fa3d080 | 5211 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5212 | { |
5213 | if (target_big_endian) | |
5214 | number_to_chars_bigendian (buf, val, n); | |
5215 | else | |
5216 | number_to_chars_littleendian (buf, val, n); | |
5217 | } | |
5218 | ||
f7e16c2a MF |
5219 | static void |
5220 | xg_init_global_config (void) | |
5221 | { | |
5222 | target_big_endian = XCHAL_HAVE_BE; | |
5223 | ||
5224 | density_supported = XCHAL_HAVE_DENSITY; | |
5225 | absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; | |
5226 | xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; | |
5227 | ||
5228 | directive_state[directive_density] = XCHAL_HAVE_DENSITY; | |
5229 | directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; | |
5230 | } | |
5231 | ||
5232 | void | |
5233 | xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) | |
5234 | { | |
5235 | xg_init_global_config (); | |
5236 | } | |
e0001a05 NC |
5237 | |
5238 | /* This function is called once, at assembler startup time. It should | |
5239 | set up all the tables, etc. that the MD part of the assembler will | |
5240 | need. */ | |
5241 | ||
5242 | void | |
7fa3d080 | 5243 | md_begin (void) |
e0001a05 NC |
5244 | { |
5245 | segT current_section = now_seg; | |
5246 | int current_subsec = now_subseg; | |
5247 | xtensa_isa isa; | |
62af60e2 | 5248 | int i; |
e0001a05 | 5249 | |
43cd72b9 | 5250 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5251 | isa = xtensa_default_isa; |
e0001a05 | 5252 | |
43cd72b9 BW |
5253 | linkrelax = 1; |
5254 | ||
74869ac7 | 5255 | /* Set up the literal sections. */ |
e0001a05 | 5256 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5257 | |
5258 | subseg_set (current_section, current_subsec); | |
5259 | ||
5260 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5261 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5262 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5263 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5264 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5265 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5266 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5267 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5268 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5269 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5270 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5271 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5272 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5273 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5274 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5275 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5276 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5277 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5278 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5279 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5280 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5281 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5282 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5283 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5284 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5285 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5286 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5287 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5288 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5289 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5290 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5291 | |
3739860c | 5292 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
62af60e2 SA |
5293 | { |
5294 | int format_slots = xtensa_format_num_slots (isa, i); | |
5295 | if (format_slots > config_max_slots) | |
5296 | config_max_slots = format_slots; | |
5297 | } | |
5298 | ||
5299 | xg_init_vinsn (&cur_vinsn); | |
5300 | ||
77cba8a3 BW |
5301 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5302 | ||
43cd72b9 BW |
5303 | init_op_placement_info_table (); |
5304 | ||
5305 | /* Set up the assembly state. */ | |
5306 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5307 | xtensa_set_frag_assembly_state (frag_now); | |
5308 | } | |
5309 | ||
5310 | ||
5311 | /* TC_INIT_FIX_DATA hook */ | |
5312 | ||
5313 | void | |
7fa3d080 | 5314 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5315 | { |
5316 | x->tc_fix_data.slot = 0; | |
5317 | x->tc_fix_data.X_add_symbol = NULL; | |
5318 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5319 | } |
5320 | ||
5321 | ||
5322 | /* tc_frob_label hook */ | |
5323 | ||
5324 | void | |
7fa3d080 | 5325 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5326 | { |
3ea38ac2 BW |
5327 | float freq; |
5328 | ||
5329 | if (cur_vinsn.inside_bundle) | |
5330 | { | |
5331 | as_bad (_("labels are not valid inside bundles")); | |
5332 | return; | |
5333 | } | |
5334 | ||
5335 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5336 | |
43cd72b9 BW |
5337 | /* Since the label was already attached to a frag associated with the |
5338 | previous basic block, it now needs to be reset to the current frag. */ | |
5339 | symbol_set_frag (sym, frag_now); | |
5340 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5341 | ||
82e7541d BW |
5342 | if (generating_literals) |
5343 | xtensa_add_literal_sym (sym); | |
5344 | else | |
5345 | xtensa_add_insn_label (sym); | |
5346 | ||
7b1cc377 BW |
5347 | if (symbol_get_tc (sym)->is_loop_target) |
5348 | { | |
5349 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5350 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5351 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5352 | ||
5353 | xtensa_set_frag_assembly_state (frag_now); | |
5354 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5355 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5356 | ||
5357 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5358 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5359 | } |
e0001a05 NC |
5360 | |
5361 | /* No target aligning in the absolute section. */ | |
61846f28 | 5362 | if (now_seg != absolute_section |
61846f28 | 5363 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5364 | && !generating_literals) |
5365 | { | |
43cd72b9 BW |
5366 | xtensa_set_frag_assembly_state (frag_now); |
5367 | ||
b7afdeef SA |
5368 | if (do_align_targets ()) |
5369 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5370 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5371 | frag_now->fr_offset, NULL); | |
5372 | else | |
5373 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5374 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5375 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5376 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5377 | } |
5378 | ||
5379 | /* We need to mark the following properties even if we aren't aligning. */ | |
5380 | ||
5381 | /* If the label is already known to be a branch target, i.e., a | |
5382 | forward branch, mark the frag accordingly. Backward branches | |
5383 | are handled by xg_add_branch_and_loop_targets. */ | |
5384 | if (symbol_get_tc (sym)->is_branch_target) | |
5385 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5386 | ||
5387 | /* Loops only go forward, so they can be identified here. */ | |
5388 | if (symbol_get_tc (sym)->is_loop_target) | |
5389 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5390 | |
5391 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5392 | } |
5393 | ||
5394 | ||
5395 | /* tc_unrecognized_line hook */ | |
5396 | ||
5397 | int | |
7fa3d080 | 5398 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5399 | { |
5400 | switch (ch) | |
5401 | { | |
5402 | case '{' : | |
5403 | if (cur_vinsn.inside_bundle == 0) | |
5404 | { | |
5405 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5406 | when using --gstabs. Temporarily disable debug info. */ | |
5407 | generate_lineno_debug (); | |
5408 | if (debug_type == DEBUG_STABS) | |
5409 | { | |
5410 | xt_saved_debug_type = debug_type; | |
5411 | debug_type = DEBUG_NONE; | |
5412 | } | |
82e7541d | 5413 | |
43cd72b9 BW |
5414 | cur_vinsn.inside_bundle = 1; |
5415 | } | |
5416 | else | |
5417 | { | |
5418 | as_bad (_("extra opening brace")); | |
5419 | return 0; | |
5420 | } | |
5421 | break; | |
82e7541d | 5422 | |
43cd72b9 BW |
5423 | case '}' : |
5424 | if (cur_vinsn.inside_bundle) | |
5425 | finish_vinsn (&cur_vinsn); | |
5426 | else | |
5427 | { | |
5428 | as_bad (_("extra closing brace")); | |
5429 | return 0; | |
5430 | } | |
5431 | break; | |
5432 | default: | |
5433 | as_bad (_("syntax error")); | |
5434 | return 0; | |
e0001a05 | 5435 | } |
43cd72b9 | 5436 | return 1; |
e0001a05 NC |
5437 | } |
5438 | ||
5439 | ||
5440 | /* md_flush_pending_output hook */ | |
5441 | ||
5442 | void | |
7fa3d080 | 5443 | xtensa_flush_pending_output (void) |
e0001a05 | 5444 | { |
a3582eee BW |
5445 | /* This line fixes a bug where automatically generated gstabs info |
5446 | separates a function label from its entry instruction, ending up | |
5447 | with the literal position between the function label and the entry | |
5448 | instruction and crashing code. It only happens with --gstabs and | |
5449 | --text-section-literals, and when several other obscure relaxation | |
5450 | conditions are met. */ | |
5451 | if (outputting_stabs_line_debug) | |
5452 | return; | |
5453 | ||
43cd72b9 BW |
5454 | if (cur_vinsn.inside_bundle) |
5455 | as_bad (_("missing closing brace")); | |
5456 | ||
e0001a05 NC |
5457 | /* If there is a non-zero instruction fragment, close it. */ |
5458 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5459 | { | |
5460 | frag_wane (frag_now); | |
5461 | frag_new (0); | |
43cd72b9 | 5462 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5463 | } |
5464 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5465 | |
5466 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5467 | } |
5468 | ||
5469 | ||
43cd72b9 BW |
5470 | /* We had an error while parsing an instruction. The string might look |
5471 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5472 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5473 | and the num_slots field will grow past the end of the array of slots, | |
5474 | and bad things happen. */ | |
5475 | ||
5476 | static void | |
7fa3d080 | 5477 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5478 | { |
5479 | if (cur_vinsn.inside_bundle) | |
5480 | { | |
5481 | if (*input_line_pointer == '}' | |
5482 | || *(input_line_pointer - 1) == '}' | |
5483 | || *(input_line_pointer - 2) == '}') | |
5484 | xg_clear_vinsn (&cur_vinsn); | |
5485 | } | |
5486 | } | |
5487 | ||
5488 | ||
e0001a05 | 5489 | void |
7fa3d080 | 5490 | md_assemble (char *str) |
e0001a05 NC |
5491 | { |
5492 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5493 | char *opname; |
e0001a05 NC |
5494 | unsigned opnamelen; |
5495 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5496 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5497 | int num_args; |
e0001a05 | 5498 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5499 | |
e0001a05 NC |
5500 | tinsn_init (&orig_insn); |
5501 | ||
5502 | /* Split off the opcode. */ | |
5503 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
4ec9d7d5 | 5504 | opname = xstrndup (str, opnamelen); |
e0001a05 NC |
5505 | |
5506 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5507 | if (num_args == -1) | |
5508 | { | |
5509 | as_bad (_("syntax error")); | |
5510 | return; | |
5511 | } | |
5512 | ||
5513 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5514 | return; | |
5515 | ||
5516 | /* Check for an underbar prefix. */ | |
5517 | if (*opname == '_') | |
5518 | { | |
5519 | has_underbar = TRUE; | |
5520 | opname += 1; | |
5521 | } | |
5522 | ||
5523 | orig_insn.insn_type = ITYPE_INSN; | |
5524 | orig_insn.ntok = 0; | |
43cd72b9 | 5525 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5526 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 | 5527 | |
2b0f3761 | 5528 | /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its |
28dbbc02 BW |
5529 | extra argument and set the opcode to "CALLXn". */ |
5530 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5531 | && strncasecmp (opname, "callx", 5) == 0) | |
5532 | { | |
5533 | unsigned long window_size; | |
5534 | char *suffix; | |
5535 | ||
5536 | window_size = strtoul (opname + 5, &suffix, 10); | |
5537 | if (suffix != opname + 5 | |
5538 | && (window_size == 0 | |
5539 | || window_size == 4 | |
5540 | || window_size == 8 | |
5541 | || window_size == 12) | |
5542 | && strcasecmp (suffix, ".tls") == 0) | |
5543 | { | |
5544 | switch (window_size) | |
5545 | { | |
5546 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5547 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5548 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5549 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5550 | } | |
5551 | ||
5552 | if (num_args != 2) | |
5553 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5554 | else | |
5555 | { | |
5556 | bfd_reloc_code_real_type reloc; | |
5557 | char *old_input_line_pointer; | |
19e8f41a | 5558 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5559 | |
5560 | old_input_line_pointer = input_line_pointer; | |
5561 | input_line_pointer = arg_strings[num_args - 1]; | |
5562 | ||
87975d2a | 5563 | expression (tok); |
28dbbc02 BW |
5564 | if (tok->X_op == O_symbol |
5565 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5566 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5567 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5568 | else | |
5569 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5570 | ||
5571 | input_line_pointer = old_input_line_pointer; | |
5572 | num_args -= 1; | |
5573 | } | |
5574 | } | |
5575 | } | |
5576 | ||
2b0f3761 | 5577 | /* Special case: Check for "j.l" pseudo op. */ |
19e8f41a BW |
5578 | if (orig_insn.opcode == XTENSA_UNDEFINED |
5579 | && strncasecmp (opname, "j.l", 3) == 0) | |
5580 | { | |
5581 | if (num_args != 2) | |
5582 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5583 | else | |
5584 | { | |
5585 | char *old_input_line_pointer; | |
5586 | expressionS *tok = &orig_insn.extra_arg; | |
5587 | ||
5588 | old_input_line_pointer = input_line_pointer; | |
5589 | input_line_pointer = arg_strings[num_args - 1]; | |
5590 | ||
5591 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5592 | input_line_pointer = old_input_line_pointer; | |
5593 | ||
5594 | num_args -= 1; | |
5595 | orig_insn.opcode = xtensa_j_opcode; | |
5596 | } | |
5597 | } | |
5598 | ||
e0001a05 NC |
5599 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5600 | { | |
43cd72b9 BW |
5601 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5602 | if (fmt == XTENSA_UNDEFINED) | |
5603 | { | |
5604 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5605 | error_reset_cur_vinsn (); | |
5606 | return; | |
5607 | } | |
5608 | if (!cur_vinsn.inside_bundle) | |
5609 | { | |
5610 | as_bad (_("format names only valid inside bundles")); | |
5611 | error_reset_cur_vinsn (); | |
5612 | return; | |
5613 | } | |
5614 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5615 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5616 | opname); | |
5617 | cur_vinsn.format = fmt; | |
5618 | free (has_underbar ? opname - 1 : opname); | |
5619 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5620 | return; |
5621 | } | |
5622 | ||
e0001a05 NC |
5623 | /* Parse the arguments. */ |
5624 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5625 | { | |
5626 | as_bad (_("syntax error")); | |
43cd72b9 | 5627 | error_reset_cur_vinsn (); |
e0001a05 NC |
5628 | return; |
5629 | } | |
5630 | ||
5631 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5632 | free (has_underbar ? opname - 1 : opname); | |
5633 | opname = 0; | |
5634 | while (num_args-- > 0) | |
5635 | free (arg_strings[num_args]); | |
5636 | ||
43cd72b9 BW |
5637 | /* Get expressions for invisible operands. */ |
5638 | if (get_invisible_operands (&orig_insn)) | |
5639 | { | |
5640 | error_reset_cur_vinsn (); | |
5641 | return; | |
5642 | } | |
5643 | ||
e0001a05 NC |
5644 | /* Check for the right number and type of arguments. */ |
5645 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5646 | { |
43cd72b9 BW |
5647 | error_reset_cur_vinsn (); |
5648 | return; | |
e0001a05 NC |
5649 | } |
5650 | ||
b224e962 BW |
5651 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5652 | spread across multiple input lines and individual instructions may be | |
5653 | moved around in some cases. */ | |
5654 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5655 | dwarf2_where (&orig_insn.debug_line); | |
5656 | dwarf2_consume_line_info (); | |
c138bc38 | 5657 | |
43cd72b9 BW |
5658 | xg_add_branch_and_loop_targets (&orig_insn); |
5659 | ||
431ad2d0 BW |
5660 | /* Check that immediate value for ENTRY is >= 16. */ |
5661 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5662 | { |
431ad2d0 BW |
5663 | expressionS *exp = &orig_insn.tok[2]; |
5664 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5665 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5666 | } |
5667 | ||
e0001a05 | 5668 | /* Finish it off: |
43cd72b9 BW |
5669 | assemble_tokens (opcode, tok, ntok); |
5670 | expand the tokens from the orig_insn into the | |
5671 | stack of instructions that will not expand | |
e0001a05 | 5672 | unless required at relaxation time. */ |
e0001a05 | 5673 | |
43cd72b9 BW |
5674 | if (!cur_vinsn.inside_bundle) |
5675 | emit_single_op (&orig_insn); | |
5676 | else /* We are inside a bundle. */ | |
e0001a05 | 5677 | { |
43cd72b9 BW |
5678 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5679 | cur_vinsn.num_slots++; | |
5680 | if (*input_line_pointer == '}' | |
5681 | || *(input_line_pointer - 1) == '}' | |
5682 | || *(input_line_pointer - 2) == '}') | |
5683 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5684 | } |
5685 | ||
43cd72b9 BW |
5686 | /* We've just emitted a new instruction so clear the list of labels. */ |
5687 | xtensa_clear_insn_labels (); | |
a82c7d90 DW |
5688 | |
5689 | xtensa_check_frag_count (); | |
e0001a05 NC |
5690 | } |
5691 | ||
5692 | ||
43cd72b9 | 5693 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5694 | |
43cd72b9 BW |
5695 | /* For a .align directive, we mark the previous block with the alignment |
5696 | information. This will be placed in the object file in the | |
5697 | property section corresponding to this section. */ | |
e0001a05 | 5698 | |
43cd72b9 | 5699 | void |
7fa3d080 | 5700 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5701 | { |
5702 | if (linkrelax | |
b08b5071 | 5703 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5704 | && (fragP->fr_type == rs_align |
5705 | || fragP->fr_type == rs_align_code) | |
43cd72b9 BW |
5706 | && fragP->fr_offset > 0 |
5707 | && now_seg != bss_section) | |
e0001a05 | 5708 | { |
43cd72b9 BW |
5709 | fragP->tc_frag_data.is_align = TRUE; |
5710 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5711 | } |
5712 | ||
43cd72b9 | 5713 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5714 | { |
43cd72b9 BW |
5715 | int count; |
5716 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5717 | if (count != 0) | |
c138bc38 | 5718 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5719 | _("unaligned entry instruction")); |
e0001a05 | 5720 | } |
99ded152 BW |
5721 | |
5722 | if (linkrelax && fragP->fr_type == rs_org) | |
5723 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5724 | } |
43cd72b9 | 5725 | |
e0001a05 NC |
5726 | |
5727 | /* TC_FRAG_INIT hook */ | |
5728 | ||
5729 | void | |
7fa3d080 | 5730 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5731 | { |
43cd72b9 | 5732 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5733 | } |
5734 | ||
5735 | ||
5736 | symbolS * | |
7fa3d080 | 5737 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5738 | { |
5739 | return NULL; | |
5740 | } | |
5741 | ||
5742 | ||
5743 | /* Round up a section size to the appropriate boundary. */ | |
5744 | ||
5745 | valueT | |
7fa3d080 | 5746 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5747 | { |
5748 | return size; /* Byte alignment is fine. */ | |
5749 | } | |
5750 | ||
5751 | ||
5752 | long | |
7fa3d080 | 5753 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5754 | { |
5755 | char *insn_p; | |
5756 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5757 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5758 | int opnum; |
43cd72b9 | 5759 | uint32 opnd_value; |
e0001a05 | 5760 | xtensa_opcode opcode; |
43cd72b9 BW |
5761 | xtensa_format fmt; |
5762 | int slot; | |
e0001a05 NC |
5763 | xtensa_isa isa = xtensa_default_isa; |
5764 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5765 | bfd_boolean alt_reloc; |
e0001a05 | 5766 | |
e0001a05 | 5767 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5768 | return 0; |
e0001a05 | 5769 | |
1bbb5f21 BW |
5770 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5771 | return addr; | |
5772 | ||
e0001a05 | 5773 | if (!insnbuf) |
43cd72b9 BW |
5774 | { |
5775 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5776 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5777 | } | |
e0001a05 NC |
5778 | |
5779 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5780 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5781 | fmt = xtensa_format_decode (isa, insnbuf); |
5782 | ||
5783 | if (fmt == XTENSA_UNDEFINED) | |
5784 | as_fatal (_("bad instruction format")); | |
5785 | ||
5786 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5787 | as_fatal (_("invalid relocation")); | |
5788 | ||
5789 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5790 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5791 | ||
30f725a1 BW |
5792 | /* Check for "alternate" relocations (operand not specified). None |
5793 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5794 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5795 | { | |
5796 | if (opcode != xtensa_l32r_opcode | |
5797 | && opcode != xtensa_const16_opcode) | |
5798 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5799 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5800 | return 0; |
e0001a05 NC |
5801 | } |
5802 | ||
43cd72b9 BW |
5803 | opnum = get_relaxable_immed (opcode); |
5804 | opnd_value = 0; | |
5805 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5806 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5807 | { |
5808 | as_bad_where (fixP->fx_file, | |
5809 | fixP->fx_line, | |
5810 | _("invalid relocation for operand %d of '%s'"), | |
5811 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5812 | return 0; |
e0001a05 | 5813 | } |
43cd72b9 BW |
5814 | return 0 - opnd_value; |
5815 | } | |
5816 | ||
5817 | ||
5818 | /* TC_FORCE_RELOCATION hook */ | |
5819 | ||
5820 | int | |
7fa3d080 | 5821 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5822 | { |
5823 | switch (fix->fx_r_type) | |
30f725a1 BW |
5824 | { |
5825 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5826 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5827 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5828 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5829 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5830 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5831 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5832 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5833 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5834 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5835 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5836 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5837 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5838 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5839 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5840 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5841 | return 1; |
5842 | default: | |
5843 | break; | |
e0001a05 NC |
5844 | } |
5845 | ||
43cd72b9 BW |
5846 | if (linkrelax && fix->fx_addsy |
5847 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5848 | return 1; | |
5849 | ||
5850 | return generic_force_reloc (fix); | |
5851 | } | |
5852 | ||
5853 | ||
30f725a1 BW |
5854 | /* TC_VALIDATE_FIX_SUB hook */ |
5855 | ||
5856 | int | |
5857 | xtensa_validate_fix_sub (fixS *fix) | |
5858 | { | |
5859 | segT add_symbol_segment, sub_symbol_segment; | |
5860 | ||
5861 | /* The difference of two symbols should be resolved by the assembler when | |
5862 | linkrelax is not set. If the linker may relax the section containing | |
5863 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5864 | the linker knows to adjust the difference value. */ | |
5865 | if (!linkrelax || fix->fx_addsy == NULL) | |
5866 | return 0; | |
5867 | ||
5868 | /* Make sure both symbols are in the same segment, and that segment is | |
5869 | "normal" and relaxable. If the segment is not "normal", then the | |
5870 | fix is not valid. If the segment is not "relaxable", then the fix | |
5871 | should have been handled earlier. */ | |
5872 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5873 | if (! SEG_NORMAL (add_symbol_segment) || | |
5874 | ! relaxable_section (add_symbol_segment)) | |
5875 | return 0; | |
5876 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5877 | return (sub_symbol_segment == add_symbol_segment); | |
5878 | } | |
5879 | ||
5880 | ||
43cd72b9 BW |
5881 | /* NO_PSEUDO_DOT hook */ |
5882 | ||
5883 | /* This function has nothing to do with pseudo dots, but this is the | |
5884 | nearest macro to where the check needs to take place. FIXME: This | |
5885 | seems wrong. */ | |
5886 | ||
5887 | bfd_boolean | |
7fa3d080 | 5888 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5889 | { |
5890 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5891 | as_bad (_("directives are not valid inside bundles")); | |
5892 | ||
5893 | /* This function must always return FALSE because it is called via a | |
5894 | macro that has nothing to do with bundling. */ | |
5895 | return FALSE; | |
e0001a05 NC |
5896 | } |
5897 | ||
5898 | ||
43cd72b9 | 5899 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5900 | |
5901 | void | |
7fa3d080 | 5902 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5903 | { |
43cd72b9 BW |
5904 | /* Set up the assembly state. */ |
5905 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5906 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5907 | } |
5908 | ||
5909 | ||
5910 | /* tc_fix_adjustable hook */ | |
5911 | ||
5912 | bfd_boolean | |
7fa3d080 | 5913 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5914 | { |
5915 | /* We need the symbol name for the VTABLE entries. */ | |
5916 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5917 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5918 | return 0; | |
5919 | ||
5920 | return 1; | |
5921 | } | |
5922 | ||
5923 | ||
6a7eedfe BW |
5924 | /* tc_symbol_new_hook */ |
5925 | ||
5926 | symbolS *expr_symbols = NULL; | |
5927 | ||
3739860c | 5928 | void |
6a7eedfe BW |
5929 | xtensa_symbol_new_hook (symbolS *sym) |
5930 | { | |
fb227da0 | 5931 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5932 | { |
5933 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5934 | expr_symbols = sym; | |
5935 | } | |
5936 | } | |
5937 | ||
5938 | ||
e0001a05 | 5939 | void |
55cf6793 | 5940 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5941 | { |
30f725a1 | 5942 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5943 | valueT val = 0; |
30f725a1 | 5944 | |
e7da6241 BW |
5945 | /* Subtracted symbols are only allowed for a few relocation types, and |
5946 | unless linkrelax is enabled, they should not make it to this point. */ | |
5947 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5948 | || fixP->fx_r_type == BFD_RELOC_16 | |
5949 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5950 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5951 | ||
30f725a1 | 5952 | switch (fixP->fx_r_type) |
e0001a05 | 5953 | { |
1bbb5f21 | 5954 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5955 | case BFD_RELOC_32: |
5956 | case BFD_RELOC_16: | |
5957 | case BFD_RELOC_8: | |
e7da6241 | 5958 | if (fixP->fx_subsy) |
30f725a1 BW |
5959 | { |
5960 | switch (fixP->fx_r_type) | |
5961 | { | |
5962 | case BFD_RELOC_8: | |
5963 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
ea173078 | 5964 | fixP->fx_signed = 0; |
30f725a1 BW |
5965 | break; |
5966 | case BFD_RELOC_16: | |
5967 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
ea173078 | 5968 | fixP->fx_signed = 0; |
30f725a1 BW |
5969 | break; |
5970 | case BFD_RELOC_32: | |
5971 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
ea173078 | 5972 | fixP->fx_signed = 0; |
30f725a1 BW |
5973 | break; |
5974 | default: | |
5975 | break; | |
5976 | } | |
e0001a05 | 5977 | |
30f725a1 BW |
5978 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
5979 | - S_GET_VALUE (fixP->fx_subsy)); | |
5980 | ||
5981 | /* The difference value gets written out, and the DIFF reloc | |
5982 | identifies the address of the subtracted symbol (i.e., the one | |
5983 | with the lowest address). */ | |
5984 | *valP = val; | |
5985 | fixP->fx_offset -= val; | |
5986 | fixP->fx_subsy = NULL; | |
5987 | } | |
5988 | else if (! fixP->fx_addsy) | |
e0001a05 | 5989 | { |
30f725a1 | 5990 | val = *valP; |
e0001a05 | 5991 | fixP->fx_done = 1; |
30f725a1 | 5992 | } |
d47d412e BW |
5993 | /* fall through */ |
5994 | ||
5995 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5996 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5997 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5998 | break; | |
e0001a05 | 5999 | |
28dbbc02 BW |
6000 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
6001 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
6002 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
6003 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
6004 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6005 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
6006 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6007 | break; | |
6008 | ||
30f725a1 BW |
6009 | case BFD_RELOC_XTENSA_SLOT0_OP: |
6010 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
6011 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
6012 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
6013 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
6014 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
6015 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
6016 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
6017 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
6018 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
6019 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
6020 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
6021 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
6022 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
6023 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
6024 | if (linkrelax) | |
6025 | { | |
6026 | /* Write the tentative value of a PC-relative relocation to a | |
6027 | local symbol into the instruction. The value will be ignored | |
6028 | by the linker, and it makes the object file disassembly | |
6029 | readable when all branch targets are encoded in relocations. */ | |
6030 | ||
9c2799c2 | 6031 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 6032 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
6033 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
6034 | { | |
6035 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
6036 | - md_pcrel_from (fixP)); | |
6037 | (void) xg_apply_fix_value (fixP, val); | |
6038 | } | |
6039 | } | |
6040 | else if (! fixP->fx_addsy) | |
6041 | { | |
6042 | val = *valP; | |
6043 | if (xg_apply_fix_value (fixP, val)) | |
6044 | fixP->fx_done = 1; | |
6045 | } | |
6046 | break; | |
e0001a05 | 6047 | |
30f725a1 | 6048 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
6049 | case BFD_RELOC_XTENSA_TLS_FUNC: |
6050 | case BFD_RELOC_XTENSA_TLS_ARG: | |
6051 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
6052 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
6053 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
6054 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
6055 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
6056 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
6057 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
6058 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
6059 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
6060 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
6061 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
6062 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
6063 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
6064 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
6065 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
6066 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
6067 | /* These all need to be resolved at link-time. Do nothing now. */ | |
6068 | break; | |
e0001a05 | 6069 | |
30f725a1 BW |
6070 | case BFD_RELOC_VTABLE_INHERIT: |
6071 | case BFD_RELOC_VTABLE_ENTRY: | |
6072 | fixP->fx_done = 0; | |
6073 | break; | |
e0001a05 | 6074 | |
30f725a1 BW |
6075 | default: |
6076 | as_bad (_("unhandled local relocation fix %s"), | |
6077 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
6078 | } |
6079 | } | |
6080 | ||
6081 | ||
6d4af3c2 | 6082 | const char * |
7fa3d080 | 6083 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 6084 | { |
499ac353 | 6085 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
6086 | } |
6087 | ||
6088 | ||
6089 | int | |
7fa3d080 | 6090 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 6091 | { |
34e41783 | 6092 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
6093 | } |
6094 | ||
6095 | ||
6096 | /* Translate internal representation of relocation info to BFD target | |
6097 | format. */ | |
6098 | ||
6099 | arelent * | |
30f725a1 | 6100 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
6101 | { |
6102 | arelent *reloc; | |
6103 | ||
325801bd TS |
6104 | reloc = XNEW (arelent); |
6105 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
e0001a05 NC |
6106 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
6107 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6108 | ||
6109 | /* Make sure none of our internal relocations make it this far. | |
6110 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 6111 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 6112 | |
30f725a1 | 6113 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 6114 | |
e0001a05 NC |
6115 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
6116 | if (reloc->howto == NULL) | |
6117 | { | |
6118 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6119 | _("cannot represent `%s' relocation in object file"), | |
6120 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
6121 | free (reloc->sym_ptr_ptr); |
6122 | free (reloc); | |
e0001a05 NC |
6123 | return NULL; |
6124 | } | |
6125 | ||
6126 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6127 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6128 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6129 | |
e0001a05 NC |
6130 | return reloc; |
6131 | } | |
6132 | ||
7fa3d080 BW |
6133 | \f |
6134 | /* Checks for resource conflicts between instructions. */ | |
6135 | ||
c138bc38 BW |
6136 | /* The func unit stuff could be implemented as bit-vectors rather |
6137 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6138 | slow, we will switch it. */ |
6139 | ||
c138bc38 | 6140 | resource_table * |
7fa3d080 BW |
6141 | new_resource_table (void *data, |
6142 | int cycles, | |
6143 | int nu, | |
6144 | unit_num_copies_func uncf, | |
6145 | opcode_num_units_func onuf, | |
6146 | opcode_funcUnit_use_unit_func ouuf, | |
6147 | opcode_funcUnit_use_stage_func ousf) | |
6148 | { | |
6149 | int i; | |
325801bd | 6150 | resource_table *rt = XNEW (resource_table); |
7fa3d080 BW |
6151 | rt->data = data; |
6152 | rt->cycles = cycles; | |
6153 | rt->allocated_cycles = cycles; | |
6154 | rt->num_units = nu; | |
6155 | rt->unit_num_copies = uncf; | |
6156 | rt->opcode_num_units = onuf; | |
6157 | rt->opcode_unit_use = ouuf; | |
6158 | rt->opcode_unit_stage = ousf; | |
6159 | ||
add39d23 | 6160 | rt->units = XCNEWVEC (unsigned char *, cycles); |
7fa3d080 | 6161 | for (i = 0; i < cycles; i++) |
add39d23 | 6162 | rt->units[i] = XCNEWVEC (unsigned char, nu); |
7fa3d080 BW |
6163 | |
6164 | return rt; | |
6165 | } | |
6166 | ||
6167 | ||
c138bc38 | 6168 | void |
7fa3d080 BW |
6169 | clear_resource_table (resource_table *rt) |
6170 | { | |
6171 | int i, j; | |
6172 | for (i = 0; i < rt->allocated_cycles; i++) | |
6173 | for (j = 0; j < rt->num_units; j++) | |
6174 | rt->units[i][j] = 0; | |
6175 | } | |
6176 | ||
6177 | ||
6178 | /* We never shrink it, just fake it into thinking so. */ | |
6179 | ||
c138bc38 | 6180 | void |
7fa3d080 BW |
6181 | resize_resource_table (resource_table *rt, int cycles) |
6182 | { | |
6183 | int i, old_cycles; | |
6184 | ||
6185 | rt->cycles = cycles; | |
6186 | if (cycles <= rt->allocated_cycles) | |
6187 | return; | |
6188 | ||
6189 | old_cycles = rt->allocated_cycles; | |
6190 | rt->allocated_cycles = cycles; | |
6191 | ||
325801bd | 6192 | rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); |
7fa3d080 | 6193 | for (i = 0; i < old_cycles; i++) |
325801bd | 6194 | rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); |
7fa3d080 | 6195 | for (i = old_cycles; i < cycles; i++) |
add39d23 | 6196 | rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); |
7fa3d080 BW |
6197 | } |
6198 | ||
6199 | ||
c138bc38 | 6200 | bfd_boolean |
7fa3d080 BW |
6201 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6202 | { | |
6203 | int i; | |
6204 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6205 | ||
c138bc38 | 6206 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6207 | { |
6208 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6209 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6210 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6211 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6212 | if (copies_in_use >= copies) | |
6213 | return FALSE; | |
6214 | } | |
6215 | return TRUE; | |
6216 | } | |
7fa3d080 | 6217 | |
c138bc38 BW |
6218 | |
6219 | void | |
7fa3d080 BW |
6220 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6221 | { | |
6222 | int i; | |
6223 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6224 | ||
c138bc38 | 6225 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6226 | { |
6227 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6228 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6229 | /* Note that this allows resources to be oversubscribed. That's |
6230 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6231 | resources_available reports when a resource is over-subscribed, |
6232 | so it's easy to tell. */ | |
6233 | rt->units[stage + cycle][unit]++; | |
6234 | } | |
6235 | } | |
6236 | ||
6237 | ||
c138bc38 | 6238 | void |
7fa3d080 BW |
6239 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6240 | { | |
6241 | int i; | |
6242 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6243 | ||
c138bc38 | 6244 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6245 | { |
6246 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6247 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6248 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6249 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6250 | } |
6251 | } | |
c138bc38 | 6252 | |
7fa3d080 BW |
6253 | |
6254 | /* Wrapper functions make parameterized resource reservation | |
6255 | more convenient. */ | |
6256 | ||
c138bc38 | 6257 | int |
7fa3d080 BW |
6258 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6259 | { | |
6260 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6261 | return use->unit; |
7fa3d080 BW |
6262 | } |
6263 | ||
6264 | ||
c138bc38 | 6265 | int |
7fa3d080 BW |
6266 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6267 | { | |
6268 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6269 | return use->stage; | |
6270 | } | |
6271 | ||
6272 | ||
6273 | /* Note that this function does not check issue constraints, but | |
6274 | solely whether the hardware is available to execute the given | |
c138bc38 | 6275 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6276 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6277 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6278 | |
6279 | static bfd_boolean | |
6280 | resources_conflict (vliw_insn *vinsn) | |
6281 | { | |
6282 | int i; | |
6283 | static resource_table *rt = NULL; | |
6284 | ||
6285 | /* This is the most common case by far. Optimize it. */ | |
6286 | if (vinsn->num_slots == 1) | |
6287 | return FALSE; | |
43cd72b9 | 6288 | |
c138bc38 | 6289 | if (rt == NULL) |
7fa3d080 BW |
6290 | { |
6291 | xtensa_isa isa = xtensa_default_isa; | |
6292 | rt = new_resource_table | |
77cba8a3 | 6293 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6294 | xtensa_isa_num_funcUnits (isa), |
6295 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6296 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6297 | opcode_funcUnit_use_unit, | |
6298 | opcode_funcUnit_use_stage); | |
6299 | } | |
43cd72b9 | 6300 | |
7fa3d080 | 6301 | clear_resource_table (rt); |
43cd72b9 | 6302 | |
7fa3d080 BW |
6303 | for (i = 0; i < vinsn->num_slots; i++) |
6304 | { | |
6305 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6306 | return TRUE; | |
6307 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6308 | } | |
e0001a05 | 6309 | |
7fa3d080 BW |
6310 | return FALSE; |
6311 | } | |
e0001a05 | 6312 | |
7fa3d080 BW |
6313 | \f |
6314 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6315 | |
7fa3d080 BW |
6316 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6317 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6318 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6319 | |
6320 | ||
43cd72b9 BW |
6321 | /* We have reached the end of a bundle; emit into the frag. */ |
6322 | ||
e0001a05 | 6323 | static void |
7fa3d080 | 6324 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6325 | { |
43cd72b9 BW |
6326 | IStack slotstack; |
6327 | int i; | |
bf3d1399 | 6328 | int slots; |
e0001a05 | 6329 | |
43cd72b9 | 6330 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6331 | { |
6332 | xg_clear_vinsn (vinsn); | |
6333 | return; | |
6334 | } | |
43cd72b9 BW |
6335 | |
6336 | /* First, find a format that works. */ | |
6337 | if (vinsn->format == XTENSA_UNDEFINED) | |
6338 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6339 | ||
bf3d1399 AM |
6340 | slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); |
6341 | if (slots > 1 | |
19fc3723 SA |
6342 | && produce_flix == FLIX_NONE) |
6343 | { | |
6344 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6345 | xg_clear_vinsn (vinsn); | |
6346 | return; | |
6347 | } | |
6348 | ||
43cd72b9 BW |
6349 | if (vinsn->format == XTENSA_UNDEFINED) |
6350 | { | |
3b4dbbbf | 6351 | as_bad (_("couldn't find a valid instruction format")); |
43cd72b9 BW |
6352 | fprintf (stderr, _(" ops were: ")); |
6353 | for (i = 0; i < vinsn->num_slots; i++) | |
6354 | fprintf (stderr, _(" %s;"), | |
6355 | xtensa_opcode_name (xtensa_default_isa, | |
6356 | vinsn->slots[i].opcode)); | |
6357 | fprintf (stderr, _("\n")); | |
6358 | xg_clear_vinsn (vinsn); | |
6359 | return; | |
6360 | } | |
6361 | ||
bf3d1399 | 6362 | if (vinsn->num_slots != slots) |
e0001a05 | 6363 | { |
bf3d1399 AM |
6364 | as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), |
6365 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6e98b342 | 6366 | slots, vinsn->num_slots); |
43cd72b9 BW |
6367 | xg_clear_vinsn (vinsn); |
6368 | return; | |
6369 | } | |
e0001a05 | 6370 | |
c138bc38 | 6371 | if (resources_conflict (vinsn)) |
43cd72b9 | 6372 | { |
3b4dbbbf | 6373 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6374 | fprintf (stderr, " ops were: "); |
6375 | for (i = 0; i < vinsn->num_slots; i++) | |
6376 | fprintf (stderr, " %s;", | |
6377 | xtensa_opcode_name (xtensa_default_isa, | |
6378 | vinsn->slots[i].opcode)); | |
6379 | fprintf (stderr, "\n"); | |
6380 | xg_clear_vinsn (vinsn); | |
6381 | return; | |
6382 | } | |
6383 | ||
6384 | for (i = 0; i < vinsn->num_slots; i++) | |
6385 | { | |
6386 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6387 | { |
43cd72b9 BW |
6388 | symbolS *lit_sym = NULL; |
6389 | int j; | |
6390 | bfd_boolean e = FALSE; | |
6391 | bfd_boolean saved_density = density_supported; | |
6392 | ||
6393 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6394 | if (vinsn->num_slots > 1) | |
6395 | density_supported = FALSE; | |
6396 | ||
6397 | istack_init (&slotstack); | |
6398 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6399 | { |
43cd72b9 BW |
6400 | vinsn->slots[i].opcode = |
6401 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6402 | vinsn->format, i); | |
6403 | vinsn->slots[i].ntok = 0; | |
6404 | } | |
e0001a05 | 6405 | |
43cd72b9 BW |
6406 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6407 | { | |
6408 | e = TRUE; | |
6409 | continue; | |
e0001a05 | 6410 | } |
e0001a05 | 6411 | |
43cd72b9 | 6412 | density_supported = saved_density; |
e0001a05 | 6413 | |
43cd72b9 BW |
6414 | if (e) |
6415 | { | |
6416 | xg_clear_vinsn (vinsn); | |
6417 | return; | |
6418 | } | |
e0001a05 | 6419 | |
0fa77c95 | 6420 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6421 | { |
6422 | TInsn *insn = &slotstack.insn[j]; | |
6423 | if (insn->insn_type == ITYPE_LITERAL) | |
6424 | { | |
9c2799c2 | 6425 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6426 | lit_sym = xg_assemble_literal (insn); |
6427 | } | |
6428 | else | |
6429 | { | |
9c2799c2 | 6430 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6431 | if (lit_sym) |
6432 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6433 | if (j != slotstack.ninsn - 1) |
6434 | emit_single_op (insn); | |
43cd72b9 BW |
6435 | } |
6436 | } | |
6437 | ||
6438 | if (vinsn->num_slots > 1) | |
6439 | { | |
6440 | if (opcode_fits_format_slot | |
6441 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6442 | vinsn->format, i)) | |
6443 | { | |
6444 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6445 | } | |
6446 | else | |
6447 | { | |
b2d179be | 6448 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6449 | if (vinsn->format == XTENSA_UNDEFINED) |
6450 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6451 | else | |
c138bc38 | 6452 | vinsn->slots[i].opcode |
43cd72b9 BW |
6453 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6454 | vinsn->format, i); | |
6455 | ||
6456 | vinsn->slots[i].ntok = 0; | |
6457 | } | |
6458 | } | |
6459 | else | |
6460 | { | |
6461 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6462 | vinsn->format = XTENSA_UNDEFINED; | |
6463 | } | |
6464 | } | |
6465 | } | |
6466 | ||
6467 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6468 | if (resources_conflict (vinsn)) |
43cd72b9 | 6469 | { |
3b4dbbbf | 6470 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6471 | fprintf (stderr, " ops were: "); |
6472 | for (i = 0; i < vinsn->num_slots; i++) | |
6473 | fprintf (stderr, " %s;", | |
6474 | xtensa_opcode_name (xtensa_default_isa, | |
6475 | vinsn->slots[i].opcode)); | |
6476 | fprintf (stderr, "\n"); | |
6477 | xg_clear_vinsn (vinsn); | |
6478 | return; | |
6479 | } | |
6480 | ||
6481 | /* First, find a format that works. */ | |
6482 | if (vinsn->format == XTENSA_UNDEFINED) | |
6483 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6484 | ||
6485 | xg_assemble_vliw_tokens (vinsn); | |
6486 | ||
6487 | xg_clear_vinsn (vinsn); | |
a82c7d90 DW |
6488 | |
6489 | xtensa_check_frag_count (); | |
43cd72b9 BW |
6490 | } |
6491 | ||
6492 | ||
6493 | /* Given an vliw instruction, what conflicts are there in register | |
6494 | usage and in writes to states and queues? | |
6495 | ||
6496 | This function does two things: | |
6497 | 1. Reports an error when a vinsn contains illegal combinations | |
6498 | of writes to registers states or queues. | |
6499 | 2. Marks individual tinsns as not relaxable if the combination | |
6500 | contains antidependencies. | |
6501 | ||
6502 | Job 2 handles things like swap semantics in instructions that need | |
6503 | to be relaxed. For example, | |
6504 | ||
6505 | addi a0, a1, 100000 | |
6506 | ||
6507 | normally would be relaxed to | |
6508 | ||
6509 | l32r a0, some_label | |
6510 | add a0, a1, a0 | |
6511 | ||
6512 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6513 | ||
6514 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6515 | ||
6516 | then we can't relax it into | |
6517 | ||
6518 | l32r a0, some_label | |
6519 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6520 | ||
6521 | because the value of a0 is trashed before the second add can read it. */ | |
6522 | ||
7fa3d080 BW |
6523 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6524 | ||
43cd72b9 | 6525 | static bfd_boolean |
7fa3d080 | 6526 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6527 | { |
6528 | int i, j; | |
6529 | int branches = 0; | |
6530 | xtensa_isa isa = xtensa_default_isa; | |
6531 | ||
9c2799c2 | 6532 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6533 | |
6534 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6535 | { | |
6536 | TInsn *op1 = &vinsn->slots[i]; | |
6537 | if (op1->is_specific_opcode) | |
6538 | op1->keep_wide = TRUE; | |
6539 | else | |
6540 | op1->keep_wide = FALSE; | |
6541 | } | |
6542 | ||
6543 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6544 | { | |
6545 | TInsn *op1 = &vinsn->slots[i]; | |
6546 | ||
6547 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6548 | branches++; | |
6549 | ||
6550 | for (j = 0; j < vinsn->num_slots; j++) | |
6551 | { | |
6552 | if (i != j) | |
6553 | { | |
6554 | TInsn *op2 = &vinsn->slots[j]; | |
6555 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6556 | switch (conflict_type) | |
6557 | { | |
6558 | case 'c': | |
6559 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6560 | xtensa_opcode_name (isa, op1->opcode), i, | |
6561 | xtensa_opcode_name (isa, op2->opcode), j); | |
6562 | return TRUE; | |
6563 | case 'd': | |
6564 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6565 | xtensa_opcode_name (isa, op1->opcode), i, | |
6566 | xtensa_opcode_name (isa, op2->opcode), j); | |
6567 | return TRUE; | |
6568 | case 'e': | |
53dfbcc7 | 6569 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6570 | xtensa_opcode_name (isa, op1->opcode), i, |
6571 | xtensa_opcode_name (isa, op2->opcode), j); | |
6572 | return TRUE; | |
6573 | case 'f': | |
53dfbcc7 | 6574 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6575 | xtensa_opcode_name (isa, op1->opcode), i, |
6576 | xtensa_opcode_name (isa, op2->opcode), j); | |
6577 | return TRUE; | |
6578 | default: | |
6579 | /* Everything is OK. */ | |
6580 | break; | |
6581 | } | |
6582 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6583 | || conflict_type == 'a'); | |
6584 | } | |
6585 | } | |
6586 | } | |
6587 | ||
6588 | if (branches > 1) | |
6589 | { | |
6590 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6591 | return TRUE; | |
6592 | } | |
6593 | ||
6594 | return FALSE; | |
6595 | } | |
6596 | ||
6597 | ||
a1ace8d8 | 6598 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6599 | Cases found are: |
6600 | ||
6601 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6602 | case B: no relationship between what is read and written (both could | |
6603 | read the same reg though) | |
c138bc38 | 6604 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6605 | bundle) |
6606 | case D: t1 writes a state that t2 also writes | |
6607 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6608 | case F: two volatile queue accesses |
43cd72b9 BW |
6609 | */ |
6610 | ||
6611 | static char | |
7fa3d080 | 6612 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6613 | { |
6614 | xtensa_isa isa = xtensa_default_isa; | |
6615 | xtensa_regfile t1_regfile, t2_regfile; | |
6616 | int t1_reg, t2_reg; | |
6617 | int t1_base_reg, t1_last_reg; | |
6618 | int t2_base_reg, t2_last_reg; | |
6619 | char t1_inout, t2_inout; | |
6620 | int i, j; | |
6621 | char conflict = 'b'; | |
6622 | int t1_states; | |
6623 | int t2_states; | |
6624 | int t1_interfaces; | |
6625 | int t2_interfaces; | |
6626 | bfd_boolean t1_volatile = FALSE; | |
6627 | bfd_boolean t2_volatile = FALSE; | |
6628 | ||
6629 | /* Check registers. */ | |
6630 | for (j = 0; j < t2->ntok; j++) | |
6631 | { | |
6632 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6633 | continue; | |
6634 | ||
6635 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6636 | t2_base_reg = t2->tok[j].X_add_number; | |
6637 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6638 | ||
6639 | for (i = 0; i < t1->ntok; i++) | |
6640 | { | |
6641 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6642 | continue; | |
6643 | ||
6644 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6645 | ||
6646 | if (t1_regfile != t2_regfile) | |
6647 | continue; | |
6648 | ||
6649 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6650 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6651 | ||
6652 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6653 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6654 | { | |
6655 | if (t1_inout == 'm' || t1_inout == 'o' | |
6656 | || t2_inout == 'm' || t2_inout == 'o') | |
6657 | { | |
6658 | conflict = 'a'; | |
6659 | continue; | |
6660 | } | |
6661 | } | |
6662 | ||
6663 | t1_base_reg = t1->tok[i].X_add_number; | |
6664 | t1_last_reg = (t1_base_reg | |
6665 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6666 | ||
6667 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6668 | { | |
6669 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6670 | { | |
6671 | if (t1_reg != t2_reg) | |
6672 | continue; | |
6673 | ||
6674 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6675 | { |
6676 | conflict = 'a'; | |
6677 | continue; | |
6678 | } | |
43cd72b9 | 6679 | |
7fa3d080 BW |
6680 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6681 | { | |
6682 | conflict = 'a'; | |
6683 | continue; | |
6684 | } | |
43cd72b9 | 6685 | |
7fa3d080 BW |
6686 | if (t1_inout != 'i' && t2_inout != 'i') |
6687 | return 'c'; | |
6688 | } | |
6689 | } | |
6690 | } | |
6691 | } | |
43cd72b9 | 6692 | |
7fa3d080 BW |
6693 | /* Check states. */ |
6694 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6695 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6696 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6697 | { |
7fa3d080 BW |
6698 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6699 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6700 | for (i = 0; i < t1_states; i++) | |
6701 | { | |
6702 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6703 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6704 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6705 | continue; |
43cd72b9 | 6706 | |
7fa3d080 BW |
6707 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6708 | { | |
6709 | conflict = 'a'; | |
6710 | continue; | |
6711 | } | |
c138bc38 | 6712 | |
7fa3d080 BW |
6713 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6714 | { | |
6715 | conflict = 'a'; | |
6716 | continue; | |
6717 | } | |
c138bc38 | 6718 | |
7fa3d080 BW |
6719 | if (t1_inout != 'i' && t2_inout != 'i') |
6720 | return 'd'; | |
c138bc38 | 6721 | } |
7fa3d080 | 6722 | } |
43cd72b9 | 6723 | |
7fa3d080 BW |
6724 | /* Check tieports. */ |
6725 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6726 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6727 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6728 | { |
7fa3d080 BW |
6729 | xtensa_interface t2_int |
6730 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6731 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6732 | ||
53dfbcc7 | 6733 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6734 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6735 | t2_volatile = TRUE; |
a1ace8d8 | 6736 | |
7fa3d080 BW |
6737 | for (i = 0; i < t1_interfaces; i++) |
6738 | { | |
6739 | xtensa_interface t1_int | |
6740 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6741 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6742 | |
53dfbcc7 | 6743 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6744 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6745 | t1_volatile = TRUE; |
a1ace8d8 BW |
6746 | |
6747 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6748 | return 'f'; | |
c138bc38 | 6749 | |
7fa3d080 BW |
6750 | if (t1_int != t2_int) |
6751 | continue; | |
c138bc38 | 6752 | |
7fa3d080 BW |
6753 | if (t2_inout == 'i' && t1_inout == 'o') |
6754 | { | |
6755 | conflict = 'a'; | |
6756 | continue; | |
6757 | } | |
c138bc38 | 6758 | |
7fa3d080 BW |
6759 | if (t1_inout == 'i' && t2_inout == 'o') |
6760 | { | |
6761 | conflict = 'a'; | |
6762 | continue; | |
6763 | } | |
c138bc38 | 6764 | |
7fa3d080 BW |
6765 | if (t1_inout != 'i' && t2_inout != 'i') |
6766 | return 'e'; | |
6767 | } | |
43cd72b9 | 6768 | } |
c138bc38 | 6769 | |
7fa3d080 | 6770 | return conflict; |
43cd72b9 BW |
6771 | } |
6772 | ||
6773 | ||
6774 | static xtensa_format | |
7fa3d080 | 6775 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6776 | { |
6777 | /* Right now we assume that the ops within the vinsn are properly | |
6778 | ordered for the slots that the programmer wanted them in. In | |
6779 | other words, we don't rearrange the ops in hopes of finding a | |
6780 | better format. The scheduler handles that. */ | |
6781 | ||
6782 | xtensa_isa isa = xtensa_default_isa; | |
6783 | xtensa_format format; | |
43cd72b9 BW |
6784 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6785 | ||
65738a7d BW |
6786 | if (vinsn->num_slots == 1) |
6787 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6788 | ||
43cd72b9 BW |
6789 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6790 | { | |
d8392fd9 SA |
6791 | vliw_insn v_copy; |
6792 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6793 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6794 | { | |
6795 | int slot; | |
6796 | int fit = 0; | |
6797 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6798 | { | |
6799 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6800 | { | |
6801 | v_copy.slots[slot].opcode = | |
6802 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6803 | v_copy.slots[slot].ntok = 0; | |
6804 | } | |
6805 | ||
6806 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6807 | format, slot)) | |
6808 | fit++; | |
7fa3d080 | 6809 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6810 | { |
7fa3d080 BW |
6811 | TInsn widened; |
6812 | /* Try the widened version. */ | |
6813 | if (!v_copy.slots[slot].keep_wide | |
6814 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6815 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6816 | &widened, TRUE) | |
7fa3d080 BW |
6817 | && opcode_fits_format_slot (widened.opcode, |
6818 | format, slot)) | |
43cd72b9 | 6819 | { |
7fa3d080 BW |
6820 | v_copy.slots[slot] = widened; |
6821 | fit++; | |
43cd72b9 BW |
6822 | } |
6823 | } | |
6824 | } | |
6825 | if (fit == v_copy.num_slots) | |
6826 | { | |
d8392fd9 | 6827 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6828 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6829 | vinsn->format = format; | |
6830 | break; | |
6831 | } | |
6832 | } | |
6833 | } | |
6834 | ||
6835 | if (format == xtensa_isa_num_formats (isa)) | |
6836 | return XTENSA_UNDEFINED; | |
6837 | ||
6838 | return format; | |
6839 | } | |
6840 | ||
6841 | ||
6842 | /* Return the additional space needed in a frag | |
6843 | for possible relaxations of any ops in a VLIW insn. | |
6844 | Also fill out the relaxations that might be required of | |
6845 | each tinsn in the vinsn. */ | |
6846 | ||
6847 | static int | |
e7da6241 | 6848 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6849 | { |
e7da6241 | 6850 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6851 | int extra_space = 0; |
6852 | int slot; | |
6853 | ||
6854 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6855 | { | |
6856 | TInsn *tinsn = &vinsn->slots[slot]; | |
6857 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6858 | { | |
6859 | /* A narrow instruction could be widened later to help | |
6860 | alignment issues. */ | |
84b08ed9 | 6861 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6862 | && !tinsn->is_specific_opcode |
6863 | && vinsn->num_slots == 1) | |
6864 | { | |
6865 | /* Difference in bytes between narrow and wide insns... */ | |
6866 | extra_space += 1; | |
6867 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6868 | } |
6869 | } | |
6870 | else | |
6871 | { | |
b08b5071 BW |
6872 | if (workaround_b_j_loop_end |
6873 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6874 | && use_transform ()) |
6875 | { | |
6876 | /* Add 2 of these. */ | |
6877 | extra_space += 3; /* for the nop size */ | |
6878 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6879 | } | |
c138bc38 | 6880 | |
43cd72b9 BW |
6881 | /* Need to assemble it with space for the relocation. */ |
6882 | if (xg_is_relaxable_insn (tinsn, 0) | |
6883 | && !tinsn->is_specific_opcode) | |
6884 | { | |
6885 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6886 | int max_literal_size = | |
6887 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6888 | |
43cd72b9 | 6889 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6890 | |
43cd72b9 | 6891 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6892 | extra_space += max_size; |
6893 | } | |
6894 | else | |
6895 | { | |
e7da6241 BW |
6896 | /* A fix record will be added for this instruction prior |
6897 | to relaxation, so make it end the frag. */ | |
6898 | finish_frag = TRUE; | |
43cd72b9 BW |
6899 | } |
6900 | } | |
6901 | } | |
e7da6241 | 6902 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6903 | return extra_space; |
6904 | } | |
6905 | ||
6906 | ||
6907 | static void | |
b2d179be | 6908 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6909 | { |
6910 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6911 | int slot, chosen_slot; |
43cd72b9 | 6912 | |
b2d179be | 6913 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6914 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6915 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6916 | |
b2d179be BW |
6917 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6918 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6919 | { |
b2d179be BW |
6920 | if (slot == chosen_slot) |
6921 | vinsn->slots[slot] = *tinsn; | |
6922 | else | |
6923 | { | |
6924 | vinsn->slots[slot].opcode = | |
6925 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6926 | vinsn->slots[slot].ntok = 0; | |
6927 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6928 | } | |
43cd72b9 | 6929 | } |
43cd72b9 BW |
6930 | } |
6931 | ||
6932 | ||
6933 | static bfd_boolean | |
7fa3d080 | 6934 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6935 | { |
6936 | int i; | |
6937 | IStack istack; /* put instructions into here */ | |
6938 | symbolS *lit_sym = NULL; | |
6939 | symbolS *label_sym = NULL; | |
6940 | ||
6941 | istack_init (&istack); | |
6942 | ||
6943 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6944 | Because the scheduling and bundling characteristics of movi and |
6945 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6946 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6947 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6948 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6949 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6950 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6951 | || orig_insn->tok[1].X_op == O_pltrel |
6952 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6953 | || orig_insn->tok[1].X_op == O_tlsarg | |
6954 | || orig_insn->tok[1].X_op == O_tpoff | |
6955 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6956 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6957 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6958 | else | |
6959 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6960 | return TRUE; | |
6961 | ||
6962 | for (i = 0; i < istack.ninsn; i++) | |
6963 | { | |
6964 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6965 | switch (insn->insn_type) |
43cd72b9 BW |
6966 | { |
6967 | case ITYPE_LITERAL: | |
9c2799c2 | 6968 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6969 | lit_sym = xg_assemble_literal (insn); |
6970 | break; | |
6971 | case ITYPE_LABEL: | |
6972 | { | |
6973 | static int relaxed_sym_idx = 0; | |
325801bd | 6974 | char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); |
43cd72b9 BW |
6975 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); |
6976 | colon (label); | |
9c2799c2 | 6977 | gas_assert (label_sym == NULL); |
43cd72b9 | 6978 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 6979 | gas_assert (label_sym); |
43cd72b9 BW |
6980 | free (label); |
6981 | } | |
6982 | break; | |
6983 | case ITYPE_INSN: | |
b2d179be BW |
6984 | { |
6985 | vliw_insn v; | |
6986 | if (lit_sym) | |
6987 | xg_resolve_literals (insn, lit_sym); | |
6988 | if (label_sym) | |
6989 | xg_resolve_labels (insn, label_sym); | |
6990 | xg_init_vinsn (&v); | |
6991 | bundle_tinsn (insn, &v); | |
6992 | finish_vinsn (&v); | |
6993 | xg_free_vinsn (&v); | |
6994 | } | |
43cd72b9 BW |
6995 | break; |
6996 | default: | |
9c2799c2 | 6997 | gas_assert (0); |
43cd72b9 BW |
6998 | break; |
6999 | } | |
7000 | } | |
7001 | return FALSE; | |
7002 | } | |
7003 | ||
7004 | ||
34e41783 BW |
7005 | static int |
7006 | total_frag_text_expansion (fragS *fragP) | |
7007 | { | |
7008 | int slot; | |
7009 | int total_expansion = 0; | |
7010 | ||
62af60e2 | 7011 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
7012 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
7013 | ||
7014 | return total_expansion; | |
7015 | } | |
7016 | ||
7017 | ||
43cd72b9 BW |
7018 | /* Emit a vliw instruction to the current fragment. */ |
7019 | ||
7fa3d080 BW |
7020 | static void |
7021 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 7022 | { |
e7da6241 | 7023 | bfd_boolean finish_frag; |
43cd72b9 BW |
7024 | bfd_boolean is_jump = FALSE; |
7025 | bfd_boolean is_branch = FALSE; | |
7026 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
7027 | int insn_size; |
7028 | int extra_space; | |
7029 | char *f = NULL; | |
7030 | int slot; | |
b224e962 BW |
7031 | struct dwarf2_line_info debug_line; |
7032 | bfd_boolean loc_directive_seen = FALSE; | |
7033 | TInsn *tinsn; | |
43cd72b9 | 7034 | |
b224e962 | 7035 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
7036 | |
7037 | if (generating_literals) | |
7038 | { | |
7039 | static int reported = 0; | |
7040 | if (reported < 4) | |
7041 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
7042 | _("cannot assemble into a literal fragment")); | |
7043 | if (reported == 3) | |
7044 | as_bad (_("...")); | |
7045 | reported++; | |
7046 | return; | |
7047 | } | |
7048 | ||
7049 | if (frag_now_fix () != 0 | |
b08b5071 | 7050 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 7051 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
28a0da39 | 7052 | || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
7053 | || (directive_state[directive_longcalls] |
7054 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
7055 | || (directive_state[directive_absolute_literals] |
7056 | != frag_now->tc_frag_data.use_absolute_literals))) | |
7057 | { | |
7058 | frag_wane (frag_now); | |
7059 | frag_new (0); | |
7060 | xtensa_set_frag_assembly_state (frag_now); | |
7061 | } | |
7062 | ||
7063 | if (workaround_a0_b_retw | |
7064 | && vinsn->num_slots == 1 | |
7065 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
7066 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
7067 | && use_transform ()) | |
7068 | { | |
7069 | has_a0_b_retw = TRUE; | |
7070 | ||
7071 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
7072 | After the first assembly pass we will check all of them and | |
7073 | add a nop if needed. */ | |
7074 | frag_now->tc_frag_data.is_insn = TRUE; | |
7075 | frag_var (rs_machine_dependent, 4, 4, | |
7076 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7077 | frag_now->fr_symbol, | |
7078 | frag_now->fr_offset, | |
7079 | NULL); | |
7080 | xtensa_set_frag_assembly_state (frag_now); | |
7081 | frag_now->tc_frag_data.is_insn = TRUE; | |
7082 | frag_var (rs_machine_dependent, 4, 4, | |
7083 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7084 | frag_now->fr_symbol, | |
7085 | frag_now->fr_offset, | |
7086 | NULL); | |
7087 | xtensa_set_frag_assembly_state (frag_now); | |
7088 | } | |
7089 | ||
b224e962 | 7090 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 7091 | { |
b224e962 BW |
7092 | tinsn = &vinsn->slots[slot]; |
7093 | ||
43cd72b9 | 7094 | /* See if the instruction implies an aligned section. */ |
b224e962 | 7095 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 7096 | record_alignment (now_seg, 2); |
c138bc38 | 7097 | |
b224e962 BW |
7098 | /* Determine the best line number for debug info. */ |
7099 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
7100 | && (tinsn->debug_line.filenum != debug_line.filenum | |
7101 | || tinsn->debug_line.line < debug_line.line | |
7102 | || tinsn->debug_line.column < debug_line.column)) | |
7103 | debug_line = tinsn->debug_line; | |
7104 | if (tinsn->loc_directive_seen) | |
7105 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
7106 | } |
7107 | ||
7108 | /* Special cases for instructions that force an alignment... */ | |
7109 | /* None of these opcodes are bundle-able. */ | |
7110 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
7111 | { | |
d77b99c9 | 7112 | int max_fill; |
c138bc38 | 7113 | |
05d58145 BW |
7114 | /* Remember the symbol that marks the end of the loop in the frag |
7115 | that marks the start of the loop. This way we can easily find | |
7116 | the end of the loop at the beginning, without adding special code | |
7117 | to mark the loop instructions themselves. */ | |
7118 | symbolS *target_sym = NULL; | |
7119 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7120 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7121 | ||
43cd72b9 BW |
7122 | xtensa_set_frag_assembly_state (frag_now); |
7123 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 7124 | |
43cd72b9 BW |
7125 | max_fill = get_text_align_max_fill_size |
7126 | (get_text_align_power (xtensa_fetch_width), | |
7127 | TRUE, frag_now->tc_frag_data.is_no_density); | |
7128 | ||
7129 | if (use_transform ()) | |
7130 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7131 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7132 | else |
c138bc38 | 7133 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7134 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7135 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7136 | } |
7137 | ||
b08b5071 | 7138 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7139 | && !vinsn->slots[0].is_specific_opcode) |
7140 | { | |
7141 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7142 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7143 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7144 | } | |
7145 | ||
7146 | if (vinsn->num_slots == 1) | |
7147 | { | |
7148 | if (workaround_a0_b_retw && use_transform ()) | |
7149 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7150 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7151 | ||
7152 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7153 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7154 | } | |
7155 | else | |
7156 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7157 | ||
7158 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7159 | ||
e7da6241 | 7160 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7161 | |
7162 | /* vinsn_to_insnbuf will produce the error. */ | |
7163 | if (vinsn->format != XTENSA_UNDEFINED) | |
7164 | { | |
d77b99c9 | 7165 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7166 | xtensa_set_frag_assembly_state (frag_now); |
7167 | frag_now->tc_frag_data.is_insn = TRUE; | |
7168 | } | |
7169 | ||
e7da6241 | 7170 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7171 | if (vinsn->format == XTENSA_UNDEFINED) |
7172 | return; | |
7173 | ||
d77b99c9 | 7174 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7175 | |
b224e962 BW |
7176 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7177 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7178 | &debug_line); | |
43cd72b9 BW |
7179 | |
7180 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7181 | { | |
b224e962 | 7182 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7183 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7184 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7185 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 | 7186 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
b46824bd MF |
7187 | if (tinsn->opcode == xtensa_l32r_opcode) |
7188 | { | |
7189 | frag_now->tc_frag_data.literal_frags[slot] = | |
7190 | tinsn->tok[1].X_add_symbol->sy_frag; | |
7191 | } | |
43cd72b9 BW |
7192 | if (tinsn->literal_space != 0) |
7193 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7194 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7195 | |
7196 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7197 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7198 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7199 | is_jump = TRUE; | |
7200 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7201 | is_branch = TRUE; | |
7202 | ||
e7da6241 BW |
7203 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7204 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7205 | finish_frag = TRUE; |
7206 | } | |
7207 | ||
7208 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7209 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7210 | |
7211 | if (finish_frag) | |
7212 | { | |
7213 | frag_variant (rs_machine_dependent, | |
7214 | extra_space, extra_space, RELAX_SLOTS, | |
7215 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7216 | xtensa_set_frag_assembly_state (frag_now); | |
7217 | } | |
7218 | ||
7219 | /* Special cases for loops: | |
7220 | close_loop_end should be inserted AFTER short_loop. | |
7221 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7222 | when converting them. */ | |
7223 | ||
7224 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7225 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7226 | && !vinsn->slots[0].is_specific_opcode) |
7227 | { | |
7228 | if (workaround_short_loop && use_transform ()) | |
7229 | { | |
7230 | maybe_has_short_loop = TRUE; | |
7231 | frag_now->tc_frag_data.is_insn = TRUE; | |
7232 | frag_var (rs_machine_dependent, 4, 4, | |
7233 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7234 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7235 | frag_now->tc_frag_data.is_insn = TRUE; | |
7236 | frag_var (rs_machine_dependent, 4, 4, | |
7237 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7238 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7239 | } | |
7240 | ||
7241 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7242 | loop at least 12 bytes away from another loop's end. */ | |
7243 | if (workaround_close_loop_end && use_transform ()) | |
7244 | { | |
7245 | maybe_has_close_loop_end = TRUE; | |
7246 | frag_now->tc_frag_data.is_insn = TRUE; | |
7247 | frag_var (rs_machine_dependent, 12, 12, | |
7248 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7249 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7250 | } | |
7251 | } | |
7252 | ||
7253 | if (use_transform ()) | |
7254 | { | |
7255 | if (is_jump) | |
7256 | { | |
9c2799c2 | 7257 | gas_assert (finish_frag); |
43cd72b9 | 7258 | frag_var (rs_machine_dependent, |
1beeb686 | 7259 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7260 | RELAX_UNREACHABLE, |
7261 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7262 | xtensa_set_frag_assembly_state (frag_now); | |
a82c7d90 | 7263 | xtensa_maybe_create_trampoline_frag (); |
b46824bd MF |
7264 | /* Always create one here. */ |
7265 | xtensa_maybe_create_literal_pool_frag (TRUE, FALSE); | |
43cd72b9 | 7266 | } |
7b1cc377 | 7267 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7268 | { |
9c2799c2 | 7269 | gas_assert (finish_frag); |
43cd72b9 | 7270 | frag_var (rs_machine_dependent, |
1beeb686 | 7271 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7272 | RELAX_MAYBE_UNREACHABLE, |
7273 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7274 | xtensa_set_frag_assembly_state (frag_now); | |
7275 | frag_var (rs_machine_dependent, | |
7276 | 0, 0, | |
7277 | RELAX_MAYBE_DESIRE_ALIGN, | |
7278 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7279 | xtensa_set_frag_assembly_state (frag_now); | |
7280 | } | |
7281 | } | |
7282 | ||
7283 | /* Now, if the original opcode was a call... */ | |
7284 | if (do_align_targets () | |
7285 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7286 | { | |
b08b5071 | 7287 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7288 | frag_now->tc_frag_data.is_insn = TRUE; |
7289 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7290 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7291 | xtensa_set_frag_assembly_state (frag_now); | |
7292 | } | |
7293 | ||
7294 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7295 | { | |
7296 | frag_wane (frag_now); | |
7297 | frag_new (0); | |
7298 | xtensa_set_frag_assembly_state (frag_now); | |
7299 | } | |
7300 | } | |
7301 | ||
7302 | \f | |
7fa3d080 BW |
7303 | /* xtensa_end and helper functions. */ |
7304 | ||
7305 | static void xtensa_cleanup_align_frags (void); | |
7306 | static void xtensa_fix_target_frags (void); | |
7307 | static void xtensa_mark_narrow_branches (void); | |
7308 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7309 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7310 | static void xtensa_fix_a0_b_retw_frags (void); |
7311 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7312 | static void xtensa_fix_close_loop_end_frags (void); | |
7313 | static void xtensa_fix_short_loop_frags (void); | |
7314 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7315 | static void xtensa_add_config_info (void); |
7fa3d080 | 7316 | |
43cd72b9 | 7317 | void |
7fa3d080 | 7318 | xtensa_end (void) |
43cd72b9 BW |
7319 | { |
7320 | directive_balance (); | |
7321 | xtensa_flush_pending_output (); | |
7322 | ||
7323 | past_xtensa_end = TRUE; | |
7324 | ||
7325 | xtensa_move_literals (); | |
7326 | ||
7327 | xtensa_reorder_segments (); | |
7328 | xtensa_cleanup_align_frags (); | |
7329 | xtensa_fix_target_frags (); | |
7330 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7331 | xtensa_fix_a0_b_retw_frags (); | |
7332 | if (workaround_b_j_loop_end) | |
7333 | xtensa_fix_b_j_loop_end_frags (); | |
7334 | ||
7335 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7336 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7337 | xtensa_fix_close_loop_end_frags (); | |
7338 | ||
7339 | if (workaround_short_loop && maybe_has_short_loop) | |
7340 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7341 | if (align_targets) |
7342 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7343 | xtensa_mark_zcl_first_insns (); |
7344 | ||
7345 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7346 | |
7347 | xtensa_add_config_info (); | |
a82c7d90 DW |
7348 | |
7349 | xtensa_check_frag_count (); | |
43cd72b9 BW |
7350 | } |
7351 | ||
7352 | ||
a82c7d90 DW |
7353 | struct trampoline_frag |
7354 | { | |
7355 | struct trampoline_frag *next; | |
7356 | bfd_boolean needs_jump_around; | |
7357 | fragS *fragP; | |
7358 | fixS *fixP; | |
7359 | }; | |
7360 | ||
7361 | struct trampoline_seg | |
7362 | { | |
7363 | struct trampoline_seg *next; | |
7364 | asection *seg; | |
7365 | struct trampoline_frag trampoline_list; | |
7366 | }; | |
7367 | ||
7368 | static struct trampoline_seg trampoline_seg_list; | |
7369 | #define J_RANGE (128 * 1024) | |
7370 | ||
7371 | static int unreachable_count = 0; | |
7372 | ||
7373 | ||
7374 | static void | |
7375 | xtensa_maybe_create_trampoline_frag (void) | |
7376 | { | |
7377 | if (!use_trampolines) | |
7378 | return; | |
7379 | ||
7380 | /* We create an area for possible trampolines every 10 unreachable frags. | |
7381 | These are preferred over the ones not preceded by an unreachable frag, | |
7382 | because we don't have to jump around them. This function is called after | |
7383 | each RELAX_UNREACHABLE frag is created. */ | |
7384 | ||
7385 | if (++unreachable_count > 10) | |
7386 | { | |
7387 | xtensa_create_trampoline_frag (FALSE); | |
7388 | clear_frag_count (); | |
7389 | unreachable_count = 0; | |
7390 | } | |
7391 | } | |
7392 | ||
7393 | static void | |
7394 | xtensa_check_frag_count (void) | |
7395 | { | |
7396 | if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) | |
7397 | return; | |
7398 | ||
7399 | /* We create an area for possible trampolines every 8000 frags or so. This | |
7400 | is an estimate based on the max range of a "j" insn (+/-128K) divided | |
7401 | by a typical frag byte count (16), minus a few for safety. This function | |
7402 | is called after each source line is processed. */ | |
7403 | ||
7404 | if (get_frag_count () > 8000) | |
7405 | { | |
7406 | xtensa_create_trampoline_frag (TRUE); | |
7407 | clear_frag_count (); | |
7408 | unreachable_count = 0; | |
7409 | } | |
b46824bd MF |
7410 | |
7411 | /* We create an area for a possible literal pool every N (default 5000) | |
7412 | frags or so. */ | |
7413 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); | |
a82c7d90 DW |
7414 | } |
7415 | ||
7416 | static xtensa_insnbuf trampoline_buf = NULL; | |
7417 | static xtensa_insnbuf trampoline_slotbuf = NULL; | |
7418 | ||
b46824bd MF |
7419 | static xtensa_insnbuf litpool_buf = NULL; |
7420 | static xtensa_insnbuf litpool_slotbuf = NULL; | |
7421 | ||
a82c7d90 DW |
7422 | #define TRAMPOLINE_FRAG_SIZE 3000 |
7423 | ||
7424 | static void | |
7425 | xtensa_create_trampoline_frag (bfd_boolean needs_jump_around) | |
7426 | { | |
7427 | /* Emit a frag where we can place intermediate jump instructions, | |
7428 | in case we need to jump farther than 128K bytes. | |
7429 | Each jump instruction takes three bytes. | |
7430 | We allocate enough for 1000 trampolines in each frag. | |
7431 | If that's not enough, oh well. */ | |
7432 | ||
7433 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7434 | struct trampoline_frag *tf; | |
7435 | char *varP; | |
7436 | fragS *fragP; | |
7437 | int size = TRAMPOLINE_FRAG_SIZE; | |
7438 | ||
7439 | for ( ; ts; ts = ts->next) | |
7440 | { | |
7441 | if (ts->seg == now_seg) | |
7442 | break; | |
7443 | } | |
7444 | ||
7445 | if (ts == NULL) | |
7446 | { | |
add39d23 | 7447 | ts = XCNEW(struct trampoline_seg); |
a82c7d90 DW |
7448 | ts->next = trampoline_seg_list.next; |
7449 | trampoline_seg_list.next = ts; | |
7450 | ts->seg = now_seg; | |
7451 | } | |
7452 | ||
7453 | frag_wane (frag_now); | |
7454 | frag_new (0); | |
7455 | xtensa_set_frag_assembly_state (frag_now); | |
7456 | varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); | |
7457 | fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); | |
7458 | if (trampoline_buf == NULL) | |
7459 | { | |
7460 | trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7461 | trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7462 | } | |
325801bd | 7463 | tf = XNEW (struct trampoline_frag); |
a82c7d90 DW |
7464 | tf->next = ts->trampoline_list.next; |
7465 | ts->trampoline_list.next = tf; | |
7466 | tf->needs_jump_around = needs_jump_around; | |
7467 | tf->fragP = fragP; | |
7468 | tf->fixP = NULL; | |
7469 | } | |
7470 | ||
7471 | ||
7472 | static struct trampoline_seg * | |
7473 | find_trampoline_seg (asection *seg) | |
7474 | { | |
7475 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7476 | ||
7477 | for ( ; ts; ts = ts->next) | |
7478 | { | |
7479 | if (ts->seg == seg) | |
7480 | return ts; | |
7481 | } | |
7482 | ||
7483 | return NULL; | |
7484 | } | |
7485 | ||
7486 | ||
7487 | void dump_trampolines (void); | |
7488 | ||
7489 | void | |
7490 | dump_trampolines (void) | |
7491 | { | |
7492 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7493 | ||
7494 | for ( ; ts; ts = ts->next) | |
7495 | { | |
7496 | asection *seg = ts->seg; | |
7497 | ||
7498 | if (seg == NULL) | |
7499 | continue; | |
7500 | fprintf(stderr, "SECTION %s\n", seg->name); | |
7501 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
7502 | for ( ; tf; tf = tf->next) | |
7503 | { | |
7504 | if (tf->fragP == NULL) | |
7505 | continue; | |
7506 | fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", | |
7507 | (int)tf->fragP->fr_address, (int)tf->fragP->fr_fix, | |
7508 | tf->needs_jump_around ? "T" : "F"); | |
7509 | } | |
7510 | } | |
7511 | } | |
7512 | ||
b46824bd MF |
7513 | static void dump_litpools (void) __attribute__ ((unused)); |
7514 | ||
7515 | static void | |
7516 | dump_litpools (void) | |
7517 | { | |
7518 | struct litpool_seg *lps = litpool_seg_list.next; | |
7519 | struct litpool_frag *lpf; | |
7520 | ||
7521 | for ( ; lps ; lps = lps->next ) | |
7522 | { | |
7523 | printf("litpool seg %s\n", lps->seg->name); | |
7524 | for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) | |
7525 | { | |
7526 | fragS *litfrag = lpf->fragP->fr_next; | |
7527 | int count = 0; | |
7528 | while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) | |
7529 | { | |
7530 | if (litfrag->fr_fix == 4) | |
7531 | count++; | |
7532 | litfrag = litfrag->fr_next; | |
7533 | } | |
7534 | printf(" %ld <%d:%d> (%d) [%d]: ", | |
7535 | lpf->addr, lpf->priority, lpf->original_priority, | |
7536 | lpf->fragP->fr_line, count); | |
7537 | //dump_frag(lpf->fragP); | |
7538 | } | |
7539 | } | |
7540 | } | |
7541 | ||
7542 | static void | |
7543 | xtensa_maybe_create_literal_pool_frag (bfd_boolean create, | |
7544 | bfd_boolean only_if_needed) | |
7545 | { | |
7546 | struct litpool_seg *lps = litpool_seg_list.next; | |
7547 | fragS *fragP; | |
7548 | struct litpool_frag *lpf; | |
7549 | bfd_boolean needed = FALSE; | |
7550 | ||
7551 | if (use_literal_section || !auto_litpools) | |
7552 | return; | |
7553 | ||
7554 | for ( ; lps ; lps = lps->next ) | |
7555 | { | |
7556 | if (lps->seg == now_seg) | |
7557 | break; | |
7558 | } | |
7559 | ||
7560 | if (lps == NULL) | |
7561 | { | |
add39d23 | 7562 | lps = XCNEW (struct litpool_seg); |
b46824bd MF |
7563 | lps->next = litpool_seg_list.next; |
7564 | litpool_seg_list.next = lps; | |
7565 | lps->seg = now_seg; | |
7566 | lps->frag_list.next = &lps->frag_list; | |
7567 | lps->frag_list.prev = &lps->frag_list; | |
947fa914 MF |
7568 | /* Put candidate literal pool at the beginning of every section, |
7569 | so that even when section starts with literal load there's a | |
7570 | literal pool available. */ | |
7571 | lps->frag_count = auto_litpool_limit; | |
b46824bd MF |
7572 | } |
7573 | ||
7574 | lps->frag_count++; | |
7575 | ||
7576 | if (create) | |
7577 | { | |
7578 | if (only_if_needed) | |
7579 | { | |
7580 | if (past_xtensa_end || !use_transform() || | |
7581 | frag_now->tc_frag_data.is_no_transform) | |
7582 | { | |
7583 | return; | |
7584 | } | |
7585 | if (auto_litpool_limit <= 0) | |
7586 | { | |
7587 | /* Don't create a litpool based only on frag count. */ | |
7588 | return; | |
7589 | } | |
7590 | else if (lps->frag_count > auto_litpool_limit) | |
7591 | { | |
7592 | needed = TRUE; | |
7593 | } | |
7594 | else | |
7595 | { | |
7596 | return; | |
7597 | } | |
7598 | } | |
7599 | else | |
7600 | { | |
7601 | needed = TRUE; | |
7602 | } | |
7603 | } | |
7604 | ||
7605 | if (needed) | |
7606 | { | |
7607 | int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ | |
7608 | /* Create a potential site for a literal pool. */ | |
7609 | frag_wane (frag_now); | |
7610 | frag_new (0); | |
7611 | xtensa_set_frag_assembly_state (frag_now); | |
7612 | fragP = frag_now; | |
7613 | fragP->tc_frag_data.lit_frchain = frchain_now; | |
7614 | fragP->tc_frag_data.literal_frag = fragP; | |
7615 | frag_var (rs_machine_dependent, size, size, | |
7616 | (only_if_needed) ? | |
7617 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN : | |
7618 | RELAX_LITERAL_POOL_BEGIN, | |
7619 | NULL, 0, NULL); | |
7620 | frag_now->tc_frag_data.lit_seg = now_seg; | |
7621 | frag_variant (rs_machine_dependent, 0, 0, | |
7622 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); | |
7623 | xtensa_set_frag_assembly_state (frag_now); | |
7624 | } | |
7625 | else | |
7626 | { | |
7627 | /* RELAX_LITERAL_POOL_BEGIN frag is being created; | |
7628 | just record it here. */ | |
7629 | fragP = frag_now; | |
7630 | } | |
7631 | ||
325801bd | 7632 | lpf = XNEW (struct litpool_frag); |
b46824bd MF |
7633 | /* Insert at tail of circular list. */ |
7634 | lpf->addr = 0; | |
7635 | lps->frag_list.prev->next = lpf; | |
7636 | lpf->next = &lps->frag_list; | |
7637 | lpf->prev = lps->frag_list.prev; | |
7638 | lps->frag_list.prev = lpf; | |
7639 | lpf->fragP = fragP; | |
7640 | lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; | |
7641 | lpf->original_priority = lpf->priority; | |
7642 | ||
7643 | lps->frag_count = 0; | |
7644 | } | |
7645 | ||
43cd72b9 | 7646 | static void |
7fa3d080 | 7647 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7648 | { |
7649 | frchainS *frchP; | |
c9049d30 | 7650 | asection *s; |
43cd72b9 | 7651 | |
c9049d30 AM |
7652 | for (s = stdoutput->sections; s; s = s->next) |
7653 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7654 | { | |
7655 | fragS *fragP; | |
7656 | /* Walk over all of the fragments in a subsection. */ | |
7657 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7658 | { | |
7659 | if ((fragP->fr_type == rs_align | |
7660 | || fragP->fr_type == rs_align_code | |
7661 | || (fragP->fr_type == rs_machine_dependent | |
7662 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7663 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7664 | && fragP->fr_fix == 0) | |
7665 | { | |
7666 | fragS *next = fragP->fr_next; | |
7667 | ||
7668 | while (next | |
7669 | && next->fr_fix == 0 | |
7670 | && next->fr_type == rs_machine_dependent | |
7671 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7672 | { | |
7673 | frag_wane (next); | |
7674 | next = next->fr_next; | |
7675 | } | |
7676 | } | |
7677 | /* If we don't widen branch targets, then they | |
7678 | will be easier to align. */ | |
7679 | if (fragP->tc_frag_data.is_branch_target | |
7680 | && fragP->fr_opcode == fragP->fr_literal | |
7681 | && fragP->fr_type == rs_machine_dependent | |
7682 | && fragP->fr_subtype == RELAX_SLOTS | |
7683 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7684 | frag_wane (fragP); | |
7685 | if (fragP->fr_type == rs_machine_dependent | |
7686 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7687 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7688 | } | |
7689 | } | |
43cd72b9 BW |
7690 | } |
7691 | ||
7692 | ||
7693 | /* Re-process all of the fragments looking to convert all of the | |
7694 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7695 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7696 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7697 | |
43cd72b9 | 7698 | static void |
7fa3d080 | 7699 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7700 | { |
7701 | frchainS *frchP; | |
c9049d30 | 7702 | asection *s; |
e0001a05 NC |
7703 | |
7704 | /* When this routine is called, all of the subsections are still intact | |
7705 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7706 | for (s = stdoutput->sections; s; s = s->next) |
7707 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7708 | { | |
7709 | fragS *fragP; | |
e0001a05 | 7710 | |
c9049d30 AM |
7711 | /* Walk over all of the fragments in a subsection. */ |
7712 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7713 | { | |
7714 | if (fragP->fr_type == rs_machine_dependent | |
7715 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7716 | { | |
7717 | if (next_frag_is_branch_target (fragP)) | |
7718 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7719 | else | |
7720 | frag_wane (fragP); | |
7721 | } | |
7722 | } | |
7723 | } | |
e0001a05 NC |
7724 | } |
7725 | ||
7726 | ||
7fa3d080 BW |
7727 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7728 | ||
43cd72b9 | 7729 | static void |
7fa3d080 | 7730 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7731 | { |
7732 | frchainS *frchP; | |
c9049d30 | 7733 | asection *s; |
43cd72b9 | 7734 | |
c9049d30 AM |
7735 | for (s = stdoutput->sections; s; s = s->next) |
7736 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7737 | { | |
7738 | fragS *fragP; | |
7739 | /* Walk over all of the fragments in a subsection. */ | |
7740 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7741 | { | |
7742 | if (fragP->fr_type == rs_machine_dependent | |
7743 | && fragP->fr_subtype == RELAX_SLOTS | |
7744 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7745 | { | |
7746 | vliw_insn vinsn; | |
7747 | ||
7748 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7749 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7750 | ||
7751 | if (vinsn.num_slots == 1 | |
7752 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7753 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7754 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7755 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7756 | &vinsn.slots[0])) | |
7757 | { | |
7758 | fragP->fr_subtype = RELAX_SLOTS; | |
7759 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7760 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7761 | } | |
7762 | } | |
7763 | } | |
7764 | } | |
43cd72b9 BW |
7765 | } |
7766 | ||
7767 | ||
7768 | /* A branch is typically widened only when its target is out of | |
7769 | range. However, we would like to widen them to align a subsequent | |
7770 | branch target when possible. | |
7771 | ||
7772 | Because the branch relaxation code is so convoluted, the optimal solution | |
7773 | (combining the two cases) is difficult to get right in all circumstances. | |
7774 | We therefore go with an "almost as good" solution, where we only | |
7775 | use for alignment narrow branches that definitely will not expand to a | |
7776 | jump and a branch. These functions find and mark these cases. */ | |
7777 | ||
a67517f4 BW |
7778 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7779 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7780 | We start counting beginning with the frag after the 2-byte branch, so the | |
7781 | maximum offset is (4 - 2) + 63 = 65. */ | |
7782 | #define MAX_IMMED6 65 | |
43cd72b9 | 7783 | |
d77b99c9 | 7784 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7785 | |
43cd72b9 | 7786 | static bfd_boolean |
7fa3d080 | 7787 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 7788 | { |
91d6fa6a NC |
7789 | const expressionS *exp = &tinsn->tok[1]; |
7790 | symbolS *symbolP = exp->X_add_symbol; | |
7791 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
7792 | fragS *target_frag; |
7793 | ||
91d6fa6a | 7794 | if (exp->X_op != O_symbol) |
e7da6241 BW |
7795 | return FALSE; |
7796 | ||
7797 | target_frag = symbol_get_frag (symbolP); | |
7798 | ||
43cd72b9 BW |
7799 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7800 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7801 | return FALSE; | |
7802 | ||
7803 | /* The branch doesn't branch over it's own frag, | |
7804 | but over the subsequent ones. */ | |
7805 | fragP = fragP->fr_next; | |
7806 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7807 | { | |
7808 | max_distance += unrelaxed_frag_max_size (fragP); | |
7809 | fragP = fragP->fr_next; | |
7810 | } | |
7811 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7812 | return TRUE; | |
e0001a05 NC |
7813 | return FALSE; |
7814 | } | |
7815 | ||
7816 | ||
43cd72b9 | 7817 | static void |
7fa3d080 | 7818 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7819 | { |
7820 | frchainS *frchP; | |
c9049d30 | 7821 | asection *s; |
43cd72b9 | 7822 | |
c9049d30 AM |
7823 | for (s = stdoutput->sections; s; s = s->next) |
7824 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7825 | { | |
7826 | fragS *fragP; | |
7827 | /* Walk over all of the fragments in a subsection. */ | |
7828 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7829 | { | |
7830 | if (fragP->fr_type == rs_machine_dependent | |
7831 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7832 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7833 | { | |
7834 | /* Find the loop frag. */ | |
3a1e9c4a | 7835 | fragS *loop_frag = next_non_empty_frag (fragP); |
c9049d30 | 7836 | /* Find the first insn frag. */ |
3a1e9c4a SA |
7837 | fragS *targ_frag = next_non_empty_frag (loop_frag); |
7838 | ||
7839 | /* Handle a corner case that comes up in hardware | |
7840 | diagnostics. The original assembly looks like this: | |
3739860c | 7841 | |
3a1e9c4a SA |
7842 | loop aX, LabelA |
7843 | <empty_frag>--not found by next_non_empty_frag | |
7844 | loop aY, LabelB | |
7845 | ||
7846 | Depending on the start address, the assembler may or | |
7847 | may not change it to look something like this: | |
7848 | ||
7849 | loop aX, LabelA | |
7850 | nop--frag isn't empty anymore | |
7851 | loop aY, LabelB | |
7852 | ||
7853 | So set up to check the alignment of the nop if it | |
7854 | exists */ | |
7855 | while (loop_frag != targ_frag) | |
7856 | { | |
7857 | if (loop_frag->fr_type == rs_machine_dependent | |
7858 | && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
3739860c | 7859 | || loop_frag->fr_subtype |
3a1e9c4a SA |
7860 | == RELAX_CHECK_ALIGN_NEXT_OPCODE)) |
7861 | targ_frag = loop_frag; | |
7862 | else | |
7863 | loop_frag = loop_frag->fr_next; | |
7864 | } | |
c9049d30 AM |
7865 | |
7866 | /* Of course, sometimes (mostly for toy test cases) a | |
7867 | zero-cost loop instruction is the last in a section. */ | |
7868 | if (targ_frag) | |
7869 | { | |
7870 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7871 | /* Do not widen a frag that is the first instruction of a | |
7872 | zero-cost loop. It makes that loop harder to align. */ | |
7873 | if (targ_frag->fr_type == rs_machine_dependent | |
7874 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7875 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7876 | == RELAX_NARROW)) | |
7877 | { | |
7878 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7879 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7880 | else | |
7881 | { | |
7882 | frag_wane (targ_frag); | |
7883 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7884 | } | |
7885 | } | |
7886 | } | |
7887 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7888 | frag_wane (fragP); | |
7889 | } | |
7890 | } | |
7891 | } | |
43cd72b9 BW |
7892 | } |
7893 | ||
7894 | ||
fb227da0 BW |
7895 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7896 | sleb128 value, the linker is unable to adjust that value to account for | |
7897 | link-time relaxation. Mark all the code between such symbols so that | |
7898 | its size cannot be changed by linker relaxation. */ | |
3739860c | 7899 | |
6a7eedfe BW |
7900 | static void |
7901 | xtensa_mark_difference_of_two_symbols (void) | |
7902 | { | |
7903 | symbolS *expr_sym; | |
7904 | ||
3739860c | 7905 | for (expr_sym = expr_symbols; expr_sym; |
6a7eedfe BW |
7906 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) |
7907 | { | |
91d6fa6a | 7908 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 7909 | |
91d6fa6a | 7910 | if (exp->X_op == O_subtract) |
6a7eedfe | 7911 | { |
91d6fa6a NC |
7912 | symbolS *left = exp->X_add_symbol; |
7913 | symbolS *right = exp->X_op_symbol; | |
3739860c | 7914 | |
6a7eedfe BW |
7915 | /* Difference of two symbols not in the same section |
7916 | are handled with relocations in the linker. */ | |
7917 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7918 | { | |
7919 | fragS *start; | |
7920 | fragS *end; | |
983f90e3 | 7921 | fragS *walk; |
6a7eedfe | 7922 | |
3739860c | 7923 | if (symbol_get_frag (left)->fr_address |
6a7eedfe BW |
7924 | <= symbol_get_frag (right)->fr_address) |
7925 | { | |
7926 | start = symbol_get_frag (left); | |
7927 | end = symbol_get_frag (right); | |
7928 | } | |
7929 | else | |
7930 | { | |
7931 | start = symbol_get_frag (right); | |
7932 | end = symbol_get_frag (left); | |
7933 | } | |
983f90e3 SA |
7934 | |
7935 | if (start->tc_frag_data.no_transform_end != NULL) | |
7936 | walk = start->tc_frag_data.no_transform_end; | |
7937 | else | |
7938 | walk = start; | |
3739860c | 7939 | do |
6a7eedfe | 7940 | { |
983f90e3 SA |
7941 | walk->tc_frag_data.is_no_transform = 1; |
7942 | walk = walk->fr_next; | |
6a7eedfe | 7943 | } |
983f90e3 SA |
7944 | while (walk && walk->fr_address < end->fr_address); |
7945 | ||
7946 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
7947 | } |
7948 | } | |
7949 | } | |
7950 | } | |
7951 | ||
7952 | ||
e0001a05 NC |
7953 | /* Re-process all of the fragments looking to convert all of the |
7954 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7955 | conditional branch or a retw/retw.n, convert this frag to one that | |
7956 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7957 | ||
7fa3d080 BW |
7958 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7959 | ||
e0001a05 | 7960 | static void |
7fa3d080 | 7961 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7962 | { |
7963 | frchainS *frchP; | |
c9049d30 | 7964 | asection *s; |
e0001a05 NC |
7965 | |
7966 | /* When this routine is called, all of the subsections are still intact | |
7967 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7968 | for (s = stdoutput->sections; s; s = s->next) |
7969 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7970 | { | |
7971 | fragS *fragP; | |
e0001a05 | 7972 | |
c9049d30 AM |
7973 | /* Walk over all of the fragments in a subsection. */ |
7974 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7975 | { | |
7976 | if (fragP->fr_type == rs_machine_dependent | |
7977 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7978 | { | |
7979 | if (next_instrs_are_b_retw (fragP)) | |
7980 | { | |
7981 | if (fragP->tc_frag_data.is_no_transform) | |
7982 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7983 | else | |
7984 | relax_frag_add_nop (fragP); | |
7985 | } | |
7986 | frag_wane (fragP); | |
7987 | } | |
7988 | } | |
7989 | } | |
e0001a05 NC |
7990 | } |
7991 | ||
7992 | ||
7fa3d080 BW |
7993 | static bfd_boolean |
7994 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7995 | { |
7996 | xtensa_opcode opcode; | |
43cd72b9 | 7997 | xtensa_format fmt; |
e0001a05 NC |
7998 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7999 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 8000 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
8001 | xtensa_isa isa = xtensa_default_isa; |
8002 | int offset = 0; | |
43cd72b9 BW |
8003 | int slot; |
8004 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
8005 | |
8006 | if (!insnbuf) | |
43cd72b9 BW |
8007 | { |
8008 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8009 | slotbuf = xtensa_insnbuf_alloc (isa); | |
8010 | } | |
e0001a05 NC |
8011 | |
8012 | if (next_fragP == NULL) | |
8013 | return FALSE; | |
8014 | ||
8015 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
8016 | xtensa_insnbuf_from_chars |
8017 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8018 | fmt = xtensa_format_decode (isa, insnbuf); |
8019 | if (fmt == XTENSA_UNDEFINED) | |
8020 | return FALSE; | |
8021 | ||
8022 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
8023 | { | |
8024 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
8025 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
8026 | ||
8027 | branch_seen = (branch_seen | |
8028 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
8029 | } | |
e0001a05 | 8030 | |
43cd72b9 | 8031 | if (!branch_seen) |
e0001a05 NC |
8032 | return FALSE; |
8033 | ||
43cd72b9 | 8034 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8035 | if (offset == next_fragP->fr_fix) |
8036 | { | |
8037 | next_fragP = next_non_empty_frag (next_fragP); | |
8038 | offset = 0; | |
8039 | } | |
43cd72b9 | 8040 | |
e0001a05 NC |
8041 | if (next_fragP == NULL) |
8042 | return FALSE; | |
8043 | ||
8044 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
8045 | xtensa_insnbuf_from_chars |
8046 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8047 | fmt = xtensa_format_decode (isa, insnbuf); |
8048 | ||
8049 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
8050 | have no problems. */ | |
8051 | if (fmt == XTENSA_UNDEFINED | |
8052 | || xtensa_format_num_slots (isa, fmt) != 1) | |
8053 | return FALSE; | |
8054 | ||
8055 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
8056 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 8057 | |
b08b5071 | 8058 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 8059 | return TRUE; |
43cd72b9 | 8060 | |
e0001a05 NC |
8061 | return FALSE; |
8062 | } | |
8063 | ||
8064 | ||
8065 | /* Re-process all of the fragments looking to convert all of the | |
8066 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
8067 | loop end label, convert this frag to one that will generate a NOP. | |
8068 | In any case close it off with a .fill 0. */ | |
8069 | ||
7fa3d080 BW |
8070 | static bfd_boolean next_instr_is_loop_end (fragS *); |
8071 | ||
e0001a05 | 8072 | static void |
7fa3d080 | 8073 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
8074 | { |
8075 | frchainS *frchP; | |
c9049d30 | 8076 | asection *s; |
e0001a05 NC |
8077 | |
8078 | /* When this routine is called, all of the subsections are still intact | |
8079 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8080 | for (s = stdoutput->sections; s; s = s->next) |
8081 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8082 | { | |
8083 | fragS *fragP; | |
e0001a05 | 8084 | |
c9049d30 AM |
8085 | /* Walk over all of the fragments in a subsection. */ |
8086 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8087 | { | |
8088 | if (fragP->fr_type == rs_machine_dependent | |
8089 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
8090 | { | |
8091 | if (next_instr_is_loop_end (fragP)) | |
8092 | { | |
8093 | if (fragP->tc_frag_data.is_no_transform) | |
8094 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
8095 | else | |
8096 | relax_frag_add_nop (fragP); | |
8097 | } | |
8098 | frag_wane (fragP); | |
8099 | } | |
8100 | } | |
8101 | } | |
e0001a05 NC |
8102 | } |
8103 | ||
8104 | ||
7fa3d080 BW |
8105 | static bfd_boolean |
8106 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
8107 | { |
8108 | const fragS *next_fragP; | |
8109 | ||
8110 | if (next_frag_is_loop_target (fragP)) | |
8111 | return FALSE; | |
8112 | ||
8113 | next_fragP = next_non_empty_frag (fragP); | |
8114 | if (next_fragP == NULL) | |
8115 | return FALSE; | |
8116 | ||
8117 | if (!next_frag_is_loop_target (next_fragP)) | |
8118 | return FALSE; | |
8119 | ||
8120 | /* If the size is >= 3 then there is more than one instruction here. | |
8121 | The hardware bug will not fire. */ | |
8122 | if (next_fragP->fr_fix > 3) | |
8123 | return FALSE; | |
8124 | ||
8125 | return TRUE; | |
8126 | } | |
8127 | ||
8128 | ||
8129 | /* Re-process all of the fragments looking to convert all of the | |
8130 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
8131 | not MY loop's loop end within 12 bytes, add enough nops here to | |
8132 | make it at least 12 bytes away. In any case close it off with a | |
8133 | .fill 0. */ | |
8134 | ||
d77b99c9 | 8135 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 8136 | (fragS *, fragS *, offsetT); |
7fa3d080 | 8137 | |
e0001a05 | 8138 | static void |
7fa3d080 | 8139 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
8140 | { |
8141 | frchainS *frchP; | |
c9049d30 | 8142 | asection *s; |
e0001a05 NC |
8143 | |
8144 | /* When this routine is called, all of the subsections are still intact | |
8145 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8146 | for (s = stdoutput->sections; s; s = s->next) |
8147 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8148 | { | |
8149 | fragS *fragP; | |
e0001a05 | 8150 | |
c9049d30 | 8151 | fragS *current_target = NULL; |
e0001a05 | 8152 | |
c9049d30 AM |
8153 | /* Walk over all of the fragments in a subsection. */ |
8154 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8155 | { | |
8156 | if (fragP->fr_type == rs_machine_dependent | |
8157 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8158 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 8159 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 8160 | |
c9049d30 AM |
8161 | if (current_target |
8162 | && fragP->fr_type == rs_machine_dependent | |
8163 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
8164 | { | |
8165 | offsetT min_bytes; | |
8166 | int bytes_added = 0; | |
e0001a05 NC |
8167 | |
8168 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
8169 | /* Max out at 12. */ |
8170 | min_bytes = min_bytes_to_other_loop_end | |
8171 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
8172 | ||
8173 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
8174 | { | |
8175 | if (fragP->tc_frag_data.is_no_transform) | |
8176 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
8177 | else | |
8178 | { | |
8179 | while (min_bytes + bytes_added | |
8180 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
8181 | { | |
8182 | int length = 3; | |
8183 | ||
8184 | if (fragP->fr_var < length) | |
8185 | as_fatal (_("fr_var %lu < length %d"), | |
8186 | (long) fragP->fr_var, length); | |
8187 | else | |
8188 | { | |
8189 | assemble_nop (length, | |
8190 | fragP->fr_literal + fragP->fr_fix); | |
8191 | fragP->fr_fix += length; | |
8192 | fragP->fr_var -= length; | |
8193 | } | |
8194 | bytes_added += length; | |
8195 | } | |
8196 | } | |
8197 | } | |
8198 | frag_wane (fragP); | |
8199 | } | |
9c2799c2 | 8200 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
8201 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
8202 | } | |
8203 | } | |
e0001a05 NC |
8204 | } |
8205 | ||
8206 | ||
d77b99c9 | 8207 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 8208 | |
d77b99c9 | 8209 | static offsetT |
7fa3d080 BW |
8210 | min_bytes_to_other_loop_end (fragS *fragP, |
8211 | fragS *current_target, | |
d77b99c9 | 8212 | offsetT max_size) |
e0001a05 | 8213 | { |
d77b99c9 | 8214 | offsetT offset = 0; |
e0001a05 NC |
8215 | fragS *current_fragP; |
8216 | ||
8217 | for (current_fragP = fragP; | |
8218 | current_fragP; | |
8219 | current_fragP = current_fragP->fr_next) | |
8220 | { | |
8221 | if (current_fragP->tc_frag_data.is_loop_target | |
8222 | && current_fragP != current_target) | |
05d58145 | 8223 | return offset; |
e0001a05 NC |
8224 | |
8225 | offset += unrelaxed_frag_min_size (current_fragP); | |
8226 | ||
05d58145 | 8227 | if (offset >= max_size) |
e0001a05 NC |
8228 | return max_size; |
8229 | } | |
8230 | return max_size; | |
8231 | } | |
8232 | ||
8233 | ||
d77b99c9 | 8234 | static offsetT |
7fa3d080 | 8235 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 8236 | { |
d77b99c9 | 8237 | offsetT size = fragP->fr_fix; |
e0001a05 | 8238 | |
d77b99c9 | 8239 | /* Add fill size. */ |
e0001a05 NC |
8240 | if (fragP->fr_type == rs_fill) |
8241 | size += fragP->fr_offset; | |
8242 | ||
8243 | return size; | |
8244 | } | |
8245 | ||
8246 | ||
d77b99c9 | 8247 | static offsetT |
7fa3d080 | 8248 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 8249 | { |
d77b99c9 | 8250 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
8251 | switch (fragP->fr_type) |
8252 | { | |
8253 | case 0: | |
c138bc38 | 8254 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
8255 | end up with type 0. */ |
8256 | break; | |
8257 | case rs_fill: | |
8258 | case rs_org: | |
8259 | case rs_space: | |
8260 | size += fragP->fr_offset; | |
8261 | break; | |
8262 | case rs_align: | |
8263 | case rs_align_code: | |
8264 | case rs_align_test: | |
8265 | case rs_leb128: | |
8266 | case rs_cfa: | |
8267 | case rs_dwarf2dbg: | |
8268 | /* No further adjustments needed. */ | |
8269 | break; | |
8270 | case rs_machine_dependent: | |
8271 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
8272 | size += fragP->fr_var; | |
8273 | break; | |
8274 | default: | |
8275 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 8276 | gas_assert (0); |
43cd72b9 BW |
8277 | break; |
8278 | } | |
8279 | ||
8280 | return size; | |
8281 | } | |
8282 | ||
8283 | ||
e0001a05 NC |
8284 | /* Re-process all of the fragments looking to convert all |
8285 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
8286 | ||
8287 | A) | |
8288 | 1) the instruction size count to the loop end label | |
8289 | is too short (<= 2 instructions), | |
8290 | 2) loop has a jump or branch in it | |
8291 | ||
8292 | or B) | |
43cd72b9 | 8293 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
8294 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
8295 | 3) the instruction size count to the loop end label is too short | |
8296 | (<= 2 instructions) | |
8297 | then convert this frag (and maybe the next one) to generate a NOP. | |
8298 | In any case close it off with a .fill 0. */ | |
8299 | ||
d77b99c9 | 8300 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
8301 | static bfd_boolean branch_before_loop_end (fragS *); |
8302 | ||
e0001a05 | 8303 | static void |
7fa3d080 | 8304 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
8305 | { |
8306 | frchainS *frchP; | |
c9049d30 | 8307 | asection *s; |
e0001a05 NC |
8308 | |
8309 | /* When this routine is called, all of the subsections are still intact | |
8310 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8311 | for (s = stdoutput->sections; s; s = s->next) |
8312 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8313 | { | |
8314 | fragS *fragP; | |
c9049d30 | 8315 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; |
e0001a05 | 8316 | |
c9049d30 AM |
8317 | /* Walk over all of the fragments in a subsection. */ |
8318 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8319 | { | |
8320 | if (fragP->fr_type == rs_machine_dependent | |
8321 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8322 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
8323 | { | |
8324 | TInsn t_insn; | |
8325 | fragS *loop_frag = next_non_empty_frag (fragP); | |
8326 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
c9049d30 | 8327 | current_opcode = t_insn.opcode; |
9c2799c2 | 8328 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 8329 | current_opcode) == 1); |
c9049d30 | 8330 | } |
e0001a05 | 8331 | |
c9049d30 AM |
8332 | if (fragP->fr_type == rs_machine_dependent |
8333 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8334 | { | |
8335 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
8336 | && (branch_before_loop_end (fragP->fr_next) | |
8337 | || (workaround_all_short_loops | |
8338 | && current_opcode != XTENSA_UNDEFINED | |
8339 | && current_opcode != xtensa_loop_opcode))) | |
8340 | { | |
8341 | if (fragP->tc_frag_data.is_no_transform) | |
8342 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
8343 | else | |
8344 | relax_frag_add_nop (fragP); | |
8345 | } | |
8346 | frag_wane (fragP); | |
8347 | } | |
8348 | } | |
8349 | } | |
e0001a05 NC |
8350 | } |
8351 | ||
8352 | ||
d77b99c9 | 8353 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 8354 | |
d77b99c9 | 8355 | static int |
7fa3d080 BW |
8356 | count_insns_to_loop_end (fragS *base_fragP, |
8357 | bfd_boolean count_relax_add, | |
d77b99c9 | 8358 | int max_count) |
e0001a05 NC |
8359 | { |
8360 | fragS *fragP = NULL; | |
d77b99c9 | 8361 | int insn_count = 0; |
e0001a05 NC |
8362 | |
8363 | fragP = base_fragP; | |
8364 | ||
8365 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
8366 | { | |
8367 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
8368 | if (insn_count >= max_count) | |
8369 | return max_count; | |
8370 | ||
8371 | if (count_relax_add) | |
8372 | { | |
8373 | if (fragP->fr_type == rs_machine_dependent | |
8374 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8375 | { | |
8376 | /* In order to add the appropriate number of | |
8377 | NOPs, we count an instruction for downstream | |
8378 | occurrences. */ | |
8379 | insn_count++; | |
8380 | if (insn_count >= max_count) | |
8381 | return max_count; | |
8382 | } | |
8383 | } | |
8384 | } | |
8385 | return insn_count; | |
8386 | } | |
8387 | ||
8388 | ||
d77b99c9 | 8389 | static int |
7fa3d080 | 8390 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 8391 | { |
43cd72b9 BW |
8392 | xtensa_isa isa = xtensa_default_isa; |
8393 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 8394 | int insn_count = 0; |
e0001a05 NC |
8395 | int offset = 0; |
8396 | ||
8397 | if (!fragP->tc_frag_data.is_insn) | |
8398 | return insn_count; | |
8399 | ||
43cd72b9 BW |
8400 | if (!insnbuf) |
8401 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8402 | ||
e0001a05 NC |
8403 | /* Decode the fixed instructions. */ |
8404 | while (offset < fragP->fr_fix) | |
8405 | { | |
43cd72b9 BW |
8406 | xtensa_format fmt; |
8407 | ||
d77b99c9 BW |
8408 | xtensa_insnbuf_from_chars |
8409 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8410 | fmt = xtensa_format_decode (isa, insnbuf); |
8411 | ||
8412 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
8413 | { |
8414 | as_fatal (_("undecodable instruction in instruction frag")); | |
8415 | return insn_count; | |
8416 | } | |
43cd72b9 | 8417 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8418 | insn_count++; |
8419 | } | |
8420 | ||
8421 | return insn_count; | |
8422 | } | |
8423 | ||
8424 | ||
7fa3d080 BW |
8425 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
8426 | ||
43cd72b9 | 8427 | static bfd_boolean |
7fa3d080 | 8428 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
8429 | { |
8430 | fragS *fragP; | |
8431 | ||
8432 | for (fragP = base_fragP; | |
8433 | fragP && !fragP->tc_frag_data.is_loop_target; | |
8434 | fragP = fragP->fr_next) | |
8435 | { | |
8436 | if (unrelaxed_frag_has_b_j (fragP)) | |
8437 | return TRUE; | |
8438 | } | |
8439 | return FALSE; | |
8440 | } | |
8441 | ||
8442 | ||
43cd72b9 | 8443 | static bfd_boolean |
7fa3d080 | 8444 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 8445 | { |
43cd72b9 BW |
8446 | static xtensa_insnbuf insnbuf = NULL; |
8447 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8448 | int offset = 0; |
8449 | ||
8450 | if (!fragP->tc_frag_data.is_insn) | |
8451 | return FALSE; | |
8452 | ||
43cd72b9 BW |
8453 | if (!insnbuf) |
8454 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8455 | ||
e0001a05 NC |
8456 | /* Decode the fixed instructions. */ |
8457 | while (offset < fragP->fr_fix) | |
8458 | { | |
43cd72b9 BW |
8459 | xtensa_format fmt; |
8460 | int slot; | |
8461 | ||
d77b99c9 BW |
8462 | xtensa_insnbuf_from_chars |
8463 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8464 | fmt = xtensa_format_decode (isa, insnbuf); |
8465 | if (fmt == XTENSA_UNDEFINED) | |
8466 | return FALSE; | |
8467 | ||
8468 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8469 | { |
43cd72b9 BW |
8470 | xtensa_opcode opcode = |
8471 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8472 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8473 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8474 | return TRUE; | |
e0001a05 | 8475 | } |
43cd72b9 | 8476 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8477 | } |
8478 | return FALSE; | |
8479 | } | |
8480 | ||
8481 | ||
8482 | /* Checks to be made after initial assembly but before relaxation. */ | |
8483 | ||
7fa3d080 BW |
8484 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8485 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8486 | ||
e0001a05 | 8487 | static void |
7fa3d080 | 8488 | xtensa_sanity_check (void) |
e0001a05 | 8489 | { |
3b4dbbbf | 8490 | const char *file_name; |
d77b99c9 | 8491 | unsigned line; |
e0001a05 | 8492 | frchainS *frchP; |
c9049d30 | 8493 | asection *s; |
e0001a05 | 8494 | |
3b4dbbbf | 8495 | file_name = as_where (&line); |
c9049d30 AM |
8496 | for (s = stdoutput->sections; s; s = s->next) |
8497 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8498 | { | |
8499 | fragS *fragP; | |
e0001a05 | 8500 | |
c9049d30 AM |
8501 | /* Walk over all of the fragments in a subsection. */ |
8502 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8503 | { | |
c9049d30 | 8504 | if (fragP->fr_type == rs_machine_dependent |
3739860c | 8505 | && fragP->fr_subtype == RELAX_SLOTS |
a7284bf1 | 8506 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) |
c9049d30 AM |
8507 | { |
8508 | static xtensa_insnbuf insnbuf = NULL; | |
8509 | TInsn t_insn; | |
8510 | ||
8511 | if (fragP->fr_opcode != NULL) | |
8512 | { | |
8513 | if (!insnbuf) | |
8514 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8515 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8516 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8517 | ||
8518 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8519 | t_insn.opcode) == 1) | |
8520 | { | |
8521 | if (is_empty_loop (&t_insn, fragP)) | |
8522 | { | |
8523 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8524 | as_bad (_("invalid empty loop")); | |
8525 | } | |
8526 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8527 | { | |
8528 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8529 | as_bad (_("loop target does not follow " | |
8530 | "loop instruction in section")); | |
8531 | } | |
8532 | } | |
8533 | } | |
8534 | } | |
8535 | } | |
8536 | } | |
e0001a05 NC |
8537 | new_logical_line (file_name, line); |
8538 | } | |
8539 | ||
8540 | ||
8541 | #define LOOP_IMMED_OPN 1 | |
8542 | ||
43cd72b9 | 8543 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8544 | |
7fa3d080 BW |
8545 | static bfd_boolean |
8546 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8547 | { |
91d6fa6a | 8548 | const expressionS *exp; |
e0001a05 NC |
8549 | symbolS *symbolP; |
8550 | fragS *next_fragP; | |
8551 | ||
8552 | if (insn->insn_type != ITYPE_INSN) | |
8553 | return FALSE; | |
8554 | ||
43cd72b9 | 8555 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8556 | return FALSE; |
8557 | ||
8558 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8559 | return FALSE; | |
8560 | ||
91d6fa6a | 8561 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8562 | |
91d6fa6a | 8563 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8564 | return FALSE; |
8565 | ||
91d6fa6a | 8566 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8567 | if (!symbolP) |
8568 | return FALSE; | |
8569 | ||
8570 | if (symbol_get_frag (symbolP) == NULL) | |
8571 | return FALSE; | |
8572 | ||
8573 | if (S_GET_VALUE (symbolP) != 0) | |
8574 | return FALSE; | |
8575 | ||
8576 | /* Walk through the zero-size fragments from this one. If we find | |
8577 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8578 | |
e0001a05 NC |
8579 | for (next_fragP = fragP->fr_next; |
8580 | next_fragP != NULL; | |
8581 | next_fragP = next_fragP->fr_next) | |
8582 | { | |
8583 | if (next_fragP == symbol_get_frag (symbolP)) | |
8584 | return TRUE; | |
8585 | if (next_fragP->fr_fix != 0) | |
8586 | return FALSE; | |
8587 | } | |
8588 | return FALSE; | |
8589 | } | |
8590 | ||
8591 | ||
7fa3d080 BW |
8592 | static bfd_boolean |
8593 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8594 | { |
91d6fa6a | 8595 | const expressionS *exp; |
e0001a05 NC |
8596 | symbolS *symbolP; |
8597 | fragS *next_fragP; | |
8598 | ||
8599 | if (insn->insn_type != ITYPE_INSN) | |
8600 | return FALSE; | |
8601 | ||
64b607e6 | 8602 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8603 | return FALSE; |
8604 | ||
8605 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8606 | return FALSE; | |
8607 | ||
91d6fa6a | 8608 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8609 | |
91d6fa6a | 8610 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8611 | return FALSE; |
8612 | ||
91d6fa6a | 8613 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8614 | if (!symbolP) |
8615 | return FALSE; | |
8616 | ||
8617 | if (symbol_get_frag (symbolP) == NULL) | |
8618 | return FALSE; | |
8619 | ||
8620 | /* Walk through fragments until we find the target. | |
8621 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8622 | |
e0001a05 NC |
8623 | for (next_fragP = fragP->fr_next; |
8624 | next_fragP != NULL; | |
8625 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8626 | { |
8627 | if (next_fragP == symbol_get_frag (symbolP)) | |
8628 | return TRUE; | |
8629 | } | |
e0001a05 NC |
8630 | |
8631 | return FALSE; | |
8632 | } | |
8633 | ||
2caa7ca0 BW |
8634 | |
8635 | #define XTINFO_NAME "Xtensa_Info" | |
8636 | #define XTINFO_NAMESZ 12 | |
8637 | #define XTINFO_TYPE 1 | |
8638 | ||
8639 | static void | |
8640 | xtensa_add_config_info (void) | |
8641 | { | |
8642 | asection *info_sec; | |
8643 | char *data, *p; | |
8644 | int sz; | |
8645 | ||
8646 | info_sec = subseg_new (".xtensa.info", 0); | |
8647 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8648 | ||
325801bd | 8649 | data = XNEWVEC (char, 100); |
2caa7ca0 BW |
8650 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", |
8651 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8652 | sz = strlen (data) + 1; | |
8653 | ||
8654 | /* Add enough null terminators to pad to a word boundary. */ | |
8655 | do | |
8656 | data[sz++] = 0; | |
8657 | while ((sz & 3) != 0); | |
8658 | ||
8659 | /* Follow the standard note section layout: | |
8660 | First write the length of the name string. */ | |
8661 | p = frag_more (4); | |
8662 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8663 | ||
8664 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8665 | p = frag_more (4); | |
8666 | md_number_to_chars (p, (valueT) sz, 4); | |
8667 | ||
8668 | /* Write the note type. */ | |
8669 | p = frag_more (4); | |
8670 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8671 | ||
8672 | /* Write the name field. */ | |
8673 | p = frag_more (XTINFO_NAMESZ); | |
8674 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8675 | ||
8676 | /* Finally, write the descriptor. */ | |
8677 | p = frag_more (sz); | |
8678 | memcpy (p, data, sz); | |
8679 | ||
8680 | free (data); | |
8681 | } | |
8682 | ||
e0001a05 NC |
8683 | \f |
8684 | /* Alignment Functions. */ | |
8685 | ||
d77b99c9 BW |
8686 | static int |
8687 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8688 | { |
03aaa593 BW |
8689 | if (target_size <= 4) |
8690 | return 2; | |
19ef5f3d SA |
8691 | |
8692 | if (target_size <= 8) | |
8693 | return 3; | |
8694 | ||
8695 | if (target_size <= 16) | |
8696 | return 4; | |
8697 | ||
8698 | if (target_size <= 32) | |
8699 | return 5; | |
8700 | ||
8701 | if (target_size <= 64) | |
8702 | return 6; | |
8703 | ||
8704 | if (target_size <= 128) | |
8705 | return 7; | |
8706 | ||
8707 | if (target_size <= 256) | |
8708 | return 8; | |
8709 | ||
8710 | if (target_size <= 512) | |
8711 | return 9; | |
8712 | ||
8713 | if (target_size <= 1024) | |
8714 | return 10; | |
8715 | ||
8716 | gas_assert (0); | |
8717 | return 0; | |
e0001a05 NC |
8718 | } |
8719 | ||
8720 | ||
d77b99c9 | 8721 | static int |
7fa3d080 BW |
8722 | get_text_align_max_fill_size (int align_pow, |
8723 | bfd_boolean use_nops, | |
8724 | bfd_boolean use_no_density) | |
e0001a05 NC |
8725 | { |
8726 | if (!use_nops) | |
8727 | return (1 << align_pow); | |
8728 | if (use_no_density) | |
8729 | return 3 * (1 << align_pow); | |
8730 | ||
8731 | return 1 + (1 << align_pow); | |
8732 | } | |
8733 | ||
8734 | ||
d77b99c9 BW |
8735 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8736 | target instruction of size "target_size" so that it does not cross a | |
8737 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8738 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8739 | be filled by NOP instructions. */ | |
e0001a05 | 8740 | |
d77b99c9 | 8741 | static int |
7fa3d080 BW |
8742 | get_text_align_fill_size (addressT address, |
8743 | int align_pow, | |
8744 | int target_size, | |
8745 | bfd_boolean use_nops, | |
8746 | bfd_boolean use_no_density) | |
e0001a05 | 8747 | { |
d77b99c9 BW |
8748 | addressT alignment, fill, fill_limit, fill_step; |
8749 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8750 | |
d77b99c9 | 8751 | alignment = (1 << align_pow); |
9c2799c2 | 8752 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 8753 | |
e0001a05 NC |
8754 | if (!use_nops) |
8755 | { | |
d77b99c9 BW |
8756 | fill_limit = alignment; |
8757 | fill_step = 1; | |
e0001a05 | 8758 | } |
d77b99c9 | 8759 | else if (!use_no_density) |
e0001a05 | 8760 | { |
d77b99c9 BW |
8761 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8762 | fill_limit = alignment * 2; | |
8763 | fill_step = 1; | |
8764 | skip_one = TRUE; | |
e0001a05 NC |
8765 | } |
8766 | else | |
8767 | { | |
d77b99c9 BW |
8768 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8769 | fill_limit = alignment * 3; | |
8770 | fill_step = 3; | |
8771 | } | |
e0001a05 | 8772 | |
d77b99c9 BW |
8773 | /* Try all fill sizes until finding one that works. */ |
8774 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8775 | { | |
8776 | if (skip_one && fill == 1) | |
8777 | continue; | |
8778 | if ((address + fill) >> align_pow | |
8779 | == (address + fill + target_size - 1) >> align_pow) | |
8780 | return fill; | |
e0001a05 | 8781 | } |
9c2799c2 | 8782 | gas_assert (0); |
e0001a05 NC |
8783 | return 0; |
8784 | } | |
8785 | ||
8786 | ||
664df4e4 BW |
8787 | static int |
8788 | branch_align_power (segT sec) | |
8789 | { | |
19ef5f3d SA |
8790 | /* If the Xtensa processor has a fetch width of X, and |
8791 | the section is aligned to at least that boundary, then a branch | |
8792 | target need only fit within that aligned block of memory to avoid | |
8793 | a stall. Otherwise, try to fit branch targets within 4-byte | |
8794 | aligned blocks (which may be insufficient, e.g., if the section | |
8795 | has no alignment, but it's good enough). */ | |
8796 | int fetch_align = get_text_align_power(xtensa_fetch_width); | |
8797 | int sec_align = get_recorded_alignment (sec); | |
8798 | ||
8799 | if (sec_align >= fetch_align) | |
8800 | return fetch_align; | |
664df4e4 BW |
8801 | |
8802 | return 2; | |
8803 | } | |
8804 | ||
8805 | ||
e0001a05 NC |
8806 | /* This will assert if it is not possible. */ |
8807 | ||
d77b99c9 BW |
8808 | static int |
8809 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8810 | { |
d77b99c9 BW |
8811 | int count = 0; |
8812 | ||
e0001a05 NC |
8813 | if (use_no_density) |
8814 | { | |
9c2799c2 | 8815 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
8816 | return (fill_size / 3); |
8817 | } | |
8818 | ||
9c2799c2 | 8819 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
8820 | |
8821 | while (fill_size > 1) | |
8822 | { | |
d77b99c9 | 8823 | int insn_size = 3; |
e0001a05 NC |
8824 | if (fill_size == 2 || fill_size == 4) |
8825 | insn_size = 2; | |
8826 | fill_size -= insn_size; | |
8827 | count++; | |
8828 | } | |
9c2799c2 | 8829 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
8830 | return count; |
8831 | } | |
8832 | ||
8833 | ||
d77b99c9 BW |
8834 | static int |
8835 | get_text_align_nth_nop_size (offsetT fill_size, | |
8836 | int n, | |
7fa3d080 | 8837 | bfd_boolean use_no_density) |
e0001a05 | 8838 | { |
d77b99c9 | 8839 | int count = 0; |
e0001a05 NC |
8840 | |
8841 | if (use_no_density) | |
8842 | return 3; | |
8843 | ||
9c2799c2 | 8844 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 8845 | |
e0001a05 NC |
8846 | while (fill_size > 1) |
8847 | { | |
d77b99c9 | 8848 | int insn_size = 3; |
e0001a05 NC |
8849 | if (fill_size == 2 || fill_size == 4) |
8850 | insn_size = 2; | |
8851 | fill_size -= insn_size; | |
8852 | count++; | |
8853 | if (n + 1 == count) | |
8854 | return insn_size; | |
8855 | } | |
9c2799c2 | 8856 | gas_assert (0); |
e0001a05 NC |
8857 | return 0; |
8858 | } | |
8859 | ||
8860 | ||
8861 | /* For the given fragment, find the appropriate address | |
8862 | for it to begin at if we are using NOPs to align it. */ | |
8863 | ||
8864 | static addressT | |
7fa3d080 | 8865 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8866 | { |
43cd72b9 BW |
8867 | /* The rule is: get next fragment's FIRST instruction. Find |
8868 | the smallest number of bytes that need to be added to | |
8869 | ensure that the next fragment's FIRST instruction will fit | |
8870 | in a single word. | |
c138bc38 | 8871 | |
43cd72b9 BW |
8872 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8873 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8874 | |
43cd72b9 BW |
8875 | If the FIRST instruction MIGHT be relaxed, |
8876 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8877 | |
43cd72b9 BW |
8878 | Note again here that LOOP instructions are not bundleable, |
8879 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8880 | |
d77b99c9 | 8881 | int fill_size = 0; |
43cd72b9 BW |
8882 | int first_insn_size; |
8883 | int loop_insn_size; | |
8884 | addressT pre_opcode_bytes; | |
d77b99c9 | 8885 | int align_power; |
43cd72b9 BW |
8886 | fragS *first_insn; |
8887 | xtensa_opcode opcode; | |
8888 | bfd_boolean is_loop; | |
e0001a05 | 8889 | |
9c2799c2 NC |
8890 | gas_assert (fragP->fr_type == rs_machine_dependent); |
8891 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8892 | |
43cd72b9 BW |
8893 | /* Find the loop frag. */ |
8894 | first_insn = next_non_empty_frag (fragP); | |
8895 | /* Now find the first insn frag. */ | |
8896 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8897 | |
43cd72b9 | 8898 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 8899 | gas_assert (is_loop); |
43cd72b9 | 8900 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 8901 | |
43cd72b9 BW |
8902 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8903 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8904 | |
43cd72b9 BW |
8905 | /* For loops, the alignment depends on the size of the |
8906 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8907 | |
43cd72b9 | 8908 | if (first_insn == NULL) |
03aaa593 BW |
8909 | first_insn_size = xtensa_fetch_width; |
8910 | else | |
8911 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8912 | |
43cd72b9 | 8913 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8914 | align_power = get_text_align_power (first_insn_size); |
8915 | record_alignment (now_seg, align_power); | |
c138bc38 | 8916 | |
43cd72b9 | 8917 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8918 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8919 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8920 | |
8921 | return address + fill_size; | |
8922 | } | |
8923 | ||
8924 | ||
43cd72b9 BW |
8925 | /* 3 mechanisms for relaxing an alignment: |
8926 | ||
8927 | Align to a power of 2. | |
8928 | Align so the next fragment's instruction does not cross a word boundary. | |
8929 | Align the current instruction so that if the next instruction | |
8930 | were 3 bytes, it would not cross a word boundary. | |
8931 | ||
e0001a05 NC |
8932 | We can align with: |
8933 | ||
43cd72b9 BW |
8934 | zeros - This is easy; always insert zeros. |
8935 | nops - 3-byte and 2-byte instructions | |
8936 | 2 - 2-byte nop | |
8937 | 3 - 3-byte nop | |
8938 | 4 - 2 2-byte nops | |
8939 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8940 | widening - widen previous instructions. */ |
8941 | ||
d77b99c9 BW |
8942 | static offsetT |
8943 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8944 | { |
43cd72b9 BW |
8945 | addressT target_address, loop_insn_offset; |
8946 | int target_size; | |
8947 | xtensa_opcode loop_opcode; | |
8948 | bfd_boolean is_loop; | |
d77b99c9 BW |
8949 | int align_power; |
8950 | offsetT opt_diff; | |
5f9084e9 | 8951 | offsetT branch_align; |
def13efb | 8952 | fragS *loop_frag; |
e0001a05 | 8953 | |
9c2799c2 | 8954 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 8955 | switch (fragP->fr_subtype) |
e0001a05 | 8956 | { |
43cd72b9 BW |
8957 | case RELAX_DESIRE_ALIGN: |
8958 | target_size = next_frag_format_size (fragP); | |
8959 | if (target_size == XTENSA_UNDEFINED) | |
8960 | target_size = 3; | |
664df4e4 BW |
8961 | align_power = branch_align_power (now_seg); |
8962 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8963 | /* Don't count on the section alignment being as large as the target. */ |
8964 | if (target_size > branch_align) | |
8965 | target_size = branch_align; | |
d77b99c9 | 8966 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8967 | target_size, FALSE, FALSE); |
8968 | ||
664df4e4 BW |
8969 | *max_diff = (opt_diff + branch_align |
8970 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 8971 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8972 | return opt_diff; |
e0001a05 | 8973 | |
43cd72b9 | 8974 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8975 | /* The next non-empty frag after this one holds the LOOP instruction |
8976 | that needs to be aligned. The required alignment depends on the | |
8977 | size of the next non-empty frag after the loop frag, i.e., the | |
8978 | first instruction in the loop. */ | |
8979 | loop_frag = next_non_empty_frag (fragP); | |
8980 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8981 | loop_insn_offset = 0; |
8982 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 8983 | gas_assert (is_loop); |
43cd72b9 BW |
8984 | |
8985 | /* If the loop has been expanded then the LOOP instruction | |
8986 | could be at an offset from this fragment. */ | |
def13efb | 8987 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8988 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8989 | ||
43cd72b9 BW |
8990 | /* In an ideal world, which is what we are shooting for here, |
8991 | we wouldn't need to use any NOPs immediately prior to the | |
8992 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8993 | will call get_noop_aligned_address. */ | |
8994 | target_address = | |
8995 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8996 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8997 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8998 | target_size, FALSE, FALSE); |
8999 | ||
9000 | *max_diff = xtensa_fetch_width | |
9001 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
9002 | - target_size + opt_diff; | |
9c2799c2 | 9003 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9004 | return opt_diff; |
e0001a05 | 9005 | |
43cd72b9 BW |
9006 | default: |
9007 | break; | |
e0001a05 | 9008 | } |
9c2799c2 | 9009 | gas_assert (0); |
43cd72b9 | 9010 | return 0; |
e0001a05 NC |
9011 | } |
9012 | ||
9013 | \f | |
9014 | /* md_relax_frag Hook and Helper Functions. */ | |
9015 | ||
7fa3d080 BW |
9016 | static long relax_frag_loop_align (fragS *, long); |
9017 | static long relax_frag_for_align (fragS *, long); | |
9018 | static long relax_frag_immed | |
9019 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
9020 | ||
b76f99d7 MF |
9021 | typedef struct cached_fixup cached_fixupS; |
9022 | struct cached_fixup | |
9023 | { | |
9024 | int addr; | |
9025 | int target; | |
9026 | int delta; | |
9027 | fixS *fixP; | |
9028 | }; | |
9029 | ||
9030 | typedef struct fixup_cache fixup_cacheS; | |
9031 | struct fixup_cache | |
9032 | { | |
9033 | cached_fixupS *fixups; | |
9034 | unsigned n_fixups; | |
9035 | unsigned n_max; | |
9036 | ||
9037 | segT seg; | |
9038 | fragS *first_frag; | |
9039 | }; | |
9040 | ||
9041 | static int fixup_order (const void *a, const void *b) | |
9042 | { | |
9043 | const cached_fixupS *pa = a; | |
9044 | const cached_fixupS *pb = b; | |
9045 | ||
9046 | if (pa->addr == pb->addr) | |
9047 | { | |
9048 | if (pa->target == pb->target) | |
9049 | { | |
9050 | if (pa->fixP->fx_r_type == pb->fixP->fx_r_type) | |
9051 | return 0; | |
9052 | return pa->fixP->fx_r_type < pb->fixP->fx_r_type ? -1 : 1; | |
9053 | } | |
9054 | return pa->target - pb->target; | |
9055 | } | |
9056 | return pa->addr - pb->addr; | |
9057 | } | |
9058 | ||
9059 | static bfd_boolean xtensa_make_cached_fixup (cached_fixupS *o, fixS *fixP) | |
9060 | { | |
9061 | xtensa_isa isa = xtensa_default_isa; | |
9062 | int addr = fixP->fx_frag->fr_address; | |
9063 | int target; | |
9064 | int delta; | |
9065 | symbolS *s = fixP->fx_addsy; | |
9066 | int slot; | |
9067 | xtensa_format fmt; | |
9068 | xtensa_opcode opcode; | |
9069 | ||
9070 | if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || | |
9071 | fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) | |
9072 | return FALSE; | |
9073 | target = S_GET_VALUE (s); | |
9074 | delta = target - addr; | |
9075 | ||
9076 | if (abs(delta) < J_RANGE / 2) | |
9077 | return FALSE; | |
9078 | ||
9079 | xtensa_insnbuf_from_chars (isa, trampoline_buf, | |
9080 | (unsigned char *) fixP->fx_frag->fr_literal + | |
9081 | fixP->fx_where, 0); | |
9082 | fmt = xtensa_format_decode (isa, trampoline_buf); | |
9083 | gas_assert (fmt != XTENSA_UNDEFINED); | |
9084 | slot = fixP->tc_fix_data.slot; | |
9085 | xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); | |
9086 | opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); | |
9087 | if (opcode != xtensa_j_opcode) | |
9088 | return FALSE; | |
9089 | ||
9090 | o->addr = addr; | |
9091 | o->target = target; | |
9092 | o->delta = delta; | |
9093 | o->fixP = fixP; | |
9094 | ||
9095 | return TRUE; | |
9096 | } | |
9097 | ||
9098 | static void xtensa_realloc_fixup_cache (fixup_cacheS *cache, unsigned add) | |
9099 | { | |
9100 | if (cache->n_fixups + add > cache->n_max) | |
9101 | { | |
9102 | cache->n_max = (cache->n_fixups + add) * 2; | |
325801bd | 9103 | cache->fixups = XRESIZEVEC (cached_fixupS, cache->fixups, cache->n_max); |
b76f99d7 MF |
9104 | } |
9105 | } | |
9106 | ||
9107 | static void xtensa_cache_relaxable_fixups (fixup_cacheS *cache, | |
9108 | segment_info_type *seginfo) | |
9109 | { | |
9110 | fixS *fixP; | |
9111 | ||
9112 | cache->n_fixups = 0; | |
9113 | ||
9114 | for (fixP = seginfo->fix_root; fixP ; fixP = fixP->fx_next) | |
9115 | { | |
9116 | xtensa_realloc_fixup_cache (cache, 1); | |
9117 | ||
9118 | if (xtensa_make_cached_fixup (cache->fixups + cache->n_fixups, fixP)) | |
9119 | ++cache->n_fixups; | |
9120 | } | |
9121 | qsort (cache->fixups, cache->n_fixups, sizeof (*cache->fixups), fixup_order); | |
9122 | } | |
9123 | ||
9124 | static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS *cache, | |
9125 | int addr) | |
9126 | { | |
9127 | unsigned a = 0; | |
9128 | unsigned b = cache->n_fixups; | |
9129 | ||
9130 | while (b - a > 1) | |
9131 | { | |
9132 | unsigned c = (a + b) / 2; | |
9133 | ||
9134 | if (cache->fixups[c].addr < addr) | |
9135 | a = c; | |
9136 | else | |
9137 | b = c; | |
9138 | } | |
9139 | return a; | |
9140 | } | |
9141 | ||
9142 | static void xtensa_delete_cached_fixup (fixup_cacheS *cache, unsigned i) | |
9143 | { | |
9144 | memmove (cache->fixups + i, cache->fixups + i + 1, | |
9145 | (cache->n_fixups - i - 1) * sizeof (*cache->fixups)); | |
9146 | --cache->n_fixups; | |
9147 | } | |
9148 | ||
9149 | static bfd_boolean xtensa_add_cached_fixup (fixup_cacheS *cache, fixS *fixP) | |
9150 | { | |
9151 | cached_fixupS o; | |
9152 | unsigned i; | |
9153 | ||
9154 | if (!xtensa_make_cached_fixup (&o, fixP)) | |
9155 | return FALSE; | |
9156 | xtensa_realloc_fixup_cache (cache, 1); | |
9157 | i = xtensa_find_first_cached_fixup (cache, o.addr); | |
9158 | if (i < cache->n_fixups) | |
9159 | { | |
9160 | ++i; | |
9161 | memmove (cache->fixups + i + 1, cache->fixups + i, | |
9162 | (cache->n_fixups - i) * sizeof (*cache->fixups)); | |
9163 | } | |
9164 | cache->fixups[i] = o; | |
9165 | ++cache->n_fixups; | |
9166 | return TRUE; | |
9167 | } | |
7fa3d080 | 9168 | |
120bc8b8 MF |
9169 | static void xg_relax_trampoline (fragS *fragP, long stretch, long *new_stretch) |
9170 | { | |
120bc8b8 MF |
9171 | static fixup_cacheS fixup_cache; |
9172 | segment_info_type *seginfo = seg_info (now_seg); | |
9173 | int trampaddr = fragP->fr_address + fragP->fr_fix; | |
9174 | int searchaddr = trampaddr < J_RANGE ? 0 : trampaddr - J_RANGE; | |
120bc8b8 MF |
9175 | unsigned i; |
9176 | ||
9177 | if (now_seg != fixup_cache.seg || | |
9178 | fragP == fixup_cache.first_frag || | |
9179 | fixup_cache.first_frag == NULL) | |
9180 | { | |
9181 | xtensa_cache_relaxable_fixups (&fixup_cache, seginfo); | |
9182 | fixup_cache.seg = now_seg; | |
9183 | fixup_cache.first_frag = fragP; | |
9184 | } | |
9185 | ||
9186 | /* Scan for jumps that will not reach. */ | |
9187 | for (i = xtensa_find_first_cached_fixup (&fixup_cache, searchaddr); | |
9188 | i < fixup_cache.n_fixups; ++i) | |
9189 | ||
9190 | { | |
9191 | fixS *fixP = fixup_cache.fixups[i].fixP; | |
9192 | int target = fixup_cache.fixups[i].target; | |
9193 | int addr = fixup_cache.fixups[i].addr; | |
9194 | int delta = fixup_cache.fixups[i].delta + stretch; | |
9195 | ||
9196 | trampaddr = fragP->fr_address + fragP->fr_fix; | |
9197 | ||
9198 | if (addr + J_RANGE < trampaddr) | |
9199 | continue; | |
9200 | if (addr > trampaddr + J_RANGE) | |
9201 | break; | |
9202 | if (abs (delta) < J_RANGE) | |
9203 | continue; | |
9204 | ||
120bc8b8 MF |
9205 | if (delta > J_RANGE || delta < -1 * J_RANGE) |
9206 | { /* Found an out-of-range jump; scan the list of trampolines for the best match. */ | |
9207 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
9208 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
9209 | struct trampoline_frag *prev = &ts->trampoline_list; | |
9210 | int lower = (target < addr) ? target : addr; | |
9211 | int upper = (target > addr) ? target : addr; | |
9212 | int midpoint = lower + (upper - lower) / 2; | |
9213 | ||
9214 | if ((upper - lower) > 2 * J_RANGE) | |
9215 | { | |
9216 | /* One trampoline won't suffice; we need multiple jumps. | |
9217 | Jump to the trampoline that's farthest, but still in | |
9218 | range relative to the original "j" instruction. */ | |
9219 | for ( ; tf; prev = tf, tf = tf->next ) | |
9220 | { | |
9221 | int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9222 | int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0 ; | |
9223 | ||
9224 | if (addr == lower) | |
9225 | { | |
9226 | /* Forward jump. */ | |
9227 | if (this_addr - addr < J_RANGE) | |
9228 | break; | |
9229 | } | |
9230 | else | |
9231 | { | |
9232 | /* Backward jump. */ | |
9233 | if (next_addr == 0 || addr - next_addr > J_RANGE) | |
9234 | break; | |
9235 | } | |
9236 | } | |
9237 | } | |
9238 | else | |
9239 | { | |
9240 | struct trampoline_frag *best_tf = NULL; | |
9241 | struct trampoline_frag *best_tf_prev = NULL; | |
9242 | int best_delta = 0; | |
9243 | ||
9244 | for ( ; tf; prev = tf, tf = tf->next ) | |
9245 | { | |
9246 | int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9247 | int this_delta = abs (this_addr - midpoint); | |
9248 | ||
9249 | if (!best_tf || this_delta < best_delta) | |
9250 | { | |
9251 | best_tf = tf; | |
9252 | best_delta = this_delta; | |
9253 | best_tf_prev = prev; | |
9254 | } | |
9255 | } | |
9256 | tf = best_tf; | |
9257 | prev = best_tf_prev; | |
9258 | } | |
9259 | if (tf->fragP == fragP) | |
9260 | { | |
9261 | if (abs (addr - trampaddr) < J_RANGE) | |
9262 | { /* The trampoline is in range of original; fix it! */ | |
9263 | fixS *newfixP; | |
120bc8b8 | 9264 | |
fec68fb1 MF |
9265 | new_stretch += init_trampoline_frag (tf) + 3; |
9266 | /* Assemble a jump to the target label in the trampoline frag. */ | |
9267 | newfixP = xg_append_jump (fragP, tf->fixP, | |
9268 | fixP->fx_addsy, fixP->fx_offset); | |
120bc8b8 | 9269 | |
fec68fb1 MF |
9270 | /* Adjust the fixup for the original "j" instruction to |
9271 | point to the newly added jump. */ | |
9272 | fixP->fx_addsy = fragP->fr_symbol; | |
9273 | fixP->fx_offset = fragP->fr_fix - 3; | |
9274 | fixP->tc_fix_data.X_add_symbol = fragP->fr_symbol; | |
9275 | fixP->tc_fix_data.X_add_number = fragP->fr_fix - 3; | |
120bc8b8 | 9276 | |
fec68fb1 MF |
9277 | fixP = newfixP; |
9278 | xtensa_delete_cached_fixup (&fixup_cache, i); | |
9279 | xtensa_add_cached_fixup (&fixup_cache, newfixP); | |
120bc8b8 MF |
9280 | |
9281 | /* re-do current fixup */ | |
9282 | --i; | |
9283 | ||
120bc8b8 MF |
9284 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ |
9285 | /* Do we have room for more? */ | |
9286 | if (fragP->fr_var < 3) | |
9287 | { /* No, convert to fill. */ | |
9288 | frag_wane (fragP); | |
9289 | fragP->fr_subtype = 0; | |
9290 | /* Remove from the trampoline_list. */ | |
9291 | prev->next = tf->next; | |
9292 | if (fragP == fixup_cache.first_frag) | |
9293 | fixup_cache.first_frag = NULL; | |
9294 | break; | |
9295 | } | |
9296 | } | |
9297 | } | |
9298 | } | |
9299 | } | |
9300 | } | |
9301 | ||
e0001a05 NC |
9302 | /* Return the number of bytes added to this fragment, given that the |
9303 | input has been stretched already by "stretch". */ | |
9304 | ||
9305 | long | |
7fa3d080 | 9306 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 9307 | { |
43cd72b9 | 9308 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9309 | int unreported = fragP->tc_frag_data.unreported_expansion; |
9310 | long new_stretch = 0; | |
3b4dbbbf | 9311 | const char *file_name; |
d77b99c9 BW |
9312 | unsigned line; |
9313 | int lit_size; | |
43cd72b9 BW |
9314 | static xtensa_insnbuf vbuf = NULL; |
9315 | int slot, num_slots; | |
9316 | xtensa_format fmt; | |
e0001a05 | 9317 | |
3b4dbbbf | 9318 | file_name = as_where (&line); |
e0001a05 NC |
9319 | new_logical_line (fragP->fr_file, fragP->fr_line); |
9320 | ||
9321 | fragP->tc_frag_data.unreported_expansion = 0; | |
9322 | ||
9323 | switch (fragP->fr_subtype) | |
9324 | { | |
9325 | case RELAX_ALIGN_NEXT_OPCODE: | |
9326 | /* Always convert. */ | |
43cd72b9 BW |
9327 | if (fragP->tc_frag_data.relax_seen) |
9328 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
9329 | break; |
9330 | ||
9331 | case RELAX_LOOP_END: | |
9332 | /* Do nothing. */ | |
9333 | break; | |
9334 | ||
9335 | case RELAX_LOOP_END_ADD_NOP: | |
9336 | /* Add a NOP and switch to .fill 0. */ | |
9337 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 9338 | frag_wane (fragP); |
e0001a05 NC |
9339 | break; |
9340 | ||
9341 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 9342 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
9343 | it or not. */ |
9344 | break; | |
9345 | ||
9346 | case RELAX_LITERAL: | |
9347 | case RELAX_LITERAL_FINAL: | |
9348 | return 0; | |
9349 | ||
9350 | case RELAX_LITERAL_NR: | |
9351 | lit_size = 4; | |
9352 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9353 | gas_assert (unreported == lit_size); |
e0001a05 NC |
9354 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
9355 | fragP->fr_var -= lit_size; | |
9356 | fragP->fr_fix += lit_size; | |
9357 | new_stretch = 4; | |
9358 | break; | |
9359 | ||
43cd72b9 BW |
9360 | case RELAX_SLOTS: |
9361 | if (vbuf == NULL) | |
9362 | vbuf = xtensa_insnbuf_alloc (isa); | |
9363 | ||
d77b99c9 BW |
9364 | xtensa_insnbuf_from_chars |
9365 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
9366 | fmt = xtensa_format_decode (isa, vbuf); |
9367 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 9368 | |
43cd72b9 BW |
9369 | for (slot = 0; slot < num_slots; slot++) |
9370 | { | |
9371 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
9372 | { | |
9373 | case RELAX_NARROW: | |
9374 | if (fragP->tc_frag_data.relax_seen) | |
9375 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9376 | break; | |
9377 | ||
9378 | case RELAX_IMMED: | |
9379 | case RELAX_IMMED_STEP1: | |
9380 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9381 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9382 | /* Place the immediate. */ |
9383 | new_stretch += relax_frag_immed | |
9384 | (now_seg, fragP, stretch, | |
9385 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9386 | fmt, slot, stretched_p, FALSE); | |
9387 | break; | |
9388 | ||
9389 | default: | |
9390 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
9391 | break; | |
9392 | } | |
9393 | } | |
e0001a05 NC |
9394 | break; |
9395 | ||
9396 | case RELAX_LITERAL_POOL_BEGIN: | |
b46824bd MF |
9397 | if (fragP->fr_var != 0) |
9398 | { | |
9399 | /* We have a converted "candidate" literal pool; | |
9400 | assemble a jump around it. */ | |
9401 | TInsn insn; | |
9402 | if (!litpool_slotbuf) | |
9403 | { | |
9404 | litpool_buf = xtensa_insnbuf_alloc (isa); | |
9405 | litpool_slotbuf = xtensa_insnbuf_alloc (isa); | |
9406 | } | |
9407 | new_stretch += 3; | |
9408 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ | |
9409 | fragP->tc_frag_data.is_insn = TRUE; | |
9410 | tinsn_init (&insn); | |
9411 | insn.insn_type = ITYPE_INSN; | |
9412 | insn.opcode = xtensa_j_opcode; | |
9413 | insn.ntok = 1; | |
9414 | set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, | |
9415 | fragP->fr_fix); | |
9416 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9417 | tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); | |
9418 | xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); | |
9419 | xtensa_insnbuf_to_chars (isa, litpool_buf, | |
9420 | (unsigned char *)fragP->fr_literal + | |
9421 | fragP->fr_fix, 3); | |
9422 | fragP->fr_fix += 3; | |
9423 | fragP->fr_var -= 3; | |
9424 | /* Add a fix-up. */ | |
9425 | fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE, | |
9426 | BFD_RELOC_XTENSA_SLOT0_OP); | |
9427 | } | |
9428 | break; | |
9429 | ||
e0001a05 | 9430 | case RELAX_LITERAL_POOL_END: |
b46824bd | 9431 | case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: |
43cd72b9 BW |
9432 | case RELAX_MAYBE_UNREACHABLE: |
9433 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
9434 | /* No relaxation required. */ |
9435 | break; | |
9436 | ||
43cd72b9 BW |
9437 | case RELAX_FILL_NOP: |
9438 | case RELAX_UNREACHABLE: | |
9439 | if (fragP->tc_frag_data.relax_seen) | |
9440 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9441 | break; | |
9442 | ||
a82c7d90 DW |
9443 | case RELAX_TRAMPOLINE: |
9444 | if (fragP->tc_frag_data.relax_seen) | |
120bc8b8 | 9445 | xg_relax_trampoline (fragP, stretch, &new_stretch); |
a82c7d90 DW |
9446 | break; |
9447 | ||
e0001a05 NC |
9448 | default: |
9449 | as_bad (_("bad relaxation state")); | |
9450 | } | |
9451 | ||
43cd72b9 | 9452 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 9453 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
9454 | { |
9455 | fragP->tc_frag_data.relax_seen = TRUE; | |
9456 | *stretched_p = 1; | |
9457 | } | |
9458 | ||
e0001a05 NC |
9459 | new_logical_line (file_name, line); |
9460 | return new_stretch; | |
9461 | } | |
9462 | ||
9463 | ||
9464 | static long | |
7fa3d080 | 9465 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
9466 | { |
9467 | addressT old_address, old_next_address, old_size; | |
9468 | addressT new_address, new_next_address, new_size; | |
9469 | addressT growth; | |
9470 | ||
43cd72b9 BW |
9471 | /* All the frags with relax_frag_for_alignment prior to this one in the |
9472 | section have been done, hopefully eliminating the need for a NOP here. | |
9473 | But, this will put it in if necessary. */ | |
e0001a05 NC |
9474 | |
9475 | /* Calculate the old address of this fragment and the next fragment. */ | |
9476 | old_address = fragP->fr_address - stretch; | |
9477 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 9478 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
9479 | old_size = old_next_address - old_address; |
9480 | ||
9481 | /* Calculate the new address of this fragment and the next fragment. */ | |
9482 | new_address = fragP->fr_address; | |
9483 | new_next_address = | |
9484 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
9485 | new_size = new_next_address - new_address; | |
9486 | ||
9487 | growth = new_size - old_size; | |
9488 | ||
9489 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 9490 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
9491 | return growth; |
9492 | } | |
9493 | ||
9494 | ||
43cd72b9 | 9495 | /* Add a NOP instruction. */ |
e0001a05 NC |
9496 | |
9497 | static long | |
7fa3d080 | 9498 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 9499 | { |
e0001a05 | 9500 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
9501 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
9502 | assemble_nop (length, nop_buf); | |
e0001a05 | 9503 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 9504 | |
e0001a05 NC |
9505 | if (fragP->fr_var < length) |
9506 | { | |
dd49a749 | 9507 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
9508 | return 0; |
9509 | } | |
9510 | ||
9511 | fragP->fr_fix += length; | |
9512 | fragP->fr_var -= length; | |
e0001a05 NC |
9513 | return length; |
9514 | } | |
9515 | ||
9516 | ||
7fa3d080 BW |
9517 | static long future_alignment_required (fragS *, long); |
9518 | ||
e0001a05 | 9519 | static long |
7fa3d080 | 9520 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 9521 | { |
43cd72b9 BW |
9522 | /* Overview of the relaxation procedure for alignment: |
9523 | We can widen with NOPs or by widening instructions or by filling | |
9524 | bytes after jump instructions. Find the opportune places and widen | |
9525 | them if necessary. */ | |
9526 | ||
9527 | long stretch_me; | |
9528 | long diff; | |
e0001a05 | 9529 | |
9c2799c2 | 9530 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
9531 | || fragP->fr_subtype == RELAX_UNREACHABLE |
9532 | || (fragP->fr_subtype == RELAX_SLOTS | |
9533 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
9534 | ||
9535 | stretch_me = future_alignment_required (fragP, stretch); | |
9536 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
9537 | if (diff == 0) | |
9538 | return 0; | |
e0001a05 | 9539 | |
43cd72b9 | 9540 | if (diff < 0) |
e0001a05 | 9541 | { |
43cd72b9 BW |
9542 | /* We expanded on a previous pass. Can we shrink now? */ |
9543 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
9544 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 9545 | { |
43cd72b9 BW |
9546 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
9547 | return -shrink; | |
e0001a05 NC |
9548 | } |
9549 | return 0; | |
9550 | } | |
9551 | ||
43cd72b9 BW |
9552 | /* Below here, diff > 0. */ |
9553 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 9554 | |
43cd72b9 | 9555 | return diff; |
e0001a05 NC |
9556 | } |
9557 | ||
9558 | ||
43cd72b9 BW |
9559 | /* Return the address of the next frag that should be aligned. |
9560 | ||
9561 | By "address" we mean the address it _would_ be at if there | |
9562 | is no action taken to align it between here and the target frag. | |
9563 | In other words, if no narrows and no fill nops are used between | |
9564 | here and the frag to align, _even_if_ some of the frags we use | |
9565 | to align targets have already expanded on a previous relaxation | |
9566 | pass. | |
9567 | ||
9568 | Also, count each frag that may be used to help align the target. | |
9569 | ||
9570 | Return 0 if there are no frags left in the chain that need to be | |
9571 | aligned. */ | |
9572 | ||
9573 | static addressT | |
7fa3d080 BW |
9574 | find_address_of_next_align_frag (fragS **fragPP, |
9575 | int *wide_nops, | |
9576 | int *narrow_nops, | |
9577 | int *widens, | |
9578 | bfd_boolean *paddable) | |
e0001a05 | 9579 | { |
43cd72b9 BW |
9580 | fragS *fragP = *fragPP; |
9581 | addressT address = fragP->fr_address; | |
9582 | ||
9583 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
9584 | |
9585 | while (fragP) | |
9586 | { | |
9587 | /* Limit this to a small search. */ | |
b5e4a23d | 9588 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
9589 | { |
9590 | *fragPP = fragP; | |
9591 | return 0; | |
9592 | } | |
e0001a05 NC |
9593 | address += fragP->fr_fix; |
9594 | ||
43cd72b9 BW |
9595 | if (fragP->fr_type == rs_fill) |
9596 | address += fragP->fr_offset * fragP->fr_var; | |
9597 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 9598 | { |
e0001a05 NC |
9599 | switch (fragP->fr_subtype) |
9600 | { | |
43cd72b9 BW |
9601 | case RELAX_UNREACHABLE: |
9602 | *paddable = TRUE; | |
9603 | break; | |
9604 | ||
9605 | case RELAX_FILL_NOP: | |
9606 | (*wide_nops)++; | |
9607 | if (!fragP->tc_frag_data.is_no_density) | |
9608 | (*narrow_nops)++; | |
9609 | break; | |
9610 | ||
9611 | case RELAX_SLOTS: | |
9612 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9613 | { | |
9614 | (*widens)++; | |
9615 | break; | |
9616 | } | |
5bb3703f | 9617 | address += total_frag_text_expansion (fragP); |
e0001a05 NC |
9618 | break; |
9619 | ||
9620 | case RELAX_IMMED: | |
43cd72b9 | 9621 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
9622 | break; |
9623 | ||
9624 | case RELAX_ALIGN_NEXT_OPCODE: | |
9625 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
9626 | *fragPP = fragP; |
9627 | return address; | |
9628 | ||
9629 | case RELAX_MAYBE_UNREACHABLE: | |
9630 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9631 | /* Do nothing. */ | |
e0001a05 NC |
9632 | break; |
9633 | ||
9634 | default: | |
43cd72b9 BW |
9635 | /* Just punt if we don't know the type. */ |
9636 | *fragPP = fragP; | |
9637 | return 0; | |
e0001a05 | 9638 | } |
43cd72b9 | 9639 | } |
c138bc38 | 9640 | else |
43cd72b9 BW |
9641 | { |
9642 | /* Just punt if we don't know the type. */ | |
9643 | *fragPP = fragP; | |
9644 | return 0; | |
9645 | } | |
9646 | fragP = fragP->fr_next; | |
9647 | } | |
9648 | ||
9649 | *fragPP = fragP; | |
9650 | return 0; | |
9651 | } | |
9652 | ||
9653 | ||
7fa3d080 BW |
9654 | static long bytes_to_stretch (fragS *, int, int, int, int); |
9655 | ||
43cd72b9 | 9656 | static long |
7fa3d080 | 9657 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
9658 | { |
9659 | fragS *this_frag = fragP; | |
9660 | long address; | |
9661 | int num_widens = 0; | |
9662 | int wide_nops = 0; | |
9663 | int narrow_nops = 0; | |
9664 | bfd_boolean paddable = FALSE; | |
9665 | offsetT local_opt_diff; | |
9666 | offsetT opt_diff; | |
9667 | offsetT max_diff; | |
9668 | int stretch_amount = 0; | |
9669 | int local_stretch_amount; | |
9670 | int global_stretch_amount; | |
9671 | ||
7fa3d080 BW |
9672 | address = find_address_of_next_align_frag |
9673 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 9674 | |
b5e4a23d BW |
9675 | if (!address) |
9676 | { | |
9677 | if (this_frag->tc_frag_data.is_aligning_branch) | |
9678 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
9679 | else | |
9680 | frag_wane (this_frag); | |
9681 | } | |
9682 | else | |
43cd72b9 BW |
9683 | { |
9684 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
9685 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
9686 | gas_assert (opt_diff >= 0); |
9687 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 9688 | if (max_diff == 0) |
43cd72b9 | 9689 | return 0; |
d2a033cd | 9690 | |
43cd72b9 BW |
9691 | if (fragP) |
9692 | fragP = fragP->fr_next; | |
9693 | ||
9694 | while (fragP && opt_diff < max_diff && address) | |
9695 | { | |
9696 | /* We only use these to determine if we can exit early | |
c138bc38 | 9697 | because there will be plenty of ways to align future |
43cd72b9 | 9698 | align frags. */ |
d77b99c9 | 9699 | int glob_widens = 0; |
43cd72b9 BW |
9700 | int dnn = 0; |
9701 | int dw = 0; | |
9702 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
9703 | address = find_address_of_next_align_frag |
9704 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 9705 | /* If there is a padable portion, then skip. */ |
664df4e4 | 9706 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 9707 | address = 0; |
43cd72b9 | 9708 | |
c138bc38 | 9709 | if (address) |
43cd72b9 BW |
9710 | { |
9711 | offsetT next_m_diff; | |
9712 | offsetT next_o_diff; | |
9713 | ||
9714 | /* Downrange frags haven't had stretch added to them yet. */ | |
9715 | address += stretch; | |
9716 | ||
9717 | /* The address also includes any text expansion from this | |
9718 | frag in a previous pass, but we don't want that. */ | |
9719 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
9720 | ||
9721 | /* Assume we are going to move at least opt_diff. In | |
9722 | reality, we might not be able to, but assuming that | |
9723 | we will helps catch cases where moving opt_diff pushes | |
9724 | the next target from aligned to unaligned. */ | |
9725 | address += opt_diff; | |
9726 | ||
9727 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
9728 | ||
9729 | /* Now cleanup for the adjustments to address. */ | |
9730 | next_o_diff += opt_diff; | |
9731 | next_m_diff += opt_diff; | |
9732 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
9733 | opt_diff = next_o_diff; | |
9734 | if (next_m_diff < max_diff) | |
9735 | max_diff = next_m_diff; | |
9736 | fragP = fragP->fr_next; | |
9737 | } | |
9738 | } | |
d2a033cd | 9739 | |
43cd72b9 BW |
9740 | /* If there are enough wideners in between, do it. */ |
9741 | if (paddable) | |
9742 | { | |
9743 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
9744 | { | |
1beeb686 | 9745 | gas_assert (opt_diff <= (signed) xtensa_fetch_width); |
43cd72b9 BW |
9746 | return opt_diff; |
9747 | } | |
9748 | return 0; | |
9749 | } | |
c138bc38 | 9750 | local_stretch_amount |
43cd72b9 BW |
9751 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
9752 | num_widens, local_opt_diff); | |
c138bc38 BW |
9753 | global_stretch_amount |
9754 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 9755 | num_widens, opt_diff); |
c138bc38 BW |
9756 | /* If the condition below is true, then the frag couldn't |
9757 | stretch the correct amount for the global case, so we just | |
9758 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
9759 | the correct alignment in the global case. */ |
9760 | if (global_stretch_amount < local_stretch_amount) | |
9761 | stretch_amount = local_stretch_amount; | |
9762 | else | |
9763 | stretch_amount = global_stretch_amount; | |
d2a033cd | 9764 | |
43cd72b9 BW |
9765 | if (this_frag->fr_subtype == RELAX_SLOTS |
9766 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 9767 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
9768 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9769 | { | |
9770 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 9771 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 9772 | else |
9c2799c2 | 9773 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
9774 | } |
9775 | } | |
9776 | return stretch_amount; | |
9777 | } | |
9778 | ||
9779 | ||
9780 | /* The idea: widen everything you can to get a target or loop aligned, | |
9781 | then start using NOPs. | |
9782 | ||
43cd72b9 BW |
9783 | wide_nops = the number of wide NOPs available for aligning |
9784 | narrow_nops = the number of narrow NOPs available for aligning | |
9785 | (a subset of wide_nops) | |
9786 | widens = the number of narrow instructions that should be widened | |
9787 | ||
43cd72b9 BW |
9788 | */ |
9789 | ||
9790 | static long | |
7fa3d080 BW |
9791 | bytes_to_stretch (fragS *this_frag, |
9792 | int wide_nops, | |
9793 | int narrow_nops, | |
9794 | int num_widens, | |
9795 | int desired_diff) | |
43cd72b9 | 9796 | { |
19ef5f3d SA |
9797 | int nops_needed; |
9798 | int nop_bytes; | |
9799 | int extra_bytes; | |
43cd72b9 BW |
9800 | int bytes_short = desired_diff - num_widens; |
9801 | ||
3739860c | 9802 | gas_assert (desired_diff >= 0 |
1beeb686 | 9803 | && desired_diff < (signed) xtensa_fetch_width); |
43cd72b9 BW |
9804 | if (desired_diff == 0) |
9805 | return 0; | |
c138bc38 | 9806 | |
9c2799c2 | 9807 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 9808 | |
43cd72b9 BW |
9809 | /* Always prefer widening to NOP-filling. */ |
9810 | if (bytes_short < 0) | |
9811 | { | |
9812 | /* There are enough RELAX_NARROW frags after this one | |
9813 | to align the target without widening this frag in any way. */ | |
9814 | return 0; | |
9815 | } | |
c138bc38 | 9816 | |
43cd72b9 BW |
9817 | if (bytes_short == 0) |
9818 | { | |
9819 | /* Widen every narrow between here and the align target | |
9820 | and the align target will be properly aligned. */ | |
9821 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9822 | return 0; | |
9823 | else | |
9824 | return 1; | |
9825 | } | |
c138bc38 | 9826 | |
43cd72b9 BW |
9827 | /* From here we will need at least one NOP to get an alignment. |
9828 | However, we may not be able to align at all, in which case, | |
9829 | don't widen. */ | |
19ef5f3d SA |
9830 | nops_needed = desired_diff / 3; |
9831 | ||
9832 | /* If there aren't enough nops, don't widen. */ | |
9833 | if (nops_needed > wide_nops) | |
9834 | return 0; | |
9835 | ||
9836 | /* First try it with all wide nops. */ | |
9837 | nop_bytes = nops_needed * 3; | |
9838 | extra_bytes = desired_diff - nop_bytes; | |
9839 | ||
9840 | if (nop_bytes + num_widens >= desired_diff) | |
43cd72b9 | 9841 | { |
19ef5f3d SA |
9842 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9843 | return 3; | |
9844 | else if (num_widens == extra_bytes) | |
9845 | return 1; | |
9846 | return 0; | |
e0001a05 | 9847 | } |
19ef5f3d SA |
9848 | |
9849 | /* Add a narrow nop. */ | |
9850 | nops_needed++; | |
9851 | nop_bytes += 2; | |
9852 | extra_bytes -= 2; | |
9853 | if (narrow_nops == 0 || nops_needed > wide_nops) | |
9854 | return 0; | |
9855 | ||
9856 | if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) | |
43cd72b9 | 9857 | { |
19ef5f3d SA |
9858 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9859 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
9860 | else if (num_widens == extra_bytes) | |
9861 | return 1; | |
9862 | return 0; | |
9863 | } | |
e0001a05 | 9864 | |
19ef5f3d SA |
9865 | /* Replace a wide nop with a narrow nop--we can get here if |
9866 | extra_bytes was negative in the previous conditional. */ | |
9867 | if (narrow_nops == 1) | |
9868 | return 0; | |
9869 | nop_bytes--; | |
9870 | extra_bytes++; | |
9871 | if (nop_bytes + num_widens >= desired_diff) | |
9872 | { | |
9873 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9874 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
9875 | else if (num_widens == extra_bytes) | |
9876 | return 1; | |
9877 | return 0; | |
43cd72b9 | 9878 | } |
19ef5f3d SA |
9879 | |
9880 | /* If we can't satisfy any of the above cases, then we can't align | |
9881 | using padding or fill nops. */ | |
43cd72b9 | 9882 | return 0; |
e0001a05 NC |
9883 | } |
9884 | ||
9885 | ||
a82c7d90 DW |
9886 | static struct trampoline_frag * |
9887 | search_trampolines (TInsn *tinsn, fragS *fragP, bfd_boolean unreachable_only) | |
9888 | { | |
9889 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
9890 | struct trampoline_frag *tf = (ts) ? ts->trampoline_list.next : NULL; | |
9891 | struct trampoline_frag *best_tf = NULL; | |
9892 | int best_delta = 0; | |
9893 | int best_addr = 0; | |
9894 | symbolS *sym = tinsn->tok[0].X_add_symbol; | |
9895 | offsetT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; | |
9896 | offsetT addr = fragP->fr_address; | |
9897 | offsetT lower = (addr < target) ? addr : target; | |
9898 | offsetT upper = (addr > target) ? addr : target; | |
9899 | int delta = upper - lower; | |
9900 | offsetT midpoint = lower + delta / 2; | |
9901 | int this_delta = -1; | |
9902 | int this_addr = -1; | |
9903 | ||
9904 | if (delta > 2 * J_RANGE) | |
9905 | { | |
9906 | /* One trampoline won't do; we need multiple. | |
9907 | Choose the farthest trampoline that's still in range of the original | |
9908 | and let a later pass finish the job. */ | |
9909 | for ( ; tf; tf = tf->next) | |
9910 | { | |
9911 | int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0; | |
9912 | ||
9913 | this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9914 | if (lower == addr) | |
9915 | { | |
9916 | /* Forward jump. */ | |
9917 | if (this_addr - addr < J_RANGE) | |
9918 | break; | |
9919 | } | |
9920 | else | |
9921 | { | |
9922 | /* Backward jump. */ | |
9923 | if (next_addr == 0 || addr - next_addr > J_RANGE) | |
9924 | break; | |
9925 | } | |
a82c7d90 | 9926 | } |
d92b6eec MF |
9927 | if (abs (addr - this_addr) < J_RANGE) |
9928 | return tf; | |
9929 | ||
9930 | return NULL; | |
a82c7d90 DW |
9931 | } |
9932 | for ( ; tf; tf = tf->next) | |
9933 | { | |
9934 | this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9935 | this_delta = abs (this_addr - midpoint); | |
9936 | if (unreachable_only && tf->needs_jump_around) | |
9937 | continue; | |
9938 | if (!best_tf || this_delta < best_delta) | |
9939 | { | |
9940 | best_tf = tf; | |
9941 | best_delta = this_delta; | |
9942 | best_addr = this_addr; | |
9943 | } | |
9944 | } | |
9945 | ||
9946 | if (best_tf && | |
9947 | best_delta < J_RANGE && | |
9948 | abs(best_addr - lower) < J_RANGE && | |
9949 | abs(best_addr - upper) < J_RANGE) | |
9950 | return best_tf; | |
9951 | ||
9952 | return NULL; /* No suitable trampoline found. */ | |
9953 | } | |
9954 | ||
9955 | ||
9956 | static struct trampoline_frag * | |
9957 | get_best_trampoline (TInsn *tinsn, fragS *fragP) | |
9958 | { | |
9959 | struct trampoline_frag *tf = NULL; | |
9960 | ||
9961 | tf = search_trampolines (tinsn, fragP, TRUE); /* Try unreachable first. */ | |
9962 | ||
9963 | if (tf == NULL) | |
9964 | tf = search_trampolines (tinsn, fragP, FALSE); /* Try ones needing a jump-around, too. */ | |
9965 | ||
9966 | return tf; | |
9967 | } | |
9968 | ||
9969 | ||
9970 | static void | |
9971 | check_and_update_trampolines (void) | |
9972 | { | |
9973 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
9974 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
9975 | struct trampoline_frag *prev = &ts->trampoline_list; | |
9976 | ||
9977 | for ( ; tf; prev = tf, tf = tf->next) | |
9978 | { | |
9979 | if (tf->fragP->fr_var < 3) | |
9980 | { | |
9981 | frag_wane (tf->fragP); | |
9982 | prev->next = tf->next; | |
9983 | tf->fragP = NULL; | |
9984 | } | |
9985 | } | |
9986 | } | |
9987 | ||
fec68fb1 MF |
9988 | static fixS *xg_append_jump (fragS *fragP, fixS *jump_around, |
9989 | symbolS *sym, offsetT offset) | |
9990 | { | |
9991 | fixS *fixP; | |
9992 | TInsn insn; | |
9993 | xtensa_format fmt; | |
9994 | xtensa_isa isa = xtensa_default_isa; | |
9995 | ||
9996 | gas_assert (fragP->fr_var >= 3); | |
9997 | tinsn_init (&insn); | |
9998 | insn.insn_type = ITYPE_INSN; | |
9999 | insn.opcode = xtensa_j_opcode; | |
10000 | insn.ntok = 1; | |
10001 | set_expr_symbol_offset (&insn.tok[0], sym, offset); | |
10002 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10003 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10004 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10005 | xtensa_insnbuf_to_chars (isa, trampoline_buf, | |
10006 | (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3); | |
10007 | fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE, | |
10008 | BFD_RELOC_XTENSA_SLOT0_OP); | |
10009 | fixP->tc_fix_data.slot = 0; | |
10010 | ||
10011 | fragP->fr_fix += 3; | |
10012 | fragP->fr_var -= 3; | |
10013 | ||
10014 | /* Adjust the jump around this trampoline (if present). */ | |
10015 | if (jump_around) | |
10016 | jump_around->fx_offset += 3; | |
10017 | ||
10018 | return fixP; | |
10019 | } | |
10020 | ||
a82c7d90 DW |
10021 | |
10022 | static int | |
10023 | init_trampoline_frag (struct trampoline_frag *trampP) | |
10024 | { | |
10025 | fragS *fp = trampP->fragP; | |
10026 | int growth = 0; | |
10027 | ||
10028 | if (fp->fr_fix == 0) | |
10029 | { | |
10030 | symbolS *lsym; | |
10031 | char label[10 + 2 * sizeof(fp)]; | |
a82c7d90 | 10032 | |
fec68fb1 | 10033 | sprintf (label, ".L0_TR_%p", fp); |
a82c7d90 DW |
10034 | lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp); |
10035 | fp->fr_symbol = lsym; | |
10036 | if (trampP->needs_jump_around) | |
10037 | { | |
fec68fb1 | 10038 | trampP->fixP = xg_append_jump (fp, NULL, lsym, 3); |
a82c7d90 | 10039 | growth = 3; |
a82c7d90 DW |
10040 | } |
10041 | } | |
10042 | return growth; | |
10043 | } | |
10044 | ||
10045 | ||
10046 | static int | |
10047 | add_jump_to_trampoline (struct trampoline_frag *trampP, fragS *origfrag) | |
10048 | { | |
10049 | fragS *tramp = trampP->fragP; | |
24e5b4e6 MF |
10050 | int i, slot = -1; |
10051 | ||
10052 | for (i = 0; i < MAX_SLOTS; ++i) | |
10053 | if (origfrag->tc_frag_data.slot_symbols[i]) | |
10054 | { | |
10055 | gas_assert (slot == -1); | |
10056 | slot = i; | |
10057 | } | |
10058 | ||
10059 | gas_assert (slot >= 0 && slot < MAX_SLOTS); | |
a82c7d90 | 10060 | |
a82c7d90 | 10061 | /* Assemble a jump to the target label in the trampoline frag. */ |
fec68fb1 MF |
10062 | xg_append_jump (tramp, trampP->fixP, |
10063 | origfrag->tc_frag_data.slot_symbols[slot], | |
10064 | origfrag->tc_frag_data.slot_offsets[slot]); | |
10065 | ||
a82c7d90 | 10066 | /* Modify the original j to point here. */ |
fec68fb1 | 10067 | origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol; |
24e5b4e6 | 10068 | origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; |
fec68fb1 | 10069 | |
a82c7d90 DW |
10070 | /* If trampoline is full, remove it from the list. */ |
10071 | check_and_update_trampolines (); | |
10072 | ||
fec68fb1 | 10073 | return 3; |
a82c7d90 DW |
10074 | } |
10075 | ||
10076 | ||
e0001a05 | 10077 | static long |
7fa3d080 BW |
10078 | relax_frag_immed (segT segP, |
10079 | fragS *fragP, | |
10080 | long stretch, | |
10081 | int min_steps, | |
10082 | xtensa_format fmt, | |
10083 | int slot, | |
10084 | int *stretched_p, | |
10085 | bfd_boolean estimate_only) | |
e0001a05 | 10086 | { |
43cd72b9 | 10087 | TInsn tinsn; |
e0001a05 NC |
10088 | int old_size; |
10089 | bfd_boolean negatable_branch = FALSE; | |
10090 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 10091 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 10092 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
10093 | IStack istack; |
10094 | offsetT frag_offset; | |
10095 | int num_steps; | |
e0001a05 | 10096 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 10097 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 10098 | |
9c2799c2 | 10099 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10100 | |
b5e4a23d BW |
10101 | xg_clear_vinsn (&cur_vinsn); |
10102 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 10103 | if (cur_vinsn.num_slots > 1) |
def13efb | 10104 | from_wide_insn = TRUE; |
43cd72b9 | 10105 | |
b5e4a23d | 10106 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 10107 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 10108 | |
64b607e6 | 10109 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 10110 | return 0; |
e0001a05 | 10111 | |
b08b5071 | 10112 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10113 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 10114 | |
43cd72b9 | 10115 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 10116 | |
43cd72b9 | 10117 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10118 | |
10119 | /* Special case: replace a branch to the next instruction with a NOP. | |
10120 | This is required to work around a hardware bug in T1040.0 and also | |
10121 | serves as an optimization. */ | |
10122 | ||
10123 | if (branch_jmp_to_next | |
10124 | && ((old_size == 2) || (old_size == 3)) | |
10125 | && !next_frag_is_loop_target (fragP)) | |
10126 | return 0; | |
10127 | ||
10128 | /* Here is the fun stuff: Get the immediate field from this | |
10129 | instruction. If it fits, we are done. If not, find the next | |
10130 | instruction sequence that fits. */ | |
10131 | ||
10132 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10133 | istack_init (&istack); | |
43cd72b9 | 10134 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 10135 | min_steps, stretch); |
9c2799c2 | 10136 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 10137 | |
43cd72b9 | 10138 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
10139 | |
10140 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 10141 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
10142 | literal_diff |
10143 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 10144 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
10145 | |
10146 | if (from_wide_insn) | |
43cd72b9 | 10147 | { |
2276bc20 BW |
10148 | int first = 0; |
10149 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
10150 | first++; | |
10151 | ||
43cd72b9 BW |
10152 | num_text_bytes += old_size; |
10153 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
10154 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
10155 | else |
10156 | { | |
10157 | /* The first instruction in the relaxed sequence will go after | |
10158 | the current wide instruction, and thus its symbolic immediates | |
10159 | might not fit. */ | |
3739860c | 10160 | |
2276bc20 | 10161 | istack_init (&istack); |
3739860c | 10162 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, |
2276bc20 BW |
10163 | frag_offset + old_size, |
10164 | min_steps, stretch + old_size); | |
9c2799c2 | 10165 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 | 10166 | |
3739860c | 10167 | fragP->tc_frag_data.slot_subtypes[slot] |
2276bc20 BW |
10168 | = (int) RELAX_IMMED + num_steps; |
10169 | ||
10170 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
3739860c | 10171 | literal_diff |
2276bc20 | 10172 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; |
3739860c | 10173 | |
2276bc20 BW |
10174 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; |
10175 | } | |
43cd72b9 | 10176 | } |
def13efb | 10177 | |
43cd72b9 BW |
10178 | total_text_diff = num_text_bytes - old_size; |
10179 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
10180 | |
10181 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
10182 | gas_assert (num_text_bytes >= 0); |
10183 | gas_assert (literal_diff >= 0); | |
10184 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 10185 | |
43cd72b9 BW |
10186 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
10187 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
10188 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
10189 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
10190 | |
10191 | /* Find the associated expandable literal for this. */ | |
10192 | if (literal_diff != 0) | |
10193 | { | |
2276bc20 | 10194 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10195 | if (lit_fragP) |
10196 | { | |
9c2799c2 | 10197 | gas_assert (literal_diff == 4); |
e0001a05 NC |
10198 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
10199 | ||
10200 | /* We expect that the literal section state has NOT been | |
10201 | modified yet. */ | |
9c2799c2 | 10202 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
10203 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
10204 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
10205 | ||
10206 | /* We need to mark this section for another iteration | |
10207 | of relaxation. */ | |
10208 | (*stretched_p)++; | |
10209 | } | |
10210 | } | |
10211 | ||
43cd72b9 | 10212 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 10213 | update_next_frag_state (fragP); |
e0001a05 | 10214 | |
a82c7d90 DW |
10215 | /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ |
10216 | if (istack.ninsn > 2 && | |
10217 | istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && | |
10218 | istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && | |
10219 | istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) | |
10220 | { | |
10221 | TInsn *jinsn = &istack.insn[istack.ninsn - 2]; | |
10222 | ||
10223 | if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, total_text_diff)) | |
10224 | { | |
10225 | struct trampoline_frag *tf = get_best_trampoline (jinsn, fragP); | |
10226 | ||
10227 | if (tf) | |
10228 | { | |
10229 | this_text_diff += init_trampoline_frag (tf); | |
10230 | this_text_diff += add_jump_to_trampoline (tf, fragP); | |
10231 | } | |
10232 | else | |
10233 | { | |
10234 | /* If target symbol is undefined, assume it will reach once linked. */ | |
10235 | expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; | |
10236 | ||
10237 | if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) | |
10238 | { | |
10239 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10240 | _("jump target out of range; no usable trampoline found")); | |
10241 | } | |
10242 | } | |
10243 | } | |
10244 | } | |
10245 | ||
43cd72b9 | 10246 | return this_text_diff; |
e0001a05 NC |
10247 | } |
10248 | ||
10249 | \f | |
10250 | /* md_convert_frag Hook and Helper Functions. */ | |
10251 | ||
7fa3d080 BW |
10252 | static void convert_frag_align_next_opcode (fragS *); |
10253 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
10254 | static void convert_frag_fill_nop (fragS *); | |
10255 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
10256 | ||
e0001a05 | 10257 | void |
7fa3d080 | 10258 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 10259 | { |
43cd72b9 BW |
10260 | static xtensa_insnbuf vbuf = NULL; |
10261 | xtensa_isa isa = xtensa_default_isa; | |
10262 | int slot; | |
10263 | int num_slots; | |
10264 | xtensa_format fmt; | |
3b4dbbbf | 10265 | const char *file_name; |
d77b99c9 | 10266 | unsigned line; |
e0001a05 | 10267 | |
3b4dbbbf | 10268 | file_name = as_where (&line); |
e0001a05 NC |
10269 | new_logical_line (fragp->fr_file, fragp->fr_line); |
10270 | ||
10271 | switch (fragp->fr_subtype) | |
10272 | { | |
10273 | case RELAX_ALIGN_NEXT_OPCODE: | |
10274 | /* Always convert. */ | |
10275 | convert_frag_align_next_opcode (fragp); | |
10276 | break; | |
10277 | ||
10278 | case RELAX_DESIRE_ALIGN: | |
10279 | /* Do nothing. If not aligned already, too bad. */ | |
10280 | break; | |
10281 | ||
43cd72b9 BW |
10282 | case RELAX_LITERAL: |
10283 | case RELAX_LITERAL_FINAL: | |
10284 | break; | |
10285 | ||
10286 | case RELAX_SLOTS: | |
10287 | if (vbuf == NULL) | |
10288 | vbuf = xtensa_insnbuf_alloc (isa); | |
10289 | ||
d77b99c9 BW |
10290 | xtensa_insnbuf_from_chars |
10291 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
10292 | fmt = xtensa_format_decode (isa, vbuf); |
10293 | num_slots = xtensa_format_num_slots (isa, fmt); | |
10294 | ||
10295 | for (slot = 0; slot < num_slots; slot++) | |
10296 | { | |
10297 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
10298 | { | |
10299 | case RELAX_NARROW: | |
10300 | convert_frag_narrow (sec, fragp, fmt, slot); | |
10301 | break; | |
10302 | ||
10303 | case RELAX_IMMED: | |
10304 | case RELAX_IMMED_STEP1: | |
10305 | case RELAX_IMMED_STEP2: | |
b81bf389 | 10306 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
10307 | /* Place the immediate. */ |
10308 | convert_frag_immed | |
10309 | (sec, fragp, | |
10310 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
10311 | fmt, slot); | |
10312 | break; | |
10313 | ||
10314 | default: | |
10315 | /* This is OK because some slots could have | |
10316 | relaxations and others have none. */ | |
10317 | break; | |
10318 | } | |
10319 | } | |
10320 | break; | |
10321 | ||
10322 | case RELAX_UNREACHABLE: | |
10323 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
10324 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
10325 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
10326 | frag_wane (fragp); | |
e0001a05 NC |
10327 | break; |
10328 | ||
43cd72b9 BW |
10329 | case RELAX_MAYBE_UNREACHABLE: |
10330 | case RELAX_MAYBE_DESIRE_ALIGN: | |
10331 | frag_wane (fragp); | |
e0001a05 NC |
10332 | break; |
10333 | ||
43cd72b9 BW |
10334 | case RELAX_FILL_NOP: |
10335 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
10336 | break; |
10337 | ||
10338 | case RELAX_LITERAL_NR: | |
10339 | if (use_literal_section) | |
10340 | { | |
10341 | /* This should have been handled during relaxation. When | |
10342 | relaxing a code segment, literals sometimes need to be | |
10343 | added to the corresponding literal segment. If that | |
10344 | literal segment has already been relaxed, then we end up | |
10345 | in this situation. Marking the literal segments as data | |
10346 | would make this happen less often (since GAS always relaxes | |
10347 | code before data), but we could still get into trouble if | |
10348 | there are instructions in a segment that is not marked as | |
10349 | containing code. Until we can implement a better solution, | |
10350 | cheat and adjust the addresses of all the following frags. | |
10351 | This could break subsequent alignments, but the linker's | |
10352 | literal coalescing will do that anyway. */ | |
10353 | ||
10354 | fragS *f; | |
10355 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 10356 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
10357 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
10358 | fragp->fr_var -= 4; | |
10359 | fragp->fr_fix += 4; | |
10360 | for (f = fragp->fr_next; f; f = f->fr_next) | |
10361 | f->fr_address += 4; | |
10362 | } | |
10363 | else | |
10364 | as_bad (_("invalid relaxation fragment result")); | |
10365 | break; | |
a82c7d90 DW |
10366 | |
10367 | case RELAX_TRAMPOLINE: | |
10368 | break; | |
e0001a05 NC |
10369 | } |
10370 | ||
10371 | fragp->fr_var = 0; | |
10372 | new_logical_line (file_name, line); | |
10373 | } | |
10374 | ||
10375 | ||
7fa3d080 BW |
10376 | static void |
10377 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
10378 | { |
10379 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
10380 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
10381 | addressT aligned_address; | |
d77b99c9 BW |
10382 | offsetT fill_size; |
10383 | int nop, nop_count; | |
e0001a05 NC |
10384 | |
10385 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
10386 | fragp->fr_fix); | |
10387 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
10388 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
10389 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
10390 | ||
d77b99c9 | 10391 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 10392 | { |
d77b99c9 BW |
10393 | int nop_size; |
10394 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
10395 | |
10396 | assemble_nop (nop_size, nop_buf); | |
10397 | nop_buf += nop_size; | |
10398 | } | |
10399 | ||
10400 | fragp->fr_fix += fill_size; | |
10401 | fragp->fr_var -= fill_size; | |
10402 | } | |
10403 | ||
10404 | ||
10405 | static void | |
7fa3d080 | 10406 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 10407 | { |
43cd72b9 | 10408 | TInsn tinsn, single_target; |
84b08ed9 | 10409 | int size, old_size, diff; |
e0001a05 NC |
10410 | offsetT frag_offset; |
10411 | ||
9c2799c2 | 10412 | gas_assert (slot == 0); |
43cd72b9 BW |
10413 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
10414 | ||
b5e4a23d | 10415 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 10416 | { |
9c2799c2 | 10417 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
10418 | || fragP->tc_frag_data.text_expansion[0] == 0); |
10419 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
10420 | fmt, slot); | |
10421 | return; | |
10422 | } | |
10423 | ||
10424 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
10425 | { |
10426 | /* No conversion. */ | |
10427 | fragP->fr_var = 0; | |
10428 | return; | |
10429 | } | |
10430 | ||
9c2799c2 | 10431 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10432 | |
43cd72b9 BW |
10433 | /* Frags in this relaxation state should only contain |
10434 | single instruction bundles. */ | |
10435 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
10436 | |
10437 | /* Just convert it to a wide form.... */ | |
10438 | size = 0; | |
43cd72b9 | 10439 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
10440 | |
10441 | tinsn_init (&single_target); | |
10442 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10443 | ||
84b08ed9 | 10444 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
10445 | { |
10446 | as_bad (_("unable to widen instruction")); | |
10447 | return; | |
10448 | } | |
10449 | ||
10450 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
10451 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
10452 | frag_offset, TRUE); | |
e0001a05 NC |
10453 | |
10454 | diff = size - old_size; | |
9c2799c2 NC |
10455 | gas_assert (diff >= 0); |
10456 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
10457 | fragP->fr_var -= diff; |
10458 | fragP->fr_fix += diff; | |
10459 | ||
10460 | /* clean it up */ | |
10461 | fragP->fr_var = 0; | |
10462 | } | |
10463 | ||
10464 | ||
10465 | static void | |
7fa3d080 | 10466 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
10467 | { |
10468 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
10469 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10470 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
10471 | - fragP->fr_address - fragP->fr_fix)); |
10472 | if (size == 0) | |
10473 | { | |
10474 | /* No conversion. */ | |
10475 | fragP->fr_var = 0; | |
10476 | return; | |
10477 | } | |
10478 | assemble_nop (size, loc); | |
10479 | fragP->tc_frag_data.is_insn = TRUE; | |
10480 | fragP->fr_var -= size; | |
10481 | fragP->fr_fix += size; | |
10482 | frag_wane (fragP); | |
10483 | } | |
10484 | ||
10485 | ||
7fa3d080 BW |
10486 | static fixS *fix_new_exp_in_seg |
10487 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
10488 | bfd_reloc_code_real_type); | |
10489 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
10490 | ||
43cd72b9 | 10491 | static void |
7fa3d080 BW |
10492 | convert_frag_immed (segT segP, |
10493 | fragS *fragP, | |
10494 | int min_steps, | |
10495 | xtensa_format fmt, | |
10496 | int slot) | |
e0001a05 NC |
10497 | { |
10498 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 10499 | TInsn orig_tinsn; |
e0001a05 | 10500 | bfd_boolean expanded = FALSE; |
e0001a05 | 10501 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 10502 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 10503 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 10504 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
10505 | int bytes; |
10506 | bfd_boolean is_loop; | |
e0001a05 | 10507 | |
9c2799c2 | 10508 | gas_assert (fr_opcode != NULL); |
e0001a05 | 10509 | |
b5e4a23d | 10510 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 10511 | |
b5e4a23d | 10512 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 10513 | if (cur_vinsn.num_slots > 1) |
def13efb | 10514 | from_wide_insn = TRUE; |
e0001a05 | 10515 | |
b5e4a23d | 10516 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
10517 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
10518 | ||
10519 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 10520 | |
b08b5071 | 10521 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10522 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
10523 | |
10524 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
10525 | { | |
10526 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
10527 | bytes = xtensa_format_length (isa, fmt); |
10528 | if (bytes >= 4) | |
10529 | { | |
b5e4a23d BW |
10530 | cur_vinsn.slots[slot].opcode = |
10531 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
10532 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
10533 | } |
10534 | else | |
10535 | { | |
10536 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10537 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 10538 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
10539 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
10540 | } | |
e7da6241 | 10541 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 10542 | xtensa_insnbuf_to_chars |
b5e4a23d | 10543 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
10544 | fragP->fr_var = 0; |
10545 | } | |
7c834684 | 10546 | else |
e0001a05 | 10547 | { |
43cd72b9 BW |
10548 | /* Here is the fun stuff: Get the immediate field from this |
10549 | instruction. If it fits, we're done. If not, find the next | |
10550 | instruction sequence that fits. */ | |
10551 | ||
e0001a05 NC |
10552 | IStack istack; |
10553 | int i; | |
10554 | symbolS *lit_sym = NULL; | |
10555 | int total_size = 0; | |
43cd72b9 | 10556 | int target_offset = 0; |
e0001a05 NC |
10557 | int old_size; |
10558 | int diff; | |
10559 | symbolS *gen_label = NULL; | |
10560 | offsetT frag_offset; | |
43cd72b9 | 10561 | bfd_boolean first = TRUE; |
e0001a05 | 10562 | |
43cd72b9 | 10563 | /* It does not fit. Find something that does and |
e0001a05 | 10564 | convert immediately. */ |
43cd72b9 | 10565 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 10566 | istack_init (&istack); |
43cd72b9 | 10567 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
10568 | segP, fragP, frag_offset, min_steps, 0); |
10569 | ||
43cd72b9 | 10570 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10571 | |
10572 | /* Assemble this right inline. */ | |
10573 | ||
10574 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 10575 | target_offset = 0; |
e0001a05 NC |
10576 | for (i = 0; i < istack.ninsn; i++) |
10577 | { | |
43cd72b9 | 10578 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10579 | fragS *lit_frag; |
10580 | ||
43cd72b9 | 10581 | switch (tinsn->insn_type) |
e0001a05 NC |
10582 | { |
10583 | case ITYPE_LITERAL: | |
10584 | if (lit_sym != NULL) | |
10585 | as_bad (_("multiple literals in expansion")); | |
10586 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 10587 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10588 | if (lit_frag == NULL) |
10589 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 10590 | if (tinsn->ntok != 1) |
e0001a05 NC |
10591 | as_bad (_("number of literal tokens != 1")); |
10592 | ||
10593 | /* Set the literal symbol and add a fixup. */ | |
10594 | lit_sym = lit_frag->fr_symbol; | |
10595 | break; | |
10596 | ||
10597 | case ITYPE_LABEL: | |
43cd72b9 BW |
10598 | if (align_targets && !is_loop) |
10599 | { | |
10600 | fragS *unreach = fragP->fr_next; | |
10601 | while (!(unreach->fr_type == rs_machine_dependent | |
10602 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
10603 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
10604 | { | |
10605 | unreach = unreach->fr_next; | |
10606 | } | |
10607 | ||
9c2799c2 | 10608 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
10609 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
10610 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
10611 | ||
10612 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
10613 | } | |
9c2799c2 | 10614 | gas_assert (gen_label == NULL); |
e0001a05 | 10615 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, |
43cd72b9 BW |
10616 | fr_opcode - fragP->fr_literal |
10617 | + target_offset, fragP); | |
e0001a05 NC |
10618 | break; |
10619 | ||
10620 | case ITYPE_INSN: | |
def13efb | 10621 | if (first && from_wide_insn) |
43cd72b9 BW |
10622 | { |
10623 | target_offset += xtensa_format_length (isa, fmt); | |
10624 | first = FALSE; | |
10625 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10626 | target_offset += xg_get_single_size (tinsn->opcode); | |
10627 | } | |
10628 | else | |
10629 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
10630 | break; |
10631 | } | |
10632 | } | |
10633 | ||
10634 | total_size = 0; | |
43cd72b9 | 10635 | first = TRUE; |
e0001a05 NC |
10636 | for (i = 0; i < istack.ninsn; i++) |
10637 | { | |
43cd72b9 | 10638 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10639 | fragS *lit_frag; |
10640 | int size; | |
10641 | segT target_seg; | |
43cd72b9 | 10642 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 10643 | |
43cd72b9 | 10644 | switch (tinsn->insn_type) |
e0001a05 NC |
10645 | { |
10646 | case ITYPE_LITERAL: | |
43cd72b9 BW |
10647 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
10648 | /* Already checked. */ | |
9c2799c2 NC |
10649 | gas_assert (lit_frag != NULL); |
10650 | gas_assert (lit_sym != NULL); | |
10651 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 10652 | /* Add a fixup. */ |
e0001a05 | 10653 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 10654 | gas_assert (target_seg); |
28dbbc02 | 10655 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 10656 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 10657 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
10658 | break; |
10659 | ||
10660 | case ITYPE_LABEL: | |
10661 | break; | |
10662 | ||
10663 | case ITYPE_INSN: | |
43cd72b9 BW |
10664 | xg_resolve_labels (tinsn, gen_label); |
10665 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 10666 | if (from_wide_insn && first) |
43cd72b9 BW |
10667 | { |
10668 | first = FALSE; | |
10669 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10670 | { | |
b5e4a23d | 10671 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
10672 | } |
10673 | else | |
10674 | { | |
b5e4a23d | 10675 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 10676 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 10677 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 10678 | } |
b5e4a23d BW |
10679 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
10680 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 10681 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
10682 | fragP->tc_frag_data.is_insn = TRUE; |
10683 | size = xtensa_format_length (isa, fmt); | |
10684 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10685 | { | |
43cd72b9 | 10686 | xg_emit_insn_to_buf |
b2d179be | 10687 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
10688 | immed_instr - fragP->fr_literal + size, TRUE); |
10689 | size += xg_get_single_size (tinsn->opcode); | |
10690 | } | |
10691 | } | |
10692 | else | |
10693 | { | |
43cd72b9 | 10694 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 10695 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 10696 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 10697 | } |
e0001a05 | 10698 | immed_instr += size; |
43cd72b9 | 10699 | total_size += size; |
e0001a05 NC |
10700 | break; |
10701 | } | |
10702 | } | |
10703 | ||
10704 | diff = total_size - old_size; | |
9c2799c2 | 10705 | gas_assert (diff >= 0); |
e0001a05 NC |
10706 | if (diff != 0) |
10707 | expanded = TRUE; | |
9c2799c2 | 10708 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
10709 | fragP->fr_var -= diff; |
10710 | fragP->fr_fix += diff; | |
10711 | } | |
10712 | ||
e0001a05 | 10713 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 10714 | if (is_loop) |
e0001a05 NC |
10715 | { |
10716 | symbolS *sym; | |
43cd72b9 | 10717 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
10718 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10719 | { | |
10720 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10721 | return; | |
10722 | } | |
43cd72b9 | 10723 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
10724 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10725 | { | |
10726 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10727 | return; | |
10728 | } | |
10729 | } | |
10730 | ||
43cd72b9 BW |
10731 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
10732 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 10733 | |
43cd72b9 | 10734 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
10735 | { |
10736 | /* Add an expansion note on the expanded instruction. */ | |
10737 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 10738 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 10739 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
10740 | } |
10741 | } | |
10742 | ||
10743 | ||
10744 | /* Add a new fix expression into the desired segment. We have to | |
10745 | switch to that segment to do this. */ | |
10746 | ||
10747 | static fixS * | |
7fa3d080 BW |
10748 | fix_new_exp_in_seg (segT new_seg, |
10749 | subsegT new_subseg, | |
10750 | fragS *frag, | |
10751 | int where, | |
10752 | int size, | |
10753 | expressionS *exp, | |
10754 | int pcrel, | |
10755 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
10756 | { |
10757 | fixS *new_fix; | |
10758 | segT seg = now_seg; | |
10759 | subsegT subseg = now_subseg; | |
43cd72b9 | 10760 | |
9c2799c2 | 10761 | gas_assert (new_seg != 0); |
e0001a05 NC |
10762 | subseg_set (new_seg, new_subseg); |
10763 | ||
e0001a05 NC |
10764 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
10765 | subseg_set (seg, subseg); | |
10766 | return new_fix; | |
10767 | } | |
10768 | ||
10769 | ||
43cd72b9 BW |
10770 | /* Relax a loop instruction so that it can span loop >256 bytes. |
10771 | ||
10772 | loop as, .L1 | |
10773 | .L0: | |
10774 | rsr as, LEND | |
10775 | wsr as, LBEG | |
10776 | addi as, as, lo8 (label-.L1) | |
10777 | addmi as, as, mid8 (label-.L1) | |
10778 | wsr as, LEND | |
10779 | isync | |
10780 | rsr as, LCOUNT | |
10781 | addi as, as, 1 | |
10782 | .L1: | |
10783 | <<body>> | |
10784 | label: | |
10785 | */ | |
e0001a05 NC |
10786 | |
10787 | static void | |
7fa3d080 | 10788 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
10789 | { |
10790 | TInsn loop_insn; | |
10791 | TInsn addi_insn; | |
10792 | TInsn addmi_insn; | |
10793 | unsigned long target; | |
10794 | static xtensa_insnbuf insnbuf = NULL; | |
10795 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
10796 | xtensa_isa isa = xtensa_default_isa; | |
10797 | addressT loop_offset; | |
10798 | addressT addi_offset = 9; | |
10799 | addressT addmi_offset = 12; | |
43cd72b9 | 10800 | fragS *next_fragP; |
d77b99c9 | 10801 | int target_count; |
e0001a05 NC |
10802 | |
10803 | if (!insnbuf) | |
10804 | insnbuf = xtensa_insnbuf_alloc (isa); | |
10805 | ||
10806 | /* Get the loop offset. */ | |
43cd72b9 | 10807 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 10808 | |
43cd72b9 BW |
10809 | /* Validate that there really is a LOOP at the loop_offset. Because |
10810 | loops are not bundleable, we can assume that the instruction will be | |
10811 | in slot 0. */ | |
10812 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
10813 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
10814 | ||
9c2799c2 | 10815 | gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); |
e0001a05 NC |
10816 | addi_offset += loop_offset; |
10817 | addmi_offset += loop_offset; | |
10818 | ||
9c2799c2 | 10819 | gas_assert (tinsn->ntok == 2); |
b08b5071 BW |
10820 | if (tinsn->tok[1].X_op == O_constant) |
10821 | target = tinsn->tok[1].X_add_number; | |
10822 | else if (tinsn->tok[1].X_op == O_symbol) | |
10823 | { | |
10824 | /* Find the fragment. */ | |
10825 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9c2799c2 | 10826 | gas_assert (S_GET_SEGMENT (sym) == segP |
b08b5071 BW |
10827 | || S_GET_SEGMENT (sym) == absolute_section); |
10828 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
10829 | } | |
10830 | else | |
10831 | { | |
10832 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
10833 | target = 0; | |
10834 | } | |
e0001a05 | 10835 | |
e0001a05 NC |
10836 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
10837 | loop_length_hi = loop_length & ~0x0ff; | |
10838 | loop_length_lo = loop_length & 0x0ff; | |
10839 | if (loop_length_lo >= 128) | |
10840 | { | |
10841 | loop_length_lo -= 256; | |
10842 | loop_length_hi += 256; | |
10843 | } | |
10844 | ||
43cd72b9 | 10845 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
10846 | 32512. If the loop is larger than that, then we just fail. */ |
10847 | if (loop_length_hi > 32512) | |
10848 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10849 | _("loop too long for LOOP instruction")); | |
10850 | ||
43cd72b9 | 10851 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
9c2799c2 | 10852 | gas_assert (addi_insn.opcode == xtensa_addi_opcode); |
e0001a05 | 10853 | |
43cd72b9 | 10854 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
9c2799c2 | 10855 | gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); |
e0001a05 NC |
10856 | |
10857 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
10858 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 10859 | |
e0001a05 | 10860 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
10861 | xtensa_insnbuf_to_chars |
10862 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
10863 | |
10864 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
10865 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
10866 | xtensa_insnbuf_to_chars |
10867 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
10868 | |
10869 | /* Walk through all of the frags from here to the loop end | |
10870 | and mark them as no_transform to keep them from being modified | |
10871 | by the linker. If we ever have a relocation for the | |
10872 | addi/addmi of the difference of two symbols we can remove this. */ | |
10873 | ||
10874 | target_count = 0; | |
10875 | for (next_fragP = fragP; next_fragP != NULL; | |
10876 | next_fragP = next_fragP->fr_next) | |
10877 | { | |
b08b5071 | 10878 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
10879 | if (next_fragP->tc_frag_data.is_loop_target) |
10880 | target_count++; | |
10881 | if (target_count == 2) | |
10882 | break; | |
10883 | } | |
e0001a05 NC |
10884 | } |
10885 | ||
b08b5071 BW |
10886 | \f |
10887 | /* A map that keeps information on a per-subsegment basis. This is | |
10888 | maintained during initial assembly, but is invalid once the | |
10889 | subsegments are smashed together. I.E., it cannot be used during | |
10890 | the relaxation. */ | |
e0001a05 | 10891 | |
b08b5071 | 10892 | typedef struct subseg_map_struct |
e0001a05 | 10893 | { |
b08b5071 BW |
10894 | /* the key */ |
10895 | segT seg; | |
10896 | subsegT subseg; | |
e0001a05 | 10897 | |
b08b5071 BW |
10898 | /* the data */ |
10899 | unsigned flags; | |
10900 | float total_freq; /* fall-through + branch target frequency */ | |
10901 | float target_freq; /* branch target frequency alone */ | |
10902 | ||
10903 | struct subseg_map_struct *next; | |
10904 | } subseg_map; | |
e0001a05 | 10905 | |
e0001a05 | 10906 | |
e0001a05 NC |
10907 | static subseg_map *sseg_map = NULL; |
10908 | ||
43cd72b9 | 10909 | static subseg_map * |
7fa3d080 | 10910 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
10911 | { |
10912 | subseg_map *subseg_e; | |
10913 | ||
10914 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 10915 | { |
43cd72b9 | 10916 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 10917 | break; |
e0001a05 | 10918 | } |
b08b5071 BW |
10919 | return subseg_e; |
10920 | } | |
10921 | ||
10922 | ||
10923 | static subseg_map * | |
10924 | add_subseg_info (segT seg, subsegT subseg) | |
10925 | { | |
325801bd | 10926 | subseg_map *subseg_e = XNEW (subseg_map); |
43cd72b9 BW |
10927 | memset (subseg_e, 0, sizeof (subseg_map)); |
10928 | subseg_e->seg = seg; | |
10929 | subseg_e->subseg = subseg; | |
10930 | subseg_e->flags = 0; | |
10931 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
10932 | subseg_e->target_freq = 1.0; |
10933 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
10934 | subseg_e->next = sseg_map; |
10935 | sseg_map = subseg_e; | |
43cd72b9 BW |
10936 | return subseg_e; |
10937 | } | |
e0001a05 | 10938 | |
7fa3d080 BW |
10939 | |
10940 | static unsigned | |
10941 | get_last_insn_flags (segT seg, subsegT subseg) | |
10942 | { | |
10943 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
10944 | if (subseg_e) |
10945 | return subseg_e->flags; | |
10946 | return 0; | |
7fa3d080 BW |
10947 | } |
10948 | ||
10949 | ||
43cd72b9 | 10950 | static void |
7fa3d080 BW |
10951 | set_last_insn_flags (segT seg, |
10952 | subsegT subseg, | |
10953 | unsigned fl, | |
10954 | bfd_boolean val) | |
43cd72b9 BW |
10955 | { |
10956 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
10957 | if (! subseg_e) |
10958 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
10959 | if (val) |
10960 | subseg_e->flags |= fl; | |
10961 | else | |
10962 | subseg_e->flags &= ~fl; | |
10963 | } | |
10964 | ||
b08b5071 BW |
10965 | |
10966 | static float | |
10967 | get_subseg_total_freq (segT seg, subsegT subseg) | |
10968 | { | |
10969 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10970 | if (subseg_e) | |
10971 | return subseg_e->total_freq; | |
10972 | return 1.0; | |
10973 | } | |
10974 | ||
10975 | ||
10976 | static float | |
10977 | get_subseg_target_freq (segT seg, subsegT subseg) | |
10978 | { | |
10979 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10980 | if (subseg_e) | |
10981 | return subseg_e->target_freq; | |
10982 | return 1.0; | |
10983 | } | |
10984 | ||
10985 | ||
10986 | static void | |
10987 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
10988 | { | |
10989 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
10990 | if (! subseg_e) | |
10991 | subseg_e = add_subseg_info (seg, subseg); | |
10992 | subseg_e->total_freq = total_f; | |
10993 | subseg_e->target_freq = target_f; | |
10994 | } | |
10995 | ||
e0001a05 NC |
10996 | \f |
10997 | /* Segment Lists and emit_state Stuff. */ | |
10998 | ||
e0001a05 | 10999 | static void |
7fa3d080 | 11000 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
11001 | { |
11002 | head = head->next; | |
11003 | while (head) | |
11004 | { | |
11005 | segT literal_section = head->seg; | |
11006 | ||
11007 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 11008 | gas_assert (literal_section); |
69852798 AM |
11009 | if (literal_section != stdoutput->sections) |
11010 | { | |
11011 | bfd_section_list_remove (stdoutput, literal_section); | |
11012 | bfd_section_list_prepend (stdoutput, literal_section); | |
11013 | } | |
e0001a05 NC |
11014 | head = head->next; |
11015 | } | |
11016 | } | |
11017 | ||
11018 | ||
7fa3d080 BW |
11019 | static void mark_literal_frags (seg_list *); |
11020 | ||
947fa914 MF |
11021 | static void |
11022 | xg_promote_candidate_litpool (struct litpool_seg *lps, | |
11023 | struct litpool_frag *lp) | |
11024 | { | |
11025 | fragS *poolbeg; | |
11026 | fragS *poolend; | |
11027 | symbolS *lsym; | |
11028 | char label[10 + 2 * sizeof (fragS *)]; | |
11029 | ||
11030 | poolbeg = lp->fragP; | |
11031 | lp->priority = 1; | |
11032 | poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; | |
11033 | poolend = poolbeg->fr_next; | |
11034 | gas_assert (poolend->fr_type == rs_machine_dependent && | |
11035 | poolend->fr_subtype == RELAX_LITERAL_POOL_END); | |
11036 | /* Create a local symbol pointing to the | |
11037 | end of the pool. */ | |
11038 | sprintf (label, ".L0_LT_%p", poolbeg); | |
11039 | lsym = (symbolS *)local_symbol_make (label, lps->seg, | |
11040 | 0, poolend); | |
11041 | poolbeg->fr_symbol = lsym; | |
11042 | /* Rest is done in xtensa_relax_frag. */ | |
11043 | } | |
11044 | ||
7fa3d080 BW |
11045 | static void |
11046 | xtensa_move_literals (void) | |
e0001a05 NC |
11047 | { |
11048 | seg_list *segment; | |
11049 | frchainS *frchain_from, *frchain_to; | |
87975d2a | 11050 | fragS *search_frag, *next_frag, *literal_pool, *insert_after; |
e0001a05 NC |
11051 | fragS **frag_splice; |
11052 | emit_state state; | |
11053 | segT dest_seg; | |
11054 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 11055 | sym_list *lit; |
b46824bd | 11056 | struct litpool_seg *lps; |
4111950f MF |
11057 | const char *init_name = INIT_SECTION_NAME; |
11058 | const char *fini_name = FINI_SECTION_NAME; | |
11059 | int init_name_len = strlen(init_name); | |
11060 | int fini_name_len = strlen(fini_name); | |
e0001a05 | 11061 | |
a7877748 | 11062 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
11063 | |
11064 | if (use_literal_section) | |
11065 | return; | |
11066 | ||
b46824bd MF |
11067 | /* Assign addresses (rough estimates) to the potential literal pool locations |
11068 | and create new ones if the gaps are too large. */ | |
11069 | ||
11070 | for (lps = litpool_seg_list.next; lps; lps = lps->next) | |
11071 | { | |
11072 | frchainS *frchP = seg_info (lps->seg)->frchainP; | |
11073 | struct litpool_frag *lpf = lps->frag_list.next; | |
11074 | addressT addr = 0; | |
11075 | ||
11076 | for ( ; frchP; frchP = frchP->frch_next) | |
11077 | { | |
11078 | fragS *fragP; | |
11079 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
11080 | { | |
11081 | if (lpf && fragP == lpf->fragP) | |
11082 | { | |
11083 | gas_assert(fragP->fr_type == rs_machine_dependent && | |
11084 | (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || | |
11085 | fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); | |
11086 | /* Found a litpool location. */ | |
11087 | lpf->addr = addr; | |
11088 | lpf = lpf->next; | |
11089 | } | |
11090 | if (fragP->fr_type == rs_machine_dependent && | |
11091 | fragP->fr_subtype == RELAX_SLOTS) | |
11092 | { | |
11093 | int slot; | |
11094 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
11095 | { | |
11096 | if (fragP->tc_frag_data.literal_frags[slot]) | |
11097 | { | |
11098 | /* L32R; point its literal to the nearest litpool | |
11099 | preferring non-"candidate" positions to avoid | |
11100 | the jump-around. */ | |
11101 | fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; | |
11102 | struct litpool_frag *lp = lpf->prev; | |
11103 | if (!lp->fragP) | |
11104 | { | |
11105 | break; | |
11106 | } | |
11107 | while (lp->fragP->fr_subtype == | |
11108 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11109 | { | |
11110 | lp = lp->prev; | |
11111 | if (lp->fragP == NULL) | |
11112 | { | |
11113 | /* End of list; have to bite the bullet. | |
11114 | Take the nearest. */ | |
11115 | lp = lpf->prev; | |
11116 | break; | |
11117 | } | |
11118 | /* Does it (conservatively) reach? */ | |
11119 | if (addr - lp->addr <= 128 * 1024) | |
11120 | { | |
11121 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
11122 | { | |
11123 | /* Found a good one. */ | |
11124 | break; | |
11125 | } | |
11126 | else if (lp->prev->fragP && | |
11127 | addr - lp->prev->addr > 128 * 1024) | |
11128 | { | |
11129 | /* This is still a "candidate" but the next one | |
11130 | will be too far away, so revert to the nearest | |
11131 | one, convert it and add the jump around. */ | |
b46824bd | 11132 | lp = lpf->prev; |
947fa914 | 11133 | break; |
b46824bd MF |
11134 | } |
11135 | } | |
11136 | } | |
947fa914 MF |
11137 | |
11138 | /* Convert candidate and add the jump around. */ | |
11139 | if (lp->fragP->fr_subtype == | |
11140 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11141 | xg_promote_candidate_litpool (lps, lp); | |
11142 | ||
b46824bd MF |
11143 | if (! litfrag->tc_frag_data.literal_frag) |
11144 | { | |
11145 | /* Take earliest use of this literal to avoid | |
11146 | forward refs. */ | |
11147 | litfrag->tc_frag_data.literal_frag = lp->fragP; | |
11148 | } | |
11149 | } | |
11150 | } | |
11151 | } | |
11152 | addr += fragP->fr_fix; | |
11153 | if (fragP->fr_type == rs_fill) | |
11154 | addr += fragP->fr_offset; | |
11155 | } | |
11156 | } | |
11157 | } | |
11158 | ||
74869ac7 | 11159 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 11160 | { |
4111950f MF |
11161 | const char *seg_name = segment_name (segment->seg); |
11162 | ||
74869ac7 | 11163 | /* Keep the literals for .init and .fini in separate sections. */ |
4111950f MF |
11164 | if ((!memcmp (seg_name, init_name, init_name_len) && |
11165 | !strcmp (seg_name + init_name_len, ".literal")) || | |
11166 | (!memcmp (seg_name, fini_name, fini_name_len) && | |
11167 | !strcmp (seg_name + fini_name_len, ".literal"))) | |
74869ac7 BW |
11168 | continue; |
11169 | ||
e0001a05 NC |
11170 | frchain_from = seg_info (segment->seg)->frchainP; |
11171 | search_frag = frchain_from->frch_root; | |
11172 | literal_pool = NULL; | |
11173 | frchain_to = NULL; | |
11174 | frag_splice = &(frchain_from->frch_root); | |
11175 | ||
4de0562a | 11176 | while (search_frag && !search_frag->tc_frag_data.literal_frag) |
e0001a05 | 11177 | { |
9c2799c2 | 11178 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
11179 | || search_frag->fr_type == rs_align); |
11180 | search_frag = search_frag->fr_next; | |
11181 | } | |
11182 | ||
4de0562a MF |
11183 | if (!search_frag) |
11184 | { | |
11185 | search_frag = frchain_from->frch_root; | |
11186 | as_bad_where (search_frag->fr_file, search_frag->fr_line, | |
11187 | _("literal pool location required for text-section-literals; specify with .literal_position")); | |
11188 | continue; | |
11189 | } | |
11190 | ||
9c2799c2 | 11191 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
11192 | == RELAX_LITERAL_POOL_BEGIN); |
11193 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
11194 | ||
11195 | /* Make sure that all the frags in this series are closed, and | |
11196 | that there is at least one left over of zero-size. This | |
11197 | prevents us from making a segment with an frchain without any | |
11198 | frags in it. */ | |
11199 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11200 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11201 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); |
43cd72b9 | 11202 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11203 | |
43cd72b9 | 11204 | while (search_frag != frag_now) |
e0001a05 NC |
11205 | { |
11206 | next_frag = search_frag->fr_next; | |
e0001a05 NC |
11207 | if (search_frag->tc_frag_data.literal_frag) |
11208 | { | |
11209 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 11210 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 11211 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 11212 | gas_assert (frchain_to); |
e0001a05 | 11213 | } |
b46824bd MF |
11214 | |
11215 | if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) | |
11216 | { | |
11217 | /* Skip empty fill frags. */ | |
11218 | *frag_splice = next_frag; | |
11219 | search_frag = next_frag; | |
11220 | continue; | |
11221 | } | |
11222 | ||
11223 | if (search_frag->fr_type == rs_align) | |
11224 | { | |
11225 | /* Skip alignment frags, because the pool as a whole will be | |
11226 | aligned if used, and we don't want to force alignment if the | |
11227 | pool is unused. */ | |
11228 | *frag_splice = next_frag; | |
11229 | search_frag = next_frag; | |
11230 | continue; | |
11231 | } | |
11232 | ||
11233 | /* First, move the frag out of the literal section and | |
11234 | to the appropriate place. */ | |
11235 | ||
33eaf5de | 11236 | /* Insert an alignment frag at start of pool. */ |
b46824bd MF |
11237 | if (literal_pool->fr_next->fr_type == rs_machine_dependent && |
11238 | literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) | |
11239 | { | |
11240 | segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; | |
11241 | emit_state prev_state; | |
11242 | fragS *prev_frag; | |
11243 | fragS *align_frag; | |
11244 | xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); | |
11245 | prev_frag = frag_now; | |
11246 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
11247 | align_frag = frag_now; | |
11248 | frag_align (2, 0, 0); | |
11249 | /* Splice it into the right place. */ | |
11250 | prev_frag->fr_next = align_frag->fr_next; | |
11251 | align_frag->fr_next = literal_pool->fr_next; | |
11252 | literal_pool->fr_next = align_frag; | |
11253 | /* Insert after this one. */ | |
11254 | literal_pool->tc_frag_data.literal_frag = align_frag; | |
11255 | xtensa_restore_emit_state (&prev_state); | |
11256 | } | |
c48aaca0 | 11257 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 11258 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
b46824bd MF |
11259 | /* Skip align frag. */ |
11260 | if (insert_after->fr_next->fr_type == rs_align) | |
11261 | { | |
11262 | insert_after = insert_after->fr_next; | |
11263 | } | |
43cd72b9 | 11264 | |
e0001a05 NC |
11265 | *frag_splice = next_frag; |
11266 | search_frag->fr_next = insert_after->fr_next; | |
11267 | insert_after->fr_next = search_frag; | |
11268 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 11269 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
11270 | |
11271 | /* Now move any fixups associated with this frag to the | |
11272 | right section. */ | |
11273 | fix = frchain_from->fix_root; | |
11274 | fix_splice = &(frchain_from->fix_root); | |
11275 | while (fix) | |
11276 | { | |
11277 | next_fix = fix->fx_next; | |
11278 | if (fix->fx_frag == search_frag) | |
11279 | { | |
11280 | *fix_splice = next_fix; | |
11281 | fix->fx_next = frchain_to->fix_root; | |
11282 | frchain_to->fix_root = fix; | |
11283 | if (frchain_to->fix_tail == NULL) | |
11284 | frchain_to->fix_tail = fix; | |
11285 | } | |
11286 | else | |
11287 | fix_splice = &(fix->fx_next); | |
11288 | fix = next_fix; | |
11289 | } | |
11290 | search_frag = next_frag; | |
11291 | } | |
11292 | ||
11293 | if (frchain_from->fix_root != NULL) | |
11294 | { | |
11295 | frchain_from = seg_info (segment->seg)->frchainP; | |
11296 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
11297 | ||
9c2799c2 | 11298 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
11299 | } |
11300 | frchain_from->fix_tail = NULL; | |
11301 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
11302 | } |
11303 | ||
82e7541d BW |
11304 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
11305 | for (lit = literal_syms; lit; lit = lit->next) | |
11306 | { | |
11307 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
11308 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
11309 | if (dseg) | |
11310 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 11311 | } |
e0001a05 NC |
11312 | } |
11313 | ||
11314 | ||
a7877748 BW |
11315 | /* Walk over all the frags for segments in a list and mark them as |
11316 | containing literals. As clunky as this is, we can't rely on frag_var | |
11317 | and frag_variant to get called in all situations. */ | |
11318 | ||
11319 | static void | |
7fa3d080 | 11320 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
11321 | { |
11322 | frchainS *frchain_from; | |
11323 | fragS *search_frag; | |
11324 | ||
11325 | while (segment) | |
11326 | { | |
11327 | frchain_from = seg_info (segment->seg)->frchainP; | |
11328 | search_frag = frchain_from->frch_root; | |
c138bc38 | 11329 | while (search_frag) |
a7877748 BW |
11330 | { |
11331 | search_frag->tc_frag_data.is_literal = TRUE; | |
11332 | search_frag = search_frag->fr_next; | |
11333 | } | |
11334 | segment = segment->next; | |
11335 | } | |
11336 | } | |
11337 | ||
11338 | ||
e0001a05 | 11339 | static void |
7fa3d080 | 11340 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
11341 | { |
11342 | /* Move all of the sections in the section list to come | |
11343 | after "after" in the gnu segment list. */ | |
11344 | ||
11345 | head = head->next; | |
11346 | while (head) | |
11347 | { | |
11348 | segT literal_section = head->seg; | |
11349 | ||
11350 | /* Move the literal section after "after". */ | |
9c2799c2 | 11351 | gas_assert (literal_section); |
e0001a05 NC |
11352 | if (literal_section != after) |
11353 | { | |
69852798 AM |
11354 | bfd_section_list_remove (stdoutput, literal_section); |
11355 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
11356 | } |
11357 | ||
11358 | head = head->next; | |
11359 | } | |
11360 | } | |
11361 | ||
11362 | ||
11363 | /* Push all the literal segments to the end of the gnu list. */ | |
11364 | ||
7fa3d080 BW |
11365 | static void |
11366 | xtensa_reorder_segments (void) | |
e0001a05 NC |
11367 | { |
11368 | segT sec; | |
b08b5071 | 11369 | segT last_sec = 0; |
e0001a05 NC |
11370 | int old_count = 0; |
11371 | int new_count = 0; | |
11372 | ||
11373 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
11374 | { |
11375 | last_sec = sec; | |
11376 | old_count++; | |
11377 | } | |
e0001a05 NC |
11378 | |
11379 | /* Now that we have the last section, push all the literal | |
11380 | sections to the end. */ | |
e0001a05 | 11381 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
11382 | |
11383 | /* Now perform the final error check. */ | |
11384 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
11385 | new_count++; | |
9c2799c2 | 11386 | gas_assert (new_count == old_count); |
e0001a05 NC |
11387 | } |
11388 | ||
11389 | ||
e0001a05 NC |
11390 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
11391 | correct location. Return a emit_state which can be passed to | |
11392 | xtensa_restore_emit_state to return to current fragment. */ | |
11393 | ||
7fa3d080 BW |
11394 | static void |
11395 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
11396 | { |
11397 | if (directive_state[directive_absolute_literals]) | |
11398 | { | |
74869ac7 BW |
11399 | segT lit4_seg = cache_literal_section (TRUE); |
11400 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
11401 | } |
11402 | else | |
11403 | xtensa_switch_to_non_abs_literal_fragment (result); | |
11404 | ||
11405 | /* Do a 4-byte align here. */ | |
11406 | frag_align (2, 0, 0); | |
11407 | record_alignment (now_seg, 2); | |
11408 | } | |
11409 | ||
11410 | ||
7fa3d080 BW |
11411 | static void |
11412 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 11413 | { |
e0001a05 | 11414 | fragS *pool_location = get_literal_pool_location (now_seg); |
74869ac7 | 11415 | segT lit_seg; |
c138bc38 | 11416 | bfd_boolean is_init = |
e0001a05 | 11417 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 11418 | bfd_boolean is_fini = |
e0001a05 | 11419 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 11420 | |
43cd72b9 BW |
11421 | if (pool_location == NULL |
11422 | && !use_literal_section | |
e0001a05 NC |
11423 | && !is_init && ! is_fini) |
11424 | { | |
b46824bd MF |
11425 | if (!auto_litpools) |
11426 | { | |
11427 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); | |
11428 | } | |
947fa914 MF |
11429 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); |
11430 | pool_location = get_literal_pool_location (now_seg); | |
e0001a05 NC |
11431 | } |
11432 | ||
74869ac7 BW |
11433 | lit_seg = cache_literal_section (FALSE); |
11434 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 11435 | |
43cd72b9 BW |
11436 | if (!use_literal_section |
11437 | && !is_init && !is_fini | |
11438 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
11439 | { |
11440 | /* Close whatever frag is there. */ | |
11441 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11442 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
11443 | frag_now->tc_frag_data.literal_frag = pool_location; |
11444 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11445 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11446 | } |
e0001a05 NC |
11447 | } |
11448 | ||
11449 | ||
11450 | /* Call this function before emitting data into the literal section. | |
11451 | This is a helper function for xtensa_switch_to_literal_fragment. | |
11452 | This is similar to a .section new_now_seg subseg. */ | |
11453 | ||
7fa3d080 BW |
11454 | static void |
11455 | xtensa_switch_section_emit_state (emit_state *state, | |
11456 | segT new_now_seg, | |
11457 | subsegT new_now_subseg) | |
e0001a05 NC |
11458 | { |
11459 | state->name = now_seg->name; | |
11460 | state->now_seg = now_seg; | |
11461 | state->now_subseg = now_subseg; | |
11462 | state->generating_literals = generating_literals; | |
11463 | generating_literals++; | |
2b0210eb | 11464 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
11465 | } |
11466 | ||
11467 | ||
11468 | /* Use to restore the emitting into the normal place. */ | |
11469 | ||
7fa3d080 BW |
11470 | static void |
11471 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
11472 | { |
11473 | generating_literals = state->generating_literals; | |
2b0210eb | 11474 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
11475 | } |
11476 | ||
11477 | ||
74869ac7 | 11478 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 11479 | |
74869ac7 BW |
11480 | static bfd_boolean |
11481 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 11482 | { |
74869ac7 BW |
11483 | const char *gname = inf; |
11484 | const char *group_name = elf_group_name (sec); | |
3739860c | 11485 | |
74869ac7 BW |
11486 | return (group_name == gname |
11487 | || (group_name != NULL | |
11488 | && gname != NULL | |
11489 | && strcmp (group_name, gname) == 0)); | |
11490 | } | |
e0001a05 | 11491 | |
e0001a05 | 11492 | |
74869ac7 BW |
11493 | /* Get the literal section to be used for the current text section. |
11494 | The result may be cached in the default_lit_sections structure. */ | |
11495 | ||
11496 | static segT | |
11497 | cache_literal_section (bfd_boolean use_abs_literals) | |
11498 | { | |
11499 | const char *text_name, *group_name = 0; | |
b9bb4a93 TS |
11500 | const char *base_name, *suffix; |
11501 | char *name; | |
74869ac7 BW |
11502 | segT *pcached; |
11503 | segT seg, current_section; | |
11504 | int current_subsec; | |
11505 | bfd_boolean linkonce = FALSE; | |
11506 | ||
11507 | /* Save the current section/subsection. */ | |
11508 | current_section = now_seg; | |
11509 | current_subsec = now_subseg; | |
11510 | ||
11511 | /* Clear the cached values if they are no longer valid. */ | |
11512 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 11513 | { |
74869ac7 BW |
11514 | default_lit_sections.current_text_seg = now_seg; |
11515 | default_lit_sections.lit_seg = NULL; | |
11516 | default_lit_sections.lit4_seg = NULL; | |
11517 | } | |
11518 | ||
11519 | /* Check if the literal section is already cached. */ | |
11520 | if (use_abs_literals) | |
11521 | pcached = &default_lit_sections.lit4_seg; | |
11522 | else | |
11523 | pcached = &default_lit_sections.lit_seg; | |
11524 | ||
11525 | if (*pcached) | |
11526 | return *pcached; | |
3739860c | 11527 | |
74869ac7 BW |
11528 | text_name = default_lit_sections.lit_prefix; |
11529 | if (! text_name || ! *text_name) | |
11530 | { | |
11531 | text_name = segment_name (current_section); | |
11532 | group_name = elf_group_name (current_section); | |
11533 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
11534 | } | |
11535 | ||
11536 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
11537 | if (group_name) | |
11538 | { | |
4ec9d7d5 | 11539 | name = concat (base_name, ".", group_name, (char *) NULL); |
74869ac7 BW |
11540 | } |
11541 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
11542 | { | |
11543 | suffix = strchr (text_name + linkonce_len, '.'); | |
11544 | ||
4ec9d7d5 TS |
11545 | name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", |
11546 | (char *) NULL); | |
74869ac7 BW |
11547 | linkonce = TRUE; |
11548 | } | |
11549 | else | |
11550 | { | |
a89c407e SA |
11551 | /* If the section name begins or ends with ".text", then replace |
11552 | that portion instead of appending an additional suffix. */ | |
74869ac7 | 11553 | size_t len = strlen (text_name); |
a89c407e SA |
11554 | if (len >= 5 |
11555 | && (strcmp (text_name + len - 5, ".text") == 0 | |
11556 | || strncmp (text_name, ".text", 5) == 0)) | |
74869ac7 BW |
11557 | len -= 5; |
11558 | ||
add39d23 | 11559 | name = XNEWVEC (char, len + strlen (base_name) + 1); |
a89c407e SA |
11560 | if (strncmp (text_name, ".text", 5) == 0) |
11561 | { | |
11562 | strcpy (name, base_name); | |
11563 | strcat (name, text_name + 5); | |
11564 | } | |
11565 | else | |
11566 | { | |
11567 | strcpy (name, text_name); | |
11568 | strcpy (name + len, base_name); | |
11569 | } | |
b08b5071 | 11570 | } |
e0001a05 | 11571 | |
74869ac7 BW |
11572 | /* Canonicalize section names to allow renaming literal sections. |
11573 | The group name, if any, came from the current text section and | |
11574 | has already been canonicalized. */ | |
11575 | name = tc_canonicalize_symbol_name (name); | |
11576 | ||
11577 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
11578 | (void *) group_name); | |
11579 | if (! seg) | |
e0001a05 | 11580 | { |
74869ac7 BW |
11581 | flagword flags; |
11582 | ||
11583 | seg = subseg_force_new (name, 0); | |
11584 | ||
11585 | if (! use_abs_literals) | |
b08b5071 | 11586 | { |
74869ac7 | 11587 | /* Add the newly created literal segment to the list. */ |
325801bd | 11588 | seg_list *n = XNEW (seg_list); |
b08b5071 | 11589 | n->seg = seg; |
74869ac7 BW |
11590 | n->next = literal_head->next; |
11591 | literal_head->next = n; | |
b08b5071 | 11592 | } |
74869ac7 BW |
11593 | |
11594 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
11595 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
11596 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
11597 | ||
11598 | elf_group_name (seg) = group_name; | |
11599 | ||
11600 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 11601 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
11602 | } |
11603 | ||
74869ac7 | 11604 | *pcached = seg; |
b08b5071 | 11605 | subseg_set (current_section, current_subsec); |
74869ac7 | 11606 | return seg; |
e0001a05 NC |
11607 | } |
11608 | ||
43cd72b9 BW |
11609 | \f |
11610 | /* Property Tables Stuff. */ | |
11611 | ||
7fa3d080 BW |
11612 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
11613 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
11614 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
11615 | ||
11616 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
11617 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
11618 | ||
b08b5071 | 11619 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
11620 | static void xtensa_create_property_segments |
11621 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
11622 | static void xtensa_create_xproperty_segments | |
11623 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 11624 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
11625 | static bfd_boolean section_has_property (segT, frag_predicate); |
11626 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
11627 | static void add_xt_block_frags | |
542f8b94 | 11628 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
11629 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
11630 | static void xtensa_frag_flags_init (frag_flags *); | |
11631 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 11632 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 11633 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
11634 | |
11635 | /* Set up property tables after relaxation. */ | |
11636 | ||
11637 | void | |
11638 | xtensa_post_relax_hook (void) | |
11639 | { | |
11640 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
11641 | |
11642 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 11643 | xtensa_mark_frags_for_org (); |
6a7eedfe | 11644 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 11645 | |
b29757dc BW |
11646 | xtensa_create_property_segments (get_frag_is_literal, |
11647 | NULL, | |
11648 | XTENSA_LIT_SEC_NAME, | |
11649 | xt_literal_sec); | |
7fa3d080 BW |
11650 | xtensa_create_xproperty_segments (get_frag_property_flags, |
11651 | XTENSA_PROP_SEC_NAME, | |
11652 | xt_prop_sec); | |
11653 | ||
11654 | if (warn_unaligned_branch_targets) | |
11655 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
11656 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
11657 | } | |
11658 | ||
11659 | ||
43cd72b9 BW |
11660 | /* This function is only meaningful after xtensa_move_literals. */ |
11661 | ||
11662 | static bfd_boolean | |
7fa3d080 | 11663 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 11664 | { |
9c2799c2 | 11665 | gas_assert (fragP != NULL); |
43cd72b9 BW |
11666 | return fragP->tc_frag_data.is_literal; |
11667 | } | |
11668 | ||
11669 | ||
43cd72b9 | 11670 | static void |
7fa3d080 BW |
11671 | xtensa_create_property_segments (frag_predicate property_function, |
11672 | frag_predicate end_property_function, | |
11673 | const char *section_name_base, | |
11674 | xt_section_type sec_type) | |
43cd72b9 BW |
11675 | { |
11676 | segT *seclist; | |
11677 | ||
11678 | /* Walk over all of the current segments. | |
11679 | Walk over each fragment | |
11680 | For each non-empty fragment, | |
11681 | Build a property record (append where possible). */ | |
11682 | ||
11683 | for (seclist = &stdoutput->sections; | |
11684 | seclist && *seclist; | |
11685 | seclist = &(*seclist)->next) | |
11686 | { | |
11687 | segT sec = *seclist; | |
43cd72b9 | 11688 | |
532f93bd | 11689 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11690 | continue; |
11691 | ||
11692 | if (section_has_property (sec, property_function)) | |
11693 | { | |
542f8b94 BW |
11694 | segment_info_type *xt_seg_info; |
11695 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11696 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11697 | |
11698 | prop_sec->output_section = prop_sec; | |
11699 | subseg_set (prop_sec, 0); | |
11700 | xt_seg_info = seg_info (prop_sec); | |
11701 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11702 | ||
43cd72b9 | 11703 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11704 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
11705 | end_property_function); |
11706 | } | |
11707 | } | |
11708 | ||
11709 | /* Now we fill them out.... */ | |
11710 | ||
11711 | for (seclist = &stdoutput->sections; | |
11712 | seclist && *seclist; | |
11713 | seclist = &(*seclist)->next) | |
11714 | { | |
11715 | segment_info_type *seginfo; | |
11716 | xtensa_block_info *block; | |
11717 | segT sec = *seclist; | |
11718 | ||
11719 | seginfo = seg_info (sec); | |
11720 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11721 | ||
11722 | if (block) | |
11723 | { | |
11724 | xtensa_block_info *cur_block; | |
43cd72b9 | 11725 | int num_recs = 0; |
d77b99c9 | 11726 | bfd_size_type rec_size; |
43cd72b9 BW |
11727 | |
11728 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11729 | num_recs++; | |
11730 | ||
11731 | rec_size = num_recs * 8; | |
11732 | bfd_set_section_size (stdoutput, sec, rec_size); | |
11733 | ||
43cd72b9 BW |
11734 | if (num_recs) |
11735 | { | |
43cd72b9 | 11736 | char *frag_data; |
542f8b94 | 11737 | int i; |
43cd72b9 | 11738 | |
542f8b94 BW |
11739 | subseg_set (sec, 0); |
11740 | frag_data = frag_more (rec_size); | |
43cd72b9 | 11741 | cur_block = block; |
43cd72b9 BW |
11742 | for (i = 0; i < num_recs; i++) |
11743 | { | |
542f8b94 | 11744 | fixS *fix; |
e0001a05 | 11745 | |
43cd72b9 | 11746 | /* Write the fixup. */ |
9c2799c2 | 11747 | gas_assert (cur_block); |
542f8b94 BW |
11748 | fix = fix_new (frag_now, i * 8, 4, |
11749 | section_symbol (cur_block->sec), | |
11750 | cur_block->offset, | |
11751 | FALSE, BFD_RELOC_32); | |
11752 | fix->fx_file = "<internal>"; | |
43cd72b9 | 11753 | fix->fx_line = 0; |
e0001a05 | 11754 | |
43cd72b9 | 11755 | /* Write the length. */ |
542f8b94 | 11756 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
11757 | cur_block->size, 4); |
11758 | cur_block = cur_block->next; | |
11759 | } | |
542f8b94 BW |
11760 | frag_wane (frag_now); |
11761 | frag_new (0); | |
11762 | frag_wane (frag_now); | |
43cd72b9 BW |
11763 | } |
11764 | } | |
11765 | } | |
e0001a05 NC |
11766 | } |
11767 | ||
11768 | ||
7fa3d080 BW |
11769 | static void |
11770 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
11771 | const char *section_name_base, | |
11772 | xt_section_type sec_type) | |
e0001a05 NC |
11773 | { |
11774 | segT *seclist; | |
11775 | ||
11776 | /* Walk over all of the current segments. | |
43cd72b9 BW |
11777 | Walk over each fragment. |
11778 | For each fragment that has instructions, | |
11779 | build an instruction record (append where possible). */ | |
e0001a05 NC |
11780 | |
11781 | for (seclist = &stdoutput->sections; | |
11782 | seclist && *seclist; | |
11783 | seclist = &(*seclist)->next) | |
11784 | { | |
11785 | segT sec = *seclist; | |
43cd72b9 | 11786 | |
532f93bd | 11787 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11788 | continue; |
11789 | ||
11790 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 11791 | { |
542f8b94 BW |
11792 | segment_info_type *xt_seg_info; |
11793 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11794 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11795 | |
11796 | prop_sec->output_section = prop_sec; | |
11797 | subseg_set (prop_sec, 0); | |
11798 | xt_seg_info = seg_info (prop_sec); | |
11799 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11800 | ||
e0001a05 | 11801 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11802 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
11803 | } |
11804 | } | |
11805 | ||
11806 | /* Now we fill them out.... */ | |
11807 | ||
11808 | for (seclist = &stdoutput->sections; | |
11809 | seclist && *seclist; | |
11810 | seclist = &(*seclist)->next) | |
11811 | { | |
11812 | segment_info_type *seginfo; | |
11813 | xtensa_block_info *block; | |
11814 | segT sec = *seclist; | |
43cd72b9 | 11815 | |
e0001a05 NC |
11816 | seginfo = seg_info (sec); |
11817 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11818 | ||
11819 | if (block) | |
11820 | { | |
11821 | xtensa_block_info *cur_block; | |
43cd72b9 | 11822 | int num_recs = 0; |
d77b99c9 | 11823 | bfd_size_type rec_size; |
e0001a05 NC |
11824 | |
11825 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11826 | num_recs++; | |
11827 | ||
43cd72b9 | 11828 | rec_size = num_recs * (8 + 4); |
e0001a05 | 11829 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
11830 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
11831 | ||
e0001a05 NC |
11832 | if (num_recs) |
11833 | { | |
e0001a05 | 11834 | char *frag_data; |
542f8b94 | 11835 | int i; |
e0001a05 | 11836 | |
542f8b94 BW |
11837 | subseg_set (sec, 0); |
11838 | frag_data = frag_more (rec_size); | |
e0001a05 | 11839 | cur_block = block; |
e0001a05 NC |
11840 | for (i = 0; i < num_recs; i++) |
11841 | { | |
542f8b94 | 11842 | fixS *fix; |
e0001a05 NC |
11843 | |
11844 | /* Write the fixup. */ | |
9c2799c2 | 11845 | gas_assert (cur_block); |
542f8b94 BW |
11846 | fix = fix_new (frag_now, i * 12, 4, |
11847 | section_symbol (cur_block->sec), | |
11848 | cur_block->offset, | |
11849 | FALSE, BFD_RELOC_32); | |
11850 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
11851 | fix->fx_line = 0; |
11852 | ||
11853 | /* Write the length. */ | |
542f8b94 | 11854 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 11855 | cur_block->size, 4); |
542f8b94 | 11856 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 11857 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 11858 | sizeof (flagword)); |
e0001a05 NC |
11859 | cur_block = cur_block->next; |
11860 | } | |
542f8b94 BW |
11861 | frag_wane (frag_now); |
11862 | frag_new (0); | |
11863 | frag_wane (frag_now); | |
e0001a05 NC |
11864 | } |
11865 | } | |
11866 | } | |
11867 | } | |
11868 | ||
11869 | ||
532f93bd BW |
11870 | static bfd_boolean |
11871 | exclude_section_from_property_tables (segT sec) | |
11872 | { | |
11873 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
11874 | ||
11875 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
11876 | if ((flags & SEC_DEBUGGING) | |
11877 | || !(flags & SEC_ALLOC) | |
11878 | || (flags & SEC_MERGE)) | |
11879 | return TRUE; | |
11880 | ||
11881 | /* Linker cie and fde optimizations mess up property entries for | |
11882 | eh_frame sections, but there is nothing inside them relevant to | |
11883 | property tables anyway. */ | |
11884 | if (strcmp (sec->name, ".eh_frame") == 0) | |
11885 | return TRUE; | |
11886 | ||
11887 | return FALSE; | |
11888 | } | |
11889 | ||
11890 | ||
7fa3d080 BW |
11891 | static bfd_boolean |
11892 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
11893 | { |
11894 | segment_info_type *seginfo = seg_info (sec); | |
11895 | fragS *fragP; | |
11896 | ||
11897 | if (seginfo && seginfo->frchainP) | |
11898 | { | |
11899 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
11900 | { | |
11901 | if (property_function (fragP) | |
11902 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
11903 | return TRUE; | |
11904 | } | |
11905 | } | |
11906 | return FALSE; | |
11907 | } | |
11908 | ||
11909 | ||
7fa3d080 BW |
11910 | static bfd_boolean |
11911 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
11912 | { |
11913 | segment_info_type *seginfo = seg_info (sec); | |
11914 | fragS *fragP; | |
11915 | ||
11916 | if (seginfo && seginfo->frchainP) | |
11917 | { | |
11918 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
11919 | { | |
11920 | frag_flags prop_flags; | |
11921 | property_function (fragP, &prop_flags); | |
11922 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
11923 | return TRUE; | |
11924 | } | |
11925 | } | |
11926 | return FALSE; | |
11927 | } | |
11928 | ||
11929 | ||
e0001a05 NC |
11930 | /* Two types of block sections exist right now: literal and insns. */ |
11931 | ||
7fa3d080 BW |
11932 | static void |
11933 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
11934 | xtensa_block_info **xt_block, |
11935 | frag_predicate property_function, | |
11936 | frag_predicate end_property_function) | |
e0001a05 | 11937 | { |
e0001a05 NC |
11938 | fragS *fragP; |
11939 | ||
e0001a05 NC |
11940 | /* Build it if needed. */ |
11941 | while (*xt_block != NULL) | |
11942 | xt_block = &(*xt_block)->next; | |
11943 | /* We are either at NULL at the beginning or at the end. */ | |
11944 | ||
11945 | /* Walk through the frags. */ | |
542f8b94 | 11946 | if (seg_info (sec)->frchainP) |
e0001a05 | 11947 | { |
542f8b94 | 11948 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
11949 | fragP; |
11950 | fragP = fragP->fr_next) | |
11951 | { | |
11952 | if (property_function (fragP) | |
11953 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
11954 | { | |
11955 | if (*xt_block != NULL) | |
11956 | { | |
11957 | if ((*xt_block)->offset + (*xt_block)->size | |
11958 | == fragP->fr_address) | |
11959 | (*xt_block)->size += fragP->fr_fix; | |
11960 | else | |
11961 | xt_block = &((*xt_block)->next); | |
11962 | } | |
11963 | if (*xt_block == NULL) | |
11964 | { | |
325801bd | 11965 | xtensa_block_info *new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
11966 | new_block->sec = sec; |
11967 | new_block->offset = fragP->fr_address; | |
11968 | new_block->size = fragP->fr_fix; | |
11969 | new_block->next = NULL; | |
11970 | xtensa_frag_flags_init (&new_block->flags); | |
11971 | *xt_block = new_block; | |
11972 | } | |
11973 | if (end_property_function | |
11974 | && end_property_function (fragP)) | |
11975 | { | |
11976 | xt_block = &((*xt_block)->next); | |
11977 | } | |
11978 | } | |
11979 | } | |
11980 | } | |
11981 | } | |
11982 | ||
11983 | ||
11984 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
11985 | ||
7fa3d080 BW |
11986 | static bfd_boolean |
11987 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
11988 | { |
11989 | if (prop_flags->is_literal | |
11990 | || prop_flags->is_insn | |
11991 | || prop_flags->is_data | |
11992 | || prop_flags->is_unreachable) | |
11993 | return FALSE; | |
11994 | return TRUE; | |
11995 | } | |
11996 | ||
11997 | ||
7fa3d080 BW |
11998 | static void |
11999 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
12000 | { |
12001 | memset (prop_flags, 0, sizeof (frag_flags)); | |
12002 | } | |
12003 | ||
12004 | ||
7fa3d080 BW |
12005 | static void |
12006 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
12007 | { |
12008 | xtensa_frag_flags_init (prop_flags); | |
12009 | if (fragP->tc_frag_data.is_literal) | |
12010 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
12011 | if (fragP->tc_frag_data.is_specific_opcode |
12012 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
12013 | { |
12014 | prop_flags->is_no_transform = TRUE; | |
12015 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12016 | prop_flags->is_data = TRUE; | |
12017 | } | |
43cd72b9 | 12018 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 12019 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
12020 | else if (fragP->tc_frag_data.is_insn) |
12021 | { | |
12022 | prop_flags->is_insn = TRUE; | |
12023 | if (fragP->tc_frag_data.is_loop_target) | |
12024 | prop_flags->insn.is_loop_target = TRUE; | |
12025 | if (fragP->tc_frag_data.is_branch_target) | |
12026 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
12027 | if (fragP->tc_frag_data.is_no_density) |
12028 | prop_flags->insn.is_no_density = TRUE; | |
12029 | if (fragP->tc_frag_data.use_absolute_literals) | |
12030 | prop_flags->insn.is_abslit = TRUE; | |
12031 | } | |
12032 | if (fragP->tc_frag_data.is_align) | |
12033 | { | |
12034 | prop_flags->is_align = TRUE; | |
12035 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
12036 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12037 | prop_flags->is_data = TRUE; | |
12038 | } | |
12039 | } | |
12040 | ||
12041 | ||
2f1bf5c1 | 12042 | static flagword |
7fa3d080 | 12043 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 12044 | { |
2f1bf5c1 | 12045 | flagword num = 0; |
43cd72b9 BW |
12046 | if (prop_flags->is_literal) |
12047 | num |= XTENSA_PROP_LITERAL; | |
12048 | if (prop_flags->is_insn) | |
12049 | num |= XTENSA_PROP_INSN; | |
12050 | if (prop_flags->is_data) | |
12051 | num |= XTENSA_PROP_DATA; | |
12052 | if (prop_flags->is_unreachable) | |
12053 | num |= XTENSA_PROP_UNREACHABLE; | |
12054 | if (prop_flags->insn.is_loop_target) | |
12055 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
12056 | if (prop_flags->insn.is_branch_target) | |
12057 | { | |
12058 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
12059 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
12060 | } | |
12061 | ||
12062 | if (prop_flags->insn.is_no_density) | |
12063 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
12064 | if (prop_flags->is_no_transform) |
12065 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
12066 | if (prop_flags->insn.is_no_reorder) |
12067 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
12068 | if (prop_flags->insn.is_abslit) | |
12069 | num |= XTENSA_PROP_INSN_ABSLIT; | |
12070 | ||
12071 | if (prop_flags->is_align) | |
12072 | { | |
12073 | num |= XTENSA_PROP_ALIGN; | |
12074 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
12075 | } | |
12076 | ||
12077 | return num; | |
12078 | } | |
12079 | ||
12080 | ||
12081 | static bfd_boolean | |
7fa3d080 BW |
12082 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
12083 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
12084 | { |
12085 | /* Cannot combine with an end marker. */ | |
12086 | ||
12087 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
12088 | return FALSE; | |
12089 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
12090 | return FALSE; | |
12091 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
12092 | return FALSE; | |
12093 | ||
12094 | if (prop_flags_1->is_insn) | |
12095 | { | |
12096 | /* Properties of the beginning of the frag. */ | |
12097 | if (prop_flags_2->insn.is_loop_target) | |
12098 | return FALSE; | |
12099 | if (prop_flags_2->insn.is_branch_target) | |
12100 | return FALSE; | |
12101 | if (prop_flags_1->insn.is_no_density != | |
12102 | prop_flags_2->insn.is_no_density) | |
12103 | return FALSE; | |
99ded152 BW |
12104 | if (prop_flags_1->is_no_transform != |
12105 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
12106 | return FALSE; |
12107 | if (prop_flags_1->insn.is_no_reorder != | |
12108 | prop_flags_2->insn.is_no_reorder) | |
12109 | return FALSE; | |
12110 | if (prop_flags_1->insn.is_abslit != | |
12111 | prop_flags_2->insn.is_abslit) | |
12112 | return FALSE; | |
12113 | } | |
12114 | ||
12115 | if (prop_flags_1->is_align) | |
12116 | return FALSE; | |
12117 | ||
12118 | return TRUE; | |
12119 | } | |
12120 | ||
12121 | ||
7fa3d080 BW |
12122 | static bfd_vma |
12123 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
12124 | { |
12125 | bfd_vma end_addr; | |
d77b99c9 | 12126 | unsigned align_bits; |
43cd72b9 BW |
12127 | |
12128 | if (!xt_block->flags.is_align) | |
12129 | return xt_block->size; | |
12130 | ||
12131 | end_addr = xt_block->offset + xt_block->size; | |
12132 | align_bits = xt_block->flags.alignment; | |
12133 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
12134 | return end_addr - xt_block->offset; | |
12135 | } | |
12136 | ||
12137 | ||
12138 | static bfd_boolean | |
7fa3d080 BW |
12139 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
12140 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
12141 | { |
12142 | if (xt_block->sec != xt_block_2->sec) | |
12143 | return FALSE; | |
12144 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
12145 | != xt_block_2->offset) | |
12146 | return FALSE; | |
12147 | ||
12148 | if (xt_block_2->size == 0 | |
12149 | && (!xt_block_2->flags.is_unreachable | |
12150 | || xt_block->flags.is_unreachable)) | |
12151 | { | |
12152 | if (xt_block_2->flags.is_align | |
12153 | && xt_block->flags.is_align) | |
12154 | { | |
12155 | /* Nothing needed. */ | |
12156 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
12157 | return TRUE; | |
12158 | } | |
12159 | else | |
12160 | { | |
12161 | if (xt_block_2->flags.is_align) | |
12162 | { | |
12163 | /* Push alignment to previous entry. */ | |
12164 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
12165 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12166 | } | |
12167 | return TRUE; | |
12168 | } | |
12169 | } | |
12170 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
12171 | &xt_block_2->flags)) | |
12172 | return FALSE; | |
12173 | ||
12174 | xt_block->size += xt_block_2->size; | |
12175 | ||
12176 | if (xt_block_2->flags.is_align) | |
12177 | { | |
12178 | xt_block->flags.is_align = TRUE; | |
12179 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12180 | } | |
12181 | ||
12182 | return TRUE; | |
12183 | } | |
12184 | ||
12185 | ||
7fa3d080 BW |
12186 | static void |
12187 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
12188 | xtensa_block_info **xt_block, |
12189 | frag_flags_fn property_function) | |
43cd72b9 | 12190 | { |
43cd72b9 BW |
12191 | fragS *fragP; |
12192 | ||
43cd72b9 BW |
12193 | /* Build it if needed. */ |
12194 | while (*xt_block != NULL) | |
12195 | { | |
12196 | xt_block = &(*xt_block)->next; | |
12197 | } | |
12198 | /* We are either at NULL at the beginning or at the end. */ | |
12199 | ||
12200 | /* Walk through the frags. */ | |
542f8b94 | 12201 | if (seg_info (sec)->frchainP) |
43cd72b9 | 12202 | { |
542f8b94 | 12203 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
12204 | fragP = fragP->fr_next) |
12205 | { | |
12206 | xtensa_block_info tmp_block; | |
12207 | tmp_block.sec = sec; | |
12208 | tmp_block.offset = fragP->fr_address; | |
12209 | tmp_block.size = fragP->fr_fix; | |
12210 | tmp_block.next = NULL; | |
12211 | property_function (fragP, &tmp_block.flags); | |
12212 | ||
12213 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
12214 | /* && fragP->fr_fix != 0) */ | |
12215 | { | |
12216 | if ((*xt_block) == NULL | |
12217 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
12218 | { | |
12219 | xtensa_block_info *new_block; | |
12220 | if ((*xt_block) != NULL) | |
12221 | xt_block = &(*xt_block)->next; | |
325801bd | 12222 | new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12223 | *new_block = tmp_block; |
12224 | *xt_block = new_block; | |
12225 | } | |
12226 | } | |
12227 | } | |
12228 | } | |
12229 | } | |
12230 | ||
12231 | \f | |
12232 | /* op_placement_info_table */ | |
12233 | ||
12234 | /* op_placement_info makes it easier to determine which | |
12235 | ops can go in which slots. */ | |
12236 | ||
12237 | static void | |
7fa3d080 | 12238 | init_op_placement_info_table (void) |
43cd72b9 BW |
12239 | { |
12240 | xtensa_isa isa = xtensa_default_isa; | |
12241 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
12242 | xtensa_opcode opcode; | |
12243 | xtensa_format fmt; | |
12244 | int slot; | |
12245 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
12246 | ||
325801bd | 12247 | op_placement_table = XNEWVEC (op_placement_info, num_opcodes); |
9c2799c2 | 12248 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
12249 | |
12250 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
12251 | { | |
12252 | op_placement_info *opi = &op_placement_table[opcode]; | |
12253 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 12254 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 12255 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
12256 | opi->narrowest = XTENSA_UNDEFINED; |
12257 | opi->narrowest_size = 0x7F; | |
b2d179be | 12258 | opi->narrowest_slot = 0; |
43cd72b9 BW |
12259 | opi->formats = 0; |
12260 | opi->num_formats = 0; | |
12261 | opi->issuef = 0; | |
12262 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
12263 | { | |
12264 | opi->slots[fmt] = 0; | |
12265 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
12266 | { | |
12267 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
12268 | { | |
12269 | int fmt_length = xtensa_format_length (isa, fmt); | |
12270 | opi->issuef++; | |
12271 | set_bit (fmt, opi->formats); | |
12272 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
12273 | if (fmt_length < opi->narrowest_size |
12274 | || (fmt_length == opi->narrowest_size | |
12275 | && (xtensa_format_num_slots (isa, fmt) | |
12276 | < xtensa_format_num_slots (isa, | |
12277 | opi->narrowest)))) | |
43cd72b9 BW |
12278 | { |
12279 | opi->narrowest = fmt; | |
12280 | opi->narrowest_size = fmt_length; | |
b2d179be | 12281 | opi->narrowest_slot = slot; |
43cd72b9 | 12282 | } |
e0001a05 NC |
12283 | } |
12284 | } | |
43cd72b9 BW |
12285 | if (opi->formats) |
12286 | opi->num_formats++; | |
e0001a05 NC |
12287 | } |
12288 | } | |
43cd72b9 BW |
12289 | xtensa_insnbuf_free (isa, ibuf); |
12290 | } | |
12291 | ||
12292 | ||
12293 | bfd_boolean | |
7fa3d080 | 12294 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
12295 | { |
12296 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
12297 | } | |
12298 | ||
12299 | ||
12300 | /* If the opcode is available in a single slot format, return its size. */ | |
12301 | ||
7fa3d080 BW |
12302 | static int |
12303 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 12304 | { |
b2d179be | 12305 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
12306 | } |
12307 | ||
12308 | ||
7fa3d080 BW |
12309 | static xtensa_format |
12310 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 12311 | { |
b2d179be BW |
12312 | return op_placement_table[opcode].narrowest; |
12313 | } | |
12314 | ||
12315 | ||
12316 | static int | |
12317 | xg_get_single_slot (xtensa_opcode opcode) | |
12318 | { | |
12319 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
12320 | } |
12321 | ||
12322 | \f | |
12323 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
12324 | ||
12325 | void | |
7fa3d080 | 12326 | istack_init (IStack *stack) |
e0001a05 | 12327 | { |
e0001a05 NC |
12328 | stack->ninsn = 0; |
12329 | } | |
12330 | ||
12331 | ||
12332 | bfd_boolean | |
7fa3d080 | 12333 | istack_empty (IStack *stack) |
e0001a05 NC |
12334 | { |
12335 | return (stack->ninsn == 0); | |
12336 | } | |
12337 | ||
12338 | ||
12339 | bfd_boolean | |
7fa3d080 | 12340 | istack_full (IStack *stack) |
e0001a05 NC |
12341 | { |
12342 | return (stack->ninsn == MAX_ISTACK); | |
12343 | } | |
12344 | ||
12345 | ||
12346 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 12347 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
12348 | |
12349 | TInsn * | |
7fa3d080 | 12350 | istack_top (IStack *stack) |
e0001a05 NC |
12351 | { |
12352 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12353 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
12354 | return &stack->insn[rec]; |
12355 | } | |
12356 | ||
12357 | ||
12358 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 12359 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12360 | |
12361 | void | |
7fa3d080 | 12362 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
12363 | { |
12364 | int rec = stack->ninsn; | |
9c2799c2 | 12365 | gas_assert (!istack_full (stack)); |
43cd72b9 | 12366 | stack->insn[rec] = *insn; |
e0001a05 NC |
12367 | stack->ninsn++; |
12368 | } | |
12369 | ||
12370 | ||
12371 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 12372 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12373 | |
12374 | TInsn * | |
7fa3d080 | 12375 | istack_push_space (IStack *stack) |
e0001a05 NC |
12376 | { |
12377 | int rec = stack->ninsn; | |
12378 | TInsn *insn; | |
9c2799c2 | 12379 | gas_assert (!istack_full (stack)); |
e0001a05 | 12380 | insn = &stack->insn[rec]; |
60242db2 | 12381 | tinsn_init (insn); |
e0001a05 NC |
12382 | stack->ninsn++; |
12383 | return insn; | |
12384 | } | |
12385 | ||
12386 | ||
12387 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 12388 | istack_empty () returns TRUE. */ |
e0001a05 NC |
12389 | |
12390 | void | |
7fa3d080 | 12391 | istack_pop (IStack *stack) |
e0001a05 NC |
12392 | { |
12393 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12394 | gas_assert (!istack_empty (stack)); |
e0001a05 | 12395 | stack->ninsn--; |
60242db2 | 12396 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
12397 | } |
12398 | ||
12399 | \f | |
12400 | /* TInsn functions. */ | |
12401 | ||
12402 | void | |
7fa3d080 | 12403 | tinsn_init (TInsn *dst) |
e0001a05 NC |
12404 | { |
12405 | memset (dst, 0, sizeof (TInsn)); | |
12406 | } | |
12407 | ||
12408 | ||
43cd72b9 | 12409 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
12410 | |
12411 | static bfd_boolean | |
7fa3d080 | 12412 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
12413 | { |
12414 | int i; | |
12415 | int n = insn->ntok; | |
12416 | ||
9c2799c2 | 12417 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12418 | |
12419 | for (i = 0; i < n; ++i) | |
12420 | { | |
12421 | switch (insn->tok[i].X_op) | |
12422 | { | |
12423 | case O_register: | |
12424 | case O_constant: | |
12425 | break; | |
12426 | default: | |
12427 | return TRUE; | |
12428 | } | |
12429 | } | |
12430 | return FALSE; | |
12431 | } | |
12432 | ||
12433 | ||
12434 | bfd_boolean | |
7fa3d080 | 12435 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 12436 | { |
43cd72b9 | 12437 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
12438 | int i; |
12439 | int n = insn->ntok; | |
12440 | ||
9c2799c2 | 12441 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12442 | |
12443 | for (i = 0; i < n; ++i) | |
12444 | { | |
12445 | switch (insn->tok[i].X_op) | |
12446 | { | |
12447 | case O_register: | |
12448 | case O_constant: | |
12449 | break; | |
43cd72b9 BW |
12450 | case O_big: |
12451 | case O_illegal: | |
12452 | case O_absent: | |
12453 | /* Errors for these types are caught later. */ | |
12454 | break; | |
12455 | case O_hi16: | |
12456 | case O_lo16: | |
e0001a05 | 12457 | default: |
43cd72b9 BW |
12458 | /* Symbolic immediates are only allowed on the last immediate |
12459 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 12460 | support non-PC-relative relocations. */ |
43cd72b9 BW |
12461 | if (i != get_relaxable_immed (insn->opcode) |
12462 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
12463 | && insn->opcode != xtensa_const16_opcode)) | |
12464 | { | |
431ad2d0 | 12465 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
12466 | return TRUE; |
12467 | } | |
e0001a05 NC |
12468 | } |
12469 | } | |
12470 | return FALSE; | |
12471 | } | |
12472 | ||
12473 | ||
12474 | /* For assembly code with complex expressions (e.g. subtraction), | |
12475 | we have to build them in the literal pool so that | |
12476 | their results are calculated correctly after relaxation. | |
12477 | The relaxation only handles expressions that | |
12478 | boil down to SYMBOL + OFFSET. */ | |
12479 | ||
12480 | static bfd_boolean | |
7fa3d080 | 12481 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
12482 | { |
12483 | int i; | |
12484 | int n = insn->ntok; | |
9c2799c2 | 12485 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12486 | for (i = 0; i < n; ++i) |
12487 | { | |
12488 | switch (insn->tok[i].X_op) | |
12489 | { | |
12490 | case O_register: | |
12491 | case O_constant: | |
12492 | case O_symbol: | |
43cd72b9 BW |
12493 | case O_lo16: |
12494 | case O_hi16: | |
e0001a05 NC |
12495 | break; |
12496 | default: | |
12497 | return TRUE; | |
12498 | } | |
12499 | } | |
12500 | return FALSE; | |
12501 | } | |
12502 | ||
12503 | ||
b2d179be BW |
12504 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
12505 | Return TRUE if there is a symbol in the immediate field. This | |
12506 | function assumes that: | |
12507 | 1) The number of operands are correct. | |
12508 | 2) The insn_type is ITYPE_INSN. | |
12509 | 3) The opcode can be encoded in the specified format and slot. | |
12510 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
12511 | |
12512 | static bfd_boolean | |
7fa3d080 BW |
12513 | tinsn_to_slotbuf (xtensa_format fmt, |
12514 | int slot, | |
12515 | TInsn *tinsn, | |
12516 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
12517 | { |
12518 | xtensa_isa isa = xtensa_default_isa; | |
12519 | xtensa_opcode opcode = tinsn->opcode; | |
12520 | bfd_boolean has_fixup = FALSE; | |
12521 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12522 | int i; | |
12523 | ||
9c2799c2 | 12524 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
12525 | if (noperands != tinsn->ntok) |
12526 | as_fatal (_("operand number mismatch")); | |
12527 | ||
12528 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
12529 | { | |
12530 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
12531 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
12532 | return FALSE; | |
12533 | } | |
12534 | ||
12535 | for (i = 0; i < noperands; i++) | |
12536 | { | |
91d6fa6a | 12537 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
12538 | int rc; |
12539 | unsigned line; | |
3b4dbbbf | 12540 | const char *file_name; |
43cd72b9 BW |
12541 | uint32 opnd_value; |
12542 | ||
91d6fa6a | 12543 | switch (exp->X_op) |
43cd72b9 BW |
12544 | { |
12545 | case O_register: | |
12546 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12547 | break; | |
12548 | /* The register number has already been checked in | |
12549 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 12550 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
12551 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
12552 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
12553 | opnd_value); | |
12554 | if (rc != 0) | |
12555 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
12556 | break; | |
12557 | ||
12558 | case O_constant: | |
12559 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12560 | break; | |
3b4dbbbf | 12561 | file_name = as_where (&line); |
43cd72b9 BW |
12562 | /* It is a constant and we called this function |
12563 | then we have to try to fit it. */ | |
12564 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 12565 | exp->X_add_number, file_name, line); |
e0001a05 NC |
12566 | break; |
12567 | ||
e0001a05 NC |
12568 | default: |
12569 | has_fixup = TRUE; | |
12570 | break; | |
12571 | } | |
12572 | } | |
43cd72b9 | 12573 | |
e0001a05 NC |
12574 | return has_fixup; |
12575 | } | |
12576 | ||
12577 | ||
b2d179be BW |
12578 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
12579 | into a multi-slot instruction, fill the other slots with NOPs. | |
12580 | Return TRUE if there is a symbol in the immediate field. See also the | |
12581 | assumptions listed for tinsn_to_slotbuf. */ | |
12582 | ||
12583 | static bfd_boolean | |
12584 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
12585 | { | |
12586 | static xtensa_insnbuf slotbuf = 0; | |
12587 | static vliw_insn vinsn; | |
12588 | xtensa_isa isa = xtensa_default_isa; | |
12589 | bfd_boolean has_fixup = FALSE; | |
12590 | int i; | |
12591 | ||
12592 | if (!slotbuf) | |
12593 | { | |
12594 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12595 | xg_init_vinsn (&vinsn); | |
12596 | } | |
12597 | ||
12598 | xg_clear_vinsn (&vinsn); | |
12599 | ||
12600 | bundle_tinsn (tinsn, &vinsn); | |
12601 | ||
12602 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
12603 | ||
12604 | for (i = 0; i < vinsn.num_slots; i++) | |
12605 | { | |
12606 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
12607 | has_fixup |= | |
12608 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
12609 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
12610 | } | |
12611 | ||
12612 | return has_fixup; | |
12613 | } | |
12614 | ||
12615 | ||
43cd72b9 | 12616 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 12617 | |
7fa3d080 BW |
12618 | static bfd_boolean |
12619 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
12620 | { |
12621 | xtensa_isa isa = xtensa_default_isa; | |
12622 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
12623 | xtensa_regfile t1_regfile, t2_regfile; |
12624 | int t1_reg, t2_reg; | |
12625 | int t1_base_reg, t1_last_reg; | |
12626 | int t2_base_reg, t2_last_reg; | |
12627 | char t1_inout, t2_inout; | |
12628 | int i, j; | |
e0001a05 NC |
12629 | |
12630 | if (opcode == XTENSA_UNDEFINED) | |
12631 | { | |
12632 | as_bad (_("invalid opcode")); | |
12633 | return TRUE; | |
12634 | } | |
12635 | ||
43cd72b9 | 12636 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
12637 | { |
12638 | as_bad (_("too few operands")); | |
12639 | return TRUE; | |
12640 | } | |
12641 | ||
43cd72b9 | 12642 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
12643 | { |
12644 | as_bad (_("too many operands")); | |
12645 | return TRUE; | |
12646 | } | |
6dc6b655 BW |
12647 | |
12648 | /* Check registers. */ | |
12649 | for (j = 0; j < insn->ntok; j++) | |
12650 | { | |
12651 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
12652 | continue; | |
12653 | ||
12654 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
12655 | t2_base_reg = insn->tok[j].X_add_number; | |
12656 | t2_last_reg | |
12657 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
12658 | ||
12659 | for (i = 0; i < insn->ntok; i++) | |
12660 | { | |
12661 | if (i == j) | |
12662 | continue; | |
12663 | ||
12664 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
12665 | continue; | |
12666 | ||
12667 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
12668 | ||
12669 | if (t1_regfile != t2_regfile) | |
12670 | continue; | |
12671 | ||
12672 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
12673 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
12674 | ||
12675 | t1_base_reg = insn->tok[i].X_add_number; | |
12676 | t1_last_reg = (t1_base_reg | |
12677 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
12678 | ||
12679 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
12680 | { | |
12681 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
12682 | { | |
12683 | if (t1_reg != t2_reg) | |
12684 | continue; | |
12685 | ||
12686 | if (t1_inout != 'i' && t2_inout != 'i') | |
12687 | { | |
12688 | as_bad (_("multiple writes to the same register")); | |
12689 | return TRUE; | |
12690 | } | |
12691 | } | |
12692 | } | |
12693 | } | |
12694 | } | |
e0001a05 NC |
12695 | return FALSE; |
12696 | } | |
12697 | ||
12698 | ||
12699 | /* Load an instruction from its encoded form. */ | |
12700 | ||
12701 | static void | |
7fa3d080 | 12702 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 12703 | { |
43cd72b9 | 12704 | vliw_insn vinsn; |
e0001a05 | 12705 | |
43cd72b9 BW |
12706 | xg_init_vinsn (&vinsn); |
12707 | vinsn_from_chars (&vinsn, f); | |
12708 | ||
12709 | *tinsn = vinsn.slots[slot]; | |
12710 | xg_free_vinsn (&vinsn); | |
12711 | } | |
e0001a05 | 12712 | |
43cd72b9 BW |
12713 | |
12714 | static void | |
7fa3d080 BW |
12715 | tinsn_from_insnbuf (TInsn *tinsn, |
12716 | xtensa_insnbuf slotbuf, | |
12717 | xtensa_format fmt, | |
12718 | int slot) | |
43cd72b9 BW |
12719 | { |
12720 | int i; | |
12721 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
12722 | |
12723 | /* Find the immed. */ | |
43cd72b9 BW |
12724 | tinsn_init (tinsn); |
12725 | tinsn->insn_type = ITYPE_INSN; | |
12726 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
12727 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
12728 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
12729 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 12730 | { |
43cd72b9 BW |
12731 | set_expr_const (&tinsn->tok[i], |
12732 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
12733 | tinsn->opcode, i)); | |
e0001a05 NC |
12734 | } |
12735 | } | |
12736 | ||
12737 | ||
12738 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
12739 | ||
12740 | static void | |
7fa3d080 | 12741 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 12742 | { |
43cd72b9 | 12743 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
12744 | int opnum; |
12745 | ||
43cd72b9 | 12746 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
12747 | { |
12748 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 12749 | gas_assert (opnum >= 0); |
e7da6241 BW |
12750 | set_expr_symbol_offset (&tinsn->tok[opnum], |
12751 | fragP->tc_frag_data.slot_symbols[slot], | |
12752 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 12753 | } |
19e8f41a | 12754 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
12755 | } |
12756 | ||
12757 | ||
12758 | static int | |
7fa3d080 | 12759 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
12760 | { |
12761 | int i; | |
12762 | int text_bytes = 0; | |
12763 | ||
12764 | for (i = 0; i < istack->ninsn; i++) | |
12765 | { | |
43cd72b9 BW |
12766 | TInsn *tinsn = &istack->insn[i]; |
12767 | if (tinsn->insn_type == ITYPE_INSN) | |
12768 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
12769 | } |
12770 | return text_bytes; | |
12771 | } | |
12772 | ||
12773 | ||
12774 | static int | |
7fa3d080 | 12775 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
12776 | { |
12777 | int i; | |
12778 | int lit_bytes = 0; | |
12779 | ||
12780 | for (i = 0; i < istack->ninsn; i++) | |
12781 | { | |
43cd72b9 BW |
12782 | TInsn *tinsn = &istack->insn[i]; |
12783 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
12784 | lit_bytes += 4; |
12785 | } | |
12786 | return lit_bytes; | |
12787 | } | |
12788 | ||
43cd72b9 BW |
12789 | \f |
12790 | /* vliw_insn functions. */ | |
12791 | ||
7fa3d080 BW |
12792 | static void |
12793 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12794 | { |
12795 | int i; | |
12796 | xtensa_isa isa = xtensa_default_isa; | |
12797 | ||
12798 | xg_clear_vinsn (v); | |
12799 | ||
12800 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
12801 | if (v->insnbuf == NULL) | |
12802 | as_fatal (_("out of memory")); | |
12803 | ||
62af60e2 | 12804 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 12805 | { |
43cd72b9 BW |
12806 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
12807 | if (v->slotbuf[i] == NULL) | |
12808 | as_fatal (_("out of memory")); | |
12809 | } | |
12810 | } | |
12811 | ||
12812 | ||
7fa3d080 BW |
12813 | static void |
12814 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12815 | { |
12816 | int i; | |
65738a7d | 12817 | |
3739860c | 12818 | memset (v, 0, offsetof (vliw_insn, slots) |
62af60e2 | 12819 | + sizeof(TInsn) * config_max_slots); |
65738a7d | 12820 | |
43cd72b9 BW |
12821 | v->format = XTENSA_UNDEFINED; |
12822 | v->num_slots = 0; | |
12823 | v->inside_bundle = FALSE; | |
12824 | ||
12825 | if (xt_saved_debug_type != DEBUG_NONE) | |
12826 | debug_type = xt_saved_debug_type; | |
12827 | ||
62af60e2 | 12828 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 12829 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
12830 | } |
12831 | ||
12832 | ||
d8392fd9 SA |
12833 | static void |
12834 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
12835 | { | |
3739860c | 12836 | memcpy (dst, src, |
d8392fd9 SA |
12837 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); |
12838 | dst->insnbuf = src->insnbuf; | |
12839 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
12840 | } | |
12841 | ||
12842 | ||
7fa3d080 BW |
12843 | static bfd_boolean |
12844 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
12845 | { |
12846 | int i; | |
c138bc38 | 12847 | |
43cd72b9 BW |
12848 | for (i = 0; i < v->num_slots; i++) |
12849 | { | |
12850 | if (v->slots[i].is_specific_opcode) | |
12851 | return TRUE; | |
12852 | } | |
12853 | return FALSE; | |
12854 | } | |
12855 | ||
12856 | ||
7fa3d080 BW |
12857 | static void |
12858 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12859 | { |
12860 | int i; | |
12861 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 12862 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
12863 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
12864 | } | |
12865 | ||
12866 | ||
e7da6241 BW |
12867 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
12868 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
12869 | |
12870 | static bfd_boolean | |
7fa3d080 BW |
12871 | vinsn_to_insnbuf (vliw_insn *vinsn, |
12872 | char *frag_offset, | |
12873 | fragS *fragP, | |
12874 | bfd_boolean record_fixup) | |
43cd72b9 BW |
12875 | { |
12876 | xtensa_isa isa = xtensa_default_isa; | |
12877 | xtensa_format fmt = vinsn->format; | |
12878 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
12879 | int slot; | |
12880 | bfd_boolean has_fixup = FALSE; | |
12881 | ||
12882 | xtensa_format_encode (isa, fmt, insnbuf); | |
12883 | ||
12884 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
12885 | { | |
12886 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 12887 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
12888 | bfd_boolean tinsn_has_fixup = |
12889 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
12890 | vinsn->slotbuf[slot]); | |
12891 | ||
12892 | xtensa_format_set_slot (isa, fmt, slot, | |
12893 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 12894 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
12895 | { |
12896 | if (vinsn->num_slots != 1) | |
12897 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
12898 | else if (record_fixup) | |
12899 | /* Instructions that generate TLS relocations should always be | |
12900 | relaxed in the front-end. If "record_fixup" is set, then this | |
12901 | function is being called during back-end relaxation, so flag | |
12902 | the unexpected behavior as an error. */ | |
12903 | as_bad (_("unexpected TLS relocation")); | |
12904 | else | |
12905 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
12906 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
12907 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
12908 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 12909 | } |
e7da6241 | 12910 | if (tinsn_has_fixup) |
43cd72b9 BW |
12911 | { |
12912 | int i; | |
12913 | xtensa_opcode opcode = tinsn->opcode; | |
12914 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12915 | has_fixup = TRUE; | |
12916 | ||
12917 | for (i = 0; i < noperands; i++) | |
12918 | { | |
91d6fa6a NC |
12919 | expressionS* exp = &tinsn->tok[i]; |
12920 | switch (exp->X_op) | |
43cd72b9 BW |
12921 | { |
12922 | case O_symbol: | |
12923 | case O_lo16: | |
12924 | case O_hi16: | |
12925 | if (get_relaxable_immed (opcode) == i) | |
12926 | { | |
e7da6241 BW |
12927 | /* Add a fix record for the instruction, except if this |
12928 | function is being called prior to relaxation, i.e., | |
12929 | if record_fixup is false, and the instruction might | |
12930 | be relaxed later. */ | |
12931 | if (record_fixup | |
12932 | || tinsn->is_specific_opcode | |
12933 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 12934 | { |
91d6fa6a | 12935 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 12936 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
12937 | } |
12938 | else | |
12939 | { | |
91d6fa6a | 12940 | if (exp->X_op != O_symbol) |
e7da6241 | 12941 | as_bad (_("invalid operand")); |
91d6fa6a NC |
12942 | tinsn->symbol = exp->X_add_symbol; |
12943 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
12944 | } |
12945 | } | |
12946 | else | |
e7da6241 | 12947 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
12948 | break; |
12949 | ||
12950 | case O_constant: | |
12951 | case O_register: | |
12952 | break; | |
12953 | ||
43cd72b9 | 12954 | default: |
e7da6241 | 12955 | as_bad (_("expression too complex")); |
43cd72b9 BW |
12956 | break; |
12957 | } | |
12958 | } | |
12959 | } | |
12960 | } | |
12961 | ||
12962 | return has_fixup; | |
12963 | } | |
12964 | ||
12965 | ||
12966 | static void | |
7fa3d080 | 12967 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
12968 | { |
12969 | static xtensa_insnbuf insnbuf = NULL; | |
12970 | static xtensa_insnbuf slotbuf = NULL; | |
12971 | int i; | |
12972 | xtensa_format fmt; | |
12973 | xtensa_isa isa = xtensa_default_isa; | |
12974 | ||
12975 | if (!insnbuf) | |
12976 | { | |
12977 | insnbuf = xtensa_insnbuf_alloc (isa); | |
12978 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12979 | } | |
12980 | ||
d77b99c9 | 12981 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
12982 | fmt = xtensa_format_decode (isa, insnbuf); |
12983 | if (fmt == XTENSA_UNDEFINED) | |
12984 | as_fatal (_("cannot decode instruction format")); | |
12985 | vinsn->format = fmt; | |
12986 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
12987 | ||
12988 | for (i = 0; i < vinsn->num_slots; i++) | |
12989 | { | |
12990 | TInsn *tinsn = &vinsn->slots[i]; | |
12991 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
12992 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
12993 | } | |
12994 | } | |
12995 | ||
e0001a05 NC |
12996 | \f |
12997 | /* Expression utilities. */ | |
12998 | ||
43cd72b9 | 12999 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
13000 | |
13001 | bfd_boolean | |
7fa3d080 | 13002 | expr_is_const (const expressionS *s) |
e0001a05 NC |
13003 | { |
13004 | return (s->X_op == O_constant); | |
13005 | } | |
13006 | ||
13007 | ||
13008 | /* Get the expression constant. | |
43cd72b9 | 13009 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
13010 | |
13011 | offsetT | |
7fa3d080 | 13012 | get_expr_const (const expressionS *s) |
e0001a05 | 13013 | { |
9c2799c2 | 13014 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
13015 | return s->X_add_number; |
13016 | } | |
13017 | ||
13018 | ||
13019 | /* Set the expression to a constant value. */ | |
13020 | ||
13021 | void | |
7fa3d080 | 13022 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
13023 | { |
13024 | s->X_op = O_constant; | |
13025 | s->X_add_number = val; | |
13026 | s->X_add_symbol = NULL; | |
13027 | s->X_op_symbol = NULL; | |
13028 | } | |
13029 | ||
13030 | ||
43cd72b9 | 13031 | bfd_boolean |
7fa3d080 | 13032 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
13033 | { |
13034 | return (s->X_op == O_register); | |
13035 | } | |
13036 | ||
13037 | ||
13038 | /* Get the expression constant. | |
13039 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
13040 | ||
13041 | offsetT | |
7fa3d080 | 13042 | get_expr_register (const expressionS *s) |
43cd72b9 | 13043 | { |
9c2799c2 | 13044 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
13045 | return s->X_add_number; |
13046 | } | |
13047 | ||
13048 | ||
e0001a05 NC |
13049 | /* Set the expression to a symbol + constant offset. */ |
13050 | ||
13051 | void | |
7fa3d080 | 13052 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
13053 | { |
13054 | s->X_op = O_symbol; | |
13055 | s->X_add_symbol = sym; | |
13056 | s->X_op_symbol = NULL; /* unused */ | |
13057 | s->X_add_number = offset; | |
13058 | } | |
13059 | ||
13060 | ||
43cd72b9 BW |
13061 | /* Return TRUE if the two expressions are equal. */ |
13062 | ||
e0001a05 | 13063 | bfd_boolean |
7fa3d080 | 13064 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
13065 | { |
13066 | if (s1->X_op != s2->X_op) | |
13067 | return FALSE; | |
13068 | if (s1->X_add_symbol != s2->X_add_symbol) | |
13069 | return FALSE; | |
13070 | if (s1->X_op_symbol != s2->X_op_symbol) | |
13071 | return FALSE; | |
13072 | if (s1->X_add_number != s2->X_add_number) | |
13073 | return FALSE; | |
13074 | return TRUE; | |
13075 | } | |
13076 | ||
13077 | ||
13078 | static void | |
7fa3d080 | 13079 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
13080 | { |
13081 | memcpy (dst, src, sizeof (expressionS)); | |
13082 | } | |
13083 | ||
13084 | \f | |
9456465c | 13085 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
13086 | |
13087 | struct rename_section_struct | |
13088 | { | |
e4a0c708 | 13089 | const char *old_name; |
e0001a05 NC |
13090 | char *new_name; |
13091 | struct rename_section_struct *next; | |
13092 | }; | |
13093 | ||
13094 | static struct rename_section_struct *section_rename; | |
13095 | ||
13096 | ||
9456465c BW |
13097 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
13098 | entries to the section_rename list. Note: Specifying multiple | |
13099 | renamings separated by colons is not documented and is retained only | |
13100 | for backward compatibility. */ | |
e0001a05 | 13101 | |
7fa3d080 BW |
13102 | static void |
13103 | build_section_rename (const char *arg) | |
e0001a05 | 13104 | { |
9456465c | 13105 | struct rename_section_struct *r; |
e0001a05 NC |
13106 | char *this_arg = NULL; |
13107 | char *next_arg = NULL; | |
13108 | ||
9456465c | 13109 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 13110 | { |
9456465c BW |
13111 | char *old_name, *new_name; |
13112 | ||
e0001a05 NC |
13113 | if (this_arg) |
13114 | { | |
13115 | next_arg = strchr (this_arg, ':'); | |
13116 | if (next_arg) | |
13117 | { | |
13118 | *next_arg = '\0'; | |
13119 | next_arg++; | |
13120 | } | |
13121 | } | |
e0001a05 | 13122 | |
9456465c BW |
13123 | old_name = this_arg; |
13124 | new_name = strchr (this_arg, '='); | |
e0001a05 | 13125 | |
9456465c BW |
13126 | if (*old_name == '\0') |
13127 | { | |
13128 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
13129 | continue; | |
13130 | } | |
13131 | if (!new_name || new_name[1] == '\0') | |
13132 | { | |
13133 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
13134 | old_name); | |
13135 | continue; | |
13136 | } | |
13137 | *new_name = '\0'; | |
13138 | new_name++; | |
e0001a05 | 13139 | |
9456465c BW |
13140 | /* Check for invalid section renaming. */ |
13141 | for (r = section_rename; r != NULL; r = r->next) | |
13142 | { | |
13143 | if (strcmp (r->old_name, old_name) == 0) | |
13144 | as_bad (_("section %s renamed multiple times"), old_name); | |
13145 | if (strcmp (r->new_name, new_name) == 0) | |
13146 | as_bad (_("multiple sections remapped to output section %s"), | |
13147 | new_name); | |
13148 | } | |
e0001a05 | 13149 | |
9456465c | 13150 | /* Now add it. */ |
325801bd | 13151 | r = XNEW (struct rename_section_struct); |
9456465c BW |
13152 | r->old_name = xstrdup (old_name); |
13153 | r->new_name = xstrdup (new_name); | |
13154 | r->next = section_rename; | |
13155 | section_rename = r; | |
e0001a05 | 13156 | } |
e0001a05 NC |
13157 | } |
13158 | ||
13159 | ||
9456465c | 13160 | char * |
e4a0c708 | 13161 | xtensa_section_rename (const char *name) |
e0001a05 NC |
13162 | { |
13163 | struct rename_section_struct *r = section_rename; | |
13164 | ||
13165 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
13166 | { |
13167 | if (strcmp (r->old_name, name) == 0) | |
13168 | return r->new_name; | |
13169 | } | |
e0001a05 | 13170 | |
e4a0c708 | 13171 | return (char *) name; |
e0001a05 | 13172 | } |