]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gas/testsuite/gas/aarch64/bfloat16.s
Fix an assertion failure in the AArch64 assembler triggered by incorrect instruction...
[thirdparty/binutils-gdb.git] / gas / testsuite / gas / aarch64 / bfloat16.s
CommitLineData
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MM
1/* The instructions with non-zero register numbers are there to ensure we have
2 the correct argument positioning (i.e. check that the first argument is at
3 the end of the word etc).
4 The instructions with all-zero register numbers are to ensure the previous
5 encoding didn't just "happen" to fit -- so that if we change the registers
6 that changes the correct part of the word.
7 Each of the numbered patterns begin and end with a 1, so we can replace
8 them with all-zeros and see the entire range has changed. */
9
10// SVE
11bfdot z17.s, z21.h, z27.h
12bfdot z0.s, z0.h, z0.h
13
14bfdot z17.s, z21.h, z5.h[3]
15bfdot z0.s, z0.h, z0.h[3]
16bfdot z0.s, z0.h, z0.h[0]
17
18bfmmla z17.s, z21.h, z27.h
19bfmmla z0.s, z0.h, z0.h
20
21bfcvt z17.h, p5/m, z21.s
22bfcvt z0.h, p0/m, z0.s
23bfcvtnt z17.h, p5/m, z21.s
24bfcvtnt z0.h, p0/m, z0.s
25
26bfmlalt z17.s, z21.h, z27.h
27bfmlalt z0.s, z0.h, z0.h
28bfmlalb z17.s, z21.h, z27.h
29bfmlalb z0.s, z0.h, z0.h
30
31bfmlalt z17.s, z21.h, z5.h[0]
32bfmlalt z0.s, z0.h, z0.h[7]
33bfmlalb z17.s, z21.h, z5.h[0]
34bfmlalb z0.s, z0.h, z0.h[7]
35
36// SIMD
37bfdot v17.2s, v21.4h, v27.4h
38bfdot v0.2s, v0.4h, v0.4h
39bfdot v17.4s, v21.8h, v27.8h
40bfdot v0.4s, v0.8h, v0.8h
41
42bfdot v17.2s, v21.4h, v27.2h[3]
43bfdot v0.2s, v0.4h, v0.2h[3]
44bfdot v17.4s, v21.8h, v27.2h[3]
45bfdot v0.4s, v0.8h, v0.2h[3]
46bfdot v17.2s, v21.4h, v27.2h[0]
47bfdot v0.2s, v0.4h, v0.2h[0]
48bfdot v17.4s, v21.8h, v27.2h[0]
49bfdot v0.4s, v0.8h, v0.2h[0]
50
51bfmmla v17.4s, v21.8h, v27.8h
52bfmmla v0.4s, v0.8h, v0.8h
53
54bfmlalb v17.4s, v21.8h, v27.8h
55bfmlalb v0.4s, v0.8h, v0.8h
56bfmlalt v17.4s, v21.8h, v27.8h
57bfmlalt v0.4s, v0.8h, v0.8h
58
59bfmlalb v17.4s, v21.8h, v15.h[0]
60bfmlalb v0.4s, v0.8h, v0.h[7]
61bfmlalt v17.4s, v21.8h, v15.h[0]
62bfmlalt v0.4s, v0.8h, v0.h[7]
63
64bfcvtn v17.4h, v21.4s
65bfcvtn v0.4h, v0.4s
66bfcvtn2 v17.8h, v21.4s
67bfcvtn2 v0.8h, v0.4s
68
69bfcvt h17, s21
70bfcvt h0, s0