[thirdparty/binutils-gdb.git] / gas / testsuite / gas / aarch64 / neon-vfp-reglist-post.s


	# ARMv8 tests to test neon register 
	# lists syntax.
	.text
	.arch armv8-a

	# Post-index multiple elements

	.macro ldst1_reg_list_post_imm_64 inst type
	\inst\()1 {v0.\type}, [x0], #8
	\inst\()1 {v0.\type, v1.\type}, [x0], #16
	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
	.endm
	
	.irp instr ld,st
	.irp bits_64 8b, 4h, 2s, 1d
	ldst1_reg_list_post_imm_64 \instr \bits_64
	.endr
	.endr

	.macro ldst1_reg_list_post_imm_128 inst type
	\inst\()1 {v0.\type}, [x0], #16
	\inst\()1 {v0.\type, v1.\type}, [x0], #32
	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
	.endm

	.irp instr ld,st
	.irp bits_128 16b, 8h, 4s, 2d
	ldst1_reg_list_post_imm_128 \instr \bits_128
	.endr
	.endr

	.macro ldst1_reg_list_post_reg inst type postreg
	\inst\()1 {v0.\type}, [x0], \postreg
	\inst\()1 {v0.\type, v1.\type}, [x0], \postreg
	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
	.endm

	.irp instr ld,st
	.irp bits 8b, 4h, 2s, 1d, 16b, 8h, 4s, 2d
	ldst1_reg_list_post_reg \instr \bits x7
	.endr
	.endr

	.macro ldst2_reg_list_post_imm_reg_64 inst type postreg
	\inst\()2 {v0.\type, v1.\type}, [x0], #16
	.ifnb \postreg
	\inst\()2 {v0.\type, v1.\type}, [x0], \postreg
	.endif
	.endm

	.macro ldst2_reg_list_post_imm_reg_128 inst type postreg
	\inst\()2 {v0.\type, v1.\type}, [x0], #32
	.ifnb \postreg
	\inst\()2 {v0.\type, v1.\type}, [x0], \postreg
	.endif
	.endm

	.irp instr ld,st
	.irp bits_64 8b, 4h, 2s
	ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
	.endr
	.endr

	.irp instr ld,st
	.irp bits_128 16b, 8h, 4s, 2d
	ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
	.endr
	.endr

	.macro ldst34_reg_list_post_imm_reg_64 inst type postreg
	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #24
	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
	.endm

	.macro ldst34_reg_list_post_imm_reg_128 inst type postreg
	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #48
	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
	.endm

	.irp instr ld,st
	.irp bits_64 8b, 4h, 2s
	ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
	.endr
	.endr

	.irp instr ld,st
	.irp bits_128 16b, 8h, 4s, 2d
	ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
	.endr
	.endr


	# Post Index Vector-element form with replicate (Immediate offset)

	# Consecutive registers in reg list

	.macro ldstn_index_rep_B_imm inst index type rep
	\inst\()1\rep {v0.\type}\index, [x0], #1
	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #2
	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #3
	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #4
	.endm

	# Vector element with index

	.irp instr, ld, st
	ldstn_index_rep_B_imm  \instr index="[1]" type=b rep=""
	.ifnc \instr, st
	.irp types 8b, 16b
	ldstn_index_rep_B_imm  \instr index="" type=\types rep="r"
	.endr
	.endif
	.endr

	.macro ldstn_index_rep_H_imm inst index type rep
	\inst\()1\rep {v0.\type}\index, [x0], #2
	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #4
	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #6
	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #8
	.endm

	.irp instr, ld, st
	ldstn_index_rep_H_imm  \instr index="[1]" type=h rep=""
	.ifnc \instr, st
	.irp types 4h, 8h
	ldstn_index_rep_H_imm  \instr index="" type=\types rep="r"
	.endr
	.endif
	.endr

	.macro ldstn_index_rep_S_imm inst index type rep
	\inst\()1\rep {v0.\type}\index, [x0], #4
	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #8
	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #12
	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #16
	.endm

	.irp instr, ld, st
	ldstn_index_rep_S_imm  \instr index="[1]" type=s rep=""
	.ifnc \instr, st
	.irp types 2s, 4s
	ldstn_index_rep_S_imm  \instr index="" type=\types rep="r"
	.endr
	.endif
	.endr

	.macro ldstn_index_rep_D_imm inst index type rep
	\inst\()1\rep {v0.\type}\index, [x0], #8
	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #16
	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #24
	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #32
	.endm

	.irp instr, ld, st
	ldstn_index_rep_D_imm  \instr index="[1]" type=d rep=""
	.ifnc \instr, st
	.irp types 1d, 2d
	ldstn_index_rep_D_imm  \instr index="" type=\types rep="r"
	.endr
	.endif
	.endr

	# Post Index Vector-element form with replicate (Register offset)
	# This could have been factored into Post-index multiple 
	# element macros but this would make this already-looking-complex
	# testcase look more complex!

	# Consecutive registers in reg list

	.macro ldstn_index_rep_reg inst index type rep postreg
	\inst\()1\rep {v0.\type}\index, [x0], \postreg
	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], \postreg
	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], \postreg
	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], \postreg
	.endm

	.irp instr, ld, st
	.irp itypes b,h,s,d
	ldstn_index_rep_reg  \instr index="[1]" type=\itypes rep="" postreg=x7
	.endr
	.ifnc \instr, st
	.irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
	ldstn_index_rep_reg  \instr index="" type=\types rep="r" postreg=x7
	.endr
	.endif
	.endr

	# ### End of test
Commit	Line	Data
a06ea964 NC	1
	2	# ARMv8 tests to test neon register
	3	# lists syntax.
	4	.text
5a1ad39d	5	.arch armv8-a
a06ea964 NC	6
	7	# Post-index multiple elements
	8
	9	.macro ldst1_reg_list_post_imm_64 inst type
	10	\inst\()1 {v0.\type}, [x0], #8
	11	\inst\()1 {v0.\type, v1.\type}, [x0], #16
	12	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
	13	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
	14	.endm
	15
	16	.irp instr ld,st
	17	.irp bits_64 8b, 4h, 2s, 1d
	18	ldst1_reg_list_post_imm_64 \instr \bits_64
	19	.endr
	20	.endr
	21
	22	.macro ldst1_reg_list_post_imm_128 inst type
	23	\inst\()1 {v0.\type}, [x0], #16
	24	\inst\()1 {v0.\type, v1.\type}, [x0], #32
	25	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
	26	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
	27	.endm
	28
	29	.irp instr ld,st
	30	.irp bits_128 16b, 8h, 4s, 2d
	31	ldst1_reg_list_post_imm_128 \instr \bits_128
	32	.endr
	33	.endr
	34
	35	.macro ldst1_reg_list_post_reg inst type postreg
	36	\inst\()1 {v0.\type}, [x0], \postreg
	37	\inst\()1 {v0.\type, v1.\type}, [x0], \postreg
	38	\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
	39	\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
	40	.endm
	41
	42	.irp instr ld,st
	43	.irp bits 8b, 4h, 2s, 1d, 16b, 8h, 4s, 2d
	44	ldst1_reg_list_post_reg \instr \bits x7
	45	.endr
	46	.endr
	47
	48	.macro ldst2_reg_list_post_imm_reg_64 inst type postreg
	49	\inst\()2 {v0.\type, v1.\type}, [x0], #16
	50	.ifnb \postreg
	51	\inst\()2 {v0.\type, v1.\type}, [x0], \postreg
	52	.endif
	53	.endm
	54
	55	.macro ldst2_reg_list_post_imm_reg_128 inst type postreg
	56	\inst\()2 {v0.\type, v1.\type}, [x0], #32
	57	.ifnb \postreg
	58	\inst\()2 {v0.\type, v1.\type}, [x0], \postreg
	59	.endif
	60	.endm
	61
	62	.irp instr ld,st
	63	.irp bits_64 8b, 4h, 2s
	64	ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
	65	.endr
	66	.endr
	67
	68	.irp instr ld,st
	69	.irp bits_128 16b, 8h, 4s, 2d
70	ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
71	.endr
72	.endr
73
74	.macro ldst34_reg_list_post_imm_reg_64 inst type postreg
75	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #24
76	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
77	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
78	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
79	.endm
80
81	.macro ldst34_reg_list_post_imm_reg_128 inst type postreg
82	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], #48
83	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
84	\inst\()3 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
85	\inst\()4 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
86	.endm
87
88	.irp instr ld,st
89	.irp bits_64 8b, 4h, 2s
90	ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
91	.endr
92	.endr
93
94	.irp instr ld,st
95	.irp bits_128 16b, 8h, 4s, 2d
96	ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
97	.endr
98	.endr
99
100
101	# Post Index Vector-element form with replicate (Immediate offset)
102
103	# Consecutive registers in reg list
104
105	.macro ldstn_index_rep_B_imm inst index type rep
106	\inst\()1\rep {v0.\type}\index, [x0], #1
107	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #2
108	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #3
109	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #4
110	.endm
111
112	# Vector element with index
113
114	.irp instr, ld, st
115	ldstn_index_rep_B_imm \instr index="[1]" type=b rep=""
116	.ifnc \instr, st
117	.irp types 8b, 16b
118	ldstn_index_rep_B_imm \instr index="" type=\types rep="r"
119	.endr
120	.endif
121	.endr
122
123	.macro ldstn_index_rep_H_imm inst index type rep
124	\inst\()1\rep {v0.\type}\index, [x0], #2
125	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #4
126	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #6
127	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #8
128	.endm
129
130	.irp instr, ld, st
131	ldstn_index_rep_H_imm \instr index="[1]" type=h rep=""
132	.ifnc \instr, st
133	.irp types 4h, 8h
134	ldstn_index_rep_H_imm \instr index="" type=\types rep="r"
135	.endr
136	.endif
137	.endr
138
139	.macro ldstn_index_rep_S_imm inst index type rep
140	\inst\()1\rep {v0.\type}\index, [x0], #4
141	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #8
142	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #12
143	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #16
144	.endm
145
146	.irp instr, ld, st
147	ldstn_index_rep_S_imm \instr index="[1]" type=s rep=""
148	.ifnc \instr, st
149	.irp types 2s, 4s
150	ldstn_index_rep_S_imm \instr index="" type=\types rep="r"
151	.endr
152	.endif
153	.endr
154
155	.macro ldstn_index_rep_D_imm inst index type rep
156	\inst\()1\rep {v0.\type}\index, [x0], #8
157	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], #16
158	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], #24
159	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], #32
160	.endm
161
162	.irp instr, ld, st
163	ldstn_index_rep_D_imm \instr index="[1]" type=d rep=""
164	.ifnc \instr, st
165	.irp types 1d, 2d
166	ldstn_index_rep_D_imm \instr index="" type=\types rep="r"
167	.endr
168	.endif
169	.endr
170
171	# Post Index Vector-element form with replicate (Register offset)
172	# This could have been factored into Post-index multiple
173	# element macros but this would make this already-looking-complex
174	# testcase look more complex!
175
176	# Consecutive registers in reg list
177
178	.macro ldstn_index_rep_reg inst index type rep postreg
179	\inst\()1\rep {v0.\type}\index, [x0], \postreg
180	\inst\()2\rep {v0.\type, v1.\type}\index, [x0], \postreg
181	\inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0], \postreg
182	\inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0], \postreg
183	.endm
184
185	.irp instr, ld, st
186	.irp itypes b,h,s,d
187	ldstn_index_rep_reg \instr index="[1]" type=\itypes rep="" postreg=x7
188	.endr
189	.ifnc \instr, st
190	.irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
191	ldstn_index_rep_reg \instr index="" type=\types rep="r" postreg=x7
192	.endr
193	.endif
194	.endr
195
196	# ### End of test