[thirdparty/gcc.git] / gcc / common / config / aarch64 / aarch64-common.c

/* Common hooks for AArch64.
   Copyright (C) 2012-2019 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

#include "config.h"
#define INCLUDE_STRING
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "memmodel.h"
#include "tm_p.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
#include "diagnostic.h"
#include "params.h"

#ifdef  TARGET_BIG_ENDIAN_DEFAULT
#undef  TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
#endif

#undef  TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION aarch64_handle_option

#undef	TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE aarch_option_optimization_table
#undef TARGET_OPTION_DEFAULT_PARAMS
#define TARGET_OPTION_DEFAULT_PARAMS aarch64_option_default_params
#undef TARGET_OPTION_VALIDATE_PARAM
#define TARGET_OPTION_VALIDATE_PARAM aarch64_option_validate_param
#undef TARGET_OPTION_INIT_STRUCT
#define TARGET_OPTION_INIT_STRUCT aarch64_option_init_struct

/* Set default optimization options.  */
static const struct default_options aarch_option_optimization_table[] =
  {
    /* Enable section anchors by default at -O1 or higher.  */
    { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
    /* Disable fomit-frame-pointer by default.  */
    { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 0 },
    /* Enable -fsched-pressure by default when optimizing.  */
    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
    /* Enable redundant extension instructions removal at -O2 and higher.  */
    { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
#if (TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1)
    { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
    { OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1},
#endif
    { OPT_LEVELS_NONE, 0, NULL, 0 }
  };

/* Implement target validation TARGET_OPTION_DEFAULT_PARAM.  */

static bool
aarch64_option_validate_param (const int value, const int param)
{
  /* Check that both parameters are the same.  */
  if (param == (int) PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE)
    {
      if (value != 12 && value != 16)
	{
	  error ("only values 12 (4 KB) and 16 (64 KB) are supported for guard "
		 "size.  Given value %d (%llu KB) is out of range",
		 value, (1ULL << value) / 1024ULL);
	  return false;
	}
    }

  return true;
}

/* Implement TARGET_OPTION_DEFAULT_PARAMS.  */

static void
aarch64_option_default_params (void)
{
  /* We assume the guard page is 64k.  */
  int index = (int) PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE;
  set_default_param_value (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE,
			   DEFAULT_STK_CLASH_GUARD_SIZE == 0
			     ? 16 : DEFAULT_STK_CLASH_GUARD_SIZE);

  int guard_size
    = default_param_value (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE);

  /* Set the interval parameter to be the same as the guard size.  This way the
     mid-end code does the right thing for us.  */
  set_default_param_value (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL,
			   guard_size);

  /* Validate the options.  */
  aarch64_option_validate_param (guard_size, index);
}

/* Implement TARGET_HANDLE_OPTION.
   This function handles the target specific options for CPU/target selection.

   -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
   If either of -march or -mtune is given, they override their
   respective component of -mcpu.  This logic is implemented
   in config/aarch64/aarch64.c:aarch64_override_options.  */

bool
aarch64_handle_option (struct gcc_options *opts,
		       struct gcc_options *opts_set ATTRIBUTE_UNUSED,
		       const struct cl_decoded_option *decoded,
		       location_t loc ATTRIBUTE_UNUSED)
{
  size_t code = decoded->opt_index;
  const char *arg = decoded->arg;
  int val = decoded->value;

  switch (code)
    {
    case OPT_march_:
      opts->x_aarch64_arch_string = arg;
      return true;

    case OPT_mcpu_:
      opts->x_aarch64_cpu_string = arg;
      return true;

    case OPT_mtune_:
      opts->x_aarch64_tune_string = arg;
      return true;

    case OPT_mgeneral_regs_only:
      opts->x_target_flags |= MASK_GENERAL_REGS_ONLY;
      return true;

    case OPT_mfix_cortex_a53_835769:
      opts->x_aarch64_fix_a53_err835769 = val;
      return true;

    case OPT_mstrict_align:
      if (val)
	opts->x_target_flags |= MASK_STRICT_ALIGN;
      else
	opts->x_target_flags &= ~MASK_STRICT_ALIGN;
      return true;

    case OPT_momit_leaf_frame_pointer:
      opts->x_flag_omit_leaf_frame_pointer = val;
      return true;

    default:
      return true;
    }
}

/* An ISA extension in the co-processor and main instruction set space.  */
struct aarch64_option_extension
{
  const char *const name;
  const uint64_t flag_canonical;
  const uint64_t flags_on;
  const uint64_t flags_off;
  const bool is_synthetic;
};

/* ISA extensions in AArch64.  */
static const struct aarch64_option_extension all_extensions[] =
{
#define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \
			      SYNTHETIC, Z) \
  {NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC},
#include "config/aarch64/aarch64-option-extensions.def"
  {NULL, 0, 0, 0, false}
};

/* A copy of the ISA extensions list for AArch64 sorted by the popcount of
   bits and extension turned on.  Cached for efficiency.  */
static struct aarch64_option_extension all_extensions_by_on[] =
{
#define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \
			      SYNTHETIC, Z) \
  {NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC},
#include "config/aarch64/aarch64-option-extensions.def"
  {NULL, 0, 0, 0, false}
};

struct processor_name_to_arch
{
  const std::string processor_name;
  const enum aarch64_arch arch;
  const uint64_t flags;
};

struct arch_to_arch_name
{
  const enum aarch64_arch arch;
  const std::string arch_name;
  const uint64_t flags;
};

/* Map processor names to the architecture revision they implement and
   the default set of architectural feature flags they support.  */
static const struct processor_name_to_arch all_cores[] =
{
#define AARCH64_CORE(NAME, X, IDENT, ARCH_IDENT, FLAGS, COSTS, IMP, PART, VARIANT) \
  {NAME, AARCH64_ARCH_##ARCH_IDENT, FLAGS},
#include "config/aarch64/aarch64-cores.def"
  {"generic", AARCH64_ARCH_8A, AARCH64_FL_FOR_ARCH8},
  {"", aarch64_no_arch, 0}
};

/* Map architecture revisions to their string representation.  */
static const struct arch_to_arch_name all_architectures[] =
{
#define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH, FLAGS) \
  {AARCH64_ARCH_##ARCH_IDENT, NAME, FLAGS},
#include "config/aarch64/aarch64-arches.def"
  {aarch64_no_arch, "", 0}
};

/* Parse the architecture extension string STR and update ISA_FLAGS
   with the architecture features turned on or off.  Return a
   aarch64_parse_opt_result describing the result.
   When the STR string contains an invalid extension,
   a copy of the string is created and stored to INVALID_EXTENSION.  */

enum aarch64_parse_opt_result
aarch64_parse_extension (const char *str, uint64_t *isa_flags,
			 std::string *invalid_extension)
{
  /* The extension string is parsed left to right.  */
  const struct aarch64_option_extension *opt = NULL;

  /* Flag to say whether we are adding or removing an extension.  */
  int adding_ext = -1;

  while (str != NULL && *str != 0)
    {
      const char *ext;
      size_t len;

      str++;
      ext = strchr (str, '+');

      if (ext != NULL)
	len = ext - str;
      else
	len = strlen (str);

      if (len >= 2 && strncmp (str, "no", 2) == 0)
	{
	  adding_ext = 0;
	  len -= 2;
	  str += 2;
	}
      else if (len > 0)
	adding_ext = 1;

      if (len == 0)
	return AARCH64_PARSE_MISSING_ARG;


      /* Scan over the extensions table trying to find an exact match.  */
      for (opt = all_extensions; opt->name != NULL; opt++)
	{
	  if (strlen (opt->name) == len && strncmp (opt->name, str, len) == 0)
	    {
	      /* Add or remove the extension.  */
	      if (adding_ext)
		*isa_flags |= (opt->flags_on | opt->flag_canonical);
	      else
		*isa_flags &= ~(opt->flags_off | opt->flag_canonical);
	      break;
	    }
	}

      if (opt->name == NULL)
	{
	  /* Extension not found in list.  */
	  if (invalid_extension)
	    *invalid_extension = std::string (str, len);
	  return AARCH64_PARSE_INVALID_FEATURE;
	}

      str = ext;
    };

  return AARCH64_PARSE_OK;
}

/* Append all architecture extension candidates to the CANDIDATES vector.  */

void
aarch64_get_all_extension_candidates (auto_vec<const char *> *candidates)
{
  const struct aarch64_option_extension *opt;
  for (opt = all_extensions; opt->name != NULL; opt++)
    candidates->safe_push (opt->name);
}

/* Comparer to sort aarch64's feature extensions by population count. Largest
   first.  */

typedef const struct aarch64_option_extension opt_ext;

int opt_ext_cmp (const void* a, const void* b)
{
  opt_ext *opt_a = (opt_ext *)a;
  opt_ext *opt_b = (opt_ext *)b;

  /* We consider the total set of bits an options turns on to be the union of
     the singleton set containing the option itself and the set of options it
     turns on as a dependency.  As an example +dotprod turns on FL_DOTPROD and
     FL_SIMD.  As such the set of bits represented by this option is
     {FL_DOTPROD, FL_SIMD}. */
  uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on;
  uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on;
  int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a);
  int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b);
  int order = popcnt_b - popcnt_a;

  /* If they have the same amount of bits set, give it a more
     deterministic ordering by using the value of the bits themselves.  */
  if (order != 0)
    return order;

  if (total_flags_a != total_flags_b)
    return total_flags_a < total_flags_b ? 1 : -1;

  return 0;
}

/* Implement TARGET_OPTION_INIT_STRUCT.  */

static void
aarch64_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED)
{
    /* Sort the extensions based on how many bits they set, order the larger
       counts first.  We sort the list because this makes processing the
       feature bits O(n) instead of O(n^2).  While n is small, the function
       to calculate the feature strings is called on every options push,
       pop and attribute change (arm_neon headers, lto etc all cause this to
       happen quite frequently).  It is a trade-off between time and space and
       so time won.  */
    int n_extensions
      = sizeof (all_extensions) / sizeof (struct aarch64_option_extension);
    qsort (&all_extensions_by_on, n_extensions,
	   sizeof (struct aarch64_option_extension), opt_ext_cmp);
}

/* Checks to see if enough bits from the option OPT are enabled in
   ISA_FLAG_BITS to be able to replace the individual options with the
   canonicalized version of the option.  This is done based on two rules:

   1) Synthetic groups, such as +crypto we only care about the bits that are
      turned on. e.g. +aes+sha2 can be replaced with +crypto.

   2) Options that themselves have a bit, such as +rdma, in this case, all the
      feature bits they turn on must be available and the bit for the option
      itself must be.  In this case it's effectively a reduction rather than a
      grouping. e.g. +fp+simd is not enough to turn on +rdma, for that you would
      need +rdma+fp+simd which is reduced down to +rdma.
*/

static bool
aarch64_contains_opt (uint64_t isa_flag_bits, opt_ext *opt)
{
  uint64_t flags_check
    = opt->is_synthetic ? opt->flags_on : opt->flag_canonical;

  return (isa_flag_bits & flags_check) == flags_check;
}

/* Return a string representation of ISA_FLAGS.  DEFAULT_ARCH_FLAGS
   gives the default set of flags which are implied by whatever -march
   we'd put out.  Our job is to figure out the minimal set of "+" and
   "+no" feature flags to put out, and to put them out grouped such
   that all the "+" flags come before the "+no" flags.  */

std::string
aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags,
					    uint64_t default_arch_flags)
{
  const struct aarch64_option_extension *opt = NULL;
  std::string outstr = "";

  uint64_t isa_flag_bits = isa_flags;

  /* Pass one: Minimize the search space by reducing the set of options
     to the smallest set that still turns on the same features as before in
     conjunction with the bits that are turned on by default for the selected
     architecture.  */
  for (opt = all_extensions_by_on; opt->name != NULL; opt++)
    {
      /* If the bit is on by default, then all the options it turns on are also
	 on by default due to the transitive dependencies.

         If the option is enabled explicitly in the set then we need to emit
	 an option for it.  Since this list is sorted by extensions setting the
	 largest number of featers first, we can be sure that nothing else will
	 ever need to set the bits we already set.  Consider the following
	 situation:

	  Feat1 = A + B + C
	  Feat2 = A + B
	  Feat3 = A + D
	  Feat4 = B + C
	  Feat5 = C

	The following results are expected:

	  A + C = A + Feat5
	  B + C = Feat4
	  Feat4 + A = Feat1
	  Feat2 + Feat5 = Feat1
	  Feat1 + C = Feat1
          Feat3 + Feat4 = Feat1 + D

	This search assumes that all invidual feature bits are use visible,
	in other words the user must be able to do +A, +B, +C and +D.  */
      if (aarch64_contains_opt (isa_flag_bits | default_arch_flags, opt))
      {
	/* We remove all the dependent bits, to prevent them from being turned
	   on twice.  This only works because we assume that all there are
	   individual options to set all bits standalone.  */
	isa_flag_bits &= ~opt->flags_on;
	isa_flag_bits |= opt->flag_canonical;
      }
    }

   /* By toggling bits on and off, we may have set bits on that are already
      enabled by default.  So we mask the default set out so we don't emit an
      option for them.  Instead of checking for this each time during Pass One
      we just mask all default bits away at the end.  */
   isa_flag_bits &= ~default_arch_flags;

   /* We now have the smallest set of features we need to process.  A subsequent
      linear scan of the bits in isa_flag_bits will allow us to print the ext
      names.  However as a special case if CRC was enabled before, always print
      it.  This is required because some CPUs have an incorrect specification
      in older assemblers.  Even though CRC should be the default for these
      cases the -mcpu values won't turn it on.  */
  if (isa_flags & AARCH64_ISA_CRC)
    isa_flag_bits |= AARCH64_ISA_CRC;

  /* Pass Two:
     Print the option names that we're sure we must turn on.  These are only
     optional extension names.  Mandatory ones have already been removed and
     ones we explicitly want off have been too.  */
  for (opt = all_extensions_by_on; opt->name != NULL; opt++)
    {
      if (isa_flag_bits & opt->flag_canonical)
	{
	  outstr += "+";
	  outstr += opt->name;
	}
    }

  /* Pass Three:
     Print out a +no for any mandatory extension that we are
     turning off.  By this point aarch64_parse_extension would have ensured
     that any optional extensions are turned off.  The only things left are
     things that can't be turned off usually, e.g. something that is on by
     default because it's mandatory and we want it off.  For turning off bits
     we don't guarantee the smallest set of flags, but instead just emit all
     options the user has specified.

     The assembler requires all +<opts> to be printed before +no<opts>.  */
  for (opt = all_extensions_by_on; opt->name != NULL; opt++)
    {
      if ((~isa_flags) & opt->flag_canonical
		&& !((~default_arch_flags) & opt->flag_canonical))
	{
	  outstr += "+no";
	  outstr += opt->name;
	}
    }

  return outstr;
}

/* Attempt to rewrite NAME, which has been passed on the command line
   as a -mcpu option to an equivalent -march value.  If we can do so,
   return the new string, otherwise return an error.  */

const char *
aarch64_rewrite_selected_cpu (const char *name)
{
  std::string original_string (name);
  std::string extension_str;
  std::string processor;
  size_t extension_pos = original_string.find_first_of ('+');

  /* Strip and save the extension string.  */
  if (extension_pos != std::string::npos)
    {
      processor = original_string.substr (0, extension_pos);
      extension_str = original_string.substr (extension_pos,
					      std::string::npos);
    }
  else
    {
      /* No extensions.  */
      processor = original_string;
    }

  const struct processor_name_to_arch* p_to_a;
  for (p_to_a = all_cores;
       p_to_a->arch != aarch64_no_arch;
       p_to_a++)
    {
      if (p_to_a->processor_name == processor)
	break;
    }

  const struct arch_to_arch_name* a_to_an;
  for (a_to_an = all_architectures;
       a_to_an->arch != aarch64_no_arch;
       a_to_an++)
    {
      if (a_to_an->arch == p_to_a->arch)
	break;
    }

  /* We couldn't find that proceesor name, or the processor name we
     found does not map to an architecture we understand.  */
  if (p_to_a->arch == aarch64_no_arch
      || a_to_an->arch == aarch64_no_arch)
    fatal_error (input_location, "unknown value %qs for %<-mcpu%>", name);

  unsigned long extensions = p_to_a->flags;
  aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);

  std::string outstr = a_to_an->arch_name
	+ aarch64_get_extension_string_for_isa_flags (extensions,
						      a_to_an->flags);

  /* We are going to memory leak here, nobody elsewhere
     in the callchain is going to clean up after us.  The alternative is
     to allocate a static buffer, and assert that it is big enough for our
     modified string, which seems much worse!  */
  return xstrdup (outstr.c_str ());
}

/* Called by the driver to rewrite a name passed to the -mcpu
   argument in preparation to be passed to the assembler.  The
   names passed from the commend line will be in ARGV, we want
   to use the right-most argument, which should be in
   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */

const char *
aarch64_rewrite_mcpu (int argc, const char **argv)
{
  gcc_assert (argc);
  return aarch64_rewrite_selected_cpu (argv[argc - 1]);
}

struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

#undef AARCH64_CPU_NAME_LENGTH
Commit	Line	Data
43e9d192	1	/* Common hooks for AArch64.
a5544970	2	Copyright (C) 2012-2019 Free Software Foundation, Inc.
43e9d192 IB	3	Contributed by ARM Ltd.
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
	21	#include "config.h"
01736018	22	#define INCLUDE_STRING
43e9d192 IB	23	#include "system.h"
	24	#include "coretypes.h"
	25	#include "tm.h"
4d0cdd0c	26	#include "memmodel.h"
43e9d192 IB	27	#include "tm_p.h"
	28	#include "common/common-target.h"
	29	#include "common/common-target-def.h"
	30	#include "opts.h"
	31	#include "flags.h"
054b4005	32	#include "diagnostic.h"
329130cc	33	#include "params.h"
43e9d192 IB	34
	35	#ifdef TARGET_BIG_ENDIAN_DEFAULT
	36	#undef TARGET_DEFAULT_TARGET_FLAGS
	37	#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
	38	#endif
	39
	40	#undef TARGET_HANDLE_OPTION
	41	#define TARGET_HANDLE_OPTION aarch64_handle_option
	42
	43	#undef TARGET_OPTION_OPTIMIZATION_TABLE
	44	#define TARGET_OPTION_OPTIMIZATION_TABLE aarch_option_optimization_table
329130cc TC	45	#undef TARGET_OPTION_DEFAULT_PARAMS
	46	#define TARGET_OPTION_DEFAULT_PARAMS aarch64_option_default_params
	47	#undef TARGET_OPTION_VALIDATE_PARAM
	48	#define TARGET_OPTION_VALIDATE_PARAM aarch64_option_validate_param
4ca82fc9 TC	49	#undef TARGET_OPTION_INIT_STRUCT
4ca82fc9 TC	50	#define TARGET_OPTION_INIT_STRUCT aarch64_option_init_struct
43e9d192 IB	51
	52	/* Set default optimization options. */
	53	static const struct default_options aarch_option_optimization_table[] =
	54	{
	55	/* Enable section anchors by default at -O1 or higher. */
	56	{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
af3b4514 RR	57	/* Disable fomit-frame-pointer by default. */
af3b4514 RR	58	{ OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 0 },
de72c50f WD	59	/* Enable -fsched-pressure by default when optimizing. */
de72c50f WD	60	{ OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
473cec55 IB	61	/* Enable redundant extension instructions removal at -O2 and higher. */
473cec55 IB	62	{ OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
b39036d2 RR	63	#if (TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1)
	64	{ OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
	65	{ OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1},
	66	#endif
43e9d192 IB	67	{ OPT_LEVELS_NONE, 0, NULL, 0 }
	68	};
	69
329130cc TC	70	/* Implement target validation TARGET_OPTION_DEFAULT_PARAM. */
	71
	72	static bool
	73	aarch64_option_validate_param (const int value, const int param)
	74	{
	75	/* Check that both parameters are the same. */
	76	if (param == (int) PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE)
	77	{
	78	if (value != 12 && value != 16)
	79	{
	80	error ("only values 12 (4 KB) and 16 (64 KB) are supported for guard "
	81	"size. Given value %d (%llu KB) is out of range",
	82	value, (1ULL << value) / 1024ULL);
	83	return false;
	84	}
	85	}
	86
	87	return true;
	88	}
	89
	90	/* Implement TARGET_OPTION_DEFAULT_PARAMS. */
	91
	92	static void
	93	aarch64_option_default_params (void)
	94	{
	95	/* We assume the guard page is 64k. */
	96	int index = (int) PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE;
	97	set_default_param_value (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE,
	98	DEFAULT_STK_CLASH_GUARD_SIZE == 0
	99	? 16 : DEFAULT_STK_CLASH_GUARD_SIZE);
	100
	101	int guard_size
	102	= default_param_value (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE);
	103
	104	/* Set the interval parameter to be the same as the guard size. This way the
	105	mid-end code does the right thing for us. */
	106	set_default_param_value (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL,
	107	guard_size);
	108
	109	/* Validate the options. */
	110	aarch64_option_validate_param (guard_size, index);
	111	}
	112
43e9d192 IB	113	/* Implement TARGET_HANDLE_OPTION.
	114	This function handles the target specific options for CPU/target selection.
	115
ffee7aa9 JG	116	-mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
	117	If either of -march or -mtune is given, they override their
	118	respective component of -mcpu. This logic is implemented
	119	in config/aarch64/aarch64.c:aarch64_override_options. */
43e9d192	120
5a2c8331	121	bool
43e9d192 IB	122	aarch64_handle_option (struct gcc_options *opts,
	123	struct gcc_options *opts_set ATTRIBUTE_UNUSED,
	124	const struct cl_decoded_option *decoded,
	125	location_t loc ATTRIBUTE_UNUSED)
	126	{
	127	size_t code = decoded->opt_index;
	128	const char *arg = decoded->arg;
5a2c8331	129	int val = decoded->value;
43e9d192 IB	130
	131	switch (code)
	132	{
	133	case OPT_march_:
	134	opts->x_aarch64_arch_string = arg;
43e9d192 IB	135	return true;
	136
	137	case OPT_mcpu_:
	138	opts->x_aarch64_cpu_string = arg;
43e9d192 IB	139	return true;
	140
	141	case OPT_mtune_:
	142	opts->x_aarch64_tune_string = arg;
	143	return true;
	144
5a2c8331 KT	145	case OPT_mgeneral_regs_only:
	146	opts->x_target_flags \|= MASK_GENERAL_REGS_ONLY;
	147	return true;
	148
	149	case OPT_mfix_cortex_a53_835769:
	150	opts->x_aarch64_fix_a53_err835769 = val;
	151	return true;
	152
	153	case OPT_mstrict_align:
675d044c SD	154	if (val)
	155	opts->x_target_flags \|= MASK_STRICT_ALIGN;
	156	else
	157	opts->x_target_flags &= ~MASK_STRICT_ALIGN;
5a2c8331 KT	158	return true;
	159
	160	case OPT_momit_leaf_frame_pointer:
48090169	161	opts->x_flag_omit_leaf_frame_pointer = val;
5a2c8331 KT	162	return true;
5a2c8331 KT	163
43e9d192 IB	164	default:
	165	return true;
	166	}
	167	}
	168
054b4005 JG	169	/* An ISA extension in the co-processor and main instruction set space. */
	170	struct aarch64_option_extension
	171	{
	172	const char *const name;
28108a53 MM	173	const uint64_t flag_canonical;
	174	const uint64_t flags_on;
	175	const uint64_t flags_off;
4ca82fc9	176	const bool is_synthetic;
054b4005 JG	177	};
	178
	179	/* ISA extensions in AArch64. */
	180	static const struct aarch64_option_extension all_extensions[] =
	181	{
4ca82fc9 TC	182	#define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \
	183	SYNTHETIC, Z) \
	184	{NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC},
	185	#include "config/aarch64/aarch64-option-extensions.def"
	186	{NULL, 0, 0, 0, false}
	187	};
	188
	189	/* A copy of the ISA extensions list for AArch64 sorted by the popcount of
	190	bits and extension turned on. Cached for efficiency. */
	191	static struct aarch64_option_extension all_extensions_by_on[] =
	192	{
	193	#define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \
	194	SYNTHETIC, Z) \
	195	{NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC},
054b4005	196	#include "config/aarch64/aarch64-option-extensions.def"
4ca82fc9	197	{NULL, 0, 0, 0, false}
054b4005 JG	198	};
	199
	200	struct processor_name_to_arch
	201	{
	202	const std::string processor_name;
	203	const enum aarch64_arch arch;
28108a53	204	const uint64_t flags;
054b4005 JG	205	};
	206
	207	struct arch_to_arch_name
	208	{
	209	const enum aarch64_arch arch;
	210	const std::string arch_name;
28108a53	211	const uint64_t flags;
054b4005 JG	212	};
	213
	214	/* Map processor names to the architecture revision they implement and
	215	the default set of architectural feature flags they support. */
	216	static const struct processor_name_to_arch all_cores[] =
	217	{
e8fcc9fa	218	#define AARCH64_CORE(NAME, X, IDENT, ARCH_IDENT, FLAGS, COSTS, IMP, PART, VARIANT) \
054b4005 JG	219	{NAME, AARCH64_ARCH_##ARCH_IDENT, FLAGS},
054b4005 JG	220	#include "config/aarch64/aarch64-cores.def"
054b4005 JG	221	{"generic", AARCH64_ARCH_8A, AARCH64_FL_FOR_ARCH8},
	222	{"", aarch64_no_arch, 0}
	223	};
	224
	225	/* Map architecture revisions to their string representation. */
	226	static const struct arch_to_arch_name all_architectures[] =
	227	{
	228	#define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH, FLAGS) \
04a99ebe	229	{AARCH64_ARCH_##ARCH_IDENT, NAME, FLAGS},
054b4005	230	#include "config/aarch64/aarch64-arches.def"
04a99ebe	231	{aarch64_no_arch, "", 0}
054b4005 JG	232	};
054b4005 JG	233
04a99ebe JG	234	/* Parse the architecture extension string STR and update ISA_FLAGS
04a99ebe JG	235	with the architecture features turned on or off. Return a
c7887347 ML	236	aarch64_parse_opt_result describing the result.
	237	When the STR string contains an invalid extension,
	238	a copy of the string is created and stored to INVALID_EXTENSION. */
04a99ebe JG	239
04a99ebe JG	240	enum aarch64_parse_opt_result
28108a53	241	aarch64_parse_extension (const char str, uint64_t isa_flags,
c7887347	242	std::string *invalid_extension)
04a99ebe JG	243	{
	244	/* The extension string is parsed left to right. */
	245	const struct aarch64_option_extension *opt = NULL;
	246
	247	/* Flag to say whether we are adding or removing an extension. */
	248	int adding_ext = -1;
	249
	250	while (str != NULL && *str != 0)
	251	{
	252	const char *ext;
	253	size_t len;
	254
	255	str++;
	256	ext = strchr (str, '+');
	257
	258	if (ext != NULL)
	259	len = ext - str;
	260	else
	261	len = strlen (str);
	262
	263	if (len >= 2 && strncmp (str, "no", 2) == 0)
	264	{
	265	adding_ext = 0;
	266	len -= 2;
	267	str += 2;
	268	}
	269	else if (len > 0)
	270	adding_ext = 1;
	271
	272	if (len == 0)
	273	return AARCH64_PARSE_MISSING_ARG;
	274
	275
	276	/* Scan over the extensions table trying to find an exact match. */
	277	for (opt = all_extensions; opt->name != NULL; opt++)
	278	{
	279	if (strlen (opt->name) == len && strncmp (opt->name, str, len) == 0)
	280	{
	281	/* Add or remove the extension. */
	282	if (adding_ext)
	283	*isa_flags \|= (opt->flags_on \| opt->flag_canonical);
	284	else
	285	*isa_flags &= ~(opt->flags_off \| opt->flag_canonical);
	286	break;
	287	}
	288	}
	289
	290	if (opt->name == NULL)
	291	{
	292	/* Extension not found in list. */
c7887347 ML	293	if (invalid_extension)
c7887347 ML	294	*invalid_extension = std::string (str, len);
04a99ebe JG	295	return AARCH64_PARSE_INVALID_FEATURE;
	296	}
	297
	298	str = ext;
	299	};
	300
	301	return AARCH64_PARSE_OK;
	302	}
	303
c7887347 ML	304	/* Append all architecture extension candidates to the CANDIDATES vector. */
	305
	306	void
	307	aarch64_get_all_extension_candidates (auto_vec<const char > candidates)
	308	{
	309	const struct aarch64_option_extension *opt;
	310	for (opt = all_extensions; opt->name != NULL; opt++)
	311	candidates->safe_push (opt->name);
	312	}
	313
4ca82fc9 TC	314	/* Comparer to sort aarch64's feature extensions by population count. Largest
	315	first. */
	316
	317	typedef const struct aarch64_option_extension opt_ext;
	318
	319	int opt_ext_cmp (const void* a, const void* b)
	320	{
	321	opt_ext opt_a = (opt_ext )a;
	322	opt_ext opt_b = (opt_ext )b;
	323
	324	/* We consider the total set of bits an options turns on to be the union of
	325	the singleton set containing the option itself and the set of options it
	326	turns on as a dependency. As an example +dotprod turns on FL_DOTPROD and
	327	FL_SIMD. As such the set of bits represented by this option is
	328	{FL_DOTPROD, FL_SIMD}. */
28108a53 MM	329	uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on;
28108a53 MM	330	uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on;
4ca82fc9 TC	331	int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a);
	332	int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b);
	333	int order = popcnt_b - popcnt_a;
	334
	335	/* If they have the same amount of bits set, give it a more
	336	deterministic ordering by using the value of the bits themselves. */
28108a53 MM	337	if (order != 0)
28108a53 MM	338	return order;
4ca82fc9	339
28108a53 MM	340	if (total_flags_a != total_flags_b)
	341	return total_flags_a < total_flags_b ? 1 : -1;
	342
	343	return 0;
4ca82fc9 TC	344	}
	345
	346	/* Implement TARGET_OPTION_INIT_STRUCT. */
	347
	348	static void
	349	aarch64_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED)
	350	{
	351	/* Sort the extensions based on how many bits they set, order the larger
	352	counts first. We sort the list because this makes processing the
	353	feature bits O(n) instead of O(n^2). While n is small, the function
	354	to calculate the feature strings is called on every options push,
	355	pop and attribute change (arm_neon headers, lto etc all cause this to
	356	happen quite frequently). It is a trade-off between time and space and
	357	so time won. */
	358	int n_extensions
	359	= sizeof (all_extensions) / sizeof (struct aarch64_option_extension);
	360	qsort (&all_extensions_by_on, n_extensions,
	361	sizeof (struct aarch64_option_extension), opt_ext_cmp);
	362	}
	363
	364	/* Checks to see if enough bits from the option OPT are enabled in
	365	ISA_FLAG_BITS to be able to replace the individual options with the
	366	canonicalized version of the option. This is done based on two rules:
	367
	368	1) Synthetic groups, such as +crypto we only care about the bits that are
	369	turned on. e.g. +aes+sha2 can be replaced with +crypto.
	370
	371	2) Options that themselves have a bit, such as +rdma, in this case, all the
	372	feature bits they turn on must be available and the bit for the option
	373	itself must be. In this case it's effectively a reduction rather than a
	374	grouping. e.g. +fp+simd is not enough to turn on +rdma, for that you would
	375	need +rdma+fp+simd which is reduced down to +rdma.
	376	*/
	377
	378	static bool
28108a53	379	aarch64_contains_opt (uint64_t isa_flag_bits, opt_ext *opt)
4ca82fc9	380	{
28108a53	381	uint64_t flags_check
4ca82fc9 TC	382	= opt->is_synthetic ? opt->flags_on : opt->flag_canonical;
	383
	384	return (isa_flag_bits & flags_check) == flags_check;
	385	}
	386
04a99ebe JG	387	/* Return a string representation of ISA_FLAGS. DEFAULT_ARCH_FLAGS
	388	gives the default set of flags which are implied by whatever -march
	389	we'd put out. Our job is to figure out the minimal set of "+" and
	390	"+no" feature flags to put out, and to put them out grouped such
	391	that all the "+" flags come before the "+no" flags. */
054b4005 JG	392
054b4005 JG	393	std::string
28108a53 MM	394	aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags,
28108a53 MM	395	uint64_t default_arch_flags)
054b4005 JG	396	{
	397	const struct aarch64_option_extension *opt = NULL;
	398	std::string outstr = "";
	399
28108a53	400	uint64_t isa_flag_bits = isa_flags;
04a99ebe	401
4ca82fc9 TC	402	/* Pass one: Minimize the search space by reducing the set of options
	403	to the smallest set that still turns on the same features as before in
	404	conjunction with the bits that are turned on by default for the selected
	405	architecture. */
	406	for (opt = all_extensions_by_on; opt->name != NULL; opt++)
	407	{
	408	/* If the bit is on by default, then all the options it turns on are also
	409	on by default due to the transitive dependencies.
	410
	411	If the option is enabled explicitly in the set then we need to emit
	412	an option for it. Since this list is sorted by extensions setting the
	413	largest number of featers first, we can be sure that nothing else will
	414	ever need to set the bits we already set. Consider the following
	415	situation:
	416
	417	Feat1 = A + B + C
	418	Feat2 = A + B
	419	Feat3 = A + D
	420	Feat4 = B + C
	421	Feat5 = C
	422
	423	The following results are expected:
	424
	425	A + C = A + Feat5
	426	B + C = Feat4
	427	Feat4 + A = Feat1
	428	Feat2 + Feat5 = Feat1
	429	Feat1 + C = Feat1
	430	Feat3 + Feat4 = Feat1 + D
	431
	432	This search assumes that all invidual feature bits are use visible,
	433	in other words the user must be able to do +A, +B, +C and +D. */
	434	if (aarch64_contains_opt (isa_flag_bits \| default_arch_flags, opt))
04a99ebe	435	{
4ca82fc9 TC	436	/* We remove all the dependent bits, to prevent them from being turned
	437	on twice. This only works because we assume that all there are
	438	individual options to set all bits standalone. */
	439	isa_flag_bits &= ~opt->flags_on;
	440	isa_flag_bits \|= opt->flag_canonical;
04a99ebe	441	}
4ca82fc9 TC	442	}
	443
	444	/* By toggling bits on and off, we may have set bits on that are already
	445	enabled by default. So we mask the default set out so we don't emit an
	446	option for them. Instead of checking for this each time during Pass One
	447	we just mask all default bits away at the end. */
	448	isa_flag_bits &= ~default_arch_flags;
	449
	450	/* We now have the smallest set of features we need to process. A subsequent
	451	linear scan of the bits in isa_flag_bits will allow us to print the ext
	452	names. However as a special case if CRC was enabled before, always print
	453	it. This is required because some CPUs have an incorrect specification
	454	in older assemblers. Even though CRC should be the default for these
	455	cases the -mcpu values won't turn it on. */
	456	if (isa_flags & AARCH64_ISA_CRC)
	457	isa_flag_bits \|= AARCH64_ISA_CRC;
	458
	459	/* Pass Two:
	460	Print the option names that we're sure we must turn on. These are only
	461	optional extension names. Mandatory ones have already been removed and
	462	ones we explicitly want off have been too. */
	463	for (opt = all_extensions_by_on; opt->name != NULL; opt++)
	464	{
	465	if (isa_flag_bits & opt->flag_canonical)
	466	{
	467	outstr += "+";
	468	outstr += opt->name;
	469	}
	470	}
	471
	472	/* Pass Three:
	473	Print out a +no for any mandatory extension that we are
	474	turning off. By this point aarch64_parse_extension would have ensured
	475	that any optional extensions are turned off. The only things left are
	476	things that can't be turned off usually, e.g. something that is on by
	477	default because it's mandatory and we want it off. For turning off bits
	478	we don't guarantee the smallest set of flags, but instead just emit all
	479	options the user has specified.
	480
	481	The assembler requires all +<opts> to be printed before +no<opts>. */
	482	for (opt = all_extensions_by_on; opt->name != NULL; opt++)
	483	{
	484	if ((~isa_flags) & opt->flag_canonical
	485	&& !((~default_arch_flags) & opt->flag_canonical))
	486	{
	487	outstr += "+no";
	488	outstr += opt->name;
	489	}
	490	}
04a99ebe	491
054b4005 JG	492	return outstr;
054b4005 JG	493	}
682287fb	494
054b4005 JG	495	/* Attempt to rewrite NAME, which has been passed on the command line
	496	as a -mcpu option to an equivalent -march value. If we can do so,
	497	return the new string, otherwise return an error. */
682287fb JG	498
	499	const char *
	500	aarch64_rewrite_selected_cpu (const char *name)
	501	{
054b4005	502	std::string original_string (name);
04a99ebe	503	std::string extension_str;
054b4005 JG	504	std::string processor;
054b4005 JG	505	size_t extension_pos = original_string.find_first_of ('+');
682287fb	506
054b4005 JG	507	/* Strip and save the extension string. */
	508	if (extension_pos != std::string::npos)
	509	{
	510	processor = original_string.substr (0, extension_pos);
04a99ebe JG	511	extension_str = original_string.substr (extension_pos,
04a99ebe JG	512	std::string::npos);
054b4005 JG	513	}
	514	else
	515	{
	516	/* No extensions. */
	517	processor = original_string;
	518	}
efb25f54	519
054b4005 JG	520	const struct processor_name_to_arch* p_to_a;
	521	for (p_to_a = all_cores;
	522	p_to_a->arch != aarch64_no_arch;
	523	p_to_a++)
	524	{
	525	if (p_to_a->processor_name == processor)
	526	break;
	527	}
efb25f54	528
054b4005 JG	529	const struct arch_to_arch_name* a_to_an;
	530	for (a_to_an = all_architectures;
	531	a_to_an->arch != aarch64_no_arch;
	532	a_to_an++)
	533	{
	534	if (a_to_an->arch == p_to_a->arch)
	535	break;
	536	}
682287fb	537
054b4005 JG	538	/* We couldn't find that proceesor name, or the processor name we
	539	found does not map to an architecture we understand. */
	540	if (p_to_a->arch == aarch64_no_arch
	541	\|\| a_to_an->arch == aarch64_no_arch)
a3f9f006	542	fatal_error (input_location, "unknown value %qs for %<-mcpu%>", name);
054b4005	543
04a99ebe	544	unsigned long extensions = p_to_a->flags;
c7887347	545	aarch64_parse_extension (extension_str.c_str (), &extensions, NULL);
04a99ebe	546
054b4005	547	std::string outstr = a_to_an->arch_name
04a99ebe JG	548	+ aarch64_get_extension_string_for_isa_flags (extensions,
04a99ebe JG	549	a_to_an->flags);
054b4005 JG	550
	551	/* We are going to memory leak here, nobody elsewhere
	552	in the callchain is going to clean up after us. The alternative is
	553	to allocate a static buffer, and assert that it is big enough for our
	554	modified string, which seems much worse! */
	555	return xstrdup (outstr.c_str ());
682287fb JG	556	}
	557
	558	/* Called by the driver to rewrite a name passed to the -mcpu
	559	argument in preparation to be passed to the assembler. The
1c05df59 JG	560	names passed from the commend line will be in ARGV, we want
	561	to use the right-most argument, which should be in
	562	ARGV[ARGC - 1]. ARGC should always be greater than 0. */
682287fb JG	563
	564	const char *
	565	aarch64_rewrite_mcpu (int argc, const char **argv)
	566	{
1c05df59 JG	567	gcc_assert (argc);
1c05df59 JG	568	return aarch64_rewrite_selected_cpu (argv[argc - 1]);
682287fb JG	569	}
682287fb JG	570
4ca82fc9 TC	571	struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
4ca82fc9 TC	572
682287fb JG	573	#undef AARCH64_CPU_NAME_LENGTH
682287fb JG	574