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3fb2c2f4 | 1 | /* Get CPU type and Features for x86 processors. |
7adcbafe | 2 | Copyright (C) 2012-2022 Free Software Foundation, Inc. |
3fb2c2f4 L |
3 | Contributed by Sriraman Tallam (tmsriram@google.com) |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | Under Section 7 of GPL version 3, you are granted additional | |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
24 | <http://www.gnu.org/licenses/>. */ | |
25 | ||
26 | /* Processor Vendor and Models. */ | |
27 | ||
28 | enum processor_vendor | |
29 | { | |
30 | VENDOR_INTEL = 1, | |
31 | VENDOR_AMD, | |
32 | VENDOR_OTHER, | |
1890f2f0 L |
33 | VENDOR_CENTAUR, |
34 | VENDOR_CYRIX, | |
35 | VENDOR_NSC, | |
3fb2c2f4 L |
36 | BUILTIN_VENDOR_MAX = VENDOR_OTHER, |
37 | VENDOR_MAX | |
38 | }; | |
39 | ||
40 | /* Any new types or subtypes have to be inserted at the end. */ | |
41 | ||
42 | enum processor_types | |
43 | { | |
44 | INTEL_BONNELL = 1, | |
45 | INTEL_CORE2, | |
46 | INTEL_COREI7, | |
47 | AMDFAM10H, | |
48 | AMDFAM15H, | |
49 | INTEL_SILVERMONT, | |
50 | INTEL_KNL, | |
51 | AMD_BTVER1, | |
52 | AMD_BTVER2, | |
53 | AMDFAM17H, | |
54 | INTEL_KNM, | |
55 | INTEL_GOLDMONT, | |
56 | INTEL_GOLDMONT_PLUS, | |
57 | INTEL_TREMONT, | |
3e2ae3ee | 58 | AMDFAM19H, |
3fb2c2f4 L |
59 | CPU_TYPE_MAX, |
60 | BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX | |
61 | }; | |
62 | ||
63 | enum processor_subtypes | |
64 | { | |
65 | INTEL_COREI7_NEHALEM = 1, | |
66 | INTEL_COREI7_WESTMERE, | |
67 | INTEL_COREI7_SANDYBRIDGE, | |
68 | AMDFAM10H_BARCELONA, | |
69 | AMDFAM10H_SHANGHAI, | |
70 | AMDFAM10H_ISTANBUL, | |
71 | AMDFAM15H_BDVER1, | |
72 | AMDFAM15H_BDVER2, | |
73 | AMDFAM15H_BDVER3, | |
74 | AMDFAM15H_BDVER4, | |
75 | AMDFAM17H_ZNVER1, | |
76 | INTEL_COREI7_IVYBRIDGE, | |
77 | INTEL_COREI7_HASWELL, | |
78 | INTEL_COREI7_BROADWELL, | |
79 | INTEL_COREI7_SKYLAKE, | |
80 | INTEL_COREI7_SKYLAKE_AVX512, | |
81 | INTEL_COREI7_CANNONLAKE, | |
82 | INTEL_COREI7_ICELAKE_CLIENT, | |
83 | INTEL_COREI7_ICELAKE_SERVER, | |
84 | AMDFAM17H_ZNVER2, | |
85 | INTEL_COREI7_CASCADELAKE, | |
86 | INTEL_COREI7_TIGERLAKE, | |
87 | INTEL_COREI7_COOPERLAKE, | |
ba9c87d3 CL |
88 | INTEL_COREI7_SAPPHIRERAPIDS, |
89 | INTEL_COREI7_ALDERLAKE, | |
3e2ae3ee | 90 | AMDFAM19H_ZNVER3, |
c02c39fa | 91 | INTEL_COREI7_ROCKETLAKE, |
3fb2c2f4 L |
92 | CPU_SUBTYPE_MAX |
93 | }; | |
94 | ||
95 | /* Priority of i386 features, greater value is higher priority. This is | |
96 | used to decide the order in which function dispatch must happen. For | |
97 | instance, a version specialized for SSE4.2 should be checked for dispatch | |
98 | before a version for SSE3, as SSE4.2 implies SSE3. */ | |
99 | enum feature_priority | |
100 | { | |
101 | P_NONE = 0, | |
102 | P_MMX, | |
103 | P_SSE, | |
104 | P_SSE2, | |
8ea29259 | 105 | P_X86_64_BASELINE, |
3fb2c2f4 L |
106 | P_SSE3, |
107 | P_SSSE3, | |
108 | P_PROC_SSSE3, | |
109 | P_SSE4_A, | |
110 | P_PROC_SSE4_A, | |
111 | P_SSE4_1, | |
112 | P_SSE4_2, | |
113 | P_PROC_SSE4_2, | |
114 | P_POPCNT, | |
8ea29259 | 115 | P_X86_64_V2, |
3fb2c2f4 L |
116 | P_AES, |
117 | P_PCLMUL, | |
118 | P_AVX, | |
119 | P_PROC_AVX, | |
120 | P_BMI, | |
121 | P_PROC_BMI, | |
122 | P_FMA4, | |
123 | P_XOP, | |
124 | P_PROC_XOP, | |
125 | P_FMA, | |
126 | P_PROC_FMA, | |
127 | P_BMI2, | |
128 | P_AVX2, | |
129 | P_PROC_AVX2, | |
8ea29259 | 130 | P_X86_64_V3, |
3fb2c2f4 L |
131 | P_AVX512F, |
132 | P_PROC_AVX512F, | |
8ea29259 | 133 | P_X86_64_V4, |
3fb2c2f4 L |
134 | P_PROC_DYNAMIC |
135 | }; | |
136 | ||
1890f2f0 L |
137 | /* ISA Features supported. New features have to be inserted at the end. */ |
138 | ||
139 | enum processor_features | |
140 | { | |
141 | FEATURE_CMOV = 0, | |
142 | FEATURE_MMX, | |
143 | FEATURE_POPCNT, | |
144 | FEATURE_SSE, | |
145 | FEATURE_SSE2, | |
146 | FEATURE_SSE3, | |
147 | FEATURE_SSSE3, | |
148 | FEATURE_SSE4_1, | |
149 | FEATURE_SSE4_2, | |
150 | FEATURE_AVX, | |
151 | FEATURE_AVX2, | |
152 | FEATURE_SSE4_A, | |
153 | FEATURE_FMA4, | |
154 | FEATURE_XOP, | |
155 | FEATURE_FMA, | |
156 | FEATURE_AVX512F, | |
157 | FEATURE_BMI, | |
158 | FEATURE_BMI2, | |
159 | FEATURE_AES, | |
160 | FEATURE_PCLMUL, | |
161 | FEATURE_AVX512VL, | |
162 | FEATURE_AVX512BW, | |
163 | FEATURE_AVX512DQ, | |
164 | FEATURE_AVX512CD, | |
165 | FEATURE_AVX512ER, | |
166 | FEATURE_AVX512PF, | |
167 | FEATURE_AVX512VBMI, | |
168 | FEATURE_AVX512IFMA, | |
169 | FEATURE_AVX5124VNNIW, | |
170 | FEATURE_AVX5124FMAPS, | |
171 | FEATURE_AVX512VPOPCNTDQ, | |
172 | FEATURE_AVX512VBMI2, | |
173 | FEATURE_GFNI, | |
174 | FEATURE_VPCLMULQDQ, | |
175 | FEATURE_AVX512VNNI, | |
176 | FEATURE_AVX512BITALG, | |
177 | FEATURE_AVX512BF16, | |
178 | FEATURE_AVX512VP2INTERSECT, | |
179 | FEATURE_3DNOW, | |
180 | FEATURE_3DNOWP, | |
181 | FEATURE_ADX, | |
182 | FEATURE_ABM, | |
183 | FEATURE_CLDEMOTE, | |
184 | FEATURE_CLFLUSHOPT, | |
185 | FEATURE_CLWB, | |
186 | FEATURE_CLZERO, | |
187 | FEATURE_CMPXCHG16B, | |
188 | FEATURE_CMPXCHG8B, | |
189 | FEATURE_ENQCMD, | |
190 | FEATURE_F16C, | |
191 | FEATURE_FSGSBASE, | |
192 | FEATURE_FXSAVE, | |
193 | FEATURE_HLE, | |
194 | FEATURE_IBT, | |
195 | FEATURE_LAHF_LM, | |
196 | FEATURE_LM, | |
197 | FEATURE_LWP, | |
198 | FEATURE_LZCNT, | |
199 | FEATURE_MOVBE, | |
200 | FEATURE_MOVDIR64B, | |
201 | FEATURE_MOVDIRI, | |
202 | FEATURE_MWAITX, | |
203 | FEATURE_OSXSAVE, | |
204 | FEATURE_PCONFIG, | |
205 | FEATURE_PKU, | |
206 | FEATURE_PREFETCHWT1, | |
207 | FEATURE_PRFCHW, | |
208 | FEATURE_PTWRITE, | |
209 | FEATURE_RDPID, | |
210 | FEATURE_RDRND, | |
211 | FEATURE_RDSEED, | |
212 | FEATURE_RTM, | |
213 | FEATURE_SERIALIZE, | |
214 | FEATURE_SGX, | |
215 | FEATURE_SHA, | |
216 | FEATURE_SHSTK, | |
217 | FEATURE_TBM, | |
218 | FEATURE_TSXLDTRK, | |
219 | FEATURE_VAES, | |
220 | FEATURE_WAITPKG, | |
221 | FEATURE_WBNOINVD, | |
222 | FEATURE_XSAVE, | |
223 | FEATURE_XSAVEC, | |
224 | FEATURE_XSAVEOPT, | |
225 | FEATURE_XSAVES, | |
5c609842 | 226 | FEATURE_AMX_TILE, |
227 | FEATURE_AMX_INT8, | |
228 | FEATURE_AMX_BF16, | |
299a53d7 | 229 | FEATURE_UINTR, |
83927c63 | 230 | FEATURE_HRESET, |
632a2f50 | 231 | FEATURE_KL, |
232 | FEATURE_AESKLE, | |
233 | FEATURE_WIDEKL, | |
ca813880 | 234 | FEATURE_AVXVNNI, |
a6841211 | 235 | FEATURE_AVX512FP16, |
8ea29259 ML |
236 | FEATURE_X86_64_BASELINE, |
237 | FEATURE_X86_64_V2, | |
238 | FEATURE_X86_64_V3, | |
239 | FEATURE_X86_64_V4, | |
1890f2f0 L |
240 | CPU_FEATURE_MAX |
241 | }; | |
242 | ||
243 | /* Size of __cpu_features2 array in libgcc/config/i386/cpuinfo.c. */ | |
244 | #define SIZE_OF_CPU_FEATURES ((CPU_FEATURE_MAX - 1) / 32) | |
245 | ||
3fb2c2f4 L |
246 | /* These are the values for vendor types, cpu types and subtypes. Cpu |
247 | types and subtypes should be subtracted by the corresponding start | |
248 | value. */ | |
249 | ||
250 | #define M_CPU_TYPE_START (BUILTIN_VENDOR_MAX) | |
251 | #define M_CPU_SUBTYPE_START \ | |
252 | (M_CPU_TYPE_START + BUILTIN_CPU_TYPE_MAX) | |
253 | #define M_VENDOR(a) (a) | |
254 | #define M_CPU_TYPE(a) (M_CPU_TYPE_START + a) | |
255 | #define M_CPU_SUBTYPE(a) (M_CPU_SUBTYPE_START + a) |