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Commit | Line | Data |
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43e9d192 | 1 | ; Machine description for AArch64 architecture. |
a5544970 | 2 | ; Copyright (C) 2009-2019 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ; Contributed by ARM Ltd. |
4 | ; | |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it | |
8 | ; under the terms of the GNU General Public License as published by | |
9 | ; the Free Software Foundation; either version 3, or (at your option) | |
10 | ; any later version. | |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but | |
13 | ; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ; General Public License for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
18 | ; along with GCC; see the file COPYING3. If not see | |
19 | ; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | HeaderInclude | |
22 | config/aarch64/aarch64-opts.h | |
23 | ||
361fb3ee KT |
24 | TargetVariable |
25 | enum aarch64_processor explicit_tune_core = aarch64_none | |
26 | ||
27 | TargetVariable | |
28 | enum aarch64_arch explicit_arch = aarch64_no_arch | |
29 | ||
30 | TargetSave | |
31 | const char *x_aarch64_override_tune_string | |
32 | ||
33 | TargetVariable | |
34 | unsigned long aarch64_isa_flags = 0 | |
35 | ||
43e9d192 IB |
36 | ; The TLS dialect names to use with -mtls-dialect. |
37 | ||
38 | Enum | |
39 | Name(tls_type) Type(enum aarch64_tls_type) | |
40 | The possible TLS dialects: | |
41 | ||
42 | EnumValue | |
43 | Enum(tls_type) String(trad) Value(TLS_TRADITIONAL) | |
44 | ||
45 | EnumValue | |
46 | Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) | |
47 | ||
48 | ; The code model option names for -mcmodel. | |
49 | ||
50 | Enum | |
51 | Name(cmodel) Type(enum aarch64_code_model) | |
52 | The code model option names for -mcmodel: | |
53 | ||
54 | EnumValue | |
55 | Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY) | |
56 | ||
57 | EnumValue | |
58 | Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL) | |
59 | ||
60 | EnumValue | |
61 | Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) | |
62 | ||
43e9d192 IB |
63 | mbig-endian |
64 | Target Report RejectNegative Mask(BIG_END) | |
a7b2e184 | 65 | Assume target CPU is configured as big endian. |
43e9d192 IB |
66 | |
67 | mgeneral-regs-only | |
361fb3ee | 68 | Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save |
a7b2e184 | 69 | Generate code which uses only the general registers. |
43e9d192 | 70 | |
75cf1494 | 71 | mfix-cortex-a53-835769 |
361fb3ee | 72 | Target Report Var(aarch64_fix_a53_err835769) Init(2) Save |
a7b2e184 | 73 | Workaround for ARM Cortex-A53 Erratum number 835769. |
75cf1494 | 74 | |
bf05ef76 | 75 | mfix-cortex-a53-843419 |
48bb1a55 | 76 | Target Report Var(aarch64_fix_a53_err843419) Init(2) Save |
a7b2e184 | 77 | Workaround for ARM Cortex-A53 Erratum number 843419. |
bf05ef76 | 78 | |
43e9d192 IB |
79 | mlittle-endian |
80 | Target Report RejectNegative InverseMask(BIG_END) | |
a7b2e184 | 81 | Assume target CPU is configured as little endian. |
43e9d192 IB |
82 | |
83 | mcmodel= | |
361fb3ee | 84 | Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save |
a7b2e184 | 85 | Specify the code model. |
43e9d192 IB |
86 | |
87 | mstrict-align | |
675d044c | 88 | Target Report Mask(STRICT_ALIGN) Save |
a7b2e184 | 89 | Don't assume that unaligned accesses are handled by the system. |
43e9d192 IB |
90 | |
91 | momit-leaf-frame-pointer | |
361fb3ee | 92 | Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save |
a7b2e184 | 93 | Omit the frame pointer in leaf functions. |
43e9d192 IB |
94 | |
95 | mtls-dialect= | |
361fb3ee | 96 | Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save |
a7b2e184 | 97 | Specify TLS dialect. |
43e9d192 | 98 | |
5eee3c34 JW |
99 | mtls-size= |
100 | Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size) | |
101 | Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. | |
102 | ||
103 | Enum | |
104 | Name(aarch64_tls_size) Type(int) | |
105 | ||
106 | EnumValue | |
107 | Enum(aarch64_tls_size) String(12) Value(12) | |
108 | ||
109 | EnumValue | |
110 | Enum(aarch64_tls_size) String(24) Value(24) | |
111 | ||
112 | EnumValue | |
113 | Enum(aarch64_tls_size) String(32) Value(32) | |
114 | ||
115 | EnumValue | |
116 | Enum(aarch64_tls_size) String(48) Value(48) | |
117 | ||
43e9d192 | 118 | march= |
608df31f | 119 | Target RejectNegative ToLower Joined Var(aarch64_arch_string) |
266c2b54 | 120 | Use features of architecture ARCH. |
43e9d192 IB |
121 | |
122 | mcpu= | |
608df31f | 123 | Target RejectNegative ToLower Joined Var(aarch64_cpu_string) |
266c2b54 | 124 | Use features of and optimize for CPU. |
43e9d192 IB |
125 | |
126 | mtune= | |
608df31f | 127 | Target RejectNegative ToLower Joined Var(aarch64_tune_string) |
266c2b54 | 128 | Optimize for CPU. |
17a819cb YZ |
129 | |
130 | mabi= | |
131 | Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT) | |
266c2b54 | 132 | Generate code that conforms to the specified ABI. |
17a819cb | 133 | |
8dec06f2 JG |
134 | moverride= |
135 | Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) | |
266c2b54 | 136 | -moverride=<string> Power users only! Override CPU optimization parameters. |
8dec06f2 | 137 | |
17a819cb YZ |
138 | Enum |
139 | Name(aarch64_abi) Type(int) | |
140 | Known AArch64 ABIs (for use with the -mabi= option): | |
141 | ||
142 | EnumValue | |
143 | Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32) | |
144 | ||
145 | EnumValue | |
146 | Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) | |
b4f50fd4 RR |
147 | |
148 | mpc-relative-literal-loads | |
9ee6540a | 149 | Target Report Save Var(pcrelative_literal_loads) Init(2) Save |
b4f50fd4 | 150 | PC relative literal loads. |
a6fc00da | 151 | |
db58fd89 JW |
152 | msign-return-address= |
153 | Target RejectNegative Report Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save | |
154 | Select return address signing scope. | |
155 | ||
156 | Enum | |
157 | Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type) | |
158 | Supported AArch64 return address signing scope (for use with -msign-return-address= option): | |
159 | ||
160 | EnumValue | |
161 | Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE) | |
162 | ||
163 | EnumValue | |
164 | Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF) | |
165 | ||
166 | EnumValue | |
167 | Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL) | |
168 | ||
a6fc00da | 169 | mlow-precision-recip-sqrt |
88e25f47 | 170 | Target Var(flag_mrecip_low_precision_sqrt) Optimization |
98daafa0 EM |
171 | Enable the reciprocal square root approximation. Enabling this reduces |
172 | precision of reciprocal square root results to about 16 bits for | |
173 | single precision and to 32 bits for double precision. | |
174 | ||
175 | mlow-precision-sqrt | |
88e25f47 | 176 | Target Var(flag_mlow_precision_sqrt) Optimization |
98daafa0 EM |
177 | Enable the square root approximation. Enabling this reduces |
178 | precision of square root results to about 16 bits for | |
179 | single precision and to 32 bits for double precision. | |
180 | If enabled, it implies -mlow-precision-recip-sqrt. | |
79a2bc2d EM |
181 | |
182 | mlow-precision-div | |
88e25f47 | 183 | Target Var(flag_mlow_precision_div) Optimization |
79a2bc2d EM |
184 | Enable the division approximation. Enabling this reduces |
185 | precision of division results to about 16 bits for | |
186 | single precision and to 32 bits for double precision. | |
c10e3d7f | 187 | |
43cacb12 RS |
188 | Enum |
189 | Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum) | |
190 | The possible SVE vector lengths: | |
191 | ||
192 | EnumValue | |
193 | Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE) | |
194 | ||
195 | EnumValue | |
196 | Enum(sve_vector_bits) String(128) Value(SVE_128) | |
197 | ||
198 | EnumValue | |
199 | Enum(sve_vector_bits) String(256) Value(SVE_256) | |
200 | ||
201 | EnumValue | |
202 | Enum(sve_vector_bits) String(512) Value(SVE_512) | |
203 | ||
204 | EnumValue | |
205 | Enum(sve_vector_bits) String(1024) Value(SVE_1024) | |
206 | ||
207 | EnumValue | |
208 | Enum(sve_vector_bits) String(2048) Value(SVE_2048) | |
209 | ||
210 | msve-vector-bits= | |
211 | Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE) | |
266c2b54 | 212 | -msve-vector-bits=<number> Set the number of bits in an SVE vector register to N. |
43cacb12 | 213 | |
c10e3d7f | 214 | mverbose-cost-dump |
88e25f47 | 215 | Target Undocumented Var(flag_aarch64_verbose_cost) |
d1132c1b | 216 | Enables verbose cost model dumping in the debug dump files. |
3b0c2502 RE |
217 | |
218 | mtrack-speculation | |
219 | Target Var(aarch64_track_speculation) | |
220 | Generate code to track when the CPU might be speculating incorrectly. |