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43e9d192 | 1 | ;; Machine description for AArch64 architecture. |
83ffe9cd | 2 | ;; Copyright (C) 2009-2023 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; ------------------------------------------------------------------- | |
22 | ;; Mode Iterators | |
23 | ;; ------------------------------------------------------------------- | |
24 | ||
865257c4 RS |
25 | ;; Condition-code iterators. |
26 | (define_mode_iterator CC_ONLY [CC]) | |
27 | (define_mode_iterator CCFP_CCFPE [CCFP CCFPE]) | |
43e9d192 IB |
28 | |
29 | ;; Iterator for General Purpose Integer registers (32- and 64-bit modes) | |
30 | (define_mode_iterator GPI [SI DI]) | |
31 | ||
d7f33f07 JW |
32 | ;; Iterator for HI, SI, DI, some instructions can only work on these modes. |
33 | (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) | |
34 | ||
4a2095eb RH |
35 | ;; "Iterator" for just TI -- features like @pattern only work with iterators. |
36 | (define_mode_iterator JUST_TI [TI]) | |
37 | ||
43e9d192 IB |
38 | ;; Iterator for QI and HI modes |
39 | (define_mode_iterator SHORT [QI HI]) | |
40 | ||
624d0f07 RS |
41 | ;; Iterators for single modes, for "@" patterns. |
42 | (define_mode_iterator SI_ONLY [SI]) | |
43 | (define_mode_iterator DI_ONLY [DI]) | |
44 | ||
43e9d192 IB |
45 | ;; Iterator for all integer modes (up to 64-bit) |
46 | (define_mode_iterator ALLI [QI HI SI DI]) | |
47 | ||
c0111dc4 RE |
48 | ;; Iterator for all integer modes (up to 128-bit) |
49 | (define_mode_iterator ALLI_TI [QI HI SI DI TI]) | |
50 | ||
43e9d192 IB |
51 | ;; Iterator for all integer modes that can be extended (up to 64-bit) |
52 | (define_mode_iterator ALLX [QI HI SI]) | |
53 | ||
54 | ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) | |
55 | (define_mode_iterator GPF [SF DF]) | |
56 | ||
d7f33f07 JW |
57 | ;; Iterator for all scalar floating point modes (HF, SF, DF) |
58 | (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) | |
59 | ||
90e6443f TC |
60 | ;; Iterator for all scalar floating point modes (HF, SF, DF) |
61 | (define_mode_iterator GPF_HF [HF SF DF]) | |
62 | ||
abbe1ed2 SMW |
63 | ;; Iterator for all 16-bit scalar floating point modes (HF, BF) |
64 | (define_mode_iterator HFBF [HF BF]) | |
65 | ||
abbe1ed2 | 66 | ;; Iterator for all scalar floating point modes suitable for moving, including |
0dc8e1e7 CL |
67 | ;; special BF type and decimal floating point types (HF, SF, DF, TF, BF, |
68 | ;; SD, DD and TD) | |
69 | (define_mode_iterator GPF_TF_F16_MOV [HF BF SF DF TF SD DD TD]) | |
70 | ||
71 | ;; Iterator for scalar 32bit fp modes (SF, SD) | |
72 | (define_mode_iterator SFD [SD SF]) | |
73 | ||
74 | ;; Iterator for scalar 64bit fp modes (DF, DD) | |
75 | (define_mode_iterator DFD [DD DF]) | |
76 | ||
77 | ;; Iterator for scalar 128bit fp modes (TF, TD) | |
78 | (define_mode_iterator TFD [TD TF]) | |
abbe1ed2 | 79 | |
922f9c25 AL |
80 | ;; Double vector modes. |
81 | (define_mode_iterator VDF [V2SF V4HF]) | |
82 | ||
0dc8e1e7 CL |
83 | ;; Iterator for all scalar floating point modes (SF, DF, TF, SD, DD, and TD) |
84 | (define_mode_iterator GPF_TF [SF DF TF SD DD TD]) | |
b4f50fd4 | 85 | |
43cacb12 | 86 | ;; Integer Advanced SIMD modes. |
43e9d192 IB |
87 | (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) |
88 | ||
43cacb12 | 89 | ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes. |
43e9d192 IB |
90 | (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) |
91 | ||
43cacb12 RS |
92 | ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD |
93 | ;; integer modes; 64-bit scalar integer mode. | |
43e9d192 IB |
94 | (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) |
95 | ||
96 | ;; Double vector modes. | |
e603cd43 | 97 | (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF]) |
43e9d192 | 98 | |
abbe1ed2 SMW |
99 | ;; Double vector modes suitable for moving. Includes BFmode. |
100 | (define_mode_iterator VDMOV [V8QI V4HI V4HF V4BF V2SI V2SF]) | |
101 | ||
f824216c KT |
102 | ;; 64-bit modes for operations that implicitly clear the top bits of a Q reg. |
103 | (define_mode_iterator VDZ [V8QI V4HI V4HF V4BF V2SI V2SF DI DF]) | |
104 | ||
dfe1da23 JW |
105 | ;; All modes stored in registers d0-d31. |
106 | (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF]) | |
107 | ||
108 | ;; Copy of the above. | |
5dbaf485 | 109 | (define_mode_iterator DREG2 [DREG]) |
dfe1da23 | 110 | |
c69db3ef KT |
111 | ;; Advanced SIMD modes for integer divides. |
112 | (define_mode_iterator VQDIV [V4SI V2DI]) | |
113 | ||
cd91a084 PW |
114 | ;; All modes suitable to store/load pair (2 elements) using STP/LDP. |
115 | (define_mode_iterator VP_2E [V2SI V2SF V2DI V2DF]) | |
116 | ||
43cacb12 | 117 | ;; Advanced SIMD, 64-bit container, all integer modes. |
43e9d192 IB |
118 | (define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) |
119 | ||
120 | ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes | |
121 | (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
122 | ||
123 | ;; Quad vector modes. | |
e603cd43 | 124 | (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF]) |
43e9d192 | 125 | |
9f5361c8 | 126 | ;; Copy of the above. |
5dbaf485 | 127 | (define_mode_iterator VQ2 [VQ]) |
9f5361c8 | 128 | |
abbe1ed2 SMW |
129 | ;; Quad vector modes suitable for moving. Includes BFmode. |
130 | (define_mode_iterator VQMOV [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF]) | |
131 | ||
132 | ;; VQMOV without 2-element modes. | |
133 | (define_mode_iterator VQMOV_NO2E [V16QI V8HI V4SI V8HF V8BF V4SF]) | |
134 | ||
e1b218d1 JW |
135 | ;; Double integer vector modes. |
136 | (define_mode_iterator VD_I [V8QI V4HI V2SI DI]) | |
137 | ||
d21052eb TC |
138 | ;; Quad integer vector modes. |
139 | (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI]) | |
140 | ||
51437269 | 141 | ;; VQ without 2 element modes. |
e603cd43 | 142 | (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF]) |
51437269 | 143 | |
5ba864c5 AC |
144 | ;; 2 element quad vector modes. |
145 | (define_mode_iterator VQ_2E [V2DI V2DF]) | |
146 | ||
f275d73a SMW |
147 | ;; BFmode vector modes. |
148 | (define_mode_iterator VBF [V4BF V8BF]) | |
149 | ||
28514dda YZ |
150 | ;; This mode iterator allows :P to be used for patterns that operate on |
151 | ;; addresses in different modes. In LP64, only DI will match, while in | |
152 | ;; ILP32, either can match. | |
153 | (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") | |
154 | (DI "ptr_mode == DImode || Pmode == DImode")]) | |
155 | ||
43e9d192 IB |
156 | ;; This mode iterator allows :PTR to be used for patterns that operate on |
157 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
28514dda | 158 | (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) |
43e9d192 | 159 | |
43cacb12 | 160 | ;; Advanced SIMD Float modes suitable for moving, loading and storing. |
8ea6c1b8 MI |
161 | (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF |
162 | V4BF V8BF]) | |
862abc04 | 163 | |
43cacb12 | 164 | ;; Advanced SIMD Float modes. |
43e9d192 | 165 | (define_mode_iterator VDQF [V2SF V4SF V2DF]) |
daef0a8c JW |
166 | (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") |
167 | (V8HF "TARGET_SIMD_F16INST") | |
168 | V2SF V4SF V2DF]) | |
43e9d192 | 169 | |
43cacb12 | 170 | ;; Advanced SIMD Float modes, and DF. |
b0d9aac8 | 171 | (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) |
daef0a8c JW |
172 | (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") |
173 | (V8HF "TARGET_SIMD_F16INST") | |
174 | V2SF V4SF V2DF DF]) | |
d7f33f07 JW |
175 | (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") |
176 | (V8HF "TARGET_SIMD_F16INST") | |
177 | V2SF V4SF V2DF | |
178 | (HF "TARGET_SIMD_F16INST") | |
179 | SF DF]) | |
f421c516 | 180 | |
10bd1d96 KT |
181 | ;; Scalar and vetor modes for SF, DF. |
182 | (define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF]) | |
183 | ||
43cacb12 | 184 | ;; Advanced SIMD single Float modes. |
828e70c1 JG |
185 | (define_mode_iterator VDQSF [V2SF V4SF]) |
186 | ||
03873eb9 AL |
187 | ;; Quad vector Float modes with half/single elements. |
188 | (define_mode_iterator VQ_HSF [V8HF V4SF]) | |
189 | ||
fc21784d JG |
190 | ;; Modes suitable to use as the return type of a vcond expression. |
191 | (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) | |
192 | ||
43cacb12 | 193 | ;; All scalar and Advanced SIMD Float modes. |
889b9412 JG |
194 | (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) |
195 | ||
43cacb12 | 196 | ;; Advanced SIMD Float modes with 2 elements. |
a40c22c3 | 197 | (define_mode_iterator V2F [V2SF V2DF]) |
43e9d192 | 198 | |
43cacb12 | 199 | ;; All Advanced SIMD modes on which we support any arithmetic operations. |
43e9d192 IB |
200 | (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) |
201 | ||
a40c22c3 | 202 | ;; All Advanced SIMD modes suitable for moving, loading, and storing. |
71a11456 | 203 | (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI |
8ea6c1b8 | 204 | V4HF V8HF V4BF V8BF V2SF V4SF V2DF]) |
71a11456 | 205 | |
88119b46 KT |
206 | ;; The VALL_F16 modes except the 128-bit 2-element ones. |
207 | (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI | |
208 | V4HF V8HF V2SF V4SF]) | |
209 | ||
43cacb12 | 210 | ;; All Advanced SIMD modes barring HF modes, plus DI. |
a50344cb TB |
211 | (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) |
212 | ||
43cacb12 | 213 | ;; All Advanced SIMD modes and DI. |
71a11456 | 214 | (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI |
8ea6c1b8 | 215 | V4HF V8HF V4BF V8BF V2SF V4SF V2DF DI]) |
71a11456 | 216 | |
43cacb12 | 217 | ;; All Advanced SIMD modes, plus DI and DF. |
e603cd43 | 218 | (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI V4BF V8BF |
7c369485 | 219 | V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) |
46e778c4 | 220 | |
6372b05e JW |
221 | ;; All Advanced SIMD polynomial modes and DI. |
222 | (define_mode_iterator VALLP [V8QI V16QI V4HI V8HI V2DI DI]) | |
223 | ||
1716ddd1 JW |
224 | ;; All Advanced SIMD polynomial modes. |
225 | (define_mode_iterator VALLP_NO_DI [V8QI V16QI V4HI V8HI V2DI]) | |
226 | ||
43cacb12 | 227 | ;; Advanced SIMD modes for Integer reduction across lanes. |
92835317 TB |
228 | (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) |
229 | ||
43cacb12 | 230 | ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. |
92835317 | 231 | (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) |
43e9d192 | 232 | |
9921bbf9 WD |
233 | ;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended). |
234 | (define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI]) | |
235 | ||
cb995de6 KT |
236 | ;; Advanced SIMD modes for Integer widening reduction across lanes. |
237 | (define_mode_iterator VDQV_L [V8QI V16QI V4HI V8HI V4SI V2SI]) | |
238 | ||
43e9d192 IB |
239 | ;; All double integer narrow-able modes. |
240 | (define_mode_iterator VDN [V4HI V2SI DI]) | |
241 | ||
242 | ;; All quad integer narrow-able modes. | |
243 | (define_mode_iterator VQN [V8HI V4SI V2DI]) | |
244 | ||
43cacb12 RS |
245 | ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit |
246 | ;; integer modes | |
43e9d192 IB |
247 | (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) |
248 | ||
249 | ;; All quad integer widen-able modes. | |
250 | (define_mode_iterator VQW [V16QI V8HI V4SI]) | |
251 | ||
252 | ;; Double vector modes for combines. | |
e603cd43 | 253 | (define_mode_iterator VDC [V8QI V4HI V4BF V4HF V2SI V2SF DI DF]) |
43e9d192 | 254 | |
83d7e720 RS |
255 | ;; VDC plus SI and SF. |
256 | (define_mode_iterator VDCSIF [V8QI V4HI V4BF V4HF V2SI V2SF SI SF DI DF]) | |
257 | ||
e1b218d1 JW |
258 | ;; Polynomial modes for vector combines. |
259 | (define_mode_iterator VDC_P [V8QI V4HI DI]) | |
260 | ||
43cacb12 | 261 | ;; Advanced SIMD modes except double int. |
43e9d192 | 262 | (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) |
703bbcdf JW |
263 | (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI |
264 | V4HF V8HF V2SF V4SF V2DF]) | |
43e9d192 | 265 | |
43cacb12 | 266 | ;; Advanced SIMD modes for S type. |
58a3bd25 FY |
267 | (define_mode_iterator VDQ_SI [V2SI V4SI]) |
268 | ||
43cacb12 | 269 | ;; Advanced SIMD modes for S and D. |
2644d4d9 JW |
270 | (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) |
271 | ||
43cacb12 | 272 | ;; Advanced SIMD modes for H, S and D. |
33d72b63 JW |
273 | (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") |
274 | (V8HI "TARGET_SIMD_F16INST") | |
275 | V2SI V4SI V2DI]) | |
276 | ||
43cacb12 | 277 | ;; Scalar and Advanced SIMD modes for S and D. |
2644d4d9 JW |
278 | (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) |
279 | ||
43cacb12 | 280 | ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H. |
33d72b63 JW |
281 | (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") |
282 | (V8HI "TARGET_SIMD_F16INST") | |
68ad28c3 JW |
283 | V2SI V4SI V2DI |
284 | (HI "TARGET_SIMD_F16INST") | |
285 | SI DI]) | |
33d72b63 | 286 | |
43cacb12 | 287 | ;; Advanced SIMD modes for Q and H types. |
66adb8eb JG |
288 | (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) |
289 | ||
43cacb12 | 290 | ;; Advanced SIMD modes for H and S types. |
43e9d192 IB |
291 | (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) |
292 | ||
43cacb12 | 293 | ;; Advanced SIMD modes for H, S and D types. |
c7f28cd5 KT |
294 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) |
295 | ||
43cacb12 | 296 | ;; Advanced SIMD and scalar integer modes for H and S. |
43e9d192 IB |
297 | (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) |
298 | ||
43cacb12 | 299 | ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
300 | (define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) |
301 | ||
43cacb12 | 302 | ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
303 | (define_mode_iterator VD_HSI [V4HI V2SI]) |
304 | ||
305 | ;; Scalar 64-bit container: 16, 32-bit integer modes | |
306 | (define_mode_iterator SD_HSI [HI SI]) | |
307 | ||
ddbdb9a3 JW |
308 | ;; Scalar 64-bit container: 16-bit, 32-bit and 64-bit integer modes. |
309 | (define_mode_iterator SD_HSDI [HI SI DI]) | |
310 | ||
43cacb12 | 311 | ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
312 | (define_mode_iterator VQ_HSI [V8HI V4SI]) |
313 | ||
314 | ;; All byte modes. | |
315 | (define_mode_iterator VB [V8QI V16QI]) | |
316 | ||
5e32e83b JW |
317 | ;; 2 and 4 lane SI modes. |
318 | (define_mode_iterator VS [V2SI V4SI]) | |
319 | ||
0dc8e1e7 | 320 | (define_mode_iterator TX [TI TF TD]) |
43e9d192 | 321 | |
947fb34a | 322 | ;; Duplicate of the above |
5dbaf485 | 323 | (define_mode_iterator TX2 [TX]) |
947fb34a | 324 | |
721c0fb3 RS |
325 | (define_mode_iterator VTX [TI TF TD V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF]) |
326 | ||
43cacb12 | 327 | ;; Advanced SIMD opaque structure modes. |
43e9d192 IB |
328 | (define_mode_iterator VSTRUCT [OI CI XI]) |
329 | ||
66f206b8 JW |
330 | ;; Advanced SIMD 64-bit 2-vector structure modes. |
331 | (define_mode_iterator VSTRUCT_2D [V2x8QI V2x4HI V2x2SI V2x1DI | |
332 | V2x4HF V2x2SF V2x1DF V2x4BF]) | |
333 | ||
334 | ;; Advanced SIMD 64-bit 3-vector structure modes. | |
335 | (define_mode_iterator VSTRUCT_3D [V3x8QI V3x4HI V3x2SI V3x1DI | |
336 | V3x4HF V3x2SF V3x1DF V3x4BF]) | |
337 | ||
338 | ;; Advanced SIMD 64-bit 4-vector structure modes. | |
339 | (define_mode_iterator VSTRUCT_4D [V4x8QI V4x4HI V4x2SI V4x1DI | |
340 | V4x4HF V4x2SF V4x1DF V4x4BF]) | |
341 | ||
5dbaf485 RS |
342 | ;; Advanced SIMD 64-bit vector structure modes. |
343 | (define_mode_iterator VSTRUCT_D [VSTRUCT_2D VSTRUCT_3D VSTRUCT_4D]) | |
344 | ||
66f206b8 JW |
345 | ;; Advanced SIMD 64-bit 2-vector structure modes minus V2x1DI and V2x1DF. |
346 | (define_mode_iterator VSTRUCT_2DNX [V2x8QI V2x4HI V2x2SI V2x4HF | |
347 | V2x2SF V2x4BF]) | |
348 | ||
349 | ;; Advanced SIMD 64-bit 3-vector structure modes minus V3x1DI and V3x1DF. | |
350 | (define_mode_iterator VSTRUCT_3DNX [V3x8QI V3x4HI V3x2SI V3x4HF | |
351 | V3x2SF V3x4BF]) | |
352 | ||
353 | ;; Advanced SIMD 64-bit 4-vector structure modes minus V4x1DI and V4x1DF. | |
354 | (define_mode_iterator VSTRUCT_4DNX [V4x8QI V4x4HI V4x2SI V4x4HF | |
355 | V4x2SF V4x4BF]) | |
356 | ||
357 | ;; Advanced SIMD 64-bit structure modes with 64-bit elements. | |
358 | (define_mode_iterator VSTRUCT_DX [V2x1DI V2x1DF V3x1DI V3x1DF V4x1DI V4x1DF]) | |
359 | ||
360 | ;; Advanced SIMD 64-bit 2-vector structure modes with 64-bit elements. | |
361 | (define_mode_iterator VSTRUCT_2DX [V2x1DI V2x1DF]) | |
362 | ||
363 | ;; Advanced SIMD 64-bit 3-vector structure modes with 64-bit elements. | |
364 | (define_mode_iterator VSTRUCT_3DX [V3x1DI V3x1DF]) | |
365 | ||
366 | ;; Advanced SIMD 64-bit 4-vector structure modes with 64-bit elements. | |
367 | (define_mode_iterator VSTRUCT_4DX [V4x1DI V4x1DF]) | |
368 | ||
66f206b8 JW |
369 | ;; Advanced SIMD 128-bit 2-vector structure modes. |
370 | (define_mode_iterator VSTRUCT_2Q [V2x16QI V2x8HI V2x4SI V2x2DI | |
371 | V2x8HF V2x4SF V2x2DF V2x8BF]) | |
372 | ||
373 | ;; Advanced SIMD 128-bit 3-vector structure modes. | |
374 | (define_mode_iterator VSTRUCT_3Q [V3x16QI V3x8HI V3x4SI V3x2DI | |
375 | V3x8HF V3x4SF V3x2DF V3x8BF]) | |
376 | ||
377 | ;; Advanced SIMD 128-bit 4-vector structure modes. | |
378 | (define_mode_iterator VSTRUCT_4Q [V4x16QI V4x8HI V4x4SI V4x2DI | |
379 | V4x8HF V4x4SF V4x2DF V4x8BF]) | |
380 | ||
5dbaf485 RS |
381 | ;; Advanced SIMD 128-bit vector structure modes. |
382 | (define_mode_iterator VSTRUCT_Q [VSTRUCT_2Q VSTRUCT_3Q VSTRUCT_4Q]) | |
383 | ||
66f206b8 | 384 | ;; Advanced SIMD 2-vector structure modes. |
5dbaf485 | 385 | (define_mode_iterator VSTRUCT_2QD [VSTRUCT_2D VSTRUCT_2Q]) |
66f206b8 JW |
386 | |
387 | ;; Advanced SIMD 3-vector structure modes. | |
5dbaf485 | 388 | (define_mode_iterator VSTRUCT_3QD [VSTRUCT_3D VSTRUCT_3Q]) |
66f206b8 JW |
389 | |
390 | ;; Advanced SIMD 4-vector structure modes. | |
5dbaf485 | 391 | (define_mode_iterator VSTRUCT_4QD [VSTRUCT_4D VSTRUCT_4Q]) |
66f206b8 JW |
392 | |
393 | ;; Advanced SIMD vector structure modes. | |
5dbaf485 | 394 | (define_mode_iterator VSTRUCT_QD [VSTRUCT_D VSTRUCT_Q]) |
66f206b8 | 395 | |
43e9d192 | 396 | ;; Double scalar modes |
0dc8e1e7 | 397 | (define_mode_iterator DX [DI DF DD]) |
43e9d192 | 398 | |
dfe1da23 | 399 | ;; Duplicate of the above |
5dbaf485 | 400 | (define_mode_iterator DX2 [DX]) |
dfe1da23 JW |
401 | |
402 | ;; Single scalar modes | |
403 | (define_mode_iterator SX [SI SF]) | |
404 | ||
405 | ;; Duplicate of the above | |
5dbaf485 | 406 | (define_mode_iterator SX2 [SX]) |
dfe1da23 JW |
407 | |
408 | ;; Single and double integer and float modes | |
409 | (define_mode_iterator DSX [DF DI SF SI]) | |
410 | ||
411 | ||
28de75d2 | 412 | ;; Modes available for Advanced SIMD <f>mul operations. |
ab2e8f01 JW |
413 | (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI |
414 | (V4HF "TARGET_SIMD_F16INST") | |
415 | (V8HF "TARGET_SIMD_F16INST") | |
416 | V2SF V4SF V2DF]) | |
779aea46 | 417 | |
28de75d2 RS |
418 | ;; The subset of VMUL for which VCOND is a vector mode. |
419 | (define_mode_iterator VMULD [V4HI V8HI V2SI V4SI | |
420 | (V4HF "TARGET_SIMD_F16INST") | |
421 | (V8HF "TARGET_SIMD_F16INST") | |
422 | V2SF V4SF]) | |
779aea46 | 423 | |
95eb5537 | 424 | ;; Iterators for single modes, for "@" patterns. |
0a09a948 | 425 | (define_mode_iterator VNx16QI_ONLY [VNx16QI]) |
624d0f07 | 426 | (define_mode_iterator VNx8HI_ONLY [VNx8HI]) |
896dff99 | 427 | (define_mode_iterator VNx8BF_ONLY [VNx8BF]) |
95eb5537 | 428 | (define_mode_iterator VNx4SI_ONLY [VNx4SI]) |
0a09a948 | 429 | (define_mode_iterator VNx4SF_ONLY [VNx4SF]) |
624d0f07 | 430 | (define_mode_iterator VNx2DI_ONLY [VNx2DI]) |
95eb5537 RS |
431 | (define_mode_iterator VNx2DF_ONLY [VNx2DF]) |
432 | ||
f75cdd2c RS |
433 | ;; All fully-packed SVE vector modes. |
434 | (define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI | |
02fcd8ac | 435 | VNx8BF VNx8HF VNx4SF VNx2DF]) |
f75cdd2c RS |
436 | |
437 | ;; All fully-packed SVE integer vector modes. | |
438 | (define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI]) | |
43cacb12 | 439 | |
f75cdd2c RS |
440 | ;; All fully-packed SVE floating-point vector modes. |
441 | (define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF]) | |
43cacb12 | 442 | |
0a09a948 RS |
443 | ;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements. |
444 | (define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI]) | |
445 | ||
f75cdd2c RS |
446 | ;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit |
447 | ;; elements. | |
448 | (define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI]) | |
43cacb12 | 449 | |
f75cdd2c | 450 | ;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements. |
02fcd8ac RS |
451 | (define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI |
452 | VNx8BF VNx8HF VNx4SF VNx2DF]) | |
95eb5537 | 453 | |
f75cdd2c RS |
454 | ;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit |
455 | ;; elements. | |
456 | (define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI]) | |
95eb5537 | 457 | |
0a09a948 RS |
458 | ;; Fully-packed SVE integer vector modes that have 16-bit or 32-bit |
459 | ;; elements. | |
460 | (define_mode_iterator SVE_FULL_HSI [VNx8HI VNx4SI]) | |
461 | ||
f75cdd2c RS |
462 | ;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit |
463 | ;; elements. | |
464 | (define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF]) | |
a70965b1 | 465 | |
0a09a948 RS |
466 | ;; Fully-packed SVE integer vector modes that have 16-bit or 64-bit elements. |
467 | (define_mode_iterator SVE_FULL_HDI [VNx8HI VNx2DI]) | |
468 | ||
f75cdd2c RS |
469 | ;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements. |
470 | (define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF]) | |
43cacb12 | 471 | |
f75cdd2c RS |
472 | ;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements. |
473 | (define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI]) | |
bfaa08b7 | 474 | |
f75cdd2c RS |
475 | ;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit |
476 | ;; elements. | |
477 | (define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF]) | |
bfaa08b7 | 478 | |
36696774 RS |
479 | ;; Same, but with the appropriate conditions for FMMLA support. |
480 | (define_mode_iterator SVE_MATMULF [(VNx4SF "TARGET_SVE_F32MM") | |
481 | (VNx2DF "TARGET_SVE_F64MM")]) | |
482 | ||
f75cdd2c RS |
483 | ;; Fully-packed SVE vector modes that have 32-bit elements. |
484 | (define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF]) | |
43cacb12 | 485 | |
f75cdd2c RS |
486 | ;; Fully-packed SVE vector modes that have 64-bit elements. |
487 | (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF]) | |
43cacb12 | 488 | |
6544cb52 RS |
489 | ;; All partial SVE integer modes. |
490 | (define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI | |
491 | VNx4HI VNx2HI | |
492 | VNx2SI]) | |
624d0f07 | 493 | |
cc68f7c2 RS |
494 | ;; All SVE vector modes. |
495 | (define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI | |
496 | VNx8HI VNx4HI VNx2HI | |
497 | VNx8HF VNx4HF VNx2HF | |
6c3ce63b | 498 | VNx8BF VNx4BF VNx2BF |
cc68f7c2 RS |
499 | VNx4SI VNx2SI |
500 | VNx4SF VNx2SF | |
501 | VNx2DI | |
502 | VNx2DF]) | |
503 | ||
1ce9dc26 RS |
504 | ;; All SVE 2-vector modes. |
505 | (define_mode_iterator SVE_FULLx2 [VNx32QI VNx16HI VNx8SI VNx4DI | |
506 | VNx16BF VNx16HF VNx8SF VNx4DF]) | |
507 | ||
508 | ;; All SVE 3-vector modes. | |
509 | (define_mode_iterator SVE_FULLx3 [VNx48QI VNx24HI VNx12SI VNx6DI | |
510 | VNx24BF VNx24HF VNx12SF VNx6DF]) | |
511 | ||
512 | ;; All SVE 4-vector modes. | |
513 | (define_mode_iterator SVE_FULLx4 [VNx64QI VNx32HI VNx16SI VNx8DI | |
514 | VNx32BF VNx32HF VNx16SF VNx8DF]) | |
515 | ||
516 | ;; All SVE vector structure modes. | |
517 | (define_mode_iterator SVE_STRUCT [SVE_FULLx2 SVE_FULLx3 SVE_FULLx4]) | |
518 | ||
519 | ;; All SVE vector and structure modes. | |
520 | (define_mode_iterator SVE_ALL_STRUCT [SVE_ALL SVE_STRUCT]) | |
521 | ||
cc68f7c2 RS |
522 | ;; All SVE integer vector modes. |
523 | (define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI | |
524 | VNx8HI VNx4HI VNx2HI | |
525 | VNx4SI VNx2SI | |
526 | VNx2DI]) | |
527 | ||
e58703e2 RS |
528 | ;; SVE integer vector modes whose elements are 16 bits or wider. |
529 | (define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI | |
530 | VNx4SI VNx2SI | |
531 | VNx2DI]) | |
532 | ||
f8186eea | 533 | ;; SVE modes with 2 or 4 elements. |
6c3ce63b RS |
534 | (define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2BF VNx2SI VNx2SF |
535 | VNx2DI VNx2DF | |
536 | VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF]) | |
f8186eea | 537 | |
3f8b0bba RS |
538 | ;; SVE integer modes with 2 or 4 elements. |
539 | (define_mode_iterator SVE_24I [VNx2QI VNx2HI VNx2SI VNx2DI | |
540 | VNx4QI VNx4HI VNx4SI]) | |
541 | ||
f8186eea | 542 | ;; SVE modes with 2 elements. |
6c3ce63b RS |
543 | (define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2BF |
544 | VNx2SI VNx2SF VNx2DI VNx2DF]) | |
f8186eea | 545 | |
87a80d27 RS |
546 | ;; SVE integer modes with 2 elements, excluding the widest element. |
547 | (define_mode_iterator SVE_2BHSI [VNx2QI VNx2HI VNx2SI]) | |
548 | ||
549 | ;; SVE integer modes with 2 elements, excluding the narrowest element. | |
550 | (define_mode_iterator SVE_2HSDI [VNx2HI VNx2SI VNx2DI]) | |
551 | ||
f8186eea | 552 | ;; SVE modes with 4 elements. |
6c3ce63b | 553 | (define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF]) |
f8186eea | 554 | |
87a80d27 RS |
555 | ;; SVE integer modes with 4 elements, excluding the widest element. |
556 | (define_mode_iterator SVE_4BHI [VNx4QI VNx4HI]) | |
557 | ||
558 | ;; SVE integer modes with 4 elements, excluding the narrowest element. | |
559 | (define_mode_iterator SVE_4HSI [VNx4HI VNx4SI]) | |
560 | ||
0a09a948 RS |
561 | ;; SVE integer modes that can form the input to an SVE2 PMULL[BT] instruction. |
562 | (define_mode_iterator SVE2_PMULL_PAIR_I [VNx16QI VNx4SI | |
563 | (VNx2DI "TARGET_SVE2_AES")]) | |
564 | ||
624d0f07 RS |
565 | ;; Modes involved in extending or truncating SVE data, for 8 elements per |
566 | ;; 128-bit block. | |
567 | (define_mode_iterator VNx8_NARROW [VNx8QI]) | |
568 | (define_mode_iterator VNx8_WIDE [VNx8HI]) | |
569 | ||
570 | ;; ...same for 4 elements per 128-bit block. | |
571 | (define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI]) | |
572 | (define_mode_iterator VNx4_WIDE [VNx4SI]) | |
573 | ||
574 | ;; ...same for 2 elements per 128-bit block. | |
575 | (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI]) | |
576 | (define_mode_iterator VNx2_WIDE [VNx2DI]) | |
577 | ||
43cacb12 RS |
578 | ;; All SVE predicate modes. |
579 | (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI]) | |
580 | ||
581 | ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements. | |
582 | (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI]) | |
583 | ||
624d0f07 RS |
584 | ;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements. |
585 | (define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI]) | |
586 | ||
1f520d34 DB |
587 | ;; Bfloat16 modes to which V4SF can be converted |
588 | (define_mode_iterator V4SF_TO_BF [V4BF V8BF]) | |
589 | ||
43e9d192 IB |
590 | ;; ------------------------------------------------------------------ |
591 | ;; Unspec enumerations for Advance SIMD. These could well go into | |
592 | ;; aarch64.md but for their use in int_iterators here. | |
593 | ;; ------------------------------------------------------------------ | |
594 | ||
595 | (define_c_enum "unspec" | |
596 | [ | |
597 | UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. | |
598 | UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. | |
285398d2 | 599 | UNSPEC_ABS ; Used in aarch64-simd.md. |
998eaf97 JG |
600 | UNSPEC_FMAX ; Used in aarch64-simd.md. |
601 | UNSPEC_FMAXNMV ; Used in aarch64-simd.md. | |
43e9d192 | 602 | UNSPEC_FMAXV ; Used in aarch64-simd.md. |
998eaf97 JG |
603 | UNSPEC_FMIN ; Used in aarch64-simd.md. |
604 | UNSPEC_FMINNMV ; Used in aarch64-simd.md. | |
43e9d192 IB |
605 | UNSPEC_FMINV ; Used in aarch64-simd.md. |
606 | UNSPEC_FADDV ; Used in aarch64-simd.md. | |
f5156c3e | 607 | UNSPEC_ADDV ; Used in aarch64-simd.md. |
43e9d192 IB |
608 | UNSPEC_SMAXV ; Used in aarch64-simd.md. |
609 | UNSPEC_SMINV ; Used in aarch64-simd.md. | |
610 | UNSPEC_UMAXV ; Used in aarch64-simd.md. | |
611 | UNSPEC_UMINV ; Used in aarch64-simd.md. | |
612 | UNSPEC_SHADD ; Used in aarch64-simd.md. | |
613 | UNSPEC_UHADD ; Used in aarch64-simd.md. | |
614 | UNSPEC_SRHADD ; Used in aarch64-simd.md. | |
615 | UNSPEC_URHADD ; Used in aarch64-simd.md. | |
616 | UNSPEC_SHSUB ; Used in aarch64-simd.md. | |
617 | UNSPEC_UHSUB ; Used in aarch64-simd.md. | |
43e9d192 IB |
618 | UNSPEC_SQDMULH ; Used in aarch64-simd.md. |
619 | UNSPEC_SQRDMULH ; Used in aarch64-simd.md. | |
620 | UNSPEC_PMUL ; Used in aarch64-simd.md. | |
496ea87d | 621 | UNSPEC_FMULX ; Used in aarch64-simd.md. |
43e9d192 IB |
622 | UNSPEC_USQADD ; Used in aarch64-simd.md. |
623 | UNSPEC_SUQADD ; Used in aarch64-simd.md. | |
43e9d192 IB |
624 | UNSPEC_SSRA ; Used in aarch64-simd.md. |
625 | UNSPEC_USRA ; Used in aarch64-simd.md. | |
43e9d192 IB |
626 | UNSPEC_SRSHR ; Used in aarch64-simd.md. |
627 | UNSPEC_URSHR ; Used in aarch64-simd.md. | |
628 | UNSPEC_SQSHLU ; Used in aarch64-simd.md. | |
629 | UNSPEC_SQSHL ; Used in aarch64-simd.md. | |
630 | UNSPEC_UQSHL ; Used in aarch64-simd.md. | |
43e9d192 IB |
631 | UNSPEC_SSHL ; Used in aarch64-simd.md. |
632 | UNSPEC_USHL ; Used in aarch64-simd.md. | |
633 | UNSPEC_SRSHL ; Used in aarch64-simd.md. | |
634 | UNSPEC_URSHL ; Used in aarch64-simd.md. | |
635 | UNSPEC_SQRSHL ; Used in aarch64-simd.md. | |
636 | UNSPEC_UQRSHL ; Used in aarch64-simd.md. | |
43e9d192 IB |
637 | UNSPEC_SSLI ; Used in aarch64-simd.md. |
638 | UNSPEC_USLI ; Used in aarch64-simd.md. | |
639 | UNSPEC_SSRI ; Used in aarch64-simd.md. | |
640 | UNSPEC_USRI ; Used in aarch64-simd.md. | |
641 | UNSPEC_SSHLL ; Used in aarch64-simd.md. | |
642 | UNSPEC_USHLL ; Used in aarch64-simd.md. | |
643 | UNSPEC_ADDP ; Used in aarch64-simd.md. | |
88b08073 | 644 | UNSPEC_TBL ; Used in vector permute patterns. |
9371aecc | 645 | UNSPEC_TBX ; Used in vector permute patterns. |
88b08073 | 646 | UNSPEC_CONCAT ; Used in vector permute patterns. |
3f8334a5 RS |
647 | |
648 | ;; The following permute unspecs are generated directly by | |
649 | ;; aarch64_expand_vec_perm_const, so any changes to the underlying | |
650 | ;; instructions would need a corresponding change there. | |
cc4d934f JG |
651 | UNSPEC_ZIP1 ; Used in vector permute patterns. |
652 | UNSPEC_ZIP2 ; Used in vector permute patterns. | |
653 | UNSPEC_UZP1 ; Used in vector permute patterns. | |
654 | UNSPEC_UZP2 ; Used in vector permute patterns. | |
655 | UNSPEC_TRN1 ; Used in vector permute patterns. | |
656 | UNSPEC_TRN2 ; Used in vector permute patterns. | |
3f8334a5 | 657 | UNSPEC_EXT ; Used in vector permute patterns. |
923fcec3 AL |
658 | UNSPEC_REV64 ; Used in vector reverse patterns (permute). |
659 | UNSPEC_REV32 ; Used in vector reverse patterns (permute). | |
660 | UNSPEC_REV16 ; Used in vector reverse patterns (permute). | |
3f8334a5 | 661 | |
5a7a4e80 TB |
662 | UNSPEC_AESE ; Used in aarch64-simd.md. |
663 | UNSPEC_AESD ; Used in aarch64-simd.md. | |
664 | UNSPEC_AESMC ; Used in aarch64-simd.md. | |
665 | UNSPEC_AESIMC ; Used in aarch64-simd.md. | |
30442682 TB |
666 | UNSPEC_SHA1C ; Used in aarch64-simd.md. |
667 | UNSPEC_SHA1M ; Used in aarch64-simd.md. | |
668 | UNSPEC_SHA1P ; Used in aarch64-simd.md. | |
669 | UNSPEC_SHA1H ; Used in aarch64-simd.md. | |
670 | UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. | |
671 | UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. | |
b9cb0a44 TB |
672 | UNSPEC_SHA256H ; Used in aarch64-simd.md. |
673 | UNSPEC_SHA256H2 ; Used in aarch64-simd.md. | |
674 | UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. | |
675 | UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. | |
7baa225d TB |
676 | UNSPEC_PMULL ; Used in aarch64-simd.md. |
677 | UNSPEC_PMULL2 ; Used in aarch64-simd.md. | |
668046d1 | 678 | UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. |
9c004c58 | 679 | UNSPEC_VEC_SHR ; Used in aarch64-simd.md. |
57b26d65 MW |
680 | UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. |
681 | UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. | |
202d0c11 DS |
682 | UNSPEC_FMAXNM ; Used in aarch64-simd.md. |
683 | UNSPEC_FMINNM ; Used in aarch64-simd.md. | |
7a08d813 TC |
684 | UNSPEC_SDOT ; Used in aarch64-simd.md. |
685 | UNSPEC_UDOT ; Used in aarch64-simd.md. | |
27086ea3 MC |
686 | UNSPEC_SM3SS1 ; Used in aarch64-simd.md. |
687 | UNSPEC_SM3TT1A ; Used in aarch64-simd.md. | |
688 | UNSPEC_SM3TT1B ; Used in aarch64-simd.md. | |
689 | UNSPEC_SM3TT2A ; Used in aarch64-simd.md. | |
690 | UNSPEC_SM3TT2B ; Used in aarch64-simd.md. | |
691 | UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md. | |
692 | UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md. | |
693 | UNSPEC_SM4E ; Used in aarch64-simd.md. | |
694 | UNSPEC_SM4EKEY ; Used in aarch64-simd.md. | |
695 | UNSPEC_SHA512H ; Used in aarch64-simd.md. | |
696 | UNSPEC_SHA512H2 ; Used in aarch64-simd.md. | |
697 | UNSPEC_SHA512SU0 ; Used in aarch64-simd.md. | |
698 | UNSPEC_SHA512SU1 ; Used in aarch64-simd.md. | |
699 | UNSPEC_FMLAL ; Used in aarch64-simd.md. | |
700 | UNSPEC_FMLSL ; Used in aarch64-simd.md. | |
701 | UNSPEC_FMLAL2 ; Used in aarch64-simd.md. | |
702 | UNSPEC_FMLSL2 ; Used in aarch64-simd.md. | |
624d0f07 | 703 | UNSPEC_ADR ; Used in aarch64-sve.md. |
43cacb12 | 704 | UNSPEC_SEL ; Used in aarch64-sve.md. |
624d0f07 RS |
705 | UNSPEC_BRKA ; Used in aarch64-sve.md. |
706 | UNSPEC_BRKB ; Used in aarch64-sve.md. | |
707 | UNSPEC_BRKN ; Used in aarch64-sve.md. | |
708 | UNSPEC_BRKPA ; Used in aarch64-sve.md. | |
709 | UNSPEC_BRKPB ; Used in aarch64-sve.md. | |
710 | UNSPEC_PFIRST ; Used in aarch64-sve.md. | |
711 | UNSPEC_PNEXT ; Used in aarch64-sve.md. | |
712 | UNSPEC_CNTP ; Used in aarch64-sve.md. | |
713 | UNSPEC_SADDV ; Used in aarch64-sve.md. | |
714 | UNSPEC_UADDV ; Used in aarch64-sve.md. | |
898f07b0 RS |
715 | UNSPEC_ANDV ; Used in aarch64-sve.md. |
716 | UNSPEC_IORV ; Used in aarch64-sve.md. | |
717 | UNSPEC_XORV ; Used in aarch64-sve.md. | |
43cacb12 RS |
718 | UNSPEC_ANDF ; Used in aarch64-sve.md. |
719 | UNSPEC_IORF ; Used in aarch64-sve.md. | |
720 | UNSPEC_XORF ; Used in aarch64-sve.md. | |
d7a09c44 RS |
721 | UNSPEC_REVB ; Used in aarch64-sve.md. |
722 | UNSPEC_REVH ; Used in aarch64-sve.md. | |
723 | UNSPEC_REVW ; Used in aarch64-sve.md. | |
6c3ce63b | 724 | UNSPEC_REVBHW ; Used in aarch64-sve.md. |
11e9443f RS |
725 | UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md. |
726 | UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md. | |
624d0f07 RS |
727 | UNSPEC_FMLA ; Used in aarch64-sve.md. |
728 | UNSPEC_FMLS ; Used in aarch64-sve.md. | |
729 | UNSPEC_FEXPA ; Used in aarch64-sve.md. | |
36696774 | 730 | UNSPEC_FMMLA ; Used in aarch64-sve.md. |
624d0f07 RS |
731 | UNSPEC_FTMAD ; Used in aarch64-sve.md. |
732 | UNSPEC_FTSMUL ; Used in aarch64-sve.md. | |
733 | UNSPEC_FTSSEL ; Used in aarch64-sve.md. | |
36696774 RS |
734 | UNSPEC_SMATMUL ; Used in aarch64-sve.md. |
735 | UNSPEC_UMATMUL ; Used in aarch64-sve.md. | |
736 | UNSPEC_USMATMUL ; Used in aarch64-sve.md. | |
737 | UNSPEC_TRN1Q ; Used in aarch64-sve.md. | |
738 | UNSPEC_TRN2Q ; Used in aarch64-sve.md. | |
739 | UNSPEC_UZP1Q ; Used in aarch64-sve.md. | |
740 | UNSPEC_UZP2Q ; Used in aarch64-sve.md. | |
741 | UNSPEC_ZIP1Q ; Used in aarch64-sve.md. | |
742 | UNSPEC_ZIP2Q ; Used in aarch64-sve.md. | |
8535755a | 743 | UNSPEC_TRN1_CONV ; Used in aarch64-sve.md. |
624d0f07 RS |
744 | UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md. |
745 | UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md. | |
746 | UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md. | |
747 | UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md. | |
748 | UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md. | |
749 | UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md. | |
750 | UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md. | |
751 | UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md. | |
752 | UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md. | |
753 | UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md. | |
d45b20a5 | 754 | UNSPEC_COND_FABS ; Used in aarch64-sve.md. |
cb18e86d | 755 | UNSPEC_COND_FADD ; Used in aarch64-sve.md. |
624d0f07 RS |
756 | UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md. |
757 | UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md. | |
cb18e86d RS |
758 | UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md. |
759 | UNSPEC_COND_FCMGE ; Used in aarch64-sve.md. | |
760 | UNSPEC_COND_FCMGT ; Used in aarch64-sve.md. | |
624d0f07 RS |
761 | UNSPEC_COND_FCMLA ; Used in aarch64-sve.md. |
762 | UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md. | |
763 | UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md. | |
764 | UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md. | |
cb18e86d RS |
765 | UNSPEC_COND_FCMLE ; Used in aarch64-sve.md. |
766 | UNSPEC_COND_FCMLT ; Used in aarch64-sve.md. | |
767 | UNSPEC_COND_FCMNE ; Used in aarch64-sve.md. | |
4a942af6 | 768 | UNSPEC_COND_FCMUO ; Used in aarch64-sve.md. |
99361551 RS |
769 | UNSPEC_COND_FCVT ; Used in aarch64-sve.md. |
770 | UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md. | |
771 | UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md. | |
cb18e86d | 772 | UNSPEC_COND_FDIV ; Used in aarch64-sve.md. |
624d0f07 | 773 | UNSPEC_COND_FMAX ; Used in aarch64-sve.md. |
cb18e86d | 774 | UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md. |
624d0f07 | 775 | UNSPEC_COND_FMIN ; Used in aarch64-sve.md. |
cb18e86d | 776 | UNSPEC_COND_FMINNM ; Used in aarch64-sve.md. |
b41d1f6e RS |
777 | UNSPEC_COND_FMLA ; Used in aarch64-sve.md. |
778 | UNSPEC_COND_FMLS ; Used in aarch64-sve.md. | |
cb18e86d | 779 | UNSPEC_COND_FMUL ; Used in aarch64-sve.md. |
624d0f07 | 780 | UNSPEC_COND_FMULX ; Used in aarch64-sve.md. |
d45b20a5 | 781 | UNSPEC_COND_FNEG ; Used in aarch64-sve.md. |
b41d1f6e RS |
782 | UNSPEC_COND_FNMLA ; Used in aarch64-sve.md. |
783 | UNSPEC_COND_FNMLS ; Used in aarch64-sve.md. | |
624d0f07 | 784 | UNSPEC_COND_FRECPX ; Used in aarch64-sve.md. |
d45b20a5 RS |
785 | UNSPEC_COND_FRINTA ; Used in aarch64-sve.md. |
786 | UNSPEC_COND_FRINTI ; Used in aarch64-sve.md. | |
787 | UNSPEC_COND_FRINTM ; Used in aarch64-sve.md. | |
788 | UNSPEC_COND_FRINTN ; Used in aarch64-sve.md. | |
789 | UNSPEC_COND_FRINTP ; Used in aarch64-sve.md. | |
790 | UNSPEC_COND_FRINTX ; Used in aarch64-sve.md. | |
791 | UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md. | |
624d0f07 | 792 | UNSPEC_COND_FSCALE ; Used in aarch64-sve.md. |
d45b20a5 | 793 | UNSPEC_COND_FSQRT ; Used in aarch64-sve.md. |
cb18e86d | 794 | UNSPEC_COND_FSUB ; Used in aarch64-sve.md. |
99361551 RS |
795 | UNSPEC_COND_SCVTF ; Used in aarch64-sve.md. |
796 | UNSPEC_COND_UCVTF ; Used in aarch64-sve.md. | |
624d0f07 | 797 | UNSPEC_LASTA ; Used in aarch64-sve.md. |
43cacb12 | 798 | UNSPEC_LASTB ; Used in aarch64-sve.md. |
624d0f07 RS |
799 | UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md. |
800 | UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md. | |
801 | UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md. | |
802 | UNSPEC_LDFF1 ; Used in aarch64-sve.md. | |
803 | UNSPEC_LDNF1 ; Used in aarch64-sve.md. | |
9d63f43b TC |
804 | UNSPEC_FCADD90 ; Used in aarch64-simd.md. |
805 | UNSPEC_FCADD270 ; Used in aarch64-simd.md. | |
806 | UNSPEC_FCMLA ; Used in aarch64-simd.md. | |
807 | UNSPEC_FCMLA90 ; Used in aarch64-simd.md. | |
808 | UNSPEC_FCMLA180 ; Used in aarch64-simd.md. | |
809 | UNSPEC_FCMLA270 ; Used in aarch64-simd.md. | |
ad260343 TC |
810 | UNSPEC_FCMUL ; Used in aarch64-simd.md. |
811 | UNSPEC_FCMUL_CONJ ; Used in aarch64-simd.md. | |
812 | UNSPEC_FCMLA_CONJ ; Used in aarch64-simd.md. | |
813 | UNSPEC_FCMLA180_CONJ ; Used in aarch64-simd.md. | |
0a09a948 RS |
814 | UNSPEC_ASRD ; Used in aarch64-sve.md. |
815 | UNSPEC_ADCLB ; Used in aarch64-sve2.md. | |
816 | UNSPEC_ADCLT ; Used in aarch64-sve2.md. | |
817 | UNSPEC_ADDHNB ; Used in aarch64-sve2.md. | |
818 | UNSPEC_ADDHNT ; Used in aarch64-sve2.md. | |
819 | UNSPEC_BDEP ; Used in aarch64-sve2.md. | |
820 | UNSPEC_BEXT ; Used in aarch64-sve2.md. | |
821 | UNSPEC_BGRP ; Used in aarch64-sve2.md. | |
822 | UNSPEC_CADD270 ; Used in aarch64-sve2.md. | |
823 | UNSPEC_CADD90 ; Used in aarch64-sve2.md. | |
824 | UNSPEC_CDOT ; Used in aarch64-sve2.md. | |
825 | UNSPEC_CDOT180 ; Used in aarch64-sve2.md. | |
826 | UNSPEC_CDOT270 ; Used in aarch64-sve2.md. | |
827 | UNSPEC_CDOT90 ; Used in aarch64-sve2.md. | |
828 | UNSPEC_CMLA ; Used in aarch64-sve2.md. | |
829 | UNSPEC_CMLA180 ; Used in aarch64-sve2.md. | |
830 | UNSPEC_CMLA270 ; Used in aarch64-sve2.md. | |
831 | UNSPEC_CMLA90 ; Used in aarch64-sve2.md. | |
ad260343 TC |
832 | UNSPEC_CMLA_CONJ ; Used in aarch64-sve2.md. |
833 | UNSPEC_CMLA180_CONJ ; Used in aarch64-sve2.md. | |
834 | UNSPEC_CMUL ; Used in aarch64-sve2.md. | |
835 | UNSPEC_CMUL_CONJ ; Used in aarch64-sve2.md. | |
0a09a948 RS |
836 | UNSPEC_COND_FCVTLT ; Used in aarch64-sve2.md. |
837 | UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md. | |
838 | UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md. | |
839 | UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md. | |
840 | UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md. | |
841 | UNSPEC_EORBT ; Used in aarch64-sve2.md. | |
842 | UNSPEC_EORTB ; Used in aarch64-sve2.md. | |
843 | UNSPEC_FADDP ; Used in aarch64-sve2.md. | |
844 | UNSPEC_FMAXNMP ; Used in aarch64-sve2.md. | |
845 | UNSPEC_FMAXP ; Used in aarch64-sve2.md. | |
846 | UNSPEC_FMINNMP ; Used in aarch64-sve2.md. | |
847 | UNSPEC_FMINP ; Used in aarch64-sve2.md. | |
848 | UNSPEC_FMLALB ; Used in aarch64-sve2.md. | |
849 | UNSPEC_FMLALT ; Used in aarch64-sve2.md. | |
850 | UNSPEC_FMLSLB ; Used in aarch64-sve2.md. | |
851 | UNSPEC_FMLSLT ; Used in aarch64-sve2.md. | |
852 | UNSPEC_HISTCNT ; Used in aarch64-sve2.md. | |
853 | UNSPEC_HISTSEG ; Used in aarch64-sve2.md. | |
854 | UNSPEC_MATCH ; Used in aarch64-sve2.md. | |
855 | UNSPEC_NMATCH ; Used in aarch64-sve2.md. | |
856 | UNSPEC_PMULLB ; Used in aarch64-sve2.md. | |
857 | UNSPEC_PMULLB_PAIR ; Used in aarch64-sve2.md. | |
858 | UNSPEC_PMULLT ; Used in aarch64-sve2.md. | |
859 | UNSPEC_PMULLT_PAIR ; Used in aarch64-sve2.md. | |
860 | UNSPEC_RADDHNB ; Used in aarch64-sve2.md. | |
861 | UNSPEC_RADDHNT ; Used in aarch64-sve2.md. | |
862 | UNSPEC_RSHRNB ; Used in aarch64-sve2.md. | |
863 | UNSPEC_RSHRNT ; Used in aarch64-sve2.md. | |
864 | UNSPEC_RSUBHNB ; Used in aarch64-sve2.md. | |
865 | UNSPEC_RSUBHNT ; Used in aarch64-sve2.md. | |
866 | UNSPEC_SABDLB ; Used in aarch64-sve2.md. | |
867 | UNSPEC_SABDLT ; Used in aarch64-sve2.md. | |
868 | UNSPEC_SADDLB ; Used in aarch64-sve2.md. | |
869 | UNSPEC_SADDLBT ; Used in aarch64-sve2.md. | |
870 | UNSPEC_SADDLT ; Used in aarch64-sve2.md. | |
871 | UNSPEC_SADDWB ; Used in aarch64-sve2.md. | |
872 | UNSPEC_SADDWT ; Used in aarch64-sve2.md. | |
873 | UNSPEC_SBCLB ; Used in aarch64-sve2.md. | |
874 | UNSPEC_SBCLT ; Used in aarch64-sve2.md. | |
875 | UNSPEC_SHRNB ; Used in aarch64-sve2.md. | |
876 | UNSPEC_SHRNT ; Used in aarch64-sve2.md. | |
877 | UNSPEC_SLI ; Used in aarch64-sve2.md. | |
878 | UNSPEC_SMAXP ; Used in aarch64-sve2.md. | |
879 | UNSPEC_SMINP ; Used in aarch64-sve2.md. | |
58cc9876 | 880 | UNSPEC_SMULHRS ; Used in aarch64-sve2.md. |
0a09a948 RS |
881 | UNSPEC_SMULHS ; Used in aarch64-sve2.md. |
882 | UNSPEC_SMULLB ; Used in aarch64-sve2.md. | |
883 | UNSPEC_SMULLT ; Used in aarch64-sve2.md. | |
884 | UNSPEC_SQCADD270 ; Used in aarch64-sve2.md. | |
885 | UNSPEC_SQCADD90 ; Used in aarch64-sve2.md. | |
886 | UNSPEC_SQDMULLB ; Used in aarch64-sve2.md. | |
887 | UNSPEC_SQDMULLBT ; Used in aarch64-sve2.md. | |
888 | UNSPEC_SQDMULLT ; Used in aarch64-sve2.md. | |
889 | UNSPEC_SQRDCMLAH ; Used in aarch64-sve2.md. | |
890 | UNSPEC_SQRDCMLAH180 ; Used in aarch64-sve2.md. | |
891 | UNSPEC_SQRDCMLAH270 ; Used in aarch64-sve2.md. | |
892 | UNSPEC_SQRDCMLAH90 ; Used in aarch64-sve2.md. | |
893 | UNSPEC_SQRSHRNB ; Used in aarch64-sve2.md. | |
894 | UNSPEC_SQRSHRNT ; Used in aarch64-sve2.md. | |
895 | UNSPEC_SQRSHRUNB ; Used in aarch64-sve2.md. | |
896 | UNSPEC_SQRSHRUNT ; Used in aarch64-sve2.md. | |
897 | UNSPEC_SQSHRNB ; Used in aarch64-sve2.md. | |
898 | UNSPEC_SQSHRNT ; Used in aarch64-sve2.md. | |
899 | UNSPEC_SQSHRUNB ; Used in aarch64-sve2.md. | |
900 | UNSPEC_SQSHRUNT ; Used in aarch64-sve2.md. | |
901 | UNSPEC_SQXTNB ; Used in aarch64-sve2.md. | |
902 | UNSPEC_SQXTNT ; Used in aarch64-sve2.md. | |
903 | UNSPEC_SQXTUNB ; Used in aarch64-sve2.md. | |
904 | UNSPEC_SQXTUNT ; Used in aarch64-sve2.md. | |
905 | UNSPEC_SRI ; Used in aarch64-sve2.md. | |
906 | UNSPEC_SSHLLB ; Used in aarch64-sve2.md. | |
907 | UNSPEC_SSHLLT ; Used in aarch64-sve2.md. | |
908 | UNSPEC_SSUBLB ; Used in aarch64-sve2.md. | |
909 | UNSPEC_SSUBLBT ; Used in aarch64-sve2.md. | |
910 | UNSPEC_SSUBLT ; Used in aarch64-sve2.md. | |
911 | UNSPEC_SSUBLTB ; Used in aarch64-sve2.md. | |
912 | UNSPEC_SSUBWB ; Used in aarch64-sve2.md. | |
913 | UNSPEC_SSUBWT ; Used in aarch64-sve2.md. | |
914 | UNSPEC_SUBHNB ; Used in aarch64-sve2.md. | |
915 | UNSPEC_SUBHNT ; Used in aarch64-sve2.md. | |
916 | UNSPEC_TBL2 ; Used in aarch64-sve2.md. | |
917 | UNSPEC_UABDLB ; Used in aarch64-sve2.md. | |
918 | UNSPEC_UABDLT ; Used in aarch64-sve2.md. | |
919 | UNSPEC_UADDLB ; Used in aarch64-sve2.md. | |
920 | UNSPEC_UADDLT ; Used in aarch64-sve2.md. | |
921 | UNSPEC_UADDWB ; Used in aarch64-sve2.md. | |
922 | UNSPEC_UADDWT ; Used in aarch64-sve2.md. | |
923 | UNSPEC_UMAXP ; Used in aarch64-sve2.md. | |
924 | UNSPEC_UMINP ; Used in aarch64-sve2.md. | |
58cc9876 | 925 | UNSPEC_UMULHRS ; Used in aarch64-sve2.md. |
0a09a948 RS |
926 | UNSPEC_UMULHS ; Used in aarch64-sve2.md. |
927 | UNSPEC_UMULLB ; Used in aarch64-sve2.md. | |
928 | UNSPEC_UMULLT ; Used in aarch64-sve2.md. | |
929 | UNSPEC_UQRSHRNB ; Used in aarch64-sve2.md. | |
930 | UNSPEC_UQRSHRNT ; Used in aarch64-sve2.md. | |
931 | UNSPEC_UQSHRNB ; Used in aarch64-sve2.md. | |
932 | UNSPEC_UQSHRNT ; Used in aarch64-sve2.md. | |
933 | UNSPEC_UQXTNB ; Used in aarch64-sve2.md. | |
934 | UNSPEC_UQXTNT ; Used in aarch64-sve2.md. | |
935 | UNSPEC_USHLLB ; Used in aarch64-sve2.md. | |
936 | UNSPEC_USHLLT ; Used in aarch64-sve2.md. | |
937 | UNSPEC_USUBLB ; Used in aarch64-sve2.md. | |
938 | UNSPEC_USUBLT ; Used in aarch64-sve2.md. | |
939 | UNSPEC_USUBWB ; Used in aarch64-sve2.md. | |
940 | UNSPEC_USUBWT ; Used in aarch64-sve2.md. | |
8c197c85 SMW |
941 | UNSPEC_USDOT ; Used in aarch64-simd.md. |
942 | UNSPEC_SUDOT ; Used in aarch64-simd.md. | |
f275d73a | 943 | UNSPEC_BFDOT ; Used in aarch64-simd.md. |
896dff99 RS |
944 | UNSPEC_BFMLALB ; Used in aarch64-sve.md. |
945 | UNSPEC_BFMLALT ; Used in aarch64-sve.md. | |
946 | UNSPEC_BFMMLA ; Used in aarch64-sve.md. | |
1f520d34 DB |
947 | UNSPEC_BFCVTN ; Used in aarch64-simd.md. |
948 | UNSPEC_BFCVTN2 ; Used in aarch64-simd.md. | |
949 | UNSPEC_BFCVT ; Used in aarch64-simd.md. | |
8456a4cd | 950 | UNSPEC_FCVTXN ; Used in aarch64-simd.md. |
43e9d192 IB |
951 | ]) |
952 | ||
d81cb613 MW |
953 | ;; ------------------------------------------------------------------ |
954 | ;; Unspec enumerations for Atomics. They are here so that they can be | |
955 | ;; used in the int_iterators for atomic operations. | |
956 | ;; ------------------------------------------------------------------ | |
957 | ||
958 | (define_c_enum "unspecv" | |
959 | [ | |
960 | UNSPECV_LX ; Represent a load-exclusive. | |
961 | UNSPECV_SX ; Represent a store-exclusive. | |
962 | UNSPECV_LDA ; Represent an atomic load or load-acquire. | |
0431e8ae | 963 | UNSPECV_LDAP ; Represent an atomic acquire load with RCpc semantics. |
d81cb613 MW |
964 | UNSPECV_STL ; Represent an atomic store or store-release. |
965 | UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. | |
966 | UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. | |
967 | UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. | |
968 | UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. | |
969 | UNSPECV_ATOMIC_OP ; Represent an atomic operation. | |
d81cb613 MW |
970 | UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or |
971 | UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic | |
972 | UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor | |
973 | UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add | |
974 | ]) | |
975 | ||
43e9d192 IB |
976 | ;; ------------------------------------------------------------------- |
977 | ;; Mode attributes | |
978 | ;; ------------------------------------------------------------------- | |
979 | ||
865257c4 RS |
980 | ;; "e" for signaling operations, "" for quiet operations. |
981 | (define_mode_attr e [(CCFP "") (CCFPE "e")]) | |
982 | ||
43e9d192 IB |
983 | ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the |
984 | ;; 32-bit version and "%x0" in the 64-bit version. | |
985 | (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) | |
986 | ||
db46a2e6 JG |
987 | ;; The size of access, in bytes. |
988 | (define_mode_attr ldst_sz [(SI "4") (DI "8")]) | |
989 | ;; Likewise for load/store pair. | |
990 | (define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) | |
991 | ||
85279b0b VDN |
992 | ;; Size of element access for STP/LDP-generated vectors. |
993 | (define_mode_attr ldpstp_vel_sz [(V2SI "8") (V2SF "8") (V2DI "16") (V2DF "16")]) | |
994 | ||
0d35c5c2 | 995 | ;; For inequal width int to float conversion |
d7f33f07 JW |
996 | (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) |
997 | (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) | |
0d35c5c2 | 998 | |
22be0d08 MC |
999 | ;; For width of fp registers in fcvt instruction |
1000 | (define_mode_attr fpw [(DI "s") (SI "d")]) | |
1001 | ||
2b8568fe KT |
1002 | (define_mode_attr short_mask [(HI "65535") (QI "255")]) |
1003 | ||
b747f54a KT |
1004 | (define_mode_attr half_mask [(HI "255") (SI "65535") (DI "4294967295")]) |
1005 | ||
051d0e2f SN |
1006 | ;; For constraints used in scalar immediate vector moves |
1007 | (define_mode_attr hq [(HI "h") (QI "q")]) | |
1008 | ||
ef22810a RH |
1009 | ;; For doubling width of an integer mode |
1010 | (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) | |
1011 | ||
22be0d08 MC |
1012 | (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) |
1013 | ||
1014 | (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) | |
1015 | ||
43e9d192 IB |
1016 | ;; For scalar usage of vector/FP registers |
1017 | (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") | |
d7f33f07 | 1018 | (HF "h") (SF "s") (DF "d") |
43e9d192 IB |
1019 | (V8QI "") (V16QI "") |
1020 | (V4HI "") (V8HI "") | |
1021 | (V2SI "") (V4SI "") | |
1022 | (V2DI "") (V2SF "") | |
daef0a8c JW |
1023 | (V4SF "") (V4HF "") |
1024 | (V8HF "") (V2DF "")]) | |
43e9d192 IB |
1025 | |
1026 | ;; For scalar usage of vector/FP registers, narrowing | |
1027 | (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") | |
1028 | (V8QI "") (V16QI "") | |
1029 | (V4HI "") (V8HI "") | |
1030 | (V2SI "") (V4SI "") | |
1031 | (V2DI "") (V2SF "") | |
1032 | (V4SF "") (V2DF "")]) | |
1033 | ||
1034 | ;; For scalar usage of vector/FP registers, widening | |
1035 | (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") | |
1036 | (V8QI "") (V16QI "") | |
1037 | (V4HI "") (V8HI "") | |
1038 | (V2SI "") (V4SI "") | |
1039 | (V2DI "") (V2SF "") | |
1040 | (V4SF "") (V2DF "")]) | |
1041 | ||
89fdc743 IB |
1042 | ;; Register Type Name and Vector Arrangement Specifier for when |
1043 | ;; we are doing scalar for DI and SIMD for SI (ignoring all but | |
1044 | ;; lane 0). | |
1045 | (define_mode_attr rtn [(DI "d") (SI "")]) | |
1046 | (define_mode_attr vas [(DI "") (SI ".2s")]) | |
1047 | ||
7ac29c0f RS |
1048 | ;; Map a vector to the number of units in it, if the size of the mode |
1049 | ;; is constant. | |
1050 | (define_mode_attr nunits [(V8QI "8") (V16QI "16") | |
1051 | (V4HI "4") (V8HI "8") | |
1052 | (V2SI "2") (V4SI "4") | |
5ba864c5 | 1053 | (V1DI "1") (V2DI "2") |
7ac29c0f | 1054 | (V4HF "4") (V8HF "8") |
abbe1ed2 | 1055 | (V4BF "4") (V8BF "8") |
7ac29c0f RS |
1056 | (V2SF "2") (V4SF "4") |
1057 | (V1DF "1") (V2DF "2") | |
5ba864c5 | 1058 | (DI "1") (DF "1") |
a40c22c3 | 1059 | (V8DI "8")]) |
7ac29c0f | 1060 | |
b187677b RS |
1061 | ;; Map a mode to the number of bits in it, if the size of the mode |
1062 | ;; is constant. | |
1063 | (define_mode_attr bitsize [(V8QI "64") (V16QI "128") | |
1064 | (V4HI "64") (V8HI "128") | |
1065 | (V2SI "64") (V4SI "128") | |
1066 | (V2DI "128")]) | |
1067 | ||
22be0d08 MC |
1068 | ;; Map a floating point or integer mode to the appropriate register name prefix |
1069 | (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) | |
43e9d192 IB |
1070 | |
1071 | ;; Give the length suffix letter for a sign- or zero-extension. | |
1072 | (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) | |
1073 | ||
1074 | ;; Give the number of bits in the mode | |
1075 | (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) | |
17ae956c TC |
1076 | (define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")]) |
1077 | (define_mode_attr zerom [(QI "si") (HI "si") (SI "si") (DI "di")]) | |
43e9d192 IB |
1078 | |
1079 | ;; Give the ordinal of the MSB in the mode | |
315fdae8 RE |
1080 | (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") |
1081 | (HF "#15") (SF "#31") (DF "#63")]) | |
43e9d192 | 1082 | |
95eb5537 RS |
1083 | ;; The number of bits in a vector element, or controlled by a predicate |
1084 | ;; element. | |
d7a09c44 RS |
1085 | (define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16") |
1086 | (VNx4BI "32") (VNx2BI "64") | |
1087 | (VNx16QI "8") (VNx8HI "16") | |
1088 | (VNx4SI "32") (VNx2DI "64") | |
95eb5537 RS |
1089 | (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")]) |
1090 | ||
6c3ce63b RS |
1091 | ;; The number of bits in a vector container. |
1092 | (define_mode_attr container_bits [(VNx16QI "8") | |
1093 | (VNx8HI "16") (VNx8QI "16") (VNx8HF "16") | |
1094 | (VNx8BF "16") | |
1095 | (VNx4SI "32") (VNx4HI "32") (VNx4QI "32") | |
1096 | (VNx4SF "32") (VNx4HF "32") (VNx4BF "32") | |
1097 | (VNx2DI "64") (VNx2SI "64") (VNx2HI "64") | |
1098 | (VNx2QI "64") (VNx2DF "64") (VNx2SF "64") | |
1099 | (VNx2HF "64") (VNx2BF "64")]) | |
1100 | ||
43e9d192 IB |
1101 | ;; Attribute to describe constants acceptable in logical operations |
1102 | (define_mode_attr lconst [(SI "K") (DI "L")]) | |
1103 | ||
43fd192f MC |
1104 | ;; Attribute to describe constants acceptable in logical and operations |
1105 | (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) | |
1106 | ||
43e9d192 IB |
1107 | ;; Map a mode to a specific constraint character. |
1108 | (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) | |
1109 | ||
0603375c KT |
1110 | ;; Map modes to Usg and Usj constraints for SISD right shifts |
1111 | (define_mode_attr cmode_simd [(SI "g") (DI "j")]) | |
1112 | ||
43e9d192 IB |
1113 | (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") |
1114 | (V4HI "4h") (V8HI "8h") | |
8ea6c1b8 | 1115 | (V4BF "4h") (V8BF "8h") |
43e9d192 IB |
1116 | (V2SI "2s") (V4SI "4s") |
1117 | (DI "1d") (DF "1d") | |
1118 | (V2DI "2d") (V2SF "2s") | |
7c369485 | 1119 | (V4SF "4s") (V2DF "2d") |
66f206b8 JW |
1120 | (V4HF "4h") (V8HF "8h") |
1121 | (V2x8QI "8b") (V2x4HI "4h") | |
1122 | (V2x2SI "2s") (V2x1DI "1d") | |
1123 | (V2x4HF "4h") (V2x2SF "2s") | |
1124 | (V2x1DF "1d") (V2x4BF "4h") | |
1125 | (V2x16QI "16b") (V2x8HI "8h") | |
1126 | (V2x4SI "4s") (V2x2DI "2d") | |
1127 | (V2x8HF "8h") (V2x4SF "4s") | |
1128 | (V2x2DF "2d") (V2x8BF "8h") | |
1129 | (V3x8QI "8b") (V3x4HI "4h") | |
1130 | (V3x2SI "2s") (V3x1DI "1d") | |
1131 | (V3x4HF "4h") (V3x2SF "2s") | |
1132 | (V3x1DF "1d") (V3x4BF "4h") | |
1133 | (V3x16QI "16b") (V3x8HI "8h") | |
1134 | (V3x4SI "4s") (V3x2DI "2d") | |
1135 | (V3x8HF "8h") (V3x4SF "4s") | |
1136 | (V3x2DF "2d") (V3x8BF "8h") | |
1137 | (V4x8QI "8b") (V4x4HI "4h") | |
1138 | (V4x2SI "2s") (V4x1DI "1d") | |
1139 | (V4x4HF "4h") (V4x2SF "2s") | |
1140 | (V4x1DF "1d") (V4x4BF "4h") | |
1141 | (V4x16QI "16b") (V4x8HI "8h") | |
1142 | (V4x4SI "4s") (V4x2DI "2d") | |
1143 | (V4x8HF "8h") (V4x4SF "4s") | |
1144 | (V4x2DF "2d") (V4x8BF "8h")]) | |
43e9d192 | 1145 | |
0b839322 WD |
1146 | ;; Map mode to type used in widening multiplies. |
1147 | (define_mode_attr Vcondtype [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")]) | |
1148 | ||
1149 | ;; Map lane mode to name | |
1150 | (define_mode_attr Qlane [(V4HI "_v4hi") (V8HI "q_v4hi") | |
1151 | (V2SI "_v2si") (V4SI "q_v2si")]) | |
1152 | ||
c7f28cd5 KT |
1153 | (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") |
1154 | (V4SI "32") (V2DI "64")]) | |
1155 | ||
43e9d192 IB |
1156 | (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") |
1157 | (V4HI ".4h") (V8HI ".8h") | |
1158 | (V2SI ".2s") (V4SI ".4s") | |
71a11456 | 1159 | (V2DI ".2d") (V4HF ".4h") |
cf9c3bff RS |
1160 | (V8HF ".8h") (V4BF ".4h") |
1161 | (V8BF ".8h") (V2SF ".2s") | |
43e9d192 IB |
1162 | (V4SF ".4s") (V2DF ".2d") |
1163 | (DI "") (SI "") | |
1164 | (HI "") (QI "") | |
d7f33f07 JW |
1165 | (TI "") (HF "") |
1166 | (SF "") (DF "")]) | |
43e9d192 IB |
1167 | |
1168 | ;; Register suffix narrowed modes for VQN. | |
1169 | (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") | |
1170 | (V2DI ".2s") | |
1171 | (DI "") (SI "") | |
1172 | (HI "")]) | |
1173 | ||
1174 | ;; Mode-to-individual element type mapping. | |
cc68f7c2 RS |
1175 | (define_mode_attr Vetype [(V8QI "b") (V16QI "b") |
1176 | (V4HI "h") (V8HI "h") | |
1177 | (V2SI "s") (V4SI "s") | |
a40c22c3 | 1178 | (V2DI "d") |
cc68f7c2 RS |
1179 | (V4HF "h") (V8HF "h") |
1180 | (V2SF "s") (V4SF "s") | |
1181 | (V2DF "d") | |
66f206b8 JW |
1182 | (V2x8QI "b") (V2x4HI "h") |
1183 | (V2x2SI "s") (V2x1DI "d") | |
1184 | (V2x4HF "h") (V2x2SF "s") | |
1185 | (V2x1DF "d") (V2x4BF "h") | |
1186 | (V2x16QI "b") (V2x8HI "h") | |
1187 | (V2x4SI "s") (V2x2DI "d") | |
1188 | (V2x8HF "h") (V2x4SF "s") | |
1189 | (V2x2DF "d") (V2x8BF "h") | |
1190 | (V3x8QI "b") (V3x4HI "h") | |
1191 | (V3x2SI "s") (V3x1DI "d") | |
1192 | (V3x4HF "h") (V3x2SF "s") | |
1193 | (V3x1DF "d") (V3x4BF "h") | |
1194 | (V3x16QI "b") (V3x8HI "h") | |
1195 | (V3x4SI "s") (V3x2DI "d") | |
1196 | (V3x8HF "h") (V3x4SF "s") | |
1197 | (V3x2DF "d") (V3x8BF "h") | |
1198 | (V4x8QI "b") (V4x4HI "h") | |
1199 | (V4x2SI "s") (V4x1DI "d") | |
1200 | (V4x4HF "h") (V4x2SF "s") | |
1201 | (V4x1DF "d") (V4x4BF "h") | |
1202 | (V4x16QI "b") (V4x8HI "h") | |
1203 | (V4x4SI "s") (V4x2DI "d") | |
1204 | (V4x8HF "h") (V4x4SF "s") | |
1205 | (V4x2DF "d") (V4x8BF "h") | |
cc68f7c2 RS |
1206 | (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d") |
1207 | (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b") | |
1208 | (VNx8HI "h") (VNx4HI "h") (VNx2HI "h") | |
1209 | (VNx8HF "h") (VNx4HF "h") (VNx2HF "h") | |
6c3ce63b | 1210 | (VNx8BF "h") (VNx4BF "h") (VNx2BF "h") |
cc68f7c2 RS |
1211 | (VNx4SI "s") (VNx2SI "s") |
1212 | (VNx4SF "s") (VNx2SF "s") | |
1213 | (VNx2DI "d") | |
1214 | (VNx2DF "d") | |
8ea6c1b8 | 1215 | (BF "h") (V4BF "h") (V8BF "h") |
cc68f7c2 RS |
1216 | (HF "h") |
1217 | (SF "s") (DF "d") | |
1218 | (QI "b") (HI "h") | |
1219 | (SI "s") (DI "d")]) | |
43e9d192 | 1220 | |
9feeafd7 AM |
1221 | ;; Like Vetype, but map to types that are a quarter of the element size. |
1222 | (define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")]) | |
1223 | ||
43cacb12 | 1224 | ;; Equivalent of "size" for a vector element. |
cc68f7c2 RS |
1225 | (define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b") |
1226 | (VNx8HI "h") (VNx4HI "h") (VNx2HI "h") | |
1227 | (VNx8HF "h") (VNx4HF "h") (VNx2HF "h") | |
6c3ce63b | 1228 | (VNx8BF "h") (VNx4BF "h") (VNx2BF "h") |
cc68f7c2 RS |
1229 | (VNx4SI "w") (VNx2SI "w") |
1230 | (VNx4SF "w") (VNx2SF "w") | |
1231 | (VNx2DI "d") | |
1232 | (VNx2DF "d") | |
9f4cbab8 RS |
1233 | (VNx32QI "b") (VNx48QI "b") (VNx64QI "b") |
1234 | (VNx16HI "h") (VNx24HI "h") (VNx32HI "h") | |
1235 | (VNx16HF "h") (VNx24HF "h") (VNx32HF "h") | |
02fcd8ac | 1236 | (VNx16BF "h") (VNx24BF "h") (VNx32BF "h") |
9f4cbab8 RS |
1237 | (VNx8SI "w") (VNx12SI "w") (VNx16SI "w") |
1238 | (VNx8SF "w") (VNx12SF "w") (VNx16SF "w") | |
1239 | (VNx4DI "d") (VNx6DI "d") (VNx8DI "d") | |
1240 | (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")]) | |
43cacb12 | 1241 | |
cc68f7c2 RS |
1242 | ;; The Z register suffix for an SVE mode's element container, i.e. the |
1243 | ;; Vetype of full SVE modes that have the same number of elements. | |
1244 | (define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d") | |
1245 | (VNx8HI "h") (VNx4HI "s") (VNx2HI "d") | |
1246 | (VNx8HF "h") (VNx4HF "s") (VNx2HF "d") | |
6c3ce63b | 1247 | (VNx8BF "h") (VNx4BF "s") (VNx2BF "d") |
cc68f7c2 RS |
1248 | (VNx4SI "s") (VNx2SI "d") |
1249 | (VNx4SF "s") (VNx2SF "d") | |
1250 | (VNx2DI "d") | |
1251 | (VNx2DF "d")]) | |
1252 | ||
6c3ce63b RS |
1253 | ;; The instruction mnemonic suffix for an SVE mode's element container, |
1254 | ;; i.e. the Vewtype of full SVE modes that have the same number of elements. | |
1255 | (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "w") (VNx2QI "d") | |
1256 | (VNx8HI "h") (VNx4HI "w") (VNx2HI "d") | |
1257 | (VNx8HF "h") (VNx4HF "w") (VNx2HF "d") | |
1258 | (VNx8BF "h") (VNx4BF "w") (VNx2BF "d") | |
1259 | (VNx4SI "w") (VNx2SI "d") | |
1260 | (VNx4SF "w") (VNx2SF "d") | |
1261 | (VNx2DI "d") | |
1262 | (VNx2DF "d")]) | |
1263 | ||
daef0a8c JW |
1264 | ;; Vetype is used everywhere in scheduling type and assembly output, |
1265 | ;; sometimes they are not the same, for example HF modes on some | |
1266 | ;; instructions. stype is defined to represent scheduling type | |
1267 | ;; more accurately. | |
1268 | (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") | |
1269 | (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") | |
a40c22c3 | 1270 | (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") |
daef0a8c JW |
1271 | (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") |
1272 | (SI "s") (DI "d")]) | |
1273 | ||
43e9d192 IB |
1274 | ;; Mode-to-bitwise operation type mapping. |
1275 | (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") | |
1276 | (V4HI "8b") (V8HI "16b") | |
1277 | (V2SI "8b") (V4SI "16b") | |
7c369485 AL |
1278 | (V2DI "16b") (V4HF "8b") |
1279 | (V8HF "16b") (V2SF "8b") | |
46e778c4 | 1280 | (V4SF "16b") (V2DF "16b") |
fe82d1f2 | 1281 | (DI "8b") (DF "8b") |
abbe1ed2 | 1282 | (SI "8b") (SF "8b") |
830460d6 | 1283 | (QI "8b") (HI "8b") |
abbe1ed2 | 1284 | (V4BF "8b") (V8BF "16b")]) |
43e9d192 | 1285 | |
66f206b8 JW |
1286 | ;; Advanced SIMD vector structure to element modes. |
1287 | (define_mode_attr VSTRUCT_ELT [(V2x8QI "V8QI") (V2x4HI "V4HI") | |
1288 | (V2x2SI "V2SI") (V2x1DI "DI") | |
1289 | (V2x4HF "V4HF") (V2x2SF "V2SF") | |
1290 | (V2x1DF "DF") (V2x4BF "V4BF") | |
1291 | (V3x8QI "V8QI") (V3x4HI "V4HI") | |
1292 | (V3x2SI "V2SI") (V3x1DI "DI") | |
1293 | (V3x4HF "V4HF") (V3x2SF "V2SF") | |
1294 | (V3x1DF "DF") (V3x4BF "V4BF") | |
1295 | (V4x8QI "V8QI") (V4x4HI "V4HI") | |
1296 | (V4x2SI "V2SI") (V4x1DI "DI") | |
1297 | (V4x4HF "V4HF") (V4x2SF "V2SF") | |
1298 | (V4x1DF "DF") (V4x4BF "V4BF") | |
1299 | (V2x16QI "V16QI") (V2x8HI "V8HI") | |
1300 | (V2x4SI "V4SI") (V2x2DI "V2DI") | |
1301 | (V2x8HF "V8HF") (V2x4SF "V4SF") | |
1302 | (V2x2DF "V2DF") (V2x8BF "V8BF") | |
1303 | (V3x16QI "V16QI") (V3x8HI "V8HI") | |
1304 | (V3x4SI "V4SI") (V3x2DI "V2DI") | |
1305 | (V3x8HF "V8HF") (V3x4SF "V4SF") | |
1306 | (V3x2DF "V2DF") (V3x8BF "V8BF") | |
1307 | (V4x16QI "V16QI") (V4x8HI "V8HI") | |
1308 | (V4x4SI "V4SI") (V4x2DI "V2DI") | |
1309 | (V4x8HF "V8HF") (V4x4SF "V4SF") | |
1310 | (V4x2DF "V2DF") (V4x8BF "V8BF")]) | |
1311 | ||
1312 | ;; Advanced SIMD vector structure to element modes in lower case. | |
1313 | (define_mode_attr vstruct_elt [(V2x8QI "v8qi") (V2x4HI "v4hi") | |
1314 | (V2x2SI "v2si") (V2x1DI "di") | |
1315 | (V2x4HF "v4hf") (V2x2SF "v2sf") | |
1316 | (V2x1DF "df") (V2x4BF "v4bf") | |
1317 | (V3x8QI "v8qi") (V3x4HI "v4hi") | |
1318 | (V3x2SI "v2si") (V3x1DI "di") | |
1319 | (V3x4HF "v4hf") (V3x2SF "v2sf") | |
1320 | (V3x1DF "df") (V3x4BF "v4bf") | |
1321 | (V4x8QI "v8qi") (V4x4HI "v4hi") | |
1322 | (V4x2SI "v2si") (V4x1DI "di") | |
1323 | (V4x4HF "v4hf") (V4x2SF "v2sf") | |
1324 | (V4x1DF "df") (V4x4BF "v4bf") | |
1325 | (V2x16QI "v16qi") (V2x8HI "v8hi") | |
1326 | (V2x4SI "v4si") (V2x2DI "v2di") | |
1327 | (V2x8HF "v8hf") (V2x4SF "v4sf") | |
1328 | (V2x2DF "v2df") (V2x8BF "v8bf") | |
1329 | (V3x16QI "v16qi") (V3x8HI "v8hi") | |
1330 | (V3x4SI "v4si") (V3x2DI "v2di") | |
1331 | (V3x8HF "v8hf") (V3x4SF "v4sf") | |
1332 | (V3x2DF "v2df") (V3x8BF "v8bf") | |
1333 | (V4x16QI "v16qi") (V4x8HI "v8hi") | |
1334 | (V4x4SI "v4si") (V4x2DI "v2di") | |
1335 | (V4x8HF "v8hf") (V4x4SF "v4sf") | |
1336 | (V4x2DF "v2df") (V4x8BF "v8bf")]) | |
1337 | ||
43e9d192 | 1338 | ;; Define element mode for each vector mode. |
cc68f7c2 RS |
1339 | (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") |
1340 | (V4HI "HI") (V8HI "HI") | |
1341 | (V2SI "SI") (V4SI "SI") | |
1342 | (DI "DI") (V2DI "DI") | |
1343 | (V4HF "HF") (V8HF "HF") | |
1344 | (V2SF "SF") (V4SF "SF") | |
1345 | (DF "DF") (V2DF "DF") | |
a40c22c3 TC |
1346 | (SI "SI") (HI "HI") |
1347 | (QI "QI") | |
8ea6c1b8 | 1348 | (V4BF "BF") (V8BF "BF") |
cc68f7c2 RS |
1349 | (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI") |
1350 | (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI") | |
1351 | (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF") | |
6c3ce63b | 1352 | (VNx8BF "BF") (VNx4BF "BF") (VNx2BF "BF") |
cc68f7c2 RS |
1353 | (VNx4SI "SI") (VNx2SI "SI") |
1354 | (VNx4SF "SF") (VNx2SF "SF") | |
1355 | (VNx2DI "DI") | |
1356 | (VNx2DF "DF")]) | |
43e9d192 | 1357 | |
ff03930a | 1358 | ;; Define element mode for each vector mode (lower case). |
cc68f7c2 RS |
1359 | (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") |
1360 | (V4HI "hi") (V8HI "hi") | |
1361 | (V2SI "si") (V4SI "si") | |
1362 | (DI "di") (V2DI "di") | |
1363 | (V4HF "hf") (V8HF "hf") | |
1364 | (V2SF "sf") (V4SF "sf") | |
1365 | (V2DF "df") (DF "df") | |
1366 | (SI "si") (HI "hi") | |
a40c22c3 | 1367 | (QI "qi") |
8ea6c1b8 | 1368 | (V4BF "bf") (V8BF "bf") |
cc68f7c2 RS |
1369 | (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") |
1370 | (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") | |
1371 | (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf") | |
6c3ce63b | 1372 | (VNx8BF "bf") (VNx4BF "bf") (VNx2BF "bf") |
cc68f7c2 RS |
1373 | (VNx4SI "si") (VNx2SI "si") |
1374 | (VNx4SF "sf") (VNx2SF "sf") | |
1375 | (VNx2DI "di") | |
1376 | (VNx2DF "df")]) | |
ff03930a | 1377 | |
43cacb12 RS |
1378 | ;; Element mode with floating-point values replaced by like-sized integers. |
1379 | (define_mode_attr VEL_INT [(VNx16QI "QI") | |
02fcd8ac | 1380 | (VNx8HI "HI") (VNx8HF "HI") (VNx8BF "HI") |
43cacb12 RS |
1381 | (VNx4SI "SI") (VNx4SF "SI") |
1382 | (VNx2DI "DI") (VNx2DF "DI")]) | |
1383 | ||
1384 | ;; Gives the mode of the 128-bit lowpart of an SVE vector. | |
1385 | (define_mode_attr V128 [(VNx16QI "V16QI") | |
02fcd8ac | 1386 | (VNx8HI "V8HI") (VNx8HF "V8HF") (VNx8BF "V8BF") |
43cacb12 RS |
1387 | (VNx4SI "V4SI") (VNx4SF "V4SF") |
1388 | (VNx2DI "V2DI") (VNx2DF "V2DF")]) | |
1389 | ||
1390 | ;; ...and again in lower case. | |
1391 | (define_mode_attr v128 [(VNx16QI "v16qi") | |
02fcd8ac | 1392 | (VNx8HI "v8hi") (VNx8HF "v8hf") (VNx8BF "v8bf") |
43cacb12 RS |
1393 | (VNx4SI "v4si") (VNx4SF "v4sf") |
1394 | (VNx2DI "v2di") (VNx2DF "v2df")]) | |
1395 | ||
c69db3ef KT |
1396 | (define_mode_attr vnx [(V4SI "vnx4si") (V2DI "vnx2di")]) |
1397 | ||
278821f2 KT |
1398 | ;; 64-bit container modes the inner or scalar source mode. |
1399 | (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") | |
1400 | (V4HI "V4HI") (V8HI "V4HI") | |
b7d7d917 TB |
1401 | (V2SI "V2SI") (V4SI "V2SI") |
1402 | (DI "DI") (V2DI "DI") | |
28de75d2 | 1403 | (V4HF "V4HF") (V8HF "V4HF") |
b7d7d917 TB |
1404 | (V2SF "V2SF") (V4SF "V2SF") |
1405 | (V2DF "DF")]) | |
1406 | ||
278821f2 | 1407 | ;; 128-bit container modes the inner or scalar source mode. |
b7d7d917 TB |
1408 | (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") |
1409 | (V4HI "V8HI") (V8HI "V8HI") | |
1410 | (V2SI "V4SI") (V4SI "V4SI") | |
1411 | (DI "V2DI") (V2DI "V2DI") | |
71a11456 | 1412 | (V4HF "V8HF") (V8HF "V8HF") |
28de75d2 | 1413 | (V2SF "V4SF") (V4SF "V4SF") |
b7d7d917 | 1414 | (V2DF "V2DF") (SI "V4SI") |
f2b23a59 TC |
1415 | (HI "V8HI") (QI "V16QI") |
1416 | (SF "V4SF") (DF "V2DF")]) | |
b7d7d917 | 1417 | |
43e9d192 IB |
1418 | ;; Half modes of all vector modes. |
1419 | (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") | |
1420 | (V4HI "V2HI") (V8HI "V4HI") | |
1421 | (V2SI "SI") (V4SI "V2SI") | |
1422 | (V2DI "DI") (V2SF "SF") | |
71a11456 | 1423 | (V4SF "V2SF") (V4HF "V2HF") |
abbe1ed2 SMW |
1424 | (V8HF "V4HF") (V2DF "DF") |
1425 | (V8BF "V4BF")]) | |
43e9d192 | 1426 | |
b1b49824 MC |
1427 | ;; Half modes of all vector modes, in lower-case. |
1428 | (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") | |
1429 | (V4HI "v2hi") (V8HI "v4hi") | |
abbe1ed2 | 1430 | (V8HF "v4hf") (V8BF "v4bf") |
b1b49824 MC |
1431 | (V2SI "si") (V4SI "v2si") |
1432 | (V2DI "di") (V2SF "sf") | |
1433 | (V4SF "v2sf") (V2DF "df")]) | |
1434 | ||
5ba864c5 AC |
1435 | ;; Single-element half modes of quad vector modes. |
1436 | (define_mode_attr V1HALF [(V2DI "V1DI") (V2DF "V1DF")]) | |
1437 | ||
1438 | ;; Single-element half modes of quad vector modes, in lower-case | |
1439 | (define_mode_attr V1half [(V2DI "v1di") (V2DF "v1df")]) | |
1440 | ||
43e9d192 IB |
1441 | ;; Double modes of vector modes. |
1442 | (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") | |
e603cd43 | 1443 | (V4HF "V8HF") (V4BF "V8BF") |
43e9d192 | 1444 | (V2SI "V4SI") (V2SF "V4SF") |
83d7e720 RS |
1445 | (SI "V2SI") (SF "V2SF") |
1446 | (DI "V2DI") (DF "V2DF")]) | |
43e9d192 | 1447 | |
922f9c25 AL |
1448 | ;; Register suffix for double-length mode. |
1449 | (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) | |
1450 | ||
43e9d192 IB |
1451 | ;; Double modes of vector modes (lower case). |
1452 | (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") | |
e603cd43 | 1453 | (V4HF "v8hf") (V4BF "v8bf") |
43e9d192 | 1454 | (V2SI "v4si") (V2SF "v4sf") |
8b033a8a SN |
1455 | (SI "v2si") (DI "v2di") |
1456 | (DF "v2df")]) | |
43e9d192 | 1457 | |
b1b49824 MC |
1458 | ;; Modes with double-width elements. |
1459 | (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") | |
1460 | (V4HI "V2SI") (V8HI "V4SI") | |
1461 | (V2SI "DI") (V4SI "V2DI")]) | |
1462 | ||
b327cbe8 KT |
1463 | (define_mode_attr VQUADW [(V8QI "V4SI") (V16QI "V8SI") |
1464 | (V4HI "V2DI") (V8HI "V4DI")]) | |
1465 | ||
43e9d192 IB |
1466 | ;; Narrowed modes for VDN. |
1467 | (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") | |
1468 | (DI "V2SI")]) | |
d8a88cda JW |
1469 | (define_mode_attr Vnarrowd [(V4HI "v8qi") (V2SI "v4hi") |
1470 | (DI "v2si")]) | |
43e9d192 IB |
1471 | |
1472 | ;; Narrowed double-modes for VQN (Used for XTN). | |
1473 | (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") | |
1474 | (V2DI "V2SI") | |
1475 | (DI "SI") (SI "HI") | |
1476 | (HI "QI")]) | |
9c437a10 RS |
1477 | (define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi") |
1478 | (V2DI "v2si")]) | |
43e9d192 IB |
1479 | |
1480 | ;; Narrowed quad-modes for VQN (Used for XTN2). | |
1481 | (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") | |
1482 | (V2DI "V4SI")]) | |
1483 | ||
0a09a948 RS |
1484 | ;; Narrowed modes of vector modes. |
1485 | (define_mode_attr VNARROW [(VNx8HI "VNx16QI") | |
1486 | (VNx4SI "VNx8HI") (VNx4SF "VNx8HF") | |
1487 | (VNx2DI "VNx4SI") (VNx2DF "VNx4SF")]) | |
1488 | ||
43e9d192 IB |
1489 | ;; Register suffix narrowed modes for VQN. |
1490 | (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") | |
1491 | (V2DI "2s")]) | |
1492 | ||
1493 | ;; Register suffix narrowed modes for VQN. | |
1494 | (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") | |
1495 | (V2DI "4s")]) | |
1496 | ||
1497 | ;; Widened modes of vector modes. | |
43cacb12 RS |
1498 | (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") |
1499 | (V2SI "V2DI") (V16QI "V8HI") | |
1500 | (V8HI "V4SI") (V4SI "V2DI") | |
1501 | (HI "SI") (SI "DI") | |
1502 | (V8HF "V4SF") (V4SF "V2DF") | |
1503 | (V4HF "V4SF") (V2SF "V2DF") | |
1504 | (VNx8HF "VNx4SF") (VNx4SF "VNx2DF") | |
1505 | (VNx16QI "VNx8HI") (VNx8HI "VNx4SI") | |
1506 | (VNx4SI "VNx2DI") | |
1507 | (VNx16BI "VNx8BI") (VNx8BI "VNx4BI") | |
1508 | (VNx4BI "VNx2BI")]) | |
1509 | ||
84152985 KT |
1510 | ;; Modes with the same number of elements but strictly 2x the width. |
1511 | (define_mode_attr V2XWIDE [(V8QI "V8HI") (V4HI "V4SI") | |
1512 | (V16QI "V16HI") (V8HI "V8SI") | |
1513 | (V2SI "V2DI") (V4SI "V4DI") | |
d20b2ad8 KT |
1514 | (V2DI "V2TI") (DI "TI") |
1515 | (HI "SI") (SI "DI")]) | |
84152985 | 1516 | |
43cacb12 RS |
1517 | ;; Predicate mode associated with VWIDE. |
1518 | (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")]) | |
43e9d192 | 1519 | |
03873eb9 | 1520 | ;; Widened modes of vector modes, lowercase |
43cacb12 RS |
1521 | (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf") |
1522 | (VNx16QI "vnx8hi") (VNx8HI "vnx4si") | |
1523 | (VNx4SI "vnx2di") | |
1524 | (VNx8HF "vnx4sf") (VNx4SF "vnx2df") | |
1525 | (VNx16BI "vnx8bi") (VNx8BI "vnx4bi") | |
1526 | (VNx4BI "vnx2bi")]) | |
03873eb9 AL |
1527 | |
1528 | ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. | |
43e9d192 | 1529 | (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") |
ad260343 | 1530 | (V2SI "2d") (V16QI "8h") |
03873eb9 AL |
1531 | (V8HI "4s") (V4SI "2d") |
1532 | (V8HF "4s") (V4SF "2d")]) | |
43e9d192 | 1533 | |
cb995de6 KT |
1534 | ;; Widened scalar register suffixes. |
1535 | (define_mode_attr Vwstype [(V8QI "h") (V4HI "s") | |
1536 | (V2SI "") (V16QI "h") | |
1537 | (V8HI "s") (V4SI "d")]) | |
1538 | ;; Add a .1d for V2SI. | |
1539 | (define_mode_attr Vwsuf [(V8QI "") (V4HI "") | |
1540 | (V2SI ".1d") (V16QI "") | |
1541 | (V8HI "") (V4SI "")]) | |
1542 | ||
1543 | ;; Scalar mode of widened vector reduction. | |
1544 | (define_mode_attr VWIDE_S [(V8QI "HI") (V4HI "SI") | |
1545 | (V2SI "DI") (V16QI "HI") | |
1546 | (V8HI "SI") (V4SI "DI")]) | |
1547 | ||
b327cbe8 KT |
1548 | (define_mode_attr VWIDE2X_S [(V8QI "SI") (V4HI "DI") |
1549 | (V16QI "SI") (V8HI "DI")]) | |
1550 | ||
e811f10b KT |
1551 | ;; Widened mode with half the element register suffixes for VD_BHSI/VQW/VQ_HSF. |
1552 | (define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s") | |
1553 | (V2SI "1d") (V16QI "8h") | |
1554 | (V8HI "4s") (V4SI "2d")]) | |
1555 | ||
0a09a948 RS |
1556 | ;; SVE vector after narrowing. |
1557 | (define_mode_attr Ventype [(VNx8HI "b") | |
1558 | (VNx4SI "h") (VNx4SF "h") | |
1559 | (VNx2DI "s") (VNx2DF "s")]) | |
1560 | ||
1561 | ;; SVE vector after widening. | |
43cacb12 RS |
1562 | (define_mode_attr Vewtype [(VNx16QI "h") |
1563 | (VNx8HI "s") (VNx8HF "s") | |
0a09a948 RS |
1564 | (VNx4SI "d") (VNx4SF "d") |
1565 | (VNx2DI "q")]) | |
43cacb12 | 1566 | |
43e9d192 IB |
1567 | ;; Widened mode register suffixes for VDW/VQW. |
1568 | (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") | |
ad260343 | 1569 | (V2SI ".2d") (V16QI ".8h") |
43e9d192 | 1570 | (V8HI ".4s") (V4SI ".2d") |
922f9c25 | 1571 | (V4HF ".4s") (V2SF ".2d") |
43e9d192 IB |
1572 | (SI "") (HI "")]) |
1573 | ||
03873eb9 | 1574 | ;; Lower part register suffixes for VQW/VQ_HSF. |
43e9d192 | 1575 | (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") |
03873eb9 AL |
1576 | (V4SI "2s") (V8HF "4h") |
1577 | (V4SF "2s")]) | |
43e9d192 | 1578 | |
83d7e720 RS |
1579 | ;; Whether a mode fits in W or X registers (i.e. "w" for 32-bit modes |
1580 | ;; and "x" for 64-bit modes). | |
1581 | (define_mode_attr single_wx [(SI "w") (SF "w") | |
1582 | (V8QI "x") (V4HI "x") | |
1583 | (V4HF "x") (V4BF "x") | |
1584 | (V2SI "x") (V2SF "x") | |
1585 | (DI "x") (DF "x")]) | |
1586 | ||
1587 | ;; Whether a mode fits in S or D registers (i.e. "s" for 32-bit modes | |
1588 | ;; and "d" for 64-bit modes). | |
1589 | (define_mode_attr single_type [(SI "s") (SF "s") | |
1590 | (V8QI "d") (V4HI "d") | |
1591 | (V4HF "d") (V4BF "d") | |
1592 | (V2SI "d") (V2SF "d") | |
1593 | (DI "d") (DF "d")]) | |
1594 | ||
1595 | ;; Whether a double-width mode fits in D or Q registers (i.e. "d" for | |
1596 | ;; 32-bit modes and "q" for 64-bit modes). | |
1597 | (define_mode_attr single_dtype [(SI "d") (SF "d") | |
1598 | (V8QI "q") (V4HI "q") | |
1599 | (V4HF "q") (V4BF "q") | |
1600 | (V2SI "q") (V2SF "q") | |
1601 | (DI "q") (DF "q")]) | |
1602 | ||
43e9d192 | 1603 | ;; Define corresponding core/FP element mode for each vector mode. |
cc68f7c2 RS |
1604 | (define_mode_attr vw [(V8QI "w") (V16QI "w") |
1605 | (V4HI "w") (V8HI "w") | |
1606 | (V2SI "w") (V4SI "w") | |
1607 | (DI "x") (V2DI "x") | |
1608 | (V2SF "s") (V4SF "s") | |
1609 | (V2DF "d")]) | |
43e9d192 | 1610 | |
66adb8eb JG |
1611 | ;; Corresponding core element mode for each vector mode. This is a |
1612 | ;; variation on <vw> mapping FP modes to GP regs. | |
cc68f7c2 RS |
1613 | (define_mode_attr vwcore [(V8QI "w") (V16QI "w") |
1614 | (V4HI "w") (V8HI "w") | |
1615 | (V2SI "w") (V4SI "w") | |
1616 | (DI "x") (V2DI "x") | |
1617 | (V4HF "w") (V8HF "w") | |
5320d4e4 | 1618 | (V4BF "w") (V8BF "w") |
cc68f7c2 RS |
1619 | (V2SF "w") (V4SF "w") |
1620 | (V2DF "x") | |
1621 | (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w") | |
1622 | (VNx8HI "w") (VNx4HI "w") (VNx2HI "w") | |
1623 | (VNx8HF "w") (VNx4HF "w") (VNx2HF "w") | |
6c3ce63b | 1624 | (VNx8BF "w") (VNx4BF "w") (VNx2BF "w") |
cc68f7c2 RS |
1625 | (VNx4SI "w") (VNx2SI "w") |
1626 | (VNx4SF "w") (VNx2SF "w") | |
1627 | (VNx2DI "x") | |
1628 | (VNx2DF "x")]) | |
66adb8eb | 1629 | |
30f8bf3d RS |
1630 | ;; Like vwcore, but for the container mode rather than the element mode. |
1631 | (define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x") | |
1632 | (VNx8HI "w") (VNx4HI "w") (VNx2HI "x") | |
1633 | (VNx4SI "w") (VNx2SI "x") | |
1634 | (VNx2DI "x")]) | |
1635 | ||
43e9d192 IB |
1636 | ;; Double vector types for ALLX. |
1637 | (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) | |
1638 | ||
5f565314 RS |
1639 | ;; Mode with floating-point values replaced by like-sized integers. |
1640 | (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") | |
1641 | (V4HI "V4HI") (V8HI "V8HI") | |
1642 | (V2SI "V2SI") (V4SI "V4SI") | |
1643 | (DI "DI") (V2DI "V2DI") | |
1644 | (V4HF "V4HI") (V8HF "V8HI") | |
e603cd43 | 1645 | (V4BF "V4HI") (V8BF "V8HI") |
5f565314 | 1646 | (V2SF "V2SI") (V4SF "V4SI") |
43cacb12 | 1647 | (DF "DI") (V2DF "V2DI") |
dfe1da23 JW |
1648 | (SF "SI") (SI "SI") |
1649 | (HF "HI") | |
43cacb12 RS |
1650 | (VNx16QI "VNx16QI") |
1651 | (VNx8HI "VNx8HI") (VNx8HF "VNx8HI") | |
02fcd8ac | 1652 | (VNx8BF "VNx8HI") |
43cacb12 RS |
1653 | (VNx4SI "VNx4SI") (VNx4SF "VNx4SI") |
1654 | (VNx2DI "VNx2DI") (VNx2DF "VNx2DI") | |
1655 | ]) | |
5f565314 RS |
1656 | |
1657 | ;; Lower case mode with floating-point values replaced by like-sized integers. | |
1658 | (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") | |
1659 | (V4HI "v4hi") (V8HI "v8hi") | |
1660 | (V2SI "v2si") (V4SI "v4si") | |
1661 | (DI "di") (V2DI "v2di") | |
1662 | (V4HF "v4hi") (V8HF "v8hi") | |
e603cd43 | 1663 | (V4BF "v4hi") (V8BF "v8hi") |
5f565314 | 1664 | (V2SF "v2si") (V4SF "v4si") |
43cacb12 RS |
1665 | (DF "di") (V2DF "v2di") |
1666 | (SF "si") | |
1667 | (VNx16QI "vnx16qi") | |
1668 | (VNx8HI "vnx8hi") (VNx8HF "vnx8hi") | |
02fcd8ac | 1669 | (VNx8BF "vnx8hi") |
43cacb12 RS |
1670 | (VNx4SI "vnx4si") (VNx4SF "vnx4si") |
1671 | (VNx2DI "vnx2di") (VNx2DF "vnx2di") | |
1672 | ]) | |
1673 | ||
1674 | ;; Floating-point equivalent of selected modes. | |
a70965b1 | 1675 | (define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF") |
02fcd8ac | 1676 | (VNx8BF "VNx8HF") |
a70965b1 | 1677 | (VNx4SI "VNx4SF") (VNx4SF "VNx4SF") |
43cacb12 | 1678 | (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")]) |
a70965b1 | 1679 | (define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf") |
02fcd8ac | 1680 | (VNx8BF "vnx8hf") |
a70965b1 | 1681 | (VNx4SI "vnx4sf") (VNx4SF "vnx4sf") |
43cacb12 | 1682 | (VNx2DI "vnx2df") (VNx2DF "vnx2df")]) |
70c67693 | 1683 | |
f8186eea RS |
1684 | ;; Maps full and partial vector modes of any element type to a full-vector |
1685 | ;; integer mode with the same number of units. | |
1686 | (define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI") | |
1687 | (VNx4QI "VNx4SI") (VNx2QI "VNx2DI") | |
1688 | (VNx8HI "VNx8HI") (VNx4HI "VNx4SI") | |
1689 | (VNx2HI "VNx2DI") | |
1690 | (VNx4SI "VNx4SI") (VNx2SI "VNx2DI") | |
1691 | (VNx2DI "VNx2DI") | |
1692 | (VNx8HF "VNx8HI") (VNx4HF "VNx4SI") | |
1693 | (VNx2HF "VNx2DI") | |
6c3ce63b RS |
1694 | (VNx8BF "VNx8HI") (VNx4BF "VNx4SI") |
1695 | (VNx2BF "VNx2DI") | |
3261d8ba | 1696 | (VNx4SF "VNx4SI") (VNx2SF "VNx2DI") |
f8186eea RS |
1697 | (VNx2DF "VNx2DI")]) |
1698 | ||
1699 | ;; Lower-case version of V_INT_CONTAINER. | |
1700 | (define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi") | |
1701 | (VNx4QI "vnx4si") (VNx2QI "vnx2di") | |
1702 | (VNx8HI "vnx8hi") (VNx4HI "vnx4si") | |
1703 | (VNx2HI "vnx2di") | |
1704 | (VNx4SI "vnx4si") (VNx2SI "vnx2di") | |
1705 | (VNx2DI "vnx2di") | |
1706 | (VNx8HF "vnx8hi") (VNx4HF "vnx4si") | |
1707 | (VNx2HF "vnx2di") | |
6c3ce63b RS |
1708 | (VNx8BF "vnx8hi") (VNx4BF "vnx4si") |
1709 | (VNx2BF "vnx2di") | |
f8186eea RS |
1710 | (VNx4SF "vnx4si") (VNx2SF "vnx2di") |
1711 | (VNx2DF "vnx2di")]) | |
1712 | ||
6c553b76 BC |
1713 | ;; Mode for vector conditional operations where the comparison has |
1714 | ;; different type from the lhs. | |
1715 | (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") | |
1716 | (V2DI "V2DF") (V2SF "V2SI") | |
1717 | (V4SF "V4SI") (V2DF "V2DI")]) | |
1718 | ||
1719 | (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf") | |
1720 | (V2DI "v2df") (V2SF "v2si") | |
1721 | (V4SF "v4si") (V2DF "v2di")]) | |
1722 | ||
cb23a30c JG |
1723 | ;; Lower case element modes (as used in shift immediate patterns). |
1724 | (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") | |
1725 | (V4HI "hi") (V8HI "hi") | |
1726 | (V2SI "si") (V4SI "si") | |
1727 | (DI "di") (V2DI "di") | |
1728 | (QI "qi") (HI "hi") | |
1729 | (SI "si")]) | |
1730 | ||
fdb904a1 KT |
1731 | ;; Like ve_mode but for the half-width modes. |
1732 | (define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")]) | |
1733 | ||
43e9d192 IB |
1734 | ;; Vm for lane instructions is restricted to FP_LO_REGS. |
1735 | (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") | |
1736 | (V2SI "w") (V4SI "w") (SI "w")]) | |
1737 | ||
66f206b8 JW |
1738 | (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V") |
1739 | (V2x8QI "T") (V2x16QI "T") | |
1740 | (V2x4HI "T") (V2x8HI "T") | |
1741 | (V2x2SI "T") (V2x4SI "T") | |
1742 | (V2x1DI "T") (V2x2DI "T") | |
1743 | (V2x4HF "T") (V2x8HF "T") | |
1744 | (V2x2SF "T") (V2x4SF "T") | |
1745 | (V2x1DF "T") (V2x2DF "T") | |
1746 | (V2x4BF "T") (V2x8BF "T") | |
1747 | (V3x8QI "U") (V3x16QI "U") | |
1748 | (V3x4HI "U") (V3x8HI "U") | |
1749 | (V3x2SI "U") (V3x4SI "U") | |
1750 | (V3x1DI "U") (V3x2DI "U") | |
1751 | (V3x4HF "U") (V3x8HF "U") | |
1752 | (V3x2SF "U") (V3x4SF "U") | |
1753 | (V3x1DF "U") (V3x2DF "U") | |
1754 | (V3x4BF "U") (V3x8BF "U") | |
1755 | (V4x8QI "V") (V4x16QI "V") | |
1756 | (V4x4HI "V") (V4x8HI "V") | |
1757 | (V4x2SI "V") (V4x4SI "V") | |
1758 | (V4x1DI "V") (V4x2DI "V") | |
1759 | (V4x4HF "V") (V4x8HF "V") | |
1760 | (V4x2SF "V") (V4x4SF "V") | |
1761 | (V4x1DF "V") (V4x2DF "V") | |
1762 | (V4x4BF "V") (V4x8BF "V")]) | |
43e9d192 | 1763 | |
97755701 AL |
1764 | ;; This is both the number of Q-Registers needed to hold the corresponding |
1765 | ;; opaque large integer mode, and the number of elements touched by the | |
1766 | ;; ld..._lane and st..._lane operations. | |
66f206b8 JW |
1767 | (define_mode_attr nregs [(OI "2") (CI "3") (XI "4") |
1768 | (V2x8QI "2") (V2x16QI "2") | |
1769 | (V2x4HI "2") (V2x8HI "2") | |
1770 | (V2x2SI "2") (V2x4SI "2") | |
1771 | (V2x1DI "2") (V2x2DI "2") | |
1772 | (V2x4HF "2") (V2x8HF "2") | |
1773 | (V2x2SF "2") (V2x4SF "2") | |
1774 | (V2x1DF "2") (V2x2DF "2") | |
1775 | (V2x4BF "2") (V2x8BF "2") | |
1776 | (V3x8QI "3") (V3x16QI "3") | |
1777 | (V3x4HI "3") (V3x8HI "3") | |
1778 | (V3x2SI "3") (V3x4SI "3") | |
1779 | (V3x1DI "3") (V3x2DI "3") | |
1780 | (V3x4HF "3") (V3x8HF "3") | |
1781 | (V3x2SF "3") (V3x4SF "3") | |
1782 | (V3x1DF "3") (V3x2DF "3") | |
1783 | (V3x4BF "3") (V3x8BF "3") | |
1784 | (V4x8QI "4") (V4x16QI "4") | |
1785 | (V4x4HI "4") (V4x8HI "4") | |
1786 | (V4x2SI "4") (V4x4SI "4") | |
1787 | (V4x1DI "4") (V4x2DI "4") | |
1788 | (V4x4HF "4") (V4x8HF "4") | |
1789 | (V4x2SF "4") (V4x4SF "4") | |
1790 | (V4x1DF "4") (V4x2DF "4") | |
1791 | (V4x4BF "4") (V4x8BF "4")]) | |
43e9d192 | 1792 | |
0462169c SN |
1793 | ;; Mode for atomic operation suffixes |
1794 | (define_mode_attr atomic_sfx | |
1795 | [(QI "b") (HI "h") (SI "") (DI "")]) | |
1796 | ||
3f598afe | 1797 | (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") |
2644d4d9 | 1798 | (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") |
daef0a8c JW |
1799 | (SF "si") (DF "di") (SI "sf") (DI "df") |
1800 | (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") | |
68ad28c3 | 1801 | (V8HI "v8hf") (HF "hi") (HI "hf")]) |
3f598afe | 1802 | (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") |
2644d4d9 | 1803 | (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") |
daef0a8c JW |
1804 | (SF "SI") (DF "DI") (SI "SF") (DI "DF") |
1805 | (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") | |
68ad28c3 | 1806 | (V8HI "V8HF") (HF "HI") (HI "HF")]) |
3f598afe | 1807 | |
0d35c5c2 VP |
1808 | |
1809 | ;; for the inequal width integer to fp conversions | |
d7f33f07 JW |
1810 | (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) |
1811 | (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) | |
42fc9a7f | 1812 | |
91bd4114 JG |
1813 | (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") |
1814 | (V4HI "V8HI") (V8HI "V4HI") | |
8ea6c1b8 | 1815 | (V8BF "V4BF") (V4BF "V8BF") |
91bd4114 JG |
1816 | (V2SI "V4SI") (V4SI "V2SI") |
1817 | (DI "V2DI") (V2DI "DI") | |
1818 | (V2SF "V4SF") (V4SF "V2SF") | |
862abc04 | 1819 | (V4HF "V8HF") (V8HF "V4HF") |
91bd4114 JG |
1820 | (DF "V2DF") (V2DF "DF")]) |
1821 | ||
1822 | (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") | |
1823 | (V4HI "to_128") (V8HI "to_64") | |
1824 | (V2SI "to_128") (V4SI "to_64") | |
1825 | (DI "to_128") (V2DI "to_64") | |
862abc04 | 1826 | (V4HF "to_128") (V8HF "to_64") |
91bd4114 | 1827 | (V2SF "to_128") (V4SF "to_64") |
8ea6c1b8 | 1828 | (V4BF "to_128") (V8BF "to_64") |
91bd4114 JG |
1829 | (DF "to_128") (V2DF "to_64")]) |
1830 | ||
779aea46 | 1831 | ;; For certain vector-by-element multiplication instructions we must |
6d06971d | 1832 | ;; constrain the 16-bit cases to use only V0-V15. This is covered by |
779aea46 JG |
1833 | ;; the 'x' constraint. All other modes may use the 'w' constraint. |
1834 | (define_mode_attr h_con [(V2SI "w") (V4SI "w") | |
1835 | (V4HI "x") (V8HI "x") | |
6d06971d | 1836 | (V4HF "x") (V8HF "x") |
779aea46 JG |
1837 | (V2SF "w") (V4SF "w") |
1838 | (V2DF "w") (DF "w")]) | |
1839 | ||
1840 | ;; Defined to 'f' for types whose element type is a float type. | |
1841 | (define_mode_attr f [(V8QI "") (V16QI "") | |
1842 | (V4HI "") (V8HI "") | |
1843 | (V2SI "") (V4SI "") | |
1844 | (DI "") (V2DI "") | |
ab2e8f01 | 1845 | (V4HF "f") (V8HF "f") |
779aea46 JG |
1846 | (V2SF "f") (V4SF "f") |
1847 | (V2DF "f") (DF "f")]) | |
1848 | ||
0f686aa9 JG |
1849 | ;; Defined to '_fp' for types whose element type is a float type. |
1850 | (define_mode_attr fp [(V8QI "") (V16QI "") | |
1851 | (V4HI "") (V8HI "") | |
1852 | (V2SI "") (V4SI "") | |
1853 | (DI "") (V2DI "") | |
ab2e8f01 | 1854 | (V4HF "_fp") (V8HF "_fp") |
0f686aa9 JG |
1855 | (V2SF "_fp") (V4SF "_fp") |
1856 | (V2DF "_fp") (DF "_fp") | |
1857 | (SF "_fp")]) | |
1858 | ||
a9e66678 JG |
1859 | ;; Defined to '_q' for 128-bit types. |
1860 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
0f686aa9 | 1861 | (V4HI "") (V8HI "_q") |
8ea6c1b8 | 1862 | (V4BF "") (V8BF "_q") |
0f686aa9 JG |
1863 | (V2SI "") (V4SI "_q") |
1864 | (DI "") (V2DI "_q") | |
71a11456 | 1865 | (V4HF "") (V8HF "_q") |
abbe1ed2 | 1866 | (V4BF "") (V8BF "_q") |
0f686aa9 | 1867 | (V2SF "") (V4SF "_q") |
a40c22c3 | 1868 | (V2DF "_q") |
66f206b8 JW |
1869 | (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "") |
1870 | (V2x8QI "") (V2x16QI "_q") | |
1871 | (V2x4HI "") (V2x8HI "_q") | |
1872 | (V2x2SI "") (V2x4SI "_q") | |
1873 | (V2x1DI "") (V2x2DI "_q") | |
1874 | (V2x4HF "") (V2x8HF "_q") | |
1875 | (V2x2SF "") (V2x4SF "_q") | |
1876 | (V2x1DF "") (V2x2DF "_q") | |
1877 | (V2x4BF "") (V2x8BF "_q") | |
1878 | (V3x8QI "") (V3x16QI "_q") | |
1879 | (V3x4HI "") (V3x8HI "_q") | |
1880 | (V3x2SI "") (V3x4SI "_q") | |
1881 | (V3x1DI "") (V3x2DI "_q") | |
1882 | (V3x4HF "") (V3x8HF "_q") | |
1883 | (V3x2SF "") (V3x4SF "_q") | |
1884 | (V3x1DF "") (V3x2DF "_q") | |
1885 | (V3x4BF "") (V3x8BF "_q") | |
1886 | (V4x8QI "") (V4x16QI "_q") | |
1887 | (V4x4HI "") (V4x8HI "_q") | |
1888 | (V4x2SI "") (V4x4SI "_q") | |
1889 | (V4x1DI "") (V4x2DI "_q") | |
1890 | (V4x4HF "") (V4x8HF "_q") | |
1891 | (V4x2SF "") (V4x4SF "_q") | |
1892 | (V4x1DF "") (V4x2DF "_q") | |
1893 | (V4x4BF "") (V4x8BF "_q")]) | |
a9e66678 | 1894 | |
83d7e720 RS |
1895 | ;; Equivalent of the "q" attribute for the <VDBL> mode. |
1896 | (define_mode_attr dblq [(SI "") (SF "") | |
1897 | (V8QI "_q") (V4HI "_q") | |
1898 | (V4HF "_q") (V4BF "_q") | |
1899 | (V2SI "_q") (V2SF "_q") | |
1900 | (DI "_q") (DF "_q")]) | |
1901 | ||
92835317 TB |
1902 | (define_mode_attr vp [(V8QI "v") (V16QI "v") |
1903 | (V4HI "v") (V8HI "v") | |
1904 | (V2SI "p") (V4SI "v") | |
703bbcdf JW |
1905 | (V2DI "p") (V2DF "p") |
1906 | (V2SF "p") (V4SF "v") | |
1907 | (V4HF "v") (V8HF "v")]) | |
92835317 | 1908 | |
9feeafd7 AM |
1909 | (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi") |
1910 | (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")]) | |
1911 | (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI") | |
1912 | (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")]) | |
5e32e83b | 1913 | |
7a08d813 TC |
1914 | |
1915 | ;; Register suffix for DOTPROD input types from the return type. | |
1916 | (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")]) | |
1917 | ||
f275d73a SMW |
1918 | ;; Register suffix for BFDOT input types from the return type. |
1919 | (define_mode_attr Vbfdottype [(V2SF "4h") (V4SF "8h")]) | |
1920 | ||
cd78b3dd | 1921 | ;; Sum of lengths of instructions needed to move vector registers of a mode. |
66f206b8 JW |
1922 | (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16") |
1923 | (V2x8QI "8") (V2x16QI "8") | |
1924 | (V2x4HI "8") (V2x8HI "8") | |
1925 | (V2x2SI "8") (V2x4SI "8") | |
1926 | (V2x1DI "8") (V2x2DI "8") | |
1927 | (V2x4HF "8") (V2x8HF "8") | |
1928 | (V2x2SF "8") (V2x4SF "8") | |
1929 | (V2x1DF "8") (V2x2DF "8") | |
1930 | (V2x4BF "8") (V2x8BF "8") | |
1931 | (V3x8QI "12") (V3x16QI "12") | |
1932 | (V3x4HI "12") (V3x8HI "12") | |
1933 | (V3x2SI "12") (V3x4SI "12") | |
1934 | (V3x1DI "12") (V3x2DI "12") | |
1935 | (V3x4HF "12") (V3x8HF "12") | |
1936 | (V3x2SF "12") (V3x4SF "12") | |
1937 | (V3x1DF "12") (V3x2DF "12") | |
1938 | (V3x4BF "12") (V3x8BF "12") | |
1939 | (V4x8QI "16") (V4x16QI "16") | |
1940 | (V4x4HI "16") (V4x8HI "16") | |
1941 | (V4x2SI "16") (V4x4SI "16") | |
1942 | (V4x1DI "16") (V4x2DI "16") | |
1943 | (V4x4HF "16") (V4x8HF "16") | |
1944 | (V4x2SF "16") (V4x4SF "16") | |
1945 | (V4x1DF "16") (V4x2DF "16") | |
1946 | (V4x4BF "16") (V4x8BF "16")]) | |
668046d1 | 1947 | |
1b1e81f8 JW |
1948 | ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. |
1949 | ;; No need of iterator for -fPIC as it use got_lo12 for both modes. | |
1950 | (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) | |
1951 | ||
27086ea3 MC |
1952 | ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub |
1953 | (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")]) | |
1954 | ||
f275d73a SMW |
1955 | ;; Width of 2nd and 3rd arguments to bf16 vector multiply add/sub |
1956 | (define_mode_attr VBFMLA_W [(V2SF "V4BF") (V4SF "V8BF")]) | |
1957 | ||
27086ea3 MC |
1958 | (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")]) |
1959 | ||
1960 | (define_mode_attr f16quad [(V2SF "") (V4SF "q")]) | |
1961 | ||
f275d73a | 1962 | (define_mode_attr isquadop [(V8QI "") (V16QI "q") (V4BF "") (V8BF "q")]) |
8c197c85 | 1963 | |
27086ea3 MC |
1964 | (define_code_attr f16mac [(plus "a") (minus "s")]) |
1965 | ||
8544ed6e KT |
1966 | ;; Map smax to smin and umax to umin. |
1967 | (define_code_attr max_opp [(smax "smin") (umax "umin")]) | |
1968 | ||
a9fad8fe AM |
1969 | ;; Same as above, but louder. |
1970 | (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) | |
1971 | ||
900945f6 OA |
1972 | ;; Map smax and umax to sign_extend and zero_extend |
1973 | (define_code_attr USMAX_EXT [(smax "sign_extend") (umax "zero_extend")]) | |
1974 | ||
9f4cbab8 RS |
1975 | ;; The number of subvectors in an SVE_STRUCT. |
1976 | (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") | |
1977 | (VNx8SI "2") (VNx4DI "2") | |
02fcd8ac | 1978 | (VNx16BF "2") |
9f4cbab8 RS |
1979 | (VNx16HF "2") (VNx8SF "2") (VNx4DF "2") |
1980 | (VNx48QI "3") (VNx24HI "3") | |
1981 | (VNx12SI "3") (VNx6DI "3") | |
02fcd8ac | 1982 | (VNx24BF "3") |
9f4cbab8 RS |
1983 | (VNx24HF "3") (VNx12SF "3") (VNx6DF "3") |
1984 | (VNx64QI "4") (VNx32HI "4") | |
1985 | (VNx16SI "4") (VNx8DI "4") | |
02fcd8ac | 1986 | (VNx32BF "4") |
9f4cbab8 RS |
1987 | (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")]) |
1988 | ||
1989 | ;; The number of instruction bytes needed for an SVE_STRUCT move. This is | |
1990 | ;; equal to vector_count * 4. | |
1991 | (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8") | |
1992 | (VNx8SI "8") (VNx4DI "8") | |
02fcd8ac | 1993 | (VNx16BF "8") |
9f4cbab8 RS |
1994 | (VNx16HF "8") (VNx8SF "8") (VNx4DF "8") |
1995 | (VNx48QI "12") (VNx24HI "12") | |
1996 | (VNx12SI "12") (VNx6DI "12") | |
02fcd8ac | 1997 | (VNx24BF "12") |
9f4cbab8 RS |
1998 | (VNx24HF "12") (VNx12SF "12") (VNx6DF "12") |
1999 | (VNx64QI "16") (VNx32HI "16") | |
2000 | (VNx16SI "16") (VNx8DI "16") | |
02fcd8ac | 2001 | (VNx32BF "16") |
9f4cbab8 RS |
2002 | (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")]) |
2003 | ||
2004 | ;; The type of a subvector in an SVE_STRUCT. | |
2005 | (define_mode_attr VSINGLE [(VNx32QI "VNx16QI") | |
2006 | (VNx16HI "VNx8HI") (VNx16HF "VNx8HF") | |
02fcd8ac | 2007 | (VNx16BF "VNx8BF") |
9f4cbab8 RS |
2008 | (VNx8SI "VNx4SI") (VNx8SF "VNx4SF") |
2009 | (VNx4DI "VNx2DI") (VNx4DF "VNx2DF") | |
2010 | (VNx48QI "VNx16QI") | |
2011 | (VNx24HI "VNx8HI") (VNx24HF "VNx8HF") | |
02fcd8ac | 2012 | (VNx24BF "VNx8BF") |
9f4cbab8 RS |
2013 | (VNx12SI "VNx4SI") (VNx12SF "VNx4SF") |
2014 | (VNx6DI "VNx2DI") (VNx6DF "VNx2DF") | |
2015 | (VNx64QI "VNx16QI") | |
2016 | (VNx32HI "VNx8HI") (VNx32HF "VNx8HF") | |
02fcd8ac | 2017 | (VNx32BF "VNx8BF") |
9f4cbab8 RS |
2018 | (VNx16SI "VNx4SI") (VNx16SF "VNx4SF") |
2019 | (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")]) | |
2020 | ||
2021 | ;; ...and again in lower case. | |
2022 | (define_mode_attr vsingle [(VNx32QI "vnx16qi") | |
2023 | (VNx16HI "vnx8hi") (VNx16HF "vnx8hf") | |
02fcd8ac | 2024 | (VNx16BF "vnx8bf") |
9f4cbab8 RS |
2025 | (VNx8SI "vnx4si") (VNx8SF "vnx4sf") |
2026 | (VNx4DI "vnx2di") (VNx4DF "vnx2df") | |
2027 | (VNx48QI "vnx16qi") | |
2028 | (VNx24HI "vnx8hi") (VNx24HF "vnx8hf") | |
02fcd8ac | 2029 | (VNx24BF "vnx8bf") |
9f4cbab8 RS |
2030 | (VNx12SI "vnx4si") (VNx12SF "vnx4sf") |
2031 | (VNx6DI "vnx2di") (VNx6DF "vnx2df") | |
2032 | (VNx64QI "vnx16qi") | |
2033 | (VNx32HI "vnx8hi") (VNx32HF "vnx8hf") | |
02fcd8ac | 2034 | (VNx32BF "vnx8bf") |
9f4cbab8 RS |
2035 | (VNx16SI "vnx4si") (VNx16SF "vnx4sf") |
2036 | (VNx8DI "vnx2di") (VNx8DF "vnx2df")]) | |
2037 | ||
2038 | ;; The predicate mode associated with an SVE data mode. For structure modes | |
2039 | ;; this is equivalent to the <VPRED> of the subvector mode. | |
cc68f7c2 RS |
2040 | (define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI") |
2041 | (VNx4QI "VNx4BI") (VNx2QI "VNx2BI") | |
2042 | (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI") | |
2043 | (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI") | |
6c3ce63b | 2044 | (VNx8BF "VNx8BI") (VNx4BF "VNx4BI") (VNx2BF "VNx2BI") |
cc68f7c2 RS |
2045 | (VNx4SI "VNx4BI") (VNx2SI "VNx2BI") |
2046 | (VNx4SF "VNx4BI") (VNx2SF "VNx2BI") | |
2047 | (VNx2DI "VNx2BI") | |
2048 | (VNx2DF "VNx2BI") | |
9f4cbab8 RS |
2049 | (VNx32QI "VNx16BI") |
2050 | (VNx16HI "VNx8BI") (VNx16HF "VNx8BI") | |
02fcd8ac | 2051 | (VNx16BF "VNx8BI") |
9f4cbab8 RS |
2052 | (VNx8SI "VNx4BI") (VNx8SF "VNx4BI") |
2053 | (VNx4DI "VNx2BI") (VNx4DF "VNx2BI") | |
2054 | (VNx48QI "VNx16BI") | |
2055 | (VNx24HI "VNx8BI") (VNx24HF "VNx8BI") | |
02fcd8ac | 2056 | (VNx24BF "VNx8BI") |
9f4cbab8 RS |
2057 | (VNx12SI "VNx4BI") (VNx12SF "VNx4BI") |
2058 | (VNx6DI "VNx2BI") (VNx6DF "VNx2BI") | |
2059 | (VNx64QI "VNx16BI") | |
2060 | (VNx32HI "VNx8BI") (VNx32HF "VNx8BI") | |
02fcd8ac | 2061 | (VNx32BF "VNx8BI") |
9f4cbab8 RS |
2062 | (VNx16SI "VNx4BI") (VNx16SF "VNx4BI") |
2063 | (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")]) | |
43cacb12 RS |
2064 | |
2065 | ;; ...and again in lower case. | |
cc68f7c2 RS |
2066 | (define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi") |
2067 | (VNx4QI "vnx4bi") (VNx2QI "vnx2bi") | |
2068 | (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi") | |
2069 | (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi") | |
6c3ce63b | 2070 | (VNx8BF "vnx8bi") (VNx4BF "vnx4bi") (VNx2BF "vnx2bi") |
cc68f7c2 RS |
2071 | (VNx4SI "vnx4bi") (VNx2SI "vnx2bi") |
2072 | (VNx4SF "vnx4bi") (VNx2SF "vnx2bi") | |
2073 | (VNx2DI "vnx2bi") | |
2074 | (VNx2DF "vnx2bi") | |
9f4cbab8 RS |
2075 | (VNx32QI "vnx16bi") |
2076 | (VNx16HI "vnx8bi") (VNx16HF "vnx8bi") | |
02fcd8ac | 2077 | (VNx16BF "vnx8bi") |
9f4cbab8 RS |
2078 | (VNx8SI "vnx4bi") (VNx8SF "vnx4bi") |
2079 | (VNx4DI "vnx2bi") (VNx4DF "vnx2bi") | |
2080 | (VNx48QI "vnx16bi") | |
2081 | (VNx24HI "vnx8bi") (VNx24HF "vnx8bi") | |
02fcd8ac | 2082 | (VNx24BF "vnx8bi") |
9f4cbab8 RS |
2083 | (VNx12SI "vnx4bi") (VNx12SF "vnx4bi") |
2084 | (VNx6DI "vnx2bi") (VNx6DF "vnx2bi") | |
2085 | (VNx64QI "vnx16bi") | |
2086 | (VNx32HI "vnx8bi") (VNx32HF "vnx4bi") | |
02fcd8ac | 2087 | (VNx32BF "vnx8bi") |
9f4cbab8 RS |
2088 | (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") |
2089 | (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) | |
43cacb12 | 2090 | |
0a09a948 RS |
2091 | (define_mode_attr VDOUBLE [(VNx16QI "VNx32QI") |
2092 | (VNx8HI "VNx16HI") (VNx8HF "VNx16HF") | |
02fcd8ac | 2093 | (VNx8BF "VNx16BF") |
0a09a948 RS |
2094 | (VNx4SI "VNx8SI") (VNx4SF "VNx8SF") |
2095 | (VNx2DI "VNx4DI") (VNx2DF "VNx4DF")]) | |
2096 | ||
9d63f43b TC |
2097 | ;; On AArch64 the By element instruction doesn't have a 2S variant. |
2098 | ;; However because the instruction always selects a pair of values | |
2099 | ;; The normal 3SAME instruction can be used here instead. | |
2100 | (define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]") | |
2101 | (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]") | |
2102 | ]) | |
2103 | ||
34467289 RS |
2104 | ;; The number of bytes controlled by a predicate |
2105 | (define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2") | |
2106 | (VNx4BI "4") (VNx2BI "8")]) | |
2107 | ||
624d0f07 RS |
2108 | ;; Two-nybble mask for partial vector modes: nunits, byte size. |
2109 | (define_mode_attr self_mask [(VNx8QI "0x81") | |
2110 | (VNx4QI "0x41") | |
2111 | (VNx2QI "0x21") | |
2112 | (VNx4HI "0x42") | |
2113 | (VNx2HI "0x22") | |
2114 | (VNx2SI "0x24")]) | |
2115 | ||
e58703e2 RS |
2116 | ;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above. |
2117 | (define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41") | |
2118 | (VNx2HI "0x21") | |
2119 | (VNx4SI "0x43") (VNx2SI "0x23") | |
624d0f07 RS |
2120 | (VNx2DI "0x27")]) |
2121 | ||
2122 | ;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index. | |
0a09a948 | 2123 | (define_mode_attr sve_lane_con [(VNx8HI "y") (VNx4SI "y") (VNx2DI "x") |
624d0f07 RS |
2124 | (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")]) |
2125 | ||
2126 | ;; The constraint to use for an SVE FCMLA lane index. | |
2127 | (define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")]) | |
2128 | ||
84152985 KT |
2129 | (define_mode_attr vec_or_offset [(V8QI "vec") (V16QI "vec") (V4HI "vec") |
2130 | (V8HI "vec") (V2SI "vec") (V4SI "vec") | |
2131 | (V2DI "vec") (DI "offset")]) | |
2132 | ||
43e9d192 IB |
2133 | ;; ------------------------------------------------------------------- |
2134 | ;; Code Iterators | |
2135 | ;; ------------------------------------------------------------------- | |
2136 | ||
2137 | ;; This code iterator allows the various shifts supported on the core | |
48f3f27f WD |
2138 | (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert rotate]) |
2139 | ||
2140 | ;; This code iterator allows all shifts except for rotates. | |
2141 | (define_code_iterator SHIFT_no_rotate [ashift ashiftrt lshiftrt]) | |
43e9d192 IB |
2142 | |
2143 | ;; This code iterator allows the shifts supported in arithmetic instructions | |
2144 | (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) | |
2145 | ||
462e6f9a ST |
2146 | (define_code_iterator SHIFTRT [ashiftrt lshiftrt]) |
2147 | ||
43e9d192 IB |
2148 | ;; Code iterator for logical operations |
2149 | (define_code_iterator LOGICAL [and ior xor]) | |
2150 | ||
25332d23 RS |
2151 | ;; LOGICAL with plus, for when | gets converted to +. |
2152 | (define_code_iterator LOGICAL_OR_PLUS [and ior xor plus]) | |
2153 | ||
43cacb12 RS |
2154 | ;; LOGICAL without AND. |
2155 | (define_code_iterator LOGICAL_OR [ior xor]) | |
2156 | ||
84be6032 AL |
2157 | ;; Code iterator for logical operations whose :nlogical works on SIMD registers. |
2158 | (define_code_iterator NLOGICAL [and ior]) | |
2159 | ||
3204ac98 KT |
2160 | ;; Code iterator for unary negate and bitwise complement. |
2161 | (define_code_iterator NEG_NOT [neg not]) | |
2162 | ||
43e9d192 IB |
2163 | ;; Code iterator for sign/zero extension |
2164 | (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) | |
87a80d27 | 2165 | (define_code_iterator ANY_EXTEND2 [sign_extend zero_extend]) |
43e9d192 IB |
2166 | |
2167 | ;; All division operations (signed/unsigned) | |
2168 | (define_code_iterator ANY_DIV [div udiv]) | |
2169 | ||
2170 | ;; Code iterator for sign/zero extraction | |
2171 | (define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) | |
2172 | ||
2173 | ;; Code iterator for equality comparisons | |
2174 | (define_code_iterator EQL [eq ne]) | |
2175 | ||
2176 | ;; Code iterator for less-than and greater/equal-to | |
2177 | (define_code_iterator LTGE [lt ge]) | |
2178 | ||
2179 | ;; Iterator for __sync_<op> operations that where the operation can be | |
2180 | ;; represented directly RTL. This is all of the sync operations bar | |
2181 | ;; nand. | |
0462169c | 2182 | (define_code_iterator atomic_op [plus minus ior xor and]) |
43e9d192 IB |
2183 | |
2184 | ;; Iterator for integer conversions | |
2185 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
2186 | ||
1709ff9b JG |
2187 | ;; Iterator for float conversions |
2188 | (define_code_iterator FLOATUORS [float unsigned_float]) | |
2189 | ||
43e9d192 IB |
2190 | ;; Code iterator for variants of vector max and min. |
2191 | (define_code_iterator MAXMIN [smax smin umax umin]) | |
2192 | ||
d758d190 KT |
2193 | ;; Code iterator for min/max ops but without UMAX. |
2194 | (define_code_iterator MAXMIN_NOUMAX [smax smin umin]) | |
2195 | ||
998eaf97 JG |
2196 | (define_code_iterator FMAXMIN [smax smin]) |
2197 | ||
8544ed6e KT |
2198 | ;; Signed and unsigned max operations. |
2199 | (define_code_iterator USMAX [smax umax]) | |
2200 | ||
dd550c99 | 2201 | ;; Code iterator for plus and minus. |
43e9d192 IB |
2202 | (define_code_iterator ADDSUB [plus minus]) |
2203 | ||
2204 | ;; Code iterator for variants of vector saturating binary ops. | |
2205 | (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) | |
2206 | ||
2207 | ;; Code iterator for variants of vector saturating unary ops. | |
2208 | (define_code_iterator UNQOPS [ss_neg ss_abs]) | |
2209 | ||
2210 | ;; Code iterator for signed variants of vector saturating binary ops. | |
2211 | (define_code_iterator SBINQOPS [ss_plus ss_minus]) | |
2212 | ||
624d0f07 RS |
2213 | ;; Code iterator for unsigned variants of vector saturating binary ops. |
2214 | (define_code_iterator UBINQOPS [us_plus us_minus]) | |
2215 | ||
2216 | ;; Modular and saturating addition. | |
2217 | (define_code_iterator ANY_PLUS [plus ss_plus us_plus]) | |
2218 | ||
2219 | ;; Saturating addition. | |
2220 | (define_code_iterator SAT_PLUS [ss_plus us_plus]) | |
2221 | ||
2222 | ;; Modular and saturating subtraction. | |
2223 | (define_code_iterator ANY_MINUS [minus ss_minus us_minus]) | |
2224 | ||
2225 | ;; Saturating subtraction. | |
2226 | (define_code_iterator SAT_MINUS [ss_minus us_minus]) | |
2227 | ||
889b9412 JG |
2228 | ;; Comparison operators for <F>CM. |
2229 | (define_code_iterator COMPARISONS [lt le eq ge gt]) | |
2230 | ||
2231 | ;; Unsigned comparison operators. | |
2232 | (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) | |
2233 | ||
75dd5ace JG |
2234 | ;; Unsigned comparison operators. |
2235 | (define_code_iterator FAC_COMPARISONS [lt le ge gt]) | |
2236 | ||
52cd1cd1 KT |
2237 | ;; Signed and unsigned saturating truncations. |
2238 | (define_code_iterator SAT_TRUNC [ss_truncate us_truncate]) | |
2239 | ||
ffb87344 KT |
2240 | (define_code_iterator ALL_TRUNC [ss_truncate us_truncate truncate]) |
2241 | ||
43cacb12 | 2242 | ;; SVE integer unary operations. |
0a09a948 RS |
2243 | (define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount |
2244 | (ss_abs "TARGET_SVE2") | |
2245 | (ss_neg "TARGET_SVE2")]) | |
43cacb12 | 2246 | |
a08acce8 | 2247 | ;; SVE integer binary operations. |
6c4fd4a9 | 2248 | (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin |
20103c0e | 2249 | ashift ashiftrt lshiftrt |
0a09a948 RS |
2250 | and ior xor |
2251 | (ss_plus "TARGET_SVE2") | |
2252 | (us_plus "TARGET_SVE2") | |
2253 | (ss_minus "TARGET_SVE2") | |
2254 | (us_minus "TARGET_SVE2")]) | |
9d4ac06e | 2255 | |
a08acce8 | 2256 | ;; SVE integer binary division operations. |
c38f7319 RS |
2257 | (define_code_iterator SVE_INT_BINARY_SD [div udiv]) |
2258 | ||
f8c22a8b RS |
2259 | ;; SVE integer binary operations that have an immediate form. |
2260 | (define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin]) | |
2261 | ||
740c1ed7 RS |
2262 | ;; SVE floating-point operations with an unpredicated all-register form. |
2263 | (define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult]) | |
2264 | ||
f22d7973 RS |
2265 | ;; SVE integer comparisons. |
2266 | (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu]) | |
2267 | ||
43e9d192 IB |
2268 | ;; ------------------------------------------------------------------- |
2269 | ;; Code Attributes | |
2270 | ;; ------------------------------------------------------------------- | |
2271 | ;; Map rtl objects to optab names | |
2272 | (define_code_attr optab [(ashift "ashl") | |
2273 | (ashiftrt "ashr") | |
2274 | (lshiftrt "lshr") | |
2275 | (rotatert "rotr") | |
48f3f27f | 2276 | (rotate "rotl") |
43e9d192 IB |
2277 | (sign_extend "extend") |
2278 | (zero_extend "zero_extend") | |
2279 | (sign_extract "extv") | |
2280 | (zero_extract "extzv") | |
384be29f JG |
2281 | (fix "fix") |
2282 | (unsigned_fix "fixuns") | |
1709ff9b JG |
2283 | (float "float") |
2284 | (unsigned_float "floatuns") | |
bca5a997 RS |
2285 | (clrsb "clrsb") |
2286 | (clz "clz") | |
43cacb12 | 2287 | (popcount "popcount") |
43e9d192 IB |
2288 | (and "and") |
2289 | (ior "ior") | |
2290 | (xor "xor") | |
2291 | (not "one_cmpl") | |
2292 | (neg "neg") | |
2293 | (plus "add") | |
2294 | (minus "sub") | |
6c4fd4a9 | 2295 | (mult "mul") |
c38f7319 RS |
2296 | (div "div") |
2297 | (udiv "udiv") | |
694e6b19 RS |
2298 | (ss_plus "ssadd") |
2299 | (us_plus "usadd") | |
2300 | (ss_minus "sssub") | |
2301 | (us_minus "ussub") | |
43e9d192 IB |
2302 | (ss_neg "qneg") |
2303 | (ss_abs "qabs") | |
43cacb12 RS |
2304 | (smin "smin") |
2305 | (smax "smax") | |
2306 | (umin "umin") | |
2307 | (umax "umax") | |
43e9d192 IB |
2308 | (eq "eq") |
2309 | (ne "ne") | |
2310 | (lt "lt") | |
889b9412 JG |
2311 | (ge "ge") |
2312 | (le "le") | |
2313 | (gt "gt") | |
2314 | (ltu "ltu") | |
2315 | (leu "leu") | |
2316 | (geu "geu") | |
43cacb12 | 2317 | (gtu "gtu") |
d45b20a5 | 2318 | (abs "abs")]) |
889b9412 | 2319 | |
694e6b19 RS |
2320 | (define_code_attr addsub [(ss_plus "add") |
2321 | (us_plus "add") | |
2322 | (ss_minus "sub") | |
2323 | (us_minus "sub")]) | |
2324 | ||
84152985 KT |
2325 | (define_code_attr SHIFTEXTEND [(ashiftrt "sign_extend") (lshiftrt "zero_extend")]) |
2326 | ||
ffb87344 KT |
2327 | (define_code_attr TRUNCEXTEND [(ss_truncate "sign_extend") |
2328 | (us_truncate "zero_extend") | |
2329 | (truncate "zero_extend")]) | |
2330 | ||
889b9412 JG |
2331 | ;; For comparison operators we use the FCM* and CM* instructions. |
2332 | ;; As there are no CMLE or CMLT instructions which act on 3 vector | |
2333 | ;; operands, we must use CMGE or CMGT and swap the order of the | |
2334 | ;; source operands. | |
2335 | ||
2336 | (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") | |
2337 | (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) | |
2338 | (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") | |
2339 | (ltu "2") (leu "2") (geu "1") (gtu "1")]) | |
2340 | (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") | |
2341 | (ltu "1") (leu "1") (geu "2") (gtu "2")]) | |
2342 | ||
2343 | (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") | |
714e1b3b KT |
2344 | (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") |
2345 | (gtu "GTU")]) | |
43e9d192 | 2346 | |
f22d7973 RS |
2347 | ;; The AArch64 condition associated with an rtl comparison code. |
2348 | (define_code_attr cmp_op [(lt "lt") | |
2349 | (le "le") | |
2350 | (eq "eq") | |
2351 | (ne "ne") | |
2352 | (ge "ge") | |
2353 | (gt "gt") | |
2354 | (ltu "lo") | |
2355 | (leu "ls") | |
2356 | (geu "hs") | |
2357 | (gtu "hi")]) | |
2358 | ||
384be29f JG |
2359 | (define_code_attr fix_trunc_optab [(fix "fix_trunc") |
2360 | (unsigned_fix "fixuns_trunc")]) | |
2361 | ||
43e9d192 IB |
2362 | ;; Optab prefix for sign/zero-extending operations |
2363 | (define_code_attr su_optab [(sign_extend "") (zero_extend "u") | |
2364 | (div "") (udiv "u") | |
2365 | (fix "") (unsigned_fix "u") | |
1709ff9b | 2366 | (float "s") (unsigned_float "u") |
43e9d192 IB |
2367 | (ss_plus "s") (us_plus "u") |
2368 | (ss_minus "s") (us_minus "u")]) | |
2369 | ||
2370 | ;; Similar for the instruction mnemonics | |
2371 | (define_code_attr shift [(ashift "lsl") (ashiftrt "asr") | |
48f3f27f WD |
2372 | (lshiftrt "lsr") (rotatert "ror") (rotate "ror")]) |
2373 | ;; True if shift is rotate left. | |
2374 | (define_code_attr is_rotl [(ashift "0") (ashiftrt "0") | |
2375 | (lshiftrt "0") (rotatert "0") (rotate "1")]) | |
43e9d192 | 2376 | |
462e6f9a ST |
2377 | ;; Op prefix for shift right and accumulate. |
2378 | (define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")]) | |
2379 | ||
e33aef11 TC |
2380 | ;; op prefix for shift right and narrow. |
2381 | (define_code_attr srn_op [(ashiftrt "r") (lshiftrt "")]) | |
2382 | ||
207db5d9 KT |
2383 | (define_code_attr shrn_s [(ashiftrt "s") (lshiftrt "")]) |
2384 | ||
43e9d192 IB |
2385 | ;; Map shift operators onto underlying bit-field instructions |
2386 | (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") | |
2387 | (lshiftrt "ubfx") (rotatert "extr")]) | |
2388 | ||
2389 | ;; Logical operator instruction mnemonics | |
2390 | (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) | |
2391 | ||
3204ac98 KT |
2392 | ;; Operation names for negate and bitwise complement. |
2393 | (define_code_attr neg_not_op [(neg "neg") (not "not")]) | |
2394 | ||
d572ad49 AC |
2395 | ;; csinv, csneg insn suffixes. |
2396 | (define_code_attr neg_not_cs [(neg "neg") (not "inv")]) | |
2397 | ||
43cacb12 | 2398 | ;; Similar, but when the second operand is inverted. |
43e9d192 IB |
2399 | (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) |
2400 | ||
43cacb12 RS |
2401 | ;; Similar, but when both operands are inverted. |
2402 | (define_code_attr logical_nn [(and "nor") (ior "nand")]) | |
2403 | ||
43e9d192 IB |
2404 | ;; Sign- or zero-extending data-op |
2405 | (define_code_attr su [(sign_extend "s") (zero_extend "u") | |
2406 | (sign_extract "s") (zero_extract "u") | |
2407 | (fix "s") (unsigned_fix "u") | |
998eaf97 JG |
2408 | (div "s") (udiv "u") |
2409 | (smax "s") (umax "u") | |
52cd1cd1 KT |
2410 | (smin "s") (umin "u") |
2411 | (ss_truncate "s") (us_truncate "u")]) | |
43e9d192 | 2412 | |
624d0f07 RS |
2413 | ;; "s" for signed ops, empty for unsigned ones. |
2414 | (define_code_attr s [(sign_extend "s") (zero_extend "")]) | |
2415 | ||
2416 | ;; Map signed/unsigned ops to the corresponding extension. | |
2417 | (define_code_attr paired_extend [(ss_plus "sign_extend") | |
2418 | (us_plus "zero_extend") | |
2419 | (ss_minus "sign_extend") | |
2420 | (us_minus "zero_extend")]) | |
2421 | ||
ffb87344 KT |
2422 | (define_code_attr TRUNC_SHIFT [(ss_truncate "ashiftrt") |
2423 | (us_truncate "lshiftrt") (truncate "lshiftrt")]) | |
2424 | ||
2425 | (define_code_attr shrn_op [(ss_truncate "sq") | |
2426 | (us_truncate "uq") (truncate "")]) | |
2427 | ||
43cacb12 RS |
2428 | ;; Whether a shift is left or right. |
2429 | (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")]) | |
2430 | ||
096e8448 JW |
2431 | ;; Emit conditional branch instructions. |
2432 | (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) | |
2433 | ||
43e9d192 IB |
2434 | ;; Emit cbz/cbnz depending on comparison type. |
2435 | (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) | |
2436 | ||
973d2e01 TP |
2437 | ;; Emit inverted cbz/cbnz depending on comparison type. |
2438 | (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) | |
2439 | ||
43e9d192 IB |
2440 | ;; Emit tbz/tbnz depending on comparison type. |
2441 | (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) | |
2442 | ||
973d2e01 TP |
2443 | ;; Emit inverted tbz/tbnz depending on comparison type. |
2444 | (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) | |
2445 | ||
43e9d192 | 2446 | ;; Max/min attributes. |
998eaf97 JG |
2447 | (define_code_attr maxmin [(smax "max") |
2448 | (smin "min") | |
2449 | (umax "max") | |
2450 | (umin "min")]) | |
43e9d192 | 2451 | |
88195141 KT |
2452 | (define_code_attr maxminand [(smax "bic") (smin "and")]) |
2453 | ||
43e9d192 IB |
2454 | ;; MLA/MLS attributes. |
2455 | (define_code_attr as [(ss_plus "a") (ss_minus "s")]) | |
2456 | ||
0462169c SN |
2457 | ;; Atomic operations |
2458 | (define_code_attr atomic_optab | |
2459 | [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) | |
2460 | ||
2461 | (define_code_attr atomic_op_operand | |
2462 | [(ior "aarch64_logical_operand") | |
2463 | (xor "aarch64_logical_operand") | |
2464 | (and "aarch64_logical_operand") | |
2465 | (plus "aarch64_plus_operand") | |
2466 | (minus "aarch64_plus_operand")]) | |
43e9d192 | 2467 | |
356c32e2 MW |
2468 | ;; Constants acceptable for atomic operations. |
2469 | ;; This definition must appear in this file before the iterators it refers to. | |
2470 | (define_code_attr const_atomic | |
2471 | [(plus "IJ") (minus "IJ") | |
2472 | (xor "<lconst_atomic>") (ior "<lconst_atomic>") | |
2473 | (and "<lconst_atomic>")]) | |
2474 | ||
2475 | ;; Attribute to describe constants acceptable in atomic logical operations | |
2476 | (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) | |
2477 | ||
43cacb12 RS |
2478 | ;; The integer SVE instruction that implements an rtx code. |
2479 | (define_code_attr sve_int_op [(plus "add") | |
9d4ac06e | 2480 | (minus "sub") |
6c4fd4a9 | 2481 | (mult "mul") |
c38f7319 RS |
2482 | (div "sdiv") |
2483 | (udiv "udiv") | |
69c5fdcf | 2484 | (abs "abs") |
43cacb12 RS |
2485 | (neg "neg") |
2486 | (smin "smin") | |
2487 | (smax "smax") | |
2488 | (umin "umin") | |
2489 | (umax "umax") | |
20103c0e RS |
2490 | (ashift "lsl") |
2491 | (ashiftrt "asr") | |
2492 | (lshiftrt "lsr") | |
43cacb12 RS |
2493 | (and "and") |
2494 | (ior "orr") | |
2495 | (xor "eor") | |
2496 | (not "not") | |
bca5a997 RS |
2497 | (clrsb "cls") |
2498 | (clz "clz") | |
0a09a948 RS |
2499 | (popcount "cnt") |
2500 | (ss_plus "sqadd") | |
2501 | (us_plus "uqadd") | |
2502 | (ss_minus "sqsub") | |
2503 | (us_minus "uqsub") | |
2504 | (ss_neg "sqneg") | |
2505 | (ss_abs "sqabs")]) | |
43cacb12 | 2506 | |
a08acce8 | 2507 | (define_code_attr sve_int_op_rev [(plus "add") |
20103c0e RS |
2508 | (minus "subr") |
2509 | (mult "mul") | |
2510 | (div "sdivr") | |
2511 | (udiv "udivr") | |
2512 | (smin "smin") | |
2513 | (smax "smax") | |
2514 | (umin "umin") | |
2515 | (umax "umax") | |
2516 | (ashift "lslr") | |
2517 | (ashiftrt "asrr") | |
2518 | (lshiftrt "lsrr") | |
2519 | (and "and") | |
2520 | (ior "orr") | |
0a09a948 RS |
2521 | (xor "eor") |
2522 | (ss_plus "sqadd") | |
2523 | (us_plus "uqadd") | |
2524 | (ss_minus "sqsubr") | |
2525 | (us_minus "uqsubr")]) | |
a08acce8 | 2526 | |
43cacb12 RS |
2527 | ;; The floating-point SVE instruction that implements an rtx code. |
2528 | (define_code_attr sve_fp_op [(plus "fadd") | |
740c1ed7 | 2529 | (minus "fsub") |
d45b20a5 | 2530 | (mult "fmul")]) |
43cacb12 | 2531 | |
f22d7973 | 2532 | ;; The SVE immediate constraint to use for an rtl code. |
f8c22a8b RS |
2533 | (define_code_attr sve_imm_con [(mult "vsm") |
2534 | (smax "vsm") | |
2535 | (smin "vsm") | |
2536 | (umax "vsb") | |
2537 | (umin "vsb") | |
2538 | (eq "vsc") | |
f22d7973 RS |
2539 | (ne "vsc") |
2540 | (lt "vsc") | |
2541 | (ge "vsc") | |
2542 | (le "vsc") | |
2543 | (gt "vsc") | |
2544 | (ltu "vsd") | |
2545 | (leu "vsd") | |
2546 | (geu "vsd") | |
2547 | (gtu "vsd")]) | |
2548 | ||
f8c22a8b RS |
2549 | ;; The prefix letter to use when printing an immediate operand. |
2550 | (define_code_attr sve_imm_prefix [(mult "") | |
2551 | (smax "") | |
2552 | (smin "") | |
2553 | (umax "D") | |
2554 | (umin "D")]) | |
2555 | ||
d113ece6 RS |
2556 | ;; The predicate to use for the second input operand in a cond_<optab><mode> |
2557 | ;; pattern. | |
2558 | (define_code_attr sve_pred_int_rhs2_operand | |
2559 | [(plus "register_operand") | |
2560 | (minus "register_operand") | |
2561 | (mult "register_operand") | |
2562 | (smax "register_operand") | |
2563 | (umax "register_operand") | |
2564 | (smin "register_operand") | |
2565 | (umin "register_operand") | |
20103c0e RS |
2566 | (ashift "aarch64_sve_lshift_operand") |
2567 | (ashiftrt "aarch64_sve_rshift_operand") | |
2568 | (lshiftrt "aarch64_sve_rshift_operand") | |
d113ece6 RS |
2569 | (and "aarch64_sve_pred_and_operand") |
2570 | (ior "register_operand") | |
0a09a948 RS |
2571 | (xor "register_operand") |
2572 | (ss_plus "register_operand") | |
2573 | (us_plus "register_operand") | |
2574 | (ss_minus "register_operand") | |
2575 | (us_minus "register_operand")]) | |
d113ece6 | 2576 | |
624d0f07 RS |
2577 | (define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec") |
2578 | (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")]) | |
2579 | ||
43e9d192 IB |
2580 | ;; ------------------------------------------------------------------- |
2581 | ;; Int Iterators. | |
2582 | ;; ------------------------------------------------------------------- | |
75add2d0 | 2583 | |
43e9d192 IB |
2584 | (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV |
2585 | UNSPEC_SMAXV UNSPEC_SMINV]) | |
2586 | ||
998eaf97 JG |
2587 | (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV |
2588 | UNSPEC_FMAXNMV UNSPEC_FMINNMV]) | |
43e9d192 | 2589 | |
e32b9eb3 RS |
2590 | (define_int_iterator FMAXMINNMV [UNSPEC_FMAXNMV UNSPEC_FMINNMV]) |
2591 | ||
624d0f07 RS |
2592 | (define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV]) |
2593 | ||
43cacb12 RS |
2594 | (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) |
2595 | ||
43e9d192 IB |
2596 | (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD |
2597 | UNSPEC_SRHADD UNSPEC_URHADD | |
2e828dfe | 2598 | UNSPEC_SHSUB UNSPEC_UHSUB]) |
43e9d192 | 2599 | |
42addb5a RS |
2600 | (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD]) |
2601 | ||
2602 | (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD]) | |
2603 | ||
2d57b12e YW |
2604 | (define_int_iterator BSL_DUP [1 2]) |
2605 | ||
7a08d813 | 2606 | (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) |
43e9d192 | 2607 | |
8c197c85 | 2608 | (define_int_iterator DOTPROD_I8MM [UNSPEC_USDOT UNSPEC_SUDOT]) |
36696774 | 2609 | (define_int_iterator DOTPROD_US_ONLY [UNSPEC_USDOT]) |
8c197c85 | 2610 | |
1efafef3 TC |
2611 | (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN |
2612 | UNSPEC_FMAXNM UNSPEC_FMINNM]) | |
202d0c11 | 2613 | |
8fc16d72 ST |
2614 | (define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP |
2615 | UNSPEC_PACIBSP UNSPEC_AUTIBSP]) | |
db58fd89 | 2616 | |
8fc16d72 ST |
2617 | (define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716 |
2618 | UNSPEC_PACIB1716 UNSPEC_AUTIB1716]) | |
db58fd89 | 2619 | |
43e9d192 IB |
2620 | (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) |
2621 | ||
58cc9876 YW |
2622 | (define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS |
2623 | UNSPEC_SMULHRS UNSPEC_UMULHRS]) | |
2624 | ||
43e9d192 IB |
2625 | (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) |
2626 | ||
43e9d192 IB |
2627 | (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL |
2628 | UNSPEC_SRSHL UNSPEC_URSHL]) | |
2629 | ||
2630 | (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) | |
2631 | ||
2632 | (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL | |
2633 | UNSPEC_SQRSHL UNSPEC_UQRSHL]) | |
2634 | ||
84152985 | 2635 | (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA]) |
43e9d192 IB |
2636 | |
2637 | (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI | |
2638 | UNSPEC_SSRI UNSPEC_USRI]) | |
2639 | ||
2640 | ||
2641 | (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) | |
2642 | ||
2643 | (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) | |
2644 | ||
57b26d65 MW |
2645 | (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) |
2646 | ||
cc4d934f JG |
2647 | (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
2648 | UNSPEC_TRN1 UNSPEC_TRN2 | |
2649 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
43e9d192 | 2650 | |
36696774 RS |
2651 | (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q |
2652 | UNSPEC_TRN1Q UNSPEC_TRN2Q | |
2653 | UNSPEC_UZP1Q UNSPEC_UZP2Q]) | |
2654 | ||
43cacb12 RS |
2655 | (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
2656 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
2657 | ||
923fcec3 AL |
2658 | (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) |
2659 | ||
42fc9a7f | 2660 | (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM |
0659ce6f JG |
2661 | UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX |
2662 | UNSPEC_FRINTA]) | |
42fc9a7f JG |
2663 | |
2664 | (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM | |
ce966824 | 2665 | UNSPEC_FRINTA UNSPEC_FRINTN]) |
42fc9a7f | 2666 | |
3f598afe JW |
2667 | (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) |
2668 | (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) | |
2669 | ||
5d357f26 KT |
2670 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
2671 | UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH | |
2672 | UNSPEC_CRC32CW UNSPEC_CRC32CX]) | |
2673 | ||
5a7a4e80 TB |
2674 | (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) |
2675 | (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) | |
2676 | ||
30442682 TB |
2677 | (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) |
2678 | ||
b9cb0a44 TB |
2679 | (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) |
2680 | ||
27086ea3 MC |
2681 | (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2]) |
2682 | ||
2683 | (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B | |
2684 | UNSPEC_SM3TT2A UNSPEC_SM3TT2B]) | |
2685 | ||
2686 | (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2]) | |
2687 | ||
2688 | ;; Iterators for fp16 operations | |
2689 | ||
2690 | (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL]) | |
2691 | ||
2692 | (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2]) | |
2693 | ||
43cacb12 RS |
2694 | (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI |
2695 | UNSPEC_UNPACKSLO UNSPEC_UNPACKULO]) | |
2696 | ||
2697 | (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI]) | |
2698 | ||
11e9443f RS |
2699 | (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) |
2700 | ||
624d0f07 RS |
2701 | (define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB]) |
2702 | ||
2703 | (define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB]) | |
2704 | ||
2705 | (define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB | |
2706 | UNSPEC_REVH UNSPEC_REVW]) | |
2707 | ||
2708 | (define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE]) | |
2709 | ||
2710 | (define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA]) | |
2711 | ||
0a09a948 RS |
2712 | (define_int_iterator SVE_INT_SHIFT_IMM [UNSPEC_ASRD |
2713 | (UNSPEC_SQSHLU "TARGET_SVE2") | |
2714 | (UNSPEC_SRSHR "TARGET_SVE2") | |
2715 | (UNSPEC_URSHR "TARGET_SVE2")]) | |
2716 | ||
624d0f07 RS |
2717 | (define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS]) |
2718 | ||
2719 | (define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL]) | |
d7a09c44 | 2720 | |
896dff99 RS |
2721 | (define_int_iterator SVE_BFLOAT_TERNARY_LONG [UNSPEC_BFDOT |
2722 | UNSPEC_BFMLALB | |
2723 | UNSPEC_BFMLALT | |
2724 | UNSPEC_BFMMLA]) | |
2725 | ||
2726 | (define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE [UNSPEC_BFDOT | |
2727 | UNSPEC_BFMLALB | |
2728 | UNSPEC_BFMLALT]) | |
2729 | ||
b0760a40 RS |
2730 | (define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV |
2731 | UNSPEC_IORV | |
2732 | UNSPEC_SMAXV | |
2733 | UNSPEC_SMINV | |
2734 | UNSPEC_UMAXV | |
2735 | UNSPEC_UMINV | |
2736 | UNSPEC_XORV]) | |
2737 | ||
2738 | (define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV | |
2739 | UNSPEC_FMAXV | |
2740 | UNSPEC_FMAXNMV | |
2741 | UNSPEC_FMINV | |
2742 | UNSPEC_FMINNMV]) | |
2743 | ||
d45b20a5 RS |
2744 | (define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS |
2745 | UNSPEC_COND_FNEG | |
624d0f07 | 2746 | UNSPEC_COND_FRECPX |
d45b20a5 RS |
2747 | UNSPEC_COND_FRINTA |
2748 | UNSPEC_COND_FRINTI | |
2749 | UNSPEC_COND_FRINTM | |
2750 | UNSPEC_COND_FRINTN | |
2751 | UNSPEC_COND_FRINTP | |
2752 | UNSPEC_COND_FRINTX | |
2753 | UNSPEC_COND_FRINTZ | |
2754 | UNSPEC_COND_FSQRT]) | |
2755 | ||
a0ee8352 RS |
2756 | ;; Same as SVE_COND_FP_UNARY, but without codes that have a dedicated |
2757 | ;; <optab><mode>2 expander. | |
2758 | (define_int_iterator SVE_COND_FP_UNARY_OPTAB [UNSPEC_COND_FABS | |
2759 | UNSPEC_COND_FNEG | |
2760 | UNSPEC_COND_FRECPX | |
2761 | UNSPEC_COND_FRINTA | |
2762 | UNSPEC_COND_FRINTI | |
2763 | UNSPEC_COND_FRINTM | |
2764 | UNSPEC_COND_FRINTN | |
2765 | UNSPEC_COND_FRINTP | |
2766 | UNSPEC_COND_FRINTX | |
2767 | UNSPEC_COND_FRINTZ]) | |
2768 | ||
95eb5537 | 2769 | (define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT]) |
99361551 RS |
2770 | (define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU]) |
2771 | (define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF]) | |
2772 | ||
cb18e86d RS |
2773 | (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD |
2774 | UNSPEC_COND_FDIV | |
624d0f07 | 2775 | UNSPEC_COND_FMAX |
cb18e86d | 2776 | UNSPEC_COND_FMAXNM |
624d0f07 | 2777 | UNSPEC_COND_FMIN |
cb18e86d RS |
2778 | UNSPEC_COND_FMINNM |
2779 | UNSPEC_COND_FMUL | |
624d0f07 | 2780 | UNSPEC_COND_FMULX |
cb18e86d | 2781 | UNSPEC_COND_FSUB]) |
0d2b3bca | 2782 | |
04f307cb RS |
2783 | ;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated |
2784 | ;; <optab><mode>3 expander. | |
2785 | (define_int_iterator SVE_COND_FP_BINARY_OPTAB [UNSPEC_COND_FADD | |
2786 | UNSPEC_COND_FMAX | |
2787 | UNSPEC_COND_FMAXNM | |
2788 | UNSPEC_COND_FMIN | |
2789 | UNSPEC_COND_FMINNM | |
2790 | UNSPEC_COND_FMUL | |
2791 | UNSPEC_COND_FMULX | |
2792 | UNSPEC_COND_FSUB]) | |
2793 | ||
624d0f07 RS |
2794 | (define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE]) |
2795 | ||
2796 | (define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD]) | |
2797 | (define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB]) | |
2798 | (define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL]) | |
2799 | ||
2800 | (define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX | |
2801 | UNSPEC_COND_FMAXNM | |
2802 | UNSPEC_COND_FMIN | |
a19ba9e1 RS |
2803 | UNSPEC_COND_FMINNM |
2804 | UNSPEC_COND_FMUL]) | |
2805 | ||
624d0f07 RS |
2806 | (define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV |
2807 | UNSPEC_COND_FMULX]) | |
2808 | ||
2809 | (define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90 | |
2810 | UNSPEC_COND_FCADD270]) | |
2811 | ||
2812 | (define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX | |
2813 | UNSPEC_COND_FMAXNM | |
2814 | UNSPEC_COND_FMIN | |
2815 | UNSPEC_COND_FMINNM]) | |
0254ed79 | 2816 | |
214c42fa RS |
2817 | ;; Floating-point max/min operations that correspond to optabs, |
2818 | ;; as opposed to those that are internal to the port. | |
2819 | (define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM | |
2820 | UNSPEC_COND_FMINNM]) | |
2821 | ||
b41d1f6e RS |
2822 | (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA |
2823 | UNSPEC_COND_FMLS | |
2824 | UNSPEC_COND_FNMLA | |
2825 | UNSPEC_COND_FNMLS]) | |
2826 | ||
624d0f07 RS |
2827 | (define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA |
2828 | UNSPEC_COND_FCMLA90 | |
2829 | UNSPEC_COND_FCMLA180 | |
2830 | UNSPEC_COND_FCMLA270]) | |
2831 | ||
2832 | (define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE | |
2833 | UNSPEC_COND_CMPGE_WIDE | |
2834 | UNSPEC_COND_CMPGT_WIDE | |
2835 | UNSPEC_COND_CMPHI_WIDE | |
2836 | UNSPEC_COND_CMPHS_WIDE | |
2837 | UNSPEC_COND_CMPLE_WIDE | |
2838 | UNSPEC_COND_CMPLO_WIDE | |
2839 | UNSPEC_COND_CMPLS_WIDE | |
2840 | UNSPEC_COND_CMPLT_WIDE | |
2841 | UNSPEC_COND_CMPNE_WIDE]) | |
2842 | ||
4a942af6 RS |
2843 | ;; SVE FP comparisons that accept #0.0. |
2844 | (define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ | |
2845 | UNSPEC_COND_FCMGE | |
2846 | UNSPEC_COND_FCMGT | |
2847 | UNSPEC_COND_FCMLE | |
2848 | UNSPEC_COND_FCMLT | |
2849 | UNSPEC_COND_FCMNE]) | |
43cacb12 | 2850 | |
42b4e87d RS |
2851 | (define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE |
2852 | UNSPEC_COND_FCMGT | |
2853 | UNSPEC_COND_FCMLE | |
2854 | UNSPEC_COND_FCMLT]) | |
2855 | ||
624d0f07 RS |
2856 | (define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS]) |
2857 | ||
2858 | (define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90 | |
2859 | UNSPEC_FCMLA180 UNSPEC_FCMLA270]) | |
2860 | ||
6ad9571b | 2861 | (define_int_iterator SVE_WHILE [UNSPEC_WHILELE UNSPEC_WHILELO |
bad5e58a | 2862 | UNSPEC_WHILELS UNSPEC_WHILELT |
0a09a948 RS |
2863 | (UNSPEC_WHILEGE "TARGET_SVE2") |
2864 | (UNSPEC_WHILEGT "TARGET_SVE2") | |
2865 | (UNSPEC_WHILEHI "TARGET_SVE2") | |
2866 | (UNSPEC_WHILEHS "TARGET_SVE2") | |
bad5e58a RS |
2867 | (UNSPEC_WHILERW "TARGET_SVE2") |
2868 | (UNSPEC_WHILEWR "TARGET_SVE2")]) | |
624d0f07 | 2869 | |
58c036c8 RS |
2870 | (define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR]) |
2871 | ||
624d0f07 RS |
2872 | (define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE |
2873 | UNSPEC_ASHIFTRT_WIDE | |
2874 | UNSPEC_LSHIFTRT_WIDE]) | |
2875 | ||
2876 | (define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1]) | |
2877 | ||
7bb4b7a5 ASDV |
2878 | (define_int_iterator SVE_PRED_LOAD [UNSPEC_PRED_X UNSPEC_LD1_SVE]) |
2879 | ||
2880 | (define_int_attr pred_load [(UNSPEC_PRED_X "_x") (UNSPEC_LD1_SVE "")]) | |
2881 | ||
0a09a948 RS |
2882 | (define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE]) |
2883 | ||
2884 | (define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB | |
2885 | UNSPEC_SQXTUNB | |
2886 | UNSPEC_UQXTNB]) | |
2887 | ||
2888 | (define_int_iterator SVE2_INT_UNARY_NARROWT [UNSPEC_SQXTNT | |
2889 | UNSPEC_SQXTUNT | |
2890 | UNSPEC_UQXTNT]) | |
2891 | ||
2892 | (define_int_iterator SVE2_INT_BINARY [UNSPEC_SQDMULH | |
2893 | UNSPEC_SQRDMULH]) | |
2894 | ||
2895 | (define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH | |
2896 | UNSPEC_SQRDMULH]) | |
2897 | ||
2898 | (define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB | |
2899 | UNSPEC_SABDLT | |
2900 | UNSPEC_SADDLB | |
2901 | UNSPEC_SADDLBT | |
2902 | UNSPEC_SADDLT | |
2903 | UNSPEC_SMULLB | |
2904 | UNSPEC_SMULLT | |
2905 | UNSPEC_SQDMULLB | |
2906 | UNSPEC_SQDMULLT | |
2907 | UNSPEC_SSUBLB | |
2908 | UNSPEC_SSUBLBT | |
2909 | UNSPEC_SSUBLT | |
2910 | UNSPEC_SSUBLTB | |
2911 | UNSPEC_UABDLB | |
2912 | UNSPEC_UABDLT | |
2913 | UNSPEC_UADDLB | |
2914 | UNSPEC_UADDLT | |
2915 | UNSPEC_UMULLB | |
2916 | UNSPEC_UMULLT | |
2917 | UNSPEC_USUBLB | |
2918 | UNSPEC_USUBLT]) | |
2919 | ||
2920 | (define_int_iterator SVE2_INT_BINARY_LONG_LANE [UNSPEC_SMULLB | |
2921 | UNSPEC_SMULLT | |
2922 | UNSPEC_SQDMULLB | |
2923 | UNSPEC_SQDMULLT | |
2924 | UNSPEC_UMULLB | |
2925 | UNSPEC_UMULLT]) | |
2926 | ||
2927 | (define_int_iterator SVE2_INT_BINARY_NARROWB [UNSPEC_ADDHNB | |
2928 | UNSPEC_RADDHNB | |
2929 | UNSPEC_RSUBHNB | |
2930 | UNSPEC_SUBHNB]) | |
2931 | ||
2932 | (define_int_iterator SVE2_INT_BINARY_NARROWT [UNSPEC_ADDHNT | |
2933 | UNSPEC_RADDHNT | |
2934 | UNSPEC_RSUBHNT | |
2935 | UNSPEC_SUBHNT]) | |
2936 | ||
2937 | (define_int_iterator SVE2_INT_BINARY_PAIR [UNSPEC_ADDP | |
2938 | UNSPEC_SMAXP | |
2939 | UNSPEC_SMINP | |
2940 | UNSPEC_UMAXP | |
2941 | UNSPEC_UMINP]) | |
2942 | ||
2943 | (define_int_iterator SVE2_FP_BINARY_PAIR [UNSPEC_FADDP | |
2944 | UNSPEC_FMAXP | |
2945 | UNSPEC_FMAXNMP | |
2946 | UNSPEC_FMINP | |
2947 | UNSPEC_FMINNMP]) | |
2948 | ||
2949 | (define_int_iterator SVE2_INT_BINARY_PAIR_LONG [UNSPEC_SADALP UNSPEC_UADALP]) | |
2950 | ||
2951 | (define_int_iterator SVE2_INT_BINARY_WIDE [UNSPEC_SADDWB | |
2952 | UNSPEC_SADDWT | |
2953 | UNSPEC_SSUBWB | |
2954 | UNSPEC_SSUBWT | |
2955 | UNSPEC_UADDWB | |
2956 | UNSPEC_UADDWT | |
2957 | UNSPEC_USUBWB | |
2958 | UNSPEC_USUBWT]) | |
2959 | ||
2960 | (define_int_iterator SVE2_INT_SHIFT_IMM_LONG [UNSPEC_SSHLLB | |
2961 | UNSPEC_SSHLLT | |
2962 | UNSPEC_USHLLB | |
2963 | UNSPEC_USHLLT]) | |
2964 | ||
2965 | (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWB [UNSPEC_RSHRNB | |
2966 | UNSPEC_SHRNB | |
2967 | UNSPEC_SQRSHRNB | |
2968 | UNSPEC_SQRSHRUNB | |
2969 | UNSPEC_SQSHRNB | |
2970 | UNSPEC_SQSHRUNB | |
2971 | UNSPEC_UQRSHRNB | |
2972 | UNSPEC_UQSHRNB]) | |
2973 | ||
2974 | (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWT [UNSPEC_RSHRNT | |
2975 | UNSPEC_SHRNT | |
2976 | UNSPEC_SQRSHRNT | |
2977 | UNSPEC_SQRSHRUNT | |
2978 | UNSPEC_SQSHRNT | |
2979 | UNSPEC_SQSHRUNT | |
2980 | UNSPEC_UQRSHRNT | |
2981 | UNSPEC_UQSHRNT]) | |
2982 | ||
2983 | (define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI]) | |
2984 | ||
2985 | (define_int_iterator SVE2_INT_CADD [UNSPEC_CADD90 | |
2986 | UNSPEC_CADD270 | |
2987 | UNSPEC_SQCADD90 | |
2988 | UNSPEC_SQCADD270]) | |
2989 | ||
2990 | (define_int_iterator SVE2_INT_BITPERM [UNSPEC_BDEP UNSPEC_BEXT UNSPEC_BGRP]) | |
2991 | ||
2992 | (define_int_iterator SVE2_INT_TERNARY [UNSPEC_ADCLB | |
2993 | UNSPEC_ADCLT | |
2994 | UNSPEC_EORBT | |
2995 | UNSPEC_EORTB | |
2996 | UNSPEC_SBCLB | |
2997 | UNSPEC_SBCLT | |
2998 | UNSPEC_SQRDMLAH | |
2999 | UNSPEC_SQRDMLSH]) | |
3000 | ||
3001 | (define_int_iterator SVE2_INT_TERNARY_LANE [UNSPEC_SQRDMLAH | |
3002 | UNSPEC_SQRDMLSH]) | |
3003 | ||
3004 | (define_int_iterator SVE2_FP_TERNARY_LONG [UNSPEC_FMLALB | |
3005 | UNSPEC_FMLALT | |
3006 | UNSPEC_FMLSLB | |
3007 | UNSPEC_FMLSLT]) | |
3008 | ||
3009 | (define_int_iterator SVE2_FP_TERNARY_LONG_LANE [UNSPEC_FMLALB | |
3010 | UNSPEC_FMLALT | |
3011 | UNSPEC_FMLSLB | |
3012 | UNSPEC_FMLSLT]) | |
3013 | ||
3014 | (define_int_iterator SVE2_INT_CMLA [UNSPEC_CMLA | |
3015 | UNSPEC_CMLA90 | |
3016 | UNSPEC_CMLA180 | |
3017 | UNSPEC_CMLA270 | |
3018 | UNSPEC_SQRDCMLAH | |
3019 | UNSPEC_SQRDCMLAH90 | |
3020 | UNSPEC_SQRDCMLAH180 | |
3021 | UNSPEC_SQRDCMLAH270]) | |
3022 | ||
ad260343 TC |
3023 | ;; Unlike the normal CMLA instructions these represent the actual operation |
3024 | ;; to be performed. They will always need to be expanded into multiple | |
3025 | ;; sequences consisting of CMLA. | |
3026 | (define_int_iterator SVE2_INT_CMLA_OP [UNSPEC_CMLA | |
3027 | UNSPEC_CMLA_CONJ | |
3028 | UNSPEC_CMLA180 | |
3029 | UNSPEC_CMLA180_CONJ]) | |
3030 | ||
3031 | ;; Unlike the normal CMLA instructions these represent the actual operation | |
3032 | ;; to be performed. They will always need to be expanded into multiple | |
3033 | ;; sequences consisting of CMLA. | |
3034 | (define_int_iterator SVE2_INT_CMUL_OP [UNSPEC_CMUL | |
3035 | UNSPEC_CMUL_CONJ]) | |
3036 | ||
84747acf TC |
3037 | ;; Same as SVE2_INT_CADD but exclude the saturating instructions |
3038 | (define_int_iterator SVE2_INT_CADD_OP [UNSPEC_CADD90 | |
3039 | UNSPEC_CADD270]) | |
3040 | ||
0a09a948 RS |
3041 | (define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT |
3042 | UNSPEC_CDOT90 | |
3043 | UNSPEC_CDOT180 | |
3044 | UNSPEC_CDOT270]) | |
3045 | ||
3046 | (define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB | |
3047 | UNSPEC_SABDLT | |
3048 | UNSPEC_SMULLB | |
3049 | UNSPEC_SMULLT | |
3050 | UNSPEC_UABDLB | |
3051 | UNSPEC_UABDLT | |
3052 | UNSPEC_UMULLB | |
3053 | UNSPEC_UMULLT]) | |
3054 | ||
3055 | (define_int_iterator SVE2_INT_QADD_BINARY_LONG [UNSPEC_SQDMULLB | |
3056 | UNSPEC_SQDMULLBT | |
3057 | UNSPEC_SQDMULLT]) | |
3058 | ||
3059 | (define_int_iterator SVE2_INT_SUB_BINARY_LONG [UNSPEC_SMULLB | |
3060 | UNSPEC_SMULLT | |
3061 | UNSPEC_UMULLB | |
3062 | UNSPEC_UMULLT]) | |
3063 | ||
3064 | (define_int_iterator SVE2_INT_QSUB_BINARY_LONG [UNSPEC_SQDMULLB | |
3065 | UNSPEC_SQDMULLBT | |
3066 | UNSPEC_SQDMULLT]) | |
3067 | ||
3068 | (define_int_iterator SVE2_INT_ADD_BINARY_LONG_LANE [UNSPEC_SMULLB | |
3069 | UNSPEC_SMULLT | |
3070 | UNSPEC_UMULLB | |
3071 | UNSPEC_UMULLT]) | |
3072 | ||
3073 | (define_int_iterator SVE2_INT_QADD_BINARY_LONG_LANE [UNSPEC_SQDMULLB | |
3074 | UNSPEC_SQDMULLT]) | |
3075 | ||
3076 | (define_int_iterator SVE2_INT_SUB_BINARY_LONG_LANE [UNSPEC_SMULLB | |
3077 | UNSPEC_SMULLT | |
3078 | UNSPEC_UMULLB | |
3079 | UNSPEC_UMULLT]) | |
3080 | ||
3081 | (define_int_iterator SVE2_INT_QSUB_BINARY_LONG_LANE [UNSPEC_SQDMULLB | |
3082 | UNSPEC_SQDMULLT]) | |
3083 | ||
3084 | (define_int_iterator SVE2_COND_INT_UNARY_FP [UNSPEC_COND_FLOGB]) | |
3085 | ||
3086 | (define_int_iterator SVE2_COND_FP_UNARY_LONG [UNSPEC_COND_FCVTLT]) | |
3087 | ||
3088 | (define_int_iterator SVE2_COND_FP_UNARY_NARROWB [UNSPEC_COND_FCVTX]) | |
3089 | ||
3090 | (define_int_iterator SVE2_COND_INT_BINARY [UNSPEC_SHADD | |
3091 | UNSPEC_SHSUB | |
3092 | UNSPEC_SQRSHL | |
3093 | UNSPEC_SRHADD | |
3094 | UNSPEC_SRSHL | |
3095 | UNSPEC_SUQADD | |
3096 | UNSPEC_UHADD | |
3097 | UNSPEC_UHSUB | |
3098 | UNSPEC_UQRSHL | |
3099 | UNSPEC_URHADD | |
3100 | UNSPEC_URSHL | |
3101 | UNSPEC_USQADD]) | |
3102 | ||
3103 | (define_int_iterator SVE2_COND_INT_BINARY_NOREV [UNSPEC_SUQADD | |
3104 | UNSPEC_USQADD]) | |
3105 | ||
3106 | (define_int_iterator SVE2_COND_INT_BINARY_REV [UNSPEC_SHADD | |
3107 | UNSPEC_SHSUB | |
3108 | UNSPEC_SQRSHL | |
3109 | UNSPEC_SRHADD | |
3110 | UNSPEC_SRSHL | |
3111 | UNSPEC_UHADD | |
3112 | UNSPEC_UHSUB | |
3113 | UNSPEC_UQRSHL | |
3114 | UNSPEC_URHADD | |
3115 | UNSPEC_URSHL]) | |
3116 | ||
3117 | (define_int_iterator SVE2_COND_INT_SHIFT [UNSPEC_SQSHL | |
3118 | UNSPEC_UQSHL]) | |
3119 | ||
3120 | (define_int_iterator SVE2_MATCH [UNSPEC_MATCH UNSPEC_NMATCH]) | |
3121 | ||
3122 | (define_int_iterator SVE2_PMULL [UNSPEC_PMULLB UNSPEC_PMULLT]) | |
3123 | ||
3124 | (define_int_iterator SVE2_PMULL_PAIR [UNSPEC_PMULLB_PAIR UNSPEC_PMULLT_PAIR]) | |
3125 | ||
9d63f43b TC |
3126 | (define_int_iterator FCADD [UNSPEC_FCADD90 |
3127 | UNSPEC_FCADD270]) | |
3128 | ||
3129 | (define_int_iterator FCMLA [UNSPEC_FCMLA | |
3130 | UNSPEC_FCMLA90 | |
3131 | UNSPEC_FCMLA180 | |
3132 | UNSPEC_FCMLA270]) | |
3133 | ||
10bd1d96 KT |
3134 | (define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X |
3135 | UNSPEC_FRINT64Z UNSPEC_FRINT64X]) | |
3136 | ||
624d0f07 RS |
3137 | (define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB]) |
3138 | ||
6bec6664 RS |
3139 | (define_int_iterator SVE_BRKP [UNSPEC_BRKPA UNSPEC_BRKPB]) |
3140 | ||
624d0f07 RS |
3141 | (define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB]) |
3142 | ||
3143 | (define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT]) | |
3144 | ||
36696774 RS |
3145 | (define_int_iterator MATMUL [UNSPEC_SMATMUL UNSPEC_UMATMUL |
3146 | UNSPEC_USMATMUL]) | |
3147 | ||
3148 | (define_int_iterator FMMLA [UNSPEC_FMMLA]) | |
3149 | ||
f78335df DB |
3150 | (define_int_iterator BF_MLA [UNSPEC_BFMLALB |
3151 | UNSPEC_BFMLALT]) | |
3152 | ||
ad260343 TC |
3153 | (define_int_iterator FCMLA_OP [UNSPEC_FCMLA |
3154 | UNSPEC_FCMLA180 | |
3155 | UNSPEC_FCMLA_CONJ | |
3156 | UNSPEC_FCMLA180_CONJ]) | |
3157 | ||
3158 | (define_int_iterator FCMUL_OP [UNSPEC_FCMUL | |
3159 | UNSPEC_FCMUL_CONJ]) | |
3160 | ||
d81cb613 MW |
3161 | ;; Iterators for atomic operations. |
3162 | ||
3163 | (define_int_iterator ATOMIC_LDOP | |
3164 | [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC | |
3165 | UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) | |
3166 | ||
3167 | (define_int_attr atomic_ldop | |
3168 | [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") | |
3169 | (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) | |
3170 | ||
7803ec5e RH |
3171 | (define_int_attr atomic_ldoptab |
3172 | [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic") | |
3173 | (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) | |
3174 | ||
b096a6eb RS |
3175 | (define_int_iterator SUBDI_BITS [8 16 32]) |
3176 | ||
43e9d192 IB |
3177 | ;; ------------------------------------------------------------------- |
3178 | ;; Int Iterators Attributes. | |
3179 | ;; ------------------------------------------------------------------- | |
43cacb12 RS |
3180 | |
3181 | ;; The optab associated with an operation. Note that for ANDF, IORF | |
3182 | ;; and XORF, the optab pattern is not actually defined; we just use this | |
3183 | ;; name for consistency with the integer patterns. | |
3184 | (define_int_attr optab [(UNSPEC_ANDF "and") | |
3185 | (UNSPEC_IORF "ior") | |
898f07b0 | 3186 | (UNSPEC_XORF "xor") |
624d0f07 RS |
3187 | (UNSPEC_SADDV "sadd") |
3188 | (UNSPEC_UADDV "uadd") | |
898f07b0 RS |
3189 | (UNSPEC_ANDV "and") |
3190 | (UNSPEC_IORV "ior") | |
0972596e | 3191 | (UNSPEC_XORV "xor") |
624d0f07 RS |
3192 | (UNSPEC_FRECPE "frecpe") |
3193 | (UNSPEC_FRECPS "frecps") | |
3194 | (UNSPEC_RSQRTE "frsqrte") | |
3195 | (UNSPEC_RSQRTS "frsqrts") | |
3196 | (UNSPEC_RBIT "rbit") | |
d7a09c44 RS |
3197 | (UNSPEC_REVB "revb") |
3198 | (UNSPEC_REVH "revh") | |
3199 | (UNSPEC_REVW "revw") | |
b0760a40 RS |
3200 | (UNSPEC_UMAXV "umax") |
3201 | (UNSPEC_UMINV "umin") | |
3202 | (UNSPEC_SMAXV "smax") | |
3203 | (UNSPEC_SMINV "smin") | |
0a09a948 RS |
3204 | (UNSPEC_CADD90 "cadd90") |
3205 | (UNSPEC_CADD270 "cadd270") | |
3206 | (UNSPEC_CDOT "cdot") | |
3207 | (UNSPEC_CDOT90 "cdot90") | |
3208 | (UNSPEC_CDOT180 "cdot180") | |
3209 | (UNSPEC_CDOT270 "cdot270") | |
3210 | (UNSPEC_CMLA "cmla") | |
3211 | (UNSPEC_CMLA90 "cmla90") | |
3212 | (UNSPEC_CMLA180 "cmla180") | |
3213 | (UNSPEC_CMLA270 "cmla270") | |
b0760a40 RS |
3214 | (UNSPEC_FADDV "plus") |
3215 | (UNSPEC_FMAXNMV "smax") | |
3216 | (UNSPEC_FMAXV "smax_nan") | |
3217 | (UNSPEC_FMINNMV "smin") | |
3218 | (UNSPEC_FMINV "smin_nan") | |
624d0f07 RS |
3219 | (UNSPEC_SMUL_HIGHPART "smulh") |
3220 | (UNSPEC_UMUL_HIGHPART "umulh") | |
3221 | (UNSPEC_FMLA "fma") | |
3222 | (UNSPEC_FMLS "fnma") | |
3223 | (UNSPEC_FCMLA "fcmla") | |
3224 | (UNSPEC_FCMLA90 "fcmla90") | |
3225 | (UNSPEC_FCMLA180 "fcmla180") | |
3226 | (UNSPEC_FCMLA270 "fcmla270") | |
3227 | (UNSPEC_FEXPA "fexpa") | |
3228 | (UNSPEC_FTSMUL "ftsmul") | |
3229 | (UNSPEC_FTSSEL "ftssel") | |
0a09a948 RS |
3230 | (UNSPEC_PMULLB "pmullb") |
3231 | (UNSPEC_PMULLB_PAIR "pmullb_pair") | |
3232 | (UNSPEC_PMULLT "pmullt") | |
3233 | (UNSPEC_PMULLT_PAIR "pmullt_pair") | |
36696774 | 3234 | (UNSPEC_SMATMUL "smatmul") |
0a09a948 RS |
3235 | (UNSPEC_SQCADD90 "sqcadd90") |
3236 | (UNSPEC_SQCADD270 "sqcadd270") | |
3237 | (UNSPEC_SQRDCMLAH "sqrdcmlah") | |
3238 | (UNSPEC_SQRDCMLAH90 "sqrdcmlah90") | |
3239 | (UNSPEC_SQRDCMLAH180 "sqrdcmlah180") | |
3240 | (UNSPEC_SQRDCMLAH270 "sqrdcmlah270") | |
36696774 RS |
3241 | (UNSPEC_TRN1Q "trn1q") |
3242 | (UNSPEC_TRN2Q "trn2q") | |
3243 | (UNSPEC_UMATMUL "umatmul") | |
3244 | (UNSPEC_USMATMUL "usmatmul") | |
3245 | (UNSPEC_UZP1Q "uzp1q") | |
3246 | (UNSPEC_UZP2Q "uzp2q") | |
58c036c8 RS |
3247 | (UNSPEC_WHILERW "vec_check_raw_alias") |
3248 | (UNSPEC_WHILEWR "vec_check_war_alias") | |
36696774 RS |
3249 | (UNSPEC_ZIP1Q "zip1q") |
3250 | (UNSPEC_ZIP2Q "zip2q") | |
d45b20a5 | 3251 | (UNSPEC_COND_FABS "abs") |
cb18e86d | 3252 | (UNSPEC_COND_FADD "add") |
624d0f07 RS |
3253 | (UNSPEC_COND_FCADD90 "cadd90") |
3254 | (UNSPEC_COND_FCADD270 "cadd270") | |
3255 | (UNSPEC_COND_FCMLA "fcmla") | |
3256 | (UNSPEC_COND_FCMLA90 "fcmla90") | |
3257 | (UNSPEC_COND_FCMLA180 "fcmla180") | |
3258 | (UNSPEC_COND_FCMLA270 "fcmla270") | |
99361551 RS |
3259 | (UNSPEC_COND_FCVT "fcvt") |
3260 | (UNSPEC_COND_FCVTZS "fix_trunc") | |
3261 | (UNSPEC_COND_FCVTZU "fixuns_trunc") | |
cb18e86d | 3262 | (UNSPEC_COND_FDIV "div") |
6d331688 | 3263 | (UNSPEC_COND_FMAX "fmax_nan") |
cb18e86d | 3264 | (UNSPEC_COND_FMAXNM "smax") |
6d331688 | 3265 | (UNSPEC_COND_FMIN "fmin_nan") |
cb18e86d | 3266 | (UNSPEC_COND_FMINNM "smin") |
b41d1f6e RS |
3267 | (UNSPEC_COND_FMLA "fma") |
3268 | (UNSPEC_COND_FMLS "fnma") | |
cb18e86d | 3269 | (UNSPEC_COND_FMUL "mul") |
624d0f07 | 3270 | (UNSPEC_COND_FMULX "mulx") |
d45b20a5 | 3271 | (UNSPEC_COND_FNEG "neg") |
b41d1f6e | 3272 | (UNSPEC_COND_FNMLA "fnms") |
cb18e86d | 3273 | (UNSPEC_COND_FNMLS "fms") |
624d0f07 | 3274 | (UNSPEC_COND_FRECPX "frecpx") |
d45b20a5 RS |
3275 | (UNSPEC_COND_FRINTA "round") |
3276 | (UNSPEC_COND_FRINTI "nearbyint") | |
3277 | (UNSPEC_COND_FRINTM "floor") | |
3278 | (UNSPEC_COND_FRINTN "frintn") | |
3279 | (UNSPEC_COND_FRINTP "ceil") | |
3280 | (UNSPEC_COND_FRINTX "rint") | |
3281 | (UNSPEC_COND_FRINTZ "btrunc") | |
624d0f07 | 3282 | (UNSPEC_COND_FSCALE "fscale") |
d45b20a5 | 3283 | (UNSPEC_COND_FSQRT "sqrt") |
99361551 RS |
3284 | (UNSPEC_COND_FSUB "sub") |
3285 | (UNSPEC_COND_SCVTF "float") | |
3286 | (UNSPEC_COND_UCVTF "floatuns")]) | |
43cacb12 | 3287 | |
6d331688 RS |
3288 | (define_int_attr fmaxmin [(UNSPEC_FMAX "fmax_nan") |
3289 | (UNSPEC_FMAXNM "fmax") | |
e32b9eb3 | 3290 | (UNSPEC_FMAXNMV "fmax") |
6d331688 RS |
3291 | (UNSPEC_FMIN "fmin_nan") |
3292 | (UNSPEC_FMINNM "fmin") | |
e32b9eb3 | 3293 | (UNSPEC_FMINNMV "fmin") |
6d331688 RS |
3294 | (UNSPEC_COND_FMAXNM "fmax") |
3295 | (UNSPEC_COND_FMINNM "fmin")]) | |
998eaf97 JG |
3296 | |
3297 | (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") | |
3298 | (UNSPEC_UMINV "umin") | |
3299 | (UNSPEC_SMAXV "smax") | |
3300 | (UNSPEC_SMINV "smin") | |
3301 | (UNSPEC_FMAX "fmax") | |
3302 | (UNSPEC_FMAXNMV "fmaxnm") | |
3303 | (UNSPEC_FMAXV "fmax") | |
3304 | (UNSPEC_FMIN "fmin") | |
3305 | (UNSPEC_FMINNMV "fminnm") | |
1efafef3 TC |
3306 | (UNSPEC_FMINV "fmin") |
3307 | (UNSPEC_FMAXNM "fmaxnm") | |
3308 | (UNSPEC_FMINNM "fminnm")]) | |
202d0c11 | 3309 | |
624d0f07 RS |
3310 | (define_code_attr binqops_op [(ss_plus "sqadd") |
3311 | (us_plus "uqadd") | |
3312 | (ss_minus "sqsub") | |
3313 | (us_minus "uqsub")]) | |
3314 | ||
3315 | (define_code_attr binqops_op_rev [(ss_plus "sqsub") | |
3316 | (ss_minus "sqadd")]) | |
3317 | ||
43cacb12 RS |
3318 | ;; The SVE logical instruction that implements an unspec. |
3319 | (define_int_attr logicalf_op [(UNSPEC_ANDF "and") | |
3320 | (UNSPEC_IORF "orr") | |
3321 | (UNSPEC_XORF "eor")]) | |
3322 | ||
624d0f07 RS |
3323 | (define_int_attr last_op [(UNSPEC_CLASTA "after_last") |
3324 | (UNSPEC_CLASTB "last") | |
3325 | (UNSPEC_LASTA "after_last") | |
3326 | (UNSPEC_LASTB "last")]) | |
3327 | ||
43cacb12 | 3328 | ;; "s" for signed operations and "u" for unsigned ones. |
624d0f07 RS |
3329 | (define_int_attr su [(UNSPEC_SADDV "s") |
3330 | (UNSPEC_UADDV "u") | |
3331 | (UNSPEC_UNPACKSHI "s") | |
43cacb12 RS |
3332 | (UNSPEC_UNPACKUHI "u") |
3333 | (UNSPEC_UNPACKSLO "s") | |
11e9443f RS |
3334 | (UNSPEC_UNPACKULO "u") |
3335 | (UNSPEC_SMUL_HIGHPART "s") | |
99361551 RS |
3336 | (UNSPEC_UMUL_HIGHPART "u") |
3337 | (UNSPEC_COND_FCVTZS "s") | |
3338 | (UNSPEC_COND_FCVTZU "u") | |
3339 | (UNSPEC_COND_SCVTF "s") | |
58cc9876 | 3340 | (UNSPEC_COND_UCVTF "u") |
58cc9876 YW |
3341 | (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u") |
3342 | (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")]) | |
43cacb12 | 3343 | |
43e9d192 IB |
3344 | (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") |
3345 | (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") | |
3346 | (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") | |
75add2d0 | 3347 | (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") |
43e9d192 IB |
3348 | (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") |
3349 | (UNSPEC_SSLI "s") (UNSPEC_USLI "u") | |
3350 | (UNSPEC_SSRI "s") (UNSPEC_USRI "u") | |
3351 | (UNSPEC_USRA "u") (UNSPEC_SSRA "s") | |
43e9d192 IB |
3352 | (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") |
3353 | (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") | |
3354 | (UNSPEC_UQSHL "u") | |
43e9d192 IB |
3355 | (UNSPEC_USHL "u") (UNSPEC_SSHL "s") |
3356 | (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") | |
3357 | (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") | |
3358 | (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") | |
7a08d813 | 3359 | (UNSPEC_SDOT "s") (UNSPEC_UDOT "u") |
8c197c85 | 3360 | (UNSPEC_USDOT "us") (UNSPEC_SUDOT "su") |
36696774 RS |
3361 | (UNSPEC_SMATMUL "s") (UNSPEC_UMATMUL "u") |
3362 | (UNSPEC_USMATMUL "us") | |
43e9d192 IB |
3363 | ]) |
3364 | ||
3365 | (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") | |
43e9d192 IB |
3366 | (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") |
3367 | (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") | |
58cc9876 YW |
3368 | (UNSPEC_SMULHS "") (UNSPEC_UMULHS "") |
3369 | (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r") | |
43e9d192 IB |
3370 | ]) |
3371 | ||
3372 | (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") | |
0a09a948 RS |
3373 | (UNSPEC_SSRI "r") (UNSPEC_USRI "r") |
3374 | (UNSPEC_SQSHL "l") (UNSPEC_UQSHL "l") | |
3375 | (UNSPEC_SQSHLU "l") | |
3376 | (UNSPEC_SRSHR "r") (UNSPEC_URSHR "r") | |
3377 | (UNSPEC_ASRD "r") | |
3378 | (UNSPEC_SLI "l") (UNSPEC_SRI "r")]) | |
43e9d192 IB |
3379 | |
3380 | (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
42addb5a RS |
3381 | (UNSPEC_SHADD "") (UNSPEC_UHADD "u") |
3382 | (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")]) | |
43e9d192 | 3383 | |
624d0f07 RS |
3384 | (define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")]) |
3385 | ||
3386 | (define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b") | |
3387 | (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")]) | |
3388 | ||
f78335df DB |
3389 | (define_int_attr bt [(UNSPEC_BFMLALB "b") (UNSPEC_BFMLALT "t")]) |
3390 | ||
43e9d192 IB |
3391 | (define_int_attr addsub [(UNSPEC_SHADD "add") |
3392 | (UNSPEC_UHADD "add") | |
3393 | (UNSPEC_SRHADD "add") | |
3394 | (UNSPEC_URHADD "add") | |
3395 | (UNSPEC_SHSUB "sub") | |
46579775 | 3396 | (UNSPEC_UHSUB "sub")]) |
43e9d192 | 3397 | |
2d57b12e YW |
3398 | ;; BSL variants: first commutative operand. |
3399 | (define_int_attr bsl_1st [(1 "w") (2 "0")]) | |
3400 | ||
3401 | ;; BSL variants: second commutative operand. | |
3402 | (define_int_attr bsl_2nd [(1 "0") (2 "w")]) | |
3403 | ||
3404 | ;; BSL variants: duplicated input operand. | |
3405 | (define_int_attr bsl_dup [(1 "1") (2 "2")]) | |
3406 | ||
3407 | ;; BSL variants: operand which requires preserving via movprfx. | |
3408 | (define_int_attr bsl_mov [(1 "2") (2 "1")]) | |
3409 | ||
cb23a30c JG |
3410 | (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") |
3411 | (UNSPEC_SSRI "offset_") | |
3412 | (UNSPEC_USRI "offset_")]) | |
43e9d192 | 3413 | |
42fc9a7f JG |
3414 | ;; Standard pattern names for floating-point rounding instructions. |
3415 | (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") | |
3416 | (UNSPEC_FRINTP "ceil") | |
3417 | (UNSPEC_FRINTM "floor") | |
3418 | (UNSPEC_FRINTI "nearbyint") | |
3419 | (UNSPEC_FRINTX "rint") | |
0659ce6f | 3420 | (UNSPEC_FRINTA "round") |
16ce822e | 3421 | (UNSPEC_FRINTN "roundeven")]) |
42fc9a7f JG |
3422 | |
3423 | ;; frint suffix for floating-point rounding instructions. | |
3424 | (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") | |
3425 | (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") | |
0659ce6f JG |
3426 | (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") |
3427 | (UNSPEC_FRINTN "n")]) | |
42fc9a7f JG |
3428 | |
3429 | (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") | |
ce966824 JG |
3430 | (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") |
3431 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f | 3432 | |
3f598afe JW |
3433 | (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") |
3434 | (UNSPEC_UCVTF "ucvtf") | |
3435 | (UNSPEC_FCVTZS "fcvtzs") | |
3436 | (UNSPEC_FCVTZU "fcvtzu")]) | |
3437 | ||
db58fd89 | 3438 | ;; Pointer authentication mnemonic prefix. |
8fc16d72 ST |
3439 | (define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia") |
3440 | (UNSPEC_PACIBSP "pacib") | |
3441 | (UNSPEC_PACIA1716 "pacia") | |
3442 | (UNSPEC_PACIB1716 "pacib") | |
3443 | (UNSPEC_AUTIASP "autia") | |
3444 | (UNSPEC_AUTIBSP "autib") | |
3445 | (UNSPEC_AUTIA1716 "autia") | |
3446 | (UNSPEC_AUTIB1716 "autib")]) | |
3447 | ||
3448 | (define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A") | |
3449 | (UNSPEC_PACIBSP "AARCH64_KEY_B") | |
3450 | (UNSPEC_PACIA1716 "AARCH64_KEY_A") | |
3451 | (UNSPEC_PACIB1716 "AARCH64_KEY_B") | |
3452 | (UNSPEC_AUTIASP "AARCH64_KEY_A") | |
3453 | (UNSPEC_AUTIBSP "AARCH64_KEY_B") | |
3454 | (UNSPEC_AUTIA1716 "AARCH64_KEY_A") | |
3455 | (UNSPEC_AUTIB1716 "AARCH64_KEY_B")]) | |
3456 | ||
3457 | ;; Pointer authentication HINT number for NOP space instructions using A and | |
3458 | ;; B key. | |
3459 | (define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25") | |
3460 | (UNSPEC_PACIBSP "27") | |
3461 | (UNSPEC_AUTIASP "29") | |
3462 | (UNSPEC_AUTIBSP "31") | |
3463 | (UNSPEC_PACIA1716 "8") | |
3464 | (UNSPEC_PACIB1716 "10") | |
3465 | (UNSPEC_AUTIA1716 "12") | |
3466 | (UNSPEC_AUTIB1716 "14")]) | |
db58fd89 | 3467 | |
3e2751ce | 3468 | (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2") |
36696774 | 3469 | (UNSPEC_ZIP1Q "zip1") (UNSPEC_ZIP2Q "zip2") |
3e2751ce | 3470 | (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2") |
36696774 RS |
3471 | (UNSPEC_TRN1Q "trn1") (UNSPEC_TRN2Q "trn2") |
3472 | (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2") | |
3473 | (UNSPEC_UZP1Q "uzp1") (UNSPEC_UZP2Q "uzp2")]) | |
cc4d934f | 3474 | |
923fcec3 AL |
3475 | ; op code for REV instructions (size within which elements are reversed). |
3476 | (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") | |
3477 | (UNSPEC_REV16 "16")]) | |
3478 | ||
3e2751ce | 3479 | (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") |
c2ef4708 | 3480 | (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) |
0050faf8 | 3481 | |
9bfb28ed RS |
3482 | ;; Return true if the associated optab refers to the high-numbered lanes, |
3483 | ;; false if it refers to the low-numbered lanes. The convention is for | |
3484 | ;; "hi" to refer to the low-numbered lanes (the first ones in memory) | |
3485 | ;; for big-endian. | |
3486 | (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN") | |
3487 | (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN") | |
3488 | (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") | |
3489 | (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) | |
3490 | ||
5d357f26 KT |
3491 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") |
3492 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") | |
3493 | (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") | |
3494 | (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) | |
3495 | ||
3496 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
3497 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") | |
3498 | (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") | |
3499 | (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) | |
3500 | ||
5a7a4e80 TB |
3501 | (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) |
3502 | (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) | |
30442682 TB |
3503 | |
3504 | (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") | |
3505 | (UNSPEC_SHA1M "m")]) | |
b9cb0a44 TB |
3506 | |
3507 | (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) | |
57b26d65 MW |
3508 | |
3509 | (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) | |
27086ea3 MC |
3510 | |
3511 | (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")]) | |
3512 | ||
3513 | (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b") | |
3514 | (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")]) | |
3515 | ||
3516 | (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")]) | |
3517 | ||
3518 | (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s") | |
3519 | (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")]) | |
43cacb12 | 3520 | |
10bd1d96 KT |
3521 | (define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x") |
3522 | (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")]) | |
3523 | ||
43cacb12 | 3524 | ;; The condition associated with an UNSPEC_COND_<xx>. |
624d0f07 RS |
3525 | (define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq") |
3526 | (UNSPEC_COND_CMPGE_WIDE "ge") | |
3527 | (UNSPEC_COND_CMPGT_WIDE "gt") | |
3528 | (UNSPEC_COND_CMPHI_WIDE "hi") | |
3529 | (UNSPEC_COND_CMPHS_WIDE "hs") | |
3530 | (UNSPEC_COND_CMPLE_WIDE "le") | |
3531 | (UNSPEC_COND_CMPLO_WIDE "lo") | |
3532 | (UNSPEC_COND_CMPLS_WIDE "ls") | |
3533 | (UNSPEC_COND_CMPLT_WIDE "lt") | |
3534 | (UNSPEC_COND_CMPNE_WIDE "ne") | |
3535 | (UNSPEC_COND_FCMEQ "eq") | |
cb18e86d RS |
3536 | (UNSPEC_COND_FCMGE "ge") |
3537 | (UNSPEC_COND_FCMGT "gt") | |
3538 | (UNSPEC_COND_FCMLE "le") | |
3539 | (UNSPEC_COND_FCMLT "lt") | |
4a942af6 | 3540 | (UNSPEC_COND_FCMNE "ne") |
0a09a948 RS |
3541 | (UNSPEC_WHILEGE "ge") |
3542 | (UNSPEC_WHILEGT "gt") | |
3543 | (UNSPEC_WHILEHI "hi") | |
3544 | (UNSPEC_WHILEHS "hs") | |
6ad9571b RS |
3545 | (UNSPEC_WHILELE "le") |
3546 | (UNSPEC_WHILELO "lo") | |
3547 | (UNSPEC_WHILELS "ls") | |
3548 | (UNSPEC_WHILELT "lt") | |
58c036c8 RS |
3549 | (UNSPEC_WHILERW "rw") |
3550 | (UNSPEC_WHILEWR "wr")]) | |
624d0f07 | 3551 | |
0a09a948 RS |
3552 | (define_int_attr while_optab_cmp [(UNSPEC_WHILEGE "ge") |
3553 | (UNSPEC_WHILEGT "gt") | |
3554 | (UNSPEC_WHILEHI "ugt") | |
3555 | (UNSPEC_WHILEHS "uge") | |
3556 | (UNSPEC_WHILELE "le") | |
6ad9571b RS |
3557 | (UNSPEC_WHILELO "ult") |
3558 | (UNSPEC_WHILELS "ule") | |
bad5e58a RS |
3559 | (UNSPEC_WHILELT "lt") |
3560 | (UNSPEC_WHILERW "rw") | |
3561 | (UNSPEC_WHILEWR "wr")]) | |
624d0f07 | 3562 | |
58c036c8 RS |
3563 | (define_int_attr raw_war [(UNSPEC_WHILERW "raw") |
3564 | (UNSPEC_WHILEWR "war")]) | |
3565 | ||
624d0f07 RS |
3566 | (define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b") |
3567 | (UNSPEC_BRKN "n") | |
3568 | (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")]) | |
3569 | ||
3570 | (define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")]) | |
cb18e86d | 3571 | |
0a09a948 RS |
3572 | (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb") |
3573 | (UNSPEC_ADCLT "adclt") | |
3574 | (UNSPEC_ADDHNB "addhnb") | |
3575 | (UNSPEC_ADDHNT "addhnt") | |
3576 | (UNSPEC_ADDP "addp") | |
3577 | (UNSPEC_ANDV "andv") | |
624d0f07 | 3578 | (UNSPEC_ASHIFTRT_WIDE "asr") |
0a09a948 RS |
3579 | (UNSPEC_ASHIFT_WIDE "lsl") |
3580 | (UNSPEC_ASRD "asrd") | |
3581 | (UNSPEC_BDEP "bdep") | |
3582 | (UNSPEC_BEXT "bext") | |
3583 | (UNSPEC_BGRP "bgrp") | |
3584 | (UNSPEC_CADD90 "cadd") | |
3585 | (UNSPEC_CADD270 "cadd") | |
3586 | (UNSPEC_CDOT "cdot") | |
3587 | (UNSPEC_CDOT90 "cdot") | |
3588 | (UNSPEC_CDOT180 "cdot") | |
3589 | (UNSPEC_CDOT270 "cdot") | |
3590 | (UNSPEC_CMLA "cmla") | |
3591 | (UNSPEC_CMLA90 "cmla") | |
3592 | (UNSPEC_CMLA180 "cmla") | |
3593 | (UNSPEC_CMLA270 "cmla") | |
3594 | (UNSPEC_EORBT "eorbt") | |
3595 | (UNSPEC_EORTB "eortb") | |
3596 | (UNSPEC_IORV "orv") | |
624d0f07 | 3597 | (UNSPEC_LSHIFTRT_WIDE "lsr") |
0a09a948 RS |
3598 | (UNSPEC_MATCH "match") |
3599 | (UNSPEC_NMATCH "nmatch") | |
3600 | (UNSPEC_PMULLB "pmullb") | |
3601 | (UNSPEC_PMULLB_PAIR "pmullb") | |
3602 | (UNSPEC_PMULLT "pmullt") | |
3603 | (UNSPEC_PMULLT_PAIR "pmullt") | |
3604 | (UNSPEC_RADDHNB "raddhnb") | |
3605 | (UNSPEC_RADDHNT "raddhnt") | |
624d0f07 | 3606 | (UNSPEC_RBIT "rbit") |
d7a09c44 RS |
3607 | (UNSPEC_REVB "revb") |
3608 | (UNSPEC_REVH "revh") | |
0a09a948 RS |
3609 | (UNSPEC_REVW "revw") |
3610 | (UNSPEC_RSHRNB "rshrnb") | |
3611 | (UNSPEC_RSHRNT "rshrnt") | |
3612 | (UNSPEC_RSQRTE "ursqrte") | |
3613 | (UNSPEC_RSUBHNB "rsubhnb") | |
3614 | (UNSPEC_RSUBHNT "rsubhnt") | |
3615 | (UNSPEC_SABDLB "sabdlb") | |
3616 | (UNSPEC_SABDLT "sabdlt") | |
3617 | (UNSPEC_SADALP "sadalp") | |
3618 | (UNSPEC_SADDLB "saddlb") | |
3619 | (UNSPEC_SADDLBT "saddlbt") | |
3620 | (UNSPEC_SADDLT "saddlt") | |
3621 | (UNSPEC_SADDWB "saddwb") | |
3622 | (UNSPEC_SADDWT "saddwt") | |
3623 | (UNSPEC_SBCLB "sbclb") | |
3624 | (UNSPEC_SBCLT "sbclt") | |
3625 | (UNSPEC_SHADD "shadd") | |
3626 | (UNSPEC_SHRNB "shrnb") | |
3627 | (UNSPEC_SHRNT "shrnt") | |
3628 | (UNSPEC_SHSUB "shsub") | |
3629 | (UNSPEC_SLI "sli") | |
3630 | (UNSPEC_SMAXP "smaxp") | |
3631 | (UNSPEC_SMAXV "smaxv") | |
3632 | (UNSPEC_SMINP "sminp") | |
3633 | (UNSPEC_SMINV "sminv") | |
3634 | (UNSPEC_SMUL_HIGHPART "smulh") | |
3635 | (UNSPEC_SMULLB "smullb") | |
3636 | (UNSPEC_SMULLT "smullt") | |
3637 | (UNSPEC_SQCADD90 "sqcadd") | |
3638 | (UNSPEC_SQCADD270 "sqcadd") | |
3639 | (UNSPEC_SQDMULH "sqdmulh") | |
3640 | (UNSPEC_SQDMULLB "sqdmullb") | |
3641 | (UNSPEC_SQDMULLBT "sqdmullbt") | |
3642 | (UNSPEC_SQDMULLT "sqdmullt") | |
3643 | (UNSPEC_SQRDCMLAH "sqrdcmlah") | |
3644 | (UNSPEC_SQRDCMLAH90 "sqrdcmlah") | |
3645 | (UNSPEC_SQRDCMLAH180 "sqrdcmlah") | |
3646 | (UNSPEC_SQRDCMLAH270 "sqrdcmlah") | |
3647 | (UNSPEC_SQRDMLAH "sqrdmlah") | |
3648 | (UNSPEC_SQRDMLSH "sqrdmlsh") | |
3649 | (UNSPEC_SQRDMULH "sqrdmulh") | |
3650 | (UNSPEC_SQRSHL "sqrshl") | |
3651 | (UNSPEC_SQRSHRNB "sqrshrnb") | |
3652 | (UNSPEC_SQRSHRNT "sqrshrnt") | |
3653 | (UNSPEC_SQRSHRUNB "sqrshrunb") | |
3654 | (UNSPEC_SQRSHRUNT "sqrshrunt") | |
3655 | (UNSPEC_SQSHL "sqshl") | |
3656 | (UNSPEC_SQSHLU "sqshlu") | |
3657 | (UNSPEC_SQSHRNB "sqshrnb") | |
3658 | (UNSPEC_SQSHRNT "sqshrnt") | |
3659 | (UNSPEC_SQSHRUNB "sqshrunb") | |
3660 | (UNSPEC_SQSHRUNT "sqshrunt") | |
3661 | (UNSPEC_SQXTNB "sqxtnb") | |
3662 | (UNSPEC_SQXTNT "sqxtnt") | |
3663 | (UNSPEC_SQXTUNB "sqxtunb") | |
3664 | (UNSPEC_SQXTUNT "sqxtunt") | |
3665 | (UNSPEC_SRHADD "srhadd") | |
3666 | (UNSPEC_SRI "sri") | |
3667 | (UNSPEC_SRSHL "srshl") | |
3668 | (UNSPEC_SRSHR "srshr") | |
3669 | (UNSPEC_SSHLLB "sshllb") | |
3670 | (UNSPEC_SSHLLT "sshllt") | |
3671 | (UNSPEC_SSUBLB "ssublb") | |
3672 | (UNSPEC_SSUBLBT "ssublbt") | |
3673 | (UNSPEC_SSUBLT "ssublt") | |
3674 | (UNSPEC_SSUBLTB "ssubltb") | |
3675 | (UNSPEC_SSUBWB "ssubwb") | |
3676 | (UNSPEC_SSUBWT "ssubwt") | |
3677 | (UNSPEC_SUBHNB "subhnb") | |
3678 | (UNSPEC_SUBHNT "subhnt") | |
3679 | (UNSPEC_SUQADD "suqadd") | |
3680 | (UNSPEC_UABDLB "uabdlb") | |
3681 | (UNSPEC_UABDLT "uabdlt") | |
3682 | (UNSPEC_UADALP "uadalp") | |
3683 | (UNSPEC_UADDLB "uaddlb") | |
3684 | (UNSPEC_UADDLT "uaddlt") | |
3685 | (UNSPEC_UADDWB "uaddwb") | |
3686 | (UNSPEC_UADDWT "uaddwt") | |
3687 | (UNSPEC_UHADD "uhadd") | |
3688 | (UNSPEC_UHSUB "uhsub") | |
3689 | (UNSPEC_UMAXP "umaxp") | |
3690 | (UNSPEC_UMAXV "umaxv") | |
3691 | (UNSPEC_UMINP "uminp") | |
3692 | (UNSPEC_UMINV "uminv") | |
3693 | (UNSPEC_UMUL_HIGHPART "umulh") | |
3694 | (UNSPEC_UMULLB "umullb") | |
3695 | (UNSPEC_UMULLT "umullt") | |
3696 | (UNSPEC_UQRSHL "uqrshl") | |
3697 | (UNSPEC_UQRSHRNB "uqrshrnb") | |
3698 | (UNSPEC_UQRSHRNT "uqrshrnt") | |
3699 | (UNSPEC_UQSHL "uqshl") | |
3700 | (UNSPEC_UQSHRNB "uqshrnb") | |
3701 | (UNSPEC_UQSHRNT "uqshrnt") | |
3702 | (UNSPEC_UQXTNB "uqxtnb") | |
3703 | (UNSPEC_UQXTNT "uqxtnt") | |
3704 | (UNSPEC_URECPE "urecpe") | |
3705 | (UNSPEC_URHADD "urhadd") | |
3706 | (UNSPEC_URSHL "urshl") | |
3707 | (UNSPEC_URSHR "urshr") | |
3708 | (UNSPEC_USHLLB "ushllb") | |
3709 | (UNSPEC_USHLLT "ushllt") | |
3710 | (UNSPEC_USQADD "usqadd") | |
3711 | (UNSPEC_USUBLB "usublb") | |
3712 | (UNSPEC_USUBLT "usublt") | |
3713 | (UNSPEC_USUBWB "usubwb") | |
3714 | (UNSPEC_USUBWT "usubwt") | |
3715 | (UNSPEC_XORV "eorv")]) | |
3716 | ||
3717 | (define_int_attr sve_int_op_rev [(UNSPEC_SHADD "shadd") | |
3718 | (UNSPEC_SHSUB "shsubr") | |
3719 | (UNSPEC_SQRSHL "sqrshlr") | |
3720 | (UNSPEC_SRHADD "srhadd") | |
3721 | (UNSPEC_SRSHL "srshlr") | |
3722 | (UNSPEC_UHADD "uhadd") | |
3723 | (UNSPEC_UHSUB "uhsubr") | |
3724 | (UNSPEC_UQRSHL "uqrshlr") | |
3725 | (UNSPEC_URHADD "urhadd") | |
3726 | (UNSPEC_URSHL "urshlr")]) | |
3727 | ||
3728 | (define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb") | |
3729 | (UNSPEC_SABDLT "sabalt") | |
3730 | (UNSPEC_SMULLB "smlalb") | |
3731 | (UNSPEC_SMULLT "smlalt") | |
3732 | (UNSPEC_UABDLB "uabalb") | |
3733 | (UNSPEC_UABDLT "uabalt") | |
3734 | (UNSPEC_UMULLB "umlalb") | |
3735 | (UNSPEC_UMULLT "umlalt")]) | |
3736 | ||
3737 | (define_int_attr sve_int_qadd_op [(UNSPEC_SQDMULLB "sqdmlalb") | |
3738 | (UNSPEC_SQDMULLBT "sqdmlalbt") | |
3739 | (UNSPEC_SQDMULLT "sqdmlalt")]) | |
3740 | ||
3741 | (define_int_attr sve_int_sub_op [(UNSPEC_SMULLB "smlslb") | |
3742 | (UNSPEC_SMULLT "smlslt") | |
3743 | (UNSPEC_UMULLB "umlslb") | |
3744 | (UNSPEC_UMULLT "umlslt")]) | |
3745 | ||
3746 | (define_int_attr sve_int_qsub_op [(UNSPEC_SQDMULLB "sqdmlslb") | |
3747 | (UNSPEC_SQDMULLBT "sqdmlslbt") | |
3748 | (UNSPEC_SQDMULLT "sqdmlslt")]) | |
b0760a40 | 3749 | |
896dff99 RS |
3750 | (define_int_attr sve_fp_op [(UNSPEC_BFDOT "bfdot") |
3751 | (UNSPEC_BFMLALB "bfmlalb") | |
3752 | (UNSPEC_BFMLALT "bfmlalt") | |
3753 | (UNSPEC_BFMMLA "bfmmla") | |
3754 | (UNSPEC_FRECPE "frecpe") | |
624d0f07 RS |
3755 | (UNSPEC_FRECPS "frecps") |
3756 | (UNSPEC_RSQRTE "frsqrte") | |
3757 | (UNSPEC_RSQRTS "frsqrts") | |
0a09a948 | 3758 | (UNSPEC_FADDP "faddp") |
624d0f07 | 3759 | (UNSPEC_FADDV "faddv") |
36696774 | 3760 | (UNSPEC_FEXPA "fexpa") |
0a09a948 | 3761 | (UNSPEC_FMAXNMP "fmaxnmp") |
b0760a40 | 3762 | (UNSPEC_FMAXNMV "fmaxnmv") |
0a09a948 | 3763 | (UNSPEC_FMAXP "fmaxp") |
b0760a40 | 3764 | (UNSPEC_FMAXV "fmaxv") |
0a09a948 | 3765 | (UNSPEC_FMINNMP "fminnmp") |
b0760a40 | 3766 | (UNSPEC_FMINNMV "fminnmv") |
0a09a948 | 3767 | (UNSPEC_FMINP "fminp") |
b0760a40 | 3768 | (UNSPEC_FMINV "fminv") |
624d0f07 | 3769 | (UNSPEC_FMLA "fmla") |
0a09a948 RS |
3770 | (UNSPEC_FMLALB "fmlalb") |
3771 | (UNSPEC_FMLALT "fmlalt") | |
624d0f07 | 3772 | (UNSPEC_FMLS "fmls") |
0a09a948 RS |
3773 | (UNSPEC_FMLSLB "fmlslb") |
3774 | (UNSPEC_FMLSLT "fmlslt") | |
36696774 | 3775 | (UNSPEC_FMMLA "fmmla") |
624d0f07 RS |
3776 | (UNSPEC_FTSMUL "ftsmul") |
3777 | (UNSPEC_FTSSEL "ftssel") | |
b0760a40 | 3778 | (UNSPEC_COND_FABS "fabs") |
d45b20a5 | 3779 | (UNSPEC_COND_FADD "fadd") |
0a09a948 RS |
3780 | (UNSPEC_COND_FCVTLT "fcvtlt") |
3781 | (UNSPEC_COND_FCVTX "fcvtx") | |
cb18e86d | 3782 | (UNSPEC_COND_FDIV "fdiv") |
0a09a948 | 3783 | (UNSPEC_COND_FLOGB "flogb") |
624d0f07 | 3784 | (UNSPEC_COND_FMAX "fmax") |
cb18e86d | 3785 | (UNSPEC_COND_FMAXNM "fmaxnm") |
624d0f07 | 3786 | (UNSPEC_COND_FMIN "fmin") |
cb18e86d RS |
3787 | (UNSPEC_COND_FMINNM "fminnm") |
3788 | (UNSPEC_COND_FMUL "fmul") | |
624d0f07 | 3789 | (UNSPEC_COND_FMULX "fmulx") |
d45b20a5 | 3790 | (UNSPEC_COND_FNEG "fneg") |
624d0f07 | 3791 | (UNSPEC_COND_FRECPX "frecpx") |
d45b20a5 RS |
3792 | (UNSPEC_COND_FRINTA "frinta") |
3793 | (UNSPEC_COND_FRINTI "frinti") | |
3794 | (UNSPEC_COND_FRINTM "frintm") | |
3795 | (UNSPEC_COND_FRINTN "frintn") | |
3796 | (UNSPEC_COND_FRINTP "frintp") | |
3797 | (UNSPEC_COND_FRINTX "frintx") | |
3798 | (UNSPEC_COND_FRINTZ "frintz") | |
624d0f07 | 3799 | (UNSPEC_COND_FSCALE "fscale") |
d45b20a5 | 3800 | (UNSPEC_COND_FSQRT "fsqrt") |
cb18e86d RS |
3801 | (UNSPEC_COND_FSUB "fsub")]) |
3802 | ||
3803 | (define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd") | |
3804 | (UNSPEC_COND_FDIV "fdivr") | |
624d0f07 | 3805 | (UNSPEC_COND_FMAX "fmax") |
cb18e86d | 3806 | (UNSPEC_COND_FMAXNM "fmaxnm") |
624d0f07 | 3807 | (UNSPEC_COND_FMIN "fmin") |
cb18e86d RS |
3808 | (UNSPEC_COND_FMINNM "fminnm") |
3809 | (UNSPEC_COND_FMUL "fmul") | |
624d0f07 | 3810 | (UNSPEC_COND_FMULX "fmulx") |
cb18e86d | 3811 | (UNSPEC_COND_FSUB "fsubr")]) |
a08acce8 | 3812 | |
0a09a948 RS |
3813 | (define_int_attr rot [(UNSPEC_CADD90 "90") |
3814 | (UNSPEC_CADD270 "270") | |
3815 | (UNSPEC_CDOT "0") | |
3816 | (UNSPEC_CDOT90 "90") | |
3817 | (UNSPEC_CDOT180 "180") | |
3818 | (UNSPEC_CDOT270 "270") | |
3819 | (UNSPEC_CMLA "0") | |
3820 | (UNSPEC_CMLA90 "90") | |
3821 | (UNSPEC_CMLA180 "180") | |
3822 | (UNSPEC_CMLA270 "270") | |
3823 | (UNSPEC_FCADD90 "90") | |
9d63f43b TC |
3824 | (UNSPEC_FCADD270 "270") |
3825 | (UNSPEC_FCMLA "0") | |
3826 | (UNSPEC_FCMLA90 "90") | |
3827 | (UNSPEC_FCMLA180 "180") | |
624d0f07 | 3828 | (UNSPEC_FCMLA270 "270") |
0a09a948 RS |
3829 | (UNSPEC_SQCADD90 "90") |
3830 | (UNSPEC_SQCADD270 "270") | |
3831 | (UNSPEC_SQRDCMLAH "0") | |
3832 | (UNSPEC_SQRDCMLAH90 "90") | |
3833 | (UNSPEC_SQRDCMLAH180 "180") | |
3834 | (UNSPEC_SQRDCMLAH270 "270") | |
624d0f07 RS |
3835 | (UNSPEC_COND_FCADD90 "90") |
3836 | (UNSPEC_COND_FCADD270 "270") | |
3837 | (UNSPEC_COND_FCMLA "0") | |
3838 | (UNSPEC_COND_FCMLA90 "90") | |
3839 | (UNSPEC_COND_FCMLA180 "180") | |
ad260343 TC |
3840 | (UNSPEC_COND_FCMLA270 "270") |
3841 | (UNSPEC_FCMUL "0") | |
3842 | (UNSPEC_FCMUL_CONJ "180")]) | |
3843 | ||
3844 | ;; A conjucate is a negation of the imaginary component | |
3845 | ;; The number in the unspecs are the rotation component of the instruction, e.g | |
3846 | ;; FCMLA180 means use the instruction with #180. | |
3847 | ;; The iterator is used to produce the right name mangling for the function. | |
3848 | (define_int_attr conj_op [(UNSPEC_FCMLA180 "") | |
3849 | (UNSPEC_FCMLA180_CONJ "_conj") | |
3850 | (UNSPEC_FCMLA "") | |
3851 | (UNSPEC_FCMLA_CONJ "_conj") | |
3852 | (UNSPEC_FCMUL "") | |
3853 | (UNSPEC_FCMUL_CONJ "_conj") | |
3854 | (UNSPEC_CMLA "") | |
3855 | (UNSPEC_CMLA180 "") | |
3856 | (UNSPEC_CMLA180_CONJ "_conj") | |
3857 | (UNSPEC_CMLA_CONJ "_conj") | |
3858 | (UNSPEC_CMUL "") | |
3859 | (UNSPEC_CMUL_CONJ "_conj")]) | |
3860 | ||
3861 | ;; The complex operations when performed on a real complex number require two | |
3862 | ;; instructions to perform the operation. e.g. complex multiplication requires | |
3863 | ;; two FCMUL with a particular rotation value. | |
3864 | ;; | |
3865 | ;; These values can be looked up in rotsplit1 and rotsplit2. as an example | |
3866 | ;; FCMUL needs the first instruction to use #0 and the second #90. | |
3867 | (define_int_attr rotsplit1 [(UNSPEC_FCMLA "0") | |
3868 | (UNSPEC_FCMLA_CONJ "0") | |
3869 | (UNSPEC_FCMUL "0") | |
3870 | (UNSPEC_FCMUL_CONJ "0") | |
3871 | (UNSPEC_FCMLA180 "180") | |
3872 | (UNSPEC_FCMLA180_CONJ "180")]) | |
3873 | ||
3874 | (define_int_attr rotsplit2 [(UNSPEC_FCMLA "90") | |
3875 | (UNSPEC_FCMLA_CONJ "270") | |
3876 | (UNSPEC_FCMUL "90") | |
3877 | (UNSPEC_FCMUL_CONJ "270") | |
3878 | (UNSPEC_FCMLA180 "270") | |
3879 | (UNSPEC_FCMLA180_CONJ "90")]) | |
3880 | ||
3881 | ;; SVE has slightly different namings from NEON so we have to split these | |
3882 | ;; iterators. | |
3883 | (define_int_attr sve_rot1 [(UNSPEC_FCMLA "") | |
3884 | (UNSPEC_FCMLA_CONJ "") | |
3885 | (UNSPEC_FCMUL "") | |
3886 | (UNSPEC_FCMUL_CONJ "") | |
3887 | (UNSPEC_FCMLA180 "180") | |
3888 | (UNSPEC_FCMLA180_CONJ "180") | |
3889 | (UNSPEC_CMLA "") | |
3890 | (UNSPEC_CMLA_CONJ "") | |
3891 | (UNSPEC_CMUL "") | |
3892 | (UNSPEC_CMUL_CONJ "") | |
3893 | (UNSPEC_CMLA180 "180") | |
3894 | (UNSPEC_CMLA180_CONJ "180")]) | |
3895 | ||
3896 | (define_int_attr sve_rot2 [(UNSPEC_FCMLA "90") | |
3897 | (UNSPEC_FCMLA_CONJ "270") | |
3898 | (UNSPEC_FCMUL "90") | |
3899 | (UNSPEC_FCMUL_CONJ "270") | |
3900 | (UNSPEC_FCMLA180 "270") | |
3901 | (UNSPEC_FCMLA180_CONJ "90") | |
3902 | (UNSPEC_CMLA "90") | |
3903 | (UNSPEC_CMLA_CONJ "270") | |
3904 | (UNSPEC_CMUL "90") | |
3905 | (UNSPEC_CMUL_CONJ "270") | |
3906 | (UNSPEC_CMLA180 "270") | |
3907 | (UNSPEC_CMLA180_CONJ "90")]) | |
3908 | ||
3909 | ||
3910 | (define_int_attr fcmac1 [(UNSPEC_FCMLA "a") (UNSPEC_FCMLA_CONJ "a") | |
3911 | (UNSPEC_FCMLA180 "s") (UNSPEC_FCMLA180_CONJ "s") | |
3912 | (UNSPEC_CMLA "a") (UNSPEC_CMLA_CONJ "a") | |
3913 | (UNSPEC_CMLA180 "s") (UNSPEC_CMLA180_CONJ "s")]) | |
9d63f43b | 3914 | |
b41d1f6e RS |
3915 | (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla") |
3916 | (UNSPEC_COND_FMLS "fmls") | |
3917 | (UNSPEC_COND_FNMLA "fnmla") | |
3918 | (UNSPEC_COND_FNMLS "fnmls")]) | |
3919 | ||
3920 | (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad") | |
3921 | (UNSPEC_COND_FMLS "fmsb") | |
3922 | (UNSPEC_COND_FNMLA "fnmad") | |
3923 | (UNSPEC_COND_FNMLS "fnmsb")]) | |
0254ed79 | 3924 | |
624d0f07 RS |
3925 | ;; The register constraint to use for the final operand in a binary BRK. |
3926 | (define_int_attr brk_reg_con [(UNSPEC_BRKN "0") | |
3927 | (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")]) | |
3928 | ||
3929 | ;; The register number to print for the above. | |
3930 | (define_int_attr brk_reg_opno [(UNSPEC_BRKN "0") | |
3931 | (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")]) | |
3932 | ||
0254ed79 RS |
3933 | ;; The predicate to use for the first input operand in a floating-point |
3934 | ;; <optab><mode>3 pattern. | |
3935 | (define_int_attr sve_pred_fp_rhs1_operand | |
3936 | [(UNSPEC_COND_FADD "register_operand") | |
3937 | (UNSPEC_COND_FDIV "register_operand") | |
624d0f07 | 3938 | (UNSPEC_COND_FMAX "register_operand") |
0254ed79 | 3939 | (UNSPEC_COND_FMAXNM "register_operand") |
624d0f07 | 3940 | (UNSPEC_COND_FMIN "register_operand") |
0254ed79 RS |
3941 | (UNSPEC_COND_FMINNM "register_operand") |
3942 | (UNSPEC_COND_FMUL "register_operand") | |
624d0f07 | 3943 | (UNSPEC_COND_FMULX "register_operand") |
0254ed79 RS |
3944 | (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")]) |
3945 | ||
3946 | ;; The predicate to use for the second input operand in a floating-point | |
3947 | ;; <optab><mode>3 pattern. | |
3948 | (define_int_attr sve_pred_fp_rhs2_operand | |
3949 | [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand") | |
3950 | (UNSPEC_COND_FDIV "register_operand") | |
624d0f07 | 3951 | (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand") |
75079ddf | 3952 | (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand") |
624d0f07 | 3953 | (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand") |
75079ddf | 3954 | (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand") |
0254ed79 | 3955 | (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand") |
624d0f07 | 3956 | (UNSPEC_COND_FMULX "register_operand") |
0254ed79 | 3957 | (UNSPEC_COND_FSUB "register_operand")]) |
a19ba9e1 RS |
3958 | |
3959 | ;; Likewise for immediates only. | |
3960 | (define_int_attr sve_pred_fp_rhs2_immediate | |
624d0f07 RS |
3961 | [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate") |
3962 | (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate") | |
3963 | (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate") | |
a19ba9e1 RS |
3964 | (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate") |
3965 | (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")]) | |
d7a09c44 | 3966 | |
624d0f07 RS |
3967 | ;; The maximum number of element bits that an instruction can handle. |
3968 | (define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32") | |
3969 | (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")]) | |
3970 | ||
d7a09c44 | 3971 | ;; The minimum number of element bits that an instruction can handle. |
624d0f07 RS |
3972 | (define_int_attr min_elem_bits [(UNSPEC_RBIT "8") |
3973 | (UNSPEC_REVB "16") | |
d7a09c44 RS |
3974 | (UNSPEC_REVH "32") |
3975 | (UNSPEC_REVW "64")]) | |
58c036c8 RS |
3976 | |
3977 | (define_int_attr unspec [(UNSPEC_WHILERW "UNSPEC_WHILERW") | |
3978 | (UNSPEC_WHILEWR "UNSPEC_WHILEWR")]) | |
0d7e5fa6 AC |
3979 | |
3980 | ;; Iterators and attributes for fpcr fpsr getter setters | |
3981 | ||
3982 | (define_int_iterator GET_FPSCR | |
3983 | [UNSPECV_GET_FPSR UNSPECV_GET_FPCR]) | |
3984 | ||
3985 | (define_int_iterator SET_FPSCR | |
3986 | [UNSPECV_SET_FPSR UNSPECV_SET_FPCR]) | |
3987 | ||
3988 | (define_int_attr fpscr_name | |
3989 | [(UNSPECV_GET_FPSR "fpsr") | |
3990 | (UNSPECV_SET_FPSR "fpsr") | |
3991 | (UNSPECV_GET_FPCR "fpcr") | |
3992 | (UNSPECV_SET_FPCR "fpcr")]) | |
b096a6eb RS |
3993 | |
3994 | (define_int_attr bits_etype [(8 "b") (16 "h") (32 "s")]) |