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43e9d192 1;; Machine description for AArch64 architecture.
8d9254fc 2;; Copyright (C) 2009-2020 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
4a2095eb
RH		 32;; "Iterator" for just TI -- features like @pattern only work with iterators.
33(define_mode_iterator JUST_TI [TI])
34
43e9d192
IB		 35;; Iterator for QI and HI modes
36(define_mode_iterator SHORT [QI HI])
37
624d0f07
RS		 38;; Iterators for single modes, for "@" patterns.
39(define_mode_iterator SI_ONLY [SI])
40(define_mode_iterator DI_ONLY [DI])
41
43e9d192
IB		 42;; Iterator for all integer modes (up to 64-bit)
43(define_mode_iterator ALLI [QI HI SI DI])
44
c0111dc4
RE		 45;; Iterator for all integer modes (up to 128-bit)
46(define_mode_iterator ALLI_TI [QI HI SI DI TI])
47
43e9d192
IB		 48;; Iterator for all integer modes that can be extended (up to 64-bit)
49(define_mode_iterator ALLX [QI HI SI])
50
51;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
52(define_mode_iterator GPF [SF DF])
53
d7f33f07
JW		 54;; Iterator for all scalar floating point modes (HF, SF, DF)
55(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
56
90e6443f
TC		 57;; Iterator for all scalar floating point modes (HF, SF, DF)
58(define_mode_iterator GPF_HF [HF SF DF])
59
09fcd8e1
RR		 60;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
61(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 62
922f9c25
AL		 63;; Double vector modes.
64(define_mode_iterator VDF [V2SF V4HF])
65
b4f50fd4
RR		 66;; Iterator for all scalar floating point modes (SF, DF and TF)
67(define_mode_iterator GPF_TF [SF DF TF])
68
43cacb12 69;; Integer Advanced SIMD modes.
43e9d192
IB		 70(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
71
43cacb12 72;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 73(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
74
43cacb12
RS		 75;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
76;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 77(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
78
79;; Double vector modes.
71a11456 80(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 81
dfe1da23
JW		 82;; All modes stored in registers d0-d31.
83(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
84
85;; Copy of the above.
86(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
87
43cacb12 88;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 89(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
90
91;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
92(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
93
94;; Quad vector modes.
71a11456 95(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 96
9f5361c8
KT		 97;; Copy of the above.
98(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
99
d21052eb
TC		 100;; Quad integer vector modes.
101(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
102
51437269 103;; VQ without 2 element modes.
71a11456 104(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 105
106;; Quad vector with only 2 element modes.
107(define_mode_iterator VQ_2E [V2DI V2DF])
108
28514dda
YZ		 109;; This mode iterator allows :P to be used for patterns that operate on
110;; addresses in different modes. In LP64, only DI will match, while in
111;; ILP32, either can match.
112(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
113 (DI "ptr_mode == DImode || Pmode == DImode")])
114
43e9d192
IB		 115;; This mode iterator allows :PTR to be used for patterns that operate on
116;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 117(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 118
43cacb12 119;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 120(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
121
43cacb12 122;; Advanced SIMD Float modes.
43e9d192 123(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 124(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
125 (V8HF "TARGET_SIMD_F16INST")
126 V2SF V4SF V2DF])
43e9d192 127
43cacb12 128;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 129(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
130 (V8HF "TARGET_SIMD_F16INST")
131 V2SF V4SF V2DF DF])
d7f33f07
JW		 132(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
133 (V8HF "TARGET_SIMD_F16INST")
134 V2SF V4SF V2DF
135 (HF "TARGET_SIMD_F16INST")
136 SF DF])
f421c516 137
10bd1d96
KT		 138;; Scalar and vetor modes for SF, DF.
139(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
140
43cacb12 141;; Advanced SIMD single Float modes.
828e70c1
JG		 142(define_mode_iterator VDQSF [V2SF V4SF])
143
03873eb9
AL		 144;; Quad vector Float modes with half/single elements.
145(define_mode_iterator VQ_HSF [V8HF V4SF])
146
fc21784d
JG		 147;; Modes suitable to use as the return type of a vcond expression.
148(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
149
43cacb12 150;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 151(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
152
43cacb12 153;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 154(define_mode_iterator V2F [V2SF V2DF])
155
43cacb12 156;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 157(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
158
43cacb12 159;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 160(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
161 V4HF V8HF V2SF V4SF V2DF])
162
88119b46
KT		 163;; The VALL_F16 modes except the 128-bit 2-element ones.
164(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
165 V4HF V8HF V2SF V4SF])
166
43cacb12 167;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 168(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
169
43cacb12 170;; All Advanced SIMD modes and DI.
71a11456
AL		 171(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
172 V4HF V8HF V2SF V4SF V2DF DI])
173
43cacb12 174;; All Advanced SIMD modes, plus DI and DF.
46e778c4 175(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 176 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 177
43cacb12 178;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 179(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
180
43cacb12 181;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 182(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 183
184;; All double integer narrow-able modes.
185(define_mode_iterator VDN [V4HI V2SI DI])
186
187;; All quad integer narrow-able modes.
188(define_mode_iterator VQN [V8HI V4SI V2DI])
189
43cacb12
RS		 190;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
191;; integer modes
43e9d192
IB		 192(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
193
194;; All quad integer widen-able modes.
195(define_mode_iterator VQW [V16QI V8HI V4SI])
196
197;; Double vector modes for combines.
7c369485 198(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 199
43cacb12 200;; Advanced SIMD modes except double int.
43e9d192 201(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 202(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
203 V4HF V8HF V2SF V4SF V2DF])
43e9d192 204
43cacb12 205;; Advanced SIMD modes for S type.
58a3bd25
FY		 206(define_mode_iterator VDQ_SI [V2SI V4SI])
207
43cacb12 208;; Advanced SIMD modes for S and D.
2644d4d9
JW		 209(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
210
43cacb12 211;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 212(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
213 (V8HI "TARGET_SIMD_F16INST")
214 V2SI V4SI V2DI])
215
43cacb12 216;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 217(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
218
43cacb12 219;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 220(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
221 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 222 V2SI V4SI V2DI
223 (HI "TARGET_SIMD_F16INST")
224 SI DI])
33d72b63 225
43cacb12 226;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 227(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
228
43cacb12 229;; Advanced SIMD modes for H and S types.
43e9d192
IB		 230(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
231
43cacb12 232;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 233(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
234
43cacb12 235;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 236(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
237
43cacb12 238;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 239(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
240
43cacb12 241;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 242(define_mode_iterator VD_HSI [V4HI V2SI])
243
244;; Scalar 64-bit container: 16, 32-bit integer modes
245(define_mode_iterator SD_HSI [HI SI])
246
43cacb12 247;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 248(define_mode_iterator VQ_HSI [V8HI V4SI])
249
250;; All byte modes.
251(define_mode_iterator VB [V8QI V16QI])
252
5e32e83b
JW		 253;; 2 and 4 lane SI modes.
254(define_mode_iterator VS [V2SI V4SI])
255
43e9d192
IB		 256(define_mode_iterator TX [TI TF])
257
43cacb12 258;; Advanced SIMD opaque structure modes.
43e9d192
IB		 259(define_mode_iterator VSTRUCT [OI CI XI])
260
261;; Double scalar modes
262(define_mode_iterator DX [DI DF])
263
dfe1da23
JW		 264;; Duplicate of the above
265(define_mode_iterator DX2 [DI DF])
266
267;; Single scalar modes
268(define_mode_iterator SX [SI SF])
269
270;; Duplicate of the above
271(define_mode_iterator SX2 [SI SF])
272
273;; Single and double integer and float modes
274(define_mode_iterator DSX [DF DI SF SI])
275
276
43cacb12 277;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 278(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
279 (V4HF "TARGET_SIMD_F16INST")
280 (V8HF "TARGET_SIMD_F16INST")
281 V2SF V4SF V2DF])
779aea46 282
43cacb12
RS		 283;; Modes available for Advanced SIMD <f>mul lane operations changing lane
284;; count.
779aea46
JG		 285(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
286
95eb5537 287;; Iterators for single modes, for "@" patterns.
624d0f07 288(define_mode_iterator VNx8HI_ONLY [VNx8HI])
95eb5537 289(define_mode_iterator VNx4SI_ONLY [VNx4SI])
624d0f07 290(define_mode_iterator VNx2DI_ONLY [VNx2DI])
95eb5537
RS		 291(define_mode_iterator VNx2DF_ONLY [VNx2DF])
292
9f4cbab8
RS		 293;; All SVE vector structure modes.
294(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
295 VNx16HF VNx8SF VNx4DF
296 VNx48QI VNx24HI VNx12SI VNx6DI
297 VNx24HF VNx12SF VNx6DF
298 VNx64QI VNx32HI VNx16SI VNx8DI
299 VNx32HF VNx16SF VNx8DF])
300
f75cdd2c
RS		 301;; All fully-packed SVE vector modes.
302(define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI
303 VNx8HF VNx4SF VNx2DF])
304
305;; All fully-packed SVE integer vector modes.
306(define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI])
43cacb12 307
f75cdd2c
RS		 308;; All fully-packed SVE floating-point vector modes.
309(define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
43cacb12 310
f75cdd2c
RS		 311;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
312;; elements.
313(define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
43cacb12 314
f75cdd2c
RS		 315;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
316(define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
95eb5537 317
f75cdd2c
RS		 318;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit
319;; elements.
320(define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI])
95eb5537 321
f75cdd2c
RS		 322;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit
323;; elements.
324(define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF])
a70965b1 325
f75cdd2c
RS		 326;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements.
327(define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
43cacb12 328
f75cdd2c
RS		 329;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements.
330(define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI])
bfaa08b7 331
f75cdd2c
RS		 332;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
333;; elements.
334(define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
bfaa08b7 335
f75cdd2c
RS		 336;; Fully-packed SVE vector modes that have 32-bit elements.
337(define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF])
43cacb12 338
f75cdd2c
RS		 339;; Fully-packed SVE vector modes that have 64-bit elements.
340(define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF])
43cacb12 341
6544cb52
RS		 342;; All partial SVE integer modes.
343(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI
344 VNx4HI VNx2HI
345 VNx2SI])
624d0f07 346
cc68f7c2
RS		 347;; All SVE vector modes.
348(define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI
349 VNx8HI VNx4HI VNx2HI
350 VNx8HF VNx4HF VNx2HF
351 VNx4SI VNx2SI
352 VNx4SF VNx2SF
353 VNx2DI
354 VNx2DF])
355
356;; All SVE integer vector modes.
357(define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
358 VNx8HI VNx4HI VNx2HI
359 VNx4SI VNx2SI
360 VNx2DI])
361
e58703e2
RS		 362;; SVE integer vector modes whose elements are 16 bits or wider.
363(define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI
364 VNx4SI VNx2SI
365 VNx2DI])
366
f8186eea
RS		 367;; SVE modes with 2 or 4 elements.
368(define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF
369 VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
370
371;; SVE modes with 2 elements.
372(define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF])
373
87a80d27
RS		 374;; SVE integer modes with 2 elements, excluding the widest element.
375(define_mode_iterator SVE_2BHSI [VNx2QI VNx2HI VNx2SI])
376
377;; SVE integer modes with 2 elements, excluding the narrowest element.
378(define_mode_iterator SVE_2HSDI [VNx2HI VNx2SI VNx2DI])
379
f8186eea
RS		 380;; SVE modes with 4 elements.
381(define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
382
87a80d27
RS		 383;; SVE integer modes with 4 elements, excluding the widest element.
384(define_mode_iterator SVE_4BHI [VNx4QI VNx4HI])
385
386;; SVE integer modes with 4 elements, excluding the narrowest element.
387(define_mode_iterator SVE_4HSI [VNx4HI VNx4SI])
388
624d0f07
RS		 389;; Modes involved in extending or truncating SVE data, for 8 elements per
390;; 128-bit block.
391(define_mode_iterator VNx8_NARROW [VNx8QI])
392(define_mode_iterator VNx8_WIDE [VNx8HI])
393
394;; ...same for 4 elements per 128-bit block.
395(define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI])
396(define_mode_iterator VNx4_WIDE [VNx4SI])
397
398;; ...same for 2 elements per 128-bit block.
399(define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])
400(define_mode_iterator VNx2_WIDE [VNx2DI])
401
43cacb12
RS		 402;; All SVE predicate modes.
403(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
404
405;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
406(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
407
624d0f07
RS		 408;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements.
409(define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI])
410
43e9d192
IB		 411;; ------------------------------------------------------------------
412;; Unspec enumerations for Advance SIMD. These could well go into
413;; aarch64.md but for their use in int_iterators here.
414;; ------------------------------------------------------------------
415
416(define_c_enum "unspec"
417 [
418 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
419 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 420 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 421 UNSPEC_FMAX ; Used in aarch64-simd.md.
422 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 423 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 424 UNSPEC_FMIN ; Used in aarch64-simd.md.
425 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 426 UNSPEC_FMINV ; Used in aarch64-simd.md.
427 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 428 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 429 UNSPEC_SMAXV ; Used in aarch64-simd.md.
430 UNSPEC_SMINV ; Used in aarch64-simd.md.
431 UNSPEC_UMAXV ; Used in aarch64-simd.md.
432 UNSPEC_UMINV ; Used in aarch64-simd.md.
433 UNSPEC_SHADD ; Used in aarch64-simd.md.
434 UNSPEC_UHADD ; Used in aarch64-simd.md.
435 UNSPEC_SRHADD ; Used in aarch64-simd.md.
436 UNSPEC_URHADD ; Used in aarch64-simd.md.
437 UNSPEC_SHSUB ; Used in aarch64-simd.md.
438 UNSPEC_UHSUB ; Used in aarch64-simd.md.
439 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
440 UNSPEC_URHSUB ; Used in aarch64-simd.md.
441 UNSPEC_ADDHN ; Used in aarch64-simd.md.
442 UNSPEC_RADDHN ; Used in aarch64-simd.md.
443 UNSPEC_SUBHN ; Used in aarch64-simd.md.
444 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
445 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
446 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
447 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
448 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
449 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
450 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
58cc9876
YW		 451 UNSPEC_SMULLB ; Used in aarch64-sve2.md.
452 UNSPEC_SMULLT ; Used in aarch64-sve2.md.
453 UNSPEC_UMULLB ; Used in aarch64-sve2.md.
454 UNSPEC_UMULLT ; Used in aarch64-sve2.md.
43e9d192 455 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 456 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 457 UNSPEC_USQADD ; Used in aarch64-simd.md.
458 UNSPEC_SUQADD ; Used in aarch64-simd.md.
459 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
460 UNSPEC_SQXTN ; Used in aarch64-simd.md.
461 UNSPEC_UQXTN ; Used in aarch64-simd.md.
462 UNSPEC_SSRA ; Used in aarch64-simd.md.
463 UNSPEC_USRA ; Used in aarch64-simd.md.
464 UNSPEC_SRSRA ; Used in aarch64-simd.md.
465 UNSPEC_URSRA ; Used in aarch64-simd.md.
466 UNSPEC_SRSHR ; Used in aarch64-simd.md.
467 UNSPEC_URSHR ; Used in aarch64-simd.md.
468 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
469 UNSPEC_SQSHL ; Used in aarch64-simd.md.
470 UNSPEC_UQSHL ; Used in aarch64-simd.md.
471 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
472 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
473 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
474 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
475 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
476 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
58cc9876
YW		 477 UNSPEC_SHRNB ; Used in aarch64-sve2.md.
478 UNSPEC_SHRNT ; Used in aarch64-sve2.md.
479 UNSPEC_RSHRNB ; Used in aarch64-sve2.md.
480 UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
43e9d192
IB		 481 UNSPEC_SSHL ; Used in aarch64-simd.md.
482 UNSPEC_USHL ; Used in aarch64-simd.md.
483 UNSPEC_SRSHL ; Used in aarch64-simd.md.
484 UNSPEC_URSHL ; Used in aarch64-simd.md.
485 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
486 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 487 UNSPEC_SSLI ; Used in aarch64-simd.md.
488 UNSPEC_USLI ; Used in aarch64-simd.md.
489 UNSPEC_SSRI ; Used in aarch64-simd.md.
490 UNSPEC_USRI ; Used in aarch64-simd.md.
491 UNSPEC_SSHLL ; Used in aarch64-simd.md.
492 UNSPEC_USHLL ; Used in aarch64-simd.md.
493 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 494 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 495 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 496 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 497
498 ;; The following permute unspecs are generated directly by
499 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
500 ;; instructions would need a corresponding change there.
cc4d934f
JG		 501 UNSPEC_ZIP1 ; Used in vector permute patterns.
502 UNSPEC_ZIP2 ; Used in vector permute patterns.
503 UNSPEC_UZP1 ; Used in vector permute patterns.
504 UNSPEC_UZP2 ; Used in vector permute patterns.
505 UNSPEC_TRN1 ; Used in vector permute patterns.
506 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 507 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 508 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
509 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
510 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 511
5a7a4e80
TB		 512 UNSPEC_AESE ; Used in aarch64-simd.md.
513 UNSPEC_AESD ; Used in aarch64-simd.md.
514 UNSPEC_AESMC ; Used in aarch64-simd.md.
515 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 516 UNSPEC_SHA1C ; Used in aarch64-simd.md.
517 UNSPEC_SHA1M ; Used in aarch64-simd.md.
518 UNSPEC_SHA1P ; Used in aarch64-simd.md.
519 UNSPEC_SHA1H ; Used in aarch64-simd.md.
520 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
521 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 522 UNSPEC_SHA256H ; Used in aarch64-simd.md.
523 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
524 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
525 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 526 UNSPEC_PMULL ; Used in aarch64-simd.md.
527 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 528 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 529 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 530 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
531 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 532 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
533 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 534 UNSPEC_SDOT ; Used in aarch64-simd.md.
535 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 536 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
537 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
538 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
539 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
540 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
541 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
542 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
543 UNSPEC_SM4E ; Used in aarch64-simd.md.
544 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
545 UNSPEC_SHA512H ; Used in aarch64-simd.md.
546 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
547 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
548 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
549 UNSPEC_FMLAL ; Used in aarch64-simd.md.
550 UNSPEC_FMLSL ; Used in aarch64-simd.md.
551 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
552 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
624d0f07 553 UNSPEC_ADR ; Used in aarch64-sve.md.
43cacb12 554 UNSPEC_SEL ; Used in aarch64-sve.md.
624d0f07
RS		 555 UNSPEC_BRKA ; Used in aarch64-sve.md.
556 UNSPEC_BRKB ; Used in aarch64-sve.md.
557 UNSPEC_BRKN ; Used in aarch64-sve.md.
558 UNSPEC_BRKPA ; Used in aarch64-sve.md.
559 UNSPEC_BRKPB ; Used in aarch64-sve.md.
560 UNSPEC_PFIRST ; Used in aarch64-sve.md.
561 UNSPEC_PNEXT ; Used in aarch64-sve.md.
562 UNSPEC_CNTP ; Used in aarch64-sve.md.
563 UNSPEC_SADDV ; Used in aarch64-sve.md.
564 UNSPEC_UADDV ; Used in aarch64-sve.md.
898f07b0
RS		 565 UNSPEC_ANDV ; Used in aarch64-sve.md.
566 UNSPEC_IORV ; Used in aarch64-sve.md.
567 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 568 UNSPEC_ANDF ; Used in aarch64-sve.md.
569 UNSPEC_IORF ; Used in aarch64-sve.md.
570 UNSPEC_XORF ; Used in aarch64-sve.md.
d7a09c44
RS		 571 UNSPEC_REVB ; Used in aarch64-sve.md.
572 UNSPEC_REVH ; Used in aarch64-sve.md.
573 UNSPEC_REVW ; Used in aarch64-sve.md.
11e9443f
RS		 574 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
575 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
624d0f07
RS		 576 UNSPEC_FMLA ; Used in aarch64-sve.md.
577 UNSPEC_FMLS ; Used in aarch64-sve.md.
578 UNSPEC_FEXPA ; Used in aarch64-sve.md.
579 UNSPEC_FTMAD ; Used in aarch64-sve.md.
580 UNSPEC_FTSMUL ; Used in aarch64-sve.md.
581 UNSPEC_FTSSEL ; Used in aarch64-sve.md.
582 UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md.
583 UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md.
584 UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md.
585 UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md.
586 UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md.
587 UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md.
588 UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md.
589 UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md.
590 UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md.
591 UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md.
d45b20a5 592 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
cb18e86d 593 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
624d0f07
RS		 594 UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md.
595 UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md.
cb18e86d
RS		 596 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
597 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
598 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
624d0f07
RS		 599 UNSPEC_COND_FCMLA ; Used in aarch64-sve.md.
600 UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md.
601 UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md.
602 UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md.
cb18e86d
RS		 603 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
604 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
605 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
4a942af6 606 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
99361551
RS		 607 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
608 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
609 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
cb18e86d 610 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
624d0f07 611 UNSPEC_COND_FMAX ; Used in aarch64-sve.md.
cb18e86d 612 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
624d0f07 613 UNSPEC_COND_FMIN ; Used in aarch64-sve.md.
cb18e86d 614 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
b41d1f6e
RS		 615 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
616 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
cb18e86d 617 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
624d0f07 618 UNSPEC_COND_FMULX ; Used in aarch64-sve.md.
d45b20a5 619 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
b41d1f6e
RS		 620 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
621 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
624d0f07 622 UNSPEC_COND_FRECPX ; Used in aarch64-sve.md.
d45b20a5
RS		 623 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
624 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
625 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
626 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
627 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
628 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
629 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
624d0f07 630 UNSPEC_COND_FSCALE ; Used in aarch64-sve.md.
d45b20a5 631 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
cb18e86d 632 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
99361551
RS		 633 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
634 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
624d0f07 635 UNSPEC_LASTA ; Used in aarch64-sve.md.
43cacb12 636 UNSPEC_LASTB ; Used in aarch64-sve.md.
624d0f07
RS		 637 UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md.
638 UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md.
639 UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md.
640 UNSPEC_LDFF1 ; Used in aarch64-sve.md.
641 UNSPEC_LDNF1 ; Used in aarch64-sve.md.
9d63f43b
TC		 642 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
643 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
644 UNSPEC_FCMLA ; Used in aarch64-simd.md.
645 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
646 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
647 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
58cc9876
YW		 648 UNSPEC_SMULHS ; Used in aarch64-sve2.md.
649 UNSPEC_SMULHRS ; Used in aarch64-sve2.md.
650 UNSPEC_UMULHS ; Used in aarch64-sve2.md.
651 UNSPEC_UMULHRS ; Used in aarch64-sve2.md.
c0c2f013 652 UNSPEC_ASRD ; Used in aarch64-sve.md.
43e9d192
IB		 653])
654
d81cb613
MW		 655;; ------------------------------------------------------------------
656;; Unspec enumerations for Atomics. They are here so that they can be
657;; used in the int_iterators for atomic operations.
658;; ------------------------------------------------------------------
659
660(define_c_enum "unspecv"
661 [
662 UNSPECV_LX ; Represent a load-exclusive.
663 UNSPECV_SX ; Represent a store-exclusive.
664 UNSPECV_LDA ; Represent an atomic load or load-acquire.
665 UNSPECV_STL ; Represent an atomic store or store-release.
666 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
667 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
668 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
669 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
670 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
d81cb613
MW		 671 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
672 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
673 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
674 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
675])
676
43e9d192
IB		 677;; -------------------------------------------------------------------
678;; Mode attributes
679;; -------------------------------------------------------------------
680
681;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
682;; 32-bit version and "%x0" in the 64-bit version.
683(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
684
db46a2e6
JG		 685;; The size of access, in bytes.
686(define_mode_attr ldst_sz [(SI "4") (DI "8")])
687;; Likewise for load/store pair.
688(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
689
0d35c5c2 690;; For inequal width int to float conversion
d7f33f07
JW		 691(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
692(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 693
22be0d08
MC		 694;; For width of fp registers in fcvt instruction
695(define_mode_attr fpw [(DI "s") (SI "d")])
696
2b8568fe
KT		 697(define_mode_attr short_mask [(HI "65535") (QI "255")])
698
051d0e2f
SN		 699;; For constraints used in scalar immediate vector moves
700(define_mode_attr hq [(HI "h") (QI "q")])
701
ef22810a
RH		 702;; For doubling width of an integer mode
703(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
704
22be0d08
MC		 705(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
706
707(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
708
43e9d192
IB		 709;; For scalar usage of vector/FP registers
710(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 711 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 712 (V8QI "") (V16QI "")
713 (V4HI "") (V8HI "")
714 (V2SI "") (V4SI "")
715 (V2DI "") (V2SF "")
daef0a8c
JW		 716 (V4SF "") (V4HF "")
717 (V8HF "") (V2DF "")])
43e9d192
IB		 718
719;; For scalar usage of vector/FP registers, narrowing
720(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
721 (V8QI "") (V16QI "")
722 (V4HI "") (V8HI "")
723 (V2SI "") (V4SI "")
724 (V2DI "") (V2SF "")
725 (V4SF "") (V2DF "")])
726
727;; For scalar usage of vector/FP registers, widening
728(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
729 (V8QI "") (V16QI "")
730 (V4HI "") (V8HI "")
731 (V2SI "") (V4SI "")
732 (V2DI "") (V2SF "")
733 (V4SF "") (V2DF "")])
734
89fdc743
IB		 735;; Register Type Name and Vector Arrangement Specifier for when
736;; we are doing scalar for DI and SIMD for SI (ignoring all but
737;; lane 0).
738(define_mode_attr rtn [(DI "d") (SI "")])
739(define_mode_attr vas [(DI "") (SI ".2s")])
740
7ac29c0f
RS		 741;; Map a vector to the number of units in it, if the size of the mode
742;; is constant.
743(define_mode_attr nunits [(V8QI "8") (V16QI "16")
744 (V4HI "4") (V8HI "8")
745 (V2SI "2") (V4SI "4")
746 (V2DI "2")
747 (V4HF "4") (V8HF "8")
748 (V2SF "2") (V4SF "4")
749 (V1DF "1") (V2DF "2")
750 (DI "1") (DF "1")])
751
b187677b
RS		 752;; Map a mode to the number of bits in it, if the size of the mode
753;; is constant.
754(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
755 (V4HI "64") (V8HI "128")
756 (V2SI "64") (V4SI "128")
757 (V2DI "128")])
758
22be0d08
MC		 759;; Map a floating point or integer mode to the appropriate register name prefix
760(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 761
762;; Give the length suffix letter for a sign- or zero-extension.
763(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
764
765;; Give the number of bits in the mode
766(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
767
768;; Give the ordinal of the MSB in the mode
315fdae8
RE		 769(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
770 (HF "#15") (SF "#31") (DF "#63")])
43e9d192 771
95eb5537
RS		 772;; The number of bits in a vector element, or controlled by a predicate
773;; element.
d7a09c44
RS		 774(define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16")
775 (VNx4BI "32") (VNx2BI "64")
776 (VNx16QI "8") (VNx8HI "16")
777 (VNx4SI "32") (VNx2DI "64")
95eb5537
RS		 778 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
779
43e9d192
IB		 780;; Attribute to describe constants acceptable in logical operations
781(define_mode_attr lconst [(SI "K") (DI "L")])
782
43fd192f
MC		 783;; Attribute to describe constants acceptable in logical and operations
784(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
785
43e9d192
IB		 786;; Map a mode to a specific constraint character.
787(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
788
0603375c
KT		 789;; Map modes to Usg and Usj constraints for SISD right shifts
790(define_mode_attr cmode_simd [(SI "g") (DI "j")])
791
43e9d192
IB		 792(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
793 (V4HI "4h") (V8HI "8h")
794 (V2SI "2s") (V4SI "4s")
795 (DI "1d") (DF "1d")
796 (V2DI "2d") (V2SF "2s")
7c369485
AL		 797 (V4SF "4s") (V2DF "2d")
798 (V4HF "4h") (V8HF "8h")])
43e9d192 799
c7f28cd5
KT		 800(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
801 (V4SI "32") (V2DI "64")])
802
43e9d192
IB		 803(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
804 (V4HI ".4h") (V8HI ".8h")
805 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 806 (V2DI ".2d") (V4HF ".4h")
807 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 808 (V4SF ".4s") (V2DF ".2d")
809 (DI "") (SI "")
810 (HI "") (QI "")
d7f33f07
JW		 811 (TI "") (HF "")
812 (SF "") (DF "")])
43e9d192
IB		 813
814;; Register suffix narrowed modes for VQN.
815(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
816 (V2DI ".2s")
817 (DI "") (SI "")
818 (HI "")])
819
820;; Mode-to-individual element type mapping.
cc68f7c2
RS		 821(define_mode_attr Vetype [(V8QI "b") (V16QI "b")
822 (V4HI "h") (V8HI "h")
823 (V2SI "s") (V4SI "s")
824 (V2DI "d")
825 (V4HF "h") (V8HF "h")
826 (V2SF "s") (V4SF "s")
827 (V2DF "d")
828 (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d")
829 (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
830 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
831 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
832 (VNx4SI "s") (VNx2SI "s")
833 (VNx4SF "s") (VNx2SF "s")
834 (VNx2DI "d")
835 (VNx2DF "d")
836 (HF "h")
837 (SF "s") (DF "d")
838 (QI "b") (HI "h")
839 (SI "s") (DI "d")])
43e9d192 840
9feeafd7
AM		 841;; Like Vetype, but map to types that are a quarter of the element size.
842(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
843
43cacb12 844;; Equivalent of "size" for a vector element.
cc68f7c2
RS		 845(define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
846 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
847 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
848 (VNx4SI "w") (VNx2SI "w")
849 (VNx4SF "w") (VNx2SF "w")
850 (VNx2DI "d")
851 (VNx2DF "d")
9f4cbab8
RS		 852 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
853 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
854 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
855 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
856 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
857 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
858 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 859
cc68f7c2
RS		 860;; The Z register suffix for an SVE mode's element container, i.e. the
861;; Vetype of full SVE modes that have the same number of elements.
862(define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d")
863 (VNx8HI "h") (VNx4HI "s") (VNx2HI "d")
864 (VNx8HF "h") (VNx4HF "s") (VNx2HF "d")
865 (VNx4SI "s") (VNx2SI "d")
866 (VNx4SF "s") (VNx2SF "d")
867 (VNx2DI "d")
868 (VNx2DF "d")])
869
daef0a8c
JW		 870;; Vetype is used everywhere in scheduling type and assembly output,
871;; sometimes they are not the same, for example HF modes on some
872;; instructions. stype is defined to represent scheduling type
873;; more accurately.
874(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
875 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
876 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
877 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
878 (SI "s") (DI "d")])
879
43e9d192
IB		 880;; Mode-to-bitwise operation type mapping.
881(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
882 (V4HI "8b") (V8HI "16b")
883 (V2SI "8b") (V4SI "16b")
7c369485
AL		 884 (V2DI "16b") (V4HF "8b")
885 (V8HF "16b") (V2SF "8b")
46e778c4 886 (V4SF "16b") (V2DF "16b")
fe82d1f2 887 (DI "8b") (DF "8b")
315fdae8 888 (SI "8b") (SF "8b")])
43e9d192
IB		 889
890;; Define element mode for each vector mode.
cc68f7c2
RS		 891(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
892 (V4HI "HI") (V8HI "HI")
893 (V2SI "SI") (V4SI "SI")
894 (DI "DI") (V2DI "DI")
895 (V4HF "HF") (V8HF "HF")
896 (V2SF "SF") (V4SF "SF")
897 (DF "DF") (V2DF "DF")
898 (SI "SI") (HI "HI")
899 (QI "QI")
900 (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI")
901 (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI")
902 (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF")
903 (VNx4SI "SI") (VNx2SI "SI")
904 (VNx4SF "SF") (VNx2SF "SF")
905 (VNx2DI "DI")
906 (VNx2DF "DF")])
43e9d192 907
ff03930a 908;; Define element mode for each vector mode (lower case).
cc68f7c2
RS		 909(define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
910 (V4HI "hi") (V8HI "hi")
911 (V2SI "si") (V4SI "si")
912 (DI "di") (V2DI "di")
913 (V4HF "hf") (V8HF "hf")
914 (V2SF "sf") (V4SF "sf")
915 (V2DF "df") (DF "df")
916 (SI "si") (HI "hi")
917 (QI "qi")
918 (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi")
919 (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi")
920 (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf")
921 (VNx4SI "si") (VNx2SI "si")
922 (VNx4SF "sf") (VNx2SF "sf")
923 (VNx2DI "di")
924 (VNx2DF "df")])
ff03930a 925
43cacb12
RS		 926;; Element mode with floating-point values replaced by like-sized integers.
927(define_mode_attr VEL_INT [(VNx16QI "QI")
928 (VNx8HI "HI") (VNx8HF "HI")
929 (VNx4SI "SI") (VNx4SF "SI")
930 (VNx2DI "DI") (VNx2DF "DI")])
931
932;; Gives the mode of the 128-bit lowpart of an SVE vector.
933(define_mode_attr V128 [(VNx16QI "V16QI")
934 (VNx8HI "V8HI") (VNx8HF "V8HF")
935 (VNx4SI "V4SI") (VNx4SF "V4SF")
936 (VNx2DI "V2DI") (VNx2DF "V2DF")])
937
938;; ...and again in lower case.
939(define_mode_attr v128 [(VNx16QI "v16qi")
940 (VNx8HI "v8hi") (VNx8HF "v8hf")
941 (VNx4SI "v4si") (VNx4SF "v4sf")
942 (VNx2DI "v2di") (VNx2DF "v2df")])
943
278821f2
KT		 944;; 64-bit container modes the inner or scalar source mode.
945(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
946 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 947 (V2SI "V2SI") (V4SI "V2SI")
948 (DI "DI") (V2DI "DI")
949 (V2SF "V2SF") (V4SF "V2SF")
950 (V2DF "DF")])
951
278821f2 952;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 953(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
954 (V4HI "V8HI") (V8HI "V8HI")
955 (V2SI "V4SI") (V4SI "V4SI")
956 (DI "V2DI") (V2DI "V2DI")
71a11456 957 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 958 (V2SF "V2SF") (V4SF "V4SF")
959 (V2DF "V2DF") (SI "V4SI")
960 (HI "V8HI") (QI "V16QI")])
961
43e9d192
IB		 962;; Half modes of all vector modes.
963(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
964 (V4HI "V2HI") (V8HI "V4HI")
965 (V2SI "SI") (V4SI "V2SI")
966 (V2DI "DI") (V2SF "SF")
71a11456
AL		 967 (V4SF "V2SF") (V4HF "V2HF")
968 (V8HF "V4HF") (V2DF "DF")])
43e9d192 969
b1b49824
MC		 970;; Half modes of all vector modes, in lower-case.
971(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
972 (V4HI "v2hi") (V8HI "v4hi")
41dab855 973 (V8HF "v4hf")
b1b49824
MC		 974 (V2SI "si") (V4SI "v2si")
975 (V2DI "di") (V2SF "sf")
976 (V4SF "v2sf") (V2DF "df")])
977
43e9d192
IB		 978;; Double modes of vector modes.
979(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 980 (V4HF "V8HF")
43e9d192
IB		 981 (V2SI "V4SI") (V2SF "V4SF")
982 (SI "V2SI") (DI "V2DI")
983 (DF "V2DF")])
984
922f9c25
AL		 985;; Register suffix for double-length mode.
986(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
987
43e9d192
IB		 988;; Double modes of vector modes (lower case).
989(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 990 (V4HF "v8hf")
43e9d192 991 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 992 (SI "v2si") (DI "v2di")
993 (DF "v2df")])
43e9d192 994
b1b49824
MC		 995;; Modes with double-width elements.
996(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
997 (V4HI "V2SI") (V8HI "V4SI")
998 (V2SI "DI") (V4SI "V2DI")])
999
43e9d192
IB		 1000;; Narrowed modes for VDN.
1001(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
1002 (DI "V2SI")])
1003
1004;; Narrowed double-modes for VQN (Used for XTN).
1005(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
1006 (V2DI "V2SI")
1007 (DI "SI") (SI "HI")
1008 (HI "QI")])
9c437a10
RS		 1009(define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi")
1010 (V2DI "v2si")])
43e9d192
IB		 1011
1012;; Narrowed quad-modes for VQN (Used for XTN2).
1013(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
1014 (V2DI "V4SI")])
1015
1016;; Register suffix narrowed modes for VQN.
1017(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
1018 (V2DI "2s")])
1019
1020;; Register suffix narrowed modes for VQN.
1021(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
1022 (V2DI "4s")])
1023
1024;; Widened modes of vector modes.
43cacb12
RS		 1025(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
1026 (V2SI "V2DI") (V16QI "V8HI")
1027 (V8HI "V4SI") (V4SI "V2DI")
1028 (HI "SI") (SI "DI")
1029 (V8HF "V4SF") (V4SF "V2DF")
1030 (V4HF "V4SF") (V2SF "V2DF")
1031 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
1032 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
1033 (VNx4SI "VNx2DI")
1034 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
1035 (VNx4BI "VNx2BI")])
1036
1037;; Predicate mode associated with VWIDE.
1038(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 1039
03873eb9 1040;; Widened modes of vector modes, lowercase
43cacb12
RS		 1041(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
1042 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
1043 (VNx4SI "vnx2di")
1044 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
1045 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
1046 (VNx4BI "vnx2bi")])
03873eb9
AL		 1047
1048;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 1049(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
1050 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 1051 (V8HI "4s") (V4SI "2d")
1052 (V8HF "4s") (V4SF "2d")])
43e9d192 1053
43cacb12
RS		 1054;; SVE vector after widening
1055(define_mode_attr Vewtype [(VNx16QI "h")
1056 (VNx8HI "s") (VNx8HF "s")
1057 (VNx4SI "d") (VNx4SF "d")])
1058
43e9d192
IB		 1059;; Widened mode register suffixes for VDW/VQW.
1060(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
1061 (V2SI ".2d") (V16QI ".8h")
1062 (V8HI ".4s") (V4SI ".2d")
922f9c25 1063 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 1064 (SI "") (HI "")])
1065
03873eb9 1066;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 1067(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 1068 (V4SI "2s") (V8HF "4h")
1069 (V4SF "2s")])
43e9d192
IB		 1070
1071;; Define corresponding core/FP element mode for each vector mode.
cc68f7c2
RS		 1072(define_mode_attr vw [(V8QI "w") (V16QI "w")
1073 (V4HI "w") (V8HI "w")
1074 (V2SI "w") (V4SI "w")
1075 (DI "x") (V2DI "x")
1076 (V2SF "s") (V4SF "s")
1077 (V2DF "d")])
43e9d192 1078
66adb8eb
JG		 1079;; Corresponding core element mode for each vector mode. This is a
1080;; variation on <vw> mapping FP modes to GP regs.
cc68f7c2
RS		 1081(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
1082 (V4HI "w") (V8HI "w")
1083 (V2SI "w") (V4SI "w")
1084 (DI "x") (V2DI "x")
1085 (V4HF "w") (V8HF "w")
1086 (V2SF "w") (V4SF "w")
1087 (V2DF "x")
1088 (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
1089 (VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
1090 (VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
1091 (VNx4SI "w") (VNx2SI "w")
1092 (VNx4SF "w") (VNx2SF "w")
1093 (VNx2DI "x")
1094 (VNx2DF "x")])
66adb8eb 1095
30f8bf3d
RS		 1096;; Like vwcore, but for the container mode rather than the element mode.
1097(define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x")
1098 (VNx8HI "w") (VNx4HI "w") (VNx2HI "x")
1099 (VNx4SI "w") (VNx2SI "x")
1100 (VNx2DI "x")])
1101
43e9d192
IB		 1102;; Double vector types for ALLX.
1103(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
1104
5f565314
RS		 1105;; Mode with floating-point values replaced by like-sized integers.
1106(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
1107 (V4HI "V4HI") (V8HI "V8HI")
1108 (V2SI "V2SI") (V4SI "V4SI")
1109 (DI "DI") (V2DI "V2DI")
1110 (V4HF "V4HI") (V8HF "V8HI")
1111 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 1112 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 1113 (SF "SI") (SI "SI")
1114 (HF "HI")
43cacb12
RS		 1115 (VNx16QI "VNx16QI")
1116 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
1117 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
1118 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
1119])
5f565314
RS		 1120
1121;; Lower case mode with floating-point values replaced by like-sized integers.
1122(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
1123 (V4HI "v4hi") (V8HI "v8hi")
1124 (V2SI "v2si") (V4SI "v4si")
1125 (DI "di") (V2DI "v2di")
1126 (V4HF "v4hi") (V8HF "v8hi")
1127 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 1128 (DF "di") (V2DF "v2di")
1129 (SF "si")
1130 (VNx16QI "vnx16qi")
1131 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
1132 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
1133 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
1134])
1135
1136;; Floating-point equivalent of selected modes.
a70965b1
RS		 1137(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
1138 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
43cacb12 1139 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
a70965b1
RS		 1140(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
1141 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
43cacb12 1142 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 1143
f8186eea
RS		 1144;; Maps full and partial vector modes of any element type to a full-vector
1145;; integer mode with the same number of units.
1146(define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI")
1147 (VNx4QI "VNx4SI") (VNx2QI "VNx2DI")
1148 (VNx8HI "VNx8HI") (VNx4HI "VNx4SI")
1149 (VNx2HI "VNx2DI")
1150 (VNx4SI "VNx4SI") (VNx2SI "VNx2DI")
1151 (VNx2DI "VNx2DI")
1152 (VNx8HF "VNx8HI") (VNx4HF "VNx4SI")
1153 (VNx2HF "VNx2DI")
3261d8ba 1154 (VNx4SF "VNx4SI") (VNx2SF "VNx2DI")
f8186eea
RS		 1155 (VNx2DF "VNx2DI")])
1156
1157;; Lower-case version of V_INT_CONTAINER.
1158(define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi")
1159 (VNx4QI "vnx4si") (VNx2QI "vnx2di")
1160 (VNx8HI "vnx8hi") (VNx4HI "vnx4si")
1161 (VNx2HI "vnx2di")
1162 (VNx4SI "vnx4si") (VNx2SI "vnx2di")
1163 (VNx2DI "vnx2di")
1164 (VNx8HF "vnx8hi") (VNx4HF "vnx4si")
1165 (VNx2HF "vnx2di")
1166 (VNx4SF "vnx4si") (VNx2SF "vnx2di")
1167 (VNx2DF "vnx2di")])
1168
6c553b76
BC		 1169;; Mode for vector conditional operations where the comparison has
1170;; different type from the lhs.
1171(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
1172 (V2DI "V2DF") (V2SF "V2SI")
1173 (V4SF "V4SI") (V2DF "V2DI")])
1174
1175(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
1176 (V2DI "v2df") (V2SF "v2si")
1177 (V4SF "v4si") (V2DF "v2di")])
1178
cb23a30c
JG		 1179;; Lower case element modes (as used in shift immediate patterns).
1180(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
1181 (V4HI "hi") (V8HI "hi")
1182 (V2SI "si") (V4SI "si")
1183 (DI "di") (V2DI "di")
1184 (QI "qi") (HI "hi")
1185 (SI "si")])
1186
43e9d192
IB		 1187;; Vm for lane instructions is restricted to FP_LO_REGS.
1188(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
1189 (V2SI "w") (V4SI "w") (SI "w")])
1190
1191(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
1192
97755701
AL		 1193;; This is both the number of Q-Registers needed to hold the corresponding
1194;; opaque large integer mode, and the number of elements touched by the
1195;; ld..._lane and st..._lane operations.
43e9d192
IB		 1196(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
1197
0462169c
SN		 1198;; Mode for atomic operation suffixes
1199(define_mode_attr atomic_sfx
1200 [(QI "b") (HI "h") (SI "") (DI "")])
1201
3f598afe 1202(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 1203 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 1204 (SF "si") (DF "di") (SI "sf") (DI "df")
1205 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 1206 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 1207(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 1208 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 1209 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1210 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 1211 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 1212
0d35c5c2
VP		 1213
1214;; for the inequal width integer to fp conversions
d7f33f07
JW		 1215(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1216(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 1217
91bd4114
JG		 1218(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1219 (V4HI "V8HI") (V8HI "V4HI")
1220 (V2SI "V4SI") (V4SI "V2SI")
1221 (DI "V2DI") (V2DI "DI")
1222 (V2SF "V4SF") (V4SF "V2SF")
862abc04 1223 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 1224 (DF "V2DF") (V2DF "DF")])
1225
1226(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1227 (V4HI "to_128") (V8HI "to_64")
1228 (V2SI "to_128") (V4SI "to_64")
1229 (DI "to_128") (V2DI "to_64")
862abc04 1230 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 1231 (V2SF "to_128") (V4SF "to_64")
1232 (DF "to_128") (V2DF "to_64")])
1233
779aea46 1234;; For certain vector-by-element multiplication instructions we must
6d06971d 1235;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 1236;; the 'x' constraint. All other modes may use the 'w' constraint.
1237(define_mode_attr h_con [(V2SI "w") (V4SI "w")
1238 (V4HI "x") (V8HI "x")
6d06971d 1239 (V4HF "x") (V8HF "x")
779aea46
JG		 1240 (V2SF "w") (V4SF "w")
1241 (V2DF "w") (DF "w")])
1242
1243;; Defined to 'f' for types whose element type is a float type.
1244(define_mode_attr f [(V8QI "") (V16QI "")
1245 (V4HI "") (V8HI "")
1246 (V2SI "") (V4SI "")
1247 (DI "") (V2DI "")
ab2e8f01 1248 (V4HF "f") (V8HF "f")
779aea46
JG		 1249 (V2SF "f") (V4SF "f")
1250 (V2DF "f") (DF "f")])
1251
0f686aa9
JG		 1252;; Defined to '_fp' for types whose element type is a float type.
1253(define_mode_attr fp [(V8QI "") (V16QI "")
1254 (V4HI "") (V8HI "")
1255 (V2SI "") (V4SI "")
1256 (DI "") (V2DI "")
ab2e8f01 1257 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1258 (V2SF "_fp") (V4SF "_fp")
1259 (V2DF "_fp") (DF "_fp")
1260 (SF "_fp")])
1261
a9e66678
JG		 1262;; Defined to '_q' for 128-bit types.
1263(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1264 (V4HI "") (V8HI "_q")
1265 (V2SI "") (V4SI "_q")
1266 (DI "") (V2DI "_q")
71a11456 1267 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1268 (V2SF "") (V4SF "_q")
1269 (V2DF "_q")
d7f33f07 1270 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1271
92835317
TB		 1272(define_mode_attr vp [(V8QI "v") (V16QI "v")
1273 (V4HI "v") (V8HI "v")
1274 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1275 (V2DI "p") (V2DF "p")
1276 (V2SF "p") (V4SF "v")
1277 (V4HF "v") (V8HF "v")])
92835317 1278
9feeafd7
AM		 1279(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1280 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1281(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1282 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
5e32e83b 1283
7a08d813
TC		 1284
1285;; Register suffix for DOTPROD input types from the return type.
1286(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1287
cd78b3dd 1288;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1289(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1290
1b1e81f8
JW		 1291;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1292;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1293(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1294
27086ea3
MC		 1295;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1296(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1297
1298(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1299
1300(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1301
1302(define_code_attr f16mac [(plus "a") (minus "s")])
1303
8544ed6e
KT		 1304;; Map smax to smin and umax to umin.
1305(define_code_attr max_opp [(smax "smin") (umax "umin")])
1306
a9fad8fe
AM		 1307;; Same as above, but louder.
1308(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1309
9f4cbab8
RS		 1310;; The number of subvectors in an SVE_STRUCT.
1311(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1312 (VNx8SI "2") (VNx4DI "2")
1313 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1314 (VNx48QI "3") (VNx24HI "3")
1315 (VNx12SI "3") (VNx6DI "3")
1316 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1317 (VNx64QI "4") (VNx32HI "4")
1318 (VNx16SI "4") (VNx8DI "4")
1319 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1320
1321;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1322;; equal to vector_count * 4.
1323(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1324 (VNx8SI "8") (VNx4DI "8")
1325 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1326 (VNx48QI "12") (VNx24HI "12")
1327 (VNx12SI "12") (VNx6DI "12")
1328 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1329 (VNx64QI "16") (VNx32HI "16")
1330 (VNx16SI "16") (VNx8DI "16")
1331 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1332
1333;; The type of a subvector in an SVE_STRUCT.
1334(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1335 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1336 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1337 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1338 (VNx48QI "VNx16QI")
1339 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1340 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1341 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1342 (VNx64QI "VNx16QI")
1343 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1344 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1345 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1346
1347;; ...and again in lower case.
1348(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1349 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1350 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1351 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1352 (VNx48QI "vnx16qi")
1353 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1354 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1355 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1356 (VNx64QI "vnx16qi")
1357 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1358 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1359 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1360
1361;; The predicate mode associated with an SVE data mode. For structure modes
1362;; this is equivalent to the <VPRED> of the subvector mode.
cc68f7c2
RS		 1363(define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI")
1364 (VNx4QI "VNx4BI") (VNx2QI "VNx2BI")
1365 (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI")
1366 (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI")
1367 (VNx4SI "VNx4BI") (VNx2SI "VNx2BI")
1368 (VNx4SF "VNx4BI") (VNx2SF "VNx2BI")
1369 (VNx2DI "VNx2BI")
1370 (VNx2DF "VNx2BI")
9f4cbab8
RS		 1371 (VNx32QI "VNx16BI")
1372 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1373 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1374 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1375 (VNx48QI "VNx16BI")
1376 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1377 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1378 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1379 (VNx64QI "VNx16BI")
1380 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1381 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1382 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1383
1384;; ...and again in lower case.
cc68f7c2
RS		 1385(define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi")
1386 (VNx4QI "vnx4bi") (VNx2QI "vnx2bi")
1387 (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi")
1388 (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi")
1389 (VNx4SI "vnx4bi") (VNx2SI "vnx2bi")
1390 (VNx4SF "vnx4bi") (VNx2SF "vnx2bi")
1391 (VNx2DI "vnx2bi")
1392 (VNx2DF "vnx2bi")
9f4cbab8
RS		 1393 (VNx32QI "vnx16bi")
1394 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1395 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1396 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1397 (VNx48QI "vnx16bi")
1398 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1399 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1400 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1401 (VNx64QI "vnx16bi")
1402 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1403 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1404 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1405
9d63f43b
TC		 1406;; On AArch64 the By element instruction doesn't have a 2S variant.
1407;; However because the instruction always selects a pair of values
1408;; The normal 3SAME instruction can be used here instead.
1409(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1410 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1411 ])
1412
34467289
RS		 1413;; The number of bytes controlled by a predicate
1414(define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
1415 (VNx4BI "4") (VNx2BI "8")])
1416
624d0f07
RS		 1417;; Two-nybble mask for partial vector modes: nunits, byte size.
1418(define_mode_attr self_mask [(VNx8QI "0x81")
1419 (VNx4QI "0x41")
1420 (VNx2QI "0x21")
1421 (VNx4HI "0x42")
1422 (VNx2HI "0x22")
1423 (VNx2SI "0x24")])
1424
e58703e2
RS		 1425;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above.
1426(define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41")
1427 (VNx2HI "0x21")
1428 (VNx4SI "0x43") (VNx2SI "0x23")
624d0f07
RS		 1429 (VNx2DI "0x27")])
1430
1431;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index.
1432(define_mode_attr sve_lane_con [(VNx4SI "y") (VNx2DI "x")
1433 (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")])
1434
1435;; The constraint to use for an SVE FCMLA lane index.
1436(define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")])
1437
43e9d192
IB		 1438;; -------------------------------------------------------------------
1439;; Code Iterators
1440;; -------------------------------------------------------------------
1441
1442;; This code iterator allows the various shifts supported on the core
1443(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1444
1445;; This code iterator allows the shifts supported in arithmetic instructions
1446(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1447
462e6f9a
ST		 1448(define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1449
43e9d192
IB		 1450;; Code iterator for logical operations
1451(define_code_iterator LOGICAL [and ior xor])
1452
43cacb12
RS		 1453;; LOGICAL without AND.
1454(define_code_iterator LOGICAL_OR [ior xor])
1455
84be6032
AL		 1456;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1457(define_code_iterator NLOGICAL [and ior])
1458
3204ac98
KT		 1459;; Code iterator for unary negate and bitwise complement.
1460(define_code_iterator NEG_NOT [neg not])
1461
43e9d192
IB		 1462;; Code iterator for sign/zero extension
1463(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
87a80d27 1464(define_code_iterator ANY_EXTEND2 [sign_extend zero_extend])
43e9d192
IB		 1465
1466;; All division operations (signed/unsigned)
1467(define_code_iterator ANY_DIV [div udiv])
1468
1469;; Code iterator for sign/zero extraction
1470(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1471
1472;; Code iterator for equality comparisons
1473(define_code_iterator EQL [eq ne])
1474
1475;; Code iterator for less-than and greater/equal-to
1476(define_code_iterator LTGE [lt ge])
1477
1478;; Iterator for __sync_<op> operations that where the operation can be
1479;; represented directly RTL. This is all of the sync operations bar
1480;; nand.
0462169c 1481(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1482
1483;; Iterator for integer conversions
1484(define_code_iterator FIXUORS [fix unsigned_fix])
1485
1709ff9b
JG		 1486;; Iterator for float conversions
1487(define_code_iterator FLOATUORS [float unsigned_float])
1488
43e9d192
IB		 1489;; Code iterator for variants of vector max and min.
1490(define_code_iterator MAXMIN [smax smin umax umin])
1491
998eaf97
JG		 1492(define_code_iterator FMAXMIN [smax smin])
1493
8544ed6e
KT		 1494;; Signed and unsigned max operations.
1495(define_code_iterator USMAX [smax umax])
1496
dd550c99 1497;; Code iterator for plus and minus.
43e9d192
IB		 1498(define_code_iterator ADDSUB [plus minus])
1499
1500;; Code iterator for variants of vector saturating binary ops.
1501(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1502
1503;; Code iterator for variants of vector saturating unary ops.
1504(define_code_iterator UNQOPS [ss_neg ss_abs])
1505
1506;; Code iterator for signed variants of vector saturating binary ops.
1507(define_code_iterator SBINQOPS [ss_plus ss_minus])
1508
624d0f07
RS		 1509;; Code iterator for unsigned variants of vector saturating binary ops.
1510(define_code_iterator UBINQOPS [us_plus us_minus])
1511
1512;; Modular and saturating addition.
1513(define_code_iterator ANY_PLUS [plus ss_plus us_plus])
1514
1515;; Saturating addition.
1516(define_code_iterator SAT_PLUS [ss_plus us_plus])
1517
1518;; Modular and saturating subtraction.
1519(define_code_iterator ANY_MINUS [minus ss_minus us_minus])
1520
1521;; Saturating subtraction.
1522(define_code_iterator SAT_MINUS [ss_minus us_minus])
1523
889b9412
JG		 1524;; Comparison operators for <F>CM.
1525(define_code_iterator COMPARISONS [lt le eq ge gt])
1526
1527;; Unsigned comparison operators.
1528(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1529
75dd5ace
JG		 1530;; Unsigned comparison operators.
1531(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1532
43cacb12 1533;; SVE integer unary operations.
bca5a997 1534(define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount])
43cacb12 1535
a08acce8 1536;; SVE integer binary operations.
6c4fd4a9 1537(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
20103c0e 1538 ashift ashiftrt lshiftrt
9d4ac06e
RS		 1539 and ior xor])
1540
a08acce8 1541;; SVE integer binary division operations.
c38f7319
RS		 1542(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1543
f8c22a8b
RS		 1544;; SVE integer binary operations that have an immediate form.
1545(define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
1546
740c1ed7
RS		 1547;; SVE floating-point operations with an unpredicated all-register form.
1548(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1549
f22d7973
RS		 1550;; SVE integer comparisons.
1551(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1552
43e9d192
IB		 1553;; -------------------------------------------------------------------
1554;; Code Attributes
1555;; -------------------------------------------------------------------
1556;; Map rtl objects to optab names
1557(define_code_attr optab [(ashift "ashl")
1558 (ashiftrt "ashr")
1559 (lshiftrt "lshr")
1560 (rotatert "rotr")
1561 (sign_extend "extend")
1562 (zero_extend "zero_extend")
1563 (sign_extract "extv")
1564 (zero_extract "extzv")
384be29f
JG		 1565 (fix "fix")
1566 (unsigned_fix "fixuns")
1709ff9b
JG		 1567 (float "float")
1568 (unsigned_float "floatuns")
bca5a997
RS		 1569 (clrsb "clrsb")
1570 (clz "clz")
43cacb12 1571 (popcount "popcount")
43e9d192
IB		 1572 (and "and")
1573 (ior "ior")
1574 (xor "xor")
1575 (not "one_cmpl")
1576 (neg "neg")
1577 (plus "add")
1578 (minus "sub")
6c4fd4a9 1579 (mult "mul")
c38f7319
RS		 1580 (div "div")
1581 (udiv "udiv")
43e9d192
IB		 1582 (ss_plus "qadd")
1583 (us_plus "qadd")
1584 (ss_minus "qsub")
1585 (us_minus "qsub")
1586 (ss_neg "qneg")
1587 (ss_abs "qabs")
43cacb12
RS		 1588 (smin "smin")
1589 (smax "smax")
1590 (umin "umin")
1591 (umax "umax")
43e9d192
IB		 1592 (eq "eq")
1593 (ne "ne")
1594 (lt "lt")
889b9412
JG		 1595 (ge "ge")
1596 (le "le")
1597 (gt "gt")
1598 (ltu "ltu")
1599 (leu "leu")
1600 (geu "geu")
43cacb12 1601 (gtu "gtu")
d45b20a5 1602 (abs "abs")])
889b9412
JG		 1603
1604;; For comparison operators we use the FCM* and CM* instructions.
1605;; As there are no CMLE or CMLT instructions which act on 3 vector
1606;; operands, we must use CMGE or CMGT and swap the order of the
1607;; source operands.
1608
1609(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1610 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1611(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1612 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1613(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1614 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1615
1616(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1617 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1618 (gtu "GTU")])
43e9d192 1619
f22d7973
RS		 1620;; The AArch64 condition associated with an rtl comparison code.
1621(define_code_attr cmp_op [(lt "lt")
1622 (le "le")
1623 (eq "eq")
1624 (ne "ne")
1625 (ge "ge")
1626 (gt "gt")
1627 (ltu "lo")
1628 (leu "ls")
1629 (geu "hs")
1630 (gtu "hi")])
1631
384be29f
JG		 1632(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1633 (unsigned_fix "fixuns_trunc")])
1634
43e9d192
IB		 1635;; Optab prefix for sign/zero-extending operations
1636(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1637 (div "") (udiv "u")
1638 (fix "") (unsigned_fix "u")
1709ff9b 1639 (float "s") (unsigned_float "u")
43e9d192
IB		 1640 (ss_plus "s") (us_plus "u")
1641 (ss_minus "s") (us_minus "u")])
1642
1643;; Similar for the instruction mnemonics
1644(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1645 (lshiftrt "lsr") (rotatert "ror")])
1646
462e6f9a
ST		 1647;; Op prefix for shift right and accumulate.
1648(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1649
43e9d192
IB		 1650;; Map shift operators onto underlying bit-field instructions
1651(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1652 (lshiftrt "ubfx") (rotatert "extr")])
1653
1654;; Logical operator instruction mnemonics
1655(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1656
3204ac98
KT		 1657;; Operation names for negate and bitwise complement.
1658(define_code_attr neg_not_op [(neg "neg") (not "not")])
1659
43cacb12 1660;; Similar, but when the second operand is inverted.
43e9d192
IB		 1661(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1662
43cacb12
RS		 1663;; Similar, but when both operands are inverted.
1664(define_code_attr logical_nn [(and "nor") (ior "nand")])
1665
43e9d192
IB		 1666;; Sign- or zero-extending data-op
1667(define_code_attr su [(sign_extend "s") (zero_extend "u")
1668 (sign_extract "s") (zero_extract "u")
1669 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1670 (div "s") (udiv "u")
1671 (smax "s") (umax "u")
1672 (smin "s") (umin "u")])
43e9d192 1673
624d0f07
RS		 1674;; "s" for signed ops, empty for unsigned ones.
1675(define_code_attr s [(sign_extend "s") (zero_extend "")])
1676
1677;; Map signed/unsigned ops to the corresponding extension.
1678(define_code_attr paired_extend [(ss_plus "sign_extend")
1679 (us_plus "zero_extend")
1680 (ss_minus "sign_extend")
1681 (us_minus "zero_extend")])
1682
43cacb12
RS		 1683;; Whether a shift is left or right.
1684(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1685
096e8448
JW		 1686;; Emit conditional branch instructions.
1687(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1688
43e9d192
IB		 1689;; Emit cbz/cbnz depending on comparison type.
1690(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1691
973d2e01
TP		 1692;; Emit inverted cbz/cbnz depending on comparison type.
1693(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1694
43e9d192
IB		 1695;; Emit tbz/tbnz depending on comparison type.
1696(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1697
973d2e01
TP		 1698;; Emit inverted tbz/tbnz depending on comparison type.
1699(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1700
43e9d192 1701;; Max/min attributes.
998eaf97
JG		 1702(define_code_attr maxmin [(smax "max")
1703 (smin "min")
1704 (umax "max")
1705 (umin "min")])
43e9d192
IB		 1706
1707;; MLA/MLS attributes.
1708(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1709
0462169c
SN		 1710;; Atomic operations
1711(define_code_attr atomic_optab
1712 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1713
1714(define_code_attr atomic_op_operand
1715 [(ior "aarch64_logical_operand")
1716 (xor "aarch64_logical_operand")
1717 (and "aarch64_logical_operand")
1718 (plus "aarch64_plus_operand")
1719 (minus "aarch64_plus_operand")])
43e9d192 1720
356c32e2
MW		 1721;; Constants acceptable for atomic operations.
1722;; This definition must appear in this file before the iterators it refers to.
1723(define_code_attr const_atomic
1724 [(plus "IJ") (minus "IJ")
1725 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1726 (and "<lconst_atomic>")])
1727
1728;; Attribute to describe constants acceptable in atomic logical operations
1729(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1730
43cacb12
RS		 1731;; The integer SVE instruction that implements an rtx code.
1732(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1733 (minus "sub")
6c4fd4a9 1734 (mult "mul")
c38f7319
RS		 1735 (div "sdiv")
1736 (udiv "udiv")
69c5fdcf 1737 (abs "abs")
43cacb12
RS		 1738 (neg "neg")
1739 (smin "smin")
1740 (smax "smax")
1741 (umin "umin")
1742 (umax "umax")
20103c0e
RS		 1743 (ashift "lsl")
1744 (ashiftrt "asr")
1745 (lshiftrt "lsr")
43cacb12
RS		 1746 (and "and")
1747 (ior "orr")
1748 (xor "eor")
1749 (not "not")
bca5a997
RS		 1750 (clrsb "cls")
1751 (clz "clz")
43cacb12
RS		 1752 (popcount "cnt")])
1753
a08acce8 1754(define_code_attr sve_int_op_rev [(plus "add")
20103c0e
RS		 1755 (minus "subr")
1756 (mult "mul")
1757 (div "sdivr")
1758 (udiv "udivr")
1759 (smin "smin")
1760 (smax "smax")
1761 (umin "umin")
1762 (umax "umax")
1763 (ashift "lslr")
1764 (ashiftrt "asrr")
1765 (lshiftrt "lsrr")
1766 (and "and")
1767 (ior "orr")
1768 (xor "eor")])
a08acce8 1769
43cacb12
RS		 1770;; The floating-point SVE instruction that implements an rtx code.
1771(define_code_attr sve_fp_op [(plus "fadd")
740c1ed7 1772 (minus "fsub")
d45b20a5 1773 (mult "fmul")])
43cacb12 1774
f22d7973 1775;; The SVE immediate constraint to use for an rtl code.
f8c22a8b
RS		 1776(define_code_attr sve_imm_con [(mult "vsm")
1777 (smax "vsm")
1778 (smin "vsm")
1779 (umax "vsb")
1780 (umin "vsb")
1781 (eq "vsc")
f22d7973
RS		 1782 (ne "vsc")
1783 (lt "vsc")
1784 (ge "vsc")
1785 (le "vsc")
1786 (gt "vsc")
1787 (ltu "vsd")
1788 (leu "vsd")
1789 (geu "vsd")
1790 (gtu "vsd")])
1791
f8c22a8b
RS		 1792;; The prefix letter to use when printing an immediate operand.
1793(define_code_attr sve_imm_prefix [(mult "")
1794 (smax "")
1795 (smin "")
1796 (umax "D")
1797 (umin "D")])
1798
d113ece6
RS		 1799;; The predicate to use for the second input operand in a cond_<optab><mode>
1800;; pattern.
1801(define_code_attr sve_pred_int_rhs2_operand
1802 [(plus "register_operand")
1803 (minus "register_operand")
1804 (mult "register_operand")
1805 (smax "register_operand")
1806 (umax "register_operand")
1807 (smin "register_operand")
1808 (umin "register_operand")
20103c0e
RS		 1809 (ashift "aarch64_sve_lshift_operand")
1810 (ashiftrt "aarch64_sve_rshift_operand")
1811 (lshiftrt "aarch64_sve_rshift_operand")
d113ece6
RS		 1812 (and "aarch64_sve_pred_and_operand")
1813 (ior "register_operand")
1814 (xor "register_operand")])
1815
624d0f07
RS		 1816(define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
1817 (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")])
1818
43e9d192
IB		 1819;; -------------------------------------------------------------------
1820;; Int Iterators.
1821;; -------------------------------------------------------------------
75add2d0
KT		 1822
1823;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1824(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1825
1826;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1827(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1828
1829;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1830(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1831
43e9d192
IB		 1832(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1833 UNSPEC_SMAXV UNSPEC_SMINV])
1834
998eaf97
JG		 1835(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1836 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1837
624d0f07
RS		 1838(define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
1839
43cacb12
RS		 1840(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1841
43e9d192
IB		 1842(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1843 UNSPEC_SRHADD UNSPEC_URHADD
1844 UNSPEC_SHSUB UNSPEC_UHSUB
1845 UNSPEC_SRHSUB UNSPEC_URHSUB])
1846
42addb5a
RS		 1847(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1848
1849(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1850
58cc9876
YW		 1851(define_int_iterator MULLBT [UNSPEC_SMULLB UNSPEC_UMULLB
1852 UNSPEC_SMULLT UNSPEC_UMULLT])
1853
1854(define_int_iterator SHRNB [UNSPEC_SHRNB UNSPEC_RSHRNB])
1855
1856(define_int_iterator SHRNT [UNSPEC_SHRNT UNSPEC_RSHRNT])
1857
2d57b12e
YW		 1858(define_int_iterator BSL_DUP [1 2])
1859
7a08d813 1860(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1861
1862(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1863 UNSPEC_SUBHN UNSPEC_RSUBHN])
1864
1865(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1866 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1867
1efafef3
TC		 1868(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1869 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1870
8fc16d72
ST		 1871(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
1872 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
db58fd89 1873
8fc16d72
ST		 1874(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
1875 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
db58fd89 1876
43e9d192
IB		 1877(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1878
58cc9876
YW		 1879(define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS
1880 UNSPEC_SMULHRS UNSPEC_UMULHRS])
1881
43e9d192
IB		 1882(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1883
1884(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1885
1886(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1887 UNSPEC_SRSHL UNSPEC_URSHL])
1888
1889(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1890
1891(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1892 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1893
1894(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1895 UNSPEC_SRSRA UNSPEC_URSRA])
1896
1897(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1898 UNSPEC_SSRI UNSPEC_USRI])
1899
1900
1901(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1902
1903(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1904
1905(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1906 UNSPEC_SQSHRN UNSPEC_UQSHRN
1907 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1908
57b26d65
MW		 1909(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1910
cc4d934f
JG		 1911(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1912 UNSPEC_TRN1 UNSPEC_TRN2
1913 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1914
43cacb12
RS		 1915(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1916 UNSPEC_UZP1 UNSPEC_UZP2])
1917
923fcec3
AL		 1918(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1919
42fc9a7f 1920(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1921 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1922 UNSPEC_FRINTA])
42fc9a7f
JG		 1923
1924(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1925 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1926
3f598afe
JW		 1927(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1928(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1929
5d357f26
KT		 1930(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1931 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1932 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1933
5a7a4e80
TB		 1934(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1935(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1936
30442682
TB		 1937(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1938
b9cb0a44
TB		 1939(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1940
27086ea3
MC		 1941(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1942
1943(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1944 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1945
1946(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1947
1948;; Iterators for fp16 operations
1949
1950(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1951
1952(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1953
43cacb12
RS		 1954(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1955 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1956
1957(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1958
11e9443f
RS		 1959(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1960
624d0f07
RS		 1961(define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB])
1962
1963(define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB])
1964
1965(define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB
1966 UNSPEC_REVH UNSPEC_REVW])
1967
1968(define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE])
1969
1970(define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA])
1971
1972(define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS])
1973
1974(define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL])
d7a09c44 1975
b0760a40
RS		 1976(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
1977 UNSPEC_IORV
1978 UNSPEC_SMAXV
1979 UNSPEC_SMINV
1980 UNSPEC_UMAXV
1981 UNSPEC_UMINV
1982 UNSPEC_XORV])
1983
1984(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
1985 UNSPEC_FMAXV
1986 UNSPEC_FMAXNMV
1987 UNSPEC_FMINV
1988 UNSPEC_FMINNMV])
1989
d45b20a5
RS		 1990(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
1991 UNSPEC_COND_FNEG
624d0f07 1992 UNSPEC_COND_FRECPX
d45b20a5
RS		 1993 UNSPEC_COND_FRINTA
1994 UNSPEC_COND_FRINTI
1995 UNSPEC_COND_FRINTM
1996 UNSPEC_COND_FRINTN
1997 UNSPEC_COND_FRINTP
1998 UNSPEC_COND_FRINTX
1999 UNSPEC_COND_FRINTZ
2000 UNSPEC_COND_FSQRT])
2001
95eb5537 2002(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
99361551
RS		 2003(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
2004(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
2005
cb18e86d
RS		 2006(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
2007 UNSPEC_COND_FDIV
624d0f07 2008 UNSPEC_COND_FMAX
cb18e86d 2009 UNSPEC_COND_FMAXNM
624d0f07 2010 UNSPEC_COND_FMIN
cb18e86d
RS		 2011 UNSPEC_COND_FMINNM
2012 UNSPEC_COND_FMUL
624d0f07 2013 UNSPEC_COND_FMULX
cb18e86d 2014 UNSPEC_COND_FSUB])
0d2b3bca 2015
624d0f07
RS		 2016(define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE])
2017
2018(define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD])
2019(define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB])
2020(define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL])
2021
2022(define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX
2023 UNSPEC_COND_FMAXNM
2024 UNSPEC_COND_FMIN
a19ba9e1
RS		 2025 UNSPEC_COND_FMINNM
2026 UNSPEC_COND_FMUL])
2027
624d0f07
RS		 2028(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV
2029 UNSPEC_COND_FMULX])
2030
2031(define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90
2032 UNSPEC_COND_FCADD270])
2033
2034(define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX
2035 UNSPEC_COND_FMAXNM
2036 UNSPEC_COND_FMIN
2037 UNSPEC_COND_FMINNM])
0254ed79 2038
214c42fa
RS		 2039;; Floating-point max/min operations that correspond to optabs,
2040;; as opposed to those that are internal to the port.
2041(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
2042 UNSPEC_COND_FMINNM])
2043
b41d1f6e
RS		 2044(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
2045 UNSPEC_COND_FMLS
2046 UNSPEC_COND_FNMLA
2047 UNSPEC_COND_FNMLS])
2048
624d0f07
RS		 2049(define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA
2050 UNSPEC_COND_FCMLA90
2051 UNSPEC_COND_FCMLA180
2052 UNSPEC_COND_FCMLA270])
2053
2054(define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE
2055 UNSPEC_COND_CMPGE_WIDE
2056 UNSPEC_COND_CMPGT_WIDE
2057 UNSPEC_COND_CMPHI_WIDE
2058 UNSPEC_COND_CMPHS_WIDE
2059 UNSPEC_COND_CMPLE_WIDE
2060 UNSPEC_COND_CMPLO_WIDE
2061 UNSPEC_COND_CMPLS_WIDE
2062 UNSPEC_COND_CMPLT_WIDE
2063 UNSPEC_COND_CMPNE_WIDE])
2064
4a942af6
RS		 2065;; SVE FP comparisons that accept #0.0.
2066(define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
2067 UNSPEC_COND_FCMGE
2068 UNSPEC_COND_FCMGT
2069 UNSPEC_COND_FCMLE
2070 UNSPEC_COND_FCMLT
2071 UNSPEC_COND_FCMNE])
43cacb12 2072
42b4e87d
RS		 2073(define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE
2074 UNSPEC_COND_FCMGT
2075 UNSPEC_COND_FCMLE
2076 UNSPEC_COND_FCMLT])
2077
624d0f07
RS		 2078(define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS])
2079
2080(define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90
2081 UNSPEC_FCMLA180 UNSPEC_FCMLA270])
2082
2083(define_int_iterator SVE_WHILE [UNSPEC_WHILE_LE UNSPEC_WHILE_LO
2084 UNSPEC_WHILE_LS UNSPEC_WHILE_LT])
2085
58c036c8
RS		 2086(define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR])
2087
624d0f07
RS		 2088(define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE
2089 UNSPEC_ASHIFTRT_WIDE
2090 UNSPEC_LSHIFTRT_WIDE])
2091
2092(define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
2093
9d63f43b
TC		 2094(define_int_iterator FCADD [UNSPEC_FCADD90
2095 UNSPEC_FCADD270])
2096
2097(define_int_iterator FCMLA [UNSPEC_FCMLA
2098 UNSPEC_FCMLA90
2099 UNSPEC_FCMLA180
2100 UNSPEC_FCMLA270])
2101
10bd1d96
KT		 2102(define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X
2103 UNSPEC_FRINT64Z UNSPEC_FRINT64X])
2104
624d0f07
RS		 2105(define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB])
2106
2107(define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB])
2108
2109(define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT])
2110
d81cb613
MW		 2111;; Iterators for atomic operations.
2112
2113(define_int_iterator ATOMIC_LDOP
2114 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
2115 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
2116
2117(define_int_attr atomic_ldop
2118 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
2119 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2120
7803ec5e
RH		 2121(define_int_attr atomic_ldoptab
2122 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
2123 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2124
43e9d192
IB		 2125;; -------------------------------------------------------------------
2126;; Int Iterators Attributes.
2127;; -------------------------------------------------------------------
43cacb12
RS		 2128
2129;; The optab associated with an operation. Note that for ANDF, IORF
2130;; and XORF, the optab pattern is not actually defined; we just use this
2131;; name for consistency with the integer patterns.
2132(define_int_attr optab [(UNSPEC_ANDF "and")
2133 (UNSPEC_IORF "ior")
898f07b0 2134 (UNSPEC_XORF "xor")
624d0f07
RS		 2135 (UNSPEC_SADDV "sadd")
2136 (UNSPEC_UADDV "uadd")
898f07b0
RS		 2137 (UNSPEC_ANDV "and")
2138 (UNSPEC_IORV "ior")
0972596e 2139 (UNSPEC_XORV "xor")
624d0f07
RS		 2140 (UNSPEC_FRECPE "frecpe")
2141 (UNSPEC_FRECPS "frecps")
2142 (UNSPEC_RSQRTE "frsqrte")
2143 (UNSPEC_RSQRTS "frsqrts")
2144 (UNSPEC_RBIT "rbit")
d7a09c44
RS		 2145 (UNSPEC_REVB "revb")
2146 (UNSPEC_REVH "revh")
2147 (UNSPEC_REVW "revw")
b0760a40
RS		 2148 (UNSPEC_UMAXV "umax")
2149 (UNSPEC_UMINV "umin")
2150 (UNSPEC_SMAXV "smax")
2151 (UNSPEC_SMINV "smin")
2152 (UNSPEC_FADDV "plus")
2153 (UNSPEC_FMAXNMV "smax")
2154 (UNSPEC_FMAXV "smax_nan")
2155 (UNSPEC_FMINNMV "smin")
2156 (UNSPEC_FMINV "smin_nan")
624d0f07
RS		 2157 (UNSPEC_SMUL_HIGHPART "smulh")
2158 (UNSPEC_UMUL_HIGHPART "umulh")
2159 (UNSPEC_FMLA "fma")
2160 (UNSPEC_FMLS "fnma")
2161 (UNSPEC_FCMLA "fcmla")
2162 (UNSPEC_FCMLA90 "fcmla90")
2163 (UNSPEC_FCMLA180 "fcmla180")
2164 (UNSPEC_FCMLA270 "fcmla270")
2165 (UNSPEC_FEXPA "fexpa")
2166 (UNSPEC_FTSMUL "ftsmul")
2167 (UNSPEC_FTSSEL "ftssel")
58c036c8
RS		 2168 (UNSPEC_WHILERW "vec_check_raw_alias")
2169 (UNSPEC_WHILEWR "vec_check_war_alias")
d45b20a5 2170 (UNSPEC_COND_FABS "abs")
cb18e86d 2171 (UNSPEC_COND_FADD "add")
624d0f07
RS		 2172 (UNSPEC_COND_FCADD90 "cadd90")
2173 (UNSPEC_COND_FCADD270 "cadd270")
2174 (UNSPEC_COND_FCMLA "fcmla")
2175 (UNSPEC_COND_FCMLA90 "fcmla90")
2176 (UNSPEC_COND_FCMLA180 "fcmla180")
2177 (UNSPEC_COND_FCMLA270 "fcmla270")
99361551
RS		 2178 (UNSPEC_COND_FCVT "fcvt")
2179 (UNSPEC_COND_FCVTZS "fix_trunc")
2180 (UNSPEC_COND_FCVTZU "fixuns_trunc")
cb18e86d 2181 (UNSPEC_COND_FDIV "div")
624d0f07 2182 (UNSPEC_COND_FMAX "smax_nan")
cb18e86d 2183 (UNSPEC_COND_FMAXNM "smax")
624d0f07 2184 (UNSPEC_COND_FMIN "smin_nan")
cb18e86d 2185 (UNSPEC_COND_FMINNM "smin")
b41d1f6e
RS		 2186 (UNSPEC_COND_FMLA "fma")
2187 (UNSPEC_COND_FMLS "fnma")
cb18e86d 2188 (UNSPEC_COND_FMUL "mul")
624d0f07 2189 (UNSPEC_COND_FMULX "mulx")
d45b20a5 2190 (UNSPEC_COND_FNEG "neg")
b41d1f6e 2191 (UNSPEC_COND_FNMLA "fnms")
cb18e86d 2192 (UNSPEC_COND_FNMLS "fms")
624d0f07 2193 (UNSPEC_COND_FRECPX "frecpx")
d45b20a5
RS		 2194 (UNSPEC_COND_FRINTA "round")
2195 (UNSPEC_COND_FRINTI "nearbyint")
2196 (UNSPEC_COND_FRINTM "floor")
2197 (UNSPEC_COND_FRINTN "frintn")
2198 (UNSPEC_COND_FRINTP "ceil")
2199 (UNSPEC_COND_FRINTX "rint")
2200 (UNSPEC_COND_FRINTZ "btrunc")
624d0f07 2201 (UNSPEC_COND_FSCALE "fscale")
d45b20a5 2202 (UNSPEC_COND_FSQRT "sqrt")
99361551
RS		 2203 (UNSPEC_COND_FSUB "sub")
2204 (UNSPEC_COND_SCVTF "float")
2205 (UNSPEC_COND_UCVTF "floatuns")])
43cacb12 2206
998eaf97
JG		 2207(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
2208 (UNSPEC_UMINV "umin")
2209 (UNSPEC_SMAXV "smax")
2210 (UNSPEC_SMINV "smin")
2211 (UNSPEC_FMAX "smax_nan")
2212 (UNSPEC_FMAXNMV "smax")
2213 (UNSPEC_FMAXV "smax_nan")
2214 (UNSPEC_FMIN "smin_nan")
2215 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 2216 (UNSPEC_FMINV "smin_nan")
2217 (UNSPEC_FMAXNM "fmax")
214c42fa 2218 (UNSPEC_FMINNM "fmin")
624d0f07 2219 (UNSPEC_COND_FMAX "fmax_nan")
214c42fa 2220 (UNSPEC_COND_FMAXNM "fmax")
624d0f07 2221 (UNSPEC_COND_FMIN "fmin_nan")
214c42fa 2222 (UNSPEC_COND_FMINNM "fmin")])
998eaf97
JG		 2223
2224(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
2225 (UNSPEC_UMINV "umin")
2226 (UNSPEC_SMAXV "smax")
2227 (UNSPEC_SMINV "smin")
2228 (UNSPEC_FMAX "fmax")
2229 (UNSPEC_FMAXNMV "fmaxnm")
2230 (UNSPEC_FMAXV "fmax")
2231 (UNSPEC_FMIN "fmin")
2232 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 2233 (UNSPEC_FMINV "fmin")
2234 (UNSPEC_FMAXNM "fmaxnm")
2235 (UNSPEC_FMINNM "fminnm")])
202d0c11 2236
624d0f07
RS		 2237(define_code_attr binqops_op [(ss_plus "sqadd")
2238 (us_plus "uqadd")
2239 (ss_minus "sqsub")
2240 (us_minus "uqsub")])
2241
2242(define_code_attr binqops_op_rev [(ss_plus "sqsub")
2243 (ss_minus "sqadd")])
2244
43cacb12
RS		 2245;; The SVE logical instruction that implements an unspec.
2246(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
2247 (UNSPEC_IORF "orr")
2248 (UNSPEC_XORF "eor")])
2249
624d0f07
RS		 2250(define_int_attr last_op [(UNSPEC_CLASTA "after_last")
2251 (UNSPEC_CLASTB "last")
2252 (UNSPEC_LASTA "after_last")
2253 (UNSPEC_LASTB "last")])
2254
43cacb12 2255;; "s" for signed operations and "u" for unsigned ones.
624d0f07
RS		 2256(define_int_attr su [(UNSPEC_SADDV "s")
2257 (UNSPEC_UADDV "u")
2258 (UNSPEC_UNPACKSHI "s")
43cacb12
RS		 2259 (UNSPEC_UNPACKUHI "u")
2260 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 2261 (UNSPEC_UNPACKULO "u")
2262 (UNSPEC_SMUL_HIGHPART "s")
99361551
RS		 2263 (UNSPEC_UMUL_HIGHPART "u")
2264 (UNSPEC_COND_FCVTZS "s")
2265 (UNSPEC_COND_FCVTZU "u")
2266 (UNSPEC_COND_SCVTF "s")
58cc9876
YW		 2267 (UNSPEC_COND_UCVTF "u")
2268 (UNSPEC_SMULLB "s") (UNSPEC_UMULLB "u")
2269 (UNSPEC_SMULLT "s") (UNSPEC_UMULLT "u")
2270 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u")
2271 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")])
43cacb12 2272
43e9d192
IB		 2273(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
2274 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
2275 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
2276 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
2277 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 2278 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
2279 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
2280 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 2281 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
2282 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
2283 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
2284 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
2285 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
2286 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
2287 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
2288 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
2289 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
2290 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
2291 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
2292 (UNSPEC_UQSHL "u")
2293 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
2294 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
2295 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
2296 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
2297 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
2298 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
2299 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 2300 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 2301])
2302
2303(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
2304 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
2305 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2306 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
2307 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2308 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
58cc9876
YW		 2309 (UNSPEC_SHRNB "") (UNSPEC_SHRNT "")
2310 (UNSPEC_RSHRNB "r") (UNSPEC_RSHRNT "r")
2311 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "")
2312 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r")
43e9d192
IB		 2313])
2314
2315(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
2316 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
2317
2318(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2319 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 2320 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2321 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
2322 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
2323 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192 2324
58cc9876
YW		 2325(define_int_attr bt [(UNSPEC_SMULLB "b") (UNSPEC_UMULLB "b")
2326 (UNSPEC_SMULLT "t") (UNSPEC_UMULLT "t")])
2327
624d0f07
RS		 2328(define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")])
2329
2330(define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b")
2331 (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")])
2332
43e9d192
IB		 2333(define_int_attr addsub [(UNSPEC_SHADD "add")
2334 (UNSPEC_UHADD "add")
2335 (UNSPEC_SRHADD "add")
2336 (UNSPEC_URHADD "add")
2337 (UNSPEC_SHSUB "sub")
2338 (UNSPEC_UHSUB "sub")
2339 (UNSPEC_SRHSUB "sub")
2340 (UNSPEC_URHSUB "sub")
2341 (UNSPEC_ADDHN "add")
2342 (UNSPEC_SUBHN "sub")
2343 (UNSPEC_RADDHN "add")
2344 (UNSPEC_RSUBHN "sub")
2345 (UNSPEC_ADDHN2 "add")
2346 (UNSPEC_SUBHN2 "sub")
2347 (UNSPEC_RADDHN2 "add")
2348 (UNSPEC_RSUBHN2 "sub")])
2349
2d57b12e
YW		 2350;; BSL variants: first commutative operand.
2351(define_int_attr bsl_1st [(1 "w") (2 "0")])
2352
2353;; BSL variants: second commutative operand.
2354(define_int_attr bsl_2nd [(1 "0") (2 "w")])
2355
2356;; BSL variants: duplicated input operand.
2357(define_int_attr bsl_dup [(1 "1") (2 "2")])
2358
2359;; BSL variants: operand which requires preserving via movprfx.
2360(define_int_attr bsl_mov [(1 "2") (2 "1")])
2361
cb23a30c
JG		 2362(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
2363 (UNSPEC_SSRI "offset_")
2364 (UNSPEC_USRI "offset_")])
43e9d192 2365
42fc9a7f
JG		 2366;; Standard pattern names for floating-point rounding instructions.
2367(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
2368 (UNSPEC_FRINTP "ceil")
2369 (UNSPEC_FRINTM "floor")
2370 (UNSPEC_FRINTI "nearbyint")
2371 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 2372 (UNSPEC_FRINTA "round")
2373 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 2374
2375;; frint suffix for floating-point rounding instructions.
2376(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
2377 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 2378 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
2379 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 2380
2381(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 2382 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
2383 (UNSPEC_FRINTN "frintn")])
42fc9a7f 2384
3f598afe
JW		 2385(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
2386 (UNSPEC_UCVTF "ucvtf")
2387 (UNSPEC_FCVTZS "fcvtzs")
2388 (UNSPEC_FCVTZU "fcvtzu")])
2389
db58fd89 2390;; Pointer authentication mnemonic prefix.
8fc16d72
ST		 2391(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
2392 (UNSPEC_PACIBSP "pacib")
2393 (UNSPEC_PACIA1716 "pacia")
2394 (UNSPEC_PACIB1716 "pacib")
2395 (UNSPEC_AUTIASP "autia")
2396 (UNSPEC_AUTIBSP "autib")
2397 (UNSPEC_AUTIA1716 "autia")
2398 (UNSPEC_AUTIB1716 "autib")])
2399
2400(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
2401 (UNSPEC_PACIBSP "AARCH64_KEY_B")
2402 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
2403 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
2404 (UNSPEC_AUTIASP "AARCH64_KEY_A")
2405 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
2406 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
2407 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
2408
2409;; Pointer authentication HINT number for NOP space instructions using A and
2410;; B key.
2411(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
2412 (UNSPEC_PACIBSP "27")
2413 (UNSPEC_AUTIASP "29")
2414 (UNSPEC_AUTIBSP "31")
2415 (UNSPEC_PACIA1716 "8")
2416 (UNSPEC_PACIB1716 "10")
2417 (UNSPEC_AUTIA1716 "12")
2418 (UNSPEC_AUTIB1716 "14")])
db58fd89 2419
3e2751ce
RS		 2420(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
2421 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
2422 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
cc4d934f 2423
923fcec3
AL		 2424; op code for REV instructions (size within which elements are reversed).
2425(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
2426 (UNSPEC_REV16 "16")])
2427
3e2751ce 2428(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
43cacb12 2429 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 2430
9bfb28ed
RS		 2431;; Return true if the associated optab refers to the high-numbered lanes,
2432;; false if it refers to the low-numbered lanes. The convention is for
2433;; "hi" to refer to the low-numbered lanes (the first ones in memory)
2434;; for big-endian.
2435(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
2436 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
2437 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
2438 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
2439
5d357f26
KT		 2440(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
2441 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
2442 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
2443 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
2444
2445(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
2446 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
2447 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
2448 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
2449
5a7a4e80
TB		 2450(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
2451(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 2452
2453(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
2454 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 2455
2456(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 2457
2458(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 2459
2460(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
2461
2462(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
2463 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
2464
2465(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
2466
2467(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
2468 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12 2469
10bd1d96
KT		 2470(define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x")
2471 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")])
2472
43cacb12 2473;; The condition associated with an UNSPEC_COND_<xx>.
624d0f07
RS		 2474(define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq")
2475 (UNSPEC_COND_CMPGE_WIDE "ge")
2476 (UNSPEC_COND_CMPGT_WIDE "gt")
2477 (UNSPEC_COND_CMPHI_WIDE "hi")
2478 (UNSPEC_COND_CMPHS_WIDE "hs")
2479 (UNSPEC_COND_CMPLE_WIDE "le")
2480 (UNSPEC_COND_CMPLO_WIDE "lo")
2481 (UNSPEC_COND_CMPLS_WIDE "ls")
2482 (UNSPEC_COND_CMPLT_WIDE "lt")
2483 (UNSPEC_COND_CMPNE_WIDE "ne")
2484 (UNSPEC_COND_FCMEQ "eq")
cb18e86d
RS		 2485 (UNSPEC_COND_FCMGE "ge")
2486 (UNSPEC_COND_FCMGT "gt")
2487 (UNSPEC_COND_FCMLE "le")
2488 (UNSPEC_COND_FCMLT "lt")
4a942af6 2489 (UNSPEC_COND_FCMNE "ne")
624d0f07
RS		 2490 (UNSPEC_WHILE_LE "le")
2491 (UNSPEC_WHILE_LO "lo")
2492 (UNSPEC_WHILE_LS "ls")
58c036c8
RS		 2493 (UNSPEC_WHILE_LT "lt")
2494 (UNSPEC_WHILERW "rw")
2495 (UNSPEC_WHILEWR "wr")])
624d0f07
RS		 2496
2497(define_int_attr while_optab_cmp [(UNSPEC_WHILE_LE "le")
2498 (UNSPEC_WHILE_LO "ult")
2499 (UNSPEC_WHILE_LS "ule")
2500 (UNSPEC_WHILE_LT "lt")])
2501
58c036c8
RS		 2502(define_int_attr raw_war [(UNSPEC_WHILERW "raw")
2503 (UNSPEC_WHILEWR "war")])
2504
624d0f07
RS		 2505(define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b")
2506 (UNSPEC_BRKN "n")
2507 (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")])
2508
2509(define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")])
cb18e86d 2510
b0760a40
RS		 2511(define_int_attr sve_int_op [(UNSPEC_ANDV "andv")
2512 (UNSPEC_IORV "orv")
2513 (UNSPEC_XORV "eorv")
2514 (UNSPEC_UMAXV "umaxv")
2515 (UNSPEC_UMINV "uminv")
2516 (UNSPEC_SMAXV "smaxv")
d7a09c44 2517 (UNSPEC_SMINV "sminv")
624d0f07
RS		 2518 (UNSPEC_SMUL_HIGHPART "smulh")
2519 (UNSPEC_UMUL_HIGHPART "umulh")
2520 (UNSPEC_ASHIFT_WIDE "lsl")
2521 (UNSPEC_ASHIFTRT_WIDE "asr")
2522 (UNSPEC_LSHIFTRT_WIDE "lsr")
2523 (UNSPEC_RBIT "rbit")
d7a09c44
RS		 2524 (UNSPEC_REVB "revb")
2525 (UNSPEC_REVH "revh")
2526 (UNSPEC_REVW "revw")])
b0760a40 2527
624d0f07
RS		 2528(define_int_attr sve_fp_op [(UNSPEC_FRECPE "frecpe")
2529 (UNSPEC_FRECPS "frecps")
2530 (UNSPEC_RSQRTE "frsqrte")
2531 (UNSPEC_RSQRTS "frsqrts")
2532 (UNSPEC_FADDV "faddv")
b0760a40
RS		 2533 (UNSPEC_FMAXNMV "fmaxnmv")
2534 (UNSPEC_FMAXV "fmaxv")
2535 (UNSPEC_FMINNMV "fminnmv")
2536 (UNSPEC_FMINV "fminv")
624d0f07
RS		 2537 (UNSPEC_FMLA "fmla")
2538 (UNSPEC_FMLS "fmls")
2539 (UNSPEC_FEXPA "fexpa")
2540 (UNSPEC_FTSMUL "ftsmul")
2541 (UNSPEC_FTSSEL "ftssel")
b0760a40 2542 (UNSPEC_COND_FABS "fabs")
d45b20a5 2543 (UNSPEC_COND_FADD "fadd")
cb18e86d 2544 (UNSPEC_COND_FDIV "fdiv")
624d0f07 2545 (UNSPEC_COND_FMAX "fmax")
cb18e86d 2546 (UNSPEC_COND_FMAXNM "fmaxnm")
624d0f07 2547 (UNSPEC_COND_FMIN "fmin")
cb18e86d
RS		 2548 (UNSPEC_COND_FMINNM "fminnm")
2549 (UNSPEC_COND_FMUL "fmul")
624d0f07 2550 (UNSPEC_COND_FMULX "fmulx")
d45b20a5 2551 (UNSPEC_COND_FNEG "fneg")
624d0f07 2552 (UNSPEC_COND_FRECPX "frecpx")
d45b20a5
RS		 2553 (UNSPEC_COND_FRINTA "frinta")
2554 (UNSPEC_COND_FRINTI "frinti")
2555 (UNSPEC_COND_FRINTM "frintm")
2556 (UNSPEC_COND_FRINTN "frintn")
2557 (UNSPEC_COND_FRINTP "frintp")
2558 (UNSPEC_COND_FRINTX "frintx")
2559 (UNSPEC_COND_FRINTZ "frintz")
624d0f07 2560 (UNSPEC_COND_FSCALE "fscale")
d45b20a5 2561 (UNSPEC_COND_FSQRT "fsqrt")
cb18e86d
RS		 2562 (UNSPEC_COND_FSUB "fsub")])
2563
2564(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
2565 (UNSPEC_COND_FDIV "fdivr")
624d0f07 2566 (UNSPEC_COND_FMAX "fmax")
cb18e86d 2567 (UNSPEC_COND_FMAXNM "fmaxnm")
624d0f07 2568 (UNSPEC_COND_FMIN "fmin")
cb18e86d
RS		 2569 (UNSPEC_COND_FMINNM "fminnm")
2570 (UNSPEC_COND_FMUL "fmul")
624d0f07 2571 (UNSPEC_COND_FMULX "fmulx")
cb18e86d 2572 (UNSPEC_COND_FSUB "fsubr")])
a08acce8 2573
9d63f43b
TC		 2574(define_int_attr rot [(UNSPEC_FCADD90 "90")
2575 (UNSPEC_FCADD270 "270")
2576 (UNSPEC_FCMLA "0")
2577 (UNSPEC_FCMLA90 "90")
2578 (UNSPEC_FCMLA180 "180")
624d0f07
RS		 2579 (UNSPEC_FCMLA270 "270")
2580 (UNSPEC_COND_FCADD90 "90")
2581 (UNSPEC_COND_FCADD270 "270")
2582 (UNSPEC_COND_FCMLA "0")
2583 (UNSPEC_COND_FCMLA90 "90")
2584 (UNSPEC_COND_FCMLA180 "180")
2585 (UNSPEC_COND_FCMLA270 "270")])
9d63f43b 2586
b41d1f6e
RS		 2587(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
2588 (UNSPEC_COND_FMLS "fmls")
2589 (UNSPEC_COND_FNMLA "fnmla")
2590 (UNSPEC_COND_FNMLS "fnmls")])
2591
2592(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
2593 (UNSPEC_COND_FMLS "fmsb")
2594 (UNSPEC_COND_FNMLA "fnmad")
2595 (UNSPEC_COND_FNMLS "fnmsb")])
0254ed79 2596
624d0f07
RS		 2597;; The register constraint to use for the final operand in a binary BRK.
2598(define_int_attr brk_reg_con [(UNSPEC_BRKN "0")
2599 (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")])
2600
2601;; The register number to print for the above.
2602(define_int_attr brk_reg_opno [(UNSPEC_BRKN "0")
2603 (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")])
2604
0254ed79
RS		 2605;; The predicate to use for the first input operand in a floating-point
2606;; <optab><mode>3 pattern.
2607(define_int_attr sve_pred_fp_rhs1_operand
2608 [(UNSPEC_COND_FADD "register_operand")
2609 (UNSPEC_COND_FDIV "register_operand")
624d0f07 2610 (UNSPEC_COND_FMAX "register_operand")
0254ed79 2611 (UNSPEC_COND_FMAXNM "register_operand")
624d0f07 2612 (UNSPEC_COND_FMIN "register_operand")
0254ed79
RS		 2613 (UNSPEC_COND_FMINNM "register_operand")
2614 (UNSPEC_COND_FMUL "register_operand")
624d0f07 2615 (UNSPEC_COND_FMULX "register_operand")
0254ed79
RS		 2616 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
2617
2618;; The predicate to use for the second input operand in a floating-point
2619;; <optab><mode>3 pattern.
2620(define_int_attr sve_pred_fp_rhs2_operand
2621 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
2622 (UNSPEC_COND_FDIV "register_operand")
624d0f07 2623 (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand")
75079ddf 2624 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
624d0f07 2625 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand")
75079ddf 2626 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
0254ed79 2627 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
624d0f07 2628 (UNSPEC_COND_FMULX "register_operand")
0254ed79 2629 (UNSPEC_COND_FSUB "register_operand")])
a19ba9e1
RS		 2630
2631;; Likewise for immediates only.
2632(define_int_attr sve_pred_fp_rhs2_immediate
624d0f07
RS		 2633 [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate")
2634 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate")
2635 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate")
a19ba9e1
RS		 2636 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate")
2637 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")])
d7a09c44 2638
624d0f07
RS		 2639;; The maximum number of element bits that an instruction can handle.
2640(define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32")
2641 (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")])
2642
d7a09c44 2643;; The minimum number of element bits that an instruction can handle.
624d0f07
RS		 2644(define_int_attr min_elem_bits [(UNSPEC_RBIT "8")
2645 (UNSPEC_REVB "16")
d7a09c44
RS		 2646 (UNSPEC_REVH "32")
2647 (UNSPEC_REVW "64")])
58c036c8
RS		 2648
2649(define_int_attr unspec [(UNSPEC_WHILERW "UNSPEC_WHILERW")
2650 (UNSPEC_WHILEWR "UNSPEC_WHILEWR")])
Mirror of https://gcc.gnu.org/git/gcc.git