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526b7aee | 1 | /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. |
85ec4feb | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
526b7aee | 3 | |
526b7aee SV |
4 | This file is part of GCC. |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef GCC_ARC_H | |
21 | #define GCC_ARC_H | |
22 | ||
f9ccf899 CZ |
23 | #include <stdbool.h> |
24 | ||
526b7aee SV |
25 | /* Things to do: |
26 | ||
27 | - incscc, decscc? | |
28 | ||
29 | */ | |
30 | ||
31 | #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0) | |
32 | #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1) | |
33 | #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2) | |
4d03dc2f | 34 | #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3) |
526b7aee | 35 | |
f9ccf899 CZ |
36 | #ifndef TARGET_CPU_DEFAULT |
37 | #define TARGET_CPU_DEFAULT PROCESSOR_arc700 | |
38 | #endif | |
39 | ||
526b7aee SV |
40 | /* Check if this symbol has a long_call attribute in its declaration */ |
41 | #define SYMBOL_REF_LONG_CALL_P(X) \ | |
42 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) | |
43 | ||
44 | /* Check if this symbol has a medium_call attribute in its declaration */ | |
45 | #define SYMBOL_REF_MEDIUM_CALL_P(X) \ | |
46 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0) | |
47 | ||
48 | /* Check if this symbol has a short_call attribute in its declaration */ | |
49 | #define SYMBOL_REF_SHORT_CALL_P(X) \ | |
50 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0) | |
51 | ||
526b7aee | 52 | /* Names to predefine in the preprocessor for this target machine. */ |
cf07c3de | 53 | #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile) |
526b7aee | 54 | |
f9ccf899 CZ |
55 | /* Macros enabled by specific command line option. FIXME: to be |
56 | deprecatd. */ | |
526b7aee SV |
57 | #define CPP_SPEC "\ |
58 | %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \ | |
59 | %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \ | |
60 | %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \ | |
61 | %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \ | |
62 | %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \ | |
63 | %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \ | |
0dee55fe CZ |
64 | %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \ |
65 | %(subtarget_cpp_spec)" | |
526b7aee | 66 | |
fad92291 | 67 | #undef CC1_SPEC |
9f532472 CZ |
68 | #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \ |
69 | %{EB:-mbig-endian} %{EL:-mlittle-endian} \ | |
70 | %{G*} \ | |
526b7aee | 71 | " |
f9ccf899 CZ |
72 | extern const char *arc_cpu_to_as (int argc, const char **argv); |
73 | ||
74 | #define EXTRA_SPEC_FUNCTIONS \ | |
75 | { "cpu_to_as", arc_cpu_to_as }, | |
76 | ||
0dee55fe CZ |
77 | /* This macro defines names of additional specifications to put in the specs |
78 | that can be used in various specifications like CC1_SPEC. Its definition | |
79 | is an initializer with a subgrouping for each command option. | |
80 | ||
81 | Each subgrouping contains a string constant, that defines the | |
82 | specification name, and a string constant that used by the GCC driver | |
83 | program. | |
84 | ||
85 | Do not define this macro if it does not need to do anything. */ | |
86 | #define EXTRA_SPECS \ | |
87 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
88 | SUBTARGET_EXTRA_SPECS | |
89 | ||
90 | #ifndef SUBTARGET_EXTRA_SPECS | |
91 | #define SUBTARGET_EXTRA_SPECS | |
92 | #endif | |
93 | ||
94 | #ifndef SUBTARGET_CPP_SPEC | |
95 | #define SUBTARGET_CPP_SPEC "" | |
96 | #endif | |
97 | ||
fad92291 | 98 | #undef ASM_SPEC |
f9ccf899 CZ |
99 | #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ |
100 | "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}" | |
526b7aee | 101 | |
f9ccf899 CZ |
102 | #define OPTION_DEFAULT_SPECS \ |
103 | {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } | |
526b7aee | 104 | |
526b7aee SV |
105 | #ifndef DRIVER_ENDIAN_SELF_SPECS |
106 | #define DRIVER_ENDIAN_SELF_SPECS "" | |
107 | #endif | |
526b7aee | 108 | |
f9ccf899 CZ |
109 | #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \ |
110 | "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \ | |
111 | "%{mARC601: -mcpu=arc601 %<mARC601}" \ | |
112 | "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \ | |
113 | "%{mEA: -mea %<mEA}" | |
526b7aee SV |
114 | |
115 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
116 | ||
117 | #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET) | |
118 | ||
119 | #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET) | |
8f3304d0 CZ |
120 | #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \ |
121 | || TARGET_FP_DP_AX) | |
526b7aee SV |
122 | |
123 | #define SUBTARGET_SWITCHES | |
124 | ||
125 | /* Instruction set characteristics. | |
126 | These are internal macros, set by the appropriate -m option. */ | |
127 | ||
128 | /* Non-zero means the cpu supports norm instruction. This flag is set by | |
129 | default for A7, and only for pre A7 cores when -mnorm is given. */ | |
f50bb868 | 130 | #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS) |
526b7aee | 131 | /* Indicate if an optimized floating point emulation library is available. */ |
c4014855 | 132 | #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK) |
526b7aee SV |
133 | |
134 | /* Non-zero means the cpu supports swap instruction. This flag is set by | |
135 | default for A7, and only for pre A7 cores when -mswap is given. */ | |
136 | #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET) | |
137 | ||
138 | /* Provide some macros for size / scheduling features of the ARC700, so | |
139 | that we can pick & choose features if we get a new cpu family member. */ | |
140 | ||
141 | /* Should we try to unalign likely taken branches without a delay slot. */ | |
142 | #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size) | |
143 | ||
144 | /* Should we upsize short delayed branches with a short delay insn? */ | |
145 | #define TARGET_UPSIZE_DBR (TARGET_ARC700 && !optimize_size) | |
146 | ||
147 | /* Should we add padding before a return insn to avoid mispredict? */ | |
148 | #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size) | |
149 | ||
150 | /* For an anulled-true delay slot insn for a delayed branch, should we only | |
151 | use conditional execution? */ | |
f50bb868 | 152 | #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2) |
526b7aee | 153 | |
c3bde35a AB |
154 | #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \ |
155 | == BASE_ARCH_6xx) \ | |
f9ccf899 | 156 | && (TARGET_BARREL_SHIFTER)) |
c3bde35a AB |
157 | #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \ |
158 | == BASE_ARCH_6xx) \ | |
f9ccf899 | 159 | && (!TARGET_BARREL_SHIFTER)) |
c3bde35a AB |
160 | #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \ |
161 | == BASE_ARCH_700) | |
3a9abd23 AB |
162 | /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400 |
163 | TARGET_ARC700 is true, and TARGET_NPS400 is true. */ | |
164 | #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \ | |
165 | == BASE_ARCH_700) \ | |
166 | && (arc_selected_cpu->processor \ | |
167 | == PROCESSOR_nps400)) | |
c3bde35a AB |
168 | #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em) |
169 | #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs) | |
f9ccf899 CZ |
170 | #define TARGET_V2 (TARGET_EM || TARGET_HS) |
171 | ||
4d03dc2f JR |
172 | #ifndef UNALIGNED_ACCESS_DEFAULT |
173 | #define UNALIGNED_ACCESS_DEFAULT 0 | |
174 | #endif | |
175 | ||
ceaaa9fe JR |
176 | #ifndef TARGET_NPS_BITOPS_DEFAULT |
177 | #define TARGET_NPS_BITOPS_DEFAULT 0 | |
178 | #endif | |
179 | ||
4d03dc2f JR |
180 | #ifndef TARGET_NPS_CMEM_DEFAULT |
181 | #define TARGET_NPS_CMEM_DEFAULT 0 | |
182 | #endif | |
183 | ||
ceaaa9fe JR |
184 | /* Enable the RRQ instruction alternatives. */ |
185 | ||
186 | #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS | |
187 | ||
526b7aee SV |
188 | /* Target machine storage layout. */ |
189 | ||
190 | /* We want zero_extract to mean the same | |
191 | no matter what the byte endianness is. */ | |
192 | #define BITS_BIG_ENDIAN 0 | |
193 | ||
194 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
195 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
196 | ||
197 | /* Define this if most significant word of a multiword number is the lowest | |
198 | numbered. */ | |
199 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
200 | ||
526b7aee SV |
201 | /* Width in bits of a "word", which is the contents of a machine register. |
202 | Note that this is not necessarily the width of data type `int'; | |
203 | if using 16-bit ints on a 68000, this would still be 32. | |
204 | But on a machine with 16-bit registers, this would be 16. */ | |
205 | #define BITS_PER_WORD 32 | |
206 | ||
207 | /* Width of a word, in units (bytes). */ | |
208 | #define UNITS_PER_WORD 4 | |
209 | ||
210 | /* Define this macro if it is advisable to hold scalars in registers | |
211 | in a wider mode than that declared by the program. In such cases, | |
212 | the value is constrained to be within the bounds of the declared | |
213 | type, but kept valid in the wider mode. The signedness of the | |
214 | extension may differ from that of the type. */ | |
215 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
216 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
217 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
218 | { \ | |
219 | (MODE) = SImode; \ | |
220 | } | |
221 | ||
222 | /* Width in bits of a pointer. | |
223 | See also the macro `Pmode' defined below. */ | |
224 | #define POINTER_SIZE 32 | |
225 | ||
226 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
227 | #define PARM_BOUNDARY 32 | |
228 | ||
229 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
230 | /* TOCHECK: Changed from 64 to 32 */ | |
231 | #define STACK_BOUNDARY 32 | |
232 | ||
233 | /* ALIGN FRAMES on word boundaries. */ | |
234 | #define ARC_STACK_ALIGN(LOC) \ | |
235 | (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT) | |
236 | ||
237 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
238 | #define FUNCTION_BOUNDARY 32 | |
239 | ||
240 | /* Alignment of field after `int : 0' in a structure. */ | |
241 | #define EMPTY_FIELD_BOUNDARY 32 | |
242 | ||
243 | /* Every structure's size must be a multiple of this. */ | |
244 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
245 | ||
246 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
247 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
248 | ||
249 | /* An expression for the alignment of a structure field FIELD if the | |
250 | alignment computed in the usual way (including applying of | |
251 | `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the | |
252 | alignment) is COMPUTED. It overrides alignment only if the field | |
253 | alignment has not been set by the `__attribute__ ((aligned (N)))' | |
254 | construct. | |
255 | */ | |
256 | ||
a4cf4b64 RB |
257 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
258 | (TYPE_MODE (strip_array_types (TYPE)) == DFmode \ | |
526b7aee SV |
259 | ? MIN ((COMPUTED), 32) : (COMPUTED)) |
260 | ||
261 | ||
262 | ||
263 | /* No data type wants to be aligned rounder than this. */ | |
264 | /* This is bigger than currently necessary for the ARC. If 8 byte floats are | |
265 | ever added it's not clear whether they'll need such alignment or not. For | |
266 | now we assume they will. We can always relax it if necessary but the | |
267 | reverse isn't true. */ | |
268 | /* TOCHECK: Changed from 64 to 32 */ | |
269 | #define BIGGEST_ALIGNMENT 32 | |
270 | ||
271 | /* The best alignment to use in cases where we have a choice. */ | |
272 | #define FASTEST_ALIGNMENT 32 | |
273 | ||
526b7aee SV |
274 | /* Make arrays of chars word-aligned for the same reasons. */ |
275 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
276 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
277 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
278 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
279 | ||
280 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
281 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
282 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
283 | && arc_size_opt_level < 3 \ | |
284 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
285 | ||
286 | /* Set this nonzero if move instructions will actually fail to work | |
287 | when given unaligned data. */ | |
288 | /* On the ARC the lower address bits are masked to 0 as necessary. The chip | |
289 | won't croak when given an unaligned address, but the insn will still fail | |
290 | to produce the correct result. */ | |
291 | #define STRICT_ALIGNMENT 1 | |
292 | ||
293 | /* Layout of source language data types. */ | |
294 | ||
295 | #define SHORT_TYPE_SIZE 16 | |
296 | #define INT_TYPE_SIZE 32 | |
297 | #define LONG_TYPE_SIZE 32 | |
298 | #define LONG_LONG_TYPE_SIZE 64 | |
299 | #define FLOAT_TYPE_SIZE 32 | |
300 | #define DOUBLE_TYPE_SIZE 64 | |
301 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
302 | ||
303 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
304 | #define DEFAULT_SIGNED_CHAR 0 | |
305 | ||
fad92291 | 306 | #undef SIZE_TYPE |
db64c64e | 307 | #define SIZE_TYPE "unsigned int" |
fad92291 CZ |
308 | |
309 | #undef PTRDIFF_TYPE | |
db64c64e | 310 | #define PTRDIFF_TYPE "int" |
fad92291 CZ |
311 | |
312 | #undef WCHAR_TYPE | |
526b7aee | 313 | #define WCHAR_TYPE "int" |
526b7aee | 314 | |
fad92291 CZ |
315 | #undef WCHAR_TYPE_SIZE |
316 | #define WCHAR_TYPE_SIZE 32 | |
526b7aee | 317 | |
526b7aee SV |
318 | #define PROGRAM_COUNTER_REGNO 63 |
319 | ||
320 | /* Standard register usage. */ | |
321 | ||
322 | /* Number of actual hardware registers. | |
323 | The hardware registers are assigned numbers for the compiler | |
324 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
325 | All registers that the compiler knows about must be given numbers, | |
326 | even those that are not normally considered general registers. | |
327 | ||
328 | Registers 61, 62, and 63 are not really registers and we needn't treat | |
329 | them as such. We still need a register for the condition code and | |
330 | argument pointer. */ | |
331 | ||
332 | /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs | |
333 | r144, r145 = lp_start, lp_end | |
334 | and therefore the pseudo registers start from r146. */ | |
335 | #define FIRST_PSEUDO_REGISTER 146 | |
336 | ||
337 | /* 1 for registers that have pervasive standard uses | |
338 | and are not available for the register allocator. | |
339 | ||
340 | 0-28 - general purpose registers | |
341 | 29 - ilink1 (interrupt link register) | |
342 | 30 - ilink2 (interrupt link register) | |
343 | 31 - blink (branch link register) | |
344 | 32-59 - reserved for extensions | |
345 | 60 - LP_COUNT | |
346 | 61 - condition code | |
347 | 62 - argument pointer | |
348 | 63 - program counter | |
349 | ||
350 | FWIW, this is how the 61-63 encodings are used by the hardware: | |
351 | 61 - reserved | |
352 | 62 - long immediate data indicator | |
353 | 63 - PCL (program counter aligned to 32 bit, read-only) | |
354 | ||
355 | The general purpose registers are further broken down into: | |
356 | ||
357 | 0-7 - arguments/results | |
358 | 8-12 - call used (r11 - static chain pointer) | |
359 | 13-25 - call saved | |
360 | 26 - global pointer | |
361 | 27 - frame pointer | |
362 | 28 - stack pointer | |
363 | 29 - ilink1 | |
364 | 30 - ilink2 | |
365 | 31 - return address register | |
366 | ||
367 | By default, the extension registers are not available. */ | |
368 | /* Present implementations only have VR0-VR23 only. */ | |
369 | /* ??? FIXME: r27 and r31 should not be fixed registers. */ | |
370 | #define FIXED_REGISTERS \ | |
371 | { 0, 0, 0, 0, 0, 0, 0, 0, \ | |
372 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
373 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
374 | 0, 0, 1, 1, 1, 1, 1, 1, \ | |
375 | \ | |
376 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
377 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
378 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
379 | 1, 1, 1, 1, 0, 1, 1, 1, \ | |
380 | \ | |
381 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
382 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
383 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
384 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
385 | \ | |
386 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
387 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
388 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
389 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
390 | \ | |
391 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
392 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
393 | 1, 1} | |
394 | ||
395 | /* 1 for registers not available across function calls. | |
396 | These must include the FIXED_REGISTERS and also any | |
397 | registers that can be used without being saved. | |
398 | The latter must include the registers where values are returned | |
399 | and the register where structure-value addresses are passed. | |
400 | Aside from that, you can include as many other registers as you like. */ | |
401 | #define CALL_USED_REGISTERS \ | |
402 | { \ | |
403 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
404 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
405 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
406 | 0, 0, 1, 1, 1, 1, 1, 1, \ | |
407 | \ | |
408 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
409 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
410 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
411 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
412 | \ | |
413 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
414 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
415 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
416 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
417 | \ | |
418 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
419 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
420 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
421 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
422 | \ | |
423 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
424 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
425 | 1, 1} | |
426 | ||
427 | /* If defined, an initializer for a vector of integers, containing the | |
428 | numbers of hard registers in the order in which GCC should | |
429 | prefer to use them (from most preferred to least). */ | |
430 | #define REG_ALLOC_ORDER \ | |
431 | { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \ | |
432 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \ | |
433 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
434 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ | |
435 | 27, 28, 29, 30, 31, 63} | |
436 | ||
526b7aee SV |
437 | /* Internal macros to classify a register number as to whether it's a |
438 | general purpose register for compact insns (r0-r3,r12-r15), or | |
439 | stack pointer (r28). */ | |
440 | ||
441 | #define COMPACT_GP_REG_P(REGNO) \ | |
442 | (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15)) | |
443 | #define SP_REG_P(REGNO) ((REGNO) == 28) | |
444 | ||
445 | ||
446 | ||
447 | /* Register classes and constants. */ | |
448 | ||
449 | /* Define the classes of registers for register constraints in the | |
450 | machine description. Also define ranges of constants. | |
451 | ||
452 | One of the classes must always be named ALL_REGS and include all hard regs. | |
453 | If there is more than one class, another class must be named NO_REGS | |
454 | and contain no registers. | |
455 | ||
456 | The name GENERAL_REGS must be the name of a class (or an alias for | |
457 | another name such as ALL_REGS). This is the class of registers | |
458 | that is allowed by "g" or "r" in a register constraint. | |
459 | Also, registers outside this class are allocated only when | |
460 | instructions express preferences for them. | |
461 | ||
462 | The classes must be numbered in nondecreasing order; that is, | |
463 | a larger-numbered class must never be contained completely | |
464 | in a smaller-numbered class. | |
465 | ||
466 | For any two classes, it is very desirable that there be another | |
467 | class that represents their union. | |
468 | ||
469 | It is important that any condition codes have class NO_REGS. | |
470 | See `register_operand'. */ | |
471 | ||
472 | enum reg_class | |
473 | { | |
474 | NO_REGS, | |
475 | R0_REGS, /* 'x' */ | |
476 | GP_REG, /* 'Rgp' */ | |
477 | FP_REG, /* 'f' */ | |
478 | SP_REGS, /* 'b' */ | |
479 | LPCOUNT_REG, /* 'l' */ | |
480 | LINK_REGS, /* 'k' */ | |
481 | DOUBLE_REGS, /* D0, D1 */ | |
482 | SIMD_VR_REGS, /* VR00-VR63 */ | |
483 | SIMD_DMA_CONFIG_REGS, /* DI0-DI7,DO0-DO7 */ | |
484 | ARCOMPACT16_REGS, /* 'q' */ | |
485 | AC16_BASE_REGS, /* 'e' */ | |
486 | SIBCALL_REGS, /* "Rsc" */ | |
487 | GENERAL_REGS, /* 'r' */ | |
488 | MPY_WRITABLE_CORE_REGS, /* 'W' */ | |
489 | WRITABLE_CORE_REGS, /* 'w' */ | |
490 | CHEAP_CORE_REGS, /* 'c' */ | |
491 | ALL_CORE_REGS, /* 'Rac' */ | |
fc1c2d04 CZ |
492 | R0R3_CD_REGS, /* 'Rcd' */ |
493 | R0R1_CD_REGS, /* 'Rsd' */ | |
494 | AC16_H_REGS, /* 'h' */ | |
526b7aee SV |
495 | ALL_REGS, |
496 | LIM_REG_CLASSES | |
497 | }; | |
498 | ||
499 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
500 | ||
501 | /* Give names of register classes as strings for dump file. */ | |
502 | #define REG_CLASS_NAMES \ | |
503 | { \ | |
504 | "NO_REGS", \ | |
505 | "R0_REGS", \ | |
506 | "GP_REG", \ | |
507 | "FP_REG", \ | |
508 | "SP_REGS", \ | |
509 | "LPCOUNT_REG", \ | |
510 | "LINK_REGS", \ | |
511 | "DOUBLE_REGS", \ | |
512 | "SIMD_VR_REGS", \ | |
513 | "SIMD_DMA_CONFIG_REGS", \ | |
514 | "ARCOMPACT16_REGS", \ | |
515 | "AC16_BASE_REGS", \ | |
516 | "SIBCALL_REGS", \ | |
517 | "GENERAL_REGS", \ | |
518 | "MPY_WRITABLE_CORE_REGS", \ | |
519 | "WRITABLE_CORE_REGS", \ | |
520 | "CHEAP_CORE_REGS", \ | |
fc1c2d04 CZ |
521 | "R0R3_CD_REGS", \ |
522 | "R0R1_CD_REGS", \ | |
523 | "AC16_H_REGS", \ | |
526b7aee SV |
524 | "ALL_CORE_REGS", \ |
525 | "ALL_REGS" \ | |
526 | } | |
527 | ||
528 | /* Define which registers fit in which classes. | |
529 | This is an initializer for a vector of HARD_REG_SET | |
530 | of length N_REG_CLASSES. */ | |
531 | ||
532 | #define REG_CLASS_CONTENTS \ | |
533 | { \ | |
534 | {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* No Registers */ \ | |
535 | {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x', r0 register , r0 */ \ | |
536 | {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \ | |
537 | {0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'f', Frame Pointer, r27 */ \ | |
538 | {0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'b', Stack Pointer, r28 */ \ | |
539 | {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \ | |
540 | {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \ | |
541 | {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D', D1, D2 Registers */ \ | |
542 | {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'V', VR00-VR63 Registers */ \ | |
543 | {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \ | |
544 | {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q', r0-r3, r12-r15 */ \ | |
545 | {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'e', r0-r3, r12-r15, sp */ \ | |
546 | {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* "Rsc", r0-r12 */ \ | |
a2de90a4 | 547 | {0x9fffffff, 0x80000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \ |
526b7aee SV |
548 | {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'W', r0-r31 */ \ |
549 | /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \ | |
550 | registers are fixed, it does not affect the literal meaning of the \ | |
551 | constraints, but it makes it a superset of GENERAL_REGS, thus \ | |
552 | enabling some operations that would otherwise not be possible. */ \ | |
a2de90a4 CZ |
553 | {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \ |
554 | {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \ | |
555 | {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \ | |
fc1c2d04 CZ |
556 | {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd', r0-r3 */ \ |
557 | {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd', r0-r1 */ \ | |
558 | {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h', r0-28, r30 */ \ | |
526b7aee SV |
559 | {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \ |
560 | } | |
561 | ||
562 | /* Local macros to mark the first and last regs of different classes. */ | |
563 | #define ARC_FIRST_SIMD_VR_REG 64 | |
564 | #define ARC_LAST_SIMD_VR_REG 127 | |
565 | ||
566 | #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128 | |
567 | #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128 | |
568 | #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136 | |
569 | #define ARC_LAST_SIMD_DMA_CONFIG_REG 143 | |
570 | ||
8f3304d0 CZ |
571 | /* ARCv2 double-register accumulator. */ |
572 | #define ACC_REG_FIRST 58 | |
573 | #define ACC_REG_LAST 59 | |
574 | #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST) | |
575 | #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1) | |
576 | ||
526b7aee SV |
577 | /* The same information, inverted: |
578 | Return the class number of the smallest class containing | |
579 | reg number REGNO. This could be a conditional expression | |
580 | or could index an array. */ | |
581 | ||
582 | extern enum reg_class arc_regno_reg_class[]; | |
583 | ||
584 | #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO]) | |
585 | ||
586 | /* The class value for valid index registers. An index register is | |
587 | one used in an address where its value is either multiplied by | |
588 | a scale factor or added to another register (as well as added to a | |
589 | displacement). */ | |
590 | ||
591 | #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS) | |
592 | ||
593 | /* The class value for valid base registers. A base register is one used in | |
594 | an address which is the register value plus a displacement. */ | |
595 | ||
596 | #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS) | |
597 | ||
598 | /* These assume that REGNO is a hard or pseudo reg number. | |
599 | They give nonzero only if REGNO is a hard reg of the suitable class | |
600 | or a pseudo reg currently allocated to a suitable hard reg. | |
601 | Since they use reg_renumber, they are safe only once reg_renumber | |
602 | has been allocated, which happens in local-alloc.c. */ | |
28633bbd CZ |
603 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
604 | ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \ | |
605 | || ((unsigned) reg_renumber[REGNO] < 29) \ | |
4f9c5d5c | 606 | || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ |
23c98523 CZ |
607 | || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ |
608 | || ((REGNO) == 30 && fixed_regs[REGNO] == 0)) | |
526b7aee SV |
609 | |
610 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) | |
611 | ||
612 | /* Given an rtx X being reloaded into a reg required to be | |
613 | in class CLASS, return the class of reg to actually use. | |
614 | In general this is just CLASS; but on some machines | |
615 | in some cases it is preferable to use a more restrictive class. */ | |
616 | ||
617 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
618 | arc_preferred_reload_class((X), (CLASS)) | |
619 | ||
620 | extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class); | |
621 | ||
622 | /* Return the maximum number of consecutive registers | |
623 | needed to represent mode MODE in a register of class CLASS. */ | |
624 | ||
625 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
626 | (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \ | |
627 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
628 | ||
629 | #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) | |
630 | #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \ | |
631 | ((unsigned) (((X) >> (SHIFT)) + 0x100) \ | |
632 | < 0x200 - ((unsigned) (OFFSET) >> (SHIFT))) | |
633 | #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000) | |
f50bb868 | 634 | #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000) |
526b7aee SV |
635 | #define LARGE_INT(X) \ |
636 | (((X) < 0) \ | |
637 | ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ | |
638 | : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff) | |
639 | #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8) | |
640 | #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20) | |
641 | #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40) | |
642 | #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80) | |
643 | #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100) | |
7132ae19 CZ |
644 | #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800) |
645 | #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000) | |
526b7aee SV |
646 | #define IS_ONE(X) ((X) == 1) |
647 | #define IS_ZERO(X) ((X) == 0) | |
648 | ||
649 | /* Stack layout and stack pointer usage. */ | |
650 | ||
651 | /* Define this macro if pushing a word onto the stack moves the stack | |
652 | pointer to a smaller address. */ | |
62f9f30b | 653 | #define STACK_GROWS_DOWNWARD 1 |
526b7aee SV |
654 | |
655 | /* Define this if the nominal address of the stack frame | |
656 | is at the high-address end of the local variables; | |
657 | that is, each additional local variable allocated | |
658 | goes at a more negative offset in the frame. */ | |
659 | #define FRAME_GROWS_DOWNWARD 1 | |
660 | ||
526b7aee SV |
661 | /* Offset from the stack pointer register to the first location at which |
662 | outgoing arguments are placed. */ | |
663 | #define STACK_POINTER_OFFSET (0) | |
664 | ||
665 | /* Offset of first parameter from the argument pointer register value. */ | |
666 | #define FIRST_PARM_OFFSET(FNDECL) (0) | |
667 | ||
668 | /* A C expression whose value is RTL representing the address in a | |
669 | stack frame where the pointer to the caller's frame is stored. | |
670 | Assume that FRAMEADDR is an RTL expression for the address of the | |
671 | stack frame itself. | |
672 | ||
673 | If you don't define this macro, the default is to return the value | |
674 | of FRAMEADDR--that is, the stack frame address is also the address | |
675 | of the stack word that points to the previous frame. */ | |
676 | /* ??? unfinished */ | |
677 | /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ | |
678 | ||
679 | /* A C expression whose value is RTL representing the value of the | |
680 | return address for the frame COUNT steps up from the current frame. | |
681 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
682 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' | |
683 | is defined. */ | |
684 | /* The current return address is in r31. The return address of anything | |
685 | farther back is at [%fp,4]. */ | |
686 | ||
687 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
688 | arc_return_addr_rtx(COUNT,FRAME) | |
689 | ||
690 | /* Register to use for pushing function arguments. */ | |
691 | #define STACK_POINTER_REGNUM 28 | |
692 | ||
693 | /* Base register for access to local variables of the function. */ | |
694 | #define FRAME_POINTER_REGNUM 27 | |
695 | ||
696 | /* Base register for access to arguments of the function. This register | |
697 | will be eliminated into either fp or sp. */ | |
698 | #define ARG_POINTER_REGNUM 62 | |
699 | ||
700 | #define RETURN_ADDR_REGNUM 31 | |
701 | ||
702 | /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */ | |
703 | /* Register in which static-chain is passed to a function. This must | |
704 | not be a register used by the prologue. */ | |
705 | #define STATIC_CHAIN_REGNUM 11 | |
706 | ||
707 | /* Function argument passing. */ | |
708 | ||
709 | /* If defined, the maximum amount of space required for outgoing | |
710 | arguments will be computed and placed into the variable | |
711 | `crtl->outgoing_args_size'. No space will be pushed | |
712 | onto the stack for each call; instead, the function prologue should | |
713 | increase the stack frame size by this amount. */ | |
714 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
715 | ||
716 | /* Define a data type for recording info about an argument list | |
717 | during the scan of that argument list. This data type should | |
718 | hold all necessary information about the function itself | |
719 | and about the args processed so far, enough to enable macros | |
720 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
721 | #define CUMULATIVE_ARGS int | |
722 | ||
723 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
724 | for a call to a function whose data type is FNTYPE. | |
725 | For a library call, FNTYPE is 0. */ | |
726 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ | |
8f3304d0 | 727 | ((CUM) = 0) |
526b7aee SV |
728 | |
729 | /* The number of registers used for parameter passing. Local to this file. */ | |
730 | #define MAX_ARC_PARM_REGS 8 | |
731 | ||
732 | /* 1 if N is a possible register number for function argument passing. */ | |
733 | #define FUNCTION_ARG_REGNO_P(N) \ | |
734 | ((unsigned) (N) < MAX_ARC_PARM_REGS) | |
735 | ||
736 | /* The ROUND_ADVANCE* macros are local to this file. */ | |
737 | /* Round SIZE up to a word boundary. */ | |
738 | #define ROUND_ADVANCE(SIZE) \ | |
739 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
740 | ||
741 | /* Round arg MODE/TYPE up to the next word boundary. */ | |
742 | #define ROUND_ADVANCE_ARG(MODE, TYPE) \ | |
743 | ((MODE) == BLKmode \ | |
744 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
745 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
746 | ||
747 | #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY | |
748 | /* Round CUM up to the necessary point for argument MODE/TYPE. */ | |
749 | /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT. | |
750 | ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */ | |
751 | #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ | |
752 | ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\ | |
753 | + 1) | |
754 | ||
755 | /* Return boolean indicating arg of type TYPE and mode MODE will be passed in | |
756 | a reg. This includes arguments that have to be passed by reference as the | |
757 | pointer to them is passed in a reg if one is available (and that is what | |
758 | we're given). | |
759 | When passing arguments NAMED is always 1. When receiving arguments NAMED | |
760 | is 1 for each argument except the last in a stdarg/varargs function. In | |
761 | a stdarg function we want to treat the last named arg as named. In a | |
762 | varargs function we want to treat the last named arg (which is | |
763 | `__builtin_va_alist') as unnamed. | |
764 | This macro is only used in this file. */ | |
765 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
766 | ((CUM) < MAX_ARC_PARM_REGS) | |
767 | ||
768 | ||
769 | /* Function results. */ | |
770 | ||
771 | /* Define how to find the value returned by a library function | |
772 | assuming the value has mode MODE. */ | |
773 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) | |
774 | ||
775 | /* 1 if N is a possible register number for a function value | |
776 | as seen by the caller. */ | |
777 | /* ??? What about r1 in DI/DF values. */ | |
778 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
779 | ||
780 | /* Tell GCC to use RETURN_IN_MEMORY. */ | |
781 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
782 | ||
526b7aee SV |
783 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
784 | the stack pointer does not matter. The value is tested only in | |
785 | functions that have frame pointers. | |
786 | No definition is equivalent to always zero. */ | |
787 | #define EXIT_IGNORE_STACK 0 | |
788 | ||
789 | #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO)) | |
790 | ||
28633bbd CZ |
791 | #define EH_USES(REGNO) arc_eh_uses((REGNO)) |
792 | ||
526b7aee SV |
793 | /* Definitions for register eliminations. |
794 | ||
795 | This is an array of structures. Each structure initializes one pair | |
796 | of eliminable registers. The "from" register number is given first, | |
797 | followed by "to". Eliminations of the same "from" register are listed | |
798 | in order of preference. | |
799 | ||
800 | We have two registers that can be eliminated on the ARC. First, the | |
801 | argument pointer register can always be eliminated in favor of the stack | |
802 | pointer register or frame pointer register. Secondly, the frame pointer | |
803 | register can often be eliminated in favor of the stack pointer register. | |
804 | */ | |
805 | ||
806 | #define ELIMINABLE_REGS \ | |
807 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
808 | {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
809 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
810 | ||
811 | /* Define the offset between two registers, one to be eliminated, and the other | |
812 | its replacement, at the start of a routine. */ | |
813 | extern int arc_initial_elimination_offset(int from, int to); | |
814 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
815 | (OFFSET) = arc_initial_elimination_offset ((FROM), (TO)) | |
816 | ||
817 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
e04ea1da CZ |
818 | for profiling a function entry. */ |
819 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
820 | do { \ | |
821 | if (flag_pic) \ | |
822 | fprintf (FILE, "\tbl\t__mcount@plt\n"); \ | |
823 | else \ | |
824 | fprintf (FILE, "\tbl\t__mcount\n"); \ | |
4397fc04 | 825 | } while (0) |
526b7aee SV |
826 | |
827 | #define NO_PROFILE_COUNTERS 1 | |
828 | ||
829 | /* Trampolines. */ | |
830 | ||
831 | /* Length in units of the trampoline for entering a nested function. */ | |
832 | #define TRAMPOLINE_SIZE 20 | |
833 | ||
834 | /* Alignment required for a trampoline in bits . */ | |
835 | /* For actual data alignment we just need 32, no more than the stack; | |
836 | however, to reduce cache coherency issues, we want to make sure that | |
837 | trampoline instructions always appear the same in any given cache line. */ | |
838 | #define TRAMPOLINE_ALIGNMENT 256 | |
839 | ||
840 | /* Library calls. */ | |
841 | ||
842 | /* Addressing modes, and classification of registers for them. */ | |
843 | ||
844 | /* Maximum number of registers that can appear in a valid memory address. */ | |
845 | /* The `ld' insn allows 2, but the `st' insn only allows 1. */ | |
846 | #define MAX_REGS_PER_ADDRESS 1 | |
847 | ||
848 | /* We have pre inc/dec (load/store with update). */ | |
849 | #define HAVE_PRE_INCREMENT 1 | |
850 | #define HAVE_PRE_DECREMENT 1 | |
851 | #define HAVE_POST_INCREMENT 1 | |
852 | #define HAVE_POST_DECREMENT 1 | |
853 | #define HAVE_PRE_MODIFY_DISP 1 | |
854 | #define HAVE_POST_MODIFY_DISP 1 | |
855 | #define HAVE_PRE_MODIFY_REG 1 | |
856 | #define HAVE_POST_MODIFY_REG 1 | |
857 | /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires | |
858 | a special predicate for the memory operand of stores, like for the SH. */ | |
859 | ||
860 | /* Recognize any constant value that is a valid address. */ | |
b6c354eb CZ |
861 | #define CONSTANT_ADDRESS_P(X) \ |
862 | (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \ | |
863 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
864 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)) | |
526b7aee SV |
865 | |
866 | /* Is the argument a const_int rtx, containing an exact power of 2 */ | |
867 | #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X)) | |
ceaaa9fe | 868 | #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1))) |
526b7aee SV |
869 | |
870 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
871 | and check its validity for a certain class. | |
872 | We have two alternate definitions for each of them. | |
873 | The *_NONSTRICT definition accepts all pseudo regs; the other rejects | |
874 | them unless they have been allocated suitable hard regs. | |
875 | ||
876 | Most source files want to accept pseudo regs in the hope that | |
877 | they will get allocated to the class that the insn wants them to be in. | |
878 | Source files for reload pass need to be strict. | |
879 | After reload, it makes no difference, since pseudo regs have | |
880 | been eliminated by then. */ | |
881 | ||
882 | /* Nonzero if X is a hard reg that can be used as an index | |
883 | or if it is a pseudo reg. */ | |
4f9c5d5c CZ |
884 | #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \ |
885 | ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
886 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
887 | ||
526b7aee SV |
888 | /* Nonzero if X is a hard reg that can be used as a base reg |
889 | or if it is a pseudo reg. */ | |
4f9c5d5c CZ |
890 | #define REG_OK_FOR_BASE_P_NONSTRICT(X) \ |
891 | ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
892 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
526b7aee SV |
893 | |
894 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
895 | #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
896 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
897 | #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
898 | ||
899 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
900 | that is a valid memory address for an instruction. | |
901 | The MODE argument is the machine mode for the MEM expression | |
902 | that wants to use this address. */ | |
903 | /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] | |
904 | but the `st' insn only allows [reg],[reg+shimm],[limm]. | |
905 | The only thing we can do is only allow the most strict case `st' and hope | |
906 | other parts optimize out the restrictions for `ld'. */ | |
907 | ||
908 | #define RTX_OK_FOR_BASE_P(X, STRICT) \ | |
909 | (REG_P (X) \ | |
910 | && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X))) | |
911 | ||
912 | #define RTX_OK_FOR_INDEX_P(X, STRICT) \ | |
913 | (REG_P (X) \ | |
914 | && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X))) | |
915 | ||
916 | /* A C compound statement that attempts to replace X, which is an address | |
917 | that needs reloading, with a valid memory address for an operand of | |
918 | mode MODE. WIN is a C statement label elsewhere in the code. | |
919 | ||
920 | We try to get a normal form | |
921 | of the address. That will allow inheritance of the address reloads. */ | |
922 | ||
923 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
924 | do { \ | |
925 | if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ | |
926 | goto WIN; \ | |
927 | } while (0) | |
928 | ||
929 | /* Reading lp_count for anything but the lp instruction is very slow on the | |
930 | ARC700. */ | |
931 | #define DONT_REALLOC(REGNO,MODE) \ | |
932 | (TARGET_ARC700 && (REGNO) == 60) | |
933 | ||
934 | ||
935 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
936 | return the mode to be used for the comparison. */ | |
ef4bddc2 | 937 | /*extern machine_mode arc_select_cc_mode ();*/ |
526b7aee SV |
938 | #define SELECT_CC_MODE(OP, X, Y) \ |
939 | arc_select_cc_mode (OP, X, Y) | |
940 | ||
941 | /* Return non-zero if SELECT_CC_MODE will never return MODE for a | |
942 | floating point inequality comparison. */ | |
943 | #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ | |
944 | ||
945 | /* Costs. */ | |
946 | ||
947 | /* Compute extra cost of moving data between one register class | |
948 | and another. */ | |
949 | #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \ | |
950 | arc_register_move_cost ((MODE), (CLASS), (TO_CLASS)) | |
951 | ||
952 | /* Compute the cost of moving data between registers and memory. */ | |
953 | /* Memory is 3 times as expensive as registers. | |
954 | ??? Is that the right way to look at it? */ | |
955 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
956 | (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) | |
957 | ||
958 | /* The cost of a branch insn. */ | |
959 | /* ??? What's the right value here? Branches are certainly more | |
960 | expensive than reg->reg moves. */ | |
961 | #define BRANCH_COST(speed_p, predictable_p) 2 | |
962 | ||
b4e23970 JR |
963 | /* Scc sets the destination to 1 and then conditionally zeroes it. |
964 | Best case, ORed SCCs can be made into clear - condset - condset. | |
965 | But it could also end up as five insns. So say it costs four on | |
966 | average. | |
967 | These extra instructions - and the second comparison - will also be | |
968 | an extra cost if the first comparison would have been decisive. | |
969 | So get an average saving, with a probability of the first branch | |
970 | beging decisive of p0, we want: | |
971 | p0 * (branch_cost - 4) > (1 - p0) * 5 | |
972 | ??? We don't get to see that probability to evaluate, so we can | |
973 | only wildly guess that it might be 50%. | |
974 | ??? The compiler also lacks the notion of branch predictability. */ | |
975 | #define LOGICAL_OP_NON_SHORT_CIRCUIT \ | |
976 | (BRANCH_COST (optimize_function_for_speed_p (cfun), \ | |
977 | false) > 9) | |
978 | ||
526b7aee SV |
979 | /* Nonzero if access to memory by bytes is slow and undesirable. |
980 | For RISC chips, it means that access to memory by bytes is no | |
981 | better than access by words when possible, so grab a whole word | |
982 | and maybe make use of that. */ | |
983 | #define SLOW_BYTE_ACCESS 0 | |
984 | ||
985 | /* Define this macro if it is as good or better to call a constant | |
986 | function address than to call an address kept in a register. */ | |
987 | /* On the ARC, calling through registers is slow. */ | |
1e8552c2 | 988 | #define NO_FUNCTION_CSE 1 |
526b7aee SV |
989 | |
990 | /* Section selection. */ | |
991 | /* WARNING: These section names also appear in dwarfout.c. */ | |
992 | ||
993 | #define TEXT_SECTION_ASM_OP "\t.section\t.text" | |
994 | #define DATA_SECTION_ASM_OP "\t.section\t.data" | |
995 | ||
996 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
997 | #define SDATA_SECTION_ASM_OP "\t.section\t.sdata" | |
998 | #define SBSS_SECTION_ASM_OP "\t.section\t.sbss" | |
999 | ||
1000 | /* Expression whose value is a string, including spacing, containing the | |
1001 | assembler operation to identify the following data as initialization/termination | |
1002 | code. If not defined, GCC will assume such a section does not exist. */ | |
1003 | #define INIT_SECTION_ASM_OP "\t.section\t.init" | |
1004 | #define FINI_SECTION_ASM_OP "\t.section\t.fini" | |
1005 | ||
1006 | /* Define this macro if jump tables (for tablejump insns) should be | |
1007 | output in the text section, along with the assembler instructions. | |
1008 | Otherwise, the readonly data section is used. | |
1009 | This macro is irrelevant if there is no separate readonly data section. */ | |
1010 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE) | |
1011 | ||
1012 | /* For DWARF. Marginally different than default so output is "prettier" | |
1013 | (and consistent with above). */ | |
1014 | #define PUSHSECTION_FORMAT "\t%s %s\n" | |
1015 | ||
1016 | /* Tell crtstuff.c we're using ELF. */ | |
1017 | #define OBJECT_FORMAT_ELF | |
1018 | ||
1019 | /* PIC */ | |
1020 | ||
1021 | /* The register number of the register used to address a table of static | |
1022 | data addresses in memory. In some cases this register is defined by a | |
1023 | processor's ``application binary interface'' (ABI). When this macro | |
1024 | is defined, RTL is generated for this register once, as with the stack | |
1025 | pointer and frame pointer registers. If this macro is not defined, it | |
1026 | is up to the machine-dependent files to allocate such a register (if | |
1027 | necessary). */ | |
1028 | #define PIC_OFFSET_TABLE_REGNUM 26 | |
1029 | ||
1030 | /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
1031 | clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
1032 | is not defined. */ | |
1033 | /* This register is call-saved on the ARC. */ | |
1034 | /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
1035 | ||
1036 | /* A C expression that is nonzero if X is a legitimate immediate | |
1037 | operand on the target machine when generating position independent code. | |
1038 | You can assume that X satisfies CONSTANT_P, so you need not | |
1039 | check this. You can also assume `flag_pic' is true, so you need not | |
1040 | check it either. You need not define this macro if all constants | |
1041 | (including SYMBOL_REF) can be immediate operands when generating | |
1042 | position independent code. */ | |
b6c354eb CZ |
1043 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1044 | (!arc_raw_symbolic_reference_mentioned_p ((X), true)) | |
526b7aee SV |
1045 | |
1046 | /* PIC and small data don't mix on ARC because they use the same register. */ | |
1047 | #define SDATA_BASE_REGNUM 26 | |
1048 | ||
1049 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
1050 | (flag_pic \ | |
1051 | ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
1052 | : DW_EH_PE_absptr) | |
1053 | ||
1054 | /* Control the assembler format that we output. */ | |
1055 | ||
1056 | /* A C string constant describing how to begin a comment in the target | |
1057 | assembler language. The compiler assumes that the comment will | |
1058 | end at the end of the line. */ | |
1059 | /* Gas needs this to be "#" in order to recognize line directives. */ | |
1060 | #define ASM_COMMENT_START "#" | |
1061 | ||
1062 | /* Output to assembler file text saying following lines | |
1063 | may contain character constants, extra white space, comments, etc. */ | |
fad92291 | 1064 | #undef ASM_APP_ON |
526b7aee SV |
1065 | #define ASM_APP_ON "" |
1066 | ||
1067 | /* Output to assembler file text saying following lines | |
1068 | no longer contain unusual constructs. */ | |
fad92291 | 1069 | #undef ASM_APP_OFF |
526b7aee SV |
1070 | #define ASM_APP_OFF "" |
1071 | ||
1072 | /* Globalizing directive for a label. */ | |
1073 | #define GLOBAL_ASM_OP "\t.global\t" | |
1074 | ||
1075 | /* This is how to output an assembler line defining a `char' constant. */ | |
1076 | #define ASM_OUTPUT_CHAR(FILE, VALUE) \ | |
1077 | ( fprintf (FILE, "\t.byte\t"), \ | |
1078 | output_addr_const (FILE, (VALUE)), \ | |
1079 | fprintf (FILE, "\n")) | |
1080 | ||
1081 | /* This is how to output an assembler line defining a `short' constant. */ | |
1082 | #define ASM_OUTPUT_SHORT(FILE, VALUE) \ | |
1083 | ( fprintf (FILE, "\t.hword\t"), \ | |
1084 | output_addr_const (FILE, (VALUE)), \ | |
1085 | fprintf (FILE, "\n")) | |
1086 | ||
1087 | /* This is how to output an assembler line defining an `int' constant. | |
1088 | We also handle symbol output here. Code addresses must be right shifted | |
1089 | by 2 because that's how the jump instruction wants them. */ | |
1090 | #define ASM_OUTPUT_INT(FILE, VALUE) \ | |
1091 | do { \ | |
1092 | fprintf (FILE, "\t.word\t"); \ | |
1093 | if (GET_CODE (VALUE) == LABEL_REF) \ | |
1094 | { \ | |
1095 | fprintf (FILE, "%%st(@"); \ | |
1096 | output_addr_const (FILE, (VALUE)); \ | |
1097 | fprintf (FILE, ")"); \ | |
1098 | } \ | |
1099 | else \ | |
1100 | output_addr_const (FILE, (VALUE)); \ | |
1101 | fprintf (FILE, "\n"); \ | |
1102 | } while (0) | |
1103 | ||
1104 | /* This is how to output an assembler line defining a `float' constant. */ | |
1105 | #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ | |
1106 | { \ | |
1107 | long t; \ | |
1108 | char str[30]; \ | |
1109 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
1110 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
1111 | fprintf (FILE, "\t.word\t0x%lx %s %s\n", \ | |
1112 | t, ASM_COMMENT_START, str); \ | |
1113 | } | |
1114 | ||
1115 | /* This is how to output an assembler line defining a `double' constant. */ | |
1116 | #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ | |
1117 | { \ | |
1118 | long t[2]; \ | |
1119 | char str[30]; \ | |
1120 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
1121 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
1122 | fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \ | |
1123 | t[0], ASM_COMMENT_START, str, t[1]); \ | |
1124 | } | |
1125 | ||
1126 | /* This is how to output the definition of a user-level label named NAME, | |
1127 | such as the label on a static function or variable NAME. */ | |
1128 | #define ASM_OUTPUT_LABEL(FILE, NAME) \ | |
1129 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1130 | ||
1131 | #define ASM_NAME_P(NAME) ( NAME[0]=='*') | |
1132 | ||
1133 | /* This is how to output a reference to a user-level label named NAME. | |
1134 | `assemble_name' uses this. */ | |
1135 | /* We work around a dwarfout.c deficiency by watching for labels from it and | |
1136 | not adding the '_' prefix. There is a comment in | |
1137 | dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */ | |
1138 | #define ASM_OUTPUT_LABELREF(FILE, NAME1) \ | |
1139 | do { \ | |
1140 | const char *NAME; \ | |
1141 | NAME = (*targetm.strip_name_encoding)(NAME1); \ | |
1142 | if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ | |
1143 | fprintf (FILE, "%s", NAME); \ | |
1144 | else \ | |
1145 | { \ | |
1146 | if (!ASM_NAME_P (NAME1)) \ | |
1147 | fprintf (FILE, "%s", user_label_prefix); \ | |
1148 | fprintf (FILE, "%s", NAME); \ | |
1149 | } \ | |
1150 | } while (0) | |
1151 | ||
1152 | /* This is how to output a reference to a symbol_ref / label_ref as | |
1153 | (part of) an operand. To disambiguate from register names like | |
1154 | a1 / a2 / status etc, symbols are preceded by '@'. */ | |
1155 | #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ | |
1156 | ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0)) | |
1157 | #define ASM_OUTPUT_LABEL_REF(FILE,STR) \ | |
1158 | do \ | |
1159 | { \ | |
1160 | fputc ('@', file); \ | |
1161 | assemble_name ((FILE), (STR)); \ | |
1162 | } \ | |
1163 | while (0) | |
1164 | ||
1165 | /* Store in OUTPUT a string (made with alloca) containing | |
1166 | an assembler-name for a local static variable named NAME. | |
1167 | LABELNO is an integer which is different for each call. */ | |
1168 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1169 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1170 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1171 | ||
1172 | /* The following macro defines the format used to output the second | |
1173 | operand of the .type assembler directive. Different svr4 assemblers | |
1174 | expect various different forms for this operand. The one given here | |
1175 | is just a default. You may need to override it in your machine- | |
1176 | specific tm.h file (depending upon the particulars of your assembler). */ | |
1177 | ||
1178 | #undef TYPE_OPERAND_FMT | |
1179 | #define TYPE_OPERAND_FMT "@%s" | |
1180 | ||
1181 | /* A C string containing the appropriate assembler directive to | |
1182 | specify the size of a symbol, without any arguments. On systems | |
1183 | that use ELF, the default (in `config/elfos.h') is `"\t.size\t"'; | |
1184 | on other systems, the default is not to define this macro. */ | |
1185 | #undef SIZE_ASM_OP | |
1186 | #define SIZE_ASM_OP "\t.size\t" | |
1187 | ||
1188 | /* Assembler pseudo-op to equate one value with another. */ | |
1189 | /* ??? This is needed because dwarfout.c provides a default definition too | |
1190 | late for defaults.h (which contains the default definition of ASM_OTPUT_DEF | |
1191 | that we use). */ | |
1192 | #ifdef SET_ASM_OP | |
1193 | #undef SET_ASM_OP | |
1194 | #endif | |
1195 | #define SET_ASM_OP "\t.set\t" | |
1196 | ||
f50bb868 | 1197 | extern char rname29[], rname30[]; |
526b7aee SV |
1198 | extern char rname56[], rname57[], rname58[], rname59[]; |
1199 | /* How to refer to registers in assembler output. | |
1200 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1201 | #define REGISTER_NAMES \ | |
1202 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1203 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
1204 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
f50bb868 | 1205 | "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ |
526b7aee SV |
1206 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ |
1207 | "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ | |
1208 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
1209 | rname56,rname57,rname58,rname59,"lp_count", "cc", "ap", "pcl", \ | |
1210 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \ | |
1211 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \ | |
1212 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \ | |
1213 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \ | |
1214 | "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \ | |
1215 | "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \ | |
1216 | "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \ | |
1217 | "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \ | |
1218 | "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ | |
1219 | "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ | |
1220 | "lp_start", "lp_end" \ | |
1221 | } | |
1222 | ||
0a98ae06 CZ |
1223 | #define ADDITIONAL_REGISTER_NAMES \ |
1224 | { \ | |
1225 | {"ilink", 29}, \ | |
1226 | {"r29", 29}, \ | |
1227 | {"r30", 30} \ | |
1228 | } | |
1229 | ||
526b7aee SV |
1230 | /* Entry to the insn conditionalizer. */ |
1231 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
1232 | arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
1233 | ||
1234 | /* A C expression which evaluates to true if CODE is a valid | |
1235 | punctuation character for use in the `PRINT_OPERAND' macro. */ | |
1236 | extern char arc_punct_chars[]; | |
1237 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1238 | arc_punct_chars[(unsigned char) (CHAR)] | |
1239 | ||
1240 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1241 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1242 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1243 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1244 | arc_print_operand (FILE, X, CODE) | |
1245 | ||
1246 | /* A C compound statement to output to stdio stream STREAM the | |
1247 | assembler syntax for an instruction operand that is a memory | |
1248 | reference whose address is ADDR. ADDR is an RTL expression. | |
1249 | ||
1250 | On some machines, the syntax for a symbolic address depends on | |
1251 | the section that the address refers to. On these machines, | |
1252 | define the macro `ENCODE_SECTION_INFO' to store the information | |
1253 | into the `symbol_ref', and then check for it here. */ | |
1254 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1255 | arc_print_operand_address (FILE, ADDR) | |
1256 | ||
1257 | /* This is how to output an element of a case-vector that is absolute. */ | |
1258 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1259 | do { \ | |
1260 | char label[30]; \ | |
1261 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1262 | fprintf (FILE, "\t.word "); \ | |
1263 | assemble_name (FILE, label); \ | |
1264 | fprintf(FILE, "\n"); \ | |
1265 | } while (0) | |
1266 | ||
1267 | /* This is how to output an element of a case-vector that is relative. */ | |
1268 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1269 | do { \ | |
1270 | char label[30]; \ | |
1271 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1272 | switch (GET_MODE (BODY)) \ | |
1273 | { \ | |
4e10a5a7 RS |
1274 | case E_QImode: fprintf (FILE, "\t.byte "); break; \ |
1275 | case E_HImode: fprintf (FILE, "\t.hword "); break; \ | |
1276 | case E_SImode: fprintf (FILE, "\t.word "); break; \ | |
526b7aee SV |
1277 | default: gcc_unreachable (); \ |
1278 | } \ | |
1279 | assemble_name (FILE, label); \ | |
1280 | fprintf (FILE, "-"); \ | |
1281 | ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
1282 | assemble_name (FILE, label); \ | |
1283 | if (TARGET_COMPACT_CASESI) \ | |
1284 | fprintf (FILE, " + %d", 4 + arc_get_unalign ()); \ | |
1285 | fprintf(FILE, "\n"); \ | |
1286 | } while (0) | |
1287 | ||
1288 | /* ADDR_DIFF_VECs are in the text section and thus can affect the | |
1289 | current alignment. */ | |
1290 | #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
1291 | do \ | |
1292 | { \ | |
1293 | if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \ | |
1294 | && ((GET_MODE_SIZE (GET_MODE (PATTERN (JUMPTABLE))) \ | |
1295 | * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \ | |
1296 | & 2)) \ | |
1297 | arc_toggle_unalign (); \ | |
1298 | } \ | |
1299 | while (0) | |
1300 | ||
1301 | #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0) | |
1302 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ | |
1303 | (JUMP_ALIGN(LABEL) \ | |
1304 | ? JUMP_ALIGN(LABEL) \ | |
1305 | : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ | |
1306 | ? 1 : 0) | |
1307 | /* The desired alignment for the location counter at the beginning | |
1308 | of a loop. */ | |
1309 | /* On the ARC, align loops to 4 byte boundaries unless doing all-out size | |
1310 | optimization. */ | |
a2de90a4 | 1311 | #define LOOP_ALIGN(X) 0 |
526b7aee SV |
1312 | |
1313 | #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL)) | |
1314 | ||
1315 | /* This is how to output an assembler line | |
1316 | that says to advance the location counter | |
1317 | to a multiple of 2**LOG bytes. */ | |
1318 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1319 | do { \ | |
1320 | if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
1321 | if ((LOG) > 1) \ | |
1322 | arc_clear_unalign (); \ | |
1323 | } while (0) | |
1324 | ||
1325 | /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT) | |
1326 | Define this macro when you need to see the variable's decl in order to | |
1327 | chose what to output. */ | |
1328 | #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ | |
1329 | arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) | |
1330 | ||
526b7aee SV |
1331 | /* Debugging information. */ |
1332 | ||
1333 | /* Generate DBX and DWARF debugging information. */ | |
1334 | #ifdef DBX_DEBUGGING_INFO | |
1335 | #undef DBX_DEBUGGING_INFO | |
1336 | #endif | |
1337 | #define DBX_DEBUGGING_INFO | |
1338 | ||
1339 | #ifdef DWARF2_DEBUGGING_INFO | |
1340 | #undef DWARF2_DEBUGGING_INFO | |
1341 | #endif | |
1342 | #define DWARF2_DEBUGGING_INFO | |
1343 | ||
1344 | /* Prefer STABS (for now). */ | |
1345 | #undef PREFERRED_DEBUGGING_TYPE | |
1346 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1347 | ||
1348 | /* How to renumber registers for dbx and gdb. */ | |
1349 | #define DBX_REGISTER_NUMBER(REGNO) \ | |
1350 | ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ | |
1351 | ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ | |
1352 | : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \ | |
1353 | ? ((REGNO) == 57 \ | |
1354 | ? 58 /* MMED */ \ | |
1355 | : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \ | |
1356 | ? 59 /* MHI */ \ | |
1357 | : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ | |
1358 | : (REGNO)) | |
1359 | ||
1360 | #define DWARF_FRAME_REGNUM(REG) (REG) | |
1361 | ||
1362 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31) | |
1363 | ||
1364 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31) | |
1365 | ||
1366 | /* Frame info. */ | |
1367 | ||
6fe5e235 CZ |
1368 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) |
1369 | ||
1370 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
1371 | ||
1372 | #define EH_RETURN_HANDLER_RTX arc_eh_return_address_location () | |
526b7aee SV |
1373 | |
1374 | /* Turn off splitting of long stabs. */ | |
1375 | #define DBX_CONTIN_LENGTH 0 | |
1376 | ||
1377 | /* Miscellaneous. */ | |
1378 | ||
1379 | /* Specify the machine mode that this machine uses | |
1380 | for the index in the tablejump instruction. | |
1381 | If we have pc relative case vectors, we start the case vector shortening | |
1382 | with QImode. */ | |
1383 | #define CASE_VECTOR_MODE \ | |
1384 | ((optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode) | |
1385 | ||
1386 | /* Define as C expression which evaluates to nonzero if the tablejump | |
1387 | instruction expects the table to contain offsets from the address of the | |
1388 | table. | |
1389 | Do not define this if the table should contain absolute addresses. */ | |
1390 | #define CASE_VECTOR_PC_RELATIVE TARGET_CASE_VECTOR_PC_RELATIVE | |
1391 | ||
1392 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ | |
1393 | CASE_VECTOR_SHORTEN_MODE_1 \ | |
1394 | (MIN_OFFSET, TARGET_COMPACT_CASESI ? MAX_OFFSET + 6 : MAX_OFFSET, BODY) | |
1395 | ||
1396 | #define CASE_VECTOR_SHORTEN_MODE_1(MIN_OFFSET, MAX_OFFSET, BODY) \ | |
1397 | ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ | |
1398 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
1399 | : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \ | |
1400 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ | |
1401 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \ | |
1402 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \ | |
1403 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \ | |
1404 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \ | |
1405 | : SImode) | |
1406 | ||
1407 | #define ADDR_VEC_ALIGN(VEC_INSN) \ | |
1408 | (exact_log2 (GET_MODE_SIZE (GET_MODE (PATTERN (VEC_INSN))))) | |
1409 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
1410 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ | |
9739c3d3 | 1411 | ASM_OUTPUT_ALIGN ((FILE), ADDR_VEC_ALIGN (TABLE)) |
526b7aee | 1412 | |
d4fe8839 CZ |
1413 | #define INSN_LENGTH_ALIGNMENT(INSN) \ |
1414 | ((JUMP_TABLE_DATA_P (INSN) \ | |
526b7aee | 1415 | && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \ |
d4fe8839 | 1416 | && GET_MODE (PATTERN (INSN)) == QImode) \ |
526b7aee SV |
1417 | ? 0 : length_unit_log) |
1418 | ||
1419 | /* Define if operations between registers always perform the operation | |
1420 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1421 | #define WORD_REGISTER_OPERATIONS 1 |
526b7aee SV |
1422 | |
1423 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1424 | will either zero-extend or sign-extend. The value of this macro should | |
1425 | be the code that says which one of the two operations is implicitly | |
1426 | done, NIL if none. */ | |
1427 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1428 | ||
1429 | ||
1430 | /* Max number of bytes we can move from memory to memory | |
1431 | in one reasonably fast instruction. */ | |
1432 | #define MOVE_MAX 4 | |
1433 | ||
526b7aee SV |
1434 | /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */ |
1435 | #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3) | |
1436 | ||
491483b0 CZ |
1437 | /* Define this to be nonzero if shift instructions ignore all but the |
1438 | low-order few bits. | |
526b7aee | 1439 | */ |
491483b0 | 1440 | #define SHIFT_COUNT_TRUNCATED 1 |
526b7aee | 1441 | |
526b7aee SV |
1442 | /* We assume that the store-condition-codes instructions store 0 for false |
1443 | and some other value for true. This is the value stored for true. */ | |
1444 | #define STORE_FLAG_VALUE 1 | |
1445 | ||
1446 | /* Specify the machine mode that pointers have. | |
1447 | After generation of rtl, the compiler makes no further distinction | |
1448 | between pointers and any other objects of this machine mode. */ | |
1449 | /* ARCompact has full 32-bit pointers. */ | |
1450 | #define Pmode SImode | |
1451 | ||
1452 | /* A function address in a call instruction. */ | |
1453 | #define FUNCTION_MODE SImode | |
1454 | ||
1455 | /* Define the information needed to generate branch and scc insns. This is | |
1456 | stored from the compare operation. Note that we can't use "rtx" here | |
1457 | since it hasn't been defined! */ | |
1458 | extern struct rtx_def *arc_compare_op0, *arc_compare_op1; | |
1459 | ||
1460 | /* ARC function types. */ | |
1461 | enum arc_function_type { | |
1825c61e CZ |
1462 | /* No function should have the unknown type. This value is used to |
1463 | indicate the that function type has not yet been computed. */ | |
1464 | ARC_FUNCTION_UNKNOWN = 0, | |
1465 | ||
1466 | /* The normal function type indicates that the function has the | |
1467 | standard prologue and epilogue. */ | |
1468 | ARC_FUNCTION_NORMAL = 1 << 0, | |
526b7aee SV |
1469 | /* These are interrupt handlers. The name corresponds to the register |
1470 | name that contains the return address. */ | |
1825c61e CZ |
1471 | ARC_FUNCTION_ILINK1 = 1 << 1, |
1472 | ARC_FUNCTION_ILINK2 = 1 << 2, | |
c7314bc1 | 1473 | /* Fast interrupt is only available on ARCv2 processors. */ |
1825c61e CZ |
1474 | ARC_FUNCTION_FIRQ = 1 << 3, |
1475 | /* The naked function type indicates that the function does not have | |
1476 | prologue or epilogue, and that no stack frame is available. */ | |
1477 | ARC_FUNCTION_NAKED = 1 << 4 | |
526b7aee | 1478 | }; |
c7314bc1 | 1479 | |
1825c61e CZ |
1480 | /* Check if a function is an interrupt function. */ |
1481 | #define ARC_INTERRUPT_P(TYPE) \ | |
1482 | (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \ | |
1483 | | ARC_FUNCTION_FIRQ)) != 0) | |
1484 | ||
1485 | /* Check if a function is a fast interrupt function. */ | |
1486 | #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0) | |
1487 | ||
1488 | /* Check if a function is normal, that is, has standard prologue and | |
1489 | epilogue. */ | |
1490 | #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0) | |
526b7aee | 1491 | |
1825c61e CZ |
1492 | /* Check if a function is naked. */ |
1493 | #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0) | |
526b7aee SV |
1494 | |
1495 | /* Called by crtstuff.c to make calls to function FUNCTION that are defined in | |
1496 | SECTION_OP, and then to switch back to text section. */ | |
1497 | #undef CRT_CALL_STATIC_FUNCTION | |
19b250c4 CZ |
1498 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
1499 | asm (SECTION_OP "\n\t" \ | |
1500 | "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \ | |
1501 | "jl [r12]\n" \ | |
1502 | TEXT_SECTION_ASM_OP); | |
526b7aee SV |
1503 | |
1504 | /* This macro expands to the name of the scratch register r12, used for | |
1505 | temporary calculations according to the ABI. */ | |
1506 | #define ARC_TEMP_SCRATCH_REG "r12" | |
1507 | ||
1508 | /* The C++ compiler must use one bit to indicate whether the function | |
1509 | that will be called through a pointer-to-member-function is | |
1510 | virtual. Normally, we assume that the low-order bit of a function | |
1511 | pointer must always be zero. Then, by ensuring that the | |
1512 | vtable_index is odd, we can distinguish which variant of the union | |
1513 | is in use. But, on some platforms function pointers can be odd, | |
1514 | and so this doesn't work. In that case, we use the low-order bit | |
1515 | of the `delta' field, and shift the remainder of the `delta' field | |
1516 | to the left. We needed to do this for A4 because the address was always | |
1517 | shifted and thus could be odd. */ | |
1518 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ | |
1519 | (ptrmemfunc_vbit_in_pfn) | |
1520 | ||
1521 | #define INSN_SETS_ARE_DELAYED(X) \ | |
1522 | (GET_CODE (X) == INSN \ | |
1523 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1524 | && GET_CODE (PATTERN (X)) != USE \ | |
1525 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1526 | && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC)) | |
1527 | ||
28633bbd | 1528 | #define INSN_REFERENCES_ARE_DELAYED(insn) \ |
5a5c5784 | 1529 | (INSN_SETS_ARE_DELAYED (insn)) |
526b7aee SV |
1530 | |
1531 | #define CALL_ATTR(X, NAME) \ | |
1532 | ((CALL_P (X) || NONJUMP_INSN_P (X)) \ | |
1533 | && GET_CODE (PATTERN (X)) != USE \ | |
1534 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1535 | && get_attr_is_##NAME (X) == IS_##NAME##_YES) \ | |
1536 | ||
8f3304d0 CZ |
1537 | #define REVERSE_CONDITION(CODE,MODE) \ |
1538 | (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ | |
1539 | || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ | |
1540 | || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ | |
1541 | || (MODE) == CC_FPUmode) \ | |
1542 | ? reverse_condition_maybe_unordered ((CODE)) \ | |
1543 | : reverse_condition ((CODE))) | |
526b7aee SV |
1544 | |
1545 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
1546 | ((LENGTH) \ | |
1547 | = (GET_CODE (PATTERN (X)) == SEQUENCE \ | |
1548 | ? ((LENGTH) \ | |
84034c69 DM |
1549 | + arc_adjust_insn_length ( \ |
1550 | as_a <rtx_sequence *> (PATTERN (X))->insn (0), \ | |
1551 | get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \ | |
1552 | true) \ | |
1553 | - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \ | |
1554 | + arc_adjust_insn_length ( \ | |
1555 | as_a <rtx_sequence *> (PATTERN (X))->insn (1), \ | |
1556 | get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \ | |
1557 | true) \ | |
1558 | - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \ | |
526b7aee SV |
1559 | : arc_adjust_insn_length ((X), (LENGTH), false))) |
1560 | ||
1561 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`') | |
1562 | ||
1563 | #define INIT_EXPANDERS arc_init_expanders () | |
1564 | ||
526b7aee SV |
1565 | enum |
1566 | { | |
1567 | ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT | |
1568 | }; | |
1569 | ||
1570 | /* The define_cond_exec construct is rather crude, as we can't have | |
1571 | different ones with different conditions apply to different sets | |
1572 | of instructions. We can't use an attribute test inside the condition, | |
1573 | because that would lead to infinite recursion as the attribute test | |
1574 | needs to recognize the insn. So, instead we have a clause for | |
1575 | the pattern condition of all sfunc patterns which is only relevant for | |
1576 | the predicated varaint. */ | |
1577 | #define SFUNC_CHECK_PREDICABLE \ | |
1578 | (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS) | |
1579 | ||
f50bb868 CZ |
1580 | /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */ |
1581 | #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2) | |
1582 | /* Full ARCv2 multiplication feature macro. */ | |
1583 | #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2) | |
1584 | /* General MPY feature macro. */ | |
1585 | #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI) | |
1586 | /* ARC700 MPY feature macro. */ | |
1587 | #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET)) | |
1588 | /* Any multiplication feature macro. */ | |
1589 | #define TARGET_ANY_MPY \ | |
1590 | (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET) | |
00c072ae CZ |
1591 | /* PLUS_DMPY feature macro. */ |
1592 | #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS) | |
1593 | /* PLUS_MACD feature macro. */ | |
1594 | #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS) | |
1595 | /* PLUS_QMACW feature macro. */ | |
1596 | #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS) | |
f50bb868 CZ |
1597 | |
1598 | /* ARC600 and ARC601 feature macro. */ | |
1599 | #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601) | |
1600 | /* ARC600, ARC601 and ARC700 feature macro. */ | |
1601 | #define TARGET_ARCOMPACT_FAMILY \ | |
1602 | (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700) | |
1603 | /* Loop count register can be read in very next instruction after has | |
1604 | been written to by an ordinary instruction. */ | |
1605 | #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY) | |
1606 | ||
8f3304d0 CZ |
1607 | /* FPU defines. */ |
1608 | /* Any FPU support. */ | |
c4014855 | 1609 | #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0) |
8f3304d0 CZ |
1610 | /* Single precision floating point support. */ |
1611 | #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0) | |
1612 | /* Double precision floating point support. */ | |
1613 | #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0) | |
1614 | /* Single precision floating point support with fused operation. */ | |
1615 | #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0) | |
1616 | /* Double precision floating point support with fused operation. */ | |
1617 | #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0) | |
1618 | /* Single precision floating point conversion instruction support. */ | |
1619 | #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0) | |
1620 | /* Double precision floating point conversion instruction support. */ | |
1621 | #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0) | |
1622 | /* Single precision floating point SQRT/DIV instruction support. */ | |
1623 | #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0) | |
1624 | /* Double precision floating point SQRT/DIV instruction support. */ | |
1625 | #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0) | |
1626 | /* Double precision floating point assist instruction support. */ | |
1627 | #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0) | |
c4014855 CZ |
1628 | /* Custom FP instructions used by QuarkSE EM cpu. */ |
1629 | #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \ | |
1630 | && (arc_fpu_build == FPX_QK)) | |
8f3304d0 | 1631 | |
526b7aee | 1632 | #endif /* GCC_ARC_H */ |