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526b7aee | 1 | ;; Predicate definitions for Synopsys DesignWare ARC. |
a5544970 | 2 | ;; Copyright (C) 2007-2019 Free Software Foundation, Inc. |
526b7aee SV |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_predicate "dest_reg_operand" | |
21 | (match_code "reg,subreg") | |
22 | { | |
526b7aee SV |
23 | return register_operand (op, mode); |
24 | }) | |
25 | ||
26 | (define_predicate "mpy_dest_reg_operand" | |
27 | (match_code "reg,subreg") | |
28 | { | |
526b7aee SV |
29 | return register_operand (op, mode); |
30 | }) | |
31 | ||
32 | ||
33 | ;; Returns 1 if OP is a symbol reference. | |
34 | (define_predicate "symbolic_operand" | |
35 | (match_code "symbol_ref, label_ref, const") | |
36 | ) | |
37 | ||
38 | ;; Acceptable arguments to the call insn. | |
39 | (define_predicate "call_address_operand" | |
40 | (ior (match_code "const_int, reg") | |
41 | (match_operand 0 "symbolic_operand") | |
42 | (match_test "CONSTANT_P (op) | |
43 | && arc_legitimate_constant_p (VOIDmode, op)")) | |
44 | ) | |
45 | ||
46 | (define_predicate "call_operand" | |
47 | (and (match_code "mem") | |
48 | (match_test "call_address_operand (XEXP (op, 0), mode)")) | |
49 | ) | |
50 | ||
51 | ;; Return true if OP is a unsigned 6-bit immediate (u6) value. | |
52 | (define_predicate "u6_immediate_operand" | |
53 | (and (match_code "const_int") | |
54 | (match_test "UNSIGNED_INT6 (INTVAL (op))")) | |
55 | ) | |
56 | ||
57 | ;; Return true if OP is a short immediate (shimm) value. | |
58 | (define_predicate "short_immediate_operand" | |
59 | (and (match_code "const_int") | |
60 | (match_test "SMALL_INT (INTVAL (op))")) | |
61 | ) | |
62 | ||
63 | (define_predicate "p2_immediate_operand" | |
64 | (and (match_code "const_int") | |
65 | (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0") | |
66 | (match_test "INTVAL (op)")) | |
67 | ) | |
68 | ||
69 | ;; Return true if OP will require a long immediate (limm) value. | |
70 | ;; This is currently only used when calculating length attributes. | |
71 | (define_predicate "long_immediate_operand" | |
72 | (match_code "symbol_ref, label_ref, const, const_double, const_int") | |
73 | { | |
74 | switch (GET_CODE (op)) | |
75 | { | |
76 | case SYMBOL_REF : | |
77 | case LABEL_REF : | |
78 | case CONST : | |
79 | return 1; | |
80 | case CONST_INT : | |
81 | return !SIGNED_INT12 (INTVAL (op)); | |
82 | case CONST_DOUBLE : | |
83 | /* These can happen because large unsigned 32 bit constants are | |
84 | represented this way (the multiplication patterns can cause these | |
85 | to be generated). They also occur for SFmode values. */ | |
86 | return 1; | |
87 | default: | |
88 | break; | |
89 | } | |
90 | return 0; | |
91 | } | |
92 | ) | |
93 | ||
94 | ;; Return true if OP is a MEM that when used as a load or store address will | |
95 | ;; require an 8 byte insn. | |
96 | ;; Load and store instructions don't allow the same possibilities but they're | |
97 | ;; similar enough that this one function will do. | |
98 | ;; This is currently only used when calculating length attributes. */ | |
99 | (define_predicate "long_immediate_loadstore_operand" | |
100 | (match_code "mem") | |
101 | { | |
102 | int size = GET_MODE_SIZE (GET_MODE (op)); | |
103 | ||
104 | op = XEXP (op, 0); | |
4d03dc2f JR |
105 | if (TARGET_NPS_CMEM && cmem_address (op, SImode)) |
106 | return 0; | |
526b7aee SV |
107 | switch (GET_CODE (op)) |
108 | { | |
109 | case SYMBOL_REF : | |
110 | case LABEL_REF : | |
111 | case CONST : | |
112 | return 1; | |
113 | case CONST_INT : | |
114 | /* This must be handled as "st c,[limm]". Ditto for load. | |
115 | Technically, the assembler could translate some possibilities to | |
116 | "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't | |
117 | assume that it does. */ | |
118 | return 1; | |
119 | case CONST_DOUBLE : | |
120 | /* These can happen because large unsigned 32 bit constants are | |
121 | represented this way (the multiplication patterns can cause these | |
122 | to be generated). They also occur for SFmode values. */ | |
123 | return 1; | |
124 | case REG : | |
125 | return 0; | |
126 | case PLUS : | |
127 | { | |
128 | rtx x = XEXP (op, 1); | |
129 | ||
ac255185 CZ |
130 | if ((GET_CODE (XEXP (op, 0)) == MULT) |
131 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
132 | && CONSTANT_P (x)) | |
133 | return 1; | |
134 | ||
526b7aee SV |
135 | if (GET_CODE (x) == CONST) |
136 | { | |
137 | x = XEXP (x, 0); | |
138 | if (GET_CODE (x) == PLUS) | |
139 | x = XEXP (x, 0); | |
140 | } | |
141 | if (CONST_INT_P (x)) | |
142 | return (!SMALL_INT (INTVAL (x)) | |
143 | && (size <= 1 || size > 4 | |
144 | || (INTVAL (x) & (size - 1)) != 0 | |
145 | || !SMALL_INT (INTVAL (x) / size))); | |
146 | else if (GET_CODE (x) == SYMBOL_REF) | |
147 | return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x); | |
148 | return 0; | |
149 | } | |
150 | default: | |
151 | break; | |
152 | } | |
153 | return 0; | |
154 | } | |
155 | ) | |
156 | ||
157 | ;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit | |
158 | ;; instructions | |
159 | (define_predicate "compact_register_operand" | |
160 | (match_code "reg, subreg") | |
161 | { | |
162 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
163 | return 0; | |
164 | ||
165 | return (GET_CODE (op) == REG) | |
166 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
167 | || COMPACT_GP_REG_P (REGNO (op))) ; | |
168 | } | |
169 | ) | |
170 | ||
0e03cebd CZ |
171 | (define_predicate "compact_hreg_operand" |
172 | (match_code "reg, subreg") | |
173 | { | |
174 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
175 | return 0; | |
176 | ||
177 | return (GET_CODE (op) == REG) | |
178 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
179 | || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30) | |
180 | || !TARGET_V2); | |
181 | } | |
182 | ) | |
183 | ||
526b7aee SV |
184 | ;; Return true if OP is an acceptable memory operand for ARCompact |
185 | ;; 16-bit store instructions | |
186 | (define_predicate "compact_store_memory_operand" | |
187 | (match_code "mem") | |
188 | { | |
189 | rtx addr, plus0, plus1; | |
190 | int size, off; | |
191 | ||
192 | if (mode == VOIDmode) | |
193 | mode = GET_MODE (op); | |
194 | ||
195 | /* .di instructions have no 16-bit form. */ | |
196 | if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET) | |
197 | return 0; | |
198 | ||
8180c03f CZ |
199 | /* likewise for uncached types. */ |
200 | if (arc_is_uncached_mem_p (op)) | |
201 | return 0; | |
202 | ||
526b7aee SV |
203 | size = GET_MODE_SIZE (mode); |
204 | ||
205 | /* dword operations really put out 2 instructions, so eliminate them. */ | |
206 | if (size > UNITS_PER_WORD) | |
207 | return 0; | |
208 | ||
209 | /* Decode the address now. */ | |
210 | addr = XEXP (op, 0); | |
211 | switch (GET_CODE (addr)) | |
212 | { | |
213 | case REG: | |
214 | return (REGNO (addr) >= FIRST_PSEUDO_REGISTER | |
215 | || COMPACT_GP_REG_P (REGNO (addr)) | |
216 | || (SP_REG_P (REGNO (addr)) && (size != 2))); | |
217 | /* stw_s does not support SP as a parameter. */ | |
218 | case PLUS: | |
219 | plus0 = XEXP (addr, 0); | |
220 | plus1 = XEXP (addr, 1); | |
221 | ||
222 | if ((GET_CODE (plus0) == REG) | |
223 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
224 | || COMPACT_GP_REG_P (REGNO (plus0))) | |
225 | && (GET_CODE (plus1) == CONST_INT)) | |
226 | { | |
227 | off = INTVAL (plus1); | |
228 | ||
229 | /* Negative offset is not supported in 16-bit load/store insns. */ | |
230 | if (off < 0) | |
231 | return 0; | |
232 | ||
233 | switch (size) | |
234 | { | |
235 | case 1: | |
236 | return (off < 32); | |
237 | case 2: | |
238 | return ((off < 64) && (off % 2 == 0)); | |
239 | case 4: | |
240 | return ((off < 128) && (off % 4 == 0)); | |
241 | } | |
242 | } | |
243 | ||
244 | if ((GET_CODE (plus0) == REG) | |
245 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
246 | || SP_REG_P (REGNO (plus0))) | |
247 | && (GET_CODE (plus1) == CONST_INT)) | |
248 | { | |
249 | off = INTVAL (plus1); | |
250 | ||
251 | return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0)); | |
252 | } | |
253 | default: | |
254 | break; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ) | |
259 | ||
260 | ;; Return true if OP is an acceptable argument for a single word | |
261 | ;; move source. | |
262 | (define_predicate "move_src_operand" | |
263 | (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem") | |
264 | { | |
265 | switch (GET_CODE (op)) | |
266 | { | |
267 | case SYMBOL_REF : | |
28633bbd CZ |
268 | if (SYMBOL_REF_TLS_MODEL (op)) |
269 | return 0; | |
3bbe0b82 | 270 | return 1; |
526b7aee | 271 | case LABEL_REF : |
28633bbd | 272 | return 1; |
526b7aee | 273 | case CONST : |
28633bbd | 274 | return arc_legitimate_constant_p (mode, op); |
526b7aee SV |
275 | case CONST_INT : |
276 | return (LARGE_INT (INTVAL (op))); | |
277 | case CONST_DOUBLE : | |
278 | /* We can handle DImode integer constants in SImode if the value | |
279 | (signed or unsigned) will fit in 32 bits. This is needed because | |
280 | large unsigned 32 bit constants are represented as CONST_DOUBLEs. */ | |
281 | if (mode == SImode) | |
282 | return arc_double_limm_p (op); | |
283 | /* We can handle 32 bit floating point constants. */ | |
284 | if (mode == SFmode) | |
285 | return GET_MODE (op) == SFmode; | |
286 | return 0; | |
287 | case REG : | |
288 | return register_operand (op, mode); | |
289 | case SUBREG : | |
290 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
291 | pseudo-reg and is now a stack slot. */ | |
292 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
293 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
294 | else | |
295 | return register_operand (op, mode); | |
296 | case MEM : | |
297 | return address_operand (XEXP (op, 0), mode); | |
298 | default : | |
299 | return 0; | |
300 | } | |
301 | } | |
302 | ) | |
303 | ||
304 | ;; Return true if OP is an acceptable argument for a double word | |
305 | ;; move source. | |
306 | (define_predicate "move_double_src_operand" | |
307 | (match_code "reg, subreg, mem, const_int, const_double") | |
308 | { | |
309 | switch (GET_CODE (op)) | |
310 | { | |
311 | case REG : | |
312 | return register_operand (op, mode); | |
313 | case SUBREG : | |
314 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
315 | pseudo-reg and is now a stack slot. */ | |
316 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
e5dcff3e | 317 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); |
526b7aee SV |
318 | else |
319 | return register_operand (op, mode); | |
320 | case MEM : | |
321 | return address_operand (XEXP (op, 0), mode); | |
322 | case CONST_INT : | |
323 | case CONST_DOUBLE : | |
324 | return 1; | |
325 | default : | |
326 | return 0; | |
327 | } | |
328 | } | |
329 | ) | |
330 | ||
331 | ;; Return true if OP is an acceptable argument for a move destination. | |
332 | (define_predicate "move_dest_operand" | |
333 | (match_code "reg, subreg, mem") | |
334 | { | |
335 | switch (GET_CODE (op)) | |
336 | { | |
337 | case REG : | |
338 | /* Program Counter register cannot be the target of a move. It is | |
339 | a readonly register. */ | |
73dac59b | 340 | if (REGNO (op) == PCL_REG) |
526b7aee SV |
341 | return 0; |
342 | else if (TARGET_MULMAC_32BY16_SET | |
73dac59b | 343 | && (REGNO (op) == MUL32x16_REG || REGNO (op) == R57_REG)) |
526b7aee SV |
344 | return 0; |
345 | else if (TARGET_MUL64_SET | |
73dac59b CZ |
346 | && (REGNO (op) == R57_REG || REGNO (op) == MUL64_OUT_REG |
347 | || REGNO (op) == R59_REG)) | |
526b7aee | 348 | return 0; |
a2de90a4 CZ |
349 | else if (REGNO (op) == LP_COUNT) |
350 | return 1; | |
526b7aee SV |
351 | else |
352 | return dest_reg_operand (op, mode); | |
353 | case SUBREG : | |
354 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
355 | pseudo-reg and is now a stack slot. */ | |
356 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
357 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
358 | else | |
359 | return dest_reg_operand (op, mode); | |
360 | case MEM : | |
361 | { | |
362 | rtx addr = XEXP (op, 0); | |
363 | ||
364 | if (GET_CODE (addr) == PLUS | |
365 | && (GET_CODE (XEXP (addr, 0)) == MULT | |
366 | || (!CONST_INT_P (XEXP (addr, 1)) | |
367 | && (TARGET_NO_SDATA_SET | |
368 | || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF | |
369 | || !SYMBOL_REF_SMALL_P (XEXP (addr, 1)))))) | |
370 | return 0; | |
371 | if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
372 | && (GET_CODE (XEXP (addr, 1)) != PLUS | |
373 | || !CONST_INT_P (XEXP (XEXP (addr, 1), 1)))) | |
374 | return 0; | |
28633bbd CZ |
375 | /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC)) |
376 | constructs are effectively indexed. */ | |
377 | if (flag_pic) | |
378 | { | |
379 | rtx ad0 = addr; | |
380 | while (GET_CODE (ad0) == PLUS) | |
381 | ad0 = XEXP (ad0, 0); | |
382 | if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC) | |
383 | return 0; | |
384 | } | |
526b7aee SV |
385 | return address_operand (addr, mode); |
386 | } | |
387 | default : | |
388 | return 0; | |
389 | } | |
390 | ||
391 | } | |
392 | ) | |
393 | ||
526b7aee SV |
394 | ;; Return true if OP is a non-volatile non-immediate operand. |
395 | ;; Volatile memory refs require a special "cache-bypass" instruction | |
396 | ;; and only the standard movXX patterns are set up to handle them. | |
397 | (define_predicate "nonvol_nonimm_operand" | |
398 | (and (match_code "subreg, reg, mem") | |
8180c03f CZ |
399 | (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)") |
400 | (match_test "!arc_is_uncached_mem_p (op)")) | |
526b7aee SV |
401 | ) |
402 | ||
403 | ;; Return 1 if OP is a comparison operator valid for the mode of CC. | |
404 | ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns. | |
405 | ||
406 | (define_predicate "proper_comparison_operator" | |
407 | (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt") | |
408 | { | |
409 | enum rtx_code code = GET_CODE (op); | |
410 | ||
411 | if (!COMPARISON_P (op)) | |
412 | return 0; | |
413 | ||
414 | /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz . | |
415 | There are some creative uses for hi / ls after shifts, but these are | |
416 | hard to understand for the compiler and could be at best the target of | |
417 | a peephole. */ | |
418 | switch (GET_MODE (XEXP (op, 0))) | |
419 | { | |
4e10a5a7 | 420 | case E_CC_ZNmode: |
526b7aee SV |
421 | return (code == EQ || code == NE || code == GE || code == LT |
422 | || code == GT); | |
4e10a5a7 | 423 | case E_CC_Zmode: |
526b7aee | 424 | return code == EQ || code == NE; |
4e10a5a7 | 425 | case E_CC_Cmode: |
526b7aee | 426 | return code == LTU || code == GEU; |
4e10a5a7 | 427 | case E_CC_FP_GTmode: |
526b7aee | 428 | return code == GT || code == UNLE; |
4e10a5a7 | 429 | case E_CC_FP_GEmode: |
526b7aee | 430 | return code == GE || code == UNLT; |
4e10a5a7 | 431 | case E_CC_FP_ORDmode: |
526b7aee | 432 | return code == ORDERED || code == UNORDERED; |
4e10a5a7 | 433 | case E_CC_FP_UNEQmode: |
526b7aee | 434 | return code == UNEQ || code == LTGT; |
4e10a5a7 | 435 | case E_CC_FPXmode: |
526b7aee SV |
436 | return (code == EQ || code == NE || code == UNEQ || code == LTGT |
437 | || code == ORDERED || code == UNORDERED); | |
438 | ||
4e10a5a7 | 439 | case E_CC_FPUmode: |
8f3304d0 | 440 | return 1; |
4e10a5a7 | 441 | case E_CC_FPU_UNEQmode: |
8f3304d0 CZ |
442 | return 1; |
443 | ||
4e10a5a7 RS |
444 | case E_CCmode: |
445 | case E_SImode: /* Used for BRcc. */ | |
526b7aee SV |
446 | return 1; |
447 | /* From combiner. */ | |
4e10a5a7 | 448 | case E_QImode: case E_HImode: case E_DImode: case E_SFmode: case E_DFmode: |
526b7aee | 449 | return 0; |
4e10a5a7 | 450 | case E_VOIDmode: |
dfa654c8 | 451 | return 0; |
526b7aee SV |
452 | default: |
453 | gcc_unreachable (); | |
454 | } | |
455 | }) | |
456 | ||
457 | (define_predicate "equality_comparison_operator" | |
458 | (match_code "eq, ne")) | |
459 | ||
e389ba30 AB |
460 | (define_predicate "ge_lt_comparison_operator" |
461 | (match_code "ge, lt")) | |
462 | ||
526b7aee SV |
463 | (define_predicate "brcc_nolimm_operator" |
464 | (ior (match_test "REG_P (XEXP (op, 1))") | |
465 | (and (match_code "eq, ne, lt, ge, ltu, geu") | |
4173ddaf | 466 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
467 | (match_test "u6_immediate_operand (XEXP (op, 1), SImode)")) |
468 | (and (match_code "le, gt, leu, gtu") | |
4173ddaf | 469 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
470 | (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)")))) |
471 | ||
472 | ;; Return TRUE if this is the condition code register, if we aren't given | |
473 | ;; a mode, accept any CCmode register | |
474 | (define_special_predicate "cc_register" | |
475 | (match_code "reg") | |
476 | { | |
477 | if (mode == VOIDmode) | |
478 | { | |
479 | mode = GET_MODE (op); | |
480 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
481 | return FALSE; | |
482 | } | |
483 | ||
484 | if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG) | |
485 | return TRUE; | |
486 | ||
487 | return FALSE; | |
488 | }) | |
489 | ||
490 | ;; Return TRUE if this is the condition code register; if we aren't given | |
491 | ;; a mode, accept any CCmode register. If we are given a mode, accept | |
492 | ;; modes that set a subset of flags. | |
493 | (define_special_predicate "cc_set_register" | |
494 | (match_code "reg") | |
495 | { | |
ef4bddc2 | 496 | machine_mode rmode = GET_MODE (op); |
526b7aee SV |
497 | |
498 | if (mode == VOIDmode) | |
499 | { | |
500 | mode = rmode; | |
501 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
502 | return FALSE; | |
503 | } | |
504 | ||
f7ace5d5 | 505 | if (REGNO (op) != CC_REG) |
526b7aee SV |
506 | return FALSE; |
507 | if (mode == rmode | |
508 | || (mode == CC_ZNmode && rmode == CC_Zmode) | |
509 | || (mode == CCmode && rmode == CC_Zmode) | |
510 | || (mode == CCmode && rmode == CC_ZNmode) | |
511 | || (mode == CCmode && rmode == CC_Cmode)) | |
512 | return TRUE; | |
513 | ||
514 | return FALSE; | |
515 | }) | |
516 | ||
517 | ; Accept CC_REG in modes which provide the flags needed for MODE. */ | |
518 | (define_special_predicate "cc_use_register" | |
519 | (match_code "reg") | |
520 | { | |
521 | if (REGNO (op) != CC_REG) | |
522 | return 0; | |
523 | if (GET_MODE (op) == mode) | |
524 | return 1; | |
525 | switch (mode) | |
526 | { | |
4e10a5a7 | 527 | case E_CC_Zmode: |
526b7aee SV |
528 | if (GET_MODE (op) == CC_ZNmode) |
529 | return 1; | |
530 | /* Fall through. */ | |
4e10a5a7 | 531 | case E_CC_ZNmode: case E_CC_Cmode: |
526b7aee SV |
532 | return GET_MODE (op) == CCmode; |
533 | default: | |
534 | gcc_unreachable (); | |
535 | } | |
536 | }) | |
537 | ||
538 | (define_special_predicate "zn_compare_operator" | |
539 | (match_code "compare") | |
540 | { | |
541 | return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode; | |
542 | }) | |
543 | ||
544 | ;; Return true if OP is a shift operator. | |
545 | (define_predicate "shift_operator" | |
546 | (match_code "ashiftrt, lshiftrt, ashift") | |
547 | ) | |
548 | ||
549 | ;; Return true if OP is a left shift operator that can be implemented in | |
550 | ;; four insn words or less without a barrel shifter or multiplier. | |
551 | (define_predicate "shiftl4_operator" | |
552 | (and (match_code "ashift") | |
553 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
554 | (match_test "UINTVAL (XEXP (op, 1)) <= 9U | |
555 | || INTVAL (XEXP (op, 1)) == 29 | |
556 | || INTVAL (XEXP (op, 1)) == 30 | |
557 | || INTVAL (XEXP (op, 1)) == 31"))) | |
558 | ||
559 | ;; Return true if OP is a right shift operator that can be implemented in | |
560 | ;; four insn words or less without a barrel shifter or multiplier. | |
561 | (define_predicate "shiftr4_operator" | |
562 | (and (match_code "ashiftrt, lshiftrt") | |
563 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
564 | (match_test "UINTVAL (XEXP (op, 1)) <= 4U | |
565 | || INTVAL (XEXP (op, 1)) == 30 | |
566 | || INTVAL (XEXP (op, 1)) == 31"))) | |
567 | ||
568 | ;; Return true if OP is a shift operator that can be implemented in | |
569 | ;; four insn words or less without a barrel shifter or multiplier. | |
570 | (define_predicate "shift4_operator" | |
571 | (ior (match_operand 0 "shiftl4_operator") | |
572 | (match_operand 0 "shiftr4_operator"))) | |
573 | ||
574 | (define_predicate "mult_operator" | |
f50bb868 | 575 | (and (match_code "mult") (match_test "TARGET_MPY")) |
526b7aee SV |
576 | ) |
577 | ||
578 | (define_predicate "commutative_operator" | |
579 | (ior (match_code "plus,ior,xor,and") | |
580 | (match_operand 0 "mult_operator") | |
581 | (and (match_code "ss_plus") | |
582 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
583 | ) | |
584 | ||
585 | (define_predicate "commutative_operator_sans_mult" | |
586 | (ior (match_code "plus,ior,xor,and") | |
587 | (and (match_code "ss_plus") | |
588 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
589 | ) | |
590 | ||
591 | (define_predicate "noncommutative_operator" | |
f7ace5d5 CZ |
592 | (ior (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
593 | (match_test "TARGET_BARREL_SHIFTER")) | |
594 | (match_code "minus") | |
526b7aee SV |
595 | (and (match_code "ss_minus") |
596 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
597 | ) | |
598 | ||
599 | (define_predicate "unary_operator" | |
600 | (ior (match_code "abs,neg,not,sign_extend,zero_extend") | |
601 | (and (ior (match_code "ss_neg") | |
602 | (and (match_code "ss_truncate") | |
603 | (match_test "GET_MODE (XEXP (op, 0)) == HImode"))) | |
604 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
605 | ) | |
606 | ||
1e466f04 GM |
607 | (define_predicate "_1_2_3_operand" |
608 | (and (match_code "const_int") | |
609 | (match_test "INTVAL (op) == 1 || INTVAL (op) == 2 || INTVAL (op) == 3")) | |
610 | ) | |
611 | ||
526b7aee SV |
612 | (define_predicate "_2_4_8_operand" |
613 | (and (match_code "const_int") | |
614 | (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8")) | |
615 | ) | |
616 | ||
617 | (define_predicate "arc_double_register_operand" | |
618 | (match_code "reg") | |
619 | { | |
620 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
621 | return 0; | |
622 | ||
623 | return (GET_CODE (op) == REG | |
624 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
625 | || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS)); | |
626 | }) | |
627 | ||
628 | (define_predicate "shouldbe_register_operand" | |
629 | (match_code "reg,subreg,mem") | |
630 | { | |
631 | return ((reload_in_progress || reload_completed) | |
632 | ? general_operand : register_operand) (op, mode); | |
633 | }) | |
634 | ||
635 | (define_predicate "vector_register_operand" | |
636 | (match_code "reg") | |
637 | { | |
638 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
639 | return 0; | |
640 | ||
641 | return (GET_CODE (op) == REG | |
642 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
643 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
644 | }) | |
645 | ||
646 | (define_predicate "vector_register_or_memory_operand" | |
647 | ( ior (match_code "reg") | |
648 | (match_code "mem")) | |
649 | { | |
650 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
651 | return 0; | |
652 | ||
653 | if ((GET_CODE (op) == MEM) | |
654 | && (mode == V8HImode) | |
655 | && GET_CODE (XEXP (op,0)) == REG) | |
656 | return 1; | |
657 | ||
658 | return (GET_CODE (op) == REG | |
659 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
660 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
661 | }) | |
662 | ||
663 | (define_predicate "arc_dpfp_operator" | |
664 | (match_code "plus, mult,minus") | |
665 | ) | |
666 | ||
667 | (define_predicate "arc_simd_dma_register_operand" | |
668 | (match_code "reg") | |
669 | { | |
670 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
671 | return 0; | |
672 | ||
673 | return (GET_CODE (op) == REG | |
674 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
675 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS)); | |
676 | }) | |
677 | ||
678 | (define_predicate "acc1_operand" | |
679 | (and (match_code "reg") | |
680 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)"))) | |
681 | ||
682 | (define_predicate "acc2_operand" | |
683 | (and (match_code "reg") | |
684 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)"))) | |
685 | ||
686 | (define_predicate "mlo_operand" | |
687 | (and (match_code "reg") | |
688 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)"))) | |
689 | ||
690 | (define_predicate "mhi_operand" | |
691 | (and (match_code "reg") | |
692 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 58 : 59)"))) | |
693 | ||
79557bae CZ |
694 | (define_predicate "accl_operand" |
695 | (and (match_code "reg") | |
696 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)") | |
697 | (match_test "TARGET_V2"))) | |
698 | ||
167ba5b9 JR |
699 | ; Unfortunately, we can not allow a const_int_operand before reload, because |
700 | ; reload needs a non-void mode to guide it how to reload the inside of a | |
701 | ; {sign_}extend. | |
526b7aee | 702 | (define_predicate "extend_operand" |
167ba5b9 JR |
703 | (ior (match_operand 0 "register_operand") |
704 | (and (match_operand 0 "immediate_operand") | |
705 | (ior (not (match_operand 0 "const_int_operand")) | |
706 | (match_test "reload_in_progress || reload_completed"))))) | |
526b7aee SV |
707 | |
708 | (define_predicate "millicode_store_operation" | |
709 | (match_code "parallel") | |
710 | { | |
711 | return arc_check_millicode (op, 0, 0); | |
712 | }) | |
713 | ||
714 | (define_predicate "millicode_load_operation" | |
715 | (match_code "parallel") | |
716 | { | |
717 | return arc_check_millicode (op, 2, 2); | |
718 | }) | |
719 | ||
720 | (define_predicate "millicode_load_clob_operation" | |
721 | (match_code "parallel") | |
722 | { | |
723 | return arc_check_millicode (op, 0, 1); | |
724 | }) | |
725 | ||
726 | (define_special_predicate "immediate_usidi_operand" | |
727 | (if_then_else | |
728 | (match_code "const_int") | |
729 | (match_test "INTVAL (op) >= 0") | |
730 | (and (match_test "const_double_operand (op, mode)") | |
731 | (match_test "CONST_DOUBLE_HIGH (op) == 0")))) | |
f50bb868 CZ |
732 | |
733 | (define_predicate "short_const_int_operand" | |
734 | (and (match_operand 0 "const_int_operand") | |
735 | (match_test "satisfies_constraint_C16 (op)"))) | |
b8a64b7f CZ |
736 | |
737 | (define_predicate "mem_noofs_operand" | |
738 | (and (match_code "mem") | |
739 | (match_code "reg" "0"))) | |
0086bd99 AB |
740 | |
741 | (define_predicate "any_mem_operand" | |
d34a0fdc CZ |
742 | (match_code "mem")) |
743 | ||
744 | ; Special predicate to match even-odd double register pair | |
745 | (define_predicate "even_register_operand" | |
746 | (match_code "reg") | |
747 | { | |
748 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
749 | return 0; | |
750 | ||
751 | return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
752 | || ((REGNO (op) & 1) == 0))); | |
753 | }) | |
8f3304d0 CZ |
754 | |
755 | (define_predicate "double_register_operand" | |
756 | (ior (match_test "even_register_operand (op, mode)") | |
757 | (match_test "arc_double_register_operand (op, mode)"))) | |
4d03dc2f JR |
758 | |
759 | (define_predicate "cmem_address_0" | |
760 | (and (match_code "symbol_ref") | |
761 | (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM"))) | |
762 | ||
763 | (define_predicate "cmem_address_1" | |
764 | (and (match_code "plus") | |
765 | (match_test "cmem_address_0 (XEXP (op, 0), SImode)"))) | |
766 | ||
767 | (define_predicate "cmem_address_2" | |
768 | (and (match_code "const") | |
769 | (match_test "cmem_address_1 (XEXP (op, 0), SImode)"))) | |
770 | ||
771 | (define_predicate "cmem_address" | |
772 | (ior (match_operand:SI 0 "cmem_address_0") | |
773 | (match_operand:SI 0 "cmem_address_1") | |
774 | (match_operand:SI 0 "cmem_address_2"))) | |
7132ae19 CZ |
775 | |
776 | (define_predicate "short_unsigned_const_operand" | |
777 | (and (match_code "const_int") | |
778 | (match_test "satisfies_constraint_J16 (op)"))) | |
779 | ||
780 | (define_predicate "arc_short_operand" | |
781 | (ior (match_test "register_operand (op, mode)") | |
782 | (match_test "short_unsigned_const_operand (op, mode)"))) | |
90b48013 CZ |
783 | |
784 | (define_special_predicate "push_multi_operand" | |
785 | (match_code "parallel") | |
786 | { | |
787 | return arc_check_multi (op, true); | |
788 | }) | |
789 | ||
790 | (define_special_predicate "pop_multi_operand" | |
791 | (match_code "parallel") | |
792 | { | |
793 | return arc_check_multi (op, false); | |
794 | }) |