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526b7aee | 1 | ;; Predicate definitions for Synopsys DesignWare ARC. |
a945c346 | 2 | ;; Copyright (C) 2007-2024 Free Software Foundation, Inc. |
526b7aee SV |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_predicate "dest_reg_operand" | |
21 | (match_code "reg,subreg") | |
22 | { | |
526b7aee SV |
23 | return register_operand (op, mode); |
24 | }) | |
25 | ||
526b7aee SV |
26 | ;; Returns 1 if OP is a symbol reference. |
27 | (define_predicate "symbolic_operand" | |
28 | (match_code "symbol_ref, label_ref, const") | |
29 | ) | |
30 | ||
31 | ;; Acceptable arguments to the call insn. | |
32 | (define_predicate "call_address_operand" | |
33 | (ior (match_code "const_int, reg") | |
34 | (match_operand 0 "symbolic_operand") | |
35 | (match_test "CONSTANT_P (op) | |
36 | && arc_legitimate_constant_p (VOIDmode, op)")) | |
37 | ) | |
38 | ||
39 | (define_predicate "call_operand" | |
40 | (and (match_code "mem") | |
41 | (match_test "call_address_operand (XEXP (op, 0), mode)")) | |
42 | ) | |
43 | ||
44 | ;; Return true if OP is a unsigned 6-bit immediate (u6) value. | |
45 | (define_predicate "u6_immediate_operand" | |
46 | (and (match_code "const_int") | |
47 | (match_test "UNSIGNED_INT6 (INTVAL (op))")) | |
48 | ) | |
49 | ||
50 | ;; Return true if OP is a short immediate (shimm) value. | |
51 | (define_predicate "short_immediate_operand" | |
52 | (and (match_code "const_int") | |
53 | (match_test "SMALL_INT (INTVAL (op))")) | |
54 | ) | |
55 | ||
56 | (define_predicate "p2_immediate_operand" | |
57 | (and (match_code "const_int") | |
58 | (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0") | |
59 | (match_test "INTVAL (op)")) | |
60 | ) | |
61 | ||
62 | ;; Return true if OP will require a long immediate (limm) value. | |
63 | ;; This is currently only used when calculating length attributes. | |
64 | (define_predicate "long_immediate_operand" | |
65 | (match_code "symbol_ref, label_ref, const, const_double, const_int") | |
66 | { | |
67 | switch (GET_CODE (op)) | |
68 | { | |
69 | case SYMBOL_REF : | |
70 | case LABEL_REF : | |
71 | case CONST : | |
72 | return 1; | |
73 | case CONST_INT : | |
74 | return !SIGNED_INT12 (INTVAL (op)); | |
75 | case CONST_DOUBLE : | |
76 | /* These can happen because large unsigned 32 bit constants are | |
77 | represented this way (the multiplication patterns can cause these | |
78 | to be generated). They also occur for SFmode values. */ | |
79 | return 1; | |
80 | default: | |
81 | break; | |
82 | } | |
83 | return 0; | |
84 | } | |
85 | ) | |
86 | ||
87 | ;; Return true if OP is a MEM that when used as a load or store address will | |
88 | ;; require an 8 byte insn. | |
89 | ;; Load and store instructions don't allow the same possibilities but they're | |
90 | ;; similar enough that this one function will do. | |
91 | ;; This is currently only used when calculating length attributes. */ | |
92 | (define_predicate "long_immediate_loadstore_operand" | |
93 | (match_code "mem") | |
94 | { | |
95 | int size = GET_MODE_SIZE (GET_MODE (op)); | |
96 | ||
97 | op = XEXP (op, 0); | |
4d03dc2f JR |
98 | if (TARGET_NPS_CMEM && cmem_address (op, SImode)) |
99 | return 0; | |
526b7aee SV |
100 | switch (GET_CODE (op)) |
101 | { | |
102 | case SYMBOL_REF : | |
103 | case LABEL_REF : | |
104 | case CONST : | |
105 | return 1; | |
106 | case CONST_INT : | |
107 | /* This must be handled as "st c,[limm]". Ditto for load. | |
108 | Technically, the assembler could translate some possibilities to | |
109 | "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't | |
110 | assume that it does. */ | |
111 | return 1; | |
112 | case CONST_DOUBLE : | |
113 | /* These can happen because large unsigned 32 bit constants are | |
114 | represented this way (the multiplication patterns can cause these | |
115 | to be generated). They also occur for SFmode values. */ | |
116 | return 1; | |
117 | case REG : | |
118 | return 0; | |
119 | case PLUS : | |
120 | { | |
121 | rtx x = XEXP (op, 1); | |
122 | ||
ac255185 CZ |
123 | if ((GET_CODE (XEXP (op, 0)) == MULT) |
124 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
125 | && CONSTANT_P (x)) | |
126 | return 1; | |
127 | ||
526b7aee SV |
128 | if (GET_CODE (x) == CONST) |
129 | { | |
130 | x = XEXP (x, 0); | |
131 | if (GET_CODE (x) == PLUS) | |
132 | x = XEXP (x, 0); | |
133 | } | |
134 | if (CONST_INT_P (x)) | |
135 | return (!SMALL_INT (INTVAL (x)) | |
136 | && (size <= 1 || size > 4 | |
137 | || (INTVAL (x) & (size - 1)) != 0 | |
138 | || !SMALL_INT (INTVAL (x) / size))); | |
139 | else if (GET_CODE (x) == SYMBOL_REF) | |
140 | return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x); | |
141 | return 0; | |
142 | } | |
143 | default: | |
144 | break; | |
145 | } | |
146 | return 0; | |
147 | } | |
148 | ) | |
149 | ||
150 | ;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit | |
151 | ;; instructions | |
152 | (define_predicate "compact_register_operand" | |
153 | (match_code "reg, subreg") | |
154 | { | |
155 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
156 | return 0; | |
157 | ||
158 | return (GET_CODE (op) == REG) | |
159 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
160 | || COMPACT_GP_REG_P (REGNO (op))) ; | |
161 | } | |
162 | ) | |
163 | ||
0e03cebd CZ |
164 | (define_predicate "compact_hreg_operand" |
165 | (match_code "reg, subreg") | |
166 | { | |
167 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
168 | return 0; | |
169 | ||
170 | return (GET_CODE (op) == REG) | |
171 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
172 | || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30) | |
173 | || !TARGET_V2); | |
174 | } | |
175 | ) | |
176 | ||
526b7aee SV |
177 | ;; Return true if OP is an acceptable memory operand for ARCompact |
178 | ;; 16-bit store instructions | |
179 | (define_predicate "compact_store_memory_operand" | |
180 | (match_code "mem") | |
181 | { | |
182 | rtx addr, plus0, plus1; | |
183 | int size, off; | |
184 | ||
185 | if (mode == VOIDmode) | |
186 | mode = GET_MODE (op); | |
187 | ||
188 | /* .di instructions have no 16-bit form. */ | |
189 | if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET) | |
190 | return 0; | |
191 | ||
8180c03f CZ |
192 | /* likewise for uncached types. */ |
193 | if (arc_is_uncached_mem_p (op)) | |
194 | return 0; | |
195 | ||
526b7aee SV |
196 | size = GET_MODE_SIZE (mode); |
197 | ||
198 | /* dword operations really put out 2 instructions, so eliminate them. */ | |
199 | if (size > UNITS_PER_WORD) | |
200 | return 0; | |
201 | ||
202 | /* Decode the address now. */ | |
203 | addr = XEXP (op, 0); | |
204 | switch (GET_CODE (addr)) | |
205 | { | |
206 | case REG: | |
207 | return (REGNO (addr) >= FIRST_PSEUDO_REGISTER | |
208 | || COMPACT_GP_REG_P (REGNO (addr)) | |
209 | || (SP_REG_P (REGNO (addr)) && (size != 2))); | |
210 | /* stw_s does not support SP as a parameter. */ | |
211 | case PLUS: | |
212 | plus0 = XEXP (addr, 0); | |
213 | plus1 = XEXP (addr, 1); | |
214 | ||
215 | if ((GET_CODE (plus0) == REG) | |
216 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
217 | || COMPACT_GP_REG_P (REGNO (plus0))) | |
218 | && (GET_CODE (plus1) == CONST_INT)) | |
219 | { | |
220 | off = INTVAL (plus1); | |
221 | ||
222 | /* Negative offset is not supported in 16-bit load/store insns. */ | |
223 | if (off < 0) | |
224 | return 0; | |
225 | ||
226 | switch (size) | |
227 | { | |
228 | case 1: | |
229 | return (off < 32); | |
230 | case 2: | |
231 | return ((off < 64) && (off % 2 == 0)); | |
232 | case 4: | |
233 | return ((off < 128) && (off % 4 == 0)); | |
234 | } | |
235 | } | |
236 | ||
237 | if ((GET_CODE (plus0) == REG) | |
238 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
239 | || SP_REG_P (REGNO (plus0))) | |
240 | && (GET_CODE (plus1) == CONST_INT)) | |
241 | { | |
242 | off = INTVAL (plus1); | |
243 | ||
244 | return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0)); | |
245 | } | |
246 | default: | |
247 | break; | |
248 | } | |
249 | return 0; | |
250 | } | |
251 | ) | |
252 | ||
253 | ;; Return true if OP is an acceptable argument for a single word | |
254 | ;; move source. | |
255 | (define_predicate "move_src_operand" | |
256 | (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem") | |
257 | { | |
258 | switch (GET_CODE (op)) | |
259 | { | |
260 | case SYMBOL_REF : | |
28633bbd CZ |
261 | if (SYMBOL_REF_TLS_MODEL (op)) |
262 | return 0; | |
3bbe0b82 | 263 | return 1; |
526b7aee | 264 | case LABEL_REF : |
28633bbd | 265 | return 1; |
526b7aee | 266 | case CONST : |
28633bbd | 267 | return arc_legitimate_constant_p (mode, op); |
526b7aee SV |
268 | case CONST_INT : |
269 | return (LARGE_INT (INTVAL (op))); | |
270 | case CONST_DOUBLE : | |
271 | /* We can handle DImode integer constants in SImode if the value | |
272 | (signed or unsigned) will fit in 32 bits. This is needed because | |
273 | large unsigned 32 bit constants are represented as CONST_DOUBLEs. */ | |
274 | if (mode == SImode) | |
275 | return arc_double_limm_p (op); | |
276 | /* We can handle 32 bit floating point constants. */ | |
277 | if (mode == SFmode) | |
278 | return GET_MODE (op) == SFmode; | |
279 | return 0; | |
280 | case REG : | |
ce9dbf20 CZ |
281 | if (REGNO (op) == LP_COUNT) |
282 | return 1; | |
526b7aee SV |
283 | return register_operand (op, mode); |
284 | case SUBREG : | |
285 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
286 | pseudo-reg and is now a stack slot. */ | |
287 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
288 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
289 | else | |
290 | return register_operand (op, mode); | |
291 | case MEM : | |
292 | return address_operand (XEXP (op, 0), mode); | |
293 | default : | |
294 | return 0; | |
295 | } | |
296 | } | |
297 | ) | |
298 | ||
299 | ;; Return true if OP is an acceptable argument for a double word | |
300 | ;; move source. | |
301 | (define_predicate "move_double_src_operand" | |
302 | (match_code "reg, subreg, mem, const_int, const_double") | |
303 | { | |
304 | switch (GET_CODE (op)) | |
305 | { | |
306 | case REG : | |
307 | return register_operand (op, mode); | |
308 | case SUBREG : | |
309 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
310 | pseudo-reg and is now a stack slot. */ | |
311 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
e5dcff3e | 312 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); |
526b7aee SV |
313 | else |
314 | return register_operand (op, mode); | |
315 | case MEM : | |
316 | return address_operand (XEXP (op, 0), mode); | |
317 | case CONST_INT : | |
318 | case CONST_DOUBLE : | |
319 | return 1; | |
320 | default : | |
321 | return 0; | |
322 | } | |
323 | } | |
324 | ) | |
325 | ||
326 | ;; Return true if OP is an acceptable argument for a move destination. | |
327 | (define_predicate "move_dest_operand" | |
328 | (match_code "reg, subreg, mem") | |
329 | { | |
330 | switch (GET_CODE (op)) | |
331 | { | |
332 | case REG : | |
333 | /* Program Counter register cannot be the target of a move. It is | |
334 | a readonly register. */ | |
73dac59b | 335 | if (REGNO (op) == PCL_REG) |
526b7aee SV |
336 | return 0; |
337 | else if (TARGET_MULMAC_32BY16_SET | |
73dac59b | 338 | && (REGNO (op) == MUL32x16_REG || REGNO (op) == R57_REG)) |
526b7aee SV |
339 | return 0; |
340 | else if (TARGET_MUL64_SET | |
73dac59b CZ |
341 | && (REGNO (op) == R57_REG || REGNO (op) == MUL64_OUT_REG |
342 | || REGNO (op) == R59_REG)) | |
526b7aee | 343 | return 0; |
a2de90a4 CZ |
344 | else if (REGNO (op) == LP_COUNT) |
345 | return 1; | |
526b7aee SV |
346 | else |
347 | return dest_reg_operand (op, mode); | |
348 | case SUBREG : | |
349 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
350 | pseudo-reg and is now a stack slot. */ | |
351 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
352 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
353 | else | |
354 | return dest_reg_operand (op, mode); | |
355 | case MEM : | |
356 | { | |
357 | rtx addr = XEXP (op, 0); | |
358 | ||
359 | if (GET_CODE (addr) == PLUS | |
360 | && (GET_CODE (XEXP (addr, 0)) == MULT | |
361 | || (!CONST_INT_P (XEXP (addr, 1)) | |
362 | && (TARGET_NO_SDATA_SET | |
363 | || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF | |
364 | || !SYMBOL_REF_SMALL_P (XEXP (addr, 1)))))) | |
365 | return 0; | |
366 | if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
367 | && (GET_CODE (XEXP (addr, 1)) != PLUS | |
368 | || !CONST_INT_P (XEXP (XEXP (addr, 1), 1)))) | |
369 | return 0; | |
28633bbd CZ |
370 | /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC)) |
371 | constructs are effectively indexed. */ | |
372 | if (flag_pic) | |
373 | { | |
374 | rtx ad0 = addr; | |
375 | while (GET_CODE (ad0) == PLUS) | |
376 | ad0 = XEXP (ad0, 0); | |
377 | if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC) | |
378 | return 0; | |
379 | } | |
526b7aee SV |
380 | return address_operand (addr, mode); |
381 | } | |
382 | default : | |
383 | return 0; | |
384 | } | |
385 | ||
386 | } | |
387 | ) | |
388 | ||
526b7aee SV |
389 | ;; Return true if OP is a non-volatile non-immediate operand. |
390 | ;; Volatile memory refs require a special "cache-bypass" instruction | |
391 | ;; and only the standard movXX patterns are set up to handle them. | |
392 | (define_predicate "nonvol_nonimm_operand" | |
393 | (and (match_code "subreg, reg, mem") | |
8180c03f CZ |
394 | (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)") |
395 | (match_test "!arc_is_uncached_mem_p (op)")) | |
526b7aee SV |
396 | ) |
397 | ||
398 | ;; Return 1 if OP is a comparison operator valid for the mode of CC. | |
399 | ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns. | |
400 | ||
401 | (define_predicate "proper_comparison_operator" | |
402 | (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt") | |
403 | { | |
404 | enum rtx_code code = GET_CODE (op); | |
405 | ||
406 | if (!COMPARISON_P (op)) | |
407 | return 0; | |
408 | ||
409 | /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz . | |
410 | There are some creative uses for hi / ls after shifts, but these are | |
411 | hard to understand for the compiler and could be at best the target of | |
412 | a peephole. */ | |
413 | switch (GET_MODE (XEXP (op, 0))) | |
414 | { | |
4e10a5a7 | 415 | case E_CC_ZNmode: |
526b7aee SV |
416 | return (code == EQ || code == NE || code == GE || code == LT |
417 | || code == GT); | |
4e10a5a7 | 418 | case E_CC_Zmode: |
526b7aee | 419 | return code == EQ || code == NE; |
4e10a5a7 | 420 | case E_CC_Cmode: |
526b7aee | 421 | return code == LTU || code == GEU; |
4e10a5a7 | 422 | case E_CC_FP_GTmode: |
526b7aee | 423 | return code == GT || code == UNLE; |
4e10a5a7 | 424 | case E_CC_FP_GEmode: |
526b7aee | 425 | return code == GE || code == UNLT; |
4e10a5a7 | 426 | case E_CC_FP_ORDmode: |
526b7aee | 427 | return code == ORDERED || code == UNORDERED; |
4e10a5a7 | 428 | case E_CC_FP_UNEQmode: |
526b7aee | 429 | return code == UNEQ || code == LTGT; |
4e10a5a7 | 430 | case E_CC_FPXmode: |
526b7aee SV |
431 | return (code == EQ || code == NE || code == UNEQ || code == LTGT |
432 | || code == ORDERED || code == UNORDERED); | |
433 | ||
4e10a5a7 | 434 | case E_CC_FPUmode: |
fbf8314b | 435 | case E_CC_FPUEmode: |
8f3304d0 | 436 | return 1; |
4e10a5a7 | 437 | case E_CC_FPU_UNEQmode: |
8f3304d0 CZ |
438 | return 1; |
439 | ||
4e10a5a7 RS |
440 | case E_CCmode: |
441 | case E_SImode: /* Used for BRcc. */ | |
526b7aee SV |
442 | return 1; |
443 | /* From combiner. */ | |
4e10a5a7 | 444 | case E_QImode: case E_HImode: case E_DImode: case E_SFmode: case E_DFmode: |
526b7aee | 445 | return 0; |
4e10a5a7 | 446 | case E_VOIDmode: |
dfa654c8 | 447 | return 0; |
526b7aee SV |
448 | default: |
449 | gcc_unreachable (); | |
450 | } | |
451 | }) | |
452 | ||
453 | (define_predicate "equality_comparison_operator" | |
454 | (match_code "eq, ne")) | |
455 | ||
e389ba30 AB |
456 | (define_predicate "ge_lt_comparison_operator" |
457 | (match_code "ge, lt")) | |
458 | ||
526b7aee SV |
459 | (define_predicate "brcc_nolimm_operator" |
460 | (ior (match_test "REG_P (XEXP (op, 1))") | |
461 | (and (match_code "eq, ne, lt, ge, ltu, geu") | |
4173ddaf | 462 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
463 | (match_test "u6_immediate_operand (XEXP (op, 1), SImode)")) |
464 | (and (match_code "le, gt, leu, gtu") | |
4173ddaf | 465 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
466 | (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)")))) |
467 | ||
468 | ;; Return TRUE if this is the condition code register, if we aren't given | |
469 | ;; a mode, accept any CCmode register | |
470 | (define_special_predicate "cc_register" | |
471 | (match_code "reg") | |
472 | { | |
473 | if (mode == VOIDmode) | |
474 | { | |
475 | mode = GET_MODE (op); | |
476 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
477 | return FALSE; | |
478 | } | |
479 | ||
480 | if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG) | |
481 | return TRUE; | |
482 | ||
483 | return FALSE; | |
484 | }) | |
485 | ||
486 | ;; Return TRUE if this is the condition code register; if we aren't given | |
487 | ;; a mode, accept any CCmode register. If we are given a mode, accept | |
488 | ;; modes that set a subset of flags. | |
489 | (define_special_predicate "cc_set_register" | |
490 | (match_code "reg") | |
491 | { | |
ef4bddc2 | 492 | machine_mode rmode = GET_MODE (op); |
526b7aee SV |
493 | |
494 | if (mode == VOIDmode) | |
495 | { | |
496 | mode = rmode; | |
497 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
498 | return FALSE; | |
499 | } | |
500 | ||
f7ace5d5 | 501 | if (REGNO (op) != CC_REG) |
526b7aee SV |
502 | return FALSE; |
503 | if (mode == rmode | |
504 | || (mode == CC_ZNmode && rmode == CC_Zmode) | |
505 | || (mode == CCmode && rmode == CC_Zmode) | |
506 | || (mode == CCmode && rmode == CC_ZNmode) | |
507 | || (mode == CCmode && rmode == CC_Cmode)) | |
508 | return TRUE; | |
509 | ||
510 | return FALSE; | |
511 | }) | |
512 | ||
513 | ; Accept CC_REG in modes which provide the flags needed for MODE. */ | |
514 | (define_special_predicate "cc_use_register" | |
515 | (match_code "reg") | |
516 | { | |
517 | if (REGNO (op) != CC_REG) | |
518 | return 0; | |
519 | if (GET_MODE (op) == mode) | |
520 | return 1; | |
521 | switch (mode) | |
522 | { | |
4e10a5a7 | 523 | case E_CC_Zmode: |
526b7aee SV |
524 | if (GET_MODE (op) == CC_ZNmode) |
525 | return 1; | |
526 | /* Fall through. */ | |
4e10a5a7 | 527 | case E_CC_ZNmode: case E_CC_Cmode: |
526b7aee SV |
528 | return GET_MODE (op) == CCmode; |
529 | default: | |
530 | gcc_unreachable (); | |
531 | } | |
532 | }) | |
533 | ||
534 | (define_special_predicate "zn_compare_operator" | |
535 | (match_code "compare") | |
536 | { | |
537 | return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode; | |
538 | }) | |
539 | ||
540 | ;; Return true if OP is a shift operator. | |
541 | (define_predicate "shift_operator" | |
542 | (match_code "ashiftrt, lshiftrt, ashift") | |
543 | ) | |
544 | ||
526b7aee | 545 | (define_predicate "mult_operator" |
f50bb868 | 546 | (and (match_code "mult") (match_test "TARGET_MPY")) |
526b7aee SV |
547 | ) |
548 | ||
549 | (define_predicate "commutative_operator" | |
550 | (ior (match_code "plus,ior,xor,and") | |
551 | (match_operand 0 "mult_operator") | |
552 | (and (match_code "ss_plus") | |
553 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
554 | ) | |
555 | ||
556 | (define_predicate "commutative_operator_sans_mult" | |
557 | (ior (match_code "plus,ior,xor,and") | |
558 | (and (match_code "ss_plus") | |
559 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
560 | ) | |
561 | ||
562 | (define_predicate "noncommutative_operator" | |
f7ace5d5 CZ |
563 | (ior (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") |
564 | (match_test "TARGET_BARREL_SHIFTER")) | |
565 | (match_code "minus") | |
526b7aee SV |
566 | (and (match_code "ss_minus") |
567 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
568 | ) | |
569 | ||
570 | (define_predicate "unary_operator" | |
571 | (ior (match_code "abs,neg,not,sign_extend,zero_extend") | |
572 | (and (ior (match_code "ss_neg") | |
573 | (and (match_code "ss_truncate") | |
574 | (match_test "GET_MODE (XEXP (op, 0)) == HImode"))) | |
575 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
576 | ) | |
577 | ||
1e466f04 GM |
578 | (define_predicate "_1_2_3_operand" |
579 | (and (match_code "const_int") | |
580 | (match_test "INTVAL (op) == 1 || INTVAL (op) == 2 || INTVAL (op) == 3")) | |
581 | ) | |
582 | ||
526b7aee SV |
583 | (define_predicate "_2_4_8_operand" |
584 | (and (match_code "const_int") | |
585 | (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8")) | |
586 | ) | |
587 | ||
588 | (define_predicate "arc_double_register_operand" | |
589 | (match_code "reg") | |
590 | { | |
591 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
592 | return 0; | |
593 | ||
594 | return (GET_CODE (op) == REG | |
595 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
596 | || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS)); | |
597 | }) | |
598 | ||
599 | (define_predicate "shouldbe_register_operand" | |
600 | (match_code "reg,subreg,mem") | |
601 | { | |
602 | return ((reload_in_progress || reload_completed) | |
603 | ? general_operand : register_operand) (op, mode); | |
604 | }) | |
605 | ||
606 | (define_predicate "vector_register_operand" | |
607 | (match_code "reg") | |
608 | { | |
609 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
610 | return 0; | |
611 | ||
612 | return (GET_CODE (op) == REG | |
613 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
614 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
615 | }) | |
616 | ||
617 | (define_predicate "vector_register_or_memory_operand" | |
618 | ( ior (match_code "reg") | |
619 | (match_code "mem")) | |
620 | { | |
621 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
622 | return 0; | |
623 | ||
624 | if ((GET_CODE (op) == MEM) | |
625 | && (mode == V8HImode) | |
626 | && GET_CODE (XEXP (op,0)) == REG) | |
627 | return 1; | |
628 | ||
629 | return (GET_CODE (op) == REG | |
630 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
631 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
632 | }) | |
633 | ||
634 | (define_predicate "arc_dpfp_operator" | |
635 | (match_code "plus, mult,minus") | |
636 | ) | |
637 | ||
638 | (define_predicate "arc_simd_dma_register_operand" | |
639 | (match_code "reg") | |
640 | { | |
641 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
642 | return 0; | |
643 | ||
644 | return (GET_CODE (op) == REG | |
645 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
646 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS)); | |
647 | }) | |
648 | ||
649 | (define_predicate "acc1_operand" | |
650 | (and (match_code "reg") | |
651 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)"))) | |
652 | ||
653 | (define_predicate "acc2_operand" | |
654 | (and (match_code "reg") | |
655 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)"))) | |
656 | ||
657 | (define_predicate "mlo_operand" | |
658 | (and (match_code "reg") | |
82cd9a96 | 659 | (match_test "REGNO (op) == R58_REG"))) |
526b7aee SV |
660 | |
661 | (define_predicate "mhi_operand" | |
662 | (and (match_code "reg") | |
82cd9a96 | 663 | (match_test "REGNO (op) == R59_REG"))) |
526b7aee | 664 | |
79557bae CZ |
665 | (define_predicate "accl_operand" |
666 | (and (match_code "reg") | |
667 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)") | |
668 | (match_test "TARGET_V2"))) | |
669 | ||
67914693 | 670 | ; Unfortunately, we cannot allow a const_int_operand before reload, because |
167ba5b9 JR |
671 | ; reload needs a non-void mode to guide it how to reload the inside of a |
672 | ; {sign_}extend. | |
526b7aee | 673 | (define_predicate "extend_operand" |
167ba5b9 JR |
674 | (ior (match_operand 0 "register_operand") |
675 | (and (match_operand 0 "immediate_operand") | |
676 | (ior (not (match_operand 0 "const_int_operand")) | |
677 | (match_test "reload_in_progress || reload_completed"))))) | |
526b7aee SV |
678 | |
679 | (define_predicate "millicode_store_operation" | |
680 | (match_code "parallel") | |
681 | { | |
682 | return arc_check_millicode (op, 0, 0); | |
683 | }) | |
684 | ||
685 | (define_predicate "millicode_load_operation" | |
686 | (match_code "parallel") | |
687 | { | |
688 | return arc_check_millicode (op, 2, 2); | |
689 | }) | |
690 | ||
691 | (define_predicate "millicode_load_clob_operation" | |
692 | (match_code "parallel") | |
693 | { | |
694 | return arc_check_millicode (op, 0, 1); | |
695 | }) | |
696 | ||
697 | (define_special_predicate "immediate_usidi_operand" | |
698 | (if_then_else | |
699 | (match_code "const_int") | |
700 | (match_test "INTVAL (op) >= 0") | |
701 | (and (match_test "const_double_operand (op, mode)") | |
702 | (match_test "CONST_DOUBLE_HIGH (op) == 0")))) | |
f50bb868 CZ |
703 | |
704 | (define_predicate "short_const_int_operand" | |
705 | (and (match_operand 0 "const_int_operand") | |
706 | (match_test "satisfies_constraint_C16 (op)"))) | |
b8a64b7f CZ |
707 | |
708 | (define_predicate "mem_noofs_operand" | |
709 | (and (match_code "mem") | |
710 | (match_code "reg" "0"))) | |
0086bd99 AB |
711 | |
712 | (define_predicate "any_mem_operand" | |
d34a0fdc CZ |
713 | (match_code "mem")) |
714 | ||
715 | ; Special predicate to match even-odd double register pair | |
716 | (define_predicate "even_register_operand" | |
717 | (match_code "reg") | |
718 | { | |
719 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
720 | return 0; | |
721 | ||
722 | return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
723 | || ((REGNO (op) & 1) == 0))); | |
724 | }) | |
8f3304d0 CZ |
725 | |
726 | (define_predicate "double_register_operand" | |
727 | (ior (match_test "even_register_operand (op, mode)") | |
728 | (match_test "arc_double_register_operand (op, mode)"))) | |
4d03dc2f JR |
729 | |
730 | (define_predicate "cmem_address_0" | |
731 | (and (match_code "symbol_ref") | |
732 | (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM"))) | |
733 | ||
734 | (define_predicate "cmem_address_1" | |
735 | (and (match_code "plus") | |
736 | (match_test "cmem_address_0 (XEXP (op, 0), SImode)"))) | |
737 | ||
738 | (define_predicate "cmem_address_2" | |
739 | (and (match_code "const") | |
740 | (match_test "cmem_address_1 (XEXP (op, 0), SImode)"))) | |
741 | ||
742 | (define_predicate "cmem_address" | |
743 | (ior (match_operand:SI 0 "cmem_address_0") | |
744 | (match_operand:SI 0 "cmem_address_1") | |
745 | (match_operand:SI 0 "cmem_address_2"))) | |
7132ae19 CZ |
746 | |
747 | (define_predicate "short_unsigned_const_operand" | |
748 | (and (match_code "const_int") | |
749 | (match_test "satisfies_constraint_J16 (op)"))) | |
750 | ||
751 | (define_predicate "arc_short_operand" | |
752 | (ior (match_test "register_operand (op, mode)") | |
753 | (match_test "short_unsigned_const_operand (op, mode)"))) | |
90b48013 CZ |
754 | |
755 | (define_special_predicate "push_multi_operand" | |
756 | (match_code "parallel") | |
757 | { | |
758 | return arc_check_multi (op, true); | |
759 | }) | |
760 | ||
761 | (define_special_predicate "pop_multi_operand" | |
762 | (match_code "parallel") | |
763 | { | |
764 | return arc_check_multi (op, false); | |
765 | }) | |
e57764be CZ |
766 | |
767 | (define_predicate "arc_nonmemory_operand" | |
768 | (ior (match_test "register_operand (op, mode)") | |
769 | (and (match_code "const_int, symbol_ref") | |
770 | (match_test "!optimize_size")))) |