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ceddf62c | 1 | ;; Code and mode itertator and attribute definitions for the ARM backend |
8d9254fc | 2 | ;; Copyright (C) 2010-2020 Free Software Foundation, Inc. |
ceddf62c SN |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ||
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;;---------------------------------------------------------------------------- | |
23 | ;; Mode iterators | |
24 | ;;---------------------------------------------------------------------------- | |
25 | ||
26 | ;; A list of modes that are exactly 64 bits in size. This is used to expand | |
2a26aed6 | 27 | ;; some splits that are the same for all modes when operating on ARM |
ceddf62c | 28 | ;; registers. |
2a26aed6 | 29 | (define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF]) |
ceddf62c | 30 | |
0f38f229 TB |
31 | (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) |
32 | ||
ceddf62c SN |
33 | ;; A list of integer modes that are up to one word long |
34 | (define_mode_iterator QHSI [QI HI SI]) | |
35 | ||
a46b23e1 RR |
36 | ;; A list of integer modes that are half and one word long |
37 | (define_mode_iterator HSI [HI SI]) | |
38 | ||
cfe52743 DAG |
39 | ;; A list of integer modes that are less than a word |
40 | (define_mode_iterator NARROW [QI HI]) | |
41 | ||
073a8998 | 42 | ;; A list of all the integer modes up to 64bit |
cfe52743 DAG |
43 | (define_mode_iterator QHSD [QI HI SI DI]) |
44 | ||
45 | ;; A list of the 32bit and 64bit integer modes | |
46 | (define_mode_iterator SIDI [SI DI]) | |
47 | ||
3cff0135 TP |
48 | ;; A list of atomic compare and swap success return modes |
49 | (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) | |
50 | ||
76f722f4 | 51 | ;; A list of modes which the VFP unit can handle |
00ea1506 | 52 | (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) |
76f722f4 | 53 | |
ceddf62c SN |
54 | ;; Integer element sizes implemented by IWMMXT. |
55 | (define_mode_iterator VMMX [V2SI V4HI V8QI]) | |
56 | ||
8fd03515 XQ |
57 | (define_mode_iterator VMMX2 [V4HI V2SI]) |
58 | ||
ceddf62c SN |
59 | ;; Integer element sizes for shifts. |
60 | (define_mode_iterator VSHFT [V4HI V2SI DI]) | |
61 | ||
62 | ;; Integer and float modes supported by Neon and IWMMXT. | |
63 | (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
64 | ||
65 | ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. | |
66 | (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) | |
67 | ||
68 | ;; Integer modes supported by Neon and IWMMXT | |
69 | (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) | |
70 | ||
71 | ;; Integer modes supported by Neon and IWMMXT, except V2DI | |
72 | (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) | |
73 | ||
4b644867 | 74 | ;; Double-width vector modes, on which we support arithmetic (no HF!) |
ceddf62c SN |
75 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) |
76 | ||
4b644867 AL |
77 | ;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate. |
78 | (define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI]) | |
79 | ||
ceddf62c | 80 | ;; Double-width vector modes plus 64-bit elements. |
4b644867 AL |
81 | (define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI]) |
82 | ||
83 | ;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane. | |
84 | (define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF]) | |
ceddf62c SN |
85 | |
86 | ;; Double-width vector modes without floating-point elements. | |
87 | (define_mode_iterator VDI [V8QI V4HI V2SI]) | |
88 | ||
4b644867 | 89 | ;; Quad-width vector modes supporting arithmetic (no HF!). |
ceddf62c SN |
90 | (define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) |
91 | ||
4b644867 AL |
92 | ;; Quad-width vector modes, including V8HF. |
93 | (define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF]) | |
94 | ||
95 | ;; Quad-width vector modes with 16- or 32-bit elements | |
96 | (define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF]) | |
97 | ||
ceddf62c | 98 | ;; Quad-width vector modes plus 64-bit elements. |
4b644867 | 99 | (define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI]) |
ceddf62c SN |
100 | |
101 | ;; Quad-width vector modes without floating-point elements. | |
102 | (define_mode_iterator VQI [V16QI V8HI V4SI]) | |
103 | ||
104 | ;; Quad-width vector modes, with TImode added, for moves. | |
92422235 | 105 | (define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI]) |
ceddf62c SN |
106 | |
107 | ;; Opaque structure types wider than TImode. | |
108 | (define_mode_iterator VSTRUCT [EI OI CI XI]) | |
109 | ||
110 | ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). | |
111 | (define_mode_iterator VTAB [TI EI OI]) | |
112 | ||
113 | ;; Widenable modes. | |
114 | (define_mode_iterator VW [V8QI V4HI V2SI]) | |
115 | ||
116 | ;; Narrowable modes. | |
117 | (define_mode_iterator VN [V8HI V4SI V2DI]) | |
118 | ||
119 | ;; All supported vector modes (except singleton DImode). | |
92422235 | 120 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) |
ceddf62c | 121 | |
d0b6b5a7 KT |
122 | ;; All supported floating-point vector modes (except V2DF). |
123 | (define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST") | |
124 | (V8HF "TARGET_NEON_FP16INST") V2SF V4SF]) | |
125 | ||
c2b7062d TC |
126 | ;; Double vector modes. |
127 | (define_mode_iterator VDF [V2SF V4HF]) | |
128 | ||
129 | ;; Quad vector Float modes with half/single elements. | |
130 | (define_mode_iterator VQ_HSF [V8HF V4SF]) | |
131 | ||
132 | ||
ceddf62c SN |
133 | ;; All supported vector modes (except those with 64-bit integer elements). |
134 | (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) | |
135 | ||
b1a970a5 MW |
136 | ;; All supported vector modes including 16-bit float modes. |
137 | (define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF | |
138 | V8HF V4HF]) | |
139 | ||
ceddf62c SN |
140 | ;; Supported integer vector modes (not 64 bit elements). |
141 | (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
142 | ||
143 | ;; Supported integer vector modes (not singleton DI) | |
144 | (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
145 | ||
146 | ;; Vector modes, including 64-bit integer elements. | |
4b644867 AL |
147 | (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI |
148 | V4HF V8HF V2SF V4SF DI V2DI]) | |
ceddf62c SN |
149 | |
150 | ;; Vector modes including 64-bit integer elements, but no floats. | |
151 | (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) | |
152 | ||
7a10ea9f KT |
153 | ;; Vector modes for H, S and D types. |
154 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
155 | ||
ceddf62c SN |
156 | ;; Vector modes for float->int conversions. |
157 | (define_mode_iterator VCVTF [V2SF V4SF]) | |
158 | ||
159 | ;; Vector modes form int->float conversions. | |
160 | (define_mode_iterator VCVTI [V2SI V4SI]) | |
161 | ||
55a9b91b MW |
162 | ;; Vector modes for int->half conversions. |
163 | (define_mode_iterator VCVTHI [V4HI V8HI]) | |
164 | ||
ceddf62c SN |
165 | ;; Vector modes for doubleword multiply-accumulate, etc. insns. |
166 | (define_mode_iterator VMD [V4HI V2SI V2SF]) | |
167 | ||
168 | ;; Vector modes for quadword multiply-accumulate, etc. insns. | |
169 | (define_mode_iterator VMQ [V8HI V4SI V4SF]) | |
170 | ||
171 | ;; Above modes combined. | |
172 | (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) | |
173 | ||
174 | ;; As VMD, but integer modes only. | |
175 | (define_mode_iterator VMDI [V4HI V2SI]) | |
176 | ||
177 | ;; As VMQ, but integer modes only. | |
178 | (define_mode_iterator VMQI [V8HI V4SI]) | |
179 | ||
180 | ;; Above modes combined. | |
181 | (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) | |
182 | ||
183 | ;; Modes with 8-bit and 16-bit elements. | |
184 | (define_mode_iterator VX [V8QI V4HI V16QI V8HI]) | |
185 | ||
186 | ;; Modes with 8-bit elements. | |
187 | (define_mode_iterator VE [V8QI V16QI]) | |
188 | ||
8ba8ebff RS |
189 | ;; V2DI only (for use with @ patterns). |
190 | (define_mode_iterator V2DI_ONLY [V2DI]) | |
191 | ||
ceddf62c SN |
192 | ;; Modes with 64-bit elements only. |
193 | (define_mode_iterator V64 [DI V2DI]) | |
194 | ||
195 | ;; Modes with 32-bit elements only. | |
196 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | |
197 | ||
46b57af1 TB |
198 | ;; Modes with 8-bit, 16-bit and 32-bit elements. |
199 | (define_mode_iterator VU [V16QI V8HI V4SI]) | |
655b30bf | 200 | |
b1a970a5 MW |
201 | ;; Vector modes for 16-bit floating-point support. |
202 | (define_mode_iterator VH [V8HF V4HF]) | |
203 | ||
655b30bf JB |
204 | ;; Iterators used for fixed-point support. |
205 | (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) | |
206 | ||
207 | (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) | |
208 | ||
209 | (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) | |
210 | ||
211 | (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) | |
212 | ||
213 | (define_mode_iterator QMUL [HQ HA]) | |
214 | ||
94f0f2cc JG |
215 | ;; Modes for polynomial or float values. |
216 | (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) | |
217 | ||
ceddf62c SN |
218 | ;;---------------------------------------------------------------------------- |
219 | ;; Code iterators | |
220 | ;;---------------------------------------------------------------------------- | |
221 | ||
381811fa KT |
222 | ;; The signed gt, ge comparisons |
223 | (define_code_iterator GTGE [gt ge]) | |
224 | ||
d403b8d4 MW |
225 | ;; The signed gt, ge, lt, le comparisons |
226 | (define_code_iterator GLTE [gt ge lt le]) | |
227 | ||
381811fa KT |
228 | ;; The unsigned gt, ge comparisons |
229 | (define_code_iterator GTUGEU [gtu geu]) | |
230 | ||
231 | ;; Comparisons for vc<cmp> | |
232 | (define_code_iterator COMPARISONS [eq gt ge le lt]) | |
233 | ||
ceddf62c | 234 | ;; A list of ... |
728dc153 | 235 | (define_code_iterator IOR_XOR [ior xor]) |
ceddf62c | 236 | |
1ea95660 WD |
237 | (define_code_iterator LOGICAL [and ior xor]) |
238 | ||
ceddf62c | 239 | ;; Operations on two halves of a quadword vector. |
728dc153 | 240 | (define_code_iterator VQH_OPS [plus smin smax umin umax]) |
ceddf62c SN |
241 | |
242 | ;; Operations on two halves of a quadword vector, | |
243 | ;; without unsigned variants (for use with *SFmode pattern). | |
728dc153 | 244 | (define_code_iterator VQHS_OPS [plus smin smax]) |
ceddf62c | 245 | |
46b57af1 TB |
246 | ;; A list of widening operators |
247 | (define_code_iterator SE [sign_extend zero_extend]) | |
ceddf62c | 248 | |
3f2dc806 | 249 | ;; Right shifts |
728dc153 | 250 | (define_code_iterator RSHIFTS [ashiftrt lshiftrt]) |
3f2dc806 | 251 | |
ababd936 KT |
252 | ;; Iterator for integer conversions |
253 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
254 | ||
004d3809 | 255 | ;; Binary operators whose second operand can be shifted. |
728dc153 | 256 | (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) |
004d3809 | 257 | |
d403b8d4 MW |
258 | ;; Operations on the sign of a number. |
259 | (define_code_iterator ABSNEG [abs neg]) | |
260 | ||
06e95715 KT |
261 | ;; The PLUS and MINUS operators. |
262 | (define_code_iterator PLUSMINUS [plus minus]) | |
263 | ||
d403b8d4 MW |
264 | ;; Conversions. |
265 | (define_code_iterator FCVT [unsigned_float float]) | |
266 | ||
e56d199b KT |
267 | ;; Saturating addition, subtraction |
268 | (define_code_iterator SSPLUSMINUS [ss_plus ss_minus]) | |
269 | ||
728dc153 | 270 | ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows |
f3b3331a | 271 | ;; a stack pointer operand. The minus operation is a candidate for an rsub |
004d3809 RE |
272 | ;; and hence only plus is supported. |
273 | (define_code_attr t2_binop0 | |
274 | [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) | |
275 | ||
728dc153 | 276 | ;; The instruction to use when a SHIFTABLE_OPS has a shift operation as |
004d3809 RE |
277 | ;; its first operand. |
278 | (define_code_attr arith_shift_insn | |
279 | [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) | |
280 | ||
381811fa KT |
281 | (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") |
282 | (gtu "gt") (geu "ge")]) | |
283 | ||
284 | (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) | |
285 | ||
06e95715 KT |
286 | (define_code_attr vfml_op [(plus "a") (minus "s")]) |
287 | ||
e56d199b KT |
288 | (define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")]) |
289 | ||
1dd4fe1f KT |
290 | ;;---------------------------------------------------------------------------- |
291 | ;; Int iterators | |
292 | ;;---------------------------------------------------------------------------- | |
293 | ||
294 | (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM | |
295 | UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) | |
296 | ||
55a9b91b MW |
297 | (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE |
298 | UNSPEC_VCLT UNSPEC_VCLE]) | |
381811fa KT |
299 | |
300 | (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) | |
301 | ||
55a9b91b MW |
302 | (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT |
303 | UNSPEC_VCALE UNSPEC_VCALT]) | |
304 | ||
ababd936 KT |
305 | (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) |
306 | ||
79739965 KT |
307 | (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM |
308 | UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) | |
309 | ||
e9e67af1 KT |
310 | (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) |
311 | ||
94f0f2cc JG |
312 | (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) |
313 | ||
314 | (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) | |
315 | ||
316 | (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U | |
317 | UNSPEC_VHADD_S UNSPEC_VHADD_U]) | |
318 | ||
319 | (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) | |
320 | ||
321 | (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) | |
322 | ||
323 | (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) | |
324 | ||
325 | (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) | |
326 | ||
327 | (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) | |
328 | ||
329 | (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) | |
330 | ||
331 | (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) | |
332 | ||
333 | (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) | |
334 | ||
335 | (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) | |
336 | ||
337 | (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) | |
338 | ||
339 | (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) | |
340 | ||
341 | (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) | |
342 | ||
343 | (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) | |
344 | ||
345 | (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) | |
346 | ||
347 | (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) | |
348 | ||
84ae7213 PW |
349 | (define_int_iterator VABAL [UNSPEC_VABAL_S UNSPEC_VABAL_U]) |
350 | ||
94f0f2cc JG |
351 | (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) |
352 | ||
353 | (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) | |
354 | ||
355 | (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U | |
356 | UNSPEC_VMIN UNSPEC_VMIN_U]) | |
357 | ||
358 | (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) | |
359 | ||
0a18c19f DS |
360 | (define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) |
361 | ||
94f0f2cc JG |
362 | (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) |
363 | ||
364 | (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) | |
365 | ||
366 | (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U | |
367 | UNSPEC_VPMIN UNSPEC_VPMIN_U]) | |
368 | ||
369 | (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) | |
370 | ||
371 | (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) | |
372 | ||
373 | (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) | |
374 | ||
d403b8d4 MW |
375 | (define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N]) |
376 | ||
377 | (define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N]) | |
378 | ||
379 | (define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U | |
380 | UNSPEC_VCVTM_S UNSPEC_VCVTM_U | |
381 | UNSPEC_VCVTN_S UNSPEC_VCVTN_U | |
382 | UNSPEC_VCVTP_S UNSPEC_VCVTP_U]) | |
383 | ||
384 | (define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U]) | |
385 | ||
386 | ;; Operators for FP16 instructions. | |
387 | (define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA | |
388 | UNSPEC_VRNDM UNSPEC_VRNDN | |
389 | UNSPEC_VRNDP UNSPEC_VRNDX]) | |
390 | ||
94f0f2cc JG |
391 | (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) |
392 | ||
393 | (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) | |
394 | ||
395 | (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U | |
396 | UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) | |
397 | ||
398 | (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U | |
399 | UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) | |
400 | ||
401 | (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N | |
402 | UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) | |
403 | ||
404 | (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) | |
405 | ||
406 | (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N | |
407 | UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) | |
408 | ||
409 | (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) | |
410 | ||
411 | (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) | |
412 | ||
413 | (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) | |
414 | ||
415 | (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N | |
416 | UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) | |
417 | ||
582e2e43 KT |
418 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
419 | UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) | |
420 | ||
4c12dc05 | 421 | (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) |
021b5e6b | 422 | |
4c12dc05 ST |
423 | (define_int_iterator CRYPTO_AES [UNSPEC_AESD UNSPEC_AESE]) |
424 | ||
425 | (define_int_iterator CRYPTO_BINARY [UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) | |
021b5e6b KT |
426 | |
427 | (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H | |
428 | UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) | |
429 | ||
430 | (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M | |
431 | UNSPEC_SHA1P]) | |
432 | ||
53cd0ac6 KT |
433 | (define_int_iterator USXTB16 [UNSPEC_SXTB16 UNSPEC_UXTB16]) |
434 | (define_int_iterator SIMD32_NOGE_BINOP | |
435 | [UNSPEC_QADD8 UNSPEC_QSUB8 UNSPEC_SHADD8 | |
436 | UNSPEC_SHSUB8 UNSPEC_UHADD8 UNSPEC_UHSUB8 | |
437 | UNSPEC_UQADD8 UNSPEC_UQSUB8 | |
438 | UNSPEC_QADD16 UNSPEC_QASX UNSPEC_QSAX | |
439 | UNSPEC_QSUB16 UNSPEC_SHADD16 UNSPEC_SHASX | |
440 | UNSPEC_SHSAX UNSPEC_SHSUB16 UNSPEC_UHADD16 | |
441 | UNSPEC_UHASX UNSPEC_UHSAX UNSPEC_UHSUB16 | |
442 | UNSPEC_UQADD16 UNSPEC_UQASX UNSPEC_UQSAX | |
443 | UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX | |
444 | UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8]) | |
445 | ||
2b5b5e24 KT |
446 | (define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX |
447 | UNSPEC_SMLSLD UNSPEC_SMLSLDX]) | |
448 | ||
08836731 KT |
449 | (define_int_iterator SMLAWBT [UNSPEC_SMLAWB UNSPEC_SMLAWT]) |
450 | ||
16155ccf KT |
451 | (define_int_iterator SIMD32_GE [UNSPEC_SADD8 UNSPEC_SSUB8 UNSPEC_UADD8 |
452 | UNSPEC_USUB8 UNSPEC_SADD16 UNSPEC_SASX | |
453 | UNSPEC_SSAX UNSPEC_SSUB16 UNSPEC_UADD16 | |
454 | UNSPEC_UASX UNSPEC_USAX UNSPEC_USUB16]) | |
455 | ||
65dd610d KT |
456 | (define_int_iterator SIMD32_TERNOP_Q [UNSPEC_SMLAD UNSPEC_SMLADX UNSPEC_SMLSD |
457 | UNSPEC_SMLSDX]) | |
458 | ||
459 | (define_int_iterator SIMD32_BINOP_Q [UNSPEC_SMUAD UNSPEC_SMUADX]) | |
460 | ||
0775830a KT |
461 | (define_int_iterator USSAT16 [UNSPEC_SSAT16 UNSPEC_USAT16]) |
462 | ||
5f2ca3b2 MW |
463 | (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) |
464 | ||
55a9b91b MW |
465 | (define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE]) |
466 | ||
f8e109ba TC |
467 | (define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U]) |
468 | ||
06e95715 KT |
469 | (define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI]) |
470 | ||
c2b7062d TC |
471 | (define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270]) |
472 | (define_int_iterator VCMLA [UNSPEC_VCMLA UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270]) | |
473 | ||
ceddf62c SN |
474 | ;;---------------------------------------------------------------------------- |
475 | ;; Mode attributes | |
476 | ;;---------------------------------------------------------------------------- | |
477 | ||
3cff0135 TP |
478 | ;; Determine name of atomic compare and swap from success result mode. This |
479 | ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. | |
480 | (define_mode_attr arch [(CC_Z "32") (SI "t1")]) | |
481 | ||
ceddf62c SN |
482 | ;; Determine element size suffix from vector mode. |
483 | (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) | |
484 | ||
485 | ;; vtbl<n> suffix for NEON vector modes. | |
486 | (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) | |
487 | ||
488 | ;; (Opposite) mode to convert to/from for NEON mode conversions. | |
489 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | |
490 | (V4SI "V4SF") (V4SF "V4SI")]) | |
491 | ||
5bf4dcf2 DP |
492 | ;; As above but in lower case. |
493 | (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") | |
494 | (V4SI "v4sf") (V4SF "v4si")]) | |
495 | ||
55a9b91b MW |
496 | ;; (Opposite) mode to convert to/from for vector-half mode conversions. |
497 | (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") | |
498 | (V8HI "V8HF") (V8HF "V8HI")]) | |
499 | ||
ceddf62c SN |
500 | ;; Define element mode for each vector mode. |
501 | (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") | |
4b644867 AL |
502 | (V4HI "HI") (V8HI "HI") |
503 | (V4HF "HF") (V8HF "HF") | |
ceddf62c SN |
504 | (V2SI "SI") (V4SI "SI") |
505 | (V2SF "SF") (V4SF "SF") | |
506 | (DI "DI") (V2DI "DI")]) | |
507 | ||
ff03930a JJ |
508 | ;; As above but in lower case. |
509 | (define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi") | |
510 | (V4HI "hi") (V8HI "hi") | |
511 | (V4HF "hf") (V8HF "hf") | |
512 | (V2SI "si") (V4SI "si") | |
513 | (V2SF "sf") (V4SF "sf") | |
514 | (DI "di") (V2DI "di")]) | |
515 | ||
ceddf62c SN |
516 | ;; Element modes for vector extraction, padded up to register size. |
517 | ||
518 | (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") | |
519 | (V4HI "SI") (V8HI "SI") | |
520 | (V2SI "SI") (V4SI "SI") | |
521 | (V2SF "SF") (V4SF "SF") | |
522 | (DI "DI") (V2DI "DI")]) | |
523 | ||
524 | ;; Mode of pair of elements for each vector mode, to define transfer | |
525 | ;; size for structure lane/dup loads and stores. | |
6308e208 RS |
526 | (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") |
527 | (V4HI "SI") (V8HI "SI") | |
4b644867 | 528 | (V4HF "SF") (V8HF "SF") |
ceddf62c SN |
529 | (V2SI "V2SI") (V4SI "V2SI") |
530 | (V2SF "V2SF") (V4SF "V2SF") | |
531 | (DI "V2DI") (V2DI "V2DI")]) | |
532 | ||
06e95715 KT |
533 | ;; Mode mapping for VFM[A,S]L instructions. |
534 | (define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")]) | |
535 | ||
536 | ;; Mode mapping for VFM[A,S]L instructions for the vec_select result. | |
537 | (define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")]) | |
538 | ||
eccf4d70 KT |
539 | ;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms. |
540 | (define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")]) | |
541 | ||
542 | ;; Same as the above, but lowercase. | |
543 | (define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")]) | |
544 | ||
ceddf62c | 545 | ;; Similar, for three elements. |
6308e208 RS |
546 | (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") |
547 | (V4HI "BLK") (V8HI "BLK") | |
4b644867 | 548 | (V4HF "BLK") (V8HF "BLK") |
6308e208 RS |
549 | (V2SI "BLK") (V4SI "BLK") |
550 | (V2SF "BLK") (V4SF "BLK") | |
551 | (DI "EI") (V2DI "EI")]) | |
ceddf62c SN |
552 | |
553 | ;; Similar, for four elements. | |
554 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | |
6308e208 | 555 | (V4HI "V4HI") (V8HI "V4HI") |
4b644867 | 556 | (V4HF "V4HF") (V8HF "V4HF") |
ceddf62c SN |
557 | (V2SI "V4SI") (V4SI "V4SI") |
558 | (V2SF "V4SF") (V4SF "V4SF") | |
559 | (DI "OI") (V2DI "OI")]) | |
560 | ||
561 | ;; Register width from element mode | |
562 | (define_mode_attr V_reg [(V8QI "P") (V16QI "q") | |
55a9b91b MW |
563 | (V4HI "P") (V8HI "q") |
564 | (V4HF "P") (V8HF "q") | |
565 | (V2SI "P") (V4SI "q") | |
566 | (V2SF "P") (V4SF "q") | |
567 | (DI "P") (V2DI "q") | |
06e95715 KT |
568 | (V2HF "") (SF "") |
569 | (DF "P") (HF "")]) | |
570 | ||
571 | ;; Output template to select the high VFP register of a mult-register value. | |
572 | (define_mode_attr V_hi [(V2SF "p") (V4SF "f")]) | |
573 | ||
574 | ;; Output template to select the low VFP register of a mult-register value. | |
575 | (define_mode_attr V_lo [(V2SF "") (V4SF "e")]) | |
ceddf62c | 576 | |
eccf4d70 KT |
577 | ;; Helper attribute for printing output templates for awkward forms of |
578 | ;; vfmlal/vfmlsl intrinsics. | |
579 | (define_mode_attr V_lane_reg [(V2SF "") (V4SF "P")]) | |
580 | ||
ceddf62c SN |
581 | ;; Wider modes with the same number of elements. |
582 | (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) | |
583 | ||
584 | ;; Narrower modes with the same number of elements. | |
585 | (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) | |
586 | ||
0f38f229 TB |
587 | ;; Narrower modes with double the number of elements. |
588 | (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") | |
589 | (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) | |
590 | ||
ceddf62c SN |
591 | ;; Modes with half the number of equal-sized elements. |
592 | (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") | |
4b644867 AL |
593 | (V8HF "V4HF") (V4SI "V2SI") |
594 | (V4SF "V2SF") (V2DF "DF") | |
55a9b91b | 595 | (V2DI "DI") (V4HF "HF")]) |
ceddf62c SN |
596 | |
597 | ;; Same, but lower-case. | |
598 | (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") | |
599 | (V4SI "v2si") (V4SF "v2sf") | |
600 | (V2DI "di")]) | |
601 | ||
602 | ;; Modes with twice the number of equal-sized elements. | |
603 | (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") | |
4b644867 AL |
604 | (V2SI "V4SI") (V4HF "V8HF") |
605 | (V2SF "V4SF") (DF "V2DF") | |
606 | (DI "V2DI")]) | |
ceddf62c SN |
607 | |
608 | ;; Same, but lower-case. | |
609 | (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") | |
610 | (V2SI "v4si") (V2SF "v4sf") | |
611 | (DI "v2di")]) | |
612 | ||
613 | ;; Modes with double-width elements. | |
614 | (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") | |
615 | (V4HI "V2SI") (V8HI "V4SI") | |
616 | (V2SI "DI") (V4SI "V2DI")]) | |
617 | ||
618 | ;; Double-sized modes with the same element size. | |
619 | ;; Used for neon_vdup_lane, where the second operand is double-sized | |
620 | ;; even when the first one is quad. | |
621 | (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | |
b1a970a5 MW |
622 | (V4SI "V2SI") (V4SF "V2SF") |
623 | (V8QI "V8QI") (V4HI "V4HI") | |
624 | (V2SI "V2SI") (V2SF "V2SF") | |
625 | (V8HF "V4HF") (V4HF "V4HF")]) | |
ceddf62c SN |
626 | |
627 | ;; Mode of result of comparison operations (and bit-select operand 1). | |
628 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
4b644867 | 629 | (V4HI "V4HI") (V8HI "V8HI") |
ceddf62c | 630 | (V2SI "V2SI") (V4SI "V4SI") |
4b644867 | 631 | (V4HF "V4HI") (V8HF "V8HI") |
ceddf62c SN |
632 | (V2SF "V2SI") (V4SF "V4SI") |
633 | (DI "DI") (V2DI "V2DI")]) | |
634 | ||
f35c297f KT |
635 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") |
636 | (V4HI "v4hi") (V8HI "v8hi") | |
637 | (V2SI "v2si") (V4SI "v4si") | |
638 | (DI "di") (V2DI "v2di") | |
639 | (V2SF "v2si") (V4SF "v4si")]) | |
640 | ||
ceddf62c SN |
641 | ;; Get element type from double-width mode, for operations where we |
642 | ;; don't care about signedness. | |
643 | (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") | |
55a9b91b MW |
644 | (V4HI "i16") (V8HI "i16") |
645 | (V2SI "i32") (V4SI "i32") | |
646 | (DI "i64") (V2DI "i64") | |
647 | (V2SF "f32") (V4SF "f32") | |
648 | (SF "f32") (DF "f64") | |
649 | (HF "f16") (V4HF "f16") | |
650 | (V8HF "f16")]) | |
ceddf62c SN |
651 | |
652 | ;; Same, but for operations which work on signed values. | |
653 | (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") | |
55a9b91b MW |
654 | (V4HI "s16") (V8HI "s16") |
655 | (V2SI "s32") (V4SI "s32") | |
656 | (DI "s64") (V2DI "s64") | |
657 | (V2SF "f32") (V4SF "f32") | |
658 | (HF "f16") (V4HF "f16") | |
659 | (V8HF "f16")]) | |
ceddf62c SN |
660 | |
661 | ;; Same, but for operations which work on unsigned values. | |
662 | (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") | |
663 | (V4HI "u16") (V8HI "u16") | |
664 | (V2SI "u32") (V4SI "u32") | |
665 | (DI "u64") (V2DI "u64") | |
666 | (V2SF "f32") (V4SF "f32")]) | |
667 | ||
668 | ;; Element types for extraction of unsigned scalars. | |
669 | (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") | |
670 | (V4HI "u16") (V8HI "u16") | |
671 | (V2SI "32") (V4SI "32") | |
4b644867 | 672 | (V4HF "u16") (V8HF "u16") |
ceddf62c SN |
673 | (V2SF "32") (V4SF "32")]) |
674 | ||
675 | (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") | |
55a9b91b MW |
676 | (V4HI "16") (V8HI "16") |
677 | (V2SI "32") (V4SI "32") | |
678 | (DI "64") (V2DI "64") | |
4b644867 | 679 | (V4HF "16") (V8HF "16") |
55a9b91b | 680 | (V2SF "32") (V4SF "32")]) |
ceddf62c | 681 | |
f7379e5e | 682 | (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") |
55a9b91b MW |
683 | (V4HI "h") (V8HI "h") |
684 | (V2SI "s") (V4SI "s") | |
685 | (DI "d") (V2DI "d") | |
686 | (V2SF "s") (V4SF "s") | |
687 | (V2SF "s") (V4SF "s")]) | |
688 | ||
689 | (define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s") | |
690 | (V4HF "s") (V8HF "s") | |
691 | (HF "s")]) | |
f7379e5e | 692 | |
ceddf62c SN |
693 | ;; Element sizes for duplicating ARM registers to all elements of a vector. |
694 | (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) | |
695 | ||
696 | ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) | |
697 | (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") | |
698 | (V4HI "TI") (V8HI "OI") | |
699 | (V2SI "TI") (V4SI "OI") | |
700 | (V2SF "TI") (V4SF "OI") | |
701 | (DI "TI") (V2DI "OI")]) | |
702 | ||
703 | ;; Same, but lower-case. | |
704 | (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") | |
705 | (V4HI "ti") (V8HI "oi") | |
706 | (V2SI "ti") (V4SI "oi") | |
707 | (V2SF "ti") (V4SF "oi") | |
708 | (DI "ti") (V2DI "oi")]) | |
709 | ||
710 | ;; Extra suffix on some 64-bit insn names (to avoid collision with standard | |
711 | ;; names which we don't want to define). | |
712 | (define_mode_attr V_suf64 [(V8QI "") (V16QI "") | |
713 | (V4HI "") (V8HI "") | |
714 | (V2SI "") (V4SI "") | |
715 | (V2SF "") (V4SF "") | |
716 | (DI "_neon") (V2DI "")]) | |
717 | ||
718 | ||
719 | ;; Scalars to be presented to scalar multiplication instructions | |
720 | ;; must satisfy the following constraints. | |
721 | ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. | |
722 | ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. | |
723 | ||
724 | ;; This mode attribute is used to obtain the correct register constraints. | |
725 | ||
726 | (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") | |
55a9b91b MW |
727 | (V8HI "x") (V4SI "t") (V4SF "t") |
728 | (V8HF "x") (V4HF "x")]) | |
ceddf62c | 729 | |
003bb7f3 | 730 | ;; Predicates used for setting type for neon instructions |
ceddf62c SN |
731 | |
732 | (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") | |
55a9b91b MW |
733 | (V4HI "false") (V8HI "false") |
734 | (V2SI "false") (V4SI "false") | |
735 | (V4HF "true") (V8HF "true") | |
736 | (V2SF "true") (V4SF "true") | |
737 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
738 | |
739 | (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") | |
b1a970a5 MW |
740 | (V4HI "true") (V8HI "true") |
741 | (V2SI "false") (V4SI "false") | |
742 | (V2SF "false") (V4SF "false") | |
743 | (DI "false") (V2DI "false")]) | |
ceddf62c SN |
744 | |
745 | (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") | |
55a9b91b MW |
746 | (V4HI "true") (V8HI "false") |
747 | (V2SI "true") (V4SI "false") | |
748 | (V2SF "true") (V4SF "false") | |
749 | (DI "true") (V2DI "false") | |
b1a970a5 | 750 | (V4HF "true") (V8HF "false")]) |
ceddf62c SN |
751 | |
752 | (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") | |
4b644867 | 753 | (V4HF "4") (V8HF "8") |
ceddf62c SN |
754 | (V4HI "4") (V8HI "8") |
755 | (V2SI "2") (V4SI "4") | |
756 | (V2SF "2") (V4SF "4") | |
0f38f229 TB |
757 | (DI "1") (V2DI "2") |
758 | (DF "1") (V2DF "2")]) | |
ceddf62c | 759 | |
46b57af1 TB |
760 | ;; Same as V_widen, but lower-case. |
761 | (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | |
762 | ||
763 | ;; Widen. Result is half the number of elements, but widened to double-width. | |
764 | (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | |
ceddf62c | 765 | |
da0a441d BS |
766 | ;; Conditions to be used in extend<mode>di patterns. |
767 | (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) | |
768 | (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") | |
769 | (QI "&& arm_arch6")]) | |
8d4f1548 | 770 | (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") |
c9cdcaa5 BS |
771 | (HI "nonimmediate_operand") |
772 | (QI "nonimmediate_operand")]) | |
8d4f1548 RR |
773 | (define_mode_attr qhs_extenddi_op [(SI "s_register_operand") |
774 | (HI "nonimmediate_operand") | |
775 | (QI "arm_reg_or_extendqisi_mem_op")]) | |
5c7c6c5f WD |
776 | (define_mode_attr qhs_extenddi_cstr [(SI "0,r,r") (HI "0,rm,rm") (QI "0,rUq,rm")]) |
777 | (define_mode_attr qhs_zextenddi_cstr [(SI "0,r") (HI "0,rm") (QI "0,rm")]) | |
da0a441d | 778 | |
655b30bf JB |
779 | ;; Mode attributes used for fixed-point support. |
780 | (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") | |
781 | (V2UHA "16") (UHA "16") | |
782 | (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") | |
783 | (V2HA "16") (HA "16") (SQ "") (SA "")]) | |
784 | ||
cf16f980 KT |
785 | (define_mode_attr qaddsub_clob_q [(V4UQQ "0") (V2UHQ "0") (UQQ "0") (UHQ "0") |
786 | (V2UHA "0") (UHA "0") | |
787 | (V4QQ "0") (V2HQ "0") (QQ "0") (HQ "0") | |
788 | (V2HA "0") (HA "0") (SQ "ARM_Q_BIT_READ") | |
789 | (SA "ARM_Q_BIT_READ")]) | |
790 | ||
36ba4aae IR |
791 | ;; Mode attribute for vshll. |
792 | (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) | |
793 | ||
1dd4fe1f | 794 | ;; Mode attributes used for VFP support. |
76f722f4 | 795 | (define_mode_attr F_constraint [(SF "t") (DF "w")]) |
1dd4fe1f KT |
796 | (define_mode_attr vfp_type [(SF "s") (DF "d")]) |
797 | (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) | |
c2b7062d | 798 | (define_mode_attr VF_constraint [(V4HF "t") (V8HF "t") (V2SF "t") (V4SF "w")]) |
76f722f4 | 799 | |
f7379e5e JG |
800 | ;; Mode attribute used to build the "type" attribute. |
801 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
55a9b91b MW |
802 | (V4HI "") (V8HI "_q") |
803 | (V2SI "") (V4SI "_q") | |
4b644867 | 804 | (V4HF "") (V8HF "_q") |
55a9b91b MW |
805 | (V2SF "") (V4SF "_q") |
806 | (V4HF "") (V8HF "_q") | |
807 | (DI "") (V2DI "_q") | |
808 | (DF "") (V2DF "_q") | |
809 | (HF "")]) | |
f7379e5e | 810 | |
94f0f2cc JG |
811 | (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) |
812 | ||
f8e109ba TC |
813 | (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) |
814 | (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) | |
815 | ||
ceddf62c SN |
816 | ;;---------------------------------------------------------------------------- |
817 | ;; Code attributes | |
818 | ;;---------------------------------------------------------------------------- | |
819 | ||
8b8ab8f4 RE |
820 | ;; Determine the mode of a 'wide compare', ie where the carry flag is |
821 | ;; propagated into the comparison. | |
822 | (define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_B")]) | |
823 | ||
ceddf62c SN |
824 | ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. |
825 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | |
826 | (umin "vmin") (umax "vmax")]) | |
827 | ||
f7379e5e JG |
828 | ;; Type attributes for vqh_ops and vqhs_ops iterators. |
829 | (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") | |
830 | (umin "minmax") (umax "minmax")]) | |
831 | ||
ceddf62c SN |
832 | ;; Signs of above, where relevant. |
833 | (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") | |
834 | (umax "u")]) | |
835 | ||
40858b9d WD |
836 | ;; Map rtl operator codes to optab names |
837 | (define_code_attr optab | |
1e271bee | 838 | [(and "and") |
40858b9d WD |
839 | (ior "ior") |
840 | (xor "xor")]) | |
46b57af1 TB |
841 | |
842 | ;; Assembler mnemonics for signedness of widening operations. | |
843 | (define_code_attr US [(sign_extend "s") (zero_extend "u")]) | |
22a8ab77 | 844 | (define_code_attr Us [(sign_extend "") (zero_extend "u")]) |
3f2dc806 | 845 | |
ababd936 KT |
846 | ;; Signedness suffix for float->fixed conversions. Empty for signed |
847 | ;; conversion. | |
848 | (define_code_attr su_optab [(fix "") (unsigned_fix "u")]) | |
849 | ||
850 | ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. | |
851 | (define_code_attr su [(fix "s") (unsigned_fix "u")]) | |
852 | ||
3f2dc806 AS |
853 | ;; Right shifts |
854 | (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) | |
855 | (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) | |
856 | ||
d403b8d4 MW |
857 | ;; String reprentations of operations on the sign of a number. |
858 | (define_code_attr absneg_str [(abs "abs") (neg "neg")]) | |
859 | ||
860 | ;; Conversions. | |
861 | (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) | |
862 | ||
55a9b91b MW |
863 | (define_code_attr float_sup [(unsigned_float "u") (float "s")]) |
864 | ||
865 | (define_code_attr float_SUP [(unsigned_float "U") (float "S")]) | |
866 | ||
1dd4fe1f KT |
867 | ;;---------------------------------------------------------------------------- |
868 | ;; Int attributes | |
869 | ;;---------------------------------------------------------------------------- | |
870 | ||
94f0f2cc JG |
871 | ;; Mapping between vector UNSPEC operations and the signed ('s'), |
872 | ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. | |
873 | (define_int_attr sup [ | |
53cd0ac6 | 874 | (UNSPEC_SXTB16 "s") (UNSPEC_UXTB16 "u") |
94f0f2cc JG |
875 | (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") |
876 | (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") | |
877 | (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") | |
878 | (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") | |
879 | (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") | |
880 | (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") | |
881 | (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") | |
882 | (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") | |
883 | (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") | |
884 | (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") | |
885 | (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") | |
886 | (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") | |
887 | (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") | |
888 | (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") | |
889 | (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") | |
84ae7213 | 890 | (UNSPEC_VABAL_S "s") (UNSPEC_VABAL_U "u") |
94f0f2cc JG |
891 | (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") |
892 | (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") | |
893 | (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") | |
894 | (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") | |
895 | (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") | |
896 | (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") | |
897 | (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") | |
898 | (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") | |
899 | (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") | |
d403b8d4 MW |
900 | (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u") |
901 | (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u") | |
902 | (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u") | |
903 | (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u") | |
94f0f2cc | 904 | (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") |
d403b8d4 MW |
905 | (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u") |
906 | (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u") | |
94f0f2cc JG |
907 | (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") |
908 | (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") | |
909 | (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") | |
910 | (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") | |
911 | (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") | |
912 | (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") | |
913 | (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") | |
914 | (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") | |
915 | (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") | |
916 | (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") | |
917 | (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") | |
918 | (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") | |
919 | (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") | |
920 | (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") | |
d403b8d4 | 921 | (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u") |
f8e109ba | 922 | (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u") |
0775830a | 923 | (UNSPEC_SSAT16 "s") (UNSPEC_USAT16 "u") |
94f0f2cc JG |
924 | ]) |
925 | ||
06e95715 KT |
926 | (define_int_attr vfml_half |
927 | [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")]) | |
928 | ||
929 | (define_int_attr vfml_half_selector | |
930 | [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")]) | |
931 | ||
d403b8d4 MW |
932 | (define_int_attr vcvth_op |
933 | [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a") | |
934 | (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m") | |
935 | (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n") | |
936 | (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")]) | |
937 | ||
938 | (define_int_attr fp16_rnd_str | |
939 | [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda") | |
940 | (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn") | |
941 | (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")]) | |
942 | ||
943 | (define_int_attr fp16_rnd_insn | |
944 | [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta") | |
945 | (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn") | |
946 | (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")]) | |
947 | ||
381811fa | 948 | (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") |
55a9b91b MW |
949 | (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") |
950 | (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") | |
951 | (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le") | |
952 | (UNSPEC_VCALT "lt")]) | |
381811fa | 953 | |
94f0f2cc JG |
954 | (define_int_attr r [ |
955 | (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") | |
956 | (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") | |
957 | (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") | |
958 | (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") | |
959 | (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") | |
960 | (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") | |
961 | ]) | |
962 | ||
963 | (define_int_attr maxmin [ | |
964 | (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") | |
965 | (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") | |
966 | (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") | |
967 | (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") | |
968 | ]) | |
969 | ||
0a18c19f DS |
970 | (define_int_attr fmaxmin [ |
971 | (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) | |
972 | ||
973 | (define_int_attr fmaxmin_op [ | |
974 | (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") | |
975 | ]) | |
976 | ||
94f0f2cc JG |
977 | (define_int_attr shift_op [ |
978 | (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") | |
979 | (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") | |
980 | (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") | |
981 | (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") | |
982 | (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") | |
983 | (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") | |
984 | (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") | |
985 | (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") | |
986 | (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") | |
987 | (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") | |
988 | (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") | |
989 | (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") | |
990 | ]) | |
991 | ||
1dd4fe1f KT |
992 | ;; Standard names for floating point to integral rounding instructions. |
993 | (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") | |
994 | (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") | |
995 | (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) | |
996 | ||
997 | ;; Suffixes for vrint instructions specifying rounding modes. | |
998 | (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") | |
999 | (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") | |
1000 | (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) | |
1001 | ||
1002 | ;; Some of the vrint instuctions are predicable. | |
1003 | (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") | |
1004 | (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") | |
1005 | (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) | |
79739965 | 1006 | |
fca0efeb KT |
1007 | (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") |
1008 | (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") | |
1009 | (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) | |
1010 | ||
79739965 KT |
1011 | (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") |
1012 | (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") | |
1013 | (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) | |
582e2e43 KT |
1014 | |
1015 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") | |
1016 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") | |
1017 | (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) | |
1018 | ||
1019 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
1020 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") | |
1021 | (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) | |
1022 | ||
021b5e6b KT |
1023 | (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") |
1024 | (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") | |
1025 | (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") | |
1026 | (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") | |
1027 | (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") | |
1028 | (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") | |
1029 | (UNSPEC_SHA256H2 "sha256h2") | |
1030 | (UNSPEC_SHA256SU1 "sha256su1")]) | |
1031 | ||
1032 | (define_int_attr crypto_type | |
b10baa95 KT |
1033 | [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") |
1034 | (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") | |
021b5e6b KT |
1035 | (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") |
1036 | (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") | |
1037 | (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") | |
1038 | (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") | |
1039 | (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) | |
1040 | ||
1041 | (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") | |
1042 | (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") | |
1043 | (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") | |
1044 | (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") | |
1045 | (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") | |
1046 | (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") | |
1047 | (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) | |
1048 | ||
1049 | (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") | |
1050 | (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") | |
1051 | (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") | |
1052 | (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") | |
1053 | (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") | |
1054 | (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") | |
1055 | (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) | |
1056 | ||
c2b7062d TC |
1057 | (define_int_attr rot [(UNSPEC_VCADD90 "90") |
1058 | (UNSPEC_VCADD270 "270") | |
1059 | (UNSPEC_VCMLA "0") | |
1060 | (UNSPEC_VCMLA90 "90") | |
1061 | (UNSPEC_VCMLA180 "180") | |
1062 | (UNSPEC_VCMLA270 "270")]) | |
1063 | ||
53cd0ac6 KT |
1064 | (define_int_attr simd32_op [(UNSPEC_QADD8 "qadd8") (UNSPEC_QSUB8 "qsub8") |
1065 | (UNSPEC_SHADD8 "shadd8") (UNSPEC_SHSUB8 "shsub8") | |
1066 | (UNSPEC_UHADD8 "uhadd8") (UNSPEC_UHSUB8 "uhsub8") | |
1067 | (UNSPEC_UQADD8 "uqadd8") (UNSPEC_UQSUB8 "uqsub8") | |
1068 | (UNSPEC_QADD16 "qadd16") (UNSPEC_QASX "qasx") | |
1069 | (UNSPEC_QSAX "qsax") (UNSPEC_QSUB16 "qsub16") | |
1070 | (UNSPEC_SHADD16 "shadd16") (UNSPEC_SHASX "shasx") | |
1071 | (UNSPEC_SHSAX "shsax") (UNSPEC_SHSUB16 "shsub16") | |
1072 | (UNSPEC_UHADD16 "uhadd16") (UNSPEC_UHASX "uhasx") | |
1073 | (UNSPEC_UHSAX "uhsax") (UNSPEC_UHSUB16 "uhsub16") | |
1074 | (UNSPEC_UQADD16 "uqadd16") (UNSPEC_UQASX "uqasx") | |
1075 | (UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16") | |
1076 | (UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx") | |
1077 | (UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16") | |
2b5b5e24 KT |
1078 | (UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald") |
1079 | (UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld") | |
16155ccf KT |
1080 | (UNSPEC_SMLSLDX "smlsldx")(UNSPEC_SADD8 "sadd8") |
1081 | (UNSPEC_UADD8 "uadd8") (UNSPEC_SSUB8 "ssub8") | |
1082 | (UNSPEC_USUB8 "usub8") (UNSPEC_SADD16 "sadd16") | |
1083 | (UNSPEC_SASX "sasx") (UNSPEC_SSAX "ssax") | |
1084 | (UNSPEC_SSUB16 "ssub16") (UNSPEC_UADD16 "uadd16") | |
1085 | (UNSPEC_UASX "uasx") (UNSPEC_USAX "usax") | |
65dd610d KT |
1086 | (UNSPEC_USUB16 "usub16") (UNSPEC_SMLAD "smlad") |
1087 | (UNSPEC_SMLADX "smladx") (UNSPEC_SMLSD "smlsd") | |
1088 | (UNSPEC_SMLSDX "smlsdx") (UNSPEC_SMUAD "smuad") | |
0775830a KT |
1089 | (UNSPEC_SMUADX "smuadx") (UNSPEC_SSAT16 "ssat16") |
1090 | (UNSPEC_USAT16 "usat16")]) | |
53cd0ac6 | 1091 | |
24d5b097 | 1092 | ;; Both kinds of return insn. |
728dc153 | 1093 | (define_code_iterator RETURNS [return simple_return]) |
24d5b097 XG |
1094 | (define_code_attr return_str [(return "") (simple_return "simple_")]) |
1095 | (define_code_attr return_simple_p [(return "false") (simple_return "true")]) | |
1096 | (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") | |
1097 | (simple_return " && use_simple_return_p ()")]) | |
1098 | (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") | |
1099 | (simple_return " && use_simple_return_p ()")]) | |
5f2ca3b2 MW |
1100 | |
1101 | ;; Attributes for VQRDMLAH/VQRDMLSH | |
1102 | (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) | |
55a9b91b MW |
1103 | |
1104 | ;; Attributes for VFMA_LANE/ VFMS_LANE | |
1105 | (define_int_attr neon_vfm_lane_as | |
1106 | [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")]) | |
d57daa0c AV |
1107 | |
1108 | ;; An iterator for the CDP coprocessor instructions | |
1109 | (define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2]) | |
1110 | (define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")]) | |
1111 | (define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")]) | |
3811581f AV |
1112 | |
1113 | ;; An iterator for the LDC coprocessor instruction | |
1114 | (define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2 | |
1115 | VUNSPEC_LDCL VUNSPEC_LDC2L]) | |
1116 | (define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2") | |
1117 | (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")]) | |
1118 | (define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2") | |
1119 | (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")]) | |
1120 | ||
1121 | ;; An iterator for the STC coprocessor instructions | |
1122 | (define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2 | |
1123 | VUNSPEC_STCL VUNSPEC_STC2L]) | |
1124 | (define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2") | |
1125 | (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")]) | |
1126 | (define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2") | |
1127 | (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")]) | |
ecc9a25b AV |
1128 | |
1129 | ;; An iterator for the MCR coprocessor instructions | |
1130 | (define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2]) | |
1131 | ||
1132 | (define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")]) | |
1133 | (define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")]) | |
1134 | ||
1135 | ;; An iterator for the MRC coprocessor instructions | |
1136 | (define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2]) | |
1137 | ||
1138 | (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) | |
1139 | (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) | |
f3caa118 AV |
1140 | |
1141 | ;; An iterator for the MCRR coprocessor instructions | |
1142 | (define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) | |
1143 | ||
1144 | (define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) | |
1145 | (define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) | |
1146 | ||
1147 | ;; An iterator for the MRRC coprocessor instructions | |
1148 | (define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) | |
1149 | ||
1150 | (define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) | |
1151 | (define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) | |
f8e109ba TC |
1152 | |
1153 | (define_int_attr opsuffix [(UNSPEC_DOT_S "s8") | |
1154 | (UNSPEC_DOT_U "u8")]) | |
08836731 KT |
1155 | |
1156 | (define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")]) |