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37119410 BS |
1 | /* ARM ldm/stm instruction patterns. This file was automatically generated |
2 | using arm-ldmstm.ml. Please do not edit manually. | |
3 | ||
99dee823 | 4 | Copyright (C) 2010-2021 Free Software Foundation, Inc. |
37119410 BS |
5 | Contributed by CodeSourcery. |
6 | ||
7 | This file is part of GCC. | |
8 | ||
9 | GCC is free software; you can redistribute it and/or modify it | |
10 | under the terms of the GNU General Public License as published | |
11 | by the Free Software Foundation; either version 3, or (at your | |
12 | option) any later version. | |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License and | |
20 | a copy of the GCC Runtime Library Exception along with this program; | |
21 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
22 | <http://www.gnu.org/licenses/>. */ | |
23 | ||
bae4ce0f | 24 | (define_insn "*ldm4_" |
37119410 | 25 | [(match_parallel 0 "load_multiple_operation" |
03158648 | 26 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 27 | (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) |
03158648 | 28 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
29 | (mem:SI (plus:SI (match_dup 5) |
30 | (const_int 4)))) | |
03158648 | 31 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
32 | (mem:SI (plus:SI (match_dup 5) |
33 | (const_int 8)))) | |
03158648 | 34 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
35 | (mem:SI (plus:SI (match_dup 5) |
36 | (const_int 12))))])] | |
37 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 38 | "ldm%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 39 | [(set_attr "type" "load_16") |
113c53c3 | 40 | (set_attr "predicable" "yes")]) |
37119410 BS |
41 | |
42 | (define_insn "*thumb_ldm4_ia" | |
43 | [(match_parallel 0 "load_multiple_operation" | |
9f178d6a | 44 | [(set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 45 | (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) |
9f178d6a | 46 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
47 | (mem:SI (plus:SI (match_dup 5) |
48 | (const_int 4)))) | |
9f178d6a | 49 | (set (match_operand:SI 3 "low_register_operand" "") |
37119410 BS |
50 | (mem:SI (plus:SI (match_dup 5) |
51 | (const_int 8)))) | |
9f178d6a | 52 | (set (match_operand:SI 4 "low_register_operand" "") |
37119410 BS |
53 | (mem:SI (plus:SI (match_dup 5) |
54 | (const_int 12))))])] | |
55 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 56 | "ldmia\t%5, {%1, %2, %3, %4}" |
89b2133e | 57 | [(set_attr "type" "load_16")]) |
37119410 BS |
58 | |
59 | (define_insn "*ldm4_ia_update" | |
60 | [(match_parallel 0 "load_multiple_operation" | |
61 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
62 | (plus:SI (match_dup 5) (const_int 16))) | |
03158648 | 63 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 64 | (mem:SI (match_dup 5))) |
03158648 | 65 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
66 | (mem:SI (plus:SI (match_dup 5) |
67 | (const_int 4)))) | |
03158648 | 68 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
69 | (mem:SI (plus:SI (match_dup 5) |
70 | (const_int 8)))) | |
03158648 | 71 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
72 | (mem:SI (plus:SI (match_dup 5) |
73 | (const_int 12))))])] | |
74 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | |
bae4ce0f | 75 | "ldmia%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 76 | [(set_attr "type" "load_16") |
113c53c3 | 77 | (set_attr "predicable" "yes")]) |
37119410 BS |
78 | |
79 | (define_insn "*thumb_ldm4_ia_update" | |
80 | [(match_parallel 0 "load_multiple_operation" | |
81 | [(set (match_operand:SI 5 "s_register_operand" "+&l") | |
82 | (plus:SI (match_dup 5) (const_int 16))) | |
9f178d6a | 83 | (set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 84 | (mem:SI (match_dup 5))) |
9f178d6a | 85 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
86 | (mem:SI (plus:SI (match_dup 5) |
87 | (const_int 4)))) | |
9f178d6a | 88 | (set (match_operand:SI 3 "low_register_operand" "") |
37119410 BS |
89 | (mem:SI (plus:SI (match_dup 5) |
90 | (const_int 8)))) | |
9f178d6a | 91 | (set (match_operand:SI 4 "low_register_operand" "") |
37119410 BS |
92 | (mem:SI (plus:SI (match_dup 5) |
93 | (const_int 12))))])] | |
94 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | |
bae4ce0f | 95 | "ldmia\t%5!, {%1, %2, %3, %4}" |
89b2133e | 96 | [(set_attr "type" "load_16")]) |
37119410 | 97 | |
bae4ce0f | 98 | (define_insn "*stm4_" |
37119410 BS |
99 | [(match_parallel 0 "store_multiple_operation" |
100 | [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) | |
03158648 | 101 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 102 | (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) |
03158648 | 103 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 104 | (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) |
03158648 | 105 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 106 | (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) |
03158648 | 107 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 108 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 109 | "stm%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 110 | [(set_attr "type" "store_16") |
113c53c3 | 111 | (set_attr "predicable" "yes")]) |
37119410 BS |
112 | |
113 | (define_insn "*stm4_ia_update" | |
114 | [(match_parallel 0 "store_multiple_operation" | |
115 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
116 | (plus:SI (match_dup 5) (const_int 16))) | |
117 | (set (mem:SI (match_dup 5)) | |
03158648 | 118 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 119 | (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) |
03158648 | 120 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 121 | (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) |
03158648 | 122 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 123 | (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) |
03158648 | 124 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 125 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" |
bae4ce0f | 126 | "stmia%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 127 | [(set_attr "type" "store_16") |
113c53c3 | 128 | (set_attr "predicable" "yes")]) |
37119410 BS |
129 | |
130 | (define_insn "*thumb_stm4_ia_update" | |
131 | [(match_parallel 0 "store_multiple_operation" | |
132 | [(set (match_operand:SI 5 "s_register_operand" "+&l") | |
133 | (plus:SI (match_dup 5) (const_int 16))) | |
134 | (set (mem:SI (match_dup 5)) | |
9f178d6a | 135 | (match_operand:SI 1 "low_register_operand" "")) |
37119410 | 136 | (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) |
9f178d6a | 137 | (match_operand:SI 2 "low_register_operand" "")) |
37119410 | 138 | (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) |
9f178d6a | 139 | (match_operand:SI 3 "low_register_operand" "")) |
37119410 | 140 | (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) |
9f178d6a | 141 | (match_operand:SI 4 "low_register_operand" ""))])] |
37119410 | 142 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" |
bae4ce0f | 143 | "stmia\t%5!, {%1, %2, %3, %4}" |
89b2133e | 144 | [(set_attr "type" "store_16")]) |
37119410 BS |
145 | |
146 | (define_insn "*ldm4_ib" | |
147 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 148 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
149 | (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") |
150 | (const_int 4)))) | |
03158648 | 151 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
152 | (mem:SI (plus:SI (match_dup 5) |
153 | (const_int 8)))) | |
03158648 | 154 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
155 | (mem:SI (plus:SI (match_dup 5) |
156 | (const_int 12)))) | |
03158648 | 157 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
158 | (mem:SI (plus:SI (match_dup 5) |
159 | (const_int 16))))])] | |
160 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 161 | "ldmib%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 162 | [(set_attr "type" "load_16") |
37119410 BS |
163 | (set_attr "predicable" "yes")]) |
164 | ||
165 | (define_insn "*ldm4_ib_update" | |
166 | [(match_parallel 0 "load_multiple_operation" | |
167 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
168 | (plus:SI (match_dup 5) (const_int 16))) | |
03158648 | 169 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
170 | (mem:SI (plus:SI (match_dup 5) |
171 | (const_int 4)))) | |
03158648 | 172 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
173 | (mem:SI (plus:SI (match_dup 5) |
174 | (const_int 8)))) | |
03158648 | 175 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
176 | (mem:SI (plus:SI (match_dup 5) |
177 | (const_int 12)))) | |
03158648 | 178 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
179 | (mem:SI (plus:SI (match_dup 5) |
180 | (const_int 16))))])] | |
181 | "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | |
bae4ce0f | 182 | "ldmib%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 183 | [(set_attr "type" "load_16") |
37119410 BS |
184 | (set_attr "predicable" "yes")]) |
185 | ||
186 | (define_insn "*stm4_ib" | |
187 | [(match_parallel 0 "store_multiple_operation" | |
188 | [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) | |
03158648 | 189 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 190 | (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) |
03158648 | 191 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 192 | (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) |
03158648 | 193 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 194 | (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) |
03158648 | 195 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 196 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 197 | "stmib%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 198 | [(set_attr "type" "store_16") |
37119410 BS |
199 | (set_attr "predicable" "yes")]) |
200 | ||
201 | (define_insn "*stm4_ib_update" | |
202 | [(match_parallel 0 "store_multiple_operation" | |
203 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
204 | (plus:SI (match_dup 5) (const_int 16))) | |
205 | (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) | |
03158648 | 206 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 207 | (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) |
03158648 | 208 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 209 | (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) |
03158648 | 210 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 211 | (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) |
03158648 | 212 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 213 | "TARGET_ARM && XVECLEN (operands[0], 0) == 5" |
bae4ce0f | 214 | "stmib%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 215 | [(set_attr "type" "store_16") |
37119410 BS |
216 | (set_attr "predicable" "yes")]) |
217 | ||
218 | (define_insn "*ldm4_da" | |
219 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 220 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
221 | (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") |
222 | (const_int -12)))) | |
03158648 | 223 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
224 | (mem:SI (plus:SI (match_dup 5) |
225 | (const_int -8)))) | |
03158648 | 226 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
227 | (mem:SI (plus:SI (match_dup 5) |
228 | (const_int -4)))) | |
03158648 | 229 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
230 | (mem:SI (match_dup 5)))])] |
231 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 232 | "ldmda%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 233 | [(set_attr "type" "load_16") |
37119410 BS |
234 | (set_attr "predicable" "yes")]) |
235 | ||
236 | (define_insn "*ldm4_da_update" | |
237 | [(match_parallel 0 "load_multiple_operation" | |
238 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
239 | (plus:SI (match_dup 5) (const_int -16))) | |
03158648 | 240 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
241 | (mem:SI (plus:SI (match_dup 5) |
242 | (const_int -12)))) | |
03158648 | 243 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
244 | (mem:SI (plus:SI (match_dup 5) |
245 | (const_int -8)))) | |
03158648 | 246 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
247 | (mem:SI (plus:SI (match_dup 5) |
248 | (const_int -4)))) | |
03158648 | 249 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
250 | (mem:SI (match_dup 5)))])] |
251 | "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | |
bae4ce0f | 252 | "ldmda%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 253 | [(set_attr "type" "load_16") |
37119410 BS |
254 | (set_attr "predicable" "yes")]) |
255 | ||
256 | (define_insn "*stm4_da" | |
257 | [(match_parallel 0 "store_multiple_operation" | |
258 | [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) | |
03158648 | 259 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 260 | (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) |
03158648 | 261 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 262 | (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) |
03158648 | 263 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 264 | (set (mem:SI (match_dup 5)) |
03158648 | 265 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 266 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 267 | "stmda%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 268 | [(set_attr "type" "store_16") |
37119410 BS |
269 | (set_attr "predicable" "yes")]) |
270 | ||
271 | (define_insn "*stm4_da_update" | |
272 | [(match_parallel 0 "store_multiple_operation" | |
273 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
274 | (plus:SI (match_dup 5) (const_int -16))) | |
275 | (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) | |
03158648 | 276 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 277 | (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) |
03158648 | 278 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 279 | (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) |
03158648 | 280 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 281 | (set (mem:SI (match_dup 5)) |
03158648 | 282 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 283 | "TARGET_ARM && XVECLEN (operands[0], 0) == 5" |
bae4ce0f | 284 | "stmda%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 285 | [(set_attr "type" "store_16") |
37119410 BS |
286 | (set_attr "predicable" "yes")]) |
287 | ||
288 | (define_insn "*ldm4_db" | |
289 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 290 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
291 | (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") |
292 | (const_int -16)))) | |
03158648 | 293 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
294 | (mem:SI (plus:SI (match_dup 5) |
295 | (const_int -12)))) | |
03158648 | 296 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
297 | (mem:SI (plus:SI (match_dup 5) |
298 | (const_int -8)))) | |
03158648 | 299 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
300 | (mem:SI (plus:SI (match_dup 5) |
301 | (const_int -4))))])] | |
302 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 303 | "ldmdb%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 304 | [(set_attr "type" "load_16") |
113c53c3 | 305 | (set_attr "predicable" "yes")]) |
37119410 BS |
306 | |
307 | (define_insn "*ldm4_db_update" | |
308 | [(match_parallel 0 "load_multiple_operation" | |
309 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
310 | (plus:SI (match_dup 5) (const_int -16))) | |
03158648 | 311 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
312 | (mem:SI (plus:SI (match_dup 5) |
313 | (const_int -16)))) | |
03158648 | 314 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
315 | (mem:SI (plus:SI (match_dup 5) |
316 | (const_int -12)))) | |
03158648 | 317 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
318 | (mem:SI (plus:SI (match_dup 5) |
319 | (const_int -8)))) | |
03158648 | 320 | (set (match_operand:SI 4 "arm_hard_general_register_operand" "") |
37119410 BS |
321 | (mem:SI (plus:SI (match_dup 5) |
322 | (const_int -4))))])] | |
323 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | |
bae4ce0f | 324 | "ldmdb%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 325 | [(set_attr "type" "load_16") |
113c53c3 | 326 | (set_attr "predicable" "yes")]) |
37119410 BS |
327 | |
328 | (define_insn "*stm4_db" | |
329 | [(match_parallel 0 "store_multiple_operation" | |
330 | [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) | |
03158648 | 331 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 332 | (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) |
03158648 | 333 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 334 | (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) |
03158648 | 335 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 336 | (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) |
03158648 | 337 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 338 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 339 | "stmdb%?\t%5, {%1, %2, %3, %4}" |
89b2133e | 340 | [(set_attr "type" "store_16") |
113c53c3 | 341 | (set_attr "predicable" "yes")]) |
37119410 BS |
342 | |
343 | (define_insn "*stm4_db_update" | |
344 | [(match_parallel 0 "store_multiple_operation" | |
345 | [(set (match_operand:SI 5 "s_register_operand" "+&rk") | |
346 | (plus:SI (match_dup 5) (const_int -16))) | |
347 | (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) | |
03158648 | 348 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 349 | (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) |
03158648 | 350 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 351 | (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) |
03158648 | 352 | (match_operand:SI 3 "arm_hard_general_register_operand" "")) |
37119410 | 353 | (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) |
03158648 | 354 | (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] |
37119410 | 355 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" |
bae4ce0f | 356 | "stmdb%?\t%5!, {%1, %2, %3, %4}" |
89b2133e | 357 | [(set_attr "type" "store_16") |
113c53c3 | 358 | (set_attr "predicable" "yes")]) |
37119410 BS |
359 | |
360 | (define_peephole2 | |
361 | [(set (match_operand:SI 0 "s_register_operand" "") | |
362 | (match_operand:SI 4 "memory_operand" "")) | |
363 | (set (match_operand:SI 1 "s_register_operand" "") | |
364 | (match_operand:SI 5 "memory_operand" "")) | |
365 | (set (match_operand:SI 2 "s_register_operand" "") | |
366 | (match_operand:SI 6 "memory_operand" "")) | |
367 | (set (match_operand:SI 3 "s_register_operand" "") | |
368 | (match_operand:SI 7 "memory_operand" ""))] | |
369 | "" | |
370 | [(const_int 0)] | |
371 | { | |
372 | if (gen_ldm_seq (operands, 4, false)) | |
373 | DONE; | |
374 | else | |
375 | FAIL; | |
376 | }) | |
377 | ||
378 | (define_peephole2 | |
379 | [(set (match_operand:SI 0 "s_register_operand" "") | |
380 | (match_operand:SI 4 "memory_operand" "")) | |
381 | (parallel | |
382 | [(set (match_operand:SI 1 "s_register_operand" "") | |
383 | (match_operand:SI 5 "memory_operand" "")) | |
384 | (set (match_operand:SI 2 "s_register_operand" "") | |
385 | (match_operand:SI 6 "memory_operand" "")) | |
386 | (set (match_operand:SI 3 "s_register_operand" "") | |
387 | (match_operand:SI 7 "memory_operand" ""))])] | |
388 | "" | |
389 | [(const_int 0)] | |
390 | { | |
391 | if (gen_ldm_seq (operands, 4, false)) | |
392 | DONE; | |
393 | else | |
394 | FAIL; | |
395 | }) | |
396 | ||
397 | (define_peephole2 | |
398 | [(set (match_operand:SI 0 "s_register_operand" "") | |
399 | (match_operand:SI 8 "const_int_operand" "")) | |
400 | (set (match_operand:SI 4 "memory_operand" "") | |
401 | (match_dup 0)) | |
402 | (set (match_operand:SI 1 "s_register_operand" "") | |
403 | (match_operand:SI 9 "const_int_operand" "")) | |
404 | (set (match_operand:SI 5 "memory_operand" "") | |
405 | (match_dup 1)) | |
406 | (set (match_operand:SI 2 "s_register_operand" "") | |
407 | (match_operand:SI 10 "const_int_operand" "")) | |
408 | (set (match_operand:SI 6 "memory_operand" "") | |
409 | (match_dup 2)) | |
410 | (set (match_operand:SI 3 "s_register_operand" "") | |
411 | (match_operand:SI 11 "const_int_operand" "")) | |
412 | (set (match_operand:SI 7 "memory_operand" "") | |
413 | (match_dup 3))] | |
414 | "" | |
415 | [(const_int 0)] | |
416 | { | |
417 | if (gen_const_stm_seq (operands, 4)) | |
418 | DONE; | |
419 | else | |
420 | FAIL; | |
421 | }) | |
422 | ||
423 | (define_peephole2 | |
424 | [(set (match_operand:SI 0 "s_register_operand" "") | |
425 | (match_operand:SI 8 "const_int_operand" "")) | |
426 | (set (match_operand:SI 1 "s_register_operand" "") | |
427 | (match_operand:SI 9 "const_int_operand" "")) | |
428 | (set (match_operand:SI 2 "s_register_operand" "") | |
429 | (match_operand:SI 10 "const_int_operand" "")) | |
430 | (set (match_operand:SI 3 "s_register_operand" "") | |
431 | (match_operand:SI 11 "const_int_operand" "")) | |
432 | (set (match_operand:SI 4 "memory_operand" "") | |
433 | (match_dup 0)) | |
434 | (set (match_operand:SI 5 "memory_operand" "") | |
435 | (match_dup 1)) | |
436 | (set (match_operand:SI 6 "memory_operand" "") | |
437 | (match_dup 2)) | |
438 | (set (match_operand:SI 7 "memory_operand" "") | |
439 | (match_dup 3))] | |
440 | "" | |
441 | [(const_int 0)] | |
442 | { | |
443 | if (gen_const_stm_seq (operands, 4)) | |
444 | DONE; | |
445 | else | |
446 | FAIL; | |
447 | }) | |
448 | ||
449 | (define_peephole2 | |
450 | [(set (match_operand:SI 4 "memory_operand" "") | |
451 | (match_operand:SI 0 "s_register_operand" "")) | |
452 | (set (match_operand:SI 5 "memory_operand" "") | |
453 | (match_operand:SI 1 "s_register_operand" "")) | |
454 | (set (match_operand:SI 6 "memory_operand" "") | |
455 | (match_operand:SI 2 "s_register_operand" "")) | |
456 | (set (match_operand:SI 7 "memory_operand" "") | |
457 | (match_operand:SI 3 "s_register_operand" ""))] | |
458 | "" | |
459 | [(const_int 0)] | |
460 | { | |
461 | if (gen_stm_seq (operands, 4)) | |
462 | DONE; | |
463 | else | |
464 | FAIL; | |
465 | }) | |
466 | ||
bae4ce0f | 467 | (define_insn "*ldm3_" |
37119410 | 468 | [(match_parallel 0 "load_multiple_operation" |
03158648 | 469 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 470 | (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) |
03158648 | 471 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
472 | (mem:SI (plus:SI (match_dup 4) |
473 | (const_int 4)))) | |
03158648 | 474 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
475 | (mem:SI (plus:SI (match_dup 4) |
476 | (const_int 8))))])] | |
477 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 478 | "ldm%?\t%4, {%1, %2, %3}" |
89b2133e | 479 | [(set_attr "type" "load_12") |
113c53c3 | 480 | (set_attr "predicable" "yes")]) |
37119410 BS |
481 | |
482 | (define_insn "*thumb_ldm3_ia" | |
483 | [(match_parallel 0 "load_multiple_operation" | |
9f178d6a | 484 | [(set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 485 | (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) |
9f178d6a | 486 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
487 | (mem:SI (plus:SI (match_dup 4) |
488 | (const_int 4)))) | |
9f178d6a | 489 | (set (match_operand:SI 3 "low_register_operand" "") |
37119410 BS |
490 | (mem:SI (plus:SI (match_dup 4) |
491 | (const_int 8))))])] | |
492 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 493 | "ldmia\t%4, {%1, %2, %3}" |
89b2133e | 494 | [(set_attr "type" "load_12")]) |
37119410 BS |
495 | |
496 | (define_insn "*ldm3_ia_update" | |
497 | [(match_parallel 0 "load_multiple_operation" | |
498 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
499 | (plus:SI (match_dup 4) (const_int 12))) | |
03158648 | 500 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 501 | (mem:SI (match_dup 4))) |
03158648 | 502 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
503 | (mem:SI (plus:SI (match_dup 4) |
504 | (const_int 4)))) | |
03158648 | 505 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
506 | (mem:SI (plus:SI (match_dup 4) |
507 | (const_int 8))))])] | |
508 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 509 | "ldmia%?\t%4!, {%1, %2, %3}" |
89b2133e | 510 | [(set_attr "type" "load_12") |
113c53c3 | 511 | (set_attr "predicable" "yes")]) |
37119410 BS |
512 | |
513 | (define_insn "*thumb_ldm3_ia_update" | |
514 | [(match_parallel 0 "load_multiple_operation" | |
515 | [(set (match_operand:SI 4 "s_register_operand" "+&l") | |
516 | (plus:SI (match_dup 4) (const_int 12))) | |
9f178d6a | 517 | (set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 518 | (mem:SI (match_dup 4))) |
9f178d6a | 519 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
520 | (mem:SI (plus:SI (match_dup 4) |
521 | (const_int 4)))) | |
9f178d6a | 522 | (set (match_operand:SI 3 "low_register_operand" "") |
37119410 BS |
523 | (mem:SI (plus:SI (match_dup 4) |
524 | (const_int 8))))])] | |
525 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 526 | "ldmia\t%4!, {%1, %2, %3}" |
89b2133e | 527 | [(set_attr "type" "load_12")]) |
37119410 | 528 | |
bae4ce0f | 529 | (define_insn "*stm3_" |
37119410 BS |
530 | [(match_parallel 0 "store_multiple_operation" |
531 | [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) | |
03158648 | 532 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 533 | (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) |
03158648 | 534 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 535 | (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) |
03158648 | 536 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 537 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 538 | "stm%?\t%4, {%1, %2, %3}" |
89b2133e | 539 | [(set_attr "type" "store_12") |
113c53c3 | 540 | (set_attr "predicable" "yes")]) |
37119410 BS |
541 | |
542 | (define_insn "*stm3_ia_update" | |
543 | [(match_parallel 0 "store_multiple_operation" | |
544 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
545 | (plus:SI (match_dup 4) (const_int 12))) | |
546 | (set (mem:SI (match_dup 4)) | |
03158648 | 547 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 548 | (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) |
03158648 | 549 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 550 | (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) |
03158648 | 551 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 552 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 553 | "stmia%?\t%4!, {%1, %2, %3}" |
89b2133e | 554 | [(set_attr "type" "store_12") |
113c53c3 | 555 | (set_attr "predicable" "yes")]) |
37119410 BS |
556 | |
557 | (define_insn "*thumb_stm3_ia_update" | |
558 | [(match_parallel 0 "store_multiple_operation" | |
559 | [(set (match_operand:SI 4 "s_register_operand" "+&l") | |
560 | (plus:SI (match_dup 4) (const_int 12))) | |
561 | (set (mem:SI (match_dup 4)) | |
9f178d6a | 562 | (match_operand:SI 1 "low_register_operand" "")) |
37119410 | 563 | (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) |
9f178d6a | 564 | (match_operand:SI 2 "low_register_operand" "")) |
37119410 | 565 | (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) |
9f178d6a | 566 | (match_operand:SI 3 "low_register_operand" ""))])] |
37119410 | 567 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 568 | "stmia\t%4!, {%1, %2, %3}" |
89b2133e | 569 | [(set_attr "type" "store_12")]) |
37119410 BS |
570 | |
571 | (define_insn "*ldm3_ib" | |
572 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 573 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
574 | (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") |
575 | (const_int 4)))) | |
03158648 | 576 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
577 | (mem:SI (plus:SI (match_dup 4) |
578 | (const_int 8)))) | |
03158648 | 579 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
580 | (mem:SI (plus:SI (match_dup 4) |
581 | (const_int 12))))])] | |
582 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 583 | "ldmib%?\t%4, {%1, %2, %3}" |
89b2133e | 584 | [(set_attr "type" "load_12") |
37119410 BS |
585 | (set_attr "predicable" "yes")]) |
586 | ||
587 | (define_insn "*ldm3_ib_update" | |
588 | [(match_parallel 0 "load_multiple_operation" | |
589 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
590 | (plus:SI (match_dup 4) (const_int 12))) | |
03158648 | 591 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
592 | (mem:SI (plus:SI (match_dup 4) |
593 | (const_int 4)))) | |
03158648 | 594 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
595 | (mem:SI (plus:SI (match_dup 4) |
596 | (const_int 8)))) | |
03158648 | 597 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
598 | (mem:SI (plus:SI (match_dup 4) |
599 | (const_int 12))))])] | |
600 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 601 | "ldmib%?\t%4!, {%1, %2, %3}" |
89b2133e | 602 | [(set_attr "type" "load_12") |
37119410 BS |
603 | (set_attr "predicable" "yes")]) |
604 | ||
605 | (define_insn "*stm3_ib" | |
606 | [(match_parallel 0 "store_multiple_operation" | |
607 | [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) | |
03158648 | 608 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 609 | (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) |
03158648 | 610 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 611 | (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) |
03158648 | 612 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 613 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 614 | "stmib%?\t%4, {%1, %2, %3}" |
89b2133e | 615 | [(set_attr "type" "store_12") |
37119410 BS |
616 | (set_attr "predicable" "yes")]) |
617 | ||
618 | (define_insn "*stm3_ib_update" | |
619 | [(match_parallel 0 "store_multiple_operation" | |
620 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
621 | (plus:SI (match_dup 4) (const_int 12))) | |
622 | (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) | |
03158648 | 623 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 624 | (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) |
03158648 | 625 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 626 | (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) |
03158648 | 627 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 628 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 629 | "stmib%?\t%4!, {%1, %2, %3}" |
89b2133e | 630 | [(set_attr "type" "store_12") |
37119410 BS |
631 | (set_attr "predicable" "yes")]) |
632 | ||
633 | (define_insn "*ldm3_da" | |
634 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 635 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
636 | (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") |
637 | (const_int -8)))) | |
03158648 | 638 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
639 | (mem:SI (plus:SI (match_dup 4) |
640 | (const_int -4)))) | |
03158648 | 641 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
642 | (mem:SI (match_dup 4)))])] |
643 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 644 | "ldmda%?\t%4, {%1, %2, %3}" |
89b2133e | 645 | [(set_attr "type" "load_12") |
37119410 BS |
646 | (set_attr "predicable" "yes")]) |
647 | ||
648 | (define_insn "*ldm3_da_update" | |
649 | [(match_parallel 0 "load_multiple_operation" | |
650 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
651 | (plus:SI (match_dup 4) (const_int -12))) | |
03158648 | 652 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
653 | (mem:SI (plus:SI (match_dup 4) |
654 | (const_int -8)))) | |
03158648 | 655 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
656 | (mem:SI (plus:SI (match_dup 4) |
657 | (const_int -4)))) | |
03158648 | 658 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
659 | (mem:SI (match_dup 4)))])] |
660 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 661 | "ldmda%?\t%4!, {%1, %2, %3}" |
89b2133e | 662 | [(set_attr "type" "load_12") |
37119410 BS |
663 | (set_attr "predicable" "yes")]) |
664 | ||
665 | (define_insn "*stm3_da" | |
666 | [(match_parallel 0 "store_multiple_operation" | |
667 | [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) | |
03158648 | 668 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 669 | (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) |
03158648 | 670 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 671 | (set (mem:SI (match_dup 4)) |
03158648 | 672 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 673 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 674 | "stmda%?\t%4, {%1, %2, %3}" |
89b2133e | 675 | [(set_attr "type" "store_12") |
37119410 BS |
676 | (set_attr "predicable" "yes")]) |
677 | ||
678 | (define_insn "*stm3_da_update" | |
679 | [(match_parallel 0 "store_multiple_operation" | |
680 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
681 | (plus:SI (match_dup 4) (const_int -12))) | |
682 | (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) | |
03158648 | 683 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 684 | (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) |
03158648 | 685 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 686 | (set (mem:SI (match_dup 4)) |
03158648 | 687 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 688 | "TARGET_ARM && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 689 | "stmda%?\t%4!, {%1, %2, %3}" |
89b2133e | 690 | [(set_attr "type" "store_12") |
37119410 BS |
691 | (set_attr "predicable" "yes")]) |
692 | ||
693 | (define_insn "*ldm3_db" | |
694 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 695 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
696 | (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") |
697 | (const_int -12)))) | |
03158648 | 698 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
699 | (mem:SI (plus:SI (match_dup 4) |
700 | (const_int -8)))) | |
03158648 | 701 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
702 | (mem:SI (plus:SI (match_dup 4) |
703 | (const_int -4))))])] | |
704 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 705 | "ldmdb%?\t%4, {%1, %2, %3}" |
89b2133e | 706 | [(set_attr "type" "load_12") |
113c53c3 | 707 | (set_attr "predicable" "yes")]) |
37119410 BS |
708 | |
709 | (define_insn "*ldm3_db_update" | |
710 | [(match_parallel 0 "load_multiple_operation" | |
711 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
712 | (plus:SI (match_dup 4) (const_int -12))) | |
03158648 | 713 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
714 | (mem:SI (plus:SI (match_dup 4) |
715 | (const_int -12)))) | |
03158648 | 716 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
717 | (mem:SI (plus:SI (match_dup 4) |
718 | (const_int -8)))) | |
03158648 | 719 | (set (match_operand:SI 3 "arm_hard_general_register_operand" "") |
37119410 BS |
720 | (mem:SI (plus:SI (match_dup 4) |
721 | (const_int -4))))])] | |
722 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | |
bae4ce0f | 723 | "ldmdb%?\t%4!, {%1, %2, %3}" |
89b2133e | 724 | [(set_attr "type" "load_12") |
113c53c3 | 725 | (set_attr "predicable" "yes")]) |
37119410 BS |
726 | |
727 | (define_insn "*stm3_db" | |
728 | [(match_parallel 0 "store_multiple_operation" | |
729 | [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) | |
03158648 | 730 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 731 | (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) |
03158648 | 732 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 733 | (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) |
03158648 | 734 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 735 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 736 | "stmdb%?\t%4, {%1, %2, %3}" |
89b2133e | 737 | [(set_attr "type" "store_12") |
113c53c3 | 738 | (set_attr "predicable" "yes")]) |
37119410 BS |
739 | |
740 | (define_insn "*stm3_db_update" | |
741 | [(match_parallel 0 "store_multiple_operation" | |
742 | [(set (match_operand:SI 4 "s_register_operand" "+&rk") | |
743 | (plus:SI (match_dup 4) (const_int -12))) | |
744 | (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) | |
03158648 | 745 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 746 | (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) |
03158648 | 747 | (match_operand:SI 2 "arm_hard_general_register_operand" "")) |
37119410 | 748 | (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) |
03158648 | 749 | (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] |
37119410 | 750 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" |
bae4ce0f | 751 | "stmdb%?\t%4!, {%1, %2, %3}" |
89b2133e | 752 | [(set_attr "type" "store_12") |
113c53c3 | 753 | (set_attr "predicable" "yes")]) |
37119410 BS |
754 | |
755 | (define_peephole2 | |
756 | [(set (match_operand:SI 0 "s_register_operand" "") | |
757 | (match_operand:SI 3 "memory_operand" "")) | |
758 | (set (match_operand:SI 1 "s_register_operand" "") | |
759 | (match_operand:SI 4 "memory_operand" "")) | |
760 | (set (match_operand:SI 2 "s_register_operand" "") | |
761 | (match_operand:SI 5 "memory_operand" ""))] | |
762 | "" | |
763 | [(const_int 0)] | |
764 | { | |
765 | if (gen_ldm_seq (operands, 3, false)) | |
766 | DONE; | |
767 | else | |
768 | FAIL; | |
769 | }) | |
770 | ||
771 | (define_peephole2 | |
772 | [(set (match_operand:SI 0 "s_register_operand" "") | |
773 | (match_operand:SI 3 "memory_operand" "")) | |
774 | (parallel | |
775 | [(set (match_operand:SI 1 "s_register_operand" "") | |
776 | (match_operand:SI 4 "memory_operand" "")) | |
777 | (set (match_operand:SI 2 "s_register_operand" "") | |
778 | (match_operand:SI 5 "memory_operand" ""))])] | |
779 | "" | |
780 | [(const_int 0)] | |
781 | { | |
782 | if (gen_ldm_seq (operands, 3, false)) | |
783 | DONE; | |
784 | else | |
785 | FAIL; | |
786 | }) | |
787 | ||
788 | (define_peephole2 | |
789 | [(set (match_operand:SI 0 "s_register_operand" "") | |
790 | (match_operand:SI 6 "const_int_operand" "")) | |
791 | (set (match_operand:SI 3 "memory_operand" "") | |
792 | (match_dup 0)) | |
793 | (set (match_operand:SI 1 "s_register_operand" "") | |
794 | (match_operand:SI 7 "const_int_operand" "")) | |
795 | (set (match_operand:SI 4 "memory_operand" "") | |
796 | (match_dup 1)) | |
797 | (set (match_operand:SI 2 "s_register_operand" "") | |
798 | (match_operand:SI 8 "const_int_operand" "")) | |
799 | (set (match_operand:SI 5 "memory_operand" "") | |
800 | (match_dup 2))] | |
801 | "" | |
802 | [(const_int 0)] | |
803 | { | |
804 | if (gen_const_stm_seq (operands, 3)) | |
805 | DONE; | |
806 | else | |
807 | FAIL; | |
808 | }) | |
809 | ||
810 | (define_peephole2 | |
811 | [(set (match_operand:SI 0 "s_register_operand" "") | |
812 | (match_operand:SI 6 "const_int_operand" "")) | |
813 | (set (match_operand:SI 1 "s_register_operand" "") | |
814 | (match_operand:SI 7 "const_int_operand" "")) | |
815 | (set (match_operand:SI 2 "s_register_operand" "") | |
816 | (match_operand:SI 8 "const_int_operand" "")) | |
817 | (set (match_operand:SI 3 "memory_operand" "") | |
818 | (match_dup 0)) | |
819 | (set (match_operand:SI 4 "memory_operand" "") | |
820 | (match_dup 1)) | |
821 | (set (match_operand:SI 5 "memory_operand" "") | |
822 | (match_dup 2))] | |
823 | "" | |
824 | [(const_int 0)] | |
825 | { | |
826 | if (gen_const_stm_seq (operands, 3)) | |
827 | DONE; | |
828 | else | |
829 | FAIL; | |
830 | }) | |
831 | ||
832 | (define_peephole2 | |
833 | [(set (match_operand:SI 3 "memory_operand" "") | |
834 | (match_operand:SI 0 "s_register_operand" "")) | |
835 | (set (match_operand:SI 4 "memory_operand" "") | |
836 | (match_operand:SI 1 "s_register_operand" "")) | |
837 | (set (match_operand:SI 5 "memory_operand" "") | |
838 | (match_operand:SI 2 "s_register_operand" ""))] | |
839 | "" | |
840 | [(const_int 0)] | |
841 | { | |
842 | if (gen_stm_seq (operands, 3)) | |
843 | DONE; | |
844 | else | |
845 | FAIL; | |
846 | }) | |
847 | ||
bae4ce0f | 848 | (define_insn "*ldm2_" |
37119410 | 849 | [(match_parallel 0 "load_multiple_operation" |
03158648 | 850 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 851 | (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) |
03158648 | 852 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
853 | (mem:SI (plus:SI (match_dup 3) |
854 | (const_int 4))))])] | |
900c07da | 855 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 856 | "ldm%?\t%3, {%1, %2}" |
89b2133e | 857 | [(set_attr "type" "load_8") |
113c53c3 | 858 | (set_attr "predicable" "yes")]) |
37119410 BS |
859 | |
860 | (define_insn "*thumb_ldm2_ia" | |
861 | [(match_parallel 0 "load_multiple_operation" | |
9f178d6a | 862 | [(set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 863 | (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) |
9f178d6a | 864 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
865 | (mem:SI (plus:SI (match_dup 3) |
866 | (const_int 4))))])] | |
867 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" | |
bae4ce0f | 868 | "ldmia\t%3, {%1, %2}" |
89b2133e | 869 | [(set_attr "type" "load_8")]) |
37119410 BS |
870 | |
871 | (define_insn "*ldm2_ia_update" | |
872 | [(match_parallel 0 "load_multiple_operation" | |
873 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
874 | (plus:SI (match_dup 3) (const_int 8))) | |
03158648 | 875 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 | 876 | (mem:SI (match_dup 3))) |
03158648 | 877 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
878 | (mem:SI (plus:SI (match_dup 3) |
879 | (const_int 4))))])] | |
880 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 881 | "ldmia%?\t%3!, {%1, %2}" |
89b2133e | 882 | [(set_attr "type" "load_8") |
113c53c3 | 883 | (set_attr "predicable" "yes")]) |
37119410 BS |
884 | |
885 | (define_insn "*thumb_ldm2_ia_update" | |
886 | [(match_parallel 0 "load_multiple_operation" | |
887 | [(set (match_operand:SI 3 "s_register_operand" "+&l") | |
888 | (plus:SI (match_dup 3) (const_int 8))) | |
9f178d6a | 889 | (set (match_operand:SI 1 "low_register_operand" "") |
37119410 | 890 | (mem:SI (match_dup 3))) |
9f178d6a | 891 | (set (match_operand:SI 2 "low_register_operand" "") |
37119410 BS |
892 | (mem:SI (plus:SI (match_dup 3) |
893 | (const_int 4))))])] | |
894 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 895 | "ldmia\t%3!, {%1, %2}" |
89b2133e | 896 | [(set_attr "type" "load_8")]) |
37119410 | 897 | |
bae4ce0f | 898 | (define_insn "*stm2_" |
37119410 BS |
899 | [(match_parallel 0 "store_multiple_operation" |
900 | [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) | |
03158648 | 901 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 902 | (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) |
03158648 | 903 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
900c07da | 904 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 905 | "stm%?\t%3, {%1, %2}" |
89b2133e | 906 | [(set_attr "type" "store_8") |
113c53c3 | 907 | (set_attr "predicable" "yes")]) |
37119410 BS |
908 | |
909 | (define_insn "*stm2_ia_update" | |
910 | [(match_parallel 0 "store_multiple_operation" | |
911 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
912 | (plus:SI (match_dup 3) (const_int 8))) | |
913 | (set (mem:SI (match_dup 3)) | |
03158648 | 914 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 915 | (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) |
03158648 | 916 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
37119410 | 917 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 918 | "stmia%?\t%3!, {%1, %2}" |
89b2133e | 919 | [(set_attr "type" "store_8") |
113c53c3 | 920 | (set_attr "predicable" "yes")]) |
37119410 BS |
921 | |
922 | (define_insn "*thumb_stm2_ia_update" | |
923 | [(match_parallel 0 "store_multiple_operation" | |
924 | [(set (match_operand:SI 3 "s_register_operand" "+&l") | |
925 | (plus:SI (match_dup 3) (const_int 8))) | |
926 | (set (mem:SI (match_dup 3)) | |
9f178d6a | 927 | (match_operand:SI 1 "low_register_operand" "")) |
37119410 | 928 | (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) |
9f178d6a | 929 | (match_operand:SI 2 "low_register_operand" ""))])] |
37119410 | 930 | "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 931 | "stmia\t%3!, {%1, %2}" |
89b2133e | 932 | [(set_attr "type" "store_8")]) |
37119410 BS |
933 | |
934 | (define_insn "*ldm2_ib" | |
935 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 936 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
937 | (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") |
938 | (const_int 4)))) | |
03158648 | 939 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
940 | (mem:SI (plus:SI (match_dup 3) |
941 | (const_int 8))))])] | |
900c07da | 942 | "TARGET_ARM && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 943 | "ldmib%?\t%3, {%1, %2}" |
89b2133e | 944 | [(set_attr "type" "load_8") |
37119410 BS |
945 | (set_attr "predicable" "yes")]) |
946 | ||
947 | (define_insn "*ldm2_ib_update" | |
948 | [(match_parallel 0 "load_multiple_operation" | |
949 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
950 | (plus:SI (match_dup 3) (const_int 8))) | |
03158648 | 951 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
952 | (mem:SI (plus:SI (match_dup 3) |
953 | (const_int 4)))) | |
03158648 | 954 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
955 | (mem:SI (plus:SI (match_dup 3) |
956 | (const_int 8))))])] | |
957 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 958 | "ldmib%?\t%3!, {%1, %2}" |
89b2133e | 959 | [(set_attr "type" "load_8") |
37119410 BS |
960 | (set_attr "predicable" "yes")]) |
961 | ||
962 | (define_insn "*stm2_ib" | |
963 | [(match_parallel 0 "store_multiple_operation" | |
964 | [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) | |
03158648 | 965 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 966 | (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) |
03158648 | 967 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
900c07da | 968 | "TARGET_ARM && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 969 | "stmib%?\t%3, {%1, %2}" |
89b2133e | 970 | [(set_attr "type" "store_8") |
37119410 BS |
971 | (set_attr "predicable" "yes")]) |
972 | ||
973 | (define_insn "*stm2_ib_update" | |
974 | [(match_parallel 0 "store_multiple_operation" | |
975 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
976 | (plus:SI (match_dup 3) (const_int 8))) | |
977 | (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) | |
03158648 | 978 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 979 | (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) |
03158648 | 980 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
37119410 | 981 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 982 | "stmib%?\t%3!, {%1, %2}" |
89b2133e | 983 | [(set_attr "type" "store_8") |
37119410 BS |
984 | (set_attr "predicable" "yes")]) |
985 | ||
986 | (define_insn "*ldm2_da" | |
987 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 988 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
989 | (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") |
990 | (const_int -4)))) | |
03158648 | 991 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 | 992 | (mem:SI (match_dup 3)))])] |
900c07da | 993 | "TARGET_ARM && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 994 | "ldmda%?\t%3, {%1, %2}" |
89b2133e | 995 | [(set_attr "type" "load_8") |
37119410 BS |
996 | (set_attr "predicable" "yes")]) |
997 | ||
998 | (define_insn "*ldm2_da_update" | |
999 | [(match_parallel 0 "load_multiple_operation" | |
1000 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
1001 | (plus:SI (match_dup 3) (const_int -8))) | |
03158648 | 1002 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
1003 | (mem:SI (plus:SI (match_dup 3) |
1004 | (const_int -4)))) | |
03158648 | 1005 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
1006 | (mem:SI (match_dup 3)))])] |
1007 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 1008 | "ldmda%?\t%3!, {%1, %2}" |
89b2133e | 1009 | [(set_attr "type" "load_8") |
37119410 BS |
1010 | (set_attr "predicable" "yes")]) |
1011 | ||
1012 | (define_insn "*stm2_da" | |
1013 | [(match_parallel 0 "store_multiple_operation" | |
1014 | [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) | |
03158648 | 1015 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 1016 | (set (mem:SI (match_dup 3)) |
03158648 | 1017 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
900c07da | 1018 | "TARGET_ARM && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 1019 | "stmda%?\t%3, {%1, %2}" |
89b2133e | 1020 | [(set_attr "type" "store_8") |
37119410 BS |
1021 | (set_attr "predicable" "yes")]) |
1022 | ||
1023 | (define_insn "*stm2_da_update" | |
1024 | [(match_parallel 0 "store_multiple_operation" | |
1025 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
1026 | (plus:SI (match_dup 3) (const_int -8))) | |
1027 | (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) | |
03158648 | 1028 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 1029 | (set (mem:SI (match_dup 3)) |
03158648 | 1030 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
37119410 | 1031 | "TARGET_ARM && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 1032 | "stmda%?\t%3!, {%1, %2}" |
89b2133e | 1033 | [(set_attr "type" "store_8") |
37119410 BS |
1034 | (set_attr "predicable" "yes")]) |
1035 | ||
1036 | (define_insn "*ldm2_db" | |
1037 | [(match_parallel 0 "load_multiple_operation" | |
03158648 | 1038 | [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
1039 | (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") |
1040 | (const_int -8)))) | |
03158648 | 1041 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
1042 | (mem:SI (plus:SI (match_dup 3) |
1043 | (const_int -4))))])] | |
900c07da | 1044 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 1045 | "ldmdb%?\t%3, {%1, %2}" |
89b2133e | 1046 | [(set_attr "type" "load_8") |
113c53c3 | 1047 | (set_attr "predicable" "yes")]) |
37119410 BS |
1048 | |
1049 | (define_insn "*ldm2_db_update" | |
1050 | [(match_parallel 0 "load_multiple_operation" | |
1051 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
1052 | (plus:SI (match_dup 3) (const_int -8))) | |
03158648 | 1053 | (set (match_operand:SI 1 "arm_hard_general_register_operand" "") |
37119410 BS |
1054 | (mem:SI (plus:SI (match_dup 3) |
1055 | (const_int -8)))) | |
03158648 | 1056 | (set (match_operand:SI 2 "arm_hard_general_register_operand" "") |
37119410 BS |
1057 | (mem:SI (plus:SI (match_dup 3) |
1058 | (const_int -4))))])] | |
1059 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | |
bae4ce0f | 1060 | "ldmdb%?\t%3!, {%1, %2}" |
89b2133e | 1061 | [(set_attr "type" "load_8") |
113c53c3 | 1062 | (set_attr "predicable" "yes")]) |
37119410 BS |
1063 | |
1064 | (define_insn "*stm2_db" | |
1065 | [(match_parallel 0 "store_multiple_operation" | |
1066 | [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) | |
03158648 | 1067 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 1068 | (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) |
03158648 | 1069 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
900c07da | 1070 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" |
bae4ce0f | 1071 | "stmdb%?\t%3, {%1, %2}" |
89b2133e | 1072 | [(set_attr "type" "store_8") |
113c53c3 | 1073 | (set_attr "predicable" "yes")]) |
37119410 BS |
1074 | |
1075 | (define_insn "*stm2_db_update" | |
1076 | [(match_parallel 0 "store_multiple_operation" | |
1077 | [(set (match_operand:SI 3 "s_register_operand" "+&rk") | |
1078 | (plus:SI (match_dup 3) (const_int -8))) | |
1079 | (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) | |
03158648 | 1080 | (match_operand:SI 1 "arm_hard_general_register_operand" "")) |
37119410 | 1081 | (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) |
03158648 | 1082 | (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] |
37119410 | 1083 | "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" |
bae4ce0f | 1084 | "stmdb%?\t%3!, {%1, %2}" |
89b2133e | 1085 | [(set_attr "type" "store_8") |
113c53c3 | 1086 | (set_attr "predicable" "yes")]) |
37119410 BS |
1087 | |
1088 | (define_peephole2 | |
1089 | [(set (match_operand:SI 0 "s_register_operand" "") | |
1090 | (match_operand:SI 2 "memory_operand" "")) | |
1091 | (set (match_operand:SI 1 "s_register_operand" "") | |
1092 | (match_operand:SI 3 "memory_operand" ""))] | |
1093 | "" | |
1094 | [(const_int 0)] | |
1095 | { | |
1096 | if (gen_ldm_seq (operands, 2, false)) | |
1097 | DONE; | |
1098 | else | |
1099 | FAIL; | |
1100 | }) | |
1101 | ||
1102 | (define_peephole2 | |
1103 | [(set (match_operand:SI 0 "s_register_operand" "") | |
1104 | (match_operand:SI 4 "const_int_operand" "")) | |
1105 | (set (match_operand:SI 2 "memory_operand" "") | |
1106 | (match_dup 0)) | |
1107 | (set (match_operand:SI 1 "s_register_operand" "") | |
1108 | (match_operand:SI 5 "const_int_operand" "")) | |
1109 | (set (match_operand:SI 3 "memory_operand" "") | |
1110 | (match_dup 1))] | |
1111 | "" | |
1112 | [(const_int 0)] | |
1113 | { | |
1114 | if (gen_const_stm_seq (operands, 2)) | |
1115 | DONE; | |
1116 | else | |
1117 | FAIL; | |
1118 | }) | |
1119 | ||
1120 | (define_peephole2 | |
1121 | [(set (match_operand:SI 0 "s_register_operand" "") | |
1122 | (match_operand:SI 4 "const_int_operand" "")) | |
1123 | (set (match_operand:SI 1 "s_register_operand" "") | |
1124 | (match_operand:SI 5 "const_int_operand" "")) | |
1125 | (set (match_operand:SI 2 "memory_operand" "") | |
1126 | (match_dup 0)) | |
1127 | (set (match_operand:SI 3 "memory_operand" "") | |
1128 | (match_dup 1))] | |
1129 | "" | |
1130 | [(const_int 0)] | |
1131 | { | |
1132 | if (gen_const_stm_seq (operands, 2)) | |
1133 | DONE; | |
1134 | else | |
1135 | FAIL; | |
1136 | }) | |
1137 | ||
1138 | (define_peephole2 | |
1139 | [(set (match_operand:SI 2 "memory_operand" "") | |
1140 | (match_operand:SI 0 "s_register_operand" "")) | |
1141 | (set (match_operand:SI 3 "memory_operand" "") | |
1142 | (match_operand:SI 1 "s_register_operand" ""))] | |
1143 | "" | |
1144 | [(const_int 0)] | |
1145 | { | |
1146 | if (gen_stm_seq (operands, 2)) | |
1147 | DONE; | |
1148 | else | |
1149 | FAIL; | |
1150 | }) | |
1151 | ||
1152 | (define_peephole2 | |
1153 | [(set (match_operand:SI 0 "s_register_operand" "") | |
1154 | (match_operand:SI 2 "memory_operand" "")) | |
1155 | (set (match_operand:SI 1 "s_register_operand" "") | |
1156 | (match_operand:SI 3 "memory_operand" "")) | |
1157 | (parallel | |
1158 | [(set (match_operand:SI 4 "s_register_operand" "") | |
1159 | (match_operator:SI 5 "commutative_binary_operator" | |
1160 | [(match_operand:SI 6 "s_register_operand" "") | |
1161 | (match_operand:SI 7 "s_register_operand" "")])) | |
1162 | (clobber (reg:CC CC_REGNUM))])] | |
2d68f67f GY |
1163 | "((((REGNO (operands[6]) == REGNO (operands[0])) |
1164 | && (REGNO (operands[7]) == REGNO (operands[1]))) | |
1165 | || ((REGNO (operands[7]) == REGNO (operands[0])) | |
1166 | && (REGNO (operands[6]) == REGNO (operands[1])))) | |
1167 | && (peep2_regno_dead_p (3, REGNO (operands[0])) | |
1168 | || (REGNO (operands[0]) == REGNO (operands[4]))) | |
1169 | && (peep2_regno_dead_p (3, REGNO (operands[1])) | |
1170 | || (REGNO (operands[1]) == REGNO (operands[4]))))" | |
37119410 BS |
1171 | [(parallel |
1172 | [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) | |
1173 | (clobber (reg:CC CC_REGNUM))])] | |
1174 | { | |
1175 | if (!gen_ldm_seq (operands, 2, true)) | |
1176 | FAIL; | |
1177 | }) | |
1178 | ||
1179 | (define_peephole2 | |
1180 | [(set (match_operand:SI 0 "s_register_operand" "") | |
1181 | (match_operand:SI 2 "memory_operand" "")) | |
1182 | (set (match_operand:SI 1 "s_register_operand" "") | |
1183 | (match_operand:SI 3 "memory_operand" "")) | |
1184 | (set (match_operand:SI 4 "s_register_operand" "") | |
1185 | (match_operator:SI 5 "commutative_binary_operator" | |
1186 | [(match_operand:SI 6 "s_register_operand" "") | |
1187 | (match_operand:SI 7 "s_register_operand" "")]))] | |
2d68f67f GY |
1188 | "((((REGNO (operands[6]) == REGNO (operands[0])) |
1189 | && (REGNO (operands[7]) == REGNO (operands[1]))) | |
1190 | || ((REGNO (operands[7]) == REGNO (operands[0])) | |
1191 | && (REGNO (operands[6]) == REGNO (operands[1])))) | |
1192 | && (peep2_regno_dead_p (3, REGNO (operands[0])) | |
1193 | || (REGNO (operands[0]) == REGNO (operands[4]))) | |
1194 | && (peep2_regno_dead_p (3, REGNO (operands[1])) | |
1195 | || (REGNO (operands[1]) == REGNO (operands[4]))))" | |
37119410 BS |
1196 | [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] |
1197 | { | |
1198 | if (!gen_ldm_seq (operands, 2, true)) | |
1199 | FAIL; | |
1200 | }) | |
1201 |