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1 | ; Options for the Blackfin port of the compiler |
2 | ; | |
a5544970 | 3 | ; Copyright (C) 2005-2019 Free Software Foundation, Inc. |
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4 | ; |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 9 | ; Software Foundation; either version 3, or (at your option) any later |
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10 | ; version. |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ; License for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
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18 | ; along with GCC; see the file COPYING3. If not see |
19 | ; <http://www.gnu.org/licenses/>. | |
0d4a78eb | 20 | |
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21 | HeaderInclude |
22 | config/bfin/bfin-opts.h | |
23 | ||
24 | ; Value of -mcpu=. | |
25 | Variable | |
26 | bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN | |
27 | ||
28 | ; -msi-revision support. There are three special values: | |
29 | ; -1 -msi-revision=none. | |
30 | ; 0xffff -msi-revision=any. | |
31 | Variable | |
32 | int bfin_si_revision | |
33 | ||
34 | ; The workarounds enabled. | |
35 | Variable | |
36 | unsigned int bfin_workarounds = 0 | |
37 | ||
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38 | msim |
39 | Target RejectNegative | |
a7b2e184 | 40 | Use simulator runtime. |
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41 | |
42 | mcpu= | |
43 | Target RejectNegative Joined | |
a7b2e184 | 44 | Specify the name of the target CPU. |
9d3f9aa3 | 45 | |
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46 | momit-leaf-frame-pointer |
47 | Target Report Mask(OMIT_LEAF_FRAME_POINTER) | |
a7b2e184 | 48 | Omit frame pointer for leaf functions. |
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49 | |
50 | mlow64k | |
51 | Target Report Mask(LOW_64K) | |
a7b2e184 | 52 | Program is entirely located in low 64k of memory. |
0d4a78eb | 53 | |
3fb192d2 | 54 | mcsync-anomaly |
ea2382be | 55 | Target Report Var(bfin_csync_anomaly) Init(-1) |
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56 | Work around a hardware anomaly by adding a number of NOPs before a |
57 | CSYNC or SSYNC instruction. | |
58 | ||
59 | mspecld-anomaly | |
ea2382be | 60 | Target Report Var(bfin_specld_anomaly) Init(-1) |
3fb192d2 | 61 | Avoid speculative loads to work around a hardware anomaly. |
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62 | |
63 | mid-shared-library | |
64 | Target Report Mask(ID_SHARED_LIBRARY) | |
a7b2e184 | 65 | Enabled ID based shared library. |
f02a5d0e | 66 | |
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67 | mleaf-id-shared-library |
68 | Target Report Mask(LEAF_ID_SHARED_LIBRARY) | |
69 | Generate code that won't be linked against any other ID shared libraries, | |
70 | but may be used as a shared library. | |
71 | ||
f02a5d0e | 72 | mshared-library-id= |
55bea00a | 73 | Target RejectNegative Joined UInteger Var(bfin_library_id) |
a7b2e184 | 74 | ID of shared library to build. |
fd078f52 | 75 | |
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76 | msep-data |
77 | Target Report Mask(SEP_DATA) | |
a7b2e184 | 78 | Enable separate data segment. |
93147119 | 79 | |
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80 | mlong-calls |
81 | Target Report Mask(LONG_CALLS) | |
a7b2e184 | 82 | Avoid generating pc-relative calls; use indirection. |
6614f9f5 | 83 | |
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84 | mfast-fp |
85 | Target Report Mask(FAST_FP) | |
a7b2e184 | 86 | Link with the fast floating-point library. |
2c117a21 | 87 | |
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88 | mfdpic |
89 | Target Report Mask(FDPIC) | |
a7b2e184 | 90 | Enable Function Descriptor PIC mode. |
d6eb07dc | 91 | |
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92 | minline-plt |
93 | Target Report Mask(INLINE_PLT) | |
a7b2e184 | 94 | Enable inlining of PLT in function calls. |
e874e49f | 95 | |
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96 | mstack-check-l1 |
97 | Target Report Mask(STACK_CHECK_L1) | |
a7b2e184 | 98 | Do stack checking using bounds in L1 scratch memory. |
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99 | |
100 | mmulticore | |
101 | Target Report Mask(MULTICORE) | |
a7b2e184 | 102 | Enable multicore support. |
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103 | |
104 | mcorea | |
105 | Target Report Mask(COREA) | |
a7b2e184 | 106 | Build for Core A. |
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107 | |
108 | mcoreb | |
109 | Target Report Mask(COREB) | |
a7b2e184 | 110 | Build for Core B. |
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111 | |
112 | msdram | |
113 | Target Report Mask(SDRAM) | |
a7b2e184 | 114 | Build for SDRAM. |
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115 | |
116 | micplb | |
117 | Target Report Mask(ICPLB) | |
118 | Assume ICPLBs are enabled at runtime. |