]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/csky/csky.opt
Update copyright years.
[thirdparty/gcc.git] / gcc / config / csky / csky.opt
CommitLineData
cc7232b9 1;; Command-line options for the C-SKY back end.
a945c346 2;; Copyright (C) 2018-2024 Free Software Foundation, Inc.
cc7232b9
J
3;; Contributed by C-SKY Microsystems and Mentor Graphics.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it under
8;; the terms of the GNU General Public License as published by the Free
9;; Software Foundation; either version 3, or (at your option) any later
10;; version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15;; for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21
22HeaderInclude
23config/csky/csky_opts.h
24
25;; Architecture/CPU options.
26;; Normal CPU and arch enums are loaded from csky_tables.opt.
27
28; For backward compatibility only.
29march=ck803s
eece52b5 30Target Var(flag_arch_ck803s) Undocumented
cc7232b9
J
31
32march=
33Target RejectNegative ToLower Joined Enum(csky_arch) Var(csky_arch_option) Save
34Specify the target architecture.
35
36mcpu=
37Target RejectNegative ToLower Joined Enum(csky_processor_type) Var(csky_cpu_option) Init(TARGET_CPU_csky_none) Save
38Specify the target processor.
39
40;; Endianness options.
41
42mbig-endian
eece52b5 43Target RejectNegative Mask(BIG_ENDIAN)
cc7232b9
J
44Generate big-endian code.
45
46EB
eece52b5 47Target RejectNegative Alias(mbig-endian) Undocumented
cc7232b9
J
48
49mlittle-endian
eece52b5 50Target RejectNegative InverseMask(BIG_ENDIAN)
cc7232b9
J
51Generate little-endian code.
52
53EL
eece52b5 54Target RejectNegative Alias(mlittle-endian) Undocumented
cc7232b9
J
55
56;; Floating point options. These affect code generation but not
57;; assembly.
58
59mhard-float
197f1e8c 60Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
cc7232b9
J
61
62msoft-float
197f1e8c
J
63Target RejectNegative Alias(mfloat-abi=, soft) Undocumented
64
65mfloat-abi=v2
66Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
67
68mfloat-abi=v1
69Target RejectNegative Alias(mfloat-abi=, softfp) Undocumented
70
71mfloat-abi=
72Target RejectNegative Joined Enum(float_abi_type) Var(csky_float_abi) Init(CSKY_FLOAT_ABI_SOFT)
73Specify if floating point hardware should be used.
74
75Enum
76Name(float_abi_type) Type(enum float_abi_type)
77Known floating-point ABIs (for use with the -mfloat-abi= option):
78
79EnumValue
80Enum(float_abi_type) String(soft) Value(CSKY_FLOAT_ABI_SOFT)
81
82EnumValue
83Enum(float_abi_type) String(softfp) Value(CSKY_FLOAT_ABI_SOFTFP)
84
85EnumValue
86Enum(float_abi_type) String(hard) Value(CSKY_FLOAT_ABI_HARD)
cc7232b9
J
87
88mfpu=
89Target RejectNegative Joined Enum(csky_fpu) Var(csky_fpu_index) Init(TARGET_FPU_auto) Save
90Specify the target floating-point hardware/format.
91
92mdouble-float
eece52b5 93Target Var(TARGET_DOUBLE_FLOAT) Init(-1)
cc7232b9
J
94Generate C-SKY FPU double float instructions (default for hard float).
95
96mfdivdu
eece52b5 97Target Var(TARGET_FDIVDU) Init(-1)
cc7232b9
J
98Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
99
100;; Instruction set extensions. Most of these don't affect code
101;; generation, and are passed through to the assembler.
102;; There are builtin preprocessor defines for each of these.
103
104melrw
eece52b5 105Target Var(TARGET_ELRW) Init(-1)
cc7232b9
J
106Enable the extended LRW instruction (default for CK801).
107
108mistack
eece52b5 109Target Mask(ISTACK)
cc7232b9
J
110Enable interrupt stack instructions.
111
112mmp
eece52b5 113Target RejectNegative Mask(MP)
cc7232b9
J
114Enable multiprocessor instructions.
115
116mcp
eece52b5 117Target RejectNegative Mask(CP)
cc7232b9
J
118Enable coprocessor instructions.
119
120mcache
eece52b5 121Target RejectNegative Mask(CACHE)
cc7232b9
J
122Enable cache prefetch instructions.
123
124msecurity
eece52b5 125Target RejectNegative Mask(SECURITY)
cc7232b9
J
126Enable C-SKY SECURE instructions.
127
128mmac
eece52b5 129Target RejectNegative Alias(msecurity) Undocumented
cc7232b9
J
130
131mtrust
eece52b5 132Target RejectNegative Mask(TRUST)
cc7232b9
J
133Enable C-SKY TRUST instructions.
134
135mdsp
eece52b5 136Target RejectNegative Var(TARGET_DSP)
cc7232b9
J
137Enable C-SKY DSP instructions.
138
139medsp
eece52b5 140Target RejectNegative Mask(EDSP)
cc7232b9
J
141Enable C-SKY Enhanced DSP instructions.
142
143mvdsp
eece52b5 144Target RejectNegative Mask(VDSP)
cc7232b9
J
145Enable C-SKY Vector DSP instructions.
146
147;; Code generation options not passed to the assembler.
148
149mdiv
eece52b5 150Target Var(TARGET_DIV) Init(-1)
cc7232b9
J
151Generate divide instructions.
152
153msmart
eece52b5 154Target Var(TARGET_MINI_REGISTERS) Init(-1)
cc7232b9
J
155Generate code for Smart Mode.
156
157mhigh-registers
eece52b5 158Target Var(TARGET_HIGH_REGISTERS) Init(-1)
cc7232b9
J
159Enable use of R16-R31 (default).
160
161manchor
eece52b5 162Target Var(TARGET_ANCHOR)
cc7232b9
J
163Generate code using global anchor symbol addresses.
164
165mpushpop
eece52b5 166Target Var(TARGET_PUSHPOP) Init(1)
cc7232b9
J
167Generate push/pop instructions (default).
168
169mmultiple-stld
eece52b5 170Target Var(TARGET_MULTIPLE_STLD) Init(-1)
cc7232b9
J
171Generate stm/ldm instructions (default).
172
173mstm
eece52b5 174Target Alias(mmultiple-stld) Undocumented
cc7232b9
J
175
176mconstpool
eece52b5 177Target Var(TARGET_CONSTANT_POOL) Init(-1)
cc7232b9
J
178Generate constant pools in the compiler instead of assembler.
179
180mstack-size
eece52b5 181Target Var(TARGET_STACK_SIZE) Init(0)
cc7232b9
J
182Emit .stack_size directives.
183
184mccrt
eece52b5 185Target Var(TARGET_LIBCCRT) Init(0)
cc7232b9
J
186Generate code for C-SKY compiler runtime instead of libgcc.
187
188mbranch-cost=
eece52b5 189Target Joined RejectNegative UInteger Var(csky_branch_cost) Init(1)
cc7232b9
J
190Set the branch costs to roughly the specified number of instructions.
191
192msched-prolog
eece52b5 193Target Var(flag_sched_prolog) Init(0)
cc7232b9 194Permit scheduling of function prologue and epilogue sequences.
6ee9c216
J
195
196msim
197Target
198Use the simulator runtime.