projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| a945c346 | 1 | /* Copyright (C) 2016-2024 Free Software Foundation, Inc. |
| 5326695a AS |
2 | |
| 3 | This file is free software; you can redistribute it and/or modify it under | |
| 4 | the terms of the GNU General Public License as published by the Free | |
| 5 | Software Foundation; either version 3 of the License, or (at your option) | |
| 6 | any later version. | |
| 7 | ||
| 8 | This file is distributed in the hope that it will be useful, but WITHOUT | |
| 9 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 11 | for more details. | |
| 12 | ||
| 13 | You should have received a copy of the GNU General Public License | |
| 14 | along with GCC; see the file COPYING3. If not see | |
| 15 | <http://www.gnu.org/licenses/>. */ | |
| 16 | ||
| 17 | #ifndef GCN_OPTS_H | |
| 18 | #define GCN_OPTS_H | |
| 19 | ||
| 20 | /* Which processor to generate code or schedule for. */ | |
| 21 | enum processor_type | |
| 22 | { | |
| f062c3f1 AS |
23 | PROCESSOR_FIJI, // gfx803 |
| 24 | PROCESSOR_VEGA10, // gfx900 | |
| 3535402e | 25 | PROCESSOR_VEGA20, // gfx906 |
| cde52d3a | 26 | PROCESSOR_GFX908, |
| c7ec7bd1 AS |
27 | PROCESSOR_GFX90a, |
| 28 | PROCESSOR_GFX1030 | |
| 5326695a AS |
29 | }; |
| 30 | ||
| e41b2433 PAA |
31 | #define TARGET_FIJI (gcn_arch == PROCESSOR_FIJI) |
| 32 | #define TARGET_VEGA10 (gcn_arch == PROCESSOR_VEGA10) | |
| 33 | #define TARGET_VEGA20 (gcn_arch == PROCESSOR_VEGA20) | |
| 34 | #define TARGET_GFX908 (gcn_arch == PROCESSOR_GFX908) | |
| 35 | #define TARGET_GFX90a (gcn_arch == PROCESSOR_GFX90a) | |
| c7ec7bd1 | 36 | #define TARGET_GFX1030 (gcn_arch == PROCESSOR_GFX1030) |
| e41b2433 | 37 | |
| 5326695a | 38 | /* Set in gcn_option_override. */ |
| cde52d3a AS |
39 | extern enum gcn_isa { |
| 40 | ISA_UNKNOWN, | |
| 41 | ISA_GCN3, | |
| 42 | ISA_GCN5, | |
| c7ec7bd1 | 43 | ISA_RDNA2, |
| cde52d3a AS |
44 | ISA_CDNA1, |
| 45 | ISA_CDNA2 | |
| 46 | } gcn_isa; | |
| 47 | ||
| 48 | #define TARGET_GCN3 (gcn_isa == ISA_GCN3) | |
| 49 | #define TARGET_GCN3_PLUS (gcn_isa >= ISA_GCN3) | |
| 50 | #define TARGET_GCN5 (gcn_isa == ISA_GCN5) | |
| 51 | #define TARGET_GCN5_PLUS (gcn_isa >= ISA_GCN5) | |
| 52 | #define TARGET_CDNA1 (gcn_isa == ISA_CDNA1) | |
| 53 | #define TARGET_CDNA1_PLUS (gcn_isa >= ISA_CDNA1) | |
| 54 | #define TARGET_CDNA2 (gcn_isa == ISA_CDNA2) | |
| 55 | #define TARGET_CDNA2_PLUS (gcn_isa >= ISA_CDNA2) | |
| c7ec7bd1 AS |
56 | #define TARGET_RDNA2 (gcn_isa == ISA_RDNA2) |
| 57 | ||
| cde52d3a AS |
58 | |
| 59 | #define TARGET_M0_LDS_LIMIT (TARGET_GCN3) | |
| 60 | #define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS) | |
| 5326695a | 61 | |
| 366e3d30 TB |
62 | #define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF) |
| 63 | ||
| 64 | enum hsaco_attr_type | |
| aad32a00 | 65 | { |
| 366e3d30 TB |
66 | HSACO_ATTR_OFF, |
| 67 | HSACO_ATTR_ON, | |
| 4c12bcbe AS |
68 | HSACO_ATTR_ANY, |
| 69 | HSACO_ATTR_DEFAULT | |
| aad32a00 AS |
70 | }; |
| 71 | ||
| 5326695a | 72 | #endif |