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07aae5c2 | 1 | /* Subroutines for insn-output.c for Hitachi H8/300. |
c4777027 JL |
2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 |
3 | Free Software Foundation, Inc. | |
48837e29 DE |
4 | Contributed by Steve Chamberlain (sac@cygnus.com), |
5 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 SC |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
07aae5c2 | 23 | |
07aae5c2 | 24 | #include "config.h" |
c5c76735 | 25 | #include "system.h" |
07aae5c2 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
07aae5c2 SC |
28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
bf6bb899 | 39 | #include "function.h" |
441d04c6 | 40 | #include "toplev.h" |
8b97c5f8 | 41 | #include "c-pragma.h" |
441d04c6 | 42 | #include "tm_p.h" |
07aae5c2 SC |
43 | |
44 | /* Forward declarations. */ | |
f6da8bc3 KG |
45 | static int h8300_interrupt_function_p PARAMS ((tree)); |
46 | static int h8300_monitor_function_p PARAMS ((tree)); | |
47 | static int h8300_os_task_function_p PARAMS ((tree)); | |
48 | static void dosize PARAMS ((FILE *, const char *, unsigned int)); | |
49 | static const char *cond_string PARAMS ((enum rtx_code)); | |
f5b65a56 | 50 | |
48837e29 DE |
51 | /* CPU_TYPE, says what cpu we're compiling for. */ |
52 | int cpu_type; | |
53 | ||
f5b65a56 JL |
54 | /* True if the current function is an interrupt handler |
55 | (either via #pragma or an attribute specification). */ | |
56 | int interrupt_handler; | |
57 | ||
808fbfac | 58 | /* True if the current function is an OS Task |
fabe72bb JL |
59 | (via an attribute specification). */ |
60 | int os_task; | |
61 | ||
62 | /* True if the current function is a monitor | |
63 | (via an attribute specification). */ | |
64 | int monitor; | |
07aae5c2 SC |
65 | |
66 | /* True if a #pragma saveall has been seen for the current function. */ | |
67 | int pragma_saveall; | |
68 | ||
441d04c6 | 69 | static const char *const names_big[] = |
07e4d94e | 70 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; |
48837e29 | 71 | |
441d04c6 | 72 | static const char *const names_extended[] = |
07e4d94e | 73 | { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; |
48837e29 | 74 | |
441d04c6 | 75 | static const char *const names_upper_extended[] = |
07e4d94e | 76 | { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; |
48837e29 DE |
77 | |
78 | /* Points to one of the above. */ | |
79 | /* ??? The above could be put in an array indexed by CPU_TYPE. */ | |
441d04c6 | 80 | const char * const *h8_reg_names; |
48837e29 DE |
81 | |
82 | /* Various operations needed by the following, indexed by CPU_TYPE. */ | |
48837e29 | 83 | |
07e4d94e KH |
84 | static const char *const h8_push_ops[2] = { "push", "push.l" }; |
85 | static const char *const h8_pop_ops[2] = { "pop", "pop.l" }; | |
86 | static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; | |
48837e29 | 87 | |
441d04c6 | 88 | const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
48837e29 DE |
89 | |
90 | /* Initialize various cpu specific globals at start up. */ | |
91 | ||
92 | void | |
93 | h8300_init_once () | |
94 | { | |
95 | if (TARGET_H8300) | |
96 | { | |
97 | cpu_type = (int) CPU_H8300; | |
98 | h8_reg_names = names_big; | |
99 | } | |
100 | else | |
101 | { | |
a1616dd9 | 102 | /* For this we treat the H8/300 and H8/S the same. */ |
48837e29 DE |
103 | cpu_type = (int) CPU_H8300H; |
104 | h8_reg_names = names_extended; | |
105 | } | |
106 | h8_push_op = h8_push_ops[cpu_type]; | |
107 | h8_pop_op = h8_pop_ops[cpu_type]; | |
108 | h8_mov_op = h8_mov_ops[cpu_type]; | |
17f0f8fa KH |
109 | |
110 | if (!TARGET_H8300S && TARGET_MAC) | |
111 | fatal ("-ms2600 is used without -ms."); | |
48837e29 | 112 | } |
07aae5c2 | 113 | |
441d04c6 | 114 | const char * |
07aae5c2 SC |
115 | byte_reg (x, b) |
116 | rtx x; | |
117 | int b; | |
118 | { | |
441d04c6 | 119 | static const char *const names_small[] = |
48837e29 | 120 | {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", |
bd93f126 | 121 | "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"}; |
07aae5c2 SC |
122 | |
123 | return names_small[REGNO (x) * 2 + b]; | |
124 | } | |
125 | ||
126 | /* REGNO must be saved/restored across calls if this macro is true. */ | |
48837e29 DE |
127 | |
128 | #define WORD_REG_USED(regno) \ | |
fc80ea73 | 129 | (regno < 7 \ |
07e4d94e | 130 | /* No need to save registers if this function will not return. */\ |
fc80ea73 JL |
131 | && ! TREE_THIS_VOLATILE (current_function_decl) \ |
132 | && (pragma_saveall \ | |
133 | /* Save any call saved register that was used. */ \ | |
134 | || (regs_ever_live[regno] && !call_used_regs[regno]) \ | |
135 | /* Save the frame pointer if it was used. */ \ | |
136 | || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\ | |
137 | /* Save any register used in an interrupt handler. */ \ | |
138 | || (interrupt_handler && regs_ever_live[regno]) \ | |
139 | /* Save call clobbered registers in non-leaf interrupt \ | |
140 | handlers. */ \ | |
141 | || (interrupt_handler \ | |
142 | && call_used_regs[regno] \ | |
143 | && !current_function_is_leaf))) | |
07aae5c2 SC |
144 | |
145 | /* Output assembly language to FILE for the operation OP with operand size | |
48837e29 | 146 | SIZE to adjust the stack pointer. */ |
48837e29 | 147 | |
07aae5c2 | 148 | static void |
f8f26adc | 149 | dosize (file, op, size) |
07aae5c2 | 150 | FILE *file; |
441d04c6 | 151 | const char *op; |
07aae5c2 | 152 | unsigned int size; |
07aae5c2 | 153 | { |
7b3d4613 KH |
154 | /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or |
155 | better to use adds/subs insns rather than add.l/sub.l with an | |
156 | immediate value. | |
157 | ||
158 | Also, on the H8/300, if we don't have a temporary to hold the | |
159 | size of the frame in the prologue, we simply emit a sequence of | |
160 | subs since this shouldn't happen often. */ | |
161 | if ((TARGET_H8300 && size <= 4) | |
162 | || ((TARGET_H8300H || TARGET_H8300S) && size <= 8) | |
163 | || (TARGET_H8300 && current_function_needs_context | |
164 | && strcmp (op, "sub"))) | |
f8f26adc | 165 | { |
64530b82 | 166 | unsigned HOST_WIDE_INT amount; |
f8f26adc | 167 | |
7b3d4613 KH |
168 | /* Try different amounts in descending order. */ |
169 | for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; | |
170 | amount > 0; | |
171 | amount /= 2) | |
82fa9209 | 172 | { |
1a63219b | 173 | for (; size >= amount; size -= amount) |
7b3d4613 | 174 | fprintf (file, "\t%ss\t#%d,sp\n", op, amount); |
82fa9209 | 175 | } |
7b3d4613 KH |
176 | } |
177 | else | |
178 | { | |
48837e29 | 179 | if (TARGET_H8300) |
7b3d4613 | 180 | fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op); |
48837e29 | 181 | else |
7b3d4613 | 182 | fprintf (file, "\t%s.l\t#%d,sp\n", op, size); |
07aae5c2 SC |
183 | } |
184 | } | |
185 | ||
186 | /* Output assembly language code for the function prologue. */ | |
48837e29 | 187 | static int push_order[FIRST_PSEUDO_REGISTER] = |
07e4d94e | 188 | { 0, 1, 2, 3, 4, 5, 6, -1, -1, -1 }; |
a1616dd9 | 189 | static int pop_order[FIRST_PSEUDO_REGISTER] = |
07e4d94e | 190 | { 6, 5, 4, 3, 2, 1, 0, -1, -1, -1 }; |
07aae5c2 SC |
191 | |
192 | /* This is what the stack looks like after the prolog of | |
193 | a function with a frame has been set up: | |
194 | ||
48837e29 DE |
195 | <args> |
196 | PC | |
197 | FP <- fp | |
198 | <locals> | |
199 | <saved registers> <- sp | |
07aae5c2 SC |
200 | |
201 | This is what the stack looks like after the prolog of | |
202 | a function which doesn't have a frame: | |
203 | ||
48837e29 DE |
204 | <args> |
205 | PC | |
206 | <locals> | |
207 | <saved registers> <- sp | |
07aae5c2 SC |
208 | */ |
209 | ||
210 | void | |
211 | function_prologue (file, size) | |
212 | FILE *file; | |
213 | int size; | |
214 | { | |
48837e29 | 215 | int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; |
07aae5c2 | 216 | int idx; |
cda4bd43 KH |
217 | int push_regs[FIRST_PSEUDO_REGISTER]; |
218 | int n_regs; | |
07aae5c2 | 219 | |
dd07092e JL |
220 | /* Note a function with the interrupt attribute and set interrupt_handler |
221 | accordingly. */ | |
f5b65a56 JL |
222 | if (h8300_interrupt_function_p (current_function_decl)) |
223 | interrupt_handler = 1; | |
224 | ||
fabe72bb JL |
225 | /* If the current function has the OS_Task attribute set, then |
226 | we have a naked prologue. */ | |
227 | if (h8300_os_task_function_p (current_function_decl)) | |
228 | { | |
229 | fprintf (file, ";OS_Task prologue\n"); | |
230 | os_task = 1; | |
231 | return; | |
232 | } | |
233 | ||
234 | if (h8300_monitor_function_p (current_function_decl)) | |
235 | { | |
236 | /* My understanding of monitor functions is they act just | |
237 | like interrupt functions, except the prologue must | |
238 | mask interrupts. */ | |
239 | fprintf (file, ";monitor prologue\n"); | |
240 | interrupt_handler = 1; | |
241 | monitor = 1; | |
ea3a7ffa JL |
242 | if (TARGET_H8300) |
243 | { | |
244 | fprintf (file, "\tsubs\t#2,sp\n"); | |
245 | fprintf (file, "\tpush\tr0\n"); | |
246 | fprintf (file, "\tstc\tccr,r0l\n"); | |
247 | fprintf (file, "\torc\t#128,ccr\n"); | |
248 | fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); | |
249 | } | |
a1616dd9 | 250 | else |
ea3a7ffa JL |
251 | { |
252 | fprintf (file, "\tpush\ter0\n"); | |
253 | fprintf (file, "\tstc\tccr,r0l\n"); | |
254 | fprintf (file, "\torc\t#128,ccr\n"); | |
255 | fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); | |
256 | } | |
fabe72bb JL |
257 | } |
258 | ||
48837e29 DE |
259 | if (frame_pointer_needed) |
260 | { | |
07e4d94e | 261 | /* Push fp. */ |
48837e29 DE |
262 | fprintf (file, "\t%s\t%s\n", h8_push_op, |
263 | h8_reg_names[FRAME_POINTER_REGNUM]); | |
264 | fprintf (file, "\t%s\t%s,%s\n", h8_mov_op, | |
265 | h8_reg_names[STACK_POINTER_REGNUM], | |
266 | h8_reg_names[FRAME_POINTER_REGNUM]); | |
a1616dd9 | 267 | } |
48837e29 | 268 | |
07e4d94e | 269 | /* Leave room for locals. */ |
a1616dd9 | 270 | dosize (file, "sub", fsize); |
07aae5c2 | 271 | |
cda4bd43 | 272 | /* Compute which registers to push. */ |
a1616dd9 | 273 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) |
07aae5c2 | 274 | { |
a1616dd9 | 275 | int regno = push_order[idx]; |
07aae5c2 | 276 | |
a1616dd9 JL |
277 | if (regno >= 0 |
278 | && WORD_REG_USED (regno) | |
279 | && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM)) | |
cda4bd43 KH |
280 | push_regs[idx] = regno; |
281 | else | |
282 | push_regs[idx] = -1; | |
283 | } | |
284 | ||
285 | /* Push the rest of the registers. */ | |
286 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs) | |
287 | { | |
288 | int regno = push_regs[idx]; | |
289 | ||
290 | n_regs = 1; | |
291 | if (regno >= 0) | |
a1616dd9 JL |
292 | { |
293 | if (TARGET_H8300S) | |
294 | { | |
cda4bd43 KH |
295 | /* See how many registers we can push at the same time. */ |
296 | if ((regno == 0 || regno == 4) | |
297 | && push_regs[idx + 1] >= 0 | |
298 | && push_regs[idx + 2] >= 0 | |
299 | && push_regs[idx + 3] >= 0) | |
300 | n_regs = 4; | |
301 | ||
302 | else if ((regno == 0 || regno == 4) | |
303 | && push_regs[idx + 1] >= 0 | |
304 | && push_regs[idx + 2] >= 0) | |
305 | n_regs = 3; | |
306 | ||
307 | else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6) | |
308 | && push_regs[idx + 1] >= 0) | |
309 | n_regs = 2; | |
a1616dd9 | 310 | } |
cda4bd43 KH |
311 | |
312 | if (n_regs == 1) | |
313 | fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]); | |
314 | else | |
315 | fprintf (file, "\tstm.l\t%s-%s,@-sp\n", | |
316 | h8_reg_names[regno], | |
317 | h8_reg_names[regno + (n_regs - 1)]); | |
07aae5c2 SC |
318 | } |
319 | } | |
320 | } | |
321 | ||
322 | /* Output assembly language code for the function epilogue. */ | |
323 | ||
324 | void | |
325 | function_epilogue (file, size) | |
326 | FILE *file; | |
327 | int size; | |
328 | { | |
48837e29 | 329 | int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; |
07aae5c2 SC |
330 | int idx; |
331 | rtx insn = get_last_insn (); | |
cda4bd43 KH |
332 | int pop_regs[FIRST_PSEUDO_REGISTER]; |
333 | int n_regs; | |
07aae5c2 | 334 | |
fabe72bb JL |
335 | if (os_task) |
336 | { | |
337 | /* OS_Task epilogues are nearly naked -- they just have an | |
338 | rts instruction. */ | |
339 | fprintf (file, ";OS_task epilogue\n"); | |
340 | fprintf (file, "\trts\n"); | |
341 | goto out; | |
342 | } | |
343 | ||
07e4d94e | 344 | /* Monitor epilogues are the same as interrupt function epilogues. |
fabe72bb JL |
345 | Just make a note that we're in an monitor epilogue. */ |
346 | if (monitor) | |
07e4d94e | 347 | fprintf (file, ";monitor epilogue\n"); |
fabe72bb | 348 | |
07aae5c2 SC |
349 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
350 | if (GET_CODE (insn) == NOTE) | |
351 | insn = prev_nonnote_insn (insn); | |
352 | if (insn && GET_CODE (insn) == BARRIER) | |
f40a8c03 | 353 | goto out; |
07aae5c2 | 354 | |
cda4bd43 | 355 | /* Compute which registers to pop. */ |
a1616dd9 | 356 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) |
07aae5c2 | 357 | { |
a1616dd9 JL |
358 | int regno = pop_order[idx]; |
359 | ||
360 | if (regno >= 0 | |
361 | && WORD_REG_USED (regno) | |
362 | && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM)) | |
cda4bd43 KH |
363 | pop_regs[idx] = regno; |
364 | else | |
365 | pop_regs[idx] = -1; | |
366 | } | |
367 | ||
368 | /* Pop the saved registers. */ | |
369 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs) | |
370 | { | |
371 | int regno = pop_regs[idx]; | |
372 | ||
373 | n_regs = 1; | |
374 | if (regno >= 0) | |
07aae5c2 | 375 | { |
a1616dd9 JL |
376 | if (TARGET_H8300S) |
377 | { | |
cda4bd43 KH |
378 | /* See how many registers we can pop at the same time. */ |
379 | if ((regno == 7 || regno == 3) | |
380 | && pop_regs[idx + 1] >= 0 | |
381 | && pop_regs[idx + 2] >= 0 | |
382 | && pop_regs[idx + 3] >= 0) | |
383 | n_regs = 4; | |
384 | ||
385 | else if ((regno == 6 || regno == 2) | |
386 | && pop_regs[idx + 1] >= 0 | |
387 | && pop_regs[idx + 2] >= 0) | |
388 | n_regs = 3; | |
389 | ||
390 | else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1) | |
391 | && pop_regs[idx + 1] >= 0) | |
392 | n_regs = 2; | |
a1616dd9 | 393 | } |
cda4bd43 KH |
394 | |
395 | if (n_regs == 1) | |
396 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]); | |
397 | else | |
398 | fprintf (file, "\tldm.l\t@sp+,%s-%s\n", | |
399 | h8_reg_names[regno - (n_regs - 1)], | |
400 | h8_reg_names[regno]); | |
07aae5c2 | 401 | } |
07aae5c2 | 402 | } |
48837e29 | 403 | |
07e4d94e | 404 | /* Deallocate locals. */ |
a1616dd9 JL |
405 | dosize (file, "add", fsize); |
406 | ||
07e4d94e | 407 | /* Pop frame pointer if we had one. */ |
a1616dd9 | 408 | if (frame_pointer_needed) |
07e4d94e KH |
409 | fprintf (file, "\t%s\t%s\n", |
410 | h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]); | |
a1616dd9 | 411 | |
ea3a7ffa JL |
412 | /* If this is a monitor function, there is one register still left on |
413 | the stack. */ | |
414 | if (monitor) | |
415 | fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]); | |
416 | ||
dd07092e JL |
417 | if (interrupt_handler) |
418 | fprintf (file, "\trte\n"); | |
07aae5c2 | 419 | else |
dd07092e | 420 | fprintf (file, "\trts\n"); |
07aae5c2 | 421 | |
07e4d94e | 422 | out: |
f5b65a56 | 423 | interrupt_handler = 0; |
fabe72bb JL |
424 | os_task = 0; |
425 | monitor = 0; | |
07aae5c2 | 426 | pragma_saveall = 0; |
48837e29 DE |
427 | } |
428 | ||
429 | /* Output assembly code for the start of the file. */ | |
430 | ||
441d04c6 | 431 | void |
48837e29 DE |
432 | asm_file_start (file) |
433 | FILE *file; | |
434 | { | |
435 | fprintf (file, ";\tGCC For the Hitachi H8/300\n"); | |
436 | fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n"); | |
437 | fprintf (file, ";\trelease F-1\n"); | |
438 | if (optimize) | |
439 | fprintf (file, "; -O%d\n", optimize); | |
440 | if (TARGET_H8300H) | |
441 | fprintf (file, "\n\t.h8300h\n"); | |
a1616dd9 JL |
442 | else if (TARGET_H8300S) |
443 | fprintf (file, "\n\t.h8300s\n"); | |
48837e29 DE |
444 | else |
445 | fprintf (file, "\n\n"); | |
446 | output_file_directive (file, main_input_filename); | |
447 | } | |
448 | ||
449 | /* Output assembly language code for the end of file. */ | |
450 | ||
451 | void | |
452 | asm_file_end (file) | |
453 | FILE *file; | |
454 | { | |
455 | fprintf (file, "\t.end\n"); | |
07aae5c2 SC |
456 | } |
457 | \f | |
48837e29 DE |
458 | /* Return true if VALUE is a valid constant for constraint 'P'. |
459 | IE: VALUE is a power of two <= 2**15. */ | |
07aae5c2 SC |
460 | |
461 | int | |
48837e29 | 462 | small_power_of_two (value) |
009ac3d3 | 463 | HOST_WIDE_INT value; |
07aae5c2 | 464 | { |
009ac3d3 RH |
465 | int power = exact_log2 (value); |
466 | return power >= 0 && power <= 15; | |
07aae5c2 SC |
467 | } |
468 | ||
48837e29 DE |
469 | /* Return true if VALUE is a valid constant for constraint 'O', which |
470 | means that the constant would be ok to use as a bit for a bclr | |
471 | instruction. */ | |
472 | ||
473 | int | |
474 | ok_for_bclr (value) | |
009ac3d3 | 475 | HOST_WIDE_INT value; |
48837e29 DE |
476 | { |
477 | return small_power_of_two ((~value) & 0xff); | |
478 | } | |
479 | ||
07aae5c2 SC |
480 | /* Return true is OP is a valid source operand for an integer move |
481 | instruction. */ | |
48837e29 | 482 | |
07aae5c2 SC |
483 | int |
484 | general_operand_src (op, mode) | |
485 | rtx op; | |
486 | enum machine_mode mode; | |
487 | { | |
48837e29 DE |
488 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) |
489 | return 1; | |
07aae5c2 SC |
490 | return general_operand (op, mode); |
491 | } | |
492 | ||
493 | /* Return true if OP is a valid destination operand for an integer move | |
494 | instruction. */ | |
48837e29 | 495 | |
07aae5c2 SC |
496 | int |
497 | general_operand_dst (op, mode) | |
498 | rtx op; | |
499 | enum machine_mode mode; | |
500 | { | |
48837e29 DE |
501 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC) |
502 | return 1; | |
07aae5c2 SC |
503 | return general_operand (op, mode); |
504 | } | |
48837e29 DE |
505 | |
506 | /* Return true if OP is a const valid for a bit clear instruction. */ | |
507 | ||
508 | int | |
509 | o_operand (operand, mode) | |
510 | rtx operand; | |
441d04c6 | 511 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
512 | { |
513 | return (GET_CODE (operand) == CONST_INT | |
514 | && CONST_OK_FOR_O (INTVAL (operand))); | |
515 | } | |
516 | ||
517 | /* Return true if OP is a const valid for a bit set or bit xor instruction. */ | |
518 | ||
519 | int | |
520 | p_operand (operand, mode) | |
521 | rtx operand; | |
441d04c6 | 522 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
523 | { |
524 | return (GET_CODE (operand) == CONST_INT | |
525 | && CONST_OK_FOR_P (INTVAL (operand))); | |
526 | } | |
527 | ||
528 | /* Return true if OP is a valid call operand. */ | |
529 | ||
530 | int | |
531 | call_insn_operand (op, mode) | |
532 | rtx op; | |
441d04c6 | 533 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
534 | { |
535 | if (GET_CODE (op) == MEM) | |
536 | { | |
537 | rtx inside = XEXP (op, 0); | |
538 | if (register_operand (inside, Pmode)) | |
539 | return 1; | |
540 | if (CONSTANT_ADDRESS_P (inside)) | |
541 | return 1; | |
542 | } | |
543 | return 0; | |
544 | } | |
545 | ||
22c9a795 | 546 | /* Return 1 if an addition/subtraction of a constant integer can be |
997e5af8 | 547 | transformed into two consecutive adds/subs that are faster than the |
22c9a795 | 548 | straightforward way. Otherwise, return 0. */ |
997e5af8 | 549 | |
3b7d443c | 550 | int |
009ac3d3 | 551 | two_insn_adds_subs_operand (op, mode) |
3b7d443c | 552 | rtx op; |
997e5af8 | 553 | enum machine_mode mode; |
3b7d443c JL |
554 | { |
555 | if (GET_CODE (op) == CONST_INT) | |
556 | { | |
009ac3d3 | 557 | HOST_WIDE_INT value = INTVAL (op); |
3b7d443c | 558 | |
997e5af8 KH |
559 | /* Force VALUE to be positive so that we do not have to consider |
560 | the negative case. */ | |
561 | if (value < 0) | |
562 | value = -value; | |
009ac3d3 RH |
563 | if (TARGET_H8300H || TARGET_H8300S) |
564 | { | |
997e5af8 KH |
565 | /* A constant addition/subtraction takes 2 states in QImode, |
566 | 4 states in HImode, and 6 states in SImode. Thus, the | |
567 | only case we can win is when SImode is used, in which | |
c59ff527 | 568 | case, two adds/subs are used, taking 4 states. */ |
997e5af8 KH |
569 | if (mode == SImode |
570 | && (value == 2 + 1 | |
571 | || value == 4 + 1 | |
572 | || value == 4 + 2 | |
573 | || value == 4 + 4)) | |
22c9a795 | 574 | return 1; |
009ac3d3 RH |
575 | } |
576 | else | |
577 | { | |
997e5af8 KH |
578 | /* A constant addition/subtraction takes 2 states in |
579 | QImode. It takes 6 states in HImode, requiring the | |
580 | constant to be loaded to a register first, and a lot more | |
581 | in SImode. Thus the only case we can win is when either | |
582 | HImode or SImode is used. */ | |
583 | if (mode != QImode | |
584 | && (value == 2 + 1 | |
585 | || value == 2 + 2)) | |
009ac3d3 RH |
586 | return 1; |
587 | } | |
588 | } | |
e6219736 | 589 | |
e6219736 JL |
590 | return 0; |
591 | } | |
592 | ||
009ac3d3 RH |
593 | /* Split an add of a small constant into two adds/subs insns. */ |
594 | ||
595 | void | |
596 | split_adds_subs (mode, operands) | |
597 | enum machine_mode mode; | |
3b7d443c JL |
598 | rtx *operands; |
599 | { | |
009ac3d3 RH |
600 | HOST_WIDE_INT val = INTVAL (operands[1]); |
601 | rtx reg = operands[0]; | |
9492393e KH |
602 | HOST_WIDE_INT sign = 1; |
603 | HOST_WIDE_INT amount; | |
3b7d443c | 604 | |
9492393e KH |
605 | /* Force VAL to be positive so that we do not have to consider the |
606 | sign. */ | |
607 | if (val < 0) | |
3b7d443c | 608 | { |
9492393e KH |
609 | val = -val; |
610 | sign = -1; | |
611 | } | |
3b7d443c | 612 | |
9492393e KH |
613 | /* Try different amounts in descending order. */ |
614 | for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; | |
615 | amount > 0; | |
616 | amount /= 2) | |
617 | { | |
1a63219b | 618 | for (; val >= amount; val -= amount) |
009ac3d3 | 619 | { |
9492393e | 620 | rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount)); |
009ac3d3 | 621 | emit_insn (gen_rtx_SET (VOIDmode, reg, tmp)); |
009ac3d3 | 622 | } |
3b7d443c JL |
623 | } |
624 | ||
9492393e | 625 | return; |
3b7d443c JL |
626 | } |
627 | ||
f5b65a56 JL |
628 | /* Return true if OP is a valid call operand, and OP represents |
629 | an operand for a small call (4 bytes instead of 6 bytes). */ | |
630 | ||
631 | int | |
632 | small_call_insn_operand (op, mode) | |
633 | rtx op; | |
441d04c6 | 634 | enum machine_mode mode ATTRIBUTE_UNUSED; |
f5b65a56 JL |
635 | { |
636 | if (GET_CODE (op) == MEM) | |
637 | { | |
638 | rtx inside = XEXP (op, 0); | |
639 | ||
640 | /* Register indirect is a small call. */ | |
641 | if (register_operand (inside, Pmode)) | |
642 | return 1; | |
643 | ||
644 | /* A call through the function vector is a small | |
645 | call too. */ | |
646 | if (GET_CODE (inside) == SYMBOL_REF | |
647 | && SYMBOL_REF_FLAG (inside)) | |
648 | return 1; | |
649 | } | |
650 | /* Otherwise it's a large call. */ | |
651 | return 0; | |
652 | } | |
653 | ||
48837e29 DE |
654 | /* Return true if OP is a valid jump operand. */ |
655 | ||
656 | int | |
657 | jump_address_operand (op, mode) | |
658 | rtx op; | |
659 | enum machine_mode mode; | |
660 | { | |
661 | if (GET_CODE (op) == REG) | |
662 | return mode == Pmode; | |
663 | ||
664 | if (GET_CODE (op) == MEM) | |
665 | { | |
666 | rtx inside = XEXP (op, 0); | |
667 | if (register_operand (inside, Pmode)) | |
668 | return 1; | |
669 | if (CONSTANT_ADDRESS_P (inside)) | |
670 | return 1; | |
671 | } | |
672 | return 0; | |
673 | } | |
674 | ||
675 | /* Recognize valid operands for bitfield instructions. */ | |
676 | ||
677 | extern int rtx_equal_function_value_matters; | |
678 | ||
679 | int | |
680 | bit_operand (op, mode) | |
681 | rtx op; | |
682 | enum machine_mode mode; | |
683 | { | |
684 | /* We can except any general operand, expept that MEM operands must | |
685 | be limited to those that use addresses valid for the 'U' constraint. */ | |
686 | if (!general_operand (op, mode)) | |
687 | return 0; | |
688 | ||
689 | /* Accept any mem during RTL generation. Otherwise, the code that does | |
690 | insv and extzv will think that we can not handle memory. However, | |
691 | to avoid reload problems, we only accept 'U' MEM operands after RTL | |
692 | generation. This means that any named pattern which uses this predicate | |
693 | must force its operands to match 'U' before emitting RTL. */ | |
694 | ||
695 | if (GET_CODE (op) == REG) | |
696 | return 1; | |
697 | if (GET_CODE (op) == SUBREG) | |
698 | return 1; | |
699 | if (!rtx_equal_function_value_matters) | |
07e4d94e KH |
700 | /* We're building rtl. */ |
701 | return GET_CODE (op) == MEM; | |
48837e29 | 702 | else |
07e4d94e KH |
703 | return (GET_CODE (op) == MEM |
704 | && EXTRA_CONSTRAINT (op, 'U')); | |
48837e29 DE |
705 | } |
706 | ||
887a8bd9 JL |
707 | int |
708 | bit_memory_operand (op, mode) | |
709 | rtx op; | |
441d04c6 | 710 | enum machine_mode mode ATTRIBUTE_UNUSED; |
887a8bd9 JL |
711 | { |
712 | return (GET_CODE (op) == MEM | |
713 | && EXTRA_CONSTRAINT (op, 'U')); | |
714 | } | |
715 | ||
48837e29 DE |
716 | /* Recognize valid operators for bit test. */ |
717 | ||
718 | int | |
719 | eq_operator (x, mode) | |
720 | rtx x; | |
441d04c6 | 721 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
722 | { |
723 | return (GET_CODE (x) == EQ || GET_CODE (x) == NE); | |
724 | } | |
725 | ||
07aae5c2 | 726 | /* Handle machine specific pragmas for compatibility with existing |
48837e29 | 727 | compilers for the H8/300. |
07aae5c2 SC |
728 | |
729 | pragma saveall generates prolog/epilog code which saves and | |
730 | restores all the registers on function entry. | |
48837e29 | 731 | |
07aae5c2 SC |
732 | pragma interrupt saves and restores all registers, and exits with |
733 | an rte instruction rather than an rts. A pointer to a function | |
734 | with this attribute may be safely used in an interrupt vector. */ | |
48837e29 | 735 | |
8b97c5f8 ZW |
736 | void |
737 | h8300_pr_interrupt (pfile) | |
738 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
07aae5c2 | 739 | { |
8b97c5f8 ZW |
740 | interrupt_handler = 1; |
741 | } | |
05a81fe5 | 742 | |
8b97c5f8 ZW |
743 | void |
744 | h8300_pr_saveall (pfile) | |
745 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
746 | { | |
747 | pragma_saveall = 1; | |
07aae5c2 | 748 | } |
8b97c5f8 | 749 | |
07aae5c2 SC |
750 | /* If the next arg with MODE and TYPE is to be passed in a register, return |
751 | the rtx to represent where it is passed. CUM represents the state after | |
752 | the last argument. NAMED is not used. */ | |
753 | ||
441d04c6 | 754 | static const char *const hand_list[] = |
48837e29 DE |
755 | { |
756 | "__main", | |
757 | "__cmpsi2", | |
758 | "__divhi3", | |
759 | "__modhi3", | |
760 | "__udivhi3", | |
761 | "__umodhi3", | |
762 | "__divsi3", | |
763 | "__modsi3", | |
764 | "__udivsi3", | |
765 | "__umodsi3", | |
766 | "__mulhi3", | |
767 | "__mulsi3", | |
768 | "__reg_memcpy", | |
769 | "__reg_memset", | |
770 | "__ucmpsi2", | |
771 | 0, | |
772 | }; | |
773 | ||
774 | /* Return an RTX to represent where a value with mode MODE will be returned | |
775 | from a function. If the result is 0, the argument is pushed. */ | |
776 | ||
07aae5c2 SC |
777 | rtx |
778 | function_arg (cum, mode, type, named) | |
779 | CUMULATIVE_ARGS *cum; | |
780 | enum machine_mode mode; | |
781 | tree type; | |
782 | int named; | |
783 | { | |
784 | rtx result = 0; | |
441d04c6 | 785 | const char *fname; |
48837e29 DE |
786 | int regpass = 0; |
787 | ||
dd07092e JL |
788 | /* Never pass unnamed arguments in registers. */ |
789 | if (!named) | |
790 | return 0; | |
791 | ||
48837e29 DE |
792 | /* Pass 3 regs worth of data in regs when user asked on the command line. */ |
793 | if (TARGET_QUICKCALL) | |
794 | regpass = 3; | |
795 | ||
796 | /* If calling hand written assembler, use 4 regs of args. */ | |
797 | ||
798 | if (cum->libcall) | |
799 | { | |
441d04c6 | 800 | const char * const *p; |
48837e29 DE |
801 | |
802 | fname = XSTR (cum->libcall, 0); | |
803 | ||
804 | /* See if this libcall is one of the hand coded ones. */ | |
07aae5c2 | 805 | |
48837e29 DE |
806 | for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) |
807 | ; | |
07aae5c2 | 808 | |
48837e29 DE |
809 | if (*p) |
810 | regpass = 4; | |
811 | } | |
812 | ||
813 | if (regpass) | |
814 | { | |
815 | int size; | |
816 | ||
817 | if (mode == BLKmode) | |
818 | size = int_size_in_bytes (type); | |
819 | else | |
820 | size = GET_MODE_SIZE (mode); | |
821 | ||
822 | if (size + cum->nbytes > regpass * UNITS_PER_WORD) | |
823 | { | |
824 | result = 0; | |
825 | } | |
826 | else | |
827 | { | |
828 | switch (cum->nbytes / UNITS_PER_WORD) | |
829 | { | |
830 | case 0: | |
c5c76735 | 831 | result = gen_rtx_REG (mode, 0); |
48837e29 DE |
832 | break; |
833 | case 1: | |
c5c76735 | 834 | result = gen_rtx_REG (mode, 1); |
48837e29 DE |
835 | break; |
836 | case 2: | |
c5c76735 | 837 | result = gen_rtx_REG (mode, 2); |
48837e29 DE |
838 | break; |
839 | case 3: | |
c5c76735 | 840 | result = gen_rtx_REG (mode, 3); |
48837e29 DE |
841 | break; |
842 | default: | |
843 | result = 0; | |
844 | } | |
845 | } | |
846 | } | |
07aae5c2 | 847 | |
48837e29 DE |
848 | return result; |
849 | } | |
850 | \f | |
851 | /* Return the cost of the rtx R with code CODE. */ | |
07aae5c2 | 852 | |
48837e29 DE |
853 | int |
854 | const_costs (r, c) | |
855 | rtx r; | |
856 | enum rtx_code c; | |
857 | { | |
858 | switch (c) | |
07aae5c2 | 859 | { |
48837e29 DE |
860 | case CONST_INT: |
861 | switch (INTVAL (r)) | |
07aae5c2 SC |
862 | { |
863 | case 0: | |
48837e29 | 864 | case 1: |
07aae5c2 | 865 | case 2: |
48837e29 DE |
866 | case -1: |
867 | case -2: | |
07aae5c2 | 868 | return 0; |
5ae5999c JL |
869 | case 4: |
870 | case -4: | |
a1616dd9 | 871 | if (TARGET_H8300H || TARGET_H8300S) |
5ae5999c JL |
872 | return 0; |
873 | else | |
874 | return 1; | |
48837e29 DE |
875 | default: |
876 | return 1; | |
07aae5c2 | 877 | } |
48837e29 DE |
878 | |
879 | case CONST: | |
880 | case LABEL_REF: | |
881 | case SYMBOL_REF: | |
882 | return 3; | |
883 | ||
884 | case CONST_DOUBLE: | |
885 | return 20; | |
886 | ||
887 | default: | |
888 | return 4; | |
07aae5c2 | 889 | } |
07aae5c2 | 890 | } |
48837e29 | 891 | \f |
07aae5c2 SC |
892 | /* Documentation for the machine specific operand escapes: |
893 | ||
e8205901 | 894 | 'A' print rn in H8/300 mode, erN in H8/300H mode |
07aae5c2 | 895 | 'C' print (operand - 2). |
48837e29 DE |
896 | 'E' like s but negative. |
897 | 'F' like t but negative. | |
898 | 'G' constant just the negative | |
07aae5c2 | 899 | 'M' turn a 'M' constant into its negative mod 2. |
48837e29 | 900 | 'P' if operand is incing/decing sp, print .w, otherwise .b. |
15dc331e JL |
901 | 'R' print operand as a byte:8 address if appropriate, else fall back to |
902 | 'X' handling. | |
48837e29 | 903 | 'S' print operand as a long word |
07aae5c2 | 904 | 'T' print operand as a word |
48837e29 DE |
905 | 'U' if operand is incing/decing sp, print l, otherwise nothing. |
906 | 'V' find the set bit, and print its number. | |
907 | 'W' find the clear bit, and print its number. | |
908 | 'X' print operand as a byte | |
07aae5c2 | 909 | 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. |
15dc331e | 910 | If this operand isn't a register, fall back to 'R' handling. |
48837e29 DE |
911 | 'Z' print int & 7. |
912 | 'b' print the bit opcode | |
913 | 'c' print the ibit opcode | |
914 | 'd' bcc if EQ, bcs if NE | |
915 | 'e' first word of 32 bit value - if reg, then least reg. if mem | |
916 | then least. if const then most sig word | |
917 | 'f' second word of 32 bit value - if reg, then biggest reg. if mem | |
918 | then +2. if const then least sig word | |
919 | 'g' bcs if EQ, bcc if NE | |
07aae5c2 SC |
920 | 'j' print operand as condition code. |
921 | 'k' print operand as reverse condition code. | |
48837e29 DE |
922 | 's' print as low byte of 16 bit value |
923 | 't' print as high byte of 16 bit value | |
924 | 'w' print as low byte of 32 bit value | |
925 | 'x' print as 2nd byte of 32 bit value | |
926 | 'y' print as 3rd byte of 32 bit value | |
927 | 'z' print as msb of 32 bit value | |
928 | */ | |
07aae5c2 SC |
929 | |
930 | /* Return assembly language string which identifies a comparison type. */ | |
931 | ||
441d04c6 | 932 | static const char * |
07aae5c2 SC |
933 | cond_string (code) |
934 | enum rtx_code code; | |
935 | { | |
936 | switch (code) | |
937 | { | |
938 | case NE: | |
939 | return "ne"; | |
940 | case EQ: | |
941 | return "eq"; | |
942 | case GE: | |
943 | return "ge"; | |
944 | case GT: | |
945 | return "gt"; | |
946 | case LE: | |
947 | return "le"; | |
948 | case LT: | |
949 | return "lt"; | |
950 | case GEU: | |
951 | return "hs"; | |
952 | case GTU: | |
953 | return "hi"; | |
954 | case LEU: | |
955 | return "ls"; | |
956 | case LTU: | |
957 | return "lo"; | |
958 | default: | |
959 | abort (); | |
960 | } | |
961 | } | |
962 | ||
963 | /* Print operand X using operand code CODE to assembly language output file | |
964 | FILE. */ | |
965 | ||
966 | void | |
967 | print_operand (file, x, code) | |
968 | FILE *file; | |
969 | rtx x; | |
970 | int code; | |
971 | { | |
07aae5c2 | 972 | /* This is used for communication between the 'P' and 'U' codes. */ |
441d04c6 | 973 | static const char *last_p; |
07aae5c2 | 974 | |
269c14e1 | 975 | /* This is used for communication between codes V,W,Z and Y. */ |
07aae5c2 SC |
976 | static int bitint; |
977 | ||
978 | switch (code) | |
979 | { | |
48837e29 | 980 | case 'A': |
07aae5c2 | 981 | if (GET_CODE (x) == REG) |
48837e29 | 982 | fprintf (file, "%s", h8_reg_names[REGNO (x)]); |
07aae5c2 SC |
983 | else |
984 | goto def; | |
985 | break; | |
48837e29 DE |
986 | case 'C': |
987 | fprintf (file, "#%d", INTVAL (x) - 2); | |
988 | break; | |
989 | case 'E': | |
990 | switch (GET_CODE (x)) | |
991 | { | |
992 | case REG: | |
993 | fprintf (file, "%sl", names_big[REGNO (x)]); | |
994 | break; | |
995 | case CONST_INT: | |
996 | fprintf (file, "#%d", (-INTVAL (x)) & 0xff); | |
997 | break; | |
998 | default: | |
999 | abort (); | |
1000 | } | |
1001 | break; | |
1002 | case 'F': | |
1003 | switch (GET_CODE (x)) | |
1004 | { | |
1005 | case REG: | |
1006 | fprintf (file, "%sh", names_big[REGNO (x)]); | |
1007 | break; | |
1008 | case CONST_INT: | |
1009 | fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8); | |
1010 | break; | |
1011 | default: | |
1012 | abort (); | |
1013 | } | |
1014 | break; | |
07aae5c2 SC |
1015 | case 'G': |
1016 | if (GET_CODE (x) != CONST_INT) | |
1017 | abort (); | |
1018 | fprintf (file, "#%d", 0xff & (-INTVAL (x))); | |
1019 | break; | |
48837e29 DE |
1020 | case 'M': |
1021 | /* For 3/-3 and 4/-4, the other 2 is handled separately. */ | |
1022 | switch (INTVAL (x)) | |
1023 | { | |
1024 | case 2: | |
1025 | case 4: | |
1026 | case -2: | |
1027 | case -4: | |
1028 | fprintf (file, "#2"); | |
1029 | break; | |
1030 | case 1: | |
1031 | case 3: | |
1032 | case -1: | |
1033 | case -3: | |
1034 | fprintf (file, "#1"); | |
1035 | break; | |
1036 | default: | |
1037 | abort (); | |
1038 | } | |
07aae5c2 | 1039 | break; |
48837e29 DE |
1040 | case 'P': |
1041 | if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM) | |
1042 | { | |
1043 | last_p = ""; | |
1044 | fprintf (file, ".w"); | |
1045 | } | |
07aae5c2 | 1046 | else |
48837e29 DE |
1047 | { |
1048 | last_p = "l"; | |
1049 | fprintf (file, ".b"); | |
1050 | } | |
07aae5c2 | 1051 | break; |
48837e29 DE |
1052 | case 'S': |
1053 | if (GET_CODE (x) == REG) | |
1054 | fprintf (file, "%s", names_extended[REGNO (x)]); | |
07aae5c2 | 1055 | else |
48837e29 | 1056 | goto def; |
07aae5c2 | 1057 | break; |
48837e29 DE |
1058 | case 'T': |
1059 | if (GET_CODE (x) == REG) | |
1060 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1061 | else |
48837e29 | 1062 | goto def; |
07aae5c2 | 1063 | break; |
48837e29 DE |
1064 | case 'U': |
1065 | fprintf (file, "%s%s", names_big[REGNO (x)], last_p); | |
07aae5c2 | 1066 | break; |
48837e29 DE |
1067 | case 'V': |
1068 | bitint = exact_log2 (INTVAL (x)); | |
1069 | if (bitint == -1) | |
07aae5c2 | 1070 | abort (); |
07aae5c2 SC |
1071 | fprintf (file, "#%d", bitint & 7); |
1072 | break; | |
48837e29 | 1073 | case 'W': |
07aae5c2 SC |
1074 | bitint = exact_log2 ((~INTVAL (x)) & 0xff); |
1075 | if (bitint == -1) | |
1076 | abort (); | |
1077 | fprintf (file, "#%d", bitint & 7); | |
1078 | break; | |
15dc331e | 1079 | case 'R': |
48837e29 DE |
1080 | case 'X': |
1081 | if (GET_CODE (x) == REG) | |
1082 | fprintf (file, "%s", byte_reg (x, 0)); | |
1083 | else | |
1084 | goto def; | |
1085 | break; | |
1086 | case 'Y': | |
07aae5c2 SC |
1087 | if (bitint == -1) |
1088 | abort (); | |
48837e29 DE |
1089 | if (GET_CODE (x) == REG) |
1090 | fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); | |
1091 | else | |
15dc331e | 1092 | print_operand (file, x, 'R'); |
48837e29 DE |
1093 | bitint = -1; |
1094 | break; | |
1095 | case 'Z': | |
1096 | bitint = INTVAL (x); | |
07aae5c2 SC |
1097 | fprintf (file, "#%d", bitint & 7); |
1098 | break; | |
48837e29 DE |
1099 | case 'b': |
1100 | switch (GET_CODE (x)) | |
07aae5c2 | 1101 | { |
48837e29 DE |
1102 | case IOR: |
1103 | fprintf (file, "bor"); | |
1104 | break; | |
1105 | case XOR: | |
1106 | fprintf (file, "bxor"); | |
1107 | break; | |
1108 | case AND: | |
1109 | fprintf (file, "band"); | |
1110 | break; | |
441d04c6 KG |
1111 | default: |
1112 | break; | |
07aae5c2 | 1113 | } |
48837e29 DE |
1114 | break; |
1115 | case 'c': | |
1116 | switch (GET_CODE (x)) | |
07aae5c2 | 1117 | { |
48837e29 DE |
1118 | case IOR: |
1119 | fprintf (file, "bior"); | |
1120 | break; | |
1121 | case XOR: | |
1122 | fprintf (file, "bixor"); | |
1123 | break; | |
1124 | case AND: | |
1125 | fprintf (file, "biand"); | |
1126 | break; | |
441d04c6 KG |
1127 | default: |
1128 | break; | |
07aae5c2 SC |
1129 | } |
1130 | break; | |
48837e29 DE |
1131 | case 'd': |
1132 | switch (GET_CODE (x)) | |
07aae5c2 | 1133 | { |
48837e29 DE |
1134 | case EQ: |
1135 | fprintf (file, "bcc"); | |
07aae5c2 | 1136 | break; |
48837e29 DE |
1137 | case NE: |
1138 | fprintf (file, "bcs"); | |
07aae5c2 | 1139 | break; |
07aae5c2 SC |
1140 | default: |
1141 | abort (); | |
1142 | } | |
1143 | break; | |
07aae5c2 SC |
1144 | case 'e': |
1145 | switch (GET_CODE (x)) | |
1146 | { | |
1147 | case REG: | |
48837e29 DE |
1148 | if (TARGET_H8300) |
1149 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1150 | else | |
1151 | fprintf (file, "%s", names_upper_extended[REGNO (x)]); | |
07aae5c2 SC |
1152 | break; |
1153 | case MEM: | |
1154 | x = adj_offsettable_operand (x, 0); | |
1155 | print_operand (file, x, 0); | |
1156 | break; | |
1157 | case CONST_INT: | |
1158 | fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff)); | |
1159 | break; | |
808fbfac JL |
1160 | case CONST_DOUBLE: |
1161 | { | |
1162 | long val; | |
1163 | REAL_VALUE_TYPE rv; | |
1164 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1165 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1166 | fprintf (file, "#%ld", ((val >> 16) & 0xffff)); |
808fbfac JL |
1167 | break; |
1168 | } | |
07aae5c2 SC |
1169 | default: |
1170 | abort (); | |
1171 | break; | |
1172 | } | |
1173 | break; | |
07aae5c2 SC |
1174 | case 'f': |
1175 | switch (GET_CODE (x)) | |
1176 | { | |
1177 | case REG: | |
48837e29 DE |
1178 | if (TARGET_H8300) |
1179 | fprintf (file, "%s", names_big[REGNO (x) + 1]); | |
1180 | else | |
1181 | fprintf (file, "%s", names_big[REGNO (x)]); | |
07aae5c2 | 1182 | break; |
07aae5c2 SC |
1183 | case MEM: |
1184 | x = adj_offsettable_operand (x, 2); | |
1185 | print_operand (file, x, 0); | |
1186 | break; | |
07aae5c2 SC |
1187 | case CONST_INT: |
1188 | fprintf (file, "#%d", INTVAL (x) & 0xffff); | |
1189 | break; | |
808fbfac JL |
1190 | case CONST_DOUBLE: |
1191 | { | |
1192 | long val; | |
1193 | REAL_VALUE_TYPE rv; | |
1194 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1195 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1196 | fprintf (file, "#%ld", (val & 0xffff)); |
808fbfac JL |
1197 | break; |
1198 | } | |
07aae5c2 SC |
1199 | default: |
1200 | abort (); | |
1201 | } | |
1202 | break; | |
48837e29 | 1203 | case 'g': |
07aae5c2 SC |
1204 | switch (GET_CODE (x)) |
1205 | { | |
48837e29 DE |
1206 | case NE: |
1207 | fprintf (file, "bcc"); | |
07aae5c2 | 1208 | break; |
48837e29 DE |
1209 | case EQ: |
1210 | fprintf (file, "bcs"); | |
07aae5c2 | 1211 | break; |
07aae5c2 SC |
1212 | default: |
1213 | abort (); | |
1214 | } | |
1215 | break; | |
07aae5c2 SC |
1216 | case 'j': |
1217 | asm_fprintf (file, cond_string (GET_CODE (x))); | |
1218 | break; | |
07aae5c2 SC |
1219 | case 'k': |
1220 | asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x)))); | |
1221 | break; | |
48837e29 DE |
1222 | case 's': |
1223 | if (GET_CODE (x) == CONST_INT) | |
1224 | fprintf (file, "#%d", (INTVAL (x)) & 0xff); | |
1225 | else | |
1226 | fprintf (file, "%s", byte_reg (x, 0)); | |
1227 | break; | |
1228 | case 't': | |
1229 | if (GET_CODE (x) == CONST_INT) | |
1230 | fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); | |
1231 | else | |
1232 | fprintf (file, "%s", byte_reg (x, 1)); | |
1233 | break; | |
1234 | case 'u': | |
1235 | if (GET_CODE (x) != CONST_INT) | |
1236 | abort (); | |
1237 | fprintf (file, "%d", INTVAL (x)); | |
1238 | break; | |
1239 | case 'w': | |
1240 | if (GET_CODE (x) == CONST_INT) | |
1241 | fprintf (file, "#%d", INTVAL (x) & 0xff); | |
1242 | else | |
a1616dd9 JL |
1243 | fprintf (file, "%s", |
1244 | byte_reg (x, TARGET_H8300 ? 2 : 0)); | |
48837e29 DE |
1245 | break; |
1246 | case 'x': | |
1247 | if (GET_CODE (x) == CONST_INT) | |
1248 | fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); | |
1249 | else | |
a1616dd9 JL |
1250 | fprintf (file, "%s", |
1251 | byte_reg (x, TARGET_H8300 ? 3 : 1)); | |
48837e29 DE |
1252 | break; |
1253 | case 'y': | |
1254 | if (GET_CODE (x) == CONST_INT) | |
1255 | fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff); | |
1256 | else | |
1257 | fprintf (file, "%s", byte_reg (x, 0)); | |
1258 | break; | |
1259 | case 'z': | |
1260 | if (GET_CODE (x) == CONST_INT) | |
1261 | fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff); | |
1262 | else | |
1263 | fprintf (file, "%s", byte_reg (x, 1)); | |
1264 | break; | |
1265 | ||
07aae5c2 | 1266 | default: |
48837e29 | 1267 | def: |
07aae5c2 SC |
1268 | switch (GET_CODE (x)) |
1269 | { | |
1270 | case REG: | |
48837e29 DE |
1271 | switch (GET_MODE (x)) |
1272 | { | |
1273 | case QImode: | |
269c14e1 | 1274 | #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ |
48837e29 DE |
1275 | fprintf (file, "%s", byte_reg (x, 0)); |
1276 | #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ | |
1277 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1278 | #endif | |
1279 | break; | |
1280 | case HImode: | |
1281 | fprintf (file, "%s", names_big[REGNO (x)]); | |
1282 | break; | |
1283 | case SImode: | |
8977e8a7 | 1284 | case SFmode: |
48837e29 DE |
1285 | fprintf (file, "%s", names_extended[REGNO (x)]); |
1286 | break; | |
1287 | default: | |
1288 | abort (); | |
1289 | } | |
07aae5c2 SC |
1290 | break; |
1291 | ||
1292 | case MEM: | |
1293 | fprintf (file, "@"); | |
1294 | output_address (XEXP (x, 0)); | |
15dc331e | 1295 | |
a653b93f VM |
1296 | /* If this is an 'R' operand (reference into the 8-bit |
1297 | area), then specify a symbolic address as "foo:8", | |
1298 | otherwise if operand is still in eight bit section, use | |
1299 | "foo:16". */ | |
07e4d94e | 1300 | if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
15dc331e | 1301 | && SYMBOL_REF_FLAG (XEXP (x, 0))) |
a653b93f VM |
1302 | fprintf (file, (code == 'R' ? ":8" : ":16")); |
1303 | else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF | |
07e4d94e | 1304 | && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0))) |
887a8bd9 | 1305 | fprintf (file, ":16"); |
9f9f0e4f KH |
1306 | else if ((code == 'R') |
1307 | && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
1308 | fprintf (file, ":8"); | |
07aae5c2 SC |
1309 | break; |
1310 | ||
1311 | case CONST_INT: | |
1312 | case SYMBOL_REF: | |
1313 | case CONST: | |
1314 | case LABEL_REF: | |
1315 | fprintf (file, "#"); | |
1316 | print_operand_address (file, x); | |
1317 | break; | |
808fbfac JL |
1318 | case CONST_DOUBLE: |
1319 | { | |
1320 | long val; | |
1321 | REAL_VALUE_TYPE rv; | |
1322 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
1323 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
441d04c6 | 1324 | fprintf (file, "#%ld", val); |
808fbfac JL |
1325 | break; |
1326 | } | |
441d04c6 KG |
1327 | default: |
1328 | break; | |
07aae5c2 SC |
1329 | } |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* Output assembly language output for the address ADDR to FILE. */ | |
1334 | ||
1335 | void | |
1336 | print_operand_address (file, addr) | |
1337 | FILE *file; | |
1338 | rtx addr; | |
1339 | { | |
1340 | switch (GET_CODE (addr)) | |
1341 | { | |
1342 | case REG: | |
48837e29 | 1343 | fprintf (file, "%s", h8_reg_names[REGNO (addr)]); |
07aae5c2 SC |
1344 | break; |
1345 | ||
1346 | case PRE_DEC: | |
48837e29 | 1347 | fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1348 | break; |
1349 | ||
1350 | case POST_INC: | |
48837e29 | 1351 | fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); |
07aae5c2 SC |
1352 | break; |
1353 | ||
1354 | case PLUS: | |
1355 | fprintf (file, "("); | |
1356 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
1357 | { | |
1358 | /* reg,foo */ | |
1359 | print_operand_address (file, XEXP (addr, 1)); | |
1360 | fprintf (file, ","); | |
1361 | print_operand_address (file, XEXP (addr, 0)); | |
1362 | } | |
1363 | else | |
1364 | { | |
1365 | /* foo+k */ | |
1366 | print_operand_address (file, XEXP (addr, 0)); | |
1367 | fprintf (file, "+"); | |
1368 | print_operand_address (file, XEXP (addr, 1)); | |
1369 | } | |
1370 | fprintf (file, ")"); | |
1371 | break; | |
1372 | ||
1373 | case CONST_INT: | |
48837e29 | 1374 | { |
64530b82 | 1375 | /* Since the H8/300 only has 16 bit pointers, negative values are also |
48837e29 DE |
1376 | those >= 32768. This happens for example with pointer minus a |
1377 | constant. We don't want to turn (char *p - 2) into | |
1378 | (char *p + 65534) because loop unrolling can build upon this | |
1379 | (IE: char *p + 131068). */ | |
1380 | int n = INTVAL (addr); | |
1381 | if (TARGET_H8300) | |
1382 | n = (int) (short) n; | |
1383 | if (n < 0) | |
07e4d94e | 1384 | /* ??? Why the special case for -ve values? */ |
48837e29 DE |
1385 | fprintf (file, "-%d", -n); |
1386 | else | |
1387 | fprintf (file, "%d", n); | |
1388 | break; | |
1389 | } | |
07aae5c2 SC |
1390 | |
1391 | default: | |
1392 | output_addr_const (file, addr); | |
1393 | break; | |
1394 | } | |
1395 | } | |
1396 | \f | |
07aae5c2 SC |
1397 | /* Output all insn addresses and their sizes into the assembly language |
1398 | output file. This is helpful for debugging whether the length attributes | |
1399 | in the md file are correct. This is not meant to be a user selectable | |
1400 | option. */ | |
1401 | ||
1402 | void | |
1403 | final_prescan_insn (insn, operand, num_operands) | |
441d04c6 KG |
1404 | rtx insn, *operand ATTRIBUTE_UNUSED; |
1405 | int num_operands ATTRIBUTE_UNUSED; | |
07aae5c2 SC |
1406 | { |
1407 | /* This holds the last insn address. */ | |
1408 | static int last_insn_address = 0; | |
1409 | ||
1410 | int uid = INSN_UID (insn); | |
1411 | ||
48837e29 DE |
1412 | if (TARGET_RTL_DUMP) |
1413 | { | |
1414 | fprintf (asm_out_file, "\n****************"); | |
1415 | print_rtl (asm_out_file, PATTERN (insn)); | |
1416 | fprintf (asm_out_file, "\n"); | |
1417 | } | |
1418 | ||
07aae5c2 SC |
1419 | if (TARGET_ADDRESSES) |
1420 | { | |
9d98a694 AO |
1421 | fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), |
1422 | INSN_ADDRESSES (uid) - last_insn_address); | |
1423 | last_insn_address = INSN_ADDRESSES (uid); | |
07aae5c2 SC |
1424 | } |
1425 | } | |
1426 | ||
48837e29 DE |
1427 | /* Prepare for an SI sized move. */ |
1428 | ||
1429 | int | |
1430 | do_movsi (operands) | |
1431 | rtx operands[]; | |
07aae5c2 | 1432 | { |
48837e29 DE |
1433 | rtx src = operands[1]; |
1434 | rtx dst = operands[0]; | |
1435 | if (!reload_in_progress && !reload_completed) | |
1436 | { | |
1437 | if (!register_operand (dst, GET_MODE (dst))) | |
1438 | { | |
1439 | rtx tmp = gen_reg_rtx (GET_MODE (dst)); | |
1440 | emit_move_insn (tmp, src); | |
1441 | operands[1] = tmp; | |
1442 | } | |
1443 | } | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). | |
07e4d94e KH |
1448 | Define the offset between two registers, one to be eliminated, and |
1449 | the other its replacement, at the start of a routine. */ | |
07aae5c2 | 1450 | |
48837e29 DE |
1451 | int |
1452 | initial_offset (from, to) | |
441d04c6 | 1453 | int from, to; |
48837e29 DE |
1454 | { |
1455 | int offset = 0; | |
1456 | ||
1457 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
1458 | offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD; | |
1459 | else | |
07aae5c2 | 1460 | { |
48837e29 DE |
1461 | int regno; |
1462 | ||
1463 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
d01d2903 | 1464 | if (WORD_REG_USED (regno)) |
48837e29 DE |
1465 | offset += UNITS_PER_WORD; |
1466 | ||
1467 | /* See the comments for get_frame_size. We need to round it up to | |
1468 | STACK_BOUNDARY. */ | |
1469 | ||
1470 | offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1) | |
1471 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
1472 | ||
1473 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
1474 | offset += UNITS_PER_WORD; /* Skip saved PC */ | |
1475 | } | |
1476 | return offset; | |
1477 | } | |
1478 | ||
1479 | /* Update the condition code from the insn. */ | |
1480 | ||
441d04c6 | 1481 | void |
48837e29 DE |
1482 | notice_update_cc (body, insn) |
1483 | rtx body; | |
1484 | rtx insn; | |
1485 | { | |
1486 | switch (get_attr_cc (insn)) | |
1487 | { | |
1488 | case CC_NONE: | |
269c14e1 | 1489 | /* Insn does not affect CC at all. */ |
48837e29 DE |
1490 | break; |
1491 | ||
1492 | case CC_NONE_0HIT: | |
269c14e1 | 1493 | /* Insn does not change CC, but the 0'th operand has been changed. */ |
48837e29 | 1494 | if (cc_status.value1 != 0 |
1ccbefce | 1495 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
48837e29 | 1496 | cc_status.value1 = 0; |
48837e29 DE |
1497 | break; |
1498 | ||
065bbfe6 | 1499 | case CC_SET_ZN: |
1ccbefce | 1500 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
269c14e1 DE |
1501 | The V flag is unusable. The C flag may or may not be known but |
1502 | that's ok because alter_cond will change tests to use EQ/NE. */ | |
48837e29 | 1503 | CC_STATUS_INIT; |
269c14e1 | 1504 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
1ccbefce | 1505 | cc_status.value1 = recog_data.operand[0]; |
48837e29 DE |
1506 | break; |
1507 | ||
065bbfe6 | 1508 | case CC_SET_ZNV: |
1ccbefce | 1509 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
065bbfe6 JL |
1510 | The C flag may or may not be known but that's ok because |
1511 | alter_cond will change tests to use EQ/NE. */ | |
1512 | CC_STATUS_INIT; | |
1513 | cc_status.flags |= CC_NO_CARRY; | |
1ccbefce | 1514 | cc_status.value1 = recog_data.operand[0]; |
065bbfe6 JL |
1515 | break; |
1516 | ||
269c14e1 DE |
1517 | case CC_COMPARE: |
1518 | /* The insn is a compare instruction. */ | |
48837e29 | 1519 | CC_STATUS_INIT; |
269c14e1 | 1520 | cc_status.value1 = SET_SRC (body); |
48837e29 DE |
1521 | break; |
1522 | ||
48837e29 | 1523 | case CC_CLOBBER: |
269c14e1 | 1524 | /* Insn doesn't leave CC in a usable state. */ |
48837e29 DE |
1525 | CC_STATUS_INIT; |
1526 | break; | |
07aae5c2 | 1527 | } |
48837e29 DE |
1528 | } |
1529 | ||
07e4d94e | 1530 | /* Recognize valid operators for bit instructions. */ |
48837e29 DE |
1531 | |
1532 | int | |
1533 | bit_operator (x, mode) | |
1534 | rtx x; | |
441d04c6 | 1535 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
1536 | { |
1537 | enum rtx_code code = GET_CODE (x); | |
07aae5c2 | 1538 | |
48837e29 DE |
1539 | return (code == XOR |
1540 | || code == AND | |
1541 | || code == IOR); | |
07aae5c2 | 1542 | } |
48837e29 DE |
1543 | \f |
1544 | /* Shifts. | |
1545 | ||
1546 | We devote a fair bit of code to getting efficient shifts since we can only | |
51c0c1d7 JL |
1547 | shift one bit at a time on the H8/300 and H8/300H and only one or two |
1548 | bits at a time on the H8/S. | |
1549 | ||
1550 | The basic shift methods: | |
1551 | ||
1552 | * loop shifts -- emit a loop using one (or two on H8/S) bit shifts; | |
1553 | this is the default. SHIFT_LOOP | |
1554 | ||
1555 | * inlined shifts -- emit straight line code for the shift; this is | |
1556 | used when a straight line shift is about the same size or smaller | |
1557 | than a loop. We allow the inline version to be slightly longer in | |
1558 | some cases as it saves a register. SHIFT_INLINE | |
1559 | ||
1560 | * rotate + and -- rotate the value the opposite direction, then | |
1561 | mask off the values we don't need. This is used when only a few | |
1562 | of the bits in the original value will survive in the shifted value. | |
1563 | Again, this is used when it's about the same size or smaller than | |
1564 | a loop. We allow this version to be slightly longer as it is usually | |
1565 | much faster than a loop. SHIFT_ROT_AND | |
1566 | ||
1567 | * swap (+ shifts) -- often it's possible to swap bytes/words to | |
1568 | simulate a shift by 8/16. Once swapped a few inline shifts can be | |
1569 | added if the shift count is slightly more than 8 or 16. This is used | |
1570 | when it's about the same size or smaller than a loop. We allow this | |
1571 | version to be slightly longer as it is usually much faster than a loop. | |
1572 | SHIFT_SPECIAL | |
1573 | ||
1574 | * There other oddballs. Not worth explaining. SHIFT_SPECIAL | |
1575 | ||
48837e29 DE |
1576 | Here are some thoughts on what the absolutely positively best code is. |
1577 | "Best" here means some rational trade-off between code size and speed, | |
1578 | where speed is more preferred but not at the expense of generating 20 insns. | |
1579 | ||
51c0c1d7 JL |
1580 | A trailing '*' after the shift count indicates the "best" mode isn't |
1581 | implemented. | |
1582 | ||
48837e29 | 1583 | H8/300 QImode shifts |
51c0c1d7 JL |
1584 | 1-4 - do them inline |
1585 | 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1586 | ASHIFTRT: loop | |
1587 | 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1588 | ASHIFTRT: shll, subx (propagate carry bit to all bits) | |
48837e29 DE |
1589 | |
1590 | H8/300 HImode shifts | |
51c0c1d7 JL |
1591 | 1-4 - do them inline |
1592 | 5-6 - loop | |
1593 | 7 - shift 2nd half other way into carry. | |
1594 | copy 1st half into 2nd half | |
1595 | rotate 2nd half other way with carry | |
1596 | rotate 1st half other way (no carry) | |
1597 | mask off bits in 1st half (ASHIFT | LSHIFTRT). | |
1598 | sign extend 1st half (ASHIFTRT) | |
1599 | 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) | |
1600 | 9-12 - do shift by 8, inline remaining shifts | |
1601 | 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 | |
1602 | - ASHIFTRT: loop | |
1603 | 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 | |
1604 | - ASHIFTRT: shll, subx, set other byte | |
48837e29 DE |
1605 | |
1606 | H8/300 SImode shifts | |
51c0c1d7 JL |
1607 | 1-2 - do them inline |
1608 | 3-6 - loop | |
1609 | 7* - shift other way once, move bytes into place, | |
1610 | move carry into place (possibly with sign extension) | |
1611 | 8 - move bytes into place, zero or sign extend other | |
1612 | 9-14 - loop | |
1613 | 15* - shift other way once, move word into place, move carry into place | |
1614 | 16 - move word, zero or sign extend other | |
1615 | 17-23 - loop | |
1616 | 24* - move bytes into place, zero or sign extend other | |
1617 | 25-27 - loop | |
1618 | 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place, | |
1619 | zero others | |
1620 | ASHIFTRT: loop | |
38e01259 | 1621 | 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place, |
51c0c1d7 JL |
1622 | zero others |
1623 | ASHIFTRT: shll top byte, subx, copy to other bytes | |
1624 | ||
1625 | H8/300H QImode shifts (same as H8/300 QImode shifts) | |
1626 | 1-4 - do them inline | |
1627 | 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1628 | ASHIFTRT: loop | |
1629 | 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1630 | ASHIFTRT: shll, subx (propagate carry bit to all bits) | |
1631 | ||
48837e29 | 1632 | H8/300H HImode shifts |
51c0c1d7 JL |
1633 | 1-4 - do them inline |
1634 | 5-6 - loop | |
1635 | 7 - shift 2nd half other way into carry. | |
1636 | copy 1st half into 2nd half | |
1637 | rotate entire word other way using carry | |
1638 | mask off remaining bits (ASHIFT | LSHIFTRT) | |
1639 | sign extend remaining bits (ASHIFTRT) | |
1640 | 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) | |
1641 | 9-12 - do shift by 8, inline remaining shifts | |
1642 | 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 | |
1643 | - ASHIFTRT: loop | |
1644 | 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 | |
1645 | - ASHIFTRT: shll, subx, set other byte | |
48837e29 DE |
1646 | |
1647 | H8/300H SImode shifts | |
1648 | (These are complicated by the fact that we don't have byte level access to | |
1649 | the top word.) | |
1650 | A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw) | |
51c0c1d7 JL |
1651 | 1-4 - do them inline |
1652 | 5-14 - loop | |
1653 | 15* - shift other way once, move word into place, move carry into place | |
1654 | (with sign extension for ASHIFTRT) | |
1655 | 16 - move word into place, zero or sign extend other | |
1656 | 17-20 - do 16bit shift, then inline remaining shifts | |
1657 | 20-23 - loop | |
1658 | 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0, | |
1659 | move word 0 to word 1, zero word 0 | |
1660 | LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1661 | zero word 1, zero byte 1 | |
1662 | ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1663 | sign extend byte 0, sign extend word 0 | |
1664 | 25-27* - either loop, or | |
1665 | do 24 bit shift, inline rest | |
1666 | 28-30 - ASHIFT: rotate 4/3/2, mask | |
1667 | LSHIFTRT: rotate 4/3/2, mask | |
1668 | ASHIFTRT: loop | |
1669 | 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0 | |
1670 | ||
1671 | H8/S QImode shifts | |
1672 | 1-6 - do them inline | |
1673 | 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits | |
1674 | ASHIFTRT: shll, subx (propagate carry bit to all bits) | |
1675 | ||
1676 | H8/S HImode shifts | |
1677 | 1-7 - do them inline | |
1678 | 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) | |
1679 | 9-12 - do shift by 8, inline remaining shifts | |
1680 | 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 | |
1681 | - ASHIFTRT: loop | |
1682 | 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 | |
1683 | - ASHIFTRT: shll, subx, set other byte | |
1684 | ||
1685 | H8/S SImode shifts | |
1686 | (These are complicated by the fact that we don't have byte level access to | |
1687 | the top word.) | |
1688 | A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw) | |
1689 | 1-10 - do them inline | |
1690 | 11-14 - loop | |
1691 | 15* - shift other way once, move word into place, move carry into place | |
1692 | (with sign extension for ASHIFTRT) | |
1693 | 16 - move word into place, zero or sign extend other | |
1694 | 17-20 - do 16bit shift, then inline remaining shifts | |
1695 | 20-23 - loop | |
1696 | 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0, | |
1697 | move word 0 to word 1, zero word 0 | |
1698 | LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1699 | zero word 1, zero byte 1 | |
1700 | ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0, | |
1701 | sign extend byte 0, sign extend word 0 | |
1702 | 25-27* - either loop, or | |
1703 | do 24 bit shift, inline rest | |
1704 | 28-30 - ASHIFT: rotate 4/3/2, mask | |
1705 | LSHIFTRT: rotate 4/3/2, mask | |
1706 | ASHIFTRT: loop | |
1707 | 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0 | |
1708 | ||
1709 | Panic!!! */ | |
07aae5c2 SC |
1710 | |
1711 | int | |
48837e29 DE |
1712 | nshift_operator (x, mode) |
1713 | rtx x; | |
441d04c6 | 1714 | enum machine_mode mode ATTRIBUTE_UNUSED; |
48837e29 DE |
1715 | { |
1716 | switch (GET_CODE (x)) | |
1717 | { | |
1718 | case ASHIFTRT: | |
1719 | case LSHIFTRT: | |
1720 | case ASHIFT: | |
1721 | return 1; | |
1722 | ||
1723 | default: | |
1724 | return 0; | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | /* Called from the .md file to emit code to do shifts. | |
64530b82 KH |
1729 | Return a boolean indicating success. |
1730 | (Currently this is always TRUE). */ | |
48837e29 DE |
1731 | |
1732 | int | |
1733 | expand_a_shift (mode, code, operands) | |
1734 | enum machine_mode mode; | |
07aae5c2 SC |
1735 | int code; |
1736 | rtx operands[]; | |
07aae5c2 | 1737 | { |
07aae5c2 SC |
1738 | emit_move_insn (operands[0], operands[1]); |
1739 | ||
07e4d94e KH |
1740 | /* Need a loop to get all the bits we want - we generate the |
1741 | code at emit time, but need to allocate a scratch reg now. */ | |
48837e29 | 1742 | |
c5c76735 JL |
1743 | emit_insn (gen_rtx_PARALLEL |
1744 | (VOIDmode, | |
48837e29 | 1745 | gen_rtvec (2, |
c5c76735 JL |
1746 | gen_rtx_SET (VOIDmode, operands[0], |
1747 | gen_rtx (code, mode, operands[0], | |
1748 | operands[2])), | |
1749 | gen_rtx_CLOBBER (VOIDmode, | |
1750 | gen_rtx_SCRATCH (QImode))))); | |
48837e29 DE |
1751 | |
1752 | return 1; | |
1753 | } | |
1754 | ||
1755 | /* Shift algorithm determination. | |
1756 | ||
1757 | There are various ways of doing a shift: | |
1758 | SHIFT_INLINE: If the amount is small enough, just generate as many one-bit | |
1759 | shifts as we need. | |
1760 | SHIFT_ROT_AND: If the amount is large but close to either end, rotate the | |
1761 | necessary bits into position and then set the rest to zero. | |
1762 | SHIFT_SPECIAL: Hand crafted assembler. | |
1763 | SHIFT_LOOP: If the above methods fail, just loop. */ | |
1764 | ||
1765 | enum shift_alg | |
1766 | { | |
1767 | SHIFT_INLINE, | |
1768 | SHIFT_ROT_AND, | |
1769 | SHIFT_SPECIAL, | |
1770 | SHIFT_LOOP, | |
1771 | SHIFT_MAX | |
1772 | }; | |
1773 | ||
1774 | /* Symbols of the various shifts which can be used as indices. */ | |
1775 | ||
1776 | enum shift_type | |
1a63219b KH |
1777 | { |
1778 | SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT | |
1779 | }; | |
48837e29 DE |
1780 | |
1781 | /* Symbols of the various modes which can be used as indices. */ | |
1782 | ||
1783 | enum shift_mode | |
1a63219b KH |
1784 | { |
1785 | QIshift, HIshift, SIshift | |
1786 | }; | |
48837e29 | 1787 | |
269c14e1 DE |
1788 | /* For single bit shift insns, record assembler and what bits of the |
1789 | condition code are valid afterwards (represented as various CC_FOO | |
1790 | bits, 0 means CC isn't left in a usable state). */ | |
48837e29 DE |
1791 | |
1792 | struct shift_insn | |
1793 | { | |
441d04c6 | 1794 | const char *assembler; |
48837e29 DE |
1795 | int cc_valid; |
1796 | }; | |
1797 | ||
1798 | /* Assembler instruction shift table. | |
1799 | ||
1800 | These tables are used to look up the basic shifts. | |
07e4d94e | 1801 | They are indexed by cpu, shift_type, and mode. */ |
07aae5c2 | 1802 | |
48837e29 DE |
1803 | static const struct shift_insn shift_one[2][3][3] = |
1804 | { | |
1805 | /* H8/300 */ | |
1806 | { | |
1807 | /* SHIFT_ASHIFT */ | |
1808 | { | |
065bbfe6 | 1809 | { "shll\t%X0", CC_NO_CARRY }, |
51c0c1d7 JL |
1810 | { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, |
1811 | { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 } | |
48837e29 DE |
1812 | }, |
1813 | /* SHIFT_LSHIFTRT */ | |
1814 | { | |
065bbfe6 | 1815 | { "shlr\t%X0", CC_NO_CARRY }, |
51c0c1d7 JL |
1816 | { "shlr\t%t0\n\trotxr\t%s0", 0 }, |
1817 | { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 } | |
48837e29 DE |
1818 | }, |
1819 | /* SHIFT_ASHIFTRT */ | |
1820 | { | |
51c0c1d7 JL |
1821 | { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, |
1822 | { "shar\t%t0\n\trotxr\t%s0", 0 }, | |
1823 | { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 } | |
48837e29 DE |
1824 | } |
1825 | }, | |
1826 | /* H8/300H */ | |
1827 | { | |
1828 | /* SHIFT_ASHIFT */ | |
1829 | { | |
065bbfe6 JL |
1830 | { "shll.b\t%X0", CC_NO_CARRY }, |
1831 | { "shll.w\t%T0", CC_NO_CARRY }, | |
1832 | { "shll.l\t%S0", CC_NO_CARRY } | |
48837e29 DE |
1833 | }, |
1834 | /* SHIFT_LSHIFTRT */ | |
1835 | { | |
065bbfe6 JL |
1836 | { "shlr.b\t%X0", CC_NO_CARRY }, |
1837 | { "shlr.w\t%T0", CC_NO_CARRY }, | |
1838 | { "shlr.l\t%S0", CC_NO_CARRY } | |
48837e29 DE |
1839 | }, |
1840 | /* SHIFT_ASHIFTRT */ | |
1841 | { | |
51c0c1d7 JL |
1842 | { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, |
1843 | { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, | |
1844 | { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY } | |
48837e29 DE |
1845 | } |
1846 | } | |
1847 | }; | |
07aae5c2 | 1848 | |
51c0c1d7 JL |
1849 | static const struct shift_insn shift_two[3][3] = |
1850 | { | |
1851 | /* SHIFT_ASHIFT */ | |
1852 | { | |
065bbfe6 JL |
1853 | { "shll.b\t#2,%X0", CC_NO_CARRY }, |
1854 | { "shll.w\t#2,%T0", CC_NO_CARRY }, | |
1855 | { "shll.l\t#2,%S0", CC_NO_CARRY } | |
51c0c1d7 JL |
1856 | }, |
1857 | /* SHIFT_LSHIFTRT */ | |
1858 | { | |
065bbfe6 JL |
1859 | { "shlr.b\t#2,%X0", CC_NO_CARRY }, |
1860 | { "shlr.w\t#2,%T0", CC_NO_CARRY }, | |
1861 | { "shlr.l\t#2,%S0", CC_NO_CARRY } | |
51c0c1d7 JL |
1862 | }, |
1863 | /* SHIFT_ASHIFTRT */ | |
1864 | { | |
1865 | { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, | |
1866 | { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, | |
1867 | { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY } | |
1868 | } | |
1869 | }; | |
1870 | ||
48837e29 DE |
1871 | /* Rotates are organized by which shift they'll be used in implementing. |
1872 | There's no need to record whether the cc is valid afterwards because | |
1873 | it is the AND insn that will decide this. */ | |
07aae5c2 | 1874 | |
48837e29 DE |
1875 | static const char *const rotate_one[2][3][3] = |
1876 | { | |
1877 | /* H8/300 */ | |
1878 | { | |
1879 | /* SHIFT_ASHIFT */ | |
1880 | { | |
51c0c1d7 JL |
1881 | "rotr\t%X0", |
1882 | "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", | |
48837e29 DE |
1883 | 0 |
1884 | }, | |
1885 | /* SHIFT_LSHIFTRT */ | |
1886 | { | |
51c0c1d7 JL |
1887 | "rotl\t%X0", |
1888 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 DE |
1889 | 0 |
1890 | }, | |
1891 | /* SHIFT_ASHIFTRT */ | |
1892 | { | |
51c0c1d7 JL |
1893 | "rotl\t%X0", |
1894 | "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", | |
48837e29 | 1895 | 0 |
07aae5c2 | 1896 | } |
48837e29 DE |
1897 | }, |
1898 | /* H8/300H */ | |
1899 | { | |
1900 | /* SHIFT_ASHIFT */ | |
1901 | { | |
51c0c1d7 JL |
1902 | "rotr.b\t%X0", |
1903 | "rotr.w\t%T0", | |
1904 | "rotr.l\t%S0" | |
48837e29 DE |
1905 | }, |
1906 | /* SHIFT_LSHIFTRT */ | |
07aae5c2 | 1907 | { |
51c0c1d7 JL |
1908 | "rotl.b\t%X0", |
1909 | "rotl.w\t%T0", | |
1910 | "rotl.l\t%S0" | |
48837e29 DE |
1911 | }, |
1912 | /* SHIFT_ASHIFTRT */ | |
1913 | { | |
51c0c1d7 JL |
1914 | "rotl.b\t%X0", |
1915 | "rotl.w\t%T0", | |
1916 | "rotl.l\t%S0" | |
48837e29 DE |
1917 | } |
1918 | } | |
1919 | }; | |
1920 | ||
51c0c1d7 JL |
1921 | static const char *const rotate_two[3][3] = |
1922 | { | |
1923 | /* SHIFT_ASHIFT */ | |
1924 | { | |
1925 | "rotr.b\t#2,%X0", | |
1926 | "rotr.w\t#2,%T0", | |
1927 | "rotr.l\t#2,%S0" | |
1928 | }, | |
1929 | /* SHIFT_LSHIFTRT */ | |
1930 | { | |
1931 | "rotl.b\t#2,%X0", | |
1932 | "rotl.w\t#2,%T0", | |
1933 | "rotl.l\t#2,%S0" | |
1934 | }, | |
1935 | /* SHIFT_ASHIFTRT */ | |
1936 | { | |
1937 | "rotl.b\t#2,%X0", | |
1938 | "rotl.w\t#2,%T0", | |
1939 | "rotl.l\t#2,%S0" | |
1940 | } | |
1941 | }; | |
1942 | ||
441d04c6 KG |
1943 | static enum shift_alg get_shift_alg PARAMS ((enum attr_cpu, enum shift_type, |
1944 | enum machine_mode, int, | |
1945 | const char **, const char **, | |
1946 | int *)); | |
1947 | ||
48837e29 DE |
1948 | /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best |
1949 | algorithm for doing the shift. The assembler code is stored in ASSEMBLER. | |
1950 | We don't achieve maximum efficiency in all cases, but the hooks are here | |
1951 | to do so. | |
1952 | ||
1953 | For now we just use lots of switch statements. Since we don't even come | |
1954 | close to supporting all the cases, this is simplest. If this function ever | |
1955 | gets too big, perhaps resort to a more table based lookup. Of course, | |
1956 | at this point you may just wish to do it all in rtl. | |
1957 | ||
1958 | WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of | |
1959 | 1,2,3,4 will be inlined (1,2 for SI). */ | |
1960 | ||
1961 | static enum shift_alg | |
51c0c1d7 JL |
1962 | get_shift_alg (cpu, shift_type, mode, count, assembler_p, |
1963 | assembler2_p, cc_valid_p) | |
48837e29 DE |
1964 | enum attr_cpu cpu; |
1965 | enum shift_type shift_type; | |
1966 | enum machine_mode mode; | |
1967 | int count; | |
1968 | const char **assembler_p; | |
51c0c1d7 | 1969 | const char **assembler2_p; |
48837e29 DE |
1970 | int *cc_valid_p; |
1971 | { | |
48837e29 DE |
1972 | enum shift_mode shift_mode; |
1973 | ||
1974 | /* We don't handle negative shifts or shifts greater than the word size, | |
1975 | they should have been handled already. */ | |
07aae5c2 | 1976 | |
64530b82 | 1977 | if (count < 0 || (unsigned int) count > GET_MODE_BITSIZE (mode)) |
48837e29 DE |
1978 | abort (); |
1979 | ||
1980 | switch (mode) | |
1981 | { | |
1982 | case QImode: | |
1983 | shift_mode = QIshift; | |
1984 | break; | |
1985 | case HImode: | |
1986 | shift_mode = HIshift; | |
1987 | break; | |
1988 | case SImode: | |
1989 | shift_mode = SIshift; | |
1990 | break; | |
1991 | default: | |
1992 | abort (); | |
1993 | } | |
1994 | ||
1995 | /* Assume either SHIFT_LOOP or SHIFT_INLINE. | |
1996 | It is up to the caller to know that looping clobbers cc. */ | |
1997 | *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler; | |
51c0c1d7 JL |
1998 | if (TARGET_H8300S) |
1999 | *assembler2_p = shift_two[shift_type][shift_mode].assembler; | |
2000 | else | |
2001 | *assembler2_p = NULL; | |
48837e29 DE |
2002 | *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid; |
2003 | ||
2004 | /* Now look for cases we want to optimize. */ | |
2005 | ||
2006 | switch (shift_mode) | |
2007 | { | |
2008 | case QIshift: | |
2009 | if (count <= 4) | |
2010 | return SHIFT_INLINE; | |
51c0c1d7 | 2011 | else |
07aae5c2 | 2012 | { |
51c0c1d7 JL |
2013 | /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as |
2014 | fast as SHIFT_ROT_AND, plus CC is valid. */ | |
2015 | if (TARGET_H8300S && count <= 6) | |
2016 | return SHIFT_INLINE; | |
2017 | ||
2018 | /* For ASHIFTRT by 7 bits, the sign bit is simply replicated | |
2019 | through the entire value. */ | |
2020 | if (shift_type == SHIFT_ASHIFTRT && count == 7) | |
2021 | { | |
2022 | *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0"; | |
2023 | *cc_valid_p = 0; | |
2024 | return SHIFT_SPECIAL; | |
2025 | } | |
2026 | ||
2027 | /* Other ASHIFTRTs are too much of a pain. */ | |
48837e29 | 2028 | if (shift_type == SHIFT_ASHIFTRT) |
51c0c1d7 JL |
2029 | return SHIFT_LOOP; |
2030 | ||
2031 | /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */ | |
2032 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
2033 | if (TARGET_H8300S) | |
2034 | *assembler2_p = rotate_two[shift_type][shift_mode]; | |
2035 | *cc_valid_p = 0; | |
2036 | return SHIFT_ROT_AND; | |
2037 | } | |
2038 | ||
2039 | case HIshift: | |
2040 | if (count <= 4) | |
2041 | return SHIFT_INLINE; | |
2042 | else if (TARGET_H8300S && count <= 7) | |
2043 | return SHIFT_INLINE; | |
2044 | else if (count == 7) | |
2045 | { | |
2046 | if (shift_type == SHIFT_ASHIFT && TARGET_H8300) | |
48837e29 | 2047 | { |
51c0c1d7 JL |
2048 | *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; |
2049 | *cc_valid_p = 0; | |
2050 | return SHIFT_SPECIAL; | |
48837e29 | 2051 | } |
51c0c1d7 JL |
2052 | |
2053 | if (shift_type == SHIFT_ASHIFT && TARGET_H8300H) | |
48837e29 | 2054 | { |
51c0c1d7 | 2055 | *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; |
48837e29 | 2056 | *cc_valid_p = 0; |
51c0c1d7 JL |
2057 | return SHIFT_SPECIAL; |
2058 | } | |
2059 | ||
2060 | if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300) | |
2061 | { | |
2062 | *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; | |
2063 | *cc_valid_p = 0; | |
2064 | return SHIFT_SPECIAL; | |
2065 | } | |
2066 | ||
2067 | if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H) | |
2068 | { | |
2069 | *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; | |
2070 | *cc_valid_p = 0; | |
2071 | return SHIFT_SPECIAL; | |
2072 | } | |
2073 | ||
2074 | if (shift_type == SHIFT_ASHIFTRT) | |
2075 | { | |
2076 | *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; | |
2077 | *cc_valid_p = 0; | |
2078 | return SHIFT_SPECIAL; | |
48837e29 | 2079 | } |
07aae5c2 | 2080 | } |
51c0c1d7 | 2081 | else if (count == 8) |
07aae5c2 | 2082 | { |
51c0c1d7 | 2083 | switch (shift_type) |
48837e29 | 2084 | { |
51c0c1d7 JL |
2085 | case SHIFT_ASHIFT: |
2086 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; | |
2087 | *cc_valid_p = 0; | |
2088 | return SHIFT_SPECIAL; | |
2089 | case SHIFT_LSHIFTRT: | |
2090 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; | |
2091 | *cc_valid_p = 0; | |
2092 | return SHIFT_SPECIAL; | |
2093 | case SHIFT_ASHIFTRT: | |
2094 | if (TARGET_H8300) | |
2095 | *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t"; | |
2096 | else | |
2097 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0"; | |
48837e29 DE |
2098 | *cc_valid_p = 0; |
2099 | return SHIFT_SPECIAL; | |
2100 | } | |
51c0c1d7 JL |
2101 | } |
2102 | else if (count == 9) | |
2103 | { | |
2104 | switch (shift_type) | |
48837e29 | 2105 | { |
51c0c1d7 JL |
2106 | case SHIFT_ASHIFT: |
2107 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0"; | |
48837e29 | 2108 | *cc_valid_p = 0; |
51c0c1d7 JL |
2109 | return SHIFT_SPECIAL; |
2110 | case SHIFT_LSHIFTRT: | |
2111 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0"; | |
2112 | *cc_valid_p = 0; | |
2113 | return SHIFT_SPECIAL; | |
2114 | case SHIFT_ASHIFTRT: | |
2115 | if (TARGET_H8300) | |
2116 | *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0"; | |
2117 | else | |
2118 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0"; | |
2119 | *cc_valid_p = 0; | |
2120 | return SHIFT_SPECIAL; | |
48837e29 | 2121 | } |
07aae5c2 | 2122 | } |
51c0c1d7 | 2123 | else if (count == 10) |
48837e29 DE |
2124 | { |
2125 | switch (shift_type) | |
2126 | { | |
2127 | case SHIFT_ASHIFT: | |
51c0c1d7 JL |
2128 | if (TARGET_H8300S) |
2129 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t"; | |
2130 | else | |
2131 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0"; | |
48837e29 DE |
2132 | *cc_valid_p = 0; |
2133 | return SHIFT_SPECIAL; | |
2134 | case SHIFT_LSHIFTRT: | |
51c0c1d7 JL |
2135 | if (TARGET_H8300S) |
2136 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0"; | |
2137 | else | |
2138 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; | |
48837e29 DE |
2139 | *cc_valid_p = 0; |
2140 | return SHIFT_SPECIAL; | |
2141 | case SHIFT_ASHIFTRT: | |
51c0c1d7 JL |
2142 | if (TARGET_H8300) |
2143 | *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2144 | else if (TARGET_H8300H) | |
2145 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2146 | else if (TARGET_H8300S) | |
2147 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0"; | |
2148 | *cc_valid_p = 0; | |
2149 | return SHIFT_SPECIAL; | |
2150 | } | |
2151 | } | |
2152 | else if (count == 11) | |
2153 | { | |
2154 | switch (shift_type) | |
2155 | { | |
2156 | case SHIFT_ASHIFT: | |
2157 | if (TARGET_H8300S) | |
2158 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0"; | |
2159 | else | |
2160 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0"; | |
2161 | *cc_valid_p = 0; | |
2162 | return SHIFT_SPECIAL; | |
2163 | case SHIFT_LSHIFTRT: | |
2164 | if (TARGET_H8300S) | |
2165 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0"; | |
48837e29 | 2166 | else |
51c0c1d7 JL |
2167 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; |
2168 | *cc_valid_p = 0; | |
2169 | return SHIFT_SPECIAL; | |
2170 | case SHIFT_ASHIFTRT: | |
2171 | if (TARGET_H8300) | |
2172 | *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2173 | else if (TARGET_H8300H) | |
2174 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2175 | else if (TARGET_H8300S) | |
2176 | *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0"; | |
48837e29 DE |
2177 | *cc_valid_p = 0; |
2178 | return SHIFT_SPECIAL; | |
2179 | } | |
48837e29 | 2180 | } |
51c0c1d7 | 2181 | else if (count == 12) |
07aae5c2 | 2182 | { |
51c0c1d7 JL |
2183 | switch (shift_type) |
2184 | { | |
2185 | case SHIFT_ASHIFT: | |
2186 | if (TARGET_H8300S) | |
2187 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0"; | |
2188 | else | |
2189 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0"; | |
2190 | *cc_valid_p = 0; | |
2191 | return SHIFT_SPECIAL; | |
2192 | case SHIFT_LSHIFTRT: | |
2193 | if (TARGET_H8300S) | |
2194 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0"; | |
2195 | else | |
2196 | *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; | |
2197 | *cc_valid_p = 0; | |
2198 | return SHIFT_SPECIAL; | |
2199 | case SHIFT_ASHIFTRT: | |
2200 | if (TARGET_H8300) | |
2201 | *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2202 | else if (TARGET_H8300H) | |
2203 | *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; | |
2204 | else if (TARGET_H8300S) | |
2205 | *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0"; | |
2206 | *cc_valid_p = 0; | |
2207 | return SHIFT_SPECIAL; | |
2208 | } | |
2209 | } | |
441d04c6 | 2210 | else if ((!TARGET_H8300 && (count == 13 || count == 14)) |
51c0c1d7 JL |
2211 | || count == 15) |
2212 | { | |
2213 | if (count == 15 && shift_type == SHIFT_ASHIFTRT) | |
48837e29 | 2214 | { |
51c0c1d7 | 2215 | *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; |
48837e29 DE |
2216 | *cc_valid_p = 0; |
2217 | return SHIFT_SPECIAL; | |
2218 | } | |
7d9f07f4 | 2219 | else if (shift_type != SHIFT_ASHIFTRT) |
48837e29 DE |
2220 | { |
2221 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
51c0c1d7 JL |
2222 | if (TARGET_H8300S) |
2223 | *assembler2_p = rotate_two[shift_type][shift_mode]; | |
2224 | else | |
2225 | *assembler2_p = NULL; | |
48837e29 DE |
2226 | *cc_valid_p = 0; |
2227 | return SHIFT_ROT_AND; | |
2228 | } | |
07aae5c2 | 2229 | } |
48837e29 | 2230 | break; |
51c0c1d7 | 2231 | |
48837e29 | 2232 | case SIshift: |
51c0c1d7 | 2233 | if (count <= (TARGET_H8300 ? 2 : 4)) |
48837e29 | 2234 | return SHIFT_INLINE; |
51c0c1d7 JL |
2235 | else if (TARGET_H8300S && count <= 10) |
2236 | return SHIFT_INLINE; | |
2237 | else if (count == 8 && TARGET_H8300) | |
48837e29 | 2238 | { |
51c0c1d7 | 2239 | switch (shift_type) |
48837e29 | 2240 | { |
51c0c1d7 | 2241 | case SHIFT_ASHIFT: |
808fbfac | 2242 | *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; |
51c0c1d7 JL |
2243 | *cc_valid_p = 0; |
2244 | return SHIFT_SPECIAL; | |
2245 | case SHIFT_LSHIFTRT: | |
2246 | *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; | |
2247 | *cc_valid_p = 0; | |
2248 | return SHIFT_SPECIAL; | |
2249 | case SHIFT_ASHIFTRT: | |
2250 | *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; | |
2251 | *cc_valid_p = 0; | |
2252 | return SHIFT_SPECIAL; | |
48837e29 | 2253 | } |
48837e29 | 2254 | } |
e6bcfef9 JS |
2255 | else if (count == 8 && !TARGET_H8300) |
2256 | { | |
2257 | switch (shift_type) | |
2258 | { | |
2259 | case SHIFT_ASHIFT: | |
2260 | *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; | |
2261 | *cc_valid_p = 0; | |
2262 | return SHIFT_SPECIAL; | |
2263 | case SHIFT_LSHIFTRT: | |
2264 | *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; | |
2265 | *cc_valid_p = 0; | |
2266 | return SHIFT_SPECIAL; | |
2267 | case SHIFT_ASHIFTRT: | |
2268 | *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; | |
2269 | *cc_valid_p = 0; | |
2270 | return SHIFT_SPECIAL; | |
2271 | } | |
2272 | } | |
48837e29 DE |
2273 | else if (count == 16) |
2274 | { | |
2275 | switch (shift_type) | |
2276 | { | |
2277 | case SHIFT_ASHIFT: | |
51c0c1d7 JL |
2278 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; |
2279 | *cc_valid_p = 0; | |
2280 | return SHIFT_SPECIAL; | |
2281 | case SHIFT_LSHIFTRT: | |
2282 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; | |
2283 | *cc_valid_p = 0; | |
2284 | return SHIFT_SPECIAL; | |
2285 | case SHIFT_ASHIFTRT: | |
2286 | if (TARGET_H8300) | |
2287 | *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; | |
2288 | else | |
2289 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0"; | |
2290 | *cc_valid_p = 0; | |
2291 | return SHIFT_SPECIAL; | |
2292 | } | |
2293 | } | |
2294 | else if (count == 17 && !TARGET_H8300) | |
2295 | { | |
2296 | switch (shift_type) | |
2297 | { | |
2298 | case SHIFT_ASHIFT: | |
2299 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0"; | |
2300 | *cc_valid_p = 0; | |
2301 | return SHIFT_SPECIAL; | |
2302 | case SHIFT_LSHIFTRT: | |
2303 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0"; | |
2304 | *cc_valid_p = 0; | |
2305 | return SHIFT_SPECIAL; | |
2306 | case SHIFT_ASHIFTRT: | |
2307 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0"; | |
2308 | *cc_valid_p = 0; | |
2309 | return SHIFT_SPECIAL; | |
2310 | } | |
2311 | } | |
2312 | else if (count == 18 && !TARGET_H8300) | |
2313 | { | |
2314 | switch (shift_type) | |
2315 | { | |
2316 | case SHIFT_ASHIFT: | |
2317 | if (TARGET_H8300S) | |
2318 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0"; | |
2319 | else | |
2320 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0"; | |
2321 | *cc_valid_p = 0; | |
2322 | return SHIFT_SPECIAL; | |
2323 | case SHIFT_LSHIFTRT: | |
2324 | if (TARGET_H8300S) | |
2325 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0"; | |
2326 | else | |
2327 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0"; | |
2328 | *cc_valid_p = 0; | |
2329 | return SHIFT_SPECIAL; | |
2330 | case SHIFT_ASHIFTRT: | |
2331 | if (TARGET_H8300S) | |
2332 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0"; | |
2333 | else | |
2334 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0"; | |
2335 | *cc_valid_p = 0; | |
2336 | return SHIFT_SPECIAL; | |
2337 | } | |
2338 | } | |
2339 | else if (count == 19 && !TARGET_H8300) | |
2340 | { | |
2341 | switch (shift_type) | |
2342 | { | |
2343 | case SHIFT_ASHIFT: | |
2344 | if (TARGET_H8300S) | |
2345 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0"; | |
2346 | else | |
2347 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0"; | |
48837e29 DE |
2348 | *cc_valid_p = 0; |
2349 | return SHIFT_SPECIAL; | |
2350 | case SHIFT_LSHIFTRT: | |
51c0c1d7 JL |
2351 | if (TARGET_H8300S) |
2352 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0"; | |
2353 | else | |
2354 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0"; | |
48837e29 DE |
2355 | *cc_valid_p = 0; |
2356 | return SHIFT_SPECIAL; | |
2357 | case SHIFT_ASHIFTRT: | |
51c0c1d7 JL |
2358 | if (TARGET_H8300S) |
2359 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0"; | |
48837e29 | 2360 | else |
51c0c1d7 | 2361 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0"; |
48837e29 DE |
2362 | *cc_valid_p = 0; |
2363 | return SHIFT_SPECIAL; | |
2364 | } | |
2365 | } | |
51c0c1d7 JL |
2366 | else if (count == 20 && TARGET_H8300S) |
2367 | { | |
2368 | switch (shift_type) | |
2369 | { | |
2370 | case SHIFT_ASHIFT: | |
2371 | *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0"; | |
2372 | *cc_valid_p = 0; | |
2373 | return SHIFT_SPECIAL; | |
2374 | case SHIFT_LSHIFTRT: | |
2375 | *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0"; | |
2376 | *cc_valid_p = 0; | |
2377 | return SHIFT_SPECIAL; | |
2378 | case SHIFT_ASHIFTRT: | |
2379 | *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0"; | |
2380 | *cc_valid_p = 0; | |
2381 | return SHIFT_SPECIAL; | |
2382 | } | |
2383 | } | |
e6bcfef9 JS |
2384 | else if (count == 24 && !TARGET_H8300) |
2385 | { | |
2386 | switch (shift_type) | |
2387 | { | |
2388 | case SHIFT_ASHIFT: | |
2389 | *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; | |
2390 | *cc_valid_p = 0; | |
2391 | return SHIFT_SPECIAL; | |
2392 | case SHIFT_LSHIFTRT: | |
2393 | *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; | |
2394 | *cc_valid_p = 0; | |
2395 | return SHIFT_SPECIAL; | |
2396 | case SHIFT_ASHIFTRT: | |
2397 | *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; | |
2398 | *cc_valid_p = 0; | |
2399 | return SHIFT_SPECIAL; | |
2400 | } | |
2401 | } | |
51c0c1d7 | 2402 | else if (count >= 28 && count <= 30 && !TARGET_H8300) |
48837e29 DE |
2403 | { |
2404 | if (shift_type == SHIFT_ASHIFTRT) | |
2405 | { | |
2406 | return SHIFT_LOOP; | |
2407 | } | |
2408 | else | |
2409 | { | |
51c0c1d7 JL |
2410 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; |
2411 | if (TARGET_H8300S) | |
07e4d94e | 2412 | *assembler2_p = rotate_two[shift_type][shift_mode]; |
48837e29 | 2413 | else |
51c0c1d7 JL |
2414 | *assembler2_p = NULL; |
2415 | *cc_valid_p = 0; | |
2416 | return SHIFT_ROT_AND; | |
48837e29 DE |
2417 | } |
2418 | } | |
2419 | else if (count == 31) | |
2420 | { | |
2421 | if (shift_type == SHIFT_ASHIFTRT) | |
2422 | { | |
51c0c1d7 JL |
2423 | if (TARGET_H8300) |
2424 | *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; | |
48837e29 | 2425 | else |
51c0c1d7 | 2426 | *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; |
48837e29 DE |
2427 | *cc_valid_p = 0; |
2428 | return SHIFT_SPECIAL; | |
2429 | } | |
2430 | else | |
2431 | { | |
51c0c1d7 | 2432 | if (TARGET_H8300) |
48837e29 DE |
2433 | { |
2434 | if (shift_type == SHIFT_ASHIFT) | |
51c0c1d7 | 2435 | *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; |
48837e29 | 2436 | else |
51c0c1d7 | 2437 | *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; |
48837e29 DE |
2438 | *cc_valid_p = 0; |
2439 | return SHIFT_SPECIAL; | |
2440 | } | |
2441 | else | |
2442 | { | |
2443 | *assembler_p = rotate_one[cpu][shift_type][shift_mode]; | |
07e4d94e KH |
2444 | if (TARGET_H8300S) |
2445 | *assembler2_p = rotate_two[shift_type][shift_mode]; | |
2446 | else | |
2447 | *assembler2_p = NULL; | |
48837e29 DE |
2448 | *cc_valid_p = 0; |
2449 | return SHIFT_ROT_AND; | |
2450 | } | |
2451 | } | |
2452 | } | |
2453 | break; | |
51c0c1d7 | 2454 | |
48837e29 DE |
2455 | default: |
2456 | abort (); | |
07aae5c2 | 2457 | } |
48837e29 | 2458 | |
b5eaf9ba KH |
2459 | /* No fancy method is available. Just loop. */ |
2460 | return SHIFT_LOOP; | |
07aae5c2 SC |
2461 | } |
2462 | ||
48837e29 DE |
2463 | /* Emit the assembler code for doing shifts. */ |
2464 | ||
441d04c6 | 2465 | const char * |
48837e29 | 2466 | emit_a_shift (insn, operands) |
441d04c6 | 2467 | rtx insn ATTRIBUTE_UNUSED; |
48837e29 | 2468 | rtx *operands; |
07aae5c2 | 2469 | { |
48837e29 | 2470 | static int loopend_lab; |
441d04c6 KG |
2471 | const char *assembler; |
2472 | const char *assembler2; | |
48837e29 | 2473 | int cc_valid; |
48837e29 DE |
2474 | rtx shift = operands[3]; |
2475 | enum machine_mode mode = GET_MODE (shift); | |
2476 | enum rtx_code code = GET_CODE (shift); | |
2477 | enum shift_type shift_type; | |
2478 | enum shift_mode shift_mode; | |
2479 | ||
2480 | loopend_lab++; | |
2481 | ||
2482 | switch (mode) | |
2483 | { | |
2484 | case QImode: | |
2485 | shift_mode = QIshift; | |
2486 | break; | |
2487 | case HImode: | |
2488 | shift_mode = HIshift; | |
2489 | break; | |
2490 | case SImode: | |
2491 | shift_mode = SIshift; | |
2492 | break; | |
2493 | default: | |
2494 | abort (); | |
2495 | } | |
07aae5c2 | 2496 | |
48837e29 | 2497 | switch (code) |
07aae5c2 | 2498 | { |
48837e29 DE |
2499 | case ASHIFTRT: |
2500 | shift_type = SHIFT_ASHIFTRT; | |
2501 | break; | |
2502 | case LSHIFTRT: | |
2503 | shift_type = SHIFT_LSHIFTRT; | |
2504 | break; | |
2505 | case ASHIFT: | |
2506 | shift_type = SHIFT_ASHIFT; | |
2507 | break; | |
2508 | default: | |
2509 | abort (); | |
2510 | } | |
07aae5c2 | 2511 | |
48837e29 DE |
2512 | if (GET_CODE (operands[2]) != CONST_INT) |
2513 | { | |
07e4d94e | 2514 | /* Indexing by reg, so have to loop and test at top. */ |
48837e29 DE |
2515 | output_asm_insn ("mov.b %X2,%X4", operands); |
2516 | fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab); | |
2517 | ||
2518 | /* Get the assembler code to do one shift. */ | |
51c0c1d7 JL |
2519 | get_shift_alg (cpu_type, shift_type, mode, 1, &assembler, |
2520 | &assembler2, &cc_valid); | |
b5eaf9ba KH |
2521 | |
2522 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
2523 | output_asm_insn (assembler, operands); | |
2524 | output_asm_insn ("add #0xff,%X4", operands); | |
2525 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
2526 | fprintf (asm_out_file, ".Lle%d:\n", loopend_lab); | |
2527 | ||
2528 | return ""; | |
48837e29 DE |
2529 | } |
2530 | else | |
2531 | { | |
2532 | int n = INTVAL (operands[2]); | |
2533 | enum shift_alg alg; | |
2534 | ||
2535 | /* If the count is negative, make it 0. */ | |
2536 | if (n < 0) | |
2537 | n = 0; | |
2538 | /* If the count is too big, truncate it. | |
2539 | ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to | |
2540 | do the intuitive thing. */ | |
64530b82 | 2541 | else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) |
48837e29 DE |
2542 | n = GET_MODE_BITSIZE (mode); |
2543 | ||
51c0c1d7 JL |
2544 | alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler, |
2545 | &assembler2, &cc_valid); | |
48837e29 DE |
2546 | |
2547 | switch (alg) | |
2548 | { | |
2549 | case SHIFT_INLINE: | |
51c0c1d7 JL |
2550 | /* Emit two bit shifts first. */ |
2551 | while (n > 1 && assembler2 != NULL) | |
2552 | { | |
2553 | output_asm_insn (assembler2, operands); | |
2554 | n -= 2; | |
2555 | } | |
2556 | ||
2557 | /* Now emit one bit shifts for any residual. */ | |
2558 | while (n > 0) | |
2559 | { | |
2560 | output_asm_insn (assembler, operands); | |
2561 | n -= 1; | |
2562 | } | |
2563 | ||
2564 | /* Keep track of CC. */ | |
48837e29 | 2565 | if (cc_valid) |
269c14e1 DE |
2566 | { |
2567 | cc_status.value1 = operands[0]; | |
2568 | cc_status.flags |= cc_valid; | |
2569 | } | |
48837e29 | 2570 | return ""; |
51c0c1d7 | 2571 | |
48837e29 DE |
2572 | case SHIFT_ROT_AND: |
2573 | { | |
2574 | int m = GET_MODE_BITSIZE (mode) - n; | |
2575 | int mask = (shift_type == SHIFT_ASHIFT | |
441d04c6 KG |
2576 | ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n |
2577 | : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1); | |
48837e29 | 2578 | char insn_buf[200]; |
b5eaf9ba | 2579 | |
48837e29 DE |
2580 | /* Not all possibilities of rotate are supported. They shouldn't |
2581 | be generated, but let's watch for 'em. */ | |
2582 | if (assembler == 0) | |
2583 | abort (); | |
51c0c1d7 JL |
2584 | |
2585 | /* Emit two bit rotates first. */ | |
2586 | while (m > 1 && assembler2 != NULL) | |
2587 | { | |
2588 | output_asm_insn (assembler2, operands); | |
2589 | m -= 2; | |
2590 | } | |
2591 | ||
2592 | /* Now single bit rotates for any residual. */ | |
2593 | while (m > 0) | |
2594 | { | |
2595 | output_asm_insn (assembler, operands); | |
2596 | m -= 1; | |
2597 | } | |
2598 | ||
2599 | /* Now mask off the high bits. */ | |
48837e29 DE |
2600 | if (TARGET_H8300) |
2601 | { | |
2602 | switch (mode) | |
2603 | { | |
2604 | case QImode: | |
441d04c6 | 2605 | sprintf (insn_buf, "and #%d,%%X0", mask); |
48837e29 | 2606 | cc_status.value1 = operands[0]; |
065bbfe6 | 2607 | cc_status.flags |= CC_NO_CARRY; |
48837e29 DE |
2608 | break; |
2609 | case HImode: | |
51c0c1d7 | 2610 | sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0", |
441d04c6 | 2611 | mask & 255, mask >> 8); |
48837e29 DE |
2612 | break; |
2613 | case SImode: | |
2614 | abort (); | |
441d04c6 KG |
2615 | default: |
2616 | break; | |
48837e29 DE |
2617 | } |
2618 | } | |
2619 | else | |
2620 | { | |
2621 | sprintf (insn_buf, "and.%c #%d,%%%c0", | |
2622 | "bwl"[shift_mode], mask, | |
2623 | mode == QImode ? 'X' : mode == HImode ? 'T' : 'S'); | |
2624 | cc_status.value1 = operands[0]; | |
065bbfe6 | 2625 | cc_status.flags |= CC_NO_CARRY; |
48837e29 DE |
2626 | } |
2627 | output_asm_insn (insn_buf, operands); | |
2628 | return ""; | |
2629 | } | |
b5eaf9ba | 2630 | |
48837e29 DE |
2631 | case SHIFT_SPECIAL: |
2632 | output_asm_insn (assembler, operands); | |
2633 | return ""; | |
48837e29 | 2634 | |
b5eaf9ba KH |
2635 | case SHIFT_LOOP: |
2636 | /* A loop to shift by a "large" constant value. | |
2637 | If we have shift-by-2 insns, use them. */ | |
2638 | if (assembler2 != NULL) | |
2639 | { | |
2640 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, | |
2641 | names_big[REGNO (operands[4])]); | |
2642 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
2643 | output_asm_insn (assembler2, operands); | |
2644 | output_asm_insn ("add #0xff,%X4", operands); | |
2645 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
2646 | if (n % 2) | |
2647 | output_asm_insn (assembler, operands); | |
2648 | } | |
2649 | else | |
2650 | { | |
2651 | fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, | |
2652 | names_big[REGNO (operands[4])]); | |
2653 | fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); | |
2654 | output_asm_insn (assembler, operands); | |
2655 | output_asm_insn ("add #0xff,%X4", operands); | |
2656 | fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); | |
2657 | } | |
51c0c1d7 | 2658 | return ""; |
b5eaf9ba KH |
2659 | |
2660 | default: | |
2661 | abort (); | |
51c0c1d7 | 2662 | } |
07aae5c2 | 2663 | } |
07aae5c2 | 2664 | } |
48837e29 | 2665 | \f |
edd71f0f KH |
2666 | /* A rotation by a non-constant will cause a loop to be generated, in |
2667 | which a rotation by one bit is used. A rotation by a constant, | |
2668 | including the one in the loop, will be taken care of by | |
2669 | emit_a_rotate () at the insn emit time. */ | |
2670 | ||
2671 | int | |
2672 | expand_a_rotate (code, operands) | |
2673 | int code; | |
2674 | rtx operands[]; | |
2675 | { | |
2676 | rtx dst = operands[0]; | |
2677 | rtx src = operands[1]; | |
2678 | rtx rotate_amount = operands[2]; | |
2679 | enum machine_mode mode = GET_MODE (dst); | |
2680 | rtx tmp; | |
2681 | ||
2682 | /* We rotate in place. */ | |
2683 | emit_move_insn (dst, src); | |
2684 | ||
2685 | if (GET_CODE (rotate_amount) != CONST_INT) | |
2686 | { | |
2687 | rtx counter = gen_reg_rtx (QImode); | |
2688 | rtx start_label = gen_label_rtx (); | |
2689 | rtx end_label = gen_label_rtx (); | |
2690 | ||
2691 | /* If the rotate amount is less than or equal to 0, | |
2692 | we go out of the loop. */ | |
2693 | emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), | |
2694 | LE, NULL_RTX, QImode, 0, 0, end_label); | |
2695 | ||
2696 | /* Initialize the loop counter. */ | |
2697 | emit_move_insn (counter, rotate_amount); | |
2698 | ||
2699 | emit_label (start_label); | |
2700 | ||
2701 | /* Rotate by one bit. */ | |
2702 | tmp = gen_rtx (code, mode, dst, GEN_INT (1)); | |
2703 | emit_insn (gen_rtx_SET (mode, dst, tmp)); | |
2704 | ||
2705 | /* Decrement the counter by 1. */ | |
2706 | tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1)); | |
2707 | emit_insn (gen_rtx_SET (VOIDmode, counter, tmp)); | |
2708 | ||
2709 | /* If the loop counter is non-zero, we go back to the beginning | |
2710 | of the loop. */ | |
2711 | emit_cmp_and_jump_insns (counter, GEN_INT (0), | |
2712 | NE, NULL_RTX, QImode, 1, 0, start_label); | |
2713 | ||
2714 | emit_label (end_label); | |
2715 | } | |
2716 | else | |
2717 | { | |
2718 | /* Rotate by AMOUNT bits. */ | |
2719 | tmp = gen_rtx (code, mode, dst, rotate_amount); | |
2720 | emit_insn (gen_rtx_SET (mode, dst, tmp)); | |
2721 | } | |
2722 | ||
2723 | return 1; | |
2724 | } | |
2725 | ||
2726 | /* Emit rotate insns. */ | |
2727 | ||
2728 | const char * | |
2729 | emit_a_rotate (code, operands) | |
2730 | int code; | |
2731 | rtx *operands; | |
2732 | { | |
2733 | rtx dst = operands[0]; | |
2734 | rtx rotate_amount = operands[2]; | |
2735 | enum shift_mode rotate_mode; | |
2736 | enum shift_type rotate_type; | |
2737 | const char *insn_buf; | |
2738 | int bits; | |
2739 | int amount; | |
2740 | enum machine_mode mode = GET_MODE (dst); | |
2741 | ||
2742 | if (GET_CODE (rotate_amount) != CONST_INT) | |
2743 | abort (); | |
2744 | ||
2745 | switch (mode) | |
2746 | { | |
2747 | case QImode: | |
2748 | rotate_mode = QIshift; | |
2749 | break; | |
2750 | case HImode: | |
2751 | rotate_mode = HIshift; | |
2752 | break; | |
2753 | case SImode: | |
2754 | rotate_mode = SIshift; | |
2755 | break; | |
2756 | default: | |
2757 | abort (); | |
2758 | } | |
2759 | ||
2760 | switch (code) | |
2761 | { | |
2762 | case ROTATERT: | |
2763 | rotate_type = SHIFT_ASHIFT; | |
2764 | break; | |
2765 | case ROTATE: | |
2766 | rotate_type = SHIFT_LSHIFTRT; | |
2767 | break; | |
2768 | default: | |
2769 | abort (); | |
2770 | } | |
2771 | ||
2772 | amount = INTVAL (rotate_amount); | |
2773 | ||
2774 | /* Clean up AMOUNT. */ | |
2775 | if (amount < 0) | |
2776 | amount = 0; | |
2777 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
2778 | amount = GET_MODE_BITSIZE (mode); | |
2779 | ||
2780 | /* Determine the faster direction. After this phase, amount will be | |
2781 | at most a half of GET_MODE_BITSIZE (mode). */ | |
2782 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2) | |
2783 | { | |
2784 | /* Flip the direction. */ | |
2785 | amount = GET_MODE_BITSIZE (mode) - amount; | |
2786 | rotate_type = | |
2787 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
2788 | } | |
2789 | ||
2790 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
2791 | boost up the rotation. */ | |
2792 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
2793 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
2794 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
2795 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
2796 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
2797 | { | |
2798 | switch (mode) | |
2799 | { | |
2800 | case HImode: | |
2801 | /* This code works on any family. */ | |
2802 | insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; | |
2803 | output_asm_insn (insn_buf, operands); | |
2804 | break; | |
2805 | ||
2806 | case SImode: | |
2807 | /* This code works on the H8/300H and H8/S. */ | |
2808 | insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; | |
2809 | output_asm_insn (insn_buf, operands); | |
2810 | break; | |
2811 | ||
2812 | default: | |
2813 | abort (); | |
2814 | } | |
2815 | ||
2816 | /* Adjust AMOUNT and flip the direction. */ | |
2817 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
2818 | rotate_type = | |
2819 | (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; | |
2820 | } | |
2821 | ||
2822 | /* Emit rotate insns. */ | |
2823 | for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) | |
2824 | { | |
2825 | if (bits == 2) | |
2826 | insn_buf = rotate_two[rotate_type][rotate_mode]; | |
2827 | else | |
2828 | insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; | |
2c54abce | 2829 | |
edd71f0f KH |
2830 | for (; amount >= bits; amount -= bits) |
2831 | output_asm_insn (insn_buf, operands); | |
2832 | } | |
2833 | ||
2834 | return ""; | |
2835 | } | |
2836 | \f | |
48837e29 | 2837 | /* Fix the operands of a gen_xxx so that it could become a bit |
2c54abce | 2838 | operating insn. */ |
07aae5c2 SC |
2839 | |
2840 | int | |
48837e29 DE |
2841 | fix_bit_operand (operands, what, type) |
2842 | rtx *operands; | |
441d04c6 | 2843 | int what; |
48837e29 | 2844 | enum rtx_code type; |
07aae5c2 | 2845 | { |
abc95ed3 | 2846 | /* The bit_operand predicate accepts any memory during RTL generation, but |
48837e29 DE |
2847 | only 'U' memory afterwards, so if this is a MEM operand, we must force |
2848 | it to be valid for 'U' by reloading the address. */ | |
07aae5c2 | 2849 | |
48837e29 | 2850 | if (GET_CODE (operands[2]) == CONST_INT) |
07aae5c2 | 2851 | { |
48837e29 DE |
2852 | if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what)) |
2853 | { | |
2854 | /* Ok to have a memory dest. */ | |
1a63219b KH |
2855 | if (GET_CODE (operands[0]) == MEM |
2856 | && !EXTRA_CONSTRAINT (operands[0], 'U')) | |
48837e29 | 2857 | { |
c5c76735 JL |
2858 | rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), |
2859 | copy_to_mode_reg (Pmode, | |
2860 | XEXP (operands[0], 0))); | |
c6df88cb | 2861 | MEM_COPY_ATTRIBUTES (mem, operands[0]); |
48837e29 DE |
2862 | operands[0] = mem; |
2863 | } | |
2864 | ||
1a63219b KH |
2865 | if (GET_CODE (operands[1]) == MEM |
2866 | && !EXTRA_CONSTRAINT (operands[1], 'U')) | |
48837e29 | 2867 | { |
c5c76735 JL |
2868 | rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), |
2869 | copy_to_mode_reg (Pmode, | |
2870 | XEXP (operands[1], 0))); | |
c6df88cb | 2871 | MEM_COPY_ATTRIBUTES (mem, operands[0]); |
48837e29 DE |
2872 | operands[1] = mem; |
2873 | } | |
2874 | return 0; | |
2875 | } | |
2876 | } | |
07aae5c2 | 2877 | |
48837e29 | 2878 | /* Dest and src op must be register. */ |
07aae5c2 | 2879 | |
48837e29 DE |
2880 | operands[1] = force_reg (QImode, operands[1]); |
2881 | { | |
2882 | rtx res = gen_reg_rtx (QImode); | |
c5c76735 JL |
2883 | emit_insn (gen_rtx_SET (VOIDmode, res, |
2884 | gen_rtx (type, QImode, operands[1], operands[2]))); | |
2885 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], res)); | |
48837e29 DE |
2886 | } |
2887 | return 1; | |
07aae5c2 | 2888 | } |
f5b65a56 | 2889 | |
f5b65a56 JL |
2890 | /* Return nonzero if FUNC is an interrupt function as specified |
2891 | by the "interrupt" attribute. */ | |
2892 | ||
2893 | static int | |
2894 | h8300_interrupt_function_p (func) | |
2895 | tree func; | |
2896 | { | |
2897 | tree a; | |
2898 | ||
2899 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2900 | return 0; | |
2901 | ||
97c5ec1d | 2902 | a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func)); |
f5b65a56 JL |
2903 | return a != NULL_TREE; |
2904 | } | |
2905 | ||
fabe72bb JL |
2906 | /* Return nonzero if FUNC is an OS_Task function as specified |
2907 | by the "OS_Task" attribute. */ | |
2908 | ||
2909 | static int | |
2910 | h8300_os_task_function_p (func) | |
2911 | tree func; | |
2912 | { | |
2913 | tree a; | |
2914 | ||
2915 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2916 | return 0; | |
2917 | ||
2918 | a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func)); | |
2919 | return a != NULL_TREE; | |
2920 | } | |
2921 | ||
2922 | /* Return nonzero if FUNC is a monitor function as specified | |
2923 | by the "monitor" attribute. */ | |
2924 | ||
2925 | static int | |
2926 | h8300_monitor_function_p (func) | |
2927 | tree func; | |
2928 | { | |
2929 | tree a; | |
2930 | ||
2931 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2932 | return 0; | |
2933 | ||
2934 | a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func)); | |
2935 | return a != NULL_TREE; | |
2936 | } | |
2937 | ||
f5b65a56 JL |
2938 | /* Return nonzero if FUNC is a function that should be called |
2939 | through the function vector. */ | |
2940 | ||
2941 | int | |
2942 | h8300_funcvec_function_p (func) | |
2943 | tree func; | |
2944 | { | |
2945 | tree a; | |
2946 | ||
2947 | if (TREE_CODE (func) != FUNCTION_DECL) | |
2948 | return 0; | |
2949 | ||
97c5ec1d | 2950 | a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func)); |
f5b65a56 JL |
2951 | return a != NULL_TREE; |
2952 | } | |
2953 | ||
887a8bd9 | 2954 | /* Return nonzero if DECL is a variable that's in the eight bit |
15dc331e JL |
2955 | data area. */ |
2956 | ||
2957 | int | |
fabdc32d | 2958 | h8300_eightbit_data_p (decl) |
15dc331e JL |
2959 | tree decl; |
2960 | { | |
2961 | tree a; | |
2962 | ||
2963 | if (TREE_CODE (decl) != VAR_DECL) | |
2964 | return 0; | |
2965 | ||
fabdc32d | 2966 | a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl)); |
15dc331e JL |
2967 | return a != NULL_TREE; |
2968 | } | |
2969 | ||
887a8bd9 JL |
2970 | /* Return nonzero if DECL is a variable that's in the tiny |
2971 | data area. */ | |
2972 | ||
2973 | int | |
2974 | h8300_tiny_data_p (decl) | |
2975 | tree decl; | |
2976 | { | |
2977 | tree a; | |
2978 | ||
2979 | if (TREE_CODE (decl) != VAR_DECL) | |
2980 | return 0; | |
2981 | ||
2982 | a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl)); | |
2983 | return a != NULL_TREE; | |
2984 | } | |
2985 | ||
f5b65a56 JL |
2986 | /* Return nonzero if ATTR is a valid attribute for DECL. |
2987 | ATTRIBUTES are any existing attributes and ARGS are the arguments | |
2988 | supplied with ATTR. | |
2989 | ||
2990 | Supported attributes: | |
2991 | ||
97c5ec1d | 2992 | interrupt_handler: output a prologue and epilogue suitable for an |
f5b65a56 JL |
2993 | interrupt handler. |
2994 | ||
97c5ec1d | 2995 | function_vector: This function should be called through the |
887a8bd9 JL |
2996 | function vector. |
2997 | ||
2998 | eightbit_data: This variable lives in the 8-bit data area and can | |
2999 | be referenced with 8-bit absolute memory addresses. | |
3000 | ||
3001 | tiny_data: This variable lives in the tiny data area and can be | |
3002 | referenced with 16-bit absolute memory references. */ | |
f5b65a56 JL |
3003 | |
3004 | int | |
3005 | h8300_valid_machine_decl_attribute (decl, attributes, attr, args) | |
3006 | tree decl; | |
441d04c6 | 3007 | tree attributes ATTRIBUTE_UNUSED; |
f5b65a56 JL |
3008 | tree attr; |
3009 | tree args; | |
3010 | { | |
3011 | if (args != NULL_TREE) | |
3012 | return 0; | |
3013 | ||
97c5ec1d | 3014 | if (is_attribute_p ("interrupt_handler", attr) |
fabe72bb JL |
3015 | || is_attribute_p ("OS_Task", attr) |
3016 | || is_attribute_p ("monitor", attr) | |
97c5ec1d | 3017 | || is_attribute_p ("function_vector", attr)) |
f5b65a56 | 3018 | return TREE_CODE (decl) == FUNCTION_DECL; |
15dc331e | 3019 | |
fabdc32d | 3020 | if (is_attribute_p ("eightbit_data", attr) |
15dc331e JL |
3021 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
3022 | { | |
3023 | if (DECL_INITIAL (decl) == NULL_TREE) | |
3024 | { | |
3025 | warning ("Only initialized variables can be placed into the 8-bit area."); | |
3026 | return 0; | |
3027 | } | |
887a8bd9 JL |
3028 | DECL_SECTION_NAME (decl) = build_string (7, ".eight"); |
3029 | return 1; | |
3030 | } | |
3031 | ||
3032 | if (is_attribute_p ("tiny_data", attr) | |
3033 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) | |
3034 | { | |
3035 | if (DECL_INITIAL (decl) == NULL_TREE) | |
3036 | { | |
3037 | warning ("Only initialized variables can be placed into the 8-bit area."); | |
3038 | return 0; | |
3039 | } | |
3040 | DECL_SECTION_NAME (decl) = build_string (6, ".tiny"); | |
15dc331e JL |
3041 | return 1; |
3042 | } | |
07e4d94e | 3043 | |
f5b65a56 JL |
3044 | return 0; |
3045 | } | |
3046 | ||
441d04c6 | 3047 | void |
887a8bd9 JL |
3048 | h8300_encode_label (decl) |
3049 | tree decl; | |
3050 | { | |
441d04c6 | 3051 | const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
887a8bd9 JL |
3052 | int len = strlen (str); |
3053 | char *newstr; | |
3054 | ||
4d231df7 | 3055 | newstr = ggc_alloc_string (NULL, len + 1); |
887a8bd9 JL |
3056 | |
3057 | strcpy (newstr + 1, str); | |
f24b26ed | 3058 | *newstr = '&'; |
887a8bd9 JL |
3059 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
3060 | } | |
3061 | ||
441d04c6 | 3062 | const char * |
bd93f126 JL |
3063 | output_simode_bld (bild, log2, operands) |
3064 | int bild; | |
3065 | int log2; | |
3066 | rtx operands[]; | |
3067 | { | |
3068 | /* Clear the destination register. */ | |
a1616dd9 | 3069 | if (TARGET_H8300H || TARGET_H8300S) |
bd93f126 JL |
3070 | output_asm_insn ("sub.l\t%S0,%S0", operands); |
3071 | else | |
3072 | output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); | |
3073 | ||
3074 | /* Get the bit number we want to load. */ | |
3075 | if (log2) | |
3076 | operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2]))); | |
3077 | ||
3078 | /* Now output the bit load or bit inverse load, and store it in | |
3079 | the destination. */ | |
3080 | if (bild) | |
3081 | output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands); | |
3082 | else | |
3083 | output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands); | |
3084 | ||
3085 | /* All done. */ | |
3086 | return ""; | |
3087 | } | |
e6219736 | 3088 | |
9ec36da5 | 3089 | /* Given INSN and its current length LENGTH, return the adjustment |
e6219736 JL |
3090 | (in bytes) to correctly compute INSN's length. |
3091 | ||
3092 | We use this to get the lengths of various memory references correct. */ | |
3093 | ||
441d04c6 | 3094 | int |
e6219736 JL |
3095 | h8300_adjust_insn_length (insn, length) |
3096 | rtx insn; | |
441d04c6 | 3097 | int length ATTRIBUTE_UNUSED; |
e6219736 | 3098 | { |
04b6000c VM |
3099 | rtx pat; |
3100 | ||
47cf37f9 JL |
3101 | /* We must filter these ou before calling get_attr_adjust_length. */ |
3102 | if (GET_CODE (PATTERN (insn)) == USE | |
3103 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
098f2a1e JL |
3104 | || GET_CODE (PATTERN (insn)) == SEQUENCE |
3105 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
3106 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) | |
47cf37f9 JL |
3107 | return 0; |
3108 | ||
04b6000c VM |
3109 | if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO) |
3110 | return 0; | |
3111 | ||
3112 | pat = PATTERN (insn); | |
e6219736 JL |
3113 | |
3114 | /* Adjust length for reg->mem and mem->reg copies. */ | |
3115 | if (GET_CODE (pat) == SET | |
3116 | && (GET_CODE (SET_SRC (pat)) == MEM | |
3117 | || GET_CODE (SET_DEST (pat)) == MEM)) | |
3118 | { | |
3119 | /* This insn might need a length adjustment. */ | |
3120 | rtx addr; | |
3121 | ||
3122 | if (GET_CODE (SET_SRC (pat)) == MEM) | |
3123 | addr = XEXP (SET_SRC (pat), 0); | |
3124 | else | |
3125 | addr = XEXP (SET_DEST (pat), 0); | |
3126 | ||
3127 | /* On the H8/300, only one adjustment is necessary; if the | |
3128 | address mode is register indirect, then this insn is two | |
3129 | bytes shorter than indicated in the machine description. */ | |
3130 | if (TARGET_H8300 && GET_CODE (addr) == REG) | |
3131 | return -2; | |
3132 | ||
a1616dd9 | 3133 | /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than |
e6219736 | 3134 | indicated in the machine description. */ |
a1616dd9 JL |
3135 | if ((TARGET_H8300H || TARGET_H8300S) |
3136 | && GET_CODE (addr) == REG) | |
e6219736 JL |
3137 | return -6; |
3138 | ||
a1616dd9 JL |
3139 | /* On the H8/300H and H8/300S, reg + d, for small displacements is 4 |
3140 | bytes shorter than indicated in the machine description. */ | |
3141 | if ((TARGET_H8300H || TARGET_H8300S) | |
e6219736 JL |
3142 | && GET_CODE (addr) == PLUS |
3143 | && GET_CODE (XEXP (addr, 0)) == REG | |
3144 | && GET_CODE (XEXP (addr, 1)) == CONST_INT | |
3145 | && INTVAL (XEXP (addr, 1)) > -32768 | |
3146 | && INTVAL (XEXP (addr, 1)) < 32767) | |
3147 | return -4; | |
887a8bd9 | 3148 | |
a1616dd9 | 3149 | /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the |
887a8bd9 | 3150 | more general abs:24. */ |
a1616dd9 | 3151 | if ((TARGET_H8300H || TARGET_H8300S) |
887a8bd9 JL |
3152 | && GET_CODE (addr) == SYMBOL_REF |
3153 | && TINY_DATA_NAME_P (XSTR (addr, 0))) | |
3154 | return -2; | |
e6219736 JL |
3155 | } |
3156 | ||
3157 | /* Loading some constants needs adjustment. */ | |
3158 | if (GET_CODE (pat) == SET | |
3159 | && GET_CODE (SET_SRC (pat)) == CONST_INT | |
3160 | && GET_MODE (SET_DEST (pat)) == SImode | |
3161 | && INTVAL (SET_SRC (pat)) != 0) | |
3162 | { | |
64530b82 KH |
3163 | int val = INTVAL (SET_SRC (pat)); |
3164 | ||
e6219736 | 3165 | if (TARGET_H8300 |
64530b82 KH |
3166 | && ((val & 0xffff) == 0 |
3167 | || ((val >> 16) & 0xffff) == 0)) | |
e6219736 JL |
3168 | return -2; |
3169 | ||
a1616dd9 | 3170 | if (TARGET_H8300H || TARGET_H8300S) |
e6219736 | 3171 | { |
e6219736 JL |
3172 | if (val == (val & 0xff) |
3173 | || val == (val & 0xff00)) | |
3174 | return -6; | |
3175 | ||
3176 | if (val == -4 || val == -2 || val == -1) | |
3177 | return -6; | |
3178 | } | |
3179 | } | |
3180 | ||
dd4fd0a0 JL |
3181 | /* Shifts need various adjustments. */ |
3182 | if (GET_CODE (pat) == PARALLEL | |
3183 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
3184 | && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT | |
07e4d94e KH |
3185 | || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT |
3186 | || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT)) | |
dd4fd0a0 JL |
3187 | { |
3188 | rtx src = SET_SRC (XVECEXP (pat, 0, 0)); | |
3189 | enum machine_mode mode = GET_MODE (src); | |
04b6000c | 3190 | int shift; |
dd4fd0a0 JL |
3191 | |
3192 | if (GET_CODE (XEXP (src, 1)) != CONST_INT) | |
3193 | return 0; | |
3194 | ||
04b6000c VM |
3195 | shift = INTVAL (XEXP (src, 1)); |
3196 | /* According to ANSI, negative shift is undefined. It is | |
3197 | considered to be zero in this case (see function | |
07e4d94e | 3198 | emit_a_shift above). */ |
04b6000c VM |
3199 | if (shift < 0) |
3200 | shift = 0; | |
3201 | ||
dd4fd0a0 JL |
3202 | /* QImode shifts by small constants take one insn |
3203 | per shift. So the adjustment is 20 (md length) - | |
3204 | # shifts * 2. */ | |
04b6000c VM |
3205 | if (mode == QImode && shift <= 4) |
3206 | return -(20 - shift * 2); | |
dd4fd0a0 JL |
3207 | |
3208 | /* Similarly for HImode and SImode shifts by | |
a1616dd9 JL |
3209 | small constants on the H8/300H and H8/300S. */ |
3210 | if ((TARGET_H8300H || TARGET_H8300S) | |
04b6000c VM |
3211 | && (mode == HImode || mode == SImode) && shift <= 4) |
3212 | return -(20 - shift * 2); | |
dd4fd0a0 JL |
3213 | |
3214 | /* HImode shifts by small constants for the H8/300. */ | |
04b6000c VM |
3215 | if (mode == HImode && shift <= 4) |
3216 | return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4))); | |
dd4fd0a0 JL |
3217 | |
3218 | /* SImode shifts by small constants for the H8/300. */ | |
04b6000c VM |
3219 | if (mode == SImode && shift <= 2) |
3220 | return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8))); | |
dd4fd0a0 JL |
3221 | |
3222 | /* XXX ??? Could check for more shift/rotate cases here. */ | |
3223 | } | |
07e4d94e | 3224 | |
edd71f0f KH |
3225 | /* Rotations need various adjustments. */ |
3226 | if (GET_CODE (pat) == SET | |
3227 | && (GET_CODE (SET_SRC (pat)) == ROTATE | |
3228 | || GET_CODE (SET_SRC (pat)) == ROTATERT)) | |
3229 | { | |
3230 | rtx src = SET_SRC (pat); | |
3231 | enum machine_mode mode = GET_MODE (src); | |
3232 | int amount; | |
3233 | int states = 0; | |
3234 | ||
3235 | if (GET_CODE (XEXP (src, 1)) != CONST_INT) | |
3236 | return 0; | |
3237 | ||
3238 | amount = INTVAL (XEXP (src, 1)); | |
3239 | ||
3240 | /* Clean up AMOUNT. */ | |
3241 | if (amount < 0) | |
3242 | amount = 0; | |
3243 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) | |
3244 | amount = GET_MODE_BITSIZE (mode); | |
3245 | ||
3246 | /* Determine the faster direction. After this phase, amount | |
3247 | will be at most a half of GET_MODE_BITSIZE (mode). */ | |
3248 | if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2) | |
3249 | /* Flip the direction. */ | |
3250 | amount = GET_MODE_BITSIZE (mode) - amount; | |
3251 | ||
3252 | /* See if a byte swap (in HImode) or a word swap (in SImode) can | |
3253 | boost up the rotation. */ | |
3254 | if ((mode == HImode && TARGET_H8300 && amount >= 5) | |
3255 | || (mode == HImode && TARGET_H8300H && amount >= 6) | |
3256 | || (mode == HImode && TARGET_H8300S && amount == 8) | |
3257 | || (mode == SImode && TARGET_H8300H && amount >= 10) | |
3258 | || (mode == SImode && TARGET_H8300S && amount >= 13)) | |
3259 | { | |
3260 | /* Adjust AMOUNT and flip the direction. */ | |
3261 | amount = GET_MODE_BITSIZE (mode) / 2 - amount; | |
3262 | states += 6; | |
3263 | } | |
3264 | ||
3265 | /* We use 2-bit rotatations on the H8/S. */ | |
3266 | if (TARGET_H8300S) | |
3267 | amount = amount / 2 + amount % 2; | |
3268 | ||
3269 | /* The H8/300 uses three insns to rotate one bit, taking 6 | |
3270 | states. */ | |
3271 | states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); | |
3272 | ||
3273 | return -(20 - states); | |
3274 | } | |
3275 | ||
e6219736 JL |
3276 | return 0; |
3277 | } |