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re PR target/13866 (ICE in extract_insn, at recog.c:2083)
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
aefc5826 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
6d6b0a12 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
48837e29
DE		 4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 6
8aa063fb 7This file is part of GCC.
07aae5c2 8
8aa063fb 9GCC is free software; you can redistribute it and/or modify
07aae5c2
SC		 10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
8aa063fb 14GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
8aa063fb 20along with GCC; see the file COPYING. If not, write to
97aadbb9
RK		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
07aae5c2 23
07aae5c2 24#include "config.h"
c5c76735 25#include "system.h"
4977bab6
ZW		 26#include "coretypes.h"
27#include "tm.h"
07aae5c2 28#include "rtl.h"
bf6bb899 29#include "tree.h"
07aae5c2
SC		 30#include "regs.h"
31#include "hard-reg-set.h"
32#include "real.h"
33#include "insn-config.h"
34#include "conditions.h"
07aae5c2
SC		 35#include "output.h"
36#include "insn-attr.h"
37#include "flags.h"
38#include "recog.h"
39#include "expr.h"
bf6bb899 40#include "function.h"
c15c90bb 41#include "optabs.h"
441d04c6 42#include "toplev.h"
8b97c5f8 43#include "c-pragma.h"
441d04c6 44#include "tm_p.h"
f2a9645f 45#include "ggc.h"
672a6f42
NB		 46#include "target.h"
47#include "target-def.h"
07aae5c2
SC		 48
49/* Forward declarations. */
cb713a8d
KH		 50static const char *byte_reg (rtx, int);
51static int h8300_interrupt_function_p (tree);
3cfa3702 52static int h8300_saveall_function_p (tree);
cb713a8d
KH		 53static int h8300_monitor_function_p (tree);
54static int h8300_os_task_function_p (tree);
81ad9ded 55static void h8300_emit_stack_adjustment (int, unsigned int);
cb713a8d
KH		 56static int round_frame_size (int);
57static unsigned int compute_saved_regs (void);
58static void push (int);
59static void pop (int);
60static const char *cond_string (enum rtx_code);
61static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 62static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
ede75ee8 65#ifndef OBJECT_FORMAT_ELF
cb713a8d 66static void h8300_asm_named_section (const char *, unsigned int);
ede75ee8 67#endif
cb713a8d
KH		 68static int h8300_and_costs (rtx);
69static int h8300_shift_costs (rtx);
f5b65a56 70
48837e29
DE		 71/* CPU_TYPE, says what cpu we're compiling for. */
72int cpu_type;
73
e392d367
KH		 74/* True if a #pragma interrupt has been seen for the current function. */
75static int pragma_interrupt;
07aae5c2
SC		 76
77/* True if a #pragma saveall has been seen for the current function. */
0869f126 78static int pragma_saveall;
07aae5c2 79
441d04c6 80static const char *const names_big[] =
07e4d94e 81{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 82
441d04c6 83static const char *const names_extended[] =
07e4d94e 84{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 85
441d04c6 86static const char *const names_upper_extended[] =
07e4d94e 87{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 88
89/* Points to one of the above. */
90/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 91const char * const *h8_reg_names;
48837e29
DE		 92
93/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 94
441d04c6 95const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4
RH		 96
97/* Machine-specific symbol_ref flags. */
98#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99#define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100#define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
672a6f42 101\f
c4dfc70c
DD		 102/* See below where shifts are handled for explanation of this enum. */
103
104enum shift_alg
105{
106 SHIFT_INLINE,
107 SHIFT_ROT_AND,
108 SHIFT_SPECIAL,
109 SHIFT_LOOP
110};
111
112/* Symbols of the various shifts which can be used as indices. */
113
114enum shift_type
115{
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
117};
118
119/* Macros to keep the shift algorithm tables small. */
120#define INL SHIFT_INLINE
121#define ROT SHIFT_ROT_AND
122#define LOP SHIFT_LOOP
123#define SPC SHIFT_SPECIAL
124
125/* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 128 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 129
130static enum shift_alg shift_alg_qi[3][3][8] = {
131 {
132 /* TARGET_H8300 */
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
137 },
138 {
139 /* TARGET_H8300H */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
144 },
145 {
146 /* TARGET_H8300S */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
151 }
152};
153
154static enum shift_alg shift_alg_hi[3][3][16] = {
155 {
156 /* TARGET_H8300 */
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
165 },
166 {
167 /* TARGET_H8300H */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
176 },
177 {
178 /* TARGET_H8300S */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
187 }
188};
189
190static enum shift_alg shift_alg_si[3][3][32] = {
191 {
192 /* TARGET_H8300 */
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
209 },
210 {
211 /* TARGET_H8300H */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
228 },
229 {
230 /* TARGET_H8300S */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
247 }
248};
249
250#undef INL
251#undef ROT
252#undef LOP
253#undef SPC
254
255enum h8_cpu
256{
257 H8_300,
258 H8_300H,
259 H8_S
260};
261
48837e29
DE		 262/* Initialize various cpu specific globals at start up. */
263
264void
cb713a8d 265h8300_init_once (void)
48837e29 266{
cbf1b2da
KH		 267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
270
48837e29
DE		 271 if (TARGET_H8300)
272 {
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
275 }
276 else
277 {
3db11b5c 278 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
281 }
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 285
286 if (!TARGET_H8300S && TARGET_MAC)
400500c4 287 {
c725bd79 288 error ("-ms2600 is used without -ms");
ec5b0c68 289 target_flags |= MASK_H8300S;
400500c4 290 }
920e86b8 291
39ba95b5
VK		 292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
293 {
92d4b8a0 294 error ("-mn is used without -mh or -ms");
39ba95b5
VK		 295 target_flags ^= MASK_NORMAL_MODE;
296 }
c4dfc70c 297
8bd06267 298 /* Some of the shifts are optimized for speed by default.
c4dfc70c 299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 300 If optimizing for size, change shift_alg for those shift to
c4dfc70c 301 SHIFT_LOOP. */
b6894857 302 if (optimize_size)
c4dfc70c 303 {
b6894857
KH		 304 /* H8/300 */
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 309
b6894857
KH		 310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 312
b6894857
KH		 313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 315
b6894857
KH		 316 /* H8/300H */
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 319
b6894857
KH		 320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 322
b6894857
KH		 323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 327
328 /* H8S */
b6894857 329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 330 }
48837e29 331}
07aae5c2 332
9c188705 333static const char *
cb713a8d 334byte_reg (rtx x, int b)
07aae5c2 335{
9cbcd983
KH		 336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
339 };
07aae5c2 340
500fc80f
KH		 341 if (!REG_P (x))
342 abort ();
343
07aae5c2
SC		 344 return names_small[REGNO (x) * 2 + b];
345}
346
347/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 348
9cbcd983 349#define WORD_REG_USED(regno) \
d60004ee 350 (regno < SP_REG \
9cbcd983
KH		 351 /* No need to save registers if this function will not return. */ \
352 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 353 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983
KH		 354 /* Save any call saved register that was used. */ \
355 || (regs_ever_live[regno] && !call_used_regs[regno]) \
356 /* Save the frame pointer if it was used. */ \
1807b726 357 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
9cbcd983 358 /* Save any register used in an interrupt handler. */ \
e392d367
KH		 359 || (h8300_current_function_interrupt_function_p () \
360 && regs_ever_live[regno]) \
9cbcd983
KH		 361 /* Save call clobbered registers in non-leaf interrupt \
362 handlers. */ \
e392d367 363 || (h8300_current_function_interrupt_function_p () \
9cbcd983 364 && call_used_regs[regno] \
fc80ea73 365 && !current_function_is_leaf)))
07aae5c2
SC		 366
367/* Output assembly language to FILE for the operation OP with operand size
48837e29 368 SIZE to adjust the stack pointer. */
48837e29 369
07aae5c2 370static void
81ad9ded 371h8300_emit_stack_adjustment (int sign, unsigned int size)
07aae5c2 372{
72b1de44
KH		 373 /* If the frame size is 0, we don't have anything to do. */
374 if (size == 0)
f8b58e56 375 return;
72b1de44 376
68ee6df6
KH		 377 /* H8/300 cannot add/subtract a large constant with a single
378 instruction. If a temporary register is available, load the
379 constant to it and then do the addition. */
380 if (TARGET_H8300
381 && size > 4
382 && !h8300_current_function_interrupt_function_p ()
383 && !(current_function_needs_context && sign < 0))
f8f26adc 384 {
68ee6df6 385 rtx r3 = gen_rtx_REG (Pmode, 3);
72b1de44
KH		 386 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
387 emit_insn (gen_addhi3 (stack_pointer_rtx,
388 stack_pointer_rtx, r3));
7b3d4613
KH		 389 }
390 else
391 {
68ee6df6
KH		 392 /* The stack adjustment made here is further optimized by the
393 splitter. In case of H8/300, the splitter always splits the
394 addition emitted here to make the adjustment
395 interrupt-safe. */
72b1de44
KH		 396 if (Pmode == HImode)
397 emit_insn (gen_addhi3 (stack_pointer_rtx,
398 stack_pointer_rtx, GEN_INT (sign * size)));
399 else
400 emit_insn (gen_addsi3 (stack_pointer_rtx,
401 stack_pointer_rtx, GEN_INT (sign * size)));
07aae5c2
SC		 402 }
403}
404
8682223f
KH		 405/* Round up frame size SIZE. */
406
407static int
cb713a8d 408round_frame_size (int size)
8682223f 409{
489eda65
KH		 410 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
411 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 412}
413
414/* Compute which registers to push/pop.
415 Return a bit vector of registers. */
416
417static unsigned int
cb713a8d 418compute_saved_regs (void)
8682223f
KH		 419{
420 unsigned int saved_regs = 0;
421 int regno;
422
423 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 424 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 425 {
426 if (WORD_REG_USED (regno))
427 saved_regs |= 1 << regno;
428 }
429
430 /* Don't push/pop the frame pointer as it is treated separately. */
431 if (frame_pointer_needed)
1807b726 432 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 433
434 return saved_regs;
435}
436
68ee6df6 437/* Emit an insn to push register RN. */
8682223f
KH		 438
439static void
cb713a8d 440push (int rn)
8682223f 441{
68ee6df6
KH		 442 rtx reg = gen_rtx_REG (word_mode, rn);
443 rtx x;
444
513f31eb 445 if (TARGET_H8300)
68ee6df6 446 x = gen_push_h8300 (reg);
f24f0897 447 else if (!TARGET_NORMAL_MODE)
32da7865 448 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 449 else
450 x = gen_push_h8300hs_normal (reg);
68ee6df6
KH		 451 x = emit_insn (x);
452 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
8682223f
KH		 453}
454
68ee6df6 455/* Emit an insn to pop register RN. */
8682223f
KH		 456
457static void
cb713a8d 458pop (int rn)
8682223f 459{
68ee6df6
KH		 460 rtx reg = gen_rtx_REG (word_mode, rn);
461 rtx x;
462
513f31eb 463 if (TARGET_H8300)
68ee6df6 464 x = gen_pop_h8300 (reg);
f24f0897 465 else if (!TARGET_NORMAL_MODE)
32da7865 466 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 467 else
468 x = gen_pop_h8300hs_normal (reg);
68ee6df6
KH		 469 x = emit_insn (x);
470 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
8682223f 471}
07aae5c2 472
f0b6f9a6 473/* This is what the stack looks like after the prolog of
07aae5c2
SC		 474 a function with a frame has been set up:
475
48837e29
DE		 476 <args>
477 PC
478 FP <- fp
479 <locals>
8bd06267 480 <saved registers> <- sp
07aae5c2
SC		 481
482 This is what the stack looks like after the prolog of
483 a function which doesn't have a frame:
484
48837e29
DE		 485 <args>
486 PC
487 <locals>
8bd06267 488 <saved registers> <- sp
07aae5c2
SC		 489*/
490
68ee6df6 491/* Generate RTL code for the function prologue. */
8682223f 492
68ee6df6 493void
cb713a8d 494h8300_expand_prologue (void)
07aae5c2 495{
e651d484 496 int regno;
8682223f 497 int saved_regs;
cda4bd43 498 int n_regs;
07aae5c2 499
fabe72bb
JL		 500 /* If the current function has the OS_Task attribute set, then
501 we have a naked prologue. */
502 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 503 return;
fabe72bb
JL		 504
505 if (h8300_monitor_function_p (current_function_decl))
68ee6df6
KH		 506 /* My understanding of monitor functions is they act just like
507 interrupt functions, except the prologue must mask
508 interrupts. */
509 emit_insn (gen_monitor_prologue ());
fabe72bb 510
48837e29
DE		 511 if (frame_pointer_needed)
512 {
07e4d94e 513 /* Push fp. */
1807b726 514 push (HARD_FRAME_POINTER_REGNUM);
6552458a 515 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
a1616dd9 516 }
48837e29 517
8682223f
KH		 518 /* Push the rest of the registers in ascending order. */
519 saved_regs = compute_saved_regs ();
e651d484 520 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 521 {
cda4bd43 522 n_regs = 1;
8682223f 523 if (saved_regs & (1 << regno))
a1616dd9
JL		 524 {
525 if (TARGET_H8300S)
526 {
cda4bd43
KH		 527 /* See how many registers we can push at the same time. */
528 if ((regno == 0 || regno == 4)
8682223f 529 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 530 n_regs = 4;
531
532 else if ((regno == 0 || regno == 4)
8682223f 533 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 534 n_regs = 3;
535
536 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
8682223f 537 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 538 n_regs = 2;
a1616dd9 539 }
cda4bd43 540
e8a68017
KH		 541 switch (n_regs)
542 {
543 case 1:
68ee6df6 544 push (regno);
e8a68017
KH		 545 break;
546 case 2:
68ee6df6
KH		 547 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
548 gen_rtx_REG (SImode, regno + 1)));
e8a68017
KH		 549 break;
550 case 3:
68ee6df6
KH		 551 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
552 gen_rtx_REG (SImode, regno + 1),
553 gen_rtx_REG (SImode, regno + 2)));
e8a68017
KH		 554 break;
555 case 4:
68ee6df6
KH		 556 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
557 gen_rtx_REG (SImode, regno + 1),
558 gen_rtx_REG (SImode, regno + 2),
559 gen_rtx_REG (SImode, regno + 3)));
e8a68017
KH		 560 break;
561 default:
562 abort ();
563 }
07aae5c2
SC		 564 }
565 }
1807b726
KH		 566
567 /* Leave room for locals. */
568 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
07aae5c2
SC		 569}
570
68ee6df6 571int
cb713a8d 572h8300_can_use_return_insn_p (void)
68ee6df6
KH		 573{
574 return (reload_completed
575 && !frame_pointer_needed
576 && get_frame_size () == 0
577 && compute_saved_regs () == 0);
578}
07aae5c2 579
68ee6df6
KH		 580/* Generate RTL code for the function epilogue. */
581
582void
cb713a8d 583h8300_expand_epilogue (void)
07aae5c2 584{
e651d484 585 int regno;
8682223f 586 int saved_regs;
cda4bd43 587 int n_regs;
07aae5c2 588
e392d367 589 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 590 /* OS_Task epilogues are nearly naked -- they just have an
591 rts instruction. */
592 return;
07aae5c2 593
1807b726
KH		 594 /* Deallocate locals. */
595 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
596
8682223f
KH		 597 /* Pop the saved registers in descending order. */
598 saved_regs = compute_saved_regs ();
e651d484 599 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 600 {
cda4bd43 601 n_regs = 1;
8682223f 602 if (saved_regs & (1 << regno))
07aae5c2 603 {
a1616dd9
JL		 604 if (TARGET_H8300S)
605 {
cda4bd43
KH		 606 /* See how many registers we can pop at the same time. */
607 if ((regno == 7 || regno == 3)
8682223f 608 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
cda4bd43
KH		 609 n_regs = 4;
610
611 else if ((regno == 6 || regno == 2)
8682223f 612 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
cda4bd43
KH		 613 n_regs = 3;
614
615 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
8682223f 616 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
cda4bd43 617 n_regs = 2;
a1616dd9 618 }
cda4bd43 619
e8a68017
KH		 620 switch (n_regs)
621 {
622 case 1:
68ee6df6 623 pop (regno);
e8a68017
KH		 624 break;
625 case 2:
68ee6df6
KH		 626 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
627 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 628 break;
629 case 3:
68ee6df6
KH		 630 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
631 gen_rtx_REG (SImode, regno - 1),
632 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 633 break;
634 case 4:
68ee6df6
KH		 635 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
636 gen_rtx_REG (SImode, regno - 2),
637 gen_rtx_REG (SImode, regno - 1),
638 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 639 break;
640 default:
641 abort ();
642 }
07aae5c2 643 }
07aae5c2 644 }
48837e29 645
07e4d94e 646 /* Pop frame pointer if we had one. */
a1616dd9 647 if (frame_pointer_needed)
1807b726 648 pop (HARD_FRAME_POINTER_REGNUM);
68ee6df6 649}
a1616dd9 650
e392d367
KH		 651/* Return nonzero if the current function is an interrupt
652 function. */
653
654int
cb713a8d 655h8300_current_function_interrupt_function_p (void)
e392d367
KH		 656{
657 return (h8300_interrupt_function_p (current_function_decl)
658 || h8300_monitor_function_p (current_function_decl));
659}
660
48837e29
DE		 661/* Output assembly code for the start of the file. */
662
1bc7c5b6
ZW		 663static void
664h8300_file_start (void)
48837e29 665{
1bc7c5b6 666 default_file_start ();
8bd06267 667
48837e29 668 if (TARGET_H8300H)
1bc7c5b6 669 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
a1616dd9 670 else if (TARGET_H8300S)
1bc7c5b6 671 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
48837e29
DE		 672}
673
674/* Output assembly language code for the end of file. */
675
a5fe455b 676static void
cb713a8d 677h8300_file_end (void)
48837e29 678{
a5fe455b 679 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 680}
681\f
68560db3 682/* Return true if OP is a valid source operand for an integer move
07aae5c2 683 instruction. */
48837e29 684
07aae5c2 685int
cb713a8d 686general_operand_src (rtx op, enum machine_mode mode)
07aae5c2 687{
ff6e1a2f
KH		 688 if (GET_MODE (op) == mode
689 && GET_CODE (op) == MEM
690 && GET_CODE (XEXP (op, 0)) == POST_INC)
48837e29 691 return 1;
07aae5c2
SC		 692 return general_operand (op, mode);
693}
694
695/* Return true if OP is a valid destination operand for an integer move
5660465a 696 instruction. */
48837e29 697
07aae5c2 698int
cb713a8d 699general_operand_dst (rtx op, enum machine_mode mode)
07aae5c2 700{
ff6e1a2f
KH		 701 if (GET_MODE (op) == mode
702 && GET_CODE (op) == MEM
703 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
48837e29 704 return 1;
07aae5c2
SC		 705 return general_operand (op, mode);
706}
48837e29 707
4d4d89e2
KH		 708/* Return true if OP is a constant that contains only one 1 in its
709 binary representation. */
48837e29
DE		 710
711int
cb713a8d 712single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29 713{
4d4d89e2
KH		 714 if (GET_CODE (operand) == CONST_INT)
715 {
716 /* We really need to do this masking because 0x80 in QImode is
717 represented as -128 for example. */
ef378bbe 718 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
4d4d89e2
KH		 719 return 1;
720 }
721
722 return 0;
723}
724
725/* Return true if OP is a constant that contains only one 0 in its
726 binary representation. */
727
728int
cb713a8d 729single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
4d4d89e2
KH		 730{
731 if (GET_CODE (operand) == CONST_INT)
732 {
733 /* We really need to do this masking because 0x80 in QImode is
734 represented as -128 for example. */
ef378bbe 735 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
4d4d89e2
KH		 736 return 1;
737 }
738
739 return 0;
48837e29
DE		 740}
741
48837e29
DE		 742/* Return true if OP is a valid call operand. */
743
744int
cb713a8d 745call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 746{
747 if (GET_CODE (op) == MEM)
748 {
749 rtx inside = XEXP (op, 0);
750 if (register_operand (inside, Pmode))
751 return 1;
752 if (CONSTANT_ADDRESS_P (inside))
753 return 1;
754 }
755 return 0;
756}
757
22c9a795 758/* Return 1 if an addition/subtraction of a constant integer can be
997e5af8 759 transformed into two consecutive adds/subs that are faster than the
22c9a795 760 straightforward way. Otherwise, return 0. */
997e5af8 761
3b7d443c 762int
cb713a8d 763two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
3b7d443c
JL		 764{
765 if (GET_CODE (op) == CONST_INT)
766 {
009ac3d3 767 HOST_WIDE_INT value = INTVAL (op);
3b7d443c 768
997e5af8
KH		 769 /* Force VALUE to be positive so that we do not have to consider
770 the negative case. */
771 if (value < 0)
772 value = -value;
009ac3d3
RH		 773 if (TARGET_H8300H || TARGET_H8300S)
774 {
997e5af8
KH		 775 /* A constant addition/subtraction takes 2 states in QImode,
776 4 states in HImode, and 6 states in SImode. Thus, the
777 only case we can win is when SImode is used, in which
c59ff527 778 case, two adds/subs are used, taking 4 states. */
997e5af8
KH		 779 if (mode == SImode
780 && (value == 2 + 1
781 || value == 4 + 1
782 || value == 4 + 2
783 || value == 4 + 4))
22c9a795 784 return 1;
009ac3d3
RH		 785 }
786 else
787 {
ae19f5ef
KH		 788 /* We do not profit directly by splitting addition or
789 subtraction of 3 and 4. However, since these are
790 implemented as a sequence of adds or subs, they do not
791 clobber (cc0) unlike a sequence of add.b and add.x. */
792 if (mode == HImode
997e5af8
KH		 793 && (value == 2 + 1
794 || value == 2 + 2))
009ac3d3
RH		 795 return 1;
796 }
797 }
e6219736 798
e6219736
JL		 799 return 0;
800}
801
3cee1a78
KH		 802/* Split an add of a small constant into two adds/subs insns.
803
804 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
805 instead of adds/subs. */
009ac3d3
RH		 806
807void
cb713a8d 808split_adds_subs (enum machine_mode mode, rtx *operands)
3b7d443c 809{
009ac3d3
RH		 810 HOST_WIDE_INT val = INTVAL (operands[1]);
811 rtx reg = operands[0];
9492393e
KH		 812 HOST_WIDE_INT sign = 1;
813 HOST_WIDE_INT amount;
590734b6 814 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 815
9492393e
KH		 816 /* Force VAL to be positive so that we do not have to consider the
817 sign. */
818 if (val < 0)
3b7d443c 819 {
9492393e
KH		 820 val = -val;
821 sign = -1;
822 }
3b7d443c 823
3cee1a78
KH		 824 switch (mode)
825 {
826 case HImode:
590734b6 827 gen_add = gen_addhi3;
3cee1a78
KH		 828 break;
829
830 case SImode:
590734b6 831 gen_add = gen_addsi3;
3cee1a78
KH		 832 break;
833
834 default:
835 abort ();
836 }
837
9492393e
KH		 838 /* Try different amounts in descending order. */
839 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
840 amount > 0;
841 amount /= 2)
842 {
1a63219b 843 for (; val >= amount; val -= amount)
590734b6 844 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 845 }
846
9492393e 847 return;
3b7d443c
JL		 848}
849
f5b65a56
JL		 850/* Return true if OP is a valid call operand, and OP represents
851 an operand for a small call (4 bytes instead of 6 bytes). */
852
853int
cb713a8d 854small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
f5b65a56
JL		 855{
856 if (GET_CODE (op) == MEM)
857 {
858 rtx inside = XEXP (op, 0);
859
860 /* Register indirect is a small call. */
861 if (register_operand (inside, Pmode))
862 return 1;
863
dc66a1c4 864 /* A call through the function vector is a small call too. */
f5b65a56 865 if (GET_CODE (inside) == SYMBOL_REF
dc66a1c4 866 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
f5b65a56
JL		 867 return 1;
868 }
869 /* Otherwise it's a large call. */
870 return 0;
871}
872
48837e29
DE		 873/* Return true if OP is a valid jump operand. */
874
875int
cb713a8d 876jump_address_operand (rtx op, enum machine_mode mode)
48837e29
DE		 877{
878 if (GET_CODE (op) == REG)
879 return mode == Pmode;
880
881 if (GET_CODE (op) == MEM)
882 {
883 rtx inside = XEXP (op, 0);
884 if (register_operand (inside, Pmode))
885 return 1;
886 if (CONSTANT_ADDRESS_P (inside))
887 return 1;
888 }
889 return 0;
890}
891
43a88a8c 892/* Recognize valid operands for bit-field instructions. */
48837e29 893
48837e29 894int
cb713a8d 895bit_operand (rtx op, enum machine_mode mode)
48837e29 896{
f411c849 897 /* We can accept any general operand, except that MEM operands must
48837e29
DE		 898 be limited to those that use addresses valid for the 'U' constraint. */
899 if (!general_operand (op, mode))
900 return 0;
901
902 /* Accept any mem during RTL generation. Otherwise, the code that does
903 insv and extzv will think that we can not handle memory. However,
904 to avoid reload problems, we only accept 'U' MEM operands after RTL
905 generation. This means that any named pattern which uses this predicate
906 must force its operands to match 'U' before emitting RTL. */
907
908 if (GET_CODE (op) == REG)
909 return 1;
910 if (GET_CODE (op) == SUBREG)
911 return 1;
6620997b
KH		 912 return (GET_CODE (op) == MEM
913 && EXTRA_CONSTRAINT (op, 'U'));
48837e29
DE		 914}
915
887a8bd9 916int
cb713a8d 917bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
887a8bd9
JL		 918{
919 return (GET_CODE (op) == MEM
920 && EXTRA_CONSTRAINT (op, 'U'));
921}
922
07aae5c2 923/* Handle machine specific pragmas for compatibility with existing
48837e29 924 compilers for the H8/300.
07aae5c2 925
f411c849 926 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 927 restores all the registers on function entry.
48837e29 928
07aae5c2
SC		 929 pragma interrupt saves and restores all registers, and exits with
930 an rte instruction rather than an rts. A pointer to a function
931 with this attribute may be safely used in an interrupt vector. */
48837e29 932
8b97c5f8 933void
cb713a8d 934h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 935{
e392d367 936 pragma_interrupt = 1;
8b97c5f8 937}
05a81fe5 938
8b97c5f8 939void
cb713a8d 940h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 941{
942 pragma_saveall = 1;
07aae5c2 943}
8b97c5f8 944
64bead4c
KH		 945/* If the next function argument with MODE and TYPE is to be passed in
946 a register, return a reg RTX for the hard register in which to pass
947 the argument. CUM represents the state after the last argument.
948 If the argument is to be pushed, NULL_RTX is returned. */
48837e29 949
07aae5c2 950rtx
cb713a8d
KH		 951function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
952 tree type, int named)
07aae5c2 953{
0ea6f6a0
KH		 954 static const char *const hand_list[] = {
955 "__main",
956 "__cmpsi2",
957 "__divhi3",
958 "__modhi3",
959 "__udivhi3",
960 "__umodhi3",
961 "__divsi3",
962 "__modsi3",
963 "__udivsi3",
964 "__umodsi3",
965 "__mulhi3",
966 "__mulsi3",
967 "__reg_memcpy",
968 "__reg_memset",
969 "__ucmpsi2",
970 0,
971 };
972
7192cbf1 973 rtx result = NULL_RTX;
441d04c6 974 const char *fname;
48837e29
DE		 975 int regpass = 0;
976
dd07092e
JL		 977 /* Never pass unnamed arguments in registers. */
978 if (!named)
7192cbf1 979 return NULL_RTX;
dd07092e 980
48837e29
DE		 981 /* Pass 3 regs worth of data in regs when user asked on the command line. */
982 if (TARGET_QUICKCALL)
983 regpass = 3;
984
985 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 986 if (cum->libcall)
987 {
441d04c6 988 const char * const *p;
48837e29
DE		 989
990 fname = XSTR (cum->libcall, 0);
991
992 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 993 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
994 ;
07aae5c2 995
48837e29
DE		 996 if (*p)
997 regpass = 4;
998 }
999
1000 if (regpass)
1001 {
1002 int size;
1003
1004 if (mode == BLKmode)
1005 size = int_size_in_bytes (type);
1006 else
1007 size = GET_MODE_SIZE (mode);
1008
15e0e275
KH		 1009 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1010 && cum->nbytes / UNITS_PER_WORD <= 3)
1011 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1012 }
07aae5c2 1013
48837e29
DE		 1014 return result;
1015}
1016\f
3c50106f 1017static int
cb713a8d 1018h8300_and_costs (rtx x)
73cc75e9
KH		 1019{
1020 rtx operands[4];
1021
1022 if (GET_MODE (x) == QImode)
1023 return 1;
1024
1025 if (GET_MODE (x) != HImode
1026 && GET_MODE (x) != SImode)
1027 return 100;
1028
1029 operands[0] = NULL;
1030 operands[1] = NULL;
1031 operands[2] = XEXP (x, 1);
1032 operands[3] = x;
4f4ebda3 1033 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1034}
1035
3c50106f 1036static int
cb713a8d 1037h8300_shift_costs (rtx x)
ae557002
KH		 1038{
1039 rtx operands[4];
1040
1041 if (GET_MODE (x) != QImode
1042 && GET_MODE (x) != HImode
1043 && GET_MODE (x) != SImode)
1044 return 100;
1045
1046 operands[0] = NULL;
1047 operands[1] = NULL;
1048 operands[2] = XEXP (x, 1);
1049 operands[3] = x;
4f4ebda3 1050 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1051}
3c50106f
RH		 1052
1053static bool
cb713a8d 1054h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f
RH		 1055{
1056 switch (code)
1057 {
08dca707
KH		 1058 case CONST_INT:
1059 {
1060 HOST_WIDE_INT n = INTVAL (x);
1061
1062 if (-4 <= n || n <= 4)
1063 {
1064 switch ((int) n)
1065 {
1066 case 0:
1067 *total = 0;
1068 return true;
1069 case 1:
1070 case 2:
1071 case -1:
1072 case -2:
1073 *total = 0 + (outer_code == SET);
1074 return true;
1075 case 4:
1076 case -4:
1077 if (TARGET_H8300H || TARGET_H8300S)
1078 *total = 0 + (outer_code == SET);
1079 else
1080 *total = 1;
1081 return true;
1082 }
1083 }
1084 *total = 1;
1085 return true;
1086 }
1087
1088 case CONST:
1089 case LABEL_REF:
1090 case SYMBOL_REF:
1091 *total = 3;
1092 return true;
1093
1094 case CONST_DOUBLE:
1095 *total = 20;
1096 return true;
1097
3c50106f
RH		 1098 case AND:
1099 *total = COSTS_N_INSNS (h8300_and_costs (x));
1100 return true;
1101
1102 /* We say that MOD and DIV are so expensive because otherwise we'll
1103 generate some really horrible code for division of a power of two. */
1104 case MOD:
1105 case DIV:
1106 *total = 60;
1107 return true;
1108
1109 case MULT:
1110 *total = 20;
1111 return true;
1112
1113 case ASHIFT:
1114 case ASHIFTRT:
1115 case LSHIFTRT:
1116 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1117 return true;
1118
1119 case ROTATE:
1120 case ROTATERT:
1121 if (GET_MODE (x) == HImode)
1122 *total = 2;
1123 else
1124 *total = 8;
1125 return true;
1126
1127 default:
08dca707 1128 *total = 4;
3c50106f
RH		 1129 return true;
1130 }
1131}
48837e29 1132\f
07aae5c2
SC		 1133/* Documentation for the machine specific operand escapes:
1134
48837e29
DE		 1135 'E' like s but negative.
1136 'F' like t but negative.
1137 'G' constant just the negative
15dc331e
JL		 1138 'R' print operand as a byte:8 address if appropriate, else fall back to
1139 'X' handling.
48837e29 1140 'S' print operand as a long word
07aae5c2 1141 'T' print operand as a word
48837e29
DE		 1142 'V' find the set bit, and print its number.
1143 'W' find the clear bit, and print its number.
1144 'X' print operand as a byte
07aae5c2 1145 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1146 If this operand isn't a register, fall back to 'R' handling.
48837e29 1147 'Z' print int & 7.
b059c02a 1148 'c' print the opcode corresponding to rtl
48837e29
DE		 1149 'e' first word of 32 bit value - if reg, then least reg. if mem
1150 then least. if const then most sig word
1151 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1152 then +2. if const then least sig word
07aae5c2
SC		 1153 'j' print operand as condition code.
1154 'k' print operand as reverse condition code.
48837e29
DE		 1155 's' print as low byte of 16 bit value
1156 't' print as high byte of 16 bit value
1157 'w' print as low byte of 32 bit value
1158 'x' print as 2nd byte of 32 bit value
1159 'y' print as 3rd byte of 32 bit value
1160 'z' print as msb of 32 bit value
1161*/
07aae5c2
SC		 1162
1163/* Return assembly language string which identifies a comparison type. */
1164
441d04c6 1165static const char *
cb713a8d 1166cond_string (enum rtx_code code)
07aae5c2
SC		 1167{
1168 switch (code)
1169 {
1170 case NE:
1171 return "ne";
1172 case EQ:
1173 return "eq";
1174 case GE:
1175 return "ge";
1176 case GT:
1177 return "gt";
1178 case LE:
1179 return "le";
1180 case LT:
1181 return "lt";
1182 case GEU:
1183 return "hs";
1184 case GTU:
1185 return "hi";
1186 case LEU:
1187 return "ls";
1188 case LTU:
1189 return "lo";
1190 default:
1191 abort ();
1192 }
1193}
1194
1195/* Print operand X using operand code CODE to assembly language output file
1196 FILE. */
1197
1198void
cb713a8d 1199print_operand (FILE *file, rtx x, int code)
07aae5c2 1200{
269c14e1 1201 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1202 static int bitint;
1203
1204 switch (code)
1205 {
48837e29
DE		 1206 case 'E':
1207 switch (GET_CODE (x))
1208 {
1209 case REG:
1210 fprintf (file, "%sl", names_big[REGNO (x)]);
1211 break;
1212 case CONST_INT:
b47900aa 1213 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1214 break;
1215 default:
1216 abort ();
1217 }
1218 break;
1219 case 'F':
1220 switch (GET_CODE (x))
1221 {
1222 case REG:
1223 fprintf (file, "%sh", names_big[REGNO (x)]);
1224 break;
1225 case CONST_INT:
b47900aa 1226 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1227 break;
1228 default:
1229 abort ();
1230 }
1231 break;
07aae5c2
SC		 1232 case 'G':
1233 if (GET_CODE (x) != CONST_INT)
1234 abort ();
b47900aa 1235 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1236 break;
48837e29
DE		 1237 case 'S':
1238 if (GET_CODE (x) == REG)
1239 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1240 else
48837e29 1241 goto def;
07aae5c2 1242 break;
48837e29
DE		 1243 case 'T':
1244 if (GET_CODE (x) == REG)
1245 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1246 else
48837e29 1247 goto def;
07aae5c2 1248 break;
48837e29 1249 case 'V':
4d4d89e2 1250 bitint = exact_log2 (INTVAL (x) & 0xff);
48837e29 1251 if (bitint == -1)
07aae5c2 1252 abort ();
4d4d89e2 1253 fprintf (file, "#%d", bitint);
07aae5c2 1254 break;
48837e29 1255 case 'W':
07aae5c2
SC		 1256 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1257 if (bitint == -1)
1258 abort ();
4d4d89e2 1259 fprintf (file, "#%d", bitint);
07aae5c2 1260 break;
15dc331e 1261 case 'R':
48837e29
DE		 1262 case 'X':
1263 if (GET_CODE (x) == REG)
1264 fprintf (file, "%s", byte_reg (x, 0));
1265 else
1266 goto def;
1267 break;
1268 case 'Y':
07aae5c2
SC		 1269 if (bitint == -1)
1270 abort ();
48837e29
DE		 1271 if (GET_CODE (x) == REG)
1272 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1273 else
15dc331e 1274 print_operand (file, x, 'R');
48837e29
DE		 1275 bitint = -1;
1276 break;
1277 case 'Z':
1278 bitint = INTVAL (x);
07aae5c2
SC		 1279 fprintf (file, "#%d", bitint & 7);
1280 break;
b059c02a
KH		 1281 case 'c':
1282 switch (GET_CODE (x))
1283 {
1284 case IOR:
1285 fprintf (file, "or");
1286 break;
1287 case XOR:
1288 fprintf (file, "xor");
1289 break;
5abfd1af
KH		 1290 case AND:
1291 fprintf (file, "and");
1292 break;
b059c02a
KH		 1293 default:
1294 break;
1295 }
1296 break;
07aae5c2
SC		 1297 case 'e':
1298 switch (GET_CODE (x))
1299 {
1300 case REG:
48837e29
DE		 1301 if (TARGET_H8300)
1302 fprintf (file, "%s", names_big[REGNO (x)]);
1303 else
1304 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1305 break;
1306 case MEM:
07aae5c2
SC		 1307 print_operand (file, x, 0);
1308 break;
1309 case CONST_INT:
b47900aa 1310 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1311 break;
808fbfac
JL		 1312 case CONST_DOUBLE:
1313 {
1314 long val;
1315 REAL_VALUE_TYPE rv;
1316 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1317 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1318 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1319 break;
1320 }
07aae5c2
SC		 1321 default:
1322 abort ();
1323 break;
1324 }
1325 break;
07aae5c2
SC		 1326 case 'f':
1327 switch (GET_CODE (x))
1328 {
1329 case REG:
48837e29
DE		 1330 if (TARGET_H8300)
1331 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1332 else
1333 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1334 break;
07aae5c2 1335 case MEM:
b72f00af 1336 x = adjust_address (x, HImode, 2);
07aae5c2
SC		 1337 print_operand (file, x, 0);
1338 break;
07aae5c2 1339 case CONST_INT:
b47900aa 1340 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1341 break;
808fbfac
JL		 1342 case CONST_DOUBLE:
1343 {
1344 long val;
1345 REAL_VALUE_TYPE rv;
1346 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1347 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1348 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1349 break;
1350 }
07aae5c2
SC		 1351 default:
1352 abort ();
1353 }
1354 break;
07aae5c2 1355 case 'j':
761c70aa 1356 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1357 break;
07aae5c2 1358 case 'k':
761c70aa 1359 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1360 break;
48837e29
DE		 1361 case 's':
1362 if (GET_CODE (x) == CONST_INT)
b47900aa 1363 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1364 else
1365 fprintf (file, "%s", byte_reg (x, 0));
1366 break;
1367 case 't':
1368 if (GET_CODE (x) == CONST_INT)
b47900aa 1369 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1370 else
1371 fprintf (file, "%s", byte_reg (x, 1));
1372 break;
48837e29
DE		 1373 case 'w':
1374 if (GET_CODE (x) == CONST_INT)
b47900aa 1375 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1376 else
a1616dd9
JL		 1377 fprintf (file, "%s",
1378 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1379 break;
1380 case 'x':
1381 if (GET_CODE (x) == CONST_INT)
b47900aa 1382 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1383 else
a1616dd9
JL		 1384 fprintf (file, "%s",
1385 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1386 break;
1387 case 'y':
1388 if (GET_CODE (x) == CONST_INT)
b47900aa 1389 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1390 else
1391 fprintf (file, "%s", byte_reg (x, 0));
1392 break;
1393 case 'z':
1394 if (GET_CODE (x) == CONST_INT)
b47900aa 1395 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1396 else
1397 fprintf (file, "%s", byte_reg (x, 1));
1398 break;
1399
07aae5c2 1400 default:
48837e29 1401 def:
07aae5c2
SC		 1402 switch (GET_CODE (x))
1403 {
1404 case REG:
48837e29
DE		 1405 switch (GET_MODE (x))
1406 {
1407 case QImode:
269c14e1 1408#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1409 fprintf (file, "%s", byte_reg (x, 0));
1410#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1411 fprintf (file, "%s", names_big[REGNO (x)]);
1412#endif
1413 break;
1414 case HImode:
1415 fprintf (file, "%s", names_big[REGNO (x)]);
1416 break;
1417 case SImode:
8977e8a7 1418 case SFmode:
48837e29
DE		 1419 fprintf (file, "%s", names_extended[REGNO (x)]);
1420 break;
1421 default:
1422 abort ();
1423 }
07aae5c2
SC		 1424 break;
1425
1426 case MEM:
87e4ee91
KH		 1427 {
1428 rtx addr = XEXP (x, 0);
1429
1430 fprintf (file, "@");
1431 output_address (addr);
1432
bc8db8a1
KH		 1433 /* We fall back from smaller addressing to larger
1434 addressing in various ways depending on CODE. */
1435 switch (code)
1436 {
1437 case 'R':
1438 /* Used for mov.b and bit operations. */
7c143ed2 1439 if (h8300_eightbit_constant_address_p (addr))
bc8db8a1
KH		 1440 {
1441 fprintf (file, ":8");
1442 break;
1443 }
1444
1445 /* Fall through. We should not get here if we are
1446 processing bit operations on H8/300 or H8/300H
1447 because 'U' constraint does not allow bit
1448 operations on the tiny area on these machines. */
1449
1450 case 'T':
1451 case 'S':
1452 /* Used for mov.w and mov.l. */
56b8e164 1453 if (h8300_tiny_constant_address_p (addr))
bc8db8a1
KH		 1454 fprintf (file, ":16");
1455 break;
1456 default:
1457 break;
1458 }
87e4ee91 1459 }
07aae5c2
SC		 1460 break;
1461
1462 case CONST_INT:
1463 case SYMBOL_REF:
1464 case CONST:
1465 case LABEL_REF:
1466 fprintf (file, "#");
1467 print_operand_address (file, x);
1468 break;
808fbfac
JL		 1469 case CONST_DOUBLE:
1470 {
1471 long val;
1472 REAL_VALUE_TYPE rv;
1473 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1474 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1475 fprintf (file, "#%ld", val);
808fbfac
JL		 1476 break;
1477 }
441d04c6
KG		 1478 default:
1479 break;
07aae5c2
SC		 1480 }
1481 }
1482}
1483
1484/* Output assembly language output for the address ADDR to FILE. */
1485
1486void
cb713a8d 1487print_operand_address (FILE *file, rtx addr)
07aae5c2
SC		 1488{
1489 switch (GET_CODE (addr))
1490 {
1491 case REG:
48837e29 1492 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1493 break;
1494
1495 case PRE_DEC:
48837e29 1496 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1497 break;
1498
1499 case POST_INC:
48837e29 1500 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1501 break;
1502
1503 case PLUS:
1504 fprintf (file, "(");
1505 if (GET_CODE (XEXP (addr, 0)) == REG)
1506 {
1507 /* reg,foo */
1508 print_operand_address (file, XEXP (addr, 1));
1509 fprintf (file, ",");
1510 print_operand_address (file, XEXP (addr, 0));
1511 }
1512 else
1513 {
1514 /* foo+k */
1515 print_operand_address (file, XEXP (addr, 0));
1516 fprintf (file, "+");
1517 print_operand_address (file, XEXP (addr, 1));
1518 }
1519 fprintf (file, ")");
1520 break;
1521
1522 case CONST_INT:
48837e29 1523 {
64530b82 1524 /* Since the H8/300 only has 16 bit pointers, negative values are also
48837e29
DE		 1525 those >= 32768. This happens for example with pointer minus a
1526 constant. We don't want to turn (char *p - 2) into
1527 (char *p + 65534) because loop unrolling can build upon this
1528 (IE: char *p + 131068). */
1529 int n = INTVAL (addr);
1530 if (TARGET_H8300)
1531 n = (int) (short) n;
7a770d8b 1532 fprintf (file, "%d", n);
48837e29
DE		 1533 break;
1534 }
07aae5c2
SC		 1535
1536 default:
1537 output_addr_const (file, addr);
1538 break;
1539 }
1540}
1541\f
07aae5c2
SC		 1542/* Output all insn addresses and their sizes into the assembly language
1543 output file. This is helpful for debugging whether the length attributes
1544 in the md file are correct. This is not meant to be a user selectable
1545 option. */
1546
1547void
cb713a8d
KH		 1548final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1549 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1550{
1551 /* This holds the last insn address. */
1552 static int last_insn_address = 0;
1553
7798db98 1554 const int uid = INSN_UID (insn);
07aae5c2
SC		 1555
1556 if (TARGET_ADDRESSES)
1557 {
9d98a694
AO		 1558 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1559 INSN_ADDRESSES (uid) - last_insn_address);
1560 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1561 }
1562}
1563
48837e29
DE		 1564/* Prepare for an SI sized move. */
1565
1566int
1a793acf 1567h8300_expand_movsi (rtx operands[])
07aae5c2 1568{
48837e29
DE		 1569 rtx src = operands[1];
1570 rtx dst = operands[0];
1571 if (!reload_in_progress && !reload_completed)
1572 {
1573 if (!register_operand (dst, GET_MODE (dst)))
1574 {
1575 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1576 emit_move_insn (tmp, src);
1577 operands[1] = tmp;
1578 }
1579 }
1580 return 0;
1581}
1582
1583/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1584 Define the offset between two registers, one to be eliminated, and
1585 the other its replacement, at the start of a routine. */
07aae5c2 1586
48837e29 1587int
cb713a8d 1588h8300_initial_elimination_offset (int from, int to)
48837e29 1589{
d18ad191
KH		 1590 /* The number of bytes that the return address takes on the stack. */
1591 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1592
1807b726
KH		 1593 /* The number of bytes that the saved frame pointer takes on the stack. */
1594 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1595
1596 /* The number of bytes that the saved registers, excluding the frame
1597 pointer, take on the stack. */
1598 int saved_regs_size = 0;
48837e29 1599
1807b726
KH		 1600 /* The number of bytes that the locals takes on the stack. */
1601 int frame_size = round_frame_size (get_frame_size ());
48837e29 1602
1807b726 1603 int regno;
48837e29 1604
1807b726
KH		 1605 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1606 if (WORD_REG_USED (regno))
1607 saved_regs_size += UNITS_PER_WORD;
48837e29 1608
1807b726
KH		 1609 /* Adjust saved_regs_size because the above loop took the frame
1610 pointer int account. */
1611 saved_regs_size -= fp_size;
39ba95b5 1612
1807b726
KH		 1613 if (to == HARD_FRAME_POINTER_REGNUM)
1614 {
1615 switch (from)
1616 {
1617 case ARG_POINTER_REGNUM:
1618 return pc_size + fp_size;
1619 case RETURN_ADDRESS_POINTER_REGNUM:
1620 return fp_size;
1621 case FRAME_POINTER_REGNUM:
1622 return -saved_regs_size;
1623 default:
1624 abort ();
1625 }
1626 }
1627 else if (to == STACK_POINTER_REGNUM)
1628 {
1629 switch (from)
1630 {
1631 case ARG_POINTER_REGNUM:
1632 return pc_size + saved_regs_size + frame_size;
1633 case RETURN_ADDRESS_POINTER_REGNUM:
1634 return saved_regs_size + frame_size;
1635 case FRAME_POINTER_REGNUM:
1636 return frame_size;
1637 default:
1638 abort ();
1639 }
1640 }
1641 else
1642 abort ();
48837e29
DE		 1643}
1644
1aae372e 1645rtx
cb713a8d 1646h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 1647{
1648 rtx ret;
1649
1650 if (count == 0)
1651 ret = gen_rtx_MEM (Pmode,
1652 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1653 else if (flag_omit_frame_pointer)
1654 return (rtx) 0;
1655 else
1656 ret = gen_rtx_MEM (Pmode,
1657 memory_address (Pmode,
1658 plus_constant (frame, UNITS_PER_WORD)));
1659 set_mem_alias_set (ret, get_frame_alias_set ());
1660 return ret;
1661}
1662
48837e29
DE		 1663/* Update the condition code from the insn. */
1664
441d04c6 1665void
cb713a8d 1666notice_update_cc (rtx body, rtx insn)
48837e29 1667{
d99c740f
KH		 1668 rtx set;
1669
48837e29
DE		 1670 switch (get_attr_cc (insn))
1671 {
1672 case CC_NONE:
269c14e1 1673 /* Insn does not affect CC at all. */
48837e29
DE		 1674 break;
1675
1676 case CC_NONE_0HIT:
269c14e1 1677 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 1678 if (cc_status.value1 != 0
1ccbefce 1679 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 1680 cc_status.value1 = 0;
d4d6d0ce
KH		 1681 if (cc_status.value2 != 0
1682 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1683 cc_status.value2 = 0;
48837e29
DE		 1684 break;
1685
065bbfe6 1686 case CC_SET_ZN:
1ccbefce 1687 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 1688 The V flag is unusable. The C flag may or may not be known but
1689 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 1690 CC_STATUS_INIT;
269c14e1 1691 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 1692 set = single_set (insn);
1693 cc_status.value1 = SET_SRC (set);
1694 if (SET_DEST (set) != cc0_rtx)
1695 cc_status.value2 = SET_DEST (set);
48837e29
DE		 1696 break;
1697
065bbfe6 1698 case CC_SET_ZNV:
1ccbefce 1699 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 1700 The C flag may or may not be known but that's ok because
1701 alter_cond will change tests to use EQ/NE. */
1702 CC_STATUS_INIT;
1703 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 1704 set = single_set (insn);
1705 cc_status.value1 = SET_SRC (set);
1706 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 1707 {
1708 /* If the destination is STRICT_LOW_PART, strip off
1709 STRICT_LOW_PART. */
1710 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1711 cc_status.value2 = XEXP (SET_DEST (set), 0);
1712 else
1713 cc_status.value2 = SET_DEST (set);
1714 }
065bbfe6
JL		 1715 break;
1716
269c14e1
DE		 1717 case CC_COMPARE:
1718 /* The insn is a compare instruction. */
48837e29 1719 CC_STATUS_INIT;
269c14e1 1720 cc_status.value1 = SET_SRC (body);
48837e29
DE		 1721 break;
1722
48837e29 1723 case CC_CLOBBER:
269c14e1 1724 /* Insn doesn't leave CC in a usable state. */
48837e29
DE		 1725 CC_STATUS_INIT;
1726 break;
07aae5c2 1727 }
48837e29
DE		 1728}
1729
8ccf5d5f
KH		 1730/* Return nonzero if X is a stack pointer. */
1731
1732int
cb713a8d 1733stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1734{
1735 return x == stack_pointer_rtx;
1736}
1737
8ccf5d5f
KH		 1738/* Return nonzero if X is a constant whose absolute value is greater
1739 than 2. */
1740
1741int
cb713a8d 1742const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1743{
1744 return (GET_CODE (x) == CONST_INT
1745 && abs (INTVAL (x)) > 2);
1746}
1747
1748/* Return nonzero if X is a constant whose absolute value is no
1749 smaller than 8. */
1750
1751int
cb713a8d 1752const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1753{
1754 return (GET_CODE (x) == CONST_INT
1755 && abs (INTVAL (x)) >= 8);
1756}
1757
2873836b
KH		 1758/* Return nonzero if X is a constant expressible in QImode. */
1759
1760int
cb713a8d 1761const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2873836b
KH		 1762{
1763 return (GET_CODE (x) == CONST_INT
1764 && (INTVAL (x) & 0xff) == INTVAL (x));
1765}
1766
1767/* Return nonzero if X is a constant expressible in HImode. */
1768
1769int
cb713a8d 1770const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2873836b
KH		 1771{
1772 return (GET_CODE (x) == CONST_INT
1773 && (INTVAL (x) & 0xffff) == INTVAL (x));
1774}
1775
f9d2de4d
KH		 1776/* Return nonzero if X is a constant suitable for inc/dec. */
1777
1778int
cb713a8d 1779incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
f9d2de4d
KH		 1780{
1781 return (GET_CODE (x) == CONST_INT
1782 && (CONST_OK_FOR_M (INTVAL (x))
1783 || CONST_OK_FOR_O (INTVAL (x))));
1784}
1785
1786/* Return nonzero if X is either EQ or NE. */
1787
1788int
cb713a8d 1789eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
f9d2de4d
KH		 1790{
1791 enum rtx_code code = GET_CODE (x);
1792
1793 return (code == EQ || code == NE);
1794}
1795
9a2dd2dd
KH		 1796/* Return nonzero if X is GT, LE, GTU, or LEU. */
1797
1798int
cb713a8d 1799gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
9a2dd2dd
KH		 1800{
1801 enum rtx_code code = GET_CODE (x);
1802
1803 return (code == GT || code == LE || code == GTU || code == LEU);
1804}
1805
717d8b71
KH		 1806/* Return nonzero if X is either GTU or LEU. */
1807
1808int
cb713a8d 1809gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
717d8b71
KH		 1810{
1811 enum rtx_code code = GET_CODE (x);
1812
1813 return (code == GTU || code == LEU);
1814}
1815
b059c02a
KH		 1816/* Return nonzero if X is either IOR or XOR. */
1817
1818int
cb713a8d 1819iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
b059c02a
KH		 1820{
1821 enum rtx_code code = GET_CODE (x);
1822
1823 return (code == IOR || code == XOR);
1824}
1825
07e4d94e 1826/* Recognize valid operators for bit instructions. */
48837e29
DE		 1827
1828int
cb713a8d 1829bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 1830{
1831 enum rtx_code code = GET_CODE (x);
07aae5c2 1832
48837e29
DE		 1833 return (code == XOR
1834 || code == AND
1835 || code == IOR);
07aae5c2 1836}
48837e29 1837\f
7948a9ea
KH		 1838/* Return the length of mov instruction. */
1839
1840unsigned int
1841compute_mov_length (rtx *operands)
1842{
1843 /* If the mov instruction involves a memory operand, we compute the
1844 length, assuming the largest addressing mode is used, and then
1845 adjust later in the function. Otherwise, we compute and return
1846 the exact length in one step. */
1847 enum machine_mode mode = GET_MODE (operands[0]);
1848 rtx dest = operands[0];
1849 rtx src = operands[1];
1850 rtx addr;
1851
1852 if (GET_CODE (src) == MEM)
1853 addr = XEXP (src, 0);
1854 else if (GET_CODE (dest) == MEM)
1855 addr = XEXP (dest, 0);
1856 else
1857 addr = NULL_RTX;
1858
1859 if (TARGET_H8300)
1860 {
1861 unsigned int base_length;
1862
1863 switch (mode)
1864 {
1865 case QImode:
1866 if (addr == NULL_RTX)
1867 return 2;
1868
1869 /* The eightbit addressing is available only in QImode, so
1870 go ahead and take care of it. */
1871 if (h8300_eightbit_constant_address_p (addr))
1872 return 2;
1873
1874 base_length = 4;
1875 break;
1876
1877 case HImode:
1878 if (addr == NULL_RTX)
1879 {
1880 if (REG_P (src))
1881 return 2;
1882
1883 if (src == const0_rtx)
1884 return 2;
1885
1886 return 4;
1887 }
1888
1889 base_length = 4;
1890 break;
1891
1892 case SImode:
1893 if (addr == NULL_RTX)
1894 {
1895 if (REG_P (src))
1896 return 4;
1897
1898 if (GET_CODE (src) == CONST_INT)
1899 {
1900 if (src == const0_rtx)
1901 return 4;
1902
1903 if ((INTVAL (src) & 0xffff) == 0)
1904 return 6;
1905
1906 if ((INTVAL (src) & 0xffff) == 0)
1907 return 6;
f5139cc5
KH		 1908
1909 if ((INTVAL (src) & 0xffff)
1910 == ((INTVAL (src) >> 16) & 0xffff))
1911 return 6;
7948a9ea
KH		 1912 }
1913 return 8;
1914 }
1915
1916 base_length = 8;
1917 break;
1918
1919 case SFmode:
1920 if (addr == NULL_RTX)
1921 {
1922 if (REG_P (src))
1923 return 4;
1924
2c4a71b3
KH		 1925 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1926 return 4;
1927
81983b04 1928 return 8;
7948a9ea
KH		 1929 }
1930
1931 base_length = 8;
1932 break;
1933
1934 default:
1935 abort ();
1936 }
1937
1938 /* Adjust the length based on the addressing mode used.
1939 Specifically, we subtract the difference between the actual
1940 length and the longest one, which is @(d:16,Rs). For SImode
1941 and SFmode, we double the adjustment because two mov.w are
1942 used to do the job. */
1943
1944 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1945 if (GET_CODE (addr) == PRE_DEC
1946 || GET_CODE (addr) == POST_INC)
1947 {
1948 if (mode == QImode || mode == HImode)
1949 return base_length - 2;
1950 else
1951 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 1952 double the adjustment. */
7948a9ea
KH		 1953 return base_length - 4;
1954 }
1955
1956 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1957 in SImode and SFmode, the second mov.w involves an address
1958 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1959 only 2 bytes. */
1960 if (GET_CODE (addr) == REG)
1961 return base_length - 2;
1962
1963 return base_length;
1964 }
1965 else
1966 {
1967 unsigned int base_length;
1968
1969 switch (mode)
1970 {
1971 case QImode:
1972 if (addr == NULL_RTX)
1973 return 2;
1974
1975 /* The eightbit addressing is available only in QImode, so
1976 go ahead and take care of it. */
1977 if (h8300_eightbit_constant_address_p (addr))
1978 return 2;
1979
1980 base_length = 8;
1981 break;
1982
1983 case HImode:
1984 if (addr == NULL_RTX)
1985 {
1986 if (REG_P (src))
1987 return 2;
1988
1989 if (src == const0_rtx)
1990 return 2;
1991
1992 return 4;
1993 }
1994
1995 base_length = 8;
1996 break;
1997
1998 case SImode:
1999 if (addr == NULL_RTX)
2000 {
2001 if (REG_P (src))
2002 {
2003 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2004 return 4;
2005 else
2006 return 2;
2007 }
2008
2009 if (GET_CODE (src) == CONST_INT)
2010 {
2011 int val = INTVAL (src);
2012
2013 if (val == 0)
2014 return 2;
2015
2016 if (val == (val & 0x00ff) || val == (val & 0xff00))
2017 return 4;
80e58519 2018
7948a9ea
KH		 2019 switch (val & 0xffffffff)
2020 {
2021 case 0xffffffff:
2022 case 0xfffffffe:
2023 case 0xfffffffc:
2024 case 0x0000ffff:
2025 case 0x0000fffe:
2026 case 0xffff0000:
2027 case 0xfffe0000:
2028 case 0x00010000:
2029 case 0x00020000:
2030 return 4;
2031 }
2032 }
2033 return 6;
2034 }
2035
2036 base_length = 10;
2037 break;
2038
2039 case SFmode:
2040 if (addr == NULL_RTX)
2041 {
2042 if (REG_P (src))
2043 return 2;
2044
fad37371 2045 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
7948a9ea 2046 return 2;
2c4a71b3 2047
7948a9ea
KH		 2048 return 6;
2049 }
2050
2051 base_length = 10;
2052 break;
2053
2054 default:
2055 abort ();
2056 }
2057
2058 /* Adjust the length based on the addressing mode used.
2059 Specifically, we subtract the difference between the actual
2060 length and the longest one, which is @(d:24,ERs). */
2061
2062 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2063 if (GET_CODE (addr) == PRE_DEC
2064 || GET_CODE (addr) == POST_INC)
2065 return base_length - 6;
2066
2067 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2068 if (GET_CODE (addr) == REG)
2069 return base_length - 6;
2070
2071 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2072 longest. */
2073 if (GET_CODE (addr) == PLUS
2074 && GET_CODE (XEXP (addr, 0)) == REG
2075 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2076 && INTVAL (XEXP (addr, 1)) > -32768
2077 && INTVAL (XEXP (addr, 1)) < 32767)
2078 return base_length - 4;
2079
2080 /* @aa:16 is 4 bytes shorter than the longest. */
2081 if (h8300_tiny_constant_address_p (addr))
2082 return base_length - 4;
2083
2084 /* @aa:24 is 2 bytes shorter than the longest. */
2085 if (CONSTANT_P (addr))
2086 return base_length - 2;
2087
2088 return base_length;
2089 }
2090}
2091\f
366a7b27 2092const char *
cb713a8d 2093output_plussi (rtx *operands)
7d6ac401
KH		 2094{
2095 enum machine_mode mode = GET_MODE (operands[0]);
2096
2097 if (mode != SImode)
2098 abort ();
2099
2100 if (TARGET_H8300)
2101 {
cfedf91b
KH		 2102 if (GET_CODE (operands[2]) == REG)
2103 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2104
2105 if (GET_CODE (operands[2]) == CONST_INT)
2106 {
2107 HOST_WIDE_INT n = INTVAL (operands[2]);
2108
2109 if ((n & 0xffffff) == 0)
2110 return "add\t%z2,%z0";
2111 if ((n & 0xffff) == 0)
2112 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2113 if ((n & 0xff) == 0)
2114 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2115 }
2116
2117 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 2118 }
2119 else
2120 {
2121 if (GET_CODE (operands[2]) == REG)
2122 return "add.l\t%S2,%S0";
2123
2124 if (GET_CODE (operands[2]) == CONST_INT)
2125 {
2126 HOST_WIDE_INT intval = INTVAL (operands[2]);
2127
2128 /* See if we can finish with 2 bytes. */
2129
9ac7ebba 2130 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2131 {
2132 case 0x00000001:
2133 case 0x00000002:
2134 case 0x00000004:
2135 return "adds\t%2,%S0";
2136
2137 case 0xffffffff:
2138 case 0xfffffffe:
2139 case 0xfffffffc:
2140 return "subs\t%G2,%S0";
2141
2142 case 0x00010000:
2143 case 0x00020000:
2144 operands[2] = GEN_INT (intval >> 16);
2145 return "inc.w\t%2,%e0";
2146
2147 case 0xffff0000:
2148 case 0xfffe0000:
2149 operands[2] = GEN_INT (intval >> 16);
2150 return "dec.w\t%G2,%e0";
2151 }
2152
2153 /* See if we can finish with 4 bytes. */
2154 if ((intval & 0xffff) == 0)
2155 {
2156 operands[2] = GEN_INT (intval >> 16);
2157 return "add.w\t%2,%e0";
2158 }
2159 }
2160
2161 return "add.l\t%S2,%S0";
2162 }
2163}
2164
2165unsigned int
cb713a8d 2166compute_plussi_length (rtx *operands)
7d6ac401
KH		 2167{
2168 enum machine_mode mode = GET_MODE (operands[0]);
2169
2170 if (mode != SImode)
2171 abort ();
2172
2173 if (TARGET_H8300)
2174 {
cfedf91b
KH		 2175 if (GET_CODE (operands[2]) == REG)
2176 return 6;
2177
2178 if (GET_CODE (operands[2]) == CONST_INT)
2179 {
2180 HOST_WIDE_INT n = INTVAL (operands[2]);
2181
2182 if ((n & 0xffffff) == 0)
2183 return 2;
2184 if ((n & 0xffff) == 0)
2185 return 4;
2186 if ((n & 0xff) == 0)
2187 return 6;
2188 }
2189
2190 return 8;
7d6ac401
KH		 2191 }
2192 else
2193 {
2194 if (GET_CODE (operands[2]) == REG)
2195 return 2;
2196
2197 if (GET_CODE (operands[2]) == CONST_INT)
2198 {
2199 HOST_WIDE_INT intval = INTVAL (operands[2]);
2200
2201 /* See if we can finish with 2 bytes. */
2202
9ac7ebba 2203 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2204 {
2205 case 0x00000001:
2206 case 0x00000002:
2207 case 0x00000004:
2208 return 2;
2209
2210 case 0xffffffff:
2211 case 0xfffffffe:
2212 case 0xfffffffc:
2213 return 2;
2214
2215 case 0x00010000:
2216 case 0x00020000:
2217 return 2;
2218
2219 case 0xffff0000:
2220 case 0xfffe0000:
2221 return 2;
2222 }
2223
2224 /* See if we can finish with 4 bytes. */
2225 if ((intval & 0xffff) == 0)
2226 return 4;
2227 }
2228
2229 return 6;
2230 }
2231}
2232
87a902e4 2233int
cb713a8d 2234compute_plussi_cc (rtx *operands)
7d6ac401
KH		 2235{
2236 enum machine_mode mode = GET_MODE (operands[0]);
2237
2238 if (mode != SImode)
2239 abort ();
2240
2241 if (TARGET_H8300)
2242 {
cfedf91b 2243 return CC_CLOBBER;
7d6ac401
KH		 2244 }
2245 else
2246 {
2247 if (GET_CODE (operands[2]) == REG)
2248 return CC_SET_ZN;
2249
2250 if (GET_CODE (operands[2]) == CONST_INT)
2251 {
2252 HOST_WIDE_INT intval = INTVAL (operands[2]);
2253
2254 /* See if we can finish with 2 bytes. */
2255
9ac7ebba 2256 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2257 {
2258 case 0x00000001:
2259 case 0x00000002:
2260 case 0x00000004:
2261 return CC_NONE_0HIT;
2262
2263 case 0xffffffff:
2264 case 0xfffffffe:
2265 case 0xfffffffc:
2266 return CC_NONE_0HIT;
2267
2268 case 0x00010000:
2269 case 0x00020000:
2270 return CC_CLOBBER;
2271
2272 case 0xffff0000:
2273 case 0xfffe0000:
2274 return CC_CLOBBER;
2275 }
2276
2277 /* See if we can finish with 4 bytes. */
2278 if ((intval & 0xffff) == 0)
2279 return CC_CLOBBER;
2280 }
2281
2282 return CC_SET_ZN;
2283 }
2284}
2285\f
2286const char *
cb713a8d 2287output_logical_op (enum machine_mode mode, rtx *operands)
366a7b27 2288{
b42cff6b
KH		 2289 /* Figure out the logical op that we need to perform. */
2290 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 2291 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2292 const unsigned HOST_WIDE_INT intval =
366a7b27
KH		 2293 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2294 ? INTVAL (operands[2]) : 0x55555555);
2295 /* The determinant of the algorithm. If we perform an AND, 0
2296 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2297 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2298 /* Break up DET into pieces. */
2299 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2300 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 2301 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2302 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 2303 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2304 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2305 int lower_half_easy_p = 0;
2306 int upper_half_easy_p = 0;
366a7b27
KH		 2307 /* The name of an insn. */
2308 const char *opname;
2309 char insn_buf[100];
2310
2311 switch (code)
2312 {
2313 case AND:
2314 opname = "and";
2315 break;
2316 case IOR:
2317 opname = "or";
2318 break;
2319 case XOR:
2320 opname = "xor";
2321 break;
2322 default:
2323 abort ();
2324 }
2325
2326 switch (mode)
2327 {
2328 case HImode:
2329 /* First, see if we can finish with one insn. */
2330 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2331 && b0 != 0
2332 && b1 != 0)
366a7b27
KH		 2333 {
2334 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2335 output_asm_insn (insn_buf, operands);
2336 }
2337 else
2338 {
2339 /* Take care of the lower byte. */
c5e7ce43 2340 if (b0 != 0)
366a7b27
KH		 2341 {
2342 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2343 output_asm_insn (insn_buf, operands);
2344 }
2345 /* Take care of the upper byte. */
c5e7ce43 2346 if (b1 != 0)
366a7b27
KH		 2347 {
2348 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2349 output_asm_insn (insn_buf, operands);
2350 }
2351 }
2352 break;
2353 case SImode:
f9ac2f95
KH		 2354 if (TARGET_H8300H || TARGET_H8300S)
2355 {
2356 /* Determine if the lower half can be taken care of in no more
2357 than two bytes. */
2358 lower_half_easy_p = (b0 == 0
2359 || b1 == 0
2360 || (code != IOR && w0 == 0xffff));
2361
2362 /* Determine if the upper half can be taken care of in no more
2363 than two bytes. */
2364 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2365 || (code == AND && w1 == 0xff00));
2366 }
366a7b27 2367
f9ac2f95
KH		 2368 /* Check if doing everything with one insn is no worse than
2369 using multiple insns. */
366a7b27 2370 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2371 && w0 != 0 && w1 != 0
472f2723
KH		 2372 && !(lower_half_easy_p && upper_half_easy_p)
2373 && !(code == IOR && w1 == 0xffff
2374 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 2375 {
2376 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2377 output_asm_insn (insn_buf, operands);
2378 }
2379 else
2380 {
2381 /* Take care of the lower and upper words individually. For
2382 each word, we try different methods in the order of
2383
2384 1) the special insn (in case of AND or XOR),
2385 2) the word-wise insn, and
2386 3) The byte-wise insn. */
c5e7ce43 2387 if (w0 == 0xffff
6dfa4005 2388 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 2389 output_asm_insn ((code == AND)
187462ac 2390 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 2391 operands);
2392 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2393 && (b0 != 0)
2394 && (b1 != 0))
366a7b27
KH		 2395 {
2396 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2397 output_asm_insn (insn_buf, operands);
2398 }
2399 else
2400 {
c5e7ce43 2401 if (b0 != 0)
366a7b27
KH		 2402 {
2403 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2404 output_asm_insn (insn_buf, operands);
2405 }
c5e7ce43 2406 if (b1 != 0)
366a7b27
KH		 2407 {
2408 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2409 output_asm_insn (insn_buf, operands);
2410 }
2411 }
2412
c5e7ce43 2413 if ((w1 == 0xffff)
6dfa4005 2414 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 2415 output_asm_insn ((code == AND)
187462ac 2416 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 2417 operands);
472f2723
KH		 2418 else if ((TARGET_H8300H || TARGET_H8300S)
2419 && code == IOR
2420 && w1 == 0xffff
2421 && (w0 & 0x8000) != 0)
2422 {
2423 output_asm_insn ("exts.l\t%S0", operands);
2424 }
a6e8d113
KH		 2425 else if ((TARGET_H8300H || TARGET_H8300S)
2426 && code == AND
c5e7ce43 2427 && w1 == 0xff00)
a6e8d113 2428 {
dc5f17ec 2429 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 2430 }
366a7b27
KH		 2431 else if (TARGET_H8300H || TARGET_H8300S)
2432 {
c5e7ce43 2433 if (w1 != 0)
366a7b27
KH		 2434 {
2435 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2436 output_asm_insn (insn_buf, operands);
2437 }
2438 }
2439 else
2440 {
c5e7ce43 2441 if (b2 != 0)
366a7b27
KH		 2442 {
2443 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2444 output_asm_insn (insn_buf, operands);
2445 }
c5e7ce43 2446 if (b3 != 0)
366a7b27
KH		 2447 {
2448 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2449 output_asm_insn (insn_buf, operands);
2450 }
2451 }
2452 }
2453 break;
2454 default:
2455 abort ();
2456 }
2457 return "";
2458}
40367e2d
KH		 2459
2460unsigned int
cb713a8d 2461compute_logical_op_length (enum machine_mode mode, rtx *operands)
40367e2d 2462{
b42cff6b
KH		 2463 /* Figure out the logical op that we need to perform. */
2464 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 2465 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2466 const unsigned HOST_WIDE_INT intval =
40367e2d
KH		 2467 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2468 ? INTVAL (operands[2]) : 0x55555555);
2469 /* The determinant of the algorithm. If we perform an AND, 0
2470 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2471 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2472 /* Break up DET into pieces. */
2473 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2474 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 2475 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2476 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 2477 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2478 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2479 int lower_half_easy_p = 0;
2480 int upper_half_easy_p = 0;
40367e2d
KH		 2481 /* Insn length. */
2482 unsigned int length = 0;
2483
2484 switch (mode)
2485 {
2486 case HImode:
2487 /* First, see if we can finish with one insn. */
2488 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2489 && b0 != 0
2490 && b1 != 0)
40367e2d
KH		 2491 {
2492 if (REG_P (operands[2]))
2493 length += 2;
2494 else
2495 length += 4;
2496 }
2497 else
2498 {
2499 /* Take care of the lower byte. */
c5e7ce43 2500 if (b0 != 0)
40367e2d
KH		 2501 length += 2;
2502
2503 /* Take care of the upper byte. */
c5e7ce43 2504 if (b1 != 0)
40367e2d
KH		 2505 length += 2;
2506 }
2507 break;
2508 case SImode:
f9ac2f95
KH		 2509 if (TARGET_H8300H || TARGET_H8300S)
2510 {
2511 /* Determine if the lower half can be taken care of in no more
2512 than two bytes. */
2513 lower_half_easy_p = (b0 == 0
2514 || b1 == 0
2515 || (code != IOR && w0 == 0xffff));
2516
2517 /* Determine if the upper half can be taken care of in no more
2518 than two bytes. */
2519 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2520 || (code == AND && w1 == 0xff00));
2521 }
40367e2d 2522
f9ac2f95
KH		 2523 /* Check if doing everything with one insn is no worse than
2524 using multiple insns. */
40367e2d 2525 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2526 && w0 != 0 && w1 != 0
472f2723
KH		 2527 && !(lower_half_easy_p && upper_half_easy_p)
2528 && !(code == IOR && w1 == 0xffff
2529 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d
KH		 2530 {
2531 if (REG_P (operands[2]))
2532 length += 4;
2533 else
2534 length += 6;
2535 }
2536 else
2537 {
2538 /* Take care of the lower and upper words individually. For
2539 each word, we try different methods in the order of
2540
2541 1) the special insn (in case of AND or XOR),
2542 2) the word-wise insn, and
2543 3) The byte-wise insn. */
c5e7ce43 2544 if (w0 == 0xffff
40367e2d
KH		 2545 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2546 {
2547 length += 2;
2548 }
2549 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2550 && (b0 != 0)
2551 && (b1 != 0))
40367e2d
KH		 2552 {
2553 length += 4;
2554 }
2555 else
2556 {
c5e7ce43 2557 if (b0 != 0)
40367e2d
KH		 2558 length += 2;
2559
c5e7ce43 2560 if (b1 != 0)
40367e2d
KH		 2561 length += 2;
2562 }
2563
c5e7ce43 2564 if (w1 == 0xffff
40367e2d
KH		 2565 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2566 {
2567 length += 2;
2568 }
472f2723
KH		 2569 else if ((TARGET_H8300H || TARGET_H8300S)
2570 && code == IOR
2571 && w1 == 0xffff
2572 && (w0 & 0x8000) != 0)
2573 {
2574 length += 2;
2575 }
a6e8d113
KH		 2576 else if ((TARGET_H8300H || TARGET_H8300S)
2577 && code == AND
c5e7ce43 2578 && w1 == 0xff00)
a6e8d113
KH		 2579 {
2580 length += 2;
2581 }
40367e2d
KH		 2582 else if (TARGET_H8300H || TARGET_H8300S)
2583 {
c5e7ce43 2584 if (w1 != 0)
40367e2d
KH		 2585 length += 4;
2586 }
2587 else
2588 {
c5e7ce43 2589 if (b2 != 0)
40367e2d
KH		 2590 length += 2;
2591
c5e7ce43 2592 if (b3 != 0)
40367e2d
KH		 2593 length += 2;
2594 }
2595 }
2596 break;
2597 default:
2598 abort ();
2599 }
2600 return length;
2601}
b42cff6b
KH		 2602
2603int
cb713a8d 2604compute_logical_op_cc (enum machine_mode mode, rtx *operands)
b42cff6b
KH		 2605{
2606 /* Figure out the logical op that we need to perform. */
2607 enum rtx_code code = GET_CODE (operands[3]);
2608 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2609 const unsigned HOST_WIDE_INT intval =
b42cff6b
KH		 2610 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2611 ? INTVAL (operands[2]) : 0x55555555);
2612 /* The determinant of the algorithm. If we perform an AND, 0
2613 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2614 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2615 /* Break up DET into pieces. */
2616 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2617 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2618 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2619 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2620 int lower_half_easy_p = 0;
2621 int upper_half_easy_p = 0;
b42cff6b
KH		 2622 /* Condition code. */
2623 enum attr_cc cc = CC_CLOBBER;
2624
2625 switch (mode)
2626 {
2627 case HImode:
2628 /* First, see if we can finish with one insn. */
2629 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2630 && b0 != 0
2631 && b1 != 0)
b42cff6b
KH		 2632 {
2633 cc = CC_SET_ZNV;
2634 }
2635 break;
2636 case SImode:
f9ac2f95
KH		 2637 if (TARGET_H8300H || TARGET_H8300S)
2638 {
2639 /* Determine if the lower half can be taken care of in no more
2640 than two bytes. */
2641 lower_half_easy_p = (b0 == 0
2642 || b1 == 0
2643 || (code != IOR && w0 == 0xffff));
2644
2645 /* Determine if the upper half can be taken care of in no more
2646 than two bytes. */
2647 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2648 || (code == AND && w1 == 0xff00));
2649 }
b42cff6b 2650
f9ac2f95
KH		 2651 /* Check if doing everything with one insn is no worse than
2652 using multiple insns. */
b42cff6b 2653 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2654 && w0 != 0 && w1 != 0
472f2723
KH		 2655 && !(lower_half_easy_p && upper_half_easy_p)
2656 && !(code == IOR && w1 == 0xffff
2657 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 2658 {
2659 cc = CC_SET_ZNV;
2660 }
472f2723
KH		 2661 else
2662 {
2663 if ((TARGET_H8300H || TARGET_H8300S)
2664 && code == IOR
2665 && w1 == 0xffff
2666 && (w0 & 0x8000) != 0)
2667 {
2668 cc = CC_SET_ZNV;
2669 }
2670 }
b42cff6b
KH		 2671 break;
2672 default:
2673 abort ();
2674 }
2675 return cc;
2676}
366a7b27 2677\f
48837e29
DE		 2678/* Shifts.
2679
005e3e05
KH		 2680 We devote a fair bit of code to getting efficient shifts since we
2681 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 2682 one or two bits at a time on the H8S.
005e3e05
KH		 2683
2684 All shift code falls into one of the following ways of
2685 implementation:
2686
2687 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2688 when a straight line shift is about the same size or smaller than
2689 a loop.
2690
2691 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2692 off the bits we don't need. This is used when only a few of the
2693 bits in the original value will survive in the shifted value.
2694
2695 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2696 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2697 shifts can be added if the shift count is slightly more than 8 or
2698 16. This case also includes other oddballs that are not worth
f411c849 2699 explaining here.
005e3e05 2700
3db11b5c 2701 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 2702
5ec0b66e
KH		 2703 For each shift count, we try to use code that has no trade-off
2704 between code size and speed whenever possible.
2705
2706 If the trade-off is unavoidable, we try to be reasonable.
2707 Specifically, the fastest version is one instruction longer than
2708 the shortest version, we take the fastest version. We also provide
2709 the use a way to switch back to the shortest version with -Os.
2710
2711 For the details of the shift algorithms for various shift counts,
2712 refer to shift_alg_[qhs]i. */
07aae5c2
SC		 2713
2714int
cb713a8d 2715nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 2716{
2717 switch (GET_CODE (x))
2718 {
2719 case ASHIFTRT:
2720 case LSHIFTRT:
2721 case ASHIFT:
2722 return 1;
2723
2724 default:
2725 return 0;
2726 }
2727}
2728
317d21e9 2729/* Emit code to do shifts. */
48837e29 2730
317d21e9 2731void
cb713a8d 2732expand_a_shift (enum machine_mode mode, int code, rtx operands[])
07aae5c2 2733{
07aae5c2
SC		 2734 emit_move_insn (operands[0], operands[1]);
2735
07e4d94e
KH		 2736 /* Need a loop to get all the bits we want - we generate the
2737 code at emit time, but need to allocate a scratch reg now. */
48837e29 2738
c5c76735
JL		 2739 emit_insn (gen_rtx_PARALLEL
2740 (VOIDmode,
48837e29 2741 gen_rtvec (2,
c5c76735 2742 gen_rtx_SET (VOIDmode, operands[0],
0f4c242b
KH		 2743 gen_rtx_fmt_ee (code, mode,
2744 operands[0], operands[2])),
c5c76735
JL		 2745 gen_rtx_CLOBBER (VOIDmode,
2746 gen_rtx_SCRATCH (QImode)))));
48837e29
DE		 2747}
2748
48837e29
DE		 2749/* Symbols of the various modes which can be used as indices. */
2750
2751enum shift_mode
1a63219b
KH		 2752{
2753 QIshift, HIshift, SIshift
2754};
48837e29 2755
269c14e1
DE		 2756/* For single bit shift insns, record assembler and what bits of the
2757 condition code are valid afterwards (represented as various CC_FOO
2758 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 2759
2760struct shift_insn
2761{
8b60264b
KG		 2762 const char *const assembler;
2763 const int cc_valid;
48837e29
DE		 2764};
2765
2766/* Assembler instruction shift table.
2767
2768 These tables are used to look up the basic shifts.
07e4d94e 2769 They are indexed by cpu, shift_type, and mode. */
07aae5c2 2770
48837e29
DE		 2771static const struct shift_insn shift_one[2][3][3] =
2772{
2773/* H8/300 */
2774 {
2775/* SHIFT_ASHIFT */
2776 {
45ca2106
KH		 2777 { "shll\t%X0", CC_SET_ZNV },
2778 { "add.w\t%T0,%T0", CC_SET_ZN },
2779 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 2780 },
2781/* SHIFT_LSHIFTRT */
2782 {
45ca2106
KH		 2783 { "shlr\t%X0", CC_SET_ZNV },
2784 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2785 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 2786 },
2787/* SHIFT_ASHIFTRT */
2788 {
45ca2106
KH		 2789 { "shar\t%X0", CC_SET_ZNV },
2790 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2791 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 2792 }
2793 },
2794/* H8/300H */
2795 {
2796/* SHIFT_ASHIFT */
2797 {
45ca2106
KH		 2798 { "shll.b\t%X0", CC_SET_ZNV },
2799 { "shll.w\t%T0", CC_SET_ZNV },
2800 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2801 },
2802/* SHIFT_LSHIFTRT */
2803 {
45ca2106
KH		 2804 { "shlr.b\t%X0", CC_SET_ZNV },
2805 { "shlr.w\t%T0", CC_SET_ZNV },
2806 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2807 },
2808/* SHIFT_ASHIFTRT */
2809 {
45ca2106
KH		 2810 { "shar.b\t%X0", CC_SET_ZNV },
2811 { "shar.w\t%T0", CC_SET_ZNV },
2812 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2813 }
2814 }
2815};
07aae5c2 2816
51c0c1d7
JL		 2817static const struct shift_insn shift_two[3][3] =
2818{
2819/* SHIFT_ASHIFT */
2820 {
45ca2106
KH		 2821 { "shll.b\t#2,%X0", CC_SET_ZNV },
2822 { "shll.w\t#2,%T0", CC_SET_ZNV },
2823 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2824 },
2825/* SHIFT_LSHIFTRT */
2826 {
45ca2106
KH		 2827 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2828 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2829 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2830 },
2831/* SHIFT_ASHIFTRT */
2832 {
45ca2106
KH		 2833 { "shar.b\t#2,%X0", CC_SET_ZNV },
2834 { "shar.w\t#2,%T0", CC_SET_ZNV },
2835 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2836 }
2837};
2838
48837e29
DE		 2839/* Rotates are organized by which shift they'll be used in implementing.
2840 There's no need to record whether the cc is valid afterwards because
2841 it is the AND insn that will decide this. */
07aae5c2 2842
48837e29
DE		 2843static const char *const rotate_one[2][3][3] =
2844{
2845/* H8/300 */
2846 {
2847/* SHIFT_ASHIFT */
2848 {
51c0c1d7
JL		 2849 "rotr\t%X0",
2850 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 2851 0
2852 },
2853/* SHIFT_LSHIFTRT */
2854 {
51c0c1d7
JL		 2855 "rotl\t%X0",
2856 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 2857 0
2858 },
2859/* SHIFT_ASHIFTRT */
2860 {
51c0c1d7
JL		 2861 "rotl\t%X0",
2862 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 2863 0
07aae5c2 2864 }
48837e29
DE		 2865 },
2866/* H8/300H */
2867 {
2868/* SHIFT_ASHIFT */
2869 {
51c0c1d7
JL		 2870 "rotr.b\t%X0",
2871 "rotr.w\t%T0",
2872 "rotr.l\t%S0"
48837e29
DE		 2873 },
2874/* SHIFT_LSHIFTRT */
07aae5c2 2875 {
51c0c1d7
JL		 2876 "rotl.b\t%X0",
2877 "rotl.w\t%T0",
2878 "rotl.l\t%S0"
48837e29
DE		 2879 },
2880/* SHIFT_ASHIFTRT */
2881 {
51c0c1d7
JL		 2882 "rotl.b\t%X0",
2883 "rotl.w\t%T0",
2884 "rotl.l\t%S0"
48837e29
DE		 2885 }
2886 }
2887};
2888
51c0c1d7
JL		 2889static const char *const rotate_two[3][3] =
2890{
2891/* SHIFT_ASHIFT */
2892 {
2893 "rotr.b\t#2,%X0",
2894 "rotr.w\t#2,%T0",
2895 "rotr.l\t#2,%S0"
2896 },
2897/* SHIFT_LSHIFTRT */
2898 {
2899 "rotl.b\t#2,%X0",
2900 "rotl.w\t#2,%T0",
2901 "rotl.l\t#2,%S0"
2902 },
2903/* SHIFT_ASHIFTRT */
2904 {
2905 "rotl.b\t#2,%X0",
2906 "rotl.w\t#2,%T0",
2907 "rotl.l\t#2,%S0"
2908 }
2909};
2910
35fb3d1f
KH		 2911struct shift_info {
2912 /* Shift algorithm. */
2913 enum shift_alg alg;
2914
2915 /* The number of bits to be shifted by shift1 and shift2. Valid
2916 when ALG is SHIFT_SPECIAL. */
2917 unsigned int remainder;
2918
2919 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2920 const char *special;
2921
2922 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 2923 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 2924 const char *shift1;
2925
2926 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 2927 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 2928 const char *shift2;
2929
45ca2106
KH		 2930 /* CC status for SHIFT_INLINE. */
2931 int cc_inline;
2932
2933 /* CC status for SHIFT_SPECIAL. */
2934 int cc_special;
35fb3d1f
KH		 2935};
2936
cb713a8d
KH		 2937static void get_shift_alg (enum shift_type,
2938 enum shift_mode, unsigned int,
2939 struct shift_info *);
441d04c6 2940
c009a745
KH		 2941/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2942 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 2943 in the pointers in INFO. We achieve the maximum efficiency in most
2944 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2945 SImode in particular have a lot of room to optimize.
2946
2947 We first determine the strategy of the shift algorithm by a table
2948 lookup. If that tells us to use a hand crafted assembly code, we
2949 go into the big switch statement to find what that is. Otherwise,
2950 we resort to a generic way, such as inlining. In either case, the
2951 result is returned through INFO. */
48837e29 2952
cb33eb17 2953static void
cb713a8d
KH		 2954get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2955 unsigned int count, struct shift_info *info)
48837e29 2956{
b9b575e6 2957 enum h8_cpu cpu;
769828ab
KH		 2958
2959 /* Find the target CPU. */
2960 if (TARGET_H8300)
b9b575e6 2961 cpu = H8_300;
769828ab 2962 else if (TARGET_H8300H)
b9b575e6 2963 cpu = H8_300H;
769828ab 2964 else
b9b575e6 2965 cpu = H8_S;
769828ab 2966
96eaf358 2967 /* Find the shift algorithm. */
b9b575e6 2968 info->alg = SHIFT_LOOP;
48837e29
DE		 2969 switch (shift_mode)
2970 {
2971 case QIshift:
b9b575e6 2972 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 2973 info->alg = shift_alg_qi[cpu][shift_type][count];
2974 break;
769828ab 2975
96eaf358 2976 case HIshift:
b9b575e6 2977 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 2978 info->alg = shift_alg_hi[cpu][shift_type][count];
2979 break;
2980
2981 case SIshift:
b9b575e6 2982 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 2983 info->alg = shift_alg_si[cpu][shift_type][count];
2984 break;
2985
2986 default:
2987 abort ();
2988 }
2989
2990 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2991 switch (info->alg)
2992 {
2993 case SHIFT_INLINE:
2994 info->remainder = count;
2995 /* Fall through. */
2996
2997 case SHIFT_LOOP:
2998 /* It is up to the caller to know that looping clobbers cc. */
2999 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3000 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 3001 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 3002 goto end;
3003
3004 case SHIFT_ROT_AND:
3005 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3006 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 3007 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 3008 goto end;
3009
3010 case SHIFT_SPECIAL:
3011 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3012 info->remainder = 0;
3013 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3014 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 3015 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3016 info->cc_special = CC_CLOBBER;
96eaf358
KH		 3017 break;
3018 }
51c0c1d7 3019
96eaf358
KH		 3020 /* Here we only deal with SHIFT_SPECIAL. */
3021 switch (shift_mode)
3022 {
3023 case QIshift:
769828ab
KH		 3024 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3025 through the entire value. */
3026 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3027 {
3028 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
692b7eb3 3029 goto end;
769828ab
KH		 3030 }
3031 abort ();
3032
3033 case HIshift:
769828ab 3034 if (count == 7)
51c0c1d7 3035 {
a77b1dbc 3036 switch (shift_type)
51c0c1d7 3037 {
a77b1dbc
KH		 3038 case SHIFT_ASHIFT:
3039 if (TARGET_H8300)
3040 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3041 else
3042 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 3043 goto end;
a77b1dbc
KH		 3044 case SHIFT_LSHIFTRT:
3045 if (TARGET_H8300)
3046 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3047 else
3048 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 3049 goto end;
a77b1dbc 3050 case SHIFT_ASHIFTRT:
35fb3d1f 3051 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 3052 goto end;
48837e29 3053 }
07aae5c2 3054 }
b30686ec 3055 else if ((8 <= count && count <= 13)
a38b3eea 3056 || (TARGET_H8300S && count == 14))
07aae5c2 3057 {
a7812c0b
KH		 3058 info->remainder = count - 8;
3059
51c0c1d7 3060 switch (shift_type)
48837e29 3061 {
51c0c1d7 3062 case SHIFT_ASHIFT:
35fb3d1f 3063 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 3064 goto end;
51c0c1d7 3065 case SHIFT_LSHIFTRT:
a7612343
KH		 3066 if (TARGET_H8300)
3067 {
3068 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3069 info->shift1 = "shlr.b\t%s0";
45ca2106 3070 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 3071 }
3072 else
3073 {
3074 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 3075 info->cc_special = CC_SET_ZNV;
a7612343 3076 }
692b7eb3 3077 goto end;
51c0c1d7
JL		 3078 case SHIFT_ASHIFTRT:
3079 if (TARGET_H8300)
a7612343
KH		 3080 {
3081 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3082 info->shift1 = "shar.b\t%s0";
a7612343 3083 }
51c0c1d7 3084 else
a7612343
KH		 3085 {
3086 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 3087 info->cc_special = CC_SET_ZNV;
a7612343 3088 }
692b7eb3 3089 goto end;
51c0c1d7
JL		 3090 }
3091 }
5e98fba2
DD		 3092 else if (count == 14)
3093 {
3094 switch (shift_type)
3095 {
3096 case SHIFT_ASHIFT:
3097 if (TARGET_H8300)
3098 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3099 goto end;
3100 case SHIFT_LSHIFTRT:
3101 if (TARGET_H8300)
3102 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3103 goto end;
3104 case SHIFT_ASHIFTRT:
3105 if (TARGET_H8300)
3106 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3107 else if (TARGET_H8300H)
45ca2106
KH		 3108 {
3109 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3110 info->cc_special = CC_SET_ZNV;
3111 }
5e98fba2 3112 else /* TARGET_H8300S */
b30686ec 3113 abort ();
5e98fba2
DD		 3114 goto end;
3115 }
3116 }
1e41e866 3117 else if (count == 15)
51c0c1d7 3118 {
1e41e866
KH		 3119 switch (shift_type)
3120 {
3121 case SHIFT_ASHIFT:
3122 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3123 goto end;
3124 case SHIFT_LSHIFTRT:
3125 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3126 goto end;
3127 case SHIFT_ASHIFTRT:
3128 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3129 goto end;
3130 }
07aae5c2 3131 }
769828ab 3132 abort ();
51c0c1d7 3133
48837e29 3134 case SIshift:
1e41e866 3135 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 3136 {
1e41e866
KH		 3137 info->remainder = count - 8;
3138
51c0c1d7 3139 switch (shift_type)
48837e29 3140 {
51c0c1d7 3141 case SHIFT_ASHIFT:
35fb3d1f 3142 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 3143 goto end;
51c0c1d7 3144 case SHIFT_LSHIFTRT:
35fb3d1f 3145 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 3146 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 3147 goto end;
51c0c1d7 3148 case SHIFT_ASHIFTRT:
35fb3d1f 3149 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 3150 goto end;
48837e29 3151 }
48837e29 3152 }
e6bcfef9
JS		 3153 else if (count == 8 && !TARGET_H8300)
3154 {
3155 switch (shift_type)
3156 {
3157 case SHIFT_ASHIFT:
35fb3d1f 3158 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 3159 goto end;
e6bcfef9 3160 case SHIFT_LSHIFTRT:
35fb3d1f 3161 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 3162 goto end;
e6bcfef9 3163 case SHIFT_ASHIFTRT:
35fb3d1f 3164 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 3165 goto end;
e6bcfef9
JS		 3166 }
3167 }
1e41e866
KH		 3168 else if (count == 15 && TARGET_H8300)
3169 {
3170 switch (shift_type)
3171 {
3172 case SHIFT_ASHIFT:
3173 abort ();
3174 case SHIFT_LSHIFTRT:
a35abc3c 3175 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 3176 goto end;
3177 case SHIFT_ASHIFTRT:
a35abc3c 3178 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 3179 goto end;
3180 }
3181 }
dd69e230
KH		 3182 else if (count == 15 && !TARGET_H8300)
3183 {
3184 switch (shift_type)
3185 {
3186 case SHIFT_ASHIFT:
3187 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 3188 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3189 goto end;
3190 case SHIFT_LSHIFTRT:
18cf8dda 3191 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 3192 info->cc_special = CC_SET_ZNV;
dd69e230 3193 goto end;
aefc5826
KH		 3194 case SHIFT_ASHIFTRT:
3195 abort ();
dd69e230
KH		 3196 }
3197 }
1e41e866 3198 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 3199 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 3200 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 3201 {
a7812c0b
KH		 3202 info->remainder = count - 16;
3203
48837e29
DE		 3204 switch (shift_type)
3205 {
3206 case SHIFT_ASHIFT:
35fb3d1f 3207 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 3208 if (TARGET_H8300)
b30686ec 3209 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 3210 goto end;
51c0c1d7 3211 case SHIFT_LSHIFTRT:
1e41e866
KH		 3212 if (TARGET_H8300)
3213 {
a7612343
KH		 3214 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3215 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 3216 }
3217 else
3218 {
a7612343 3219 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 3220 info->cc_special = CC_SET_ZNV;
1e41e866 3221 }
692b7eb3 3222 goto end;
51c0c1d7
JL		 3223 case SHIFT_ASHIFTRT:
3224 if (TARGET_H8300)
1e41e866
KH		 3225 {
3226 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3227 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3228 }
51c0c1d7 3229 else
1e41e866
KH		 3230 {
3231 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 3232 info->cc_special = CC_SET_ZNV;
1e41e866 3233 }
692b7eb3 3234 goto end;
51c0c1d7
JL		 3235 }
3236 }
1e41e866 3237 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 3238 {
3239 info->remainder = count - 24;
f0b6f9a6 3240
f9477efd
KH		 3241 switch (shift_type)
3242 {
3243 case SHIFT_ASHIFT:
3244 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3245 info->shift1 = "shll.b\t%z0";
45ca2106 3246 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 3247 goto end;
3248 case SHIFT_LSHIFTRT:
3249 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3250 info->shift1 = "shlr.b\t%w0";
45ca2106 3251 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 3252 goto end;
3253 case SHIFT_ASHIFTRT:
3254 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3255 info->shift1 = "shar.b\t%w0";
45ca2106 3256 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 3257 goto end;
3258 }
3259 }
4a4ae922
KH		 3260 else if ((TARGET_H8300H && count == 24)
3261 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 3262 {
4a4ae922
KH		 3263 info->remainder = count - 24;
3264
e6bcfef9
JS		 3265 switch (shift_type)
3266 {
3267 case SHIFT_ASHIFT:
35fb3d1f 3268 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 3269 goto end;
e6bcfef9 3270 case SHIFT_LSHIFTRT:
35fb3d1f 3271 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 3272 info->cc_special = CC_SET_ZNV;
692b7eb3 3273 goto end;
e6bcfef9 3274 case SHIFT_ASHIFTRT:
35fb3d1f 3275 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 3276 info->cc_special = CC_SET_ZNV;
692b7eb3 3277 goto end;
e6bcfef9
JS		 3278 }
3279 }
1e5bdc40
KH		 3280 else if (!TARGET_H8300 && count == 28)
3281 {
3282 switch (shift_type)
3283 {
3284 case SHIFT_ASHIFT:
3285 if (TARGET_H8300H)
3286 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3287 else
3288 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3289 goto end;
3290 case SHIFT_LSHIFTRT:
3291 if (TARGET_H8300H)
45ca2106
KH		 3292 {
3293 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3294 info->cc_special = CC_SET_ZNV;
3295 }
1e5bdc40 3296 else
a7612343 3297 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3298 goto end;
3299 case SHIFT_ASHIFTRT:
3300 abort ();
3301 }
3302 }
3303 else if (!TARGET_H8300 && count == 29)
3304 {
3305 switch (shift_type)
3306 {
3307 case SHIFT_ASHIFT:
3308 if (TARGET_H8300H)
3309 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3310 else
3311 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3312 goto end;
3313 case SHIFT_LSHIFTRT:
3314 if (TARGET_H8300H)
45ca2106
KH		 3315 {
3316 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3317 info->cc_special = CC_SET_ZNV;
3318 }
1e5bdc40 3319 else
45ca2106
KH		 3320 {
3321 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3322 info->cc_special = CC_SET_ZNV;
3323 }
1e5bdc40
KH		 3324 goto end;
3325 case SHIFT_ASHIFTRT:
3326 abort ();
3327 }
3328 }
3329 else if (!TARGET_H8300 && count == 30)
3330 {
3331 switch (shift_type)
3332 {
3333 case SHIFT_ASHIFT:
3334 if (TARGET_H8300H)
3335 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3336 else
3337 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3338 goto end;
3339 case SHIFT_LSHIFTRT:
3340 if (TARGET_H8300H)
a7612343 3341 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 3342 else
a7612343 3343 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3344 goto end;
3345 case SHIFT_ASHIFTRT:
3346 abort ();
3347 }
3348 }
48837e29
DE		 3349 else if (count == 31)
3350 {
dd69e230 3351 if (TARGET_H8300)
48837e29 3352 {
dd69e230
KH		 3353 switch (shift_type)
3354 {
3355 case SHIFT_ASHIFT:
3356 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3357 goto end;
3358 case SHIFT_LSHIFTRT:
3359 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3360 goto end;
3361 case SHIFT_ASHIFTRT:
3362 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3363 goto end;
3364 }
48837e29
DE		 3365 }
3366 else
3367 {
dd69e230 3368 switch (shift_type)
48837e29 3369 {
dd69e230
KH		 3370 case SHIFT_ASHIFT:
3371 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 3372 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3373 goto end;
3374 case SHIFT_LSHIFTRT:
3375 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 3376 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3377 goto end;
3378 case SHIFT_ASHIFTRT:
a7612343 3379 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 3380 info->cc_special = CC_SET_ZNV;
692b7eb3 3381 goto end;
48837e29 3382 }
48837e29
DE		 3383 }
3384 }
769828ab 3385 abort ();
51c0c1d7 3386
48837e29
DE		 3387 default:
3388 abort ();
07aae5c2 3389 }
48837e29 3390
cb33eb17
KH		 3391 end:
3392 if (!TARGET_H8300S)
3393 info->shift2 = NULL;
07aae5c2
SC		 3394}
3395
be1e06df
KH		 3396/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3397 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3398
3399int
cb713a8d 3400h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
be1e06df 3401{
b9b575e6 3402 enum h8_cpu cpu;
be1e06df
KH		 3403 int a, lr, ar;
3404
3405 if (GET_MODE_BITSIZE (mode) <= count)
3406 return 1;
3407
3408 /* Find out the target CPU. */
3409 if (TARGET_H8300)
b9b575e6 3410 cpu = H8_300;
be1e06df 3411 else if (TARGET_H8300H)
b9b575e6 3412 cpu = H8_300H;
be1e06df 3413 else
b9b575e6 3414 cpu = H8_S;
be1e06df
KH		 3415
3416 /* Find the shift algorithm. */
3417 switch (mode)
3418 {
3419 case QImode:
3420 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3421 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3422 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3423 break;
3424
3425 case HImode:
3426 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3427 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3428 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3429 break;
3430
3431 case SImode:
3432 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3433 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3434 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3435 break;
3436
3437 default:
3438 abort ();
3439 }
3440
aa2fb4dd 3441 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 3442 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 3443 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 3444}
3445
48837e29
DE		 3446/* Emit the assembler code for doing shifts. */
3447
441d04c6 3448const char *
cb713a8d 3449output_a_shift (rtx *operands)
07aae5c2 3450{
48837e29 3451 static int loopend_lab;
48837e29
DE		 3452 rtx shift = operands[3];
3453 enum machine_mode mode = GET_MODE (shift);
3454 enum rtx_code code = GET_CODE (shift);
3455 enum shift_type shift_type;
3456 enum shift_mode shift_mode;
35fb3d1f 3457 struct shift_info info;
48837e29
DE		 3458
3459 loopend_lab++;
3460
3461 switch (mode)
3462 {
3463 case QImode:
3464 shift_mode = QIshift;
3465 break;
3466 case HImode:
3467 shift_mode = HIshift;
3468 break;
3469 case SImode:
3470 shift_mode = SIshift;
3471 break;
3472 default:
3473 abort ();
3474 }
07aae5c2 3475
48837e29 3476 switch (code)
07aae5c2 3477 {
48837e29
DE		 3478 case ASHIFTRT:
3479 shift_type = SHIFT_ASHIFTRT;
3480 break;
3481 case LSHIFTRT:
3482 shift_type = SHIFT_LSHIFTRT;
3483 break;
3484 case ASHIFT:
3485 shift_type = SHIFT_ASHIFT;
3486 break;
3487 default:
3488 abort ();
3489 }
07aae5c2 3490
48837e29
DE		 3491 if (GET_CODE (operands[2]) != CONST_INT)
3492 {
cd9b5ca8
KH		 3493 /* This case must be taken care of by one of the two splitters
3494 that convert a variable shift into a loop. */
3495 abort ();
48837e29
DE		 3496 }
3497 else
3498 {
3499 int n = INTVAL (operands[2]);
48837e29
DE		 3500
3501 /* If the count is negative, make it 0. */
3502 if (n < 0)
3503 n = 0;
3504 /* If the count is too big, truncate it.
3505 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3506 do the intuitive thing. */
64530b82 3507 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
48837e29
DE		 3508 n = GET_MODE_BITSIZE (mode);
3509
cb33eb17 3510 get_shift_alg (shift_type, shift_mode, n, &info);
48837e29 3511
cb33eb17 3512 switch (info.alg)
48837e29 3513 {
cb33eb17
KH		 3514 case SHIFT_SPECIAL:
3515 output_asm_insn (info.special, operands);
3516 /* Fall through. */
3517
48837e29 3518 case SHIFT_INLINE:
cb33eb17
KH		 3519 n = info.remainder;
3520
51c0c1d7 3521 /* Emit two bit shifts first. */
1a275226 3522 if (info.shift2 != NULL)
51c0c1d7 3523 {
1a275226
KH		 3524 for (; n > 1; n -= 2)
3525 output_asm_insn (info.shift2, operands);
51c0c1d7
JL		 3526 }
3527
3528 /* Now emit one bit shifts for any residual. */
1a275226
KH		 3529 for (; n > 0; n--)
3530 output_asm_insn (info.shift1, operands);
48837e29 3531 return "";
51c0c1d7 3532
48837e29
DE		 3533 case SHIFT_ROT_AND:
3534 {
3535 int m = GET_MODE_BITSIZE (mode) - n;
7798db98
KH		 3536 const int mask = (shift_type == SHIFT_ASHIFT
3537 ? ((1 << m) - 1) << n
3538 : (1 << m) - 1);
48837e29 3539 char insn_buf[200];
b5eaf9ba 3540
48837e29
DE		 3541 /* Not all possibilities of rotate are supported. They shouldn't
3542 be generated, but let's watch for 'em. */
35fb3d1f 3543 if (info.shift1 == 0)
48837e29 3544 abort ();
51c0c1d7
JL		 3545
3546 /* Emit two bit rotates first. */
1a275226 3547 if (info.shift2 != NULL)
51c0c1d7 3548 {
1a275226
KH		 3549 for (; m > 1; m -= 2)
3550 output_asm_insn (info.shift2, operands);
51c0c1d7
JL		 3551 }
3552
3553 /* Now single bit rotates for any residual. */
1a275226
KH		 3554 for (; m > 0; m--)
3555 output_asm_insn (info.shift1, operands);
51c0c1d7
JL		 3556
3557 /* Now mask off the high bits. */
ade53a50
KH		 3558 if (mode == QImode)
3559 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3560 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3561 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3562 else
3563 abort ();
3564
48837e29
DE		 3565 output_asm_insn (insn_buf, operands);
3566 return "";
3567 }
b5eaf9ba 3568
b5eaf9ba
KH		 3569 case SHIFT_LOOP:
3570 /* A loop to shift by a "large" constant value.
3571 If we have shift-by-2 insns, use them. */
35fb3d1f 3572 if (info.shift2 != NULL)
b5eaf9ba
KH		 3573 {
3574 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3575 names_big[REGNO (operands[4])]);
3576 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
35fb3d1f 3577 output_asm_insn (info.shift2, operands);
b5eaf9ba
KH		 3578 output_asm_insn ("add #0xff,%X4", operands);
3579 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3580 if (n % 2)
35fb3d1f 3581 output_asm_insn (info.shift1, operands);
b5eaf9ba
KH		 3582 }
3583 else
3584 {
3585 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3586 names_big[REGNO (operands[4])]);
3587 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
35fb3d1f 3588 output_asm_insn (info.shift1, operands);
b5eaf9ba
KH		 3589 output_asm_insn ("add #0xff,%X4", operands);
3590 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3591 }
51c0c1d7 3592 return "";
b5eaf9ba
KH		 3593
3594 default:
3595 abort ();
51c0c1d7 3596 }
07aae5c2 3597 }
07aae5c2 3598}
86855e8c
KH		 3599
3600static unsigned int
cb713a8d 3601h8300_asm_insn_count (const char *template)
86855e8c
KH		 3602{
3603 unsigned int count = 1;
3604
3605 for (; *template; template++)
3606 if (*template == '\n')
3607 count++;
3608
3609 return count;
3610}
3611
3612unsigned int
cb713a8d 3613compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 3614{
3615 rtx shift = operands[3];
3616 enum machine_mode mode = GET_MODE (shift);
3617 enum rtx_code code = GET_CODE (shift);
3618 enum shift_type shift_type;
3619 enum shift_mode shift_mode;
3620 struct shift_info info;
3621 unsigned int wlength = 0;
3622
3623 switch (mode)
3624 {
3625 case QImode:
3626 shift_mode = QIshift;
3627 break;
3628 case HImode:
3629 shift_mode = HIshift;
3630 break;
3631 case SImode:
3632 shift_mode = SIshift;
3633 break;
3634 default:
3635 abort ();
3636 }
3637
3638 switch (code)
3639 {
3640 case ASHIFTRT:
3641 shift_type = SHIFT_ASHIFTRT;
3642 break;
3643 case LSHIFTRT:
3644 shift_type = SHIFT_LSHIFTRT;
3645 break;
3646 case ASHIFT:
3647 shift_type = SHIFT_ASHIFT;
3648 break;
3649 default:
3650 abort ();
3651 }
3652
3653 if (GET_CODE (operands[2]) != CONST_INT)
3654 {
3655 /* Get the assembler code to do one shift. */
3656 get_shift_alg (shift_type, shift_mode, 1, &info);
3657
3658 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3659 }
3660 else
3661 {
3662 int n = INTVAL (operands[2]);
3663
3664 /* If the count is negative, make it 0. */
3665 if (n < 0)
3666 n = 0;
3667 /* If the count is too big, truncate it.
3668 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3669 do the intuitive thing. */
3670 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3671 n = GET_MODE_BITSIZE (mode);
3672
3673 get_shift_alg (shift_type, shift_mode, n, &info);
3674
3675 switch (info.alg)
3676 {
3677 case SHIFT_SPECIAL:
3678 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 3679
3680 /* Every assembly instruction used in SHIFT_SPECIAL case
3681 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3682 see xor.l, we just pretend that xor.l counts as two insns
3683 so that the insn length will be computed correctly. */
3684 if (strstr (info.special, "xor.l") != NULL)
3685 wlength++;
3686
86855e8c
KH		 3687 /* Fall through. */
3688
3689 case SHIFT_INLINE:
3690 n = info.remainder;
3691
3692 if (info.shift2 != NULL)
3693 {
3694 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3695 n = n % 2;
3696 }
3697
3698 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 3699
86855e8c
KH		 3700 return 2 * wlength;
3701
3702 case SHIFT_ROT_AND:
3703 {
3704 int m = GET_MODE_BITSIZE (mode) - n;
3705
3706 /* Not all possibilities of rotate are supported. They shouldn't
3707 be generated, but let's watch for 'em. */
3708 if (info.shift1 == 0)
3709 abort ();
3710
3711 if (info.shift2 != NULL)
3712 {
3713 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3714 m = m % 2;
3715 }
3716
3717 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 3718
86855e8c
KH		 3719 /* Now mask off the high bits. */
3720 switch (mode)
3721 {
3722 case QImode:
3723 wlength += 1;
3724 break;
3725 case HImode:
3726 wlength += 2;
3727 break;
3728 case SImode:
3729 if (TARGET_H8300)
3730 abort ();
3731 wlength += 3;
3732 break;
3733 default:
3734 abort ();
3735 }
3736 return 2 * wlength;
3737 }
3738
3739 case SHIFT_LOOP:
3740 /* A loop to shift by a "large" constant value.
3741 If we have shift-by-2 insns, use them. */
3742 if (info.shift2 != NULL)
3743 {
3744 wlength += 3 + h8300_asm_insn_count (info.shift2);
3745 if (n % 2)
3746 wlength += h8300_asm_insn_count (info.shift1);
3747 }
3748 else
3749 {
3750 wlength += 3 + h8300_asm_insn_count (info.shift1);
3751 }
3752 return 2 * wlength;
3753
3754 default:
3755 abort ();
3756 }
3757 }
3758}
45ca2106
KH		 3759
3760int
cb713a8d 3761compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 3762{
3763 rtx shift = operands[3];
3764 enum machine_mode mode = GET_MODE (shift);
3765 enum rtx_code code = GET_CODE (shift);
3766 enum shift_type shift_type;
3767 enum shift_mode shift_mode;
3768 struct shift_info info;
3769
3770 switch (mode)
3771 {
3772 case QImode:
3773 shift_mode = QIshift;
3774 break;
3775 case HImode:
3776 shift_mode = HIshift;
3777 break;
3778 case SImode:
3779 shift_mode = SIshift;
3780 break;
3781 default:
3782 abort ();
3783 }
3784
3785 switch (code)
3786 {
3787 case ASHIFTRT:
3788 shift_type = SHIFT_ASHIFTRT;
3789 break;
3790 case LSHIFTRT:
3791 shift_type = SHIFT_LSHIFTRT;
3792 break;
3793 case ASHIFT:
3794 shift_type = SHIFT_ASHIFT;
3795 break;
3796 default:
3797 abort ();
3798 }
3799
3800 if (GET_CODE (operands[2]) != CONST_INT)
3801 {
3802 /* This case must be taken care of by one of the two splitters
3803 that convert a variable shift into a loop. */
3804 abort ();
3805 }
3806 else
3807 {
3808 int n = INTVAL (operands[2]);
3809
3810 /* If the count is negative, make it 0. */
3811 if (n < 0)
3812 n = 0;
3813 /* If the count is too big, truncate it.
3814 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3815 do the intuitive thing. */
3816 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3817 n = GET_MODE_BITSIZE (mode);
3818
3819 get_shift_alg (shift_type, shift_mode, n, &info);
3820
3821 switch (info.alg)
3822 {
3823 case SHIFT_SPECIAL:
3824 if (info.remainder == 0)
3825 return info.cc_special;
3826
3827 /* Fall through. */
3828
3829 case SHIFT_INLINE:
3830 return info.cc_inline;
3831
3832 case SHIFT_ROT_AND:
3833 /* This case always ends with an and instruction. */
3834 return CC_SET_ZNV;
3835
3836 case SHIFT_LOOP:
3837 /* A loop to shift by a "large" constant value.
3838 If we have shift-by-2 insns, use them. */
3839 if (info.shift2 != NULL)
3840 {
3841 if (n % 2)
3842 return info.cc_inline;
3843 }
3844 return CC_CLOBBER;
3845
3846 default:
3847 abort ();
3848 }
3849 }
3850}
48837e29 3851\f
edd71f0f
KH		 3852/* A rotation by a non-constant will cause a loop to be generated, in
3853 which a rotation by one bit is used. A rotation by a constant,
3854 including the one in the loop, will be taken care of by
caf7f21a 3855 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 3856
3857int
cb713a8d 3858expand_a_rotate (enum rtx_code code, rtx operands[])
edd71f0f
KH		 3859{
3860 rtx dst = operands[0];
3861 rtx src = operands[1];
3862 rtx rotate_amount = operands[2];
3863 enum machine_mode mode = GET_MODE (dst);
3864 rtx tmp;
3865
3866 /* We rotate in place. */
3867 emit_move_insn (dst, src);
3868
3869 if (GET_CODE (rotate_amount) != CONST_INT)
3870 {
3871 rtx counter = gen_reg_rtx (QImode);
3872 rtx start_label = gen_label_rtx ();
3873 rtx end_label = gen_label_rtx ();
3874
3875 /* If the rotate amount is less than or equal to 0,
3876 we go out of the loop. */
a556fd39 3877 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 3878 QImode, 0, end_label);
edd71f0f
KH		 3879
3880 /* Initialize the loop counter. */
3881 emit_move_insn (counter, rotate_amount);
3882
3883 emit_label (start_label);
3884
3885 /* Rotate by one bit. */
a556fd39 3886 tmp = gen_rtx_fmt_ee (code, mode, dst, const1_rtx);
edd71f0f
KH		 3887 emit_insn (gen_rtx_SET (mode, dst, tmp));
3888
3889 /* Decrement the counter by 1. */
a556fd39 3890 tmp = gen_rtx_PLUS (QImode, counter, constm1_rtx);
edd71f0f
KH		 3891 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3892
9cd10576 3893 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 3894 of the loop. */
a556fd39 3895 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 3896 start_label);
edd71f0f
KH		 3897
3898 emit_label (end_label);
3899 }
3900 else
3901 {
3902 /* Rotate by AMOUNT bits. */
1c563bed 3903 tmp = gen_rtx_fmt_ee (code, mode, dst, rotate_amount);
edd71f0f
KH		 3904 emit_insn (gen_rtx_SET (mode, dst, tmp));
3905 }
3906
3907 return 1;
3908}
3909
caf7f21a 3910/* Output rotate insns. */
edd71f0f
KH		 3911
3912const char *
caf7f21a 3913output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 3914{
3915 rtx dst = operands[0];
3916 rtx rotate_amount = operands[2];
3917 enum shift_mode rotate_mode;
3918 enum shift_type rotate_type;
3919 const char *insn_buf;
3920 int bits;
3921 int amount;
3922 enum machine_mode mode = GET_MODE (dst);
3923
3924 if (GET_CODE (rotate_amount) != CONST_INT)
3925 abort ();
3926
3927 switch (mode)
3928 {
3929 case QImode:
3930 rotate_mode = QIshift;
3931 break;
3932 case HImode:
3933 rotate_mode = HIshift;
3934 break;
3935 case SImode:
3936 rotate_mode = SIshift;
3937 break;
3938 default:
3939 abort ();
3940 }
3941
3942 switch (code)
3943 {
3944 case ROTATERT:
3945 rotate_type = SHIFT_ASHIFT;
3946 break;
3947 case ROTATE:
3948 rotate_type = SHIFT_LSHIFTRT;
3949 break;
3950 default:
3951 abort ();
3952 }
3953
3954 amount = INTVAL (rotate_amount);
3955
3956 /* Clean up AMOUNT. */
3957 if (amount < 0)
3958 amount = 0;
3959 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3960 amount = GET_MODE_BITSIZE (mode);
3961
3962 /* Determine the faster direction. After this phase, amount will be
3963 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 3964 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 3965 {
3966 /* Flip the direction. */
3967 amount = GET_MODE_BITSIZE (mode) - amount;
3968 rotate_type =
3969 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3970 }
3971
3972 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3973 boost up the rotation. */
3974 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3975 || (mode == HImode && TARGET_H8300H && amount >= 6)
3976 || (mode == HImode && TARGET_H8300S && amount == 8)
3977 || (mode == SImode && TARGET_H8300H && amount >= 10)
3978 || (mode == SImode && TARGET_H8300S && amount >= 13))
3979 {
3980 switch (mode)
3981 {
3982 case HImode:
3983 /* This code works on any family. */
3984 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3985 output_asm_insn (insn_buf, operands);
3986 break;
3987
3988 case SImode:
3db11b5c 3989 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 3990 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3991 output_asm_insn (insn_buf, operands);
3992 break;
3993
3994 default:
3995 abort ();
3996 }
3997
3998 /* Adjust AMOUNT and flip the direction. */
3999 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4000 rotate_type =
4001 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4002 }
4003
4004 /* Emit rotate insns. */
4005 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4006 {
4007 if (bits == 2)
4008 insn_buf = rotate_two[rotate_type][rotate_mode];
4009 else
4010 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 4011
edd71f0f
KH		 4012 for (; amount >= bits; amount -= bits)
4013 output_asm_insn (insn_buf, operands);
4014 }
4015
4016 return "";
4017}
caf7f21a
KH		 4018
4019unsigned int
4020compute_a_rotate_length (rtx *operands)
4021{
4022 rtx src = operands[1];
343fd2c7 4023 rtx amount_rtx = operands[2];
caf7f21a
KH		 4024 enum machine_mode mode = GET_MODE (src);
4025 int amount;
4026 unsigned int length = 0;
4027
343fd2c7
KH		 4028 if (GET_CODE (amount_rtx) != CONST_INT)
4029 abort ();
caf7f21a 4030
343fd2c7 4031 amount = INTVAL (amount_rtx);
caf7f21a
KH		 4032
4033 /* Clean up AMOUNT. */
4034 if (amount < 0)
4035 amount = 0;
4036 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4037 amount = GET_MODE_BITSIZE (mode);
4038
4039 /* Determine the faster direction. After this phase, amount
4040 will be at most a half of GET_MODE_BITSIZE (mode). */
4041 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4042 /* Flip the direction. */
4043 amount = GET_MODE_BITSIZE (mode) - amount;
4044
4045 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4046 boost up the rotation. */
4047 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4048 || (mode == HImode && TARGET_H8300H && amount >= 6)
4049 || (mode == HImode && TARGET_H8300S && amount == 8)
4050 || (mode == SImode && TARGET_H8300H && amount >= 10)
4051 || (mode == SImode && TARGET_H8300S && amount >= 13))
4052 {
4053 /* Adjust AMOUNT and flip the direction. */
4054 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4055 length += 6;
4056 }
4057
4058 /* We use 2-bit rotations on the H8S. */
4059 if (TARGET_H8300S)
4060 amount = amount / 2 + amount % 2;
4061
4062 /* The H8/300 uses three insns to rotate one bit, taking 6
4063 length. */
4064 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4065
4066 return length;
4067}
edd71f0f 4068\f
48837e29 4069/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 4070 operating insn. */
07aae5c2
SC		 4071
4072int
4093985c 4073fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 4074{
abc95ed3 4075 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 4076 only 'U' memory afterwards, so if this is a MEM operand, we must force
4077 it to be valid for 'U' by reloading the address. */
07aae5c2 4078
4093985c
KH		 4079 if (code == AND
4080 ? single_zero_operand (operands[2], QImode)
4081 : single_one_operand (operands[2], QImode))
07aae5c2 4082 {
2e760b15
KH		 4083 /* OK to have a memory dest. */
4084 if (GET_CODE (operands[0]) == MEM
4085 && !EXTRA_CONSTRAINT (operands[0], 'U'))
48837e29 4086 {
2e760b15
KH		 4087 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4088 copy_to_mode_reg (Pmode,
4089 XEXP (operands[0], 0)));
4090 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4091 operands[0] = mem;
4092 }
48837e29 4093
2e760b15
KH		 4094 if (GET_CODE (operands[1]) == MEM
4095 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4096 {
4097 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4098 copy_to_mode_reg (Pmode,
4099 XEXP (operands[1], 0)));
4100 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4101 operands[1] = mem;
48837e29 4102 }
2e760b15 4103 return 0;
48837e29 4104 }
07aae5c2 4105
48837e29 4106 /* Dest and src op must be register. */
07aae5c2 4107
48837e29
DE		 4108 operands[1] = force_reg (QImode, operands[1]);
4109 {
4110 rtx res = gen_reg_rtx (QImode);
fd57a6e4 4111 switch (code)
a3579575
KH		 4112 {
4113 case AND:
4114 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4115 break;
4116 case IOR:
4117 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4118 break;
4119 case XOR:
4120 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4121 break;
4122 default:
4123 abort ();
4124 }
4125 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 4126 }
4127 return 1;
07aae5c2 4128}
f5b65a56 4129
f5b65a56
JL		 4130/* Return nonzero if FUNC is an interrupt function as specified
4131 by the "interrupt" attribute. */
4132
4133static int
cb713a8d 4134h8300_interrupt_function_p (tree func)
f5b65a56
JL		 4135{
4136 tree a;
4137
4138 if (TREE_CODE (func) != FUNCTION_DECL)
4139 return 0;
4140
91d231cb 4141 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4142 return a != NULL_TREE;
4143}
4144
3cfa3702
KH		 4145/* Return nonzero if FUNC is a saveall function as specified by the
4146 "saveall" attribute. */
4147
4148static int
4149h8300_saveall_function_p (tree func)
4150{
4151 tree a;
4152
4153 if (TREE_CODE (func) != FUNCTION_DECL)
4154 return 0;
4155
4156 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4157 return a != NULL_TREE;
4158}
4159
fabe72bb
JL		 4160/* Return nonzero if FUNC is an OS_Task function as specified
4161 by the "OS_Task" attribute. */
4162
4163static int
cb713a8d 4164h8300_os_task_function_p (tree func)
fabe72bb
JL		 4165{
4166 tree a;
4167
4168 if (TREE_CODE (func) != FUNCTION_DECL)
4169 return 0;
4170
91d231cb 4171 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4172 return a != NULL_TREE;
4173}
4174
4175/* Return nonzero if FUNC is a monitor function as specified
4176 by the "monitor" attribute. */
4177
4178static int
cb713a8d 4179h8300_monitor_function_p (tree func)
fabe72bb
JL		 4180{
4181 tree a;
4182
4183 if (TREE_CODE (func) != FUNCTION_DECL)
4184 return 0;
4185
91d231cb 4186 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4187 return a != NULL_TREE;
4188}
4189
f5b65a56
JL		 4190/* Return nonzero if FUNC is a function that should be called
4191 through the function vector. */
4192
4193int
cb713a8d 4194h8300_funcvec_function_p (tree func)
f5b65a56
JL		 4195{
4196 tree a;
4197
4198 if (TREE_CODE (func) != FUNCTION_DECL)
4199 return 0;
4200
91d231cb 4201 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4202 return a != NULL_TREE;
4203}
4204
887a8bd9 4205/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 4206 data area. */
4207
4208int
cb713a8d 4209h8300_eightbit_data_p (tree decl)
15dc331e
JL		 4210{
4211 tree a;
4212
4213 if (TREE_CODE (decl) != VAR_DECL)
4214 return 0;
4215
91d231cb 4216 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 4217 return a != NULL_TREE;
4218}
4219
887a8bd9
JL		 4220/* Return nonzero if DECL is a variable that's in the tiny
4221 data area. */
4222
4223int
cb713a8d 4224h8300_tiny_data_p (tree decl)
887a8bd9
JL		 4225{
4226 tree a;
4227
4228 if (TREE_CODE (decl) != VAR_DECL)
4229 return 0;
4230
91d231cb 4231 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 4232 return a != NULL_TREE;
4233}
4234
3cfa3702
KH		 4235/* Generate an 'interrupt_handler' attribute for decls. We convert
4236 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 4237
4238static void
cb713a8d 4239h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 4240{
3cfa3702
KH		 4241 if (TREE_CODE (node) == FUNCTION_DECL)
4242 {
4243 if (pragma_interrupt)
4244 {
4245 pragma_interrupt = 0;
2c1d2fcb 4246
3cfa3702
KH		 4247 /* Add an 'interrupt_handler' attribute. */
4248 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4249 NULL, *attributes);
4250 }
e392d367 4251
3cfa3702
KH		 4252 if (pragma_saveall)
4253 {
4254 pragma_saveall = 0;
4255
4256 /* Add an 'saveall' attribute. */
4257 *attributes = tree_cons (get_identifier ("saveall"),
4258 NULL, *attributes);
4259 }
4260 }
2c1d2fcb
DD		 4261}
4262
91d231cb 4263/* Supported attributes:
f5b65a56 4264
97c5ec1d 4265 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 4266 interrupt handler.
4267
3cfa3702
KH		 4268 saveall: output a prologue and epilogue that saves and restores
4269 all registers except the stack pointer.
4270
97c5ec1d 4271 function_vector: This function should be called through the
887a8bd9
JL		 4272 function vector.
4273
4274 eightbit_data: This variable lives in the 8-bit data area and can
4275 be referenced with 8-bit absolute memory addresses.
4276
4277 tiny_data: This variable lives in the tiny data area and can be
4278 referenced with 16-bit absolute memory references. */
f5b65a56 4279
91d231cb 4280const struct attribute_spec h8300_attribute_table[] =
f5b65a56 4281{
91d231cb
JM		 4282 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4283 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3cfa3702 4284 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
91d231cb
JM		 4285 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4286 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4287 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4288 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4289 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4290 { NULL, 0, 0, false, false, false, NULL }
4291};
f5b65a56 4292
15dc331e 4293
91d231cb
JM		 4294/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4295 struct attribute_spec.handler. */
4296static tree
cb713a8d
KH		 4297h8300_handle_fndecl_attribute (tree *node, tree name,
4298 tree args ATTRIBUTE_UNUSED,
4299 int flags ATTRIBUTE_UNUSED,
4300 bool *no_add_attrs)
91d231cb
JM		 4301{
4302 if (TREE_CODE (*node) != FUNCTION_DECL)
4303 {
4304 warning ("`%s' attribute only applies to functions",
4305 IDENTIFIER_POINTER (name));
4306 *no_add_attrs = true;
4307 }
4308
4309 return NULL_TREE;
4310}
4311
4312/* Handle an "eightbit_data" attribute; arguments as in
4313 struct attribute_spec.handler. */
4314static tree
cb713a8d
KH		 4315h8300_handle_eightbit_data_attribute (tree *node, tree name,
4316 tree args ATTRIBUTE_UNUSED,
4317 int flags ATTRIBUTE_UNUSED,
4318 bool *no_add_attrs)
91d231cb
JM		 4319{
4320 tree decl = *node;
4321
4322 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 4323 {
64378c91 4324 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
91d231cb
JM		 4325 }
4326 else
4327 {
4328 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4329 *no_add_attrs = true;
887a8bd9
JL		 4330 }
4331
91d231cb
JM		 4332 return NULL_TREE;
4333}
4334
4335/* Handle an "tiny_data" attribute; arguments as in
4336 struct attribute_spec.handler. */
4337static tree
cb713a8d
KH		 4338h8300_handle_tiny_data_attribute (tree *node, tree name,
4339 tree args ATTRIBUTE_UNUSED,
4340 int flags ATTRIBUTE_UNUSED,
4341 bool *no_add_attrs)
91d231cb
JM		 4342{
4343 tree decl = *node;
4344
4345 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 4346 {
64378c91 4347 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
91d231cb
JM		 4348 }
4349 else
4350 {
4351 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4352 *no_add_attrs = true;
15dc331e 4353 }
07e4d94e 4354
91d231cb 4355 return NULL_TREE;
f5b65a56
JL		 4356}
4357
dc66a1c4 4358/* Mark function vectors, and various small data objects. */
fb49053f
RH		 4359
4360static void
cb713a8d 4361h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 4362{
dc66a1c4
RH		 4363 int extra_flags = 0;
4364
c6a2438a 4365 default_encode_section_info (decl, rtl, first);
dc66a1c4 4366
fb49053f
RH		 4367 if (TREE_CODE (decl) == FUNCTION_DECL
4368 && h8300_funcvec_function_p (decl))
dc66a1c4 4369 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 4370 else if (TREE_CODE (decl) == VAR_DECL
4371 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4372 {
4373 if (h8300_eightbit_data_p (decl))
dc66a1c4 4374 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 4375 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 4376 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 4377 }
772c5265 4378
dc66a1c4 4379 if (extra_flags)
c6a2438a 4380 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 4381}
4382
441d04c6 4383const char *
cb713a8d 4384output_simode_bld (int bild, rtx operands[])
bd93f126 4385{
6be580c7
KH		 4386 if (TARGET_H8300)
4387 {
4388 /* Clear the destination register. */
4389 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4390
4391 /* Now output the bit load or bit inverse load, and store it in
4392 the destination. */
4393 if (bild)
4394 output_asm_insn ("bild\t%Z2,%Y1", operands);
4395 else
4396 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 4397
6be580c7
KH		 4398 output_asm_insn ("bst\t#0,%w0", operands);
4399 }
bd93f126 4400 else
6be580c7 4401 {
0eb933a0
KH		 4402 /* Determine if we can clear the destination first. */
4403 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4404 && REGNO (operands[0]) != REGNO (operands[1]));
4405
4406 if (clear_first)
4407 output_asm_insn ("sub.l\t%S0,%S0", operands);
4408
6be580c7
KH		 4409 /* Output the bit load or bit inverse load. */
4410 if (bild)
4411 output_asm_insn ("bild\t%Z2,%Y1", operands);
4412 else
4413 output_asm_insn ("bld\t%Z2,%Y1", operands);
4414
0eb933a0
KH		 4415 if (!clear_first)
4416 output_asm_insn ("xor.l\t%S0,%S0", operands);
4417
4418 /* Perform the bit store. */
802a9907 4419 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 4420 }
bd93f126
JL		 4421
4422 /* All done. */
4423 return "";
4424}
e6219736 4425
ede75ee8 4426#ifndef OBJECT_FORMAT_ELF
7c262518 4427static void
cb713a8d 4428h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
7c262518
RH		 4429{
4430 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4431 fprintf (asm_out_file, "\t.section %s\n", name);
4432}
ede75ee8 4433#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 4434
7c143ed2
KH		 4435/* Nonzero if X is a constant address suitable as an 8-bit absolute,
4436 which is a special case of the 'R' operand. */
4437
803d56f5 4438int
cb713a8d 4439h8300_eightbit_constant_address_p (rtx x)
803d56f5 4440{
ff482c8d 4441 /* The ranges of the 8-bit area. */
d2d199a3
KH		 4442 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4443 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 4444 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4445 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4446 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4447 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4448
4449 unsigned HOST_WIDE_INT addr;
4450
9675a91e 4451 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 4452 if (GET_CODE (x) == SYMBOL_REF)
4453 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 4454
803d56f5
KH		 4455 if (GET_CODE (x) != CONST_INT)
4456 return 0;
4457
4458 addr = INTVAL (x);
4459
4460 return (0
39ba95b5 4461 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 4462 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4463 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4464}
4465
7c143ed2
KH		 4466/* Nonzero if X is a constant address suitable as an 16-bit absolute
4467 on H8/300H and H8S. */
4468
803d56f5 4469int
cb713a8d 4470h8300_tiny_constant_address_p (rtx x)
803d56f5 4471{
3f7211f1 4472 /* The ranges of the 16-bit area. */
803d56f5
KH		 4473 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4474 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4475 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4476 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4477 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4478 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4479 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4480 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4481
4482 unsigned HOST_WIDE_INT addr;
4483
d6456562
KH		 4484 switch (GET_CODE (x))
4485 {
4486 case SYMBOL_REF:
a4bb41cc
KH		 4487 /* In the normal mode, any symbol fits in the 16-bit absolute
4488 address range. We also accept symbols declared with
4489 tiny_data. */
4490 return (TARGET_NORMAL_MODE
4491 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 4492
d6456562
KH		 4493 case CONST_INT:
4494 addr = INTVAL (x);
4495 return (TARGET_NORMAL_MODE
4496 || (TARGET_H8300H
4497 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4498 || (TARGET_H8300S
4499 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 4500
a4bb41cc
KH		 4501 case CONST:
4502 return TARGET_NORMAL_MODE;
4503
d6456562
KH		 4504 default:
4505 return 0;
4506 }
803d56f5 4507
803d56f5 4508}
9b98dc74
KH		 4509
4510int
cb713a8d 4511byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 4512{
4513 HOST_WIDE_INT offset1, offset2;
4514 rtx reg1, reg2;
4515
4516 if (REG_P (addr1))
4517 {
4518 reg1 = addr1;
4519 offset1 = 0;
4520 }
4521 else if (GET_CODE (addr1) == PLUS
4522 && REG_P (XEXP (addr1, 0))
4523 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4524 {
4525 reg1 = XEXP (addr1, 0);
4526 offset1 = INTVAL (XEXP (addr1, 1));
4527 }
4528 else
4529 return 0;
4530
4531 if (REG_P (addr2))
4532 {
4533 reg2 = addr2;
4534 offset2 = 0;
4535 }
4536 else if (GET_CODE (addr2) == PLUS
4537 && REG_P (XEXP (addr2, 0))
4538 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4539 {
4540 reg2 = XEXP (addr2, 0);
4541 offset2 = INTVAL (XEXP (addr2, 1));
4542 }
4543 else
4544 return 0;
4545
4546 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4547 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4548 && offset1 % 2 == 0
4549 && offset1 + 1 == offset2)
4550 return 1;
4551
4552 return 0;
4553}
02529902
KH		 4554
4555/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 4556 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 4557
4558int
4559same_cmp_preceding_p (rtx i3)
4560{
4561 rtx i1, i2;
4562
4563 /* Make sure we have a sequence of three insns. */
4564 i2 = prev_nonnote_insn (i3);
4565 if (i2 == NULL_RTX)
4566 return 0;
4567 i1 = prev_nonnote_insn (i2);
4568 if (i1 == NULL_RTX)
4569 return 0;
4570
4571 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4572 && any_condjump_p (i2) && onlyjump_p (i2));
4573}
c87ec0ba 4574
c06d5c85
KH		 4575/* Return nonzero if we have the same comparison insn as I1 two insns
4576 after I1. I1 is assumed to be a comparison insn. */
4577
4578int
4579same_cmp_following_p (rtx i1)
4580{
4581 rtx i2, i3;
4582
4583 /* Make sure we have a sequence of three insns. */
4584 i2 = next_nonnote_insn (i1);
4585 if (i2 == NULL_RTX)
4586 return 0;
4587 i3 = next_nonnote_insn (i2);
4588 if (i3 == NULL_RTX)
4589 return 0;
4590
4591 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4592 && any_condjump_p (i2) && onlyjump_p (i2));
4593}
4594
a466bea3
KH		 4595/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
4596 (or pops) N registers. OPERANDS are asssumed to be an array of
4597 registers. */
4598
4599int
4600h8300_regs_ok_for_stm (int n, rtx operands[])
4601{
4602 switch (n)
4603 {
4604 case 2:
4605 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4606 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4607 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
4608 case 3:
4609 return ((REGNO (operands[0]) == 0
4610 && REGNO (operands[1]) == 1
4611 && REGNO (operands[2]) == 2)
4612 || (REGNO (operands[0]) == 4
4613 && REGNO (operands[1]) == 5
4614 && REGNO (operands[2]) == 6));
4615
4616 case 4:
4617 return (REGNO (operands[0]) == 0
4618 && REGNO (operands[1]) == 1
4619 && REGNO (operands[2]) == 2
4620 && REGNO (operands[3]) == 3);
4621 }
4622
4623 abort ();
4624}
4625
c87ec0ba
NY		 4626/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4627
4628int
4629h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4630 unsigned int new_reg)
4631{
4632 /* Interrupt functions can only use registers that have already been
4633 saved by the prologue, even if they would normally be
4634 call-clobbered. */
4635
4636 if (h8300_current_function_interrupt_function_p ()
4637 && !regs_ever_live[new_reg])
4638 return 0;
4639
80e58519 4640 return 1;
c87ec0ba 4641}
d0022200
KH		 4642
4643/* Return nonzero if X is a legitimate constant. */
4644
4645int
4646h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4647{
4648 return 1;
4649}
4650
4651/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4652
4653static int
4654h8300_rtx_ok_for_base_p (rtx x, int strict)
4655{
4656 /* Strip off SUBREG if any. */
4657 if (GET_CODE (x) == SUBREG)
4658 x = SUBREG_REG (x);
4659
4660 return (REG_P (x)
4661 && (strict
4662 ? REG_OK_FOR_BASE_STRICT_P (x)
4663 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4664}
4665
4666/* Return nozero if X is a legitimate address. On the H8/300, a
4667 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4668 CONSTANT_ADDRESS. */
4669
4670int
4671h8300_legitimate_address_p (rtx x, int strict)
4672{
4673 /* The register indirect addresses like @er0 is always valid. */
4674 if (h8300_rtx_ok_for_base_p (x, strict))
4675 return 1;
4676
4677 if (CONSTANT_ADDRESS_P (x))
4678 return 1;
4679
4680 if (GET_CODE (x) == PLUS
4681 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4682 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4683 return 1;
4684
4685 return 0;
4686}
6e014ef3 4687\f
c15c90bb
ZW		 4688/* Perform target dependent optabs initialization. */
4689static void
4690h8300_init_libfuncs (void)
4691{
4692 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4693 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4694 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4695 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4696 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4697}
4698\f
34bf1fe3
KH		 4699static bool
4700h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4701{
4702 return (TYPE_MODE (type) == BLKmode
4703 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4704}
4705\f
6e014ef3
KH		 4706/* Initialize the GCC target structure. */
4707#undef TARGET_ATTRIBUTE_TABLE
4708#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4709
4710#undef TARGET_ASM_ALIGNED_HI_OP
4711#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4712
1bc7c5b6
ZW		 4713#undef TARGET_ASM_FILE_START
4714#define TARGET_ASM_FILE_START h8300_file_start
4715#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4716#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4717
6e014ef3
KH		 4718#undef TARGET_ASM_FILE_END
4719#define TARGET_ASM_FILE_END h8300_file_end
4720
4721#undef TARGET_ENCODE_SECTION_INFO
4722#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4723
4724#undef TARGET_INSERT_ATTRIBUTES
4725#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4726
4727#undef TARGET_RTX_COSTS
4728#define TARGET_RTX_COSTS h8300_rtx_costs
4729
c15c90bb
ZW		 4730#undef TARGET_INIT_LIBFUNCS
4731#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4732
34bf1fe3
KH		 4733#undef TARGET_RETURN_IN_MEMORY
4734#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4735
6e014ef3 4736struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git