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80e8bb90 1;; GCC machine description for MMX and 3dNOW! instructions
7adcbafe 2;; Copyright (C) 2005-2022 Free Software Foundation, Inc.
80e8bb90
RH		 3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
2f83c7d6 8;; the Free Software Foundation; either version 3, or (at your option)
80e8bb90
RH		 9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
80e8bb90
RH		 19
20;; The MMX and 3dNOW! patterns are in the same file because they use
21;; the same register file, and 3dNOW! adds a number of extensions to
22;; the base integer MMX isa.
23
4f3f76e6 24;; Note! Except for the basic move instructions, *all* of these
80e8bb90
RH		 25;; patterns are outside the normal optabs namespace. This is because
26;; use of these registers requires the insertion of emms or femms
27;; instructions to return to normal fpu mode. The compiler doesn't
28;; know how to do that itself, which means it's up to the user. Which
29;; means that we should never use any of these patterns except at the
30;; direction of the user via a builtin.
31
dc9945a4
UB		 32(define_c_enum "unspec" [
33 UNSPEC_MOVNTQ
34 UNSPEC_PFRCP
35 UNSPEC_PFRCPIT1
36 UNSPEC_PFRCPIT2
37 UNSPEC_PFRSQRT
38 UNSPEC_PFRSQIT1
39])
40
41(define_c_enum "unspecv" [
42 UNSPECV_EMMS
43 UNSPECV_FEMMS
44])
45
80e8bb90 46;; 8 byte integral modes handled by MMX (and by extension, SSE)
3abcb3a7 47(define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
1f0dc22a 48(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")])
80e8bb90
RH		 49
50;; All 8-byte vector modes handled by MMX
eea10afe 51(define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF V4HF])
b1f7fd8a 52(define_mode_iterator MMXMODE124 [V8QI V4HI V2SI V2SF])
80e8bb90
RH		 53
54;; Mix-n-match
3abcb3a7 55(define_mode_iterator MMXMODE12 [V8QI V4HI])
f3661f2d 56(define_mode_iterator MMXMODE14 [V8QI V2SI])
3abcb3a7 57(define_mode_iterator MMXMODE24 [V4HI V2SI])
10a97ae6 58(define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
80e8bb90 59
eea10afe
HW		 60;; All 4-byte integer/float16 vector modes
61(define_mode_iterator V_32 [V4QI V2HI V1SI V2HF])
663a014e
UB		 62
63;; 4-byte integer vector modes
46ca31d6
UB		 64(define_mode_iterator VI_32 [V4QI V2HI])
65
663a014e 66;; V2S* modes
b1f7fd8a
UB		 67(define_mode_iterator V2FI [V2SF V2SI])
68
eea10afe
HW		 69;; 4-byte and 8-byte float16 vector modes
70(define_mode_iterator VHF_32_64 [V4HF V2HF])
71
80e8bb90 72;; Mapping from integer vector mode to mnemonic suffix
46ca31d6
UB		 73(define_mode_attr mmxvecsize
74 [(V8QI "b") (V4QI "b") (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
80e8bb90 75
94538b65
UB		 76(define_mode_attr mmxdoublemode
77 [(V8QI "V8HI") (V4HI "V4SI")])
78
b1f7fd8a
UB		 79;; Mapping of vector float modes to an integer mode of the same size
80(define_mode_attr mmxintvecmode
81 [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")])
82
83(define_mode_attr mmxintvecmodelower
84 [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")])
85
3bb345c9 86(define_mode_attr Yv_Yw
507359e1 87 [(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")])
3bb345c9 88
80e8bb90
RH		 89;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
90;;
91;; Move patterns
92;;
93;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
94
95;; All of these patterns are enabled for MMX as well as 3dNOW.
96;; This is essential for maintaining stable calling conventions.
97
98(define_expand "mov<mode>"
2cd9804e
UB		 99 [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
100 (match_operand:MMXMODE 1 "nonimmediate_operand"))]
e093d046 101 "TARGET_MMX || TARGET_MMX_WITH_SSE"
80e8bb90
RH		 102{
103 ix86_expand_vector_move (<MODE>mode, operands);
104 DONE;
105})
106
bed852cf 107(define_insn "*mov<mode>_internal"
2cd9804e 108 [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
b1ea8387 109 "=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!y,v,v,v,m,r,v,!y,*x")
808d8de5 110 (match_operand:MMXMODE 1 "nonimm_or_0_operand"
b1ea8387 111 "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))]
e093d046 112 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
7656aee4 113 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
bed852cf
UB		 114{
115 switch (get_attr_type (insn))
116 {
117 case TYPE_MULTI:
118 return "#";
119
120 case TYPE_IMOV:
121 if (get_attr_mode (insn) == MODE_SI)
122 return "mov{l}\t{%1, %k0|%k0, %1}";
123 else
124 return "mov{q}\t{%1, %0|%0, %1}";
125
126 case TYPE_MMX:
127 return "pxor\t%0, %0";
128
129 case TYPE_MMXMOV:
bed852cf 130 /* Handle broken assemblers that require movd instead of movq. */
13a26a7d
UB		 131 if (!HAVE_AS_IX86_INTERUNIT_MOVQ
132 && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
bed852cf 133 return "movd\t{%1, %0|%0, %1}";
bed852cf
UB		 134 return "movq\t{%1, %0|%0, %1}";
135
136 case TYPE_SSECVT:
137 if (SSE_REG_P (operands[0]))
138 return "movq2dq\t{%1, %0|%0, %1}";
139 else
140 return "movdq2q\t{%1, %0|%0, %1}";
141
142 case TYPE_SSELOG1:
3b5e1089 143 return standard_sse_constant_opcode (insn, operands);
bed852cf
UB		 144
145 case TYPE_SSEMOV:
54f46d82 146 return ix86_output_ssemov (insn, operands);
bed852cf
UB		 147
148 default:
149 gcc_unreachable ();
150 }
151}
152 [(set (attr "isa")
ba94c7af 153 (cond [(eq_attr "alternative" "0,1")
bed852cf 154 (const_string "nox64")
b1ea8387 155 (eq_attr "alternative" "2,3,4,9,10")
bed852cf 156 (const_string "x64")
b1ea8387
UB		 157 (eq_attr "alternative" "15,16")
158 (const_string "x64_sse2")
159 (eq_attr "alternative" "17,18")
160 (const_string "sse2")
bed852cf
UB		 161 ]
162 (const_string "*")))
163 (set (attr "type")
164 (cond [(eq_attr "alternative" "0,1")
165 (const_string "multi")
166 (eq_attr "alternative" "2,3,4")
ba94c7af 167 (const_string "imov")
bed852cf 168 (eq_attr "alternative" "5")
ba94c7af 169 (const_string "mmx")
acef5fe0 170 (eq_attr "alternative" "6,7,8,9,10")
ba94c7af 171 (const_string "mmxmov")
e4171e10 172 (eq_attr "alternative" "11")
ba94c7af 173 (const_string "sselog1")
e4171e10 174 (eq_attr "alternative" "17,18")
bed852cf 175 (const_string "ssecvt")
ba94c7af
UB		 176 ]
177 (const_string "ssemov")))
725fd454 178 (set (attr "prefix_rex")
e4171e10 179 (if_then_else (eq_attr "alternative" "9,10,15,16")
bed852cf 180 (const_string "1")
725fd454 181 (const_string "*")))
95879c72 182 (set (attr "prefix")
bed852cf 183 (if_then_else (eq_attr "type" "sselog1,ssemov")
95879c72
L		 184 (const_string "maybe_vex")
185 (const_string "orig")))
4e938ce6
UB		 186 (set (attr "prefix_data16")
187 (if_then_else
bed852cf 188 (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
4e938ce6
UB		 189 (const_string "1")
190 (const_string "*")))
bed852cf
UB		 191 (set (attr "mode")
192 (cond [(eq_attr "alternative" "2")
193 (const_string "SI")
e4171e10 194 (eq_attr "alternative" "11,12")
54f46d82 195 (cond [(match_test "<MODE>mode == V2SFmode")
2cd9804e 196 (const_string "V4SF")
eea10afe
HW		 197 (match_test "<MODE>mode == V4HFmode")
198 (const_string "V4SF")
2cd9804e 199 (ior (not (match_test "TARGET_SSE2"))
828573a5 200 (match_test "optimize_function_for_size_p (cfun)"))
bed852cf
UB		 201 (const_string "V4SF")
202 ]
203 (const_string "TI"))
204
7c355156 205 (and (eq_attr "alternative" "13")
eea10afe
HW		 206 (ior (ior (and (match_test "<MODE>mode == V2SFmode")
207 (not (match_test "TARGET_MMX_WITH_SSE")))
208 (not (match_test "TARGET_SSE2")))
209 (match_test "<MODE>mode == V4HFmode")))
7c355156
UB		 210 (const_string "V2SF")
211
212 (and (eq_attr "alternative" "14")
eea10afe
HW		 213 (ior (ior (match_test "<MODE>mode == V2SFmode")
214 (not (match_test "TARGET_SSE2")))
215 (match_test "<MODE>mode == V4HFmode")))
bed852cf
UB		 216 (const_string "V2SF")
217 ]
b1ea8387
UB		 218 (const_string "DI")))
219 (set (attr "preferred_for_speed")
9bb3d6c4 220 (cond [(eq_attr "alternative" "9,15")
b1ea8387 221 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
9bb3d6c4 222 (eq_attr "alternative" "10,16")
b1ea8387
UB		 223 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
224 ]
225 (symbol_ref "true")))])
80e8bb90 226
eb701deb 227(define_split
cd3fe55a 228 [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
7be65e79
UB		 229 (match_operand:MMXMODE 1 "nonimmediate_gr_operand"))]
230 "!TARGET_64BIT && reload_completed"
231 [(const_int 0)]
232 "ix86_split_long_move (operands); DONE;")
233
234(define_split
235 [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
236 (match_operand:MMXMODE 1 "const0_operand"))]
cd3fe55a 237 "!TARGET_64BIT && reload_completed"
eb701deb
RH		 238 [(const_int 0)]
239 "ix86_split_long_move (operands); DONE;")
80e8bb90
RH		 240
241(define_expand "movmisalign<mode>"
82e86dc6
UB		 242 [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
243 (match_operand:MMXMODE 1 "nonimmediate_operand"))]
e093d046 244 "TARGET_MMX || TARGET_MMX_WITH_SSE"
80e8bb90
RH		 245{
246 ix86_expand_vector_move (<MODE>mode, operands);
247 DONE;
248})
249
46ca31d6 250(define_expand "mov<mode>"
663a014e
UB		 251 [(set (match_operand:V_32 0 "nonimmediate_operand")
252 (match_operand:V_32 1 "nonimmediate_operand"))]
46ca31d6
UB		 253 "TARGET_SSE2"
254{
255 ix86_expand_vector_move (<MODE>mode, operands);
256 DONE;
257})
258
259(define_insn "*mov<mode>_internal"
663a014e 260 [(set (match_operand:V_32 0 "nonimmediate_operand"
46ca31d6 261 "=r ,m ,v,v,v,m,r,v")
663a014e 262 (match_operand:V_32 1 "general_operand"
46ca31d6 263 "rmC,rC,C,v,m,v,v,r"))]
9ff206d3
UB		 264 "TARGET_SSE2
265 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
46ca31d6
UB		 266{
267 switch (get_attr_type (insn))
268 {
269 case TYPE_IMOV:
270 return "mov{l}\t{%1, %0|%0, %1}";
271
272 case TYPE_SSELOG1:
273 return standard_sse_constant_opcode (insn, operands);
274
275 case TYPE_SSEMOV:
276 return ix86_output_ssemov (insn, operands);
277
278 default:
279 gcc_unreachable ();
280 }
281}
282 [(set (attr "type")
283 (cond [(eq_attr "alternative" "2")
284 (const_string "sselog1")
285 (eq_attr "alternative" "3,4,5,6,7")
286 (const_string "ssemov")
287 ]
288 (const_string "imov")))
289 (set (attr "prefix")
290 (if_then_else (eq_attr "type" "sselog1,ssemov")
291 (const_string "maybe_vex")
292 (const_string "orig")))
293 (set (attr "prefix_data16")
294 (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
295 (const_string "1")
296 (const_string "*")))
297 (set (attr "mode")
298 (cond [(eq_attr "alternative" "2,3")
eea10afe
HW		 299 (cond [(match_test "<MODE>mode == V2HFmode")
300 (const_string "V4SF")
301 (match_test "TARGET_AVX")
46ca31d6
UB		 302 (const_string "TI")
303 (match_test "optimize_function_for_size_p (cfun)")
304 (const_string "V4SF")
305 ]
306 (const_string "TI"))
eea10afe
HW		 307 (and (eq_attr "alternative" "4,5")
308 (match_test "<MODE>mode == V2HFmode"))
309 (const_string "SF")
46ca31d6
UB		 310 ]
311 (const_string "SI")))
312 (set (attr "preferred_for_speed")
313 (cond [(eq_attr "alternative" "6")
314 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
315 (eq_attr "alternative" "7")
316 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
317 ]
318 (symbol_ref "true")))])
319
c01c4331
UB		 320;; For TARGET_64BIT we always round up to 8 bytes.
321(define_insn "*push<mode>2_rex64"
663a014e
UB		 322 [(set (match_operand:V_32 0 "push_operand" "=X,X")
323 (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))]
c01c4331
UB		 324 "TARGET_SSE2 && TARGET_64BIT"
325 "@
326 push{q}\t%q1
327 #"
328 [(set_attr "type" "push,multi")
329 (set_attr "mode" "DI")])
330
331(define_insn "*push<mode>2"
663a014e
UB		 332 [(set (match_operand:V_32 0 "push_operand" "=<,<")
333 (match_operand:V_32 1 "general_no_elim_operand" "rC*m,*v"))]
c01c4331
UB		 334 "TARGET_SSE2 && !TARGET_64BIT"
335 "@
336 push{l}\t%1
337 #"
338 [(set_attr "type" "push,multi")
339 (set_attr "mode" "SI")])
340
341(define_split
663a014e
UB		 342 [(set (match_operand:V_32 0 "push_operand")
343 (match_operand:V_32 1 "sse_reg_operand"))]
c01c4331
UB		 344 "TARGET_SSE2 && reload_completed"
345 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
346 (set (match_dup 0) (match_dup 1))]
347{
663a014e 348 operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<V_32:MODE>mode)));
c01c4331
UB		 349 /* Preserve memory attributes. */
350 operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
351})
352
46ca31d6 353(define_expand "movmisalign<mode>"
663a014e
UB		 354 [(set (match_operand:V_32 0 "nonimmediate_operand")
355 (match_operand:V_32 1 "nonimmediate_operand"))]
46ca31d6
UB		 356 "TARGET_SSE2"
357{
358 ix86_expand_vector_move (<MODE>mode, operands);
359 DONE;
360})
361
9ff206d3
UB		 362(define_expand "movv2qi"
363 [(set (match_operand:V2QI 0 "nonimmediate_operand")
364 (match_operand:V2QI 1 "nonimmediate_operand"))]
365 ""
366{
367 ix86_expand_vector_move (V2QImode, operands);
368 DONE;
369})
370
371(define_insn "*movv2qi_internal"
372 [(set (match_operand:V2QI 0 "nonimmediate_operand"
373 "=r,r,r,m ,v,v,v,m,r,v")
374 (match_operand:V2QI 1 "general_operand"
375 "r ,C,m,rC,C,v,m,v,v,r"))]
376 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
377{
378 switch (get_attr_type (insn))
379 {
380 case TYPE_IMOV:
381 if (get_attr_mode (insn) == MODE_SI)
382 return "mov{l}\t{%k1, %k0|%k0, %k1}";
383 else
384 return "mov{w}\t{%1, %0|%0, %1}";
385
386 case TYPE_IMOVX:
387 /* movzwl is faster than movw on p2 due to partial word stalls,
388 though not as fast as an aligned movl. */
389 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
390
391 case TYPE_SSELOG1:
392 if (satisfies_constraint_C (operands[1]))
393 return standard_sse_constant_opcode (insn, operands);
394
395 if (SSE_REG_P (operands[0]))
396 return MEM_P (operands[1])
397 ? "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}"
398 : "%vpinsrw\t{$0, %k1, %d0|%d0, %k1, 0}";
399 else
400 return MEM_P (operands[0])
401 ? "%vpextrw\t{$0, %1, %0|%0, %1, 0}"
402 : "%vpextrw\t{$0, %1, %k0|%k0, %1, 0}";
403
404 case TYPE_SSEMOV:
405 return ix86_output_ssemov (insn, operands);
406
407 default:
408 gcc_unreachable ();
409 }
410}
411 [(set (attr "isa")
412 (cond [(eq_attr "alternative" "4,5,6,8,9")
413 (const_string "sse2")
414 (eq_attr "alternative" "7")
415 (const_string "sse4")
416 ]
417 (const_string "*")))
418 (set (attr "type")
419 (cond [(eq_attr "alternative" "6,7,8,9")
420 (if_then_else (match_test "TARGET_AVX512FP16")
421 (const_string "ssemov")
422 (const_string "sselog1"))
423 (eq_attr "alternative" "4")
424 (const_string "sselog1")
425 (eq_attr "alternative" "5")
426 (const_string "ssemov")
427 (match_test "optimize_function_for_size_p (cfun)")
428 (const_string "imov")
429 (and (eq_attr "alternative" "0")
430 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
431 (not (match_test "TARGET_HIMODE_MATH"))))
432 (const_string "imov")
433 (and (eq_attr "alternative" "1,2")
434 (match_operand:V2QI 1 "aligned_operand"))
435 (const_string "imov")
436 (and (match_test "TARGET_MOVX")
437 (eq_attr "alternative" "0,2"))
438 (const_string "imovx")
439 ]
440 (const_string "imov")))
441 (set (attr "prefix")
442 (cond [(eq_attr "alternative" "4,5,6,7,8,9")
443 (const_string "maybe_evex")
444 ]
445 (const_string "orig")))
446 (set (attr "mode")
447 (cond [(eq_attr "alternative" "6,7,8,9")
448 (if_then_else (match_test "TARGET_AVX512FP16")
449 (const_string "HI")
450 (const_string "TI"))
451 (eq_attr "alternative" "4")
452 (cond [(match_test "TARGET_AVX")
453 (const_string "TI")
454 (ior (not (match_test "TARGET_SSE2"))
455 (match_test "optimize_function_for_size_p (cfun)"))
456 (const_string "V4SF")
457 ]
458 (const_string "TI"))
459 (eq_attr "alternative" "5")
460 (cond [(match_test "TARGET_AVX512FP16")
461 (const_string "HI")
462 (match_test "TARGET_AVX")
463 (const_string "TI")
464 (ior (not (match_test "TARGET_SSE2"))
465 (match_test "optimize_function_for_size_p (cfun)"))
466 (const_string "V4SF")
467 ]
468 (const_string "TI"))
469 (eq_attr "type" "imovx")
470 (const_string "SI")
471 (and (eq_attr "alternative" "1,2")
472 (match_operand:V2QI 1 "aligned_operand"))
473 (const_string "SI")
474 (and (eq_attr "alternative" "0")
475 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
476 (not (match_test "TARGET_HIMODE_MATH"))))
477 (const_string "SI")
478 ]
479 (const_string "HI")))
480 (set (attr "preferred_for_speed")
481 (cond [(eq_attr "alternative" "8")
482 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
483 (eq_attr "alternative" "9")
484 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
485 ]
486 (symbol_ref "true")))])
487
488;; We always round up to UNITS_PER_WORD bytes.
489(define_insn "*pushv2qi2"
490 [(set (match_operand:V2QI 0 "push_operand" "=X,X")
491 (match_operand:V2QI 1 "nonmemory_no_elim_operand" "rC,v"))]
492 ""
493 "* return TARGET_64BIT ? \"push{q}\t%q1\" : \"push{l}\t%k1\";
494 #"
495 [(set_attr "isa" "*,sse4")
496 (set_attr "type" "push,multi")
497 (set (attr "mode")
498 (cond [(eq_attr "alternative" "0")
499 (if_then_else (match_test "TARGET_64BIT")
500 (const_string "DI")
501 (const_string "SI"))
502 (eq_attr "alternative" "1")
503 (if_then_else (match_test "TARGET_AVX512FP16")
504 (const_string "HI")
505 (const_string "TI"))
506 ]
507 (const_string "HI")))])
508
509(define_split
510 [(set (match_operand:V2QI 0 "push_operand")
511 (match_operand:V2QI 1 "sse_reg_operand"))]
512 "TARGET_SSE4_1 && reload_completed"
513 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
514 (set (match_dup 0) (match_dup 1))]
515{
516 operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (V2QImode)));
517 /* Preserve memory attributes. */
518 operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
519})
520
521(define_expand "movmisalignv2qi"
522 [(set (match_operand:V2QI 0 "nonimmediate_operand")
523 (match_operand:V2QI 1 "nonimmediate_operand"))]
524 ""
525{
526 ix86_expand_vector_move (V2QImode, operands);
527 DONE;
528})
529
aa198500 530(define_insn "sse_movntq"
2ed7ae16
L		 531 [(set (match_operand:DI 0 "memory_operand" "=m,m")
532 (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
aa198500 533 UNSPEC_MOVNTQ))]
2ed7ae16
L		 534 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
535 && (TARGET_SSE || TARGET_3DNOW_A)"
536 "@
537 movntq\t{%1, %0|%0, %1}
538 movnti\t{%1, %0|%0, %1}"
b49ae8a5
UB		 539 [(set_attr "isa" "*,x64")
540 (set_attr "mmx_isa" "native,*")
2ed7ae16 541 (set_attr "type" "mmxmov,ssemov")
80e8bb90
RH		 542 (set_attr "mode" "DI")])
543
544;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
545;;
546;; Parallel single-precision floating point arithmetic
547;;
548;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
549
6416f672
UB		 550(define_expand "<code>v2sf2"
551 [(set (match_operand:V2SF 0 "register_operand")
552 (absneg:V2SF
553 (match_operand:V2SF 1 "register_operand")))]
554 "TARGET_MMX_WITH_SSE"
555 "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
556
557(define_insn_and_split "*mmx_<code>v2sf2"
7797f5ec 558 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
6416f672 559 (absneg:V2SF
7797f5ec
UB		 560 (match_operand:V2SF 1 "register_operand" "0,x,x")))
561 (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
6416f672
UB		 562 "TARGET_MMX_WITH_SSE"
563 "#"
564 "&& reload_completed"
565 [(set (match_dup 0)
566 (<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
7797f5ec
UB		 567{
568 if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
569 std::swap (operands[1], operands[2]);
570}
571 [(set_attr "isa" "noavx,noavx,avx")])
6416f672
UB		 572
573(define_insn_and_split "*mmx_nabsv2sf2"
7797f5ec 574 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
6416f672
UB		 575 (neg:V2SF
576 (abs:V2SF
7797f5ec
UB		 577 (match_operand:V2SF 1 "register_operand" "0,x,x"))))
578 (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
6416f672
UB		 579 "TARGET_MMX_WITH_SSE"
580 "#"
581 "&& reload_completed"
582 [(set (match_dup 0)
583 (ior:V2SF (match_dup 1) (match_dup 2)))]
7797f5ec
UB		 584{
585 if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
586 std::swap (operands[1], operands[2]);
587}
588 [(set_attr "isa" "noavx,noavx,avx")])
6416f672 589
333d8f61 590(define_expand "mmx_addv2sf3"
82e86dc6 591 [(set (match_operand:V2SF 0 "register_operand")
333d8f61 592 (plus:V2SF
7c355156
UB		 593 (match_operand:V2SF 1 "register_mmxmem_operand")
594 (match_operand:V2SF 2 "register_mmxmem_operand")))]
333d8f61
UB		 595 "TARGET_3DNOW"
596 "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
597
7c355156
UB		 598(define_expand "addv2sf3"
599 [(set (match_operand:V2SF 0 "register_operand")
600 (plus:V2SF
601 (match_operand:V2SF 1 "register_operand")
602 (match_operand:V2SF 2 "register_operand")))]
a617e5d5 603 "TARGET_MMX_WITH_SSE")
7c355156 604
d0b48c67 605(define_insn "*mmx_addv2sf3"
aa431786 606 [(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
7c355156 607 (plus:V2SF
aa431786
UB		 608 (match_operand:V2SF 1 "register_mmxmem_operand" "%0,0,v")
609 (match_operand:V2SF 2 "register_mmxmem_operand" "ym,x,v")))]
7c355156
UB		 610 "(TARGET_3DNOW || TARGET_MMX_WITH_SSE)
611 && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
612 "@
613 pfadd\t{%2, %0|%0, %2}
614 addps\t{%2, %0|%0, %2}
615 vaddps\t{%2, %1, %0|%0, %1, %2}"
616 [(set_attr "isa" "*,sse2_noavx,avx")
617 (set_attr "mmx_isa" "native,*,*")
618 (set_attr "type" "mmxadd,sseadd,sseadd")
619 (set_attr "prefix_extra" "1,*,*")
aa431786 620 (set_attr "prefix" "*,orig,vex")
7c355156 621 (set_attr "mode" "V2SF,V4SF,V4SF")])
80e8bb90 622
ffbaf337 623(define_expand "mmx_subv2sf3"
82e86dc6
UB		 624 [(set (match_operand:V2SF 0 "register_operand")
625 (minus:V2SF (match_operand:V2SF 1 "register_operand")
7c355156 626 (match_operand:V2SF 2 "register_mmxmem_operand")))]
a427621f 627 "TARGET_3DNOW")
ffbaf337
UB		 628
629(define_expand "mmx_subrv2sf3"
82e86dc6
UB		 630 [(set (match_operand:V2SF 0 "register_operand")
631 (minus:V2SF (match_operand:V2SF 2 "register_operand")
7c355156 632 (match_operand:V2SF 1 "register_mmxmem_operand")))]
a427621f 633 "TARGET_3DNOW")
ffbaf337 634
7c355156
UB		 635(define_expand "subv2sf3"
636 [(set (match_operand:V2SF 0 "register_operand")
637 (minus:V2SF
638 (match_operand:V2SF 1 "register_operand")
639 (match_operand:V2SF 2 "register_operand")))]
a617e5d5 640 "TARGET_MMX_WITH_SSE")
7c355156 641
ffbaf337 642(define_insn "*mmx_subv2sf3"
aa431786 643 [(set (match_operand:V2SF 0 "register_operand" "=y,y,x,v")
7c355156 644 (minus:V2SF
aa431786
UB		 645 (match_operand:V2SF 1 "register_mmxmem_operand" "0,ym,0,v")
646 (match_operand:V2SF 2 "register_mmxmem_operand" "ym,0,x,v")))]
7c355156
UB		 647 "(TARGET_3DNOW || TARGET_MMX_WITH_SSE)
648 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
80e8bb90 649 "@
333d8f61 650 pfsub\t{%2, %0|%0, %2}
7c355156
UB		 651 pfsubr\t{%1, %0|%0, %1}
652 subps\t{%2, %0|%0, %2}
653 vsubps\t{%2, %1, %0|%0, %1, %2}"
654 [(set_attr "isa" "*,*,sse2_noavx,avx")
655 (set_attr "mmx_isa" "native,native,*,*")
656 (set_attr "type" "mmxadd,mmxadd,sseadd,sseadd")
657 (set_attr "prefix_extra" "1,1,*,*")
aa431786 658 (set_attr "prefix" "*,*,orig,vex")
7c355156 659 (set_attr "mode" "V2SF,V2SF,V4SF,V4SF")])
80e8bb90 660
333d8f61 661(define_expand "mmx_mulv2sf3"
82e86dc6 662 [(set (match_operand:V2SF 0 "register_operand")
7c355156
UB		 663 (mult:V2SF (match_operand:V2SF 1 "register_mmxmem_operand")
664 (match_operand:V2SF 2 "register_mmxmem_operand")))]
333d8f61
UB		 665 "TARGET_3DNOW"
666 "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
667
7c355156
UB		 668(define_expand "mulv2sf3"
669 [(set (match_operand:V2SF 0 "register_operand")
670 (mult:V2SF
671 (match_operand:V2SF 1 "register_operand")
672 (match_operand:V2SF 2 "register_operand")))]
a617e5d5 673 "TARGET_MMX_WITH_SSE")
7c355156 674
d0b48c67 675(define_insn "*mmx_mulv2sf3"
aa431786 676 [(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
7c355156 677 (mult:V2SF
aa431786
UB		 678 (match_operand:V2SF 1 "register_mmxmem_operand" "%0,0,v")
679 (match_operand:V2SF 2 "register_mmxmem_operand" "ym,x,v")))]
7c355156
UB		 680 "(TARGET_3DNOW || TARGET_MMX_WITH_SSE)
681 && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
682 "@
683 pfmul\t{%2, %0|%0, %2}
684 mulps\t{%2, %0|%0, %2}
685 vmulps\t{%2, %1, %0|%0, %1, %2}"
686 [(set_attr "isa" "*,sse2_noavx,avx")
687 (set_attr "mmx_isa" "native,*,*")
688 (set_attr "type" "mmxmul,ssemul,ssemul")
7c355156 689 (set_attr "btver2_decode" "*,direct,double")
aa431786
UB		 690 (set_attr "prefix_extra" "1,*,*")
691 (set_attr "prefix" "*,orig,vex")
7c355156 692 (set_attr "mode" "V2SF,V4SF,V4SF")])
80e8bb90 693
8f921393
UB		 694(define_expand "divv2sf3"
695 [(set (match_operand:V2SF 0 "register_operand")
696 (div:V2SF (match_operand:V2SF 1 "register_operand")
697 (match_operand:V2SF 2 "register_operand")))]
698 "TARGET_MMX_WITH_SSE"
699{
242783c5
JJ		 700 rtx op1 = lowpart_subreg (V4SFmode, force_reg (V2SFmode, operands[1]),
701 V2SFmode);
8f921393
UB		 702 rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
703 force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
704 rtx tmp = gen_reg_rtx (V4SFmode);
705
706 emit_insn (gen_rtx_SET (tmp, op2));
707
242783c5
JJ		 708 rtx op0 = gen_reg_rtx (V4SFmode);
709
8f921393 710 emit_insn (gen_divv4sf3 (op0, op1, tmp));
242783c5
JJ		 711
712 emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
8f921393
UB		 713 DONE;
714})
715
333d8f61 716(define_expand "mmx_<code>v2sf3"
82e86dc6 717 [(set (match_operand:V2SF 0 "register_operand")
333d8f61 718 (smaxmin:V2SF
7c355156
UB		 719 (match_operand:V2SF 1 "register_mmxmem_operand")
720 (match_operand:V2SF 2 "register_mmxmem_operand")))]
333d8f61
UB		 721 "TARGET_3DNOW"
722{
432baa02
UB		 723 if (!flag_finite_math_only || flag_signed_zeros)
724 {
725 operands[1] = force_reg (V2SFmode, operands[1]);
726 emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
727 (operands[0], operands[1], operands[2]));
728 DONE;
729 }
730 else
731 ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
333d8f61
UB		 732})
733
7c355156
UB		 734(define_expand "<code>v2sf3"
735 [(set (match_operand:V2SF 0 "register_operand")
736 (smaxmin:V2SF
737 (match_operand:V2SF 1 "register_operand")
738 (match_operand:V2SF 2 "register_operand")))]
739 "TARGET_MMX_WITH_SSE"
740{
741 if (!flag_finite_math_only || flag_signed_zeros)
742 {
743 emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
744 (operands[0], operands[1], operands[2]));
745 DONE;
746 }
7c355156
UB		 747})
748
432baa02
UB		 749;; These versions of the min/max patterns are intentionally ignorant of
750;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
751;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
752;; are undefined in this condition, we're certain this is correct.
753
754(define_insn "*mmx_<code>v2sf3"
aa431786 755 [(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
78e8956b 756 (smaxmin:V2SF
aa431786
UB		 757 (match_operand:V2SF 1 "register_mmxmem_operand" "%0,0,v")
758 (match_operand:V2SF 2 "register_mmxmem_operand" "ym,x,v")))]
7c355156
UB		 759 "(TARGET_3DNOW || TARGET_MMX_WITH_SSE)
760 && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
761 "@
762 pf<maxmin_float>\t{%2, %0|%0, %2}
763 <maxmin_float>ps\t{%2, %0|%0, %2}
764 v<maxmin_float>ps\t{%2, %1, %0|%0, %1, %2}"
765 [(set_attr "isa" "*,sse2_noavx,avx")
766 (set_attr "mmx_isa" "native,*,*")
767 (set_attr "type" "mmxadd,sseadd,sseadd")
768 (set_attr "btver2_sse_attr" "*,maxmin,maxmin")
769 (set_attr "prefix_extra" "1,*,*")
aa431786 770 (set_attr "prefix" "*,orig,vex")
7c355156 771 (set_attr "mode" "V2SF,V4SF,V4SF")])
333d8f61 772
432baa02
UB		 773;; These versions of the min/max patterns implement exactly the operations
774;; min = (op1 < op2 ? op1 : op2)
775;; max = (!(op1 < op2) ? op1 : op2)
776;; Their operands are not commutative, and thus they may be used in the
777;; presence of -0.0 and NaN.
778
779(define_insn "mmx_ieee_<ieee_maxmin>v2sf3"
aa431786 780 [(set (match_operand:V2SF 0 "register_operand" "=y,x,v")
432baa02 781 (unspec:V2SF
aa431786
UB		 782 [(match_operand:V2SF 1 "register_operand" "0,0,v")
783 (match_operand:V2SF 2 "register_mmxmem_operand" "ym,x,v")]
432baa02 784 IEEE_MAXMIN))]
7c355156
UB		 785 "TARGET_3DNOW || TARGET_MMX_WITH_SSE"
786 "@
787 pf<ieee_maxmin>\t{%2, %0|%0, %2}
788 <ieee_maxmin>ps\t{%2, %0|%0, %2}
789 v<ieee_maxmin>ps\t{%2, %1, %0|%0, %1, %2}"
790 [(set_attr "isa" "*,sse2_noavx,avx")
791 (set_attr "mmx_isa" "native,*,*")
792 (set_attr "type" "mmxadd,sseadd,sseadd")
793 (set_attr "btver2_sse_attr" "*,maxmin,maxmin")
794 (set_attr "prefix_extra" "1,*,*")
aa431786 795 (set_attr "prefix" "*,orig,vex")
7c355156 796 (set_attr "mode" "V2SF,V4SF,V4SF")])
80e8bb90
RH		 797
798(define_insn "mmx_rcpv2sf2"
799 [(set (match_operand:V2SF 0 "register_operand" "=y")
800 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
801 UNSPEC_PFRCP))]
802 "TARGET_3DNOW"
333d8f61 803 "pfrcp\t{%1, %0|%0, %1}"
80e8bb90 804 [(set_attr "type" "mmx")
725fd454 805 (set_attr "prefix_extra" "1")
80e8bb90
RH		 806 (set_attr "mode" "V2SF")])
807
808(define_insn "mmx_rcpit1v2sf3"
809 [(set (match_operand:V2SF 0 "register_operand" "=y")
810 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
811 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
812 UNSPEC_PFRCPIT1))]
813 "TARGET_3DNOW"
333d8f61 814 "pfrcpit1\t{%2, %0|%0, %2}"
80e8bb90 815 [(set_attr "type" "mmx")
725fd454 816 (set_attr "prefix_extra" "1")
80e8bb90
RH		 817 (set_attr "mode" "V2SF")])
818
819(define_insn "mmx_rcpit2v2sf3"
820 [(set (match_operand:V2SF 0 "register_operand" "=y")
821 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
822 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
823 UNSPEC_PFRCPIT2))]
824 "TARGET_3DNOW"
333d8f61 825 "pfrcpit2\t{%2, %0|%0, %2}"
80e8bb90 826 [(set_attr "type" "mmx")
725fd454 827 (set_attr "prefix_extra" "1")
80e8bb90
RH		 828 (set_attr "mode" "V2SF")])
829
2b2d298f
UB		 830(define_insn "sqrtv2sf2"
831 [(set (match_operand:V2SF 0 "register_operand" "=x,v")
832 (sqrt:V2SF (match_operand:V2SF 1 "register_operand" "0,v")))]
833 "TARGET_MMX_WITH_SSE"
834 "@
835 sqrtps\t{%1, %0|%0, %1}
836 vsqrtps\t{%1, %0|%0, %1}"
837 [(set_attr "isa" "noavx,avx")
838 (set_attr "type" "sse")
839 (set_attr "atom_sse_attr" "sqrt")
840 (set_attr "btver2_sse_attr" "sqrt")
841 (set_attr "prefix" "orig,vex")
842 (set_attr "mode" "V4SF")])
843
80e8bb90
RH		 844(define_insn "mmx_rsqrtv2sf2"
845 [(set (match_operand:V2SF 0 "register_operand" "=y")
846 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
847 UNSPEC_PFRSQRT))]
848 "TARGET_3DNOW"
333d8f61 849 "pfrsqrt\t{%1, %0|%0, %1}"
80e8bb90 850 [(set_attr "type" "mmx")
725fd454 851 (set_attr "prefix_extra" "1")
80e8bb90 852 (set_attr "mode" "V2SF")])
4f3f76e6 853
80e8bb90
RH		 854(define_insn "mmx_rsqit1v2sf3"
855 [(set (match_operand:V2SF 0 "register_operand" "=y")
856 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
857 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
858 UNSPEC_PFRSQIT1))]
859 "TARGET_3DNOW"
333d8f61 860 "pfrsqit1\t{%2, %0|%0, %2}"
80e8bb90 861 [(set_attr "type" "mmx")
725fd454 862 (set_attr "prefix_extra" "1")
80e8bb90
RH		 863 (set_attr "mode" "V2SF")])
864
f8b06654
UB		 865(define_expand "mmx_haddv2sf3"
866 [(set (match_operand:V2SF 0 "register_operand")
80e8bb90
RH		 867 (vec_concat:V2SF
868 (plus:SF
869 (vec_select:SF
f8b06654
UB		 870 (match_operand:V2SF 1 "register_operand")
871 (parallel [(const_int 0)]))
80e8bb90
RH		 872 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
873 (plus:SF
f8b06654
UB		 874 (vec_select:SF
875 (match_operand:V2SF 2 "nonimmediate_operand")
876 (parallel [(const_int 0)]))
80e8bb90 877 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
f8b06654
UB		 878 "TARGET_3DNOW")
879
880(define_insn "*mmx_haddv2sf3"
1852a26b 881 [(set (match_operand:V2SF 0 "register_operand" "=y")
f8b06654
UB		 882 (vec_concat:V2SF
883 (plus:SF
884 (vec_select:SF
1852a26b 885 (match_operand:V2SF 1 "register_operand" "0")
f8b06654
UB		 886 (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
887 (vec_select:SF (match_dup 1)
888 (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))
889 (plus:SF
890 (vec_select:SF
1852a26b 891 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
f8b06654
UB		 892 (parallel [(match_operand:SI 5 "const_0_to_1_operand")]))
893 (vec_select:SF (match_dup 2)
894 (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))]
895 "TARGET_3DNOW
896 && INTVAL (operands[3]) != INTVAL (operands[4])
897 && INTVAL (operands[5]) != INTVAL (operands[6])"
1852a26b
UB		 898 "pfacc\t{%2, %0|%0, %2}"
899 [(set_attr "type" "mmxadd")
900 (set_attr "prefix_extra" "1")
901 (set_attr "mode" "V2SF")])
f8b06654
UB		 902
903(define_insn "*mmx_haddv2sf3_low"
904 [(set (match_operand:SF 0 "register_operand" "=x,x")
905 (plus:SF
906 (vec_select:SF
907 (match_operand:V2SF 1 "register_operand" "0,x")
908 (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))
909 (vec_select:SF
910 (match_dup 1)
911 (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
a617e5d5 912 "TARGET_SSE3 && TARGET_MMX_WITH_SSE
f8b06654
UB		 913 && INTVAL (operands[2]) != INTVAL (operands[3])"
914 "@
915 haddps\t{%0, %0|%0, %0}
916 vhaddps\t{%1, %1, %0|%0, %1, %1}"
917 [(set_attr "isa" "noavx,avx")
918 (set_attr "type" "sseadd1")
919 (set_attr "prefix" "orig,vex")
920 (set_attr "mode" "V4SF")])
80e8bb90
RH		 921
922(define_insn "mmx_hsubv2sf3"
1852a26b 923 [(set (match_operand:V2SF 0 "register_operand" "=y")
80e8bb90
RH		 924 (vec_concat:V2SF
925 (minus:SF
926 (vec_select:SF
1852a26b 927 (match_operand:V2SF 1 "register_operand" "0")
80e8bb90
RH		 928 (parallel [(const_int 0)]))
929 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
930 (minus:SF
931 (vec_select:SF
1852a26b 932 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
80e8bb90
RH		 933 (parallel [(const_int 0)]))
934 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
935 "TARGET_3DNOW_A"
1852a26b
UB		 936 "pfnacc\t{%2, %0|%0, %2}"
937 [(set_attr "type" "mmxadd")
938 (set_attr "prefix_extra" "1")
939 (set_attr "mode" "V2SF")])
f8b06654
UB		 940
941(define_insn "*mmx_hsubv2sf3_low"
942 [(set (match_operand:SF 0 "register_operand" "=x,x")
943 (minus:SF
944 (vec_select:SF
945 (match_operand:V2SF 1 "register_operand" "0,x")
946 (parallel [(const_int 0)]))
947 (vec_select:SF
948 (match_dup 1)
949 (parallel [(const_int 1)]))))]
a617e5d5 950 "TARGET_SSE3 && TARGET_MMX_WITH_SSE"
f8b06654
UB		 951 "@
952 hsubps\t{%0, %0|%0, %0}
953 vhsubps\t{%1, %1, %0|%0, %1, %1}"
954 [(set_attr "isa" "noavx,avx")
955 (set_attr "type" "sseadd1")
956 (set_attr "prefix" "orig,vex")
957 (set_attr "mode" "V4SF")])
80e8bb90 958
1852a26b
UB		 959(define_expand "mmx_haddsubv2sf3"
960 [(set (match_operand:V2SF 0 "register_operand")
961 (vec_concat:V2SF
962 (minus:SF
963 (vec_select:SF
964 (match_operand:V2SF 1 "register_operand")
965 (parallel [(const_int 0)]))
966 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
967 (plus:SF
968 (vec_select:SF
969 (match_operand:V2SF 2 "nonimmediate_operand")
970 (parallel [(const_int 0)]))
971 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
972 "TARGET_3DNOW_A")
973
974(define_insn "*mmx_haddsubv2sf3"
80e8bb90 975 [(set (match_operand:V2SF 0 "register_operand" "=y")
1852a26b
UB		 976 (vec_concat:V2SF
977 (minus:SF
978 (vec_select:SF
979 (match_operand:V2SF 1 "register_operand" "0")
980 (parallel [(const_int 0)]))
981 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
982 (plus:SF
983 (vec_select:SF
984 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
985 (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
986 (vec_select:SF
987 (match_dup 2)
988 (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))))]
989 "TARGET_3DNOW_A
990 && INTVAL (operands[3]) != INTVAL (operands[4])"
333d8f61 991 "pfpnacc\t{%2, %0|%0, %2}"
80e8bb90 992 [(set_attr "type" "mmxadd")
725fd454 993 (set_attr "prefix_extra" "1")
80e8bb90
RH		 994 (set_attr "mode" "V2SF")])
995
c60d9160
UB		 996(define_insn "vec_addsubv2sf3"
997 [(set (match_operand:V2SF 0 "register_operand" "=x,x")
998 (vec_merge:V2SF
999 (minus:V2SF
1000 (match_operand:V2SF 1 "register_operand" "0,x")
1001 (match_operand:V2SF 2 "register_operand" "x,x"))
1002 (plus:V2SF (match_dup 1) (match_dup 2))
1003 (const_int 1)))]
1004 "TARGET_SSE3 && TARGET_MMX_WITH_SSE"
1005 "@
1006 addsubps\t{%2, %0|%0, %2}
1007 vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1008 [(set_attr "isa" "noavx,avx")
1009 (set_attr "type" "sseadd")
1010 (set_attr "prefix" "orig,vex")
1011 (set_attr "prefix_rep" "1,*")
1012 (set_attr "mode" "V4SF")])
1013
80e8bb90
RH		 1014;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1015;;
1016;; Parallel single-precision floating point comparisons
1017;;
1018;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1019
ffbaf337 1020(define_expand "mmx_eqv2sf3"
82e86dc6
UB		 1021 [(set (match_operand:V2SI 0 "register_operand")
1022 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
1023 (match_operand:V2SF 2 "nonimmediate_operand")))]
ffbaf337
UB		 1024 "TARGET_3DNOW"
1025 "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
1026
1027(define_insn "*mmx_eqv2sf3"
1028 [(set (match_operand:V2SI 0 "register_operand" "=y")
1029 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
1030 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
1031 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
1032 "pfcmpeq\t{%2, %0|%0, %2}"
1033 [(set_attr "type" "mmxcmp")
725fd454 1034 (set_attr "prefix_extra" "1")
ffbaf337
UB		 1035 (set_attr "mode" "V2SF")])
1036
80e8bb90
RH		 1037(define_insn "mmx_gtv2sf3"
1038 [(set (match_operand:V2SI 0 "register_operand" "=y")
1039 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
1040 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
1041 "TARGET_3DNOW"
333d8f61 1042 "pfcmpgt\t{%2, %0|%0, %2}"
80e8bb90 1043 [(set_attr "type" "mmxcmp")
725fd454 1044 (set_attr "prefix_extra" "1")
80e8bb90
RH		 1045 (set_attr "mode" "V2SF")])
1046
1047(define_insn "mmx_gev2sf3"
1048 [(set (match_operand:V2SI 0 "register_operand" "=y")
1049 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
1050 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
1051 "TARGET_3DNOW"
333d8f61 1052 "pfcmpge\t{%2, %0|%0, %2}"
80e8bb90 1053 [(set_attr "type" "mmxcmp")
725fd454 1054 (set_attr "prefix_extra" "1")
80e8bb90
RH		 1055 (set_attr "mode" "V2SF")])
1056
b1f7fd8a
UB		 1057(define_insn "*mmx_maskcmpv2sf3_comm"
1058 [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1059 (match_operator:V2SF 3 "sse_comparison_operator"
1060 [(match_operand:V2SF 1 "register_operand" "%0,x")
1061 (match_operand:V2SF 2 "register_operand" "x,x")]))]
1062 "TARGET_MMX_WITH_SSE
1063 && GET_RTX_CLASS (GET_CODE (operands[3])) == RTX_COMM_COMPARE"
1064 "@
1065 cmp%D3ps\t{%2, %0|%0, %2}
1066 vcmp%D3ps\t{%2, %1, %0|%0, %1, %2}"
1067 [(set_attr "isa" "noavx,avx")
1068 (set_attr "type" "ssecmp")
1069 (set_attr "length_immediate" "1")
1070 (set_attr "prefix" "orig,vex")
1071 (set_attr "mode" "V4SF")])
1072
1073(define_insn "*mmx_maskcmpv2sf3"
1074 [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1075 (match_operator:V2SF 3 "sse_comparison_operator"
1076 [(match_operand:V2SF 1 "register_operand" "0,x")
1077 (match_operand:V2SF 2 "register_operand" "x,x")]))]
1078 "TARGET_MMX_WITH_SSE"
1079 "@
1080 cmp%D3ps\t{%2, %0|%0, %2}
1081 vcmp%D3ps\t{%2, %1, %0|%0, %1, %2}"
1082 [(set_attr "isa" "noavx,avx")
1083 (set_attr "type" "ssecmp")
1084 (set_attr "length_immediate" "1")
1085 (set_attr "prefix" "orig,vex")
1086 (set_attr "mode" "V4SF")])
1087
1088(define_expand "vec_cmpv2sfv2si"
1089 [(set (match_operand:V2SI 0 "register_operand")
1090 (match_operator:V2SI 1 ""
1091 [(match_operand:V2SF 2 "register_operand")
1092 (match_operand:V2SF 3 "register_operand")]))]
1093 "TARGET_MMX_WITH_SSE"
1094{
1095 bool ok = ix86_expand_fp_vec_cmp (operands);
1096 gcc_assert (ok);
1097 DONE;
1098})
1099
1100(define_expand "vcond<mode>v2sf"
1101 [(set (match_operand:V2FI 0 "register_operand")
1102 (if_then_else:V2FI
1103 (match_operator 3 ""
1104 [(match_operand:V2SF 4 "register_operand")
1105 (match_operand:V2SF 5 "register_operand")])
1106 (match_operand:V2FI 1)
1107 (match_operand:V2FI 2)))]
1108 "TARGET_MMX_WITH_SSE"
1109{
1110 bool ok = ix86_expand_fp_vcond (operands);
1111 gcc_assert (ok);
1112 DONE;
1113})
1114
1115(define_insn "mmx_blendvps"
1116 [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1117 (unspec:V2SF
1118 [(match_operand:V2SF 1 "register_operand" "0,0,x")
1119 (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1120 (match_operand:V2SF 3 "register_operand" "Yz,Yz,x")]
1121 UNSPEC_BLENDV))]
1122 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1123 "@
1124 blendvps\t{%3, %2, %0|%0, %2, %3}
1125 blendvps\t{%3, %2, %0|%0, %2, %3}
1126 vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1127 [(set_attr "isa" "noavx,noavx,avx")
1128 (set_attr "type" "ssemov")
1129 (set_attr "length_immediate" "1")
1130 (set_attr "prefix_data16" "1,1,*")
1131 (set_attr "prefix_extra" "1")
1132 (set_attr "prefix" "orig,orig,vex")
1133 (set_attr "btver2_decode" "vector")
1134 (set_attr "mode" "V4SF")])
1135
6416f672
UB		 1136;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1137;;
1138;; Parallel single-precision floating point logical operations
1139;;
1140;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1141
1142(define_insn "*mmx_andnotv2sf3"
1143 [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1144 (and:V2SF
1145 (not:V2SF
1146 (match_operand:V2SF 1 "register_operand" "0,x"))
1147 (match_operand:V2SF 2 "register_operand" "x,x")))]
1148 "TARGET_MMX_WITH_SSE"
1149 "@
8a6790fb
UB		 1150 andnps\t{%2, %0|%0, %2}
1151 vandnps\t{%2, %1, %0|%0, %1, %2}"
6416f672
UB		 1152 [(set_attr "isa" "noavx,avx")
1153 (set_attr "type" "sselog")
1154 (set_attr "prefix" "orig,vex")
1155 (set_attr "mode" "V4SF")])
1156
9d2d660a 1157(define_insn "<code>v2sf3"
6416f672
UB		 1158 [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1159 (any_logic:V2SF
1160 (match_operand:V2SF 1 "register_operand" "%0,x")
1161 (match_operand:V2SF 2 "register_operand" "x,x")))]
1162 "TARGET_MMX_WITH_SSE"
1163 "@
1164 <logic>ps\t{%2, %0|%0, %2}
1165 v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
1166 [(set_attr "isa" "noavx,avx")
1167 (set_attr "type" "sselog")
1168 (set_attr "prefix" "orig,vex")
1169 (set_attr "mode" "V4SF")])
1170
8a6790fb
UB		 1171(define_expand "copysignv2sf3"
1172 [(set (match_dup 4)
1173 (and:V2SF
1174 (not:V2SF (match_dup 3))
1175 (match_operand:V2SF 1 "register_operand")))
1176 (set (match_dup 5)
1177 (and:V2SF (match_dup 3)
1178 (match_operand:V2SF 2 "register_operand")))
1179 (set (match_operand:V2SF 0 "register_operand")
1180 (ior:V2SF (match_dup 4) (match_dup 5)))]
1181 "TARGET_MMX_WITH_SSE"
1182{
1183 operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1184
1185 operands[4] = gen_reg_rtx (V2SFmode);
1186 operands[5] = gen_reg_rtx (V2SFmode);
1187})
1188
1189(define_expand "xorsignv2sf3"
1190 [(set (match_dup 4)
1191 (and:V2SF (match_dup 3)
1192 (match_operand:V2SF 2 "register_operand")))
1193 (set (match_operand:V2SF 0 "register_operand")
1194 (xor:V2SF (match_dup 4)
1195 (match_operand:V2SF 1 "register_operand")))]
1196 "TARGET_MMX_WITH_SSE"
1197{
1198 operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1199
1200 operands[4] = gen_reg_rtx (V2SFmode);
1201})
1202
1203(define_expand "signbitv2sf2"
1204 [(set (match_operand:V2SI 0 "register_operand")
1205 (lshiftrt:V2SI
1206 (subreg:V2SI
1207 (match_operand:V2SF 1 "register_operand") 0)
1208 (match_dup 2)))]
1209 "TARGET_MMX_WITH_SSE"
1210 "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);")
1211
955b1f92
UB		 1212;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1213;;
1214;; Parallel single-precision FMA multiply/accumulate instructions.
1215;;
1216;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1217
1218(define_insn "fmav2sf4"
1219 [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1220 (fma:V2SF
1221 (match_operand:V2SF 1 "register_operand" "%0,v,x")
1222 (match_operand:V2SF 2 "register_operand" "v,v,x")
1223 (match_operand:V2SF 3 "register_operand" "v,0,x")))]
b0ac84dc 1224 "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1225 && TARGET_MMX_WITH_SSE"
955b1f92
UB		 1226 "@
1227 vfmadd132ps\t{%2, %3, %0|%0, %3, %2}
1228 vfmadd231ps\t{%2, %1, %0|%0, %1, %2}
1229 vfmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
b0ac84dc 1230 [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
955b1f92
UB		 1231 (set_attr "type" "ssemuladd")
1232 (set_attr "mode" "V4SF")])
1233
1234(define_insn "fmsv2sf4"
1235 [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1236 (fma:V2SF
1237 (match_operand:V2SF 1 "register_operand" "%0,v,x")
1238 (match_operand:V2SF 2 "register_operand" "v,v,x")
1239 (neg:V2SF
1240 (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
b0ac84dc 1241 "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1242 && TARGET_MMX_WITH_SSE"
955b1f92
UB		 1243 "@
1244 vfmsub132ps\t{%2, %3, %0|%0, %3, %2}
1245 vfmsub231ps\t{%2, %1, %0|%0, %1, %2}
1246 vfmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
b0ac84dc 1247 [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
955b1f92
UB		 1248 (set_attr "type" "ssemuladd")
1249 (set_attr "mode" "V4SF")])
1250
1251(define_insn "fnmav2sf4"
1252 [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1253 (fma:V2SF
1254 (neg:V2SF
1255 (match_operand:V2SF 1 "register_operand" "%0,v,x"))
1256 (match_operand:V2SF 2 "register_operand" "v,v,x")
1257 (match_operand:V2SF 3 "register_operand" "v,0,x")))]
b0ac84dc 1258 "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1259 && TARGET_MMX_WITH_SSE"
955b1f92
UB		 1260 "@
1261 vfnmadd132ps\t{%2, %3, %0|%0, %3, %2}
1262 vfnmadd231ps\t{%2, %1, %0|%0, %1, %2}
1263 vfnmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
b0ac84dc 1264 [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
955b1f92
UB		 1265 (set_attr "type" "ssemuladd")
1266 (set_attr "mode" "V4SF")])
1267
1268(define_insn "fnmsv2sf4"
1269 [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1270 (fma:V2SF
1271 (neg:V2SF
1272 (match_operand:V2SF 1 "register_operand" "%0,v,x"))
1273 (match_operand:V2SF 2 "register_operand" "v,v,x")
1274 (neg:V2SF
1275 (match_operand:V2SF 3 "register_operand" "v,0,x"))))]
b0ac84dc 1276 "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1277 && TARGET_MMX_WITH_SSE"
955b1f92
UB		 1278 "@
1279 vfnmsub132ps\t{%2, %3, %0|%0, %3, %2}
1280 vfnmsub231ps\t{%2, %1, %0|%0, %1, %2}
1281 vfnmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
b0ac84dc 1282 [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4")
955b1f92
UB		 1283 (set_attr "type" "ssemuladd")
1284 (set_attr "mode" "V4SF")])
1285
80e8bb90
RH		 1286;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1287;;
1288;; Parallel single-precision floating point conversion operations
1289;;
1290;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1291
42ef8a5e
UB		 1292(define_insn "mmx_fix_truncv2sfv2si2"
1293 [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
1294 (fix:V2SI (match_operand:V2SF 1 "register_mmxmem_operand" "ym,Yv")))]
1295 "TARGET_3DNOW || TARGET_MMX_WITH_SSE"
1296 "@
1297 pf2id\t{%1, %0|%0, %1}
1298 %vcvttps2dq\t{%1, %0|%0, %1}"
1299 [(set_attr "isa" "*,sse2")
1300 (set_attr "mmx_isa" "native,*")
1301 (set_attr "type" "mmxcvt,ssecvt")
1302 (set_attr "prefix_extra" "1,*")
1303 (set_attr "prefix_rep" "*,1")
1304 (set_attr "prefix_data16" "*,0")
1305 (set_attr "prefix" "*,maybe_vex")
1306 (set_attr "mode" "V2SF,TI")])
1307
1308(define_expand "fix_truncv2sfv2si2"
1309 [(set (match_operand:V2SI 0 "register_operand")
1310 (fix:V2SI (match_operand:V2SF 1 "register_operand")))]
1311 "TARGET_MMX_WITH_SSE")
1312
1313(define_insn "fixuns_truncv2sfv2si2"
1314 [(set (match_operand:V2SI 0 "register_operand" "=v")
1315 (unsigned_fix:V2SI (match_operand:V2SF 1 "register_operand" "v")))]
a617e5d5 1316 "TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
42ef8a5e
UB		 1317 "vcvttps2udq\t{%1, %0|%0, %1}"
1318 [(set_attr "type" "ssecvt")
1319 (set_attr "prefix" "evex")
1320 (set_attr "mode" "TI")])
1321
1322(define_insn "mmx_floatv2siv2sf2"
1323 [(set (match_operand:V2SF 0 "register_operand" "=y,Yv")
1324 (float:V2SF (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")))]
1325 "TARGET_3DNOW || TARGET_MMX_WITH_SSE"
1326 "@
1327 pi2fd\t{%1, %0|%0, %1}
1328 %vcvtdq2ps\t{%1, %0|%0, %1}"
1329 [(set_attr "isa" "*,sse2")
1330 (set_attr "mmx_isa" "native,*")
1331 (set_attr "type" "mmxcvt,ssecvt")
725fd454 1332 (set_attr "prefix_extra" "1")
42ef8a5e
UB		 1333 (set_attr "prefix" "*,maybe_vex")
1334 (set_attr "mode" "V2SF,V4SF")])
1335
1336(define_expand "floatv2siv2sf2"
1337 [(set (match_operand:V2SF 0 "register_operand")
1338 (float:V2SF (match_operand:V2SI 1 "register_operand")))]
1339 "TARGET_MMX_WITH_SSE")
1340
1341(define_insn "floatunsv2siv2sf2"
1342 [(set (match_operand:V2SF 0 "register_operand" "=v")
1343 (unsigned_float:V2SF (match_operand:V2SI 1 "register_operand" "v")))]
a617e5d5 1344 "TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
42ef8a5e
UB		 1345 "vcvtudq2ps\t{%1, %0|%0, %1}"
1346 [(set_attr "type" "ssecvt")
1347 (set_attr "prefix" "evex")
1348 (set_attr "mode" "V4SF")])
80e8bb90
RH		 1349
1350(define_insn "mmx_pf2iw"
1351 [(set (match_operand:V2SI 0 "register_operand" "=y")
1352 (sign_extend:V2SI
1353 (ss_truncate:V2HI
1354 (fix:V2SI
1355 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
1356 "TARGET_3DNOW_A"
333d8f61 1357 "pf2iw\t{%1, %0|%0, %1}"
80e8bb90 1358 [(set_attr "type" "mmxcvt")
725fd454 1359 (set_attr "prefix_extra" "1")
80e8bb90
RH		 1360 (set_attr "mode" "V2SF")])
1361
1362(define_insn "mmx_pi2fw"
1363 [(set (match_operand:V2SF 0 "register_operand" "=y")
1364 (float:V2SF
1365 (sign_extend:V2SI
1366 (truncate:V2HI
1367 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
1368 "TARGET_3DNOW_A"
333d8f61 1369 "pi2fw\t{%1, %0|%0, %1}"
80e8bb90 1370 [(set_attr "type" "mmxcvt")
725fd454 1371 (set_attr "prefix_extra" "1")
80e8bb90
RH		 1372 (set_attr "mode" "V2SF")])
1373
1374;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1375;;
1376;; Parallel single-precision floating point element swizzling
1377;;
1378;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1379
1380(define_insn "mmx_pswapdv2sf2"
240198fe
UB		 1381 [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv")
1382 (vec_select:V2SF
1383 (match_operand:V2SF 1 "register_mmxmem_operand" "ym,0,Yv")
1384 (parallel [(const_int 1) (const_int 0)])))]
1385 "TARGET_3DNOW_A || TARGET_MMX_WITH_SSE"
1386 "@
1387 pswapd\t{%1, %0|%0, %1}
1388 shufps\t{$0xe1, %1, %0|%0, %1, 0xe1}
1389 vshufps\t{$0xe1, %1, %1, %0|%0, %1, %1, 0xe1}"
1390 [(set_attr "isa" "*,sse_noavx,avx")
1391 (set_attr "mmx_isa" "native,*,*")
1392 (set_attr "type" "mmxcvt,ssemov,ssemov")
1393 (set_attr "prefix_extra" "1,*,*")
1394 (set_attr "mode" "V2SF,V4SF,V4SF")])
1395
1396(define_insn "*mmx_movshdup"
1397 [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1398 (vec_select:V2SF
1399 (match_operand:V2SF 1 "register_operand" "v,0")
1400 (parallel [(const_int 1) (const_int 1)])))]
1401 "TARGET_MMX_WITH_SSE"
1402 "@
1403 %vmovshdup\t{%1, %0|%0, %1}
1404 shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}"
1405 [(set_attr "isa" "sse3,*")
1406 (set_attr "type" "sse,sseshuf1")
1407 (set_attr "length_immediate" "*,1")
1408 (set_attr "prefix_rep" "1,*")
1409 (set_attr "prefix" "maybe_vex,orig")
1410 (set_attr "mode" "V4SF")])
1411
1412(define_insn "*mmx_movsldup"
1413 [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1414 (vec_select:V2SF
1415 (match_operand:V2SF 1 "register_operand" "v,0")
1416 (parallel [(const_int 0) (const_int 0)])))]
1417 "TARGET_MMX_WITH_SSE"
1418 "@
1419 %vmovsldup\t{%1, %0|%0, %1}
1420 shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1421 [(set_attr "isa" "sse3,*")
1422 (set_attr "type" "sse,sseshuf1")
1423 (set_attr "length_immediate" "*,1")
1424 (set_attr "prefix_rep" "1,*")
1425 (set_attr "prefix" "maybe_vex,orig")
1426 (set_attr "mode" "V4SF")])
80e8bb90 1427
a325bdd1
PB		 1428(define_insn_and_split "*vec_interleave_lowv2sf"
1429 [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1430 (vec_select:V2SF
1431 (vec_concat:V4SF
1432 (match_operand:V2SF 1 "register_operand" "0,v")
1433 (match_operand:V2SF 2 "register_operand" "x,v"))
1434 (parallel [(const_int 0) (const_int 2)])))]
1435 "TARGET_MMX_WITH_SSE"
1436 "#"
1437 "&& reload_completed"
1438 [(const_int 0)]
1439 "ix86_split_mmx_punpck (operands, false); DONE;"
1440 [(set_attr "isa" "noavx,avx")
1441 (set_attr "type" "sselog")
1442 (set_attr "prefix" "orig,maybe_evex")
1443 (set_attr "mode" "V4SF")])
1444
1445(define_insn_and_split "*vec_interleave_highv2sf"
1446 [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1447 (vec_select:V2SF
1448 (vec_concat:V4SF
1449 (match_operand:V2SF 1 "register_operand" "0,v")
1450 (match_operand:V2SF 2 "register_operand" "x,v"))
1451 (parallel [(const_int 1) (const_int 3)])))]
1452 "TARGET_MMX_WITH_SSE"
1453 "#"
1454 "&& reload_completed"
1455 [(const_int 0)]
1456 "ix86_split_mmx_punpck (operands, true); DONE;"
1457 [(set_attr "isa" "noavx,avx")
1458 (set_attr "type" "sselog")
1459 (set_attr "prefix" "orig,vex")
1460 (set_attr "mode" "V4SF")])
1461
14cd049a 1462(define_insn "*vec_dupv2sf"
240198fe 1463 [(set (match_operand:V2SF 0 "register_operand" "=y,Yv,x")
eb701deb 1464 (vec_duplicate:V2SF
240198fe 1465 (match_operand:SF 1 "register_operand" "0,Yv,0")))]
d4410ec0
L		 1466 "TARGET_MMX || TARGET_MMX_WITH_SSE"
1467 "@
1468 punpckldq\t%0, %0
240198fe
UB		 1469 %vmovsldup\t{%1, %0|%0, %1}
1470 shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1471 [(set_attr "isa" "*,sse3,sse_noavx")
37d8d439 1472 (set_attr "mmx_isa" "native,*,*")
240198fe
UB		 1473 (set_attr "type" "mmxcvt,sse,sseshuf1")
1474 (set_attr "length_immediate" "*,*,1")
1475 (set_attr "prefix_rep" "*,1,*")
1476 (set_attr "prefix" "*,maybe_vex,orig")
14cd049a 1477 (set_attr "mode" "DI,V4SF,V4SF")])
eb701deb 1478
240198fe
UB		 1479(define_insn "*mmx_movss"
1480 [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1481 (vec_merge:V2SF
1482 (match_operand:V2SF 2 "register_operand" " x,v")
1483 (match_operand:V2SF 1 "register_operand" " 0,v")
1484 (const_int 1)))]
1485 "TARGET_MMX_WITH_SSE"
1486 "@
1487 movss\t{%2, %0|%0, %2}
1488 vmovss\t{%2, %1, %0|%0, %1, %2}"
1489 [(set_attr "isa" "noavx,avx")
1490 (set_attr "type" "ssemov")
1491 (set_attr "prefix" "orig,maybe_evex")
1492 (set_attr "mode" "SF")])
1493
eb701deb
RH		 1494(define_insn "*mmx_concatv2sf"
1495 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
1496 (vec_concat:V2SF
1497 (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
808d8de5 1498 (match_operand:SF 2 "nonimm_or_0_operand" "ym,C")))]
eb701deb
RH		 1499 "TARGET_MMX && !TARGET_SSE"
1500 "@
1501 punpckldq\t{%2, %0|%0, %2}
1502 movd\t{%1, %0|%0, %1}"
1503 [(set_attr "type" "mmxcvt,mmxmov")
1504 (set_attr "mode" "DI")])
1505
1506(define_expand "vec_setv2sf"
82e86dc6
UB		 1507 [(match_operand:V2SF 0 "register_operand")
1508 (match_operand:SF 1 "register_operand")
20a2c8ac 1509 (match_operand 2 "vec_setm_mmx_operand")]
d4410ec0 1510 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 1511{
20a2c8ac
UB		 1512 if (CONST_INT_P (operands[2]))
1513 ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
1514 INTVAL (operands[2]));
1515 else
1516 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
eb701deb
RH		 1517 DONE;
1518})
1519
a3d4a22b
UB		 1520;; Avoid combining registers from different units in a single alternative,
1521;; see comment above inline_secondary_memory_needed function in i386.c
0f2698d0 1522(define_insn_and_split "*vec_extractv2sf_0"
a3d4a22b 1523 [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
0f2698d0 1524 (vec_select:SF
a3d4a22b 1525 (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
0f2698d0 1526 (parallel [(const_int 0)])))]
d4410ec0
L		 1527 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1528 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
0f2698d0
RH		 1529 "#"
1530 "&& reload_completed"
0b013847 1531 [(set (match_dup 0) (match_dup 1))]
d4410ec0
L		 1532 "operands[1] = gen_lowpart (SFmode, operands[1]);"
1533 [(set_attr "mmx_isa" "*,*,native,native,*,*")])
0f2698d0 1534
a3d4a22b
UB		 1535;; Avoid combining registers from different units in a single alternative,
1536;; see comment above inline_secondary_memory_needed function in i386.c
0f2698d0 1537(define_insn "*vec_extractv2sf_1"
db67dfda 1538 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,x,y,x,f,r")
0f2698d0 1539 (vec_select:SF
d56779b8 1540 (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,0,o,o,o,o")
0f2698d0 1541 (parallel [(const_int 1)])))]
d4410ec0
L		 1542 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1543 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
0f2698d0
RH		 1544 "@
1545 punpckhdq\t%0, %0
db67dfda 1546 %vmovshdup\t{%1, %0|%0, %1}
d56779b8 1547 shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
a3d4a22b
UB		 1548 #
1549 #
1550 #
0f2698d0 1551 #"
db67dfda 1552 [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
d4410ec0 1553 (set_attr "mmx_isa" "native,*,*,native,*,*,*")
db67dfda 1554 (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
e070095c
UB		 1555 (set (attr "length_immediate")
1556 (if_then_else (eq_attr "alternative" "2")
1557 (const_string "1")
1558 (const_string "*")))
1559 (set (attr "prefix_rep")
1560 (if_then_else (eq_attr "alternative" "1")
1561 (const_string "1")
1562 (const_string "*")))
db67dfda
UB		 1563 (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
1564 (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
0f2698d0
RH		 1565
1566(define_split
82e86dc6 1567 [(set (match_operand:SF 0 "register_operand")
0f2698d0 1568 (vec_select:SF
82e86dc6 1569 (match_operand:V2SF 1 "memory_operand")
0f2698d0 1570 (parallel [(const_int 1)])))]
d4410ec0 1571 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
0b013847
UB		 1572 [(set (match_dup 0) (match_dup 1))]
1573 "operands[1] = adjust_address (operands[1], SFmode, 4);")
0f2698d0 1574
ff03930a 1575(define_expand "vec_extractv2sfsf"
82e86dc6
UB		 1576 [(match_operand:SF 0 "register_operand")
1577 (match_operand:V2SF 1 "register_operand")
1578 (match_operand 2 "const_int_operand")]
d4410ec0 1579 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 1580{
d4410ec0
L		 1581 ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
1582 operands[1], INTVAL (operands[2]));
eb701deb
RH		 1583 DONE;
1584})
1585
ff03930a 1586(define_expand "vec_initv2sfsf"
82e86dc6
UB		 1587 [(match_operand:V2SF 0 "register_operand")
1588 (match_operand 1)]
d4410ec0 1589 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
eb701deb 1590{
d4410ec0
L		 1591 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
1592 operands[1]);
eb701deb
RH		 1593 DONE;
1594})
1595
eea10afe
HW		 1596;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1597;;
1598;; Parallel half-precision floating point arithmetic
1599;;
1600;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1601
1602(define_insn "<insn><mode>3"
1603 [(set (match_operand:VHF_32_64 0 "register_operand" "=v")
1604 (plusminusmultdiv:VHF_32_64
1605 (match_operand:VHF_32_64 1 "register_operand" "<comm>v")
1606 (match_operand:VHF_32_64 2 "register_operand" "v")))]
1607 "TARGET_AVX512FP16 && TARGET_AVX512VL"
1608 "v<insn>ph\t{%2, %1, %0|%0, %1, %2}"
1609 [(set (attr "type")
1610 (cond [(match_test "<CODE> == MULT")
1611 (const_string "ssemul")
1612 (match_test "<CODE> == DIV")
1613 (const_string "ssediv")]
1614 (const_string "sseadd")))
1615 (set_attr "prefix" "evex")
1616 (set_attr "mode" "V8HF")])
1617
80e8bb90
RH		 1618;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1619;;
1620;; Parallel integral arithmetic
1621;;
1622;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1623
46ca31d6
UB		 1624(define_expand "neg<mode>2"
1625 [(set (match_operand:MMXMODEI 0 "register_operand")
1626 (minus:MMXMODEI
1627 (match_dup 2)
1628 (match_operand:MMXMODEI 1 "register_operand")))]
1629 "TARGET_MMX_WITH_SSE"
1630 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
1631
9ff206d3
UB		 1632(define_insn "negv2qi2"
1633 [(set (match_operand:V2QI 0 "register_operand" "=Q,&Yw")
1634 (neg:V2QI
1635 (match_operand:V2QI 1 "register_operand" "0,Yw")))
1636 (clobber (reg:CC FLAGS_REG))]
1637 ""
1638 "#"
1639 [(set_attr "isa" "*,sse2")
1640 (set_attr "type" "multi")
1641 (set_attr "mode" "QI,TI")])
1642
1643(define_split
1644 [(set (match_operand:V2QI 0 "general_reg_operand")
1645 (neg:V2QI
1646 (match_operand:V2QI 1 "general_reg_operand")))
1647 (clobber (reg:CC FLAGS_REG))]
1648 "reload_completed"
1649 [(parallel
1650 [(set (strict_low_part (match_dup 0))
1651 (neg:QI (match_dup 1)))
1652 (clobber (reg:CC FLAGS_REG))])
1653 (parallel
1654 [(set (zero_extract:HI (match_dup 2) (const_int 8) (const_int 8))
1655 (subreg:HI
1656 (neg:QI
1657 (subreg:QI
1658 (zero_extract:HI (match_dup 3)
1659 (const_int 8)
1660 (const_int 8)) 0)) 0))
1661 (clobber (reg:CC FLAGS_REG))])]
1662{
1663 operands[3] = gen_lowpart (HImode, operands[1]);
1664 operands[2] = gen_lowpart (HImode, operands[0]);
1665 operands[1] = gen_lowpart (QImode, operands[1]);
1666 operands[0] = gen_lowpart (QImode, operands[0]);
1667})
1668
1669(define_split
1670 [(set (match_operand:V2QI 0 "sse_reg_operand")
1671 (neg:V2QI
1672 (match_operand:V2QI 1 "sse_reg_operand")))
1673 (clobber (reg:CC FLAGS_REG))]
1674 "reload_completed"
1675 [(set (match_dup 0) (match_dup 2))
1676 (set (match_dup 0)
1677 (minus:V4QI (match_dup 0) (match_dup 1)))]
1678{
1679 operands[2] = CONST0_RTX (V4QImode);
1680 operands[1] = gen_lowpart (V4QImode, operands[1]);
1681 operands[0] = gen_lowpart (V4QImode, operands[0]);
1682})
1683
d54be5ad 1684(define_expand "mmx_<insn><mode>3"
82e86dc6 1685 [(set (match_operand:MMXMODEI8 0 "register_operand")
333d8f61 1686 (plusminus:MMXMODEI8
1f0dc22a
L		 1687 (match_operand:MMXMODEI8 1 "register_mmxmem_operand")
1688 (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))]
1689 "TARGET_MMX || TARGET_MMX_WITH_SSE"
1690 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1691
d54be5ad 1692(define_expand "<insn><mode>3"
1f0dc22a
L		 1693 [(set (match_operand:MMXMODEI 0 "register_operand")
1694 (plusminus:MMXMODEI
1695 (match_operand:MMXMODEI 1 "register_operand")
1696 (match_operand:MMXMODEI 2 "register_operand")))]
a617e5d5 1697 "TARGET_MMX_WITH_SSE")
333d8f61 1698
d54be5ad 1699(define_insn "*mmx_<insn><mode>3"
3bb345c9 1700 [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,<Yv_Yw>")
333d8f61 1701 (plusminus:MMXMODEI8
46ca31d6
UB		 1702 (match_operand:MMXMODEI8 1 "register_mmxmem_operand"
1703 "<comm>0,0,<Yv_Yw>")
1704 (match_operand:MMXMODEI8 2 "register_mmxmem_operand"
1705 "ym,x,<Yv_Yw>")))]
1f0dc22a 1706 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
333d8f61 1707 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1f0dc22a
L		 1708 "@
1709 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1710 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1711 vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 1712 [(set_attr "isa" "*,sse2_noavx,avx")
1713 (set_attr "mmx_isa" "native,*,*")
1f0dc22a
L		 1714 (set_attr "type" "mmxadd,sseadd,sseadd")
1715 (set_attr "mode" "DI,TI,TI")])
80e8bb90 1716
46ca31d6
UB		 1717(define_expand "neg<mode>2"
1718 [(set (match_operand:VI_32 0 "register_operand")
1719 (minus:VI_32
1720 (match_dup 2)
1721 (match_operand:VI_32 1 "register_operand")))]
1722 "TARGET_SSE2"
1723 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
1724
a617e5d5 1725(define_insn "<insn><mode>3"
507359e1 1726 [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
46ca31d6 1727 (plusminus:VI_32
507359e1
UB		 1728 (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
1729 (match_operand:VI_32 2 "register_operand" "x,Yw")))]
a617e5d5 1730 "TARGET_SSE2"
46ca31d6
UB		 1731 "@
1732 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1733 vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
1734 [(set_attr "isa" "noavx,avx")
1735 (set_attr "type" "sseadd")
1736 (set_attr "mode" "TI")])
1737
9ff206d3
UB		 1738(define_insn "<insn>v2qi3"
1739 [(set (match_operand:V2QI 0 "register_operand" "=Q,x,Yw")
1740 (plusminus:V2QI
1741 (match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
1742 (match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
1743 (clobber (reg:CC FLAGS_REG))]
1744 ""
1745 "#"
1746 [(set_attr "isa" "*,sse2_noavx,avx")
1747 (set_attr "type" "multi,sseadd,sseadd")
1748 (set_attr "mode" "QI,TI,TI")])
1749
1750(define_split
1751 [(set (match_operand:V2QI 0 "general_reg_operand")
1752 (plusminus:V2QI
1753 (match_operand:V2QI 1 "general_reg_operand")
1754 (match_operand:V2QI 2 "general_reg_operand")))
1755 (clobber (reg:CC FLAGS_REG))]
1756 "reload_completed"
1757 [(parallel
1758 [(set (strict_low_part (match_dup 0))
1759 (plusminus:QI (match_dup 1) (match_dup 2)))
1760 (clobber (reg:CC FLAGS_REG))])
1761 (parallel
1762 [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
1763 (subreg:HI
1764 (plusminus:QI
1765 (subreg:QI
1766 (zero_extract:HI (match_dup 4)
1767 (const_int 8)
1768 (const_int 8)) 0)
1769 (subreg:QI
1770 (zero_extract:HI (match_dup 5)
1771 (const_int 8)
1772 (const_int 8)) 0)) 0))
1773 (clobber (reg:CC FLAGS_REG))])]
1774{
1775 operands[5] = gen_lowpart (HImode, operands[2]);
1776 operands[4] = gen_lowpart (HImode, operands[1]);
1777 operands[3] = gen_lowpart (HImode, operands[0]);
1778 operands[2] = gen_lowpart (QImode, operands[2]);
1779 operands[1] = gen_lowpart (QImode, operands[1]);
1780 operands[0] = gen_lowpart (QImode, operands[0]);
1781})
1782
1783(define_split
1784 [(set (match_operand:V2QI 0 "sse_reg_operand")
1785 (plusminus:V2QI
1786 (match_operand:V2QI 1 "sse_reg_operand")
1787 (match_operand:V2QI 2 "sse_reg_operand")))
1788 (clobber (reg:CC FLAGS_REG))]
1789 "TARGET_SSE2 && reload_completed"
1790 [(set (match_dup 0)
1791 (plusminus:V4QI (match_dup 1) (match_dup 2)))]
1792{
1793 operands[2] = gen_lowpart (V4QImode, operands[2]);
1794 operands[1] = gen_lowpart (V4QImode, operands[1]);
1795 operands[0] = gen_lowpart (V4QImode, operands[0]);
1796})
1797
d54be5ad 1798(define_expand "mmx_<insn><mode>3"
82e86dc6 1799 [(set (match_operand:MMXMODE12 0 "register_operand")
333d8f61 1800 (sat_plusminus:MMXMODE12
1f0dc22a
L		 1801 (match_operand:MMXMODE12 1 "register_mmxmem_operand")
1802 (match_operand:MMXMODE12 2 "register_mmxmem_operand")))]
1803 "TARGET_MMX || TARGET_MMX_WITH_SSE"
333d8f61 1804 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
80e8bb90 1805
d54be5ad 1806(define_insn "*mmx_<insn><mode>3"
3bb345c9 1807 [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yw")
333d8f61 1808 (sat_plusminus:MMXMODE12
3bb345c9
JJ		 1809 (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yw")
1810 (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yw")))]
1f0dc22a
L		 1811 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1812 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1813 "@
1814 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1815 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1816 vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 1817 [(set_attr "isa" "*,sse2_noavx,avx")
1818 (set_attr "mmx_isa" "native,*,*")
1f0dc22a
L		 1819 (set_attr "type" "mmxadd,sseadd,sseadd")
1820 (set_attr "mode" "DI,TI,TI")])
80e8bb90 1821
2df9d3c5
UB		 1822(define_insn "*<insn><mode>3"
1823 [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
1824 (sat_plusminus:VI_32
1825 (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
1826 (match_operand:VI_32 2 "register_operand" "x,Yw")))]
a617e5d5 1827 "TARGET_SSE2"
2df9d3c5
UB		 1828 "@
1829 p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
1830 vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
1831 [(set_attr "isa" "noavx,avx")
1832 (set_attr "type" "sseadd")
1833 (set_attr "mode" "TI")])
1834
333d8f61 1835(define_expand "mmx_mulv4hi3"
82e86dc6 1836 [(set (match_operand:V4HI 0 "register_operand")
08266db9
L		 1837 (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand")
1838 (match_operand:V4HI 2 "register_mmxmem_operand")))]
1839 "TARGET_MMX || TARGET_MMX_WITH_SSE"
1840 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
1841
1842(define_expand "mulv4hi3"
1843 [(set (match_operand:V4HI 0 "register_operand")
1844 (mult:V4HI (match_operand:V4HI 1 "register_operand")
1845 (match_operand:V4HI 2 "register_operand")))]
a617e5d5 1846 "TARGET_MMX_WITH_SSE")
80e8bb90 1847
d0b48c67 1848(define_insn "*mmx_mulv4hi3"
3bb345c9
JJ		 1849 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
1850 (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
1851 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
08266db9
L		 1852 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1853 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
1854 "@
1855 pmullw\t{%2, %0|%0, %2}
1856 pmullw\t{%2, %0|%0, %2}
1857 vpmullw\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 1858 [(set_attr "isa" "*,sse2_noavx,avx")
1859 (set_attr "mmx_isa" "native,*,*")
08266db9
L		 1860 (set_attr "type" "mmxmul,ssemul,ssemul")
1861 (set_attr "mode" "DI,TI,TI")])
80e8bb90 1862
a617e5d5 1863(define_insn "mulv2hi3"
46ca31d6
UB		 1864 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
1865 (mult:V2HI (match_operand:V2HI 1 "register_operand" "%0,Yw")
1866 (match_operand:V2HI 2 "register_operand" "x,Yw")))]
a617e5d5 1867 "TARGET_SSE2"
46ca31d6
UB		 1868 "@
1869 pmullw\t{%2, %0|%0, %2}
1870 vpmullw\t{%2, %1, %0|%0, %1, %2}"
1871 [(set_attr "isa" "noavx,avx")
1872 (set_attr "type" "ssemul")
1873 (set_attr "mode" "TI")])
1874
333d8f61 1875(define_expand "mmx_smulv4hi3_highpart"
82e86dc6 1876 [(set (match_operand:V4HI 0 "register_operand")
333d8f61
UB		 1877 (truncate:V4HI
1878 (lshiftrt:V4SI
1879 (mult:V4SI
1880 (sign_extend:V4SI
3fdce4b1 1881 (match_operand:V4HI 1 "register_mmxmem_operand"))
333d8f61 1882 (sign_extend:V4SI
3fdce4b1 1883 (match_operand:V4HI 2 "register_mmxmem_operand")))
333d8f61 1884 (const_int 16))))]
3fdce4b1 1885 "TARGET_MMX || TARGET_MMX_WITH_SSE"
333d8f61
UB		 1886 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
1887
d0b48c67 1888(define_insn "*mmx_smulv4hi3_highpart"
3bb345c9 1889 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90 1890 (truncate:V4HI
333d8f61
UB		 1891 (lshiftrt:V4SI
1892 (mult:V4SI
1893 (sign_extend:V4SI
3bb345c9 1894 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
333d8f61 1895 (sign_extend:V4SI
3bb345c9 1896 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
333d8f61 1897 (const_int 16))))]
3fdce4b1
L		 1898 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1899 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
1900 "@
1901 pmulhw\t{%2, %0|%0, %2}
1902 pmulhw\t{%2, %0|%0, %2}
1903 vpmulhw\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 1904 [(set_attr "isa" "*,sse2_noavx,avx")
1905 (set_attr "mmx_isa" "native,*,*")
3fdce4b1
L		 1906 (set_attr "type" "mmxmul,ssemul,ssemul")
1907 (set_attr "mode" "DI,TI,TI")])
80e8bb90 1908
333d8f61 1909(define_expand "mmx_umulv4hi3_highpart"
82e86dc6 1910 [(set (match_operand:V4HI 0 "register_operand")
333d8f61
UB		 1911 (truncate:V4HI
1912 (lshiftrt:V4SI
1913 (mult:V4SI
1914 (zero_extend:V4SI
9377b54a 1915 (match_operand:V4HI 1 "register_mmxmem_operand"))
333d8f61 1916 (zero_extend:V4SI
9377b54a 1917 (match_operand:V4HI 2 "register_mmxmem_operand")))
333d8f61 1918 (const_int 16))))]
9377b54a
L		 1919 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1920 && (TARGET_SSE || TARGET_3DNOW_A)"
333d8f61
UB		 1921 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
1922
d0b48c67 1923(define_insn "*mmx_umulv4hi3_highpart"
3bb345c9 1924 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90 1925 (truncate:V4HI
333d8f61
UB		 1926 (lshiftrt:V4SI
1927 (mult:V4SI
1928 (zero_extend:V4SI
3bb345c9 1929 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
333d8f61 1930 (zero_extend:V4SI
3bb345c9 1931 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
80e8bb90 1932 (const_int 16))))]
9377b54a
L		 1933 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1934 && (TARGET_SSE || TARGET_3DNOW_A)
80e8bb90 1935 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
9377b54a
L		 1936 "@
1937 pmulhuw\t{%2, %0|%0, %2}
1938 pmulhuw\t{%2, %0|%0, %2}
1939 vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 1940 [(set_attr "isa" "*,sse2_noavx,avx")
1941 (set_attr "mmx_isa" "native,*,*")
9377b54a
L		 1942 (set_attr "type" "mmxmul,ssemul,ssemul")
1943 (set_attr "mode" "DI,TI,TI")])
80e8bb90 1944
507359e1
UB		 1945(define_expand "<s>mulv4hi3_highpart"
1946 [(set (match_operand:V4HI 0 "register_operand")
1947 (truncate:V4HI
1948 (lshiftrt:V4SI
1949 (mult:V4SI
1950 (any_extend:V4SI
1951 (match_operand:V4HI 1 "register_operand"))
1952 (any_extend:V4SI
1953 (match_operand:V4HI 2 "register_operand")))
1954 (const_int 16))))]
a617e5d5 1955 "TARGET_MMX_WITH_SSE")
507359e1 1956
a617e5d5 1957(define_insn "<s>mulv2hi3_highpart"
507359e1
UB		 1958 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
1959 (truncate:V2HI
1960 (lshiftrt:V2SI
1961 (mult:V2SI
1962 (any_extend:V2SI
1963 (match_operand:V2HI 1 "register_operand" "%0,Yw"))
1964 (any_extend:V2SI
1965 (match_operand:V2HI 2 "register_operand" "x,Yw")))
1966 (const_int 16))))]
a617e5d5 1967 "TARGET_SSE2"
507359e1
UB		 1968 "@
1969 pmulh<u>w\t{%2, %0|%0, %2}
1970 vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
1971 [(set_attr "isa" "noavx,avx")
1972 (set_attr "type" "ssemul")
1973 (set_attr "mode" "TI")])
1974
ffbaf337 1975(define_expand "mmx_pmaddwd"
82e86dc6 1976 [(set (match_operand:V2SI 0 "register_operand")
ffbaf337
UB		 1977 (plus:V2SI
1978 (mult:V2SI
1979 (sign_extend:V2SI
1980 (vec_select:V2HI
d0e9bf2a 1981 (match_operand:V4HI 1 "register_mmxmem_operand")
ffbaf337
UB		 1982 (parallel [(const_int 0) (const_int 2)])))
1983 (sign_extend:V2SI
1984 (vec_select:V2HI
d0e9bf2a 1985 (match_operand:V4HI 2 "register_mmxmem_operand")
ffbaf337
UB		 1986 (parallel [(const_int 0) (const_int 2)]))))
1987 (mult:V2SI
1988 (sign_extend:V2SI
1989 (vec_select:V2HI (match_dup 1)
1990 (parallel [(const_int 1) (const_int 3)])))
1991 (sign_extend:V2SI
1992 (vec_select:V2HI (match_dup 2)
1993 (parallel [(const_int 1) (const_int 3)]))))))]
d0e9bf2a 1994 "TARGET_MMX || TARGET_MMX_WITH_SSE"
ffbaf337
UB		 1995 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
1996
1997(define_insn "*mmx_pmaddwd"
3bb345c9 1998 [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 1999 (plus:V2SI
2000 (mult:V2SI
2001 (sign_extend:V2SI
2002 (vec_select:V2HI
3bb345c9 2003 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
80e8bb90
RH		 2004 (parallel [(const_int 0) (const_int 2)])))
2005 (sign_extend:V2SI
2006 (vec_select:V2HI
3bb345c9 2007 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")
80e8bb90
RH		 2008 (parallel [(const_int 0) (const_int 2)]))))
2009 (mult:V2SI
2010 (sign_extend:V2SI
2011 (vec_select:V2HI (match_dup 1)
2012 (parallel [(const_int 1) (const_int 3)])))
2013 (sign_extend:V2SI
2014 (vec_select:V2HI (match_dup 2)
2015 (parallel [(const_int 1) (const_int 3)]))))))]
d0e9bf2a
L		 2016 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2017 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
2018 "@
2019 pmaddwd\t{%2, %0|%0, %2}
2020 pmaddwd\t{%2, %0|%0, %2}
2021 vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2022 [(set_attr "isa" "*,sse2_noavx,avx")
2023 (set_attr "mmx_isa" "native,*,*")
d0e9bf2a
L		 2024 (set_attr "type" "mmxmul,sseiadd,sseiadd")
2025 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2026
ffbaf337 2027(define_expand "mmx_pmulhrwv4hi3"
82e86dc6 2028 [(set (match_operand:V4HI 0 "register_operand")
ffbaf337
UB		 2029 (truncate:V4HI
2030 (lshiftrt:V4SI
2031 (plus:V4SI
2032 (mult:V4SI
2033 (sign_extend:V4SI
82e86dc6 2034 (match_operand:V4HI 1 "nonimmediate_operand"))
ffbaf337 2035 (sign_extend:V4SI
82e86dc6 2036 (match_operand:V4HI 2 "nonimmediate_operand")))
ffbaf337
UB		 2037 (const_vector:V4SI [(const_int 32768) (const_int 32768)
2038 (const_int 32768) (const_int 32768)]))
2039 (const_int 16))))]
2040 "TARGET_3DNOW"
2041 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
2042
2043(define_insn "*mmx_pmulhrwv4hi3"
80e8bb90
RH		 2044 [(set (match_operand:V4HI 0 "register_operand" "=y")
2045 (truncate:V4HI
2046 (lshiftrt:V4SI
2047 (plus:V4SI
2048 (mult:V4SI
2049 (sign_extend:V4SI
2050 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
2051 (sign_extend:V4SI
2052 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
2053 (const_vector:V4SI [(const_int 32768) (const_int 32768)
2054 (const_int 32768) (const_int 32768)]))
2055 (const_int 16))))]
2056 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
333d8f61 2057 "pmulhrw\t{%2, %0|%0, %2}"
80e8bb90 2058 [(set_attr "type" "mmxmul")
725fd454 2059 (set_attr "prefix_extra" "1")
80e8bb90
RH		 2060 (set_attr "mode" "DI")])
2061
ffbaf337 2062(define_expand "sse2_umulv1siv1di3"
82e86dc6 2063 [(set (match_operand:V1DI 0 "register_operand")
ffbaf337
UB		 2064 (mult:V1DI
2065 (zero_extend:V1DI
2066 (vec_select:V1SI
66248623 2067 (match_operand:V2SI 1 "register_mmxmem_operand")
ffbaf337
UB		 2068 (parallel [(const_int 0)])))
2069 (zero_extend:V1DI
2070 (vec_select:V1SI
66248623 2071 (match_operand:V2SI 2 "register_mmxmem_operand")
ffbaf337 2072 (parallel [(const_int 0)])))))]
66248623 2073 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
ffbaf337
UB		 2074 "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
2075
2076(define_insn "*sse2_umulv1siv1di3"
66248623 2077 [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
ab555a5b
UB		 2078 (mult:V1DI
2079 (zero_extend:V1DI
2080 (vec_select:V1SI
66248623 2081 (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
80e8bb90 2082 (parallel [(const_int 0)])))
ab555a5b
UB		 2083 (zero_extend:V1DI
2084 (vec_select:V1SI
66248623 2085 (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
80e8bb90 2086 (parallel [(const_int 0)])))))]
66248623
L		 2087 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2088 && TARGET_SSE2
2089 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
2090 "@
2091 pmuludq\t{%2, %0|%0, %2}
2092 pmuludq\t{%2, %0|%0, %2}
2093 vpmuludq\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2094 [(set_attr "isa" "*,sse2_noavx,avx")
2095 (set_attr "mmx_isa" "native,*,*")
66248623
L		 2096 (set_attr "type" "mmxmul,ssemul,ssemul")
2097 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2098
dcde8113
UB		 2099;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2100;;
2101;; Parallel integral shifts
2102;;
2103;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
f3661f2d 2104
a617e5d5 2105(define_insn "<code><mode>3"
f3661f2d
UB		 2106 [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
2107 (smaxmin:MMXMODE14
2108 (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
2109 (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
a617e5d5 2110 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
f3661f2d
UB		 2111 "@
2112 p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
2113 p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
2114 vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
2115 [(set_attr "isa" "noavx,noavx,avx")
2116 (set_attr "type" "sseiadd")
2117 (set_attr "prefix_extra" "1,1,*")
2118 (set_attr "prefix" "orig,orig,vex")
2119 (set_attr "mode" "TI")])
2120
333d8f61 2121(define_expand "mmx_<code>v4hi3"
82e86dc6 2122 [(set (match_operand:V4HI 0 "register_operand")
333d8f61 2123 (smaxmin:V4HI
18184fdd
L		 2124 (match_operand:V4HI 1 "register_mmxmem_operand")
2125 (match_operand:V4HI 2 "register_mmxmem_operand")))]
2126 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2127 && (TARGET_SSE || TARGET_3DNOW_A)"
2128 "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
2129
d0b48c67 2130(define_insn "*mmx_<code>v4hi3"
3bb345c9 2131 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
78e8956b 2132 (smaxmin:V4HI
3bb345c9
JJ		 2133 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
2134 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
18184fdd
L		 2135 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2136 && (TARGET_SSE || TARGET_3DNOW_A)
333d8f61 2137 && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
18184fdd
L		 2138 "@
2139 p<maxmin_int>w\t{%2, %0|%0, %2}
2140 p<maxmin_int>w\t{%2, %0|%0, %2}
2141 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2142 [(set_attr "isa" "*,sse2_noavx,avx")
2143 (set_attr "mmx_isa" "native,*,*")
18184fdd
L		 2144 (set_attr "type" "mmxadd,sseiadd,sseiadd")
2145 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2146
a617e5d5
UB		 2147(define_expand "<code>v4hi3"
2148 [(set (match_operand:V4HI 0 "register_operand")
2149 (smaxmin:V4HI
2150 (match_operand:V4HI 1 "register_operand")
2151 (match_operand:V4HI 2 "register_operand")))]
2152 "TARGET_MMX_WITH_SSE")
f3661f2d 2153
a617e5d5 2154(define_insn "<code>v4qi3"
dcde8113
UB		 2155 [(set (match_operand:V4QI 0 "register_operand" "=Yr,*x,Yv")
2156 (smaxmin:V4QI
2157 (match_operand:V4QI 1 "register_operand" "%0,0,Yv")
2158 (match_operand:V4QI 2 "register_operand" "Yr,*x,Yv")))]
a617e5d5 2159 "TARGET_SSE4_1"
dcde8113
UB		 2160 "@
2161 p<maxmin_int>b\t{%2, %0|%0, %2}
2162 p<maxmin_int>b\t{%2, %0|%0, %2}
2163 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
2164 [(set_attr "isa" "noavx,noavx,avx")
2165 (set_attr "type" "sseiadd")
2166 (set_attr "prefix_extra" "1,1,*")
2167 (set_attr "prefix" "orig,orig,vex")
2168 (set_attr "mode" "TI")])
2169
a617e5d5 2170(define_insn "<code>v2hi3"
dcde8113
UB		 2171 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
2172 (smaxmin:V2HI
2173 (match_operand:V2HI 1 "register_operand" "%0,Yw")
2174 (match_operand:V2HI 2 "register_operand" "x,Yw")))]
a617e5d5 2175 "TARGET_SSE2"
dcde8113
UB		 2176 "@
2177 p<maxmin_int>w\t{%2, %0|%0, %2}
2178 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
2179 [(set_attr "isa" "noavx,avx")
2180 (set_attr "type" "sseiadd")
2181 (set_attr "mode" "TI")])
2182
a617e5d5 2183(define_insn "<code><mode>3"
f3661f2d
UB		 2184 [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
2185 (umaxmin:MMXMODE24
2186 (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
2187 (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
a617e5d5 2188 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
f3661f2d
UB		 2189 "@
2190 p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
2191 p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
2192 vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
2193 [(set_attr "isa" "noavx,noavx,avx")
2194 (set_attr "type" "sseiadd")
2195 (set_attr "prefix_extra" "1,1,*")
2196 (set_attr "prefix" "orig,orig,vex")
2197 (set_attr "mode" "TI")])
2198
333d8f61 2199(define_expand "mmx_<code>v8qi3"
82e86dc6 2200 [(set (match_operand:V8QI 0 "register_operand")
333d8f61 2201 (umaxmin:V8QI
18184fdd
L		 2202 (match_operand:V8QI 1 "register_mmxmem_operand")
2203 (match_operand:V8QI 2 "register_mmxmem_operand")))]
2204 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2205 && (TARGET_SSE || TARGET_3DNOW_A)"
2206 "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
2207
d0b48c67 2208(define_insn "*mmx_<code>v8qi3"
3bb345c9 2209 [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
78e8956b 2210 (umaxmin:V8QI
3bb345c9
JJ		 2211 (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
2212 (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))]
18184fdd
L		 2213 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2214 && (TARGET_SSE || TARGET_3DNOW_A)
333d8f61 2215 && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
18184fdd
L		 2216 "@
2217 p<maxmin_int>b\t{%2, %0|%0, %2}
2218 p<maxmin_int>b\t{%2, %0|%0, %2}
2219 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2220 [(set_attr "isa" "*,sse2_noavx,avx")
2221 (set_attr "mmx_isa" "native,*,*")
18184fdd
L		 2222 (set_attr "type" "mmxadd,sseiadd,sseiadd")
2223 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2224
a617e5d5
UB		 2225(define_expand "<code>v8qi3"
2226 [(set (match_operand:V8QI 0 "register_operand")
2227 (umaxmin:V8QI
2228 (match_operand:V8QI 1 "register_operand")
2229 (match_operand:V8QI 2 "register_operand")))]
2230 "TARGET_MMX_WITH_SSE")
dcde8113 2231
a617e5d5 2232(define_insn "<code>v4qi3"
dcde8113
UB		 2233 [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
2234 (umaxmin:V4QI
2235 (match_operand:V4QI 1 "register_operand" "%0,Yw")
2236 (match_operand:V4QI 2 "register_operand" "x,Yw")))]
a617e5d5 2237 "TARGET_SSE2"
dcde8113
UB		 2238 "@
2239 p<maxmin_int>b\t{%2, %0|%0, %2}
2240 vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
2241 [(set_attr "isa" "noavx,avx")
2242 (set_attr "type" "sseiadd")
2243 (set_attr "mode" "TI")])
2244
a617e5d5 2245(define_insn "<code>v2hi3"
dcde8113
UB		 2246 [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yv")
2247 (umaxmin:V2HI
2248 (match_operand:V2HI 1 "register_operand" "%0,0,Yv")
2249 (match_operand:V2HI 2 "register_operand" "Yr,*x,Yv")))]
a617e5d5 2250 "TARGET_SSE4_1"
dcde8113
UB		 2251 "@
2252 p<maxmin_int>w\t{%2, %0|%0, %2}
2253 p<maxmin_int>w\t{%2, %0|%0, %2}
2254 vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
2255 [(set_attr "isa" "noavx,noavx,avx")
2256 (set_attr "type" "sseiadd")
2257 (set_attr "prefix_extra" "1,1,*")
2258 (set_attr "prefix" "orig,orig,vex")
2259 (set_attr "mode" "TI")])
2260
dcde8113
UB		 2261(define_insn "ssse3_abs<mode>2"
2262 [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
2263 (abs:MMXMODEI
2264 (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))]
2265 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
2266 "@
2267 pabs<mmxvecsize>\t{%1, %0|%0, %1}
2268 %vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
2269 [(set_attr "mmx_isa" "native,*")
2270 (set_attr "type" "sselog1")
2271 (set_attr "prefix_rep" "0")
2272 (set_attr "prefix_extra" "1")
2273 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
2274 (set_attr "mode" "DI,TI")])
2275
2276(define_expand "abs<mode>2"
2277 [(set (match_operand:MMXMODEI 0 "register_operand")
2278 (abs:MMXMODEI
2279 (match_operand:MMXMODEI 1 "register_operand")))]
a617e5d5 2280 "TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
dcde8113
UB		 2281
2282(define_insn "abs<mode>2"
2283 [(set (match_operand:VI_32 0 "register_operand" "=Yv")
2284 (abs:VI_32
2285 (match_operand:VI_32 1 "register_operand" "Yv")))]
2286 "TARGET_SSSE3"
2287 "%vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
2288 [(set_attr "type" "sselog1")
2289 (set_attr "prefix_rep" "0")
2290 (set_attr "prefix_extra" "1")
2291 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
2292 (set_attr "mode" "TI")])
2293
2294;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2295;;
2296;; Parallel integral shifts
2297;;
2298;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2299
80e8bb90 2300(define_insn "mmx_ashr<mode>3"
3bb345c9 2301 [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,<Yv_Yw>")
80e8bb90 2302 (ashiftrt:MMXMODE24
3bb345c9
JJ		 2303 (match_operand:MMXMODE24 1 "register_operand" "0,0,<Yv_Yw>")
2304 (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
5d48867b
L		 2305 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2306 "@
2307 psra<mmxvecsize>\t{%2, %0|%0, %2}
2308 psra<mmxvecsize>\t{%2, %0|%0, %2}
2309 vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2310 [(set_attr "isa" "*,sse2_noavx,avx")
2311 (set_attr "mmx_isa" "native,*,*")
5d48867b 2312 (set_attr "type" "mmxshft,sseishft,sseishft")
725fd454 2313 (set (attr "length_immediate")
82e86dc6 2314 (if_then_else (match_operand 2 "const_int_operand")
725fd454
JJ		 2315 (const_string "1")
2316 (const_string "0")))
5d48867b
L		 2317 (set_attr "mode" "DI,TI,TI")])
2318
2319(define_expand "ashr<mode>3"
2320 [(set (match_operand:MMXMODE24 0 "register_operand")
2321 (ashiftrt:MMXMODE24
2322 (match_operand:MMXMODE24 1 "register_operand")
2323 (match_operand:DI 2 "nonmemory_operand")))]
2324 "TARGET_MMX_WITH_SSE")
80e8bb90 2325
d54be5ad 2326(define_insn "mmx_<insn><mode>3"
3bb345c9 2327 [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,<Yv_Yw>")
1162730f 2328 (any_lshift:MMXMODE248
3bb345c9
JJ		 2329 (match_operand:MMXMODE248 1 "register_operand" "0,0,<Yv_Yw>")
2330 (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
5d48867b
L		 2331 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2332 "@
2333 p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
2334 p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
2335 vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2336 [(set_attr "isa" "*,sse2_noavx,avx")
2337 (set_attr "mmx_isa" "native,*,*")
5d48867b 2338 (set_attr "type" "mmxshft,sseishft,sseishft")
725fd454 2339 (set (attr "length_immediate")
82e86dc6 2340 (if_then_else (match_operand 2 "const_int_operand")
725fd454
JJ		 2341 (const_string "1")
2342 (const_string "0")))
5d48867b
L		 2343 (set_attr "mode" "DI,TI,TI")])
2344
d54be5ad 2345(define_expand "<insn><mode>3"
1b5572ed
JJ		 2346 [(set (match_operand:MMXMODE24 0 "register_operand")
2347 (any_lshift:MMXMODE24
2348 (match_operand:MMXMODE24 1 "register_operand")
5d48867b
L		 2349 (match_operand:DI 2 "nonmemory_operand")))]
2350 "TARGET_MMX_WITH_SSE")
80e8bb90 2351
663a014e
UB		 2352(define_insn "mmx_<insn>v1si3"
2353 [(set (match_operand:V1SI 0 "register_operand" "=x,Yw")
2354 (any_lshift:V1SI
2355 (match_operand:V1SI 1 "register_operand" "0,Yw")
2356 (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
2357 "TARGET_SSE2"
2358 "@
2359 p<vshift>d\t{%2, %0|%0, %2}
2360 vp<vshift>d\t{%2, %1, %0|%0, %1, %2}"
2361 [(set_attr "isa" "noavx,avx")
2362 (set_attr "type" "sseishft")
2363 (set (attr "length_immediate")
2364 (if_then_else (match_operand 2 "const_int_operand")
2365 (const_string "1")
2366 (const_string "0")))
2367 (set_attr "mode" "TI")])
2368
a617e5d5 2369(define_insn "<insn>v2hi3"
507359e1
UB		 2370 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
2371 (any_shift:V2HI
2372 (match_operand:V2HI 1 "register_operand" "0,Yw")
2373 (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
2374 "TARGET_SSE2"
2375 "@
2376 p<vshift>w\t{%2, %0|%0, %2}
2377 vp<vshift>w\t{%2, %1, %0|%0, %1, %2}"
2378 [(set_attr "isa" "noavx,avx")
2379 (set_attr "type" "sseishft")
2380 (set (attr "length_immediate")
2381 (if_then_else (match_operand 2 "const_int_operand")
2382 (const_string "1")
2383 (const_string "0")))
2384 (set_attr "mode" "TI")])
2385
80e8bb90
RH		 2386;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2387;;
2388;; Parallel integral comparisons
2389;;
2390;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2391
ffbaf337 2392(define_expand "mmx_eq<mode>3"
82e86dc6 2393 [(set (match_operand:MMXMODEI 0 "register_operand")
ffbaf337 2394 (eq:MMXMODEI
2629da83
L		 2395 (match_operand:MMXMODEI 1 "register_mmxmem_operand")
2396 (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
2397 "TARGET_MMX || TARGET_MMX_WITH_SSE"
ffbaf337
UB		 2398 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
2399
2400(define_insn "*mmx_eq<mode>3"
3bb345c9 2401 [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
80e8bb90 2402 (eq:MMXMODEI
3bb345c9
JJ		 2403 (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x")
2404 (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
2629da83
L		 2405 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2406 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
2407 "@
2408 pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
2409 pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
2410 vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2411 [(set_attr "isa" "*,sse2_noavx,avx")
2412 (set_attr "mmx_isa" "native,*,*")
2629da83
L		 2413 (set_attr "type" "mmxcmp,ssecmp,ssecmp")
2414 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2415
2df9d3c5
UB		 2416(define_insn "*eq<mode>3"
2417 [(set (match_operand:VI_32 0 "register_operand" "=x,x")
2418 (eq:VI_32
2419 (match_operand:VI_32 1 "register_operand" "%0,x")
2420 (match_operand:VI_32 2 "register_operand" "x,x")))]
a617e5d5 2421 "TARGET_SSE2"
2df9d3c5
UB		 2422 "@
2423 pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
2424 vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
2425 [(set_attr "isa" "noavx,avx")
2426 (set_attr "type" "ssecmp")
2427 (set_attr "mode" "TI")])
2428
80e8bb90 2429(define_insn "mmx_gt<mode>3"
3bb345c9 2430 [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
80e8bb90 2431 (gt:MMXMODEI
3bb345c9
JJ		 2432 (match_operand:MMXMODEI 1 "register_operand" "0,0,x")
2433 (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
2629da83
L		 2434 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2435 "@
2436 pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
2437 pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
2438 vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 2439 [(set_attr "isa" "*,sse2_noavx,avx")
2440 (set_attr "mmx_isa" "native,*,*")
2629da83
L		 2441 (set_attr "type" "mmxcmp,ssecmp,ssecmp")
2442 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2443
2df9d3c5
UB		 2444(define_insn "*gt<mode>3"
2445 [(set (match_operand:VI_32 0 "register_operand" "=x,x")
2446 (gt:VI_32
2447 (match_operand:VI_32 1 "register_operand" "0,x")
2448 (match_operand:VI_32 2 "register_operand" "x,x")))]
2449 "TARGET_SSE2"
2450 "@
2451 pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
2452 vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
2453 [(set_attr "isa" "noavx,avx")
2454 (set_attr "type" "ssecmp")
2455 (set_attr "mode" "TI")])
2456
6c67afaf
UB		 2457(define_insn "*xop_maskcmp<mode>3"
2458 [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
2459 (match_operator:MMXMODEI 1 "ix86_comparison_int_operator"
2460 [(match_operand:MMXMODEI 2 "register_operand" "x")
2461 (match_operand:MMXMODEI 3 "register_operand" "x")]))]
2462 "TARGET_XOP"
2463 "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
2464 [(set_attr "type" "sse4arg")
2465 (set_attr "prefix_data16" "0")
2466 (set_attr "prefix_rep" "0")
2467 (set_attr "prefix_extra" "2")
2468 (set_attr "length_immediate" "1")
2469 (set_attr "mode" "TI")])
2470
2471(define_insn "*xop_maskcmp<mode>3"
2472 [(set (match_operand:VI_32 0 "register_operand" "=x")
2473 (match_operator:VI_32 1 "ix86_comparison_int_operator"
2474 [(match_operand:VI_32 2 "register_operand" "x")
2475 (match_operand:VI_32 3 "register_operand" "x")]))]
2476 "TARGET_XOP"
2477 "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
2478 [(set_attr "type" "sse4arg")
2479 (set_attr "prefix_data16" "0")
2480 (set_attr "prefix_rep" "0")
2481 (set_attr "prefix_extra" "2")
2482 (set_attr "length_immediate" "1")
2483 (set_attr "mode" "TI")])
2484
2485(define_insn "*xop_maskcmp_uns<mode>3"
2486 [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
2487 (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator"
2488 [(match_operand:MMXMODEI 2 "register_operand" "x")
2489 (match_operand:MMXMODEI 3 "register_operand" "x")]))]
2490 "TARGET_XOP"
2491 "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
2492 [(set_attr "type" "ssecmp")
2493 (set_attr "prefix_data16" "0")
2494 (set_attr "prefix_rep" "0")
2495 (set_attr "prefix_extra" "2")
2496 (set_attr "length_immediate" "1")
2497 (set_attr "mode" "TI")])
2498
2499(define_insn "*xop_maskcmp_uns<mode>3"
2500 [(set (match_operand:VI_32 0 "register_operand" "=x")
2501 (match_operator:VI_32 1 "ix86_comparison_uns_operator"
2502 [(match_operand:VI_32 2 "register_operand" "x")
2503 (match_operand:VI_32 3 "register_operand" "x")]))]
2504 "TARGET_XOP"
2505 "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
2506 [(set_attr "type" "ssecmp")
2507 (set_attr "prefix_data16" "0")
2508 (set_attr "prefix_rep" "0")
2509 (set_attr "prefix_extra" "2")
2510 (set_attr "length_immediate" "1")
2511 (set_attr "mode" "TI")])
2512
f3661f2d
UB		 2513(define_expand "vec_cmp<mode><mode>"
2514 [(set (match_operand:MMXMODEI 0 "register_operand")
2515 (match_operator:MMXMODEI 1 ""
2516 [(match_operand:MMXMODEI 2 "register_operand")
2517 (match_operand:MMXMODEI 3 "register_operand")]))]
2518 "TARGET_MMX_WITH_SSE"
2519{
2520 bool ok = ix86_expand_int_vec_cmp (operands);
2521 gcc_assert (ok);
2522 DONE;
2523})
2524
2df9d3c5
UB		 2525(define_expand "vec_cmp<mode><mode>"
2526 [(set (match_operand:VI_32 0 "register_operand")
2527 (match_operator:VI_32 1 ""
2528 [(match_operand:VI_32 2 "register_operand")
2529 (match_operand:VI_32 3 "register_operand")]))]
2530 "TARGET_SSE2"
2531{
2532 bool ok = ix86_expand_int_vec_cmp (operands);
2533 gcc_assert (ok);
2534 DONE;
2535})
2536
f3661f2d
UB		 2537(define_expand "vec_cmpu<mode><mode>"
2538 [(set (match_operand:MMXMODEI 0 "register_operand")
2539 (match_operator:MMXMODEI 1 ""
2540 [(match_operand:MMXMODEI 2 "register_operand")
2541 (match_operand:MMXMODEI 3 "register_operand")]))]
2542 "TARGET_MMX_WITH_SSE"
2543{
2544 bool ok = ix86_expand_int_vec_cmp (operands);
2545 gcc_assert (ok);
2546 DONE;
2547})
2548
2df9d3c5
UB		 2549(define_expand "vec_cmpu<mode><mode>"
2550 [(set (match_operand:VI_32 0 "register_operand")
2551 (match_operator:VI_32 1 ""
2552 [(match_operand:VI_32 2 "register_operand")
2553 (match_operand:VI_32 3 "register_operand")]))]
2554 "TARGET_SSE2"
2555{
2556 bool ok = ix86_expand_int_vec_cmp (operands);
2557 gcc_assert (ok);
2558 DONE;
2559})
2560
b1f7fd8a
UB		 2561(define_expand "vcond<MMXMODE124:mode><MMXMODEI:mode>"
2562 [(set (match_operand:MMXMODE124 0 "register_operand")
2563 (if_then_else:MMXMODE124
f3661f2d
UB		 2564 (match_operator 3 ""
2565 [(match_operand:MMXMODEI 4 "register_operand")
2566 (match_operand:MMXMODEI 5 "register_operand")])
b1f7fd8a
UB		 2567 (match_operand:MMXMODE124 1)
2568 (match_operand:MMXMODE124 2)))]
2569 "TARGET_MMX_WITH_SSE
2570 && (GET_MODE_NUNITS (<MMXMODE124:MODE>mode)
2571 == GET_MODE_NUNITS (<MMXMODEI:MODE>mode))"
f3661f2d
UB		 2572{
2573 bool ok = ix86_expand_int_vcond (operands);
2574 gcc_assert (ok);
2575 DONE;
2576})
2577
2df9d3c5
UB		 2578(define_expand "vcond<mode><mode>"
2579 [(set (match_operand:VI_32 0 "register_operand")
2580 (if_then_else:VI_32
2581 (match_operator 3 ""
2582 [(match_operand:VI_32 4 "register_operand")
2583 (match_operand:VI_32 5 "register_operand")])
2584 (match_operand:VI_32 1)
2585 (match_operand:VI_32 2)))]
2586 "TARGET_SSE2"
2587{
2588 bool ok = ix86_expand_int_vcond (operands);
2589 gcc_assert (ok);
2590 DONE;
2591})
2592
b1f7fd8a
UB		 2593(define_expand "vcondu<MMXMODE124:mode><MMXMODEI:mode>"
2594 [(set (match_operand:MMXMODE124 0 "register_operand")
2595 (if_then_else:MMXMODE124
f3661f2d
UB		 2596 (match_operator 3 ""
2597 [(match_operand:MMXMODEI 4 "register_operand")
2598 (match_operand:MMXMODEI 5 "register_operand")])
b1f7fd8a
UB		 2599 (match_operand:MMXMODE124 1)
2600 (match_operand:MMXMODE124 2)))]
2601 "TARGET_MMX_WITH_SSE
2602 && (GET_MODE_NUNITS (<MMXMODE124:MODE>mode)
2603 == GET_MODE_NUNITS (<MMXMODEI:MODE>mode))"
f3661f2d
UB		 2604{
2605 bool ok = ix86_expand_int_vcond (operands);
2606 gcc_assert (ok);
2607 DONE;
2608})
2609
2df9d3c5
UB		 2610(define_expand "vcondu<mode><mode>"
2611 [(set (match_operand:VI_32 0 "register_operand")
2612 (if_then_else:VI_32
2613 (match_operator 3 ""
2614 [(match_operand:VI_32 4 "register_operand")
2615 (match_operand:VI_32 5 "register_operand")])
2616 (match_operand:VI_32 1)
2617 (match_operand:VI_32 2)))]
2618 "TARGET_SSE2"
2619{
2620 bool ok = ix86_expand_int_vcond (operands);
2621 gcc_assert (ok);
2622 DONE;
2623})
2624
b1f7fd8a
UB		 2625(define_expand "vcond_mask_<mode><mmxintvecmodelower>"
2626 [(set (match_operand:MMXMODE124 0 "register_operand")
2627 (vec_merge:MMXMODE124
2628 (match_operand:MMXMODE124 1 "register_operand")
2629 (match_operand:MMXMODE124 2 "register_operand")
2630 (match_operand:<mmxintvecmode> 3 "register_operand")))]
f3661f2d
UB		 2631 "TARGET_MMX_WITH_SSE"
2632{
2633 ix86_expand_sse_movcc (operands[0], operands[3],
2634 operands[1], operands[2]);
2635 DONE;
2636})
2637
2df9d3c5
UB		 2638(define_expand "vcond_mask_<mode><mode>"
2639 [(set (match_operand:VI_32 0 "register_operand")
2640 (vec_merge:VI_32
2641 (match_operand:VI_32 1 "register_operand")
2642 (match_operand:VI_32 2 "register_operand")
2643 (match_operand:VI_32 3 "register_operand")))]
2644 "TARGET_SSE2"
2645{
2646 ix86_expand_sse_movcc (operands[0], operands[3],
2647 operands[1], operands[2]);
2648 DONE;
2649})
2650
2651(define_insn "mmx_pblendvb64"
5795ec0e
UB		 2652 [(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x")
2653 (unspec:V8QI
2654 [(match_operand:V8QI 1 "register_operand" "0,0,x")
2655 (match_operand:V8QI 2 "register_operand" "Yr,*x,x")
2656 (match_operand:V8QI 3 "register_operand" "Yz,Yz,x")]
2657 UNSPEC_BLENDV))]
2658 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
2659 "@
2660 pblendvb\t{%3, %2, %0|%0, %2, %3}
2661 pblendvb\t{%3, %2, %0|%0, %2, %3}
2662 vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2663 [(set_attr "isa" "noavx,noavx,avx")
2664 (set_attr "type" "ssemov")
2665 (set_attr "prefix_extra" "1")
2666 (set_attr "length_immediate" "*,*,1")
2667 (set_attr "prefix" "orig,orig,vex")
2668 (set_attr "btver2_decode" "vector")
2669 (set_attr "mode" "TI")])
2670
2df9d3c5
UB		 2671(define_insn "mmx_pblendvb32"
2672 [(set (match_operand:V4QI 0 "register_operand" "=Yr,*x,x")
2673 (unspec:V4QI
2674 [(match_operand:V4QI 1 "register_operand" "0,0,x")
2675 (match_operand:V4QI 2 "register_operand" "Yr,*x,x")
2676 (match_operand:V4QI 3 "register_operand" "Yz,Yz,x")]
2677 UNSPEC_BLENDV))]
2678 "TARGET_SSE4_1"
2679 "@
2680 pblendvb\t{%3, %2, %0|%0, %2, %3}
2681 pblendvb\t{%3, %2, %0|%0, %2, %3}
2682 vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2683 [(set_attr "isa" "noavx,noavx,avx")
2684 (set_attr "type" "ssemov")
2685 (set_attr "prefix_extra" "1")
2686 (set_attr "length_immediate" "*,*,1")
2687 (set_attr "prefix" "orig,orig,vex")
2688 (set_attr "btver2_decode" "vector")
2689 (set_attr "mode" "TI")])
2690
323b18d5
JJ		 2691;; XOP parallel XMM conditional moves
2692(define_insn "*xop_pcmov_<mode>"
f1693741
UB		 2693 [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
2694 (if_then_else:MMXMODE124
2695 (match_operand:MMXMODE124 3 "register_operand" "x")
2696 (match_operand:MMXMODE124 1 "register_operand" "x")
2697 (match_operand:MMXMODE124 2 "register_operand" "x")))]
323b18d5
JJ		 2698 "TARGET_XOP && TARGET_MMX_WITH_SSE"
2699 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2700 [(set_attr "type" "sse4arg")])
2701
2df9d3c5
UB		 2702(define_insn "*xop_pcmov_<mode>"
2703 [(set (match_operand:VI_32 0 "register_operand" "=x")
2704 (if_then_else:VI_32
2705 (match_operand:VI_32 3 "register_operand" "x")
2706 (match_operand:VI_32 1 "register_operand" "x")
2707 (match_operand:VI_32 2 "register_operand" "x")))]
2708 "TARGET_XOP"
2709 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2710 [(set_attr "type" "sse4arg")])
2711
37e93925
UB		 2712;; XOP permute instructions
2713(define_insn "mmx_ppermv64"
2714 [(set (match_operand:V8QI 0 "register_operand" "=x")
2715 (unspec:V8QI
2716 [(match_operand:V8QI 1 "register_operand" "x")
2717 (match_operand:V8QI 2 "register_operand" "x")
2718 (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
2719 UNSPEC_XOP_PERMUTE))]
2720 "TARGET_XOP && TARGET_MMX_WITH_SSE"
2721 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2722 [(set_attr "type" "sse4arg")
2723 (set_attr "mode" "TI")])
2724
be8749f9
UB		 2725(define_insn "mmx_ppermv32"
2726 [(set (match_operand:V4QI 0 "register_operand" "=x")
2727 (unspec:V4QI
2728 [(match_operand:V4QI 1 "register_operand" "x")
2729 (match_operand:V4QI 2 "register_operand" "x")
2730 (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
2731 UNSPEC_XOP_PERMUTE))]
2732 "TARGET_XOP"
2733 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2734 [(set_attr "type" "sse4arg")
2735 (set_attr "mode" "TI")])
2736
80e8bb90
RH		 2737;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2738;;
2739;; Parallel integral logical operations
2740;;
2741;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2742
d826ea32
UB		 2743(define_expand "one_cmpl<mode>2"
2744 [(set (match_operand:MMXMODEI 0 "register_operand")
2745 (xor:MMXMODEI
2746 (match_operand:MMXMODEI 1 "register_operand")
2747 (match_dup 2)))]
2748 "TARGET_MMX_WITH_SSE"
2749 "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
2750
46ca31d6
UB		 2751(define_expand "one_cmpl<mode>2"
2752 [(set (match_operand:VI_32 0 "register_operand")
2753 (xor:VI_32
2754 (match_operand:VI_32 1 "register_operand")
2755 (match_dup 2)))]
2756 "TARGET_SSE2"
2757 "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
2758
c6d55c5b 2759(define_insn "mmx_andnot<mode>3"
a71f55c4 2760 [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
80e8bb90 2761 (and:MMXMODEI
a71f55c4
UB		 2762 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
2763 (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
df0e1979
L		 2764 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2765 "@
2766 pandn\t{%2, %0|%0, %2}
2767 pandn\t{%2, %0|%0, %2}
3bb345c9
JJ		 2768 vpandn\t{%2, %1, %0|%0, %1, %2}
2769 vpandnd\t{%2, %1, %0|%0, %1, %2}"
a71f55c4
UB		 2770 [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
2771 (set_attr "mmx_isa" "native,*,*,*")
2772 (set_attr "type" "mmxadd,sselog,sselog,sselog")
2773 (set_attr "mode" "DI,TI,TI,TI")])
80e8bb90 2774
46ca31d6 2775(define_insn "*andnot<mode>3"
a71f55c4 2776 [(set (match_operand:VI_32 0 "register_operand" "=x,x,v")
46ca31d6 2777 (and:VI_32
a71f55c4
UB		 2778 (not:VI_32 (match_operand:VI_32 1 "register_operand" "0,x,v"))
2779 (match_operand:VI_32 2 "register_operand" "x,x,v")))]
46ca31d6
UB		 2780 "TARGET_SSE2"
2781 "@
46ca31d6
UB		 2782 pandn\t{%2, %0|%0, %2}
2783 vpandn\t{%2, %1, %0|%0, %1, %2}
2784 vpandnd\t{%2, %1, %0|%0, %1, %2}"
a71f55c4
UB		 2785 [(set_attr "isa" "noavx,avx,avx512vl")
2786 (set_attr "type" "sselog")
2787 (set_attr "mode" "TI")])
46ca31d6 2788
333d8f61 2789(define_expand "mmx_<code><mode>3"
82e86dc6 2790 [(set (match_operand:MMXMODEI 0 "register_operand")
c8427064 2791 (any_logic:MMXMODEI
fff6304f
L		 2792 (match_operand:MMXMODEI 1 "register_mmxmem_operand")
2793 (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
2794 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2795 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
2796
2797(define_expand "<code><mode>3"
2798 [(set (match_operand:MMXMODEI 0 "register_operand")
2799 (any_logic:MMXMODEI
2800 (match_operand:MMXMODEI 1 "register_operand")
2801 (match_operand:MMXMODEI 2 "register_operand")))]
a617e5d5 2802 "TARGET_MMX_WITH_SSE")
333d8f61 2803
d0b48c67 2804(define_insn "*mmx_<code><mode>3"
a71f55c4 2805 [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
c8427064 2806 (any_logic:MMXMODEI
a71f55c4
UB		 2807 (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
2808 (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
fff6304f
L		 2809 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
2810 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
2811 "@
2812 p<logic>\t{%2, %0|%0, %2}
2813 p<logic>\t{%2, %0|%0, %2}
3bb345c9
JJ		 2814 vp<logic>\t{%2, %1, %0|%0, %1, %2}
2815 vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
a71f55c4
UB		 2816 [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
2817 (set_attr "mmx_isa" "native,*,*,*")
2818 (set_attr "type" "mmxadd,sselog,sselog,sselog")
2819 (set_attr "mode" "DI,TI,TI,TI")])
80e8bb90 2820
a617e5d5 2821(define_insn "<code><mode>3"
a71f55c4 2822 [(set (match_operand:VI_32 0 "register_operand" "=x,x,v")
46ca31d6 2823 (any_logic:VI_32
a71f55c4
UB		 2824 (match_operand:VI_32 1 "register_operand" "%0,x,v")
2825 (match_operand:VI_32 2 "register_operand" "x,x,v")))]
a617e5d5 2826 "TARGET_SSE2"
46ca31d6 2827 "@
46ca31d6
UB		 2828 p<logic>\t{%2, %0|%0, %2}
2829 vp<logic>\t{%2, %1, %0|%0, %1, %2}
2830 vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
a71f55c4
UB		 2831 [(set_attr "isa" "noavx,avx,avx512vl")
2832 (set_attr "type" "sselog")
2833 (set_attr "mode" "TI")])
46ca31d6 2834
80e8bb90
RH		 2835;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2836;;
2837;; Parallel integral element swizzling
2838;;
2839;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2840
b74ebb2a
L		 2841;; Used in signed and unsigned truncations with saturation.
2842(define_code_iterator any_s_truncate [ss_truncate us_truncate])
2843;; Instruction suffix for truncations with saturation.
2844(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")])
2845
2846(define_insn_and_split "mmx_pack<s_trunsuffix>swb"
3bb345c9 2847 [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
80e8bb90 2848 (vec_concat:V8QI
b74ebb2a 2849 (any_s_truncate:V4QI
3bb345c9 2850 (match_operand:V4HI 1 "register_operand" "0,0,Yw"))
b74ebb2a 2851 (any_s_truncate:V4QI
3bb345c9 2852 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
b74ebb2a
L		 2853 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2854 "@
2855 pack<s_trunsuffix>swb\t{%2, %0|%0, %2}
2856 #
2857 #"
a325bdd1 2858 "&& reload_completed
dab0477b 2859 && SSE_REGNO_P (REGNO (operands[0]))"
b74ebb2a
L		 2860 [(const_int 0)]
2861 "ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;"
b49ae8a5 2862 [(set_attr "mmx_isa" "native,sse_noavx,avx")
b74ebb2a
L		 2863 (set_attr "type" "mmxshft,sselog,sselog")
2864 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2865
b74ebb2a 2866(define_insn_and_split "mmx_packssdw"
3bb345c9 2867 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 2868 (vec_concat:V4HI
2869 (ss_truncate:V2HI
3bb345c9 2870 (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
80e8bb90 2871 (ss_truncate:V2HI
3bb345c9 2872 (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
b74ebb2a
L		 2873 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2874 "@
2875 packssdw\t{%2, %0|%0, %2}
2876 #
2877 #"
a325bdd1 2878 "&& reload_completed
dab0477b 2879 && SSE_REGNO_P (REGNO (operands[0]))"
b74ebb2a
L		 2880 [(const_int 0)]
2881 "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
b49ae8a5 2882 [(set_attr "mmx_isa" "native,sse_noavx,avx")
b74ebb2a
L		 2883 (set_attr "type" "mmxshft,sselog,sselog")
2884 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2885
dd835ec2
UB		 2886(define_insn_and_split "mmx_packusdw"
2887 [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
2888 (vec_concat:V4HI
2889 (us_truncate:V2HI
2890 (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
2891 (us_truncate:V2HI
2892 (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw"))))]
2893 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
2894 "#"
2895 "&& reload_completed"
2896 [(const_int 0)]
2897 "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
2898 [(set_attr "isa" "noavx,noavx,avx")
2899 (set_attr "type" "sselog")
2900 (set_attr "mode" "TI")])
2901
6e9fffcf 2902(define_insn_and_split "mmx_punpckhbw"
3bb345c9 2903 [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 2904 (vec_select:V8QI
2905 (vec_concat:V16QI
3bb345c9
JJ		 2906 (match_operand:V8QI 1 "register_operand" "0,0,Yw")
2907 (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
80e8bb90
RH		 2908 (parallel [(const_int 4) (const_int 12)
2909 (const_int 5) (const_int 13)
2910 (const_int 6) (const_int 14)
2911 (const_int 7) (const_int 15)])))]
6e9fffcf
L		 2912 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2913 "@
2914 punpckhbw\t{%2, %0|%0, %2}
2915 #
2916 #"
a325bdd1 2917 "&& reload_completed
dab0477b 2918 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 2919 [(const_int 0)]
2920 "ix86_split_mmx_punpck (operands, true); DONE;"
b49ae8a5 2921 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 2922 (set_attr "type" "mmxcvt,sselog,sselog")
2923 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2924
be8749f9
UB		 2925(define_insn_and_split "mmx_punpckhbw_low"
2926 [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
2927 (vec_select:V4QI
2928 (vec_concat:V8QI
2929 (match_operand:V4QI 1 "register_operand" "0,Yw")
2930 (match_operand:V4QI 2 "register_operand" "x,Yw"))
2931 (parallel [(const_int 2) (const_int 6)
2932 (const_int 3) (const_int 7)])))]
2933 "TARGET_SSE2"
2934 "#"
2935 "&& reload_completed"
2936 [(const_int 0)]
2937 "ix86_split_mmx_punpck (operands, true); DONE;"
2938 [(set_attr "isa" "noavx,avx")
2939 (set_attr "type" "sselog")
2940 (set_attr "mode" "TI")])
2941
6e9fffcf 2942(define_insn_and_split "mmx_punpcklbw"
3bb345c9 2943 [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 2944 (vec_select:V8QI
2945 (vec_concat:V16QI
3bb345c9
JJ		 2946 (match_operand:V8QI 1 "register_operand" "0,0,Yw")
2947 (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
80e8bb90
RH		 2948 (parallel [(const_int 0) (const_int 8)
2949 (const_int 1) (const_int 9)
2950 (const_int 2) (const_int 10)
2951 (const_int 3) (const_int 11)])))]
6e9fffcf
L		 2952 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2953 "@
2954 punpcklbw\t{%2, %0|%0, %k2}
2955 #
2956 #"
a325bdd1 2957 "&& reload_completed
dab0477b 2958 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 2959 [(const_int 0)]
2960 "ix86_split_mmx_punpck (operands, false); DONE;"
b49ae8a5 2961 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 2962 (set_attr "type" "mmxcvt,sselog,sselog")
2963 (set_attr "mode" "DI,TI,TI")])
80e8bb90 2964
be8749f9
UB		 2965(define_insn_and_split "mmx_punpcklbw_low"
2966 [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
2967 (vec_select:V4QI
2968 (vec_concat:V8QI
2969 (match_operand:V4QI 1 "register_operand" "0,Yw")
2970 (match_operand:V4QI 2 "register_operand" "x,Yw"))
2971 (parallel [(const_int 0) (const_int 4)
2972 (const_int 1) (const_int 5)])))]
2973 "TARGET_SSE2"
2974 "#"
2975 "&& reload_completed"
2976 [(const_int 0)]
2977 "ix86_split_mmx_punpck (operands, false); DONE;"
2978 [(set_attr "isa" "noavx,avx")
2979 (set_attr "type" "sselog")
2980 (set_attr "mode" "TI")])
2981
6e9fffcf 2982(define_insn_and_split "mmx_punpckhwd"
3bb345c9 2983 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 2984 (vec_select:V4HI
2985 (vec_concat:V8HI
3bb345c9
JJ		 2986 (match_operand:V4HI 1 "register_operand" "0,0,Yw")
2987 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
80e8bb90
RH		 2988 (parallel [(const_int 2) (const_int 6)
2989 (const_int 3) (const_int 7)])))]
6e9fffcf
L		 2990 "TARGET_MMX || TARGET_MMX_WITH_SSE"
2991 "@
2992 punpckhwd\t{%2, %0|%0, %2}
2993 #
2994 #"
a325bdd1 2995 "&& reload_completed
dab0477b 2996 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 2997 [(const_int 0)]
2998 "ix86_split_mmx_punpck (operands, true); DONE;"
b49ae8a5 2999 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 3000 (set_attr "type" "mmxcvt,sselog,sselog")
3001 (set_attr "mode" "DI,TI,TI")])
80e8bb90 3002
6e9fffcf 3003(define_insn_and_split "mmx_punpcklwd"
3bb345c9 3004 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 3005 (vec_select:V4HI
3006 (vec_concat:V8HI
3bb345c9
JJ		 3007 (match_operand:V4HI 1 "register_operand" "0,0,Yw")
3008 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
80e8bb90
RH		 3009 (parallel [(const_int 0) (const_int 4)
3010 (const_int 1) (const_int 5)])))]
6e9fffcf
L		 3011 "TARGET_MMX || TARGET_MMX_WITH_SSE"
3012 "@
3013 punpcklwd\t{%2, %0|%0, %k2}
3014 #
3015 #"
a325bdd1 3016 "&& reload_completed
dab0477b 3017 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 3018 [(const_int 0)]
3019 "ix86_split_mmx_punpck (operands, false); DONE;"
b49ae8a5 3020 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 3021 (set_attr "type" "mmxcvt,sselog,sselog")
3022 (set_attr "mode" "DI,TI,TI")])
80e8bb90 3023
6e9fffcf
L		 3024(define_insn_and_split "mmx_punpckhdq"
3025 [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
80e8bb90
RH		 3026 (vec_select:V2SI
3027 (vec_concat:V4SI
6e9fffcf
L		 3028 (match_operand:V2SI 1 "register_operand" "0,0,Yv")
3029 (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
80e8bb90
RH		 3030 (parallel [(const_int 1)
3031 (const_int 3)])))]
6e9fffcf
L		 3032 "TARGET_MMX || TARGET_MMX_WITH_SSE"
3033 "@
3034 punpckhdq\t{%2, %0|%0, %2}
3035 #
3036 #"
a325bdd1 3037 "&& reload_completed
dab0477b 3038 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 3039 [(const_int 0)]
3040 "ix86_split_mmx_punpck (operands, true); DONE;"
b49ae8a5 3041 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 3042 (set_attr "type" "mmxcvt,sselog,sselog")
3043 (set_attr "mode" "DI,TI,TI")])
80e8bb90 3044
6e9fffcf
L		 3045(define_insn_and_split "mmx_punpckldq"
3046 [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
80e8bb90
RH		 3047 (vec_select:V2SI
3048 (vec_concat:V4SI
6e9fffcf
L		 3049 (match_operand:V2SI 1 "register_operand" "0,0,Yv")
3050 (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
80e8bb90
RH		 3051 (parallel [(const_int 0)
3052 (const_int 2)])))]
6e9fffcf
L		 3053 "TARGET_MMX || TARGET_MMX_WITH_SSE"
3054 "@
3055 punpckldq\t{%2, %0|%0, %k2}
3056 #
3057 #"
a325bdd1 3058 "&& reload_completed
dab0477b 3059 && SSE_REGNO_P (REGNO (operands[0]))"
6e9fffcf
L		 3060 [(const_int 0)]
3061 "ix86_split_mmx_punpck (operands, false); DONE;"
b49ae8a5 3062 [(set_attr "mmx_isa" "native,sse_noavx,avx")
6e9fffcf
L		 3063 (set_attr "type" "mmxcvt,sselog,sselog")
3064 (set_attr "mode" "DI,TI,TI")])
80e8bb90 3065
836328b2
UB		 3066(define_insn "sse4_1_<code>v4qiv4hi2"
3067 [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
3068 (any_extend:V4HI
3069 (vec_select:V4QI
3070 (match_operand:V8QI 1 "register_operand" "Yr,*x,Yw")
3071 (parallel [(const_int 0) (const_int 1)
3072 (const_int 2) (const_int 3)]))))]
3073 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3074 "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
3075 [(set_attr "isa" "noavx,noavx,avx")
3076 (set_attr "type" "ssemov")
3077 (set_attr "prefix_extra" "1")
3078 (set_attr "prefix" "orig,orig,maybe_evex")
3079 (set_attr "mode" "TI")])
3080
3081(define_insn "sse4_1_<code>v2hiv2si2"
3082 [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
3083 (any_extend:V2SI
3084 (vec_select:V2HI
3085 (match_operand:V4HI 1 "register_operand" "Yr,*x,v")
3086 (parallel [(const_int 0) (const_int 1)]))))]
3087 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3088 "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
3089 [(set_attr "isa" "noavx,noavx,avx")
3090 (set_attr "type" "ssemov")
3091 (set_attr "prefix_extra" "1")
3092 (set_attr "prefix" "orig,orig,maybe_evex")
3093 (set_attr "mode" "TI")])
3094
663a014e
UB		 3095(define_insn "sse4_1_<code>v2qiv2hi2"
3096 [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yw")
3097 (any_extend:V2HI
3098 (vec_select:V2QI
3099 (match_operand:V4QI 1 "register_operand" "Yr,*x,Yw")
3100 (parallel [(const_int 0) (const_int 1)]))))]
3101 "TARGET_SSE4_1"
3102 "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
3103 [(set_attr "isa" "noavx,noavx,avx")
3104 (set_attr "type" "ssemov")
3105 (set_attr "prefix_extra" "1")
3106 (set_attr "prefix" "orig,orig,maybe_evex")
3107 (set_attr "mode" "TI")])
3108
836328b2
UB		 3109;; Pack/unpack vector modes
3110(define_mode_attr mmxpackmode
3111 [(V4HI "V8QI") (V2SI "V4HI")])
3112
3113(define_expand "vec_pack_trunc_<mode>"
3114 [(match_operand:<mmxpackmode> 0 "register_operand")
3115 (match_operand:MMXMODE24 1 "register_operand")
3116 (match_operand:MMXMODE24 2 "register_operand")]
3117 "TARGET_MMX_WITH_SSE"
3118{
3119 rtx op1 = gen_lowpart (<mmxpackmode>mode, operands[1]);
3120 rtx op2 = gen_lowpart (<mmxpackmode>mode, operands[2]);
3121 ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
3122 DONE;
3123})
3124
663a014e
UB		 3125(define_expand "vec_pack_trunc_v2hi"
3126 [(match_operand:V4QI 0 "register_operand")
3127 (match_operand:V2HI 1 "register_operand")
3128 (match_operand:V2HI 2 "register_operand")]
3129 "TARGET_SSE2"
3130{
3131 rtx op1 = gen_lowpart (V4QImode, operands[1]);
3132 rtx op2 = gen_lowpart (V4QImode, operands[2]);
3133 ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
3134 DONE;
3135})
3136
836328b2
UB		 3137(define_mode_attr mmxunpackmode
3138 [(V8QI "V4HI") (V4HI "V2SI")])
3139
3140(define_expand "vec_unpacks_lo_<mode>"
3141 [(match_operand:<mmxunpackmode> 0 "register_operand")
3142 (match_operand:MMXMODE12 1 "register_operand")]
3143 "TARGET_MMX_WITH_SSE"
3144 "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
3145
3146(define_expand "vec_unpacks_hi_<mode>"
3147 [(match_operand:<mmxunpackmode> 0 "register_operand")
3148 (match_operand:MMXMODE12 1 "register_operand")]
3149 "TARGET_MMX_WITH_SSE"
3150 "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
3151
3152(define_expand "vec_unpacku_lo_<mode>"
3153 [(match_operand:<mmxunpackmode> 0 "register_operand")
3154 (match_operand:MMXMODE12 1 "register_operand")]
3155 "TARGET_MMX_WITH_SSE"
3156 "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
3157
3158(define_expand "vec_unpacku_hi_<mode>"
3159 [(match_operand:<mmxunpackmode> 0 "register_operand")
3160 (match_operand:MMXMODE12 1 "register_operand")]
3161 "TARGET_MMX_WITH_SSE"
3162 "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
3163
663a014e
UB		 3164(define_expand "vec_unpacks_lo_v4qi"
3165 [(match_operand:V2HI 0 "register_operand")
3166 (match_operand:V4QI 1 "register_operand")]
3167 "TARGET_SSE2"
3168 "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
3169
3170(define_expand "vec_unpacks_hi_v4qi"
3171 [(match_operand:V2HI 0 "register_operand")
3172 (match_operand:V4QI 1 "register_operand")]
3173 "TARGET_SSE2"
3174 "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
3175
3176(define_expand "vec_unpacku_lo_v4qi"
3177 [(match_operand:V2HI 0 "register_operand")
3178 (match_operand:V4QI 1 "register_operand")]
3179 "TARGET_SSE2"
3180 "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
3181
3182(define_expand "vec_unpacku_hi_v4qi"
3183 [(match_operand:V2HI 0 "register_operand")
3184 (match_operand:V4QI 1 "register_operand")]
3185 "TARGET_SSE2"
3186 "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
3187
f15c7bd1
UB		 3188(define_insn "*mmx_pinsrd"
3189 [(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
3190 (vec_merge:V2SI
3191 (vec_duplicate:V2SI
3192 (match_operand:SI 2 "nonimmediate_operand" "rm,rm"))
3193 (match_operand:V2SI 1 "register_operand" "0,Yv")
3194 (match_operand:SI 3 "const_int_operand")))]
a617e5d5 3195 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
f15c7bd1
UB		 3196 && ((unsigned) exact_log2 (INTVAL (operands[3]))
3197 < GET_MODE_NUNITS (V2SImode))"
3198{
3199 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3200 switch (which_alternative)
3201 {
3202 case 1:
3203 return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3204 case 0:
3205 return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
3206 default:
3207 gcc_unreachable ();
3208 }
3209}
3210 [(set_attr "isa" "noavx,avx")
3211 (set_attr "prefix_data16" "1")
3212 (set_attr "prefix_extra" "1")
3213 (set_attr "type" "sselog")
3214 (set_attr "length_immediate" "1")
3215 (set_attr "prefix" "orig,vex")
3216 (set_attr "mode" "TI")])
3217
80e8bb90 3218(define_expand "mmx_pinsrw"
82e86dc6 3219 [(set (match_operand:V4HI 0 "register_operand")
80e8bb90 3220 (vec_merge:V4HI
80e8bb90 3221 (vec_duplicate:V4HI
82e86dc6
UB		 3222 (match_operand:SI 2 "nonimmediate_operand"))
3223 (match_operand:V4HI 1 "register_operand")
3224 (match_operand:SI 3 "const_0_to_3_operand")))]
42500d83
L		 3225 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3226 && (TARGET_SSE || TARGET_3DNOW_A)"
80e8bb90
RH		 3227{
3228 operands[2] = gen_lowpart (HImode, operands[2]);
3229 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
3230})
3231
3232(define_insn "*mmx_pinsrw"
3bb345c9 3233 [(set (match_operand:V4HI 0 "register_operand" "=y,x,YW")
80e8bb90 3234 (vec_merge:V4HI
80e8bb90 3235 (vec_duplicate:V4HI
42500d83 3236 (match_operand:HI 2 "nonimmediate_operand" "rm,rm,rm"))
3bb345c9 3237 (match_operand:V4HI 1 "register_operand" "0,0,YW")
82e86dc6 3238 (match_operand:SI 3 "const_int_operand")))]
42500d83
L		 3239 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3240 && (TARGET_SSE || TARGET_3DNOW_A)
51e7f377
UB		 3241 && ((unsigned) exact_log2 (INTVAL (operands[3]))
3242 < GET_MODE_NUNITS (V4HImode))"
80e8bb90
RH		 3243{
3244 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
b49ae8a5 3245 switch (which_alternative)
42500d83 3246 {
b49ae8a5 3247 case 2:
42500d83
L		 3248 if (MEM_P (operands[2]))
3249 return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3250 else
3251 return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
b49ae8a5
UB		 3252 case 1:
3253 case 0:
42500d83
L		 3254 if (MEM_P (operands[2]))
3255 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
3256 else
3257 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
b49ae8a5
UB		 3258 default:
3259 gcc_unreachable ();
42500d83 3260 }
80e8bb90 3261}
b49ae8a5
UB		 3262 [(set_attr "isa" "*,sse2_noavx,avx")
3263 (set_attr "mmx_isa" "native,*,*")
42500d83 3264 (set_attr "type" "mmxcvt,sselog,sselog")
725fd454 3265 (set_attr "length_immediate" "1")
42500d83 3266 (set_attr "mode" "DI,TI,TI")])
80e8bb90 3267
f15c7bd1 3268(define_insn "*mmx_pinsrb"
3bb345c9 3269 [(set (match_operand:V8QI 0 "register_operand" "=x,YW")
f15c7bd1
UB		 3270 (vec_merge:V8QI
3271 (vec_duplicate:V8QI
3272 (match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
3bb345c9 3273 (match_operand:V8QI 1 "register_operand" "0,YW")
f15c7bd1 3274 (match_operand:SI 3 "const_int_operand")))]
a617e5d5 3275 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
f15c7bd1
UB		 3276 && ((unsigned) exact_log2 (INTVAL (operands[3]))
3277 < GET_MODE_NUNITS (V8QImode))"
3278{
3279 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3280 switch (which_alternative)
3281 {
3282 case 1:
3283 if (MEM_P (operands[2]))
3284 return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3285 else
3286 return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
3287 case 0:
3288 if (MEM_P (operands[2]))
3289 return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
3290 else
3291 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
3292 default:
3293 gcc_unreachable ();
3294 }
3295}
3296 [(set_attr "isa" "noavx,avx")
3297 (set_attr "type" "sselog")
3298 (set_attr "prefix_data16" "1")
3299 (set_attr "prefix_extra" "1")
3300 (set_attr "length_immediate" "1")
3301 (set_attr "prefix" "orig,vex")
3302 (set_attr "mode" "TI")])
3303
5fbc8ab4
UB		 3304(define_insn "*mmx_pextrw"
3305 [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m")
3306 (vec_select:HI
3bb345c9 3307 (match_operand:V4HI 1 "register_operand" "y,YW,YW")
5fbc8ab4
UB		 3308 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))]
3309 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3310 && (TARGET_SSE || TARGET_3DNOW_A)"
3311 "@
3312 pextrw\t{%2, %1, %k0|%k0, %1, %2}
3313 %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
3314 %vpextrw\t{%2, %1, %0|%0, %1, %2}"
3315 [(set_attr "isa" "*,sse2,sse4")
3316 (set_attr "mmx_isa" "native,*,*")
3317 (set_attr "type" "mmxcvt,sselog1,sselog1")
3318 (set_attr "length_immediate" "1")
3319 (set_attr "prefix" "orig,maybe_vex,maybe_vex")
3320 (set_attr "mode" "DI,TI,TI")])
3321
3322(define_insn "*mmx_pextrw_zext"
3323 [(set (match_operand:SWI48 0 "register_operand" "=r,r")
3324 (zero_extend:SWI48
80e8bb90 3325 (vec_select:HI
3bb345c9 3326 (match_operand:V4HI 1 "register_operand" "y,YW")
f2c2a6fb
L		 3327 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
3328 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3329 && (TARGET_SSE || TARGET_3DNOW_A)"
3330 "@
5fbc8ab4
UB		 3331 pextrw\t{%2, %1, %k0|%k0, %1, %2}
3332 %vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
b49ae8a5
UB		 3333 [(set_attr "isa" "*,sse2")
3334 (set_attr "mmx_isa" "native,*")
f2c2a6fb 3335 (set_attr "type" "mmxcvt,sselog1")
725fd454 3336 (set_attr "length_immediate" "1")
5fbc8ab4 3337 (set_attr "prefix" "orig,maybe_vex")
f2c2a6fb 3338 (set_attr "mode" "DI,TI")])
80e8bb90 3339
5fbc8ab4
UB		 3340(define_insn "*mmx_pextrb"
3341 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
3342 (vec_select:QI
3bb345c9 3343 (match_operand:V8QI 1 "register_operand" "YW,YW")
5fbc8ab4 3344 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))]
a617e5d5 3345 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5fbc8ab4
UB		 3346 "@
3347 %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
3348 %vpextrb\t{%2, %1, %0|%0, %1, %2}"
3349 [(set_attr "type" "sselog1")
3350 (set_attr "prefix_data16" "1")
3351 (set_attr "prefix_extra" "1")
3352 (set_attr "length_immediate" "1")
3353 (set_attr "prefix" "maybe_vex")
3354 (set_attr "mode" "TI")])
3355
3356(define_insn "*mmx_pextrb_zext"
3357 [(set (match_operand:SWI248 0 "register_operand" "=r")
3358 (zero_extend:SWI248
3359 (vec_select:QI
3bb345c9 3360 (match_operand:V8QI 1 "register_operand" "YW")
5fbc8ab4 3361 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
a617e5d5 3362 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5fbc8ab4
UB		 3363 "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
3364 [(set_attr "type" "sselog1")
3365 (set_attr "prefix_data16" "1")
3366 (set_attr "prefix_extra" "1")
3367 (set_attr "length_immediate" "1")
3368 (set_attr "prefix" "maybe_vex")
3369 (set_attr "mode" "TI")])
3370
a325bdd1
PB		 3371(define_insn "mmx_pshufbv8qi3"
3372 [(set (match_operand:V8QI 0 "register_operand" "=x,Yw")
3373 (unspec:V8QI
3374 [(match_operand:V8QI 1 "register_operand" "0,Yw")
3375 (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")]
3376 UNSPEC_PSHUFB))]
3377 "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
3378 "@
3379 pshufb\t{%2, %0|%0, %2}
3380 vpshufb\t{%2, %1, %0|%0, %1, %2}"
3381 [(set_attr "isa" "noavx,avx")
3382 (set_attr "type" "sselog1")
3383 (set_attr "prefix_data16" "1,*")
3384 (set_attr "prefix_extra" "1")
3385 (set_attr "prefix" "orig,maybe_evex")
3386 (set_attr "btver2_decode" "vector")
3387 (set_attr "mode" "TI")])
3388
be8749f9
UB		 3389(define_insn "mmx_pshufbv4qi3"
3390 [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
3391 (unspec:V4QI
3392 [(match_operand:V4QI 1 "register_operand" "0,Yw")
3393 (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")]
3394 UNSPEC_PSHUFB))]
3395 "TARGET_SSSE3"
3396 "@
3397 pshufb\t{%2, %0|%0, %2}
3398 vpshufb\t{%2, %1, %0|%0, %1, %2}"
3399 [(set_attr "isa" "noavx,avx")
3400 (set_attr "type" "sselog1")
3401 (set_attr "prefix_data16" "1,*")
3402 (set_attr "prefix_extra" "1")
3403 (set_attr "prefix" "orig,maybe_evex")
3404 (set_attr "btver2_decode" "vector")
3405 (set_attr "mode" "TI")])
3406
80e8bb90 3407(define_expand "mmx_pshufw"
82e86dc6 3408 [(match_operand:V4HI 0 "register_operand")
3d34e8b0 3409 (match_operand:V4HI 1 "register_mmxmem_operand")
82e86dc6 3410 (match_operand:SI 2 "const_int_operand")]
3d34e8b0
L		 3411 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3412 && (TARGET_SSE || TARGET_3DNOW_A)"
80e8bb90
RH		 3413{
3414 int mask = INTVAL (operands[2]);
3415 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
3416 GEN_INT ((mask >> 0) & 3),
3417 GEN_INT ((mask >> 2) & 3),
3418 GEN_INT ((mask >> 4) & 3),
3419 GEN_INT ((mask >> 6) & 3)));
3420 DONE;
3421})
3422
3423(define_insn "mmx_pshufw_1"
a18ebd6c 3424 [(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
80e8bb90 3425 (vec_select:V4HI
a18ebd6c 3426 (match_operand:V4HI 1 "register_mmxmem_operand" "ym,Yw")
82e86dc6
UB		 3427 (parallel [(match_operand 2 "const_0_to_3_operand")
3428 (match_operand 3 "const_0_to_3_operand")
3429 (match_operand 4 "const_0_to_3_operand")
3430 (match_operand 5 "const_0_to_3_operand")])))]
3d34e8b0
L		 3431 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3432 && (TARGET_SSE || TARGET_3DNOW_A)"
80e8bb90
RH		 3433{
3434 int mask = 0;
3435 mask |= INTVAL (operands[2]) << 0;
3436 mask |= INTVAL (operands[3]) << 2;
3437 mask |= INTVAL (operands[4]) << 4;
3438 mask |= INTVAL (operands[5]) << 6;
3439 operands[2] = GEN_INT (mask);
3440
3d34e8b0
L		 3441 switch (which_alternative)
3442 {
3443 case 0:
3444 return "pshufw\t{%2, %1, %0|%0, %1, %2}";
3445 case 1:
3446 return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
3447 default:
3448 gcc_unreachable ();
3449 }
80e8bb90 3450}
b49ae8a5
UB		 3451 [(set_attr "isa" "*,sse2")
3452 (set_attr "mmx_isa" "native,*")
14cd049a 3453 (set_attr "type" "mmxcvt,sselog1")
725fd454 3454 (set_attr "length_immediate" "1")
3d34e8b0 3455 (set_attr "mode" "DI,TI")])
80e8bb90 3456
9b8579a6
UB		 3457(define_insn "*mmx_pshufd_1"
3458 [(set (match_operand:V2SI 0 "register_operand" "=Yv")
3459 (vec_select:V2SI
3460 (match_operand:V2SI 1 "register_operand" "Yv")
3461 (parallel [(match_operand 2 "const_0_to_1_operand")
3462 (match_operand 3 "const_0_to_1_operand")])))]
3463 "TARGET_MMX_WITH_SSE"
3464{
3465 int mask = 0;
3466 mask |= INTVAL (operands[2]) << 0;
3467 mask |= INTVAL (operands[3]) << 2;
3468 mask |= 2 << 4;
3469 mask |= 3 << 6;
3470 operands[2] = GEN_INT (mask);
3471
3472 return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
3473}
3474 [(set_attr "type" "sselog1")
3475 (set_attr "prefix_data16" "1")
3476 (set_attr "length_immediate" "1")
3477 (set_attr "mode" "TI")])
3478
be8749f9 3479(define_insn "*mmx_pblendw64"
a325bdd1
PB		 3480 [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,x")
3481 (vec_merge:V4HI
3482 (match_operand:V4HI 2 "register_operand" "Yr,*x,x")
3483 (match_operand:V4HI 1 "register_operand" "0,0,x")
be8749f9 3484 (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")))]
a325bdd1
PB		 3485 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3486 "@
3487 pblendw\t{%3, %2, %0|%0, %2, %3}
3488 pblendw\t{%3, %2, %0|%0, %2, %3}
3489 vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
3490 [(set_attr "isa" "noavx,noavx,avx")
3491 (set_attr "type" "ssemov")
3492 (set_attr "prefix_extra" "1")
3493 (set_attr "length_immediate" "1")
3494 (set_attr "prefix" "orig,orig,vex")
3495 (set_attr "mode" "TI")])
3496
be8749f9
UB		 3497(define_insn "*mmx_pblendw32"
3498 [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,x")
3499 (vec_merge:V2HI
3500 (match_operand:V2HI 2 "register_operand" "Yr,*x,x")
3501 (match_operand:V2HI 1 "register_operand" "0,0,x")
3502 (match_operand:SI 3 "const_0_to_7_operand" "n,n,n")))]
3503 "TARGET_SSE4_1"
3504 "@
3505 pblendw\t{%3, %2, %0|%0, %2, %3}
3506 pblendw\t{%3, %2, %0|%0, %2, %3}
3507 vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
3508 [(set_attr "isa" "noavx,noavx,avx")
3509 (set_attr "type" "ssemov")
3510 (set_attr "prefix_extra" "1")
3511 (set_attr "length_immediate" "1")
3512 (set_attr "prefix" "orig,orig,vex")
3513 (set_attr "mode" "TI")])
3514
0f3a743b
JJ		 3515;; Optimize V2SImode load from memory, swapping the elements and
3516;; storing back into the memory into DImode rotate of the memory by 32.
3517(define_split
3518 [(set (match_operand:V2SI 0 "memory_operand")
3519 (vec_select:V2SI (match_dup 0)
3520 (parallel [(const_int 1) (const_int 0)])))]
3521 "TARGET_64BIT && (TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())"
3522 [(set (match_dup 0)
3523 (rotate:DI (match_dup 0) (const_int 32)))]
3524 "operands[0] = adjust_address (operands[0], DImode, 0);")
3525
80e8bb90 3526(define_insn "mmx_pswapdv2si2"
9f0cb44e 3527 [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
80e8bb90 3528 (vec_select:V2SI
9f0cb44e 3529 (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")
80e8bb90 3530 (parallel [(const_int 1) (const_int 0)])))]
240198fe 3531 "TARGET_3DNOW_A"
9f0cb44e
UB		 3532 "@
3533 pswapd\t{%1, %0|%0, %1}
3534 %vpshufd\t{$0xe1, %1, %0|%0, %1, 0xe1}";
3535 [(set_attr "isa" "*,sse2")
3536 (set_attr "mmx_isa" "native,*")
3537 (set_attr "type" "mmxcvt,sselog1")
3538 (set_attr "prefix_extra" "1,*")
3539 (set_attr "prefix_data16" "*,1")
3540 (set_attr "length_immediate" "*,1")
3541 (set_attr "mode" "DI,TI")])
80e8bb90 3542
14cd049a 3543(define_insn "*vec_dupv4hi"
a18ebd6c 3544 [(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
eb701deb
RH		 3545 (vec_duplicate:V4HI
3546 (truncate:HI
a18ebd6c 3547 (match_operand:SI 1 "register_operand" "0,Yw"))))]
3d34e8b0
L		 3548 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3549 && (TARGET_SSE || TARGET_3DNOW_A)"
3550 "@
3551 pshufw\t{$0, %0, %0|%0, %0, 0}
14cd049a
UB		 3552 %vpshuflw\t{$0, %1, %0|%0, %1, 0}"
3553 [(set_attr "isa" "*,sse2")
3554 (set_attr "mmx_isa" "native,*")
3555 (set_attr "type" "mmxcvt,sselog1")
3556 (set_attr "length_immediate" "1")
3557 (set_attr "mode" "DI,TI")])
3558
eb701deb 3559
14cd049a
UB		 3560(define_insn "*vec_dupv2si"
3561 [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
eb701deb 3562 (vec_duplicate:V2SI
14cd049a 3563 (match_operand:SI 1 "register_operand" "0,Yv")))]
74e299b9
L		 3564 "TARGET_MMX || TARGET_MMX_WITH_SSE"
3565 "@
3566 punpckldq\t%0, %0
14cd049a
UB		 3567 %vpshufd\t{$0xe0, %1, %0|%0, %1, 0xe0}"
3568 [(set_attr "isa" "*,sse2")
3569 (set_attr "mmx_isa" "native,*")
3570 (set_attr "type" "mmxcvt,sselog1")
3571 (set_attr "prefix_data16" "*,1")
3572 (set_attr "length_immediate" "*,1")
3573 (set_attr "mode" "DI,TI")])
eb701deb
RH		 3574
3575(define_insn "*mmx_concatv2si"
3576 [(set (match_operand:V2SI 0 "register_operand" "=y,y")
3577 (vec_concat:V2SI
3578 (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
808d8de5 3579 (match_operand:SI 2 "nonimm_or_0_operand" "ym,C")))]
eb701deb
RH		 3580 "TARGET_MMX && !TARGET_SSE"
3581 "@
3582 punpckldq\t{%2, %0|%0, %2}
3583 movd\t{%1, %0|%0, %1}"
3584 [(set_attr "type" "mmxcvt,mmxmov")
3585 (set_attr "mode" "DI")])
3586
3587(define_expand "vec_setv2si"
82e86dc6
UB		 3588 [(match_operand:V2SI 0 "register_operand")
3589 (match_operand:SI 1 "register_operand")
20a2c8ac 3590 (match_operand 2 "vec_setm_mmx_operand")]
d4410ec0 3591 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 3592{
20a2c8ac
UB		 3593 if (CONST_INT_P (operands[2]))
3594 ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
3595 INTVAL (operands[2]));
3596 else
3597 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
eb701deb
RH		 3598 DONE;
3599})
3600
a3d4a22b
UB		 3601;; Avoid combining registers from different units in a single alternative,
3602;; see comment above inline_secondary_memory_needed function in i386.c
0f2698d0 3603(define_insn_and_split "*vec_extractv2si_0"
2c726f94 3604 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r,r")
0f2698d0 3605 (vec_select:SI
2c726f94 3606 (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m,x")
0f2698d0 3607 (parallel [(const_int 0)])))]
d4410ec0
L		 3608 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3609 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
0f2698d0
RH		 3610 "#"
3611 "&& reload_completed"
0b013847 3612 [(set (match_dup 0) (match_dup 1))]
d4410ec0 3613 "operands[1] = gen_lowpart (SImode, operands[1]);"
2c726f94
UB		 3614 [(set_attr "isa" "*,*,*,*,*,sse2")
3615 (set_attr "mmx_isa" "*,*,native,native,*,*")
3616 (set (attr "preferred_for_speed")
3617 (cond [(eq_attr "alternative" "5")
3618 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
3619 ]
3620 (symbol_ref "true")))])
3621
3622(define_insn "*vec_extractv2si_0_zext_sse4"
3623 [(set (match_operand:DI 0 "register_operand" "=r,x")
3624 (zero_extend:DI
3625 (vec_select:SI
3626 (match_operand:V2SI 1 "register_operand" "x,x")
3627 (parallel [(const_int 0)]))))]
3628 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE4_1"
3629 "#"
3630 [(set_attr "isa" "x64,*")
3631 (set (attr "preferred_for_speed")
3632 (cond [(eq_attr "alternative" "0")
3633 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
3634 ]
3635 (symbol_ref "true")))])
3636
3637(define_insn "*vec_extractv2si_0_zext"
3638 [(set (match_operand:DI 0 "register_operand" "=r")
3639 (zero_extend:DI
3640 (vec_select:SI
3641 (match_operand:V2SI 1 "register_operand" "x")
3642 (parallel [(const_int 0)]))))]
3643 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3644 && TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC"
3645 "#")
3646
3647(define_split
3648 [(set (match_operand:DI 0 "register_operand")
3649 (zero_extend:DI
3650 (vec_select:SI
3651 (match_operand:V2SI 1 "register_operand")
3652 (parallel [(const_int 0)]))))]
3653 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3654 && TARGET_SSE2 && reload_completed"
3655 [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
3656 "operands[1] = gen_lowpart (SImode, operands[1]);")
0f2698d0 3657
a3d4a22b
UB		 3658;; Avoid combining registers from different units in a single alternative,
3659;; see comment above inline_secondary_memory_needed function in i386.c
0f2698d0 3660(define_insn "*vec_extractv2si_1"
2c726f94 3661 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,rm,x,x,y,x,r")
0f2698d0 3662 (vec_select:SI
d56779b8 3663 (match_operand:V2SI 1 "nonimmediate_operand" " 0,x ,x,0,o,o,o")
0f2698d0 3664 (parallel [(const_int 1)])))]
d4410ec0
L		 3665 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3666 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
0f2698d0
RH		 3667 "@
3668 punpckhdq\t%0, %0
2c726f94 3669 %vpextrd\t{$1, %1, %0|%0, %1, 1}
db67dfda 3670 %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
d56779b8 3671 shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
a3d4a22b
UB		 3672 #
3673 #
0f2698d0 3674 #"
2c726f94
UB		 3675 [(set_attr "isa" "*,sse4,sse2,noavx,*,*,*")
3676 (set_attr "mmx_isa" "native,*,*,*,native,*,*")
3677 (set_attr "type" "mmxcvt,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
e070095c 3678 (set (attr "length_immediate")
2c726f94 3679 (if_then_else (eq_attr "alternative" "1,2,3")
e070095c
UB		 3680 (const_string "1")
3681 (const_string "*")))
2c726f94
UB		 3682 (set_attr "prefix" "orig,maybe_vex,maybe_vex,orig,orig,orig,orig")
3683 (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
0f2698d0
RH		 3684
3685(define_split
82e86dc6 3686 [(set (match_operand:SI 0 "register_operand")
0f2698d0 3687 (vec_select:SI
82e86dc6 3688 (match_operand:V2SI 1 "memory_operand")
0f2698d0 3689 (parallel [(const_int 1)])))]
d4410ec0 3690 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
0b013847
UB		 3691 [(set (match_dup 0) (match_dup 1))]
3692 "operands[1] = adjust_address (operands[1], SImode, 4);")
0f2698d0 3693
2c726f94
UB		 3694(define_insn "*vec_extractv2si_1_zext"
3695 [(set (match_operand:DI 0 "register_operand" "=r")
3696 (zero_extend:DI
3697 (vec_select:SI
3698 (match_operand:V2SI 1 "register_operand" "x")
3699 (parallel [(const_int 1)]))))]
3700 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3701 && TARGET_64BIT && TARGET_SSE4_1"
3702 "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
3703 [(set_attr "type" "sselog1")
3704 (set_attr "prefix_extra" "1")
3705 (set_attr "length_immediate" "1")
3706 (set_attr "prefix" "maybe_vex")
3707 (set_attr "mode" "TI")])
3708
60ca9a65
UB		 3709(define_insn_and_split "*vec_extractv2si_zext_mem"
3710 [(set (match_operand:DI 0 "register_operand" "=y,x,r")
3711 (zero_extend:DI
3712 (vec_select:SI
3713 (match_operand:V2SI 1 "memory_operand" "o,o,o")
3714 (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
2c726f94 3715 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_64BIT"
60ca9a65
UB		 3716 "#"
3717 "&& reload_completed"
3718 [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
3719{
3720 operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
49be11f5 3721}
d4410ec0
L		 3722 [(set_attr "isa" "*,sse2,*")
3723 (set_attr "mmx_isa" "native,*,*")])
60ca9a65 3724
ff03930a 3725(define_expand "vec_extractv2sisi"
82e86dc6
UB		 3726 [(match_operand:SI 0 "register_operand")
3727 (match_operand:V2SI 1 "register_operand")
3728 (match_operand 2 "const_int_operand")]
d4410ec0 3729 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 3730{
d4410ec0
L		 3731 ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
3732 operands[1], INTVAL (operands[2]));
eb701deb
RH		 3733 DONE;
3734})
3735
ff03930a 3736(define_expand "vec_initv2sisi"
82e86dc6
UB		 3737 [(match_operand:V2SI 0 "register_operand")
3738 (match_operand 1)]
d4410ec0 3739 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
eb701deb 3740{
d4410ec0
L		 3741 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
3742 operands[1]);
eb701deb
RH		 3743 DONE;
3744})
3745
3746(define_expand "vec_setv4hi"
82e86dc6
UB		 3747 [(match_operand:V4HI 0 "register_operand")
3748 (match_operand:HI 1 "register_operand")
20a2c8ac 3749 (match_operand 2 "vec_setm_mmx_operand")]
d4410ec0 3750 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 3751{
20a2c8ac
UB		 3752 if (CONST_INT_P (operands[2]))
3753 ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
3754 INTVAL (operands[2]));
3755 else
3756 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
eb701deb
RH		 3757 DONE;
3758})
3759
ff03930a 3760(define_expand "vec_extractv4hihi"
82e86dc6
UB		 3761 [(match_operand:HI 0 "register_operand")
3762 (match_operand:V4HI 1 "register_operand")
3763 (match_operand 2 "const_int_operand")]
d4410ec0 3764 "TARGET_MMX || TARGET_MMX_WITH_SSE"
eb701deb 3765{
d4410ec0
L		 3766 ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
3767 operands[1], INTVAL (operands[2]));
eb701deb
RH		 3768 DONE;
3769})
3770
ff03930a 3771(define_expand "vec_initv4hihi"
82e86dc6
UB		 3772 [(match_operand:V4HI 0 "register_operand")
3773 (match_operand 1)]
d4410ec0 3774 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
eb701deb 3775{
d4410ec0
L		 3776 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
3777 operands[1]);
eb701deb
RH		 3778 DONE;
3779})
3780
3781(define_expand "vec_setv8qi"
82e86dc6
UB		 3782 [(match_operand:V8QI 0 "register_operand")
3783 (match_operand:QI 1 "register_operand")
20a2c8ac 3784 (match_operand 2 "vec_setm_mmx_operand")]
5883e567 3785 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
eb701deb 3786{
20a2c8ac
UB		 3787 if (CONST_INT_P (operands[2]))
3788 ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
3789 INTVAL (operands[2]));
3790 else
3791 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
eb701deb
RH		 3792 DONE;
3793})
3794
ff03930a 3795(define_expand "vec_extractv8qiqi"
82e86dc6
UB		 3796 [(match_operand:QI 0 "register_operand")
3797 (match_operand:V8QI 1 "register_operand")
3798 (match_operand 2 "const_int_operand")]
5883e567 3799 "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
eb701deb 3800{
d4410ec0
L		 3801 ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
3802 operands[1], INTVAL (operands[2]));
eb701deb
RH		 3803 DONE;
3804})
3805
ff03930a 3806(define_expand "vec_initv8qiqi"
82e86dc6
UB		 3807 [(match_operand:V8QI 0 "register_operand")
3808 (match_operand 1)]
d4410ec0 3809 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
eb701deb 3810{
d4410ec0
L		 3811 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
3812 operands[1]);
eb701deb
RH		 3813 DONE;
3814})
3815
5883e567
UB		 3816(define_insn "*pinsrw"
3817 [(set (match_operand:V2HI 0 "register_operand" "=x,YW")
3818 (vec_merge:V2HI
3819 (vec_duplicate:V2HI
3820 (match_operand:HI 2 "nonimmediate_operand" "rm,rm"))
3821 (match_operand:V2HI 1 "register_operand" "0,YW")
3822 (match_operand:SI 3 "const_int_operand")))]
3823 "TARGET_SSE2
3824 && ((unsigned) exact_log2 (INTVAL (operands[3]))
3825 < GET_MODE_NUNITS (V2HImode))"
3826{
3827 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3828 switch (which_alternative)
3829 {
3830 case 1:
3831 if (MEM_P (operands[2]))
3832 return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3833 else
3834 return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
3835 case 0:
3836 if (MEM_P (operands[2]))
3837 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
3838 else
3839 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
3840 default:
3841 gcc_unreachable ();
3842 }
3843}
3844 [(set_attr "isa" "noavx,avx")
3845 (set_attr "type" "sselog")
3846 (set_attr "length_immediate" "1")
3847 (set_attr "mode" "TI")])
3848
3849(define_insn "*pinsrb"
3850 [(set (match_operand:V4QI 0 "register_operand" "=x,YW")
3851 (vec_merge:V4QI
3852 (vec_duplicate:V4QI
3853 (match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
3854 (match_operand:V4QI 1 "register_operand" "0,YW")
3855 (match_operand:SI 3 "const_int_operand")))]
3856 "TARGET_SSE4_1
3857 && ((unsigned) exact_log2 (INTVAL (operands[3]))
3858 < GET_MODE_NUNITS (V4QImode))"
3859{
3860 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3861 switch (which_alternative)
3862 {
3863 case 1:
3864 if (MEM_P (operands[2]))
3865 return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3866 else
3867 return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
3868 case 0:
3869 if (MEM_P (operands[2]))
3870 return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
3871 else
3872 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
3873 default:
3874 gcc_unreachable ();
3875 }
3876}
3877 [(set_attr "isa" "noavx,avx")
3878 (set_attr "type" "sselog")
3879 (set_attr "prefix_data16" "1")
3880 (set_attr "prefix_extra" "1")
3881 (set_attr "length_immediate" "1")
3882 (set_attr "prefix" "orig,vex")
3883 (set_attr "mode" "TI")])
3884
3885(define_insn "*pextrw"
3886 [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m")
3887 (vec_select:HI
3888 (match_operand:V2HI 1 "register_operand" "YW,YW")
3889 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n,n")])))]
3890 "TARGET_SSE2"
3891 "@
3892 %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
3893 %vpextrw\t{%2, %1, %0|%0, %1, %2}"
3894 [(set_attr "isa" "*,sse4")
3895 (set_attr "type" "sselog1")
3896 (set_attr "length_immediate" "1")
3897 (set_attr "prefix" "maybe_vex")
3898 (set_attr "mode" "TI")])
3899
3900(define_insn "*pextrw_zext"
3901 [(set (match_operand:SWI48 0 "register_operand" "=r")
3902 (zero_extend:SWI48
3903 (vec_select:HI
3904 (match_operand:V2HI 1 "register_operand" "YW")
3905 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")]))))]
3906 "TARGET_SSE2"
3907 "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
3908 [(set_attr "type" "sselog1")
3909 (set_attr "length_immediate" "1")
3910 (set_attr "prefix" "maybe_vex")
3911 (set_attr "mode" "TI")])
3912
3913(define_insn "*pextrb"
3914 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
3915 (vec_select:QI
3916 (match_operand:V4QI 1 "register_operand" "YW,YW")
3917 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")])))]
3918 "TARGET_SSE4_1"
3919 "@
3920 %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
3921 %vpextrb\t{%2, %1, %0|%0, %1, %2}"
3922 [(set_attr "type" "sselog1")
3923 (set_attr "prefix_data16" "1")
3924 (set_attr "prefix_extra" "1")
3925 (set_attr "length_immediate" "1")
3926 (set_attr "prefix" "maybe_vex")
3927 (set_attr "mode" "TI")])
3928
3929(define_insn "*pextrb_zext"
3930 [(set (match_operand:SWI248 0 "register_operand" "=r")
3931 (zero_extend:SWI248
3932 (vec_select:QI
3933 (match_operand:V4QI 1 "register_operand" "YW")
3934 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
3935 "TARGET_SSE4_1"
3936 "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
3937 [(set_attr "type" "sselog1")
3938 (set_attr "prefix_data16" "1")
3939 (set_attr "prefix_extra" "1")
3940 (set_attr "length_immediate" "1")
3941 (set_attr "prefix" "maybe_vex")
3942 (set_attr "mode" "TI")])
3943
3944(define_expand "vec_setv2hi"
3945 [(match_operand:V2HI 0 "register_operand")
3946 (match_operand:HI 1 "register_operand")
8d980e84 3947 (match_operand 2 "vec_setm_sse41_operand")]
5883e567
UB		 3948 "TARGET_SSE2"
3949{
f6587817
UB		 3950 if (CONST_INT_P (operands[2]))
3951 ix86_expand_vector_set (false, operands[0], operands[1],
3952 INTVAL (operands[2]));
3953 else
3954 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5883e567
UB		 3955 DONE;
3956})
3957
3958(define_expand "vec_extractv2hihi"
3959 [(match_operand:HI 0 "register_operand")
3960 (match_operand:V2HI 1 "register_operand")
3961 (match_operand 2 "const_int_operand")]
3962 "TARGET_SSE2"
3963{
3964 ix86_expand_vector_extract (false, operands[0],
3965 operands[1], INTVAL (operands[2]));
3966 DONE;
3967})
3968
3969(define_expand "vec_setv4qi"
3970 [(match_operand:V4QI 0 "register_operand")
3971 (match_operand:QI 1 "register_operand")
f6587817 3972 (match_operand 2 "vec_setm_mmx_operand")]
5883e567
UB		 3973 "TARGET_SSE4_1"
3974{
f6587817
UB		 3975 if (CONST_INT_P (operands[2]))
3976 ix86_expand_vector_set (false, operands[0], operands[1],
3977 INTVAL (operands[2]));
3978 else
3979 ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5883e567
UB		 3980 DONE;
3981})
3982
3983(define_expand "vec_extractv4qiqi"
3984 [(match_operand:QI 0 "register_operand")
3985 (match_operand:V4QI 1 "register_operand")
3986 (match_operand 2 "const_int_operand")]
3987 "TARGET_SSE4_1"
3988{
3989 ix86_expand_vector_extract (false, operands[0],
3990 operands[1], INTVAL (operands[2]));
3991 DONE;
3992})
3993
8d7dae0e
UB		 3994(define_insn_and_split "*punpckwd"
3995 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3996 (vec_select:V2HI
3997 (vec_concat:V4HI
3998 (match_operand:V2HI 1 "register_operand" "0,Yw")
3999 (match_operand:V2HI 2 "register_operand" "x,Yw"))
4986946f
UB		 4000 (parallel [(match_operand 3 "const_0_to_3_operand")
4001 (match_operand 4 "const_0_to_3_operand")])))]
8d7dae0e
UB		 4002 "TARGET_SSE2"
4003 "#"
4004 "&& reload_completed"
4005 [(set (match_dup 5)
4986946f 4006 (vec_select:V8HI
8d7dae0e
UB		 4007 (match_dup 5)
4008 (parallel [(match_dup 3) (match_dup 4)
4986946f
UB		 4009 (const_int 2) (const_int 3)
4010 (const_int 4) (const_int 5)
4011 (const_int 6) (const_int 7)])))]
8d7dae0e
UB		 4012{
4013 rtx dest = lowpart_subreg (V8HImode, operands[0], V2HImode);
4014 rtx op1 = lowpart_subreg (V8HImode, operands[1], V2HImode);
4015 rtx op2 = lowpart_subreg (V8HImode, operands[2], V2HImode);
4016
4017 emit_insn (gen_vec_interleave_lowv8hi (dest, op1, op2));
4018
4019 static const int map[4] = { 0, 2, 1, 3 };
4020
4021 int sel0 = map[INTVAL (operands[3])];
4022 int sel1 = map[INTVAL (operands[4])];
4023
4024 if (sel0 == 0 && sel1 == 1)
4025 DONE;
4026
4027 operands[3] = GEN_INT (sel0);
4028 operands[4] = GEN_INT (sel1);
4986946f 4029 operands[5] = dest;
8d7dae0e
UB		 4030}
4031 [(set_attr "isa" "noavx,avx")
4032 (set_attr "type" "sselog")
4033 (set_attr "mode" "TI")])
4034
4035(define_insn "*pshufw_1"
4036 [(set (match_operand:V2HI 0 "register_operand" "=Yw")
4037 (vec_select:V2HI
4038 (match_operand:V2HI 1 "register_operand" "Yw")
4039 (parallel [(match_operand 2 "const_0_to_1_operand")
4040 (match_operand 3 "const_0_to_1_operand")])))]
4041 "TARGET_SSE2"
4042{
4043 int mask = 0;
4044 mask |= INTVAL (operands[2]) << 0;
4045 mask |= INTVAL (operands[3]) << 2;
4046 mask |= 2 << 4;
4047 mask |= 3 << 6;
4048 operands[2] = GEN_INT (mask);
4049
4050 return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
4051}
4052 [(set_attr "type" "sselog1")
4053 (set_attr "length_immediate" "1")
4054 (set_attr "mode" "TI")])
4055
4056(define_insn "*vec_dupv2hi"
4057 [(set (match_operand:V2HI 0 "register_operand" "=Yw")
4058 (vec_duplicate:V2HI
4059 (truncate:HI
4060 (match_operand:SI 1 "register_operand" "Yw"))))]
4061 "TARGET_SSE2"
4062 "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
4063 [(set_attr "type" "sselog1")
4064 (set_attr "length_immediate" "1")
4065 (set_attr "mode" "TI")])
4066
4067(define_expand "vec_initv2hihi"
4068 [(match_operand:V2HI 0 "register_operand")
4069 (match_operand 1)]
4070 "TARGET_SSE2"
4071{
64735dc9
UB		 4072 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
4073 operands[1]);
4074 DONE;
4075})
4076
4077(define_expand "vec_initv4qiqi"
4078 [(match_operand:V2HI 0 "register_operand")
4079 (match_operand 1)]
4080 "TARGET_SSE2"
4081{
4082 ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
8d7dae0e
UB		 4083 operands[1]);
4084 DONE;
4085})
4086
80e8bb90
RH		 4087;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4088;;
35c0104b 4089;; Miscellaneous
80e8bb90
RH		 4090;;
4091;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4092
94538b65
UB		 4093(define_expand "mmx_uavg<mode>3"
4094 [(set (match_operand:MMXMODE12 0 "register_operand")
4095 (truncate:MMXMODE12
4096 (lshiftrt:<mmxdoublemode>
4097 (plus:<mmxdoublemode>
4098 (plus:<mmxdoublemode>
4099 (zero_extend:<mmxdoublemode>
4100 (match_operand:MMXMODE12 1 "register_mmxmem_operand"))
4101 (zero_extend:<mmxdoublemode>
4102 (match_operand:MMXMODE12 2 "register_mmxmem_operand")))
4103 (match_dup 3))
ffbaf337 4104 (const_int 1))))]
a899fa35 4105 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
45641b31 4106 && (TARGET_SSE || TARGET_3DNOW)"
94538b65
UB		 4107{
4108 operands[3] = CONST1_RTX(<mmxdoublemode>mode);
4109 ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
4110})
ffbaf337
UB		 4111
4112(define_insn "*mmx_uavgv8qi3"
3bb345c9 4113 [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 4114 (truncate:V8QI
4115 (lshiftrt:V8HI
4116 (plus:V8HI
4117 (plus:V8HI
4118 (zero_extend:V8HI
3bb345c9 4119 (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw"))
80e8bb90 4120 (zero_extend:V8HI
3bb345c9 4121 (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))
80e8bb90
RH		 4122 (const_vector:V8HI [(const_int 1) (const_int 1)
4123 (const_int 1) (const_int 1)
4124 (const_int 1) (const_int 1)
4125 (const_int 1) (const_int 1)]))
4126 (const_int 1))))]
a899fa35 4127 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
45641b31 4128 && (TARGET_SSE || TARGET_3DNOW)
94538b65 4129 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
80e8bb90 4130{
b49ae8a5
UB		 4131 switch (which_alternative)
4132 {
4133 case 2:
4134 return "vpavgb\t{%2, %1, %0|%0, %1, %2}";
4135 case 1:
4136 case 0:
4137 /* These two instructions have the same operation, but their encoding
4138 is different. Prefer the one that is de facto standard. */
4139 if (TARGET_SSE || TARGET_3DNOW_A)
4140 return "pavgb\t{%2, %0|%0, %2}";
4141 else
4142 return "pavgusb\t{%2, %0|%0, %2}";
4143 default:
4144 gcc_unreachable ();
4145 }
80e8bb90 4146}
b49ae8a5
UB		 4147 [(set_attr "isa" "*,sse2_noavx,avx")
4148 (set_attr "mmx_isa" "native,*,*")
a899fa35 4149 (set_attr "type" "mmxshft,sseiadd,sseiadd")
725fd454
JJ		 4150 (set (attr "prefix_extra")
4151 (if_then_else
67b2c493
RS		 4152 (not (ior (match_test "TARGET_SSE")
4153 (match_test "TARGET_3DNOW_A")))
725fd454
JJ		 4154 (const_string "1")
4155 (const_string "*")))
a899fa35 4156 (set_attr "mode" "DI,TI,TI")])
80e8bb90 4157
ffbaf337 4158(define_insn "*mmx_uavgv4hi3"
3bb345c9 4159 [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
80e8bb90
RH		 4160 (truncate:V4HI
4161 (lshiftrt:V4SI
4162 (plus:V4SI
4163 (plus:V4SI
4164 (zero_extend:V4SI
3bb345c9 4165 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
80e8bb90 4166 (zero_extend:V4SI
3bb345c9 4167 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
80e8bb90
RH		 4168 (const_vector:V4SI [(const_int 1) (const_int 1)
4169 (const_int 1) (const_int 1)]))
4170 (const_int 1))))]
d9d6e621
L		 4171 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4172 && (TARGET_SSE || TARGET_3DNOW_A)
94538b65 4173 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
d9d6e621
L		 4174 "@
4175 pavgw\t{%2, %0|%0, %2}
4176 pavgw\t{%2, %0|%0, %2}
4177 vpavgw\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 4178 [(set_attr "isa" "*,sse2_noavx,avx")
4179 (set_attr "mmx_isa" "native,*,*")
d9d6e621
L		 4180 (set_attr "type" "mmxshft,sseiadd,sseiadd")
4181 (set_attr "mode" "DI,TI,TI")])
80e8bb90 4182
94538b65
UB		 4183(define_expand "uavg<mode>3_ceil"
4184 [(set (match_operand:MMXMODE12 0 "register_operand")
4185 (truncate:MMXMODE12
4186 (lshiftrt:<mmxdoublemode>
4187 (plus:<mmxdoublemode>
4188 (plus:<mmxdoublemode>
4189 (zero_extend:<mmxdoublemode>
4190 (match_operand:MMXMODE12 1 "register_operand"))
4191 (zero_extend:<mmxdoublemode>
4192 (match_operand:MMXMODE12 2 "register_operand")))
4193 (match_dup 3))
4194 (const_int 1))))]
4195 "TARGET_MMX_WITH_SSE"
a617e5d5 4196 "operands[3] = CONST1_RTX(<mmxdoublemode>mode);")
94538b65 4197
04ba00d4
UB		 4198(define_insn "uavgv4qi3_ceil"
4199 [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4200 (truncate:V4QI
4201 (lshiftrt:V4HI
4202 (plus:V4HI
4203 (plus:V4HI
4204 (zero_extend:V4HI
4205 (match_operand:V4QI 1 "register_operand" "%0,Yw"))
4206 (zero_extend:V4HI
4207 (match_operand:V4QI 2 "register_operand" "x,Yw")))
4208 (const_vector:V4HI [(const_int 1) (const_int 1)
4209 (const_int 1) (const_int 1)]))
4210 (const_int 1))))]
4211 "TARGET_SSE2"
4212 "@
4213 pavgb\t{%2, %0|%0, %2}
4214 vpavgb\t{%2, %1, %0|%0, %1, %2}"
4215 [(set_attr "isa" "noavx,avx")
4216 (set_attr "type" "sseiadd")
4217 (set_attr "mode" "TI")])
4218
4219(define_insn "uavgv2hi3_ceil"
4220 [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
4221 (truncate:V2HI
4222 (lshiftrt:V2SI
4223 (plus:V2SI
4224 (plus:V2SI
4225 (zero_extend:V2SI
4226 (match_operand:V2HI 1 "register_operand" "%0,Yw"))
4227 (zero_extend:V2SI
4228 (match_operand:V2HI 2 "register_operand" "x,Yw")))
4229 (const_vector:V2SI [(const_int 1) (const_int 1)]))
4230 (const_int 1))))]
4231 "TARGET_SSE2"
4232 "@
4233 pavgw\t{%2, %0|%0, %2}
4234 vpavgw\t{%2, %1, %0|%0, %1, %2}"
4235 [(set_attr "isa" "noavx,avx")
4236 (set_attr "type" "sseiadd")
4237 (set_attr "mode" "TI")])
4238
80e8bb90 4239(define_insn "mmx_psadbw"
3bb345c9
JJ		 4240 [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yw")
4241 (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yw")
4242 (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")]
ab555a5b 4243 UNSPEC_PSADBW))]
018a45bd
L		 4244 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4245 && (TARGET_SSE || TARGET_3DNOW_A)"
4246 "@
4247 psadbw\t{%2, %0|%0, %2}
4248 psadbw\t{%2, %0|%0, %2}
4249 vpsadbw\t{%2, %1, %0|%0, %1, %2}"
b49ae8a5
UB		 4250 [(set_attr "isa" "*,sse2_noavx,avx")
4251 (set_attr "mmx_isa" "native,*,*")
018a45bd
L		 4252 (set_attr "type" "mmxshft,sseiadd,sseiadd")
4253 (set_attr "mode" "DI,TI,TI")])
80e8bb90 4254
538e4cdc
JJ		 4255(define_expand "reduc_plus_scal_v8qi"
4256 [(plus:V8QI
4257 (match_operand:QI 0 "register_operand")
4258 (match_operand:V8QI 1 "register_operand"))]
4259 "TARGET_MMX_WITH_SSE"
4260{
4261 rtx tmp = gen_reg_rtx (V8QImode);
4262 emit_move_insn (tmp, CONST0_RTX (V8QImode));
4263 rtx tmp2 = gen_reg_rtx (V1DImode);
4264 emit_insn (gen_mmx_psadbw (tmp2, operands[1], tmp));
4265 tmp2 = gen_lowpart (V8QImode, tmp2);
4266 emit_insn (gen_vec_extractv8qiqi (operands[0], tmp2, const0_rtx));
4267 DONE;
4268})
4269
77ca2cfc 4270(define_expand "reduc_plus_scal_v4hi"
4271 [(plus:V4HI
4272 (match_operand:HI 0 "register_operand")
4273 (match_operand:V4HI 1 "register_operand"))]
4274 "TARGET_MMX_WITH_SSE"
4275{
4276 rtx tmp = gen_reg_rtx (V4HImode);
4277 ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
4278 emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
4279 DONE;
4280})
4281
4282(define_expand "reduc_<code>_scal_v4hi"
4283 [(smaxmin:V4HI
4284 (match_operand:HI 0 "register_operand")
4285 (match_operand:V4HI 1 "register_operand"))]
4286 "TARGET_MMX_WITH_SSE"
4287{
4288 rtx tmp = gen_reg_rtx (V4HImode);
4289 ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
4290 emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
4291 DONE;
4292})
4293
73c535a0 4294(define_expand "reduc_<code>_scal_v4qi"
4295 [(smaxmin:V4QI
4296 (match_operand:QI 0 "register_operand")
4297 (match_operand:V4QI 1 "register_operand"))]
4298 "TARGET_SSE4_1"
4299{
4300 rtx tmp = gen_reg_rtx (V4QImode);
4301 ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
4302 emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
4303 DONE;
4304})
4305
77ca2cfc 4306(define_expand "reduc_<code>_scal_v4hi"
4307 [(umaxmin:V4HI
4308 (match_operand:HI 0 "register_operand")
4309 (match_operand:V4HI 1 "register_operand"))]
4310 "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
4311{
4312 rtx tmp = gen_reg_rtx (V4HImode);
4313 ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
4314 emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
4315 DONE;
4316})
4317
73c535a0 4318(define_expand "reduc_<code>_scal_v4qi"
4319 [(umaxmin:V4QI
4320 (match_operand:QI 0 "register_operand")
4321 (match_operand:V4QI 1 "register_operand"))]
4322 "TARGET_SSE4_1"
4323{
4324 rtx tmp = gen_reg_rtx (V4QImode);
4325 ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
4326 emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
4327 DONE;
4328})
4329
4330(define_expand "reduc_plus_scal_v4qi"
4331 [(plus:V4QI
4332 (match_operand:QI 0 "register_operand")
4333 (match_operand:V4QI 1 "register_operand"))]
4334 "TARGET_SSE2"
4335{
4336 rtx op1 = gen_reg_rtx (V16QImode);
4337 emit_insn (gen_vec_setv4si_0 (lowpart_subreg (V4SImode, op1, V16QImode),
4338 CONST0_RTX (V4SImode),
4339 lowpart_subreg (SImode,
4340 operands[1],
4341 V4QImode)));
4342 rtx tmp = gen_reg_rtx (V16QImode);
4343 emit_move_insn (tmp, CONST0_RTX (V16QImode));
4344 rtx tmp2 = gen_reg_rtx (V2DImode);
4345 emit_insn (gen_sse2_psadbw (tmp2, op1, tmp));
4346 tmp2 = gen_lowpart (V16QImode, tmp2);
4347 emit_insn (gen_vec_extractv16qiqi (operands[0], tmp2, const0_rtx));
4348 DONE;
4349})
4350
45230a40
UB		 4351(define_expand "usadv8qi"
4352 [(match_operand:V2SI 0 "register_operand")
4353 (match_operand:V8QI 1 "register_operand")
5b7ed762
JJ		 4354 (match_operand:V8QI 2 "register_operand")
4355 (match_operand:V2SI 3 "register_operand")]
45230a40
UB		 4356 "TARGET_MMX_WITH_SSE"
4357{
4358 rtx t1 = gen_reg_rtx (V1DImode);
4359 rtx t2 = gen_reg_rtx (V2SImode);
4360 emit_insn (gen_mmx_psadbw (t1, operands[1], operands[2]));
4361 convert_move (t2, t1, 0);
4362 emit_insn (gen_addv2si3 (operands[0], t2, operands[3]));
4363 DONE;
4364})
4365
73371f6a
L		 4366(define_insn_and_split "mmx_pmovmskb"
4367 [(set (match_operand:SI 0 "register_operand" "=r,r")
4368 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")]
80e8bb90 4369 UNSPEC_MOVMSK))]
73371f6a
L		 4370 "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4371 && (TARGET_SSE || TARGET_3DNOW_A)"
4372 "@
4373 pmovmskb\t{%1, %0|%0, %1}
4374 #"
dab0477b
UB		 4375 "TARGET_SSE2 && reload_completed
4376 && SSE_REGNO_P (REGNO (operands[1]))"
73371f6a
L		 4377 [(set (match_dup 0)
4378 (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
4379 (set (match_dup 0)
4380 (zero_extend:SI (match_dup 2)))]
4381{
4382 /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
4383 operands[1] = lowpart_subreg (V16QImode, operands[1],
4384 GET_MODE (operands[1]));
4385 operands[2] = lowpart_subreg (QImode, operands[0],
4386 GET_MODE (operands[0]));
4387}
b49ae8a5 4388 [(set_attr "mmx_isa" "native,sse")
73371f6a
L		 4389 (set_attr "type" "mmxcvt,ssemov")
4390 (set_attr "mode" "DI,TI")])
80e8bb90
RH		 4391
4392(define_expand "mmx_maskmovq"
82e86dc6
UB		 4393 [(set (match_operand:V8QI 0 "memory_operand")
4394 (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
4395 (match_operand:V8QI 2 "register_operand")
80e8bb90
RH		 4396 (match_dup 0)]
4397 UNSPEC_MASKMOV))]
a427621f 4398 "TARGET_SSE || TARGET_3DNOW_A")
80e8bb90
RH		 4399
4400(define_insn "*mmx_maskmovq"
d7115452 4401 [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
80e8bb90
RH		 4402 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
4403 (match_operand:V8QI 2 "register_operand" "y")
4404 (mem:V8QI (match_dup 0))]
4405 UNSPEC_MASKMOV))]
d7115452 4406 "TARGET_SSE || TARGET_3DNOW_A"
80e8bb90
RH		 4407 ;; @@@ check ordering of operands in intel/nonintel syntax
4408 "maskmovq\t{%2, %1|%1, %2}"
4409 [(set_attr "type" "mmxcvt")
9ce29eb0 4410 (set_attr "znver1_decode" "vector")
80e8bb90
RH		 4411 (set_attr "mode" "DI")])
4412
b38ab29f
UB		 4413(define_int_iterator EMMS
4414 [(UNSPECV_EMMS "TARGET_MMX")
4415 (UNSPECV_FEMMS "TARGET_3DNOW")])
4416
4417(define_int_attr emms
4418 [(UNSPECV_EMMS "emms")
4419 (UNSPECV_FEMMS "femms")])
4420
84791fca
L		 4421(define_expand "mmx_<emms>"
4422 [(parallel
4423 [(unspec_volatile [(const_int 0)] EMMS)
4424 (clobber (reg:XF ST0_REG))
4425 (clobber (reg:XF ST1_REG))
4426 (clobber (reg:XF ST2_REG))
4427 (clobber (reg:XF ST3_REG))
4428 (clobber (reg:XF ST4_REG))
4429 (clobber (reg:XF ST5_REG))
4430 (clobber (reg:XF ST6_REG))
4431 (clobber (reg:XF ST7_REG))
4432 (clobber (reg:DI MM0_REG))
4433 (clobber (reg:DI MM1_REG))
4434 (clobber (reg:DI MM2_REG))
4435 (clobber (reg:DI MM3_REG))
4436 (clobber (reg:DI MM4_REG))
4437 (clobber (reg:DI MM5_REG))
4438 (clobber (reg:DI MM6_REG))
4439 (clobber (reg:DI MM7_REG))])]
4440 "TARGET_MMX || TARGET_MMX_WITH_SSE"
4441{
4442 if (!TARGET_MMX)
4443 {
4444 emit_insn (gen_nop ());
4445 DONE;
4446 }
4447})
4448
4449(define_insn "*mmx_<emms>"
b38ab29f
UB		 4450 [(unspec_volatile [(const_int 0)] EMMS)
4451 (clobber (reg:XF ST0_REG))
4452 (clobber (reg:XF ST1_REG))
4453 (clobber (reg:XF ST2_REG))
4454 (clobber (reg:XF ST3_REG))
4455 (clobber (reg:XF ST4_REG))
4456 (clobber (reg:XF ST5_REG))
4457 (clobber (reg:XF ST6_REG))
4458 (clobber (reg:XF ST7_REG))
4459 (clobber (reg:DI MM0_REG))
4460 (clobber (reg:DI MM1_REG))
4461 (clobber (reg:DI MM2_REG))
4462 (clobber (reg:DI MM3_REG))
4463 (clobber (reg:DI MM4_REG))
4464 (clobber (reg:DI MM5_REG))
4465 (clobber (reg:DI MM6_REG))
4466 (clobber (reg:DI MM7_REG))]
4467 ""
4468 "<emms>"
80e8bb90 4469 [(set_attr "type" "mmx")
725fd454 4470 (set_attr "modrm" "0")
4f3f76e6 4471 (set_attr "memory" "none")])
Mirror of https://gcc.gnu.org/git/gcc.git