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7adcbafe 1;; Copyright (C) 2012-2022 Free Software Foundation, Inc.
9ce29eb0
VK		 2;;
3;; This file is part of GCC.
4;;
5;; GCC is free software; you can redistribute it and/or modify
6;; it under the terms of the GNU General Public License as published by
7;; the Free Software Foundation; either version 3, or (at your option)
8;; any later version.
9;;
10;; GCC is distributed in the hope that it will be useful,
11;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13;; GNU General Public License for more details.
14;;
15;; You should have received a copy of the GNU General Public License
16;; along with GCC; see the file COPYING3. If not see
17;; <http://www.gnu.org/licenses/>.
18;;
19
e1eb82f5 20
9ce29eb0
VK		 21(define_attr "znver1_decode" "direct,vector,double"
22 (const_string "direct"))
23
3e2ae3ee 24;; AMD znver1, znver2 and znver3 Scheduling
9ce29eb0
VK		 25;; Modeling automatons for zen decoders, integer execution pipes,
26;; AGU pipes and floating point execution units.
27(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu")
28
29;; Decoders unit has 4 decoders and all of them can decode fast path
30;; and vector type instructions.
31(define_cpu_unit "znver1-decode0" "znver1")
32(define_cpu_unit "znver1-decode1" "znver1")
33(define_cpu_unit "znver1-decode2" "znver1")
34(define_cpu_unit "znver1-decode3" "znver1")
35
36;; Currently blocking all decoders for vector path instructions as
37;; they are dispatched separetely as microcode sequence.
38;; Fix me: Need to revisit this.
39(define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3")
40
41;; Direct instructions can be issued to any of the four decoders.
42(define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3")
43
9c582551 44;; Fix me: Need to revisit this later to simulate fast path double behavior.
9ce29eb0
VK		 45(define_reservation "znver1-double" "znver1-direct")
46
47
48;; Integer unit 4 ALU pipes.
49(define_cpu_unit "znver1-ieu0" "znver1_ieu")
50(define_cpu_unit "znver1-ieu1" "znver1_ieu")
51(define_cpu_unit "znver1-ieu2" "znver1_ieu")
52(define_cpu_unit "znver1-ieu3" "znver1_ieu")
53(define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3")
54
3e2ae3ee 55;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2 and znver3
e1eb82f5 56;; According to CPU diagram last AGU unit is used only for stores.
9ce29eb0
VK		 57(define_cpu_unit "znver1-agu0" "znver1_agu")
58(define_cpu_unit "znver1-agu1" "znver1_agu")
e1eb82f5 59(define_cpu_unit "znver2-agu2" "znver1_agu")
9ce29eb0 60(define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1")
e1eb82f5 61(define_reservation "znver2-store-agu-reserve" "znver1-agu0|znver1-agu1|znver2-agu2")
9ce29eb0 62
e1eb82f5
JH		 63;; Load is 4 cycles. We do not model reservation of load unit.
64;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
9ce29eb0 65(define_reservation "znver1-load" "znver1-agu-reserve")
3e2ae3ee 66;; Store operations differs between znver1, znver2 and znver3 because extra AGU
e1eb82f5 67;; was added.
9ce29eb0 68(define_reservation "znver1-store" "znver1-agu-reserve")
e1eb82f5 69(define_reservation "znver2-store" "znver2-store-agu-reserve")
9ce29eb0
VK		 70
71;; vectorpath (microcoded) instructions are single issue instructions.
72;; So, they occupy all the integer units.
73(define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1
74 +znver1-ieu2+znver1-ieu3
75 +znver1-agu0+znver1-agu1")
76
e1eb82f5
JH		 77(define_reservation "znver2-ivector" "znver1-ieu0+znver1-ieu1
78 +znver1-ieu2+znver1-ieu3
79 +znver1-agu0+znver1-agu1+znver2-agu2")
3e2ae3ee 80
9ce29eb0
VK		 81;; Floating point unit 4 FP pipes.
82(define_cpu_unit "znver1-fp0" "znver1_fp")
83(define_cpu_unit "znver1-fp1" "znver1_fp")
84(define_cpu_unit "znver1-fp2" "znver1_fp")
85(define_cpu_unit "znver1-fp3" "znver1_fp")
86
87(define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3")
88
89(define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1
90 +znver1-fp2+znver1-fp3
91 +znver1-agu0+znver1-agu1")
e1eb82f5
JH		 92(define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1
93 +znver1-fp2+znver1-fp3
94 +znver1-agu0+znver1-agu1+znver2-agu2")
9ce29eb0
VK		 95
96;; Call instruction
97(define_insn_reservation "znver1_call" 1
98 (and (eq_attr "cpu" "znver1")
99 (eq_attr "type" "call,callv"))
100 "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3")
101
e1eb82f5 102(define_insn_reservation "znver2_call" 1
3e2ae3ee 103 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 104 (eq_attr "type" "call,callv"))
105 "znver1-double,znver2-store,znver1-ieu0|znver1-ieu3")
106
9ce29eb0
VK		 107;; General instructions
108(define_insn_reservation "znver1_push" 1
109 (and (eq_attr "cpu" "znver1")
110 (and (eq_attr "type" "push")
e1eb82f5 111 (eq_attr "memory" "store")))
9ce29eb0 112 "znver1-direct,znver1-store")
e1eb82f5 113(define_insn_reservation "znver2_push" 1
3e2ae3ee 114 (and (eq_attr "cpu" "znver2,znver3")
9ce29eb0
VK		 115 (and (eq_attr "type" "push")
116 (eq_attr "memory" "store")))
3e2ae3ee 117 "znver1-direct,znver2-store")
9ce29eb0 118
e1eb82f5 119(define_insn_reservation "znver1_push_load" 4
9ce29eb0
VK		 120 (and (eq_attr "cpu" "znver1")
121 (and (eq_attr "type" "push")
122 (eq_attr "memory" "both")))
123 "znver1-direct,znver1-load,znver1-store")
e1eb82f5 124(define_insn_reservation "znver2_push_load" 4
3e2ae3ee 125 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 126 (and (eq_attr "type" "push")
127 (eq_attr "memory" "both")))
128 "znver1-direct,znver1-load,znver2-store")
9ce29eb0 129
cdc647c3 130(define_insn_reservation "znver1_pop" 4
3e2ae3ee 131 (and (eq_attr "cpu" "znver1,znver2,znver3")
cdc647c3
VK		 132 (and (eq_attr "type" "pop")
133 (eq_attr "memory" "load")))
134 "znver1-direct,znver1-load")
135
136(define_insn_reservation "znver1_pop_mem" 4
137 (and (eq_attr "cpu" "znver1")
138 (and (eq_attr "type" "pop")
139 (eq_attr "memory" "both")))
140 "znver1-direct,znver1-load,znver1-store")
e1eb82f5 141(define_insn_reservation "znver2_pop_mem" 4
3e2ae3ee 142 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 143 (and (eq_attr "type" "pop")
144 (eq_attr "memory" "both")))
145 "znver1-direct,znver1-load,znver2-store")
cdc647c3 146
9ce29eb0
VK		 147;; Leave
148(define_insn_reservation "znver1_leave" 1
149 (and (eq_attr "cpu" "znver1")
150 (eq_attr "type" "leave"))
151 "znver1-double,znver1-ieu, znver1-store")
e1eb82f5 152(define_insn_reservation "znver2_leave" 1
3e2ae3ee 153 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 154 (eq_attr "type" "leave"))
155 "znver1-double,znver1-ieu, znver2-store")
9ce29eb0 156
bd2c6270 157;; Integer Instructions or General instructions
9ce29eb0
VK		 158;; Multiplications
159;; Reg operands
160(define_insn_reservation "znver1_imul" 3
3e2ae3ee 161 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 162 (and (eq_attr "type" "imul")
163 (eq_attr "memory" "none")))
164 "znver1-direct,znver1-ieu1")
165
166(define_insn_reservation "znver1_imul_mem" 7
3e2ae3ee 167 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 168 (and (eq_attr "type" "imul")
169 (eq_attr "memory" "!none")))
170 "znver1-direct,znver1-load, znver1-ieu1")
171
172;; Divisions
173;; Reg operands
174(define_insn_reservation "znver1_idiv_DI" 41
e1eb82f5 175 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 176 (and (eq_attr "type" "idiv")
177 (and (eq_attr "mode" "DI")
178 (eq_attr "memory" "none"))))
179 "znver1-double,znver1-ieu2*41")
180
181(define_insn_reservation "znver1_idiv_SI" 25
e1eb82f5 182 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 183 (and (eq_attr "type" "idiv")
184 (and (eq_attr "mode" "SI")
185 (eq_attr "memory" "none"))))
186 "znver1-double,znver1-ieu2*25")
187
188(define_insn_reservation "znver1_idiv_HI" 17
e1eb82f5 189 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 190 (and (eq_attr "type" "idiv")
191 (and (eq_attr "mode" "HI")
192 (eq_attr "memory" "none"))))
193 "znver1-double,znver1-ieu2*17")
194
195(define_insn_reservation "znver1_idiv_QI" 12
e1eb82f5 196 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 197 (and (eq_attr "type" "idiv")
198 (and (eq_attr "mode" "QI")
199 (eq_attr "memory" "none"))))
200 "znver1-direct,znver1-ieu2*12")
201
202;; Mem operands
203(define_insn_reservation "znver1_idiv_mem_DI" 45
e1eb82f5 204 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 205 (and (eq_attr "type" "idiv")
206 (and (eq_attr "mode" "DI")
207 (eq_attr "memory" "none"))))
208 "znver1-double,znver1-load,znver1-ieu2*41")
209
210(define_insn_reservation "znver1_idiv_mem_SI" 29
e1eb82f5 211 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 212 (and (eq_attr "type" "idiv")
213 (and (eq_attr "mode" "SI")
214 (eq_attr "memory" "none"))))
215 "znver1-double,znver1-load,znver1-ieu2*25")
216
217(define_insn_reservation "znver1_idiv_mem_HI" 21
e1eb82f5 218 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 219 (and (eq_attr "type" "idiv")
220 (and (eq_attr "mode" "HI")
221 (eq_attr "memory" "none"))))
222 "znver1-double,znver1-load,znver1-ieu2*17")
223
224(define_insn_reservation "znver1_idiv_mem_QI" 16
e1eb82f5 225 (and (eq_attr "cpu" "znver1,znver2")
9ce29eb0
VK		 226 (and (eq_attr "type" "idiv")
227 (and (eq_attr "mode" "QI")
228 (eq_attr "memory" "none"))))
229 "znver1-direct,znver1-load,znver1-ieu2*12")
230
3e2ae3ee
VK		 231(define_insn_reservation "znver3_idiv_DI" 18
232 (and (eq_attr "cpu" "znver3")
233 (and (eq_attr "type" "idiv")
234 (and (eq_attr "mode" "DI")
235 (eq_attr "memory" "none"))))
236 "znver1-double,znver1-ieu2*18")
237
238(define_insn_reservation "znver3_idiv_SI" 12
239 (and (eq_attr "cpu" "znver3")
240 (and (eq_attr "type" "idiv")
241 (and (eq_attr "mode" "SI")
242 (eq_attr "memory" "none"))))
243 "znver1-double,znver1-ieu2*12")
244
245(define_insn_reservation "znver3_idiv_HI" 10
246 (and (eq_attr "cpu" "znver3")
247 (and (eq_attr "type" "idiv")
248 (and (eq_attr "mode" "HI")
249 (eq_attr "memory" "none"))))
250 "znver1-double,znver1-ieu2*10")
251
252(define_insn_reservation "znver3_idiv_QI" 9
253 (and (eq_attr "cpu" "znver3")
254 (and (eq_attr "type" "idiv")
255 (and (eq_attr "mode" "QI")
256 (eq_attr "memory" "none"))))
257 "znver1-direct,znver1-ieu2*9")
258
259(define_insn_reservation "znver3_idiv_mem_DI" 22
260 (and (eq_attr "cpu" "znver3")
261 (and (eq_attr "type" "idiv")
262 (and (eq_attr "mode" "DI")
263 (eq_attr "memory" "load"))))
264 "znver1-double,znver1-load,znver1-ieu2*22")
265
266(define_insn_reservation "znver3_idiv_mem_SI" 16
267 (and (eq_attr "cpu" "znver3")
268 (and (eq_attr "type" "idiv")
269 (and (eq_attr "mode" "SI")
270 (eq_attr "memory" "load"))))
271 "znver1-double,znver1-load,znver1-ieu2*16")
272
273(define_insn_reservation "znver3_idiv_mem_HI" 14
274 (and (eq_attr "cpu" "znver3")
275 (and (eq_attr "type" "idiv")
276 (and (eq_attr "mode" "HI")
277 (eq_attr "memory" "load"))))
278 "znver1-double,znver1-load,znver1-ieu2*10")
279
280(define_insn_reservation "znver3_idiv_mem_QI" 13
281 (and (eq_attr "cpu" "znver3")
282 (and (eq_attr "type" "idiv")
283 (and (eq_attr "mode" "QI")
284 (eq_attr "memory" "load"))))
285 "znver1-direct,znver1-load,znver1-ieu2*9")
286
9ce29eb0
VK		 287;; STR ISHIFT which are micro coded.
288;; Fix me: Latency need to be rechecked.
289(define_insn_reservation "znver1_str_ishift" 6
290 (and (eq_attr "cpu" "znver1")
291 (and (eq_attr "type" "str,ishift")
292 (eq_attr "memory" "both,store")))
293 "znver1-vector,znver1-ivector")
e1eb82f5
JH		 294
295(define_insn_reservation "znver2_str_ishift" 3
3e2ae3ee 296 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 297 (and (eq_attr "type" "ishift")
298 (eq_attr "memory" "both,store")))
299 "znver1-vector,znver1-ivector")
300(define_insn_reservation "znver2_str_istr" 19
3e2ae3ee 301 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 302 (and (eq_attr "type" "str")
303 (eq_attr "memory" "both,store")))
304 "znver1-vector,znver1-ivector")
3e2ae3ee 305
9ce29eb0
VK		 306;; MOV - integer moves
307(define_insn_reservation "znver1_load_imov_double" 2
308 (and (eq_attr "cpu" "znver1")
309 (and (eq_attr "znver1_decode" "double")
310 (and (eq_attr "type" "imovx")
cdc647c3 311 (eq_attr "memory" "none"))))
e1eb82f5
JH		 312 "znver1-double,znver1-ieu|znver1-ieu")
313
314(define_insn_reservation "znver2_load_imov_double" 1
3e2ae3ee 315 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 316 (and (eq_attr "znver1_decode" "double")
317 (and (eq_attr "type" "imovx")
318 (eq_attr "memory" "none"))))
319 "znver1-double,znver1-ieu|znver1-ieu")
9ce29eb0
VK		 320
321(define_insn_reservation "znver1_load_imov_direct" 1
3e2ae3ee 322 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0 323 (and (eq_attr "type" "imov,imovx")
cdc647c3 324 (eq_attr "memory" "none")))
9ce29eb0
VK		 325 "znver1-direct,znver1-ieu")
326
cdc647c3
VK		 327(define_insn_reservation "znver1_load_imov_double_store" 2
328 (and (eq_attr "cpu" "znver1")
329 (and (eq_attr "znver1_decode" "double")
330 (and (eq_attr "type" "imovx")
331 (eq_attr "memory" "store"))))
e1eb82f5
JH		 332 "znver1-double,znver1-ieu|znver1-ieu,znver1-store")
333
334(define_insn_reservation "znver2_load_imov_double_store" 1
3e2ae3ee 335 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 336 (and (eq_attr "znver1_decode" "double")
337 (and (eq_attr "type" "imovx")
338 (eq_attr "memory" "store"))))
339 "znver1-double,znver1-ieu|znver1-ieu,znver2-store")
cdc647c3
VK		 340
341(define_insn_reservation "znver1_load_imov_direct_store" 1
342 (and (eq_attr "cpu" "znver1")
343 (and (eq_attr "type" "imov,imovx")
344 (eq_attr "memory" "store")))
345 "znver1-direct,znver1-ieu,znver1-store")
346
e1eb82f5 347(define_insn_reservation "znver2_load_imov_direct_store" 1
3e2ae3ee 348 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 349 (and (eq_attr "type" "imov,imovx")
350 (eq_attr "memory" "store")))
351 "znver1-direct,znver1-ieu,znver2-store")
352
1d0eabee 353(define_insn_reservation "znver1_load_imov_double_load" 5
e1eb82f5 354 (and (eq_attr "cpu" "znver1,znver2")
cdc647c3
VK		 355 (and (eq_attr "znver1_decode" "double")
356 (and (eq_attr "type" "imovx")
357 (eq_attr "memory" "load"))))
e1eb82f5
JH		 358 "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
359
360(define_insn_reservation "znver2_load_imov_double_load" 4
3e2ae3ee 361 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 362 (and (eq_attr "znver1_decode" "double")
363 (and (eq_attr "type" "imovx")
364 (eq_attr "memory" "load"))))
365 "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
cdc647c3 366
1d0eabee 367(define_insn_reservation "znver1_load_imov_direct_load" 4
3e2ae3ee 368 (and (eq_attr "cpu" "znver1,znver2,znver3")
cdc647c3
VK		 369 (and (eq_attr "type" "imov,imovx")
370 (eq_attr "memory" "load")))
1d0eabee 371 "znver1-direct,znver1-load")
cdc647c3 372
9ce29eb0
VK		 373;; INTEGER/GENERAL instructions
374;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
375(define_insn_reservation "znver1_insn" 1
3e2ae3ee 376 (and (eq_attr "cpu" "znver1,znver2,znver3")
cdc647c3 377 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
9ce29eb0
VK		 378 (eq_attr "memory" "none,unknown")))
379 "znver1-direct,znver1-ieu")
380
381(define_insn_reservation "znver1_insn_load" 5
3e2ae3ee 382 (and (eq_attr "cpu" "znver1,znver2,znver3")
cdc647c3 383 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
9ce29eb0
VK		 384 (eq_attr "memory" "load")))
385 "znver1-direct,znver1-load,znver1-ieu")
386
387(define_insn_reservation "znver1_insn_store" 1
388 (and (eq_attr "cpu" "znver1")
389 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
390 (eq_attr "memory" "store")))
391 "znver1-direct,znver1-ieu,znver1-store")
392
e1eb82f5 393(define_insn_reservation "znver2_insn_store" 1
3e2ae3ee 394 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 395 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
396 (eq_attr "memory" "store")))
397 "znver1-direct,znver1-ieu,znver2-store")
398
9ce29eb0
VK		 399(define_insn_reservation "znver1_insn_both" 5
400 (and (eq_attr "cpu" "znver1")
401 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
402 (eq_attr "memory" "both")))
403 "znver1-direct,znver1-load,znver1-ieu,znver1-store")
404
e1eb82f5 405(define_insn_reservation "znver2_insn_both" 5
3e2ae3ee 406 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 407 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
408 (eq_attr "memory" "both")))
409 "znver1-direct,znver1-load,znver1-ieu,znver2-store")
410
9ce29eb0
VK		 411;; Fix me: Other vector type insns keeping latency 6 as of now.
412(define_insn_reservation "znver1_ieu_vector" 6
413 (and (eq_attr "cpu" "znver1")
414 (eq_attr "type" "other,str,multi"))
415 "znver1-vector,znver1-ivector")
416
e1eb82f5 417(define_insn_reservation "znver2_ieu_vector" 5
3e2ae3ee 418 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 419 (eq_attr "type" "other,str,multi"))
420 "znver1-vector,znver2-ivector")
421
9ce29eb0
VK		 422;; ALU1 register operands.
423(define_insn_reservation "znver1_alu1_vector" 3
424 (and (eq_attr "cpu" "znver1")
425 (and (eq_attr "znver1_decode" "vector")
426 (and (eq_attr "type" "alu1")
427 (eq_attr "memory" "none,unknown"))))
428 "znver1-vector,znver1-ivector")
429
e1eb82f5 430(define_insn_reservation "znver2_alu1_vector" 3
3e2ae3ee 431 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 432 (and (eq_attr "znver1_decode" "vector")
433 (and (eq_attr "type" "alu1")
434 (eq_attr "memory" "none,unknown"))))
435 "znver1-vector,znver2-ivector")
436
9ce29eb0 437(define_insn_reservation "znver1_alu1_double" 2
3e2ae3ee 438 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 439 (and (eq_attr "znver1_decode" "double")
440 (and (eq_attr "type" "alu1")
441 (eq_attr "memory" "none,unknown"))))
442 "znver1-double,znver1-ieu")
443
444(define_insn_reservation "znver1_alu1_direct" 1
3e2ae3ee 445 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 446 (and (eq_attr "znver1_decode" "direct")
447 (and (eq_attr "type" "alu1")
448 (eq_attr "memory" "none,unknown"))))
449 "znver1-direct,znver1-ieu")
450
451;; Branches : Fix me need to model conditional branches.
452(define_insn_reservation "znver1_branch" 1
3e2ae3ee 453 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0 454 (and (eq_attr "type" "ibr")
3e2ae3ee 455 (eq_attr "memory" "none")))
9ce29eb0
VK		 456 "znver1-direct")
457
458;; Indirect branches check latencies.
459(define_insn_reservation "znver1_indirect_branch_mem" 6
460 (and (eq_attr "cpu" "znver1")
461 (and (eq_attr "type" "ibr")
3e2ae3ee 462 (eq_attr "memory" "load")))
9ce29eb0
VK		 463 "znver1-vector,znver1-ivector")
464
e1eb82f5 465(define_insn_reservation "znver2_indirect_branch_mem" 6
3e2ae3ee 466 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5 467 (and (eq_attr "type" "ibr")
3e2ae3ee 468 (eq_attr "memory" "load")))
e1eb82f5
JH		 469 "znver1-vector,znver2-ivector")
470
9ce29eb0
VK		 471;; LEA executes in ALU units with 1 cycle latency.
472(define_insn_reservation "znver1_lea" 1
3e2ae3ee 473 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 474 (eq_attr "type" "lea"))
475 "znver1-direct,znver1-ieu")
476
477;; Other integer instrucions
478(define_insn_reservation "znver1_idirect" 1
3e2ae3ee 479 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 480 (and (eq_attr "unit" "integer,unknown")
481 (eq_attr "memory" "none,unknown")))
482 "znver1-direct,znver1-ieu")
483
484;; Floating point
485(define_insn_reservation "znver1_fp_cmov" 6
3e2ae3ee 486 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 487 (eq_attr "type" "fcmov"))
488 "znver1-vector,znver1-fvector")
489
a065dbc9 490(define_insn_reservation "znver1_fp_mov_direct_load" 8
3e2ae3ee 491 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 492 (and (eq_attr "znver1_decode" "direct")
493 (and (eq_attr "type" "fmov")
494 (eq_attr "memory" "load"))))
495 "znver1-direct,znver1-load,znver1-fp3|znver1-fp1")
496
497(define_insn_reservation "znver1_fp_mov_direct_store" 5
498 (and (eq_attr "cpu" "znver1")
499 (and (eq_attr "znver1_decode" "direct")
500 (and (eq_attr "type" "fmov")
501 (eq_attr "memory" "store"))))
502 "znver1-direct,znver1-fp2|znver1-fp3,znver1-store")
e1eb82f5 503(define_insn_reservation "znver2_fp_mov_direct_store" 5
3e2ae3ee 504 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 505 (and (eq_attr "znver1_decode" "direct")
506 (and (eq_attr "type" "fmov")
507 (eq_attr "memory" "store"))))
508 "znver1-direct,znver1-fp2|znver1-fp3,znver2-store")
9ce29eb0
VK		 509
510(define_insn_reservation "znver1_fp_mov_double" 4
3e2ae3ee 511 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 512 (and (eq_attr "znver1_decode" "double")
513 (and (eq_attr "type" "fmov")
514 (eq_attr "memory" "none"))))
515 "znver1-double,znver1-fp3")
516
a065dbc9 517(define_insn_reservation "znver1_fp_mov_double_load" 12
3e2ae3ee 518 (and (eq_attr "cpu" "znver1,znver2,znver3")
e1eb82f5
JH		 519 (and (eq_attr "znver1_decode" "double")
520 (and (eq_attr "type" "fmov")
521 (eq_attr "memory" "load"))))
522 "znver1-double,znver1-load,znver1-fp3")
523
9ce29eb0 524(define_insn_reservation "znver1_fp_mov_direct" 1
3e2ae3ee 525 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 526 (eq_attr "type" "fmov"))
527 "znver1-direct,znver1-fp3")
528
e1eb82f5 529;; TODO: AGU?
9ce29eb0 530(define_insn_reservation "znver1_fp_spc_direct" 5
3e2ae3ee 531 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 532 (and (eq_attr "type" "fpspc")
533 (eq_attr "memory" "store")))
534 "znver1-direct,znver1-fp3,znver1-fp2")
535
536(define_insn_reservation "znver1_fp_insn_vector" 6
537 (and (eq_attr "cpu" "znver1")
538 (and (eq_attr "znver1_decode" "vector")
539 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
540 "znver1-vector,znver1-fvector")
e1eb82f5 541(define_insn_reservation "znver2_fp_insn_vector" 6
3e2ae3ee 542 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 543 (and (eq_attr "znver1_decode" "vector")
544 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
545 "znver1-vector,znver2-fvector")
9ce29eb0
VK		 546
547;; FABS
548(define_insn_reservation "znver1_fp_fsgn" 1
3e2ae3ee 549 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 550 (eq_attr "type" "fsgn"))
551 "znver1-direct,znver1-fp3")
552
553(define_insn_reservation "znver1_fp_fcmp" 2
3e2ae3ee 554 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 555 (and (eq_attr "memory" "none")
556 (and (eq_attr "znver1_decode" "double")
557 (eq_attr "type" "fcmp"))))
558 "znver1-double,znver1-fp0,znver1-fp2")
559
a065dbc9 560(define_insn_reservation "znver1_fp_fcmp_load" 9
3e2ae3ee 561 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 562 (and (eq_attr "memory" "none")
563 (and (eq_attr "znver1_decode" "double")
564 (eq_attr "type" "fcmp"))))
565 "znver1-double,znver1-load, znver1-fp0,znver1-fp2")
566
567;;FADD FSUB FMUL
568(define_insn_reservation "znver1_fp_op_mul" 5
3e2ae3ee 569 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 570 (and (eq_attr "type" "fop,fmul")
571 (eq_attr "memory" "none")))
572 "znver1-direct,znver1-fp0*5")
573
a065dbc9 574(define_insn_reservation "znver1_fp_op_mul_load" 12
3e2ae3ee 575 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 576 (and (eq_attr "type" "fop,fmul")
577 (eq_attr "memory" "load")))
578 "znver1-direct,znver1-load,znver1-fp0*5")
579
a065dbc9 580(define_insn_reservation "znver1_fp_op_imul_load" 16
3e2ae3ee 581 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 582 (and (eq_attr "type" "fop,fmul")
583 (and (eq_attr "fp_int_src" "true")
584 (eq_attr "memory" "load"))))
585 "znver1-double,znver1-load,znver1-fp3,znver1-fp0")
586
587(define_insn_reservation "znver1_fp_op_div" 15
3e2ae3ee 588 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 589 (and (eq_attr "type" "fdiv")
590 (eq_attr "memory" "none")))
591 "znver1-direct,znver1-fp3*15")
592
a065dbc9 593(define_insn_reservation "znver1_fp_op_div_load" 22
3e2ae3ee 594 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 595 (and (eq_attr "type" "fdiv")
596 (eq_attr "memory" "load")))
597 "znver1-direct,znver1-load,znver1-fp3*15")
598
a065dbc9 599(define_insn_reservation "znver1_fp_op_idiv_load" 27
9ce29eb0
VK		 600 (and (eq_attr "cpu" "znver1")
601 (and (eq_attr "type" "fdiv")
602 (and (eq_attr "fp_int_src" "true")
603 (eq_attr "memory" "load"))))
604 "znver1-double,znver1-load,znver1-fp3*19")
605
e1eb82f5 606(define_insn_reservation "znver2_fp_op_idiv_load" 26
3e2ae3ee 607 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 608 (and (eq_attr "type" "fdiv")
609 (and (eq_attr "fp_int_src" "true")
610 (eq_attr "memory" "load"))))
611 "znver1-double,znver1-load,znver1-fp3*19")
612
3e2ae3ee 613
9ce29eb0
VK		 614;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
615(define_insn_reservation "znver1_fp_insn" 1
3e2ae3ee 616 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 617 (eq_attr "type" "mmx"))
618 "znver1-direct,znver1-fpu")
619
620(define_insn_reservation "znver1_mmx_add" 1
3e2ae3ee 621 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 622 (and (eq_attr "type" "mmxadd")
623 (eq_attr "memory" "none")))
624 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
625
a065dbc9 626(define_insn_reservation "znver1_mmx_add_load" 8
3e2ae3ee 627 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 628 (and (eq_attr "type" "mmxadd")
629 (eq_attr "memory" "load")))
630 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
631
632(define_insn_reservation "znver1_mmx_cmp" 1
3e2ae3ee 633 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 634 (and (eq_attr "type" "mmxcmp")
635 (eq_attr "memory" "none")))
636 "znver1-direct,znver1-fp0|znver1-fp3")
637
a065dbc9 638(define_insn_reservation "znver1_mmx_cmp_load" 8
3e2ae3ee 639 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 640 (and (eq_attr "type" "mmxcmp")
641 (eq_attr "memory" "load")))
642 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
643
644(define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1
3e2ae3ee 645 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 646 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
647 (eq_attr "memory" "none")))
648 "znver1-direct,znver1-fp1|znver1-fp2")
649
a065dbc9 650(define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8
3e2ae3ee 651 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 652 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
653 (eq_attr "memory" "load")))
654 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
655
656(define_insn_reservation "znver1_mmx_shift_move" 1
3e2ae3ee 657 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 658 (and (eq_attr "type" "mmxshft,mmxmov")
659 (eq_attr "memory" "none")))
3e2ae3ee 660 "znver1-direct,znver1-fp2")
9ce29eb0 661
a065dbc9 662(define_insn_reservation "znver1_mmx_shift_move_load" 8
3e2ae3ee 663 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 664 (and (eq_attr "type" "mmxshft,mmxmov")
665 (eq_attr "memory" "load")))
666 "znver1-direct,znver1-load,znver1-fp2")
667
668(define_insn_reservation "znver1_mmx_move_store" 1
669 (and (eq_attr "cpu" "znver1")
670 (and (eq_attr "type" "mmxshft,mmxmov")
671 (eq_attr "memory" "store,both")))
672 "znver1-direct,znver1-fp2,znver1-store")
e1eb82f5 673(define_insn_reservation "znver2_mmx_move_store" 1
3e2ae3ee 674 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 675 (and (eq_attr "type" "mmxshft,mmxmov")
676 (eq_attr "memory" "store,both")))
677 "znver1-direct,znver1-fp2,znver2-store")
9ce29eb0
VK		 678
679(define_insn_reservation "znver1_mmx_mul" 3
3e2ae3ee 680 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 681 (and (eq_attr "type" "mmxmul")
682 (eq_attr "memory" "none")))
683 "znver1-direct,znver1-fp0*3")
684
a065dbc9 685(define_insn_reservation "znver1_mmx_load" 10
3e2ae3ee 686 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 687 (and (eq_attr "type" "mmxmul")
688 (eq_attr "memory" "load")))
689 "znver1-direct,znver1-load,znver1-fp0*3")
690
e1eb82f5 691;; TODO
9ce29eb0
VK		 692(define_insn_reservation "znver1_avx256_log" 1
693 (and (eq_attr "cpu" "znver1")
694 (and (eq_attr "mode" "V8SF,V4DF,OI")
695 (and (eq_attr "type" "sselog")
696 (eq_attr "memory" "none"))))
697 "znver1-double,znver1-fpu")
698
a065dbc9 699(define_insn_reservation "znver1_avx256_log_load" 8
9ce29eb0
VK		 700 (and (eq_attr "cpu" "znver1")
701 (and (eq_attr "mode" "V8SF,V4DF,OI")
702 (and (eq_attr "type" "sselog")
703 (eq_attr "memory" "load"))))
704 "znver1-double,znver1-load,znver1-fpu")
705
706(define_insn_reservation "znver1_sse_log" 1
3e2ae3ee 707 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 708 (and (eq_attr "type" "sselog")
709 (eq_attr "memory" "none")))
710 "znver1-direct,znver1-fpu")
711
a065dbc9 712(define_insn_reservation "znver1_sse_log_load" 8
3e2ae3ee 713 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 714 (and (eq_attr "type" "sselog")
715 (eq_attr "memory" "load")))
716 "znver1-direct,znver1-load,znver1-fpu")
717
718(define_insn_reservation "znver1_avx256_log1" 1
719 (and (eq_attr "cpu" "znver1")
720 (and (eq_attr "mode" "V8SF,V4DF,OI")
721 (and (eq_attr "type" "sselog1")
722 (eq_attr "memory" "none"))))
723 "znver1-double,znver1-fp1|znver1-fp2")
724
a065dbc9 725(define_insn_reservation "znver1_avx256_log1_load" 8
9ce29eb0
VK		 726 (and (eq_attr "cpu" "znver1")
727 (and (eq_attr "mode" "V8SF,V4DF,OI")
728 (and (eq_attr "type" "sselog1")
729 (eq_attr "memory" "!none"))))
730 "znver1-double,znver1-load,znver1-fp1|znver1-fp2")
731
732(define_insn_reservation "znver1_sse_log1" 1
3e2ae3ee 733 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 734 (and (eq_attr "type" "sselog1")
735 (eq_attr "memory" "none")))
736 "znver1-direct,znver1-fp1|znver1-fp2")
737
a065dbc9 738(define_insn_reservation "znver1_sse_log1_load" 8
3e2ae3ee 739 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 740 (and (eq_attr "type" "sselog1")
741 (eq_attr "memory" "!none")))
742 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
743
744(define_insn_reservation "znver1_sse_comi" 1
745 (and (eq_attr "cpu" "znver1")
746 (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
747 (and (eq_attr "prefix" "!vex")
748 (and (eq_attr "prefix_extra" "0")
749 (and (eq_attr "type" "ssecomi")
750 (eq_attr "memory" "none"))))))
751 "znver1-direct,znver1-fp0|znver1-fp1")
752
a065dbc9 753(define_insn_reservation "znver1_sse_comi_load" 8
e1eb82f5
JH		 754 (and (ior (and (eq_attr "cpu" "znver1")
755 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
3e2ae3ee
VK		 756 (ior (eq_attr "cpu" "znver2")
757 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 758 (and (eq_attr "prefix_extra" "0")
759 (and (eq_attr "type" "ssecomi")
760 (eq_attr "memory" "load"))))
9ce29eb0
VK		 761 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
762
763(define_insn_reservation "znver1_sse_comi_double" 2
e1eb82f5
JH		 764 (and (ior (and (eq_attr "cpu" "znver1")
765 (eq_attr "mode" "V4SF,V2DF,TI"))
3e2ae3ee
VK		 766 (ior (eq_attr "cpu" "znver2")
767 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 768 (and (eq_attr "prefix" "vex")
769 (and (eq_attr "prefix_extra" "0")
770 (and (eq_attr "type" "ssecomi")
771 (eq_attr "memory" "none")))))
9ce29eb0
VK		 772 "znver1-double,znver1-fp0|znver1-fp1")
773
a065dbc9 774(define_insn_reservation "znver1_sse_comi_double_load" 10
e1eb82f5
JH		 775 (and (ior (and (eq_attr "cpu" "znver1")
776 (eq_attr "mode" "V4SF,V2DF,TI"))
3e2ae3ee
VK		 777 (ior (eq_attr "cpu" "znver2")
778 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 779 (and (eq_attr "prefix" "vex")
780 (and (eq_attr "prefix_extra" "0")
781 (and (eq_attr "type" "ssecomi")
782 (eq_attr "memory" "load")))))
9ce29eb0
VK		 783 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
784
785(define_insn_reservation "znver1_sse_test" 1
e1eb82f5
JH		 786 (and (ior (and (eq_attr "cpu" "znver1")
787 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 788 (ior (eq_attr "cpu" "znver2")
789 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 790 (and (eq_attr "prefix_extra" "1")
791 (and (eq_attr "type" "ssecomi")
792 (eq_attr "memory" "none"))))
9ce29eb0
VK		 793 "znver1-direct,znver1-fp1|znver1-fp2")
794
a065dbc9 795(define_insn_reservation "znver1_sse_test_load" 8
e1eb82f5
JH		 796 (and (ior (and (eq_attr "cpu" "znver1")
797 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 798 (ior (eq_attr "cpu" "znver2")
799 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 800 (and (eq_attr "prefix_extra" "1")
801 (and (eq_attr "type" "ssecomi")
802 (eq_attr "memory" "load"))))
9ce29eb0
VK		 803 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
804
805;; SSE moves
806;; Fix me: Need to revist this again some of the moves may be restricted
807;; to some fpu pipes.
808(define_insn_reservation "znver1_sse_mov" 2
809 (and (eq_attr "cpu" "znver1")
810 (and (eq_attr "mode" "SI")
811 (and (eq_attr "isa" "avx")
812 (and (eq_attr "type" "ssemov")
813 (eq_attr "memory" "none")))))
814 "znver1-direct,znver1-ieu0")
815
e1eb82f5 816(define_insn_reservation "znver2_sse_mov" 1
3e2ae3ee 817 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 818 (and (eq_attr "mode" "SI")
819 (and (eq_attr "isa" "avx")
820 (and (eq_attr "type" "ssemov")
821 (eq_attr "memory" "none")))))
822 "znver1-direct,znver1-ieu0")
823
9ce29eb0
VK		 824(define_insn_reservation "znver1_avx_mov" 2
825 (and (eq_attr "cpu" "znver1")
826 (and (eq_attr "mode" "TI")
827 (and (eq_attr "isa" "avx")
828 (and (eq_attr "type" "ssemov")
829 (and (match_operand:SI 1 "register_operand")
830 (eq_attr "memory" "none"))))))
831 "znver1-direct,znver1-ieu2")
832
e1eb82f5 833(define_insn_reservation "znver2_avx_mov" 1
3e2ae3ee 834 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 835 (and (eq_attr "mode" "TI")
836 (and (eq_attr "isa" "avx")
837 (and (eq_attr "type" "ssemov")
838 (and (match_operand:SI 1 "register_operand")
839 (eq_attr "memory" "none"))))))
840 "znver1-direct,znver1-ieu2")
841
9ce29eb0 842(define_insn_reservation "znver1_sseavx_mov" 1
e1eb82f5
JH		 843 (and (ior (and (eq_attr "cpu" "znver1")
844 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 845 (ior (eq_attr "cpu" "znver2")
846 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 847 (and (eq_attr "type" "ssemov")
848 (eq_attr "memory" "none")))
9ce29eb0
VK		 849 "znver1-direct,znver1-fpu")
850
851(define_insn_reservation "znver1_sseavx_mov_store" 1
852 (and (eq_attr "cpu" "znver1")
853 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
854 (and (eq_attr "type" "ssemov")
855 (eq_attr "memory" "store"))))
856 "znver1-direct,znver1-fpu,znver1-store")
e1eb82f5 857(define_insn_reservation "znver2_sseavx_mov_store" 1
3e2ae3ee 858 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 859 (and (eq_attr "type" "ssemov")
860 (eq_attr "memory" "store")))
861 "znver1-direct,znver1-fpu,znver2-store")
9ce29eb0 862
a065dbc9 863(define_insn_reservation "znver1_sseavx_mov_load" 8
e1eb82f5
JH		 864 (and (ior (and (eq_attr "cpu" "znver1")
865 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 866 (ior (eq_attr "cpu" "znver2")
867 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 868 (and (eq_attr "type" "ssemov")
869 (eq_attr "memory" "load")))
9ce29eb0
VK		 870 "znver1-direct,znver1-load,znver1-fpu")
871
872(define_insn_reservation "znver1_avx256_mov" 1
873 (and (eq_attr "cpu" "znver1")
874 (and (eq_attr "mode" "V8SF,V4DF,OI")
875 (and (eq_attr "type" "ssemov")
876 (eq_attr "memory" "none"))))
877 "znver1-double,znver1-fpu")
878
879(define_insn_reservation "znver1_avx256_mov_store" 1
880 (and (eq_attr "cpu" "znver1")
881 (and (eq_attr "mode" "V8SF,V4DF,OI")
882 (and (eq_attr "type" "ssemov")
883 (eq_attr "memory" "store"))))
884 "znver1-double,znver1-fpu,znver1-store")
885
a065dbc9 886(define_insn_reservation "znver1_avx256_mov_load" 8
9ce29eb0
VK		 887 (and (eq_attr "cpu" "znver1")
888 (and (eq_attr "mode" "V8SF,V4DF,OI")
889 (and (eq_attr "type" "ssemov")
890 (eq_attr "memory" "load"))))
891 "znver1-double,znver1-load,znver1-fpu")
892
893;; SSE add
894(define_insn_reservation "znver1_sseavx_add" 3
e1eb82f5
JH		 895 (and (ior (and (eq_attr "cpu" "znver1")
896 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 897 (ior (eq_attr "cpu" "znver2")
898 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 899 (and (eq_attr "type" "sseadd")
900 (eq_attr "memory" "none")))
9ce29eb0
VK		 901 "znver1-direct,znver1-fp2|znver1-fp3")
902
a065dbc9 903(define_insn_reservation "znver1_sseavx_add_load" 10
e1eb82f5
JH		 904 (and (ior (and (eq_attr "cpu" "znver1")
905 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
3e2ae3ee
VK		 906 (ior (eq_attr "cpu" "znver2")
907 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 908 (and (eq_attr "type" "sseadd")
909 (eq_attr "memory" "load")))
9ce29eb0
VK		 910 "znver1-direct,znver1-load,znver1-fp2|znver1-fp3")
911
912(define_insn_reservation "znver1_avx256_add" 3
913 (and (eq_attr "cpu" "znver1")
914 (and (eq_attr "mode" "V8SF,V4DF,OI")
915 (and (eq_attr "type" "sseadd")
916 (eq_attr "memory" "none"))))
917 "znver1-double,znver1-fp2|znver1-fp3")
918
a065dbc9 919(define_insn_reservation "znver1_avx256_add_load" 10
9ce29eb0
VK		 920 (and (eq_attr "cpu" "znver1")
921 (and (eq_attr "mode" "V8SF,V4DF,OI")
922 (and (eq_attr "type" "sseadd")
923 (eq_attr "memory" "load"))))
924 "znver1-double,znver1-load,znver1-fp2|znver1-fp3")
925
926(define_insn_reservation "znver1_sseavx_fma" 5
e1eb82f5
JH		 927 (and (ior (and (eq_attr "cpu" "znver1")
928 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
929 (eq_attr "cpu" "znver2"))
930 (and (eq_attr "type" "ssemuladd")
931 (eq_attr "memory" "none")))
cdc647c3 932 "znver1-direct,znver1-fp0|znver1-fp1")
9ce29eb0 933
a065dbc9 934(define_insn_reservation "znver1_sseavx_fma_load" 12
e1eb82f5
JH		 935 (and (ior (and (eq_attr "cpu" "znver1")
936 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
937 (eq_attr "cpu" "znver2"))
938 (and (eq_attr "type" "ssemuladd")
939 (eq_attr "memory" "load")))
cdc647c3 940 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
9ce29eb0
VK		 941
942(define_insn_reservation "znver1_avx256_fma" 5
943 (and (eq_attr "cpu" "znver1")
944 (and (eq_attr "mode" "V8SF,V4DF")
945 (and (eq_attr "type" "ssemuladd")
946 (eq_attr "memory" "none"))))
cdc647c3 947 "znver1-double,znver1-fp0|znver1-fp1")
9ce29eb0 948
a065dbc9 949(define_insn_reservation "znver1_avx256_fma_load" 12
9ce29eb0
VK		 950 (and (eq_attr "cpu" "znver1")
951 (and (eq_attr "mode" "V8SF,V4DF")
952 (and (eq_attr "type" "ssemuladd")
953 (eq_attr "memory" "load"))))
cdc647c3 954 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
9ce29eb0 955
3e2ae3ee
VK		 956(define_insn_reservation "znver3_sseavx_fma" 4
957 (and (and (eq_attr "cpu" "znver3")
958 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
959 (and (eq_attr "type" "ssemuladd")
960 (eq_attr "memory" "none")))
961 "znver1-direct,znver1-fp0|znver1-fp1")
962
963(define_insn_reservation "znver3_sseavx_fma_load" 11
964 (and (and (eq_attr "cpu" "znver3")
965 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
966 (and (eq_attr "type" "ssemuladd")
967 (eq_attr "memory" "load")))
968 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
969
970(define_insn_reservation "znver3_avx256_fma" 4
971 (and (eq_attr "cpu" "znver3")
972 (and (eq_attr "mode" "V8SF,V4DF")
973 (and (eq_attr "type" "ssemuladd")
974 (eq_attr "memory" "none"))))
975 "znver1-double,znver1-fp0|znver1-fp1")
976
977(define_insn_reservation "znver3_avx256_fma_load" 11
978 (and (eq_attr "cpu" "znver3")
979 (and (eq_attr "mode" "V8SF,V4DF")
980 (and (eq_attr "type" "ssemuladd")
981 (eq_attr "memory" "load"))))
982 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
983
9ce29eb0 984(define_insn_reservation "znver1_sseavx_iadd" 1
e1eb82f5
JH		 985 (and (ior (and (eq_attr "cpu" "znver1")
986 (eq_attr "mode" "DI,TI"))
3e2ae3ee
VK		 987 (ior (eq_attr "cpu" "znver2")
988 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 989 (and (eq_attr "type" "sseiadd")
990 (eq_attr "memory" "none")))
9ce29eb0
VK		 991 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
992
a065dbc9 993(define_insn_reservation "znver1_sseavx_iadd_load" 8
e1eb82f5
JH		 994 (and (ior (and (eq_attr "cpu" "znver1")
995 (eq_attr "mode" "DI,TI"))
3e2ae3ee
VK		 996 (ior (eq_attr "cpu" "znver2")
997 (eq_attr "cpu" "znver3")))
e1eb82f5
JH		 998 (and (eq_attr "type" "sseiadd")
999 (eq_attr "memory" "load")))
9ce29eb0
VK		 1000 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
1001
1002(define_insn_reservation "znver1_avx256_iadd" 1
1003 (and (eq_attr "cpu" "znver1")
1004 (and (eq_attr "mode" "OI")
1005 (and (eq_attr "type" "sseiadd")
1006 (eq_attr "memory" "none"))))
1007 "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3")
1008
a065dbc9 1009(define_insn_reservation "znver1_avx256_iadd_load" 8
9ce29eb0
VK		 1010 (and (eq_attr "cpu" "znver1")
1011 (and (eq_attr "mode" "OI")
1012 (and (eq_attr "type" "sseiadd")
1013 (eq_attr "memory" "load"))))
1014 "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
1015
1016;; SSE conversions.
a065dbc9 1017(define_insn_reservation "znver1_ssecvtsf_si_load" 12
3e2ae3ee 1018 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 1019 (and (eq_attr "mode" "SI")
1020 (and (eq_attr "type" "sseicvt")
1021 (and (match_operand:SF 1 "memory_operand")
1022 (eq_attr "memory" "load")))))
1023 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
1024
1025(define_insn_reservation "znver1_ssecvtdf_si" 5
1026 (and (eq_attr "cpu" "znver1")
1027 (and (eq_attr "mode" "SI")
1028 (and (match_operand:DF 1 "register_operand")
1029 (and (eq_attr "type" "sseicvt")
1030 (eq_attr "memory" "none")))))
1031 "znver1-double,znver1-fp3,znver1-ieu0")
e1eb82f5 1032(define_insn_reservation "znver2_ssecvtdf_si" 4
3e2ae3ee 1033 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 1034 (and (eq_attr "mode" "SI")
1035 (and (match_operand:DF 1 "register_operand")
1036 (and (eq_attr "type" "sseicvt")
1037 (eq_attr "memory" "none")))))
1038 "znver1-double,znver1-fp3,znver1-ieu0")
9ce29eb0 1039
a065dbc9 1040(define_insn_reservation "znver1_ssecvtdf_si_load" 12
9ce29eb0
VK		 1041 (and (eq_attr "cpu" "znver1")
1042 (and (eq_attr "mode" "SI")
1043 (and (eq_attr "type" "sseicvt")
1044 (and (match_operand:DF 1 "memory_operand")
1045 (eq_attr "memory" "load")))))
1046 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
1047
e1eb82f5 1048(define_insn_reservation "znver2_ssecvtdf_si_load" 11
3e2ae3ee 1049 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 1050 (and (eq_attr "mode" "SI")
1051 (and (eq_attr "type" "sseicvt")
1052 (and (match_operand:DF 1 "memory_operand")
1053 (eq_attr "memory" "load")))))
1054 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
1055
3e2ae3ee 1056
9ce29eb0
VK		 1057;; All other used ssecvt fp3 pipes
1058;; Check: Need to revisit this again.
1059;; Some SSE converts may use different pipe combinations.
1060(define_insn_reservation "znver1_ssecvt" 4
1061 (and (eq_attr "cpu" "znver1")
1062 (and (eq_attr "type" "ssecvt")
1063 (eq_attr "memory" "none")))
1064 "znver1-direct,znver1-fp3")
1065
e1eb82f5 1066(define_insn_reservation "znver2_ssecvt" 3
3e2ae3ee 1067 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 1068 (and (eq_attr "type" "ssecvt")
1069 (eq_attr "memory" "none")))
1070 "znver1-direct,znver1-fp3")
1071
a065dbc9 1072(define_insn_reservation "znver1_ssecvt_load" 11
3e2ae3ee 1073 (and (eq_attr "cpu" "znver1,znver2,znver3")
e1eb82f5
JH		 1074 (and (eq_attr "type" "ssecvt")
1075 (eq_attr "memory" "load")))
1076 "znver1-direct,znver1-load,znver1-fp3")
1077
9ce29eb0
VK		 1078;; SSE div
1079(define_insn_reservation "znver1_ssediv_ss_ps" 10
e1eb82f5
JH		 1080 (and (ior (and (eq_attr "cpu" "znver1")
1081 (eq_attr "mode" "V4SF,SF"))
1082 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1083 (eq_attr "mode" "V8SF,V4SF,SF"))
1084 (and (eq_attr "cpu" "znver3")
1085 (eq_attr "mode" "V8SF,V4SF,SF")))
e1eb82f5
JH		 1086 (and (eq_attr "type" "ssediv")
1087 (eq_attr "memory" "none")))
9ce29eb0
VK		 1088 "znver1-direct,znver1-fp3*10")
1089
a065dbc9 1090(define_insn_reservation "znver1_ssediv_ss_ps_load" 17
e1eb82f5
JH		 1091 (and (ior (and (eq_attr "cpu" "znver1")
1092 (eq_attr "mode" "V4SF,SF"))
1093 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1094 (eq_attr "mode" "V8SF,V4SF,SF"))
1095 (and (eq_attr "cpu" "znver3")
1096 (eq_attr "mode" "V8SF,V4SF,SF")))
e1eb82f5
JH		 1097 (and (eq_attr "type" "ssediv")
1098 (eq_attr "memory" "load")))
9ce29eb0
VK		 1099 "znver1-direct,znver1-load,znver1-fp3*10")
1100
1101(define_insn_reservation "znver1_ssediv_sd_pd" 13
e1eb82f5
JH		 1102 (and (ior (and (eq_attr "cpu" "znver1")
1103 (eq_attr "mode" "V2DF,DF"))
1104 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1105 (eq_attr "mode" "V4DF,V2DF,DF"))
1106 (and (eq_attr "cpu" "znver3")
1107 (eq_attr "mode" "V4DF,V2DF,DF")))
e1eb82f5
JH		 1108 (and (eq_attr "type" "ssediv")
1109 (eq_attr "memory" "none")))
9ce29eb0
VK		 1110 "znver1-direct,znver1-fp3*13")
1111
a065dbc9 1112(define_insn_reservation "znver1_ssediv_sd_pd_load" 20
e1eb82f5 1113 (and (ior (and (eq_attr "cpu" "znver1")
3e2ae3ee 1114 (eq_attr "mode" "V2DF,DF"))
e1eb82f5 1115 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1116 (eq_attr "mode" "V4DF,V2DF,DF"))
1117 (and (eq_attr "cpu" "znver3")
1118 (eq_attr "mode" "V4DF,V2DF,DF")))
e1eb82f5
JH		 1119 (and (eq_attr "type" "ssediv")
1120 (eq_attr "memory" "load")))
9ce29eb0
VK		 1121 "znver1-direct,znver1-load,znver1-fp3*13")
1122
1123(define_insn_reservation "znver1_ssediv_avx256_ps" 12
1124 (and (eq_attr "cpu" "znver1")
1125 (and (eq_attr "mode" "V8SF")
1126 (and (eq_attr "memory" "none")
1127 (eq_attr "type" "ssediv"))))
1128 "znver1-double,znver1-fp3*12")
1129
a065dbc9 1130(define_insn_reservation "znver1_ssediv_avx256_ps_load" 19
9ce29eb0
VK		 1131 (and (eq_attr "cpu" "znver1")
1132 (and (eq_attr "mode" "V8SF")
1133 (and (eq_attr "type" "ssediv")
1134 (eq_attr "memory" "load"))))
1135 "znver1-double,znver1-load,znver1-fp3*12")
1136
1137(define_insn_reservation "znver1_ssediv_avx256_pd" 15
1138 (and (eq_attr "cpu" "znver1")
1139 (and (eq_attr "mode" "V4DF")
1140 (and (eq_attr "type" "ssediv")
1141 (eq_attr "memory" "none"))))
1142 "znver1-double,znver1-fp3*15")
1143
a065dbc9 1144(define_insn_reservation "znver1_ssediv_avx256_pd_load" 22
9ce29eb0
VK		 1145 (and (eq_attr "cpu" "znver1")
1146 (and (eq_attr "mode" "V4DF")
1147 (and (eq_attr "type" "ssediv")
1148 (eq_attr "memory" "load"))))
1149 "znver1-double,znver1-load,znver1-fp3*15")
1150;; SSE MUL
1151(define_insn_reservation "znver1_ssemul_ss_ps" 3
e1eb82f5
JH		 1152 (and (ior (and (eq_attr "cpu" "znver1")
1153 (eq_attr "mode" "V4SF,SF"))
1154 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1155 (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF"))
1156 (and (eq_attr "cpu" "znver3")
1157 (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF")))
e1eb82f5
JH		 1158 (and (eq_attr "type" "ssemul")
1159 (eq_attr "memory" "none")))
9ce29eb0
VK		 1160 "znver1-direct,(znver1-fp0|znver1-fp1)*3")
1161
a065dbc9 1162(define_insn_reservation "znver1_ssemul_ss_ps_load" 10
e1eb82f5
JH		 1163 (and (ior (and (eq_attr "cpu" "znver1")
1164 (eq_attr "mode" "V4SF,SF"))
1165 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1166 (eq_attr "mode" "V8SF,V4SF,SF"))
1167 (and (eq_attr "cpu" "znver3")
1168 (eq_attr "mode" "V8SF,V4SF,SF")))
e1eb82f5
JH		 1169 (and (eq_attr "type" "ssemul")
1170 (eq_attr "memory" "load")))
9ce29eb0
VK		 1171 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
1172
1173(define_insn_reservation "znver1_ssemul_avx256_ps" 3
1174 (and (eq_attr "cpu" "znver1")
1175 (and (eq_attr "mode" "V8SF")
1176 (and (eq_attr "type" "ssemul")
1177 (eq_attr "memory" "none"))))
1178 "znver1-double,(znver1-fp0|znver1-fp1)*3")
1179
a065dbc9 1180(define_insn_reservation "znver1_ssemul_avx256_ps_load" 10
9ce29eb0
VK		 1181 (and (eq_attr "cpu" "znver1")
1182 (and (eq_attr "mode" "V8SF")
1183 (and (eq_attr "type" "ssemul")
1184 (eq_attr "memory" "load"))))
1185 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3")
1186
1187(define_insn_reservation "znver1_ssemul_sd_pd" 4
1188 (and (eq_attr "cpu" "znver1")
1189 (and (eq_attr "mode" "V2DF,DF")
1190 (and (eq_attr "type" "ssemul")
1191 (eq_attr "memory" "none"))))
1192 "znver1-direct,(znver1-fp0|znver1-fp1)*4")
1193
a065dbc9 1194(define_insn_reservation "znver1_ssemul_sd_pd_load" 11
9ce29eb0
VK		 1195 (and (eq_attr "cpu" "znver1")
1196 (and (eq_attr "mode" "V2DF,DF")
1197 (and (eq_attr "type" "ssemul")
1198 (eq_attr "memory" "load"))))
1199 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4")
1200
e1eb82f5 1201(define_insn_reservation "znver2_ssemul_sd_pd" 3
3e2ae3ee 1202 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 1203 (and (eq_attr "type" "ssemul")
1204 (eq_attr "memory" "none")))
1205 "znver1-direct,(znver1-fp0|znver1-fp1)*3")
1206
1207(define_insn_reservation "znver2_ssemul_sd_pd_load" 10
3e2ae3ee 1208 (and (eq_attr "cpu" "znver2,znver3")
e1eb82f5
JH		 1209 (and (eq_attr "type" "ssemul")
1210 (eq_attr "memory" "load")))
1211 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
1212
3e2ae3ee 1213
9ce29eb0
VK		 1214(define_insn_reservation "znver1_ssemul_avx256_pd" 5
1215 (and (eq_attr "cpu" "znver1")
1216 (and (eq_attr "mode" "V4DF")
e1eb82f5
JH		 1217 (and (eq_attr "type" "ssemul")
1218 (eq_attr "memory" "none"))))
9ce29eb0
VK		 1219 "znver1-double,(znver1-fp0|znver1-fp1)*4")
1220
a065dbc9 1221(define_insn_reservation "znver1_ssemul_avx256_pd_load" 12
9ce29eb0
VK		 1222 (and (eq_attr "cpu" "znver1")
1223 (and (eq_attr "mode" "V4DF")
1224 (and (eq_attr "type" "ssemul")
1225 (eq_attr "memory" "load"))))
1226 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4")
1227
1228;;SSE imul
1229(define_insn_reservation "znver1_sseimul" 3
e1eb82f5
JH		 1230 (and (ior (and (eq_attr "cpu" "znver1")
1231 (eq_attr "mode" "TI"))
1232 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1233 (eq_attr "mode" "TI,OI"))
1234 (and (eq_attr "cpu" "znver3")
1235 (eq_attr "mode" "TI,OI")))
e1eb82f5
JH		 1236 (and (eq_attr "type" "sseimul")
1237 (eq_attr "memory" "none")))
9ce29eb0
VK		 1238 "znver1-direct,znver1-fp0*3")
1239
1240(define_insn_reservation "znver1_sseimul_avx256" 4
3e2ae3ee 1241 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0 1242 (and (eq_attr "mode" "OI")
bdf2429b 1243 (and (eq_attr "type" "sseimul")
9ce29eb0
VK		 1244 (eq_attr "memory" "none"))))
1245 "znver1-double,znver1-fp0*4")
1246
a065dbc9 1247(define_insn_reservation "znver1_sseimul_load" 10
e1eb82f5
JH		 1248 (and (ior (and (eq_attr "cpu" "znver1")
1249 (eq_attr "mode" "TI"))
1250 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1251 (eq_attr "mode" "TI,OI"))
1252 (and (eq_attr "cpu" "znver3")
e1eb82f5
JH		 1253 (eq_attr "mode" "TI,OI")))
1254 (and (eq_attr "type" "sseimul")
1255 (eq_attr "memory" "load")))
9ce29eb0
VK		 1256 "znver1-direct,znver1-load,znver1-fp0*3")
1257
a065dbc9 1258(define_insn_reservation "znver1_sseimul_avx256_load" 11
3e2ae3ee 1259 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0 1260 (and (eq_attr "mode" "OI")
bdf2429b 1261 (and (eq_attr "type" "sseimul")
9ce29eb0
VK		 1262 (eq_attr "memory" "load"))))
1263 "znver1-double,znver1-load,znver1-fp0*4")
1264
bdf2429b 1265(define_insn_reservation "znver1_sseimul_di" 3
3e2ae3ee 1266 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0
VK		 1267 (and (eq_attr "mode" "DI")
1268 (and (eq_attr "memory" "none")
bdf2429b
VK		 1269 (eq_attr "type" "sseimul"))))
1270 "znver1-direct,znver1-fp0*3")
9ce29eb0 1271
a065dbc9 1272(define_insn_reservation "znver1_sseimul_load_di" 10
3e2ae3ee 1273 (and (eq_attr "cpu" "znver1,znver2,znver3")
9ce29eb0 1274 (and (eq_attr "mode" "DI")
bdf2429b 1275 (and (eq_attr "type" "sseimul")
9ce29eb0 1276 (eq_attr "memory" "load"))))
bdf2429b 1277 "znver1-direct,znver1-load,znver1-fp0*3")
9ce29eb0
VK		 1278
1279;; SSE compares
1280(define_insn_reservation "znver1_sse_cmp" 1
e1eb82f5
JH		 1281 (and (ior (and (eq_attr "cpu" "znver1")
1282 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
1283 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1284 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))
1285 (and (eq_attr "cpu" "znver3")
1286 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
e1eb82f5
JH		 1287 (and (eq_attr "type" "ssecmp")
1288 (eq_attr "memory" "none")))
9ce29eb0
VK		 1289 "znver1-direct,znver1-fp0|znver1-fp1")
1290
a065dbc9 1291(define_insn_reservation "znver1_sse_cmp_load" 8
e1eb82f5 1292 (and (ior (and (eq_attr "cpu" "znver1")
3e2ae3ee 1293 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
e1eb82f5 1294 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1295 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))
1296 (and (eq_attr "cpu" "znver3")
1297 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
e1eb82f5
JH		 1298 (and (eq_attr "type" "ssecmp")
1299 (eq_attr "memory" "load")))
9ce29eb0
VK		 1300 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
1301
1302(define_insn_reservation "znver1_sse_cmp_avx256" 1
1303 (and (eq_attr "cpu" "znver1")
1304 (and (eq_attr "mode" "V8SF,V4DF")
1305 (and (eq_attr "type" "ssecmp")
1306 (eq_attr "memory" "none"))))
1307 "znver1-double,znver1-fp0|znver1-fp1")
1308
a065dbc9 1309(define_insn_reservation "znver1_sse_cmp_avx256_load" 8
9ce29eb0
VK		 1310 (and (eq_attr "cpu" "znver1")
1311 (and (eq_attr "mode" "V8SF,V4DF")
1312 (and (eq_attr "type" "ssecmp")
1313 (eq_attr "memory" "load"))))
1314 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
1315
1316(define_insn_reservation "znver1_sse_icmp" 1
e1eb82f5 1317 (and (ior (and (eq_attr "cpu" "znver1")
3e2ae3ee 1318 (eq_attr "mode" "QI,HI,SI,DI,TI"))
e1eb82f5 1319 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1320 (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))
1321 (and (eq_attr "cpu" "znver3")
1322 (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
e1eb82f5
JH		 1323 (and (eq_attr "type" "ssecmp")
1324 (eq_attr "memory" "none")))
9ce29eb0
VK		 1325 "znver1-direct,znver1-fp0|znver1-fp3")
1326
a065dbc9 1327(define_insn_reservation "znver1_sse_icmp_load" 8
e1eb82f5
JH		 1328 (and (ior (and (eq_attr "cpu" "znver1")
1329 (eq_attr "mode" "QI,HI,SI,DI,TI"))
1330 (and (eq_attr "cpu" "znver2")
3e2ae3ee
VK		 1331 (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))
1332 (and (eq_attr "cpu" "znver3")
1333 (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
e1eb82f5
JH		 1334 (and (eq_attr "type" "ssecmp")
1335 (eq_attr "memory" "load")))
9ce29eb0
VK		 1336 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
1337
1338(define_insn_reservation "znver1_sse_icmp_avx256" 1
1339 (and (eq_attr "cpu" "znver1")
1340 (and (eq_attr "mode" "OI")
1341 (and (eq_attr "type" "ssecmp")
1342 (eq_attr "memory" "none"))))
1343 "znver1-double,znver1-fp0|znver1-fp3")
1344
a065dbc9 1345(define_insn_reservation "znver1_sse_icmp_avx256_load" 8
9ce29eb0
VK		 1346 (and (eq_attr "cpu" "znver1")
1347 (and (eq_attr "mode" "OI")
1348 (and (eq_attr "type" "ssecmp")
1349 (eq_attr "memory" "load"))))
1350 "znver1-double,znver1-load,znver1-fp0|znver1-fp3")
Mirror of https://gcc.gnu.org/git/gcc.git