]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/m32c/m32c.md
Update copyright years.
[thirdparty/gcc.git] / gcc / config / m32c / m32c.md
CommitLineData
38b2d076 1;; Machine Descriptions for R8C/M16C/M32C
a5544970 2;; Copyright (C) 2005-2019 Free Software Foundation, Inc.
38b2d076
DD
3;; Contributed by Red Hat.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
2f83c7d6 9;; by the Free Software Foundation; either version 3, or (at your
38b2d076
DD
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
2f83c7d6
NC
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
38b2d076
DD
20
21(define_constants
22 [(R0_REGNO 0)
23 (R2_REGNO 1)
24 (R1_REGNO 2)
25 (R3_REGNO 3)
26
27 (A0_REGNO 4)
28 (A1_REGNO 5)
29 (SB_REGNO 6)
30 (FB_REGNO 7)
31
32 (SP_REGNO 8)
33 (PC_REGNO 9)
34 (FLG_REGNO 10)
35 (MEM0_REGNO 12)
36 (MEM7_REGNO 19)
37 ])
38
39(define_constants
40 [(UNS_PROLOGUE_END 1)
41 (UNS_EPILOGUE_START 2)
42 (UNS_EH_EPILOGUE 3)
43 (UNS_PUSHM 4)
44 (UNS_POPM 5)
07127a0a
DD
45 (UNS_SMOVF 6)
46 (UNS_SSTR 7)
47 (UNS_SCMPU 8)
48 (UNS_SMOVU 9)
65655f79
DD
49 (UNS_FSETB 10)
50 (UNS_FREIT 11)
38b2d076
DD
51 ])
52
07127a0a
DD
53;; n = no change, x = clobbered. The first 16 values are chosen such
54;; that the enum has one bit set for each flag.
55(define_attr "flags" "x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n" (const_string "n"))
56(define_asm_attributes [(set_attr "flags" "x")])
57
3abcb3a7
HPN
58(define_mode_iterator QHI [QI HI])
59(define_mode_iterator HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
60(define_mode_iterator QHPSI [QI HI (PSI "TARGET_A24")])
61(define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
07127a0a
DD
62(define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
63
3abcb3a7 64(define_code_iterator eqne_cond [eq ne])
07127a0a
DD
65
66
38b2d076
DD
67(define_insn "nop"
68 [(const_int 0)]
69 ""
16659fcf
DD
70 "nop"
71 [(set_attr "flags" "n")]
72)
38b2d076 73
07127a0a
DD
74(define_insn "no_insn"
75 [(const_int 1)]
76 ""
16659fcf
DD
77 ""
78 [(set_attr "flags" "n")]
79)