[thirdparty/gcc.git] / gcc / config / m32c / muldiv.md

;; Machine Descriptions for R8C/M16C/M32C
;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
;; Contributed by Red Hat.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; multiply and divide

; Here is the pattern for the const_int.
(define_insn "mulqihi3_c"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
                 (match_operand 2 "immediate_operand" "i,i")))]
  ""
  "mul.b\t%2,%1"
  [(set_attr "flags" "o")]
)

; Here is the pattern for registers and such.
(define_insn "mulqihi3_r"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
                 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
  ""
  "mul.b\t%2,%1"
  [(set_attr "flags" "o")]
)

; Don't try to sign_extend a const_int.  Same for all other multiplies.
(define_expand "mulqihi3"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
  ""
  "{ if (GET_MODE (operands[2]) != VOIDmode)
      operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
)

(define_insn "umulqihi3_c"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
                 (match_operand 2 "immediate_operand" "i,i")))]
  ""
  "mulu.b\t%U2,%1"
  [(set_attr "flags" "o")]
)

(define_insn "umulqihi3_r"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
                 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
  ""
  "mulu.b\t%U2,%1"
  [(set_attr "flags" "o")]
)

(define_expand "umulqihi3"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
  ""
  "{ if (GET_MODE (operands[2]) != VOIDmode)
      operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
)

(define_insn "mulhisi3_c"
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
                 (match_operand:HI 2 "immediate_operand" "i")))]
  ""
  "mul.w\t%2,%1"
  [(set_attr "flags" "o")]
)

(define_insn "mulhisi3_r"
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
                 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
  ""
  "mul.w\t%2,%1"
  [(set_attr "flags" "o")]
)

(define_expand "mulhisi3"
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
  ""
  "{ if (GET_MODE (operands[2]) != VOIDmode)
      operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
)

(define_insn "umulhisi3_c"
  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
                 (match_operand 2 "immediate_operand" "i")))]
  ""
  "mulu.w\t%u2,%1"
  [(set_attr "flags" "o")]
)

(define_insn "umulhisi3_r"
  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
  ""
  "mulu.w\t%u2,%1"
  [(set_attr "flags" "o")]
)

(define_expand "umulhisi3"
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
  ""
  "{ if (GET_MODE (operands[2]) != VOIDmode)
      operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
)


; GCC expects to be able to multiply pointer-sized integers too, but
; fortunately it only multiplies by powers of two, although sometimes
; they're negative.
(define_insn "mulpsi3_op"
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
		  (match_operand 2 "m32c_psi_scale" "Ilb")))]
  "TARGET_A24"
  "shl.l\t%b2,%0"
  [(set_attr "flags" "szc")]
  )

(define_expand "mulpsi3"
  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
		  (match_operand 2 "m32c_psi_scale" "Ilb")))]
  "TARGET_A24"
  "if (GET_CODE (operands[2]) != CONST_INT
       || ! m32c_psi_scale (operands[2], PSImode))
     {
       m32c_expand_neg_mulpsi3 (operands);
       DONE;
     }"
  )

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
        (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
  "TARGET_M32C"
  "mul.l\t%2,%1"
  [(set_attr "flags" "o")]
)

(define_expand "divmodqi4"
  [(set (match_dup 4)
	(sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
		   (div:QI (match_dup 4)
			   (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	      (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
		   (mod:QI (match_dup 4) (match_dup 2)))
	      ])]
  "0"
  "operands[4] = gen_reg_rtx (HImode);"
  )

(define_insn "divmodqi4_n"
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
	(div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
		(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
	(mod:QI (match_dup 1) (match_dup 2)))
   ]
  "0"
  "div.b\t%2"
  [(set_attr "flags" "o")]
  )

(define_expand "udivmodqi4"
  [(set (match_dup 4)
	(zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
   (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
		   (udiv:QI (match_dup 4)
			   (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	      (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
		   (umod:QI (match_dup 4) (match_dup 2)))
	      ])]
  "0"
  "operands[4] = gen_reg_rtx (HImode);"
  )

(define_insn "udivmodqi4_n"
  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
	(udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
		(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
	(umod:QI (match_dup 1) (match_dup 2)))
   ]
  "0"
  "divu.b\t%2"
  [(set_attr "flags" "o")]
  )

(define_expand "divmodhi4"
  [(set (match_dup 4)
	(sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
		   (div:HI (match_dup 4)
			   (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
	      (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
		   (mod:HI (match_dup 4) (match_dup 2)))
	      ])]
  ""
  "operands[4] = gen_reg_rtx (SImode);"
  )

(define_insn "divmodhi4_n"
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
	(div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
		(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
	(mod:HI (match_dup 1) (match_dup 2)))
   ]
  ""
  "div.w\t%2"
  [(set_attr "flags" "o")]
  )

(define_expand "udivmodhi4"
  [(set (match_dup 4)
	(zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
		   (udiv:HI (match_dup 4)
			   (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
	      (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
		   (umod:HI (match_dup 4) (match_dup 2)))
	      ])]
  ""
  "operands[4] = gen_reg_rtx (SImode);"
  )

(define_insn "udivmodhi4_n"
  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
	(udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
		(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
	(umod:HI (match_dup 1) (match_dup 2)))
   ]
  ""
  "divu.w\t%2"
  [(set_attr "flags" "o")]
  )

(define_insn "divsi3"
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
        (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
                (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
  "TARGET_M32C"
  "div.l\t%2"
  [(set_attr "flags" "o")]
)

(define_insn "udivsi3"
  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
        (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
  "TARGET_M32C"
  "divu.l\t%2"
  [(set_attr "flags" "o")]
)
Commit	Line	Data
38b2d076	1	;; Machine Descriptions for R8C/M16C/M32C
99dee823	2	;; Copyright (C) 2005-2021 Free Software Foundation, Inc.
38b2d076 DD	3	;; Contributed by Red Hat.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
2f83c7d6	9	;; by the Free Software Foundation; either version 3, or (at your
38b2d076 DD	10	;; option) any later version.
	11	;;
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16	;;
	17	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>.
38b2d076 DD	20
	21	;; multiply and divide
	22
	23	; Here is the pattern for the const_int.
	24	(define_insn "mulqihi3_c"
	25	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
	26	(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
	27	(match_operand 2 "immediate_operand" "i,i")))]
	28	""
	29	"mul.b\t%2,%1"
16659fcf	30	[(set_attr "flags" "o")]
38b2d076 DD	31	)
	32
	33	; Here is the pattern for registers and such.
	34	(define_insn "mulqihi3_r"
	35	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
	36	(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
	37	(sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
	38	""
	39	"mul.b\t%2,%1"
16659fcf	40	[(set_attr "flags" "o")]
38b2d076 DD	41	)
	42
	43	; Don't try to sign_extend a const_int. Same for all other multiplies.
	44	(define_expand "mulqihi3"
	45	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
	46	(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
	47	(match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
	48	""
	49	"{ if (GET_MODE (operands[2]) != VOIDmode)
	50	operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
	51	)
	52
	53	(define_insn "umulqihi3_c"
	54	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
	55	(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
	56	(match_operand 2 "immediate_operand" "i,i")))]
	57	""
	58	"mulu.b\t%U2,%1"
16659fcf	59	[(set_attr "flags" "o")]
38b2d076 DD	60	)
	61
	62	(define_insn "umulqihi3_r"
	63	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
	64	(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
	65	(zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
	66	""
	67	"mulu.b\t%U2,%1"
16659fcf	68	[(set_attr "flags" "o")]
38b2d076 DD	69	)
	70
	71	(define_expand "umulqihi3"
	72	[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
	73	(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
	74	(match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
	75	""
	76	"{ if (GET_MODE (operands[2]) != VOIDmode)
	77	operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
	78	)
	79
	80	(define_insn "mulhisi3_c"
a1ec220c DD	81	[(set (match_operand:SI 0 "ra_operand" "=Rsi")
a1ec220c DD	82	(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
44cfab35	83	(match_operand:HI 2 "immediate_operand" "i")))]
38b2d076 DD	84	""
38b2d076 DD	85	"mul.w\t%2,%1"
16659fcf	86	[(set_attr "flags" "o")]
38b2d076 DD	87	)
	88
	89	(define_insn "mulhisi3_r"
a1ec220c DD	90	[(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
	91	(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
	92	(sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
38b2d076 DD	93	""
38b2d076 DD	94	"mul.w\t%2,%1"
16659fcf	95	[(set_attr "flags" "o")]
38b2d076 DD	96	)
	97
	98	(define_expand "mulhisi3"
	99	[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
	100	(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
	101	(match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
	102	""
	103	"{ if (GET_MODE (operands[2]) != VOIDmode)
	104	operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
	105	)
	106
	107	(define_insn "umulhisi3_c"
8a01e7d9 N	108	[(set (match_operand:SI 0 "ra_operand" "=Rsi")
	109	(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
	110	(match_operand 2 "immediate_operand" "i")))]
38b2d076 DD	111	""
38b2d076 DD	112	"mulu.w\t%u2,%1"
16659fcf	113	[(set_attr "flags" "o")]
38b2d076 DD	114	)
	115
	116	(define_insn "umulhisi3_r"
8a01e7d9 N	117	[(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
	118	(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
	119	(zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
38b2d076 DD	120	""
38b2d076 DD	121	"mulu.w\t%u2,%1"
16659fcf	122	[(set_attr "flags" "o")]
38b2d076 DD	123	)
	124
	125	(define_expand "umulhisi3"
	126	[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
	127	(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
	128	(match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
	129	""
	130	"{ if (GET_MODE (operands[2]) != VOIDmode)
	131	operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
	132	)
	133
	134
	135	; GCC expects to be able to multiply pointer-sized integers too, but
12ea2512 DD	136	; fortunately it only multiplies by powers of two, although sometimes
	137	; they're negative.
	138	(define_insn "mulpsi3_op"
38b2d076 DD	139	[(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
38b2d076 DD	140	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
12ea2512	141	(match_operand 2 "m32c_psi_scale" "Ilb")))]
38b2d076 DD	142	"TARGET_A24"
	143	"shl.l\t%b2,%0"
	144	[(set_attr "flags" "szc")]
	145	)
	146
12ea2512 DD	147	(define_expand "mulpsi3"
	148	[(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
	149	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
	150	(match_operand 2 "m32c_psi_scale" "Ilb")))]
	151	"TARGET_A24"
07127a0a	152	"if (GET_CODE (operands[2]) != CONST_INT
e3d437c0	153	\|\| ! m32c_psi_scale (operands[2], PSImode))
12ea2512 DD	154	{
	155	m32c_expand_neg_mulpsi3 (operands);
	156	DONE;
	157	}"
	158	)
	159
44cfab35 N	160	(define_insn "mulsi3"
	161	[(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
	162	(mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
	163	(match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
	164	"TARGET_M32C"
	165	"mul.l\t%2,%1"
	166	[(set_attr "flags" "o")]
	167	)
38b2d076 DD	168
	169	(define_expand "divmodqi4"
	170	[(set (match_dup 4)
	171	(sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
	172	(parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
	173	(div:QI (match_dup 4)
	174	(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	175	(set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
	176	(mod:QI (match_dup 4) (match_dup 2)))
	177	])]
	178	"0"
	179	"operands[4] = gen_reg_rtx (HImode);"
	180	)
	181
	182	(define_insn "divmodqi4_n"
	183	[(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
	184	(div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
	185	(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	186	(set (match_operand:QI 3 "register_operand" "=R0h,R0h")
	187	(mod:QI (match_dup 1) (match_dup 2)))
	188	]
	189	"0"
	190	"div.b\t%2"
16659fcf	191	[(set_attr "flags" "o")]
38b2d076 DD	192	)
	193
	194	(define_expand "udivmodqi4"
	195	[(set (match_dup 4)
	196	(zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
	197	(parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
	198	(udiv:QI (match_dup 4)
	199	(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	200	(set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
	201	(umod:QI (match_dup 4) (match_dup 2)))
	202	])]
	203	"0"
	204	"operands[4] = gen_reg_rtx (HImode);"
	205	)
	206
	207	(define_insn "udivmodqi4_n"
	208	[(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
	209	(udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
	210	(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
	211	(set (match_operand:QI 3 "register_operand" "=R0h,R0h")
	212	(umod:QI (match_dup 1) (match_dup 2)))
	213	]
	214	"0"
	215	"divu.b\t%2"
16659fcf	216	[(set_attr "flags" "o")]
38b2d076 DD	217	)
	218
	219	(define_expand "divmodhi4"
	220	[(set (match_dup 4)
	221	(sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
	222	(parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
	223	(div:HI (match_dup 4)
	224	(match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
	225	(set (match_operand:HI 3 "register_operand" "=R2w,R2w")
	226	(mod:HI (match_dup 4) (match_dup 2)))
	227	])]
	228	""
	229	"operands[4] = gen_reg_rtx (SImode);"
	230	)
	231
	232	(define_insn "divmodhi4_n"
	233	[(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
	234	(div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
	235	(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
	236	(set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
	237	(mod:HI (match_dup 1) (match_dup 2)))
	238	]
	239	""
	240	"div.w\t%2"
16659fcf	241	[(set_attr "flags" "o")]
38b2d076 DD	242	)
	243
	244	(define_expand "udivmodhi4"
	245	[(set (match_dup 4)
	246	(zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
	247	(parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
	248	(udiv:HI (match_dup 4)
	249	(match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
	250	(set (match_operand:HI 3 "register_operand" "=R2w,R2w")
	251	(umod:HI (match_dup 4) (match_dup 2)))
	252	])]
	253	""
	254	"operands[4] = gen_reg_rtx (SImode);"
	255	)
	256
	257	(define_insn "udivmodhi4_n"
	258	[(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
	259	(udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
	260	(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
	261	(set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
	262	(umod:HI (match_dup 1) (match_dup 2)))
	263	]
	264	""
	265	"divu.w\t%2"
16659fcf	266	[(set_attr "flags" "o")]
38b2d076	267	)
44cfab35 N	268
	269	(define_insn "divsi3"
	270	[(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
	271	(div:SI (match_operand:SI 1 "r0123_operand" "0,0")
	272	(match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
	273	"TARGET_M32C"
	274	"div.l\t%2"
	275	[(set_attr "flags" "o")]
	276	)
	277
	278	(define_insn "udivsi3"
	279	[(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
	280	(udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
	281	(match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
	282	"TARGET_M32C"
	283	"divu.l\t%2"
	284	[(set_attr "flags" "o")]
	285	)
	286
	287