[thirdparty/gcc.git] / gcc / config / m32c / shift.md

;; Machine Descriptions for R8C/M16C/M32C
;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
;; Contributed by Red Hat.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; bit shifting

; Shifts are unusual for m32c.  We only support shifting in one
; "direction" but the shift count is signed.  Also, immediate shift
; counts have a limited range, and variable shift counts have to be in
; $r1h which GCC normally doesn't even know about.

; Other than compensating for the above, the patterns below are pretty
; straightforward.

(define_insn "ashlqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.b\t%2,%0
   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.b\t%2,%0
   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrqi3_i"
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   shl.b\t%2,%0
   mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
	(ashift:QI (match_operand:QI 1 "mra_operand" "")
		   (match_operand:QI 2 "general_operand" "")))
   (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
		     (neg:QI (match_operand:QI 2 "general_operand" ""))))
   (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrqi3"
  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
		   (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

(define_insn "ashlhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
	(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.w\t%2,%0
   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   sha.w\t%2,%0
   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrhi3_i"
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  ""
  "@
   shl.w\t%2,%0
   mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (ashift:HI (match_operand:HI 1 "mra_operand" "")
			      (match_operand:QI 2 "general_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrhi3"
  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
		   (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
				(neg:QI (match_operand:QI 2 "general_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )


; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


(define_insn "ashlpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
	(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		    (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrpsi3_i"
  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_expand "ashlpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
			       (match_operand:QI 2 "shiftcount_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrpsi3"
  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
		   (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  "TARGET_A24"
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

; The m16c has a maximum shift count of -16..16, even when in a
; register.  It's optimal to use multiple shifts of -8..8 rather than
; loading larger constants into R1H multiple time.  The m32c can shift
; -32..32 either via immediates or in registers.  Hence, separate
; patterns.


(define_insn "ashlsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
		   (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "ashrsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  [(set_attr "flags" "oszc,oszc")]
  )

(define_insn "lshrsi3_16"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A16"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  [(set_attr "flags" "szc,szc")]
  )


(define_insn "ashlsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
		   (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  )

(define_insn "ashrsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   sha.l\t%2,%0
   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
  )

(define_insn "lshrsi3_24"
  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
   (clobber (match_scratch:HI 3 "=X,R1w"))]
  "TARGET_A24"
  "@
   shl.l\t%2,%0
   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
  )


(define_expand "ashlsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (ashift:SI (match_operand:SI 1 "r0123_operand" "")
			      (match_operand:QI 2 "mrai_operand" "")))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, 1, ASHIFT))
     DONE;"
  )

(define_expand "ashrsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
     DONE;"
  )

(define_expand "lshrsi3"
  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
		   (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	      (clobber (match_scratch:HI 3 ""))])]
  ""
  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
     DONE;"
  )
Commit	Line	Data
38b2d076	1	;; Machine Descriptions for R8C/M16C/M32C
8d9254fc	2	;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
38b2d076 DD	3	;; Contributed by Red Hat.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
2f83c7d6	9	;; by the Free Software Foundation; either version 3, or (at your
38b2d076 DD	10	;; option) any later version.
	11	;;
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16	;;
	17	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	18	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	19	;; <http://www.gnu.org/licenses/>.
38b2d076 DD	20
	21	;; bit shifting
	22
	23	; Shifts are unusual for m32c. We only support shifting in one
	24	; "direction" but the shift count is signed. Also, immediate shift
	25	; counts have a limited range, and variable shift counts have to be in
	26	; $r1h which GCC normally doesn't even know about.
	27
	28	; Other than compensating for the above, the patterns below are pretty
	29	; straightforward.
	30
	31	(define_insn "ashlqi3_i"
	32	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
	33	(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	34	(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
38b2d076 DD	35	(clobber (match_scratch:HI 3 "=X,R1w"))]
	36	""
	37	"@
	38	sha.b\t%2,%0
23fed240	39	mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
16659fcf	40	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	41	)
	42
	43	(define_insn "ashrqi3_i"
	44	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
	45	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	46	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	47	(clobber (match_scratch:HI 3 "=X,R1w"))]
	48	""
	49	"@
	50	sha.b\t%2,%0
23fed240	51	mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
16659fcf	52	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	53	)
38b2d076 DD	54
23fed240	55	(define_insn "lshrqi3_i"
38b2d076 DD	56	[(set (match_operand:QI 0 "mra_operand" "=RqiSdRmm,RqiSdRmm")
38b2d076 DD	57	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
23fed240	58	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	59	(clobber (match_scratch:HI 3 "=X,R1w"))]
	60	""
	61	"@
	62	shl.b\t%2,%0
23fed240	63	mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
16659fcf	64	[(set_attr "flags" "szc,szc")]
38b2d076 DD	65	)
	66
	67
	68	(define_expand "ashlqi3"
	69	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	70	(ashift:QI (match_operand:QI 1 "mra_operand" "")
	71	(match_operand:QI 2 "general_operand" "")))
	72	(clobber (match_scratch:HI 3 ""))])]
	73	""
23fed240	74	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	75	DONE;"
	76	)
	77
	78	(define_expand "ashrqi3"
	79	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	80	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
	81	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	82	(clobber (match_scratch:HI 3 ""))])]
	83	""
23fed240	84	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	85	DONE;"
	86	)
	87
	88	(define_expand "lshrqi3"
	89	[(parallel [(set (match_operand:QI 0 "mra_operand" "")
	90	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
	91	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	92	(clobber (match_scratch:HI 3 ""))])]
	93	""
23fed240	94	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	95	DONE;"
	96	)
	97
	98	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	99
	100	(define_insn "ashlhi3_i"
	101	[(set (match_operand:HI 0 "mra_operand" "=SdRhiRmm,SdRhiRmm")
	102	(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	103	(match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
38b2d076 DD	104	(clobber (match_scratch:HI 3 "=X,R1w"))]
	105	""
	106	"@
	107	sha.w\t%2,%0
23fed240	108	mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
16659fcf	109	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	110	)
	111
	112	(define_insn "ashrhi3_i"
	113	[(set (match_operand:HI 0 "mra_operand" "=SdRhiRmm,SdRhiRmm")
	114	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	115	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	116	(clobber (match_scratch:HI 3 "=X,R1w"))]
	117	""
	118	"@
	119	sha.w\t%2,%0
23fed240	120	mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
16659fcf	121	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	122	)
38b2d076 DD	123
23fed240	124	(define_insn "lshrhi3_i"
38b2d076 DD	125	[(set (match_operand:HI 0 "mra_operand" "=RhiSdRmm,RhiSdRmm")
38b2d076 DD	126	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
23fed240	127	(neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
38b2d076 DD	128	(clobber (match_scratch:HI 3 "=X,R1w"))]
	129	""
	130	"@
	131	shl.w\t%2,%0
23fed240	132	mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
16659fcf	133	[(set_attr "flags" "szc,szc")]
38b2d076 DD	134	)
	135
	136
	137	(define_expand "ashlhi3"
	138	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	139	(ashift:HI (match_operand:HI 1 "mra_operand" "")
	140	(match_operand:QI 2 "general_operand" "")))
	141	(clobber (match_scratch:HI 3 ""))])]
	142	""
23fed240	143	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	144	DONE;"
	145	)
	146
	147	(define_expand "ashrhi3"
	148	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	149	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
	150	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	151	(clobber (match_scratch:HI 3 ""))])]
	152	""
23fed240	153	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	154	DONE;"
	155	)
	156
	157	(define_expand "lshrhi3"
	158	[(parallel [(set (match_operand:HI 0 "mra_operand" "")
	159	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
	160	(neg:QI (match_operand:QI 2 "general_operand" ""))))
	161	(clobber (match_scratch:HI 3 ""))])]
	162	""
23fed240	163	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	164	DONE;"
	165	)
	166
	167
	168
	169
	170	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	171
	172
	173	(define_insn "ashlpsi3_i"
	174	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSdRmm,R02RaaSdRmm")
	175	(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
3eb5f26f	176	(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
38b2d076 DD	177	(clobber (match_scratch:HI 3 "=X,R1w"))]
	178	"TARGET_A24"
	179	"@
	180	sha.l\t%2,%0
23fed240	181	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	182	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	183	)
	184
	185	(define_insn "ashrpsi3_i"
	186	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSdRmm,R02RaaSdRmm")
	187	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
3eb5f26f	188	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076 DD	189	(clobber (match_scratch:HI 3 "=X,R1w"))]
	190	"TARGET_A24"
	191	"@
	192	sha.l\t%2,%0
23fed240	193	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	194	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	195	)
38b2d076 DD	196
23fed240	197	(define_insn "lshrpsi3_i"
38b2d076 DD	198	[(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
38b2d076 DD	199	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
23fed240	200	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076 DD	201	(clobber (match_scratch:HI 3 "=X,R1w"))]
	202	"TARGET_A24"
	203	"@
	204	shl.l\t%2,%0
23fed240	205	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
16659fcf	206	[(set_attr "flags" "szc,szc")]
38b2d076 DD	207	)
	208
	209
	210	(define_expand "ashlpsi3"
	211	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	212	(ashift:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	213	(match_operand:QI 2 "shiftcount_operand" "")))
38b2d076 DD	214	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	215	"TARGET_A24"
23fed240	216	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	217	DONE;"
	218	)
	219
	220	(define_expand "ashrpsi3"
	221	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	222	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	223	(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
38b2d076 DD	224	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	225	"TARGET_A24"
23fed240	226	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	227	DONE;"
	228	)
	229
	230	(define_expand "lshrpsi3"
	231	[(parallel [(set (match_operand:PSI 0 "mra_operand" "")
	232	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
3eb5f26f	233	(neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
38b2d076 DD	234	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	235	"TARGET_A24"
23fed240	236	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	237	DONE;"
	238	)
	239
	240	; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	241
23fed240 DD	242	; The m16c has a maximum shift count of -16..16, even when in a
	243	; register. It's optimal to use multiple shifts of -8..8 rather than
	244	; loading larger constants into R1H multiple time. The m32c can shift
	245	; -32..32 either via immediates or in registers. Hence, separate
	246	; patterns.
38b2d076 DD	247
38b2d076 DD	248
23fed240	249	(define_insn "ashlsi3_16"
38b2d076 DD	250	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	251	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	252	(match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
38b2d076	253	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	254	"TARGET_A16"
38b2d076 DD	255	"@
38b2d076 DD	256	sha.l\t%2,%0
23fed240	257	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	258	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	259	)
38b2d076 DD	260
23fed240	261	(define_insn "ashrsi3_16"
38b2d076 DD	262	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	263	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	264	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076	265	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	266	"TARGET_A16"
38b2d076 DD	267	"@
38b2d076 DD	268	sha.l\t%2,%0
23fed240	269	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
16659fcf	270	[(set_attr "flags" "oszc,oszc")]
38b2d076 DD	271	)
38b2d076 DD	272
23fed240	273	(define_insn "lshrsi3_16"
38b2d076 DD	274	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
38b2d076 DD	275	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
23fed240	276	(neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
38b2d076	277	(clobber (match_scratch:HI 3 "=X,R1w"))]
23fed240	278	"TARGET_A16"
38b2d076 DD	279	"@
38b2d076 DD	280	shl.l\t%2,%0
23fed240	281	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
16659fcf	282	[(set_attr "flags" "szc,szc")]
23fed240 DD	283	)
	284
	285
	286
	287	(define_insn "ashlsi3_24"
	288	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	289	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
	290	(match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
	291	(clobber (match_scratch:HI 3 "=X,R1w"))]
	292	"TARGET_A24"
	293	"@
	294	sha.l\t%2,%0
	295	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
38b2d076 DD	296	)
38b2d076 DD	297
23fed240 DD	298	(define_insn "ashrsi3_24"
	299	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	300	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
	301	(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
	302	(clobber (match_scratch:HI 3 "=X,R1w"))]
	303	"TARGET_A24"
	304	"@
	305	sha.l\t%2,%0
	306	mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
	307	)
	308
	309	(define_insn "lshrsi3_24"
	310	[(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
	311	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
	312	(neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
	313	(clobber (match_scratch:HI 3 "=X,R1w"))]
	314	"TARGET_A24"
	315	"@
	316	shl.l\t%2,%0
	317	mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
	318	)
	319
	320
	321
38b2d076 DD	322
	323	(define_expand "ashlsi3"
	324	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
23fed240 DD	325	(ashift:SI (match_operand:SI 1 "r0123_operand" "")
23fed240 DD	326	(match_operand:QI 2 "mrai_operand" "")))
38b2d076 DD	327	(clobber (match_scratch:HI 3 ""))])]
38b2d076 DD	328	""
23fed240	329	"if (m32c_prepare_shift (operands, 1, ASHIFT))
38b2d076 DD	330	DONE;"
	331	)
	332
	333	(define_expand "ashrsi3"
	334	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
	335	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
	336	(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	337	(clobber (match_scratch:HI 3 ""))])]
	338	""
23fed240	339	"if (m32c_prepare_shift (operands, -1, ASHIFTRT))
38b2d076 DD	340	DONE;"
	341	)
	342
	343	(define_expand "lshrsi3"
	344	[(parallel [(set (match_operand:SI 0 "r0123_operand" "")
	345	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
	346	(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
	347	(clobber (match_scratch:HI 3 ""))])]
	348	""
23fed240	349	"if (m32c_prepare_shift (operands, -1, LSHIFTRT))
38b2d076 DD	350	DONE;"
38b2d076 DD	351	)