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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
b6a9c30c | 3 | 2001, 2003, 2004, 2005, 2006, 2007 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
79e68feb RS |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
79e68feb | 21 | |
79e68feb | 22 | #include "config.h" |
f5220a5d | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
da932f04 | 26 | #include "tree.h" |
79e68feb | 27 | #include "rtl.h" |
49ad7cfa | 28 | #include "function.h" |
79e68feb RS |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
79e68feb RS |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
1d8eaa6b | 36 | #include "recog.h" |
f5220a5d | 37 | #include "toplev.h" |
6d5f49b2 RH |
38 | #include "expr.h" |
39 | #include "reload.h" | |
5505f548 | 40 | #include "tm_p.h" |
672a6f42 NB |
41 | #include "target.h" |
42 | #include "target-def.h" | |
2cc07db4 | 43 | #include "debug.h" |
79e68feb | 44 | #include "flags.h" |
6fb5fa3c | 45 | #include "df.h" |
79e68feb | 46 | |
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
a40ed0f3 KH |
59 | /* The minimum number of integer registers that we want to save with the |
60 | movem instruction. Using two movel instructions instead of a single | |
61 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
62 | code size. */ | |
63 | #define MIN_MOVEM_REGS 3 | |
64 | ||
65 | /* The minimum number of floating point registers that we want to save | |
66 | with the fmovem instruction. */ | |
67 | #define MIN_FMOVEM_REGS 1 | |
68 | ||
ff482c8d | 69 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
70 | struct m68k_frame |
71 | { | |
72 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 73 | HOST_WIDE_INT offset; |
3d74bc09 BI |
74 | |
75 | /* Offset of FPU registers. */ | |
76 | HOST_WIDE_INT foffset; | |
77 | ||
78 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 79 | HOST_WIDE_INT size; |
3d74bc09 BI |
80 | |
81 | /* Data and address register. */ | |
48ed72a4 PB |
82 | int reg_no; |
83 | unsigned int reg_mask; | |
3d74bc09 BI |
84 | |
85 | /* FPU registers. */ | |
48ed72a4 PB |
86 | int fpu_no; |
87 | unsigned int fpu_mask; | |
3d74bc09 BI |
88 | |
89 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
90 | HOST_WIDE_INT frame_pointer_offset; |
91 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
92 | |
93 | /* Function which the above information refers to. */ | |
94 | int funcdef_no; | |
48ed72a4 PB |
95 | }; |
96 | ||
3d74bc09 BI |
97 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
98 | static struct m68k_frame current_frame; | |
99 | ||
fc2241eb RS |
100 | /* Structure describing an m68k address. |
101 | ||
102 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
103 | with null fields evaluating to 0. Here: | |
104 | ||
105 | - BASE satisfies m68k_legitimate_base_reg_p | |
106 | - INDEX satisfies m68k_legitimate_index_reg_p | |
107 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
108 | ||
109 | INDEX is either HImode or SImode. The other fields are SImode. | |
110 | ||
111 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
112 | the address is (BASE)+. */ | |
113 | struct m68k_address { | |
114 | enum rtx_code code; | |
115 | rtx base; | |
116 | rtx index; | |
117 | rtx offset; | |
118 | int scale; | |
119 | }; | |
120 | ||
4af06170 | 121 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
122 | static rtx find_addr_reg (rtx); |
123 | static const char *singlemove_string (rtx *); | |
45849738 | 124 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 125 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 126 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
127 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
128 | HOST_WIDE_INT, tree); | |
8636be86 | 129 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
130 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
131 | tree args, int flags, | |
132 | bool *no_add_attrs); | |
3d74bc09 | 133 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 134 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
f7e70894 | 135 | static bool m68k_ok_for_sibcall_p (tree, tree); |
8a4a2253 | 136 | static bool m68k_rtx_costs (rtx, int, int, int *); |
1c445f03 NS |
137 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
138 | static bool m68k_return_in_memory (tree, tree); | |
139 | #endif | |
79e68feb RS |
140 | \f |
141 | ||
a2ef3db7 | 142 | /* Specify the identification number of the library being built */ |
4af06170 | 143 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 144 | |
2b3600ac JL |
145 | /* Nonzero if the last compare/test insn had FP operands. The |
146 | sCC expanders peek at this to determine what to do for the | |
147 | 68060, which has no fsCC instructions. */ | |
148 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
149 | \f |
150 | /* Initialize the GCC target structure. */ | |
301d03af RS |
151 | |
152 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
153 | #undef TARGET_ASM_ALIGNED_HI_OP | |
154 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
155 | #endif | |
156 | ||
157 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
158 | #undef TARGET_ASM_BYTE_OP | |
159 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
160 | #undef TARGET_ASM_ALIGNED_HI_OP | |
161 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
162 | #undef TARGET_ASM_ALIGNED_SI_OP | |
163 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
164 | #endif | |
165 | ||
166 | #if INT_OP_GROUP == INT_OP_DC | |
167 | #undef TARGET_ASM_BYTE_OP | |
168 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
169 | #undef TARGET_ASM_ALIGNED_HI_OP | |
170 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
171 | #undef TARGET_ASM_ALIGNED_SI_OP | |
172 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
173 | #endif | |
174 | ||
175 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
176 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
177 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
178 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
179 | ||
c590b625 RH |
180 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
181 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 | 182 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 183 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 184 | |
1bc7c5b6 ZW |
185 | #undef TARGET_ASM_FILE_START_APP_OFF |
186 | #define TARGET_ASM_FILE_START_APP_OFF true | |
187 | ||
4af06170 RS |
188 | #undef TARGET_HANDLE_OPTION |
189 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
190 | ||
3c50106f RH |
191 | #undef TARGET_RTX_COSTS |
192 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
193 | ||
48ed72a4 PB |
194 | #undef TARGET_ATTRIBUTE_TABLE |
195 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
196 | ||
8636be86 | 197 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 198 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
8636be86 KH |
199 | |
200 | #undef TARGET_STRUCT_VALUE_RTX | |
201 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
202 | ||
7ffb5e78 RS |
203 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
204 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p | |
205 | ||
f7e70894 RS |
206 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
207 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
208 | ||
1c445f03 NS |
209 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
210 | #undef TARGET_RETURN_IN_MEMORY | |
211 | #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory | |
212 | #endif | |
213 | ||
48ed72a4 PB |
214 | static const struct attribute_spec m68k_attribute_table[] = |
215 | { | |
216 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
2bccb817 | 217 | { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
48ed72a4 | 218 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
a4242737 | 219 | { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
48ed72a4 PB |
220 | { NULL, 0, 0, false, false, false, NULL } |
221 | }; | |
222 | ||
f6897b10 | 223 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 224 | \f |
900ec02d JB |
225 | /* Base flags for 68k ISAs. */ |
226 | #define FL_FOR_isa_00 FL_ISA_68000 | |
227 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
228 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
229 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
230 | not to. */ | |
231 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
232 | | FL_BITFIELD | FL_68881) | |
233 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
234 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
235 | ||
236 | /* Base flags for ColdFire ISAs. */ | |
237 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
238 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
239 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
240 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
4e2b26aa | 241 | /* ISA_C is not upwardly compatible with ISA_B. */ |
8c5c99dc | 242 | #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP) |
900ec02d JB |
243 | |
244 | enum m68k_isa | |
245 | { | |
246 | /* Traditional 68000 instruction sets. */ | |
247 | isa_00, | |
248 | isa_10, | |
249 | isa_20, | |
250 | isa_40, | |
251 | isa_cpu32, | |
252 | /* ColdFire instruction set variants. */ | |
253 | isa_a, | |
254 | isa_aplus, | |
255 | isa_b, | |
256 | isa_c, | |
257 | isa_max | |
258 | }; | |
259 | ||
260 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
261 | struct m68k_target_selection | |
262 | { | |
263 | /* The argument being described. */ | |
264 | const char *name; | |
265 | ||
266 | /* For -mcpu, this is the device selected by the option. | |
267 | For -mtune and -march, it is a representative device | |
268 | for the microarchitecture or ISA respectively. */ | |
269 | enum target_device device; | |
270 | ||
271 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
272 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
273 | const char *family; | |
274 | enum uarch_type microarch; | |
275 | enum m68k_isa isa; | |
276 | unsigned long flags; | |
277 | }; | |
278 | ||
279 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
280 | static const struct m68k_target_selection all_devices[] = | |
281 | { | |
282 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
283 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
284 | #include "m68k-devices.def" | |
285 | #undef M68K_DEVICE | |
286 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
287 | }; | |
288 | ||
289 | /* A list of all ISAs, mapping each one to a representative device. | |
290 | Used for -march selection. */ | |
291 | static const struct m68k_target_selection all_isas[] = | |
292 | { | |
293 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
294 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
295 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
296 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
297 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
298 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
299 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
300 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
301 | | FL_CF_HWDIV) }, | |
302 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
303 | | FL_CF_HWDIV) }, | |
304 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
8c5c99dc MK |
305 | { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c |
306 | | FL_CF_HWDIV) }, | |
900ec02d JB |
307 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
308 | }; | |
309 | ||
310 | /* A list of all microarchitectures, mapping each one to a representative | |
311 | device. Used for -mtune selection. */ | |
312 | static const struct m68k_target_selection all_microarchs[] = | |
313 | { | |
314 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
315 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
316 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
317 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
318 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
319 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
320 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
321 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
322 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
8c5c99dc | 323 | { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c }, |
900ec02d JB |
324 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, |
325 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
326 | | FL_CF_HWDIV) }, | |
327 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
328 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
329 | | FL_CF_USP | |
330 | | FL_CF_EMAC | |
331 | | FL_CF_FPU) }, | |
332 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
333 | }; | |
334 | \f | |
335 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
336 | or null for options that have not been used. */ | |
337 | const struct m68k_target_selection *m68k_cpu_entry; | |
338 | const struct m68k_target_selection *m68k_arch_entry; | |
339 | const struct m68k_target_selection *m68k_tune_entry; | |
340 | ||
341 | /* Which CPU we are generating code for. */ | |
342 | enum target_device m68k_cpu; | |
343 | ||
344 | /* Which microarchitecture to tune for. */ | |
345 | enum uarch_type m68k_tune; | |
346 | ||
347 | /* Which FPU to use. */ | |
348 | enum fpu_type m68k_fpu; | |
4af06170 | 349 | |
900ec02d JB |
350 | /* The set of FL_* flags that apply to the target processor. */ |
351 | unsigned int m68k_cpu_flags; | |
29ca003a RS |
352 | |
353 | /* Asm templates for calling or jumping to an arbitrary symbolic address, | |
354 | or NULL if such calls or jumps are not supported. The address is held | |
355 | in operand 0. */ | |
356 | const char *m68k_symbolic_call; | |
357 | const char *m68k_symbolic_jump; | |
c47b0cb4 MK |
358 | |
359 | /* Enum variable that corresponds to m68k_symbolic_call values. */ | |
360 | enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; | |
361 | ||
900ec02d JB |
362 | \f |
363 | /* See whether TABLE has an entry with name NAME. Return true and | |
364 | store the entry in *ENTRY if so, otherwise return false and | |
365 | leave *ENTRY alone. */ | |
366 | ||
367 | static bool | |
368 | m68k_find_selection (const struct m68k_target_selection **entry, | |
369 | const struct m68k_target_selection *table, | |
370 | const char *name) | |
371 | { | |
372 | size_t i; | |
373 | ||
374 | for (i = 0; table[i].name; i++) | |
375 | if (strcmp (table[i].name, name) == 0) | |
376 | { | |
377 | *entry = table + i; | |
378 | return true; | |
379 | } | |
380 | return false; | |
381 | } | |
4af06170 RS |
382 | |
383 | /* Implement TARGET_HANDLE_OPTION. */ | |
384 | ||
385 | static bool | |
386 | m68k_handle_option (size_t code, const char *arg, int value) | |
387 | { | |
388 | switch (code) | |
389 | { | |
900ec02d JB |
390 | case OPT_march_: |
391 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
392 | ||
393 | case OPT_mcpu_: | |
394 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
395 | ||
396 | case OPT_mtune_: | |
397 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
398 | ||
4af06170 | 399 | case OPT_m5200: |
900ec02d | 400 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
401 | |
402 | case OPT_m5206e: | |
900ec02d | 403 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
404 | |
405 | case OPT_m528x: | |
900ec02d | 406 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
407 | |
408 | case OPT_m5307: | |
900ec02d | 409 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
410 | |
411 | case OPT_m5407: | |
900ec02d | 412 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 413 | |
dcc21c4c | 414 | case OPT_mcfv4e: |
900ec02d | 415 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 416 | |
4af06170 RS |
417 | case OPT_m68000: |
418 | case OPT_mc68000: | |
900ec02d | 419 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 420 | |
3197c489 | 421 | case OPT_m68010: |
900ec02d | 422 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 423 | |
4af06170 RS |
424 | case OPT_m68020: |
425 | case OPT_mc68020: | |
900ec02d | 426 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
427 | |
428 | case OPT_m68020_40: | |
900ec02d JB |
429 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
430 | "68020-40") | |
431 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
432 | |
433 | case OPT_m68020_60: | |
900ec02d JB |
434 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
435 | "68020-60") | |
436 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
437 | |
438 | case OPT_m68030: | |
900ec02d | 439 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
440 | |
441 | case OPT_m68040: | |
900ec02d | 442 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
443 | |
444 | case OPT_m68060: | |
900ec02d | 445 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
446 | |
447 | case OPT_m68302: | |
900ec02d | 448 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
449 | |
450 | case OPT_m68332: | |
451 | case OPT_mcpu32: | |
900ec02d | 452 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
453 | |
454 | case OPT_mshared_library_id_: | |
455 | if (value > MAX_LIBRARY_ID) | |
456 | error ("-mshared-library-id=%s is not between 0 and %d", | |
457 | arg, MAX_LIBRARY_ID); | |
458 | else | |
459 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
460 | return true; | |
461 | ||
462 | default: | |
463 | return true; | |
464 | } | |
465 | } | |
466 | ||
ef1dbfb0 RK |
467 | /* Sometimes certain combinations of command options do not make |
468 | sense on a particular target machine. You can define a macro | |
469 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
470 | defined, is executed once just after all the command options have | |
471 | been parsed. | |
472 | ||
473 | Don't use this macro to turn on various extra optimizations for | |
474 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
475 | ||
476 | void | |
8a4a2253 | 477 | override_options (void) |
ef1dbfb0 | 478 | { |
900ec02d JB |
479 | const struct m68k_target_selection *entry; |
480 | unsigned long target_mask; | |
481 | ||
482 | /* User can choose: | |
483 | ||
484 | -mcpu= | |
485 | -march= | |
486 | -mtune= | |
487 | ||
488 | -march=ARCH should generate code that runs any processor | |
489 | implementing architecture ARCH. -mcpu=CPU should override -march | |
490 | and should generate code that runs on processor CPU, making free | |
491 | use of any instructions that CPU understands. -mtune=UARCH applies | |
9f5ed61a | 492 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
900ec02d JB |
493 | not change the target architecture. */ |
494 | if (m68k_cpu_entry) | |
495 | { | |
496 | /* Complain if the -march setting is for a different microarchitecture, | |
497 | or includes flags that the -mcpu setting doesn't. */ | |
498 | if (m68k_arch_entry | |
499 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
500 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
501 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
502 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
503 | ||
504 | entry = m68k_cpu_entry; | |
505 | } | |
506 | else | |
507 | entry = m68k_arch_entry; | |
508 | ||
509 | if (!entry) | |
510 | entry = all_devices + TARGET_CPU_DEFAULT; | |
511 | ||
512 | m68k_cpu_flags = entry->flags; | |
513 | ||
514 | /* Use the architecture setting to derive default values for | |
515 | certain flags. */ | |
516 | target_mask = 0; | |
8785d88c KH |
517 | |
518 | /* ColdFire is lenient about alignment. */ | |
519 | if (!TARGET_COLDFIRE) | |
520 | target_mask |= MASK_STRICT_ALIGNMENT; | |
521 | ||
900ec02d JB |
522 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) |
523 | target_mask |= MASK_BITFIELD; | |
524 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
525 | target_mask |= MASK_CF_HWDIV; | |
526 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
527 | target_mask |= MASK_HARD_FLOAT; | |
528 | target_flags |= target_mask & ~target_flags_explicit; | |
529 | ||
530 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
531 | m68k_cpu = entry->device; | |
532 | if (m68k_tune_entry) | |
533 | m68k_tune = m68k_tune_entry->microarch; | |
534 | #ifdef M68K_DEFAULT_TUNE | |
535 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
536 | m68k_tune = M68K_DEFAULT_TUNE; | |
537 | #endif | |
538 | else | |
539 | m68k_tune = entry->microarch; | |
540 | ||
541 | /* Set the type of FPU. */ | |
542 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
543 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
544 | : FPUTYPE_68881); | |
545 | ||
a2ef3db7 BI |
546 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
547 | * both specified together. Doing so simply doesn't make sense. | |
548 | */ | |
549 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
550 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
551 | ||
552 | /* If we're generating code for a separate A5 relative data segment, | |
553 | * we've got to enable -fPIC as well. This might be relaxable to | |
554 | * -fpic but it hasn't been tested properly. | |
555 | */ | |
556 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
557 | flag_pic = 2; | |
558 | ||
abe92a04 RS |
559 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
560 | error if the target does not support them. */ | |
561 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
562 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
563 | |
564 | /* ??? A historic way of turning on pic, or is this intended to | |
565 | be an embedded thing that doesn't have the same name binding | |
566 | significance that it does on hosted ELF systems? */ | |
567 | if (TARGET_PCREL && flag_pic == 0) | |
568 | flag_pic = 1; | |
569 | ||
29ca003a RS |
570 | if (!flag_pic) |
571 | { | |
c47b0cb4 MK |
572 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR; |
573 | ||
29ca003a | 574 | m68k_symbolic_jump = "jra %a0"; |
29ca003a RS |
575 | } |
576 | else if (TARGET_ID_SHARED_LIBRARY) | |
577 | /* All addresses must be loaded from the GOT. */ | |
578 | ; | |
4e2b26aa | 579 | else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) |
29ca003a RS |
580 | { |
581 | if (TARGET_PCREL) | |
c47b0cb4 | 582 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C; |
4e2b26aa | 583 | else |
c47b0cb4 MK |
584 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P; |
585 | ||
4e2b26aa NS |
586 | if (TARGET_ISAC) |
587 | /* No unconditional long branch */; | |
588 | else if (TARGET_PCREL) | |
da398bb5 | 589 | m68k_symbolic_jump = "bra%.l %c0"; |
29ca003a | 590 | else |
da398bb5 | 591 | m68k_symbolic_jump = "bra%.l %p0"; |
29ca003a RS |
592 | /* Turn off function cse if we are doing PIC. We always want |
593 | function call to be done as `bsr foo@PLTPC'. */ | |
594 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
595 | clear how intentional that is. */ | |
596 | flag_no_function_cse = 1; | |
597 | } | |
adf2ac37 | 598 | |
c47b0cb4 MK |
599 | switch (m68k_symbolic_call_var) |
600 | { | |
601 | case M68K_SYMBOLIC_CALL_JSR: | |
c47b0cb4 | 602 | m68k_symbolic_call = "jsr %a0"; |
c47b0cb4 MK |
603 | break; |
604 | ||
605 | case M68K_SYMBOLIC_CALL_BSR_C: | |
da398bb5 | 606 | m68k_symbolic_call = "bsr%.l %c0"; |
c47b0cb4 MK |
607 | break; |
608 | ||
609 | case M68K_SYMBOLIC_CALL_BSR_P: | |
da398bb5 | 610 | m68k_symbolic_call = "bsr%.l %p0"; |
c47b0cb4 MK |
611 | break; |
612 | ||
613 | case M68K_SYMBOLIC_CALL_NONE: | |
614 | gcc_assert (m68k_symbolic_call == NULL); | |
615 | break; | |
616 | ||
617 | default: | |
618 | gcc_unreachable (); | |
619 | } | |
620 | ||
aaca7021 RZ |
621 | #ifndef ASM_OUTPUT_ALIGN_WITH_NOP |
622 | if (align_labels > 2) | |
623 | { | |
624 | warning (0, "-falign-labels=%d is not supported", align_labels); | |
625 | align_labels = 0; | |
626 | } | |
627 | if (align_loops > 2) | |
628 | { | |
629 | warning (0, "-falign-loops=%d is not supported", align_loops); | |
630 | align_loops = 0; | |
631 | } | |
632 | #endif | |
633 | ||
adf2ac37 | 634 | SUBTARGET_OVERRIDE_OPTIONS; |
c47b0cb4 MK |
635 | |
636 | /* Setup scheduling options. */ | |
637 | if (TUNE_CFV2) | |
638 | m68k_sched_cpu = CPU_CF_V2; | |
639 | else | |
640 | { | |
641 | m68k_sched_cpu = CPU_UNKNOWN; | |
642 | flag_schedule_insns = 0; | |
643 | flag_schedule_insns_after_reload = 0; | |
644 | flag_modulo_sched = 0; | |
645 | } | |
ef1dbfb0 | 646 | } |
7eb4f044 NS |
647 | |
648 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the | |
649 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
650 | if -mcpu was not passed. */ | |
651 | ||
652 | const char * | |
653 | m68k_cpp_cpu_ident (const char *prefix) | |
654 | { | |
655 | if (!m68k_cpu_entry) | |
656 | return NULL; | |
657 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
658 | } | |
659 | ||
660 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
661 | given argument and NAME is the name of the representative device for | |
662 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
663 | ||
664 | const char * | |
665 | m68k_cpp_cpu_family (const char *prefix) | |
666 | { | |
667 | if (!m68k_cpu_entry) | |
668 | return NULL; | |
669 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
670 | } | |
79e68feb | 671 | \f |
2bccb817 KH |
672 | /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or |
673 | "interrupt_handler" attribute and interrupt_thread if FUNC has an | |
674 | "interrupt_thread" attribute. Otherwise, return | |
675 | m68k_fk_normal_function. */ | |
a4242737 KH |
676 | |
677 | enum m68k_function_kind | |
678 | m68k_get_function_kind (tree func) | |
48ed72a4 PB |
679 | { |
680 | tree a; | |
681 | ||
fa157b28 NS |
682 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
683 | ||
2bccb817 KH |
684 | a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); |
685 | if (a != NULL_TREE) | |
686 | return m68k_fk_interrupt_handler; | |
687 | ||
48ed72a4 | 688 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
a4242737 KH |
689 | if (a != NULL_TREE) |
690 | return m68k_fk_interrupt_handler; | |
691 | ||
692 | a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); | |
693 | if (a != NULL_TREE) | |
694 | return m68k_fk_interrupt_thread; | |
695 | ||
696 | return m68k_fk_normal_function; | |
48ed72a4 PB |
697 | } |
698 | ||
699 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
700 | struct attribute_spec.handler. */ | |
701 | static tree | |
702 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
703 | tree args ATTRIBUTE_UNUSED, | |
704 | int flags ATTRIBUTE_UNUSED, | |
705 | bool *no_add_attrs) | |
706 | { | |
707 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
708 | { | |
5c498b10 | 709 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
710 | IDENTIFIER_POINTER (name)); |
711 | *no_add_attrs = true; | |
712 | } | |
713 | ||
a4242737 KH |
714 | if (m68k_get_function_kind (*node) != m68k_fk_normal_function) |
715 | { | |
716 | error ("multiple interrupt attributes not allowed"); | |
717 | *no_add_attrs = true; | |
718 | } | |
719 | ||
720 | if (!TARGET_FIDOA | |
721 | && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) | |
722 | { | |
723 | error ("interrupt_thread is available only on fido"); | |
724 | *no_add_attrs = true; | |
725 | } | |
726 | ||
48ed72a4 PB |
727 | return NULL_TREE; |
728 | } | |
860c4900 BI |
729 | |
730 | static void | |
3d74bc09 | 731 | m68k_compute_frame_layout (void) |
860c4900 BI |
732 | { |
733 | int regno, saved; | |
a40ed0f3 | 734 | unsigned int mask; |
a4242737 KH |
735 | enum m68k_function_kind func_kind = |
736 | m68k_get_function_kind (current_function_decl); | |
737 | bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; | |
738 | bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; | |
860c4900 | 739 | |
3d74bc09 BI |
740 | /* Only compute the frame once per function. |
741 | Don't cache information until reload has been completed. */ | |
742 | if (current_frame.funcdef_no == current_function_funcdef_no | |
743 | && reload_completed) | |
744 | return; | |
745 | ||
746 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 | 747 | |
a40ed0f3 | 748 | mask = saved = 0; |
a4242737 KH |
749 | |
750 | /* Interrupt thread does not need to save any register. */ | |
751 | if (!interrupt_thread) | |
752 | for (regno = 0; regno < 16; regno++) | |
753 | if (m68k_save_reg (regno, interrupt_handler)) | |
754 | { | |
755 | mask |= 1 << (regno - D0_REG); | |
756 | saved++; | |
757 | } | |
3d74bc09 BI |
758 | current_frame.offset = saved * 4; |
759 | current_frame.reg_no = saved; | |
760 | current_frame.reg_mask = mask; | |
860c4900 | 761 | |
57047680 | 762 | current_frame.foffset = 0; |
a40ed0f3 | 763 | mask = saved = 0; |
dcc21c4c | 764 | if (TARGET_HARD_FLOAT) |
860c4900 | 765 | { |
a4242737 KH |
766 | /* Interrupt thread does not need to save any register. */ |
767 | if (!interrupt_thread) | |
768 | for (regno = 16; regno < 24; regno++) | |
769 | if (m68k_save_reg (regno, interrupt_handler)) | |
770 | { | |
771 | mask |= 1 << (regno - FP0_REG); | |
772 | saved++; | |
773 | } | |
dcc21c4c | 774 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 775 | current_frame.offset += current_frame.foffset; |
860c4900 | 776 | } |
57047680 GN |
777 | current_frame.fpu_no = saved; |
778 | current_frame.fpu_mask = mask; | |
3d74bc09 BI |
779 | |
780 | /* Remember what function this frame refers to. */ | |
781 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
782 | } |
783 | ||
784 | HOST_WIDE_INT | |
785 | m68k_initial_elimination_offset (int from, int to) | |
786 | { | |
42b67c06 PB |
787 | int argptr_offset; |
788 | /* The arg pointer points 8 bytes before the start of the arguments, | |
789 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
790 | frame pointer in most frames. */ | |
791 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 792 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 793 | return argptr_offset; |
860c4900 | 794 | |
3d74bc09 | 795 | m68k_compute_frame_layout (); |
860c4900 | 796 | |
4761e388 NS |
797 | gcc_assert (to == STACK_POINTER_REGNUM); |
798 | switch (from) | |
799 | { | |
a0a7fbc9 | 800 | case ARG_POINTER_REGNUM: |
42b67c06 | 801 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
802 | case FRAME_POINTER_REGNUM: |
803 | return current_frame.offset + current_frame.size; | |
804 | default: | |
805 | gcc_unreachable (); | |
806 | } | |
860c4900 BI |
807 | } |
808 | ||
97c55091 GN |
809 | /* Refer to the array `regs_ever_live' to determine which registers |
810 | to save; `regs_ever_live[I]' is nonzero if register number I | |
811 | is ever used in the function. This function is responsible for | |
812 | knowing which registers should not be saved even if used. | |
813 | Return true if we need to save REGNO. */ | |
814 | ||
48ed72a4 PB |
815 | static bool |
816 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 817 | { |
4ab870f5 | 818 | if (flag_pic && regno == PIC_REG) |
b86ba8a3 | 819 | { |
215161e2 | 820 | if (current_function_saves_all_registers) |
afcb440c | 821 | return true; |
b86ba8a3 AT |
822 | if (current_function_uses_pic_offset_table) |
823 | return true; | |
6357eb0d RS |
824 | /* Reload may introduce constant pool references into a function |
825 | that thitherto didn't need a PIC register. Note that the test | |
826 | above will not catch that case because we will only set | |
827 | current_function_uses_pic_offset_table when emitting | |
828 | the address reloads. */ | |
829 | if (current_function_uses_const_pool) | |
830 | return true; | |
b86ba8a3 | 831 | } |
2cff4a6e AS |
832 | |
833 | if (current_function_calls_eh_return) | |
834 | { | |
835 | unsigned int i; | |
836 | for (i = 0; ; i++) | |
837 | { | |
838 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
839 | if (test == INVALID_REGNUM) | |
840 | break; | |
841 | if (test == regno) | |
48ed72a4 | 842 | return true; |
2cff4a6e AS |
843 | } |
844 | } | |
845 | ||
48ed72a4 PB |
846 | /* Fixed regs we never touch. */ |
847 | if (fixed_regs[regno]) | |
848 | return false; | |
849 | ||
850 | /* The frame pointer (if it is such) is handled specially. */ | |
851 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
852 | return false; | |
853 | ||
854 | /* Interrupt handlers must also save call_used_regs | |
855 | if they are live or when calling nested functions. */ | |
856 | if (interrupt_handler) | |
a0a7fbc9 | 857 | { |
6fb5fa3c | 858 | if (df_regs_ever_live_p (regno)) |
a0a7fbc9 | 859 | return true; |
48ed72a4 | 860 | |
a0a7fbc9 AS |
861 | if (!current_function_is_leaf && call_used_regs[regno]) |
862 | return true; | |
863 | } | |
48ed72a4 PB |
864 | |
865 | /* Never need to save registers that aren't touched. */ | |
6fb5fa3c | 866 | if (!df_regs_ever_live_p (regno)) |
48ed72a4 PB |
867 | return false; |
868 | ||
b2e08ed4 | 869 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 870 | return !call_used_regs[regno]; |
2cff4a6e AS |
871 | } |
872 | ||
a40ed0f3 KH |
873 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
874 | the lowest memory address. COUNT is the number of registers to be | |
875 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
876 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
877 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
878 | (if !STORE_P) operation. */ | |
879 | ||
880 | static rtx | |
881 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, | |
882 | unsigned int count, unsigned int regno, | |
883 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
884 | { | |
885 | int i; | |
886 | rtx body, addr, src, operands[2]; | |
887 | enum machine_mode mode; | |
888 | ||
889 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
890 | mode = reg_raw_mode[regno]; | |
891 | i = 0; | |
892 | ||
893 | if (adjust_stack_p) | |
894 | { | |
895 | src = plus_constant (base, (count | |
896 | * GET_MODE_SIZE (mode) | |
897 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
898 | XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src); | |
899 | } | |
900 | ||
901 | for (; mask != 0; mask >>= 1, regno++) | |
902 | if (mask & 1) | |
903 | { | |
904 | addr = plus_constant (base, offset); | |
905 | operands[!store_p] = gen_frame_mem (mode, addr); | |
906 | operands[store_p] = gen_rtx_REG (mode, regno); | |
907 | XVECEXP (body, 0, i++) | |
908 | = gen_rtx_SET (VOIDmode, operands[0], operands[1]); | |
909 | offset += GET_MODE_SIZE (mode); | |
910 | } | |
911 | gcc_assert (i == XVECLEN (body, 0)); | |
912 | ||
913 | return emit_insn (body); | |
914 | } | |
915 | ||
916 | /* Make INSN a frame-related instruction. */ | |
79e68feb | 917 | |
08c148a8 | 918 | static void |
a40ed0f3 KH |
919 | m68k_set_frame_related (rtx insn) |
920 | { | |
921 | rtx body; | |
922 | int i; | |
923 | ||
924 | RTX_FRAME_RELATED_P (insn) = 1; | |
925 | body = PATTERN (insn); | |
926 | if (GET_CODE (body) == PARALLEL) | |
927 | for (i = 0; i < XVECLEN (body, 0); i++) | |
928 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
929 | } | |
930 | ||
931 | /* Emit RTL for the "prologue" define_expand. */ | |
932 | ||
933 | void | |
934 | m68k_expand_prologue (void) | |
79e68feb | 935 | { |
860c4900 | 936 | HOST_WIDE_INT fsize_with_regs; |
a40ed0f3 | 937 | rtx limit, src, dest, insn; |
3d74bc09 | 938 | |
a40ed0f3 | 939 | m68k_compute_frame_layout (); |
3d74bc09 | 940 | |
a157febd GK |
941 | /* If the stack limit is a symbol, we can check it here, |
942 | before actually allocating the space. */ | |
943 | if (current_function_limit_stack | |
944 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
a40ed0f3 KH |
945 | { |
946 | limit = plus_constant (stack_limit_rtx, current_frame.size + 4); | |
947 | if (!LEGITIMATE_CONSTANT_P (limit)) | |
948 | { | |
949 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
950 | limit = gen_rtx_REG (Pmode, D0_REG); | |
951 | } | |
952 | emit_insn (gen_cmpsi (stack_pointer_rtx, limit)); | |
953 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
954 | cc0_rtx, const0_rtx), | |
955 | const1_rtx)); | |
956 | } | |
79e68feb | 957 | |
a89e3f21 | 958 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
959 | if (TARGET_COLDFIRE) |
960 | { | |
a40ed0f3 KH |
961 | /* ColdFire's move multiple instructions do not allow pre-decrement |
962 | addressing. Add the size of movem saves to the initial stack | |
963 | allocation instead. */ | |
964 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
965 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
966 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
967 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 968 | } |
860c4900 | 969 | |
79e68feb RS |
970 | if (frame_pointer_needed) |
971 | { | |
a40ed0f3 | 972 | if (fsize_with_regs == 0 && TUNE_68040) |
79e68feb | 973 | { |
a40ed0f3 KH |
974 | /* On the 68040, two separate moves are faster than link.w 0. */ |
975 | dest = gen_frame_mem (Pmode, | |
976 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
977 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
978 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
979 | stack_pointer_rtx)); | |
79e68feb | 980 | } |
a40ed0f3 KH |
981 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
982 | m68k_set_frame_related | |
983 | (emit_insn (gen_link (frame_pointer_rtx, | |
984 | GEN_INT (-4 - fsize_with_regs)))); | |
d9e88af0 | 985 | else |
a40ed0f3 KH |
986 | { |
987 | m68k_set_frame_related | |
988 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
989 | m68k_set_frame_related | |
990 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
991 | stack_pointer_rtx, | |
992 | GEN_INT (-fsize_with_regs)))); | |
993 | } | |
d9e88af0 | 994 | } |
a40ed0f3 KH |
995 | else if (fsize_with_regs != 0) |
996 | m68k_set_frame_related | |
997 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
998 | stack_pointer_rtx, | |
999 | GEN_INT (-fsize_with_regs)))); | |
860c4900 | 1000 | |
57047680 | 1001 | if (current_frame.fpu_mask) |
79e68feb | 1002 | { |
a40ed0f3 | 1003 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
dcc21c4c | 1004 | if (TARGET_68881) |
a40ed0f3 KH |
1005 | m68k_set_frame_related |
1006 | (m68k_emit_movem (stack_pointer_rtx, | |
1007 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
1008 | current_frame.fpu_no, FP0_REG, | |
1009 | current_frame.fpu_mask, true, true)); | |
dcc21c4c PB |
1010 | else |
1011 | { | |
1012 | int offset; | |
1013 | ||
a40ed0f3 KH |
1014 | /* If we're using moveml to save the integer registers, |
1015 | the stack pointer will point to the bottom of the moveml | |
1016 | save area. Find the stack offset of the first FP register. */ | |
1017 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1018 | offset = 0; |
1019 | else | |
a40ed0f3 KH |
1020 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1021 | m68k_set_frame_related | |
1022 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
1023 | current_frame.fpu_no, FP0_REG, | |
1024 | current_frame.fpu_mask, true, false)); | |
f277471f | 1025 | } |
79e68feb | 1026 | } |
99df2465 | 1027 | |
01bbf777 | 1028 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
1029 | This has the disadvantage that it may be too late... */ |
1030 | if (current_function_limit_stack) | |
1031 | { | |
1032 | if (REG_P (stack_limit_rtx)) | |
a40ed0f3 KH |
1033 | { |
1034 | emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx)); | |
1035 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
1036 | cc0_rtx, const0_rtx), | |
1037 | const1_rtx)); | |
1038 | } | |
a157febd | 1039 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 1040 | warning (0, "stack limit expression is not supported"); |
a157febd | 1041 | } |
01bbf777 | 1042 | |
a40ed0f3 | 1043 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
79e68feb | 1044 | { |
a40ed0f3 | 1045 | /* Store each register separately in the same order moveml does. */ |
79e68feb RS |
1046 | int i; |
1047 | ||
a40ed0f3 KH |
1048 | for (i = 16; i-- > 0; ) |
1049 | if (current_frame.reg_mask & (1 << i)) | |
078e983e | 1050 | { |
a40ed0f3 KH |
1051 | src = gen_rtx_REG (SImode, D0_REG + i); |
1052 | dest = gen_frame_mem (SImode, | |
1053 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1054 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
078e983e | 1055 | } |
79e68feb | 1056 | } |
a40ed0f3 | 1057 | else |
79e68feb | 1058 | { |
9425fb04 | 1059 | if (TARGET_COLDFIRE) |
a40ed0f3 KH |
1060 | /* The required register save space has already been allocated. |
1061 | The first register should be stored at (%sp). */ | |
1062 | m68k_set_frame_related | |
1063 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
1064 | current_frame.reg_no, D0_REG, | |
1065 | current_frame.reg_mask, true, false)); | |
afaff477 | 1066 | else |
a40ed0f3 KH |
1067 | m68k_set_frame_related |
1068 | (m68k_emit_movem (stack_pointer_rtx, | |
1069 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1070 | current_frame.reg_no, D0_REG, | |
1071 | current_frame.reg_mask, true, true)); | |
79e68feb | 1072 | } |
a40ed0f3 KH |
1073 | |
1074 | if (flag_pic | |
1075 | && !TARGET_SEP_DATA | |
4f44ecc0 | 1076 | && current_function_uses_pic_offset_table) |
6fb5fa3c | 1077 | insn = emit_insn (gen_load_got (pic_offset_table_rtx)); |
79e68feb RS |
1078 | } |
1079 | \f | |
413ac1b2 RS |
1080 | /* Return true if a simple (return) instruction is sufficient for this |
1081 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1082 | |
3d74bc09 | 1083 | bool |
a2bda628 | 1084 | m68k_use_return_insn (void) |
79e68feb | 1085 | { |
79e68feb | 1086 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1087 | return false; |
125ed86f | 1088 | |
a0a7fbc9 | 1089 | m68k_compute_frame_layout (); |
413ac1b2 | 1090 | return current_frame.offset == 0; |
79e68feb RS |
1091 | } |
1092 | ||
f7e70894 RS |
1093 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1094 | SIBCALL_P says which. | |
79e68feb RS |
1095 | |
1096 | The function epilogue should not depend on the current stack pointer! | |
1097 | It should use the frame pointer only, if there is a frame pointer. | |
1098 | This is mandatory because of alloca; we also take advantage of it to | |
1099 | omit stack adjustments before returning. */ | |
1100 | ||
a40ed0f3 | 1101 | void |
f7e70894 | 1102 | m68k_expand_epilogue (bool sibcall_p) |
08c148a8 | 1103 | { |
3d74bc09 | 1104 | HOST_WIDE_INT fsize, fsize_with_regs; |
a40ed0f3 | 1105 | bool big, restore_from_sp; |
3d74bc09 | 1106 | |
a0a7fbc9 | 1107 | m68k_compute_frame_layout (); |
3d74bc09 | 1108 | |
3d74bc09 | 1109 | fsize = current_frame.size; |
a40ed0f3 KH |
1110 | big = false; |
1111 | restore_from_sp = false; | |
3d74bc09 | 1112 | |
a40ed0f3 | 1113 | /* FIXME : current_function_is_leaf below is too strong. |
c67ddce5 | 1114 | What we really need to know there is if there could be pending |
7a1929e1 | 1115 | stack adjustment needed at that point. */ |
a40ed0f3 KH |
1116 | restore_from_sp = (!frame_pointer_needed |
1117 | || (!current_function_calls_alloca | |
1118 | && current_function_is_leaf)); | |
860c4900 BI |
1119 | |
1120 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1121 | popping the frame. */ |
860c4900 | 1122 | fsize_with_regs = fsize; |
dcc21c4c PB |
1123 | if (TARGET_COLDFIRE && restore_from_sp) |
1124 | { | |
a40ed0f3 KH |
1125 | /* ColdFire's move multiple instructions do not allow post-increment |
1126 | addressing. Add the size of movem loads to the final deallocation | |
1127 | instead. */ | |
1128 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1129 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1130 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1131 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1132 | } |
860c4900 | 1133 | |
3d74bc09 | 1134 | if (current_frame.offset + fsize >= 0x8000 |
a40ed0f3 | 1135 | && !restore_from_sp |
3d74bc09 | 1136 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1137 | { |
a40ed0f3 KH |
1138 | if (TARGET_COLDFIRE |
1139 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1140 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1141 | { | |
1142 | /* ColdFire's move multiple instructions do not support the | |
1143 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1144 | stack-based restore. */ | |
1145 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1146 | GEN_INT (-(current_frame.offset + fsize))); | |
1147 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1148 | gen_rtx_REG (Pmode, A1_REG), | |
1149 | frame_pointer_rtx)); | |
1150 | restore_from_sp = true; | |
1151 | } | |
1152 | else | |
1153 | { | |
1154 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1155 | fsize = 0; | |
1156 | big = true; | |
1157 | } | |
79e68feb | 1158 | } |
79e68feb | 1159 | |
a40ed0f3 KH |
1160 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1161 | { | |
1162 | /* Restore each register separately in the same order moveml does. */ | |
79e68feb | 1163 | int i; |
a40ed0f3 | 1164 | HOST_WIDE_INT offset; |
79e68feb | 1165 | |
a40ed0f3 | 1166 | offset = current_frame.offset + fsize; |
3d74bc09 BI |
1167 | for (i = 0; i < 16; i++) |
1168 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb | 1169 | { |
a40ed0f3 KH |
1170 | rtx addr; |
1171 | ||
1172 | if (big) | |
79e68feb | 1173 | { |
a40ed0f3 KH |
1174 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1175 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1176 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
1177 | addr = plus_constant (addr, -offset); | |
79e68feb | 1178 | } |
a40ed0f3 KH |
1179 | else if (restore_from_sp) |
1180 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1181 | else | |
1182 | addr = plus_constant (frame_pointer_rtx, -offset); | |
1183 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), | |
1184 | gen_frame_mem (SImode, addr)); | |
1185 | offset -= GET_MODE_SIZE (SImode); | |
1186 | } | |
79e68feb | 1187 | } |
3d74bc09 | 1188 | else if (current_frame.reg_mask) |
79e68feb | 1189 | { |
a40ed0f3 KH |
1190 | if (big) |
1191 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1192 | gen_rtx_REG (Pmode, A1_REG), | |
1193 | frame_pointer_rtx), | |
1194 | -(current_frame.offset + fsize), | |
1195 | current_frame.reg_no, D0_REG, | |
1196 | current_frame.reg_mask, false, false); | |
1197 | else if (restore_from_sp) | |
1198 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1199 | current_frame.reg_no, D0_REG, | |
1200 | current_frame.reg_mask, false, | |
1201 | !TARGET_COLDFIRE); | |
1202 | else | |
1203 | m68k_emit_movem (frame_pointer_rtx, | |
1204 | -(current_frame.offset + fsize), | |
1205 | current_frame.reg_no, D0_REG, | |
1206 | current_frame.reg_mask, false, false); | |
79e68feb | 1207 | } |
a40ed0f3 KH |
1208 | |
1209 | if (current_frame.fpu_no > 0) | |
79e68feb RS |
1210 | { |
1211 | if (big) | |
a40ed0f3 KH |
1212 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1213 | gen_rtx_REG (Pmode, A1_REG), | |
1214 | frame_pointer_rtx), | |
1215 | -(current_frame.foffset + fsize), | |
1216 | current_frame.fpu_no, FP0_REG, | |
1217 | current_frame.fpu_mask, false, false); | |
6910dd70 | 1218 | else if (restore_from_sp) |
79e68feb | 1219 | { |
dcc21c4c PB |
1220 | if (TARGET_COLDFIRE) |
1221 | { | |
1222 | int offset; | |
1223 | ||
a40ed0f3 KH |
1224 | /* If we used moveml to restore the integer registers, the |
1225 | stack pointer will still point to the bottom of the moveml | |
1226 | save area. Find the stack offset of the first FP | |
1227 | register. */ | |
1228 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1229 | offset = 0; |
1230 | else | |
a40ed0f3 KH |
1231 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1232 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1233 | current_frame.fpu_no, FP0_REG, | |
1234 | current_frame.fpu_mask, false, false); | |
dcc21c4c | 1235 | } |
884b74f0 | 1236 | else |
a40ed0f3 KH |
1237 | m68k_emit_movem (stack_pointer_rtx, 0, |
1238 | current_frame.fpu_no, FP0_REG, | |
1239 | current_frame.fpu_mask, false, true); | |
79e68feb RS |
1240 | } |
1241 | else | |
a40ed0f3 KH |
1242 | m68k_emit_movem (frame_pointer_rtx, |
1243 | -(current_frame.foffset + fsize), | |
1244 | current_frame.fpu_no, FP0_REG, | |
1245 | current_frame.fpu_mask, false, false); | |
79e68feb | 1246 | } |
a40ed0f3 | 1247 | |
79e68feb | 1248 | if (frame_pointer_needed) |
a40ed0f3 | 1249 | emit_insn (gen_unlink (frame_pointer_rtx)); |
860c4900 | 1250 | else if (fsize_with_regs) |
a40ed0f3 KH |
1251 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1252 | stack_pointer_rtx, | |
1253 | GEN_INT (fsize_with_regs))); | |
1254 | ||
2cff4a6e | 1255 | if (current_function_calls_eh_return) |
a40ed0f3 KH |
1256 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1257 | stack_pointer_rtx, | |
1258 | EH_RETURN_STACKADJ_RTX)); | |
1259 | ||
f7e70894 | 1260 | if (!sibcall_p) |
49570723 | 1261 | emit_jump_insn (gen_rtx_RETURN (VOIDmode)); |
79e68feb RS |
1262 | } |
1263 | \f | |
8a4a2253 | 1264 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1265 | instruction. |
1266 | ||
1267 | Note it rejects floating point comparison operators. | |
1268 | (In the future we could use Fdbcc). | |
1269 | ||
1270 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1271 | ||
1272 | int | |
41b6a5e2 | 1273 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1274 | { |
64a184e9 RS |
1275 | switch (GET_CODE (x)) |
1276 | { | |
64a184e9 RS |
1277 | case EQ: case NE: case GTU: case LTU: |
1278 | case GEU: case LEU: | |
1279 | return 1; | |
1280 | ||
1281 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1282 | conservative */ | |
1283 | case GT: case LT: case GE: case LE: | |
1284 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1285 | default: | |
1286 | return 0; | |
1287 | } | |
1288 | } | |
1289 | ||
a0ab749a | 1290 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1291 | int |
8a4a2253 | 1292 | flags_in_68881 (void) |
6a0f85e3 TG |
1293 | { |
1294 | /* We could add support for these in the future */ | |
1295 | return cc_status.flags & CC_IN_68881; | |
1296 | } | |
1297 | ||
fa157b28 | 1298 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ |
f7e70894 RS |
1299 | |
1300 | static bool | |
fa157b28 | 1301 | m68k_ok_for_sibcall_p (tree decl, tree exp) |
f7e70894 | 1302 | { |
fa157b28 NS |
1303 | enum m68k_function_kind kind; |
1304 | ||
1305 | /* We cannot use sibcalls for nested functions because we use the | |
1306 | static chain register for indirect calls. */ | |
1307 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1308 | return false; | |
1309 | ||
1310 | kind = m68k_get_function_kind (current_function_decl); | |
1311 | if (kind == m68k_fk_normal_function) | |
1312 | /* We can always sibcall from a normal function, because it's | |
1313 | undefined if it is calling an interrupt function. */ | |
1314 | return true; | |
1315 | ||
1316 | /* Otherwise we can only sibcall if the function kind is known to be | |
1317 | the same. */ | |
1318 | if (decl && m68k_get_function_kind (decl) == kind) | |
1319 | return true; | |
1320 | ||
1321 | return false; | |
f7e70894 RS |
1322 | } |
1323 | ||
29ca003a RS |
1324 | /* Convert X to a legitimate function call memory reference and return the |
1325 | result. */ | |
a2ef3db7 | 1326 | |
29ca003a RS |
1327 | rtx |
1328 | m68k_legitimize_call_address (rtx x) | |
1329 | { | |
1330 | gcc_assert (MEM_P (x)); | |
1331 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1332 | return x; | |
1333 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1334 | } |
1335 | ||
f7e70894 RS |
1336 | /* Likewise for sibling calls. */ |
1337 | ||
1338 | rtx | |
1339 | m68k_legitimize_sibcall_address (rtx x) | |
1340 | { | |
1341 | gcc_assert (MEM_P (x)); | |
1342 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1343 | return x; | |
1344 | ||
1345 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1346 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1347 | } | |
1348 | ||
64a184e9 RS |
1349 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1350 | floating point version of this sequence (Fdbcc). We also | |
1351 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1352 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1353 | kick those out before we get here. */ | |
64a184e9 | 1354 | |
1d8eaa6b | 1355 | void |
8a4a2253 | 1356 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1357 | { |
64a184e9 RS |
1358 | switch (GET_CODE (operands[3])) |
1359 | { | |
1360 | case EQ: | |
da398bb5 | 1361 | output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); |
e6d98cb0 | 1362 | break; |
64a184e9 RS |
1363 | |
1364 | case NE: | |
da398bb5 | 1365 | output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); |
e6d98cb0 | 1366 | break; |
64a184e9 RS |
1367 | |
1368 | case GT: | |
da398bb5 | 1369 | output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); |
e6d98cb0 | 1370 | break; |
64a184e9 RS |
1371 | |
1372 | case GTU: | |
da398bb5 | 1373 | output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); |
e6d98cb0 | 1374 | break; |
64a184e9 RS |
1375 | |
1376 | case LT: | |
da398bb5 | 1377 | output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); |
e6d98cb0 | 1378 | break; |
64a184e9 RS |
1379 | |
1380 | case LTU: | |
da398bb5 | 1381 | output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); |
e6d98cb0 | 1382 | break; |
64a184e9 RS |
1383 | |
1384 | case GE: | |
da398bb5 | 1385 | output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); |
e6d98cb0 | 1386 | break; |
64a184e9 RS |
1387 | |
1388 | case GEU: | |
da398bb5 | 1389 | output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); |
e6d98cb0 | 1390 | break; |
64a184e9 RS |
1391 | |
1392 | case LE: | |
da398bb5 | 1393 | output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); |
e6d98cb0 | 1394 | break; |
64a184e9 RS |
1395 | |
1396 | case LEU: | |
da398bb5 | 1397 | output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); |
e6d98cb0 | 1398 | break; |
64a184e9 RS |
1399 | |
1400 | default: | |
4761e388 | 1401 | gcc_unreachable (); |
64a184e9 RS |
1402 | } |
1403 | ||
1404 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1405 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1406 | switch (GET_MODE (operands[0])) |
1407 | { | |
1408 | case SImode: | |
da398bb5 | 1409 | output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands); |
64a184e9 RS |
1410 | break; |
1411 | ||
1412 | case HImode: | |
1413 | break; | |
1414 | ||
1415 | default: | |
4761e388 | 1416 | gcc_unreachable (); |
64a184e9 RS |
1417 | } |
1418 | } | |
1419 | ||
5505f548 | 1420 | const char * |
4761e388 | 1421 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1422 | { |
1423 | rtx loperands[7]; | |
d9832fd2 | 1424 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1425 | |
f710504c | 1426 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1427 | CC_STATUS_INIT; |
1428 | ||
d9832fd2 RK |
1429 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1430 | below. Swap the operands and change the op if these requirements | |
1431 | are not fulfilled. */ | |
1432 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1433 | { | |
1434 | rtx tmp = operand1; | |
1435 | ||
1436 | operand1 = operand2; | |
1437 | operand2 = tmp; | |
1438 | op_code = swap_condition (op_code); | |
1439 | } | |
c59c3b1c RK |
1440 | loperands[0] = operand1; |
1441 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1442 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1443 | else |
b72f00af | 1444 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1445 | if (operand2 != const0_rtx) |
1446 | { | |
1447 | loperands[2] = operand2; | |
1448 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1449 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1450 | else |
b72f00af | 1451 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1452 | } |
428511bb | 1453 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1454 | if (operand2 != const0_rtx) |
da398bb5 | 1455 | output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands); |
392582fa | 1456 | else |
4a8c52e0 | 1457 | { |
9425fb04 | 1458 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1459 | output_asm_insn ("tst%.l %0", loperands); |
1460 | else | |
a0a7fbc9 | 1461 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1462 | |
da398bb5 | 1463 | output_asm_insn ("jne %l4", loperands); |
4a8c52e0 | 1464 | |
9425fb04 | 1465 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1466 | output_asm_insn ("tst%.l %1", loperands); |
1467 | else | |
3b4b85c9 | 1468 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1469 | } |
1470 | ||
c59c3b1c | 1471 | loperands[5] = dest; |
3b4b85c9 | 1472 | |
d9832fd2 | 1473 | switch (op_code) |
c59c3b1c RK |
1474 | { |
1475 | case EQ: | |
4977bab6 | 1476 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1477 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1478 | output_asm_insn ("seq %5", loperands); |
1479 | break; | |
1480 | ||
1481 | case NE: | |
4977bab6 | 1482 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1483 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1484 | output_asm_insn ("sne %5", loperands); |
1485 | break; | |
1486 | ||
1487 | case GT: | |
428511bb | 1488 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1489 | output_asm_insn ("shi %5\n\tjra %l6", loperands); |
4977bab6 | 1490 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1491 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1492 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1493 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1494 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1495 | break; |
1496 | ||
1497 | case GTU: | |
4977bab6 | 1498 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1499 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1500 | output_asm_insn ("shi %5", loperands); |
1501 | break; | |
1502 | ||
1503 | case LT: | |
428511bb | 1504 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1505 | output_asm_insn ("scs %5\n\tjra %l6", loperands); |
4977bab6 | 1506 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1507 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1508 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1509 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1510 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1511 | break; |
1512 | ||
1513 | case LTU: | |
4977bab6 | 1514 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1515 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1516 | output_asm_insn ("scs %5", loperands); |
1517 | break; | |
1518 | ||
1519 | case GE: | |
428511bb | 1520 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1521 | output_asm_insn ("scc %5\n\tjra %l6", loperands); |
4977bab6 | 1522 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1523 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1524 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1525 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1526 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1527 | break; |
1528 | ||
1529 | case GEU: | |
4977bab6 | 1530 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1531 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1532 | output_asm_insn ("scc %5", loperands); |
1533 | break; | |
1534 | ||
1535 | case LE: | |
428511bb | 1536 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1537 | output_asm_insn ("sls %5\n\tjra %l6", loperands); |
4977bab6 | 1538 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1539 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1540 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1541 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1542 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1543 | break; |
1544 | ||
1545 | case LEU: | |
4977bab6 | 1546 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1547 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1548 | output_asm_insn ("sls %5", loperands); |
1549 | break; | |
1550 | ||
1551 | default: | |
4761e388 | 1552 | gcc_unreachable (); |
c59c3b1c RK |
1553 | } |
1554 | return ""; | |
1555 | } | |
1556 | ||
5505f548 | 1557 | const char * |
8a4a2253 | 1558 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1559 | { |
1560 | operands[0] = countop; | |
1561 | operands[1] = dataop; | |
1562 | ||
1563 | if (GET_CODE (countop) == CONST_INT) | |
1564 | { | |
1565 | register int count = INTVAL (countop); | |
1566 | /* If COUNT is bigger than size of storage unit in use, | |
1567 | advance to the containing unit of same size. */ | |
1568 | if (count > signpos) | |
1569 | { | |
1570 | int offset = (count & ~signpos) / 8; | |
1571 | count = count & signpos; | |
b72f00af | 1572 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1573 | } |
1574 | if (count == signpos) | |
1575 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1576 | else | |
1577 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1578 | ||
1579 | /* These three statements used to use next_insns_test_no... | |
1580 | but it appears that this should do the same job. */ | |
1581 | if (count == 31 | |
1582 | && next_insn_tests_no_inequality (insn)) | |
1583 | return "tst%.l %1"; | |
1584 | if (count == 15 | |
1585 | && next_insn_tests_no_inequality (insn)) | |
1586 | return "tst%.w %1"; | |
1587 | if (count == 7 | |
1588 | && next_insn_tests_no_inequality (insn)) | |
1589 | return "tst%.b %1"; | |
5083912d PDM |
1590 | /* Try to use `movew to ccr' followed by the appropriate branch insn. |
1591 | On some m68k variants unfortunately that's slower than btst. | |
1592 | On 68000 and higher, that should also work for all HImode operands. */ | |
1593 | if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) | |
1594 | { | |
1595 | if (count == 3 && DATA_REG_P (operands[1]) | |
1596 | && next_insn_tests_no_inequality (insn)) | |
1597 | { | |
1598 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW; | |
1599 | return "move%.w %1,%%ccr"; | |
1600 | } | |
1601 | if (count == 2 && DATA_REG_P (operands[1]) | |
1602 | && next_insn_tests_no_inequality (insn)) | |
1603 | { | |
1604 | cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW; | |
1605 | return "move%.w %1,%%ccr"; | |
1606 | } | |
1607 | /* count == 1 followed by bvc/bvs and | |
1608 | count == 0 followed by bcc/bcs are also possible, but need | |
1609 | m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ | |
1610 | } | |
79e68feb RS |
1611 | |
1612 | cc_status.flags = CC_NOT_NEGATIVE; | |
1613 | } | |
1614 | return "btst %0,%1"; | |
1615 | } | |
79e68feb | 1616 | \f |
fc2241eb RS |
1617 | /* Return true if X is a legitimate base register. STRICT_P says |
1618 | whether we need strict checking. */ | |
1619 | ||
1620 | bool | |
1621 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
1622 | { | |
1623 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
1624 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1625 | x = SUBREG_REG (x); | |
1626 | ||
1627 | return (REG_P (x) | |
1628 | && (strict_p | |
1629 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
bf32249e | 1630 | : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1631 | } |
1632 | ||
1633 | /* Return true if X is a legitimate index register. STRICT_P says | |
1634 | whether we need strict checking. */ | |
1635 | ||
1636 | bool | |
1637 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
1638 | { | |
1639 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1640 | x = SUBREG_REG (x); | |
1641 | ||
1642 | return (REG_P (x) | |
1643 | && (strict_p | |
1644 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
bf32249e | 1645 | : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1646 | } |
1647 | ||
1648 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
1649 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
1650 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
1651 | ||
1652 | static bool | |
1653 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
1654 | { | |
1655 | int scale; | |
1656 | ||
1657 | /* Check for a scale factor. */ | |
1658 | scale = 1; | |
1659 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
1660 | && GET_CODE (x) == MULT | |
1661 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1662 | && (INTVAL (XEXP (x, 1)) == 2 | |
1663 | || INTVAL (XEXP (x, 1)) == 4 | |
1664 | || (INTVAL (XEXP (x, 1)) == 8 | |
1665 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
1666 | { | |
1667 | scale = INTVAL (XEXP (x, 1)); | |
1668 | x = XEXP (x, 0); | |
1669 | } | |
1670 | ||
1671 | /* Check for a word extension. */ | |
1672 | if (!TARGET_COLDFIRE | |
1673 | && GET_CODE (x) == SIGN_EXTEND | |
1674 | && GET_MODE (XEXP (x, 0)) == HImode) | |
1675 | x = XEXP (x, 0); | |
1676 | ||
1677 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
1678 | { | |
1679 | address->scale = scale; | |
1680 | address->index = x; | |
1681 | return true; | |
1682 | } | |
1683 | ||
1684 | return false; | |
1685 | } | |
1686 | ||
7ffb5e78 RS |
1687 | /* Return true if X is an illegitimate symbolic constant. */ |
1688 | ||
1689 | bool | |
1690 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
1691 | { | |
1692 | rtx base, offset; | |
1693 | ||
1694 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1695 | { | |
1696 | split_const (x, &base, &offset); | |
1697 | if (GET_CODE (base) == SYMBOL_REF | |
1698 | && !offset_within_block_p (base, INTVAL (offset))) | |
1699 | return true; | |
1700 | } | |
1701 | return false; | |
1702 | } | |
1703 | ||
fc2241eb RS |
1704 | /* Return true if X is a legitimate constant address that can reach |
1705 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
1706 | strict checking. */ | |
1707 | ||
1708 | static bool | |
1709 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
1710 | { | |
1711 | rtx base, offset; | |
1712 | ||
1713 | if (!CONSTANT_ADDRESS_P (x)) | |
1714 | return false; | |
1715 | ||
1716 | if (flag_pic | |
1717 | && !(strict_p && TARGET_PCREL) | |
1718 | && symbolic_operand (x, VOIDmode)) | |
1719 | return false; | |
1720 | ||
1721 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
1722 | { | |
1723 | split_const (x, &base, &offset); | |
1724 | if (GET_CODE (base) == SYMBOL_REF | |
1725 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
1726 | return false; | |
1727 | } | |
1728 | ||
1729 | return true; | |
1730 | } | |
1731 | ||
1732 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
1733 | labels will become jump tables. */ | |
1734 | ||
1735 | static bool | |
1736 | m68k_jump_table_ref_p (rtx x) | |
1737 | { | |
1738 | if (GET_CODE (x) != LABEL_REF) | |
1739 | return false; | |
1740 | ||
1741 | x = XEXP (x, 0); | |
1742 | if (!NEXT_INSN (x) && !PREV_INSN (x)) | |
1743 | return true; | |
1744 | ||
1745 | x = next_nonnote_insn (x); | |
1746 | return x && JUMP_TABLE_DATA_P (x); | |
1747 | } | |
1748 | ||
1749 | /* Return true if X is a legitimate address for values of mode MODE. | |
1750 | STRICT_P says whether strict checking is needed. If the address | |
1751 | is valid, describe its components in *ADDRESS. */ | |
1752 | ||
1753 | static bool | |
1754 | m68k_decompose_address (enum machine_mode mode, rtx x, | |
1755 | bool strict_p, struct m68k_address *address) | |
1756 | { | |
1757 | unsigned int reach; | |
1758 | ||
1759 | memset (address, 0, sizeof (*address)); | |
1760 | ||
1761 | if (mode == BLKmode) | |
1762 | reach = 1; | |
1763 | else | |
1764 | reach = GET_MODE_SIZE (mode); | |
1765 | ||
1766 | /* Check for (An) (mode 2). */ | |
1767 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1768 | { | |
1769 | address->base = x; | |
1770 | return true; | |
1771 | } | |
1772 | ||
1773 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
1774 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
1775 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1776 | { | |
1777 | address->code = GET_CODE (x); | |
1778 | address->base = XEXP (x, 0); | |
1779 | return true; | |
1780 | } | |
1781 | ||
1782 | /* Check for (d16,An) (mode 5). */ | |
1783 | if (GET_CODE (x) == PLUS | |
1784 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1785 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
1786 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1787 | { | |
1788 | address->base = XEXP (x, 0); | |
1789 | address->offset = XEXP (x, 1); | |
1790 | return true; | |
1791 | } | |
1792 | ||
1793 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
1794 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
1795 | addresses. */ | |
1796 | if (flag_pic | |
1797 | && GET_CODE (x) == PLUS | |
1798 | && XEXP (x, 0) == pic_offset_table_rtx | |
1799 | && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF | |
1800 | || GET_CODE (XEXP (x, 1)) == LABEL_REF)) | |
1801 | { | |
1802 | address->base = XEXP (x, 0); | |
1803 | address->offset = XEXP (x, 1); | |
1804 | return true; | |
1805 | } | |
1806 | ||
1807 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
1808 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1809 | return false; | |
1810 | ||
1811 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
1812 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
1813 | All these modes are variations of mode 7. */ | |
1814 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
1815 | { | |
1816 | address->offset = x; | |
1817 | return true; | |
1818 | } | |
1819 | ||
1820 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
1821 | tablejumps. | |
1822 | ||
1823 | ??? do_tablejump creates these addresses before placing the target | |
1824 | label, so we have to assume that unplaced labels are jump table | |
1825 | references. It seems unlikely that we would ever generate indexed | |
1826 | accesses to unplaced labels in other cases. */ | |
1827 | if (GET_CODE (x) == PLUS | |
1828 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
1829 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1830 | { | |
1831 | address->offset = XEXP (x, 1); | |
1832 | return true; | |
1833 | } | |
1834 | ||
1835 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
1836 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
1837 | ||
1838 | if (TARGET_68020) | |
1839 | { | |
1840 | /* Check for a nonzero base displacement. */ | |
1841 | if (GET_CODE (x) == PLUS | |
1842 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
1843 | { | |
1844 | address->offset = XEXP (x, 1); | |
1845 | x = XEXP (x, 0); | |
1846 | } | |
1847 | ||
1848 | /* Check for a suppressed index register. */ | |
1849 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1850 | { | |
1851 | address->base = x; | |
1852 | return true; | |
1853 | } | |
1854 | ||
1855 | /* Check for a suppressed base register. Do not allow this case | |
1856 | for non-symbolic offsets as it effectively gives gcc freedom | |
1857 | to treat data registers as base registers, which can generate | |
1858 | worse code. */ | |
1859 | if (address->offset | |
1860 | && symbolic_operand (address->offset, VOIDmode) | |
1861 | && m68k_decompose_index (x, strict_p, address)) | |
1862 | return true; | |
1863 | } | |
1864 | else | |
1865 | { | |
1866 | /* Check for a nonzero base displacement. */ | |
1867 | if (GET_CODE (x) == PLUS | |
1868 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1869 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
1870 | { | |
1871 | address->offset = XEXP (x, 1); | |
1872 | x = XEXP (x, 0); | |
1873 | } | |
1874 | } | |
1875 | ||
1876 | /* We now expect the sum of a base and an index. */ | |
1877 | if (GET_CODE (x) == PLUS) | |
1878 | { | |
1879 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
1880 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
1881 | { | |
1882 | address->base = XEXP (x, 0); | |
1883 | return true; | |
1884 | } | |
1885 | ||
1886 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
1887 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1888 | { | |
1889 | address->base = XEXP (x, 1); | |
1890 | return true; | |
1891 | } | |
1892 | } | |
1893 | return false; | |
1894 | } | |
1895 | ||
1896 | /* Return true if X is a legitimate address for values of mode MODE. | |
1897 | STRICT_P says whether strict checking is needed. */ | |
1898 | ||
1899 | bool | |
1900 | m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
1901 | { | |
1902 | struct m68k_address address; | |
1903 | ||
1904 | return m68k_decompose_address (mode, x, strict_p, &address); | |
1905 | } | |
1906 | ||
1907 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
1908 | Apply strict checking if called during or after reload. */ | |
1909 | ||
1910 | static bool | |
1911 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
1912 | { | |
1913 | return (MEM_P (x) | |
1914 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
1915 | reload_in_progress || reload_completed, | |
1916 | address)); | |
1917 | } | |
1918 | ||
1919 | /* Return true if X matches the 'Q' constraint. It must be a memory | |
1920 | with a base address and no constant offset or index. */ | |
1921 | ||
1922 | bool | |
1923 | m68k_matches_q_p (rtx x) | |
1924 | { | |
1925 | struct m68k_address address; | |
1926 | ||
1927 | return (m68k_legitimate_mem_p (x, &address) | |
1928 | && address.code == UNKNOWN | |
1929 | && address.base | |
1930 | && !address.offset | |
1931 | && !address.index); | |
1932 | } | |
1933 | ||
1934 | /* Return true if X matches the 'U' constraint. It must be a base address | |
1935 | with a constant offset and no index. */ | |
1936 | ||
1937 | bool | |
1938 | m68k_matches_u_p (rtx x) | |
1939 | { | |
1940 | struct m68k_address address; | |
1941 | ||
1942 | return (m68k_legitimate_mem_p (x, &address) | |
1943 | && address.code == UNKNOWN | |
1944 | && address.base | |
1945 | && address.offset | |
1946 | && !address.index); | |
1947 | } | |
1948 | ||
79e68feb RS |
1949 | /* Legitimize PIC addresses. If the address is already |
1950 | position-independent, we return ORIG. Newly generated | |
1951 | position-independent addresses go to REG. If we need more | |
1952 | than one register, we lose. | |
1953 | ||
1954 | An address is legitimized by making an indirect reference | |
1955 | through the Global Offset Table with the name of the symbol | |
1956 | used as an offset. | |
1957 | ||
1958 | The assembler and linker are responsible for placing the | |
1959 | address of the symbol in the GOT. The function prologue | |
1960 | is responsible for initializing a5 to the starting address | |
1961 | of the GOT. | |
1962 | ||
1963 | The assembler is also responsible for translating a symbol name | |
1964 | into a constant displacement from the start of the GOT. | |
1965 | ||
1966 | A quick example may make things a little clearer: | |
1967 | ||
1968 | When not generating PIC code to store the value 12345 into _foo | |
1969 | we would generate the following code: | |
1970 | ||
1971 | movel #12345, _foo | |
1972 | ||
1973 | When generating PIC two transformations are made. First, the compiler | |
1974 | loads the address of foo into a register. So the first transformation makes: | |
1975 | ||
1976 | lea _foo, a0 | |
1977 | movel #12345, a0@ | |
1978 | ||
1979 | The code in movsi will intercept the lea instruction and call this | |
1980 | routine which will transform the instructions into: | |
1981 | ||
1982 | movel a5@(_foo:w), a0 | |
1983 | movel #12345, a0@ | |
1984 | ||
1985 | ||
1986 | That (in a nutshell) is how *all* symbol and label references are | |
1987 | handled. */ | |
1988 | ||
1989 | rtx | |
8a4a2253 BI |
1990 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1991 | rtx reg) | |
79e68feb RS |
1992 | { |
1993 | rtx pic_ref = orig; | |
1994 | ||
1995 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1996 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1997 | { | |
4761e388 | 1998 | gcc_assert (reg); |
79e68feb | 1999 | |
1d8eaa6b AS |
2000 | pic_ref = gen_rtx_MEM (Pmode, |
2001 | gen_rtx_PLUS (Pmode, | |
2002 | pic_offset_table_rtx, orig)); | |
79e68feb | 2003 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 2004 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
2005 | emit_move_insn (reg, pic_ref); |
2006 | return reg; | |
2007 | } | |
2008 | else if (GET_CODE (orig) == CONST) | |
2009 | { | |
1d8eaa6b | 2010 | rtx base; |
79e68feb | 2011 | |
b2e08ed4 | 2012 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
2013 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2014 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2015 | return orig; | |
2016 | ||
4761e388 | 2017 | gcc_assert (reg); |
79e68feb RS |
2018 | |
2019 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
2020 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
2021 | ||
2022 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2023 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2024 | base == reg ? 0 : reg); | |
79e68feb RS |
2025 | |
2026 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 2027 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 2028 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
2029 | /* Likewise, should we set special REG_NOTEs here? */ |
2030 | } | |
2031 | return pic_ref; | |
2032 | } | |
2033 | ||
2034 | \f | |
0ce6f9fb | 2035 | |
a0a7fbc9 | 2036 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 2037 | |
bda2a571 RS |
2038 | /* Return the type of move that should be used for integer I. */ |
2039 | ||
c47b0cb4 MK |
2040 | M68K_CONST_METHOD |
2041 | m68k_const_method (HOST_WIDE_INT i) | |
0ce6f9fb | 2042 | { |
0ce6f9fb RK |
2043 | unsigned u; |
2044 | ||
6910dd70 | 2045 | if (USE_MOVQ (i)) |
0ce6f9fb | 2046 | return MOVQ; |
24092242 | 2047 | |
c16eadc7 | 2048 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 2049 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 2050 | if (!TARGET_COLDFIRE) |
24092242 RK |
2051 | { |
2052 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 2053 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
2054 | if (USE_MOVQ (i ^ 0xff)) |
2055 | return NOTB; | |
2056 | /* Likewise, try with not.w */ | |
2057 | if (USE_MOVQ (i ^ 0xffff)) | |
2058 | return NOTW; | |
2059 | /* This is the only value where neg.w is useful */ | |
2060 | if (i == -65408) | |
2061 | return NEGW; | |
24092242 | 2062 | } |
28bad6d1 | 2063 | |
5e04daf3 PB |
2064 | /* Try also with swap. */ |
2065 | u = i; | |
2066 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2067 | return SWAP; | |
2068 | ||
986e74d5 | 2069 | if (TARGET_ISAB) |
28bad6d1 | 2070 | { |
72edf146 | 2071 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
2072 | if (i >= 0 && i <= 65535) |
2073 | return MVZ; | |
2074 | if (i >= -32768 && i <= 32767) | |
2075 | return MVS; | |
2076 | } | |
2077 | ||
0ce6f9fb RK |
2078 | /* Otherwise, use move.l */ |
2079 | return MOVL; | |
2080 | } | |
2081 | ||
bda2a571 RS |
2082 | /* Return the cost of moving constant I into a data register. */ |
2083 | ||
3c50106f | 2084 | static int |
bda2a571 | 2085 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 2086 | { |
c47b0cb4 | 2087 | switch (m68k_const_method (i)) |
0ce6f9fb | 2088 | { |
a0a7fbc9 AS |
2089 | case MOVQ: |
2090 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2091 | return 0; | |
2092 | case MVZ: | |
2093 | case MVS: | |
2094 | case NOTB: | |
2095 | case NOTW: | |
2096 | case NEGW: | |
2097 | case SWAP: | |
2098 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2099 | return 1; | |
2100 | case MOVL: | |
2101 | return 2; | |
2102 | default: | |
2103 | gcc_unreachable (); | |
0ce6f9fb RK |
2104 | } |
2105 | } | |
2106 | ||
3c50106f | 2107 | static bool |
8a4a2253 | 2108 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
2109 | { |
2110 | switch (code) | |
2111 | { | |
2112 | case CONST_INT: | |
2113 | /* Constant zero is super cheap due to clr instruction. */ | |
2114 | if (x == const0_rtx) | |
2115 | *total = 0; | |
2116 | else | |
bda2a571 | 2117 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
2118 | return true; |
2119 | ||
2120 | case CONST: | |
2121 | case LABEL_REF: | |
2122 | case SYMBOL_REF: | |
2123 | *total = 3; | |
2124 | return true; | |
2125 | ||
2126 | case CONST_DOUBLE: | |
2127 | /* Make 0.0 cheaper than other floating constants to | |
2128 | encourage creating tstsf and tstdf insns. */ | |
2129 | if (outer_code == COMPARE | |
2130 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
2131 | *total = 4; | |
2132 | else | |
2133 | *total = 5; | |
2134 | return true; | |
2135 | ||
2136 | /* These are vaguely right for a 68020. */ | |
2137 | /* The costs for long multiply have been adjusted to work properly | |
2138 | in synth_mult on the 68020, relative to an average of the time | |
2139 | for add and the time for shift, taking away a little more because | |
2140 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
2141 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
2142 | terms. */ | |
fe95f2f7 JB |
2143 | #define MULL_COST \ |
2144 | (TUNE_68060 ? 2 \ | |
2145 | : TUNE_68040 ? 5 \ | |
2146 | : TUNE_CFV2 ? 10 \ | |
2147 | : TARGET_COLDFIRE ? 3 : 13) | |
2148 | ||
2149 | #define MULW_COST \ | |
2150 | (TUNE_68060 ? 2 \ | |
2151 | : TUNE_68040 ? 3 \ | |
2152 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
2153 | : TARGET_COLDFIRE ? 2 : 8) | |
2154 | ||
2155 | #define DIVW_COST \ | |
2156 | (TARGET_CF_HWDIV ? 11 \ | |
2157 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
2158 | |
2159 | case PLUS: | |
2160 | /* An lea costs about three times as much as a simple add. */ | |
2161 | if (GET_MODE (x) == SImode | |
2162 | && GET_CODE (XEXP (x, 1)) == REG | |
2163 | && GET_CODE (XEXP (x, 0)) == MULT | |
2164 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2165 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2166 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
2167 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
2168 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
2169 | { |
2170 | /* lea an@(dx:l:i),am */ | |
2171 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
2172 | return true; | |
2173 | } | |
3c50106f RH |
2174 | return false; |
2175 | ||
2176 | case ASHIFT: | |
2177 | case ASHIFTRT: | |
2178 | case LSHIFTRT: | |
fe95f2f7 | 2179 | if (TUNE_68060) |
3c50106f RH |
2180 | { |
2181 | *total = COSTS_N_INSNS(1); | |
2182 | return true; | |
2183 | } | |
fe95f2f7 | 2184 | if (TUNE_68000_10) |
3c50106f RH |
2185 | { |
2186 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2187 | { | |
2188 | if (INTVAL (XEXP (x, 1)) < 16) | |
2189 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
2190 | else | |
2191 | /* We're using clrw + swap for these cases. */ | |
2192 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
2193 | } | |
2194 | else | |
a0a7fbc9 | 2195 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
2196 | return true; |
2197 | } | |
2198 | /* A shift by a big integer takes an extra instruction. */ | |
2199 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2200 | && (INTVAL (XEXP (x, 1)) == 16)) | |
2201 | { | |
2202 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
2203 | return true; | |
2204 | } | |
2205 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2206 | && !(INTVAL (XEXP (x, 1)) > 0 | |
2207 | && INTVAL (XEXP (x, 1)) <= 8)) | |
2208 | { | |
eb849993 | 2209 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
2210 | return true; |
2211 | } | |
2212 | return false; | |
2213 | ||
2214 | case MULT: | |
2215 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2216 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
2217 | && GET_MODE (x) == SImode) | |
2218 | *total = COSTS_N_INSNS (MULW_COST); | |
2219 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2220 | *total = COSTS_N_INSNS (MULW_COST); | |
2221 | else | |
2222 | *total = COSTS_N_INSNS (MULL_COST); | |
2223 | return true; | |
2224 | ||
2225 | case DIV: | |
2226 | case UDIV: | |
2227 | case MOD: | |
2228 | case UMOD: | |
2229 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2230 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
2231 | else if (TARGET_CF_HWDIV) |
2232 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
2233 | else |
2234 | *total = COSTS_N_INSNS (43); /* div.l */ | |
2235 | return true; | |
2236 | ||
2237 | default: | |
2238 | return false; | |
2239 | } | |
2240 | } | |
2241 | ||
88512ba0 | 2242 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
2243 | OPERANDS[0]. */ |
2244 | ||
2245 | static const char * | |
8a4a2253 | 2246 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 2247 | { |
bda2a571 | 2248 | HOST_WIDE_INT i; |
0ce6f9fb RK |
2249 | |
2250 | i = INTVAL (operands[1]); | |
c47b0cb4 | 2251 | switch (m68k_const_method (i)) |
0ce6f9fb | 2252 | { |
28bad6d1 | 2253 | case MVZ: |
28bad6d1 | 2254 | return "mvzw %1,%0"; |
1cbae84f PB |
2255 | case MVS: |
2256 | return "mvsw %1,%0"; | |
a0a7fbc9 | 2257 | case MOVQ: |
0ce6f9fb | 2258 | return "moveq %1,%0"; |
a0a7fbc9 | 2259 | case NOTB: |
66e07510 | 2260 | CC_STATUS_INIT; |
1d8eaa6b | 2261 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 2262 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 2263 | case NOTW: |
66e07510 | 2264 | CC_STATUS_INIT; |
1d8eaa6b | 2265 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 2266 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 2267 | case NEGW: |
66e07510 | 2268 | CC_STATUS_INIT; |
3b4b85c9 | 2269 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 2270 | case SWAP: |
0ce6f9fb RK |
2271 | { |
2272 | unsigned u = i; | |
2273 | ||
1d8eaa6b | 2274 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 2275 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 2276 | } |
a0a7fbc9 | 2277 | case MOVL: |
bda2a571 | 2278 | return "move%.l %1,%0"; |
a0a7fbc9 | 2279 | default: |
bda2a571 | 2280 | gcc_unreachable (); |
0ce6f9fb RK |
2281 | } |
2282 | } | |
2283 | ||
bda2a571 | 2284 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 2285 | |
bda2a571 RS |
2286 | bool |
2287 | valid_mov3q_const (HOST_WIDE_INT i) | |
2288 | { | |
2289 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
2290 | } |
2291 | ||
bda2a571 RS |
2292 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
2293 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 2294 | |
bda2a571 | 2295 | static const char * |
8a4a2253 | 2296 | output_move_simode_const (rtx *operands) |
02ed0c07 | 2297 | { |
bda2a571 RS |
2298 | rtx dest; |
2299 | HOST_WIDE_INT src; | |
2300 | ||
2301 | dest = operands[0]; | |
2302 | src = INTVAL (operands[1]); | |
2303 | if (src == 0 | |
2304 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
2305 | /* clr insns on 68000 read before writing. */ |
2306 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 2307 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 2308 | return "clr%.l %0"; |
bda2a571 | 2309 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 2310 | return "mov3q%.l %1,%0"; |
bda2a571 | 2311 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 2312 | return "sub%.l %0,%0"; |
bda2a571 | 2313 | else if (DATA_REG_P (dest)) |
02ed0c07 | 2314 | return output_move_const_into_data_reg (operands); |
bda2a571 | 2315 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 2316 | { |
bda2a571 | 2317 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2318 | return "mov3q%.l %1,%0"; |
2319 | return "move%.w %1,%0"; | |
2320 | } | |
bda2a571 RS |
2321 | else if (MEM_P (dest) |
2322 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2323 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
2324 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 2325 | { |
bda2a571 | 2326 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2327 | return "mov3q%.l %1,%-"; |
2328 | return "pea %a1"; | |
2329 | } | |
02ed0c07 RK |
2330 | return "move%.l %1,%0"; |
2331 | } | |
2332 | ||
5505f548 | 2333 | const char * |
8a4a2253 | 2334 | output_move_simode (rtx *operands) |
f4e80198 RK |
2335 | { |
2336 | if (GET_CODE (operands[1]) == CONST_INT) | |
2337 | return output_move_simode_const (operands); | |
2338 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2339 | || GET_CODE (operands[1]) == CONST) | |
2340 | && push_operand (operands[0], SImode)) | |
2341 | return "pea %a1"; | |
2342 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2343 | || GET_CODE (operands[1]) == CONST) | |
2344 | && ADDRESS_REG_P (operands[0])) | |
2345 | return "lea %a1,%0"; | |
2346 | return "move%.l %1,%0"; | |
2347 | } | |
2348 | ||
5505f548 | 2349 | const char * |
8a4a2253 | 2350 | output_move_himode (rtx *operands) |
f4e80198 RK |
2351 | { |
2352 | if (GET_CODE (operands[1]) == CONST_INT) | |
2353 | { | |
2354 | if (operands[1] == const0_rtx | |
2355 | && (DATA_REG_P (operands[0]) | |
2356 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2357 | /* clr insns on 68000 read before writing. */ |
2358 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2359 | || !(GET_CODE (operands[0]) == MEM |
2360 | && MEM_VOLATILE_P (operands[0])))) | |
2361 | return "clr%.w %0"; | |
38198304 AS |
2362 | else if (operands[1] == const0_rtx |
2363 | && ADDRESS_REG_P (operands[0])) | |
2364 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2365 | else if (DATA_REG_P (operands[0]) |
2366 | && INTVAL (operands[1]) < 128 | |
2367 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2368 | return "moveq %1,%0"; |
f4e80198 RK |
2369 | else if (INTVAL (operands[1]) < 0x8000 |
2370 | && INTVAL (operands[1]) >= -0x8000) | |
2371 | return "move%.w %1,%0"; | |
2372 | } | |
2373 | else if (CONSTANT_P (operands[1])) | |
2374 | return "move%.l %1,%0"; | |
f4e80198 RK |
2375 | return "move%.w %1,%0"; |
2376 | } | |
2377 | ||
5505f548 | 2378 | const char * |
8a4a2253 | 2379 | output_move_qimode (rtx *operands) |
f4e80198 | 2380 | { |
102701ff | 2381 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2382 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2383 | |
a0a7fbc9 | 2384 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2385 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2386 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2387 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2388 | && ! ADDRESS_REG_P (operands[1]) | |
2389 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2390 | |
3197c489 | 2391 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2392 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2393 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2394 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2395 | { | |
2396 | if (operands[1] == const0_rtx) | |
2397 | return "clr%.b %0"; | |
9425fb04 | 2398 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2399 | && GET_CODE (operands[1]) == CONST_INT |
2400 | && (INTVAL (operands[1]) & 255) == 255) | |
2401 | { | |
2402 | CC_STATUS_INIT; | |
2403 | return "st %0"; | |
2404 | } | |
2405 | } | |
2406 | if (GET_CODE (operands[1]) == CONST_INT | |
2407 | && DATA_REG_P (operands[0]) | |
2408 | && INTVAL (operands[1]) < 128 | |
2409 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2410 | return "moveq %1,%0"; |
38198304 AS |
2411 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2412 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2413 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2414 | return "move%.l %1,%0"; | |
c16eadc7 | 2415 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2416 | from address registers. */ |
2417 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2418 | return "move%.w %1,%0"; |
2419 | return "move%.b %1,%0"; | |
2420 | } | |
2421 | ||
5505f548 | 2422 | const char * |
8a4a2253 | 2423 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2424 | { |
2425 | if (operands[1] == const0_rtx | |
3197c489 RS |
2426 | /* clr insns on 68000 read before writing. */ |
2427 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2428 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2429 | return "clr%.w %0"; | |
2430 | return "move%.w %1,%0"; | |
2431 | } | |
2432 | ||
5505f548 | 2433 | const char * |
8a4a2253 | 2434 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2435 | { |
2436 | if (operands[1] == const0_rtx | |
3197c489 RS |
2437 | /* clr insns on 68000 read before writing. */ |
2438 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2439 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2440 | return "clr%.b %0"; | |
2441 | return "move%.b %1,%0"; | |
2442 | } | |
2443 | ||
79e68feb RS |
2444 | /* Return the best assembler insn template |
2445 | for moving operands[1] into operands[0] as a fullword. */ | |
2446 | ||
5505f548 | 2447 | static const char * |
8a4a2253 | 2448 | singlemove_string (rtx *operands) |
79e68feb | 2449 | { |
02ed0c07 RK |
2450 | if (GET_CODE (operands[1]) == CONST_INT) |
2451 | return output_move_simode_const (operands); | |
2452 | return "move%.l %1,%0"; | |
79e68feb RS |
2453 | } |
2454 | ||
2505bc97 | 2455 | |
c47b0cb4 MK |
2456 | /* Output assembler or rtl code to perform a doubleword move insn |
2457 | with operands OPERANDS. | |
2458 | Pointers to 3 helper functions should be specified: | |
2459 | HANDLE_REG_ADJUST to adjust a register by a small value, | |
2460 | HANDLE_COMPADR to compute an address and | |
2461 | HANDLE_MOVSI to move 4 bytes. */ | |
79e68feb | 2462 | |
c47b0cb4 MK |
2463 | static void |
2464 | handle_move_double (rtx operands[2], | |
2465 | void (*handle_reg_adjust) (rtx, int), | |
2466 | void (*handle_compadr) (rtx [2]), | |
2467 | void (*handle_movsi) (rtx [2])) | |
79e68feb | 2468 | { |
2505bc97 RS |
2469 | enum |
2470 | { | |
2471 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2472 | } optype0, optype1; | |
79e68feb | 2473 | rtx latehalf[2]; |
2505bc97 | 2474 | rtx middlehalf[2]; |
7f98eeb6 | 2475 | rtx xops[2]; |
79e68feb | 2476 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2477 | int dest_overlapped_low = 0; |
184916bc | 2478 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2479 | |
2480 | middlehalf[0] = 0; | |
2481 | middlehalf[1] = 0; | |
79e68feb RS |
2482 | |
2483 | /* First classify both operands. */ | |
2484 | ||
2485 | if (REG_P (operands[0])) | |
2486 | optype0 = REGOP; | |
2487 | else if (offsettable_memref_p (operands[0])) | |
2488 | optype0 = OFFSOP; | |
2489 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2490 | optype0 = POPOP; | |
2491 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2492 | optype0 = PUSHOP; | |
2493 | else if (GET_CODE (operands[0]) == MEM) | |
2494 | optype0 = MEMOP; | |
2495 | else | |
2496 | optype0 = RNDOP; | |
2497 | ||
2498 | if (REG_P (operands[1])) | |
2499 | optype1 = REGOP; | |
2500 | else if (CONSTANT_P (operands[1])) | |
2501 | optype1 = CNSTOP; | |
2502 | else if (offsettable_memref_p (operands[1])) | |
2503 | optype1 = OFFSOP; | |
2504 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2505 | optype1 = POPOP; | |
2506 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2507 | optype1 = PUSHOP; | |
2508 | else if (GET_CODE (operands[1]) == MEM) | |
2509 | optype1 = MEMOP; | |
2510 | else | |
2511 | optype1 = RNDOP; | |
2512 | ||
4761e388 NS |
2513 | /* Check for the cases that the operand constraints are not supposed |
2514 | to allow to happen. Generating code for these cases is | |
2515 | painful. */ | |
2516 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2517 | |
2518 | /* If one operand is decrementing and one is incrementing | |
2519 | decrement the former register explicitly | |
2520 | and change that operand into ordinary indexing. */ | |
2521 | ||
2522 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2523 | { | |
2524 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
c47b0cb4 MK |
2525 | |
2526 | handle_reg_adjust (operands[0], -size); | |
2527 | ||
2505bc97 | 2528 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2529 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2530 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2531 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2532 | else |
1d8eaa6b | 2533 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2534 | optype0 = OFFSOP; |
2535 | } | |
2536 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2537 | { | |
2538 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
c47b0cb4 MK |
2539 | |
2540 | handle_reg_adjust (operands[1], -size); | |
2541 | ||
2505bc97 | 2542 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2543 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2544 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2545 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2546 | else |
1d8eaa6b | 2547 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2548 | optype1 = OFFSOP; |
2549 | } | |
2550 | ||
2551 | /* If an operand is an unoffsettable memory ref, find a register | |
2552 | we can increment temporarily to make it refer to the second word. */ | |
2553 | ||
2554 | if (optype0 == MEMOP) | |
2555 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2556 | ||
2557 | if (optype1 == MEMOP) | |
2558 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2559 | ||
2560 | /* Ok, we can do one word at a time. | |
2561 | Normally we do the low-numbered word first, | |
2562 | but if either operand is autodecrementing then we | |
2563 | do the high-numbered word first. | |
2564 | ||
2565 | In either case, set up in LATEHALF the operands to use | |
2566 | for the high-numbered word and in some cases alter the | |
2567 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2568 | ||
2505bc97 RS |
2569 | if (size == 12) |
2570 | { | |
2571 | if (optype0 == REGOP) | |
2572 | { | |
1d8eaa6b AS |
2573 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2574 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2575 | } |
2576 | else if (optype0 == OFFSOP) | |
2577 | { | |
b72f00af RK |
2578 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2579 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2580 | } |
2581 | else | |
2582 | { | |
c47b0cb4 MK |
2583 | middlehalf[0] = adjust_address (operands[0], SImode, 0); |
2584 | latehalf[0] = adjust_address (operands[0], SImode, 0); | |
2505bc97 RS |
2585 | } |
2586 | ||
2587 | if (optype1 == REGOP) | |
2588 | { | |
1d8eaa6b AS |
2589 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2590 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2591 | } |
2592 | else if (optype1 == OFFSOP) | |
2593 | { | |
b72f00af RK |
2594 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2595 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2596 | } |
2597 | else if (optype1 == CNSTOP) | |
2598 | { | |
2599 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2600 | { | |
2601 | REAL_VALUE_TYPE r; | |
2602 | long l[3]; | |
2603 | ||
2604 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2605 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2606 | operands[1] = GEN_INT (l[0]); | |
2607 | middlehalf[1] = GEN_INT (l[1]); | |
2608 | latehalf[1] = GEN_INT (l[2]); | |
2609 | } | |
4761e388 | 2610 | else |
2505bc97 | 2611 | { |
4761e388 NS |
2612 | /* No non-CONST_DOUBLE constant should ever appear |
2613 | here. */ | |
2614 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2615 | } |
2616 | } | |
2617 | else | |
2618 | { | |
c47b0cb4 MK |
2619 | middlehalf[1] = adjust_address (operands[1], SImode, 0); |
2620 | latehalf[1] = adjust_address (operands[1], SImode, 0); | |
2505bc97 RS |
2621 | } |
2622 | } | |
79e68feb | 2623 | else |
2505bc97 RS |
2624 | /* size is not 12: */ |
2625 | { | |
2626 | if (optype0 == REGOP) | |
1d8eaa6b | 2627 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2628 | else if (optype0 == OFFSOP) |
b72f00af | 2629 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 | 2630 | else |
c47b0cb4 | 2631 | latehalf[0] = adjust_address (operands[0], SImode, 0); |
2505bc97 RS |
2632 | |
2633 | if (optype1 == REGOP) | |
1d8eaa6b | 2634 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2635 | else if (optype1 == OFFSOP) |
b72f00af | 2636 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2637 | else if (optype1 == CNSTOP) |
2638 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2639 | else | |
c47b0cb4 | 2640 | latehalf[1] = adjust_address (operands[1], SImode, 0); |
2505bc97 | 2641 | } |
79e68feb RS |
2642 | |
2643 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2644 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2645 | for the low word as well, to compensate for the first decrement of sp. */ | |
2646 | if (optype0 == PUSHOP | |
2647 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2648 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2649 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2650 | |
7f98eeb6 RS |
2651 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2652 | if the upper part of reg N does not appear in the MEM, arrange to | |
2653 | emit the move late-half first. Otherwise, compute the MEM address | |
2654 | into the upper part of N and use that as a pointer to the memory | |
2655 | operand. */ | |
2656 | if (optype0 == REGOP | |
2657 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2658 | { | |
1d8eaa6b | 2659 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2660 | |
2661 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2662 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2663 | { |
2664 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2665 | compute the address into latehalf of dest. |
2666 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2667 | compadr: |
7f98eeb6 RS |
2668 | xops[0] = latehalf[0]; |
2669 | xops[1] = XEXP (operands[1], 0); | |
c47b0cb4 MK |
2670 | |
2671 | handle_compadr (xops); | |
2672 | if (GET_MODE (operands[1]) == XFmode) | |
7f98eeb6 | 2673 | { |
1d8eaa6b | 2674 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2675 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2676 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2677 | } |
2678 | else | |
2679 | { | |
1d8eaa6b | 2680 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2681 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2682 | } |
2683 | } | |
2684 | else if (size == 12 | |
d7e8d581 RS |
2685 | && reg_overlap_mentioned_p (middlehalf[0], |
2686 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2687 | { |
3a58400f RS |
2688 | /* Check for two regs used by both source and dest. |
2689 | Note that this can't happen if the dest is all data regs. | |
2690 | It can happen if the dest is d6, d7, a0. | |
2691 | But in that case, latehalf is an addr reg, so | |
2692 | the code at compadr does ok. */ | |
2693 | ||
2694 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2695 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2696 | goto compadr; | |
7f98eeb6 RS |
2697 | |
2698 | /* JRV says this can't happen: */ | |
4761e388 | 2699 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2700 | |
7a1929e1 | 2701 | /* Only the middle reg conflicts; simply put it last. */ |
c47b0cb4 MK |
2702 | handle_movsi (operands); |
2703 | handle_movsi (latehalf); | |
2704 | handle_movsi (middlehalf); | |
2705 | ||
2706 | return; | |
7f98eeb6 | 2707 | } |
2fb8a81d | 2708 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2709 | /* If the low half of dest is mentioned in the source memory |
2710 | address, the arrange to emit the move late half first. */ | |
2711 | dest_overlapped_low = 1; | |
2712 | } | |
2713 | ||
79e68feb RS |
2714 | /* If one or both operands autodecrementing, |
2715 | do the two words, high-numbered first. */ | |
2716 | ||
2717 | /* Likewise, the first move would clobber the source of the second one, | |
2718 | do them in the other order. This happens only for registers; | |
2719 | such overlap can't happen in memory unless the user explicitly | |
2720 | sets it up, and that is an undefined circumstance. */ | |
2721 | ||
2722 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2723 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2724 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2725 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2726 | || dest_overlapped_low) | |
79e68feb RS |
2727 | { |
2728 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2729 | if (addreg0) | |
c47b0cb4 | 2730 | handle_reg_adjust (addreg0, size - 4); |
79e68feb | 2731 | if (addreg1) |
c47b0cb4 | 2732 | handle_reg_adjust (addreg1, size - 4); |
79e68feb RS |
2733 | |
2734 | /* Do that word. */ | |
c47b0cb4 | 2735 | handle_movsi (latehalf); |
79e68feb RS |
2736 | |
2737 | /* Undo the adds we just did. */ | |
2738 | if (addreg0) | |
c47b0cb4 | 2739 | handle_reg_adjust (addreg0, -4); |
79e68feb | 2740 | if (addreg1) |
c47b0cb4 | 2741 | handle_reg_adjust (addreg1, -4); |
79e68feb | 2742 | |
2505bc97 RS |
2743 | if (size == 12) |
2744 | { | |
c47b0cb4 MK |
2745 | handle_movsi (middlehalf); |
2746 | ||
2505bc97 | 2747 | if (addreg0) |
c47b0cb4 | 2748 | handle_reg_adjust (addreg0, -4); |
2505bc97 | 2749 | if (addreg1) |
c47b0cb4 | 2750 | handle_reg_adjust (addreg1, -4); |
2505bc97 RS |
2751 | } |
2752 | ||
79e68feb | 2753 | /* Do low-numbered word. */ |
c47b0cb4 MK |
2754 | |
2755 | handle_movsi (operands); | |
2756 | return; | |
79e68feb RS |
2757 | } |
2758 | ||
2759 | /* Normal case: do the two words, low-numbered first. */ | |
2760 | ||
c47b0cb4 | 2761 | handle_movsi (operands); |
79e68feb | 2762 | |
2505bc97 RS |
2763 | /* Do the middle one of the three words for long double */ |
2764 | if (size == 12) | |
2765 | { | |
2766 | if (addreg0) | |
c47b0cb4 | 2767 | handle_reg_adjust (addreg0, 4); |
2505bc97 | 2768 | if (addreg1) |
c47b0cb4 | 2769 | handle_reg_adjust (addreg1, 4); |
2505bc97 | 2770 | |
c47b0cb4 | 2771 | handle_movsi (middlehalf); |
2505bc97 RS |
2772 | } |
2773 | ||
79e68feb RS |
2774 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2775 | if (addreg0) | |
c47b0cb4 | 2776 | handle_reg_adjust (addreg0, 4); |
79e68feb | 2777 | if (addreg1) |
c47b0cb4 | 2778 | handle_reg_adjust (addreg1, 4); |
79e68feb RS |
2779 | |
2780 | /* Do that word. */ | |
c47b0cb4 | 2781 | handle_movsi (latehalf); |
79e68feb RS |
2782 | |
2783 | /* Undo the adds we just did. */ | |
2784 | if (addreg0) | |
c47b0cb4 MK |
2785 | handle_reg_adjust (addreg0, -(size - 4)); |
2786 | if (addreg1) | |
2787 | handle_reg_adjust (addreg1, -(size - 4)); | |
2788 | ||
2789 | return; | |
2790 | } | |
2791 | ||
2792 | /* Output assembler code to adjust REG by N. */ | |
2793 | static void | |
2794 | output_reg_adjust (rtx reg, int n) | |
2795 | { | |
2796 | const char *s; | |
2797 | ||
2798 | gcc_assert (GET_MODE (reg) == SImode | |
2799 | && -12 <= n && n != 0 && n <= 12); | |
2800 | ||
2801 | switch (n) | |
2505bc97 | 2802 | { |
c47b0cb4 MK |
2803 | case 12: |
2804 | s = "add%.l #12,%0"; | |
2805 | break; | |
2806 | ||
2807 | case 8: | |
2808 | s = "addq%.l #8,%0"; | |
2809 | break; | |
2810 | ||
2811 | case 4: | |
2812 | s = "addq%.l #4,%0"; | |
2813 | break; | |
2814 | ||
2815 | case -12: | |
2816 | s = "sub%.l #12,%0"; | |
2817 | break; | |
2818 | ||
2819 | case -8: | |
2820 | s = "subq%.l #8,%0"; | |
2821 | break; | |
2822 | ||
2823 | case -4: | |
2824 | s = "subq%.l #4,%0"; | |
2825 | break; | |
2826 | ||
2827 | default: | |
2828 | gcc_unreachable (); | |
2829 | s = NULL; | |
2505bc97 | 2830 | } |
c47b0cb4 MK |
2831 | |
2832 | output_asm_insn (s, ®); | |
2833 | } | |
2834 | ||
2835 | /* Emit rtl code to adjust REG by N. */ | |
2836 | static void | |
2837 | emit_reg_adjust (rtx reg1, int n) | |
2838 | { | |
2839 | rtx reg2; | |
2840 | ||
2841 | gcc_assert (GET_MODE (reg1) == SImode | |
2842 | && -12 <= n && n != 0 && n <= 12); | |
2843 | ||
2844 | reg1 = copy_rtx (reg1); | |
2845 | reg2 = copy_rtx (reg1); | |
2846 | ||
2847 | if (n < 0) | |
2848 | emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n))); | |
2849 | else if (n > 0) | |
2850 | emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n))); | |
2851 | else | |
2852 | gcc_unreachable (); | |
2853 | } | |
2854 | ||
2855 | /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */ | |
2856 | static void | |
2857 | output_compadr (rtx operands[2]) | |
2858 | { | |
2859 | output_asm_insn ("lea %a1,%0", operands); | |
2860 | } | |
2861 | ||
2862 | /* Output the best assembler insn for moving operands[1] into operands[0] | |
2863 | as a fullword. */ | |
2864 | static void | |
2865 | output_movsi (rtx operands[2]) | |
2866 | { | |
2867 | output_asm_insn (singlemove_string (operands), operands); | |
2868 | } | |
2869 | ||
2870 | /* Copy OP and change its mode to MODE. */ | |
2871 | static rtx | |
2872 | copy_operand (rtx op, enum machine_mode mode) | |
2873 | { | |
2874 | /* ??? This looks really ugly. There must be a better way | |
2875 | to change a mode on the operand. */ | |
2876 | if (GET_MODE (op) != VOIDmode) | |
2505bc97 | 2877 | { |
c47b0cb4 MK |
2878 | if (REG_P (op)) |
2879 | op = gen_rtx_REG (mode, REGNO (op)); | |
2505bc97 | 2880 | else |
c47b0cb4 MK |
2881 | { |
2882 | op = copy_rtx (op); | |
2883 | PUT_MODE (op, mode); | |
2884 | } | |
2505bc97 | 2885 | } |
79e68feb | 2886 | |
c47b0cb4 MK |
2887 | return op; |
2888 | } | |
2889 | ||
2890 | /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */ | |
2891 | static void | |
2892 | emit_movsi (rtx operands[2]) | |
2893 | { | |
2894 | operands[0] = copy_operand (operands[0], SImode); | |
2895 | operands[1] = copy_operand (operands[1], SImode); | |
2896 | ||
2897 | emit_insn (gen_movsi (operands[0], operands[1])); | |
2898 | } | |
2899 | ||
2900 | /* Output assembler code to perform a doubleword move insn | |
2901 | with operands OPERANDS. */ | |
2902 | const char * | |
2903 | output_move_double (rtx *operands) | |
2904 | { | |
2905 | handle_move_double (operands, | |
2906 | output_reg_adjust, output_compadr, output_movsi); | |
2907 | ||
79e68feb RS |
2908 | return ""; |
2909 | } | |
2910 | ||
c47b0cb4 MK |
2911 | /* Output rtl code to perform a doubleword move insn |
2912 | with operands OPERANDS. */ | |
2913 | void | |
2914 | m68k_emit_move_double (rtx operands[2]) | |
2915 | { | |
2916 | handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi); | |
2917 | } | |
dcc21c4c PB |
2918 | |
2919 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2920 | new rtx with the correct mode. */ | |
2921 | ||
2922 | static rtx | |
2923 | force_mode (enum machine_mode mode, rtx orig) | |
2924 | { | |
2925 | if (mode == GET_MODE (orig)) | |
2926 | return orig; | |
2927 | ||
2928 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2929 | abort (); | |
2930 | ||
2931 | return gen_rtx_REG (mode, REGNO (orig)); | |
2932 | } | |
2933 | ||
2934 | static int | |
2935 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2936 | { | |
2937 | return reg_renumber && FP_REG_P (op); | |
2938 | } | |
2939 | ||
2940 | /* Emit insns to move operands[1] into operands[0]. | |
2941 | ||
2942 | Return 1 if we have written out everything that needs to be done to | |
2943 | do the move. Otherwise, return 0 and the caller will emit the move | |
2944 | normally. | |
2945 | ||
2946 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2947 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2948 | of SCRATCH_REG in the proper mode. */ |
2949 | ||
2950 | int | |
2951 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2952 | { | |
2953 | register rtx operand0 = operands[0]; | |
2954 | register rtx operand1 = operands[1]; | |
2955 | register rtx tem; | |
2956 | ||
2957 | if (scratch_reg | |
2958 | && reload_in_progress && GET_CODE (operand0) == REG | |
2959 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2960 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2961 | else if (scratch_reg | |
2962 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2963 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2964 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2965 | { | |
2966 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2967 | the code which tracks sets/uses for delete_output_reload. */ | |
2968 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2969 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2970 | SUBREG_BYTE (operand0)); | |
2971 | operand0 = alter_subreg (&temp); | |
2972 | } | |
2973 | ||
2974 | if (scratch_reg | |
2975 | && reload_in_progress && GET_CODE (operand1) == REG | |
2976 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2977 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2978 | else if (scratch_reg | |
2979 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2980 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2981 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2982 | { | |
2983 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2984 | the code which tracks sets/uses for delete_output_reload. */ | |
2985 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2986 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2987 | SUBREG_BYTE (operand1)); | |
2988 | operand1 = alter_subreg (&temp); | |
2989 | } | |
2990 | ||
2991 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2992 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2993 | != XEXP (operand0, 0))) | |
2994 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2995 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2996 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2997 | != XEXP (operand1, 0))) | |
2998 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2999 | ||
3000 | /* Handle secondary reloads for loads/stores of FP registers where | |
3001 | the address is symbolic by using the scratch register */ | |
3002 | if (fp_reg_operand (operand0, mode) | |
3003 | && ((GET_CODE (operand1) == MEM | |
3004 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
3005 | || ((GET_CODE (operand1) == SUBREG | |
3006 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
3007 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
3008 | && scratch_reg) | |
3009 | { | |
3010 | if (GET_CODE (operand1) == SUBREG) | |
3011 | operand1 = XEXP (operand1, 0); | |
3012 | ||
3013 | /* SCRATCH_REG will hold an address. We want | |
3014 | it in SImode regardless of what mode it was originally given | |
3015 | to us. */ | |
3016 | scratch_reg = force_mode (SImode, scratch_reg); | |
3017 | ||
3018 | /* D might not fit in 14 bits either; for such cases load D into | |
3019 | scratch reg. */ | |
3020 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
3021 | { | |
3022 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
3023 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
3024 | Pmode, | |
3025 | XEXP (XEXP (operand1, 0), 0), | |
3026 | scratch_reg)); | |
3027 | } | |
3028 | else | |
3029 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
3030 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
3031 | gen_rtx_MEM (mode, scratch_reg))); | |
3032 | return 1; | |
3033 | } | |
3034 | else if (fp_reg_operand (operand1, mode) | |
3035 | && ((GET_CODE (operand0) == MEM | |
3036 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
3037 | || ((GET_CODE (operand0) == SUBREG) | |
3038 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
3039 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
3040 | && scratch_reg) | |
3041 | { | |
3042 | if (GET_CODE (operand0) == SUBREG) | |
3043 | operand0 = XEXP (operand0, 0); | |
3044 | ||
3045 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3046 | it in SIMODE regardless of what mode it was originally given | |
3047 | to us. */ | |
3048 | scratch_reg = force_mode (SImode, scratch_reg); | |
3049 | ||
3050 | /* D might not fit in 14 bits either; for such cases load D into | |
3051 | scratch reg. */ | |
3052 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
3053 | { | |
3054 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
3055 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
3056 | 0)), | |
3057 | Pmode, | |
3058 | XEXP (XEXP (operand0, 0), | |
3059 | 0), | |
3060 | scratch_reg)); | |
3061 | } | |
3062 | else | |
3063 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
3064 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
3065 | operand1)); | |
3066 | return 1; | |
3067 | } | |
3068 | /* Handle secondary reloads for loads of FP registers from constant | |
3069 | expressions by forcing the constant into memory. | |
3070 | ||
3071 | use scratch_reg to hold the address of the memory location. | |
3072 | ||
3073 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
3074 | NO_REGS when presented with a const_int and an register class | |
3075 | containing only FP registers. Doing so unfortunately creates | |
3076 | more problems than it solves. Fix this for 2.5. */ | |
3077 | else if (fp_reg_operand (operand0, mode) | |
3078 | && CONSTANT_P (operand1) | |
3079 | && scratch_reg) | |
3080 | { | |
3081 | rtx xoperands[2]; | |
3082 | ||
3083 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3084 | it in SIMODE regardless of what mode it was originally given | |
3085 | to us. */ | |
3086 | scratch_reg = force_mode (SImode, scratch_reg); | |
3087 | ||
3088 | /* Force the constant into memory and put the address of the | |
3089 | memory location into scratch_reg. */ | |
3090 | xoperands[0] = scratch_reg; | |
3091 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
3092 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
3093 | ||
3094 | /* Now load the destination register. */ | |
3095 | emit_insn (gen_rtx_SET (mode, operand0, | |
3096 | gen_rtx_MEM (mode, scratch_reg))); | |
3097 | return 1; | |
3098 | } | |
3099 | ||
3100 | /* Now have insn-emit do whatever it normally does. */ | |
3101 | return 0; | |
3102 | } | |
3103 | ||
01e304f8 RZ |
3104 | /* Split one or more DImode RTL references into pairs of SImode |
3105 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
3106 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
3107 | split and "num" is its length. lo_half and hi_half are output arrays | |
3108 | that parallel "operands". */ | |
3109 | ||
3110 | void | |
3111 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
3112 | { | |
3113 | while (num--) | |
3114 | { | |
3115 | rtx op = operands[num]; | |
3116 | ||
3117 | /* simplify_subreg refuses to split volatile memory addresses, | |
3118 | but we still have to handle it. */ | |
3119 | if (GET_CODE (op) == MEM) | |
3120 | { | |
3121 | lo_half[num] = adjust_address (op, SImode, 4); | |
3122 | hi_half[num] = adjust_address (op, SImode, 0); | |
3123 | } | |
3124 | else | |
3125 | { | |
3126 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
3127 | GET_MODE (op) == VOIDmode | |
3128 | ? DImode : GET_MODE (op), 4); | |
3129 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
3130 | GET_MODE (op) == VOIDmode | |
3131 | ? DImode : GET_MODE (op), 0); | |
3132 | } | |
3133 | } | |
3134 | } | |
3135 | ||
a40ed0f3 KH |
3136 | /* Split X into a base and a constant offset, storing them in *BASE |
3137 | and *OFFSET respectively. */ | |
3138 | ||
3139 | static void | |
3140 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
3141 | { | |
3142 | *offset = 0; | |
3143 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3144 | { | |
3145 | *offset += INTVAL (XEXP (x, 1)); | |
3146 | x = XEXP (x, 0); | |
3147 | } | |
3148 | *base = x; | |
3149 | } | |
3150 | ||
3151 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
3152 | instruction. STORE_P says whether the move is a load or store. | |
3153 | ||
3154 | If the instruction uses post-increment or pre-decrement addressing, | |
3155 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
3156 | adjustment. This adjustment will be made by the first element of | |
3157 | PARALLEL, with the loads or stores starting at element 1. If the | |
3158 | instruction does not use post-increment or pre-decrement addressing, | |
3159 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
3160 | start at element 0. */ | |
3161 | ||
3162 | bool | |
3163 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
3164 | HOST_WIDE_INT automod_offset, bool store_p) | |
3165 | { | |
3166 | rtx base, mem_base, set, mem, reg, last_reg; | |
3167 | HOST_WIDE_INT offset, mem_offset; | |
3168 | int i, first, len; | |
3169 | enum reg_class rclass; | |
3170 | ||
3171 | len = XVECLEN (pattern, 0); | |
3172 | first = (automod_base != NULL); | |
3173 | ||
3174 | if (automod_base) | |
3175 | { | |
3176 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
3177 | if (store_p != (automod_offset < 0)) | |
3178 | return false; | |
3179 | ||
3180 | /* Work out the base and offset for lowest memory location. */ | |
3181 | base = automod_base; | |
3182 | offset = (automod_offset < 0 ? automod_offset : 0); | |
3183 | } | |
3184 | else | |
3185 | { | |
3186 | /* Allow any valid base and offset in the first access. */ | |
3187 | base = NULL; | |
3188 | offset = 0; | |
3189 | } | |
3190 | ||
3191 | last_reg = NULL; | |
3192 | rclass = NO_REGS; | |
3193 | for (i = first; i < len; i++) | |
3194 | { | |
3195 | /* We need a plain SET. */ | |
3196 | set = XVECEXP (pattern, 0, i); | |
3197 | if (GET_CODE (set) != SET) | |
3198 | return false; | |
3199 | ||
3200 | /* Check that we have a memory location... */ | |
3201 | mem = XEXP (set, !store_p); | |
3202 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
3203 | return false; | |
3204 | ||
3205 | /* ...with the right address. */ | |
3206 | if (base == NULL) | |
3207 | { | |
3208 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
3209 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
3210 | There are no mode restrictions for 680x0 besides the | |
3211 | automodification rules enforced above. */ | |
3212 | if (TARGET_COLDFIRE | |
3213 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
3214 | return false; | |
3215 | } | |
3216 | else | |
3217 | { | |
3218 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
3219 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
3220 | return false; | |
3221 | } | |
3222 | ||
3223 | /* Check that we have a register of the required mode and class. */ | |
3224 | reg = XEXP (set, store_p); | |
3225 | if (!REG_P (reg) | |
3226 | || !HARD_REGISTER_P (reg) | |
3227 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
3228 | return false; | |
3229 | ||
3230 | if (last_reg) | |
3231 | { | |
3232 | /* The register must belong to RCLASS and have a higher number | |
3233 | than the register in the previous SET. */ | |
3234 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
3235 | || REGNO (last_reg) >= REGNO (reg)) | |
3236 | return false; | |
3237 | } | |
3238 | else | |
3239 | { | |
3240 | /* Work out which register class we need. */ | |
3241 | if (INT_REGNO_P (REGNO (reg))) | |
3242 | rclass = GENERAL_REGS; | |
3243 | else if (FP_REGNO_P (REGNO (reg))) | |
3244 | rclass = FP_REGS; | |
3245 | else | |
3246 | return false; | |
3247 | } | |
3248 | ||
3249 | last_reg = reg; | |
3250 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
3251 | } | |
3252 | ||
3253 | /* If we have an automodification, check whether the final offset is OK. */ | |
3254 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
3255 | return false; | |
3256 | ||
3257 | /* Reject unprofitable cases. */ | |
3258 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
3259 | return false; | |
3260 | ||
3261 | return true; | |
3262 | } | |
3263 | ||
3264 | /* Return the assembly code template for a movem or fmovem instruction | |
3265 | whose pattern is given by PATTERN. Store the template's operands | |
3266 | in OPERANDS. | |
3267 | ||
3268 | If the instruction uses post-increment or pre-decrement addressing, | |
3269 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
3270 | is true if this is a store instruction. */ | |
3271 | ||
3272 | const char * | |
3273 | m68k_output_movem (rtx *operands, rtx pattern, | |
3274 | HOST_WIDE_INT automod_offset, bool store_p) | |
3275 | { | |
3276 | unsigned int mask; | |
3277 | int i, first; | |
3278 | ||
3279 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
3280 | mask = 0; | |
3281 | first = (automod_offset != 0); | |
3282 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
3283 | { | |
3284 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
3285 | is controlled by bit 15 - X. For all other addressing modes, | |
3286 | register X + D0_REG is controlled by bit X. Confusingly, the | |
3287 | register mask for fmovem is in the opposite order to that for | |
3288 | movem. */ | |
3289 | unsigned int regno; | |
3290 | ||
3291 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
3292 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
3293 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
3294 | if (automod_offset < 0) | |
3295 | { | |
3296 | if (FP_REGNO_P (regno)) | |
3297 | mask |= 1 << (regno - FP0_REG); | |
3298 | else | |
3299 | mask |= 1 << (15 - (regno - D0_REG)); | |
3300 | } | |
3301 | else | |
3302 | { | |
3303 | if (FP_REGNO_P (regno)) | |
3304 | mask |= 1 << (7 - (regno - FP0_REG)); | |
3305 | else | |
3306 | mask |= 1 << (regno - D0_REG); | |
3307 | } | |
3308 | } | |
3309 | CC_STATUS_INIT; | |
3310 | ||
3311 | if (automod_offset == 0) | |
3312 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
3313 | else if (automod_offset < 0) | |
3314 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3315 | else | |
3316 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3317 | operands[1] = GEN_INT (mask); | |
3318 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
3319 | { | |
3320 | if (store_p) | |
1fae2d80 | 3321 | return "fmovem %1,%a0"; |
a40ed0f3 | 3322 | else |
1fae2d80 | 3323 | return "fmovem %a0,%1"; |
a40ed0f3 KH |
3324 | } |
3325 | else | |
3326 | { | |
3327 | if (store_p) | |
1fae2d80 | 3328 | return "movem%.l %1,%a0"; |
a40ed0f3 | 3329 | else |
1fae2d80 | 3330 | return "movem%.l %a0,%1"; |
a40ed0f3 KH |
3331 | } |
3332 | } | |
3333 | ||
79e68feb RS |
3334 | /* Return a REG that occurs in ADDR with coefficient 1. |
3335 | ADDR can be effectively incremented by incrementing REG. */ | |
3336 | ||
3337 | static rtx | |
8a4a2253 | 3338 | find_addr_reg (rtx addr) |
79e68feb RS |
3339 | { |
3340 | while (GET_CODE (addr) == PLUS) | |
3341 | { | |
3342 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3343 | addr = XEXP (addr, 0); | |
3344 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3345 | addr = XEXP (addr, 1); | |
3346 | else if (CONSTANT_P (XEXP (addr, 0))) | |
3347 | addr = XEXP (addr, 1); | |
3348 | else if (CONSTANT_P (XEXP (addr, 1))) | |
3349 | addr = XEXP (addr, 0); | |
3350 | else | |
4761e388 | 3351 | gcc_unreachable (); |
79e68feb | 3352 | } |
4761e388 NS |
3353 | gcc_assert (GET_CODE (addr) == REG); |
3354 | return addr; | |
79e68feb | 3355 | } |
9ee3c687 | 3356 | |
c16eadc7 | 3357 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 3358 | |
5505f548 | 3359 | const char * |
8a4a2253 | 3360 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
3361 | { |
3362 | if (! operands_match_p (operands[0], operands[1])) | |
3363 | { | |
3364 | if (!ADDRESS_REG_P (operands[1])) | |
3365 | { | |
3366 | rtx tmp = operands[1]; | |
3367 | ||
3368 | operands[1] = operands[2]; | |
3369 | operands[2] = tmp; | |
3370 | } | |
3371 | ||
3372 | /* These insns can result from reloads to access | |
3373 | stack slots over 64k from the frame pointer. */ | |
3374 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 3375 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 3376 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 3377 | if (GET_CODE (operands[2]) == REG) |
becb103c KH |
3378 | return "lea {(%1,%2.l)|%1@(0,%2:l)},%0"; |
3379 | return "lea {(%c2,%1)|%1@(%c2)},%0"; | |
9ee3c687 JW |
3380 | } |
3381 | if (GET_CODE (operands[2]) == CONST_INT) | |
3382 | { | |
9ee3c687 JW |
3383 | if (INTVAL (operands[2]) > 0 |
3384 | && INTVAL (operands[2]) <= 8) | |
3385 | return "addq%.l %2,%0"; | |
3386 | if (INTVAL (operands[2]) < 0 | |
3387 | && INTVAL (operands[2]) >= -8) | |
3388 | { | |
c5c76735 | 3389 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
3390 | return "subq%.l %2,%0"; |
3391 | } | |
3392 | /* On the CPU32 it is faster to use two addql instructions to | |
3393 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 3394 | Likewise for subql. */ |
fe95f2f7 | 3395 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
3396 | { |
3397 | if (INTVAL (operands[2]) > 8 | |
3398 | && INTVAL (operands[2]) <= 16) | |
3399 | { | |
1d8eaa6b | 3400 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 3401 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
3402 | } |
3403 | if (INTVAL (operands[2]) < -8 | |
3404 | && INTVAL (operands[2]) >= -16) | |
3405 | { | |
c5c76735 | 3406 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 3407 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
3408 | } |
3409 | } | |
9ee3c687 JW |
3410 | if (ADDRESS_REG_P (operands[0]) |
3411 | && INTVAL (operands[2]) >= -0x8000 | |
3412 | && INTVAL (operands[2]) < 0x8000) | |
3413 | { | |
fe95f2f7 | 3414 | if (TUNE_68040) |
9ee3c687 JW |
3415 | return "add%.w %2,%0"; |
3416 | else | |
becb103c | 3417 | return "lea {(%c2,%0)|%0@(%c2)},%0"; |
9ee3c687 JW |
3418 | } |
3419 | } | |
3420 | return "add%.l %2,%0"; | |
3421 | } | |
79e68feb RS |
3422 | \f |
3423 | /* Store in cc_status the expressions that the condition codes will | |
3424 | describe after execution of an instruction whose pattern is EXP. | |
3425 | Do not alter them if the instruction would not alter the cc's. */ | |
3426 | ||
3427 | /* On the 68000, all the insns to store in an address register fail to | |
3428 | set the cc's. However, in some cases these instructions can make it | |
3429 | possibly invalid to use the saved cc's. In those cases we clear out | |
3430 | some or all of the saved cc's so they won't be used. */ | |
3431 | ||
1d8eaa6b | 3432 | void |
8a4a2253 | 3433 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 3434 | { |
1a8965c4 | 3435 | if (GET_CODE (exp) == SET) |
79e68feb RS |
3436 | { |
3437 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 3438 | CC_STATUS_INIT; |
79e68feb RS |
3439 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
3440 | { | |
f5963e61 | 3441 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 3442 | cc_status.value1 = 0; |
f5963e61 | 3443 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
3444 | cc_status.value2 = 0; |
3445 | } | |
f6ab62e8 RS |
3446 | /* fmoves to memory or data registers do not set the condition |
3447 | codes. Normal moves _do_ set the condition codes, but not in | |
3448 | a way that is appropriate for comparison with 0, because -0.0 | |
3449 | would be treated as a negative nonzero number. Note that it | |
88512ba0 | 3450 | isn't appropriate to conditionalize this restriction on |
f6ab62e8 RS |
3451 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
3452 | we care about the difference between -0.0 and +0.0. */ | |
79e68feb RS |
3453 | else if (!FP_REG_P (SET_DEST (exp)) |
3454 | && SET_DEST (exp) != cc0_rtx | |
3455 | && (FP_REG_P (SET_SRC (exp)) | |
3456 | || GET_CODE (SET_SRC (exp)) == FIX | |
f6ab62e8 | 3457 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
a0a7fbc9 | 3458 | CC_STATUS_INIT; |
79e68feb RS |
3459 | /* A pair of move insns doesn't produce a useful overall cc. */ |
3460 | else if (!FP_REG_P (SET_DEST (exp)) | |
3461 | && !FP_REG_P (SET_SRC (exp)) | |
3462 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
3463 | && (GET_CODE (SET_SRC (exp)) == REG | |
3464 | || GET_CODE (SET_SRC (exp)) == MEM | |
3465 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 3466 | CC_STATUS_INIT; |
e1dff52a | 3467 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
3468 | { |
3469 | cc_status.flags = 0; | |
e1dff52a KH |
3470 | cc_status.value1 = SET_DEST (exp); |
3471 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
3472 | } |
3473 | } | |
3474 | else if (GET_CODE (exp) == PARALLEL | |
3475 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
3476 | { | |
e1dff52a KH |
3477 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
3478 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
3479 | ||
3480 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 3481 | CC_STATUS_INIT; |
e1dff52a | 3482 | else if (dest != pc_rtx) |
79e68feb RS |
3483 | { |
3484 | cc_status.flags = 0; | |
e1dff52a KH |
3485 | cc_status.value1 = dest; |
3486 | cc_status.value2 = src; | |
79e68feb RS |
3487 | } |
3488 | } | |
3489 | else | |
3490 | CC_STATUS_INIT; | |
3491 | if (cc_status.value2 != 0 | |
3492 | && ADDRESS_REG_P (cc_status.value2) | |
3493 | && GET_MODE (cc_status.value2) == QImode) | |
3494 | CC_STATUS_INIT; | |
1a8965c4 | 3495 | if (cc_status.value2 != 0) |
79e68feb RS |
3496 | switch (GET_CODE (cc_status.value2)) |
3497 | { | |
996a5f59 | 3498 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 3499 | case ROTATE: case ROTATERT: |
a126dc3a RH |
3500 | /* These instructions always clear the overflow bit, and set |
3501 | the carry to the bit shifted out. */ | |
3502 | /* ??? We don't currently have a way to signal carry not valid, | |
3503 | nor do we check for it in the branch insns. */ | |
3504 | CC_STATUS_INIT; | |
3505 | break; | |
3506 | ||
3507 | case PLUS: case MINUS: case MULT: | |
3508 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
3509 | if (GET_MODE (cc_status.value2) != VOIDmode) |
3510 | cc_status.flags |= CC_NO_OVERFLOW; | |
3511 | break; | |
3512 | case ZERO_EXTEND: | |
3513 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
3514 | ends with a move insn moving r2 in r2's mode. | |
3515 | Thus, the cc's are set for r2. | |
7a1929e1 | 3516 | This can set N bit spuriously. */ |
79e68feb | 3517 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
3518 | |
3519 | default: | |
3520 | break; | |
79e68feb RS |
3521 | } |
3522 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
3523 | && cc_status.value2 | |
3524 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
3525 | cc_status.value2 = 0; | |
3526 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 3527 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb | 3528 | cc_status.flags = CC_IN_68881; |
67595cbb RZ |
3529 | if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE |
3530 | && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT) | |
3531 | { | |
3532 | cc_status.flags = CC_IN_68881; | |
3533 | if (!FP_REG_P (XEXP (cc_status.value2, 0))) | |
3534 | cc_status.flags |= CC_REVERSED; | |
3535 | } | |
79e68feb RS |
3536 | } |
3537 | \f | |
5505f548 | 3538 | const char * |
8a4a2253 | 3539 | output_move_const_double (rtx *operands) |
79e68feb | 3540 | { |
1a8965c4 | 3541 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3542 | |
1a8965c4 | 3543 | if (code != 0) |
79e68feb | 3544 | { |
1a8965c4 | 3545 | static char buf[40]; |
79e68feb | 3546 | |
3b4b85c9 | 3547 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3548 | return buf; |
79e68feb | 3549 | } |
1a8965c4 | 3550 | return "fmove%.d %1,%0"; |
79e68feb RS |
3551 | } |
3552 | ||
5505f548 | 3553 | const char * |
8a4a2253 | 3554 | output_move_const_single (rtx *operands) |
79e68feb | 3555 | { |
1a8965c4 | 3556 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3557 | |
1a8965c4 | 3558 | if (code != 0) |
79e68feb | 3559 | { |
1a8965c4 | 3560 | static char buf[40]; |
79e68feb | 3561 | |
3b4b85c9 | 3562 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3563 | return buf; |
79e68feb | 3564 | } |
1a8965c4 | 3565 | return "fmove%.s %f1,%0"; |
79e68feb RS |
3566 | } |
3567 | ||
3568 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
3569 | from the "fmovecr" instruction. | |
3570 | The value, anded with 0xff, gives the code to use in fmovecr | |
3571 | to get the desired constant. */ | |
3572 | ||
7a1929e1 | 3573 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
3574 | |
3575 | static int inited_68881_table = 0; | |
3576 | ||
5505f548 | 3577 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
3578 | "0.0", |
3579 | "1.0", | |
3580 | "10.0", | |
3581 | "100.0", | |
3582 | "10000.0", | |
3583 | "1e8", | |
3584 | "1e16" | |
a0a7fbc9 | 3585 | }; |
c1cfb2ae | 3586 | |
8b60264b | 3587 | static const int codes_68881[7] = { |
c1cfb2ae RS |
3588 | 0x0f, |
3589 | 0x32, | |
3590 | 0x33, | |
3591 | 0x34, | |
3592 | 0x35, | |
3593 | 0x36, | |
3594 | 0x37 | |
a0a7fbc9 | 3595 | }; |
c1cfb2ae RS |
3596 | |
3597 | REAL_VALUE_TYPE values_68881[7]; | |
3598 | ||
3599 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 3600 | strings_68881 to binary. */ |
c1cfb2ae RS |
3601 | |
3602 | void | |
8a4a2253 | 3603 | init_68881_table (void) |
c1cfb2ae RS |
3604 | { |
3605 | int i; | |
3606 | REAL_VALUE_TYPE r; | |
3607 | enum machine_mode mode; | |
3608 | ||
16d82c3c | 3609 | mode = SFmode; |
c1cfb2ae RS |
3610 | for (i = 0; i < 7; i++) |
3611 | { | |
3612 | if (i == 6) | |
16d82c3c | 3613 | mode = DFmode; |
c1cfb2ae RS |
3614 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
3615 | values_68881[i] = r; | |
3616 | } | |
3617 | inited_68881_table = 1; | |
3618 | } | |
79e68feb RS |
3619 | |
3620 | int | |
8a4a2253 | 3621 | standard_68881_constant_p (rtx x) |
79e68feb | 3622 | { |
c1cfb2ae RS |
3623 | REAL_VALUE_TYPE r; |
3624 | int i; | |
79e68feb | 3625 | |
e18db50d | 3626 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 3627 | used at all on those chips. */ |
9cf106c8 | 3628 | if (TUNE_68040_60) |
79e68feb RS |
3629 | return 0; |
3630 | ||
c1cfb2ae RS |
3631 | if (! inited_68881_table) |
3632 | init_68881_table (); | |
3633 | ||
3634 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3635 | ||
64c0b414 AS |
3636 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
3637 | is rejected. */ | |
c1cfb2ae RS |
3638 | for (i = 0; i < 6; i++) |
3639 | { | |
64c0b414 | 3640 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
3641 | return (codes_68881[i]); |
3642 | } | |
3643 | ||
79e68feb RS |
3644 | if (GET_MODE (x) == SFmode) |
3645 | return 0; | |
c1cfb2ae RS |
3646 | |
3647 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
3648 | return (codes_68881[6]); | |
3649 | ||
79e68feb RS |
3650 | /* larger powers of ten in the constants ram are not used |
3651 | because they are not equal to a `double' C constant. */ | |
3652 | return 0; | |
3653 | } | |
3654 | ||
3655 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3656 | or 0 if X is not a power of 2. */ | |
3657 | ||
3658 | int | |
8a4a2253 | 3659 | floating_exact_log2 (rtx x) |
79e68feb | 3660 | { |
c1cfb2ae | 3661 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3662 | int exp; |
79e68feb | 3663 | |
c1cfb2ae | 3664 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3665 | |
eaff3bf8 | 3666 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3667 | return 0; |
3668 | ||
eaff3bf8 | 3669 | exp = real_exponent (&r); |
6ef9a246 | 3670 | real_2expN (&r1, exp, DFmode); |
eaff3bf8 RH |
3671 | if (REAL_VALUES_EQUAL (r1, r)) |
3672 | return exp; | |
3673 | ||
79e68feb RS |
3674 | return 0; |
3675 | } | |
3676 | \f | |
79e68feb RS |
3677 | /* A C compound statement to output to stdio stream STREAM the |
3678 | assembler syntax for an instruction operand X. X is an RTL | |
3679 | expression. | |
3680 | ||
3681 | CODE is a value that can be used to specify one of several ways | |
3682 | of printing the operand. It is used when identical operands | |
3683 | must be printed differently depending on the context. CODE | |
3684 | comes from the `%' specification that was used to request | |
3685 | printing of the operand. If the specification was just `%DIGIT' | |
3686 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3687 | is the ASCII code for LTR. | |
3688 | ||
3689 | If X is a register, this macro should print the register's name. | |
3690 | The names can be found in an array `reg_names' whose type is | |
3691 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3692 | ||
3693 | When the machine description has a specification `%PUNCT' (a `%' | |
3694 | followed by a punctuation character), this macro is called with | |
3695 | a null pointer for X and the punctuation character for CODE. | |
3696 | ||
3697 | The m68k specific codes are: | |
3698 | ||
3699 | '.' for dot needed in Motorola-style opcode names. | |
3700 | '-' for an operand pushing on the stack: | |
3701 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3702 | '+' for an operand pushing on the stack: | |
3703 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3704 | '@' for a reference to the top word on the stack: | |
3705 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3706 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3707 | but & in SGS syntax). |
79e68feb RS |
3708 | '!' for the cc register (used in an `and to cc' insn). |
3709 | '$' for the letter `s' in an op code, but only on the 68040. | |
3710 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3711 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 3712 | '?' for m68k_library_id_string |
e477cbcb KH |
3713 | '{' for '{' |
3714 | '}' for '}' | |
79e68feb RS |
3715 | |
3716 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3717 | 'd' to force memory addressing to be absolute, not relative. | |
3718 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
3719 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3720 | or print pair of registers as rx:ry. | |
29ca003a RS |
3721 | 'p' print an address with @PLTPC attached, but only if the operand |
3722 | is not locally-bound. */ | |
79e68feb RS |
3723 | |
3724 | void | |
8a4a2253 | 3725 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3726 | { |
79e68feb RS |
3727 | if (letter == '.') |
3728 | { | |
e6d98cb0 BI |
3729 | if (MOTOROLA) |
3730 | fprintf (file, "."); | |
79e68feb | 3731 | } |
e477cbcb KH |
3732 | else if (letter == '{') |
3733 | fprintf (file, "{"); | |
3734 | else if (letter == '}') | |
3735 | fprintf (file, "}"); | |
79e68feb | 3736 | else if (letter == '#') |
e6d98cb0 | 3737 | asm_fprintf (file, "%I"); |
79e68feb | 3738 | else if (letter == '-') |
becb103c | 3739 | asm_fprintf (file, "{-(%Rsp)|%Rsp@-}"); |
79e68feb | 3740 | else if (letter == '+') |
becb103c | 3741 | asm_fprintf (file, "{(%Rsp)+|%Rsp@+}"); |
79e68feb | 3742 | else if (letter == '@') |
becb103c | 3743 | asm_fprintf (file, "{(%Rsp)|%Rsp@}"); |
79e68feb | 3744 | else if (letter == '!') |
e6d98cb0 | 3745 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3746 | else if (letter == '$') |
3747 | { | |
b101567e | 3748 | if (TARGET_68040) |
e6d98cb0 | 3749 | fprintf (file, "s"); |
79e68feb RS |
3750 | } |
3751 | else if (letter == '&') | |
3752 | { | |
b101567e | 3753 | if (TARGET_68040) |
e6d98cb0 | 3754 | fprintf (file, "d"); |
79e68feb | 3755 | } |
2ac5f14a | 3756 | else if (letter == '/') |
e6d98cb0 | 3757 | asm_fprintf (file, "%R"); |
a40ed0f3 KH |
3758 | else if (letter == '?') |
3759 | asm_fprintf (file, m68k_library_id_string); | |
29ca003a | 3760 | else if (letter == 'p') |
2c8ec431 | 3761 | { |
29ca003a RS |
3762 | output_addr_const (file, op); |
3763 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
3764 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 3765 | } |
79e68feb RS |
3766 | else if (GET_CODE (op) == REG) |
3767 | { | |
1a8965c4 AS |
3768 | if (letter == 'R') |
3769 | /* Print out the second register name of a register pair. | |
3770 | I.e., R (6) => 7. */ | |
01bbf777 | 3771 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3772 | else |
01bbf777 | 3773 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3774 | } |
3775 | else if (GET_CODE (op) == MEM) | |
3776 | { | |
3777 | output_address (XEXP (op, 0)); | |
3778 | if (letter == 'd' && ! TARGET_68020 | |
3779 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3780 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3781 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3782 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
becb103c | 3783 | asm_fprintf (file, "{.|:}l"); |
79e68feb | 3784 | } |
79e68feb RS |
3785 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3786 | { | |
c1cfb2ae RS |
3787 | REAL_VALUE_TYPE r; |
3788 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3789 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3790 | } | |
3791 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3792 | { | |
3793 | REAL_VALUE_TYPE r; | |
3794 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3795 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3796 | } |
e2c0a924 | 3797 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3798 | { |
c1cfb2ae RS |
3799 | REAL_VALUE_TYPE r; |
3800 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3801 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3802 | } |
3803 | else | |
3804 | { | |
2c8ec431 DL |
3805 | /* Use `print_operand_address' instead of `output_addr_const' |
3806 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3807 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3808 | if (TARGET_PCREL |
3809 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3810 | print_operand_address (file, op); | |
3811 | else | |
3812 | output_addr_const (file, op); | |
79e68feb RS |
3813 | } |
3814 | } | |
3815 | ||
3816 | \f | |
3817 | /* A C compound statement to output to stdio stream STREAM the | |
3818 | assembler syntax for an instruction operand that is a memory | |
3819 | reference whose address is ADDR. ADDR is an RTL expression. | |
3820 | ||
3821 | Note that this contains a kludge that knows that the only reason | |
3822 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3823 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3824 | generates a label LInnn: on such an insn. | |
3825 | ||
3826 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3827 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3828 | ||
79e68feb RS |
3829 | This routine is responsible for distinguishing between -fpic and -fPIC |
3830 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3831 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3832 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb RS |
3833 | |
3834 | void | |
8a4a2253 | 3835 | print_operand_address (FILE *file, rtx addr) |
79e68feb | 3836 | { |
fc2241eb RS |
3837 | struct m68k_address address; |
3838 | ||
3839 | if (!m68k_decompose_address (QImode, addr, true, &address)) | |
3840 | gcc_unreachable (); | |
3841 | ||
3842 | if (address.code == PRE_DEC) | |
becb103c KH |
3843 | asm_fprintf (file, "{-(%s)|%s@-}", |
3844 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb | 3845 | else if (address.code == POST_INC) |
becb103c KH |
3846 | asm_fprintf (file, "{(%s)+|%s@+}", |
3847 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb RS |
3848 | else if (!address.base && !address.index) |
3849 | { | |
3850 | /* A constant address. */ | |
3851 | gcc_assert (address.offset == addr); | |
3852 | if (GET_CODE (addr) == CONST_INT) | |
3853 | { | |
3854 | /* (xxx).w or (xxx).l. */ | |
3855 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
becb103c | 3856 | asm_fprintf (file, "%d{.|:}w", (int) INTVAL (addr)); |
a0a7fbc9 | 3857 | else |
fc2241eb | 3858 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
a0a7fbc9 | 3859 | } |
fc2241eb | 3860 | else if (TARGET_PCREL) |
a0a7fbc9 | 3861 | { |
fc2241eb RS |
3862 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
3863 | fputc ('(', file); | |
3864 | output_addr_const (file, addr); | |
3865 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
a0a7fbc9 | 3866 | } |
fc2241eb | 3867 | else |
a0a7fbc9 | 3868 | { |
fc2241eb RS |
3869 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
3870 | name ends in `.<letter>', as the last 2 characters can be | |
3871 | mistaken as a size suffix. Put the name in parentheses. */ | |
3872 | if (GET_CODE (addr) == SYMBOL_REF | |
3873 | && strlen (XSTR (addr, 0)) > 2 | |
3874 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
a0a7fbc9 | 3875 | { |
fc2241eb RS |
3876 | putc ('(', file); |
3877 | output_addr_const (file, addr); | |
3878 | putc (')', file); | |
a0a7fbc9 AS |
3879 | } |
3880 | else | |
fc2241eb | 3881 | output_addr_const (file, addr); |
a0a7fbc9 | 3882 | } |
fc2241eb RS |
3883 | } |
3884 | else | |
3885 | { | |
3886 | int labelno; | |
3887 | ||
3888 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
44c7bd63 | 3889 | label being accessed, otherwise it is -1. */ |
fc2241eb RS |
3890 | labelno = (address.offset |
3891 | && !address.base | |
3892 | && GET_CODE (address.offset) == LABEL_REF | |
3893 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
3894 | : -1); | |
3895 | if (MOTOROLA) | |
a0a7fbc9 | 3896 | { |
fc2241eb RS |
3897 | /* Print the "offset(base" component. */ |
3898 | if (labelno >= 0) | |
e59d83aa | 3899 | asm_fprintf (file, "%LL%d(%Rpc,", labelno); |
fc2241eb | 3900 | else |
a0a7fbc9 | 3901 | { |
fc2241eb | 3902 | if (address.offset) |
a0a7fbc9 | 3903 | { |
fc2241eb RS |
3904 | output_addr_const (file, address.offset); |
3905 | if (flag_pic && address.base == pic_offset_table_rtx) | |
a0a7fbc9 AS |
3906 | { |
3907 | fprintf (file, "@GOT"); | |
fc2241eb | 3908 | if (flag_pic == 1 && TARGET_68020) |
a0a7fbc9 AS |
3909 | fprintf (file, ".w"); |
3910 | } | |
3911 | } | |
fc2241eb RS |
3912 | putc ('(', file); |
3913 | if (address.base) | |
3914 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
a0a7fbc9 | 3915 | } |
fc2241eb RS |
3916 | /* Print the ",index" component, if any. */ |
3917 | if (address.index) | |
a0a7fbc9 | 3918 | { |
fc2241eb RS |
3919 | if (address.base) |
3920 | putc (',', file); | |
3921 | fprintf (file, "%s.%c", | |
3922 | M68K_REGNAME (REGNO (address.index)), | |
3923 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3924 | if (address.scale != 1) | |
3925 | fprintf (file, "*%d", address.scale); | |
a0a7fbc9 | 3926 | } |
a0a7fbc9 | 3927 | putc (')', file); |
a0a7fbc9 | 3928 | } |
fc2241eb | 3929 | else /* !MOTOROLA */ |
a0a7fbc9 | 3930 | { |
fc2241eb RS |
3931 | if (!address.offset && !address.index) |
3932 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
a0a7fbc9 | 3933 | else |
a0a7fbc9 | 3934 | { |
fc2241eb RS |
3935 | /* Print the "base@(offset" component. */ |
3936 | if (labelno >= 0) | |
e59d83aa | 3937 | asm_fprintf (file, "%Rpc@(%LL%d", labelno); |
fc2241eb RS |
3938 | else |
3939 | { | |
3940 | if (address.base) | |
3941 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
3942 | fprintf (file, "@("); | |
3943 | if (address.offset) | |
3944 | { | |
3945 | output_addr_const (file, address.offset); | |
3946 | if (address.base == pic_offset_table_rtx && TARGET_68020) | |
3947 | switch (flag_pic) | |
3948 | { | |
3949 | case 1: | |
3950 | fprintf (file, ":w"); break; | |
3951 | case 2: | |
3952 | fprintf (file, ":l"); break; | |
3953 | default: | |
3954 | break; | |
3955 | } | |
3956 | } | |
3957 | } | |
3958 | /* Print the ",index" component, if any. */ | |
3959 | if (address.index) | |
3960 | { | |
3961 | fprintf (file, ",%s:%c", | |
3962 | M68K_REGNAME (REGNO (address.index)), | |
3963 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3964 | if (address.scale != 1) | |
3965 | fprintf (file, ":%d", address.scale); | |
3966 | } | |
a0a7fbc9 AS |
3967 | putc (')', file); |
3968 | } | |
a0a7fbc9 | 3969 | } |
79e68feb RS |
3970 | } |
3971 | } | |
af13f02d JW |
3972 | \f |
3973 | /* Check for cases where a clr insns can be omitted from code using | |
3974 | strict_low_part sets. For example, the second clrl here is not needed: | |
3975 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3976 | ||
3977 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3978 | insn we are checking for redundancy. TARGET is the register set by the | |
3979 | clear insn. */ | |
3980 | ||
8a4a2253 BI |
3981 | bool |
3982 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3983 | rtx target) | |
af13f02d | 3984 | { |
39250081 | 3985 | rtx p = first_insn; |
af13f02d | 3986 | |
39250081 | 3987 | while ((p = PREV_INSN (p))) |
af13f02d | 3988 | { |
39250081 RZ |
3989 | if (NOTE_INSN_BASIC_BLOCK_P (p)) |
3990 | return false; | |
3991 | ||
3992 | if (NOTE_P (p)) | |
3993 | continue; | |
3994 | ||
af13f02d | 3995 | /* If it isn't an insn, then give up. */ |
39250081 | 3996 | if (!INSN_P (p)) |
8a4a2253 | 3997 | return false; |
af13f02d JW |
3998 | |
3999 | if (reg_set_p (target, p)) | |
4000 | { | |
4001 | rtx set = single_set (p); | |
4002 | rtx dest; | |
4003 | ||
4004 | /* If it isn't an easy to recognize insn, then give up. */ | |
4005 | if (! set) | |
8a4a2253 | 4006 | return false; |
af13f02d JW |
4007 | |
4008 | dest = SET_DEST (set); | |
4009 | ||
4010 | /* If this sets the entire target register to zero, then our | |
4011 | first_insn is redundant. */ | |
4012 | if (rtx_equal_p (dest, target) | |
4013 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 4014 | return true; |
af13f02d JW |
4015 | else if (GET_CODE (dest) == STRICT_LOW_PART |
4016 | && GET_CODE (XEXP (dest, 0)) == REG | |
4017 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
4018 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
4019 | <= GET_MODE_SIZE (mode))) | |
4020 | /* This is a strict low part set which modifies less than | |
4021 | we are using, so it is safe. */ | |
4022 | ; | |
4023 | else | |
8a4a2253 | 4024 | return false; |
af13f02d | 4025 | } |
af13f02d JW |
4026 | } |
4027 | ||
8a4a2253 | 4028 | return false; |
af13f02d | 4029 | } |
67cd4f83 | 4030 | |
2c8ec431 DL |
4031 | /* Operand predicates for implementing asymmetric pc-relative addressing |
4032 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 4033 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
4034 | |
4035 | We model this by restricting the meaning of the basic predicates | |
4036 | (general_operand, memory_operand, etc) to forbid the use of this | |
4037 | addressing mode, and then define the following predicates that permit | |
4038 | this addressing mode. These predicates can then be used for the | |
4039 | source operands of the appropriate instructions. | |
4040 | ||
4041 | n.b. While it is theoretically possible to change all machine patterns | |
4042 | to use this addressing more where permitted by the architecture, | |
4043 | it has only been implemented for "common" cases: SImode, HImode, and | |
4044 | QImode operands, and only for the principle operations that would | |
4045 | require this addressing mode: data movement and simple integer operations. | |
4046 | ||
4047 | In parallel with these new predicates, two new constraint letters | |
4048 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
4049 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
4050 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
4051 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
4052 | of how these constraints are used. | |
4053 | ||
4054 | The use of these predicates is strictly optional, though patterns that | |
4055 | don't will cause an extra reload register to be allocated where one | |
4056 | was not necessary: | |
4057 | ||
4058 | lea (abc:w,%pc),%a0 ; need to reload address | |
4059 | moveq &1,%d1 ; since write to pc-relative space | |
4060 | movel %d1,%a0@ ; is not allowed | |
4061 | ... | |
4062 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
4063 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
4064 | ||
4065 | For more info, consult tiemann@cygnus.com. | |
4066 | ||
4067 | ||
4068 | All of the ugliness with predicates and constraints is due to the | |
4069 | simple fact that the m68k does not allow a pc-relative addressing | |
4070 | mode as a destination. gcc does not distinguish between source and | |
4071 | destination addresses. Hence, if we claim that pc-relative address | |
4072 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
4073 | end up with invalid code. To get around this problem, we left | |
4074 | pc-relative modes as invalid addresses, and then added special | |
4075 | predicates and constraints to accept them. | |
4076 | ||
4077 | A cleaner way to handle this is to modify gcc to distinguish | |
4078 | between source and destination addresses. We can then say that | |
4079 | pc-relative is a valid source address but not a valid destination | |
4080 | address, and hopefully avoid a lot of the predicate and constraint | |
4081 | hackery. Unfortunately, this would be a pretty big change. It would | |
4082 | be a useful change for a number of ports, but there aren't any current | |
4083 | plans to undertake this. | |
4084 | ||
4085 | ***************************************************************************/ | |
4086 | ||
4087 | ||
5505f548 | 4088 | const char * |
8a4a2253 | 4089 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
4090 | { |
4091 | int logval; | |
4092 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 4093 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
4094 | && (DATA_REG_P (operands[0]) |
4095 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4096 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4097 | { |
4098 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4099 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 4100 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
4101 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4102 | CC_STATUS_INIT; | |
4103 | if (operands[2] == const0_rtx) | |
4104 | return "clr%.w %0"; | |
4105 | return "and%.w %2,%0"; | |
4106 | } | |
4107 | if (GET_CODE (operands[2]) == CONST_INT | |
4108 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
4109 | && (DATA_REG_P (operands[0]) | |
4110 | || offsettable_memref_p (operands[0]))) | |
4111 | { | |
4112 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 4113 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4114 | else |
4115 | { | |
b72f00af | 4116 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4117 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4118 | } |
4119 | /* This does not set condition codes in a standard way. */ | |
4120 | CC_STATUS_INIT; | |
4121 | return "bclr %1,%0"; | |
4122 | } | |
4123 | return "and%.l %2,%0"; | |
4124 | } | |
4125 | ||
5505f548 | 4126 | const char * |
8a4a2253 | 4127 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
4128 | { |
4129 | register int logval; | |
4130 | if (GET_CODE (operands[2]) == CONST_INT | |
4131 | && INTVAL (operands[2]) >> 16 == 0 | |
4132 | && (DATA_REG_P (operands[0]) | |
4133 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4134 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4135 | { |
4136 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4137 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4138 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4139 | CC_STATUS_INIT; | |
4140 | if (INTVAL (operands[2]) == 0xffff) | |
4141 | return "mov%.w %2,%0"; | |
4142 | return "or%.w %2,%0"; | |
4143 | } | |
4144 | if (GET_CODE (operands[2]) == CONST_INT | |
4145 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
4146 | && (DATA_REG_P (operands[0]) | |
4147 | || offsettable_memref_p (operands[0]))) | |
4148 | { | |
4149 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4150 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4151 | else |
4152 | { | |
b72f00af | 4153 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4154 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4155 | } |
4156 | CC_STATUS_INIT; | |
4157 | return "bset %1,%0"; | |
4158 | } | |
4159 | return "or%.l %2,%0"; | |
4160 | } | |
4161 | ||
5505f548 | 4162 | const char * |
8a4a2253 | 4163 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
4164 | { |
4165 | register int logval; | |
4166 | if (GET_CODE (operands[2]) == CONST_INT | |
4167 | && INTVAL (operands[2]) >> 16 == 0 | |
4168 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 4169 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4170 | { |
4171 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 4172 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4173 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4174 | CC_STATUS_INIT; | |
4175 | if (INTVAL (operands[2]) == 0xffff) | |
4176 | return "not%.w %0"; | |
4177 | return "eor%.w %2,%0"; | |
4178 | } | |
4179 | if (GET_CODE (operands[2]) == CONST_INT | |
4180 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
4181 | && (DATA_REG_P (operands[0]) | |
4182 | || offsettable_memref_p (operands[0]))) | |
4183 | { | |
4184 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4185 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4186 | else |
4187 | { | |
b72f00af | 4188 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4189 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4190 | } |
4191 | CC_STATUS_INIT; | |
4192 | return "bchg %1,%0"; | |
4193 | } | |
4194 | return "eor%.l %2,%0"; | |
4195 | } | |
7c262518 | 4196 | |
29ca003a RS |
4197 | /* Return the instruction that should be used for a call to address X, |
4198 | which is known to be in operand 0. */ | |
4199 | ||
4200 | const char * | |
4201 | output_call (rtx x) | |
4202 | { | |
4203 | if (symbolic_operand (x, VOIDmode)) | |
4204 | return m68k_symbolic_call; | |
4205 | else | |
4206 | return "jsr %a0"; | |
4207 | } | |
4208 | ||
f7e70894 RS |
4209 | /* Likewise sibling calls. */ |
4210 | ||
4211 | const char * | |
4212 | output_sibcall (rtx x) | |
4213 | { | |
4214 | if (symbolic_operand (x, VOIDmode)) | |
4215 | return m68k_symbolic_jump; | |
4216 | else | |
4217 | return "jmp %a0"; | |
4218 | } | |
4219 | ||
45849738 BI |
4220 | #ifdef M68K_TARGET_COFF |
4221 | ||
4222 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
4223 | ||
4224 | static void | |
c18a5b6c MM |
4225 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
4226 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
4227 | { |
4228 | char flagchar; | |
4229 | ||
4230 | if (flags & SECTION_WRITE) | |
4231 | flagchar = 'd'; | |
4232 | else | |
4233 | flagchar = 'x'; | |
4234 | ||
4235 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
4236 | } | |
4237 | ||
4238 | #endif /* M68K_TARGET_COFF */ | |
4239 | ||
c590b625 | 4240 | static void |
8a4a2253 | 4241 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
4ab870f5 | 4242 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
8a4a2253 | 4243 | tree function) |
483ab821 | 4244 | { |
4ab870f5 RS |
4245 | rtx this_slot, offset, addr, mem, insn; |
4246 | ||
4247 | /* Pretend to be a post-reload pass while generating rtl. */ | |
4ab870f5 | 4248 | reload_completed = 1; |
4ab870f5 RS |
4249 | |
4250 | /* The "this" pointer is stored at 4(%sp). */ | |
4251 | this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4)); | |
4252 | ||
4253 | /* Add DELTA to THIS. */ | |
4254 | if (delta != 0) | |
5050d266 | 4255 | { |
4ab870f5 RS |
4256 | /* Make the offset a legitimate operand for memory addition. */ |
4257 | offset = GEN_INT (delta); | |
4258 | if ((delta < -8 || delta > 8) | |
4259 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
4260 | { | |
4261 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
4262 | offset = gen_rtx_REG (Pmode, D0_REG); | |
4263 | } | |
4264 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4265 | copy_rtx (this_slot), offset)); | |
5050d266 | 4266 | } |
c590b625 | 4267 | |
4ab870f5 RS |
4268 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
4269 | if (vcall_offset != 0) | |
4270 | { | |
4271 | /* Set the static chain register to *THIS. */ | |
4272 | emit_move_insn (static_chain_rtx, this_slot); | |
4273 | emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx)); | |
4274 | ||
4275 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
4276 | addr = plus_constant (static_chain_rtx, vcall_offset); | |
4277 | if (!m68k_legitimate_address_p (Pmode, addr, true)) | |
4278 | { | |
4279 | emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr)); | |
4280 | addr = static_chain_rtx; | |
4281 | } | |
c590b625 | 4282 | |
4ab870f5 RS |
4283 | /* Load the offset into %d0 and add it to THIS. */ |
4284 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
4285 | gen_rtx_MEM (Pmode, addr)); | |
4286 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4287 | copy_rtx (this_slot), | |
4288 | gen_rtx_REG (Pmode, D0_REG))); | |
4289 | } | |
29ca003a | 4290 | |
4ab870f5 RS |
4291 | /* Jump to the target function. Use a sibcall if direct jumps are |
4292 | allowed, otherwise load the address into a register first. */ | |
4293 | mem = DECL_RTL (function); | |
4294 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
4295 | { | |
4296 | gcc_assert (flag_pic); | |
c590b625 | 4297 | |
4ab870f5 RS |
4298 | if (!TARGET_SEP_DATA) |
4299 | { | |
4300 | /* Use the static chain register as a temporary (call-clobbered) | |
4301 | GOT pointer for this function. We can use the static chain | |
4302 | register because it isn't live on entry to the thunk. */ | |
6fb5fa3c | 4303 | SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); |
4ab870f5 RS |
4304 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
4305 | } | |
4306 | legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx); | |
4307 | mem = replace_equiv_address (mem, static_chain_rtx); | |
4308 | } | |
4309 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
4310 | SIBLING_CALL_P (insn) = 1; | |
4311 | ||
4312 | /* Run just enough of rest_of_compilation. */ | |
4313 | insn = get_insns (); | |
4314 | split_all_insns_noflow (); | |
4315 | final_start_function (insn, file, 1); | |
4316 | final (insn, file, 1); | |
4317 | final_end_function (); | |
4318 | ||
4319 | /* Clean up the vars set above. */ | |
4320 | reload_completed = 0; | |
4ab870f5 RS |
4321 | |
4322 | /* Restore the original PIC register. */ | |
4323 | if (flag_pic) | |
6fb5fa3c | 4324 | SET_REGNO (pic_offset_table_rtx, PIC_REG); |
483ab821 | 4325 | } |
8636be86 KH |
4326 | |
4327 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
4328 | ||
4329 | static rtx | |
4330 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
4331 | int incoming ATTRIBUTE_UNUSED) | |
4332 | { | |
4333 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
4334 | } | |
cfca21cb PB |
4335 | |
4336 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
4337 | int | |
4338 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
4339 | unsigned int new_reg) | |
4340 | { | |
4341 | ||
4342 | /* Interrupt functions can only use registers that have already been | |
4343 | saved by the prologue, even if they would normally be | |
4344 | call-clobbered. */ | |
4345 | ||
a4242737 KH |
4346 | if ((m68k_get_function_kind (current_function_decl) |
4347 | == m68k_fk_interrupt_handler) | |
6fb5fa3c | 4348 | && !df_regs_ever_live_p (new_reg)) |
cfca21cb PB |
4349 | return 0; |
4350 | ||
4351 | return 1; | |
4352 | } | |
70028b61 | 4353 | |
ffa2596e RS |
4354 | /* Value is true if hard register REGNO can hold a value of machine-mode |
4355 | MODE. On the 68000, we let the cpu registers can hold any mode, but | |
4356 | restrict the 68881 registers to floating-point modes. */ | |
4357 | ||
70028b61 PB |
4358 | bool |
4359 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
4360 | { | |
36e04090 | 4361 | if (DATA_REGNO_P (regno)) |
70028b61 | 4362 | { |
a0a7fbc9 AS |
4363 | /* Data Registers, can hold aggregate if fits in. */ |
4364 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
4365 | return true; | |
70028b61 | 4366 | } |
36e04090 | 4367 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 4368 | { |
a0a7fbc9 AS |
4369 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
4370 | return true; | |
70028b61 | 4371 | } |
36e04090 | 4372 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
4373 | { |
4374 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
4375 | smaller. */ |
4376 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4377 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 4378 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 4379 | return true; |
70028b61 PB |
4380 | } |
4381 | return false; | |
4382 | } | |
dcc21c4c | 4383 | |
ffa2596e RS |
4384 | /* Implement SECONDARY_RELOAD_CLASS. */ |
4385 | ||
4386 | enum reg_class | |
4387 | m68k_secondary_reload_class (enum reg_class rclass, | |
4388 | enum machine_mode mode, rtx x) | |
4389 | { | |
4390 | int regno; | |
4391 | ||
4392 | regno = true_regnum (x); | |
4393 | ||
4394 | /* If one operand of a movqi is an address register, the other | |
4395 | operand must be a general register or constant. Other types | |
4396 | of operand must be reloaded through a data register. */ | |
4397 | if (GET_MODE_SIZE (mode) == 1 | |
4398 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
4399 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
4400 | return DATA_REGS; | |
4401 | ||
4402 | /* PC-relative addresses must be loaded into an address register first. */ | |
4403 | if (TARGET_PCREL | |
4404 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
4405 | && symbolic_operand (x, VOIDmode)) | |
4406 | return ADDR_REGS; | |
4407 | ||
4408 | return NO_REGS; | |
4409 | } | |
4410 | ||
4411 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
4412 | ||
4413 | enum reg_class | |
4414 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
4415 | { | |
4416 | enum reg_class secondary_class; | |
4417 | ||
4418 | /* If RCLASS might need a secondary reload, try restricting it to | |
4419 | a class that doesn't. */ | |
4420 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
4421 | if (secondary_class != NO_REGS | |
4422 | && reg_class_subset_p (secondary_class, rclass)) | |
4423 | return secondary_class; | |
4424 | ||
4425 | /* Prefer to use moveq for in-range constants. */ | |
4426 | if (GET_CODE (x) == CONST_INT | |
4427 | && reg_class_subset_p (DATA_REGS, rclass) | |
4428 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
4429 | return DATA_REGS; | |
4430 | ||
4431 | /* ??? Do we really need this now? */ | |
4432 | if (GET_CODE (x) == CONST_DOUBLE | |
4433 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
4434 | { | |
4435 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
4436 | return FP_REGS; | |
4437 | ||
4438 | return NO_REGS; | |
4439 | } | |
4440 | ||
4441 | return rclass; | |
4442 | } | |
4443 | ||
dcc21c4c PB |
4444 | /* Return floating point values in a 68881 register. This makes 68881 code |
4445 | a little bit faster. It also makes -msoft-float code incompatible with | |
4446 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 4447 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
4448 | If there is need for a hard-float ABI it is probably worth doing it |
4449 | properly and also passing function arguments in FP registers. */ | |
4450 | rtx | |
4451 | m68k_libcall_value (enum machine_mode mode) | |
4452 | { | |
4453 | switch (mode) { | |
4454 | case SFmode: | |
4455 | case DFmode: | |
4456 | case XFmode: | |
4457 | if (TARGET_68881) | |
8d989403 | 4458 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
4459 | break; |
4460 | default: | |
4461 | break; | |
4462 | } | |
8d989403 | 4463 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c PB |
4464 | } |
4465 | ||
4466 | rtx | |
586de218 | 4467 | m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
dcc21c4c PB |
4468 | { |
4469 | enum machine_mode mode; | |
4470 | ||
4471 | mode = TYPE_MODE (valtype); | |
4472 | switch (mode) { | |
4473 | case SFmode: | |
4474 | case DFmode: | |
4475 | case XFmode: | |
4476 | if (TARGET_68881) | |
8d989403 | 4477 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
4478 | break; |
4479 | default: | |
4480 | break; | |
4481 | } | |
4482 | ||
576c9028 KH |
4483 | /* If the function returns a pointer, push that into %a0. */ |
4484 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
4485 | /* For compatibility with the large body of existing code which | |
4486 | does not always properly declare external functions returning | |
4487 | pointer types, the m68k/SVR4 convention is to copy the value | |
4488 | returned for pointer functions from a0 to d0 in the function | |
4489 | epilogue, so that callers that have neglected to properly | |
4490 | declare the callee can still find the correct return value in | |
4491 | d0. */ | |
4492 | return gen_rtx_PARALLEL | |
4493 | (mode, | |
4494 | gen_rtvec (2, | |
4495 | gen_rtx_EXPR_LIST (VOIDmode, | |
4496 | gen_rtx_REG (mode, A0_REG), | |
4497 | const0_rtx), | |
4498 | gen_rtx_EXPR_LIST (VOIDmode, | |
4499 | gen_rtx_REG (mode, D0_REG), | |
4500 | const0_rtx))); | |
4501 | else if (POINTER_TYPE_P (valtype)) | |
4502 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 4503 | else |
576c9028 | 4504 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 4505 | } |
1c445f03 NS |
4506 | |
4507 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
4508 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT | |
4509 | static bool | |
4510 | m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4511 | { | |
4512 | enum machine_mode mode = TYPE_MODE (type); | |
4513 | ||
4514 | if (mode == BLKmode) | |
4515 | return true; | |
4516 | ||
4517 | /* If TYPE's known alignment is less than the alignment of MODE that | |
4518 | would contain the structure, then return in memory. We need to | |
4519 | do so to maintain the compatibility between code compiled with | |
4520 | -mstrict-align and that compiled with -mno-strict-align. */ | |
4521 | if (AGGREGATE_TYPE_P (type) | |
4522 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) | |
4523 | return true; | |
4524 | ||
4525 | return false; | |
4526 | } | |
4527 | #endif | |
c47b0cb4 MK |
4528 | |
4529 | /* CPU to schedule the program for. */ | |
4530 | enum attr_cpu m68k_sched_cpu; | |
4531 | ||
4532 | /* Operand type. */ | |
4533 | enum attr_op_type | |
4534 | { | |
4535 | /* No operand. */ | |
4536 | OP_TYPE_NONE, | |
4537 | ||
4538 | /* Register. */ | |
4539 | OP_TYPE_REG, | |
4540 | ||
4541 | /* Implicit mem reference (e.g. stack). */ | |
4542 | OP_TYPE_MEM1, | |
4543 | ||
4544 | /* Memory without offset or indexing. EA modes 2, 3 and 4. */ | |
4545 | OP_TYPE_MEM234, | |
4546 | ||
4547 | /* Memory with offset but without indexing. EA mode 5. */ | |
4548 | OP_TYPE_MEM5, | |
4549 | ||
4550 | /* Memory with indexing. EA mode 6. */ | |
4551 | OP_TYPE_MEM6, | |
4552 | ||
4553 | /* Memory referenced by absolute address. EA mode 7. */ | |
4554 | OP_TYPE_MEM7, | |
4555 | ||
4556 | /* Immediate operand that doesn't require extension word. */ | |
4557 | OP_TYPE_IMM_Q, | |
4558 | ||
4559 | /* Immediate 16 bit operand. */ | |
4560 | OP_TYPE_IMM_W, | |
4561 | ||
4562 | /* Immediate 32 bit operand. */ | |
4563 | OP_TYPE_IMM_L | |
4564 | }; | |
4565 | ||
4566 | /* True if current insn doesn't have complete pipeline description. */ | |
4567 | static bool sched_guess_p; | |
4568 | ||
4569 | /* Return type of memory ADDR_RTX refers to. */ | |
4570 | static enum attr_op_type | |
4571 | sched_address_type (enum machine_mode mode, rtx addr_rtx) | |
4572 | { | |
4573 | struct m68k_address address; | |
4574 | ||
4575 | if (!m68k_decompose_address (mode, addr_rtx, | |
4576 | reload_completed, &address)) | |
4577 | { | |
4578 | gcc_assert (sched_guess_p); | |
4579 | /* Reload will likely fix the address to be in the register. */ | |
4580 | return OP_TYPE_MEM234; | |
4581 | } | |
4582 | ||
4583 | if (address.scale != 0) | |
4584 | return OP_TYPE_MEM6; | |
4585 | ||
4586 | if (address.base != NULL_RTX) | |
4587 | { | |
4588 | if (address.offset == NULL_RTX) | |
4589 | return OP_TYPE_MEM234; | |
4590 | ||
4591 | return OP_TYPE_MEM5; | |
4592 | } | |
4593 | ||
4594 | gcc_assert (address.offset != NULL_RTX); | |
4595 | ||
4596 | return OP_TYPE_MEM7; | |
4597 | } | |
4598 | ||
4599 | /* Return type of the operand OP. | |
4600 | If ADDRESS_P is true, return type of memory location OP refers to. */ | |
4601 | static enum attr_op_type | |
4602 | sched_operand_type (rtx op, bool address_p) | |
4603 | { | |
4604 | gcc_assert (op != NULL_RTX); | |
4605 | ||
4606 | if (address_p) | |
4607 | return sched_address_type (QImode, op); | |
4608 | ||
4609 | if (memory_operand (op, VOIDmode)) | |
4610 | return sched_address_type (GET_MODE (op), XEXP (op, 0)); | |
4611 | ||
4612 | if (register_operand (op, VOIDmode)) | |
4613 | return OP_TYPE_REG; | |
4614 | ||
4615 | if (GET_CODE (op) == CONST_INT) | |
4616 | { | |
4617 | /* ??? Below condition should probably check if the operation is | |
4618 | signed or unsigned. */ | |
4619 | if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff)) | |
4620 | return OP_TYPE_IMM_W; | |
4621 | ||
4622 | return OP_TYPE_IMM_L; | |
4623 | } | |
4624 | ||
4625 | if (GET_CODE (op) == CONST_DOUBLE) | |
4626 | { | |
4627 | switch (GET_MODE (op)) | |
4628 | { | |
4629 | case SFmode: | |
4630 | return OP_TYPE_IMM_W; | |
4631 | ||
4632 | case VOIDmode: | |
4633 | case DFmode: | |
4634 | return OP_TYPE_IMM_L; | |
4635 | ||
4636 | default: | |
4637 | gcc_unreachable (); | |
4638 | } | |
4639 | } | |
4640 | ||
4641 | if (symbolic_operand (op, VOIDmode) | |
4642 | || LABEL_P (op)) | |
4643 | { | |
4644 | switch (GET_MODE (op)) | |
4645 | { | |
4646 | case QImode: | |
4647 | return OP_TYPE_IMM_Q; | |
4648 | ||
4649 | case HImode: | |
4650 | return OP_TYPE_IMM_W; | |
4651 | ||
4652 | case SImode: | |
4653 | return OP_TYPE_IMM_L; | |
4654 | ||
4655 | default: | |
4656 | if (GET_CODE (op) == SYMBOL_REF) | |
4657 | /* ??? Just a guess. Probably we can guess better using length | |
4658 | attribute of the instructions. */ | |
4659 | return OP_TYPE_IMM_W; | |
4660 | ||
4661 | return OP_TYPE_IMM_L; | |
4662 | } | |
4663 | } | |
4664 | ||
4665 | gcc_assert (sched_guess_p); | |
4666 | ||
4667 | return OP_TYPE_REG; | |
4668 | } | |
4669 | ||
4670 | /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). | |
4671 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
4672 | static enum attr_op_type | |
4673 | sched_attr_op_type (rtx insn, bool opx_p, bool address_p) | |
4674 | { | |
4675 | int i; | |
4676 | ||
4677 | extract_constrain_insn_cached (insn); | |
4678 | ||
4679 | if (opx_p) | |
4680 | i = get_attr_opx (insn); | |
4681 | else | |
4682 | i = get_attr_opy (insn); | |
4683 | ||
4684 | if (i >= recog_data.n_operands) | |
4685 | { | |
4686 | gcc_assert (sched_guess_p); | |
4687 | return OP_TYPE_REG; | |
4688 | } | |
4689 | ||
4690 | return sched_operand_type (recog_data.operand[i], address_p); | |
4691 | } | |
4692 | ||
4693 | /* Implement opx_type attribute. | |
4694 | Return type of INSN's operand X. | |
4695 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
4696 | enum attr_opx_type | |
4697 | m68k_sched_attr_opx_type (rtx insn, int address_p) | |
4698 | { | |
4699 | sched_guess_p = (get_attr_guess (insn) == GUESS_YES); | |
4700 | ||
4701 | switch (sched_attr_op_type (insn, true, address_p != 0)) | |
4702 | { | |
4703 | case OP_TYPE_REG: | |
4704 | return OPX_TYPE_REG; | |
4705 | ||
4706 | case OP_TYPE_MEM1: | |
4707 | return OPX_TYPE_MEM1; | |
4708 | ||
4709 | case OP_TYPE_MEM234: | |
4710 | return OPX_TYPE_MEM234; | |
4711 | ||
4712 | case OP_TYPE_MEM5: | |
4713 | return OPX_TYPE_MEM5; | |
4714 | ||
4715 | case OP_TYPE_MEM6: | |
4716 | return OPX_TYPE_MEM6; | |
4717 | ||
4718 | case OP_TYPE_MEM7: | |
4719 | return OPX_TYPE_MEM7; | |
4720 | ||
4721 | case OP_TYPE_IMM_Q: | |
4722 | return OPX_TYPE_IMM_Q; | |
4723 | ||
4724 | case OP_TYPE_IMM_W: | |
4725 | return OPX_TYPE_IMM_W; | |
4726 | ||
4727 | case OP_TYPE_IMM_L: | |
4728 | return OPX_TYPE_IMM_L; | |
4729 | ||
4730 | default: | |
4731 | gcc_unreachable (); | |
4732 | return 0; | |
4733 | } | |
4734 | } | |
4735 | ||
4736 | /* Implement opy_type attribute. | |
4737 | Return type of INSN's operand Y. | |
4738 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
4739 | enum attr_opy_type | |
4740 | m68k_sched_attr_opy_type (rtx insn, int address_p) | |
4741 | { | |
4742 | sched_guess_p = (get_attr_guess (insn) == GUESS_YES); | |
4743 | ||
4744 | switch (sched_attr_op_type (insn, false, address_p != 0)) | |
4745 | { | |
4746 | case OP_TYPE_REG: | |
4747 | return OPY_TYPE_REG; | |
4748 | ||
4749 | case OP_TYPE_MEM1: | |
4750 | return OPY_TYPE_MEM1; | |
4751 | ||
4752 | case OP_TYPE_MEM234: | |
4753 | return OPY_TYPE_MEM234; | |
4754 | ||
4755 | case OP_TYPE_MEM5: | |
4756 | return OPY_TYPE_MEM5; | |
4757 | ||
4758 | case OP_TYPE_MEM6: | |
4759 | return OPY_TYPE_MEM6; | |
4760 | ||
4761 | case OP_TYPE_MEM7: | |
4762 | return OPY_TYPE_MEM7; | |
4763 | ||
4764 | case OP_TYPE_IMM_Q: | |
4765 | return OPY_TYPE_IMM_Q; | |
4766 | ||
4767 | case OP_TYPE_IMM_W: | |
4768 | return OPY_TYPE_IMM_W; | |
4769 | ||
4770 | case OP_TYPE_IMM_L: | |
4771 | return OPY_TYPE_IMM_L; | |
4772 | ||
4773 | default: | |
4774 | gcc_unreachable (); | |
4775 | return 0; | |
4776 | } | |
4777 | } | |
4778 | ||
4779 | /* Return the size of INSN. */ | |
4780 | int | |
4781 | m68k_sched_attr_size (rtx insn) | |
4782 | { | |
4783 | int size; | |
4784 | ||
4785 | sched_guess_p = (get_attr_guess (insn) == GUESS_YES); | |
4786 | ||
4787 | switch (get_attr_type1 (insn)) | |
4788 | { | |
4789 | case TYPE1_MUL_L: | |
4790 | size = 2; | |
4791 | break; | |
4792 | ||
4793 | default: | |
4794 | size = 1; | |
4795 | break; | |
4796 | } | |
4797 | ||
4798 | switch (get_attr_opx_type (insn)) | |
4799 | { | |
4800 | case OPX_TYPE_NONE: | |
4801 | case OPX_TYPE_REG: | |
4802 | case OPX_TYPE_MEM1: | |
4803 | case OPX_TYPE_MEM234: | |
4804 | case OPY_TYPE_IMM_Q: | |
4805 | break; | |
4806 | ||
4807 | case OPX_TYPE_MEM5: | |
4808 | case OPX_TYPE_MEM6: | |
4809 | /* Here we assume that most absolute references are short. */ | |
4810 | case OPX_TYPE_MEM7: | |
4811 | case OPY_TYPE_IMM_W: | |
4812 | ++size; | |
4813 | break; | |
4814 | ||
4815 | case OPY_TYPE_IMM_L: | |
4816 | size += 2; | |
4817 | break; | |
4818 | ||
4819 | default: | |
4820 | gcc_unreachable (); | |
4821 | } | |
4822 | ||
4823 | switch (get_attr_opy_type (insn)) | |
4824 | { | |
4825 | case OPY_TYPE_NONE: | |
4826 | case OPY_TYPE_REG: | |
4827 | case OPY_TYPE_MEM1: | |
4828 | case OPY_TYPE_MEM234: | |
4829 | case OPY_TYPE_IMM_Q: | |
4830 | break; | |
4831 | ||
4832 | case OPY_TYPE_MEM5: | |
4833 | case OPY_TYPE_MEM6: | |
4834 | /* Here we assume that most absolute references are short. */ | |
4835 | case OPY_TYPE_MEM7: | |
4836 | case OPY_TYPE_IMM_W: | |
4837 | ++size; | |
4838 | break; | |
4839 | ||
4840 | case OPY_TYPE_IMM_L: | |
4841 | size += 2; | |
4842 | break; | |
4843 | ||
4844 | default: | |
4845 | gcc_unreachable (); | |
4846 | } | |
4847 | ||
4848 | if (size > 3) | |
4849 | { | |
4850 | gcc_assert (sched_guess_p); | |
4851 | ||
4852 | size = 3; | |
4853 | } | |
4854 | ||
4855 | return size; | |
4856 | } | |
4857 | ||
4858 | /* Implement op_mem attribute. */ | |
4859 | enum attr_op_mem | |
4860 | m68k_sched_attr_op_mem (rtx insn) | |
4861 | { | |
4862 | enum attr_opy_mem opy; | |
4863 | enum attr_opx_mem opx; | |
4864 | ||
4865 | sched_guess_p = (get_attr_guess (insn) == GUESS_YES); | |
4866 | ||
4867 | opy = get_attr_opy_mem (insn); | |
4868 | opx = get_attr_opx_mem (insn); | |
4869 | ||
4870 | if (opy == OPY_MEM_R && opx == OPX_MEM_R) | |
4871 | return OP_MEM_00; | |
4872 | ||
4873 | if (opy == OPY_MEM_R && opx == OPX_MEM_M) | |
4874 | { | |
4875 | switch (get_attr_opx_access (insn)) | |
4876 | { | |
4877 | case OPX_ACCESS_R: | |
4878 | return OP_MEM_10; | |
4879 | ||
4880 | case OPX_ACCESS_W: | |
4881 | return OP_MEM_01; | |
4882 | ||
4883 | case OPX_ACCESS_RW: | |
4884 | return OP_MEM_11; | |
4885 | ||
4886 | default: | |
4887 | gcc_assert (sched_guess_p); | |
4888 | return OP_MEM_UNKNOWN; | |
4889 | } | |
4890 | } | |
4891 | ||
4892 | if (opy == OPY_MEM_R && opx == OPX_MEM_I) | |
4893 | { | |
4894 | switch (get_attr_opx_access (insn)) | |
4895 | { | |
4896 | case OPX_ACCESS_R: | |
4897 | return OP_MEM_I0; | |
4898 | ||
4899 | case OPX_ACCESS_W: | |
4900 | return OP_MEM_0I; | |
4901 | ||
4902 | case OPX_ACCESS_RW: | |
4903 | return OP_MEM_I1; | |
4904 | ||
4905 | default: | |
4906 | gcc_assert (sched_guess_p); | |
4907 | return OP_MEM_UNKNOWN; | |
4908 | } | |
4909 | } | |
4910 | ||
4911 | if (opy == OPY_MEM_M && opx == OPX_MEM_R) | |
4912 | return OP_MEM_10; | |
4913 | ||
4914 | if (opy == OPY_MEM_M && opx == OPX_MEM_M) | |
4915 | { | |
4916 | switch (get_attr_opx_access (insn)) | |
4917 | { | |
4918 | case OPX_ACCESS_W: | |
4919 | return OP_MEM_11; | |
4920 | ||
4921 | default: | |
4922 | gcc_assert (sched_guess_p); | |
4923 | return OP_MEM_UNKNOWN; | |
4924 | } | |
4925 | } | |
4926 | ||
4927 | if (opy == OPY_MEM_M && opx == OPX_MEM_I) | |
4928 | { | |
4929 | switch (get_attr_opx_access (insn)) | |
4930 | { | |
4931 | case OPX_ACCESS_W: | |
4932 | return OP_MEM_1I; | |
4933 | ||
4934 | default: | |
4935 | gcc_assert (sched_guess_p); | |
4936 | return OP_MEM_UNKNOWN; | |
4937 | } | |
4938 | } | |
4939 | ||
4940 | if (opy == OPY_MEM_I && opx == OPX_MEM_R) | |
4941 | return OP_MEM_I0; | |
4942 | ||
4943 | ||
4944 | if (opy == OPY_MEM_I && opx == OPX_MEM_M) | |
4945 | { | |
4946 | switch (get_attr_opx_access (insn)) | |
4947 | { | |
4948 | case OPX_ACCESS_W: | |
4949 | return OP_MEM_I1; | |
4950 | ||
4951 | default: | |
4952 | gcc_assert (sched_guess_p); | |
4953 | return OP_MEM_UNKNOWN; | |
4954 | } | |
4955 | } | |
4956 | ||
4957 | gcc_assert (sched_guess_p); | |
4958 | return OP_MEM_UNKNOWN; | |
4959 | } | |
4960 | ||
4961 | /* Jump instructions types. Indexed by INSN_UID. | |
4962 | The same rtl insn can be expanded into different asm instructions | |
4963 | depending on the cc0_status. To properly determine type of jump | |
4964 | instructions we scan instruction stream and map jumps types to this | |
4965 | array. */ | |
4966 | static enum attr_type *sched_branch_type; | |
4967 | ||
4968 | /* Return the type of the jump insn. */ | |
4969 | enum attr_type | |
4970 | m68k_sched_branch_type (rtx insn) | |
4971 | { | |
4972 | enum attr_type type; | |
4973 | ||
4974 | type = sched_branch_type[INSN_UID (insn)]; | |
4975 | ||
4976 | gcc_assert (type != 0); | |
4977 | ||
4978 | return type; | |
4979 | } |