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Commit | Line | Data |
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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
a8c253d0 | 3 | 2001, 2003, 2004, 2005, 2006 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
20 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
79e68feb | 22 | |
79e68feb | 23 | #include "config.h" |
f5220a5d | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
da932f04 | 27 | #include "tree.h" |
79e68feb | 28 | #include "rtl.h" |
49ad7cfa | 29 | #include "function.h" |
79e68feb RS |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
79e68feb RS |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
1d8eaa6b | 37 | #include "recog.h" |
f5220a5d | 38 | #include "toplev.h" |
6d5f49b2 RH |
39 | #include "expr.h" |
40 | #include "reload.h" | |
5505f548 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
2cc07db4 | 44 | #include "debug.h" |
79e68feb RS |
45 | #include "flags.h" |
46 | ||
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
e6d98cb0 BI |
59 | /* The ASM_DOT macro allows easy string pasting to handle the differences |
60 | between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't | |
61 | support the %. option. */ | |
62 | #if MOTOROLA | |
63 | # define ASM_DOT "." | |
64 | # define ASM_DOTW ".w" | |
65 | # define ASM_DOTL ".l" | |
66 | #else | |
67 | # define ASM_DOT "" | |
68 | # define ASM_DOTW "" | |
69 | # define ASM_DOTL "" | |
70 | #endif | |
71 | ||
72 | ||
ff482c8d | 73 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
74 | struct m68k_frame |
75 | { | |
76 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 77 | HOST_WIDE_INT offset; |
3d74bc09 BI |
78 | |
79 | /* Offset of FPU registers. */ | |
80 | HOST_WIDE_INT foffset; | |
81 | ||
82 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 83 | HOST_WIDE_INT size; |
3d74bc09 BI |
84 | |
85 | /* Data and address register. */ | |
48ed72a4 PB |
86 | int reg_no; |
87 | unsigned int reg_mask; | |
88 | unsigned int reg_rev_mask; | |
3d74bc09 BI |
89 | |
90 | /* FPU registers. */ | |
48ed72a4 PB |
91 | int fpu_no; |
92 | unsigned int fpu_mask; | |
93 | unsigned int fpu_rev_mask; | |
3d74bc09 BI |
94 | |
95 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
96 | HOST_WIDE_INT frame_pointer_offset; |
97 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
98 | |
99 | /* Function which the above information refers to. */ | |
100 | int funcdef_no; | |
48ed72a4 PB |
101 | }; |
102 | ||
3d74bc09 BI |
103 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
104 | static struct m68k_frame current_frame; | |
105 | ||
4af06170 | 106 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
107 | static rtx find_addr_reg (rtx); |
108 | static const char *singlemove_string (rtx *); | |
109 | static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT); | |
110 | static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
45849738 | 111 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 112 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 113 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
114 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
115 | HOST_WIDE_INT, tree); | |
8636be86 | 116 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
117 | static bool m68k_interrupt_function_p (tree func); |
118 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, | |
119 | tree args, int flags, | |
120 | bool *no_add_attrs); | |
3d74bc09 | 121 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 122 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
8a4a2253 BI |
123 | static int const_int_cost (rtx); |
124 | static bool m68k_rtx_costs (rtx, int, int, int *); | |
79e68feb RS |
125 | \f |
126 | ||
a2ef3db7 | 127 | /* Specify the identification number of the library being built */ |
4af06170 | 128 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 129 | |
2b3600ac JL |
130 | /* Nonzero if the last compare/test insn had FP operands. The |
131 | sCC expanders peek at this to determine what to do for the | |
132 | 68060, which has no fsCC instructions. */ | |
133 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
134 | \f |
135 | /* Initialize the GCC target structure. */ | |
301d03af RS |
136 | |
137 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
138 | #undef TARGET_ASM_ALIGNED_HI_OP | |
139 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
140 | #endif | |
141 | ||
142 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
143 | #undef TARGET_ASM_BYTE_OP | |
144 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
145 | #undef TARGET_ASM_ALIGNED_HI_OP | |
146 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
147 | #undef TARGET_ASM_ALIGNED_SI_OP | |
148 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
149 | #endif | |
150 | ||
151 | #if INT_OP_GROUP == INT_OP_DC | |
152 | #undef TARGET_ASM_BYTE_OP | |
153 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
154 | #undef TARGET_ASM_ALIGNED_HI_OP | |
155 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
156 | #undef TARGET_ASM_ALIGNED_SI_OP | |
157 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
158 | #endif | |
159 | ||
160 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
161 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
162 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
163 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
164 | ||
08c148a8 NB |
165 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
166 | #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue | |
167 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
168 | #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue | |
ef1dbfb0 | 169 | |
c590b625 RH |
170 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
171 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 AS |
172 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
173 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 174 | |
1bc7c5b6 ZW |
175 | #undef TARGET_ASM_FILE_START_APP_OFF |
176 | #define TARGET_ASM_FILE_START_APP_OFF true | |
177 | ||
4af06170 | 178 | #undef TARGET_DEFAULT_TARGET_FLAGS |
900ec02d | 179 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT |
4af06170 RS |
180 | #undef TARGET_HANDLE_OPTION |
181 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
182 | ||
3c50106f RH |
183 | #undef TARGET_RTX_COSTS |
184 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
185 | ||
48ed72a4 PB |
186 | #undef TARGET_ATTRIBUTE_TABLE |
187 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
188 | ||
8636be86 KH |
189 | #undef TARGET_PROMOTE_PROTOTYPES |
190 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
191 | ||
192 | #undef TARGET_STRUCT_VALUE_RTX | |
193 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
194 | ||
48ed72a4 PB |
195 | static const struct attribute_spec m68k_attribute_table[] = |
196 | { | |
197 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
198 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, | |
199 | { NULL, 0, 0, false, false, false, NULL } | |
200 | }; | |
201 | ||
f6897b10 | 202 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 203 | \f |
900ec02d JB |
204 | /* Base flags for 68k ISAs. */ |
205 | #define FL_FOR_isa_00 FL_ISA_68000 | |
206 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
207 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
208 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
209 | not to. */ | |
210 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
211 | | FL_BITFIELD | FL_68881) | |
212 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
213 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
214 | ||
215 | /* Base flags for ColdFire ISAs. */ | |
216 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
217 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
218 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
219 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
220 | #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP) | |
221 | ||
222 | enum m68k_isa | |
223 | { | |
224 | /* Traditional 68000 instruction sets. */ | |
225 | isa_00, | |
226 | isa_10, | |
227 | isa_20, | |
228 | isa_40, | |
229 | isa_cpu32, | |
230 | /* ColdFire instruction set variants. */ | |
231 | isa_a, | |
232 | isa_aplus, | |
233 | isa_b, | |
234 | isa_c, | |
235 | isa_max | |
236 | }; | |
237 | ||
238 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
239 | struct m68k_target_selection | |
240 | { | |
241 | /* The argument being described. */ | |
242 | const char *name; | |
243 | ||
244 | /* For -mcpu, this is the device selected by the option. | |
245 | For -mtune and -march, it is a representative device | |
246 | for the microarchitecture or ISA respectively. */ | |
247 | enum target_device device; | |
248 | ||
249 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
250 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
251 | const char *family; | |
252 | enum uarch_type microarch; | |
253 | enum m68k_isa isa; | |
254 | unsigned long flags; | |
255 | }; | |
256 | ||
257 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
258 | static const struct m68k_target_selection all_devices[] = | |
259 | { | |
260 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
261 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
262 | #include "m68k-devices.def" | |
263 | #undef M68K_DEVICE | |
264 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
265 | }; | |
266 | ||
267 | /* A list of all ISAs, mapping each one to a representative device. | |
268 | Used for -march selection. */ | |
269 | static const struct m68k_target_selection all_isas[] = | |
270 | { | |
271 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
272 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
273 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
274 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
275 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
276 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
277 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
278 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
279 | | FL_CF_HWDIV) }, | |
280 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
281 | | FL_CF_HWDIV) }, | |
282 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
283 | { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c | |
284 | | FL_CF_FPU | |
285 | | FL_CF_EMAC) }, | |
286 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
287 | }; | |
288 | ||
289 | /* A list of all microarchitectures, mapping each one to a representative | |
290 | device. Used for -mtune selection. */ | |
291 | static const struct m68k_target_selection all_microarchs[] = | |
292 | { | |
293 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
294 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
295 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
296 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
297 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
298 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
299 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
300 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
301 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
302 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, | |
303 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
304 | | FL_CF_HWDIV) }, | |
305 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
306 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
307 | | FL_CF_USP | |
308 | | FL_CF_EMAC | |
309 | | FL_CF_FPU) }, | |
310 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
311 | }; | |
312 | \f | |
313 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
314 | or null for options that have not been used. */ | |
315 | const struct m68k_target_selection *m68k_cpu_entry; | |
316 | const struct m68k_target_selection *m68k_arch_entry; | |
317 | const struct m68k_target_selection *m68k_tune_entry; | |
318 | ||
319 | /* Which CPU we are generating code for. */ | |
320 | enum target_device m68k_cpu; | |
321 | ||
322 | /* Which microarchitecture to tune for. */ | |
323 | enum uarch_type m68k_tune; | |
324 | ||
325 | /* Which FPU to use. */ | |
326 | enum fpu_type m68k_fpu; | |
4af06170 | 327 | |
900ec02d JB |
328 | /* The set of FL_* flags that apply to the target processor. */ |
329 | unsigned int m68k_cpu_flags; | |
29ca003a RS |
330 | |
331 | /* Asm templates for calling or jumping to an arbitrary symbolic address, | |
332 | or NULL if such calls or jumps are not supported. The address is held | |
333 | in operand 0. */ | |
334 | const char *m68k_symbolic_call; | |
335 | const char *m68k_symbolic_jump; | |
900ec02d JB |
336 | \f |
337 | /* See whether TABLE has an entry with name NAME. Return true and | |
338 | store the entry in *ENTRY if so, otherwise return false and | |
339 | leave *ENTRY alone. */ | |
340 | ||
341 | static bool | |
342 | m68k_find_selection (const struct m68k_target_selection **entry, | |
343 | const struct m68k_target_selection *table, | |
344 | const char *name) | |
345 | { | |
346 | size_t i; | |
347 | ||
348 | for (i = 0; table[i].name; i++) | |
349 | if (strcmp (table[i].name, name) == 0) | |
350 | { | |
351 | *entry = table + i; | |
352 | return true; | |
353 | } | |
354 | return false; | |
355 | } | |
4af06170 RS |
356 | |
357 | /* Implement TARGET_HANDLE_OPTION. */ | |
358 | ||
359 | static bool | |
360 | m68k_handle_option (size_t code, const char *arg, int value) | |
361 | { | |
362 | switch (code) | |
363 | { | |
900ec02d JB |
364 | case OPT_march_: |
365 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
366 | ||
367 | case OPT_mcpu_: | |
368 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
369 | ||
370 | case OPT_mtune_: | |
371 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
372 | ||
4af06170 | 373 | case OPT_m5200: |
900ec02d | 374 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
375 | |
376 | case OPT_m5206e: | |
900ec02d | 377 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
378 | |
379 | case OPT_m528x: | |
900ec02d | 380 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
381 | |
382 | case OPT_m5307: | |
900ec02d | 383 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
384 | |
385 | case OPT_m5407: | |
900ec02d | 386 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 387 | |
dcc21c4c | 388 | case OPT_mcfv4e: |
900ec02d | 389 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 390 | |
4af06170 RS |
391 | case OPT_m68000: |
392 | case OPT_mc68000: | |
900ec02d | 393 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 394 | |
3197c489 | 395 | case OPT_m68010: |
900ec02d | 396 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 397 | |
4af06170 RS |
398 | case OPT_m68020: |
399 | case OPT_mc68020: | |
900ec02d | 400 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
401 | |
402 | case OPT_m68020_40: | |
900ec02d JB |
403 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
404 | "68020-40") | |
405 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
406 | |
407 | case OPT_m68020_60: | |
900ec02d JB |
408 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
409 | "68020-60") | |
410 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
411 | |
412 | case OPT_m68030: | |
900ec02d | 413 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
414 | |
415 | case OPT_m68040: | |
900ec02d | 416 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
417 | |
418 | case OPT_m68060: | |
900ec02d | 419 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
420 | |
421 | case OPT_m68302: | |
900ec02d | 422 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
423 | |
424 | case OPT_m68332: | |
425 | case OPT_mcpu32: | |
900ec02d | 426 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
427 | |
428 | case OPT_mshared_library_id_: | |
429 | if (value > MAX_LIBRARY_ID) | |
430 | error ("-mshared-library-id=%s is not between 0 and %d", | |
431 | arg, MAX_LIBRARY_ID); | |
432 | else | |
433 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
434 | return true; | |
435 | ||
436 | default: | |
437 | return true; | |
438 | } | |
439 | } | |
440 | ||
ef1dbfb0 RK |
441 | /* Sometimes certain combinations of command options do not make |
442 | sense on a particular target machine. You can define a macro | |
443 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
444 | defined, is executed once just after all the command options have | |
445 | been parsed. | |
446 | ||
447 | Don't use this macro to turn on various extra optimizations for | |
448 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
449 | ||
450 | void | |
8a4a2253 | 451 | override_options (void) |
ef1dbfb0 | 452 | { |
900ec02d JB |
453 | const struct m68k_target_selection *entry; |
454 | unsigned long target_mask; | |
455 | ||
456 | /* User can choose: | |
457 | ||
458 | -mcpu= | |
459 | -march= | |
460 | -mtune= | |
461 | ||
462 | -march=ARCH should generate code that runs any processor | |
463 | implementing architecture ARCH. -mcpu=CPU should override -march | |
464 | and should generate code that runs on processor CPU, making free | |
465 | use of any instructions that CPU understands. -mtune=UARCH applies | |
466 | on top of -mcpu or -march and optimises the code for UARCH. It does | |
467 | not change the target architecture. */ | |
468 | if (m68k_cpu_entry) | |
469 | { | |
470 | /* Complain if the -march setting is for a different microarchitecture, | |
471 | or includes flags that the -mcpu setting doesn't. */ | |
472 | if (m68k_arch_entry | |
473 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
474 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
475 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
476 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
477 | ||
478 | entry = m68k_cpu_entry; | |
479 | } | |
480 | else | |
481 | entry = m68k_arch_entry; | |
482 | ||
483 | if (!entry) | |
484 | entry = all_devices + TARGET_CPU_DEFAULT; | |
485 | ||
486 | m68k_cpu_flags = entry->flags; | |
487 | ||
488 | /* Use the architecture setting to derive default values for | |
489 | certain flags. */ | |
490 | target_mask = 0; | |
491 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) | |
492 | target_mask |= MASK_BITFIELD; | |
493 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
494 | target_mask |= MASK_CF_HWDIV; | |
495 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
496 | target_mask |= MASK_HARD_FLOAT; | |
497 | target_flags |= target_mask & ~target_flags_explicit; | |
498 | ||
499 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
500 | m68k_cpu = entry->device; | |
501 | if (m68k_tune_entry) | |
502 | m68k_tune = m68k_tune_entry->microarch; | |
503 | #ifdef M68K_DEFAULT_TUNE | |
504 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
505 | m68k_tune = M68K_DEFAULT_TUNE; | |
506 | #endif | |
507 | else | |
508 | m68k_tune = entry->microarch; | |
509 | ||
510 | /* Set the type of FPU. */ | |
511 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
512 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
513 | : FPUTYPE_68881); | |
514 | ||
58145e4d RS |
515 | if (TARGET_COLDFIRE_FPU) |
516 | { | |
517 | REAL_MODE_FORMAT (SFmode) = &coldfire_single_format; | |
518 | REAL_MODE_FORMAT (DFmode) = &coldfire_double_format; | |
519 | } | |
520 | ||
a2ef3db7 BI |
521 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
522 | * both specified together. Doing so simply doesn't make sense. | |
523 | */ | |
524 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
525 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
526 | ||
527 | /* If we're generating code for a separate A5 relative data segment, | |
528 | * we've got to enable -fPIC as well. This might be relaxable to | |
529 | * -fpic but it hasn't been tested properly. | |
530 | */ | |
531 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
532 | flag_pic = 2; | |
533 | ||
abe92a04 RS |
534 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
535 | error if the target does not support them. */ | |
536 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
537 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
538 | |
539 | /* ??? A historic way of turning on pic, or is this intended to | |
540 | be an embedded thing that doesn't have the same name binding | |
541 | significance that it does on hosted ELF systems? */ | |
542 | if (TARGET_PCREL && flag_pic == 0) | |
543 | flag_pic = 1; | |
544 | ||
29ca003a RS |
545 | if (!flag_pic) |
546 | { | |
547 | #if MOTOROLA && !defined (USE_GAS) | |
548 | m68k_symbolic_call = "jsr %a0"; | |
549 | m68k_symbolic_jump = "jmp %a0"; | |
550 | #else | |
551 | m68k_symbolic_call = "jbsr %a0"; | |
552 | m68k_symbolic_jump = "jra %a0"; | |
553 | #endif | |
554 | } | |
555 | else if (TARGET_ID_SHARED_LIBRARY) | |
556 | /* All addresses must be loaded from the GOT. */ | |
557 | ; | |
558 | else if (TARGET_68020 || TARGET_ISAB) | |
559 | { | |
560 | if (TARGET_PCREL) | |
561 | { | |
562 | m68k_symbolic_call = "bsr.l %c0"; | |
563 | m68k_symbolic_jump = "bra.l %c0"; | |
564 | } | |
565 | else | |
566 | { | |
567 | #if defined(USE_GAS) | |
568 | m68k_symbolic_call = "bsr.l %p0"; | |
569 | m68k_symbolic_jump = "bra.l %p0"; | |
570 | #else | |
571 | m68k_symbolic_call = "bsr %p0"; | |
572 | m68k_symbolic_jump = "bra %p0"; | |
573 | #endif | |
574 | } | |
575 | /* Turn off function cse if we are doing PIC. We always want | |
576 | function call to be done as `bsr foo@PLTPC'. */ | |
577 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
578 | clear how intentional that is. */ | |
579 | flag_no_function_cse = 1; | |
580 | } | |
adf2ac37 RH |
581 | |
582 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 583 | } |
7eb4f044 NS |
584 | |
585 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the | |
586 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
587 | if -mcpu was not passed. */ | |
588 | ||
589 | const char * | |
590 | m68k_cpp_cpu_ident (const char *prefix) | |
591 | { | |
592 | if (!m68k_cpu_entry) | |
593 | return NULL; | |
594 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
595 | } | |
596 | ||
597 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
598 | given argument and NAME is the name of the representative device for | |
599 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
600 | ||
601 | const char * | |
602 | m68k_cpp_cpu_family (const char *prefix) | |
603 | { | |
604 | if (!m68k_cpu_entry) | |
605 | return NULL; | |
606 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
607 | } | |
79e68feb | 608 | \f |
48ed72a4 PB |
609 | /* Return nonzero if FUNC is an interrupt function as specified by the |
610 | "interrupt_handler" attribute. */ | |
611 | static bool | |
612 | m68k_interrupt_function_p(tree func) | |
613 | { | |
614 | tree a; | |
615 | ||
616 | if (TREE_CODE (func) != FUNCTION_DECL) | |
617 | return false; | |
618 | ||
619 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); | |
620 | return (a != NULL_TREE); | |
621 | } | |
622 | ||
623 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
624 | struct attribute_spec.handler. */ | |
625 | static tree | |
626 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
627 | tree args ATTRIBUTE_UNUSED, | |
628 | int flags ATTRIBUTE_UNUSED, | |
629 | bool *no_add_attrs) | |
630 | { | |
631 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
632 | { | |
5c498b10 | 633 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
634 | IDENTIFIER_POINTER (name)); |
635 | *no_add_attrs = true; | |
636 | } | |
637 | ||
638 | return NULL_TREE; | |
639 | } | |
860c4900 BI |
640 | |
641 | static void | |
3d74bc09 | 642 | m68k_compute_frame_layout (void) |
860c4900 BI |
643 | { |
644 | int regno, saved; | |
645 | unsigned int mask, rmask; | |
48ed72a4 | 646 | bool interrupt_handler = m68k_interrupt_function_p (current_function_decl); |
860c4900 | 647 | |
3d74bc09 BI |
648 | /* Only compute the frame once per function. |
649 | Don't cache information until reload has been completed. */ | |
650 | if (current_frame.funcdef_no == current_function_funcdef_no | |
651 | && reload_completed) | |
652 | return; | |
653 | ||
654 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 BI |
655 | |
656 | mask = rmask = saved = 0; | |
657 | for (regno = 0; regno < 16; regno++) | |
48ed72a4 | 658 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 BI |
659 | { |
660 | mask |= 1 << regno; | |
661 | rmask |= 1 << (15 - regno); | |
662 | saved++; | |
663 | } | |
3d74bc09 BI |
664 | current_frame.offset = saved * 4; |
665 | current_frame.reg_no = saved; | |
666 | current_frame.reg_mask = mask; | |
667 | current_frame.reg_rev_mask = rmask; | |
860c4900 | 668 | |
57047680 GN |
669 | current_frame.foffset = 0; |
670 | mask = rmask = saved = 0; | |
dcc21c4c | 671 | if (TARGET_HARD_FLOAT) |
860c4900 | 672 | { |
860c4900 | 673 | for (regno = 16; regno < 24; regno++) |
3d74bc09 | 674 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 675 | { |
85802504 GN |
676 | mask |= 1 << (regno - 16); |
677 | rmask |= 1 << (23 - regno); | |
860c4900 BI |
678 | saved++; |
679 | } | |
dcc21c4c | 680 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 681 | current_frame.offset += current_frame.foffset; |
860c4900 | 682 | } |
57047680 GN |
683 | current_frame.fpu_no = saved; |
684 | current_frame.fpu_mask = mask; | |
685 | current_frame.fpu_rev_mask = rmask; | |
3d74bc09 BI |
686 | |
687 | /* Remember what function this frame refers to. */ | |
688 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
689 | } |
690 | ||
691 | HOST_WIDE_INT | |
692 | m68k_initial_elimination_offset (int from, int to) | |
693 | { | |
42b67c06 PB |
694 | int argptr_offset; |
695 | /* The arg pointer points 8 bytes before the start of the arguments, | |
696 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
697 | frame pointer in most frames. */ | |
698 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 699 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 700 | return argptr_offset; |
860c4900 | 701 | |
3d74bc09 | 702 | m68k_compute_frame_layout (); |
860c4900 | 703 | |
4761e388 NS |
704 | gcc_assert (to == STACK_POINTER_REGNUM); |
705 | switch (from) | |
706 | { | |
a0a7fbc9 | 707 | case ARG_POINTER_REGNUM: |
42b67c06 | 708 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
709 | case FRAME_POINTER_REGNUM: |
710 | return current_frame.offset + current_frame.size; | |
711 | default: | |
712 | gcc_unreachable (); | |
713 | } | |
860c4900 BI |
714 | } |
715 | ||
97c55091 GN |
716 | /* Refer to the array `regs_ever_live' to determine which registers |
717 | to save; `regs_ever_live[I]' is nonzero if register number I | |
718 | is ever used in the function. This function is responsible for | |
719 | knowing which registers should not be saved even if used. | |
720 | Return true if we need to save REGNO. */ | |
721 | ||
48ed72a4 PB |
722 | static bool |
723 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 724 | { |
b86ba8a3 AT |
725 | if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM) |
726 | { | |
727 | if (current_function_uses_pic_offset_table) | |
728 | return true; | |
729 | if (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY) | |
730 | return true; | |
731 | } | |
2cff4a6e AS |
732 | |
733 | if (current_function_calls_eh_return) | |
734 | { | |
735 | unsigned int i; | |
736 | for (i = 0; ; i++) | |
737 | { | |
738 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
739 | if (test == INVALID_REGNUM) | |
740 | break; | |
741 | if (test == regno) | |
48ed72a4 | 742 | return true; |
2cff4a6e AS |
743 | } |
744 | } | |
745 | ||
48ed72a4 PB |
746 | /* Fixed regs we never touch. */ |
747 | if (fixed_regs[regno]) | |
748 | return false; | |
749 | ||
750 | /* The frame pointer (if it is such) is handled specially. */ | |
751 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
752 | return false; | |
753 | ||
754 | /* Interrupt handlers must also save call_used_regs | |
755 | if they are live or when calling nested functions. */ | |
756 | if (interrupt_handler) | |
a0a7fbc9 AS |
757 | { |
758 | if (regs_ever_live[regno]) | |
759 | return true; | |
48ed72a4 | 760 | |
a0a7fbc9 AS |
761 | if (!current_function_is_leaf && call_used_regs[regno]) |
762 | return true; | |
763 | } | |
48ed72a4 PB |
764 | |
765 | /* Never need to save registers that aren't touched. */ | |
766 | if (!regs_ever_live[regno]) | |
767 | return false; | |
768 | ||
b2e08ed4 | 769 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 770 | return !call_used_regs[regno]; |
2cff4a6e AS |
771 | } |
772 | ||
79e68feb RS |
773 | /* This function generates the assembly code for function entry. |
774 | STREAM is a stdio stream to output the code to. | |
97c55091 | 775 | SIZE is an int: how many units of temporary storage to allocate. */ |
79e68feb | 776 | |
08c148a8 | 777 | static void |
a0a7fbc9 AS |
778 | m68k_output_function_prologue (FILE *stream, |
779 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
79e68feb | 780 | { |
860c4900 | 781 | HOST_WIDE_INT fsize_with_regs; |
08c148a8 | 782 | HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET; |
3d74bc09 BI |
783 | |
784 | m68k_compute_frame_layout(); | |
785 | ||
a157febd GK |
786 | /* If the stack limit is a symbol, we can check it here, |
787 | before actually allocating the space. */ | |
788 | if (current_function_limit_stack | |
789 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
e6d98cb0 BI |
790 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %I%s+%wd,%Rsp\n\ttrapcs\n", |
791 | XSTR (stack_limit_rtx, 0), current_frame.size + 4); | |
79e68feb | 792 | |
97c55091 | 793 | /* On ColdFire add register save into initial stack frame setup, if possible. */ |
a89e3f21 | 794 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
795 | if (TARGET_COLDFIRE) |
796 | { | |
797 | if (current_frame.reg_no > 2) | |
798 | fsize_with_regs += current_frame.reg_no * 4; | |
799 | if (current_frame.fpu_no) | |
800 | fsize_with_regs += current_frame.fpu_no * 8; | |
801 | } | |
860c4900 | 802 | |
79e68feb RS |
803 | if (frame_pointer_needed) |
804 | { | |
fe95f2f7 | 805 | if (current_frame.size == 0 && TUNE_68040) |
e4e873f1 | 806 | /* on the 68040, pea + move is faster than link.w 0 */ |
a0a7fbc9 AS |
807 | fprintf (stream, (MOTOROLA |
808 | ? "\tpea (%s)\n\tmove.l %s,%s\n" | |
809 | : "\tpea %s@\n\tmovel %s,%s\n"), | |
810 | M68K_REGNAME (FRAME_POINTER_REGNUM), | |
811 | M68K_REGNAME (STACK_POINTER_REGNUM), | |
812 | M68K_REGNAME (FRAME_POINTER_REGNUM)); | |
860c4900 | 813 | else if (fsize_with_regs < 0x8000) |
e6d98cb0 | 814 | asm_fprintf (stream, "\tlink" ASM_DOTW " %s,%I%wd\n", |
a0a7fbc9 | 815 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 816 | else if (TARGET_68020) |
e6d98cb0 | 817 | asm_fprintf (stream, "\tlink" ASM_DOTL " %s,%I%wd\n", |
a0a7fbc9 | 818 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 819 | else |
e6d98cb0 | 820 | /* Adding negative number is faster on the 68040. */ |
a0a7fbc9 AS |
821 | asm_fprintf (stream, |
822 | "\tlink" ASM_DOTW " %s,%I0\n" | |
823 | "\tadd" ASM_DOT "l %I%wd,%Rsp\n", | |
824 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); | |
79e68feb | 825 | } |
860c4900 | 826 | else if (fsize_with_regs) /* !frame_pointer_needed */ |
79e68feb | 827 | { |
860c4900 | 828 | if (fsize_with_regs < 0x8000) |
79e68feb | 829 | { |
860c4900 | 830 | if (fsize_with_regs <= 8) |
afaff477 | 831 | { |
9425fb04 | 832 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
833 | asm_fprintf (stream, "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", |
834 | fsize_with_regs); | |
7bc88d49 | 835 | else |
e6d98cb0 BI |
836 | asm_fprintf (stream, "\tsubq" ASM_DOT "l %I%wd,%Rsp\n", |
837 | fsize_with_regs); | |
afaff477 | 838 | } |
fe95f2f7 | 839 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
e6d98cb0 BI |
840 | /* On the CPU32 it is faster to use two subqw instructions to |
841 | subtract a small integer (8 < N <= 16) to a register. */ | |
842 | asm_fprintf (stream, | |
843 | "\tsubq" ASM_DOT "w %I8,%Rsp\n" | |
844 | "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", | |
845 | fsize_with_regs - 8); | |
fe95f2f7 | 846 | else if (TUNE_68040) |
e6d98cb0 BI |
847 | /* Adding negative number is faster on the 68040. */ |
848 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", | |
849 | -fsize_with_regs); | |
7bc88d49 | 850 | else |
a0a7fbc9 AS |
851 | asm_fprintf (stream, (MOTOROLA |
852 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
853 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 854 | -fsize_with_regs); |
79e68feb | 855 | } |
860c4900 | 856 | else /* fsize_with_regs >= 0x8000 */ |
a0a7fbc9 AS |
857 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", |
858 | -fsize_with_regs); | |
d9e88af0 | 859 | } /* !frame_pointer_needed */ |
e6d98cb0 | 860 | |
d9e88af0 PB |
861 | if (dwarf2out_do_frame ()) |
862 | { | |
863 | if (frame_pointer_needed) | |
078e983e | 864 | { |
b214e1e7 | 865 | char *l; |
d9e88af0 | 866 | l = (char *) dwarf2out_cfi_label (); |
b214e1e7 PB |
867 | cfa_offset += 4; |
868 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_offset); | |
869 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset); | |
870 | cfa_offset += current_frame.size; | |
871 | } | |
d9e88af0 | 872 | else |
b214e1e7 PB |
873 | { |
874 | cfa_offset += current_frame.size; | |
875 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); | |
876 | } | |
d9e88af0 | 877 | } |
860c4900 | 878 | |
57047680 | 879 | if (current_frame.fpu_mask) |
79e68feb | 880 | { |
dcc21c4c PB |
881 | if (TARGET_68881) |
882 | { | |
883 | asm_fprintf (stream, (MOTOROLA | |
884 | ? "\tfmovm %I0x%x,-(%Rsp)\n" | |
885 | : "\tfmovem %I0x%x,%Rsp@-\n"), | |
886 | current_frame.fpu_mask); | |
887 | } | |
888 | else | |
889 | { | |
890 | int offset; | |
891 | ||
892 | /* stack already has registers in it. Find the offset from | |
893 | the bottom of stack to where the FP registers go */ | |
894 | if (current_frame.reg_no <= 2) | |
895 | offset = 0; | |
896 | else | |
897 | offset = current_frame.reg_no * 4; | |
898 | if (offset) | |
899 | asm_fprintf (stream, | |
900 | "\tfmovem %I0x%x,%d(%Rsp)\n", | |
901 | current_frame.fpu_rev_mask, | |
902 | offset); | |
903 | else | |
904 | asm_fprintf (stream, | |
905 | "\tfmovem %I0x%x,(%Rsp)\n", | |
906 | current_frame.fpu_rev_mask); | |
907 | } | |
e6d98cb0 | 908 | |
57047680 GN |
909 | if (dwarf2out_do_frame ()) |
910 | { | |
911 | char *l = (char *) dwarf2out_cfi_label (); | |
912 | int n_regs, regno; | |
913 | ||
dcc21c4c | 914 | cfa_offset += current_frame.fpu_no * TARGET_FP_REG_SIZE; |
57047680 GN |
915 | if (! frame_pointer_needed) |
916 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
917 | for (regno = 16, n_regs = 0; regno < 24; regno++) | |
918 | if (current_frame.fpu_mask & (1 << (regno - 16))) | |
dcc21c4c PB |
919 | dwarf2out_reg_save (l, regno, -cfa_offset |
920 | + n_regs++ * TARGET_FP_REG_SIZE); | |
f277471f | 921 | } |
79e68feb | 922 | } |
99df2465 | 923 | |
01bbf777 | 924 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
925 | This has the disadvantage that it may be too late... */ |
926 | if (current_function_limit_stack) | |
927 | { | |
928 | if (REG_P (stack_limit_rtx)) | |
e6d98cb0 | 929 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %s,%Rsp\n\ttrapcs\n", |
a0a7fbc9 | 930 | M68K_REGNAME (REGNO (stack_limit_rtx))); |
a157febd | 931 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 932 | warning (0, "stack limit expression is not supported"); |
a157febd | 933 | } |
01bbf777 | 934 | |
a89e3f21 | 935 | if (current_frame.reg_no <= 2) |
79e68feb RS |
936 | { |
937 | /* Store each separately in the same order moveml uses. | |
938 | Using two movel instructions instead of a single moveml | |
939 | is about 15% faster for the 68020 and 68030 at no expense | |
97c55091 | 940 | in code size. */ |
79e68feb RS |
941 | |
942 | int i; | |
943 | ||
3d74bc09 BI |
944 | for (i = 0; i < 16; i++) |
945 | if (current_frame.reg_rev_mask & (1 << i)) | |
078e983e | 946 | { |
a0a7fbc9 AS |
947 | asm_fprintf (stream, (MOTOROLA |
948 | ? "\t%Omove.l %s,-(%Rsp)\n" | |
949 | : "\tmovel %s,%Rsp@-\n"), | |
950 | M68K_REGNAME (15 - i)); | |
078e983e AS |
951 | if (dwarf2out_do_frame ()) |
952 | { | |
f5c4bc60 | 953 | char *l = (char *) dwarf2out_cfi_label (); |
a7cc7f29 | 954 | |
ed311a33 | 955 | cfa_offset += 4; |
01bbf777 AS |
956 | if (! frame_pointer_needed) |
957 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
958 | dwarf2out_reg_save (l, 15 - i, -cfa_offset); | |
078e983e AS |
959 | } |
960 | } | |
79e68feb | 961 | } |
3d74bc09 | 962 | else if (current_frame.reg_rev_mask) |
79e68feb | 963 | { |
9425fb04 | 964 | if (TARGET_COLDFIRE) |
01bbf777 | 965 | /* The ColdFire does not support the predecrement form of the |
e6d98cb0 BI |
966 | MOVEM instruction, so we must adjust the stack pointer and |
967 | then use the plain address register indirect mode. | |
968 | The required register save space was combined earlier with | |
969 | the fsize_with_regs amount. */ | |
970 | ||
a0a7fbc9 AS |
971 | asm_fprintf (stream, (MOTOROLA |
972 | ? "\tmovm.l %I0x%x,(%Rsp)\n" | |
973 | : "\tmoveml %I0x%x,%Rsp@\n"), | |
e6d98cb0 | 974 | current_frame.reg_mask); |
afaff477 | 975 | else |
a0a7fbc9 AS |
976 | asm_fprintf (stream, (MOTOROLA |
977 | ? "\tmovm.l %I0x%x,-(%Rsp)\n" | |
978 | : "\tmoveml %I0x%x,%Rsp@-\n"), | |
e6d98cb0 | 979 | current_frame.reg_rev_mask); |
078e983e AS |
980 | if (dwarf2out_do_frame ()) |
981 | { | |
f5c4bc60 | 982 | char *l = (char *) dwarf2out_cfi_label (); |
3d74bc09 | 983 | int n_regs, regno; |
a7cc7f29 | 984 | |
3d74bc09 | 985 | cfa_offset += current_frame.reg_no * 4; |
078e983e | 986 | if (! frame_pointer_needed) |
ed311a33 | 987 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); |
078e983e | 988 | for (regno = 0, n_regs = 0; regno < 16; regno++) |
3d74bc09 | 989 | if (current_frame.reg_mask & (1 << regno)) |
57047680 | 990 | dwarf2out_reg_save (l, regno, -cfa_offset + n_regs++ * 4); |
078e983e | 991 | } |
79e68feb | 992 | } |
a0a7fbc9 AS |
993 | if (!TARGET_SEP_DATA && flag_pic |
994 | && (current_function_uses_pic_offset_table | |
995 | || (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY))) | |
79e68feb | 996 | { |
a2ef3db7 BI |
997 | if (TARGET_ID_SHARED_LIBRARY) |
998 | { | |
999 | asm_fprintf (stream, "\tmovel %s@(%s), %s\n", | |
a0a7fbc9 | 1000 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
a2ef3db7 | 1001 | m68k_library_id_string, |
a0a7fbc9 | 1002 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
a2ef3db7 BI |
1003 | } |
1004 | else | |
1005 | { | |
e6d98cb0 | 1006 | if (MOTOROLA) |
a0a7fbc9 AS |
1007 | asm_fprintf (stream, |
1008 | "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", | |
1009 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 BI |
1010 | else |
1011 | { | |
1012 | asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n", | |
a0a7fbc9 | 1013 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
e6d98cb0 | 1014 | asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", |
a0a7fbc9 AS |
1015 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
1016 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 | 1017 | } |
a2ef3db7 | 1018 | } |
79e68feb RS |
1019 | } |
1020 | } | |
1021 | \f | |
413ac1b2 RS |
1022 | /* Return true if a simple (return) instruction is sufficient for this |
1023 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1024 | |
3d74bc09 | 1025 | bool |
a2bda628 | 1026 | m68k_use_return_insn (void) |
79e68feb | 1027 | { |
79e68feb | 1028 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1029 | return false; |
125ed86f | 1030 | |
a0a7fbc9 | 1031 | m68k_compute_frame_layout (); |
413ac1b2 | 1032 | return current_frame.offset == 0; |
79e68feb RS |
1033 | } |
1034 | ||
1035 | /* This function generates the assembly code for function exit, | |
08c148a8 | 1036 | on machines that need it. |
79e68feb RS |
1037 | |
1038 | The function epilogue should not depend on the current stack pointer! | |
1039 | It should use the frame pointer only, if there is a frame pointer. | |
1040 | This is mandatory because of alloca; we also take advantage of it to | |
1041 | omit stack adjustments before returning. */ | |
1042 | ||
08c148a8 | 1043 | static void |
a0a7fbc9 AS |
1044 | m68k_output_function_epilogue (FILE *stream, |
1045 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
08c148a8 | 1046 | { |
3d74bc09 BI |
1047 | HOST_WIDE_INT fsize, fsize_with_regs; |
1048 | bool big = false; | |
1049 | bool restore_from_sp = false; | |
79e68feb | 1050 | rtx insn = get_last_insn (); |
3d74bc09 | 1051 | |
a0a7fbc9 | 1052 | m68k_compute_frame_layout (); |
3d74bc09 | 1053 | |
79e68feb RS |
1054 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
1055 | if (GET_CODE (insn) == NOTE) | |
1056 | insn = prev_nonnote_insn (insn); | |
1057 | if (insn && GET_CODE (insn) == BARRIER) | |
dfd05074 | 1058 | return; |
79e68feb | 1059 | |
3d74bc09 BI |
1060 | fsize = current_frame.size; |
1061 | ||
a0a7fbc9 | 1062 | /* FIXME: leaf_function_p below is too strong. |
c67ddce5 | 1063 | What we really need to know there is if there could be pending |
7a1929e1 | 1064 | stack adjustment needed at that point. */ |
a0a7fbc9 AS |
1065 | restore_from_sp |
1066 | = (! frame_pointer_needed | |
1067 | || (! current_function_calls_alloca && leaf_function_p ())); | |
860c4900 BI |
1068 | |
1069 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1070 | popping the frame. */ |
860c4900 BI |
1071 | fsize_with_regs = fsize; |
1072 | ||
1073 | /* Because the ColdFire doesn't support moveml with | |
1074 | complex address modes, we must adjust the stack manually | |
1075 | after restoring registers. When the frame pointer isn't used, | |
1076 | we can merge movem adjustment into frame unlinking | |
97c55091 | 1077 | made immediately after it. */ |
dcc21c4c PB |
1078 | if (TARGET_COLDFIRE && restore_from_sp) |
1079 | { | |
1080 | if (current_frame.reg_no > 2) | |
1081 | fsize_with_regs += current_frame.reg_no * 4; | |
1082 | if (current_frame.fpu_no) | |
1083 | fsize_with_regs += current_frame.fpu_no * 8; | |
1084 | } | |
860c4900 | 1085 | |
3d74bc09 | 1086 | if (current_frame.offset + fsize >= 0x8000 |
6910dd70 | 1087 | && ! restore_from_sp |
3d74bc09 | 1088 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1089 | { |
860c4900 | 1090 | /* Because the ColdFire doesn't support moveml with |
97c55091 | 1091 | complex address modes we make an extra correction here. */ |
860c4900 | 1092 | if (TARGET_COLDFIRE) |
e6d98cb0 | 1093 | fsize += current_frame.offset; |
860c4900 | 1094 | |
e6d98cb0 | 1095 | asm_fprintf (stream, "\t%Omove" ASM_DOT "l %I%wd,%Ra1\n", -fsize); |
3d74bc09 | 1096 | fsize = 0, big = true; |
79e68feb | 1097 | } |
3d74bc09 | 1098 | if (current_frame.reg_no <= 2) |
79e68feb RS |
1099 | { |
1100 | /* Restore each separately in the same order moveml does. | |
1101 | Using two movel instructions instead of a single moveml | |
1102 | is about 15% faster for the 68020 and 68030 at no expense | |
7a1929e1 | 1103 | in code size. */ |
79e68feb RS |
1104 | |
1105 | int i; | |
3d74bc09 | 1106 | HOST_WIDE_INT offset = current_frame.offset + fsize; |
79e68feb | 1107 | |
3d74bc09 BI |
1108 | for (i = 0; i < 16; i++) |
1109 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb RS |
1110 | { |
1111 | if (big) | |
1112 | { | |
e6d98cb0 BI |
1113 | if (MOTOROLA) |
1114 | asm_fprintf (stream, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n", | |
1115 | offset, | |
a0a7fbc9 AS |
1116 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1117 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1118 | else |
1119 | asm_fprintf (stream, "\tmovel %s@(-%wd,%Ra1:l),%s\n", | |
a0a7fbc9 | 1120 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1121 | offset, |
a0a7fbc9 | 1122 | M68K_REGNAME (i)); |
79e68feb | 1123 | } |
6910dd70 | 1124 | else if (restore_from_sp) |
a0a7fbc9 AS |
1125 | asm_fprintf (stream, (MOTOROLA |
1126 | ? "\t%Omove.l (%Rsp)+,%s\n" | |
1127 | : "\tmovel %Rsp@+,%s\n"), | |
1128 | M68K_REGNAME (i)); | |
79e68feb RS |
1129 | else |
1130 | { | |
e6d98cb0 BI |
1131 | if (MOTOROLA) |
1132 | asm_fprintf (stream, "\t%Omove.l -%wd(%s),%s\n", | |
1133 | offset, | |
a0a7fbc9 AS |
1134 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1135 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1136 | else |
1137 | asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n", | |
a0a7fbc9 | 1138 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1139 | offset, |
a0a7fbc9 | 1140 | M68K_REGNAME (i)); |
79e68feb | 1141 | } |
3d74bc09 | 1142 | offset -= 4; |
79e68feb RS |
1143 | } |
1144 | } | |
3d74bc09 | 1145 | else if (current_frame.reg_mask) |
79e68feb | 1146 | { |
a0a7fbc9 AS |
1147 | /* The ColdFire requires special handling due to its limited moveml |
1148 | insn. */ | |
860c4900 BI |
1149 | if (TARGET_COLDFIRE) |
1150 | { | |
1151 | if (big) | |
1152 | { | |
e6d98cb0 | 1153 | asm_fprintf (stream, "\tadd" ASM_DOT "l %s,%Ra1\n", |
a0a7fbc9 AS |
1154 | M68K_REGNAME (FRAME_POINTER_REGNUM)); |
1155 | asm_fprintf (stream, (MOTOROLA | |
1156 | ? "\tmovm.l (%Ra1),%I0x%x\n" | |
1157 | : "\tmoveml %Ra1@,%I0x%x\n"), | |
e6d98cb0 | 1158 | current_frame.reg_mask); |
860c4900 BI |
1159 | } |
1160 | else if (restore_from_sp) | |
a0a7fbc9 AS |
1161 | asm_fprintf (stream, (MOTOROLA |
1162 | ? "\tmovm.l (%Rsp),%I0x%x\n" | |
1163 | : "\tmoveml %Rsp@,%I0x%x\n"), | |
e6d98cb0 | 1164 | current_frame.reg_mask); |
860c4900 BI |
1165 | else |
1166 | { | |
e6d98cb0 BI |
1167 | if (MOTOROLA) |
1168 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1169 | current_frame.offset + fsize, | |
a0a7fbc9 | 1170 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1171 | current_frame.reg_mask); |
1172 | else | |
1173 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1174 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1175 | current_frame.offset + fsize, |
1176 | current_frame.reg_mask); | |
860c4900 BI |
1177 | } |
1178 | } | |
1179 | else /* !TARGET_COLDFIRE */ | |
79e68feb | 1180 | { |
860c4900 BI |
1181 | if (big) |
1182 | { | |
e6d98cb0 BI |
1183 | if (MOTOROLA) |
1184 | asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n", | |
1185 | current_frame.offset + fsize, | |
a0a7fbc9 | 1186 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1187 | current_frame.reg_mask); |
1188 | else | |
1189 | asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1190 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1191 | current_frame.offset + fsize, |
1192 | current_frame.reg_mask); | |
860c4900 BI |
1193 | } |
1194 | else if (restore_from_sp) | |
1195 | { | |
a0a7fbc9 AS |
1196 | asm_fprintf (stream, (MOTOROLA |
1197 | ? "\tmovm.l (%Rsp)+,%I0x%x\n" | |
1198 | : "\tmoveml %Rsp@+,%I0x%x\n"), | |
3d74bc09 | 1199 | current_frame.reg_mask); |
860c4900 BI |
1200 | } |
1201 | else | |
1202 | { | |
e6d98cb0 BI |
1203 | if (MOTOROLA) |
1204 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1205 | current_frame.offset + fsize, | |
a0a7fbc9 | 1206 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1207 | current_frame.reg_mask); |
1208 | else | |
1209 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1210 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1211 | current_frame.offset + fsize, |
1212 | current_frame.reg_mask); | |
860c4900 | 1213 | } |
79e68feb RS |
1214 | } |
1215 | } | |
3d74bc09 | 1216 | if (current_frame.fpu_rev_mask) |
79e68feb RS |
1217 | { |
1218 | if (big) | |
1219 | { | |
dcc21c4c PB |
1220 | if (TARGET_COLDFIRE) |
1221 | { | |
1222 | if (current_frame.reg_no) | |
1223 | asm_fprintf (stream, MOTOROLA ? | |
1224 | "\tfmovem.d %d(%Ra1),%I0x%x\n" : | |
1225 | "\tfmovmd (%d,%Ra1),%I0x%x\n", | |
1226 | current_frame.reg_no * 4, | |
1227 | current_frame.fpu_rev_mask); | |
1228 | else | |
1229 | asm_fprintf (stream, MOTOROLA ? | |
1230 | "\tfmovem.d (%Ra1),%I0x%x\n" : | |
1231 | "\tfmovmd (%Ra1),%I0x%x\n", | |
1232 | current_frame.fpu_rev_mask); | |
1233 | } | |
1234 | else if (MOTOROLA) | |
e6d98cb0 BI |
1235 | asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n", |
1236 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1237 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1238 | current_frame.fpu_rev_mask); |
1239 | else | |
1240 | asm_fprintf (stream, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1241 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1242 | current_frame.foffset + fsize, |
1243 | current_frame.fpu_rev_mask); | |
79e68feb | 1244 | } |
6910dd70 | 1245 | else if (restore_from_sp) |
79e68feb | 1246 | { |
dcc21c4c PB |
1247 | if (TARGET_COLDFIRE) |
1248 | { | |
1249 | int offset; | |
1250 | ||
884b74f0 AS |
1251 | /* Stack already has registers in it. Find the offset from |
1252 | the bottom of stack to where the FP registers go. */ | |
dcc21c4c PB |
1253 | if (current_frame.reg_no <= 2) |
1254 | offset = 0; | |
1255 | else | |
1256 | offset = current_frame.reg_no * 4; | |
1257 | if (offset) | |
884b74f0 AS |
1258 | asm_fprintf (stream, |
1259 | "\tfmovem %Rsp@(%d), %I0x%x\n", | |
dcc21c4c PB |
1260 | offset, current_frame.fpu_rev_mask); |
1261 | else | |
884b74f0 | 1262 | asm_fprintf (stream, |
dcc21c4c PB |
1263 | "\tfmovem %Rsp@, %I0x%x\n", |
1264 | current_frame.fpu_rev_mask); | |
1265 | } | |
884b74f0 AS |
1266 | else |
1267 | asm_fprintf (stream, MOTOROLA ? | |
1268 | "\tfmovm (%Rsp)+,%I0x%x\n" : | |
1269 | "\tfmovem %Rsp@+,%I0x%x\n", | |
1270 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1271 | } |
1272 | else | |
1273 | { | |
dcc21c4c | 1274 | if (MOTOROLA && !TARGET_COLDFIRE) |
e6d98cb0 BI |
1275 | asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n", |
1276 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1277 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1278 | current_frame.fpu_rev_mask); |
1279 | else | |
1280 | asm_fprintf (stream, "\tfmovem %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1281 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1282 | current_frame.foffset + fsize, |
1283 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1284 | } |
1285 | } | |
79e68feb | 1286 | if (frame_pointer_needed) |
a0a7fbc9 | 1287 | fprintf (stream, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM)); |
860c4900 | 1288 | else if (fsize_with_regs) |
79e68feb | 1289 | { |
860c4900 | 1290 | if (fsize_with_regs <= 8) |
79e68feb | 1291 | { |
9425fb04 | 1292 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
1293 | asm_fprintf (stream, "\taddq" ASM_DOT "w %I%wd,%Rsp\n", |
1294 | fsize_with_regs); | |
1295 | else | |
1296 | asm_fprintf (stream, "\taddq" ASM_DOT "l %I%wd,%Rsp\n", | |
1297 | fsize_with_regs); | |
7bc88d49 | 1298 | } |
fe95f2f7 | 1299 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
7bc88d49 RK |
1300 | { |
1301 | /* On the CPU32 it is faster to use two addqw instructions to | |
7a1929e1 | 1302 | add a small integer (8 < N <= 16) to a register. */ |
a0a7fbc9 AS |
1303 | asm_fprintf (stream, |
1304 | "\taddq" ASM_DOT "w %I8,%Rsp\n" | |
1305 | "\taddq" ASM_DOT "w %I%wd,%Rsp\n", | |
860c4900 | 1306 | fsize_with_regs - 8); |
7bc88d49 | 1307 | } |
860c4900 | 1308 | else if (fsize_with_regs < 0x8000) |
7bc88d49 | 1309 | { |
fe95f2f7 | 1310 | if (TUNE_68040) |
e6d98cb0 BI |
1311 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", |
1312 | fsize_with_regs); | |
7bc88d49 | 1313 | else |
a0a7fbc9 AS |
1314 | asm_fprintf (stream, (MOTOROLA |
1315 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
1316 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 1317 | fsize_with_regs); |
79e68feb RS |
1318 | } |
1319 | else | |
e6d98cb0 | 1320 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); |
79e68feb | 1321 | } |
2cff4a6e | 1322 | if (current_function_calls_eh_return) |
a0a7fbc9 | 1323 | asm_fprintf (stream, "\tadd" ASM_DOT "l %Ra0,%Rsp\n"); |
3d74bc09 | 1324 | if (m68k_interrupt_function_p (current_function_decl)) |
48ed72a4 PB |
1325 | fprintf (stream, "\trte\n"); |
1326 | else if (current_function_pops_args) | |
1f85a612 | 1327 | asm_fprintf (stream, "\trtd %I%d\n", current_function_pops_args); |
79e68feb RS |
1328 | else |
1329 | fprintf (stream, "\trts\n"); | |
1330 | } | |
1331 | \f | |
8a4a2253 | 1332 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1333 | instruction. |
1334 | ||
1335 | Note it rejects floating point comparison operators. | |
1336 | (In the future we could use Fdbcc). | |
1337 | ||
1338 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1339 | ||
1340 | int | |
41b6a5e2 | 1341 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1342 | { |
64a184e9 RS |
1343 | switch (GET_CODE (x)) |
1344 | { | |
64a184e9 RS |
1345 | case EQ: case NE: case GTU: case LTU: |
1346 | case GEU: case LEU: | |
1347 | return 1; | |
1348 | ||
1349 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1350 | conservative */ | |
1351 | case GT: case LT: case GE: case LE: | |
1352 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1353 | default: | |
1354 | return 0; | |
1355 | } | |
1356 | } | |
1357 | ||
a0ab749a | 1358 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1359 | int |
8a4a2253 | 1360 | flags_in_68881 (void) |
6a0f85e3 TG |
1361 | { |
1362 | /* We could add support for these in the future */ | |
1363 | return cc_status.flags & CC_IN_68881; | |
1364 | } | |
1365 | ||
29ca003a RS |
1366 | /* Convert X to a legitimate function call memory reference and return the |
1367 | result. */ | |
a2ef3db7 | 1368 | |
29ca003a RS |
1369 | rtx |
1370 | m68k_legitimize_call_address (rtx x) | |
1371 | { | |
1372 | gcc_assert (MEM_P (x)); | |
1373 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1374 | return x; | |
1375 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1376 | } |
1377 | ||
64a184e9 RS |
1378 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1379 | floating point version of this sequence (Fdbcc). We also | |
1380 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1381 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1382 | kick those out before we get here. */ | |
64a184e9 | 1383 | |
1d8eaa6b | 1384 | void |
8a4a2253 | 1385 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1386 | { |
64a184e9 RS |
1387 | switch (GET_CODE (operands[3])) |
1388 | { | |
1389 | case EQ: | |
a0a7fbc9 AS |
1390 | output_asm_insn (MOTOROLA |
1391 | ? "dbeq %0,%l1\n\tjbeq %l2" | |
1392 | : "dbeq %0,%l1\n\tjeq %l2", | |
e6d98cb0 BI |
1393 | operands); |
1394 | break; | |
64a184e9 RS |
1395 | |
1396 | case NE: | |
a0a7fbc9 AS |
1397 | output_asm_insn (MOTOROLA |
1398 | ? "dbne %0,%l1\n\tjbne %l2" | |
1399 | : "dbne %0,%l1\n\tjne %l2", | |
e6d98cb0 BI |
1400 | operands); |
1401 | break; | |
64a184e9 RS |
1402 | |
1403 | case GT: | |
a0a7fbc9 AS |
1404 | output_asm_insn (MOTOROLA |
1405 | ? "dbgt %0,%l1\n\tjbgt %l2" | |
1406 | : "dbgt %0,%l1\n\tjgt %l2", | |
e6d98cb0 BI |
1407 | operands); |
1408 | break; | |
64a184e9 RS |
1409 | |
1410 | case GTU: | |
a0a7fbc9 AS |
1411 | output_asm_insn (MOTOROLA |
1412 | ? "dbhi %0,%l1\n\tjbhi %l2" | |
1413 | : "dbhi %0,%l1\n\tjhi %l2", | |
e6d98cb0 BI |
1414 | operands); |
1415 | break; | |
64a184e9 RS |
1416 | |
1417 | case LT: | |
a0a7fbc9 AS |
1418 | output_asm_insn (MOTOROLA |
1419 | ? "dblt %0,%l1\n\tjblt %l2" | |
1420 | : "dblt %0,%l1\n\tjlt %l2", | |
e6d98cb0 BI |
1421 | operands); |
1422 | break; | |
64a184e9 RS |
1423 | |
1424 | case LTU: | |
a0a7fbc9 AS |
1425 | output_asm_insn (MOTOROLA |
1426 | ? "dbcs %0,%l1\n\tjbcs %l2" | |
1427 | : "dbcs %0,%l1\n\tjcs %l2", | |
e6d98cb0 BI |
1428 | operands); |
1429 | break; | |
64a184e9 RS |
1430 | |
1431 | case GE: | |
a0a7fbc9 AS |
1432 | output_asm_insn (MOTOROLA |
1433 | ? "dbge %0,%l1\n\tjbge %l2" | |
1434 | : "dbge %0,%l1\n\tjge %l2", | |
e6d98cb0 BI |
1435 | operands); |
1436 | break; | |
64a184e9 RS |
1437 | |
1438 | case GEU: | |
a0a7fbc9 AS |
1439 | output_asm_insn (MOTOROLA |
1440 | ? "dbcc %0,%l1\n\tjbcc %l2" | |
1441 | : "dbcc %0,%l1\n\tjcc %l2", | |
e6d98cb0 BI |
1442 | operands); |
1443 | break; | |
64a184e9 RS |
1444 | |
1445 | case LE: | |
a0a7fbc9 AS |
1446 | output_asm_insn (MOTOROLA |
1447 | ? "dble %0,%l1\n\tjble %l2" | |
1448 | : "dble %0,%l1\n\tjle %l2", | |
e6d98cb0 BI |
1449 | operands); |
1450 | break; | |
64a184e9 RS |
1451 | |
1452 | case LEU: | |
a0a7fbc9 AS |
1453 | output_asm_insn (MOTOROLA |
1454 | ? "dbls %0,%l1\n\tjbls %l2" | |
1455 | : "dbls %0,%l1\n\tjls %l2", | |
e6d98cb0 BI |
1456 | operands); |
1457 | break; | |
64a184e9 RS |
1458 | |
1459 | default: | |
4761e388 | 1460 | gcc_unreachable (); |
64a184e9 RS |
1461 | } |
1462 | ||
1463 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1464 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1465 | switch (GET_MODE (operands[0])) |
1466 | { | |
1467 | case SImode: | |
a0a7fbc9 AS |
1468 | output_asm_insn (MOTOROLA |
1469 | ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" | |
1470 | : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1471 | operands); |
64a184e9 RS |
1472 | break; |
1473 | ||
1474 | case HImode: | |
1475 | break; | |
1476 | ||
1477 | default: | |
4761e388 | 1478 | gcc_unreachable (); |
64a184e9 RS |
1479 | } |
1480 | } | |
1481 | ||
5505f548 | 1482 | const char * |
4761e388 | 1483 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1484 | { |
1485 | rtx loperands[7]; | |
d9832fd2 | 1486 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1487 | |
f710504c | 1488 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1489 | CC_STATUS_INIT; |
1490 | ||
d9832fd2 RK |
1491 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1492 | below. Swap the operands and change the op if these requirements | |
1493 | are not fulfilled. */ | |
1494 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1495 | { | |
1496 | rtx tmp = operand1; | |
1497 | ||
1498 | operand1 = operand2; | |
1499 | operand2 = tmp; | |
1500 | op_code = swap_condition (op_code); | |
1501 | } | |
c59c3b1c RK |
1502 | loperands[0] = operand1; |
1503 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1504 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1505 | else |
b72f00af | 1506 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1507 | if (operand2 != const0_rtx) |
1508 | { | |
1509 | loperands[2] = operand2; | |
1510 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1511 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1512 | else |
b72f00af | 1513 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1514 | } |
428511bb | 1515 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1516 | if (operand2 != const0_rtx) |
4a8c52e0 | 1517 | { |
a0a7fbc9 AS |
1518 | output_asm_insn (MOTOROLA |
1519 | ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" | |
1520 | : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1521 | loperands); | |
4a8c52e0 | 1522 | } |
392582fa | 1523 | else |
4a8c52e0 | 1524 | { |
9425fb04 | 1525 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1526 | output_asm_insn ("tst%.l %0", loperands); |
1527 | else | |
a0a7fbc9 | 1528 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1529 | |
e6d98cb0 | 1530 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1531 | |
9425fb04 | 1532 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1533 | output_asm_insn ("tst%.l %1", loperands); |
1534 | else | |
3b4b85c9 | 1535 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1536 | } |
1537 | ||
c59c3b1c | 1538 | loperands[5] = dest; |
3b4b85c9 | 1539 | |
d9832fd2 | 1540 | switch (op_code) |
c59c3b1c RK |
1541 | { |
1542 | case EQ: | |
4977bab6 | 1543 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1544 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1545 | output_asm_insn ("seq %5", loperands); |
1546 | break; | |
1547 | ||
1548 | case NE: | |
4977bab6 | 1549 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1550 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1551 | output_asm_insn ("sne %5", loperands); |
1552 | break; | |
1553 | ||
1554 | case GT: | |
428511bb | 1555 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1556 | output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6", |
e6d98cb0 | 1557 | loperands); |
4977bab6 | 1558 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1559 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1560 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1561 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1562 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1563 | break; |
1564 | ||
1565 | case GTU: | |
4977bab6 | 1566 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1567 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1568 | output_asm_insn ("shi %5", loperands); |
1569 | break; | |
1570 | ||
1571 | case LT: | |
428511bb | 1572 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1573 | output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6", |
e6d98cb0 | 1574 | loperands); |
4977bab6 | 1575 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1576 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1577 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1578 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1579 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1580 | break; |
1581 | ||
1582 | case LTU: | |
4977bab6 | 1583 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1584 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1585 | output_asm_insn ("scs %5", loperands); |
1586 | break; | |
1587 | ||
1588 | case GE: | |
428511bb | 1589 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 AS |
1590 | output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6", |
1591 | loperands); | |
4977bab6 | 1592 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1593 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1594 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1595 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1596 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1597 | break; |
1598 | ||
1599 | case GEU: | |
4977bab6 | 1600 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1601 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1602 | output_asm_insn ("scc %5", loperands); |
1603 | break; | |
1604 | ||
1605 | case LE: | |
428511bb | 1606 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1607 | output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6", |
e6d98cb0 | 1608 | loperands); |
4977bab6 | 1609 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1610 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1611 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1612 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1613 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1614 | break; |
1615 | ||
1616 | case LEU: | |
4977bab6 | 1617 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1618 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1619 | output_asm_insn ("sls %5", loperands); |
1620 | break; | |
1621 | ||
1622 | default: | |
4761e388 | 1623 | gcc_unreachable (); |
c59c3b1c RK |
1624 | } |
1625 | return ""; | |
1626 | } | |
1627 | ||
5505f548 | 1628 | const char * |
8a4a2253 | 1629 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1630 | { |
1631 | operands[0] = countop; | |
1632 | operands[1] = dataop; | |
1633 | ||
1634 | if (GET_CODE (countop) == CONST_INT) | |
1635 | { | |
1636 | register int count = INTVAL (countop); | |
1637 | /* If COUNT is bigger than size of storage unit in use, | |
1638 | advance to the containing unit of same size. */ | |
1639 | if (count > signpos) | |
1640 | { | |
1641 | int offset = (count & ~signpos) / 8; | |
1642 | count = count & signpos; | |
b72f00af | 1643 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1644 | } |
1645 | if (count == signpos) | |
1646 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1647 | else | |
1648 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1649 | ||
1650 | /* These three statements used to use next_insns_test_no... | |
1651 | but it appears that this should do the same job. */ | |
1652 | if (count == 31 | |
1653 | && next_insn_tests_no_inequality (insn)) | |
1654 | return "tst%.l %1"; | |
1655 | if (count == 15 | |
1656 | && next_insn_tests_no_inequality (insn)) | |
1657 | return "tst%.w %1"; | |
1658 | if (count == 7 | |
1659 | && next_insn_tests_no_inequality (insn)) | |
1660 | return "tst%.b %1"; | |
1661 | ||
1662 | cc_status.flags = CC_NOT_NEGATIVE; | |
1663 | } | |
1664 | return "btst %0,%1"; | |
1665 | } | |
79e68feb RS |
1666 | \f |
1667 | /* Legitimize PIC addresses. If the address is already | |
1668 | position-independent, we return ORIG. Newly generated | |
1669 | position-independent addresses go to REG. If we need more | |
1670 | than one register, we lose. | |
1671 | ||
1672 | An address is legitimized by making an indirect reference | |
1673 | through the Global Offset Table with the name of the symbol | |
1674 | used as an offset. | |
1675 | ||
1676 | The assembler and linker are responsible for placing the | |
1677 | address of the symbol in the GOT. The function prologue | |
1678 | is responsible for initializing a5 to the starting address | |
1679 | of the GOT. | |
1680 | ||
1681 | The assembler is also responsible for translating a symbol name | |
1682 | into a constant displacement from the start of the GOT. | |
1683 | ||
1684 | A quick example may make things a little clearer: | |
1685 | ||
1686 | When not generating PIC code to store the value 12345 into _foo | |
1687 | we would generate the following code: | |
1688 | ||
1689 | movel #12345, _foo | |
1690 | ||
1691 | When generating PIC two transformations are made. First, the compiler | |
1692 | loads the address of foo into a register. So the first transformation makes: | |
1693 | ||
1694 | lea _foo, a0 | |
1695 | movel #12345, a0@ | |
1696 | ||
1697 | The code in movsi will intercept the lea instruction and call this | |
1698 | routine which will transform the instructions into: | |
1699 | ||
1700 | movel a5@(_foo:w), a0 | |
1701 | movel #12345, a0@ | |
1702 | ||
1703 | ||
1704 | That (in a nutshell) is how *all* symbol and label references are | |
1705 | handled. */ | |
1706 | ||
1707 | rtx | |
8a4a2253 BI |
1708 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1709 | rtx reg) | |
79e68feb RS |
1710 | { |
1711 | rtx pic_ref = orig; | |
1712 | ||
1713 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1714 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1715 | { | |
4761e388 | 1716 | gcc_assert (reg); |
79e68feb | 1717 | |
1d8eaa6b AS |
1718 | pic_ref = gen_rtx_MEM (Pmode, |
1719 | gen_rtx_PLUS (Pmode, | |
1720 | pic_offset_table_rtx, orig)); | |
79e68feb | 1721 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 1722 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
1723 | emit_move_insn (reg, pic_ref); |
1724 | return reg; | |
1725 | } | |
1726 | else if (GET_CODE (orig) == CONST) | |
1727 | { | |
1d8eaa6b | 1728 | rtx base; |
79e68feb | 1729 | |
b2e08ed4 | 1730 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
1731 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
1732 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1733 | return orig; | |
1734 | ||
4761e388 | 1735 | gcc_assert (reg); |
79e68feb RS |
1736 | |
1737 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
1738 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
1739 | ||
1740 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
1741 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
1742 | base == reg ? 0 : reg); | |
79e68feb RS |
1743 | |
1744 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 1745 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 1746 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
1747 | /* Likewise, should we set special REG_NOTEs here? */ |
1748 | } | |
1749 | return pic_ref; | |
1750 | } | |
1751 | ||
1752 | \f | |
28bad6d1 | 1753 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 1754 | |
8a4a2253 | 1755 | static CONST_METHOD const_method (rtx); |
5505f548 | 1756 | |
a0a7fbc9 | 1757 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 1758 | |
5505f548 | 1759 | static CONST_METHOD |
8a4a2253 | 1760 | const_method (rtx constant) |
0ce6f9fb RK |
1761 | { |
1762 | int i; | |
1763 | unsigned u; | |
1764 | ||
1765 | i = INTVAL (constant); | |
6910dd70 | 1766 | if (USE_MOVQ (i)) |
0ce6f9fb | 1767 | return MOVQ; |
24092242 | 1768 | |
c16eadc7 | 1769 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 1770 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 1771 | if (!TARGET_COLDFIRE) |
24092242 RK |
1772 | { |
1773 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 1774 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
1775 | if (USE_MOVQ (i ^ 0xff)) |
1776 | return NOTB; | |
1777 | /* Likewise, try with not.w */ | |
1778 | if (USE_MOVQ (i ^ 0xffff)) | |
1779 | return NOTW; | |
1780 | /* This is the only value where neg.w is useful */ | |
1781 | if (i == -65408) | |
1782 | return NEGW; | |
24092242 | 1783 | } |
28bad6d1 | 1784 | |
5e04daf3 PB |
1785 | /* Try also with swap. */ |
1786 | u = i; | |
1787 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
1788 | return SWAP; | |
1789 | ||
986e74d5 | 1790 | if (TARGET_ISAB) |
28bad6d1 | 1791 | { |
72edf146 | 1792 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
1793 | if (i >= 0 && i <= 65535) |
1794 | return MVZ; | |
1795 | if (i >= -32768 && i <= 32767) | |
1796 | return MVS; | |
1797 | } | |
1798 | ||
0ce6f9fb RK |
1799 | /* Otherwise, use move.l */ |
1800 | return MOVL; | |
1801 | } | |
1802 | ||
3c50106f | 1803 | static int |
8a4a2253 | 1804 | const_int_cost (rtx constant) |
0ce6f9fb RK |
1805 | { |
1806 | switch (const_method (constant)) | |
1807 | { | |
a0a7fbc9 AS |
1808 | case MOVQ: |
1809 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
1810 | return 0; | |
1811 | case MVZ: | |
1812 | case MVS: | |
1813 | case NOTB: | |
1814 | case NOTW: | |
1815 | case NEGW: | |
1816 | case SWAP: | |
1817 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
1818 | return 1; | |
1819 | case MOVL: | |
1820 | return 2; | |
1821 | default: | |
1822 | gcc_unreachable (); | |
0ce6f9fb RK |
1823 | } |
1824 | } | |
1825 | ||
3c50106f | 1826 | static bool |
8a4a2253 | 1827 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1828 | { |
1829 | switch (code) | |
1830 | { | |
1831 | case CONST_INT: | |
1832 | /* Constant zero is super cheap due to clr instruction. */ | |
1833 | if (x == const0_rtx) | |
1834 | *total = 0; | |
1835 | else | |
1836 | *total = const_int_cost (x); | |
1837 | return true; | |
1838 | ||
1839 | case CONST: | |
1840 | case LABEL_REF: | |
1841 | case SYMBOL_REF: | |
1842 | *total = 3; | |
1843 | return true; | |
1844 | ||
1845 | case CONST_DOUBLE: | |
1846 | /* Make 0.0 cheaper than other floating constants to | |
1847 | encourage creating tstsf and tstdf insns. */ | |
1848 | if (outer_code == COMPARE | |
1849 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
1850 | *total = 4; | |
1851 | else | |
1852 | *total = 5; | |
1853 | return true; | |
1854 | ||
1855 | /* These are vaguely right for a 68020. */ | |
1856 | /* The costs for long multiply have been adjusted to work properly | |
1857 | in synth_mult on the 68020, relative to an average of the time | |
1858 | for add and the time for shift, taking away a little more because | |
1859 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
1860 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
1861 | terms. */ | |
fe95f2f7 JB |
1862 | #define MULL_COST \ |
1863 | (TUNE_68060 ? 2 \ | |
1864 | : TUNE_68040 ? 5 \ | |
1865 | : TUNE_CFV2 ? 10 \ | |
1866 | : TARGET_COLDFIRE ? 3 : 13) | |
1867 | ||
1868 | #define MULW_COST \ | |
1869 | (TUNE_68060 ? 2 \ | |
1870 | : TUNE_68040 ? 3 \ | |
1871 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
1872 | : TARGET_COLDFIRE ? 2 : 8) | |
1873 | ||
1874 | #define DIVW_COST \ | |
1875 | (TARGET_CF_HWDIV ? 11 \ | |
1876 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
1877 | |
1878 | case PLUS: | |
1879 | /* An lea costs about three times as much as a simple add. */ | |
1880 | if (GET_MODE (x) == SImode | |
1881 | && GET_CODE (XEXP (x, 1)) == REG | |
1882 | && GET_CODE (XEXP (x, 0)) == MULT | |
1883 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1884 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1885 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
1886 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
1887 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
1888 | { |
1889 | /* lea an@(dx:l:i),am */ | |
1890 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
1891 | return true; | |
1892 | } | |
3c50106f RH |
1893 | return false; |
1894 | ||
1895 | case ASHIFT: | |
1896 | case ASHIFTRT: | |
1897 | case LSHIFTRT: | |
fe95f2f7 | 1898 | if (TUNE_68060) |
3c50106f RH |
1899 | { |
1900 | *total = COSTS_N_INSNS(1); | |
1901 | return true; | |
1902 | } | |
fe95f2f7 | 1903 | if (TUNE_68000_10) |
3c50106f RH |
1904 | { |
1905 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1906 | { | |
1907 | if (INTVAL (XEXP (x, 1)) < 16) | |
1908 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
1909 | else | |
1910 | /* We're using clrw + swap for these cases. */ | |
1911 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
1912 | } | |
1913 | else | |
a0a7fbc9 | 1914 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
1915 | return true; |
1916 | } | |
1917 | /* A shift by a big integer takes an extra instruction. */ | |
1918 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1919 | && (INTVAL (XEXP (x, 1)) == 16)) | |
1920 | { | |
1921 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
1922 | return true; | |
1923 | } | |
1924 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1925 | && !(INTVAL (XEXP (x, 1)) > 0 | |
1926 | && INTVAL (XEXP (x, 1)) <= 8)) | |
1927 | { | |
eb849993 | 1928 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
1929 | return true; |
1930 | } | |
1931 | return false; | |
1932 | ||
1933 | case MULT: | |
1934 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
1935 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
1936 | && GET_MODE (x) == SImode) | |
1937 | *total = COSTS_N_INSNS (MULW_COST); | |
1938 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1939 | *total = COSTS_N_INSNS (MULW_COST); | |
1940 | else | |
1941 | *total = COSTS_N_INSNS (MULL_COST); | |
1942 | return true; | |
1943 | ||
1944 | case DIV: | |
1945 | case UDIV: | |
1946 | case MOD: | |
1947 | case UMOD: | |
1948 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1949 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
1950 | else if (TARGET_CF_HWDIV) |
1951 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
1952 | else |
1953 | *total = COSTS_N_INSNS (43); /* div.l */ | |
1954 | return true; | |
1955 | ||
1956 | default: | |
1957 | return false; | |
1958 | } | |
1959 | } | |
1960 | ||
5505f548 | 1961 | const char * |
8a4a2253 | 1962 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb RK |
1963 | { |
1964 | int i; | |
1965 | ||
1966 | i = INTVAL (operands[1]); | |
1967 | switch (const_method (operands[1])) | |
1968 | { | |
28bad6d1 | 1969 | case MVZ: |
28bad6d1 | 1970 | return "mvzw %1,%0"; |
1cbae84f PB |
1971 | case MVS: |
1972 | return "mvsw %1,%0"; | |
a0a7fbc9 | 1973 | case MOVQ: |
0ce6f9fb | 1974 | return "moveq %1,%0"; |
a0a7fbc9 | 1975 | case NOTB: |
66e07510 | 1976 | CC_STATUS_INIT; |
1d8eaa6b | 1977 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 1978 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 1979 | case NOTW: |
66e07510 | 1980 | CC_STATUS_INIT; |
1d8eaa6b | 1981 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 1982 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 1983 | case NEGW: |
66e07510 | 1984 | CC_STATUS_INIT; |
3b4b85c9 | 1985 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 1986 | case SWAP: |
0ce6f9fb RK |
1987 | { |
1988 | unsigned u = i; | |
1989 | ||
1d8eaa6b | 1990 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 1991 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 1992 | } |
a0a7fbc9 | 1993 | case MOVL: |
0ce6f9fb | 1994 | return "move%.l %1,%0"; |
a0a7fbc9 | 1995 | default: |
4761e388 | 1996 | gcc_unreachable (); |
0ce6f9fb RK |
1997 | } |
1998 | } | |
1999 | ||
5e04daf3 PB |
2000 | /* Return 1 if 'constant' can be represented by |
2001 | mov3q on a ColdFire V4 core. */ | |
2002 | int | |
2003 | valid_mov3q_const (rtx constant) | |
2004 | { | |
2005 | int i; | |
2006 | ||
986e74d5 | 2007 | if (TARGET_ISAB && GET_CODE (constant) == CONST_INT) |
5e04daf3 PB |
2008 | { |
2009 | i = INTVAL (constant); | |
a0a7fbc9 | 2010 | if (i == -1 || (i >= 1 && i <= 7)) |
5e04daf3 PB |
2011 | return 1; |
2012 | } | |
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | ||
5505f548 | 2017 | const char * |
8a4a2253 | 2018 | output_move_simode_const (rtx *operands) |
02ed0c07 RK |
2019 | { |
2020 | if (operands[1] == const0_rtx | |
2021 | && (DATA_REG_P (operands[0]) | |
2022 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2023 | /* clr insns on 68000 read before writing. */ |
2024 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
02ed0c07 RK |
2025 | || !(GET_CODE (operands[0]) == MEM |
2026 | && MEM_VOLATILE_P (operands[0])))) | |
2027 | return "clr%.l %0"; | |
5e04daf3 PB |
2028 | else if ((GET_MODE (operands[0]) == SImode) |
2029 | && valid_mov3q_const (operands[1])) | |
a0a7fbc9 | 2030 | return "mov3q%.l %1,%0"; |
38198304 AS |
2031 | else if (operands[1] == const0_rtx |
2032 | && ADDRESS_REG_P (operands[0])) | |
2033 | return "sub%.l %0,%0"; | |
02ed0c07 RK |
2034 | else if (DATA_REG_P (operands[0])) |
2035 | return output_move_const_into_data_reg (operands); | |
2036 | else if (ADDRESS_REG_P (operands[0]) | |
2037 | && INTVAL (operands[1]) < 0x8000 | |
2038 | && INTVAL (operands[1]) >= -0x8000) | |
5e04daf3 PB |
2039 | { |
2040 | if (valid_mov3q_const (operands[1])) | |
2041 | return "mov3q%.l %1,%0"; | |
2042 | return "move%.w %1,%0"; | |
2043 | } | |
02ed0c07 | 2044 | else if (GET_CODE (operands[0]) == MEM |
a0a7fbc9 AS |
2045 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC |
2046 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
02ed0c07 RK |
2047 | && INTVAL (operands[1]) < 0x8000 |
2048 | && INTVAL (operands[1]) >= -0x8000) | |
5e04daf3 PB |
2049 | { |
2050 | if (valid_mov3q_const (operands[1])) | |
2051 | return "mov3q%.l %1,%-"; | |
2052 | return "pea %a1"; | |
2053 | } | |
02ed0c07 RK |
2054 | return "move%.l %1,%0"; |
2055 | } | |
2056 | ||
5505f548 | 2057 | const char * |
8a4a2253 | 2058 | output_move_simode (rtx *operands) |
f4e80198 RK |
2059 | { |
2060 | if (GET_CODE (operands[1]) == CONST_INT) | |
2061 | return output_move_simode_const (operands); | |
2062 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2063 | || GET_CODE (operands[1]) == CONST) | |
2064 | && push_operand (operands[0], SImode)) | |
2065 | return "pea %a1"; | |
2066 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2067 | || GET_CODE (operands[1]) == CONST) | |
2068 | && ADDRESS_REG_P (operands[0])) | |
2069 | return "lea %a1,%0"; | |
2070 | return "move%.l %1,%0"; | |
2071 | } | |
2072 | ||
5505f548 | 2073 | const char * |
8a4a2253 | 2074 | output_move_himode (rtx *operands) |
f4e80198 RK |
2075 | { |
2076 | if (GET_CODE (operands[1]) == CONST_INT) | |
2077 | { | |
2078 | if (operands[1] == const0_rtx | |
2079 | && (DATA_REG_P (operands[0]) | |
2080 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2081 | /* clr insns on 68000 read before writing. */ |
2082 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2083 | || !(GET_CODE (operands[0]) == MEM |
2084 | && MEM_VOLATILE_P (operands[0])))) | |
2085 | return "clr%.w %0"; | |
38198304 AS |
2086 | else if (operands[1] == const0_rtx |
2087 | && ADDRESS_REG_P (operands[0])) | |
2088 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2089 | else if (DATA_REG_P (operands[0]) |
2090 | && INTVAL (operands[1]) < 128 | |
2091 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2092 | return "moveq %1,%0"; |
f4e80198 RK |
2093 | else if (INTVAL (operands[1]) < 0x8000 |
2094 | && INTVAL (operands[1]) >= -0x8000) | |
2095 | return "move%.w %1,%0"; | |
2096 | } | |
2097 | else if (CONSTANT_P (operands[1])) | |
2098 | return "move%.l %1,%0"; | |
f4e80198 RK |
2099 | /* Recognize the insn before a tablejump, one that refers |
2100 | to a table of offsets. Such an insn will need to refer | |
2101 | to a label on the insn. So output one. Use the label-number | |
2102 | of the table of offsets to generate this label. This code, | |
2103 | and similar code below, assumes that there will be at most one | |
2104 | reference to each table. */ | |
2105 | if (GET_CODE (operands[1]) == MEM | |
2106 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2107 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
2108 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
2109 | { | |
2110 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
2111 | if (MOTOROLA) |
2112 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
2113 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
2114 | else | |
2115 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
a0a7fbc9 | 2116 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); |
f4e80198 | 2117 | } |
f4e80198 RK |
2118 | return "move%.w %1,%0"; |
2119 | } | |
2120 | ||
5505f548 | 2121 | const char * |
8a4a2253 | 2122 | output_move_qimode (rtx *operands) |
f4e80198 | 2123 | { |
102701ff | 2124 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2125 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2126 | |
a0a7fbc9 | 2127 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2128 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2129 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2130 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2131 | && ! ADDRESS_REG_P (operands[1]) | |
2132 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2133 | |
3197c489 | 2134 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2135 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2136 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2137 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2138 | { | |
2139 | if (operands[1] == const0_rtx) | |
2140 | return "clr%.b %0"; | |
9425fb04 | 2141 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2142 | && GET_CODE (operands[1]) == CONST_INT |
2143 | && (INTVAL (operands[1]) & 255) == 255) | |
2144 | { | |
2145 | CC_STATUS_INIT; | |
2146 | return "st %0"; | |
2147 | } | |
2148 | } | |
2149 | if (GET_CODE (operands[1]) == CONST_INT | |
2150 | && DATA_REG_P (operands[0]) | |
2151 | && INTVAL (operands[1]) < 128 | |
2152 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2153 | return "moveq %1,%0"; |
38198304 AS |
2154 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2155 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2156 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2157 | return "move%.l %1,%0"; | |
c16eadc7 | 2158 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2159 | from address registers. */ |
2160 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2161 | return "move%.w %1,%0"; |
2162 | return "move%.b %1,%0"; | |
2163 | } | |
2164 | ||
5505f548 | 2165 | const char * |
8a4a2253 | 2166 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2167 | { |
2168 | if (operands[1] == const0_rtx | |
3197c489 RS |
2169 | /* clr insns on 68000 read before writing. */ |
2170 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2171 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2172 | return "clr%.w %0"; | |
2173 | return "move%.w %1,%0"; | |
2174 | } | |
2175 | ||
5505f548 | 2176 | const char * |
8a4a2253 | 2177 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2178 | { |
2179 | if (operands[1] == const0_rtx | |
3197c489 RS |
2180 | /* clr insns on 68000 read before writing. */ |
2181 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2182 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2183 | return "clr%.b %0"; | |
2184 | return "move%.b %1,%0"; | |
2185 | } | |
2186 | ||
79e68feb RS |
2187 | /* Return the best assembler insn template |
2188 | for moving operands[1] into operands[0] as a fullword. */ | |
2189 | ||
5505f548 | 2190 | static const char * |
8a4a2253 | 2191 | singlemove_string (rtx *operands) |
79e68feb | 2192 | { |
02ed0c07 RK |
2193 | if (GET_CODE (operands[1]) == CONST_INT) |
2194 | return output_move_simode_const (operands); | |
2195 | return "move%.l %1,%0"; | |
79e68feb RS |
2196 | } |
2197 | ||
2505bc97 | 2198 | |
79e68feb RS |
2199 | /* Output assembler code to perform a doubleword move insn |
2200 | with operands OPERANDS. */ | |
2201 | ||
5505f548 | 2202 | const char * |
8a4a2253 | 2203 | output_move_double (rtx *operands) |
79e68feb | 2204 | { |
2505bc97 RS |
2205 | enum |
2206 | { | |
2207 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2208 | } optype0, optype1; | |
79e68feb | 2209 | rtx latehalf[2]; |
2505bc97 | 2210 | rtx middlehalf[2]; |
7f98eeb6 | 2211 | rtx xops[2]; |
79e68feb | 2212 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2213 | int dest_overlapped_low = 0; |
184916bc | 2214 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2215 | |
2216 | middlehalf[0] = 0; | |
2217 | middlehalf[1] = 0; | |
79e68feb RS |
2218 | |
2219 | /* First classify both operands. */ | |
2220 | ||
2221 | if (REG_P (operands[0])) | |
2222 | optype0 = REGOP; | |
2223 | else if (offsettable_memref_p (operands[0])) | |
2224 | optype0 = OFFSOP; | |
2225 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2226 | optype0 = POPOP; | |
2227 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2228 | optype0 = PUSHOP; | |
2229 | else if (GET_CODE (operands[0]) == MEM) | |
2230 | optype0 = MEMOP; | |
2231 | else | |
2232 | optype0 = RNDOP; | |
2233 | ||
2234 | if (REG_P (operands[1])) | |
2235 | optype1 = REGOP; | |
2236 | else if (CONSTANT_P (operands[1])) | |
2237 | optype1 = CNSTOP; | |
2238 | else if (offsettable_memref_p (operands[1])) | |
2239 | optype1 = OFFSOP; | |
2240 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2241 | optype1 = POPOP; | |
2242 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2243 | optype1 = PUSHOP; | |
2244 | else if (GET_CODE (operands[1]) == MEM) | |
2245 | optype1 = MEMOP; | |
2246 | else | |
2247 | optype1 = RNDOP; | |
2248 | ||
4761e388 NS |
2249 | /* Check for the cases that the operand constraints are not supposed |
2250 | to allow to happen. Generating code for these cases is | |
2251 | painful. */ | |
2252 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2253 | |
2254 | /* If one operand is decrementing and one is incrementing | |
2255 | decrement the former register explicitly | |
2256 | and change that operand into ordinary indexing. */ | |
2257 | ||
2258 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2259 | { | |
2260 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 2261 | if (size == 12) |
3b4b85c9 | 2262 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 2263 | else |
3b4b85c9 | 2264 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 2265 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2266 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2267 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2268 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2269 | else |
1d8eaa6b | 2270 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2271 | optype0 = OFFSOP; |
2272 | } | |
2273 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2274 | { | |
2275 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 2276 | if (size == 12) |
3b4b85c9 | 2277 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 2278 | else |
3b4b85c9 | 2279 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 2280 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2281 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2282 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2283 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2284 | else |
1d8eaa6b | 2285 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2286 | optype1 = OFFSOP; |
2287 | } | |
2288 | ||
2289 | /* If an operand is an unoffsettable memory ref, find a register | |
2290 | we can increment temporarily to make it refer to the second word. */ | |
2291 | ||
2292 | if (optype0 == MEMOP) | |
2293 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2294 | ||
2295 | if (optype1 == MEMOP) | |
2296 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2297 | ||
2298 | /* Ok, we can do one word at a time. | |
2299 | Normally we do the low-numbered word first, | |
2300 | but if either operand is autodecrementing then we | |
2301 | do the high-numbered word first. | |
2302 | ||
2303 | In either case, set up in LATEHALF the operands to use | |
2304 | for the high-numbered word and in some cases alter the | |
2305 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2306 | ||
2505bc97 RS |
2307 | if (size == 12) |
2308 | { | |
2309 | if (optype0 == REGOP) | |
2310 | { | |
1d8eaa6b AS |
2311 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2312 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2313 | } |
2314 | else if (optype0 == OFFSOP) | |
2315 | { | |
b72f00af RK |
2316 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2317 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2318 | } |
2319 | else | |
2320 | { | |
2321 | middlehalf[0] = operands[0]; | |
2322 | latehalf[0] = operands[0]; | |
2323 | } | |
2324 | ||
2325 | if (optype1 == REGOP) | |
2326 | { | |
1d8eaa6b AS |
2327 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2328 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2329 | } |
2330 | else if (optype1 == OFFSOP) | |
2331 | { | |
b72f00af RK |
2332 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2333 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2334 | } |
2335 | else if (optype1 == CNSTOP) | |
2336 | { | |
2337 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2338 | { | |
2339 | REAL_VALUE_TYPE r; | |
2340 | long l[3]; | |
2341 | ||
2342 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2343 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2344 | operands[1] = GEN_INT (l[0]); | |
2345 | middlehalf[1] = GEN_INT (l[1]); | |
2346 | latehalf[1] = GEN_INT (l[2]); | |
2347 | } | |
4761e388 | 2348 | else |
2505bc97 | 2349 | { |
4761e388 NS |
2350 | /* No non-CONST_DOUBLE constant should ever appear |
2351 | here. */ | |
2352 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2353 | } |
2354 | } | |
2355 | else | |
2356 | { | |
2357 | middlehalf[1] = operands[1]; | |
2358 | latehalf[1] = operands[1]; | |
2359 | } | |
2360 | } | |
79e68feb | 2361 | else |
2505bc97 RS |
2362 | /* size is not 12: */ |
2363 | { | |
2364 | if (optype0 == REGOP) | |
1d8eaa6b | 2365 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2366 | else if (optype0 == OFFSOP) |
b72f00af | 2367 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2368 | else |
2369 | latehalf[0] = operands[0]; | |
2370 | ||
2371 | if (optype1 == REGOP) | |
1d8eaa6b | 2372 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2373 | else if (optype1 == OFFSOP) |
b72f00af | 2374 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2375 | else if (optype1 == CNSTOP) |
2376 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2377 | else | |
2378 | latehalf[1] = operands[1]; | |
2379 | } | |
79e68feb RS |
2380 | |
2381 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2382 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2383 | for the low word as well, to compensate for the first decrement of sp. */ | |
2384 | if (optype0 == PUSHOP | |
2385 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2386 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2387 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2388 | |
7f98eeb6 RS |
2389 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2390 | if the upper part of reg N does not appear in the MEM, arrange to | |
2391 | emit the move late-half first. Otherwise, compute the MEM address | |
2392 | into the upper part of N and use that as a pointer to the memory | |
2393 | operand. */ | |
2394 | if (optype0 == REGOP | |
2395 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2396 | { | |
1d8eaa6b | 2397 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2398 | |
2399 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2400 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2401 | { |
2402 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2403 | compute the address into latehalf of dest. |
2404 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2405 | compadr: |
7f98eeb6 RS |
2406 | xops[0] = latehalf[0]; |
2407 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2408 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2409 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2410 | { |
1d8eaa6b | 2411 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2412 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2413 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2414 | } |
2415 | else | |
2416 | { | |
1d8eaa6b | 2417 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2418 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2419 | } |
2420 | } | |
2421 | else if (size == 12 | |
d7e8d581 RS |
2422 | && reg_overlap_mentioned_p (middlehalf[0], |
2423 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2424 | { |
3a58400f RS |
2425 | /* Check for two regs used by both source and dest. |
2426 | Note that this can't happen if the dest is all data regs. | |
2427 | It can happen if the dest is d6, d7, a0. | |
2428 | But in that case, latehalf is an addr reg, so | |
2429 | the code at compadr does ok. */ | |
2430 | ||
2431 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2432 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2433 | goto compadr; | |
7f98eeb6 RS |
2434 | |
2435 | /* JRV says this can't happen: */ | |
4761e388 | 2436 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2437 | |
7a1929e1 | 2438 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2439 | output_asm_insn (singlemove_string (operands), operands); |
2440 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2441 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2442 | return ""; | |
2443 | } | |
2fb8a81d | 2444 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2445 | /* If the low half of dest is mentioned in the source memory |
2446 | address, the arrange to emit the move late half first. */ | |
2447 | dest_overlapped_low = 1; | |
2448 | } | |
2449 | ||
79e68feb RS |
2450 | /* If one or both operands autodecrementing, |
2451 | do the two words, high-numbered first. */ | |
2452 | ||
2453 | /* Likewise, the first move would clobber the source of the second one, | |
2454 | do them in the other order. This happens only for registers; | |
2455 | such overlap can't happen in memory unless the user explicitly | |
2456 | sets it up, and that is an undefined circumstance. */ | |
2457 | ||
2458 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2459 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2460 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2461 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2462 | || dest_overlapped_low) | |
79e68feb RS |
2463 | { |
2464 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2465 | if (addreg0) | |
2505bc97 RS |
2466 | { |
2467 | if (size == 12) | |
3b4b85c9 | 2468 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2469 | else |
3b4b85c9 | 2470 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2471 | } |
79e68feb | 2472 | if (addreg1) |
2505bc97 RS |
2473 | { |
2474 | if (size == 12) | |
3b4b85c9 | 2475 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2476 | else |
3b4b85c9 | 2477 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2478 | } |
79e68feb RS |
2479 | |
2480 | /* Do that word. */ | |
2481 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2482 | ||
2483 | /* Undo the adds we just did. */ | |
2484 | if (addreg0) | |
3b4b85c9 | 2485 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2486 | if (addreg1) |
3b4b85c9 | 2487 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2488 | |
2505bc97 RS |
2489 | if (size == 12) |
2490 | { | |
2491 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2492 | if (addreg0) | |
3b4b85c9 | 2493 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2494 | if (addreg1) |
3b4b85c9 | 2495 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2496 | } |
2497 | ||
79e68feb RS |
2498 | /* Do low-numbered word. */ |
2499 | return singlemove_string (operands); | |
2500 | } | |
2501 | ||
2502 | /* Normal case: do the two words, low-numbered first. */ | |
2503 | ||
2504 | output_asm_insn (singlemove_string (operands), operands); | |
2505 | ||
2505bc97 RS |
2506 | /* Do the middle one of the three words for long double */ |
2507 | if (size == 12) | |
2508 | { | |
2509 | if (addreg0) | |
3b4b85c9 | 2510 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2511 | if (addreg1) |
3b4b85c9 | 2512 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2513 | |
2514 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2515 | } | |
2516 | ||
79e68feb RS |
2517 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2518 | if (addreg0) | |
3b4b85c9 | 2519 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2520 | if (addreg1) |
3b4b85c9 | 2521 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2522 | |
2523 | /* Do that word. */ | |
2524 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2525 | ||
2526 | /* Undo the adds we just did. */ | |
2527 | if (addreg0) | |
2505bc97 RS |
2528 | { |
2529 | if (size == 12) | |
3b4b85c9 | 2530 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2531 | else |
3b4b85c9 | 2532 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2533 | } |
79e68feb | 2534 | if (addreg1) |
2505bc97 RS |
2535 | { |
2536 | if (size == 12) | |
3b4b85c9 | 2537 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2538 | else |
3b4b85c9 | 2539 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2540 | } |
79e68feb RS |
2541 | |
2542 | return ""; | |
2543 | } | |
2544 | ||
dcc21c4c PB |
2545 | |
2546 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2547 | new rtx with the correct mode. */ | |
2548 | ||
2549 | static rtx | |
2550 | force_mode (enum machine_mode mode, rtx orig) | |
2551 | { | |
2552 | if (mode == GET_MODE (orig)) | |
2553 | return orig; | |
2554 | ||
2555 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2556 | abort (); | |
2557 | ||
2558 | return gen_rtx_REG (mode, REGNO (orig)); | |
2559 | } | |
2560 | ||
2561 | static int | |
2562 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2563 | { | |
2564 | return reg_renumber && FP_REG_P (op); | |
2565 | } | |
2566 | ||
2567 | /* Emit insns to move operands[1] into operands[0]. | |
2568 | ||
2569 | Return 1 if we have written out everything that needs to be done to | |
2570 | do the move. Otherwise, return 0 and the caller will emit the move | |
2571 | normally. | |
2572 | ||
2573 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2574 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2575 | of SCRATCH_REG in the proper mode. */ |
2576 | ||
2577 | int | |
2578 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2579 | { | |
2580 | register rtx operand0 = operands[0]; | |
2581 | register rtx operand1 = operands[1]; | |
2582 | register rtx tem; | |
2583 | ||
2584 | if (scratch_reg | |
2585 | && reload_in_progress && GET_CODE (operand0) == REG | |
2586 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2587 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2588 | else if (scratch_reg | |
2589 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2590 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2591 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2592 | { | |
2593 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2594 | the code which tracks sets/uses for delete_output_reload. */ | |
2595 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2596 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2597 | SUBREG_BYTE (operand0)); | |
2598 | operand0 = alter_subreg (&temp); | |
2599 | } | |
2600 | ||
2601 | if (scratch_reg | |
2602 | && reload_in_progress && GET_CODE (operand1) == REG | |
2603 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2604 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2605 | else if (scratch_reg | |
2606 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2607 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2608 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2609 | { | |
2610 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2611 | the code which tracks sets/uses for delete_output_reload. */ | |
2612 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2613 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2614 | SUBREG_BYTE (operand1)); | |
2615 | operand1 = alter_subreg (&temp); | |
2616 | } | |
2617 | ||
2618 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2619 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2620 | != XEXP (operand0, 0))) | |
2621 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2622 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2623 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2624 | != XEXP (operand1, 0))) | |
2625 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2626 | ||
2627 | /* Handle secondary reloads for loads/stores of FP registers where | |
2628 | the address is symbolic by using the scratch register */ | |
2629 | if (fp_reg_operand (operand0, mode) | |
2630 | && ((GET_CODE (operand1) == MEM | |
2631 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
2632 | || ((GET_CODE (operand1) == SUBREG | |
2633 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
2634 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
2635 | && scratch_reg) | |
2636 | { | |
2637 | if (GET_CODE (operand1) == SUBREG) | |
2638 | operand1 = XEXP (operand1, 0); | |
2639 | ||
2640 | /* SCRATCH_REG will hold an address. We want | |
2641 | it in SImode regardless of what mode it was originally given | |
2642 | to us. */ | |
2643 | scratch_reg = force_mode (SImode, scratch_reg); | |
2644 | ||
2645 | /* D might not fit in 14 bits either; for such cases load D into | |
2646 | scratch reg. */ | |
2647 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
2648 | { | |
2649 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
2650 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
2651 | Pmode, | |
2652 | XEXP (XEXP (operand1, 0), 0), | |
2653 | scratch_reg)); | |
2654 | } | |
2655 | else | |
2656 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
2657 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
2658 | gen_rtx_MEM (mode, scratch_reg))); | |
2659 | return 1; | |
2660 | } | |
2661 | else if (fp_reg_operand (operand1, mode) | |
2662 | && ((GET_CODE (operand0) == MEM | |
2663 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
2664 | || ((GET_CODE (operand0) == SUBREG) | |
2665 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
2666 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
2667 | && scratch_reg) | |
2668 | { | |
2669 | if (GET_CODE (operand0) == SUBREG) | |
2670 | operand0 = XEXP (operand0, 0); | |
2671 | ||
2672 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2673 | it in SIMODE regardless of what mode it was originally given | |
2674 | to us. */ | |
2675 | scratch_reg = force_mode (SImode, scratch_reg); | |
2676 | ||
2677 | /* D might not fit in 14 bits either; for such cases load D into | |
2678 | scratch reg. */ | |
2679 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
2680 | { | |
2681 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
2682 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
2683 | 0)), | |
2684 | Pmode, | |
2685 | XEXP (XEXP (operand0, 0), | |
2686 | 0), | |
2687 | scratch_reg)); | |
2688 | } | |
2689 | else | |
2690 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
2691 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
2692 | operand1)); | |
2693 | return 1; | |
2694 | } | |
2695 | /* Handle secondary reloads for loads of FP registers from constant | |
2696 | expressions by forcing the constant into memory. | |
2697 | ||
2698 | use scratch_reg to hold the address of the memory location. | |
2699 | ||
2700 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
2701 | NO_REGS when presented with a const_int and an register class | |
2702 | containing only FP registers. Doing so unfortunately creates | |
2703 | more problems than it solves. Fix this for 2.5. */ | |
2704 | else if (fp_reg_operand (operand0, mode) | |
2705 | && CONSTANT_P (operand1) | |
2706 | && scratch_reg) | |
2707 | { | |
2708 | rtx xoperands[2]; | |
2709 | ||
2710 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2711 | it in SIMODE regardless of what mode it was originally given | |
2712 | to us. */ | |
2713 | scratch_reg = force_mode (SImode, scratch_reg); | |
2714 | ||
2715 | /* Force the constant into memory and put the address of the | |
2716 | memory location into scratch_reg. */ | |
2717 | xoperands[0] = scratch_reg; | |
2718 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
2719 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
2720 | ||
2721 | /* Now load the destination register. */ | |
2722 | emit_insn (gen_rtx_SET (mode, operand0, | |
2723 | gen_rtx_MEM (mode, scratch_reg))); | |
2724 | return 1; | |
2725 | } | |
2726 | ||
2727 | /* Now have insn-emit do whatever it normally does. */ | |
2728 | return 0; | |
2729 | } | |
2730 | ||
79e68feb RS |
2731 | /* Return a REG that occurs in ADDR with coefficient 1. |
2732 | ADDR can be effectively incremented by incrementing REG. */ | |
2733 | ||
2734 | static rtx | |
8a4a2253 | 2735 | find_addr_reg (rtx addr) |
79e68feb RS |
2736 | { |
2737 | while (GET_CODE (addr) == PLUS) | |
2738 | { | |
2739 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2740 | addr = XEXP (addr, 0); | |
2741 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2742 | addr = XEXP (addr, 1); | |
2743 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2744 | addr = XEXP (addr, 1); | |
2745 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2746 | addr = XEXP (addr, 0); | |
2747 | else | |
4761e388 | 2748 | gcc_unreachable (); |
79e68feb | 2749 | } |
4761e388 NS |
2750 | gcc_assert (GET_CODE (addr) == REG); |
2751 | return addr; | |
79e68feb | 2752 | } |
9ee3c687 | 2753 | |
c16eadc7 | 2754 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 2755 | |
5505f548 | 2756 | const char * |
8a4a2253 | 2757 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
2758 | { |
2759 | if (! operands_match_p (operands[0], operands[1])) | |
2760 | { | |
2761 | if (!ADDRESS_REG_P (operands[1])) | |
2762 | { | |
2763 | rtx tmp = operands[1]; | |
2764 | ||
2765 | operands[1] = operands[2]; | |
2766 | operands[2] = tmp; | |
2767 | } | |
2768 | ||
2769 | /* These insns can result from reloads to access | |
2770 | stack slots over 64k from the frame pointer. */ | |
2771 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 2772 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 2773 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 2774 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
2775 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
2776 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
2777 | } |
2778 | if (GET_CODE (operands[2]) == CONST_INT) | |
2779 | { | |
9ee3c687 JW |
2780 | if (INTVAL (operands[2]) > 0 |
2781 | && INTVAL (operands[2]) <= 8) | |
2782 | return "addq%.l %2,%0"; | |
2783 | if (INTVAL (operands[2]) < 0 | |
2784 | && INTVAL (operands[2]) >= -8) | |
2785 | { | |
c5c76735 | 2786 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
2787 | return "subq%.l %2,%0"; |
2788 | } | |
2789 | /* On the CPU32 it is faster to use two addql instructions to | |
2790 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 2791 | Likewise for subql. */ |
fe95f2f7 | 2792 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
2793 | { |
2794 | if (INTVAL (operands[2]) > 8 | |
2795 | && INTVAL (operands[2]) <= 16) | |
2796 | { | |
1d8eaa6b | 2797 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 2798 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
2799 | } |
2800 | if (INTVAL (operands[2]) < -8 | |
2801 | && INTVAL (operands[2]) >= -16) | |
2802 | { | |
c5c76735 | 2803 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 2804 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
2805 | } |
2806 | } | |
9ee3c687 JW |
2807 | if (ADDRESS_REG_P (operands[0]) |
2808 | && INTVAL (operands[2]) >= -0x8000 | |
2809 | && INTVAL (operands[2]) < 0x8000) | |
2810 | { | |
fe95f2f7 | 2811 | if (TUNE_68040) |
9ee3c687 JW |
2812 | return "add%.w %2,%0"; |
2813 | else | |
e6d98cb0 | 2814 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
2815 | } |
2816 | } | |
2817 | return "add%.l %2,%0"; | |
2818 | } | |
79e68feb RS |
2819 | \f |
2820 | /* Store in cc_status the expressions that the condition codes will | |
2821 | describe after execution of an instruction whose pattern is EXP. | |
2822 | Do not alter them if the instruction would not alter the cc's. */ | |
2823 | ||
2824 | /* On the 68000, all the insns to store in an address register fail to | |
2825 | set the cc's. However, in some cases these instructions can make it | |
2826 | possibly invalid to use the saved cc's. In those cases we clear out | |
2827 | some or all of the saved cc's so they won't be used. */ | |
2828 | ||
1d8eaa6b | 2829 | void |
8a4a2253 | 2830 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 2831 | { |
1a8965c4 | 2832 | if (GET_CODE (exp) == SET) |
79e68feb RS |
2833 | { |
2834 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 2835 | CC_STATUS_INIT; |
79e68feb RS |
2836 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
2837 | { | |
f5963e61 | 2838 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 2839 | cc_status.value1 = 0; |
f5963e61 | 2840 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
2841 | cc_status.value2 = 0; |
2842 | } | |
2843 | else if (!FP_REG_P (SET_DEST (exp)) | |
2844 | && SET_DEST (exp) != cc0_rtx | |
2845 | && (FP_REG_P (SET_SRC (exp)) | |
2846 | || GET_CODE (SET_SRC (exp)) == FIX | |
2847 | || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE | |
2848 | || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND)) | |
a0a7fbc9 | 2849 | CC_STATUS_INIT; |
79e68feb RS |
2850 | /* A pair of move insns doesn't produce a useful overall cc. */ |
2851 | else if (!FP_REG_P (SET_DEST (exp)) | |
2852 | && !FP_REG_P (SET_SRC (exp)) | |
2853 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
2854 | && (GET_CODE (SET_SRC (exp)) == REG | |
2855 | || GET_CODE (SET_SRC (exp)) == MEM | |
2856 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 2857 | CC_STATUS_INIT; |
e1dff52a | 2858 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
2859 | { |
2860 | cc_status.flags = 0; | |
e1dff52a KH |
2861 | cc_status.value1 = SET_DEST (exp); |
2862 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
2863 | } |
2864 | } | |
2865 | else if (GET_CODE (exp) == PARALLEL | |
2866 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
2867 | { | |
e1dff52a KH |
2868 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
2869 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
2870 | ||
2871 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 2872 | CC_STATUS_INIT; |
e1dff52a | 2873 | else if (dest != pc_rtx) |
79e68feb RS |
2874 | { |
2875 | cc_status.flags = 0; | |
e1dff52a KH |
2876 | cc_status.value1 = dest; |
2877 | cc_status.value2 = src; | |
79e68feb RS |
2878 | } |
2879 | } | |
2880 | else | |
2881 | CC_STATUS_INIT; | |
2882 | if (cc_status.value2 != 0 | |
2883 | && ADDRESS_REG_P (cc_status.value2) | |
2884 | && GET_MODE (cc_status.value2) == QImode) | |
2885 | CC_STATUS_INIT; | |
1a8965c4 | 2886 | if (cc_status.value2 != 0) |
79e68feb RS |
2887 | switch (GET_CODE (cc_status.value2)) |
2888 | { | |
996a5f59 | 2889 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 2890 | case ROTATE: case ROTATERT: |
a126dc3a RH |
2891 | /* These instructions always clear the overflow bit, and set |
2892 | the carry to the bit shifted out. */ | |
2893 | /* ??? We don't currently have a way to signal carry not valid, | |
2894 | nor do we check for it in the branch insns. */ | |
2895 | CC_STATUS_INIT; | |
2896 | break; | |
2897 | ||
2898 | case PLUS: case MINUS: case MULT: | |
2899 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
2900 | if (GET_MODE (cc_status.value2) != VOIDmode) |
2901 | cc_status.flags |= CC_NO_OVERFLOW; | |
2902 | break; | |
2903 | case ZERO_EXTEND: | |
2904 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
2905 | ends with a move insn moving r2 in r2's mode. | |
2906 | Thus, the cc's are set for r2. | |
7a1929e1 | 2907 | This can set N bit spuriously. */ |
79e68feb | 2908 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
2909 | |
2910 | default: | |
2911 | break; | |
79e68feb RS |
2912 | } |
2913 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
2914 | && cc_status.value2 | |
2915 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
2916 | cc_status.value2 = 0; | |
2917 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 2918 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
2919 | cc_status.flags = CC_IN_68881; |
2920 | } | |
2921 | \f | |
5505f548 | 2922 | const char * |
8a4a2253 | 2923 | output_move_const_double (rtx *operands) |
79e68feb | 2924 | { |
1a8965c4 | 2925 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2926 | |
1a8965c4 | 2927 | if (code != 0) |
79e68feb | 2928 | { |
1a8965c4 | 2929 | static char buf[40]; |
79e68feb | 2930 | |
3b4b85c9 | 2931 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2932 | return buf; |
79e68feb | 2933 | } |
1a8965c4 | 2934 | return "fmove%.d %1,%0"; |
79e68feb RS |
2935 | } |
2936 | ||
5505f548 | 2937 | const char * |
8a4a2253 | 2938 | output_move_const_single (rtx *operands) |
79e68feb | 2939 | { |
1a8965c4 | 2940 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2941 | |
1a8965c4 | 2942 | if (code != 0) |
79e68feb | 2943 | { |
1a8965c4 | 2944 | static char buf[40]; |
79e68feb | 2945 | |
3b4b85c9 | 2946 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2947 | return buf; |
79e68feb | 2948 | } |
1a8965c4 | 2949 | return "fmove%.s %f1,%0"; |
79e68feb RS |
2950 | } |
2951 | ||
2952 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
2953 | from the "fmovecr" instruction. | |
2954 | The value, anded with 0xff, gives the code to use in fmovecr | |
2955 | to get the desired constant. */ | |
2956 | ||
7a1929e1 | 2957 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
2958 | |
2959 | static int inited_68881_table = 0; | |
2960 | ||
5505f548 | 2961 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
2962 | "0.0", |
2963 | "1.0", | |
2964 | "10.0", | |
2965 | "100.0", | |
2966 | "10000.0", | |
2967 | "1e8", | |
2968 | "1e16" | |
a0a7fbc9 | 2969 | }; |
c1cfb2ae | 2970 | |
8b60264b | 2971 | static const int codes_68881[7] = { |
c1cfb2ae RS |
2972 | 0x0f, |
2973 | 0x32, | |
2974 | 0x33, | |
2975 | 0x34, | |
2976 | 0x35, | |
2977 | 0x36, | |
2978 | 0x37 | |
a0a7fbc9 | 2979 | }; |
c1cfb2ae RS |
2980 | |
2981 | REAL_VALUE_TYPE values_68881[7]; | |
2982 | ||
2983 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 2984 | strings_68881 to binary. */ |
c1cfb2ae RS |
2985 | |
2986 | void | |
8a4a2253 | 2987 | init_68881_table (void) |
c1cfb2ae RS |
2988 | { |
2989 | int i; | |
2990 | REAL_VALUE_TYPE r; | |
2991 | enum machine_mode mode; | |
2992 | ||
16d82c3c | 2993 | mode = SFmode; |
c1cfb2ae RS |
2994 | for (i = 0; i < 7; i++) |
2995 | { | |
2996 | if (i == 6) | |
16d82c3c | 2997 | mode = DFmode; |
c1cfb2ae RS |
2998 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
2999 | values_68881[i] = r; | |
3000 | } | |
3001 | inited_68881_table = 1; | |
3002 | } | |
79e68feb RS |
3003 | |
3004 | int | |
8a4a2253 | 3005 | standard_68881_constant_p (rtx x) |
79e68feb | 3006 | { |
c1cfb2ae RS |
3007 | REAL_VALUE_TYPE r; |
3008 | int i; | |
79e68feb | 3009 | |
e18db50d | 3010 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 3011 | used at all on those chips. */ |
9cf106c8 | 3012 | if (TUNE_68040_60) |
79e68feb RS |
3013 | return 0; |
3014 | ||
c1cfb2ae RS |
3015 | if (! inited_68881_table) |
3016 | init_68881_table (); | |
3017 | ||
3018 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3019 | ||
64c0b414 AS |
3020 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
3021 | is rejected. */ | |
c1cfb2ae RS |
3022 | for (i = 0; i < 6; i++) |
3023 | { | |
64c0b414 | 3024 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
3025 | return (codes_68881[i]); |
3026 | } | |
3027 | ||
79e68feb RS |
3028 | if (GET_MODE (x) == SFmode) |
3029 | return 0; | |
c1cfb2ae RS |
3030 | |
3031 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
3032 | return (codes_68881[6]); | |
3033 | ||
79e68feb RS |
3034 | /* larger powers of ten in the constants ram are not used |
3035 | because they are not equal to a `double' C constant. */ | |
3036 | return 0; | |
3037 | } | |
3038 | ||
3039 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3040 | or 0 if X is not a power of 2. */ | |
3041 | ||
3042 | int | |
8a4a2253 | 3043 | floating_exact_log2 (rtx x) |
79e68feb | 3044 | { |
c1cfb2ae | 3045 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3046 | int exp; |
79e68feb | 3047 | |
c1cfb2ae | 3048 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3049 | |
eaff3bf8 | 3050 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3051 | return 0; |
3052 | ||
eaff3bf8 RH |
3053 | exp = real_exponent (&r); |
3054 | real_2expN (&r1, exp); | |
3055 | if (REAL_VALUES_EQUAL (r1, r)) | |
3056 | return exp; | |
3057 | ||
79e68feb RS |
3058 | return 0; |
3059 | } | |
3060 | \f | |
79e68feb RS |
3061 | /* A C compound statement to output to stdio stream STREAM the |
3062 | assembler syntax for an instruction operand X. X is an RTL | |
3063 | expression. | |
3064 | ||
3065 | CODE is a value that can be used to specify one of several ways | |
3066 | of printing the operand. It is used when identical operands | |
3067 | must be printed differently depending on the context. CODE | |
3068 | comes from the `%' specification that was used to request | |
3069 | printing of the operand. If the specification was just `%DIGIT' | |
3070 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3071 | is the ASCII code for LTR. | |
3072 | ||
3073 | If X is a register, this macro should print the register's name. | |
3074 | The names can be found in an array `reg_names' whose type is | |
3075 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3076 | ||
3077 | When the machine description has a specification `%PUNCT' (a `%' | |
3078 | followed by a punctuation character), this macro is called with | |
3079 | a null pointer for X and the punctuation character for CODE. | |
3080 | ||
3081 | The m68k specific codes are: | |
3082 | ||
3083 | '.' for dot needed in Motorola-style opcode names. | |
3084 | '-' for an operand pushing on the stack: | |
3085 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3086 | '+' for an operand pushing on the stack: | |
3087 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3088 | '@' for a reference to the top word on the stack: | |
3089 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3090 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3091 | but & in SGS syntax). |
79e68feb RS |
3092 | '!' for the cc register (used in an `and to cc' insn). |
3093 | '$' for the letter `s' in an op code, but only on the 68040. | |
3094 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3095 | '/' for register prefix needed by longlong.h. |
79e68feb RS |
3096 | |
3097 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3098 | 'd' to force memory addressing to be absolute, not relative. | |
3099 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
3100 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3101 | or print pair of registers as rx:ry. | |
29ca003a RS |
3102 | 'p' print an address with @PLTPC attached, but only if the operand |
3103 | is not locally-bound. */ | |
79e68feb RS |
3104 | |
3105 | void | |
8a4a2253 | 3106 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3107 | { |
79e68feb RS |
3108 | if (letter == '.') |
3109 | { | |
e6d98cb0 BI |
3110 | if (MOTOROLA) |
3111 | fprintf (file, "."); | |
79e68feb RS |
3112 | } |
3113 | else if (letter == '#') | |
e6d98cb0 | 3114 | asm_fprintf (file, "%I"); |
79e68feb | 3115 | else if (letter == '-') |
e6d98cb0 | 3116 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 3117 | else if (letter == '+') |
e6d98cb0 | 3118 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 3119 | else if (letter == '@') |
e6d98cb0 | 3120 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 3121 | else if (letter == '!') |
e6d98cb0 | 3122 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3123 | else if (letter == '$') |
3124 | { | |
b101567e | 3125 | if (TARGET_68040) |
e6d98cb0 | 3126 | fprintf (file, "s"); |
79e68feb RS |
3127 | } |
3128 | else if (letter == '&') | |
3129 | { | |
b101567e | 3130 | if (TARGET_68040) |
e6d98cb0 | 3131 | fprintf (file, "d"); |
79e68feb | 3132 | } |
2ac5f14a | 3133 | else if (letter == '/') |
e6d98cb0 | 3134 | asm_fprintf (file, "%R"); |
29ca003a | 3135 | else if (letter == 'p') |
2c8ec431 | 3136 | { |
29ca003a RS |
3137 | output_addr_const (file, op); |
3138 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
3139 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 3140 | } |
79e68feb RS |
3141 | else if (GET_CODE (op) == REG) |
3142 | { | |
1a8965c4 AS |
3143 | if (letter == 'R') |
3144 | /* Print out the second register name of a register pair. | |
3145 | I.e., R (6) => 7. */ | |
01bbf777 | 3146 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3147 | else |
01bbf777 | 3148 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3149 | } |
3150 | else if (GET_CODE (op) == MEM) | |
3151 | { | |
3152 | output_address (XEXP (op, 0)); | |
3153 | if (letter == 'd' && ! TARGET_68020 | |
3154 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3155 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3156 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3157 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 3158 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 3159 | } |
79e68feb RS |
3160 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3161 | { | |
c1cfb2ae RS |
3162 | REAL_VALUE_TYPE r; |
3163 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3164 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3165 | } | |
3166 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3167 | { | |
3168 | REAL_VALUE_TYPE r; | |
3169 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3170 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3171 | } |
e2c0a924 | 3172 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3173 | { |
c1cfb2ae RS |
3174 | REAL_VALUE_TYPE r; |
3175 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3176 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3177 | } |
3178 | else | |
3179 | { | |
2c8ec431 DL |
3180 | /* Use `print_operand_address' instead of `output_addr_const' |
3181 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3182 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3183 | if (TARGET_PCREL |
3184 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3185 | print_operand_address (file, op); | |
3186 | else | |
3187 | output_addr_const (file, op); | |
79e68feb RS |
3188 | } |
3189 | } | |
3190 | ||
3191 | \f | |
3192 | /* A C compound statement to output to stdio stream STREAM the | |
3193 | assembler syntax for an instruction operand that is a memory | |
3194 | reference whose address is ADDR. ADDR is an RTL expression. | |
3195 | ||
3196 | Note that this contains a kludge that knows that the only reason | |
3197 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3198 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3199 | generates a label LInnn: on such an insn. | |
3200 | ||
3201 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3202 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3203 | ||
3204 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
3205 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
3206 | we want. This difference can be accommodated by using an assembler | |
3207 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
3208 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 3209 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
3210 | Some assemblers refuse all the above solutions. The workaround is to |
3211 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 3212 | right behavior. |
79e68feb RS |
3213 | |
3214 | They also do not like things like "pea 1.w", so we simple leave off | |
3215 | the .w on small constants. | |
3216 | ||
3217 | This routine is responsible for distinguishing between -fpic and -fPIC | |
3218 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3219 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3220 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb | 3221 | |
3b4b85c9 | 3222 | #if MOTOROLA |
a0a7fbc9 AS |
3223 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3224 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname) | |
3b4b85c9 | 3225 | #else /* !MOTOROLA */ |
a0a7fbc9 AS |
3226 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3227 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname) | |
3b4b85c9 | 3228 | #endif /* !MOTOROLA */ |
f4a6e73b | 3229 | |
79e68feb | 3230 | void |
8a4a2253 | 3231 | print_operand_address (FILE *file, rtx addr) |
79e68feb RS |
3232 | { |
3233 | register rtx reg1, reg2, breg, ireg; | |
3234 | rtx offset; | |
3235 | ||
3236 | switch (GET_CODE (addr)) | |
3237 | { | |
a0a7fbc9 AS |
3238 | case REG: |
3239 | fprintf (file, MOTOROLA ? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr))); | |
3240 | break; | |
3241 | case PRE_DEC: | |
3242 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", | |
3243 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3244 | break; | |
3245 | case POST_INC: | |
3246 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", | |
3247 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3248 | break; | |
3249 | case PLUS: | |
3250 | reg1 = reg2 = ireg = breg = offset = 0; | |
3251 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) | |
3252 | { | |
3253 | offset = XEXP (addr, 0); | |
3254 | addr = XEXP (addr, 1); | |
3255 | } | |
3256 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) | |
3257 | { | |
3258 | offset = XEXP (addr, 1); | |
3259 | addr = XEXP (addr, 0); | |
3260 | } | |
3261 | if (GET_CODE (addr) != PLUS) | |
3262 | { | |
3263 | ; | |
3264 | } | |
3265 | else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) | |
3266 | { | |
3267 | reg1 = XEXP (addr, 0); | |
3268 | addr = XEXP (addr, 1); | |
3269 | } | |
3270 | else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) | |
3271 | { | |
3272 | reg1 = XEXP (addr, 1); | |
3273 | addr = XEXP (addr, 0); | |
3274 | } | |
3275 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
3276 | { | |
3277 | reg1 = XEXP (addr, 0); | |
3278 | addr = XEXP (addr, 1); | |
3279 | } | |
3280 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
3281 | { | |
3282 | reg1 = XEXP (addr, 1); | |
3283 | addr = XEXP (addr, 0); | |
3284 | } | |
3285 | else if (GET_CODE (XEXP (addr, 0)) == REG) | |
3286 | { | |
3287 | reg1 = XEXP (addr, 0); | |
3288 | addr = XEXP (addr, 1); | |
3289 | } | |
3290 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3291 | { | |
3292 | reg1 = XEXP (addr, 1); | |
3293 | addr = XEXP (addr, 0); | |
3294 | } | |
3295 | if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT | |
3296 | || GET_CODE (addr) == SIGN_EXTEND) | |
3297 | { | |
3298 | if (reg1 == 0) | |
3299 | reg1 = addr; | |
3300 | else | |
3301 | reg2 = addr; | |
3302 | addr = 0; | |
3303 | } | |
79e68feb | 3304 | #if 0 /* for OLD_INDEXING */ |
a0a7fbc9 AS |
3305 | else if (GET_CODE (addr) == PLUS) |
3306 | { | |
3307 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3308 | { | |
3309 | reg2 = XEXP (addr, 0); | |
3310 | addr = XEXP (addr, 1); | |
3311 | } | |
3312 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3313 | { | |
3314 | reg2 = XEXP (addr, 1); | |
3315 | addr = XEXP (addr, 0); | |
3316 | } | |
3317 | } | |
79e68feb | 3318 | #endif |
a0a7fbc9 AS |
3319 | if (offset != 0) |
3320 | { | |
3321 | gcc_assert (!addr); | |
3322 | addr = offset; | |
3323 | } | |
3324 | if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND | |
3325 | || GET_CODE (reg1) == MULT)) | |
3326 | || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) | |
3327 | { | |
3328 | breg = reg2; | |
3329 | ireg = reg1; | |
3330 | } | |
3331 | else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) | |
3332 | { | |
3333 | breg = reg1; | |
3334 | ireg = reg2; | |
3335 | } | |
3336 | if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF | |
3337 | && ! (flag_pic && ireg == pic_offset_table_rtx)) | |
3338 | { | |
3339 | int scale = 1; | |
3340 | if (GET_CODE (ireg) == MULT) | |
3341 | { | |
3342 | scale = INTVAL (XEXP (ireg, 1)); | |
3343 | ireg = XEXP (ireg, 0); | |
3344 | } | |
3345 | if (GET_CODE (ireg) == SIGN_EXTEND) | |
3346 | { | |
3347 | ASM_OUTPUT_CASE_FETCH (file, | |
3348 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3349 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3350 | fprintf (file, "w"); | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | ASM_OUTPUT_CASE_FETCH (file, | |
3355 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3356 | M68K_REGNAME (REGNO (ireg))); | |
3357 | fprintf (file, "l"); | |
3358 | } | |
3359 | if (scale != 1) | |
3360 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3361 | putc (')', file); | |
3362 | break; | |
3363 | } | |
3364 | if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF | |
3365 | && ! (flag_pic && breg == pic_offset_table_rtx)) | |
3366 | { | |
3367 | ASM_OUTPUT_CASE_FETCH (file, | |
3368 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3369 | M68K_REGNAME (REGNO (breg))); | |
3370 | fprintf (file, "l)"); | |
3371 | break; | |
3372 | } | |
3373 | if (ireg != 0 || breg != 0) | |
3374 | { | |
3375 | int scale = 1; | |
4761e388 | 3376 | |
a0a7fbc9 AS |
3377 | gcc_assert (breg); |
3378 | gcc_assert (flag_pic || !addr || GET_CODE (addr) != LABEL_REF); | |
4761e388 | 3379 | |
a0a7fbc9 AS |
3380 | if (MOTOROLA) |
3381 | { | |
3382 | if (addr != 0) | |
3383 | { | |
3384 | output_addr_const (file, addr); | |
3385 | if (flag_pic && (breg == pic_offset_table_rtx)) | |
3386 | { | |
3387 | fprintf (file, "@GOT"); | |
3388 | if (flag_pic == 1) | |
3389 | fprintf (file, ".w"); | |
3390 | } | |
3391 | } | |
3392 | fprintf (file, "(%s", M68K_REGNAME (REGNO (breg))); | |
3393 | if (ireg != 0) | |
3394 | putc (',', file); | |
3395 | } | |
3396 | else /* !MOTOROLA */ | |
3397 | { | |
3398 | fprintf (file, "%s@(", M68K_REGNAME (REGNO (breg))); | |
3399 | if (addr != 0) | |
3400 | { | |
3401 | output_addr_const (file, addr); | |
3402 | if (breg == pic_offset_table_rtx) | |
3403 | switch (flag_pic) | |
e6d98cb0 | 3404 | { |
a0a7fbc9 AS |
3405 | case 1: |
3406 | fprintf (file, ":w"); | |
3407 | break; | |
3408 | case 2: | |
3409 | fprintf (file, ":l"); | |
3410 | break; | |
3411 | default: | |
3412 | break; | |
e6d98cb0 | 3413 | } |
a0a7fbc9 AS |
3414 | if (ireg != 0) |
3415 | putc (',', file); | |
3416 | } | |
3417 | } /* !MOTOROLA */ | |
3418 | if (ireg != 0 && GET_CODE (ireg) == MULT) | |
3419 | { | |
3420 | scale = INTVAL (XEXP (ireg, 1)); | |
3421 | ireg = XEXP (ireg, 0); | |
3422 | } | |
3423 | if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) | |
3424 | fprintf (file, MOTOROLA ? "%s.w" : "%s:w", | |
3425 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3426 | else if (ireg != 0) | |
3427 | fprintf (file, MOTOROLA ? "%s.l" : "%s:l", | |
3428 | M68K_REGNAME (REGNO (ireg))); | |
3429 | if (scale != 1) | |
3430 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3431 | putc (')', file); | |
3432 | break; | |
3433 | } | |
3434 | else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF | |
3435 | && ! (flag_pic && reg1 == pic_offset_table_rtx)) | |
3436 | { | |
3437 | ASM_OUTPUT_CASE_FETCH (file, | |
3438 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3439 | M68K_REGNAME (REGNO (reg1))); | |
3440 | fprintf (file, "l)"); | |
3441 | break; | |
3442 | } | |
3443 | /* FALL-THROUGH (is this really what we want?) */ | |
3444 | default: | |
3445 | if (GET_CODE (addr) == CONST_INT | |
3446 | && INTVAL (addr) < 0x8000 | |
3447 | && INTVAL (addr) >= -0x8000) | |
3448 | { | |
3449 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); | |
3450 | } | |
3451 | else if (GET_CODE (addr) == CONST_INT) | |
3452 | { | |
3453 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); | |
3454 | } | |
3455 | else if (TARGET_PCREL) | |
3456 | { | |
3457 | fputc ('(', file); | |
3458 | output_addr_const (file, addr); | |
3459 | if (flag_pic == 1) | |
3460 | asm_fprintf (file, ":w,%Rpc)"); | |
3461 | else | |
3462 | asm_fprintf (file, ":l,%Rpc)"); | |
3463 | } | |
3464 | else | |
3465 | { | |
3466 | /* Special case for SYMBOL_REF if the symbol name ends in | |
3467 | `.<letter>', this can be mistaken as a size suffix. Put | |
3468 | the name in parentheses. */ | |
3469 | if (GET_CODE (addr) == SYMBOL_REF | |
3470 | && strlen (XSTR (addr, 0)) > 2 | |
3471 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
3472 | { | |
3473 | putc ('(', file); | |
c2ac2ff6 | 3474 | output_addr_const (file, addr); |
a0a7fbc9 AS |
3475 | putc (')', file); |
3476 | } | |
3477 | else | |
3478 | output_addr_const (file, addr); | |
3479 | } | |
3480 | break; | |
79e68feb RS |
3481 | } |
3482 | } | |
af13f02d JW |
3483 | \f |
3484 | /* Check for cases where a clr insns can be omitted from code using | |
3485 | strict_low_part sets. For example, the second clrl here is not needed: | |
3486 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3487 | ||
3488 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3489 | insn we are checking for redundancy. TARGET is the register set by the | |
3490 | clear insn. */ | |
3491 | ||
8a4a2253 BI |
3492 | bool |
3493 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3494 | rtx target) | |
af13f02d JW |
3495 | { |
3496 | rtx p; | |
3497 | ||
3498 | p = prev_nonnote_insn (first_insn); | |
3499 | ||
3500 | while (p) | |
3501 | { | |
3502 | /* If it isn't an insn, then give up. */ | |
3503 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 3504 | return false; |
af13f02d JW |
3505 | |
3506 | if (reg_set_p (target, p)) | |
3507 | { | |
3508 | rtx set = single_set (p); | |
3509 | rtx dest; | |
3510 | ||
3511 | /* If it isn't an easy to recognize insn, then give up. */ | |
3512 | if (! set) | |
8a4a2253 | 3513 | return false; |
af13f02d JW |
3514 | |
3515 | dest = SET_DEST (set); | |
3516 | ||
3517 | /* If this sets the entire target register to zero, then our | |
3518 | first_insn is redundant. */ | |
3519 | if (rtx_equal_p (dest, target) | |
3520 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3521 | return true; |
af13f02d JW |
3522 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3523 | && GET_CODE (XEXP (dest, 0)) == REG | |
3524 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3525 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3526 | <= GET_MODE_SIZE (mode))) | |
3527 | /* This is a strict low part set which modifies less than | |
3528 | we are using, so it is safe. */ | |
3529 | ; | |
3530 | else | |
8a4a2253 | 3531 | return false; |
af13f02d JW |
3532 | } |
3533 | ||
3534 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3535 | } |
3536 | ||
8a4a2253 | 3537 | return false; |
af13f02d | 3538 | } |
67cd4f83 | 3539 | |
2c8ec431 DL |
3540 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3541 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3542 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3543 | |
3544 | We model this by restricting the meaning of the basic predicates | |
3545 | (general_operand, memory_operand, etc) to forbid the use of this | |
3546 | addressing mode, and then define the following predicates that permit | |
3547 | this addressing mode. These predicates can then be used for the | |
3548 | source operands of the appropriate instructions. | |
3549 | ||
3550 | n.b. While it is theoretically possible to change all machine patterns | |
3551 | to use this addressing more where permitted by the architecture, | |
3552 | it has only been implemented for "common" cases: SImode, HImode, and | |
3553 | QImode operands, and only for the principle operations that would | |
3554 | require this addressing mode: data movement and simple integer operations. | |
3555 | ||
3556 | In parallel with these new predicates, two new constraint letters | |
3557 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3558 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3559 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3560 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3561 | of how these constraints are used. | |
3562 | ||
3563 | The use of these predicates is strictly optional, though patterns that | |
3564 | don't will cause an extra reload register to be allocated where one | |
3565 | was not necessary: | |
3566 | ||
3567 | lea (abc:w,%pc),%a0 ; need to reload address | |
3568 | moveq &1,%d1 ; since write to pc-relative space | |
3569 | movel %d1,%a0@ ; is not allowed | |
3570 | ... | |
3571 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3572 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3573 | ||
3574 | For more info, consult tiemann@cygnus.com. | |
3575 | ||
3576 | ||
3577 | All of the ugliness with predicates and constraints is due to the | |
3578 | simple fact that the m68k does not allow a pc-relative addressing | |
3579 | mode as a destination. gcc does not distinguish between source and | |
3580 | destination addresses. Hence, if we claim that pc-relative address | |
3581 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3582 | end up with invalid code. To get around this problem, we left | |
3583 | pc-relative modes as invalid addresses, and then added special | |
3584 | predicates and constraints to accept them. | |
3585 | ||
3586 | A cleaner way to handle this is to modify gcc to distinguish | |
3587 | between source and destination addresses. We can then say that | |
3588 | pc-relative is a valid source address but not a valid destination | |
3589 | address, and hopefully avoid a lot of the predicate and constraint | |
3590 | hackery. Unfortunately, this would be a pretty big change. It would | |
3591 | be a useful change for a number of ports, but there aren't any current | |
3592 | plans to undertake this. | |
3593 | ||
3594 | ***************************************************************************/ | |
3595 | ||
3596 | ||
5505f548 | 3597 | const char * |
8a4a2253 | 3598 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3599 | { |
3600 | int logval; | |
3601 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 3602 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
3603 | && (DATA_REG_P (operands[0]) |
3604 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3605 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3606 | { |
3607 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3608 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 3609 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
3610 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3611 | CC_STATUS_INIT; | |
3612 | if (operands[2] == const0_rtx) | |
3613 | return "clr%.w %0"; | |
3614 | return "and%.w %2,%0"; | |
3615 | } | |
3616 | if (GET_CODE (operands[2]) == CONST_INT | |
3617 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
3618 | && (DATA_REG_P (operands[0]) | |
3619 | || offsettable_memref_p (operands[0]))) | |
3620 | { | |
3621 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 3622 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3623 | else |
3624 | { | |
b72f00af | 3625 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3626 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3627 | } |
3628 | /* This does not set condition codes in a standard way. */ | |
3629 | CC_STATUS_INIT; | |
3630 | return "bclr %1,%0"; | |
3631 | } | |
3632 | return "and%.l %2,%0"; | |
3633 | } | |
3634 | ||
5505f548 | 3635 | const char * |
8a4a2253 | 3636 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
3637 | { |
3638 | register int logval; | |
3639 | if (GET_CODE (operands[2]) == CONST_INT | |
3640 | && INTVAL (operands[2]) >> 16 == 0 | |
3641 | && (DATA_REG_P (operands[0]) | |
3642 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3643 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3644 | { |
3645 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3646 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3647 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3648 | CC_STATUS_INIT; | |
3649 | if (INTVAL (operands[2]) == 0xffff) | |
3650 | return "mov%.w %2,%0"; | |
3651 | return "or%.w %2,%0"; | |
3652 | } | |
3653 | if (GET_CODE (operands[2]) == CONST_INT | |
3654 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3655 | && (DATA_REG_P (operands[0]) | |
3656 | || offsettable_memref_p (operands[0]))) | |
3657 | { | |
3658 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3659 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3660 | else |
3661 | { | |
b72f00af | 3662 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3663 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3664 | } |
3665 | CC_STATUS_INIT; | |
3666 | return "bset %1,%0"; | |
3667 | } | |
3668 | return "or%.l %2,%0"; | |
3669 | } | |
3670 | ||
5505f548 | 3671 | const char * |
8a4a2253 | 3672 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
3673 | { |
3674 | register int logval; | |
3675 | if (GET_CODE (operands[2]) == CONST_INT | |
3676 | && INTVAL (operands[2]) >> 16 == 0 | |
3677 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 3678 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3679 | { |
3680 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 3681 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3682 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3683 | CC_STATUS_INIT; | |
3684 | if (INTVAL (operands[2]) == 0xffff) | |
3685 | return "not%.w %0"; | |
3686 | return "eor%.w %2,%0"; | |
3687 | } | |
3688 | if (GET_CODE (operands[2]) == CONST_INT | |
3689 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3690 | && (DATA_REG_P (operands[0]) | |
3691 | || offsettable_memref_p (operands[0]))) | |
3692 | { | |
3693 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3694 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3695 | else |
3696 | { | |
b72f00af | 3697 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3698 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3699 | } |
3700 | CC_STATUS_INIT; | |
3701 | return "bchg %1,%0"; | |
3702 | } | |
3703 | return "eor%.l %2,%0"; | |
3704 | } | |
7c262518 | 3705 | |
29ca003a RS |
3706 | /* Return the instruction that should be used for a call to address X, |
3707 | which is known to be in operand 0. */ | |
3708 | ||
3709 | const char * | |
3710 | output_call (rtx x) | |
3711 | { | |
3712 | if (symbolic_operand (x, VOIDmode)) | |
3713 | return m68k_symbolic_call; | |
3714 | else | |
3715 | return "jsr %a0"; | |
3716 | } | |
3717 | ||
45849738 BI |
3718 | #ifdef M68K_TARGET_COFF |
3719 | ||
3720 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
3721 | ||
3722 | static void | |
c18a5b6c MM |
3723 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
3724 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
3725 | { |
3726 | char flagchar; | |
3727 | ||
3728 | if (flags & SECTION_WRITE) | |
3729 | flagchar = 'd'; | |
3730 | else | |
3731 | flagchar = 'x'; | |
3732 | ||
3733 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
3734 | } | |
3735 | ||
3736 | #endif /* M68K_TARGET_COFF */ | |
3737 | ||
c590b625 | 3738 | static void |
8a4a2253 BI |
3739 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
3740 | HOST_WIDE_INT delta, | |
3741 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
3742 | tree function) | |
483ab821 | 3743 | { |
c590b625 RH |
3744 | rtx xops[1]; |
3745 | const char *fmt; | |
3746 | ||
3747 | if (delta > 0 && delta <= 8) | |
a0a7fbc9 AS |
3748 | asm_fprintf (file, (MOTOROLA |
3749 | ? "\taddq.l %I%d,4(%Rsp)\n" | |
3750 | : "\taddql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3751 | (int) delta); |
c590b625 | 3752 | else if (delta < 0 && delta >= -8) |
a0a7fbc9 AS |
3753 | asm_fprintf (file, (MOTOROLA |
3754 | ? "\tsubq.l %I%d,4(%Rsp)\n" | |
3755 | : "\tsubql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3756 | (int) -delta); |
5050d266 PB |
3757 | else if (TARGET_COLDFIRE) |
3758 | { | |
3759 | /* ColdFire can't add/sub a constant to memory unless it is in | |
3760 | the range of addq/subq. So load the value into %d0 and | |
3761 | then add it to 4(%sp). */ | |
3762 | if (delta >= -128 && delta <= 127) | |
a0a7fbc9 AS |
3763 | asm_fprintf (file, (MOTOROLA |
3764 | ? "\tmoveq.l %I%wd,%Rd0\n" | |
3765 | : "\tmoveql %I%wd,%Rd0\n"), | |
3766 | delta); | |
5050d266 | 3767 | else |
a0a7fbc9 AS |
3768 | asm_fprintf (file, (MOTOROLA |
3769 | ? "\tmove.l %I%wd,%Rd0\n" | |
3770 | : "\tmovel %I%wd,%Rd0\n"), | |
3771 | delta); | |
3772 | asm_fprintf (file, (MOTOROLA | |
3773 | ? "\tadd.l %Rd0,4(%Rsp)\n" | |
3774 | : "\taddl %Rd0,%Rsp@(4)\n")); | |
5050d266 | 3775 | } |
c590b625 | 3776 | else |
a0a7fbc9 AS |
3777 | asm_fprintf (file, (MOTOROLA |
3778 | ? "\tadd.l %I%wd,4(%Rsp)\n" | |
3779 | : "\taddl %I%wd,%Rsp@(4)\n"), | |
e6d98cb0 | 3780 | delta); |
c590b625 RH |
3781 | |
3782 | xops[0] = DECL_RTL (function); | |
3783 | ||
29ca003a RS |
3784 | gcc_assert (MEM_P (xops[0]) |
3785 | && symbolic_operand (XEXP (xops[0], 0), VOIDmode)); | |
3786 | xops[0] = XEXP (xops[0], 0); | |
3787 | ||
3788 | fmt = m68k_symbolic_jump; | |
3789 | if (m68k_symbolic_jump == NULL) | |
3790 | fmt = "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)"; | |
c590b625 RH |
3791 | |
3792 | output_asm_insn (fmt, xops); | |
483ab821 | 3793 | } |
8636be86 KH |
3794 | |
3795 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
3796 | ||
3797 | static rtx | |
3798 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3799 | int incoming ATTRIBUTE_UNUSED) | |
3800 | { | |
3801 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
3802 | } | |
cfca21cb PB |
3803 | |
3804 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
3805 | int | |
3806 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
3807 | unsigned int new_reg) | |
3808 | { | |
3809 | ||
3810 | /* Interrupt functions can only use registers that have already been | |
3811 | saved by the prologue, even if they would normally be | |
3812 | call-clobbered. */ | |
3813 | ||
3814 | if (m68k_interrupt_function_p (current_function_decl) | |
3815 | && !regs_ever_live[new_reg]) | |
3816 | return 0; | |
3817 | ||
3818 | return 1; | |
3819 | } | |
70028b61 PB |
3820 | |
3821 | /* Value is true if hard register REGNO can hold a value of machine-mode MODE. | |
3822 | On the 68000, the cpu registers can hold any mode except bytes in address | |
3823 | registers, but the 68881 registers can hold only SFmode or DFmode. */ | |
3824 | bool | |
3825 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
3826 | { | |
36e04090 | 3827 | if (DATA_REGNO_P (regno)) |
70028b61 | 3828 | { |
a0a7fbc9 AS |
3829 | /* Data Registers, can hold aggregate if fits in. */ |
3830 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
3831 | return true; | |
70028b61 | 3832 | } |
36e04090 | 3833 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 3834 | { |
a0a7fbc9 AS |
3835 | /* Address Registers, can't hold bytes, can hold aggregate if |
3836 | fits in. */ | |
3837 | if (GET_MODE_SIZE (mode) == 1) | |
3838 | return false; | |
3839 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) | |
3840 | return true; | |
70028b61 | 3841 | } |
36e04090 | 3842 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
3843 | { |
3844 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
3845 | smaller. */ |
3846 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
3847 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 3848 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 3849 | return true; |
70028b61 PB |
3850 | } |
3851 | return false; | |
3852 | } | |
dcc21c4c PB |
3853 | |
3854 | /* Return floating point values in a 68881 register. This makes 68881 code | |
3855 | a little bit faster. It also makes -msoft-float code incompatible with | |
3856 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 3857 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
3858 | If there is need for a hard-float ABI it is probably worth doing it |
3859 | properly and also passing function arguments in FP registers. */ | |
3860 | rtx | |
3861 | m68k_libcall_value (enum machine_mode mode) | |
3862 | { | |
3863 | switch (mode) { | |
3864 | case SFmode: | |
3865 | case DFmode: | |
3866 | case XFmode: | |
3867 | if (TARGET_68881) | |
3868 | return gen_rtx_REG (mode, 16); | |
3869 | break; | |
3870 | default: | |
3871 | break; | |
3872 | } | |
3873 | return gen_rtx_REG (mode, 0); | |
3874 | } | |
3875 | ||
3876 | rtx | |
3877 | m68k_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
3878 | { | |
3879 | enum machine_mode mode; | |
3880 | ||
3881 | mode = TYPE_MODE (valtype); | |
3882 | switch (mode) { | |
3883 | case SFmode: | |
3884 | case DFmode: | |
3885 | case XFmode: | |
3886 | if (TARGET_68881) | |
3887 | return gen_rtx_REG (mode, 16); | |
3888 | break; | |
3889 | default: | |
3890 | break; | |
3891 | } | |
3892 | ||
576c9028 KH |
3893 | /* If the function returns a pointer, push that into %a0. */ |
3894 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
3895 | /* For compatibility with the large body of existing code which | |
3896 | does not always properly declare external functions returning | |
3897 | pointer types, the m68k/SVR4 convention is to copy the value | |
3898 | returned for pointer functions from a0 to d0 in the function | |
3899 | epilogue, so that callers that have neglected to properly | |
3900 | declare the callee can still find the correct return value in | |
3901 | d0. */ | |
3902 | return gen_rtx_PARALLEL | |
3903 | (mode, | |
3904 | gen_rtvec (2, | |
3905 | gen_rtx_EXPR_LIST (VOIDmode, | |
3906 | gen_rtx_REG (mode, A0_REG), | |
3907 | const0_rtx), | |
3908 | gen_rtx_EXPR_LIST (VOIDmode, | |
3909 | gen_rtx_REG (mode, D0_REG), | |
3910 | const0_rtx))); | |
3911 | else if (POINTER_TYPE_P (valtype)) | |
3912 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 3913 | else |
576c9028 | 3914 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 3915 | } |