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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
96e45421 | 3 | 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
79e68feb RS |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
79e68feb | 21 | |
79e68feb | 22 | #include "config.h" |
f5220a5d | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
da932f04 | 26 | #include "tree.h" |
79e68feb | 27 | #include "rtl.h" |
49ad7cfa | 28 | #include "function.h" |
79e68feb RS |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
79e68feb RS |
31 | #include "insn-config.h" |
32 | #include "conditions.h" | |
79e68feb RS |
33 | #include "output.h" |
34 | #include "insn-attr.h" | |
1d8eaa6b | 35 | #include "recog.h" |
718f9c0f | 36 | #include "diagnostic-core.h" |
6d5f49b2 RH |
37 | #include "expr.h" |
38 | #include "reload.h" | |
5505f548 | 39 | #include "tm_p.h" |
672a6f42 NB |
40 | #include "target.h" |
41 | #include "target-def.h" | |
2cc07db4 | 42 | #include "debug.h" |
79e68feb | 43 | #include "flags.h" |
6fb5fa3c | 44 | #include "df.h" |
b8c96320 MK |
45 | /* ??? Need to add a dependency between m68k.o and sched-int.h. */ |
46 | #include "sched-int.h" | |
47 | #include "insn-codes.h" | |
75df395f | 48 | #include "ggc.h" |
96e45421 | 49 | #include "opts.h" |
79e68feb | 50 | |
a4e9467d RZ |
51 | enum reg_class regno_reg_class[] = |
52 | { | |
53 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
54 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
55 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
56 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
57 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
58 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
59 | ADDR_REGS | |
60 | }; | |
61 | ||
62 | ||
a40ed0f3 KH |
63 | /* The minimum number of integer registers that we want to save with the |
64 | movem instruction. Using two movel instructions instead of a single | |
65 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
66 | code size. */ | |
67 | #define MIN_MOVEM_REGS 3 | |
68 | ||
69 | /* The minimum number of floating point registers that we want to save | |
70 | with the fmovem instruction. */ | |
71 | #define MIN_FMOVEM_REGS 1 | |
72 | ||
ff482c8d | 73 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
74 | struct m68k_frame |
75 | { | |
76 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 77 | HOST_WIDE_INT offset; |
3d74bc09 BI |
78 | |
79 | /* Offset of FPU registers. */ | |
80 | HOST_WIDE_INT foffset; | |
81 | ||
82 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 83 | HOST_WIDE_INT size; |
3d74bc09 BI |
84 | |
85 | /* Data and address register. */ | |
48ed72a4 PB |
86 | int reg_no; |
87 | unsigned int reg_mask; | |
3d74bc09 BI |
88 | |
89 | /* FPU registers. */ | |
48ed72a4 PB |
90 | int fpu_no; |
91 | unsigned int fpu_mask; | |
3d74bc09 BI |
92 | |
93 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
94 | HOST_WIDE_INT frame_pointer_offset; |
95 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
96 | |
97 | /* Function which the above information refers to. */ | |
98 | int funcdef_no; | |
48ed72a4 PB |
99 | }; |
100 | ||
3d74bc09 BI |
101 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
102 | static struct m68k_frame current_frame; | |
103 | ||
fc2241eb RS |
104 | /* Structure describing an m68k address. |
105 | ||
106 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
107 | with null fields evaluating to 0. Here: | |
108 | ||
109 | - BASE satisfies m68k_legitimate_base_reg_p | |
110 | - INDEX satisfies m68k_legitimate_index_reg_p | |
111 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
112 | ||
113 | INDEX is either HImode or SImode. The other fields are SImode. | |
114 | ||
115 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
116 | the address is (BASE)+. */ | |
117 | struct m68k_address { | |
118 | enum rtx_code code; | |
119 | rtx base; | |
120 | rtx index; | |
121 | rtx offset; | |
122 | int scale; | |
123 | }; | |
124 | ||
b8c96320 | 125 | static int m68k_sched_adjust_cost (rtx, rtx, rtx, int); |
96fcacb7 | 126 | static int m68k_sched_issue_rate (void); |
b8c96320 MK |
127 | static int m68k_sched_variable_issue (FILE *, int, rtx, int); |
128 | static void m68k_sched_md_init_global (FILE *, int, int); | |
129 | static void m68k_sched_md_finish_global (FILE *, int); | |
130 | static void m68k_sched_md_init (FILE *, int, int); | |
131 | static void m68k_sched_dfa_pre_advance_cycle (void); | |
132 | static void m68k_sched_dfa_post_advance_cycle (void); | |
96fcacb7 | 133 | static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); |
b8c96320 | 134 | |
7b5cbb57 | 135 | static bool m68k_can_eliminate (const int, const int); |
5efd84c5 | 136 | static void m68k_conditional_register_usage (void); |
c6c3dba9 | 137 | static bool m68k_legitimate_address_p (enum machine_mode, rtx, bool); |
c5387660 | 138 | static void m68k_option_override (void); |
03e69b12 | 139 | static void m68k_override_options_after_change (void); |
8a4a2253 BI |
140 | static rtx find_addr_reg (rtx); |
141 | static const char *singlemove_string (rtx *); | |
8a4a2253 BI |
142 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
143 | HOST_WIDE_INT, tree); | |
8636be86 | 144 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
145 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
146 | tree args, int flags, | |
147 | bool *no_add_attrs); | |
3d74bc09 | 148 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 149 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
f7e70894 | 150 | static bool m68k_ok_for_sibcall_p (tree, tree); |
75df395f | 151 | static bool m68k_tls_symbol_p (rtx); |
506d7b68 | 152 | static rtx m68k_legitimize_address (rtx, rtx, enum machine_mode); |
f40751dd | 153 | static bool m68k_rtx_costs (rtx, int, int, int *, bool); |
1c445f03 | 154 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
511e41e5 | 155 | static bool m68k_return_in_memory (const_tree, const_tree); |
1c445f03 | 156 | #endif |
75df395f | 157 | static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
e0601576 | 158 | static void m68k_trampoline_init (rtx, tree, rtx); |
079e7538 | 159 | static int m68k_return_pops_args (tree, tree, int); |
7b0f476d | 160 | static rtx m68k_delegitimize_address (rtx); |
d5cc9181 | 161 | static void m68k_function_arg_advance (cumulative_args_t, enum machine_mode, |
13d3961c | 162 | const_tree, bool); |
d5cc9181 | 163 | static rtx m68k_function_arg (cumulative_args_t, enum machine_mode, |
13d3961c | 164 | const_tree, bool); |
fbbf66e7 | 165 | static bool m68k_cannot_force_const_mem (enum machine_mode mode, rtx x); |
79e68feb | 166 | \f |
672a6f42 | 167 | /* Initialize the GCC target structure. */ |
301d03af RS |
168 | |
169 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
170 | #undef TARGET_ASM_ALIGNED_HI_OP | |
171 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
172 | #endif | |
173 | ||
174 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
175 | #undef TARGET_ASM_BYTE_OP | |
176 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
177 | #undef TARGET_ASM_ALIGNED_HI_OP | |
178 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
179 | #undef TARGET_ASM_ALIGNED_SI_OP | |
180 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
181 | #endif | |
182 | ||
183 | #if INT_OP_GROUP == INT_OP_DC | |
184 | #undef TARGET_ASM_BYTE_OP | |
185 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
186 | #undef TARGET_ASM_ALIGNED_HI_OP | |
187 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
188 | #undef TARGET_ASM_ALIGNED_SI_OP | |
189 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
190 | #endif | |
191 | ||
192 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
193 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
194 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
195 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
196 | ||
c590b625 RH |
197 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
198 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 | 199 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 200 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 201 | |
1bc7c5b6 ZW |
202 | #undef TARGET_ASM_FILE_START_APP_OFF |
203 | #define TARGET_ASM_FILE_START_APP_OFF true | |
204 | ||
506d7b68 PB |
205 | #undef TARGET_LEGITIMIZE_ADDRESS |
206 | #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address | |
207 | ||
b8c96320 MK |
208 | #undef TARGET_SCHED_ADJUST_COST |
209 | #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost | |
210 | ||
96fcacb7 MK |
211 | #undef TARGET_SCHED_ISSUE_RATE |
212 | #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate | |
213 | ||
b8c96320 MK |
214 | #undef TARGET_SCHED_VARIABLE_ISSUE |
215 | #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue | |
216 | ||
217 | #undef TARGET_SCHED_INIT_GLOBAL | |
218 | #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global | |
219 | ||
220 | #undef TARGET_SCHED_FINISH_GLOBAL | |
221 | #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global | |
222 | ||
223 | #undef TARGET_SCHED_INIT | |
224 | #define TARGET_SCHED_INIT m68k_sched_md_init | |
225 | ||
226 | #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE | |
227 | #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle | |
228 | ||
229 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
230 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle | |
231 | ||
96fcacb7 MK |
232 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
233 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
234 | m68k_sched_first_cycle_multipass_dfa_lookahead | |
235 | ||
c5387660 JM |
236 | #undef TARGET_OPTION_OVERRIDE |
237 | #define TARGET_OPTION_OVERRIDE m68k_option_override | |
238 | ||
03e69b12 MP |
239 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
240 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change | |
241 | ||
3c50106f RH |
242 | #undef TARGET_RTX_COSTS |
243 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
244 | ||
48ed72a4 PB |
245 | #undef TARGET_ATTRIBUTE_TABLE |
246 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
247 | ||
8636be86 | 248 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 249 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
8636be86 KH |
250 | |
251 | #undef TARGET_STRUCT_VALUE_RTX | |
252 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
253 | ||
7ffb5e78 | 254 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
fbbf66e7 | 255 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem |
7ffb5e78 | 256 | |
f7e70894 RS |
257 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
258 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
259 | ||
1c445f03 NS |
260 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
261 | #undef TARGET_RETURN_IN_MEMORY | |
262 | #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory | |
263 | #endif | |
264 | ||
75df395f MK |
265 | #ifdef HAVE_AS_TLS |
266 | #undef TARGET_HAVE_TLS | |
267 | #define TARGET_HAVE_TLS (true) | |
268 | ||
269 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
270 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel | |
271 | #endif | |
272 | ||
c6c3dba9 PB |
273 | #undef TARGET_LEGITIMATE_ADDRESS_P |
274 | #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p | |
275 | ||
7b5cbb57 AS |
276 | #undef TARGET_CAN_ELIMINATE |
277 | #define TARGET_CAN_ELIMINATE m68k_can_eliminate | |
278 | ||
5efd84c5 NF |
279 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
280 | #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage | |
281 | ||
e0601576 RH |
282 | #undef TARGET_TRAMPOLINE_INIT |
283 | #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init | |
284 | ||
079e7538 NF |
285 | #undef TARGET_RETURN_POPS_ARGS |
286 | #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args | |
287 | ||
7b0f476d AS |
288 | #undef TARGET_DELEGITIMIZE_ADDRESS |
289 | #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address | |
290 | ||
13d3961c NF |
291 | #undef TARGET_FUNCTION_ARG |
292 | #define TARGET_FUNCTION_ARG m68k_function_arg | |
293 | ||
294 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
295 | #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance | |
296 | ||
1a627b35 RS |
297 | #undef TARGET_LEGITIMATE_CONSTANT_P |
298 | #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p | |
299 | ||
48ed72a4 PB |
300 | static const struct attribute_spec m68k_attribute_table[] = |
301 | { | |
62d784f7 KT |
302 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
303 | affects_type_identity } */ | |
304 | { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute, | |
305 | false }, | |
306 | { "interrupt_handler", 0, 0, true, false, false, | |
307 | m68k_handle_fndecl_attribute, false }, | |
308 | { "interrupt_thread", 0, 0, true, false, false, | |
309 | m68k_handle_fndecl_attribute, false }, | |
310 | { NULL, 0, 0, false, false, false, NULL, false } | |
48ed72a4 PB |
311 | }; |
312 | ||
f6897b10 | 313 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 314 | \f |
900ec02d JB |
315 | /* Base flags for 68k ISAs. */ |
316 | #define FL_FOR_isa_00 FL_ISA_68000 | |
317 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
318 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
319 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
320 | not to. */ | |
321 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
322 | | FL_BITFIELD | FL_68881) | |
323 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
324 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
325 | ||
326 | /* Base flags for ColdFire ISAs. */ | |
327 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
328 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
329 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
330 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
4e2b26aa | 331 | /* ISA_C is not upwardly compatible with ISA_B. */ |
8c5c99dc | 332 | #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP) |
900ec02d JB |
333 | |
334 | enum m68k_isa | |
335 | { | |
336 | /* Traditional 68000 instruction sets. */ | |
337 | isa_00, | |
338 | isa_10, | |
339 | isa_20, | |
340 | isa_40, | |
341 | isa_cpu32, | |
342 | /* ColdFire instruction set variants. */ | |
343 | isa_a, | |
344 | isa_aplus, | |
345 | isa_b, | |
346 | isa_c, | |
347 | isa_max | |
348 | }; | |
349 | ||
350 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
351 | struct m68k_target_selection | |
352 | { | |
353 | /* The argument being described. */ | |
354 | const char *name; | |
355 | ||
356 | /* For -mcpu, this is the device selected by the option. | |
357 | For -mtune and -march, it is a representative device | |
358 | for the microarchitecture or ISA respectively. */ | |
359 | enum target_device device; | |
360 | ||
361 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
362 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
363 | const char *family; | |
364 | enum uarch_type microarch; | |
365 | enum m68k_isa isa; | |
366 | unsigned long flags; | |
367 | }; | |
368 | ||
369 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
370 | static const struct m68k_target_selection all_devices[] = | |
371 | { | |
372 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
373 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
374 | #include "m68k-devices.def" | |
375 | #undef M68K_DEVICE | |
376 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
377 | }; | |
378 | ||
379 | /* A list of all ISAs, mapping each one to a representative device. | |
380 | Used for -march selection. */ | |
381 | static const struct m68k_target_selection all_isas[] = | |
382 | { | |
47c94d21 JM |
383 | #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
384 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
385 | #include "m68k-isas.def" | |
386 | #undef M68K_ISA | |
900ec02d JB |
387 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
388 | }; | |
389 | ||
390 | /* A list of all microarchitectures, mapping each one to a representative | |
391 | device. Used for -mtune selection. */ | |
392 | static const struct m68k_target_selection all_microarchs[] = | |
393 | { | |
47c94d21 JM |
394 | #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
395 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
396 | #include "m68k-microarchs.def" | |
397 | #undef M68K_MICROARCH | |
900ec02d JB |
398 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
399 | }; | |
400 | \f | |
401 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
402 | or null for options that have not been used. */ | |
403 | const struct m68k_target_selection *m68k_cpu_entry; | |
404 | const struct m68k_target_selection *m68k_arch_entry; | |
405 | const struct m68k_target_selection *m68k_tune_entry; | |
406 | ||
407 | /* Which CPU we are generating code for. */ | |
408 | enum target_device m68k_cpu; | |
409 | ||
410 | /* Which microarchitecture to tune for. */ | |
411 | enum uarch_type m68k_tune; | |
412 | ||
413 | /* Which FPU to use. */ | |
414 | enum fpu_type m68k_fpu; | |
4af06170 | 415 | |
900ec02d JB |
416 | /* The set of FL_* flags that apply to the target processor. */ |
417 | unsigned int m68k_cpu_flags; | |
29ca003a | 418 | |
03b3e271 KH |
419 | /* The set of FL_* flags that apply to the processor to be tuned for. */ |
420 | unsigned int m68k_tune_flags; | |
421 | ||
29ca003a RS |
422 | /* Asm templates for calling or jumping to an arbitrary symbolic address, |
423 | or NULL if such calls or jumps are not supported. The address is held | |
424 | in operand 0. */ | |
425 | const char *m68k_symbolic_call; | |
426 | const char *m68k_symbolic_jump; | |
c47b0cb4 MK |
427 | |
428 | /* Enum variable that corresponds to m68k_symbolic_call values. */ | |
429 | enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; | |
430 | ||
900ec02d | 431 | \f |
c5387660 | 432 | /* Implement TARGET_OPTION_OVERRIDE. */ |
ef1dbfb0 | 433 | |
c5387660 JM |
434 | static void |
435 | m68k_option_override (void) | |
ef1dbfb0 | 436 | { |
900ec02d JB |
437 | const struct m68k_target_selection *entry; |
438 | unsigned long target_mask; | |
439 | ||
47c94d21 JM |
440 | if (global_options_set.x_m68k_arch_option) |
441 | m68k_arch_entry = &all_isas[m68k_arch_option]; | |
442 | ||
443 | if (global_options_set.x_m68k_cpu_option) | |
444 | m68k_cpu_entry = &all_devices[(int) m68k_cpu_option]; | |
445 | ||
446 | if (global_options_set.x_m68k_tune_option) | |
447 | m68k_tune_entry = &all_microarchs[(int) m68k_tune_option]; | |
448 | ||
900ec02d JB |
449 | /* User can choose: |
450 | ||
451 | -mcpu= | |
452 | -march= | |
453 | -mtune= | |
454 | ||
455 | -march=ARCH should generate code that runs any processor | |
456 | implementing architecture ARCH. -mcpu=CPU should override -march | |
457 | and should generate code that runs on processor CPU, making free | |
458 | use of any instructions that CPU understands. -mtune=UARCH applies | |
9f5ed61a | 459 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
900ec02d JB |
460 | not change the target architecture. */ |
461 | if (m68k_cpu_entry) | |
462 | { | |
463 | /* Complain if the -march setting is for a different microarchitecture, | |
464 | or includes flags that the -mcpu setting doesn't. */ | |
465 | if (m68k_arch_entry | |
466 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
467 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
468 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
469 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
470 | ||
471 | entry = m68k_cpu_entry; | |
472 | } | |
473 | else | |
474 | entry = m68k_arch_entry; | |
475 | ||
476 | if (!entry) | |
477 | entry = all_devices + TARGET_CPU_DEFAULT; | |
478 | ||
479 | m68k_cpu_flags = entry->flags; | |
480 | ||
481 | /* Use the architecture setting to derive default values for | |
482 | certain flags. */ | |
483 | target_mask = 0; | |
8785d88c KH |
484 | |
485 | /* ColdFire is lenient about alignment. */ | |
486 | if (!TARGET_COLDFIRE) | |
487 | target_mask |= MASK_STRICT_ALIGNMENT; | |
488 | ||
900ec02d JB |
489 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) |
490 | target_mask |= MASK_BITFIELD; | |
491 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
492 | target_mask |= MASK_CF_HWDIV; | |
493 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
494 | target_mask |= MASK_HARD_FLOAT; | |
495 | target_flags |= target_mask & ~target_flags_explicit; | |
496 | ||
497 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
498 | m68k_cpu = entry->device; | |
499 | if (m68k_tune_entry) | |
03b3e271 KH |
500 | { |
501 | m68k_tune = m68k_tune_entry->microarch; | |
502 | m68k_tune_flags = m68k_tune_entry->flags; | |
503 | } | |
900ec02d JB |
504 | #ifdef M68K_DEFAULT_TUNE |
505 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
03b3e271 KH |
506 | { |
507 | enum target_device dev; | |
508 | dev = all_microarchs[M68K_DEFAULT_TUNE].device; | |
509 | m68k_tune_flags = all_devices[dev]->flags; | |
510 | } | |
900ec02d JB |
511 | #endif |
512 | else | |
03b3e271 KH |
513 | { |
514 | m68k_tune = entry->microarch; | |
515 | m68k_tune_flags = entry->flags; | |
516 | } | |
900ec02d JB |
517 | |
518 | /* Set the type of FPU. */ | |
519 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
520 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
521 | : FPUTYPE_68881); | |
522 | ||
a2ef3db7 BI |
523 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
524 | * both specified together. Doing so simply doesn't make sense. | |
525 | */ | |
526 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
527 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
528 | ||
529 | /* If we're generating code for a separate A5 relative data segment, | |
530 | * we've got to enable -fPIC as well. This might be relaxable to | |
531 | * -fpic but it hasn't been tested properly. | |
532 | */ | |
533 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
534 | flag_pic = 2; | |
535 | ||
abe92a04 RS |
536 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
537 | error if the target does not support them. */ | |
538 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
539 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
540 | |
541 | /* ??? A historic way of turning on pic, or is this intended to | |
542 | be an embedded thing that doesn't have the same name binding | |
543 | significance that it does on hosted ELF systems? */ | |
544 | if (TARGET_PCREL && flag_pic == 0) | |
545 | flag_pic = 1; | |
546 | ||
29ca003a RS |
547 | if (!flag_pic) |
548 | { | |
c47b0cb4 MK |
549 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR; |
550 | ||
29ca003a | 551 | m68k_symbolic_jump = "jra %a0"; |
29ca003a RS |
552 | } |
553 | else if (TARGET_ID_SHARED_LIBRARY) | |
554 | /* All addresses must be loaded from the GOT. */ | |
555 | ; | |
4e2b26aa | 556 | else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) |
29ca003a RS |
557 | { |
558 | if (TARGET_PCREL) | |
c47b0cb4 | 559 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C; |
4e2b26aa | 560 | else |
c47b0cb4 MK |
561 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P; |
562 | ||
4e2b26aa NS |
563 | if (TARGET_ISAC) |
564 | /* No unconditional long branch */; | |
565 | else if (TARGET_PCREL) | |
da398bb5 | 566 | m68k_symbolic_jump = "bra%.l %c0"; |
29ca003a | 567 | else |
da398bb5 | 568 | m68k_symbolic_jump = "bra%.l %p0"; |
29ca003a RS |
569 | /* Turn off function cse if we are doing PIC. We always want |
570 | function call to be done as `bsr foo@PLTPC'. */ | |
571 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
572 | clear how intentional that is. */ | |
573 | flag_no_function_cse = 1; | |
574 | } | |
adf2ac37 | 575 | |
c47b0cb4 MK |
576 | switch (m68k_symbolic_call_var) |
577 | { | |
578 | case M68K_SYMBOLIC_CALL_JSR: | |
c47b0cb4 | 579 | m68k_symbolic_call = "jsr %a0"; |
c47b0cb4 MK |
580 | break; |
581 | ||
582 | case M68K_SYMBOLIC_CALL_BSR_C: | |
da398bb5 | 583 | m68k_symbolic_call = "bsr%.l %c0"; |
c47b0cb4 MK |
584 | break; |
585 | ||
586 | case M68K_SYMBOLIC_CALL_BSR_P: | |
da398bb5 | 587 | m68k_symbolic_call = "bsr%.l %p0"; |
c47b0cb4 MK |
588 | break; |
589 | ||
590 | case M68K_SYMBOLIC_CALL_NONE: | |
591 | gcc_assert (m68k_symbolic_call == NULL); | |
592 | break; | |
593 | ||
594 | default: | |
595 | gcc_unreachable (); | |
596 | } | |
597 | ||
aaca7021 RZ |
598 | #ifndef ASM_OUTPUT_ALIGN_WITH_NOP |
599 | if (align_labels > 2) | |
600 | { | |
601 | warning (0, "-falign-labels=%d is not supported", align_labels); | |
602 | align_labels = 0; | |
603 | } | |
604 | if (align_loops > 2) | |
605 | { | |
606 | warning (0, "-falign-loops=%d is not supported", align_loops); | |
607 | align_loops = 0; | |
608 | } | |
609 | #endif | |
610 | ||
adf2ac37 | 611 | SUBTARGET_OVERRIDE_OPTIONS; |
c47b0cb4 MK |
612 | |
613 | /* Setup scheduling options. */ | |
826fadba MK |
614 | if (TUNE_CFV1) |
615 | m68k_sched_cpu = CPU_CFV1; | |
616 | else if (TUNE_CFV2) | |
617 | m68k_sched_cpu = CPU_CFV2; | |
618 | else if (TUNE_CFV3) | |
619 | m68k_sched_cpu = CPU_CFV3; | |
96fcacb7 MK |
620 | else if (TUNE_CFV4) |
621 | m68k_sched_cpu = CPU_CFV4; | |
c47b0cb4 MK |
622 | else |
623 | { | |
624 | m68k_sched_cpu = CPU_UNKNOWN; | |
625 | flag_schedule_insns = 0; | |
626 | flag_schedule_insns_after_reload = 0; | |
627 | flag_modulo_sched = 0; | |
628 | } | |
826fadba MK |
629 | |
630 | if (m68k_sched_cpu != CPU_UNKNOWN) | |
631 | { | |
632 | if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0) | |
633 | m68k_sched_mac = MAC_CF_EMAC; | |
634 | else if ((m68k_cpu_flags & FL_CF_MAC) != 0) | |
635 | m68k_sched_mac = MAC_CF_MAC; | |
636 | else | |
637 | m68k_sched_mac = MAC_NO; | |
638 | } | |
ef1dbfb0 | 639 | } |
7eb4f044 | 640 | |
03e69b12 MP |
641 | /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */ |
642 | ||
643 | static void | |
644 | m68k_override_options_after_change (void) | |
645 | { | |
646 | if (m68k_sched_cpu == CPU_UNKNOWN) | |
647 | { | |
648 | flag_schedule_insns = 0; | |
649 | flag_schedule_insns_after_reload = 0; | |
650 | flag_modulo_sched = 0; | |
651 | } | |
652 | } | |
653 | ||
7eb4f044 NS |
654 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the |
655 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
656 | if -mcpu was not passed. */ | |
657 | ||
658 | const char * | |
659 | m68k_cpp_cpu_ident (const char *prefix) | |
660 | { | |
661 | if (!m68k_cpu_entry) | |
662 | return NULL; | |
663 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
664 | } | |
665 | ||
666 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
667 | given argument and NAME is the name of the representative device for | |
668 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
669 | ||
670 | const char * | |
671 | m68k_cpp_cpu_family (const char *prefix) | |
672 | { | |
673 | if (!m68k_cpu_entry) | |
674 | return NULL; | |
675 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
676 | } | |
79e68feb | 677 | \f |
2bccb817 KH |
678 | /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or |
679 | "interrupt_handler" attribute and interrupt_thread if FUNC has an | |
680 | "interrupt_thread" attribute. Otherwise, return | |
681 | m68k_fk_normal_function. */ | |
a4242737 KH |
682 | |
683 | enum m68k_function_kind | |
684 | m68k_get_function_kind (tree func) | |
48ed72a4 PB |
685 | { |
686 | tree a; | |
687 | ||
fa157b28 NS |
688 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
689 | ||
2bccb817 KH |
690 | a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); |
691 | if (a != NULL_TREE) | |
692 | return m68k_fk_interrupt_handler; | |
693 | ||
48ed72a4 | 694 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
a4242737 KH |
695 | if (a != NULL_TREE) |
696 | return m68k_fk_interrupt_handler; | |
697 | ||
698 | a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); | |
699 | if (a != NULL_TREE) | |
700 | return m68k_fk_interrupt_thread; | |
701 | ||
702 | return m68k_fk_normal_function; | |
48ed72a4 PB |
703 | } |
704 | ||
705 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
706 | struct attribute_spec.handler. */ | |
707 | static tree | |
708 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
709 | tree args ATTRIBUTE_UNUSED, | |
710 | int flags ATTRIBUTE_UNUSED, | |
711 | bool *no_add_attrs) | |
712 | { | |
713 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
714 | { | |
29d08eba JM |
715 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
716 | name); | |
48ed72a4 PB |
717 | *no_add_attrs = true; |
718 | } | |
719 | ||
a4242737 KH |
720 | if (m68k_get_function_kind (*node) != m68k_fk_normal_function) |
721 | { | |
722 | error ("multiple interrupt attributes not allowed"); | |
723 | *no_add_attrs = true; | |
724 | } | |
725 | ||
726 | if (!TARGET_FIDOA | |
727 | && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) | |
728 | { | |
729 | error ("interrupt_thread is available only on fido"); | |
730 | *no_add_attrs = true; | |
731 | } | |
732 | ||
48ed72a4 PB |
733 | return NULL_TREE; |
734 | } | |
860c4900 BI |
735 | |
736 | static void | |
3d74bc09 | 737 | m68k_compute_frame_layout (void) |
860c4900 BI |
738 | { |
739 | int regno, saved; | |
a40ed0f3 | 740 | unsigned int mask; |
a4242737 KH |
741 | enum m68k_function_kind func_kind = |
742 | m68k_get_function_kind (current_function_decl); | |
743 | bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; | |
744 | bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; | |
860c4900 | 745 | |
3d74bc09 BI |
746 | /* Only compute the frame once per function. |
747 | Don't cache information until reload has been completed. */ | |
748 | if (current_frame.funcdef_no == current_function_funcdef_no | |
749 | && reload_completed) | |
750 | return; | |
751 | ||
752 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 | 753 | |
a40ed0f3 | 754 | mask = saved = 0; |
a4242737 KH |
755 | |
756 | /* Interrupt thread does not need to save any register. */ | |
757 | if (!interrupt_thread) | |
758 | for (regno = 0; regno < 16; regno++) | |
759 | if (m68k_save_reg (regno, interrupt_handler)) | |
760 | { | |
761 | mask |= 1 << (regno - D0_REG); | |
762 | saved++; | |
763 | } | |
3d74bc09 BI |
764 | current_frame.offset = saved * 4; |
765 | current_frame.reg_no = saved; | |
766 | current_frame.reg_mask = mask; | |
860c4900 | 767 | |
57047680 | 768 | current_frame.foffset = 0; |
a40ed0f3 | 769 | mask = saved = 0; |
dcc21c4c | 770 | if (TARGET_HARD_FLOAT) |
860c4900 | 771 | { |
a4242737 KH |
772 | /* Interrupt thread does not need to save any register. */ |
773 | if (!interrupt_thread) | |
774 | for (regno = 16; regno < 24; regno++) | |
775 | if (m68k_save_reg (regno, interrupt_handler)) | |
776 | { | |
777 | mask |= 1 << (regno - FP0_REG); | |
778 | saved++; | |
779 | } | |
dcc21c4c | 780 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 781 | current_frame.offset += current_frame.foffset; |
860c4900 | 782 | } |
57047680 GN |
783 | current_frame.fpu_no = saved; |
784 | current_frame.fpu_mask = mask; | |
3d74bc09 BI |
785 | |
786 | /* Remember what function this frame refers to. */ | |
787 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
788 | } |
789 | ||
7b5cbb57 AS |
790 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
791 | ||
792 | bool | |
793 | m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
794 | { | |
795 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
796 | } | |
797 | ||
860c4900 BI |
798 | HOST_WIDE_INT |
799 | m68k_initial_elimination_offset (int from, int to) | |
800 | { | |
42b67c06 PB |
801 | int argptr_offset; |
802 | /* The arg pointer points 8 bytes before the start of the arguments, | |
803 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
804 | frame pointer in most frames. */ | |
805 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 806 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 807 | return argptr_offset; |
860c4900 | 808 | |
3d74bc09 | 809 | m68k_compute_frame_layout (); |
860c4900 | 810 | |
4761e388 NS |
811 | gcc_assert (to == STACK_POINTER_REGNUM); |
812 | switch (from) | |
813 | { | |
a0a7fbc9 | 814 | case ARG_POINTER_REGNUM: |
42b67c06 | 815 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
816 | case FRAME_POINTER_REGNUM: |
817 | return current_frame.offset + current_frame.size; | |
818 | default: | |
819 | gcc_unreachable (); | |
820 | } | |
860c4900 BI |
821 | } |
822 | ||
97c55091 GN |
823 | /* Refer to the array `regs_ever_live' to determine which registers |
824 | to save; `regs_ever_live[I]' is nonzero if register number I | |
825 | is ever used in the function. This function is responsible for | |
826 | knowing which registers should not be saved even if used. | |
827 | Return true if we need to save REGNO. */ | |
828 | ||
48ed72a4 PB |
829 | static bool |
830 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 831 | { |
4ab870f5 | 832 | if (flag_pic && regno == PIC_REG) |
b86ba8a3 | 833 | { |
e3b5732b | 834 | if (crtl->saves_all_registers) |
afcb440c | 835 | return true; |
e3b5732b | 836 | if (crtl->uses_pic_offset_table) |
b86ba8a3 | 837 | return true; |
6357eb0d RS |
838 | /* Reload may introduce constant pool references into a function |
839 | that thitherto didn't need a PIC register. Note that the test | |
840 | above will not catch that case because we will only set | |
e3b5732b | 841 | crtl->uses_pic_offset_table when emitting |
6357eb0d | 842 | the address reloads. */ |
e3b5732b | 843 | if (crtl->uses_const_pool) |
6357eb0d | 844 | return true; |
b86ba8a3 | 845 | } |
2cff4a6e | 846 | |
e3b5732b | 847 | if (crtl->calls_eh_return) |
2cff4a6e AS |
848 | { |
849 | unsigned int i; | |
850 | for (i = 0; ; i++) | |
851 | { | |
852 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
853 | if (test == INVALID_REGNUM) | |
854 | break; | |
855 | if (test == regno) | |
48ed72a4 | 856 | return true; |
2cff4a6e AS |
857 | } |
858 | } | |
859 | ||
48ed72a4 PB |
860 | /* Fixed regs we never touch. */ |
861 | if (fixed_regs[regno]) | |
862 | return false; | |
863 | ||
864 | /* The frame pointer (if it is such) is handled specially. */ | |
865 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
866 | return false; | |
867 | ||
868 | /* Interrupt handlers must also save call_used_regs | |
869 | if they are live or when calling nested functions. */ | |
870 | if (interrupt_handler) | |
a0a7fbc9 | 871 | { |
6fb5fa3c | 872 | if (df_regs_ever_live_p (regno)) |
a0a7fbc9 | 873 | return true; |
48ed72a4 | 874 | |
a0a7fbc9 AS |
875 | if (!current_function_is_leaf && call_used_regs[regno]) |
876 | return true; | |
877 | } | |
48ed72a4 PB |
878 | |
879 | /* Never need to save registers that aren't touched. */ | |
6fb5fa3c | 880 | if (!df_regs_ever_live_p (regno)) |
48ed72a4 PB |
881 | return false; |
882 | ||
b2e08ed4 | 883 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 884 | return !call_used_regs[regno]; |
2cff4a6e AS |
885 | } |
886 | ||
a40ed0f3 KH |
887 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
888 | the lowest memory address. COUNT is the number of registers to be | |
889 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
890 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
891 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
892 | (if !STORE_P) operation. */ | |
893 | ||
894 | static rtx | |
895 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, | |
896 | unsigned int count, unsigned int regno, | |
897 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
898 | { | |
899 | int i; | |
900 | rtx body, addr, src, operands[2]; | |
901 | enum machine_mode mode; | |
902 | ||
903 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
904 | mode = reg_raw_mode[regno]; | |
905 | i = 0; | |
906 | ||
907 | if (adjust_stack_p) | |
908 | { | |
909 | src = plus_constant (base, (count | |
910 | * GET_MODE_SIZE (mode) | |
911 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
912 | XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src); | |
913 | } | |
914 | ||
915 | for (; mask != 0; mask >>= 1, regno++) | |
916 | if (mask & 1) | |
917 | { | |
918 | addr = plus_constant (base, offset); | |
919 | operands[!store_p] = gen_frame_mem (mode, addr); | |
920 | operands[store_p] = gen_rtx_REG (mode, regno); | |
921 | XVECEXP (body, 0, i++) | |
922 | = gen_rtx_SET (VOIDmode, operands[0], operands[1]); | |
923 | offset += GET_MODE_SIZE (mode); | |
924 | } | |
925 | gcc_assert (i == XVECLEN (body, 0)); | |
926 | ||
927 | return emit_insn (body); | |
928 | } | |
929 | ||
930 | /* Make INSN a frame-related instruction. */ | |
79e68feb | 931 | |
08c148a8 | 932 | static void |
a40ed0f3 KH |
933 | m68k_set_frame_related (rtx insn) |
934 | { | |
935 | rtx body; | |
936 | int i; | |
937 | ||
938 | RTX_FRAME_RELATED_P (insn) = 1; | |
939 | body = PATTERN (insn); | |
940 | if (GET_CODE (body) == PARALLEL) | |
941 | for (i = 0; i < XVECLEN (body, 0); i++) | |
942 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
943 | } | |
944 | ||
945 | /* Emit RTL for the "prologue" define_expand. */ | |
946 | ||
947 | void | |
948 | m68k_expand_prologue (void) | |
79e68feb | 949 | { |
860c4900 | 950 | HOST_WIDE_INT fsize_with_regs; |
2dc8bd76 | 951 | rtx limit, src, dest; |
3d74bc09 | 952 | |
a40ed0f3 | 953 | m68k_compute_frame_layout (); |
3d74bc09 | 954 | |
a11e0df4 | 955 | if (flag_stack_usage_info) |
f69ea688 AS |
956 | current_function_static_stack_size |
957 | = current_frame.size + current_frame.offset; | |
958 | ||
a157febd GK |
959 | /* If the stack limit is a symbol, we can check it here, |
960 | before actually allocating the space. */ | |
e3b5732b | 961 | if (crtl->limit_stack |
a157febd | 962 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) |
a40ed0f3 KH |
963 | { |
964 | limit = plus_constant (stack_limit_rtx, current_frame.size + 4); | |
1a627b35 | 965 | if (!m68k_legitimate_constant_p (Pmode, limit)) |
a40ed0f3 KH |
966 | { |
967 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
968 | limit = gen_rtx_REG (Pmode, D0_REG); | |
969 | } | |
f90b7a5a PB |
970 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, |
971 | stack_pointer_rtx, limit), | |
972 | stack_pointer_rtx, limit, | |
973 | const1_rtx)); | |
a40ed0f3 | 974 | } |
79e68feb | 975 | |
a89e3f21 | 976 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
977 | if (TARGET_COLDFIRE) |
978 | { | |
a40ed0f3 KH |
979 | /* ColdFire's move multiple instructions do not allow pre-decrement |
980 | addressing. Add the size of movem saves to the initial stack | |
981 | allocation instead. */ | |
982 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
983 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
984 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
985 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 986 | } |
860c4900 | 987 | |
79e68feb RS |
988 | if (frame_pointer_needed) |
989 | { | |
a40ed0f3 | 990 | if (fsize_with_regs == 0 && TUNE_68040) |
79e68feb | 991 | { |
a40ed0f3 KH |
992 | /* On the 68040, two separate moves are faster than link.w 0. */ |
993 | dest = gen_frame_mem (Pmode, | |
994 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
995 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
996 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
997 | stack_pointer_rtx)); | |
79e68feb | 998 | } |
a40ed0f3 KH |
999 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
1000 | m68k_set_frame_related | |
1001 | (emit_insn (gen_link (frame_pointer_rtx, | |
1002 | GEN_INT (-4 - fsize_with_regs)))); | |
d9e88af0 | 1003 | else |
a40ed0f3 KH |
1004 | { |
1005 | m68k_set_frame_related | |
1006 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
1007 | m68k_set_frame_related | |
1008 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1009 | stack_pointer_rtx, | |
1010 | GEN_INT (-fsize_with_regs)))); | |
1011 | } | |
96fcacb7 MK |
1012 | |
1013 | /* If the frame pointer is needed, emit a special barrier that | |
1014 | will prevent the scheduler from moving stores to the frame | |
1015 | before the stack adjustment. */ | |
1016 | emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx)); | |
d9e88af0 | 1017 | } |
a40ed0f3 KH |
1018 | else if (fsize_with_regs != 0) |
1019 | m68k_set_frame_related | |
1020 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1021 | stack_pointer_rtx, | |
1022 | GEN_INT (-fsize_with_regs)))); | |
860c4900 | 1023 | |
57047680 | 1024 | if (current_frame.fpu_mask) |
79e68feb | 1025 | { |
a40ed0f3 | 1026 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
dcc21c4c | 1027 | if (TARGET_68881) |
a40ed0f3 KH |
1028 | m68k_set_frame_related |
1029 | (m68k_emit_movem (stack_pointer_rtx, | |
1030 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
1031 | current_frame.fpu_no, FP0_REG, | |
1032 | current_frame.fpu_mask, true, true)); | |
dcc21c4c PB |
1033 | else |
1034 | { | |
1035 | int offset; | |
1036 | ||
a40ed0f3 KH |
1037 | /* If we're using moveml to save the integer registers, |
1038 | the stack pointer will point to the bottom of the moveml | |
1039 | save area. Find the stack offset of the first FP register. */ | |
1040 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1041 | offset = 0; |
1042 | else | |
a40ed0f3 KH |
1043 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1044 | m68k_set_frame_related | |
1045 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
1046 | current_frame.fpu_no, FP0_REG, | |
1047 | current_frame.fpu_mask, true, false)); | |
f277471f | 1048 | } |
79e68feb | 1049 | } |
99df2465 | 1050 | |
01bbf777 | 1051 | /* If the stack limit is not a symbol, check it here. |
a157febd | 1052 | This has the disadvantage that it may be too late... */ |
e3b5732b | 1053 | if (crtl->limit_stack) |
a157febd GK |
1054 | { |
1055 | if (REG_P (stack_limit_rtx)) | |
f90b7a5a PB |
1056 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx, |
1057 | stack_limit_rtx), | |
1058 | stack_pointer_rtx, stack_limit_rtx, | |
1059 | const1_rtx)); | |
1060 | ||
a157febd | 1061 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 1062 | warning (0, "stack limit expression is not supported"); |
a157febd | 1063 | } |
01bbf777 | 1064 | |
a40ed0f3 | 1065 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
79e68feb | 1066 | { |
a40ed0f3 | 1067 | /* Store each register separately in the same order moveml does. */ |
79e68feb RS |
1068 | int i; |
1069 | ||
a40ed0f3 KH |
1070 | for (i = 16; i-- > 0; ) |
1071 | if (current_frame.reg_mask & (1 << i)) | |
078e983e | 1072 | { |
a40ed0f3 KH |
1073 | src = gen_rtx_REG (SImode, D0_REG + i); |
1074 | dest = gen_frame_mem (SImode, | |
1075 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1076 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
078e983e | 1077 | } |
79e68feb | 1078 | } |
a40ed0f3 | 1079 | else |
79e68feb | 1080 | { |
9425fb04 | 1081 | if (TARGET_COLDFIRE) |
a40ed0f3 KH |
1082 | /* The required register save space has already been allocated. |
1083 | The first register should be stored at (%sp). */ | |
1084 | m68k_set_frame_related | |
1085 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
1086 | current_frame.reg_no, D0_REG, | |
1087 | current_frame.reg_mask, true, false)); | |
afaff477 | 1088 | else |
a40ed0f3 KH |
1089 | m68k_set_frame_related |
1090 | (m68k_emit_movem (stack_pointer_rtx, | |
1091 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1092 | current_frame.reg_no, D0_REG, | |
1093 | current_frame.reg_mask, true, true)); | |
79e68feb | 1094 | } |
a40ed0f3 | 1095 | |
75df395f | 1096 | if (!TARGET_SEP_DATA |
e3b5732b | 1097 | && crtl->uses_pic_offset_table) |
2dc8bd76 | 1098 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
79e68feb RS |
1099 | } |
1100 | \f | |
413ac1b2 RS |
1101 | /* Return true if a simple (return) instruction is sufficient for this |
1102 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1103 | |
3d74bc09 | 1104 | bool |
a2bda628 | 1105 | m68k_use_return_insn (void) |
79e68feb | 1106 | { |
79e68feb | 1107 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1108 | return false; |
125ed86f | 1109 | |
a0a7fbc9 | 1110 | m68k_compute_frame_layout (); |
413ac1b2 | 1111 | return current_frame.offset == 0; |
79e68feb RS |
1112 | } |
1113 | ||
f7e70894 RS |
1114 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1115 | SIBCALL_P says which. | |
79e68feb RS |
1116 | |
1117 | The function epilogue should not depend on the current stack pointer! | |
1118 | It should use the frame pointer only, if there is a frame pointer. | |
1119 | This is mandatory because of alloca; we also take advantage of it to | |
1120 | omit stack adjustments before returning. */ | |
1121 | ||
a40ed0f3 | 1122 | void |
f7e70894 | 1123 | m68k_expand_epilogue (bool sibcall_p) |
08c148a8 | 1124 | { |
3d74bc09 | 1125 | HOST_WIDE_INT fsize, fsize_with_regs; |
a40ed0f3 | 1126 | bool big, restore_from_sp; |
3d74bc09 | 1127 | |
a0a7fbc9 | 1128 | m68k_compute_frame_layout (); |
3d74bc09 | 1129 | |
3d74bc09 | 1130 | fsize = current_frame.size; |
a40ed0f3 KH |
1131 | big = false; |
1132 | restore_from_sp = false; | |
3d74bc09 | 1133 | |
a40ed0f3 | 1134 | /* FIXME : current_function_is_leaf below is too strong. |
c67ddce5 | 1135 | What we really need to know there is if there could be pending |
7a1929e1 | 1136 | stack adjustment needed at that point. */ |
a40ed0f3 | 1137 | restore_from_sp = (!frame_pointer_needed |
e3b5732b | 1138 | || (!cfun->calls_alloca |
a40ed0f3 | 1139 | && current_function_is_leaf)); |
860c4900 BI |
1140 | |
1141 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1142 | popping the frame. */ |
860c4900 | 1143 | fsize_with_regs = fsize; |
dcc21c4c PB |
1144 | if (TARGET_COLDFIRE && restore_from_sp) |
1145 | { | |
a40ed0f3 KH |
1146 | /* ColdFire's move multiple instructions do not allow post-increment |
1147 | addressing. Add the size of movem loads to the final deallocation | |
1148 | instead. */ | |
1149 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1150 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1151 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1152 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1153 | } |
860c4900 | 1154 | |
3d74bc09 | 1155 | if (current_frame.offset + fsize >= 0x8000 |
a40ed0f3 | 1156 | && !restore_from_sp |
3d74bc09 | 1157 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1158 | { |
a40ed0f3 KH |
1159 | if (TARGET_COLDFIRE |
1160 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1161 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1162 | { | |
1163 | /* ColdFire's move multiple instructions do not support the | |
1164 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1165 | stack-based restore. */ | |
1166 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1167 | GEN_INT (-(current_frame.offset + fsize))); | |
1168 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1169 | gen_rtx_REG (Pmode, A1_REG), | |
1170 | frame_pointer_rtx)); | |
1171 | restore_from_sp = true; | |
1172 | } | |
1173 | else | |
1174 | { | |
1175 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1176 | fsize = 0; | |
1177 | big = true; | |
1178 | } | |
79e68feb | 1179 | } |
79e68feb | 1180 | |
a40ed0f3 KH |
1181 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1182 | { | |
1183 | /* Restore each register separately in the same order moveml does. */ | |
79e68feb | 1184 | int i; |
a40ed0f3 | 1185 | HOST_WIDE_INT offset; |
79e68feb | 1186 | |
a40ed0f3 | 1187 | offset = current_frame.offset + fsize; |
3d74bc09 BI |
1188 | for (i = 0; i < 16; i++) |
1189 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb | 1190 | { |
a40ed0f3 KH |
1191 | rtx addr; |
1192 | ||
1193 | if (big) | |
79e68feb | 1194 | { |
a40ed0f3 KH |
1195 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1196 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1197 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
1198 | addr = plus_constant (addr, -offset); | |
79e68feb | 1199 | } |
a40ed0f3 KH |
1200 | else if (restore_from_sp) |
1201 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1202 | else | |
1203 | addr = plus_constant (frame_pointer_rtx, -offset); | |
1204 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), | |
1205 | gen_frame_mem (SImode, addr)); | |
1206 | offset -= GET_MODE_SIZE (SImode); | |
1207 | } | |
79e68feb | 1208 | } |
3d74bc09 | 1209 | else if (current_frame.reg_mask) |
79e68feb | 1210 | { |
a40ed0f3 KH |
1211 | if (big) |
1212 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1213 | gen_rtx_REG (Pmode, A1_REG), | |
1214 | frame_pointer_rtx), | |
1215 | -(current_frame.offset + fsize), | |
1216 | current_frame.reg_no, D0_REG, | |
1217 | current_frame.reg_mask, false, false); | |
1218 | else if (restore_from_sp) | |
1219 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1220 | current_frame.reg_no, D0_REG, | |
1221 | current_frame.reg_mask, false, | |
1222 | !TARGET_COLDFIRE); | |
1223 | else | |
1224 | m68k_emit_movem (frame_pointer_rtx, | |
1225 | -(current_frame.offset + fsize), | |
1226 | current_frame.reg_no, D0_REG, | |
1227 | current_frame.reg_mask, false, false); | |
79e68feb | 1228 | } |
a40ed0f3 KH |
1229 | |
1230 | if (current_frame.fpu_no > 0) | |
79e68feb RS |
1231 | { |
1232 | if (big) | |
a40ed0f3 KH |
1233 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1234 | gen_rtx_REG (Pmode, A1_REG), | |
1235 | frame_pointer_rtx), | |
1236 | -(current_frame.foffset + fsize), | |
1237 | current_frame.fpu_no, FP0_REG, | |
1238 | current_frame.fpu_mask, false, false); | |
6910dd70 | 1239 | else if (restore_from_sp) |
79e68feb | 1240 | { |
dcc21c4c PB |
1241 | if (TARGET_COLDFIRE) |
1242 | { | |
1243 | int offset; | |
1244 | ||
a40ed0f3 KH |
1245 | /* If we used moveml to restore the integer registers, the |
1246 | stack pointer will still point to the bottom of the moveml | |
1247 | save area. Find the stack offset of the first FP | |
1248 | register. */ | |
1249 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1250 | offset = 0; |
1251 | else | |
a40ed0f3 KH |
1252 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1253 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1254 | current_frame.fpu_no, FP0_REG, | |
1255 | current_frame.fpu_mask, false, false); | |
dcc21c4c | 1256 | } |
884b74f0 | 1257 | else |
a40ed0f3 KH |
1258 | m68k_emit_movem (stack_pointer_rtx, 0, |
1259 | current_frame.fpu_no, FP0_REG, | |
1260 | current_frame.fpu_mask, false, true); | |
79e68feb RS |
1261 | } |
1262 | else | |
a40ed0f3 KH |
1263 | m68k_emit_movem (frame_pointer_rtx, |
1264 | -(current_frame.foffset + fsize), | |
1265 | current_frame.fpu_no, FP0_REG, | |
1266 | current_frame.fpu_mask, false, false); | |
79e68feb | 1267 | } |
a40ed0f3 | 1268 | |
79e68feb | 1269 | if (frame_pointer_needed) |
a40ed0f3 | 1270 | emit_insn (gen_unlink (frame_pointer_rtx)); |
860c4900 | 1271 | else if (fsize_with_regs) |
a40ed0f3 KH |
1272 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1273 | stack_pointer_rtx, | |
1274 | GEN_INT (fsize_with_regs))); | |
1275 | ||
e3b5732b | 1276 | if (crtl->calls_eh_return) |
a40ed0f3 KH |
1277 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1278 | stack_pointer_rtx, | |
1279 | EH_RETURN_STACKADJ_RTX)); | |
1280 | ||
f7e70894 | 1281 | if (!sibcall_p) |
3810076b | 1282 | emit_jump_insn (ret_rtx); |
79e68feb RS |
1283 | } |
1284 | \f | |
8a4a2253 | 1285 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1286 | instruction. |
1287 | ||
1288 | Note it rejects floating point comparison operators. | |
1289 | (In the future we could use Fdbcc). | |
1290 | ||
1291 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1292 | ||
1293 | int | |
41b6a5e2 | 1294 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1295 | { |
64a184e9 RS |
1296 | switch (GET_CODE (x)) |
1297 | { | |
64a184e9 RS |
1298 | case EQ: case NE: case GTU: case LTU: |
1299 | case GEU: case LEU: | |
1300 | return 1; | |
1301 | ||
1302 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1303 | conservative */ | |
1304 | case GT: case LT: case GE: case LE: | |
1305 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1306 | default: | |
1307 | return 0; | |
1308 | } | |
1309 | } | |
1310 | ||
a0ab749a | 1311 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1312 | int |
8a4a2253 | 1313 | flags_in_68881 (void) |
6a0f85e3 TG |
1314 | { |
1315 | /* We could add support for these in the future */ | |
1316 | return cc_status.flags & CC_IN_68881; | |
1317 | } | |
1318 | ||
db5e2d51 MK |
1319 | /* Return true if PARALLEL contains register REGNO. */ |
1320 | static bool | |
1321 | m68k_reg_present_p (const_rtx parallel, unsigned int regno) | |
1322 | { | |
1323 | int i; | |
1324 | ||
1325 | if (REG_P (parallel) && REGNO (parallel) == regno) | |
1326 | return true; | |
1327 | ||
1328 | if (GET_CODE (parallel) != PARALLEL) | |
1329 | return false; | |
1330 | ||
1331 | for (i = 0; i < XVECLEN (parallel, 0); ++i) | |
1332 | { | |
1333 | const_rtx x; | |
1334 | ||
1335 | x = XEXP (XVECEXP (parallel, 0, i), 0); | |
1336 | if (REG_P (x) && REGNO (x) == regno) | |
1337 | return true; | |
1338 | } | |
1339 | ||
1340 | return false; | |
1341 | } | |
1342 | ||
fa157b28 | 1343 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ |
f7e70894 RS |
1344 | |
1345 | static bool | |
fa157b28 | 1346 | m68k_ok_for_sibcall_p (tree decl, tree exp) |
f7e70894 | 1347 | { |
fa157b28 NS |
1348 | enum m68k_function_kind kind; |
1349 | ||
1350 | /* We cannot use sibcalls for nested functions because we use the | |
1351 | static chain register for indirect calls. */ | |
1352 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1353 | return false; | |
1354 | ||
db5e2d51 MK |
1355 | if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) |
1356 | { | |
1357 | /* Check that the return value locations are the same. For | |
1358 | example that we aren't returning a value from the sibling in | |
1359 | a D0 register but then need to transfer it to a A0 register. */ | |
1360 | rtx cfun_value; | |
1361 | rtx call_value; | |
1362 | ||
1363 | cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)), | |
1364 | cfun->decl); | |
1365 | call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl); | |
1366 | ||
1367 | /* Check that the values are equal or that the result the callee | |
1368 | function returns is superset of what the current function returns. */ | |
1369 | if (!(rtx_equal_p (cfun_value, call_value) | |
1370 | || (REG_P (cfun_value) | |
1371 | && m68k_reg_present_p (call_value, REGNO (cfun_value))))) | |
1372 | return false; | |
1373 | } | |
1374 | ||
fa157b28 NS |
1375 | kind = m68k_get_function_kind (current_function_decl); |
1376 | if (kind == m68k_fk_normal_function) | |
1377 | /* We can always sibcall from a normal function, because it's | |
1378 | undefined if it is calling an interrupt function. */ | |
1379 | return true; | |
1380 | ||
1381 | /* Otherwise we can only sibcall if the function kind is known to be | |
1382 | the same. */ | |
1383 | if (decl && m68k_get_function_kind (decl) == kind) | |
1384 | return true; | |
1385 | ||
1386 | return false; | |
f7e70894 RS |
1387 | } |
1388 | ||
13d3961c NF |
1389 | /* On the m68k all args are always pushed. */ |
1390 | ||
1391 | static rtx | |
d5cc9181 | 1392 | m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, |
13d3961c NF |
1393 | enum machine_mode mode ATTRIBUTE_UNUSED, |
1394 | const_tree type ATTRIBUTE_UNUSED, | |
1395 | bool named ATTRIBUTE_UNUSED) | |
1396 | { | |
1397 | return NULL_RTX; | |
1398 | } | |
1399 | ||
1400 | static void | |
d5cc9181 | 1401 | m68k_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
13d3961c NF |
1402 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1403 | { | |
d5cc9181 JR |
1404 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1405 | ||
13d3961c NF |
1406 | *cum += (mode != BLKmode |
1407 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1408 | : (int_size_in_bytes (type) + 3) & ~3); | |
1409 | } | |
1410 | ||
29ca003a RS |
1411 | /* Convert X to a legitimate function call memory reference and return the |
1412 | result. */ | |
a2ef3db7 | 1413 | |
29ca003a RS |
1414 | rtx |
1415 | m68k_legitimize_call_address (rtx x) | |
1416 | { | |
1417 | gcc_assert (MEM_P (x)); | |
1418 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1419 | return x; | |
1420 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1421 | } |
1422 | ||
f7e70894 RS |
1423 | /* Likewise for sibling calls. */ |
1424 | ||
1425 | rtx | |
1426 | m68k_legitimize_sibcall_address (rtx x) | |
1427 | { | |
1428 | gcc_assert (MEM_P (x)); | |
1429 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1430 | return x; | |
1431 | ||
1432 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1433 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1434 | } | |
1435 | ||
506d7b68 PB |
1436 | /* Convert X to a legitimate address and return it if successful. Otherwise |
1437 | return X. | |
1438 | ||
1439 | For the 68000, we handle X+REG by loading X into a register R and | |
1440 | using R+REG. R will go in an address reg and indexing will be used. | |
1441 | However, if REG is a broken-out memory address or multiplication, | |
1442 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1443 | ||
ab7256e4 | 1444 | static rtx |
506d7b68 PB |
1445 | m68k_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) |
1446 | { | |
75df395f MK |
1447 | if (m68k_tls_symbol_p (x)) |
1448 | return m68k_legitimize_tls_address (x); | |
1449 | ||
506d7b68 PB |
1450 | if (GET_CODE (x) == PLUS) |
1451 | { | |
1452 | int ch = (x) != (oldx); | |
1453 | int copied = 0; | |
1454 | ||
1455 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1456 | ||
1457 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
1458 | { | |
1459 | COPY_ONCE (x); | |
1460 | XEXP (x, 0) = force_operand (XEXP (x, 0), 0); | |
1461 | } | |
1462 | if (GET_CODE (XEXP (x, 1)) == MULT) | |
1463 | { | |
1464 | COPY_ONCE (x); | |
1465 | XEXP (x, 1) = force_operand (XEXP (x, 1), 0); | |
1466 | } | |
1467 | if (ch) | |
1468 | { | |
1469 | if (GET_CODE (XEXP (x, 1)) == REG | |
1470 | && GET_CODE (XEXP (x, 0)) == REG) | |
1471 | { | |
1472 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1473 | { | |
1474 | COPY_ONCE (x); | |
1475 | x = force_operand (x, 0); | |
1476 | } | |
1477 | return x; | |
1478 | } | |
1479 | if (memory_address_p (mode, x)) | |
1480 | return x; | |
1481 | } | |
1482 | if (GET_CODE (XEXP (x, 0)) == REG | |
1483 | || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
1484 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1485 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)) | |
1486 | { | |
1487 | rtx temp = gen_reg_rtx (Pmode); | |
1488 | rtx val = force_operand (XEXP (x, 1), 0); | |
1489 | emit_move_insn (temp, val); | |
1490 | COPY_ONCE (x); | |
1491 | XEXP (x, 1) = temp; | |
1492 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1493 | && GET_CODE (XEXP (x, 0)) == REG) | |
1494 | x = force_operand (x, 0); | |
1495 | } | |
1496 | else if (GET_CODE (XEXP (x, 1)) == REG | |
1497 | || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND | |
1498 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
1499 | && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode)) | |
1500 | { | |
1501 | rtx temp = gen_reg_rtx (Pmode); | |
1502 | rtx val = force_operand (XEXP (x, 0), 0); | |
1503 | emit_move_insn (temp, val); | |
1504 | COPY_ONCE (x); | |
1505 | XEXP (x, 0) = temp; | |
1506 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1507 | && GET_CODE (XEXP (x, 1)) == REG) | |
1508 | x = force_operand (x, 0); | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | return x; | |
1513 | } | |
1514 | ||
1515 | ||
64a184e9 RS |
1516 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1517 | floating point version of this sequence (Fdbcc). We also | |
1518 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1519 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1520 | kick those out before we get here. */ | |
64a184e9 | 1521 | |
1d8eaa6b | 1522 | void |
8a4a2253 | 1523 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1524 | { |
64a184e9 RS |
1525 | switch (GET_CODE (operands[3])) |
1526 | { | |
1527 | case EQ: | |
da398bb5 | 1528 | output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); |
e6d98cb0 | 1529 | break; |
64a184e9 RS |
1530 | |
1531 | case NE: | |
da398bb5 | 1532 | output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); |
e6d98cb0 | 1533 | break; |
64a184e9 RS |
1534 | |
1535 | case GT: | |
da398bb5 | 1536 | output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); |
e6d98cb0 | 1537 | break; |
64a184e9 RS |
1538 | |
1539 | case GTU: | |
da398bb5 | 1540 | output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); |
e6d98cb0 | 1541 | break; |
64a184e9 RS |
1542 | |
1543 | case LT: | |
da398bb5 | 1544 | output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); |
e6d98cb0 | 1545 | break; |
64a184e9 RS |
1546 | |
1547 | case LTU: | |
da398bb5 | 1548 | output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); |
e6d98cb0 | 1549 | break; |
64a184e9 RS |
1550 | |
1551 | case GE: | |
da398bb5 | 1552 | output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); |
e6d98cb0 | 1553 | break; |
64a184e9 RS |
1554 | |
1555 | case GEU: | |
da398bb5 | 1556 | output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); |
e6d98cb0 | 1557 | break; |
64a184e9 RS |
1558 | |
1559 | case LE: | |
da398bb5 | 1560 | output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); |
e6d98cb0 | 1561 | break; |
64a184e9 RS |
1562 | |
1563 | case LEU: | |
da398bb5 | 1564 | output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); |
e6d98cb0 | 1565 | break; |
64a184e9 RS |
1566 | |
1567 | default: | |
4761e388 | 1568 | gcc_unreachable (); |
64a184e9 RS |
1569 | } |
1570 | ||
1571 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1572 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1573 | switch (GET_MODE (operands[0])) |
1574 | { | |
1575 | case SImode: | |
da398bb5 | 1576 | output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands); |
64a184e9 RS |
1577 | break; |
1578 | ||
1579 | case HImode: | |
1580 | break; | |
1581 | ||
1582 | default: | |
4761e388 | 1583 | gcc_unreachable (); |
64a184e9 RS |
1584 | } |
1585 | } | |
1586 | ||
5505f548 | 1587 | const char * |
4761e388 | 1588 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1589 | { |
1590 | rtx loperands[7]; | |
d9832fd2 | 1591 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1592 | |
f710504c | 1593 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1594 | CC_STATUS_INIT; |
1595 | ||
d9832fd2 RK |
1596 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1597 | below. Swap the operands and change the op if these requirements | |
1598 | are not fulfilled. */ | |
1599 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1600 | { | |
1601 | rtx tmp = operand1; | |
1602 | ||
1603 | operand1 = operand2; | |
1604 | operand2 = tmp; | |
1605 | op_code = swap_condition (op_code); | |
1606 | } | |
c59c3b1c RK |
1607 | loperands[0] = operand1; |
1608 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1609 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1610 | else |
b72f00af | 1611 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1612 | if (operand2 != const0_rtx) |
1613 | { | |
1614 | loperands[2] = operand2; | |
1615 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1616 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1617 | else |
b72f00af | 1618 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1619 | } |
428511bb | 1620 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1621 | if (operand2 != const0_rtx) |
da398bb5 | 1622 | output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands); |
392582fa | 1623 | else |
4a8c52e0 | 1624 | { |
9425fb04 | 1625 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1626 | output_asm_insn ("tst%.l %0", loperands); |
1627 | else | |
a0a7fbc9 | 1628 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1629 | |
da398bb5 | 1630 | output_asm_insn ("jne %l4", loperands); |
4a8c52e0 | 1631 | |
9425fb04 | 1632 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1633 | output_asm_insn ("tst%.l %1", loperands); |
1634 | else | |
3b4b85c9 | 1635 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1636 | } |
1637 | ||
c59c3b1c | 1638 | loperands[5] = dest; |
3b4b85c9 | 1639 | |
d9832fd2 | 1640 | switch (op_code) |
c59c3b1c RK |
1641 | { |
1642 | case EQ: | |
4977bab6 | 1643 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1644 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1645 | output_asm_insn ("seq %5", loperands); |
1646 | break; | |
1647 | ||
1648 | case NE: | |
4977bab6 | 1649 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1650 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1651 | output_asm_insn ("sne %5", loperands); |
1652 | break; | |
1653 | ||
1654 | case GT: | |
428511bb | 1655 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1656 | output_asm_insn ("shi %5\n\tjra %l6", loperands); |
4977bab6 | 1657 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1658 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1659 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1660 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1661 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1662 | break; |
1663 | ||
1664 | case GTU: | |
4977bab6 | 1665 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1666 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1667 | output_asm_insn ("shi %5", loperands); |
1668 | break; | |
1669 | ||
1670 | case LT: | |
428511bb | 1671 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1672 | output_asm_insn ("scs %5\n\tjra %l6", loperands); |
4977bab6 | 1673 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1674 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1675 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1676 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1677 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1678 | break; |
1679 | ||
1680 | case LTU: | |
4977bab6 | 1681 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1682 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1683 | output_asm_insn ("scs %5", loperands); |
1684 | break; | |
1685 | ||
1686 | case GE: | |
428511bb | 1687 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1688 | output_asm_insn ("scc %5\n\tjra %l6", loperands); |
4977bab6 | 1689 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1690 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1691 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1692 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1693 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1694 | break; |
1695 | ||
1696 | case GEU: | |
4977bab6 | 1697 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1698 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1699 | output_asm_insn ("scc %5", loperands); |
1700 | break; | |
1701 | ||
1702 | case LE: | |
428511bb | 1703 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1704 | output_asm_insn ("sls %5\n\tjra %l6", loperands); |
4977bab6 | 1705 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1706 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1707 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1708 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1709 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1710 | break; |
1711 | ||
1712 | case LEU: | |
4977bab6 | 1713 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1714 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1715 | output_asm_insn ("sls %5", loperands); |
1716 | break; | |
1717 | ||
1718 | default: | |
4761e388 | 1719 | gcc_unreachable (); |
c59c3b1c RK |
1720 | } |
1721 | return ""; | |
1722 | } | |
1723 | ||
5505f548 | 1724 | const char * |
8a4a2253 | 1725 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1726 | { |
1727 | operands[0] = countop; | |
1728 | operands[1] = dataop; | |
1729 | ||
1730 | if (GET_CODE (countop) == CONST_INT) | |
1731 | { | |
1732 | register int count = INTVAL (countop); | |
1733 | /* If COUNT is bigger than size of storage unit in use, | |
1734 | advance to the containing unit of same size. */ | |
1735 | if (count > signpos) | |
1736 | { | |
1737 | int offset = (count & ~signpos) / 8; | |
1738 | count = count & signpos; | |
b72f00af | 1739 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1740 | } |
1741 | if (count == signpos) | |
1742 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1743 | else | |
1744 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1745 | ||
1746 | /* These three statements used to use next_insns_test_no... | |
1747 | but it appears that this should do the same job. */ | |
1748 | if (count == 31 | |
1749 | && next_insn_tests_no_inequality (insn)) | |
1750 | return "tst%.l %1"; | |
1751 | if (count == 15 | |
1752 | && next_insn_tests_no_inequality (insn)) | |
1753 | return "tst%.w %1"; | |
1754 | if (count == 7 | |
1755 | && next_insn_tests_no_inequality (insn)) | |
1756 | return "tst%.b %1"; | |
5083912d PDM |
1757 | /* Try to use `movew to ccr' followed by the appropriate branch insn. |
1758 | On some m68k variants unfortunately that's slower than btst. | |
1759 | On 68000 and higher, that should also work for all HImode operands. */ | |
1760 | if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) | |
1761 | { | |
1762 | if (count == 3 && DATA_REG_P (operands[1]) | |
1763 | && next_insn_tests_no_inequality (insn)) | |
1764 | { | |
1765 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW; | |
1766 | return "move%.w %1,%%ccr"; | |
1767 | } | |
1768 | if (count == 2 && DATA_REG_P (operands[1]) | |
1769 | && next_insn_tests_no_inequality (insn)) | |
1770 | { | |
1771 | cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW; | |
1772 | return "move%.w %1,%%ccr"; | |
1773 | } | |
1774 | /* count == 1 followed by bvc/bvs and | |
1775 | count == 0 followed by bcc/bcs are also possible, but need | |
1776 | m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ | |
1777 | } | |
79e68feb RS |
1778 | |
1779 | cc_status.flags = CC_NOT_NEGATIVE; | |
1780 | } | |
1781 | return "btst %0,%1"; | |
1782 | } | |
79e68feb | 1783 | \f |
fc2241eb RS |
1784 | /* Return true if X is a legitimate base register. STRICT_P says |
1785 | whether we need strict checking. */ | |
1786 | ||
1787 | bool | |
1788 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
1789 | { | |
1790 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
1791 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1792 | x = SUBREG_REG (x); | |
1793 | ||
1794 | return (REG_P (x) | |
1795 | && (strict_p | |
1796 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
bf32249e | 1797 | : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1798 | } |
1799 | ||
1800 | /* Return true if X is a legitimate index register. STRICT_P says | |
1801 | whether we need strict checking. */ | |
1802 | ||
1803 | bool | |
1804 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
1805 | { | |
1806 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1807 | x = SUBREG_REG (x); | |
1808 | ||
1809 | return (REG_P (x) | |
1810 | && (strict_p | |
1811 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
bf32249e | 1812 | : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1813 | } |
1814 | ||
1815 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
1816 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
1817 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
1818 | ||
1819 | static bool | |
1820 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
1821 | { | |
1822 | int scale; | |
1823 | ||
1824 | /* Check for a scale factor. */ | |
1825 | scale = 1; | |
1826 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
1827 | && GET_CODE (x) == MULT | |
1828 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1829 | && (INTVAL (XEXP (x, 1)) == 2 | |
1830 | || INTVAL (XEXP (x, 1)) == 4 | |
1831 | || (INTVAL (XEXP (x, 1)) == 8 | |
1832 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
1833 | { | |
1834 | scale = INTVAL (XEXP (x, 1)); | |
1835 | x = XEXP (x, 0); | |
1836 | } | |
1837 | ||
1838 | /* Check for a word extension. */ | |
1839 | if (!TARGET_COLDFIRE | |
1840 | && GET_CODE (x) == SIGN_EXTEND | |
1841 | && GET_MODE (XEXP (x, 0)) == HImode) | |
1842 | x = XEXP (x, 0); | |
1843 | ||
1844 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
1845 | { | |
1846 | address->scale = scale; | |
1847 | address->index = x; | |
1848 | return true; | |
1849 | } | |
1850 | ||
1851 | return false; | |
1852 | } | |
1853 | ||
7ffb5e78 RS |
1854 | /* Return true if X is an illegitimate symbolic constant. */ |
1855 | ||
1856 | bool | |
1857 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
1858 | { | |
1859 | rtx base, offset; | |
1860 | ||
1861 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1862 | { | |
1863 | split_const (x, &base, &offset); | |
1864 | if (GET_CODE (base) == SYMBOL_REF | |
1865 | && !offset_within_block_p (base, INTVAL (offset))) | |
1866 | return true; | |
1867 | } | |
75df395f | 1868 | return m68k_tls_reference_p (x, false); |
7ffb5e78 RS |
1869 | } |
1870 | ||
fbbf66e7 RS |
1871 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
1872 | ||
1873 | static bool | |
1874 | m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
1875 | { | |
1876 | return m68k_illegitimate_symbolic_constant_p (x); | |
1877 | } | |
1878 | ||
fc2241eb RS |
1879 | /* Return true if X is a legitimate constant address that can reach |
1880 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
1881 | strict checking. */ | |
1882 | ||
1883 | static bool | |
1884 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
1885 | { | |
1886 | rtx base, offset; | |
1887 | ||
1888 | if (!CONSTANT_ADDRESS_P (x)) | |
1889 | return false; | |
1890 | ||
1891 | if (flag_pic | |
1892 | && !(strict_p && TARGET_PCREL) | |
1893 | && symbolic_operand (x, VOIDmode)) | |
1894 | return false; | |
1895 | ||
1896 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
1897 | { | |
1898 | split_const (x, &base, &offset); | |
1899 | if (GET_CODE (base) == SYMBOL_REF | |
1900 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
1901 | return false; | |
1902 | } | |
1903 | ||
75df395f | 1904 | return !m68k_tls_reference_p (x, false); |
fc2241eb RS |
1905 | } |
1906 | ||
1907 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
1908 | labels will become jump tables. */ | |
1909 | ||
1910 | static bool | |
1911 | m68k_jump_table_ref_p (rtx x) | |
1912 | { | |
1913 | if (GET_CODE (x) != LABEL_REF) | |
1914 | return false; | |
1915 | ||
1916 | x = XEXP (x, 0); | |
1917 | if (!NEXT_INSN (x) && !PREV_INSN (x)) | |
1918 | return true; | |
1919 | ||
1920 | x = next_nonnote_insn (x); | |
1921 | return x && JUMP_TABLE_DATA_P (x); | |
1922 | } | |
1923 | ||
1924 | /* Return true if X is a legitimate address for values of mode MODE. | |
1925 | STRICT_P says whether strict checking is needed. If the address | |
1926 | is valid, describe its components in *ADDRESS. */ | |
1927 | ||
1928 | static bool | |
1929 | m68k_decompose_address (enum machine_mode mode, rtx x, | |
1930 | bool strict_p, struct m68k_address *address) | |
1931 | { | |
1932 | unsigned int reach; | |
1933 | ||
1934 | memset (address, 0, sizeof (*address)); | |
1935 | ||
1936 | if (mode == BLKmode) | |
1937 | reach = 1; | |
1938 | else | |
1939 | reach = GET_MODE_SIZE (mode); | |
1940 | ||
1941 | /* Check for (An) (mode 2). */ | |
1942 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1943 | { | |
1944 | address->base = x; | |
1945 | return true; | |
1946 | } | |
1947 | ||
1948 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
1949 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
1950 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1951 | { | |
1952 | address->code = GET_CODE (x); | |
1953 | address->base = XEXP (x, 0); | |
1954 | return true; | |
1955 | } | |
1956 | ||
1957 | /* Check for (d16,An) (mode 5). */ | |
1958 | if (GET_CODE (x) == PLUS | |
1959 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1960 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
1961 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1962 | { | |
1963 | address->base = XEXP (x, 0); | |
1964 | address->offset = XEXP (x, 1); | |
1965 | return true; | |
1966 | } | |
1967 | ||
1968 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
1969 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
1970 | addresses. */ | |
75df395f MK |
1971 | if (GET_CODE (x) == PLUS |
1972 | && XEXP (x, 0) == pic_offset_table_rtx) | |
fc2241eb | 1973 | { |
75df395f MK |
1974 | /* As we are processing a PLUS, do not unwrap RELOC32 symbols -- |
1975 | they are invalid in this context. */ | |
1976 | if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1)) | |
1977 | { | |
1978 | address->base = XEXP (x, 0); | |
1979 | address->offset = XEXP (x, 1); | |
1980 | return true; | |
1981 | } | |
fc2241eb RS |
1982 | } |
1983 | ||
1984 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
1985 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1986 | return false; | |
1987 | ||
1988 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
1989 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
1990 | All these modes are variations of mode 7. */ | |
1991 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
1992 | { | |
1993 | address->offset = x; | |
1994 | return true; | |
1995 | } | |
1996 | ||
1997 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
1998 | tablejumps. | |
1999 | ||
2000 | ??? do_tablejump creates these addresses before placing the target | |
2001 | label, so we have to assume that unplaced labels are jump table | |
2002 | references. It seems unlikely that we would ever generate indexed | |
2003 | accesses to unplaced labels in other cases. */ | |
2004 | if (GET_CODE (x) == PLUS | |
2005 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
2006 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2007 | { | |
2008 | address->offset = XEXP (x, 1); | |
2009 | return true; | |
2010 | } | |
2011 | ||
2012 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
2013 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
2014 | ||
2015 | if (TARGET_68020) | |
2016 | { | |
2017 | /* Check for a nonzero base displacement. */ | |
2018 | if (GET_CODE (x) == PLUS | |
2019 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
2020 | { | |
2021 | address->offset = XEXP (x, 1); | |
2022 | x = XEXP (x, 0); | |
2023 | } | |
2024 | ||
2025 | /* Check for a suppressed index register. */ | |
2026 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
2027 | { | |
2028 | address->base = x; | |
2029 | return true; | |
2030 | } | |
2031 | ||
2032 | /* Check for a suppressed base register. Do not allow this case | |
2033 | for non-symbolic offsets as it effectively gives gcc freedom | |
2034 | to treat data registers as base registers, which can generate | |
2035 | worse code. */ | |
2036 | if (address->offset | |
2037 | && symbolic_operand (address->offset, VOIDmode) | |
2038 | && m68k_decompose_index (x, strict_p, address)) | |
2039 | return true; | |
2040 | } | |
2041 | else | |
2042 | { | |
2043 | /* Check for a nonzero base displacement. */ | |
2044 | if (GET_CODE (x) == PLUS | |
2045 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2046 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
2047 | { | |
2048 | address->offset = XEXP (x, 1); | |
2049 | x = XEXP (x, 0); | |
2050 | } | |
2051 | } | |
2052 | ||
2053 | /* We now expect the sum of a base and an index. */ | |
2054 | if (GET_CODE (x) == PLUS) | |
2055 | { | |
2056 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
2057 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
2058 | { | |
2059 | address->base = XEXP (x, 0); | |
2060 | return true; | |
2061 | } | |
2062 | ||
2063 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
2064 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2065 | { | |
2066 | address->base = XEXP (x, 1); | |
2067 | return true; | |
2068 | } | |
2069 | } | |
2070 | return false; | |
2071 | } | |
2072 | ||
2073 | /* Return true if X is a legitimate address for values of mode MODE. | |
2074 | STRICT_P says whether strict checking is needed. */ | |
2075 | ||
2076 | bool | |
2077 | m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
2078 | { | |
2079 | struct m68k_address address; | |
2080 | ||
2081 | return m68k_decompose_address (mode, x, strict_p, &address); | |
2082 | } | |
2083 | ||
2084 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
2085 | Apply strict checking if called during or after reload. */ | |
2086 | ||
2087 | static bool | |
2088 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
2089 | { | |
2090 | return (MEM_P (x) | |
2091 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
2092 | reload_in_progress || reload_completed, | |
2093 | address)); | |
2094 | } | |
2095 | ||
1a627b35 RS |
2096 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
2097 | ||
2098 | bool | |
2099 | m68k_legitimate_constant_p (enum machine_mode mode, rtx x) | |
2100 | { | |
2101 | return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x); | |
2102 | } | |
2103 | ||
fc2241eb RS |
2104 | /* Return true if X matches the 'Q' constraint. It must be a memory |
2105 | with a base address and no constant offset or index. */ | |
2106 | ||
2107 | bool | |
2108 | m68k_matches_q_p (rtx x) | |
2109 | { | |
2110 | struct m68k_address address; | |
2111 | ||
2112 | return (m68k_legitimate_mem_p (x, &address) | |
2113 | && address.code == UNKNOWN | |
2114 | && address.base | |
2115 | && !address.offset | |
2116 | && !address.index); | |
2117 | } | |
2118 | ||
2119 | /* Return true if X matches the 'U' constraint. It must be a base address | |
2120 | with a constant offset and no index. */ | |
2121 | ||
2122 | bool | |
2123 | m68k_matches_u_p (rtx x) | |
2124 | { | |
2125 | struct m68k_address address; | |
2126 | ||
2127 | return (m68k_legitimate_mem_p (x, &address) | |
2128 | && address.code == UNKNOWN | |
2129 | && address.base | |
2130 | && address.offset | |
2131 | && !address.index); | |
2132 | } | |
2133 | ||
75df395f MK |
2134 | /* Return GOT pointer. */ |
2135 | ||
2136 | static rtx | |
2137 | m68k_get_gp (void) | |
2138 | { | |
2139 | if (pic_offset_table_rtx == NULL_RTX) | |
2140 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG); | |
2141 | ||
2142 | crtl->uses_pic_offset_table = 1; | |
2143 | ||
2144 | return pic_offset_table_rtx; | |
2145 | } | |
2146 | ||
2147 | /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC | |
2148 | wrappers. */ | |
2149 | enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO, | |
2150 | RELOC_TLSIE, RELOC_TLSLE }; | |
2151 | ||
2152 | #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT) | |
2153 | ||
2154 | /* Wrap symbol X into unspec representing relocation RELOC. | |
2155 | BASE_REG - register that should be added to the result. | |
2156 | TEMP_REG - if non-null, temporary register. */ | |
2157 | ||
2158 | static rtx | |
2159 | m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg) | |
2160 | { | |
2161 | bool use_x_p; | |
2162 | ||
2163 | use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS; | |
2164 | ||
2165 | if (TARGET_COLDFIRE && use_x_p) | |
2166 | /* When compiling with -mx{got, tls} switch the code will look like this: | |
2167 | ||
2168 | move.l <X>@<RELOC>,<TEMP_REG> | |
2169 | add.l <BASE_REG>,<TEMP_REG> */ | |
2170 | { | |
2171 | /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra | |
2172 | to put @RELOC after reference. */ | |
2173 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2174 | UNSPEC_RELOC32); | |
2175 | x = gen_rtx_CONST (Pmode, x); | |
2176 | ||
2177 | if (temp_reg == NULL) | |
2178 | { | |
2179 | gcc_assert (can_create_pseudo_p ()); | |
2180 | temp_reg = gen_reg_rtx (Pmode); | |
2181 | } | |
2182 | ||
2183 | emit_move_insn (temp_reg, x); | |
2184 | emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg)); | |
2185 | x = temp_reg; | |
2186 | } | |
2187 | else | |
2188 | { | |
2189 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2190 | UNSPEC_RELOC16); | |
2191 | x = gen_rtx_CONST (Pmode, x); | |
2192 | ||
2193 | x = gen_rtx_PLUS (Pmode, base_reg, x); | |
2194 | } | |
2195 | ||
2196 | return x; | |
2197 | } | |
2198 | ||
2199 | /* Helper for m68k_unwrap_symbol. | |
2200 | Also, if unwrapping was successful (that is if (ORIG != <return value>)), | |
2201 | sets *RELOC_PTR to relocation type for the symbol. */ | |
2202 | ||
2203 | static rtx | |
2204 | m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p, | |
2205 | enum m68k_reloc *reloc_ptr) | |
2206 | { | |
2207 | if (GET_CODE (orig) == CONST) | |
2208 | { | |
2209 | rtx x; | |
2210 | enum m68k_reloc dummy; | |
2211 | ||
2212 | x = XEXP (orig, 0); | |
2213 | ||
2214 | if (reloc_ptr == NULL) | |
2215 | reloc_ptr = &dummy; | |
2216 | ||
2217 | /* Handle an addend. */ | |
2218 | if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS) | |
2219 | && CONST_INT_P (XEXP (x, 1))) | |
2220 | x = XEXP (x, 0); | |
2221 | ||
2222 | if (GET_CODE (x) == UNSPEC) | |
2223 | { | |
2224 | switch (XINT (x, 1)) | |
2225 | { | |
2226 | case UNSPEC_RELOC16: | |
2227 | orig = XVECEXP (x, 0, 0); | |
2228 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2229 | break; | |
2230 | ||
2231 | case UNSPEC_RELOC32: | |
2232 | if (unwrap_reloc32_p) | |
2233 | { | |
2234 | orig = XVECEXP (x, 0, 0); | |
2235 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2236 | } | |
2237 | break; | |
2238 | ||
2239 | default: | |
2240 | break; | |
2241 | } | |
2242 | } | |
2243 | } | |
2244 | ||
2245 | return orig; | |
2246 | } | |
2247 | ||
2248 | /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p, | |
2249 | UNSPEC_RELOC32 wrappers. */ | |
2250 | ||
2251 | rtx | |
2252 | m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p) | |
2253 | { | |
2254 | return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL); | |
2255 | } | |
2256 | ||
2257 | /* Helper for m68k_final_prescan_insn. */ | |
2258 | ||
2259 | static int | |
2260 | m68k_final_prescan_insn_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED) | |
2261 | { | |
2262 | rtx x = *x_ptr; | |
2263 | ||
2264 | if (m68k_unwrap_symbol (x, true) != x) | |
2265 | /* For rationale of the below, see comment in m68k_final_prescan_insn. */ | |
2266 | { | |
2267 | rtx plus; | |
2268 | ||
2269 | gcc_assert (GET_CODE (x) == CONST); | |
2270 | plus = XEXP (x, 0); | |
2271 | ||
2272 | if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS) | |
2273 | { | |
2274 | rtx unspec; | |
2275 | rtx addend; | |
2276 | ||
2277 | unspec = XEXP (plus, 0); | |
2278 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
2279 | addend = XEXP (plus, 1); | |
2280 | gcc_assert (CONST_INT_P (addend)); | |
2281 | ||
2282 | /* We now have all the pieces, rearrange them. */ | |
2283 | ||
2284 | /* Move symbol to plus. */ | |
2285 | XEXP (plus, 0) = XVECEXP (unspec, 0, 0); | |
2286 | ||
2287 | /* Move plus inside unspec. */ | |
2288 | XVECEXP (unspec, 0, 0) = plus; | |
2289 | ||
2290 | /* Move unspec to top level of const. */ | |
2291 | XEXP (x, 0) = unspec; | |
2292 | } | |
2293 | ||
2294 | return -1; | |
2295 | } | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
2300 | /* Prescan insn before outputing assembler for it. */ | |
2301 | ||
2302 | void | |
2303 | m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED, | |
2304 | rtx *operands, int n_operands) | |
2305 | { | |
2306 | int i; | |
2307 | ||
2308 | /* Combine and, possibly, other optimizations may do good job | |
2309 | converting | |
2310 | (const (unspec [(symbol)])) | |
2311 | into | |
2312 | (const (plus (unspec [(symbol)]) | |
2313 | (const_int N))). | |
2314 | The problem with this is emitting @TLS or @GOT decorations. | |
2315 | The decoration is emitted when processing (unspec), so the | |
2316 | result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE". | |
2317 | ||
2318 | It seems that the easiest solution to this is to convert such | |
2319 | operands to | |
2320 | (const (unspec [(plus (symbol) | |
2321 | (const_int N))])). | |
2322 | Note, that the top level of operand remains intact, so we don't have | |
2323 | to patch up anything outside of the operand. */ | |
2324 | ||
2325 | for (i = 0; i < n_operands; ++i) | |
2326 | { | |
2327 | rtx op; | |
2328 | ||
2329 | op = operands[i]; | |
2330 | ||
2331 | for_each_rtx (&op, m68k_final_prescan_insn_1, NULL); | |
2332 | } | |
2333 | } | |
2334 | ||
2335 | /* Move X to a register and add REG_EQUAL note pointing to ORIG. | |
2336 | If REG is non-null, use it; generate new pseudo otherwise. */ | |
2337 | ||
2338 | static rtx | |
2339 | m68k_move_to_reg (rtx x, rtx orig, rtx reg) | |
2340 | { | |
2341 | rtx insn; | |
2342 | ||
2343 | if (reg == NULL_RTX) | |
2344 | { | |
2345 | gcc_assert (can_create_pseudo_p ()); | |
2346 | reg = gen_reg_rtx (Pmode); | |
2347 | } | |
2348 | ||
2349 | insn = emit_move_insn (reg, x); | |
2350 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2351 | by loop. */ | |
2352 | set_unique_reg_note (insn, REG_EQUAL, orig); | |
2353 | ||
2354 | return reg; | |
2355 | } | |
2356 | ||
2357 | /* Does the same as m68k_wrap_symbol, but returns a memory reference to | |
2358 | GOT slot. */ | |
2359 | ||
2360 | static rtx | |
2361 | m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) | |
2362 | { | |
2363 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg); | |
2364 | ||
2365 | x = gen_rtx_MEM (Pmode, x); | |
2366 | MEM_READONLY_P (x) = 1; | |
2367 | ||
2368 | return x; | |
2369 | } | |
2370 | ||
79e68feb RS |
2371 | /* Legitimize PIC addresses. If the address is already |
2372 | position-independent, we return ORIG. Newly generated | |
2373 | position-independent addresses go to REG. If we need more | |
2374 | than one register, we lose. | |
2375 | ||
2376 | An address is legitimized by making an indirect reference | |
2377 | through the Global Offset Table with the name of the symbol | |
2378 | used as an offset. | |
2379 | ||
2380 | The assembler and linker are responsible for placing the | |
2381 | address of the symbol in the GOT. The function prologue | |
2382 | is responsible for initializing a5 to the starting address | |
2383 | of the GOT. | |
2384 | ||
2385 | The assembler is also responsible for translating a symbol name | |
2386 | into a constant displacement from the start of the GOT. | |
2387 | ||
2388 | A quick example may make things a little clearer: | |
2389 | ||
2390 | When not generating PIC code to store the value 12345 into _foo | |
2391 | we would generate the following code: | |
2392 | ||
2393 | movel #12345, _foo | |
2394 | ||
2395 | When generating PIC two transformations are made. First, the compiler | |
2396 | loads the address of foo into a register. So the first transformation makes: | |
2397 | ||
2398 | lea _foo, a0 | |
2399 | movel #12345, a0@ | |
2400 | ||
2401 | The code in movsi will intercept the lea instruction and call this | |
2402 | routine which will transform the instructions into: | |
2403 | ||
2404 | movel a5@(_foo:w), a0 | |
2405 | movel #12345, a0@ | |
2406 | ||
2407 | ||
2408 | That (in a nutshell) is how *all* symbol and label references are | |
2409 | handled. */ | |
2410 | ||
2411 | rtx | |
8a4a2253 BI |
2412 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
2413 | rtx reg) | |
79e68feb RS |
2414 | { |
2415 | rtx pic_ref = orig; | |
2416 | ||
2417 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
2418 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
2419 | { | |
4761e388 | 2420 | gcc_assert (reg); |
79e68feb | 2421 | |
75df395f MK |
2422 | pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg); |
2423 | pic_ref = m68k_move_to_reg (pic_ref, orig, reg); | |
79e68feb RS |
2424 | } |
2425 | else if (GET_CODE (orig) == CONST) | |
2426 | { | |
1d8eaa6b | 2427 | rtx base; |
79e68feb | 2428 | |
b2e08ed4 | 2429 | /* Make sure this has not already been legitimized. */ |
75df395f | 2430 | if (m68k_unwrap_symbol (orig, true) != orig) |
79e68feb RS |
2431 | return orig; |
2432 | ||
4761e388 | 2433 | gcc_assert (reg); |
79e68feb RS |
2434 | |
2435 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
2436 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
2437 | ||
2438 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2439 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2440 | base == reg ? 0 : reg); | |
79e68feb RS |
2441 | |
2442 | if (GET_CODE (orig) == CONST_INT) | |
75df395f MK |
2443 | pic_ref = plus_constant (base, INTVAL (orig)); |
2444 | else | |
2445 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); | |
79e68feb | 2446 | } |
75df395f | 2447 | |
79e68feb RS |
2448 | return pic_ref; |
2449 | } | |
2450 | ||
75df395f MK |
2451 | /* The __tls_get_addr symbol. */ |
2452 | static GTY(()) rtx m68k_tls_get_addr; | |
2453 | ||
2454 | /* Return SYMBOL_REF for __tls_get_addr. */ | |
2455 | ||
2456 | static rtx | |
2457 | m68k_get_tls_get_addr (void) | |
2458 | { | |
2459 | if (m68k_tls_get_addr == NULL_RTX) | |
2460 | m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr"); | |
2461 | ||
2462 | return m68k_tls_get_addr; | |
2463 | } | |
2464 | ||
2465 | /* Return libcall result in A0 instead of usual D0. */ | |
2466 | static bool m68k_libcall_value_in_a0_p = false; | |
2467 | ||
2468 | /* Emit instruction sequence that calls __tls_get_addr. X is | |
2469 | the TLS symbol we are referencing and RELOC is the symbol type to use | |
2470 | (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence | |
2471 | emitted. A pseudo register with result of __tls_get_addr call is | |
2472 | returned. */ | |
2473 | ||
2474 | static rtx | |
2475 | m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc) | |
2476 | { | |
2477 | rtx a0; | |
2478 | rtx insns; | |
2479 | rtx dest; | |
2480 | ||
2481 | /* Emit the call sequence. */ | |
2482 | start_sequence (); | |
2483 | ||
2484 | /* FIXME: Unfortunately, emit_library_call_value does not | |
2485 | consider (plus (%a5) (const (unspec))) to be a good enough | |
2486 | operand for push, so it forces it into a register. The bad | |
2487 | thing about this is that combiner, due to copy propagation and other | |
2488 | optimizations, sometimes can not later fix this. As a consequence, | |
2489 | additional register may be allocated resulting in a spill. | |
2490 | For reference, see args processing loops in | |
2491 | calls.c:emit_library_call_value_1. | |
2492 | For testcase, see gcc.target/m68k/tls-{gd, ld}.c */ | |
2493 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX); | |
2494 | ||
2495 | /* __tls_get_addr() is not a libcall, but emitting a libcall_value | |
2496 | is the simpliest way of generating a call. The difference between | |
2497 | __tls_get_addr() and libcall is that the result is returned in D0 | |
2498 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2499 | which temporarily switches returning the result to A0. */ | |
2500 | ||
2501 | m68k_libcall_value_in_a0_p = true; | |
2502 | a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE, | |
2503 | Pmode, 1, x, Pmode); | |
2504 | m68k_libcall_value_in_a0_p = false; | |
2505 | ||
2506 | insns = get_insns (); | |
2507 | end_sequence (); | |
2508 | ||
2509 | gcc_assert (can_create_pseudo_p ()); | |
2510 | dest = gen_reg_rtx (Pmode); | |
2511 | emit_libcall_block (insns, dest, a0, eqv); | |
2512 | ||
2513 | return dest; | |
2514 | } | |
2515 | ||
2516 | /* The __tls_get_addr symbol. */ | |
2517 | static GTY(()) rtx m68k_read_tp; | |
2518 | ||
2519 | /* Return SYMBOL_REF for __m68k_read_tp. */ | |
2520 | ||
2521 | static rtx | |
2522 | m68k_get_m68k_read_tp (void) | |
2523 | { | |
2524 | if (m68k_read_tp == NULL_RTX) | |
2525 | m68k_read_tp = init_one_libfunc ("__m68k_read_tp"); | |
2526 | ||
2527 | return m68k_read_tp; | |
2528 | } | |
2529 | ||
2530 | /* Emit instruction sequence that calls __m68k_read_tp. | |
2531 | A pseudo register with result of __m68k_read_tp call is returned. */ | |
2532 | ||
2533 | static rtx | |
2534 | m68k_call_m68k_read_tp (void) | |
2535 | { | |
2536 | rtx a0; | |
2537 | rtx eqv; | |
2538 | rtx insns; | |
2539 | rtx dest; | |
2540 | ||
2541 | start_sequence (); | |
2542 | ||
2543 | /* __m68k_read_tp() is not a libcall, but emitting a libcall_value | |
2544 | is the simpliest way of generating a call. The difference between | |
2545 | __m68k_read_tp() and libcall is that the result is returned in D0 | |
2546 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2547 | which temporarily switches returning the result to A0. */ | |
2548 | ||
2549 | /* Emit the call sequence. */ | |
2550 | m68k_libcall_value_in_a0_p = true; | |
2551 | a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE, | |
2552 | Pmode, 0); | |
2553 | m68k_libcall_value_in_a0_p = false; | |
2554 | insns = get_insns (); | |
2555 | end_sequence (); | |
2556 | ||
2557 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2558 | share the m68k_read_tp result with other IE/LE model accesses. */ | |
2559 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32); | |
2560 | ||
2561 | gcc_assert (can_create_pseudo_p ()); | |
2562 | dest = gen_reg_rtx (Pmode); | |
2563 | emit_libcall_block (insns, dest, a0, eqv); | |
2564 | ||
2565 | return dest; | |
2566 | } | |
2567 | ||
2568 | /* Return a legitimized address for accessing TLS SYMBOL_REF X. | |
2569 | For explanations on instructions sequences see TLS/NPTL ABI for m68k and | |
2570 | ColdFire. */ | |
2571 | ||
2572 | rtx | |
2573 | m68k_legitimize_tls_address (rtx orig) | |
2574 | { | |
2575 | switch (SYMBOL_REF_TLS_MODEL (orig)) | |
2576 | { | |
2577 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
2578 | orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD); | |
2579 | break; | |
2580 | ||
2581 | case TLS_MODEL_LOCAL_DYNAMIC: | |
2582 | { | |
2583 | rtx eqv; | |
2584 | rtx a0; | |
2585 | rtx x; | |
2586 | ||
2587 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2588 | share the LDM result with other LD model accesses. */ | |
2589 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2590 | UNSPEC_RELOC32); | |
2591 | ||
2592 | a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM); | |
2593 | ||
2594 | x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX); | |
2595 | ||
2596 | if (can_create_pseudo_p ()) | |
2597 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2598 | ||
2599 | orig = x; | |
2600 | break; | |
2601 | } | |
2602 | ||
2603 | case TLS_MODEL_INITIAL_EXEC: | |
2604 | { | |
2605 | rtx a0; | |
2606 | rtx x; | |
2607 | ||
2608 | a0 = m68k_call_m68k_read_tp (); | |
2609 | ||
2610 | x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX); | |
2611 | x = gen_rtx_PLUS (Pmode, x, a0); | |
2612 | ||
2613 | if (can_create_pseudo_p ()) | |
2614 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2615 | ||
2616 | orig = x; | |
2617 | break; | |
2618 | } | |
2619 | ||
2620 | case TLS_MODEL_LOCAL_EXEC: | |
2621 | { | |
2622 | rtx a0; | |
2623 | rtx x; | |
2624 | ||
2625 | a0 = m68k_call_m68k_read_tp (); | |
2626 | ||
2627 | x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX); | |
2628 | ||
2629 | if (can_create_pseudo_p ()) | |
2630 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2631 | ||
2632 | orig = x; | |
2633 | break; | |
2634 | } | |
2635 | ||
2636 | default: | |
2637 | gcc_unreachable (); | |
2638 | } | |
2639 | ||
2640 | return orig; | |
2641 | } | |
2642 | ||
2643 | /* Return true if X is a TLS symbol. */ | |
2644 | ||
2645 | static bool | |
2646 | m68k_tls_symbol_p (rtx x) | |
2647 | { | |
2648 | if (!TARGET_HAVE_TLS) | |
2649 | return false; | |
2650 | ||
2651 | if (GET_CODE (x) != SYMBOL_REF) | |
2652 | return false; | |
2653 | ||
2654 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
2655 | } | |
2656 | ||
2657 | /* Helper for m68k_tls_referenced_p. */ | |
2658 | ||
2659 | static int | |
2660 | m68k_tls_reference_p_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED) | |
2661 | { | |
2662 | /* Note: this is not the same as m68k_tls_symbol_p. */ | |
2663 | if (GET_CODE (*x_ptr) == SYMBOL_REF) | |
2664 | return SYMBOL_REF_TLS_MODEL (*x_ptr) != 0 ? 1 : 0; | |
2665 | ||
2666 | /* Don't recurse into legitimate TLS references. */ | |
2667 | if (m68k_tls_reference_p (*x_ptr, true)) | |
2668 | return -1; | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | ||
2673 | /* If !LEGITIMATE_P, return true if X is a TLS symbol reference, | |
2674 | though illegitimate one. | |
2675 | If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */ | |
2676 | ||
2677 | bool | |
2678 | m68k_tls_reference_p (rtx x, bool legitimate_p) | |
2679 | { | |
2680 | if (!TARGET_HAVE_TLS) | |
2681 | return false; | |
2682 | ||
2683 | if (!legitimate_p) | |
2684 | return for_each_rtx (&x, m68k_tls_reference_p_1, NULL) == 1 ? true : false; | |
2685 | else | |
2686 | { | |
2687 | enum m68k_reloc reloc = RELOC_GOT; | |
2688 | ||
2689 | return (m68k_unwrap_symbol_1 (x, true, &reloc) != x | |
2690 | && TLS_RELOC_P (reloc)); | |
2691 | } | |
2692 | } | |
2693 | ||
79e68feb | 2694 | \f |
0ce6f9fb | 2695 | |
a0a7fbc9 | 2696 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 2697 | |
bda2a571 RS |
2698 | /* Return the type of move that should be used for integer I. */ |
2699 | ||
c47b0cb4 MK |
2700 | M68K_CONST_METHOD |
2701 | m68k_const_method (HOST_WIDE_INT i) | |
0ce6f9fb | 2702 | { |
0ce6f9fb RK |
2703 | unsigned u; |
2704 | ||
6910dd70 | 2705 | if (USE_MOVQ (i)) |
0ce6f9fb | 2706 | return MOVQ; |
24092242 | 2707 | |
c16eadc7 | 2708 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 2709 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 2710 | if (!TARGET_COLDFIRE) |
24092242 RK |
2711 | { |
2712 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 2713 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
2714 | if (USE_MOVQ (i ^ 0xff)) |
2715 | return NOTB; | |
2716 | /* Likewise, try with not.w */ | |
2717 | if (USE_MOVQ (i ^ 0xffff)) | |
2718 | return NOTW; | |
2719 | /* This is the only value where neg.w is useful */ | |
2720 | if (i == -65408) | |
2721 | return NEGW; | |
24092242 | 2722 | } |
28bad6d1 | 2723 | |
5e04daf3 PB |
2724 | /* Try also with swap. */ |
2725 | u = i; | |
2726 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2727 | return SWAP; | |
2728 | ||
986e74d5 | 2729 | if (TARGET_ISAB) |
28bad6d1 | 2730 | { |
72edf146 | 2731 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
2732 | if (i >= 0 && i <= 65535) |
2733 | return MVZ; | |
2734 | if (i >= -32768 && i <= 32767) | |
2735 | return MVS; | |
2736 | } | |
2737 | ||
0ce6f9fb RK |
2738 | /* Otherwise, use move.l */ |
2739 | return MOVL; | |
2740 | } | |
2741 | ||
bda2a571 RS |
2742 | /* Return the cost of moving constant I into a data register. */ |
2743 | ||
3c50106f | 2744 | static int |
bda2a571 | 2745 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 2746 | { |
c47b0cb4 | 2747 | switch (m68k_const_method (i)) |
0ce6f9fb | 2748 | { |
a0a7fbc9 AS |
2749 | case MOVQ: |
2750 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2751 | return 0; | |
2752 | case MVZ: | |
2753 | case MVS: | |
2754 | case NOTB: | |
2755 | case NOTW: | |
2756 | case NEGW: | |
2757 | case SWAP: | |
2758 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2759 | return 1; | |
2760 | case MOVL: | |
2761 | return 2; | |
2762 | default: | |
2763 | gcc_unreachable (); | |
0ce6f9fb RK |
2764 | } |
2765 | } | |
2766 | ||
3c50106f | 2767 | static bool |
f40751dd JH |
2768 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total, |
2769 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
2770 | { |
2771 | switch (code) | |
2772 | { | |
2773 | case CONST_INT: | |
2774 | /* Constant zero is super cheap due to clr instruction. */ | |
2775 | if (x == const0_rtx) | |
2776 | *total = 0; | |
2777 | else | |
bda2a571 | 2778 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
2779 | return true; |
2780 | ||
2781 | case CONST: | |
2782 | case LABEL_REF: | |
2783 | case SYMBOL_REF: | |
2784 | *total = 3; | |
2785 | return true; | |
2786 | ||
2787 | case CONST_DOUBLE: | |
2788 | /* Make 0.0 cheaper than other floating constants to | |
2789 | encourage creating tstsf and tstdf insns. */ | |
2790 | if (outer_code == COMPARE | |
2791 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
2792 | *total = 4; | |
2793 | else | |
2794 | *total = 5; | |
2795 | return true; | |
2796 | ||
2797 | /* These are vaguely right for a 68020. */ | |
2798 | /* The costs for long multiply have been adjusted to work properly | |
2799 | in synth_mult on the 68020, relative to an average of the time | |
2800 | for add and the time for shift, taking away a little more because | |
2801 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
2802 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
2803 | terms. */ | |
fe95f2f7 JB |
2804 | #define MULL_COST \ |
2805 | (TUNE_68060 ? 2 \ | |
2806 | : TUNE_68040 ? 5 \ | |
03b3e271 KH |
2807 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ |
2808 | : (TUNE_CFV2 && TUNE_MAC) ? 4 \ | |
2809 | : TUNE_CFV2 ? 8 \ | |
fe95f2f7 JB |
2810 | : TARGET_COLDFIRE ? 3 : 13) |
2811 | ||
2812 | #define MULW_COST \ | |
2813 | (TUNE_68060 ? 2 \ | |
2814 | : TUNE_68040 ? 3 \ | |
03b3e271 KH |
2815 | : TUNE_68000_10 ? 5 \ |
2816 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ | |
2817 | : (TUNE_CFV2 && TUNE_MAC) ? 2 \ | |
2818 | : TUNE_CFV2 ? 8 \ | |
fe95f2f7 JB |
2819 | : TARGET_COLDFIRE ? 2 : 8) |
2820 | ||
2821 | #define DIVW_COST \ | |
2822 | (TARGET_CF_HWDIV ? 11 \ | |
2823 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
2824 | |
2825 | case PLUS: | |
2826 | /* An lea costs about three times as much as a simple add. */ | |
2827 | if (GET_MODE (x) == SImode | |
2828 | && GET_CODE (XEXP (x, 1)) == REG | |
2829 | && GET_CODE (XEXP (x, 0)) == MULT | |
2830 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2831 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2832 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
2833 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
2834 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
2835 | { |
2836 | /* lea an@(dx:l:i),am */ | |
2837 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
2838 | return true; | |
2839 | } | |
3c50106f RH |
2840 | return false; |
2841 | ||
2842 | case ASHIFT: | |
2843 | case ASHIFTRT: | |
2844 | case LSHIFTRT: | |
fe95f2f7 | 2845 | if (TUNE_68060) |
3c50106f RH |
2846 | { |
2847 | *total = COSTS_N_INSNS(1); | |
2848 | return true; | |
2849 | } | |
fe95f2f7 | 2850 | if (TUNE_68000_10) |
3c50106f RH |
2851 | { |
2852 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2853 | { | |
2854 | if (INTVAL (XEXP (x, 1)) < 16) | |
2855 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
2856 | else | |
2857 | /* We're using clrw + swap for these cases. */ | |
2858 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
2859 | } | |
2860 | else | |
a0a7fbc9 | 2861 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
2862 | return true; |
2863 | } | |
2864 | /* A shift by a big integer takes an extra instruction. */ | |
2865 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2866 | && (INTVAL (XEXP (x, 1)) == 16)) | |
2867 | { | |
2868 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
2869 | return true; | |
2870 | } | |
2871 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2872 | && !(INTVAL (XEXP (x, 1)) > 0 | |
2873 | && INTVAL (XEXP (x, 1)) <= 8)) | |
2874 | { | |
eb849993 | 2875 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
2876 | return true; |
2877 | } | |
2878 | return false; | |
2879 | ||
2880 | case MULT: | |
2881 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2882 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
2883 | && GET_MODE (x) == SImode) | |
2884 | *total = COSTS_N_INSNS (MULW_COST); | |
2885 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2886 | *total = COSTS_N_INSNS (MULW_COST); | |
2887 | else | |
2888 | *total = COSTS_N_INSNS (MULL_COST); | |
2889 | return true; | |
2890 | ||
2891 | case DIV: | |
2892 | case UDIV: | |
2893 | case MOD: | |
2894 | case UMOD: | |
2895 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2896 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
2897 | else if (TARGET_CF_HWDIV) |
2898 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
2899 | else |
2900 | *total = COSTS_N_INSNS (43); /* div.l */ | |
2901 | return true; | |
2902 | ||
f90b7a5a PB |
2903 | case ZERO_EXTRACT: |
2904 | if (outer_code == COMPARE) | |
2905 | *total = 0; | |
2906 | return false; | |
2907 | ||
3c50106f RH |
2908 | default: |
2909 | return false; | |
2910 | } | |
2911 | } | |
2912 | ||
88512ba0 | 2913 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
2914 | OPERANDS[0]. */ |
2915 | ||
2916 | static const char * | |
8a4a2253 | 2917 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 2918 | { |
bda2a571 | 2919 | HOST_WIDE_INT i; |
0ce6f9fb RK |
2920 | |
2921 | i = INTVAL (operands[1]); | |
c47b0cb4 | 2922 | switch (m68k_const_method (i)) |
0ce6f9fb | 2923 | { |
28bad6d1 | 2924 | case MVZ: |
28bad6d1 | 2925 | return "mvzw %1,%0"; |
1cbae84f PB |
2926 | case MVS: |
2927 | return "mvsw %1,%0"; | |
a0a7fbc9 | 2928 | case MOVQ: |
0ce6f9fb | 2929 | return "moveq %1,%0"; |
a0a7fbc9 | 2930 | case NOTB: |
66e07510 | 2931 | CC_STATUS_INIT; |
1d8eaa6b | 2932 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 2933 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 2934 | case NOTW: |
66e07510 | 2935 | CC_STATUS_INIT; |
1d8eaa6b | 2936 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 2937 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 2938 | case NEGW: |
66e07510 | 2939 | CC_STATUS_INIT; |
3b4b85c9 | 2940 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 2941 | case SWAP: |
0ce6f9fb RK |
2942 | { |
2943 | unsigned u = i; | |
2944 | ||
1d8eaa6b | 2945 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 2946 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 2947 | } |
a0a7fbc9 | 2948 | case MOVL: |
bda2a571 | 2949 | return "move%.l %1,%0"; |
a0a7fbc9 | 2950 | default: |
bda2a571 | 2951 | gcc_unreachable (); |
0ce6f9fb RK |
2952 | } |
2953 | } | |
2954 | ||
bda2a571 | 2955 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 2956 | |
bda2a571 RS |
2957 | bool |
2958 | valid_mov3q_const (HOST_WIDE_INT i) | |
2959 | { | |
2960 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
2961 | } |
2962 | ||
bda2a571 RS |
2963 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
2964 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 2965 | |
bda2a571 | 2966 | static const char * |
8a4a2253 | 2967 | output_move_simode_const (rtx *operands) |
02ed0c07 | 2968 | { |
bda2a571 RS |
2969 | rtx dest; |
2970 | HOST_WIDE_INT src; | |
2971 | ||
2972 | dest = operands[0]; | |
2973 | src = INTVAL (operands[1]); | |
2974 | if (src == 0 | |
2975 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
2976 | /* clr insns on 68000 read before writing. */ |
2977 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 2978 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 2979 | return "clr%.l %0"; |
bda2a571 | 2980 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 2981 | return "mov3q%.l %1,%0"; |
bda2a571 | 2982 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 2983 | return "sub%.l %0,%0"; |
bda2a571 | 2984 | else if (DATA_REG_P (dest)) |
02ed0c07 | 2985 | return output_move_const_into_data_reg (operands); |
bda2a571 | 2986 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 2987 | { |
bda2a571 | 2988 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2989 | return "mov3q%.l %1,%0"; |
2990 | return "move%.w %1,%0"; | |
2991 | } | |
bda2a571 RS |
2992 | else if (MEM_P (dest) |
2993 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2994 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
2995 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 2996 | { |
bda2a571 | 2997 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2998 | return "mov3q%.l %1,%-"; |
2999 | return "pea %a1"; | |
3000 | } | |
02ed0c07 RK |
3001 | return "move%.l %1,%0"; |
3002 | } | |
3003 | ||
5505f548 | 3004 | const char * |
8a4a2253 | 3005 | output_move_simode (rtx *operands) |
f4e80198 RK |
3006 | { |
3007 | if (GET_CODE (operands[1]) == CONST_INT) | |
3008 | return output_move_simode_const (operands); | |
3009 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3010 | || GET_CODE (operands[1]) == CONST) | |
3011 | && push_operand (operands[0], SImode)) | |
3012 | return "pea %a1"; | |
3013 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3014 | || GET_CODE (operands[1]) == CONST) | |
3015 | && ADDRESS_REG_P (operands[0])) | |
3016 | return "lea %a1,%0"; | |
3017 | return "move%.l %1,%0"; | |
3018 | } | |
3019 | ||
5505f548 | 3020 | const char * |
8a4a2253 | 3021 | output_move_himode (rtx *operands) |
f4e80198 RK |
3022 | { |
3023 | if (GET_CODE (operands[1]) == CONST_INT) | |
3024 | { | |
3025 | if (operands[1] == const0_rtx | |
3026 | && (DATA_REG_P (operands[0]) | |
3027 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
3028 | /* clr insns on 68000 read before writing. */ |
3029 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
3030 | || !(GET_CODE (operands[0]) == MEM |
3031 | && MEM_VOLATILE_P (operands[0])))) | |
3032 | return "clr%.w %0"; | |
38198304 AS |
3033 | else if (operands[1] == const0_rtx |
3034 | && ADDRESS_REG_P (operands[0])) | |
3035 | return "sub%.l %0,%0"; | |
f4e80198 RK |
3036 | else if (DATA_REG_P (operands[0]) |
3037 | && INTVAL (operands[1]) < 128 | |
3038 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 3039 | return "moveq %1,%0"; |
f4e80198 RK |
3040 | else if (INTVAL (operands[1]) < 0x8000 |
3041 | && INTVAL (operands[1]) >= -0x8000) | |
3042 | return "move%.w %1,%0"; | |
3043 | } | |
3044 | else if (CONSTANT_P (operands[1])) | |
3045 | return "move%.l %1,%0"; | |
f4e80198 RK |
3046 | return "move%.w %1,%0"; |
3047 | } | |
3048 | ||
5505f548 | 3049 | const char * |
8a4a2253 | 3050 | output_move_qimode (rtx *operands) |
f4e80198 | 3051 | { |
102701ff | 3052 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 3053 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 3054 | |
a0a7fbc9 | 3055 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
3056 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
3057 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
3058 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
3059 | && ! ADDRESS_REG_P (operands[1]) | |
3060 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 3061 | |
3197c489 | 3062 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 3063 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 3064 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
3065 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3066 | { | |
3067 | if (operands[1] == const0_rtx) | |
3068 | return "clr%.b %0"; | |
9425fb04 | 3069 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
3070 | && GET_CODE (operands[1]) == CONST_INT |
3071 | && (INTVAL (operands[1]) & 255) == 255) | |
3072 | { | |
3073 | CC_STATUS_INIT; | |
3074 | return "st %0"; | |
3075 | } | |
3076 | } | |
3077 | if (GET_CODE (operands[1]) == CONST_INT | |
3078 | && DATA_REG_P (operands[0]) | |
3079 | && INTVAL (operands[1]) < 128 | |
3080 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 3081 | return "moveq %1,%0"; |
38198304 AS |
3082 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
3083 | return "sub%.l %0,%0"; | |
f4e80198 RK |
3084 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
3085 | return "move%.l %1,%0"; | |
c16eadc7 | 3086 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
3087 | from address registers. */ |
3088 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
3089 | return "move%.w %1,%0"; |
3090 | return "move%.b %1,%0"; | |
3091 | } | |
3092 | ||
5505f548 | 3093 | const char * |
8a4a2253 | 3094 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
3095 | { |
3096 | if (operands[1] == const0_rtx | |
3197c489 RS |
3097 | /* clr insns on 68000 read before writing. */ |
3098 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
3099 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3100 | return "clr%.w %0"; | |
3101 | return "move%.w %1,%0"; | |
3102 | } | |
3103 | ||
5505f548 | 3104 | const char * |
8a4a2253 | 3105 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
3106 | { |
3107 | if (operands[1] == const0_rtx | |
3197c489 RS |
3108 | /* clr insns on 68000 read before writing. */ |
3109 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
3110 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3111 | return "clr%.b %0"; | |
3112 | return "move%.b %1,%0"; | |
3113 | } | |
3114 | ||
79e68feb RS |
3115 | /* Return the best assembler insn template |
3116 | for moving operands[1] into operands[0] as a fullword. */ | |
3117 | ||
5505f548 | 3118 | static const char * |
8a4a2253 | 3119 | singlemove_string (rtx *operands) |
79e68feb | 3120 | { |
02ed0c07 RK |
3121 | if (GET_CODE (operands[1]) == CONST_INT) |
3122 | return output_move_simode_const (operands); | |
3123 | return "move%.l %1,%0"; | |
79e68feb RS |
3124 | } |
3125 | ||
2505bc97 | 3126 | |
c47b0cb4 MK |
3127 | /* Output assembler or rtl code to perform a doubleword move insn |
3128 | with operands OPERANDS. | |
3129 | Pointers to 3 helper functions should be specified: | |
3130 | HANDLE_REG_ADJUST to adjust a register by a small value, | |
3131 | HANDLE_COMPADR to compute an address and | |
3132 | HANDLE_MOVSI to move 4 bytes. */ | |
79e68feb | 3133 | |
c47b0cb4 MK |
3134 | static void |
3135 | handle_move_double (rtx operands[2], | |
3136 | void (*handle_reg_adjust) (rtx, int), | |
3137 | void (*handle_compadr) (rtx [2]), | |
3138 | void (*handle_movsi) (rtx [2])) | |
79e68feb | 3139 | { |
2505bc97 RS |
3140 | enum |
3141 | { | |
3142 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
3143 | } optype0, optype1; | |
79e68feb | 3144 | rtx latehalf[2]; |
2505bc97 | 3145 | rtx middlehalf[2]; |
7f98eeb6 | 3146 | rtx xops[2]; |
79e68feb | 3147 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 3148 | int dest_overlapped_low = 0; |
184916bc | 3149 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
3150 | |
3151 | middlehalf[0] = 0; | |
3152 | middlehalf[1] = 0; | |
79e68feb RS |
3153 | |
3154 | /* First classify both operands. */ | |
3155 | ||
3156 | if (REG_P (operands[0])) | |
3157 | optype0 = REGOP; | |
3158 | else if (offsettable_memref_p (operands[0])) | |
3159 | optype0 = OFFSOP; | |
3160 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
3161 | optype0 = POPOP; | |
3162 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
3163 | optype0 = PUSHOP; | |
3164 | else if (GET_CODE (operands[0]) == MEM) | |
3165 | optype0 = MEMOP; | |
3166 | else | |
3167 | optype0 = RNDOP; | |
3168 | ||
3169 | if (REG_P (operands[1])) | |
3170 | optype1 = REGOP; | |
3171 | else if (CONSTANT_P (operands[1])) | |
3172 | optype1 = CNSTOP; | |
3173 | else if (offsettable_memref_p (operands[1])) | |
3174 | optype1 = OFFSOP; | |
3175 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
3176 | optype1 = POPOP; | |
3177 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
3178 | optype1 = PUSHOP; | |
3179 | else if (GET_CODE (operands[1]) == MEM) | |
3180 | optype1 = MEMOP; | |
3181 | else | |
3182 | optype1 = RNDOP; | |
3183 | ||
4761e388 NS |
3184 | /* Check for the cases that the operand constraints are not supposed |
3185 | to allow to happen. Generating code for these cases is | |
3186 | painful. */ | |
3187 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
3188 | |
3189 | /* If one operand is decrementing and one is incrementing | |
3190 | decrement the former register explicitly | |
3191 | and change that operand into ordinary indexing. */ | |
3192 | ||
3193 | if (optype0 == PUSHOP && optype1 == POPOP) | |
3194 | { | |
3195 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
c47b0cb4 MK |
3196 | |
3197 | handle_reg_adjust (operands[0], -size); | |
3198 | ||
2505bc97 | 3199 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 3200 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 3201 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 3202 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 3203 | else |
1d8eaa6b | 3204 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
3205 | optype0 = OFFSOP; |
3206 | } | |
3207 | if (optype0 == POPOP && optype1 == PUSHOP) | |
3208 | { | |
3209 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
c47b0cb4 MK |
3210 | |
3211 | handle_reg_adjust (operands[1], -size); | |
3212 | ||
2505bc97 | 3213 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 3214 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 3215 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 3216 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 3217 | else |
1d8eaa6b | 3218 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
3219 | optype1 = OFFSOP; |
3220 | } | |
3221 | ||
3222 | /* If an operand is an unoffsettable memory ref, find a register | |
3223 | we can increment temporarily to make it refer to the second word. */ | |
3224 | ||
3225 | if (optype0 == MEMOP) | |
3226 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
3227 | ||
3228 | if (optype1 == MEMOP) | |
3229 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
3230 | ||
3231 | /* Ok, we can do one word at a time. | |
3232 | Normally we do the low-numbered word first, | |
3233 | but if either operand is autodecrementing then we | |
3234 | do the high-numbered word first. | |
3235 | ||
3236 | In either case, set up in LATEHALF the operands to use | |
3237 | for the high-numbered word and in some cases alter the | |
3238 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
3239 | ||
2505bc97 RS |
3240 | if (size == 12) |
3241 | { | |
3242 | if (optype0 == REGOP) | |
3243 | { | |
1d8eaa6b AS |
3244 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
3245 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
3246 | } |
3247 | else if (optype0 == OFFSOP) | |
3248 | { | |
b72f00af RK |
3249 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
3250 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
3251 | } |
3252 | else | |
3253 | { | |
c47b0cb4 MK |
3254 | middlehalf[0] = adjust_address (operands[0], SImode, 0); |
3255 | latehalf[0] = adjust_address (operands[0], SImode, 0); | |
2505bc97 RS |
3256 | } |
3257 | ||
3258 | if (optype1 == REGOP) | |
3259 | { | |
1d8eaa6b AS |
3260 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
3261 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
3262 | } |
3263 | else if (optype1 == OFFSOP) | |
3264 | { | |
b72f00af RK |
3265 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
3266 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
3267 | } |
3268 | else if (optype1 == CNSTOP) | |
3269 | { | |
3270 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3271 | { | |
3272 | REAL_VALUE_TYPE r; | |
3273 | long l[3]; | |
3274 | ||
3275 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
3276 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
3277 | operands[1] = GEN_INT (l[0]); | |
3278 | middlehalf[1] = GEN_INT (l[1]); | |
3279 | latehalf[1] = GEN_INT (l[2]); | |
3280 | } | |
4761e388 | 3281 | else |
2505bc97 | 3282 | { |
4761e388 NS |
3283 | /* No non-CONST_DOUBLE constant should ever appear |
3284 | here. */ | |
3285 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
3286 | } |
3287 | } | |
3288 | else | |
3289 | { | |
c47b0cb4 MK |
3290 | middlehalf[1] = adjust_address (operands[1], SImode, 0); |
3291 | latehalf[1] = adjust_address (operands[1], SImode, 0); | |
2505bc97 RS |
3292 | } |
3293 | } | |
79e68feb | 3294 | else |
2505bc97 RS |
3295 | /* size is not 12: */ |
3296 | { | |
3297 | if (optype0 == REGOP) | |
1d8eaa6b | 3298 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 3299 | else if (optype0 == OFFSOP) |
b72f00af | 3300 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 | 3301 | else |
c47b0cb4 | 3302 | latehalf[0] = adjust_address (operands[0], SImode, 0); |
2505bc97 RS |
3303 | |
3304 | if (optype1 == REGOP) | |
1d8eaa6b | 3305 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 3306 | else if (optype1 == OFFSOP) |
b72f00af | 3307 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
3308 | else if (optype1 == CNSTOP) |
3309 | split_double (operands[1], &operands[1], &latehalf[1]); | |
3310 | else | |
c47b0cb4 | 3311 | latehalf[1] = adjust_address (operands[1], SImode, 0); |
2505bc97 | 3312 | } |
79e68feb RS |
3313 | |
3314 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
3315 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
3316 | for the low word as well, to compensate for the first decrement of sp. */ | |
3317 | if (optype0 == PUSHOP | |
3318 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
3319 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 3320 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 3321 | |
7f98eeb6 RS |
3322 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
3323 | if the upper part of reg N does not appear in the MEM, arrange to | |
3324 | emit the move late-half first. Otherwise, compute the MEM address | |
3325 | into the upper part of N and use that as a pointer to the memory | |
3326 | operand. */ | |
3327 | if (optype0 == REGOP | |
3328 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
3329 | { | |
1d8eaa6b | 3330 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
3331 | |
3332 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 3333 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
3334 | { |
3335 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
3336 | compute the address into latehalf of dest. |
3337 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 3338 | compadr: |
7f98eeb6 RS |
3339 | xops[0] = latehalf[0]; |
3340 | xops[1] = XEXP (operands[1], 0); | |
c47b0cb4 MK |
3341 | |
3342 | handle_compadr (xops); | |
3343 | if (GET_MODE (operands[1]) == XFmode) | |
7f98eeb6 | 3344 | { |
1d8eaa6b | 3345 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
3346 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
3347 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
3348 | } |
3349 | else | |
3350 | { | |
1d8eaa6b | 3351 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 3352 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
3353 | } |
3354 | } | |
3355 | else if (size == 12 | |
d7e8d581 RS |
3356 | && reg_overlap_mentioned_p (middlehalf[0], |
3357 | XEXP (operands[1], 0))) | |
7f98eeb6 | 3358 | { |
3a58400f RS |
3359 | /* Check for two regs used by both source and dest. |
3360 | Note that this can't happen if the dest is all data regs. | |
3361 | It can happen if the dest is d6, d7, a0. | |
3362 | But in that case, latehalf is an addr reg, so | |
3363 | the code at compadr does ok. */ | |
3364 | ||
3365 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
3366 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
3367 | goto compadr; | |
7f98eeb6 RS |
3368 | |
3369 | /* JRV says this can't happen: */ | |
4761e388 | 3370 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 3371 | |
7a1929e1 | 3372 | /* Only the middle reg conflicts; simply put it last. */ |
c47b0cb4 MK |
3373 | handle_movsi (operands); |
3374 | handle_movsi (latehalf); | |
3375 | handle_movsi (middlehalf); | |
3376 | ||
3377 | return; | |
7f98eeb6 | 3378 | } |
2fb8a81d | 3379 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
3380 | /* If the low half of dest is mentioned in the source memory |
3381 | address, the arrange to emit the move late half first. */ | |
3382 | dest_overlapped_low = 1; | |
3383 | } | |
3384 | ||
79e68feb RS |
3385 | /* If one or both operands autodecrementing, |
3386 | do the two words, high-numbered first. */ | |
3387 | ||
3388 | /* Likewise, the first move would clobber the source of the second one, | |
3389 | do them in the other order. This happens only for registers; | |
3390 | such overlap can't happen in memory unless the user explicitly | |
3391 | sets it up, and that is an undefined circumstance. */ | |
3392 | ||
3393 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
3394 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 3395 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
3396 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
3397 | || dest_overlapped_low) | |
79e68feb RS |
3398 | { |
3399 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
3400 | if (addreg0) | |
c47b0cb4 | 3401 | handle_reg_adjust (addreg0, size - 4); |
79e68feb | 3402 | if (addreg1) |
c47b0cb4 | 3403 | handle_reg_adjust (addreg1, size - 4); |
79e68feb RS |
3404 | |
3405 | /* Do that word. */ | |
c47b0cb4 | 3406 | handle_movsi (latehalf); |
79e68feb RS |
3407 | |
3408 | /* Undo the adds we just did. */ | |
3409 | if (addreg0) | |
c47b0cb4 | 3410 | handle_reg_adjust (addreg0, -4); |
79e68feb | 3411 | if (addreg1) |
c47b0cb4 | 3412 | handle_reg_adjust (addreg1, -4); |
79e68feb | 3413 | |
2505bc97 RS |
3414 | if (size == 12) |
3415 | { | |
c47b0cb4 MK |
3416 | handle_movsi (middlehalf); |
3417 | ||
2505bc97 | 3418 | if (addreg0) |
c47b0cb4 | 3419 | handle_reg_adjust (addreg0, -4); |
2505bc97 | 3420 | if (addreg1) |
c47b0cb4 | 3421 | handle_reg_adjust (addreg1, -4); |
2505bc97 RS |
3422 | } |
3423 | ||
79e68feb | 3424 | /* Do low-numbered word. */ |
c47b0cb4 MK |
3425 | |
3426 | handle_movsi (operands); | |
3427 | return; | |
79e68feb RS |
3428 | } |
3429 | ||
3430 | /* Normal case: do the two words, low-numbered first. */ | |
3431 | ||
dcac2e64 | 3432 | m68k_final_prescan_insn (NULL, operands, 2); |
c47b0cb4 | 3433 | handle_movsi (operands); |
79e68feb | 3434 | |
2505bc97 RS |
3435 | /* Do the middle one of the three words for long double */ |
3436 | if (size == 12) | |
3437 | { | |
3438 | if (addreg0) | |
c47b0cb4 | 3439 | handle_reg_adjust (addreg0, 4); |
2505bc97 | 3440 | if (addreg1) |
c47b0cb4 | 3441 | handle_reg_adjust (addreg1, 4); |
2505bc97 | 3442 | |
dcac2e64 | 3443 | m68k_final_prescan_insn (NULL, middlehalf, 2); |
c47b0cb4 | 3444 | handle_movsi (middlehalf); |
2505bc97 RS |
3445 | } |
3446 | ||
79e68feb RS |
3447 | /* Make any unoffsettable addresses point at high-numbered word. */ |
3448 | if (addreg0) | |
c47b0cb4 | 3449 | handle_reg_adjust (addreg0, 4); |
79e68feb | 3450 | if (addreg1) |
c47b0cb4 | 3451 | handle_reg_adjust (addreg1, 4); |
79e68feb RS |
3452 | |
3453 | /* Do that word. */ | |
dcac2e64 | 3454 | m68k_final_prescan_insn (NULL, latehalf, 2); |
c47b0cb4 | 3455 | handle_movsi (latehalf); |
79e68feb RS |
3456 | |
3457 | /* Undo the adds we just did. */ | |
3458 | if (addreg0) | |
c47b0cb4 MK |
3459 | handle_reg_adjust (addreg0, -(size - 4)); |
3460 | if (addreg1) | |
3461 | handle_reg_adjust (addreg1, -(size - 4)); | |
3462 | ||
3463 | return; | |
3464 | } | |
3465 | ||
3466 | /* Output assembler code to adjust REG by N. */ | |
3467 | static void | |
3468 | output_reg_adjust (rtx reg, int n) | |
3469 | { | |
3470 | const char *s; | |
3471 | ||
3472 | gcc_assert (GET_MODE (reg) == SImode | |
3473 | && -12 <= n && n != 0 && n <= 12); | |
3474 | ||
3475 | switch (n) | |
2505bc97 | 3476 | { |
c47b0cb4 MK |
3477 | case 12: |
3478 | s = "add%.l #12,%0"; | |
3479 | break; | |
3480 | ||
3481 | case 8: | |
3482 | s = "addq%.l #8,%0"; | |
3483 | break; | |
3484 | ||
3485 | case 4: | |
3486 | s = "addq%.l #4,%0"; | |
3487 | break; | |
3488 | ||
3489 | case -12: | |
3490 | s = "sub%.l #12,%0"; | |
3491 | break; | |
3492 | ||
3493 | case -8: | |
3494 | s = "subq%.l #8,%0"; | |
3495 | break; | |
3496 | ||
3497 | case -4: | |
3498 | s = "subq%.l #4,%0"; | |
3499 | break; | |
3500 | ||
3501 | default: | |
3502 | gcc_unreachable (); | |
3503 | s = NULL; | |
2505bc97 | 3504 | } |
c47b0cb4 MK |
3505 | |
3506 | output_asm_insn (s, ®); | |
3507 | } | |
3508 | ||
3509 | /* Emit rtl code to adjust REG by N. */ | |
3510 | static void | |
3511 | emit_reg_adjust (rtx reg1, int n) | |
3512 | { | |
3513 | rtx reg2; | |
3514 | ||
3515 | gcc_assert (GET_MODE (reg1) == SImode | |
3516 | && -12 <= n && n != 0 && n <= 12); | |
3517 | ||
3518 | reg1 = copy_rtx (reg1); | |
3519 | reg2 = copy_rtx (reg1); | |
3520 | ||
3521 | if (n < 0) | |
3522 | emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n))); | |
3523 | else if (n > 0) | |
3524 | emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n))); | |
3525 | else | |
3526 | gcc_unreachable (); | |
3527 | } | |
3528 | ||
3529 | /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */ | |
3530 | static void | |
3531 | output_compadr (rtx operands[2]) | |
3532 | { | |
3533 | output_asm_insn ("lea %a1,%0", operands); | |
3534 | } | |
3535 | ||
3536 | /* Output the best assembler insn for moving operands[1] into operands[0] | |
3537 | as a fullword. */ | |
3538 | static void | |
3539 | output_movsi (rtx operands[2]) | |
3540 | { | |
3541 | output_asm_insn (singlemove_string (operands), operands); | |
3542 | } | |
3543 | ||
3544 | /* Copy OP and change its mode to MODE. */ | |
3545 | static rtx | |
3546 | copy_operand (rtx op, enum machine_mode mode) | |
3547 | { | |
3548 | /* ??? This looks really ugly. There must be a better way | |
3549 | to change a mode on the operand. */ | |
3550 | if (GET_MODE (op) != VOIDmode) | |
2505bc97 | 3551 | { |
c47b0cb4 MK |
3552 | if (REG_P (op)) |
3553 | op = gen_rtx_REG (mode, REGNO (op)); | |
2505bc97 | 3554 | else |
c47b0cb4 MK |
3555 | { |
3556 | op = copy_rtx (op); | |
3557 | PUT_MODE (op, mode); | |
3558 | } | |
2505bc97 | 3559 | } |
79e68feb | 3560 | |
c47b0cb4 MK |
3561 | return op; |
3562 | } | |
3563 | ||
3564 | /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */ | |
3565 | static void | |
3566 | emit_movsi (rtx operands[2]) | |
3567 | { | |
3568 | operands[0] = copy_operand (operands[0], SImode); | |
3569 | operands[1] = copy_operand (operands[1], SImode); | |
3570 | ||
3571 | emit_insn (gen_movsi (operands[0], operands[1])); | |
3572 | } | |
3573 | ||
3574 | /* Output assembler code to perform a doubleword move insn | |
3575 | with operands OPERANDS. */ | |
3576 | const char * | |
3577 | output_move_double (rtx *operands) | |
3578 | { | |
3579 | handle_move_double (operands, | |
3580 | output_reg_adjust, output_compadr, output_movsi); | |
3581 | ||
79e68feb RS |
3582 | return ""; |
3583 | } | |
3584 | ||
c47b0cb4 MK |
3585 | /* Output rtl code to perform a doubleword move insn |
3586 | with operands OPERANDS. */ | |
3587 | void | |
3588 | m68k_emit_move_double (rtx operands[2]) | |
3589 | { | |
3590 | handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi); | |
3591 | } | |
dcc21c4c PB |
3592 | |
3593 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
3594 | new rtx with the correct mode. */ | |
3595 | ||
3596 | static rtx | |
3597 | force_mode (enum machine_mode mode, rtx orig) | |
3598 | { | |
3599 | if (mode == GET_MODE (orig)) | |
3600 | return orig; | |
3601 | ||
3602 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
3603 | abort (); | |
3604 | ||
3605 | return gen_rtx_REG (mode, REGNO (orig)); | |
3606 | } | |
3607 | ||
3608 | static int | |
3609 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3610 | { | |
3611 | return reg_renumber && FP_REG_P (op); | |
3612 | } | |
3613 | ||
3614 | /* Emit insns to move operands[1] into operands[0]. | |
3615 | ||
3616 | Return 1 if we have written out everything that needs to be done to | |
3617 | do the move. Otherwise, return 0 and the caller will emit the move | |
3618 | normally. | |
3619 | ||
3620 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 3621 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
3622 | of SCRATCH_REG in the proper mode. */ |
3623 | ||
3624 | int | |
3625 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
3626 | { | |
3627 | register rtx operand0 = operands[0]; | |
3628 | register rtx operand1 = operands[1]; | |
3629 | register rtx tem; | |
3630 | ||
3631 | if (scratch_reg | |
3632 | && reload_in_progress && GET_CODE (operand0) == REG | |
3633 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
f2034d06 | 3634 | operand0 = reg_equiv_mem (REGNO (operand0)); |
dcc21c4c PB |
3635 | else if (scratch_reg |
3636 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
3637 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
3638 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
3639 | { | |
3640 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3641 | the code which tracks sets/uses for delete_output_reload. */ | |
3642 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
f2034d06 | 3643 | reg_equiv_mem (REGNO (SUBREG_REG (operand0))), |
dcc21c4c PB |
3644 | SUBREG_BYTE (operand0)); |
3645 | operand0 = alter_subreg (&temp); | |
3646 | } | |
3647 | ||
3648 | if (scratch_reg | |
3649 | && reload_in_progress && GET_CODE (operand1) == REG | |
3650 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
f2034d06 | 3651 | operand1 = reg_equiv_mem (REGNO (operand1)); |
dcc21c4c PB |
3652 | else if (scratch_reg |
3653 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
3654 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
3655 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
3656 | { | |
3657 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3658 | the code which tracks sets/uses for delete_output_reload. */ | |
3659 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
f2034d06 | 3660 | reg_equiv_mem (REGNO (SUBREG_REG (operand1))), |
dcc21c4c PB |
3661 | SUBREG_BYTE (operand1)); |
3662 | operand1 = alter_subreg (&temp); | |
3663 | } | |
3664 | ||
3665 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
3666 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
3667 | != XEXP (operand0, 0))) | |
3668 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
3669 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
3670 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
3671 | != XEXP (operand1, 0))) | |
3672 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
3673 | ||
3674 | /* Handle secondary reloads for loads/stores of FP registers where | |
3675 | the address is symbolic by using the scratch register */ | |
3676 | if (fp_reg_operand (operand0, mode) | |
3677 | && ((GET_CODE (operand1) == MEM | |
3678 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
3679 | || ((GET_CODE (operand1) == SUBREG | |
3680 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
3681 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
3682 | && scratch_reg) | |
3683 | { | |
3684 | if (GET_CODE (operand1) == SUBREG) | |
3685 | operand1 = XEXP (operand1, 0); | |
3686 | ||
3687 | /* SCRATCH_REG will hold an address. We want | |
3688 | it in SImode regardless of what mode it was originally given | |
3689 | to us. */ | |
3690 | scratch_reg = force_mode (SImode, scratch_reg); | |
3691 | ||
3692 | /* D might not fit in 14 bits either; for such cases load D into | |
3693 | scratch reg. */ | |
3694 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
3695 | { | |
3696 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
3697 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
3698 | Pmode, | |
3699 | XEXP (XEXP (operand1, 0), 0), | |
3700 | scratch_reg)); | |
3701 | } | |
3702 | else | |
3703 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
3704 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
3705 | gen_rtx_MEM (mode, scratch_reg))); | |
3706 | return 1; | |
3707 | } | |
3708 | else if (fp_reg_operand (operand1, mode) | |
3709 | && ((GET_CODE (operand0) == MEM | |
3710 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
3711 | || ((GET_CODE (operand0) == SUBREG) | |
3712 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
3713 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
3714 | && scratch_reg) | |
3715 | { | |
3716 | if (GET_CODE (operand0) == SUBREG) | |
3717 | operand0 = XEXP (operand0, 0); | |
3718 | ||
3719 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3720 | it in SIMODE regardless of what mode it was originally given | |
3721 | to us. */ | |
3722 | scratch_reg = force_mode (SImode, scratch_reg); | |
3723 | ||
3724 | /* D might not fit in 14 bits either; for such cases load D into | |
3725 | scratch reg. */ | |
3726 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
3727 | { | |
3728 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
3729 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
3730 | 0)), | |
3731 | Pmode, | |
3732 | XEXP (XEXP (operand0, 0), | |
3733 | 0), | |
3734 | scratch_reg)); | |
3735 | } | |
3736 | else | |
3737 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
3738 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
3739 | operand1)); | |
3740 | return 1; | |
3741 | } | |
3742 | /* Handle secondary reloads for loads of FP registers from constant | |
3743 | expressions by forcing the constant into memory. | |
3744 | ||
3745 | use scratch_reg to hold the address of the memory location. | |
3746 | ||
3747 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
3748 | NO_REGS when presented with a const_int and an register class | |
3749 | containing only FP registers. Doing so unfortunately creates | |
3750 | more problems than it solves. Fix this for 2.5. */ | |
3751 | else if (fp_reg_operand (operand0, mode) | |
3752 | && CONSTANT_P (operand1) | |
3753 | && scratch_reg) | |
3754 | { | |
3755 | rtx xoperands[2]; | |
3756 | ||
3757 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3758 | it in SIMODE regardless of what mode it was originally given | |
3759 | to us. */ | |
3760 | scratch_reg = force_mode (SImode, scratch_reg); | |
3761 | ||
3762 | /* Force the constant into memory and put the address of the | |
3763 | memory location into scratch_reg. */ | |
3764 | xoperands[0] = scratch_reg; | |
3765 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
3766 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
3767 | ||
3768 | /* Now load the destination register. */ | |
3769 | emit_insn (gen_rtx_SET (mode, operand0, | |
3770 | gen_rtx_MEM (mode, scratch_reg))); | |
3771 | return 1; | |
3772 | } | |
3773 | ||
3774 | /* Now have insn-emit do whatever it normally does. */ | |
3775 | return 0; | |
3776 | } | |
3777 | ||
01e304f8 RZ |
3778 | /* Split one or more DImode RTL references into pairs of SImode |
3779 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
3780 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
3781 | split and "num" is its length. lo_half and hi_half are output arrays | |
3782 | that parallel "operands". */ | |
3783 | ||
3784 | void | |
3785 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
3786 | { | |
3787 | while (num--) | |
3788 | { | |
3789 | rtx op = operands[num]; | |
3790 | ||
3791 | /* simplify_subreg refuses to split volatile memory addresses, | |
3792 | but we still have to handle it. */ | |
3793 | if (GET_CODE (op) == MEM) | |
3794 | { | |
3795 | lo_half[num] = adjust_address (op, SImode, 4); | |
3796 | hi_half[num] = adjust_address (op, SImode, 0); | |
3797 | } | |
3798 | else | |
3799 | { | |
3800 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
3801 | GET_MODE (op) == VOIDmode | |
3802 | ? DImode : GET_MODE (op), 4); | |
3803 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
3804 | GET_MODE (op) == VOIDmode | |
3805 | ? DImode : GET_MODE (op), 0); | |
3806 | } | |
3807 | } | |
3808 | } | |
3809 | ||
a40ed0f3 KH |
3810 | /* Split X into a base and a constant offset, storing them in *BASE |
3811 | and *OFFSET respectively. */ | |
3812 | ||
3813 | static void | |
3814 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
3815 | { | |
3816 | *offset = 0; | |
3817 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3818 | { | |
3819 | *offset += INTVAL (XEXP (x, 1)); | |
3820 | x = XEXP (x, 0); | |
3821 | } | |
3822 | *base = x; | |
3823 | } | |
3824 | ||
3825 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
3826 | instruction. STORE_P says whether the move is a load or store. | |
3827 | ||
3828 | If the instruction uses post-increment or pre-decrement addressing, | |
3829 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
3830 | adjustment. This adjustment will be made by the first element of | |
3831 | PARALLEL, with the loads or stores starting at element 1. If the | |
3832 | instruction does not use post-increment or pre-decrement addressing, | |
3833 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
3834 | start at element 0. */ | |
3835 | ||
3836 | bool | |
3837 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
3838 | HOST_WIDE_INT automod_offset, bool store_p) | |
3839 | { | |
3840 | rtx base, mem_base, set, mem, reg, last_reg; | |
3841 | HOST_WIDE_INT offset, mem_offset; | |
3842 | int i, first, len; | |
3843 | enum reg_class rclass; | |
3844 | ||
3845 | len = XVECLEN (pattern, 0); | |
3846 | first = (automod_base != NULL); | |
3847 | ||
3848 | if (automod_base) | |
3849 | { | |
3850 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
3851 | if (store_p != (automod_offset < 0)) | |
3852 | return false; | |
3853 | ||
3854 | /* Work out the base and offset for lowest memory location. */ | |
3855 | base = automod_base; | |
3856 | offset = (automod_offset < 0 ? automod_offset : 0); | |
3857 | } | |
3858 | else | |
3859 | { | |
3860 | /* Allow any valid base and offset in the first access. */ | |
3861 | base = NULL; | |
3862 | offset = 0; | |
3863 | } | |
3864 | ||
3865 | last_reg = NULL; | |
3866 | rclass = NO_REGS; | |
3867 | for (i = first; i < len; i++) | |
3868 | { | |
3869 | /* We need a plain SET. */ | |
3870 | set = XVECEXP (pattern, 0, i); | |
3871 | if (GET_CODE (set) != SET) | |
3872 | return false; | |
3873 | ||
3874 | /* Check that we have a memory location... */ | |
3875 | mem = XEXP (set, !store_p); | |
3876 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
3877 | return false; | |
3878 | ||
3879 | /* ...with the right address. */ | |
3880 | if (base == NULL) | |
3881 | { | |
3882 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
3883 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
3884 | There are no mode restrictions for 680x0 besides the | |
3885 | automodification rules enforced above. */ | |
3886 | if (TARGET_COLDFIRE | |
3887 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
3888 | return false; | |
3889 | } | |
3890 | else | |
3891 | { | |
3892 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
3893 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
3894 | return false; | |
3895 | } | |
3896 | ||
3897 | /* Check that we have a register of the required mode and class. */ | |
3898 | reg = XEXP (set, store_p); | |
3899 | if (!REG_P (reg) | |
3900 | || !HARD_REGISTER_P (reg) | |
3901 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
3902 | return false; | |
3903 | ||
3904 | if (last_reg) | |
3905 | { | |
3906 | /* The register must belong to RCLASS and have a higher number | |
3907 | than the register in the previous SET. */ | |
3908 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
3909 | || REGNO (last_reg) >= REGNO (reg)) | |
3910 | return false; | |
3911 | } | |
3912 | else | |
3913 | { | |
3914 | /* Work out which register class we need. */ | |
3915 | if (INT_REGNO_P (REGNO (reg))) | |
3916 | rclass = GENERAL_REGS; | |
3917 | else if (FP_REGNO_P (REGNO (reg))) | |
3918 | rclass = FP_REGS; | |
3919 | else | |
3920 | return false; | |
3921 | } | |
3922 | ||
3923 | last_reg = reg; | |
3924 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
3925 | } | |
3926 | ||
3927 | /* If we have an automodification, check whether the final offset is OK. */ | |
3928 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
3929 | return false; | |
3930 | ||
3931 | /* Reject unprofitable cases. */ | |
3932 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
3933 | return false; | |
3934 | ||
3935 | return true; | |
3936 | } | |
3937 | ||
3938 | /* Return the assembly code template for a movem or fmovem instruction | |
3939 | whose pattern is given by PATTERN. Store the template's operands | |
3940 | in OPERANDS. | |
3941 | ||
3942 | If the instruction uses post-increment or pre-decrement addressing, | |
3943 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
3944 | is true if this is a store instruction. */ | |
3945 | ||
3946 | const char * | |
3947 | m68k_output_movem (rtx *operands, rtx pattern, | |
3948 | HOST_WIDE_INT automod_offset, bool store_p) | |
3949 | { | |
3950 | unsigned int mask; | |
3951 | int i, first; | |
3952 | ||
3953 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
3954 | mask = 0; | |
3955 | first = (automod_offset != 0); | |
3956 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
3957 | { | |
3958 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
3959 | is controlled by bit 15 - X. For all other addressing modes, | |
3960 | register X + D0_REG is controlled by bit X. Confusingly, the | |
3961 | register mask for fmovem is in the opposite order to that for | |
3962 | movem. */ | |
3963 | unsigned int regno; | |
3964 | ||
3965 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
3966 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
3967 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
3968 | if (automod_offset < 0) | |
3969 | { | |
3970 | if (FP_REGNO_P (regno)) | |
3971 | mask |= 1 << (regno - FP0_REG); | |
3972 | else | |
3973 | mask |= 1 << (15 - (regno - D0_REG)); | |
3974 | } | |
3975 | else | |
3976 | { | |
3977 | if (FP_REGNO_P (regno)) | |
3978 | mask |= 1 << (7 - (regno - FP0_REG)); | |
3979 | else | |
3980 | mask |= 1 << (regno - D0_REG); | |
3981 | } | |
3982 | } | |
3983 | CC_STATUS_INIT; | |
3984 | ||
3985 | if (automod_offset == 0) | |
3986 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
3987 | else if (automod_offset < 0) | |
3988 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3989 | else | |
3990 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3991 | operands[1] = GEN_INT (mask); | |
3992 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
3993 | { | |
3994 | if (store_p) | |
1fae2d80 | 3995 | return "fmovem %1,%a0"; |
a40ed0f3 | 3996 | else |
1fae2d80 | 3997 | return "fmovem %a0,%1"; |
a40ed0f3 KH |
3998 | } |
3999 | else | |
4000 | { | |
4001 | if (store_p) | |
1fae2d80 | 4002 | return "movem%.l %1,%a0"; |
a40ed0f3 | 4003 | else |
1fae2d80 | 4004 | return "movem%.l %a0,%1"; |
a40ed0f3 KH |
4005 | } |
4006 | } | |
4007 | ||
79e68feb RS |
4008 | /* Return a REG that occurs in ADDR with coefficient 1. |
4009 | ADDR can be effectively incremented by incrementing REG. */ | |
4010 | ||
4011 | static rtx | |
8a4a2253 | 4012 | find_addr_reg (rtx addr) |
79e68feb RS |
4013 | { |
4014 | while (GET_CODE (addr) == PLUS) | |
4015 | { | |
4016 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
4017 | addr = XEXP (addr, 0); | |
4018 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
4019 | addr = XEXP (addr, 1); | |
4020 | else if (CONSTANT_P (XEXP (addr, 0))) | |
4021 | addr = XEXP (addr, 1); | |
4022 | else if (CONSTANT_P (XEXP (addr, 1))) | |
4023 | addr = XEXP (addr, 0); | |
4024 | else | |
4761e388 | 4025 | gcc_unreachable (); |
79e68feb | 4026 | } |
4761e388 NS |
4027 | gcc_assert (GET_CODE (addr) == REG); |
4028 | return addr; | |
79e68feb | 4029 | } |
9ee3c687 | 4030 | |
c16eadc7 | 4031 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 4032 | |
5505f548 | 4033 | const char * |
8a4a2253 | 4034 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
4035 | { |
4036 | if (! operands_match_p (operands[0], operands[1])) | |
4037 | { | |
4038 | if (!ADDRESS_REG_P (operands[1])) | |
4039 | { | |
4040 | rtx tmp = operands[1]; | |
4041 | ||
4042 | operands[1] = operands[2]; | |
4043 | operands[2] = tmp; | |
4044 | } | |
4045 | ||
4046 | /* These insns can result from reloads to access | |
4047 | stack slots over 64k from the frame pointer. */ | |
4048 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 4049 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 4050 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 4051 | if (GET_CODE (operands[2]) == REG) |
4b3d1177 KH |
4052 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
4053 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
4054 | } |
4055 | if (GET_CODE (operands[2]) == CONST_INT) | |
4056 | { | |
9ee3c687 JW |
4057 | if (INTVAL (operands[2]) > 0 |
4058 | && INTVAL (operands[2]) <= 8) | |
4059 | return "addq%.l %2,%0"; | |
4060 | if (INTVAL (operands[2]) < 0 | |
4061 | && INTVAL (operands[2]) >= -8) | |
4062 | { | |
c5c76735 | 4063 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
4064 | return "subq%.l %2,%0"; |
4065 | } | |
4066 | /* On the CPU32 it is faster to use two addql instructions to | |
4067 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 4068 | Likewise for subql. */ |
fe95f2f7 | 4069 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
4070 | { |
4071 | if (INTVAL (operands[2]) > 8 | |
4072 | && INTVAL (operands[2]) <= 16) | |
4073 | { | |
1d8eaa6b | 4074 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 4075 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
4076 | } |
4077 | if (INTVAL (operands[2]) < -8 | |
4078 | && INTVAL (operands[2]) >= -16) | |
4079 | { | |
c5c76735 | 4080 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 4081 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
4082 | } |
4083 | } | |
9ee3c687 JW |
4084 | if (ADDRESS_REG_P (operands[0]) |
4085 | && INTVAL (operands[2]) >= -0x8000 | |
4086 | && INTVAL (operands[2]) < 0x8000) | |
4087 | { | |
fe95f2f7 | 4088 | if (TUNE_68040) |
9ee3c687 JW |
4089 | return "add%.w %2,%0"; |
4090 | else | |
4b3d1177 | 4091 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
4092 | } |
4093 | } | |
4094 | return "add%.l %2,%0"; | |
4095 | } | |
79e68feb RS |
4096 | \f |
4097 | /* Store in cc_status the expressions that the condition codes will | |
4098 | describe after execution of an instruction whose pattern is EXP. | |
4099 | Do not alter them if the instruction would not alter the cc's. */ | |
4100 | ||
4101 | /* On the 68000, all the insns to store in an address register fail to | |
4102 | set the cc's. However, in some cases these instructions can make it | |
4103 | possibly invalid to use the saved cc's. In those cases we clear out | |
4104 | some or all of the saved cc's so they won't be used. */ | |
4105 | ||
1d8eaa6b | 4106 | void |
8a4a2253 | 4107 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 4108 | { |
1a8965c4 | 4109 | if (GET_CODE (exp) == SET) |
79e68feb RS |
4110 | { |
4111 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 4112 | CC_STATUS_INIT; |
79e68feb RS |
4113 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
4114 | { | |
f5963e61 | 4115 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 4116 | cc_status.value1 = 0; |
f5963e61 | 4117 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
4118 | cc_status.value2 = 0; |
4119 | } | |
f6ab62e8 RS |
4120 | /* fmoves to memory or data registers do not set the condition |
4121 | codes. Normal moves _do_ set the condition codes, but not in | |
4122 | a way that is appropriate for comparison with 0, because -0.0 | |
4123 | would be treated as a negative nonzero number. Note that it | |
88512ba0 | 4124 | isn't appropriate to conditionalize this restriction on |
f6ab62e8 RS |
4125 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
4126 | we care about the difference between -0.0 and +0.0. */ | |
79e68feb RS |
4127 | else if (!FP_REG_P (SET_DEST (exp)) |
4128 | && SET_DEST (exp) != cc0_rtx | |
4129 | && (FP_REG_P (SET_SRC (exp)) | |
4130 | || GET_CODE (SET_SRC (exp)) == FIX | |
f6ab62e8 | 4131 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
a0a7fbc9 | 4132 | CC_STATUS_INIT; |
79e68feb RS |
4133 | /* A pair of move insns doesn't produce a useful overall cc. */ |
4134 | else if (!FP_REG_P (SET_DEST (exp)) | |
4135 | && !FP_REG_P (SET_SRC (exp)) | |
4136 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
4137 | && (GET_CODE (SET_SRC (exp)) == REG | |
4138 | || GET_CODE (SET_SRC (exp)) == MEM | |
4139 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 4140 | CC_STATUS_INIT; |
e1dff52a | 4141 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
4142 | { |
4143 | cc_status.flags = 0; | |
e1dff52a KH |
4144 | cc_status.value1 = SET_DEST (exp); |
4145 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
4146 | } |
4147 | } | |
4148 | else if (GET_CODE (exp) == PARALLEL | |
4149 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
4150 | { | |
e1dff52a KH |
4151 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
4152 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
4153 | ||
4154 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 4155 | CC_STATUS_INIT; |
e1dff52a | 4156 | else if (dest != pc_rtx) |
79e68feb RS |
4157 | { |
4158 | cc_status.flags = 0; | |
e1dff52a KH |
4159 | cc_status.value1 = dest; |
4160 | cc_status.value2 = src; | |
79e68feb RS |
4161 | } |
4162 | } | |
4163 | else | |
4164 | CC_STATUS_INIT; | |
4165 | if (cc_status.value2 != 0 | |
4166 | && ADDRESS_REG_P (cc_status.value2) | |
4167 | && GET_MODE (cc_status.value2) == QImode) | |
4168 | CC_STATUS_INIT; | |
1a8965c4 | 4169 | if (cc_status.value2 != 0) |
79e68feb RS |
4170 | switch (GET_CODE (cc_status.value2)) |
4171 | { | |
996a5f59 | 4172 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 4173 | case ROTATE: case ROTATERT: |
a126dc3a RH |
4174 | /* These instructions always clear the overflow bit, and set |
4175 | the carry to the bit shifted out. */ | |
1afac9a6 | 4176 | cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; |
a126dc3a RH |
4177 | break; |
4178 | ||
4179 | case PLUS: case MINUS: case MULT: | |
4180 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
4181 | if (GET_MODE (cc_status.value2) != VOIDmode) |
4182 | cc_status.flags |= CC_NO_OVERFLOW; | |
4183 | break; | |
4184 | case ZERO_EXTEND: | |
4185 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
4186 | ends with a move insn moving r2 in r2's mode. | |
4187 | Thus, the cc's are set for r2. | |
7a1929e1 | 4188 | This can set N bit spuriously. */ |
79e68feb | 4189 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
4190 | |
4191 | default: | |
4192 | break; | |
79e68feb RS |
4193 | } |
4194 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
4195 | && cc_status.value2 | |
4196 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
4197 | cc_status.value2 = 0; | |
4198 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 4199 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb | 4200 | cc_status.flags = CC_IN_68881; |
67595cbb RZ |
4201 | if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE |
4202 | && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT) | |
4203 | { | |
4204 | cc_status.flags = CC_IN_68881; | |
4205 | if (!FP_REG_P (XEXP (cc_status.value2, 0))) | |
4206 | cc_status.flags |= CC_REVERSED; | |
4207 | } | |
79e68feb RS |
4208 | } |
4209 | \f | |
5505f548 | 4210 | const char * |
8a4a2253 | 4211 | output_move_const_double (rtx *operands) |
79e68feb | 4212 | { |
1a8965c4 | 4213 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 4214 | |
1a8965c4 | 4215 | if (code != 0) |
79e68feb | 4216 | { |
1a8965c4 | 4217 | static char buf[40]; |
79e68feb | 4218 | |
3b4b85c9 | 4219 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 4220 | return buf; |
79e68feb | 4221 | } |
1a8965c4 | 4222 | return "fmove%.d %1,%0"; |
79e68feb RS |
4223 | } |
4224 | ||
5505f548 | 4225 | const char * |
8a4a2253 | 4226 | output_move_const_single (rtx *operands) |
79e68feb | 4227 | { |
1a8965c4 | 4228 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 4229 | |
1a8965c4 | 4230 | if (code != 0) |
79e68feb | 4231 | { |
1a8965c4 | 4232 | static char buf[40]; |
79e68feb | 4233 | |
3b4b85c9 | 4234 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 4235 | return buf; |
79e68feb | 4236 | } |
1a8965c4 | 4237 | return "fmove%.s %f1,%0"; |
79e68feb RS |
4238 | } |
4239 | ||
4240 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
4241 | from the "fmovecr" instruction. | |
4242 | The value, anded with 0xff, gives the code to use in fmovecr | |
4243 | to get the desired constant. */ | |
4244 | ||
7a1929e1 | 4245 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
4246 | |
4247 | static int inited_68881_table = 0; | |
4248 | ||
5505f548 | 4249 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
4250 | "0.0", |
4251 | "1.0", | |
4252 | "10.0", | |
4253 | "100.0", | |
4254 | "10000.0", | |
4255 | "1e8", | |
4256 | "1e16" | |
a0a7fbc9 | 4257 | }; |
c1cfb2ae | 4258 | |
8b60264b | 4259 | static const int codes_68881[7] = { |
c1cfb2ae RS |
4260 | 0x0f, |
4261 | 0x32, | |
4262 | 0x33, | |
4263 | 0x34, | |
4264 | 0x35, | |
4265 | 0x36, | |
4266 | 0x37 | |
a0a7fbc9 | 4267 | }; |
c1cfb2ae RS |
4268 | |
4269 | REAL_VALUE_TYPE values_68881[7]; | |
4270 | ||
4271 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 4272 | strings_68881 to binary. */ |
c1cfb2ae RS |
4273 | |
4274 | void | |
8a4a2253 | 4275 | init_68881_table (void) |
c1cfb2ae RS |
4276 | { |
4277 | int i; | |
4278 | REAL_VALUE_TYPE r; | |
4279 | enum machine_mode mode; | |
4280 | ||
16d82c3c | 4281 | mode = SFmode; |
c1cfb2ae RS |
4282 | for (i = 0; i < 7; i++) |
4283 | { | |
4284 | if (i == 6) | |
16d82c3c | 4285 | mode = DFmode; |
c1cfb2ae RS |
4286 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
4287 | values_68881[i] = r; | |
4288 | } | |
4289 | inited_68881_table = 1; | |
4290 | } | |
79e68feb RS |
4291 | |
4292 | int | |
8a4a2253 | 4293 | standard_68881_constant_p (rtx x) |
79e68feb | 4294 | { |
c1cfb2ae RS |
4295 | REAL_VALUE_TYPE r; |
4296 | int i; | |
79e68feb | 4297 | |
e18db50d | 4298 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 4299 | used at all on those chips. */ |
9cf106c8 | 4300 | if (TUNE_68040_60) |
79e68feb RS |
4301 | return 0; |
4302 | ||
c1cfb2ae RS |
4303 | if (! inited_68881_table) |
4304 | init_68881_table (); | |
4305 | ||
4306 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
4307 | ||
64c0b414 AS |
4308 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
4309 | is rejected. */ | |
c1cfb2ae RS |
4310 | for (i = 0; i < 6; i++) |
4311 | { | |
64c0b414 | 4312 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
4313 | return (codes_68881[i]); |
4314 | } | |
4315 | ||
79e68feb RS |
4316 | if (GET_MODE (x) == SFmode) |
4317 | return 0; | |
c1cfb2ae RS |
4318 | |
4319 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
4320 | return (codes_68881[6]); | |
4321 | ||
79e68feb RS |
4322 | /* larger powers of ten in the constants ram are not used |
4323 | because they are not equal to a `double' C constant. */ | |
4324 | return 0; | |
4325 | } | |
4326 | ||
4327 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
4328 | or 0 if X is not a power of 2. */ | |
4329 | ||
4330 | int | |
8a4a2253 | 4331 | floating_exact_log2 (rtx x) |
79e68feb | 4332 | { |
c1cfb2ae | 4333 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 4334 | int exp; |
79e68feb | 4335 | |
c1cfb2ae | 4336 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 4337 | |
eaff3bf8 | 4338 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
4339 | return 0; |
4340 | ||
eaff3bf8 | 4341 | exp = real_exponent (&r); |
6ef9a246 | 4342 | real_2expN (&r1, exp, DFmode); |
eaff3bf8 RH |
4343 | if (REAL_VALUES_EQUAL (r1, r)) |
4344 | return exp; | |
4345 | ||
79e68feb RS |
4346 | return 0; |
4347 | } | |
4348 | \f | |
79e68feb RS |
4349 | /* A C compound statement to output to stdio stream STREAM the |
4350 | assembler syntax for an instruction operand X. X is an RTL | |
4351 | expression. | |
4352 | ||
4353 | CODE is a value that can be used to specify one of several ways | |
4354 | of printing the operand. It is used when identical operands | |
4355 | must be printed differently depending on the context. CODE | |
4356 | comes from the `%' specification that was used to request | |
4357 | printing of the operand. If the specification was just `%DIGIT' | |
4358 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
4359 | is the ASCII code for LTR. | |
4360 | ||
4361 | If X is a register, this macro should print the register's name. | |
4362 | The names can be found in an array `reg_names' whose type is | |
4363 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
4364 | ||
4365 | When the machine description has a specification `%PUNCT' (a `%' | |
4366 | followed by a punctuation character), this macro is called with | |
4367 | a null pointer for X and the punctuation character for CODE. | |
4368 | ||
4369 | The m68k specific codes are: | |
4370 | ||
4371 | '.' for dot needed in Motorola-style opcode names. | |
4372 | '-' for an operand pushing on the stack: | |
4373 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
4374 | '+' for an operand pushing on the stack: | |
4375 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
4376 | '@' for a reference to the top word on the stack: | |
4377 | sp@, (sp) or (%sp) depending on the style of syntax. | |
4378 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 4379 | but & in SGS syntax). |
79e68feb RS |
4380 | '!' for the cc register (used in an `and to cc' insn). |
4381 | '$' for the letter `s' in an op code, but only on the 68040. | |
4382 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 4383 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 4384 | '?' for m68k_library_id_string |
79e68feb RS |
4385 | |
4386 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
4387 | 'd' to force memory addressing to be absolute, not relative. | |
4388 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
4389 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
4390 | or print pair of registers as rx:ry. | |
29ca003a RS |
4391 | 'p' print an address with @PLTPC attached, but only if the operand |
4392 | is not locally-bound. */ | |
79e68feb RS |
4393 | |
4394 | void | |
8a4a2253 | 4395 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 4396 | { |
79e68feb RS |
4397 | if (letter == '.') |
4398 | { | |
e6d98cb0 BI |
4399 | if (MOTOROLA) |
4400 | fprintf (file, "."); | |
79e68feb RS |
4401 | } |
4402 | else if (letter == '#') | |
e6d98cb0 | 4403 | asm_fprintf (file, "%I"); |
79e68feb | 4404 | else if (letter == '-') |
4b3d1177 | 4405 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 4406 | else if (letter == '+') |
4b3d1177 | 4407 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 4408 | else if (letter == '@') |
4b3d1177 | 4409 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 4410 | else if (letter == '!') |
e6d98cb0 | 4411 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
4412 | else if (letter == '$') |
4413 | { | |
b101567e | 4414 | if (TARGET_68040) |
e6d98cb0 | 4415 | fprintf (file, "s"); |
79e68feb RS |
4416 | } |
4417 | else if (letter == '&') | |
4418 | { | |
b101567e | 4419 | if (TARGET_68040) |
e6d98cb0 | 4420 | fprintf (file, "d"); |
79e68feb | 4421 | } |
2ac5f14a | 4422 | else if (letter == '/') |
e6d98cb0 | 4423 | asm_fprintf (file, "%R"); |
a40ed0f3 KH |
4424 | else if (letter == '?') |
4425 | asm_fprintf (file, m68k_library_id_string); | |
29ca003a | 4426 | else if (letter == 'p') |
2c8ec431 | 4427 | { |
29ca003a RS |
4428 | output_addr_const (file, op); |
4429 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
4430 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 4431 | } |
79e68feb RS |
4432 | else if (GET_CODE (op) == REG) |
4433 | { | |
1a8965c4 AS |
4434 | if (letter == 'R') |
4435 | /* Print out the second register name of a register pair. | |
4436 | I.e., R (6) => 7. */ | |
01bbf777 | 4437 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 4438 | else |
01bbf777 | 4439 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
4440 | } |
4441 | else if (GET_CODE (op) == MEM) | |
4442 | { | |
4443 | output_address (XEXP (op, 0)); | |
4444 | if (letter == 'd' && ! TARGET_68020 | |
4445 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
4446 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
4447 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
4448 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
4b3d1177 | 4449 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 4450 | } |
79e68feb RS |
4451 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
4452 | { | |
c1cfb2ae | 4453 | REAL_VALUE_TYPE r; |
6ae89ea8 | 4454 | long l; |
c1cfb2ae | 4455 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); |
6ae89ea8 | 4456 | REAL_VALUE_TO_TARGET_SINGLE (r, l); |
429ce992 | 4457 | asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF); |
c1cfb2ae RS |
4458 | } |
4459 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
4460 | { | |
4461 | REAL_VALUE_TYPE r; | |
6ae89ea8 | 4462 | long l[3]; |
c1cfb2ae | 4463 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); |
6ae89ea8 | 4464 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); |
429ce992 AS |
4465 | asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF, |
4466 | l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF); | |
79e68feb | 4467 | } |
e2c0a924 | 4468 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 4469 | { |
c1cfb2ae | 4470 | REAL_VALUE_TYPE r; |
6ae89ea8 | 4471 | long l[2]; |
c1cfb2ae | 4472 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); |
6ae89ea8 | 4473 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); |
429ce992 | 4474 | asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF); |
79e68feb RS |
4475 | } |
4476 | else | |
4477 | { | |
2c8ec431 DL |
4478 | /* Use `print_operand_address' instead of `output_addr_const' |
4479 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 4480 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
4481 | if (TARGET_PCREL |
4482 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
4483 | print_operand_address (file, op); | |
4484 | else | |
4485 | output_addr_const (file, op); | |
79e68feb RS |
4486 | } |
4487 | } | |
4488 | ||
75df395f MK |
4489 | /* Return string for TLS relocation RELOC. */ |
4490 | ||
4491 | static const char * | |
4492 | m68k_get_reloc_decoration (enum m68k_reloc reloc) | |
4493 | { | |
4494 | /* To my knowledge, !MOTOROLA assemblers don't support TLS. */ | |
4495 | gcc_assert (MOTOROLA || reloc == RELOC_GOT); | |
4496 | ||
4497 | switch (reloc) | |
4498 | { | |
4499 | case RELOC_GOT: | |
4500 | if (MOTOROLA) | |
4501 | { | |
4502 | if (flag_pic == 1 && TARGET_68020) | |
4503 | return "@GOT.w"; | |
4504 | else | |
4505 | return "@GOT"; | |
4506 | } | |
4507 | else | |
4508 | { | |
4509 | if (TARGET_68020) | |
4510 | { | |
4511 | switch (flag_pic) | |
4512 | { | |
4513 | case 1: | |
4514 | return ":w"; | |
4515 | case 2: | |
4516 | return ":l"; | |
4517 | default: | |
4518 | return ""; | |
4519 | } | |
4520 | } | |
4521 | } | |
4522 | ||
4523 | case RELOC_TLSGD: | |
4524 | return "@TLSGD"; | |
4525 | ||
4526 | case RELOC_TLSLDM: | |
4527 | return "@TLSLDM"; | |
4528 | ||
4529 | case RELOC_TLSLDO: | |
4530 | return "@TLSLDO"; | |
4531 | ||
4532 | case RELOC_TLSIE: | |
4533 | return "@TLSIE"; | |
4534 | ||
4535 | case RELOC_TLSLE: | |
4536 | return "@TLSLE"; | |
4537 | ||
4538 | default: | |
4539 | gcc_unreachable (); | |
4540 | } | |
4541 | } | |
4542 | ||
884316ff JM |
4543 | /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */ |
4544 | ||
4545 | bool | |
4546 | m68k_output_addr_const_extra (FILE *file, rtx x) | |
4547 | { | |
75df395f MK |
4548 | if (GET_CODE (x) == UNSPEC) |
4549 | { | |
4550 | switch (XINT (x, 1)) | |
4551 | { | |
4552 | case UNSPEC_RELOC16: | |
4553 | case UNSPEC_RELOC32: | |
4554 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
f878882b AS |
4555 | fputs (m68k_get_reloc_decoration |
4556 | ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file); | |
75df395f | 4557 | return true; |
884316ff | 4558 | |
75df395f MK |
4559 | default: |
4560 | break; | |
4561 | } | |
4562 | } | |
4563 | ||
4564 | return false; | |
4565 | } | |
4566 | ||
4567 | /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ | |
4568 | ||
4569 | static void | |
4570 | m68k_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
4571 | { | |
4572 | gcc_assert (size == 4); | |
4573 | fputs ("\t.long\t", file); | |
4574 | output_addr_const (file, x); | |
4575 | fputs ("@TLSLDO+0x8000", file); | |
884316ff JM |
4576 | } |
4577 | ||
7b0f476d AS |
4578 | /* In the name of slightly smaller debug output, and to cater to |
4579 | general assembler lossage, recognize various UNSPEC sequences | |
4580 | and turn them back into a direct symbol reference. */ | |
4581 | ||
4582 | static rtx | |
33d67485 | 4583 | m68k_delegitimize_address (rtx orig_x) |
7b0f476d | 4584 | { |
8390b335 AS |
4585 | rtx x; |
4586 | struct m68k_address addr; | |
4587 | rtx unspec; | |
7b0f476d | 4588 | |
33d67485 | 4589 | orig_x = delegitimize_mem_from_attrs (orig_x); |
8390b335 AS |
4590 | x = orig_x; |
4591 | if (MEM_P (x)) | |
4592 | x = XEXP (x, 0); | |
4593 | ||
4594 | if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) | |
33d67485 AS |
4595 | return orig_x; |
4596 | ||
8390b335 AS |
4597 | if (!m68k_decompose_address (GET_MODE (x), x, false, &addr) |
4598 | || addr.offset == NULL_RTX | |
4599 | || GET_CODE (addr.offset) != CONST) | |
4600 | return orig_x; | |
7b0f476d | 4601 | |
8390b335 AS |
4602 | unspec = XEXP (addr.offset, 0); |
4603 | if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1))) | |
4604 | unspec = XEXP (unspec, 0); | |
4605 | if (GET_CODE (unspec) != UNSPEC | |
4606 | || (XINT (unspec, 1) != UNSPEC_RELOC16 | |
4607 | && XINT (unspec, 1) != UNSPEC_RELOC32)) | |
4608 | return orig_x; | |
4609 | x = XVECEXP (unspec, 0, 0); | |
92cf7399 | 4610 | gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF); |
8390b335 AS |
4611 | if (unspec != XEXP (addr.offset, 0)) |
4612 | x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1)); | |
4613 | if (addr.index) | |
7b0f476d | 4614 | { |
8390b335 AS |
4615 | rtx idx = addr.index; |
4616 | if (addr.scale != 1) | |
4617 | idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale)); | |
4618 | x = gen_rtx_PLUS (Pmode, idx, x); | |
7b0f476d | 4619 | } |
8390b335 AS |
4620 | if (addr.base) |
4621 | x = gen_rtx_PLUS (Pmode, addr.base, x); | |
4622 | if (MEM_P (orig_x)) | |
4623 | x = replace_equiv_address_nv (orig_x, x); | |
4624 | return x; | |
7b0f476d AS |
4625 | } |
4626 | ||
79e68feb RS |
4627 | \f |
4628 | /* A C compound statement to output to stdio stream STREAM the | |
4629 | assembler syntax for an instruction operand that is a memory | |
4630 | reference whose address is ADDR. ADDR is an RTL expression. | |
4631 | ||
4632 | Note that this contains a kludge that knows that the only reason | |
4633 | we have an address (plus (label_ref...) (reg...)) when not generating | |
4634 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
4635 | generates a label LInnn: on such an insn. | |
4636 | ||
4637 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
4638 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
4639 | ||
79e68feb RS |
4640 | This routine is responsible for distinguishing between -fpic and -fPIC |
4641 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
4642 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
4643 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb RS |
4644 | |
4645 | void | |
8a4a2253 | 4646 | print_operand_address (FILE *file, rtx addr) |
79e68feb | 4647 | { |
fc2241eb RS |
4648 | struct m68k_address address; |
4649 | ||
4650 | if (!m68k_decompose_address (QImode, addr, true, &address)) | |
4651 | gcc_unreachable (); | |
4652 | ||
4653 | if (address.code == PRE_DEC) | |
4b3d1177 KH |
4654 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", |
4655 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb | 4656 | else if (address.code == POST_INC) |
4b3d1177 KH |
4657 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", |
4658 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb RS |
4659 | else if (!address.base && !address.index) |
4660 | { | |
4661 | /* A constant address. */ | |
4662 | gcc_assert (address.offset == addr); | |
4663 | if (GET_CODE (addr) == CONST_INT) | |
4664 | { | |
4665 | /* (xxx).w or (xxx).l. */ | |
4666 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
4b3d1177 | 4667 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); |
a0a7fbc9 | 4668 | else |
fc2241eb | 4669 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
a0a7fbc9 | 4670 | } |
fc2241eb | 4671 | else if (TARGET_PCREL) |
a0a7fbc9 | 4672 | { |
fc2241eb RS |
4673 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
4674 | fputc ('(', file); | |
4675 | output_addr_const (file, addr); | |
4676 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
a0a7fbc9 | 4677 | } |
fc2241eb | 4678 | else |
a0a7fbc9 | 4679 | { |
fc2241eb RS |
4680 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
4681 | name ends in `.<letter>', as the last 2 characters can be | |
4682 | mistaken as a size suffix. Put the name in parentheses. */ | |
4683 | if (GET_CODE (addr) == SYMBOL_REF | |
4684 | && strlen (XSTR (addr, 0)) > 2 | |
4685 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
a0a7fbc9 | 4686 | { |
fc2241eb RS |
4687 | putc ('(', file); |
4688 | output_addr_const (file, addr); | |
4689 | putc (')', file); | |
a0a7fbc9 AS |
4690 | } |
4691 | else | |
fc2241eb | 4692 | output_addr_const (file, addr); |
a0a7fbc9 | 4693 | } |
fc2241eb RS |
4694 | } |
4695 | else | |
4696 | { | |
4697 | int labelno; | |
4698 | ||
4699 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
44c7bd63 | 4700 | label being accessed, otherwise it is -1. */ |
fc2241eb RS |
4701 | labelno = (address.offset |
4702 | && !address.base | |
4703 | && GET_CODE (address.offset) == LABEL_REF | |
4704 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
4705 | : -1); | |
4706 | if (MOTOROLA) | |
a0a7fbc9 | 4707 | { |
fc2241eb RS |
4708 | /* Print the "offset(base" component. */ |
4709 | if (labelno >= 0) | |
e59d83aa | 4710 | asm_fprintf (file, "%LL%d(%Rpc,", labelno); |
fc2241eb | 4711 | else |
a0a7fbc9 | 4712 | { |
fc2241eb | 4713 | if (address.offset) |
75df395f MK |
4714 | output_addr_const (file, address.offset); |
4715 | ||
fc2241eb RS |
4716 | putc ('(', file); |
4717 | if (address.base) | |
4718 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
a0a7fbc9 | 4719 | } |
fc2241eb RS |
4720 | /* Print the ",index" component, if any. */ |
4721 | if (address.index) | |
a0a7fbc9 | 4722 | { |
fc2241eb RS |
4723 | if (address.base) |
4724 | putc (',', file); | |
4725 | fprintf (file, "%s.%c", | |
4726 | M68K_REGNAME (REGNO (address.index)), | |
4727 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
4728 | if (address.scale != 1) | |
4729 | fprintf (file, "*%d", address.scale); | |
a0a7fbc9 | 4730 | } |
a0a7fbc9 | 4731 | putc (')', file); |
a0a7fbc9 | 4732 | } |
fc2241eb | 4733 | else /* !MOTOROLA */ |
a0a7fbc9 | 4734 | { |
fc2241eb RS |
4735 | if (!address.offset && !address.index) |
4736 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
a0a7fbc9 | 4737 | else |
a0a7fbc9 | 4738 | { |
fc2241eb RS |
4739 | /* Print the "base@(offset" component. */ |
4740 | if (labelno >= 0) | |
e59d83aa | 4741 | asm_fprintf (file, "%Rpc@(%LL%d", labelno); |
fc2241eb RS |
4742 | else |
4743 | { | |
4744 | if (address.base) | |
4745 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
4746 | fprintf (file, "@("); | |
4747 | if (address.offset) | |
75df395f | 4748 | output_addr_const (file, address.offset); |
fc2241eb RS |
4749 | } |
4750 | /* Print the ",index" component, if any. */ | |
4751 | if (address.index) | |
4752 | { | |
4753 | fprintf (file, ",%s:%c", | |
4754 | M68K_REGNAME (REGNO (address.index)), | |
4755 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
4756 | if (address.scale != 1) | |
4757 | fprintf (file, ":%d", address.scale); | |
4758 | } | |
a0a7fbc9 AS |
4759 | putc (')', file); |
4760 | } | |
a0a7fbc9 | 4761 | } |
79e68feb RS |
4762 | } |
4763 | } | |
af13f02d JW |
4764 | \f |
4765 | /* Check for cases where a clr insns can be omitted from code using | |
4766 | strict_low_part sets. For example, the second clrl here is not needed: | |
4767 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
4768 | ||
4769 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
4770 | insn we are checking for redundancy. TARGET is the register set by the | |
4771 | clear insn. */ | |
4772 | ||
8a4a2253 BI |
4773 | bool |
4774 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
4775 | rtx target) | |
af13f02d | 4776 | { |
39250081 | 4777 | rtx p = first_insn; |
af13f02d | 4778 | |
39250081 | 4779 | while ((p = PREV_INSN (p))) |
af13f02d | 4780 | { |
39250081 RZ |
4781 | if (NOTE_INSN_BASIC_BLOCK_P (p)) |
4782 | return false; | |
4783 | ||
4784 | if (NOTE_P (p)) | |
4785 | continue; | |
4786 | ||
af13f02d | 4787 | /* If it isn't an insn, then give up. */ |
39250081 | 4788 | if (!INSN_P (p)) |
8a4a2253 | 4789 | return false; |
af13f02d JW |
4790 | |
4791 | if (reg_set_p (target, p)) | |
4792 | { | |
4793 | rtx set = single_set (p); | |
4794 | rtx dest; | |
4795 | ||
4796 | /* If it isn't an easy to recognize insn, then give up. */ | |
4797 | if (! set) | |
8a4a2253 | 4798 | return false; |
af13f02d JW |
4799 | |
4800 | dest = SET_DEST (set); | |
4801 | ||
4802 | /* If this sets the entire target register to zero, then our | |
4803 | first_insn is redundant. */ | |
4804 | if (rtx_equal_p (dest, target) | |
4805 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 4806 | return true; |
af13f02d JW |
4807 | else if (GET_CODE (dest) == STRICT_LOW_PART |
4808 | && GET_CODE (XEXP (dest, 0)) == REG | |
4809 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
4810 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
4811 | <= GET_MODE_SIZE (mode))) | |
4812 | /* This is a strict low part set which modifies less than | |
4813 | we are using, so it is safe. */ | |
4814 | ; | |
4815 | else | |
8a4a2253 | 4816 | return false; |
af13f02d | 4817 | } |
af13f02d JW |
4818 | } |
4819 | ||
8a4a2253 | 4820 | return false; |
af13f02d | 4821 | } |
67cd4f83 | 4822 | |
2c8ec431 DL |
4823 | /* Operand predicates for implementing asymmetric pc-relative addressing |
4824 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 4825 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
4826 | |
4827 | We model this by restricting the meaning of the basic predicates | |
4828 | (general_operand, memory_operand, etc) to forbid the use of this | |
4829 | addressing mode, and then define the following predicates that permit | |
4830 | this addressing mode. These predicates can then be used for the | |
4831 | source operands of the appropriate instructions. | |
4832 | ||
4833 | n.b. While it is theoretically possible to change all machine patterns | |
4834 | to use this addressing more where permitted by the architecture, | |
4835 | it has only been implemented for "common" cases: SImode, HImode, and | |
4836 | QImode operands, and only for the principle operations that would | |
4837 | require this addressing mode: data movement and simple integer operations. | |
4838 | ||
4839 | In parallel with these new predicates, two new constraint letters | |
4840 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
4841 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
4842 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
4843 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
4844 | of how these constraints are used. | |
4845 | ||
4846 | The use of these predicates is strictly optional, though patterns that | |
4847 | don't will cause an extra reload register to be allocated where one | |
4848 | was not necessary: | |
4849 | ||
4850 | lea (abc:w,%pc),%a0 ; need to reload address | |
4851 | moveq &1,%d1 ; since write to pc-relative space | |
4852 | movel %d1,%a0@ ; is not allowed | |
4853 | ... | |
4854 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
4855 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
4856 | ||
4857 | For more info, consult tiemann@cygnus.com. | |
4858 | ||
4859 | ||
4860 | All of the ugliness with predicates and constraints is due to the | |
4861 | simple fact that the m68k does not allow a pc-relative addressing | |
4862 | mode as a destination. gcc does not distinguish between source and | |
4863 | destination addresses. Hence, if we claim that pc-relative address | |
331d9186 | 4864 | modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we |
2c8ec431 DL |
4865 | end up with invalid code. To get around this problem, we left |
4866 | pc-relative modes as invalid addresses, and then added special | |
4867 | predicates and constraints to accept them. | |
4868 | ||
4869 | A cleaner way to handle this is to modify gcc to distinguish | |
4870 | between source and destination addresses. We can then say that | |
4871 | pc-relative is a valid source address but not a valid destination | |
4872 | address, and hopefully avoid a lot of the predicate and constraint | |
4873 | hackery. Unfortunately, this would be a pretty big change. It would | |
4874 | be a useful change for a number of ports, but there aren't any current | |
4875 | plans to undertake this. | |
4876 | ||
4877 | ***************************************************************************/ | |
4878 | ||
4879 | ||
5505f548 | 4880 | const char * |
8a4a2253 | 4881 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
4882 | { |
4883 | int logval; | |
4884 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 4885 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
4886 | && (DATA_REG_P (operands[0]) |
4887 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4888 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4889 | { |
4890 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4891 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 4892 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
4893 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4894 | CC_STATUS_INIT; | |
4895 | if (operands[2] == const0_rtx) | |
4896 | return "clr%.w %0"; | |
4897 | return "and%.w %2,%0"; | |
4898 | } | |
4899 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 4900 | && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
4901 | && (DATA_REG_P (operands[0]) |
4902 | || offsettable_memref_p (operands[0]))) | |
4903 | { | |
4904 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 4905 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4906 | else |
4907 | { | |
b72f00af | 4908 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4909 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4910 | } |
4911 | /* This does not set condition codes in a standard way. */ | |
4912 | CC_STATUS_INIT; | |
4913 | return "bclr %1,%0"; | |
4914 | } | |
4915 | return "and%.l %2,%0"; | |
4916 | } | |
4917 | ||
5505f548 | 4918 | const char * |
8a4a2253 | 4919 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
4920 | { |
4921 | register int logval; | |
4922 | if (GET_CODE (operands[2]) == CONST_INT | |
4923 | && INTVAL (operands[2]) >> 16 == 0 | |
4924 | && (DATA_REG_P (operands[0]) | |
4925 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4926 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4927 | { |
4928 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4929 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4930 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4931 | CC_STATUS_INIT; | |
4932 | if (INTVAL (operands[2]) == 0xffff) | |
4933 | return "mov%.w %2,%0"; | |
4934 | return "or%.w %2,%0"; | |
4935 | } | |
4936 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 4937 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
4938 | && (DATA_REG_P (operands[0]) |
4939 | || offsettable_memref_p (operands[0]))) | |
4940 | { | |
4941 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4942 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4943 | else |
4944 | { | |
b72f00af | 4945 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4946 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4947 | } |
4948 | CC_STATUS_INIT; | |
4949 | return "bset %1,%0"; | |
4950 | } | |
4951 | return "or%.l %2,%0"; | |
4952 | } | |
4953 | ||
5505f548 | 4954 | const char * |
8a4a2253 | 4955 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
4956 | { |
4957 | register int logval; | |
4958 | if (GET_CODE (operands[2]) == CONST_INT | |
4959 | && INTVAL (operands[2]) >> 16 == 0 | |
4960 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 4961 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4962 | { |
4963 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 4964 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4965 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4966 | CC_STATUS_INIT; | |
4967 | if (INTVAL (operands[2]) == 0xffff) | |
4968 | return "not%.w %0"; | |
4969 | return "eor%.w %2,%0"; | |
4970 | } | |
4971 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 4972 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
4973 | && (DATA_REG_P (operands[0]) |
4974 | || offsettable_memref_p (operands[0]))) | |
4975 | { | |
4976 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4977 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4978 | else |
4979 | { | |
b72f00af | 4980 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4981 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4982 | } |
4983 | CC_STATUS_INIT; | |
4984 | return "bchg %1,%0"; | |
4985 | } | |
4986 | return "eor%.l %2,%0"; | |
4987 | } | |
7c262518 | 4988 | |
29ca003a RS |
4989 | /* Return the instruction that should be used for a call to address X, |
4990 | which is known to be in operand 0. */ | |
4991 | ||
4992 | const char * | |
4993 | output_call (rtx x) | |
4994 | { | |
4995 | if (symbolic_operand (x, VOIDmode)) | |
4996 | return m68k_symbolic_call; | |
4997 | else | |
4998 | return "jsr %a0"; | |
4999 | } | |
5000 | ||
f7e70894 RS |
5001 | /* Likewise sibling calls. */ |
5002 | ||
5003 | const char * | |
5004 | output_sibcall (rtx x) | |
5005 | { | |
5006 | if (symbolic_operand (x, VOIDmode)) | |
5007 | return m68k_symbolic_jump; | |
5008 | else | |
5009 | return "jmp %a0"; | |
5010 | } | |
5011 | ||
c590b625 | 5012 | static void |
8a4a2253 | 5013 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
4ab870f5 | 5014 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
8a4a2253 | 5015 | tree function) |
483ab821 | 5016 | { |
e0601576 RH |
5017 | rtx this_slot, offset, addr, mem, insn, tmp; |
5018 | ||
5019 | /* Avoid clobbering the struct value reg by using the | |
5020 | static chain reg as a temporary. */ | |
5021 | tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4ab870f5 RS |
5022 | |
5023 | /* Pretend to be a post-reload pass while generating rtl. */ | |
4ab870f5 | 5024 | reload_completed = 1; |
4ab870f5 RS |
5025 | |
5026 | /* The "this" pointer is stored at 4(%sp). */ | |
5027 | this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4)); | |
5028 | ||
5029 | /* Add DELTA to THIS. */ | |
5030 | if (delta != 0) | |
5050d266 | 5031 | { |
4ab870f5 RS |
5032 | /* Make the offset a legitimate operand for memory addition. */ |
5033 | offset = GEN_INT (delta); | |
5034 | if ((delta < -8 || delta > 8) | |
5035 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
5036 | { | |
5037 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
5038 | offset = gen_rtx_REG (Pmode, D0_REG); | |
5039 | } | |
5040 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5041 | copy_rtx (this_slot), offset)); | |
5050d266 | 5042 | } |
c590b625 | 5043 | |
4ab870f5 RS |
5044 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
5045 | if (vcall_offset != 0) | |
5046 | { | |
5047 | /* Set the static chain register to *THIS. */ | |
e0601576 RH |
5048 | emit_move_insn (tmp, this_slot); |
5049 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
4ab870f5 RS |
5050 | |
5051 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
e0601576 | 5052 | addr = plus_constant (tmp, vcall_offset); |
4ab870f5 RS |
5053 | if (!m68k_legitimate_address_p (Pmode, addr, true)) |
5054 | { | |
e0601576 RH |
5055 | emit_insn (gen_rtx_SET (VOIDmode, tmp, addr)); |
5056 | addr = tmp; | |
4ab870f5 | 5057 | } |
c590b625 | 5058 | |
4ab870f5 RS |
5059 | /* Load the offset into %d0 and add it to THIS. */ |
5060 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
5061 | gen_rtx_MEM (Pmode, addr)); | |
5062 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5063 | copy_rtx (this_slot), | |
5064 | gen_rtx_REG (Pmode, D0_REG))); | |
5065 | } | |
29ca003a | 5066 | |
4ab870f5 RS |
5067 | /* Jump to the target function. Use a sibcall if direct jumps are |
5068 | allowed, otherwise load the address into a register first. */ | |
5069 | mem = DECL_RTL (function); | |
5070 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
5071 | { | |
5072 | gcc_assert (flag_pic); | |
c590b625 | 5073 | |
4ab870f5 RS |
5074 | if (!TARGET_SEP_DATA) |
5075 | { | |
5076 | /* Use the static chain register as a temporary (call-clobbered) | |
5077 | GOT pointer for this function. We can use the static chain | |
5078 | register because it isn't live on entry to the thunk. */ | |
6fb5fa3c | 5079 | SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); |
4ab870f5 RS |
5080 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
5081 | } | |
e0601576 RH |
5082 | legitimize_pic_address (XEXP (mem, 0), Pmode, tmp); |
5083 | mem = replace_equiv_address (mem, tmp); | |
4ab870f5 RS |
5084 | } |
5085 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
5086 | SIBLING_CALL_P (insn) = 1; | |
5087 | ||
5088 | /* Run just enough of rest_of_compilation. */ | |
5089 | insn = get_insns (); | |
5090 | split_all_insns_noflow (); | |
5091 | final_start_function (insn, file, 1); | |
5092 | final (insn, file, 1); | |
5093 | final_end_function (); | |
5094 | ||
5095 | /* Clean up the vars set above. */ | |
5096 | reload_completed = 0; | |
4ab870f5 RS |
5097 | |
5098 | /* Restore the original PIC register. */ | |
5099 | if (flag_pic) | |
6fb5fa3c | 5100 | SET_REGNO (pic_offset_table_rtx, PIC_REG); |
483ab821 | 5101 | } |
8636be86 KH |
5102 | |
5103 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
5104 | ||
5105 | static rtx | |
5106 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
5107 | int incoming ATTRIBUTE_UNUSED) | |
5108 | { | |
5109 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
5110 | } | |
cfca21cb PB |
5111 | |
5112 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
5113 | int | |
5114 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5115 | unsigned int new_reg) | |
5116 | { | |
5117 | ||
5118 | /* Interrupt functions can only use registers that have already been | |
5119 | saved by the prologue, even if they would normally be | |
5120 | call-clobbered. */ | |
5121 | ||
a4242737 KH |
5122 | if ((m68k_get_function_kind (current_function_decl) |
5123 | == m68k_fk_interrupt_handler) | |
6fb5fa3c | 5124 | && !df_regs_ever_live_p (new_reg)) |
cfca21cb PB |
5125 | return 0; |
5126 | ||
5127 | return 1; | |
5128 | } | |
70028b61 | 5129 | |
ffa2596e RS |
5130 | /* Value is true if hard register REGNO can hold a value of machine-mode |
5131 | MODE. On the 68000, we let the cpu registers can hold any mode, but | |
5132 | restrict the 68881 registers to floating-point modes. */ | |
5133 | ||
70028b61 PB |
5134 | bool |
5135 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
5136 | { | |
36e04090 | 5137 | if (DATA_REGNO_P (regno)) |
70028b61 | 5138 | { |
a0a7fbc9 AS |
5139 | /* Data Registers, can hold aggregate if fits in. */ |
5140 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
5141 | return true; | |
70028b61 | 5142 | } |
36e04090 | 5143 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 5144 | { |
a0a7fbc9 AS |
5145 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
5146 | return true; | |
70028b61 | 5147 | } |
36e04090 | 5148 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
5149 | { |
5150 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
5151 | smaller. */ |
5152 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5153 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 5154 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 5155 | return true; |
70028b61 PB |
5156 | } |
5157 | return false; | |
5158 | } | |
dcc21c4c | 5159 | |
ffa2596e RS |
5160 | /* Implement SECONDARY_RELOAD_CLASS. */ |
5161 | ||
5162 | enum reg_class | |
5163 | m68k_secondary_reload_class (enum reg_class rclass, | |
5164 | enum machine_mode mode, rtx x) | |
5165 | { | |
5166 | int regno; | |
5167 | ||
5168 | regno = true_regnum (x); | |
5169 | ||
5170 | /* If one operand of a movqi is an address register, the other | |
5171 | operand must be a general register or constant. Other types | |
5172 | of operand must be reloaded through a data register. */ | |
5173 | if (GET_MODE_SIZE (mode) == 1 | |
5174 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
5175 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
5176 | return DATA_REGS; | |
5177 | ||
5178 | /* PC-relative addresses must be loaded into an address register first. */ | |
5179 | if (TARGET_PCREL | |
5180 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
5181 | && symbolic_operand (x, VOIDmode)) | |
5182 | return ADDR_REGS; | |
5183 | ||
5184 | return NO_REGS; | |
5185 | } | |
5186 | ||
5187 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
5188 | ||
5189 | enum reg_class | |
5190 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
5191 | { | |
5192 | enum reg_class secondary_class; | |
5193 | ||
5194 | /* If RCLASS might need a secondary reload, try restricting it to | |
5195 | a class that doesn't. */ | |
5196 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
5197 | if (secondary_class != NO_REGS | |
5198 | && reg_class_subset_p (secondary_class, rclass)) | |
5199 | return secondary_class; | |
5200 | ||
5201 | /* Prefer to use moveq for in-range constants. */ | |
5202 | if (GET_CODE (x) == CONST_INT | |
5203 | && reg_class_subset_p (DATA_REGS, rclass) | |
5204 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
5205 | return DATA_REGS; | |
5206 | ||
5207 | /* ??? Do we really need this now? */ | |
5208 | if (GET_CODE (x) == CONST_DOUBLE | |
5209 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
5210 | { | |
5211 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
5212 | return FP_REGS; | |
5213 | ||
5214 | return NO_REGS; | |
5215 | } | |
5216 | ||
5217 | return rclass; | |
5218 | } | |
5219 | ||
dcc21c4c PB |
5220 | /* Return floating point values in a 68881 register. This makes 68881 code |
5221 | a little bit faster. It also makes -msoft-float code incompatible with | |
5222 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 5223 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
5224 | If there is need for a hard-float ABI it is probably worth doing it |
5225 | properly and also passing function arguments in FP registers. */ | |
5226 | rtx | |
5227 | m68k_libcall_value (enum machine_mode mode) | |
5228 | { | |
5229 | switch (mode) { | |
5230 | case SFmode: | |
5231 | case DFmode: | |
5232 | case XFmode: | |
5233 | if (TARGET_68881) | |
8d989403 | 5234 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
5235 | break; |
5236 | default: | |
5237 | break; | |
5238 | } | |
75df395f MK |
5239 | |
5240 | return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG); | |
dcc21c4c PB |
5241 | } |
5242 | ||
db5e2d51 MK |
5243 | /* Location in which function value is returned. |
5244 | NOTE: Due to differences in ABIs, don't call this function directly, | |
5245 | use FUNCTION_VALUE instead. */ | |
dcc21c4c | 5246 | rtx |
586de218 | 5247 | m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
dcc21c4c PB |
5248 | { |
5249 | enum machine_mode mode; | |
5250 | ||
5251 | mode = TYPE_MODE (valtype); | |
5252 | switch (mode) { | |
5253 | case SFmode: | |
5254 | case DFmode: | |
5255 | case XFmode: | |
5256 | if (TARGET_68881) | |
8d989403 | 5257 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
5258 | break; |
5259 | default: | |
5260 | break; | |
5261 | } | |
5262 | ||
576c9028 KH |
5263 | /* If the function returns a pointer, push that into %a0. */ |
5264 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
5265 | /* For compatibility with the large body of existing code which | |
5266 | does not always properly declare external functions returning | |
5267 | pointer types, the m68k/SVR4 convention is to copy the value | |
5268 | returned for pointer functions from a0 to d0 in the function | |
5269 | epilogue, so that callers that have neglected to properly | |
5270 | declare the callee can still find the correct return value in | |
5271 | d0. */ | |
5272 | return gen_rtx_PARALLEL | |
5273 | (mode, | |
5274 | gen_rtvec (2, | |
5275 | gen_rtx_EXPR_LIST (VOIDmode, | |
5276 | gen_rtx_REG (mode, A0_REG), | |
5277 | const0_rtx), | |
5278 | gen_rtx_EXPR_LIST (VOIDmode, | |
5279 | gen_rtx_REG (mode, D0_REG), | |
5280 | const0_rtx))); | |
5281 | else if (POINTER_TYPE_P (valtype)) | |
5282 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 5283 | else |
576c9028 | 5284 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 5285 | } |
1c445f03 NS |
5286 | |
5287 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
5288 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT | |
5289 | static bool | |
511e41e5 | 5290 | m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
1c445f03 NS |
5291 | { |
5292 | enum machine_mode mode = TYPE_MODE (type); | |
5293 | ||
5294 | if (mode == BLKmode) | |
5295 | return true; | |
5296 | ||
5297 | /* If TYPE's known alignment is less than the alignment of MODE that | |
5298 | would contain the structure, then return in memory. We need to | |
5299 | do so to maintain the compatibility between code compiled with | |
5300 | -mstrict-align and that compiled with -mno-strict-align. */ | |
5301 | if (AGGREGATE_TYPE_P (type) | |
5302 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) | |
5303 | return true; | |
5304 | ||
5305 | return false; | |
5306 | } | |
5307 | #endif | |
c47b0cb4 MK |
5308 | |
5309 | /* CPU to schedule the program for. */ | |
5310 | enum attr_cpu m68k_sched_cpu; | |
5311 | ||
826fadba MK |
5312 | /* MAC to schedule the program for. */ |
5313 | enum attr_mac m68k_sched_mac; | |
5314 | ||
c47b0cb4 MK |
5315 | /* Operand type. */ |
5316 | enum attr_op_type | |
5317 | { | |
5318 | /* No operand. */ | |
5319 | OP_TYPE_NONE, | |
5320 | ||
96fcacb7 MK |
5321 | /* Integer register. */ |
5322 | OP_TYPE_RN, | |
5323 | ||
5324 | /* FP register. */ | |
5325 | OP_TYPE_FPN, | |
c47b0cb4 MK |
5326 | |
5327 | /* Implicit mem reference (e.g. stack). */ | |
5328 | OP_TYPE_MEM1, | |
5329 | ||
5330 | /* Memory without offset or indexing. EA modes 2, 3 and 4. */ | |
5331 | OP_TYPE_MEM234, | |
5332 | ||
5333 | /* Memory with offset but without indexing. EA mode 5. */ | |
5334 | OP_TYPE_MEM5, | |
5335 | ||
5336 | /* Memory with indexing. EA mode 6. */ | |
5337 | OP_TYPE_MEM6, | |
5338 | ||
5339 | /* Memory referenced by absolute address. EA mode 7. */ | |
5340 | OP_TYPE_MEM7, | |
5341 | ||
5342 | /* Immediate operand that doesn't require extension word. */ | |
5343 | OP_TYPE_IMM_Q, | |
5344 | ||
5345 | /* Immediate 16 bit operand. */ | |
5346 | OP_TYPE_IMM_W, | |
5347 | ||
5348 | /* Immediate 32 bit operand. */ | |
5349 | OP_TYPE_IMM_L | |
5350 | }; | |
5351 | ||
c47b0cb4 MK |
5352 | /* Return type of memory ADDR_RTX refers to. */ |
5353 | static enum attr_op_type | |
5354 | sched_address_type (enum machine_mode mode, rtx addr_rtx) | |
5355 | { | |
5356 | struct m68k_address address; | |
5357 | ||
96fcacb7 MK |
5358 | if (symbolic_operand (addr_rtx, VOIDmode)) |
5359 | return OP_TYPE_MEM7; | |
5360 | ||
c47b0cb4 MK |
5361 | if (!m68k_decompose_address (mode, addr_rtx, |
5362 | reload_completed, &address)) | |
5363 | { | |
96fcacb7 | 5364 | gcc_assert (!reload_completed); |
c47b0cb4 MK |
5365 | /* Reload will likely fix the address to be in the register. */ |
5366 | return OP_TYPE_MEM234; | |
5367 | } | |
5368 | ||
5369 | if (address.scale != 0) | |
5370 | return OP_TYPE_MEM6; | |
5371 | ||
5372 | if (address.base != NULL_RTX) | |
5373 | { | |
5374 | if (address.offset == NULL_RTX) | |
5375 | return OP_TYPE_MEM234; | |
5376 | ||
5377 | return OP_TYPE_MEM5; | |
5378 | } | |
5379 | ||
5380 | gcc_assert (address.offset != NULL_RTX); | |
5381 | ||
5382 | return OP_TYPE_MEM7; | |
5383 | } | |
5384 | ||
96fcacb7 MK |
5385 | /* Return X or Y (depending on OPX_P) operand of INSN. */ |
5386 | static rtx | |
5387 | sched_get_operand (rtx insn, bool opx_p) | |
5388 | { | |
5389 | int i; | |
5390 | ||
5391 | if (recog_memoized (insn) < 0) | |
5392 | gcc_unreachable (); | |
5393 | ||
5394 | extract_constrain_insn_cached (insn); | |
5395 | ||
5396 | if (opx_p) | |
5397 | i = get_attr_opx (insn); | |
5398 | else | |
5399 | i = get_attr_opy (insn); | |
5400 | ||
5401 | if (i >= recog_data.n_operands) | |
5402 | return NULL; | |
5403 | ||
5404 | return recog_data.operand[i]; | |
5405 | } | |
5406 | ||
5407 | /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). | |
5408 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
c47b0cb4 | 5409 | static enum attr_op_type |
96fcacb7 | 5410 | sched_attr_op_type (rtx insn, bool opx_p, bool address_p) |
c47b0cb4 | 5411 | { |
96fcacb7 MK |
5412 | rtx op; |
5413 | ||
5414 | op = sched_get_operand (insn, opx_p); | |
5415 | ||
5416 | if (op == NULL) | |
5417 | { | |
5418 | gcc_assert (!reload_completed); | |
5419 | return OP_TYPE_RN; | |
5420 | } | |
c47b0cb4 MK |
5421 | |
5422 | if (address_p) | |
5423 | return sched_address_type (QImode, op); | |
5424 | ||
5425 | if (memory_operand (op, VOIDmode)) | |
5426 | return sched_address_type (GET_MODE (op), XEXP (op, 0)); | |
5427 | ||
5428 | if (register_operand (op, VOIDmode)) | |
96fcacb7 MK |
5429 | { |
5430 | if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op))) | |
5431 | || (reload_completed && FP_REG_P (op))) | |
5432 | return OP_TYPE_FPN; | |
5433 | ||
5434 | return OP_TYPE_RN; | |
5435 | } | |
c47b0cb4 MK |
5436 | |
5437 | if (GET_CODE (op) == CONST_INT) | |
5438 | { | |
96fcacb7 MK |
5439 | int ival; |
5440 | ||
5441 | ival = INTVAL (op); | |
5442 | ||
5443 | /* Check for quick constants. */ | |
5444 | switch (get_attr_type (insn)) | |
5445 | { | |
5446 | case TYPE_ALUQ_L: | |
5447 | if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1)) | |
5448 | return OP_TYPE_IMM_Q; | |
5449 | ||
5450 | gcc_assert (!reload_completed); | |
5451 | break; | |
5452 | ||
5453 | case TYPE_MOVEQ_L: | |
5454 | if (USE_MOVQ (ival)) | |
5455 | return OP_TYPE_IMM_Q; | |
5456 | ||
5457 | gcc_assert (!reload_completed); | |
5458 | break; | |
5459 | ||
5460 | case TYPE_MOV3Q_L: | |
5461 | if (valid_mov3q_const (ival)) | |
5462 | return OP_TYPE_IMM_Q; | |
5463 | ||
5464 | gcc_assert (!reload_completed); | |
5465 | break; | |
5466 | ||
5467 | default: | |
5468 | break; | |
5469 | } | |
5470 | ||
5471 | if (IN_RANGE (ival, -0x8000, 0x7fff)) | |
c47b0cb4 MK |
5472 | return OP_TYPE_IMM_W; |
5473 | ||
5474 | return OP_TYPE_IMM_L; | |
5475 | } | |
5476 | ||
5477 | if (GET_CODE (op) == CONST_DOUBLE) | |
5478 | { | |
5479 | switch (GET_MODE (op)) | |
5480 | { | |
5481 | case SFmode: | |
5482 | return OP_TYPE_IMM_W; | |
5483 | ||
5484 | case VOIDmode: | |
5485 | case DFmode: | |
5486 | return OP_TYPE_IMM_L; | |
5487 | ||
5488 | default: | |
5489 | gcc_unreachable (); | |
5490 | } | |
5491 | } | |
5492 | ||
00b2ef14 MK |
5493 | if (GET_CODE (op) == CONST |
5494 | || symbolic_operand (op, VOIDmode) | |
c47b0cb4 MK |
5495 | || LABEL_P (op)) |
5496 | { | |
5497 | switch (GET_MODE (op)) | |
5498 | { | |
5499 | case QImode: | |
5500 | return OP_TYPE_IMM_Q; | |
5501 | ||
5502 | case HImode: | |
5503 | return OP_TYPE_IMM_W; | |
5504 | ||
5505 | case SImode: | |
5506 | return OP_TYPE_IMM_L; | |
5507 | ||
5508 | default: | |
75df395f MK |
5509 | if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode)) |
5510 | /* Just a guess. */ | |
c47b0cb4 MK |
5511 | return OP_TYPE_IMM_W; |
5512 | ||
5513 | return OP_TYPE_IMM_L; | |
5514 | } | |
5515 | } | |
5516 | ||
96fcacb7 | 5517 | gcc_assert (!reload_completed); |
c47b0cb4 | 5518 | |
96fcacb7 MK |
5519 | if (FLOAT_MODE_P (GET_MODE (op))) |
5520 | return OP_TYPE_FPN; | |
c47b0cb4 | 5521 | |
96fcacb7 | 5522 | return OP_TYPE_RN; |
c47b0cb4 MK |
5523 | } |
5524 | ||
5525 | /* Implement opx_type attribute. | |
5526 | Return type of INSN's operand X. | |
5527 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
5528 | enum attr_opx_type | |
5529 | m68k_sched_attr_opx_type (rtx insn, int address_p) | |
5530 | { | |
c47b0cb4 MK |
5531 | switch (sched_attr_op_type (insn, true, address_p != 0)) |
5532 | { | |
96fcacb7 MK |
5533 | case OP_TYPE_RN: |
5534 | return OPX_TYPE_RN; | |
5535 | ||
5536 | case OP_TYPE_FPN: | |
5537 | return OPX_TYPE_FPN; | |
c47b0cb4 MK |
5538 | |
5539 | case OP_TYPE_MEM1: | |
5540 | return OPX_TYPE_MEM1; | |
5541 | ||
5542 | case OP_TYPE_MEM234: | |
5543 | return OPX_TYPE_MEM234; | |
5544 | ||
5545 | case OP_TYPE_MEM5: | |
5546 | return OPX_TYPE_MEM5; | |
5547 | ||
5548 | case OP_TYPE_MEM6: | |
5549 | return OPX_TYPE_MEM6; | |
5550 | ||
5551 | case OP_TYPE_MEM7: | |
5552 | return OPX_TYPE_MEM7; | |
5553 | ||
5554 | case OP_TYPE_IMM_Q: | |
5555 | return OPX_TYPE_IMM_Q; | |
5556 | ||
5557 | case OP_TYPE_IMM_W: | |
5558 | return OPX_TYPE_IMM_W; | |
5559 | ||
5560 | case OP_TYPE_IMM_L: | |
5561 | return OPX_TYPE_IMM_L; | |
5562 | ||
5563 | default: | |
5564 | gcc_unreachable (); | |
c47b0cb4 MK |
5565 | } |
5566 | } | |
5567 | ||
5568 | /* Implement opy_type attribute. | |
5569 | Return type of INSN's operand Y. | |
5570 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
5571 | enum attr_opy_type | |
5572 | m68k_sched_attr_opy_type (rtx insn, int address_p) | |
5573 | { | |
c47b0cb4 MK |
5574 | switch (sched_attr_op_type (insn, false, address_p != 0)) |
5575 | { | |
96fcacb7 MK |
5576 | case OP_TYPE_RN: |
5577 | return OPY_TYPE_RN; | |
5578 | ||
5579 | case OP_TYPE_FPN: | |
5580 | return OPY_TYPE_FPN; | |
c47b0cb4 MK |
5581 | |
5582 | case OP_TYPE_MEM1: | |
5583 | return OPY_TYPE_MEM1; | |
5584 | ||
5585 | case OP_TYPE_MEM234: | |
5586 | return OPY_TYPE_MEM234; | |
5587 | ||
5588 | case OP_TYPE_MEM5: | |
5589 | return OPY_TYPE_MEM5; | |
5590 | ||
5591 | case OP_TYPE_MEM6: | |
5592 | return OPY_TYPE_MEM6; | |
5593 | ||
5594 | case OP_TYPE_MEM7: | |
5595 | return OPY_TYPE_MEM7; | |
5596 | ||
5597 | case OP_TYPE_IMM_Q: | |
5598 | return OPY_TYPE_IMM_Q; | |
5599 | ||
5600 | case OP_TYPE_IMM_W: | |
5601 | return OPY_TYPE_IMM_W; | |
5602 | ||
5603 | case OP_TYPE_IMM_L: | |
5604 | return OPY_TYPE_IMM_L; | |
5605 | ||
5606 | default: | |
5607 | gcc_unreachable (); | |
c47b0cb4 MK |
5608 | } |
5609 | } | |
5610 | ||
96fcacb7 MK |
5611 | /* Return size of INSN as int. */ |
5612 | static int | |
5613 | sched_get_attr_size_int (rtx insn) | |
c47b0cb4 MK |
5614 | { |
5615 | int size; | |
5616 | ||
96fcacb7 | 5617 | switch (get_attr_type (insn)) |
c47b0cb4 | 5618 | { |
96fcacb7 MK |
5619 | case TYPE_IGNORE: |
5620 | /* There should be no references to m68k_sched_attr_size for 'ignore' | |
5621 | instructions. */ | |
5622 | gcc_unreachable (); | |
5623 | return 0; | |
5624 | ||
5625 | case TYPE_MUL_L: | |
c47b0cb4 MK |
5626 | size = 2; |
5627 | break; | |
5628 | ||
5629 | default: | |
5630 | size = 1; | |
5631 | break; | |
5632 | } | |
5633 | ||
5634 | switch (get_attr_opx_type (insn)) | |
5635 | { | |
5636 | case OPX_TYPE_NONE: | |
96fcacb7 MK |
5637 | case OPX_TYPE_RN: |
5638 | case OPX_TYPE_FPN: | |
c47b0cb4 MK |
5639 | case OPX_TYPE_MEM1: |
5640 | case OPX_TYPE_MEM234: | |
5641 | case OPY_TYPE_IMM_Q: | |
5642 | break; | |
5643 | ||
5644 | case OPX_TYPE_MEM5: | |
5645 | case OPX_TYPE_MEM6: | |
5646 | /* Here we assume that most absolute references are short. */ | |
5647 | case OPX_TYPE_MEM7: | |
5648 | case OPY_TYPE_IMM_W: | |
5649 | ++size; | |
5650 | break; | |
5651 | ||
5652 | case OPY_TYPE_IMM_L: | |
5653 | size += 2; | |
5654 | break; | |
5655 | ||
5656 | default: | |
5657 | gcc_unreachable (); | |
5658 | } | |
5659 | ||
5660 | switch (get_attr_opy_type (insn)) | |
5661 | { | |
5662 | case OPY_TYPE_NONE: | |
96fcacb7 MK |
5663 | case OPY_TYPE_RN: |
5664 | case OPY_TYPE_FPN: | |
c47b0cb4 MK |
5665 | case OPY_TYPE_MEM1: |
5666 | case OPY_TYPE_MEM234: | |
5667 | case OPY_TYPE_IMM_Q: | |
5668 | break; | |
5669 | ||
5670 | case OPY_TYPE_MEM5: | |
5671 | case OPY_TYPE_MEM6: | |
5672 | /* Here we assume that most absolute references are short. */ | |
5673 | case OPY_TYPE_MEM7: | |
5674 | case OPY_TYPE_IMM_W: | |
5675 | ++size; | |
5676 | break; | |
5677 | ||
5678 | case OPY_TYPE_IMM_L: | |
5679 | size += 2; | |
5680 | break; | |
5681 | ||
5682 | default: | |
5683 | gcc_unreachable (); | |
5684 | } | |
5685 | ||
5686 | if (size > 3) | |
5687 | { | |
96fcacb7 | 5688 | gcc_assert (!reload_completed); |
c47b0cb4 MK |
5689 | |
5690 | size = 3; | |
5691 | } | |
5692 | ||
5693 | return size; | |
5694 | } | |
5695 | ||
96fcacb7 MK |
5696 | /* Return size of INSN as attribute enum value. */ |
5697 | enum attr_size | |
5698 | m68k_sched_attr_size (rtx insn) | |
5699 | { | |
5700 | switch (sched_get_attr_size_int (insn)) | |
5701 | { | |
5702 | case 1: | |
5703 | return SIZE_1; | |
5704 | ||
5705 | case 2: | |
5706 | return SIZE_2; | |
5707 | ||
5708 | case 3: | |
5709 | return SIZE_3; | |
5710 | ||
5711 | default: | |
5712 | gcc_unreachable (); | |
96fcacb7 MK |
5713 | } |
5714 | } | |
5715 | ||
5716 | /* Return operand X or Y (depending on OPX_P) of INSN, | |
5717 | if it is a MEM, or NULL overwise. */ | |
5718 | static enum attr_op_type | |
5719 | sched_get_opxy_mem_type (rtx insn, bool opx_p) | |
5720 | { | |
5721 | if (opx_p) | |
5722 | { | |
5723 | switch (get_attr_opx_type (insn)) | |
5724 | { | |
5725 | case OPX_TYPE_NONE: | |
5726 | case OPX_TYPE_RN: | |
5727 | case OPX_TYPE_FPN: | |
5728 | case OPX_TYPE_IMM_Q: | |
5729 | case OPX_TYPE_IMM_W: | |
5730 | case OPX_TYPE_IMM_L: | |
5731 | return OP_TYPE_RN; | |
5732 | ||
5733 | case OPX_TYPE_MEM1: | |
5734 | case OPX_TYPE_MEM234: | |
5735 | case OPX_TYPE_MEM5: | |
5736 | case OPX_TYPE_MEM7: | |
5737 | return OP_TYPE_MEM1; | |
5738 | ||
5739 | case OPX_TYPE_MEM6: | |
5740 | return OP_TYPE_MEM6; | |
5741 | ||
5742 | default: | |
5743 | gcc_unreachable (); | |
96fcacb7 MK |
5744 | } |
5745 | } | |
5746 | else | |
5747 | { | |
5748 | switch (get_attr_opy_type (insn)) | |
5749 | { | |
5750 | case OPY_TYPE_NONE: | |
5751 | case OPY_TYPE_RN: | |
5752 | case OPY_TYPE_FPN: | |
5753 | case OPY_TYPE_IMM_Q: | |
5754 | case OPY_TYPE_IMM_W: | |
5755 | case OPY_TYPE_IMM_L: | |
5756 | return OP_TYPE_RN; | |
5757 | ||
5758 | case OPY_TYPE_MEM1: | |
5759 | case OPY_TYPE_MEM234: | |
5760 | case OPY_TYPE_MEM5: | |
5761 | case OPY_TYPE_MEM7: | |
5762 | return OP_TYPE_MEM1; | |
5763 | ||
5764 | case OPY_TYPE_MEM6: | |
5765 | return OP_TYPE_MEM6; | |
5766 | ||
5767 | default: | |
5768 | gcc_unreachable (); | |
96fcacb7 MK |
5769 | } |
5770 | } | |
5771 | } | |
5772 | ||
c47b0cb4 MK |
5773 | /* Implement op_mem attribute. */ |
5774 | enum attr_op_mem | |
5775 | m68k_sched_attr_op_mem (rtx insn) | |
5776 | { | |
96fcacb7 MK |
5777 | enum attr_op_type opx; |
5778 | enum attr_op_type opy; | |
c47b0cb4 | 5779 | |
96fcacb7 MK |
5780 | opx = sched_get_opxy_mem_type (insn, true); |
5781 | opy = sched_get_opxy_mem_type (insn, false); | |
c47b0cb4 | 5782 | |
96fcacb7 | 5783 | if (opy == OP_TYPE_RN && opx == OP_TYPE_RN) |
c47b0cb4 MK |
5784 | return OP_MEM_00; |
5785 | ||
96fcacb7 | 5786 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
5787 | { |
5788 | switch (get_attr_opx_access (insn)) | |
5789 | { | |
5790 | case OPX_ACCESS_R: | |
5791 | return OP_MEM_10; | |
5792 | ||
5793 | case OPX_ACCESS_W: | |
5794 | return OP_MEM_01; | |
5795 | ||
5796 | case OPX_ACCESS_RW: | |
5797 | return OP_MEM_11; | |
5798 | ||
5799 | default: | |
96fcacb7 | 5800 | gcc_unreachable (); |
c47b0cb4 MK |
5801 | } |
5802 | } | |
5803 | ||
96fcacb7 | 5804 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6) |
c47b0cb4 MK |
5805 | { |
5806 | switch (get_attr_opx_access (insn)) | |
5807 | { | |
5808 | case OPX_ACCESS_R: | |
5809 | return OP_MEM_I0; | |
5810 | ||
5811 | case OPX_ACCESS_W: | |
5812 | return OP_MEM_0I; | |
5813 | ||
5814 | case OPX_ACCESS_RW: | |
5815 | return OP_MEM_I1; | |
5816 | ||
5817 | default: | |
96fcacb7 | 5818 | gcc_unreachable (); |
c47b0cb4 MK |
5819 | } |
5820 | } | |
5821 | ||
96fcacb7 | 5822 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN) |
c47b0cb4 MK |
5823 | return OP_MEM_10; |
5824 | ||
96fcacb7 | 5825 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
5826 | { |
5827 | switch (get_attr_opx_access (insn)) | |
5828 | { | |
5829 | case OPX_ACCESS_W: | |
5830 | return OP_MEM_11; | |
5831 | ||
5832 | default: | |
96fcacb7 MK |
5833 | gcc_assert (!reload_completed); |
5834 | return OP_MEM_11; | |
c47b0cb4 MK |
5835 | } |
5836 | } | |
5837 | ||
96fcacb7 | 5838 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6) |
c47b0cb4 MK |
5839 | { |
5840 | switch (get_attr_opx_access (insn)) | |
5841 | { | |
5842 | case OPX_ACCESS_W: | |
5843 | return OP_MEM_1I; | |
5844 | ||
5845 | default: | |
96fcacb7 MK |
5846 | gcc_assert (!reload_completed); |
5847 | return OP_MEM_1I; | |
c47b0cb4 MK |
5848 | } |
5849 | } | |
5850 | ||
96fcacb7 | 5851 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN) |
c47b0cb4 MK |
5852 | return OP_MEM_I0; |
5853 | ||
96fcacb7 | 5854 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
5855 | { |
5856 | switch (get_attr_opx_access (insn)) | |
5857 | { | |
5858 | case OPX_ACCESS_W: | |
5859 | return OP_MEM_I1; | |
5860 | ||
5861 | default: | |
96fcacb7 MK |
5862 | gcc_assert (!reload_completed); |
5863 | return OP_MEM_I1; | |
c47b0cb4 MK |
5864 | } |
5865 | } | |
5866 | ||
96fcacb7 MK |
5867 | gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6); |
5868 | gcc_assert (!reload_completed); | |
5869 | return OP_MEM_I1; | |
c47b0cb4 MK |
5870 | } |
5871 | ||
5872 | /* Jump instructions types. Indexed by INSN_UID. | |
5873 | The same rtl insn can be expanded into different asm instructions | |
5874 | depending on the cc0_status. To properly determine type of jump | |
5875 | instructions we scan instruction stream and map jumps types to this | |
5876 | array. */ | |
5877 | static enum attr_type *sched_branch_type; | |
5878 | ||
5879 | /* Return the type of the jump insn. */ | |
5880 | enum attr_type | |
5881 | m68k_sched_branch_type (rtx insn) | |
5882 | { | |
5883 | enum attr_type type; | |
5884 | ||
5885 | type = sched_branch_type[INSN_UID (insn)]; | |
5886 | ||
5887 | gcc_assert (type != 0); | |
5888 | ||
5889 | return type; | |
5890 | } | |
b8c96320 | 5891 | |
96fcacb7 MK |
5892 | /* Data for ColdFire V4 index bypass. |
5893 | Producer modifies register that is used as index in consumer with | |
5894 | specified scale. */ | |
5895 | static struct | |
b8c96320 | 5896 | { |
96fcacb7 MK |
5897 | /* Producer instruction. */ |
5898 | rtx pro; | |
826fadba | 5899 | |
96fcacb7 MK |
5900 | /* Consumer instruction. */ |
5901 | rtx con; | |
b8c96320 | 5902 | |
96fcacb7 MK |
5903 | /* Scale of indexed memory access within consumer. |
5904 | Or zero if bypass should not be effective at the moment. */ | |
5905 | int scale; | |
5906 | } sched_cfv4_bypass_data; | |
b8c96320 MK |
5907 | |
5908 | /* An empty state that is used in m68k_sched_adjust_cost. */ | |
5909 | static state_t sched_adjust_cost_state; | |
5910 | ||
5911 | /* Implement adjust_cost scheduler hook. | |
5912 | Return adjusted COST of dependency LINK between DEF_INSN and INSN. */ | |
5913 | static int | |
5914 | m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn, | |
5915 | int cost) | |
5916 | { | |
5917 | int delay; | |
5918 | ||
5919 | if (recog_memoized (def_insn) < 0 | |
5920 | || recog_memoized (insn) < 0) | |
5921 | return cost; | |
5922 | ||
96fcacb7 MK |
5923 | if (sched_cfv4_bypass_data.scale == 1) |
5924 | /* Handle ColdFire V4 bypass for indexed address with 1x scale. */ | |
5925 | { | |
5926 | /* haifa-sched.c: insn_cost () calls bypass_p () just before | |
5927 | targetm.sched.adjust_cost (). Hence, we can be relatively sure | |
5928 | that the data in sched_cfv4_bypass_data is up to date. */ | |
5929 | gcc_assert (sched_cfv4_bypass_data.pro == def_insn | |
5930 | && sched_cfv4_bypass_data.con == insn); | |
5931 | ||
5932 | if (cost < 3) | |
5933 | cost = 3; | |
5934 | ||
5935 | sched_cfv4_bypass_data.pro = NULL; | |
5936 | sched_cfv4_bypass_data.con = NULL; | |
5937 | sched_cfv4_bypass_data.scale = 0; | |
5938 | } | |
5939 | else | |
5940 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
5941 | && sched_cfv4_bypass_data.con == NULL | |
5942 | && sched_cfv4_bypass_data.scale == 0); | |
5943 | ||
b8c96320 MK |
5944 | /* Don't try to issue INSN earlier than DFA permits. |
5945 | This is especially useful for instructions that write to memory, | |
5946 | as their true dependence (default) latency is better to be set to 0 | |
5947 | to workaround alias analysis limitations. | |
5948 | This is, in fact, a machine independent tweak, so, probably, | |
5949 | it should be moved to haifa-sched.c: insn_cost (). */ | |
b8c96320 MK |
5950 | delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn); |
5951 | if (delay > cost) | |
5952 | cost = delay; | |
5953 | ||
5954 | return cost; | |
5955 | } | |
5956 | ||
96fcacb7 MK |
5957 | /* Return maximal number of insns that can be scheduled on a single cycle. */ |
5958 | static int | |
5959 | m68k_sched_issue_rate (void) | |
5960 | { | |
5961 | switch (m68k_sched_cpu) | |
5962 | { | |
5963 | case CPU_CFV1: | |
5964 | case CPU_CFV2: | |
5965 | case CPU_CFV3: | |
5966 | return 1; | |
5967 | ||
5968 | case CPU_CFV4: | |
5969 | return 2; | |
5970 | ||
5971 | default: | |
5972 | gcc_unreachable (); | |
5973 | return 0; | |
5974 | } | |
5975 | } | |
5976 | ||
826fadba MK |
5977 | /* Maximal length of instruction for current CPU. |
5978 | E.g. it is 3 for any ColdFire core. */ | |
5979 | static int max_insn_size; | |
5980 | ||
5981 | /* Data to model instruction buffer of CPU. */ | |
5982 | struct _sched_ib | |
5983 | { | |
96fcacb7 MK |
5984 | /* True if instruction buffer model is modeled for current CPU. */ |
5985 | bool enabled_p; | |
5986 | ||
826fadba MK |
5987 | /* Size of the instruction buffer in words. */ |
5988 | int size; | |
5989 | ||
5990 | /* Number of filled words in the instruction buffer. */ | |
5991 | int filled; | |
5992 | ||
5993 | /* Additional information about instruction buffer for CPUs that have | |
5994 | a buffer of instruction records, rather then a plain buffer | |
5995 | of instruction words. */ | |
5996 | struct _sched_ib_records | |
5997 | { | |
5998 | /* Size of buffer in records. */ | |
5999 | int n_insns; | |
b8c96320 | 6000 | |
826fadba MK |
6001 | /* Array to hold data on adjustements made to the size of the buffer. */ |
6002 | int *adjust; | |
b8c96320 | 6003 | |
826fadba MK |
6004 | /* Index of the above array. */ |
6005 | int adjust_index; | |
6006 | } records; | |
6007 | ||
6008 | /* An insn that reserves (marks empty) one word in the instruction buffer. */ | |
6009 | rtx insn; | |
6010 | }; | |
6011 | ||
6012 | static struct _sched_ib sched_ib; | |
b8c96320 MK |
6013 | |
6014 | /* ID of memory unit. */ | |
6015 | static int sched_mem_unit_code; | |
6016 | ||
6017 | /* Implementation of the targetm.sched.variable_issue () hook. | |
6018 | It is called after INSN was issued. It returns the number of insns | |
6019 | that can possibly get scheduled on the current cycle. | |
6020 | It is used here to determine the effect of INSN on the instruction | |
6021 | buffer. */ | |
6022 | static int | |
6023 | m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6024 | int sched_verbose ATTRIBUTE_UNUSED, | |
6025 | rtx insn, int can_issue_more) | |
6026 | { | |
6027 | int insn_size; | |
6028 | ||
96fcacb7 | 6029 | if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE) |
b8c96320 | 6030 | { |
826fadba MK |
6031 | switch (m68k_sched_cpu) |
6032 | { | |
6033 | case CPU_CFV1: | |
6034 | case CPU_CFV2: | |
96fcacb7 | 6035 | insn_size = sched_get_attr_size_int (insn); |
826fadba MK |
6036 | break; |
6037 | ||
6038 | case CPU_CFV3: | |
96fcacb7 | 6039 | insn_size = sched_get_attr_size_int (insn); |
826fadba MK |
6040 | |
6041 | /* ColdFire V3 and V4 cores have instruction buffers that can | |
6042 | accumulate up to 8 instructions regardless of instructions' | |
6043 | sizes. So we should take care not to "prefetch" 24 one-word | |
6044 | or 12 two-words instructions. | |
6045 | To model this behavior we temporarily decrease size of the | |
6046 | buffer by (max_insn_size - insn_size) for next 7 instructions. */ | |
6047 | { | |
6048 | int adjust; | |
6049 | ||
6050 | adjust = max_insn_size - insn_size; | |
6051 | sched_ib.size -= adjust; | |
6052 | ||
6053 | if (sched_ib.filled > sched_ib.size) | |
6054 | sched_ib.filled = sched_ib.size; | |
6055 | ||
6056 | sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust; | |
6057 | } | |
6058 | ||
6059 | ++sched_ib.records.adjust_index; | |
6060 | if (sched_ib.records.adjust_index == sched_ib.records.n_insns) | |
6061 | sched_ib.records.adjust_index = 0; | |
6062 | ||
6063 | /* Undo adjustement we did 7 instructions ago. */ | |
6064 | sched_ib.size | |
6065 | += sched_ib.records.adjust[sched_ib.records.adjust_index]; | |
6066 | ||
6067 | break; | |
b8c96320 | 6068 | |
96fcacb7 MK |
6069 | case CPU_CFV4: |
6070 | gcc_assert (!sched_ib.enabled_p); | |
6071 | insn_size = 0; | |
6072 | break; | |
6073 | ||
826fadba MK |
6074 | default: |
6075 | gcc_unreachable (); | |
6076 | } | |
b8c96320 | 6077 | |
3162fdf4 MK |
6078 | if (insn_size > sched_ib.filled) |
6079 | /* Scheduling for register pressure does not always take DFA into | |
6080 | account. Workaround instruction buffer not being filled enough. */ | |
6081 | { | |
6082 | gcc_assert (sched_pressure_p); | |
6083 | insn_size = sched_ib.filled; | |
6084 | } | |
6085 | ||
b8c96320 MK |
6086 | --can_issue_more; |
6087 | } | |
6088 | else if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6089 | || asm_noperands (PATTERN (insn)) >= 0) | |
826fadba | 6090 | insn_size = sched_ib.filled; |
b8c96320 MK |
6091 | else |
6092 | insn_size = 0; | |
6093 | ||
826fadba | 6094 | sched_ib.filled -= insn_size; |
b8c96320 MK |
6095 | |
6096 | return can_issue_more; | |
6097 | } | |
6098 | ||
96fcacb7 MK |
6099 | /* Return how many instructions should scheduler lookahead to choose the |
6100 | best one. */ | |
6101 | static int | |
6102 | m68k_sched_first_cycle_multipass_dfa_lookahead (void) | |
b8c96320 | 6103 | { |
96fcacb7 | 6104 | return m68k_sched_issue_rate () - 1; |
b8c96320 MK |
6105 | } |
6106 | ||
7ecb00a6 | 6107 | /* Implementation of targetm.sched.init_global () hook. |
b8c96320 MK |
6108 | It is invoked once per scheduling pass and is used here |
6109 | to initialize scheduler constants. */ | |
6110 | static void | |
6111 | m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6112 | int sched_verbose ATTRIBUTE_UNUSED, | |
6113 | int n_insns ATTRIBUTE_UNUSED) | |
6114 | { | |
6115 | /* Init branch types. */ | |
6116 | { | |
6117 | rtx insn; | |
6118 | ||
5ead67f6 | 6119 | sched_branch_type = XCNEWVEC (enum attr_type, get_max_uid () + 1); |
b8c96320 MK |
6120 | |
6121 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
6122 | { | |
6123 | if (JUMP_P (insn)) | |
6124 | /* !!! FIXME: Implement real scan here. */ | |
6125 | sched_branch_type[INSN_UID (insn)] = TYPE_BCC; | |
6126 | } | |
6127 | } | |
6128 | ||
96fcacb7 MK |
6129 | #ifdef ENABLE_CHECKING |
6130 | /* Check that all instructions have DFA reservations and | |
6131 | that all instructions can be issued from a clean state. */ | |
6132 | { | |
6133 | rtx insn; | |
6134 | state_t state; | |
b8c96320 | 6135 | |
96fcacb7 | 6136 | state = alloca (state_size ()); |
b8c96320 | 6137 | |
96fcacb7 MK |
6138 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
6139 | { | |
6140 | if (INSN_P (insn) && recog_memoized (insn) >= 0) | |
6141 | { | |
6142 | gcc_assert (insn_has_dfa_reservation_p (insn)); | |
b8c96320 | 6143 | |
96fcacb7 MK |
6144 | state_reset (state); |
6145 | if (state_transition (state, insn) >= 0) | |
6146 | gcc_unreachable (); | |
6147 | } | |
6148 | } | |
6149 | } | |
6150 | #endif | |
b8c96320 MK |
6151 | |
6152 | /* Setup target cpu. */ | |
96fcacb7 MK |
6153 | |
6154 | /* ColdFire V4 has a set of features to keep its instruction buffer full | |
6155 | (e.g., a separate memory bus for instructions) and, hence, we do not model | |
6156 | buffer for this CPU. */ | |
6157 | sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4); | |
6158 | ||
b8c96320 MK |
6159 | switch (m68k_sched_cpu) |
6160 | { | |
96fcacb7 MK |
6161 | case CPU_CFV4: |
6162 | sched_ib.filled = 0; | |
6163 | ||
6164 | /* FALLTHRU */ | |
6165 | ||
826fadba MK |
6166 | case CPU_CFV1: |
6167 | case CPU_CFV2: | |
6168 | max_insn_size = 3; | |
6169 | sched_ib.records.n_insns = 0; | |
6170 | sched_ib.records.adjust = NULL; | |
6171 | break; | |
6172 | ||
6173 | case CPU_CFV3: | |
6174 | max_insn_size = 3; | |
6175 | sched_ib.records.n_insns = 8; | |
5ead67f6 | 6176 | sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns); |
b8c96320 MK |
6177 | break; |
6178 | ||
6179 | default: | |
6180 | gcc_unreachable (); | |
6181 | } | |
6182 | ||
826fadba MK |
6183 | sched_mem_unit_code = get_cpu_unit_code ("cf_mem1"); |
6184 | ||
b8c96320 MK |
6185 | sched_adjust_cost_state = xmalloc (state_size ()); |
6186 | state_reset (sched_adjust_cost_state); | |
6187 | ||
6188 | start_sequence (); | |
6189 | emit_insn (gen_ib ()); | |
826fadba | 6190 | sched_ib.insn = get_insns (); |
b8c96320 MK |
6191 | end_sequence (); |
6192 | } | |
6193 | ||
6194 | /* Scheduling pass is now finished. Free/reset static variables. */ | |
6195 | static void | |
6196 | m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
6197 | int verbose ATTRIBUTE_UNUSED) | |
6198 | { | |
826fadba | 6199 | sched_ib.insn = NULL; |
b8c96320 MK |
6200 | |
6201 | free (sched_adjust_cost_state); | |
6202 | sched_adjust_cost_state = NULL; | |
6203 | ||
6204 | sched_mem_unit_code = 0; | |
826fadba MK |
6205 | |
6206 | free (sched_ib.records.adjust); | |
6207 | sched_ib.records.adjust = NULL; | |
6208 | sched_ib.records.n_insns = 0; | |
6209 | max_insn_size = 0; | |
b8c96320 MK |
6210 | |
6211 | free (sched_branch_type); | |
6212 | sched_branch_type = NULL; | |
6213 | } | |
6214 | ||
7ecb00a6 | 6215 | /* Implementation of targetm.sched.init () hook. |
b8c96320 MK |
6216 | It is invoked each time scheduler starts on the new block (basic block or |
6217 | extended basic block). */ | |
6218 | static void | |
6219 | m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6220 | int sched_verbose ATTRIBUTE_UNUSED, | |
6221 | int n_insns ATTRIBUTE_UNUSED) | |
6222 | { | |
826fadba MK |
6223 | switch (m68k_sched_cpu) |
6224 | { | |
6225 | case CPU_CFV1: | |
6226 | case CPU_CFV2: | |
6227 | sched_ib.size = 6; | |
6228 | break; | |
6229 | ||
6230 | case CPU_CFV3: | |
6231 | sched_ib.size = sched_ib.records.n_insns * max_insn_size; | |
6232 | ||
6233 | memset (sched_ib.records.adjust, 0, | |
6234 | sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust)); | |
6235 | sched_ib.records.adjust_index = 0; | |
6236 | break; | |
6237 | ||
96fcacb7 MK |
6238 | case CPU_CFV4: |
6239 | gcc_assert (!sched_ib.enabled_p); | |
6240 | sched_ib.size = 0; | |
6241 | break; | |
6242 | ||
826fadba MK |
6243 | default: |
6244 | gcc_unreachable (); | |
6245 | } | |
6246 | ||
96fcacb7 MK |
6247 | if (sched_ib.enabled_p) |
6248 | /* haifa-sched.c: schedule_block () calls advance_cycle () just before | |
6249 | the first cycle. Workaround that. */ | |
6250 | sched_ib.filled = -2; | |
b8c96320 MK |
6251 | } |
6252 | ||
6253 | /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook. | |
6254 | It is invoked just before current cycle finishes and is used here | |
6255 | to track if instruction buffer got its two words this cycle. */ | |
6256 | static void | |
6257 | m68k_sched_dfa_pre_advance_cycle (void) | |
6258 | { | |
96fcacb7 MK |
6259 | if (!sched_ib.enabled_p) |
6260 | return; | |
6261 | ||
b8c96320 MK |
6262 | if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code)) |
6263 | { | |
826fadba | 6264 | sched_ib.filled += 2; |
b8c96320 | 6265 | |
826fadba MK |
6266 | if (sched_ib.filled > sched_ib.size) |
6267 | sched_ib.filled = sched_ib.size; | |
b8c96320 MK |
6268 | } |
6269 | } | |
6270 | ||
6271 | /* Implementation of targetm.sched.dfa_post_advance_cycle () hook. | |
6272 | It is invoked just after new cycle begins and is used here | |
6273 | to setup number of filled words in the instruction buffer so that | |
6274 | instructions which won't have all their words prefetched would be | |
6275 | stalled for a cycle. */ | |
6276 | static void | |
6277 | m68k_sched_dfa_post_advance_cycle (void) | |
6278 | { | |
6279 | int i; | |
b8c96320 | 6280 | |
96fcacb7 MK |
6281 | if (!sched_ib.enabled_p) |
6282 | return; | |
6283 | ||
b8c96320 MK |
6284 | /* Setup number of prefetched instruction words in the instruction |
6285 | buffer. */ | |
826fadba MK |
6286 | i = max_insn_size - sched_ib.filled; |
6287 | ||
6288 | while (--i >= 0) | |
b8c96320 | 6289 | { |
826fadba | 6290 | if (state_transition (curr_state, sched_ib.insn) >= 0) |
b8c96320 MK |
6291 | gcc_unreachable (); |
6292 | } | |
6293 | } | |
96fcacb7 MK |
6294 | |
6295 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6296 | if it is an integer register, or NULL overwise. */ | |
6297 | static rtx | |
6298 | sched_get_reg_operand (rtx insn, bool opx_p) | |
6299 | { | |
6300 | rtx op = NULL; | |
6301 | ||
6302 | if (opx_p) | |
6303 | { | |
6304 | if (get_attr_opx_type (insn) == OPX_TYPE_RN) | |
6305 | { | |
6306 | op = sched_get_operand (insn, true); | |
6307 | gcc_assert (op != NULL); | |
6308 | ||
6309 | if (!reload_completed && !REG_P (op)) | |
6310 | return NULL; | |
6311 | } | |
6312 | } | |
6313 | else | |
6314 | { | |
6315 | if (get_attr_opy_type (insn) == OPY_TYPE_RN) | |
6316 | { | |
6317 | op = sched_get_operand (insn, false); | |
6318 | gcc_assert (op != NULL); | |
6319 | ||
6320 | if (!reload_completed && !REG_P (op)) | |
6321 | return NULL; | |
6322 | } | |
6323 | } | |
6324 | ||
6325 | return op; | |
6326 | } | |
6327 | ||
6328 | /* Return true, if X or Y (depending on OPX_P) operand of INSN | |
6329 | is a MEM. */ | |
6330 | static bool | |
6331 | sched_mem_operand_p (rtx insn, bool opx_p) | |
6332 | { | |
6333 | switch (sched_get_opxy_mem_type (insn, opx_p)) | |
6334 | { | |
6335 | case OP_TYPE_MEM1: | |
6336 | case OP_TYPE_MEM6: | |
6337 | return true; | |
6338 | ||
6339 | default: | |
6340 | return false; | |
6341 | } | |
6342 | } | |
6343 | ||
6344 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6345 | if it is a MEM, or NULL overwise. */ | |
6346 | static rtx | |
6347 | sched_get_mem_operand (rtx insn, bool must_read_p, bool must_write_p) | |
6348 | { | |
6349 | bool opx_p; | |
6350 | bool opy_p; | |
6351 | ||
6352 | opx_p = false; | |
6353 | opy_p = false; | |
6354 | ||
6355 | if (must_read_p) | |
6356 | { | |
6357 | opx_p = true; | |
6358 | opy_p = true; | |
6359 | } | |
6360 | ||
6361 | if (must_write_p) | |
6362 | { | |
6363 | opx_p = true; | |
6364 | opy_p = false; | |
6365 | } | |
6366 | ||
6367 | if (opy_p && sched_mem_operand_p (insn, false)) | |
6368 | return sched_get_operand (insn, false); | |
6369 | ||
6370 | if (opx_p && sched_mem_operand_p (insn, true)) | |
6371 | return sched_get_operand (insn, true); | |
6372 | ||
6373 | gcc_unreachable (); | |
6374 | return NULL; | |
6375 | } | |
6376 | ||
6377 | /* Return non-zero if PRO modifies register used as part of | |
6378 | address in CON. */ | |
6379 | int | |
6380 | m68k_sched_address_bypass_p (rtx pro, rtx con) | |
6381 | { | |
6382 | rtx pro_x; | |
6383 | rtx con_mem_read; | |
6384 | ||
6385 | pro_x = sched_get_reg_operand (pro, true); | |
6386 | if (pro_x == NULL) | |
6387 | return 0; | |
6388 | ||
6389 | con_mem_read = sched_get_mem_operand (con, true, false); | |
6390 | gcc_assert (con_mem_read != NULL); | |
6391 | ||
6392 | if (reg_mentioned_p (pro_x, con_mem_read)) | |
6393 | return 1; | |
6394 | ||
6395 | return 0; | |
6396 | } | |
6397 | ||
6398 | /* Helper function for m68k_sched_indexed_address_bypass_p. | |
6399 | if PRO modifies register used as index in CON, | |
6400 | return scale of indexed memory access in CON. Return zero overwise. */ | |
6401 | static int | |
6402 | sched_get_indexed_address_scale (rtx pro, rtx con) | |
6403 | { | |
6404 | rtx reg; | |
6405 | rtx mem; | |
6406 | struct m68k_address address; | |
6407 | ||
6408 | reg = sched_get_reg_operand (pro, true); | |
6409 | if (reg == NULL) | |
6410 | return 0; | |
6411 | ||
6412 | mem = sched_get_mem_operand (con, true, false); | |
6413 | gcc_assert (mem != NULL && MEM_P (mem)); | |
6414 | ||
6415 | if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed, | |
6416 | &address)) | |
6417 | gcc_unreachable (); | |
6418 | ||
6419 | if (REGNO (reg) == REGNO (address.index)) | |
6420 | { | |
6421 | gcc_assert (address.scale != 0); | |
6422 | return address.scale; | |
6423 | } | |
6424 | ||
6425 | return 0; | |
6426 | } | |
6427 | ||
6428 | /* Return non-zero if PRO modifies register used | |
6429 | as index with scale 2 or 4 in CON. */ | |
6430 | int | |
6431 | m68k_sched_indexed_address_bypass_p (rtx pro, rtx con) | |
6432 | { | |
6433 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
6434 | && sched_cfv4_bypass_data.con == NULL | |
6435 | && sched_cfv4_bypass_data.scale == 0); | |
6436 | ||
6437 | switch (sched_get_indexed_address_scale (pro, con)) | |
6438 | { | |
6439 | case 1: | |
6440 | /* We can't have a variable latency bypass, so | |
6441 | remember to adjust the insn cost in adjust_cost hook. */ | |
6442 | sched_cfv4_bypass_data.pro = pro; | |
6443 | sched_cfv4_bypass_data.con = con; | |
6444 | sched_cfv4_bypass_data.scale = 1; | |
6445 | return 0; | |
6446 | ||
6447 | case 2: | |
6448 | case 4: | |
6449 | return 1; | |
6450 | ||
6451 | default: | |
6452 | return 0; | |
6453 | } | |
6454 | } | |
75df395f | 6455 | |
e0601576 RH |
6456 | /* We generate a two-instructions program at M_TRAMP : |
6457 | movea.l &CHAIN_VALUE,%a0 | |
6458 | jmp FNADDR | |
6459 | where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */ | |
6460 | ||
6461 | static void | |
6462 | m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
6463 | { | |
6464 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
6465 | rtx mem; | |
6466 | ||
6467 | gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM)); | |
6468 | ||
6469 | mem = adjust_address (m_tramp, HImode, 0); | |
6470 | emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); | |
6471 | mem = adjust_address (m_tramp, SImode, 2); | |
6472 | emit_move_insn (mem, chain_value); | |
6473 | ||
6474 | mem = adjust_address (m_tramp, HImode, 6); | |
6475 | emit_move_insn (mem, GEN_INT(0x4EF9)); | |
6476 | mem = adjust_address (m_tramp, SImode, 8); | |
6477 | emit_move_insn (mem, fnaddr); | |
6478 | ||
6479 | FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0)); | |
6480 | } | |
6481 | ||
079e7538 NF |
6482 | /* On the 68000, the RTS insn cannot pop anything. |
6483 | On the 68010, the RTD insn may be used to pop them if the number | |
6484 | of args is fixed, but if the number is variable then the caller | |
6485 | must pop them all. RTD can't be used for library calls now | |
6486 | because the library is compiled with the Unix compiler. | |
6487 | Use of RTD is a selectable option, since it is incompatible with | |
6488 | standard Unix calling sequences. If the option is not selected, | |
6489 | the caller must always pop the args. */ | |
6490 | ||
6491 | static int | |
6492 | m68k_return_pops_args (tree fundecl, tree funtype, int size) | |
6493 | { | |
6494 | return ((TARGET_RTD | |
6495 | && (!fundecl | |
6496 | || TREE_CODE (fundecl) != IDENTIFIER_NODE) | |
f38958e8 | 6497 | && (!stdarg_p (funtype))) |
079e7538 NF |
6498 | ? size : 0); |
6499 | } | |
6500 | ||
5efd84c5 NF |
6501 | /* Make sure everything's fine if we *don't* have a given processor. |
6502 | This assumes that putting a register in fixed_regs will keep the | |
6503 | compiler's mitts completely off it. We don't bother to zero it out | |
6504 | of register classes. */ | |
6505 | ||
6506 | static void | |
6507 | m68k_conditional_register_usage (void) | |
6508 | { | |
6509 | int i; | |
6510 | HARD_REG_SET x; | |
6511 | if (!TARGET_HARD_FLOAT) | |
6512 | { | |
6513 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); | |
6514 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
6515 | if (TEST_HARD_REG_BIT (x, i)) | |
6516 | fixed_regs[i] = call_used_regs[i] = 1; | |
6517 | } | |
6518 | if (flag_pic) | |
6519 | fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; | |
6520 | } | |
6521 | ||
75df395f | 6522 | #include "gt-m68k.h" |