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79e68feb 1/* Subroutines for insn-output.c for Motorola 68000 family.
7bc88d49 2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
79e68feb
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
0e29e3c9
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
79e68feb
RS		 20
21
22/* Some output-actions in m68k.md need these. */
23#include <stdio.h>
24#include "config.h"
25#include "rtl.h"
26#include "regs.h"
27#include "hard-reg-set.h"
28#include "real.h"
29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34
35/* Needed for use_return_insn. */
36#include "flags.h"
37
38#ifdef SUPPORT_SUN_FPA
39
40/* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42enum reg_class regno_reg_class[]
43 = { DATA_REGS, ADDR_REGS, FP_REGS,
44 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
45
46#endif /* defined SUPPORT_SUN_FPA */
47
9eb4f6fc
RS		 48/* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50int switch_table_difference_label_flag;
51
79e68feb
RS		 52static rtx find_addr_reg ();
53rtx legitimize_pic_address ();
54\f
55
ef1dbfb0
RK		 56/* Alignment to use for loops and jumps */
57/* Specify power of two alignment used for loops. */
58char *m68k_align_loops_string;
59/* Specify power of two alignment used for non-loop jumps. */
60char *m68k_align_jumps_string;
61/* Specify power of two alignment used for functions. */
62char *m68k_align_funcs_string;
63
64/* Specify power of two alignment used for loops. */
65int m68k_align_loops;
66/* Specify power of two alignment used for non-loop jumps. */
67int m68k_align_jumps;
68/* Specify power of two alignment used for functions. */
69int m68k_align_funcs;
70
2b3600ac
JL		 71/* Nonzero if the last compare/test insn had FP operands. The
72 sCC expanders peek at this to determine what to do for the
73 68060, which has no fsCC instructions. */
74int m68k_last_compare_had_fp_operands;
ef1dbfb0
RK		 75
76/* Sometimes certain combinations of command options do not make
77 sense on a particular target machine. You can define a macro
78 `OVERRIDE_OPTIONS' to take account of this. This macro, if
79 defined, is executed once just after all the command options have
80 been parsed.
81
82 Don't use this macro to turn on various extra optimizations for
83 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
84
85void
86override_options ()
87{
88 int def_align;
89
90 def_align = 1;
91
92 /* Validate -malign-loops= value, or provide default */
93 if (m68k_align_loops_string)
94 {
95 m68k_align_loops = atoi (m68k_align_loops_string);
96 if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
97 fatal ("-malign-loops=%d is not between 1 and %d",
98 m68k_align_loops, MAX_CODE_ALIGN);
99 }
100 else
101 m68k_align_loops = def_align;
102
103 /* Validate -malign-jumps= value, or provide default */
104 if (m68k_align_jumps_string)
105 {
106 m68k_align_jumps = atoi (m68k_align_jumps_string);
107 if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
108 fatal ("-malign-jumps=%d is not between 1 and %d",
109 m68k_align_jumps, MAX_CODE_ALIGN);
110 }
111 else
112 m68k_align_jumps = def_align;
113
114 /* Validate -malign-functions= value, or provide default */
115 if (m68k_align_funcs_string)
116 {
117 m68k_align_funcs = atoi (m68k_align_funcs_string);
118 if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
119 fatal ("-malign-functions=%d is not between 1 and %d",
120 m68k_align_funcs, MAX_CODE_ALIGN);
121 }
122 else
123 m68k_align_funcs = def_align;
124}
125\f
79e68feb
RS		 126/* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
127 function at any time during the compilation process. In the future
64a184e9 128 we should try and eliminate the USE if we can easily determine that
79e68feb
RS		 129 all PIC references were deleted from the current function. That would
130 save an address register */
131
6317749b 132void
64a184e9 133finalize_pic ()
79e68feb
RS		 134{
135 if (flag_pic && current_function_uses_pic_offset_table)
adedad3e
RK		 136 {
137 rtx insn = gen_rtx (USE, VOIDmode, pic_offset_table_rtx);
138 emit_insn_after (insn, get_insns ());
139 emit_insn (insn);
140 }
79e68feb
RS		 141}
142
143\f
144/* This function generates the assembly code for function entry.
145 STREAM is a stdio stream to output the code to.
146 SIZE is an int: how many units of temporary storage to allocate.
147 Refer to the array `regs_ever_live' to determine which registers
148 to save; `regs_ever_live[I]' is nonzero if register number I
149 is ever used in the function. This function is responsible for
150 knowing which registers should not be saved even if used. */
151
152
153/* Note that the order of the bit mask for fmovem is the opposite
154 of the order for movem! */
155
156
157void
158output_function_prologue (stream, size)
159 FILE *stream;
160 int size;
161{
162 register int regno;
163 register int mask = 0;
164 int num_saved_regs = 0;
165 extern char call_used_regs[];
166 int fsize = (size + 3) & -4;
167
168
169 if (frame_pointer_needed)
170 {
2d0933a2 171 if (fsize == 0 && TARGET_68040)
e4e873f1
RK		 172 {
173 /* on the 68040, pea + move is faster than link.w 0 */
174#ifdef MOTOROLA
175 asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
176 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
177 reg_names[FRAME_POINTER_REGNUM]);
178#else
2d0933a2 179 asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
e4e873f1
RK		 180 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
181 reg_names[FRAME_POINTER_REGNUM]);
182#endif
183 }
184 else if (fsize < 0x8000)
79e68feb
RS		 185 {
186#ifdef MOTOROLA
338818c7 187 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
79e68feb
RS		 188 reg_names[FRAME_POINTER_REGNUM], -fsize);
189#else
338818c7 190 asm_fprintf (stream, "\tlink %s,%0I%d\n",
79e68feb
RS		 191 reg_names[FRAME_POINTER_REGNUM], -fsize);
192#endif
193 }
194 else if (TARGET_68020)
195 {
196#ifdef MOTOROLA
338818c7 197 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
79e68feb
RS		 198 reg_names[FRAME_POINTER_REGNUM], -fsize);
199#else
338818c7 200 asm_fprintf (stream, "\tlink %s,%0I%d\n",
79e68feb
RS		 201 reg_names[FRAME_POINTER_REGNUM], -fsize);
202#endif
203 }
204 else
205 {
e4e873f1 206 /* Adding negative number is faster on the 68040. */
79e68feb 207#ifdef MOTOROLA
cffd0d74 208 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
79e68feb
RS		 209 reg_names[FRAME_POINTER_REGNUM], -fsize);
210#else
cffd0d74 211 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
79e68feb
RS		 212 reg_names[FRAME_POINTER_REGNUM], -fsize);
213#endif
214 }
215 }
216 else if (fsize)
217 {
afaff477 218 if (fsize + 4 < 0x8000)
79e68feb 219 {
7bc88d49
RK		 220#ifdef NO_ADDSUB_Q
221 if (fsize + 4 <= 8)
afaff477 222 {
7bc88d49
RK		 223 if (!TARGET_5200)
224 {
225 /* asm_fprintf() cannot handle %. */
2d0933a2 226#ifdef MOTOROLA
7bc88d49 227 asm_fprintf (stream, "\tsubq.w %OI%d,%Rsp\n", fsize + 4);
2d0933a2 228#else
7bc88d49 229 asm_fprintf (stream, "\tsubqw %OI%d,%Rsp\n", fsize + 4);
2d0933a2 230#endif
7bc88d49
RK		 231 }
232 else
233 {
a7e2b014 234 /* asm_fprintf() cannot handle %. */
7bc88d49
RK		 235#ifdef MOTOROLA
236 asm_fprintf (stream, "\tsubq.l %OI%d,%Rsp\n", fsize + 4);
237#else
238 asm_fprintf (stream, "\tsubql %OI%d,%Rsp\n", fsize + 4);
239#endif
240 }
afaff477 241 }
7bc88d49
RK		 242 else if (fsize + 4 <= 16 && TARGET_CPU32)
243 {
244 /* On the CPU32 it is faster to use two subqw instructions to
245 subtract a small integer (8 < N <= 16) to a register. */
246 /* asm_fprintf() cannot handle %. */
247#ifdef MOTOROLA
248 asm_fprintf (stream, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
249 fsize + 4);
250#else
251 asm_fprintf (stream, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
252 fsize + 4);
253#endif
254 }
255 else
256#endif /* NO_ADDSUB_Q */
257 if (TARGET_68040)
afaff477 258 {
7bc88d49 259 /* Adding negative number is faster on the 68040. */
afaff477
RK		 260 /* asm_fprintf() cannot handle %. */
261#ifdef MOTOROLA
262 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
263#else
264 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
7bc88d49
RK		 265#endif
266 }
267 else
268 {
7bc88d49
RK		 269#ifdef MOTOROLA
270 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
271#else
272 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
afaff477
RK		 273#endif
274 }
79e68feb
RS		 275 }
276 else
277 {
2d0933a2
RK		 278 /* asm_fprintf() cannot handle %. */
279#ifdef MOTOROLA
280 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
281#else
282 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
283#endif
79e68feb
RS		 284 }
285 }
286#ifdef SUPPORT_SUN_FPA
287 for (regno = 24; regno < 56; regno++)
288 if (regs_ever_live[regno] && ! call_used_regs[regno])
289 {
290#ifdef MOTOROLA
291 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
292 reg_names[regno]);
293#else
294 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
295 reg_names[regno]);
296#endif
297 }
298#endif
f277471f 299 if (TARGET_68881)
79e68feb 300 {
f277471f
RK		 301 for (regno = 16; regno < 24; regno++)
302 if (regs_ever_live[regno] && ! call_used_regs[regno])
303 mask |= 1 << (regno - 16);
304 if ((mask & 0xff) != 0)
305 {
79e68feb 306#ifdef MOTOROLA
f277471f 307 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
79e68feb 308#else
f277471f 309 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
79e68feb 310#endif
f277471f
RK		 311 }
312 mask = 0;
79e68feb 313 }
79e68feb
RS		 314 for (regno = 0; regno < 16; regno++)
315 if (regs_ever_live[regno] && ! call_used_regs[regno])
316 {
317 mask |= 1 << (15 - regno);
318 num_saved_regs++;
319 }
320 if (frame_pointer_needed)
321 {
322 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
323 num_saved_regs--;
324 }
99df2465
RS		 325
326#if NEED_PROBE
a7e2b014
RK		 327#ifdef MOTOROLA
328#ifdef CRDS
329 asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
330#else
331 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
332#endif
333#else
81bd5278 334 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
a7e2b014 335#endif
99df2465
RS		 336#endif
337
79e68feb
RS		 338 if (num_saved_regs <= 2)
339 {
340 /* Store each separately in the same order moveml uses.
341 Using two movel instructions instead of a single moveml
342 is about 15% faster for the 68020 and 68030 at no expense
343 in code size */
344
345 int i;
346
347 /* Undo the work from above. */
348 for (i = 0; i< 16; i++)
349 if (mask & (1 << i))
350 asm_fprintf (stream,
351#ifdef MOTOROLA
64a184e9 352 "\t%Omove.l %s,-(%Rsp)\n",
79e68feb
RS		 353#else
354 "\tmovel %s,%Rsp@-\n",
355#endif
356 reg_names[15 - i]);
357 }
358 else if (mask)
359 {
afaff477
RK		 360 if (TARGET_5200)
361 {
362 /* The coldfire does not support the predecrement form of the
363 movml instruction, so we must adjust the stack pointer and
364 then use the plain address register indirect mode. We also
365 have to invert the register save mask to use the new mode.
366
367 FIXME: if num_saved_regs was calculated earlier, we could
368 combine the stack pointer adjustment with any adjustment
369 done when the initial stack frame is created. This would
370 save an instruction */
371
372 int newmask = 0;
373 int i;
374
375 for (i = 0; i < 16; i++)
376 if (mask & (1 << i))
377 newmask |= (1 << (15-i));
378
379#ifdef MOTOROLA
de649959 380 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
afaff477
RK		 381 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
382#else
de649959 383 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
afaff477
RK		 384 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
385#endif
386 }
387 else
388 {
79e68feb 389#ifdef MOTOROLA
afaff477 390 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
79e68feb 391#else
afaff477 392 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
79e68feb 393#endif
afaff477 394 }
79e68feb
RS		 395 }
396 if (flag_pic && current_function_uses_pic_offset_table)
397 {
398#ifdef MOTOROLA
66c432a7 399 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
79e68feb
RS		 400 reg_names[PIC_OFFSET_TABLE_REGNUM]);
401#else
cffd0d74 402 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
79e68feb
RS		 403 reg_names[PIC_OFFSET_TABLE_REGNUM]);
404 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
405 reg_names[PIC_OFFSET_TABLE_REGNUM],
406 reg_names[PIC_OFFSET_TABLE_REGNUM]);
407#endif
408 }
409}
410\f
411/* Return true if this function's epilogue can be output as RTL. */
412
413int
414use_return_insn ()
415{
416 int regno;
417
418 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
419 return 0;
420
421 /* Copied from output_function_epilogue (). We should probably create a
422 separate layout routine to perform the common work. */
423
424 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
425 if (regs_ever_live[regno] && ! call_used_regs[regno])
426 return 0;
427
428 return 1;
429}
430
431/* This function generates the assembly code for function exit,
432 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
433
434 The function epilogue should not depend on the current stack pointer!
435 It should use the frame pointer only, if there is a frame pointer.
436 This is mandatory because of alloca; we also take advantage of it to
437 omit stack adjustments before returning. */
438
439void
440output_function_epilogue (stream, size)
441 FILE *stream;
442 int size;
443{
444 register int regno;
445 register int mask, fmask;
446 register int nregs;
447 int offset, foffset, fpoffset;
448 extern char call_used_regs[];
449 int fsize = (size + 3) & -4;
450 int big = 0;
451 rtx insn = get_last_insn ();
6910dd70 452 int restore_from_sp = 0;
79e68feb
RS		 453
454 /* If the last insn was a BARRIER, we don't have to write any code. */
455 if (GET_CODE (insn) == NOTE)
456 insn = prev_nonnote_insn (insn);
457 if (insn && GET_CODE (insn) == BARRIER)
cffd0d74
RS		 458 {
459 /* Output just a no-op so that debuggers don't get confused
460 about which function the pc is in at this address. */
461 asm_fprintf (stream, "\tnop\n");
462 return;
463 }
79e68feb 464
b69649e4
RK		 465#ifdef FUNCTION_BLOCK_PROFILER_EXIT
466 if (profile_block_flag == 2)
467 {
468 FUNCTION_BLOCK_PROFILER_EXIT (stream);
469 }
470#endif
471
79e68feb
RS		 472#ifdef FUNCTION_EXTRA_EPILOGUE
473 FUNCTION_EXTRA_EPILOGUE (stream, size);
474#endif
475 nregs = 0; fmask = 0; fpoffset = 0;
476#ifdef SUPPORT_SUN_FPA
477 for (regno = 24 ; regno < 56 ; regno++)
478 if (regs_ever_live[regno] && ! call_used_regs[regno])
479 nregs++;
480 fpoffset = nregs * 8;
481#endif
482 nregs = 0;
f277471f
RK		 483 if (TARGET_68881)
484 {
485 for (regno = 16; regno < 24; regno++)
486 if (regs_ever_live[regno] && ! call_used_regs[regno])
487 {
488 nregs++;
489 fmask |= 1 << (23 - regno);
490 }
491 }
79e68feb
RS		 492 foffset = fpoffset + nregs * 12;
493 nregs = 0; mask = 0;
494 if (frame_pointer_needed)
495 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
496 for (regno = 0; regno < 16; regno++)
497 if (regs_ever_live[regno] && ! call_used_regs[regno])
498 {
499 nregs++;
500 mask |= 1 << regno;
501 }
502 offset = foffset + nregs * 4;
c67ddce5
RK		 503 /* FIXME : leaf_function_p below is too strong.
504 What we really need to know there is if there could be pending
505 stack adjustment needed at that point. */
6910dd70
RK		 506 restore_from_sp = ! frame_pointer_needed
507 || (! current_function_calls_alloca && leaf_function_p ());
79e68feb 508 if (offset + fsize >= 0x8000
6910dd70 509 && ! restore_from_sp
79e68feb
RS		 510 && (mask || fmask || fpoffset))
511 {
512#ifdef MOTOROLA
e7eefaec 513 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
79e68feb 514#else
e7eefaec 515 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
79e68feb
RS		 516#endif
517 fsize = 0, big = 1;
518 }
afaff477 519 if (TARGET_5200 || nregs <= 2)
79e68feb
RS		 520 {
521 /* Restore each separately in the same order moveml does.
522 Using two movel instructions instead of a single moveml
523 is about 15% faster for the 68020 and 68030 at no expense
524 in code size. */
525
526 int i;
527
528 /* Undo the work from above. */
529 for (i = 0; i< 16; i++)
530 if (mask & (1 << i))
531 {
532 if (big)
533 {
534#ifdef MOTOROLA
e7eefaec 535 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
79e68feb
RS		 536 offset + fsize,
537 reg_names[FRAME_POINTER_REGNUM],
538 reg_names[i]);
539#else
e7eefaec 540 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
79e68feb
RS		 541 reg_names[FRAME_POINTER_REGNUM],
542 offset + fsize, reg_names[i]);
543#endif
544 }
6910dd70 545 else if (restore_from_sp)
79e68feb
RS		 546 {
547#ifdef MOTOROLA
64a184e9 548 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
79e68feb
RS		 549 reg_names[i]);
550#else
551 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
552 reg_names[i]);
553#endif
554 }
555 else
556 {
557#ifdef MOTOROLA
64a184e9 558 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
79e68feb
RS		 559 offset + fsize,
560 reg_names[FRAME_POINTER_REGNUM],
561 reg_names[i]);
562#else
563 asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
564 reg_names[FRAME_POINTER_REGNUM],
565 offset + fsize, reg_names[i]);
566#endif
567 }
568 offset = offset - 4;
569 }
570 }
571 else if (mask)
572 {
573 if (big)
574 {
575#ifdef MOTOROLA
e7eefaec 576 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
79e68feb
RS		 577 offset + fsize,
578 reg_names[FRAME_POINTER_REGNUM],
579 mask);
580#else
e7eefaec 581 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
79e68feb
RS		 582 reg_names[FRAME_POINTER_REGNUM],
583 offset + fsize, mask);
584#endif
585 }
6910dd70 586 else if (restore_from_sp)
79e68feb
RS		 587 {
588#ifdef MOTOROLA
cffd0d74 589 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
79e68feb 590#else
cffd0d74 591 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
79e68feb
RS		 592#endif
593 }
594 else
595 {
596#ifdef MOTOROLA
cffd0d74 597 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
79e68feb
RS		 598 offset + fsize,
599 reg_names[FRAME_POINTER_REGNUM],
600 mask);
601#else
cffd0d74 602 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
79e68feb
RS		 603 reg_names[FRAME_POINTER_REGNUM],
604 offset + fsize, mask);
605#endif
606 }
607 }
608 if (fmask)
609 {
610 if (big)
611 {
612#ifdef MOTOROLA
e7eefaec 613 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
79e68feb
RS		 614 foffset + fsize,
615 reg_names[FRAME_POINTER_REGNUM],
616 fmask);
617#else
e7eefaec 618 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
79e68feb
RS		 619 reg_names[FRAME_POINTER_REGNUM],
620 foffset + fsize, fmask);
621#endif
622 }
6910dd70 623 else if (restore_from_sp)
79e68feb
RS		 624 {
625#ifdef MOTOROLA
cffd0d74 626 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
79e68feb 627#else
cffd0d74 628 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
79e68feb
RS		 629#endif
630 }
631 else
632 {
633#ifdef MOTOROLA
cffd0d74 634 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
79e68feb
RS		 635 foffset + fsize,
636 reg_names[FRAME_POINTER_REGNUM],
637 fmask);
638#else
cffd0d74 639 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
79e68feb
RS		 640 reg_names[FRAME_POINTER_REGNUM],
641 foffset + fsize, fmask);
642#endif
643 }
644 }
645 if (fpoffset != 0)
646 for (regno = 55; regno >= 24; regno--)
647 if (regs_ever_live[regno] && ! call_used_regs[regno])
648 {
649 if (big)
650 {
651#ifdef MOTOROLA
e7eefaec 652 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
79e68feb
RS		 653 fpoffset + fsize,
654 reg_names[FRAME_POINTER_REGNUM],
655 reg_names[regno]);
656#else
e7eefaec 657 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
79e68feb
RS		 658 reg_names[FRAME_POINTER_REGNUM],
659 fpoffset + fsize, reg_names[regno]);
660#endif
661 }
6910dd70 662 else if (restore_from_sp)
79e68feb
RS		 663 {
664#ifdef MOTOROLA
665 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
666 reg_names[regno]);
667#else
668 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
669 reg_names[regno]);
670#endif
671 }
672 else
673 {
674#ifdef MOTOROLA
675 asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
676 fpoffset + fsize,
677 reg_names[FRAME_POINTER_REGNUM],
678 reg_names[regno]);
679#else
680 asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
681 reg_names[FRAME_POINTER_REGNUM],
682 fpoffset + fsize, reg_names[regno]);
683#endif
684 }
685 fpoffset -= 8;
686 }
687 if (frame_pointer_needed)
688 fprintf (stream, "\tunlk %s\n",
689 reg_names[FRAME_POINTER_REGNUM]);
690 else if (fsize)
691 {
7bc88d49
RK		 692#ifdef NO_ADDSUB_Q
693 if (fsize + 4 <= 8)
79e68feb 694 {
7bc88d49
RK		 695 if (!TARGET_5200)
696 {
2d0933a2 697#ifdef MOTOROLA
7bc88d49 698 asm_fprintf (stream, "\taddq.w %OI%d,%Rsp\n", fsize + 4);
2d0933a2 699#else
7bc88d49 700 asm_fprintf (stream, "\taddqw %OI%d,%Rsp\n", fsize + 4);
2d0933a2 701#endif
afaff477
RK		 702 }
703 else
704 {
7bc88d49
RK		 705#ifdef MOTOROLA
706 asm_fprintf (stream, "\taddq.l %OI%d,%Rsp\n", fsize + 4);
707#else
708 asm_fprintf (stream, "\taddql %OI%d,%Rsp\n", fsize + 4);
709#endif
710 }
711 }
712 else if (fsize + 4 <= 16 && TARGET_CPU32)
713 {
714 /* On the CPU32 it is faster to use two addqw instructions to
715 add a small integer (8 < N <= 16) to a register. */
a7e2b014 716 /* asm_fprintf() cannot handle %. */
7bc88d49
RK		 717#ifdef MOTOROLA
718 asm_fprintf (stream, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
719 fsize + 4);
720#else
721 asm_fprintf (stream, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
722 fsize + 4);
723#endif
724 }
725 else
726#endif /* NO_ADDSUB_Q */
727 if (fsize + 4 < 0x8000)
728 {
729 if (TARGET_68040)
730 {
afaff477
RK		 731 /* asm_fprintf() cannot handle %. */
732#ifdef MOTOROLA
733 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
734#else
735 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
7bc88d49
RK		 736#endif
737 }
738 else
739 {
7bc88d49
RK		 740#ifdef MOTOROLA
741 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
742#else
743 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
afaff477
RK		 744#endif
745 }
79e68feb
RS		 746 }
747 else
748 {
2d0933a2
RK		 749 /* asm_fprintf() cannot handle %. */
750#ifdef MOTOROLA
751 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
752#else
753 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
754#endif
79e68feb
RS		 755 }
756 }
757 if (current_function_pops_args)
338818c7 758 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
79e68feb
RS		 759 else
760 fprintf (stream, "\trts\n");
761}
762\f
763/* Similar to general_operand, but exclude stack_pointer_rtx. */
764
765int
766not_sp_operand (op, mode)
767 register rtx op;
768 enum machine_mode mode;
769{
770 return op != stack_pointer_rtx && general_operand (op, mode);
771}
772
64a184e9
RS		 773/* Return TRUE if X is a valid comparison operator for the dbcc
774 instruction.
775
776 Note it rejects floating point comparison operators.
777 (In the future we could use Fdbcc).
778
779 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
780
781int
782valid_dbcc_comparison_p (x, mode)
783 rtx x;
784 enum machine_mode mode;
785{
64a184e9
RS		 786 switch (GET_CODE (x))
787 {
64a184e9
RS		 788 case EQ: case NE: case GTU: case LTU:
789 case GEU: case LEU:
790 return 1;
791
792 /* Reject some when CC_NO_OVERFLOW is set. This may be over
793 conservative */
794 case GT: case LT: case GE: case LE:
795 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
796 default:
797 return 0;
798 }
799}
800
6a0f85e3
TG		 801/* Return non-zero if flags are currently in the 68881 flag register. */
802int
803flags_in_68881 ()
804{
805 /* We could add support for these in the future */
806 return cc_status.flags & CC_IN_68881;
807}
808
64a184e9
RS		 809/* Output a dbCC; jCC sequence. Note we do not handle the
810 floating point version of this sequence (Fdbcc). We also
811 do not handle alternative conditions when CC_NO_OVERFLOW is
6a0f85e3
TG		 812 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
813 kick those out before we get here. */
64a184e9
RS		 814
815output_dbcc_and_branch (operands)
816 rtx *operands;
817{
64a184e9
RS		 818 switch (GET_CODE (operands[3]))
819 {
820 case EQ:
821#ifdef MOTOROLA
822 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
823#else
824 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
825#endif
826 break;
827
828 case NE:
829#ifdef MOTOROLA
830 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
831#else
832 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
833#endif
834 break;
835
836 case GT:
837#ifdef MOTOROLA
838 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
839#else
840 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
841#endif
842 break;
843
844 case GTU:
845#ifdef MOTOROLA
846 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
847#else
848 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
849#endif
850 break;
851
852 case LT:
853#ifdef MOTOROLA
854 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
855#else
856 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
857#endif
858 break;
859
860 case LTU:
861#ifdef MOTOROLA
862 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
863#else
864 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
865#endif
866 break;
867
868 case GE:
869#ifdef MOTOROLA
870 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
871#else
872 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
873#endif
874 break;
875
876 case GEU:
877#ifdef MOTOROLA
878 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
879#else
880 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
881#endif
882 break;
883
884 case LE:
885#ifdef MOTOROLA
886 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
887#else
888 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
889#endif
890 break;
891
892 case LEU:
893#ifdef MOTOROLA
894 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
895#else
896 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
897#endif
898 break;
899
900 default:
901 abort ();
902 }
903
904 /* If the decrement is to be done in SImode, then we have
905 to compensate for the fact that dbcc decrements in HImode. */
906 switch (GET_MODE (operands[0]))
907 {
908 case SImode:
909#ifdef MOTOROLA
910 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
911#else
912 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
913#endif
914 break;
915
916 case HImode:
917 break;
918
919 default:
920 abort ();
921 }
922}
923
c59c3b1c
RK		 924char *
925output_scc_di(op, operand1, operand2, dest)
926 rtx op;
927 rtx operand1;
928 rtx operand2;
929 rtx dest;
930{
931 rtx loperands[7];
d9832fd2 932 enum rtx_code op_code = GET_CODE (op);
c59c3b1c 933
906a2d3c
RK		 934 /* This does not produce a usefull cc. */
935 CC_STATUS_INIT;
936
d9832fd2
RK		 937 /* The m68k cmp.l instruction requires operand1 to be a reg as used
938 below. Swap the operands and change the op if these requirements
939 are not fulfilled. */
940 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
941 {
942 rtx tmp = operand1;
943
944 operand1 = operand2;
945 operand2 = tmp;
946 op_code = swap_condition (op_code);
947 }
c59c3b1c
RK		 948 loperands[0] = operand1;
949 if (GET_CODE (operand1) == REG)
950 loperands[1] = gen_rtx (REG, SImode, REGNO (operand1) + 1);
951 else
952 loperands[1] = adj_offsettable_operand (operand1, 4);
953 if (operand2 != const0_rtx)
954 {
955 loperands[2] = operand2;
956 if (GET_CODE (operand2) == REG)
957 loperands[3] = gen_rtx (REG, SImode, REGNO (operand2) + 1);
958 else
959 loperands[3] = adj_offsettable_operand (operand2, 4);
960 }
961 loperands[4] = gen_label_rtx();
962 if (operand2 != const0_rtx)
963#ifdef MOTOROLA
f2121711 964#ifdef SGS_CMP_ORDER
c59c3b1c
RK		 965 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
966#else
f2121711
RK		 967 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
968#endif
969#else
970#ifdef SGS_CMP_ORDER
c59c3b1c 971 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
f2121711
RK		 972#else
973 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
974#endif
c59c3b1c
RK		 975#endif
976 else
977#ifdef MOTOROLA
978 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands);
979#else
980 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands);
981#endif
982 loperands[5] = dest;
983
d9832fd2 984 switch (op_code)
c59c3b1c
RK		 985 {
986 case EQ:
987 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
988 CODE_LABEL_NUMBER (loperands[4]));
989 output_asm_insn ("seq %5", loperands);
990 break;
991
992 case NE:
993 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
994 CODE_LABEL_NUMBER (loperands[4]));
995 output_asm_insn ("sne %5", loperands);
996 break;
997
998 case GT:
999 loperands[6] = gen_label_rtx();
1000#ifdef MOTOROLA
1001 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1002#else
1003 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1004#endif
1005 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1006 CODE_LABEL_NUMBER (loperands[4]));
1007 output_asm_insn ("sgt %5", loperands);
1008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1009 CODE_LABEL_NUMBER (loperands[6]));
1010 break;
1011
1012 case GTU:
1013 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1014 CODE_LABEL_NUMBER (loperands[4]));
1015 output_asm_insn ("shi %5", loperands);
1016 break;
1017
1018 case LT:
1019 loperands[6] = gen_label_rtx();
1020#ifdef MOTOROLA
1021 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1022#else
1023 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1024#endif
1025 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1026 CODE_LABEL_NUMBER (loperands[4]));
1027 output_asm_insn ("slt %5", loperands);
1028 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1029 CODE_LABEL_NUMBER (loperands[6]));
1030 break;
1031
1032 case LTU:
1033 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1034 CODE_LABEL_NUMBER (loperands[4]));
1035 output_asm_insn ("scs %5", loperands);
1036 break;
1037
1038 case GE:
1039 loperands[6] = gen_label_rtx();
1040#ifdef MOTOROLA
1041 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1042#else
1043 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1044#endif
1045 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1046 CODE_LABEL_NUMBER (loperands[4]));
1047 output_asm_insn ("sge %5", loperands);
1048 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1049 CODE_LABEL_NUMBER (loperands[6]));
1050 break;
1051
1052 case GEU:
1053 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1054 CODE_LABEL_NUMBER (loperands[4]));
1055 output_asm_insn ("scc %5", loperands);
1056 break;
1057
1058 case LE:
1059 loperands[6] = gen_label_rtx();
1060#ifdef MOTOROLA
1061 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1062#else
1063 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1064#endif
1065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1066 CODE_LABEL_NUMBER (loperands[4]));
1067 output_asm_insn ("sle %5", loperands);
1068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1069 CODE_LABEL_NUMBER (loperands[6]));
1070 break;
1071
1072 case LEU:
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1074 CODE_LABEL_NUMBER (loperands[4]));
1075 output_asm_insn ("sls %5", loperands);
1076 break;
1077
1078 default:
1079 abort ();
1080 }
1081 return "";
1082}
1083
79e68feb
RS		 1084char *
1085output_btst (operands, countop, dataop, insn, signpos)
1086 rtx *operands;
1087 rtx countop, dataop;
1088 rtx insn;
1089 int signpos;
1090{
1091 operands[0] = countop;
1092 operands[1] = dataop;
1093
1094 if (GET_CODE (countop) == CONST_INT)
1095 {
1096 register int count = INTVAL (countop);
1097 /* If COUNT is bigger than size of storage unit in use,
1098 advance to the containing unit of same size. */
1099 if (count > signpos)
1100 {
1101 int offset = (count & ~signpos) / 8;
1102 count = count & signpos;
1103 operands[1] = dataop = adj_offsettable_operand (dataop, offset);
1104 }
1105 if (count == signpos)
1106 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1107 else
1108 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1109
1110 /* These three statements used to use next_insns_test_no...
1111 but it appears that this should do the same job. */
1112 if (count == 31
1113 && next_insn_tests_no_inequality (insn))
1114 return "tst%.l %1";
1115 if (count == 15
1116 && next_insn_tests_no_inequality (insn))
1117 return "tst%.w %1";
1118 if (count == 7
1119 && next_insn_tests_no_inequality (insn))
1120 return "tst%.b %1";
1121
1122 cc_status.flags = CC_NOT_NEGATIVE;
1123 }
1124 return "btst %0,%1";
1125}
1126\f
1127/* Returns 1 if OP is either a symbol reference or a sum of a symbol
1128 reference and a constant. */
1129
1130int
1131symbolic_operand (op, mode)
1132 register rtx op;
1133 enum machine_mode mode;
1134{
1135 switch (GET_CODE (op))
1136 {
1137 case SYMBOL_REF:
1138 case LABEL_REF:
1139 return 1;
1140
1141 case CONST:
1142 op = XEXP (op, 0);
1143 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1144 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1145 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1146
1147#if 0 /* Deleted, with corresponding change in m68k.h,
1148 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1149 case CONST_DOUBLE:
1150 return GET_MODE (op) == mode;
1151#endif
1152
1153 default:
1154 return 0;
1155 }
1156}
16f323be
RK		 1157\f
1158/* Check for sign_extend or zero_extend. Used for bit-count operands. */
1159
1160int
1161extend_operator(x, mode)
1162 rtx x;
1163 enum machine_mode mode;
1164{
c59c3b1c 1165 if (mode != VOIDmode && GET_MODE(x) != mode)
16f323be
RK		 1166 return 0;
1167 switch (GET_CODE(x))
1168 {
1169 case SIGN_EXTEND :
1170 case ZERO_EXTEND :
16f323be
RK		 1171 return 1;
1172 default :
1173 return 0;
1174 }
1175}
79e68feb
RS		 1176
1177\f
1178/* Legitimize PIC addresses. If the address is already
1179 position-independent, we return ORIG. Newly generated
1180 position-independent addresses go to REG. If we need more
1181 than one register, we lose.
1182
1183 An address is legitimized by making an indirect reference
1184 through the Global Offset Table with the name of the symbol
1185 used as an offset.
1186
1187 The assembler and linker are responsible for placing the
1188 address of the symbol in the GOT. The function prologue
1189 is responsible for initializing a5 to the starting address
1190 of the GOT.
1191
1192 The assembler is also responsible for translating a symbol name
1193 into a constant displacement from the start of the GOT.
1194
1195 A quick example may make things a little clearer:
1196
1197 When not generating PIC code to store the value 12345 into _foo
1198 we would generate the following code:
1199
1200 movel #12345, _foo
1201
1202 When generating PIC two transformations are made. First, the compiler
1203 loads the address of foo into a register. So the first transformation makes:
1204
1205 lea _foo, a0
1206 movel #12345, a0@
1207
1208 The code in movsi will intercept the lea instruction and call this
1209 routine which will transform the instructions into:
1210
1211 movel a5@(_foo:w), a0
1212 movel #12345, a0@
1213
1214
1215 That (in a nutshell) is how *all* symbol and label references are
1216 handled. */
1217
1218rtx
1219legitimize_pic_address (orig, mode, reg)
1220 rtx orig, reg;
1221 enum machine_mode mode;
1222{
1223 rtx pic_ref = orig;
1224
1225 /* First handle a simple SYMBOL_REF or LABEL_REF */
1226 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1227 {
1228 if (reg == 0)
1229 abort ();
1230
1231 pic_ref = gen_rtx (MEM, Pmode,
1232 gen_rtx (PLUS, Pmode,
1233 pic_offset_table_rtx, orig));
1234 current_function_uses_pic_offset_table = 1;
1235 RTX_UNCHANGING_P (pic_ref) = 1;
1236 emit_move_insn (reg, pic_ref);
1237 return reg;
1238 }
1239 else if (GET_CODE (orig) == CONST)
1240 {
1241 rtx base, offset;
1242
1243 /* Make sure this is CONST has not already been legitimized */
1244 if (GET_CODE (XEXP (orig, 0)) == PLUS
1245 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1246 return orig;
1247
1248 if (reg == 0)
1249 abort ();
1250
1251 /* legitimize both operands of the PLUS */
1252 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1253 {
1254 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1255 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1256 base == reg ? 0 : reg);
1257 }
1258 else abort ();
1259
1260 if (GET_CODE (orig) == CONST_INT)
1261 return plus_constant_for_output (base, INTVAL (orig));
1262 pic_ref = gen_rtx (PLUS, Pmode, base, orig);
1263 /* Likewise, should we set special REG_NOTEs here? */
1264 }
1265 return pic_ref;
1266}
1267
1268\f
0ce6f9fb
RK		 1269typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1270
6910dd70 1271#define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
0ce6f9fb
RK		 1272
1273CONST_METHOD
1274const_method (constant)
1275 rtx constant;
1276{
1277 int i;
1278 unsigned u;
1279
1280 i = INTVAL (constant);
6910dd70 1281 if (USE_MOVQ (i))
0ce6f9fb 1282 return MOVQ;
24092242
RK		 1283
1284 /* The Coldfire doesn't have byte or word operations. */
1285 /* FIXME: This may not be useful for the m68060 either */
1286 if (!TARGET_5200)
1287 {
1288 /* if -256 < N < 256 but N is not in range for a moveq
1289 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1290 if (USE_MOVQ (i ^ 0xff))
1291 return NOTB;
1292 /* Likewise, try with not.w */
1293 if (USE_MOVQ (i ^ 0xffff))
1294 return NOTW;
1295 /* This is the only value where neg.w is useful */
1296 if (i == -65408)
1297 return NEGW;
1298 /* Try also with swap */
1299 u = i;
1300 if (USE_MOVQ ((u >> 16) | (u << 16)))
1301 return SWAP;
1302 }
0ce6f9fb
RK		 1303 /* Otherwise, use move.l */
1304 return MOVL;
1305}
1306
1307const_int_cost (constant)
1308 rtx constant;
1309{
1310 switch (const_method (constant))
1311 {
1312 case MOVQ :
1313 /* Constants between -128 and 127 are cheap due to moveq */
1314 return 0;
1315 case NOTB :
1316 case NOTW :
1317 case NEGW :
1318 case SWAP :
1319 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1320 return 1;
1321 case MOVL :
1322 return 2;
1323 default :
1324 abort ();
1325 }
1326}
1327
1328char *
1329output_move_const_into_data_reg (operands)
1330 rtx *operands;
1331{
1332 int i;
1333
1334 i = INTVAL (operands[1]);
1335 switch (const_method (operands[1]))
1336 {
1337 case MOVQ :
1338#if defined (MOTOROLA) && !defined (CRDS)
1339 return "moveq%.l %1,%0";
1340#else
1341 return "moveq %1,%0";
1342#endif
1343 case NOTB :
1344 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xff);
1345#if defined (MOTOROLA) && !defined (CRDS)
1346 return "moveq%.l %1,%0\n\tnot%.b %0";
1347#else
1348 return "moveq %1,%0\n\tnot%.b %0";
1349#endif
1350 case NOTW :
1351 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xffff);
1352#if defined (MOTOROLA) && !defined (CRDS)
1353 return "moveq%.l %1,%0\n\tnot%.w %0";
1354#else
1355 return "moveq %1,%0\n\tnot%.w %0";
1356#endif
1357 case NEGW :
1358#if defined (MOTOROLA) && !defined (CRDS)
1359 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1360#else
1361 return "moveq %#-128,%0\n\tneg%.w %0";
1362#endif
1363 case SWAP :
1364 {
1365 unsigned u = i;
1366
1367 operands[1] = gen_rtx (CONST_INT, VOIDmode, (u << 16) | (u >> 16));
1368#if defined (MOTOROLA) && !defined (CRDS)
1369 return "moveq%.l %1,%0\n\tswap %0";
1370#else
1371 return "moveq %1,%0\n\tswap %0";
1372#endif
1373 }
1374 case MOVL :
1375 return "move%.l %1,%0";
1376 default :
1377 abort ();
1378 }
1379}
1380
02ed0c07
RK		 1381char *
1382output_move_simode_const (operands)
1383 rtx *operands;
1384{
1385 if (operands[1] == const0_rtx
1386 && (DATA_REG_P (operands[0])
1387 || GET_CODE (operands[0]) == MEM)
1388 /* clr insns on 68000 read before writing.
c67ddce5 1389 This isn't so on the 68010, but we have no TARGET_68010. */
0cb7cfed 1390 && ((TARGET_68020 || TARGET_5200)
02ed0c07
RK		 1391 || !(GET_CODE (operands[0]) == MEM
1392 && MEM_VOLATILE_P (operands[0]))))
1393 return "clr%.l %0";
1394 else if (DATA_REG_P (operands[0]))
1395 return output_move_const_into_data_reg (operands);
1396 else if (ADDRESS_REG_P (operands[0])
1397 && INTVAL (operands[1]) < 0x8000
1398 && INTVAL (operands[1]) >= -0x8000)
1399 return "move%.w %1,%0";
1400 else if (GET_CODE (operands[0]) == MEM
1401 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1402 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1403 && INTVAL (operands[1]) < 0x8000
1404 && INTVAL (operands[1]) >= -0x8000)
1405 return "pea %a1";
1406 return "move%.l %1,%0";
1407}
1408
f4e80198
RK		 1409char *
1410output_move_simode (operands)
1411 rtx *operands;
1412{
1413 if (GET_CODE (operands[1]) == CONST_INT)
1414 return output_move_simode_const (operands);
1415 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1416 || GET_CODE (operands[1]) == CONST)
1417 && push_operand (operands[0], SImode))
1418 return "pea %a1";
1419 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1420 || GET_CODE (operands[1]) == CONST)
1421 && ADDRESS_REG_P (operands[0]))
1422 return "lea %a1,%0";
1423 return "move%.l %1,%0";
1424}
1425
1426char *
1427output_move_himode (operands)
1428 rtx *operands;
1429{
1430 if (GET_CODE (operands[1]) == CONST_INT)
1431 {
1432 if (operands[1] == const0_rtx
1433 && (DATA_REG_P (operands[0])
1434 || GET_CODE (operands[0]) == MEM)
1435 /* clr insns on 68000 read before writing.
1436 This isn't so on the 68010, but we have no TARGET_68010. */
1437 && ((TARGET_68020 || TARGET_5200)
1438 || !(GET_CODE (operands[0]) == MEM
1439 && MEM_VOLATILE_P (operands[0]))))
1440 return "clr%.w %0";
1441 else if (DATA_REG_P (operands[0])
1442 && INTVAL (operands[1]) < 128
1443 && INTVAL (operands[1]) >= -128)
1444 {
1445#if defined(MOTOROLA) && !defined(CRDS)
1446 return "moveq%.l %1,%0";
1447#else
1448 return "moveq %1,%0";
1449#endif
1450 }
1451 else if (INTVAL (operands[1]) < 0x8000
1452 && INTVAL (operands[1]) >= -0x8000)
1453 return "move%.w %1,%0";
1454 }
1455 else if (CONSTANT_P (operands[1]))
1456 return "move%.l %1,%0";
1457#ifndef SGS_NO_LI
1458 /* Recognize the insn before a tablejump, one that refers
1459 to a table of offsets. Such an insn will need to refer
1460 to a label on the insn. So output one. Use the label-number
1461 of the table of offsets to generate this label. This code,
1462 and similar code below, assumes that there will be at most one
1463 reference to each table. */
1464 if (GET_CODE (operands[1]) == MEM
1465 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1466 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1467 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1468 {
1469 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1470#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1471#ifdef SGS
1472 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1473 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1474#else /* not SGS */
1475 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1476 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1477#endif /* not SGS */
1478#else /* SGS_SWITCH_TABLES or not MOTOROLA */
1479 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
1480 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1481#ifdef SGS_SWITCH_TABLES
1482 /* Set flag saying we need to define the symbol
1483 LD%n (with value L%n-LI%n) at the end of the switch table. */
1484 switch_table_difference_label_flag = 1;
1485#endif /* SGS_SWITCH_TABLES */
1486#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1487 }
1488#endif /* SGS_NO_LI */
1489 return "move%.w %1,%0";
1490}
1491
1492char *
1493output_move_qimode (operands)
1494 rtx *operands;
1495{
1496 rtx xoperands[4];
1497
1498 /* This is probably useless, since it loses for pushing a struct
1499 of several bytes a byte at a time. */
102701ff
JW		 1500 /* 68k family always modifies the stack pointer by at least 2, even for
1501 byte pushes. The 5200 (coldfire) does not do this. */
f4e80198
RK		 1502 if (GET_CODE (operands[0]) == MEM
1503 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1504 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
102701ff
JW		 1505 && ! ADDRESS_REG_P (operands[1])
1506 && ! TARGET_5200)
f4e80198
RK		 1507 {
1508 xoperands[1] = operands[1];
1509 xoperands[2]
1510 = gen_rtx (MEM, QImode,
1511 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
1512 /* Just pushing a byte puts it in the high byte of the halfword. */
1513 /* We must put it in the low-order, high-numbered byte. */
3879920c
RK		 1514 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1515 {
1516 xoperands[3] = stack_pointer_rtx;
1517#ifndef NO_ADDSUB_Q
1518 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1519#else
1520 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1521#endif
1522 }
1523 else
1524 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
f4e80198
RK		 1525 return "";
1526 }
1527
1528 /* clr and st insns on 68000 read before writing.
1529 This isn't so on the 68010, but we have no TARGET_68010. */
1530 if (!ADDRESS_REG_P (operands[0])
1531 && ((TARGET_68020 || TARGET_5200)
1532 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1533 {
1534 if (operands[1] == const0_rtx)
1535 return "clr%.b %0";
1536 if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1537 && GET_CODE (operands[1]) == CONST_INT
1538 && (INTVAL (operands[1]) & 255) == 255)
1539 {
1540 CC_STATUS_INIT;
1541 return "st %0";
1542 }
1543 }
1544 if (GET_CODE (operands[1]) == CONST_INT
1545 && DATA_REG_P (operands[0])
1546 && INTVAL (operands[1]) < 128
1547 && INTVAL (operands[1]) >= -128)
1548 {
1549#if defined(MOTOROLA) && !defined(CRDS)
1550 return "moveq%.l %1,%0";
1551#else
1552 return "moveq %1,%0";
1553#endif
1554 }
1555 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1556 return "move%.l %1,%0";
102701ff
JW		 1557 /* 68k family doesn't support byte moves to from address registers. The
1558 5200 (coldfire) does not have this restriction. */
1559 if ((ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1560 && ! TARGET_5200)
f4e80198
RK		 1561 return "move%.w %1,%0";
1562 return "move%.b %1,%0";
1563}
1564
9b55bf04
RK		 1565char *
1566output_move_stricthi (operands)
1567 rtx *operands;
1568{
1569 if (operands[1] == const0_rtx
1570 /* clr insns on 68000 read before writing.
1571 This isn't so on the 68010, but we have no TARGET_68010. */
1572 && ((TARGET_68020 || TARGET_5200)
1573 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1574 return "clr%.w %0";
1575 return "move%.w %1,%0";
1576}
1577
1578char *
1579output_move_strictqi (operands)
1580 rtx *operands;
1581{
1582 if (operands[1] == const0_rtx
1583 /* clr insns on 68000 read before writing.
1584 This isn't so on the 68010, but we have no TARGET_68010. */
1585 && ((TARGET_68020 || TARGET_5200)
1586 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1587 return "clr%.b %0";
1588 return "move%.b %1,%0";
1589}
1590
79e68feb
RS		 1591/* Return the best assembler insn template
1592 for moving operands[1] into operands[0] as a fullword. */
1593
1594static char *
1595singlemove_string (operands)
1596 rtx *operands;
1597{
1598#ifdef SUPPORT_SUN_FPA
1599 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1600 return "fpmoves %1,%0";
1601#endif
02ed0c07
RK		 1602 if (GET_CODE (operands[1]) == CONST_INT)
1603 return output_move_simode_const (operands);
1604 return "move%.l %1,%0";
79e68feb
RS		 1605}
1606
2505bc97 1607
79e68feb
RS		 1608/* Output assembler code to perform a doubleword move insn
1609 with operands OPERANDS. */
1610
1611char *
1612output_move_double (operands)
1613 rtx *operands;
1614{
2505bc97
RS		 1615 enum
1616 {
1617 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1618 } optype0, optype1;
79e68feb 1619 rtx latehalf[2];
2505bc97 1620 rtx middlehalf[2];
7f98eeb6 1621 rtx xops[2];
79e68feb 1622 rtx addreg0 = 0, addreg1 = 0;
7f98eeb6 1623 int dest_overlapped_low = 0;
184916bc 1624 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2505bc97
RS		 1625
1626 middlehalf[0] = 0;
1627 middlehalf[1] = 0;
79e68feb
RS		 1628
1629 /* First classify both operands. */
1630
1631 if (REG_P (operands[0]))
1632 optype0 = REGOP;
1633 else if (offsettable_memref_p (operands[0]))
1634 optype0 = OFFSOP;
1635 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1636 optype0 = POPOP;
1637 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1638 optype0 = PUSHOP;
1639 else if (GET_CODE (operands[0]) == MEM)
1640 optype0 = MEMOP;
1641 else
1642 optype0 = RNDOP;
1643
1644 if (REG_P (operands[1]))
1645 optype1 = REGOP;
1646 else if (CONSTANT_P (operands[1]))
1647 optype1 = CNSTOP;
1648 else if (offsettable_memref_p (operands[1]))
1649 optype1 = OFFSOP;
1650 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1651 optype1 = POPOP;
1652 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1653 optype1 = PUSHOP;
1654 else if (GET_CODE (operands[1]) == MEM)
1655 optype1 = MEMOP;
1656 else
1657 optype1 = RNDOP;
1658
1659 /* Check for the cases that the operand constraints are not
1660 supposed to allow to happen. Abort if we get one,
1661 because generating code for these cases is painful. */
1662
1663 if (optype0 == RNDOP || optype1 == RNDOP)
1664 abort ();
1665
1666 /* If one operand is decrementing and one is incrementing
1667 decrement the former register explicitly
1668 and change that operand into ordinary indexing. */
1669
1670 if (optype0 == PUSHOP && optype1 == POPOP)
1671 {
1672 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2505bc97
RS		 1673 if (size == 12)
1674 output_asm_insn ("sub%.l %#12,%0", operands);
1675 else
1676 output_asm_insn ("subq%.l %#8,%0", operands);
1677 if (GET_MODE (operands[1]) == XFmode)
1678 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
1679 else if (GET_MODE (operands[0]) == DFmode)
1680 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
1681 else
1682 operands[0] = gen_rtx (MEM, DImode, operands[0]);
79e68feb
RS		 1683 optype0 = OFFSOP;
1684 }
1685 if (optype0 == POPOP && optype1 == PUSHOP)
1686 {
1687 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2505bc97
RS		 1688 if (size == 12)
1689 output_asm_insn ("sub%.l %#12,%1", operands);
1690 else
1691 output_asm_insn ("subq%.l %#8,%1", operands);
1692 if (GET_MODE (operands[1]) == XFmode)
1693 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
1694 else if (GET_MODE (operands[1]) == DFmode)
1695 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
1696 else
1697 operands[1] = gen_rtx (MEM, DImode, operands[1]);
79e68feb
RS		 1698 optype1 = OFFSOP;
1699 }
1700
1701 /* If an operand is an unoffsettable memory ref, find a register
1702 we can increment temporarily to make it refer to the second word. */
1703
1704 if (optype0 == MEMOP)
1705 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1706
1707 if (optype1 == MEMOP)
1708 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1709
1710 /* Ok, we can do one word at a time.
1711 Normally we do the low-numbered word first,
1712 but if either operand is autodecrementing then we
1713 do the high-numbered word first.
1714
1715 In either case, set up in LATEHALF the operands to use
1716 for the high-numbered word and in some cases alter the
1717 operands in OPERANDS to be suitable for the low-numbered word. */
1718
2505bc97
RS		 1719 if (size == 12)
1720 {
1721 if (optype0 == REGOP)
1722 {
1723 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
1724 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1725 }
1726 else if (optype0 == OFFSOP)
1727 {
1728 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1729 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1730 }
1731 else
1732 {
1733 middlehalf[0] = operands[0];
1734 latehalf[0] = operands[0];
1735 }
1736
1737 if (optype1 == REGOP)
1738 {
1739 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1740 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1741 }
1742 else if (optype1 == OFFSOP)
1743 {
1744 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1745 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1746 }
1747 else if (optype1 == CNSTOP)
1748 {
1749 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1750 {
1751 REAL_VALUE_TYPE r;
1752 long l[3];
1753
1754 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1755 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1756 operands[1] = GEN_INT (l[0]);
1757 middlehalf[1] = GEN_INT (l[1]);
1758 latehalf[1] = GEN_INT (l[2]);
1759 }
1760 else if (CONSTANT_P (operands[1]))
1761 {
1762 /* actually, no non-CONST_DOUBLE constant should ever
1763 appear here. */
1764 abort ();
1765 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
1766 latehalf[1] = constm1_rtx;
1767 else
1768 latehalf[1] = const0_rtx;
1769 }
1770 }
1771 else
1772 {
1773 middlehalf[1] = operands[1];
1774 latehalf[1] = operands[1];
1775 }
1776 }
79e68feb 1777 else
2505bc97
RS		 1778 /* size is not 12: */
1779 {
1780 if (optype0 == REGOP)
1781 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1782 else if (optype0 == OFFSOP)
1783 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1784 else
1785 latehalf[0] = operands[0];
1786
1787 if (optype1 == REGOP)
1788 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1789 else if (optype1 == OFFSOP)
1790 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1791 else if (optype1 == CNSTOP)
1792 split_double (operands[1], &operands[1], &latehalf[1]);
1793 else
1794 latehalf[1] = operands[1];
1795 }
79e68feb
RS		 1796
1797 /* If insn is effectively movd N(sp),-(sp) then we will do the
1798 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1799 for the low word as well, to compensate for the first decrement of sp. */
1800 if (optype0 == PUSHOP
1801 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1802 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
c88aeaf8 1803 operands[1] = middlehalf[1] = latehalf[1];
79e68feb 1804
7f98eeb6
RS		 1805 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1806 if the upper part of reg N does not appear in the MEM, arrange to
1807 emit the move late-half first. Otherwise, compute the MEM address
1808 into the upper part of N and use that as a pointer to the memory
1809 operand. */
1810 if (optype0 == REGOP
1811 && (optype1 == OFFSOP || optype1 == MEMOP))
1812 {
3a58400f
RS		 1813 rtx testlow = gen_rtx (REG, SImode, REGNO (operands[0]));
1814
1815 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
d7e8d581 1816 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
7f98eeb6
RS		 1817 {
1818 /* If both halves of dest are used in the src memory address,
3a58400f
RS		 1819 compute the address into latehalf of dest.
1820 Note that this can't happen if the dest is two data regs. */
7f98eeb6
RS		 1821compadr:
1822 xops[0] = latehalf[0];
1823 xops[1] = XEXP (operands[1], 0);
d7e8d581 1824 output_asm_insn ("lea %a1,%0", xops);
7f98eeb6
RS		 1825 if( GET_MODE (operands[1]) == XFmode )
1826 {
1827 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
1828 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1829 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1830 }
1831 else
1832 {
1833 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
1834 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1835 }
1836 }
1837 else if (size == 12
d7e8d581
RS		 1838 && reg_overlap_mentioned_p (middlehalf[0],
1839 XEXP (operands[1], 0)))
7f98eeb6 1840 {
3a58400f
RS		 1841 /* Check for two regs used by both source and dest.
1842 Note that this can't happen if the dest is all data regs.
1843 It can happen if the dest is d6, d7, a0.
1844 But in that case, latehalf is an addr reg, so
1845 the code at compadr does ok. */
1846
1847 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
d7e8d581
RS		 1848 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1849 goto compadr;
7f98eeb6
RS		 1850
1851 /* JRV says this can't happen: */
1852 if (addreg0 || addreg1)
d7e8d581 1853 abort ();
7f98eeb6
RS		 1854
1855 /* Only the middle reg conflicts; simply put it last. */
1856 output_asm_insn (singlemove_string (operands), operands);
1857 output_asm_insn (singlemove_string (latehalf), latehalf);
1858 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1859 return "";
1860 }
2fb8a81d 1861 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
7f98eeb6
RS		 1862 /* If the low half of dest is mentioned in the source memory
1863 address, the arrange to emit the move late half first. */
1864 dest_overlapped_low = 1;
1865 }
1866
79e68feb
RS		 1867 /* If one or both operands autodecrementing,
1868 do the two words, high-numbered first. */
1869
1870 /* Likewise, the first move would clobber the source of the second one,
1871 do them in the other order. This happens only for registers;
1872 such overlap can't happen in memory unless the user explicitly
1873 sets it up, and that is an undefined circumstance. */
1874
1875 if (optype0 == PUSHOP || optype1 == PUSHOP
1876 || (optype0 == REGOP && optype1 == REGOP
2505bc97 1877 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
7f98eeb6
RS		 1878 || REGNO (operands[0]) == REGNO (latehalf[1])))
1879 || dest_overlapped_low)
79e68feb
RS		 1880 {
1881 /* Make any unoffsettable addresses point at high-numbered word. */
1882 if (addreg0)
2505bc97
RS		 1883 {
1884 if (size == 12)
07eced4d 1885 output_asm_insn ("addq%.l %#8,%0", &addreg0);
2505bc97 1886 else
07eced4d 1887 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2505bc97 1888 }
79e68feb 1889 if (addreg1)
2505bc97
RS		 1890 {
1891 if (size == 12)
07eced4d 1892 output_asm_insn ("addq%.l %#8,%0", &addreg1);
2505bc97 1893 else
07eced4d 1894 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2505bc97 1895 }
79e68feb
RS		 1896
1897 /* Do that word. */
1898 output_asm_insn (singlemove_string (latehalf), latehalf);
1899
1900 /* Undo the adds we just did. */
1901 if (addreg0)
07eced4d 1902 output_asm_insn ("subq%.l %#4,%0", &addreg0);
79e68feb 1903 if (addreg1)
07eced4d 1904 output_asm_insn ("subq%.l %#4,%0", &addreg1);
79e68feb 1905
2505bc97
RS		 1906 if (size == 12)
1907 {
1908 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1909 if (addreg0)
07eced4d 1910 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2505bc97 1911 if (addreg1)
07eced4d 1912 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2505bc97
RS		 1913 }
1914
79e68feb
RS		 1915 /* Do low-numbered word. */
1916 return singlemove_string (operands);
1917 }
1918
1919 /* Normal case: do the two words, low-numbered first. */
1920
1921 output_asm_insn (singlemove_string (operands), operands);
1922
2505bc97
RS		 1923 /* Do the middle one of the three words for long double */
1924 if (size == 12)
1925 {
1926 if (addreg0)
07eced4d 1927 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2505bc97 1928 if (addreg1)
07eced4d 1929 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2505bc97
RS		 1930
1931 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1932 }
1933
79e68feb
RS		 1934 /* Make any unoffsettable addresses point at high-numbered word. */
1935 if (addreg0)
07eced4d 1936 output_asm_insn ("addq%.l %#4,%0", &addreg0);
79e68feb 1937 if (addreg1)
07eced4d 1938 output_asm_insn ("addq%.l %#4,%0", &addreg1);
79e68feb
RS		 1939
1940 /* Do that word. */
1941 output_asm_insn (singlemove_string (latehalf), latehalf);
1942
1943 /* Undo the adds we just did. */
1944 if (addreg0)
2505bc97
RS		 1945 {
1946 if (size == 12)
07eced4d 1947 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2505bc97 1948 else
07eced4d 1949 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2505bc97 1950 }
79e68feb 1951 if (addreg1)
2505bc97
RS		 1952 {
1953 if (size == 12)
07eced4d 1954 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2505bc97 1955 else
07eced4d 1956 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2505bc97 1957 }
79e68feb
RS		 1958
1959 return "";
1960}
1961
1962/* Return a REG that occurs in ADDR with coefficient 1.
1963 ADDR can be effectively incremented by incrementing REG. */
1964
1965static rtx
1966find_addr_reg (addr)
1967 rtx addr;
1968{
1969 while (GET_CODE (addr) == PLUS)
1970 {
1971 if (GET_CODE (XEXP (addr, 0)) == REG)
1972 addr = XEXP (addr, 0);
1973 else if (GET_CODE (XEXP (addr, 1)) == REG)
1974 addr = XEXP (addr, 1);
1975 else if (CONSTANT_P (XEXP (addr, 0)))
1976 addr = XEXP (addr, 1);
1977 else if (CONSTANT_P (XEXP (addr, 1)))
1978 addr = XEXP (addr, 0);
1979 else
1980 abort ();
1981 }
1982 if (GET_CODE (addr) == REG)
1983 return addr;
1984 abort ();
1985}
9ee3c687
JW		 1986
1987/* Output assembler code to perform a 32 bit 3 operand add. */
1988
1989char *
1990output_addsi3 (operands)
1991 rtx *operands;
1992{
1993 if (! operands_match_p (operands[0], operands[1]))
1994 {
1995 if (!ADDRESS_REG_P (operands[1]))
1996 {
1997 rtx tmp = operands[1];
1998
1999 operands[1] = operands[2];
2000 operands[2] = tmp;
2001 }
2002
2003 /* These insns can result from reloads to access
2004 stack slots over 64k from the frame pointer. */
2005 if (GET_CODE (operands[2]) == CONST_INT
2006 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
8c61b6c1 2007 return "move%.l %2,%0\n\tadd%.l %1,%0";
9ee3c687
JW		 2008#ifdef SGS
2009 if (GET_CODE (operands[2]) == REG)
2010 return "lea 0(%1,%2.l),%0";
2011 else
2012 return "lea %c2(%1),%0";
2013#else /* not SGS */
2014#ifdef MOTOROLA
2015 if (GET_CODE (operands[2]) == REG)
2016 return "lea (%1,%2.l),%0";
2017 else
2018 return "lea (%c2,%1),%0";
2019#else /* not MOTOROLA (MIT syntax) */
2020 if (GET_CODE (operands[2]) == REG)
2021 return "lea %1@(0,%2:l),%0";
2022 else
2023 return "lea %1@(%c2),%0";
2024#endif /* not MOTOROLA */
2025#endif /* not SGS */
2026 }
2027 if (GET_CODE (operands[2]) == CONST_INT)
2028 {
2029#ifndef NO_ADDSUB_Q
2030 if (INTVAL (operands[2]) > 0
2031 && INTVAL (operands[2]) <= 8)
2032 return "addq%.l %2,%0";
2033 if (INTVAL (operands[2]) < 0
2034 && INTVAL (operands[2]) >= -8)
2035 {
2036 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2037 - INTVAL (operands[2]));
2038 return "subq%.l %2,%0";
2039 }
2040 /* On the CPU32 it is faster to use two addql instructions to
2041 add a small integer (8 < N <= 16) to a register.
2042 Likewise for subql. */
2043 if (TARGET_CPU32 && REG_P (operands[0]))
2044 {
2045 if (INTVAL (operands[2]) > 8
2046 && INTVAL (operands[2]) <= 16)
2047 {
2048 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2049 INTVAL (operands[2]) - 8);
8c61b6c1 2050 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
9ee3c687
JW		 2051 }
2052 if (INTVAL (operands[2]) < -8
2053 && INTVAL (operands[2]) >= -16)
2054 {
2055 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2056 - INTVAL (operands[2]) - 8);
8c61b6c1 2057 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
9ee3c687
JW		 2058 }
2059 }
2060#endif
2061 if (ADDRESS_REG_P (operands[0])
2062 && INTVAL (operands[2]) >= -0x8000
2063 && INTVAL (operands[2]) < 0x8000)
2064 {
2065 if (TARGET_68040)
2066 return "add%.w %2,%0";
2067 else
2068#ifdef MOTOROLA
2069 return "lea (%c2,%0),%0";
2070#else
2071 return "lea %0@(%c2),%0";
2072#endif
2073 }
2074 }
2075 return "add%.l %2,%0";
2076}
79e68feb
RS		 2077\f
2078/* Store in cc_status the expressions that the condition codes will
2079 describe after execution of an instruction whose pattern is EXP.
2080 Do not alter them if the instruction would not alter the cc's. */
2081
2082/* On the 68000, all the insns to store in an address register fail to
2083 set the cc's. However, in some cases these instructions can make it
2084 possibly invalid to use the saved cc's. In those cases we clear out
2085 some or all of the saved cc's so they won't be used. */
2086
2087notice_update_cc (exp, insn)
2088 rtx exp;
2089 rtx insn;
2090{
2091 /* If the cc is being set from the fpa and the expression is not an
2092 explicit floating point test instruction (which has code to deal with
2093 this), reinit the CC. */
2094 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
2095 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
2096 && !(GET_CODE (exp) == PARALLEL
2097 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
2098 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
2099 {
2100 CC_STATUS_INIT;
2101 }
2102 else if (GET_CODE (exp) == SET)
2103 {
2104 if (GET_CODE (SET_SRC (exp)) == CALL)
2105 {
2106 CC_STATUS_INIT;
2107 }
2108 else if (ADDRESS_REG_P (SET_DEST (exp)))
2109 {
2110 if (cc_status.value1
2111 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
2112 cc_status.value1 = 0;
2113 if (cc_status.value2
2114 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
2115 cc_status.value2 = 0;
2116 }
2117 else if (!FP_REG_P (SET_DEST (exp))
2118 && SET_DEST (exp) != cc0_rtx
2119 && (FP_REG_P (SET_SRC (exp))
2120 || GET_CODE (SET_SRC (exp)) == FIX
2121 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2122 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2123 {
2124 CC_STATUS_INIT;
2125 }
2126 /* A pair of move insns doesn't produce a useful overall cc. */
2127 else if (!FP_REG_P (SET_DEST (exp))
2128 && !FP_REG_P (SET_SRC (exp))
2129 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2130 && (GET_CODE (SET_SRC (exp)) == REG
2131 || GET_CODE (SET_SRC (exp)) == MEM
2132 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2133 {
2134 CC_STATUS_INIT;
2135 }
2136 else if (GET_CODE (SET_SRC (exp)) == CALL)
2137 {
2138 CC_STATUS_INIT;
2139 }
2140 else if (XEXP (exp, 0) != pc_rtx)
2141 {
2142 cc_status.flags = 0;
2143 cc_status.value1 = XEXP (exp, 0);
2144 cc_status.value2 = XEXP (exp, 1);
2145 }
2146 }
2147 else if (GET_CODE (exp) == PARALLEL
2148 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2149 {
2150 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2151 CC_STATUS_INIT;
2152 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2153 {
2154 cc_status.flags = 0;
2155 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2156 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2157 }
2158 }
2159 else
2160 CC_STATUS_INIT;
2161 if (cc_status.value2 != 0
2162 && ADDRESS_REG_P (cc_status.value2)
2163 && GET_MODE (cc_status.value2) == QImode)
2164 CC_STATUS_INIT;
2165 if (cc_status.value2 != 0
2166 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
2167 switch (GET_CODE (cc_status.value2))
2168 {
2169 case PLUS: case MINUS: case MULT:
2170 case DIV: case UDIV: case MOD: case UMOD: case NEG:
b757e352 2171#if 0 /* These instructions always clear the overflow bit */
996a5f59 2172 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
79e68feb 2173 case ROTATE: case ROTATERT:
b757e352 2174#endif
79e68feb
RS		 2175 if (GET_MODE (cc_status.value2) != VOIDmode)
2176 cc_status.flags |= CC_NO_OVERFLOW;
2177 break;
2178 case ZERO_EXTEND:
2179 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2180 ends with a move insn moving r2 in r2's mode.
2181 Thus, the cc's are set for r2.
2182 This can set N bit spuriously. */
2183 cc_status.flags |= CC_NOT_NEGATIVE;
2184 }
2185 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2186 && cc_status.value2
2187 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2188 cc_status.value2 = 0;
2189 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2190 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
2191 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
2192 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
2193 cc_status.flags = CC_IN_68881;
2194}
2195\f
2196char *
2197output_move_const_double (operands)
2198 rtx *operands;
2199{
2200#ifdef SUPPORT_SUN_FPA
64a184e9 2201 if (TARGET_FPA && FPA_REG_P (operands[0]))
79e68feb
RS		 2202 {
2203 int code = standard_sun_fpa_constant_p (operands[1]);
2204
2205 if (code != 0)
2206 {
2207 static char buf[40];
2208
2209 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
2210 return buf;
2211 }
2212 return "fpmove%.d %1,%0";
2213 }
2214 else
2215#endif
2216 {
2217 int code = standard_68881_constant_p (operands[1]);
2218
2219 if (code != 0)
2220 {
2221 static char buf[40];
2222
2223 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2224 return buf;
2225 }
2226 return "fmove%.d %1,%0";
2227 }
2228}
2229
2230char *
2231output_move_const_single (operands)
2232 rtx *operands;
2233{
2234#ifdef SUPPORT_SUN_FPA
2235 if (TARGET_FPA)
2236 {
2237 int code = standard_sun_fpa_constant_p (operands[1]);
2238
2239 if (code != 0)
2240 {
2241 static char buf[40];
2242
2243 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
2244 return buf;
2245 }
2246 return "fpmove%.s %1,%0";
2247 }
2248 else
2249#endif /* defined SUPPORT_SUN_FPA */
2250 {
2251 int code = standard_68881_constant_p (operands[1]);
2252
2253 if (code != 0)
2254 {
2255 static char buf[40];
2256
2257 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2258 return buf;
2259 }
2260 return "fmove%.s %f1,%0";
2261 }
2262}
2263
2264/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2265 from the "fmovecr" instruction.
2266 The value, anded with 0xff, gives the code to use in fmovecr
2267 to get the desired constant. */
2268
c1cfb2ae
RS		 2269/* This code has been fixed for cross-compilation. */
2270
2271static int inited_68881_table = 0;
2272
2273char *strings_68881[7] = {
2274 "0.0",
2275 "1.0",
2276 "10.0",
2277 "100.0",
2278 "10000.0",
2279 "1e8",
2280 "1e16"
2281 };
2282
2283int codes_68881[7] = {
2284 0x0f,
2285 0x32,
2286 0x33,
2287 0x34,
2288 0x35,
2289 0x36,
2290 0x37
2291 };
2292
2293REAL_VALUE_TYPE values_68881[7];
2294
2295/* Set up values_68881 array by converting the decimal values
2296 strings_68881 to binary. */
2297
2298void
2299init_68881_table ()
2300{
2301 int i;
2302 REAL_VALUE_TYPE r;
2303 enum machine_mode mode;
2304
16d82c3c 2305 mode = SFmode;
c1cfb2ae
RS		 2306 for (i = 0; i < 7; i++)
2307 {
2308 if (i == 6)
16d82c3c 2309 mode = DFmode;
c1cfb2ae
RS		 2310 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2311 values_68881[i] = r;
2312 }
2313 inited_68881_table = 1;
2314}
79e68feb
RS		 2315
2316int
2317standard_68881_constant_p (x)
2318 rtx x;
2319{
c1cfb2ae
RS		 2320 REAL_VALUE_TYPE r;
2321 int i;
2322 enum machine_mode mode;
79e68feb 2323
a5d54cc5
RK		 2324#ifdef NO_ASM_FMOVECR
2325 return 0;
2326#endif
2327
2296cba3 2328 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
79e68feb
RS		 2329 if (TARGET_68040)
2330 return 0;
2331
c1cfb2ae 2332#ifndef REAL_ARITHMETIC
79e68feb
RS		 2333#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2334 if (! flag_pretend_float)
2335 return 0;
c1cfb2ae 2336#endif
79e68feb
RS		 2337#endif
2338
c1cfb2ae
RS		 2339 if (! inited_68881_table)
2340 init_68881_table ();
2341
2342 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2343
2344 for (i = 0; i < 6; i++)
2345 {
2346 if (REAL_VALUES_EQUAL (r, values_68881[i]))
2347 return (codes_68881[i]);
2348 }
2349
79e68feb
RS		 2350 if (GET_MODE (x) == SFmode)
2351 return 0;
c1cfb2ae
RS		 2352
2353 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2354 return (codes_68881[6]);
2355
79e68feb
RS		 2356 /* larger powers of ten in the constants ram are not used
2357 because they are not equal to a `double' C constant. */
2358 return 0;
2359}
2360
2361/* If X is a floating-point constant, return the logarithm of X base 2,
2362 or 0 if X is not a power of 2. */
2363
2364int
2365floating_exact_log2 (x)
2366 rtx x;
2367{
c1cfb2ae 2368 REAL_VALUE_TYPE r, r1;
79e68feb
RS		 2369 int i;
2370
c1cfb2ae 2371#ifndef REAL_ARITHMETIC
79e68feb
RS		 2372#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2373 if (! flag_pretend_float)
2374 return 0;
c1cfb2ae 2375#endif
79e68feb
RS		 2376#endif
2377
c1cfb2ae 2378 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
79e68feb 2379
c1cfb2ae 2380 if (REAL_VALUES_LESS (r, dconst0))
79e68feb
RS		 2381 return 0;
2382
6b62e557 2383 r1 = dconst1;
c1cfb2ae
RS		 2384 i = 0;
2385 while (REAL_VALUES_LESS (r1, r))
2386 {
2387 r1 = REAL_VALUE_LDEXP (dconst1, i);
2388 if (REAL_VALUES_EQUAL (r1, r))
2389 return i;
2390 i = i + 1;
2391 }
79e68feb
RS		 2392 return 0;
2393}
2394\f
2395#ifdef SUPPORT_SUN_FPA
2396/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2397 from the Sun FPA's constant RAM.
2398 The value returned, anded with 0x1ff, gives the code to use in fpmove
2399 to get the desired constant. */
c1cfb2ae
RS		 2400
2401static int inited_FPA_table = 0;
2402
2403char *strings_FPA[38] = {
2404/* small rationals */
2405 "0.0",
2406 "1.0",
2407 "0.5",
2408 "-1.0",
2409 "2.0",
2410 "3.0",
2411 "4.0",
2412 "8.0",
2413 "0.25",
2414 "0.125",
2415 "10.0",
2416 "-0.5",
2417/* Decimal equivalents of double precision values */
2418 "2.718281828459045091", /* D_E */
2419 "6.283185307179586477", /* 2 pi */
2420 "3.141592653589793116", /* D_PI */
2421 "1.570796326794896619", /* pi/2 */
2422 "1.414213562373095145", /* D_SQRT2 */
2423 "0.7071067811865475244", /* 1/sqrt(2) */
2424 "-1.570796326794896619", /* -pi/2 */
2425 "1.442695040888963387", /* D_LOG2ofE */
2426 "3.321928024887362182", /* D_LOG2of10 */
2427 "0.6931471805599452862", /* D_LOGEof2 */
2428 "2.302585092994045901", /* D_LOGEof10 */
2429 "0.3010299956639811980", /* D_LOG10of2 */
2430 "0.4342944819032518167", /* D_LOG10ofE */
2431/* Decimal equivalents of single precision values */
2432 "2.718281745910644531", /* S_E */
2433 "6.283185307179586477", /* 2 pi */
2434 "3.141592741012573242", /* S_PI */
2435 "1.570796326794896619", /* pi/2 */
2436 "1.414213538169860840", /* S_SQRT2 */
2437 "0.7071067811865475244", /* 1/sqrt(2) */
2438 "-1.570796326794896619", /* -pi/2 */
2439 "1.442695021629333496", /* S_LOG2ofE */
2440 "3.321928024291992188", /* S_LOG2of10 */
2441 "0.6931471824645996094", /* S_LOGEof2 */
2442 "2.302585124969482442", /* S_LOGEof10 */
2443 "0.3010300099849700928", /* S_LOG10of2 */
2444 "0.4342944920063018799", /* S_LOG10ofE */
2445};
2446
2447
2448int codes_FPA[38] = {
2449/* small rationals */
2450 0x200,
2451 0xe,
2452 0xf,
2453 0x10,
2454 0x11,
2455 0xb1,
2456 0x12,
2457 0x13,
2458 0x15,
2459 0x16,
2460 0x17,
2461 0x2e,
2462/* double precision */
2463 0x8,
2464 0x9,
2465 0xa,
2466 0xb,
2467 0xc,
2468 0xd,
2469 0x27,
2470 0x28,
2471 0x29,
2472 0x2a,
2473 0x2b,
2474 0x2c,
2475 0x2d,
2476/* single precision */
2477 0x8,
2478 0x9,
2479 0xa,
2480 0xb,
2481 0xc,
2482 0xd,
2483 0x27,
2484 0x28,
2485 0x29,
2486 0x2a,
2487 0x2b,
2488 0x2c,
2489 0x2d
2490 };
2491
2492REAL_VALUE_TYPE values_FPA[38];
2493
2494/* This code has been fixed for cross-compilation. */
2495
2496void
2497init_FPA_table ()
2498{
2499 enum machine_mode mode;
2500 int i;
2501 REAL_VALUE_TYPE r;
2502
2503 mode = DFmode;
2504 for (i = 0; i < 38; i++)
2505 {
2506 if (i == 25)
2507 mode = SFmode;
2508 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2509 values_FPA[i] = r;
2510 }
2511 inited_FPA_table = 1;
2512}
2513
79e68feb
RS		 2514
2515int
2516standard_sun_fpa_constant_p (x)
2517 rtx x;
2518{
c1cfb2ae
RS		 2519 REAL_VALUE_TYPE r;
2520 int i;
79e68feb 2521
c1cfb2ae 2522#ifndef REAL_ARITHMETIC
79e68feb
RS		 2523#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2524 if (! flag_pretend_float)
2525 return 0;
2526#endif
c1cfb2ae
RS		 2527#endif
2528
2529 if (! inited_FPA_table)
2530 init_FPA_table ();
2531
2532 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2533
2534 for (i=0; i<12; i++)
2535 {
2536 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2537 return (codes_FPA[i]);
2538 }
79e68feb 2539
64a184e9 2540 if (GET_MODE (x) == SFmode)
79e68feb 2541 {
c1cfb2ae
RS		 2542 for (i=25; i<38; i++)
2543 {
2544 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2545 return (codes_FPA[i]);
2546 }
79e68feb
RS		 2547 }
2548 else
2549 {
c1cfb2ae
RS		 2550 for (i=12; i<25; i++)
2551 {
2552 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2553 return (codes_FPA[i]);
2554 }
79e68feb
RS		 2555 }
2556 return 0x0;
2557}
2558#endif /* define SUPPORT_SUN_FPA */
2559\f
2560/* A C compound statement to output to stdio stream STREAM the
2561 assembler syntax for an instruction operand X. X is an RTL
2562 expression.
2563
2564 CODE is a value that can be used to specify one of several ways
2565 of printing the operand. It is used when identical operands
2566 must be printed differently depending on the context. CODE
2567 comes from the `%' specification that was used to request
2568 printing of the operand. If the specification was just `%DIGIT'
2569 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2570 is the ASCII code for LTR.
2571
2572 If X is a register, this macro should print the register's name.
2573 The names can be found in an array `reg_names' whose type is
2574 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2575
2576 When the machine description has a specification `%PUNCT' (a `%'
2577 followed by a punctuation character), this macro is called with
2578 a null pointer for X and the punctuation character for CODE.
2579
2580 The m68k specific codes are:
2581
2582 '.' for dot needed in Motorola-style opcode names.
2583 '-' for an operand pushing on the stack:
2584 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2585 '+' for an operand pushing on the stack:
2586 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2587 '@' for a reference to the top word on the stack:
2588 sp@, (sp) or (%sp) depending on the style of syntax.
2589 '#' for an immediate operand prefix (# in MIT and Motorola syntax
a7e2b014 2590 but & in SGS syntax, $ in CRDS/UNOS syntax).
79e68feb
RS		 2591 '!' for the cc register (used in an `and to cc' insn).
2592 '$' for the letter `s' in an op code, but only on the 68040.
2593 '&' for the letter `d' in an op code, but only on the 68040.
2ac5f14a 2594 '/' for register prefix needed by longlong.h.
79e68feb
RS		 2595
2596 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2597 'd' to force memory addressing to be absolute, not relative.
2598 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2599 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2600 than directly). Second part of 'y' below.
2601 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2602 or print pair of registers as rx:ry.
2603 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2604 CONST_DOUBLE's as SunFPA constant RAM registers if
2605 possible, so it should not be used except for the SunFPA.
2606
2607 */
2608
2609void
2610print_operand (file, op, letter)
2611 FILE *file; /* file to write to */
2612 rtx op; /* operand to print */
2613 int letter; /* %<letter> or 0 */
2614{
2615 int i;
2616
2617 if (letter == '.')
2618 {
a7e2b014 2619#if defined (MOTOROLA) && !defined (CRDS)
79e68feb
RS		 2620 asm_fprintf (file, ".");
2621#endif
2622 }
2623 else if (letter == '#')
2624 {
cffd0d74 2625 asm_fprintf (file, "%0I");
79e68feb
RS		 2626 }
2627 else if (letter == '-')
2628 {
2629#ifdef MOTOROLA
2630 asm_fprintf (file, "-(%Rsp)");
2631#else
2632 asm_fprintf (file, "%Rsp@-");
2633#endif
2634 }
2635 else if (letter == '+')
2636 {
2637#ifdef MOTOROLA
2638 asm_fprintf (file, "(%Rsp)+");
2639#else
2640 asm_fprintf (file, "%Rsp@+");
2641#endif
2642 }
2643 else if (letter == '@')
2644 {
2645#ifdef MOTOROLA
2646 asm_fprintf (file, "(%Rsp)");
2647#else
2648 asm_fprintf (file, "%Rsp@");
2649#endif
2650 }
2651 else if (letter == '!')
2652 {
cffd0d74 2653 asm_fprintf (file, "%Rfpcr");
79e68feb
RS		 2654 }
2655 else if (letter == '$')
2656 {
2657 if (TARGET_68040_ONLY)
2658 {
2659 fprintf (file, "s");
2660 }
2661 }
2662 else if (letter == '&')
2663 {
2664 if (TARGET_68040_ONLY)
2665 {
2666 fprintf (file, "d");
2667 }
2668 }
2ac5f14a
ILT		 2669 else if (letter == '/')
2670 {
2671 asm_fprintf (file, "%R");
2672 }
79e68feb
RS		 2673 else if (GET_CODE (op) == REG)
2674 {
f4a6e73b 2675#ifdef SUPPORT_SUN_FPA
79e68feb
RS		 2676 if (REGNO (op) < 16
2677 && (letter == 'y' || letter == 'x')
2678 && GET_MODE (op) == DFmode)
2679 {
2680 fprintf (file, "%s:%s", reg_names[REGNO (op)],
2681 reg_names[REGNO (op)+1]);
2682 }
2683 else
f4a6e73b 2684#endif
79e68feb 2685 {
7f49c331
RK		 2686 if (letter == 'R')
2687 /* Print out the second register name of a register pair.
2688 I.e., R (6) => 7. */
2689 fputs (reg_names[REGNO (op) + 1], file);
2690 else
2691 fputs (reg_names[REGNO (op)], file);
79e68feb
RS		 2692 }
2693 }
2694 else if (GET_CODE (op) == MEM)
2695 {
2696 output_address (XEXP (op, 0));
2697 if (letter == 'd' && ! TARGET_68020
2698 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2699 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2700 && INTVAL (XEXP (op, 0)) < 0x8000
2701 && INTVAL (XEXP (op, 0)) >= -0x8000))
2702 {
3f889ae8
RK		 2703#ifdef MOTOROLA
2704 fprintf (file, ".l");
2705#else
79e68feb 2706 fprintf (file, ":l");
3f889ae8 2707#endif
79e68feb
RS		 2708 }
2709 }
2710#ifdef SUPPORT_SUN_FPA
2711 else if ((letter == 'y' || letter == 'w')
64a184e9 2712 && GET_CODE (op) == CONST_DOUBLE
79e68feb
RS		 2713 && (i = standard_sun_fpa_constant_p (op)))
2714 {
2715 fprintf (file, "%%%d", i & 0x1ff);
2716 }
2717#endif
2718 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2719 {
c1cfb2ae
RS		 2720 REAL_VALUE_TYPE r;
2721 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2722 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2723 }
2724 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2725 {
2726 REAL_VALUE_TYPE r;
2727 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2728 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
79e68feb 2729 }
e2c0a924 2730 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
79e68feb 2731 {
c1cfb2ae
RS		 2732 REAL_VALUE_TYPE r;
2733 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2734 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
79e68feb
RS		 2735 }
2736 else
2737 {
cffd0d74 2738 asm_fprintf (file, "%0I"); output_addr_const (file, op);
79e68feb
RS		 2739 }
2740}
2741
2742\f
2743/* A C compound statement to output to stdio stream STREAM the
2744 assembler syntax for an instruction operand that is a memory
2745 reference whose address is ADDR. ADDR is an RTL expression.
2746
2747 Note that this contains a kludge that knows that the only reason
2748 we have an address (plus (label_ref...) (reg...)) when not generating
2749 PIC code is in the insn before a tablejump, and we know that m68k.md
2750 generates a label LInnn: on such an insn.
2751
2752 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2753 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2754
2755 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2756 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2757 we want. This difference can be accommodated by using an assembler
2758 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2759 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
ad7c12b2 2760 macro. See m68k/sgs.h for an example; for versions without the bug.
f4a6e73b
RK		 2761 Some assemblers refuse all the above solutions. The workaround is to
2762 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2763 right behaviour.
79e68feb
RS		 2764
2765 They also do not like things like "pea 1.w", so we simple leave off
2766 the .w on small constants.
2767
2768 This routine is responsible for distinguishing between -fpic and -fPIC
2769 style relocations in an address. When generating -fpic code the
2770 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2771 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2772
f4a6e73b
RK		 2773#ifndef ASM_OUTPUT_CASE_FETCH
2774#ifdef MOTOROLA
2775#ifdef SGS
2776#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2777 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2778#else
2779#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2780 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2781#endif
2782#else
2783#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2784 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2785#endif
2786#endif /* ASM_OUTPUT_CASE_FETCH */
2787
79e68feb
RS		 2788void
2789print_operand_address (file, addr)
2790 FILE *file;
2791 rtx addr;
2792{
2793 register rtx reg1, reg2, breg, ireg;
2794 rtx offset;
2795
2796 switch (GET_CODE (addr))
2797 {
2798 case REG:
2799#ifdef MOTOROLA
2800 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2801#else
2802 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2803#endif
2804 break;
2805 case PRE_DEC:
2806#ifdef MOTOROLA
2807 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2808#else
2809 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2810#endif
2811 break;
2812 case POST_INC:
2813#ifdef MOTOROLA
2814 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2815#else
2816 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2817#endif
2818 break;
2819 case PLUS:
2820 reg1 = reg2 = ireg = breg = offset = 0;
2821 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2822 {
2823 offset = XEXP (addr, 0);
2824 addr = XEXP (addr, 1);
2825 }
2826 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2827 {
2828 offset = XEXP (addr, 1);
2829 addr = XEXP (addr, 0);
2830 }
2831 if (GET_CODE (addr) != PLUS)
2832 {
2833 ;
2834 }
2835 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2836 {
2837 reg1 = XEXP (addr, 0);
2838 addr = XEXP (addr, 1);
2839 }
2840 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2841 {
2842 reg1 = XEXP (addr, 1);
2843 addr = XEXP (addr, 0);
2844 }
2845 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2846 {
2847 reg1 = XEXP (addr, 0);
2848 addr = XEXP (addr, 1);
2849 }
2850 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2851 {
2852 reg1 = XEXP (addr, 1);
2853 addr = XEXP (addr, 0);
2854 }
2855 else if (GET_CODE (XEXP (addr, 0)) == REG)
2856 {
2857 reg1 = XEXP (addr, 0);
2858 addr = XEXP (addr, 1);
2859 }
2860 else if (GET_CODE (XEXP (addr, 1)) == REG)
2861 {
2862 reg1 = XEXP (addr, 1);
2863 addr = XEXP (addr, 0);
2864 }
2865 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2866 || GET_CODE (addr) == SIGN_EXTEND)
2867 {
2868 if (reg1 == 0)
2869 {
2870 reg1 = addr;
2871 }
2872 else
2873 {
2874 reg2 = addr;
2875 }
2876 addr = 0;
2877 }
2878#if 0 /* for OLD_INDEXING */
2879 else if (GET_CODE (addr) == PLUS)
2880 {
2881 if (GET_CODE (XEXP (addr, 0)) == REG)
2882 {
2883 reg2 = XEXP (addr, 0);
2884 addr = XEXP (addr, 1);
2885 }
2886 else if (GET_CODE (XEXP (addr, 1)) == REG)
2887 {
2888 reg2 = XEXP (addr, 1);
2889 addr = XEXP (addr, 0);
2890 }
2891 }
2892#endif
2893 if (offset != 0)
2894 {
2895 if (addr != 0)
2896 {
2897 abort ();
2898 }
2899 addr = offset;
2900 }
2901 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
2902 || GET_CODE (reg1) == MULT))
2903 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2904 {
2905 breg = reg2;
2906 ireg = reg1;
2907 }
2908 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2909 {
2910 breg = reg1;
2911 ireg = reg2;
2912 }
2913 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
63d415c0 2914 && ! (flag_pic && ireg == pic_offset_table_rtx))
79e68feb
RS		 2915 {
2916 int scale = 1;
2917 if (GET_CODE (ireg) == MULT)
2918 {
2919 scale = INTVAL (XEXP (ireg, 1));
2920 ireg = XEXP (ireg, 0);
2921 }
2922 if (GET_CODE (ireg) == SIGN_EXTEND)
2923 {
f4a6e73b 2924 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2925 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2926 reg_names[REGNO (XEXP (ireg, 0))]);
f4a6e73b 2927 fprintf (file, "w");
79e68feb
RS		 2928 }
2929 else
2930 {
f4a6e73b 2931 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2932 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2933 reg_names[REGNO (ireg)]);
f4a6e73b 2934 fprintf (file, "l");
79e68feb
RS		 2935 }
2936 if (scale != 1)
2937 {
2938#ifdef MOTOROLA
2939 fprintf (file, "*%d", scale);
2940#else
2941 fprintf (file, ":%d", scale);
2942#endif
2943 }
2944 putc (')', file);
2945 break;
2946 }
2947 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
63d415c0 2948 && ! (flag_pic && breg == pic_offset_table_rtx))
79e68feb 2949 {
f4a6e73b 2950 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2951 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2952 reg_names[REGNO (breg)]);
f4a6e73b 2953 fprintf (file, "l)");
79e68feb
RS		 2954 break;
2955 }
2956 if (ireg != 0 || breg != 0)
2957 {
2958 int scale = 1;
2959 if (breg == 0)
2960 {
2961 abort ();
2962 }
2963 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
2964 {
2965 abort ();
2966 }
2967#ifdef MOTOROLA
2968 if (addr != 0)
2969 {
2970 output_addr_const (file, addr);
66c432a7
RS		 2971 if (flag_pic && (breg == pic_offset_table_rtx))
2972 fprintf (file, "@GOT");
79e68feb
RS		 2973 }
2974 fprintf (file, "(%s", reg_names[REGNO (breg)]);
2975 if (ireg != 0)
2976 {
2977 putc (',', file);
2978 }
2979#else
2980 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
2981 if (addr != 0)
2982 {
2983 output_addr_const (file, addr);
2984 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
2985 fprintf (file, ":w");
2986 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
2987 fprintf (file, ":l");
2988 }
2989 if (addr != 0 && ireg != 0)
2990 {
2991 putc (',', file);
2992 }
2993#endif
2994 if (ireg != 0 && GET_CODE (ireg) == MULT)
2995 {
2996 scale = INTVAL (XEXP (ireg, 1));
2997 ireg = XEXP (ireg, 0);
2998 }
2999 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
3000 {
3001#ifdef MOTOROLA
3002 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
3003#else
3004 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
3005#endif
3006 }
3007 else if (ireg != 0)
3008 {
3009#ifdef MOTOROLA
3010 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3011#else
3012 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3013#endif
3014 }
3015 if (scale != 1)
3016 {
3017#ifdef MOTOROLA
3018 fprintf (file, "*%d", scale);
3019#else
3020 fprintf (file, ":%d", scale);
3021#endif
3022 }
3023 putc (')', file);
3024 break;
3025 }
3026 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
63d415c0 3027 && ! (flag_pic && reg1 == pic_offset_table_rtx))
79e68feb 3028 {
f4a6e73b 3029 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 3030 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3031 reg_names[REGNO (reg1)]);
f4a6e73b 3032 fprintf (file, "l)");
79e68feb
RS		 3033 break;
3034 }
3035 /* FALL-THROUGH (is this really what we want? */
3036 default:
3037 if (GET_CODE (addr) == CONST_INT
3038 && INTVAL (addr) < 0x8000
3039 && INTVAL (addr) >= -0x8000)
3040 {
3041#ifdef MOTOROLA
3042#ifdef SGS
3043 /* Many SGS assemblers croak on size specifiers for constants. */
3044 fprintf (file, "%d", INTVAL (addr));
3045#else
3046 fprintf (file, "%d.w", INTVAL (addr));
3047#endif
3048#else
3049 fprintf (file, "%d:w", INTVAL (addr));
3050#endif
3051 }
3052 else
3053 {
3054 output_addr_const (file, addr);
3055 }
3056 break;
3057 }
3058}
af13f02d
JW		 3059\f
3060/* Check for cases where a clr insns can be omitted from code using
3061 strict_low_part sets. For example, the second clrl here is not needed:
3062 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3063
3064 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3065 insn we are checking for redundancy. TARGET is the register set by the
3066 clear insn. */
3067
3068int
3069strict_low_part_peephole_ok (mode, first_insn, target)
3070 enum machine_mode mode;
3071 rtx first_insn;
3072 rtx target;
3073{
3074 rtx p;
3075
3076 p = prev_nonnote_insn (first_insn);
3077
3078 while (p)
3079 {
3080 /* If it isn't an insn, then give up. */
3081 if (GET_CODE (p) != INSN)
3082 return 0;
3083
3084 if (reg_set_p (target, p))
3085 {
3086 rtx set = single_set (p);
3087 rtx dest;
3088
3089 /* If it isn't an easy to recognize insn, then give up. */
3090 if (! set)
3091 return 0;
3092
3093 dest = SET_DEST (set);
3094
3095 /* If this sets the entire target register to zero, then our
3096 first_insn is redundant. */
3097 if (rtx_equal_p (dest, target)
3098 && SET_SRC (set) == const0_rtx)
3099 return 1;
3100 else if (GET_CODE (dest) == STRICT_LOW_PART
3101 && GET_CODE (XEXP (dest, 0)) == REG
3102 && REGNO (XEXP (dest, 0)) == REGNO (target)
3103 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3104 <= GET_MODE_SIZE (mode)))
3105 /* This is a strict low part set which modifies less than
3106 we are using, so it is safe. */
3107 ;
3108 else
3109 return 0;
3110 }
3111
3112 p = prev_nonnote_insn (p);
3113
3114 }
3115
3116 return 0;
3117}
67cd4f83
TG		 3118
3119/* Accept integer operands in the range 0..0xffffffff. We have to check the
3120 range carefully since this predicate is used in DImode contexts. Also, we
3121 need some extra crud to make it work when hosted on 64-bit machines. */
3122
3123int
3124const_uint32_operand (op, mode)
3125 rtx op;
3126 enum machine_mode mode;
3127{
3128#if HOST_BITS_PER_WIDE_INT > 32
3129 /* All allowed constants will fit a CONST_INT. */
3130 return (GET_CODE (op) == CONST_INT
3131 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3132#else
fd25a29a 3133 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
67cd4f83
TG		 3134 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3135#endif
3136}
3137
3138/* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3139 to check the range carefully since this predicate is used in DImode
3140 contexts. */
3141
3142int
3143const_sint32_operand (op, mode)
3144 rtx op;
3145 enum machine_mode mode;
3146{
3147 /* All allowed constants will fit a CONST_INT. */
3148 return (GET_CODE (op) == CONST_INT
3149 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3150}
Mirror of https://gcc.gnu.org/git/gcc.git