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(PUSH_ROUNDING): Add coldfire support.
[thirdparty/gcc.git] / gcc / config / m68k / m68k.c
CommitLineData
79e68feb 1/* Subroutines for insn-output.c for Motorola 68000 family.
7bc88d49 2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
79e68feb
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
0e29e3c9
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
79e68feb
RS		 20
21
22/* Some output-actions in m68k.md need these. */
23#include <stdio.h>
24#include "config.h"
25#include "rtl.h"
26#include "regs.h"
27#include "hard-reg-set.h"
28#include "real.h"
29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34
35/* Needed for use_return_insn. */
36#include "flags.h"
37
38#ifdef SUPPORT_SUN_FPA
39
40/* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42enum reg_class regno_reg_class[]
43 = { DATA_REGS, ADDR_REGS, FP_REGS,
44 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
45
46#endif /* defined SUPPORT_SUN_FPA */
47
9eb4f6fc
RS		 48/* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50int switch_table_difference_label_flag;
51
79e68feb
RS		 52static rtx find_addr_reg ();
53rtx legitimize_pic_address ();
54\f
55
ef1dbfb0
RK		 56/* Alignment to use for loops and jumps */
57/* Specify power of two alignment used for loops. */
58char *m68k_align_loops_string;
59/* Specify power of two alignment used for non-loop jumps. */
60char *m68k_align_jumps_string;
61/* Specify power of two alignment used for functions. */
62char *m68k_align_funcs_string;
63
64/* Specify power of two alignment used for loops. */
65int m68k_align_loops;
66/* Specify power of two alignment used for non-loop jumps. */
67int m68k_align_jumps;
68/* Specify power of two alignment used for functions. */
69int m68k_align_funcs;
70
2b3600ac
JL		 71/* Nonzero if the last compare/test insn had FP operands. The
72 sCC expanders peek at this to determine what to do for the
73 68060, which has no fsCC instructions. */
74int m68k_last_compare_had_fp_operands;
ef1dbfb0
RK		 75
76/* Sometimes certain combinations of command options do not make
77 sense on a particular target machine. You can define a macro
78 `OVERRIDE_OPTIONS' to take account of this. This macro, if
79 defined, is executed once just after all the command options have
80 been parsed.
81
82 Don't use this macro to turn on various extra optimizations for
83 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
84
85void
86override_options ()
87{
88 int def_align;
89
90 def_align = 1;
91
92 /* Validate -malign-loops= value, or provide default */
93 if (m68k_align_loops_string)
94 {
95 m68k_align_loops = atoi (m68k_align_loops_string);
96 if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
97 fatal ("-malign-loops=%d is not between 1 and %d",
98 m68k_align_loops, MAX_CODE_ALIGN);
99 }
100 else
101 m68k_align_loops = def_align;
102
103 /* Validate -malign-jumps= value, or provide default */
104 if (m68k_align_jumps_string)
105 {
106 m68k_align_jumps = atoi (m68k_align_jumps_string);
107 if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
108 fatal ("-malign-jumps=%d is not between 1 and %d",
109 m68k_align_jumps, MAX_CODE_ALIGN);
110 }
111 else
112 m68k_align_jumps = def_align;
113
114 /* Validate -malign-functions= value, or provide default */
115 if (m68k_align_funcs_string)
116 {
117 m68k_align_funcs = atoi (m68k_align_funcs_string);
118 if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
119 fatal ("-malign-functions=%d is not between 1 and %d",
120 m68k_align_funcs, MAX_CODE_ALIGN);
121 }
122 else
123 m68k_align_funcs = def_align;
124}
125\f
79e68feb
RS		 126/* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
127 function at any time during the compilation process. In the future
64a184e9 128 we should try and eliminate the USE if we can easily determine that
79e68feb
RS		 129 all PIC references were deleted from the current function. That would
130 save an address register */
131
6317749b 132void
64a184e9 133finalize_pic ()
79e68feb
RS		 134{
135 if (flag_pic && current_function_uses_pic_offset_table)
adedad3e
RK		 136 {
137 rtx insn = gen_rtx (USE, VOIDmode, pic_offset_table_rtx);
138 emit_insn_after (insn, get_insns ());
139 emit_insn (insn);
140 }
79e68feb
RS		 141}
142
143\f
144/* This function generates the assembly code for function entry.
145 STREAM is a stdio stream to output the code to.
146 SIZE is an int: how many units of temporary storage to allocate.
147 Refer to the array `regs_ever_live' to determine which registers
148 to save; `regs_ever_live[I]' is nonzero if register number I
149 is ever used in the function. This function is responsible for
150 knowing which registers should not be saved even if used. */
151
152
153/* Note that the order of the bit mask for fmovem is the opposite
154 of the order for movem! */
155
156
157void
158output_function_prologue (stream, size)
159 FILE *stream;
160 int size;
161{
162 register int regno;
163 register int mask = 0;
164 int num_saved_regs = 0;
165 extern char call_used_regs[];
166 int fsize = (size + 3) & -4;
167
168
169 if (frame_pointer_needed)
170 {
2d0933a2 171 if (fsize == 0 && TARGET_68040)
e4e873f1
RK		 172 {
173 /* on the 68040, pea + move is faster than link.w 0 */
174#ifdef MOTOROLA
175 asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
176 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
177 reg_names[FRAME_POINTER_REGNUM]);
178#else
2d0933a2 179 asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
e4e873f1
RK		 180 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
181 reg_names[FRAME_POINTER_REGNUM]);
182#endif
183 }
184 else if (fsize < 0x8000)
79e68feb
RS		 185 {
186#ifdef MOTOROLA
338818c7 187 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
79e68feb
RS		 188 reg_names[FRAME_POINTER_REGNUM], -fsize);
189#else
338818c7 190 asm_fprintf (stream, "\tlink %s,%0I%d\n",
79e68feb
RS		 191 reg_names[FRAME_POINTER_REGNUM], -fsize);
192#endif
193 }
194 else if (TARGET_68020)
195 {
196#ifdef MOTOROLA
338818c7 197 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
79e68feb
RS		 198 reg_names[FRAME_POINTER_REGNUM], -fsize);
199#else
338818c7 200 asm_fprintf (stream, "\tlink %s,%0I%d\n",
79e68feb
RS		 201 reg_names[FRAME_POINTER_REGNUM], -fsize);
202#endif
203 }
204 else
205 {
e4e873f1 206 /* Adding negative number is faster on the 68040. */
79e68feb 207#ifdef MOTOROLA
cffd0d74 208 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
79e68feb
RS		 209 reg_names[FRAME_POINTER_REGNUM], -fsize);
210#else
cffd0d74 211 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
79e68feb
RS		 212 reg_names[FRAME_POINTER_REGNUM], -fsize);
213#endif
214 }
215 }
216 else if (fsize)
217 {
afaff477 218 if (fsize + 4 < 0x8000)
79e68feb 219 {
7bc88d49
RK		 220#ifdef NO_ADDSUB_Q
221 if (fsize + 4 <= 8)
afaff477 222 {
7bc88d49
RK		 223 if (!TARGET_5200)
224 {
225 /* asm_fprintf() cannot handle %. */
2d0933a2 226#ifdef MOTOROLA
7bc88d49 227 asm_fprintf (stream, "\tsubq.w %OI%d,%Rsp\n", fsize + 4);
2d0933a2 228#else
7bc88d49 229 asm_fprintf (stream, "\tsubqw %OI%d,%Rsp\n", fsize + 4);
2d0933a2 230#endif
7bc88d49
RK		 231 }
232 else
233 {
a7e2b014 234 /* asm_fprintf() cannot handle %. */
7bc88d49
RK		 235#ifdef MOTOROLA
236 asm_fprintf (stream, "\tsubq.l %OI%d,%Rsp\n", fsize + 4);
237#else
238 asm_fprintf (stream, "\tsubql %OI%d,%Rsp\n", fsize + 4);
239#endif
240 }
afaff477 241 }
7bc88d49
RK		 242 else if (fsize + 4 <= 16 && TARGET_CPU32)
243 {
244 /* On the CPU32 it is faster to use two subqw instructions to
245 subtract a small integer (8 < N <= 16) to a register. */
246 /* asm_fprintf() cannot handle %. */
247#ifdef MOTOROLA
248 asm_fprintf (stream, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
249 fsize + 4);
250#else
251 asm_fprintf (stream, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
252 fsize + 4);
253#endif
254 }
255 else
256#endif /* NO_ADDSUB_Q */
257 if (TARGET_68040)
afaff477 258 {
7bc88d49 259 /* Adding negative number is faster on the 68040. */
afaff477
RK		 260 /* asm_fprintf() cannot handle %. */
261#ifdef MOTOROLA
262 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
263#else
264 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
7bc88d49
RK		 265#endif
266 }
267 else
268 {
7bc88d49
RK		 269#ifdef MOTOROLA
270 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
271#else
272 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
afaff477
RK		 273#endif
274 }
79e68feb
RS		 275 }
276 else
277 {
2d0933a2
RK		 278 /* asm_fprintf() cannot handle %. */
279#ifdef MOTOROLA
280 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
281#else
282 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
283#endif
79e68feb
RS		 284 }
285 }
286#ifdef SUPPORT_SUN_FPA
287 for (regno = 24; regno < 56; regno++)
288 if (regs_ever_live[regno] && ! call_used_regs[regno])
289 {
290#ifdef MOTOROLA
291 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
292 reg_names[regno]);
293#else
294 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
295 reg_names[regno]);
296#endif
297 }
298#endif
f277471f 299 if (TARGET_68881)
79e68feb 300 {
f277471f
RK		 301 for (regno = 16; regno < 24; regno++)
302 if (regs_ever_live[regno] && ! call_used_regs[regno])
303 mask |= 1 << (regno - 16);
304 if ((mask & 0xff) != 0)
305 {
79e68feb 306#ifdef MOTOROLA
f277471f 307 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
79e68feb 308#else
f277471f 309 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
79e68feb 310#endif
f277471f
RK		 311 }
312 mask = 0;
79e68feb 313 }
79e68feb
RS		 314 for (regno = 0; regno < 16; regno++)
315 if (regs_ever_live[regno] && ! call_used_regs[regno])
316 {
317 mask |= 1 << (15 - regno);
318 num_saved_regs++;
319 }
320 if (frame_pointer_needed)
321 {
322 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
323 num_saved_regs--;
324 }
99df2465
RS		 325
326#if NEED_PROBE
a7e2b014
RK		 327#ifdef MOTOROLA
328#ifdef CRDS
329 asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
330#else
331 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
332#endif
333#else
81bd5278 334 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
a7e2b014 335#endif
99df2465
RS		 336#endif
337
79e68feb
RS		 338 if (num_saved_regs <= 2)
339 {
340 /* Store each separately in the same order moveml uses.
341 Using two movel instructions instead of a single moveml
342 is about 15% faster for the 68020 and 68030 at no expense
343 in code size */
344
345 int i;
346
347 /* Undo the work from above. */
348 for (i = 0; i< 16; i++)
349 if (mask & (1 << i))
350 asm_fprintf (stream,
351#ifdef MOTOROLA
64a184e9 352 "\t%Omove.l %s,-(%Rsp)\n",
79e68feb
RS		 353#else
354 "\tmovel %s,%Rsp@-\n",
355#endif
356 reg_names[15 - i]);
357 }
358 else if (mask)
359 {
afaff477
RK		 360 if (TARGET_5200)
361 {
362 /* The coldfire does not support the predecrement form of the
363 movml instruction, so we must adjust the stack pointer and
364 then use the plain address register indirect mode. We also
365 have to invert the register save mask to use the new mode.
366
367 FIXME: if num_saved_regs was calculated earlier, we could
368 combine the stack pointer adjustment with any adjustment
369 done when the initial stack frame is created. This would
370 save an instruction */
371
372 int newmask = 0;
373 int i;
374
375 for (i = 0; i < 16; i++)
376 if (mask & (1 << i))
377 newmask |= (1 << (15-i));
378
379#ifdef MOTOROLA
de649959 380 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
afaff477
RK		 381 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
382#else
de649959 383 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
afaff477
RK		 384 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
385#endif
386 }
387 else
388 {
79e68feb 389#ifdef MOTOROLA
afaff477 390 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
79e68feb 391#else
afaff477 392 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
79e68feb 393#endif
afaff477 394 }
79e68feb
RS		 395 }
396 if (flag_pic && current_function_uses_pic_offset_table)
397 {
398#ifdef MOTOROLA
66c432a7 399 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
79e68feb
RS		 400 reg_names[PIC_OFFSET_TABLE_REGNUM]);
401#else
cffd0d74 402 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
79e68feb
RS		 403 reg_names[PIC_OFFSET_TABLE_REGNUM]);
404 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
405 reg_names[PIC_OFFSET_TABLE_REGNUM],
406 reg_names[PIC_OFFSET_TABLE_REGNUM]);
407#endif
408 }
409}
410\f
411/* Return true if this function's epilogue can be output as RTL. */
412
413int
414use_return_insn ()
415{
416 int regno;
417
418 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
419 return 0;
420
421 /* Copied from output_function_epilogue (). We should probably create a
422 separate layout routine to perform the common work. */
423
424 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
425 if (regs_ever_live[regno] && ! call_used_regs[regno])
426 return 0;
427
428 return 1;
429}
430
431/* This function generates the assembly code for function exit,
432 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
433
434 The function epilogue should not depend on the current stack pointer!
435 It should use the frame pointer only, if there is a frame pointer.
436 This is mandatory because of alloca; we also take advantage of it to
437 omit stack adjustments before returning. */
438
439void
440output_function_epilogue (stream, size)
441 FILE *stream;
442 int size;
443{
444 register int regno;
445 register int mask, fmask;
446 register int nregs;
447 int offset, foffset, fpoffset;
448 extern char call_used_regs[];
449 int fsize = (size + 3) & -4;
450 int big = 0;
451 rtx insn = get_last_insn ();
6910dd70 452 int restore_from_sp = 0;
79e68feb
RS		 453
454 /* If the last insn was a BARRIER, we don't have to write any code. */
455 if (GET_CODE (insn) == NOTE)
456 insn = prev_nonnote_insn (insn);
457 if (insn && GET_CODE (insn) == BARRIER)
cffd0d74
RS		 458 {
459 /* Output just a no-op so that debuggers don't get confused
460 about which function the pc is in at this address. */
461 asm_fprintf (stream, "\tnop\n");
462 return;
463 }
79e68feb 464
b69649e4
RK		 465#ifdef FUNCTION_BLOCK_PROFILER_EXIT
466 if (profile_block_flag == 2)
467 {
468 FUNCTION_BLOCK_PROFILER_EXIT (stream);
469 }
470#endif
471
79e68feb
RS		 472#ifdef FUNCTION_EXTRA_EPILOGUE
473 FUNCTION_EXTRA_EPILOGUE (stream, size);
474#endif
475 nregs = 0; fmask = 0; fpoffset = 0;
476#ifdef SUPPORT_SUN_FPA
477 for (regno = 24 ; regno < 56 ; regno++)
478 if (regs_ever_live[regno] && ! call_used_regs[regno])
479 nregs++;
480 fpoffset = nregs * 8;
481#endif
482 nregs = 0;
f277471f
RK		 483 if (TARGET_68881)
484 {
485 for (regno = 16; regno < 24; regno++)
486 if (regs_ever_live[regno] && ! call_used_regs[regno])
487 {
488 nregs++;
489 fmask |= 1 << (23 - regno);
490 }
491 }
79e68feb
RS		 492 foffset = fpoffset + nregs * 12;
493 nregs = 0; mask = 0;
494 if (frame_pointer_needed)
495 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
496 for (regno = 0; regno < 16; regno++)
497 if (regs_ever_live[regno] && ! call_used_regs[regno])
498 {
499 nregs++;
500 mask |= 1 << regno;
501 }
502 offset = foffset + nregs * 4;
c67ddce5
RK		 503 /* FIXME : leaf_function_p below is too strong.
504 What we really need to know there is if there could be pending
505 stack adjustment needed at that point. */
6910dd70
RK		 506 restore_from_sp = ! frame_pointer_needed
507 || (! current_function_calls_alloca && leaf_function_p ());
79e68feb 508 if (offset + fsize >= 0x8000
6910dd70 509 && ! restore_from_sp
79e68feb
RS		 510 && (mask || fmask || fpoffset))
511 {
512#ifdef MOTOROLA
e7eefaec 513 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
79e68feb 514#else
e7eefaec 515 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
79e68feb
RS		 516#endif
517 fsize = 0, big = 1;
518 }
afaff477 519 if (TARGET_5200 || nregs <= 2)
79e68feb
RS		 520 {
521 /* Restore each separately in the same order moveml does.
522 Using two movel instructions instead of a single moveml
523 is about 15% faster for the 68020 and 68030 at no expense
524 in code size. */
525
526 int i;
527
528 /* Undo the work from above. */
529 for (i = 0; i< 16; i++)
530 if (mask & (1 << i))
531 {
532 if (big)
533 {
534#ifdef MOTOROLA
e7eefaec 535 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
79e68feb
RS		 536 offset + fsize,
537 reg_names[FRAME_POINTER_REGNUM],
538 reg_names[i]);
539#else
e7eefaec 540 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
79e68feb
RS		 541 reg_names[FRAME_POINTER_REGNUM],
542 offset + fsize, reg_names[i]);
543#endif
544 }
6910dd70 545 else if (restore_from_sp)
79e68feb
RS		 546 {
547#ifdef MOTOROLA
64a184e9 548 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
79e68feb
RS		 549 reg_names[i]);
550#else
551 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
552 reg_names[i]);
553#endif
554 }
555 else
556 {
557#ifdef MOTOROLA
64a184e9 558 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
79e68feb
RS		 559 offset + fsize,
560 reg_names[FRAME_POINTER_REGNUM],
561 reg_names[i]);
562#else
563 asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
564 reg_names[FRAME_POINTER_REGNUM],
565 offset + fsize, reg_names[i]);
566#endif
567 }
568 offset = offset - 4;
569 }
570 }
571 else if (mask)
572 {
573 if (big)
574 {
575#ifdef MOTOROLA
e7eefaec 576 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
79e68feb
RS		 577 offset + fsize,
578 reg_names[FRAME_POINTER_REGNUM],
579 mask);
580#else
e7eefaec 581 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
79e68feb
RS		 582 reg_names[FRAME_POINTER_REGNUM],
583 offset + fsize, mask);
584#endif
585 }
6910dd70 586 else if (restore_from_sp)
79e68feb
RS		 587 {
588#ifdef MOTOROLA
cffd0d74 589 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
79e68feb 590#else
cffd0d74 591 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
79e68feb
RS		 592#endif
593 }
594 else
595 {
596#ifdef MOTOROLA
cffd0d74 597 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
79e68feb
RS		 598 offset + fsize,
599 reg_names[FRAME_POINTER_REGNUM],
600 mask);
601#else
cffd0d74 602 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
79e68feb
RS		 603 reg_names[FRAME_POINTER_REGNUM],
604 offset + fsize, mask);
605#endif
606 }
607 }
608 if (fmask)
609 {
610 if (big)
611 {
612#ifdef MOTOROLA
e7eefaec 613 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
79e68feb
RS		 614 foffset + fsize,
615 reg_names[FRAME_POINTER_REGNUM],
616 fmask);
617#else
e7eefaec 618 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
79e68feb
RS		 619 reg_names[FRAME_POINTER_REGNUM],
620 foffset + fsize, fmask);
621#endif
622 }
6910dd70 623 else if (restore_from_sp)
79e68feb
RS		 624 {
625#ifdef MOTOROLA
cffd0d74 626 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
79e68feb 627#else
cffd0d74 628 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
79e68feb
RS		 629#endif
630 }
631 else
632 {
633#ifdef MOTOROLA
cffd0d74 634 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
79e68feb
RS		 635 foffset + fsize,
636 reg_names[FRAME_POINTER_REGNUM],
637 fmask);
638#else
cffd0d74 639 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
79e68feb
RS		 640 reg_names[FRAME_POINTER_REGNUM],
641 foffset + fsize, fmask);
642#endif
643 }
644 }
645 if (fpoffset != 0)
646 for (regno = 55; regno >= 24; regno--)
647 if (regs_ever_live[regno] && ! call_used_regs[regno])
648 {
649 if (big)
650 {
651#ifdef MOTOROLA
e7eefaec 652 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
79e68feb
RS		 653 fpoffset + fsize,
654 reg_names[FRAME_POINTER_REGNUM],
655 reg_names[regno]);
656#else
e7eefaec 657 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
79e68feb
RS		 658 reg_names[FRAME_POINTER_REGNUM],
659 fpoffset + fsize, reg_names[regno]);
660#endif
661 }
6910dd70 662 else if (restore_from_sp)
79e68feb
RS		 663 {
664#ifdef MOTOROLA
665 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
666 reg_names[regno]);
667#else
668 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
669 reg_names[regno]);
670#endif
671 }
672 else
673 {
674#ifdef MOTOROLA
675 asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
676 fpoffset + fsize,
677 reg_names[FRAME_POINTER_REGNUM],
678 reg_names[regno]);
679#else
680 asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
681 reg_names[FRAME_POINTER_REGNUM],
682 fpoffset + fsize, reg_names[regno]);
683#endif
684 }
685 fpoffset -= 8;
686 }
687 if (frame_pointer_needed)
688 fprintf (stream, "\tunlk %s\n",
689 reg_names[FRAME_POINTER_REGNUM]);
690 else if (fsize)
691 {
7bc88d49
RK		 692#ifdef NO_ADDSUB_Q
693 if (fsize + 4 <= 8)
79e68feb 694 {
7bc88d49
RK		 695 if (!TARGET_5200)
696 {
2d0933a2 697#ifdef MOTOROLA
7bc88d49 698 asm_fprintf (stream, "\taddq.w %OI%d,%Rsp\n", fsize + 4);
2d0933a2 699#else
7bc88d49 700 asm_fprintf (stream, "\taddqw %OI%d,%Rsp\n", fsize + 4);
2d0933a2 701#endif
afaff477
RK		 702 }
703 else
704 {
7bc88d49
RK		 705#ifdef MOTOROLA
706 asm_fprintf (stream, "\taddq.l %OI%d,%Rsp\n", fsize + 4);
707#else
708 asm_fprintf (stream, "\taddql %OI%d,%Rsp\n", fsize + 4);
709#endif
710 }
711 }
712 else if (fsize + 4 <= 16 && TARGET_CPU32)
713 {
714 /* On the CPU32 it is faster to use two addqw instructions to
715 add a small integer (8 < N <= 16) to a register. */
a7e2b014 716 /* asm_fprintf() cannot handle %. */
7bc88d49
RK		 717#ifdef MOTOROLA
718 asm_fprintf (stream, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
719 fsize + 4);
720#else
721 asm_fprintf (stream, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
722 fsize + 4);
723#endif
724 }
725 else
726#endif /* NO_ADDSUB_Q */
727 if (fsize + 4 < 0x8000)
728 {
729 if (TARGET_68040)
730 {
afaff477
RK		 731 /* asm_fprintf() cannot handle %. */
732#ifdef MOTOROLA
733 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
734#else
735 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
7bc88d49
RK		 736#endif
737 }
738 else
739 {
7bc88d49
RK		 740#ifdef MOTOROLA
741 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
742#else
743 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
afaff477
RK		 744#endif
745 }
79e68feb
RS		 746 }
747 else
748 {
2d0933a2
RK		 749 /* asm_fprintf() cannot handle %. */
750#ifdef MOTOROLA
751 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
752#else
753 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
754#endif
79e68feb
RS		 755 }
756 }
757 if (current_function_pops_args)
338818c7 758 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
79e68feb
RS		 759 else
760 fprintf (stream, "\trts\n");
761}
762\f
763/* Similar to general_operand, but exclude stack_pointer_rtx. */
764
765int
766not_sp_operand (op, mode)
767 register rtx op;
768 enum machine_mode mode;
769{
770 return op != stack_pointer_rtx && general_operand (op, mode);
771}
772
64a184e9
RS		 773/* Return TRUE if X is a valid comparison operator for the dbcc
774 instruction.
775
776 Note it rejects floating point comparison operators.
777 (In the future we could use Fdbcc).
778
779 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
780
781int
782valid_dbcc_comparison_p (x, mode)
783 rtx x;
784 enum machine_mode mode;
785{
64a184e9
RS		 786 switch (GET_CODE (x))
787 {
64a184e9
RS		 788 case EQ: case NE: case GTU: case LTU:
789 case GEU: case LEU:
790 return 1;
791
792 /* Reject some when CC_NO_OVERFLOW is set. This may be over
793 conservative */
794 case GT: case LT: case GE: case LE:
795 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
796 default:
797 return 0;
798 }
799}
800
6a0f85e3
TG		 801/* Return non-zero if flags are currently in the 68881 flag register. */
802int
803flags_in_68881 ()
804{
805 /* We could add support for these in the future */
806 return cc_status.flags & CC_IN_68881;
807}
808
64a184e9
RS		 809/* Output a dbCC; jCC sequence. Note we do not handle the
810 floating point version of this sequence (Fdbcc). We also
811 do not handle alternative conditions when CC_NO_OVERFLOW is
6a0f85e3
TG		 812 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
813 kick those out before we get here. */
64a184e9
RS		 814
815output_dbcc_and_branch (operands)
816 rtx *operands;
817{
64a184e9
RS		 818 switch (GET_CODE (operands[3]))
819 {
820 case EQ:
821#ifdef MOTOROLA
822 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
823#else
824 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
825#endif
826 break;
827
828 case NE:
829#ifdef MOTOROLA
830 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
831#else
832 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
833#endif
834 break;
835
836 case GT:
837#ifdef MOTOROLA
838 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
839#else
840 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
841#endif
842 break;
843
844 case GTU:
845#ifdef MOTOROLA
846 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
847#else
848 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
849#endif
850 break;
851
852 case LT:
853#ifdef MOTOROLA
854 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
855#else
856 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
857#endif
858 break;
859
860 case LTU:
861#ifdef MOTOROLA
862 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
863#else
864 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
865#endif
866 break;
867
868 case GE:
869#ifdef MOTOROLA
870 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
871#else
872 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
873#endif
874 break;
875
876 case GEU:
877#ifdef MOTOROLA
878 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
879#else
880 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
881#endif
882 break;
883
884 case LE:
885#ifdef MOTOROLA
886 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
887#else
888 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
889#endif
890 break;
891
892 case LEU:
893#ifdef MOTOROLA
894 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
895#else
896 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
897#endif
898 break;
899
900 default:
901 abort ();
902 }
903
904 /* If the decrement is to be done in SImode, then we have
905 to compensate for the fact that dbcc decrements in HImode. */
906 switch (GET_MODE (operands[0]))
907 {
908 case SImode:
909#ifdef MOTOROLA
910 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
911#else
912 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
913#endif
914 break;
915
916 case HImode:
917 break;
918
919 default:
920 abort ();
921 }
922}
923
c59c3b1c
RK		 924char *
925output_scc_di(op, operand1, operand2, dest)
926 rtx op;
927 rtx operand1;
928 rtx operand2;
929 rtx dest;
930{
931 rtx loperands[7];
d9832fd2 932 enum rtx_code op_code = GET_CODE (op);
c59c3b1c 933
906a2d3c
RK		 934 /* This does not produce a usefull cc. */
935 CC_STATUS_INIT;
936
d9832fd2
RK		 937 /* The m68k cmp.l instruction requires operand1 to be a reg as used
938 below. Swap the operands and change the op if these requirements
939 are not fulfilled. */
940 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
941 {
942 rtx tmp = operand1;
943
944 operand1 = operand2;
945 operand2 = tmp;
946 op_code = swap_condition (op_code);
947 }
c59c3b1c
RK		 948 loperands[0] = operand1;
949 if (GET_CODE (operand1) == REG)
950 loperands[1] = gen_rtx (REG, SImode, REGNO (operand1) + 1);
951 else
952 loperands[1] = adj_offsettable_operand (operand1, 4);
953 if (operand2 != const0_rtx)
954 {
955 loperands[2] = operand2;
956 if (GET_CODE (operand2) == REG)
957 loperands[3] = gen_rtx (REG, SImode, REGNO (operand2) + 1);
958 else
959 loperands[3] = adj_offsettable_operand (operand2, 4);
960 }
961 loperands[4] = gen_label_rtx();
962 if (operand2 != const0_rtx)
963#ifdef MOTOROLA
f2121711 964#ifdef SGS_CMP_ORDER
c59c3b1c
RK		 965 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
966#else
f2121711
RK		 967 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
968#endif
969#else
970#ifdef SGS_CMP_ORDER
c59c3b1c 971 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
f2121711
RK		 972#else
973 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
974#endif
c59c3b1c
RK		 975#endif
976 else
977#ifdef MOTOROLA
978 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands);
979#else
980 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands);
981#endif
982 loperands[5] = dest;
983
d9832fd2 984 switch (op_code)
c59c3b1c
RK		 985 {
986 case EQ:
987 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
988 CODE_LABEL_NUMBER (loperands[4]));
989 output_asm_insn ("seq %5", loperands);
990 break;
991
992 case NE:
993 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
994 CODE_LABEL_NUMBER (loperands[4]));
995 output_asm_insn ("sne %5", loperands);
996 break;
997
998 case GT:
999 loperands[6] = gen_label_rtx();
1000#ifdef MOTOROLA
1001 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1002#else
1003 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1004#endif
1005 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1006 CODE_LABEL_NUMBER (loperands[4]));
1007 output_asm_insn ("sgt %5", loperands);
1008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1009 CODE_LABEL_NUMBER (loperands[6]));
1010 break;
1011
1012 case GTU:
1013 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1014 CODE_LABEL_NUMBER (loperands[4]));
1015 output_asm_insn ("shi %5", loperands);
1016 break;
1017
1018 case LT:
1019 loperands[6] = gen_label_rtx();
1020#ifdef MOTOROLA
1021 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1022#else
1023 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1024#endif
1025 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1026 CODE_LABEL_NUMBER (loperands[4]));
1027 output_asm_insn ("slt %5", loperands);
1028 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1029 CODE_LABEL_NUMBER (loperands[6]));
1030 break;
1031
1032 case LTU:
1033 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1034 CODE_LABEL_NUMBER (loperands[4]));
1035 output_asm_insn ("scs %5", loperands);
1036 break;
1037
1038 case GE:
1039 loperands[6] = gen_label_rtx();
1040#ifdef MOTOROLA
1041 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1042#else
1043 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1044#endif
1045 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1046 CODE_LABEL_NUMBER (loperands[4]));
1047 output_asm_insn ("sge %5", loperands);
1048 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1049 CODE_LABEL_NUMBER (loperands[6]));
1050 break;
1051
1052 case GEU:
1053 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1054 CODE_LABEL_NUMBER (loperands[4]));
1055 output_asm_insn ("scc %5", loperands);
1056 break;
1057
1058 case LE:
1059 loperands[6] = gen_label_rtx();
1060#ifdef MOTOROLA
1061 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1062#else
1063 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1064#endif
1065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1066 CODE_LABEL_NUMBER (loperands[4]));
1067 output_asm_insn ("sle %5", loperands);
1068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1069 CODE_LABEL_NUMBER (loperands[6]));
1070 break;
1071
1072 case LEU:
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1074 CODE_LABEL_NUMBER (loperands[4]));
1075 output_asm_insn ("sls %5", loperands);
1076 break;
1077
1078 default:
1079 abort ();
1080 }
1081 return "";
1082}
1083
79e68feb
RS		 1084char *
1085output_btst (operands, countop, dataop, insn, signpos)
1086 rtx *operands;
1087 rtx countop, dataop;
1088 rtx insn;
1089 int signpos;
1090{
1091 operands[0] = countop;
1092 operands[1] = dataop;
1093
1094 if (GET_CODE (countop) == CONST_INT)
1095 {
1096 register int count = INTVAL (countop);
1097 /* If COUNT is bigger than size of storage unit in use,
1098 advance to the containing unit of same size. */
1099 if (count > signpos)
1100 {
1101 int offset = (count & ~signpos) / 8;
1102 count = count & signpos;
1103 operands[1] = dataop = adj_offsettable_operand (dataop, offset);
1104 }
1105 if (count == signpos)
1106 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1107 else
1108 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1109
1110 /* These three statements used to use next_insns_test_no...
1111 but it appears that this should do the same job. */
1112 if (count == 31
1113 && next_insn_tests_no_inequality (insn))
1114 return "tst%.l %1";
1115 if (count == 15
1116 && next_insn_tests_no_inequality (insn))
1117 return "tst%.w %1";
1118 if (count == 7
1119 && next_insn_tests_no_inequality (insn))
1120 return "tst%.b %1";
1121
1122 cc_status.flags = CC_NOT_NEGATIVE;
1123 }
1124 return "btst %0,%1";
1125}
1126\f
1127/* Returns 1 if OP is either a symbol reference or a sum of a symbol
1128 reference and a constant. */
1129
1130int
1131symbolic_operand (op, mode)
1132 register rtx op;
1133 enum machine_mode mode;
1134{
1135 switch (GET_CODE (op))
1136 {
1137 case SYMBOL_REF:
1138 case LABEL_REF:
1139 return 1;
1140
1141 case CONST:
1142 op = XEXP (op, 0);
1143 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1144 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1145 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1146
1147#if 0 /* Deleted, with corresponding change in m68k.h,
1148 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1149 case CONST_DOUBLE:
1150 return GET_MODE (op) == mode;
1151#endif
1152
1153 default:
1154 return 0;
1155 }
1156}
16f323be
RK		 1157\f
1158/* Check for sign_extend or zero_extend. Used for bit-count operands. */
1159
1160int
1161extend_operator(x, mode)
1162 rtx x;
1163 enum machine_mode mode;
1164{
c59c3b1c 1165 if (mode != VOIDmode && GET_MODE(x) != mode)
16f323be
RK		 1166 return 0;
1167 switch (GET_CODE(x))
1168 {
1169 case SIGN_EXTEND :
1170 case ZERO_EXTEND :
16f323be
RK		 1171 return 1;
1172 default :
1173 return 0;
1174 }
1175}
79e68feb
RS		 1176
1177\f
1178/* Legitimize PIC addresses. If the address is already
1179 position-independent, we return ORIG. Newly generated
1180 position-independent addresses go to REG. If we need more
1181 than one register, we lose.
1182
1183 An address is legitimized by making an indirect reference
1184 through the Global Offset Table with the name of the symbol
1185 used as an offset.
1186
1187 The assembler and linker are responsible for placing the
1188 address of the symbol in the GOT. The function prologue
1189 is responsible for initializing a5 to the starting address
1190 of the GOT.
1191
1192 The assembler is also responsible for translating a symbol name
1193 into a constant displacement from the start of the GOT.
1194
1195 A quick example may make things a little clearer:
1196
1197 When not generating PIC code to store the value 12345 into _foo
1198 we would generate the following code:
1199
1200 movel #12345, _foo
1201
1202 When generating PIC two transformations are made. First, the compiler
1203 loads the address of foo into a register. So the first transformation makes:
1204
1205 lea _foo, a0
1206 movel #12345, a0@
1207
1208 The code in movsi will intercept the lea instruction and call this
1209 routine which will transform the instructions into:
1210
1211 movel a5@(_foo:w), a0
1212 movel #12345, a0@
1213
1214
1215 That (in a nutshell) is how *all* symbol and label references are
1216 handled. */
1217
1218rtx
1219legitimize_pic_address (orig, mode, reg)
1220 rtx orig, reg;
1221 enum machine_mode mode;
1222{
1223 rtx pic_ref = orig;
1224
1225 /* First handle a simple SYMBOL_REF or LABEL_REF */
1226 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1227 {
1228 if (reg == 0)
1229 abort ();
1230
1231 pic_ref = gen_rtx (MEM, Pmode,
1232 gen_rtx (PLUS, Pmode,
1233 pic_offset_table_rtx, orig));
1234 current_function_uses_pic_offset_table = 1;
1235 RTX_UNCHANGING_P (pic_ref) = 1;
1236 emit_move_insn (reg, pic_ref);
1237 return reg;
1238 }
1239 else if (GET_CODE (orig) == CONST)
1240 {
1241 rtx base, offset;
1242
1243 /* Make sure this is CONST has not already been legitimized */
1244 if (GET_CODE (XEXP (orig, 0)) == PLUS
1245 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1246 return orig;
1247
1248 if (reg == 0)
1249 abort ();
1250
1251 /* legitimize both operands of the PLUS */
1252 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1253 {
1254 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1255 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1256 base == reg ? 0 : reg);
1257 }
1258 else abort ();
1259
1260 if (GET_CODE (orig) == CONST_INT)
1261 return plus_constant_for_output (base, INTVAL (orig));
1262 pic_ref = gen_rtx (PLUS, Pmode, base, orig);
1263 /* Likewise, should we set special REG_NOTEs here? */
1264 }
1265 return pic_ref;
1266}
1267
1268\f
0ce6f9fb
RK		 1269typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1270
6910dd70 1271#define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
0ce6f9fb
RK		 1272
1273CONST_METHOD
1274const_method (constant)
1275 rtx constant;
1276{
1277 int i;
1278 unsigned u;
1279
1280 i = INTVAL (constant);
6910dd70 1281 if (USE_MOVQ (i))
0ce6f9fb 1282 return MOVQ;
24092242
RK		 1283
1284 /* The Coldfire doesn't have byte or word operations. */
1285 /* FIXME: This may not be useful for the m68060 either */
1286 if (!TARGET_5200)
1287 {
1288 /* if -256 < N < 256 but N is not in range for a moveq
1289 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1290 if (USE_MOVQ (i ^ 0xff))
1291 return NOTB;
1292 /* Likewise, try with not.w */
1293 if (USE_MOVQ (i ^ 0xffff))
1294 return NOTW;
1295 /* This is the only value where neg.w is useful */
1296 if (i == -65408)
1297 return NEGW;
1298 /* Try also with swap */
1299 u = i;
1300 if (USE_MOVQ ((u >> 16) | (u << 16)))
1301 return SWAP;
1302 }
0ce6f9fb
RK		 1303 /* Otherwise, use move.l */
1304 return MOVL;
1305}
1306
1307const_int_cost (constant)
1308 rtx constant;
1309{
1310 switch (const_method (constant))
1311 {
1312 case MOVQ :
1313 /* Constants between -128 and 127 are cheap due to moveq */
1314 return 0;
1315 case NOTB :
1316 case NOTW :
1317 case NEGW :
1318 case SWAP :
1319 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1320 return 1;
1321 case MOVL :
1322 return 2;
1323 default :
1324 abort ();
1325 }
1326}
1327
1328char *
1329output_move_const_into_data_reg (operands)
1330 rtx *operands;
1331{
1332 int i;
1333
1334 i = INTVAL (operands[1]);
1335 switch (const_method (operands[1]))
1336 {
1337 case MOVQ :
1338#if defined (MOTOROLA) && !defined (CRDS)
1339 return "moveq%.l %1,%0";
1340#else
1341 return "moveq %1,%0";
1342#endif
1343 case NOTB :
1344 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xff);
1345#if defined (MOTOROLA) && !defined (CRDS)
1346 return "moveq%.l %1,%0\n\tnot%.b %0";
1347#else
1348 return "moveq %1,%0\n\tnot%.b %0";
1349#endif
1350 case NOTW :
1351 operands[1] = gen_rtx (CONST_INT, VOIDmode, i ^ 0xffff);
1352#if defined (MOTOROLA) && !defined (CRDS)
1353 return "moveq%.l %1,%0\n\tnot%.w %0";
1354#else
1355 return "moveq %1,%0\n\tnot%.w %0";
1356#endif
1357 case NEGW :
1358#if defined (MOTOROLA) && !defined (CRDS)
1359 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1360#else
1361 return "moveq %#-128,%0\n\tneg%.w %0";
1362#endif
1363 case SWAP :
1364 {
1365 unsigned u = i;
1366
1367 operands[1] = gen_rtx (CONST_INT, VOIDmode, (u << 16) | (u >> 16));
1368#if defined (MOTOROLA) && !defined (CRDS)
1369 return "moveq%.l %1,%0\n\tswap %0";
1370#else
1371 return "moveq %1,%0\n\tswap %0";
1372#endif
1373 }
1374 case MOVL :
1375 return "move%.l %1,%0";
1376 default :
1377 abort ();
1378 }
1379}
1380
02ed0c07
RK		 1381char *
1382output_move_simode_const (operands)
1383 rtx *operands;
1384{
1385 if (operands[1] == const0_rtx
1386 && (DATA_REG_P (operands[0])
1387 || GET_CODE (operands[0]) == MEM)
1388 /* clr insns on 68000 read before writing.
c67ddce5 1389 This isn't so on the 68010, but we have no TARGET_68010. */
0cb7cfed 1390 && ((TARGET_68020 || TARGET_5200)
02ed0c07
RK		 1391 || !(GET_CODE (operands[0]) == MEM
1392 && MEM_VOLATILE_P (operands[0]))))
1393 return "clr%.l %0";
1394 else if (DATA_REG_P (operands[0]))
1395 return output_move_const_into_data_reg (operands);
1396 else if (ADDRESS_REG_P (operands[0])
1397 && INTVAL (operands[1]) < 0x8000
1398 && INTVAL (operands[1]) >= -0x8000)
1399 return "move%.w %1,%0";
1400 else if (GET_CODE (operands[0]) == MEM
1401 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1402 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1403 && INTVAL (operands[1]) < 0x8000
1404 && INTVAL (operands[1]) >= -0x8000)
1405 return "pea %a1";
1406 return "move%.l %1,%0";
1407}
1408
f4e80198
RK		 1409char *
1410output_move_simode (operands)
1411 rtx *operands;
1412{
1413 if (GET_CODE (operands[1]) == CONST_INT)
1414 return output_move_simode_const (operands);
1415 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1416 || GET_CODE (operands[1]) == CONST)
1417 && push_operand (operands[0], SImode))
1418 return "pea %a1";
1419 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1420 || GET_CODE (operands[1]) == CONST)
1421 && ADDRESS_REG_P (operands[0]))
1422 return "lea %a1,%0";
1423 return "move%.l %1,%0";
1424}
1425
1426char *
1427output_move_himode (operands)
1428 rtx *operands;
1429{
1430 if (GET_CODE (operands[1]) == CONST_INT)
1431 {
1432 if (operands[1] == const0_rtx
1433 && (DATA_REG_P (operands[0])
1434 || GET_CODE (operands[0]) == MEM)
1435 /* clr insns on 68000 read before writing.
1436 This isn't so on the 68010, but we have no TARGET_68010. */
1437 && ((TARGET_68020 || TARGET_5200)
1438 || !(GET_CODE (operands[0]) == MEM
1439 && MEM_VOLATILE_P (operands[0]))))
1440 return "clr%.w %0";
1441 else if (DATA_REG_P (operands[0])
1442 && INTVAL (operands[1]) < 128
1443 && INTVAL (operands[1]) >= -128)
1444 {
1445#if defined(MOTOROLA) && !defined(CRDS)
1446 return "moveq%.l %1,%0";
1447#else
1448 return "moveq %1,%0";
1449#endif
1450 }
1451 else if (INTVAL (operands[1]) < 0x8000
1452 && INTVAL (operands[1]) >= -0x8000)
1453 return "move%.w %1,%0";
1454 }
1455 else if (CONSTANT_P (operands[1]))
1456 return "move%.l %1,%0";
1457#ifndef SGS_NO_LI
1458 /* Recognize the insn before a tablejump, one that refers
1459 to a table of offsets. Such an insn will need to refer
1460 to a label on the insn. So output one. Use the label-number
1461 of the table of offsets to generate this label. This code,
1462 and similar code below, assumes that there will be at most one
1463 reference to each table. */
1464 if (GET_CODE (operands[1]) == MEM
1465 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1466 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1467 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1468 {
1469 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1470#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1471#ifdef SGS
1472 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1473 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1474#else /* not SGS */
1475 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1476 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1477#endif /* not SGS */
1478#else /* SGS_SWITCH_TABLES or not MOTOROLA */
1479 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
1480 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1481#ifdef SGS_SWITCH_TABLES
1482 /* Set flag saying we need to define the symbol
1483 LD%n (with value L%n-LI%n) at the end of the switch table. */
1484 switch_table_difference_label_flag = 1;
1485#endif /* SGS_SWITCH_TABLES */
1486#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1487 }
1488#endif /* SGS_NO_LI */
1489 return "move%.w %1,%0";
1490}
1491
1492char *
1493output_move_qimode (operands)
1494 rtx *operands;
1495{
1496 rtx xoperands[4];
1497
1498 /* This is probably useless, since it loses for pushing a struct
1499 of several bytes a byte at a time. */
1500 if (GET_CODE (operands[0]) == MEM
1501 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1502 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1503 && ! ADDRESS_REG_P (operands[1]))
1504 {
1505 xoperands[1] = operands[1];
1506 xoperands[2]
1507 = gen_rtx (MEM, QImode,
1508 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
1509 /* Just pushing a byte puts it in the high byte of the halfword. */
1510 /* We must put it in the low-order, high-numbered byte. */
3879920c
RK		 1511 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1512 {
1513 xoperands[3] = stack_pointer_rtx;
1514#ifndef NO_ADDSUB_Q
1515 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1516#else
1517 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1518#endif
1519 }
1520 else
1521 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
f4e80198
RK		 1522 return "";
1523 }
1524
1525 /* clr and st insns on 68000 read before writing.
1526 This isn't so on the 68010, but we have no TARGET_68010. */
1527 if (!ADDRESS_REG_P (operands[0])
1528 && ((TARGET_68020 || TARGET_5200)
1529 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1530 {
1531 if (operands[1] == const0_rtx)
1532 return "clr%.b %0";
1533 if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1534 && GET_CODE (operands[1]) == CONST_INT
1535 && (INTVAL (operands[1]) & 255) == 255)
1536 {
1537 CC_STATUS_INIT;
1538 return "st %0";
1539 }
1540 }
1541 if (GET_CODE (operands[1]) == CONST_INT
1542 && DATA_REG_P (operands[0])
1543 && INTVAL (operands[1]) < 128
1544 && INTVAL (operands[1]) >= -128)
1545 {
1546#if defined(MOTOROLA) && !defined(CRDS)
1547 return "moveq%.l %1,%0";
1548#else
1549 return "moveq %1,%0";
1550#endif
1551 }
1552 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1553 return "move%.l %1,%0";
1554 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1555 return "move%.w %1,%0";
1556 return "move%.b %1,%0";
1557}
1558
9b55bf04
RK		 1559char *
1560output_move_stricthi (operands)
1561 rtx *operands;
1562{
1563 if (operands[1] == const0_rtx
1564 /* clr insns on 68000 read before writing.
1565 This isn't so on the 68010, but we have no TARGET_68010. */
1566 && ((TARGET_68020 || TARGET_5200)
1567 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1568 return "clr%.w %0";
1569 return "move%.w %1,%0";
1570}
1571
1572char *
1573output_move_strictqi (operands)
1574 rtx *operands;
1575{
1576 if (operands[1] == const0_rtx
1577 /* clr insns on 68000 read before writing.
1578 This isn't so on the 68010, but we have no TARGET_68010. */
1579 && ((TARGET_68020 || TARGET_5200)
1580 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1581 return "clr%.b %0";
1582 return "move%.b %1,%0";
1583}
1584
79e68feb
RS		 1585/* Return the best assembler insn template
1586 for moving operands[1] into operands[0] as a fullword. */
1587
1588static char *
1589singlemove_string (operands)
1590 rtx *operands;
1591{
1592#ifdef SUPPORT_SUN_FPA
1593 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1594 return "fpmoves %1,%0";
1595#endif
02ed0c07
RK		 1596 if (GET_CODE (operands[1]) == CONST_INT)
1597 return output_move_simode_const (operands);
1598 return "move%.l %1,%0";
79e68feb
RS		 1599}
1600
2505bc97 1601
79e68feb
RS		 1602/* Output assembler code to perform a doubleword move insn
1603 with operands OPERANDS. */
1604
1605char *
1606output_move_double (operands)
1607 rtx *operands;
1608{
2505bc97
RS		 1609 enum
1610 {
1611 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1612 } optype0, optype1;
79e68feb 1613 rtx latehalf[2];
2505bc97 1614 rtx middlehalf[2];
7f98eeb6 1615 rtx xops[2];
79e68feb 1616 rtx addreg0 = 0, addreg1 = 0;
7f98eeb6 1617 int dest_overlapped_low = 0;
184916bc 1618 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2505bc97
RS		 1619
1620 middlehalf[0] = 0;
1621 middlehalf[1] = 0;
79e68feb
RS		 1622
1623 /* First classify both operands. */
1624
1625 if (REG_P (operands[0]))
1626 optype0 = REGOP;
1627 else if (offsettable_memref_p (operands[0]))
1628 optype0 = OFFSOP;
1629 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1630 optype0 = POPOP;
1631 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1632 optype0 = PUSHOP;
1633 else if (GET_CODE (operands[0]) == MEM)
1634 optype0 = MEMOP;
1635 else
1636 optype0 = RNDOP;
1637
1638 if (REG_P (operands[1]))
1639 optype1 = REGOP;
1640 else if (CONSTANT_P (operands[1]))
1641 optype1 = CNSTOP;
1642 else if (offsettable_memref_p (operands[1]))
1643 optype1 = OFFSOP;
1644 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1645 optype1 = POPOP;
1646 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1647 optype1 = PUSHOP;
1648 else if (GET_CODE (operands[1]) == MEM)
1649 optype1 = MEMOP;
1650 else
1651 optype1 = RNDOP;
1652
1653 /* Check for the cases that the operand constraints are not
1654 supposed to allow to happen. Abort if we get one,
1655 because generating code for these cases is painful. */
1656
1657 if (optype0 == RNDOP || optype1 == RNDOP)
1658 abort ();
1659
1660 /* If one operand is decrementing and one is incrementing
1661 decrement the former register explicitly
1662 and change that operand into ordinary indexing. */
1663
1664 if (optype0 == PUSHOP && optype1 == POPOP)
1665 {
1666 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2505bc97
RS		 1667 if (size == 12)
1668 output_asm_insn ("sub%.l %#12,%0", operands);
1669 else
1670 output_asm_insn ("subq%.l %#8,%0", operands);
1671 if (GET_MODE (operands[1]) == XFmode)
1672 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
1673 else if (GET_MODE (operands[0]) == DFmode)
1674 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
1675 else
1676 operands[0] = gen_rtx (MEM, DImode, operands[0]);
79e68feb
RS		 1677 optype0 = OFFSOP;
1678 }
1679 if (optype0 == POPOP && optype1 == PUSHOP)
1680 {
1681 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2505bc97
RS		 1682 if (size == 12)
1683 output_asm_insn ("sub%.l %#12,%1", operands);
1684 else
1685 output_asm_insn ("subq%.l %#8,%1", operands);
1686 if (GET_MODE (operands[1]) == XFmode)
1687 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
1688 else if (GET_MODE (operands[1]) == DFmode)
1689 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
1690 else
1691 operands[1] = gen_rtx (MEM, DImode, operands[1]);
79e68feb
RS		 1692 optype1 = OFFSOP;
1693 }
1694
1695 /* If an operand is an unoffsettable memory ref, find a register
1696 we can increment temporarily to make it refer to the second word. */
1697
1698 if (optype0 == MEMOP)
1699 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1700
1701 if (optype1 == MEMOP)
1702 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1703
1704 /* Ok, we can do one word at a time.
1705 Normally we do the low-numbered word first,
1706 but if either operand is autodecrementing then we
1707 do the high-numbered word first.
1708
1709 In either case, set up in LATEHALF the operands to use
1710 for the high-numbered word and in some cases alter the
1711 operands in OPERANDS to be suitable for the low-numbered word. */
1712
2505bc97
RS		 1713 if (size == 12)
1714 {
1715 if (optype0 == REGOP)
1716 {
1717 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
1718 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1719 }
1720 else if (optype0 == OFFSOP)
1721 {
1722 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1723 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1724 }
1725 else
1726 {
1727 middlehalf[0] = operands[0];
1728 latehalf[0] = operands[0];
1729 }
1730
1731 if (optype1 == REGOP)
1732 {
1733 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1734 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1735 }
1736 else if (optype1 == OFFSOP)
1737 {
1738 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1739 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1740 }
1741 else if (optype1 == CNSTOP)
1742 {
1743 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1744 {
1745 REAL_VALUE_TYPE r;
1746 long l[3];
1747
1748 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1749 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1750 operands[1] = GEN_INT (l[0]);
1751 middlehalf[1] = GEN_INT (l[1]);
1752 latehalf[1] = GEN_INT (l[2]);
1753 }
1754 else if (CONSTANT_P (operands[1]))
1755 {
1756 /* actually, no non-CONST_DOUBLE constant should ever
1757 appear here. */
1758 abort ();
1759 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
1760 latehalf[1] = constm1_rtx;
1761 else
1762 latehalf[1] = const0_rtx;
1763 }
1764 }
1765 else
1766 {
1767 middlehalf[1] = operands[1];
1768 latehalf[1] = operands[1];
1769 }
1770 }
79e68feb 1771 else
2505bc97
RS		 1772 /* size is not 12: */
1773 {
1774 if (optype0 == REGOP)
1775 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1776 else if (optype0 == OFFSOP)
1777 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1778 else
1779 latehalf[0] = operands[0];
1780
1781 if (optype1 == REGOP)
1782 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1783 else if (optype1 == OFFSOP)
1784 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1785 else if (optype1 == CNSTOP)
1786 split_double (operands[1], &operands[1], &latehalf[1]);
1787 else
1788 latehalf[1] = operands[1];
1789 }
79e68feb
RS		 1790
1791 /* If insn is effectively movd N(sp),-(sp) then we will do the
1792 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1793 for the low word as well, to compensate for the first decrement of sp. */
1794 if (optype0 == PUSHOP
1795 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1796 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
c88aeaf8 1797 operands[1] = middlehalf[1] = latehalf[1];
79e68feb 1798
7f98eeb6
RS		 1799 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1800 if the upper part of reg N does not appear in the MEM, arrange to
1801 emit the move late-half first. Otherwise, compute the MEM address
1802 into the upper part of N and use that as a pointer to the memory
1803 operand. */
1804 if (optype0 == REGOP
1805 && (optype1 == OFFSOP || optype1 == MEMOP))
1806 {
3a58400f
RS		 1807 rtx testlow = gen_rtx (REG, SImode, REGNO (operands[0]));
1808
1809 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
d7e8d581 1810 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
7f98eeb6
RS		 1811 {
1812 /* If both halves of dest are used in the src memory address,
3a58400f
RS		 1813 compute the address into latehalf of dest.
1814 Note that this can't happen if the dest is two data regs. */
7f98eeb6
RS		 1815compadr:
1816 xops[0] = latehalf[0];
1817 xops[1] = XEXP (operands[1], 0);
d7e8d581 1818 output_asm_insn ("lea %a1,%0", xops);
7f98eeb6
RS		 1819 if( GET_MODE (operands[1]) == XFmode )
1820 {
1821 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
1822 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1823 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1824 }
1825 else
1826 {
1827 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
1828 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1829 }
1830 }
1831 else if (size == 12
d7e8d581
RS		 1832 && reg_overlap_mentioned_p (middlehalf[0],
1833 XEXP (operands[1], 0)))
7f98eeb6 1834 {
3a58400f
RS		 1835 /* Check for two regs used by both source and dest.
1836 Note that this can't happen if the dest is all data regs.
1837 It can happen if the dest is d6, d7, a0.
1838 But in that case, latehalf is an addr reg, so
1839 the code at compadr does ok. */
1840
1841 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
d7e8d581
RS		 1842 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1843 goto compadr;
7f98eeb6
RS		 1844
1845 /* JRV says this can't happen: */
1846 if (addreg0 || addreg1)
d7e8d581 1847 abort ();
7f98eeb6
RS		 1848
1849 /* Only the middle reg conflicts; simply put it last. */
1850 output_asm_insn (singlemove_string (operands), operands);
1851 output_asm_insn (singlemove_string (latehalf), latehalf);
1852 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1853 return "";
1854 }
2fb8a81d 1855 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
7f98eeb6
RS		 1856 /* If the low half of dest is mentioned in the source memory
1857 address, the arrange to emit the move late half first. */
1858 dest_overlapped_low = 1;
1859 }
1860
79e68feb
RS		 1861 /* If one or both operands autodecrementing,
1862 do the two words, high-numbered first. */
1863
1864 /* Likewise, the first move would clobber the source of the second one,
1865 do them in the other order. This happens only for registers;
1866 such overlap can't happen in memory unless the user explicitly
1867 sets it up, and that is an undefined circumstance. */
1868
1869 if (optype0 == PUSHOP || optype1 == PUSHOP
1870 || (optype0 == REGOP && optype1 == REGOP
2505bc97 1871 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
7f98eeb6
RS		 1872 || REGNO (operands[0]) == REGNO (latehalf[1])))
1873 || dest_overlapped_low)
79e68feb
RS		 1874 {
1875 /* Make any unoffsettable addresses point at high-numbered word. */
1876 if (addreg0)
2505bc97
RS		 1877 {
1878 if (size == 12)
07eced4d 1879 output_asm_insn ("addq%.l %#8,%0", &addreg0);
2505bc97 1880 else
07eced4d 1881 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2505bc97 1882 }
79e68feb 1883 if (addreg1)
2505bc97
RS		 1884 {
1885 if (size == 12)
07eced4d 1886 output_asm_insn ("addq%.l %#8,%0", &addreg1);
2505bc97 1887 else
07eced4d 1888 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2505bc97 1889 }
79e68feb
RS		 1890
1891 /* Do that word. */
1892 output_asm_insn (singlemove_string (latehalf), latehalf);
1893
1894 /* Undo the adds we just did. */
1895 if (addreg0)
07eced4d 1896 output_asm_insn ("subq%.l %#4,%0", &addreg0);
79e68feb 1897 if (addreg1)
07eced4d 1898 output_asm_insn ("subq%.l %#4,%0", &addreg1);
79e68feb 1899
2505bc97
RS		 1900 if (size == 12)
1901 {
1902 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1903 if (addreg0)
07eced4d 1904 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2505bc97 1905 if (addreg1)
07eced4d 1906 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2505bc97
RS		 1907 }
1908
79e68feb
RS		 1909 /* Do low-numbered word. */
1910 return singlemove_string (operands);
1911 }
1912
1913 /* Normal case: do the two words, low-numbered first. */
1914
1915 output_asm_insn (singlemove_string (operands), operands);
1916
2505bc97
RS		 1917 /* Do the middle one of the three words for long double */
1918 if (size == 12)
1919 {
1920 if (addreg0)
07eced4d 1921 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2505bc97 1922 if (addreg1)
07eced4d 1923 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2505bc97
RS		 1924
1925 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1926 }
1927
79e68feb
RS		 1928 /* Make any unoffsettable addresses point at high-numbered word. */
1929 if (addreg0)
07eced4d 1930 output_asm_insn ("addq%.l %#4,%0", &addreg0);
79e68feb 1931 if (addreg1)
07eced4d 1932 output_asm_insn ("addq%.l %#4,%0", &addreg1);
79e68feb
RS		 1933
1934 /* Do that word. */
1935 output_asm_insn (singlemove_string (latehalf), latehalf);
1936
1937 /* Undo the adds we just did. */
1938 if (addreg0)
2505bc97
RS		 1939 {
1940 if (size == 12)
07eced4d 1941 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2505bc97 1942 else
07eced4d 1943 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2505bc97 1944 }
79e68feb 1945 if (addreg1)
2505bc97
RS		 1946 {
1947 if (size == 12)
07eced4d 1948 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2505bc97 1949 else
07eced4d 1950 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2505bc97 1951 }
79e68feb
RS		 1952
1953 return "";
1954}
1955
1956/* Return a REG that occurs in ADDR with coefficient 1.
1957 ADDR can be effectively incremented by incrementing REG. */
1958
1959static rtx
1960find_addr_reg (addr)
1961 rtx addr;
1962{
1963 while (GET_CODE (addr) == PLUS)
1964 {
1965 if (GET_CODE (XEXP (addr, 0)) == REG)
1966 addr = XEXP (addr, 0);
1967 else if (GET_CODE (XEXP (addr, 1)) == REG)
1968 addr = XEXP (addr, 1);
1969 else if (CONSTANT_P (XEXP (addr, 0)))
1970 addr = XEXP (addr, 1);
1971 else if (CONSTANT_P (XEXP (addr, 1)))
1972 addr = XEXP (addr, 0);
1973 else
1974 abort ();
1975 }
1976 if (GET_CODE (addr) == REG)
1977 return addr;
1978 abort ();
1979}
9ee3c687
JW		 1980
1981/* Output assembler code to perform a 32 bit 3 operand add. */
1982
1983char *
1984output_addsi3 (operands)
1985 rtx *operands;
1986{
1987 if (! operands_match_p (operands[0], operands[1]))
1988 {
1989 if (!ADDRESS_REG_P (operands[1]))
1990 {
1991 rtx tmp = operands[1];
1992
1993 operands[1] = operands[2];
1994 operands[2] = tmp;
1995 }
1996
1997 /* These insns can result from reloads to access
1998 stack slots over 64k from the frame pointer. */
1999 if (GET_CODE (operands[2]) == CONST_INT
2000 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
8c61b6c1 2001 return "move%.l %2,%0\n\tadd%.l %1,%0";
9ee3c687
JW		 2002#ifdef SGS
2003 if (GET_CODE (operands[2]) == REG)
2004 return "lea 0(%1,%2.l),%0";
2005 else
2006 return "lea %c2(%1),%0";
2007#else /* not SGS */
2008#ifdef MOTOROLA
2009 if (GET_CODE (operands[2]) == REG)
2010 return "lea (%1,%2.l),%0";
2011 else
2012 return "lea (%c2,%1),%0";
2013#else /* not MOTOROLA (MIT syntax) */
2014 if (GET_CODE (operands[2]) == REG)
2015 return "lea %1@(0,%2:l),%0";
2016 else
2017 return "lea %1@(%c2),%0";
2018#endif /* not MOTOROLA */
2019#endif /* not SGS */
2020 }
2021 if (GET_CODE (operands[2]) == CONST_INT)
2022 {
2023#ifndef NO_ADDSUB_Q
2024 if (INTVAL (operands[2]) > 0
2025 && INTVAL (operands[2]) <= 8)
2026 return "addq%.l %2,%0";
2027 if (INTVAL (operands[2]) < 0
2028 && INTVAL (operands[2]) >= -8)
2029 {
2030 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2031 - INTVAL (operands[2]));
2032 return "subq%.l %2,%0";
2033 }
2034 /* On the CPU32 it is faster to use two addql instructions to
2035 add a small integer (8 < N <= 16) to a register.
2036 Likewise for subql. */
2037 if (TARGET_CPU32 && REG_P (operands[0]))
2038 {
2039 if (INTVAL (operands[2]) > 8
2040 && INTVAL (operands[2]) <= 16)
2041 {
2042 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2043 INTVAL (operands[2]) - 8);
8c61b6c1 2044 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
9ee3c687
JW		 2045 }
2046 if (INTVAL (operands[2]) < -8
2047 && INTVAL (operands[2]) >= -16)
2048 {
2049 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2050 - INTVAL (operands[2]) - 8);
8c61b6c1 2051 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
9ee3c687
JW		 2052 }
2053 }
2054#endif
2055 if (ADDRESS_REG_P (operands[0])
2056 && INTVAL (operands[2]) >= -0x8000
2057 && INTVAL (operands[2]) < 0x8000)
2058 {
2059 if (TARGET_68040)
2060 return "add%.w %2,%0";
2061 else
2062#ifdef MOTOROLA
2063 return "lea (%c2,%0),%0";
2064#else
2065 return "lea %0@(%c2),%0";
2066#endif
2067 }
2068 }
2069 return "add%.l %2,%0";
2070}
79e68feb
RS		 2071\f
2072/* Store in cc_status the expressions that the condition codes will
2073 describe after execution of an instruction whose pattern is EXP.
2074 Do not alter them if the instruction would not alter the cc's. */
2075
2076/* On the 68000, all the insns to store in an address register fail to
2077 set the cc's. However, in some cases these instructions can make it
2078 possibly invalid to use the saved cc's. In those cases we clear out
2079 some or all of the saved cc's so they won't be used. */
2080
2081notice_update_cc (exp, insn)
2082 rtx exp;
2083 rtx insn;
2084{
2085 /* If the cc is being set from the fpa and the expression is not an
2086 explicit floating point test instruction (which has code to deal with
2087 this), reinit the CC. */
2088 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
2089 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
2090 && !(GET_CODE (exp) == PARALLEL
2091 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
2092 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
2093 {
2094 CC_STATUS_INIT;
2095 }
2096 else if (GET_CODE (exp) == SET)
2097 {
2098 if (GET_CODE (SET_SRC (exp)) == CALL)
2099 {
2100 CC_STATUS_INIT;
2101 }
2102 else if (ADDRESS_REG_P (SET_DEST (exp)))
2103 {
2104 if (cc_status.value1
2105 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
2106 cc_status.value1 = 0;
2107 if (cc_status.value2
2108 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
2109 cc_status.value2 = 0;
2110 }
2111 else if (!FP_REG_P (SET_DEST (exp))
2112 && SET_DEST (exp) != cc0_rtx
2113 && (FP_REG_P (SET_SRC (exp))
2114 || GET_CODE (SET_SRC (exp)) == FIX
2115 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2116 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2117 {
2118 CC_STATUS_INIT;
2119 }
2120 /* A pair of move insns doesn't produce a useful overall cc. */
2121 else if (!FP_REG_P (SET_DEST (exp))
2122 && !FP_REG_P (SET_SRC (exp))
2123 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2124 && (GET_CODE (SET_SRC (exp)) == REG
2125 || GET_CODE (SET_SRC (exp)) == MEM
2126 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2127 {
2128 CC_STATUS_INIT;
2129 }
2130 else if (GET_CODE (SET_SRC (exp)) == CALL)
2131 {
2132 CC_STATUS_INIT;
2133 }
2134 else if (XEXP (exp, 0) != pc_rtx)
2135 {
2136 cc_status.flags = 0;
2137 cc_status.value1 = XEXP (exp, 0);
2138 cc_status.value2 = XEXP (exp, 1);
2139 }
2140 }
2141 else if (GET_CODE (exp) == PARALLEL
2142 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2143 {
2144 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2145 CC_STATUS_INIT;
2146 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2147 {
2148 cc_status.flags = 0;
2149 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2150 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2151 }
2152 }
2153 else
2154 CC_STATUS_INIT;
2155 if (cc_status.value2 != 0
2156 && ADDRESS_REG_P (cc_status.value2)
2157 && GET_MODE (cc_status.value2) == QImode)
2158 CC_STATUS_INIT;
2159 if (cc_status.value2 != 0
2160 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
2161 switch (GET_CODE (cc_status.value2))
2162 {
2163 case PLUS: case MINUS: case MULT:
2164 case DIV: case UDIV: case MOD: case UMOD: case NEG:
b757e352 2165#if 0 /* These instructions always clear the overflow bit */
996a5f59 2166 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
79e68feb 2167 case ROTATE: case ROTATERT:
b757e352 2168#endif
79e68feb
RS		 2169 if (GET_MODE (cc_status.value2) != VOIDmode)
2170 cc_status.flags |= CC_NO_OVERFLOW;
2171 break;
2172 case ZERO_EXTEND:
2173 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2174 ends with a move insn moving r2 in r2's mode.
2175 Thus, the cc's are set for r2.
2176 This can set N bit spuriously. */
2177 cc_status.flags |= CC_NOT_NEGATIVE;
2178 }
2179 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2180 && cc_status.value2
2181 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2182 cc_status.value2 = 0;
2183 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2184 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
2185 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
2186 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
2187 cc_status.flags = CC_IN_68881;
2188}
2189\f
2190char *
2191output_move_const_double (operands)
2192 rtx *operands;
2193{
2194#ifdef SUPPORT_SUN_FPA
64a184e9 2195 if (TARGET_FPA && FPA_REG_P (operands[0]))
79e68feb
RS		 2196 {
2197 int code = standard_sun_fpa_constant_p (operands[1]);
2198
2199 if (code != 0)
2200 {
2201 static char buf[40];
2202
2203 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
2204 return buf;
2205 }
2206 return "fpmove%.d %1,%0";
2207 }
2208 else
2209#endif
2210 {
2211 int code = standard_68881_constant_p (operands[1]);
2212
2213 if (code != 0)
2214 {
2215 static char buf[40];
2216
2217 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2218 return buf;
2219 }
2220 return "fmove%.d %1,%0";
2221 }
2222}
2223
2224char *
2225output_move_const_single (operands)
2226 rtx *operands;
2227{
2228#ifdef SUPPORT_SUN_FPA
2229 if (TARGET_FPA)
2230 {
2231 int code = standard_sun_fpa_constant_p (operands[1]);
2232
2233 if (code != 0)
2234 {
2235 static char buf[40];
2236
2237 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
2238 return buf;
2239 }
2240 return "fpmove%.s %1,%0";
2241 }
2242 else
2243#endif /* defined SUPPORT_SUN_FPA */
2244 {
2245 int code = standard_68881_constant_p (operands[1]);
2246
2247 if (code != 0)
2248 {
2249 static char buf[40];
2250
2251 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2252 return buf;
2253 }
2254 return "fmove%.s %f1,%0";
2255 }
2256}
2257
2258/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2259 from the "fmovecr" instruction.
2260 The value, anded with 0xff, gives the code to use in fmovecr
2261 to get the desired constant. */
2262
c1cfb2ae
RS		 2263/* This code has been fixed for cross-compilation. */
2264
2265static int inited_68881_table = 0;
2266
2267char *strings_68881[7] = {
2268 "0.0",
2269 "1.0",
2270 "10.0",
2271 "100.0",
2272 "10000.0",
2273 "1e8",
2274 "1e16"
2275 };
2276
2277int codes_68881[7] = {
2278 0x0f,
2279 0x32,
2280 0x33,
2281 0x34,
2282 0x35,
2283 0x36,
2284 0x37
2285 };
2286
2287REAL_VALUE_TYPE values_68881[7];
2288
2289/* Set up values_68881 array by converting the decimal values
2290 strings_68881 to binary. */
2291
2292void
2293init_68881_table ()
2294{
2295 int i;
2296 REAL_VALUE_TYPE r;
2297 enum machine_mode mode;
2298
16d82c3c 2299 mode = SFmode;
c1cfb2ae
RS		 2300 for (i = 0; i < 7; i++)
2301 {
2302 if (i == 6)
16d82c3c 2303 mode = DFmode;
c1cfb2ae
RS		 2304 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2305 values_68881[i] = r;
2306 }
2307 inited_68881_table = 1;
2308}
79e68feb
RS		 2309
2310int
2311standard_68881_constant_p (x)
2312 rtx x;
2313{
c1cfb2ae
RS		 2314 REAL_VALUE_TYPE r;
2315 int i;
2316 enum machine_mode mode;
79e68feb 2317
a5d54cc5
RK		 2318#ifdef NO_ASM_FMOVECR
2319 return 0;
2320#endif
2321
2296cba3 2322 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
79e68feb
RS		 2323 if (TARGET_68040)
2324 return 0;
2325
c1cfb2ae 2326#ifndef REAL_ARITHMETIC
79e68feb
RS		 2327#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2328 if (! flag_pretend_float)
2329 return 0;
c1cfb2ae 2330#endif
79e68feb
RS		 2331#endif
2332
c1cfb2ae
RS		 2333 if (! inited_68881_table)
2334 init_68881_table ();
2335
2336 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2337
2338 for (i = 0; i < 6; i++)
2339 {
2340 if (REAL_VALUES_EQUAL (r, values_68881[i]))
2341 return (codes_68881[i]);
2342 }
2343
79e68feb
RS		 2344 if (GET_MODE (x) == SFmode)
2345 return 0;
c1cfb2ae
RS		 2346
2347 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2348 return (codes_68881[6]);
2349
79e68feb
RS		 2350 /* larger powers of ten in the constants ram are not used
2351 because they are not equal to a `double' C constant. */
2352 return 0;
2353}
2354
2355/* If X is a floating-point constant, return the logarithm of X base 2,
2356 or 0 if X is not a power of 2. */
2357
2358int
2359floating_exact_log2 (x)
2360 rtx x;
2361{
c1cfb2ae 2362 REAL_VALUE_TYPE r, r1;
79e68feb
RS		 2363 int i;
2364
c1cfb2ae 2365#ifndef REAL_ARITHMETIC
79e68feb
RS		 2366#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2367 if (! flag_pretend_float)
2368 return 0;
c1cfb2ae 2369#endif
79e68feb
RS		 2370#endif
2371
c1cfb2ae 2372 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
79e68feb 2373
c1cfb2ae 2374 if (REAL_VALUES_LESS (r, dconst0))
79e68feb
RS		 2375 return 0;
2376
6b62e557 2377 r1 = dconst1;
c1cfb2ae
RS		 2378 i = 0;
2379 while (REAL_VALUES_LESS (r1, r))
2380 {
2381 r1 = REAL_VALUE_LDEXP (dconst1, i);
2382 if (REAL_VALUES_EQUAL (r1, r))
2383 return i;
2384 i = i + 1;
2385 }
79e68feb
RS		 2386 return 0;
2387}
2388\f
2389#ifdef SUPPORT_SUN_FPA
2390/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2391 from the Sun FPA's constant RAM.
2392 The value returned, anded with 0x1ff, gives the code to use in fpmove
2393 to get the desired constant. */
c1cfb2ae
RS		 2394
2395static int inited_FPA_table = 0;
2396
2397char *strings_FPA[38] = {
2398/* small rationals */
2399 "0.0",
2400 "1.0",
2401 "0.5",
2402 "-1.0",
2403 "2.0",
2404 "3.0",
2405 "4.0",
2406 "8.0",
2407 "0.25",
2408 "0.125",
2409 "10.0",
2410 "-0.5",
2411/* Decimal equivalents of double precision values */
2412 "2.718281828459045091", /* D_E */
2413 "6.283185307179586477", /* 2 pi */
2414 "3.141592653589793116", /* D_PI */
2415 "1.570796326794896619", /* pi/2 */
2416 "1.414213562373095145", /* D_SQRT2 */
2417 "0.7071067811865475244", /* 1/sqrt(2) */
2418 "-1.570796326794896619", /* -pi/2 */
2419 "1.442695040888963387", /* D_LOG2ofE */
2420 "3.321928024887362182", /* D_LOG2of10 */
2421 "0.6931471805599452862", /* D_LOGEof2 */
2422 "2.302585092994045901", /* D_LOGEof10 */
2423 "0.3010299956639811980", /* D_LOG10of2 */
2424 "0.4342944819032518167", /* D_LOG10ofE */
2425/* Decimal equivalents of single precision values */
2426 "2.718281745910644531", /* S_E */
2427 "6.283185307179586477", /* 2 pi */
2428 "3.141592741012573242", /* S_PI */
2429 "1.570796326794896619", /* pi/2 */
2430 "1.414213538169860840", /* S_SQRT2 */
2431 "0.7071067811865475244", /* 1/sqrt(2) */
2432 "-1.570796326794896619", /* -pi/2 */
2433 "1.442695021629333496", /* S_LOG2ofE */
2434 "3.321928024291992188", /* S_LOG2of10 */
2435 "0.6931471824645996094", /* S_LOGEof2 */
2436 "2.302585124969482442", /* S_LOGEof10 */
2437 "0.3010300099849700928", /* S_LOG10of2 */
2438 "0.4342944920063018799", /* S_LOG10ofE */
2439};
2440
2441
2442int codes_FPA[38] = {
2443/* small rationals */
2444 0x200,
2445 0xe,
2446 0xf,
2447 0x10,
2448 0x11,
2449 0xb1,
2450 0x12,
2451 0x13,
2452 0x15,
2453 0x16,
2454 0x17,
2455 0x2e,
2456/* double precision */
2457 0x8,
2458 0x9,
2459 0xa,
2460 0xb,
2461 0xc,
2462 0xd,
2463 0x27,
2464 0x28,
2465 0x29,
2466 0x2a,
2467 0x2b,
2468 0x2c,
2469 0x2d,
2470/* single precision */
2471 0x8,
2472 0x9,
2473 0xa,
2474 0xb,
2475 0xc,
2476 0xd,
2477 0x27,
2478 0x28,
2479 0x29,
2480 0x2a,
2481 0x2b,
2482 0x2c,
2483 0x2d
2484 };
2485
2486REAL_VALUE_TYPE values_FPA[38];
2487
2488/* This code has been fixed for cross-compilation. */
2489
2490void
2491init_FPA_table ()
2492{
2493 enum machine_mode mode;
2494 int i;
2495 REAL_VALUE_TYPE r;
2496
2497 mode = DFmode;
2498 for (i = 0; i < 38; i++)
2499 {
2500 if (i == 25)
2501 mode = SFmode;
2502 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2503 values_FPA[i] = r;
2504 }
2505 inited_FPA_table = 1;
2506}
2507
79e68feb
RS		 2508
2509int
2510standard_sun_fpa_constant_p (x)
2511 rtx x;
2512{
c1cfb2ae
RS		 2513 REAL_VALUE_TYPE r;
2514 int i;
79e68feb 2515
c1cfb2ae 2516#ifndef REAL_ARITHMETIC
79e68feb
RS		 2517#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2518 if (! flag_pretend_float)
2519 return 0;
2520#endif
c1cfb2ae
RS		 2521#endif
2522
2523 if (! inited_FPA_table)
2524 init_FPA_table ();
2525
2526 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2527
2528 for (i=0; i<12; i++)
2529 {
2530 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2531 return (codes_FPA[i]);
2532 }
79e68feb 2533
64a184e9 2534 if (GET_MODE (x) == SFmode)
79e68feb 2535 {
c1cfb2ae
RS		 2536 for (i=25; i<38; i++)
2537 {
2538 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2539 return (codes_FPA[i]);
2540 }
79e68feb
RS		 2541 }
2542 else
2543 {
c1cfb2ae
RS		 2544 for (i=12; i<25; i++)
2545 {
2546 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2547 return (codes_FPA[i]);
2548 }
79e68feb
RS		 2549 }
2550 return 0x0;
2551}
2552#endif /* define SUPPORT_SUN_FPA */
2553\f
2554/* A C compound statement to output to stdio stream STREAM the
2555 assembler syntax for an instruction operand X. X is an RTL
2556 expression.
2557
2558 CODE is a value that can be used to specify one of several ways
2559 of printing the operand. It is used when identical operands
2560 must be printed differently depending on the context. CODE
2561 comes from the `%' specification that was used to request
2562 printing of the operand. If the specification was just `%DIGIT'
2563 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2564 is the ASCII code for LTR.
2565
2566 If X is a register, this macro should print the register's name.
2567 The names can be found in an array `reg_names' whose type is
2568 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2569
2570 When the machine description has a specification `%PUNCT' (a `%'
2571 followed by a punctuation character), this macro is called with
2572 a null pointer for X and the punctuation character for CODE.
2573
2574 The m68k specific codes are:
2575
2576 '.' for dot needed in Motorola-style opcode names.
2577 '-' for an operand pushing on the stack:
2578 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2579 '+' for an operand pushing on the stack:
2580 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2581 '@' for a reference to the top word on the stack:
2582 sp@, (sp) or (%sp) depending on the style of syntax.
2583 '#' for an immediate operand prefix (# in MIT and Motorola syntax
a7e2b014 2584 but & in SGS syntax, $ in CRDS/UNOS syntax).
79e68feb
RS		 2585 '!' for the cc register (used in an `and to cc' insn).
2586 '$' for the letter `s' in an op code, but only on the 68040.
2587 '&' for the letter `d' in an op code, but only on the 68040.
2ac5f14a 2588 '/' for register prefix needed by longlong.h.
79e68feb
RS		 2589
2590 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2591 'd' to force memory addressing to be absolute, not relative.
2592 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2593 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2594 than directly). Second part of 'y' below.
2595 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2596 or print pair of registers as rx:ry.
2597 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2598 CONST_DOUBLE's as SunFPA constant RAM registers if
2599 possible, so it should not be used except for the SunFPA.
2600
2601 */
2602
2603void
2604print_operand (file, op, letter)
2605 FILE *file; /* file to write to */
2606 rtx op; /* operand to print */
2607 int letter; /* %<letter> or 0 */
2608{
2609 int i;
2610
2611 if (letter == '.')
2612 {
a7e2b014 2613#if defined (MOTOROLA) && !defined (CRDS)
79e68feb
RS		 2614 asm_fprintf (file, ".");
2615#endif
2616 }
2617 else if (letter == '#')
2618 {
cffd0d74 2619 asm_fprintf (file, "%0I");
79e68feb
RS		 2620 }
2621 else if (letter == '-')
2622 {
2623#ifdef MOTOROLA
2624 asm_fprintf (file, "-(%Rsp)");
2625#else
2626 asm_fprintf (file, "%Rsp@-");
2627#endif
2628 }
2629 else if (letter == '+')
2630 {
2631#ifdef MOTOROLA
2632 asm_fprintf (file, "(%Rsp)+");
2633#else
2634 asm_fprintf (file, "%Rsp@+");
2635#endif
2636 }
2637 else if (letter == '@')
2638 {
2639#ifdef MOTOROLA
2640 asm_fprintf (file, "(%Rsp)");
2641#else
2642 asm_fprintf (file, "%Rsp@");
2643#endif
2644 }
2645 else if (letter == '!')
2646 {
cffd0d74 2647 asm_fprintf (file, "%Rfpcr");
79e68feb
RS		 2648 }
2649 else if (letter == '$')
2650 {
2651 if (TARGET_68040_ONLY)
2652 {
2653 fprintf (file, "s");
2654 }
2655 }
2656 else if (letter == '&')
2657 {
2658 if (TARGET_68040_ONLY)
2659 {
2660 fprintf (file, "d");
2661 }
2662 }
2ac5f14a
ILT		 2663 else if (letter == '/')
2664 {
2665 asm_fprintf (file, "%R");
2666 }
79e68feb
RS		 2667 else if (GET_CODE (op) == REG)
2668 {
f4a6e73b 2669#ifdef SUPPORT_SUN_FPA
79e68feb
RS		 2670 if (REGNO (op) < 16
2671 && (letter == 'y' || letter == 'x')
2672 && GET_MODE (op) == DFmode)
2673 {
2674 fprintf (file, "%s:%s", reg_names[REGNO (op)],
2675 reg_names[REGNO (op)+1]);
2676 }
2677 else
f4a6e73b 2678#endif
79e68feb 2679 {
7f49c331
RK		 2680 if (letter == 'R')
2681 /* Print out the second register name of a register pair.
2682 I.e., R (6) => 7. */
2683 fputs (reg_names[REGNO (op) + 1], file);
2684 else
2685 fputs (reg_names[REGNO (op)], file);
79e68feb
RS		 2686 }
2687 }
2688 else if (GET_CODE (op) == MEM)
2689 {
2690 output_address (XEXP (op, 0));
2691 if (letter == 'd' && ! TARGET_68020
2692 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2693 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2694 && INTVAL (XEXP (op, 0)) < 0x8000
2695 && INTVAL (XEXP (op, 0)) >= -0x8000))
2696 {
3f889ae8
RK		 2697#ifdef MOTOROLA
2698 fprintf (file, ".l");
2699#else
79e68feb 2700 fprintf (file, ":l");
3f889ae8 2701#endif
79e68feb
RS		 2702 }
2703 }
2704#ifdef SUPPORT_SUN_FPA
2705 else if ((letter == 'y' || letter == 'w')
64a184e9 2706 && GET_CODE (op) == CONST_DOUBLE
79e68feb
RS		 2707 && (i = standard_sun_fpa_constant_p (op)))
2708 {
2709 fprintf (file, "%%%d", i & 0x1ff);
2710 }
2711#endif
2712 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2713 {
c1cfb2ae
RS		 2714 REAL_VALUE_TYPE r;
2715 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2716 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2717 }
2718 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2719 {
2720 REAL_VALUE_TYPE r;
2721 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2722 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
79e68feb 2723 }
e2c0a924 2724 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
79e68feb 2725 {
c1cfb2ae
RS		 2726 REAL_VALUE_TYPE r;
2727 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2728 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
79e68feb
RS		 2729 }
2730 else
2731 {
cffd0d74 2732 asm_fprintf (file, "%0I"); output_addr_const (file, op);
79e68feb
RS		 2733 }
2734}
2735
2736\f
2737/* A C compound statement to output to stdio stream STREAM the
2738 assembler syntax for an instruction operand that is a memory
2739 reference whose address is ADDR. ADDR is an RTL expression.
2740
2741 Note that this contains a kludge that knows that the only reason
2742 we have an address (plus (label_ref...) (reg...)) when not generating
2743 PIC code is in the insn before a tablejump, and we know that m68k.md
2744 generates a label LInnn: on such an insn.
2745
2746 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2747 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2748
2749 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2750 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2751 we want. This difference can be accommodated by using an assembler
2752 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2753 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
ad7c12b2 2754 macro. See m68k/sgs.h for an example; for versions without the bug.
f4a6e73b
RK		 2755 Some assemblers refuse all the above solutions. The workaround is to
2756 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2757 right behaviour.
79e68feb
RS		 2758
2759 They also do not like things like "pea 1.w", so we simple leave off
2760 the .w on small constants.
2761
2762 This routine is responsible for distinguishing between -fpic and -fPIC
2763 style relocations in an address. When generating -fpic code the
2764 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2765 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2766
f4a6e73b
RK		 2767#ifndef ASM_OUTPUT_CASE_FETCH
2768#ifdef MOTOROLA
2769#ifdef SGS
2770#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2771 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2772#else
2773#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2774 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2775#endif
2776#else
2777#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2778 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2779#endif
2780#endif /* ASM_OUTPUT_CASE_FETCH */
2781
79e68feb
RS		 2782void
2783print_operand_address (file, addr)
2784 FILE *file;
2785 rtx addr;
2786{
2787 register rtx reg1, reg2, breg, ireg;
2788 rtx offset;
2789
2790 switch (GET_CODE (addr))
2791 {
2792 case REG:
2793#ifdef MOTOROLA
2794 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2795#else
2796 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2797#endif
2798 break;
2799 case PRE_DEC:
2800#ifdef MOTOROLA
2801 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2802#else
2803 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2804#endif
2805 break;
2806 case POST_INC:
2807#ifdef MOTOROLA
2808 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2809#else
2810 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2811#endif
2812 break;
2813 case PLUS:
2814 reg1 = reg2 = ireg = breg = offset = 0;
2815 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2816 {
2817 offset = XEXP (addr, 0);
2818 addr = XEXP (addr, 1);
2819 }
2820 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2821 {
2822 offset = XEXP (addr, 1);
2823 addr = XEXP (addr, 0);
2824 }
2825 if (GET_CODE (addr) != PLUS)
2826 {
2827 ;
2828 }
2829 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2830 {
2831 reg1 = XEXP (addr, 0);
2832 addr = XEXP (addr, 1);
2833 }
2834 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2835 {
2836 reg1 = XEXP (addr, 1);
2837 addr = XEXP (addr, 0);
2838 }
2839 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2840 {
2841 reg1 = XEXP (addr, 0);
2842 addr = XEXP (addr, 1);
2843 }
2844 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2845 {
2846 reg1 = XEXP (addr, 1);
2847 addr = XEXP (addr, 0);
2848 }
2849 else if (GET_CODE (XEXP (addr, 0)) == REG)
2850 {
2851 reg1 = XEXP (addr, 0);
2852 addr = XEXP (addr, 1);
2853 }
2854 else if (GET_CODE (XEXP (addr, 1)) == REG)
2855 {
2856 reg1 = XEXP (addr, 1);
2857 addr = XEXP (addr, 0);
2858 }
2859 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2860 || GET_CODE (addr) == SIGN_EXTEND)
2861 {
2862 if (reg1 == 0)
2863 {
2864 reg1 = addr;
2865 }
2866 else
2867 {
2868 reg2 = addr;
2869 }
2870 addr = 0;
2871 }
2872#if 0 /* for OLD_INDEXING */
2873 else if (GET_CODE (addr) == PLUS)
2874 {
2875 if (GET_CODE (XEXP (addr, 0)) == REG)
2876 {
2877 reg2 = XEXP (addr, 0);
2878 addr = XEXP (addr, 1);
2879 }
2880 else if (GET_CODE (XEXP (addr, 1)) == REG)
2881 {
2882 reg2 = XEXP (addr, 1);
2883 addr = XEXP (addr, 0);
2884 }
2885 }
2886#endif
2887 if (offset != 0)
2888 {
2889 if (addr != 0)
2890 {
2891 abort ();
2892 }
2893 addr = offset;
2894 }
2895 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
2896 || GET_CODE (reg1) == MULT))
2897 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2898 {
2899 breg = reg2;
2900 ireg = reg1;
2901 }
2902 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2903 {
2904 breg = reg1;
2905 ireg = reg2;
2906 }
2907 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
63d415c0 2908 && ! (flag_pic && ireg == pic_offset_table_rtx))
79e68feb
RS		 2909 {
2910 int scale = 1;
2911 if (GET_CODE (ireg) == MULT)
2912 {
2913 scale = INTVAL (XEXP (ireg, 1));
2914 ireg = XEXP (ireg, 0);
2915 }
2916 if (GET_CODE (ireg) == SIGN_EXTEND)
2917 {
f4a6e73b 2918 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2919 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2920 reg_names[REGNO (XEXP (ireg, 0))]);
f4a6e73b 2921 fprintf (file, "w");
79e68feb
RS		 2922 }
2923 else
2924 {
f4a6e73b 2925 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2926 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2927 reg_names[REGNO (ireg)]);
f4a6e73b 2928 fprintf (file, "l");
79e68feb
RS		 2929 }
2930 if (scale != 1)
2931 {
2932#ifdef MOTOROLA
2933 fprintf (file, "*%d", scale);
2934#else
2935 fprintf (file, ":%d", scale);
2936#endif
2937 }
2938 putc (')', file);
2939 break;
2940 }
2941 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
63d415c0 2942 && ! (flag_pic && breg == pic_offset_table_rtx))
79e68feb 2943 {
f4a6e73b 2944 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 2945 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2946 reg_names[REGNO (breg)]);
f4a6e73b 2947 fprintf (file, "l)");
79e68feb
RS		 2948 break;
2949 }
2950 if (ireg != 0 || breg != 0)
2951 {
2952 int scale = 1;
2953 if (breg == 0)
2954 {
2955 abort ();
2956 }
2957 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
2958 {
2959 abort ();
2960 }
2961#ifdef MOTOROLA
2962 if (addr != 0)
2963 {
2964 output_addr_const (file, addr);
66c432a7
RS		 2965 if (flag_pic && (breg == pic_offset_table_rtx))
2966 fprintf (file, "@GOT");
79e68feb
RS		 2967 }
2968 fprintf (file, "(%s", reg_names[REGNO (breg)]);
2969 if (ireg != 0)
2970 {
2971 putc (',', file);
2972 }
2973#else
2974 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
2975 if (addr != 0)
2976 {
2977 output_addr_const (file, addr);
2978 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
2979 fprintf (file, ":w");
2980 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
2981 fprintf (file, ":l");
2982 }
2983 if (addr != 0 && ireg != 0)
2984 {
2985 putc (',', file);
2986 }
2987#endif
2988 if (ireg != 0 && GET_CODE (ireg) == MULT)
2989 {
2990 scale = INTVAL (XEXP (ireg, 1));
2991 ireg = XEXP (ireg, 0);
2992 }
2993 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
2994 {
2995#ifdef MOTOROLA
2996 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
2997#else
2998 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
2999#endif
3000 }
3001 else if (ireg != 0)
3002 {
3003#ifdef MOTOROLA
3004 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3005#else
3006 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3007#endif
3008 }
3009 if (scale != 1)
3010 {
3011#ifdef MOTOROLA
3012 fprintf (file, "*%d", scale);
3013#else
3014 fprintf (file, ":%d", scale);
3015#endif
3016 }
3017 putc (')', file);
3018 break;
3019 }
3020 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
63d415c0 3021 && ! (flag_pic && reg1 == pic_offset_table_rtx))
79e68feb 3022 {
f4a6e73b 3023 ASM_OUTPUT_CASE_FETCH (file,
79e68feb
RS		 3024 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3025 reg_names[REGNO (reg1)]);
f4a6e73b 3026 fprintf (file, "l)");
79e68feb
RS		 3027 break;
3028 }
3029 /* FALL-THROUGH (is this really what we want? */
3030 default:
3031 if (GET_CODE (addr) == CONST_INT
3032 && INTVAL (addr) < 0x8000
3033 && INTVAL (addr) >= -0x8000)
3034 {
3035#ifdef MOTOROLA
3036#ifdef SGS
3037 /* Many SGS assemblers croak on size specifiers for constants. */
3038 fprintf (file, "%d", INTVAL (addr));
3039#else
3040 fprintf (file, "%d.w", INTVAL (addr));
3041#endif
3042#else
3043 fprintf (file, "%d:w", INTVAL (addr));
3044#endif
3045 }
3046 else
3047 {
3048 output_addr_const (file, addr);
3049 }
3050 break;
3051 }
3052}
af13f02d
JW		 3053\f
3054/* Check for cases where a clr insns can be omitted from code using
3055 strict_low_part sets. For example, the second clrl here is not needed:
3056 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3057
3058 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3059 insn we are checking for redundancy. TARGET is the register set by the
3060 clear insn. */
3061
3062int
3063strict_low_part_peephole_ok (mode, first_insn, target)
3064 enum machine_mode mode;
3065 rtx first_insn;
3066 rtx target;
3067{
3068 rtx p;
3069
3070 p = prev_nonnote_insn (first_insn);
3071
3072 while (p)
3073 {
3074 /* If it isn't an insn, then give up. */
3075 if (GET_CODE (p) != INSN)
3076 return 0;
3077
3078 if (reg_set_p (target, p))
3079 {
3080 rtx set = single_set (p);
3081 rtx dest;
3082
3083 /* If it isn't an easy to recognize insn, then give up. */
3084 if (! set)
3085 return 0;
3086
3087 dest = SET_DEST (set);
3088
3089 /* If this sets the entire target register to zero, then our
3090 first_insn is redundant. */
3091 if (rtx_equal_p (dest, target)
3092 && SET_SRC (set) == const0_rtx)
3093 return 1;
3094 else if (GET_CODE (dest) == STRICT_LOW_PART
3095 && GET_CODE (XEXP (dest, 0)) == REG
3096 && REGNO (XEXP (dest, 0)) == REGNO (target)
3097 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3098 <= GET_MODE_SIZE (mode)))
3099 /* This is a strict low part set which modifies less than
3100 we are using, so it is safe. */
3101 ;
3102 else
3103 return 0;
3104 }
3105
3106 p = prev_nonnote_insn (p);
3107
3108 }
3109
3110 return 0;
3111}
67cd4f83
TG		 3112
3113/* Accept integer operands in the range 0..0xffffffff. We have to check the
3114 range carefully since this predicate is used in DImode contexts. Also, we
3115 need some extra crud to make it work when hosted on 64-bit machines. */
3116
3117int
3118const_uint32_operand (op, mode)
3119 rtx op;
3120 enum machine_mode mode;
3121{
3122#if HOST_BITS_PER_WIDE_INT > 32
3123 /* All allowed constants will fit a CONST_INT. */
3124 return (GET_CODE (op) == CONST_INT
3125 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3126#else
fd25a29a 3127 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
67cd4f83
TG		 3128 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3129#endif
3130}
3131
3132/* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3133 to check the range carefully since this predicate is used in DImode
3134 contexts. */
3135
3136int
3137const_sint32_operand (op, mode)
3138 rtx op;
3139 enum machine_mode mode;
3140{
3141 /* All allowed constants will fit a CONST_INT. */
3142 return (GET_CODE (op) == CONST_INT
3143 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3144}
Mirror of https://gcc.gnu.org/git/gcc.git