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Commit | Line | Data |
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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
a8c253d0 | 3 | 2001, 2003, 2004, 2005, 2006 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
20 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
79e68feb | 22 | |
79e68feb | 23 | #include "config.h" |
f5220a5d | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
da932f04 | 27 | #include "tree.h" |
79e68feb | 28 | #include "rtl.h" |
49ad7cfa | 29 | #include "function.h" |
79e68feb RS |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
79e68feb RS |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
1d8eaa6b | 37 | #include "recog.h" |
f5220a5d | 38 | #include "toplev.h" |
6d5f49b2 RH |
39 | #include "expr.h" |
40 | #include "reload.h" | |
5505f548 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
2cc07db4 | 44 | #include "debug.h" |
79e68feb RS |
45 | #include "flags.h" |
46 | ||
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
e6d98cb0 BI |
59 | /* The ASM_DOT macro allows easy string pasting to handle the differences |
60 | between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't | |
61 | support the %. option. */ | |
62 | #if MOTOROLA | |
63 | # define ASM_DOT "." | |
64 | # define ASM_DOTW ".w" | |
65 | # define ASM_DOTL ".l" | |
66 | #else | |
67 | # define ASM_DOT "" | |
68 | # define ASM_DOTW "" | |
69 | # define ASM_DOTL "" | |
70 | #endif | |
71 | ||
72 | ||
ff482c8d | 73 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
74 | struct m68k_frame |
75 | { | |
76 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 77 | HOST_WIDE_INT offset; |
3d74bc09 BI |
78 | |
79 | /* Offset of FPU registers. */ | |
80 | HOST_WIDE_INT foffset; | |
81 | ||
82 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 83 | HOST_WIDE_INT size; |
3d74bc09 BI |
84 | |
85 | /* Data and address register. */ | |
48ed72a4 PB |
86 | int reg_no; |
87 | unsigned int reg_mask; | |
88 | unsigned int reg_rev_mask; | |
3d74bc09 BI |
89 | |
90 | /* FPU registers. */ | |
48ed72a4 PB |
91 | int fpu_no; |
92 | unsigned int fpu_mask; | |
93 | unsigned int fpu_rev_mask; | |
3d74bc09 BI |
94 | |
95 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
96 | HOST_WIDE_INT frame_pointer_offset; |
97 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
98 | |
99 | /* Function which the above information refers to. */ | |
100 | int funcdef_no; | |
48ed72a4 PB |
101 | }; |
102 | ||
3d74bc09 BI |
103 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
104 | static struct m68k_frame current_frame; | |
105 | ||
4af06170 | 106 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
107 | static rtx find_addr_reg (rtx); |
108 | static const char *singlemove_string (rtx *); | |
109 | static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT); | |
110 | static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
45849738 | 111 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 112 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 113 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
114 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
115 | HOST_WIDE_INT, tree); | |
8636be86 | 116 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
117 | static bool m68k_interrupt_function_p (tree func); |
118 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, | |
119 | tree args, int flags, | |
120 | bool *no_add_attrs); | |
3d74bc09 | 121 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 122 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
8a4a2253 | 123 | static bool m68k_rtx_costs (rtx, int, int, int *); |
79e68feb RS |
124 | \f |
125 | ||
a2ef3db7 | 126 | /* Specify the identification number of the library being built */ |
4af06170 | 127 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 128 | |
2b3600ac JL |
129 | /* Nonzero if the last compare/test insn had FP operands. The |
130 | sCC expanders peek at this to determine what to do for the | |
131 | 68060, which has no fsCC instructions. */ | |
132 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
133 | \f |
134 | /* Initialize the GCC target structure. */ | |
301d03af RS |
135 | |
136 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
137 | #undef TARGET_ASM_ALIGNED_HI_OP | |
138 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
139 | #endif | |
140 | ||
141 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
142 | #undef TARGET_ASM_BYTE_OP | |
143 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
144 | #undef TARGET_ASM_ALIGNED_HI_OP | |
145 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
146 | #undef TARGET_ASM_ALIGNED_SI_OP | |
147 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
148 | #endif | |
149 | ||
150 | #if INT_OP_GROUP == INT_OP_DC | |
151 | #undef TARGET_ASM_BYTE_OP | |
152 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
153 | #undef TARGET_ASM_ALIGNED_HI_OP | |
154 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
155 | #undef TARGET_ASM_ALIGNED_SI_OP | |
156 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
157 | #endif | |
158 | ||
159 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
160 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
161 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
162 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
163 | ||
08c148a8 NB |
164 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
165 | #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue | |
166 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
167 | #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue | |
ef1dbfb0 | 168 | |
c590b625 RH |
169 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
170 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 AS |
171 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
172 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 173 | |
1bc7c5b6 ZW |
174 | #undef TARGET_ASM_FILE_START_APP_OFF |
175 | #define TARGET_ASM_FILE_START_APP_OFF true | |
176 | ||
4af06170 | 177 | #undef TARGET_DEFAULT_TARGET_FLAGS |
900ec02d | 178 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT |
4af06170 RS |
179 | #undef TARGET_HANDLE_OPTION |
180 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
181 | ||
3c50106f RH |
182 | #undef TARGET_RTX_COSTS |
183 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
184 | ||
48ed72a4 PB |
185 | #undef TARGET_ATTRIBUTE_TABLE |
186 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
187 | ||
8636be86 KH |
188 | #undef TARGET_PROMOTE_PROTOTYPES |
189 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
190 | ||
191 | #undef TARGET_STRUCT_VALUE_RTX | |
192 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
193 | ||
48ed72a4 PB |
194 | static const struct attribute_spec m68k_attribute_table[] = |
195 | { | |
196 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
197 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, | |
198 | { NULL, 0, 0, false, false, false, NULL } | |
199 | }; | |
200 | ||
f6897b10 | 201 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 202 | \f |
900ec02d JB |
203 | /* Base flags for 68k ISAs. */ |
204 | #define FL_FOR_isa_00 FL_ISA_68000 | |
205 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
206 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
207 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
208 | not to. */ | |
209 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
210 | | FL_BITFIELD | FL_68881) | |
211 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
212 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
213 | ||
214 | /* Base flags for ColdFire ISAs. */ | |
215 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
216 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
217 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
218 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
219 | #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP) | |
220 | ||
221 | enum m68k_isa | |
222 | { | |
223 | /* Traditional 68000 instruction sets. */ | |
224 | isa_00, | |
225 | isa_10, | |
226 | isa_20, | |
227 | isa_40, | |
228 | isa_cpu32, | |
229 | /* ColdFire instruction set variants. */ | |
230 | isa_a, | |
231 | isa_aplus, | |
232 | isa_b, | |
233 | isa_c, | |
234 | isa_max | |
235 | }; | |
236 | ||
237 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
238 | struct m68k_target_selection | |
239 | { | |
240 | /* The argument being described. */ | |
241 | const char *name; | |
242 | ||
243 | /* For -mcpu, this is the device selected by the option. | |
244 | For -mtune and -march, it is a representative device | |
245 | for the microarchitecture or ISA respectively. */ | |
246 | enum target_device device; | |
247 | ||
248 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
249 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
250 | const char *family; | |
251 | enum uarch_type microarch; | |
252 | enum m68k_isa isa; | |
253 | unsigned long flags; | |
254 | }; | |
255 | ||
256 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
257 | static const struct m68k_target_selection all_devices[] = | |
258 | { | |
259 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
260 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
261 | #include "m68k-devices.def" | |
262 | #undef M68K_DEVICE | |
263 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
264 | }; | |
265 | ||
266 | /* A list of all ISAs, mapping each one to a representative device. | |
267 | Used for -march selection. */ | |
268 | static const struct m68k_target_selection all_isas[] = | |
269 | { | |
270 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
271 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
272 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
273 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
274 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
275 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
276 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
277 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
278 | | FL_CF_HWDIV) }, | |
279 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
280 | | FL_CF_HWDIV) }, | |
281 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
282 | { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c | |
283 | | FL_CF_FPU | |
284 | | FL_CF_EMAC) }, | |
285 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
286 | }; | |
287 | ||
288 | /* A list of all microarchitectures, mapping each one to a representative | |
289 | device. Used for -mtune selection. */ | |
290 | static const struct m68k_target_selection all_microarchs[] = | |
291 | { | |
292 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
293 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
294 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
295 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
296 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
297 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
298 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
299 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
300 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
301 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, | |
302 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
303 | | FL_CF_HWDIV) }, | |
304 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
305 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
306 | | FL_CF_USP | |
307 | | FL_CF_EMAC | |
308 | | FL_CF_FPU) }, | |
309 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
310 | }; | |
311 | \f | |
312 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
313 | or null for options that have not been used. */ | |
314 | const struct m68k_target_selection *m68k_cpu_entry; | |
315 | const struct m68k_target_selection *m68k_arch_entry; | |
316 | const struct m68k_target_selection *m68k_tune_entry; | |
317 | ||
318 | /* Which CPU we are generating code for. */ | |
319 | enum target_device m68k_cpu; | |
320 | ||
321 | /* Which microarchitecture to tune for. */ | |
322 | enum uarch_type m68k_tune; | |
323 | ||
324 | /* Which FPU to use. */ | |
325 | enum fpu_type m68k_fpu; | |
4af06170 | 326 | |
900ec02d JB |
327 | /* The set of FL_* flags that apply to the target processor. */ |
328 | unsigned int m68k_cpu_flags; | |
29ca003a RS |
329 | |
330 | /* Asm templates for calling or jumping to an arbitrary symbolic address, | |
331 | or NULL if such calls or jumps are not supported. The address is held | |
332 | in operand 0. */ | |
333 | const char *m68k_symbolic_call; | |
334 | const char *m68k_symbolic_jump; | |
900ec02d JB |
335 | \f |
336 | /* See whether TABLE has an entry with name NAME. Return true and | |
337 | store the entry in *ENTRY if so, otherwise return false and | |
338 | leave *ENTRY alone. */ | |
339 | ||
340 | static bool | |
341 | m68k_find_selection (const struct m68k_target_selection **entry, | |
342 | const struct m68k_target_selection *table, | |
343 | const char *name) | |
344 | { | |
345 | size_t i; | |
346 | ||
347 | for (i = 0; table[i].name; i++) | |
348 | if (strcmp (table[i].name, name) == 0) | |
349 | { | |
350 | *entry = table + i; | |
351 | return true; | |
352 | } | |
353 | return false; | |
354 | } | |
4af06170 RS |
355 | |
356 | /* Implement TARGET_HANDLE_OPTION. */ | |
357 | ||
358 | static bool | |
359 | m68k_handle_option (size_t code, const char *arg, int value) | |
360 | { | |
361 | switch (code) | |
362 | { | |
900ec02d JB |
363 | case OPT_march_: |
364 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
365 | ||
366 | case OPT_mcpu_: | |
367 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
368 | ||
369 | case OPT_mtune_: | |
370 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
371 | ||
4af06170 | 372 | case OPT_m5200: |
900ec02d | 373 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
374 | |
375 | case OPT_m5206e: | |
900ec02d | 376 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
377 | |
378 | case OPT_m528x: | |
900ec02d | 379 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
380 | |
381 | case OPT_m5307: | |
900ec02d | 382 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
383 | |
384 | case OPT_m5407: | |
900ec02d | 385 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 386 | |
dcc21c4c | 387 | case OPT_mcfv4e: |
900ec02d | 388 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 389 | |
4af06170 RS |
390 | case OPT_m68000: |
391 | case OPT_mc68000: | |
900ec02d | 392 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 393 | |
3197c489 | 394 | case OPT_m68010: |
900ec02d | 395 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 396 | |
4af06170 RS |
397 | case OPT_m68020: |
398 | case OPT_mc68020: | |
900ec02d | 399 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
400 | |
401 | case OPT_m68020_40: | |
900ec02d JB |
402 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
403 | "68020-40") | |
404 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
405 | |
406 | case OPT_m68020_60: | |
900ec02d JB |
407 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
408 | "68020-60") | |
409 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
410 | |
411 | case OPT_m68030: | |
900ec02d | 412 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
413 | |
414 | case OPT_m68040: | |
900ec02d | 415 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
416 | |
417 | case OPT_m68060: | |
900ec02d | 418 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
419 | |
420 | case OPT_m68302: | |
900ec02d | 421 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
422 | |
423 | case OPT_m68332: | |
424 | case OPT_mcpu32: | |
900ec02d | 425 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
426 | |
427 | case OPT_mshared_library_id_: | |
428 | if (value > MAX_LIBRARY_ID) | |
429 | error ("-mshared-library-id=%s is not between 0 and %d", | |
430 | arg, MAX_LIBRARY_ID); | |
431 | else | |
432 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
433 | return true; | |
434 | ||
435 | default: | |
436 | return true; | |
437 | } | |
438 | } | |
439 | ||
ef1dbfb0 RK |
440 | /* Sometimes certain combinations of command options do not make |
441 | sense on a particular target machine. You can define a macro | |
442 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
443 | defined, is executed once just after all the command options have | |
444 | been parsed. | |
445 | ||
446 | Don't use this macro to turn on various extra optimizations for | |
447 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
448 | ||
449 | void | |
8a4a2253 | 450 | override_options (void) |
ef1dbfb0 | 451 | { |
900ec02d JB |
452 | const struct m68k_target_selection *entry; |
453 | unsigned long target_mask; | |
454 | ||
455 | /* User can choose: | |
456 | ||
457 | -mcpu= | |
458 | -march= | |
459 | -mtune= | |
460 | ||
461 | -march=ARCH should generate code that runs any processor | |
462 | implementing architecture ARCH. -mcpu=CPU should override -march | |
463 | and should generate code that runs on processor CPU, making free | |
464 | use of any instructions that CPU understands. -mtune=UARCH applies | |
465 | on top of -mcpu or -march and optimises the code for UARCH. It does | |
466 | not change the target architecture. */ | |
467 | if (m68k_cpu_entry) | |
468 | { | |
469 | /* Complain if the -march setting is for a different microarchitecture, | |
470 | or includes flags that the -mcpu setting doesn't. */ | |
471 | if (m68k_arch_entry | |
472 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
473 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
474 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
475 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
476 | ||
477 | entry = m68k_cpu_entry; | |
478 | } | |
479 | else | |
480 | entry = m68k_arch_entry; | |
481 | ||
482 | if (!entry) | |
483 | entry = all_devices + TARGET_CPU_DEFAULT; | |
484 | ||
485 | m68k_cpu_flags = entry->flags; | |
486 | ||
487 | /* Use the architecture setting to derive default values for | |
488 | certain flags. */ | |
489 | target_mask = 0; | |
490 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) | |
491 | target_mask |= MASK_BITFIELD; | |
492 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
493 | target_mask |= MASK_CF_HWDIV; | |
494 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
495 | target_mask |= MASK_HARD_FLOAT; | |
496 | target_flags |= target_mask & ~target_flags_explicit; | |
497 | ||
498 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
499 | m68k_cpu = entry->device; | |
500 | if (m68k_tune_entry) | |
501 | m68k_tune = m68k_tune_entry->microarch; | |
502 | #ifdef M68K_DEFAULT_TUNE | |
503 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
504 | m68k_tune = M68K_DEFAULT_TUNE; | |
505 | #endif | |
506 | else | |
507 | m68k_tune = entry->microarch; | |
508 | ||
509 | /* Set the type of FPU. */ | |
510 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
511 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
512 | : FPUTYPE_68881); | |
513 | ||
58145e4d RS |
514 | if (TARGET_COLDFIRE_FPU) |
515 | { | |
516 | REAL_MODE_FORMAT (SFmode) = &coldfire_single_format; | |
517 | REAL_MODE_FORMAT (DFmode) = &coldfire_double_format; | |
518 | } | |
519 | ||
a2ef3db7 BI |
520 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
521 | * both specified together. Doing so simply doesn't make sense. | |
522 | */ | |
523 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
524 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
525 | ||
526 | /* If we're generating code for a separate A5 relative data segment, | |
527 | * we've got to enable -fPIC as well. This might be relaxable to | |
528 | * -fpic but it hasn't been tested properly. | |
529 | */ | |
530 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
531 | flag_pic = 2; | |
532 | ||
abe92a04 RS |
533 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
534 | error if the target does not support them. */ | |
535 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
536 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
537 | |
538 | /* ??? A historic way of turning on pic, or is this intended to | |
539 | be an embedded thing that doesn't have the same name binding | |
540 | significance that it does on hosted ELF systems? */ | |
541 | if (TARGET_PCREL && flag_pic == 0) | |
542 | flag_pic = 1; | |
543 | ||
29ca003a RS |
544 | if (!flag_pic) |
545 | { | |
546 | #if MOTOROLA && !defined (USE_GAS) | |
547 | m68k_symbolic_call = "jsr %a0"; | |
548 | m68k_symbolic_jump = "jmp %a0"; | |
549 | #else | |
550 | m68k_symbolic_call = "jbsr %a0"; | |
551 | m68k_symbolic_jump = "jra %a0"; | |
552 | #endif | |
553 | } | |
554 | else if (TARGET_ID_SHARED_LIBRARY) | |
555 | /* All addresses must be loaded from the GOT. */ | |
556 | ; | |
557 | else if (TARGET_68020 || TARGET_ISAB) | |
558 | { | |
559 | if (TARGET_PCREL) | |
560 | { | |
561 | m68k_symbolic_call = "bsr.l %c0"; | |
562 | m68k_symbolic_jump = "bra.l %c0"; | |
563 | } | |
564 | else | |
565 | { | |
566 | #if defined(USE_GAS) | |
567 | m68k_symbolic_call = "bsr.l %p0"; | |
568 | m68k_symbolic_jump = "bra.l %p0"; | |
569 | #else | |
570 | m68k_symbolic_call = "bsr %p0"; | |
571 | m68k_symbolic_jump = "bra %p0"; | |
572 | #endif | |
573 | } | |
574 | /* Turn off function cse if we are doing PIC. We always want | |
575 | function call to be done as `bsr foo@PLTPC'. */ | |
576 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
577 | clear how intentional that is. */ | |
578 | flag_no_function_cse = 1; | |
579 | } | |
adf2ac37 RH |
580 | |
581 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 582 | } |
7eb4f044 NS |
583 | |
584 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the | |
585 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
586 | if -mcpu was not passed. */ | |
587 | ||
588 | const char * | |
589 | m68k_cpp_cpu_ident (const char *prefix) | |
590 | { | |
591 | if (!m68k_cpu_entry) | |
592 | return NULL; | |
593 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
594 | } | |
595 | ||
596 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
597 | given argument and NAME is the name of the representative device for | |
598 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
599 | ||
600 | const char * | |
601 | m68k_cpp_cpu_family (const char *prefix) | |
602 | { | |
603 | if (!m68k_cpu_entry) | |
604 | return NULL; | |
605 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
606 | } | |
79e68feb | 607 | \f |
48ed72a4 PB |
608 | /* Return nonzero if FUNC is an interrupt function as specified by the |
609 | "interrupt_handler" attribute. */ | |
610 | static bool | |
611 | m68k_interrupt_function_p(tree func) | |
612 | { | |
613 | tree a; | |
614 | ||
615 | if (TREE_CODE (func) != FUNCTION_DECL) | |
616 | return false; | |
617 | ||
618 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); | |
619 | return (a != NULL_TREE); | |
620 | } | |
621 | ||
622 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
623 | struct attribute_spec.handler. */ | |
624 | static tree | |
625 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
626 | tree args ATTRIBUTE_UNUSED, | |
627 | int flags ATTRIBUTE_UNUSED, | |
628 | bool *no_add_attrs) | |
629 | { | |
630 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
631 | { | |
5c498b10 | 632 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
633 | IDENTIFIER_POINTER (name)); |
634 | *no_add_attrs = true; | |
635 | } | |
636 | ||
637 | return NULL_TREE; | |
638 | } | |
860c4900 BI |
639 | |
640 | static void | |
3d74bc09 | 641 | m68k_compute_frame_layout (void) |
860c4900 BI |
642 | { |
643 | int regno, saved; | |
644 | unsigned int mask, rmask; | |
48ed72a4 | 645 | bool interrupt_handler = m68k_interrupt_function_p (current_function_decl); |
860c4900 | 646 | |
3d74bc09 BI |
647 | /* Only compute the frame once per function. |
648 | Don't cache information until reload has been completed. */ | |
649 | if (current_frame.funcdef_no == current_function_funcdef_no | |
650 | && reload_completed) | |
651 | return; | |
652 | ||
653 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 BI |
654 | |
655 | mask = rmask = saved = 0; | |
656 | for (regno = 0; regno < 16; regno++) | |
48ed72a4 | 657 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 BI |
658 | { |
659 | mask |= 1 << regno; | |
660 | rmask |= 1 << (15 - regno); | |
661 | saved++; | |
662 | } | |
3d74bc09 BI |
663 | current_frame.offset = saved * 4; |
664 | current_frame.reg_no = saved; | |
665 | current_frame.reg_mask = mask; | |
666 | current_frame.reg_rev_mask = rmask; | |
860c4900 | 667 | |
57047680 GN |
668 | current_frame.foffset = 0; |
669 | mask = rmask = saved = 0; | |
dcc21c4c | 670 | if (TARGET_HARD_FLOAT) |
860c4900 | 671 | { |
860c4900 | 672 | for (regno = 16; regno < 24; regno++) |
3d74bc09 | 673 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 674 | { |
85802504 GN |
675 | mask |= 1 << (regno - 16); |
676 | rmask |= 1 << (23 - regno); | |
860c4900 BI |
677 | saved++; |
678 | } | |
dcc21c4c | 679 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 680 | current_frame.offset += current_frame.foffset; |
860c4900 | 681 | } |
57047680 GN |
682 | current_frame.fpu_no = saved; |
683 | current_frame.fpu_mask = mask; | |
684 | current_frame.fpu_rev_mask = rmask; | |
3d74bc09 BI |
685 | |
686 | /* Remember what function this frame refers to. */ | |
687 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
688 | } |
689 | ||
690 | HOST_WIDE_INT | |
691 | m68k_initial_elimination_offset (int from, int to) | |
692 | { | |
42b67c06 PB |
693 | int argptr_offset; |
694 | /* The arg pointer points 8 bytes before the start of the arguments, | |
695 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
696 | frame pointer in most frames. */ | |
697 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 698 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 699 | return argptr_offset; |
860c4900 | 700 | |
3d74bc09 | 701 | m68k_compute_frame_layout (); |
860c4900 | 702 | |
4761e388 NS |
703 | gcc_assert (to == STACK_POINTER_REGNUM); |
704 | switch (from) | |
705 | { | |
a0a7fbc9 | 706 | case ARG_POINTER_REGNUM: |
42b67c06 | 707 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
708 | case FRAME_POINTER_REGNUM: |
709 | return current_frame.offset + current_frame.size; | |
710 | default: | |
711 | gcc_unreachable (); | |
712 | } | |
860c4900 BI |
713 | } |
714 | ||
97c55091 GN |
715 | /* Refer to the array `regs_ever_live' to determine which registers |
716 | to save; `regs_ever_live[I]' is nonzero if register number I | |
717 | is ever used in the function. This function is responsible for | |
718 | knowing which registers should not be saved even if used. | |
719 | Return true if we need to save REGNO. */ | |
720 | ||
48ed72a4 PB |
721 | static bool |
722 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 723 | { |
b86ba8a3 AT |
724 | if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM) |
725 | { | |
726 | if (current_function_uses_pic_offset_table) | |
727 | return true; | |
728 | if (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY) | |
729 | return true; | |
730 | } | |
2cff4a6e AS |
731 | |
732 | if (current_function_calls_eh_return) | |
733 | { | |
734 | unsigned int i; | |
735 | for (i = 0; ; i++) | |
736 | { | |
737 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
738 | if (test == INVALID_REGNUM) | |
739 | break; | |
740 | if (test == regno) | |
48ed72a4 | 741 | return true; |
2cff4a6e AS |
742 | } |
743 | } | |
744 | ||
48ed72a4 PB |
745 | /* Fixed regs we never touch. */ |
746 | if (fixed_regs[regno]) | |
747 | return false; | |
748 | ||
749 | /* The frame pointer (if it is such) is handled specially. */ | |
750 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
751 | return false; | |
752 | ||
753 | /* Interrupt handlers must also save call_used_regs | |
754 | if they are live or when calling nested functions. */ | |
755 | if (interrupt_handler) | |
a0a7fbc9 AS |
756 | { |
757 | if (regs_ever_live[regno]) | |
758 | return true; | |
48ed72a4 | 759 | |
a0a7fbc9 AS |
760 | if (!current_function_is_leaf && call_used_regs[regno]) |
761 | return true; | |
762 | } | |
48ed72a4 PB |
763 | |
764 | /* Never need to save registers that aren't touched. */ | |
765 | if (!regs_ever_live[regno]) | |
766 | return false; | |
767 | ||
b2e08ed4 | 768 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 769 | return !call_used_regs[regno]; |
2cff4a6e AS |
770 | } |
771 | ||
79e68feb RS |
772 | /* This function generates the assembly code for function entry. |
773 | STREAM is a stdio stream to output the code to. | |
97c55091 | 774 | SIZE is an int: how many units of temporary storage to allocate. */ |
79e68feb | 775 | |
08c148a8 | 776 | static void |
a0a7fbc9 AS |
777 | m68k_output_function_prologue (FILE *stream, |
778 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
79e68feb | 779 | { |
860c4900 | 780 | HOST_WIDE_INT fsize_with_regs; |
08c148a8 | 781 | HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET; |
3d74bc09 BI |
782 | |
783 | m68k_compute_frame_layout(); | |
784 | ||
a157febd GK |
785 | /* If the stack limit is a symbol, we can check it here, |
786 | before actually allocating the space. */ | |
787 | if (current_function_limit_stack | |
788 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
e6d98cb0 BI |
789 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %I%s+%wd,%Rsp\n\ttrapcs\n", |
790 | XSTR (stack_limit_rtx, 0), current_frame.size + 4); | |
79e68feb | 791 | |
97c55091 | 792 | /* On ColdFire add register save into initial stack frame setup, if possible. */ |
a89e3f21 | 793 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
794 | if (TARGET_COLDFIRE) |
795 | { | |
796 | if (current_frame.reg_no > 2) | |
797 | fsize_with_regs += current_frame.reg_no * 4; | |
798 | if (current_frame.fpu_no) | |
799 | fsize_with_regs += current_frame.fpu_no * 8; | |
800 | } | |
860c4900 | 801 | |
79e68feb RS |
802 | if (frame_pointer_needed) |
803 | { | |
fe95f2f7 | 804 | if (current_frame.size == 0 && TUNE_68040) |
e4e873f1 | 805 | /* on the 68040, pea + move is faster than link.w 0 */ |
a0a7fbc9 AS |
806 | fprintf (stream, (MOTOROLA |
807 | ? "\tpea (%s)\n\tmove.l %s,%s\n" | |
808 | : "\tpea %s@\n\tmovel %s,%s\n"), | |
809 | M68K_REGNAME (FRAME_POINTER_REGNUM), | |
810 | M68K_REGNAME (STACK_POINTER_REGNUM), | |
811 | M68K_REGNAME (FRAME_POINTER_REGNUM)); | |
860c4900 | 812 | else if (fsize_with_regs < 0x8000) |
e6d98cb0 | 813 | asm_fprintf (stream, "\tlink" ASM_DOTW " %s,%I%wd\n", |
a0a7fbc9 | 814 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 815 | else if (TARGET_68020) |
e6d98cb0 | 816 | asm_fprintf (stream, "\tlink" ASM_DOTL " %s,%I%wd\n", |
a0a7fbc9 | 817 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 818 | else |
e6d98cb0 | 819 | /* Adding negative number is faster on the 68040. */ |
a0a7fbc9 AS |
820 | asm_fprintf (stream, |
821 | "\tlink" ASM_DOTW " %s,%I0\n" | |
822 | "\tadd" ASM_DOT "l %I%wd,%Rsp\n", | |
823 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); | |
79e68feb | 824 | } |
860c4900 | 825 | else if (fsize_with_regs) /* !frame_pointer_needed */ |
79e68feb | 826 | { |
860c4900 | 827 | if (fsize_with_regs < 0x8000) |
79e68feb | 828 | { |
860c4900 | 829 | if (fsize_with_regs <= 8) |
afaff477 | 830 | { |
9425fb04 | 831 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
832 | asm_fprintf (stream, "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", |
833 | fsize_with_regs); | |
7bc88d49 | 834 | else |
e6d98cb0 BI |
835 | asm_fprintf (stream, "\tsubq" ASM_DOT "l %I%wd,%Rsp\n", |
836 | fsize_with_regs); | |
afaff477 | 837 | } |
fe95f2f7 | 838 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
e6d98cb0 BI |
839 | /* On the CPU32 it is faster to use two subqw instructions to |
840 | subtract a small integer (8 < N <= 16) to a register. */ | |
841 | asm_fprintf (stream, | |
842 | "\tsubq" ASM_DOT "w %I8,%Rsp\n" | |
843 | "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", | |
844 | fsize_with_regs - 8); | |
fe95f2f7 | 845 | else if (TUNE_68040) |
e6d98cb0 BI |
846 | /* Adding negative number is faster on the 68040. */ |
847 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", | |
848 | -fsize_with_regs); | |
7bc88d49 | 849 | else |
a0a7fbc9 AS |
850 | asm_fprintf (stream, (MOTOROLA |
851 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
852 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 853 | -fsize_with_regs); |
79e68feb | 854 | } |
860c4900 | 855 | else /* fsize_with_regs >= 0x8000 */ |
a0a7fbc9 AS |
856 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", |
857 | -fsize_with_regs); | |
d9e88af0 | 858 | } /* !frame_pointer_needed */ |
e6d98cb0 | 859 | |
d9e88af0 PB |
860 | if (dwarf2out_do_frame ()) |
861 | { | |
862 | if (frame_pointer_needed) | |
078e983e | 863 | { |
b214e1e7 | 864 | char *l; |
d9e88af0 | 865 | l = (char *) dwarf2out_cfi_label (); |
b214e1e7 PB |
866 | cfa_offset += 4; |
867 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_offset); | |
868 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset); | |
869 | cfa_offset += current_frame.size; | |
870 | } | |
d9e88af0 | 871 | else |
b214e1e7 PB |
872 | { |
873 | cfa_offset += current_frame.size; | |
874 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); | |
875 | } | |
d9e88af0 | 876 | } |
860c4900 | 877 | |
57047680 | 878 | if (current_frame.fpu_mask) |
79e68feb | 879 | { |
dcc21c4c PB |
880 | if (TARGET_68881) |
881 | { | |
882 | asm_fprintf (stream, (MOTOROLA | |
883 | ? "\tfmovm %I0x%x,-(%Rsp)\n" | |
884 | : "\tfmovem %I0x%x,%Rsp@-\n"), | |
885 | current_frame.fpu_mask); | |
886 | } | |
887 | else | |
888 | { | |
889 | int offset; | |
890 | ||
891 | /* stack already has registers in it. Find the offset from | |
892 | the bottom of stack to where the FP registers go */ | |
893 | if (current_frame.reg_no <= 2) | |
894 | offset = 0; | |
895 | else | |
896 | offset = current_frame.reg_no * 4; | |
897 | if (offset) | |
898 | asm_fprintf (stream, | |
899 | "\tfmovem %I0x%x,%d(%Rsp)\n", | |
900 | current_frame.fpu_rev_mask, | |
901 | offset); | |
902 | else | |
903 | asm_fprintf (stream, | |
904 | "\tfmovem %I0x%x,(%Rsp)\n", | |
905 | current_frame.fpu_rev_mask); | |
906 | } | |
e6d98cb0 | 907 | |
57047680 GN |
908 | if (dwarf2out_do_frame ()) |
909 | { | |
910 | char *l = (char *) dwarf2out_cfi_label (); | |
911 | int n_regs, regno; | |
912 | ||
dcc21c4c | 913 | cfa_offset += current_frame.fpu_no * TARGET_FP_REG_SIZE; |
57047680 GN |
914 | if (! frame_pointer_needed) |
915 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
916 | for (regno = 16, n_regs = 0; regno < 24; regno++) | |
917 | if (current_frame.fpu_mask & (1 << (regno - 16))) | |
dcc21c4c PB |
918 | dwarf2out_reg_save (l, regno, -cfa_offset |
919 | + n_regs++ * TARGET_FP_REG_SIZE); | |
f277471f | 920 | } |
79e68feb | 921 | } |
99df2465 | 922 | |
01bbf777 | 923 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
924 | This has the disadvantage that it may be too late... */ |
925 | if (current_function_limit_stack) | |
926 | { | |
927 | if (REG_P (stack_limit_rtx)) | |
e6d98cb0 | 928 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %s,%Rsp\n\ttrapcs\n", |
a0a7fbc9 | 929 | M68K_REGNAME (REGNO (stack_limit_rtx))); |
a157febd | 930 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 931 | warning (0, "stack limit expression is not supported"); |
a157febd | 932 | } |
01bbf777 | 933 | |
a89e3f21 | 934 | if (current_frame.reg_no <= 2) |
79e68feb RS |
935 | { |
936 | /* Store each separately in the same order moveml uses. | |
937 | Using two movel instructions instead of a single moveml | |
938 | is about 15% faster for the 68020 and 68030 at no expense | |
97c55091 | 939 | in code size. */ |
79e68feb RS |
940 | |
941 | int i; | |
942 | ||
3d74bc09 BI |
943 | for (i = 0; i < 16; i++) |
944 | if (current_frame.reg_rev_mask & (1 << i)) | |
078e983e | 945 | { |
a0a7fbc9 AS |
946 | asm_fprintf (stream, (MOTOROLA |
947 | ? "\t%Omove.l %s,-(%Rsp)\n" | |
948 | : "\tmovel %s,%Rsp@-\n"), | |
949 | M68K_REGNAME (15 - i)); | |
078e983e AS |
950 | if (dwarf2out_do_frame ()) |
951 | { | |
f5c4bc60 | 952 | char *l = (char *) dwarf2out_cfi_label (); |
a7cc7f29 | 953 | |
ed311a33 | 954 | cfa_offset += 4; |
01bbf777 AS |
955 | if (! frame_pointer_needed) |
956 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
957 | dwarf2out_reg_save (l, 15 - i, -cfa_offset); | |
078e983e AS |
958 | } |
959 | } | |
79e68feb | 960 | } |
3d74bc09 | 961 | else if (current_frame.reg_rev_mask) |
79e68feb | 962 | { |
9425fb04 | 963 | if (TARGET_COLDFIRE) |
01bbf777 | 964 | /* The ColdFire does not support the predecrement form of the |
e6d98cb0 BI |
965 | MOVEM instruction, so we must adjust the stack pointer and |
966 | then use the plain address register indirect mode. | |
967 | The required register save space was combined earlier with | |
968 | the fsize_with_regs amount. */ | |
969 | ||
a0a7fbc9 AS |
970 | asm_fprintf (stream, (MOTOROLA |
971 | ? "\tmovm.l %I0x%x,(%Rsp)\n" | |
972 | : "\tmoveml %I0x%x,%Rsp@\n"), | |
e6d98cb0 | 973 | current_frame.reg_mask); |
afaff477 | 974 | else |
a0a7fbc9 AS |
975 | asm_fprintf (stream, (MOTOROLA |
976 | ? "\tmovm.l %I0x%x,-(%Rsp)\n" | |
977 | : "\tmoveml %I0x%x,%Rsp@-\n"), | |
e6d98cb0 | 978 | current_frame.reg_rev_mask); |
078e983e AS |
979 | if (dwarf2out_do_frame ()) |
980 | { | |
f5c4bc60 | 981 | char *l = (char *) dwarf2out_cfi_label (); |
3d74bc09 | 982 | int n_regs, regno; |
a7cc7f29 | 983 | |
3d74bc09 | 984 | cfa_offset += current_frame.reg_no * 4; |
078e983e | 985 | if (! frame_pointer_needed) |
ed311a33 | 986 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); |
078e983e | 987 | for (regno = 0, n_regs = 0; regno < 16; regno++) |
3d74bc09 | 988 | if (current_frame.reg_mask & (1 << regno)) |
57047680 | 989 | dwarf2out_reg_save (l, regno, -cfa_offset + n_regs++ * 4); |
078e983e | 990 | } |
79e68feb | 991 | } |
a0a7fbc9 AS |
992 | if (!TARGET_SEP_DATA && flag_pic |
993 | && (current_function_uses_pic_offset_table | |
994 | || (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY))) | |
79e68feb | 995 | { |
a2ef3db7 BI |
996 | if (TARGET_ID_SHARED_LIBRARY) |
997 | { | |
998 | asm_fprintf (stream, "\tmovel %s@(%s), %s\n", | |
a0a7fbc9 | 999 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
a2ef3db7 | 1000 | m68k_library_id_string, |
a0a7fbc9 | 1001 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
a2ef3db7 BI |
1002 | } |
1003 | else | |
1004 | { | |
e6d98cb0 | 1005 | if (MOTOROLA) |
a0a7fbc9 AS |
1006 | asm_fprintf (stream, |
1007 | "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", | |
1008 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 BI |
1009 | else |
1010 | { | |
1011 | asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n", | |
a0a7fbc9 | 1012 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
e6d98cb0 | 1013 | asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", |
a0a7fbc9 AS |
1014 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
1015 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 | 1016 | } |
a2ef3db7 | 1017 | } |
79e68feb RS |
1018 | } |
1019 | } | |
1020 | \f | |
413ac1b2 RS |
1021 | /* Return true if a simple (return) instruction is sufficient for this |
1022 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1023 | |
3d74bc09 | 1024 | bool |
a2bda628 | 1025 | m68k_use_return_insn (void) |
79e68feb | 1026 | { |
79e68feb | 1027 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1028 | return false; |
125ed86f | 1029 | |
a0a7fbc9 | 1030 | m68k_compute_frame_layout (); |
413ac1b2 | 1031 | return current_frame.offset == 0; |
79e68feb RS |
1032 | } |
1033 | ||
1034 | /* This function generates the assembly code for function exit, | |
08c148a8 | 1035 | on machines that need it. |
79e68feb RS |
1036 | |
1037 | The function epilogue should not depend on the current stack pointer! | |
1038 | It should use the frame pointer only, if there is a frame pointer. | |
1039 | This is mandatory because of alloca; we also take advantage of it to | |
1040 | omit stack adjustments before returning. */ | |
1041 | ||
08c148a8 | 1042 | static void |
a0a7fbc9 AS |
1043 | m68k_output_function_epilogue (FILE *stream, |
1044 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
08c148a8 | 1045 | { |
3d74bc09 BI |
1046 | HOST_WIDE_INT fsize, fsize_with_regs; |
1047 | bool big = false; | |
1048 | bool restore_from_sp = false; | |
79e68feb | 1049 | rtx insn = get_last_insn (); |
3d74bc09 | 1050 | |
a0a7fbc9 | 1051 | m68k_compute_frame_layout (); |
3d74bc09 | 1052 | |
79e68feb RS |
1053 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
1054 | if (GET_CODE (insn) == NOTE) | |
1055 | insn = prev_nonnote_insn (insn); | |
1056 | if (insn && GET_CODE (insn) == BARRIER) | |
dfd05074 | 1057 | return; |
79e68feb | 1058 | |
3d74bc09 BI |
1059 | fsize = current_frame.size; |
1060 | ||
a0a7fbc9 | 1061 | /* FIXME: leaf_function_p below is too strong. |
c67ddce5 | 1062 | What we really need to know there is if there could be pending |
7a1929e1 | 1063 | stack adjustment needed at that point. */ |
a0a7fbc9 AS |
1064 | restore_from_sp |
1065 | = (! frame_pointer_needed | |
1066 | || (! current_function_calls_alloca && leaf_function_p ())); | |
860c4900 BI |
1067 | |
1068 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1069 | popping the frame. */ |
860c4900 BI |
1070 | fsize_with_regs = fsize; |
1071 | ||
1072 | /* Because the ColdFire doesn't support moveml with | |
1073 | complex address modes, we must adjust the stack manually | |
1074 | after restoring registers. When the frame pointer isn't used, | |
1075 | we can merge movem adjustment into frame unlinking | |
97c55091 | 1076 | made immediately after it. */ |
dcc21c4c PB |
1077 | if (TARGET_COLDFIRE && restore_from_sp) |
1078 | { | |
1079 | if (current_frame.reg_no > 2) | |
1080 | fsize_with_regs += current_frame.reg_no * 4; | |
1081 | if (current_frame.fpu_no) | |
1082 | fsize_with_regs += current_frame.fpu_no * 8; | |
1083 | } | |
860c4900 | 1084 | |
3d74bc09 | 1085 | if (current_frame.offset + fsize >= 0x8000 |
6910dd70 | 1086 | && ! restore_from_sp |
3d74bc09 | 1087 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1088 | { |
860c4900 | 1089 | /* Because the ColdFire doesn't support moveml with |
97c55091 | 1090 | complex address modes we make an extra correction here. */ |
860c4900 | 1091 | if (TARGET_COLDFIRE) |
e6d98cb0 | 1092 | fsize += current_frame.offset; |
860c4900 | 1093 | |
e6d98cb0 | 1094 | asm_fprintf (stream, "\t%Omove" ASM_DOT "l %I%wd,%Ra1\n", -fsize); |
3d74bc09 | 1095 | fsize = 0, big = true; |
79e68feb | 1096 | } |
3d74bc09 | 1097 | if (current_frame.reg_no <= 2) |
79e68feb RS |
1098 | { |
1099 | /* Restore each separately in the same order moveml does. | |
1100 | Using two movel instructions instead of a single moveml | |
1101 | is about 15% faster for the 68020 and 68030 at no expense | |
7a1929e1 | 1102 | in code size. */ |
79e68feb RS |
1103 | |
1104 | int i; | |
3d74bc09 | 1105 | HOST_WIDE_INT offset = current_frame.offset + fsize; |
79e68feb | 1106 | |
3d74bc09 BI |
1107 | for (i = 0; i < 16; i++) |
1108 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb RS |
1109 | { |
1110 | if (big) | |
1111 | { | |
e6d98cb0 BI |
1112 | if (MOTOROLA) |
1113 | asm_fprintf (stream, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n", | |
1114 | offset, | |
a0a7fbc9 AS |
1115 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1116 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1117 | else |
1118 | asm_fprintf (stream, "\tmovel %s@(-%wd,%Ra1:l),%s\n", | |
a0a7fbc9 | 1119 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1120 | offset, |
a0a7fbc9 | 1121 | M68K_REGNAME (i)); |
79e68feb | 1122 | } |
6910dd70 | 1123 | else if (restore_from_sp) |
a0a7fbc9 AS |
1124 | asm_fprintf (stream, (MOTOROLA |
1125 | ? "\t%Omove.l (%Rsp)+,%s\n" | |
1126 | : "\tmovel %Rsp@+,%s\n"), | |
1127 | M68K_REGNAME (i)); | |
79e68feb RS |
1128 | else |
1129 | { | |
e6d98cb0 BI |
1130 | if (MOTOROLA) |
1131 | asm_fprintf (stream, "\t%Omove.l -%wd(%s),%s\n", | |
1132 | offset, | |
a0a7fbc9 AS |
1133 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1134 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1135 | else |
1136 | asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n", | |
a0a7fbc9 | 1137 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1138 | offset, |
a0a7fbc9 | 1139 | M68K_REGNAME (i)); |
79e68feb | 1140 | } |
3d74bc09 | 1141 | offset -= 4; |
79e68feb RS |
1142 | } |
1143 | } | |
3d74bc09 | 1144 | else if (current_frame.reg_mask) |
79e68feb | 1145 | { |
a0a7fbc9 AS |
1146 | /* The ColdFire requires special handling due to its limited moveml |
1147 | insn. */ | |
860c4900 BI |
1148 | if (TARGET_COLDFIRE) |
1149 | { | |
1150 | if (big) | |
1151 | { | |
e6d98cb0 | 1152 | asm_fprintf (stream, "\tadd" ASM_DOT "l %s,%Ra1\n", |
a0a7fbc9 AS |
1153 | M68K_REGNAME (FRAME_POINTER_REGNUM)); |
1154 | asm_fprintf (stream, (MOTOROLA | |
1155 | ? "\tmovm.l (%Ra1),%I0x%x\n" | |
1156 | : "\tmoveml %Ra1@,%I0x%x\n"), | |
e6d98cb0 | 1157 | current_frame.reg_mask); |
860c4900 BI |
1158 | } |
1159 | else if (restore_from_sp) | |
a0a7fbc9 AS |
1160 | asm_fprintf (stream, (MOTOROLA |
1161 | ? "\tmovm.l (%Rsp),%I0x%x\n" | |
1162 | : "\tmoveml %Rsp@,%I0x%x\n"), | |
e6d98cb0 | 1163 | current_frame.reg_mask); |
860c4900 BI |
1164 | else |
1165 | { | |
e6d98cb0 BI |
1166 | if (MOTOROLA) |
1167 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1168 | current_frame.offset + fsize, | |
a0a7fbc9 | 1169 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1170 | current_frame.reg_mask); |
1171 | else | |
1172 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1173 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1174 | current_frame.offset + fsize, |
1175 | current_frame.reg_mask); | |
860c4900 BI |
1176 | } |
1177 | } | |
1178 | else /* !TARGET_COLDFIRE */ | |
79e68feb | 1179 | { |
860c4900 BI |
1180 | if (big) |
1181 | { | |
e6d98cb0 BI |
1182 | if (MOTOROLA) |
1183 | asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n", | |
1184 | current_frame.offset + fsize, | |
a0a7fbc9 | 1185 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1186 | current_frame.reg_mask); |
1187 | else | |
1188 | asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1189 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1190 | current_frame.offset + fsize, |
1191 | current_frame.reg_mask); | |
860c4900 BI |
1192 | } |
1193 | else if (restore_from_sp) | |
1194 | { | |
a0a7fbc9 AS |
1195 | asm_fprintf (stream, (MOTOROLA |
1196 | ? "\tmovm.l (%Rsp)+,%I0x%x\n" | |
1197 | : "\tmoveml %Rsp@+,%I0x%x\n"), | |
3d74bc09 | 1198 | current_frame.reg_mask); |
860c4900 BI |
1199 | } |
1200 | else | |
1201 | { | |
e6d98cb0 BI |
1202 | if (MOTOROLA) |
1203 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1204 | current_frame.offset + fsize, | |
a0a7fbc9 | 1205 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1206 | current_frame.reg_mask); |
1207 | else | |
1208 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1209 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1210 | current_frame.offset + fsize, |
1211 | current_frame.reg_mask); | |
860c4900 | 1212 | } |
79e68feb RS |
1213 | } |
1214 | } | |
3d74bc09 | 1215 | if (current_frame.fpu_rev_mask) |
79e68feb RS |
1216 | { |
1217 | if (big) | |
1218 | { | |
dcc21c4c PB |
1219 | if (TARGET_COLDFIRE) |
1220 | { | |
1221 | if (current_frame.reg_no) | |
1222 | asm_fprintf (stream, MOTOROLA ? | |
1223 | "\tfmovem.d %d(%Ra1),%I0x%x\n" : | |
1224 | "\tfmovmd (%d,%Ra1),%I0x%x\n", | |
1225 | current_frame.reg_no * 4, | |
1226 | current_frame.fpu_rev_mask); | |
1227 | else | |
1228 | asm_fprintf (stream, MOTOROLA ? | |
1229 | "\tfmovem.d (%Ra1),%I0x%x\n" : | |
1230 | "\tfmovmd (%Ra1),%I0x%x\n", | |
1231 | current_frame.fpu_rev_mask); | |
1232 | } | |
1233 | else if (MOTOROLA) | |
e6d98cb0 BI |
1234 | asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n", |
1235 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1236 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1237 | current_frame.fpu_rev_mask); |
1238 | else | |
1239 | asm_fprintf (stream, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1240 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1241 | current_frame.foffset + fsize, |
1242 | current_frame.fpu_rev_mask); | |
79e68feb | 1243 | } |
6910dd70 | 1244 | else if (restore_from_sp) |
79e68feb | 1245 | { |
dcc21c4c PB |
1246 | if (TARGET_COLDFIRE) |
1247 | { | |
1248 | int offset; | |
1249 | ||
884b74f0 AS |
1250 | /* Stack already has registers in it. Find the offset from |
1251 | the bottom of stack to where the FP registers go. */ | |
dcc21c4c PB |
1252 | if (current_frame.reg_no <= 2) |
1253 | offset = 0; | |
1254 | else | |
1255 | offset = current_frame.reg_no * 4; | |
1256 | if (offset) | |
884b74f0 AS |
1257 | asm_fprintf (stream, |
1258 | "\tfmovem %Rsp@(%d), %I0x%x\n", | |
dcc21c4c PB |
1259 | offset, current_frame.fpu_rev_mask); |
1260 | else | |
884b74f0 | 1261 | asm_fprintf (stream, |
dcc21c4c PB |
1262 | "\tfmovem %Rsp@, %I0x%x\n", |
1263 | current_frame.fpu_rev_mask); | |
1264 | } | |
884b74f0 AS |
1265 | else |
1266 | asm_fprintf (stream, MOTOROLA ? | |
1267 | "\tfmovm (%Rsp)+,%I0x%x\n" : | |
1268 | "\tfmovem %Rsp@+,%I0x%x\n", | |
1269 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1270 | } |
1271 | else | |
1272 | { | |
dcc21c4c | 1273 | if (MOTOROLA && !TARGET_COLDFIRE) |
e6d98cb0 BI |
1274 | asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n", |
1275 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1276 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1277 | current_frame.fpu_rev_mask); |
1278 | else | |
1279 | asm_fprintf (stream, "\tfmovem %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1280 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1281 | current_frame.foffset + fsize, |
1282 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1283 | } |
1284 | } | |
79e68feb | 1285 | if (frame_pointer_needed) |
a0a7fbc9 | 1286 | fprintf (stream, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM)); |
860c4900 | 1287 | else if (fsize_with_regs) |
79e68feb | 1288 | { |
860c4900 | 1289 | if (fsize_with_regs <= 8) |
79e68feb | 1290 | { |
9425fb04 | 1291 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
1292 | asm_fprintf (stream, "\taddq" ASM_DOT "w %I%wd,%Rsp\n", |
1293 | fsize_with_regs); | |
1294 | else | |
1295 | asm_fprintf (stream, "\taddq" ASM_DOT "l %I%wd,%Rsp\n", | |
1296 | fsize_with_regs); | |
7bc88d49 | 1297 | } |
fe95f2f7 | 1298 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
7bc88d49 RK |
1299 | { |
1300 | /* On the CPU32 it is faster to use two addqw instructions to | |
7a1929e1 | 1301 | add a small integer (8 < N <= 16) to a register. */ |
a0a7fbc9 AS |
1302 | asm_fprintf (stream, |
1303 | "\taddq" ASM_DOT "w %I8,%Rsp\n" | |
1304 | "\taddq" ASM_DOT "w %I%wd,%Rsp\n", | |
860c4900 | 1305 | fsize_with_regs - 8); |
7bc88d49 | 1306 | } |
860c4900 | 1307 | else if (fsize_with_regs < 0x8000) |
7bc88d49 | 1308 | { |
fe95f2f7 | 1309 | if (TUNE_68040) |
e6d98cb0 BI |
1310 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", |
1311 | fsize_with_regs); | |
7bc88d49 | 1312 | else |
a0a7fbc9 AS |
1313 | asm_fprintf (stream, (MOTOROLA |
1314 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
1315 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 1316 | fsize_with_regs); |
79e68feb RS |
1317 | } |
1318 | else | |
e6d98cb0 | 1319 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); |
79e68feb | 1320 | } |
2cff4a6e | 1321 | if (current_function_calls_eh_return) |
a0a7fbc9 | 1322 | asm_fprintf (stream, "\tadd" ASM_DOT "l %Ra0,%Rsp\n"); |
3d74bc09 | 1323 | if (m68k_interrupt_function_p (current_function_decl)) |
48ed72a4 PB |
1324 | fprintf (stream, "\trte\n"); |
1325 | else if (current_function_pops_args) | |
1f85a612 | 1326 | asm_fprintf (stream, "\trtd %I%d\n", current_function_pops_args); |
79e68feb RS |
1327 | else |
1328 | fprintf (stream, "\trts\n"); | |
1329 | } | |
1330 | \f | |
8a4a2253 | 1331 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1332 | instruction. |
1333 | ||
1334 | Note it rejects floating point comparison operators. | |
1335 | (In the future we could use Fdbcc). | |
1336 | ||
1337 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1338 | ||
1339 | int | |
41b6a5e2 | 1340 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1341 | { |
64a184e9 RS |
1342 | switch (GET_CODE (x)) |
1343 | { | |
64a184e9 RS |
1344 | case EQ: case NE: case GTU: case LTU: |
1345 | case GEU: case LEU: | |
1346 | return 1; | |
1347 | ||
1348 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1349 | conservative */ | |
1350 | case GT: case LT: case GE: case LE: | |
1351 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1352 | default: | |
1353 | return 0; | |
1354 | } | |
1355 | } | |
1356 | ||
a0ab749a | 1357 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1358 | int |
8a4a2253 | 1359 | flags_in_68881 (void) |
6a0f85e3 TG |
1360 | { |
1361 | /* We could add support for these in the future */ | |
1362 | return cc_status.flags & CC_IN_68881; | |
1363 | } | |
1364 | ||
29ca003a RS |
1365 | /* Convert X to a legitimate function call memory reference and return the |
1366 | result. */ | |
a2ef3db7 | 1367 | |
29ca003a RS |
1368 | rtx |
1369 | m68k_legitimize_call_address (rtx x) | |
1370 | { | |
1371 | gcc_assert (MEM_P (x)); | |
1372 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1373 | return x; | |
1374 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1375 | } |
1376 | ||
64a184e9 RS |
1377 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1378 | floating point version of this sequence (Fdbcc). We also | |
1379 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1380 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1381 | kick those out before we get here. */ | |
64a184e9 | 1382 | |
1d8eaa6b | 1383 | void |
8a4a2253 | 1384 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1385 | { |
64a184e9 RS |
1386 | switch (GET_CODE (operands[3])) |
1387 | { | |
1388 | case EQ: | |
a0a7fbc9 AS |
1389 | output_asm_insn (MOTOROLA |
1390 | ? "dbeq %0,%l1\n\tjbeq %l2" | |
1391 | : "dbeq %0,%l1\n\tjeq %l2", | |
e6d98cb0 BI |
1392 | operands); |
1393 | break; | |
64a184e9 RS |
1394 | |
1395 | case NE: | |
a0a7fbc9 AS |
1396 | output_asm_insn (MOTOROLA |
1397 | ? "dbne %0,%l1\n\tjbne %l2" | |
1398 | : "dbne %0,%l1\n\tjne %l2", | |
e6d98cb0 BI |
1399 | operands); |
1400 | break; | |
64a184e9 RS |
1401 | |
1402 | case GT: | |
a0a7fbc9 AS |
1403 | output_asm_insn (MOTOROLA |
1404 | ? "dbgt %0,%l1\n\tjbgt %l2" | |
1405 | : "dbgt %0,%l1\n\tjgt %l2", | |
e6d98cb0 BI |
1406 | operands); |
1407 | break; | |
64a184e9 RS |
1408 | |
1409 | case GTU: | |
a0a7fbc9 AS |
1410 | output_asm_insn (MOTOROLA |
1411 | ? "dbhi %0,%l1\n\tjbhi %l2" | |
1412 | : "dbhi %0,%l1\n\tjhi %l2", | |
e6d98cb0 BI |
1413 | operands); |
1414 | break; | |
64a184e9 RS |
1415 | |
1416 | case LT: | |
a0a7fbc9 AS |
1417 | output_asm_insn (MOTOROLA |
1418 | ? "dblt %0,%l1\n\tjblt %l2" | |
1419 | : "dblt %0,%l1\n\tjlt %l2", | |
e6d98cb0 BI |
1420 | operands); |
1421 | break; | |
64a184e9 RS |
1422 | |
1423 | case LTU: | |
a0a7fbc9 AS |
1424 | output_asm_insn (MOTOROLA |
1425 | ? "dbcs %0,%l1\n\tjbcs %l2" | |
1426 | : "dbcs %0,%l1\n\tjcs %l2", | |
e6d98cb0 BI |
1427 | operands); |
1428 | break; | |
64a184e9 RS |
1429 | |
1430 | case GE: | |
a0a7fbc9 AS |
1431 | output_asm_insn (MOTOROLA |
1432 | ? "dbge %0,%l1\n\tjbge %l2" | |
1433 | : "dbge %0,%l1\n\tjge %l2", | |
e6d98cb0 BI |
1434 | operands); |
1435 | break; | |
64a184e9 RS |
1436 | |
1437 | case GEU: | |
a0a7fbc9 AS |
1438 | output_asm_insn (MOTOROLA |
1439 | ? "dbcc %0,%l1\n\tjbcc %l2" | |
1440 | : "dbcc %0,%l1\n\tjcc %l2", | |
e6d98cb0 BI |
1441 | operands); |
1442 | break; | |
64a184e9 RS |
1443 | |
1444 | case LE: | |
a0a7fbc9 AS |
1445 | output_asm_insn (MOTOROLA |
1446 | ? "dble %0,%l1\n\tjble %l2" | |
1447 | : "dble %0,%l1\n\tjle %l2", | |
e6d98cb0 BI |
1448 | operands); |
1449 | break; | |
64a184e9 RS |
1450 | |
1451 | case LEU: | |
a0a7fbc9 AS |
1452 | output_asm_insn (MOTOROLA |
1453 | ? "dbls %0,%l1\n\tjbls %l2" | |
1454 | : "dbls %0,%l1\n\tjls %l2", | |
e6d98cb0 BI |
1455 | operands); |
1456 | break; | |
64a184e9 RS |
1457 | |
1458 | default: | |
4761e388 | 1459 | gcc_unreachable (); |
64a184e9 RS |
1460 | } |
1461 | ||
1462 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1463 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1464 | switch (GET_MODE (operands[0])) |
1465 | { | |
1466 | case SImode: | |
a0a7fbc9 AS |
1467 | output_asm_insn (MOTOROLA |
1468 | ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" | |
1469 | : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1470 | operands); |
64a184e9 RS |
1471 | break; |
1472 | ||
1473 | case HImode: | |
1474 | break; | |
1475 | ||
1476 | default: | |
4761e388 | 1477 | gcc_unreachable (); |
64a184e9 RS |
1478 | } |
1479 | } | |
1480 | ||
5505f548 | 1481 | const char * |
4761e388 | 1482 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1483 | { |
1484 | rtx loperands[7]; | |
d9832fd2 | 1485 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1486 | |
f710504c | 1487 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1488 | CC_STATUS_INIT; |
1489 | ||
d9832fd2 RK |
1490 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1491 | below. Swap the operands and change the op if these requirements | |
1492 | are not fulfilled. */ | |
1493 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1494 | { | |
1495 | rtx tmp = operand1; | |
1496 | ||
1497 | operand1 = operand2; | |
1498 | operand2 = tmp; | |
1499 | op_code = swap_condition (op_code); | |
1500 | } | |
c59c3b1c RK |
1501 | loperands[0] = operand1; |
1502 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1503 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1504 | else |
b72f00af | 1505 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1506 | if (operand2 != const0_rtx) |
1507 | { | |
1508 | loperands[2] = operand2; | |
1509 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1510 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1511 | else |
b72f00af | 1512 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1513 | } |
428511bb | 1514 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1515 | if (operand2 != const0_rtx) |
4a8c52e0 | 1516 | { |
a0a7fbc9 AS |
1517 | output_asm_insn (MOTOROLA |
1518 | ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" | |
1519 | : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1520 | loperands); | |
4a8c52e0 | 1521 | } |
392582fa | 1522 | else |
4a8c52e0 | 1523 | { |
9425fb04 | 1524 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1525 | output_asm_insn ("tst%.l %0", loperands); |
1526 | else | |
a0a7fbc9 | 1527 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1528 | |
e6d98cb0 | 1529 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1530 | |
9425fb04 | 1531 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1532 | output_asm_insn ("tst%.l %1", loperands); |
1533 | else | |
3b4b85c9 | 1534 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1535 | } |
1536 | ||
c59c3b1c | 1537 | loperands[5] = dest; |
3b4b85c9 | 1538 | |
d9832fd2 | 1539 | switch (op_code) |
c59c3b1c RK |
1540 | { |
1541 | case EQ: | |
4977bab6 | 1542 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1543 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1544 | output_asm_insn ("seq %5", loperands); |
1545 | break; | |
1546 | ||
1547 | case NE: | |
4977bab6 | 1548 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1549 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1550 | output_asm_insn ("sne %5", loperands); |
1551 | break; | |
1552 | ||
1553 | case GT: | |
428511bb | 1554 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1555 | output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6", |
e6d98cb0 | 1556 | loperands); |
4977bab6 | 1557 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1558 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1559 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1560 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1561 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1562 | break; |
1563 | ||
1564 | case GTU: | |
4977bab6 | 1565 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1566 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1567 | output_asm_insn ("shi %5", loperands); |
1568 | break; | |
1569 | ||
1570 | case LT: | |
428511bb | 1571 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1572 | output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6", |
e6d98cb0 | 1573 | loperands); |
4977bab6 | 1574 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1575 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1576 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1577 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1578 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1579 | break; |
1580 | ||
1581 | case LTU: | |
4977bab6 | 1582 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1583 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1584 | output_asm_insn ("scs %5", loperands); |
1585 | break; | |
1586 | ||
1587 | case GE: | |
428511bb | 1588 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 AS |
1589 | output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6", |
1590 | loperands); | |
4977bab6 | 1591 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1592 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1593 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1594 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1595 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1596 | break; |
1597 | ||
1598 | case GEU: | |
4977bab6 | 1599 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1600 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1601 | output_asm_insn ("scc %5", loperands); |
1602 | break; | |
1603 | ||
1604 | case LE: | |
428511bb | 1605 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1606 | output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6", |
e6d98cb0 | 1607 | loperands); |
4977bab6 | 1608 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1609 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1610 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1611 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1612 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1613 | break; |
1614 | ||
1615 | case LEU: | |
4977bab6 | 1616 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1617 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1618 | output_asm_insn ("sls %5", loperands); |
1619 | break; | |
1620 | ||
1621 | default: | |
4761e388 | 1622 | gcc_unreachable (); |
c59c3b1c RK |
1623 | } |
1624 | return ""; | |
1625 | } | |
1626 | ||
5505f548 | 1627 | const char * |
8a4a2253 | 1628 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1629 | { |
1630 | operands[0] = countop; | |
1631 | operands[1] = dataop; | |
1632 | ||
1633 | if (GET_CODE (countop) == CONST_INT) | |
1634 | { | |
1635 | register int count = INTVAL (countop); | |
1636 | /* If COUNT is bigger than size of storage unit in use, | |
1637 | advance to the containing unit of same size. */ | |
1638 | if (count > signpos) | |
1639 | { | |
1640 | int offset = (count & ~signpos) / 8; | |
1641 | count = count & signpos; | |
b72f00af | 1642 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1643 | } |
1644 | if (count == signpos) | |
1645 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1646 | else | |
1647 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1648 | ||
1649 | /* These three statements used to use next_insns_test_no... | |
1650 | but it appears that this should do the same job. */ | |
1651 | if (count == 31 | |
1652 | && next_insn_tests_no_inequality (insn)) | |
1653 | return "tst%.l %1"; | |
1654 | if (count == 15 | |
1655 | && next_insn_tests_no_inequality (insn)) | |
1656 | return "tst%.w %1"; | |
1657 | if (count == 7 | |
1658 | && next_insn_tests_no_inequality (insn)) | |
1659 | return "tst%.b %1"; | |
1660 | ||
1661 | cc_status.flags = CC_NOT_NEGATIVE; | |
1662 | } | |
1663 | return "btst %0,%1"; | |
1664 | } | |
79e68feb RS |
1665 | \f |
1666 | /* Legitimize PIC addresses. If the address is already | |
1667 | position-independent, we return ORIG. Newly generated | |
1668 | position-independent addresses go to REG. If we need more | |
1669 | than one register, we lose. | |
1670 | ||
1671 | An address is legitimized by making an indirect reference | |
1672 | through the Global Offset Table with the name of the symbol | |
1673 | used as an offset. | |
1674 | ||
1675 | The assembler and linker are responsible for placing the | |
1676 | address of the symbol in the GOT. The function prologue | |
1677 | is responsible for initializing a5 to the starting address | |
1678 | of the GOT. | |
1679 | ||
1680 | The assembler is also responsible for translating a symbol name | |
1681 | into a constant displacement from the start of the GOT. | |
1682 | ||
1683 | A quick example may make things a little clearer: | |
1684 | ||
1685 | When not generating PIC code to store the value 12345 into _foo | |
1686 | we would generate the following code: | |
1687 | ||
1688 | movel #12345, _foo | |
1689 | ||
1690 | When generating PIC two transformations are made. First, the compiler | |
1691 | loads the address of foo into a register. So the first transformation makes: | |
1692 | ||
1693 | lea _foo, a0 | |
1694 | movel #12345, a0@ | |
1695 | ||
1696 | The code in movsi will intercept the lea instruction and call this | |
1697 | routine which will transform the instructions into: | |
1698 | ||
1699 | movel a5@(_foo:w), a0 | |
1700 | movel #12345, a0@ | |
1701 | ||
1702 | ||
1703 | That (in a nutshell) is how *all* symbol and label references are | |
1704 | handled. */ | |
1705 | ||
1706 | rtx | |
8a4a2253 BI |
1707 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1708 | rtx reg) | |
79e68feb RS |
1709 | { |
1710 | rtx pic_ref = orig; | |
1711 | ||
1712 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1713 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1714 | { | |
4761e388 | 1715 | gcc_assert (reg); |
79e68feb | 1716 | |
1d8eaa6b AS |
1717 | pic_ref = gen_rtx_MEM (Pmode, |
1718 | gen_rtx_PLUS (Pmode, | |
1719 | pic_offset_table_rtx, orig)); | |
79e68feb | 1720 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 1721 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
1722 | emit_move_insn (reg, pic_ref); |
1723 | return reg; | |
1724 | } | |
1725 | else if (GET_CODE (orig) == CONST) | |
1726 | { | |
1d8eaa6b | 1727 | rtx base; |
79e68feb | 1728 | |
b2e08ed4 | 1729 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
1730 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
1731 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1732 | return orig; | |
1733 | ||
4761e388 | 1734 | gcc_assert (reg); |
79e68feb RS |
1735 | |
1736 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
1737 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
1738 | ||
1739 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
1740 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
1741 | base == reg ? 0 : reg); | |
79e68feb RS |
1742 | |
1743 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 1744 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 1745 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
1746 | /* Likewise, should we set special REG_NOTEs here? */ |
1747 | } | |
1748 | return pic_ref; | |
1749 | } | |
1750 | ||
1751 | \f | |
28bad6d1 | 1752 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 1753 | |
a0a7fbc9 | 1754 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 1755 | |
bda2a571 RS |
1756 | /* Return the type of move that should be used for integer I. */ |
1757 | ||
5505f548 | 1758 | static CONST_METHOD |
bda2a571 | 1759 | const_method (HOST_WIDE_INT i) |
0ce6f9fb | 1760 | { |
0ce6f9fb RK |
1761 | unsigned u; |
1762 | ||
6910dd70 | 1763 | if (USE_MOVQ (i)) |
0ce6f9fb | 1764 | return MOVQ; |
24092242 | 1765 | |
c16eadc7 | 1766 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 1767 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 1768 | if (!TARGET_COLDFIRE) |
24092242 RK |
1769 | { |
1770 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 1771 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
1772 | if (USE_MOVQ (i ^ 0xff)) |
1773 | return NOTB; | |
1774 | /* Likewise, try with not.w */ | |
1775 | if (USE_MOVQ (i ^ 0xffff)) | |
1776 | return NOTW; | |
1777 | /* This is the only value where neg.w is useful */ | |
1778 | if (i == -65408) | |
1779 | return NEGW; | |
24092242 | 1780 | } |
28bad6d1 | 1781 | |
5e04daf3 PB |
1782 | /* Try also with swap. */ |
1783 | u = i; | |
1784 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
1785 | return SWAP; | |
1786 | ||
986e74d5 | 1787 | if (TARGET_ISAB) |
28bad6d1 | 1788 | { |
72edf146 | 1789 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
1790 | if (i >= 0 && i <= 65535) |
1791 | return MVZ; | |
1792 | if (i >= -32768 && i <= 32767) | |
1793 | return MVS; | |
1794 | } | |
1795 | ||
0ce6f9fb RK |
1796 | /* Otherwise, use move.l */ |
1797 | return MOVL; | |
1798 | } | |
1799 | ||
bda2a571 RS |
1800 | /* Return the cost of moving constant I into a data register. */ |
1801 | ||
3c50106f | 1802 | static int |
bda2a571 | 1803 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 1804 | { |
bda2a571 | 1805 | switch (const_method (i)) |
0ce6f9fb | 1806 | { |
a0a7fbc9 AS |
1807 | case MOVQ: |
1808 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
1809 | return 0; | |
1810 | case MVZ: | |
1811 | case MVS: | |
1812 | case NOTB: | |
1813 | case NOTW: | |
1814 | case NEGW: | |
1815 | case SWAP: | |
1816 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
1817 | return 1; | |
1818 | case MOVL: | |
1819 | return 2; | |
1820 | default: | |
1821 | gcc_unreachable (); | |
0ce6f9fb RK |
1822 | } |
1823 | } | |
1824 | ||
3c50106f | 1825 | static bool |
8a4a2253 | 1826 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1827 | { |
1828 | switch (code) | |
1829 | { | |
1830 | case CONST_INT: | |
1831 | /* Constant zero is super cheap due to clr instruction. */ | |
1832 | if (x == const0_rtx) | |
1833 | *total = 0; | |
1834 | else | |
bda2a571 | 1835 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
1836 | return true; |
1837 | ||
1838 | case CONST: | |
1839 | case LABEL_REF: | |
1840 | case SYMBOL_REF: | |
1841 | *total = 3; | |
1842 | return true; | |
1843 | ||
1844 | case CONST_DOUBLE: | |
1845 | /* Make 0.0 cheaper than other floating constants to | |
1846 | encourage creating tstsf and tstdf insns. */ | |
1847 | if (outer_code == COMPARE | |
1848 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
1849 | *total = 4; | |
1850 | else | |
1851 | *total = 5; | |
1852 | return true; | |
1853 | ||
1854 | /* These are vaguely right for a 68020. */ | |
1855 | /* The costs for long multiply have been adjusted to work properly | |
1856 | in synth_mult on the 68020, relative to an average of the time | |
1857 | for add and the time for shift, taking away a little more because | |
1858 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
1859 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
1860 | terms. */ | |
fe95f2f7 JB |
1861 | #define MULL_COST \ |
1862 | (TUNE_68060 ? 2 \ | |
1863 | : TUNE_68040 ? 5 \ | |
1864 | : TUNE_CFV2 ? 10 \ | |
1865 | : TARGET_COLDFIRE ? 3 : 13) | |
1866 | ||
1867 | #define MULW_COST \ | |
1868 | (TUNE_68060 ? 2 \ | |
1869 | : TUNE_68040 ? 3 \ | |
1870 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
1871 | : TARGET_COLDFIRE ? 2 : 8) | |
1872 | ||
1873 | #define DIVW_COST \ | |
1874 | (TARGET_CF_HWDIV ? 11 \ | |
1875 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
1876 | |
1877 | case PLUS: | |
1878 | /* An lea costs about three times as much as a simple add. */ | |
1879 | if (GET_MODE (x) == SImode | |
1880 | && GET_CODE (XEXP (x, 1)) == REG | |
1881 | && GET_CODE (XEXP (x, 0)) == MULT | |
1882 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1883 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1884 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
1885 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
1886 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
1887 | { |
1888 | /* lea an@(dx:l:i),am */ | |
1889 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
1890 | return true; | |
1891 | } | |
3c50106f RH |
1892 | return false; |
1893 | ||
1894 | case ASHIFT: | |
1895 | case ASHIFTRT: | |
1896 | case LSHIFTRT: | |
fe95f2f7 | 1897 | if (TUNE_68060) |
3c50106f RH |
1898 | { |
1899 | *total = COSTS_N_INSNS(1); | |
1900 | return true; | |
1901 | } | |
fe95f2f7 | 1902 | if (TUNE_68000_10) |
3c50106f RH |
1903 | { |
1904 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1905 | { | |
1906 | if (INTVAL (XEXP (x, 1)) < 16) | |
1907 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
1908 | else | |
1909 | /* We're using clrw + swap for these cases. */ | |
1910 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
1911 | } | |
1912 | else | |
a0a7fbc9 | 1913 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
1914 | return true; |
1915 | } | |
1916 | /* A shift by a big integer takes an extra instruction. */ | |
1917 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1918 | && (INTVAL (XEXP (x, 1)) == 16)) | |
1919 | { | |
1920 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
1921 | return true; | |
1922 | } | |
1923 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1924 | && !(INTVAL (XEXP (x, 1)) > 0 | |
1925 | && INTVAL (XEXP (x, 1)) <= 8)) | |
1926 | { | |
eb849993 | 1927 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
1928 | return true; |
1929 | } | |
1930 | return false; | |
1931 | ||
1932 | case MULT: | |
1933 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
1934 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
1935 | && GET_MODE (x) == SImode) | |
1936 | *total = COSTS_N_INSNS (MULW_COST); | |
1937 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1938 | *total = COSTS_N_INSNS (MULW_COST); | |
1939 | else | |
1940 | *total = COSTS_N_INSNS (MULL_COST); | |
1941 | return true; | |
1942 | ||
1943 | case DIV: | |
1944 | case UDIV: | |
1945 | case MOD: | |
1946 | case UMOD: | |
1947 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1948 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
1949 | else if (TARGET_CF_HWDIV) |
1950 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
1951 | else |
1952 | *total = COSTS_N_INSNS (43); /* div.l */ | |
1953 | return true; | |
1954 | ||
1955 | default: | |
1956 | return false; | |
1957 | } | |
1958 | } | |
1959 | ||
88512ba0 | 1960 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
1961 | OPERANDS[0]. */ |
1962 | ||
1963 | static const char * | |
8a4a2253 | 1964 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 1965 | { |
bda2a571 | 1966 | HOST_WIDE_INT i; |
0ce6f9fb RK |
1967 | |
1968 | i = INTVAL (operands[1]); | |
bda2a571 | 1969 | switch (const_method (i)) |
0ce6f9fb | 1970 | { |
28bad6d1 | 1971 | case MVZ: |
28bad6d1 | 1972 | return "mvzw %1,%0"; |
1cbae84f PB |
1973 | case MVS: |
1974 | return "mvsw %1,%0"; | |
a0a7fbc9 | 1975 | case MOVQ: |
0ce6f9fb | 1976 | return "moveq %1,%0"; |
a0a7fbc9 | 1977 | case NOTB: |
66e07510 | 1978 | CC_STATUS_INIT; |
1d8eaa6b | 1979 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 1980 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 1981 | case NOTW: |
66e07510 | 1982 | CC_STATUS_INIT; |
1d8eaa6b | 1983 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 1984 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 1985 | case NEGW: |
66e07510 | 1986 | CC_STATUS_INIT; |
3b4b85c9 | 1987 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 1988 | case SWAP: |
0ce6f9fb RK |
1989 | { |
1990 | unsigned u = i; | |
1991 | ||
1d8eaa6b | 1992 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 1993 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 1994 | } |
a0a7fbc9 | 1995 | case MOVL: |
bda2a571 | 1996 | return "move%.l %1,%0"; |
a0a7fbc9 | 1997 | default: |
bda2a571 | 1998 | gcc_unreachable (); |
0ce6f9fb RK |
1999 | } |
2000 | } | |
2001 | ||
bda2a571 | 2002 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 2003 | |
bda2a571 RS |
2004 | bool |
2005 | valid_mov3q_const (HOST_WIDE_INT i) | |
2006 | { | |
2007 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
2008 | } |
2009 | ||
bda2a571 RS |
2010 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
2011 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 2012 | |
bda2a571 | 2013 | static const char * |
8a4a2253 | 2014 | output_move_simode_const (rtx *operands) |
02ed0c07 | 2015 | { |
bda2a571 RS |
2016 | rtx dest; |
2017 | HOST_WIDE_INT src; | |
2018 | ||
2019 | dest = operands[0]; | |
2020 | src = INTVAL (operands[1]); | |
2021 | if (src == 0 | |
2022 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
2023 | /* clr insns on 68000 read before writing. */ |
2024 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 2025 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 2026 | return "clr%.l %0"; |
bda2a571 | 2027 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 2028 | return "mov3q%.l %1,%0"; |
bda2a571 | 2029 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 2030 | return "sub%.l %0,%0"; |
bda2a571 | 2031 | else if (DATA_REG_P (dest)) |
02ed0c07 | 2032 | return output_move_const_into_data_reg (operands); |
bda2a571 | 2033 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 2034 | { |
bda2a571 | 2035 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2036 | return "mov3q%.l %1,%0"; |
2037 | return "move%.w %1,%0"; | |
2038 | } | |
bda2a571 RS |
2039 | else if (MEM_P (dest) |
2040 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2041 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
2042 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 2043 | { |
bda2a571 | 2044 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2045 | return "mov3q%.l %1,%-"; |
2046 | return "pea %a1"; | |
2047 | } | |
02ed0c07 RK |
2048 | return "move%.l %1,%0"; |
2049 | } | |
2050 | ||
5505f548 | 2051 | const char * |
8a4a2253 | 2052 | output_move_simode (rtx *operands) |
f4e80198 RK |
2053 | { |
2054 | if (GET_CODE (operands[1]) == CONST_INT) | |
2055 | return output_move_simode_const (operands); | |
2056 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2057 | || GET_CODE (operands[1]) == CONST) | |
2058 | && push_operand (operands[0], SImode)) | |
2059 | return "pea %a1"; | |
2060 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2061 | || GET_CODE (operands[1]) == CONST) | |
2062 | && ADDRESS_REG_P (operands[0])) | |
2063 | return "lea %a1,%0"; | |
2064 | return "move%.l %1,%0"; | |
2065 | } | |
2066 | ||
5505f548 | 2067 | const char * |
8a4a2253 | 2068 | output_move_himode (rtx *operands) |
f4e80198 RK |
2069 | { |
2070 | if (GET_CODE (operands[1]) == CONST_INT) | |
2071 | { | |
2072 | if (operands[1] == const0_rtx | |
2073 | && (DATA_REG_P (operands[0]) | |
2074 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2075 | /* clr insns on 68000 read before writing. */ |
2076 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2077 | || !(GET_CODE (operands[0]) == MEM |
2078 | && MEM_VOLATILE_P (operands[0])))) | |
2079 | return "clr%.w %0"; | |
38198304 AS |
2080 | else if (operands[1] == const0_rtx |
2081 | && ADDRESS_REG_P (operands[0])) | |
2082 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2083 | else if (DATA_REG_P (operands[0]) |
2084 | && INTVAL (operands[1]) < 128 | |
2085 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2086 | return "moveq %1,%0"; |
f4e80198 RK |
2087 | else if (INTVAL (operands[1]) < 0x8000 |
2088 | && INTVAL (operands[1]) >= -0x8000) | |
2089 | return "move%.w %1,%0"; | |
2090 | } | |
2091 | else if (CONSTANT_P (operands[1])) | |
2092 | return "move%.l %1,%0"; | |
f4e80198 RK |
2093 | /* Recognize the insn before a tablejump, one that refers |
2094 | to a table of offsets. Such an insn will need to refer | |
2095 | to a label on the insn. So output one. Use the label-number | |
2096 | of the table of offsets to generate this label. This code, | |
2097 | and similar code below, assumes that there will be at most one | |
2098 | reference to each table. */ | |
2099 | if (GET_CODE (operands[1]) == MEM | |
2100 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2101 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
2102 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
2103 | { | |
2104 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
2105 | if (MOTOROLA) |
2106 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
2107 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
2108 | else | |
2109 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
a0a7fbc9 | 2110 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); |
f4e80198 | 2111 | } |
f4e80198 RK |
2112 | return "move%.w %1,%0"; |
2113 | } | |
2114 | ||
5505f548 | 2115 | const char * |
8a4a2253 | 2116 | output_move_qimode (rtx *operands) |
f4e80198 | 2117 | { |
102701ff | 2118 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2119 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2120 | |
a0a7fbc9 | 2121 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2122 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2123 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2124 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2125 | && ! ADDRESS_REG_P (operands[1]) | |
2126 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2127 | |
3197c489 | 2128 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2129 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2130 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2131 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2132 | { | |
2133 | if (operands[1] == const0_rtx) | |
2134 | return "clr%.b %0"; | |
9425fb04 | 2135 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2136 | && GET_CODE (operands[1]) == CONST_INT |
2137 | && (INTVAL (operands[1]) & 255) == 255) | |
2138 | { | |
2139 | CC_STATUS_INIT; | |
2140 | return "st %0"; | |
2141 | } | |
2142 | } | |
2143 | if (GET_CODE (operands[1]) == CONST_INT | |
2144 | && DATA_REG_P (operands[0]) | |
2145 | && INTVAL (operands[1]) < 128 | |
2146 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2147 | return "moveq %1,%0"; |
38198304 AS |
2148 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2149 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2150 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2151 | return "move%.l %1,%0"; | |
c16eadc7 | 2152 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2153 | from address registers. */ |
2154 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2155 | return "move%.w %1,%0"; |
2156 | return "move%.b %1,%0"; | |
2157 | } | |
2158 | ||
5505f548 | 2159 | const char * |
8a4a2253 | 2160 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2161 | { |
2162 | if (operands[1] == const0_rtx | |
3197c489 RS |
2163 | /* clr insns on 68000 read before writing. */ |
2164 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2165 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2166 | return "clr%.w %0"; | |
2167 | return "move%.w %1,%0"; | |
2168 | } | |
2169 | ||
5505f548 | 2170 | const char * |
8a4a2253 | 2171 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2172 | { |
2173 | if (operands[1] == const0_rtx | |
3197c489 RS |
2174 | /* clr insns on 68000 read before writing. */ |
2175 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2176 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2177 | return "clr%.b %0"; | |
2178 | return "move%.b %1,%0"; | |
2179 | } | |
2180 | ||
79e68feb RS |
2181 | /* Return the best assembler insn template |
2182 | for moving operands[1] into operands[0] as a fullword. */ | |
2183 | ||
5505f548 | 2184 | static const char * |
8a4a2253 | 2185 | singlemove_string (rtx *operands) |
79e68feb | 2186 | { |
02ed0c07 RK |
2187 | if (GET_CODE (operands[1]) == CONST_INT) |
2188 | return output_move_simode_const (operands); | |
2189 | return "move%.l %1,%0"; | |
79e68feb RS |
2190 | } |
2191 | ||
2505bc97 | 2192 | |
79e68feb RS |
2193 | /* Output assembler code to perform a doubleword move insn |
2194 | with operands OPERANDS. */ | |
2195 | ||
5505f548 | 2196 | const char * |
8a4a2253 | 2197 | output_move_double (rtx *operands) |
79e68feb | 2198 | { |
2505bc97 RS |
2199 | enum |
2200 | { | |
2201 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2202 | } optype0, optype1; | |
79e68feb | 2203 | rtx latehalf[2]; |
2505bc97 | 2204 | rtx middlehalf[2]; |
7f98eeb6 | 2205 | rtx xops[2]; |
79e68feb | 2206 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2207 | int dest_overlapped_low = 0; |
184916bc | 2208 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2209 | |
2210 | middlehalf[0] = 0; | |
2211 | middlehalf[1] = 0; | |
79e68feb RS |
2212 | |
2213 | /* First classify both operands. */ | |
2214 | ||
2215 | if (REG_P (operands[0])) | |
2216 | optype0 = REGOP; | |
2217 | else if (offsettable_memref_p (operands[0])) | |
2218 | optype0 = OFFSOP; | |
2219 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2220 | optype0 = POPOP; | |
2221 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2222 | optype0 = PUSHOP; | |
2223 | else if (GET_CODE (operands[0]) == MEM) | |
2224 | optype0 = MEMOP; | |
2225 | else | |
2226 | optype0 = RNDOP; | |
2227 | ||
2228 | if (REG_P (operands[1])) | |
2229 | optype1 = REGOP; | |
2230 | else if (CONSTANT_P (operands[1])) | |
2231 | optype1 = CNSTOP; | |
2232 | else if (offsettable_memref_p (operands[1])) | |
2233 | optype1 = OFFSOP; | |
2234 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2235 | optype1 = POPOP; | |
2236 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2237 | optype1 = PUSHOP; | |
2238 | else if (GET_CODE (operands[1]) == MEM) | |
2239 | optype1 = MEMOP; | |
2240 | else | |
2241 | optype1 = RNDOP; | |
2242 | ||
4761e388 NS |
2243 | /* Check for the cases that the operand constraints are not supposed |
2244 | to allow to happen. Generating code for these cases is | |
2245 | painful. */ | |
2246 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2247 | |
2248 | /* If one operand is decrementing and one is incrementing | |
2249 | decrement the former register explicitly | |
2250 | and change that operand into ordinary indexing. */ | |
2251 | ||
2252 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2253 | { | |
2254 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 2255 | if (size == 12) |
3b4b85c9 | 2256 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 2257 | else |
3b4b85c9 | 2258 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 2259 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2260 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2261 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2262 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2263 | else |
1d8eaa6b | 2264 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2265 | optype0 = OFFSOP; |
2266 | } | |
2267 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2268 | { | |
2269 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 2270 | if (size == 12) |
3b4b85c9 | 2271 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 2272 | else |
3b4b85c9 | 2273 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 2274 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2275 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2276 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2277 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2278 | else |
1d8eaa6b | 2279 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2280 | optype1 = OFFSOP; |
2281 | } | |
2282 | ||
2283 | /* If an operand is an unoffsettable memory ref, find a register | |
2284 | we can increment temporarily to make it refer to the second word. */ | |
2285 | ||
2286 | if (optype0 == MEMOP) | |
2287 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2288 | ||
2289 | if (optype1 == MEMOP) | |
2290 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2291 | ||
2292 | /* Ok, we can do one word at a time. | |
2293 | Normally we do the low-numbered word first, | |
2294 | but if either operand is autodecrementing then we | |
2295 | do the high-numbered word first. | |
2296 | ||
2297 | In either case, set up in LATEHALF the operands to use | |
2298 | for the high-numbered word and in some cases alter the | |
2299 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2300 | ||
2505bc97 RS |
2301 | if (size == 12) |
2302 | { | |
2303 | if (optype0 == REGOP) | |
2304 | { | |
1d8eaa6b AS |
2305 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2306 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2307 | } |
2308 | else if (optype0 == OFFSOP) | |
2309 | { | |
b72f00af RK |
2310 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2311 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2312 | } |
2313 | else | |
2314 | { | |
2315 | middlehalf[0] = operands[0]; | |
2316 | latehalf[0] = operands[0]; | |
2317 | } | |
2318 | ||
2319 | if (optype1 == REGOP) | |
2320 | { | |
1d8eaa6b AS |
2321 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2322 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2323 | } |
2324 | else if (optype1 == OFFSOP) | |
2325 | { | |
b72f00af RK |
2326 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2327 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2328 | } |
2329 | else if (optype1 == CNSTOP) | |
2330 | { | |
2331 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2332 | { | |
2333 | REAL_VALUE_TYPE r; | |
2334 | long l[3]; | |
2335 | ||
2336 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2337 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2338 | operands[1] = GEN_INT (l[0]); | |
2339 | middlehalf[1] = GEN_INT (l[1]); | |
2340 | latehalf[1] = GEN_INT (l[2]); | |
2341 | } | |
4761e388 | 2342 | else |
2505bc97 | 2343 | { |
4761e388 NS |
2344 | /* No non-CONST_DOUBLE constant should ever appear |
2345 | here. */ | |
2346 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2347 | } |
2348 | } | |
2349 | else | |
2350 | { | |
2351 | middlehalf[1] = operands[1]; | |
2352 | latehalf[1] = operands[1]; | |
2353 | } | |
2354 | } | |
79e68feb | 2355 | else |
2505bc97 RS |
2356 | /* size is not 12: */ |
2357 | { | |
2358 | if (optype0 == REGOP) | |
1d8eaa6b | 2359 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2360 | else if (optype0 == OFFSOP) |
b72f00af | 2361 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2362 | else |
2363 | latehalf[0] = operands[0]; | |
2364 | ||
2365 | if (optype1 == REGOP) | |
1d8eaa6b | 2366 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2367 | else if (optype1 == OFFSOP) |
b72f00af | 2368 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2369 | else if (optype1 == CNSTOP) |
2370 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2371 | else | |
2372 | latehalf[1] = operands[1]; | |
2373 | } | |
79e68feb RS |
2374 | |
2375 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2376 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2377 | for the low word as well, to compensate for the first decrement of sp. */ | |
2378 | if (optype0 == PUSHOP | |
2379 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2380 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2381 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2382 | |
7f98eeb6 RS |
2383 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2384 | if the upper part of reg N does not appear in the MEM, arrange to | |
2385 | emit the move late-half first. Otherwise, compute the MEM address | |
2386 | into the upper part of N and use that as a pointer to the memory | |
2387 | operand. */ | |
2388 | if (optype0 == REGOP | |
2389 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2390 | { | |
1d8eaa6b | 2391 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2392 | |
2393 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2394 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2395 | { |
2396 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2397 | compute the address into latehalf of dest. |
2398 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2399 | compadr: |
7f98eeb6 RS |
2400 | xops[0] = latehalf[0]; |
2401 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2402 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2403 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2404 | { |
1d8eaa6b | 2405 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2406 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2407 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2408 | } |
2409 | else | |
2410 | { | |
1d8eaa6b | 2411 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2412 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2413 | } |
2414 | } | |
2415 | else if (size == 12 | |
d7e8d581 RS |
2416 | && reg_overlap_mentioned_p (middlehalf[0], |
2417 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2418 | { |
3a58400f RS |
2419 | /* Check for two regs used by both source and dest. |
2420 | Note that this can't happen if the dest is all data regs. | |
2421 | It can happen if the dest is d6, d7, a0. | |
2422 | But in that case, latehalf is an addr reg, so | |
2423 | the code at compadr does ok. */ | |
2424 | ||
2425 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2426 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2427 | goto compadr; | |
7f98eeb6 RS |
2428 | |
2429 | /* JRV says this can't happen: */ | |
4761e388 | 2430 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2431 | |
7a1929e1 | 2432 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2433 | output_asm_insn (singlemove_string (operands), operands); |
2434 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2435 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2436 | return ""; | |
2437 | } | |
2fb8a81d | 2438 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2439 | /* If the low half of dest is mentioned in the source memory |
2440 | address, the arrange to emit the move late half first. */ | |
2441 | dest_overlapped_low = 1; | |
2442 | } | |
2443 | ||
79e68feb RS |
2444 | /* If one or both operands autodecrementing, |
2445 | do the two words, high-numbered first. */ | |
2446 | ||
2447 | /* Likewise, the first move would clobber the source of the second one, | |
2448 | do them in the other order. This happens only for registers; | |
2449 | such overlap can't happen in memory unless the user explicitly | |
2450 | sets it up, and that is an undefined circumstance. */ | |
2451 | ||
2452 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2453 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2454 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2455 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2456 | || dest_overlapped_low) | |
79e68feb RS |
2457 | { |
2458 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2459 | if (addreg0) | |
2505bc97 RS |
2460 | { |
2461 | if (size == 12) | |
3b4b85c9 | 2462 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2463 | else |
3b4b85c9 | 2464 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2465 | } |
79e68feb | 2466 | if (addreg1) |
2505bc97 RS |
2467 | { |
2468 | if (size == 12) | |
3b4b85c9 | 2469 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2470 | else |
3b4b85c9 | 2471 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2472 | } |
79e68feb RS |
2473 | |
2474 | /* Do that word. */ | |
2475 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2476 | ||
2477 | /* Undo the adds we just did. */ | |
2478 | if (addreg0) | |
3b4b85c9 | 2479 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2480 | if (addreg1) |
3b4b85c9 | 2481 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2482 | |
2505bc97 RS |
2483 | if (size == 12) |
2484 | { | |
2485 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2486 | if (addreg0) | |
3b4b85c9 | 2487 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2488 | if (addreg1) |
3b4b85c9 | 2489 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2490 | } |
2491 | ||
79e68feb RS |
2492 | /* Do low-numbered word. */ |
2493 | return singlemove_string (operands); | |
2494 | } | |
2495 | ||
2496 | /* Normal case: do the two words, low-numbered first. */ | |
2497 | ||
2498 | output_asm_insn (singlemove_string (operands), operands); | |
2499 | ||
2505bc97 RS |
2500 | /* Do the middle one of the three words for long double */ |
2501 | if (size == 12) | |
2502 | { | |
2503 | if (addreg0) | |
3b4b85c9 | 2504 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2505 | if (addreg1) |
3b4b85c9 | 2506 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2507 | |
2508 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2509 | } | |
2510 | ||
79e68feb RS |
2511 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2512 | if (addreg0) | |
3b4b85c9 | 2513 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2514 | if (addreg1) |
3b4b85c9 | 2515 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2516 | |
2517 | /* Do that word. */ | |
2518 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2519 | ||
2520 | /* Undo the adds we just did. */ | |
2521 | if (addreg0) | |
2505bc97 RS |
2522 | { |
2523 | if (size == 12) | |
3b4b85c9 | 2524 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2525 | else |
3b4b85c9 | 2526 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2527 | } |
79e68feb | 2528 | if (addreg1) |
2505bc97 RS |
2529 | { |
2530 | if (size == 12) | |
3b4b85c9 | 2531 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2532 | else |
3b4b85c9 | 2533 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2534 | } |
79e68feb RS |
2535 | |
2536 | return ""; | |
2537 | } | |
2538 | ||
dcc21c4c PB |
2539 | |
2540 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2541 | new rtx with the correct mode. */ | |
2542 | ||
2543 | static rtx | |
2544 | force_mode (enum machine_mode mode, rtx orig) | |
2545 | { | |
2546 | if (mode == GET_MODE (orig)) | |
2547 | return orig; | |
2548 | ||
2549 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2550 | abort (); | |
2551 | ||
2552 | return gen_rtx_REG (mode, REGNO (orig)); | |
2553 | } | |
2554 | ||
2555 | static int | |
2556 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2557 | { | |
2558 | return reg_renumber && FP_REG_P (op); | |
2559 | } | |
2560 | ||
2561 | /* Emit insns to move operands[1] into operands[0]. | |
2562 | ||
2563 | Return 1 if we have written out everything that needs to be done to | |
2564 | do the move. Otherwise, return 0 and the caller will emit the move | |
2565 | normally. | |
2566 | ||
2567 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2568 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2569 | of SCRATCH_REG in the proper mode. */ |
2570 | ||
2571 | int | |
2572 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2573 | { | |
2574 | register rtx operand0 = operands[0]; | |
2575 | register rtx operand1 = operands[1]; | |
2576 | register rtx tem; | |
2577 | ||
2578 | if (scratch_reg | |
2579 | && reload_in_progress && GET_CODE (operand0) == REG | |
2580 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2581 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2582 | else if (scratch_reg | |
2583 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2584 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2585 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2586 | { | |
2587 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2588 | the code which tracks sets/uses for delete_output_reload. */ | |
2589 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2590 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2591 | SUBREG_BYTE (operand0)); | |
2592 | operand0 = alter_subreg (&temp); | |
2593 | } | |
2594 | ||
2595 | if (scratch_reg | |
2596 | && reload_in_progress && GET_CODE (operand1) == REG | |
2597 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2598 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2599 | else if (scratch_reg | |
2600 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2601 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2602 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2603 | { | |
2604 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2605 | the code which tracks sets/uses for delete_output_reload. */ | |
2606 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2607 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2608 | SUBREG_BYTE (operand1)); | |
2609 | operand1 = alter_subreg (&temp); | |
2610 | } | |
2611 | ||
2612 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2613 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2614 | != XEXP (operand0, 0))) | |
2615 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2616 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2617 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2618 | != XEXP (operand1, 0))) | |
2619 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2620 | ||
2621 | /* Handle secondary reloads for loads/stores of FP registers where | |
2622 | the address is symbolic by using the scratch register */ | |
2623 | if (fp_reg_operand (operand0, mode) | |
2624 | && ((GET_CODE (operand1) == MEM | |
2625 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
2626 | || ((GET_CODE (operand1) == SUBREG | |
2627 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
2628 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
2629 | && scratch_reg) | |
2630 | { | |
2631 | if (GET_CODE (operand1) == SUBREG) | |
2632 | operand1 = XEXP (operand1, 0); | |
2633 | ||
2634 | /* SCRATCH_REG will hold an address. We want | |
2635 | it in SImode regardless of what mode it was originally given | |
2636 | to us. */ | |
2637 | scratch_reg = force_mode (SImode, scratch_reg); | |
2638 | ||
2639 | /* D might not fit in 14 bits either; for such cases load D into | |
2640 | scratch reg. */ | |
2641 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
2642 | { | |
2643 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
2644 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
2645 | Pmode, | |
2646 | XEXP (XEXP (operand1, 0), 0), | |
2647 | scratch_reg)); | |
2648 | } | |
2649 | else | |
2650 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
2651 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
2652 | gen_rtx_MEM (mode, scratch_reg))); | |
2653 | return 1; | |
2654 | } | |
2655 | else if (fp_reg_operand (operand1, mode) | |
2656 | && ((GET_CODE (operand0) == MEM | |
2657 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
2658 | || ((GET_CODE (operand0) == SUBREG) | |
2659 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
2660 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
2661 | && scratch_reg) | |
2662 | { | |
2663 | if (GET_CODE (operand0) == SUBREG) | |
2664 | operand0 = XEXP (operand0, 0); | |
2665 | ||
2666 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2667 | it in SIMODE regardless of what mode it was originally given | |
2668 | to us. */ | |
2669 | scratch_reg = force_mode (SImode, scratch_reg); | |
2670 | ||
2671 | /* D might not fit in 14 bits either; for such cases load D into | |
2672 | scratch reg. */ | |
2673 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
2674 | { | |
2675 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
2676 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
2677 | 0)), | |
2678 | Pmode, | |
2679 | XEXP (XEXP (operand0, 0), | |
2680 | 0), | |
2681 | scratch_reg)); | |
2682 | } | |
2683 | else | |
2684 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
2685 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
2686 | operand1)); | |
2687 | return 1; | |
2688 | } | |
2689 | /* Handle secondary reloads for loads of FP registers from constant | |
2690 | expressions by forcing the constant into memory. | |
2691 | ||
2692 | use scratch_reg to hold the address of the memory location. | |
2693 | ||
2694 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
2695 | NO_REGS when presented with a const_int and an register class | |
2696 | containing only FP registers. Doing so unfortunately creates | |
2697 | more problems than it solves. Fix this for 2.5. */ | |
2698 | else if (fp_reg_operand (operand0, mode) | |
2699 | && CONSTANT_P (operand1) | |
2700 | && scratch_reg) | |
2701 | { | |
2702 | rtx xoperands[2]; | |
2703 | ||
2704 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2705 | it in SIMODE regardless of what mode it was originally given | |
2706 | to us. */ | |
2707 | scratch_reg = force_mode (SImode, scratch_reg); | |
2708 | ||
2709 | /* Force the constant into memory and put the address of the | |
2710 | memory location into scratch_reg. */ | |
2711 | xoperands[0] = scratch_reg; | |
2712 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
2713 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
2714 | ||
2715 | /* Now load the destination register. */ | |
2716 | emit_insn (gen_rtx_SET (mode, operand0, | |
2717 | gen_rtx_MEM (mode, scratch_reg))); | |
2718 | return 1; | |
2719 | } | |
2720 | ||
2721 | /* Now have insn-emit do whatever it normally does. */ | |
2722 | return 0; | |
2723 | } | |
2724 | ||
79e68feb RS |
2725 | /* Return a REG that occurs in ADDR with coefficient 1. |
2726 | ADDR can be effectively incremented by incrementing REG. */ | |
2727 | ||
2728 | static rtx | |
8a4a2253 | 2729 | find_addr_reg (rtx addr) |
79e68feb RS |
2730 | { |
2731 | while (GET_CODE (addr) == PLUS) | |
2732 | { | |
2733 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2734 | addr = XEXP (addr, 0); | |
2735 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2736 | addr = XEXP (addr, 1); | |
2737 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2738 | addr = XEXP (addr, 1); | |
2739 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2740 | addr = XEXP (addr, 0); | |
2741 | else | |
4761e388 | 2742 | gcc_unreachable (); |
79e68feb | 2743 | } |
4761e388 NS |
2744 | gcc_assert (GET_CODE (addr) == REG); |
2745 | return addr; | |
79e68feb | 2746 | } |
9ee3c687 | 2747 | |
c16eadc7 | 2748 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 2749 | |
5505f548 | 2750 | const char * |
8a4a2253 | 2751 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
2752 | { |
2753 | if (! operands_match_p (operands[0], operands[1])) | |
2754 | { | |
2755 | if (!ADDRESS_REG_P (operands[1])) | |
2756 | { | |
2757 | rtx tmp = operands[1]; | |
2758 | ||
2759 | operands[1] = operands[2]; | |
2760 | operands[2] = tmp; | |
2761 | } | |
2762 | ||
2763 | /* These insns can result from reloads to access | |
2764 | stack slots over 64k from the frame pointer. */ | |
2765 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 2766 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 2767 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 2768 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
2769 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
2770 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
2771 | } |
2772 | if (GET_CODE (operands[2]) == CONST_INT) | |
2773 | { | |
9ee3c687 JW |
2774 | if (INTVAL (operands[2]) > 0 |
2775 | && INTVAL (operands[2]) <= 8) | |
2776 | return "addq%.l %2,%0"; | |
2777 | if (INTVAL (operands[2]) < 0 | |
2778 | && INTVAL (operands[2]) >= -8) | |
2779 | { | |
c5c76735 | 2780 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
2781 | return "subq%.l %2,%0"; |
2782 | } | |
2783 | /* On the CPU32 it is faster to use two addql instructions to | |
2784 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 2785 | Likewise for subql. */ |
fe95f2f7 | 2786 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
2787 | { |
2788 | if (INTVAL (operands[2]) > 8 | |
2789 | && INTVAL (operands[2]) <= 16) | |
2790 | { | |
1d8eaa6b | 2791 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 2792 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
2793 | } |
2794 | if (INTVAL (operands[2]) < -8 | |
2795 | && INTVAL (operands[2]) >= -16) | |
2796 | { | |
c5c76735 | 2797 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 2798 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
2799 | } |
2800 | } | |
9ee3c687 JW |
2801 | if (ADDRESS_REG_P (operands[0]) |
2802 | && INTVAL (operands[2]) >= -0x8000 | |
2803 | && INTVAL (operands[2]) < 0x8000) | |
2804 | { | |
fe95f2f7 | 2805 | if (TUNE_68040) |
9ee3c687 JW |
2806 | return "add%.w %2,%0"; |
2807 | else | |
e6d98cb0 | 2808 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
2809 | } |
2810 | } | |
2811 | return "add%.l %2,%0"; | |
2812 | } | |
79e68feb RS |
2813 | \f |
2814 | /* Store in cc_status the expressions that the condition codes will | |
2815 | describe after execution of an instruction whose pattern is EXP. | |
2816 | Do not alter them if the instruction would not alter the cc's. */ | |
2817 | ||
2818 | /* On the 68000, all the insns to store in an address register fail to | |
2819 | set the cc's. However, in some cases these instructions can make it | |
2820 | possibly invalid to use the saved cc's. In those cases we clear out | |
2821 | some or all of the saved cc's so they won't be used. */ | |
2822 | ||
1d8eaa6b | 2823 | void |
8a4a2253 | 2824 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 2825 | { |
1a8965c4 | 2826 | if (GET_CODE (exp) == SET) |
79e68feb RS |
2827 | { |
2828 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 2829 | CC_STATUS_INIT; |
79e68feb RS |
2830 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
2831 | { | |
f5963e61 | 2832 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 2833 | cc_status.value1 = 0; |
f5963e61 | 2834 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
2835 | cc_status.value2 = 0; |
2836 | } | |
f6ab62e8 RS |
2837 | /* fmoves to memory or data registers do not set the condition |
2838 | codes. Normal moves _do_ set the condition codes, but not in | |
2839 | a way that is appropriate for comparison with 0, because -0.0 | |
2840 | would be treated as a negative nonzero number. Note that it | |
88512ba0 | 2841 | isn't appropriate to conditionalize this restriction on |
f6ab62e8 RS |
2842 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
2843 | we care about the difference between -0.0 and +0.0. */ | |
79e68feb RS |
2844 | else if (!FP_REG_P (SET_DEST (exp)) |
2845 | && SET_DEST (exp) != cc0_rtx | |
2846 | && (FP_REG_P (SET_SRC (exp)) | |
2847 | || GET_CODE (SET_SRC (exp)) == FIX | |
f6ab62e8 | 2848 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
a0a7fbc9 | 2849 | CC_STATUS_INIT; |
79e68feb RS |
2850 | /* A pair of move insns doesn't produce a useful overall cc. */ |
2851 | else if (!FP_REG_P (SET_DEST (exp)) | |
2852 | && !FP_REG_P (SET_SRC (exp)) | |
2853 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
2854 | && (GET_CODE (SET_SRC (exp)) == REG | |
2855 | || GET_CODE (SET_SRC (exp)) == MEM | |
2856 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 2857 | CC_STATUS_INIT; |
e1dff52a | 2858 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
2859 | { |
2860 | cc_status.flags = 0; | |
e1dff52a KH |
2861 | cc_status.value1 = SET_DEST (exp); |
2862 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
2863 | } |
2864 | } | |
2865 | else if (GET_CODE (exp) == PARALLEL | |
2866 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
2867 | { | |
e1dff52a KH |
2868 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
2869 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
2870 | ||
2871 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 2872 | CC_STATUS_INIT; |
e1dff52a | 2873 | else if (dest != pc_rtx) |
79e68feb RS |
2874 | { |
2875 | cc_status.flags = 0; | |
e1dff52a KH |
2876 | cc_status.value1 = dest; |
2877 | cc_status.value2 = src; | |
79e68feb RS |
2878 | } |
2879 | } | |
2880 | else | |
2881 | CC_STATUS_INIT; | |
2882 | if (cc_status.value2 != 0 | |
2883 | && ADDRESS_REG_P (cc_status.value2) | |
2884 | && GET_MODE (cc_status.value2) == QImode) | |
2885 | CC_STATUS_INIT; | |
1a8965c4 | 2886 | if (cc_status.value2 != 0) |
79e68feb RS |
2887 | switch (GET_CODE (cc_status.value2)) |
2888 | { | |
996a5f59 | 2889 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 2890 | case ROTATE: case ROTATERT: |
a126dc3a RH |
2891 | /* These instructions always clear the overflow bit, and set |
2892 | the carry to the bit shifted out. */ | |
2893 | /* ??? We don't currently have a way to signal carry not valid, | |
2894 | nor do we check for it in the branch insns. */ | |
2895 | CC_STATUS_INIT; | |
2896 | break; | |
2897 | ||
2898 | case PLUS: case MINUS: case MULT: | |
2899 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
2900 | if (GET_MODE (cc_status.value2) != VOIDmode) |
2901 | cc_status.flags |= CC_NO_OVERFLOW; | |
2902 | break; | |
2903 | case ZERO_EXTEND: | |
2904 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
2905 | ends with a move insn moving r2 in r2's mode. | |
2906 | Thus, the cc's are set for r2. | |
7a1929e1 | 2907 | This can set N bit spuriously. */ |
79e68feb | 2908 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
2909 | |
2910 | default: | |
2911 | break; | |
79e68feb RS |
2912 | } |
2913 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
2914 | && cc_status.value2 | |
2915 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
2916 | cc_status.value2 = 0; | |
2917 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 2918 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
2919 | cc_status.flags = CC_IN_68881; |
2920 | } | |
2921 | \f | |
5505f548 | 2922 | const char * |
8a4a2253 | 2923 | output_move_const_double (rtx *operands) |
79e68feb | 2924 | { |
1a8965c4 | 2925 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2926 | |
1a8965c4 | 2927 | if (code != 0) |
79e68feb | 2928 | { |
1a8965c4 | 2929 | static char buf[40]; |
79e68feb | 2930 | |
3b4b85c9 | 2931 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2932 | return buf; |
79e68feb | 2933 | } |
1a8965c4 | 2934 | return "fmove%.d %1,%0"; |
79e68feb RS |
2935 | } |
2936 | ||
5505f548 | 2937 | const char * |
8a4a2253 | 2938 | output_move_const_single (rtx *operands) |
79e68feb | 2939 | { |
1a8965c4 | 2940 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2941 | |
1a8965c4 | 2942 | if (code != 0) |
79e68feb | 2943 | { |
1a8965c4 | 2944 | static char buf[40]; |
79e68feb | 2945 | |
3b4b85c9 | 2946 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2947 | return buf; |
79e68feb | 2948 | } |
1a8965c4 | 2949 | return "fmove%.s %f1,%0"; |
79e68feb RS |
2950 | } |
2951 | ||
2952 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
2953 | from the "fmovecr" instruction. | |
2954 | The value, anded with 0xff, gives the code to use in fmovecr | |
2955 | to get the desired constant. */ | |
2956 | ||
7a1929e1 | 2957 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
2958 | |
2959 | static int inited_68881_table = 0; | |
2960 | ||
5505f548 | 2961 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
2962 | "0.0", |
2963 | "1.0", | |
2964 | "10.0", | |
2965 | "100.0", | |
2966 | "10000.0", | |
2967 | "1e8", | |
2968 | "1e16" | |
a0a7fbc9 | 2969 | }; |
c1cfb2ae | 2970 | |
8b60264b | 2971 | static const int codes_68881[7] = { |
c1cfb2ae RS |
2972 | 0x0f, |
2973 | 0x32, | |
2974 | 0x33, | |
2975 | 0x34, | |
2976 | 0x35, | |
2977 | 0x36, | |
2978 | 0x37 | |
a0a7fbc9 | 2979 | }; |
c1cfb2ae RS |
2980 | |
2981 | REAL_VALUE_TYPE values_68881[7]; | |
2982 | ||
2983 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 2984 | strings_68881 to binary. */ |
c1cfb2ae RS |
2985 | |
2986 | void | |
8a4a2253 | 2987 | init_68881_table (void) |
c1cfb2ae RS |
2988 | { |
2989 | int i; | |
2990 | REAL_VALUE_TYPE r; | |
2991 | enum machine_mode mode; | |
2992 | ||
16d82c3c | 2993 | mode = SFmode; |
c1cfb2ae RS |
2994 | for (i = 0; i < 7; i++) |
2995 | { | |
2996 | if (i == 6) | |
16d82c3c | 2997 | mode = DFmode; |
c1cfb2ae RS |
2998 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
2999 | values_68881[i] = r; | |
3000 | } | |
3001 | inited_68881_table = 1; | |
3002 | } | |
79e68feb RS |
3003 | |
3004 | int | |
8a4a2253 | 3005 | standard_68881_constant_p (rtx x) |
79e68feb | 3006 | { |
c1cfb2ae RS |
3007 | REAL_VALUE_TYPE r; |
3008 | int i; | |
79e68feb | 3009 | |
e18db50d | 3010 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 3011 | used at all on those chips. */ |
9cf106c8 | 3012 | if (TUNE_68040_60) |
79e68feb RS |
3013 | return 0; |
3014 | ||
c1cfb2ae RS |
3015 | if (! inited_68881_table) |
3016 | init_68881_table (); | |
3017 | ||
3018 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3019 | ||
64c0b414 AS |
3020 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
3021 | is rejected. */ | |
c1cfb2ae RS |
3022 | for (i = 0; i < 6; i++) |
3023 | { | |
64c0b414 | 3024 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
3025 | return (codes_68881[i]); |
3026 | } | |
3027 | ||
79e68feb RS |
3028 | if (GET_MODE (x) == SFmode) |
3029 | return 0; | |
c1cfb2ae RS |
3030 | |
3031 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
3032 | return (codes_68881[6]); | |
3033 | ||
79e68feb RS |
3034 | /* larger powers of ten in the constants ram are not used |
3035 | because they are not equal to a `double' C constant. */ | |
3036 | return 0; | |
3037 | } | |
3038 | ||
3039 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3040 | or 0 if X is not a power of 2. */ | |
3041 | ||
3042 | int | |
8a4a2253 | 3043 | floating_exact_log2 (rtx x) |
79e68feb | 3044 | { |
c1cfb2ae | 3045 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3046 | int exp; |
79e68feb | 3047 | |
c1cfb2ae | 3048 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3049 | |
eaff3bf8 | 3050 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3051 | return 0; |
3052 | ||
eaff3bf8 RH |
3053 | exp = real_exponent (&r); |
3054 | real_2expN (&r1, exp); | |
3055 | if (REAL_VALUES_EQUAL (r1, r)) | |
3056 | return exp; | |
3057 | ||
79e68feb RS |
3058 | return 0; |
3059 | } | |
3060 | \f | |
79e68feb RS |
3061 | /* A C compound statement to output to stdio stream STREAM the |
3062 | assembler syntax for an instruction operand X. X is an RTL | |
3063 | expression. | |
3064 | ||
3065 | CODE is a value that can be used to specify one of several ways | |
3066 | of printing the operand. It is used when identical operands | |
3067 | must be printed differently depending on the context. CODE | |
3068 | comes from the `%' specification that was used to request | |
3069 | printing of the operand. If the specification was just `%DIGIT' | |
3070 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3071 | is the ASCII code for LTR. | |
3072 | ||
3073 | If X is a register, this macro should print the register's name. | |
3074 | The names can be found in an array `reg_names' whose type is | |
3075 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3076 | ||
3077 | When the machine description has a specification `%PUNCT' (a `%' | |
3078 | followed by a punctuation character), this macro is called with | |
3079 | a null pointer for X and the punctuation character for CODE. | |
3080 | ||
3081 | The m68k specific codes are: | |
3082 | ||
3083 | '.' for dot needed in Motorola-style opcode names. | |
3084 | '-' for an operand pushing on the stack: | |
3085 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3086 | '+' for an operand pushing on the stack: | |
3087 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3088 | '@' for a reference to the top word on the stack: | |
3089 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3090 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3091 | but & in SGS syntax). |
79e68feb RS |
3092 | '!' for the cc register (used in an `and to cc' insn). |
3093 | '$' for the letter `s' in an op code, but only on the 68040. | |
3094 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3095 | '/' for register prefix needed by longlong.h. |
79e68feb RS |
3096 | |
3097 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3098 | 'd' to force memory addressing to be absolute, not relative. | |
3099 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
3100 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3101 | or print pair of registers as rx:ry. | |
29ca003a RS |
3102 | 'p' print an address with @PLTPC attached, but only if the operand |
3103 | is not locally-bound. */ | |
79e68feb RS |
3104 | |
3105 | void | |
8a4a2253 | 3106 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3107 | { |
79e68feb RS |
3108 | if (letter == '.') |
3109 | { | |
e6d98cb0 BI |
3110 | if (MOTOROLA) |
3111 | fprintf (file, "."); | |
79e68feb RS |
3112 | } |
3113 | else if (letter == '#') | |
e6d98cb0 | 3114 | asm_fprintf (file, "%I"); |
79e68feb | 3115 | else if (letter == '-') |
e6d98cb0 | 3116 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 3117 | else if (letter == '+') |
e6d98cb0 | 3118 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 3119 | else if (letter == '@') |
e6d98cb0 | 3120 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 3121 | else if (letter == '!') |
e6d98cb0 | 3122 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3123 | else if (letter == '$') |
3124 | { | |
b101567e | 3125 | if (TARGET_68040) |
e6d98cb0 | 3126 | fprintf (file, "s"); |
79e68feb RS |
3127 | } |
3128 | else if (letter == '&') | |
3129 | { | |
b101567e | 3130 | if (TARGET_68040) |
e6d98cb0 | 3131 | fprintf (file, "d"); |
79e68feb | 3132 | } |
2ac5f14a | 3133 | else if (letter == '/') |
e6d98cb0 | 3134 | asm_fprintf (file, "%R"); |
29ca003a | 3135 | else if (letter == 'p') |
2c8ec431 | 3136 | { |
29ca003a RS |
3137 | output_addr_const (file, op); |
3138 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
3139 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 3140 | } |
79e68feb RS |
3141 | else if (GET_CODE (op) == REG) |
3142 | { | |
1a8965c4 AS |
3143 | if (letter == 'R') |
3144 | /* Print out the second register name of a register pair. | |
3145 | I.e., R (6) => 7. */ | |
01bbf777 | 3146 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3147 | else |
01bbf777 | 3148 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3149 | } |
3150 | else if (GET_CODE (op) == MEM) | |
3151 | { | |
3152 | output_address (XEXP (op, 0)); | |
3153 | if (letter == 'd' && ! TARGET_68020 | |
3154 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3155 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3156 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3157 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 3158 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 3159 | } |
79e68feb RS |
3160 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3161 | { | |
c1cfb2ae RS |
3162 | REAL_VALUE_TYPE r; |
3163 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3164 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3165 | } | |
3166 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3167 | { | |
3168 | REAL_VALUE_TYPE r; | |
3169 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3170 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3171 | } |
e2c0a924 | 3172 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3173 | { |
c1cfb2ae RS |
3174 | REAL_VALUE_TYPE r; |
3175 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3176 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3177 | } |
3178 | else | |
3179 | { | |
2c8ec431 DL |
3180 | /* Use `print_operand_address' instead of `output_addr_const' |
3181 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3182 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3183 | if (TARGET_PCREL |
3184 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3185 | print_operand_address (file, op); | |
3186 | else | |
3187 | output_addr_const (file, op); | |
79e68feb RS |
3188 | } |
3189 | } | |
3190 | ||
3191 | \f | |
3192 | /* A C compound statement to output to stdio stream STREAM the | |
3193 | assembler syntax for an instruction operand that is a memory | |
3194 | reference whose address is ADDR. ADDR is an RTL expression. | |
3195 | ||
3196 | Note that this contains a kludge that knows that the only reason | |
3197 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3198 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3199 | generates a label LInnn: on such an insn. | |
3200 | ||
3201 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3202 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3203 | ||
3204 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
3205 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
3206 | we want. This difference can be accommodated by using an assembler | |
3207 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
3208 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 3209 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
3210 | Some assemblers refuse all the above solutions. The workaround is to |
3211 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 3212 | right behavior. |
79e68feb RS |
3213 | |
3214 | They also do not like things like "pea 1.w", so we simple leave off | |
3215 | the .w on small constants. | |
3216 | ||
3217 | This routine is responsible for distinguishing between -fpic and -fPIC | |
3218 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3219 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3220 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb | 3221 | |
3b4b85c9 | 3222 | #if MOTOROLA |
a0a7fbc9 AS |
3223 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3224 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname) | |
3b4b85c9 | 3225 | #else /* !MOTOROLA */ |
a0a7fbc9 AS |
3226 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3227 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname) | |
3b4b85c9 | 3228 | #endif /* !MOTOROLA */ |
f4a6e73b | 3229 | |
79e68feb | 3230 | void |
8a4a2253 | 3231 | print_operand_address (FILE *file, rtx addr) |
79e68feb RS |
3232 | { |
3233 | register rtx reg1, reg2, breg, ireg; | |
3234 | rtx offset; | |
3235 | ||
3236 | switch (GET_CODE (addr)) | |
3237 | { | |
a0a7fbc9 AS |
3238 | case REG: |
3239 | fprintf (file, MOTOROLA ? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr))); | |
3240 | break; | |
3241 | case PRE_DEC: | |
3242 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", | |
3243 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3244 | break; | |
3245 | case POST_INC: | |
3246 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", | |
3247 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3248 | break; | |
3249 | case PLUS: | |
3250 | reg1 = reg2 = ireg = breg = offset = 0; | |
3251 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) | |
3252 | { | |
3253 | offset = XEXP (addr, 0); | |
3254 | addr = XEXP (addr, 1); | |
3255 | } | |
3256 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) | |
3257 | { | |
3258 | offset = XEXP (addr, 1); | |
3259 | addr = XEXP (addr, 0); | |
3260 | } | |
3261 | if (GET_CODE (addr) != PLUS) | |
3262 | { | |
3263 | ; | |
3264 | } | |
3265 | else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) | |
3266 | { | |
3267 | reg1 = XEXP (addr, 0); | |
3268 | addr = XEXP (addr, 1); | |
3269 | } | |
3270 | else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) | |
3271 | { | |
3272 | reg1 = XEXP (addr, 1); | |
3273 | addr = XEXP (addr, 0); | |
3274 | } | |
3275 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
3276 | { | |
3277 | reg1 = XEXP (addr, 0); | |
3278 | addr = XEXP (addr, 1); | |
3279 | } | |
3280 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
3281 | { | |
3282 | reg1 = XEXP (addr, 1); | |
3283 | addr = XEXP (addr, 0); | |
3284 | } | |
3285 | else if (GET_CODE (XEXP (addr, 0)) == REG) | |
3286 | { | |
3287 | reg1 = XEXP (addr, 0); | |
3288 | addr = XEXP (addr, 1); | |
3289 | } | |
3290 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3291 | { | |
3292 | reg1 = XEXP (addr, 1); | |
3293 | addr = XEXP (addr, 0); | |
3294 | } | |
3295 | if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT | |
3296 | || GET_CODE (addr) == SIGN_EXTEND) | |
3297 | { | |
3298 | if (reg1 == 0) | |
3299 | reg1 = addr; | |
3300 | else | |
3301 | reg2 = addr; | |
3302 | addr = 0; | |
3303 | } | |
79e68feb | 3304 | #if 0 /* for OLD_INDEXING */ |
a0a7fbc9 AS |
3305 | else if (GET_CODE (addr) == PLUS) |
3306 | { | |
3307 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3308 | { | |
3309 | reg2 = XEXP (addr, 0); | |
3310 | addr = XEXP (addr, 1); | |
3311 | } | |
3312 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3313 | { | |
3314 | reg2 = XEXP (addr, 1); | |
3315 | addr = XEXP (addr, 0); | |
3316 | } | |
3317 | } | |
79e68feb | 3318 | #endif |
a0a7fbc9 AS |
3319 | if (offset != 0) |
3320 | { | |
3321 | gcc_assert (!addr); | |
3322 | addr = offset; | |
3323 | } | |
3324 | if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND | |
3325 | || GET_CODE (reg1) == MULT)) | |
3326 | || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) | |
3327 | { | |
3328 | breg = reg2; | |
3329 | ireg = reg1; | |
3330 | } | |
3331 | else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) | |
3332 | { | |
3333 | breg = reg1; | |
3334 | ireg = reg2; | |
3335 | } | |
3336 | if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF | |
3337 | && ! (flag_pic && ireg == pic_offset_table_rtx)) | |
3338 | { | |
3339 | int scale = 1; | |
3340 | if (GET_CODE (ireg) == MULT) | |
3341 | { | |
3342 | scale = INTVAL (XEXP (ireg, 1)); | |
3343 | ireg = XEXP (ireg, 0); | |
3344 | } | |
3345 | if (GET_CODE (ireg) == SIGN_EXTEND) | |
3346 | { | |
3347 | ASM_OUTPUT_CASE_FETCH (file, | |
3348 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3349 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3350 | fprintf (file, "w"); | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | ASM_OUTPUT_CASE_FETCH (file, | |
3355 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3356 | M68K_REGNAME (REGNO (ireg))); | |
3357 | fprintf (file, "l"); | |
3358 | } | |
3359 | if (scale != 1) | |
3360 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3361 | putc (')', file); | |
3362 | break; | |
3363 | } | |
3364 | if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF | |
3365 | && ! (flag_pic && breg == pic_offset_table_rtx)) | |
3366 | { | |
3367 | ASM_OUTPUT_CASE_FETCH (file, | |
3368 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3369 | M68K_REGNAME (REGNO (breg))); | |
3370 | fprintf (file, "l)"); | |
3371 | break; | |
3372 | } | |
3373 | if (ireg != 0 || breg != 0) | |
3374 | { | |
3375 | int scale = 1; | |
4761e388 | 3376 | |
a0a7fbc9 AS |
3377 | gcc_assert (breg); |
3378 | gcc_assert (flag_pic || !addr || GET_CODE (addr) != LABEL_REF); | |
4761e388 | 3379 | |
a0a7fbc9 AS |
3380 | if (MOTOROLA) |
3381 | { | |
3382 | if (addr != 0) | |
3383 | { | |
3384 | output_addr_const (file, addr); | |
3385 | if (flag_pic && (breg == pic_offset_table_rtx)) | |
3386 | { | |
3387 | fprintf (file, "@GOT"); | |
3388 | if (flag_pic == 1) | |
3389 | fprintf (file, ".w"); | |
3390 | } | |
3391 | } | |
3392 | fprintf (file, "(%s", M68K_REGNAME (REGNO (breg))); | |
3393 | if (ireg != 0) | |
3394 | putc (',', file); | |
3395 | } | |
3396 | else /* !MOTOROLA */ | |
3397 | { | |
3398 | fprintf (file, "%s@(", M68K_REGNAME (REGNO (breg))); | |
3399 | if (addr != 0) | |
3400 | { | |
3401 | output_addr_const (file, addr); | |
3402 | if (breg == pic_offset_table_rtx) | |
3403 | switch (flag_pic) | |
e6d98cb0 | 3404 | { |
a0a7fbc9 AS |
3405 | case 1: |
3406 | fprintf (file, ":w"); | |
3407 | break; | |
3408 | case 2: | |
3409 | fprintf (file, ":l"); | |
3410 | break; | |
3411 | default: | |
3412 | break; | |
e6d98cb0 | 3413 | } |
a0a7fbc9 AS |
3414 | if (ireg != 0) |
3415 | putc (',', file); | |
3416 | } | |
3417 | } /* !MOTOROLA */ | |
3418 | if (ireg != 0 && GET_CODE (ireg) == MULT) | |
3419 | { | |
3420 | scale = INTVAL (XEXP (ireg, 1)); | |
3421 | ireg = XEXP (ireg, 0); | |
3422 | } | |
3423 | if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) | |
3424 | fprintf (file, MOTOROLA ? "%s.w" : "%s:w", | |
3425 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3426 | else if (ireg != 0) | |
3427 | fprintf (file, MOTOROLA ? "%s.l" : "%s:l", | |
3428 | M68K_REGNAME (REGNO (ireg))); | |
3429 | if (scale != 1) | |
3430 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3431 | putc (')', file); | |
3432 | break; | |
3433 | } | |
3434 | else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF | |
3435 | && ! (flag_pic && reg1 == pic_offset_table_rtx)) | |
3436 | { | |
3437 | ASM_OUTPUT_CASE_FETCH (file, | |
3438 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3439 | M68K_REGNAME (REGNO (reg1))); | |
3440 | fprintf (file, "l)"); | |
3441 | break; | |
3442 | } | |
3443 | /* FALL-THROUGH (is this really what we want?) */ | |
3444 | default: | |
3445 | if (GET_CODE (addr) == CONST_INT | |
3446 | && INTVAL (addr) < 0x8000 | |
3447 | && INTVAL (addr) >= -0x8000) | |
3448 | { | |
3449 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); | |
3450 | } | |
3451 | else if (GET_CODE (addr) == CONST_INT) | |
3452 | { | |
3453 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); | |
3454 | } | |
3455 | else if (TARGET_PCREL) | |
3456 | { | |
3457 | fputc ('(', file); | |
3458 | output_addr_const (file, addr); | |
3459 | if (flag_pic == 1) | |
3460 | asm_fprintf (file, ":w,%Rpc)"); | |
3461 | else | |
3462 | asm_fprintf (file, ":l,%Rpc)"); | |
3463 | } | |
3464 | else | |
3465 | { | |
3466 | /* Special case for SYMBOL_REF if the symbol name ends in | |
3467 | `.<letter>', this can be mistaken as a size suffix. Put | |
3468 | the name in parentheses. */ | |
3469 | if (GET_CODE (addr) == SYMBOL_REF | |
3470 | && strlen (XSTR (addr, 0)) > 2 | |
3471 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
3472 | { | |
3473 | putc ('(', file); | |
c2ac2ff6 | 3474 | output_addr_const (file, addr); |
a0a7fbc9 AS |
3475 | putc (')', file); |
3476 | } | |
3477 | else | |
3478 | output_addr_const (file, addr); | |
3479 | } | |
3480 | break; | |
79e68feb RS |
3481 | } |
3482 | } | |
af13f02d JW |
3483 | \f |
3484 | /* Check for cases where a clr insns can be omitted from code using | |
3485 | strict_low_part sets. For example, the second clrl here is not needed: | |
3486 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3487 | ||
3488 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3489 | insn we are checking for redundancy. TARGET is the register set by the | |
3490 | clear insn. */ | |
3491 | ||
8a4a2253 BI |
3492 | bool |
3493 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3494 | rtx target) | |
af13f02d JW |
3495 | { |
3496 | rtx p; | |
3497 | ||
3498 | p = prev_nonnote_insn (first_insn); | |
3499 | ||
3500 | while (p) | |
3501 | { | |
3502 | /* If it isn't an insn, then give up. */ | |
3503 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 3504 | return false; |
af13f02d JW |
3505 | |
3506 | if (reg_set_p (target, p)) | |
3507 | { | |
3508 | rtx set = single_set (p); | |
3509 | rtx dest; | |
3510 | ||
3511 | /* If it isn't an easy to recognize insn, then give up. */ | |
3512 | if (! set) | |
8a4a2253 | 3513 | return false; |
af13f02d JW |
3514 | |
3515 | dest = SET_DEST (set); | |
3516 | ||
3517 | /* If this sets the entire target register to zero, then our | |
3518 | first_insn is redundant. */ | |
3519 | if (rtx_equal_p (dest, target) | |
3520 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3521 | return true; |
af13f02d JW |
3522 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3523 | && GET_CODE (XEXP (dest, 0)) == REG | |
3524 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3525 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3526 | <= GET_MODE_SIZE (mode))) | |
3527 | /* This is a strict low part set which modifies less than | |
3528 | we are using, so it is safe. */ | |
3529 | ; | |
3530 | else | |
8a4a2253 | 3531 | return false; |
af13f02d JW |
3532 | } |
3533 | ||
3534 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3535 | } |
3536 | ||
8a4a2253 | 3537 | return false; |
af13f02d | 3538 | } |
67cd4f83 | 3539 | |
2c8ec431 DL |
3540 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3541 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3542 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3543 | |
3544 | We model this by restricting the meaning of the basic predicates | |
3545 | (general_operand, memory_operand, etc) to forbid the use of this | |
3546 | addressing mode, and then define the following predicates that permit | |
3547 | this addressing mode. These predicates can then be used for the | |
3548 | source operands of the appropriate instructions. | |
3549 | ||
3550 | n.b. While it is theoretically possible to change all machine patterns | |
3551 | to use this addressing more where permitted by the architecture, | |
3552 | it has only been implemented for "common" cases: SImode, HImode, and | |
3553 | QImode operands, and only for the principle operations that would | |
3554 | require this addressing mode: data movement and simple integer operations. | |
3555 | ||
3556 | In parallel with these new predicates, two new constraint letters | |
3557 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3558 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3559 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3560 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3561 | of how these constraints are used. | |
3562 | ||
3563 | The use of these predicates is strictly optional, though patterns that | |
3564 | don't will cause an extra reload register to be allocated where one | |
3565 | was not necessary: | |
3566 | ||
3567 | lea (abc:w,%pc),%a0 ; need to reload address | |
3568 | moveq &1,%d1 ; since write to pc-relative space | |
3569 | movel %d1,%a0@ ; is not allowed | |
3570 | ... | |
3571 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3572 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3573 | ||
3574 | For more info, consult tiemann@cygnus.com. | |
3575 | ||
3576 | ||
3577 | All of the ugliness with predicates and constraints is due to the | |
3578 | simple fact that the m68k does not allow a pc-relative addressing | |
3579 | mode as a destination. gcc does not distinguish between source and | |
3580 | destination addresses. Hence, if we claim that pc-relative address | |
3581 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3582 | end up with invalid code. To get around this problem, we left | |
3583 | pc-relative modes as invalid addresses, and then added special | |
3584 | predicates and constraints to accept them. | |
3585 | ||
3586 | A cleaner way to handle this is to modify gcc to distinguish | |
3587 | between source and destination addresses. We can then say that | |
3588 | pc-relative is a valid source address but not a valid destination | |
3589 | address, and hopefully avoid a lot of the predicate and constraint | |
3590 | hackery. Unfortunately, this would be a pretty big change. It would | |
3591 | be a useful change for a number of ports, but there aren't any current | |
3592 | plans to undertake this. | |
3593 | ||
3594 | ***************************************************************************/ | |
3595 | ||
3596 | ||
5505f548 | 3597 | const char * |
8a4a2253 | 3598 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3599 | { |
3600 | int logval; | |
3601 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 3602 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
3603 | && (DATA_REG_P (operands[0]) |
3604 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3605 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3606 | { |
3607 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3608 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 3609 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
3610 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3611 | CC_STATUS_INIT; | |
3612 | if (operands[2] == const0_rtx) | |
3613 | return "clr%.w %0"; | |
3614 | return "and%.w %2,%0"; | |
3615 | } | |
3616 | if (GET_CODE (operands[2]) == CONST_INT | |
3617 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
3618 | && (DATA_REG_P (operands[0]) | |
3619 | || offsettable_memref_p (operands[0]))) | |
3620 | { | |
3621 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 3622 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3623 | else |
3624 | { | |
b72f00af | 3625 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3626 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3627 | } |
3628 | /* This does not set condition codes in a standard way. */ | |
3629 | CC_STATUS_INIT; | |
3630 | return "bclr %1,%0"; | |
3631 | } | |
3632 | return "and%.l %2,%0"; | |
3633 | } | |
3634 | ||
5505f548 | 3635 | const char * |
8a4a2253 | 3636 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
3637 | { |
3638 | register int logval; | |
3639 | if (GET_CODE (operands[2]) == CONST_INT | |
3640 | && INTVAL (operands[2]) >> 16 == 0 | |
3641 | && (DATA_REG_P (operands[0]) | |
3642 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3643 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3644 | { |
3645 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3646 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3647 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3648 | CC_STATUS_INIT; | |
3649 | if (INTVAL (operands[2]) == 0xffff) | |
3650 | return "mov%.w %2,%0"; | |
3651 | return "or%.w %2,%0"; | |
3652 | } | |
3653 | if (GET_CODE (operands[2]) == CONST_INT | |
3654 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3655 | && (DATA_REG_P (operands[0]) | |
3656 | || offsettable_memref_p (operands[0]))) | |
3657 | { | |
3658 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3659 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3660 | else |
3661 | { | |
b72f00af | 3662 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3663 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3664 | } |
3665 | CC_STATUS_INIT; | |
3666 | return "bset %1,%0"; | |
3667 | } | |
3668 | return "or%.l %2,%0"; | |
3669 | } | |
3670 | ||
5505f548 | 3671 | const char * |
8a4a2253 | 3672 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
3673 | { |
3674 | register int logval; | |
3675 | if (GET_CODE (operands[2]) == CONST_INT | |
3676 | && INTVAL (operands[2]) >> 16 == 0 | |
3677 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 3678 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3679 | { |
3680 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 3681 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3682 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3683 | CC_STATUS_INIT; | |
3684 | if (INTVAL (operands[2]) == 0xffff) | |
3685 | return "not%.w %0"; | |
3686 | return "eor%.w %2,%0"; | |
3687 | } | |
3688 | if (GET_CODE (operands[2]) == CONST_INT | |
3689 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3690 | && (DATA_REG_P (operands[0]) | |
3691 | || offsettable_memref_p (operands[0]))) | |
3692 | { | |
3693 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3694 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3695 | else |
3696 | { | |
b72f00af | 3697 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3698 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3699 | } |
3700 | CC_STATUS_INIT; | |
3701 | return "bchg %1,%0"; | |
3702 | } | |
3703 | return "eor%.l %2,%0"; | |
3704 | } | |
7c262518 | 3705 | |
29ca003a RS |
3706 | /* Return the instruction that should be used for a call to address X, |
3707 | which is known to be in operand 0. */ | |
3708 | ||
3709 | const char * | |
3710 | output_call (rtx x) | |
3711 | { | |
3712 | if (symbolic_operand (x, VOIDmode)) | |
3713 | return m68k_symbolic_call; | |
3714 | else | |
3715 | return "jsr %a0"; | |
3716 | } | |
3717 | ||
45849738 BI |
3718 | #ifdef M68K_TARGET_COFF |
3719 | ||
3720 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
3721 | ||
3722 | static void | |
c18a5b6c MM |
3723 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
3724 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
3725 | { |
3726 | char flagchar; | |
3727 | ||
3728 | if (flags & SECTION_WRITE) | |
3729 | flagchar = 'd'; | |
3730 | else | |
3731 | flagchar = 'x'; | |
3732 | ||
3733 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
3734 | } | |
3735 | ||
3736 | #endif /* M68K_TARGET_COFF */ | |
3737 | ||
c590b625 | 3738 | static void |
8a4a2253 BI |
3739 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
3740 | HOST_WIDE_INT delta, | |
3741 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
3742 | tree function) | |
483ab821 | 3743 | { |
c590b625 RH |
3744 | rtx xops[1]; |
3745 | const char *fmt; | |
3746 | ||
3747 | if (delta > 0 && delta <= 8) | |
a0a7fbc9 AS |
3748 | asm_fprintf (file, (MOTOROLA |
3749 | ? "\taddq.l %I%d,4(%Rsp)\n" | |
3750 | : "\taddql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3751 | (int) delta); |
c590b625 | 3752 | else if (delta < 0 && delta >= -8) |
a0a7fbc9 AS |
3753 | asm_fprintf (file, (MOTOROLA |
3754 | ? "\tsubq.l %I%d,4(%Rsp)\n" | |
3755 | : "\tsubql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3756 | (int) -delta); |
5050d266 PB |
3757 | else if (TARGET_COLDFIRE) |
3758 | { | |
3759 | /* ColdFire can't add/sub a constant to memory unless it is in | |
3760 | the range of addq/subq. So load the value into %d0 and | |
3761 | then add it to 4(%sp). */ | |
3762 | if (delta >= -128 && delta <= 127) | |
a0a7fbc9 AS |
3763 | asm_fprintf (file, (MOTOROLA |
3764 | ? "\tmoveq.l %I%wd,%Rd0\n" | |
3765 | : "\tmoveql %I%wd,%Rd0\n"), | |
3766 | delta); | |
5050d266 | 3767 | else |
a0a7fbc9 AS |
3768 | asm_fprintf (file, (MOTOROLA |
3769 | ? "\tmove.l %I%wd,%Rd0\n" | |
3770 | : "\tmovel %I%wd,%Rd0\n"), | |
3771 | delta); | |
3772 | asm_fprintf (file, (MOTOROLA | |
3773 | ? "\tadd.l %Rd0,4(%Rsp)\n" | |
3774 | : "\taddl %Rd0,%Rsp@(4)\n")); | |
5050d266 | 3775 | } |
c590b625 | 3776 | else |
a0a7fbc9 AS |
3777 | asm_fprintf (file, (MOTOROLA |
3778 | ? "\tadd.l %I%wd,4(%Rsp)\n" | |
3779 | : "\taddl %I%wd,%Rsp@(4)\n"), | |
e6d98cb0 | 3780 | delta); |
c590b625 RH |
3781 | |
3782 | xops[0] = DECL_RTL (function); | |
3783 | ||
29ca003a RS |
3784 | gcc_assert (MEM_P (xops[0]) |
3785 | && symbolic_operand (XEXP (xops[0], 0), VOIDmode)); | |
3786 | xops[0] = XEXP (xops[0], 0); | |
3787 | ||
3788 | fmt = m68k_symbolic_jump; | |
3789 | if (m68k_symbolic_jump == NULL) | |
3790 | fmt = "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)"; | |
c590b625 RH |
3791 | |
3792 | output_asm_insn (fmt, xops); | |
483ab821 | 3793 | } |
8636be86 KH |
3794 | |
3795 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
3796 | ||
3797 | static rtx | |
3798 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3799 | int incoming ATTRIBUTE_UNUSED) | |
3800 | { | |
3801 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
3802 | } | |
cfca21cb PB |
3803 | |
3804 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
3805 | int | |
3806 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
3807 | unsigned int new_reg) | |
3808 | { | |
3809 | ||
3810 | /* Interrupt functions can only use registers that have already been | |
3811 | saved by the prologue, even if they would normally be | |
3812 | call-clobbered. */ | |
3813 | ||
3814 | if (m68k_interrupt_function_p (current_function_decl) | |
3815 | && !regs_ever_live[new_reg]) | |
3816 | return 0; | |
3817 | ||
3818 | return 1; | |
3819 | } | |
70028b61 PB |
3820 | |
3821 | /* Value is true if hard register REGNO can hold a value of machine-mode MODE. | |
3822 | On the 68000, the cpu registers can hold any mode except bytes in address | |
3823 | registers, but the 68881 registers can hold only SFmode or DFmode. */ | |
3824 | bool | |
3825 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
3826 | { | |
36e04090 | 3827 | if (DATA_REGNO_P (regno)) |
70028b61 | 3828 | { |
a0a7fbc9 AS |
3829 | /* Data Registers, can hold aggregate if fits in. */ |
3830 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
3831 | return true; | |
70028b61 | 3832 | } |
36e04090 | 3833 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 3834 | { |
a0a7fbc9 AS |
3835 | /* Address Registers, can't hold bytes, can hold aggregate if |
3836 | fits in. */ | |
3837 | if (GET_MODE_SIZE (mode) == 1) | |
3838 | return false; | |
3839 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) | |
3840 | return true; | |
70028b61 | 3841 | } |
36e04090 | 3842 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
3843 | { |
3844 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
3845 | smaller. */ |
3846 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
3847 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 3848 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 3849 | return true; |
70028b61 PB |
3850 | } |
3851 | return false; | |
3852 | } | |
dcc21c4c PB |
3853 | |
3854 | /* Return floating point values in a 68881 register. This makes 68881 code | |
3855 | a little bit faster. It also makes -msoft-float code incompatible with | |
3856 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 3857 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
3858 | If there is need for a hard-float ABI it is probably worth doing it |
3859 | properly and also passing function arguments in FP registers. */ | |
3860 | rtx | |
3861 | m68k_libcall_value (enum machine_mode mode) | |
3862 | { | |
3863 | switch (mode) { | |
3864 | case SFmode: | |
3865 | case DFmode: | |
3866 | case XFmode: | |
3867 | if (TARGET_68881) | |
3868 | return gen_rtx_REG (mode, 16); | |
3869 | break; | |
3870 | default: | |
3871 | break; | |
3872 | } | |
3873 | return gen_rtx_REG (mode, 0); | |
3874 | } | |
3875 | ||
3876 | rtx | |
3877 | m68k_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
3878 | { | |
3879 | enum machine_mode mode; | |
3880 | ||
3881 | mode = TYPE_MODE (valtype); | |
3882 | switch (mode) { | |
3883 | case SFmode: | |
3884 | case DFmode: | |
3885 | case XFmode: | |
3886 | if (TARGET_68881) | |
3887 | return gen_rtx_REG (mode, 16); | |
3888 | break; | |
3889 | default: | |
3890 | break; | |
3891 | } | |
3892 | ||
576c9028 KH |
3893 | /* If the function returns a pointer, push that into %a0. */ |
3894 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
3895 | /* For compatibility with the large body of existing code which | |
3896 | does not always properly declare external functions returning | |
3897 | pointer types, the m68k/SVR4 convention is to copy the value | |
3898 | returned for pointer functions from a0 to d0 in the function | |
3899 | epilogue, so that callers that have neglected to properly | |
3900 | declare the callee can still find the correct return value in | |
3901 | d0. */ | |
3902 | return gen_rtx_PARALLEL | |
3903 | (mode, | |
3904 | gen_rtvec (2, | |
3905 | gen_rtx_EXPR_LIST (VOIDmode, | |
3906 | gen_rtx_REG (mode, A0_REG), | |
3907 | const0_rtx), | |
3908 | gen_rtx_EXPR_LIST (VOIDmode, | |
3909 | gen_rtx_REG (mode, D0_REG), | |
3910 | const0_rtx))); | |
3911 | else if (POINTER_TYPE_P (valtype)) | |
3912 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 3913 | else |
576c9028 | 3914 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 3915 | } |