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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
7adcbafe | 2 | Copyright (C) 1987-2022 Free Software Foundation, Inc. |
79e68feb | 3 | |
7ec022b2 | 4 | This file is part of GCC. |
79e68feb | 5 | |
7ec022b2 | 6 | GCC is free software; you can redistribute it and/or modify |
79e68feb | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
79e68feb RS |
9 | any later version. |
10 | ||
7ec022b2 | 11 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
79e68feb | 19 | |
8fcc61f8 RS |
20 | #define IN_TARGET_CODE 1 |
21 | ||
79e68feb | 22 | #include "config.h" |
6cebc6cb | 23 | #define INCLUDE_STRING |
f5220a5d | 24 | #include "system.h" |
4977bab6 | 25 | #include "coretypes.h" |
c7131fb2 | 26 | #include "backend.h" |
9fdcd34e | 27 | #include "cfghooks.h" |
da932f04 | 28 | #include "tree.h" |
314e6352 ML |
29 | #include "stringpool.h" |
30 | #include "attribs.h" | |
c7131fb2 AM |
31 | #include "rtl.h" |
32 | #include "df.h" | |
33 | #include "alias.h" | |
40e23961 | 34 | #include "fold-const.h" |
d8a2d370 DN |
35 | #include "calls.h" |
36 | #include "stor-layout.h" | |
37 | #include "varasm.h" | |
79e68feb | 38 | #include "regs.h" |
79e68feb RS |
39 | #include "insn-config.h" |
40 | #include "conditions.h" | |
79e68feb RS |
41 | #include "output.h" |
42 | #include "insn-attr.h" | |
1d8eaa6b | 43 | #include "recog.h" |
718f9c0f | 44 | #include "diagnostic-core.h" |
36566b39 | 45 | #include "flags.h" |
36566b39 PK |
46 | #include "expmed.h" |
47 | #include "dojump.h" | |
48 | #include "explow.h" | |
4d0cdd0c | 49 | #include "memmodel.h" |
36566b39 PK |
50 | #include "emit-rtl.h" |
51 | #include "stmt.h" | |
6d5f49b2 RH |
52 | #include "expr.h" |
53 | #include "reload.h" | |
5505f548 | 54 | #include "tm_p.h" |
672a6f42 | 55 | #include "target.h" |
2cc07db4 | 56 | #include "debug.h" |
60393bbc AM |
57 | #include "cfgrtl.h" |
58 | #include "cfganal.h" | |
59 | #include "lcm.h" | |
60 | #include "cfgbuild.h" | |
61 | #include "cfgcleanup.h" | |
b8c96320 MK |
62 | /* ??? Need to add a dependency between m68k.o and sched-int.h. */ |
63 | #include "sched-int.h" | |
64 | #include "insn-codes.h" | |
96e45421 | 65 | #include "opts.h" |
8b281334 | 66 | #include "optabs.h" |
9b2b7279 | 67 | #include "builtins.h" |
82eee4f1 | 68 | #include "rtl-iter.h" |
c518c102 | 69 | #include "toplev.h" |
79e68feb | 70 | |
994c5d85 | 71 | /* This file should be included last. */ |
d58627a0 RS |
72 | #include "target-def.h" |
73 | ||
a4e9467d RZ |
74 | enum reg_class regno_reg_class[] = |
75 | { | |
76 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
77 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
78 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
79 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
80 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
81 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
82 | ADDR_REGS | |
83 | }; | |
84 | ||
85 | ||
a40ed0f3 KH |
86 | /* The minimum number of integer registers that we want to save with the |
87 | movem instruction. Using two movel instructions instead of a single | |
88 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
89 | code size. */ | |
90 | #define MIN_MOVEM_REGS 3 | |
91 | ||
92 | /* The minimum number of floating point registers that we want to save | |
93 | with the fmovem instruction. */ | |
94 | #define MIN_FMOVEM_REGS 1 | |
95 | ||
ff482c8d | 96 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
97 | struct m68k_frame |
98 | { | |
99 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 100 | HOST_WIDE_INT offset; |
3d74bc09 BI |
101 | |
102 | /* Offset of FPU registers. */ | |
103 | HOST_WIDE_INT foffset; | |
104 | ||
105 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 106 | HOST_WIDE_INT size; |
3d74bc09 BI |
107 | |
108 | /* Data and address register. */ | |
48ed72a4 PB |
109 | int reg_no; |
110 | unsigned int reg_mask; | |
3d74bc09 BI |
111 | |
112 | /* FPU registers. */ | |
48ed72a4 PB |
113 | int fpu_no; |
114 | unsigned int fpu_mask; | |
3d74bc09 BI |
115 | |
116 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
117 | HOST_WIDE_INT frame_pointer_offset; |
118 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
119 | |
120 | /* Function which the above information refers to. */ | |
121 | int funcdef_no; | |
48ed72a4 PB |
122 | }; |
123 | ||
3d74bc09 BI |
124 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
125 | static struct m68k_frame current_frame; | |
126 | ||
fc2241eb RS |
127 | /* Structure describing an m68k address. |
128 | ||
129 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
130 | with null fields evaluating to 0. Here: | |
131 | ||
132 | - BASE satisfies m68k_legitimate_base_reg_p | |
133 | - INDEX satisfies m68k_legitimate_index_reg_p | |
134 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
135 | ||
136 | INDEX is either HImode or SImode. The other fields are SImode. | |
137 | ||
138 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
139 | the address is (BASE)+. */ | |
140 | struct m68k_address { | |
141 | enum rtx_code code; | |
142 | rtx base; | |
143 | rtx index; | |
144 | rtx offset; | |
145 | int scale; | |
146 | }; | |
147 | ||
b505225b TS |
148 | static int m68k_sched_adjust_cost (rtx_insn *, int, rtx_insn *, int, |
149 | unsigned int); | |
96fcacb7 | 150 | static int m68k_sched_issue_rate (void); |
ac44248e | 151 | static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int); |
b8c96320 MK |
152 | static void m68k_sched_md_init_global (FILE *, int, int); |
153 | static void m68k_sched_md_finish_global (FILE *, int); | |
154 | static void m68k_sched_md_init (FILE *, int, int); | |
155 | static void m68k_sched_dfa_pre_advance_cycle (void); | |
156 | static void m68k_sched_dfa_post_advance_cycle (void); | |
96fcacb7 | 157 | static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); |
b8c96320 | 158 | |
7b5cbb57 | 159 | static bool m68k_can_eliminate (const int, const int); |
5efd84c5 | 160 | static void m68k_conditional_register_usage (void); |
ef4bddc2 | 161 | static bool m68k_legitimate_address_p (machine_mode, rtx, bool); |
c5387660 | 162 | static void m68k_option_override (void); |
03e69b12 | 163 | static void m68k_override_options_after_change (void); |
8a4a2253 BI |
164 | static rtx find_addr_reg (rtx); |
165 | static const char *singlemove_string (rtx *); | |
8a4a2253 BI |
166 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
167 | HOST_WIDE_INT, tree); | |
8636be86 | 168 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
169 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
170 | tree args, int flags, | |
171 | bool *no_add_attrs); | |
3d74bc09 | 172 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 173 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
f7e70894 | 174 | static bool m68k_ok_for_sibcall_p (tree, tree); |
75df395f | 175 | static bool m68k_tls_symbol_p (rtx); |
ef4bddc2 | 176 | static rtx m68k_legitimize_address (rtx, rtx, machine_mode); |
e548c9df | 177 | static bool m68k_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
1c445f03 | 178 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
511e41e5 | 179 | static bool m68k_return_in_memory (const_tree, const_tree); |
1c445f03 | 180 | #endif |
75df395f | 181 | static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
e0601576 | 182 | static void m68k_trampoline_init (rtx, tree, rtx); |
a20c5714 | 183 | static poly_int64 m68k_return_pops_args (tree, tree, poly_int64); |
7b0f476d | 184 | static rtx m68k_delegitimize_address (rtx); |
6930c98c RS |
185 | static void m68k_function_arg_advance (cumulative_args_t, |
186 | const function_arg_info &); | |
6783fdb7 | 187 | static rtx m68k_function_arg (cumulative_args_t, const function_arg_info &); |
ef4bddc2 | 188 | static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x); |
cb69db4f | 189 | static bool m68k_output_addr_const_extra (FILE *, rtx); |
8b281334 | 190 | static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; |
b89de1b8 JG |
191 | static enum flt_eval_method |
192 | m68k_excess_precision (enum excess_precision_type); | |
c43f4279 | 193 | static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode); |
f939c3e6 | 194 | static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode); |
99e1629f | 195 | static bool m68k_modes_tieable_p (machine_mode, machine_mode); |
d3719ee2 JM |
196 | static machine_mode m68k_promote_function_mode (const_tree, machine_mode, |
197 | int *, const_tree, int); | |
6cebc6cb | 198 | static void m68k_asm_final_postscan_insn (FILE *, rtx_insn *insn, rtx [], int); |
79e68feb | 199 | \f |
672a6f42 | 200 | /* Initialize the GCC target structure. */ |
301d03af RS |
201 | |
202 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
203 | #undef TARGET_ASM_ALIGNED_HI_OP | |
204 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
205 | #endif | |
206 | ||
207 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
208 | #undef TARGET_ASM_BYTE_OP | |
209 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
210 | #undef TARGET_ASM_ALIGNED_HI_OP | |
211 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
212 | #undef TARGET_ASM_ALIGNED_SI_OP | |
213 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
214 | #endif | |
215 | ||
216 | #if INT_OP_GROUP == INT_OP_DC | |
217 | #undef TARGET_ASM_BYTE_OP | |
218 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
219 | #undef TARGET_ASM_ALIGNED_HI_OP | |
220 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
221 | #undef TARGET_ASM_ALIGNED_SI_OP | |
222 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
223 | #endif | |
224 | ||
225 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
226 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
227 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
228 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
229 | ||
c590b625 RH |
230 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
231 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 | 232 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 233 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 234 | |
1bc7c5b6 ZW |
235 | #undef TARGET_ASM_FILE_START_APP_OFF |
236 | #define TARGET_ASM_FILE_START_APP_OFF true | |
237 | ||
506d7b68 PB |
238 | #undef TARGET_LEGITIMIZE_ADDRESS |
239 | #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address | |
240 | ||
b8c96320 MK |
241 | #undef TARGET_SCHED_ADJUST_COST |
242 | #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost | |
243 | ||
96fcacb7 MK |
244 | #undef TARGET_SCHED_ISSUE_RATE |
245 | #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate | |
246 | ||
b8c96320 MK |
247 | #undef TARGET_SCHED_VARIABLE_ISSUE |
248 | #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue | |
249 | ||
250 | #undef TARGET_SCHED_INIT_GLOBAL | |
251 | #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global | |
252 | ||
253 | #undef TARGET_SCHED_FINISH_GLOBAL | |
254 | #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global | |
255 | ||
256 | #undef TARGET_SCHED_INIT | |
257 | #define TARGET_SCHED_INIT m68k_sched_md_init | |
258 | ||
259 | #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE | |
260 | #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle | |
261 | ||
262 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
263 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle | |
264 | ||
96fcacb7 MK |
265 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
266 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
267 | m68k_sched_first_cycle_multipass_dfa_lookahead | |
268 | ||
c5387660 JM |
269 | #undef TARGET_OPTION_OVERRIDE |
270 | #define TARGET_OPTION_OVERRIDE m68k_option_override | |
271 | ||
03e69b12 MP |
272 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
273 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change | |
274 | ||
3c50106f RH |
275 | #undef TARGET_RTX_COSTS |
276 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
277 | ||
48ed72a4 PB |
278 | #undef TARGET_ATTRIBUTE_TABLE |
279 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
280 | ||
8636be86 | 281 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 282 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
8636be86 KH |
283 | |
284 | #undef TARGET_STRUCT_VALUE_RTX | |
285 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
286 | ||
7ffb5e78 | 287 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
fbbf66e7 | 288 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem |
7ffb5e78 | 289 | |
f7e70894 RS |
290 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
291 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
292 | ||
1c445f03 NS |
293 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
294 | #undef TARGET_RETURN_IN_MEMORY | |
295 | #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory | |
296 | #endif | |
297 | ||
75df395f MK |
298 | #ifdef HAVE_AS_TLS |
299 | #undef TARGET_HAVE_TLS | |
300 | #define TARGET_HAVE_TLS (true) | |
301 | ||
302 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
303 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel | |
304 | #endif | |
305 | ||
d81db636 SB |
306 | #undef TARGET_LRA_P |
307 | #define TARGET_LRA_P hook_bool_void_false | |
308 | ||
c6c3dba9 PB |
309 | #undef TARGET_LEGITIMATE_ADDRESS_P |
310 | #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p | |
311 | ||
7b5cbb57 AS |
312 | #undef TARGET_CAN_ELIMINATE |
313 | #define TARGET_CAN_ELIMINATE m68k_can_eliminate | |
314 | ||
5efd84c5 NF |
315 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
316 | #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage | |
317 | ||
e0601576 RH |
318 | #undef TARGET_TRAMPOLINE_INIT |
319 | #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init | |
320 | ||
079e7538 NF |
321 | #undef TARGET_RETURN_POPS_ARGS |
322 | #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args | |
323 | ||
7b0f476d AS |
324 | #undef TARGET_DELEGITIMIZE_ADDRESS |
325 | #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address | |
326 | ||
13d3961c NF |
327 | #undef TARGET_FUNCTION_ARG |
328 | #define TARGET_FUNCTION_ARG m68k_function_arg | |
329 | ||
330 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
331 | #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance | |
332 | ||
1a627b35 RS |
333 | #undef TARGET_LEGITIMATE_CONSTANT_P |
334 | #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p | |
335 | ||
cb69db4f AS |
336 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
337 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra | |
338 | ||
b89de1b8 JG |
339 | #undef TARGET_C_EXCESS_PRECISION |
340 | #define TARGET_C_EXCESS_PRECISION m68k_excess_precision | |
341 | ||
4c1fd084 RH |
342 | /* The value stored by TAS. */ |
343 | #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL | |
344 | #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128 | |
345 | ||
c43f4279 RS |
346 | #undef TARGET_HARD_REGNO_NREGS |
347 | #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs | |
f939c3e6 RS |
348 | #undef TARGET_HARD_REGNO_MODE_OK |
349 | #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok | |
350 | ||
99e1629f RS |
351 | #undef TARGET_MODES_TIEABLE_P |
352 | #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p | |
353 | ||
d3719ee2 JM |
354 | #undef TARGET_PROMOTE_FUNCTION_MODE |
355 | #define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode | |
356 | ||
a1293ed1 JL |
357 | #undef TARGET_HAVE_SPECULATION_SAFE_VALUE |
358 | #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed | |
359 | ||
6cebc6cb BS |
360 | #undef TARGET_ASM_FINAL_POSTSCAN_INSN |
361 | #define TARGET_ASM_FINAL_POSTSCAN_INSN m68k_asm_final_postscan_insn | |
362 | ||
48ed72a4 PB |
363 | static const struct attribute_spec m68k_attribute_table[] = |
364 | { | |
4849deb1 JJ |
365 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, |
366 | affects_type_identity, handler, exclude } */ | |
367 | { "interrupt", 0, 0, true, false, false, false, | |
368 | m68k_handle_fndecl_attribute, NULL }, | |
369 | { "interrupt_handler", 0, 0, true, false, false, false, | |
370 | m68k_handle_fndecl_attribute, NULL }, | |
371 | { "interrupt_thread", 0, 0, true, false, false, false, | |
372 | m68k_handle_fndecl_attribute, NULL }, | |
373 | { NULL, 0, 0, false, false, false, false, NULL, NULL } | |
48ed72a4 PB |
374 | }; |
375 | ||
f6897b10 | 376 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 377 | \f |
900ec02d JB |
378 | /* Base flags for 68k ISAs. */ |
379 | #define FL_FOR_isa_00 FL_ISA_68000 | |
380 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
381 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
382 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
383 | not to. */ | |
384 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
6a2b269b | 385 | | FL_BITFIELD | FL_68881 | FL_CAS) |
900ec02d JB |
386 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) |
387 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
388 | ||
389 | /* Base flags for ColdFire ISAs. */ | |
390 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
391 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
392 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
393 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
4e2b26aa | 394 | /* ISA_C is not upwardly compatible with ISA_B. */ |
8c5c99dc | 395 | #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP) |
900ec02d JB |
396 | |
397 | enum m68k_isa | |
398 | { | |
399 | /* Traditional 68000 instruction sets. */ | |
400 | isa_00, | |
401 | isa_10, | |
402 | isa_20, | |
403 | isa_40, | |
404 | isa_cpu32, | |
405 | /* ColdFire instruction set variants. */ | |
406 | isa_a, | |
407 | isa_aplus, | |
408 | isa_b, | |
409 | isa_c, | |
410 | isa_max | |
411 | }; | |
412 | ||
413 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
414 | struct m68k_target_selection | |
415 | { | |
416 | /* The argument being described. */ | |
417 | const char *name; | |
418 | ||
419 | /* For -mcpu, this is the device selected by the option. | |
420 | For -mtune and -march, it is a representative device | |
421 | for the microarchitecture or ISA respectively. */ | |
422 | enum target_device device; | |
423 | ||
424 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
425 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
426 | const char *family; | |
427 | enum uarch_type microarch; | |
428 | enum m68k_isa isa; | |
429 | unsigned long flags; | |
430 | }; | |
431 | ||
432 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
433 | static const struct m68k_target_selection all_devices[] = | |
434 | { | |
435 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
436 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
437 | #include "m68k-devices.def" | |
438 | #undef M68K_DEVICE | |
439 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
440 | }; | |
441 | ||
442 | /* A list of all ISAs, mapping each one to a representative device. | |
443 | Used for -march selection. */ | |
444 | static const struct m68k_target_selection all_isas[] = | |
445 | { | |
47c94d21 JM |
446 | #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
447 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
448 | #include "m68k-isas.def" | |
449 | #undef M68K_ISA | |
900ec02d JB |
450 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
451 | }; | |
452 | ||
453 | /* A list of all microarchitectures, mapping each one to a representative | |
454 | device. Used for -mtune selection. */ | |
455 | static const struct m68k_target_selection all_microarchs[] = | |
456 | { | |
47c94d21 JM |
457 | #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ |
458 | { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, | |
459 | #include "m68k-microarchs.def" | |
460 | #undef M68K_MICROARCH | |
900ec02d JB |
461 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
462 | }; | |
463 | \f | |
464 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
465 | or null for options that have not been used. */ | |
466 | const struct m68k_target_selection *m68k_cpu_entry; | |
467 | const struct m68k_target_selection *m68k_arch_entry; | |
468 | const struct m68k_target_selection *m68k_tune_entry; | |
469 | ||
470 | /* Which CPU we are generating code for. */ | |
471 | enum target_device m68k_cpu; | |
472 | ||
473 | /* Which microarchitecture to tune for. */ | |
474 | enum uarch_type m68k_tune; | |
475 | ||
476 | /* Which FPU to use. */ | |
477 | enum fpu_type m68k_fpu; | |
4af06170 | 478 | |
900ec02d JB |
479 | /* The set of FL_* flags that apply to the target processor. */ |
480 | unsigned int m68k_cpu_flags; | |
29ca003a | 481 | |
03b3e271 KH |
482 | /* The set of FL_* flags that apply to the processor to be tuned for. */ |
483 | unsigned int m68k_tune_flags; | |
484 | ||
29ca003a RS |
485 | /* Asm templates for calling or jumping to an arbitrary symbolic address, |
486 | or NULL if such calls or jumps are not supported. The address is held | |
487 | in operand 0. */ | |
488 | const char *m68k_symbolic_call; | |
489 | const char *m68k_symbolic_jump; | |
c47b0cb4 MK |
490 | |
491 | /* Enum variable that corresponds to m68k_symbolic_call values. */ | |
492 | enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; | |
493 | ||
900ec02d | 494 | \f |
c5387660 | 495 | /* Implement TARGET_OPTION_OVERRIDE. */ |
ef1dbfb0 | 496 | |
c5387660 JM |
497 | static void |
498 | m68k_option_override (void) | |
ef1dbfb0 | 499 | { |
900ec02d JB |
500 | const struct m68k_target_selection *entry; |
501 | unsigned long target_mask; | |
502 | ||
00f34291 | 503 | if (OPTION_SET_P (m68k_arch_option)) |
47c94d21 JM |
504 | m68k_arch_entry = &all_isas[m68k_arch_option]; |
505 | ||
00f34291 | 506 | if (OPTION_SET_P (m68k_cpu_option)) |
47c94d21 JM |
507 | m68k_cpu_entry = &all_devices[(int) m68k_cpu_option]; |
508 | ||
00f34291 | 509 | if (OPTION_SET_P (m68k_tune_option)) |
47c94d21 JM |
510 | m68k_tune_entry = &all_microarchs[(int) m68k_tune_option]; |
511 | ||
900ec02d JB |
512 | /* User can choose: |
513 | ||
514 | -mcpu= | |
515 | -march= | |
516 | -mtune= | |
517 | ||
518 | -march=ARCH should generate code that runs any processor | |
519 | implementing architecture ARCH. -mcpu=CPU should override -march | |
520 | and should generate code that runs on processor CPU, making free | |
521 | use of any instructions that CPU understands. -mtune=UARCH applies | |
9f5ed61a | 522 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
900ec02d JB |
523 | not change the target architecture. */ |
524 | if (m68k_cpu_entry) | |
525 | { | |
526 | /* Complain if the -march setting is for a different microarchitecture, | |
527 | or includes flags that the -mcpu setting doesn't. */ | |
528 | if (m68k_arch_entry | |
529 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
530 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
a3f9f006 | 531 | warning (0, "%<-mcpu=%s%> conflicts with %<-march=%s%>", |
900ec02d JB |
532 | m68k_cpu_entry->name, m68k_arch_entry->name); |
533 | ||
534 | entry = m68k_cpu_entry; | |
535 | } | |
536 | else | |
537 | entry = m68k_arch_entry; | |
538 | ||
539 | if (!entry) | |
540 | entry = all_devices + TARGET_CPU_DEFAULT; | |
541 | ||
542 | m68k_cpu_flags = entry->flags; | |
543 | ||
544 | /* Use the architecture setting to derive default values for | |
545 | certain flags. */ | |
546 | target_mask = 0; | |
8785d88c KH |
547 | |
548 | /* ColdFire is lenient about alignment. */ | |
549 | if (!TARGET_COLDFIRE) | |
550 | target_mask |= MASK_STRICT_ALIGNMENT; | |
551 | ||
900ec02d JB |
552 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) |
553 | target_mask |= MASK_BITFIELD; | |
554 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
555 | target_mask |= MASK_CF_HWDIV; | |
556 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
557 | target_mask |= MASK_HARD_FLOAT; | |
558 | target_flags |= target_mask & ~target_flags_explicit; | |
559 | ||
560 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
561 | m68k_cpu = entry->device; | |
562 | if (m68k_tune_entry) | |
03b3e271 KH |
563 | { |
564 | m68k_tune = m68k_tune_entry->microarch; | |
565 | m68k_tune_flags = m68k_tune_entry->flags; | |
566 | } | |
900ec02d JB |
567 | #ifdef M68K_DEFAULT_TUNE |
568 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
03b3e271 KH |
569 | { |
570 | enum target_device dev; | |
571 | dev = all_microarchs[M68K_DEFAULT_TUNE].device; | |
3b891d26 | 572 | m68k_tune_flags = all_devices[dev].flags; |
03b3e271 | 573 | } |
900ec02d JB |
574 | #endif |
575 | else | |
03b3e271 KH |
576 | { |
577 | m68k_tune = entry->microarch; | |
578 | m68k_tune_flags = entry->flags; | |
579 | } | |
900ec02d JB |
580 | |
581 | /* Set the type of FPU. */ | |
582 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
583 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
584 | : FPUTYPE_68881); | |
585 | ||
a2ef3db7 BI |
586 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
587 | * both specified together. Doing so simply doesn't make sense. | |
588 | */ | |
589 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
a3f9f006 | 590 | error ("cannot specify both %<-msep-data%> and %<-mid-shared-library%>"); |
a2ef3db7 BI |
591 | |
592 | /* If we're generating code for a separate A5 relative data segment, | |
593 | * we've got to enable -fPIC as well. This might be relaxable to | |
594 | * -fpic but it hasn't been tested properly. | |
595 | */ | |
596 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
597 | flag_pic = 2; | |
598 | ||
abe92a04 RS |
599 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
600 | error if the target does not support them. */ | |
601 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
a3f9f006 | 602 | error ("%<-mpcrel%> %<-fPIC%> is not currently supported on selected cpu"); |
adf2ac37 RH |
603 | |
604 | /* ??? A historic way of turning on pic, or is this intended to | |
605 | be an embedded thing that doesn't have the same name binding | |
606 | significance that it does on hosted ELF systems? */ | |
607 | if (TARGET_PCREL && flag_pic == 0) | |
608 | flag_pic = 1; | |
609 | ||
29ca003a RS |
610 | if (!flag_pic) |
611 | { | |
c47b0cb4 MK |
612 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR; |
613 | ||
29ca003a | 614 | m68k_symbolic_jump = "jra %a0"; |
29ca003a RS |
615 | } |
616 | else if (TARGET_ID_SHARED_LIBRARY) | |
617 | /* All addresses must be loaded from the GOT. */ | |
618 | ; | |
4e2b26aa | 619 | else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) |
29ca003a RS |
620 | { |
621 | if (TARGET_PCREL) | |
c47b0cb4 | 622 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C; |
4e2b26aa | 623 | else |
c47b0cb4 MK |
624 | m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P; |
625 | ||
4e2b26aa NS |
626 | if (TARGET_ISAC) |
627 | /* No unconditional long branch */; | |
628 | else if (TARGET_PCREL) | |
da398bb5 | 629 | m68k_symbolic_jump = "bra%.l %c0"; |
29ca003a | 630 | else |
da398bb5 | 631 | m68k_symbolic_jump = "bra%.l %p0"; |
29ca003a RS |
632 | /* Turn off function cse if we are doing PIC. We always want |
633 | function call to be done as `bsr foo@PLTPC'. */ | |
634 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
635 | clear how intentional that is. */ | |
636 | flag_no_function_cse = 1; | |
637 | } | |
adf2ac37 | 638 | |
c47b0cb4 MK |
639 | switch (m68k_symbolic_call_var) |
640 | { | |
641 | case M68K_SYMBOLIC_CALL_JSR: | |
c47b0cb4 | 642 | m68k_symbolic_call = "jsr %a0"; |
c47b0cb4 MK |
643 | break; |
644 | ||
645 | case M68K_SYMBOLIC_CALL_BSR_C: | |
da398bb5 | 646 | m68k_symbolic_call = "bsr%.l %c0"; |
c47b0cb4 MK |
647 | break; |
648 | ||
649 | case M68K_SYMBOLIC_CALL_BSR_P: | |
da398bb5 | 650 | m68k_symbolic_call = "bsr%.l %p0"; |
c47b0cb4 MK |
651 | break; |
652 | ||
653 | case M68K_SYMBOLIC_CALL_NONE: | |
654 | gcc_assert (m68k_symbolic_call == NULL); | |
655 | break; | |
656 | ||
657 | default: | |
658 | gcc_unreachable (); | |
659 | } | |
660 | ||
aaca7021 | 661 | #ifndef ASM_OUTPUT_ALIGN_WITH_NOP |
c518c102 | 662 | parse_alignment_opts (); |
e6de5335 ML |
663 | int label_alignment = align_labels.levels[0].get_value (); |
664 | if (label_alignment > 2) | |
aaca7021 | 665 | { |
a3f9f006 | 666 | warning (0, "%<-falign-labels=%d%> is not supported", label_alignment); |
c518c102 | 667 | str_align_labels = "1"; |
aaca7021 | 668 | } |
c518c102 | 669 | |
e6de5335 ML |
670 | int loop_alignment = align_loops.levels[0].get_value (); |
671 | if (loop_alignment > 2) | |
aaca7021 | 672 | { |
a3f9f006 | 673 | warning (0, "%<-falign-loops=%d%> is not supported", loop_alignment); |
c518c102 | 674 | str_align_loops = "1"; |
aaca7021 RZ |
675 | } |
676 | #endif | |
677 | ||
253abb2a AS |
678 | if ((opt_fstack_limit_symbol_arg != NULL || opt_fstack_limit_register_no >= 0) |
679 | && !TARGET_68020) | |
8e22f79f | 680 | { |
a3f9f006 | 681 | warning (0, "%<-fstack-limit-%> options are not supported on this cpu"); |
253abb2a AS |
682 | opt_fstack_limit_symbol_arg = NULL; |
683 | opt_fstack_limit_register_no = -1; | |
8e22f79f AS |
684 | } |
685 | ||
adf2ac37 | 686 | SUBTARGET_OVERRIDE_OPTIONS; |
c47b0cb4 MK |
687 | |
688 | /* Setup scheduling options. */ | |
826fadba MK |
689 | if (TUNE_CFV1) |
690 | m68k_sched_cpu = CPU_CFV1; | |
691 | else if (TUNE_CFV2) | |
692 | m68k_sched_cpu = CPU_CFV2; | |
693 | else if (TUNE_CFV3) | |
694 | m68k_sched_cpu = CPU_CFV3; | |
96fcacb7 MK |
695 | else if (TUNE_CFV4) |
696 | m68k_sched_cpu = CPU_CFV4; | |
c47b0cb4 MK |
697 | else |
698 | { | |
699 | m68k_sched_cpu = CPU_UNKNOWN; | |
700 | flag_schedule_insns = 0; | |
701 | flag_schedule_insns_after_reload = 0; | |
702 | flag_modulo_sched = 0; | |
1ee6eb01 | 703 | flag_live_range_shrinkage = 0; |
c47b0cb4 | 704 | } |
826fadba MK |
705 | |
706 | if (m68k_sched_cpu != CPU_UNKNOWN) | |
707 | { | |
708 | if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0) | |
709 | m68k_sched_mac = MAC_CF_EMAC; | |
710 | else if ((m68k_cpu_flags & FL_CF_MAC) != 0) | |
711 | m68k_sched_mac = MAC_CF_MAC; | |
712 | else | |
713 | m68k_sched_mac = MAC_NO; | |
714 | } | |
ef1dbfb0 | 715 | } |
7eb4f044 | 716 | |
03e69b12 MP |
717 | /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */ |
718 | ||
719 | static void | |
720 | m68k_override_options_after_change (void) | |
721 | { | |
722 | if (m68k_sched_cpu == CPU_UNKNOWN) | |
723 | { | |
724 | flag_schedule_insns = 0; | |
725 | flag_schedule_insns_after_reload = 0; | |
726 | flag_modulo_sched = 0; | |
1ee6eb01 | 727 | flag_live_range_shrinkage = 0; |
03e69b12 MP |
728 | } |
729 | } | |
730 | ||
7eb4f044 NS |
731 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the |
732 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
733 | if -mcpu was not passed. */ | |
734 | ||
735 | const char * | |
736 | m68k_cpp_cpu_ident (const char *prefix) | |
737 | { | |
738 | if (!m68k_cpu_entry) | |
739 | return NULL; | |
740 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
741 | } | |
742 | ||
743 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
744 | given argument and NAME is the name of the representative device for | |
745 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
746 | ||
747 | const char * | |
748 | m68k_cpp_cpu_family (const char *prefix) | |
749 | { | |
750 | if (!m68k_cpu_entry) | |
751 | return NULL; | |
752 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
753 | } | |
79e68feb | 754 | \f |
2bccb817 KH |
755 | /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or |
756 | "interrupt_handler" attribute and interrupt_thread if FUNC has an | |
757 | "interrupt_thread" attribute. Otherwise, return | |
758 | m68k_fk_normal_function. */ | |
a4242737 KH |
759 | |
760 | enum m68k_function_kind | |
761 | m68k_get_function_kind (tree func) | |
48ed72a4 PB |
762 | { |
763 | tree a; | |
764 | ||
fa157b28 NS |
765 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
766 | ||
2bccb817 KH |
767 | a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); |
768 | if (a != NULL_TREE) | |
769 | return m68k_fk_interrupt_handler; | |
770 | ||
48ed72a4 | 771 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
a4242737 KH |
772 | if (a != NULL_TREE) |
773 | return m68k_fk_interrupt_handler; | |
774 | ||
775 | a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); | |
776 | if (a != NULL_TREE) | |
777 | return m68k_fk_interrupt_thread; | |
778 | ||
779 | return m68k_fk_normal_function; | |
48ed72a4 PB |
780 | } |
781 | ||
782 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
783 | struct attribute_spec.handler. */ | |
784 | static tree | |
785 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
786 | tree args ATTRIBUTE_UNUSED, | |
787 | int flags ATTRIBUTE_UNUSED, | |
788 | bool *no_add_attrs) | |
789 | { | |
790 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
791 | { | |
29d08eba JM |
792 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
793 | name); | |
48ed72a4 PB |
794 | *no_add_attrs = true; |
795 | } | |
796 | ||
a4242737 KH |
797 | if (m68k_get_function_kind (*node) != m68k_fk_normal_function) |
798 | { | |
799 | error ("multiple interrupt attributes not allowed"); | |
800 | *no_add_attrs = true; | |
801 | } | |
802 | ||
803 | if (!TARGET_FIDOA | |
804 | && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) | |
805 | { | |
806 | error ("interrupt_thread is available only on fido"); | |
807 | *no_add_attrs = true; | |
808 | } | |
809 | ||
48ed72a4 PB |
810 | return NULL_TREE; |
811 | } | |
860c4900 BI |
812 | |
813 | static void | |
3d74bc09 | 814 | m68k_compute_frame_layout (void) |
860c4900 BI |
815 | { |
816 | int regno, saved; | |
a40ed0f3 | 817 | unsigned int mask; |
a4242737 KH |
818 | enum m68k_function_kind func_kind = |
819 | m68k_get_function_kind (current_function_decl); | |
820 | bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; | |
821 | bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; | |
860c4900 | 822 | |
3d74bc09 BI |
823 | /* Only compute the frame once per function. |
824 | Don't cache information until reload has been completed. */ | |
825 | if (current_frame.funcdef_no == current_function_funcdef_no | |
826 | && reload_completed) | |
827 | return; | |
828 | ||
829 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 | 830 | |
a40ed0f3 | 831 | mask = saved = 0; |
a4242737 KH |
832 | |
833 | /* Interrupt thread does not need to save any register. */ | |
834 | if (!interrupt_thread) | |
835 | for (regno = 0; regno < 16; regno++) | |
836 | if (m68k_save_reg (regno, interrupt_handler)) | |
837 | { | |
838 | mask |= 1 << (regno - D0_REG); | |
839 | saved++; | |
840 | } | |
3d74bc09 BI |
841 | current_frame.offset = saved * 4; |
842 | current_frame.reg_no = saved; | |
843 | current_frame.reg_mask = mask; | |
860c4900 | 844 | |
57047680 | 845 | current_frame.foffset = 0; |
a40ed0f3 | 846 | mask = saved = 0; |
dcc21c4c | 847 | if (TARGET_HARD_FLOAT) |
860c4900 | 848 | { |
a4242737 KH |
849 | /* Interrupt thread does not need to save any register. */ |
850 | if (!interrupt_thread) | |
851 | for (regno = 16; regno < 24; regno++) | |
852 | if (m68k_save_reg (regno, interrupt_handler)) | |
853 | { | |
854 | mask |= 1 << (regno - FP0_REG); | |
855 | saved++; | |
856 | } | |
dcc21c4c | 857 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 858 | current_frame.offset += current_frame.foffset; |
860c4900 | 859 | } |
57047680 GN |
860 | current_frame.fpu_no = saved; |
861 | current_frame.fpu_mask = mask; | |
3d74bc09 BI |
862 | |
863 | /* Remember what function this frame refers to. */ | |
864 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
865 | } |
866 | ||
7b5cbb57 AS |
867 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
868 | ||
869 | bool | |
870 | m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
871 | { | |
872 | return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); | |
873 | } | |
874 | ||
860c4900 BI |
875 | HOST_WIDE_INT |
876 | m68k_initial_elimination_offset (int from, int to) | |
877 | { | |
42b67c06 PB |
878 | int argptr_offset; |
879 | /* The arg pointer points 8 bytes before the start of the arguments, | |
880 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
881 | frame pointer in most frames. */ | |
882 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 883 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 884 | return argptr_offset; |
860c4900 | 885 | |
3d74bc09 | 886 | m68k_compute_frame_layout (); |
860c4900 | 887 | |
4761e388 NS |
888 | gcc_assert (to == STACK_POINTER_REGNUM); |
889 | switch (from) | |
890 | { | |
a0a7fbc9 | 891 | case ARG_POINTER_REGNUM: |
42b67c06 | 892 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
893 | case FRAME_POINTER_REGNUM: |
894 | return current_frame.offset + current_frame.size; | |
895 | default: | |
896 | gcc_unreachable (); | |
897 | } | |
860c4900 BI |
898 | } |
899 | ||
97c55091 GN |
900 | /* Refer to the array `regs_ever_live' to determine which registers |
901 | to save; `regs_ever_live[I]' is nonzero if register number I | |
902 | is ever used in the function. This function is responsible for | |
903 | knowing which registers should not be saved even if used. | |
904 | Return true if we need to save REGNO. */ | |
905 | ||
48ed72a4 PB |
906 | static bool |
907 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 908 | { |
4ab870f5 | 909 | if (flag_pic && regno == PIC_REG) |
b86ba8a3 | 910 | { |
e3b5732b | 911 | if (crtl->saves_all_registers) |
afcb440c | 912 | return true; |
e3b5732b | 913 | if (crtl->uses_pic_offset_table) |
b86ba8a3 | 914 | return true; |
6357eb0d RS |
915 | /* Reload may introduce constant pool references into a function |
916 | that thitherto didn't need a PIC register. Note that the test | |
917 | above will not catch that case because we will only set | |
e3b5732b | 918 | crtl->uses_pic_offset_table when emitting |
6357eb0d | 919 | the address reloads. */ |
e3b5732b | 920 | if (crtl->uses_const_pool) |
6357eb0d | 921 | return true; |
b86ba8a3 | 922 | } |
2cff4a6e | 923 | |
e3b5732b | 924 | if (crtl->calls_eh_return) |
2cff4a6e AS |
925 | { |
926 | unsigned int i; | |
927 | for (i = 0; ; i++) | |
928 | { | |
929 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
930 | if (test == INVALID_REGNUM) | |
931 | break; | |
932 | if (test == regno) | |
48ed72a4 | 933 | return true; |
2cff4a6e AS |
934 | } |
935 | } | |
936 | ||
48ed72a4 PB |
937 | /* Fixed regs we never touch. */ |
938 | if (fixed_regs[regno]) | |
939 | return false; | |
940 | ||
941 | /* The frame pointer (if it is such) is handled specially. */ | |
942 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
943 | return false; | |
944 | ||
945 | /* Interrupt handlers must also save call_used_regs | |
946 | if they are live or when calling nested functions. */ | |
947 | if (interrupt_handler) | |
a0a7fbc9 | 948 | { |
6fb5fa3c | 949 | if (df_regs_ever_live_p (regno)) |
a0a7fbc9 | 950 | return true; |
48ed72a4 | 951 | |
a365fa06 | 952 | if (!crtl->is_leaf && call_used_or_fixed_reg_p (regno)) |
a0a7fbc9 AS |
953 | return true; |
954 | } | |
48ed72a4 PB |
955 | |
956 | /* Never need to save registers that aren't touched. */ | |
6fb5fa3c | 957 | if (!df_regs_ever_live_p (regno)) |
48ed72a4 PB |
958 | return false; |
959 | ||
b2e08ed4 | 960 | /* Otherwise save everything that isn't call-clobbered. */ |
a365fa06 | 961 | return !call_used_or_fixed_reg_p (regno); |
2cff4a6e AS |
962 | } |
963 | ||
a40ed0f3 KH |
964 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
965 | the lowest memory address. COUNT is the number of registers to be | |
966 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
967 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
968 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
969 | (if !STORE_P) operation. */ | |
970 | ||
c85e862a | 971 | static rtx_insn * |
a40ed0f3 KH |
972 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, |
973 | unsigned int count, unsigned int regno, | |
974 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
975 | { | |
976 | int i; | |
977 | rtx body, addr, src, operands[2]; | |
ef4bddc2 | 978 | machine_mode mode; |
a40ed0f3 KH |
979 | |
980 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
981 | mode = reg_raw_mode[regno]; | |
982 | i = 0; | |
983 | ||
984 | if (adjust_stack_p) | |
985 | { | |
0a81f074 RS |
986 | src = plus_constant (Pmode, base, |
987 | (count | |
988 | * GET_MODE_SIZE (mode) | |
989 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
f7df4a84 | 990 | XVECEXP (body, 0, i++) = gen_rtx_SET (base, src); |
a40ed0f3 KH |
991 | } |
992 | ||
993 | for (; mask != 0; mask >>= 1, regno++) | |
994 | if (mask & 1) | |
995 | { | |
0a81f074 | 996 | addr = plus_constant (Pmode, base, offset); |
a40ed0f3 KH |
997 | operands[!store_p] = gen_frame_mem (mode, addr); |
998 | operands[store_p] = gen_rtx_REG (mode, regno); | |
999 | XVECEXP (body, 0, i++) | |
f7df4a84 | 1000 | = gen_rtx_SET (operands[0], operands[1]); |
a40ed0f3 KH |
1001 | offset += GET_MODE_SIZE (mode); |
1002 | } | |
1003 | gcc_assert (i == XVECLEN (body, 0)); | |
1004 | ||
1005 | return emit_insn (body); | |
1006 | } | |
1007 | ||
1008 | /* Make INSN a frame-related instruction. */ | |
79e68feb | 1009 | |
08c148a8 | 1010 | static void |
c85e862a | 1011 | m68k_set_frame_related (rtx_insn *insn) |
a40ed0f3 KH |
1012 | { |
1013 | rtx body; | |
1014 | int i; | |
1015 | ||
1016 | RTX_FRAME_RELATED_P (insn) = 1; | |
1017 | body = PATTERN (insn); | |
1018 | if (GET_CODE (body) == PARALLEL) | |
1019 | for (i = 0; i < XVECLEN (body, 0); i++) | |
1020 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
1021 | } | |
1022 | ||
1023 | /* Emit RTL for the "prologue" define_expand. */ | |
1024 | ||
1025 | void | |
1026 | m68k_expand_prologue (void) | |
79e68feb | 1027 | { |
860c4900 | 1028 | HOST_WIDE_INT fsize_with_regs; |
2dc8bd76 | 1029 | rtx limit, src, dest; |
3d74bc09 | 1030 | |
a40ed0f3 | 1031 | m68k_compute_frame_layout (); |
3d74bc09 | 1032 | |
a11e0df4 | 1033 | if (flag_stack_usage_info) |
f69ea688 AS |
1034 | current_function_static_stack_size |
1035 | = current_frame.size + current_frame.offset; | |
1036 | ||
a157febd GK |
1037 | /* If the stack limit is a symbol, we can check it here, |
1038 | before actually allocating the space. */ | |
e3b5732b | 1039 | if (crtl->limit_stack |
a157febd | 1040 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) |
a40ed0f3 | 1041 | { |
0a81f074 | 1042 | limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4); |
1a627b35 | 1043 | if (!m68k_legitimate_constant_p (Pmode, limit)) |
a40ed0f3 KH |
1044 | { |
1045 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
1046 | limit = gen_rtx_REG (Pmode, D0_REG); | |
1047 | } | |
f90b7a5a PB |
1048 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, |
1049 | stack_pointer_rtx, limit), | |
1050 | stack_pointer_rtx, limit, | |
1051 | const1_rtx)); | |
a40ed0f3 | 1052 | } |
79e68feb | 1053 | |
a89e3f21 | 1054 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
1055 | if (TARGET_COLDFIRE) |
1056 | { | |
a40ed0f3 KH |
1057 | /* ColdFire's move multiple instructions do not allow pre-decrement |
1058 | addressing. Add the size of movem saves to the initial stack | |
1059 | allocation instead. */ | |
1060 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1061 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1062 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1063 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1064 | } |
860c4900 | 1065 | |
79e68feb RS |
1066 | if (frame_pointer_needed) |
1067 | { | |
a40ed0f3 | 1068 | if (fsize_with_regs == 0 && TUNE_68040) |
79e68feb | 1069 | { |
a40ed0f3 KH |
1070 | /* On the 68040, two separate moves are faster than link.w 0. */ |
1071 | dest = gen_frame_mem (Pmode, | |
1072 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1073 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
1074 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
1075 | stack_pointer_rtx)); | |
79e68feb | 1076 | } |
a40ed0f3 KH |
1077 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
1078 | m68k_set_frame_related | |
1079 | (emit_insn (gen_link (frame_pointer_rtx, | |
1080 | GEN_INT (-4 - fsize_with_regs)))); | |
d9e88af0 | 1081 | else |
a40ed0f3 KH |
1082 | { |
1083 | m68k_set_frame_related | |
1084 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
1085 | m68k_set_frame_related | |
1086 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1087 | stack_pointer_rtx, | |
1088 | GEN_INT (-fsize_with_regs)))); | |
1089 | } | |
96fcacb7 MK |
1090 | |
1091 | /* If the frame pointer is needed, emit a special barrier that | |
1092 | will prevent the scheduler from moving stores to the frame | |
1093 | before the stack adjustment. */ | |
1094 | emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx)); | |
d9e88af0 | 1095 | } |
a40ed0f3 KH |
1096 | else if (fsize_with_regs != 0) |
1097 | m68k_set_frame_related | |
1098 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1099 | stack_pointer_rtx, | |
1100 | GEN_INT (-fsize_with_regs)))); | |
860c4900 | 1101 | |
57047680 | 1102 | if (current_frame.fpu_mask) |
79e68feb | 1103 | { |
a40ed0f3 | 1104 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
dcc21c4c | 1105 | if (TARGET_68881) |
a40ed0f3 KH |
1106 | m68k_set_frame_related |
1107 | (m68k_emit_movem (stack_pointer_rtx, | |
1108 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
1109 | current_frame.fpu_no, FP0_REG, | |
1110 | current_frame.fpu_mask, true, true)); | |
dcc21c4c PB |
1111 | else |
1112 | { | |
1113 | int offset; | |
1114 | ||
a40ed0f3 KH |
1115 | /* If we're using moveml to save the integer registers, |
1116 | the stack pointer will point to the bottom of the moveml | |
1117 | save area. Find the stack offset of the first FP register. */ | |
1118 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1119 | offset = 0; |
1120 | else | |
a40ed0f3 KH |
1121 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1122 | m68k_set_frame_related | |
1123 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
1124 | current_frame.fpu_no, FP0_REG, | |
1125 | current_frame.fpu_mask, true, false)); | |
f277471f | 1126 | } |
79e68feb | 1127 | } |
99df2465 | 1128 | |
01bbf777 | 1129 | /* If the stack limit is not a symbol, check it here. |
a157febd | 1130 | This has the disadvantage that it may be too late... */ |
e3b5732b | 1131 | if (crtl->limit_stack) |
a157febd GK |
1132 | { |
1133 | if (REG_P (stack_limit_rtx)) | |
f90b7a5a PB |
1134 | emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx, |
1135 | stack_limit_rtx), | |
1136 | stack_pointer_rtx, stack_limit_rtx, | |
1137 | const1_rtx)); | |
1138 | ||
a157febd | 1139 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 1140 | warning (0, "stack limit expression is not supported"); |
a157febd | 1141 | } |
01bbf777 | 1142 | |
a40ed0f3 | 1143 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
79e68feb | 1144 | { |
a40ed0f3 | 1145 | /* Store each register separately in the same order moveml does. */ |
79e68feb RS |
1146 | int i; |
1147 | ||
a40ed0f3 KH |
1148 | for (i = 16; i-- > 0; ) |
1149 | if (current_frame.reg_mask & (1 << i)) | |
078e983e | 1150 | { |
a40ed0f3 KH |
1151 | src = gen_rtx_REG (SImode, D0_REG + i); |
1152 | dest = gen_frame_mem (SImode, | |
1153 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1154 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
078e983e | 1155 | } |
79e68feb | 1156 | } |
a40ed0f3 | 1157 | else |
79e68feb | 1158 | { |
9425fb04 | 1159 | if (TARGET_COLDFIRE) |
a40ed0f3 KH |
1160 | /* The required register save space has already been allocated. |
1161 | The first register should be stored at (%sp). */ | |
1162 | m68k_set_frame_related | |
1163 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
1164 | current_frame.reg_no, D0_REG, | |
1165 | current_frame.reg_mask, true, false)); | |
afaff477 | 1166 | else |
a40ed0f3 KH |
1167 | m68k_set_frame_related |
1168 | (m68k_emit_movem (stack_pointer_rtx, | |
1169 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1170 | current_frame.reg_no, D0_REG, | |
1171 | current_frame.reg_mask, true, true)); | |
79e68feb | 1172 | } |
a40ed0f3 | 1173 | |
75df395f | 1174 | if (!TARGET_SEP_DATA |
e3b5732b | 1175 | && crtl->uses_pic_offset_table) |
2dc8bd76 | 1176 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
79e68feb RS |
1177 | } |
1178 | \f | |
413ac1b2 RS |
1179 | /* Return true if a simple (return) instruction is sufficient for this |
1180 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1181 | |
3d74bc09 | 1182 | bool |
a2bda628 | 1183 | m68k_use_return_insn (void) |
79e68feb | 1184 | { |
79e68feb | 1185 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1186 | return false; |
125ed86f | 1187 | |
a0a7fbc9 | 1188 | m68k_compute_frame_layout (); |
413ac1b2 | 1189 | return current_frame.offset == 0; |
79e68feb RS |
1190 | } |
1191 | ||
f7e70894 RS |
1192 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1193 | SIBCALL_P says which. | |
79e68feb RS |
1194 | |
1195 | The function epilogue should not depend on the current stack pointer! | |
1196 | It should use the frame pointer only, if there is a frame pointer. | |
1197 | This is mandatory because of alloca; we also take advantage of it to | |
1198 | omit stack adjustments before returning. */ | |
1199 | ||
a40ed0f3 | 1200 | void |
f7e70894 | 1201 | m68k_expand_epilogue (bool sibcall_p) |
08c148a8 | 1202 | { |
3d74bc09 | 1203 | HOST_WIDE_INT fsize, fsize_with_regs; |
a40ed0f3 | 1204 | bool big, restore_from_sp; |
3d74bc09 | 1205 | |
a0a7fbc9 | 1206 | m68k_compute_frame_layout (); |
3d74bc09 | 1207 | |
3d74bc09 | 1208 | fsize = current_frame.size; |
a40ed0f3 KH |
1209 | big = false; |
1210 | restore_from_sp = false; | |
3d74bc09 | 1211 | |
416ff32e | 1212 | /* FIXME : crtl->is_leaf below is too strong. |
c67ddce5 | 1213 | What we really need to know there is if there could be pending |
7a1929e1 | 1214 | stack adjustment needed at that point. */ |
a40ed0f3 | 1215 | restore_from_sp = (!frame_pointer_needed |
416ff32e | 1216 | || (!cfun->calls_alloca && crtl->is_leaf)); |
860c4900 BI |
1217 | |
1218 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1219 | popping the frame. */ |
860c4900 | 1220 | fsize_with_regs = fsize; |
dcc21c4c PB |
1221 | if (TARGET_COLDFIRE && restore_from_sp) |
1222 | { | |
a40ed0f3 KH |
1223 | /* ColdFire's move multiple instructions do not allow post-increment |
1224 | addressing. Add the size of movem loads to the final deallocation | |
1225 | instead. */ | |
1226 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1227 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1228 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1229 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1230 | } |
860c4900 | 1231 | |
3d74bc09 | 1232 | if (current_frame.offset + fsize >= 0x8000 |
a40ed0f3 | 1233 | && !restore_from_sp |
3d74bc09 | 1234 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1235 | { |
a40ed0f3 KH |
1236 | if (TARGET_COLDFIRE |
1237 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1238 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1239 | { | |
1240 | /* ColdFire's move multiple instructions do not support the | |
1241 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1242 | stack-based restore. */ | |
1243 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1244 | GEN_INT (-(current_frame.offset + fsize))); | |
f2b6aad9 | 1245 | emit_insn (gen_blockage ()); |
a40ed0f3 KH |
1246 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1247 | gen_rtx_REG (Pmode, A1_REG), | |
1248 | frame_pointer_rtx)); | |
1249 | restore_from_sp = true; | |
1250 | } | |
1251 | else | |
1252 | { | |
1253 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1254 | fsize = 0; | |
1255 | big = true; | |
1256 | } | |
79e68feb | 1257 | } |
79e68feb | 1258 | |
a40ed0f3 KH |
1259 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1260 | { | |
1261 | /* Restore each register separately in the same order moveml does. */ | |
79e68feb | 1262 | int i; |
a40ed0f3 | 1263 | HOST_WIDE_INT offset; |
79e68feb | 1264 | |
a40ed0f3 | 1265 | offset = current_frame.offset + fsize; |
3d74bc09 BI |
1266 | for (i = 0; i < 16; i++) |
1267 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb | 1268 | { |
a40ed0f3 KH |
1269 | rtx addr; |
1270 | ||
1271 | if (big) | |
79e68feb | 1272 | { |
a40ed0f3 KH |
1273 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1274 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1275 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
0a81f074 | 1276 | addr = plus_constant (Pmode, addr, -offset); |
79e68feb | 1277 | } |
a40ed0f3 KH |
1278 | else if (restore_from_sp) |
1279 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1280 | else | |
0a81f074 | 1281 | addr = plus_constant (Pmode, frame_pointer_rtx, -offset); |
a40ed0f3 KH |
1282 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), |
1283 | gen_frame_mem (SImode, addr)); | |
1284 | offset -= GET_MODE_SIZE (SImode); | |
1285 | } | |
79e68feb | 1286 | } |
3d74bc09 | 1287 | else if (current_frame.reg_mask) |
79e68feb | 1288 | { |
a40ed0f3 KH |
1289 | if (big) |
1290 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1291 | gen_rtx_REG (Pmode, A1_REG), | |
1292 | frame_pointer_rtx), | |
1293 | -(current_frame.offset + fsize), | |
1294 | current_frame.reg_no, D0_REG, | |
1295 | current_frame.reg_mask, false, false); | |
1296 | else if (restore_from_sp) | |
1297 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1298 | current_frame.reg_no, D0_REG, | |
1299 | current_frame.reg_mask, false, | |
1300 | !TARGET_COLDFIRE); | |
1301 | else | |
1302 | m68k_emit_movem (frame_pointer_rtx, | |
1303 | -(current_frame.offset + fsize), | |
1304 | current_frame.reg_no, D0_REG, | |
1305 | current_frame.reg_mask, false, false); | |
79e68feb | 1306 | } |
a40ed0f3 KH |
1307 | |
1308 | if (current_frame.fpu_no > 0) | |
79e68feb RS |
1309 | { |
1310 | if (big) | |
a40ed0f3 KH |
1311 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1312 | gen_rtx_REG (Pmode, A1_REG), | |
1313 | frame_pointer_rtx), | |
1314 | -(current_frame.foffset + fsize), | |
1315 | current_frame.fpu_no, FP0_REG, | |
1316 | current_frame.fpu_mask, false, false); | |
6910dd70 | 1317 | else if (restore_from_sp) |
79e68feb | 1318 | { |
dcc21c4c PB |
1319 | if (TARGET_COLDFIRE) |
1320 | { | |
1321 | int offset; | |
1322 | ||
a40ed0f3 KH |
1323 | /* If we used moveml to restore the integer registers, the |
1324 | stack pointer will still point to the bottom of the moveml | |
1325 | save area. Find the stack offset of the first FP | |
1326 | register. */ | |
1327 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1328 | offset = 0; |
1329 | else | |
a40ed0f3 KH |
1330 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1331 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1332 | current_frame.fpu_no, FP0_REG, | |
1333 | current_frame.fpu_mask, false, false); | |
dcc21c4c | 1334 | } |
884b74f0 | 1335 | else |
a40ed0f3 KH |
1336 | m68k_emit_movem (stack_pointer_rtx, 0, |
1337 | current_frame.fpu_no, FP0_REG, | |
1338 | current_frame.fpu_mask, false, true); | |
79e68feb RS |
1339 | } |
1340 | else | |
a40ed0f3 KH |
1341 | m68k_emit_movem (frame_pointer_rtx, |
1342 | -(current_frame.foffset + fsize), | |
1343 | current_frame.fpu_no, FP0_REG, | |
1344 | current_frame.fpu_mask, false, false); | |
79e68feb | 1345 | } |
a40ed0f3 | 1346 | |
f2b6aad9 | 1347 | emit_insn (gen_blockage ()); |
79e68feb | 1348 | if (frame_pointer_needed) |
a40ed0f3 | 1349 | emit_insn (gen_unlink (frame_pointer_rtx)); |
860c4900 | 1350 | else if (fsize_with_regs) |
a40ed0f3 KH |
1351 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1352 | stack_pointer_rtx, | |
1353 | GEN_INT (fsize_with_regs))); | |
1354 | ||
e3b5732b | 1355 | if (crtl->calls_eh_return) |
a40ed0f3 KH |
1356 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1357 | stack_pointer_rtx, | |
1358 | EH_RETURN_STACKADJ_RTX)); | |
1359 | ||
f7e70894 | 1360 | if (!sibcall_p) |
3810076b | 1361 | emit_jump_insn (ret_rtx); |
79e68feb RS |
1362 | } |
1363 | \f | |
db5e2d51 MK |
1364 | /* Return true if PARALLEL contains register REGNO. */ |
1365 | static bool | |
1366 | m68k_reg_present_p (const_rtx parallel, unsigned int regno) | |
1367 | { | |
1368 | int i; | |
1369 | ||
1370 | if (REG_P (parallel) && REGNO (parallel) == regno) | |
1371 | return true; | |
1372 | ||
1373 | if (GET_CODE (parallel) != PARALLEL) | |
1374 | return false; | |
1375 | ||
1376 | for (i = 0; i < XVECLEN (parallel, 0); ++i) | |
1377 | { | |
1378 | const_rtx x; | |
1379 | ||
1380 | x = XEXP (XVECEXP (parallel, 0, i), 0); | |
1381 | if (REG_P (x) && REGNO (x) == regno) | |
1382 | return true; | |
1383 | } | |
1384 | ||
1385 | return false; | |
1386 | } | |
1387 | ||
fa157b28 | 1388 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ |
f7e70894 RS |
1389 | |
1390 | static bool | |
fa157b28 | 1391 | m68k_ok_for_sibcall_p (tree decl, tree exp) |
f7e70894 | 1392 | { |
fa157b28 NS |
1393 | enum m68k_function_kind kind; |
1394 | ||
1395 | /* We cannot use sibcalls for nested functions because we use the | |
1396 | static chain register for indirect calls. */ | |
1397 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1398 | return false; | |
1399 | ||
db5e2d51 MK |
1400 | if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) |
1401 | { | |
1402 | /* Check that the return value locations are the same. For | |
1403 | example that we aren't returning a value from the sibling in | |
1404 | a D0 register but then need to transfer it to a A0 register. */ | |
1405 | rtx cfun_value; | |
1406 | rtx call_value; | |
1407 | ||
1408 | cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)), | |
1409 | cfun->decl); | |
1410 | call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl); | |
1411 | ||
1412 | /* Check that the values are equal or that the result the callee | |
1413 | function returns is superset of what the current function returns. */ | |
1414 | if (!(rtx_equal_p (cfun_value, call_value) | |
1415 | || (REG_P (cfun_value) | |
1416 | && m68k_reg_present_p (call_value, REGNO (cfun_value))))) | |
1417 | return false; | |
1418 | } | |
1419 | ||
fa157b28 NS |
1420 | kind = m68k_get_function_kind (current_function_decl); |
1421 | if (kind == m68k_fk_normal_function) | |
1422 | /* We can always sibcall from a normal function, because it's | |
1423 | undefined if it is calling an interrupt function. */ | |
1424 | return true; | |
1425 | ||
1426 | /* Otherwise we can only sibcall if the function kind is known to be | |
1427 | the same. */ | |
1428 | if (decl && m68k_get_function_kind (decl) == kind) | |
1429 | return true; | |
1430 | ||
1431 | return false; | |
f7e70894 RS |
1432 | } |
1433 | ||
13d3961c NF |
1434 | /* On the m68k all args are always pushed. */ |
1435 | ||
1436 | static rtx | |
6783fdb7 | 1437 | m68k_function_arg (cumulative_args_t, const function_arg_info &) |
13d3961c NF |
1438 | { |
1439 | return NULL_RTX; | |
1440 | } | |
1441 | ||
1442 | static void | |
6930c98c RS |
1443 | m68k_function_arg_advance (cumulative_args_t cum_v, |
1444 | const function_arg_info &arg) | |
13d3961c | 1445 | { |
d5cc9181 JR |
1446 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1447 | ||
6930c98c | 1448 | *cum += (arg.promoted_size_in_bytes () + 3) & ~3; |
13d3961c NF |
1449 | } |
1450 | ||
29ca003a RS |
1451 | /* Convert X to a legitimate function call memory reference and return the |
1452 | result. */ | |
a2ef3db7 | 1453 | |
29ca003a RS |
1454 | rtx |
1455 | m68k_legitimize_call_address (rtx x) | |
1456 | { | |
1457 | gcc_assert (MEM_P (x)); | |
1458 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1459 | return x; | |
1460 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1461 | } |
1462 | ||
f7e70894 RS |
1463 | /* Likewise for sibling calls. */ |
1464 | ||
1465 | rtx | |
1466 | m68k_legitimize_sibcall_address (rtx x) | |
1467 | { | |
1468 | gcc_assert (MEM_P (x)); | |
1469 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1470 | return x; | |
1471 | ||
1472 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1473 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1474 | } | |
1475 | ||
506d7b68 PB |
1476 | /* Convert X to a legitimate address and return it if successful. Otherwise |
1477 | return X. | |
1478 | ||
1479 | For the 68000, we handle X+REG by loading X into a register R and | |
1480 | using R+REG. R will go in an address reg and indexing will be used. | |
1481 | However, if REG is a broken-out memory address or multiplication, | |
1482 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1483 | ||
ab7256e4 | 1484 | static rtx |
ef4bddc2 | 1485 | m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode) |
506d7b68 | 1486 | { |
75df395f MK |
1487 | if (m68k_tls_symbol_p (x)) |
1488 | return m68k_legitimize_tls_address (x); | |
1489 | ||
506d7b68 PB |
1490 | if (GET_CODE (x) == PLUS) |
1491 | { | |
1492 | int ch = (x) != (oldx); | |
1493 | int copied = 0; | |
1494 | ||
1495 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1496 | ||
1497 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
1498 | { | |
1499 | COPY_ONCE (x); | |
1500 | XEXP (x, 0) = force_operand (XEXP (x, 0), 0); | |
1501 | } | |
1502 | if (GET_CODE (XEXP (x, 1)) == MULT) | |
1503 | { | |
1504 | COPY_ONCE (x); | |
1505 | XEXP (x, 1) = force_operand (XEXP (x, 1), 0); | |
1506 | } | |
1507 | if (ch) | |
1508 | { | |
1509 | if (GET_CODE (XEXP (x, 1)) == REG | |
1510 | && GET_CODE (XEXP (x, 0)) == REG) | |
1511 | { | |
1512 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1513 | { | |
1514 | COPY_ONCE (x); | |
1515 | x = force_operand (x, 0); | |
1516 | } | |
1517 | return x; | |
1518 | } | |
1519 | if (memory_address_p (mode, x)) | |
1520 | return x; | |
1521 | } | |
1522 | if (GET_CODE (XEXP (x, 0)) == REG | |
1523 | || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
1524 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1525 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)) | |
1526 | { | |
1527 | rtx temp = gen_reg_rtx (Pmode); | |
1528 | rtx val = force_operand (XEXP (x, 1), 0); | |
1529 | emit_move_insn (temp, val); | |
1530 | COPY_ONCE (x); | |
1531 | XEXP (x, 1) = temp; | |
1532 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1533 | && GET_CODE (XEXP (x, 0)) == REG) | |
1534 | x = force_operand (x, 0); | |
1535 | } | |
1536 | else if (GET_CODE (XEXP (x, 1)) == REG | |
1537 | || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND | |
1538 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
1539 | && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode)) | |
1540 | { | |
1541 | rtx temp = gen_reg_rtx (Pmode); | |
1542 | rtx val = force_operand (XEXP (x, 0), 0); | |
1543 | emit_move_insn (temp, val); | |
1544 | COPY_ONCE (x); | |
1545 | XEXP (x, 0) = temp; | |
1546 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1547 | && GET_CODE (XEXP (x, 1)) == REG) | |
1548 | x = force_operand (x, 0); | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | return x; | |
1553 | } | |
6cebc6cb BS |
1554 | \f |
1555 | /* For eliding comparisons, we remember how the flags were set. | |
1556 | FLAGS_COMPARE_OP0 and FLAGS_COMPARE_OP1 are remembered for a direct | |
1557 | comparison, they take priority. FLAGS_OPERAND1 and FLAGS_OPERAND2 | |
1558 | are used in more cases, they are a fallback for comparisons against | |
1559 | zero after a move or arithmetic insn. | |
1560 | FLAGS_VALID is set to FLAGS_VALID_NO if we should not use any of | |
1561 | these values. */ | |
1562 | ||
1563 | static rtx flags_compare_op0, flags_compare_op1; | |
1564 | static rtx flags_operand1, flags_operand2; | |
1565 | static attr_flags_valid flags_valid = FLAGS_VALID_NO; | |
1566 | ||
1567 | /* Return a code other than UNKNOWN if we can elide a CODE comparison of | |
1568 | OP0 with OP1. */ | |
1569 | ||
1570 | rtx_code | |
1571 | m68k_find_flags_value (rtx op0, rtx op1, rtx_code code) | |
1572 | { | |
1573 | if (flags_compare_op0 != NULL_RTX) | |
1574 | { | |
1575 | if (rtx_equal_p (op0, flags_compare_op0) | |
1576 | && rtx_equal_p (op1, flags_compare_op1)) | |
1577 | return code; | |
1578 | if (rtx_equal_p (op0, flags_compare_op1) | |
1579 | && rtx_equal_p (op1, flags_compare_op0)) | |
1580 | return swap_condition (code); | |
1581 | return UNKNOWN; | |
1582 | } | |
1583 | ||
1584 | machine_mode mode = GET_MODE (op0); | |
1585 | if (op1 != CONST0_RTX (mode)) | |
1586 | return UNKNOWN; | |
1587 | /* Comparisons against 0 with these two should have been optimized out. */ | |
1588 | gcc_assert (code != LTU && code != GEU); | |
1589 | if (flags_valid == FLAGS_VALID_NOOV && (code == GT || code == LE)) | |
1590 | return UNKNOWN; | |
1591 | if (rtx_equal_p (flags_operand1, op0) || rtx_equal_p (flags_operand2, op0)) | |
1592 | return (FLOAT_MODE_P (mode) ? code | |
1593 | : code == GE ? PLUS : code == LT ? MINUS : code); | |
1594 | /* See if we are testing whether the high part of a DImode value is | |
1595 | positive or negative and we have the full value as a remembered | |
1596 | operand. */ | |
1597 | if (code != GE && code != LT) | |
1598 | return UNKNOWN; | |
1599 | if (mode == SImode | |
1600 | && flags_operand1 != NULL_RTX && GET_MODE (flags_operand1) == DImode | |
1601 | && REG_P (flags_operand1) && REG_P (op0) | |
1602 | && hard_regno_nregs (REGNO (flags_operand1), DImode) == 2 | |
1603 | && REGNO (flags_operand1) == REGNO (op0)) | |
1604 | return code == GE ? PLUS : MINUS; | |
1605 | if (mode == SImode | |
1606 | && flags_operand2 != NULL_RTX && GET_MODE (flags_operand2) == DImode | |
1607 | && REG_P (flags_operand2) && REG_P (op0) | |
1608 | && hard_regno_nregs (REGNO (flags_operand2), DImode) == 2 | |
1609 | && REGNO (flags_operand2) == REGNO (op0)) | |
1610 | return code == GE ? PLUS : MINUS; | |
1611 | return UNKNOWN; | |
1612 | } | |
1613 | ||
1614 | /* Called through CC_STATUS_INIT, which is invoked by final whenever a | |
1615 | label is encountered. */ | |
1616 | ||
1617 | void | |
1618 | m68k_init_cc () | |
1619 | { | |
1620 | flags_compare_op0 = flags_compare_op1 = NULL_RTX; | |
1621 | flags_operand1 = flags_operand2 = NULL_RTX; | |
1622 | flags_valid = FLAGS_VALID_NO; | |
1623 | } | |
1624 | ||
1625 | /* Update flags for a move operation with OPERANDS. Called for move | |
1626 | operations where attr_flags_valid returns "set". */ | |
1627 | ||
1628 | static void | |
1629 | handle_flags_for_move (rtx *operands) | |
1630 | { | |
1631 | flags_compare_op0 = flags_compare_op1 = NULL_RTX; | |
1632 | if (!ADDRESS_REG_P (operands[0])) | |
1633 | { | |
1634 | flags_valid = FLAGS_VALID_MOVE; | |
1635 | flags_operand1 = side_effects_p (operands[0]) ? NULL_RTX : operands[0]; | |
1636 | if (side_effects_p (operands[1]) | |
1637 | /* ??? For mem->mem moves, this can discard the source as a | |
1638 | valid compare operand. If you assume aligned moves, this | |
1639 | is unnecessary, but in theory, we could have an unaligned | |
1640 | move overwriting parts of its source. */ | |
1641 | || modified_in_p (operands[1], current_output_insn)) | |
1642 | flags_operand2 = NULL_RTX; | |
1643 | else | |
1644 | flags_operand2 = operands[1]; | |
1645 | return; | |
1646 | } | |
1647 | if (flags_operand1 != NULL_RTX | |
1648 | && modified_in_p (flags_operand1, current_output_insn)) | |
1649 | flags_operand1 = NULL_RTX; | |
1650 | if (flags_operand2 != NULL_RTX | |
1651 | && modified_in_p (flags_operand2, current_output_insn)) | |
1652 | flags_operand2 = NULL_RTX; | |
1653 | } | |
1654 | ||
1655 | /* Process INSN to remember flag operands if possible. */ | |
1656 | ||
1657 | static void | |
1658 | m68k_asm_final_postscan_insn (FILE *, rtx_insn *insn, rtx [], int) | |
1659 | { | |
1660 | enum attr_flags_valid v = get_attr_flags_valid (insn); | |
1661 | if (v == FLAGS_VALID_SET) | |
1662 | return; | |
1663 | /* Comparisons use FLAGS_VALID_SET, so we can be sure we need to clear these | |
1664 | now. */ | |
1665 | flags_compare_op0 = flags_compare_op1 = NULL_RTX; | |
1666 | ||
1667 | if (v == FLAGS_VALID_NO) | |
1668 | { | |
1669 | flags_operand1 = flags_operand2 = NULL_RTX; | |
1670 | return; | |
1671 | } | |
1672 | else if (v == FLAGS_VALID_UNCHANGED) | |
1673 | { | |
1674 | if (flags_operand1 != NULL_RTX && modified_in_p (flags_operand1, insn)) | |
1675 | flags_operand1 = NULL_RTX; | |
1676 | if (flags_operand2 != NULL_RTX && modified_in_p (flags_operand2, insn)) | |
1677 | flags_operand2 = NULL_RTX; | |
1678 | return; | |
1679 | } | |
1680 | ||
1681 | flags_valid = v; | |
1682 | rtx set = single_set (insn); | |
1683 | rtx dest = SET_DEST (set); | |
1684 | rtx src = SET_SRC (set); | |
1685 | if (side_effects_p (dest)) | |
1686 | dest = NULL_RTX; | |
1687 | ||
1688 | switch (v) | |
1689 | { | |
1690 | case FLAGS_VALID_YES: | |
1691 | case FLAGS_VALID_NOOV: | |
1692 | flags_operand1 = dest; | |
1693 | flags_operand2 = NULL_RTX; | |
1694 | break; | |
1695 | case FLAGS_VALID_MOVE: | |
1696 | /* fmoves to memory or data registers do not set the condition | |
1697 | codes. Normal moves _do_ set the condition codes, but not in | |
1698 | a way that is appropriate for comparison with 0, because -0.0 | |
1699 | would be treated as a negative nonzero number. Note that it | |
1700 | isn't appropriate to conditionalize this restriction on | |
1701 | HONOR_SIGNED_ZEROS because that macro merely indicates whether | |
1702 | we care about the difference between -0.0 and +0.0. */ | |
1703 | if (dest != NULL_RTX | |
1704 | && !FP_REG_P (dest) | |
1705 | && (FP_REG_P (src) | |
1706 | || GET_CODE (src) == FIX | |
1707 | || FLOAT_MODE_P (GET_MODE (dest)))) | |
1708 | flags_operand1 = flags_operand2 = NULL_RTX; | |
1709 | else | |
1710 | { | |
1711 | flags_operand1 = dest; | |
1712 | if (GET_MODE (src) != VOIDmode && !side_effects_p (src) | |
1713 | && !modified_in_p (src, insn)) | |
1714 | flags_operand2 = src; | |
1715 | else | |
1716 | flags_operand2 = NULL_RTX; | |
1717 | } | |
1718 | break; | |
1719 | default: | |
1720 | gcc_unreachable (); | |
1721 | } | |
1722 | return; | |
1723 | } | |
506d7b68 | 1724 | |
64a184e9 | 1725 | /* Output a dbCC; jCC sequence. Note we do not handle the |
6cebc6cb BS |
1726 | floating point version of this sequence (Fdbcc). |
1727 | OPERANDS are as in the two peepholes. CODE is the code | |
1728 | returned by m68k_output_branch_<mode>. */ | |
64a184e9 | 1729 | |
1d8eaa6b | 1730 | void |
6cebc6cb | 1731 | output_dbcc_and_branch (rtx *operands, rtx_code code) |
64a184e9 | 1732 | { |
6cebc6cb | 1733 | switch (code) |
64a184e9 RS |
1734 | { |
1735 | case EQ: | |
da398bb5 | 1736 | output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); |
e6d98cb0 | 1737 | break; |
64a184e9 RS |
1738 | |
1739 | case NE: | |
da398bb5 | 1740 | output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); |
e6d98cb0 | 1741 | break; |
64a184e9 RS |
1742 | |
1743 | case GT: | |
da398bb5 | 1744 | output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); |
e6d98cb0 | 1745 | break; |
64a184e9 RS |
1746 | |
1747 | case GTU: | |
da398bb5 | 1748 | output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); |
e6d98cb0 | 1749 | break; |
64a184e9 RS |
1750 | |
1751 | case LT: | |
da398bb5 | 1752 | output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); |
e6d98cb0 | 1753 | break; |
64a184e9 RS |
1754 | |
1755 | case LTU: | |
da398bb5 | 1756 | output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); |
e6d98cb0 | 1757 | break; |
64a184e9 RS |
1758 | |
1759 | case GE: | |
da398bb5 | 1760 | output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); |
e6d98cb0 | 1761 | break; |
64a184e9 RS |
1762 | |
1763 | case GEU: | |
da398bb5 | 1764 | output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); |
e6d98cb0 | 1765 | break; |
64a184e9 RS |
1766 | |
1767 | case LE: | |
da398bb5 | 1768 | output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); |
e6d98cb0 | 1769 | break; |
64a184e9 RS |
1770 | |
1771 | case LEU: | |
da398bb5 | 1772 | output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); |
e6d98cb0 | 1773 | break; |
64a184e9 | 1774 | |
6cebc6cb BS |
1775 | case PLUS: |
1776 | output_asm_insn ("dbpl %0,%l1\n\tjle %l2", operands); | |
1777 | break; | |
1778 | ||
1779 | case MINUS: | |
1780 | output_asm_insn ("dbmi %0,%l1\n\tjle %l2", operands); | |
1781 | break; | |
1782 | ||
64a184e9 | 1783 | default: |
4761e388 | 1784 | gcc_unreachable (); |
64a184e9 RS |
1785 | } |
1786 | ||
1787 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1788 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1789 | switch (GET_MODE (operands[0])) |
1790 | { | |
4e10a5a7 | 1791 | case E_SImode: |
da398bb5 | 1792 | output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands); |
64a184e9 RS |
1793 | break; |
1794 | ||
4e10a5a7 | 1795 | case E_HImode: |
64a184e9 RS |
1796 | break; |
1797 | ||
1798 | default: | |
4761e388 | 1799 | gcc_unreachable (); |
64a184e9 RS |
1800 | } |
1801 | } | |
1802 | ||
5505f548 | 1803 | const char * |
4761e388 | 1804 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1805 | { |
1806 | rtx loperands[7]; | |
d9832fd2 | 1807 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1808 | |
f710504c | 1809 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1810 | CC_STATUS_INIT; |
1811 | ||
d9832fd2 RK |
1812 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1813 | below. Swap the operands and change the op if these requirements | |
1814 | are not fulfilled. */ | |
1815 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1816 | { | |
1817 | rtx tmp = operand1; | |
1818 | ||
1819 | operand1 = operand2; | |
1820 | operand2 = tmp; | |
1821 | op_code = swap_condition (op_code); | |
1822 | } | |
c59c3b1c RK |
1823 | loperands[0] = operand1; |
1824 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1825 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1826 | else |
b72f00af | 1827 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1828 | if (operand2 != const0_rtx) |
1829 | { | |
1830 | loperands[2] = operand2; | |
1831 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1832 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1833 | else |
b72f00af | 1834 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1835 | } |
428511bb | 1836 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1837 | if (operand2 != const0_rtx) |
da398bb5 | 1838 | output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands); |
392582fa | 1839 | else |
4a8c52e0 | 1840 | { |
9425fb04 | 1841 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1842 | output_asm_insn ("tst%.l %0", loperands); |
1843 | else | |
a0a7fbc9 | 1844 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1845 | |
da398bb5 | 1846 | output_asm_insn ("jne %l4", loperands); |
4a8c52e0 | 1847 | |
9425fb04 | 1848 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1849 | output_asm_insn ("tst%.l %1", loperands); |
1850 | else | |
3b4b85c9 | 1851 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1852 | } |
1853 | ||
c59c3b1c | 1854 | loperands[5] = dest; |
3b4b85c9 | 1855 | |
d9832fd2 | 1856 | switch (op_code) |
c59c3b1c RK |
1857 | { |
1858 | case EQ: | |
4977bab6 | 1859 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1860 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1861 | output_asm_insn ("seq %5", loperands); |
1862 | break; | |
1863 | ||
1864 | case NE: | |
4977bab6 | 1865 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1866 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1867 | output_asm_insn ("sne %5", loperands); |
1868 | break; | |
1869 | ||
1870 | case GT: | |
428511bb | 1871 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1872 | output_asm_insn ("shi %5\n\tjra %l6", loperands); |
4977bab6 | 1873 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1874 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1875 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1876 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1877 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1878 | break; |
1879 | ||
1880 | case GTU: | |
4977bab6 | 1881 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1882 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1883 | output_asm_insn ("shi %5", loperands); |
1884 | break; | |
1885 | ||
1886 | case LT: | |
428511bb | 1887 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1888 | output_asm_insn ("scs %5\n\tjra %l6", loperands); |
4977bab6 | 1889 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1890 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1891 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1892 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1893 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1894 | break; |
1895 | ||
1896 | case LTU: | |
4977bab6 | 1897 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1898 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1899 | output_asm_insn ("scs %5", loperands); |
1900 | break; | |
1901 | ||
1902 | case GE: | |
428511bb | 1903 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1904 | output_asm_insn ("scc %5\n\tjra %l6", loperands); |
4977bab6 | 1905 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1906 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1907 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1908 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1909 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1910 | break; |
1911 | ||
1912 | case GEU: | |
4977bab6 | 1913 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1914 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1915 | output_asm_insn ("scc %5", loperands); |
1916 | break; | |
1917 | ||
1918 | case LE: | |
428511bb | 1919 | loperands[6] = gen_label_rtx (); |
da398bb5 | 1920 | output_asm_insn ("sls %5\n\tjra %l6", loperands); |
4977bab6 | 1921 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1922 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1923 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1924 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1925 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1926 | break; |
1927 | ||
1928 | case LEU: | |
4977bab6 | 1929 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1930 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1931 | output_asm_insn ("sls %5", loperands); |
1932 | break; | |
1933 | ||
1934 | default: | |
4761e388 | 1935 | gcc_unreachable (); |
c59c3b1c RK |
1936 | } |
1937 | return ""; | |
1938 | } | |
1939 | ||
6cebc6cb BS |
1940 | rtx_code |
1941 | m68k_output_btst (rtx countop, rtx dataop, rtx_code code, int signpos) | |
79e68feb | 1942 | { |
6cebc6cb BS |
1943 | rtx ops[2]; |
1944 | ops[0] = countop; | |
1945 | ops[1] = dataop; | |
79e68feb RS |
1946 | |
1947 | if (GET_CODE (countop) == CONST_INT) | |
1948 | { | |
fb43b412 | 1949 | int count = INTVAL (countop); |
79e68feb RS |
1950 | /* If COUNT is bigger than size of storage unit in use, |
1951 | advance to the containing unit of same size. */ | |
1952 | if (count > signpos) | |
1953 | { | |
1954 | int offset = (count & ~signpos) / 8; | |
1955 | count = count & signpos; | |
6cebc6cb BS |
1956 | ops[1] = dataop = adjust_address (dataop, QImode, offset); |
1957 | } | |
1958 | ||
1959 | if (code == EQ || code == NE) | |
1960 | { | |
1961 | if (count == 31) | |
1962 | { | |
1963 | output_asm_insn ("tst%.l %1", ops); | |
1964 | return code == EQ ? PLUS : MINUS; | |
1965 | } | |
1966 | if (count == 15) | |
1967 | { | |
1968 | output_asm_insn ("tst%.w %1", ops); | |
1969 | return code == EQ ? PLUS : MINUS; | |
1970 | } | |
1971 | if (count == 7) | |
1972 | { | |
1973 | output_asm_insn ("tst%.b %1", ops); | |
1974 | return code == EQ ? PLUS : MINUS; | |
1975 | } | |
79e68feb | 1976 | } |
5083912d PDM |
1977 | /* Try to use `movew to ccr' followed by the appropriate branch insn. |
1978 | On some m68k variants unfortunately that's slower than btst. | |
1979 | On 68000 and higher, that should also work for all HImode operands. */ | |
1980 | if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) | |
1981 | { | |
6cebc6cb | 1982 | if (count == 3 && DATA_REG_P (ops[1]) && (code == EQ || code == NE)) |
5083912d | 1983 | { |
6cebc6cb BS |
1984 | output_asm_insn ("move%.w %1,%%ccr", ops); |
1985 | return code == EQ ? PLUS : MINUS; | |
5083912d | 1986 | } |
6cebc6cb | 1987 | if (count == 2 && DATA_REG_P (ops[1]) && (code == EQ || code == NE)) |
5083912d | 1988 | { |
6cebc6cb BS |
1989 | output_asm_insn ("move%.w %1,%%ccr", ops); |
1990 | return code == EQ ? NE : EQ; | |
5083912d PDM |
1991 | } |
1992 | /* count == 1 followed by bvc/bvs and | |
1993 | count == 0 followed by bcc/bcs are also possible, but need | |
1994 | m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ | |
1995 | } | |
79e68feb | 1996 | } |
6cebc6cb BS |
1997 | output_asm_insn ("btst %0,%1", ops); |
1998 | return code; | |
1999 | } | |
2000 | ||
2001 | /* Output a bftst instruction for a zero_extract with ZXOP0, ZXOP1 and ZXOP2 | |
2002 | operands. CODE is the code of the comparison, and we return the code to | |
2003 | be actually used in the jump. */ | |
2004 | ||
2005 | rtx_code | |
2006 | m68k_output_bftst (rtx zxop0, rtx zxop1, rtx zxop2, rtx_code code) | |
2007 | { | |
2008 | if (zxop1 == const1_rtx && GET_CODE (zxop2) == CONST_INT) | |
2009 | { | |
2010 | int width = GET_CODE (zxop0) == REG ? 31 : 7; | |
2011 | /* Pass 1000 as SIGNPOS argument so that btst will | |
2012 | not think we are testing the sign bit for an `and' | |
2013 | and assume that nonzero implies a negative result. */ | |
2014 | return m68k_output_btst (GEN_INT (width - INTVAL (zxop2)), zxop0, code, 1000); | |
2015 | } | |
2016 | rtx ops[3] = { zxop0, zxop1, zxop2 }; | |
2017 | output_asm_insn ("bftst %0{%b2:%b1}", ops); | |
2018 | return code; | |
79e68feb | 2019 | } |
79e68feb | 2020 | \f |
fc2241eb RS |
2021 | /* Return true if X is a legitimate base register. STRICT_P says |
2022 | whether we need strict checking. */ | |
2023 | ||
2024 | bool | |
2025 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
2026 | { | |
2027 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
2028 | if (!strict_p && GET_CODE (x) == SUBREG) | |
2029 | x = SUBREG_REG (x); | |
2030 | ||
2031 | return (REG_P (x) | |
2032 | && (strict_p | |
2033 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
bf32249e | 2034 | : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
2035 | } |
2036 | ||
2037 | /* Return true if X is a legitimate index register. STRICT_P says | |
2038 | whether we need strict checking. */ | |
2039 | ||
2040 | bool | |
2041 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
2042 | { | |
2043 | if (!strict_p && GET_CODE (x) == SUBREG) | |
2044 | x = SUBREG_REG (x); | |
2045 | ||
2046 | return (REG_P (x) | |
2047 | && (strict_p | |
2048 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
bf32249e | 2049 | : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
2050 | } |
2051 | ||
2052 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
2053 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
2054 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
2055 | ||
2056 | static bool | |
2057 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
2058 | { | |
2059 | int scale; | |
2060 | ||
2061 | /* Check for a scale factor. */ | |
2062 | scale = 1; | |
2063 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
2064 | && GET_CODE (x) == MULT | |
2065 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2066 | && (INTVAL (XEXP (x, 1)) == 2 | |
2067 | || INTVAL (XEXP (x, 1)) == 4 | |
2068 | || (INTVAL (XEXP (x, 1)) == 8 | |
2069 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
2070 | { | |
2071 | scale = INTVAL (XEXP (x, 1)); | |
2072 | x = XEXP (x, 0); | |
2073 | } | |
2074 | ||
2075 | /* Check for a word extension. */ | |
2076 | if (!TARGET_COLDFIRE | |
2077 | && GET_CODE (x) == SIGN_EXTEND | |
2078 | && GET_MODE (XEXP (x, 0)) == HImode) | |
2079 | x = XEXP (x, 0); | |
2080 | ||
2081 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
2082 | { | |
2083 | address->scale = scale; | |
2084 | address->index = x; | |
2085 | return true; | |
2086 | } | |
2087 | ||
2088 | return false; | |
2089 | } | |
2090 | ||
7ffb5e78 RS |
2091 | /* Return true if X is an illegitimate symbolic constant. */ |
2092 | ||
2093 | bool | |
2094 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
2095 | { | |
2096 | rtx base, offset; | |
2097 | ||
2098 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
2099 | { | |
2100 | split_const (x, &base, &offset); | |
2101 | if (GET_CODE (base) == SYMBOL_REF | |
2102 | && !offset_within_block_p (base, INTVAL (offset))) | |
2103 | return true; | |
2104 | } | |
75df395f | 2105 | return m68k_tls_reference_p (x, false); |
7ffb5e78 RS |
2106 | } |
2107 | ||
fbbf66e7 RS |
2108 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
2109 | ||
2110 | static bool | |
ef4bddc2 | 2111 | m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
fbbf66e7 RS |
2112 | { |
2113 | return m68k_illegitimate_symbolic_constant_p (x); | |
2114 | } | |
2115 | ||
fc2241eb RS |
2116 | /* Return true if X is a legitimate constant address that can reach |
2117 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
2118 | strict checking. */ | |
2119 | ||
2120 | static bool | |
2121 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
2122 | { | |
2123 | rtx base, offset; | |
2124 | ||
2125 | if (!CONSTANT_ADDRESS_P (x)) | |
2126 | return false; | |
2127 | ||
2128 | if (flag_pic | |
2129 | && !(strict_p && TARGET_PCREL) | |
2130 | && symbolic_operand (x, VOIDmode)) | |
2131 | return false; | |
2132 | ||
2133 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
2134 | { | |
2135 | split_const (x, &base, &offset); | |
2136 | if (GET_CODE (base) == SYMBOL_REF | |
2137 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
2138 | return false; | |
2139 | } | |
2140 | ||
75df395f | 2141 | return !m68k_tls_reference_p (x, false); |
fc2241eb RS |
2142 | } |
2143 | ||
2144 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
2145 | labels will become jump tables. */ | |
2146 | ||
2147 | static bool | |
2148 | m68k_jump_table_ref_p (rtx x) | |
2149 | { | |
2150 | if (GET_CODE (x) != LABEL_REF) | |
2151 | return false; | |
2152 | ||
b32d5189 DM |
2153 | rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0)); |
2154 | if (!NEXT_INSN (insn) && !PREV_INSN (insn)) | |
fc2241eb RS |
2155 | return true; |
2156 | ||
b32d5189 DM |
2157 | insn = next_nonnote_insn (insn); |
2158 | return insn && JUMP_TABLE_DATA_P (insn); | |
fc2241eb RS |
2159 | } |
2160 | ||
2161 | /* Return true if X is a legitimate address for values of mode MODE. | |
2162 | STRICT_P says whether strict checking is needed. If the address | |
2163 | is valid, describe its components in *ADDRESS. */ | |
2164 | ||
2165 | static bool | |
ef4bddc2 | 2166 | m68k_decompose_address (machine_mode mode, rtx x, |
fc2241eb RS |
2167 | bool strict_p, struct m68k_address *address) |
2168 | { | |
2169 | unsigned int reach; | |
2170 | ||
2171 | memset (address, 0, sizeof (*address)); | |
2172 | ||
2173 | if (mode == BLKmode) | |
2174 | reach = 1; | |
2175 | else | |
2176 | reach = GET_MODE_SIZE (mode); | |
2177 | ||
2178 | /* Check for (An) (mode 2). */ | |
2179 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
2180 | { | |
2181 | address->base = x; | |
2182 | return true; | |
2183 | } | |
2184 | ||
2185 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
2186 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
2187 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
2188 | { | |
2189 | address->code = GET_CODE (x); | |
2190 | address->base = XEXP (x, 0); | |
2191 | return true; | |
2192 | } | |
2193 | ||
2194 | /* Check for (d16,An) (mode 5). */ | |
2195 | if (GET_CODE (x) == PLUS | |
2196 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2197 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
2198 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
2199 | { | |
2200 | address->base = XEXP (x, 0); | |
2201 | address->offset = XEXP (x, 1); | |
2202 | return true; | |
2203 | } | |
2204 | ||
2205 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
2206 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
2207 | addresses. */ | |
75df395f MK |
2208 | if (GET_CODE (x) == PLUS |
2209 | && XEXP (x, 0) == pic_offset_table_rtx) | |
fc2241eb | 2210 | { |
75df395f MK |
2211 | /* As we are processing a PLUS, do not unwrap RELOC32 symbols -- |
2212 | they are invalid in this context. */ | |
2213 | if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1)) | |
2214 | { | |
2215 | address->base = XEXP (x, 0); | |
2216 | address->offset = XEXP (x, 1); | |
2217 | return true; | |
2218 | } | |
fc2241eb RS |
2219 | } |
2220 | ||
2221 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
2222 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2223 | return false; | |
2224 | ||
2225 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
2226 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
2227 | All these modes are variations of mode 7. */ | |
2228 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
2229 | { | |
2230 | address->offset = x; | |
2231 | return true; | |
2232 | } | |
2233 | ||
2234 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
2235 | tablejumps. | |
2236 | ||
2237 | ??? do_tablejump creates these addresses before placing the target | |
2238 | label, so we have to assume that unplaced labels are jump table | |
2239 | references. It seems unlikely that we would ever generate indexed | |
2240 | accesses to unplaced labels in other cases. */ | |
2241 | if (GET_CODE (x) == PLUS | |
2242 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
2243 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2244 | { | |
2245 | address->offset = XEXP (x, 1); | |
2246 | return true; | |
2247 | } | |
2248 | ||
2249 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
2250 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
2251 | ||
2252 | if (TARGET_68020) | |
2253 | { | |
2254 | /* Check for a nonzero base displacement. */ | |
2255 | if (GET_CODE (x) == PLUS | |
2256 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
2257 | { | |
2258 | address->offset = XEXP (x, 1); | |
2259 | x = XEXP (x, 0); | |
2260 | } | |
2261 | ||
2262 | /* Check for a suppressed index register. */ | |
2263 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
2264 | { | |
2265 | address->base = x; | |
2266 | return true; | |
2267 | } | |
2268 | ||
2269 | /* Check for a suppressed base register. Do not allow this case | |
2270 | for non-symbolic offsets as it effectively gives gcc freedom | |
2271 | to treat data registers as base registers, which can generate | |
2272 | worse code. */ | |
2273 | if (address->offset | |
2274 | && symbolic_operand (address->offset, VOIDmode) | |
2275 | && m68k_decompose_index (x, strict_p, address)) | |
2276 | return true; | |
2277 | } | |
2278 | else | |
2279 | { | |
2280 | /* Check for a nonzero base displacement. */ | |
2281 | if (GET_CODE (x) == PLUS | |
2282 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2283 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
2284 | { | |
2285 | address->offset = XEXP (x, 1); | |
2286 | x = XEXP (x, 0); | |
2287 | } | |
2288 | } | |
2289 | ||
2290 | /* We now expect the sum of a base and an index. */ | |
2291 | if (GET_CODE (x) == PLUS) | |
2292 | { | |
2293 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
2294 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
2295 | { | |
2296 | address->base = XEXP (x, 0); | |
2297 | return true; | |
2298 | } | |
2299 | ||
2300 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
2301 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
2302 | { | |
2303 | address->base = XEXP (x, 1); | |
2304 | return true; | |
2305 | } | |
2306 | } | |
2307 | return false; | |
2308 | } | |
2309 | ||
2310 | /* Return true if X is a legitimate address for values of mode MODE. | |
2311 | STRICT_P says whether strict checking is needed. */ | |
2312 | ||
2313 | bool | |
ef4bddc2 | 2314 | m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) |
fc2241eb RS |
2315 | { |
2316 | struct m68k_address address; | |
2317 | ||
2318 | return m68k_decompose_address (mode, x, strict_p, &address); | |
2319 | } | |
2320 | ||
2321 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
2322 | Apply strict checking if called during or after reload. */ | |
2323 | ||
2324 | static bool | |
2325 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
2326 | { | |
2327 | return (MEM_P (x) | |
2328 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
2329 | reload_in_progress || reload_completed, | |
2330 | address)); | |
2331 | } | |
2332 | ||
1a627b35 RS |
2333 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
2334 | ||
2335 | bool | |
ef4bddc2 | 2336 | m68k_legitimate_constant_p (machine_mode mode, rtx x) |
1a627b35 RS |
2337 | { |
2338 | return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x); | |
2339 | } | |
2340 | ||
fc2241eb RS |
2341 | /* Return true if X matches the 'Q' constraint. It must be a memory |
2342 | with a base address and no constant offset or index. */ | |
2343 | ||
2344 | bool | |
2345 | m68k_matches_q_p (rtx x) | |
2346 | { | |
2347 | struct m68k_address address; | |
2348 | ||
2349 | return (m68k_legitimate_mem_p (x, &address) | |
2350 | && address.code == UNKNOWN | |
2351 | && address.base | |
2352 | && !address.offset | |
2353 | && !address.index); | |
2354 | } | |
2355 | ||
2356 | /* Return true if X matches the 'U' constraint. It must be a base address | |
2357 | with a constant offset and no index. */ | |
2358 | ||
2359 | bool | |
2360 | m68k_matches_u_p (rtx x) | |
2361 | { | |
2362 | struct m68k_address address; | |
2363 | ||
2364 | return (m68k_legitimate_mem_p (x, &address) | |
2365 | && address.code == UNKNOWN | |
2366 | && address.base | |
2367 | && address.offset | |
2368 | && !address.index); | |
2369 | } | |
2370 | ||
75df395f MK |
2371 | /* Return GOT pointer. */ |
2372 | ||
2373 | static rtx | |
2374 | m68k_get_gp (void) | |
2375 | { | |
2376 | if (pic_offset_table_rtx == NULL_RTX) | |
2377 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG); | |
2378 | ||
2379 | crtl->uses_pic_offset_table = 1; | |
2380 | ||
2381 | return pic_offset_table_rtx; | |
2382 | } | |
2383 | ||
2384 | /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC | |
2385 | wrappers. */ | |
2386 | enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO, | |
2387 | RELOC_TLSIE, RELOC_TLSLE }; | |
2388 | ||
2389 | #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT) | |
2390 | ||
2391 | /* Wrap symbol X into unspec representing relocation RELOC. | |
2392 | BASE_REG - register that should be added to the result. | |
2393 | TEMP_REG - if non-null, temporary register. */ | |
2394 | ||
2395 | static rtx | |
2396 | m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg) | |
2397 | { | |
2398 | bool use_x_p; | |
2399 | ||
2400 | use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS; | |
2401 | ||
2402 | if (TARGET_COLDFIRE && use_x_p) | |
2403 | /* When compiling with -mx{got, tls} switch the code will look like this: | |
2404 | ||
2405 | move.l <X>@<RELOC>,<TEMP_REG> | |
2406 | add.l <BASE_REG>,<TEMP_REG> */ | |
2407 | { | |
2408 | /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra | |
2409 | to put @RELOC after reference. */ | |
2410 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2411 | UNSPEC_RELOC32); | |
2412 | x = gen_rtx_CONST (Pmode, x); | |
2413 | ||
2414 | if (temp_reg == NULL) | |
2415 | { | |
2416 | gcc_assert (can_create_pseudo_p ()); | |
2417 | temp_reg = gen_reg_rtx (Pmode); | |
2418 | } | |
2419 | ||
2420 | emit_move_insn (temp_reg, x); | |
2421 | emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg)); | |
2422 | x = temp_reg; | |
2423 | } | |
2424 | else | |
2425 | { | |
2426 | x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), | |
2427 | UNSPEC_RELOC16); | |
2428 | x = gen_rtx_CONST (Pmode, x); | |
2429 | ||
2430 | x = gen_rtx_PLUS (Pmode, base_reg, x); | |
2431 | } | |
2432 | ||
2433 | return x; | |
2434 | } | |
2435 | ||
2436 | /* Helper for m68k_unwrap_symbol. | |
2437 | Also, if unwrapping was successful (that is if (ORIG != <return value>)), | |
2438 | sets *RELOC_PTR to relocation type for the symbol. */ | |
2439 | ||
2440 | static rtx | |
2441 | m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p, | |
2442 | enum m68k_reloc *reloc_ptr) | |
2443 | { | |
2444 | if (GET_CODE (orig) == CONST) | |
2445 | { | |
2446 | rtx x; | |
2447 | enum m68k_reloc dummy; | |
2448 | ||
2449 | x = XEXP (orig, 0); | |
2450 | ||
2451 | if (reloc_ptr == NULL) | |
2452 | reloc_ptr = &dummy; | |
2453 | ||
2454 | /* Handle an addend. */ | |
2455 | if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS) | |
2456 | && CONST_INT_P (XEXP (x, 1))) | |
2457 | x = XEXP (x, 0); | |
2458 | ||
2459 | if (GET_CODE (x) == UNSPEC) | |
2460 | { | |
2461 | switch (XINT (x, 1)) | |
2462 | { | |
2463 | case UNSPEC_RELOC16: | |
2464 | orig = XVECEXP (x, 0, 0); | |
2465 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2466 | break; | |
2467 | ||
2468 | case UNSPEC_RELOC32: | |
2469 | if (unwrap_reloc32_p) | |
2470 | { | |
2471 | orig = XVECEXP (x, 0, 0); | |
2472 | *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); | |
2473 | } | |
2474 | break; | |
2475 | ||
2476 | default: | |
2477 | break; | |
2478 | } | |
2479 | } | |
2480 | } | |
2481 | ||
2482 | return orig; | |
2483 | } | |
2484 | ||
2485 | /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p, | |
2486 | UNSPEC_RELOC32 wrappers. */ | |
2487 | ||
2488 | rtx | |
2489 | m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p) | |
2490 | { | |
2491 | return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL); | |
2492 | } | |
2493 | ||
ede9446c | 2494 | /* Adjust decorated address operand before outputing assembler for it. */ |
75df395f | 2495 | |
ede9446c AS |
2496 | static void |
2497 | m68k_adjust_decorated_operand (rtx op) | |
75df395f | 2498 | { |
75df395f MK |
2499 | /* Combine and, possibly, other optimizations may do good job |
2500 | converting | |
2501 | (const (unspec [(symbol)])) | |
2502 | into | |
2503 | (const (plus (unspec [(symbol)]) | |
2504 | (const_int N))). | |
2505 | The problem with this is emitting @TLS or @GOT decorations. | |
2506 | The decoration is emitted when processing (unspec), so the | |
2507 | result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE". | |
2508 | ||
2509 | It seems that the easiest solution to this is to convert such | |
2510 | operands to | |
2511 | (const (unspec [(plus (symbol) | |
2512 | (const_int N))])). | |
2513 | Note, that the top level of operand remains intact, so we don't have | |
2514 | to patch up anything outside of the operand. */ | |
2515 | ||
82eee4f1 | 2516 | subrtx_var_iterator::array_type array; |
ede9446c | 2517 | FOR_EACH_SUBRTX_VAR (iter, array, op, ALL) |
75df395f | 2518 | { |
ede9446c AS |
2519 | rtx x = *iter; |
2520 | if (m68k_unwrap_symbol (x, true) != x) | |
82eee4f1 | 2521 | { |
ede9446c | 2522 | rtx plus; |
82eee4f1 | 2523 | |
ede9446c AS |
2524 | gcc_assert (GET_CODE (x) == CONST); |
2525 | plus = XEXP (x, 0); | |
82eee4f1 | 2526 | |
ede9446c AS |
2527 | if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS) |
2528 | { | |
2529 | rtx unspec; | |
2530 | rtx addend; | |
82eee4f1 | 2531 | |
ede9446c AS |
2532 | unspec = XEXP (plus, 0); |
2533 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
2534 | addend = XEXP (plus, 1); | |
2535 | gcc_assert (CONST_INT_P (addend)); | |
82eee4f1 | 2536 | |
ede9446c | 2537 | /* We now have all the pieces, rearrange them. */ |
82eee4f1 | 2538 | |
ede9446c AS |
2539 | /* Move symbol to plus. */ |
2540 | XEXP (plus, 0) = XVECEXP (unspec, 0, 0); | |
82eee4f1 | 2541 | |
ede9446c AS |
2542 | /* Move plus inside unspec. */ |
2543 | XVECEXP (unspec, 0, 0) = plus; | |
82eee4f1 | 2544 | |
ede9446c AS |
2545 | /* Move unspec to top level of const. */ |
2546 | XEXP (x, 0) = unspec; | |
82eee4f1 | 2547 | } |
ede9446c | 2548 | iter.skip_subrtxes (); |
82eee4f1 | 2549 | } |
75df395f MK |
2550 | } |
2551 | } | |
2552 | ||
2553 | /* Move X to a register and add REG_EQUAL note pointing to ORIG. | |
2554 | If REG is non-null, use it; generate new pseudo otherwise. */ | |
2555 | ||
2556 | static rtx | |
2557 | m68k_move_to_reg (rtx x, rtx orig, rtx reg) | |
2558 | { | |
c85e862a | 2559 | rtx_insn *insn; |
75df395f MK |
2560 | |
2561 | if (reg == NULL_RTX) | |
2562 | { | |
2563 | gcc_assert (can_create_pseudo_p ()); | |
2564 | reg = gen_reg_rtx (Pmode); | |
2565 | } | |
2566 | ||
2567 | insn = emit_move_insn (reg, x); | |
2568 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2569 | by loop. */ | |
2570 | set_unique_reg_note (insn, REG_EQUAL, orig); | |
2571 | ||
2572 | return reg; | |
2573 | } | |
2574 | ||
2575 | /* Does the same as m68k_wrap_symbol, but returns a memory reference to | |
2576 | GOT slot. */ | |
2577 | ||
2578 | static rtx | |
2579 | m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) | |
2580 | { | |
2581 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg); | |
2582 | ||
2583 | x = gen_rtx_MEM (Pmode, x); | |
2584 | MEM_READONLY_P (x) = 1; | |
2585 | ||
2586 | return x; | |
2587 | } | |
2588 | ||
79e68feb RS |
2589 | /* Legitimize PIC addresses. If the address is already |
2590 | position-independent, we return ORIG. Newly generated | |
2591 | position-independent addresses go to REG. If we need more | |
2592 | than one register, we lose. | |
2593 | ||
2594 | An address is legitimized by making an indirect reference | |
2595 | through the Global Offset Table with the name of the symbol | |
2596 | used as an offset. | |
2597 | ||
2598 | The assembler and linker are responsible for placing the | |
2599 | address of the symbol in the GOT. The function prologue | |
2600 | is responsible for initializing a5 to the starting address | |
2601 | of the GOT. | |
2602 | ||
2603 | The assembler is also responsible for translating a symbol name | |
2604 | into a constant displacement from the start of the GOT. | |
2605 | ||
2606 | A quick example may make things a little clearer: | |
2607 | ||
2608 | When not generating PIC code to store the value 12345 into _foo | |
2609 | we would generate the following code: | |
2610 | ||
2611 | movel #12345, _foo | |
2612 | ||
2613 | When generating PIC two transformations are made. First, the compiler | |
2614 | loads the address of foo into a register. So the first transformation makes: | |
2615 | ||
2616 | lea _foo, a0 | |
2617 | movel #12345, a0@ | |
2618 | ||
2619 | The code in movsi will intercept the lea instruction and call this | |
2620 | routine which will transform the instructions into: | |
2621 | ||
2622 | movel a5@(_foo:w), a0 | |
2623 | movel #12345, a0@ | |
2624 | ||
2625 | ||
2626 | That (in a nutshell) is how *all* symbol and label references are | |
2627 | handled. */ | |
2628 | ||
2629 | rtx | |
ef4bddc2 | 2630 | legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, |
8a4a2253 | 2631 | rtx reg) |
79e68feb RS |
2632 | { |
2633 | rtx pic_ref = orig; | |
2634 | ||
2635 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
2636 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
2637 | { | |
4761e388 | 2638 | gcc_assert (reg); |
79e68feb | 2639 | |
75df395f MK |
2640 | pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg); |
2641 | pic_ref = m68k_move_to_reg (pic_ref, orig, reg); | |
79e68feb RS |
2642 | } |
2643 | else if (GET_CODE (orig) == CONST) | |
2644 | { | |
1d8eaa6b | 2645 | rtx base; |
79e68feb | 2646 | |
b2e08ed4 | 2647 | /* Make sure this has not already been legitimized. */ |
75df395f | 2648 | if (m68k_unwrap_symbol (orig, true) != orig) |
79e68feb RS |
2649 | return orig; |
2650 | ||
4761e388 | 2651 | gcc_assert (reg); |
79e68feb RS |
2652 | |
2653 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
2654 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
2655 | ||
2656 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2657 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2658 | base == reg ? 0 : reg); | |
79e68feb RS |
2659 | |
2660 | if (GET_CODE (orig) == CONST_INT) | |
0a81f074 | 2661 | pic_ref = plus_constant (Pmode, base, INTVAL (orig)); |
75df395f MK |
2662 | else |
2663 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); | |
79e68feb | 2664 | } |
75df395f | 2665 | |
79e68feb RS |
2666 | return pic_ref; |
2667 | } | |
2668 | ||
75df395f MK |
2669 | /* The __tls_get_addr symbol. */ |
2670 | static GTY(()) rtx m68k_tls_get_addr; | |
2671 | ||
2672 | /* Return SYMBOL_REF for __tls_get_addr. */ | |
2673 | ||
2674 | static rtx | |
2675 | m68k_get_tls_get_addr (void) | |
2676 | { | |
2677 | if (m68k_tls_get_addr == NULL_RTX) | |
2678 | m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr"); | |
2679 | ||
2680 | return m68k_tls_get_addr; | |
2681 | } | |
2682 | ||
2683 | /* Return libcall result in A0 instead of usual D0. */ | |
2684 | static bool m68k_libcall_value_in_a0_p = false; | |
2685 | ||
2686 | /* Emit instruction sequence that calls __tls_get_addr. X is | |
2687 | the TLS symbol we are referencing and RELOC is the symbol type to use | |
2688 | (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence | |
2689 | emitted. A pseudo register with result of __tls_get_addr call is | |
2690 | returned. */ | |
2691 | ||
2692 | static rtx | |
2693 | m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc) | |
2694 | { | |
2695 | rtx a0; | |
c85e862a | 2696 | rtx_insn *insns; |
75df395f MK |
2697 | rtx dest; |
2698 | ||
2699 | /* Emit the call sequence. */ | |
2700 | start_sequence (); | |
2701 | ||
2702 | /* FIXME: Unfortunately, emit_library_call_value does not | |
2703 | consider (plus (%a5) (const (unspec))) to be a good enough | |
2704 | operand for push, so it forces it into a register. The bad | |
2705 | thing about this is that combiner, due to copy propagation and other | |
67914693 | 2706 | optimizations, sometimes cannot later fix this. As a consequence, |
75df395f MK |
2707 | additional register may be allocated resulting in a spill. |
2708 | For reference, see args processing loops in | |
2709 | calls.c:emit_library_call_value_1. | |
2710 | For testcase, see gcc.target/m68k/tls-{gd, ld}.c */ | |
2711 | x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX); | |
2712 | ||
2713 | /* __tls_get_addr() is not a libcall, but emitting a libcall_value | |
2714 | is the simpliest way of generating a call. The difference between | |
2715 | __tls_get_addr() and libcall is that the result is returned in D0 | |
2716 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2717 | which temporarily switches returning the result to A0. */ | |
2718 | ||
2719 | m68k_libcall_value_in_a0_p = true; | |
2720 | a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE, | |
db69559b | 2721 | Pmode, x, Pmode); |
75df395f MK |
2722 | m68k_libcall_value_in_a0_p = false; |
2723 | ||
2724 | insns = get_insns (); | |
2725 | end_sequence (); | |
2726 | ||
2727 | gcc_assert (can_create_pseudo_p ()); | |
2728 | dest = gen_reg_rtx (Pmode); | |
2729 | emit_libcall_block (insns, dest, a0, eqv); | |
2730 | ||
2731 | return dest; | |
2732 | } | |
2733 | ||
2734 | /* The __tls_get_addr symbol. */ | |
2735 | static GTY(()) rtx m68k_read_tp; | |
2736 | ||
2737 | /* Return SYMBOL_REF for __m68k_read_tp. */ | |
2738 | ||
2739 | static rtx | |
2740 | m68k_get_m68k_read_tp (void) | |
2741 | { | |
2742 | if (m68k_read_tp == NULL_RTX) | |
2743 | m68k_read_tp = init_one_libfunc ("__m68k_read_tp"); | |
2744 | ||
2745 | return m68k_read_tp; | |
2746 | } | |
2747 | ||
2748 | /* Emit instruction sequence that calls __m68k_read_tp. | |
2749 | A pseudo register with result of __m68k_read_tp call is returned. */ | |
2750 | ||
2751 | static rtx | |
2752 | m68k_call_m68k_read_tp (void) | |
2753 | { | |
2754 | rtx a0; | |
2755 | rtx eqv; | |
c85e862a | 2756 | rtx_insn *insns; |
75df395f MK |
2757 | rtx dest; |
2758 | ||
2759 | start_sequence (); | |
2760 | ||
2761 | /* __m68k_read_tp() is not a libcall, but emitting a libcall_value | |
2762 | is the simpliest way of generating a call. The difference between | |
2763 | __m68k_read_tp() and libcall is that the result is returned in D0 | |
2764 | instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p | |
2765 | which temporarily switches returning the result to A0. */ | |
2766 | ||
2767 | /* Emit the call sequence. */ | |
2768 | m68k_libcall_value_in_a0_p = true; | |
2769 | a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE, | |
db69559b | 2770 | Pmode); |
75df395f MK |
2771 | m68k_libcall_value_in_a0_p = false; |
2772 | insns = get_insns (); | |
2773 | end_sequence (); | |
2774 | ||
2775 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2776 | share the m68k_read_tp result with other IE/LE model accesses. */ | |
2777 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32); | |
2778 | ||
2779 | gcc_assert (can_create_pseudo_p ()); | |
2780 | dest = gen_reg_rtx (Pmode); | |
2781 | emit_libcall_block (insns, dest, a0, eqv); | |
2782 | ||
2783 | return dest; | |
2784 | } | |
2785 | ||
2786 | /* Return a legitimized address for accessing TLS SYMBOL_REF X. | |
2787 | For explanations on instructions sequences see TLS/NPTL ABI for m68k and | |
2788 | ColdFire. */ | |
2789 | ||
2790 | rtx | |
2791 | m68k_legitimize_tls_address (rtx orig) | |
2792 | { | |
2793 | switch (SYMBOL_REF_TLS_MODEL (orig)) | |
2794 | { | |
2795 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
2796 | orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD); | |
2797 | break; | |
2798 | ||
2799 | case TLS_MODEL_LOCAL_DYNAMIC: | |
2800 | { | |
2801 | rtx eqv; | |
2802 | rtx a0; | |
2803 | rtx x; | |
2804 | ||
2805 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2806 | share the LDM result with other LD model accesses. */ | |
2807 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2808 | UNSPEC_RELOC32); | |
2809 | ||
2810 | a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM); | |
2811 | ||
2812 | x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX); | |
2813 | ||
2814 | if (can_create_pseudo_p ()) | |
2815 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2816 | ||
2817 | orig = x; | |
2818 | break; | |
2819 | } | |
2820 | ||
2821 | case TLS_MODEL_INITIAL_EXEC: | |
2822 | { | |
2823 | rtx a0; | |
2824 | rtx x; | |
2825 | ||
2826 | a0 = m68k_call_m68k_read_tp (); | |
2827 | ||
2828 | x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX); | |
2829 | x = gen_rtx_PLUS (Pmode, x, a0); | |
2830 | ||
2831 | if (can_create_pseudo_p ()) | |
2832 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2833 | ||
2834 | orig = x; | |
2835 | break; | |
2836 | } | |
2837 | ||
2838 | case TLS_MODEL_LOCAL_EXEC: | |
2839 | { | |
2840 | rtx a0; | |
2841 | rtx x; | |
2842 | ||
2843 | a0 = m68k_call_m68k_read_tp (); | |
2844 | ||
2845 | x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX); | |
2846 | ||
2847 | if (can_create_pseudo_p ()) | |
2848 | x = m68k_move_to_reg (x, orig, NULL_RTX); | |
2849 | ||
2850 | orig = x; | |
2851 | break; | |
2852 | } | |
2853 | ||
2854 | default: | |
2855 | gcc_unreachable (); | |
2856 | } | |
2857 | ||
2858 | return orig; | |
2859 | } | |
2860 | ||
2861 | /* Return true if X is a TLS symbol. */ | |
2862 | ||
2863 | static bool | |
2864 | m68k_tls_symbol_p (rtx x) | |
2865 | { | |
2866 | if (!TARGET_HAVE_TLS) | |
2867 | return false; | |
2868 | ||
2869 | if (GET_CODE (x) != SYMBOL_REF) | |
2870 | return false; | |
2871 | ||
2872 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
2873 | } | |
2874 | ||
75df395f MK |
2875 | /* If !LEGITIMATE_P, return true if X is a TLS symbol reference, |
2876 | though illegitimate one. | |
2877 | If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */ | |
2878 | ||
2879 | bool | |
2880 | m68k_tls_reference_p (rtx x, bool legitimate_p) | |
2881 | { | |
2882 | if (!TARGET_HAVE_TLS) | |
2883 | return false; | |
2884 | ||
2885 | if (!legitimate_p) | |
a5784152 RS |
2886 | { |
2887 | subrtx_var_iterator::array_type array; | |
2888 | FOR_EACH_SUBRTX_VAR (iter, array, x, ALL) | |
2889 | { | |
2890 | rtx x = *iter; | |
2891 | ||
2892 | /* Note: this is not the same as m68k_tls_symbol_p. */ | |
2893 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) | |
2894 | return true; | |
2895 | ||
2896 | /* Don't recurse into legitimate TLS references. */ | |
2897 | if (m68k_tls_reference_p (x, true)) | |
2898 | iter.skip_subrtxes (); | |
2899 | } | |
2900 | return false; | |
2901 | } | |
75df395f MK |
2902 | else |
2903 | { | |
2904 | enum m68k_reloc reloc = RELOC_GOT; | |
2905 | ||
2906 | return (m68k_unwrap_symbol_1 (x, true, &reloc) != x | |
2907 | && TLS_RELOC_P (reloc)); | |
2908 | } | |
2909 | } | |
2910 | ||
79e68feb | 2911 | \f |
0ce6f9fb | 2912 | |
a0a7fbc9 | 2913 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 2914 | |
bda2a571 RS |
2915 | /* Return the type of move that should be used for integer I. */ |
2916 | ||
c47b0cb4 MK |
2917 | M68K_CONST_METHOD |
2918 | m68k_const_method (HOST_WIDE_INT i) | |
0ce6f9fb | 2919 | { |
0ce6f9fb RK |
2920 | unsigned u; |
2921 | ||
6910dd70 | 2922 | if (USE_MOVQ (i)) |
0ce6f9fb | 2923 | return MOVQ; |
24092242 | 2924 | |
c16eadc7 | 2925 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 2926 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 2927 | if (!TARGET_COLDFIRE) |
24092242 RK |
2928 | { |
2929 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 2930 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
2931 | if (USE_MOVQ (i ^ 0xff)) |
2932 | return NOTB; | |
2933 | /* Likewise, try with not.w */ | |
2934 | if (USE_MOVQ (i ^ 0xffff)) | |
2935 | return NOTW; | |
2936 | /* This is the only value where neg.w is useful */ | |
2937 | if (i == -65408) | |
2938 | return NEGW; | |
24092242 | 2939 | } |
28bad6d1 | 2940 | |
5e04daf3 PB |
2941 | /* Try also with swap. */ |
2942 | u = i; | |
2943 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2944 | return SWAP; | |
2945 | ||
986e74d5 | 2946 | if (TARGET_ISAB) |
28bad6d1 | 2947 | { |
72edf146 | 2948 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
2949 | if (i >= 0 && i <= 65535) |
2950 | return MVZ; | |
2951 | if (i >= -32768 && i <= 32767) | |
2952 | return MVS; | |
2953 | } | |
2954 | ||
0ce6f9fb RK |
2955 | /* Otherwise, use move.l */ |
2956 | return MOVL; | |
2957 | } | |
2958 | ||
bda2a571 RS |
2959 | /* Return the cost of moving constant I into a data register. */ |
2960 | ||
3c50106f | 2961 | static int |
bda2a571 | 2962 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 2963 | { |
c47b0cb4 | 2964 | switch (m68k_const_method (i)) |
0ce6f9fb | 2965 | { |
a0a7fbc9 AS |
2966 | case MOVQ: |
2967 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2968 | return 0; | |
2969 | case MVZ: | |
2970 | case MVS: | |
2971 | case NOTB: | |
2972 | case NOTW: | |
2973 | case NEGW: | |
2974 | case SWAP: | |
2975 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2976 | return 1; | |
2977 | case MOVL: | |
2978 | return 2; | |
2979 | default: | |
2980 | gcc_unreachable (); | |
0ce6f9fb RK |
2981 | } |
2982 | } | |
2983 | ||
3c50106f | 2984 | static bool |
e548c9df AM |
2985 | m68k_rtx_costs (rtx x, machine_mode mode, int outer_code, |
2986 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 2987 | int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f | 2988 | { |
e548c9df AM |
2989 | int code = GET_CODE (x); |
2990 | ||
3c50106f RH |
2991 | switch (code) |
2992 | { | |
2993 | case CONST_INT: | |
2994 | /* Constant zero is super cheap due to clr instruction. */ | |
2995 | if (x == const0_rtx) | |
2996 | *total = 0; | |
2997 | else | |
bda2a571 | 2998 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
2999 | return true; |
3000 | ||
3001 | case CONST: | |
3002 | case LABEL_REF: | |
3003 | case SYMBOL_REF: | |
3004 | *total = 3; | |
3005 | return true; | |
3006 | ||
3007 | case CONST_DOUBLE: | |
3008 | /* Make 0.0 cheaper than other floating constants to | |
3009 | encourage creating tstsf and tstdf insns. */ | |
6cebc6cb BS |
3010 | if ((GET_RTX_CLASS (outer_code) == RTX_COMPARE |
3011 | || GET_RTX_CLASS (outer_code) == RTX_COMM_COMPARE) | |
3c50106f RH |
3012 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) |
3013 | *total = 4; | |
3014 | else | |
3015 | *total = 5; | |
3016 | return true; | |
3017 | ||
3018 | /* These are vaguely right for a 68020. */ | |
3019 | /* The costs for long multiply have been adjusted to work properly | |
3020 | in synth_mult on the 68020, relative to an average of the time | |
3021 | for add and the time for shift, taking away a little more because | |
3022 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
3023 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
3024 | terms. */ | |
fe95f2f7 JB |
3025 | #define MULL_COST \ |
3026 | (TUNE_68060 ? 2 \ | |
3027 | : TUNE_68040 ? 5 \ | |
03b3e271 KH |
3028 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ |
3029 | : (TUNE_CFV2 && TUNE_MAC) ? 4 \ | |
3030 | : TUNE_CFV2 ? 8 \ | |
fe95f2f7 JB |
3031 | : TARGET_COLDFIRE ? 3 : 13) |
3032 | ||
3033 | #define MULW_COST \ | |
3034 | (TUNE_68060 ? 2 \ | |
3035 | : TUNE_68040 ? 3 \ | |
03b3e271 KH |
3036 | : TUNE_68000_10 ? 5 \ |
3037 | : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ | |
3038 | : (TUNE_CFV2 && TUNE_MAC) ? 2 \ | |
3039 | : TUNE_CFV2 ? 8 \ | |
fe95f2f7 JB |
3040 | : TARGET_COLDFIRE ? 2 : 8) |
3041 | ||
3042 | #define DIVW_COST \ | |
3043 | (TARGET_CF_HWDIV ? 11 \ | |
3044 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
3045 | |
3046 | case PLUS: | |
3047 | /* An lea costs about three times as much as a simple add. */ | |
e548c9df | 3048 | if (mode == SImode |
3c50106f RH |
3049 | && GET_CODE (XEXP (x, 1)) == REG |
3050 | && GET_CODE (XEXP (x, 0)) == MULT | |
3051 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3052 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3053 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
3054 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
3055 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
3056 | { |
3057 | /* lea an@(dx:l:i),am */ | |
3058 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
3059 | return true; | |
3060 | } | |
3c50106f RH |
3061 | return false; |
3062 | ||
3063 | case ASHIFT: | |
3064 | case ASHIFTRT: | |
3065 | case LSHIFTRT: | |
fe95f2f7 | 3066 | if (TUNE_68060) |
3c50106f RH |
3067 | { |
3068 | *total = COSTS_N_INSNS(1); | |
3069 | return true; | |
3070 | } | |
fe95f2f7 | 3071 | if (TUNE_68000_10) |
3c50106f RH |
3072 | { |
3073 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3074 | { | |
3075 | if (INTVAL (XEXP (x, 1)) < 16) | |
3076 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
3077 | else | |
3078 | /* We're using clrw + swap for these cases. */ | |
3079 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
3080 | } | |
3081 | else | |
a0a7fbc9 | 3082 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
3083 | return true; |
3084 | } | |
3085 | /* A shift by a big integer takes an extra instruction. */ | |
3086 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
3087 | && (INTVAL (XEXP (x, 1)) == 16)) | |
3088 | { | |
3089 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
3090 | return true; | |
3091 | } | |
3092 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
3093 | && !(INTVAL (XEXP (x, 1)) > 0 | |
3094 | && INTVAL (XEXP (x, 1)) <= 8)) | |
3095 | { | |
eb849993 | 3096 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
3097 | return true; |
3098 | } | |
3099 | return false; | |
3100 | ||
3101 | case MULT: | |
3102 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
3103 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
e548c9df | 3104 | && mode == SImode) |
3c50106f | 3105 | *total = COSTS_N_INSNS (MULW_COST); |
e548c9df | 3106 | else if (mode == QImode || mode == HImode) |
3c50106f RH |
3107 | *total = COSTS_N_INSNS (MULW_COST); |
3108 | else | |
3109 | *total = COSTS_N_INSNS (MULL_COST); | |
3110 | return true; | |
3111 | ||
3112 | case DIV: | |
3113 | case UDIV: | |
3114 | case MOD: | |
3115 | case UMOD: | |
e548c9df | 3116 | if (mode == QImode || mode == HImode) |
3c50106f | 3117 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ |
eb849993 BI |
3118 | else if (TARGET_CF_HWDIV) |
3119 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
3120 | else |
3121 | *total = COSTS_N_INSNS (43); /* div.l */ | |
3122 | return true; | |
3123 | ||
f90b7a5a | 3124 | case ZERO_EXTRACT: |
6cebc6cb BS |
3125 | if (GET_RTX_CLASS (outer_code) == RTX_COMPARE |
3126 | || GET_RTX_CLASS (outer_code) == RTX_COMM_COMPARE) | |
f90b7a5a PB |
3127 | *total = 0; |
3128 | return false; | |
3129 | ||
3c50106f RH |
3130 | default: |
3131 | return false; | |
3132 | } | |
3133 | } | |
3134 | ||
88512ba0 | 3135 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
3136 | OPERANDS[0]. */ |
3137 | ||
3138 | static const char * | |
8a4a2253 | 3139 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 3140 | { |
bda2a571 | 3141 | HOST_WIDE_INT i; |
0ce6f9fb RK |
3142 | |
3143 | i = INTVAL (operands[1]); | |
c47b0cb4 | 3144 | switch (m68k_const_method (i)) |
0ce6f9fb | 3145 | { |
28bad6d1 | 3146 | case MVZ: |
28bad6d1 | 3147 | return "mvzw %1,%0"; |
1cbae84f PB |
3148 | case MVS: |
3149 | return "mvsw %1,%0"; | |
a0a7fbc9 | 3150 | case MOVQ: |
0ce6f9fb | 3151 | return "moveq %1,%0"; |
a0a7fbc9 | 3152 | case NOTB: |
66e07510 | 3153 | CC_STATUS_INIT; |
1d8eaa6b | 3154 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 3155 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 3156 | case NOTW: |
66e07510 | 3157 | CC_STATUS_INIT; |
1d8eaa6b | 3158 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 3159 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 3160 | case NEGW: |
66e07510 | 3161 | CC_STATUS_INIT; |
3b4b85c9 | 3162 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 3163 | case SWAP: |
0ce6f9fb RK |
3164 | { |
3165 | unsigned u = i; | |
3166 | ||
1d8eaa6b | 3167 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 3168 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 3169 | } |
a0a7fbc9 | 3170 | case MOVL: |
bda2a571 | 3171 | return "move%.l %1,%0"; |
a0a7fbc9 | 3172 | default: |
bda2a571 | 3173 | gcc_unreachable (); |
0ce6f9fb RK |
3174 | } |
3175 | } | |
3176 | ||
bda2a571 | 3177 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 3178 | |
bda2a571 RS |
3179 | bool |
3180 | valid_mov3q_const (HOST_WIDE_INT i) | |
3181 | { | |
3182 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
3183 | } |
3184 | ||
bda2a571 RS |
3185 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
3186 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 3187 | |
bda2a571 | 3188 | static const char * |
8a4a2253 | 3189 | output_move_simode_const (rtx *operands) |
02ed0c07 | 3190 | { |
bda2a571 RS |
3191 | rtx dest; |
3192 | HOST_WIDE_INT src; | |
3193 | ||
3194 | dest = operands[0]; | |
3195 | src = INTVAL (operands[1]); | |
3196 | if (src == 0 | |
3197 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
3198 | /* clr insns on 68000 read before writing. */ |
3199 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 3200 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 3201 | return "clr%.l %0"; |
bda2a571 | 3202 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 3203 | return "mov3q%.l %1,%0"; |
bda2a571 | 3204 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 3205 | return "sub%.l %0,%0"; |
bda2a571 | 3206 | else if (DATA_REG_P (dest)) |
02ed0c07 | 3207 | return output_move_const_into_data_reg (operands); |
bda2a571 | 3208 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 3209 | { |
bda2a571 | 3210 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
3211 | return "mov3q%.l %1,%0"; |
3212 | return "move%.w %1,%0"; | |
3213 | } | |
bda2a571 RS |
3214 | else if (MEM_P (dest) |
3215 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
3216 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
3217 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 3218 | { |
bda2a571 | 3219 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
3220 | return "mov3q%.l %1,%-"; |
3221 | return "pea %a1"; | |
3222 | } | |
02ed0c07 RK |
3223 | return "move%.l %1,%0"; |
3224 | } | |
3225 | ||
5505f548 | 3226 | const char * |
8a4a2253 | 3227 | output_move_simode (rtx *operands) |
f4e80198 | 3228 | { |
6cebc6cb BS |
3229 | handle_flags_for_move (operands); |
3230 | ||
f4e80198 RK |
3231 | if (GET_CODE (operands[1]) == CONST_INT) |
3232 | return output_move_simode_const (operands); | |
3233 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3234 | || GET_CODE (operands[1]) == CONST) | |
3235 | && push_operand (operands[0], SImode)) | |
3236 | return "pea %a1"; | |
3237 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
3238 | || GET_CODE (operands[1]) == CONST) | |
3239 | && ADDRESS_REG_P (operands[0])) | |
3240 | return "lea %a1,%0"; | |
3241 | return "move%.l %1,%0"; | |
3242 | } | |
3243 | ||
5505f548 | 3244 | const char * |
8a4a2253 | 3245 | output_move_himode (rtx *operands) |
f4e80198 | 3246 | { |
6cebc6cb | 3247 | if (GET_CODE (operands[1]) == CONST_INT) |
f4e80198 RK |
3248 | { |
3249 | if (operands[1] == const0_rtx | |
3250 | && (DATA_REG_P (operands[0]) | |
3251 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
3252 | /* clr insns on 68000 read before writing. */ |
3253 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
3254 | || !(GET_CODE (operands[0]) == MEM |
3255 | && MEM_VOLATILE_P (operands[0])))) | |
3256 | return "clr%.w %0"; | |
38198304 AS |
3257 | else if (operands[1] == const0_rtx |
3258 | && ADDRESS_REG_P (operands[0])) | |
3259 | return "sub%.l %0,%0"; | |
f4e80198 RK |
3260 | else if (DATA_REG_P (operands[0]) |
3261 | && INTVAL (operands[1]) < 128 | |
3262 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 3263 | return "moveq %1,%0"; |
f4e80198 RK |
3264 | else if (INTVAL (operands[1]) < 0x8000 |
3265 | && INTVAL (operands[1]) >= -0x8000) | |
3266 | return "move%.w %1,%0"; | |
3267 | } | |
3268 | else if (CONSTANT_P (operands[1])) | |
6cebc6cb | 3269 | gcc_unreachable (); |
f4e80198 RK |
3270 | return "move%.w %1,%0"; |
3271 | } | |
3272 | ||
5505f548 | 3273 | const char * |
8a4a2253 | 3274 | output_move_qimode (rtx *operands) |
f4e80198 | 3275 | { |
6cebc6cb BS |
3276 | handle_flags_for_move (operands); |
3277 | ||
102701ff | 3278 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 3279 | byte pushes. The 5200 (ColdFire) does not do this. */ |
6cebc6cb | 3280 | |
a0a7fbc9 | 3281 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
3282 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
3283 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
3284 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
3285 | && ! ADDRESS_REG_P (operands[1]) | |
3286 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 3287 | |
3197c489 | 3288 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 3289 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 3290 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
3291 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3292 | { | |
3293 | if (operands[1] == const0_rtx) | |
3294 | return "clr%.b %0"; | |
9425fb04 | 3295 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
3296 | && GET_CODE (operands[1]) == CONST_INT |
3297 | && (INTVAL (operands[1]) & 255) == 255) | |
3298 | { | |
3299 | CC_STATUS_INIT; | |
3300 | return "st %0"; | |
3301 | } | |
3302 | } | |
3303 | if (GET_CODE (operands[1]) == CONST_INT | |
3304 | && DATA_REG_P (operands[0]) | |
3305 | && INTVAL (operands[1]) < 128 | |
3306 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 3307 | return "moveq %1,%0"; |
38198304 AS |
3308 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
3309 | return "sub%.l %0,%0"; | |
f4e80198 | 3310 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
6cebc6cb | 3311 | gcc_unreachable (); |
c16eadc7 | 3312 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
3313 | from address registers. */ |
3314 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
6cebc6cb BS |
3315 | { |
3316 | if (ADDRESS_REG_P (operands[1])) | |
3317 | CC_STATUS_INIT; | |
3318 | return "move%.w %1,%0"; | |
3319 | } | |
f4e80198 RK |
3320 | return "move%.b %1,%0"; |
3321 | } | |
3322 | ||
5505f548 | 3323 | const char * |
8a4a2253 | 3324 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
3325 | { |
3326 | if (operands[1] == const0_rtx | |
3197c489 RS |
3327 | /* clr insns on 68000 read before writing. */ |
3328 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
3329 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3330 | return "clr%.w %0"; | |
3331 | return "move%.w %1,%0"; | |
3332 | } | |
3333 | ||
5505f548 | 3334 | const char * |
8a4a2253 | 3335 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
3336 | { |
3337 | if (operands[1] == const0_rtx | |
3197c489 RS |
3338 | /* clr insns on 68000 read before writing. */ |
3339 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
3340 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
3341 | return "clr%.b %0"; | |
3342 | return "move%.b %1,%0"; | |
3343 | } | |
3344 | ||
79e68feb RS |
3345 | /* Return the best assembler insn template |
3346 | for moving operands[1] into operands[0] as a fullword. */ | |
3347 | ||
5505f548 | 3348 | static const char * |
8a4a2253 | 3349 | singlemove_string (rtx *operands) |
79e68feb | 3350 | { |
02ed0c07 RK |
3351 | if (GET_CODE (operands[1]) == CONST_INT) |
3352 | return output_move_simode_const (operands); | |
3353 | return "move%.l %1,%0"; | |
79e68feb RS |
3354 | } |
3355 | ||
2505bc97 | 3356 | |
c47b0cb4 MK |
3357 | /* Output assembler or rtl code to perform a doubleword move insn |
3358 | with operands OPERANDS. | |
3359 | Pointers to 3 helper functions should be specified: | |
3360 | HANDLE_REG_ADJUST to adjust a register by a small value, | |
3361 | HANDLE_COMPADR to compute an address and | |
3362 | HANDLE_MOVSI to move 4 bytes. */ | |
79e68feb | 3363 | |
c47b0cb4 MK |
3364 | static void |
3365 | handle_move_double (rtx operands[2], | |
3366 | void (*handle_reg_adjust) (rtx, int), | |
3367 | void (*handle_compadr) (rtx [2]), | |
3368 | void (*handle_movsi) (rtx [2])) | |
79e68feb | 3369 | { |
2505bc97 RS |
3370 | enum |
3371 | { | |
3372 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
3373 | } optype0, optype1; | |
79e68feb | 3374 | rtx latehalf[2]; |
2505bc97 | 3375 | rtx middlehalf[2]; |
7f98eeb6 | 3376 | rtx xops[2]; |
79e68feb | 3377 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 3378 | int dest_overlapped_low = 0; |
184916bc | 3379 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
3380 | |
3381 | middlehalf[0] = 0; | |
3382 | middlehalf[1] = 0; | |
79e68feb RS |
3383 | |
3384 | /* First classify both operands. */ | |
3385 | ||
3386 | if (REG_P (operands[0])) | |
3387 | optype0 = REGOP; | |
3388 | else if (offsettable_memref_p (operands[0])) | |
3389 | optype0 = OFFSOP; | |
3390 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
3391 | optype0 = POPOP; | |
3392 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
3393 | optype0 = PUSHOP; | |
3394 | else if (GET_CODE (operands[0]) == MEM) | |
3395 | optype0 = MEMOP; | |
3396 | else | |
3397 | optype0 = RNDOP; | |
3398 | ||
3399 | if (REG_P (operands[1])) | |
3400 | optype1 = REGOP; | |
3401 | else if (CONSTANT_P (operands[1])) | |
3402 | optype1 = CNSTOP; | |
3403 | else if (offsettable_memref_p (operands[1])) | |
3404 | optype1 = OFFSOP; | |
3405 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
3406 | optype1 = POPOP; | |
3407 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
3408 | optype1 = PUSHOP; | |
3409 | else if (GET_CODE (operands[1]) == MEM) | |
3410 | optype1 = MEMOP; | |
3411 | else | |
3412 | optype1 = RNDOP; | |
3413 | ||
4761e388 NS |
3414 | /* Check for the cases that the operand constraints are not supposed |
3415 | to allow to happen. Generating code for these cases is | |
3416 | painful. */ | |
3417 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
3418 | |
3419 | /* If one operand is decrementing and one is incrementing | |
3420 | decrement the former register explicitly | |
3421 | and change that operand into ordinary indexing. */ | |
3422 | ||
3423 | if (optype0 == PUSHOP && optype1 == POPOP) | |
3424 | { | |
3425 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
c47b0cb4 MK |
3426 | |
3427 | handle_reg_adjust (operands[0], -size); | |
3428 | ||
2505bc97 | 3429 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 3430 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 3431 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 3432 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 3433 | else |
1d8eaa6b | 3434 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
3435 | optype0 = OFFSOP; |
3436 | } | |
3437 | if (optype0 == POPOP && optype1 == PUSHOP) | |
3438 | { | |
3439 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
c47b0cb4 MK |
3440 | |
3441 | handle_reg_adjust (operands[1], -size); | |
3442 | ||
2505bc97 | 3443 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 3444 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 3445 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 3446 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 3447 | else |
1d8eaa6b | 3448 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
3449 | optype1 = OFFSOP; |
3450 | } | |
3451 | ||
3452 | /* If an operand is an unoffsettable memory ref, find a register | |
3453 | we can increment temporarily to make it refer to the second word. */ | |
3454 | ||
3455 | if (optype0 == MEMOP) | |
3456 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
3457 | ||
3458 | if (optype1 == MEMOP) | |
3459 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
3460 | ||
3461 | /* Ok, we can do one word at a time. | |
3462 | Normally we do the low-numbered word first, | |
3463 | but if either operand is autodecrementing then we | |
3464 | do the high-numbered word first. | |
3465 | ||
3466 | In either case, set up in LATEHALF the operands to use | |
3467 | for the high-numbered word and in some cases alter the | |
3468 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
3469 | ||
2505bc97 RS |
3470 | if (size == 12) |
3471 | { | |
3472 | if (optype0 == REGOP) | |
3473 | { | |
1d8eaa6b AS |
3474 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
3475 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
3476 | } |
3477 | else if (optype0 == OFFSOP) | |
3478 | { | |
b72f00af RK |
3479 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
3480 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
3481 | } |
3482 | else | |
3483 | { | |
c47b0cb4 MK |
3484 | middlehalf[0] = adjust_address (operands[0], SImode, 0); |
3485 | latehalf[0] = adjust_address (operands[0], SImode, 0); | |
2505bc97 RS |
3486 | } |
3487 | ||
3488 | if (optype1 == REGOP) | |
3489 | { | |
1d8eaa6b AS |
3490 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
3491 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
3492 | } |
3493 | else if (optype1 == OFFSOP) | |
3494 | { | |
b72f00af RK |
3495 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
3496 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
3497 | } |
3498 | else if (optype1 == CNSTOP) | |
3499 | { | |
3500 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3501 | { | |
2505bc97 RS |
3502 | long l[3]; |
3503 | ||
34a72c33 RS |
3504 | REAL_VALUE_TO_TARGET_LONG_DOUBLE |
3505 | (*CONST_DOUBLE_REAL_VALUE (operands[1]), l); | |
2505bc97 RS |
3506 | operands[1] = GEN_INT (l[0]); |
3507 | middlehalf[1] = GEN_INT (l[1]); | |
3508 | latehalf[1] = GEN_INT (l[2]); | |
3509 | } | |
4761e388 | 3510 | else |
2505bc97 | 3511 | { |
4761e388 NS |
3512 | /* No non-CONST_DOUBLE constant should ever appear |
3513 | here. */ | |
3514 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
3515 | } |
3516 | } | |
3517 | else | |
3518 | { | |
c47b0cb4 MK |
3519 | middlehalf[1] = adjust_address (operands[1], SImode, 0); |
3520 | latehalf[1] = adjust_address (operands[1], SImode, 0); | |
2505bc97 RS |
3521 | } |
3522 | } | |
79e68feb | 3523 | else |
2505bc97 RS |
3524 | /* size is not 12: */ |
3525 | { | |
3526 | if (optype0 == REGOP) | |
1d8eaa6b | 3527 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 3528 | else if (optype0 == OFFSOP) |
b72f00af | 3529 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 | 3530 | else |
c47b0cb4 | 3531 | latehalf[0] = adjust_address (operands[0], SImode, 0); |
2505bc97 RS |
3532 | |
3533 | if (optype1 == REGOP) | |
1d8eaa6b | 3534 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 3535 | else if (optype1 == OFFSOP) |
b72f00af | 3536 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
3537 | else if (optype1 == CNSTOP) |
3538 | split_double (operands[1], &operands[1], &latehalf[1]); | |
3539 | else | |
c47b0cb4 | 3540 | latehalf[1] = adjust_address (operands[1], SImode, 0); |
2505bc97 | 3541 | } |
79e68feb | 3542 | |
e864837a AS |
3543 | /* If insn is effectively movd N(REG),-(REG) then we will do the high |
3544 | word first. We should use the adjusted operand 1 (which is N+4(REG)) | |
3545 | for the low word as well, to compensate for the first decrement of | |
3546 | REG. */ | |
79e68feb | 3547 | if (optype0 == PUSHOP |
e864837a | 3548 | && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1])) |
c88aeaf8 | 3549 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 3550 | |
7f98eeb6 RS |
3551 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
3552 | if the upper part of reg N does not appear in the MEM, arrange to | |
3553 | emit the move late-half first. Otherwise, compute the MEM address | |
3554 | into the upper part of N and use that as a pointer to the memory | |
3555 | operand. */ | |
3556 | if (optype0 == REGOP | |
3557 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
3558 | { | |
1d8eaa6b | 3559 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
3560 | |
3561 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 3562 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
3563 | { |
3564 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
3565 | compute the address into latehalf of dest. |
3566 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 3567 | compadr: |
7f98eeb6 RS |
3568 | xops[0] = latehalf[0]; |
3569 | xops[1] = XEXP (operands[1], 0); | |
c47b0cb4 MK |
3570 | |
3571 | handle_compadr (xops); | |
3572 | if (GET_MODE (operands[1]) == XFmode) | |
7f98eeb6 | 3573 | { |
1d8eaa6b | 3574 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
3575 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
3576 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
3577 | } |
3578 | else | |
3579 | { | |
1d8eaa6b | 3580 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 3581 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
3582 | } |
3583 | } | |
3584 | else if (size == 12 | |
d7e8d581 RS |
3585 | && reg_overlap_mentioned_p (middlehalf[0], |
3586 | XEXP (operands[1], 0))) | |
7f98eeb6 | 3587 | { |
3a58400f RS |
3588 | /* Check for two regs used by both source and dest. |
3589 | Note that this can't happen if the dest is all data regs. | |
3590 | It can happen if the dest is d6, d7, a0. | |
3591 | But in that case, latehalf is an addr reg, so | |
3592 | the code at compadr does ok. */ | |
3593 | ||
3594 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
3595 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
3596 | goto compadr; | |
7f98eeb6 RS |
3597 | |
3598 | /* JRV says this can't happen: */ | |
4761e388 | 3599 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 3600 | |
7a1929e1 | 3601 | /* Only the middle reg conflicts; simply put it last. */ |
c47b0cb4 MK |
3602 | handle_movsi (operands); |
3603 | handle_movsi (latehalf); | |
3604 | handle_movsi (middlehalf); | |
3605 | ||
3606 | return; | |
7f98eeb6 | 3607 | } |
2fb8a81d | 3608 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
3609 | /* If the low half of dest is mentioned in the source memory |
3610 | address, the arrange to emit the move late half first. */ | |
3611 | dest_overlapped_low = 1; | |
3612 | } | |
3613 | ||
79e68feb RS |
3614 | /* If one or both operands autodecrementing, |
3615 | do the two words, high-numbered first. */ | |
3616 | ||
3617 | /* Likewise, the first move would clobber the source of the second one, | |
3618 | do them in the other order. This happens only for registers; | |
3619 | such overlap can't happen in memory unless the user explicitly | |
3620 | sets it up, and that is an undefined circumstance. */ | |
3621 | ||
3622 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
3623 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 3624 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
3625 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
3626 | || dest_overlapped_low) | |
79e68feb RS |
3627 | { |
3628 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
3629 | if (addreg0) | |
c47b0cb4 | 3630 | handle_reg_adjust (addreg0, size - 4); |
79e68feb | 3631 | if (addreg1) |
c47b0cb4 | 3632 | handle_reg_adjust (addreg1, size - 4); |
79e68feb RS |
3633 | |
3634 | /* Do that word. */ | |
c47b0cb4 | 3635 | handle_movsi (latehalf); |
79e68feb RS |
3636 | |
3637 | /* Undo the adds we just did. */ | |
3638 | if (addreg0) | |
c47b0cb4 | 3639 | handle_reg_adjust (addreg0, -4); |
79e68feb | 3640 | if (addreg1) |
c47b0cb4 | 3641 | handle_reg_adjust (addreg1, -4); |
79e68feb | 3642 | |
2505bc97 RS |
3643 | if (size == 12) |
3644 | { | |
c47b0cb4 MK |
3645 | handle_movsi (middlehalf); |
3646 | ||
2505bc97 | 3647 | if (addreg0) |
c47b0cb4 | 3648 | handle_reg_adjust (addreg0, -4); |
2505bc97 | 3649 | if (addreg1) |
c47b0cb4 | 3650 | handle_reg_adjust (addreg1, -4); |
2505bc97 RS |
3651 | } |
3652 | ||
79e68feb | 3653 | /* Do low-numbered word. */ |
c47b0cb4 MK |
3654 | |
3655 | handle_movsi (operands); | |
3656 | return; | |
79e68feb RS |
3657 | } |
3658 | ||
3659 | /* Normal case: do the two words, low-numbered first. */ | |
3660 | ||
c47b0cb4 | 3661 | handle_movsi (operands); |
79e68feb | 3662 | |
2505bc97 RS |
3663 | /* Do the middle one of the three words for long double */ |
3664 | if (size == 12) | |
3665 | { | |
3666 | if (addreg0) | |
c47b0cb4 | 3667 | handle_reg_adjust (addreg0, 4); |
2505bc97 | 3668 | if (addreg1) |
c47b0cb4 | 3669 | handle_reg_adjust (addreg1, 4); |
2505bc97 | 3670 | |
c47b0cb4 | 3671 | handle_movsi (middlehalf); |
2505bc97 RS |
3672 | } |
3673 | ||
79e68feb RS |
3674 | /* Make any unoffsettable addresses point at high-numbered word. */ |
3675 | if (addreg0) | |
c47b0cb4 | 3676 | handle_reg_adjust (addreg0, 4); |
79e68feb | 3677 | if (addreg1) |
c47b0cb4 | 3678 | handle_reg_adjust (addreg1, 4); |
79e68feb RS |
3679 | |
3680 | /* Do that word. */ | |
c47b0cb4 | 3681 | handle_movsi (latehalf); |
79e68feb RS |
3682 | |
3683 | /* Undo the adds we just did. */ | |
3684 | if (addreg0) | |
c47b0cb4 MK |
3685 | handle_reg_adjust (addreg0, -(size - 4)); |
3686 | if (addreg1) | |
3687 | handle_reg_adjust (addreg1, -(size - 4)); | |
3688 | ||
3689 | return; | |
3690 | } | |
3691 | ||
3692 | /* Output assembler code to adjust REG by N. */ | |
3693 | static void | |
3694 | output_reg_adjust (rtx reg, int n) | |
3695 | { | |
3696 | const char *s; | |
3697 | ||
01512446 | 3698 | gcc_assert (GET_MODE (reg) == SImode && n >= -12 && n != 0 && n <= 12); |
c47b0cb4 MK |
3699 | |
3700 | switch (n) | |
2505bc97 | 3701 | { |
c47b0cb4 MK |
3702 | case 12: |
3703 | s = "add%.l #12,%0"; | |
3704 | break; | |
3705 | ||
3706 | case 8: | |
3707 | s = "addq%.l #8,%0"; | |
3708 | break; | |
3709 | ||
3710 | case 4: | |
3711 | s = "addq%.l #4,%0"; | |
3712 | break; | |
3713 | ||
3714 | case -12: | |
3715 | s = "sub%.l #12,%0"; | |
3716 | break; | |
3717 | ||
3718 | case -8: | |
3719 | s = "subq%.l #8,%0"; | |
3720 | break; | |
3721 | ||
3722 | case -4: | |
3723 | s = "subq%.l #4,%0"; | |
3724 | break; | |
3725 | ||
3726 | default: | |
3727 | gcc_unreachable (); | |
3728 | s = NULL; | |
2505bc97 | 3729 | } |
c47b0cb4 MK |
3730 | |
3731 | output_asm_insn (s, ®); | |
3732 | } | |
3733 | ||
3734 | /* Emit rtl code to adjust REG by N. */ | |
3735 | static void | |
3736 | emit_reg_adjust (rtx reg1, int n) | |
3737 | { | |
3738 | rtx reg2; | |
3739 | ||
01512446 | 3740 | gcc_assert (GET_MODE (reg1) == SImode && n >= -12 && n != 0 && n <= 12); |
c47b0cb4 MK |
3741 | |
3742 | reg1 = copy_rtx (reg1); | |
3743 | reg2 = copy_rtx (reg1); | |
3744 | ||
3745 | if (n < 0) | |
3746 | emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n))); | |
3747 | else if (n > 0) | |
3748 | emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n))); | |
3749 | else | |
3750 | gcc_unreachable (); | |
3751 | } | |
3752 | ||
3753 | /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */ | |
3754 | static void | |
3755 | output_compadr (rtx operands[2]) | |
3756 | { | |
3757 | output_asm_insn ("lea %a1,%0", operands); | |
3758 | } | |
3759 | ||
3760 | /* Output the best assembler insn for moving operands[1] into operands[0] | |
3761 | as a fullword. */ | |
3762 | static void | |
3763 | output_movsi (rtx operands[2]) | |
3764 | { | |
3765 | output_asm_insn (singlemove_string (operands), operands); | |
3766 | } | |
3767 | ||
3768 | /* Copy OP and change its mode to MODE. */ | |
3769 | static rtx | |
ef4bddc2 | 3770 | copy_operand (rtx op, machine_mode mode) |
c47b0cb4 MK |
3771 | { |
3772 | /* ??? This looks really ugly. There must be a better way | |
3773 | to change a mode on the operand. */ | |
3774 | if (GET_MODE (op) != VOIDmode) | |
2505bc97 | 3775 | { |
c47b0cb4 MK |
3776 | if (REG_P (op)) |
3777 | op = gen_rtx_REG (mode, REGNO (op)); | |
2505bc97 | 3778 | else |
c47b0cb4 MK |
3779 | { |
3780 | op = copy_rtx (op); | |
3781 | PUT_MODE (op, mode); | |
3782 | } | |
2505bc97 | 3783 | } |
79e68feb | 3784 | |
c47b0cb4 MK |
3785 | return op; |
3786 | } | |
3787 | ||
3788 | /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */ | |
3789 | static void | |
3790 | emit_movsi (rtx operands[2]) | |
3791 | { | |
3792 | operands[0] = copy_operand (operands[0], SImode); | |
3793 | operands[1] = copy_operand (operands[1], SImode); | |
3794 | ||
3795 | emit_insn (gen_movsi (operands[0], operands[1])); | |
3796 | } | |
3797 | ||
3798 | /* Output assembler code to perform a doubleword move insn | |
3799 | with operands OPERANDS. */ | |
3800 | const char * | |
3801 | output_move_double (rtx *operands) | |
3802 | { | |
3803 | handle_move_double (operands, | |
3804 | output_reg_adjust, output_compadr, output_movsi); | |
3805 | ||
79e68feb RS |
3806 | return ""; |
3807 | } | |
3808 | ||
c47b0cb4 MK |
3809 | /* Output rtl code to perform a doubleword move insn |
3810 | with operands OPERANDS. */ | |
3811 | void | |
3812 | m68k_emit_move_double (rtx operands[2]) | |
3813 | { | |
3814 | handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi); | |
3815 | } | |
dcc21c4c PB |
3816 | |
3817 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
3818 | new rtx with the correct mode. */ | |
3819 | ||
3820 | static rtx | |
ef4bddc2 | 3821 | force_mode (machine_mode mode, rtx orig) |
dcc21c4c PB |
3822 | { |
3823 | if (mode == GET_MODE (orig)) | |
3824 | return orig; | |
3825 | ||
3826 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
3827 | abort (); | |
3828 | ||
3829 | return gen_rtx_REG (mode, REGNO (orig)); | |
3830 | } | |
3831 | ||
3832 | static int | |
ef4bddc2 | 3833 | fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
dcc21c4c PB |
3834 | { |
3835 | return reg_renumber && FP_REG_P (op); | |
3836 | } | |
3837 | ||
3838 | /* Emit insns to move operands[1] into operands[0]. | |
3839 | ||
3840 | Return 1 if we have written out everything that needs to be done to | |
3841 | do the move. Otherwise, return 0 and the caller will emit the move | |
3842 | normally. | |
3843 | ||
3844 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 3845 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
3846 | of SCRATCH_REG in the proper mode. */ |
3847 | ||
3848 | int | |
ef4bddc2 | 3849 | emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) |
dcc21c4c | 3850 | { |
fb43b412 JL |
3851 | rtx operand0 = operands[0]; |
3852 | rtx operand1 = operands[1]; | |
3853 | rtx tem; | |
dcc21c4c PB |
3854 | |
3855 | if (scratch_reg | |
3856 | && reload_in_progress && GET_CODE (operand0) == REG | |
3857 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
f2034d06 | 3858 | operand0 = reg_equiv_mem (REGNO (operand0)); |
dcc21c4c PB |
3859 | else if (scratch_reg |
3860 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
3861 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
3862 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
3863 | { | |
3864 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3865 | the code which tracks sets/uses for delete_output_reload. */ | |
3866 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
f2034d06 | 3867 | reg_equiv_mem (REGNO (SUBREG_REG (operand0))), |
dcc21c4c | 3868 | SUBREG_BYTE (operand0)); |
55a2c322 | 3869 | operand0 = alter_subreg (&temp, true); |
dcc21c4c PB |
3870 | } |
3871 | ||
3872 | if (scratch_reg | |
3873 | && reload_in_progress && GET_CODE (operand1) == REG | |
3874 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
f2034d06 | 3875 | operand1 = reg_equiv_mem (REGNO (operand1)); |
dcc21c4c PB |
3876 | else if (scratch_reg |
3877 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
3878 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
3879 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
3880 | { | |
3881 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
3882 | the code which tracks sets/uses for delete_output_reload. */ | |
3883 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
f2034d06 | 3884 | reg_equiv_mem (REGNO (SUBREG_REG (operand1))), |
dcc21c4c | 3885 | SUBREG_BYTE (operand1)); |
55a2c322 | 3886 | operand1 = alter_subreg (&temp, true); |
dcc21c4c PB |
3887 | } |
3888 | ||
3889 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
3890 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
3891 | != XEXP (operand0, 0))) | |
3892 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
3893 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
3894 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
3895 | != XEXP (operand1, 0))) | |
3896 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
3897 | ||
3898 | /* Handle secondary reloads for loads/stores of FP registers where | |
3899 | the address is symbolic by using the scratch register */ | |
3900 | if (fp_reg_operand (operand0, mode) | |
3901 | && ((GET_CODE (operand1) == MEM | |
3902 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
3903 | || ((GET_CODE (operand1) == SUBREG | |
3904 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
3905 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
3906 | && scratch_reg) | |
3907 | { | |
3908 | if (GET_CODE (operand1) == SUBREG) | |
3909 | operand1 = XEXP (operand1, 0); | |
3910 | ||
3911 | /* SCRATCH_REG will hold an address. We want | |
3912 | it in SImode regardless of what mode it was originally given | |
3913 | to us. */ | |
3914 | scratch_reg = force_mode (SImode, scratch_reg); | |
3915 | ||
3916 | /* D might not fit in 14 bits either; for such cases load D into | |
3917 | scratch reg. */ | |
3918 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
3919 | { | |
3920 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
3921 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
3922 | Pmode, | |
3923 | XEXP (XEXP (operand1, 0), 0), | |
3924 | scratch_reg)); | |
3925 | } | |
3926 | else | |
3927 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
f7df4a84 | 3928 | emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg))); |
dcc21c4c PB |
3929 | return 1; |
3930 | } | |
3931 | else if (fp_reg_operand (operand1, mode) | |
3932 | && ((GET_CODE (operand0) == MEM | |
3933 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
3934 | || ((GET_CODE (operand0) == SUBREG) | |
3935 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
3936 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
3937 | && scratch_reg) | |
3938 | { | |
3939 | if (GET_CODE (operand0) == SUBREG) | |
3940 | operand0 = XEXP (operand0, 0); | |
3941 | ||
3942 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3943 | it in SIMODE regardless of what mode it was originally given | |
3944 | to us. */ | |
3945 | scratch_reg = force_mode (SImode, scratch_reg); | |
3946 | ||
3947 | /* D might not fit in 14 bits either; for such cases load D into | |
3948 | scratch reg. */ | |
3949 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
3950 | { | |
3951 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
3952 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
3953 | 0)), | |
3954 | Pmode, | |
3955 | XEXP (XEXP (operand0, 0), | |
3956 | 0), | |
3957 | scratch_reg)); | |
3958 | } | |
3959 | else | |
3960 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
f7df4a84 | 3961 | emit_insn (gen_rtx_SET (gen_rtx_MEM (mode, scratch_reg), operand1)); |
dcc21c4c PB |
3962 | return 1; |
3963 | } | |
3964 | /* Handle secondary reloads for loads of FP registers from constant | |
3965 | expressions by forcing the constant into memory. | |
3966 | ||
3967 | use scratch_reg to hold the address of the memory location. | |
3968 | ||
3969 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
3970 | NO_REGS when presented with a const_int and an register class | |
3971 | containing only FP registers. Doing so unfortunately creates | |
3972 | more problems than it solves. Fix this for 2.5. */ | |
3973 | else if (fp_reg_operand (operand0, mode) | |
3974 | && CONSTANT_P (operand1) | |
3975 | && scratch_reg) | |
3976 | { | |
3977 | rtx xoperands[2]; | |
3978 | ||
3979 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
3980 | it in SIMODE regardless of what mode it was originally given | |
3981 | to us. */ | |
3982 | scratch_reg = force_mode (SImode, scratch_reg); | |
3983 | ||
3984 | /* Force the constant into memory and put the address of the | |
3985 | memory location into scratch_reg. */ | |
3986 | xoperands[0] = scratch_reg; | |
3987 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
f7df4a84 | 3988 | emit_insn (gen_rtx_SET (scratch_reg, xoperands[1])); |
dcc21c4c PB |
3989 | |
3990 | /* Now load the destination register. */ | |
f7df4a84 | 3991 | emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg))); |
dcc21c4c PB |
3992 | return 1; |
3993 | } | |
3994 | ||
3995 | /* Now have insn-emit do whatever it normally does. */ | |
3996 | return 0; | |
3997 | } | |
3998 | ||
01e304f8 RZ |
3999 | /* Split one or more DImode RTL references into pairs of SImode |
4000 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
4001 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
4002 | split and "num" is its length. lo_half and hi_half are output arrays | |
4003 | that parallel "operands". */ | |
4004 | ||
4005 | void | |
4006 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
4007 | { | |
4008 | while (num--) | |
4009 | { | |
4010 | rtx op = operands[num]; | |
4011 | ||
4012 | /* simplify_subreg refuses to split volatile memory addresses, | |
4013 | but we still have to handle it. */ | |
4014 | if (GET_CODE (op) == MEM) | |
4015 | { | |
4016 | lo_half[num] = adjust_address (op, SImode, 4); | |
4017 | hi_half[num] = adjust_address (op, SImode, 0); | |
4018 | } | |
4019 | else | |
4020 | { | |
4021 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
4022 | GET_MODE (op) == VOIDmode | |
4023 | ? DImode : GET_MODE (op), 4); | |
4024 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
4025 | GET_MODE (op) == VOIDmode | |
4026 | ? DImode : GET_MODE (op), 0); | |
4027 | } | |
4028 | } | |
4029 | } | |
4030 | ||
a40ed0f3 KH |
4031 | /* Split X into a base and a constant offset, storing them in *BASE |
4032 | and *OFFSET respectively. */ | |
4033 | ||
4034 | static void | |
4035 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
4036 | { | |
4037 | *offset = 0; | |
4038 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4039 | { | |
4040 | *offset += INTVAL (XEXP (x, 1)); | |
4041 | x = XEXP (x, 0); | |
4042 | } | |
4043 | *base = x; | |
4044 | } | |
4045 | ||
4046 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
4047 | instruction. STORE_P says whether the move is a load or store. | |
4048 | ||
4049 | If the instruction uses post-increment or pre-decrement addressing, | |
4050 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
4051 | adjustment. This adjustment will be made by the first element of | |
4052 | PARALLEL, with the loads or stores starting at element 1. If the | |
4053 | instruction does not use post-increment or pre-decrement addressing, | |
4054 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
4055 | start at element 0. */ | |
4056 | ||
4057 | bool | |
4058 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
4059 | HOST_WIDE_INT automod_offset, bool store_p) | |
4060 | { | |
4061 | rtx base, mem_base, set, mem, reg, last_reg; | |
4062 | HOST_WIDE_INT offset, mem_offset; | |
4063 | int i, first, len; | |
4064 | enum reg_class rclass; | |
4065 | ||
4066 | len = XVECLEN (pattern, 0); | |
4067 | first = (automod_base != NULL); | |
4068 | ||
4069 | if (automod_base) | |
4070 | { | |
4071 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
4072 | if (store_p != (automod_offset < 0)) | |
4073 | return false; | |
4074 | ||
4075 | /* Work out the base and offset for lowest memory location. */ | |
4076 | base = automod_base; | |
4077 | offset = (automod_offset < 0 ? automod_offset : 0); | |
4078 | } | |
4079 | else | |
4080 | { | |
4081 | /* Allow any valid base and offset in the first access. */ | |
4082 | base = NULL; | |
4083 | offset = 0; | |
4084 | } | |
4085 | ||
4086 | last_reg = NULL; | |
4087 | rclass = NO_REGS; | |
4088 | for (i = first; i < len; i++) | |
4089 | { | |
4090 | /* We need a plain SET. */ | |
4091 | set = XVECEXP (pattern, 0, i); | |
4092 | if (GET_CODE (set) != SET) | |
4093 | return false; | |
4094 | ||
4095 | /* Check that we have a memory location... */ | |
4096 | mem = XEXP (set, !store_p); | |
4097 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
4098 | return false; | |
4099 | ||
4100 | /* ...with the right address. */ | |
4101 | if (base == NULL) | |
4102 | { | |
4103 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
4104 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
4105 | There are no mode restrictions for 680x0 besides the | |
4106 | automodification rules enforced above. */ | |
4107 | if (TARGET_COLDFIRE | |
4108 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
4109 | return false; | |
4110 | } | |
4111 | else | |
4112 | { | |
4113 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
4114 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
4115 | return false; | |
4116 | } | |
4117 | ||
4118 | /* Check that we have a register of the required mode and class. */ | |
4119 | reg = XEXP (set, store_p); | |
4120 | if (!REG_P (reg) | |
4121 | || !HARD_REGISTER_P (reg) | |
4122 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
4123 | return false; | |
4124 | ||
4125 | if (last_reg) | |
4126 | { | |
4127 | /* The register must belong to RCLASS and have a higher number | |
4128 | than the register in the previous SET. */ | |
4129 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
4130 | || REGNO (last_reg) >= REGNO (reg)) | |
4131 | return false; | |
4132 | } | |
4133 | else | |
4134 | { | |
4135 | /* Work out which register class we need. */ | |
4136 | if (INT_REGNO_P (REGNO (reg))) | |
4137 | rclass = GENERAL_REGS; | |
4138 | else if (FP_REGNO_P (REGNO (reg))) | |
4139 | rclass = FP_REGS; | |
4140 | else | |
4141 | return false; | |
4142 | } | |
4143 | ||
4144 | last_reg = reg; | |
4145 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
4146 | } | |
4147 | ||
4148 | /* If we have an automodification, check whether the final offset is OK. */ | |
4149 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
4150 | return false; | |
4151 | ||
4152 | /* Reject unprofitable cases. */ | |
4153 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
4154 | return false; | |
4155 | ||
4156 | return true; | |
4157 | } | |
4158 | ||
4159 | /* Return the assembly code template for a movem or fmovem instruction | |
4160 | whose pattern is given by PATTERN. Store the template's operands | |
4161 | in OPERANDS. | |
4162 | ||
4163 | If the instruction uses post-increment or pre-decrement addressing, | |
4164 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
4165 | is true if this is a store instruction. */ | |
4166 | ||
4167 | const char * | |
4168 | m68k_output_movem (rtx *operands, rtx pattern, | |
4169 | HOST_WIDE_INT automod_offset, bool store_p) | |
4170 | { | |
4171 | unsigned int mask; | |
4172 | int i, first; | |
4173 | ||
4174 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
4175 | mask = 0; | |
4176 | first = (automod_offset != 0); | |
4177 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
4178 | { | |
4179 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
4180 | is controlled by bit 15 - X. For all other addressing modes, | |
4181 | register X + D0_REG is controlled by bit X. Confusingly, the | |
4182 | register mask for fmovem is in the opposite order to that for | |
4183 | movem. */ | |
4184 | unsigned int regno; | |
4185 | ||
4186 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
4187 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
4188 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
4189 | if (automod_offset < 0) | |
4190 | { | |
4191 | if (FP_REGNO_P (regno)) | |
4192 | mask |= 1 << (regno - FP0_REG); | |
4193 | else | |
4194 | mask |= 1 << (15 - (regno - D0_REG)); | |
4195 | } | |
4196 | else | |
4197 | { | |
4198 | if (FP_REGNO_P (regno)) | |
4199 | mask |= 1 << (7 - (regno - FP0_REG)); | |
4200 | else | |
4201 | mask |= 1 << (regno - D0_REG); | |
4202 | } | |
4203 | } | |
4204 | CC_STATUS_INIT; | |
4205 | ||
4206 | if (automod_offset == 0) | |
4207 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
4208 | else if (automod_offset < 0) | |
4209 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
4210 | else | |
4211 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
4212 | operands[1] = GEN_INT (mask); | |
4213 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
4214 | { | |
4215 | if (store_p) | |
1fae2d80 | 4216 | return "fmovem %1,%a0"; |
a40ed0f3 | 4217 | else |
1fae2d80 | 4218 | return "fmovem %a0,%1"; |
a40ed0f3 KH |
4219 | } |
4220 | else | |
4221 | { | |
4222 | if (store_p) | |
1fae2d80 | 4223 | return "movem%.l %1,%a0"; |
a40ed0f3 | 4224 | else |
1fae2d80 | 4225 | return "movem%.l %a0,%1"; |
a40ed0f3 KH |
4226 | } |
4227 | } | |
4228 | ||
79e68feb RS |
4229 | /* Return a REG that occurs in ADDR with coefficient 1. |
4230 | ADDR can be effectively incremented by incrementing REG. */ | |
4231 | ||
4232 | static rtx | |
8a4a2253 | 4233 | find_addr_reg (rtx addr) |
79e68feb RS |
4234 | { |
4235 | while (GET_CODE (addr) == PLUS) | |
4236 | { | |
4237 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
4238 | addr = XEXP (addr, 0); | |
4239 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
4240 | addr = XEXP (addr, 1); | |
4241 | else if (CONSTANT_P (XEXP (addr, 0))) | |
4242 | addr = XEXP (addr, 1); | |
4243 | else if (CONSTANT_P (XEXP (addr, 1))) | |
4244 | addr = XEXP (addr, 0); | |
4245 | else | |
4761e388 | 4246 | gcc_unreachable (); |
79e68feb | 4247 | } |
4761e388 NS |
4248 | gcc_assert (GET_CODE (addr) == REG); |
4249 | return addr; | |
79e68feb | 4250 | } |
9ee3c687 | 4251 | |
c16eadc7 | 4252 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 4253 | |
5505f548 | 4254 | const char * |
8a4a2253 | 4255 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
4256 | { |
4257 | if (! operands_match_p (operands[0], operands[1])) | |
4258 | { | |
4259 | if (!ADDRESS_REG_P (operands[1])) | |
4260 | { | |
4261 | rtx tmp = operands[1]; | |
4262 | ||
4263 | operands[1] = operands[2]; | |
4264 | operands[2] = tmp; | |
4265 | } | |
4266 | ||
4267 | /* These insns can result from reloads to access | |
4268 | stack slots over 64k from the frame pointer. */ | |
4269 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 4270 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 4271 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 4272 | if (GET_CODE (operands[2]) == REG) |
4b3d1177 KH |
4273 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
4274 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
4275 | } |
4276 | if (GET_CODE (operands[2]) == CONST_INT) | |
4277 | { | |
9ee3c687 JW |
4278 | if (INTVAL (operands[2]) > 0 |
4279 | && INTVAL (operands[2]) <= 8) | |
4280 | return "addq%.l %2,%0"; | |
4281 | if (INTVAL (operands[2]) < 0 | |
4282 | && INTVAL (operands[2]) >= -8) | |
4283 | { | |
c5c76735 | 4284 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
4285 | return "subq%.l %2,%0"; |
4286 | } | |
4287 | /* On the CPU32 it is faster to use two addql instructions to | |
4288 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 4289 | Likewise for subql. */ |
fe95f2f7 | 4290 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
4291 | { |
4292 | if (INTVAL (operands[2]) > 8 | |
4293 | && INTVAL (operands[2]) <= 16) | |
4294 | { | |
1d8eaa6b | 4295 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 4296 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
4297 | } |
4298 | if (INTVAL (operands[2]) < -8 | |
4299 | && INTVAL (operands[2]) >= -16) | |
4300 | { | |
c5c76735 | 4301 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 4302 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
4303 | } |
4304 | } | |
9ee3c687 JW |
4305 | if (ADDRESS_REG_P (operands[0]) |
4306 | && INTVAL (operands[2]) >= -0x8000 | |
4307 | && INTVAL (operands[2]) < 0x8000) | |
4308 | { | |
fe95f2f7 | 4309 | if (TUNE_68040) |
9ee3c687 JW |
4310 | return "add%.w %2,%0"; |
4311 | else | |
4b3d1177 | 4312 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
4313 | } |
4314 | } | |
4315 | return "add%.l %2,%0"; | |
4316 | } | |
79e68feb | 4317 | |
6cebc6cb BS |
4318 | /* Emit a comparison between OP0 and OP1. Return true iff the comparison |
4319 | was reversed. SC1 is an SImode scratch reg, and SC2 a DImode scratch reg, | |
4320 | as needed. CODE is the code of the comparison, we return it unchanged or | |
4321 | swapped, as necessary. */ | |
4322 | rtx_code | |
4323 | m68k_output_compare_di (rtx op0, rtx op1, rtx sc1, rtx sc2, rtx_insn *insn, | |
4324 | rtx_code code) | |
79e68feb | 4325 | { |
6cebc6cb BS |
4326 | rtx ops[4]; |
4327 | ops[0] = op0; | |
4328 | ops[1] = op1; | |
4329 | ops[2] = sc1; | |
4330 | ops[3] = sc2; | |
4331 | if (op1 == const0_rtx) | |
4332 | { | |
4333 | if (!REG_P (op0) || ADDRESS_REG_P (op0)) | |
79e68feb | 4334 | { |
6cebc6cb BS |
4335 | rtx xoperands[2]; |
4336 | ||
4337 | xoperands[0] = sc2; | |
4338 | xoperands[1] = op0; | |
4339 | output_move_double (xoperands); | |
4340 | output_asm_insn ("neg%.l %R0\n\tnegx%.l %0", xoperands); | |
4341 | return swap_condition (code); | |
79e68feb | 4342 | } |
6cebc6cb | 4343 | if (find_reg_note (insn, REG_DEAD, op0)) |
79e68feb | 4344 | { |
6cebc6cb BS |
4345 | output_asm_insn ("neg%.l %R0\n\tnegx%.l %0", ops); |
4346 | return swap_condition (code); | |
79e68feb | 4347 | } |
6cebc6cb | 4348 | else |
79e68feb | 4349 | { |
6cebc6cb BS |
4350 | /* 'sub' clears %1, and also clears the X cc bit. |
4351 | 'tst' sets the Z cc bit according to the low part of the DImode | |
4352 | operand. | |
4353 | 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high | |
4354 | part. */ | |
4355 | output_asm_insn ("sub%.l %2,%2\n\ttst%.l %R0\n\tsubx%.l %2,%0", ops); | |
4356 | return code; | |
79e68feb RS |
4357 | } |
4358 | } | |
6cebc6cb BS |
4359 | |
4360 | if (rtx_equal_p (sc2, op0)) | |
4361 | { | |
4362 | output_asm_insn ("sub%.l %R1,%R3\n\tsubx%.l %1,%3", ops); | |
4363 | return code; | |
4364 | } | |
79e68feb | 4365 | else |
6cebc6cb BS |
4366 | { |
4367 | output_asm_insn ("sub%.l %R0,%R3\n\tsubx%.l %0,%3", ops); | |
4368 | return swap_condition (code); | |
4369 | } | |
4370 | } | |
4371 | ||
4372 | static void | |
4373 | remember_compare_flags (rtx op0, rtx op1) | |
4374 | { | |
4375 | if (side_effects_p (op0) || side_effects_p (op1)) | |
79e68feb | 4376 | CC_STATUS_INIT; |
6cebc6cb BS |
4377 | else |
4378 | { | |
4379 | flags_compare_op0 = op0; | |
4380 | flags_compare_op1 = op1; | |
4381 | flags_operand1 = flags_operand2 = NULL_RTX; | |
4382 | flags_valid = FLAGS_VALID_SET; | |
4383 | } | |
4384 | } | |
a126dc3a | 4385 | |
6cebc6cb BS |
4386 | /* Emit a comparison between OP0 and OP1. CODE is the code of the |
4387 | comparison. It is returned, potentially modified if necessary. */ | |
4388 | rtx_code | |
4389 | m68k_output_compare_si (rtx op0, rtx op1, rtx_code code) | |
4390 | { | |
4391 | rtx_code tmp = m68k_find_flags_value (op0, op1, code); | |
4392 | if (tmp != UNKNOWN) | |
4393 | return tmp; | |
4394 | ||
4395 | remember_compare_flags (op0, op1); | |
4396 | ||
4397 | rtx ops[2]; | |
4398 | ops[0] = op0; | |
4399 | ops[1] = op1; | |
4400 | if (op1 == const0_rtx && (TARGET_68020 || TARGET_COLDFIRE || !ADDRESS_REG_P (op0))) | |
4401 | output_asm_insn ("tst%.l %0", ops); | |
4402 | else if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM) | |
4403 | output_asm_insn ("cmpm%.l %1,%0", ops); | |
4404 | else if (REG_P (op1) | |
4405 | || (!REG_P (op0) && GET_CODE (op0) != MEM)) | |
4406 | { | |
4407 | output_asm_insn ("cmp%.l %d0,%d1", ops); | |
4408 | std::swap (flags_compare_op0, flags_compare_op1); | |
4409 | return swap_condition (code); | |
4410 | } | |
4411 | else if (!TARGET_COLDFIRE | |
4412 | && ADDRESS_REG_P (op0) | |
4413 | && GET_CODE (op1) == CONST_INT | |
4414 | && INTVAL (op1) < 0x8000 | |
4415 | && INTVAL (op1) >= -0x8000) | |
4416 | output_asm_insn ("cmp%.w %1,%0", ops); | |
4417 | else | |
4418 | output_asm_insn ("cmp%.l %d1,%d0", ops); | |
4419 | return code; | |
4420 | } | |
1d8eaa6b | 4421 | |
6cebc6cb BS |
4422 | /* Emit a comparison between OP0 and OP1. CODE is the code of the |
4423 | comparison. It is returned, potentially modified if necessary. */ | |
4424 | rtx_code | |
4425 | m68k_output_compare_hi (rtx op0, rtx op1, rtx_code code) | |
4426 | { | |
4427 | rtx_code tmp = m68k_find_flags_value (op0, op1, code); | |
4428 | if (tmp != UNKNOWN) | |
4429 | return tmp; | |
4430 | ||
4431 | remember_compare_flags (op0, op1); | |
4432 | ||
4433 | rtx ops[2]; | |
4434 | ops[0] = op0; | |
4435 | ops[1] = op1; | |
4436 | if (op1 == const0_rtx) | |
4437 | output_asm_insn ("tst%.w %d0", ops); | |
4438 | else if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM) | |
4439 | output_asm_insn ("cmpm%.w %1,%0", ops); | |
4440 | else if ((REG_P (op1) && !ADDRESS_REG_P (op1)) | |
4441 | || (!REG_P (op0) && GET_CODE (op0) != MEM)) | |
4442 | { | |
4443 | output_asm_insn ("cmp%.w %d0,%d1", ops); | |
4444 | std::swap (flags_compare_op0, flags_compare_op1); | |
4445 | return swap_condition (code); | |
4446 | } | |
4447 | else | |
4448 | output_asm_insn ("cmp%.w %d1,%d0", ops); | |
4449 | return code; | |
4450 | } | |
4451 | ||
4452 | /* Emit a comparison between OP0 and OP1. CODE is the code of the | |
4453 | comparison. It is returned, potentially modified if necessary. */ | |
4454 | rtx_code | |
4455 | m68k_output_compare_qi (rtx op0, rtx op1, rtx_code code) | |
4456 | { | |
4457 | rtx_code tmp = m68k_find_flags_value (op0, op1, code); | |
4458 | if (tmp != UNKNOWN) | |
4459 | return tmp; | |
4460 | ||
4461 | remember_compare_flags (op0, op1); | |
4462 | ||
4463 | rtx ops[2]; | |
4464 | ops[0] = op0; | |
4465 | ops[1] = op1; | |
4466 | if (op1 == const0_rtx) | |
4467 | output_asm_insn ("tst%.b %d0", ops); | |
4468 | else if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM) | |
4469 | output_asm_insn ("cmpm%.b %1,%0", ops); | |
4470 | else if (REG_P (op1) || (!REG_P (op0) && GET_CODE (op0) != MEM)) | |
4471 | { | |
4472 | output_asm_insn ("cmp%.b %d0,%d1", ops); | |
4473 | std::swap (flags_compare_op0, flags_compare_op1); | |
4474 | return swap_condition (code); | |
4475 | } | |
4476 | else | |
4477 | output_asm_insn ("cmp%.b %d1,%d0", ops); | |
4478 | return code; | |
4479 | } | |
4480 | ||
4481 | /* Emit a comparison between OP0 and OP1. CODE is the code of the | |
4482 | comparison. It is returned, potentially modified if necessary. */ | |
4483 | rtx_code | |
4484 | m68k_output_compare_fp (rtx op0, rtx op1, rtx_code code) | |
4485 | { | |
4486 | rtx_code tmp = m68k_find_flags_value (op0, op1, code); | |
4487 | if (tmp != UNKNOWN) | |
4488 | return tmp; | |
4489 | ||
4490 | rtx ops[2]; | |
4491 | ops[0] = op0; | |
4492 | ops[1] = op1; | |
4493 | ||
4494 | remember_compare_flags (op0, op1); | |
4495 | ||
4496 | machine_mode mode = GET_MODE (op0); | |
4497 | std::string prec = mode == SFmode ? "s" : mode == DFmode ? "d" : "x"; | |
4498 | ||
4499 | if (op1 == CONST0_RTX (GET_MODE (op0))) | |
4500 | { | |
4501 | if (FP_REG_P (op0)) | |
45a45488 BS |
4502 | { |
4503 | if (TARGET_COLDFIRE_FPU) | |
4504 | output_asm_insn ("ftst%.d %0", ops); | |
4505 | else | |
4506 | output_asm_insn ("ftst%.x %0", ops); | |
4507 | } | |
6cebc6cb BS |
4508 | else |
4509 | output_asm_insn (("ftst%." + prec + " %0").c_str (), ops); | |
4510 | return code; | |
4511 | } | |
4512 | ||
4513 | switch (which_alternative) | |
4514 | { | |
4515 | case 0: | |
45a45488 BS |
4516 | if (TARGET_COLDFIRE_FPU) |
4517 | output_asm_insn ("fcmp%.d %1,%0", ops); | |
4518 | else | |
4519 | output_asm_insn ("fcmp%.x %1,%0", ops); | |
6cebc6cb BS |
4520 | break; |
4521 | case 1: | |
4522 | output_asm_insn (("fcmp%." + prec + " %f1,%0").c_str (), ops); | |
4523 | break; | |
4524 | case 2: | |
4525 | output_asm_insn (("fcmp%." + prec + " %0,%f1").c_str (), ops); | |
4526 | std::swap (flags_compare_op0, flags_compare_op1); | |
4527 | return swap_condition (code); | |
4528 | case 3: | |
4529 | /* This is the ftst case, handled earlier. */ | |
4530 | gcc_unreachable (); | |
4531 | } | |
4532 | return code; | |
4533 | } | |
4534 | ||
4535 | /* Return an output template for a branch with CODE. */ | |
4536 | const char * | |
4537 | m68k_output_branch_integer (rtx_code code) | |
4538 | { | |
4539 | switch (code) | |
4540 | { | |
4541 | case EQ: | |
4542 | return "jeq %l3"; | |
4543 | case NE: | |
4544 | return "jne %l3"; | |
4545 | case GT: | |
4546 | return "jgt %l3"; | |
4547 | case GTU: | |
4548 | return "jhi %l3"; | |
4549 | case LT: | |
4550 | return "jlt %l3"; | |
4551 | case LTU: | |
4552 | return "jcs %l3"; | |
4553 | case GE: | |
4554 | return "jge %l3"; | |
4555 | case GEU: | |
4556 | return "jcc %l3"; | |
4557 | case LE: | |
4558 | return "jle %l3"; | |
4559 | case LEU: | |
4560 | return "jls %l3"; | |
4561 | case PLUS: | |
4562 | return "jpl %l3"; | |
4563 | case MINUS: | |
4564 | return "jmi %l3"; | |
4565 | default: | |
4566 | gcc_unreachable (); | |
4567 | } | |
4568 | } | |
4569 | ||
4570 | /* Return an output template for a reversed branch with CODE. */ | |
4571 | const char * | |
4572 | m68k_output_branch_integer_rev (rtx_code code) | |
4573 | { | |
4574 | switch (code) | |
4575 | { | |
4576 | case EQ: | |
4577 | return "jne %l3"; | |
4578 | case NE: | |
4579 | return "jeq %l3"; | |
4580 | case GT: | |
4581 | return "jle %l3"; | |
4582 | case GTU: | |
4583 | return "jls %l3"; | |
4584 | case LT: | |
4585 | return "jge %l3"; | |
4586 | case LTU: | |
4587 | return "jcc %l3"; | |
4588 | case GE: | |
4589 | return "jlt %l3"; | |
4590 | case GEU: | |
4591 | return "jcs %l3"; | |
4592 | case LE: | |
4593 | return "jgt %l3"; | |
4594 | case LEU: | |
4595 | return "jhi %l3"; | |
4596 | case PLUS: | |
4597 | return "jmi %l3"; | |
4598 | case MINUS: | |
4599 | return "jpl %l3"; | |
4600 | default: | |
4601 | gcc_unreachable (); | |
4602 | } | |
4603 | } | |
4604 | ||
4605 | /* Return an output template for a scc instruction with CODE. */ | |
4606 | const char * | |
4607 | m68k_output_scc (rtx_code code) | |
4608 | { | |
4609 | switch (code) | |
4610 | { | |
4611 | case EQ: | |
4612 | return "seq %0"; | |
4613 | case NE: | |
4614 | return "sne %0"; | |
4615 | case GT: | |
4616 | return "sgt %0"; | |
4617 | case GTU: | |
4618 | return "shi %0"; | |
4619 | case LT: | |
4620 | return "slt %0"; | |
4621 | case LTU: | |
4622 | return "scs %0"; | |
4623 | case GE: | |
4624 | return "sge %0"; | |
4625 | case GEU: | |
4626 | return "scc %0"; | |
4627 | case LE: | |
4628 | return "sle %0"; | |
4629 | case LEU: | |
4630 | return "sls %0"; | |
4631 | case PLUS: | |
4632 | return "spl %0"; | |
4633 | case MINUS: | |
4634 | return "smi %0"; | |
4635 | default: | |
4636 | gcc_unreachable (); | |
4637 | } | |
4638 | } | |
4639 | ||
4640 | /* Return an output template for a floating point branch | |
4641 | instruction with CODE. */ | |
4642 | const char * | |
4643 | m68k_output_branch_float (rtx_code code) | |
4644 | { | |
4645 | switch (code) | |
4646 | { | |
4647 | case EQ: | |
4648 | return "fjeq %l3"; | |
4649 | case NE: | |
4650 | return "fjne %l3"; | |
4651 | case GT: | |
4652 | return "fjgt %l3"; | |
4653 | case LT: | |
4654 | return "fjlt %l3"; | |
4655 | case GE: | |
4656 | return "fjge %l3"; | |
4657 | case LE: | |
4658 | return "fjle %l3"; | |
4659 | case ORDERED: | |
4660 | return "fjor %l3"; | |
4661 | case UNORDERED: | |
4662 | return "fjun %l3"; | |
4663 | case UNEQ: | |
4664 | return "fjueq %l3"; | |
4665 | case UNGE: | |
4666 | return "fjuge %l3"; | |
4667 | case UNGT: | |
4668 | return "fjugt %l3"; | |
4669 | case UNLE: | |
4670 | return "fjule %l3"; | |
4671 | case UNLT: | |
4672 | return "fjult %l3"; | |
4673 | case LTGT: | |
4674 | return "fjogl %l3"; | |
4675 | default: | |
4676 | gcc_unreachable (); | |
4677 | } | |
4678 | } | |
4679 | ||
4680 | /* Return an output template for a reversed floating point branch | |
4681 | instruction with CODE. */ | |
4682 | const char * | |
4683 | m68k_output_branch_float_rev (rtx_code code) | |
4684 | { | |
4685 | switch (code) | |
4686 | { | |
4687 | case EQ: | |
4688 | return "fjne %l3"; | |
4689 | case NE: | |
4690 | return "fjeq %l3"; | |
4691 | case GT: | |
4692 | return "fjngt %l3"; | |
4693 | case LT: | |
4694 | return "fjnlt %l3"; | |
4695 | case GE: | |
4696 | return "fjnge %l3"; | |
4697 | case LE: | |
4698 | return "fjnle %l3"; | |
4699 | case ORDERED: | |
4700 | return "fjun %l3"; | |
4701 | case UNORDERED: | |
4702 | return "fjor %l3"; | |
4703 | case UNEQ: | |
4704 | return "fjogl %l3"; | |
4705 | case UNGE: | |
4706 | return "fjolt %l3"; | |
4707 | case UNGT: | |
4708 | return "fjole %l3"; | |
4709 | case UNLE: | |
4710 | return "fjogt %l3"; | |
4711 | case UNLT: | |
4712 | return "fjoge %l3"; | |
4713 | case LTGT: | |
4714 | return "fjueq %l3"; | |
4715 | default: | |
4716 | gcc_unreachable (); | |
4717 | } | |
4718 | } | |
4719 | ||
4720 | /* Return an output template for a floating point scc | |
4721 | instruction with CODE. */ | |
4722 | const char * | |
4723 | m68k_output_scc_float (rtx_code code) | |
4724 | { | |
4725 | switch (code) | |
4726 | { | |
4727 | case EQ: | |
4728 | return "fseq %0"; | |
4729 | case NE: | |
4730 | return "fsne %0"; | |
4731 | case GT: | |
4732 | return "fsgt %0"; | |
4733 | case GTU: | |
4734 | return "fshi %0"; | |
4735 | case LT: | |
4736 | return "fslt %0"; | |
4737 | case GE: | |
4738 | return "fsge %0"; | |
4739 | case LE: | |
4740 | return "fsle %0"; | |
4741 | case ORDERED: | |
4742 | return "fsor %0"; | |
4743 | case UNORDERED: | |
4744 | return "fsun %0"; | |
4745 | case UNEQ: | |
4746 | return "fsueq %0"; | |
4747 | case UNGE: | |
4748 | return "fsuge %0"; | |
4749 | case UNGT: | |
4750 | return "fsugt %0"; | |
4751 | case UNLE: | |
4752 | return "fsule %0"; | |
4753 | case UNLT: | |
4754 | return "fsult %0"; | |
4755 | case LTGT: | |
4756 | return "fsogl %0"; | |
4757 | default: | |
4758 | gcc_unreachable (); | |
67595cbb | 4759 | } |
79e68feb RS |
4760 | } |
4761 | \f | |
5505f548 | 4762 | const char * |
8a4a2253 | 4763 | output_move_const_double (rtx *operands) |
79e68feb | 4764 | { |
1a8965c4 | 4765 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 4766 | |
1a8965c4 | 4767 | if (code != 0) |
79e68feb | 4768 | { |
1a8965c4 | 4769 | static char buf[40]; |
79e68feb | 4770 | |
3b4b85c9 | 4771 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 4772 | return buf; |
79e68feb | 4773 | } |
1a8965c4 | 4774 | return "fmove%.d %1,%0"; |
79e68feb RS |
4775 | } |
4776 | ||
5505f548 | 4777 | const char * |
8a4a2253 | 4778 | output_move_const_single (rtx *operands) |
79e68feb | 4779 | { |
1a8965c4 | 4780 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 4781 | |
1a8965c4 | 4782 | if (code != 0) |
79e68feb | 4783 | { |
1a8965c4 | 4784 | static char buf[40]; |
79e68feb | 4785 | |
3b4b85c9 | 4786 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 4787 | return buf; |
79e68feb | 4788 | } |
1a8965c4 | 4789 | return "fmove%.s %f1,%0"; |
79e68feb RS |
4790 | } |
4791 | ||
4792 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
4793 | from the "fmovecr" instruction. | |
4794 | The value, anded with 0xff, gives the code to use in fmovecr | |
4795 | to get the desired constant. */ | |
4796 | ||
7a1929e1 | 4797 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
4798 | |
4799 | static int inited_68881_table = 0; | |
4800 | ||
5505f548 | 4801 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
4802 | "0.0", |
4803 | "1.0", | |
4804 | "10.0", | |
4805 | "100.0", | |
4806 | "10000.0", | |
4807 | "1e8", | |
4808 | "1e16" | |
a0a7fbc9 | 4809 | }; |
c1cfb2ae | 4810 | |
8b60264b | 4811 | static const int codes_68881[7] = { |
c1cfb2ae RS |
4812 | 0x0f, |
4813 | 0x32, | |
4814 | 0x33, | |
4815 | 0x34, | |
4816 | 0x35, | |
4817 | 0x36, | |
4818 | 0x37 | |
a0a7fbc9 | 4819 | }; |
c1cfb2ae RS |
4820 | |
4821 | REAL_VALUE_TYPE values_68881[7]; | |
4822 | ||
4823 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 4824 | strings_68881 to binary. */ |
c1cfb2ae RS |
4825 | |
4826 | void | |
8a4a2253 | 4827 | init_68881_table (void) |
c1cfb2ae RS |
4828 | { |
4829 | int i; | |
4830 | REAL_VALUE_TYPE r; | |
ef4bddc2 | 4831 | machine_mode mode; |
c1cfb2ae | 4832 | |
16d82c3c | 4833 | mode = SFmode; |
c1cfb2ae RS |
4834 | for (i = 0; i < 7; i++) |
4835 | { | |
4836 | if (i == 6) | |
16d82c3c | 4837 | mode = DFmode; |
c1cfb2ae RS |
4838 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
4839 | values_68881[i] = r; | |
4840 | } | |
4841 | inited_68881_table = 1; | |
4842 | } | |
79e68feb RS |
4843 | |
4844 | int | |
8a4a2253 | 4845 | standard_68881_constant_p (rtx x) |
79e68feb | 4846 | { |
34a72c33 | 4847 | const REAL_VALUE_TYPE *r; |
c1cfb2ae | 4848 | int i; |
79e68feb | 4849 | |
e18db50d | 4850 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 4851 | used at all on those chips. */ |
9cf106c8 | 4852 | if (TUNE_68040_60) |
79e68feb RS |
4853 | return 0; |
4854 | ||
c1cfb2ae RS |
4855 | if (! inited_68881_table) |
4856 | init_68881_table (); | |
4857 | ||
34a72c33 | 4858 | r = CONST_DOUBLE_REAL_VALUE (x); |
c1cfb2ae | 4859 | |
1a25c6b1 | 4860 | /* Use real_identical instead of real_equal so that -0.0 is rejected. */ |
c1cfb2ae RS |
4861 | for (i = 0; i < 6; i++) |
4862 | { | |
34a72c33 | 4863 | if (real_identical (r, &values_68881[i])) |
c1cfb2ae RS |
4864 | return (codes_68881[i]); |
4865 | } | |
4866 | ||
79e68feb RS |
4867 | if (GET_MODE (x) == SFmode) |
4868 | return 0; | |
c1cfb2ae | 4869 | |
34a72c33 | 4870 | if (real_equal (r, &values_68881[6])) |
c1cfb2ae RS |
4871 | return (codes_68881[6]); |
4872 | ||
79e68feb RS |
4873 | /* larger powers of ten in the constants ram are not used |
4874 | because they are not equal to a `double' C constant. */ | |
4875 | return 0; | |
4876 | } | |
4877 | ||
4878 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
4879 | or 0 if X is not a power of 2. */ | |
4880 | ||
4881 | int | |
8a4a2253 | 4882 | floating_exact_log2 (rtx x) |
79e68feb | 4883 | { |
34a72c33 RS |
4884 | const REAL_VALUE_TYPE *r; |
4885 | REAL_VALUE_TYPE r1; | |
eaff3bf8 | 4886 | int exp; |
79e68feb | 4887 | |
34a72c33 | 4888 | r = CONST_DOUBLE_REAL_VALUE (x); |
79e68feb | 4889 | |
34a72c33 | 4890 | if (real_less (r, &dconst1)) |
79e68feb RS |
4891 | return 0; |
4892 | ||
34a72c33 | 4893 | exp = real_exponent (r); |
6ef9a246 | 4894 | real_2expN (&r1, exp, DFmode); |
34a72c33 | 4895 | if (real_equal (&r1, r)) |
eaff3bf8 RH |
4896 | return exp; |
4897 | ||
79e68feb RS |
4898 | return 0; |
4899 | } | |
4900 | \f | |
79e68feb RS |
4901 | /* A C compound statement to output to stdio stream STREAM the |
4902 | assembler syntax for an instruction operand X. X is an RTL | |
4903 | expression. | |
4904 | ||
4905 | CODE is a value that can be used to specify one of several ways | |
4906 | of printing the operand. It is used when identical operands | |
4907 | must be printed differently depending on the context. CODE | |
4908 | comes from the `%' specification that was used to request | |
4909 | printing of the operand. If the specification was just `%DIGIT' | |
4910 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
4911 | is the ASCII code for LTR. | |
4912 | ||
4913 | If X is a register, this macro should print the register's name. | |
4914 | The names can be found in an array `reg_names' whose type is | |
4915 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
4916 | ||
4917 | When the machine description has a specification `%PUNCT' (a `%' | |
4918 | followed by a punctuation character), this macro is called with | |
4919 | a null pointer for X and the punctuation character for CODE. | |
4920 | ||
4921 | The m68k specific codes are: | |
4922 | ||
4923 | '.' for dot needed in Motorola-style opcode names. | |
4924 | '-' for an operand pushing on the stack: | |
4925 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
4926 | '+' for an operand pushing on the stack: | |
4927 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
4928 | '@' for a reference to the top word on the stack: | |
4929 | sp@, (sp) or (%sp) depending on the style of syntax. | |
4930 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 4931 | but & in SGS syntax). |
79e68feb RS |
4932 | '!' for the cc register (used in an `and to cc' insn). |
4933 | '$' for the letter `s' in an op code, but only on the 68040. | |
4934 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 4935 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 4936 | '?' for m68k_library_id_string |
79e68feb RS |
4937 | |
4938 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
4939 | 'd' to force memory addressing to be absolute, not relative. | |
4940 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
4941 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
4942 | or print pair of registers as rx:ry. | |
29ca003a RS |
4943 | 'p' print an address with @PLTPC attached, but only if the operand |
4944 | is not locally-bound. */ | |
79e68feb RS |
4945 | |
4946 | void | |
8a4a2253 | 4947 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 4948 | { |
ede9446c AS |
4949 | if (op != NULL_RTX) |
4950 | m68k_adjust_decorated_operand (op); | |
4951 | ||
79e68feb RS |
4952 | if (letter == '.') |
4953 | { | |
e6d98cb0 BI |
4954 | if (MOTOROLA) |
4955 | fprintf (file, "."); | |
79e68feb RS |
4956 | } |
4957 | else if (letter == '#') | |
e6d98cb0 | 4958 | asm_fprintf (file, "%I"); |
79e68feb | 4959 | else if (letter == '-') |
4b3d1177 | 4960 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 4961 | else if (letter == '+') |
4b3d1177 | 4962 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 4963 | else if (letter == '@') |
4b3d1177 | 4964 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 4965 | else if (letter == '!') |
e6d98cb0 | 4966 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
4967 | else if (letter == '$') |
4968 | { | |
b101567e | 4969 | if (TARGET_68040) |
e6d98cb0 | 4970 | fprintf (file, "s"); |
79e68feb RS |
4971 | } |
4972 | else if (letter == '&') | |
4973 | { | |
b101567e | 4974 | if (TARGET_68040) |
e6d98cb0 | 4975 | fprintf (file, "d"); |
79e68feb | 4976 | } |
2ac5f14a | 4977 | else if (letter == '/') |
e6d98cb0 | 4978 | asm_fprintf (file, "%R"); |
a40ed0f3 KH |
4979 | else if (letter == '?') |
4980 | asm_fprintf (file, m68k_library_id_string); | |
29ca003a | 4981 | else if (letter == 'p') |
2c8ec431 | 4982 | { |
29ca003a RS |
4983 | output_addr_const (file, op); |
4984 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
4985 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 4986 | } |
79e68feb RS |
4987 | else if (GET_CODE (op) == REG) |
4988 | { | |
1a8965c4 AS |
4989 | if (letter == 'R') |
4990 | /* Print out the second register name of a register pair. | |
4991 | I.e., R (6) => 7. */ | |
01bbf777 | 4992 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 4993 | else |
01bbf777 | 4994 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
4995 | } |
4996 | else if (GET_CODE (op) == MEM) | |
4997 | { | |
cc8ca59e | 4998 | output_address (GET_MODE (op), XEXP (op, 0)); |
79e68feb RS |
4999 | if (letter == 'd' && ! TARGET_68020 |
5000 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
5001 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
5002 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
5003 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
4b3d1177 | 5004 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 5005 | } |
79e68feb RS |
5006 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
5007 | { | |
6ae89ea8 | 5008 | long l; |
34a72c33 | 5009 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
429ce992 | 5010 | asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF); |
c1cfb2ae RS |
5011 | } |
5012 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
5013 | { | |
6ae89ea8 | 5014 | long l[3]; |
34a72c33 | 5015 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
429ce992 AS |
5016 | asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF, |
5017 | l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF); | |
79e68feb | 5018 | } |
e2c0a924 | 5019 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 5020 | { |
6ae89ea8 | 5021 | long l[2]; |
34a72c33 | 5022 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
429ce992 | 5023 | asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF); |
79e68feb RS |
5024 | } |
5025 | else | |
5026 | { | |
2c8ec431 DL |
5027 | /* Use `print_operand_address' instead of `output_addr_const' |
5028 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 5029 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
5030 | if (TARGET_PCREL |
5031 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
5032 | print_operand_address (file, op); | |
5033 | else | |
5034 | output_addr_const (file, op); | |
79e68feb RS |
5035 | } |
5036 | } | |
5037 | ||
75df395f MK |
5038 | /* Return string for TLS relocation RELOC. */ |
5039 | ||
5040 | static const char * | |
5041 | m68k_get_reloc_decoration (enum m68k_reloc reloc) | |
5042 | { | |
5043 | /* To my knowledge, !MOTOROLA assemblers don't support TLS. */ | |
5044 | gcc_assert (MOTOROLA || reloc == RELOC_GOT); | |
5045 | ||
5046 | switch (reloc) | |
5047 | { | |
5048 | case RELOC_GOT: | |
5049 | if (MOTOROLA) | |
5050 | { | |
5051 | if (flag_pic == 1 && TARGET_68020) | |
5052 | return "@GOT.w"; | |
5053 | else | |
5054 | return "@GOT"; | |
5055 | } | |
5056 | else | |
5057 | { | |
5058 | if (TARGET_68020) | |
5059 | { | |
5060 | switch (flag_pic) | |
5061 | { | |
5062 | case 1: | |
5063 | return ":w"; | |
5064 | case 2: | |
5065 | return ":l"; | |
5066 | default: | |
5067 | return ""; | |
5068 | } | |
5069 | } | |
5070 | } | |
b1a2b0ba | 5071 | gcc_unreachable (); |
75df395f MK |
5072 | |
5073 | case RELOC_TLSGD: | |
5074 | return "@TLSGD"; | |
5075 | ||
5076 | case RELOC_TLSLDM: | |
5077 | return "@TLSLDM"; | |
5078 | ||
5079 | case RELOC_TLSLDO: | |
5080 | return "@TLSLDO"; | |
5081 | ||
5082 | case RELOC_TLSIE: | |
5083 | return "@TLSIE"; | |
5084 | ||
5085 | case RELOC_TLSLE: | |
5086 | return "@TLSLE"; | |
5087 | ||
5088 | default: | |
5089 | gcc_unreachable (); | |
5090 | } | |
5091 | } | |
5092 | ||
cb69db4f | 5093 | /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */ |
884316ff | 5094 | |
cb69db4f | 5095 | static bool |
884316ff JM |
5096 | m68k_output_addr_const_extra (FILE *file, rtx x) |
5097 | { | |
75df395f MK |
5098 | if (GET_CODE (x) == UNSPEC) |
5099 | { | |
5100 | switch (XINT (x, 1)) | |
5101 | { | |
5102 | case UNSPEC_RELOC16: | |
5103 | case UNSPEC_RELOC32: | |
5104 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
f878882b AS |
5105 | fputs (m68k_get_reloc_decoration |
5106 | ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file); | |
75df395f | 5107 | return true; |
884316ff | 5108 | |
75df395f MK |
5109 | default: |
5110 | break; | |
5111 | } | |
5112 | } | |
5113 | ||
5114 | return false; | |
5115 | } | |
5116 | ||
5117 | /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ | |
5118 | ||
5119 | static void | |
5120 | m68k_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
5121 | { | |
5122 | gcc_assert (size == 4); | |
5123 | fputs ("\t.long\t", file); | |
5124 | output_addr_const (file, x); | |
5125 | fputs ("@TLSLDO+0x8000", file); | |
884316ff JM |
5126 | } |
5127 | ||
7b0f476d AS |
5128 | /* In the name of slightly smaller debug output, and to cater to |
5129 | general assembler lossage, recognize various UNSPEC sequences | |
5130 | and turn them back into a direct symbol reference. */ | |
5131 | ||
5132 | static rtx | |
33d67485 | 5133 | m68k_delegitimize_address (rtx orig_x) |
7b0f476d | 5134 | { |
8390b335 AS |
5135 | rtx x; |
5136 | struct m68k_address addr; | |
5137 | rtx unspec; | |
7b0f476d | 5138 | |
33d67485 | 5139 | orig_x = delegitimize_mem_from_attrs (orig_x); |
8390b335 AS |
5140 | x = orig_x; |
5141 | if (MEM_P (x)) | |
5142 | x = XEXP (x, 0); | |
5143 | ||
5144 | if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) | |
33d67485 AS |
5145 | return orig_x; |
5146 | ||
8390b335 AS |
5147 | if (!m68k_decompose_address (GET_MODE (x), x, false, &addr) |
5148 | || addr.offset == NULL_RTX | |
5149 | || GET_CODE (addr.offset) != CONST) | |
5150 | return orig_x; | |
7b0f476d | 5151 | |
8390b335 AS |
5152 | unspec = XEXP (addr.offset, 0); |
5153 | if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1))) | |
5154 | unspec = XEXP (unspec, 0); | |
5155 | if (GET_CODE (unspec) != UNSPEC | |
5156 | || (XINT (unspec, 1) != UNSPEC_RELOC16 | |
5157 | && XINT (unspec, 1) != UNSPEC_RELOC32)) | |
5158 | return orig_x; | |
5159 | x = XVECEXP (unspec, 0, 0); | |
92cf7399 | 5160 | gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF); |
8390b335 AS |
5161 | if (unspec != XEXP (addr.offset, 0)) |
5162 | x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1)); | |
5163 | if (addr.index) | |
7b0f476d | 5164 | { |
8390b335 AS |
5165 | rtx idx = addr.index; |
5166 | if (addr.scale != 1) | |
5167 | idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale)); | |
5168 | x = gen_rtx_PLUS (Pmode, idx, x); | |
7b0f476d | 5169 | } |
8390b335 AS |
5170 | if (addr.base) |
5171 | x = gen_rtx_PLUS (Pmode, addr.base, x); | |
5172 | if (MEM_P (orig_x)) | |
5173 | x = replace_equiv_address_nv (orig_x, x); | |
5174 | return x; | |
7b0f476d AS |
5175 | } |
5176 | ||
79e68feb RS |
5177 | \f |
5178 | /* A C compound statement to output to stdio stream STREAM the | |
5179 | assembler syntax for an instruction operand that is a memory | |
5180 | reference whose address is ADDR. ADDR is an RTL expression. | |
5181 | ||
5182 | Note that this contains a kludge that knows that the only reason | |
5183 | we have an address (plus (label_ref...) (reg...)) when not generating | |
5184 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
5185 | generates a label LInnn: on such an insn. | |
5186 | ||
5187 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
5188 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
5189 | ||
79e68feb RS |
5190 | This routine is responsible for distinguishing between -fpic and -fPIC |
5191 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
5192 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
5193 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb RS |
5194 | |
5195 | void | |
8a4a2253 | 5196 | print_operand_address (FILE *file, rtx addr) |
79e68feb | 5197 | { |
fc2241eb RS |
5198 | struct m68k_address address; |
5199 | ||
ede9446c AS |
5200 | m68k_adjust_decorated_operand (addr); |
5201 | ||
fc2241eb RS |
5202 | if (!m68k_decompose_address (QImode, addr, true, &address)) |
5203 | gcc_unreachable (); | |
5204 | ||
5205 | if (address.code == PRE_DEC) | |
4b3d1177 KH |
5206 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", |
5207 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb | 5208 | else if (address.code == POST_INC) |
4b3d1177 KH |
5209 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", |
5210 | M68K_REGNAME (REGNO (address.base))); | |
fc2241eb RS |
5211 | else if (!address.base && !address.index) |
5212 | { | |
5213 | /* A constant address. */ | |
5214 | gcc_assert (address.offset == addr); | |
5215 | if (GET_CODE (addr) == CONST_INT) | |
5216 | { | |
5217 | /* (xxx).w or (xxx).l. */ | |
5218 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
4b3d1177 | 5219 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); |
a0a7fbc9 | 5220 | else |
fc2241eb | 5221 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
a0a7fbc9 | 5222 | } |
fc2241eb | 5223 | else if (TARGET_PCREL) |
a0a7fbc9 | 5224 | { |
fc2241eb RS |
5225 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
5226 | fputc ('(', file); | |
5227 | output_addr_const (file, addr); | |
5228 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
a0a7fbc9 | 5229 | } |
fc2241eb | 5230 | else |
a0a7fbc9 | 5231 | { |
fc2241eb RS |
5232 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
5233 | name ends in `.<letter>', as the last 2 characters can be | |
5234 | mistaken as a size suffix. Put the name in parentheses. */ | |
5235 | if (GET_CODE (addr) == SYMBOL_REF | |
5236 | && strlen (XSTR (addr, 0)) > 2 | |
5237 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
a0a7fbc9 | 5238 | { |
fc2241eb RS |
5239 | putc ('(', file); |
5240 | output_addr_const (file, addr); | |
5241 | putc (')', file); | |
a0a7fbc9 AS |
5242 | } |
5243 | else | |
fc2241eb | 5244 | output_addr_const (file, addr); |
a0a7fbc9 | 5245 | } |
fc2241eb RS |
5246 | } |
5247 | else | |
5248 | { | |
5249 | int labelno; | |
5250 | ||
5251 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
44c7bd63 | 5252 | label being accessed, otherwise it is -1. */ |
fc2241eb RS |
5253 | labelno = (address.offset |
5254 | && !address.base | |
5255 | && GET_CODE (address.offset) == LABEL_REF | |
5256 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
5257 | : -1); | |
5258 | if (MOTOROLA) | |
a0a7fbc9 | 5259 | { |
fc2241eb RS |
5260 | /* Print the "offset(base" component. */ |
5261 | if (labelno >= 0) | |
e59d83aa | 5262 | asm_fprintf (file, "%LL%d(%Rpc,", labelno); |
fc2241eb | 5263 | else |
a0a7fbc9 | 5264 | { |
fc2241eb | 5265 | if (address.offset) |
75df395f MK |
5266 | output_addr_const (file, address.offset); |
5267 | ||
fc2241eb RS |
5268 | putc ('(', file); |
5269 | if (address.base) | |
5270 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
a0a7fbc9 | 5271 | } |
fc2241eb RS |
5272 | /* Print the ",index" component, if any. */ |
5273 | if (address.index) | |
a0a7fbc9 | 5274 | { |
fc2241eb RS |
5275 | if (address.base) |
5276 | putc (',', file); | |
5277 | fprintf (file, "%s.%c", | |
5278 | M68K_REGNAME (REGNO (address.index)), | |
5279 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
5280 | if (address.scale != 1) | |
5281 | fprintf (file, "*%d", address.scale); | |
a0a7fbc9 | 5282 | } |
a0a7fbc9 | 5283 | putc (')', file); |
a0a7fbc9 | 5284 | } |
fc2241eb | 5285 | else /* !MOTOROLA */ |
a0a7fbc9 | 5286 | { |
fc2241eb RS |
5287 | if (!address.offset && !address.index) |
5288 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
a0a7fbc9 | 5289 | else |
a0a7fbc9 | 5290 | { |
fc2241eb RS |
5291 | /* Print the "base@(offset" component. */ |
5292 | if (labelno >= 0) | |
e59d83aa | 5293 | asm_fprintf (file, "%Rpc@(%LL%d", labelno); |
fc2241eb RS |
5294 | else |
5295 | { | |
5296 | if (address.base) | |
5297 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
5298 | fprintf (file, "@("); | |
5299 | if (address.offset) | |
75df395f | 5300 | output_addr_const (file, address.offset); |
fc2241eb RS |
5301 | } |
5302 | /* Print the ",index" component, if any. */ | |
5303 | if (address.index) | |
5304 | { | |
5305 | fprintf (file, ",%s:%c", | |
5306 | M68K_REGNAME (REGNO (address.index)), | |
5307 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
5308 | if (address.scale != 1) | |
5309 | fprintf (file, ":%d", address.scale); | |
5310 | } | |
a0a7fbc9 AS |
5311 | putc (')', file); |
5312 | } | |
a0a7fbc9 | 5313 | } |
79e68feb RS |
5314 | } |
5315 | } | |
af13f02d JW |
5316 | \f |
5317 | /* Check for cases where a clr insns can be omitted from code using | |
5318 | strict_low_part sets. For example, the second clrl here is not needed: | |
5319 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
5320 | ||
5321 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
5322 | insn we are checking for redundancy. TARGET is the register set by the | |
5323 | clear insn. */ | |
5324 | ||
8a4a2253 | 5325 | bool |
ef4bddc2 | 5326 | strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn, |
8a4a2253 | 5327 | rtx target) |
af13f02d | 5328 | { |
c85e862a | 5329 | rtx_insn *p = first_insn; |
af13f02d | 5330 | |
39250081 | 5331 | while ((p = PREV_INSN (p))) |
af13f02d | 5332 | { |
39250081 RZ |
5333 | if (NOTE_INSN_BASIC_BLOCK_P (p)) |
5334 | return false; | |
5335 | ||
5336 | if (NOTE_P (p)) | |
5337 | continue; | |
5338 | ||
af13f02d | 5339 | /* If it isn't an insn, then give up. */ |
39250081 | 5340 | if (!INSN_P (p)) |
8a4a2253 | 5341 | return false; |
af13f02d JW |
5342 | |
5343 | if (reg_set_p (target, p)) | |
5344 | { | |
5345 | rtx set = single_set (p); | |
5346 | rtx dest; | |
5347 | ||
5348 | /* If it isn't an easy to recognize insn, then give up. */ | |
5349 | if (! set) | |
8a4a2253 | 5350 | return false; |
af13f02d JW |
5351 | |
5352 | dest = SET_DEST (set); | |
5353 | ||
5354 | /* If this sets the entire target register to zero, then our | |
5355 | first_insn is redundant. */ | |
5356 | if (rtx_equal_p (dest, target) | |
5357 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 5358 | return true; |
af13f02d JW |
5359 | else if (GET_CODE (dest) == STRICT_LOW_PART |
5360 | && GET_CODE (XEXP (dest, 0)) == REG | |
5361 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
5362 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
5363 | <= GET_MODE_SIZE (mode))) | |
5364 | /* This is a strict low part set which modifies less than | |
5365 | we are using, so it is safe. */ | |
5366 | ; | |
5367 | else | |
8a4a2253 | 5368 | return false; |
af13f02d | 5369 | } |
af13f02d JW |
5370 | } |
5371 | ||
8a4a2253 | 5372 | return false; |
af13f02d | 5373 | } |
67cd4f83 | 5374 | |
2c8ec431 DL |
5375 | /* Operand predicates for implementing asymmetric pc-relative addressing |
5376 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 5377 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
5378 | |
5379 | We model this by restricting the meaning of the basic predicates | |
5380 | (general_operand, memory_operand, etc) to forbid the use of this | |
5381 | addressing mode, and then define the following predicates that permit | |
5382 | this addressing mode. These predicates can then be used for the | |
5383 | source operands of the appropriate instructions. | |
5384 | ||
5385 | n.b. While it is theoretically possible to change all machine patterns | |
5386 | to use this addressing more where permitted by the architecture, | |
5387 | it has only been implemented for "common" cases: SImode, HImode, and | |
5388 | QImode operands, and only for the principle operations that would | |
5389 | require this addressing mode: data movement and simple integer operations. | |
5390 | ||
5391 | In parallel with these new predicates, two new constraint letters | |
5392 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
5393 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
5394 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
5395 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
5396 | of how these constraints are used. | |
5397 | ||
5398 | The use of these predicates is strictly optional, though patterns that | |
5399 | don't will cause an extra reload register to be allocated where one | |
5400 | was not necessary: | |
5401 | ||
5402 | lea (abc:w,%pc),%a0 ; need to reload address | |
5403 | moveq &1,%d1 ; since write to pc-relative space | |
5404 | movel %d1,%a0@ ; is not allowed | |
5405 | ... | |
5406 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
5407 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
5408 | ||
5409 | For more info, consult tiemann@cygnus.com. | |
5410 | ||
5411 | ||
5412 | All of the ugliness with predicates and constraints is due to the | |
5413 | simple fact that the m68k does not allow a pc-relative addressing | |
5414 | mode as a destination. gcc does not distinguish between source and | |
5415 | destination addresses. Hence, if we claim that pc-relative address | |
331d9186 | 5416 | modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we |
2c8ec431 DL |
5417 | end up with invalid code. To get around this problem, we left |
5418 | pc-relative modes as invalid addresses, and then added special | |
5419 | predicates and constraints to accept them. | |
5420 | ||
5421 | A cleaner way to handle this is to modify gcc to distinguish | |
5422 | between source and destination addresses. We can then say that | |
5423 | pc-relative is a valid source address but not a valid destination | |
5424 | address, and hopefully avoid a lot of the predicate and constraint | |
5425 | hackery. Unfortunately, this would be a pretty big change. It would | |
5426 | be a useful change for a number of ports, but there aren't any current | |
5427 | plans to undertake this. | |
5428 | ||
5429 | ***************************************************************************/ | |
5430 | ||
5431 | ||
5505f548 | 5432 | const char * |
8a4a2253 | 5433 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
5434 | { |
5435 | int logval; | |
6cebc6cb | 5436 | CC_STATUS_INIT; |
29ae8a3c | 5437 | if (GET_CODE (operands[2]) == CONST_INT |
25c99d8f | 5438 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
5439 | && (DATA_REG_P (operands[0]) |
5440 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 5441 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
5442 | { |
5443 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 5444 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 5445 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
5446 | if (operands[2] == const0_rtx) |
5447 | return "clr%.w %0"; | |
5448 | return "and%.w %2,%0"; | |
5449 | } | |
5450 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 5451 | && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
5452 | && (DATA_REG_P (operands[0]) |
5453 | || offsettable_memref_p (operands[0]))) | |
5454 | { | |
5455 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 5456 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
5457 | else |
5458 | { | |
b72f00af | 5459 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 5460 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c | 5461 | } |
29ae8a3c RK |
5462 | return "bclr %1,%0"; |
5463 | } | |
6cebc6cb BS |
5464 | /* Only a standard logical operation on the whole word sets the |
5465 | condition codes in a way we can use. */ | |
5466 | if (!side_effects_p (operands[0])) | |
5467 | flags_operand1 = operands[0]; | |
5468 | flags_valid = FLAGS_VALID_YES; | |
29ae8a3c RK |
5469 | return "and%.l %2,%0"; |
5470 | } | |
5471 | ||
5505f548 | 5472 | const char * |
8a4a2253 | 5473 | output_iorsi3 (rtx *operands) |
29ae8a3c | 5474 | { |
fb43b412 | 5475 | int logval; |
6cebc6cb | 5476 | CC_STATUS_INIT; |
29ae8a3c RK |
5477 | if (GET_CODE (operands[2]) == CONST_INT |
5478 | && INTVAL (operands[2]) >> 16 == 0 | |
5479 | && (DATA_REG_P (operands[0]) | |
5480 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 5481 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
5482 | { |
5483 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 5484 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
5485 | if (INTVAL (operands[2]) == 0xffff) |
5486 | return "mov%.w %2,%0"; | |
5487 | return "or%.w %2,%0"; | |
5488 | } | |
5489 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 5490 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
5491 | && (DATA_REG_P (operands[0]) |
5492 | || offsettable_memref_p (operands[0]))) | |
5493 | { | |
5494 | if (DATA_REG_P (operands[0])) | |
b72f00af | 5495 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
5496 | else |
5497 | { | |
b72f00af | 5498 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 5499 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c | 5500 | } |
29ae8a3c RK |
5501 | return "bset %1,%0"; |
5502 | } | |
6cebc6cb BS |
5503 | /* Only a standard logical operation on the whole word sets the |
5504 | condition codes in a way we can use. */ | |
5505 | if (!side_effects_p (operands[0])) | |
5506 | flags_operand1 = operands[0]; | |
5507 | flags_valid = FLAGS_VALID_YES; | |
29ae8a3c RK |
5508 | return "or%.l %2,%0"; |
5509 | } | |
5510 | ||
5505f548 | 5511 | const char * |
8a4a2253 | 5512 | output_xorsi3 (rtx *operands) |
29ae8a3c | 5513 | { |
fb43b412 | 5514 | int logval; |
6cebc6cb | 5515 | CC_STATUS_INIT; |
29ae8a3c RK |
5516 | if (GET_CODE (operands[2]) == CONST_INT |
5517 | && INTVAL (operands[2]) >> 16 == 0 | |
5518 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 5519 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
5520 | { |
5521 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 5522 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
5523 | if (INTVAL (operands[2]) == 0xffff) |
5524 | return "not%.w %0"; | |
5525 | return "eor%.w %2,%0"; | |
5526 | } | |
5527 | if (GET_CODE (operands[2]) == CONST_INT | |
c4406f74 | 5528 | && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 |
29ae8a3c RK |
5529 | && (DATA_REG_P (operands[0]) |
5530 | || offsettable_memref_p (operands[0]))) | |
5531 | { | |
5532 | if (DATA_REG_P (operands[0])) | |
b72f00af | 5533 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
5534 | else |
5535 | { | |
b72f00af | 5536 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 5537 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c | 5538 | } |
29ae8a3c RK |
5539 | return "bchg %1,%0"; |
5540 | } | |
6cebc6cb BS |
5541 | /* Only a standard logical operation on the whole word sets the |
5542 | condition codes in a way we can use. */ | |
5543 | if (!side_effects_p (operands[0])) | |
5544 | flags_operand1 = operands[0]; | |
5545 | flags_valid = FLAGS_VALID_YES; | |
29ae8a3c RK |
5546 | return "eor%.l %2,%0"; |
5547 | } | |
7c262518 | 5548 | |
29ca003a RS |
5549 | /* Return the instruction that should be used for a call to address X, |
5550 | which is known to be in operand 0. */ | |
5551 | ||
5552 | const char * | |
5553 | output_call (rtx x) | |
5554 | { | |
5555 | if (symbolic_operand (x, VOIDmode)) | |
5556 | return m68k_symbolic_call; | |
5557 | else | |
5558 | return "jsr %a0"; | |
5559 | } | |
5560 | ||
f7e70894 RS |
5561 | /* Likewise sibling calls. */ |
5562 | ||
5563 | const char * | |
5564 | output_sibcall (rtx x) | |
5565 | { | |
5566 | if (symbolic_operand (x, VOIDmode)) | |
5567 | return m68k_symbolic_jump; | |
5568 | else | |
5569 | return "jmp %a0"; | |
5570 | } | |
5571 | ||
c590b625 | 5572 | static void |
8a4a2253 | 5573 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
4ab870f5 | 5574 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
8a4a2253 | 5575 | tree function) |
483ab821 | 5576 | { |
f7430263 | 5577 | const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); |
c85e862a DM |
5578 | rtx this_slot, offset, addr, mem, tmp; |
5579 | rtx_insn *insn; | |
e0601576 RH |
5580 | |
5581 | /* Avoid clobbering the struct value reg by using the | |
5582 | static chain reg as a temporary. */ | |
5583 | tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4ab870f5 RS |
5584 | |
5585 | /* Pretend to be a post-reload pass while generating rtl. */ | |
4ab870f5 | 5586 | reload_completed = 1; |
4ab870f5 RS |
5587 | |
5588 | /* The "this" pointer is stored at 4(%sp). */ | |
0a81f074 RS |
5589 | this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode, |
5590 | stack_pointer_rtx, 4)); | |
4ab870f5 RS |
5591 | |
5592 | /* Add DELTA to THIS. */ | |
5593 | if (delta != 0) | |
5050d266 | 5594 | { |
4ab870f5 RS |
5595 | /* Make the offset a legitimate operand for memory addition. */ |
5596 | offset = GEN_INT (delta); | |
5597 | if ((delta < -8 || delta > 8) | |
5598 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
5599 | { | |
5600 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
5601 | offset = gen_rtx_REG (Pmode, D0_REG); | |
5602 | } | |
5603 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5604 | copy_rtx (this_slot), offset)); | |
5050d266 | 5605 | } |
c590b625 | 5606 | |
4ab870f5 RS |
5607 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
5608 | if (vcall_offset != 0) | |
5609 | { | |
5610 | /* Set the static chain register to *THIS. */ | |
e0601576 RH |
5611 | emit_move_insn (tmp, this_slot); |
5612 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
4ab870f5 RS |
5613 | |
5614 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
0a81f074 | 5615 | addr = plus_constant (Pmode, tmp, vcall_offset); |
4ab870f5 RS |
5616 | if (!m68k_legitimate_address_p (Pmode, addr, true)) |
5617 | { | |
f7df4a84 | 5618 | emit_insn (gen_rtx_SET (tmp, addr)); |
e0601576 | 5619 | addr = tmp; |
4ab870f5 | 5620 | } |
c590b625 | 5621 | |
4ab870f5 RS |
5622 | /* Load the offset into %d0 and add it to THIS. */ |
5623 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
5624 | gen_rtx_MEM (Pmode, addr)); | |
5625 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
5626 | copy_rtx (this_slot), | |
5627 | gen_rtx_REG (Pmode, D0_REG))); | |
5628 | } | |
29ca003a | 5629 | |
4ab870f5 RS |
5630 | /* Jump to the target function. Use a sibcall if direct jumps are |
5631 | allowed, otherwise load the address into a register first. */ | |
5632 | mem = DECL_RTL (function); | |
5633 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
5634 | { | |
5635 | gcc_assert (flag_pic); | |
c590b625 | 5636 | |
4ab870f5 RS |
5637 | if (!TARGET_SEP_DATA) |
5638 | { | |
5639 | /* Use the static chain register as a temporary (call-clobbered) | |
5640 | GOT pointer for this function. We can use the static chain | |
5641 | register because it isn't live on entry to the thunk. */ | |
6fb5fa3c | 5642 | SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); |
4ab870f5 RS |
5643 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
5644 | } | |
e0601576 RH |
5645 | legitimize_pic_address (XEXP (mem, 0), Pmode, tmp); |
5646 | mem = replace_equiv_address (mem, tmp); | |
4ab870f5 RS |
5647 | } |
5648 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
5649 | SIBLING_CALL_P (insn) = 1; | |
5650 | ||
5651 | /* Run just enough of rest_of_compilation. */ | |
5652 | insn = get_insns (); | |
5653 | split_all_insns_noflow (); | |
f7430263 | 5654 | assemble_start_function (thunk, fnname); |
4ab870f5 RS |
5655 | final_start_function (insn, file, 1); |
5656 | final (insn, file, 1); | |
5657 | final_end_function (); | |
f7430263 | 5658 | assemble_end_function (thunk, fnname); |
4ab870f5 RS |
5659 | |
5660 | /* Clean up the vars set above. */ | |
5661 | reload_completed = 0; | |
4ab870f5 RS |
5662 | |
5663 | /* Restore the original PIC register. */ | |
5664 | if (flag_pic) | |
6fb5fa3c | 5665 | SET_REGNO (pic_offset_table_rtx, PIC_REG); |
483ab821 | 5666 | } |
8636be86 KH |
5667 | |
5668 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
5669 | ||
5670 | static rtx | |
5671 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
5672 | int incoming ATTRIBUTE_UNUSED) | |
5673 | { | |
5674 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
5675 | } | |
cfca21cb PB |
5676 | |
5677 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
5678 | int | |
5679 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
5680 | unsigned int new_reg) | |
5681 | { | |
5682 | ||
5683 | /* Interrupt functions can only use registers that have already been | |
5684 | saved by the prologue, even if they would normally be | |
5685 | call-clobbered. */ | |
5686 | ||
a4242737 KH |
5687 | if ((m68k_get_function_kind (current_function_decl) |
5688 | == m68k_fk_interrupt_handler) | |
6fb5fa3c | 5689 | && !df_regs_ever_live_p (new_reg)) |
cfca21cb PB |
5690 | return 0; |
5691 | ||
5692 | return 1; | |
5693 | } | |
70028b61 | 5694 | |
c43f4279 RS |
5695 | /* Implement TARGET_HARD_REGNO_NREGS. |
5696 | ||
5697 | On the m68k, ordinary registers hold 32 bits worth; | |
5698 | for the 68881 registers, a single register is always enough for | |
5699 | anything that can be stored in them at all. */ | |
5700 | ||
5701 | static unsigned int | |
5702 | m68k_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
5703 | { | |
5704 | if (regno >= 16) | |
5705 | return GET_MODE_NUNITS (mode); | |
5706 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
5707 | } | |
5708 | ||
f939c3e6 RS |
5709 | /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu |
5710 | registers can hold any mode, but restrict the 68881 registers to | |
5711 | floating-point modes. */ | |
ffa2596e | 5712 | |
f939c3e6 RS |
5713 | static bool |
5714 | m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
70028b61 | 5715 | { |
36e04090 | 5716 | if (DATA_REGNO_P (regno)) |
70028b61 | 5717 | { |
a0a7fbc9 AS |
5718 | /* Data Registers, can hold aggregate if fits in. */ |
5719 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
5720 | return true; | |
70028b61 | 5721 | } |
36e04090 | 5722 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 5723 | { |
a0a7fbc9 AS |
5724 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
5725 | return true; | |
70028b61 | 5726 | } |
36e04090 | 5727 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
5728 | { |
5729 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
5730 | smaller. */ |
5731 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5732 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 5733 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 5734 | return true; |
70028b61 PB |
5735 | } |
5736 | return false; | |
5737 | } | |
dcc21c4c | 5738 | |
99e1629f RS |
5739 | /* Implement TARGET_MODES_TIEABLE_P. */ |
5740 | ||
5741 | static bool | |
5742 | m68k_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
5743 | { | |
5744 | return (!TARGET_HARD_FLOAT | |
5745 | || ((GET_MODE_CLASS (mode1) == MODE_FLOAT | |
5746 | || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT) | |
5747 | == (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
5748 | || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT))); | |
5749 | } | |
5750 | ||
ffa2596e RS |
5751 | /* Implement SECONDARY_RELOAD_CLASS. */ |
5752 | ||
5753 | enum reg_class | |
5754 | m68k_secondary_reload_class (enum reg_class rclass, | |
ef4bddc2 | 5755 | machine_mode mode, rtx x) |
ffa2596e RS |
5756 | { |
5757 | int regno; | |
5758 | ||
5759 | regno = true_regnum (x); | |
5760 | ||
5761 | /* If one operand of a movqi is an address register, the other | |
5762 | operand must be a general register or constant. Other types | |
5763 | of operand must be reloaded through a data register. */ | |
5764 | if (GET_MODE_SIZE (mode) == 1 | |
5765 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
5766 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
5767 | return DATA_REGS; | |
5768 | ||
5769 | /* PC-relative addresses must be loaded into an address register first. */ | |
5770 | if (TARGET_PCREL | |
5771 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
5772 | && symbolic_operand (x, VOIDmode)) | |
5773 | return ADDR_REGS; | |
5774 | ||
5775 | return NO_REGS; | |
5776 | } | |
5777 | ||
5778 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
5779 | ||
5780 | enum reg_class | |
5781 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
5782 | { | |
5783 | enum reg_class secondary_class; | |
5784 | ||
5785 | /* If RCLASS might need a secondary reload, try restricting it to | |
5786 | a class that doesn't. */ | |
5787 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
5788 | if (secondary_class != NO_REGS | |
5789 | && reg_class_subset_p (secondary_class, rclass)) | |
5790 | return secondary_class; | |
5791 | ||
5792 | /* Prefer to use moveq for in-range constants. */ | |
5793 | if (GET_CODE (x) == CONST_INT | |
5794 | && reg_class_subset_p (DATA_REGS, rclass) | |
5795 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
5796 | return DATA_REGS; | |
5797 | ||
5798 | /* ??? Do we really need this now? */ | |
5799 | if (GET_CODE (x) == CONST_DOUBLE | |
5800 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
5801 | { | |
5802 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
5803 | return FP_REGS; | |
5804 | ||
5805 | return NO_REGS; | |
5806 | } | |
5807 | ||
5808 | return rclass; | |
5809 | } | |
5810 | ||
dcc21c4c PB |
5811 | /* Return floating point values in a 68881 register. This makes 68881 code |
5812 | a little bit faster. It also makes -msoft-float code incompatible with | |
5813 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 5814 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
5815 | If there is need for a hard-float ABI it is probably worth doing it |
5816 | properly and also passing function arguments in FP registers. */ | |
5817 | rtx | |
ef4bddc2 | 5818 | m68k_libcall_value (machine_mode mode) |
dcc21c4c PB |
5819 | { |
5820 | switch (mode) { | |
4e10a5a7 RS |
5821 | case E_SFmode: |
5822 | case E_DFmode: | |
5823 | case E_XFmode: | |
dcc21c4c | 5824 | if (TARGET_68881) |
8d989403 | 5825 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
5826 | break; |
5827 | default: | |
5828 | break; | |
5829 | } | |
75df395f MK |
5830 | |
5831 | return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG); | |
dcc21c4c PB |
5832 | } |
5833 | ||
db5e2d51 MK |
5834 | /* Location in which function value is returned. |
5835 | NOTE: Due to differences in ABIs, don't call this function directly, | |
5836 | use FUNCTION_VALUE instead. */ | |
dcc21c4c | 5837 | rtx |
586de218 | 5838 | m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
dcc21c4c | 5839 | { |
ef4bddc2 | 5840 | machine_mode mode; |
dcc21c4c PB |
5841 | |
5842 | mode = TYPE_MODE (valtype); | |
5843 | switch (mode) { | |
4e10a5a7 RS |
5844 | case E_SFmode: |
5845 | case E_DFmode: | |
5846 | case E_XFmode: | |
dcc21c4c | 5847 | if (TARGET_68881) |
8d989403 | 5848 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
5849 | break; |
5850 | default: | |
5851 | break; | |
5852 | } | |
5853 | ||
576c9028 KH |
5854 | /* If the function returns a pointer, push that into %a0. */ |
5855 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
5856 | /* For compatibility with the large body of existing code which | |
5857 | does not always properly declare external functions returning | |
5858 | pointer types, the m68k/SVR4 convention is to copy the value | |
5859 | returned for pointer functions from a0 to d0 in the function | |
5860 | epilogue, so that callers that have neglected to properly | |
5861 | declare the callee can still find the correct return value in | |
5862 | d0. */ | |
5863 | return gen_rtx_PARALLEL | |
5864 | (mode, | |
5865 | gen_rtvec (2, | |
5866 | gen_rtx_EXPR_LIST (VOIDmode, | |
5867 | gen_rtx_REG (mode, A0_REG), | |
5868 | const0_rtx), | |
5869 | gen_rtx_EXPR_LIST (VOIDmode, | |
5870 | gen_rtx_REG (mode, D0_REG), | |
5871 | const0_rtx))); | |
5872 | else if (POINTER_TYPE_P (valtype)) | |
5873 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 5874 | else |
576c9028 | 5875 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 5876 | } |
1c445f03 NS |
5877 | |
5878 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
5879 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT | |
5880 | static bool | |
511e41e5 | 5881 | m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
1c445f03 | 5882 | { |
ef4bddc2 | 5883 | machine_mode mode = TYPE_MODE (type); |
1c445f03 NS |
5884 | |
5885 | if (mode == BLKmode) | |
5886 | return true; | |
5887 | ||
5888 | /* If TYPE's known alignment is less than the alignment of MODE that | |
5889 | would contain the structure, then return in memory. We need to | |
5890 | do so to maintain the compatibility between code compiled with | |
5891 | -mstrict-align and that compiled with -mno-strict-align. */ | |
5892 | if (AGGREGATE_TYPE_P (type) | |
5893 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) | |
5894 | return true; | |
5895 | ||
5896 | return false; | |
5897 | } | |
5898 | #endif | |
c47b0cb4 MK |
5899 | |
5900 | /* CPU to schedule the program for. */ | |
5901 | enum attr_cpu m68k_sched_cpu; | |
5902 | ||
826fadba MK |
5903 | /* MAC to schedule the program for. */ |
5904 | enum attr_mac m68k_sched_mac; | |
5905 | ||
c47b0cb4 MK |
5906 | /* Operand type. */ |
5907 | enum attr_op_type | |
5908 | { | |
5909 | /* No operand. */ | |
5910 | OP_TYPE_NONE, | |
5911 | ||
96fcacb7 MK |
5912 | /* Integer register. */ |
5913 | OP_TYPE_RN, | |
5914 | ||
5915 | /* FP register. */ | |
5916 | OP_TYPE_FPN, | |
c47b0cb4 MK |
5917 | |
5918 | /* Implicit mem reference (e.g. stack). */ | |
5919 | OP_TYPE_MEM1, | |
5920 | ||
5921 | /* Memory without offset or indexing. EA modes 2, 3 and 4. */ | |
5922 | OP_TYPE_MEM234, | |
5923 | ||
5924 | /* Memory with offset but without indexing. EA mode 5. */ | |
5925 | OP_TYPE_MEM5, | |
5926 | ||
5927 | /* Memory with indexing. EA mode 6. */ | |
5928 | OP_TYPE_MEM6, | |
5929 | ||
5930 | /* Memory referenced by absolute address. EA mode 7. */ | |
5931 | OP_TYPE_MEM7, | |
5932 | ||
5933 | /* Immediate operand that doesn't require extension word. */ | |
5934 | OP_TYPE_IMM_Q, | |
5935 | ||
5936 | /* Immediate 16 bit operand. */ | |
5937 | OP_TYPE_IMM_W, | |
5938 | ||
5939 | /* Immediate 32 bit operand. */ | |
5940 | OP_TYPE_IMM_L | |
5941 | }; | |
5942 | ||
c47b0cb4 MK |
5943 | /* Return type of memory ADDR_RTX refers to. */ |
5944 | static enum attr_op_type | |
ef4bddc2 | 5945 | sched_address_type (machine_mode mode, rtx addr_rtx) |
c47b0cb4 MK |
5946 | { |
5947 | struct m68k_address address; | |
5948 | ||
96fcacb7 MK |
5949 | if (symbolic_operand (addr_rtx, VOIDmode)) |
5950 | return OP_TYPE_MEM7; | |
5951 | ||
c47b0cb4 MK |
5952 | if (!m68k_decompose_address (mode, addr_rtx, |
5953 | reload_completed, &address)) | |
5954 | { | |
96fcacb7 | 5955 | gcc_assert (!reload_completed); |
c47b0cb4 MK |
5956 | /* Reload will likely fix the address to be in the register. */ |
5957 | return OP_TYPE_MEM234; | |
5958 | } | |
5959 | ||
5960 | if (address.scale != 0) | |
5961 | return OP_TYPE_MEM6; | |
5962 | ||
5963 | if (address.base != NULL_RTX) | |
5964 | { | |
5965 | if (address.offset == NULL_RTX) | |
5966 | return OP_TYPE_MEM234; | |
5967 | ||
5968 | return OP_TYPE_MEM5; | |
5969 | } | |
5970 | ||
5971 | gcc_assert (address.offset != NULL_RTX); | |
5972 | ||
5973 | return OP_TYPE_MEM7; | |
5974 | } | |
5975 | ||
96fcacb7 MK |
5976 | /* Return X or Y (depending on OPX_P) operand of INSN. */ |
5977 | static rtx | |
647d790d | 5978 | sched_get_operand (rtx_insn *insn, bool opx_p) |
96fcacb7 MK |
5979 | { |
5980 | int i; | |
5981 | ||
5982 | if (recog_memoized (insn) < 0) | |
5983 | gcc_unreachable (); | |
5984 | ||
5985 | extract_constrain_insn_cached (insn); | |
5986 | ||
5987 | if (opx_p) | |
5988 | i = get_attr_opx (insn); | |
5989 | else | |
5990 | i = get_attr_opy (insn); | |
5991 | ||
5992 | if (i >= recog_data.n_operands) | |
5993 | return NULL; | |
5994 | ||
5995 | return recog_data.operand[i]; | |
5996 | } | |
5997 | ||
5998 | /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). | |
5999 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
c47b0cb4 | 6000 | static enum attr_op_type |
647d790d | 6001 | sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p) |
c47b0cb4 | 6002 | { |
96fcacb7 MK |
6003 | rtx op; |
6004 | ||
6005 | op = sched_get_operand (insn, opx_p); | |
6006 | ||
6007 | if (op == NULL) | |
6008 | { | |
6009 | gcc_assert (!reload_completed); | |
6010 | return OP_TYPE_RN; | |
6011 | } | |
c47b0cb4 MK |
6012 | |
6013 | if (address_p) | |
6014 | return sched_address_type (QImode, op); | |
6015 | ||
6016 | if (memory_operand (op, VOIDmode)) | |
6017 | return sched_address_type (GET_MODE (op), XEXP (op, 0)); | |
6018 | ||
6019 | if (register_operand (op, VOIDmode)) | |
96fcacb7 MK |
6020 | { |
6021 | if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op))) | |
6022 | || (reload_completed && FP_REG_P (op))) | |
6023 | return OP_TYPE_FPN; | |
6024 | ||
6025 | return OP_TYPE_RN; | |
6026 | } | |
c47b0cb4 MK |
6027 | |
6028 | if (GET_CODE (op) == CONST_INT) | |
6029 | { | |
96fcacb7 MK |
6030 | int ival; |
6031 | ||
6032 | ival = INTVAL (op); | |
6033 | ||
6034 | /* Check for quick constants. */ | |
6035 | switch (get_attr_type (insn)) | |
6036 | { | |
6037 | case TYPE_ALUQ_L: | |
6038 | if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1)) | |
6039 | return OP_TYPE_IMM_Q; | |
6040 | ||
6041 | gcc_assert (!reload_completed); | |
6042 | break; | |
6043 | ||
6044 | case TYPE_MOVEQ_L: | |
6045 | if (USE_MOVQ (ival)) | |
6046 | return OP_TYPE_IMM_Q; | |
6047 | ||
6048 | gcc_assert (!reload_completed); | |
6049 | break; | |
6050 | ||
6051 | case TYPE_MOV3Q_L: | |
6052 | if (valid_mov3q_const (ival)) | |
6053 | return OP_TYPE_IMM_Q; | |
6054 | ||
6055 | gcc_assert (!reload_completed); | |
6056 | break; | |
6057 | ||
6058 | default: | |
6059 | break; | |
6060 | } | |
6061 | ||
6062 | if (IN_RANGE (ival, -0x8000, 0x7fff)) | |
c47b0cb4 MK |
6063 | return OP_TYPE_IMM_W; |
6064 | ||
6065 | return OP_TYPE_IMM_L; | |
6066 | } | |
6067 | ||
6068 | if (GET_CODE (op) == CONST_DOUBLE) | |
6069 | { | |
6070 | switch (GET_MODE (op)) | |
6071 | { | |
4e10a5a7 | 6072 | case E_SFmode: |
c47b0cb4 MK |
6073 | return OP_TYPE_IMM_W; |
6074 | ||
4e10a5a7 RS |
6075 | case E_VOIDmode: |
6076 | case E_DFmode: | |
c47b0cb4 MK |
6077 | return OP_TYPE_IMM_L; |
6078 | ||
6079 | default: | |
6080 | gcc_unreachable (); | |
6081 | } | |
6082 | } | |
6083 | ||
00b2ef14 MK |
6084 | if (GET_CODE (op) == CONST |
6085 | || symbolic_operand (op, VOIDmode) | |
c47b0cb4 MK |
6086 | || LABEL_P (op)) |
6087 | { | |
6088 | switch (GET_MODE (op)) | |
6089 | { | |
4e10a5a7 | 6090 | case E_QImode: |
c47b0cb4 MK |
6091 | return OP_TYPE_IMM_Q; |
6092 | ||
4e10a5a7 | 6093 | case E_HImode: |
c47b0cb4 MK |
6094 | return OP_TYPE_IMM_W; |
6095 | ||
4e10a5a7 | 6096 | case E_SImode: |
c47b0cb4 MK |
6097 | return OP_TYPE_IMM_L; |
6098 | ||
6099 | default: | |
75df395f MK |
6100 | if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode)) |
6101 | /* Just a guess. */ | |
c47b0cb4 MK |
6102 | return OP_TYPE_IMM_W; |
6103 | ||
6104 | return OP_TYPE_IMM_L; | |
6105 | } | |
6106 | } | |
6107 | ||
96fcacb7 | 6108 | gcc_assert (!reload_completed); |
c47b0cb4 | 6109 | |
96fcacb7 MK |
6110 | if (FLOAT_MODE_P (GET_MODE (op))) |
6111 | return OP_TYPE_FPN; | |
c47b0cb4 | 6112 | |
96fcacb7 | 6113 | return OP_TYPE_RN; |
c47b0cb4 MK |
6114 | } |
6115 | ||
6116 | /* Implement opx_type attribute. | |
6117 | Return type of INSN's operand X. | |
6118 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
6119 | enum attr_opx_type | |
647d790d | 6120 | m68k_sched_attr_opx_type (rtx_insn *insn, int address_p) |
c47b0cb4 | 6121 | { |
c47b0cb4 MK |
6122 | switch (sched_attr_op_type (insn, true, address_p != 0)) |
6123 | { | |
96fcacb7 MK |
6124 | case OP_TYPE_RN: |
6125 | return OPX_TYPE_RN; | |
6126 | ||
6127 | case OP_TYPE_FPN: | |
6128 | return OPX_TYPE_FPN; | |
c47b0cb4 MK |
6129 | |
6130 | case OP_TYPE_MEM1: | |
6131 | return OPX_TYPE_MEM1; | |
6132 | ||
6133 | case OP_TYPE_MEM234: | |
6134 | return OPX_TYPE_MEM234; | |
6135 | ||
6136 | case OP_TYPE_MEM5: | |
6137 | return OPX_TYPE_MEM5; | |
6138 | ||
6139 | case OP_TYPE_MEM6: | |
6140 | return OPX_TYPE_MEM6; | |
6141 | ||
6142 | case OP_TYPE_MEM7: | |
6143 | return OPX_TYPE_MEM7; | |
6144 | ||
6145 | case OP_TYPE_IMM_Q: | |
6146 | return OPX_TYPE_IMM_Q; | |
6147 | ||
6148 | case OP_TYPE_IMM_W: | |
6149 | return OPX_TYPE_IMM_W; | |
6150 | ||
6151 | case OP_TYPE_IMM_L: | |
6152 | return OPX_TYPE_IMM_L; | |
6153 | ||
6154 | default: | |
6155 | gcc_unreachable (); | |
c47b0cb4 MK |
6156 | } |
6157 | } | |
6158 | ||
6159 | /* Implement opy_type attribute. | |
6160 | Return type of INSN's operand Y. | |
6161 | If ADDRESS_P is true, return type of memory location operand refers to. */ | |
6162 | enum attr_opy_type | |
647d790d | 6163 | m68k_sched_attr_opy_type (rtx_insn *insn, int address_p) |
c47b0cb4 | 6164 | { |
c47b0cb4 MK |
6165 | switch (sched_attr_op_type (insn, false, address_p != 0)) |
6166 | { | |
96fcacb7 MK |
6167 | case OP_TYPE_RN: |
6168 | return OPY_TYPE_RN; | |
6169 | ||
6170 | case OP_TYPE_FPN: | |
6171 | return OPY_TYPE_FPN; | |
c47b0cb4 MK |
6172 | |
6173 | case OP_TYPE_MEM1: | |
6174 | return OPY_TYPE_MEM1; | |
6175 | ||
6176 | case OP_TYPE_MEM234: | |
6177 | return OPY_TYPE_MEM234; | |
6178 | ||
6179 | case OP_TYPE_MEM5: | |
6180 | return OPY_TYPE_MEM5; | |
6181 | ||
6182 | case OP_TYPE_MEM6: | |
6183 | return OPY_TYPE_MEM6; | |
6184 | ||
6185 | case OP_TYPE_MEM7: | |
6186 | return OPY_TYPE_MEM7; | |
6187 | ||
6188 | case OP_TYPE_IMM_Q: | |
6189 | return OPY_TYPE_IMM_Q; | |
6190 | ||
6191 | case OP_TYPE_IMM_W: | |
6192 | return OPY_TYPE_IMM_W; | |
6193 | ||
6194 | case OP_TYPE_IMM_L: | |
6195 | return OPY_TYPE_IMM_L; | |
6196 | ||
6197 | default: | |
6198 | gcc_unreachable (); | |
c47b0cb4 MK |
6199 | } |
6200 | } | |
6201 | ||
96fcacb7 MK |
6202 | /* Return size of INSN as int. */ |
6203 | static int | |
84034c69 | 6204 | sched_get_attr_size_int (rtx_insn *insn) |
c47b0cb4 MK |
6205 | { |
6206 | int size; | |
6207 | ||
96fcacb7 | 6208 | switch (get_attr_type (insn)) |
c47b0cb4 | 6209 | { |
96fcacb7 MK |
6210 | case TYPE_IGNORE: |
6211 | /* There should be no references to m68k_sched_attr_size for 'ignore' | |
6212 | instructions. */ | |
6213 | gcc_unreachable (); | |
6214 | return 0; | |
6215 | ||
6216 | case TYPE_MUL_L: | |
c47b0cb4 MK |
6217 | size = 2; |
6218 | break; | |
6219 | ||
6220 | default: | |
6221 | size = 1; | |
6222 | break; | |
6223 | } | |
6224 | ||
6225 | switch (get_attr_opx_type (insn)) | |
6226 | { | |
6227 | case OPX_TYPE_NONE: | |
96fcacb7 MK |
6228 | case OPX_TYPE_RN: |
6229 | case OPX_TYPE_FPN: | |
c47b0cb4 MK |
6230 | case OPX_TYPE_MEM1: |
6231 | case OPX_TYPE_MEM234: | |
6232 | case OPY_TYPE_IMM_Q: | |
6233 | break; | |
6234 | ||
6235 | case OPX_TYPE_MEM5: | |
6236 | case OPX_TYPE_MEM6: | |
6237 | /* Here we assume that most absolute references are short. */ | |
6238 | case OPX_TYPE_MEM7: | |
6239 | case OPY_TYPE_IMM_W: | |
6240 | ++size; | |
6241 | break; | |
6242 | ||
6243 | case OPY_TYPE_IMM_L: | |
6244 | size += 2; | |
6245 | break; | |
6246 | ||
6247 | default: | |
6248 | gcc_unreachable (); | |
6249 | } | |
6250 | ||
6251 | switch (get_attr_opy_type (insn)) | |
6252 | { | |
6253 | case OPY_TYPE_NONE: | |
96fcacb7 MK |
6254 | case OPY_TYPE_RN: |
6255 | case OPY_TYPE_FPN: | |
c47b0cb4 MK |
6256 | case OPY_TYPE_MEM1: |
6257 | case OPY_TYPE_MEM234: | |
6258 | case OPY_TYPE_IMM_Q: | |
6259 | break; | |
6260 | ||
6261 | case OPY_TYPE_MEM5: | |
6262 | case OPY_TYPE_MEM6: | |
6263 | /* Here we assume that most absolute references are short. */ | |
6264 | case OPY_TYPE_MEM7: | |
6265 | case OPY_TYPE_IMM_W: | |
6266 | ++size; | |
6267 | break; | |
6268 | ||
6269 | case OPY_TYPE_IMM_L: | |
6270 | size += 2; | |
6271 | break; | |
6272 | ||
6273 | default: | |
6274 | gcc_unreachable (); | |
6275 | } | |
6276 | ||
6277 | if (size > 3) | |
6278 | { | |
96fcacb7 | 6279 | gcc_assert (!reload_completed); |
c47b0cb4 MK |
6280 | |
6281 | size = 3; | |
6282 | } | |
6283 | ||
6284 | return size; | |
6285 | } | |
6286 | ||
96fcacb7 MK |
6287 | /* Return size of INSN as attribute enum value. */ |
6288 | enum attr_size | |
84034c69 | 6289 | m68k_sched_attr_size (rtx_insn *insn) |
96fcacb7 MK |
6290 | { |
6291 | switch (sched_get_attr_size_int (insn)) | |
6292 | { | |
6293 | case 1: | |
6294 | return SIZE_1; | |
6295 | ||
6296 | case 2: | |
6297 | return SIZE_2; | |
6298 | ||
6299 | case 3: | |
6300 | return SIZE_3; | |
6301 | ||
6302 | default: | |
6303 | gcc_unreachable (); | |
96fcacb7 MK |
6304 | } |
6305 | } | |
6306 | ||
6307 | /* Return operand X or Y (depending on OPX_P) of INSN, | |
6308 | if it is a MEM, or NULL overwise. */ | |
6309 | static enum attr_op_type | |
84034c69 | 6310 | sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p) |
96fcacb7 MK |
6311 | { |
6312 | if (opx_p) | |
6313 | { | |
6314 | switch (get_attr_opx_type (insn)) | |
6315 | { | |
6316 | case OPX_TYPE_NONE: | |
6317 | case OPX_TYPE_RN: | |
6318 | case OPX_TYPE_FPN: | |
6319 | case OPX_TYPE_IMM_Q: | |
6320 | case OPX_TYPE_IMM_W: | |
6321 | case OPX_TYPE_IMM_L: | |
6322 | return OP_TYPE_RN; | |
6323 | ||
6324 | case OPX_TYPE_MEM1: | |
6325 | case OPX_TYPE_MEM234: | |
6326 | case OPX_TYPE_MEM5: | |
6327 | case OPX_TYPE_MEM7: | |
6328 | return OP_TYPE_MEM1; | |
6329 | ||
6330 | case OPX_TYPE_MEM6: | |
6331 | return OP_TYPE_MEM6; | |
6332 | ||
6333 | default: | |
6334 | gcc_unreachable (); | |
96fcacb7 MK |
6335 | } |
6336 | } | |
6337 | else | |
6338 | { | |
6339 | switch (get_attr_opy_type (insn)) | |
6340 | { | |
6341 | case OPY_TYPE_NONE: | |
6342 | case OPY_TYPE_RN: | |
6343 | case OPY_TYPE_FPN: | |
6344 | case OPY_TYPE_IMM_Q: | |
6345 | case OPY_TYPE_IMM_W: | |
6346 | case OPY_TYPE_IMM_L: | |
6347 | return OP_TYPE_RN; | |
6348 | ||
6349 | case OPY_TYPE_MEM1: | |
6350 | case OPY_TYPE_MEM234: | |
6351 | case OPY_TYPE_MEM5: | |
6352 | case OPY_TYPE_MEM7: | |
6353 | return OP_TYPE_MEM1; | |
6354 | ||
6355 | case OPY_TYPE_MEM6: | |
6356 | return OP_TYPE_MEM6; | |
6357 | ||
6358 | default: | |
6359 | gcc_unreachable (); | |
96fcacb7 MK |
6360 | } |
6361 | } | |
6362 | } | |
6363 | ||
c47b0cb4 MK |
6364 | /* Implement op_mem attribute. */ |
6365 | enum attr_op_mem | |
84034c69 | 6366 | m68k_sched_attr_op_mem (rtx_insn *insn) |
c47b0cb4 | 6367 | { |
96fcacb7 MK |
6368 | enum attr_op_type opx; |
6369 | enum attr_op_type opy; | |
c47b0cb4 | 6370 | |
96fcacb7 MK |
6371 | opx = sched_get_opxy_mem_type (insn, true); |
6372 | opy = sched_get_opxy_mem_type (insn, false); | |
c47b0cb4 | 6373 | |
96fcacb7 | 6374 | if (opy == OP_TYPE_RN && opx == OP_TYPE_RN) |
c47b0cb4 MK |
6375 | return OP_MEM_00; |
6376 | ||
96fcacb7 | 6377 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
6378 | { |
6379 | switch (get_attr_opx_access (insn)) | |
6380 | { | |
6381 | case OPX_ACCESS_R: | |
6382 | return OP_MEM_10; | |
6383 | ||
6384 | case OPX_ACCESS_W: | |
6385 | return OP_MEM_01; | |
6386 | ||
6387 | case OPX_ACCESS_RW: | |
6388 | return OP_MEM_11; | |
6389 | ||
6390 | default: | |
96fcacb7 | 6391 | gcc_unreachable (); |
c47b0cb4 MK |
6392 | } |
6393 | } | |
6394 | ||
96fcacb7 | 6395 | if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6) |
c47b0cb4 MK |
6396 | { |
6397 | switch (get_attr_opx_access (insn)) | |
6398 | { | |
6399 | case OPX_ACCESS_R: | |
6400 | return OP_MEM_I0; | |
6401 | ||
6402 | case OPX_ACCESS_W: | |
6403 | return OP_MEM_0I; | |
6404 | ||
6405 | case OPX_ACCESS_RW: | |
6406 | return OP_MEM_I1; | |
6407 | ||
6408 | default: | |
96fcacb7 | 6409 | gcc_unreachable (); |
c47b0cb4 MK |
6410 | } |
6411 | } | |
6412 | ||
96fcacb7 | 6413 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN) |
c47b0cb4 MK |
6414 | return OP_MEM_10; |
6415 | ||
96fcacb7 | 6416 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
6417 | { |
6418 | switch (get_attr_opx_access (insn)) | |
6419 | { | |
6420 | case OPX_ACCESS_W: | |
6421 | return OP_MEM_11; | |
6422 | ||
6423 | default: | |
96fcacb7 MK |
6424 | gcc_assert (!reload_completed); |
6425 | return OP_MEM_11; | |
c47b0cb4 MK |
6426 | } |
6427 | } | |
6428 | ||
96fcacb7 | 6429 | if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6) |
c47b0cb4 MK |
6430 | { |
6431 | switch (get_attr_opx_access (insn)) | |
6432 | { | |
6433 | case OPX_ACCESS_W: | |
6434 | return OP_MEM_1I; | |
6435 | ||
6436 | default: | |
96fcacb7 MK |
6437 | gcc_assert (!reload_completed); |
6438 | return OP_MEM_1I; | |
c47b0cb4 MK |
6439 | } |
6440 | } | |
6441 | ||
96fcacb7 | 6442 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN) |
c47b0cb4 MK |
6443 | return OP_MEM_I0; |
6444 | ||
96fcacb7 | 6445 | if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1) |
c47b0cb4 MK |
6446 | { |
6447 | switch (get_attr_opx_access (insn)) | |
6448 | { | |
6449 | case OPX_ACCESS_W: | |
6450 | return OP_MEM_I1; | |
6451 | ||
6452 | default: | |
96fcacb7 MK |
6453 | gcc_assert (!reload_completed); |
6454 | return OP_MEM_I1; | |
c47b0cb4 MK |
6455 | } |
6456 | } | |
6457 | ||
96fcacb7 MK |
6458 | gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6); |
6459 | gcc_assert (!reload_completed); | |
6460 | return OP_MEM_I1; | |
c47b0cb4 MK |
6461 | } |
6462 | ||
96fcacb7 MK |
6463 | /* Data for ColdFire V4 index bypass. |
6464 | Producer modifies register that is used as index in consumer with | |
6465 | specified scale. */ | |
6466 | static struct | |
b8c96320 | 6467 | { |
96fcacb7 MK |
6468 | /* Producer instruction. */ |
6469 | rtx pro; | |
826fadba | 6470 | |
96fcacb7 MK |
6471 | /* Consumer instruction. */ |
6472 | rtx con; | |
b8c96320 | 6473 | |
96fcacb7 MK |
6474 | /* Scale of indexed memory access within consumer. |
6475 | Or zero if bypass should not be effective at the moment. */ | |
6476 | int scale; | |
6477 | } sched_cfv4_bypass_data; | |
b8c96320 MK |
6478 | |
6479 | /* An empty state that is used in m68k_sched_adjust_cost. */ | |
6480 | static state_t sched_adjust_cost_state; | |
6481 | ||
6482 | /* Implement adjust_cost scheduler hook. | |
6483 | Return adjusted COST of dependency LINK between DEF_INSN and INSN. */ | |
6484 | static int | |
b505225b TS |
6485 | m68k_sched_adjust_cost (rtx_insn *insn, int, rtx_insn *def_insn, int cost, |
6486 | unsigned int) | |
b8c96320 MK |
6487 | { |
6488 | int delay; | |
6489 | ||
6490 | if (recog_memoized (def_insn) < 0 | |
6491 | || recog_memoized (insn) < 0) | |
6492 | return cost; | |
6493 | ||
96fcacb7 MK |
6494 | if (sched_cfv4_bypass_data.scale == 1) |
6495 | /* Handle ColdFire V4 bypass for indexed address with 1x scale. */ | |
6496 | { | |
6497 | /* haifa-sched.c: insn_cost () calls bypass_p () just before | |
6498 | targetm.sched.adjust_cost (). Hence, we can be relatively sure | |
6499 | that the data in sched_cfv4_bypass_data is up to date. */ | |
6500 | gcc_assert (sched_cfv4_bypass_data.pro == def_insn | |
6501 | && sched_cfv4_bypass_data.con == insn); | |
6502 | ||
6503 | if (cost < 3) | |
6504 | cost = 3; | |
6505 | ||
6506 | sched_cfv4_bypass_data.pro = NULL; | |
6507 | sched_cfv4_bypass_data.con = NULL; | |
6508 | sched_cfv4_bypass_data.scale = 0; | |
6509 | } | |
6510 | else | |
6511 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
6512 | && sched_cfv4_bypass_data.con == NULL | |
6513 | && sched_cfv4_bypass_data.scale == 0); | |
6514 | ||
b8c96320 MK |
6515 | /* Don't try to issue INSN earlier than DFA permits. |
6516 | This is especially useful for instructions that write to memory, | |
6517 | as their true dependence (default) latency is better to be set to 0 | |
6518 | to workaround alias analysis limitations. | |
6519 | This is, in fact, a machine independent tweak, so, probably, | |
6520 | it should be moved to haifa-sched.c: insn_cost (). */ | |
b8c96320 MK |
6521 | delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn); |
6522 | if (delay > cost) | |
6523 | cost = delay; | |
6524 | ||
6525 | return cost; | |
6526 | } | |
6527 | ||
96fcacb7 MK |
6528 | /* Return maximal number of insns that can be scheduled on a single cycle. */ |
6529 | static int | |
6530 | m68k_sched_issue_rate (void) | |
6531 | { | |
6532 | switch (m68k_sched_cpu) | |
6533 | { | |
6534 | case CPU_CFV1: | |
6535 | case CPU_CFV2: | |
6536 | case CPU_CFV3: | |
6537 | return 1; | |
6538 | ||
6539 | case CPU_CFV4: | |
6540 | return 2; | |
6541 | ||
6542 | default: | |
6543 | gcc_unreachable (); | |
6544 | return 0; | |
6545 | } | |
6546 | } | |
6547 | ||
826fadba MK |
6548 | /* Maximal length of instruction for current CPU. |
6549 | E.g. it is 3 for any ColdFire core. */ | |
6550 | static int max_insn_size; | |
6551 | ||
6552 | /* Data to model instruction buffer of CPU. */ | |
6553 | struct _sched_ib | |
6554 | { | |
96fcacb7 MK |
6555 | /* True if instruction buffer model is modeled for current CPU. */ |
6556 | bool enabled_p; | |
6557 | ||
826fadba MK |
6558 | /* Size of the instruction buffer in words. */ |
6559 | int size; | |
6560 | ||
6561 | /* Number of filled words in the instruction buffer. */ | |
6562 | int filled; | |
6563 | ||
6564 | /* Additional information about instruction buffer for CPUs that have | |
6565 | a buffer of instruction records, rather then a plain buffer | |
6566 | of instruction words. */ | |
6567 | struct _sched_ib_records | |
6568 | { | |
6569 | /* Size of buffer in records. */ | |
6570 | int n_insns; | |
b8c96320 | 6571 | |
5764ee3c | 6572 | /* Array to hold data on adjustments made to the size of the buffer. */ |
826fadba | 6573 | int *adjust; |
b8c96320 | 6574 | |
826fadba MK |
6575 | /* Index of the above array. */ |
6576 | int adjust_index; | |
6577 | } records; | |
6578 | ||
6579 | /* An insn that reserves (marks empty) one word in the instruction buffer. */ | |
6580 | rtx insn; | |
6581 | }; | |
6582 | ||
6583 | static struct _sched_ib sched_ib; | |
b8c96320 MK |
6584 | |
6585 | /* ID of memory unit. */ | |
6586 | static int sched_mem_unit_code; | |
6587 | ||
6588 | /* Implementation of the targetm.sched.variable_issue () hook. | |
6589 | It is called after INSN was issued. It returns the number of insns | |
6590 | that can possibly get scheduled on the current cycle. | |
6591 | It is used here to determine the effect of INSN on the instruction | |
6592 | buffer. */ | |
6593 | static int | |
6594 | m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6595 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 6596 | rtx_insn *insn, int can_issue_more) |
b8c96320 MK |
6597 | { |
6598 | int insn_size; | |
6599 | ||
96fcacb7 | 6600 | if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE) |
b8c96320 | 6601 | { |
826fadba MK |
6602 | switch (m68k_sched_cpu) |
6603 | { | |
6604 | case CPU_CFV1: | |
6605 | case CPU_CFV2: | |
96fcacb7 | 6606 | insn_size = sched_get_attr_size_int (insn); |
826fadba MK |
6607 | break; |
6608 | ||
6609 | case CPU_CFV3: | |
96fcacb7 | 6610 | insn_size = sched_get_attr_size_int (insn); |
826fadba MK |
6611 | |
6612 | /* ColdFire V3 and V4 cores have instruction buffers that can | |
6613 | accumulate up to 8 instructions regardless of instructions' | |
6614 | sizes. So we should take care not to "prefetch" 24 one-word | |
6615 | or 12 two-words instructions. | |
6616 | To model this behavior we temporarily decrease size of the | |
6617 | buffer by (max_insn_size - insn_size) for next 7 instructions. */ | |
6618 | { | |
6619 | int adjust; | |
6620 | ||
6621 | adjust = max_insn_size - insn_size; | |
6622 | sched_ib.size -= adjust; | |
6623 | ||
6624 | if (sched_ib.filled > sched_ib.size) | |
6625 | sched_ib.filled = sched_ib.size; | |
6626 | ||
6627 | sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust; | |
6628 | } | |
6629 | ||
6630 | ++sched_ib.records.adjust_index; | |
6631 | if (sched_ib.records.adjust_index == sched_ib.records.n_insns) | |
6632 | sched_ib.records.adjust_index = 0; | |
6633 | ||
5764ee3c | 6634 | /* Undo adjustment we did 7 instructions ago. */ |
826fadba MK |
6635 | sched_ib.size |
6636 | += sched_ib.records.adjust[sched_ib.records.adjust_index]; | |
6637 | ||
6638 | break; | |
b8c96320 | 6639 | |
96fcacb7 MK |
6640 | case CPU_CFV4: |
6641 | gcc_assert (!sched_ib.enabled_p); | |
6642 | insn_size = 0; | |
6643 | break; | |
6644 | ||
826fadba MK |
6645 | default: |
6646 | gcc_unreachable (); | |
6647 | } | |
b8c96320 | 6648 | |
3162fdf4 MK |
6649 | if (insn_size > sched_ib.filled) |
6650 | /* Scheduling for register pressure does not always take DFA into | |
6651 | account. Workaround instruction buffer not being filled enough. */ | |
6652 | { | |
60867e8c | 6653 | gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED); |
3162fdf4 MK |
6654 | insn_size = sched_ib.filled; |
6655 | } | |
6656 | ||
b8c96320 MK |
6657 | --can_issue_more; |
6658 | } | |
6659 | else if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6660 | || asm_noperands (PATTERN (insn)) >= 0) | |
826fadba | 6661 | insn_size = sched_ib.filled; |
b8c96320 MK |
6662 | else |
6663 | insn_size = 0; | |
6664 | ||
826fadba | 6665 | sched_ib.filled -= insn_size; |
b8c96320 MK |
6666 | |
6667 | return can_issue_more; | |
6668 | } | |
6669 | ||
96fcacb7 MK |
6670 | /* Return how many instructions should scheduler lookahead to choose the |
6671 | best one. */ | |
6672 | static int | |
6673 | m68k_sched_first_cycle_multipass_dfa_lookahead (void) | |
b8c96320 | 6674 | { |
96fcacb7 | 6675 | return m68k_sched_issue_rate () - 1; |
b8c96320 MK |
6676 | } |
6677 | ||
7ecb00a6 | 6678 | /* Implementation of targetm.sched.init_global () hook. |
b8c96320 MK |
6679 | It is invoked once per scheduling pass and is used here |
6680 | to initialize scheduler constants. */ | |
6681 | static void | |
6682 | m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6683 | int sched_verbose ATTRIBUTE_UNUSED, | |
6684 | int n_insns ATTRIBUTE_UNUSED) | |
6685 | { | |
96fcacb7 MK |
6686 | /* Check that all instructions have DFA reservations and |
6687 | that all instructions can be issued from a clean state. */ | |
e28c2052 MM |
6688 | if (flag_checking) |
6689 | { | |
6690 | rtx_insn *insn; | |
6691 | state_t state; | |
b8c96320 | 6692 | |
e28c2052 | 6693 | state = alloca (state_size ()); |
b8c96320 | 6694 | |
e28c2052 MM |
6695 | for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) |
6696 | { | |
6697 | if (INSN_P (insn) && recog_memoized (insn) >= 0) | |
6698 | { | |
6699 | gcc_assert (insn_has_dfa_reservation_p (insn)); | |
b8c96320 | 6700 | |
e28c2052 MM |
6701 | state_reset (state); |
6702 | if (state_transition (state, insn) >= 0) | |
6703 | gcc_unreachable (); | |
6704 | } | |
6705 | } | |
6706 | } | |
b8c96320 MK |
6707 | |
6708 | /* Setup target cpu. */ | |
96fcacb7 MK |
6709 | |
6710 | /* ColdFire V4 has a set of features to keep its instruction buffer full | |
6711 | (e.g., a separate memory bus for instructions) and, hence, we do not model | |
6712 | buffer for this CPU. */ | |
6713 | sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4); | |
6714 | ||
b8c96320 MK |
6715 | switch (m68k_sched_cpu) |
6716 | { | |
96fcacb7 MK |
6717 | case CPU_CFV4: |
6718 | sched_ib.filled = 0; | |
6719 | ||
6720 | /* FALLTHRU */ | |
6721 | ||
826fadba MK |
6722 | case CPU_CFV1: |
6723 | case CPU_CFV2: | |
6724 | max_insn_size = 3; | |
6725 | sched_ib.records.n_insns = 0; | |
6726 | sched_ib.records.adjust = NULL; | |
6727 | break; | |
6728 | ||
6729 | case CPU_CFV3: | |
6730 | max_insn_size = 3; | |
6731 | sched_ib.records.n_insns = 8; | |
5ead67f6 | 6732 | sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns); |
b8c96320 MK |
6733 | break; |
6734 | ||
6735 | default: | |
6736 | gcc_unreachable (); | |
6737 | } | |
6738 | ||
826fadba MK |
6739 | sched_mem_unit_code = get_cpu_unit_code ("cf_mem1"); |
6740 | ||
b8c96320 MK |
6741 | sched_adjust_cost_state = xmalloc (state_size ()); |
6742 | state_reset (sched_adjust_cost_state); | |
6743 | ||
6744 | start_sequence (); | |
6745 | emit_insn (gen_ib ()); | |
826fadba | 6746 | sched_ib.insn = get_insns (); |
b8c96320 MK |
6747 | end_sequence (); |
6748 | } | |
6749 | ||
6750 | /* Scheduling pass is now finished. Free/reset static variables. */ | |
6751 | static void | |
6752 | m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
6753 | int verbose ATTRIBUTE_UNUSED) | |
6754 | { | |
826fadba | 6755 | sched_ib.insn = NULL; |
b8c96320 MK |
6756 | |
6757 | free (sched_adjust_cost_state); | |
6758 | sched_adjust_cost_state = NULL; | |
6759 | ||
6760 | sched_mem_unit_code = 0; | |
826fadba MK |
6761 | |
6762 | free (sched_ib.records.adjust); | |
6763 | sched_ib.records.adjust = NULL; | |
6764 | sched_ib.records.n_insns = 0; | |
6765 | max_insn_size = 0; | |
b8c96320 MK |
6766 | } |
6767 | ||
7ecb00a6 | 6768 | /* Implementation of targetm.sched.init () hook. |
b8c96320 MK |
6769 | It is invoked each time scheduler starts on the new block (basic block or |
6770 | extended basic block). */ | |
6771 | static void | |
6772 | m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, | |
6773 | int sched_verbose ATTRIBUTE_UNUSED, | |
6774 | int n_insns ATTRIBUTE_UNUSED) | |
6775 | { | |
826fadba MK |
6776 | switch (m68k_sched_cpu) |
6777 | { | |
6778 | case CPU_CFV1: | |
6779 | case CPU_CFV2: | |
6780 | sched_ib.size = 6; | |
6781 | break; | |
6782 | ||
6783 | case CPU_CFV3: | |
6784 | sched_ib.size = sched_ib.records.n_insns * max_insn_size; | |
6785 | ||
6786 | memset (sched_ib.records.adjust, 0, | |
6787 | sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust)); | |
6788 | sched_ib.records.adjust_index = 0; | |
6789 | break; | |
6790 | ||
96fcacb7 MK |
6791 | case CPU_CFV4: |
6792 | gcc_assert (!sched_ib.enabled_p); | |
6793 | sched_ib.size = 0; | |
6794 | break; | |
6795 | ||
826fadba MK |
6796 | default: |
6797 | gcc_unreachable (); | |
6798 | } | |
6799 | ||
96fcacb7 MK |
6800 | if (sched_ib.enabled_p) |
6801 | /* haifa-sched.c: schedule_block () calls advance_cycle () just before | |
6802 | the first cycle. Workaround that. */ | |
6803 | sched_ib.filled = -2; | |
b8c96320 MK |
6804 | } |
6805 | ||
6806 | /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook. | |
6807 | It is invoked just before current cycle finishes and is used here | |
6808 | to track if instruction buffer got its two words this cycle. */ | |
6809 | static void | |
6810 | m68k_sched_dfa_pre_advance_cycle (void) | |
6811 | { | |
96fcacb7 MK |
6812 | if (!sched_ib.enabled_p) |
6813 | return; | |
6814 | ||
b8c96320 MK |
6815 | if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code)) |
6816 | { | |
826fadba | 6817 | sched_ib.filled += 2; |
b8c96320 | 6818 | |
826fadba MK |
6819 | if (sched_ib.filled > sched_ib.size) |
6820 | sched_ib.filled = sched_ib.size; | |
b8c96320 MK |
6821 | } |
6822 | } | |
6823 | ||
6824 | /* Implementation of targetm.sched.dfa_post_advance_cycle () hook. | |
6825 | It is invoked just after new cycle begins and is used here | |
6826 | to setup number of filled words in the instruction buffer so that | |
6827 | instructions which won't have all their words prefetched would be | |
6828 | stalled for a cycle. */ | |
6829 | static void | |
6830 | m68k_sched_dfa_post_advance_cycle (void) | |
6831 | { | |
6832 | int i; | |
b8c96320 | 6833 | |
96fcacb7 MK |
6834 | if (!sched_ib.enabled_p) |
6835 | return; | |
6836 | ||
b8c96320 MK |
6837 | /* Setup number of prefetched instruction words in the instruction |
6838 | buffer. */ | |
826fadba MK |
6839 | i = max_insn_size - sched_ib.filled; |
6840 | ||
6841 | while (--i >= 0) | |
b8c96320 | 6842 | { |
826fadba | 6843 | if (state_transition (curr_state, sched_ib.insn) >= 0) |
5f3b7d7c MK |
6844 | /* Pick up scheduler state. */ |
6845 | ++sched_ib.filled; | |
b8c96320 MK |
6846 | } |
6847 | } | |
96fcacb7 MK |
6848 | |
6849 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6850 | if it is an integer register, or NULL overwise. */ | |
6851 | static rtx | |
647d790d | 6852 | sched_get_reg_operand (rtx_insn *insn, bool opx_p) |
96fcacb7 MK |
6853 | { |
6854 | rtx op = NULL; | |
6855 | ||
6856 | if (opx_p) | |
6857 | { | |
6858 | if (get_attr_opx_type (insn) == OPX_TYPE_RN) | |
6859 | { | |
6860 | op = sched_get_operand (insn, true); | |
6861 | gcc_assert (op != NULL); | |
6862 | ||
6863 | if (!reload_completed && !REG_P (op)) | |
6864 | return NULL; | |
6865 | } | |
6866 | } | |
6867 | else | |
6868 | { | |
6869 | if (get_attr_opy_type (insn) == OPY_TYPE_RN) | |
6870 | { | |
6871 | op = sched_get_operand (insn, false); | |
6872 | gcc_assert (op != NULL); | |
6873 | ||
6874 | if (!reload_completed && !REG_P (op)) | |
6875 | return NULL; | |
6876 | } | |
6877 | } | |
6878 | ||
6879 | return op; | |
6880 | } | |
6881 | ||
6882 | /* Return true, if X or Y (depending on OPX_P) operand of INSN | |
6883 | is a MEM. */ | |
6884 | static bool | |
84034c69 | 6885 | sched_mem_operand_p (rtx_insn *insn, bool opx_p) |
96fcacb7 MK |
6886 | { |
6887 | switch (sched_get_opxy_mem_type (insn, opx_p)) | |
6888 | { | |
6889 | case OP_TYPE_MEM1: | |
6890 | case OP_TYPE_MEM6: | |
6891 | return true; | |
6892 | ||
6893 | default: | |
6894 | return false; | |
6895 | } | |
6896 | } | |
6897 | ||
6898 | /* Return X or Y (depending on OPX_P) operand of INSN, | |
6899 | if it is a MEM, or NULL overwise. */ | |
6900 | static rtx | |
647d790d | 6901 | sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p) |
96fcacb7 MK |
6902 | { |
6903 | bool opx_p; | |
6904 | bool opy_p; | |
6905 | ||
6906 | opx_p = false; | |
6907 | opy_p = false; | |
6908 | ||
6909 | if (must_read_p) | |
6910 | { | |
6911 | opx_p = true; | |
6912 | opy_p = true; | |
6913 | } | |
6914 | ||
6915 | if (must_write_p) | |
6916 | { | |
6917 | opx_p = true; | |
6918 | opy_p = false; | |
6919 | } | |
6920 | ||
6921 | if (opy_p && sched_mem_operand_p (insn, false)) | |
6922 | return sched_get_operand (insn, false); | |
6923 | ||
6924 | if (opx_p && sched_mem_operand_p (insn, true)) | |
6925 | return sched_get_operand (insn, true); | |
6926 | ||
6927 | gcc_unreachable (); | |
6928 | return NULL; | |
6929 | } | |
6930 | ||
6931 | /* Return non-zero if PRO modifies register used as part of | |
6932 | address in CON. */ | |
6933 | int | |
647d790d | 6934 | m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con) |
96fcacb7 MK |
6935 | { |
6936 | rtx pro_x; | |
6937 | rtx con_mem_read; | |
6938 | ||
6939 | pro_x = sched_get_reg_operand (pro, true); | |
6940 | if (pro_x == NULL) | |
6941 | return 0; | |
6942 | ||
6943 | con_mem_read = sched_get_mem_operand (con, true, false); | |
6944 | gcc_assert (con_mem_read != NULL); | |
6945 | ||
6946 | if (reg_mentioned_p (pro_x, con_mem_read)) | |
6947 | return 1; | |
6948 | ||
6949 | return 0; | |
6950 | } | |
6951 | ||
6952 | /* Helper function for m68k_sched_indexed_address_bypass_p. | |
6953 | if PRO modifies register used as index in CON, | |
6954 | return scale of indexed memory access in CON. Return zero overwise. */ | |
6955 | static int | |
647d790d | 6956 | sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con) |
96fcacb7 MK |
6957 | { |
6958 | rtx reg; | |
6959 | rtx mem; | |
6960 | struct m68k_address address; | |
6961 | ||
6962 | reg = sched_get_reg_operand (pro, true); | |
6963 | if (reg == NULL) | |
6964 | return 0; | |
6965 | ||
6966 | mem = sched_get_mem_operand (con, true, false); | |
6967 | gcc_assert (mem != NULL && MEM_P (mem)); | |
6968 | ||
6969 | if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed, | |
6970 | &address)) | |
6971 | gcc_unreachable (); | |
6972 | ||
6973 | if (REGNO (reg) == REGNO (address.index)) | |
6974 | { | |
6975 | gcc_assert (address.scale != 0); | |
6976 | return address.scale; | |
6977 | } | |
6978 | ||
6979 | return 0; | |
6980 | } | |
6981 | ||
6982 | /* Return non-zero if PRO modifies register used | |
6983 | as index with scale 2 or 4 in CON. */ | |
6984 | int | |
647d790d | 6985 | m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con) |
96fcacb7 MK |
6986 | { |
6987 | gcc_assert (sched_cfv4_bypass_data.pro == NULL | |
6988 | && sched_cfv4_bypass_data.con == NULL | |
6989 | && sched_cfv4_bypass_data.scale == 0); | |
6990 | ||
6991 | switch (sched_get_indexed_address_scale (pro, con)) | |
6992 | { | |
6993 | case 1: | |
6994 | /* We can't have a variable latency bypass, so | |
6995 | remember to adjust the insn cost in adjust_cost hook. */ | |
6996 | sched_cfv4_bypass_data.pro = pro; | |
6997 | sched_cfv4_bypass_data.con = con; | |
6998 | sched_cfv4_bypass_data.scale = 1; | |
6999 | return 0; | |
7000 | ||
7001 | case 2: | |
7002 | case 4: | |
7003 | return 1; | |
7004 | ||
7005 | default: | |
7006 | return 0; | |
7007 | } | |
7008 | } | |
75df395f | 7009 | |
e0601576 RH |
7010 | /* We generate a two-instructions program at M_TRAMP : |
7011 | movea.l &CHAIN_VALUE,%a0 | |
7012 | jmp FNADDR | |
7013 | where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */ | |
7014 | ||
7015 | static void | |
7016 | m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
7017 | { | |
7018 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
7019 | rtx mem; | |
7020 | ||
7021 | gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM)); | |
7022 | ||
7023 | mem = adjust_address (m_tramp, HImode, 0); | |
7024 | emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); | |
7025 | mem = adjust_address (m_tramp, SImode, 2); | |
7026 | emit_move_insn (mem, chain_value); | |
7027 | ||
7028 | mem = adjust_address (m_tramp, HImode, 6); | |
7029 | emit_move_insn (mem, GEN_INT(0x4EF9)); | |
7030 | mem = adjust_address (m_tramp, SImode, 8); | |
7031 | emit_move_insn (mem, fnaddr); | |
7032 | ||
7033 | FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0)); | |
7034 | } | |
7035 | ||
079e7538 NF |
7036 | /* On the 68000, the RTS insn cannot pop anything. |
7037 | On the 68010, the RTD insn may be used to pop them if the number | |
7038 | of args is fixed, but if the number is variable then the caller | |
7039 | must pop them all. RTD can't be used for library calls now | |
7040 | because the library is compiled with the Unix compiler. | |
7041 | Use of RTD is a selectable option, since it is incompatible with | |
7042 | standard Unix calling sequences. If the option is not selected, | |
7043 | the caller must always pop the args. */ | |
7044 | ||
a20c5714 RS |
7045 | static poly_int64 |
7046 | m68k_return_pops_args (tree fundecl, tree funtype, poly_int64 size) | |
079e7538 NF |
7047 | { |
7048 | return ((TARGET_RTD | |
7049 | && (!fundecl | |
7050 | || TREE_CODE (fundecl) != IDENTIFIER_NODE) | |
f38958e8 | 7051 | && (!stdarg_p (funtype))) |
a20c5714 | 7052 | ? (HOST_WIDE_INT) size : 0); |
079e7538 NF |
7053 | } |
7054 | ||
5efd84c5 NF |
7055 | /* Make sure everything's fine if we *don't* have a given processor. |
7056 | This assumes that putting a register in fixed_regs will keep the | |
7057 | compiler's mitts completely off it. We don't bother to zero it out | |
7058 | of register classes. */ | |
7059 | ||
7060 | static void | |
7061 | m68k_conditional_register_usage (void) | |
7062 | { | |
7063 | int i; | |
7064 | HARD_REG_SET x; | |
7065 | if (!TARGET_HARD_FLOAT) | |
7066 | { | |
6576d245 | 7067 | x = reg_class_contents[FP_REGS]; |
5efd84c5 NF |
7068 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
7069 | if (TEST_HARD_REG_BIT (x, i)) | |
7070 | fixed_regs[i] = call_used_regs[i] = 1; | |
7071 | } | |
7072 | if (flag_pic) | |
7073 | fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; | |
7074 | } | |
7075 | ||
8b281334 RH |
7076 | static void |
7077 | m68k_init_sync_libfuncs (void) | |
7078 | { | |
7079 | init_sync_libfuncs (UNITS_PER_WORD); | |
7080 | } | |
7081 | ||
175aed00 AS |
7082 | /* Implements EPILOGUE_USES. All registers are live on exit from an |
7083 | interrupt routine. */ | |
7084 | bool | |
7085 | m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED) | |
7086 | { | |
7087 | return (reload_completed | |
7088 | && (m68k_get_function_kind (current_function_decl) | |
7089 | == m68k_fk_interrupt_handler)); | |
7090 | } | |
7091 | ||
b89de1b8 JG |
7092 | |
7093 | /* Implement TARGET_C_EXCESS_PRECISION. | |
7094 | ||
7095 | Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp | |
7096 | instructions, we get proper intermediate rounding, otherwise we | |
7097 | get extended precision results. */ | |
7098 | ||
7099 | static enum flt_eval_method | |
7100 | m68k_excess_precision (enum excess_precision_type type) | |
7101 | { | |
7102 | switch (type) | |
7103 | { | |
7104 | case EXCESS_PRECISION_TYPE_FAST: | |
7105 | /* The fastest type to promote to will always be the native type, | |
7106 | whether that occurs with implicit excess precision or | |
7107 | otherwise. */ | |
7108 | return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT; | |
7109 | case EXCESS_PRECISION_TYPE_STANDARD: | |
7110 | case EXCESS_PRECISION_TYPE_IMPLICIT: | |
7111 | /* Otherwise, the excess precision we want when we are | |
7112 | in a standards compliant mode, and the implicit precision we | |
7113 | provide can be identical. */ | |
7114 | if (TARGET_68040 || ! TARGET_68881) | |
7115 | return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT; | |
7116 | ||
7117 | return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE; | |
f19a3270 | 7118 | case EXCESS_PRECISION_TYPE_FLOAT16: |
7119 | error ("%<-fexcess-precision=16%> is not supported on this target"); | |
7120 | break; | |
b89de1b8 JG |
7121 | default: |
7122 | gcc_unreachable (); | |
7123 | } | |
7124 | return FLT_EVAL_METHOD_UNPREDICTABLE; | |
7125 | } | |
7126 | ||
7b4df2bf RS |
7127 | /* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes |
7128 | a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */ | |
7129 | ||
7130 | poly_int64 | |
7131 | m68k_push_rounding (poly_int64 bytes) | |
7132 | { | |
7133 | if (TARGET_COLDFIRE) | |
7134 | return bytes; | |
7135 | return (bytes + 1) & ~1; | |
7136 | } | |
7137 | ||
d3719ee2 JM |
7138 | /* Implement TARGET_PROMOTE_FUNCTION_MODE. */ |
7139 | ||
7140 | static machine_mode | |
7141 | m68k_promote_function_mode (const_tree type, machine_mode mode, | |
7142 | int *punsignedp ATTRIBUTE_UNUSED, | |
7143 | const_tree fntype ATTRIBUTE_UNUSED, | |
7144 | int for_return) | |
7145 | { | |
7146 | /* Promote libcall arguments narrower than int to match the normal C | |
7147 | ABI (for which promotions are handled via | |
7148 | TARGET_PROMOTE_PROTOTYPES). */ | |
7149 | if (type == NULL_TREE && !for_return && (mode == QImode || mode == HImode)) | |
7150 | return SImode; | |
7151 | return mode; | |
7152 | } | |
7153 | ||
75df395f | 7154 | #include "gt-m68k.h" |