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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 KH |
2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
3 | 2001, 2003, 2004 | |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
0e29e3c9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
79e68feb | 22 | |
79e68feb | 23 | #include "config.h" |
f5220a5d | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
da932f04 | 27 | #include "tree.h" |
79e68feb | 28 | #include "rtl.h" |
49ad7cfa | 29 | #include "function.h" |
79e68feb RS |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
79e68feb RS |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
1d8eaa6b | 37 | #include "recog.h" |
f5220a5d | 38 | #include "toplev.h" |
6d5f49b2 RH |
39 | #include "expr.h" |
40 | #include "reload.h" | |
5505f548 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
2cc07db4 | 44 | #include "debug.h" |
79e68feb RS |
45 | #include "flags.h" |
46 | ||
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
e6d98cb0 BI |
59 | /* The ASM_DOT macro allows easy string pasting to handle the differences |
60 | between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't | |
61 | support the %. option. */ | |
62 | #if MOTOROLA | |
63 | # define ASM_DOT "." | |
64 | # define ASM_DOTW ".w" | |
65 | # define ASM_DOTL ".l" | |
66 | #else | |
67 | # define ASM_DOT "" | |
68 | # define ASM_DOTW "" | |
69 | # define ASM_DOTL "" | |
70 | #endif | |
71 | ||
72 | ||
ff482c8d | 73 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
74 | struct m68k_frame |
75 | { | |
76 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 77 | HOST_WIDE_INT offset; |
3d74bc09 BI |
78 | |
79 | /* Offset of FPU registers. */ | |
80 | HOST_WIDE_INT foffset; | |
81 | ||
82 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 83 | HOST_WIDE_INT size; |
3d74bc09 BI |
84 | |
85 | /* Data and address register. */ | |
48ed72a4 PB |
86 | int reg_no; |
87 | unsigned int reg_mask; | |
88 | unsigned int reg_rev_mask; | |
3d74bc09 BI |
89 | |
90 | /* FPU registers. */ | |
48ed72a4 PB |
91 | int fpu_no; |
92 | unsigned int fpu_mask; | |
93 | unsigned int fpu_rev_mask; | |
3d74bc09 BI |
94 | |
95 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
96 | HOST_WIDE_INT frame_pointer_offset; |
97 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
98 | |
99 | /* Function which the above information refers to. */ | |
100 | int funcdef_no; | |
48ed72a4 PB |
101 | }; |
102 | ||
3d74bc09 BI |
103 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
104 | static struct m68k_frame current_frame; | |
105 | ||
8a4a2253 BI |
106 | static rtx find_addr_reg (rtx); |
107 | static const char *singlemove_string (rtx *); | |
108 | static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT); | |
109 | static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
45849738 BI |
110 | #ifdef M68K_TARGET_COFF |
111 | static void m68k_coff_asm_named_section (const char *, unsigned int); | |
112 | #endif /* M68K_TARGET_COFF */ | |
8a4a2253 BI |
113 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
114 | HOST_WIDE_INT, tree); | |
8636be86 | 115 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
116 | static bool m68k_interrupt_function_p (tree func); |
117 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, | |
118 | tree args, int flags, | |
119 | bool *no_add_attrs); | |
3d74bc09 | 120 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 121 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
8a4a2253 BI |
122 | static int const_int_cost (rtx); |
123 | static bool m68k_rtx_costs (rtx, int, int, int *); | |
79e68feb RS |
124 | \f |
125 | ||
a2ef3db7 BI |
126 | /* Specify the identification number of the library being built */ |
127 | const char *m68k_library_id_string; | |
ef1dbfb0 | 128 | |
2b3600ac JL |
129 | /* Nonzero if the last compare/test insn had FP operands. The |
130 | sCC expanders peek at this to determine what to do for the | |
131 | 68060, which has no fsCC instructions. */ | |
132 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
133 | \f |
134 | /* Initialize the GCC target structure. */ | |
301d03af RS |
135 | |
136 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
137 | #undef TARGET_ASM_ALIGNED_HI_OP | |
138 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
139 | #endif | |
140 | ||
141 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
142 | #undef TARGET_ASM_BYTE_OP | |
143 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
144 | #undef TARGET_ASM_ALIGNED_HI_OP | |
145 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
146 | #undef TARGET_ASM_ALIGNED_SI_OP | |
147 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
148 | #endif | |
149 | ||
150 | #if INT_OP_GROUP == INT_OP_DC | |
151 | #undef TARGET_ASM_BYTE_OP | |
152 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
153 | #undef TARGET_ASM_ALIGNED_HI_OP | |
154 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
155 | #undef TARGET_ASM_ALIGNED_SI_OP | |
156 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
157 | #endif | |
158 | ||
159 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
160 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
161 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
162 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
163 | ||
08c148a8 NB |
164 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
165 | #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue | |
166 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
167 | #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue | |
ef1dbfb0 | 168 | |
c590b625 RH |
169 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
170 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 AS |
171 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
172 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 173 | |
1bc7c5b6 ZW |
174 | #undef TARGET_ASM_FILE_START_APP_OFF |
175 | #define TARGET_ASM_FILE_START_APP_OFF true | |
176 | ||
3c50106f RH |
177 | #undef TARGET_RTX_COSTS |
178 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
179 | ||
48ed72a4 PB |
180 | #undef TARGET_ATTRIBUTE_TABLE |
181 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
182 | ||
8636be86 KH |
183 | #undef TARGET_PROMOTE_PROTOTYPES |
184 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
185 | ||
186 | #undef TARGET_STRUCT_VALUE_RTX | |
187 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
188 | ||
48ed72a4 PB |
189 | static const struct attribute_spec m68k_attribute_table[] = |
190 | { | |
191 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
192 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, | |
193 | { NULL, 0, 0, false, false, false, NULL } | |
194 | }; | |
195 | ||
f6897b10 | 196 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 197 | \f |
ef1dbfb0 RK |
198 | /* Sometimes certain combinations of command options do not make |
199 | sense on a particular target machine. You can define a macro | |
200 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
201 | defined, is executed once just after all the command options have | |
202 | been parsed. | |
203 | ||
204 | Don't use this macro to turn on various extra optimizations for | |
205 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
206 | ||
207 | void | |
8a4a2253 | 208 | override_options (void) |
ef1dbfb0 | 209 | { |
a2ef3db7 BI |
210 | /* Library identification */ |
211 | if (m68k_library_id_string) | |
212 | { | |
213 | int id; | |
214 | ||
215 | if (! TARGET_ID_SHARED_LIBRARY) | |
216 | error ("-mshared-library-id= specified without -mid-shared-library"); | |
217 | id = atoi (m68k_library_id_string); | |
218 | if (id < 0 || id > MAX_LIBRARY_ID) | |
219 | error ("-mshared-library-id=%d is not between 0 and %d", id, MAX_LIBRARY_ID); | |
220 | ||
221 | /* From now on, m68k_library_id_string will contain the library offset. */ | |
222 | asprintf ((char **)&m68k_library_id_string, "%d", (id * -4) - 4); | |
223 | } | |
224 | else | |
225 | /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the | |
226 | current library. */ | |
227 | m68k_library_id_string = "_current_shared_library_a5_offset_"; | |
228 | ||
229 | /* Sanity check to ensure that msep-data and mid-sahred-library are not | |
230 | * both specified together. Doing so simply doesn't make sense. | |
231 | */ | |
232 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
233 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
234 | ||
235 | /* If we're generating code for a separate A5 relative data segment, | |
236 | * we've got to enable -fPIC as well. This might be relaxable to | |
237 | * -fpic but it hasn't been tested properly. | |
238 | */ | |
239 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
240 | flag_pic = 2; | |
241 | ||
adf2ac37 RH |
242 | /* -fPIC uses 32-bit pc-relative displacements, which don't exist |
243 | until the 68020. */ | |
a2ef3db7 | 244 | if (!TARGET_68020 && !TARGET_COLDFIRE && (flag_pic == 2)) |
adf2ac37 RH |
245 | error("-fPIC is not currently supported on the 68000 or 68010\n"); |
246 | ||
247 | /* ??? A historic way of turning on pic, or is this intended to | |
248 | be an embedded thing that doesn't have the same name binding | |
249 | significance that it does on hosted ELF systems? */ | |
250 | if (TARGET_PCREL && flag_pic == 0) | |
251 | flag_pic = 1; | |
252 | ||
253 | /* Turn off function cse if we are doing PIC. We always want function call | |
254 | to be done as `bsr foo@PLTPC', so it will force the assembler to create | |
255 | the PLT entry for `foo'. Doing function cse will cause the address of | |
256 | `foo' to be loaded into a register, which is exactly what we want to | |
257 | avoid when we are doing PIC on svr4 m68k. */ | |
258 | if (flag_pic) | |
259 | flag_no_function_cse = 1; | |
260 | ||
261 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 262 | } |
79e68feb | 263 | \f |
48ed72a4 PB |
264 | /* Return nonzero if FUNC is an interrupt function as specified by the |
265 | "interrupt_handler" attribute. */ | |
266 | static bool | |
267 | m68k_interrupt_function_p(tree func) | |
268 | { | |
269 | tree a; | |
270 | ||
271 | if (TREE_CODE (func) != FUNCTION_DECL) | |
272 | return false; | |
273 | ||
274 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); | |
275 | return (a != NULL_TREE); | |
276 | } | |
277 | ||
278 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
279 | struct attribute_spec.handler. */ | |
280 | static tree | |
281 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
282 | tree args ATTRIBUTE_UNUSED, | |
283 | int flags ATTRIBUTE_UNUSED, | |
284 | bool *no_add_attrs) | |
285 | { | |
286 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
287 | { | |
288 | warning ("`%s' attribute only applies to functions", | |
289 | IDENTIFIER_POINTER (name)); | |
290 | *no_add_attrs = true; | |
291 | } | |
292 | ||
293 | return NULL_TREE; | |
294 | } | |
860c4900 BI |
295 | |
296 | static void | |
3d74bc09 | 297 | m68k_compute_frame_layout (void) |
860c4900 BI |
298 | { |
299 | int regno, saved; | |
300 | unsigned int mask, rmask; | |
48ed72a4 | 301 | bool interrupt_handler = m68k_interrupt_function_p (current_function_decl); |
860c4900 | 302 | |
3d74bc09 BI |
303 | /* Only compute the frame once per function. |
304 | Don't cache information until reload has been completed. */ | |
305 | if (current_frame.funcdef_no == current_function_funcdef_no | |
306 | && reload_completed) | |
307 | return; | |
308 | ||
309 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 BI |
310 | |
311 | mask = rmask = saved = 0; | |
312 | for (regno = 0; regno < 16; regno++) | |
48ed72a4 | 313 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 BI |
314 | { |
315 | mask |= 1 << regno; | |
316 | rmask |= 1 << (15 - regno); | |
317 | saved++; | |
318 | } | |
3d74bc09 BI |
319 | current_frame.offset = saved * 4; |
320 | current_frame.reg_no = saved; | |
321 | current_frame.reg_mask = mask; | |
322 | current_frame.reg_rev_mask = rmask; | |
860c4900 | 323 | |
57047680 GN |
324 | current_frame.foffset = 0; |
325 | mask = rmask = saved = 0; | |
860c4900 BI |
326 | if (TARGET_68881 /* || TARGET_CFV4E */) |
327 | { | |
860c4900 | 328 | for (regno = 16; regno < 24; regno++) |
3d74bc09 | 329 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 330 | { |
85802504 GN |
331 | mask |= 1 << (regno - 16); |
332 | rmask |= 1 << (23 - regno); | |
860c4900 BI |
333 | saved++; |
334 | } | |
3d74bc09 BI |
335 | current_frame.foffset = saved * 12 /* (TARGET_CFV4E ? 8 : 12) */; |
336 | current_frame.offset += current_frame.foffset; | |
860c4900 | 337 | } |
57047680 GN |
338 | current_frame.fpu_no = saved; |
339 | current_frame.fpu_mask = mask; | |
340 | current_frame.fpu_rev_mask = rmask; | |
3d74bc09 BI |
341 | |
342 | /* Remember what function this frame refers to. */ | |
343 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
344 | } |
345 | ||
346 | HOST_WIDE_INT | |
347 | m68k_initial_elimination_offset (int from, int to) | |
348 | { | |
860c4900 BI |
349 | /* FIXME: The correct offset to compute here would appear to be |
350 | (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD); | |
351 | but for some obscure reason, this must be 0 to get correct code. */ | |
352 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
353 | return 0; | |
354 | ||
3d74bc09 | 355 | m68k_compute_frame_layout (); |
860c4900 BI |
356 | |
357 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
3d74bc09 | 358 | return current_frame.offset + current_frame.size + (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD); |
860c4900 | 359 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
3d74bc09 | 360 | return current_frame.offset + current_frame.size; |
860c4900 BI |
361 | |
362 | abort(); | |
363 | } | |
364 | ||
97c55091 GN |
365 | /* Refer to the array `regs_ever_live' to determine which registers |
366 | to save; `regs_ever_live[I]' is nonzero if register number I | |
367 | is ever used in the function. This function is responsible for | |
368 | knowing which registers should not be saved even if used. | |
369 | Return true if we need to save REGNO. */ | |
370 | ||
48ed72a4 PB |
371 | static bool |
372 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e AS |
373 | { |
374 | if (flag_pic && current_function_uses_pic_offset_table | |
375 | && regno == PIC_OFFSET_TABLE_REGNUM) | |
48ed72a4 | 376 | return true; |
2cff4a6e AS |
377 | |
378 | if (current_function_calls_eh_return) | |
379 | { | |
380 | unsigned int i; | |
381 | for (i = 0; ; i++) | |
382 | { | |
383 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
384 | if (test == INVALID_REGNUM) | |
385 | break; | |
386 | if (test == regno) | |
48ed72a4 | 387 | return true; |
2cff4a6e AS |
388 | } |
389 | } | |
390 | ||
48ed72a4 PB |
391 | /* Fixed regs we never touch. */ |
392 | if (fixed_regs[regno]) | |
393 | return false; | |
394 | ||
395 | /* The frame pointer (if it is such) is handled specially. */ | |
396 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
397 | return false; | |
398 | ||
399 | /* Interrupt handlers must also save call_used_regs | |
400 | if they are live or when calling nested functions. */ | |
401 | if (interrupt_handler) | |
402 | { | |
403 | if (regs_ever_live[regno]) | |
404 | return true; | |
405 | ||
406 | if (!current_function_is_leaf && call_used_regs[regno]) | |
407 | return true; | |
408 | } | |
409 | ||
410 | /* Never need to save registers that aren't touched. */ | |
411 | if (!regs_ever_live[regno]) | |
412 | return false; | |
413 | ||
b2e08ed4 | 414 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 415 | return !call_used_regs[regno]; |
2cff4a6e AS |
416 | } |
417 | ||
79e68feb RS |
418 | /* This function generates the assembly code for function entry. |
419 | STREAM is a stdio stream to output the code to. | |
97c55091 | 420 | SIZE is an int: how many units of temporary storage to allocate. */ |
79e68feb | 421 | |
08c148a8 | 422 | static void |
3d74bc09 | 423 | m68k_output_function_prologue (FILE *stream, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
79e68feb | 424 | { |
860c4900 | 425 | HOST_WIDE_INT fsize_with_regs; |
08c148a8 | 426 | HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET; |
3d74bc09 BI |
427 | |
428 | m68k_compute_frame_layout(); | |
429 | ||
a157febd GK |
430 | /* If the stack limit is a symbol, we can check it here, |
431 | before actually allocating the space. */ | |
432 | if (current_function_limit_stack | |
433 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
e6d98cb0 BI |
434 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %I%s+%wd,%Rsp\n\ttrapcs\n", |
435 | XSTR (stack_limit_rtx, 0), current_frame.size + 4); | |
79e68feb | 436 | |
97c55091 | 437 | /* On ColdFire add register save into initial stack frame setup, if possible. */ |
a89e3f21 | 438 | fsize_with_regs = current_frame.size; |
3d74bc09 | 439 | if (TARGET_COLDFIRE && current_frame.reg_no > 2) |
a89e3f21 | 440 | fsize_with_regs += current_frame.reg_no * 4; |
860c4900 | 441 | |
79e68feb RS |
442 | if (frame_pointer_needed) |
443 | { | |
3d74bc09 | 444 | if (current_frame.size == 0 && TARGET_68040) |
e4e873f1 | 445 | /* on the 68040, pea + move is faster than link.w 0 */ |
e6d98cb0 BI |
446 | fprintf (stream, MOTOROLA ? |
447 | "\tpea (%s)\n\tmove.l %s,%s\n" : | |
448 | "\tpea %s@\n\tmovel %s,%s\n", | |
01bbf777 AS |
449 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
450 | M68K_REGNAME(STACK_POINTER_REGNUM), | |
451 | M68K_REGNAME(FRAME_POINTER_REGNUM)); | |
860c4900 | 452 | else if (fsize_with_regs < 0x8000) |
e6d98cb0 | 453 | asm_fprintf (stream, "\tlink" ASM_DOTW " %s,%I%wd\n", |
01bbf777 | 454 | M68K_REGNAME(FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 455 | else if (TARGET_68020) |
e6d98cb0 | 456 | asm_fprintf (stream, "\tlink" ASM_DOTL " %s,%I%wd\n", |
01bbf777 | 457 | M68K_REGNAME(FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 458 | else |
e6d98cb0 BI |
459 | /* Adding negative number is faster on the 68040. */ |
460 | asm_fprintf (stream, "\tlink" ASM_DOTW " %s,%I0\n" | |
461 | "\tadd" ASM_DOT "l %I%wd,%Rsp\n", | |
01bbf777 | 462 | M68K_REGNAME(FRAME_POINTER_REGNUM), -fsize_with_regs); |
e6d98cb0 | 463 | |
078e983e AS |
464 | if (dwarf2out_do_frame ()) |
465 | { | |
f5c4bc60 | 466 | char *l; |
01bbf777 | 467 | l = (char *) dwarf2out_cfi_label (); |
ed311a33 BI |
468 | cfa_offset += 4; |
469 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_offset); | |
67935d3f | 470 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset); |
3d74bc09 | 471 | cfa_offset += current_frame.size; |
078e983e | 472 | } |
79e68feb | 473 | } |
860c4900 | 474 | else if (fsize_with_regs) /* !frame_pointer_needed */ |
79e68feb | 475 | { |
860c4900 | 476 | if (fsize_with_regs < 0x8000) |
79e68feb | 477 | { |
860c4900 | 478 | if (fsize_with_regs <= 8) |
afaff477 | 479 | { |
9425fb04 | 480 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
481 | asm_fprintf (stream, "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", |
482 | fsize_with_regs); | |
7bc88d49 | 483 | else |
e6d98cb0 BI |
484 | asm_fprintf (stream, "\tsubq" ASM_DOT "l %I%wd,%Rsp\n", |
485 | fsize_with_regs); | |
afaff477 | 486 | } |
860c4900 | 487 | else if (fsize_with_regs <= 16 && TARGET_CPU32) |
e6d98cb0 BI |
488 | /* On the CPU32 it is faster to use two subqw instructions to |
489 | subtract a small integer (8 < N <= 16) to a register. */ | |
490 | asm_fprintf (stream, | |
491 | "\tsubq" ASM_DOT "w %I8,%Rsp\n" | |
492 | "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", | |
493 | fsize_with_regs - 8); | |
d1b87863 | 494 | else if (TARGET_68040) |
e6d98cb0 BI |
495 | /* Adding negative number is faster on the 68040. */ |
496 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", | |
497 | -fsize_with_regs); | |
7bc88d49 | 498 | else |
e6d98cb0 BI |
499 | asm_fprintf (stream, MOTOROLA ? |
500 | "\tlea (%wd,%Rsp),%Rsp\n" : | |
501 | "\tlea %Rsp@(%wd),%Rsp\n", | |
502 | -fsize_with_regs); | |
79e68feb | 503 | } |
860c4900 | 504 | else /* fsize_with_regs >= 0x8000 */ |
e6d98cb0 BI |
505 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", -fsize_with_regs); |
506 | ||
078e983e AS |
507 | if (dwarf2out_do_frame ()) |
508 | { | |
3d74bc09 | 509 | cfa_offset += current_frame.size + 4; |
078e983e AS |
510 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); |
511 | } | |
860c4900 BI |
512 | } /* !frame_pointer_needed */ |
513 | ||
57047680 | 514 | if (current_frame.fpu_mask) |
79e68feb | 515 | { |
e6d98cb0 BI |
516 | asm_fprintf (stream, MOTOROLA ? |
517 | "\tfmovm %I0x%x,-(%Rsp)\n" : | |
518 | "\tfmovem %I0x%x,%Rsp@-\n", | |
519 | current_frame.fpu_mask); | |
520 | ||
57047680 GN |
521 | if (dwarf2out_do_frame ()) |
522 | { | |
523 | char *l = (char *) dwarf2out_cfi_label (); | |
524 | int n_regs, regno; | |
525 | ||
526 | cfa_offset += current_frame.fpu_no * 12; | |
527 | if (! frame_pointer_needed) | |
528 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
529 | for (regno = 16, n_regs = 0; regno < 24; regno++) | |
530 | if (current_frame.fpu_mask & (1 << (regno - 16))) | |
531 | dwarf2out_reg_save (l, regno, -cfa_offset + n_regs++ * 12); | |
f277471f | 532 | } |
79e68feb | 533 | } |
99df2465 | 534 | |
01bbf777 | 535 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
536 | This has the disadvantage that it may be too late... */ |
537 | if (current_function_limit_stack) | |
538 | { | |
539 | if (REG_P (stack_limit_rtx)) | |
e6d98cb0 | 540 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %s,%Rsp\n\ttrapcs\n", |
01bbf777 | 541 | M68K_REGNAME(REGNO (stack_limit_rtx))); |
a157febd GK |
542 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
543 | warning ("stack limit expression is not supported"); | |
544 | } | |
01bbf777 | 545 | |
a89e3f21 | 546 | if (current_frame.reg_no <= 2) |
79e68feb RS |
547 | { |
548 | /* Store each separately in the same order moveml uses. | |
549 | Using two movel instructions instead of a single moveml | |
550 | is about 15% faster for the 68020 and 68030 at no expense | |
97c55091 | 551 | in code size. */ |
79e68feb RS |
552 | |
553 | int i; | |
554 | ||
3d74bc09 BI |
555 | for (i = 0; i < 16; i++) |
556 | if (current_frame.reg_rev_mask & (1 << i)) | |
078e983e | 557 | { |
e6d98cb0 BI |
558 | asm_fprintf (stream, MOTOROLA ? |
559 | "\t%Omove.l %s,-(%Rsp)\n" : | |
560 | "\tmovel %s,%Rsp@-\n", | |
01bbf777 | 561 | M68K_REGNAME(15 - i)); |
078e983e AS |
562 | if (dwarf2out_do_frame ()) |
563 | { | |
f5c4bc60 | 564 | char *l = (char *) dwarf2out_cfi_label (); |
a7cc7f29 | 565 | |
ed311a33 | 566 | cfa_offset += 4; |
01bbf777 AS |
567 | if (! frame_pointer_needed) |
568 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
569 | dwarf2out_reg_save (l, 15 - i, -cfa_offset); | |
078e983e AS |
570 | } |
571 | } | |
79e68feb | 572 | } |
3d74bc09 | 573 | else if (current_frame.reg_rev_mask) |
79e68feb | 574 | { |
9425fb04 | 575 | if (TARGET_COLDFIRE) |
01bbf777 | 576 | /* The ColdFire does not support the predecrement form of the |
e6d98cb0 BI |
577 | MOVEM instruction, so we must adjust the stack pointer and |
578 | then use the plain address register indirect mode. | |
579 | The required register save space was combined earlier with | |
580 | the fsize_with_regs amount. */ | |
581 | ||
582 | asm_fprintf (stream, MOTOROLA ? | |
583 | "\tmovm.l %I0x%x,(%Rsp)\n" : | |
584 | "\tmoveml %I0x%x,%Rsp@\n", | |
585 | current_frame.reg_mask); | |
afaff477 | 586 | else |
e6d98cb0 BI |
587 | asm_fprintf (stream, MOTOROLA ? |
588 | "\tmovm.l %I0x%x,-(%Rsp)\n" : | |
589 | "\tmoveml %I0x%x,%Rsp@-\n", | |
590 | current_frame.reg_rev_mask); | |
078e983e AS |
591 | if (dwarf2out_do_frame ()) |
592 | { | |
f5c4bc60 | 593 | char *l = (char *) dwarf2out_cfi_label (); |
3d74bc09 | 594 | int n_regs, regno; |
a7cc7f29 | 595 | |
3d74bc09 | 596 | cfa_offset += current_frame.reg_no * 4; |
078e983e | 597 | if (! frame_pointer_needed) |
ed311a33 | 598 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); |
078e983e | 599 | for (regno = 0, n_regs = 0; regno < 16; regno++) |
3d74bc09 | 600 | if (current_frame.reg_mask & (1 << regno)) |
57047680 | 601 | dwarf2out_reg_save (l, regno, -cfa_offset + n_regs++ * 4); |
078e983e | 602 | } |
79e68feb | 603 | } |
a2ef3db7 BI |
604 | if (!TARGET_SEP_DATA && flag_pic && |
605 | (current_function_uses_pic_offset_table || | |
606 | (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY))) | |
79e68feb | 607 | { |
a2ef3db7 BI |
608 | if (TARGET_ID_SHARED_LIBRARY) |
609 | { | |
610 | asm_fprintf (stream, "\tmovel %s@(%s), %s\n", | |
01bbf777 | 611 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM), |
a2ef3db7 | 612 | m68k_library_id_string, |
01bbf777 | 613 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM)); |
a2ef3db7 BI |
614 | } |
615 | else | |
616 | { | |
e6d98cb0 BI |
617 | if (MOTOROLA) |
618 | asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", | |
01bbf777 | 619 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM)); |
e6d98cb0 BI |
620 | else |
621 | { | |
622 | asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n", | |
01bbf777 | 623 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM)); |
e6d98cb0 | 624 | asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", |
01bbf777 AS |
625 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM), |
626 | M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 | 627 | } |
a2ef3db7 | 628 | } |
79e68feb RS |
629 | } |
630 | } | |
631 | \f | |
632 | /* Return true if this function's epilogue can be output as RTL. */ | |
633 | ||
3d74bc09 BI |
634 | bool |
635 | use_return_insn (void) | |
79e68feb | 636 | { |
79e68feb | 637 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 638 | return false; |
125ed86f | 639 | |
3d74bc09 BI |
640 | /* We can output the epilogue as RTL only if no registers need to be |
641 | restored. */ | |
642 | m68k_compute_frame_layout(); | |
643 | return current_frame.reg_no ? false : true; | |
79e68feb RS |
644 | } |
645 | ||
646 | /* This function generates the assembly code for function exit, | |
08c148a8 | 647 | on machines that need it. |
79e68feb RS |
648 | |
649 | The function epilogue should not depend on the current stack pointer! | |
650 | It should use the frame pointer only, if there is a frame pointer. | |
651 | This is mandatory because of alloca; we also take advantage of it to | |
652 | omit stack adjustments before returning. */ | |
653 | ||
08c148a8 | 654 | static void |
3d74bc09 | 655 | m68k_output_function_epilogue (FILE *stream, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
08c148a8 | 656 | { |
3d74bc09 BI |
657 | HOST_WIDE_INT fsize, fsize_with_regs; |
658 | bool big = false; | |
659 | bool restore_from_sp = false; | |
79e68feb | 660 | rtx insn = get_last_insn (); |
3d74bc09 BI |
661 | |
662 | m68k_compute_frame_layout(); | |
663 | ||
79e68feb RS |
664 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
665 | if (GET_CODE (insn) == NOTE) | |
666 | insn = prev_nonnote_insn (insn); | |
667 | if (insn && GET_CODE (insn) == BARRIER) | |
cffd0d74 RS |
668 | { |
669 | /* Output just a no-op so that debuggers don't get confused | |
670 | about which function the pc is in at this address. */ | |
761c70aa | 671 | fprintf (stream, "\tnop\n"); |
cffd0d74 RS |
672 | return; |
673 | } | |
79e68feb RS |
674 | |
675 | #ifdef FUNCTION_EXTRA_EPILOGUE | |
676 | FUNCTION_EXTRA_EPILOGUE (stream, size); | |
677 | #endif | |
3d74bc09 BI |
678 | |
679 | fsize = current_frame.size; | |
680 | ||
c67ddce5 RK |
681 | /* FIXME : leaf_function_p below is too strong. |
682 | What we really need to know there is if there could be pending | |
7a1929e1 | 683 | stack adjustment needed at that point. */ |
6910dd70 RK |
684 | restore_from_sp = ! frame_pointer_needed |
685 | || (! current_function_calls_alloca && leaf_function_p ()); | |
860c4900 BI |
686 | |
687 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 688 | popping the frame. */ |
860c4900 BI |
689 | fsize_with_regs = fsize; |
690 | ||
691 | /* Because the ColdFire doesn't support moveml with | |
692 | complex address modes, we must adjust the stack manually | |
693 | after restoring registers. When the frame pointer isn't used, | |
694 | we can merge movem adjustment into frame unlinking | |
97c55091 | 695 | made immediately after it. */ |
3d74bc09 BI |
696 | if (TARGET_COLDFIRE && restore_from_sp && (current_frame.reg_no > 2)) |
697 | fsize_with_regs += current_frame.reg_no * 4; | |
860c4900 | 698 | |
3d74bc09 | 699 | if (current_frame.offset + fsize >= 0x8000 |
6910dd70 | 700 | && ! restore_from_sp |
3d74bc09 | 701 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 702 | { |
860c4900 | 703 | /* Because the ColdFire doesn't support moveml with |
97c55091 | 704 | complex address modes we make an extra correction here. */ |
860c4900 | 705 | if (TARGET_COLDFIRE) |
e6d98cb0 | 706 | fsize += current_frame.offset; |
860c4900 | 707 | |
e6d98cb0 | 708 | asm_fprintf (stream, "\t%Omove" ASM_DOT "l %I%wd,%Ra1\n", -fsize); |
3d74bc09 | 709 | fsize = 0, big = true; |
79e68feb | 710 | } |
3d74bc09 | 711 | if (current_frame.reg_no <= 2) |
79e68feb RS |
712 | { |
713 | /* Restore each separately in the same order moveml does. | |
714 | Using two movel instructions instead of a single moveml | |
715 | is about 15% faster for the 68020 and 68030 at no expense | |
7a1929e1 | 716 | in code size. */ |
79e68feb RS |
717 | |
718 | int i; | |
3d74bc09 | 719 | HOST_WIDE_INT offset = current_frame.offset + fsize; |
79e68feb | 720 | |
3d74bc09 BI |
721 | for (i = 0; i < 16; i++) |
722 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb RS |
723 | { |
724 | if (big) | |
725 | { | |
e6d98cb0 BI |
726 | if (MOTOROLA) |
727 | asm_fprintf (stream, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n", | |
728 | offset, | |
01bbf777 AS |
729 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
730 | M68K_REGNAME(i)); | |
e6d98cb0 BI |
731 | else |
732 | asm_fprintf (stream, "\tmovel %s@(-%wd,%Ra1:l),%s\n", | |
01bbf777 | 733 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 | 734 | offset, |
01bbf777 | 735 | M68K_REGNAME(i)); |
79e68feb | 736 | } |
6910dd70 | 737 | else if (restore_from_sp) |
e6d98cb0 BI |
738 | asm_fprintf (stream, MOTOROLA ? |
739 | "\t%Omove.l (%Rsp)+,%s\n" : | |
740 | "\tmovel %Rsp@+,%s\n", | |
01bbf777 | 741 | M68K_REGNAME(i)); |
79e68feb RS |
742 | else |
743 | { | |
e6d98cb0 BI |
744 | if (MOTOROLA) |
745 | asm_fprintf (stream, "\t%Omove.l -%wd(%s),%s\n", | |
746 | offset, | |
01bbf777 AS |
747 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
748 | M68K_REGNAME(i)); | |
e6d98cb0 BI |
749 | else |
750 | asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n", | |
01bbf777 | 751 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 | 752 | offset, |
01bbf777 | 753 | M68K_REGNAME(i)); |
79e68feb | 754 | } |
3d74bc09 | 755 | offset -= 4; |
79e68feb RS |
756 | } |
757 | } | |
3d74bc09 | 758 | else if (current_frame.reg_mask) |
79e68feb | 759 | { |
97c55091 | 760 | /* The ColdFire requires special handling due to its limited moveml insn. */ |
860c4900 BI |
761 | if (TARGET_COLDFIRE) |
762 | { | |
763 | if (big) | |
764 | { | |
e6d98cb0 | 765 | asm_fprintf (stream, "\tadd" ASM_DOT "l %s,%Ra1\n", |
01bbf777 | 766 | M68K_REGNAME(FRAME_POINTER_REGNUM)); |
e6d98cb0 BI |
767 | asm_fprintf (stream, MOTOROLA ? |
768 | "\tmovm.l (%Ra1),%I0x%x\n" : | |
769 | "\tmoveml %Ra1@,%I0x%x\n", | |
770 | current_frame.reg_mask); | |
860c4900 BI |
771 | } |
772 | else if (restore_from_sp) | |
e6d98cb0 BI |
773 | asm_fprintf (stream, MOTOROLA ? |
774 | "\tmovm.l (%Rsp),%I0x%x\n" : | |
775 | "\tmoveml %Rsp@,%I0x%x\n", | |
776 | current_frame.reg_mask); | |
860c4900 BI |
777 | else |
778 | { | |
e6d98cb0 BI |
779 | if (MOTOROLA) |
780 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
781 | current_frame.offset + fsize, | |
01bbf777 | 782 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
783 | current_frame.reg_mask); |
784 | else | |
785 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
01bbf777 | 786 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
787 | current_frame.offset + fsize, |
788 | current_frame.reg_mask); | |
860c4900 BI |
789 | } |
790 | } | |
791 | else /* !TARGET_COLDFIRE */ | |
79e68feb | 792 | { |
860c4900 BI |
793 | if (big) |
794 | { | |
e6d98cb0 BI |
795 | if (MOTOROLA) |
796 | asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n", | |
797 | current_frame.offset + fsize, | |
01bbf777 | 798 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
799 | current_frame.reg_mask); |
800 | else | |
801 | asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n", | |
01bbf777 | 802 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
803 | current_frame.offset + fsize, |
804 | current_frame.reg_mask); | |
860c4900 BI |
805 | } |
806 | else if (restore_from_sp) | |
807 | { | |
e6d98cb0 BI |
808 | asm_fprintf (stream, MOTOROLA ? |
809 | "\tmovm.l (%Rsp)+,%I0x%x\n" : | |
810 | "\tmoveml %Rsp@+,%I0x%x\n", | |
3d74bc09 | 811 | current_frame.reg_mask); |
860c4900 BI |
812 | } |
813 | else | |
814 | { | |
e6d98cb0 BI |
815 | if (MOTOROLA) |
816 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
817 | current_frame.offset + fsize, | |
01bbf777 | 818 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
819 | current_frame.reg_mask); |
820 | else | |
821 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
01bbf777 | 822 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
823 | current_frame.offset + fsize, |
824 | current_frame.reg_mask); | |
860c4900 | 825 | } |
79e68feb RS |
826 | } |
827 | } | |
3d74bc09 | 828 | if (current_frame.fpu_rev_mask) |
79e68feb RS |
829 | { |
830 | if (big) | |
831 | { | |
e6d98cb0 BI |
832 | if (MOTOROLA) |
833 | asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n", | |
834 | current_frame.foffset + fsize, | |
01bbf777 | 835 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
836 | current_frame.fpu_rev_mask); |
837 | else | |
838 | asm_fprintf (stream, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n", | |
01bbf777 | 839 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
840 | current_frame.foffset + fsize, |
841 | current_frame.fpu_rev_mask); | |
79e68feb | 842 | } |
6910dd70 | 843 | else if (restore_from_sp) |
79e68feb | 844 | { |
e6d98cb0 BI |
845 | if (MOTOROLA) |
846 | asm_fprintf (stream, "\tfmovm (%Rsp)+,%I0x%x\n", | |
847 | current_frame.fpu_rev_mask); | |
848 | else | |
849 | asm_fprintf (stream, "\tfmovem %Rsp@+,%I0x%x\n", | |
850 | current_frame.fpu_rev_mask); | |
79e68feb RS |
851 | } |
852 | else | |
853 | { | |
e6d98cb0 BI |
854 | if (MOTOROLA) |
855 | asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n", | |
856 | current_frame.foffset + fsize, | |
01bbf777 | 857 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
858 | current_frame.fpu_rev_mask); |
859 | else | |
860 | asm_fprintf (stream, "\tfmovem %s@(-%wd),%I0x%x\n", | |
01bbf777 | 861 | M68K_REGNAME(FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
862 | current_frame.foffset + fsize, |
863 | current_frame.fpu_rev_mask); | |
79e68feb RS |
864 | } |
865 | } | |
79e68feb | 866 | if (frame_pointer_needed) |
01bbf777 | 867 | fprintf (stream, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM)); |
860c4900 | 868 | else if (fsize_with_regs) |
79e68feb | 869 | { |
860c4900 | 870 | if (fsize_with_regs <= 8) |
79e68feb | 871 | { |
9425fb04 | 872 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
873 | asm_fprintf (stream, "\taddq" ASM_DOT "w %I%wd,%Rsp\n", |
874 | fsize_with_regs); | |
875 | else | |
876 | asm_fprintf (stream, "\taddq" ASM_DOT "l %I%wd,%Rsp\n", | |
877 | fsize_with_regs); | |
7bc88d49 | 878 | } |
860c4900 | 879 | else if (fsize_with_regs <= 16 && TARGET_CPU32) |
7bc88d49 RK |
880 | { |
881 | /* On the CPU32 it is faster to use two addqw instructions to | |
7a1929e1 | 882 | add a small integer (8 < N <= 16) to a register. */ |
e6d98cb0 BI |
883 | asm_fprintf (stream, "\taddq" ASM_DOT "w %I8,%Rsp\n" |
884 | "\taddq" ASM_DOT "w %I%wd,%Rsp\n", | |
860c4900 | 885 | fsize_with_regs - 8); |
7bc88d49 | 886 | } |
860c4900 | 887 | else if (fsize_with_regs < 0x8000) |
7bc88d49 RK |
888 | { |
889 | if (TARGET_68040) | |
e6d98cb0 BI |
890 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", |
891 | fsize_with_regs); | |
7bc88d49 | 892 | else |
e6d98cb0 BI |
893 | asm_fprintf (stream, MOTOROLA ? |
894 | "\tlea (%wd,%Rsp),%Rsp\n" : | |
895 | "\tlea %Rsp@(%wd),%Rsp\n", | |
896 | fsize_with_regs); | |
79e68feb RS |
897 | } |
898 | else | |
e6d98cb0 | 899 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); |
79e68feb | 900 | } |
2cff4a6e | 901 | if (current_function_calls_eh_return) |
e6d98cb0 | 902 | asm_fprintf (stream, "\tadd" ASM_DOT"l %Ra0,%Rsp\n"); |
3d74bc09 | 903 | if (m68k_interrupt_function_p (current_function_decl)) |
48ed72a4 PB |
904 | fprintf (stream, "\trte\n"); |
905 | else if (current_function_pops_args) | |
1f85a612 | 906 | asm_fprintf (stream, "\trtd %I%d\n", current_function_pops_args); |
79e68feb RS |
907 | else |
908 | fprintf (stream, "\trts\n"); | |
909 | } | |
910 | \f | |
911 | /* Similar to general_operand, but exclude stack_pointer_rtx. */ | |
912 | ||
913 | int | |
8a4a2253 | 914 | not_sp_operand (rtx op, enum machine_mode mode) |
79e68feb | 915 | { |
8406d023 | 916 | return op != stack_pointer_rtx && nonimmediate_operand (op, mode); |
79e68feb RS |
917 | } |
918 | ||
8a4a2253 | 919 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
920 | instruction. |
921 | ||
922 | Note it rejects floating point comparison operators. | |
923 | (In the future we could use Fdbcc). | |
924 | ||
925 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
926 | ||
927 | int | |
8a4a2253 | 928 | valid_dbcc_comparison_p (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 929 | { |
64a184e9 RS |
930 | switch (GET_CODE (x)) |
931 | { | |
64a184e9 RS |
932 | case EQ: case NE: case GTU: case LTU: |
933 | case GEU: case LEU: | |
934 | return 1; | |
935 | ||
936 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
937 | conservative */ | |
938 | case GT: case LT: case GE: case LE: | |
939 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
940 | default: | |
941 | return 0; | |
942 | } | |
943 | } | |
944 | ||
a0ab749a | 945 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 946 | int |
8a4a2253 | 947 | flags_in_68881 (void) |
6a0f85e3 TG |
948 | { |
949 | /* We could add support for these in the future */ | |
950 | return cc_status.flags & CC_IN_68881; | |
951 | } | |
952 | ||
a2ef3db7 BI |
953 | /* Output a BSR instruction suitable for PIC code. */ |
954 | void | |
955 | m68k_output_pic_call(rtx dest) | |
956 | { | |
957 | const char *out; | |
958 | ||
959 | if (!(GET_CODE (dest) == MEM && GET_CODE (XEXP (dest, 0)) == SYMBOL_REF)) | |
960 | out = "jsr %0"; | |
b2e08ed4 | 961 | /* We output a BSR instruction if we're using -fpic or we're building for |
a2ef3db7 BI |
962 | * a target that supports long branches. If we're building -fPIC on the |
963 | * 68000, 68010 or ColdFire we generate one of two sequences: | |
964 | * a shorter one that uses a GOT entry or a longer one that doesn't. | |
965 | * We'll use the -Os command-line flag to decide which to generate. | |
966 | * Both sequences take the same time to execute on the ColdFire. | |
967 | */ | |
968 | else if (TARGET_PCREL) | |
969 | out = "bsr.l %o0"; | |
970 | else if ((flag_pic == 1) || TARGET_68020) | |
1f0282cb | 971 | #if defined(USE_GAS) |
a2ef3db7 BI |
972 | out = "bsr.l %0@PLTPC"; |
973 | #else | |
974 | out = "bsr %0@PLTPC"; | |
975 | #endif | |
976 | else if (optimize_size || TARGET_ID_SHARED_LIBRARY) | |
977 | out = "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)"; | |
978 | else | |
979 | out = "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)"; | |
980 | ||
981 | output_asm_insn(out, &dest); | |
982 | } | |
983 | ||
64a184e9 RS |
984 | /* Output a dbCC; jCC sequence. Note we do not handle the |
985 | floating point version of this sequence (Fdbcc). We also | |
986 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
987 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
988 | kick those out before we get here. */ | |
64a184e9 | 989 | |
1d8eaa6b | 990 | void |
8a4a2253 | 991 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 992 | { |
64a184e9 RS |
993 | switch (GET_CODE (operands[3])) |
994 | { | |
995 | case EQ: | |
e6d98cb0 BI |
996 | output_asm_insn (MOTOROLA ? |
997 | "dbeq %0,%l1\n\tjbeq %l2" : | |
998 | "dbeq %0,%l1\n\tjeq %l2", | |
999 | operands); | |
1000 | break; | |
64a184e9 RS |
1001 | |
1002 | case NE: | |
e6d98cb0 BI |
1003 | output_asm_insn (MOTOROLA ? |
1004 | "dbne %0,%l1\n\tjbne %l2" : | |
1005 | "dbne %0,%l1\n\tjne %l2", | |
1006 | operands); | |
1007 | break; | |
64a184e9 RS |
1008 | |
1009 | case GT: | |
e6d98cb0 BI |
1010 | output_asm_insn (MOTOROLA ? |
1011 | "dbgt %0,%l1\n\tjbgt %l2" : | |
1012 | "dbgt %0,%l1\n\tjgt %l2", | |
1013 | operands); | |
1014 | break; | |
64a184e9 RS |
1015 | |
1016 | case GTU: | |
e6d98cb0 BI |
1017 | output_asm_insn (MOTOROLA ? |
1018 | "dbhi %0,%l1\n\tjbhi %l2" : | |
1019 | "dbhi %0,%l1\n\tjhi %l2", | |
1020 | operands); | |
1021 | break; | |
64a184e9 RS |
1022 | |
1023 | case LT: | |
e6d98cb0 BI |
1024 | output_asm_insn (MOTOROLA ? |
1025 | "dblt %0,%l1\n\tjblt %l2" : | |
1026 | "dblt %0,%l1\n\tjlt %l2", | |
1027 | operands); | |
1028 | break; | |
64a184e9 RS |
1029 | |
1030 | case LTU: | |
e6d98cb0 BI |
1031 | output_asm_insn (MOTOROLA ? |
1032 | "dbcs %0,%l1\n\tjbcs %l2" : | |
1033 | "dbcs %0,%l1\n\tjcs %l2", | |
1034 | operands); | |
1035 | break; | |
64a184e9 RS |
1036 | |
1037 | case GE: | |
e6d98cb0 BI |
1038 | output_asm_insn (MOTOROLA ? |
1039 | "dbge %0,%l1\n\tjbge %l2" : | |
1040 | "dbge %0,%l1\n\tjge %l2", | |
1041 | operands); | |
1042 | break; | |
64a184e9 RS |
1043 | |
1044 | case GEU: | |
e6d98cb0 BI |
1045 | output_asm_insn (MOTOROLA ? |
1046 | "dbcc %0,%l1\n\tjbcc %l2" : | |
1047 | "dbcc %0,%l1\n\tjcc %l2", | |
1048 | operands); | |
1049 | break; | |
64a184e9 RS |
1050 | |
1051 | case LE: | |
e6d98cb0 BI |
1052 | output_asm_insn (MOTOROLA ? |
1053 | "dble %0,%l1\n\tjble %l2" : | |
1054 | "dble %0,%l1\n\tjle %l2", | |
1055 | operands); | |
1056 | break; | |
64a184e9 RS |
1057 | |
1058 | case LEU: | |
e6d98cb0 BI |
1059 | output_asm_insn (MOTOROLA ? |
1060 | "dbls %0,%l1\n\tjbls %l2" : | |
1061 | "dbls %0,%l1\n\tjls %l2", | |
1062 | operands); | |
1063 | break; | |
64a184e9 RS |
1064 | |
1065 | default: | |
1066 | abort (); | |
1067 | } | |
1068 | ||
1069 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1070 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1071 | switch (GET_MODE (operands[0])) |
1072 | { | |
1073 | case SImode: | |
e6d98cb0 | 1074 | output_asm_insn (MOTOROLA ? |
3b4b85c9 BI |
1075 | "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" : |
1076 | "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1077 | operands); |
64a184e9 RS |
1078 | break; |
1079 | ||
1080 | case HImode: | |
1081 | break; | |
1082 | ||
1083 | default: | |
1084 | abort (); | |
1085 | } | |
1086 | } | |
1087 | ||
5505f548 | 1088 | const char * |
8a4a2253 | 1089 | output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1090 | { |
1091 | rtx loperands[7]; | |
d9832fd2 | 1092 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1093 | |
f710504c | 1094 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1095 | CC_STATUS_INIT; |
1096 | ||
d9832fd2 RK |
1097 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1098 | below. Swap the operands and change the op if these requirements | |
1099 | are not fulfilled. */ | |
1100 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1101 | { | |
1102 | rtx tmp = operand1; | |
1103 | ||
1104 | operand1 = operand2; | |
1105 | operand2 = tmp; | |
1106 | op_code = swap_condition (op_code); | |
1107 | } | |
c59c3b1c RK |
1108 | loperands[0] = operand1; |
1109 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1110 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1111 | else |
b72f00af | 1112 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1113 | if (operand2 != const0_rtx) |
1114 | { | |
1115 | loperands[2] = operand2; | |
1116 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1117 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1118 | else |
b72f00af | 1119 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c RK |
1120 | } |
1121 | loperands[4] = gen_label_rtx(); | |
1122 | if (operand2 != const0_rtx) | |
4a8c52e0 | 1123 | { |
3b4b85c9 BI |
1124 | output_asm_insn (MOTOROLA ? |
1125 | "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" : | |
1126 | "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1127 | loperands); | |
4a8c52e0 | 1128 | } |
392582fa | 1129 | else |
4a8c52e0 | 1130 | { |
9425fb04 | 1131 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1132 | output_asm_insn ("tst%.l %0", loperands); |
1133 | else | |
1134 | { | |
3b4b85c9 | 1135 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 AS |
1136 | } |
1137 | ||
e6d98cb0 | 1138 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1139 | |
9425fb04 | 1140 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1141 | output_asm_insn ("tst%.l %1", loperands); |
1142 | else | |
3b4b85c9 | 1143 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1144 | } |
1145 | ||
c59c3b1c | 1146 | loperands[5] = dest; |
3b4b85c9 | 1147 | |
d9832fd2 | 1148 | switch (op_code) |
c59c3b1c RK |
1149 | { |
1150 | case EQ: | |
4977bab6 | 1151 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1152 | CODE_LABEL_NUMBER (loperands[4])); |
1153 | output_asm_insn ("seq %5", loperands); | |
1154 | break; | |
1155 | ||
1156 | case NE: | |
4977bab6 | 1157 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1158 | CODE_LABEL_NUMBER (loperands[4])); |
1159 | output_asm_insn ("sne %5", loperands); | |
1160 | break; | |
1161 | ||
1162 | case GT: | |
1163 | loperands[6] = gen_label_rtx(); | |
e6d98cb0 BI |
1164 | output_asm_insn (MOTOROLA ? |
1165 | "shi %5\n\tjbra %l6" : | |
1166 | "shi %5\n\tjra %l6", | |
1167 | loperands); | |
4977bab6 | 1168 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1169 | CODE_LABEL_NUMBER (loperands[4])); |
1170 | output_asm_insn ("sgt %5", loperands); | |
4977bab6 | 1171 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1172 | CODE_LABEL_NUMBER (loperands[6])); |
1173 | break; | |
1174 | ||
1175 | case GTU: | |
4977bab6 | 1176 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1177 | CODE_LABEL_NUMBER (loperands[4])); |
1178 | output_asm_insn ("shi %5", loperands); | |
1179 | break; | |
1180 | ||
1181 | case LT: | |
1182 | loperands[6] = gen_label_rtx(); | |
e6d98cb0 BI |
1183 | output_asm_insn (MOTOROLA ? |
1184 | "scs %5\n\tjbra %l6" : | |
1185 | "scs %5\n\tjra %l6", | |
1186 | loperands); | |
4977bab6 | 1187 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1188 | CODE_LABEL_NUMBER (loperands[4])); |
1189 | output_asm_insn ("slt %5", loperands); | |
4977bab6 | 1190 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1191 | CODE_LABEL_NUMBER (loperands[6])); |
1192 | break; | |
1193 | ||
1194 | case LTU: | |
4977bab6 | 1195 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1196 | CODE_LABEL_NUMBER (loperands[4])); |
1197 | output_asm_insn ("scs %5", loperands); | |
1198 | break; | |
1199 | ||
1200 | case GE: | |
1201 | loperands[6] = gen_label_rtx(); | |
e6d98cb0 BI |
1202 | output_asm_insn (MOTOROLA ? |
1203 | "scc %5\n\tjbra %l6" : | |
1204 | "scc %5\n\tjra %l6", | |
1205 | loperands); | |
4977bab6 | 1206 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1207 | CODE_LABEL_NUMBER (loperands[4])); |
1208 | output_asm_insn ("sge %5", loperands); | |
4977bab6 | 1209 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1210 | CODE_LABEL_NUMBER (loperands[6])); |
1211 | break; | |
1212 | ||
1213 | case GEU: | |
4977bab6 | 1214 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1215 | CODE_LABEL_NUMBER (loperands[4])); |
1216 | output_asm_insn ("scc %5", loperands); | |
1217 | break; | |
1218 | ||
1219 | case LE: | |
1220 | loperands[6] = gen_label_rtx(); | |
e6d98cb0 BI |
1221 | output_asm_insn (MOTOROLA ? |
1222 | "sls %5\n\tjbra %l6" : | |
1223 | "sls %5\n\tjra %l6", | |
1224 | loperands); | |
4977bab6 | 1225 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1226 | CODE_LABEL_NUMBER (loperands[4])); |
1227 | output_asm_insn ("sle %5", loperands); | |
4977bab6 | 1228 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1229 | CODE_LABEL_NUMBER (loperands[6])); |
1230 | break; | |
1231 | ||
1232 | case LEU: | |
4977bab6 | 1233 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
c59c3b1c RK |
1234 | CODE_LABEL_NUMBER (loperands[4])); |
1235 | output_asm_insn ("sls %5", loperands); | |
1236 | break; | |
1237 | ||
1238 | default: | |
1239 | abort (); | |
1240 | } | |
1241 | return ""; | |
1242 | } | |
1243 | ||
5505f548 | 1244 | const char * |
8a4a2253 | 1245 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1246 | { |
1247 | operands[0] = countop; | |
1248 | operands[1] = dataop; | |
1249 | ||
1250 | if (GET_CODE (countop) == CONST_INT) | |
1251 | { | |
1252 | register int count = INTVAL (countop); | |
1253 | /* If COUNT is bigger than size of storage unit in use, | |
1254 | advance to the containing unit of same size. */ | |
1255 | if (count > signpos) | |
1256 | { | |
1257 | int offset = (count & ~signpos) / 8; | |
1258 | count = count & signpos; | |
b72f00af | 1259 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1260 | } |
1261 | if (count == signpos) | |
1262 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1263 | else | |
1264 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1265 | ||
1266 | /* These three statements used to use next_insns_test_no... | |
1267 | but it appears that this should do the same job. */ | |
1268 | if (count == 31 | |
1269 | && next_insn_tests_no_inequality (insn)) | |
1270 | return "tst%.l %1"; | |
1271 | if (count == 15 | |
1272 | && next_insn_tests_no_inequality (insn)) | |
1273 | return "tst%.w %1"; | |
1274 | if (count == 7 | |
1275 | && next_insn_tests_no_inequality (insn)) | |
1276 | return "tst%.b %1"; | |
1277 | ||
1278 | cc_status.flags = CC_NOT_NEGATIVE; | |
1279 | } | |
1280 | return "btst %0,%1"; | |
1281 | } | |
1282 | \f | |
8a4a2253 | 1283 | /* Returns true if OP is either a symbol reference or a sum of a symbol |
79e68feb RS |
1284 | reference and a constant. */ |
1285 | ||
8a4a2253 BI |
1286 | bool |
1287 | symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
79e68feb RS |
1288 | { |
1289 | switch (GET_CODE (op)) | |
1290 | { | |
1291 | case SYMBOL_REF: | |
1292 | case LABEL_REF: | |
8a4a2253 | 1293 | return true; |
79e68feb RS |
1294 | |
1295 | case CONST: | |
1296 | op = XEXP (op, 0); | |
1297 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1298 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1299 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1300 | ||
1301 | #if 0 /* Deleted, with corresponding change in m68k.h, | |
1302 | so as to fit the specs. No CONST_DOUBLE is ever symbolic. */ | |
1303 | case CONST_DOUBLE: | |
1304 | return GET_MODE (op) == mode; | |
1305 | #endif | |
1306 | ||
1307 | default: | |
8a4a2253 | 1308 | return false; |
79e68feb RS |
1309 | } |
1310 | } | |
16f323be | 1311 | \f |
7a1929e1 | 1312 | /* Check for sign_extend or zero_extend. Used for bit-count operands. */ |
16f323be RK |
1313 | |
1314 | int | |
8a4a2253 | 1315 | extend_operator(rtx x, enum machine_mode mode) |
16f323be | 1316 | { |
c59c3b1c | 1317 | if (mode != VOIDmode && GET_MODE(x) != mode) |
16f323be RK |
1318 | return 0; |
1319 | switch (GET_CODE(x)) | |
1320 | { | |
1321 | case SIGN_EXTEND : | |
1322 | case ZERO_EXTEND : | |
16f323be RK |
1323 | return 1; |
1324 | default : | |
1325 | return 0; | |
1326 | } | |
1327 | } | |
79e68feb RS |
1328 | |
1329 | \f | |
1330 | /* Legitimize PIC addresses. If the address is already | |
1331 | position-independent, we return ORIG. Newly generated | |
1332 | position-independent addresses go to REG. If we need more | |
1333 | than one register, we lose. | |
1334 | ||
1335 | An address is legitimized by making an indirect reference | |
1336 | through the Global Offset Table with the name of the symbol | |
1337 | used as an offset. | |
1338 | ||
1339 | The assembler and linker are responsible for placing the | |
1340 | address of the symbol in the GOT. The function prologue | |
1341 | is responsible for initializing a5 to the starting address | |
1342 | of the GOT. | |
1343 | ||
1344 | The assembler is also responsible for translating a symbol name | |
1345 | into a constant displacement from the start of the GOT. | |
1346 | ||
1347 | A quick example may make things a little clearer: | |
1348 | ||
1349 | When not generating PIC code to store the value 12345 into _foo | |
1350 | we would generate the following code: | |
1351 | ||
1352 | movel #12345, _foo | |
1353 | ||
1354 | When generating PIC two transformations are made. First, the compiler | |
1355 | loads the address of foo into a register. So the first transformation makes: | |
1356 | ||
1357 | lea _foo, a0 | |
1358 | movel #12345, a0@ | |
1359 | ||
1360 | The code in movsi will intercept the lea instruction and call this | |
1361 | routine which will transform the instructions into: | |
1362 | ||
1363 | movel a5@(_foo:w), a0 | |
1364 | movel #12345, a0@ | |
1365 | ||
1366 | ||
1367 | That (in a nutshell) is how *all* symbol and label references are | |
1368 | handled. */ | |
1369 | ||
1370 | rtx | |
8a4a2253 BI |
1371 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1372 | rtx reg) | |
79e68feb RS |
1373 | { |
1374 | rtx pic_ref = orig; | |
1375 | ||
1376 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1377 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1378 | { | |
1379 | if (reg == 0) | |
1380 | abort (); | |
1381 | ||
1d8eaa6b AS |
1382 | pic_ref = gen_rtx_MEM (Pmode, |
1383 | gen_rtx_PLUS (Pmode, | |
1384 | pic_offset_table_rtx, orig)); | |
79e68feb RS |
1385 | current_function_uses_pic_offset_table = 1; |
1386 | RTX_UNCHANGING_P (pic_ref) = 1; | |
1387 | emit_move_insn (reg, pic_ref); | |
1388 | return reg; | |
1389 | } | |
1390 | else if (GET_CODE (orig) == CONST) | |
1391 | { | |
1d8eaa6b | 1392 | rtx base; |
79e68feb | 1393 | |
b2e08ed4 | 1394 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
1395 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
1396 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1397 | return orig; | |
1398 | ||
1399 | if (reg == 0) | |
1400 | abort (); | |
1401 | ||
1402 | /* legitimize both operands of the PLUS */ | |
1403 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1404 | { | |
1405 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
1406 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
1407 | base == reg ? 0 : reg); | |
1408 | } | |
1409 | else abort (); | |
1410 | ||
1411 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 1412 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 1413 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
1414 | /* Likewise, should we set special REG_NOTEs here? */ |
1415 | } | |
1416 | return pic_ref; | |
1417 | } | |
1418 | ||
1419 | \f | |
28bad6d1 | 1420 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 1421 | |
8a4a2253 | 1422 | static CONST_METHOD const_method (rtx); |
5505f548 | 1423 | |
6910dd70 | 1424 | #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255) |
0ce6f9fb | 1425 | |
5505f548 | 1426 | static CONST_METHOD |
8a4a2253 | 1427 | const_method (rtx constant) |
0ce6f9fb RK |
1428 | { |
1429 | int i; | |
1430 | unsigned u; | |
1431 | ||
1432 | i = INTVAL (constant); | |
6910dd70 | 1433 | if (USE_MOVQ (i)) |
0ce6f9fb | 1434 | return MOVQ; |
24092242 | 1435 | |
c16eadc7 | 1436 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 1437 | /* FIXME: This may not be useful for the m68060 either. */ |
9425fb04 | 1438 | if (!TARGET_COLDFIRE) |
24092242 RK |
1439 | { |
1440 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 1441 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
1442 | if (USE_MOVQ (i ^ 0xff)) |
1443 | return NOTB; | |
1444 | /* Likewise, try with not.w */ | |
1445 | if (USE_MOVQ (i ^ 0xffff)) | |
1446 | return NOTW; | |
1447 | /* This is the only value where neg.w is useful */ | |
1448 | if (i == -65408) | |
1449 | return NEGW; | |
1450 | /* Try also with swap */ | |
1451 | u = i; | |
1452 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
1453 | return SWAP; | |
1454 | } | |
28bad6d1 PB |
1455 | |
1456 | if (TARGET_CFV4) | |
1457 | { | |
72edf146 | 1458 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
1459 | if (i >= 0 && i <= 65535) |
1460 | return MVZ; | |
1461 | if (i >= -32768 && i <= 32767) | |
1462 | return MVS; | |
1463 | } | |
1464 | ||
0ce6f9fb RK |
1465 | /* Otherwise, use move.l */ |
1466 | return MOVL; | |
1467 | } | |
1468 | ||
3c50106f | 1469 | static int |
8a4a2253 | 1470 | const_int_cost (rtx constant) |
0ce6f9fb RK |
1471 | { |
1472 | switch (const_method (constant)) | |
1473 | { | |
1474 | case MOVQ : | |
1475 | /* Constants between -128 and 127 are cheap due to moveq */ | |
1476 | return 0; | |
28bad6d1 PB |
1477 | case MVZ: |
1478 | case MVS: | |
0ce6f9fb RK |
1479 | case NOTB : |
1480 | case NOTW : | |
1481 | case NEGW : | |
1482 | case SWAP : | |
1483 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */ | |
1484 | return 1; | |
1485 | case MOVL : | |
1486 | return 2; | |
1487 | default : | |
1488 | abort (); | |
1489 | } | |
1490 | } | |
1491 | ||
3c50106f | 1492 | static bool |
8a4a2253 | 1493 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1494 | { |
1495 | switch (code) | |
1496 | { | |
1497 | case CONST_INT: | |
1498 | /* Constant zero is super cheap due to clr instruction. */ | |
1499 | if (x == const0_rtx) | |
1500 | *total = 0; | |
1501 | else | |
1502 | *total = const_int_cost (x); | |
1503 | return true; | |
1504 | ||
1505 | case CONST: | |
1506 | case LABEL_REF: | |
1507 | case SYMBOL_REF: | |
1508 | *total = 3; | |
1509 | return true; | |
1510 | ||
1511 | case CONST_DOUBLE: | |
1512 | /* Make 0.0 cheaper than other floating constants to | |
1513 | encourage creating tstsf and tstdf insns. */ | |
1514 | if (outer_code == COMPARE | |
1515 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
1516 | *total = 4; | |
1517 | else | |
1518 | *total = 5; | |
1519 | return true; | |
1520 | ||
1521 | /* These are vaguely right for a 68020. */ | |
1522 | /* The costs for long multiply have been adjusted to work properly | |
1523 | in synth_mult on the 68020, relative to an average of the time | |
1524 | for add and the time for shift, taking away a little more because | |
1525 | sometimes move insns are needed. */ | |
1526 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ | |
eb849993 BI |
1527 | #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13) |
1528 | #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \ | |
1529 | TARGET_CFV3 ? 2 : 5) | |
1530 | #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12) | |
3c50106f RH |
1531 | |
1532 | case PLUS: | |
1533 | /* An lea costs about three times as much as a simple add. */ | |
1534 | if (GET_MODE (x) == SImode | |
1535 | && GET_CODE (XEXP (x, 1)) == REG | |
1536 | && GET_CODE (XEXP (x, 0)) == MULT | |
1537 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1538 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1539 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
1540 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
1541 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
1542 | { |
1543 | /* lea an@(dx:l:i),am */ | |
1544 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
1545 | return true; | |
1546 | } | |
3c50106f RH |
1547 | return false; |
1548 | ||
1549 | case ASHIFT: | |
1550 | case ASHIFTRT: | |
1551 | case LSHIFTRT: | |
1552 | if (TARGET_68060) | |
1553 | { | |
1554 | *total = COSTS_N_INSNS(1); | |
1555 | return true; | |
1556 | } | |
eb849993 | 1557 | if (! TARGET_68020 && ! TARGET_COLDFIRE) |
3c50106f RH |
1558 | { |
1559 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1560 | { | |
1561 | if (INTVAL (XEXP (x, 1)) < 16) | |
1562 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
1563 | else | |
1564 | /* We're using clrw + swap for these cases. */ | |
1565 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
1566 | } | |
1567 | else | |
1568 | *total = COSTS_N_INSNS (10); /* worst case */ | |
1569 | return true; | |
1570 | } | |
1571 | /* A shift by a big integer takes an extra instruction. */ | |
1572 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1573 | && (INTVAL (XEXP (x, 1)) == 16)) | |
1574 | { | |
1575 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
1576 | return true; | |
1577 | } | |
1578 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1579 | && !(INTVAL (XEXP (x, 1)) > 0 | |
1580 | && INTVAL (XEXP (x, 1)) <= 8)) | |
1581 | { | |
eb849993 | 1582 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
1583 | return true; |
1584 | } | |
1585 | return false; | |
1586 | ||
1587 | case MULT: | |
1588 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
1589 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
1590 | && GET_MODE (x) == SImode) | |
1591 | *total = COSTS_N_INSNS (MULW_COST); | |
1592 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1593 | *total = COSTS_N_INSNS (MULW_COST); | |
1594 | else | |
1595 | *total = COSTS_N_INSNS (MULL_COST); | |
1596 | return true; | |
1597 | ||
1598 | case DIV: | |
1599 | case UDIV: | |
1600 | case MOD: | |
1601 | case UMOD: | |
1602 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1603 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
1604 | else if (TARGET_CF_HWDIV) |
1605 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
1606 | else |
1607 | *total = COSTS_N_INSNS (43); /* div.l */ | |
1608 | return true; | |
1609 | ||
1610 | default: | |
1611 | return false; | |
1612 | } | |
1613 | } | |
1614 | ||
5505f548 | 1615 | const char * |
8a4a2253 | 1616 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb RK |
1617 | { |
1618 | int i; | |
1619 | ||
1620 | i = INTVAL (operands[1]); | |
1621 | switch (const_method (operands[1])) | |
1622 | { | |
28bad6d1 PB |
1623 | case MVZ: |
1624 | return "mvsw %1,%0"; | |
1625 | case MVS: | |
1626 | return "mvzw %1,%0"; | |
0ce6f9fb | 1627 | case MOVQ : |
0ce6f9fb | 1628 | return "moveq %1,%0"; |
0ce6f9fb | 1629 | case NOTB : |
66e07510 | 1630 | CC_STATUS_INIT; |
1d8eaa6b | 1631 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 1632 | return "moveq %1,%0\n\tnot%.b %0"; |
0ce6f9fb | 1633 | case NOTW : |
66e07510 | 1634 | CC_STATUS_INIT; |
1d8eaa6b | 1635 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 1636 | return "moveq %1,%0\n\tnot%.w %0"; |
0ce6f9fb | 1637 | case NEGW : |
66e07510 | 1638 | CC_STATUS_INIT; |
3b4b85c9 | 1639 | return "moveq #-128,%0\n\tneg%.w %0"; |
0ce6f9fb RK |
1640 | case SWAP : |
1641 | { | |
1642 | unsigned u = i; | |
1643 | ||
1d8eaa6b | 1644 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 1645 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb RK |
1646 | } |
1647 | case MOVL : | |
1648 | return "move%.l %1,%0"; | |
1649 | default : | |
1650 | abort (); | |
1651 | } | |
1652 | } | |
1653 | ||
5505f548 | 1654 | const char * |
8a4a2253 | 1655 | output_move_simode_const (rtx *operands) |
02ed0c07 RK |
1656 | { |
1657 | if (operands[1] == const0_rtx | |
1658 | && (DATA_REG_P (operands[0]) | |
1659 | || GET_CODE (operands[0]) == MEM) | |
1660 | /* clr insns on 68000 read before writing. | |
c67ddce5 | 1661 | This isn't so on the 68010, but we have no TARGET_68010. */ |
9425fb04 | 1662 | && ((TARGET_68020 || TARGET_COLDFIRE) |
02ed0c07 RK |
1663 | || !(GET_CODE (operands[0]) == MEM |
1664 | && MEM_VOLATILE_P (operands[0])))) | |
1665 | return "clr%.l %0"; | |
38198304 AS |
1666 | else if (operands[1] == const0_rtx |
1667 | && ADDRESS_REG_P (operands[0])) | |
1668 | return "sub%.l %0,%0"; | |
02ed0c07 RK |
1669 | else if (DATA_REG_P (operands[0])) |
1670 | return output_move_const_into_data_reg (operands); | |
1671 | else if (ADDRESS_REG_P (operands[0]) | |
1672 | && INTVAL (operands[1]) < 0x8000 | |
1673 | && INTVAL (operands[1]) >= -0x8000) | |
1674 | return "move%.w %1,%0"; | |
1675 | else if (GET_CODE (operands[0]) == MEM | |
1676 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
1677 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
1678 | && INTVAL (operands[1]) < 0x8000 | |
1679 | && INTVAL (operands[1]) >= -0x8000) | |
1680 | return "pea %a1"; | |
1681 | return "move%.l %1,%0"; | |
1682 | } | |
1683 | ||
5505f548 | 1684 | const char * |
8a4a2253 | 1685 | output_move_simode (rtx *operands) |
f4e80198 RK |
1686 | { |
1687 | if (GET_CODE (operands[1]) == CONST_INT) | |
1688 | return output_move_simode_const (operands); | |
1689 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
1690 | || GET_CODE (operands[1]) == CONST) | |
1691 | && push_operand (operands[0], SImode)) | |
1692 | return "pea %a1"; | |
1693 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
1694 | || GET_CODE (operands[1]) == CONST) | |
1695 | && ADDRESS_REG_P (operands[0])) | |
1696 | return "lea %a1,%0"; | |
1697 | return "move%.l %1,%0"; | |
1698 | } | |
1699 | ||
5505f548 | 1700 | const char * |
8a4a2253 | 1701 | output_move_himode (rtx *operands) |
f4e80198 RK |
1702 | { |
1703 | if (GET_CODE (operands[1]) == CONST_INT) | |
1704 | { | |
1705 | if (operands[1] == const0_rtx | |
1706 | && (DATA_REG_P (operands[0]) | |
1707 | || GET_CODE (operands[0]) == MEM) | |
1708 | /* clr insns on 68000 read before writing. | |
1709 | This isn't so on the 68010, but we have no TARGET_68010. */ | |
9425fb04 | 1710 | && ((TARGET_68020 || TARGET_COLDFIRE) |
f4e80198 RK |
1711 | || !(GET_CODE (operands[0]) == MEM |
1712 | && MEM_VOLATILE_P (operands[0])))) | |
1713 | return "clr%.w %0"; | |
38198304 AS |
1714 | else if (operands[1] == const0_rtx |
1715 | && ADDRESS_REG_P (operands[0])) | |
1716 | return "sub%.l %0,%0"; | |
f4e80198 RK |
1717 | else if (DATA_REG_P (operands[0]) |
1718 | && INTVAL (operands[1]) < 128 | |
1719 | && INTVAL (operands[1]) >= -128) | |
1720 | { | |
f4e80198 | 1721 | return "moveq %1,%0"; |
f4e80198 RK |
1722 | } |
1723 | else if (INTVAL (operands[1]) < 0x8000 | |
1724 | && INTVAL (operands[1]) >= -0x8000) | |
1725 | return "move%.w %1,%0"; | |
1726 | } | |
1727 | else if (CONSTANT_P (operands[1])) | |
1728 | return "move%.l %1,%0"; | |
f4e80198 RK |
1729 | /* Recognize the insn before a tablejump, one that refers |
1730 | to a table of offsets. Such an insn will need to refer | |
1731 | to a label on the insn. So output one. Use the label-number | |
1732 | of the table of offsets to generate this label. This code, | |
1733 | and similar code below, assumes that there will be at most one | |
1734 | reference to each table. */ | |
1735 | if (GET_CODE (operands[1]) == MEM | |
1736 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1737 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
1738 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
1739 | { | |
1740 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
1741 | if (MOTOROLA) |
1742 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
1743 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
1744 | else | |
1745 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
1746 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
f4e80198 | 1747 | } |
f4e80198 RK |
1748 | return "move%.w %1,%0"; |
1749 | } | |
1750 | ||
5505f548 | 1751 | const char * |
8a4a2253 | 1752 | output_move_qimode (rtx *operands) |
f4e80198 RK |
1753 | { |
1754 | rtx xoperands[4]; | |
1755 | ||
1756 | /* This is probably useless, since it loses for pushing a struct | |
1757 | of several bytes a byte at a time. */ | |
102701ff | 1758 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 1759 | byte pushes. The 5200 (ColdFire) does not do this. */ |
f4e80198 RK |
1760 | if (GET_CODE (operands[0]) == MEM |
1761 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
1762 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
102701ff | 1763 | && ! ADDRESS_REG_P (operands[1]) |
9425fb04 | 1764 | && ! TARGET_COLDFIRE) |
f4e80198 RK |
1765 | { |
1766 | xoperands[1] = operands[1]; | |
1767 | xoperands[2] | |
1d8eaa6b AS |
1768 | = gen_rtx_MEM (QImode, |
1769 | gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx)); | |
f4e80198 RK |
1770 | /* Just pushing a byte puts it in the high byte of the halfword. */ |
1771 | /* We must put it in the low-order, high-numbered byte. */ | |
3879920c RK |
1772 | if (!reg_mentioned_p (stack_pointer_rtx, operands[1])) |
1773 | { | |
1774 | xoperands[3] = stack_pointer_rtx; | |
3b4b85c9 | 1775 | output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands); |
3879920c RK |
1776 | } |
1777 | else | |
1778 | output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands); | |
f4e80198 RK |
1779 | return ""; |
1780 | } | |
1781 | ||
1782 | /* clr and st insns on 68000 read before writing. | |
1783 | This isn't so on the 68010, but we have no TARGET_68010. */ | |
1784 | if (!ADDRESS_REG_P (operands[0]) | |
9425fb04 | 1785 | && ((TARGET_68020 || TARGET_COLDFIRE) |
f4e80198 RK |
1786 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
1787 | { | |
1788 | if (operands[1] == const0_rtx) | |
1789 | return "clr%.b %0"; | |
9425fb04 | 1790 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
1791 | && GET_CODE (operands[1]) == CONST_INT |
1792 | && (INTVAL (operands[1]) & 255) == 255) | |
1793 | { | |
1794 | CC_STATUS_INIT; | |
1795 | return "st %0"; | |
1796 | } | |
1797 | } | |
1798 | if (GET_CODE (operands[1]) == CONST_INT | |
1799 | && DATA_REG_P (operands[0]) | |
1800 | && INTVAL (operands[1]) < 128 | |
1801 | && INTVAL (operands[1]) >= -128) | |
1802 | { | |
f4e80198 | 1803 | return "moveq %1,%0"; |
f4e80198 | 1804 | } |
38198304 AS |
1805 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
1806 | return "sub%.l %0,%0"; | |
f4e80198 RK |
1807 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
1808 | return "move%.l %1,%0"; | |
c16eadc7 | 1809 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
1810 | from address registers. */ |
1811 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
1812 | return "move%.w %1,%0"; |
1813 | return "move%.b %1,%0"; | |
1814 | } | |
1815 | ||
5505f548 | 1816 | const char * |
8a4a2253 | 1817 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
1818 | { |
1819 | if (operands[1] == const0_rtx | |
1820 | /* clr insns on 68000 read before writing. | |
1821 | This isn't so on the 68010, but we have no TARGET_68010. */ | |
9425fb04 | 1822 | && ((TARGET_68020 || TARGET_COLDFIRE) |
9b55bf04 RK |
1823 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
1824 | return "clr%.w %0"; | |
1825 | return "move%.w %1,%0"; | |
1826 | } | |
1827 | ||
5505f548 | 1828 | const char * |
8a4a2253 | 1829 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
1830 | { |
1831 | if (operands[1] == const0_rtx | |
1832 | /* clr insns on 68000 read before writing. | |
1833 | This isn't so on the 68010, but we have no TARGET_68010. */ | |
9425fb04 | 1834 | && ((TARGET_68020 || TARGET_COLDFIRE) |
9b55bf04 RK |
1835 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
1836 | return "clr%.b %0"; | |
1837 | return "move%.b %1,%0"; | |
1838 | } | |
1839 | ||
79e68feb RS |
1840 | /* Return the best assembler insn template |
1841 | for moving operands[1] into operands[0] as a fullword. */ | |
1842 | ||
5505f548 | 1843 | static const char * |
8a4a2253 | 1844 | singlemove_string (rtx *operands) |
79e68feb | 1845 | { |
02ed0c07 RK |
1846 | if (GET_CODE (operands[1]) == CONST_INT) |
1847 | return output_move_simode_const (operands); | |
1848 | return "move%.l %1,%0"; | |
79e68feb RS |
1849 | } |
1850 | ||
2505bc97 | 1851 | |
79e68feb RS |
1852 | /* Output assembler code to perform a doubleword move insn |
1853 | with operands OPERANDS. */ | |
1854 | ||
5505f548 | 1855 | const char * |
8a4a2253 | 1856 | output_move_double (rtx *operands) |
79e68feb | 1857 | { |
2505bc97 RS |
1858 | enum |
1859 | { | |
1860 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
1861 | } optype0, optype1; | |
79e68feb | 1862 | rtx latehalf[2]; |
2505bc97 | 1863 | rtx middlehalf[2]; |
7f98eeb6 | 1864 | rtx xops[2]; |
79e68feb | 1865 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 1866 | int dest_overlapped_low = 0; |
184916bc | 1867 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
1868 | |
1869 | middlehalf[0] = 0; | |
1870 | middlehalf[1] = 0; | |
79e68feb RS |
1871 | |
1872 | /* First classify both operands. */ | |
1873 | ||
1874 | if (REG_P (operands[0])) | |
1875 | optype0 = REGOP; | |
1876 | else if (offsettable_memref_p (operands[0])) | |
1877 | optype0 = OFFSOP; | |
1878 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
1879 | optype0 = POPOP; | |
1880 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
1881 | optype0 = PUSHOP; | |
1882 | else if (GET_CODE (operands[0]) == MEM) | |
1883 | optype0 = MEMOP; | |
1884 | else | |
1885 | optype0 = RNDOP; | |
1886 | ||
1887 | if (REG_P (operands[1])) | |
1888 | optype1 = REGOP; | |
1889 | else if (CONSTANT_P (operands[1])) | |
1890 | optype1 = CNSTOP; | |
1891 | else if (offsettable_memref_p (operands[1])) | |
1892 | optype1 = OFFSOP; | |
1893 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
1894 | optype1 = POPOP; | |
1895 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
1896 | optype1 = PUSHOP; | |
1897 | else if (GET_CODE (operands[1]) == MEM) | |
1898 | optype1 = MEMOP; | |
1899 | else | |
1900 | optype1 = RNDOP; | |
1901 | ||
1902 | /* Check for the cases that the operand constraints are not | |
1903 | supposed to allow to happen. Abort if we get one, | |
1904 | because generating code for these cases is painful. */ | |
1905 | ||
1906 | if (optype0 == RNDOP || optype1 == RNDOP) | |
1907 | abort (); | |
1908 | ||
1909 | /* If one operand is decrementing and one is incrementing | |
1910 | decrement the former register explicitly | |
1911 | and change that operand into ordinary indexing. */ | |
1912 | ||
1913 | if (optype0 == PUSHOP && optype1 == POPOP) | |
1914 | { | |
1915 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 1916 | if (size == 12) |
3b4b85c9 | 1917 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 1918 | else |
3b4b85c9 | 1919 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 1920 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 1921 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 1922 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 1923 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 1924 | else |
1d8eaa6b | 1925 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
1926 | optype0 = OFFSOP; |
1927 | } | |
1928 | if (optype0 == POPOP && optype1 == PUSHOP) | |
1929 | { | |
1930 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 1931 | if (size == 12) |
3b4b85c9 | 1932 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 1933 | else |
3b4b85c9 | 1934 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 1935 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 1936 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 1937 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 1938 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 1939 | else |
1d8eaa6b | 1940 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
1941 | optype1 = OFFSOP; |
1942 | } | |
1943 | ||
1944 | /* If an operand is an unoffsettable memory ref, find a register | |
1945 | we can increment temporarily to make it refer to the second word. */ | |
1946 | ||
1947 | if (optype0 == MEMOP) | |
1948 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
1949 | ||
1950 | if (optype1 == MEMOP) | |
1951 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
1952 | ||
1953 | /* Ok, we can do one word at a time. | |
1954 | Normally we do the low-numbered word first, | |
1955 | but if either operand is autodecrementing then we | |
1956 | do the high-numbered word first. | |
1957 | ||
1958 | In either case, set up in LATEHALF the operands to use | |
1959 | for the high-numbered word and in some cases alter the | |
1960 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
1961 | ||
2505bc97 RS |
1962 | if (size == 12) |
1963 | { | |
1964 | if (optype0 == REGOP) | |
1965 | { | |
1d8eaa6b AS |
1966 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
1967 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
1968 | } |
1969 | else if (optype0 == OFFSOP) | |
1970 | { | |
b72f00af RK |
1971 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
1972 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
1973 | } |
1974 | else | |
1975 | { | |
1976 | middlehalf[0] = operands[0]; | |
1977 | latehalf[0] = operands[0]; | |
1978 | } | |
1979 | ||
1980 | if (optype1 == REGOP) | |
1981 | { | |
1d8eaa6b AS |
1982 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
1983 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
1984 | } |
1985 | else if (optype1 == OFFSOP) | |
1986 | { | |
b72f00af RK |
1987 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
1988 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
1989 | } |
1990 | else if (optype1 == CNSTOP) | |
1991 | { | |
1992 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1993 | { | |
1994 | REAL_VALUE_TYPE r; | |
1995 | long l[3]; | |
1996 | ||
1997 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
1998 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
1999 | operands[1] = GEN_INT (l[0]); | |
2000 | middlehalf[1] = GEN_INT (l[1]); | |
2001 | latehalf[1] = GEN_INT (l[2]); | |
2002 | } | |
2003 | else if (CONSTANT_P (operands[1])) | |
2004 | { | |
2005 | /* actually, no non-CONST_DOUBLE constant should ever | |
2006 | appear here. */ | |
2007 | abort (); | |
2008 | if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) | |
2009 | latehalf[1] = constm1_rtx; | |
2010 | else | |
2011 | latehalf[1] = const0_rtx; | |
2012 | } | |
2013 | } | |
2014 | else | |
2015 | { | |
2016 | middlehalf[1] = operands[1]; | |
2017 | latehalf[1] = operands[1]; | |
2018 | } | |
2019 | } | |
79e68feb | 2020 | else |
2505bc97 RS |
2021 | /* size is not 12: */ |
2022 | { | |
2023 | if (optype0 == REGOP) | |
1d8eaa6b | 2024 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2025 | else if (optype0 == OFFSOP) |
b72f00af | 2026 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2027 | else |
2028 | latehalf[0] = operands[0]; | |
2029 | ||
2030 | if (optype1 == REGOP) | |
1d8eaa6b | 2031 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2032 | else if (optype1 == OFFSOP) |
b72f00af | 2033 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2034 | else if (optype1 == CNSTOP) |
2035 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2036 | else | |
2037 | latehalf[1] = operands[1]; | |
2038 | } | |
79e68feb RS |
2039 | |
2040 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2041 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2042 | for the low word as well, to compensate for the first decrement of sp. */ | |
2043 | if (optype0 == PUSHOP | |
2044 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2045 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2046 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2047 | |
7f98eeb6 RS |
2048 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2049 | if the upper part of reg N does not appear in the MEM, arrange to | |
2050 | emit the move late-half first. Otherwise, compute the MEM address | |
2051 | into the upper part of N and use that as a pointer to the memory | |
2052 | operand. */ | |
2053 | if (optype0 == REGOP | |
2054 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2055 | { | |
1d8eaa6b | 2056 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2057 | |
2058 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2059 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2060 | { |
2061 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2062 | compute the address into latehalf of dest. |
2063 | Note that this can't happen if the dest is two data regs. */ | |
7f98eeb6 RS |
2064 | compadr: |
2065 | xops[0] = latehalf[0]; | |
2066 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2067 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2068 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2069 | { |
1d8eaa6b | 2070 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2071 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2072 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2073 | } |
2074 | else | |
2075 | { | |
1d8eaa6b | 2076 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2077 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2078 | } |
2079 | } | |
2080 | else if (size == 12 | |
d7e8d581 RS |
2081 | && reg_overlap_mentioned_p (middlehalf[0], |
2082 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2083 | { |
3a58400f RS |
2084 | /* Check for two regs used by both source and dest. |
2085 | Note that this can't happen if the dest is all data regs. | |
2086 | It can happen if the dest is d6, d7, a0. | |
2087 | But in that case, latehalf is an addr reg, so | |
2088 | the code at compadr does ok. */ | |
2089 | ||
2090 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2091 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2092 | goto compadr; | |
7f98eeb6 RS |
2093 | |
2094 | /* JRV says this can't happen: */ | |
2095 | if (addreg0 || addreg1) | |
d7e8d581 | 2096 | abort (); |
7f98eeb6 | 2097 | |
7a1929e1 | 2098 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2099 | output_asm_insn (singlemove_string (operands), operands); |
2100 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2101 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2102 | return ""; | |
2103 | } | |
2fb8a81d | 2104 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2105 | /* If the low half of dest is mentioned in the source memory |
2106 | address, the arrange to emit the move late half first. */ | |
2107 | dest_overlapped_low = 1; | |
2108 | } | |
2109 | ||
79e68feb RS |
2110 | /* If one or both operands autodecrementing, |
2111 | do the two words, high-numbered first. */ | |
2112 | ||
2113 | /* Likewise, the first move would clobber the source of the second one, | |
2114 | do them in the other order. This happens only for registers; | |
2115 | such overlap can't happen in memory unless the user explicitly | |
2116 | sets it up, and that is an undefined circumstance. */ | |
2117 | ||
2118 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2119 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2120 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2121 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2122 | || dest_overlapped_low) | |
79e68feb RS |
2123 | { |
2124 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2125 | if (addreg0) | |
2505bc97 RS |
2126 | { |
2127 | if (size == 12) | |
3b4b85c9 | 2128 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2129 | else |
3b4b85c9 | 2130 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2131 | } |
79e68feb | 2132 | if (addreg1) |
2505bc97 RS |
2133 | { |
2134 | if (size == 12) | |
3b4b85c9 | 2135 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2136 | else |
3b4b85c9 | 2137 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2138 | } |
79e68feb RS |
2139 | |
2140 | /* Do that word. */ | |
2141 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2142 | ||
2143 | /* Undo the adds we just did. */ | |
2144 | if (addreg0) | |
3b4b85c9 | 2145 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2146 | if (addreg1) |
3b4b85c9 | 2147 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2148 | |
2505bc97 RS |
2149 | if (size == 12) |
2150 | { | |
2151 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2152 | if (addreg0) | |
3b4b85c9 | 2153 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2154 | if (addreg1) |
3b4b85c9 | 2155 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2156 | } |
2157 | ||
79e68feb RS |
2158 | /* Do low-numbered word. */ |
2159 | return singlemove_string (operands); | |
2160 | } | |
2161 | ||
2162 | /* Normal case: do the two words, low-numbered first. */ | |
2163 | ||
2164 | output_asm_insn (singlemove_string (operands), operands); | |
2165 | ||
2505bc97 RS |
2166 | /* Do the middle one of the three words for long double */ |
2167 | if (size == 12) | |
2168 | { | |
2169 | if (addreg0) | |
3b4b85c9 | 2170 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2171 | if (addreg1) |
3b4b85c9 | 2172 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2173 | |
2174 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2175 | } | |
2176 | ||
79e68feb RS |
2177 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2178 | if (addreg0) | |
3b4b85c9 | 2179 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2180 | if (addreg1) |
3b4b85c9 | 2181 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2182 | |
2183 | /* Do that word. */ | |
2184 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2185 | ||
2186 | /* Undo the adds we just did. */ | |
2187 | if (addreg0) | |
2505bc97 RS |
2188 | { |
2189 | if (size == 12) | |
3b4b85c9 | 2190 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2191 | else |
3b4b85c9 | 2192 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2193 | } |
79e68feb | 2194 | if (addreg1) |
2505bc97 RS |
2195 | { |
2196 | if (size == 12) | |
3b4b85c9 | 2197 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2198 | else |
3b4b85c9 | 2199 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2200 | } |
79e68feb RS |
2201 | |
2202 | return ""; | |
2203 | } | |
2204 | ||
2205 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2206 | ADDR can be effectively incremented by incrementing REG. */ | |
2207 | ||
2208 | static rtx | |
8a4a2253 | 2209 | find_addr_reg (rtx addr) |
79e68feb RS |
2210 | { |
2211 | while (GET_CODE (addr) == PLUS) | |
2212 | { | |
2213 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2214 | addr = XEXP (addr, 0); | |
2215 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2216 | addr = XEXP (addr, 1); | |
2217 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2218 | addr = XEXP (addr, 1); | |
2219 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2220 | addr = XEXP (addr, 0); | |
2221 | else | |
2222 | abort (); | |
2223 | } | |
2224 | if (GET_CODE (addr) == REG) | |
2225 | return addr; | |
2226 | abort (); | |
2227 | } | |
9ee3c687 | 2228 | |
c16eadc7 | 2229 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 2230 | |
5505f548 | 2231 | const char * |
8a4a2253 | 2232 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
2233 | { |
2234 | if (! operands_match_p (operands[0], operands[1])) | |
2235 | { | |
2236 | if (!ADDRESS_REG_P (operands[1])) | |
2237 | { | |
2238 | rtx tmp = operands[1]; | |
2239 | ||
2240 | operands[1] = operands[2]; | |
2241 | operands[2] = tmp; | |
2242 | } | |
2243 | ||
2244 | /* These insns can result from reloads to access | |
2245 | stack slots over 64k from the frame pointer. */ | |
2246 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 2247 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 2248 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 2249 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
2250 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
2251 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
2252 | } |
2253 | if (GET_CODE (operands[2]) == CONST_INT) | |
2254 | { | |
9ee3c687 JW |
2255 | if (INTVAL (operands[2]) > 0 |
2256 | && INTVAL (operands[2]) <= 8) | |
2257 | return "addq%.l %2,%0"; | |
2258 | if (INTVAL (operands[2]) < 0 | |
2259 | && INTVAL (operands[2]) >= -8) | |
2260 | { | |
c5c76735 | 2261 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
2262 | return "subq%.l %2,%0"; |
2263 | } | |
2264 | /* On the CPU32 it is faster to use two addql instructions to | |
2265 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 2266 | Likewise for subql. */ |
9ee3c687 JW |
2267 | if (TARGET_CPU32 && REG_P (operands[0])) |
2268 | { | |
2269 | if (INTVAL (operands[2]) > 8 | |
2270 | && INTVAL (operands[2]) <= 16) | |
2271 | { | |
1d8eaa6b | 2272 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 2273 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
2274 | } |
2275 | if (INTVAL (operands[2]) < -8 | |
2276 | && INTVAL (operands[2]) >= -16) | |
2277 | { | |
c5c76735 | 2278 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 2279 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
2280 | } |
2281 | } | |
9ee3c687 JW |
2282 | if (ADDRESS_REG_P (operands[0]) |
2283 | && INTVAL (operands[2]) >= -0x8000 | |
2284 | && INTVAL (operands[2]) < 0x8000) | |
2285 | { | |
2286 | if (TARGET_68040) | |
2287 | return "add%.w %2,%0"; | |
2288 | else | |
e6d98cb0 | 2289 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
2290 | } |
2291 | } | |
2292 | return "add%.l %2,%0"; | |
2293 | } | |
79e68feb RS |
2294 | \f |
2295 | /* Store in cc_status the expressions that the condition codes will | |
2296 | describe after execution of an instruction whose pattern is EXP. | |
2297 | Do not alter them if the instruction would not alter the cc's. */ | |
2298 | ||
2299 | /* On the 68000, all the insns to store in an address register fail to | |
2300 | set the cc's. However, in some cases these instructions can make it | |
2301 | possibly invalid to use the saved cc's. In those cases we clear out | |
2302 | some or all of the saved cc's so they won't be used. */ | |
2303 | ||
1d8eaa6b | 2304 | void |
8a4a2253 | 2305 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 2306 | { |
1a8965c4 | 2307 | if (GET_CODE (exp) == SET) |
79e68feb RS |
2308 | { |
2309 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
2310 | { | |
2311 | CC_STATUS_INIT; | |
2312 | } | |
2313 | else if (ADDRESS_REG_P (SET_DEST (exp))) | |
2314 | { | |
f5963e61 | 2315 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 2316 | cc_status.value1 = 0; |
f5963e61 | 2317 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
2318 | cc_status.value2 = 0; |
2319 | } | |
2320 | else if (!FP_REG_P (SET_DEST (exp)) | |
2321 | && SET_DEST (exp) != cc0_rtx | |
2322 | && (FP_REG_P (SET_SRC (exp)) | |
2323 | || GET_CODE (SET_SRC (exp)) == FIX | |
2324 | || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE | |
2325 | || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND)) | |
2326 | { | |
2327 | CC_STATUS_INIT; | |
2328 | } | |
2329 | /* A pair of move insns doesn't produce a useful overall cc. */ | |
2330 | else if (!FP_REG_P (SET_DEST (exp)) | |
2331 | && !FP_REG_P (SET_SRC (exp)) | |
2332 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
2333 | && (GET_CODE (SET_SRC (exp)) == REG | |
2334 | || GET_CODE (SET_SRC (exp)) == MEM | |
2335 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
2336 | { | |
2337 | CC_STATUS_INIT; | |
2338 | } | |
2339 | else if (GET_CODE (SET_SRC (exp)) == CALL) | |
2340 | { | |
2341 | CC_STATUS_INIT; | |
2342 | } | |
2343 | else if (XEXP (exp, 0) != pc_rtx) | |
2344 | { | |
2345 | cc_status.flags = 0; | |
2346 | cc_status.value1 = XEXP (exp, 0); | |
2347 | cc_status.value2 = XEXP (exp, 1); | |
2348 | } | |
2349 | } | |
2350 | else if (GET_CODE (exp) == PARALLEL | |
2351 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
2352 | { | |
2353 | if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0))) | |
2354 | CC_STATUS_INIT; | |
2355 | else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx) | |
2356 | { | |
2357 | cc_status.flags = 0; | |
2358 | cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); | |
2359 | cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1); | |
2360 | } | |
2361 | } | |
2362 | else | |
2363 | CC_STATUS_INIT; | |
2364 | if (cc_status.value2 != 0 | |
2365 | && ADDRESS_REG_P (cc_status.value2) | |
2366 | && GET_MODE (cc_status.value2) == QImode) | |
2367 | CC_STATUS_INIT; | |
1a8965c4 | 2368 | if (cc_status.value2 != 0) |
79e68feb RS |
2369 | switch (GET_CODE (cc_status.value2)) |
2370 | { | |
996a5f59 | 2371 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 2372 | case ROTATE: case ROTATERT: |
a126dc3a RH |
2373 | /* These instructions always clear the overflow bit, and set |
2374 | the carry to the bit shifted out. */ | |
2375 | /* ??? We don't currently have a way to signal carry not valid, | |
2376 | nor do we check for it in the branch insns. */ | |
2377 | CC_STATUS_INIT; | |
2378 | break; | |
2379 | ||
2380 | case PLUS: case MINUS: case MULT: | |
2381 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
2382 | if (GET_MODE (cc_status.value2) != VOIDmode) |
2383 | cc_status.flags |= CC_NO_OVERFLOW; | |
2384 | break; | |
2385 | case ZERO_EXTEND: | |
2386 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
2387 | ends with a move insn moving r2 in r2's mode. | |
2388 | Thus, the cc's are set for r2. | |
7a1929e1 | 2389 | This can set N bit spuriously. */ |
79e68feb | 2390 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
2391 | |
2392 | default: | |
2393 | break; | |
79e68feb RS |
2394 | } |
2395 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
2396 | && cc_status.value2 | |
2397 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
2398 | cc_status.value2 = 0; | |
2399 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 2400 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
2401 | cc_status.flags = CC_IN_68881; |
2402 | } | |
2403 | \f | |
5505f548 | 2404 | const char * |
8a4a2253 | 2405 | output_move_const_double (rtx *operands) |
79e68feb | 2406 | { |
1a8965c4 | 2407 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2408 | |
1a8965c4 | 2409 | if (code != 0) |
79e68feb | 2410 | { |
1a8965c4 | 2411 | static char buf[40]; |
79e68feb | 2412 | |
3b4b85c9 | 2413 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2414 | return buf; |
79e68feb | 2415 | } |
1a8965c4 | 2416 | return "fmove%.d %1,%0"; |
79e68feb RS |
2417 | } |
2418 | ||
5505f548 | 2419 | const char * |
8a4a2253 | 2420 | output_move_const_single (rtx *operands) |
79e68feb | 2421 | { |
1a8965c4 | 2422 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2423 | |
1a8965c4 | 2424 | if (code != 0) |
79e68feb | 2425 | { |
1a8965c4 | 2426 | static char buf[40]; |
79e68feb | 2427 | |
3b4b85c9 | 2428 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2429 | return buf; |
79e68feb | 2430 | } |
1a8965c4 | 2431 | return "fmove%.s %f1,%0"; |
79e68feb RS |
2432 | } |
2433 | ||
2434 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
2435 | from the "fmovecr" instruction. | |
2436 | The value, anded with 0xff, gives the code to use in fmovecr | |
2437 | to get the desired constant. */ | |
2438 | ||
7a1929e1 | 2439 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
2440 | |
2441 | static int inited_68881_table = 0; | |
2442 | ||
5505f548 | 2443 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
2444 | "0.0", |
2445 | "1.0", | |
2446 | "10.0", | |
2447 | "100.0", | |
2448 | "10000.0", | |
2449 | "1e8", | |
2450 | "1e16" | |
2451 | }; | |
2452 | ||
8b60264b | 2453 | static const int codes_68881[7] = { |
c1cfb2ae RS |
2454 | 0x0f, |
2455 | 0x32, | |
2456 | 0x33, | |
2457 | 0x34, | |
2458 | 0x35, | |
2459 | 0x36, | |
2460 | 0x37 | |
2461 | }; | |
2462 | ||
2463 | REAL_VALUE_TYPE values_68881[7]; | |
2464 | ||
2465 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 2466 | strings_68881 to binary. */ |
c1cfb2ae RS |
2467 | |
2468 | void | |
8a4a2253 | 2469 | init_68881_table (void) |
c1cfb2ae RS |
2470 | { |
2471 | int i; | |
2472 | REAL_VALUE_TYPE r; | |
2473 | enum machine_mode mode; | |
2474 | ||
16d82c3c | 2475 | mode = SFmode; |
c1cfb2ae RS |
2476 | for (i = 0; i < 7; i++) |
2477 | { | |
2478 | if (i == 6) | |
16d82c3c | 2479 | mode = DFmode; |
c1cfb2ae RS |
2480 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
2481 | values_68881[i] = r; | |
2482 | } | |
2483 | inited_68881_table = 1; | |
2484 | } | |
79e68feb RS |
2485 | |
2486 | int | |
8a4a2253 | 2487 | standard_68881_constant_p (rtx x) |
79e68feb | 2488 | { |
c1cfb2ae RS |
2489 | REAL_VALUE_TYPE r; |
2490 | int i; | |
79e68feb | 2491 | |
e18db50d | 2492 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 2493 | used at all on those chips. */ |
e18db50d | 2494 | if (TARGET_68040 || TARGET_68060) |
79e68feb RS |
2495 | return 0; |
2496 | ||
c1cfb2ae RS |
2497 | if (! inited_68881_table) |
2498 | init_68881_table (); | |
2499 | ||
2500 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2501 | ||
64c0b414 AS |
2502 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
2503 | is rejected. */ | |
c1cfb2ae RS |
2504 | for (i = 0; i < 6; i++) |
2505 | { | |
64c0b414 | 2506 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
2507 | return (codes_68881[i]); |
2508 | } | |
2509 | ||
79e68feb RS |
2510 | if (GET_MODE (x) == SFmode) |
2511 | return 0; | |
c1cfb2ae RS |
2512 | |
2513 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
2514 | return (codes_68881[6]); | |
2515 | ||
79e68feb RS |
2516 | /* larger powers of ten in the constants ram are not used |
2517 | because they are not equal to a `double' C constant. */ | |
2518 | return 0; | |
2519 | } | |
2520 | ||
2521 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
2522 | or 0 if X is not a power of 2. */ | |
2523 | ||
2524 | int | |
8a4a2253 | 2525 | floating_exact_log2 (rtx x) |
79e68feb | 2526 | { |
c1cfb2ae | 2527 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 2528 | int exp; |
79e68feb | 2529 | |
c1cfb2ae | 2530 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 2531 | |
eaff3bf8 | 2532 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
2533 | return 0; |
2534 | ||
eaff3bf8 RH |
2535 | exp = real_exponent (&r); |
2536 | real_2expN (&r1, exp); | |
2537 | if (REAL_VALUES_EQUAL (r1, r)) | |
2538 | return exp; | |
2539 | ||
79e68feb RS |
2540 | return 0; |
2541 | } | |
2542 | \f | |
79e68feb RS |
2543 | /* A C compound statement to output to stdio stream STREAM the |
2544 | assembler syntax for an instruction operand X. X is an RTL | |
2545 | expression. | |
2546 | ||
2547 | CODE is a value that can be used to specify one of several ways | |
2548 | of printing the operand. It is used when identical operands | |
2549 | must be printed differently depending on the context. CODE | |
2550 | comes from the `%' specification that was used to request | |
2551 | printing of the operand. If the specification was just `%DIGIT' | |
2552 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
2553 | is the ASCII code for LTR. | |
2554 | ||
2555 | If X is a register, this macro should print the register's name. | |
2556 | The names can be found in an array `reg_names' whose type is | |
2557 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
2558 | ||
2559 | When the machine description has a specification `%PUNCT' (a `%' | |
2560 | followed by a punctuation character), this macro is called with | |
2561 | a null pointer for X and the punctuation character for CODE. | |
2562 | ||
2563 | The m68k specific codes are: | |
2564 | ||
2565 | '.' for dot needed in Motorola-style opcode names. | |
2566 | '-' for an operand pushing on the stack: | |
2567 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
2568 | '+' for an operand pushing on the stack: | |
2569 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
2570 | '@' for a reference to the top word on the stack: | |
2571 | sp@, (sp) or (%sp) depending on the style of syntax. | |
2572 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 2573 | but & in SGS syntax). |
79e68feb RS |
2574 | '!' for the cc register (used in an `and to cc' insn). |
2575 | '$' for the letter `s' in an op code, but only on the 68040. | |
2576 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 2577 | '/' for register prefix needed by longlong.h. |
79e68feb RS |
2578 | |
2579 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
2580 | 'd' to force memory addressing to be absolute, not relative. | |
2581 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
2c8ec431 DL |
2582 | 'o' for operands to go directly to output_operand_address (bypassing |
2583 | print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) | |
79e68feb RS |
2584 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
2585 | or print pair of registers as rx:ry. | |
79e68feb RS |
2586 | |
2587 | */ | |
2588 | ||
2589 | void | |
8a4a2253 | 2590 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 2591 | { |
79e68feb RS |
2592 | if (letter == '.') |
2593 | { | |
e6d98cb0 BI |
2594 | if (MOTOROLA) |
2595 | fprintf (file, "."); | |
79e68feb RS |
2596 | } |
2597 | else if (letter == '#') | |
e6d98cb0 | 2598 | asm_fprintf (file, "%I"); |
79e68feb | 2599 | else if (letter == '-') |
e6d98cb0 | 2600 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 2601 | else if (letter == '+') |
e6d98cb0 | 2602 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 2603 | else if (letter == '@') |
e6d98cb0 | 2604 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 2605 | else if (letter == '!') |
e6d98cb0 | 2606 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
2607 | else if (letter == '$') |
2608 | { | |
2609 | if (TARGET_68040_ONLY) | |
e6d98cb0 | 2610 | fprintf (file, "s"); |
79e68feb RS |
2611 | } |
2612 | else if (letter == '&') | |
2613 | { | |
2614 | if (TARGET_68040_ONLY) | |
e6d98cb0 | 2615 | fprintf (file, "d"); |
79e68feb | 2616 | } |
2ac5f14a | 2617 | else if (letter == '/') |
e6d98cb0 | 2618 | asm_fprintf (file, "%R"); |
2c8ec431 DL |
2619 | else if (letter == 'o') |
2620 | { | |
2621 | /* This is only for direct addresses with TARGET_PCREL */ | |
2622 | if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF | |
01bbf777 | 2623 | || !TARGET_PCREL) |
2c8ec431 DL |
2624 | abort (); |
2625 | output_addr_const (file, XEXP (op, 0)); | |
2626 | } | |
79e68feb RS |
2627 | else if (GET_CODE (op) == REG) |
2628 | { | |
1a8965c4 AS |
2629 | if (letter == 'R') |
2630 | /* Print out the second register name of a register pair. | |
2631 | I.e., R (6) => 7. */ | |
01bbf777 | 2632 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 2633 | else |
01bbf777 | 2634 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
2635 | } |
2636 | else if (GET_CODE (op) == MEM) | |
2637 | { | |
2638 | output_address (XEXP (op, 0)); | |
2639 | if (letter == 'd' && ! TARGET_68020 | |
2640 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
2641 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
2642 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
2643 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 2644 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 2645 | } |
79e68feb RS |
2646 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
2647 | { | |
c1cfb2ae RS |
2648 | REAL_VALUE_TYPE r; |
2649 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
2650 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
2651 | } | |
2652 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
2653 | { | |
2654 | REAL_VALUE_TYPE r; | |
2655 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
2656 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 2657 | } |
e2c0a924 | 2658 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 2659 | { |
c1cfb2ae RS |
2660 | REAL_VALUE_TYPE r; |
2661 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
2662 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
2663 | } |
2664 | else | |
2665 | { | |
2c8ec431 DL |
2666 | /* Use `print_operand_address' instead of `output_addr_const' |
2667 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 2668 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
2669 | if (TARGET_PCREL |
2670 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
2671 | print_operand_address (file, op); | |
2672 | else | |
2673 | output_addr_const (file, op); | |
79e68feb RS |
2674 | } |
2675 | } | |
2676 | ||
2677 | \f | |
2678 | /* A C compound statement to output to stdio stream STREAM the | |
2679 | assembler syntax for an instruction operand that is a memory | |
2680 | reference whose address is ADDR. ADDR is an RTL expression. | |
2681 | ||
2682 | Note that this contains a kludge that knows that the only reason | |
2683 | we have an address (plus (label_ref...) (reg...)) when not generating | |
2684 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
2685 | generates a label LInnn: on such an insn. | |
2686 | ||
2687 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
2688 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
2689 | ||
2690 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
2691 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
2692 | we want. This difference can be accommodated by using an assembler | |
2693 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
2694 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 2695 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
2696 | Some assemblers refuse all the above solutions. The workaround is to |
2697 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 2698 | right behavior. |
79e68feb RS |
2699 | |
2700 | They also do not like things like "pea 1.w", so we simple leave off | |
2701 | the .w on small constants. | |
2702 | ||
2703 | This routine is responsible for distinguishing between -fpic and -fPIC | |
2704 | style relocations in an address. When generating -fpic code the | |
2705 | offset is output in word mode (eg movel a5@(_foo:w), a0). When generating | |
2706 | -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */ | |
2707 | ||
3b4b85c9 | 2708 | #if MOTOROLA |
e6d98cb0 | 2709 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\ |
3b4b85c9 BI |
2710 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname) |
2711 | #else /* !MOTOROLA */ | |
2712 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\ | |
f4a6e73b | 2713 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname) |
3b4b85c9 | 2714 | #endif /* !MOTOROLA */ |
f4a6e73b | 2715 | |
79e68feb | 2716 | void |
8a4a2253 | 2717 | print_operand_address (FILE *file, rtx addr) |
79e68feb RS |
2718 | { |
2719 | register rtx reg1, reg2, breg, ireg; | |
2720 | rtx offset; | |
2721 | ||
2722 | switch (GET_CODE (addr)) | |
2723 | { | |
2724 | case REG: | |
01bbf777 | 2725 | fprintf (file, MOTOROLA ? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr))); |
79e68feb RS |
2726 | break; |
2727 | case PRE_DEC: | |
e6d98cb0 | 2728 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", |
01bbf777 | 2729 | M68K_REGNAME(REGNO (XEXP (addr, 0)))); |
79e68feb RS |
2730 | break; |
2731 | case POST_INC: | |
e6d98cb0 | 2732 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", |
01bbf777 | 2733 | M68K_REGNAME(REGNO (XEXP (addr, 0)))); |
79e68feb RS |
2734 | break; |
2735 | case PLUS: | |
2736 | reg1 = reg2 = ireg = breg = offset = 0; | |
2737 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) | |
2738 | { | |
2739 | offset = XEXP (addr, 0); | |
2740 | addr = XEXP (addr, 1); | |
2741 | } | |
2742 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) | |
2743 | { | |
2744 | offset = XEXP (addr, 1); | |
2745 | addr = XEXP (addr, 0); | |
2746 | } | |
2747 | if (GET_CODE (addr) != PLUS) | |
2748 | { | |
2749 | ; | |
2750 | } | |
2751 | else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) | |
2752 | { | |
2753 | reg1 = XEXP (addr, 0); | |
2754 | addr = XEXP (addr, 1); | |
2755 | } | |
2756 | else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) | |
2757 | { | |
2758 | reg1 = XEXP (addr, 1); | |
2759 | addr = XEXP (addr, 0); | |
2760 | } | |
2761 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
2762 | { | |
2763 | reg1 = XEXP (addr, 0); | |
2764 | addr = XEXP (addr, 1); | |
2765 | } | |
2766 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
2767 | { | |
2768 | reg1 = XEXP (addr, 1); | |
2769 | addr = XEXP (addr, 0); | |
2770 | } | |
2771 | else if (GET_CODE (XEXP (addr, 0)) == REG) | |
2772 | { | |
2773 | reg1 = XEXP (addr, 0); | |
2774 | addr = XEXP (addr, 1); | |
2775 | } | |
2776 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2777 | { | |
2778 | reg1 = XEXP (addr, 1); | |
2779 | addr = XEXP (addr, 0); | |
2780 | } | |
2781 | if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT | |
2782 | || GET_CODE (addr) == SIGN_EXTEND) | |
2783 | { | |
2784 | if (reg1 == 0) | |
2785 | { | |
2786 | reg1 = addr; | |
2787 | } | |
2788 | else | |
2789 | { | |
2790 | reg2 = addr; | |
2791 | } | |
2792 | addr = 0; | |
2793 | } | |
2794 | #if 0 /* for OLD_INDEXING */ | |
2795 | else if (GET_CODE (addr) == PLUS) | |
2796 | { | |
2797 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2798 | { | |
2799 | reg2 = XEXP (addr, 0); | |
2800 | addr = XEXP (addr, 1); | |
2801 | } | |
2802 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2803 | { | |
2804 | reg2 = XEXP (addr, 1); | |
2805 | addr = XEXP (addr, 0); | |
2806 | } | |
2807 | } | |
2808 | #endif | |
2809 | if (offset != 0) | |
2810 | { | |
2811 | if (addr != 0) | |
2812 | { | |
2813 | abort (); | |
2814 | } | |
2815 | addr = offset; | |
2816 | } | |
2817 | if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND | |
2818 | || GET_CODE (reg1) == MULT)) | |
2819 | || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) | |
2820 | { | |
2821 | breg = reg2; | |
2822 | ireg = reg1; | |
2823 | } | |
2824 | else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) | |
2825 | { | |
2826 | breg = reg1; | |
2827 | ireg = reg2; | |
2828 | } | |
2829 | if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF | |
63d415c0 | 2830 | && ! (flag_pic && ireg == pic_offset_table_rtx)) |
79e68feb RS |
2831 | { |
2832 | int scale = 1; | |
2833 | if (GET_CODE (ireg) == MULT) | |
2834 | { | |
2835 | scale = INTVAL (XEXP (ireg, 1)); | |
2836 | ireg = XEXP (ireg, 0); | |
2837 | } | |
2838 | if (GET_CODE (ireg) == SIGN_EXTEND) | |
2839 | { | |
f4a6e73b | 2840 | ASM_OUTPUT_CASE_FETCH (file, |
79e68feb | 2841 | CODE_LABEL_NUMBER (XEXP (addr, 0)), |
01bbf777 | 2842 | M68K_REGNAME(REGNO (XEXP (ireg, 0)))); |
f4a6e73b | 2843 | fprintf (file, "w"); |
79e68feb RS |
2844 | } |
2845 | else | |
2846 | { | |
f4a6e73b | 2847 | ASM_OUTPUT_CASE_FETCH (file, |
79e68feb | 2848 | CODE_LABEL_NUMBER (XEXP (addr, 0)), |
01bbf777 | 2849 | M68K_REGNAME(REGNO (ireg))); |
f4a6e73b | 2850 | fprintf (file, "l"); |
79e68feb RS |
2851 | } |
2852 | if (scale != 1) | |
e6d98cb0 | 2853 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); |
79e68feb RS |
2854 | putc (')', file); |
2855 | break; | |
2856 | } | |
2857 | if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF | |
63d415c0 | 2858 | && ! (flag_pic && breg == pic_offset_table_rtx)) |
79e68feb | 2859 | { |
f4a6e73b | 2860 | ASM_OUTPUT_CASE_FETCH (file, |
79e68feb | 2861 | CODE_LABEL_NUMBER (XEXP (addr, 0)), |
01bbf777 | 2862 | M68K_REGNAME(REGNO (breg))); |
f4a6e73b | 2863 | fprintf (file, "l)"); |
79e68feb RS |
2864 | break; |
2865 | } | |
2866 | if (ireg != 0 || breg != 0) | |
2867 | { | |
2868 | int scale = 1; | |
2869 | if (breg == 0) | |
2870 | { | |
2871 | abort (); | |
2872 | } | |
2873 | if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF) | |
2874 | { | |
2875 | abort (); | |
2876 | } | |
e6d98cb0 | 2877 | if (MOTOROLA) |
79e68feb | 2878 | { |
e6d98cb0 | 2879 | if (addr != 0) |
e9a25f70 | 2880 | { |
e6d98cb0 BI |
2881 | output_addr_const (file, addr); |
2882 | if (flag_pic && (breg == pic_offset_table_rtx)) | |
2883 | { | |
2884 | fprintf (file, "@GOT"); | |
2885 | if (flag_pic == 1) | |
2886 | fprintf (file, ".w"); | |
2887 | } | |
e9a25f70 | 2888 | } |
01bbf777 | 2889 | fprintf (file, "(%s", M68K_REGNAME(REGNO (breg))); |
e6d98cb0 BI |
2890 | if (ireg != 0) |
2891 | putc (',', file); | |
79e68feb | 2892 | } |
e6d98cb0 | 2893 | else /* !MOTOROLA */ |
79e68feb | 2894 | { |
01bbf777 | 2895 | fprintf (file, "%s@(", M68K_REGNAME(REGNO (breg))); |
e6d98cb0 BI |
2896 | if (addr != 0) |
2897 | { | |
2898 | output_addr_const (file, addr); | |
2899 | if (breg == pic_offset_table_rtx) | |
2900 | switch (flag_pic) | |
2901 | { | |
2902 | case 1: | |
2903 | fprintf (file, ":w"); break; | |
2904 | case 2: | |
2905 | fprintf (file, ":l"); break; | |
2906 | default: | |
2907 | break; | |
2908 | } | |
2909 | if (ireg != 0) | |
2910 | putc (',', file); | |
2911 | } | |
2912 | } /* !MOTOROLA */ | |
79e68feb RS |
2913 | if (ireg != 0 && GET_CODE (ireg) == MULT) |
2914 | { | |
2915 | scale = INTVAL (XEXP (ireg, 1)); | |
2916 | ireg = XEXP (ireg, 0); | |
2917 | } | |
2918 | if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) | |
e6d98cb0 | 2919 | fprintf (file, MOTOROLA ? "%s.w" : "%s:w", |
01bbf777 | 2920 | M68K_REGNAME(REGNO (XEXP (ireg, 0)))); |
79e68feb | 2921 | else if (ireg != 0) |
e6d98cb0 | 2922 | fprintf (file, MOTOROLA ? "%s.l" : "%s:l", |
01bbf777 | 2923 | M68K_REGNAME(REGNO (ireg))); |
79e68feb | 2924 | if (scale != 1) |
e6d98cb0 | 2925 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); |
79e68feb RS |
2926 | putc (')', file); |
2927 | break; | |
2928 | } | |
2929 | else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF | |
01bbf777 | 2930 | && ! (flag_pic && reg1 == pic_offset_table_rtx)) |
79e68feb | 2931 | { |
f4a6e73b | 2932 | ASM_OUTPUT_CASE_FETCH (file, |
79e68feb | 2933 | CODE_LABEL_NUMBER (XEXP (addr, 0)), |
01bbf777 | 2934 | M68K_REGNAME(REGNO (reg1))); |
f4a6e73b | 2935 | fprintf (file, "l)"); |
79e68feb RS |
2936 | break; |
2937 | } | |
2c8ec431 | 2938 | /* FALL-THROUGH (is this really what we want?) */ |
79e68feb RS |
2939 | default: |
2940 | if (GET_CODE (addr) == CONST_INT | |
2941 | && INTVAL (addr) < 0x8000 | |
2942 | && INTVAL (addr) >= -0x8000) | |
2943 | { | |
3b4b85c9 | 2944 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); |
79e68feb | 2945 | } |
2c8ec431 DL |
2946 | else if (GET_CODE (addr) == CONST_INT) |
2947 | { | |
6d5f49b2 | 2948 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
2c8ec431 DL |
2949 | } |
2950 | else if (TARGET_PCREL) | |
2951 | { | |
2952 | fputc ('(', file); | |
2953 | output_addr_const (file, addr); | |
2954 | if (flag_pic == 1) | |
2955 | asm_fprintf (file, ":w,%Rpc)"); | |
2956 | else | |
2957 | asm_fprintf (file, ":l,%Rpc)"); | |
2958 | } | |
79e68feb RS |
2959 | else |
2960 | { | |
c2ac2ff6 AS |
2961 | /* Special case for SYMBOL_REF if the symbol name ends in |
2962 | `.<letter>', this can be mistaken as a size suffix. Put | |
2963 | the name in parentheses. */ | |
2964 | if (GET_CODE (addr) == SYMBOL_REF | |
2965 | && strlen (XSTR (addr, 0)) > 2 | |
2966 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
2967 | { | |
2968 | putc ('(', file); | |
2969 | output_addr_const (file, addr); | |
2970 | putc (')', file); | |
2971 | } | |
2972 | else | |
2973 | output_addr_const (file, addr); | |
79e68feb RS |
2974 | } |
2975 | break; | |
2976 | } | |
2977 | } | |
af13f02d JW |
2978 | \f |
2979 | /* Check for cases where a clr insns can be omitted from code using | |
2980 | strict_low_part sets. For example, the second clrl here is not needed: | |
2981 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
2982 | ||
2983 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
2984 | insn we are checking for redundancy. TARGET is the register set by the | |
2985 | clear insn. */ | |
2986 | ||
8a4a2253 BI |
2987 | bool |
2988 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
2989 | rtx target) | |
af13f02d JW |
2990 | { |
2991 | rtx p; | |
2992 | ||
2993 | p = prev_nonnote_insn (first_insn); | |
2994 | ||
2995 | while (p) | |
2996 | { | |
2997 | /* If it isn't an insn, then give up. */ | |
2998 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 2999 | return false; |
af13f02d JW |
3000 | |
3001 | if (reg_set_p (target, p)) | |
3002 | { | |
3003 | rtx set = single_set (p); | |
3004 | rtx dest; | |
3005 | ||
3006 | /* If it isn't an easy to recognize insn, then give up. */ | |
3007 | if (! set) | |
8a4a2253 | 3008 | return false; |
af13f02d JW |
3009 | |
3010 | dest = SET_DEST (set); | |
3011 | ||
3012 | /* If this sets the entire target register to zero, then our | |
3013 | first_insn is redundant. */ | |
3014 | if (rtx_equal_p (dest, target) | |
3015 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3016 | return true; |
af13f02d JW |
3017 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3018 | && GET_CODE (XEXP (dest, 0)) == REG | |
3019 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3020 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3021 | <= GET_MODE_SIZE (mode))) | |
3022 | /* This is a strict low part set which modifies less than | |
3023 | we are using, so it is safe. */ | |
3024 | ; | |
3025 | else | |
8a4a2253 | 3026 | return false; |
af13f02d JW |
3027 | } |
3028 | ||
3029 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3030 | } |
3031 | ||
8a4a2253 | 3032 | return false; |
af13f02d | 3033 | } |
67cd4f83 TG |
3034 | |
3035 | /* Accept integer operands in the range 0..0xffffffff. We have to check the | |
3036 | range carefully since this predicate is used in DImode contexts. Also, we | |
3037 | need some extra crud to make it work when hosted on 64-bit machines. */ | |
3038 | ||
3039 | int | |
8a4a2253 | 3040 | const_uint32_operand (rtx op, enum machine_mode mode) |
67cd4f83 | 3041 | { |
97660e20 RH |
3042 | /* It doesn't make sense to ask this question with a mode that is |
3043 | not larger than 32 bits. */ | |
3044 | if (GET_MODE_BITSIZE (mode) <= 32) | |
3045 | abort (); | |
3046 | ||
67cd4f83 TG |
3047 | #if HOST_BITS_PER_WIDE_INT > 32 |
3048 | /* All allowed constants will fit a CONST_INT. */ | |
3049 | return (GET_CODE (op) == CONST_INT | |
3050 | && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL)); | |
3051 | #else | |
07ed7ecf | 3052 | return (GET_CODE (op) == CONST_INT |
67cd4f83 TG |
3053 | || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0)); |
3054 | #endif | |
3055 | } | |
3056 | ||
3057 | /* Accept integer operands in the range -0x80000000..0x7fffffff. We have | |
3058 | to check the range carefully since this predicate is used in DImode | |
3059 | contexts. */ | |
3060 | ||
3061 | int | |
8a4a2253 | 3062 | const_sint32_operand (rtx op, enum machine_mode mode) |
67cd4f83 | 3063 | { |
97660e20 RH |
3064 | /* It doesn't make sense to ask this question with a mode that is |
3065 | not larger than 32 bits. */ | |
3066 | if (GET_MODE_BITSIZE (mode) <= 32) | |
3067 | abort (); | |
3068 | ||
67cd4f83 TG |
3069 | /* All allowed constants will fit a CONST_INT. */ |
3070 | return (GET_CODE (op) == CONST_INT | |
3071 | && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff)); | |
3072 | } | |
29ae8a3c | 3073 | |
2c8ec431 DL |
3074 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3075 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3076 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3077 | |
3078 | We model this by restricting the meaning of the basic predicates | |
3079 | (general_operand, memory_operand, etc) to forbid the use of this | |
3080 | addressing mode, and then define the following predicates that permit | |
3081 | this addressing mode. These predicates can then be used for the | |
3082 | source operands of the appropriate instructions. | |
3083 | ||
3084 | n.b. While it is theoretically possible to change all machine patterns | |
3085 | to use this addressing more where permitted by the architecture, | |
3086 | it has only been implemented for "common" cases: SImode, HImode, and | |
3087 | QImode operands, and only for the principle operations that would | |
3088 | require this addressing mode: data movement and simple integer operations. | |
3089 | ||
3090 | In parallel with these new predicates, two new constraint letters | |
3091 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3092 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3093 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3094 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3095 | of how these constraints are used. | |
3096 | ||
3097 | The use of these predicates is strictly optional, though patterns that | |
3098 | don't will cause an extra reload register to be allocated where one | |
3099 | was not necessary: | |
3100 | ||
3101 | lea (abc:w,%pc),%a0 ; need to reload address | |
3102 | moveq &1,%d1 ; since write to pc-relative space | |
3103 | movel %d1,%a0@ ; is not allowed | |
3104 | ... | |
3105 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3106 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3107 | ||
3108 | For more info, consult tiemann@cygnus.com. | |
3109 | ||
3110 | ||
3111 | All of the ugliness with predicates and constraints is due to the | |
3112 | simple fact that the m68k does not allow a pc-relative addressing | |
3113 | mode as a destination. gcc does not distinguish between source and | |
3114 | destination addresses. Hence, if we claim that pc-relative address | |
3115 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3116 | end up with invalid code. To get around this problem, we left | |
3117 | pc-relative modes as invalid addresses, and then added special | |
3118 | predicates and constraints to accept them. | |
3119 | ||
3120 | A cleaner way to handle this is to modify gcc to distinguish | |
3121 | between source and destination addresses. We can then say that | |
3122 | pc-relative is a valid source address but not a valid destination | |
3123 | address, and hopefully avoid a lot of the predicate and constraint | |
3124 | hackery. Unfortunately, this would be a pretty big change. It would | |
3125 | be a useful change for a number of ports, but there aren't any current | |
3126 | plans to undertake this. | |
3127 | ||
3128 | ***************************************************************************/ | |
3129 | ||
3130 | ||
3131 | /* Special case of a general operand that's used as a source operand. | |
3132 | Use this to permit reads from PC-relative memory when -mpcrel | |
3133 | is specified. */ | |
3134 | ||
3135 | int | |
8a4a2253 | 3136 | general_src_operand (rtx op, enum machine_mode mode) |
2c8ec431 DL |
3137 | { |
3138 | if (TARGET_PCREL | |
3139 | && GET_CODE (op) == MEM | |
3140 | && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
3141 | || GET_CODE (XEXP (op, 0)) == LABEL_REF | |
3142 | || GET_CODE (XEXP (op, 0)) == CONST)) | |
3143 | return 1; | |
3144 | return general_operand (op, mode); | |
3145 | } | |
3146 | ||
3147 | /* Special case of a nonimmediate operand that's used as a source. | |
3148 | Use this to permit reads from PC-relative memory when -mpcrel | |
3149 | is specified. */ | |
3150 | ||
3151 | int | |
8a4a2253 | 3152 | nonimmediate_src_operand (rtx op, enum machine_mode mode) |
2c8ec431 DL |
3153 | { |
3154 | if (TARGET_PCREL && GET_CODE (op) == MEM | |
3155 | && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
3156 | || GET_CODE (XEXP (op, 0)) == LABEL_REF | |
3157 | || GET_CODE (XEXP (op, 0)) == CONST)) | |
3158 | return 1; | |
3159 | return nonimmediate_operand (op, mode); | |
3160 | } | |
3161 | ||
3162 | /* Special case of a memory operand that's used as a source. | |
3163 | Use this to permit reads from PC-relative memory when -mpcrel | |
3164 | is specified. */ | |
3165 | ||
3166 | int | |
8a4a2253 | 3167 | memory_src_operand (rtx op, enum machine_mode mode) |
2c8ec431 DL |
3168 | { |
3169 | if (TARGET_PCREL && GET_CODE (op) == MEM | |
3170 | && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
3171 | || GET_CODE (XEXP (op, 0)) == LABEL_REF | |
3172 | || GET_CODE (XEXP (op, 0)) == CONST)) | |
3173 | return 1; | |
3174 | return memory_operand (op, mode); | |
3175 | } | |
3176 | ||
3177 | /* Predicate that accepts only a pc-relative address. This is needed | |
3178 | because pc-relative addresses don't satisfy the predicate | |
3179 | "general_src_operand". */ | |
3180 | ||
3181 | int | |
8a4a2253 | 3182 | pcrel_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c8ec431 DL |
3183 | { |
3184 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF | |
3185 | || GET_CODE (op) == CONST); | |
3186 | } | |
3187 | ||
5505f548 | 3188 | const char * |
8a4a2253 | 3189 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3190 | { |
3191 | int logval; | |
3192 | if (GET_CODE (operands[2]) == CONST_INT | |
d7b3c085 | 3193 | && (INTVAL (operands[2]) | 0xffff) == (HOST_WIDE_INT)0xffffffff |
29ae8a3c RK |
3194 | && (DATA_REG_P (operands[0]) |
3195 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3196 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3197 | { |
3198 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3199 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 3200 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
3201 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3202 | CC_STATUS_INIT; | |
3203 | if (operands[2] == const0_rtx) | |
3204 | return "clr%.w %0"; | |
3205 | return "and%.w %2,%0"; | |
3206 | } | |
3207 | if (GET_CODE (operands[2]) == CONST_INT | |
3208 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
3209 | && (DATA_REG_P (operands[0]) | |
3210 | || offsettable_memref_p (operands[0]))) | |
3211 | { | |
3212 | if (DATA_REG_P (operands[0])) | |
3213 | { | |
1d8eaa6b | 3214 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3215 | } |
3216 | else | |
3217 | { | |
b72f00af | 3218 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3219 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3220 | } |
3221 | /* This does not set condition codes in a standard way. */ | |
3222 | CC_STATUS_INIT; | |
3223 | return "bclr %1,%0"; | |
3224 | } | |
3225 | return "and%.l %2,%0"; | |
3226 | } | |
3227 | ||
5505f548 | 3228 | const char * |
8a4a2253 | 3229 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
3230 | { |
3231 | register int logval; | |
3232 | if (GET_CODE (operands[2]) == CONST_INT | |
3233 | && INTVAL (operands[2]) >> 16 == 0 | |
3234 | && (DATA_REG_P (operands[0]) | |
3235 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3236 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3237 | { |
3238 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3239 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3240 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3241 | CC_STATUS_INIT; | |
3242 | if (INTVAL (operands[2]) == 0xffff) | |
3243 | return "mov%.w %2,%0"; | |
3244 | return "or%.w %2,%0"; | |
3245 | } | |
3246 | if (GET_CODE (operands[2]) == CONST_INT | |
3247 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3248 | && (DATA_REG_P (operands[0]) | |
3249 | || offsettable_memref_p (operands[0]))) | |
3250 | { | |
3251 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3252 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3253 | else |
3254 | { | |
b72f00af | 3255 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3256 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3257 | } |
3258 | CC_STATUS_INIT; | |
3259 | return "bset %1,%0"; | |
3260 | } | |
3261 | return "or%.l %2,%0"; | |
3262 | } | |
3263 | ||
5505f548 | 3264 | const char * |
8a4a2253 | 3265 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
3266 | { |
3267 | register int logval; | |
3268 | if (GET_CODE (operands[2]) == CONST_INT | |
3269 | && INTVAL (operands[2]) >> 16 == 0 | |
3270 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 3271 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3272 | { |
3273 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 3274 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3275 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3276 | CC_STATUS_INIT; | |
3277 | if (INTVAL (operands[2]) == 0xffff) | |
3278 | return "not%.w %0"; | |
3279 | return "eor%.w %2,%0"; | |
3280 | } | |
3281 | if (GET_CODE (operands[2]) == CONST_INT | |
3282 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3283 | && (DATA_REG_P (operands[0]) | |
3284 | || offsettable_memref_p (operands[0]))) | |
3285 | { | |
3286 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3287 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3288 | else |
3289 | { | |
b72f00af | 3290 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3291 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3292 | } |
3293 | CC_STATUS_INIT; | |
3294 | return "bchg %1,%0"; | |
3295 | } | |
3296 | return "eor%.l %2,%0"; | |
3297 | } | |
7c262518 | 3298 | |
45849738 BI |
3299 | #ifdef M68K_TARGET_COFF |
3300 | ||
3301 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
3302 | ||
3303 | static void | |
3304 | m68k_coff_asm_named_section (const char *name, unsigned int flags) | |
3305 | { | |
3306 | char flagchar; | |
3307 | ||
3308 | if (flags & SECTION_WRITE) | |
3309 | flagchar = 'd'; | |
3310 | else | |
3311 | flagchar = 'x'; | |
3312 | ||
3313 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
3314 | } | |
3315 | ||
3316 | #endif /* M68K_TARGET_COFF */ | |
3317 | ||
c590b625 | 3318 | static void |
8a4a2253 BI |
3319 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
3320 | HOST_WIDE_INT delta, | |
3321 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
3322 | tree function) | |
483ab821 | 3323 | { |
c590b625 RH |
3324 | rtx xops[1]; |
3325 | const char *fmt; | |
3326 | ||
3327 | if (delta > 0 && delta <= 8) | |
e6d98cb0 BI |
3328 | asm_fprintf (file, MOTOROLA ? |
3329 | "\taddq.l %I%d,4(%Rsp)\n" : | |
3330 | "\taddql %I%d,%Rsp@(4)\n", | |
3331 | (int) delta); | |
c590b625 | 3332 | else if (delta < 0 && delta >= -8) |
e6d98cb0 BI |
3333 | asm_fprintf (file, MOTOROLA ? |
3334 | "\tsubq.l %I%d,4(%Rsp)\n" : | |
3335 | "\tsubql %I%d,%Rsp@(4)\n", | |
3336 | (int) -delta); | |
5050d266 PB |
3337 | else if (TARGET_COLDFIRE) |
3338 | { | |
3339 | /* ColdFire can't add/sub a constant to memory unless it is in | |
3340 | the range of addq/subq. So load the value into %d0 and | |
3341 | then add it to 4(%sp). */ | |
3342 | if (delta >= -128 && delta <= 127) | |
3343 | asm_fprintf (file, MOTOROLA ? | |
3344 | "\tmoveq.l %I%wd,%Rd0\n" : | |
3345 | "\tmoveql %I%wd,%Rd0\n", delta); | |
3346 | else | |
3347 | asm_fprintf (file, MOTOROLA ? | |
3348 | "\tmove.l %I%wd,%Rd0\n" : | |
3349 | "\tmovel %I%wd,%Rd0\n", delta); | |
3350 | asm_fprintf (file, MOTOROLA ? | |
3351 | "\tadd.l %Rd0,4(%Rsp)\n" : | |
3352 | "\taddl %Rd0,%Rsp@(4)\n"); | |
3353 | } | |
c590b625 | 3354 | else |
e6d98cb0 BI |
3355 | asm_fprintf (file, MOTOROLA ? |
3356 | "\tadd.l %I%wd,4(%Rsp)\n" : | |
3357 | "\taddl %I%wd,%Rsp@(4)\n", | |
3358 | delta); | |
c590b625 RH |
3359 | |
3360 | xops[0] = DECL_RTL (function); | |
3361 | ||
3362 | /* Logic taken from call patterns in m68k.md. */ | |
3363 | if (flag_pic) | |
3364 | { | |
3365 | if (TARGET_PCREL) | |
3366 | fmt = "bra.l %o0"; | |
a2ef3db7 | 3367 | else if ((flag_pic == 1) || TARGET_68020) |
c590b625 | 3368 | { |
e6d98cb0 | 3369 | if (MOTOROLA) |
1f0282cb | 3370 | #if defined(USE_GAS) |
e6d98cb0 | 3371 | fmt = "bra.l %0@PLTPC"; |
c590b625 | 3372 | #else |
e6d98cb0 | 3373 | fmt = "bra %0@PLTPC"; |
c590b625 | 3374 | #endif |
e6d98cb0 | 3375 | else /* !MOTOROLA */ |
c590b625 | 3376 | #ifdef USE_GAS |
e6d98cb0 | 3377 | fmt = "bra.l %0"; |
c590b625 | 3378 | #else |
e6d98cb0 | 3379 | fmt = "jra %0,a1"; |
c590b625 RH |
3380 | #endif |
3381 | } | |
a2ef3db7 BI |
3382 | else if (optimize_size || TARGET_ID_SHARED_LIBRARY) |
3383 | fmt = "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)"; | |
3384 | else | |
3385 | fmt = "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)"; | |
c590b625 RH |
3386 | } |
3387 | else | |
3388 | { | |
e6d98cb0 | 3389 | #if MOTOROLA && !defined (USE_GAS) |
c590b625 | 3390 | fmt = "jmp %0"; |
c590b625 | 3391 | #else |
1d6302b1 | 3392 | fmt = "jra %0"; |
c590b625 RH |
3393 | #endif |
3394 | } | |
3395 | ||
3396 | output_asm_insn (fmt, xops); | |
483ab821 | 3397 | } |
8636be86 KH |
3398 | |
3399 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
3400 | ||
3401 | static rtx | |
3402 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3403 | int incoming ATTRIBUTE_UNUSED) | |
3404 | { | |
3405 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
3406 | } |