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Commit | Line | Data |
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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
a8c253d0 | 3 | 2001, 2003, 2004, 2005, 2006 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
20 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
79e68feb | 22 | |
79e68feb | 23 | #include "config.h" |
f5220a5d | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
da932f04 | 27 | #include "tree.h" |
79e68feb | 28 | #include "rtl.h" |
49ad7cfa | 29 | #include "function.h" |
79e68feb RS |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
79e68feb RS |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
1d8eaa6b | 37 | #include "recog.h" |
f5220a5d | 38 | #include "toplev.h" |
6d5f49b2 RH |
39 | #include "expr.h" |
40 | #include "reload.h" | |
5505f548 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
2cc07db4 | 44 | #include "debug.h" |
79e68feb RS |
45 | #include "flags.h" |
46 | ||
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
e6d98cb0 BI |
59 | /* The ASM_DOT macro allows easy string pasting to handle the differences |
60 | between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't | |
61 | support the %. option. */ | |
62 | #if MOTOROLA | |
63 | # define ASM_DOT "." | |
64 | # define ASM_DOTW ".w" | |
65 | # define ASM_DOTL ".l" | |
66 | #else | |
67 | # define ASM_DOT "" | |
68 | # define ASM_DOTW "" | |
69 | # define ASM_DOTL "" | |
70 | #endif | |
71 | ||
72 | ||
ff482c8d | 73 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
74 | struct m68k_frame |
75 | { | |
76 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 77 | HOST_WIDE_INT offset; |
3d74bc09 BI |
78 | |
79 | /* Offset of FPU registers. */ | |
80 | HOST_WIDE_INT foffset; | |
81 | ||
82 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 83 | HOST_WIDE_INT size; |
3d74bc09 BI |
84 | |
85 | /* Data and address register. */ | |
48ed72a4 PB |
86 | int reg_no; |
87 | unsigned int reg_mask; | |
88 | unsigned int reg_rev_mask; | |
3d74bc09 BI |
89 | |
90 | /* FPU registers. */ | |
48ed72a4 PB |
91 | int fpu_no; |
92 | unsigned int fpu_mask; | |
93 | unsigned int fpu_rev_mask; | |
3d74bc09 BI |
94 | |
95 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
96 | HOST_WIDE_INT frame_pointer_offset; |
97 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
98 | |
99 | /* Function which the above information refers to. */ | |
100 | int funcdef_no; | |
48ed72a4 PB |
101 | }; |
102 | ||
3d74bc09 BI |
103 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
104 | static struct m68k_frame current_frame; | |
105 | ||
4af06170 | 106 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
107 | static rtx find_addr_reg (rtx); |
108 | static const char *singlemove_string (rtx *); | |
109 | static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT); | |
110 | static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
45849738 | 111 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 112 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 113 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
114 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
115 | HOST_WIDE_INT, tree); | |
8636be86 | 116 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
117 | static bool m68k_interrupt_function_p (tree func); |
118 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, | |
119 | tree args, int flags, | |
120 | bool *no_add_attrs); | |
3d74bc09 | 121 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 122 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
8a4a2253 BI |
123 | static int const_int_cost (rtx); |
124 | static bool m68k_rtx_costs (rtx, int, int, int *); | |
79e68feb RS |
125 | \f |
126 | ||
a2ef3db7 | 127 | /* Specify the identification number of the library being built */ |
4af06170 | 128 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 129 | |
2b3600ac JL |
130 | /* Nonzero if the last compare/test insn had FP operands. The |
131 | sCC expanders peek at this to determine what to do for the | |
132 | 68060, which has no fsCC instructions. */ | |
133 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
134 | \f |
135 | /* Initialize the GCC target structure. */ | |
301d03af RS |
136 | |
137 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
138 | #undef TARGET_ASM_ALIGNED_HI_OP | |
139 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
140 | #endif | |
141 | ||
142 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
143 | #undef TARGET_ASM_BYTE_OP | |
144 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
145 | #undef TARGET_ASM_ALIGNED_HI_OP | |
146 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
147 | #undef TARGET_ASM_ALIGNED_SI_OP | |
148 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
149 | #endif | |
150 | ||
151 | #if INT_OP_GROUP == INT_OP_DC | |
152 | #undef TARGET_ASM_BYTE_OP | |
153 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
154 | #undef TARGET_ASM_ALIGNED_HI_OP | |
155 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
156 | #undef TARGET_ASM_ALIGNED_SI_OP | |
157 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
158 | #endif | |
159 | ||
160 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
161 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
162 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
163 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
164 | ||
08c148a8 NB |
165 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
166 | #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue | |
167 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
168 | #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue | |
ef1dbfb0 | 169 | |
c590b625 RH |
170 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
171 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 AS |
172 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
173 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 174 | |
1bc7c5b6 ZW |
175 | #undef TARGET_ASM_FILE_START_APP_OFF |
176 | #define TARGET_ASM_FILE_START_APP_OFF true | |
177 | ||
4af06170 | 178 | #undef TARGET_DEFAULT_TARGET_FLAGS |
900ec02d | 179 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT |
4af06170 RS |
180 | #undef TARGET_HANDLE_OPTION |
181 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
182 | ||
3c50106f RH |
183 | #undef TARGET_RTX_COSTS |
184 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
185 | ||
48ed72a4 PB |
186 | #undef TARGET_ATTRIBUTE_TABLE |
187 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
188 | ||
8636be86 KH |
189 | #undef TARGET_PROMOTE_PROTOTYPES |
190 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
191 | ||
192 | #undef TARGET_STRUCT_VALUE_RTX | |
193 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
194 | ||
48ed72a4 PB |
195 | static const struct attribute_spec m68k_attribute_table[] = |
196 | { | |
197 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
198 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, | |
199 | { NULL, 0, 0, false, false, false, NULL } | |
200 | }; | |
201 | ||
f6897b10 | 202 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 203 | \f |
900ec02d JB |
204 | /* Base flags for 68k ISAs. */ |
205 | #define FL_FOR_isa_00 FL_ISA_68000 | |
206 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
207 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
208 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
209 | not to. */ | |
210 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
211 | | FL_BITFIELD | FL_68881) | |
212 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
213 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
214 | ||
215 | /* Base flags for ColdFire ISAs. */ | |
216 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
217 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
218 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
219 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
220 | #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP) | |
221 | ||
222 | enum m68k_isa | |
223 | { | |
224 | /* Traditional 68000 instruction sets. */ | |
225 | isa_00, | |
226 | isa_10, | |
227 | isa_20, | |
228 | isa_40, | |
229 | isa_cpu32, | |
230 | /* ColdFire instruction set variants. */ | |
231 | isa_a, | |
232 | isa_aplus, | |
233 | isa_b, | |
234 | isa_c, | |
235 | isa_max | |
236 | }; | |
237 | ||
238 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
239 | struct m68k_target_selection | |
240 | { | |
241 | /* The argument being described. */ | |
242 | const char *name; | |
243 | ||
244 | /* For -mcpu, this is the device selected by the option. | |
245 | For -mtune and -march, it is a representative device | |
246 | for the microarchitecture or ISA respectively. */ | |
247 | enum target_device device; | |
248 | ||
249 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
250 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
251 | const char *family; | |
252 | enum uarch_type microarch; | |
253 | enum m68k_isa isa; | |
254 | unsigned long flags; | |
255 | }; | |
256 | ||
257 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
258 | static const struct m68k_target_selection all_devices[] = | |
259 | { | |
260 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
261 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
262 | #include "m68k-devices.def" | |
263 | #undef M68K_DEVICE | |
264 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
265 | }; | |
266 | ||
267 | /* A list of all ISAs, mapping each one to a representative device. | |
268 | Used for -march selection. */ | |
269 | static const struct m68k_target_selection all_isas[] = | |
270 | { | |
271 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
272 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
273 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
274 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
275 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
276 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
277 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
278 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
279 | | FL_CF_HWDIV) }, | |
280 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
281 | | FL_CF_HWDIV) }, | |
282 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
283 | { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c | |
284 | | FL_CF_FPU | |
285 | | FL_CF_EMAC) }, | |
286 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
287 | }; | |
288 | ||
289 | /* A list of all microarchitectures, mapping each one to a representative | |
290 | device. Used for -mtune selection. */ | |
291 | static const struct m68k_target_selection all_microarchs[] = | |
292 | { | |
293 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
294 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
295 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
296 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
297 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
298 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
299 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
300 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
301 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
302 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, | |
303 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
304 | | FL_CF_HWDIV) }, | |
305 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
306 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
307 | | FL_CF_USP | |
308 | | FL_CF_EMAC | |
309 | | FL_CF_FPU) }, | |
310 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
311 | }; | |
312 | \f | |
313 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
314 | or null for options that have not been used. */ | |
315 | const struct m68k_target_selection *m68k_cpu_entry; | |
316 | const struct m68k_target_selection *m68k_arch_entry; | |
317 | const struct m68k_target_selection *m68k_tune_entry; | |
318 | ||
319 | /* Which CPU we are generating code for. */ | |
320 | enum target_device m68k_cpu; | |
321 | ||
322 | /* Which microarchitecture to tune for. */ | |
323 | enum uarch_type m68k_tune; | |
324 | ||
325 | /* Which FPU to use. */ | |
326 | enum fpu_type m68k_fpu; | |
4af06170 | 327 | |
900ec02d JB |
328 | /* The set of FL_* flags that apply to the target processor. */ |
329 | unsigned int m68k_cpu_flags; | |
330 | \f | |
331 | /* See whether TABLE has an entry with name NAME. Return true and | |
332 | store the entry in *ENTRY if so, otherwise return false and | |
333 | leave *ENTRY alone. */ | |
334 | ||
335 | static bool | |
336 | m68k_find_selection (const struct m68k_target_selection **entry, | |
337 | const struct m68k_target_selection *table, | |
338 | const char *name) | |
339 | { | |
340 | size_t i; | |
341 | ||
342 | for (i = 0; table[i].name; i++) | |
343 | if (strcmp (table[i].name, name) == 0) | |
344 | { | |
345 | *entry = table + i; | |
346 | return true; | |
347 | } | |
348 | return false; | |
349 | } | |
4af06170 RS |
350 | |
351 | /* Implement TARGET_HANDLE_OPTION. */ | |
352 | ||
353 | static bool | |
354 | m68k_handle_option (size_t code, const char *arg, int value) | |
355 | { | |
356 | switch (code) | |
357 | { | |
900ec02d JB |
358 | case OPT_march_: |
359 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
360 | ||
361 | case OPT_mcpu_: | |
362 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
363 | ||
364 | case OPT_mtune_: | |
365 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
366 | ||
4af06170 | 367 | case OPT_m5200: |
900ec02d | 368 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
369 | |
370 | case OPT_m5206e: | |
900ec02d | 371 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
372 | |
373 | case OPT_m528x: | |
900ec02d | 374 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
375 | |
376 | case OPT_m5307: | |
900ec02d | 377 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
378 | |
379 | case OPT_m5407: | |
900ec02d | 380 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 381 | |
dcc21c4c | 382 | case OPT_mcfv4e: |
900ec02d | 383 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 384 | |
4af06170 RS |
385 | case OPT_m68000: |
386 | case OPT_mc68000: | |
900ec02d | 387 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 388 | |
3197c489 | 389 | case OPT_m68010: |
900ec02d | 390 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 391 | |
4af06170 RS |
392 | case OPT_m68020: |
393 | case OPT_mc68020: | |
900ec02d | 394 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
395 | |
396 | case OPT_m68020_40: | |
900ec02d JB |
397 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
398 | "68020-40") | |
399 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
400 | |
401 | case OPT_m68020_60: | |
900ec02d JB |
402 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
403 | "68020-60") | |
404 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
405 | |
406 | case OPT_m68030: | |
900ec02d | 407 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
408 | |
409 | case OPT_m68040: | |
900ec02d | 410 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
411 | |
412 | case OPT_m68060: | |
900ec02d | 413 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
414 | |
415 | case OPT_m68302: | |
900ec02d | 416 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
417 | |
418 | case OPT_m68332: | |
419 | case OPT_mcpu32: | |
900ec02d | 420 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
421 | |
422 | case OPT_mshared_library_id_: | |
423 | if (value > MAX_LIBRARY_ID) | |
424 | error ("-mshared-library-id=%s is not between 0 and %d", | |
425 | arg, MAX_LIBRARY_ID); | |
426 | else | |
427 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
428 | return true; | |
429 | ||
430 | default: | |
431 | return true; | |
432 | } | |
433 | } | |
434 | ||
ef1dbfb0 RK |
435 | /* Sometimes certain combinations of command options do not make |
436 | sense on a particular target machine. You can define a macro | |
437 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
438 | defined, is executed once just after all the command options have | |
439 | been parsed. | |
440 | ||
441 | Don't use this macro to turn on various extra optimizations for | |
442 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
443 | ||
444 | void | |
8a4a2253 | 445 | override_options (void) |
ef1dbfb0 | 446 | { |
900ec02d JB |
447 | const struct m68k_target_selection *entry; |
448 | unsigned long target_mask; | |
449 | ||
450 | /* User can choose: | |
451 | ||
452 | -mcpu= | |
453 | -march= | |
454 | -mtune= | |
455 | ||
456 | -march=ARCH should generate code that runs any processor | |
457 | implementing architecture ARCH. -mcpu=CPU should override -march | |
458 | and should generate code that runs on processor CPU, making free | |
459 | use of any instructions that CPU understands. -mtune=UARCH applies | |
460 | on top of -mcpu or -march and optimises the code for UARCH. It does | |
461 | not change the target architecture. */ | |
462 | if (m68k_cpu_entry) | |
463 | { | |
464 | /* Complain if the -march setting is for a different microarchitecture, | |
465 | or includes flags that the -mcpu setting doesn't. */ | |
466 | if (m68k_arch_entry | |
467 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
468 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
469 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
470 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
471 | ||
472 | entry = m68k_cpu_entry; | |
473 | } | |
474 | else | |
475 | entry = m68k_arch_entry; | |
476 | ||
477 | if (!entry) | |
478 | entry = all_devices + TARGET_CPU_DEFAULT; | |
479 | ||
480 | m68k_cpu_flags = entry->flags; | |
481 | ||
482 | /* Use the architecture setting to derive default values for | |
483 | certain flags. */ | |
484 | target_mask = 0; | |
485 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) | |
486 | target_mask |= MASK_BITFIELD; | |
487 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
488 | target_mask |= MASK_CF_HWDIV; | |
489 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
490 | target_mask |= MASK_HARD_FLOAT; | |
491 | target_flags |= target_mask & ~target_flags_explicit; | |
492 | ||
493 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
494 | m68k_cpu = entry->device; | |
495 | if (m68k_tune_entry) | |
496 | m68k_tune = m68k_tune_entry->microarch; | |
497 | #ifdef M68K_DEFAULT_TUNE | |
498 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
499 | m68k_tune = M68K_DEFAULT_TUNE; | |
500 | #endif | |
501 | else | |
502 | m68k_tune = entry->microarch; | |
503 | ||
504 | /* Set the type of FPU. */ | |
505 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
506 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
507 | : FPUTYPE_68881); | |
508 | ||
a2ef3db7 BI |
509 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
510 | * both specified together. Doing so simply doesn't make sense. | |
511 | */ | |
512 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
513 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
514 | ||
515 | /* If we're generating code for a separate A5 relative data segment, | |
516 | * we've got to enable -fPIC as well. This might be relaxable to | |
517 | * -fpic but it hasn't been tested properly. | |
518 | */ | |
519 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
520 | flag_pic = 2; | |
521 | ||
adf2ac37 RH |
522 | /* -fPIC uses 32-bit pc-relative displacements, which don't exist |
523 | until the 68020. */ | |
a2ef3db7 | 524 | if (!TARGET_68020 && !TARGET_COLDFIRE && (flag_pic == 2)) |
ab532386 | 525 | error ("-fPIC is not currently supported on the 68000 or 68010"); |
adf2ac37 RH |
526 | |
527 | /* ??? A historic way of turning on pic, or is this intended to | |
528 | be an embedded thing that doesn't have the same name binding | |
529 | significance that it does on hosted ELF systems? */ | |
530 | if (TARGET_PCREL && flag_pic == 0) | |
531 | flag_pic = 1; | |
532 | ||
533 | /* Turn off function cse if we are doing PIC. We always want function call | |
534 | to be done as `bsr foo@PLTPC', so it will force the assembler to create | |
535 | the PLT entry for `foo'. Doing function cse will cause the address of | |
536 | `foo' to be loaded into a register, which is exactly what we want to | |
537 | avoid when we are doing PIC on svr4 m68k. */ | |
538 | if (flag_pic) | |
539 | flag_no_function_cse = 1; | |
540 | ||
541 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 542 | } |
79e68feb | 543 | \f |
48ed72a4 PB |
544 | /* Return nonzero if FUNC is an interrupt function as specified by the |
545 | "interrupt_handler" attribute. */ | |
546 | static bool | |
547 | m68k_interrupt_function_p(tree func) | |
548 | { | |
549 | tree a; | |
550 | ||
551 | if (TREE_CODE (func) != FUNCTION_DECL) | |
552 | return false; | |
553 | ||
554 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); | |
555 | return (a != NULL_TREE); | |
556 | } | |
557 | ||
558 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
559 | struct attribute_spec.handler. */ | |
560 | static tree | |
561 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
562 | tree args ATTRIBUTE_UNUSED, | |
563 | int flags ATTRIBUTE_UNUSED, | |
564 | bool *no_add_attrs) | |
565 | { | |
566 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
567 | { | |
5c498b10 | 568 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
569 | IDENTIFIER_POINTER (name)); |
570 | *no_add_attrs = true; | |
571 | } | |
572 | ||
573 | return NULL_TREE; | |
574 | } | |
860c4900 BI |
575 | |
576 | static void | |
3d74bc09 | 577 | m68k_compute_frame_layout (void) |
860c4900 BI |
578 | { |
579 | int regno, saved; | |
580 | unsigned int mask, rmask; | |
48ed72a4 | 581 | bool interrupt_handler = m68k_interrupt_function_p (current_function_decl); |
860c4900 | 582 | |
3d74bc09 BI |
583 | /* Only compute the frame once per function. |
584 | Don't cache information until reload has been completed. */ | |
585 | if (current_frame.funcdef_no == current_function_funcdef_no | |
586 | && reload_completed) | |
587 | return; | |
588 | ||
589 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 BI |
590 | |
591 | mask = rmask = saved = 0; | |
592 | for (regno = 0; regno < 16; regno++) | |
48ed72a4 | 593 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 BI |
594 | { |
595 | mask |= 1 << regno; | |
596 | rmask |= 1 << (15 - regno); | |
597 | saved++; | |
598 | } | |
3d74bc09 BI |
599 | current_frame.offset = saved * 4; |
600 | current_frame.reg_no = saved; | |
601 | current_frame.reg_mask = mask; | |
602 | current_frame.reg_rev_mask = rmask; | |
860c4900 | 603 | |
57047680 GN |
604 | current_frame.foffset = 0; |
605 | mask = rmask = saved = 0; | |
dcc21c4c | 606 | if (TARGET_HARD_FLOAT) |
860c4900 | 607 | { |
860c4900 | 608 | for (regno = 16; regno < 24; regno++) |
3d74bc09 | 609 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 610 | { |
85802504 GN |
611 | mask |= 1 << (regno - 16); |
612 | rmask |= 1 << (23 - regno); | |
860c4900 BI |
613 | saved++; |
614 | } | |
dcc21c4c | 615 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 616 | current_frame.offset += current_frame.foffset; |
860c4900 | 617 | } |
57047680 GN |
618 | current_frame.fpu_no = saved; |
619 | current_frame.fpu_mask = mask; | |
620 | current_frame.fpu_rev_mask = rmask; | |
3d74bc09 BI |
621 | |
622 | /* Remember what function this frame refers to. */ | |
623 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
624 | } |
625 | ||
626 | HOST_WIDE_INT | |
627 | m68k_initial_elimination_offset (int from, int to) | |
628 | { | |
42b67c06 PB |
629 | int argptr_offset; |
630 | /* The arg pointer points 8 bytes before the start of the arguments, | |
631 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
632 | frame pointer in most frames. */ | |
633 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 634 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 635 | return argptr_offset; |
860c4900 | 636 | |
3d74bc09 | 637 | m68k_compute_frame_layout (); |
860c4900 | 638 | |
4761e388 NS |
639 | gcc_assert (to == STACK_POINTER_REGNUM); |
640 | switch (from) | |
641 | { | |
a0a7fbc9 | 642 | case ARG_POINTER_REGNUM: |
42b67c06 | 643 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
644 | case FRAME_POINTER_REGNUM: |
645 | return current_frame.offset + current_frame.size; | |
646 | default: | |
647 | gcc_unreachable (); | |
648 | } | |
860c4900 BI |
649 | } |
650 | ||
97c55091 GN |
651 | /* Refer to the array `regs_ever_live' to determine which registers |
652 | to save; `regs_ever_live[I]' is nonzero if register number I | |
653 | is ever used in the function. This function is responsible for | |
654 | knowing which registers should not be saved even if used. | |
655 | Return true if we need to save REGNO. */ | |
656 | ||
48ed72a4 PB |
657 | static bool |
658 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 659 | { |
b86ba8a3 AT |
660 | if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM) |
661 | { | |
662 | if (current_function_uses_pic_offset_table) | |
663 | return true; | |
664 | if (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY) | |
665 | return true; | |
666 | } | |
2cff4a6e AS |
667 | |
668 | if (current_function_calls_eh_return) | |
669 | { | |
670 | unsigned int i; | |
671 | for (i = 0; ; i++) | |
672 | { | |
673 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
674 | if (test == INVALID_REGNUM) | |
675 | break; | |
676 | if (test == regno) | |
48ed72a4 | 677 | return true; |
2cff4a6e AS |
678 | } |
679 | } | |
680 | ||
48ed72a4 PB |
681 | /* Fixed regs we never touch. */ |
682 | if (fixed_regs[regno]) | |
683 | return false; | |
684 | ||
685 | /* The frame pointer (if it is such) is handled specially. */ | |
686 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
687 | return false; | |
688 | ||
689 | /* Interrupt handlers must also save call_used_regs | |
690 | if they are live or when calling nested functions. */ | |
691 | if (interrupt_handler) | |
a0a7fbc9 AS |
692 | { |
693 | if (regs_ever_live[regno]) | |
694 | return true; | |
48ed72a4 | 695 | |
a0a7fbc9 AS |
696 | if (!current_function_is_leaf && call_used_regs[regno]) |
697 | return true; | |
698 | } | |
48ed72a4 PB |
699 | |
700 | /* Never need to save registers that aren't touched. */ | |
701 | if (!regs_ever_live[regno]) | |
702 | return false; | |
703 | ||
b2e08ed4 | 704 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 705 | return !call_used_regs[regno]; |
2cff4a6e AS |
706 | } |
707 | ||
79e68feb RS |
708 | /* This function generates the assembly code for function entry. |
709 | STREAM is a stdio stream to output the code to. | |
97c55091 | 710 | SIZE is an int: how many units of temporary storage to allocate. */ |
79e68feb | 711 | |
08c148a8 | 712 | static void |
a0a7fbc9 AS |
713 | m68k_output_function_prologue (FILE *stream, |
714 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
79e68feb | 715 | { |
860c4900 | 716 | HOST_WIDE_INT fsize_with_regs; |
08c148a8 | 717 | HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET; |
3d74bc09 BI |
718 | |
719 | m68k_compute_frame_layout(); | |
720 | ||
a157febd GK |
721 | /* If the stack limit is a symbol, we can check it here, |
722 | before actually allocating the space. */ | |
723 | if (current_function_limit_stack | |
724 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
e6d98cb0 BI |
725 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %I%s+%wd,%Rsp\n\ttrapcs\n", |
726 | XSTR (stack_limit_rtx, 0), current_frame.size + 4); | |
79e68feb | 727 | |
97c55091 | 728 | /* On ColdFire add register save into initial stack frame setup, if possible. */ |
a89e3f21 | 729 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
730 | if (TARGET_COLDFIRE) |
731 | { | |
732 | if (current_frame.reg_no > 2) | |
733 | fsize_with_regs += current_frame.reg_no * 4; | |
734 | if (current_frame.fpu_no) | |
735 | fsize_with_regs += current_frame.fpu_no * 8; | |
736 | } | |
860c4900 | 737 | |
79e68feb RS |
738 | if (frame_pointer_needed) |
739 | { | |
fe95f2f7 | 740 | if (current_frame.size == 0 && TUNE_68040) |
e4e873f1 | 741 | /* on the 68040, pea + move is faster than link.w 0 */ |
a0a7fbc9 AS |
742 | fprintf (stream, (MOTOROLA |
743 | ? "\tpea (%s)\n\tmove.l %s,%s\n" | |
744 | : "\tpea %s@\n\tmovel %s,%s\n"), | |
745 | M68K_REGNAME (FRAME_POINTER_REGNUM), | |
746 | M68K_REGNAME (STACK_POINTER_REGNUM), | |
747 | M68K_REGNAME (FRAME_POINTER_REGNUM)); | |
860c4900 | 748 | else if (fsize_with_regs < 0x8000) |
e6d98cb0 | 749 | asm_fprintf (stream, "\tlink" ASM_DOTW " %s,%I%wd\n", |
a0a7fbc9 | 750 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 751 | else if (TARGET_68020) |
e6d98cb0 | 752 | asm_fprintf (stream, "\tlink" ASM_DOTL " %s,%I%wd\n", |
a0a7fbc9 | 753 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); |
79e68feb | 754 | else |
e6d98cb0 | 755 | /* Adding negative number is faster on the 68040. */ |
a0a7fbc9 AS |
756 | asm_fprintf (stream, |
757 | "\tlink" ASM_DOTW " %s,%I0\n" | |
758 | "\tadd" ASM_DOT "l %I%wd,%Rsp\n", | |
759 | M68K_REGNAME (FRAME_POINTER_REGNUM), -fsize_with_regs); | |
79e68feb | 760 | } |
860c4900 | 761 | else if (fsize_with_regs) /* !frame_pointer_needed */ |
79e68feb | 762 | { |
860c4900 | 763 | if (fsize_with_regs < 0x8000) |
79e68feb | 764 | { |
860c4900 | 765 | if (fsize_with_regs <= 8) |
afaff477 | 766 | { |
9425fb04 | 767 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
768 | asm_fprintf (stream, "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", |
769 | fsize_with_regs); | |
7bc88d49 | 770 | else |
e6d98cb0 BI |
771 | asm_fprintf (stream, "\tsubq" ASM_DOT "l %I%wd,%Rsp\n", |
772 | fsize_with_regs); | |
afaff477 | 773 | } |
fe95f2f7 | 774 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
e6d98cb0 BI |
775 | /* On the CPU32 it is faster to use two subqw instructions to |
776 | subtract a small integer (8 < N <= 16) to a register. */ | |
777 | asm_fprintf (stream, | |
778 | "\tsubq" ASM_DOT "w %I8,%Rsp\n" | |
779 | "\tsubq" ASM_DOT "w %I%wd,%Rsp\n", | |
780 | fsize_with_regs - 8); | |
fe95f2f7 | 781 | else if (TUNE_68040) |
e6d98cb0 BI |
782 | /* Adding negative number is faster on the 68040. */ |
783 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", | |
784 | -fsize_with_regs); | |
7bc88d49 | 785 | else |
a0a7fbc9 AS |
786 | asm_fprintf (stream, (MOTOROLA |
787 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
788 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 789 | -fsize_with_regs); |
79e68feb | 790 | } |
860c4900 | 791 | else /* fsize_with_regs >= 0x8000 */ |
a0a7fbc9 AS |
792 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", |
793 | -fsize_with_regs); | |
d9e88af0 | 794 | } /* !frame_pointer_needed */ |
e6d98cb0 | 795 | |
d9e88af0 PB |
796 | if (dwarf2out_do_frame ()) |
797 | { | |
798 | if (frame_pointer_needed) | |
078e983e | 799 | { |
b214e1e7 | 800 | char *l; |
d9e88af0 | 801 | l = (char *) dwarf2out_cfi_label (); |
b214e1e7 PB |
802 | cfa_offset += 4; |
803 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_offset); | |
804 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset); | |
805 | cfa_offset += current_frame.size; | |
806 | } | |
d9e88af0 | 807 | else |
b214e1e7 PB |
808 | { |
809 | cfa_offset += current_frame.size; | |
810 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); | |
811 | } | |
d9e88af0 | 812 | } |
860c4900 | 813 | |
57047680 | 814 | if (current_frame.fpu_mask) |
79e68feb | 815 | { |
dcc21c4c PB |
816 | if (TARGET_68881) |
817 | { | |
818 | asm_fprintf (stream, (MOTOROLA | |
819 | ? "\tfmovm %I0x%x,-(%Rsp)\n" | |
820 | : "\tfmovem %I0x%x,%Rsp@-\n"), | |
821 | current_frame.fpu_mask); | |
822 | } | |
823 | else | |
824 | { | |
825 | int offset; | |
826 | ||
827 | /* stack already has registers in it. Find the offset from | |
828 | the bottom of stack to where the FP registers go */ | |
829 | if (current_frame.reg_no <= 2) | |
830 | offset = 0; | |
831 | else | |
832 | offset = current_frame.reg_no * 4; | |
833 | if (offset) | |
834 | asm_fprintf (stream, | |
835 | "\tfmovem %I0x%x,%d(%Rsp)\n", | |
836 | current_frame.fpu_rev_mask, | |
837 | offset); | |
838 | else | |
839 | asm_fprintf (stream, | |
840 | "\tfmovem %I0x%x,(%Rsp)\n", | |
841 | current_frame.fpu_rev_mask); | |
842 | } | |
e6d98cb0 | 843 | |
57047680 GN |
844 | if (dwarf2out_do_frame ()) |
845 | { | |
846 | char *l = (char *) dwarf2out_cfi_label (); | |
847 | int n_regs, regno; | |
848 | ||
dcc21c4c | 849 | cfa_offset += current_frame.fpu_no * TARGET_FP_REG_SIZE; |
57047680 GN |
850 | if (! frame_pointer_needed) |
851 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
852 | for (regno = 16, n_regs = 0; regno < 24; regno++) | |
853 | if (current_frame.fpu_mask & (1 << (regno - 16))) | |
dcc21c4c PB |
854 | dwarf2out_reg_save (l, regno, -cfa_offset |
855 | + n_regs++ * TARGET_FP_REG_SIZE); | |
f277471f | 856 | } |
79e68feb | 857 | } |
99df2465 | 858 | |
01bbf777 | 859 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
860 | This has the disadvantage that it may be too late... */ |
861 | if (current_function_limit_stack) | |
862 | { | |
863 | if (REG_P (stack_limit_rtx)) | |
e6d98cb0 | 864 | asm_fprintf (stream, "\tcmp" ASM_DOT "l %s,%Rsp\n\ttrapcs\n", |
a0a7fbc9 | 865 | M68K_REGNAME (REGNO (stack_limit_rtx))); |
a157febd | 866 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 867 | warning (0, "stack limit expression is not supported"); |
a157febd | 868 | } |
01bbf777 | 869 | |
a89e3f21 | 870 | if (current_frame.reg_no <= 2) |
79e68feb RS |
871 | { |
872 | /* Store each separately in the same order moveml uses. | |
873 | Using two movel instructions instead of a single moveml | |
874 | is about 15% faster for the 68020 and 68030 at no expense | |
97c55091 | 875 | in code size. */ |
79e68feb RS |
876 | |
877 | int i; | |
878 | ||
3d74bc09 BI |
879 | for (i = 0; i < 16; i++) |
880 | if (current_frame.reg_rev_mask & (1 << i)) | |
078e983e | 881 | { |
a0a7fbc9 AS |
882 | asm_fprintf (stream, (MOTOROLA |
883 | ? "\t%Omove.l %s,-(%Rsp)\n" | |
884 | : "\tmovel %s,%Rsp@-\n"), | |
885 | M68K_REGNAME (15 - i)); | |
078e983e AS |
886 | if (dwarf2out_do_frame ()) |
887 | { | |
f5c4bc60 | 888 | char *l = (char *) dwarf2out_cfi_label (); |
a7cc7f29 | 889 | |
ed311a33 | 890 | cfa_offset += 4; |
01bbf777 AS |
891 | if (! frame_pointer_needed) |
892 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); | |
893 | dwarf2out_reg_save (l, 15 - i, -cfa_offset); | |
078e983e AS |
894 | } |
895 | } | |
79e68feb | 896 | } |
3d74bc09 | 897 | else if (current_frame.reg_rev_mask) |
79e68feb | 898 | { |
9425fb04 | 899 | if (TARGET_COLDFIRE) |
01bbf777 | 900 | /* The ColdFire does not support the predecrement form of the |
e6d98cb0 BI |
901 | MOVEM instruction, so we must adjust the stack pointer and |
902 | then use the plain address register indirect mode. | |
903 | The required register save space was combined earlier with | |
904 | the fsize_with_regs amount. */ | |
905 | ||
a0a7fbc9 AS |
906 | asm_fprintf (stream, (MOTOROLA |
907 | ? "\tmovm.l %I0x%x,(%Rsp)\n" | |
908 | : "\tmoveml %I0x%x,%Rsp@\n"), | |
e6d98cb0 | 909 | current_frame.reg_mask); |
afaff477 | 910 | else |
a0a7fbc9 AS |
911 | asm_fprintf (stream, (MOTOROLA |
912 | ? "\tmovm.l %I0x%x,-(%Rsp)\n" | |
913 | : "\tmoveml %I0x%x,%Rsp@-\n"), | |
e6d98cb0 | 914 | current_frame.reg_rev_mask); |
078e983e AS |
915 | if (dwarf2out_do_frame ()) |
916 | { | |
f5c4bc60 | 917 | char *l = (char *) dwarf2out_cfi_label (); |
3d74bc09 | 918 | int n_regs, regno; |
a7cc7f29 | 919 | |
3d74bc09 | 920 | cfa_offset += current_frame.reg_no * 4; |
078e983e | 921 | if (! frame_pointer_needed) |
ed311a33 | 922 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); |
078e983e | 923 | for (regno = 0, n_regs = 0; regno < 16; regno++) |
3d74bc09 | 924 | if (current_frame.reg_mask & (1 << regno)) |
57047680 | 925 | dwarf2out_reg_save (l, regno, -cfa_offset + n_regs++ * 4); |
078e983e | 926 | } |
79e68feb | 927 | } |
a0a7fbc9 AS |
928 | if (!TARGET_SEP_DATA && flag_pic |
929 | && (current_function_uses_pic_offset_table | |
930 | || (!current_function_is_leaf && TARGET_ID_SHARED_LIBRARY))) | |
79e68feb | 931 | { |
a2ef3db7 BI |
932 | if (TARGET_ID_SHARED_LIBRARY) |
933 | { | |
934 | asm_fprintf (stream, "\tmovel %s@(%s), %s\n", | |
a0a7fbc9 | 935 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
a2ef3db7 | 936 | m68k_library_id_string, |
a0a7fbc9 | 937 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
a2ef3db7 BI |
938 | } |
939 | else | |
940 | { | |
e6d98cb0 | 941 | if (MOTOROLA) |
a0a7fbc9 AS |
942 | asm_fprintf (stream, |
943 | "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", | |
944 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 BI |
945 | else |
946 | { | |
947 | asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n", | |
a0a7fbc9 | 948 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); |
e6d98cb0 | 949 | asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", |
a0a7fbc9 AS |
950 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM), |
951 | M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM)); | |
e6d98cb0 | 952 | } |
a2ef3db7 | 953 | } |
79e68feb RS |
954 | } |
955 | } | |
956 | \f | |
957 | /* Return true if this function's epilogue can be output as RTL. */ | |
958 | ||
3d74bc09 BI |
959 | bool |
960 | use_return_insn (void) | |
79e68feb | 961 | { |
79e68feb | 962 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 963 | return false; |
125ed86f | 964 | |
3d74bc09 BI |
965 | /* We can output the epilogue as RTL only if no registers need to be |
966 | restored. */ | |
a0a7fbc9 | 967 | m68k_compute_frame_layout (); |
3d74bc09 | 968 | return current_frame.reg_no ? false : true; |
79e68feb RS |
969 | } |
970 | ||
971 | /* This function generates the assembly code for function exit, | |
08c148a8 | 972 | on machines that need it. |
79e68feb RS |
973 | |
974 | The function epilogue should not depend on the current stack pointer! | |
975 | It should use the frame pointer only, if there is a frame pointer. | |
976 | This is mandatory because of alloca; we also take advantage of it to | |
977 | omit stack adjustments before returning. */ | |
978 | ||
08c148a8 | 979 | static void |
a0a7fbc9 AS |
980 | m68k_output_function_epilogue (FILE *stream, |
981 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
08c148a8 | 982 | { |
3d74bc09 BI |
983 | HOST_WIDE_INT fsize, fsize_with_regs; |
984 | bool big = false; | |
985 | bool restore_from_sp = false; | |
79e68feb | 986 | rtx insn = get_last_insn (); |
3d74bc09 | 987 | |
a0a7fbc9 | 988 | m68k_compute_frame_layout (); |
3d74bc09 | 989 | |
79e68feb RS |
990 | /* If the last insn was a BARRIER, we don't have to write any code. */ |
991 | if (GET_CODE (insn) == NOTE) | |
992 | insn = prev_nonnote_insn (insn); | |
993 | if (insn && GET_CODE (insn) == BARRIER) | |
cffd0d74 RS |
994 | { |
995 | /* Output just a no-op so that debuggers don't get confused | |
996 | about which function the pc is in at this address. */ | |
761c70aa | 997 | fprintf (stream, "\tnop\n"); |
cffd0d74 RS |
998 | return; |
999 | } | |
79e68feb RS |
1000 | |
1001 | #ifdef FUNCTION_EXTRA_EPILOGUE | |
1002 | FUNCTION_EXTRA_EPILOGUE (stream, size); | |
1003 | #endif | |
3d74bc09 BI |
1004 | |
1005 | fsize = current_frame.size; | |
1006 | ||
a0a7fbc9 | 1007 | /* FIXME: leaf_function_p below is too strong. |
c67ddce5 | 1008 | What we really need to know there is if there could be pending |
7a1929e1 | 1009 | stack adjustment needed at that point. */ |
a0a7fbc9 AS |
1010 | restore_from_sp |
1011 | = (! frame_pointer_needed | |
1012 | || (! current_function_calls_alloca && leaf_function_p ())); | |
860c4900 BI |
1013 | |
1014 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1015 | popping the frame. */ |
860c4900 BI |
1016 | fsize_with_regs = fsize; |
1017 | ||
1018 | /* Because the ColdFire doesn't support moveml with | |
1019 | complex address modes, we must adjust the stack manually | |
1020 | after restoring registers. When the frame pointer isn't used, | |
1021 | we can merge movem adjustment into frame unlinking | |
97c55091 | 1022 | made immediately after it. */ |
dcc21c4c PB |
1023 | if (TARGET_COLDFIRE && restore_from_sp) |
1024 | { | |
1025 | if (current_frame.reg_no > 2) | |
1026 | fsize_with_regs += current_frame.reg_no * 4; | |
1027 | if (current_frame.fpu_no) | |
1028 | fsize_with_regs += current_frame.fpu_no * 8; | |
1029 | } | |
860c4900 | 1030 | |
3d74bc09 | 1031 | if (current_frame.offset + fsize >= 0x8000 |
6910dd70 | 1032 | && ! restore_from_sp |
3d74bc09 | 1033 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1034 | { |
860c4900 | 1035 | /* Because the ColdFire doesn't support moveml with |
97c55091 | 1036 | complex address modes we make an extra correction here. */ |
860c4900 | 1037 | if (TARGET_COLDFIRE) |
e6d98cb0 | 1038 | fsize += current_frame.offset; |
860c4900 | 1039 | |
e6d98cb0 | 1040 | asm_fprintf (stream, "\t%Omove" ASM_DOT "l %I%wd,%Ra1\n", -fsize); |
3d74bc09 | 1041 | fsize = 0, big = true; |
79e68feb | 1042 | } |
3d74bc09 | 1043 | if (current_frame.reg_no <= 2) |
79e68feb RS |
1044 | { |
1045 | /* Restore each separately in the same order moveml does. | |
1046 | Using two movel instructions instead of a single moveml | |
1047 | is about 15% faster for the 68020 and 68030 at no expense | |
7a1929e1 | 1048 | in code size. */ |
79e68feb RS |
1049 | |
1050 | int i; | |
3d74bc09 | 1051 | HOST_WIDE_INT offset = current_frame.offset + fsize; |
79e68feb | 1052 | |
3d74bc09 BI |
1053 | for (i = 0; i < 16; i++) |
1054 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb RS |
1055 | { |
1056 | if (big) | |
1057 | { | |
e6d98cb0 BI |
1058 | if (MOTOROLA) |
1059 | asm_fprintf (stream, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n", | |
1060 | offset, | |
a0a7fbc9 AS |
1061 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1062 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1063 | else |
1064 | asm_fprintf (stream, "\tmovel %s@(-%wd,%Ra1:l),%s\n", | |
a0a7fbc9 | 1065 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1066 | offset, |
a0a7fbc9 | 1067 | M68K_REGNAME (i)); |
79e68feb | 1068 | } |
6910dd70 | 1069 | else if (restore_from_sp) |
a0a7fbc9 AS |
1070 | asm_fprintf (stream, (MOTOROLA |
1071 | ? "\t%Omove.l (%Rsp)+,%s\n" | |
1072 | : "\tmovel %Rsp@+,%s\n"), | |
1073 | M68K_REGNAME (i)); | |
79e68feb RS |
1074 | else |
1075 | { | |
e6d98cb0 BI |
1076 | if (MOTOROLA) |
1077 | asm_fprintf (stream, "\t%Omove.l -%wd(%s),%s\n", | |
1078 | offset, | |
a0a7fbc9 AS |
1079 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
1080 | M68K_REGNAME (i)); | |
e6d98cb0 BI |
1081 | else |
1082 | asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n", | |
a0a7fbc9 | 1083 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 | 1084 | offset, |
a0a7fbc9 | 1085 | M68K_REGNAME (i)); |
79e68feb | 1086 | } |
3d74bc09 | 1087 | offset -= 4; |
79e68feb RS |
1088 | } |
1089 | } | |
3d74bc09 | 1090 | else if (current_frame.reg_mask) |
79e68feb | 1091 | { |
a0a7fbc9 AS |
1092 | /* The ColdFire requires special handling due to its limited moveml |
1093 | insn. */ | |
860c4900 BI |
1094 | if (TARGET_COLDFIRE) |
1095 | { | |
1096 | if (big) | |
1097 | { | |
e6d98cb0 | 1098 | asm_fprintf (stream, "\tadd" ASM_DOT "l %s,%Ra1\n", |
a0a7fbc9 AS |
1099 | M68K_REGNAME (FRAME_POINTER_REGNUM)); |
1100 | asm_fprintf (stream, (MOTOROLA | |
1101 | ? "\tmovm.l (%Ra1),%I0x%x\n" | |
1102 | : "\tmoveml %Ra1@,%I0x%x\n"), | |
e6d98cb0 | 1103 | current_frame.reg_mask); |
860c4900 BI |
1104 | } |
1105 | else if (restore_from_sp) | |
a0a7fbc9 AS |
1106 | asm_fprintf (stream, (MOTOROLA |
1107 | ? "\tmovm.l (%Rsp),%I0x%x\n" | |
1108 | : "\tmoveml %Rsp@,%I0x%x\n"), | |
e6d98cb0 | 1109 | current_frame.reg_mask); |
860c4900 BI |
1110 | else |
1111 | { | |
e6d98cb0 BI |
1112 | if (MOTOROLA) |
1113 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1114 | current_frame.offset + fsize, | |
a0a7fbc9 | 1115 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1116 | current_frame.reg_mask); |
1117 | else | |
1118 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1119 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1120 | current_frame.offset + fsize, |
1121 | current_frame.reg_mask); | |
860c4900 BI |
1122 | } |
1123 | } | |
1124 | else /* !TARGET_COLDFIRE */ | |
79e68feb | 1125 | { |
860c4900 BI |
1126 | if (big) |
1127 | { | |
e6d98cb0 BI |
1128 | if (MOTOROLA) |
1129 | asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n", | |
1130 | current_frame.offset + fsize, | |
a0a7fbc9 | 1131 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1132 | current_frame.reg_mask); |
1133 | else | |
1134 | asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1135 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1136 | current_frame.offset + fsize, |
1137 | current_frame.reg_mask); | |
860c4900 BI |
1138 | } |
1139 | else if (restore_from_sp) | |
1140 | { | |
a0a7fbc9 AS |
1141 | asm_fprintf (stream, (MOTOROLA |
1142 | ? "\tmovm.l (%Rsp)+,%I0x%x\n" | |
1143 | : "\tmoveml %Rsp@+,%I0x%x\n"), | |
3d74bc09 | 1144 | current_frame.reg_mask); |
860c4900 BI |
1145 | } |
1146 | else | |
1147 | { | |
e6d98cb0 BI |
1148 | if (MOTOROLA) |
1149 | asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n", | |
1150 | current_frame.offset + fsize, | |
a0a7fbc9 | 1151 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1152 | current_frame.reg_mask); |
1153 | else | |
1154 | asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1155 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1156 | current_frame.offset + fsize, |
1157 | current_frame.reg_mask); | |
860c4900 | 1158 | } |
79e68feb RS |
1159 | } |
1160 | } | |
3d74bc09 | 1161 | if (current_frame.fpu_rev_mask) |
79e68feb RS |
1162 | { |
1163 | if (big) | |
1164 | { | |
dcc21c4c PB |
1165 | if (TARGET_COLDFIRE) |
1166 | { | |
1167 | if (current_frame.reg_no) | |
1168 | asm_fprintf (stream, MOTOROLA ? | |
1169 | "\tfmovem.d %d(%Ra1),%I0x%x\n" : | |
1170 | "\tfmovmd (%d,%Ra1),%I0x%x\n", | |
1171 | current_frame.reg_no * 4, | |
1172 | current_frame.fpu_rev_mask); | |
1173 | else | |
1174 | asm_fprintf (stream, MOTOROLA ? | |
1175 | "\tfmovem.d (%Ra1),%I0x%x\n" : | |
1176 | "\tfmovmd (%Ra1),%I0x%x\n", | |
1177 | current_frame.fpu_rev_mask); | |
1178 | } | |
1179 | else if (MOTOROLA) | |
e6d98cb0 BI |
1180 | asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n", |
1181 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1182 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1183 | current_frame.fpu_rev_mask); |
1184 | else | |
1185 | asm_fprintf (stream, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n", | |
a0a7fbc9 | 1186 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1187 | current_frame.foffset + fsize, |
1188 | current_frame.fpu_rev_mask); | |
79e68feb | 1189 | } |
6910dd70 | 1190 | else if (restore_from_sp) |
79e68feb | 1191 | { |
dcc21c4c PB |
1192 | if (TARGET_COLDFIRE) |
1193 | { | |
1194 | int offset; | |
1195 | ||
884b74f0 AS |
1196 | /* Stack already has registers in it. Find the offset from |
1197 | the bottom of stack to where the FP registers go. */ | |
dcc21c4c PB |
1198 | if (current_frame.reg_no <= 2) |
1199 | offset = 0; | |
1200 | else | |
1201 | offset = current_frame.reg_no * 4; | |
1202 | if (offset) | |
884b74f0 AS |
1203 | asm_fprintf (stream, |
1204 | "\tfmovem %Rsp@(%d), %I0x%x\n", | |
dcc21c4c PB |
1205 | offset, current_frame.fpu_rev_mask); |
1206 | else | |
884b74f0 | 1207 | asm_fprintf (stream, |
dcc21c4c PB |
1208 | "\tfmovem %Rsp@, %I0x%x\n", |
1209 | current_frame.fpu_rev_mask); | |
1210 | } | |
884b74f0 AS |
1211 | else |
1212 | asm_fprintf (stream, MOTOROLA ? | |
1213 | "\tfmovm (%Rsp)+,%I0x%x\n" : | |
1214 | "\tfmovem %Rsp@+,%I0x%x\n", | |
1215 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1216 | } |
1217 | else | |
1218 | { | |
dcc21c4c | 1219 | if (MOTOROLA && !TARGET_COLDFIRE) |
e6d98cb0 BI |
1220 | asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n", |
1221 | current_frame.foffset + fsize, | |
a0a7fbc9 | 1222 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1223 | current_frame.fpu_rev_mask); |
1224 | else | |
1225 | asm_fprintf (stream, "\tfmovem %s@(-%wd),%I0x%x\n", | |
a0a7fbc9 | 1226 | M68K_REGNAME (FRAME_POINTER_REGNUM), |
e6d98cb0 BI |
1227 | current_frame.foffset + fsize, |
1228 | current_frame.fpu_rev_mask); | |
79e68feb RS |
1229 | } |
1230 | } | |
79e68feb | 1231 | if (frame_pointer_needed) |
a0a7fbc9 | 1232 | fprintf (stream, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM)); |
860c4900 | 1233 | else if (fsize_with_regs) |
79e68feb | 1234 | { |
860c4900 | 1235 | if (fsize_with_regs <= 8) |
79e68feb | 1236 | { |
9425fb04 | 1237 | if (!TARGET_COLDFIRE) |
e6d98cb0 BI |
1238 | asm_fprintf (stream, "\taddq" ASM_DOT "w %I%wd,%Rsp\n", |
1239 | fsize_with_regs); | |
1240 | else | |
1241 | asm_fprintf (stream, "\taddq" ASM_DOT "l %I%wd,%Rsp\n", | |
1242 | fsize_with_regs); | |
7bc88d49 | 1243 | } |
fe95f2f7 | 1244 | else if (fsize_with_regs <= 16 && TUNE_CPU32) |
7bc88d49 RK |
1245 | { |
1246 | /* On the CPU32 it is faster to use two addqw instructions to | |
7a1929e1 | 1247 | add a small integer (8 < N <= 16) to a register. */ |
a0a7fbc9 AS |
1248 | asm_fprintf (stream, |
1249 | "\taddq" ASM_DOT "w %I8,%Rsp\n" | |
1250 | "\taddq" ASM_DOT "w %I%wd,%Rsp\n", | |
860c4900 | 1251 | fsize_with_regs - 8); |
7bc88d49 | 1252 | } |
860c4900 | 1253 | else if (fsize_with_regs < 0x8000) |
7bc88d49 | 1254 | { |
fe95f2f7 | 1255 | if (TUNE_68040) |
e6d98cb0 BI |
1256 | asm_fprintf (stream, "\tadd" ASM_DOT "w %I%wd,%Rsp\n", |
1257 | fsize_with_regs); | |
7bc88d49 | 1258 | else |
a0a7fbc9 AS |
1259 | asm_fprintf (stream, (MOTOROLA |
1260 | ? "\tlea (%wd,%Rsp),%Rsp\n" | |
1261 | : "\tlea %Rsp@(%wd),%Rsp\n"), | |
e6d98cb0 | 1262 | fsize_with_regs); |
79e68feb RS |
1263 | } |
1264 | else | |
e6d98cb0 | 1265 | asm_fprintf (stream, "\tadd" ASM_DOT "l %I%wd,%Rsp\n", fsize_with_regs); |
79e68feb | 1266 | } |
2cff4a6e | 1267 | if (current_function_calls_eh_return) |
a0a7fbc9 | 1268 | asm_fprintf (stream, "\tadd" ASM_DOT "l %Ra0,%Rsp\n"); |
3d74bc09 | 1269 | if (m68k_interrupt_function_p (current_function_decl)) |
48ed72a4 PB |
1270 | fprintf (stream, "\trte\n"); |
1271 | else if (current_function_pops_args) | |
1f85a612 | 1272 | asm_fprintf (stream, "\trtd %I%d\n", current_function_pops_args); |
79e68feb RS |
1273 | else |
1274 | fprintf (stream, "\trts\n"); | |
1275 | } | |
1276 | \f | |
8a4a2253 | 1277 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1278 | instruction. |
1279 | ||
1280 | Note it rejects floating point comparison operators. | |
1281 | (In the future we could use Fdbcc). | |
1282 | ||
1283 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1284 | ||
1285 | int | |
41b6a5e2 | 1286 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1287 | { |
64a184e9 RS |
1288 | switch (GET_CODE (x)) |
1289 | { | |
64a184e9 RS |
1290 | case EQ: case NE: case GTU: case LTU: |
1291 | case GEU: case LEU: | |
1292 | return 1; | |
1293 | ||
1294 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1295 | conservative */ | |
1296 | case GT: case LT: case GE: case LE: | |
1297 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1298 | default: | |
1299 | return 0; | |
1300 | } | |
1301 | } | |
1302 | ||
a0ab749a | 1303 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1304 | int |
8a4a2253 | 1305 | flags_in_68881 (void) |
6a0f85e3 TG |
1306 | { |
1307 | /* We could add support for these in the future */ | |
1308 | return cc_status.flags & CC_IN_68881; | |
1309 | } | |
1310 | ||
a2ef3db7 BI |
1311 | /* Output a BSR instruction suitable for PIC code. */ |
1312 | void | |
a0a7fbc9 | 1313 | m68k_output_pic_call (rtx dest) |
a2ef3db7 BI |
1314 | { |
1315 | const char *out; | |
1316 | ||
1317 | if (!(GET_CODE (dest) == MEM && GET_CODE (XEXP (dest, 0)) == SYMBOL_REF)) | |
1318 | out = "jsr %0"; | |
33827630 PB |
1319 | /* We output a BSR instruction if we're building for a target that |
1320 | supports long branches. Otherwise we generate one of two sequences: | |
a0a7fbc9 AS |
1321 | a shorter one that uses a GOT entry or a longer one that doesn't. |
1322 | We'll use the -Os command-line flag to decide which to generate. | |
1323 | Both sequences take the same time to execute on the ColdFire. */ | |
a2ef3db7 BI |
1324 | else if (TARGET_PCREL) |
1325 | out = "bsr.l %o0"; | |
33827630 | 1326 | else if (TARGET_68020) |
1f0282cb | 1327 | #if defined(USE_GAS) |
a2ef3db7 BI |
1328 | out = "bsr.l %0@PLTPC"; |
1329 | #else | |
1330 | out = "bsr %0@PLTPC"; | |
1331 | #endif | |
1332 | else if (optimize_size || TARGET_ID_SHARED_LIBRARY) | |
1333 | out = "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)"; | |
1334 | else | |
1335 | out = "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)"; | |
1336 | ||
a0a7fbc9 | 1337 | output_asm_insn (out, &dest); |
a2ef3db7 BI |
1338 | } |
1339 | ||
64a184e9 RS |
1340 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1341 | floating point version of this sequence (Fdbcc). We also | |
1342 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1343 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1344 | kick those out before we get here. */ | |
64a184e9 | 1345 | |
1d8eaa6b | 1346 | void |
8a4a2253 | 1347 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1348 | { |
64a184e9 RS |
1349 | switch (GET_CODE (operands[3])) |
1350 | { | |
1351 | case EQ: | |
a0a7fbc9 AS |
1352 | output_asm_insn (MOTOROLA |
1353 | ? "dbeq %0,%l1\n\tjbeq %l2" | |
1354 | : "dbeq %0,%l1\n\tjeq %l2", | |
e6d98cb0 BI |
1355 | operands); |
1356 | break; | |
64a184e9 RS |
1357 | |
1358 | case NE: | |
a0a7fbc9 AS |
1359 | output_asm_insn (MOTOROLA |
1360 | ? "dbne %0,%l1\n\tjbne %l2" | |
1361 | : "dbne %0,%l1\n\tjne %l2", | |
e6d98cb0 BI |
1362 | operands); |
1363 | break; | |
64a184e9 RS |
1364 | |
1365 | case GT: | |
a0a7fbc9 AS |
1366 | output_asm_insn (MOTOROLA |
1367 | ? "dbgt %0,%l1\n\tjbgt %l2" | |
1368 | : "dbgt %0,%l1\n\tjgt %l2", | |
e6d98cb0 BI |
1369 | operands); |
1370 | break; | |
64a184e9 RS |
1371 | |
1372 | case GTU: | |
a0a7fbc9 AS |
1373 | output_asm_insn (MOTOROLA |
1374 | ? "dbhi %0,%l1\n\tjbhi %l2" | |
1375 | : "dbhi %0,%l1\n\tjhi %l2", | |
e6d98cb0 BI |
1376 | operands); |
1377 | break; | |
64a184e9 RS |
1378 | |
1379 | case LT: | |
a0a7fbc9 AS |
1380 | output_asm_insn (MOTOROLA |
1381 | ? "dblt %0,%l1\n\tjblt %l2" | |
1382 | : "dblt %0,%l1\n\tjlt %l2", | |
e6d98cb0 BI |
1383 | operands); |
1384 | break; | |
64a184e9 RS |
1385 | |
1386 | case LTU: | |
a0a7fbc9 AS |
1387 | output_asm_insn (MOTOROLA |
1388 | ? "dbcs %0,%l1\n\tjbcs %l2" | |
1389 | : "dbcs %0,%l1\n\tjcs %l2", | |
e6d98cb0 BI |
1390 | operands); |
1391 | break; | |
64a184e9 RS |
1392 | |
1393 | case GE: | |
a0a7fbc9 AS |
1394 | output_asm_insn (MOTOROLA |
1395 | ? "dbge %0,%l1\n\tjbge %l2" | |
1396 | : "dbge %0,%l1\n\tjge %l2", | |
e6d98cb0 BI |
1397 | operands); |
1398 | break; | |
64a184e9 RS |
1399 | |
1400 | case GEU: | |
a0a7fbc9 AS |
1401 | output_asm_insn (MOTOROLA |
1402 | ? "dbcc %0,%l1\n\tjbcc %l2" | |
1403 | : "dbcc %0,%l1\n\tjcc %l2", | |
e6d98cb0 BI |
1404 | operands); |
1405 | break; | |
64a184e9 RS |
1406 | |
1407 | case LE: | |
a0a7fbc9 AS |
1408 | output_asm_insn (MOTOROLA |
1409 | ? "dble %0,%l1\n\tjble %l2" | |
1410 | : "dble %0,%l1\n\tjle %l2", | |
e6d98cb0 BI |
1411 | operands); |
1412 | break; | |
64a184e9 RS |
1413 | |
1414 | case LEU: | |
a0a7fbc9 AS |
1415 | output_asm_insn (MOTOROLA |
1416 | ? "dbls %0,%l1\n\tjbls %l2" | |
1417 | : "dbls %0,%l1\n\tjls %l2", | |
e6d98cb0 BI |
1418 | operands); |
1419 | break; | |
64a184e9 RS |
1420 | |
1421 | default: | |
4761e388 | 1422 | gcc_unreachable (); |
64a184e9 RS |
1423 | } |
1424 | ||
1425 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1426 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1427 | switch (GET_MODE (operands[0])) |
1428 | { | |
1429 | case SImode: | |
a0a7fbc9 AS |
1430 | output_asm_insn (MOTOROLA |
1431 | ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" | |
1432 | : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1433 | operands); |
64a184e9 RS |
1434 | break; |
1435 | ||
1436 | case HImode: | |
1437 | break; | |
1438 | ||
1439 | default: | |
4761e388 | 1440 | gcc_unreachable (); |
64a184e9 RS |
1441 | } |
1442 | } | |
1443 | ||
5505f548 | 1444 | const char * |
4761e388 | 1445 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1446 | { |
1447 | rtx loperands[7]; | |
d9832fd2 | 1448 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1449 | |
f710504c | 1450 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1451 | CC_STATUS_INIT; |
1452 | ||
d9832fd2 RK |
1453 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1454 | below. Swap the operands and change the op if these requirements | |
1455 | are not fulfilled. */ | |
1456 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1457 | { | |
1458 | rtx tmp = operand1; | |
1459 | ||
1460 | operand1 = operand2; | |
1461 | operand2 = tmp; | |
1462 | op_code = swap_condition (op_code); | |
1463 | } | |
c59c3b1c RK |
1464 | loperands[0] = operand1; |
1465 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1466 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1467 | else |
b72f00af | 1468 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1469 | if (operand2 != const0_rtx) |
1470 | { | |
1471 | loperands[2] = operand2; | |
1472 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1473 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1474 | else |
b72f00af | 1475 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1476 | } |
428511bb | 1477 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1478 | if (operand2 != const0_rtx) |
4a8c52e0 | 1479 | { |
a0a7fbc9 AS |
1480 | output_asm_insn (MOTOROLA |
1481 | ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" | |
1482 | : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1483 | loperands); | |
4a8c52e0 | 1484 | } |
392582fa | 1485 | else |
4a8c52e0 | 1486 | { |
9425fb04 | 1487 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1488 | output_asm_insn ("tst%.l %0", loperands); |
1489 | else | |
a0a7fbc9 | 1490 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1491 | |
e6d98cb0 | 1492 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1493 | |
9425fb04 | 1494 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1495 | output_asm_insn ("tst%.l %1", loperands); |
1496 | else | |
3b4b85c9 | 1497 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1498 | } |
1499 | ||
c59c3b1c | 1500 | loperands[5] = dest; |
3b4b85c9 | 1501 | |
d9832fd2 | 1502 | switch (op_code) |
c59c3b1c RK |
1503 | { |
1504 | case EQ: | |
4977bab6 | 1505 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1506 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1507 | output_asm_insn ("seq %5", loperands); |
1508 | break; | |
1509 | ||
1510 | case NE: | |
4977bab6 | 1511 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1512 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1513 | output_asm_insn ("sne %5", loperands); |
1514 | break; | |
1515 | ||
1516 | case GT: | |
428511bb | 1517 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1518 | output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6", |
e6d98cb0 | 1519 | loperands); |
4977bab6 | 1520 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1521 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1522 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1523 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1524 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1525 | break; |
1526 | ||
1527 | case GTU: | |
4977bab6 | 1528 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1529 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1530 | output_asm_insn ("shi %5", loperands); |
1531 | break; | |
1532 | ||
1533 | case LT: | |
428511bb | 1534 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1535 | output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6", |
e6d98cb0 | 1536 | loperands); |
4977bab6 | 1537 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1538 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1539 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1540 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1541 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1542 | break; |
1543 | ||
1544 | case LTU: | |
4977bab6 | 1545 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1546 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1547 | output_asm_insn ("scs %5", loperands); |
1548 | break; | |
1549 | ||
1550 | case GE: | |
428511bb | 1551 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 AS |
1552 | output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6", |
1553 | loperands); | |
4977bab6 | 1554 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1555 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1556 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1557 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1558 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1559 | break; |
1560 | ||
1561 | case GEU: | |
4977bab6 | 1562 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1563 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1564 | output_asm_insn ("scc %5", loperands); |
1565 | break; | |
1566 | ||
1567 | case LE: | |
428511bb | 1568 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1569 | output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6", |
e6d98cb0 | 1570 | loperands); |
4977bab6 | 1571 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1572 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1573 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1574 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1575 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1576 | break; |
1577 | ||
1578 | case LEU: | |
4977bab6 | 1579 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1580 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1581 | output_asm_insn ("sls %5", loperands); |
1582 | break; | |
1583 | ||
1584 | default: | |
4761e388 | 1585 | gcc_unreachable (); |
c59c3b1c RK |
1586 | } |
1587 | return ""; | |
1588 | } | |
1589 | ||
5505f548 | 1590 | const char * |
8a4a2253 | 1591 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1592 | { |
1593 | operands[0] = countop; | |
1594 | operands[1] = dataop; | |
1595 | ||
1596 | if (GET_CODE (countop) == CONST_INT) | |
1597 | { | |
1598 | register int count = INTVAL (countop); | |
1599 | /* If COUNT is bigger than size of storage unit in use, | |
1600 | advance to the containing unit of same size. */ | |
1601 | if (count > signpos) | |
1602 | { | |
1603 | int offset = (count & ~signpos) / 8; | |
1604 | count = count & signpos; | |
b72f00af | 1605 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1606 | } |
1607 | if (count == signpos) | |
1608 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1609 | else | |
1610 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1611 | ||
1612 | /* These three statements used to use next_insns_test_no... | |
1613 | but it appears that this should do the same job. */ | |
1614 | if (count == 31 | |
1615 | && next_insn_tests_no_inequality (insn)) | |
1616 | return "tst%.l %1"; | |
1617 | if (count == 15 | |
1618 | && next_insn_tests_no_inequality (insn)) | |
1619 | return "tst%.w %1"; | |
1620 | if (count == 7 | |
1621 | && next_insn_tests_no_inequality (insn)) | |
1622 | return "tst%.b %1"; | |
1623 | ||
1624 | cc_status.flags = CC_NOT_NEGATIVE; | |
1625 | } | |
1626 | return "btst %0,%1"; | |
1627 | } | |
79e68feb RS |
1628 | \f |
1629 | /* Legitimize PIC addresses. If the address is already | |
1630 | position-independent, we return ORIG. Newly generated | |
1631 | position-independent addresses go to REG. If we need more | |
1632 | than one register, we lose. | |
1633 | ||
1634 | An address is legitimized by making an indirect reference | |
1635 | through the Global Offset Table with the name of the symbol | |
1636 | used as an offset. | |
1637 | ||
1638 | The assembler and linker are responsible for placing the | |
1639 | address of the symbol in the GOT. The function prologue | |
1640 | is responsible for initializing a5 to the starting address | |
1641 | of the GOT. | |
1642 | ||
1643 | The assembler is also responsible for translating a symbol name | |
1644 | into a constant displacement from the start of the GOT. | |
1645 | ||
1646 | A quick example may make things a little clearer: | |
1647 | ||
1648 | When not generating PIC code to store the value 12345 into _foo | |
1649 | we would generate the following code: | |
1650 | ||
1651 | movel #12345, _foo | |
1652 | ||
1653 | When generating PIC two transformations are made. First, the compiler | |
1654 | loads the address of foo into a register. So the first transformation makes: | |
1655 | ||
1656 | lea _foo, a0 | |
1657 | movel #12345, a0@ | |
1658 | ||
1659 | The code in movsi will intercept the lea instruction and call this | |
1660 | routine which will transform the instructions into: | |
1661 | ||
1662 | movel a5@(_foo:w), a0 | |
1663 | movel #12345, a0@ | |
1664 | ||
1665 | ||
1666 | That (in a nutshell) is how *all* symbol and label references are | |
1667 | handled. */ | |
1668 | ||
1669 | rtx | |
8a4a2253 BI |
1670 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1671 | rtx reg) | |
79e68feb RS |
1672 | { |
1673 | rtx pic_ref = orig; | |
1674 | ||
1675 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1676 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1677 | { | |
4761e388 | 1678 | gcc_assert (reg); |
79e68feb | 1679 | |
1d8eaa6b AS |
1680 | pic_ref = gen_rtx_MEM (Pmode, |
1681 | gen_rtx_PLUS (Pmode, | |
1682 | pic_offset_table_rtx, orig)); | |
79e68feb | 1683 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 1684 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
1685 | emit_move_insn (reg, pic_ref); |
1686 | return reg; | |
1687 | } | |
1688 | else if (GET_CODE (orig) == CONST) | |
1689 | { | |
1d8eaa6b | 1690 | rtx base; |
79e68feb | 1691 | |
b2e08ed4 | 1692 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
1693 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
1694 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1695 | return orig; | |
1696 | ||
4761e388 | 1697 | gcc_assert (reg); |
79e68feb RS |
1698 | |
1699 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
1700 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
1701 | ||
1702 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
1703 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
1704 | base == reg ? 0 : reg); | |
79e68feb RS |
1705 | |
1706 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 1707 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 1708 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
1709 | /* Likewise, should we set special REG_NOTEs here? */ |
1710 | } | |
1711 | return pic_ref; | |
1712 | } | |
1713 | ||
1714 | \f | |
28bad6d1 | 1715 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 1716 | |
8a4a2253 | 1717 | static CONST_METHOD const_method (rtx); |
5505f548 | 1718 | |
a0a7fbc9 | 1719 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 1720 | |
5505f548 | 1721 | static CONST_METHOD |
8a4a2253 | 1722 | const_method (rtx constant) |
0ce6f9fb RK |
1723 | { |
1724 | int i; | |
1725 | unsigned u; | |
1726 | ||
1727 | i = INTVAL (constant); | |
6910dd70 | 1728 | if (USE_MOVQ (i)) |
0ce6f9fb | 1729 | return MOVQ; |
24092242 | 1730 | |
c16eadc7 | 1731 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 1732 | /* FIXME: This may not be useful for the m68060 either. */ |
9425fb04 | 1733 | if (!TARGET_COLDFIRE) |
24092242 RK |
1734 | { |
1735 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 1736 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
1737 | if (USE_MOVQ (i ^ 0xff)) |
1738 | return NOTB; | |
1739 | /* Likewise, try with not.w */ | |
1740 | if (USE_MOVQ (i ^ 0xffff)) | |
1741 | return NOTW; | |
1742 | /* This is the only value where neg.w is useful */ | |
1743 | if (i == -65408) | |
1744 | return NEGW; | |
24092242 | 1745 | } |
28bad6d1 | 1746 | |
5e04daf3 PB |
1747 | /* Try also with swap. */ |
1748 | u = i; | |
1749 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
1750 | return SWAP; | |
1751 | ||
986e74d5 | 1752 | if (TARGET_ISAB) |
28bad6d1 | 1753 | { |
72edf146 | 1754 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
1755 | if (i >= 0 && i <= 65535) |
1756 | return MVZ; | |
1757 | if (i >= -32768 && i <= 32767) | |
1758 | return MVS; | |
1759 | } | |
1760 | ||
0ce6f9fb RK |
1761 | /* Otherwise, use move.l */ |
1762 | return MOVL; | |
1763 | } | |
1764 | ||
3c50106f | 1765 | static int |
8a4a2253 | 1766 | const_int_cost (rtx constant) |
0ce6f9fb RK |
1767 | { |
1768 | switch (const_method (constant)) | |
1769 | { | |
a0a7fbc9 AS |
1770 | case MOVQ: |
1771 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
1772 | return 0; | |
1773 | case MVZ: | |
1774 | case MVS: | |
1775 | case NOTB: | |
1776 | case NOTW: | |
1777 | case NEGW: | |
1778 | case SWAP: | |
1779 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
1780 | return 1; | |
1781 | case MOVL: | |
1782 | return 2; | |
1783 | default: | |
1784 | gcc_unreachable (); | |
0ce6f9fb RK |
1785 | } |
1786 | } | |
1787 | ||
3c50106f | 1788 | static bool |
8a4a2253 | 1789 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1790 | { |
1791 | switch (code) | |
1792 | { | |
1793 | case CONST_INT: | |
1794 | /* Constant zero is super cheap due to clr instruction. */ | |
1795 | if (x == const0_rtx) | |
1796 | *total = 0; | |
1797 | else | |
1798 | *total = const_int_cost (x); | |
1799 | return true; | |
1800 | ||
1801 | case CONST: | |
1802 | case LABEL_REF: | |
1803 | case SYMBOL_REF: | |
1804 | *total = 3; | |
1805 | return true; | |
1806 | ||
1807 | case CONST_DOUBLE: | |
1808 | /* Make 0.0 cheaper than other floating constants to | |
1809 | encourage creating tstsf and tstdf insns. */ | |
1810 | if (outer_code == COMPARE | |
1811 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
1812 | *total = 4; | |
1813 | else | |
1814 | *total = 5; | |
1815 | return true; | |
1816 | ||
1817 | /* These are vaguely right for a 68020. */ | |
1818 | /* The costs for long multiply have been adjusted to work properly | |
1819 | in synth_mult on the 68020, relative to an average of the time | |
1820 | for add and the time for shift, taking away a little more because | |
1821 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
1822 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
1823 | terms. */ | |
fe95f2f7 JB |
1824 | #define MULL_COST \ |
1825 | (TUNE_68060 ? 2 \ | |
1826 | : TUNE_68040 ? 5 \ | |
1827 | : TUNE_CFV2 ? 10 \ | |
1828 | : TARGET_COLDFIRE ? 3 : 13) | |
1829 | ||
1830 | #define MULW_COST \ | |
1831 | (TUNE_68060 ? 2 \ | |
1832 | : TUNE_68040 ? 3 \ | |
1833 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
1834 | : TARGET_COLDFIRE ? 2 : 8) | |
1835 | ||
1836 | #define DIVW_COST \ | |
1837 | (TARGET_CF_HWDIV ? 11 \ | |
1838 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
1839 | |
1840 | case PLUS: | |
1841 | /* An lea costs about three times as much as a simple add. */ | |
1842 | if (GET_MODE (x) == SImode | |
1843 | && GET_CODE (XEXP (x, 1)) == REG | |
1844 | && GET_CODE (XEXP (x, 0)) == MULT | |
1845 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1846 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1847 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
1848 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
1849 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
1850 | { |
1851 | /* lea an@(dx:l:i),am */ | |
1852 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
1853 | return true; | |
1854 | } | |
3c50106f RH |
1855 | return false; |
1856 | ||
1857 | case ASHIFT: | |
1858 | case ASHIFTRT: | |
1859 | case LSHIFTRT: | |
fe95f2f7 | 1860 | if (TUNE_68060) |
3c50106f RH |
1861 | { |
1862 | *total = COSTS_N_INSNS(1); | |
1863 | return true; | |
1864 | } | |
fe95f2f7 | 1865 | if (TUNE_68000_10) |
3c50106f RH |
1866 | { |
1867 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1868 | { | |
1869 | if (INTVAL (XEXP (x, 1)) < 16) | |
1870 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
1871 | else | |
1872 | /* We're using clrw + swap for these cases. */ | |
1873 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
1874 | } | |
1875 | else | |
a0a7fbc9 | 1876 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
1877 | return true; |
1878 | } | |
1879 | /* A shift by a big integer takes an extra instruction. */ | |
1880 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1881 | && (INTVAL (XEXP (x, 1)) == 16)) | |
1882 | { | |
1883 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
1884 | return true; | |
1885 | } | |
1886 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1887 | && !(INTVAL (XEXP (x, 1)) > 0 | |
1888 | && INTVAL (XEXP (x, 1)) <= 8)) | |
1889 | { | |
eb849993 | 1890 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
1891 | return true; |
1892 | } | |
1893 | return false; | |
1894 | ||
1895 | case MULT: | |
1896 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
1897 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
1898 | && GET_MODE (x) == SImode) | |
1899 | *total = COSTS_N_INSNS (MULW_COST); | |
1900 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1901 | *total = COSTS_N_INSNS (MULW_COST); | |
1902 | else | |
1903 | *total = COSTS_N_INSNS (MULL_COST); | |
1904 | return true; | |
1905 | ||
1906 | case DIV: | |
1907 | case UDIV: | |
1908 | case MOD: | |
1909 | case UMOD: | |
1910 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
1911 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
1912 | else if (TARGET_CF_HWDIV) |
1913 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
1914 | else |
1915 | *total = COSTS_N_INSNS (43); /* div.l */ | |
1916 | return true; | |
1917 | ||
1918 | default: | |
1919 | return false; | |
1920 | } | |
1921 | } | |
1922 | ||
5505f548 | 1923 | const char * |
8a4a2253 | 1924 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb RK |
1925 | { |
1926 | int i; | |
1927 | ||
1928 | i = INTVAL (operands[1]); | |
1929 | switch (const_method (operands[1])) | |
1930 | { | |
28bad6d1 | 1931 | case MVZ: |
28bad6d1 | 1932 | return "mvzw %1,%0"; |
1cbae84f PB |
1933 | case MVS: |
1934 | return "mvsw %1,%0"; | |
a0a7fbc9 | 1935 | case MOVQ: |
0ce6f9fb | 1936 | return "moveq %1,%0"; |
a0a7fbc9 | 1937 | case NOTB: |
66e07510 | 1938 | CC_STATUS_INIT; |
1d8eaa6b | 1939 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 1940 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 1941 | case NOTW: |
66e07510 | 1942 | CC_STATUS_INIT; |
1d8eaa6b | 1943 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 1944 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 1945 | case NEGW: |
66e07510 | 1946 | CC_STATUS_INIT; |
3b4b85c9 | 1947 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 1948 | case SWAP: |
0ce6f9fb RK |
1949 | { |
1950 | unsigned u = i; | |
1951 | ||
1d8eaa6b | 1952 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 1953 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 1954 | } |
a0a7fbc9 | 1955 | case MOVL: |
0ce6f9fb | 1956 | return "move%.l %1,%0"; |
a0a7fbc9 | 1957 | default: |
4761e388 | 1958 | gcc_unreachable (); |
0ce6f9fb RK |
1959 | } |
1960 | } | |
1961 | ||
5e04daf3 PB |
1962 | /* Return 1 if 'constant' can be represented by |
1963 | mov3q on a ColdFire V4 core. */ | |
1964 | int | |
1965 | valid_mov3q_const (rtx constant) | |
1966 | { | |
1967 | int i; | |
1968 | ||
986e74d5 | 1969 | if (TARGET_ISAB && GET_CODE (constant) == CONST_INT) |
5e04daf3 PB |
1970 | { |
1971 | i = INTVAL (constant); | |
a0a7fbc9 | 1972 | if (i == -1 || (i >= 1 && i <= 7)) |
5e04daf3 PB |
1973 | return 1; |
1974 | } | |
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | ||
5505f548 | 1979 | const char * |
8a4a2253 | 1980 | output_move_simode_const (rtx *operands) |
02ed0c07 RK |
1981 | { |
1982 | if (operands[1] == const0_rtx | |
1983 | && (DATA_REG_P (operands[0]) | |
1984 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
1985 | /* clr insns on 68000 read before writing. */ |
1986 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
02ed0c07 RK |
1987 | || !(GET_CODE (operands[0]) == MEM |
1988 | && MEM_VOLATILE_P (operands[0])))) | |
1989 | return "clr%.l %0"; | |
5e04daf3 PB |
1990 | else if ((GET_MODE (operands[0]) == SImode) |
1991 | && valid_mov3q_const (operands[1])) | |
a0a7fbc9 | 1992 | return "mov3q%.l %1,%0"; |
38198304 AS |
1993 | else if (operands[1] == const0_rtx |
1994 | && ADDRESS_REG_P (operands[0])) | |
1995 | return "sub%.l %0,%0"; | |
02ed0c07 RK |
1996 | else if (DATA_REG_P (operands[0])) |
1997 | return output_move_const_into_data_reg (operands); | |
1998 | else if (ADDRESS_REG_P (operands[0]) | |
1999 | && INTVAL (operands[1]) < 0x8000 | |
2000 | && INTVAL (operands[1]) >= -0x8000) | |
5e04daf3 PB |
2001 | { |
2002 | if (valid_mov3q_const (operands[1])) | |
2003 | return "mov3q%.l %1,%0"; | |
2004 | return "move%.w %1,%0"; | |
2005 | } | |
02ed0c07 | 2006 | else if (GET_CODE (operands[0]) == MEM |
a0a7fbc9 AS |
2007 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC |
2008 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
02ed0c07 RK |
2009 | && INTVAL (operands[1]) < 0x8000 |
2010 | && INTVAL (operands[1]) >= -0x8000) | |
5e04daf3 PB |
2011 | { |
2012 | if (valid_mov3q_const (operands[1])) | |
2013 | return "mov3q%.l %1,%-"; | |
2014 | return "pea %a1"; | |
2015 | } | |
02ed0c07 RK |
2016 | return "move%.l %1,%0"; |
2017 | } | |
2018 | ||
5505f548 | 2019 | const char * |
8a4a2253 | 2020 | output_move_simode (rtx *operands) |
f4e80198 RK |
2021 | { |
2022 | if (GET_CODE (operands[1]) == CONST_INT) | |
2023 | return output_move_simode_const (operands); | |
2024 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2025 | || GET_CODE (operands[1]) == CONST) | |
2026 | && push_operand (operands[0], SImode)) | |
2027 | return "pea %a1"; | |
2028 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2029 | || GET_CODE (operands[1]) == CONST) | |
2030 | && ADDRESS_REG_P (operands[0])) | |
2031 | return "lea %a1,%0"; | |
2032 | return "move%.l %1,%0"; | |
2033 | } | |
2034 | ||
5505f548 | 2035 | const char * |
8a4a2253 | 2036 | output_move_himode (rtx *operands) |
f4e80198 RK |
2037 | { |
2038 | if (GET_CODE (operands[1]) == CONST_INT) | |
2039 | { | |
2040 | if (operands[1] == const0_rtx | |
2041 | && (DATA_REG_P (operands[0]) | |
2042 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2043 | /* clr insns on 68000 read before writing. */ |
2044 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2045 | || !(GET_CODE (operands[0]) == MEM |
2046 | && MEM_VOLATILE_P (operands[0])))) | |
2047 | return "clr%.w %0"; | |
38198304 AS |
2048 | else if (operands[1] == const0_rtx |
2049 | && ADDRESS_REG_P (operands[0])) | |
2050 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2051 | else if (DATA_REG_P (operands[0]) |
2052 | && INTVAL (operands[1]) < 128 | |
2053 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2054 | return "moveq %1,%0"; |
f4e80198 RK |
2055 | else if (INTVAL (operands[1]) < 0x8000 |
2056 | && INTVAL (operands[1]) >= -0x8000) | |
2057 | return "move%.w %1,%0"; | |
2058 | } | |
2059 | else if (CONSTANT_P (operands[1])) | |
2060 | return "move%.l %1,%0"; | |
f4e80198 RK |
2061 | /* Recognize the insn before a tablejump, one that refers |
2062 | to a table of offsets. Such an insn will need to refer | |
2063 | to a label on the insn. So output one. Use the label-number | |
2064 | of the table of offsets to generate this label. This code, | |
2065 | and similar code below, assumes that there will be at most one | |
2066 | reference to each table. */ | |
2067 | if (GET_CODE (operands[1]) == MEM | |
2068 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2069 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
2070 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
2071 | { | |
2072 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
2073 | if (MOTOROLA) |
2074 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
2075 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
2076 | else | |
2077 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
a0a7fbc9 | 2078 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); |
f4e80198 | 2079 | } |
f4e80198 RK |
2080 | return "move%.w %1,%0"; |
2081 | } | |
2082 | ||
5505f548 | 2083 | const char * |
8a4a2253 | 2084 | output_move_qimode (rtx *operands) |
f4e80198 | 2085 | { |
102701ff | 2086 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2087 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2088 | |
a0a7fbc9 | 2089 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2090 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2091 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2092 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2093 | && ! ADDRESS_REG_P (operands[1]) | |
2094 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2095 | |
3197c489 | 2096 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2097 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2098 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2099 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2100 | { | |
2101 | if (operands[1] == const0_rtx) | |
2102 | return "clr%.b %0"; | |
9425fb04 | 2103 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2104 | && GET_CODE (operands[1]) == CONST_INT |
2105 | && (INTVAL (operands[1]) & 255) == 255) | |
2106 | { | |
2107 | CC_STATUS_INIT; | |
2108 | return "st %0"; | |
2109 | } | |
2110 | } | |
2111 | if (GET_CODE (operands[1]) == CONST_INT | |
2112 | && DATA_REG_P (operands[0]) | |
2113 | && INTVAL (operands[1]) < 128 | |
2114 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2115 | return "moveq %1,%0"; |
38198304 AS |
2116 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2117 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2118 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2119 | return "move%.l %1,%0"; | |
c16eadc7 | 2120 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2121 | from address registers. */ |
2122 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2123 | return "move%.w %1,%0"; |
2124 | return "move%.b %1,%0"; | |
2125 | } | |
2126 | ||
5505f548 | 2127 | const char * |
8a4a2253 | 2128 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2129 | { |
2130 | if (operands[1] == const0_rtx | |
3197c489 RS |
2131 | /* clr insns on 68000 read before writing. */ |
2132 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2133 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2134 | return "clr%.w %0"; | |
2135 | return "move%.w %1,%0"; | |
2136 | } | |
2137 | ||
5505f548 | 2138 | const char * |
8a4a2253 | 2139 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2140 | { |
2141 | if (operands[1] == const0_rtx | |
3197c489 RS |
2142 | /* clr insns on 68000 read before writing. */ |
2143 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2144 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2145 | return "clr%.b %0"; | |
2146 | return "move%.b %1,%0"; | |
2147 | } | |
2148 | ||
79e68feb RS |
2149 | /* Return the best assembler insn template |
2150 | for moving operands[1] into operands[0] as a fullword. */ | |
2151 | ||
5505f548 | 2152 | static const char * |
8a4a2253 | 2153 | singlemove_string (rtx *operands) |
79e68feb | 2154 | { |
02ed0c07 RK |
2155 | if (GET_CODE (operands[1]) == CONST_INT) |
2156 | return output_move_simode_const (operands); | |
2157 | return "move%.l %1,%0"; | |
79e68feb RS |
2158 | } |
2159 | ||
2505bc97 | 2160 | |
79e68feb RS |
2161 | /* Output assembler code to perform a doubleword move insn |
2162 | with operands OPERANDS. */ | |
2163 | ||
5505f548 | 2164 | const char * |
8a4a2253 | 2165 | output_move_double (rtx *operands) |
79e68feb | 2166 | { |
2505bc97 RS |
2167 | enum |
2168 | { | |
2169 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2170 | } optype0, optype1; | |
79e68feb | 2171 | rtx latehalf[2]; |
2505bc97 | 2172 | rtx middlehalf[2]; |
7f98eeb6 | 2173 | rtx xops[2]; |
79e68feb | 2174 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2175 | int dest_overlapped_low = 0; |
184916bc | 2176 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2177 | |
2178 | middlehalf[0] = 0; | |
2179 | middlehalf[1] = 0; | |
79e68feb RS |
2180 | |
2181 | /* First classify both operands. */ | |
2182 | ||
2183 | if (REG_P (operands[0])) | |
2184 | optype0 = REGOP; | |
2185 | else if (offsettable_memref_p (operands[0])) | |
2186 | optype0 = OFFSOP; | |
2187 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2188 | optype0 = POPOP; | |
2189 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2190 | optype0 = PUSHOP; | |
2191 | else if (GET_CODE (operands[0]) == MEM) | |
2192 | optype0 = MEMOP; | |
2193 | else | |
2194 | optype0 = RNDOP; | |
2195 | ||
2196 | if (REG_P (operands[1])) | |
2197 | optype1 = REGOP; | |
2198 | else if (CONSTANT_P (operands[1])) | |
2199 | optype1 = CNSTOP; | |
2200 | else if (offsettable_memref_p (operands[1])) | |
2201 | optype1 = OFFSOP; | |
2202 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2203 | optype1 = POPOP; | |
2204 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2205 | optype1 = PUSHOP; | |
2206 | else if (GET_CODE (operands[1]) == MEM) | |
2207 | optype1 = MEMOP; | |
2208 | else | |
2209 | optype1 = RNDOP; | |
2210 | ||
4761e388 NS |
2211 | /* Check for the cases that the operand constraints are not supposed |
2212 | to allow to happen. Generating code for these cases is | |
2213 | painful. */ | |
2214 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2215 | |
2216 | /* If one operand is decrementing and one is incrementing | |
2217 | decrement the former register explicitly | |
2218 | and change that operand into ordinary indexing. */ | |
2219 | ||
2220 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2221 | { | |
2222 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 2223 | if (size == 12) |
3b4b85c9 | 2224 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 2225 | else |
3b4b85c9 | 2226 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 2227 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2228 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2229 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2230 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2231 | else |
1d8eaa6b | 2232 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2233 | optype0 = OFFSOP; |
2234 | } | |
2235 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2236 | { | |
2237 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 2238 | if (size == 12) |
3b4b85c9 | 2239 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 2240 | else |
3b4b85c9 | 2241 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 2242 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2243 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2244 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2245 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2246 | else |
1d8eaa6b | 2247 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2248 | optype1 = OFFSOP; |
2249 | } | |
2250 | ||
2251 | /* If an operand is an unoffsettable memory ref, find a register | |
2252 | we can increment temporarily to make it refer to the second word. */ | |
2253 | ||
2254 | if (optype0 == MEMOP) | |
2255 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2256 | ||
2257 | if (optype1 == MEMOP) | |
2258 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2259 | ||
2260 | /* Ok, we can do one word at a time. | |
2261 | Normally we do the low-numbered word first, | |
2262 | but if either operand is autodecrementing then we | |
2263 | do the high-numbered word first. | |
2264 | ||
2265 | In either case, set up in LATEHALF the operands to use | |
2266 | for the high-numbered word and in some cases alter the | |
2267 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2268 | ||
2505bc97 RS |
2269 | if (size == 12) |
2270 | { | |
2271 | if (optype0 == REGOP) | |
2272 | { | |
1d8eaa6b AS |
2273 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2274 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2275 | } |
2276 | else if (optype0 == OFFSOP) | |
2277 | { | |
b72f00af RK |
2278 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2279 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2280 | } |
2281 | else | |
2282 | { | |
2283 | middlehalf[0] = operands[0]; | |
2284 | latehalf[0] = operands[0]; | |
2285 | } | |
2286 | ||
2287 | if (optype1 == REGOP) | |
2288 | { | |
1d8eaa6b AS |
2289 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2290 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2291 | } |
2292 | else if (optype1 == OFFSOP) | |
2293 | { | |
b72f00af RK |
2294 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2295 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2296 | } |
2297 | else if (optype1 == CNSTOP) | |
2298 | { | |
2299 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2300 | { | |
2301 | REAL_VALUE_TYPE r; | |
2302 | long l[3]; | |
2303 | ||
2304 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2305 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2306 | operands[1] = GEN_INT (l[0]); | |
2307 | middlehalf[1] = GEN_INT (l[1]); | |
2308 | latehalf[1] = GEN_INT (l[2]); | |
2309 | } | |
4761e388 | 2310 | else |
2505bc97 | 2311 | { |
4761e388 NS |
2312 | /* No non-CONST_DOUBLE constant should ever appear |
2313 | here. */ | |
2314 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2315 | } |
2316 | } | |
2317 | else | |
2318 | { | |
2319 | middlehalf[1] = operands[1]; | |
2320 | latehalf[1] = operands[1]; | |
2321 | } | |
2322 | } | |
79e68feb | 2323 | else |
2505bc97 RS |
2324 | /* size is not 12: */ |
2325 | { | |
2326 | if (optype0 == REGOP) | |
1d8eaa6b | 2327 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2328 | else if (optype0 == OFFSOP) |
b72f00af | 2329 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2330 | else |
2331 | latehalf[0] = operands[0]; | |
2332 | ||
2333 | if (optype1 == REGOP) | |
1d8eaa6b | 2334 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2335 | else if (optype1 == OFFSOP) |
b72f00af | 2336 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2337 | else if (optype1 == CNSTOP) |
2338 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2339 | else | |
2340 | latehalf[1] = operands[1]; | |
2341 | } | |
79e68feb RS |
2342 | |
2343 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2344 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2345 | for the low word as well, to compensate for the first decrement of sp. */ | |
2346 | if (optype0 == PUSHOP | |
2347 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2348 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2349 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2350 | |
7f98eeb6 RS |
2351 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2352 | if the upper part of reg N does not appear in the MEM, arrange to | |
2353 | emit the move late-half first. Otherwise, compute the MEM address | |
2354 | into the upper part of N and use that as a pointer to the memory | |
2355 | operand. */ | |
2356 | if (optype0 == REGOP | |
2357 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2358 | { | |
1d8eaa6b | 2359 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2360 | |
2361 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2362 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2363 | { |
2364 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2365 | compute the address into latehalf of dest. |
2366 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2367 | compadr: |
7f98eeb6 RS |
2368 | xops[0] = latehalf[0]; |
2369 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2370 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2371 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2372 | { |
1d8eaa6b | 2373 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2374 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2375 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2376 | } |
2377 | else | |
2378 | { | |
1d8eaa6b | 2379 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2380 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2381 | } |
2382 | } | |
2383 | else if (size == 12 | |
d7e8d581 RS |
2384 | && reg_overlap_mentioned_p (middlehalf[0], |
2385 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2386 | { |
3a58400f RS |
2387 | /* Check for two regs used by both source and dest. |
2388 | Note that this can't happen if the dest is all data regs. | |
2389 | It can happen if the dest is d6, d7, a0. | |
2390 | But in that case, latehalf is an addr reg, so | |
2391 | the code at compadr does ok. */ | |
2392 | ||
2393 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2394 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2395 | goto compadr; | |
7f98eeb6 RS |
2396 | |
2397 | /* JRV says this can't happen: */ | |
4761e388 | 2398 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2399 | |
7a1929e1 | 2400 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2401 | output_asm_insn (singlemove_string (operands), operands); |
2402 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2403 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2404 | return ""; | |
2405 | } | |
2fb8a81d | 2406 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2407 | /* If the low half of dest is mentioned in the source memory |
2408 | address, the arrange to emit the move late half first. */ | |
2409 | dest_overlapped_low = 1; | |
2410 | } | |
2411 | ||
79e68feb RS |
2412 | /* If one or both operands autodecrementing, |
2413 | do the two words, high-numbered first. */ | |
2414 | ||
2415 | /* Likewise, the first move would clobber the source of the second one, | |
2416 | do them in the other order. This happens only for registers; | |
2417 | such overlap can't happen in memory unless the user explicitly | |
2418 | sets it up, and that is an undefined circumstance. */ | |
2419 | ||
2420 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2421 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2422 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2423 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2424 | || dest_overlapped_low) | |
79e68feb RS |
2425 | { |
2426 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2427 | if (addreg0) | |
2505bc97 RS |
2428 | { |
2429 | if (size == 12) | |
3b4b85c9 | 2430 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2431 | else |
3b4b85c9 | 2432 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2433 | } |
79e68feb | 2434 | if (addreg1) |
2505bc97 RS |
2435 | { |
2436 | if (size == 12) | |
3b4b85c9 | 2437 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2438 | else |
3b4b85c9 | 2439 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2440 | } |
79e68feb RS |
2441 | |
2442 | /* Do that word. */ | |
2443 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2444 | ||
2445 | /* Undo the adds we just did. */ | |
2446 | if (addreg0) | |
3b4b85c9 | 2447 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2448 | if (addreg1) |
3b4b85c9 | 2449 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2450 | |
2505bc97 RS |
2451 | if (size == 12) |
2452 | { | |
2453 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2454 | if (addreg0) | |
3b4b85c9 | 2455 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2456 | if (addreg1) |
3b4b85c9 | 2457 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2458 | } |
2459 | ||
79e68feb RS |
2460 | /* Do low-numbered word. */ |
2461 | return singlemove_string (operands); | |
2462 | } | |
2463 | ||
2464 | /* Normal case: do the two words, low-numbered first. */ | |
2465 | ||
2466 | output_asm_insn (singlemove_string (operands), operands); | |
2467 | ||
2505bc97 RS |
2468 | /* Do the middle one of the three words for long double */ |
2469 | if (size == 12) | |
2470 | { | |
2471 | if (addreg0) | |
3b4b85c9 | 2472 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2473 | if (addreg1) |
3b4b85c9 | 2474 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2475 | |
2476 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2477 | } | |
2478 | ||
79e68feb RS |
2479 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2480 | if (addreg0) | |
3b4b85c9 | 2481 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2482 | if (addreg1) |
3b4b85c9 | 2483 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2484 | |
2485 | /* Do that word. */ | |
2486 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2487 | ||
2488 | /* Undo the adds we just did. */ | |
2489 | if (addreg0) | |
2505bc97 RS |
2490 | { |
2491 | if (size == 12) | |
3b4b85c9 | 2492 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2493 | else |
3b4b85c9 | 2494 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2495 | } |
79e68feb | 2496 | if (addreg1) |
2505bc97 RS |
2497 | { |
2498 | if (size == 12) | |
3b4b85c9 | 2499 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2500 | else |
3b4b85c9 | 2501 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2502 | } |
79e68feb RS |
2503 | |
2504 | return ""; | |
2505 | } | |
2506 | ||
dcc21c4c PB |
2507 | |
2508 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2509 | new rtx with the correct mode. */ | |
2510 | ||
2511 | static rtx | |
2512 | force_mode (enum machine_mode mode, rtx orig) | |
2513 | { | |
2514 | if (mode == GET_MODE (orig)) | |
2515 | return orig; | |
2516 | ||
2517 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2518 | abort (); | |
2519 | ||
2520 | return gen_rtx_REG (mode, REGNO (orig)); | |
2521 | } | |
2522 | ||
2523 | static int | |
2524 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2525 | { | |
2526 | return reg_renumber && FP_REG_P (op); | |
2527 | } | |
2528 | ||
2529 | /* Emit insns to move operands[1] into operands[0]. | |
2530 | ||
2531 | Return 1 if we have written out everything that needs to be done to | |
2532 | do the move. Otherwise, return 0 and the caller will emit the move | |
2533 | normally. | |
2534 | ||
2535 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2536 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2537 | of SCRATCH_REG in the proper mode. */ |
2538 | ||
2539 | int | |
2540 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2541 | { | |
2542 | register rtx operand0 = operands[0]; | |
2543 | register rtx operand1 = operands[1]; | |
2544 | register rtx tem; | |
2545 | ||
2546 | if (scratch_reg | |
2547 | && reload_in_progress && GET_CODE (operand0) == REG | |
2548 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2549 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2550 | else if (scratch_reg | |
2551 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2552 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2553 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2554 | { | |
2555 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2556 | the code which tracks sets/uses for delete_output_reload. */ | |
2557 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2558 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2559 | SUBREG_BYTE (operand0)); | |
2560 | operand0 = alter_subreg (&temp); | |
2561 | } | |
2562 | ||
2563 | if (scratch_reg | |
2564 | && reload_in_progress && GET_CODE (operand1) == REG | |
2565 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2566 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2567 | else if (scratch_reg | |
2568 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2569 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2570 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2571 | { | |
2572 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2573 | the code which tracks sets/uses for delete_output_reload. */ | |
2574 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2575 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2576 | SUBREG_BYTE (operand1)); | |
2577 | operand1 = alter_subreg (&temp); | |
2578 | } | |
2579 | ||
2580 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2581 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2582 | != XEXP (operand0, 0))) | |
2583 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2584 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2585 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2586 | != XEXP (operand1, 0))) | |
2587 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2588 | ||
2589 | /* Handle secondary reloads for loads/stores of FP registers where | |
2590 | the address is symbolic by using the scratch register */ | |
2591 | if (fp_reg_operand (operand0, mode) | |
2592 | && ((GET_CODE (operand1) == MEM | |
2593 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
2594 | || ((GET_CODE (operand1) == SUBREG | |
2595 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
2596 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
2597 | && scratch_reg) | |
2598 | { | |
2599 | if (GET_CODE (operand1) == SUBREG) | |
2600 | operand1 = XEXP (operand1, 0); | |
2601 | ||
2602 | /* SCRATCH_REG will hold an address. We want | |
2603 | it in SImode regardless of what mode it was originally given | |
2604 | to us. */ | |
2605 | scratch_reg = force_mode (SImode, scratch_reg); | |
2606 | ||
2607 | /* D might not fit in 14 bits either; for such cases load D into | |
2608 | scratch reg. */ | |
2609 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
2610 | { | |
2611 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
2612 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
2613 | Pmode, | |
2614 | XEXP (XEXP (operand1, 0), 0), | |
2615 | scratch_reg)); | |
2616 | } | |
2617 | else | |
2618 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
2619 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
2620 | gen_rtx_MEM (mode, scratch_reg))); | |
2621 | return 1; | |
2622 | } | |
2623 | else if (fp_reg_operand (operand1, mode) | |
2624 | && ((GET_CODE (operand0) == MEM | |
2625 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
2626 | || ((GET_CODE (operand0) == SUBREG) | |
2627 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
2628 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
2629 | && scratch_reg) | |
2630 | { | |
2631 | if (GET_CODE (operand0) == SUBREG) | |
2632 | operand0 = XEXP (operand0, 0); | |
2633 | ||
2634 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2635 | it in SIMODE regardless of what mode it was originally given | |
2636 | to us. */ | |
2637 | scratch_reg = force_mode (SImode, scratch_reg); | |
2638 | ||
2639 | /* D might not fit in 14 bits either; for such cases load D into | |
2640 | scratch reg. */ | |
2641 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
2642 | { | |
2643 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
2644 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
2645 | 0)), | |
2646 | Pmode, | |
2647 | XEXP (XEXP (operand0, 0), | |
2648 | 0), | |
2649 | scratch_reg)); | |
2650 | } | |
2651 | else | |
2652 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
2653 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
2654 | operand1)); | |
2655 | return 1; | |
2656 | } | |
2657 | /* Handle secondary reloads for loads of FP registers from constant | |
2658 | expressions by forcing the constant into memory. | |
2659 | ||
2660 | use scratch_reg to hold the address of the memory location. | |
2661 | ||
2662 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
2663 | NO_REGS when presented with a const_int and an register class | |
2664 | containing only FP registers. Doing so unfortunately creates | |
2665 | more problems than it solves. Fix this for 2.5. */ | |
2666 | else if (fp_reg_operand (operand0, mode) | |
2667 | && CONSTANT_P (operand1) | |
2668 | && scratch_reg) | |
2669 | { | |
2670 | rtx xoperands[2]; | |
2671 | ||
2672 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2673 | it in SIMODE regardless of what mode it was originally given | |
2674 | to us. */ | |
2675 | scratch_reg = force_mode (SImode, scratch_reg); | |
2676 | ||
2677 | /* Force the constant into memory and put the address of the | |
2678 | memory location into scratch_reg. */ | |
2679 | xoperands[0] = scratch_reg; | |
2680 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
2681 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
2682 | ||
2683 | /* Now load the destination register. */ | |
2684 | emit_insn (gen_rtx_SET (mode, operand0, | |
2685 | gen_rtx_MEM (mode, scratch_reg))); | |
2686 | return 1; | |
2687 | } | |
2688 | ||
2689 | /* Now have insn-emit do whatever it normally does. */ | |
2690 | return 0; | |
2691 | } | |
2692 | ||
79e68feb RS |
2693 | /* Return a REG that occurs in ADDR with coefficient 1. |
2694 | ADDR can be effectively incremented by incrementing REG. */ | |
2695 | ||
2696 | static rtx | |
8a4a2253 | 2697 | find_addr_reg (rtx addr) |
79e68feb RS |
2698 | { |
2699 | while (GET_CODE (addr) == PLUS) | |
2700 | { | |
2701 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2702 | addr = XEXP (addr, 0); | |
2703 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2704 | addr = XEXP (addr, 1); | |
2705 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2706 | addr = XEXP (addr, 1); | |
2707 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2708 | addr = XEXP (addr, 0); | |
2709 | else | |
4761e388 | 2710 | gcc_unreachable (); |
79e68feb | 2711 | } |
4761e388 NS |
2712 | gcc_assert (GET_CODE (addr) == REG); |
2713 | return addr; | |
79e68feb | 2714 | } |
9ee3c687 | 2715 | |
c16eadc7 | 2716 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 2717 | |
5505f548 | 2718 | const char * |
8a4a2253 | 2719 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
2720 | { |
2721 | if (! operands_match_p (operands[0], operands[1])) | |
2722 | { | |
2723 | if (!ADDRESS_REG_P (operands[1])) | |
2724 | { | |
2725 | rtx tmp = operands[1]; | |
2726 | ||
2727 | operands[1] = operands[2]; | |
2728 | operands[2] = tmp; | |
2729 | } | |
2730 | ||
2731 | /* These insns can result from reloads to access | |
2732 | stack slots over 64k from the frame pointer. */ | |
2733 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 2734 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 2735 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 2736 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
2737 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
2738 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
2739 | } |
2740 | if (GET_CODE (operands[2]) == CONST_INT) | |
2741 | { | |
9ee3c687 JW |
2742 | if (INTVAL (operands[2]) > 0 |
2743 | && INTVAL (operands[2]) <= 8) | |
2744 | return "addq%.l %2,%0"; | |
2745 | if (INTVAL (operands[2]) < 0 | |
2746 | && INTVAL (operands[2]) >= -8) | |
2747 | { | |
c5c76735 | 2748 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
2749 | return "subq%.l %2,%0"; |
2750 | } | |
2751 | /* On the CPU32 it is faster to use two addql instructions to | |
2752 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 2753 | Likewise for subql. */ |
fe95f2f7 | 2754 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
2755 | { |
2756 | if (INTVAL (operands[2]) > 8 | |
2757 | && INTVAL (operands[2]) <= 16) | |
2758 | { | |
1d8eaa6b | 2759 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 2760 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
2761 | } |
2762 | if (INTVAL (operands[2]) < -8 | |
2763 | && INTVAL (operands[2]) >= -16) | |
2764 | { | |
c5c76735 | 2765 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 2766 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
2767 | } |
2768 | } | |
9ee3c687 JW |
2769 | if (ADDRESS_REG_P (operands[0]) |
2770 | && INTVAL (operands[2]) >= -0x8000 | |
2771 | && INTVAL (operands[2]) < 0x8000) | |
2772 | { | |
fe95f2f7 | 2773 | if (TUNE_68040) |
9ee3c687 JW |
2774 | return "add%.w %2,%0"; |
2775 | else | |
e6d98cb0 | 2776 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
2777 | } |
2778 | } | |
2779 | return "add%.l %2,%0"; | |
2780 | } | |
79e68feb RS |
2781 | \f |
2782 | /* Store in cc_status the expressions that the condition codes will | |
2783 | describe after execution of an instruction whose pattern is EXP. | |
2784 | Do not alter them if the instruction would not alter the cc's. */ | |
2785 | ||
2786 | /* On the 68000, all the insns to store in an address register fail to | |
2787 | set the cc's. However, in some cases these instructions can make it | |
2788 | possibly invalid to use the saved cc's. In those cases we clear out | |
2789 | some or all of the saved cc's so they won't be used. */ | |
2790 | ||
1d8eaa6b | 2791 | void |
8a4a2253 | 2792 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 2793 | { |
1a8965c4 | 2794 | if (GET_CODE (exp) == SET) |
79e68feb RS |
2795 | { |
2796 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 2797 | CC_STATUS_INIT; |
79e68feb RS |
2798 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
2799 | { | |
f5963e61 | 2800 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 2801 | cc_status.value1 = 0; |
f5963e61 | 2802 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
2803 | cc_status.value2 = 0; |
2804 | } | |
2805 | else if (!FP_REG_P (SET_DEST (exp)) | |
2806 | && SET_DEST (exp) != cc0_rtx | |
2807 | && (FP_REG_P (SET_SRC (exp)) | |
2808 | || GET_CODE (SET_SRC (exp)) == FIX | |
2809 | || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE | |
2810 | || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND)) | |
a0a7fbc9 | 2811 | CC_STATUS_INIT; |
79e68feb RS |
2812 | /* A pair of move insns doesn't produce a useful overall cc. */ |
2813 | else if (!FP_REG_P (SET_DEST (exp)) | |
2814 | && !FP_REG_P (SET_SRC (exp)) | |
2815 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
2816 | && (GET_CODE (SET_SRC (exp)) == REG | |
2817 | || GET_CODE (SET_SRC (exp)) == MEM | |
2818 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 2819 | CC_STATUS_INIT; |
e1dff52a | 2820 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
2821 | { |
2822 | cc_status.flags = 0; | |
e1dff52a KH |
2823 | cc_status.value1 = SET_DEST (exp); |
2824 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
2825 | } |
2826 | } | |
2827 | else if (GET_CODE (exp) == PARALLEL | |
2828 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
2829 | { | |
e1dff52a KH |
2830 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
2831 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
2832 | ||
2833 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 2834 | CC_STATUS_INIT; |
e1dff52a | 2835 | else if (dest != pc_rtx) |
79e68feb RS |
2836 | { |
2837 | cc_status.flags = 0; | |
e1dff52a KH |
2838 | cc_status.value1 = dest; |
2839 | cc_status.value2 = src; | |
79e68feb RS |
2840 | } |
2841 | } | |
2842 | else | |
2843 | CC_STATUS_INIT; | |
2844 | if (cc_status.value2 != 0 | |
2845 | && ADDRESS_REG_P (cc_status.value2) | |
2846 | && GET_MODE (cc_status.value2) == QImode) | |
2847 | CC_STATUS_INIT; | |
1a8965c4 | 2848 | if (cc_status.value2 != 0) |
79e68feb RS |
2849 | switch (GET_CODE (cc_status.value2)) |
2850 | { | |
996a5f59 | 2851 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 2852 | case ROTATE: case ROTATERT: |
a126dc3a RH |
2853 | /* These instructions always clear the overflow bit, and set |
2854 | the carry to the bit shifted out. */ | |
2855 | /* ??? We don't currently have a way to signal carry not valid, | |
2856 | nor do we check for it in the branch insns. */ | |
2857 | CC_STATUS_INIT; | |
2858 | break; | |
2859 | ||
2860 | case PLUS: case MINUS: case MULT: | |
2861 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
2862 | if (GET_MODE (cc_status.value2) != VOIDmode) |
2863 | cc_status.flags |= CC_NO_OVERFLOW; | |
2864 | break; | |
2865 | case ZERO_EXTEND: | |
2866 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
2867 | ends with a move insn moving r2 in r2's mode. | |
2868 | Thus, the cc's are set for r2. | |
7a1929e1 | 2869 | This can set N bit spuriously. */ |
79e68feb | 2870 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
2871 | |
2872 | default: | |
2873 | break; | |
79e68feb RS |
2874 | } |
2875 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
2876 | && cc_status.value2 | |
2877 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
2878 | cc_status.value2 = 0; | |
2879 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 2880 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
2881 | cc_status.flags = CC_IN_68881; |
2882 | } | |
2883 | \f | |
5505f548 | 2884 | const char * |
8a4a2253 | 2885 | output_move_const_double (rtx *operands) |
79e68feb | 2886 | { |
1a8965c4 | 2887 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2888 | |
1a8965c4 | 2889 | if (code != 0) |
79e68feb | 2890 | { |
1a8965c4 | 2891 | static char buf[40]; |
79e68feb | 2892 | |
3b4b85c9 | 2893 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2894 | return buf; |
79e68feb | 2895 | } |
1a8965c4 | 2896 | return "fmove%.d %1,%0"; |
79e68feb RS |
2897 | } |
2898 | ||
5505f548 | 2899 | const char * |
8a4a2253 | 2900 | output_move_const_single (rtx *operands) |
79e68feb | 2901 | { |
1a8965c4 | 2902 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 2903 | |
1a8965c4 | 2904 | if (code != 0) |
79e68feb | 2905 | { |
1a8965c4 | 2906 | static char buf[40]; |
79e68feb | 2907 | |
3b4b85c9 | 2908 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 2909 | return buf; |
79e68feb | 2910 | } |
1a8965c4 | 2911 | return "fmove%.s %f1,%0"; |
79e68feb RS |
2912 | } |
2913 | ||
2914 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
2915 | from the "fmovecr" instruction. | |
2916 | The value, anded with 0xff, gives the code to use in fmovecr | |
2917 | to get the desired constant. */ | |
2918 | ||
7a1929e1 | 2919 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
2920 | |
2921 | static int inited_68881_table = 0; | |
2922 | ||
5505f548 | 2923 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
2924 | "0.0", |
2925 | "1.0", | |
2926 | "10.0", | |
2927 | "100.0", | |
2928 | "10000.0", | |
2929 | "1e8", | |
2930 | "1e16" | |
a0a7fbc9 | 2931 | }; |
c1cfb2ae | 2932 | |
8b60264b | 2933 | static const int codes_68881[7] = { |
c1cfb2ae RS |
2934 | 0x0f, |
2935 | 0x32, | |
2936 | 0x33, | |
2937 | 0x34, | |
2938 | 0x35, | |
2939 | 0x36, | |
2940 | 0x37 | |
a0a7fbc9 | 2941 | }; |
c1cfb2ae RS |
2942 | |
2943 | REAL_VALUE_TYPE values_68881[7]; | |
2944 | ||
2945 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 2946 | strings_68881 to binary. */ |
c1cfb2ae RS |
2947 | |
2948 | void | |
8a4a2253 | 2949 | init_68881_table (void) |
c1cfb2ae RS |
2950 | { |
2951 | int i; | |
2952 | REAL_VALUE_TYPE r; | |
2953 | enum machine_mode mode; | |
2954 | ||
16d82c3c | 2955 | mode = SFmode; |
c1cfb2ae RS |
2956 | for (i = 0; i < 7; i++) |
2957 | { | |
2958 | if (i == 6) | |
16d82c3c | 2959 | mode = DFmode; |
c1cfb2ae RS |
2960 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
2961 | values_68881[i] = r; | |
2962 | } | |
2963 | inited_68881_table = 1; | |
2964 | } | |
79e68feb RS |
2965 | |
2966 | int | |
8a4a2253 | 2967 | standard_68881_constant_p (rtx x) |
79e68feb | 2968 | { |
c1cfb2ae RS |
2969 | REAL_VALUE_TYPE r; |
2970 | int i; | |
79e68feb | 2971 | |
e18db50d | 2972 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 2973 | used at all on those chips. */ |
9cf106c8 | 2974 | if (TUNE_68040_60) |
79e68feb RS |
2975 | return 0; |
2976 | ||
c1cfb2ae RS |
2977 | if (! inited_68881_table) |
2978 | init_68881_table (); | |
2979 | ||
2980 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2981 | ||
64c0b414 AS |
2982 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
2983 | is rejected. */ | |
c1cfb2ae RS |
2984 | for (i = 0; i < 6; i++) |
2985 | { | |
64c0b414 | 2986 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
2987 | return (codes_68881[i]); |
2988 | } | |
2989 | ||
79e68feb RS |
2990 | if (GET_MODE (x) == SFmode) |
2991 | return 0; | |
c1cfb2ae RS |
2992 | |
2993 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
2994 | return (codes_68881[6]); | |
2995 | ||
79e68feb RS |
2996 | /* larger powers of ten in the constants ram are not used |
2997 | because they are not equal to a `double' C constant. */ | |
2998 | return 0; | |
2999 | } | |
3000 | ||
3001 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3002 | or 0 if X is not a power of 2. */ | |
3003 | ||
3004 | int | |
8a4a2253 | 3005 | floating_exact_log2 (rtx x) |
79e68feb | 3006 | { |
c1cfb2ae | 3007 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3008 | int exp; |
79e68feb | 3009 | |
c1cfb2ae | 3010 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3011 | |
eaff3bf8 | 3012 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3013 | return 0; |
3014 | ||
eaff3bf8 RH |
3015 | exp = real_exponent (&r); |
3016 | real_2expN (&r1, exp); | |
3017 | if (REAL_VALUES_EQUAL (r1, r)) | |
3018 | return exp; | |
3019 | ||
79e68feb RS |
3020 | return 0; |
3021 | } | |
3022 | \f | |
79e68feb RS |
3023 | /* A C compound statement to output to stdio stream STREAM the |
3024 | assembler syntax for an instruction operand X. X is an RTL | |
3025 | expression. | |
3026 | ||
3027 | CODE is a value that can be used to specify one of several ways | |
3028 | of printing the operand. It is used when identical operands | |
3029 | must be printed differently depending on the context. CODE | |
3030 | comes from the `%' specification that was used to request | |
3031 | printing of the operand. If the specification was just `%DIGIT' | |
3032 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3033 | is the ASCII code for LTR. | |
3034 | ||
3035 | If X is a register, this macro should print the register's name. | |
3036 | The names can be found in an array `reg_names' whose type is | |
3037 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3038 | ||
3039 | When the machine description has a specification `%PUNCT' (a `%' | |
3040 | followed by a punctuation character), this macro is called with | |
3041 | a null pointer for X and the punctuation character for CODE. | |
3042 | ||
3043 | The m68k specific codes are: | |
3044 | ||
3045 | '.' for dot needed in Motorola-style opcode names. | |
3046 | '-' for an operand pushing on the stack: | |
3047 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3048 | '+' for an operand pushing on the stack: | |
3049 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3050 | '@' for a reference to the top word on the stack: | |
3051 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3052 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3053 | but & in SGS syntax). |
79e68feb RS |
3054 | '!' for the cc register (used in an `and to cc' insn). |
3055 | '$' for the letter `s' in an op code, but only on the 68040. | |
3056 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3057 | '/' for register prefix needed by longlong.h. |
79e68feb RS |
3058 | |
3059 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3060 | 'd' to force memory addressing to be absolute, not relative. | |
3061 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
2c8ec431 DL |
3062 | 'o' for operands to go directly to output_operand_address (bypassing |
3063 | print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) | |
79e68feb RS |
3064 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3065 | or print pair of registers as rx:ry. | |
79e68feb RS |
3066 | |
3067 | */ | |
3068 | ||
3069 | void | |
8a4a2253 | 3070 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3071 | { |
79e68feb RS |
3072 | if (letter == '.') |
3073 | { | |
e6d98cb0 BI |
3074 | if (MOTOROLA) |
3075 | fprintf (file, "."); | |
79e68feb RS |
3076 | } |
3077 | else if (letter == '#') | |
e6d98cb0 | 3078 | asm_fprintf (file, "%I"); |
79e68feb | 3079 | else if (letter == '-') |
e6d98cb0 | 3080 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 3081 | else if (letter == '+') |
e6d98cb0 | 3082 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 3083 | else if (letter == '@') |
e6d98cb0 | 3084 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 3085 | else if (letter == '!') |
e6d98cb0 | 3086 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3087 | else if (letter == '$') |
3088 | { | |
b101567e | 3089 | if (TARGET_68040) |
e6d98cb0 | 3090 | fprintf (file, "s"); |
79e68feb RS |
3091 | } |
3092 | else if (letter == '&') | |
3093 | { | |
b101567e | 3094 | if (TARGET_68040) |
e6d98cb0 | 3095 | fprintf (file, "d"); |
79e68feb | 3096 | } |
2ac5f14a | 3097 | else if (letter == '/') |
e6d98cb0 | 3098 | asm_fprintf (file, "%R"); |
2c8ec431 DL |
3099 | else if (letter == 'o') |
3100 | { | |
3101 | /* This is only for direct addresses with TARGET_PCREL */ | |
4761e388 NS |
3102 | gcc_assert (GET_CODE (op) == MEM |
3103 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
3104 | && TARGET_PCREL); | |
2c8ec431 DL |
3105 | output_addr_const (file, XEXP (op, 0)); |
3106 | } | |
79e68feb RS |
3107 | else if (GET_CODE (op) == REG) |
3108 | { | |
1a8965c4 AS |
3109 | if (letter == 'R') |
3110 | /* Print out the second register name of a register pair. | |
3111 | I.e., R (6) => 7. */ | |
01bbf777 | 3112 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3113 | else |
01bbf777 | 3114 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3115 | } |
3116 | else if (GET_CODE (op) == MEM) | |
3117 | { | |
3118 | output_address (XEXP (op, 0)); | |
3119 | if (letter == 'd' && ! TARGET_68020 | |
3120 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3121 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3122 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3123 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 3124 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 3125 | } |
79e68feb RS |
3126 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3127 | { | |
c1cfb2ae RS |
3128 | REAL_VALUE_TYPE r; |
3129 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3130 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3131 | } | |
3132 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3133 | { | |
3134 | REAL_VALUE_TYPE r; | |
3135 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3136 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3137 | } |
e2c0a924 | 3138 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3139 | { |
c1cfb2ae RS |
3140 | REAL_VALUE_TYPE r; |
3141 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3142 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3143 | } |
3144 | else | |
3145 | { | |
2c8ec431 DL |
3146 | /* Use `print_operand_address' instead of `output_addr_const' |
3147 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3148 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3149 | if (TARGET_PCREL |
3150 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3151 | print_operand_address (file, op); | |
3152 | else | |
3153 | output_addr_const (file, op); | |
79e68feb RS |
3154 | } |
3155 | } | |
3156 | ||
3157 | \f | |
3158 | /* A C compound statement to output to stdio stream STREAM the | |
3159 | assembler syntax for an instruction operand that is a memory | |
3160 | reference whose address is ADDR. ADDR is an RTL expression. | |
3161 | ||
3162 | Note that this contains a kludge that knows that the only reason | |
3163 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3164 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3165 | generates a label LInnn: on such an insn. | |
3166 | ||
3167 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3168 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3169 | ||
3170 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
3171 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
3172 | we want. This difference can be accommodated by using an assembler | |
3173 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
3174 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 3175 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
3176 | Some assemblers refuse all the above solutions. The workaround is to |
3177 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 3178 | right behavior. |
79e68feb RS |
3179 | |
3180 | They also do not like things like "pea 1.w", so we simple leave off | |
3181 | the .w on small constants. | |
3182 | ||
3183 | This routine is responsible for distinguishing between -fpic and -fPIC | |
3184 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3185 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3186 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb | 3187 | |
3b4b85c9 | 3188 | #if MOTOROLA |
a0a7fbc9 AS |
3189 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3190 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname) | |
3b4b85c9 | 3191 | #else /* !MOTOROLA */ |
a0a7fbc9 AS |
3192 | # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \ |
3193 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname) | |
3b4b85c9 | 3194 | #endif /* !MOTOROLA */ |
f4a6e73b | 3195 | |
79e68feb | 3196 | void |
8a4a2253 | 3197 | print_operand_address (FILE *file, rtx addr) |
79e68feb RS |
3198 | { |
3199 | register rtx reg1, reg2, breg, ireg; | |
3200 | rtx offset; | |
3201 | ||
3202 | switch (GET_CODE (addr)) | |
3203 | { | |
a0a7fbc9 AS |
3204 | case REG: |
3205 | fprintf (file, MOTOROLA ? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr))); | |
3206 | break; | |
3207 | case PRE_DEC: | |
3208 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", | |
3209 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3210 | break; | |
3211 | case POST_INC: | |
3212 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", | |
3213 | M68K_REGNAME (REGNO (XEXP (addr, 0)))); | |
3214 | break; | |
3215 | case PLUS: | |
3216 | reg1 = reg2 = ireg = breg = offset = 0; | |
3217 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) | |
3218 | { | |
3219 | offset = XEXP (addr, 0); | |
3220 | addr = XEXP (addr, 1); | |
3221 | } | |
3222 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) | |
3223 | { | |
3224 | offset = XEXP (addr, 1); | |
3225 | addr = XEXP (addr, 0); | |
3226 | } | |
3227 | if (GET_CODE (addr) != PLUS) | |
3228 | { | |
3229 | ; | |
3230 | } | |
3231 | else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) | |
3232 | { | |
3233 | reg1 = XEXP (addr, 0); | |
3234 | addr = XEXP (addr, 1); | |
3235 | } | |
3236 | else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) | |
3237 | { | |
3238 | reg1 = XEXP (addr, 1); | |
3239 | addr = XEXP (addr, 0); | |
3240 | } | |
3241 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
3242 | { | |
3243 | reg1 = XEXP (addr, 0); | |
3244 | addr = XEXP (addr, 1); | |
3245 | } | |
3246 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
3247 | { | |
3248 | reg1 = XEXP (addr, 1); | |
3249 | addr = XEXP (addr, 0); | |
3250 | } | |
3251 | else if (GET_CODE (XEXP (addr, 0)) == REG) | |
3252 | { | |
3253 | reg1 = XEXP (addr, 0); | |
3254 | addr = XEXP (addr, 1); | |
3255 | } | |
3256 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3257 | { | |
3258 | reg1 = XEXP (addr, 1); | |
3259 | addr = XEXP (addr, 0); | |
3260 | } | |
3261 | if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT | |
3262 | || GET_CODE (addr) == SIGN_EXTEND) | |
3263 | { | |
3264 | if (reg1 == 0) | |
3265 | reg1 = addr; | |
3266 | else | |
3267 | reg2 = addr; | |
3268 | addr = 0; | |
3269 | } | |
79e68feb | 3270 | #if 0 /* for OLD_INDEXING */ |
a0a7fbc9 AS |
3271 | else if (GET_CODE (addr) == PLUS) |
3272 | { | |
3273 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3274 | { | |
3275 | reg2 = XEXP (addr, 0); | |
3276 | addr = XEXP (addr, 1); | |
3277 | } | |
3278 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3279 | { | |
3280 | reg2 = XEXP (addr, 1); | |
3281 | addr = XEXP (addr, 0); | |
3282 | } | |
3283 | } | |
79e68feb | 3284 | #endif |
a0a7fbc9 AS |
3285 | if (offset != 0) |
3286 | { | |
3287 | gcc_assert (!addr); | |
3288 | addr = offset; | |
3289 | } | |
3290 | if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND | |
3291 | || GET_CODE (reg1) == MULT)) | |
3292 | || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) | |
3293 | { | |
3294 | breg = reg2; | |
3295 | ireg = reg1; | |
3296 | } | |
3297 | else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) | |
3298 | { | |
3299 | breg = reg1; | |
3300 | ireg = reg2; | |
3301 | } | |
3302 | if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF | |
3303 | && ! (flag_pic && ireg == pic_offset_table_rtx)) | |
3304 | { | |
3305 | int scale = 1; | |
3306 | if (GET_CODE (ireg) == MULT) | |
3307 | { | |
3308 | scale = INTVAL (XEXP (ireg, 1)); | |
3309 | ireg = XEXP (ireg, 0); | |
3310 | } | |
3311 | if (GET_CODE (ireg) == SIGN_EXTEND) | |
3312 | { | |
3313 | ASM_OUTPUT_CASE_FETCH (file, | |
3314 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3315 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3316 | fprintf (file, "w"); | |
3317 | } | |
3318 | else | |
3319 | { | |
3320 | ASM_OUTPUT_CASE_FETCH (file, | |
3321 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3322 | M68K_REGNAME (REGNO (ireg))); | |
3323 | fprintf (file, "l"); | |
3324 | } | |
3325 | if (scale != 1) | |
3326 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3327 | putc (')', file); | |
3328 | break; | |
3329 | } | |
3330 | if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF | |
3331 | && ! (flag_pic && breg == pic_offset_table_rtx)) | |
3332 | { | |
3333 | ASM_OUTPUT_CASE_FETCH (file, | |
3334 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3335 | M68K_REGNAME (REGNO (breg))); | |
3336 | fprintf (file, "l)"); | |
3337 | break; | |
3338 | } | |
3339 | if (ireg != 0 || breg != 0) | |
3340 | { | |
3341 | int scale = 1; | |
4761e388 | 3342 | |
a0a7fbc9 AS |
3343 | gcc_assert (breg); |
3344 | gcc_assert (flag_pic || !addr || GET_CODE (addr) != LABEL_REF); | |
4761e388 | 3345 | |
a0a7fbc9 AS |
3346 | if (MOTOROLA) |
3347 | { | |
3348 | if (addr != 0) | |
3349 | { | |
3350 | output_addr_const (file, addr); | |
3351 | if (flag_pic && (breg == pic_offset_table_rtx)) | |
3352 | { | |
3353 | fprintf (file, "@GOT"); | |
3354 | if (flag_pic == 1) | |
3355 | fprintf (file, ".w"); | |
3356 | } | |
3357 | } | |
3358 | fprintf (file, "(%s", M68K_REGNAME (REGNO (breg))); | |
3359 | if (ireg != 0) | |
3360 | putc (',', file); | |
3361 | } | |
3362 | else /* !MOTOROLA */ | |
3363 | { | |
3364 | fprintf (file, "%s@(", M68K_REGNAME (REGNO (breg))); | |
3365 | if (addr != 0) | |
3366 | { | |
3367 | output_addr_const (file, addr); | |
3368 | if (breg == pic_offset_table_rtx) | |
3369 | switch (flag_pic) | |
e6d98cb0 | 3370 | { |
a0a7fbc9 AS |
3371 | case 1: |
3372 | fprintf (file, ":w"); | |
3373 | break; | |
3374 | case 2: | |
3375 | fprintf (file, ":l"); | |
3376 | break; | |
3377 | default: | |
3378 | break; | |
e6d98cb0 | 3379 | } |
a0a7fbc9 AS |
3380 | if (ireg != 0) |
3381 | putc (',', file); | |
3382 | } | |
3383 | } /* !MOTOROLA */ | |
3384 | if (ireg != 0 && GET_CODE (ireg) == MULT) | |
3385 | { | |
3386 | scale = INTVAL (XEXP (ireg, 1)); | |
3387 | ireg = XEXP (ireg, 0); | |
3388 | } | |
3389 | if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) | |
3390 | fprintf (file, MOTOROLA ? "%s.w" : "%s:w", | |
3391 | M68K_REGNAME (REGNO (XEXP (ireg, 0)))); | |
3392 | else if (ireg != 0) | |
3393 | fprintf (file, MOTOROLA ? "%s.l" : "%s:l", | |
3394 | M68K_REGNAME (REGNO (ireg))); | |
3395 | if (scale != 1) | |
3396 | fprintf (file, MOTOROLA ? "*%d" : ":%d", scale); | |
3397 | putc (')', file); | |
3398 | break; | |
3399 | } | |
3400 | else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF | |
3401 | && ! (flag_pic && reg1 == pic_offset_table_rtx)) | |
3402 | { | |
3403 | ASM_OUTPUT_CASE_FETCH (file, | |
3404 | CODE_LABEL_NUMBER (XEXP (addr, 0)), | |
3405 | M68K_REGNAME (REGNO (reg1))); | |
3406 | fprintf (file, "l)"); | |
3407 | break; | |
3408 | } | |
3409 | /* FALL-THROUGH (is this really what we want?) */ | |
3410 | default: | |
3411 | if (GET_CODE (addr) == CONST_INT | |
3412 | && INTVAL (addr) < 0x8000 | |
3413 | && INTVAL (addr) >= -0x8000) | |
3414 | { | |
3415 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); | |
3416 | } | |
3417 | else if (GET_CODE (addr) == CONST_INT) | |
3418 | { | |
3419 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); | |
3420 | } | |
3421 | else if (TARGET_PCREL) | |
3422 | { | |
3423 | fputc ('(', file); | |
3424 | output_addr_const (file, addr); | |
3425 | if (flag_pic == 1) | |
3426 | asm_fprintf (file, ":w,%Rpc)"); | |
3427 | else | |
3428 | asm_fprintf (file, ":l,%Rpc)"); | |
3429 | } | |
3430 | else | |
3431 | { | |
3432 | /* Special case for SYMBOL_REF if the symbol name ends in | |
3433 | `.<letter>', this can be mistaken as a size suffix. Put | |
3434 | the name in parentheses. */ | |
3435 | if (GET_CODE (addr) == SYMBOL_REF | |
3436 | && strlen (XSTR (addr, 0)) > 2 | |
3437 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
3438 | { | |
3439 | putc ('(', file); | |
c2ac2ff6 | 3440 | output_addr_const (file, addr); |
a0a7fbc9 AS |
3441 | putc (')', file); |
3442 | } | |
3443 | else | |
3444 | output_addr_const (file, addr); | |
3445 | } | |
3446 | break; | |
79e68feb RS |
3447 | } |
3448 | } | |
af13f02d JW |
3449 | \f |
3450 | /* Check for cases where a clr insns can be omitted from code using | |
3451 | strict_low_part sets. For example, the second clrl here is not needed: | |
3452 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3453 | ||
3454 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3455 | insn we are checking for redundancy. TARGET is the register set by the | |
3456 | clear insn. */ | |
3457 | ||
8a4a2253 BI |
3458 | bool |
3459 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3460 | rtx target) | |
af13f02d JW |
3461 | { |
3462 | rtx p; | |
3463 | ||
3464 | p = prev_nonnote_insn (first_insn); | |
3465 | ||
3466 | while (p) | |
3467 | { | |
3468 | /* If it isn't an insn, then give up. */ | |
3469 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 3470 | return false; |
af13f02d JW |
3471 | |
3472 | if (reg_set_p (target, p)) | |
3473 | { | |
3474 | rtx set = single_set (p); | |
3475 | rtx dest; | |
3476 | ||
3477 | /* If it isn't an easy to recognize insn, then give up. */ | |
3478 | if (! set) | |
8a4a2253 | 3479 | return false; |
af13f02d JW |
3480 | |
3481 | dest = SET_DEST (set); | |
3482 | ||
3483 | /* If this sets the entire target register to zero, then our | |
3484 | first_insn is redundant. */ | |
3485 | if (rtx_equal_p (dest, target) | |
3486 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3487 | return true; |
af13f02d JW |
3488 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3489 | && GET_CODE (XEXP (dest, 0)) == REG | |
3490 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3491 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3492 | <= GET_MODE_SIZE (mode))) | |
3493 | /* This is a strict low part set which modifies less than | |
3494 | we are using, so it is safe. */ | |
3495 | ; | |
3496 | else | |
8a4a2253 | 3497 | return false; |
af13f02d JW |
3498 | } |
3499 | ||
3500 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3501 | } |
3502 | ||
8a4a2253 | 3503 | return false; |
af13f02d | 3504 | } |
67cd4f83 | 3505 | |
2c8ec431 DL |
3506 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3507 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3508 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3509 | |
3510 | We model this by restricting the meaning of the basic predicates | |
3511 | (general_operand, memory_operand, etc) to forbid the use of this | |
3512 | addressing mode, and then define the following predicates that permit | |
3513 | this addressing mode. These predicates can then be used for the | |
3514 | source operands of the appropriate instructions. | |
3515 | ||
3516 | n.b. While it is theoretically possible to change all machine patterns | |
3517 | to use this addressing more where permitted by the architecture, | |
3518 | it has only been implemented for "common" cases: SImode, HImode, and | |
3519 | QImode operands, and only for the principle operations that would | |
3520 | require this addressing mode: data movement and simple integer operations. | |
3521 | ||
3522 | In parallel with these new predicates, two new constraint letters | |
3523 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3524 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3525 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3526 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3527 | of how these constraints are used. | |
3528 | ||
3529 | The use of these predicates is strictly optional, though patterns that | |
3530 | don't will cause an extra reload register to be allocated where one | |
3531 | was not necessary: | |
3532 | ||
3533 | lea (abc:w,%pc),%a0 ; need to reload address | |
3534 | moveq &1,%d1 ; since write to pc-relative space | |
3535 | movel %d1,%a0@ ; is not allowed | |
3536 | ... | |
3537 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3538 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3539 | ||
3540 | For more info, consult tiemann@cygnus.com. | |
3541 | ||
3542 | ||
3543 | All of the ugliness with predicates and constraints is due to the | |
3544 | simple fact that the m68k does not allow a pc-relative addressing | |
3545 | mode as a destination. gcc does not distinguish between source and | |
3546 | destination addresses. Hence, if we claim that pc-relative address | |
3547 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3548 | end up with invalid code. To get around this problem, we left | |
3549 | pc-relative modes as invalid addresses, and then added special | |
3550 | predicates and constraints to accept them. | |
3551 | ||
3552 | A cleaner way to handle this is to modify gcc to distinguish | |
3553 | between source and destination addresses. We can then say that | |
3554 | pc-relative is a valid source address but not a valid destination | |
3555 | address, and hopefully avoid a lot of the predicate and constraint | |
3556 | hackery. Unfortunately, this would be a pretty big change. It would | |
3557 | be a useful change for a number of ports, but there aren't any current | |
3558 | plans to undertake this. | |
3559 | ||
3560 | ***************************************************************************/ | |
3561 | ||
3562 | ||
5505f548 | 3563 | const char * |
8a4a2253 | 3564 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3565 | { |
3566 | int logval; | |
3567 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 3568 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
3569 | && (DATA_REG_P (operands[0]) |
3570 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3571 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3572 | { |
3573 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3574 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 3575 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
3576 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3577 | CC_STATUS_INIT; | |
3578 | if (operands[2] == const0_rtx) | |
3579 | return "clr%.w %0"; | |
3580 | return "and%.w %2,%0"; | |
3581 | } | |
3582 | if (GET_CODE (operands[2]) == CONST_INT | |
3583 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
3584 | && (DATA_REG_P (operands[0]) | |
3585 | || offsettable_memref_p (operands[0]))) | |
3586 | { | |
3587 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 3588 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3589 | else |
3590 | { | |
b72f00af | 3591 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3592 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3593 | } |
3594 | /* This does not set condition codes in a standard way. */ | |
3595 | CC_STATUS_INIT; | |
3596 | return "bclr %1,%0"; | |
3597 | } | |
3598 | return "and%.l %2,%0"; | |
3599 | } | |
3600 | ||
5505f548 | 3601 | const char * |
8a4a2253 | 3602 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
3603 | { |
3604 | register int logval; | |
3605 | if (GET_CODE (operands[2]) == CONST_INT | |
3606 | && INTVAL (operands[2]) >> 16 == 0 | |
3607 | && (DATA_REG_P (operands[0]) | |
3608 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3609 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3610 | { |
3611 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3612 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3613 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3614 | CC_STATUS_INIT; | |
3615 | if (INTVAL (operands[2]) == 0xffff) | |
3616 | return "mov%.w %2,%0"; | |
3617 | return "or%.w %2,%0"; | |
3618 | } | |
3619 | if (GET_CODE (operands[2]) == CONST_INT | |
3620 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3621 | && (DATA_REG_P (operands[0]) | |
3622 | || offsettable_memref_p (operands[0]))) | |
3623 | { | |
3624 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3625 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3626 | else |
3627 | { | |
b72f00af | 3628 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3629 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3630 | } |
3631 | CC_STATUS_INIT; | |
3632 | return "bset %1,%0"; | |
3633 | } | |
3634 | return "or%.l %2,%0"; | |
3635 | } | |
3636 | ||
5505f548 | 3637 | const char * |
8a4a2253 | 3638 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
3639 | { |
3640 | register int logval; | |
3641 | if (GET_CODE (operands[2]) == CONST_INT | |
3642 | && INTVAL (operands[2]) >> 16 == 0 | |
3643 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 3644 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3645 | { |
3646 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 3647 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3648 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3649 | CC_STATUS_INIT; | |
3650 | if (INTVAL (operands[2]) == 0xffff) | |
3651 | return "not%.w %0"; | |
3652 | return "eor%.w %2,%0"; | |
3653 | } | |
3654 | if (GET_CODE (operands[2]) == CONST_INT | |
3655 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3656 | && (DATA_REG_P (operands[0]) | |
3657 | || offsettable_memref_p (operands[0]))) | |
3658 | { | |
3659 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3660 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3661 | else |
3662 | { | |
b72f00af | 3663 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3664 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3665 | } |
3666 | CC_STATUS_INIT; | |
3667 | return "bchg %1,%0"; | |
3668 | } | |
3669 | return "eor%.l %2,%0"; | |
3670 | } | |
7c262518 | 3671 | |
45849738 BI |
3672 | #ifdef M68K_TARGET_COFF |
3673 | ||
3674 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
3675 | ||
3676 | static void | |
c18a5b6c MM |
3677 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
3678 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
3679 | { |
3680 | char flagchar; | |
3681 | ||
3682 | if (flags & SECTION_WRITE) | |
3683 | flagchar = 'd'; | |
3684 | else | |
3685 | flagchar = 'x'; | |
3686 | ||
3687 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
3688 | } | |
3689 | ||
3690 | #endif /* M68K_TARGET_COFF */ | |
3691 | ||
c590b625 | 3692 | static void |
8a4a2253 BI |
3693 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
3694 | HOST_WIDE_INT delta, | |
3695 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
3696 | tree function) | |
483ab821 | 3697 | { |
c590b625 RH |
3698 | rtx xops[1]; |
3699 | const char *fmt; | |
3700 | ||
3701 | if (delta > 0 && delta <= 8) | |
a0a7fbc9 AS |
3702 | asm_fprintf (file, (MOTOROLA |
3703 | ? "\taddq.l %I%d,4(%Rsp)\n" | |
3704 | : "\taddql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3705 | (int) delta); |
c590b625 | 3706 | else if (delta < 0 && delta >= -8) |
a0a7fbc9 AS |
3707 | asm_fprintf (file, (MOTOROLA |
3708 | ? "\tsubq.l %I%d,4(%Rsp)\n" | |
3709 | : "\tsubql %I%d,%Rsp@(4)\n"), | |
e6d98cb0 | 3710 | (int) -delta); |
5050d266 PB |
3711 | else if (TARGET_COLDFIRE) |
3712 | { | |
3713 | /* ColdFire can't add/sub a constant to memory unless it is in | |
3714 | the range of addq/subq. So load the value into %d0 and | |
3715 | then add it to 4(%sp). */ | |
3716 | if (delta >= -128 && delta <= 127) | |
a0a7fbc9 AS |
3717 | asm_fprintf (file, (MOTOROLA |
3718 | ? "\tmoveq.l %I%wd,%Rd0\n" | |
3719 | : "\tmoveql %I%wd,%Rd0\n"), | |
3720 | delta); | |
5050d266 | 3721 | else |
a0a7fbc9 AS |
3722 | asm_fprintf (file, (MOTOROLA |
3723 | ? "\tmove.l %I%wd,%Rd0\n" | |
3724 | : "\tmovel %I%wd,%Rd0\n"), | |
3725 | delta); | |
3726 | asm_fprintf (file, (MOTOROLA | |
3727 | ? "\tadd.l %Rd0,4(%Rsp)\n" | |
3728 | : "\taddl %Rd0,%Rsp@(4)\n")); | |
5050d266 | 3729 | } |
c590b625 | 3730 | else |
a0a7fbc9 AS |
3731 | asm_fprintf (file, (MOTOROLA |
3732 | ? "\tadd.l %I%wd,4(%Rsp)\n" | |
3733 | : "\taddl %I%wd,%Rsp@(4)\n"), | |
e6d98cb0 | 3734 | delta); |
c590b625 RH |
3735 | |
3736 | xops[0] = DECL_RTL (function); | |
3737 | ||
3738 | /* Logic taken from call patterns in m68k.md. */ | |
3739 | if (flag_pic) | |
3740 | { | |
3741 | if (TARGET_PCREL) | |
3742 | fmt = "bra.l %o0"; | |
a0a7fbc9 | 3743 | else if (flag_pic == 1 || TARGET_68020) |
c590b625 | 3744 | { |
e6d98cb0 | 3745 | if (MOTOROLA) |
a0a7fbc9 AS |
3746 | { |
3747 | #if defined (USE_GAS) | |
3748 | fmt = "bra.l %0@PLTPC"; | |
c590b625 | 3749 | #else |
a0a7fbc9 | 3750 | fmt = "bra %0@PLTPC"; |
c590b625 | 3751 | #endif |
a0a7fbc9 | 3752 | } |
e6d98cb0 | 3753 | else /* !MOTOROLA */ |
a0a7fbc9 | 3754 | { |
c590b625 | 3755 | #ifdef USE_GAS |
a0a7fbc9 | 3756 | fmt = "bra.l %0"; |
c590b625 | 3757 | #else |
a0a7fbc9 | 3758 | fmt = "jra %0,a1"; |
c590b625 | 3759 | #endif |
a0a7fbc9 | 3760 | } |
c590b625 | 3761 | } |
a2ef3db7 BI |
3762 | else if (optimize_size || TARGET_ID_SHARED_LIBRARY) |
3763 | fmt = "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)"; | |
3764 | else | |
a8c253d0 | 3765 | fmt = "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)"; |
c590b625 RH |
3766 | } |
3767 | else | |
3768 | { | |
e6d98cb0 | 3769 | #if MOTOROLA && !defined (USE_GAS) |
c590b625 | 3770 | fmt = "jmp %0"; |
c590b625 | 3771 | #else |
1d6302b1 | 3772 | fmt = "jra %0"; |
c590b625 RH |
3773 | #endif |
3774 | } | |
3775 | ||
3776 | output_asm_insn (fmt, xops); | |
483ab821 | 3777 | } |
8636be86 KH |
3778 | |
3779 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
3780 | ||
3781 | static rtx | |
3782 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
3783 | int incoming ATTRIBUTE_UNUSED) | |
3784 | { | |
3785 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
3786 | } | |
cfca21cb PB |
3787 | |
3788 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
3789 | int | |
3790 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
3791 | unsigned int new_reg) | |
3792 | { | |
3793 | ||
3794 | /* Interrupt functions can only use registers that have already been | |
3795 | saved by the prologue, even if they would normally be | |
3796 | call-clobbered. */ | |
3797 | ||
3798 | if (m68k_interrupt_function_p (current_function_decl) | |
3799 | && !regs_ever_live[new_reg]) | |
3800 | return 0; | |
3801 | ||
3802 | return 1; | |
3803 | } | |
70028b61 PB |
3804 | |
3805 | /* Value is true if hard register REGNO can hold a value of machine-mode MODE. | |
3806 | On the 68000, the cpu registers can hold any mode except bytes in address | |
3807 | registers, but the 68881 registers can hold only SFmode or DFmode. */ | |
3808 | bool | |
3809 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
3810 | { | |
3811 | if (regno < 8) | |
3812 | { | |
a0a7fbc9 AS |
3813 | /* Data Registers, can hold aggregate if fits in. */ |
3814 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
3815 | return true; | |
70028b61 PB |
3816 | } |
3817 | else if (regno < 16) | |
3818 | { | |
a0a7fbc9 AS |
3819 | /* Address Registers, can't hold bytes, can hold aggregate if |
3820 | fits in. */ | |
3821 | if (GET_MODE_SIZE (mode) == 1) | |
3822 | return false; | |
3823 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) | |
3824 | return true; | |
70028b61 PB |
3825 | } |
3826 | else if (regno < 24) | |
3827 | { | |
3828 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
3829 | smaller. */ |
3830 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
3831 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 3832 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 3833 | return true; |
70028b61 PB |
3834 | } |
3835 | return false; | |
3836 | } | |
dcc21c4c PB |
3837 | |
3838 | /* Return floating point values in a 68881 register. This makes 68881 code | |
3839 | a little bit faster. It also makes -msoft-float code incompatible with | |
3840 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 3841 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
3842 | If there is need for a hard-float ABI it is probably worth doing it |
3843 | properly and also passing function arguments in FP registers. */ | |
3844 | rtx | |
3845 | m68k_libcall_value (enum machine_mode mode) | |
3846 | { | |
3847 | switch (mode) { | |
3848 | case SFmode: | |
3849 | case DFmode: | |
3850 | case XFmode: | |
3851 | if (TARGET_68881) | |
3852 | return gen_rtx_REG (mode, 16); | |
3853 | break; | |
3854 | default: | |
3855 | break; | |
3856 | } | |
3857 | return gen_rtx_REG (mode, 0); | |
3858 | } | |
3859 | ||
3860 | rtx | |
3861 | m68k_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
3862 | { | |
3863 | enum machine_mode mode; | |
3864 | ||
3865 | mode = TYPE_MODE (valtype); | |
3866 | switch (mode) { | |
3867 | case SFmode: | |
3868 | case DFmode: | |
3869 | case XFmode: | |
3870 | if (TARGET_68881) | |
3871 | return gen_rtx_REG (mode, 16); | |
3872 | break; | |
3873 | default: | |
3874 | break; | |
3875 | } | |
3876 | ||
3877 | /* If the function returns a pointer, push that into %a0 */ | |
3878 | if (POINTER_TYPE_P (valtype)) | |
3879 | return gen_rtx_REG (mode, 8); | |
3880 | else | |
3881 | return gen_rtx_REG (mode, 0); | |
3882 | } |