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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
a8c253d0 | 3 | 2001, 2003, 2004, 2005, 2006 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
20 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
79e68feb | 22 | |
79e68feb | 23 | #include "config.h" |
f5220a5d | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
da932f04 | 27 | #include "tree.h" |
79e68feb | 28 | #include "rtl.h" |
49ad7cfa | 29 | #include "function.h" |
79e68feb RS |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
79e68feb RS |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
1d8eaa6b | 37 | #include "recog.h" |
f5220a5d | 38 | #include "toplev.h" |
6d5f49b2 RH |
39 | #include "expr.h" |
40 | #include "reload.h" | |
5505f548 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
2cc07db4 | 44 | #include "debug.h" |
79e68feb RS |
45 | #include "flags.h" |
46 | ||
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
e6d98cb0 BI |
59 | /* The ASM_DOT macro allows easy string pasting to handle the differences |
60 | between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't | |
61 | support the %. option. */ | |
62 | #if MOTOROLA | |
63 | # define ASM_DOT "." | |
64 | # define ASM_DOTW ".w" | |
65 | # define ASM_DOTL ".l" | |
66 | #else | |
67 | # define ASM_DOT "" | |
68 | # define ASM_DOTW "" | |
69 | # define ASM_DOTL "" | |
70 | #endif | |
71 | ||
72 | ||
a40ed0f3 KH |
73 | /* The minimum number of integer registers that we want to save with the |
74 | movem instruction. Using two movel instructions instead of a single | |
75 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
76 | code size. */ | |
77 | #define MIN_MOVEM_REGS 3 | |
78 | ||
79 | /* The minimum number of floating point registers that we want to save | |
80 | with the fmovem instruction. */ | |
81 | #define MIN_FMOVEM_REGS 1 | |
82 | ||
ff482c8d | 83 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
84 | struct m68k_frame |
85 | { | |
86 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 87 | HOST_WIDE_INT offset; |
3d74bc09 BI |
88 | |
89 | /* Offset of FPU registers. */ | |
90 | HOST_WIDE_INT foffset; | |
91 | ||
92 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 93 | HOST_WIDE_INT size; |
3d74bc09 BI |
94 | |
95 | /* Data and address register. */ | |
48ed72a4 PB |
96 | int reg_no; |
97 | unsigned int reg_mask; | |
3d74bc09 BI |
98 | |
99 | /* FPU registers. */ | |
48ed72a4 PB |
100 | int fpu_no; |
101 | unsigned int fpu_mask; | |
3d74bc09 BI |
102 | |
103 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
104 | HOST_WIDE_INT frame_pointer_offset; |
105 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
106 | |
107 | /* Function which the above information refers to. */ | |
108 | int funcdef_no; | |
48ed72a4 PB |
109 | }; |
110 | ||
3d74bc09 BI |
111 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
112 | static struct m68k_frame current_frame; | |
113 | ||
fc2241eb RS |
114 | /* Structure describing an m68k address. |
115 | ||
116 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
117 | with null fields evaluating to 0. Here: | |
118 | ||
119 | - BASE satisfies m68k_legitimate_base_reg_p | |
120 | - INDEX satisfies m68k_legitimate_index_reg_p | |
121 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
122 | ||
123 | INDEX is either HImode or SImode. The other fields are SImode. | |
124 | ||
125 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
126 | the address is (BASE)+. */ | |
127 | struct m68k_address { | |
128 | enum rtx_code code; | |
129 | rtx base; | |
130 | rtx index; | |
131 | rtx offset; | |
132 | int scale; | |
133 | }; | |
134 | ||
4af06170 | 135 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
136 | static rtx find_addr_reg (rtx); |
137 | static const char *singlemove_string (rtx *); | |
45849738 | 138 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 139 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 140 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
141 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
142 | HOST_WIDE_INT, tree); | |
8636be86 | 143 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
144 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
145 | tree args, int flags, | |
146 | bool *no_add_attrs); | |
3d74bc09 | 147 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 148 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
f7e70894 | 149 | static bool m68k_ok_for_sibcall_p (tree, tree); |
8a4a2253 | 150 | static bool m68k_rtx_costs (rtx, int, int, int *); |
79e68feb RS |
151 | \f |
152 | ||
a2ef3db7 | 153 | /* Specify the identification number of the library being built */ |
4af06170 | 154 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 155 | |
2b3600ac JL |
156 | /* Nonzero if the last compare/test insn had FP operands. The |
157 | sCC expanders peek at this to determine what to do for the | |
158 | 68060, which has no fsCC instructions. */ | |
159 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
160 | \f |
161 | /* Initialize the GCC target structure. */ | |
301d03af RS |
162 | |
163 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
164 | #undef TARGET_ASM_ALIGNED_HI_OP | |
165 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
166 | #endif | |
167 | ||
168 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
169 | #undef TARGET_ASM_BYTE_OP | |
170 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
171 | #undef TARGET_ASM_ALIGNED_HI_OP | |
172 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
173 | #undef TARGET_ASM_ALIGNED_SI_OP | |
174 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
175 | #endif | |
176 | ||
177 | #if INT_OP_GROUP == INT_OP_DC | |
178 | #undef TARGET_ASM_BYTE_OP | |
179 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
180 | #undef TARGET_ASM_ALIGNED_HI_OP | |
181 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
182 | #undef TARGET_ASM_ALIGNED_SI_OP | |
183 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
184 | #endif | |
185 | ||
186 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
187 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
188 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
189 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
190 | ||
c590b625 RH |
191 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
192 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 | 193 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
4ab870f5 | 194 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
c590b625 | 195 | |
1bc7c5b6 ZW |
196 | #undef TARGET_ASM_FILE_START_APP_OFF |
197 | #define TARGET_ASM_FILE_START_APP_OFF true | |
198 | ||
4af06170 | 199 | #undef TARGET_DEFAULT_TARGET_FLAGS |
900ec02d | 200 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT |
4af06170 RS |
201 | #undef TARGET_HANDLE_OPTION |
202 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
203 | ||
3c50106f RH |
204 | #undef TARGET_RTX_COSTS |
205 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
206 | ||
48ed72a4 PB |
207 | #undef TARGET_ATTRIBUTE_TABLE |
208 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
209 | ||
8636be86 KH |
210 | #undef TARGET_PROMOTE_PROTOTYPES |
211 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
212 | ||
213 | #undef TARGET_STRUCT_VALUE_RTX | |
214 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
215 | ||
7ffb5e78 RS |
216 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
217 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p | |
218 | ||
f7e70894 RS |
219 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
220 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
221 | ||
48ed72a4 PB |
222 | static const struct attribute_spec m68k_attribute_table[] = |
223 | { | |
224 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
225 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, | |
226 | { NULL, 0, 0, false, false, false, NULL } | |
227 | }; | |
228 | ||
f6897b10 | 229 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 230 | \f |
900ec02d JB |
231 | /* Base flags for 68k ISAs. */ |
232 | #define FL_FOR_isa_00 FL_ISA_68000 | |
233 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
234 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
235 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
236 | not to. */ | |
237 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
238 | | FL_BITFIELD | FL_68881) | |
239 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
240 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
241 | ||
242 | /* Base flags for ColdFire ISAs. */ | |
243 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
244 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
245 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
246 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
247 | #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP) | |
248 | ||
249 | enum m68k_isa | |
250 | { | |
251 | /* Traditional 68000 instruction sets. */ | |
252 | isa_00, | |
253 | isa_10, | |
254 | isa_20, | |
255 | isa_40, | |
256 | isa_cpu32, | |
257 | /* ColdFire instruction set variants. */ | |
258 | isa_a, | |
259 | isa_aplus, | |
260 | isa_b, | |
261 | isa_c, | |
262 | isa_max | |
263 | }; | |
264 | ||
265 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
266 | struct m68k_target_selection | |
267 | { | |
268 | /* The argument being described. */ | |
269 | const char *name; | |
270 | ||
271 | /* For -mcpu, this is the device selected by the option. | |
272 | For -mtune and -march, it is a representative device | |
273 | for the microarchitecture or ISA respectively. */ | |
274 | enum target_device device; | |
275 | ||
276 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
277 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
278 | const char *family; | |
279 | enum uarch_type microarch; | |
280 | enum m68k_isa isa; | |
281 | unsigned long flags; | |
282 | }; | |
283 | ||
284 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
285 | static const struct m68k_target_selection all_devices[] = | |
286 | { | |
287 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
288 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
289 | #include "m68k-devices.def" | |
290 | #undef M68K_DEVICE | |
291 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
292 | }; | |
293 | ||
294 | /* A list of all ISAs, mapping each one to a representative device. | |
295 | Used for -march selection. */ | |
296 | static const struct m68k_target_selection all_isas[] = | |
297 | { | |
298 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
299 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
300 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
301 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
302 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
303 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
304 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
305 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
306 | | FL_CF_HWDIV) }, | |
307 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
308 | | FL_CF_HWDIV) }, | |
309 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
310 | { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c | |
311 | | FL_CF_FPU | |
312 | | FL_CF_EMAC) }, | |
313 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
314 | }; | |
315 | ||
316 | /* A list of all microarchitectures, mapping each one to a representative | |
317 | device. Used for -mtune selection. */ | |
318 | static const struct m68k_target_selection all_microarchs[] = | |
319 | { | |
320 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
321 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
322 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
323 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
324 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
325 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
326 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
327 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
328 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
329 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, | |
330 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
331 | | FL_CF_HWDIV) }, | |
332 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
333 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
334 | | FL_CF_USP | |
335 | | FL_CF_EMAC | |
336 | | FL_CF_FPU) }, | |
337 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
338 | }; | |
339 | \f | |
340 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
341 | or null for options that have not been used. */ | |
342 | const struct m68k_target_selection *m68k_cpu_entry; | |
343 | const struct m68k_target_selection *m68k_arch_entry; | |
344 | const struct m68k_target_selection *m68k_tune_entry; | |
345 | ||
346 | /* Which CPU we are generating code for. */ | |
347 | enum target_device m68k_cpu; | |
348 | ||
349 | /* Which microarchitecture to tune for. */ | |
350 | enum uarch_type m68k_tune; | |
351 | ||
352 | /* Which FPU to use. */ | |
353 | enum fpu_type m68k_fpu; | |
4af06170 | 354 | |
900ec02d JB |
355 | /* The set of FL_* flags that apply to the target processor. */ |
356 | unsigned int m68k_cpu_flags; | |
29ca003a RS |
357 | |
358 | /* Asm templates for calling or jumping to an arbitrary symbolic address, | |
359 | or NULL if such calls or jumps are not supported. The address is held | |
360 | in operand 0. */ | |
361 | const char *m68k_symbolic_call; | |
362 | const char *m68k_symbolic_jump; | |
900ec02d JB |
363 | \f |
364 | /* See whether TABLE has an entry with name NAME. Return true and | |
365 | store the entry in *ENTRY if so, otherwise return false and | |
366 | leave *ENTRY alone. */ | |
367 | ||
368 | static bool | |
369 | m68k_find_selection (const struct m68k_target_selection **entry, | |
370 | const struct m68k_target_selection *table, | |
371 | const char *name) | |
372 | { | |
373 | size_t i; | |
374 | ||
375 | for (i = 0; table[i].name; i++) | |
376 | if (strcmp (table[i].name, name) == 0) | |
377 | { | |
378 | *entry = table + i; | |
379 | return true; | |
380 | } | |
381 | return false; | |
382 | } | |
4af06170 RS |
383 | |
384 | /* Implement TARGET_HANDLE_OPTION. */ | |
385 | ||
386 | static bool | |
387 | m68k_handle_option (size_t code, const char *arg, int value) | |
388 | { | |
389 | switch (code) | |
390 | { | |
900ec02d JB |
391 | case OPT_march_: |
392 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
393 | ||
394 | case OPT_mcpu_: | |
395 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
396 | ||
397 | case OPT_mtune_: | |
398 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
399 | ||
4af06170 | 400 | case OPT_m5200: |
900ec02d | 401 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
402 | |
403 | case OPT_m5206e: | |
900ec02d | 404 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
405 | |
406 | case OPT_m528x: | |
900ec02d | 407 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
408 | |
409 | case OPT_m5307: | |
900ec02d | 410 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
411 | |
412 | case OPT_m5407: | |
900ec02d | 413 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 414 | |
dcc21c4c | 415 | case OPT_mcfv4e: |
900ec02d | 416 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 417 | |
4af06170 RS |
418 | case OPT_m68000: |
419 | case OPT_mc68000: | |
900ec02d | 420 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 421 | |
3197c489 | 422 | case OPT_m68010: |
900ec02d | 423 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 424 | |
4af06170 RS |
425 | case OPT_m68020: |
426 | case OPT_mc68020: | |
900ec02d | 427 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
428 | |
429 | case OPT_m68020_40: | |
900ec02d JB |
430 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
431 | "68020-40") | |
432 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
433 | |
434 | case OPT_m68020_60: | |
900ec02d JB |
435 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
436 | "68020-60") | |
437 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
438 | |
439 | case OPT_m68030: | |
900ec02d | 440 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
441 | |
442 | case OPT_m68040: | |
900ec02d | 443 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
444 | |
445 | case OPT_m68060: | |
900ec02d | 446 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
447 | |
448 | case OPT_m68302: | |
900ec02d | 449 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
450 | |
451 | case OPT_m68332: | |
452 | case OPT_mcpu32: | |
900ec02d | 453 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
454 | |
455 | case OPT_mshared_library_id_: | |
456 | if (value > MAX_LIBRARY_ID) | |
457 | error ("-mshared-library-id=%s is not between 0 and %d", | |
458 | arg, MAX_LIBRARY_ID); | |
459 | else | |
460 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
461 | return true; | |
462 | ||
463 | default: | |
464 | return true; | |
465 | } | |
466 | } | |
467 | ||
ef1dbfb0 RK |
468 | /* Sometimes certain combinations of command options do not make |
469 | sense on a particular target machine. You can define a macro | |
470 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
471 | defined, is executed once just after all the command options have | |
472 | been parsed. | |
473 | ||
474 | Don't use this macro to turn on various extra optimizations for | |
475 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
476 | ||
477 | void | |
8a4a2253 | 478 | override_options (void) |
ef1dbfb0 | 479 | { |
900ec02d JB |
480 | const struct m68k_target_selection *entry; |
481 | unsigned long target_mask; | |
482 | ||
483 | /* User can choose: | |
484 | ||
485 | -mcpu= | |
486 | -march= | |
487 | -mtune= | |
488 | ||
489 | -march=ARCH should generate code that runs any processor | |
490 | implementing architecture ARCH. -mcpu=CPU should override -march | |
491 | and should generate code that runs on processor CPU, making free | |
492 | use of any instructions that CPU understands. -mtune=UARCH applies | |
9f5ed61a | 493 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
900ec02d JB |
494 | not change the target architecture. */ |
495 | if (m68k_cpu_entry) | |
496 | { | |
497 | /* Complain if the -march setting is for a different microarchitecture, | |
498 | or includes flags that the -mcpu setting doesn't. */ | |
499 | if (m68k_arch_entry | |
500 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
501 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
502 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
503 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
504 | ||
505 | entry = m68k_cpu_entry; | |
506 | } | |
507 | else | |
508 | entry = m68k_arch_entry; | |
509 | ||
510 | if (!entry) | |
511 | entry = all_devices + TARGET_CPU_DEFAULT; | |
512 | ||
513 | m68k_cpu_flags = entry->flags; | |
514 | ||
515 | /* Use the architecture setting to derive default values for | |
516 | certain flags. */ | |
517 | target_mask = 0; | |
518 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) | |
519 | target_mask |= MASK_BITFIELD; | |
520 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
521 | target_mask |= MASK_CF_HWDIV; | |
522 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
523 | target_mask |= MASK_HARD_FLOAT; | |
524 | target_flags |= target_mask & ~target_flags_explicit; | |
525 | ||
526 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
527 | m68k_cpu = entry->device; | |
528 | if (m68k_tune_entry) | |
529 | m68k_tune = m68k_tune_entry->microarch; | |
530 | #ifdef M68K_DEFAULT_TUNE | |
531 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
532 | m68k_tune = M68K_DEFAULT_TUNE; | |
533 | #endif | |
534 | else | |
535 | m68k_tune = entry->microarch; | |
536 | ||
537 | /* Set the type of FPU. */ | |
538 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
539 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
540 | : FPUTYPE_68881); | |
541 | ||
58145e4d RS |
542 | if (TARGET_COLDFIRE_FPU) |
543 | { | |
544 | REAL_MODE_FORMAT (SFmode) = &coldfire_single_format; | |
545 | REAL_MODE_FORMAT (DFmode) = &coldfire_double_format; | |
546 | } | |
547 | ||
a2ef3db7 BI |
548 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
549 | * both specified together. Doing so simply doesn't make sense. | |
550 | */ | |
551 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
552 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
553 | ||
554 | /* If we're generating code for a separate A5 relative data segment, | |
555 | * we've got to enable -fPIC as well. This might be relaxable to | |
556 | * -fpic but it hasn't been tested properly. | |
557 | */ | |
558 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
559 | flag_pic = 2; | |
560 | ||
abe92a04 RS |
561 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
562 | error if the target does not support them. */ | |
563 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
564 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
565 | |
566 | /* ??? A historic way of turning on pic, or is this intended to | |
567 | be an embedded thing that doesn't have the same name binding | |
568 | significance that it does on hosted ELF systems? */ | |
569 | if (TARGET_PCREL && flag_pic == 0) | |
570 | flag_pic = 1; | |
571 | ||
29ca003a RS |
572 | if (!flag_pic) |
573 | { | |
574 | #if MOTOROLA && !defined (USE_GAS) | |
575 | m68k_symbolic_call = "jsr %a0"; | |
576 | m68k_symbolic_jump = "jmp %a0"; | |
577 | #else | |
578 | m68k_symbolic_call = "jbsr %a0"; | |
579 | m68k_symbolic_jump = "jra %a0"; | |
580 | #endif | |
581 | } | |
582 | else if (TARGET_ID_SHARED_LIBRARY) | |
583 | /* All addresses must be loaded from the GOT. */ | |
584 | ; | |
585 | else if (TARGET_68020 || TARGET_ISAB) | |
586 | { | |
587 | if (TARGET_PCREL) | |
588 | { | |
589 | m68k_symbolic_call = "bsr.l %c0"; | |
590 | m68k_symbolic_jump = "bra.l %c0"; | |
591 | } | |
592 | else | |
593 | { | |
594 | #if defined(USE_GAS) | |
595 | m68k_symbolic_call = "bsr.l %p0"; | |
596 | m68k_symbolic_jump = "bra.l %p0"; | |
597 | #else | |
598 | m68k_symbolic_call = "bsr %p0"; | |
599 | m68k_symbolic_jump = "bra %p0"; | |
600 | #endif | |
601 | } | |
602 | /* Turn off function cse if we are doing PIC. We always want | |
603 | function call to be done as `bsr foo@PLTPC'. */ | |
604 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
605 | clear how intentional that is. */ | |
606 | flag_no_function_cse = 1; | |
607 | } | |
adf2ac37 RH |
608 | |
609 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 610 | } |
7eb4f044 NS |
611 | |
612 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the | |
613 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
614 | if -mcpu was not passed. */ | |
615 | ||
616 | const char * | |
617 | m68k_cpp_cpu_ident (const char *prefix) | |
618 | { | |
619 | if (!m68k_cpu_entry) | |
620 | return NULL; | |
621 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
622 | } | |
623 | ||
624 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
625 | given argument and NAME is the name of the representative device for | |
626 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
627 | ||
628 | const char * | |
629 | m68k_cpp_cpu_family (const char *prefix) | |
630 | { | |
631 | if (!m68k_cpu_entry) | |
632 | return NULL; | |
633 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
634 | } | |
79e68feb | 635 | \f |
48ed72a4 PB |
636 | /* Return nonzero if FUNC is an interrupt function as specified by the |
637 | "interrupt_handler" attribute. */ | |
a40ed0f3 KH |
638 | bool |
639 | m68k_interrupt_function_p (tree func) | |
48ed72a4 PB |
640 | { |
641 | tree a; | |
642 | ||
643 | if (TREE_CODE (func) != FUNCTION_DECL) | |
644 | return false; | |
645 | ||
646 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); | |
647 | return (a != NULL_TREE); | |
648 | } | |
649 | ||
650 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
651 | struct attribute_spec.handler. */ | |
652 | static tree | |
653 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
654 | tree args ATTRIBUTE_UNUSED, | |
655 | int flags ATTRIBUTE_UNUSED, | |
656 | bool *no_add_attrs) | |
657 | { | |
658 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
659 | { | |
5c498b10 | 660 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
661 | IDENTIFIER_POINTER (name)); |
662 | *no_add_attrs = true; | |
663 | } | |
664 | ||
665 | return NULL_TREE; | |
666 | } | |
860c4900 BI |
667 | |
668 | static void | |
3d74bc09 | 669 | m68k_compute_frame_layout (void) |
860c4900 BI |
670 | { |
671 | int regno, saved; | |
a40ed0f3 | 672 | unsigned int mask; |
48ed72a4 | 673 | bool interrupt_handler = m68k_interrupt_function_p (current_function_decl); |
860c4900 | 674 | |
3d74bc09 BI |
675 | /* Only compute the frame once per function. |
676 | Don't cache information until reload has been completed. */ | |
677 | if (current_frame.funcdef_no == current_function_funcdef_no | |
678 | && reload_completed) | |
679 | return; | |
680 | ||
681 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 | 682 | |
a40ed0f3 | 683 | mask = saved = 0; |
860c4900 | 684 | for (regno = 0; regno < 16; regno++) |
48ed72a4 | 685 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 686 | { |
a40ed0f3 | 687 | mask |= 1 << (regno - D0_REG); |
860c4900 BI |
688 | saved++; |
689 | } | |
3d74bc09 BI |
690 | current_frame.offset = saved * 4; |
691 | current_frame.reg_no = saved; | |
692 | current_frame.reg_mask = mask; | |
860c4900 | 693 | |
57047680 | 694 | current_frame.foffset = 0; |
a40ed0f3 | 695 | mask = saved = 0; |
dcc21c4c | 696 | if (TARGET_HARD_FLOAT) |
860c4900 | 697 | { |
860c4900 | 698 | for (regno = 16; regno < 24; regno++) |
3d74bc09 | 699 | if (m68k_save_reg (regno, interrupt_handler)) |
860c4900 | 700 | { |
a40ed0f3 | 701 | mask |= 1 << (regno - FP0_REG); |
860c4900 BI |
702 | saved++; |
703 | } | |
dcc21c4c | 704 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 705 | current_frame.offset += current_frame.foffset; |
860c4900 | 706 | } |
57047680 GN |
707 | current_frame.fpu_no = saved; |
708 | current_frame.fpu_mask = mask; | |
3d74bc09 BI |
709 | |
710 | /* Remember what function this frame refers to. */ | |
711 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
712 | } |
713 | ||
714 | HOST_WIDE_INT | |
715 | m68k_initial_elimination_offset (int from, int to) | |
716 | { | |
42b67c06 PB |
717 | int argptr_offset; |
718 | /* The arg pointer points 8 bytes before the start of the arguments, | |
719 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
720 | frame pointer in most frames. */ | |
721 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 722 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 723 | return argptr_offset; |
860c4900 | 724 | |
3d74bc09 | 725 | m68k_compute_frame_layout (); |
860c4900 | 726 | |
4761e388 NS |
727 | gcc_assert (to == STACK_POINTER_REGNUM); |
728 | switch (from) | |
729 | { | |
a0a7fbc9 | 730 | case ARG_POINTER_REGNUM: |
42b67c06 | 731 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
732 | case FRAME_POINTER_REGNUM: |
733 | return current_frame.offset + current_frame.size; | |
734 | default: | |
735 | gcc_unreachable (); | |
736 | } | |
860c4900 BI |
737 | } |
738 | ||
97c55091 GN |
739 | /* Refer to the array `regs_ever_live' to determine which registers |
740 | to save; `regs_ever_live[I]' is nonzero if register number I | |
741 | is ever used in the function. This function is responsible for | |
742 | knowing which registers should not be saved even if used. | |
743 | Return true if we need to save REGNO. */ | |
744 | ||
48ed72a4 PB |
745 | static bool |
746 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 747 | { |
4ab870f5 | 748 | if (flag_pic && regno == PIC_REG) |
b86ba8a3 | 749 | { |
afcb440c RS |
750 | /* A function that receives a nonlocal goto must save all call-saved |
751 | registers. */ | |
752 | if (current_function_has_nonlocal_label) | |
753 | return true; | |
b86ba8a3 AT |
754 | if (current_function_uses_pic_offset_table) |
755 | return true; | |
6357eb0d RS |
756 | /* Reload may introduce constant pool references into a function |
757 | that thitherto didn't need a PIC register. Note that the test | |
758 | above will not catch that case because we will only set | |
759 | current_function_uses_pic_offset_table when emitting | |
760 | the address reloads. */ | |
761 | if (current_function_uses_const_pool) | |
762 | return true; | |
b86ba8a3 | 763 | } |
2cff4a6e AS |
764 | |
765 | if (current_function_calls_eh_return) | |
766 | { | |
767 | unsigned int i; | |
768 | for (i = 0; ; i++) | |
769 | { | |
770 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
771 | if (test == INVALID_REGNUM) | |
772 | break; | |
773 | if (test == regno) | |
48ed72a4 | 774 | return true; |
2cff4a6e AS |
775 | } |
776 | } | |
777 | ||
48ed72a4 PB |
778 | /* Fixed regs we never touch. */ |
779 | if (fixed_regs[regno]) | |
780 | return false; | |
781 | ||
782 | /* The frame pointer (if it is such) is handled specially. */ | |
783 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
784 | return false; | |
785 | ||
786 | /* Interrupt handlers must also save call_used_regs | |
787 | if they are live or when calling nested functions. */ | |
788 | if (interrupt_handler) | |
a0a7fbc9 AS |
789 | { |
790 | if (regs_ever_live[regno]) | |
791 | return true; | |
48ed72a4 | 792 | |
a0a7fbc9 AS |
793 | if (!current_function_is_leaf && call_used_regs[regno]) |
794 | return true; | |
795 | } | |
48ed72a4 PB |
796 | |
797 | /* Never need to save registers that aren't touched. */ | |
798 | if (!regs_ever_live[regno]) | |
799 | return false; | |
800 | ||
b2e08ed4 | 801 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 802 | return !call_used_regs[regno]; |
2cff4a6e AS |
803 | } |
804 | ||
a40ed0f3 KH |
805 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
806 | the lowest memory address. COUNT is the number of registers to be | |
807 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
808 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
809 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
810 | (if !STORE_P) operation. */ | |
811 | ||
812 | static rtx | |
813 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, | |
814 | unsigned int count, unsigned int regno, | |
815 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
816 | { | |
817 | int i; | |
818 | rtx body, addr, src, operands[2]; | |
819 | enum machine_mode mode; | |
820 | ||
821 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
822 | mode = reg_raw_mode[regno]; | |
823 | i = 0; | |
824 | ||
825 | if (adjust_stack_p) | |
826 | { | |
827 | src = plus_constant (base, (count | |
828 | * GET_MODE_SIZE (mode) | |
829 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
830 | XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src); | |
831 | } | |
832 | ||
833 | for (; mask != 0; mask >>= 1, regno++) | |
834 | if (mask & 1) | |
835 | { | |
836 | addr = plus_constant (base, offset); | |
837 | operands[!store_p] = gen_frame_mem (mode, addr); | |
838 | operands[store_p] = gen_rtx_REG (mode, regno); | |
839 | XVECEXP (body, 0, i++) | |
840 | = gen_rtx_SET (VOIDmode, operands[0], operands[1]); | |
841 | offset += GET_MODE_SIZE (mode); | |
842 | } | |
843 | gcc_assert (i == XVECLEN (body, 0)); | |
844 | ||
845 | return emit_insn (body); | |
846 | } | |
847 | ||
848 | /* Make INSN a frame-related instruction. */ | |
79e68feb | 849 | |
08c148a8 | 850 | static void |
a40ed0f3 KH |
851 | m68k_set_frame_related (rtx insn) |
852 | { | |
853 | rtx body; | |
854 | int i; | |
855 | ||
856 | RTX_FRAME_RELATED_P (insn) = 1; | |
857 | body = PATTERN (insn); | |
858 | if (GET_CODE (body) == PARALLEL) | |
859 | for (i = 0; i < XVECLEN (body, 0); i++) | |
860 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
861 | } | |
862 | ||
863 | /* Emit RTL for the "prologue" define_expand. */ | |
864 | ||
865 | void | |
866 | m68k_expand_prologue (void) | |
79e68feb | 867 | { |
860c4900 | 868 | HOST_WIDE_INT fsize_with_regs; |
a40ed0f3 | 869 | rtx limit, src, dest, insn; |
3d74bc09 | 870 | |
a40ed0f3 | 871 | m68k_compute_frame_layout (); |
3d74bc09 | 872 | |
a157febd GK |
873 | /* If the stack limit is a symbol, we can check it here, |
874 | before actually allocating the space. */ | |
875 | if (current_function_limit_stack | |
876 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
a40ed0f3 KH |
877 | { |
878 | limit = plus_constant (stack_limit_rtx, current_frame.size + 4); | |
879 | if (!LEGITIMATE_CONSTANT_P (limit)) | |
880 | { | |
881 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
882 | limit = gen_rtx_REG (Pmode, D0_REG); | |
883 | } | |
884 | emit_insn (gen_cmpsi (stack_pointer_rtx, limit)); | |
885 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
886 | cc0_rtx, const0_rtx), | |
887 | const1_rtx)); | |
888 | } | |
79e68feb | 889 | |
a89e3f21 | 890 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
891 | if (TARGET_COLDFIRE) |
892 | { | |
a40ed0f3 KH |
893 | /* ColdFire's move multiple instructions do not allow pre-decrement |
894 | addressing. Add the size of movem saves to the initial stack | |
895 | allocation instead. */ | |
896 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
897 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
898 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
899 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 900 | } |
860c4900 | 901 | |
79e68feb RS |
902 | if (frame_pointer_needed) |
903 | { | |
a40ed0f3 | 904 | if (fsize_with_regs == 0 && TUNE_68040) |
79e68feb | 905 | { |
a40ed0f3 KH |
906 | /* On the 68040, two separate moves are faster than link.w 0. */ |
907 | dest = gen_frame_mem (Pmode, | |
908 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
909 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
910 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
911 | stack_pointer_rtx)); | |
79e68feb | 912 | } |
a40ed0f3 KH |
913 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
914 | m68k_set_frame_related | |
915 | (emit_insn (gen_link (frame_pointer_rtx, | |
916 | GEN_INT (-4 - fsize_with_regs)))); | |
d9e88af0 | 917 | else |
a40ed0f3 KH |
918 | { |
919 | m68k_set_frame_related | |
920 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
921 | m68k_set_frame_related | |
922 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
923 | stack_pointer_rtx, | |
924 | GEN_INT (-fsize_with_regs)))); | |
925 | } | |
d9e88af0 | 926 | } |
a40ed0f3 KH |
927 | else if (fsize_with_regs != 0) |
928 | m68k_set_frame_related | |
929 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
930 | stack_pointer_rtx, | |
931 | GEN_INT (-fsize_with_regs)))); | |
860c4900 | 932 | |
57047680 | 933 | if (current_frame.fpu_mask) |
79e68feb | 934 | { |
a40ed0f3 | 935 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
dcc21c4c | 936 | if (TARGET_68881) |
a40ed0f3 KH |
937 | m68k_set_frame_related |
938 | (m68k_emit_movem (stack_pointer_rtx, | |
939 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
940 | current_frame.fpu_no, FP0_REG, | |
941 | current_frame.fpu_mask, true, true)); | |
dcc21c4c PB |
942 | else |
943 | { | |
944 | int offset; | |
945 | ||
a40ed0f3 KH |
946 | /* If we're using moveml to save the integer registers, |
947 | the stack pointer will point to the bottom of the moveml | |
948 | save area. Find the stack offset of the first FP register. */ | |
949 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
950 | offset = 0; |
951 | else | |
a40ed0f3 KH |
952 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
953 | m68k_set_frame_related | |
954 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
955 | current_frame.fpu_no, FP0_REG, | |
956 | current_frame.fpu_mask, true, false)); | |
f277471f | 957 | } |
79e68feb | 958 | } |
99df2465 | 959 | |
01bbf777 | 960 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
961 | This has the disadvantage that it may be too late... */ |
962 | if (current_function_limit_stack) | |
963 | { | |
964 | if (REG_P (stack_limit_rtx)) | |
a40ed0f3 KH |
965 | { |
966 | emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx)); | |
967 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
968 | cc0_rtx, const0_rtx), | |
969 | const1_rtx)); | |
970 | } | |
a157febd | 971 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 972 | warning (0, "stack limit expression is not supported"); |
a157febd | 973 | } |
01bbf777 | 974 | |
a40ed0f3 | 975 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
79e68feb | 976 | { |
a40ed0f3 | 977 | /* Store each register separately in the same order moveml does. */ |
79e68feb RS |
978 | int i; |
979 | ||
a40ed0f3 KH |
980 | for (i = 16; i-- > 0; ) |
981 | if (current_frame.reg_mask & (1 << i)) | |
078e983e | 982 | { |
a40ed0f3 KH |
983 | src = gen_rtx_REG (SImode, D0_REG + i); |
984 | dest = gen_frame_mem (SImode, | |
985 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
986 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
078e983e | 987 | } |
79e68feb | 988 | } |
a40ed0f3 | 989 | else |
79e68feb | 990 | { |
9425fb04 | 991 | if (TARGET_COLDFIRE) |
a40ed0f3 KH |
992 | /* The required register save space has already been allocated. |
993 | The first register should be stored at (%sp). */ | |
994 | m68k_set_frame_related | |
995 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
996 | current_frame.reg_no, D0_REG, | |
997 | current_frame.reg_mask, true, false)); | |
afaff477 | 998 | else |
a40ed0f3 KH |
999 | m68k_set_frame_related |
1000 | (m68k_emit_movem (stack_pointer_rtx, | |
1001 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1002 | current_frame.reg_no, D0_REG, | |
1003 | current_frame.reg_mask, true, true)); | |
79e68feb | 1004 | } |
a40ed0f3 KH |
1005 | |
1006 | if (flag_pic | |
1007 | && !TARGET_SEP_DATA | |
4f44ecc0 | 1008 | && current_function_uses_pic_offset_table) |
79e68feb | 1009 | { |
a40ed0f3 KH |
1010 | insn = emit_insn (gen_load_got (pic_offset_table_rtx)); |
1011 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
1012 | const0_rtx, | |
1013 | REG_NOTES (insn)); | |
79e68feb RS |
1014 | } |
1015 | } | |
1016 | \f | |
413ac1b2 RS |
1017 | /* Return true if a simple (return) instruction is sufficient for this |
1018 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1019 | |
3d74bc09 | 1020 | bool |
a2bda628 | 1021 | m68k_use_return_insn (void) |
79e68feb | 1022 | { |
79e68feb | 1023 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1024 | return false; |
125ed86f | 1025 | |
a0a7fbc9 | 1026 | m68k_compute_frame_layout (); |
413ac1b2 | 1027 | return current_frame.offset == 0; |
79e68feb RS |
1028 | } |
1029 | ||
f7e70894 RS |
1030 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1031 | SIBCALL_P says which. | |
79e68feb RS |
1032 | |
1033 | The function epilogue should not depend on the current stack pointer! | |
1034 | It should use the frame pointer only, if there is a frame pointer. | |
1035 | This is mandatory because of alloca; we also take advantage of it to | |
1036 | omit stack adjustments before returning. */ | |
1037 | ||
a40ed0f3 | 1038 | void |
f7e70894 | 1039 | m68k_expand_epilogue (bool sibcall_p) |
08c148a8 | 1040 | { |
3d74bc09 | 1041 | HOST_WIDE_INT fsize, fsize_with_regs; |
a40ed0f3 | 1042 | bool big, restore_from_sp; |
3d74bc09 | 1043 | |
a0a7fbc9 | 1044 | m68k_compute_frame_layout (); |
3d74bc09 | 1045 | |
3d74bc09 | 1046 | fsize = current_frame.size; |
a40ed0f3 KH |
1047 | big = false; |
1048 | restore_from_sp = false; | |
3d74bc09 | 1049 | |
a40ed0f3 | 1050 | /* FIXME : current_function_is_leaf below is too strong. |
c67ddce5 | 1051 | What we really need to know there is if there could be pending |
7a1929e1 | 1052 | stack adjustment needed at that point. */ |
a40ed0f3 KH |
1053 | restore_from_sp = (!frame_pointer_needed |
1054 | || (!current_function_calls_alloca | |
1055 | && current_function_is_leaf)); | |
860c4900 BI |
1056 | |
1057 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1058 | popping the frame. */ |
860c4900 | 1059 | fsize_with_regs = fsize; |
dcc21c4c PB |
1060 | if (TARGET_COLDFIRE && restore_from_sp) |
1061 | { | |
a40ed0f3 KH |
1062 | /* ColdFire's move multiple instructions do not allow post-increment |
1063 | addressing. Add the size of movem loads to the final deallocation | |
1064 | instead. */ | |
1065 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1066 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1067 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1068 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1069 | } |
860c4900 | 1070 | |
3d74bc09 | 1071 | if (current_frame.offset + fsize >= 0x8000 |
a40ed0f3 | 1072 | && !restore_from_sp |
3d74bc09 | 1073 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1074 | { |
a40ed0f3 KH |
1075 | if (TARGET_COLDFIRE |
1076 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1077 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1078 | { | |
1079 | /* ColdFire's move multiple instructions do not support the | |
1080 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1081 | stack-based restore. */ | |
1082 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1083 | GEN_INT (-(current_frame.offset + fsize))); | |
1084 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1085 | gen_rtx_REG (Pmode, A1_REG), | |
1086 | frame_pointer_rtx)); | |
1087 | restore_from_sp = true; | |
1088 | } | |
1089 | else | |
1090 | { | |
1091 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1092 | fsize = 0; | |
1093 | big = true; | |
1094 | } | |
79e68feb | 1095 | } |
79e68feb | 1096 | |
a40ed0f3 KH |
1097 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1098 | { | |
1099 | /* Restore each register separately in the same order moveml does. */ | |
79e68feb | 1100 | int i; |
a40ed0f3 | 1101 | HOST_WIDE_INT offset; |
79e68feb | 1102 | |
a40ed0f3 | 1103 | offset = current_frame.offset + fsize; |
3d74bc09 BI |
1104 | for (i = 0; i < 16; i++) |
1105 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb | 1106 | { |
a40ed0f3 KH |
1107 | rtx addr; |
1108 | ||
1109 | if (big) | |
79e68feb | 1110 | { |
a40ed0f3 KH |
1111 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1112 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1113 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
1114 | addr = plus_constant (addr, -offset); | |
79e68feb | 1115 | } |
a40ed0f3 KH |
1116 | else if (restore_from_sp) |
1117 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1118 | else | |
1119 | addr = plus_constant (frame_pointer_rtx, -offset); | |
1120 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), | |
1121 | gen_frame_mem (SImode, addr)); | |
1122 | offset -= GET_MODE_SIZE (SImode); | |
1123 | } | |
79e68feb | 1124 | } |
3d74bc09 | 1125 | else if (current_frame.reg_mask) |
79e68feb | 1126 | { |
a40ed0f3 KH |
1127 | if (big) |
1128 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1129 | gen_rtx_REG (Pmode, A1_REG), | |
1130 | frame_pointer_rtx), | |
1131 | -(current_frame.offset + fsize), | |
1132 | current_frame.reg_no, D0_REG, | |
1133 | current_frame.reg_mask, false, false); | |
1134 | else if (restore_from_sp) | |
1135 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1136 | current_frame.reg_no, D0_REG, | |
1137 | current_frame.reg_mask, false, | |
1138 | !TARGET_COLDFIRE); | |
1139 | else | |
1140 | m68k_emit_movem (frame_pointer_rtx, | |
1141 | -(current_frame.offset + fsize), | |
1142 | current_frame.reg_no, D0_REG, | |
1143 | current_frame.reg_mask, false, false); | |
79e68feb | 1144 | } |
a40ed0f3 KH |
1145 | |
1146 | if (current_frame.fpu_no > 0) | |
79e68feb RS |
1147 | { |
1148 | if (big) | |
a40ed0f3 KH |
1149 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1150 | gen_rtx_REG (Pmode, A1_REG), | |
1151 | frame_pointer_rtx), | |
1152 | -(current_frame.foffset + fsize), | |
1153 | current_frame.fpu_no, FP0_REG, | |
1154 | current_frame.fpu_mask, false, false); | |
6910dd70 | 1155 | else if (restore_from_sp) |
79e68feb | 1156 | { |
dcc21c4c PB |
1157 | if (TARGET_COLDFIRE) |
1158 | { | |
1159 | int offset; | |
1160 | ||
a40ed0f3 KH |
1161 | /* If we used moveml to restore the integer registers, the |
1162 | stack pointer will still point to the bottom of the moveml | |
1163 | save area. Find the stack offset of the first FP | |
1164 | register. */ | |
1165 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1166 | offset = 0; |
1167 | else | |
a40ed0f3 KH |
1168 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1169 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1170 | current_frame.fpu_no, FP0_REG, | |
1171 | current_frame.fpu_mask, false, false); | |
dcc21c4c | 1172 | } |
884b74f0 | 1173 | else |
a40ed0f3 KH |
1174 | m68k_emit_movem (stack_pointer_rtx, 0, |
1175 | current_frame.fpu_no, FP0_REG, | |
1176 | current_frame.fpu_mask, false, true); | |
79e68feb RS |
1177 | } |
1178 | else | |
a40ed0f3 KH |
1179 | m68k_emit_movem (frame_pointer_rtx, |
1180 | -(current_frame.foffset + fsize), | |
1181 | current_frame.fpu_no, FP0_REG, | |
1182 | current_frame.fpu_mask, false, false); | |
79e68feb | 1183 | } |
a40ed0f3 | 1184 | |
79e68feb | 1185 | if (frame_pointer_needed) |
a40ed0f3 | 1186 | emit_insn (gen_unlink (frame_pointer_rtx)); |
860c4900 | 1187 | else if (fsize_with_regs) |
a40ed0f3 KH |
1188 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1189 | stack_pointer_rtx, | |
1190 | GEN_INT (fsize_with_regs))); | |
1191 | ||
2cff4a6e | 1192 | if (current_function_calls_eh_return) |
a40ed0f3 KH |
1193 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1194 | stack_pointer_rtx, | |
1195 | EH_RETURN_STACKADJ_RTX)); | |
1196 | ||
f7e70894 RS |
1197 | if (!sibcall_p) |
1198 | emit_insn (gen_rtx_RETURN (VOIDmode)); | |
79e68feb RS |
1199 | } |
1200 | \f | |
8a4a2253 | 1201 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1202 | instruction. |
1203 | ||
1204 | Note it rejects floating point comparison operators. | |
1205 | (In the future we could use Fdbcc). | |
1206 | ||
1207 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1208 | ||
1209 | int | |
41b6a5e2 | 1210 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1211 | { |
64a184e9 RS |
1212 | switch (GET_CODE (x)) |
1213 | { | |
64a184e9 RS |
1214 | case EQ: case NE: case GTU: case LTU: |
1215 | case GEU: case LEU: | |
1216 | return 1; | |
1217 | ||
1218 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1219 | conservative */ | |
1220 | case GT: case LT: case GE: case LE: | |
1221 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1222 | default: | |
1223 | return 0; | |
1224 | } | |
1225 | } | |
1226 | ||
a0ab749a | 1227 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1228 | int |
8a4a2253 | 1229 | flags_in_68881 (void) |
6a0f85e3 TG |
1230 | { |
1231 | /* We could add support for these in the future */ | |
1232 | return cc_status.flags & CC_IN_68881; | |
1233 | } | |
1234 | ||
f7e70894 RS |
1235 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls |
1236 | for nested functions because we use the static chain register for | |
1237 | indirect calls. */ | |
1238 | ||
1239 | static bool | |
1240 | m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED, tree exp) | |
1241 | { | |
1242 | return TREE_OPERAND (exp, 2) == NULL; | |
1243 | } | |
1244 | ||
29ca003a RS |
1245 | /* Convert X to a legitimate function call memory reference and return the |
1246 | result. */ | |
a2ef3db7 | 1247 | |
29ca003a RS |
1248 | rtx |
1249 | m68k_legitimize_call_address (rtx x) | |
1250 | { | |
1251 | gcc_assert (MEM_P (x)); | |
1252 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1253 | return x; | |
1254 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1255 | } |
1256 | ||
f7e70894 RS |
1257 | /* Likewise for sibling calls. */ |
1258 | ||
1259 | rtx | |
1260 | m68k_legitimize_sibcall_address (rtx x) | |
1261 | { | |
1262 | gcc_assert (MEM_P (x)); | |
1263 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1264 | return x; | |
1265 | ||
1266 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1267 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1268 | } | |
1269 | ||
64a184e9 RS |
1270 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1271 | floating point version of this sequence (Fdbcc). We also | |
1272 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1273 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1274 | kick those out before we get here. */ | |
64a184e9 | 1275 | |
1d8eaa6b | 1276 | void |
8a4a2253 | 1277 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1278 | { |
64a184e9 RS |
1279 | switch (GET_CODE (operands[3])) |
1280 | { | |
1281 | case EQ: | |
a0a7fbc9 AS |
1282 | output_asm_insn (MOTOROLA |
1283 | ? "dbeq %0,%l1\n\tjbeq %l2" | |
1284 | : "dbeq %0,%l1\n\tjeq %l2", | |
e6d98cb0 BI |
1285 | operands); |
1286 | break; | |
64a184e9 RS |
1287 | |
1288 | case NE: | |
a0a7fbc9 AS |
1289 | output_asm_insn (MOTOROLA |
1290 | ? "dbne %0,%l1\n\tjbne %l2" | |
1291 | : "dbne %0,%l1\n\tjne %l2", | |
e6d98cb0 BI |
1292 | operands); |
1293 | break; | |
64a184e9 RS |
1294 | |
1295 | case GT: | |
a0a7fbc9 AS |
1296 | output_asm_insn (MOTOROLA |
1297 | ? "dbgt %0,%l1\n\tjbgt %l2" | |
1298 | : "dbgt %0,%l1\n\tjgt %l2", | |
e6d98cb0 BI |
1299 | operands); |
1300 | break; | |
64a184e9 RS |
1301 | |
1302 | case GTU: | |
a0a7fbc9 AS |
1303 | output_asm_insn (MOTOROLA |
1304 | ? "dbhi %0,%l1\n\tjbhi %l2" | |
1305 | : "dbhi %0,%l1\n\tjhi %l2", | |
e6d98cb0 BI |
1306 | operands); |
1307 | break; | |
64a184e9 RS |
1308 | |
1309 | case LT: | |
a0a7fbc9 AS |
1310 | output_asm_insn (MOTOROLA |
1311 | ? "dblt %0,%l1\n\tjblt %l2" | |
1312 | : "dblt %0,%l1\n\tjlt %l2", | |
e6d98cb0 BI |
1313 | operands); |
1314 | break; | |
64a184e9 RS |
1315 | |
1316 | case LTU: | |
a0a7fbc9 AS |
1317 | output_asm_insn (MOTOROLA |
1318 | ? "dbcs %0,%l1\n\tjbcs %l2" | |
1319 | : "dbcs %0,%l1\n\tjcs %l2", | |
e6d98cb0 BI |
1320 | operands); |
1321 | break; | |
64a184e9 RS |
1322 | |
1323 | case GE: | |
a0a7fbc9 AS |
1324 | output_asm_insn (MOTOROLA |
1325 | ? "dbge %0,%l1\n\tjbge %l2" | |
1326 | : "dbge %0,%l1\n\tjge %l2", | |
e6d98cb0 BI |
1327 | operands); |
1328 | break; | |
64a184e9 RS |
1329 | |
1330 | case GEU: | |
a0a7fbc9 AS |
1331 | output_asm_insn (MOTOROLA |
1332 | ? "dbcc %0,%l1\n\tjbcc %l2" | |
1333 | : "dbcc %0,%l1\n\tjcc %l2", | |
e6d98cb0 BI |
1334 | operands); |
1335 | break; | |
64a184e9 RS |
1336 | |
1337 | case LE: | |
a0a7fbc9 AS |
1338 | output_asm_insn (MOTOROLA |
1339 | ? "dble %0,%l1\n\tjble %l2" | |
1340 | : "dble %0,%l1\n\tjle %l2", | |
e6d98cb0 BI |
1341 | operands); |
1342 | break; | |
64a184e9 RS |
1343 | |
1344 | case LEU: | |
a0a7fbc9 AS |
1345 | output_asm_insn (MOTOROLA |
1346 | ? "dbls %0,%l1\n\tjbls %l2" | |
1347 | : "dbls %0,%l1\n\tjls %l2", | |
e6d98cb0 BI |
1348 | operands); |
1349 | break; | |
64a184e9 RS |
1350 | |
1351 | default: | |
4761e388 | 1352 | gcc_unreachable (); |
64a184e9 RS |
1353 | } |
1354 | ||
1355 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1356 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1357 | switch (GET_MODE (operands[0])) |
1358 | { | |
1359 | case SImode: | |
a0a7fbc9 AS |
1360 | output_asm_insn (MOTOROLA |
1361 | ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" | |
1362 | : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1363 | operands); |
64a184e9 RS |
1364 | break; |
1365 | ||
1366 | case HImode: | |
1367 | break; | |
1368 | ||
1369 | default: | |
4761e388 | 1370 | gcc_unreachable (); |
64a184e9 RS |
1371 | } |
1372 | } | |
1373 | ||
5505f548 | 1374 | const char * |
4761e388 | 1375 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1376 | { |
1377 | rtx loperands[7]; | |
d9832fd2 | 1378 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1379 | |
f710504c | 1380 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1381 | CC_STATUS_INIT; |
1382 | ||
d9832fd2 RK |
1383 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1384 | below. Swap the operands and change the op if these requirements | |
1385 | are not fulfilled. */ | |
1386 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1387 | { | |
1388 | rtx tmp = operand1; | |
1389 | ||
1390 | operand1 = operand2; | |
1391 | operand2 = tmp; | |
1392 | op_code = swap_condition (op_code); | |
1393 | } | |
c59c3b1c RK |
1394 | loperands[0] = operand1; |
1395 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1396 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1397 | else |
b72f00af | 1398 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1399 | if (operand2 != const0_rtx) |
1400 | { | |
1401 | loperands[2] = operand2; | |
1402 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1403 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1404 | else |
b72f00af | 1405 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1406 | } |
428511bb | 1407 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1408 | if (operand2 != const0_rtx) |
4a8c52e0 | 1409 | { |
a0a7fbc9 AS |
1410 | output_asm_insn (MOTOROLA |
1411 | ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" | |
1412 | : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1413 | loperands); | |
4a8c52e0 | 1414 | } |
392582fa | 1415 | else |
4a8c52e0 | 1416 | { |
9425fb04 | 1417 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1418 | output_asm_insn ("tst%.l %0", loperands); |
1419 | else | |
a0a7fbc9 | 1420 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1421 | |
e6d98cb0 | 1422 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1423 | |
9425fb04 | 1424 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1425 | output_asm_insn ("tst%.l %1", loperands); |
1426 | else | |
3b4b85c9 | 1427 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1428 | } |
1429 | ||
c59c3b1c | 1430 | loperands[5] = dest; |
3b4b85c9 | 1431 | |
d9832fd2 | 1432 | switch (op_code) |
c59c3b1c RK |
1433 | { |
1434 | case EQ: | |
4977bab6 | 1435 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1436 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1437 | output_asm_insn ("seq %5", loperands); |
1438 | break; | |
1439 | ||
1440 | case NE: | |
4977bab6 | 1441 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1442 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1443 | output_asm_insn ("sne %5", loperands); |
1444 | break; | |
1445 | ||
1446 | case GT: | |
428511bb | 1447 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1448 | output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6", |
e6d98cb0 | 1449 | loperands); |
4977bab6 | 1450 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1451 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1452 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1453 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1454 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1455 | break; |
1456 | ||
1457 | case GTU: | |
4977bab6 | 1458 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1459 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1460 | output_asm_insn ("shi %5", loperands); |
1461 | break; | |
1462 | ||
1463 | case LT: | |
428511bb | 1464 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1465 | output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6", |
e6d98cb0 | 1466 | loperands); |
4977bab6 | 1467 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1468 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1469 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1470 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1471 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1472 | break; |
1473 | ||
1474 | case LTU: | |
4977bab6 | 1475 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1476 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1477 | output_asm_insn ("scs %5", loperands); |
1478 | break; | |
1479 | ||
1480 | case GE: | |
428511bb | 1481 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 AS |
1482 | output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6", |
1483 | loperands); | |
4977bab6 | 1484 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1485 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1486 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1487 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1488 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1489 | break; |
1490 | ||
1491 | case GEU: | |
4977bab6 | 1492 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1493 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1494 | output_asm_insn ("scc %5", loperands); |
1495 | break; | |
1496 | ||
1497 | case LE: | |
428511bb | 1498 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1499 | output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6", |
e6d98cb0 | 1500 | loperands); |
4977bab6 | 1501 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1502 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1503 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1504 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1505 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1506 | break; |
1507 | ||
1508 | case LEU: | |
4977bab6 | 1509 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1510 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1511 | output_asm_insn ("sls %5", loperands); |
1512 | break; | |
1513 | ||
1514 | default: | |
4761e388 | 1515 | gcc_unreachable (); |
c59c3b1c RK |
1516 | } |
1517 | return ""; | |
1518 | } | |
1519 | ||
5505f548 | 1520 | const char * |
8a4a2253 | 1521 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1522 | { |
1523 | operands[0] = countop; | |
1524 | operands[1] = dataop; | |
1525 | ||
1526 | if (GET_CODE (countop) == CONST_INT) | |
1527 | { | |
1528 | register int count = INTVAL (countop); | |
1529 | /* If COUNT is bigger than size of storage unit in use, | |
1530 | advance to the containing unit of same size. */ | |
1531 | if (count > signpos) | |
1532 | { | |
1533 | int offset = (count & ~signpos) / 8; | |
1534 | count = count & signpos; | |
b72f00af | 1535 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1536 | } |
1537 | if (count == signpos) | |
1538 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1539 | else | |
1540 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1541 | ||
1542 | /* These three statements used to use next_insns_test_no... | |
1543 | but it appears that this should do the same job. */ | |
1544 | if (count == 31 | |
1545 | && next_insn_tests_no_inequality (insn)) | |
1546 | return "tst%.l %1"; | |
1547 | if (count == 15 | |
1548 | && next_insn_tests_no_inequality (insn)) | |
1549 | return "tst%.w %1"; | |
1550 | if (count == 7 | |
1551 | && next_insn_tests_no_inequality (insn)) | |
1552 | return "tst%.b %1"; | |
1553 | ||
1554 | cc_status.flags = CC_NOT_NEGATIVE; | |
1555 | } | |
1556 | return "btst %0,%1"; | |
1557 | } | |
79e68feb | 1558 | \f |
fc2241eb RS |
1559 | /* Return true if X is a legitimate base register. STRICT_P says |
1560 | whether we need strict checking. */ | |
1561 | ||
1562 | bool | |
1563 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
1564 | { | |
1565 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
1566 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1567 | x = SUBREG_REG (x); | |
1568 | ||
1569 | return (REG_P (x) | |
1570 | && (strict_p | |
1571 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
1572 | : !DATA_REGNO_P (REGNO (x)) && !FP_REGNO_P (REGNO (x)))); | |
1573 | } | |
1574 | ||
1575 | /* Return true if X is a legitimate index register. STRICT_P says | |
1576 | whether we need strict checking. */ | |
1577 | ||
1578 | bool | |
1579 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
1580 | { | |
1581 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1582 | x = SUBREG_REG (x); | |
1583 | ||
1584 | return (REG_P (x) | |
1585 | && (strict_p | |
1586 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
1587 | : !FP_REGNO_P (REGNO (x)))); | |
1588 | } | |
1589 | ||
1590 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
1591 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
1592 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
1593 | ||
1594 | static bool | |
1595 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
1596 | { | |
1597 | int scale; | |
1598 | ||
1599 | /* Check for a scale factor. */ | |
1600 | scale = 1; | |
1601 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
1602 | && GET_CODE (x) == MULT | |
1603 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1604 | && (INTVAL (XEXP (x, 1)) == 2 | |
1605 | || INTVAL (XEXP (x, 1)) == 4 | |
1606 | || (INTVAL (XEXP (x, 1)) == 8 | |
1607 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
1608 | { | |
1609 | scale = INTVAL (XEXP (x, 1)); | |
1610 | x = XEXP (x, 0); | |
1611 | } | |
1612 | ||
1613 | /* Check for a word extension. */ | |
1614 | if (!TARGET_COLDFIRE | |
1615 | && GET_CODE (x) == SIGN_EXTEND | |
1616 | && GET_MODE (XEXP (x, 0)) == HImode) | |
1617 | x = XEXP (x, 0); | |
1618 | ||
1619 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
1620 | { | |
1621 | address->scale = scale; | |
1622 | address->index = x; | |
1623 | return true; | |
1624 | } | |
1625 | ||
1626 | return false; | |
1627 | } | |
1628 | ||
7ffb5e78 RS |
1629 | /* Return true if X is an illegitimate symbolic constant. */ |
1630 | ||
1631 | bool | |
1632 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
1633 | { | |
1634 | rtx base, offset; | |
1635 | ||
1636 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1637 | { | |
1638 | split_const (x, &base, &offset); | |
1639 | if (GET_CODE (base) == SYMBOL_REF | |
1640 | && !offset_within_block_p (base, INTVAL (offset))) | |
1641 | return true; | |
1642 | } | |
1643 | return false; | |
1644 | } | |
1645 | ||
fc2241eb RS |
1646 | /* Return true if X is a legitimate constant address that can reach |
1647 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
1648 | strict checking. */ | |
1649 | ||
1650 | static bool | |
1651 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
1652 | { | |
1653 | rtx base, offset; | |
1654 | ||
1655 | if (!CONSTANT_ADDRESS_P (x)) | |
1656 | return false; | |
1657 | ||
1658 | if (flag_pic | |
1659 | && !(strict_p && TARGET_PCREL) | |
1660 | && symbolic_operand (x, VOIDmode)) | |
1661 | return false; | |
1662 | ||
1663 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
1664 | { | |
1665 | split_const (x, &base, &offset); | |
1666 | if (GET_CODE (base) == SYMBOL_REF | |
1667 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
1668 | return false; | |
1669 | } | |
1670 | ||
1671 | return true; | |
1672 | } | |
1673 | ||
1674 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
1675 | labels will become jump tables. */ | |
1676 | ||
1677 | static bool | |
1678 | m68k_jump_table_ref_p (rtx x) | |
1679 | { | |
1680 | if (GET_CODE (x) != LABEL_REF) | |
1681 | return false; | |
1682 | ||
1683 | x = XEXP (x, 0); | |
1684 | if (!NEXT_INSN (x) && !PREV_INSN (x)) | |
1685 | return true; | |
1686 | ||
1687 | x = next_nonnote_insn (x); | |
1688 | return x && JUMP_TABLE_DATA_P (x); | |
1689 | } | |
1690 | ||
1691 | /* Return true if X is a legitimate address for values of mode MODE. | |
1692 | STRICT_P says whether strict checking is needed. If the address | |
1693 | is valid, describe its components in *ADDRESS. */ | |
1694 | ||
1695 | static bool | |
1696 | m68k_decompose_address (enum machine_mode mode, rtx x, | |
1697 | bool strict_p, struct m68k_address *address) | |
1698 | { | |
1699 | unsigned int reach; | |
1700 | ||
1701 | memset (address, 0, sizeof (*address)); | |
1702 | ||
1703 | if (mode == BLKmode) | |
1704 | reach = 1; | |
1705 | else | |
1706 | reach = GET_MODE_SIZE (mode); | |
1707 | ||
1708 | /* Check for (An) (mode 2). */ | |
1709 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1710 | { | |
1711 | address->base = x; | |
1712 | return true; | |
1713 | } | |
1714 | ||
1715 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
1716 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
1717 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1718 | { | |
1719 | address->code = GET_CODE (x); | |
1720 | address->base = XEXP (x, 0); | |
1721 | return true; | |
1722 | } | |
1723 | ||
1724 | /* Check for (d16,An) (mode 5). */ | |
1725 | if (GET_CODE (x) == PLUS | |
1726 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1727 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
1728 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1729 | { | |
1730 | address->base = XEXP (x, 0); | |
1731 | address->offset = XEXP (x, 1); | |
1732 | return true; | |
1733 | } | |
1734 | ||
1735 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
1736 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
1737 | addresses. */ | |
1738 | if (flag_pic | |
1739 | && GET_CODE (x) == PLUS | |
1740 | && XEXP (x, 0) == pic_offset_table_rtx | |
1741 | && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF | |
1742 | || GET_CODE (XEXP (x, 1)) == LABEL_REF)) | |
1743 | { | |
1744 | address->base = XEXP (x, 0); | |
1745 | address->offset = XEXP (x, 1); | |
1746 | return true; | |
1747 | } | |
1748 | ||
1749 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
1750 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1751 | return false; | |
1752 | ||
1753 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
1754 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
1755 | All these modes are variations of mode 7. */ | |
1756 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
1757 | { | |
1758 | address->offset = x; | |
1759 | return true; | |
1760 | } | |
1761 | ||
1762 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
1763 | tablejumps. | |
1764 | ||
1765 | ??? do_tablejump creates these addresses before placing the target | |
1766 | label, so we have to assume that unplaced labels are jump table | |
1767 | references. It seems unlikely that we would ever generate indexed | |
1768 | accesses to unplaced labels in other cases. */ | |
1769 | if (GET_CODE (x) == PLUS | |
1770 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
1771 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1772 | { | |
1773 | address->offset = XEXP (x, 1); | |
1774 | return true; | |
1775 | } | |
1776 | ||
1777 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
1778 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
1779 | ||
1780 | if (TARGET_68020) | |
1781 | { | |
1782 | /* Check for a nonzero base displacement. */ | |
1783 | if (GET_CODE (x) == PLUS | |
1784 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
1785 | { | |
1786 | address->offset = XEXP (x, 1); | |
1787 | x = XEXP (x, 0); | |
1788 | } | |
1789 | ||
1790 | /* Check for a suppressed index register. */ | |
1791 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1792 | { | |
1793 | address->base = x; | |
1794 | return true; | |
1795 | } | |
1796 | ||
1797 | /* Check for a suppressed base register. Do not allow this case | |
1798 | for non-symbolic offsets as it effectively gives gcc freedom | |
1799 | to treat data registers as base registers, which can generate | |
1800 | worse code. */ | |
1801 | if (address->offset | |
1802 | && symbolic_operand (address->offset, VOIDmode) | |
1803 | && m68k_decompose_index (x, strict_p, address)) | |
1804 | return true; | |
1805 | } | |
1806 | else | |
1807 | { | |
1808 | /* Check for a nonzero base displacement. */ | |
1809 | if (GET_CODE (x) == PLUS | |
1810 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1811 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
1812 | { | |
1813 | address->offset = XEXP (x, 1); | |
1814 | x = XEXP (x, 0); | |
1815 | } | |
1816 | } | |
1817 | ||
1818 | /* We now expect the sum of a base and an index. */ | |
1819 | if (GET_CODE (x) == PLUS) | |
1820 | { | |
1821 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
1822 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
1823 | { | |
1824 | address->base = XEXP (x, 0); | |
1825 | return true; | |
1826 | } | |
1827 | ||
1828 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
1829 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1830 | { | |
1831 | address->base = XEXP (x, 1); | |
1832 | return true; | |
1833 | } | |
1834 | } | |
1835 | return false; | |
1836 | } | |
1837 | ||
1838 | /* Return true if X is a legitimate address for values of mode MODE. | |
1839 | STRICT_P says whether strict checking is needed. */ | |
1840 | ||
1841 | bool | |
1842 | m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
1843 | { | |
1844 | struct m68k_address address; | |
1845 | ||
1846 | return m68k_decompose_address (mode, x, strict_p, &address); | |
1847 | } | |
1848 | ||
1849 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
1850 | Apply strict checking if called during or after reload. */ | |
1851 | ||
1852 | static bool | |
1853 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
1854 | { | |
1855 | return (MEM_P (x) | |
1856 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
1857 | reload_in_progress || reload_completed, | |
1858 | address)); | |
1859 | } | |
1860 | ||
1861 | /* Return true if X matches the 'Q' constraint. It must be a memory | |
1862 | with a base address and no constant offset or index. */ | |
1863 | ||
1864 | bool | |
1865 | m68k_matches_q_p (rtx x) | |
1866 | { | |
1867 | struct m68k_address address; | |
1868 | ||
1869 | return (m68k_legitimate_mem_p (x, &address) | |
1870 | && address.code == UNKNOWN | |
1871 | && address.base | |
1872 | && !address.offset | |
1873 | && !address.index); | |
1874 | } | |
1875 | ||
1876 | /* Return true if X matches the 'U' constraint. It must be a base address | |
1877 | with a constant offset and no index. */ | |
1878 | ||
1879 | bool | |
1880 | m68k_matches_u_p (rtx x) | |
1881 | { | |
1882 | struct m68k_address address; | |
1883 | ||
1884 | return (m68k_legitimate_mem_p (x, &address) | |
1885 | && address.code == UNKNOWN | |
1886 | && address.base | |
1887 | && address.offset | |
1888 | && !address.index); | |
1889 | } | |
1890 | ||
79e68feb RS |
1891 | /* Legitimize PIC addresses. If the address is already |
1892 | position-independent, we return ORIG. Newly generated | |
1893 | position-independent addresses go to REG. If we need more | |
1894 | than one register, we lose. | |
1895 | ||
1896 | An address is legitimized by making an indirect reference | |
1897 | through the Global Offset Table with the name of the symbol | |
1898 | used as an offset. | |
1899 | ||
1900 | The assembler and linker are responsible for placing the | |
1901 | address of the symbol in the GOT. The function prologue | |
1902 | is responsible for initializing a5 to the starting address | |
1903 | of the GOT. | |
1904 | ||
1905 | The assembler is also responsible for translating a symbol name | |
1906 | into a constant displacement from the start of the GOT. | |
1907 | ||
1908 | A quick example may make things a little clearer: | |
1909 | ||
1910 | When not generating PIC code to store the value 12345 into _foo | |
1911 | we would generate the following code: | |
1912 | ||
1913 | movel #12345, _foo | |
1914 | ||
1915 | When generating PIC two transformations are made. First, the compiler | |
1916 | loads the address of foo into a register. So the first transformation makes: | |
1917 | ||
1918 | lea _foo, a0 | |
1919 | movel #12345, a0@ | |
1920 | ||
1921 | The code in movsi will intercept the lea instruction and call this | |
1922 | routine which will transform the instructions into: | |
1923 | ||
1924 | movel a5@(_foo:w), a0 | |
1925 | movel #12345, a0@ | |
1926 | ||
1927 | ||
1928 | That (in a nutshell) is how *all* symbol and label references are | |
1929 | handled. */ | |
1930 | ||
1931 | rtx | |
8a4a2253 BI |
1932 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1933 | rtx reg) | |
79e68feb RS |
1934 | { |
1935 | rtx pic_ref = orig; | |
1936 | ||
1937 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
1938 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1939 | { | |
4761e388 | 1940 | gcc_assert (reg); |
79e68feb | 1941 | |
1d8eaa6b AS |
1942 | pic_ref = gen_rtx_MEM (Pmode, |
1943 | gen_rtx_PLUS (Pmode, | |
1944 | pic_offset_table_rtx, orig)); | |
79e68feb | 1945 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 1946 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
1947 | emit_move_insn (reg, pic_ref); |
1948 | return reg; | |
1949 | } | |
1950 | else if (GET_CODE (orig) == CONST) | |
1951 | { | |
1d8eaa6b | 1952 | rtx base; |
79e68feb | 1953 | |
b2e08ed4 | 1954 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
1955 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
1956 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1957 | return orig; | |
1958 | ||
4761e388 | 1959 | gcc_assert (reg); |
79e68feb RS |
1960 | |
1961 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
1962 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
1963 | ||
1964 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
1965 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
1966 | base == reg ? 0 : reg); | |
79e68feb RS |
1967 | |
1968 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 1969 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 1970 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
1971 | /* Likewise, should we set special REG_NOTEs here? */ |
1972 | } | |
1973 | return pic_ref; | |
1974 | } | |
1975 | ||
1976 | \f | |
28bad6d1 | 1977 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 1978 | |
a0a7fbc9 | 1979 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 1980 | |
bda2a571 RS |
1981 | /* Return the type of move that should be used for integer I. */ |
1982 | ||
5505f548 | 1983 | static CONST_METHOD |
bda2a571 | 1984 | const_method (HOST_WIDE_INT i) |
0ce6f9fb | 1985 | { |
0ce6f9fb RK |
1986 | unsigned u; |
1987 | ||
6910dd70 | 1988 | if (USE_MOVQ (i)) |
0ce6f9fb | 1989 | return MOVQ; |
24092242 | 1990 | |
c16eadc7 | 1991 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 1992 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 1993 | if (!TARGET_COLDFIRE) |
24092242 RK |
1994 | { |
1995 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 1996 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
1997 | if (USE_MOVQ (i ^ 0xff)) |
1998 | return NOTB; | |
1999 | /* Likewise, try with not.w */ | |
2000 | if (USE_MOVQ (i ^ 0xffff)) | |
2001 | return NOTW; | |
2002 | /* This is the only value where neg.w is useful */ | |
2003 | if (i == -65408) | |
2004 | return NEGW; | |
24092242 | 2005 | } |
28bad6d1 | 2006 | |
5e04daf3 PB |
2007 | /* Try also with swap. */ |
2008 | u = i; | |
2009 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2010 | return SWAP; | |
2011 | ||
986e74d5 | 2012 | if (TARGET_ISAB) |
28bad6d1 | 2013 | { |
72edf146 | 2014 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
2015 | if (i >= 0 && i <= 65535) |
2016 | return MVZ; | |
2017 | if (i >= -32768 && i <= 32767) | |
2018 | return MVS; | |
2019 | } | |
2020 | ||
0ce6f9fb RK |
2021 | /* Otherwise, use move.l */ |
2022 | return MOVL; | |
2023 | } | |
2024 | ||
bda2a571 RS |
2025 | /* Return the cost of moving constant I into a data register. */ |
2026 | ||
3c50106f | 2027 | static int |
bda2a571 | 2028 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 2029 | { |
bda2a571 | 2030 | switch (const_method (i)) |
0ce6f9fb | 2031 | { |
a0a7fbc9 AS |
2032 | case MOVQ: |
2033 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2034 | return 0; | |
2035 | case MVZ: | |
2036 | case MVS: | |
2037 | case NOTB: | |
2038 | case NOTW: | |
2039 | case NEGW: | |
2040 | case SWAP: | |
2041 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2042 | return 1; | |
2043 | case MOVL: | |
2044 | return 2; | |
2045 | default: | |
2046 | gcc_unreachable (); | |
0ce6f9fb RK |
2047 | } |
2048 | } | |
2049 | ||
3c50106f | 2050 | static bool |
8a4a2253 | 2051 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
2052 | { |
2053 | switch (code) | |
2054 | { | |
2055 | case CONST_INT: | |
2056 | /* Constant zero is super cheap due to clr instruction. */ | |
2057 | if (x == const0_rtx) | |
2058 | *total = 0; | |
2059 | else | |
bda2a571 | 2060 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
2061 | return true; |
2062 | ||
2063 | case CONST: | |
2064 | case LABEL_REF: | |
2065 | case SYMBOL_REF: | |
2066 | *total = 3; | |
2067 | return true; | |
2068 | ||
2069 | case CONST_DOUBLE: | |
2070 | /* Make 0.0 cheaper than other floating constants to | |
2071 | encourage creating tstsf and tstdf insns. */ | |
2072 | if (outer_code == COMPARE | |
2073 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
2074 | *total = 4; | |
2075 | else | |
2076 | *total = 5; | |
2077 | return true; | |
2078 | ||
2079 | /* These are vaguely right for a 68020. */ | |
2080 | /* The costs for long multiply have been adjusted to work properly | |
2081 | in synth_mult on the 68020, relative to an average of the time | |
2082 | for add and the time for shift, taking away a little more because | |
2083 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
2084 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
2085 | terms. */ | |
fe95f2f7 JB |
2086 | #define MULL_COST \ |
2087 | (TUNE_68060 ? 2 \ | |
2088 | : TUNE_68040 ? 5 \ | |
2089 | : TUNE_CFV2 ? 10 \ | |
2090 | : TARGET_COLDFIRE ? 3 : 13) | |
2091 | ||
2092 | #define MULW_COST \ | |
2093 | (TUNE_68060 ? 2 \ | |
2094 | : TUNE_68040 ? 3 \ | |
2095 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
2096 | : TARGET_COLDFIRE ? 2 : 8) | |
2097 | ||
2098 | #define DIVW_COST \ | |
2099 | (TARGET_CF_HWDIV ? 11 \ | |
2100 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
2101 | |
2102 | case PLUS: | |
2103 | /* An lea costs about three times as much as a simple add. */ | |
2104 | if (GET_MODE (x) == SImode | |
2105 | && GET_CODE (XEXP (x, 1)) == REG | |
2106 | && GET_CODE (XEXP (x, 0)) == MULT | |
2107 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2108 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2109 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
2110 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
2111 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
2112 | { |
2113 | /* lea an@(dx:l:i),am */ | |
2114 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
2115 | return true; | |
2116 | } | |
3c50106f RH |
2117 | return false; |
2118 | ||
2119 | case ASHIFT: | |
2120 | case ASHIFTRT: | |
2121 | case LSHIFTRT: | |
fe95f2f7 | 2122 | if (TUNE_68060) |
3c50106f RH |
2123 | { |
2124 | *total = COSTS_N_INSNS(1); | |
2125 | return true; | |
2126 | } | |
fe95f2f7 | 2127 | if (TUNE_68000_10) |
3c50106f RH |
2128 | { |
2129 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2130 | { | |
2131 | if (INTVAL (XEXP (x, 1)) < 16) | |
2132 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
2133 | else | |
2134 | /* We're using clrw + swap for these cases. */ | |
2135 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
2136 | } | |
2137 | else | |
a0a7fbc9 | 2138 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
2139 | return true; |
2140 | } | |
2141 | /* A shift by a big integer takes an extra instruction. */ | |
2142 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2143 | && (INTVAL (XEXP (x, 1)) == 16)) | |
2144 | { | |
2145 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
2146 | return true; | |
2147 | } | |
2148 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2149 | && !(INTVAL (XEXP (x, 1)) > 0 | |
2150 | && INTVAL (XEXP (x, 1)) <= 8)) | |
2151 | { | |
eb849993 | 2152 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
2153 | return true; |
2154 | } | |
2155 | return false; | |
2156 | ||
2157 | case MULT: | |
2158 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2159 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
2160 | && GET_MODE (x) == SImode) | |
2161 | *total = COSTS_N_INSNS (MULW_COST); | |
2162 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2163 | *total = COSTS_N_INSNS (MULW_COST); | |
2164 | else | |
2165 | *total = COSTS_N_INSNS (MULL_COST); | |
2166 | return true; | |
2167 | ||
2168 | case DIV: | |
2169 | case UDIV: | |
2170 | case MOD: | |
2171 | case UMOD: | |
2172 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2173 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
2174 | else if (TARGET_CF_HWDIV) |
2175 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
2176 | else |
2177 | *total = COSTS_N_INSNS (43); /* div.l */ | |
2178 | return true; | |
2179 | ||
2180 | default: | |
2181 | return false; | |
2182 | } | |
2183 | } | |
2184 | ||
88512ba0 | 2185 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
2186 | OPERANDS[0]. */ |
2187 | ||
2188 | static const char * | |
8a4a2253 | 2189 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 2190 | { |
bda2a571 | 2191 | HOST_WIDE_INT i; |
0ce6f9fb RK |
2192 | |
2193 | i = INTVAL (operands[1]); | |
bda2a571 | 2194 | switch (const_method (i)) |
0ce6f9fb | 2195 | { |
28bad6d1 | 2196 | case MVZ: |
28bad6d1 | 2197 | return "mvzw %1,%0"; |
1cbae84f PB |
2198 | case MVS: |
2199 | return "mvsw %1,%0"; | |
a0a7fbc9 | 2200 | case MOVQ: |
0ce6f9fb | 2201 | return "moveq %1,%0"; |
a0a7fbc9 | 2202 | case NOTB: |
66e07510 | 2203 | CC_STATUS_INIT; |
1d8eaa6b | 2204 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 2205 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 2206 | case NOTW: |
66e07510 | 2207 | CC_STATUS_INIT; |
1d8eaa6b | 2208 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 2209 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 2210 | case NEGW: |
66e07510 | 2211 | CC_STATUS_INIT; |
3b4b85c9 | 2212 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 2213 | case SWAP: |
0ce6f9fb RK |
2214 | { |
2215 | unsigned u = i; | |
2216 | ||
1d8eaa6b | 2217 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 2218 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 2219 | } |
a0a7fbc9 | 2220 | case MOVL: |
bda2a571 | 2221 | return "move%.l %1,%0"; |
a0a7fbc9 | 2222 | default: |
bda2a571 | 2223 | gcc_unreachable (); |
0ce6f9fb RK |
2224 | } |
2225 | } | |
2226 | ||
bda2a571 | 2227 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 2228 | |
bda2a571 RS |
2229 | bool |
2230 | valid_mov3q_const (HOST_WIDE_INT i) | |
2231 | { | |
2232 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
2233 | } |
2234 | ||
bda2a571 RS |
2235 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
2236 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 2237 | |
bda2a571 | 2238 | static const char * |
8a4a2253 | 2239 | output_move_simode_const (rtx *operands) |
02ed0c07 | 2240 | { |
bda2a571 RS |
2241 | rtx dest; |
2242 | HOST_WIDE_INT src; | |
2243 | ||
2244 | dest = operands[0]; | |
2245 | src = INTVAL (operands[1]); | |
2246 | if (src == 0 | |
2247 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
2248 | /* clr insns on 68000 read before writing. */ |
2249 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 2250 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 2251 | return "clr%.l %0"; |
bda2a571 | 2252 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 2253 | return "mov3q%.l %1,%0"; |
bda2a571 | 2254 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 2255 | return "sub%.l %0,%0"; |
bda2a571 | 2256 | else if (DATA_REG_P (dest)) |
02ed0c07 | 2257 | return output_move_const_into_data_reg (operands); |
bda2a571 | 2258 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 2259 | { |
bda2a571 | 2260 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2261 | return "mov3q%.l %1,%0"; |
2262 | return "move%.w %1,%0"; | |
2263 | } | |
bda2a571 RS |
2264 | else if (MEM_P (dest) |
2265 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2266 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
2267 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 2268 | { |
bda2a571 | 2269 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2270 | return "mov3q%.l %1,%-"; |
2271 | return "pea %a1"; | |
2272 | } | |
02ed0c07 RK |
2273 | return "move%.l %1,%0"; |
2274 | } | |
2275 | ||
5505f548 | 2276 | const char * |
8a4a2253 | 2277 | output_move_simode (rtx *operands) |
f4e80198 RK |
2278 | { |
2279 | if (GET_CODE (operands[1]) == CONST_INT) | |
2280 | return output_move_simode_const (operands); | |
2281 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2282 | || GET_CODE (operands[1]) == CONST) | |
2283 | && push_operand (operands[0], SImode)) | |
2284 | return "pea %a1"; | |
2285 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2286 | || GET_CODE (operands[1]) == CONST) | |
2287 | && ADDRESS_REG_P (operands[0])) | |
2288 | return "lea %a1,%0"; | |
2289 | return "move%.l %1,%0"; | |
2290 | } | |
2291 | ||
5505f548 | 2292 | const char * |
8a4a2253 | 2293 | output_move_himode (rtx *operands) |
f4e80198 RK |
2294 | { |
2295 | if (GET_CODE (operands[1]) == CONST_INT) | |
2296 | { | |
2297 | if (operands[1] == const0_rtx | |
2298 | && (DATA_REG_P (operands[0]) | |
2299 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2300 | /* clr insns on 68000 read before writing. */ |
2301 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2302 | || !(GET_CODE (operands[0]) == MEM |
2303 | && MEM_VOLATILE_P (operands[0])))) | |
2304 | return "clr%.w %0"; | |
38198304 AS |
2305 | else if (operands[1] == const0_rtx |
2306 | && ADDRESS_REG_P (operands[0])) | |
2307 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2308 | else if (DATA_REG_P (operands[0]) |
2309 | && INTVAL (operands[1]) < 128 | |
2310 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2311 | return "moveq %1,%0"; |
f4e80198 RK |
2312 | else if (INTVAL (operands[1]) < 0x8000 |
2313 | && INTVAL (operands[1]) >= -0x8000) | |
2314 | return "move%.w %1,%0"; | |
2315 | } | |
2316 | else if (CONSTANT_P (operands[1])) | |
2317 | return "move%.l %1,%0"; | |
f4e80198 RK |
2318 | /* Recognize the insn before a tablejump, one that refers |
2319 | to a table of offsets. Such an insn will need to refer | |
2320 | to a label on the insn. So output one. Use the label-number | |
2321 | of the table of offsets to generate this label. This code, | |
2322 | and similar code below, assumes that there will be at most one | |
2323 | reference to each table. */ | |
2324 | if (GET_CODE (operands[1]) == MEM | |
2325 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2326 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
2327 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
2328 | { | |
2329 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
2330 | if (MOTOROLA) |
2331 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
2332 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
2333 | else | |
2334 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
a0a7fbc9 | 2335 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); |
f4e80198 | 2336 | } |
f4e80198 RK |
2337 | return "move%.w %1,%0"; |
2338 | } | |
2339 | ||
5505f548 | 2340 | const char * |
8a4a2253 | 2341 | output_move_qimode (rtx *operands) |
f4e80198 | 2342 | { |
102701ff | 2343 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2344 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2345 | |
a0a7fbc9 | 2346 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2347 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2348 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2349 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2350 | && ! ADDRESS_REG_P (operands[1]) | |
2351 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2352 | |
3197c489 | 2353 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2354 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2355 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2356 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2357 | { | |
2358 | if (operands[1] == const0_rtx) | |
2359 | return "clr%.b %0"; | |
9425fb04 | 2360 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2361 | && GET_CODE (operands[1]) == CONST_INT |
2362 | && (INTVAL (operands[1]) & 255) == 255) | |
2363 | { | |
2364 | CC_STATUS_INIT; | |
2365 | return "st %0"; | |
2366 | } | |
2367 | } | |
2368 | if (GET_CODE (operands[1]) == CONST_INT | |
2369 | && DATA_REG_P (operands[0]) | |
2370 | && INTVAL (operands[1]) < 128 | |
2371 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2372 | return "moveq %1,%0"; |
38198304 AS |
2373 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2374 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2375 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2376 | return "move%.l %1,%0"; | |
c16eadc7 | 2377 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2378 | from address registers. */ |
2379 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2380 | return "move%.w %1,%0"; |
2381 | return "move%.b %1,%0"; | |
2382 | } | |
2383 | ||
5505f548 | 2384 | const char * |
8a4a2253 | 2385 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2386 | { |
2387 | if (operands[1] == const0_rtx | |
3197c489 RS |
2388 | /* clr insns on 68000 read before writing. */ |
2389 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2390 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2391 | return "clr%.w %0"; | |
2392 | return "move%.w %1,%0"; | |
2393 | } | |
2394 | ||
5505f548 | 2395 | const char * |
8a4a2253 | 2396 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2397 | { |
2398 | if (operands[1] == const0_rtx | |
3197c489 RS |
2399 | /* clr insns on 68000 read before writing. */ |
2400 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2401 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2402 | return "clr%.b %0"; | |
2403 | return "move%.b %1,%0"; | |
2404 | } | |
2405 | ||
79e68feb RS |
2406 | /* Return the best assembler insn template |
2407 | for moving operands[1] into operands[0] as a fullword. */ | |
2408 | ||
5505f548 | 2409 | static const char * |
8a4a2253 | 2410 | singlemove_string (rtx *operands) |
79e68feb | 2411 | { |
02ed0c07 RK |
2412 | if (GET_CODE (operands[1]) == CONST_INT) |
2413 | return output_move_simode_const (operands); | |
2414 | return "move%.l %1,%0"; | |
79e68feb RS |
2415 | } |
2416 | ||
2505bc97 | 2417 | |
79e68feb RS |
2418 | /* Output assembler code to perform a doubleword move insn |
2419 | with operands OPERANDS. */ | |
2420 | ||
5505f548 | 2421 | const char * |
8a4a2253 | 2422 | output_move_double (rtx *operands) |
79e68feb | 2423 | { |
2505bc97 RS |
2424 | enum |
2425 | { | |
2426 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2427 | } optype0, optype1; | |
79e68feb | 2428 | rtx latehalf[2]; |
2505bc97 | 2429 | rtx middlehalf[2]; |
7f98eeb6 | 2430 | rtx xops[2]; |
79e68feb | 2431 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2432 | int dest_overlapped_low = 0; |
184916bc | 2433 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2434 | |
2435 | middlehalf[0] = 0; | |
2436 | middlehalf[1] = 0; | |
79e68feb RS |
2437 | |
2438 | /* First classify both operands. */ | |
2439 | ||
2440 | if (REG_P (operands[0])) | |
2441 | optype0 = REGOP; | |
2442 | else if (offsettable_memref_p (operands[0])) | |
2443 | optype0 = OFFSOP; | |
2444 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2445 | optype0 = POPOP; | |
2446 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2447 | optype0 = PUSHOP; | |
2448 | else if (GET_CODE (operands[0]) == MEM) | |
2449 | optype0 = MEMOP; | |
2450 | else | |
2451 | optype0 = RNDOP; | |
2452 | ||
2453 | if (REG_P (operands[1])) | |
2454 | optype1 = REGOP; | |
2455 | else if (CONSTANT_P (operands[1])) | |
2456 | optype1 = CNSTOP; | |
2457 | else if (offsettable_memref_p (operands[1])) | |
2458 | optype1 = OFFSOP; | |
2459 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2460 | optype1 = POPOP; | |
2461 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2462 | optype1 = PUSHOP; | |
2463 | else if (GET_CODE (operands[1]) == MEM) | |
2464 | optype1 = MEMOP; | |
2465 | else | |
2466 | optype1 = RNDOP; | |
2467 | ||
4761e388 NS |
2468 | /* Check for the cases that the operand constraints are not supposed |
2469 | to allow to happen. Generating code for these cases is | |
2470 | painful. */ | |
2471 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2472 | |
2473 | /* If one operand is decrementing and one is incrementing | |
2474 | decrement the former register explicitly | |
2475 | and change that operand into ordinary indexing. */ | |
2476 | ||
2477 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2478 | { | |
2479 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 2480 | if (size == 12) |
3b4b85c9 | 2481 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 2482 | else |
3b4b85c9 | 2483 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 2484 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2485 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2486 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2487 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2488 | else |
1d8eaa6b | 2489 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2490 | optype0 = OFFSOP; |
2491 | } | |
2492 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2493 | { | |
2494 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 2495 | if (size == 12) |
3b4b85c9 | 2496 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 2497 | else |
3b4b85c9 | 2498 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 2499 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2500 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2501 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2502 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2503 | else |
1d8eaa6b | 2504 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2505 | optype1 = OFFSOP; |
2506 | } | |
2507 | ||
2508 | /* If an operand is an unoffsettable memory ref, find a register | |
2509 | we can increment temporarily to make it refer to the second word. */ | |
2510 | ||
2511 | if (optype0 == MEMOP) | |
2512 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2513 | ||
2514 | if (optype1 == MEMOP) | |
2515 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2516 | ||
2517 | /* Ok, we can do one word at a time. | |
2518 | Normally we do the low-numbered word first, | |
2519 | but if either operand is autodecrementing then we | |
2520 | do the high-numbered word first. | |
2521 | ||
2522 | In either case, set up in LATEHALF the operands to use | |
2523 | for the high-numbered word and in some cases alter the | |
2524 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2525 | ||
2505bc97 RS |
2526 | if (size == 12) |
2527 | { | |
2528 | if (optype0 == REGOP) | |
2529 | { | |
1d8eaa6b AS |
2530 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2531 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2532 | } |
2533 | else if (optype0 == OFFSOP) | |
2534 | { | |
b72f00af RK |
2535 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2536 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2537 | } |
2538 | else | |
2539 | { | |
2540 | middlehalf[0] = operands[0]; | |
2541 | latehalf[0] = operands[0]; | |
2542 | } | |
2543 | ||
2544 | if (optype1 == REGOP) | |
2545 | { | |
1d8eaa6b AS |
2546 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2547 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2548 | } |
2549 | else if (optype1 == OFFSOP) | |
2550 | { | |
b72f00af RK |
2551 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2552 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2553 | } |
2554 | else if (optype1 == CNSTOP) | |
2555 | { | |
2556 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2557 | { | |
2558 | REAL_VALUE_TYPE r; | |
2559 | long l[3]; | |
2560 | ||
2561 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2562 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2563 | operands[1] = GEN_INT (l[0]); | |
2564 | middlehalf[1] = GEN_INT (l[1]); | |
2565 | latehalf[1] = GEN_INT (l[2]); | |
2566 | } | |
4761e388 | 2567 | else |
2505bc97 | 2568 | { |
4761e388 NS |
2569 | /* No non-CONST_DOUBLE constant should ever appear |
2570 | here. */ | |
2571 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2572 | } |
2573 | } | |
2574 | else | |
2575 | { | |
2576 | middlehalf[1] = operands[1]; | |
2577 | latehalf[1] = operands[1]; | |
2578 | } | |
2579 | } | |
79e68feb | 2580 | else |
2505bc97 RS |
2581 | /* size is not 12: */ |
2582 | { | |
2583 | if (optype0 == REGOP) | |
1d8eaa6b | 2584 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2585 | else if (optype0 == OFFSOP) |
b72f00af | 2586 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2587 | else |
2588 | latehalf[0] = operands[0]; | |
2589 | ||
2590 | if (optype1 == REGOP) | |
1d8eaa6b | 2591 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2592 | else if (optype1 == OFFSOP) |
b72f00af | 2593 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2594 | else if (optype1 == CNSTOP) |
2595 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2596 | else | |
2597 | latehalf[1] = operands[1]; | |
2598 | } | |
79e68feb RS |
2599 | |
2600 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2601 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2602 | for the low word as well, to compensate for the first decrement of sp. */ | |
2603 | if (optype0 == PUSHOP | |
2604 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2605 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2606 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2607 | |
7f98eeb6 RS |
2608 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2609 | if the upper part of reg N does not appear in the MEM, arrange to | |
2610 | emit the move late-half first. Otherwise, compute the MEM address | |
2611 | into the upper part of N and use that as a pointer to the memory | |
2612 | operand. */ | |
2613 | if (optype0 == REGOP | |
2614 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2615 | { | |
1d8eaa6b | 2616 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2617 | |
2618 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2619 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2620 | { |
2621 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2622 | compute the address into latehalf of dest. |
2623 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2624 | compadr: |
7f98eeb6 RS |
2625 | xops[0] = latehalf[0]; |
2626 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2627 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2628 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2629 | { |
1d8eaa6b | 2630 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2631 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2632 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2633 | } |
2634 | else | |
2635 | { | |
1d8eaa6b | 2636 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2637 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2638 | } |
2639 | } | |
2640 | else if (size == 12 | |
d7e8d581 RS |
2641 | && reg_overlap_mentioned_p (middlehalf[0], |
2642 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2643 | { |
3a58400f RS |
2644 | /* Check for two regs used by both source and dest. |
2645 | Note that this can't happen if the dest is all data regs. | |
2646 | It can happen if the dest is d6, d7, a0. | |
2647 | But in that case, latehalf is an addr reg, so | |
2648 | the code at compadr does ok. */ | |
2649 | ||
2650 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2651 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2652 | goto compadr; | |
7f98eeb6 RS |
2653 | |
2654 | /* JRV says this can't happen: */ | |
4761e388 | 2655 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2656 | |
7a1929e1 | 2657 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2658 | output_asm_insn (singlemove_string (operands), operands); |
2659 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2660 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2661 | return ""; | |
2662 | } | |
2fb8a81d | 2663 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2664 | /* If the low half of dest is mentioned in the source memory |
2665 | address, the arrange to emit the move late half first. */ | |
2666 | dest_overlapped_low = 1; | |
2667 | } | |
2668 | ||
79e68feb RS |
2669 | /* If one or both operands autodecrementing, |
2670 | do the two words, high-numbered first. */ | |
2671 | ||
2672 | /* Likewise, the first move would clobber the source of the second one, | |
2673 | do them in the other order. This happens only for registers; | |
2674 | such overlap can't happen in memory unless the user explicitly | |
2675 | sets it up, and that is an undefined circumstance. */ | |
2676 | ||
2677 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2678 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2679 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2680 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2681 | || dest_overlapped_low) | |
79e68feb RS |
2682 | { |
2683 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2684 | if (addreg0) | |
2505bc97 RS |
2685 | { |
2686 | if (size == 12) | |
3b4b85c9 | 2687 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2688 | else |
3b4b85c9 | 2689 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2690 | } |
79e68feb | 2691 | if (addreg1) |
2505bc97 RS |
2692 | { |
2693 | if (size == 12) | |
3b4b85c9 | 2694 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2695 | else |
3b4b85c9 | 2696 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2697 | } |
79e68feb RS |
2698 | |
2699 | /* Do that word. */ | |
2700 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2701 | ||
2702 | /* Undo the adds we just did. */ | |
2703 | if (addreg0) | |
3b4b85c9 | 2704 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2705 | if (addreg1) |
3b4b85c9 | 2706 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2707 | |
2505bc97 RS |
2708 | if (size == 12) |
2709 | { | |
2710 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2711 | if (addreg0) | |
3b4b85c9 | 2712 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2713 | if (addreg1) |
3b4b85c9 | 2714 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2715 | } |
2716 | ||
79e68feb RS |
2717 | /* Do low-numbered word. */ |
2718 | return singlemove_string (operands); | |
2719 | } | |
2720 | ||
2721 | /* Normal case: do the two words, low-numbered first. */ | |
2722 | ||
2723 | output_asm_insn (singlemove_string (operands), operands); | |
2724 | ||
2505bc97 RS |
2725 | /* Do the middle one of the three words for long double */ |
2726 | if (size == 12) | |
2727 | { | |
2728 | if (addreg0) | |
3b4b85c9 | 2729 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2730 | if (addreg1) |
3b4b85c9 | 2731 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2732 | |
2733 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2734 | } | |
2735 | ||
79e68feb RS |
2736 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2737 | if (addreg0) | |
3b4b85c9 | 2738 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2739 | if (addreg1) |
3b4b85c9 | 2740 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2741 | |
2742 | /* Do that word. */ | |
2743 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2744 | ||
2745 | /* Undo the adds we just did. */ | |
2746 | if (addreg0) | |
2505bc97 RS |
2747 | { |
2748 | if (size == 12) | |
3b4b85c9 | 2749 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2750 | else |
3b4b85c9 | 2751 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2752 | } |
79e68feb | 2753 | if (addreg1) |
2505bc97 RS |
2754 | { |
2755 | if (size == 12) | |
3b4b85c9 | 2756 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2757 | else |
3b4b85c9 | 2758 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2759 | } |
79e68feb RS |
2760 | |
2761 | return ""; | |
2762 | } | |
2763 | ||
dcc21c4c PB |
2764 | |
2765 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2766 | new rtx with the correct mode. */ | |
2767 | ||
2768 | static rtx | |
2769 | force_mode (enum machine_mode mode, rtx orig) | |
2770 | { | |
2771 | if (mode == GET_MODE (orig)) | |
2772 | return orig; | |
2773 | ||
2774 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2775 | abort (); | |
2776 | ||
2777 | return gen_rtx_REG (mode, REGNO (orig)); | |
2778 | } | |
2779 | ||
2780 | static int | |
2781 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2782 | { | |
2783 | return reg_renumber && FP_REG_P (op); | |
2784 | } | |
2785 | ||
2786 | /* Emit insns to move operands[1] into operands[0]. | |
2787 | ||
2788 | Return 1 if we have written out everything that needs to be done to | |
2789 | do the move. Otherwise, return 0 and the caller will emit the move | |
2790 | normally. | |
2791 | ||
2792 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2793 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2794 | of SCRATCH_REG in the proper mode. */ |
2795 | ||
2796 | int | |
2797 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2798 | { | |
2799 | register rtx operand0 = operands[0]; | |
2800 | register rtx operand1 = operands[1]; | |
2801 | register rtx tem; | |
2802 | ||
2803 | if (scratch_reg | |
2804 | && reload_in_progress && GET_CODE (operand0) == REG | |
2805 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2806 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2807 | else if (scratch_reg | |
2808 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2809 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2810 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2811 | { | |
2812 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2813 | the code which tracks sets/uses for delete_output_reload. */ | |
2814 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2815 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2816 | SUBREG_BYTE (operand0)); | |
2817 | operand0 = alter_subreg (&temp); | |
2818 | } | |
2819 | ||
2820 | if (scratch_reg | |
2821 | && reload_in_progress && GET_CODE (operand1) == REG | |
2822 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2823 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2824 | else if (scratch_reg | |
2825 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2826 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2827 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2828 | { | |
2829 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2830 | the code which tracks sets/uses for delete_output_reload. */ | |
2831 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2832 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2833 | SUBREG_BYTE (operand1)); | |
2834 | operand1 = alter_subreg (&temp); | |
2835 | } | |
2836 | ||
2837 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2838 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2839 | != XEXP (operand0, 0))) | |
2840 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2841 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2842 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2843 | != XEXP (operand1, 0))) | |
2844 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2845 | ||
2846 | /* Handle secondary reloads for loads/stores of FP registers where | |
2847 | the address is symbolic by using the scratch register */ | |
2848 | if (fp_reg_operand (operand0, mode) | |
2849 | && ((GET_CODE (operand1) == MEM | |
2850 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
2851 | || ((GET_CODE (operand1) == SUBREG | |
2852 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
2853 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
2854 | && scratch_reg) | |
2855 | { | |
2856 | if (GET_CODE (operand1) == SUBREG) | |
2857 | operand1 = XEXP (operand1, 0); | |
2858 | ||
2859 | /* SCRATCH_REG will hold an address. We want | |
2860 | it in SImode regardless of what mode it was originally given | |
2861 | to us. */ | |
2862 | scratch_reg = force_mode (SImode, scratch_reg); | |
2863 | ||
2864 | /* D might not fit in 14 bits either; for such cases load D into | |
2865 | scratch reg. */ | |
2866 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
2867 | { | |
2868 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
2869 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
2870 | Pmode, | |
2871 | XEXP (XEXP (operand1, 0), 0), | |
2872 | scratch_reg)); | |
2873 | } | |
2874 | else | |
2875 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
2876 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
2877 | gen_rtx_MEM (mode, scratch_reg))); | |
2878 | return 1; | |
2879 | } | |
2880 | else if (fp_reg_operand (operand1, mode) | |
2881 | && ((GET_CODE (operand0) == MEM | |
2882 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
2883 | || ((GET_CODE (operand0) == SUBREG) | |
2884 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
2885 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
2886 | && scratch_reg) | |
2887 | { | |
2888 | if (GET_CODE (operand0) == SUBREG) | |
2889 | operand0 = XEXP (operand0, 0); | |
2890 | ||
2891 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2892 | it in SIMODE regardless of what mode it was originally given | |
2893 | to us. */ | |
2894 | scratch_reg = force_mode (SImode, scratch_reg); | |
2895 | ||
2896 | /* D might not fit in 14 bits either; for such cases load D into | |
2897 | scratch reg. */ | |
2898 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
2899 | { | |
2900 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
2901 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
2902 | 0)), | |
2903 | Pmode, | |
2904 | XEXP (XEXP (operand0, 0), | |
2905 | 0), | |
2906 | scratch_reg)); | |
2907 | } | |
2908 | else | |
2909 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
2910 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
2911 | operand1)); | |
2912 | return 1; | |
2913 | } | |
2914 | /* Handle secondary reloads for loads of FP registers from constant | |
2915 | expressions by forcing the constant into memory. | |
2916 | ||
2917 | use scratch_reg to hold the address of the memory location. | |
2918 | ||
2919 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
2920 | NO_REGS when presented with a const_int and an register class | |
2921 | containing only FP registers. Doing so unfortunately creates | |
2922 | more problems than it solves. Fix this for 2.5. */ | |
2923 | else if (fp_reg_operand (operand0, mode) | |
2924 | && CONSTANT_P (operand1) | |
2925 | && scratch_reg) | |
2926 | { | |
2927 | rtx xoperands[2]; | |
2928 | ||
2929 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2930 | it in SIMODE regardless of what mode it was originally given | |
2931 | to us. */ | |
2932 | scratch_reg = force_mode (SImode, scratch_reg); | |
2933 | ||
2934 | /* Force the constant into memory and put the address of the | |
2935 | memory location into scratch_reg. */ | |
2936 | xoperands[0] = scratch_reg; | |
2937 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
2938 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
2939 | ||
2940 | /* Now load the destination register. */ | |
2941 | emit_insn (gen_rtx_SET (mode, operand0, | |
2942 | gen_rtx_MEM (mode, scratch_reg))); | |
2943 | return 1; | |
2944 | } | |
2945 | ||
2946 | /* Now have insn-emit do whatever it normally does. */ | |
2947 | return 0; | |
2948 | } | |
2949 | ||
01e304f8 RZ |
2950 | /* Split one or more DImode RTL references into pairs of SImode |
2951 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
2952 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
2953 | split and "num" is its length. lo_half and hi_half are output arrays | |
2954 | that parallel "operands". */ | |
2955 | ||
2956 | void | |
2957 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
2958 | { | |
2959 | while (num--) | |
2960 | { | |
2961 | rtx op = operands[num]; | |
2962 | ||
2963 | /* simplify_subreg refuses to split volatile memory addresses, | |
2964 | but we still have to handle it. */ | |
2965 | if (GET_CODE (op) == MEM) | |
2966 | { | |
2967 | lo_half[num] = adjust_address (op, SImode, 4); | |
2968 | hi_half[num] = adjust_address (op, SImode, 0); | |
2969 | } | |
2970 | else | |
2971 | { | |
2972 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
2973 | GET_MODE (op) == VOIDmode | |
2974 | ? DImode : GET_MODE (op), 4); | |
2975 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
2976 | GET_MODE (op) == VOIDmode | |
2977 | ? DImode : GET_MODE (op), 0); | |
2978 | } | |
2979 | } | |
2980 | } | |
2981 | ||
a40ed0f3 KH |
2982 | /* Split X into a base and a constant offset, storing them in *BASE |
2983 | and *OFFSET respectively. */ | |
2984 | ||
2985 | static void | |
2986 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
2987 | { | |
2988 | *offset = 0; | |
2989 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2990 | { | |
2991 | *offset += INTVAL (XEXP (x, 1)); | |
2992 | x = XEXP (x, 0); | |
2993 | } | |
2994 | *base = x; | |
2995 | } | |
2996 | ||
2997 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
2998 | instruction. STORE_P says whether the move is a load or store. | |
2999 | ||
3000 | If the instruction uses post-increment or pre-decrement addressing, | |
3001 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
3002 | adjustment. This adjustment will be made by the first element of | |
3003 | PARALLEL, with the loads or stores starting at element 1. If the | |
3004 | instruction does not use post-increment or pre-decrement addressing, | |
3005 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
3006 | start at element 0. */ | |
3007 | ||
3008 | bool | |
3009 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
3010 | HOST_WIDE_INT automod_offset, bool store_p) | |
3011 | { | |
3012 | rtx base, mem_base, set, mem, reg, last_reg; | |
3013 | HOST_WIDE_INT offset, mem_offset; | |
3014 | int i, first, len; | |
3015 | enum reg_class rclass; | |
3016 | ||
3017 | len = XVECLEN (pattern, 0); | |
3018 | first = (automod_base != NULL); | |
3019 | ||
3020 | if (automod_base) | |
3021 | { | |
3022 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
3023 | if (store_p != (automod_offset < 0)) | |
3024 | return false; | |
3025 | ||
3026 | /* Work out the base and offset for lowest memory location. */ | |
3027 | base = automod_base; | |
3028 | offset = (automod_offset < 0 ? automod_offset : 0); | |
3029 | } | |
3030 | else | |
3031 | { | |
3032 | /* Allow any valid base and offset in the first access. */ | |
3033 | base = NULL; | |
3034 | offset = 0; | |
3035 | } | |
3036 | ||
3037 | last_reg = NULL; | |
3038 | rclass = NO_REGS; | |
3039 | for (i = first; i < len; i++) | |
3040 | { | |
3041 | /* We need a plain SET. */ | |
3042 | set = XVECEXP (pattern, 0, i); | |
3043 | if (GET_CODE (set) != SET) | |
3044 | return false; | |
3045 | ||
3046 | /* Check that we have a memory location... */ | |
3047 | mem = XEXP (set, !store_p); | |
3048 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
3049 | return false; | |
3050 | ||
3051 | /* ...with the right address. */ | |
3052 | if (base == NULL) | |
3053 | { | |
3054 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
3055 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
3056 | There are no mode restrictions for 680x0 besides the | |
3057 | automodification rules enforced above. */ | |
3058 | if (TARGET_COLDFIRE | |
3059 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
3060 | return false; | |
3061 | } | |
3062 | else | |
3063 | { | |
3064 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
3065 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
3066 | return false; | |
3067 | } | |
3068 | ||
3069 | /* Check that we have a register of the required mode and class. */ | |
3070 | reg = XEXP (set, store_p); | |
3071 | if (!REG_P (reg) | |
3072 | || !HARD_REGISTER_P (reg) | |
3073 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
3074 | return false; | |
3075 | ||
3076 | if (last_reg) | |
3077 | { | |
3078 | /* The register must belong to RCLASS and have a higher number | |
3079 | than the register in the previous SET. */ | |
3080 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
3081 | || REGNO (last_reg) >= REGNO (reg)) | |
3082 | return false; | |
3083 | } | |
3084 | else | |
3085 | { | |
3086 | /* Work out which register class we need. */ | |
3087 | if (INT_REGNO_P (REGNO (reg))) | |
3088 | rclass = GENERAL_REGS; | |
3089 | else if (FP_REGNO_P (REGNO (reg))) | |
3090 | rclass = FP_REGS; | |
3091 | else | |
3092 | return false; | |
3093 | } | |
3094 | ||
3095 | last_reg = reg; | |
3096 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
3097 | } | |
3098 | ||
3099 | /* If we have an automodification, check whether the final offset is OK. */ | |
3100 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
3101 | return false; | |
3102 | ||
3103 | /* Reject unprofitable cases. */ | |
3104 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
3105 | return false; | |
3106 | ||
3107 | return true; | |
3108 | } | |
3109 | ||
3110 | /* Return the assembly code template for a movem or fmovem instruction | |
3111 | whose pattern is given by PATTERN. Store the template's operands | |
3112 | in OPERANDS. | |
3113 | ||
3114 | If the instruction uses post-increment or pre-decrement addressing, | |
3115 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
3116 | is true if this is a store instruction. */ | |
3117 | ||
3118 | const char * | |
3119 | m68k_output_movem (rtx *operands, rtx pattern, | |
3120 | HOST_WIDE_INT automod_offset, bool store_p) | |
3121 | { | |
3122 | unsigned int mask; | |
3123 | int i, first; | |
3124 | ||
3125 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
3126 | mask = 0; | |
3127 | first = (automod_offset != 0); | |
3128 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
3129 | { | |
3130 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
3131 | is controlled by bit 15 - X. For all other addressing modes, | |
3132 | register X + D0_REG is controlled by bit X. Confusingly, the | |
3133 | register mask for fmovem is in the opposite order to that for | |
3134 | movem. */ | |
3135 | unsigned int regno; | |
3136 | ||
3137 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
3138 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
3139 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
3140 | if (automod_offset < 0) | |
3141 | { | |
3142 | if (FP_REGNO_P (regno)) | |
3143 | mask |= 1 << (regno - FP0_REG); | |
3144 | else | |
3145 | mask |= 1 << (15 - (regno - D0_REG)); | |
3146 | } | |
3147 | else | |
3148 | { | |
3149 | if (FP_REGNO_P (regno)) | |
3150 | mask |= 1 << (7 - (regno - FP0_REG)); | |
3151 | else | |
3152 | mask |= 1 << (regno - D0_REG); | |
3153 | } | |
3154 | } | |
3155 | CC_STATUS_INIT; | |
3156 | ||
3157 | if (automod_offset == 0) | |
3158 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
3159 | else if (automod_offset < 0) | |
3160 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3161 | else | |
3162 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3163 | operands[1] = GEN_INT (mask); | |
3164 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
3165 | { | |
3166 | if (store_p) | |
3167 | return MOTOROLA ? "fmovm %1,%a0" : "fmovem %1,%a0"; | |
3168 | else | |
3169 | return MOTOROLA ? "fmovm %a0,%1" : "fmovem %a0,%1"; | |
3170 | } | |
3171 | else | |
3172 | { | |
3173 | if (store_p) | |
3174 | return MOTOROLA ? "movm.l %1,%a0" : "moveml %1,%a0"; | |
3175 | else | |
3176 | return MOTOROLA ? "movm.l %a0,%1" : "moveml %a0,%1"; | |
3177 | } | |
3178 | } | |
3179 | ||
79e68feb RS |
3180 | /* Return a REG that occurs in ADDR with coefficient 1. |
3181 | ADDR can be effectively incremented by incrementing REG. */ | |
3182 | ||
3183 | static rtx | |
8a4a2253 | 3184 | find_addr_reg (rtx addr) |
79e68feb RS |
3185 | { |
3186 | while (GET_CODE (addr) == PLUS) | |
3187 | { | |
3188 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3189 | addr = XEXP (addr, 0); | |
3190 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3191 | addr = XEXP (addr, 1); | |
3192 | else if (CONSTANT_P (XEXP (addr, 0))) | |
3193 | addr = XEXP (addr, 1); | |
3194 | else if (CONSTANT_P (XEXP (addr, 1))) | |
3195 | addr = XEXP (addr, 0); | |
3196 | else | |
4761e388 | 3197 | gcc_unreachable (); |
79e68feb | 3198 | } |
4761e388 NS |
3199 | gcc_assert (GET_CODE (addr) == REG); |
3200 | return addr; | |
79e68feb | 3201 | } |
9ee3c687 | 3202 | |
c16eadc7 | 3203 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 3204 | |
5505f548 | 3205 | const char * |
8a4a2253 | 3206 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
3207 | { |
3208 | if (! operands_match_p (operands[0], operands[1])) | |
3209 | { | |
3210 | if (!ADDRESS_REG_P (operands[1])) | |
3211 | { | |
3212 | rtx tmp = operands[1]; | |
3213 | ||
3214 | operands[1] = operands[2]; | |
3215 | operands[2] = tmp; | |
3216 | } | |
3217 | ||
3218 | /* These insns can result from reloads to access | |
3219 | stack slots over 64k from the frame pointer. */ | |
3220 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 3221 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 3222 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 3223 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
3224 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
3225 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
3226 | } |
3227 | if (GET_CODE (operands[2]) == CONST_INT) | |
3228 | { | |
9ee3c687 JW |
3229 | if (INTVAL (operands[2]) > 0 |
3230 | && INTVAL (operands[2]) <= 8) | |
3231 | return "addq%.l %2,%0"; | |
3232 | if (INTVAL (operands[2]) < 0 | |
3233 | && INTVAL (operands[2]) >= -8) | |
3234 | { | |
c5c76735 | 3235 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
3236 | return "subq%.l %2,%0"; |
3237 | } | |
3238 | /* On the CPU32 it is faster to use two addql instructions to | |
3239 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 3240 | Likewise for subql. */ |
fe95f2f7 | 3241 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
3242 | { |
3243 | if (INTVAL (operands[2]) > 8 | |
3244 | && INTVAL (operands[2]) <= 16) | |
3245 | { | |
1d8eaa6b | 3246 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 3247 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
3248 | } |
3249 | if (INTVAL (operands[2]) < -8 | |
3250 | && INTVAL (operands[2]) >= -16) | |
3251 | { | |
c5c76735 | 3252 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 3253 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
3254 | } |
3255 | } | |
9ee3c687 JW |
3256 | if (ADDRESS_REG_P (operands[0]) |
3257 | && INTVAL (operands[2]) >= -0x8000 | |
3258 | && INTVAL (operands[2]) < 0x8000) | |
3259 | { | |
fe95f2f7 | 3260 | if (TUNE_68040) |
9ee3c687 JW |
3261 | return "add%.w %2,%0"; |
3262 | else | |
e6d98cb0 | 3263 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
3264 | } |
3265 | } | |
3266 | return "add%.l %2,%0"; | |
3267 | } | |
79e68feb RS |
3268 | \f |
3269 | /* Store in cc_status the expressions that the condition codes will | |
3270 | describe after execution of an instruction whose pattern is EXP. | |
3271 | Do not alter them if the instruction would not alter the cc's. */ | |
3272 | ||
3273 | /* On the 68000, all the insns to store in an address register fail to | |
3274 | set the cc's. However, in some cases these instructions can make it | |
3275 | possibly invalid to use the saved cc's. In those cases we clear out | |
3276 | some or all of the saved cc's so they won't be used. */ | |
3277 | ||
1d8eaa6b | 3278 | void |
8a4a2253 | 3279 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 3280 | { |
1a8965c4 | 3281 | if (GET_CODE (exp) == SET) |
79e68feb RS |
3282 | { |
3283 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 3284 | CC_STATUS_INIT; |
79e68feb RS |
3285 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
3286 | { | |
f5963e61 | 3287 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 3288 | cc_status.value1 = 0; |
f5963e61 | 3289 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
3290 | cc_status.value2 = 0; |
3291 | } | |
f6ab62e8 RS |
3292 | /* fmoves to memory or data registers do not set the condition |
3293 | codes. Normal moves _do_ set the condition codes, but not in | |
3294 | a way that is appropriate for comparison with 0, because -0.0 | |
3295 | would be treated as a negative nonzero number. Note that it | |
88512ba0 | 3296 | isn't appropriate to conditionalize this restriction on |
f6ab62e8 RS |
3297 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
3298 | we care about the difference between -0.0 and +0.0. */ | |
79e68feb RS |
3299 | else if (!FP_REG_P (SET_DEST (exp)) |
3300 | && SET_DEST (exp) != cc0_rtx | |
3301 | && (FP_REG_P (SET_SRC (exp)) | |
3302 | || GET_CODE (SET_SRC (exp)) == FIX | |
f6ab62e8 | 3303 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
a0a7fbc9 | 3304 | CC_STATUS_INIT; |
79e68feb RS |
3305 | /* A pair of move insns doesn't produce a useful overall cc. */ |
3306 | else if (!FP_REG_P (SET_DEST (exp)) | |
3307 | && !FP_REG_P (SET_SRC (exp)) | |
3308 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
3309 | && (GET_CODE (SET_SRC (exp)) == REG | |
3310 | || GET_CODE (SET_SRC (exp)) == MEM | |
3311 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 3312 | CC_STATUS_INIT; |
e1dff52a | 3313 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
3314 | { |
3315 | cc_status.flags = 0; | |
e1dff52a KH |
3316 | cc_status.value1 = SET_DEST (exp); |
3317 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
3318 | } |
3319 | } | |
3320 | else if (GET_CODE (exp) == PARALLEL | |
3321 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
3322 | { | |
e1dff52a KH |
3323 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
3324 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
3325 | ||
3326 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 3327 | CC_STATUS_INIT; |
e1dff52a | 3328 | else if (dest != pc_rtx) |
79e68feb RS |
3329 | { |
3330 | cc_status.flags = 0; | |
e1dff52a KH |
3331 | cc_status.value1 = dest; |
3332 | cc_status.value2 = src; | |
79e68feb RS |
3333 | } |
3334 | } | |
3335 | else | |
3336 | CC_STATUS_INIT; | |
3337 | if (cc_status.value2 != 0 | |
3338 | && ADDRESS_REG_P (cc_status.value2) | |
3339 | && GET_MODE (cc_status.value2) == QImode) | |
3340 | CC_STATUS_INIT; | |
1a8965c4 | 3341 | if (cc_status.value2 != 0) |
79e68feb RS |
3342 | switch (GET_CODE (cc_status.value2)) |
3343 | { | |
996a5f59 | 3344 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 3345 | case ROTATE: case ROTATERT: |
a126dc3a RH |
3346 | /* These instructions always clear the overflow bit, and set |
3347 | the carry to the bit shifted out. */ | |
3348 | /* ??? We don't currently have a way to signal carry not valid, | |
3349 | nor do we check for it in the branch insns. */ | |
3350 | CC_STATUS_INIT; | |
3351 | break; | |
3352 | ||
3353 | case PLUS: case MINUS: case MULT: | |
3354 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
3355 | if (GET_MODE (cc_status.value2) != VOIDmode) |
3356 | cc_status.flags |= CC_NO_OVERFLOW; | |
3357 | break; | |
3358 | case ZERO_EXTEND: | |
3359 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
3360 | ends with a move insn moving r2 in r2's mode. | |
3361 | Thus, the cc's are set for r2. | |
7a1929e1 | 3362 | This can set N bit spuriously. */ |
79e68feb | 3363 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
3364 | |
3365 | default: | |
3366 | break; | |
79e68feb RS |
3367 | } |
3368 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
3369 | && cc_status.value2 | |
3370 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
3371 | cc_status.value2 = 0; | |
3372 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 3373 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
3374 | cc_status.flags = CC_IN_68881; |
3375 | } | |
3376 | \f | |
5505f548 | 3377 | const char * |
8a4a2253 | 3378 | output_move_const_double (rtx *operands) |
79e68feb | 3379 | { |
1a8965c4 | 3380 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3381 | |
1a8965c4 | 3382 | if (code != 0) |
79e68feb | 3383 | { |
1a8965c4 | 3384 | static char buf[40]; |
79e68feb | 3385 | |
3b4b85c9 | 3386 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3387 | return buf; |
79e68feb | 3388 | } |
1a8965c4 | 3389 | return "fmove%.d %1,%0"; |
79e68feb RS |
3390 | } |
3391 | ||
5505f548 | 3392 | const char * |
8a4a2253 | 3393 | output_move_const_single (rtx *operands) |
79e68feb | 3394 | { |
1a8965c4 | 3395 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3396 | |
1a8965c4 | 3397 | if (code != 0) |
79e68feb | 3398 | { |
1a8965c4 | 3399 | static char buf[40]; |
79e68feb | 3400 | |
3b4b85c9 | 3401 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3402 | return buf; |
79e68feb | 3403 | } |
1a8965c4 | 3404 | return "fmove%.s %f1,%0"; |
79e68feb RS |
3405 | } |
3406 | ||
3407 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
3408 | from the "fmovecr" instruction. | |
3409 | The value, anded with 0xff, gives the code to use in fmovecr | |
3410 | to get the desired constant. */ | |
3411 | ||
7a1929e1 | 3412 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
3413 | |
3414 | static int inited_68881_table = 0; | |
3415 | ||
5505f548 | 3416 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
3417 | "0.0", |
3418 | "1.0", | |
3419 | "10.0", | |
3420 | "100.0", | |
3421 | "10000.0", | |
3422 | "1e8", | |
3423 | "1e16" | |
a0a7fbc9 | 3424 | }; |
c1cfb2ae | 3425 | |
8b60264b | 3426 | static const int codes_68881[7] = { |
c1cfb2ae RS |
3427 | 0x0f, |
3428 | 0x32, | |
3429 | 0x33, | |
3430 | 0x34, | |
3431 | 0x35, | |
3432 | 0x36, | |
3433 | 0x37 | |
a0a7fbc9 | 3434 | }; |
c1cfb2ae RS |
3435 | |
3436 | REAL_VALUE_TYPE values_68881[7]; | |
3437 | ||
3438 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 3439 | strings_68881 to binary. */ |
c1cfb2ae RS |
3440 | |
3441 | void | |
8a4a2253 | 3442 | init_68881_table (void) |
c1cfb2ae RS |
3443 | { |
3444 | int i; | |
3445 | REAL_VALUE_TYPE r; | |
3446 | enum machine_mode mode; | |
3447 | ||
16d82c3c | 3448 | mode = SFmode; |
c1cfb2ae RS |
3449 | for (i = 0; i < 7; i++) |
3450 | { | |
3451 | if (i == 6) | |
16d82c3c | 3452 | mode = DFmode; |
c1cfb2ae RS |
3453 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
3454 | values_68881[i] = r; | |
3455 | } | |
3456 | inited_68881_table = 1; | |
3457 | } | |
79e68feb RS |
3458 | |
3459 | int | |
8a4a2253 | 3460 | standard_68881_constant_p (rtx x) |
79e68feb | 3461 | { |
c1cfb2ae RS |
3462 | REAL_VALUE_TYPE r; |
3463 | int i; | |
79e68feb | 3464 | |
e18db50d | 3465 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 3466 | used at all on those chips. */ |
9cf106c8 | 3467 | if (TUNE_68040_60) |
79e68feb RS |
3468 | return 0; |
3469 | ||
c1cfb2ae RS |
3470 | if (! inited_68881_table) |
3471 | init_68881_table (); | |
3472 | ||
3473 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3474 | ||
64c0b414 AS |
3475 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
3476 | is rejected. */ | |
c1cfb2ae RS |
3477 | for (i = 0; i < 6; i++) |
3478 | { | |
64c0b414 | 3479 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
3480 | return (codes_68881[i]); |
3481 | } | |
3482 | ||
79e68feb RS |
3483 | if (GET_MODE (x) == SFmode) |
3484 | return 0; | |
c1cfb2ae RS |
3485 | |
3486 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
3487 | return (codes_68881[6]); | |
3488 | ||
79e68feb RS |
3489 | /* larger powers of ten in the constants ram are not used |
3490 | because they are not equal to a `double' C constant. */ | |
3491 | return 0; | |
3492 | } | |
3493 | ||
3494 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3495 | or 0 if X is not a power of 2. */ | |
3496 | ||
3497 | int | |
8a4a2253 | 3498 | floating_exact_log2 (rtx x) |
79e68feb | 3499 | { |
c1cfb2ae | 3500 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3501 | int exp; |
79e68feb | 3502 | |
c1cfb2ae | 3503 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3504 | |
eaff3bf8 | 3505 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3506 | return 0; |
3507 | ||
eaff3bf8 RH |
3508 | exp = real_exponent (&r); |
3509 | real_2expN (&r1, exp); | |
3510 | if (REAL_VALUES_EQUAL (r1, r)) | |
3511 | return exp; | |
3512 | ||
79e68feb RS |
3513 | return 0; |
3514 | } | |
3515 | \f | |
79e68feb RS |
3516 | /* A C compound statement to output to stdio stream STREAM the |
3517 | assembler syntax for an instruction operand X. X is an RTL | |
3518 | expression. | |
3519 | ||
3520 | CODE is a value that can be used to specify one of several ways | |
3521 | of printing the operand. It is used when identical operands | |
3522 | must be printed differently depending on the context. CODE | |
3523 | comes from the `%' specification that was used to request | |
3524 | printing of the operand. If the specification was just `%DIGIT' | |
3525 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3526 | is the ASCII code for LTR. | |
3527 | ||
3528 | If X is a register, this macro should print the register's name. | |
3529 | The names can be found in an array `reg_names' whose type is | |
3530 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3531 | ||
3532 | When the machine description has a specification `%PUNCT' (a `%' | |
3533 | followed by a punctuation character), this macro is called with | |
3534 | a null pointer for X and the punctuation character for CODE. | |
3535 | ||
3536 | The m68k specific codes are: | |
3537 | ||
3538 | '.' for dot needed in Motorola-style opcode names. | |
3539 | '-' for an operand pushing on the stack: | |
3540 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3541 | '+' for an operand pushing on the stack: | |
3542 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3543 | '@' for a reference to the top word on the stack: | |
3544 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3545 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3546 | but & in SGS syntax). |
79e68feb RS |
3547 | '!' for the cc register (used in an `and to cc' insn). |
3548 | '$' for the letter `s' in an op code, but only on the 68040. | |
3549 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3550 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 3551 | '?' for m68k_library_id_string |
79e68feb RS |
3552 | |
3553 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3554 | 'd' to force memory addressing to be absolute, not relative. | |
3555 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
3556 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3557 | or print pair of registers as rx:ry. | |
29ca003a RS |
3558 | 'p' print an address with @PLTPC attached, but only if the operand |
3559 | is not locally-bound. */ | |
79e68feb RS |
3560 | |
3561 | void | |
8a4a2253 | 3562 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3563 | { |
79e68feb RS |
3564 | if (letter == '.') |
3565 | { | |
e6d98cb0 BI |
3566 | if (MOTOROLA) |
3567 | fprintf (file, "."); | |
79e68feb RS |
3568 | } |
3569 | else if (letter == '#') | |
e6d98cb0 | 3570 | asm_fprintf (file, "%I"); |
79e68feb | 3571 | else if (letter == '-') |
e6d98cb0 | 3572 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 3573 | else if (letter == '+') |
e6d98cb0 | 3574 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 3575 | else if (letter == '@') |
e6d98cb0 | 3576 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 3577 | else if (letter == '!') |
e6d98cb0 | 3578 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3579 | else if (letter == '$') |
3580 | { | |
b101567e | 3581 | if (TARGET_68040) |
e6d98cb0 | 3582 | fprintf (file, "s"); |
79e68feb RS |
3583 | } |
3584 | else if (letter == '&') | |
3585 | { | |
b101567e | 3586 | if (TARGET_68040) |
e6d98cb0 | 3587 | fprintf (file, "d"); |
79e68feb | 3588 | } |
2ac5f14a | 3589 | else if (letter == '/') |
e6d98cb0 | 3590 | asm_fprintf (file, "%R"); |
a40ed0f3 KH |
3591 | else if (letter == '?') |
3592 | asm_fprintf (file, m68k_library_id_string); | |
29ca003a | 3593 | else if (letter == 'p') |
2c8ec431 | 3594 | { |
29ca003a RS |
3595 | output_addr_const (file, op); |
3596 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
3597 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 3598 | } |
79e68feb RS |
3599 | else if (GET_CODE (op) == REG) |
3600 | { | |
1a8965c4 AS |
3601 | if (letter == 'R') |
3602 | /* Print out the second register name of a register pair. | |
3603 | I.e., R (6) => 7. */ | |
01bbf777 | 3604 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3605 | else |
01bbf777 | 3606 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3607 | } |
3608 | else if (GET_CODE (op) == MEM) | |
3609 | { | |
3610 | output_address (XEXP (op, 0)); | |
3611 | if (letter == 'd' && ! TARGET_68020 | |
3612 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3613 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3614 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3615 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 3616 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 3617 | } |
79e68feb RS |
3618 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3619 | { | |
c1cfb2ae RS |
3620 | REAL_VALUE_TYPE r; |
3621 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3622 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3623 | } | |
3624 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3625 | { | |
3626 | REAL_VALUE_TYPE r; | |
3627 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3628 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3629 | } |
e2c0a924 | 3630 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3631 | { |
c1cfb2ae RS |
3632 | REAL_VALUE_TYPE r; |
3633 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3634 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3635 | } |
3636 | else | |
3637 | { | |
2c8ec431 DL |
3638 | /* Use `print_operand_address' instead of `output_addr_const' |
3639 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3640 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3641 | if (TARGET_PCREL |
3642 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3643 | print_operand_address (file, op); | |
3644 | else | |
3645 | output_addr_const (file, op); | |
79e68feb RS |
3646 | } |
3647 | } | |
3648 | ||
3649 | \f | |
3650 | /* A C compound statement to output to stdio stream STREAM the | |
3651 | assembler syntax for an instruction operand that is a memory | |
3652 | reference whose address is ADDR. ADDR is an RTL expression. | |
3653 | ||
3654 | Note that this contains a kludge that knows that the only reason | |
3655 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3656 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3657 | generates a label LInnn: on such an insn. | |
3658 | ||
3659 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3660 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3661 | ||
3662 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
3663 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
3664 | we want. This difference can be accommodated by using an assembler | |
3665 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
3666 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 3667 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
3668 | Some assemblers refuse all the above solutions. The workaround is to |
3669 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 3670 | right behavior. |
79e68feb RS |
3671 | |
3672 | They also do not like things like "pea 1.w", so we simple leave off | |
3673 | the .w on small constants. | |
3674 | ||
3675 | This routine is responsible for distinguishing between -fpic and -fPIC | |
3676 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3677 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3678 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb RS |
3679 | |
3680 | void | |
8a4a2253 | 3681 | print_operand_address (FILE *file, rtx addr) |
79e68feb | 3682 | { |
fc2241eb RS |
3683 | struct m68k_address address; |
3684 | ||
3685 | if (!m68k_decompose_address (QImode, addr, true, &address)) | |
3686 | gcc_unreachable (); | |
3687 | ||
3688 | if (address.code == PRE_DEC) | |
3689 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", | |
3690 | M68K_REGNAME (REGNO (address.base))); | |
3691 | else if (address.code == POST_INC) | |
3692 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", | |
3693 | M68K_REGNAME (REGNO (address.base))); | |
3694 | else if (!address.base && !address.index) | |
3695 | { | |
3696 | /* A constant address. */ | |
3697 | gcc_assert (address.offset == addr); | |
3698 | if (GET_CODE (addr) == CONST_INT) | |
3699 | { | |
3700 | /* (xxx).w or (xxx).l. */ | |
3701 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
3702 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); | |
a0a7fbc9 | 3703 | else |
fc2241eb | 3704 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
a0a7fbc9 | 3705 | } |
fc2241eb | 3706 | else if (TARGET_PCREL) |
a0a7fbc9 | 3707 | { |
fc2241eb RS |
3708 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
3709 | fputc ('(', file); | |
3710 | output_addr_const (file, addr); | |
3711 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
a0a7fbc9 | 3712 | } |
fc2241eb | 3713 | else |
a0a7fbc9 | 3714 | { |
fc2241eb RS |
3715 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
3716 | name ends in `.<letter>', as the last 2 characters can be | |
3717 | mistaken as a size suffix. Put the name in parentheses. */ | |
3718 | if (GET_CODE (addr) == SYMBOL_REF | |
3719 | && strlen (XSTR (addr, 0)) > 2 | |
3720 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
a0a7fbc9 | 3721 | { |
fc2241eb RS |
3722 | putc ('(', file); |
3723 | output_addr_const (file, addr); | |
3724 | putc (')', file); | |
a0a7fbc9 AS |
3725 | } |
3726 | else | |
fc2241eb | 3727 | output_addr_const (file, addr); |
a0a7fbc9 | 3728 | } |
fc2241eb RS |
3729 | } |
3730 | else | |
3731 | { | |
3732 | int labelno; | |
3733 | ||
3734 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
3735 | label being acceesed, otherwise it is -1. */ | |
3736 | labelno = (address.offset | |
3737 | && !address.base | |
3738 | && GET_CODE (address.offset) == LABEL_REF | |
3739 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
3740 | : -1); | |
3741 | if (MOTOROLA) | |
a0a7fbc9 | 3742 | { |
fc2241eb RS |
3743 | /* Print the "offset(base" component. */ |
3744 | if (labelno >= 0) | |
3745 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,", labelno, labelno); | |
3746 | else | |
a0a7fbc9 | 3747 | { |
fc2241eb | 3748 | if (address.offset) |
a0a7fbc9 | 3749 | { |
fc2241eb RS |
3750 | output_addr_const (file, address.offset); |
3751 | if (flag_pic && address.base == pic_offset_table_rtx) | |
a0a7fbc9 AS |
3752 | { |
3753 | fprintf (file, "@GOT"); | |
fc2241eb | 3754 | if (flag_pic == 1 && TARGET_68020) |
a0a7fbc9 AS |
3755 | fprintf (file, ".w"); |
3756 | } | |
3757 | } | |
fc2241eb RS |
3758 | putc ('(', file); |
3759 | if (address.base) | |
3760 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
a0a7fbc9 | 3761 | } |
fc2241eb RS |
3762 | /* Print the ",index" component, if any. */ |
3763 | if (address.index) | |
a0a7fbc9 | 3764 | { |
fc2241eb RS |
3765 | if (address.base) |
3766 | putc (',', file); | |
3767 | fprintf (file, "%s.%c", | |
3768 | M68K_REGNAME (REGNO (address.index)), | |
3769 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3770 | if (address.scale != 1) | |
3771 | fprintf (file, "*%d", address.scale); | |
a0a7fbc9 | 3772 | } |
a0a7fbc9 | 3773 | putc (')', file); |
a0a7fbc9 | 3774 | } |
fc2241eb | 3775 | else /* !MOTOROLA */ |
a0a7fbc9 | 3776 | { |
fc2241eb RS |
3777 | if (!address.offset && !address.index) |
3778 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
a0a7fbc9 | 3779 | else |
a0a7fbc9 | 3780 | { |
fc2241eb RS |
3781 | /* Print the "base@(offset" component. */ |
3782 | if (labelno >= 0) | |
3783 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b", labelno, labelno); | |
3784 | else | |
3785 | { | |
3786 | if (address.base) | |
3787 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
3788 | fprintf (file, "@("); | |
3789 | if (address.offset) | |
3790 | { | |
3791 | output_addr_const (file, address.offset); | |
3792 | if (address.base == pic_offset_table_rtx && TARGET_68020) | |
3793 | switch (flag_pic) | |
3794 | { | |
3795 | case 1: | |
3796 | fprintf (file, ":w"); break; | |
3797 | case 2: | |
3798 | fprintf (file, ":l"); break; | |
3799 | default: | |
3800 | break; | |
3801 | } | |
3802 | } | |
3803 | } | |
3804 | /* Print the ",index" component, if any. */ | |
3805 | if (address.index) | |
3806 | { | |
3807 | fprintf (file, ",%s:%c", | |
3808 | M68K_REGNAME (REGNO (address.index)), | |
3809 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3810 | if (address.scale != 1) | |
3811 | fprintf (file, ":%d", address.scale); | |
3812 | } | |
a0a7fbc9 AS |
3813 | putc (')', file); |
3814 | } | |
a0a7fbc9 | 3815 | } |
79e68feb RS |
3816 | } |
3817 | } | |
af13f02d JW |
3818 | \f |
3819 | /* Check for cases where a clr insns can be omitted from code using | |
3820 | strict_low_part sets. For example, the second clrl here is not needed: | |
3821 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3822 | ||
3823 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3824 | insn we are checking for redundancy. TARGET is the register set by the | |
3825 | clear insn. */ | |
3826 | ||
8a4a2253 BI |
3827 | bool |
3828 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3829 | rtx target) | |
af13f02d JW |
3830 | { |
3831 | rtx p; | |
3832 | ||
3833 | p = prev_nonnote_insn (first_insn); | |
3834 | ||
3835 | while (p) | |
3836 | { | |
3837 | /* If it isn't an insn, then give up. */ | |
3838 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 3839 | return false; |
af13f02d JW |
3840 | |
3841 | if (reg_set_p (target, p)) | |
3842 | { | |
3843 | rtx set = single_set (p); | |
3844 | rtx dest; | |
3845 | ||
3846 | /* If it isn't an easy to recognize insn, then give up. */ | |
3847 | if (! set) | |
8a4a2253 | 3848 | return false; |
af13f02d JW |
3849 | |
3850 | dest = SET_DEST (set); | |
3851 | ||
3852 | /* If this sets the entire target register to zero, then our | |
3853 | first_insn is redundant. */ | |
3854 | if (rtx_equal_p (dest, target) | |
3855 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3856 | return true; |
af13f02d JW |
3857 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3858 | && GET_CODE (XEXP (dest, 0)) == REG | |
3859 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3860 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3861 | <= GET_MODE_SIZE (mode))) | |
3862 | /* This is a strict low part set which modifies less than | |
3863 | we are using, so it is safe. */ | |
3864 | ; | |
3865 | else | |
8a4a2253 | 3866 | return false; |
af13f02d JW |
3867 | } |
3868 | ||
3869 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3870 | } |
3871 | ||
8a4a2253 | 3872 | return false; |
af13f02d | 3873 | } |
67cd4f83 | 3874 | |
2c8ec431 DL |
3875 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3876 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3877 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3878 | |
3879 | We model this by restricting the meaning of the basic predicates | |
3880 | (general_operand, memory_operand, etc) to forbid the use of this | |
3881 | addressing mode, and then define the following predicates that permit | |
3882 | this addressing mode. These predicates can then be used for the | |
3883 | source operands of the appropriate instructions. | |
3884 | ||
3885 | n.b. While it is theoretically possible to change all machine patterns | |
3886 | to use this addressing more where permitted by the architecture, | |
3887 | it has only been implemented for "common" cases: SImode, HImode, and | |
3888 | QImode operands, and only for the principle operations that would | |
3889 | require this addressing mode: data movement and simple integer operations. | |
3890 | ||
3891 | In parallel with these new predicates, two new constraint letters | |
3892 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3893 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3894 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3895 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3896 | of how these constraints are used. | |
3897 | ||
3898 | The use of these predicates is strictly optional, though patterns that | |
3899 | don't will cause an extra reload register to be allocated where one | |
3900 | was not necessary: | |
3901 | ||
3902 | lea (abc:w,%pc),%a0 ; need to reload address | |
3903 | moveq &1,%d1 ; since write to pc-relative space | |
3904 | movel %d1,%a0@ ; is not allowed | |
3905 | ... | |
3906 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3907 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3908 | ||
3909 | For more info, consult tiemann@cygnus.com. | |
3910 | ||
3911 | ||
3912 | All of the ugliness with predicates and constraints is due to the | |
3913 | simple fact that the m68k does not allow a pc-relative addressing | |
3914 | mode as a destination. gcc does not distinguish between source and | |
3915 | destination addresses. Hence, if we claim that pc-relative address | |
3916 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3917 | end up with invalid code. To get around this problem, we left | |
3918 | pc-relative modes as invalid addresses, and then added special | |
3919 | predicates and constraints to accept them. | |
3920 | ||
3921 | A cleaner way to handle this is to modify gcc to distinguish | |
3922 | between source and destination addresses. We can then say that | |
3923 | pc-relative is a valid source address but not a valid destination | |
3924 | address, and hopefully avoid a lot of the predicate and constraint | |
3925 | hackery. Unfortunately, this would be a pretty big change. It would | |
3926 | be a useful change for a number of ports, but there aren't any current | |
3927 | plans to undertake this. | |
3928 | ||
3929 | ***************************************************************************/ | |
3930 | ||
3931 | ||
5505f548 | 3932 | const char * |
8a4a2253 | 3933 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3934 | { |
3935 | int logval; | |
3936 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 3937 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
3938 | && (DATA_REG_P (operands[0]) |
3939 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3940 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3941 | { |
3942 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3943 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 3944 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
3945 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3946 | CC_STATUS_INIT; | |
3947 | if (operands[2] == const0_rtx) | |
3948 | return "clr%.w %0"; | |
3949 | return "and%.w %2,%0"; | |
3950 | } | |
3951 | if (GET_CODE (operands[2]) == CONST_INT | |
3952 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
3953 | && (DATA_REG_P (operands[0]) | |
3954 | || offsettable_memref_p (operands[0]))) | |
3955 | { | |
3956 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 3957 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3958 | else |
3959 | { | |
b72f00af | 3960 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3961 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3962 | } |
3963 | /* This does not set condition codes in a standard way. */ | |
3964 | CC_STATUS_INIT; | |
3965 | return "bclr %1,%0"; | |
3966 | } | |
3967 | return "and%.l %2,%0"; | |
3968 | } | |
3969 | ||
5505f548 | 3970 | const char * |
8a4a2253 | 3971 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
3972 | { |
3973 | register int logval; | |
3974 | if (GET_CODE (operands[2]) == CONST_INT | |
3975 | && INTVAL (operands[2]) >> 16 == 0 | |
3976 | && (DATA_REG_P (operands[0]) | |
3977 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 3978 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
3979 | { |
3980 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 3981 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
3982 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
3983 | CC_STATUS_INIT; | |
3984 | if (INTVAL (operands[2]) == 0xffff) | |
3985 | return "mov%.w %2,%0"; | |
3986 | return "or%.w %2,%0"; | |
3987 | } | |
3988 | if (GET_CODE (operands[2]) == CONST_INT | |
3989 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
3990 | && (DATA_REG_P (operands[0]) | |
3991 | || offsettable_memref_p (operands[0]))) | |
3992 | { | |
3993 | if (DATA_REG_P (operands[0])) | |
b72f00af | 3994 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
3995 | else |
3996 | { | |
b72f00af | 3997 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 3998 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
3999 | } |
4000 | CC_STATUS_INIT; | |
4001 | return "bset %1,%0"; | |
4002 | } | |
4003 | return "or%.l %2,%0"; | |
4004 | } | |
4005 | ||
5505f548 | 4006 | const char * |
8a4a2253 | 4007 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
4008 | { |
4009 | register int logval; | |
4010 | if (GET_CODE (operands[2]) == CONST_INT | |
4011 | && INTVAL (operands[2]) >> 16 == 0 | |
4012 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 4013 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4014 | { |
4015 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 4016 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4017 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4018 | CC_STATUS_INIT; | |
4019 | if (INTVAL (operands[2]) == 0xffff) | |
4020 | return "not%.w %0"; | |
4021 | return "eor%.w %2,%0"; | |
4022 | } | |
4023 | if (GET_CODE (operands[2]) == CONST_INT | |
4024 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
4025 | && (DATA_REG_P (operands[0]) | |
4026 | || offsettable_memref_p (operands[0]))) | |
4027 | { | |
4028 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4029 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4030 | else |
4031 | { | |
b72f00af | 4032 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4033 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4034 | } |
4035 | CC_STATUS_INIT; | |
4036 | return "bchg %1,%0"; | |
4037 | } | |
4038 | return "eor%.l %2,%0"; | |
4039 | } | |
7c262518 | 4040 | |
29ca003a RS |
4041 | /* Return the instruction that should be used for a call to address X, |
4042 | which is known to be in operand 0. */ | |
4043 | ||
4044 | const char * | |
4045 | output_call (rtx x) | |
4046 | { | |
4047 | if (symbolic_operand (x, VOIDmode)) | |
4048 | return m68k_symbolic_call; | |
4049 | else | |
4050 | return "jsr %a0"; | |
4051 | } | |
4052 | ||
f7e70894 RS |
4053 | /* Likewise sibling calls. */ |
4054 | ||
4055 | const char * | |
4056 | output_sibcall (rtx x) | |
4057 | { | |
4058 | if (symbolic_operand (x, VOIDmode)) | |
4059 | return m68k_symbolic_jump; | |
4060 | else | |
4061 | return "jmp %a0"; | |
4062 | } | |
4063 | ||
45849738 BI |
4064 | #ifdef M68K_TARGET_COFF |
4065 | ||
4066 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
4067 | ||
4068 | static void | |
c18a5b6c MM |
4069 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
4070 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
4071 | { |
4072 | char flagchar; | |
4073 | ||
4074 | if (flags & SECTION_WRITE) | |
4075 | flagchar = 'd'; | |
4076 | else | |
4077 | flagchar = 'x'; | |
4078 | ||
4079 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
4080 | } | |
4081 | ||
4082 | #endif /* M68K_TARGET_COFF */ | |
4083 | ||
c590b625 | 4084 | static void |
8a4a2253 | 4085 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
4ab870f5 | 4086 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
8a4a2253 | 4087 | tree function) |
483ab821 | 4088 | { |
4ab870f5 RS |
4089 | rtx this_slot, offset, addr, mem, insn; |
4090 | ||
4091 | /* Pretend to be a post-reload pass while generating rtl. */ | |
4092 | no_new_pseudos = 1; | |
4093 | reload_completed = 1; | |
4094 | reset_block_changes (); | |
4095 | allocate_reg_info (FIRST_PSEUDO_REGISTER, true, true); | |
4096 | ||
4097 | /* The "this" pointer is stored at 4(%sp). */ | |
4098 | this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4)); | |
4099 | ||
4100 | /* Add DELTA to THIS. */ | |
4101 | if (delta != 0) | |
5050d266 | 4102 | { |
4ab870f5 RS |
4103 | /* Make the offset a legitimate operand for memory addition. */ |
4104 | offset = GEN_INT (delta); | |
4105 | if ((delta < -8 || delta > 8) | |
4106 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
4107 | { | |
4108 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
4109 | offset = gen_rtx_REG (Pmode, D0_REG); | |
4110 | } | |
4111 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4112 | copy_rtx (this_slot), offset)); | |
5050d266 | 4113 | } |
c590b625 | 4114 | |
4ab870f5 RS |
4115 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
4116 | if (vcall_offset != 0) | |
4117 | { | |
4118 | /* Set the static chain register to *THIS. */ | |
4119 | emit_move_insn (static_chain_rtx, this_slot); | |
4120 | emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx)); | |
4121 | ||
4122 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
4123 | addr = plus_constant (static_chain_rtx, vcall_offset); | |
4124 | if (!m68k_legitimate_address_p (Pmode, addr, true)) | |
4125 | { | |
4126 | emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr)); | |
4127 | addr = static_chain_rtx; | |
4128 | } | |
c590b625 | 4129 | |
4ab870f5 RS |
4130 | /* Load the offset into %d0 and add it to THIS. */ |
4131 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
4132 | gen_rtx_MEM (Pmode, addr)); | |
4133 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4134 | copy_rtx (this_slot), | |
4135 | gen_rtx_REG (Pmode, D0_REG))); | |
4136 | } | |
29ca003a | 4137 | |
4ab870f5 RS |
4138 | /* Jump to the target function. Use a sibcall if direct jumps are |
4139 | allowed, otherwise load the address into a register first. */ | |
4140 | mem = DECL_RTL (function); | |
4141 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
4142 | { | |
4143 | gcc_assert (flag_pic); | |
c590b625 | 4144 | |
4ab870f5 RS |
4145 | if (!TARGET_SEP_DATA) |
4146 | { | |
4147 | /* Use the static chain register as a temporary (call-clobbered) | |
4148 | GOT pointer for this function. We can use the static chain | |
4149 | register because it isn't live on entry to the thunk. */ | |
4150 | REGNO (pic_offset_table_rtx) = STATIC_CHAIN_REGNUM; | |
4151 | emit_insn (gen_load_got (pic_offset_table_rtx)); | |
4152 | } | |
4153 | legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx); | |
4154 | mem = replace_equiv_address (mem, static_chain_rtx); | |
4155 | } | |
4156 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
4157 | SIBLING_CALL_P (insn) = 1; | |
4158 | ||
4159 | /* Run just enough of rest_of_compilation. */ | |
4160 | insn = get_insns (); | |
4161 | split_all_insns_noflow (); | |
4162 | final_start_function (insn, file, 1); | |
4163 | final (insn, file, 1); | |
4164 | final_end_function (); | |
4165 | ||
4166 | /* Clean up the vars set above. */ | |
4167 | reload_completed = 0; | |
4168 | no_new_pseudos = 0; | |
4169 | ||
4170 | /* Restore the original PIC register. */ | |
4171 | if (flag_pic) | |
4172 | REGNO (pic_offset_table_rtx) = PIC_REG; | |
483ab821 | 4173 | } |
8636be86 KH |
4174 | |
4175 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
4176 | ||
4177 | static rtx | |
4178 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
4179 | int incoming ATTRIBUTE_UNUSED) | |
4180 | { | |
4181 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
4182 | } | |
cfca21cb PB |
4183 | |
4184 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
4185 | int | |
4186 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
4187 | unsigned int new_reg) | |
4188 | { | |
4189 | ||
4190 | /* Interrupt functions can only use registers that have already been | |
4191 | saved by the prologue, even if they would normally be | |
4192 | call-clobbered. */ | |
4193 | ||
4194 | if (m68k_interrupt_function_p (current_function_decl) | |
4195 | && !regs_ever_live[new_reg]) | |
4196 | return 0; | |
4197 | ||
4198 | return 1; | |
4199 | } | |
70028b61 | 4200 | |
ffa2596e RS |
4201 | /* Value is true if hard register REGNO can hold a value of machine-mode |
4202 | MODE. On the 68000, we let the cpu registers can hold any mode, but | |
4203 | restrict the 68881 registers to floating-point modes. */ | |
4204 | ||
70028b61 PB |
4205 | bool |
4206 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
4207 | { | |
36e04090 | 4208 | if (DATA_REGNO_P (regno)) |
70028b61 | 4209 | { |
a0a7fbc9 AS |
4210 | /* Data Registers, can hold aggregate if fits in. */ |
4211 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
4212 | return true; | |
70028b61 | 4213 | } |
36e04090 | 4214 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 4215 | { |
a0a7fbc9 AS |
4216 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
4217 | return true; | |
70028b61 | 4218 | } |
36e04090 | 4219 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
4220 | { |
4221 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
4222 | smaller. */ |
4223 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4224 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 4225 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 4226 | return true; |
70028b61 PB |
4227 | } |
4228 | return false; | |
4229 | } | |
dcc21c4c | 4230 | |
ffa2596e RS |
4231 | /* Implement SECONDARY_RELOAD_CLASS. */ |
4232 | ||
4233 | enum reg_class | |
4234 | m68k_secondary_reload_class (enum reg_class rclass, | |
4235 | enum machine_mode mode, rtx x) | |
4236 | { | |
4237 | int regno; | |
4238 | ||
4239 | regno = true_regnum (x); | |
4240 | ||
4241 | /* If one operand of a movqi is an address register, the other | |
4242 | operand must be a general register or constant. Other types | |
4243 | of operand must be reloaded through a data register. */ | |
4244 | if (GET_MODE_SIZE (mode) == 1 | |
4245 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
4246 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
4247 | return DATA_REGS; | |
4248 | ||
4249 | /* PC-relative addresses must be loaded into an address register first. */ | |
4250 | if (TARGET_PCREL | |
4251 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
4252 | && symbolic_operand (x, VOIDmode)) | |
4253 | return ADDR_REGS; | |
4254 | ||
4255 | return NO_REGS; | |
4256 | } | |
4257 | ||
4258 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
4259 | ||
4260 | enum reg_class | |
4261 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
4262 | { | |
4263 | enum reg_class secondary_class; | |
4264 | ||
4265 | /* If RCLASS might need a secondary reload, try restricting it to | |
4266 | a class that doesn't. */ | |
4267 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
4268 | if (secondary_class != NO_REGS | |
4269 | && reg_class_subset_p (secondary_class, rclass)) | |
4270 | return secondary_class; | |
4271 | ||
4272 | /* Prefer to use moveq for in-range constants. */ | |
4273 | if (GET_CODE (x) == CONST_INT | |
4274 | && reg_class_subset_p (DATA_REGS, rclass) | |
4275 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
4276 | return DATA_REGS; | |
4277 | ||
4278 | /* ??? Do we really need this now? */ | |
4279 | if (GET_CODE (x) == CONST_DOUBLE | |
4280 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
4281 | { | |
4282 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
4283 | return FP_REGS; | |
4284 | ||
4285 | return NO_REGS; | |
4286 | } | |
4287 | ||
4288 | return rclass; | |
4289 | } | |
4290 | ||
dcc21c4c PB |
4291 | /* Return floating point values in a 68881 register. This makes 68881 code |
4292 | a little bit faster. It also makes -msoft-float code incompatible with | |
4293 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 4294 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
4295 | If there is need for a hard-float ABI it is probably worth doing it |
4296 | properly and also passing function arguments in FP registers. */ | |
4297 | rtx | |
4298 | m68k_libcall_value (enum machine_mode mode) | |
4299 | { | |
4300 | switch (mode) { | |
4301 | case SFmode: | |
4302 | case DFmode: | |
4303 | case XFmode: | |
4304 | if (TARGET_68881) | |
4305 | return gen_rtx_REG (mode, 16); | |
4306 | break; | |
4307 | default: | |
4308 | break; | |
4309 | } | |
4310 | return gen_rtx_REG (mode, 0); | |
4311 | } | |
4312 | ||
4313 | rtx | |
4314 | m68k_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
4315 | { | |
4316 | enum machine_mode mode; | |
4317 | ||
4318 | mode = TYPE_MODE (valtype); | |
4319 | switch (mode) { | |
4320 | case SFmode: | |
4321 | case DFmode: | |
4322 | case XFmode: | |
4323 | if (TARGET_68881) | |
4324 | return gen_rtx_REG (mode, 16); | |
4325 | break; | |
4326 | default: | |
4327 | break; | |
4328 | } | |
4329 | ||
576c9028 KH |
4330 | /* If the function returns a pointer, push that into %a0. */ |
4331 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
4332 | /* For compatibility with the large body of existing code which | |
4333 | does not always properly declare external functions returning | |
4334 | pointer types, the m68k/SVR4 convention is to copy the value | |
4335 | returned for pointer functions from a0 to d0 in the function | |
4336 | epilogue, so that callers that have neglected to properly | |
4337 | declare the callee can still find the correct return value in | |
4338 | d0. */ | |
4339 | return gen_rtx_PARALLEL | |
4340 | (mode, | |
4341 | gen_rtvec (2, | |
4342 | gen_rtx_EXPR_LIST (VOIDmode, | |
4343 | gen_rtx_REG (mode, A0_REG), | |
4344 | const0_rtx), | |
4345 | gen_rtx_EXPR_LIST (VOIDmode, | |
4346 | gen_rtx_REG (mode, D0_REG), | |
4347 | const0_rtx))); | |
4348 | else if (POINTER_TYPE_P (valtype)) | |
4349 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 4350 | else |
576c9028 | 4351 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 4352 | } |