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79e68feb | 1 | /* Subroutines for insn-output.c for Motorola 68000 family. |
8636be86 | 2 | Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
b6a9c30c | 3 | 2001, 2003, 2004, 2005, 2006, 2007 |
4592bdcb | 4 | Free Software Foundation, Inc. |
79e68feb | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
79e68feb | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
79e68feb | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
79e68feb RS |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
79e68feb RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
79e68feb | 21 | |
79e68feb | 22 | #include "config.h" |
f5220a5d | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
da932f04 | 26 | #include "tree.h" |
79e68feb | 27 | #include "rtl.h" |
49ad7cfa | 28 | #include "function.h" |
79e68feb RS |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
79e68feb RS |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
1d8eaa6b | 36 | #include "recog.h" |
f5220a5d | 37 | #include "toplev.h" |
6d5f49b2 RH |
38 | #include "expr.h" |
39 | #include "reload.h" | |
5505f548 | 40 | #include "tm_p.h" |
672a6f42 NB |
41 | #include "target.h" |
42 | #include "target-def.h" | |
2cc07db4 | 43 | #include "debug.h" |
79e68feb | 44 | #include "flags.h" |
6fb5fa3c | 45 | #include "df.h" |
79e68feb | 46 | |
a4e9467d RZ |
47 | enum reg_class regno_reg_class[] = |
48 | { | |
49 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
50 | DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, | |
51 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
52 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
53 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
54 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
55 | ADDR_REGS | |
56 | }; | |
57 | ||
58 | ||
a40ed0f3 KH |
59 | /* The minimum number of integer registers that we want to save with the |
60 | movem instruction. Using two movel instructions instead of a single | |
61 | moveml is about 15% faster for the 68020 and 68030 at no expense in | |
62 | code size. */ | |
63 | #define MIN_MOVEM_REGS 3 | |
64 | ||
65 | /* The minimum number of floating point registers that we want to save | |
66 | with the fmovem instruction. */ | |
67 | #define MIN_FMOVEM_REGS 1 | |
68 | ||
ff482c8d | 69 | /* Structure describing stack frame layout. */ |
3d74bc09 BI |
70 | struct m68k_frame |
71 | { | |
72 | /* Stack pointer to frame pointer offset. */ | |
48ed72a4 | 73 | HOST_WIDE_INT offset; |
3d74bc09 BI |
74 | |
75 | /* Offset of FPU registers. */ | |
76 | HOST_WIDE_INT foffset; | |
77 | ||
78 | /* Frame size in bytes (rounded up). */ | |
48ed72a4 | 79 | HOST_WIDE_INT size; |
3d74bc09 BI |
80 | |
81 | /* Data and address register. */ | |
48ed72a4 PB |
82 | int reg_no; |
83 | unsigned int reg_mask; | |
3d74bc09 BI |
84 | |
85 | /* FPU registers. */ | |
48ed72a4 PB |
86 | int fpu_no; |
87 | unsigned int fpu_mask; | |
3d74bc09 BI |
88 | |
89 | /* Offsets relative to ARG_POINTER. */ | |
48ed72a4 PB |
90 | HOST_WIDE_INT frame_pointer_offset; |
91 | HOST_WIDE_INT stack_pointer_offset; | |
3d74bc09 BI |
92 | |
93 | /* Function which the above information refers to. */ | |
94 | int funcdef_no; | |
48ed72a4 PB |
95 | }; |
96 | ||
3d74bc09 BI |
97 | /* Current frame information calculated by m68k_compute_frame_layout(). */ |
98 | static struct m68k_frame current_frame; | |
99 | ||
fc2241eb RS |
100 | /* Structure describing an m68k address. |
101 | ||
102 | If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, | |
103 | with null fields evaluating to 0. Here: | |
104 | ||
105 | - BASE satisfies m68k_legitimate_base_reg_p | |
106 | - INDEX satisfies m68k_legitimate_index_reg_p | |
107 | - OFFSET satisfies m68k_legitimate_constant_address_p | |
108 | ||
109 | INDEX is either HImode or SImode. The other fields are SImode. | |
110 | ||
111 | If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, | |
112 | the address is (BASE)+. */ | |
113 | struct m68k_address { | |
114 | enum rtx_code code; | |
115 | rtx base; | |
116 | rtx index; | |
117 | rtx offset; | |
118 | int scale; | |
119 | }; | |
120 | ||
4af06170 | 121 | static bool m68k_handle_option (size_t, const char *, int); |
8a4a2253 BI |
122 | static rtx find_addr_reg (rtx); |
123 | static const char *singlemove_string (rtx *); | |
45849738 | 124 | #ifdef M68K_TARGET_COFF |
c18a5b6c | 125 | static void m68k_coff_asm_named_section (const char *, unsigned int, tree); |
45849738 | 126 | #endif /* M68K_TARGET_COFF */ |
8a4a2253 BI |
127 | static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
128 | HOST_WIDE_INT, tree); | |
8636be86 | 129 | static rtx m68k_struct_value_rtx (tree, int); |
48ed72a4 PB |
130 | static tree m68k_handle_fndecl_attribute (tree *node, tree name, |
131 | tree args, int flags, | |
132 | bool *no_add_attrs); | |
3d74bc09 | 133 | static void m68k_compute_frame_layout (void); |
48ed72a4 | 134 | static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); |
f7e70894 | 135 | static bool m68k_ok_for_sibcall_p (tree, tree); |
8a4a2253 | 136 | static bool m68k_rtx_costs (rtx, int, int, int *); |
1c445f03 NS |
137 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
138 | static bool m68k_return_in_memory (tree, tree); | |
139 | #endif | |
79e68feb RS |
140 | \f |
141 | ||
a2ef3db7 | 142 | /* Specify the identification number of the library being built */ |
4af06170 | 143 | const char *m68k_library_id_string = "_current_shared_library_a5_offset_"; |
ef1dbfb0 | 144 | |
2b3600ac JL |
145 | /* Nonzero if the last compare/test insn had FP operands. The |
146 | sCC expanders peek at this to determine what to do for the | |
147 | 68060, which has no fsCC instructions. */ | |
148 | int m68k_last_compare_had_fp_operands; | |
672a6f42 NB |
149 | \f |
150 | /* Initialize the GCC target structure. */ | |
301d03af RS |
151 | |
152 | #if INT_OP_GROUP == INT_OP_DOT_WORD | |
153 | #undef TARGET_ASM_ALIGNED_HI_OP | |
154 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
155 | #endif | |
156 | ||
157 | #if INT_OP_GROUP == INT_OP_NO_DOT | |
158 | #undef TARGET_ASM_BYTE_OP | |
159 | #define TARGET_ASM_BYTE_OP "\tbyte\t" | |
160 | #undef TARGET_ASM_ALIGNED_HI_OP | |
161 | #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" | |
162 | #undef TARGET_ASM_ALIGNED_SI_OP | |
163 | #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" | |
164 | #endif | |
165 | ||
166 | #if INT_OP_GROUP == INT_OP_DC | |
167 | #undef TARGET_ASM_BYTE_OP | |
168 | #define TARGET_ASM_BYTE_OP "\tdc.b\t" | |
169 | #undef TARGET_ASM_ALIGNED_HI_OP | |
170 | #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" | |
171 | #undef TARGET_ASM_ALIGNED_SI_OP | |
172 | #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" | |
173 | #endif | |
174 | ||
175 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
176 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
177 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
178 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
179 | ||
c590b625 RH |
180 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
181 | #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk | |
bdabc150 | 182 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 183 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 184 | |
1bc7c5b6 ZW |
185 | #undef TARGET_ASM_FILE_START_APP_OFF |
186 | #define TARGET_ASM_FILE_START_APP_OFF true | |
187 | ||
4af06170 RS |
188 | #undef TARGET_HANDLE_OPTION |
189 | #define TARGET_HANDLE_OPTION m68k_handle_option | |
190 | ||
3c50106f RH |
191 | #undef TARGET_RTX_COSTS |
192 | #define TARGET_RTX_COSTS m68k_rtx_costs | |
193 | ||
48ed72a4 PB |
194 | #undef TARGET_ATTRIBUTE_TABLE |
195 | #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table | |
196 | ||
8636be86 | 197 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 198 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
8636be86 KH |
199 | |
200 | #undef TARGET_STRUCT_VALUE_RTX | |
201 | #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx | |
202 | ||
7ffb5e78 RS |
203 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
204 | #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p | |
205 | ||
f7e70894 RS |
206 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
207 | #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p | |
208 | ||
1c445f03 NS |
209 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT |
210 | #undef TARGET_RETURN_IN_MEMORY | |
211 | #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory | |
212 | #endif | |
213 | ||
48ed72a4 PB |
214 | static const struct attribute_spec m68k_attribute_table[] = |
215 | { | |
216 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
2bccb817 | 217 | { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
48ed72a4 | 218 | { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
a4242737 | 219 | { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute }, |
48ed72a4 PB |
220 | { NULL, 0, 0, false, false, false, NULL } |
221 | }; | |
222 | ||
f6897b10 | 223 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 224 | \f |
900ec02d JB |
225 | /* Base flags for 68k ISAs. */ |
226 | #define FL_FOR_isa_00 FL_ISA_68000 | |
227 | #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) | |
228 | /* FL_68881 controls the default setting of -m68881. gcc has traditionally | |
229 | generated 68881 code for 68020 and 68030 targets unless explicitly told | |
230 | not to. */ | |
231 | #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ | |
232 | | FL_BITFIELD | FL_68881) | |
233 | #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) | |
234 | #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) | |
235 | ||
236 | /* Base flags for ColdFire ISAs. */ | |
237 | #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) | |
238 | #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) | |
239 | /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ | |
240 | #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) | |
4e2b26aa NS |
241 | /* ISA_C is not upwardly compatible with ISA_B. */ |
242 | #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_HWDIV | FL_CF_USP) | |
900ec02d JB |
243 | |
244 | enum m68k_isa | |
245 | { | |
246 | /* Traditional 68000 instruction sets. */ | |
247 | isa_00, | |
248 | isa_10, | |
249 | isa_20, | |
250 | isa_40, | |
251 | isa_cpu32, | |
252 | /* ColdFire instruction set variants. */ | |
253 | isa_a, | |
254 | isa_aplus, | |
255 | isa_b, | |
256 | isa_c, | |
257 | isa_max | |
258 | }; | |
259 | ||
260 | /* Information about one of the -march, -mcpu or -mtune arguments. */ | |
261 | struct m68k_target_selection | |
262 | { | |
263 | /* The argument being described. */ | |
264 | const char *name; | |
265 | ||
266 | /* For -mcpu, this is the device selected by the option. | |
267 | For -mtune and -march, it is a representative device | |
268 | for the microarchitecture or ISA respectively. */ | |
269 | enum target_device device; | |
270 | ||
271 | /* The M68K_DEVICE fields associated with DEVICE. See the comment | |
272 | in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ | |
273 | const char *family; | |
274 | enum uarch_type microarch; | |
275 | enum m68k_isa isa; | |
276 | unsigned long flags; | |
277 | }; | |
278 | ||
279 | /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ | |
280 | static const struct m68k_target_selection all_devices[] = | |
281 | { | |
282 | #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ | |
283 | { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, | |
284 | #include "m68k-devices.def" | |
285 | #undef M68K_DEVICE | |
286 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
287 | }; | |
288 | ||
289 | /* A list of all ISAs, mapping each one to a representative device. | |
290 | Used for -march selection. */ | |
291 | static const struct m68k_target_selection all_isas[] = | |
292 | { | |
293 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
294 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
295 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
296 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
297 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
298 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
299 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
300 | { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a | |
301 | | FL_CF_HWDIV) }, | |
302 | { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus | |
303 | | FL_CF_HWDIV) }, | |
304 | { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
fe116068 | 305 | { "isac", unk_device, NULL, ucfv4, isa_c, FL_FOR_isa_c }, |
900ec02d JB |
306 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } |
307 | }; | |
308 | ||
309 | /* A list of all microarchitectures, mapping each one to a representative | |
310 | device. Used for -mtune selection. */ | |
311 | static const struct m68k_target_selection all_microarchs[] = | |
312 | { | |
313 | { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, | |
314 | { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, | |
315 | { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, | |
316 | { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, | |
317 | { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, | |
318 | { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, | |
319 | { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, | |
320 | { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, | |
321 | { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, | |
322 | { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, | |
323 | { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a | |
324 | | FL_CF_HWDIV) }, | |
325 | { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, | |
326 | { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b | |
327 | | FL_CF_USP | |
328 | | FL_CF_EMAC | |
329 | | FL_CF_FPU) }, | |
330 | { NULL, unk_device, NULL, unk_arch, isa_max, 0 } | |
331 | }; | |
332 | \f | |
333 | /* The entries associated with the -mcpu, -march and -mtune settings, | |
334 | or null for options that have not been used. */ | |
335 | const struct m68k_target_selection *m68k_cpu_entry; | |
336 | const struct m68k_target_selection *m68k_arch_entry; | |
337 | const struct m68k_target_selection *m68k_tune_entry; | |
338 | ||
339 | /* Which CPU we are generating code for. */ | |
340 | enum target_device m68k_cpu; | |
341 | ||
342 | /* Which microarchitecture to tune for. */ | |
343 | enum uarch_type m68k_tune; | |
344 | ||
345 | /* Which FPU to use. */ | |
346 | enum fpu_type m68k_fpu; | |
4af06170 | 347 | |
900ec02d JB |
348 | /* The set of FL_* flags that apply to the target processor. */ |
349 | unsigned int m68k_cpu_flags; | |
29ca003a RS |
350 | |
351 | /* Asm templates for calling or jumping to an arbitrary symbolic address, | |
352 | or NULL if such calls or jumps are not supported. The address is held | |
353 | in operand 0. */ | |
354 | const char *m68k_symbolic_call; | |
355 | const char *m68k_symbolic_jump; | |
900ec02d JB |
356 | \f |
357 | /* See whether TABLE has an entry with name NAME. Return true and | |
358 | store the entry in *ENTRY if so, otherwise return false and | |
359 | leave *ENTRY alone. */ | |
360 | ||
361 | static bool | |
362 | m68k_find_selection (const struct m68k_target_selection **entry, | |
363 | const struct m68k_target_selection *table, | |
364 | const char *name) | |
365 | { | |
366 | size_t i; | |
367 | ||
368 | for (i = 0; table[i].name; i++) | |
369 | if (strcmp (table[i].name, name) == 0) | |
370 | { | |
371 | *entry = table + i; | |
372 | return true; | |
373 | } | |
374 | return false; | |
375 | } | |
4af06170 RS |
376 | |
377 | /* Implement TARGET_HANDLE_OPTION. */ | |
378 | ||
379 | static bool | |
380 | m68k_handle_option (size_t code, const char *arg, int value) | |
381 | { | |
382 | switch (code) | |
383 | { | |
900ec02d JB |
384 | case OPT_march_: |
385 | return m68k_find_selection (&m68k_arch_entry, all_isas, arg); | |
386 | ||
387 | case OPT_mcpu_: | |
388 | return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); | |
389 | ||
390 | case OPT_mtune_: | |
391 | return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); | |
392 | ||
4af06170 | 393 | case OPT_m5200: |
900ec02d | 394 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); |
4af06170 RS |
395 | |
396 | case OPT_m5206e: | |
900ec02d | 397 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); |
4af06170 RS |
398 | |
399 | case OPT_m528x: | |
900ec02d | 400 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); |
4af06170 RS |
401 | |
402 | case OPT_m5307: | |
900ec02d | 403 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); |
4af06170 RS |
404 | |
405 | case OPT_m5407: | |
900ec02d | 406 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); |
4af06170 | 407 | |
dcc21c4c | 408 | case OPT_mcfv4e: |
900ec02d | 409 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); |
dcc21c4c | 410 | |
4af06170 RS |
411 | case OPT_m68000: |
412 | case OPT_mc68000: | |
900ec02d | 413 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); |
4af06170 | 414 | |
3197c489 | 415 | case OPT_m68010: |
900ec02d | 416 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); |
3197c489 | 417 | |
4af06170 RS |
418 | case OPT_m68020: |
419 | case OPT_mc68020: | |
900ec02d | 420 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); |
4af06170 RS |
421 | |
422 | case OPT_m68020_40: | |
900ec02d JB |
423 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
424 | "68020-40") | |
425 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
426 | |
427 | case OPT_m68020_60: | |
900ec02d JB |
428 | return (m68k_find_selection (&m68k_tune_entry, all_microarchs, |
429 | "68020-60") | |
430 | && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); | |
4af06170 RS |
431 | |
432 | case OPT_m68030: | |
900ec02d | 433 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); |
4af06170 RS |
434 | |
435 | case OPT_m68040: | |
900ec02d | 436 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); |
4af06170 RS |
437 | |
438 | case OPT_m68060: | |
900ec02d | 439 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); |
4af06170 RS |
440 | |
441 | case OPT_m68302: | |
900ec02d | 442 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); |
4af06170 RS |
443 | |
444 | case OPT_m68332: | |
445 | case OPT_mcpu32: | |
900ec02d | 446 | return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); |
4af06170 RS |
447 | |
448 | case OPT_mshared_library_id_: | |
449 | if (value > MAX_LIBRARY_ID) | |
450 | error ("-mshared-library-id=%s is not between 0 and %d", | |
451 | arg, MAX_LIBRARY_ID); | |
452 | else | |
453 | asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4); | |
454 | return true; | |
455 | ||
456 | default: | |
457 | return true; | |
458 | } | |
459 | } | |
460 | ||
ef1dbfb0 RK |
461 | /* Sometimes certain combinations of command options do not make |
462 | sense on a particular target machine. You can define a macro | |
463 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
464 | defined, is executed once just after all the command options have | |
465 | been parsed. | |
466 | ||
467 | Don't use this macro to turn on various extra optimizations for | |
468 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
469 | ||
470 | void | |
8a4a2253 | 471 | override_options (void) |
ef1dbfb0 | 472 | { |
900ec02d JB |
473 | const struct m68k_target_selection *entry; |
474 | unsigned long target_mask; | |
475 | ||
476 | /* User can choose: | |
477 | ||
478 | -mcpu= | |
479 | -march= | |
480 | -mtune= | |
481 | ||
482 | -march=ARCH should generate code that runs any processor | |
483 | implementing architecture ARCH. -mcpu=CPU should override -march | |
484 | and should generate code that runs on processor CPU, making free | |
485 | use of any instructions that CPU understands. -mtune=UARCH applies | |
9f5ed61a | 486 | on top of -mcpu or -march and optimizes the code for UARCH. It does |
900ec02d JB |
487 | not change the target architecture. */ |
488 | if (m68k_cpu_entry) | |
489 | { | |
490 | /* Complain if the -march setting is for a different microarchitecture, | |
491 | or includes flags that the -mcpu setting doesn't. */ | |
492 | if (m68k_arch_entry | |
493 | && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch | |
494 | || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) | |
495 | warning (0, "-mcpu=%s conflicts with -march=%s", | |
496 | m68k_cpu_entry->name, m68k_arch_entry->name); | |
497 | ||
498 | entry = m68k_cpu_entry; | |
499 | } | |
500 | else | |
501 | entry = m68k_arch_entry; | |
502 | ||
503 | if (!entry) | |
504 | entry = all_devices + TARGET_CPU_DEFAULT; | |
505 | ||
506 | m68k_cpu_flags = entry->flags; | |
507 | ||
508 | /* Use the architecture setting to derive default values for | |
509 | certain flags. */ | |
510 | target_mask = 0; | |
8785d88c KH |
511 | |
512 | /* ColdFire is lenient about alignment. */ | |
513 | if (!TARGET_COLDFIRE) | |
514 | target_mask |= MASK_STRICT_ALIGNMENT; | |
515 | ||
900ec02d JB |
516 | if ((m68k_cpu_flags & FL_BITFIELD) != 0) |
517 | target_mask |= MASK_BITFIELD; | |
518 | if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) | |
519 | target_mask |= MASK_CF_HWDIV; | |
520 | if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) | |
521 | target_mask |= MASK_HARD_FLOAT; | |
522 | target_flags |= target_mask & ~target_flags_explicit; | |
523 | ||
524 | /* Set the directly-usable versions of the -mcpu and -mtune settings. */ | |
525 | m68k_cpu = entry->device; | |
526 | if (m68k_tune_entry) | |
527 | m68k_tune = m68k_tune_entry->microarch; | |
528 | #ifdef M68K_DEFAULT_TUNE | |
529 | else if (!m68k_cpu_entry && !m68k_arch_entry) | |
530 | m68k_tune = M68K_DEFAULT_TUNE; | |
531 | #endif | |
532 | else | |
533 | m68k_tune = entry->microarch; | |
534 | ||
535 | /* Set the type of FPU. */ | |
536 | m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE | |
537 | : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE | |
538 | : FPUTYPE_68881); | |
539 | ||
a2ef3db7 BI |
540 | /* Sanity check to ensure that msep-data and mid-sahred-library are not |
541 | * both specified together. Doing so simply doesn't make sense. | |
542 | */ | |
543 | if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) | |
544 | error ("cannot specify both -msep-data and -mid-shared-library"); | |
545 | ||
546 | /* If we're generating code for a separate A5 relative data segment, | |
547 | * we've got to enable -fPIC as well. This might be relaxable to | |
548 | * -fpic but it hasn't been tested properly. | |
549 | */ | |
550 | if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) | |
551 | flag_pic = 2; | |
552 | ||
abe92a04 RS |
553 | /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an |
554 | error if the target does not support them. */ | |
555 | if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) | |
556 | error ("-mpcrel -fPIC is not currently supported on selected cpu"); | |
adf2ac37 RH |
557 | |
558 | /* ??? A historic way of turning on pic, or is this intended to | |
559 | be an embedded thing that doesn't have the same name binding | |
560 | significance that it does on hosted ELF systems? */ | |
561 | if (TARGET_PCREL && flag_pic == 0) | |
562 | flag_pic = 1; | |
563 | ||
29ca003a RS |
564 | if (!flag_pic) |
565 | { | |
566 | #if MOTOROLA && !defined (USE_GAS) | |
567 | m68k_symbolic_call = "jsr %a0"; | |
568 | m68k_symbolic_jump = "jmp %a0"; | |
569 | #else | |
570 | m68k_symbolic_call = "jbsr %a0"; | |
571 | m68k_symbolic_jump = "jra %a0"; | |
572 | #endif | |
573 | } | |
574 | else if (TARGET_ID_SHARED_LIBRARY) | |
575 | /* All addresses must be loaded from the GOT. */ | |
576 | ; | |
4e2b26aa | 577 | else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) |
29ca003a RS |
578 | { |
579 | if (TARGET_PCREL) | |
4e2b26aa NS |
580 | m68k_symbolic_call = "bsr.l %c0"; |
581 | else | |
29ca003a | 582 | { |
4e2b26aa NS |
583 | #if defined(USE_GAS) |
584 | m68k_symbolic_call = "bsr.l %p0"; | |
585 | #else | |
586 | m68k_symbolic_call = "bsr %p0"; | |
587 | #endif | |
29ca003a | 588 | } |
4e2b26aa NS |
589 | if (TARGET_ISAC) |
590 | /* No unconditional long branch */; | |
591 | else if (TARGET_PCREL) | |
592 | m68k_symbolic_jump = "bra.l %c0"; | |
29ca003a RS |
593 | else |
594 | { | |
595 | #if defined(USE_GAS) | |
29ca003a RS |
596 | m68k_symbolic_jump = "bra.l %p0"; |
597 | #else | |
29ca003a RS |
598 | m68k_symbolic_jump = "bra %p0"; |
599 | #endif | |
600 | } | |
601 | /* Turn off function cse if we are doing PIC. We always want | |
602 | function call to be done as `bsr foo@PLTPC'. */ | |
603 | /* ??? It's traditional to do this for -mpcrel too, but it isn't | |
604 | clear how intentional that is. */ | |
605 | flag_no_function_cse = 1; | |
606 | } | |
adf2ac37 RH |
607 | |
608 | SUBTARGET_OVERRIDE_OPTIONS; | |
ef1dbfb0 | 609 | } |
7eb4f044 NS |
610 | |
611 | /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the | |
612 | given argument and NAME is the argument passed to -mcpu. Return NULL | |
613 | if -mcpu was not passed. */ | |
614 | ||
615 | const char * | |
616 | m68k_cpp_cpu_ident (const char *prefix) | |
617 | { | |
618 | if (!m68k_cpu_entry) | |
619 | return NULL; | |
620 | return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); | |
621 | } | |
622 | ||
623 | /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the | |
624 | given argument and NAME is the name of the representative device for | |
625 | the -mcpu argument's family. Return NULL if -mcpu was not passed. */ | |
626 | ||
627 | const char * | |
628 | m68k_cpp_cpu_family (const char *prefix) | |
629 | { | |
630 | if (!m68k_cpu_entry) | |
631 | return NULL; | |
632 | return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); | |
633 | } | |
79e68feb | 634 | \f |
2bccb817 KH |
635 | /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or |
636 | "interrupt_handler" attribute and interrupt_thread if FUNC has an | |
637 | "interrupt_thread" attribute. Otherwise, return | |
638 | m68k_fk_normal_function. */ | |
a4242737 KH |
639 | |
640 | enum m68k_function_kind | |
641 | m68k_get_function_kind (tree func) | |
48ed72a4 PB |
642 | { |
643 | tree a; | |
644 | ||
fa157b28 NS |
645 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
646 | ||
2bccb817 KH |
647 | a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); |
648 | if (a != NULL_TREE) | |
649 | return m68k_fk_interrupt_handler; | |
650 | ||
48ed72a4 | 651 | a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); |
a4242737 KH |
652 | if (a != NULL_TREE) |
653 | return m68k_fk_interrupt_handler; | |
654 | ||
655 | a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); | |
656 | if (a != NULL_TREE) | |
657 | return m68k_fk_interrupt_thread; | |
658 | ||
659 | return m68k_fk_normal_function; | |
48ed72a4 PB |
660 | } |
661 | ||
662 | /* Handle an attribute requiring a FUNCTION_DECL; arguments as in | |
663 | struct attribute_spec.handler. */ | |
664 | static tree | |
665 | m68k_handle_fndecl_attribute (tree *node, tree name, | |
666 | tree args ATTRIBUTE_UNUSED, | |
667 | int flags ATTRIBUTE_UNUSED, | |
668 | bool *no_add_attrs) | |
669 | { | |
670 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
671 | { | |
5c498b10 | 672 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
48ed72a4 PB |
673 | IDENTIFIER_POINTER (name)); |
674 | *no_add_attrs = true; | |
675 | } | |
676 | ||
a4242737 KH |
677 | if (m68k_get_function_kind (*node) != m68k_fk_normal_function) |
678 | { | |
679 | error ("multiple interrupt attributes not allowed"); | |
680 | *no_add_attrs = true; | |
681 | } | |
682 | ||
683 | if (!TARGET_FIDOA | |
684 | && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) | |
685 | { | |
686 | error ("interrupt_thread is available only on fido"); | |
687 | *no_add_attrs = true; | |
688 | } | |
689 | ||
48ed72a4 PB |
690 | return NULL_TREE; |
691 | } | |
860c4900 BI |
692 | |
693 | static void | |
3d74bc09 | 694 | m68k_compute_frame_layout (void) |
860c4900 BI |
695 | { |
696 | int regno, saved; | |
a40ed0f3 | 697 | unsigned int mask; |
a4242737 KH |
698 | enum m68k_function_kind func_kind = |
699 | m68k_get_function_kind (current_function_decl); | |
700 | bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; | |
701 | bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; | |
860c4900 | 702 | |
3d74bc09 BI |
703 | /* Only compute the frame once per function. |
704 | Don't cache information until reload has been completed. */ | |
705 | if (current_frame.funcdef_no == current_function_funcdef_no | |
706 | && reload_completed) | |
707 | return; | |
708 | ||
709 | current_frame.size = (get_frame_size () + 3) & -4; | |
860c4900 | 710 | |
a40ed0f3 | 711 | mask = saved = 0; |
a4242737 KH |
712 | |
713 | /* Interrupt thread does not need to save any register. */ | |
714 | if (!interrupt_thread) | |
715 | for (regno = 0; regno < 16; regno++) | |
716 | if (m68k_save_reg (regno, interrupt_handler)) | |
717 | { | |
718 | mask |= 1 << (regno - D0_REG); | |
719 | saved++; | |
720 | } | |
3d74bc09 BI |
721 | current_frame.offset = saved * 4; |
722 | current_frame.reg_no = saved; | |
723 | current_frame.reg_mask = mask; | |
860c4900 | 724 | |
57047680 | 725 | current_frame.foffset = 0; |
a40ed0f3 | 726 | mask = saved = 0; |
dcc21c4c | 727 | if (TARGET_HARD_FLOAT) |
860c4900 | 728 | { |
a4242737 KH |
729 | /* Interrupt thread does not need to save any register. */ |
730 | if (!interrupt_thread) | |
731 | for (regno = 16; regno < 24; regno++) | |
732 | if (m68k_save_reg (regno, interrupt_handler)) | |
733 | { | |
734 | mask |= 1 << (regno - FP0_REG); | |
735 | saved++; | |
736 | } | |
dcc21c4c | 737 | current_frame.foffset = saved * TARGET_FP_REG_SIZE; |
3d74bc09 | 738 | current_frame.offset += current_frame.foffset; |
860c4900 | 739 | } |
57047680 GN |
740 | current_frame.fpu_no = saved; |
741 | current_frame.fpu_mask = mask; | |
3d74bc09 BI |
742 | |
743 | /* Remember what function this frame refers to. */ | |
744 | current_frame.funcdef_no = current_function_funcdef_no; | |
860c4900 BI |
745 | } |
746 | ||
747 | HOST_WIDE_INT | |
748 | m68k_initial_elimination_offset (int from, int to) | |
749 | { | |
42b67c06 PB |
750 | int argptr_offset; |
751 | /* The arg pointer points 8 bytes before the start of the arguments, | |
752 | as defined by FIRST_PARM_OFFSET. This makes it coincident with the | |
753 | frame pointer in most frames. */ | |
754 | argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; | |
860c4900 | 755 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
42b67c06 | 756 | return argptr_offset; |
860c4900 | 757 | |
3d74bc09 | 758 | m68k_compute_frame_layout (); |
860c4900 | 759 | |
4761e388 NS |
760 | gcc_assert (to == STACK_POINTER_REGNUM); |
761 | switch (from) | |
762 | { | |
a0a7fbc9 | 763 | case ARG_POINTER_REGNUM: |
42b67c06 | 764 | return current_frame.offset + current_frame.size - argptr_offset; |
4761e388 NS |
765 | case FRAME_POINTER_REGNUM: |
766 | return current_frame.offset + current_frame.size; | |
767 | default: | |
768 | gcc_unreachable (); | |
769 | } | |
860c4900 BI |
770 | } |
771 | ||
97c55091 GN |
772 | /* Refer to the array `regs_ever_live' to determine which registers |
773 | to save; `regs_ever_live[I]' is nonzero if register number I | |
774 | is ever used in the function. This function is responsible for | |
775 | knowing which registers should not be saved even if used. | |
776 | Return true if we need to save REGNO. */ | |
777 | ||
48ed72a4 PB |
778 | static bool |
779 | m68k_save_reg (unsigned int regno, bool interrupt_handler) | |
2cff4a6e | 780 | { |
4ab870f5 | 781 | if (flag_pic && regno == PIC_REG) |
b86ba8a3 | 782 | { |
afcb440c RS |
783 | /* A function that receives a nonlocal goto must save all call-saved |
784 | registers. */ | |
785 | if (current_function_has_nonlocal_label) | |
786 | return true; | |
b86ba8a3 AT |
787 | if (current_function_uses_pic_offset_table) |
788 | return true; | |
6357eb0d RS |
789 | /* Reload may introduce constant pool references into a function |
790 | that thitherto didn't need a PIC register. Note that the test | |
791 | above will not catch that case because we will only set | |
792 | current_function_uses_pic_offset_table when emitting | |
793 | the address reloads. */ | |
794 | if (current_function_uses_const_pool) | |
795 | return true; | |
b86ba8a3 | 796 | } |
2cff4a6e AS |
797 | |
798 | if (current_function_calls_eh_return) | |
799 | { | |
800 | unsigned int i; | |
801 | for (i = 0; ; i++) | |
802 | { | |
803 | unsigned int test = EH_RETURN_DATA_REGNO (i); | |
804 | if (test == INVALID_REGNUM) | |
805 | break; | |
806 | if (test == regno) | |
48ed72a4 | 807 | return true; |
2cff4a6e AS |
808 | } |
809 | } | |
810 | ||
48ed72a4 PB |
811 | /* Fixed regs we never touch. */ |
812 | if (fixed_regs[regno]) | |
813 | return false; | |
814 | ||
815 | /* The frame pointer (if it is such) is handled specially. */ | |
816 | if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) | |
817 | return false; | |
818 | ||
819 | /* Interrupt handlers must also save call_used_regs | |
820 | if they are live or when calling nested functions. */ | |
821 | if (interrupt_handler) | |
a0a7fbc9 | 822 | { |
6fb5fa3c | 823 | if (df_regs_ever_live_p (regno)) |
a0a7fbc9 | 824 | return true; |
48ed72a4 | 825 | |
a0a7fbc9 AS |
826 | if (!current_function_is_leaf && call_used_regs[regno]) |
827 | return true; | |
828 | } | |
48ed72a4 PB |
829 | |
830 | /* Never need to save registers that aren't touched. */ | |
6fb5fa3c | 831 | if (!df_regs_ever_live_p (regno)) |
48ed72a4 PB |
832 | return false; |
833 | ||
b2e08ed4 | 834 | /* Otherwise save everything that isn't call-clobbered. */ |
48ed72a4 | 835 | return !call_used_regs[regno]; |
2cff4a6e AS |
836 | } |
837 | ||
a40ed0f3 KH |
838 | /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents |
839 | the lowest memory address. COUNT is the number of registers to be | |
840 | moved, with register REGNO + I being moved if bit I of MASK is set. | |
841 | STORE_P specifies the direction of the move and ADJUST_STACK_P says | |
842 | whether or not this is pre-decrement (if STORE_P) or post-increment | |
843 | (if !STORE_P) operation. */ | |
844 | ||
845 | static rtx | |
846 | m68k_emit_movem (rtx base, HOST_WIDE_INT offset, | |
847 | unsigned int count, unsigned int regno, | |
848 | unsigned int mask, bool store_p, bool adjust_stack_p) | |
849 | { | |
850 | int i; | |
851 | rtx body, addr, src, operands[2]; | |
852 | enum machine_mode mode; | |
853 | ||
854 | body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); | |
855 | mode = reg_raw_mode[regno]; | |
856 | i = 0; | |
857 | ||
858 | if (adjust_stack_p) | |
859 | { | |
860 | src = plus_constant (base, (count | |
861 | * GET_MODE_SIZE (mode) | |
862 | * (HOST_WIDE_INT) (store_p ? -1 : 1))); | |
863 | XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src); | |
864 | } | |
865 | ||
866 | for (; mask != 0; mask >>= 1, regno++) | |
867 | if (mask & 1) | |
868 | { | |
869 | addr = plus_constant (base, offset); | |
870 | operands[!store_p] = gen_frame_mem (mode, addr); | |
871 | operands[store_p] = gen_rtx_REG (mode, regno); | |
872 | XVECEXP (body, 0, i++) | |
873 | = gen_rtx_SET (VOIDmode, operands[0], operands[1]); | |
874 | offset += GET_MODE_SIZE (mode); | |
875 | } | |
876 | gcc_assert (i == XVECLEN (body, 0)); | |
877 | ||
878 | return emit_insn (body); | |
879 | } | |
880 | ||
881 | /* Make INSN a frame-related instruction. */ | |
79e68feb | 882 | |
08c148a8 | 883 | static void |
a40ed0f3 KH |
884 | m68k_set_frame_related (rtx insn) |
885 | { | |
886 | rtx body; | |
887 | int i; | |
888 | ||
889 | RTX_FRAME_RELATED_P (insn) = 1; | |
890 | body = PATTERN (insn); | |
891 | if (GET_CODE (body) == PARALLEL) | |
892 | for (i = 0; i < XVECLEN (body, 0); i++) | |
893 | RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; | |
894 | } | |
895 | ||
896 | /* Emit RTL for the "prologue" define_expand. */ | |
897 | ||
898 | void | |
899 | m68k_expand_prologue (void) | |
79e68feb | 900 | { |
860c4900 | 901 | HOST_WIDE_INT fsize_with_regs; |
a40ed0f3 | 902 | rtx limit, src, dest, insn; |
3d74bc09 | 903 | |
a40ed0f3 | 904 | m68k_compute_frame_layout (); |
3d74bc09 | 905 | |
a157febd GK |
906 | /* If the stack limit is a symbol, we can check it here, |
907 | before actually allocating the space. */ | |
908 | if (current_function_limit_stack | |
909 | && GET_CODE (stack_limit_rtx) == SYMBOL_REF) | |
a40ed0f3 KH |
910 | { |
911 | limit = plus_constant (stack_limit_rtx, current_frame.size + 4); | |
912 | if (!LEGITIMATE_CONSTANT_P (limit)) | |
913 | { | |
914 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); | |
915 | limit = gen_rtx_REG (Pmode, D0_REG); | |
916 | } | |
917 | emit_insn (gen_cmpsi (stack_pointer_rtx, limit)); | |
918 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
919 | cc0_rtx, const0_rtx), | |
920 | const1_rtx)); | |
921 | } | |
79e68feb | 922 | |
a89e3f21 | 923 | fsize_with_regs = current_frame.size; |
dcc21c4c PB |
924 | if (TARGET_COLDFIRE) |
925 | { | |
a40ed0f3 KH |
926 | /* ColdFire's move multiple instructions do not allow pre-decrement |
927 | addressing. Add the size of movem saves to the initial stack | |
928 | allocation instead. */ | |
929 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
930 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
931 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
932 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 933 | } |
860c4900 | 934 | |
79e68feb RS |
935 | if (frame_pointer_needed) |
936 | { | |
a40ed0f3 | 937 | if (fsize_with_regs == 0 && TUNE_68040) |
79e68feb | 938 | { |
a40ed0f3 KH |
939 | /* On the 68040, two separate moves are faster than link.w 0. */ |
940 | dest = gen_frame_mem (Pmode, | |
941 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
942 | m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); | |
943 | m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, | |
944 | stack_pointer_rtx)); | |
79e68feb | 945 | } |
a40ed0f3 KH |
946 | else if (fsize_with_regs < 0x8000 || TARGET_68020) |
947 | m68k_set_frame_related | |
948 | (emit_insn (gen_link (frame_pointer_rtx, | |
949 | GEN_INT (-4 - fsize_with_regs)))); | |
d9e88af0 | 950 | else |
a40ed0f3 KH |
951 | { |
952 | m68k_set_frame_related | |
953 | (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); | |
954 | m68k_set_frame_related | |
955 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
956 | stack_pointer_rtx, | |
957 | GEN_INT (-fsize_with_regs)))); | |
958 | } | |
d9e88af0 | 959 | } |
a40ed0f3 KH |
960 | else if (fsize_with_regs != 0) |
961 | m68k_set_frame_related | |
962 | (emit_insn (gen_addsi3 (stack_pointer_rtx, | |
963 | stack_pointer_rtx, | |
964 | GEN_INT (-fsize_with_regs)))); | |
860c4900 | 965 | |
57047680 | 966 | if (current_frame.fpu_mask) |
79e68feb | 967 | { |
a40ed0f3 | 968 | gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); |
dcc21c4c | 969 | if (TARGET_68881) |
a40ed0f3 KH |
970 | m68k_set_frame_related |
971 | (m68k_emit_movem (stack_pointer_rtx, | |
972 | current_frame.fpu_no * -GET_MODE_SIZE (XFmode), | |
973 | current_frame.fpu_no, FP0_REG, | |
974 | current_frame.fpu_mask, true, true)); | |
dcc21c4c PB |
975 | else |
976 | { | |
977 | int offset; | |
978 | ||
a40ed0f3 KH |
979 | /* If we're using moveml to save the integer registers, |
980 | the stack pointer will point to the bottom of the moveml | |
981 | save area. Find the stack offset of the first FP register. */ | |
982 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
983 | offset = 0; |
984 | else | |
a40ed0f3 KH |
985 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
986 | m68k_set_frame_related | |
987 | (m68k_emit_movem (stack_pointer_rtx, offset, | |
988 | current_frame.fpu_no, FP0_REG, | |
989 | current_frame.fpu_mask, true, false)); | |
f277471f | 990 | } |
79e68feb | 991 | } |
99df2465 | 992 | |
01bbf777 | 993 | /* If the stack limit is not a symbol, check it here. |
a157febd GK |
994 | This has the disadvantage that it may be too late... */ |
995 | if (current_function_limit_stack) | |
996 | { | |
997 | if (REG_P (stack_limit_rtx)) | |
a40ed0f3 KH |
998 | { |
999 | emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx)); | |
1000 | emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode, | |
1001 | cc0_rtx, const0_rtx), | |
1002 | const1_rtx)); | |
1003 | } | |
a157febd | 1004 | else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) |
d4ee4d25 | 1005 | warning (0, "stack limit expression is not supported"); |
a157febd | 1006 | } |
01bbf777 | 1007 | |
a40ed0f3 | 1008 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
79e68feb | 1009 | { |
a40ed0f3 | 1010 | /* Store each register separately in the same order moveml does. */ |
79e68feb RS |
1011 | int i; |
1012 | ||
a40ed0f3 KH |
1013 | for (i = 16; i-- > 0; ) |
1014 | if (current_frame.reg_mask & (1 << i)) | |
078e983e | 1015 | { |
a40ed0f3 KH |
1016 | src = gen_rtx_REG (SImode, D0_REG + i); |
1017 | dest = gen_frame_mem (SImode, | |
1018 | gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); | |
1019 | m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); | |
078e983e | 1020 | } |
79e68feb | 1021 | } |
a40ed0f3 | 1022 | else |
79e68feb | 1023 | { |
9425fb04 | 1024 | if (TARGET_COLDFIRE) |
a40ed0f3 KH |
1025 | /* The required register save space has already been allocated. |
1026 | The first register should be stored at (%sp). */ | |
1027 | m68k_set_frame_related | |
1028 | (m68k_emit_movem (stack_pointer_rtx, 0, | |
1029 | current_frame.reg_no, D0_REG, | |
1030 | current_frame.reg_mask, true, false)); | |
afaff477 | 1031 | else |
a40ed0f3 KH |
1032 | m68k_set_frame_related |
1033 | (m68k_emit_movem (stack_pointer_rtx, | |
1034 | current_frame.reg_no * -GET_MODE_SIZE (SImode), | |
1035 | current_frame.reg_no, D0_REG, | |
1036 | current_frame.reg_mask, true, true)); | |
79e68feb | 1037 | } |
a40ed0f3 KH |
1038 | |
1039 | if (flag_pic | |
1040 | && !TARGET_SEP_DATA | |
4f44ecc0 | 1041 | && current_function_uses_pic_offset_table) |
6fb5fa3c | 1042 | insn = emit_insn (gen_load_got (pic_offset_table_rtx)); |
79e68feb RS |
1043 | } |
1044 | \f | |
413ac1b2 RS |
1045 | /* Return true if a simple (return) instruction is sufficient for this |
1046 | instruction (i.e. if no epilogue is needed). */ | |
79e68feb | 1047 | |
3d74bc09 | 1048 | bool |
a2bda628 | 1049 | m68k_use_return_insn (void) |
79e68feb | 1050 | { |
79e68feb | 1051 | if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) |
3d74bc09 | 1052 | return false; |
125ed86f | 1053 | |
a0a7fbc9 | 1054 | m68k_compute_frame_layout (); |
413ac1b2 | 1055 | return current_frame.offset == 0; |
79e68feb RS |
1056 | } |
1057 | ||
f7e70894 RS |
1058 | /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; |
1059 | SIBCALL_P says which. | |
79e68feb RS |
1060 | |
1061 | The function epilogue should not depend on the current stack pointer! | |
1062 | It should use the frame pointer only, if there is a frame pointer. | |
1063 | This is mandatory because of alloca; we also take advantage of it to | |
1064 | omit stack adjustments before returning. */ | |
1065 | ||
a40ed0f3 | 1066 | void |
f7e70894 | 1067 | m68k_expand_epilogue (bool sibcall_p) |
08c148a8 | 1068 | { |
3d74bc09 | 1069 | HOST_WIDE_INT fsize, fsize_with_regs; |
a40ed0f3 | 1070 | bool big, restore_from_sp; |
3d74bc09 | 1071 | |
a0a7fbc9 | 1072 | m68k_compute_frame_layout (); |
3d74bc09 | 1073 | |
3d74bc09 | 1074 | fsize = current_frame.size; |
a40ed0f3 KH |
1075 | big = false; |
1076 | restore_from_sp = false; | |
3d74bc09 | 1077 | |
a40ed0f3 | 1078 | /* FIXME : current_function_is_leaf below is too strong. |
c67ddce5 | 1079 | What we really need to know there is if there could be pending |
7a1929e1 | 1080 | stack adjustment needed at that point. */ |
a40ed0f3 KH |
1081 | restore_from_sp = (!frame_pointer_needed |
1082 | || (!current_function_calls_alloca | |
1083 | && current_function_is_leaf)); | |
860c4900 BI |
1084 | |
1085 | /* fsize_with_regs is the size we need to adjust the sp when | |
97c55091 | 1086 | popping the frame. */ |
860c4900 | 1087 | fsize_with_regs = fsize; |
dcc21c4c PB |
1088 | if (TARGET_COLDFIRE && restore_from_sp) |
1089 | { | |
a40ed0f3 KH |
1090 | /* ColdFire's move multiple instructions do not allow post-increment |
1091 | addressing. Add the size of movem loads to the final deallocation | |
1092 | instead. */ | |
1093 | if (current_frame.reg_no >= MIN_MOVEM_REGS) | |
1094 | fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); | |
1095 | if (current_frame.fpu_no >= MIN_FMOVEM_REGS) | |
1096 | fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); | |
dcc21c4c | 1097 | } |
860c4900 | 1098 | |
3d74bc09 | 1099 | if (current_frame.offset + fsize >= 0x8000 |
a40ed0f3 | 1100 | && !restore_from_sp |
3d74bc09 | 1101 | && (current_frame.reg_mask || current_frame.fpu_mask)) |
79e68feb | 1102 | { |
a40ed0f3 KH |
1103 | if (TARGET_COLDFIRE |
1104 | && (current_frame.reg_no >= MIN_MOVEM_REGS | |
1105 | || current_frame.fpu_no >= MIN_FMOVEM_REGS)) | |
1106 | { | |
1107 | /* ColdFire's move multiple instructions do not support the | |
1108 | (d8,Ax,Xi) addressing mode, so we're as well using a normal | |
1109 | stack-based restore. */ | |
1110 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), | |
1111 | GEN_INT (-(current_frame.offset + fsize))); | |
1112 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1113 | gen_rtx_REG (Pmode, A1_REG), | |
1114 | frame_pointer_rtx)); | |
1115 | restore_from_sp = true; | |
1116 | } | |
1117 | else | |
1118 | { | |
1119 | emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); | |
1120 | fsize = 0; | |
1121 | big = true; | |
1122 | } | |
79e68feb | 1123 | } |
79e68feb | 1124 | |
a40ed0f3 KH |
1125 | if (current_frame.reg_no < MIN_MOVEM_REGS) |
1126 | { | |
1127 | /* Restore each register separately in the same order moveml does. */ | |
79e68feb | 1128 | int i; |
a40ed0f3 | 1129 | HOST_WIDE_INT offset; |
79e68feb | 1130 | |
a40ed0f3 | 1131 | offset = current_frame.offset + fsize; |
3d74bc09 BI |
1132 | for (i = 0; i < 16; i++) |
1133 | if (current_frame.reg_mask & (1 << i)) | |
79e68feb | 1134 | { |
a40ed0f3 KH |
1135 | rtx addr; |
1136 | ||
1137 | if (big) | |
79e68feb | 1138 | { |
a40ed0f3 KH |
1139 | /* Generate the address -OFFSET(%fp,%a1.l). */ |
1140 | addr = gen_rtx_REG (Pmode, A1_REG); | |
1141 | addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); | |
1142 | addr = plus_constant (addr, -offset); | |
79e68feb | 1143 | } |
a40ed0f3 KH |
1144 | else if (restore_from_sp) |
1145 | addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); | |
1146 | else | |
1147 | addr = plus_constant (frame_pointer_rtx, -offset); | |
1148 | emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), | |
1149 | gen_frame_mem (SImode, addr)); | |
1150 | offset -= GET_MODE_SIZE (SImode); | |
1151 | } | |
79e68feb | 1152 | } |
3d74bc09 | 1153 | else if (current_frame.reg_mask) |
79e68feb | 1154 | { |
a40ed0f3 KH |
1155 | if (big) |
1156 | m68k_emit_movem (gen_rtx_PLUS (Pmode, | |
1157 | gen_rtx_REG (Pmode, A1_REG), | |
1158 | frame_pointer_rtx), | |
1159 | -(current_frame.offset + fsize), | |
1160 | current_frame.reg_no, D0_REG, | |
1161 | current_frame.reg_mask, false, false); | |
1162 | else if (restore_from_sp) | |
1163 | m68k_emit_movem (stack_pointer_rtx, 0, | |
1164 | current_frame.reg_no, D0_REG, | |
1165 | current_frame.reg_mask, false, | |
1166 | !TARGET_COLDFIRE); | |
1167 | else | |
1168 | m68k_emit_movem (frame_pointer_rtx, | |
1169 | -(current_frame.offset + fsize), | |
1170 | current_frame.reg_no, D0_REG, | |
1171 | current_frame.reg_mask, false, false); | |
79e68feb | 1172 | } |
a40ed0f3 KH |
1173 | |
1174 | if (current_frame.fpu_no > 0) | |
79e68feb RS |
1175 | { |
1176 | if (big) | |
a40ed0f3 KH |
1177 | m68k_emit_movem (gen_rtx_PLUS (Pmode, |
1178 | gen_rtx_REG (Pmode, A1_REG), | |
1179 | frame_pointer_rtx), | |
1180 | -(current_frame.foffset + fsize), | |
1181 | current_frame.fpu_no, FP0_REG, | |
1182 | current_frame.fpu_mask, false, false); | |
6910dd70 | 1183 | else if (restore_from_sp) |
79e68feb | 1184 | { |
dcc21c4c PB |
1185 | if (TARGET_COLDFIRE) |
1186 | { | |
1187 | int offset; | |
1188 | ||
a40ed0f3 KH |
1189 | /* If we used moveml to restore the integer registers, the |
1190 | stack pointer will still point to the bottom of the moveml | |
1191 | save area. Find the stack offset of the first FP | |
1192 | register. */ | |
1193 | if (current_frame.reg_no < MIN_MOVEM_REGS) | |
dcc21c4c PB |
1194 | offset = 0; |
1195 | else | |
a40ed0f3 KH |
1196 | offset = current_frame.reg_no * GET_MODE_SIZE (SImode); |
1197 | m68k_emit_movem (stack_pointer_rtx, offset, | |
1198 | current_frame.fpu_no, FP0_REG, | |
1199 | current_frame.fpu_mask, false, false); | |
dcc21c4c | 1200 | } |
884b74f0 | 1201 | else |
a40ed0f3 KH |
1202 | m68k_emit_movem (stack_pointer_rtx, 0, |
1203 | current_frame.fpu_no, FP0_REG, | |
1204 | current_frame.fpu_mask, false, true); | |
79e68feb RS |
1205 | } |
1206 | else | |
a40ed0f3 KH |
1207 | m68k_emit_movem (frame_pointer_rtx, |
1208 | -(current_frame.foffset + fsize), | |
1209 | current_frame.fpu_no, FP0_REG, | |
1210 | current_frame.fpu_mask, false, false); | |
79e68feb | 1211 | } |
a40ed0f3 | 1212 | |
79e68feb | 1213 | if (frame_pointer_needed) |
a40ed0f3 | 1214 | emit_insn (gen_unlink (frame_pointer_rtx)); |
860c4900 | 1215 | else if (fsize_with_regs) |
a40ed0f3 KH |
1216 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1217 | stack_pointer_rtx, | |
1218 | GEN_INT (fsize_with_regs))); | |
1219 | ||
2cff4a6e | 1220 | if (current_function_calls_eh_return) |
a40ed0f3 KH |
1221 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
1222 | stack_pointer_rtx, | |
1223 | EH_RETURN_STACKADJ_RTX)); | |
1224 | ||
f7e70894 | 1225 | if (!sibcall_p) |
49570723 | 1226 | emit_jump_insn (gen_rtx_RETURN (VOIDmode)); |
79e68feb RS |
1227 | } |
1228 | \f | |
8a4a2253 | 1229 | /* Return true if X is a valid comparison operator for the dbcc |
64a184e9 RS |
1230 | instruction. |
1231 | ||
1232 | Note it rejects floating point comparison operators. | |
1233 | (In the future we could use Fdbcc). | |
1234 | ||
1235 | It also rejects some comparisons when CC_NO_OVERFLOW is set. */ | |
1236 | ||
1237 | int | |
41b6a5e2 | 1238 | valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
64a184e9 | 1239 | { |
64a184e9 RS |
1240 | switch (GET_CODE (x)) |
1241 | { | |
64a184e9 RS |
1242 | case EQ: case NE: case GTU: case LTU: |
1243 | case GEU: case LEU: | |
1244 | return 1; | |
1245 | ||
1246 | /* Reject some when CC_NO_OVERFLOW is set. This may be over | |
1247 | conservative */ | |
1248 | case GT: case LT: case GE: case LE: | |
1249 | return ! (cc_prev_status.flags & CC_NO_OVERFLOW); | |
1250 | default: | |
1251 | return 0; | |
1252 | } | |
1253 | } | |
1254 | ||
a0ab749a | 1255 | /* Return nonzero if flags are currently in the 68881 flag register. */ |
6a0f85e3 | 1256 | int |
8a4a2253 | 1257 | flags_in_68881 (void) |
6a0f85e3 TG |
1258 | { |
1259 | /* We could add support for these in the future */ | |
1260 | return cc_status.flags & CC_IN_68881; | |
1261 | } | |
1262 | ||
fa157b28 | 1263 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ |
f7e70894 RS |
1264 | |
1265 | static bool | |
fa157b28 | 1266 | m68k_ok_for_sibcall_p (tree decl, tree exp) |
f7e70894 | 1267 | { |
fa157b28 NS |
1268 | enum m68k_function_kind kind; |
1269 | ||
1270 | /* We cannot use sibcalls for nested functions because we use the | |
1271 | static chain register for indirect calls. */ | |
1272 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1273 | return false; | |
1274 | ||
1275 | kind = m68k_get_function_kind (current_function_decl); | |
1276 | if (kind == m68k_fk_normal_function) | |
1277 | /* We can always sibcall from a normal function, because it's | |
1278 | undefined if it is calling an interrupt function. */ | |
1279 | return true; | |
1280 | ||
1281 | /* Otherwise we can only sibcall if the function kind is known to be | |
1282 | the same. */ | |
1283 | if (decl && m68k_get_function_kind (decl) == kind) | |
1284 | return true; | |
1285 | ||
1286 | return false; | |
f7e70894 RS |
1287 | } |
1288 | ||
29ca003a RS |
1289 | /* Convert X to a legitimate function call memory reference and return the |
1290 | result. */ | |
a2ef3db7 | 1291 | |
29ca003a RS |
1292 | rtx |
1293 | m68k_legitimize_call_address (rtx x) | |
1294 | { | |
1295 | gcc_assert (MEM_P (x)); | |
1296 | if (call_operand (XEXP (x, 0), VOIDmode)) | |
1297 | return x; | |
1298 | return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); | |
a2ef3db7 BI |
1299 | } |
1300 | ||
f7e70894 RS |
1301 | /* Likewise for sibling calls. */ |
1302 | ||
1303 | rtx | |
1304 | m68k_legitimize_sibcall_address (rtx x) | |
1305 | { | |
1306 | gcc_assert (MEM_P (x)); | |
1307 | if (sibcall_operand (XEXP (x, 0), VOIDmode)) | |
1308 | return x; | |
1309 | ||
1310 | emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); | |
1311 | return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); | |
1312 | } | |
1313 | ||
64a184e9 RS |
1314 | /* Output a dbCC; jCC sequence. Note we do not handle the |
1315 | floating point version of this sequence (Fdbcc). We also | |
1316 | do not handle alternative conditions when CC_NO_OVERFLOW is | |
6a0f85e3 TG |
1317 | set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will |
1318 | kick those out before we get here. */ | |
64a184e9 | 1319 | |
1d8eaa6b | 1320 | void |
8a4a2253 | 1321 | output_dbcc_and_branch (rtx *operands) |
64a184e9 | 1322 | { |
64a184e9 RS |
1323 | switch (GET_CODE (operands[3])) |
1324 | { | |
1325 | case EQ: | |
a0a7fbc9 AS |
1326 | output_asm_insn (MOTOROLA |
1327 | ? "dbeq %0,%l1\n\tjbeq %l2" | |
1328 | : "dbeq %0,%l1\n\tjeq %l2", | |
e6d98cb0 BI |
1329 | operands); |
1330 | break; | |
64a184e9 RS |
1331 | |
1332 | case NE: | |
a0a7fbc9 AS |
1333 | output_asm_insn (MOTOROLA |
1334 | ? "dbne %0,%l1\n\tjbne %l2" | |
1335 | : "dbne %0,%l1\n\tjne %l2", | |
e6d98cb0 BI |
1336 | operands); |
1337 | break; | |
64a184e9 RS |
1338 | |
1339 | case GT: | |
a0a7fbc9 AS |
1340 | output_asm_insn (MOTOROLA |
1341 | ? "dbgt %0,%l1\n\tjbgt %l2" | |
1342 | : "dbgt %0,%l1\n\tjgt %l2", | |
e6d98cb0 BI |
1343 | operands); |
1344 | break; | |
64a184e9 RS |
1345 | |
1346 | case GTU: | |
a0a7fbc9 AS |
1347 | output_asm_insn (MOTOROLA |
1348 | ? "dbhi %0,%l1\n\tjbhi %l2" | |
1349 | : "dbhi %0,%l1\n\tjhi %l2", | |
e6d98cb0 BI |
1350 | operands); |
1351 | break; | |
64a184e9 RS |
1352 | |
1353 | case LT: | |
a0a7fbc9 AS |
1354 | output_asm_insn (MOTOROLA |
1355 | ? "dblt %0,%l1\n\tjblt %l2" | |
1356 | : "dblt %0,%l1\n\tjlt %l2", | |
e6d98cb0 BI |
1357 | operands); |
1358 | break; | |
64a184e9 RS |
1359 | |
1360 | case LTU: | |
a0a7fbc9 AS |
1361 | output_asm_insn (MOTOROLA |
1362 | ? "dbcs %0,%l1\n\tjbcs %l2" | |
1363 | : "dbcs %0,%l1\n\tjcs %l2", | |
e6d98cb0 BI |
1364 | operands); |
1365 | break; | |
64a184e9 RS |
1366 | |
1367 | case GE: | |
a0a7fbc9 AS |
1368 | output_asm_insn (MOTOROLA |
1369 | ? "dbge %0,%l1\n\tjbge %l2" | |
1370 | : "dbge %0,%l1\n\tjge %l2", | |
e6d98cb0 BI |
1371 | operands); |
1372 | break; | |
64a184e9 RS |
1373 | |
1374 | case GEU: | |
a0a7fbc9 AS |
1375 | output_asm_insn (MOTOROLA |
1376 | ? "dbcc %0,%l1\n\tjbcc %l2" | |
1377 | : "dbcc %0,%l1\n\tjcc %l2", | |
e6d98cb0 BI |
1378 | operands); |
1379 | break; | |
64a184e9 RS |
1380 | |
1381 | case LE: | |
a0a7fbc9 AS |
1382 | output_asm_insn (MOTOROLA |
1383 | ? "dble %0,%l1\n\tjble %l2" | |
1384 | : "dble %0,%l1\n\tjle %l2", | |
e6d98cb0 BI |
1385 | operands); |
1386 | break; | |
64a184e9 RS |
1387 | |
1388 | case LEU: | |
a0a7fbc9 AS |
1389 | output_asm_insn (MOTOROLA |
1390 | ? "dbls %0,%l1\n\tjbls %l2" | |
1391 | : "dbls %0,%l1\n\tjls %l2", | |
e6d98cb0 BI |
1392 | operands); |
1393 | break; | |
64a184e9 RS |
1394 | |
1395 | default: | |
4761e388 | 1396 | gcc_unreachable (); |
64a184e9 RS |
1397 | } |
1398 | ||
1399 | /* If the decrement is to be done in SImode, then we have | |
7a1929e1 | 1400 | to compensate for the fact that dbcc decrements in HImode. */ |
64a184e9 RS |
1401 | switch (GET_MODE (operands[0])) |
1402 | { | |
1403 | case SImode: | |
a0a7fbc9 AS |
1404 | output_asm_insn (MOTOROLA |
1405 | ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" | |
1406 | : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", | |
e6d98cb0 | 1407 | operands); |
64a184e9 RS |
1408 | break; |
1409 | ||
1410 | case HImode: | |
1411 | break; | |
1412 | ||
1413 | default: | |
4761e388 | 1414 | gcc_unreachable (); |
64a184e9 RS |
1415 | } |
1416 | } | |
1417 | ||
5505f548 | 1418 | const char * |
4761e388 | 1419 | output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) |
c59c3b1c RK |
1420 | { |
1421 | rtx loperands[7]; | |
d9832fd2 | 1422 | enum rtx_code op_code = GET_CODE (op); |
c59c3b1c | 1423 | |
f710504c | 1424 | /* This does not produce a useful cc. */ |
906a2d3c RK |
1425 | CC_STATUS_INIT; |
1426 | ||
d9832fd2 RK |
1427 | /* The m68k cmp.l instruction requires operand1 to be a reg as used |
1428 | below. Swap the operands and change the op if these requirements | |
1429 | are not fulfilled. */ | |
1430 | if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) | |
1431 | { | |
1432 | rtx tmp = operand1; | |
1433 | ||
1434 | operand1 = operand2; | |
1435 | operand2 = tmp; | |
1436 | op_code = swap_condition (op_code); | |
1437 | } | |
c59c3b1c RK |
1438 | loperands[0] = operand1; |
1439 | if (GET_CODE (operand1) == REG) | |
1d8eaa6b | 1440 | loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); |
c59c3b1c | 1441 | else |
b72f00af | 1442 | loperands[1] = adjust_address (operand1, SImode, 4); |
c59c3b1c RK |
1443 | if (operand2 != const0_rtx) |
1444 | { | |
1445 | loperands[2] = operand2; | |
1446 | if (GET_CODE (operand2) == REG) | |
1d8eaa6b | 1447 | loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); |
c59c3b1c | 1448 | else |
b72f00af | 1449 | loperands[3] = adjust_address (operand2, SImode, 4); |
c59c3b1c | 1450 | } |
428511bb | 1451 | loperands[4] = gen_label_rtx (); |
c59c3b1c | 1452 | if (operand2 != const0_rtx) |
4a8c52e0 | 1453 | { |
a0a7fbc9 AS |
1454 | output_asm_insn (MOTOROLA |
1455 | ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" | |
1456 | : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", | |
1457 | loperands); | |
4a8c52e0 | 1458 | } |
392582fa | 1459 | else |
4a8c52e0 | 1460 | { |
9425fb04 | 1461 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) |
4a8c52e0 AS |
1462 | output_asm_insn ("tst%.l %0", loperands); |
1463 | else | |
a0a7fbc9 | 1464 | output_asm_insn ("cmp%.w #0,%0", loperands); |
4a8c52e0 | 1465 | |
e6d98cb0 | 1466 | output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands); |
4a8c52e0 | 1467 | |
9425fb04 | 1468 | if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) |
4a8c52e0 AS |
1469 | output_asm_insn ("tst%.l %1", loperands); |
1470 | else | |
3b4b85c9 | 1471 | output_asm_insn ("cmp%.w #0,%1", loperands); |
4a8c52e0 AS |
1472 | } |
1473 | ||
c59c3b1c | 1474 | loperands[5] = dest; |
3b4b85c9 | 1475 | |
d9832fd2 | 1476 | switch (op_code) |
c59c3b1c RK |
1477 | { |
1478 | case EQ: | |
4977bab6 | 1479 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1480 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1481 | output_asm_insn ("seq %5", loperands); |
1482 | break; | |
1483 | ||
1484 | case NE: | |
4977bab6 | 1485 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1486 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1487 | output_asm_insn ("sne %5", loperands); |
1488 | break; | |
1489 | ||
1490 | case GT: | |
428511bb | 1491 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1492 | output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6", |
e6d98cb0 | 1493 | loperands); |
4977bab6 | 1494 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1495 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1496 | output_asm_insn ("sgt %5", loperands); |
4977bab6 | 1497 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1498 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1499 | break; |
1500 | ||
1501 | case GTU: | |
4977bab6 | 1502 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1503 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1504 | output_asm_insn ("shi %5", loperands); |
1505 | break; | |
1506 | ||
1507 | case LT: | |
428511bb | 1508 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1509 | output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6", |
e6d98cb0 | 1510 | loperands); |
4977bab6 | 1511 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1512 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1513 | output_asm_insn ("slt %5", loperands); |
4977bab6 | 1514 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1515 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1516 | break; |
1517 | ||
1518 | case LTU: | |
4977bab6 | 1519 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1520 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1521 | output_asm_insn ("scs %5", loperands); |
1522 | break; | |
1523 | ||
1524 | case GE: | |
428511bb | 1525 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 AS |
1526 | output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6", |
1527 | loperands); | |
4977bab6 | 1528 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1529 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1530 | output_asm_insn ("sge %5", loperands); |
4977bab6 | 1531 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1532 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1533 | break; |
1534 | ||
1535 | case GEU: | |
4977bab6 | 1536 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1537 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1538 | output_asm_insn ("scc %5", loperands); |
1539 | break; | |
1540 | ||
1541 | case LE: | |
428511bb | 1542 | loperands[6] = gen_label_rtx (); |
a0a7fbc9 | 1543 | output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6", |
e6d98cb0 | 1544 | loperands); |
4977bab6 | 1545 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1546 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c | 1547 | output_asm_insn ("sle %5", loperands); |
4977bab6 | 1548 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1549 | CODE_LABEL_NUMBER (loperands[6])); |
c59c3b1c RK |
1550 | break; |
1551 | ||
1552 | case LEU: | |
4977bab6 | 1553 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
a0a7fbc9 | 1554 | CODE_LABEL_NUMBER (loperands[4])); |
c59c3b1c RK |
1555 | output_asm_insn ("sls %5", loperands); |
1556 | break; | |
1557 | ||
1558 | default: | |
4761e388 | 1559 | gcc_unreachable (); |
c59c3b1c RK |
1560 | } |
1561 | return ""; | |
1562 | } | |
1563 | ||
5505f548 | 1564 | const char * |
8a4a2253 | 1565 | output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos) |
79e68feb RS |
1566 | { |
1567 | operands[0] = countop; | |
1568 | operands[1] = dataop; | |
1569 | ||
1570 | if (GET_CODE (countop) == CONST_INT) | |
1571 | { | |
1572 | register int count = INTVAL (countop); | |
1573 | /* If COUNT is bigger than size of storage unit in use, | |
1574 | advance to the containing unit of same size. */ | |
1575 | if (count > signpos) | |
1576 | { | |
1577 | int offset = (count & ~signpos) / 8; | |
1578 | count = count & signpos; | |
b72f00af | 1579 | operands[1] = dataop = adjust_address (dataop, QImode, offset); |
79e68feb RS |
1580 | } |
1581 | if (count == signpos) | |
1582 | cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; | |
1583 | else | |
1584 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; | |
1585 | ||
1586 | /* These three statements used to use next_insns_test_no... | |
1587 | but it appears that this should do the same job. */ | |
1588 | if (count == 31 | |
1589 | && next_insn_tests_no_inequality (insn)) | |
1590 | return "tst%.l %1"; | |
1591 | if (count == 15 | |
1592 | && next_insn_tests_no_inequality (insn)) | |
1593 | return "tst%.w %1"; | |
1594 | if (count == 7 | |
1595 | && next_insn_tests_no_inequality (insn)) | |
1596 | return "tst%.b %1"; | |
5083912d PDM |
1597 | /* Try to use `movew to ccr' followed by the appropriate branch insn. |
1598 | On some m68k variants unfortunately that's slower than btst. | |
1599 | On 68000 and higher, that should also work for all HImode operands. */ | |
1600 | if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) | |
1601 | { | |
1602 | if (count == 3 && DATA_REG_P (operands[1]) | |
1603 | && next_insn_tests_no_inequality (insn)) | |
1604 | { | |
1605 | cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW; | |
1606 | return "move%.w %1,%%ccr"; | |
1607 | } | |
1608 | if (count == 2 && DATA_REG_P (operands[1]) | |
1609 | && next_insn_tests_no_inequality (insn)) | |
1610 | { | |
1611 | cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW; | |
1612 | return "move%.w %1,%%ccr"; | |
1613 | } | |
1614 | /* count == 1 followed by bvc/bvs and | |
1615 | count == 0 followed by bcc/bcs are also possible, but need | |
1616 | m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ | |
1617 | } | |
79e68feb RS |
1618 | |
1619 | cc_status.flags = CC_NOT_NEGATIVE; | |
1620 | } | |
1621 | return "btst %0,%1"; | |
1622 | } | |
79e68feb | 1623 | \f |
fc2241eb RS |
1624 | /* Return true if X is a legitimate base register. STRICT_P says |
1625 | whether we need strict checking. */ | |
1626 | ||
1627 | bool | |
1628 | m68k_legitimate_base_reg_p (rtx x, bool strict_p) | |
1629 | { | |
1630 | /* Allow SUBREG everywhere we allow REG. This results in better code. */ | |
1631 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1632 | x = SUBREG_REG (x); | |
1633 | ||
1634 | return (REG_P (x) | |
1635 | && (strict_p | |
1636 | ? REGNO_OK_FOR_BASE_P (REGNO (x)) | |
bf32249e | 1637 | : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1638 | } |
1639 | ||
1640 | /* Return true if X is a legitimate index register. STRICT_P says | |
1641 | whether we need strict checking. */ | |
1642 | ||
1643 | bool | |
1644 | m68k_legitimate_index_reg_p (rtx x, bool strict_p) | |
1645 | { | |
1646 | if (!strict_p && GET_CODE (x) == SUBREG) | |
1647 | x = SUBREG_REG (x); | |
1648 | ||
1649 | return (REG_P (x) | |
1650 | && (strict_p | |
1651 | ? REGNO_OK_FOR_INDEX_P (REGNO (x)) | |
bf32249e | 1652 | : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); |
fc2241eb RS |
1653 | } |
1654 | ||
1655 | /* Return true if X is a legitimate index expression for a (d8,An,Xn) or | |
1656 | (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of | |
1657 | ADDRESS if so. STRICT_P says whether we need strict checking. */ | |
1658 | ||
1659 | static bool | |
1660 | m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) | |
1661 | { | |
1662 | int scale; | |
1663 | ||
1664 | /* Check for a scale factor. */ | |
1665 | scale = 1; | |
1666 | if ((TARGET_68020 || TARGET_COLDFIRE) | |
1667 | && GET_CODE (x) == MULT | |
1668 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1669 | && (INTVAL (XEXP (x, 1)) == 2 | |
1670 | || INTVAL (XEXP (x, 1)) == 4 | |
1671 | || (INTVAL (XEXP (x, 1)) == 8 | |
1672 | && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) | |
1673 | { | |
1674 | scale = INTVAL (XEXP (x, 1)); | |
1675 | x = XEXP (x, 0); | |
1676 | } | |
1677 | ||
1678 | /* Check for a word extension. */ | |
1679 | if (!TARGET_COLDFIRE | |
1680 | && GET_CODE (x) == SIGN_EXTEND | |
1681 | && GET_MODE (XEXP (x, 0)) == HImode) | |
1682 | x = XEXP (x, 0); | |
1683 | ||
1684 | if (m68k_legitimate_index_reg_p (x, strict_p)) | |
1685 | { | |
1686 | address->scale = scale; | |
1687 | address->index = x; | |
1688 | return true; | |
1689 | } | |
1690 | ||
1691 | return false; | |
1692 | } | |
1693 | ||
7ffb5e78 RS |
1694 | /* Return true if X is an illegitimate symbolic constant. */ |
1695 | ||
1696 | bool | |
1697 | m68k_illegitimate_symbolic_constant_p (rtx x) | |
1698 | { | |
1699 | rtx base, offset; | |
1700 | ||
1701 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1702 | { | |
1703 | split_const (x, &base, &offset); | |
1704 | if (GET_CODE (base) == SYMBOL_REF | |
1705 | && !offset_within_block_p (base, INTVAL (offset))) | |
1706 | return true; | |
1707 | } | |
1708 | return false; | |
1709 | } | |
1710 | ||
fc2241eb RS |
1711 | /* Return true if X is a legitimate constant address that can reach |
1712 | bytes in the range [X, X + REACH). STRICT_P says whether we need | |
1713 | strict checking. */ | |
1714 | ||
1715 | static bool | |
1716 | m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) | |
1717 | { | |
1718 | rtx base, offset; | |
1719 | ||
1720 | if (!CONSTANT_ADDRESS_P (x)) | |
1721 | return false; | |
1722 | ||
1723 | if (flag_pic | |
1724 | && !(strict_p && TARGET_PCREL) | |
1725 | && symbolic_operand (x, VOIDmode)) | |
1726 | return false; | |
1727 | ||
1728 | if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) | |
1729 | { | |
1730 | split_const (x, &base, &offset); | |
1731 | if (GET_CODE (base) == SYMBOL_REF | |
1732 | && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) | |
1733 | return false; | |
1734 | } | |
1735 | ||
1736 | return true; | |
1737 | } | |
1738 | ||
1739 | /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced | |
1740 | labels will become jump tables. */ | |
1741 | ||
1742 | static bool | |
1743 | m68k_jump_table_ref_p (rtx x) | |
1744 | { | |
1745 | if (GET_CODE (x) != LABEL_REF) | |
1746 | return false; | |
1747 | ||
1748 | x = XEXP (x, 0); | |
1749 | if (!NEXT_INSN (x) && !PREV_INSN (x)) | |
1750 | return true; | |
1751 | ||
1752 | x = next_nonnote_insn (x); | |
1753 | return x && JUMP_TABLE_DATA_P (x); | |
1754 | } | |
1755 | ||
1756 | /* Return true if X is a legitimate address for values of mode MODE. | |
1757 | STRICT_P says whether strict checking is needed. If the address | |
1758 | is valid, describe its components in *ADDRESS. */ | |
1759 | ||
1760 | static bool | |
1761 | m68k_decompose_address (enum machine_mode mode, rtx x, | |
1762 | bool strict_p, struct m68k_address *address) | |
1763 | { | |
1764 | unsigned int reach; | |
1765 | ||
1766 | memset (address, 0, sizeof (*address)); | |
1767 | ||
1768 | if (mode == BLKmode) | |
1769 | reach = 1; | |
1770 | else | |
1771 | reach = GET_MODE_SIZE (mode); | |
1772 | ||
1773 | /* Check for (An) (mode 2). */ | |
1774 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1775 | { | |
1776 | address->base = x; | |
1777 | return true; | |
1778 | } | |
1779 | ||
1780 | /* Check for -(An) and (An)+ (modes 3 and 4). */ | |
1781 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) | |
1782 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1783 | { | |
1784 | address->code = GET_CODE (x); | |
1785 | address->base = XEXP (x, 0); | |
1786 | return true; | |
1787 | } | |
1788 | ||
1789 | /* Check for (d16,An) (mode 5). */ | |
1790 | if (GET_CODE (x) == PLUS | |
1791 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1792 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) | |
1793 | && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) | |
1794 | { | |
1795 | address->base = XEXP (x, 0); | |
1796 | address->offset = XEXP (x, 1); | |
1797 | return true; | |
1798 | } | |
1799 | ||
1800 | /* Check for GOT loads. These are (bd,An,Xn) addresses if | |
1801 | TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) | |
1802 | addresses. */ | |
1803 | if (flag_pic | |
1804 | && GET_CODE (x) == PLUS | |
1805 | && XEXP (x, 0) == pic_offset_table_rtx | |
1806 | && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF | |
1807 | || GET_CODE (XEXP (x, 1)) == LABEL_REF)) | |
1808 | { | |
1809 | address->base = XEXP (x, 0); | |
1810 | address->offset = XEXP (x, 1); | |
1811 | return true; | |
1812 | } | |
1813 | ||
1814 | /* The ColdFire FPU only accepts addressing modes 2-5. */ | |
1815 | if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1816 | return false; | |
1817 | ||
1818 | /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, | |
1819 | check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. | |
1820 | All these modes are variations of mode 7. */ | |
1821 | if (m68k_legitimate_constant_address_p (x, reach, strict_p)) | |
1822 | { | |
1823 | address->offset = x; | |
1824 | return true; | |
1825 | } | |
1826 | ||
1827 | /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for | |
1828 | tablejumps. | |
1829 | ||
1830 | ??? do_tablejump creates these addresses before placing the target | |
1831 | label, so we have to assume that unplaced labels are jump table | |
1832 | references. It seems unlikely that we would ever generate indexed | |
1833 | accesses to unplaced labels in other cases. */ | |
1834 | if (GET_CODE (x) == PLUS | |
1835 | && m68k_jump_table_ref_p (XEXP (x, 1)) | |
1836 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1837 | { | |
1838 | address->offset = XEXP (x, 1); | |
1839 | return true; | |
1840 | } | |
1841 | ||
1842 | /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or | |
1843 | (bd,An,Xn.SIZE*SCALE) addresses. */ | |
1844 | ||
1845 | if (TARGET_68020) | |
1846 | { | |
1847 | /* Check for a nonzero base displacement. */ | |
1848 | if (GET_CODE (x) == PLUS | |
1849 | && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) | |
1850 | { | |
1851 | address->offset = XEXP (x, 1); | |
1852 | x = XEXP (x, 0); | |
1853 | } | |
1854 | ||
1855 | /* Check for a suppressed index register. */ | |
1856 | if (m68k_legitimate_base_reg_p (x, strict_p)) | |
1857 | { | |
1858 | address->base = x; | |
1859 | return true; | |
1860 | } | |
1861 | ||
1862 | /* Check for a suppressed base register. Do not allow this case | |
1863 | for non-symbolic offsets as it effectively gives gcc freedom | |
1864 | to treat data registers as base registers, which can generate | |
1865 | worse code. */ | |
1866 | if (address->offset | |
1867 | && symbolic_operand (address->offset, VOIDmode) | |
1868 | && m68k_decompose_index (x, strict_p, address)) | |
1869 | return true; | |
1870 | } | |
1871 | else | |
1872 | { | |
1873 | /* Check for a nonzero base displacement. */ | |
1874 | if (GET_CODE (x) == PLUS | |
1875 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1876 | && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) | |
1877 | { | |
1878 | address->offset = XEXP (x, 1); | |
1879 | x = XEXP (x, 0); | |
1880 | } | |
1881 | } | |
1882 | ||
1883 | /* We now expect the sum of a base and an index. */ | |
1884 | if (GET_CODE (x) == PLUS) | |
1885 | { | |
1886 | if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) | |
1887 | && m68k_decompose_index (XEXP (x, 1), strict_p, address)) | |
1888 | { | |
1889 | address->base = XEXP (x, 0); | |
1890 | return true; | |
1891 | } | |
1892 | ||
1893 | if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) | |
1894 | && m68k_decompose_index (XEXP (x, 0), strict_p, address)) | |
1895 | { | |
1896 | address->base = XEXP (x, 1); | |
1897 | return true; | |
1898 | } | |
1899 | } | |
1900 | return false; | |
1901 | } | |
1902 | ||
1903 | /* Return true if X is a legitimate address for values of mode MODE. | |
1904 | STRICT_P says whether strict checking is needed. */ | |
1905 | ||
1906 | bool | |
1907 | m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
1908 | { | |
1909 | struct m68k_address address; | |
1910 | ||
1911 | return m68k_decompose_address (mode, x, strict_p, &address); | |
1912 | } | |
1913 | ||
1914 | /* Return true if X is a memory, describing its address in ADDRESS if so. | |
1915 | Apply strict checking if called during or after reload. */ | |
1916 | ||
1917 | static bool | |
1918 | m68k_legitimate_mem_p (rtx x, struct m68k_address *address) | |
1919 | { | |
1920 | return (MEM_P (x) | |
1921 | && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), | |
1922 | reload_in_progress || reload_completed, | |
1923 | address)); | |
1924 | } | |
1925 | ||
1926 | /* Return true if X matches the 'Q' constraint. It must be a memory | |
1927 | with a base address and no constant offset or index. */ | |
1928 | ||
1929 | bool | |
1930 | m68k_matches_q_p (rtx x) | |
1931 | { | |
1932 | struct m68k_address address; | |
1933 | ||
1934 | return (m68k_legitimate_mem_p (x, &address) | |
1935 | && address.code == UNKNOWN | |
1936 | && address.base | |
1937 | && !address.offset | |
1938 | && !address.index); | |
1939 | } | |
1940 | ||
1941 | /* Return true if X matches the 'U' constraint. It must be a base address | |
1942 | with a constant offset and no index. */ | |
1943 | ||
1944 | bool | |
1945 | m68k_matches_u_p (rtx x) | |
1946 | { | |
1947 | struct m68k_address address; | |
1948 | ||
1949 | return (m68k_legitimate_mem_p (x, &address) | |
1950 | && address.code == UNKNOWN | |
1951 | && address.base | |
1952 | && address.offset | |
1953 | && !address.index); | |
1954 | } | |
1955 | ||
79e68feb RS |
1956 | /* Legitimize PIC addresses. If the address is already |
1957 | position-independent, we return ORIG. Newly generated | |
1958 | position-independent addresses go to REG. If we need more | |
1959 | than one register, we lose. | |
1960 | ||
1961 | An address is legitimized by making an indirect reference | |
1962 | through the Global Offset Table with the name of the symbol | |
1963 | used as an offset. | |
1964 | ||
1965 | The assembler and linker are responsible for placing the | |
1966 | address of the symbol in the GOT. The function prologue | |
1967 | is responsible for initializing a5 to the starting address | |
1968 | of the GOT. | |
1969 | ||
1970 | The assembler is also responsible for translating a symbol name | |
1971 | into a constant displacement from the start of the GOT. | |
1972 | ||
1973 | A quick example may make things a little clearer: | |
1974 | ||
1975 | When not generating PIC code to store the value 12345 into _foo | |
1976 | we would generate the following code: | |
1977 | ||
1978 | movel #12345, _foo | |
1979 | ||
1980 | When generating PIC two transformations are made. First, the compiler | |
1981 | loads the address of foo into a register. So the first transformation makes: | |
1982 | ||
1983 | lea _foo, a0 | |
1984 | movel #12345, a0@ | |
1985 | ||
1986 | The code in movsi will intercept the lea instruction and call this | |
1987 | routine which will transform the instructions into: | |
1988 | ||
1989 | movel a5@(_foo:w), a0 | |
1990 | movel #12345, a0@ | |
1991 | ||
1992 | ||
1993 | That (in a nutshell) is how *all* symbol and label references are | |
1994 | handled. */ | |
1995 | ||
1996 | rtx | |
8a4a2253 BI |
1997 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
1998 | rtx reg) | |
79e68feb RS |
1999 | { |
2000 | rtx pic_ref = orig; | |
2001 | ||
2002 | /* First handle a simple SYMBOL_REF or LABEL_REF */ | |
2003 | if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
2004 | { | |
4761e388 | 2005 | gcc_assert (reg); |
79e68feb | 2006 | |
1d8eaa6b AS |
2007 | pic_ref = gen_rtx_MEM (Pmode, |
2008 | gen_rtx_PLUS (Pmode, | |
2009 | pic_offset_table_rtx, orig)); | |
79e68feb | 2010 | current_function_uses_pic_offset_table = 1; |
389fdba0 | 2011 | MEM_READONLY_P (pic_ref) = 1; |
79e68feb RS |
2012 | emit_move_insn (reg, pic_ref); |
2013 | return reg; | |
2014 | } | |
2015 | else if (GET_CODE (orig) == CONST) | |
2016 | { | |
1d8eaa6b | 2017 | rtx base; |
79e68feb | 2018 | |
b2e08ed4 | 2019 | /* Make sure this has not already been legitimized. */ |
79e68feb RS |
2020 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2021 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2022 | return orig; | |
2023 | ||
4761e388 | 2024 | gcc_assert (reg); |
79e68feb RS |
2025 | |
2026 | /* legitimize both operands of the PLUS */ | |
4761e388 NS |
2027 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
2028 | ||
2029 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2030 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2031 | base == reg ? 0 : reg); | |
79e68feb RS |
2032 | |
2033 | if (GET_CODE (orig) == CONST_INT) | |
ed8908e7 | 2034 | return plus_constant (base, INTVAL (orig)); |
1d8eaa6b | 2035 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
79e68feb RS |
2036 | /* Likewise, should we set special REG_NOTEs here? */ |
2037 | } | |
2038 | return pic_ref; | |
2039 | } | |
2040 | ||
2041 | \f | |
28bad6d1 | 2042 | typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD; |
0ce6f9fb | 2043 | |
a0a7fbc9 | 2044 | #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) |
0ce6f9fb | 2045 | |
bda2a571 RS |
2046 | /* Return the type of move that should be used for integer I. */ |
2047 | ||
5505f548 | 2048 | static CONST_METHOD |
bda2a571 | 2049 | const_method (HOST_WIDE_INT i) |
0ce6f9fb | 2050 | { |
0ce6f9fb RK |
2051 | unsigned u; |
2052 | ||
6910dd70 | 2053 | if (USE_MOVQ (i)) |
0ce6f9fb | 2054 | return MOVQ; |
24092242 | 2055 | |
c16eadc7 | 2056 | /* The ColdFire doesn't have byte or word operations. */ |
97c55091 | 2057 | /* FIXME: This may not be useful for the m68060 either. */ |
85dbf7e2 | 2058 | if (!TARGET_COLDFIRE) |
24092242 RK |
2059 | { |
2060 | /* if -256 < N < 256 but N is not in range for a moveq | |
7a1929e1 | 2061 | N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ |
24092242 RK |
2062 | if (USE_MOVQ (i ^ 0xff)) |
2063 | return NOTB; | |
2064 | /* Likewise, try with not.w */ | |
2065 | if (USE_MOVQ (i ^ 0xffff)) | |
2066 | return NOTW; | |
2067 | /* This is the only value where neg.w is useful */ | |
2068 | if (i == -65408) | |
2069 | return NEGW; | |
24092242 | 2070 | } |
28bad6d1 | 2071 | |
5e04daf3 PB |
2072 | /* Try also with swap. */ |
2073 | u = i; | |
2074 | if (USE_MOVQ ((u >> 16) | (u << 16))) | |
2075 | return SWAP; | |
2076 | ||
986e74d5 | 2077 | if (TARGET_ISAB) |
28bad6d1 | 2078 | { |
72edf146 | 2079 | /* Try using MVZ/MVS with an immediate value to load constants. */ |
28bad6d1 PB |
2080 | if (i >= 0 && i <= 65535) |
2081 | return MVZ; | |
2082 | if (i >= -32768 && i <= 32767) | |
2083 | return MVS; | |
2084 | } | |
2085 | ||
0ce6f9fb RK |
2086 | /* Otherwise, use move.l */ |
2087 | return MOVL; | |
2088 | } | |
2089 | ||
bda2a571 RS |
2090 | /* Return the cost of moving constant I into a data register. */ |
2091 | ||
3c50106f | 2092 | static int |
bda2a571 | 2093 | const_int_cost (HOST_WIDE_INT i) |
0ce6f9fb | 2094 | { |
bda2a571 | 2095 | switch (const_method (i)) |
0ce6f9fb | 2096 | { |
a0a7fbc9 AS |
2097 | case MOVQ: |
2098 | /* Constants between -128 and 127 are cheap due to moveq. */ | |
2099 | return 0; | |
2100 | case MVZ: | |
2101 | case MVS: | |
2102 | case NOTB: | |
2103 | case NOTW: | |
2104 | case NEGW: | |
2105 | case SWAP: | |
2106 | /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ | |
2107 | return 1; | |
2108 | case MOVL: | |
2109 | return 2; | |
2110 | default: | |
2111 | gcc_unreachable (); | |
0ce6f9fb RK |
2112 | } |
2113 | } | |
2114 | ||
3c50106f | 2115 | static bool |
8a4a2253 | 2116 | m68k_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
2117 | { |
2118 | switch (code) | |
2119 | { | |
2120 | case CONST_INT: | |
2121 | /* Constant zero is super cheap due to clr instruction. */ | |
2122 | if (x == const0_rtx) | |
2123 | *total = 0; | |
2124 | else | |
bda2a571 | 2125 | *total = const_int_cost (INTVAL (x)); |
3c50106f RH |
2126 | return true; |
2127 | ||
2128 | case CONST: | |
2129 | case LABEL_REF: | |
2130 | case SYMBOL_REF: | |
2131 | *total = 3; | |
2132 | return true; | |
2133 | ||
2134 | case CONST_DOUBLE: | |
2135 | /* Make 0.0 cheaper than other floating constants to | |
2136 | encourage creating tstsf and tstdf insns. */ | |
2137 | if (outer_code == COMPARE | |
2138 | && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) | |
2139 | *total = 4; | |
2140 | else | |
2141 | *total = 5; | |
2142 | return true; | |
2143 | ||
2144 | /* These are vaguely right for a 68020. */ | |
2145 | /* The costs for long multiply have been adjusted to work properly | |
2146 | in synth_mult on the 68020, relative to an average of the time | |
2147 | for add and the time for shift, taking away a little more because | |
2148 | sometimes move insns are needed. */ | |
a0a7fbc9 AS |
2149 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS |
2150 | terms. */ | |
fe95f2f7 JB |
2151 | #define MULL_COST \ |
2152 | (TUNE_68060 ? 2 \ | |
2153 | : TUNE_68040 ? 5 \ | |
2154 | : TUNE_CFV2 ? 10 \ | |
2155 | : TARGET_COLDFIRE ? 3 : 13) | |
2156 | ||
2157 | #define MULW_COST \ | |
2158 | (TUNE_68060 ? 2 \ | |
2159 | : TUNE_68040 ? 3 \ | |
2160 | : TUNE_68000_10 || TUNE_CFV2 ? 5 \ | |
2161 | : TARGET_COLDFIRE ? 2 : 8) | |
2162 | ||
2163 | #define DIVW_COST \ | |
2164 | (TARGET_CF_HWDIV ? 11 \ | |
2165 | : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) | |
3c50106f RH |
2166 | |
2167 | case PLUS: | |
2168 | /* An lea costs about three times as much as a simple add. */ | |
2169 | if (GET_MODE (x) == SImode | |
2170 | && GET_CODE (XEXP (x, 1)) == REG | |
2171 | && GET_CODE (XEXP (x, 0)) == MULT | |
2172 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2173 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2174 | && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 | |
2175 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 | |
2176 | || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) | |
eb849993 BI |
2177 | { |
2178 | /* lea an@(dx:l:i),am */ | |
2179 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); | |
2180 | return true; | |
2181 | } | |
3c50106f RH |
2182 | return false; |
2183 | ||
2184 | case ASHIFT: | |
2185 | case ASHIFTRT: | |
2186 | case LSHIFTRT: | |
fe95f2f7 | 2187 | if (TUNE_68060) |
3c50106f RH |
2188 | { |
2189 | *total = COSTS_N_INSNS(1); | |
2190 | return true; | |
2191 | } | |
fe95f2f7 | 2192 | if (TUNE_68000_10) |
3c50106f RH |
2193 | { |
2194 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2195 | { | |
2196 | if (INTVAL (XEXP (x, 1)) < 16) | |
2197 | *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; | |
2198 | else | |
2199 | /* We're using clrw + swap for these cases. */ | |
2200 | *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; | |
2201 | } | |
2202 | else | |
a0a7fbc9 | 2203 | *total = COSTS_N_INSNS (10); /* Worst case. */ |
3c50106f RH |
2204 | return true; |
2205 | } | |
2206 | /* A shift by a big integer takes an extra instruction. */ | |
2207 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2208 | && (INTVAL (XEXP (x, 1)) == 16)) | |
2209 | { | |
2210 | *total = COSTS_N_INSNS (2); /* clrw;swap */ | |
2211 | return true; | |
2212 | } | |
2213 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2214 | && !(INTVAL (XEXP (x, 1)) > 0 | |
2215 | && INTVAL (XEXP (x, 1)) <= 8)) | |
2216 | { | |
eb849993 | 2217 | *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ |
3c50106f RH |
2218 | return true; |
2219 | } | |
2220 | return false; | |
2221 | ||
2222 | case MULT: | |
2223 | if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2224 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
2225 | && GET_MODE (x) == SImode) | |
2226 | *total = COSTS_N_INSNS (MULW_COST); | |
2227 | else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2228 | *total = COSTS_N_INSNS (MULW_COST); | |
2229 | else | |
2230 | *total = COSTS_N_INSNS (MULL_COST); | |
2231 | return true; | |
2232 | ||
2233 | case DIV: | |
2234 | case UDIV: | |
2235 | case MOD: | |
2236 | case UMOD: | |
2237 | if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) | |
2238 | *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ | |
eb849993 BI |
2239 | else if (TARGET_CF_HWDIV) |
2240 | *total = COSTS_N_INSNS (18); | |
3c50106f RH |
2241 | else |
2242 | *total = COSTS_N_INSNS (43); /* div.l */ | |
2243 | return true; | |
2244 | ||
2245 | default: | |
2246 | return false; | |
2247 | } | |
2248 | } | |
2249 | ||
88512ba0 | 2250 | /* Return an instruction to move CONST_INT OPERANDS[1] into data register |
bda2a571 RS |
2251 | OPERANDS[0]. */ |
2252 | ||
2253 | static const char * | |
8a4a2253 | 2254 | output_move_const_into_data_reg (rtx *operands) |
0ce6f9fb | 2255 | { |
bda2a571 | 2256 | HOST_WIDE_INT i; |
0ce6f9fb RK |
2257 | |
2258 | i = INTVAL (operands[1]); | |
bda2a571 | 2259 | switch (const_method (i)) |
0ce6f9fb | 2260 | { |
28bad6d1 | 2261 | case MVZ: |
28bad6d1 | 2262 | return "mvzw %1,%0"; |
1cbae84f PB |
2263 | case MVS: |
2264 | return "mvsw %1,%0"; | |
a0a7fbc9 | 2265 | case MOVQ: |
0ce6f9fb | 2266 | return "moveq %1,%0"; |
a0a7fbc9 | 2267 | case NOTB: |
66e07510 | 2268 | CC_STATUS_INIT; |
1d8eaa6b | 2269 | operands[1] = GEN_INT (i ^ 0xff); |
0ce6f9fb | 2270 | return "moveq %1,%0\n\tnot%.b %0"; |
a0a7fbc9 | 2271 | case NOTW: |
66e07510 | 2272 | CC_STATUS_INIT; |
1d8eaa6b | 2273 | operands[1] = GEN_INT (i ^ 0xffff); |
0ce6f9fb | 2274 | return "moveq %1,%0\n\tnot%.w %0"; |
a0a7fbc9 | 2275 | case NEGW: |
66e07510 | 2276 | CC_STATUS_INIT; |
3b4b85c9 | 2277 | return "moveq #-128,%0\n\tneg%.w %0"; |
a0a7fbc9 | 2278 | case SWAP: |
0ce6f9fb RK |
2279 | { |
2280 | unsigned u = i; | |
2281 | ||
1d8eaa6b | 2282 | operands[1] = GEN_INT ((u << 16) | (u >> 16)); |
0ce6f9fb | 2283 | return "moveq %1,%0\n\tswap %0"; |
0ce6f9fb | 2284 | } |
a0a7fbc9 | 2285 | case MOVL: |
bda2a571 | 2286 | return "move%.l %1,%0"; |
a0a7fbc9 | 2287 | default: |
bda2a571 | 2288 | gcc_unreachable (); |
0ce6f9fb RK |
2289 | } |
2290 | } | |
2291 | ||
bda2a571 | 2292 | /* Return true if I can be handled by ISA B's mov3q instruction. */ |
5e04daf3 | 2293 | |
bda2a571 RS |
2294 | bool |
2295 | valid_mov3q_const (HOST_WIDE_INT i) | |
2296 | { | |
2297 | return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); | |
5e04daf3 PB |
2298 | } |
2299 | ||
bda2a571 RS |
2300 | /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. |
2301 | I is the value of OPERANDS[1]. */ | |
5e04daf3 | 2302 | |
bda2a571 | 2303 | static const char * |
8a4a2253 | 2304 | output_move_simode_const (rtx *operands) |
02ed0c07 | 2305 | { |
bda2a571 RS |
2306 | rtx dest; |
2307 | HOST_WIDE_INT src; | |
2308 | ||
2309 | dest = operands[0]; | |
2310 | src = INTVAL (operands[1]); | |
2311 | if (src == 0 | |
2312 | && (DATA_REG_P (dest) || MEM_P (dest)) | |
3197c489 RS |
2313 | /* clr insns on 68000 read before writing. */ |
2314 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
bda2a571 | 2315 | || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) |
02ed0c07 | 2316 | return "clr%.l %0"; |
bda2a571 | 2317 | else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) |
a0a7fbc9 | 2318 | return "mov3q%.l %1,%0"; |
bda2a571 | 2319 | else if (src == 0 && ADDRESS_REG_P (dest)) |
38198304 | 2320 | return "sub%.l %0,%0"; |
bda2a571 | 2321 | else if (DATA_REG_P (dest)) |
02ed0c07 | 2322 | return output_move_const_into_data_reg (operands); |
bda2a571 | 2323 | else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) |
5e04daf3 | 2324 | { |
bda2a571 | 2325 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2326 | return "mov3q%.l %1,%0"; |
2327 | return "move%.w %1,%0"; | |
2328 | } | |
bda2a571 RS |
2329 | else if (MEM_P (dest) |
2330 | && GET_CODE (XEXP (dest, 0)) == PRE_DEC | |
2331 | && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
2332 | && IN_RANGE (src, -0x8000, 0x7fff)) | |
5e04daf3 | 2333 | { |
bda2a571 | 2334 | if (valid_mov3q_const (src)) |
5e04daf3 PB |
2335 | return "mov3q%.l %1,%-"; |
2336 | return "pea %a1"; | |
2337 | } | |
02ed0c07 RK |
2338 | return "move%.l %1,%0"; |
2339 | } | |
2340 | ||
5505f548 | 2341 | const char * |
8a4a2253 | 2342 | output_move_simode (rtx *operands) |
f4e80198 RK |
2343 | { |
2344 | if (GET_CODE (operands[1]) == CONST_INT) | |
2345 | return output_move_simode_const (operands); | |
2346 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2347 | || GET_CODE (operands[1]) == CONST) | |
2348 | && push_operand (operands[0], SImode)) | |
2349 | return "pea %a1"; | |
2350 | else if ((GET_CODE (operands[1]) == SYMBOL_REF | |
2351 | || GET_CODE (operands[1]) == CONST) | |
2352 | && ADDRESS_REG_P (operands[0])) | |
2353 | return "lea %a1,%0"; | |
2354 | return "move%.l %1,%0"; | |
2355 | } | |
2356 | ||
5505f548 | 2357 | const char * |
8a4a2253 | 2358 | output_move_himode (rtx *operands) |
f4e80198 RK |
2359 | { |
2360 | if (GET_CODE (operands[1]) == CONST_INT) | |
2361 | { | |
2362 | if (operands[1] == const0_rtx | |
2363 | && (DATA_REG_P (operands[0]) | |
2364 | || GET_CODE (operands[0]) == MEM) | |
3197c489 RS |
2365 | /* clr insns on 68000 read before writing. */ |
2366 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
f4e80198 RK |
2367 | || !(GET_CODE (operands[0]) == MEM |
2368 | && MEM_VOLATILE_P (operands[0])))) | |
2369 | return "clr%.w %0"; | |
38198304 AS |
2370 | else if (operands[1] == const0_rtx |
2371 | && ADDRESS_REG_P (operands[0])) | |
2372 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2373 | else if (DATA_REG_P (operands[0]) |
2374 | && INTVAL (operands[1]) < 128 | |
2375 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2376 | return "moveq %1,%0"; |
f4e80198 RK |
2377 | else if (INTVAL (operands[1]) < 0x8000 |
2378 | && INTVAL (operands[1]) >= -0x8000) | |
2379 | return "move%.w %1,%0"; | |
2380 | } | |
2381 | else if (CONSTANT_P (operands[1])) | |
2382 | return "move%.l %1,%0"; | |
f4e80198 RK |
2383 | /* Recognize the insn before a tablejump, one that refers |
2384 | to a table of offsets. Such an insn will need to refer | |
2385 | to a label on the insn. So output one. Use the label-number | |
2386 | of the table of offsets to generate this label. This code, | |
2387 | and similar code below, assumes that there will be at most one | |
2388 | reference to each table. */ | |
2389 | if (GET_CODE (operands[1]) == MEM | |
2390 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2391 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF | |
2392 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) | |
2393 | { | |
2394 | rtx labelref = XEXP (XEXP (operands[1], 0), 1); | |
3b4b85c9 BI |
2395 | if (MOTOROLA) |
2396 | asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", | |
2397 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); | |
2398 | else | |
2399 | (*targetm.asm_out.internal_label) (asm_out_file, "LI", | |
a0a7fbc9 | 2400 | CODE_LABEL_NUMBER (XEXP (labelref, 0))); |
f4e80198 | 2401 | } |
f4e80198 RK |
2402 | return "move%.w %1,%0"; |
2403 | } | |
2404 | ||
5505f548 | 2405 | const char * |
8a4a2253 | 2406 | output_move_qimode (rtx *operands) |
f4e80198 | 2407 | { |
102701ff | 2408 | /* 68k family always modifies the stack pointer by at least 2, even for |
c16eadc7 | 2409 | byte pushes. The 5200 (ColdFire) does not do this. */ |
4761e388 | 2410 | |
a0a7fbc9 | 2411 | /* This case is generated by pushqi1 pattern now. */ |
4761e388 NS |
2412 | gcc_assert (!(GET_CODE (operands[0]) == MEM |
2413 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
2414 | && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx | |
2415 | && ! ADDRESS_REG_P (operands[1]) | |
2416 | && ! TARGET_COLDFIRE)); | |
f4e80198 | 2417 | |
3197c489 | 2418 | /* clr and st insns on 68000 read before writing. */ |
f4e80198 | 2419 | if (!ADDRESS_REG_P (operands[0]) |
3197c489 | 2420 | && ((TARGET_68010 || TARGET_COLDFIRE) |
f4e80198 RK |
2421 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2422 | { | |
2423 | if (operands[1] == const0_rtx) | |
2424 | return "clr%.b %0"; | |
9425fb04 | 2425 | if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) |
f4e80198 RK |
2426 | && GET_CODE (operands[1]) == CONST_INT |
2427 | && (INTVAL (operands[1]) & 255) == 255) | |
2428 | { | |
2429 | CC_STATUS_INIT; | |
2430 | return "st %0"; | |
2431 | } | |
2432 | } | |
2433 | if (GET_CODE (operands[1]) == CONST_INT | |
2434 | && DATA_REG_P (operands[0]) | |
2435 | && INTVAL (operands[1]) < 128 | |
2436 | && INTVAL (operands[1]) >= -128) | |
a0a7fbc9 | 2437 | return "moveq %1,%0"; |
38198304 AS |
2438 | if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) |
2439 | return "sub%.l %0,%0"; | |
f4e80198 RK |
2440 | if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) |
2441 | return "move%.l %1,%0"; | |
c16eadc7 | 2442 | /* 68k family (including the 5200 ColdFire) does not support byte moves to |
37834fc8 JL |
2443 | from address registers. */ |
2444 | if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) | |
f4e80198 RK |
2445 | return "move%.w %1,%0"; |
2446 | return "move%.b %1,%0"; | |
2447 | } | |
2448 | ||
5505f548 | 2449 | const char * |
8a4a2253 | 2450 | output_move_stricthi (rtx *operands) |
9b55bf04 RK |
2451 | { |
2452 | if (operands[1] == const0_rtx | |
3197c489 RS |
2453 | /* clr insns on 68000 read before writing. */ |
2454 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2455 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2456 | return "clr%.w %0"; | |
2457 | return "move%.w %1,%0"; | |
2458 | } | |
2459 | ||
5505f548 | 2460 | const char * |
8a4a2253 | 2461 | output_move_strictqi (rtx *operands) |
9b55bf04 RK |
2462 | { |
2463 | if (operands[1] == const0_rtx | |
3197c489 RS |
2464 | /* clr insns on 68000 read before writing. */ |
2465 | && ((TARGET_68010 || TARGET_COLDFIRE) | |
9b55bf04 RK |
2466 | || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) |
2467 | return "clr%.b %0"; | |
2468 | return "move%.b %1,%0"; | |
2469 | } | |
2470 | ||
79e68feb RS |
2471 | /* Return the best assembler insn template |
2472 | for moving operands[1] into operands[0] as a fullword. */ | |
2473 | ||
5505f548 | 2474 | static const char * |
8a4a2253 | 2475 | singlemove_string (rtx *operands) |
79e68feb | 2476 | { |
02ed0c07 RK |
2477 | if (GET_CODE (operands[1]) == CONST_INT) |
2478 | return output_move_simode_const (operands); | |
2479 | return "move%.l %1,%0"; | |
79e68feb RS |
2480 | } |
2481 | ||
2505bc97 | 2482 | |
79e68feb RS |
2483 | /* Output assembler code to perform a doubleword move insn |
2484 | with operands OPERANDS. */ | |
2485 | ||
5505f548 | 2486 | const char * |
8a4a2253 | 2487 | output_move_double (rtx *operands) |
79e68feb | 2488 | { |
2505bc97 RS |
2489 | enum |
2490 | { | |
2491 | REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP | |
2492 | } optype0, optype1; | |
79e68feb | 2493 | rtx latehalf[2]; |
2505bc97 | 2494 | rtx middlehalf[2]; |
7f98eeb6 | 2495 | rtx xops[2]; |
79e68feb | 2496 | rtx addreg0 = 0, addreg1 = 0; |
7f98eeb6 | 2497 | int dest_overlapped_low = 0; |
184916bc | 2498 | int size = GET_MODE_SIZE (GET_MODE (operands[0])); |
2505bc97 RS |
2499 | |
2500 | middlehalf[0] = 0; | |
2501 | middlehalf[1] = 0; | |
79e68feb RS |
2502 | |
2503 | /* First classify both operands. */ | |
2504 | ||
2505 | if (REG_P (operands[0])) | |
2506 | optype0 = REGOP; | |
2507 | else if (offsettable_memref_p (operands[0])) | |
2508 | optype0 = OFFSOP; | |
2509 | else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) | |
2510 | optype0 = POPOP; | |
2511 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
2512 | optype0 = PUSHOP; | |
2513 | else if (GET_CODE (operands[0]) == MEM) | |
2514 | optype0 = MEMOP; | |
2515 | else | |
2516 | optype0 = RNDOP; | |
2517 | ||
2518 | if (REG_P (operands[1])) | |
2519 | optype1 = REGOP; | |
2520 | else if (CONSTANT_P (operands[1])) | |
2521 | optype1 = CNSTOP; | |
2522 | else if (offsettable_memref_p (operands[1])) | |
2523 | optype1 = OFFSOP; | |
2524 | else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) | |
2525 | optype1 = POPOP; | |
2526 | else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) | |
2527 | optype1 = PUSHOP; | |
2528 | else if (GET_CODE (operands[1]) == MEM) | |
2529 | optype1 = MEMOP; | |
2530 | else | |
2531 | optype1 = RNDOP; | |
2532 | ||
4761e388 NS |
2533 | /* Check for the cases that the operand constraints are not supposed |
2534 | to allow to happen. Generating code for these cases is | |
2535 | painful. */ | |
2536 | gcc_assert (optype0 != RNDOP && optype1 != RNDOP); | |
79e68feb RS |
2537 | |
2538 | /* If one operand is decrementing and one is incrementing | |
2539 | decrement the former register explicitly | |
2540 | and change that operand into ordinary indexing. */ | |
2541 | ||
2542 | if (optype0 == PUSHOP && optype1 == POPOP) | |
2543 | { | |
2544 | operands[0] = XEXP (XEXP (operands[0], 0), 0); | |
2505bc97 | 2545 | if (size == 12) |
3b4b85c9 | 2546 | output_asm_insn ("sub%.l #12,%0", operands); |
2505bc97 | 2547 | else |
3b4b85c9 | 2548 | output_asm_insn ("subq%.l #8,%0", operands); |
2505bc97 | 2549 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2550 | operands[0] = gen_rtx_MEM (XFmode, operands[0]); |
2505bc97 | 2551 | else if (GET_MODE (operands[0]) == DFmode) |
1d8eaa6b | 2552 | operands[0] = gen_rtx_MEM (DFmode, operands[0]); |
2505bc97 | 2553 | else |
1d8eaa6b | 2554 | operands[0] = gen_rtx_MEM (DImode, operands[0]); |
79e68feb RS |
2555 | optype0 = OFFSOP; |
2556 | } | |
2557 | if (optype0 == POPOP && optype1 == PUSHOP) | |
2558 | { | |
2559 | operands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2505bc97 | 2560 | if (size == 12) |
3b4b85c9 | 2561 | output_asm_insn ("sub%.l #12,%1", operands); |
2505bc97 | 2562 | else |
3b4b85c9 | 2563 | output_asm_insn ("subq%.l #8,%1", operands); |
2505bc97 | 2564 | if (GET_MODE (operands[1]) == XFmode) |
1d8eaa6b | 2565 | operands[1] = gen_rtx_MEM (XFmode, operands[1]); |
2505bc97 | 2566 | else if (GET_MODE (operands[1]) == DFmode) |
1d8eaa6b | 2567 | operands[1] = gen_rtx_MEM (DFmode, operands[1]); |
2505bc97 | 2568 | else |
1d8eaa6b | 2569 | operands[1] = gen_rtx_MEM (DImode, operands[1]); |
79e68feb RS |
2570 | optype1 = OFFSOP; |
2571 | } | |
2572 | ||
2573 | /* If an operand is an unoffsettable memory ref, find a register | |
2574 | we can increment temporarily to make it refer to the second word. */ | |
2575 | ||
2576 | if (optype0 == MEMOP) | |
2577 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2578 | ||
2579 | if (optype1 == MEMOP) | |
2580 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2581 | ||
2582 | /* Ok, we can do one word at a time. | |
2583 | Normally we do the low-numbered word first, | |
2584 | but if either operand is autodecrementing then we | |
2585 | do the high-numbered word first. | |
2586 | ||
2587 | In either case, set up in LATEHALF the operands to use | |
2588 | for the high-numbered word and in some cases alter the | |
2589 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2590 | ||
2505bc97 RS |
2591 | if (size == 12) |
2592 | { | |
2593 | if (optype0 == REGOP) | |
2594 | { | |
1d8eaa6b AS |
2595 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); |
2596 | middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2505bc97 RS |
2597 | } |
2598 | else if (optype0 == OFFSOP) | |
2599 | { | |
b72f00af RK |
2600 | middlehalf[0] = adjust_address (operands[0], SImode, 4); |
2601 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); | |
2505bc97 RS |
2602 | } |
2603 | else | |
2604 | { | |
2605 | middlehalf[0] = operands[0]; | |
2606 | latehalf[0] = operands[0]; | |
2607 | } | |
2608 | ||
2609 | if (optype1 == REGOP) | |
2610 | { | |
1d8eaa6b AS |
2611 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); |
2612 | middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
2505bc97 RS |
2613 | } |
2614 | else if (optype1 == OFFSOP) | |
2615 | { | |
b72f00af RK |
2616 | middlehalf[1] = adjust_address (operands[1], SImode, 4); |
2617 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); | |
2505bc97 RS |
2618 | } |
2619 | else if (optype1 == CNSTOP) | |
2620 | { | |
2621 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
2622 | { | |
2623 | REAL_VALUE_TYPE r; | |
2624 | long l[3]; | |
2625 | ||
2626 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
2627 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2628 | operands[1] = GEN_INT (l[0]); | |
2629 | middlehalf[1] = GEN_INT (l[1]); | |
2630 | latehalf[1] = GEN_INT (l[2]); | |
2631 | } | |
4761e388 | 2632 | else |
2505bc97 | 2633 | { |
4761e388 NS |
2634 | /* No non-CONST_DOUBLE constant should ever appear |
2635 | here. */ | |
2636 | gcc_assert (!CONSTANT_P (operands[1])); | |
2505bc97 RS |
2637 | } |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | middlehalf[1] = operands[1]; | |
2642 | latehalf[1] = operands[1]; | |
2643 | } | |
2644 | } | |
79e68feb | 2645 | else |
2505bc97 RS |
2646 | /* size is not 12: */ |
2647 | { | |
2648 | if (optype0 == REGOP) | |
1d8eaa6b | 2649 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
2505bc97 | 2650 | else if (optype0 == OFFSOP) |
b72f00af | 2651 | latehalf[0] = adjust_address (operands[0], SImode, size - 4); |
2505bc97 RS |
2652 | else |
2653 | latehalf[0] = operands[0]; | |
2654 | ||
2655 | if (optype1 == REGOP) | |
1d8eaa6b | 2656 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
2505bc97 | 2657 | else if (optype1 == OFFSOP) |
b72f00af | 2658 | latehalf[1] = adjust_address (operands[1], SImode, size - 4); |
2505bc97 RS |
2659 | else if (optype1 == CNSTOP) |
2660 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2661 | else | |
2662 | latehalf[1] = operands[1]; | |
2663 | } | |
79e68feb RS |
2664 | |
2665 | /* If insn is effectively movd N(sp),-(sp) then we will do the | |
2666 | high word first. We should use the adjusted operand 1 (which is N+4(sp)) | |
2667 | for the low word as well, to compensate for the first decrement of sp. */ | |
2668 | if (optype0 == PUSHOP | |
2669 | && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM | |
2670 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
c88aeaf8 | 2671 | operands[1] = middlehalf[1] = latehalf[1]; |
79e68feb | 2672 | |
7f98eeb6 RS |
2673 | /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), |
2674 | if the upper part of reg N does not appear in the MEM, arrange to | |
2675 | emit the move late-half first. Otherwise, compute the MEM address | |
2676 | into the upper part of N and use that as a pointer to the memory | |
2677 | operand. */ | |
2678 | if (optype0 == REGOP | |
2679 | && (optype1 == OFFSOP || optype1 == MEMOP)) | |
2680 | { | |
1d8eaa6b | 2681 | rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); |
3a58400f RS |
2682 | |
2683 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 | 2684 | && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
7f98eeb6 RS |
2685 | { |
2686 | /* If both halves of dest are used in the src memory address, | |
3a58400f RS |
2687 | compute the address into latehalf of dest. |
2688 | Note that this can't happen if the dest is two data regs. */ | |
4761e388 | 2689 | compadr: |
7f98eeb6 RS |
2690 | xops[0] = latehalf[0]; |
2691 | xops[1] = XEXP (operands[1], 0); | |
d7e8d581 | 2692 | output_asm_insn ("lea %a1,%0", xops); |
b72f00af | 2693 | if (GET_MODE (operands[1]) == XFmode ) |
7f98eeb6 | 2694 | { |
1d8eaa6b | 2695 | operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); |
b72f00af RK |
2696 | middlehalf[1] = adjust_address (operands[1], DImode, size - 8); |
2697 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); | |
7f98eeb6 RS |
2698 | } |
2699 | else | |
2700 | { | |
1d8eaa6b | 2701 | operands[1] = gen_rtx_MEM (DImode, latehalf[0]); |
b72f00af | 2702 | latehalf[1] = adjust_address (operands[1], DImode, size - 4); |
7f98eeb6 RS |
2703 | } |
2704 | } | |
2705 | else if (size == 12 | |
d7e8d581 RS |
2706 | && reg_overlap_mentioned_p (middlehalf[0], |
2707 | XEXP (operands[1], 0))) | |
7f98eeb6 | 2708 | { |
3a58400f RS |
2709 | /* Check for two regs used by both source and dest. |
2710 | Note that this can't happen if the dest is all data regs. | |
2711 | It can happen if the dest is d6, d7, a0. | |
2712 | But in that case, latehalf is an addr reg, so | |
2713 | the code at compadr does ok. */ | |
2714 | ||
2715 | if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) | |
d7e8d581 RS |
2716 | || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) |
2717 | goto compadr; | |
7f98eeb6 RS |
2718 | |
2719 | /* JRV says this can't happen: */ | |
4761e388 | 2720 | gcc_assert (!addreg0 && !addreg1); |
7f98eeb6 | 2721 | |
7a1929e1 | 2722 | /* Only the middle reg conflicts; simply put it last. */ |
7f98eeb6 RS |
2723 | output_asm_insn (singlemove_string (operands), operands); |
2724 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2725 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2726 | return ""; | |
2727 | } | |
2fb8a81d | 2728 | else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) |
7f98eeb6 RS |
2729 | /* If the low half of dest is mentioned in the source memory |
2730 | address, the arrange to emit the move late half first. */ | |
2731 | dest_overlapped_low = 1; | |
2732 | } | |
2733 | ||
79e68feb RS |
2734 | /* If one or both operands autodecrementing, |
2735 | do the two words, high-numbered first. */ | |
2736 | ||
2737 | /* Likewise, the first move would clobber the source of the second one, | |
2738 | do them in the other order. This happens only for registers; | |
2739 | such overlap can't happen in memory unless the user explicitly | |
2740 | sets it up, and that is an undefined circumstance. */ | |
2741 | ||
2742 | if (optype0 == PUSHOP || optype1 == PUSHOP | |
2743 | || (optype0 == REGOP && optype1 == REGOP | |
2505bc97 | 2744 | && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) |
7f98eeb6 RS |
2745 | || REGNO (operands[0]) == REGNO (latehalf[1]))) |
2746 | || dest_overlapped_low) | |
79e68feb RS |
2747 | { |
2748 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2749 | if (addreg0) | |
2505bc97 RS |
2750 | { |
2751 | if (size == 12) | |
3b4b85c9 | 2752 | output_asm_insn ("addq%.l #8,%0", &addreg0); |
2505bc97 | 2753 | else |
3b4b85c9 | 2754 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2755 | } |
79e68feb | 2756 | if (addreg1) |
2505bc97 RS |
2757 | { |
2758 | if (size == 12) | |
3b4b85c9 | 2759 | output_asm_insn ("addq%.l #8,%0", &addreg1); |
2505bc97 | 2760 | else |
3b4b85c9 | 2761 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 | 2762 | } |
79e68feb RS |
2763 | |
2764 | /* Do that word. */ | |
2765 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2766 | ||
2767 | /* Undo the adds we just did. */ | |
2768 | if (addreg0) | |
3b4b85c9 | 2769 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
79e68feb | 2770 | if (addreg1) |
3b4b85c9 | 2771 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
79e68feb | 2772 | |
2505bc97 RS |
2773 | if (size == 12) |
2774 | { | |
2775 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2776 | if (addreg0) | |
3b4b85c9 | 2777 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2778 | if (addreg1) |
3b4b85c9 | 2779 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 RS |
2780 | } |
2781 | ||
79e68feb RS |
2782 | /* Do low-numbered word. */ |
2783 | return singlemove_string (operands); | |
2784 | } | |
2785 | ||
2786 | /* Normal case: do the two words, low-numbered first. */ | |
2787 | ||
2788 | output_asm_insn (singlemove_string (operands), operands); | |
2789 | ||
2505bc97 RS |
2790 | /* Do the middle one of the three words for long double */ |
2791 | if (size == 12) | |
2792 | { | |
2793 | if (addreg0) | |
3b4b85c9 | 2794 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
2505bc97 | 2795 | if (addreg1) |
3b4b85c9 | 2796 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
2505bc97 RS |
2797 | |
2798 | output_asm_insn (singlemove_string (middlehalf), middlehalf); | |
2799 | } | |
2800 | ||
79e68feb RS |
2801 | /* Make any unoffsettable addresses point at high-numbered word. */ |
2802 | if (addreg0) | |
3b4b85c9 | 2803 | output_asm_insn ("addq%.l #4,%0", &addreg0); |
79e68feb | 2804 | if (addreg1) |
3b4b85c9 | 2805 | output_asm_insn ("addq%.l #4,%0", &addreg1); |
79e68feb RS |
2806 | |
2807 | /* Do that word. */ | |
2808 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2809 | ||
2810 | /* Undo the adds we just did. */ | |
2811 | if (addreg0) | |
2505bc97 RS |
2812 | { |
2813 | if (size == 12) | |
3b4b85c9 | 2814 | output_asm_insn ("subq%.l #8,%0", &addreg0); |
2505bc97 | 2815 | else |
3b4b85c9 | 2816 | output_asm_insn ("subq%.l #4,%0", &addreg0); |
2505bc97 | 2817 | } |
79e68feb | 2818 | if (addreg1) |
2505bc97 RS |
2819 | { |
2820 | if (size == 12) | |
3b4b85c9 | 2821 | output_asm_insn ("subq%.l #8,%0", &addreg1); |
2505bc97 | 2822 | else |
3b4b85c9 | 2823 | output_asm_insn ("subq%.l #4,%0", &addreg1); |
2505bc97 | 2824 | } |
79e68feb RS |
2825 | |
2826 | return ""; | |
2827 | } | |
2828 | ||
dcc21c4c PB |
2829 | |
2830 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a | |
2831 | new rtx with the correct mode. */ | |
2832 | ||
2833 | static rtx | |
2834 | force_mode (enum machine_mode mode, rtx orig) | |
2835 | { | |
2836 | if (mode == GET_MODE (orig)) | |
2837 | return orig; | |
2838 | ||
2839 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
2840 | abort (); | |
2841 | ||
2842 | return gen_rtx_REG (mode, REGNO (orig)); | |
2843 | } | |
2844 | ||
2845 | static int | |
2846 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2847 | { | |
2848 | return reg_renumber && FP_REG_P (op); | |
2849 | } | |
2850 | ||
2851 | /* Emit insns to move operands[1] into operands[0]. | |
2852 | ||
2853 | Return 1 if we have written out everything that needs to be done to | |
2854 | do the move. Otherwise, return 0 and the caller will emit the move | |
2855 | normally. | |
2856 | ||
2857 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c0220ea4 | 2858 | will be used. This routine is responsible for creating a new copy |
dcc21c4c PB |
2859 | of SCRATCH_REG in the proper mode. */ |
2860 | ||
2861 | int | |
2862 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) | |
2863 | { | |
2864 | register rtx operand0 = operands[0]; | |
2865 | register rtx operand1 = operands[1]; | |
2866 | register rtx tem; | |
2867 | ||
2868 | if (scratch_reg | |
2869 | && reload_in_progress && GET_CODE (operand0) == REG | |
2870 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
2871 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2872 | else if (scratch_reg | |
2873 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
2874 | && GET_CODE (SUBREG_REG (operand0)) == REG | |
2875 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
2876 | { | |
2877 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2878 | the code which tracks sets/uses for delete_output_reload. */ | |
2879 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
2880 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
2881 | SUBREG_BYTE (operand0)); | |
2882 | operand0 = alter_subreg (&temp); | |
2883 | } | |
2884 | ||
2885 | if (scratch_reg | |
2886 | && reload_in_progress && GET_CODE (operand1) == REG | |
2887 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) | |
2888 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2889 | else if (scratch_reg | |
2890 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
2891 | && GET_CODE (SUBREG_REG (operand1)) == REG | |
2892 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
2893 | { | |
2894 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse | |
2895 | the code which tracks sets/uses for delete_output_reload. */ | |
2896 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
2897 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
2898 | SUBREG_BYTE (operand1)); | |
2899 | operand1 = alter_subreg (&temp); | |
2900 | } | |
2901 | ||
2902 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM | |
2903 | && ((tem = find_replacement (&XEXP (operand0, 0))) | |
2904 | != XEXP (operand0, 0))) | |
2905 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); | |
2906 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM | |
2907 | && ((tem = find_replacement (&XEXP (operand1, 0))) | |
2908 | != XEXP (operand1, 0))) | |
2909 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); | |
2910 | ||
2911 | /* Handle secondary reloads for loads/stores of FP registers where | |
2912 | the address is symbolic by using the scratch register */ | |
2913 | if (fp_reg_operand (operand0, mode) | |
2914 | && ((GET_CODE (operand1) == MEM | |
2915 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
2916 | || ((GET_CODE (operand1) == SUBREG | |
2917 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
2918 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
2919 | && scratch_reg) | |
2920 | { | |
2921 | if (GET_CODE (operand1) == SUBREG) | |
2922 | operand1 = XEXP (operand1, 0); | |
2923 | ||
2924 | /* SCRATCH_REG will hold an address. We want | |
2925 | it in SImode regardless of what mode it was originally given | |
2926 | to us. */ | |
2927 | scratch_reg = force_mode (SImode, scratch_reg); | |
2928 | ||
2929 | /* D might not fit in 14 bits either; for such cases load D into | |
2930 | scratch reg. */ | |
2931 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) | |
2932 | { | |
2933 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
2934 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
2935 | Pmode, | |
2936 | XEXP (XEXP (operand1, 0), 0), | |
2937 | scratch_reg)); | |
2938 | } | |
2939 | else | |
2940 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
2941 | emit_insn (gen_rtx_SET (VOIDmode, operand0, | |
2942 | gen_rtx_MEM (mode, scratch_reg))); | |
2943 | return 1; | |
2944 | } | |
2945 | else if (fp_reg_operand (operand1, mode) | |
2946 | && ((GET_CODE (operand0) == MEM | |
2947 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
2948 | || ((GET_CODE (operand0) == SUBREG) | |
2949 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
2950 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
2951 | && scratch_reg) | |
2952 | { | |
2953 | if (GET_CODE (operand0) == SUBREG) | |
2954 | operand0 = XEXP (operand0, 0); | |
2955 | ||
2956 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2957 | it in SIMODE regardless of what mode it was originally given | |
2958 | to us. */ | |
2959 | scratch_reg = force_mode (SImode, scratch_reg); | |
2960 | ||
2961 | /* D might not fit in 14 bits either; for such cases load D into | |
2962 | scratch reg. */ | |
2963 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) | |
2964 | { | |
2965 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
2966 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, | |
2967 | 0)), | |
2968 | Pmode, | |
2969 | XEXP (XEXP (operand0, 0), | |
2970 | 0), | |
2971 | scratch_reg)); | |
2972 | } | |
2973 | else | |
2974 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
2975 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), | |
2976 | operand1)); | |
2977 | return 1; | |
2978 | } | |
2979 | /* Handle secondary reloads for loads of FP registers from constant | |
2980 | expressions by forcing the constant into memory. | |
2981 | ||
2982 | use scratch_reg to hold the address of the memory location. | |
2983 | ||
2984 | The proper fix is to change PREFERRED_RELOAD_CLASS to return | |
2985 | NO_REGS when presented with a const_int and an register class | |
2986 | containing only FP registers. Doing so unfortunately creates | |
2987 | more problems than it solves. Fix this for 2.5. */ | |
2988 | else if (fp_reg_operand (operand0, mode) | |
2989 | && CONSTANT_P (operand1) | |
2990 | && scratch_reg) | |
2991 | { | |
2992 | rtx xoperands[2]; | |
2993 | ||
2994 | /* SCRATCH_REG will hold an address and maybe the actual data. We want | |
2995 | it in SIMODE regardless of what mode it was originally given | |
2996 | to us. */ | |
2997 | scratch_reg = force_mode (SImode, scratch_reg); | |
2998 | ||
2999 | /* Force the constant into memory and put the address of the | |
3000 | memory location into scratch_reg. */ | |
3001 | xoperands[0] = scratch_reg; | |
3002 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
3003 | emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); | |
3004 | ||
3005 | /* Now load the destination register. */ | |
3006 | emit_insn (gen_rtx_SET (mode, operand0, | |
3007 | gen_rtx_MEM (mode, scratch_reg))); | |
3008 | return 1; | |
3009 | } | |
3010 | ||
3011 | /* Now have insn-emit do whatever it normally does. */ | |
3012 | return 0; | |
3013 | } | |
3014 | ||
01e304f8 RZ |
3015 | /* Split one or more DImode RTL references into pairs of SImode |
3016 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
3017 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
3018 | split and "num" is its length. lo_half and hi_half are output arrays | |
3019 | that parallel "operands". */ | |
3020 | ||
3021 | void | |
3022 | split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) | |
3023 | { | |
3024 | while (num--) | |
3025 | { | |
3026 | rtx op = operands[num]; | |
3027 | ||
3028 | /* simplify_subreg refuses to split volatile memory addresses, | |
3029 | but we still have to handle it. */ | |
3030 | if (GET_CODE (op) == MEM) | |
3031 | { | |
3032 | lo_half[num] = adjust_address (op, SImode, 4); | |
3033 | hi_half[num] = adjust_address (op, SImode, 0); | |
3034 | } | |
3035 | else | |
3036 | { | |
3037 | lo_half[num] = simplify_gen_subreg (SImode, op, | |
3038 | GET_MODE (op) == VOIDmode | |
3039 | ? DImode : GET_MODE (op), 4); | |
3040 | hi_half[num] = simplify_gen_subreg (SImode, op, | |
3041 | GET_MODE (op) == VOIDmode | |
3042 | ? DImode : GET_MODE (op), 0); | |
3043 | } | |
3044 | } | |
3045 | } | |
3046 | ||
a40ed0f3 KH |
3047 | /* Split X into a base and a constant offset, storing them in *BASE |
3048 | and *OFFSET respectively. */ | |
3049 | ||
3050 | static void | |
3051 | m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) | |
3052 | { | |
3053 | *offset = 0; | |
3054 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3055 | { | |
3056 | *offset += INTVAL (XEXP (x, 1)); | |
3057 | x = XEXP (x, 0); | |
3058 | } | |
3059 | *base = x; | |
3060 | } | |
3061 | ||
3062 | /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem | |
3063 | instruction. STORE_P says whether the move is a load or store. | |
3064 | ||
3065 | If the instruction uses post-increment or pre-decrement addressing, | |
3066 | AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total | |
3067 | adjustment. This adjustment will be made by the first element of | |
3068 | PARALLEL, with the loads or stores starting at element 1. If the | |
3069 | instruction does not use post-increment or pre-decrement addressing, | |
3070 | AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores | |
3071 | start at element 0. */ | |
3072 | ||
3073 | bool | |
3074 | m68k_movem_pattern_p (rtx pattern, rtx automod_base, | |
3075 | HOST_WIDE_INT automod_offset, bool store_p) | |
3076 | { | |
3077 | rtx base, mem_base, set, mem, reg, last_reg; | |
3078 | HOST_WIDE_INT offset, mem_offset; | |
3079 | int i, first, len; | |
3080 | enum reg_class rclass; | |
3081 | ||
3082 | len = XVECLEN (pattern, 0); | |
3083 | first = (automod_base != NULL); | |
3084 | ||
3085 | if (automod_base) | |
3086 | { | |
3087 | /* Stores must be pre-decrement and loads must be post-increment. */ | |
3088 | if (store_p != (automod_offset < 0)) | |
3089 | return false; | |
3090 | ||
3091 | /* Work out the base and offset for lowest memory location. */ | |
3092 | base = automod_base; | |
3093 | offset = (automod_offset < 0 ? automod_offset : 0); | |
3094 | } | |
3095 | else | |
3096 | { | |
3097 | /* Allow any valid base and offset in the first access. */ | |
3098 | base = NULL; | |
3099 | offset = 0; | |
3100 | } | |
3101 | ||
3102 | last_reg = NULL; | |
3103 | rclass = NO_REGS; | |
3104 | for (i = first; i < len; i++) | |
3105 | { | |
3106 | /* We need a plain SET. */ | |
3107 | set = XVECEXP (pattern, 0, i); | |
3108 | if (GET_CODE (set) != SET) | |
3109 | return false; | |
3110 | ||
3111 | /* Check that we have a memory location... */ | |
3112 | mem = XEXP (set, !store_p); | |
3113 | if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) | |
3114 | return false; | |
3115 | ||
3116 | /* ...with the right address. */ | |
3117 | if (base == NULL) | |
3118 | { | |
3119 | m68k_split_offset (XEXP (mem, 0), &base, &offset); | |
3120 | /* The ColdFire instruction only allows (An) and (d16,An) modes. | |
3121 | There are no mode restrictions for 680x0 besides the | |
3122 | automodification rules enforced above. */ | |
3123 | if (TARGET_COLDFIRE | |
3124 | && !m68k_legitimate_base_reg_p (base, reload_completed)) | |
3125 | return false; | |
3126 | } | |
3127 | else | |
3128 | { | |
3129 | m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); | |
3130 | if (!rtx_equal_p (base, mem_base) || offset != mem_offset) | |
3131 | return false; | |
3132 | } | |
3133 | ||
3134 | /* Check that we have a register of the required mode and class. */ | |
3135 | reg = XEXP (set, store_p); | |
3136 | if (!REG_P (reg) | |
3137 | || !HARD_REGISTER_P (reg) | |
3138 | || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) | |
3139 | return false; | |
3140 | ||
3141 | if (last_reg) | |
3142 | { | |
3143 | /* The register must belong to RCLASS and have a higher number | |
3144 | than the register in the previous SET. */ | |
3145 | if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) | |
3146 | || REGNO (last_reg) >= REGNO (reg)) | |
3147 | return false; | |
3148 | } | |
3149 | else | |
3150 | { | |
3151 | /* Work out which register class we need. */ | |
3152 | if (INT_REGNO_P (REGNO (reg))) | |
3153 | rclass = GENERAL_REGS; | |
3154 | else if (FP_REGNO_P (REGNO (reg))) | |
3155 | rclass = FP_REGS; | |
3156 | else | |
3157 | return false; | |
3158 | } | |
3159 | ||
3160 | last_reg = reg; | |
3161 | offset += GET_MODE_SIZE (GET_MODE (reg)); | |
3162 | } | |
3163 | ||
3164 | /* If we have an automodification, check whether the final offset is OK. */ | |
3165 | if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) | |
3166 | return false; | |
3167 | ||
3168 | /* Reject unprofitable cases. */ | |
3169 | if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) | |
3170 | return false; | |
3171 | ||
3172 | return true; | |
3173 | } | |
3174 | ||
3175 | /* Return the assembly code template for a movem or fmovem instruction | |
3176 | whose pattern is given by PATTERN. Store the template's operands | |
3177 | in OPERANDS. | |
3178 | ||
3179 | If the instruction uses post-increment or pre-decrement addressing, | |
3180 | AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P | |
3181 | is true if this is a store instruction. */ | |
3182 | ||
3183 | const char * | |
3184 | m68k_output_movem (rtx *operands, rtx pattern, | |
3185 | HOST_WIDE_INT automod_offset, bool store_p) | |
3186 | { | |
3187 | unsigned int mask; | |
3188 | int i, first; | |
3189 | ||
3190 | gcc_assert (GET_CODE (pattern) == PARALLEL); | |
3191 | mask = 0; | |
3192 | first = (automod_offset != 0); | |
3193 | for (i = first; i < XVECLEN (pattern, 0); i++) | |
3194 | { | |
3195 | /* When using movem with pre-decrement addressing, register X + D0_REG | |
3196 | is controlled by bit 15 - X. For all other addressing modes, | |
3197 | register X + D0_REG is controlled by bit X. Confusingly, the | |
3198 | register mask for fmovem is in the opposite order to that for | |
3199 | movem. */ | |
3200 | unsigned int regno; | |
3201 | ||
3202 | gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); | |
3203 | gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); | |
3204 | regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); | |
3205 | if (automod_offset < 0) | |
3206 | { | |
3207 | if (FP_REGNO_P (regno)) | |
3208 | mask |= 1 << (regno - FP0_REG); | |
3209 | else | |
3210 | mask |= 1 << (15 - (regno - D0_REG)); | |
3211 | } | |
3212 | else | |
3213 | { | |
3214 | if (FP_REGNO_P (regno)) | |
3215 | mask |= 1 << (7 - (regno - FP0_REG)); | |
3216 | else | |
3217 | mask |= 1 << (regno - D0_REG); | |
3218 | } | |
3219 | } | |
3220 | CC_STATUS_INIT; | |
3221 | ||
3222 | if (automod_offset == 0) | |
3223 | operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); | |
3224 | else if (automod_offset < 0) | |
3225 | operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3226 | else | |
3227 | operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); | |
3228 | operands[1] = GEN_INT (mask); | |
3229 | if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) | |
3230 | { | |
3231 | if (store_p) | |
3232 | return MOTOROLA ? "fmovm %1,%a0" : "fmovem %1,%a0"; | |
3233 | else | |
3234 | return MOTOROLA ? "fmovm %a0,%1" : "fmovem %a0,%1"; | |
3235 | } | |
3236 | else | |
3237 | { | |
3238 | if (store_p) | |
3239 | return MOTOROLA ? "movm.l %1,%a0" : "moveml %1,%a0"; | |
3240 | else | |
3241 | return MOTOROLA ? "movm.l %a0,%1" : "moveml %a0,%1"; | |
3242 | } | |
3243 | } | |
3244 | ||
79e68feb RS |
3245 | /* Return a REG that occurs in ADDR with coefficient 1. |
3246 | ADDR can be effectively incremented by incrementing REG. */ | |
3247 | ||
3248 | static rtx | |
8a4a2253 | 3249 | find_addr_reg (rtx addr) |
79e68feb RS |
3250 | { |
3251 | while (GET_CODE (addr) == PLUS) | |
3252 | { | |
3253 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
3254 | addr = XEXP (addr, 0); | |
3255 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
3256 | addr = XEXP (addr, 1); | |
3257 | else if (CONSTANT_P (XEXP (addr, 0))) | |
3258 | addr = XEXP (addr, 1); | |
3259 | else if (CONSTANT_P (XEXP (addr, 1))) | |
3260 | addr = XEXP (addr, 0); | |
3261 | else | |
4761e388 | 3262 | gcc_unreachable (); |
79e68feb | 3263 | } |
4761e388 NS |
3264 | gcc_assert (GET_CODE (addr) == REG); |
3265 | return addr; | |
79e68feb | 3266 | } |
9ee3c687 | 3267 | |
c16eadc7 | 3268 | /* Output assembler code to perform a 32-bit 3-operand add. */ |
9ee3c687 | 3269 | |
5505f548 | 3270 | const char * |
8a4a2253 | 3271 | output_addsi3 (rtx *operands) |
9ee3c687 JW |
3272 | { |
3273 | if (! operands_match_p (operands[0], operands[1])) | |
3274 | { | |
3275 | if (!ADDRESS_REG_P (operands[1])) | |
3276 | { | |
3277 | rtx tmp = operands[1]; | |
3278 | ||
3279 | operands[1] = operands[2]; | |
3280 | operands[2] = tmp; | |
3281 | } | |
3282 | ||
3283 | /* These insns can result from reloads to access | |
3284 | stack slots over 64k from the frame pointer. */ | |
3285 | if (GET_CODE (operands[2]) == CONST_INT | |
218d5a87 | 3286 | && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) |
8c61b6c1 | 3287 | return "move%.l %2,%0\n\tadd%.l %1,%0"; |
9ee3c687 | 3288 | if (GET_CODE (operands[2]) == REG) |
3b4b85c9 BI |
3289 | return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; |
3290 | return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; | |
9ee3c687 JW |
3291 | } |
3292 | if (GET_CODE (operands[2]) == CONST_INT) | |
3293 | { | |
9ee3c687 JW |
3294 | if (INTVAL (operands[2]) > 0 |
3295 | && INTVAL (operands[2]) <= 8) | |
3296 | return "addq%.l %2,%0"; | |
3297 | if (INTVAL (operands[2]) < 0 | |
3298 | && INTVAL (operands[2]) >= -8) | |
3299 | { | |
c5c76735 | 3300 | operands[2] = GEN_INT (- INTVAL (operands[2])); |
9ee3c687 JW |
3301 | return "subq%.l %2,%0"; |
3302 | } | |
3303 | /* On the CPU32 it is faster to use two addql instructions to | |
3304 | add a small integer (8 < N <= 16) to a register. | |
7a1929e1 | 3305 | Likewise for subql. */ |
fe95f2f7 | 3306 | if (TUNE_CPU32 && REG_P (operands[0])) |
9ee3c687 JW |
3307 | { |
3308 | if (INTVAL (operands[2]) > 8 | |
3309 | && INTVAL (operands[2]) <= 16) | |
3310 | { | |
1d8eaa6b | 3311 | operands[2] = GEN_INT (INTVAL (operands[2]) - 8); |
3b4b85c9 | 3312 | return "addq%.l #8,%0\n\taddq%.l %2,%0"; |
9ee3c687 JW |
3313 | } |
3314 | if (INTVAL (operands[2]) < -8 | |
3315 | && INTVAL (operands[2]) >= -16) | |
3316 | { | |
c5c76735 | 3317 | operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); |
3b4b85c9 | 3318 | return "subq%.l #8,%0\n\tsubq%.l %2,%0"; |
9ee3c687 JW |
3319 | } |
3320 | } | |
9ee3c687 JW |
3321 | if (ADDRESS_REG_P (operands[0]) |
3322 | && INTVAL (operands[2]) >= -0x8000 | |
3323 | && INTVAL (operands[2]) < 0x8000) | |
3324 | { | |
fe95f2f7 | 3325 | if (TUNE_68040) |
9ee3c687 JW |
3326 | return "add%.w %2,%0"; |
3327 | else | |
e6d98cb0 | 3328 | return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; |
9ee3c687 JW |
3329 | } |
3330 | } | |
3331 | return "add%.l %2,%0"; | |
3332 | } | |
79e68feb RS |
3333 | \f |
3334 | /* Store in cc_status the expressions that the condition codes will | |
3335 | describe after execution of an instruction whose pattern is EXP. | |
3336 | Do not alter them if the instruction would not alter the cc's. */ | |
3337 | ||
3338 | /* On the 68000, all the insns to store in an address register fail to | |
3339 | set the cc's. However, in some cases these instructions can make it | |
3340 | possibly invalid to use the saved cc's. In those cases we clear out | |
3341 | some or all of the saved cc's so they won't be used. */ | |
3342 | ||
1d8eaa6b | 3343 | void |
8a4a2253 | 3344 | notice_update_cc (rtx exp, rtx insn) |
79e68feb | 3345 | { |
1a8965c4 | 3346 | if (GET_CODE (exp) == SET) |
79e68feb RS |
3347 | { |
3348 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
a0a7fbc9 | 3349 | CC_STATUS_INIT; |
79e68feb RS |
3350 | else if (ADDRESS_REG_P (SET_DEST (exp))) |
3351 | { | |
f5963e61 | 3352 | if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) |
79e68feb | 3353 | cc_status.value1 = 0; |
f5963e61 | 3354 | if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) |
79e68feb RS |
3355 | cc_status.value2 = 0; |
3356 | } | |
f6ab62e8 RS |
3357 | /* fmoves to memory or data registers do not set the condition |
3358 | codes. Normal moves _do_ set the condition codes, but not in | |
3359 | a way that is appropriate for comparison with 0, because -0.0 | |
3360 | would be treated as a negative nonzero number. Note that it | |
88512ba0 | 3361 | isn't appropriate to conditionalize this restriction on |
f6ab62e8 RS |
3362 | HONOR_SIGNED_ZEROS because that macro merely indicates whether |
3363 | we care about the difference between -0.0 and +0.0. */ | |
79e68feb RS |
3364 | else if (!FP_REG_P (SET_DEST (exp)) |
3365 | && SET_DEST (exp) != cc0_rtx | |
3366 | && (FP_REG_P (SET_SRC (exp)) | |
3367 | || GET_CODE (SET_SRC (exp)) == FIX | |
f6ab62e8 | 3368 | || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) |
a0a7fbc9 | 3369 | CC_STATUS_INIT; |
79e68feb RS |
3370 | /* A pair of move insns doesn't produce a useful overall cc. */ |
3371 | else if (!FP_REG_P (SET_DEST (exp)) | |
3372 | && !FP_REG_P (SET_SRC (exp)) | |
3373 | && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 | |
3374 | && (GET_CODE (SET_SRC (exp)) == REG | |
3375 | || GET_CODE (SET_SRC (exp)) == MEM | |
3376 | || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) | |
a0a7fbc9 | 3377 | CC_STATUS_INIT; |
e1dff52a | 3378 | else if (SET_DEST (exp) != pc_rtx) |
79e68feb RS |
3379 | { |
3380 | cc_status.flags = 0; | |
e1dff52a KH |
3381 | cc_status.value1 = SET_DEST (exp); |
3382 | cc_status.value2 = SET_SRC (exp); | |
79e68feb RS |
3383 | } |
3384 | } | |
3385 | else if (GET_CODE (exp) == PARALLEL | |
3386 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
3387 | { | |
e1dff52a KH |
3388 | rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); |
3389 | rtx src = SET_SRC (XVECEXP (exp, 0, 0)); | |
3390 | ||
3391 | if (ADDRESS_REG_P (dest)) | |
79e68feb | 3392 | CC_STATUS_INIT; |
e1dff52a | 3393 | else if (dest != pc_rtx) |
79e68feb RS |
3394 | { |
3395 | cc_status.flags = 0; | |
e1dff52a KH |
3396 | cc_status.value1 = dest; |
3397 | cc_status.value2 = src; | |
79e68feb RS |
3398 | } |
3399 | } | |
3400 | else | |
3401 | CC_STATUS_INIT; | |
3402 | if (cc_status.value2 != 0 | |
3403 | && ADDRESS_REG_P (cc_status.value2) | |
3404 | && GET_MODE (cc_status.value2) == QImode) | |
3405 | CC_STATUS_INIT; | |
1a8965c4 | 3406 | if (cc_status.value2 != 0) |
79e68feb RS |
3407 | switch (GET_CODE (cc_status.value2)) |
3408 | { | |
996a5f59 | 3409 | case ASHIFT: case ASHIFTRT: case LSHIFTRT: |
79e68feb | 3410 | case ROTATE: case ROTATERT: |
a126dc3a RH |
3411 | /* These instructions always clear the overflow bit, and set |
3412 | the carry to the bit shifted out. */ | |
3413 | /* ??? We don't currently have a way to signal carry not valid, | |
3414 | nor do we check for it in the branch insns. */ | |
3415 | CC_STATUS_INIT; | |
3416 | break; | |
3417 | ||
3418 | case PLUS: case MINUS: case MULT: | |
3419 | case DIV: case UDIV: case MOD: case UMOD: case NEG: | |
79e68feb RS |
3420 | if (GET_MODE (cc_status.value2) != VOIDmode) |
3421 | cc_status.flags |= CC_NO_OVERFLOW; | |
3422 | break; | |
3423 | case ZERO_EXTEND: | |
3424 | /* (SET r1 (ZERO_EXTEND r2)) on this machine | |
3425 | ends with a move insn moving r2 in r2's mode. | |
3426 | Thus, the cc's are set for r2. | |
7a1929e1 | 3427 | This can set N bit spuriously. */ |
79e68feb | 3428 | cc_status.flags |= CC_NOT_NEGATIVE; |
1d8eaa6b AS |
3429 | |
3430 | default: | |
3431 | break; | |
79e68feb RS |
3432 | } |
3433 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG | |
3434 | && cc_status.value2 | |
3435 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
3436 | cc_status.value2 = 0; | |
3437 | if (((cc_status.value1 && FP_REG_P (cc_status.value1)) | |
1a8965c4 | 3438 | || (cc_status.value2 && FP_REG_P (cc_status.value2)))) |
79e68feb RS |
3439 | cc_status.flags = CC_IN_68881; |
3440 | } | |
3441 | \f | |
5505f548 | 3442 | const char * |
8a4a2253 | 3443 | output_move_const_double (rtx *operands) |
79e68feb | 3444 | { |
1a8965c4 | 3445 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3446 | |
1a8965c4 | 3447 | if (code != 0) |
79e68feb | 3448 | { |
1a8965c4 | 3449 | static char buf[40]; |
79e68feb | 3450 | |
3b4b85c9 | 3451 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3452 | return buf; |
79e68feb | 3453 | } |
1a8965c4 | 3454 | return "fmove%.d %1,%0"; |
79e68feb RS |
3455 | } |
3456 | ||
5505f548 | 3457 | const char * |
8a4a2253 | 3458 | output_move_const_single (rtx *operands) |
79e68feb | 3459 | { |
1a8965c4 | 3460 | int code = standard_68881_constant_p (operands[1]); |
79e68feb | 3461 | |
1a8965c4 | 3462 | if (code != 0) |
79e68feb | 3463 | { |
1a8965c4 | 3464 | static char buf[40]; |
79e68feb | 3465 | |
3b4b85c9 | 3466 | sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); |
1a8965c4 | 3467 | return buf; |
79e68feb | 3468 | } |
1a8965c4 | 3469 | return "fmove%.s %f1,%0"; |
79e68feb RS |
3470 | } |
3471 | ||
3472 | /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get | |
3473 | from the "fmovecr" instruction. | |
3474 | The value, anded with 0xff, gives the code to use in fmovecr | |
3475 | to get the desired constant. */ | |
3476 | ||
7a1929e1 | 3477 | /* This code has been fixed for cross-compilation. */ |
c1cfb2ae RS |
3478 | |
3479 | static int inited_68881_table = 0; | |
3480 | ||
5505f548 | 3481 | static const char *const strings_68881[7] = { |
c1cfb2ae RS |
3482 | "0.0", |
3483 | "1.0", | |
3484 | "10.0", | |
3485 | "100.0", | |
3486 | "10000.0", | |
3487 | "1e8", | |
3488 | "1e16" | |
a0a7fbc9 | 3489 | }; |
c1cfb2ae | 3490 | |
8b60264b | 3491 | static const int codes_68881[7] = { |
c1cfb2ae RS |
3492 | 0x0f, |
3493 | 0x32, | |
3494 | 0x33, | |
3495 | 0x34, | |
3496 | 0x35, | |
3497 | 0x36, | |
3498 | 0x37 | |
a0a7fbc9 | 3499 | }; |
c1cfb2ae RS |
3500 | |
3501 | REAL_VALUE_TYPE values_68881[7]; | |
3502 | ||
3503 | /* Set up values_68881 array by converting the decimal values | |
7a1929e1 | 3504 | strings_68881 to binary. */ |
c1cfb2ae RS |
3505 | |
3506 | void | |
8a4a2253 | 3507 | init_68881_table (void) |
c1cfb2ae RS |
3508 | { |
3509 | int i; | |
3510 | REAL_VALUE_TYPE r; | |
3511 | enum machine_mode mode; | |
3512 | ||
16d82c3c | 3513 | mode = SFmode; |
c1cfb2ae RS |
3514 | for (i = 0; i < 7; i++) |
3515 | { | |
3516 | if (i == 6) | |
16d82c3c | 3517 | mode = DFmode; |
c1cfb2ae RS |
3518 | r = REAL_VALUE_ATOF (strings_68881[i], mode); |
3519 | values_68881[i] = r; | |
3520 | } | |
3521 | inited_68881_table = 1; | |
3522 | } | |
79e68feb RS |
3523 | |
3524 | int | |
8a4a2253 | 3525 | standard_68881_constant_p (rtx x) |
79e68feb | 3526 | { |
c1cfb2ae RS |
3527 | REAL_VALUE_TYPE r; |
3528 | int i; | |
79e68feb | 3529 | |
e18db50d | 3530 | /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be |
7a1929e1 | 3531 | used at all on those chips. */ |
9cf106c8 | 3532 | if (TUNE_68040_60) |
79e68feb RS |
3533 | return 0; |
3534 | ||
c1cfb2ae RS |
3535 | if (! inited_68881_table) |
3536 | init_68881_table (); | |
3537 | ||
3538 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3539 | ||
64c0b414 AS |
3540 | /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 |
3541 | is rejected. */ | |
c1cfb2ae RS |
3542 | for (i = 0; i < 6; i++) |
3543 | { | |
64c0b414 | 3544 | if (REAL_VALUES_IDENTICAL (r, values_68881[i])) |
c1cfb2ae RS |
3545 | return (codes_68881[i]); |
3546 | } | |
3547 | ||
79e68feb RS |
3548 | if (GET_MODE (x) == SFmode) |
3549 | return 0; | |
c1cfb2ae RS |
3550 | |
3551 | if (REAL_VALUES_EQUAL (r, values_68881[6])) | |
3552 | return (codes_68881[6]); | |
3553 | ||
79e68feb RS |
3554 | /* larger powers of ten in the constants ram are not used |
3555 | because they are not equal to a `double' C constant. */ | |
3556 | return 0; | |
3557 | } | |
3558 | ||
3559 | /* If X is a floating-point constant, return the logarithm of X base 2, | |
3560 | or 0 if X is not a power of 2. */ | |
3561 | ||
3562 | int | |
8a4a2253 | 3563 | floating_exact_log2 (rtx x) |
79e68feb | 3564 | { |
c1cfb2ae | 3565 | REAL_VALUE_TYPE r, r1; |
eaff3bf8 | 3566 | int exp; |
79e68feb | 3567 | |
c1cfb2ae | 3568 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
79e68feb | 3569 | |
eaff3bf8 | 3570 | if (REAL_VALUES_LESS (r, dconst1)) |
79e68feb RS |
3571 | return 0; |
3572 | ||
eaff3bf8 RH |
3573 | exp = real_exponent (&r); |
3574 | real_2expN (&r1, exp); | |
3575 | if (REAL_VALUES_EQUAL (r1, r)) | |
3576 | return exp; | |
3577 | ||
79e68feb RS |
3578 | return 0; |
3579 | } | |
3580 | \f | |
79e68feb RS |
3581 | /* A C compound statement to output to stdio stream STREAM the |
3582 | assembler syntax for an instruction operand X. X is an RTL | |
3583 | expression. | |
3584 | ||
3585 | CODE is a value that can be used to specify one of several ways | |
3586 | of printing the operand. It is used when identical operands | |
3587 | must be printed differently depending on the context. CODE | |
3588 | comes from the `%' specification that was used to request | |
3589 | printing of the operand. If the specification was just `%DIGIT' | |
3590 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3591 | is the ASCII code for LTR. | |
3592 | ||
3593 | If X is a register, this macro should print the register's name. | |
3594 | The names can be found in an array `reg_names' whose type is | |
3595 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3596 | ||
3597 | When the machine description has a specification `%PUNCT' (a `%' | |
3598 | followed by a punctuation character), this macro is called with | |
3599 | a null pointer for X and the punctuation character for CODE. | |
3600 | ||
3601 | The m68k specific codes are: | |
3602 | ||
3603 | '.' for dot needed in Motorola-style opcode names. | |
3604 | '-' for an operand pushing on the stack: | |
3605 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
3606 | '+' for an operand pushing on the stack: | |
3607 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
3608 | '@' for a reference to the top word on the stack: | |
3609 | sp@, (sp) or (%sp) depending on the style of syntax. | |
3610 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
5ee084df | 3611 | but & in SGS syntax). |
79e68feb RS |
3612 | '!' for the cc register (used in an `and to cc' insn). |
3613 | '$' for the letter `s' in an op code, but only on the 68040. | |
3614 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 3615 | '/' for register prefix needed by longlong.h. |
a40ed0f3 | 3616 | '?' for m68k_library_id_string |
79e68feb RS |
3617 | |
3618 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
3619 | 'd' to force memory addressing to be absolute, not relative. | |
3620 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
79e68feb RS |
3621 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), |
3622 | or print pair of registers as rx:ry. | |
29ca003a RS |
3623 | 'p' print an address with @PLTPC attached, but only if the operand |
3624 | is not locally-bound. */ | |
79e68feb RS |
3625 | |
3626 | void | |
8a4a2253 | 3627 | print_operand (FILE *file, rtx op, int letter) |
79e68feb | 3628 | { |
79e68feb RS |
3629 | if (letter == '.') |
3630 | { | |
e6d98cb0 BI |
3631 | if (MOTOROLA) |
3632 | fprintf (file, "."); | |
79e68feb RS |
3633 | } |
3634 | else if (letter == '#') | |
e6d98cb0 | 3635 | asm_fprintf (file, "%I"); |
79e68feb | 3636 | else if (letter == '-') |
e6d98cb0 | 3637 | asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); |
79e68feb | 3638 | else if (letter == '+') |
e6d98cb0 | 3639 | asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); |
79e68feb | 3640 | else if (letter == '@') |
e6d98cb0 | 3641 | asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); |
79e68feb | 3642 | else if (letter == '!') |
e6d98cb0 | 3643 | asm_fprintf (file, "%Rfpcr"); |
79e68feb RS |
3644 | else if (letter == '$') |
3645 | { | |
b101567e | 3646 | if (TARGET_68040) |
e6d98cb0 | 3647 | fprintf (file, "s"); |
79e68feb RS |
3648 | } |
3649 | else if (letter == '&') | |
3650 | { | |
b101567e | 3651 | if (TARGET_68040) |
e6d98cb0 | 3652 | fprintf (file, "d"); |
79e68feb | 3653 | } |
2ac5f14a | 3654 | else if (letter == '/') |
e6d98cb0 | 3655 | asm_fprintf (file, "%R"); |
a40ed0f3 KH |
3656 | else if (letter == '?') |
3657 | asm_fprintf (file, m68k_library_id_string); | |
29ca003a | 3658 | else if (letter == 'p') |
2c8ec431 | 3659 | { |
29ca003a RS |
3660 | output_addr_const (file, op); |
3661 | if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) | |
3662 | fprintf (file, "@PLTPC"); | |
2c8ec431 | 3663 | } |
79e68feb RS |
3664 | else if (GET_CODE (op) == REG) |
3665 | { | |
1a8965c4 AS |
3666 | if (letter == 'R') |
3667 | /* Print out the second register name of a register pair. | |
3668 | I.e., R (6) => 7. */ | |
01bbf777 | 3669 | fputs (M68K_REGNAME(REGNO (op) + 1), file); |
79e68feb | 3670 | else |
01bbf777 | 3671 | fputs (M68K_REGNAME(REGNO (op)), file); |
79e68feb RS |
3672 | } |
3673 | else if (GET_CODE (op) == MEM) | |
3674 | { | |
3675 | output_address (XEXP (op, 0)); | |
3676 | if (letter == 'd' && ! TARGET_68020 | |
3677 | && CONSTANT_ADDRESS_P (XEXP (op, 0)) | |
3678 | && !(GET_CODE (XEXP (op, 0)) == CONST_INT | |
3679 | && INTVAL (XEXP (op, 0)) < 0x8000 | |
3680 | && INTVAL (XEXP (op, 0)) >= -0x8000)) | |
e6d98cb0 | 3681 | fprintf (file, MOTOROLA ? ".l" : ":l"); |
79e68feb | 3682 | } |
79e68feb RS |
3683 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) |
3684 | { | |
c1cfb2ae RS |
3685 | REAL_VALUE_TYPE r; |
3686 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3687 | ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); | |
3688 | } | |
3689 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) | |
3690 | { | |
3691 | REAL_VALUE_TYPE r; | |
3692 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3693 | ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); | |
79e68feb | 3694 | } |
e2c0a924 | 3695 | else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) |
79e68feb | 3696 | { |
c1cfb2ae RS |
3697 | REAL_VALUE_TYPE r; |
3698 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
3699 | ASM_OUTPUT_DOUBLE_OPERAND (file, r); | |
79e68feb RS |
3700 | } |
3701 | else | |
3702 | { | |
2c8ec431 DL |
3703 | /* Use `print_operand_address' instead of `output_addr_const' |
3704 | to ensure that we print relevant PIC stuff. */ | |
1f85a612 | 3705 | asm_fprintf (file, "%I"); |
2c8ec431 DL |
3706 | if (TARGET_PCREL |
3707 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) | |
3708 | print_operand_address (file, op); | |
3709 | else | |
3710 | output_addr_const (file, op); | |
79e68feb RS |
3711 | } |
3712 | } | |
3713 | ||
3714 | \f | |
3715 | /* A C compound statement to output to stdio stream STREAM the | |
3716 | assembler syntax for an instruction operand that is a memory | |
3717 | reference whose address is ADDR. ADDR is an RTL expression. | |
3718 | ||
3719 | Note that this contains a kludge that knows that the only reason | |
3720 | we have an address (plus (label_ref...) (reg...)) when not generating | |
3721 | PIC code is in the insn before a tablejump, and we know that m68k.md | |
3722 | generates a label LInnn: on such an insn. | |
3723 | ||
3724 | It is possible for PIC to generate a (plus (label_ref...) (reg...)) | |
3725 | and we handle that just like we would a (plus (symbol_ref...) (reg...)). | |
3726 | ||
3727 | Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" | |
3728 | fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results | |
3729 | we want. This difference can be accommodated by using an assembler | |
3730 | define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other | |
3731 | string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END | |
ad7c12b2 | 3732 | macro. See m68k/sgs.h for an example; for versions without the bug. |
f4a6e73b RK |
3733 | Some assemblers refuse all the above solutions. The workaround is to |
3734 | emit "K(pc,d0.l*2)" with K being a small constant known to give the | |
a0ab749a | 3735 | right behavior. |
79e68feb RS |
3736 | |
3737 | They also do not like things like "pea 1.w", so we simple leave off | |
3738 | the .w on small constants. | |
3739 | ||
3740 | This routine is responsible for distinguishing between -fpic and -fPIC | |
3741 | style relocations in an address. When generating -fpic code the | |
112cdef5 KH |
3742 | offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating |
3743 | -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ | |
79e68feb RS |
3744 | |
3745 | void | |
8a4a2253 | 3746 | print_operand_address (FILE *file, rtx addr) |
79e68feb | 3747 | { |
fc2241eb RS |
3748 | struct m68k_address address; |
3749 | ||
3750 | if (!m68k_decompose_address (QImode, addr, true, &address)) | |
3751 | gcc_unreachable (); | |
3752 | ||
3753 | if (address.code == PRE_DEC) | |
3754 | fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", | |
3755 | M68K_REGNAME (REGNO (address.base))); | |
3756 | else if (address.code == POST_INC) | |
3757 | fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", | |
3758 | M68K_REGNAME (REGNO (address.base))); | |
3759 | else if (!address.base && !address.index) | |
3760 | { | |
3761 | /* A constant address. */ | |
3762 | gcc_assert (address.offset == addr); | |
3763 | if (GET_CODE (addr) == CONST_INT) | |
3764 | { | |
3765 | /* (xxx).w or (xxx).l. */ | |
3766 | if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) | |
3767 | fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); | |
a0a7fbc9 | 3768 | else |
fc2241eb | 3769 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); |
a0a7fbc9 | 3770 | } |
fc2241eb | 3771 | else if (TARGET_PCREL) |
a0a7fbc9 | 3772 | { |
fc2241eb RS |
3773 | /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ |
3774 | fputc ('(', file); | |
3775 | output_addr_const (file, addr); | |
3776 | asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); | |
a0a7fbc9 | 3777 | } |
fc2241eb | 3778 | else |
a0a7fbc9 | 3779 | { |
fc2241eb RS |
3780 | /* (xxx).l. We need a special case for SYMBOL_REF if the symbol |
3781 | name ends in `.<letter>', as the last 2 characters can be | |
3782 | mistaken as a size suffix. Put the name in parentheses. */ | |
3783 | if (GET_CODE (addr) == SYMBOL_REF | |
3784 | && strlen (XSTR (addr, 0)) > 2 | |
3785 | && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') | |
a0a7fbc9 | 3786 | { |
fc2241eb RS |
3787 | putc ('(', file); |
3788 | output_addr_const (file, addr); | |
3789 | putc (')', file); | |
a0a7fbc9 AS |
3790 | } |
3791 | else | |
fc2241eb | 3792 | output_addr_const (file, addr); |
a0a7fbc9 | 3793 | } |
fc2241eb RS |
3794 | } |
3795 | else | |
3796 | { | |
3797 | int labelno; | |
3798 | ||
3799 | /* If ADDR is a (d8,pc,Xn) address, this is the number of the | |
44c7bd63 | 3800 | label being accessed, otherwise it is -1. */ |
fc2241eb RS |
3801 | labelno = (address.offset |
3802 | && !address.base | |
3803 | && GET_CODE (address.offset) == LABEL_REF | |
3804 | ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) | |
3805 | : -1); | |
3806 | if (MOTOROLA) | |
a0a7fbc9 | 3807 | { |
fc2241eb RS |
3808 | /* Print the "offset(base" component. */ |
3809 | if (labelno >= 0) | |
3810 | asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,", labelno, labelno); | |
3811 | else | |
a0a7fbc9 | 3812 | { |
fc2241eb | 3813 | if (address.offset) |
a0a7fbc9 | 3814 | { |
fc2241eb RS |
3815 | output_addr_const (file, address.offset); |
3816 | if (flag_pic && address.base == pic_offset_table_rtx) | |
a0a7fbc9 AS |
3817 | { |
3818 | fprintf (file, "@GOT"); | |
fc2241eb | 3819 | if (flag_pic == 1 && TARGET_68020) |
a0a7fbc9 AS |
3820 | fprintf (file, ".w"); |
3821 | } | |
3822 | } | |
fc2241eb RS |
3823 | putc ('(', file); |
3824 | if (address.base) | |
3825 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
a0a7fbc9 | 3826 | } |
fc2241eb RS |
3827 | /* Print the ",index" component, if any. */ |
3828 | if (address.index) | |
a0a7fbc9 | 3829 | { |
fc2241eb RS |
3830 | if (address.base) |
3831 | putc (',', file); | |
3832 | fprintf (file, "%s.%c", | |
3833 | M68K_REGNAME (REGNO (address.index)), | |
3834 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3835 | if (address.scale != 1) | |
3836 | fprintf (file, "*%d", address.scale); | |
a0a7fbc9 | 3837 | } |
a0a7fbc9 | 3838 | putc (')', file); |
a0a7fbc9 | 3839 | } |
fc2241eb | 3840 | else /* !MOTOROLA */ |
a0a7fbc9 | 3841 | { |
fc2241eb RS |
3842 | if (!address.offset && !address.index) |
3843 | fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); | |
a0a7fbc9 | 3844 | else |
a0a7fbc9 | 3845 | { |
fc2241eb RS |
3846 | /* Print the "base@(offset" component. */ |
3847 | if (labelno >= 0) | |
3848 | asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b", labelno, labelno); | |
3849 | else | |
3850 | { | |
3851 | if (address.base) | |
3852 | fputs (M68K_REGNAME (REGNO (address.base)), file); | |
3853 | fprintf (file, "@("); | |
3854 | if (address.offset) | |
3855 | { | |
3856 | output_addr_const (file, address.offset); | |
3857 | if (address.base == pic_offset_table_rtx && TARGET_68020) | |
3858 | switch (flag_pic) | |
3859 | { | |
3860 | case 1: | |
3861 | fprintf (file, ":w"); break; | |
3862 | case 2: | |
3863 | fprintf (file, ":l"); break; | |
3864 | default: | |
3865 | break; | |
3866 | } | |
3867 | } | |
3868 | } | |
3869 | /* Print the ",index" component, if any. */ | |
3870 | if (address.index) | |
3871 | { | |
3872 | fprintf (file, ",%s:%c", | |
3873 | M68K_REGNAME (REGNO (address.index)), | |
3874 | GET_MODE (address.index) == HImode ? 'w' : 'l'); | |
3875 | if (address.scale != 1) | |
3876 | fprintf (file, ":%d", address.scale); | |
3877 | } | |
a0a7fbc9 AS |
3878 | putc (')', file); |
3879 | } | |
a0a7fbc9 | 3880 | } |
79e68feb RS |
3881 | } |
3882 | } | |
af13f02d JW |
3883 | \f |
3884 | /* Check for cases where a clr insns can be omitted from code using | |
3885 | strict_low_part sets. For example, the second clrl here is not needed: | |
3886 | clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... | |
3887 | ||
3888 | MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear | |
3889 | insn we are checking for redundancy. TARGET is the register set by the | |
3890 | clear insn. */ | |
3891 | ||
8a4a2253 BI |
3892 | bool |
3893 | strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, | |
3894 | rtx target) | |
af13f02d JW |
3895 | { |
3896 | rtx p; | |
3897 | ||
3898 | p = prev_nonnote_insn (first_insn); | |
3899 | ||
3900 | while (p) | |
3901 | { | |
3902 | /* If it isn't an insn, then give up. */ | |
3903 | if (GET_CODE (p) != INSN) | |
8a4a2253 | 3904 | return false; |
af13f02d JW |
3905 | |
3906 | if (reg_set_p (target, p)) | |
3907 | { | |
3908 | rtx set = single_set (p); | |
3909 | rtx dest; | |
3910 | ||
3911 | /* If it isn't an easy to recognize insn, then give up. */ | |
3912 | if (! set) | |
8a4a2253 | 3913 | return false; |
af13f02d JW |
3914 | |
3915 | dest = SET_DEST (set); | |
3916 | ||
3917 | /* If this sets the entire target register to zero, then our | |
3918 | first_insn is redundant. */ | |
3919 | if (rtx_equal_p (dest, target) | |
3920 | && SET_SRC (set) == const0_rtx) | |
8a4a2253 | 3921 | return true; |
af13f02d JW |
3922 | else if (GET_CODE (dest) == STRICT_LOW_PART |
3923 | && GET_CODE (XEXP (dest, 0)) == REG | |
3924 | && REGNO (XEXP (dest, 0)) == REGNO (target) | |
3925 | && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) | |
3926 | <= GET_MODE_SIZE (mode))) | |
3927 | /* This is a strict low part set which modifies less than | |
3928 | we are using, so it is safe. */ | |
3929 | ; | |
3930 | else | |
8a4a2253 | 3931 | return false; |
af13f02d JW |
3932 | } |
3933 | ||
3934 | p = prev_nonnote_insn (p); | |
af13f02d JW |
3935 | } |
3936 | ||
8a4a2253 | 3937 | return false; |
af13f02d | 3938 | } |
67cd4f83 | 3939 | |
2c8ec431 DL |
3940 | /* Operand predicates for implementing asymmetric pc-relative addressing |
3941 | on m68k. The m68k supports pc-relative addressing (mode 7, register 2) | |
dab66575 | 3942 | when used as a source operand, but not as a destination operand. |
2c8ec431 DL |
3943 | |
3944 | We model this by restricting the meaning of the basic predicates | |
3945 | (general_operand, memory_operand, etc) to forbid the use of this | |
3946 | addressing mode, and then define the following predicates that permit | |
3947 | this addressing mode. These predicates can then be used for the | |
3948 | source operands of the appropriate instructions. | |
3949 | ||
3950 | n.b. While it is theoretically possible to change all machine patterns | |
3951 | to use this addressing more where permitted by the architecture, | |
3952 | it has only been implemented for "common" cases: SImode, HImode, and | |
3953 | QImode operands, and only for the principle operations that would | |
3954 | require this addressing mode: data movement and simple integer operations. | |
3955 | ||
3956 | In parallel with these new predicates, two new constraint letters | |
3957 | were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. | |
3958 | 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. | |
3959 | In the pcrel case 's' is only valid in combination with 'a' registers. | |
3960 | See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding | |
3961 | of how these constraints are used. | |
3962 | ||
3963 | The use of these predicates is strictly optional, though patterns that | |
3964 | don't will cause an extra reload register to be allocated where one | |
3965 | was not necessary: | |
3966 | ||
3967 | lea (abc:w,%pc),%a0 ; need to reload address | |
3968 | moveq &1,%d1 ; since write to pc-relative space | |
3969 | movel %d1,%a0@ ; is not allowed | |
3970 | ... | |
3971 | lea (abc:w,%pc),%a1 ; no need to reload address here | |
3972 | movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok | |
3973 | ||
3974 | For more info, consult tiemann@cygnus.com. | |
3975 | ||
3976 | ||
3977 | All of the ugliness with predicates and constraints is due to the | |
3978 | simple fact that the m68k does not allow a pc-relative addressing | |
3979 | mode as a destination. gcc does not distinguish between source and | |
3980 | destination addresses. Hence, if we claim that pc-relative address | |
3981 | modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we | |
3982 | end up with invalid code. To get around this problem, we left | |
3983 | pc-relative modes as invalid addresses, and then added special | |
3984 | predicates and constraints to accept them. | |
3985 | ||
3986 | A cleaner way to handle this is to modify gcc to distinguish | |
3987 | between source and destination addresses. We can then say that | |
3988 | pc-relative is a valid source address but not a valid destination | |
3989 | address, and hopefully avoid a lot of the predicate and constraint | |
3990 | hackery. Unfortunately, this would be a pretty big change. It would | |
3991 | be a useful change for a number of ports, but there aren't any current | |
3992 | plans to undertake this. | |
3993 | ||
3994 | ***************************************************************************/ | |
3995 | ||
3996 | ||
5505f548 | 3997 | const char * |
8a4a2253 | 3998 | output_andsi3 (rtx *operands) |
29ae8a3c RK |
3999 | { |
4000 | int logval; | |
4001 | if (GET_CODE (operands[2]) == CONST_INT | |
25c99d8f | 4002 | && (INTVAL (operands[2]) | 0xffff) == -1 |
29ae8a3c RK |
4003 | && (DATA_REG_P (operands[0]) |
4004 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4005 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4006 | { |
4007 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4008 | operands[0] = adjust_address (operands[0], HImode, 2); |
1d8eaa6b | 4009 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
29ae8a3c RK |
4010 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4011 | CC_STATUS_INIT; | |
4012 | if (operands[2] == const0_rtx) | |
4013 | return "clr%.w %0"; | |
4014 | return "and%.w %2,%0"; | |
4015 | } | |
4016 | if (GET_CODE (operands[2]) == CONST_INT | |
4017 | && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 | |
4018 | && (DATA_REG_P (operands[0]) | |
4019 | || offsettable_memref_p (operands[0]))) | |
4020 | { | |
4021 | if (DATA_REG_P (operands[0])) | |
a0a7fbc9 | 4022 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4023 | else |
4024 | { | |
b72f00af | 4025 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4026 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4027 | } |
4028 | /* This does not set condition codes in a standard way. */ | |
4029 | CC_STATUS_INIT; | |
4030 | return "bclr %1,%0"; | |
4031 | } | |
4032 | return "and%.l %2,%0"; | |
4033 | } | |
4034 | ||
5505f548 | 4035 | const char * |
8a4a2253 | 4036 | output_iorsi3 (rtx *operands) |
29ae8a3c RK |
4037 | { |
4038 | register int logval; | |
4039 | if (GET_CODE (operands[2]) == CONST_INT | |
4040 | && INTVAL (operands[2]) >> 16 == 0 | |
4041 | && (DATA_REG_P (operands[0]) | |
4042 | || offsettable_memref_p (operands[0])) | |
9425fb04 | 4043 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4044 | { |
4045 | if (GET_CODE (operands[0]) != REG) | |
b72f00af | 4046 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4047 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4048 | CC_STATUS_INIT; | |
4049 | if (INTVAL (operands[2]) == 0xffff) | |
4050 | return "mov%.w %2,%0"; | |
4051 | return "or%.w %2,%0"; | |
4052 | } | |
4053 | if (GET_CODE (operands[2]) == CONST_INT | |
4054 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
4055 | && (DATA_REG_P (operands[0]) | |
4056 | || offsettable_memref_p (operands[0]))) | |
4057 | { | |
4058 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4059 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4060 | else |
4061 | { | |
b72f00af | 4062 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4063 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4064 | } |
4065 | CC_STATUS_INIT; | |
4066 | return "bset %1,%0"; | |
4067 | } | |
4068 | return "or%.l %2,%0"; | |
4069 | } | |
4070 | ||
5505f548 | 4071 | const char * |
8a4a2253 | 4072 | output_xorsi3 (rtx *operands) |
29ae8a3c RK |
4073 | { |
4074 | register int logval; | |
4075 | if (GET_CODE (operands[2]) == CONST_INT | |
4076 | && INTVAL (operands[2]) >> 16 == 0 | |
4077 | && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) | |
9425fb04 | 4078 | && !TARGET_COLDFIRE) |
29ae8a3c RK |
4079 | { |
4080 | if (! DATA_REG_P (operands[0])) | |
b72f00af | 4081 | operands[0] = adjust_address (operands[0], HImode, 2); |
29ae8a3c RK |
4082 | /* Do not delete a following tstl %0 insn; that would be incorrect. */ |
4083 | CC_STATUS_INIT; | |
4084 | if (INTVAL (operands[2]) == 0xffff) | |
4085 | return "not%.w %0"; | |
4086 | return "eor%.w %2,%0"; | |
4087 | } | |
4088 | if (GET_CODE (operands[2]) == CONST_INT | |
4089 | && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 | |
4090 | && (DATA_REG_P (operands[0]) | |
4091 | || offsettable_memref_p (operands[0]))) | |
4092 | { | |
4093 | if (DATA_REG_P (operands[0])) | |
b72f00af | 4094 | operands[1] = GEN_INT (logval); |
29ae8a3c RK |
4095 | else |
4096 | { | |
b72f00af | 4097 | operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); |
1d8eaa6b | 4098 | operands[1] = GEN_INT (logval % 8); |
29ae8a3c RK |
4099 | } |
4100 | CC_STATUS_INIT; | |
4101 | return "bchg %1,%0"; | |
4102 | } | |
4103 | return "eor%.l %2,%0"; | |
4104 | } | |
7c262518 | 4105 | |
29ca003a RS |
4106 | /* Return the instruction that should be used for a call to address X, |
4107 | which is known to be in operand 0. */ | |
4108 | ||
4109 | const char * | |
4110 | output_call (rtx x) | |
4111 | { | |
4112 | if (symbolic_operand (x, VOIDmode)) | |
4113 | return m68k_symbolic_call; | |
4114 | else | |
4115 | return "jsr %a0"; | |
4116 | } | |
4117 | ||
f7e70894 RS |
4118 | /* Likewise sibling calls. */ |
4119 | ||
4120 | const char * | |
4121 | output_sibcall (rtx x) | |
4122 | { | |
4123 | if (symbolic_operand (x, VOIDmode)) | |
4124 | return m68k_symbolic_jump; | |
4125 | else | |
4126 | return "jmp %a0"; | |
4127 | } | |
4128 | ||
45849738 BI |
4129 | #ifdef M68K_TARGET_COFF |
4130 | ||
4131 | /* Output assembly to switch to section NAME with attribute FLAGS. */ | |
4132 | ||
4133 | static void | |
c18a5b6c MM |
4134 | m68k_coff_asm_named_section (const char *name, unsigned int flags, |
4135 | tree decl ATTRIBUTE_UNUSED) | |
45849738 BI |
4136 | { |
4137 | char flagchar; | |
4138 | ||
4139 | if (flags & SECTION_WRITE) | |
4140 | flagchar = 'd'; | |
4141 | else | |
4142 | flagchar = 'x'; | |
4143 | ||
4144 | fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); | |
4145 | } | |
4146 | ||
4147 | #endif /* M68K_TARGET_COFF */ | |
4148 | ||
c590b625 | 4149 | static void |
8a4a2253 | 4150 | m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
4ab870f5 | 4151 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
8a4a2253 | 4152 | tree function) |
483ab821 | 4153 | { |
4ab870f5 RS |
4154 | rtx this_slot, offset, addr, mem, insn; |
4155 | ||
4156 | /* Pretend to be a post-reload pass while generating rtl. */ | |
4ab870f5 | 4157 | reload_completed = 1; |
4ab870f5 RS |
4158 | |
4159 | /* The "this" pointer is stored at 4(%sp). */ | |
4160 | this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4)); | |
4161 | ||
4162 | /* Add DELTA to THIS. */ | |
4163 | if (delta != 0) | |
5050d266 | 4164 | { |
4ab870f5 RS |
4165 | /* Make the offset a legitimate operand for memory addition. */ |
4166 | offset = GEN_INT (delta); | |
4167 | if ((delta < -8 || delta > 8) | |
4168 | && (TARGET_COLDFIRE || USE_MOVQ (delta))) | |
4169 | { | |
4170 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); | |
4171 | offset = gen_rtx_REG (Pmode, D0_REG); | |
4172 | } | |
4173 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4174 | copy_rtx (this_slot), offset)); | |
5050d266 | 4175 | } |
c590b625 | 4176 | |
4ab870f5 RS |
4177 | /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ |
4178 | if (vcall_offset != 0) | |
4179 | { | |
4180 | /* Set the static chain register to *THIS. */ | |
4181 | emit_move_insn (static_chain_rtx, this_slot); | |
4182 | emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx)); | |
4183 | ||
4184 | /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ | |
4185 | addr = plus_constant (static_chain_rtx, vcall_offset); | |
4186 | if (!m68k_legitimate_address_p (Pmode, addr, true)) | |
4187 | { | |
4188 | emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr)); | |
4189 | addr = static_chain_rtx; | |
4190 | } | |
c590b625 | 4191 | |
4ab870f5 RS |
4192 | /* Load the offset into %d0 and add it to THIS. */ |
4193 | emit_move_insn (gen_rtx_REG (Pmode, D0_REG), | |
4194 | gen_rtx_MEM (Pmode, addr)); | |
4195 | emit_insn (gen_add3_insn (copy_rtx (this_slot), | |
4196 | copy_rtx (this_slot), | |
4197 | gen_rtx_REG (Pmode, D0_REG))); | |
4198 | } | |
29ca003a | 4199 | |
4ab870f5 RS |
4200 | /* Jump to the target function. Use a sibcall if direct jumps are |
4201 | allowed, otherwise load the address into a register first. */ | |
4202 | mem = DECL_RTL (function); | |
4203 | if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) | |
4204 | { | |
4205 | gcc_assert (flag_pic); | |
c590b625 | 4206 | |
4ab870f5 RS |
4207 | if (!TARGET_SEP_DATA) |
4208 | { | |
4209 | /* Use the static chain register as a temporary (call-clobbered) | |
4210 | GOT pointer for this function. We can use the static chain | |
4211 | register because it isn't live on entry to the thunk. */ | |
6fb5fa3c | 4212 | SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); |
4ab870f5 RS |
4213 | emit_insn (gen_load_got (pic_offset_table_rtx)); |
4214 | } | |
4215 | legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx); | |
4216 | mem = replace_equiv_address (mem, static_chain_rtx); | |
4217 | } | |
4218 | insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); | |
4219 | SIBLING_CALL_P (insn) = 1; | |
4220 | ||
4221 | /* Run just enough of rest_of_compilation. */ | |
4222 | insn = get_insns (); | |
4223 | split_all_insns_noflow (); | |
4224 | final_start_function (insn, file, 1); | |
4225 | final (insn, file, 1); | |
4226 | final_end_function (); | |
4227 | ||
4228 | /* Clean up the vars set above. */ | |
4229 | reload_completed = 0; | |
4ab870f5 RS |
4230 | |
4231 | /* Restore the original PIC register. */ | |
4232 | if (flag_pic) | |
6fb5fa3c | 4233 | SET_REGNO (pic_offset_table_rtx, PIC_REG); |
483ab821 | 4234 | } |
8636be86 KH |
4235 | |
4236 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ | |
4237 | ||
4238 | static rtx | |
4239 | m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
4240 | int incoming ATTRIBUTE_UNUSED) | |
4241 | { | |
4242 | return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); | |
4243 | } | |
cfca21cb PB |
4244 | |
4245 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ | |
4246 | int | |
4247 | m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
4248 | unsigned int new_reg) | |
4249 | { | |
4250 | ||
4251 | /* Interrupt functions can only use registers that have already been | |
4252 | saved by the prologue, even if they would normally be | |
4253 | call-clobbered. */ | |
4254 | ||
a4242737 KH |
4255 | if ((m68k_get_function_kind (current_function_decl) |
4256 | == m68k_fk_interrupt_handler) | |
6fb5fa3c | 4257 | && !df_regs_ever_live_p (new_reg)) |
cfca21cb PB |
4258 | return 0; |
4259 | ||
4260 | return 1; | |
4261 | } | |
70028b61 | 4262 | |
ffa2596e RS |
4263 | /* Value is true if hard register REGNO can hold a value of machine-mode |
4264 | MODE. On the 68000, we let the cpu registers can hold any mode, but | |
4265 | restrict the 68881 registers to floating-point modes. */ | |
4266 | ||
70028b61 PB |
4267 | bool |
4268 | m68k_regno_mode_ok (int regno, enum machine_mode mode) | |
4269 | { | |
36e04090 | 4270 | if (DATA_REGNO_P (regno)) |
70028b61 | 4271 | { |
a0a7fbc9 AS |
4272 | /* Data Registers, can hold aggregate if fits in. */ |
4273 | if (regno + GET_MODE_SIZE (mode) / 4 <= 8) | |
4274 | return true; | |
70028b61 | 4275 | } |
36e04090 | 4276 | else if (ADDRESS_REGNO_P (regno)) |
70028b61 | 4277 | { |
a0a7fbc9 AS |
4278 | if (regno + GET_MODE_SIZE (mode) / 4 <= 16) |
4279 | return true; | |
70028b61 | 4280 | } |
36e04090 | 4281 | else if (FP_REGNO_P (regno)) |
70028b61 PB |
4282 | { |
4283 | /* FPU registers, hold float or complex float of long double or | |
a0a7fbc9 AS |
4284 | smaller. */ |
4285 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4286 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
dcc21c4c | 4287 | && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) |
a0a7fbc9 | 4288 | return true; |
70028b61 PB |
4289 | } |
4290 | return false; | |
4291 | } | |
dcc21c4c | 4292 | |
ffa2596e RS |
4293 | /* Implement SECONDARY_RELOAD_CLASS. */ |
4294 | ||
4295 | enum reg_class | |
4296 | m68k_secondary_reload_class (enum reg_class rclass, | |
4297 | enum machine_mode mode, rtx x) | |
4298 | { | |
4299 | int regno; | |
4300 | ||
4301 | regno = true_regnum (x); | |
4302 | ||
4303 | /* If one operand of a movqi is an address register, the other | |
4304 | operand must be a general register or constant. Other types | |
4305 | of operand must be reloaded through a data register. */ | |
4306 | if (GET_MODE_SIZE (mode) == 1 | |
4307 | && reg_classes_intersect_p (rclass, ADDR_REGS) | |
4308 | && !(INT_REGNO_P (regno) || CONSTANT_P (x))) | |
4309 | return DATA_REGS; | |
4310 | ||
4311 | /* PC-relative addresses must be loaded into an address register first. */ | |
4312 | if (TARGET_PCREL | |
4313 | && !reg_class_subset_p (rclass, ADDR_REGS) | |
4314 | && symbolic_operand (x, VOIDmode)) | |
4315 | return ADDR_REGS; | |
4316 | ||
4317 | return NO_REGS; | |
4318 | } | |
4319 | ||
4320 | /* Implement PREFERRED_RELOAD_CLASS. */ | |
4321 | ||
4322 | enum reg_class | |
4323 | m68k_preferred_reload_class (rtx x, enum reg_class rclass) | |
4324 | { | |
4325 | enum reg_class secondary_class; | |
4326 | ||
4327 | /* If RCLASS might need a secondary reload, try restricting it to | |
4328 | a class that doesn't. */ | |
4329 | secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); | |
4330 | if (secondary_class != NO_REGS | |
4331 | && reg_class_subset_p (secondary_class, rclass)) | |
4332 | return secondary_class; | |
4333 | ||
4334 | /* Prefer to use moveq for in-range constants. */ | |
4335 | if (GET_CODE (x) == CONST_INT | |
4336 | && reg_class_subset_p (DATA_REGS, rclass) | |
4337 | && IN_RANGE (INTVAL (x), -0x80, 0x7f)) | |
4338 | return DATA_REGS; | |
4339 | ||
4340 | /* ??? Do we really need this now? */ | |
4341 | if (GET_CODE (x) == CONST_DOUBLE | |
4342 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
4343 | { | |
4344 | if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) | |
4345 | return FP_REGS; | |
4346 | ||
4347 | return NO_REGS; | |
4348 | } | |
4349 | ||
4350 | return rclass; | |
4351 | } | |
4352 | ||
dcc21c4c PB |
4353 | /* Return floating point values in a 68881 register. This makes 68881 code |
4354 | a little bit faster. It also makes -msoft-float code incompatible with | |
4355 | hard-float code, so people have to be careful not to mix the two. | |
c0220ea4 | 4356 | For ColdFire it was decided the ABI incompatibility is undesirable. |
dcc21c4c PB |
4357 | If there is need for a hard-float ABI it is probably worth doing it |
4358 | properly and also passing function arguments in FP registers. */ | |
4359 | rtx | |
4360 | m68k_libcall_value (enum machine_mode mode) | |
4361 | { | |
4362 | switch (mode) { | |
4363 | case SFmode: | |
4364 | case DFmode: | |
4365 | case XFmode: | |
4366 | if (TARGET_68881) | |
8d989403 | 4367 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
4368 | break; |
4369 | default: | |
4370 | break; | |
4371 | } | |
8d989403 | 4372 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c PB |
4373 | } |
4374 | ||
4375 | rtx | |
586de218 | 4376 | m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
dcc21c4c PB |
4377 | { |
4378 | enum machine_mode mode; | |
4379 | ||
4380 | mode = TYPE_MODE (valtype); | |
4381 | switch (mode) { | |
4382 | case SFmode: | |
4383 | case DFmode: | |
4384 | case XFmode: | |
4385 | if (TARGET_68881) | |
8d989403 | 4386 | return gen_rtx_REG (mode, FP0_REG); |
dcc21c4c PB |
4387 | break; |
4388 | default: | |
4389 | break; | |
4390 | } | |
4391 | ||
576c9028 KH |
4392 | /* If the function returns a pointer, push that into %a0. */ |
4393 | if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) | |
4394 | /* For compatibility with the large body of existing code which | |
4395 | does not always properly declare external functions returning | |
4396 | pointer types, the m68k/SVR4 convention is to copy the value | |
4397 | returned for pointer functions from a0 to d0 in the function | |
4398 | epilogue, so that callers that have neglected to properly | |
4399 | declare the callee can still find the correct return value in | |
4400 | d0. */ | |
4401 | return gen_rtx_PARALLEL | |
4402 | (mode, | |
4403 | gen_rtvec (2, | |
4404 | gen_rtx_EXPR_LIST (VOIDmode, | |
4405 | gen_rtx_REG (mode, A0_REG), | |
4406 | const0_rtx), | |
4407 | gen_rtx_EXPR_LIST (VOIDmode, | |
4408 | gen_rtx_REG (mode, D0_REG), | |
4409 | const0_rtx))); | |
4410 | else if (POINTER_TYPE_P (valtype)) | |
4411 | return gen_rtx_REG (mode, A0_REG); | |
dcc21c4c | 4412 | else |
576c9028 | 4413 | return gen_rtx_REG (mode, D0_REG); |
dcc21c4c | 4414 | } |
1c445f03 NS |
4415 | |
4416 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
4417 | #if M68K_HONOR_TARGET_STRICT_ALIGNMENT | |
4418 | static bool | |
4419 | m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4420 | { | |
4421 | enum machine_mode mode = TYPE_MODE (type); | |
4422 | ||
4423 | if (mode == BLKmode) | |
4424 | return true; | |
4425 | ||
4426 | /* If TYPE's known alignment is less than the alignment of MODE that | |
4427 | would contain the structure, then return in memory. We need to | |
4428 | do so to maintain the compatibility between code compiled with | |
4429 | -mstrict-align and that compiled with -mno-strict-align. */ | |
4430 | if (AGGREGATE_TYPE_P (type) | |
4431 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) | |
4432 | return true; | |
4433 | ||
4434 | return false; | |
4435 | } | |
4436 | #endif |